diff --git a/projects/Allwinner/linux/linux.aarch64.conf b/projects/Allwinner/linux/linux.aarch64.conf index d313c1b44f..b43117d5c3 100644 --- a/projects/Allwinner/linux/linux.aarch64.conf +++ b/projects/Allwinner/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.4.12 Kernel Configuration +# Linux/arm64 5.5.0 Kernel Configuration # # @@ -22,7 +22,6 @@ CONFIG_THREAD_INFO_IN_TASK=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set -# CONFIG_HEADER_TEST is not set CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" @@ -129,6 +128,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y # end of Scheduler features CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_CC_HAS_INT128=y CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_NUMA_BALANCING=y CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y @@ -254,6 +254,7 @@ CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CSUM=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_SMP=y @@ -288,6 +289,7 @@ CONFIG_ARCH_SUNXI=y # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_RENESAS is not set # CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_S32 is not set # CONFIG_ARCH_SEATTLE is not set # CONFIG_ARCH_STRATIX10 is not set # CONFIG_ARCH_SYNQUACER is not set @@ -321,7 +323,9 @@ CONFIG_ARM64_ERRATUM_1024718=y CONFIG_ARM64_ERRATUM_1418040=y CONFIG_ARM64_ERRATUM_1165522=y CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_ARM64_ERRATUM_1319367=y CONFIG_ARM64_ERRATUM_1463225=y +CONFIG_ARM64_ERRATUM_1542419=y CONFIG_CAVIUM_ERRATUM_22375=y CONFIG_CAVIUM_ERRATUM_23144=y CONFIG_CAVIUM_ERRATUM_23154=y @@ -347,6 +351,7 @@ CONFIG_ARM64_VA_BITS=48 CONFIG_ARM64_PA_BITS_48=y CONFIG_ARM64_PA_BITS=48 # CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SCHED_MC=y # CONFIG_SCHED_SMT is not set CONFIG_NR_CPUS=64 @@ -426,7 +431,6 @@ CONFIG_ARM64_MODULE_PLTS=y # Boot options # CONFIG_CMDLINE="" -# CONFIG_CMDLINE_FORCE is not set CONFIG_EFI_STUB=y CONFIG_EFI=y CONFIG_DMI=y @@ -570,6 +574,7 @@ CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_NEON_BLK=m CONFIG_CRYPTO_CHACHA20_NEON=m +# CONFIG_CRYPTO_POLY1305_NEON is not set # CONFIG_CRYPTO_NHPOLY1305_NEON is not set CONFIG_CRYPTO_AES_ARM64_BS=m @@ -635,7 +640,6 @@ CONFIG_HAVE_COPY_THREAD_TLS=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_COMPAT_OLD_SIGACTION=y -CONFIG_64BIT_TIME=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y @@ -643,7 +647,6 @@ CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y -CONFIG_REFCOUNT_FULL=y CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y CONFIG_ARCH_USE_MEMREMAP_PROT=y # CONFIG_LOCK_EVENT_COUNTS is not set @@ -675,6 +678,7 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_CGROUP_RWSTAT=y CONFIG_BLK_DEV_BSG=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y @@ -753,6 +757,7 @@ CONFIG_COMPACTION=y CONFIG_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_BOUNCE=y CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y @@ -1335,6 +1340,7 @@ CONFIG_FW_LOADER=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_FW_LOADER_USER_HELPER is not set # CONFIG_FW_LOADER_COMPRESS is not set +CONFIG_FW_CACHE=y # end of Firmware loader CONFIG_WANT_DEV_COREDUMP=y @@ -1536,39 +1542,7 @@ CONFIG_EEPROM_93CX6=m # # Intel MIC & related support # - -# -# Intel MIC Bus Driver -# - -# -# SCIF Bus Driver -# - -# -# VOP Bus Driver -# # CONFIG_VOP_BUS is not set - -# -# Intel MIC Host Driver -# - -# -# Intel MIC Card Driver -# - -# -# SCIF Driver -# - -# -# Intel MIC Coprocessor State Management (COSM) Drivers -# - -# -# VOP Driver -# # end of Intel MIC & related support # CONFIG_ECHO is not set @@ -1714,10 +1688,6 @@ CONFIG_TAP=m CONFIG_VETH=m # CONFIG_NLMON is not set -# -# CAIF transport drivers -# - # # Distributed Switch Architecture drivers # @@ -1811,6 +1781,7 @@ CONFIG_NET_VENDOR_VIA=y CONFIG_NET_VENDOR_WIZNET=y # CONFIG_WIZNET_W5100 is not set # CONFIG_WIZNET_W5300 is not set +# CONFIG_NET_VENDOR_XILINX is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y # CONFIG_MDIO_BCM_UNIMAC is not set @@ -1838,7 +1809,6 @@ CONFIG_AC200_PHY=y # CONFIG_AMD_PHY is not set # CONFIG_AQUANTIA_PHY is not set # CONFIG_AX88796B_PHY is not set -CONFIG_AT803X_PHY=m # CONFIG_BCM7XXX_PHY is not set # CONFIG_BCM87XX_PHY is not set # CONFIG_BROADCOM_PHY is not set @@ -1849,6 +1819,7 @@ CONFIG_AT803X_PHY=m # CONFIG_DP83TC811_PHY is not set # CONFIG_DP83848_PHY is not set # CONFIG_DP83867_PHY is not set +# CONFIG_DP83869_PHY is not set CONFIG_FIXED_PHY=y # CONFIG_ICPLUS_PHY is not set # CONFIG_INTEL_XWAY_PHY is not set @@ -1862,6 +1833,7 @@ CONFIG_MICROCHIP_PHY=m # CONFIG_MICROSEMI_PHY is not set # CONFIG_NATIONAL_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set +CONFIG_AT803X_PHY=m # CONFIG_QSEMI_PHY is not set CONFIG_REALTEK_PHY=y # CONFIG_RENESAS_PHY is not set @@ -2115,7 +2087,6 @@ CONFIG_JOYSTICK_XPAD_LEDS=y # CONFIG_JOYSTICK_PSXPAD_SPI is not set # CONFIG_JOYSTICK_PXRC is not set # CONFIG_JOYSTICK_FSIA6B is not set -# CONFIG_JOYSTICK_RPISENSE is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_PROPERTIES=y @@ -2471,6 +2442,7 @@ CONFIG_PTP_1588_CLOCK=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # +# CONFIG_PTP_1588_CLOCK_IDTCM is not set # end of PTP clock support CONFIG_PINCTRL=y @@ -2509,6 +2481,7 @@ CONFIG_PINCTRL_SUN50I_A64_R=y CONFIG_PINCTRL_SUN50I_H5=y CONFIG_PINCTRL_SUN50I_H6=y CONFIG_PINCTRL_SUN50I_H6_R=y +# CONFIG_PINCTRL_EQUILIBRIUM is not set CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y @@ -2670,6 +2643,8 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LINEAGE is not set # CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2947_I2C is not set +# CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set @@ -2749,6 +2724,7 @@ CONFIG_SENSORS_INA2XX=m # CONFIG_SENSORS_TMP108 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TMP513 is not set # CONFIG_SENSORS_VEXPRESS is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83773G is not set @@ -2770,12 +2746,10 @@ CONFIG_THERMAL_OF=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set # CONFIG_THERMAL_GOV_FAIR_SHARE is not set CONFIG_THERMAL_GOV_STEP_WISE=y # CONFIG_THERMAL_GOV_BANG_BANG is not set # CONFIG_THERMAL_GOV_USER_SPACE is not set -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y # CONFIG_CLOCK_THERMAL is not set # CONFIG_DEVFREQ_THERMAL is not set @@ -3170,6 +3144,7 @@ CONFIG_VIDEO_EM28XX_RC=m CONFIG_V4L_MEM2MEM_DRIVERS=y # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set # CONFIG_VIDEO_SH_VEU is not set +CONFIG_VIDEO_SUN8I_DEINTERLACE=m # CONFIG_V4L_TEST_DRIVERS is not set CONFIG_DVB_PLATFORM_DRIVERS=y CONFIG_CEC_PLATFORM_DRIVERS=y @@ -3658,7 +3633,7 @@ CONFIG_LCD_CLASS_DEVICE=m CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_GENERIC=m CONFIG_BACKLIGHT_PWM=m -# CONFIG_BACKLIGHT_PM8941_WLED is not set +# CONFIG_BACKLIGHT_QCOM_WLED is not set # CONFIG_BACKLIGHT_ADP8860 is not set # CONFIG_BACKLIGHT_ADP8870 is not set # CONFIG_BACKLIGHT_LM3630A is not set @@ -3795,6 +3770,8 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ADAU1761_I2C is not set # CONFIG_SND_SOC_ADAU1761_SPI is not set # CONFIG_SND_SOC_ADAU7002 is not set +# CONFIG_SND_SOC_ADAU7118_HW is not set +# CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4118 is not set # CONFIG_SND_SOC_AK4458 is not set @@ -3826,6 +3803,7 @@ CONFIG_SND_SOC_AK4613=m # CONFIG_SND_SOC_CS4349 is not set # CONFIG_SND_SOC_CS53L30 is not set # CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DA7213 is not set # CONFIG_SND_SOC_DMIC is not set CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES7134 is not set @@ -3870,6 +3848,8 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_STA350 is not set # CONFIG_SND_SOC_STI_SAS is not set # CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2770 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set @@ -4279,6 +4259,7 @@ CONFIG_MMC_SDHCI_OF_ARASAN=y # CONFIG_MMC_SDHCI_OF_DWCMSHC is not set CONFIG_MMC_SDHCI_CADENCE=y CONFIG_MMC_SDHCI_F_SDH30=y +# CONFIG_MMC_SDHCI_MILBEAUT is not set CONFIG_MMC_SPI=y CONFIG_MMC_DW=y CONFIG_MMC_DW_PLTFM=y @@ -4308,6 +4289,7 @@ CONFIG_LEDS_CLASS=y # CONFIG_LEDS_BCM6328 is not set # CONFIG_LEDS_BCM6358 is not set # CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_EL15203000 is not set # CONFIG_LEDS_LM3530 is not set # CONFIG_LEDS_LM3532 is not set # CONFIG_LEDS_LM3642 is not set @@ -4513,6 +4495,7 @@ CONFIG_PL330_DMA=y CONFIG_QCOM_HIDMA_MGMT=y CONFIG_QCOM_HIDMA=y # CONFIG_DW_DMAC is not set +# CONFIG_SF_PDMA is not set # # DMA Clients @@ -4650,6 +4633,7 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_USB_WUSB_CBAF is not set # CONFIG_UWB is not set # CONFIG_EXFAT_FS is not set +# CONFIG_WFX is not set # CONFIG_GOLDFISH is not set # CONFIG_MFD_CROS_EC is not set # CONFIG_CHROME_PLATFORMS is not set @@ -4777,6 +4761,7 @@ CONFIG_SOC_BRCMSTB=y # # NXP/Freescale QorIQ SoC drivers # +# CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers # @@ -4880,6 +4865,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_AD7124 is not set # CONFIG_AD7266 is not set # CONFIG_AD7291 is not set +# CONFIG_AD7292 is not set # CONFIG_AD7298 is not set # CONFIG_AD7476 is not set # CONFIG_AD7606_IFACE_PARALLEL is not set @@ -5076,6 +5062,8 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_ADIS16480 is not set # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set +# CONFIG_FXOS8700_I2C is not set +# CONFIG_FXOS8700_SPI is not set # CONFIG_KMX61 is not set # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set @@ -5086,6 +5074,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # Light sensors # # CONFIG_ADJD_S311 is not set +# CONFIG_ADUX1020 is not set # CONFIG_AL3320A is not set # CONFIG_APDS9300 is not set # CONFIG_APDS9960 is not set @@ -5122,6 +5111,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_US5182D is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set +# CONFIG_VEML6030 is not set # CONFIG_VEML6070 is not set # CONFIG_VL6180 is not set # CONFIG_ZOPT2201 is not set @@ -5230,6 +5220,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # # Temperature sensors # +# CONFIG_LTC2983 is not set # CONFIG_MAXIM_THERMOCOUPLE is not set # CONFIG_MLX90614 is not set # CONFIG_MLX90632 is not set @@ -5594,13 +5585,13 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_UTF8 is not set # CONFIG_DLM is not set # CONFIG_UNICODE is not set +CONFIG_IO_WQ=y # end of File systems # # Security options # CONFIG_KEYS=y -CONFIG_KEYS_COMPAT=y # CONFIG_KEYS_REQUEST_CACHE is not set # CONFIG_PERSISTENT_KEYRINGS is not set # CONFIG_BIG_KEYS is not set @@ -5657,8 +5648,8 @@ CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y @@ -5681,6 +5672,7 @@ CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_AUTHENC=y # CONFIG_CRYPTO_TEST is not set CONFIG_CRYPTO_SIMD=y +CONFIG_CRYPTO_ENGINE=y # # Public-key cryptography @@ -5690,6 +5682,7 @@ CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m # CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_CURVE25519 is not set # # Authenticated Encryption with Associated Data @@ -5730,7 +5723,9 @@ CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CRC32=m -# CONFIG_CRYPTO_XXHASH is not set +CONFIG_CRYPTO_XXHASH=m +CONFIG_CRYPTO_BLAKE2B=m +# CONFIG_CRYPTO_BLAKE2S is not set CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_GHASH=m # CONFIG_CRYPTO_POLY1305 is not set @@ -5742,7 +5737,6 @@ CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_RMD256 is not set # CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_SHA3=m @@ -5754,17 +5748,14 @@ CONFIG_CRYPTO_SM3=m # # Ciphers # -CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set # CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_ARC4=m # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set @@ -5802,13 +5793,36 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y # CONFIG_CRYPTO_USER_API_RNG is not set CONFIG_CRYPTO_USER_API_AEAD=y CONFIG_CRYPTO_HASH_INFO=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +# CONFIG_CRYPTO_LIB_BLAKE2S is not set +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m +# CONFIG_CRYPTO_LIB_CHACHA is not set +# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +# CONFIG_CRYPTO_LIB_POLY1305 is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_ALLWINNER=y +# CONFIG_CRYPTO_DEV_SUN4I_SS is not set +CONFIG_CRYPTO_DEV_SUN8I_CE=y +# CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG is not set +CONFIG_CRYPTO_DEV_SUN8I_SS=y +# CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG is not set # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set # CONFIG_CRYPTO_DEV_CCP is not set # CONFIG_CRYPTO_DEV_SAFEXCEL is not set # CONFIG_CRYPTO_DEV_CCREE is not set # CONFIG_CRYPTO_DEV_HISI_SEC is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y @@ -5895,8 +5909,8 @@ CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y -CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y CONFIG_SWIOTLB=y +CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_REMAP=y CONFIG_DMA_DIRECT_REMAP=y CONFIG_DMA_CMA=y @@ -5948,6 +5962,8 @@ CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_DYNAMIC_DEBUG is not set +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options # @@ -5963,7 +5979,6 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set -CONFIG_DEBUG_FS=y # CONFIG_HEADERS_INSTALL is not set CONFIG_OPTIMIZE_INLINING=y # CONFIG_DEBUG_SECTION_MISMATCH is not set @@ -5973,9 +5988,20 @@ CONFIG_FRAME_POINTER=y # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options +# +# Generic Kernel Debugging Instruments +# CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_DEBUG_FS=y +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_UBSAN_ALIGNMENT=y +# end of Generic Kernel Debugging Instruments + CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y @@ -5993,6 +6019,7 @@ CONFIG_DEBUG_MISC=y CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_SCHED_STACK_END_CHECK is not set # CONFIG_DEBUG_VM is not set CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set @@ -6005,26 +6032,27 @@ CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_KASAN_STACK=1 # end of Memory Debugging -CONFIG_ARCH_HAS_KCOV=y -CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set # CONFIG_DEBUG_SHIRQ is not set # -# Debug Lockups and Hangs +# Debug Oops, Lockups and Hangs # -# CONFIG_SOFTLOCKUP_DETECTOR is not set -# CONFIG_DETECT_HUNG_TASK is not set -# CONFIG_WQ_WATCHDOG is not set -# end of Debug Lockups and Hangs - # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SOFTLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_WQ_WATCHDOG is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# # CONFIG_SCHED_DEBUG is not set CONFIG_SCHED_INFO=y # CONFIG_SCHEDSTATS is not set -# CONFIG_SCHED_STACK_END_CHECK is not set +# end of Scheduler Debugging + # CONFIG_DEBUG_TIMEKEEPING is not set # CONFIG_DEBUG_PREEMPT is not set @@ -6050,11 +6078,17 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set CONFIG_HAVE_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_BUGVERBOSE=y + +# +# Debug kernel data structures +# # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_PLIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Debug kernel data structures + # CONFIG_DEBUG_CREDENTIALS is not set # @@ -6070,17 +6104,43 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=21 # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_NOTIFIER_ERROR_INJECTION is not set -# CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +CONFIG_STRICT_DEVMEM=y +# CONFIG_IO_STRICT_DEVMEM is not set + +# +# arm64 Debugging +# +# CONFIG_ARM64_PTDUMP_DEBUGFS is not set +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set +# CONFIG_DEBUG_WX is not set +# CONFIG_DEBUG_ALIGN_RODATA is not set +# CONFIG_DEBUG_EFI is not set +# CONFIG_ARM64_RELOC_TEST is not set +# CONFIG_CORESIGHT is not set +# end of arm64 Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_LIST_SORT is not set @@ -6119,22 +6179,5 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_STACKINIT is not set # CONFIG_TEST_MEMINIT is not set CONFIG_MEMTEST=y -# CONFIG_BUG_ON_DATA_CORRUPTION is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y -# CONFIG_UBSAN is not set -CONFIG_UBSAN_ALIGNMENT=y -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y -CONFIG_STRICT_DEVMEM=y -# CONFIG_IO_STRICT_DEVMEM is not set -# CONFIG_ARM64_PTDUMP_DEBUGFS is not set -# CONFIG_PID_IN_CONTEXTIDR is not set -# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set -# CONFIG_DEBUG_WX is not set -# CONFIG_DEBUG_ALIGN_RODATA is not set -# CONFIG_DEBUG_EFI is not set -# CONFIG_ARM64_RELOC_TEST is not set -# CONFIG_CORESIGHT is not set +# end of Kernel Testing and Coverage # end of Kernel hacking diff --git a/projects/Allwinner/linux/linux.arm.conf b/projects/Allwinner/linux/linux.arm.conf index bba3c244d9..981ab3cb63 100644 --- a/projects/Allwinner/linux/linux.arm.conf +++ b/projects/Allwinner/linux/linux.arm.conf @@ -1,13 +1,13 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.4.12 Kernel Configuration +# Linux/arm 5.5.0 Kernel Configuration # # -# Compiler: armv7ve-libreelec-linux-gnueabi-gcc-8.3.0 (GCC) 8.3.0 +# Compiler: armv7ve-libreelec-linux-gnueabihf-gcc-9.2.0 (GCC) 9.2.0 # CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=80300 +CONFIG_GCC_VERSION=90200 CONFIG_CLANG_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_HAS_ASM_GOTO=y @@ -21,7 +21,6 @@ CONFIG_BUILDTIME_EXTABLE_SORT=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set -# CONFIG_HEADER_TEST is not set CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" @@ -181,7 +180,6 @@ CONFIG_UID16=y CONFIG_MULTIUSER=y # CONFIG_SGETMASK_SYSCALL is not set CONFIG_SYSFS_SYSCALL=y -# CONFIG_SYSCTL_SYSCALL is not set CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y @@ -513,7 +511,6 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y # CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM is not set -# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set # CONFIG_QORIQ_CPUFREQ is not set # end of CPU Frequency scaling @@ -593,6 +590,8 @@ CONFIG_CRYPTO_SHA1_ARM=y CONFIG_CRYPTO_SHA256_ARM=y CONFIG_CRYPTO_SHA512_ARM=y CONFIG_CRYPTO_AES_ARM=y +# CONFIG_CRYPTO_CHACHA20_NEON is not set +# CONFIG_CRYPTO_POLY1305_ARM is not set # CONFIG_VIRTUALIZATION is not set # @@ -643,7 +642,6 @@ CONFIG_HAVE_COPY_THREAD_TLS=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y -CONFIG_64BIT_TIME=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y @@ -652,7 +650,6 @@ CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y CONFIG_ARCH_HAS_PHYS_TO_DMA=y -CONFIG_REFCOUNT_FULL=y # CONFIG_LOCK_EVENT_COUNTS is not set # @@ -682,6 +679,7 @@ CONFIG_MODULE_UNLOAD=y CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_CGROUP_RWSTAT=y CONFIG_BLK_DEV_BSG=y CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_DEV_INTEGRITY is not set @@ -1350,6 +1348,7 @@ CONFIG_FW_LOADER=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_FW_LOADER_USER_HELPER is not set # CONFIG_FW_LOADER_COMPRESS is not set +CONFIG_FW_CACHE=y # end of Firmware loader CONFIG_WANT_DEV_COREDUMP=y @@ -1471,39 +1470,7 @@ CONFIG_EEPROM_93CX6=m # # Intel MIC & related support # - -# -# Intel MIC Bus Driver -# - -# -# SCIF Bus Driver -# - -# -# VOP Bus Driver -# # CONFIG_VOP_BUS is not set - -# -# Intel MIC Host Driver -# - -# -# Intel MIC Card Driver -# - -# -# SCIF Driver -# - -# -# Intel MIC Coprocessor State Management (COSM) Drivers -# - -# -# VOP Driver -# # end of Intel MIC & related support # CONFIG_ECHO is not set @@ -1641,10 +1608,6 @@ CONFIG_TUN=y CONFIG_VETH=m # CONFIG_NLMON is not set -# -# CAIF transport drivers -# - # # Distributed Switch Architecture drivers # @@ -1741,7 +1704,6 @@ CONFIG_SWPHY=y # CONFIG_AMD_PHY is not set # CONFIG_AQUANTIA_PHY is not set # CONFIG_AX88796B_PHY is not set -# CONFIG_AT803X_PHY is not set # CONFIG_BCM7XXX_PHY is not set # CONFIG_BCM87XX_PHY is not set # CONFIG_BROADCOM_PHY is not set @@ -1752,6 +1714,7 @@ CONFIG_SWPHY=y # CONFIG_DP83TC811_PHY is not set # CONFIG_DP83848_PHY is not set # CONFIG_DP83867_PHY is not set +# CONFIG_DP83869_PHY is not set CONFIG_FIXED_PHY=y # CONFIG_ICPLUS_PHY is not set # CONFIG_INTEL_XWAY_PHY is not set @@ -1765,6 +1728,7 @@ CONFIG_MICROCHIP_T1_PHY=y # CONFIG_MICROSEMI_PHY is not set # CONFIG_NATIONAL_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_AT803X_PHY is not set # CONFIG_QSEMI_PHY is not set # CONFIG_REALTEK_PHY is not set # CONFIG_RENESAS_PHY is not set @@ -2038,7 +2002,6 @@ CONFIG_JOYSTICK_XPAD_LEDS=y # CONFIG_JOYSTICK_PSXPAD_SPI is not set # CONFIG_JOYSTICK_PXRC is not set # CONFIG_JOYSTICK_FSIA6B is not set -# CONFIG_JOYSTICK_RPISENSE is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set CONFIG_INPUT_MISC=y @@ -2307,6 +2270,7 @@ CONFIG_PTP_1588_CLOCK=y # # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # +# CONFIG_PTP_1588_CLOCK_IDTCM is not set # end of PTP clock support CONFIG_PINCTRL=y @@ -2341,6 +2305,7 @@ CONFIG_PINCTRL_SUN9I_A80_R=y # CONFIG_PINCTRL_SUN50I_H5 is not set # CONFIG_PINCTRL_SUN50I_H6 is not set # CONFIG_PINCTRL_SUN50I_H6_R is not set +# CONFIG_PINCTRL_EQUILIBRIUM is not set CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 @@ -2487,6 +2452,8 @@ CONFIG_HWMON=y # CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LINEAGE is not set # CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2947_I2C is not set +# CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set @@ -2566,6 +2533,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_TMP108 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TMP513 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83773G is not set # CONFIG_SENSORS_W83781D is not set @@ -2586,12 +2554,10 @@ CONFIG_THERMAL_OF=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set # CONFIG_THERMAL_GOV_FAIR_SHARE is not set CONFIG_THERMAL_GOV_STEP_WISE=y # CONFIG_THERMAL_GOV_BANG_BANG is not set # CONFIG_THERMAL_GOV_USER_SPACE is not set -CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y CONFIG_CLOCK_THERMAL=y CONFIG_DEVFREQ_THERMAL=y @@ -2978,7 +2944,10 @@ CONFIG_DVB_AS102=m # USB HDMI CEC adapters # # CONFIG_V4L_PLATFORM_DRIVERS is not set -# CONFIG_V4L_MEM2MEM_DRIVERS is not set +CONFIG_V4L_MEM2MEM_DRIVERS=y +# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set +# CONFIG_VIDEO_SH_VEU is not set +CONFIG_VIDEO_SUN8I_DEINTERLACE=m # CONFIG_V4L_TEST_DRIVERS is not set # CONFIG_DVB_PLATFORM_DRIVERS is not set # CONFIG_CEC_PLATFORM_DRIVERS is not set @@ -3092,9 +3061,11 @@ CONFIG_VIDEO_THS8200=m # # Camera sensor devices # +# CONFIG_VIDEO_HI556 is not set # CONFIG_VIDEO_IMX214 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX319 is not set # CONFIG_VIDEO_IMX355 is not set # CONFIG_VIDEO_OV2640 is not set @@ -3414,6 +3385,7 @@ CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y CONFIG_DRM_KMS_FB_HELPER=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set @@ -3694,6 +3666,8 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ADAU1761_I2C is not set # CONFIG_SND_SOC_ADAU1761_SPI is not set # CONFIG_SND_SOC_ADAU7002 is not set +# CONFIG_SND_SOC_ADAU7118_HW is not set +# CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4118 is not set # CONFIG_SND_SOC_AK4458 is not set @@ -3725,6 +3699,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_CS4349 is not set # CONFIG_SND_SOC_CS53L30 is not set # CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DA7213 is not set # CONFIG_SND_SOC_DMIC is not set CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES7134 is not set @@ -3769,6 +3744,8 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_STA350 is not set # CONFIG_SND_SOC_STI_SAS is not set # CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2770 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set @@ -4209,6 +4186,7 @@ CONFIG_LEDS_CLASS=y # CONFIG_LEDS_BCM6328 is not set # CONFIG_LEDS_BCM6358 is not set # CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_EL15203000 is not set # CONFIG_LEDS_LM3530 is not set # CONFIG_LEDS_LM3532 is not set # CONFIG_LEDS_LM3642 is not set @@ -4403,6 +4381,7 @@ CONFIG_DMA_SUN6I=y # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_DW_DMAC is not set +# CONFIG_SF_PDMA is not set # # DMA Clients @@ -4538,6 +4517,7 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_USB_WUSB_CBAF is not set # CONFIG_UWB is not set # CONFIG_EXFAT_FS is not set +# CONFIG_WFX is not set # CONFIG_GOLDFISH is not set # CONFIG_MFD_CROS_EC is not set # CONFIG_CHROME_PLATFORMS is not set @@ -4634,6 +4614,7 @@ CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y # # NXP/Freescale QorIQ SoC drivers # +# CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers # @@ -4735,6 +4716,7 @@ CONFIG_IIO_SW_TRIGGER=y # CONFIG_AD7124 is not set # CONFIG_AD7266 is not set # CONFIG_AD7291 is not set +# CONFIG_AD7292 is not set # CONFIG_AD7298 is not set # CONFIG_AD7476 is not set # CONFIG_AD7606_IFACE_PARALLEL is not set @@ -4932,6 +4914,8 @@ CONFIG_SUN4I_GPADC=y # CONFIG_ADIS16480 is not set # CONFIG_BMI160_I2C is not set # CONFIG_BMI160_SPI is not set +# CONFIG_FXOS8700_I2C is not set +# CONFIG_FXOS8700_SPI is not set # CONFIG_KMX61 is not set # CONFIG_INV_MPU6050_I2C is not set # CONFIG_INV_MPU6050_SPI is not set @@ -4942,6 +4926,7 @@ CONFIG_SUN4I_GPADC=y # Light sensors # # CONFIG_ADJD_S311 is not set +# CONFIG_ADUX1020 is not set # CONFIG_AL3320A is not set # CONFIG_APDS9300 is not set # CONFIG_APDS9960 is not set @@ -4978,6 +4963,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_US5182D is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set +# CONFIG_VEML6030 is not set # CONFIG_VEML6070 is not set # CONFIG_VL6180 is not set # CONFIG_ZOPT2201 is not set @@ -5079,6 +5065,7 @@ CONFIG_SUN4I_GPADC=y # # Temperature sensors # +# CONFIG_LTC2983 is not set # CONFIG_MAXIM_THERMOCOUPLE is not set # CONFIG_MLX90614 is not set # CONFIG_MLX90632 is not set @@ -5412,6 +5399,7 @@ CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y # CONFIG_DLM is not set # CONFIG_UNICODE is not set +CONFIG_IO_WQ=y # end of File systems # @@ -5457,8 +5445,8 @@ CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=m @@ -5480,6 +5468,7 @@ CONFIG_CRYPTO_NULL2=y # CONFIG_CRYPTO_CRYPTD is not set CONFIG_CRYPTO_AUTHENC=m # CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_ENGINE=m # # Public-key cryptography @@ -5489,6 +5478,7 @@ CONFIG_CRYPTO_DH=y CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m # CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_CURVE25519 is not set # # Authenticated Encryption with Associated Data @@ -5529,7 +5519,9 @@ CONFIG_CRYPTO_HMAC=m # CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CRC32=m -# CONFIG_CRYPTO_XXHASH is not set +CONFIG_CRYPTO_XXHASH=m +CONFIG_CRYPTO_BLAKE2B=m +# CONFIG_CRYPTO_BLAKE2S is not set # CONFIG_CRYPTO_CRCT10DIF is not set CONFIG_CRYPTO_GHASH=m # CONFIG_CRYPTO_POLY1305 is not set @@ -5541,7 +5533,6 @@ CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_RMD256 is not set # CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=m CONFIG_CRYPTO_SHA256=m # CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_SHA3 is not set @@ -5553,17 +5544,14 @@ CONFIG_CRYPTO_SHA256=m # # Ciphers # -CONFIG_CRYPTO_LIB_AES=y CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set # CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_ARC4=m # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_LIB_DES=y CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set @@ -5601,13 +5589,33 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y # CONFIG_CRYPTO_USER_API_RNG is not set CONFIG_CRYPTO_USER_API_AEAD=y CONFIG_CRYPTO_HASH_INFO=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +# CONFIG_CRYPTO_LIB_BLAKE2S is not set +# CONFIG_CRYPTO_LIB_CHACHA is not set +# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +# CONFIG_CRYPTO_LIB_POLY1305 is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_LIB_SHA256=m CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_ALLWINNER=y +CONFIG_CRYPTO_DEV_SUN4I_SS=m +# CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG is not set +CONFIG_CRYPTO_DEV_SUN8I_CE=m +# CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG is not set +CONFIG_CRYPTO_DEV_SUN8I_SS=m +# CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG is not set # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set -CONFIG_CRYPTO_DEV_SUN4I_SS=y -# CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG is not set # CONFIG_CRYPTO_DEV_SAFEXCEL is not set # CONFIG_CRYPTO_DEV_CCREE is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y @@ -5684,6 +5692,7 @@ CONFIG_NEED_DMA_MAP_STATE=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_REMAP=y CONFIG_DMA_CMA=y @@ -5708,6 +5717,9 @@ CONFIG_CLZ_TAB=y CONFIG_MPILIB=y CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_32=y CONFIG_FONT_SUPPORT=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y @@ -5731,6 +5743,8 @@ CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_DYNAMIC_DEBUG is not set +CONFIG_SYMBOLIC_ERRNAME=y +# CONFIG_DEBUG_BUGVERBOSE is not set # end of printk and dmesg options # @@ -5741,7 +5755,6 @@ CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set -CONFIG_DEBUG_FS=y # CONFIG_HEADERS_INSTALL is not set CONFIG_OPTIMIZE_INLINING=y # CONFIG_DEBUG_SECTION_MISMATCH is not set @@ -5749,9 +5762,19 @@ CONFIG_SECTION_MISMATCH_WARN_ONLY=y # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options +# +# Generic Kernel Debugging Instruments +# CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_DEBUG_FS=y +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_UBSAN is not set +CONFIG_UBSAN_ALIGNMENT=y +# end of Generic Kernel Debugging Instruments + CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y @@ -5769,6 +5792,7 @@ CONFIG_DEBUG_MISC=y CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_SCHED_STACK_END_CHECK is not set # CONFIG_DEBUG_VM is not set CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set @@ -5779,25 +5803,26 @@ CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_KASAN_STACK=1 # end of Memory Debugging -CONFIG_ARCH_HAS_KCOV=y -CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set # CONFIG_DEBUG_SHIRQ is not set # -# Debug Lockups and Hangs +# Debug Oops, Lockups and Hangs # -# CONFIG_SOFTLOCKUP_DETECTOR is not set -# CONFIG_DETECT_HUNG_TASK is not set -# CONFIG_WQ_WATCHDOG is not set -# end of Debug Lockups and Hangs - # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SOFTLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_WQ_WATCHDOG is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# # CONFIG_SCHED_DEBUG is not set # CONFIG_SCHEDSTATS is not set -# CONFIG_SCHED_STACK_END_CHECK is not set +# end of Scheduler Debugging + # CONFIG_DEBUG_TIMEKEEPING is not set # @@ -5821,11 +5846,17 @@ CONFIG_LOCK_DEBUGGING_SUPPORT=y # CONFIG_STACKTRACE is not set # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set -# CONFIG_DEBUG_BUGVERBOSE is not set + +# +# Debug kernel data structures +# # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_PLIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Debug kernel data structures + # CONFIG_DEBUG_CREDENTIALS is not set # @@ -5841,8 +5872,6 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=21 # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_NOTIFIER_ERROR_INJECTION is not set -# CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y @@ -5853,6 +5882,35 @@ CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set + +# +# arm Debugging +# +# CONFIG_ARM_PTDUMP_DEBUGFS is not set +# CONFIG_DEBUG_WX is not set +# CONFIG_UNWINDER_FRAME_POINTER is not set +CONFIG_UNWINDER_ARM=y +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_LL is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_CORESIGHT is not set +# end of arm Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_LIST_SORT is not set @@ -5891,23 +5949,5 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_STACKINIT is not set # CONFIG_TEST_MEMINIT is not set # CONFIG_MEMTEST is not set -# CONFIG_BUG_ON_DATA_CORRUPTION is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -# CONFIG_UBSAN is not set -CONFIG_UBSAN_ALIGNMENT=y -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y -# CONFIG_STRICT_DEVMEM is not set -# CONFIG_ARM_PTDUMP_DEBUGFS is not set -# CONFIG_DEBUG_WX is not set -# CONFIG_UNWINDER_FRAME_POINTER is not set -CONFIG_UNWINDER_ARM=y -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_LL is not set -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -# CONFIG_PID_IN_CONTEXTIDR is not set -# CONFIG_CORESIGHT is not set +# end of Kernel Testing and Coverage # end of Kernel hacking diff --git a/projects/Allwinner/patches/linux/0001-backport-from-5.5.patch b/projects/Allwinner/patches/linux/0001-backport-from-5.5.patch deleted file mode 100644 index c2d0bdbed7..0000000000 --- a/projects/Allwinner/patches/linux/0001-backport-from-5.5.patch +++ /dev/null @@ -1,5556 +0,0 @@ -From c41784b042ac9cf97f2e871aceef3e06eff14140 Mon Sep 17 00:00:00 2001 -From: Cheng-Yi Chiang -Date: Mon, 2 Sep 2019 11:54:35 +0800 -Subject: [PATCH] drm: dw-hdmi-i2s: enable audio clock in audio_startup - -In the designware databook, the sequence of enabling audio clock and -setting format is not clearly specified. -Currently, audio clock is enabled in the end of hw_param ops after -setting format. - -On some monitors, there is a possibility that audio does not come out. -Fix this by enabling audio clock in audio_startup ops -before hw_param ops setting format. - -Signed-off-by: Cheng-Yi Chiang -Reviewed-by: Douglas Anderson -Reviewed-by: Jonas Karlman -Tested-by: Douglas Anderson -Signed-off-by: Neil Armstrong -Link: https://patchwork.freedesktop.org/patch/msgid/20190902035435.44463-1-cychiang@chromium.org ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -index 1d15cf9b6821..34d8e837555f 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -@@ -109,6 +109,14 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, - hdmi_write(audio, conf0, HDMI_AUD_CONF0); - hdmi_write(audio, conf1, HDMI_AUD_CONF1); - -+ return 0; -+} -+ -+static int dw_hdmi_i2s_audio_startup(struct device *dev, void *data) -+{ -+ struct dw_hdmi_i2s_audio_data *audio = data; -+ struct dw_hdmi *hdmi = audio->hdmi; -+ - dw_hdmi_audio_enable(hdmi); - - return 0; -@@ -153,6 +161,7 @@ static int dw_hdmi_i2s_get_dai_id(struct snd_soc_component *component, - - static struct hdmi_codec_ops dw_hdmi_i2s_ops = { - .hw_params = dw_hdmi_i2s_hw_params, -+ .audio_startup = dw_hdmi_i2s_audio_startup, - .audio_shutdown = dw_hdmi_i2s_audio_shutdown, - .get_eld = dw_hdmi_i2s_get_eld, - .get_dai_id = dw_hdmi_i2s_get_dai_id, --- -2.23.0 - -From 3250cdf938dce5447cf4f895bb3ec3b929a95e09 Mon Sep 17 00:00:00 2001 -From: Yakir Yang -Date: Wed, 11 Sep 2019 16:26:46 +0800 -Subject: [PATCH] drm: bridge/dw_hdmi: add audio sample channel status setting - -When transmitting IEC60985 linear PCM audio, we configure the -Aduio Sample Channel Status information in the IEC60958 frame. -The status bit is already available in iec.status of hdmi_codec_params. - -This fix the issue that audio does not come out on some monitors -(e.g. LG 22CV241) - -Note that these registers are only for interfaces: -I2S audio interface, General Purpose Audio (GPA), or AHB audio DMA -(AHBAUDDMA). -For S/PDIF interface this information comes from the stream. - -Currently this function dw_hdmi_set_channel_status is only called -from dw-hdmi-i2s-audio in I2S setup. - -Signed-off-by: Yakir Yang -Signed-off-by: Cheng-Yi Chiang -Reviewed-by: Jonas Karlman -Signed-off-by: Neil Armstrong -Link: https://patchwork.freedesktop.org/patch/msgid/20190911082646.134347-1-cychiang@chromium.org ---- - .../drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 1 + - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 20 +++++++++++++++++++ - drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 2 ++ - include/drm/bridge/dw_hdmi.h | 1 + - 4 files changed, 24 insertions(+) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -index 34d8e837555f..20f4f92dd866 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -@@ -102,6 +102,7 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, - } - - dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate); -+ dw_hdmi_set_channel_status(hdmi, hparms->iec.status); - dw_hdmi_set_channel_count(hdmi, hparms->channels); - dw_hdmi_set_channel_allocation(hdmi, hparms->cea.channel_allocation); - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index bd65d0479683..aa7efd4da1c8 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -582,6 +582,26 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) - return n; - } - -+/* -+ * When transmitting IEC60958 linear PCM audio, these registers allow to -+ * configure the channel status information of all the channel status -+ * bits in the IEC60958 frame. For the moment this configuration is only -+ * used when the I2S audio interface, General Purpose Audio (GPA), -+ * or AHB audio DMA (AHBAUDDMA) interface is active -+ * (for S/PDIF interface this information comes from the stream). -+ */ -+void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, -+ u8 *channel_status) -+{ -+ /* -+ * Set channel status register for frequency and word length. -+ * Use default values for other registers. -+ */ -+ hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7); -+ hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8); -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status); -+ - static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, - unsigned long pixel_clk, unsigned int sample_rate) - { -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -index 6988f12d89d9..fcff5059db24 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h -@@ -158,6 +158,8 @@ - #define HDMI_FC_SPDDEVICEINF 0x1062 - #define HDMI_FC_AUDSCONF 0x1063 - #define HDMI_FC_AUDSSTAT 0x1064 -+#define HDMI_FC_AUDSCHNLS7 0x106e -+#define HDMI_FC_AUDSCHNLS8 0x106f - #define HDMI_FC_DATACH0FILL 0x1070 - #define HDMI_FC_DATACH1FILL 0x1071 - #define HDMI_FC_DATACH2FILL 0x1072 -diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h -index cf528c289857..4b3e863c4f8a 100644 ---- a/include/drm/bridge/dw_hdmi.h -+++ b/include/drm/bridge/dw_hdmi.h -@@ -156,6 +156,7 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense); - - void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); - void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt); -+void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, u8 *channel_status); - void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca); - void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); - void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); --- -2.23.0 - -From 3ee5f8ab5e718afdde9984a089137360bdfc66eb Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 14 Sep 2019 15:51:00 +0200 -Subject: [PATCH] clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLL - -Audio devices needs exact clock rates in order to correctly reproduce -the sound. Until now, only integer factors were used to configure H6 -audio PLL which resulted in inexact rates. Fix that by adding support -for fractional factors using sigma-delta modulation look-up table. It -contains values for two most commonly used audio base frequencies. - -Signed-off-by: Jernej Skrabec -Acked-by: Chen-Yu Tsai -Signed-off-by: Maxime Ripard ---- - drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 21 +++++++++++++++------ - 1 file changed, 15 insertions(+), 6 deletions(-) - -diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -index d89353a3cdec..ed6338d74474 100644 ---- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -@@ -203,12 +203,21 @@ static struct ccu_nkmp pll_hsic_clk = { - * hardcode it to match with the clock names. - */ - #define SUN50I_H6_PLL_AUDIO_REG 0x078 -+ -+static struct ccu_sdm_setting pll_audio_sdm_table[] = { -+ { .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 }, -+ { .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 }, -+}; -+ - static struct ccu_nm pll_audio_base_clk = { - .enable = BIT(31), - .lock = BIT(28), - .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), - .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ -+ .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, -+ BIT(24), 0x178, BIT(31)), - .common = { -+ .features = CCU_FEATURE_SIGMA_DELTA_MOD, - .reg = 0x078, - .hw.init = CLK_HW_INIT("pll-audio-base", "osc24M", - &ccu_nm_ops, -@@ -753,12 +762,12 @@ static const struct clk_hw *clk_parent_pll_audio[] = { - }; - - /* -- * The divider of pll-audio is fixed to 8 now, as pll-audio-4x has a -- * fixed post-divider 2. -+ * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200 -+ * rates can be set exactly in conjunction with sigma-delta modulation. - */ - static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio", - clk_parent_pll_audio, -- 8, 1, CLK_SET_RATE_PARENT); -+ 24, 1, CLK_SET_RATE_PARENT); - static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", - clk_parent_pll_audio, - 4, 1, CLK_SET_RATE_PARENT); -@@ -1215,12 +1224,12 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev) - } - - /* -- * Force the post-divider of pll-audio to 8 and the output divider -- * of it to 1, to make the clock name represents the real frequency. -+ * Force the post-divider of pll-audio to 12 and the output divider -+ * of it to 2, so 24576000 and 22579200 rates can be set exactly. - */ - val = readl(reg + SUN50I_H6_PLL_AUDIO_REG); - val &= ~(GENMASK(21, 16) | BIT(0)); -- writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG); -+ writel(val | (11 << 16) | BIT(0), reg + SUN50I_H6_PLL_AUDIO_REG); - - /* - * First clock parent (osc32K) is unusable for CEC. But since there --- -2.23.0 - -From 4947913491aa83d760e5710c3290f150eb56847a Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 1 Oct 2019 21:59:25 +0200 -Subject: [PATCH] clk: sunxi-ng: h6: Allow GPU to change parent rate - -GPU PLL was designed with dynamic frequency switching in mind so driver -can adjust rate based on the GPU load. - -Allow GPU clock to change parent rate (GPU PLL is the only possible -parent of GPU clock). - -Signed-off-by: Jernej Skrabec ---- - drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -index d89353a3cdec..e254c06c8621 100644 ---- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c -@@ -290,7 +290,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670, - 0, 3, /* M */ - 24, 1, /* mux */ - BIT(31), /* gate */ -- 0); -+ CLK_SET_RATE_PARENT); - - static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2", - 0x67c, BIT(0), 0); --- -2.23.0 - -From 1606cf29f8e743fe254485bb350f0d9d3c33affd Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Fri, 4 Oct 2019 00:14:15 +0200 -Subject: [PATCH] arm64: dts: allwinner: a64: orangepi-win: Enable audio codec - -This patch enables internal audio codec on OrangePi Win board by -enabling all relevant nodes and adding appropriate routing. Board has -on-board microphone (MIC1) and 3.5 mm jack with stereo audio and -microphone (MIC2). - -Signed-off-by: Jernej Skrabec ---- - .../dts/allwinner/sun50i-a64-orangepi-win.dts | 29 +++++++++++++++++++ - 1 file changed, 29 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -index 04446e4716c4..f54a415f2e3b 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -@@ -114,6 +114,19 @@ - }; - }; - -+&codec { -+ status = "okay"; -+}; -+ -+&codec_analog { -+ cpvdd-supply = <®_eldo1>; -+ status = "okay"; -+}; -+ -+&dai { -+ status = "okay"; -+}; -+ - &de { - status = "okay"; - }; -@@ -333,6 +346,22 @@ - vcc-hdmi-supply = <®_dldo1>; - }; - -+&sound { -+ status = "okay"; -+ simple-audio-card,widgets = "Headphone", "Headphone Jack", -+ "Microphone", "Microphone Jack", -+ "Microphone", "Onboard Microphone"; -+ simple-audio-card,routing = -+ "Left DAC", "AIF1 Slot 0 Left", -+ "Right DAC", "AIF1 Slot 0 Right", -+ "AIF1 Slot 0 Left ADC", "Left ADC", -+ "AIF1 Slot 0 Right ADC", "Right ADC", -+ "Headphone Jack", "HP", -+ "MIC2", "Microphone Jack", -+ "Onboard Microphone", "MBIAS", -+ "MIC1", "Onboard Microphone"; -+}; -+ - &spi0 { - status = "okay"; - --- -2.23.0 - -From cd380e0d00b2b21506f9319a626b6205e9d64aae Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Mon, 7 Oct 2019 22:31:51 +0200 -Subject: [PATCH] arm64: dts: allwinner: h6: Add pin configs for uart1 - -Orange Pi 3 uses UART1 for bluetooth. Add pinconfigs so that we can use -them. - -Signed-off-by: Ondrej Jirman -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 4020a1aafa3e..0754f01fd731 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -299,6 +299,16 @@ - pins = "PH0", "PH1"; - function = "uart0"; - }; -+ -+ uart1_pins: uart1-pins { -+ pins = "PG6", "PG7"; -+ function = "uart1"; -+ }; -+ -+ uart1_rts_cts_pins: uart1-rts-cts-pins { -+ pins = "PG8", "PG9"; -+ function = "uart1"; -+ }; - }; - - gic: interrupt-controller@3021000 { --- -2.23.0 - -From 351170463471d2037aa034625d05f185e6d85f80 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Mon, 7 Oct 2019 22:31:52 +0200 -Subject: [PATCH] arm64: dts: allwinner: orange-pi-3: Enable UART1 / Bluetooth - -The board contains AP6256 WiFi/BT module that has its bluetooth part -connected to SoC's UART1 port. Enable this port, and add node for the -bluetooth device. - -Bluetooth part is named bcm4345c5. - -You'll need a BCM4345C5.hcd firmware file that can be found in the -Xulongs's repository for H6: - -https://github.com/orangepi-xunlong/OrangePiH6_external/tree/master/ap6256 - -The driver expects the firmware at the following path relative to the -firmware directory: - - brcm/BCM4345C5.hcd - -Signed-off-by: Ondrej Jirman -Signed-off-by: Maxime Ripard ---- - .../dts/allwinner/sun50i-h6-orangepi-3.dts | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -index eb379cd402ac..2557cc6c8d50 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -@@ -15,6 +15,7 @@ - - aliases { - serial0 = &uart0; -+ serial1 = &uart1; - }; - - chosen { -@@ -269,6 +270,24 @@ - status = "okay"; - }; - -+/* There's the BT part of the AP6256 connected to that UART */ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; -+ uart-has-rtscts; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm4345c5"; -+ clocks = <&rtc 1>; -+ clock-names = "lpo"; -+ device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ -+ host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ -+ shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ -+ max-speed = <1500000>; -+ }; -+}; -+ - &usb2otg { - /* - * This board doesn't have a controllable VBUS even though it --- -2.23.0 - -From 8ae3a0862993c09a8ef0f9abb379553370c517e3 Mon Sep 17 00:00:00 2001 -From: Ricardo Ribalda Delgado -Date: Mon, 7 Oct 2019 12:06:32 -0300 -Subject: [PATCH] media: Documentation: media: Document V4L2_CTRL_TYPE_AREA - -A struct v4l2_area containing the width and the height of a rectangular -area. - -Reviewed-by: Jacopo Mondi -Reviewed-by: Philipp Zabel -Signed-off-by: Ricardo Ribalda Delgado -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - Documentation/media/uapi/v4l/vidioc-queryctrl.rst | 6 ++++++ - Documentation/media/videodev2.h.rst.exceptions | 1 + - 2 files changed, 7 insertions(+) - -diff --git a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -index a3d56ffbf4cc..33aff21b7d11 100644 ---- a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -+++ b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -@@ -443,6 +443,12 @@ See also the examples in :ref:`control`. - - n/a - - A struct :c:type:`v4l2_ctrl_mpeg2_quantization`, containing MPEG-2 - quantization matrices for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_AREA`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_area`, containing the width and the height -+ of a rectangular area. Units depend on the use case. - * - ``V4L2_CTRL_TYPE_H264_SPS`` - - n/a - - n/a -diff --git a/Documentation/media/videodev2.h.rst.exceptions b/Documentation/media/videodev2.h.rst.exceptions -index adeb6b7a15cb..b58e381bdf7b 100644 ---- a/Documentation/media/videodev2.h.rst.exceptions -+++ b/Documentation/media/videodev2.h.rst.exceptions -@@ -141,6 +141,7 @@ replace symbol V4L2_CTRL_TYPE_H264_PPS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_H264_SCALING_MATRIX :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_H264_SLICE_PARAMS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_H264_DECODE_PARAMS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_AREA :c:type:`v4l2_ctrl_type` - - # V4L2 capability defines - replace define V4L2_CAP_VIDEO_CAPTURE device-capabilities --- -2.23.0 - -From 61fd036d01111679b01e4b92e6bd0cdd33809aea Mon Sep 17 00:00:00 2001 -From: Ricardo Ribalda Delgado -Date: Mon, 7 Oct 2019 12:06:33 -0300 -Subject: [PATCH] media: add V4L2_CID_UNIT_CELL_SIZE control - -This control returns the unit cell size in nanometres. The struct provides -the width and the height in separated fields to take into consideration -asymmetric pixels and/or hardware binning. -This control is required for automatic calibration of sensors/cameras. - -Reviewed-by: Philipp Zabel -Signed-off-by: Ricardo Ribalda Delgado -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/v4l2-core/v4l2-ctrls.c | 5 +++++ - include/uapi/linux/v4l2-controls.h | 1 + - 2 files changed, 6 insertions(+) - -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 96cab2e173d3..bf50d37ef6c1 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -996,6 +996,7 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_AUTO_FOCUS_RANGE: return "Auto Focus, Range"; - case V4L2_CID_PAN_SPEED: return "Pan, Speed"; - case V4L2_CID_TILT_SPEED: return "Tilt, Speed"; -+ case V4L2_CID_UNIT_CELL_SIZE: return "Unit Cell Size"; - - /* FM Radio Modulator controls */ - /* Keep the order of the 'case's the same as in v4l2-controls.h! */ -@@ -1377,6 +1378,10 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER: - *type = V4L2_CTRL_TYPE_VP8_FRAME_HEADER; - break; -+ case V4L2_CID_UNIT_CELL_SIZE: -+ *type = V4L2_CTRL_TYPE_AREA; -+ *flags |= V4L2_CTRL_FLAG_READ_ONLY; -+ break; - default: - *type = V4L2_CTRL_TYPE_INTEGER; - break; -diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h -index a2669b79b294..5a7bedee2b0e 100644 ---- a/include/uapi/linux/v4l2-controls.h -+++ b/include/uapi/linux/v4l2-controls.h -@@ -1034,6 +1034,7 @@ enum v4l2_jpeg_chroma_subsampling { - #define V4L2_CID_TEST_PATTERN_GREENR (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 5) - #define V4L2_CID_TEST_PATTERN_BLUE (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 6) - #define V4L2_CID_TEST_PATTERN_GREENB (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 7) -+#define V4L2_CID_UNIT_CELL_SIZE (V4L2_CID_IMAGE_SOURCE_CLASS_BASE + 8) - - - /* Image processing controls */ --- -2.23.0 - -From d1dc49370f8371b00e682ac409aa1987ce641e93 Mon Sep 17 00:00:00 2001 -From: Ricardo Ribalda Delgado -Date: Mon, 7 Oct 2019 12:06:31 -0300 -Subject: [PATCH] media: add V4L2_CTRL_TYPE_AREA control type - -This type contains the width and the height of a rectangular area. - -Reviewed-by: Jacopo Mondi -Signed-off-by: Ricardo Ribalda Delgado -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/v4l2-core/v4l2-ctrls.c | 21 ++++++++++++++ - include/media/v4l2-ctrls.h | 42 ++++++++++++++++++++++++++++ - include/uapi/linux/videodev2.h | 6 ++++ - 3 files changed, 69 insertions(+) - -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 219d8aeefa20..96cab2e173d3 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -1677,6 +1677,7 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, - { - struct v4l2_ctrl_mpeg2_slice_params *p_mpeg2_slice_params; - struct v4l2_ctrl_vp8_frame_header *p_vp8_frame_header; -+ struct v4l2_area *area; - void *p = ptr.p + idx * ctrl->elem_size; - - switch ((u32)ctrl->type) { -@@ -1753,6 +1754,11 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, - zero_padding(p_vp8_frame_header->entropy_header); - zero_padding(p_vp8_frame_header->coder_state); - break; -+ case V4L2_CTRL_TYPE_AREA: -+ area = p; -+ if (!area->width || !area->height) -+ return -EINVAL; -+ break; - default: - return -EINVAL; - } -@@ -2427,6 +2433,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, - case V4L2_CTRL_TYPE_VP8_FRAME_HEADER: - elem_size = sizeof(struct v4l2_ctrl_vp8_frame_header); - break; -+ case V4L2_CTRL_TYPE_AREA: -+ elem_size = sizeof(struct v4l2_area); -+ break; - default: - if (type < V4L2_CTRL_COMPOUND_TYPES) - elem_size = sizeof(s32); -@@ -4116,6 +4125,18 @@ int __v4l2_ctrl_s_ctrl_string(struct v4l2_ctrl *ctrl, const char *s) - } - EXPORT_SYMBOL(__v4l2_ctrl_s_ctrl_string); - -+int __v4l2_ctrl_s_ctrl_area(struct v4l2_ctrl *ctrl, -+ const struct v4l2_area *area) -+{ -+ lockdep_assert_held(ctrl->handler->lock); -+ -+ /* It's a driver bug if this happens. */ -+ WARN_ON(ctrl->type != V4L2_CTRL_TYPE_AREA); -+ *ctrl->p_new.p_area = *area; -+ return set_ctrl(NULL, ctrl, 0); -+} -+EXPORT_SYMBOL(__v4l2_ctrl_s_ctrl_area); -+ - void v4l2_ctrl_request_complete(struct media_request *req, - struct v4l2_ctrl_handler *main_hdl) - { -diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h -index fb0883836548..c9ca867ef32b 100644 ---- a/include/media/v4l2-ctrls.h -+++ b/include/media/v4l2-ctrls.h -@@ -50,6 +50,7 @@ struct poll_table_struct; - * @p_h264_slice_params: Pointer to a struct v4l2_ctrl_h264_slice_params. - * @p_h264_decode_params: Pointer to a struct v4l2_ctrl_h264_decode_params. - * @p_vp8_frame_header: Pointer to a VP8 frame header structure. -+ * @p_area: Pointer to an area. - * @p: Pointer to a compound value. - */ - union v4l2_ctrl_ptr { -@@ -68,6 +69,7 @@ union v4l2_ctrl_ptr { - struct v4l2_ctrl_h264_slice_params *p_h264_slice_params; - struct v4l2_ctrl_h264_decode_params *p_h264_decode_params; - struct v4l2_ctrl_vp8_frame_header *p_vp8_frame_header; -+ struct v4l2_area *p_area; - void *p; - }; - -@@ -1087,6 +1089,46 @@ static inline int v4l2_ctrl_s_ctrl_string(struct v4l2_ctrl *ctrl, const char *s) - return rval; - } - -+/** -+ * __v4l2_ctrl_s_ctrl_area() - Unlocked variant of v4l2_ctrl_s_ctrl_area(). -+ * -+ * @ctrl: The control. -+ * @area: The new area. -+ * -+ * This sets the control's new area safely by going through the control -+ * framework. This function assumes the control's handler is already locked, -+ * allowing it to be used from within the &v4l2_ctrl_ops functions. -+ * -+ * This function is for area type controls only. -+ */ -+int __v4l2_ctrl_s_ctrl_area(struct v4l2_ctrl *ctrl, -+ const struct v4l2_area *area); -+ -+/** -+ * v4l2_ctrl_s_ctrl_area() - Helper function to set a control's area value -+ * from within a driver. -+ * -+ * @ctrl: The control. -+ * @area: The new area. -+ * -+ * This sets the control's new area safely by going through the control -+ * framework. This function will lock the control's handler, so it cannot be -+ * used from within the &v4l2_ctrl_ops functions. -+ * -+ * This function is for area type controls only. -+ */ -+static inline int v4l2_ctrl_s_ctrl_area(struct v4l2_ctrl *ctrl, -+ const struct v4l2_area *area) -+{ -+ int rval; -+ -+ v4l2_ctrl_lock(ctrl); -+ rval = __v4l2_ctrl_s_ctrl_area(ctrl, area); -+ v4l2_ctrl_unlock(ctrl); -+ -+ return rval; -+} -+ - /* Internal helper functions that deal with control events. */ - extern const struct v4l2_subscribed_event_ops v4l2_ctrl_sub_ev_ops; - -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index 530638dffd93..b3c0961b62a0 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -422,6 +422,11 @@ struct v4l2_fract { - __u32 denominator; - }; - -+struct v4l2_area { -+ __u32 width; -+ __u32 height; -+}; -+ - /** - * struct v4l2_capability - Describes V4L2 device caps returned by VIDIOC_QUERYCAP - * -@@ -1720,6 +1725,7 @@ enum v4l2_ctrl_type { - V4L2_CTRL_TYPE_U8 = 0x0100, - V4L2_CTRL_TYPE_U16 = 0x0101, - V4L2_CTRL_TYPE_U32 = 0x0102, -+ V4L2_CTRL_TYPE_AREA = 0x0106, - }; - - /* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */ --- -2.23.0 - -From 256fa3920874b0f1f4cb79ad6766493a22187153 Mon Sep 17 00:00:00 2001 -From: Paul Kocialkowski -Date: Tue, 22 Oct 2019 12:26:52 -0300 -Subject: [PATCH] media: v4l: Add definitions for HEVC stateless decoding - -This introduces the required definitions for HEVC decoding support with -stateless VPUs. The controls associated to the HEVC slice format provide -the required meta-data for decoding slices extracted from the bitstream. - -They are not exported to the public V4L2 API since reworking this API -will likely be needed for covering various use-cases and new hardware. - -Multi-slice decoding is exposed as a valid decoding mode to match current -H.264 support but it is not yet implemented. - -The interface comes with the following limitations: -* No custom quantization matrices (scaling lists); -* Support for a single temporal layer only; -* No slice entry point offsets support; -* No conformance window support; -* No VUI parameters support; -* No support for SPS extensions: range, multilayer, 3d, scc, 4 bits; -* No support for PPS extensions: range, multilayer, 3d, scc, 4 bits. - -Signed-off-by: Paul Kocialkowski -[hverkuil-cisco@xs4all.nl: use 1ULL in flags defines in hevc-ctrls.h] -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - Documentation/media/uapi/v4l/biblio.rst | 9 + - .../media/uapi/v4l/ext-ctrls-codec.rst | 553 +++++++++++++++++- - .../media/uapi/v4l/vidioc-queryctrl.rst | 18 + - .../media/videodev2.h.rst.exceptions | 3 + - drivers/media/v4l2-core/v4l2-ctrls.c | 109 +++- - drivers/media/v4l2-core/v4l2-ioctl.c | 1 + - include/media/hevc-ctrls.h | 212 +++++++ - include/media/v4l2-ctrls.h | 7 + - 8 files changed, 908 insertions(+), 4 deletions(-) - create mode 100644 include/media/hevc-ctrls.h - -diff --git a/Documentation/media/uapi/v4l/biblio.rst b/Documentation/media/uapi/v4l/biblio.rst -index ad2ff258afa8..8095f57d3d75 100644 ---- a/Documentation/media/uapi/v4l/biblio.rst -+++ b/Documentation/media/uapi/v4l/biblio.rst -@@ -131,6 +131,15 @@ ITU-T Rec. H.264 Specification (04/2017 Edition) - - :author: International Telecommunication Union (http://www.itu.ch) - -+.. _hevc: -+ -+ITU H.265/HEVC -+============== -+ -+:title: ITU-T Rec. H.265 | ISO/IEC 23008-2 "High Efficiency Video Coding" -+ -+:author: International Telecommunication Union (http://www.itu.ch), International Organisation for Standardisation (http://www.iso.ch) -+ - .. _jfif: - - JFIF -diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -index 6bb901de0939..a1209f68c5e8 100644 ---- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -+++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -@@ -1985,9 +1985,9 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type - - - ``reference_ts`` - - Timestamp of the V4L2 capture buffer to use as reference, used - with B-coded and P-coded frames. The timestamp refers to the -- ``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the -- :c:func:`v4l2_timeval_to_ns()` function to convert the struct -- :c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64. -+ ``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the -+ :c:func:`v4l2_timeval_to_ns()` function to convert the struct -+ :c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64. - * - __u16 - - ``frame_num`` - - -@@ -3695,3 +3695,550 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - - Indicates whether to generate SPS and PPS at every IDR. Setting it to 0 - disables generating SPS and PPS at every IDR. Setting it to one enables - generating SPS and PPS at every IDR. -+ -+.. _v4l2-mpeg-hevc: -+ -+``V4L2_CID_MPEG_VIDEO_HEVC_SPS (struct)`` -+ Specifies the Sequence Parameter Set fields (as extracted from the -+ bitstream) for the associated HEVC slice data. -+ These bitstream parameters are defined according to :ref:`hevc`. -+ They are described in section 7.4.3.2 "Sequence parameter set RBSP -+ semantics" of the specification. -+ -+.. c:type:: v4l2_ctrl_hevc_sps -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_hevc_sps -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u16 -+ - ``pic_width_in_luma_samples`` -+ - -+ * - __u16 -+ - ``pic_height_in_luma_samples`` -+ - -+ * - __u8 -+ - ``bit_depth_luma_minus8`` -+ - -+ * - __u8 -+ - ``bit_depth_chroma_minus8`` -+ - -+ * - __u8 -+ - ``log2_max_pic_order_cnt_lsb_minus4`` -+ - -+ * - __u8 -+ - ``sps_max_dec_pic_buffering_minus1`` -+ - -+ * - __u8 -+ - ``sps_max_num_reorder_pics`` -+ - -+ * - __u8 -+ - ``sps_max_latency_increase_plus1`` -+ - -+ * - __u8 -+ - ``log2_min_luma_coding_block_size_minus3`` -+ - -+ * - __u8 -+ - ``log2_diff_max_min_luma_coding_block_size`` -+ - -+ * - __u8 -+ - ``log2_min_luma_transform_block_size_minus2`` -+ - -+ * - __u8 -+ - ``log2_diff_max_min_luma_transform_block_size`` -+ - -+ * - __u8 -+ - ``max_transform_hierarchy_depth_inter`` -+ - -+ * - __u8 -+ - ``max_transform_hierarchy_depth_intra`` -+ - -+ * - __u8 -+ - ``pcm_sample_bit_depth_luma_minus1`` -+ - -+ * - __u8 -+ - ``pcm_sample_bit_depth_chroma_minus1`` -+ - -+ * - __u8 -+ - ``log2_min_pcm_luma_coding_block_size_minus3`` -+ - -+ * - __u8 -+ - ``log2_diff_max_min_pcm_luma_coding_block_size`` -+ - -+ * - __u8 -+ - ``num_short_term_ref_pic_sets`` -+ - -+ * - __u8 -+ - ``num_long_term_ref_pics_sps`` -+ - -+ * - __u8 -+ - ``chroma_format_idc`` -+ - -+ * - __u64 -+ - ``flags`` -+ - See :ref:`Sequence Parameter Set Flags ` -+ -+.. _hevc_sps_flags: -+ -+``Sequence Parameter Set Flags`` -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE`` -+ - 0x00000001 -+ - -+ * - ``V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED`` -+ - 0x00000002 -+ - -+ * - ``V4L2_HEVC_SPS_FLAG_AMP_ENABLED`` -+ - 0x00000004 -+ - -+ * - ``V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET`` -+ - 0x00000008 -+ - -+ * - ``V4L2_HEVC_SPS_FLAG_PCM_ENABLED`` -+ - 0x00000010 -+ - -+ * - ``V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED`` -+ - 0x00000020 -+ - -+ * - ``V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT`` -+ - 0x00000040 -+ - -+ * - ``V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED`` -+ - 0x00000080 -+ - -+ * - ``V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED`` -+ - 0x00000100 -+ - -+ -+``V4L2_CID_MPEG_VIDEO_HEVC_PPS (struct)`` -+ Specifies the Picture Parameter Set fields (as extracted from the -+ bitstream) for the associated HEVC slice data. -+ These bitstream parameters are defined according to :ref:`hevc`. -+ They are described in section 7.4.3.3 "Picture parameter set RBSP -+ semantics" of the specification. -+ -+.. c:type:: v4l2_ctrl_hevc_pps -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_hevc_pps -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``num_extra_slice_header_bits`` -+ - -+ * - __s8 -+ - ``init_qp_minus26`` -+ - -+ * - __u8 -+ - ``diff_cu_qp_delta_depth`` -+ - -+ * - __s8 -+ - ``pps_cb_qp_offset`` -+ - -+ * - __s8 -+ - ``pps_cr_qp_offset`` -+ - -+ * - __u8 -+ - ``num_tile_columns_minus1`` -+ - -+ * - __u8 -+ - ``num_tile_rows_minus1`` -+ - -+ * - __u8 -+ - ``column_width_minus1[20]`` -+ - -+ * - __u8 -+ - ``row_height_minus1[22]`` -+ - -+ * - __s8 -+ - ``pps_beta_offset_div2`` -+ - -+ * - __s8 -+ - ``pps_tc_offset_div2`` -+ - -+ * - __u8 -+ - ``log2_parallel_merge_level_minus2`` -+ - -+ * - __u8 -+ - ``padding[4]`` -+ - Applications and drivers must set this to zero. -+ * - __u64 -+ - ``flags`` -+ - See :ref:`Picture Parameter Set Flags ` -+ -+.. _hevc_pps_flags: -+ -+``Picture Parameter Set Flags`` -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT`` -+ - 0x00000001 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT`` -+ - 0x00000002 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED`` -+ - 0x00000004 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT`` -+ - 0x00000008 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED`` -+ - 0x00000010 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED`` -+ - 0x00000020 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED`` -+ - 0x00000040 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT`` -+ - 0x00000080 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED`` -+ - 0x00000100 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED`` -+ - 0x00000200 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED`` -+ - 0x00000400 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_TILES_ENABLED`` -+ - 0x00000800 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED`` -+ - 0x00001000 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED`` -+ - 0x00002000 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED`` -+ - 0x00004000 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED`` -+ - 0x00008000 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER`` -+ - 0x00010000 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT`` -+ - 0x00020000 -+ - -+ * - ``V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT`` -+ - 0x00040000 -+ - -+ -+``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (struct)`` -+ Specifies various slice-specific parameters, especially from the NAL unit -+ header, general slice segment header and weighted prediction parameter -+ parts of the bitstream. -+ These bitstream parameters are defined according to :ref:`hevc`. -+ They are described in section 7.4.7 "General slice segment header -+ semantics" of the specification. -+ -+.. c:type:: v4l2_ctrl_hevc_slice_params -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_hevc_slice_params -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u32 -+ - ``bit_size`` -+ - Size (in bits) of the current slice data. -+ * - __u32 -+ - ``data_bit_offset`` -+ - Offset (in bits) to the video data in the current slice data. -+ * - __u8 -+ - ``nal_unit_type`` -+ - -+ * - __u8 -+ - ``nuh_temporal_id_plus1`` -+ - -+ * - __u8 -+ - ``slice_type`` -+ - -+ (V4L2_HEVC_SLICE_TYPE_I, V4L2_HEVC_SLICE_TYPE_P or -+ V4L2_HEVC_SLICE_TYPE_B). -+ * - __u8 -+ - ``colour_plane_id`` -+ - -+ * - __u16 -+ - ``slice_pic_order_cnt`` -+ - -+ * - __u8 -+ - ``num_ref_idx_l0_active_minus1`` -+ - -+ * - __u8 -+ - ``num_ref_idx_l1_active_minus1`` -+ - -+ * - __u8 -+ - ``collocated_ref_idx`` -+ - -+ * - __u8 -+ - ``five_minus_max_num_merge_cand`` -+ - -+ * - __s8 -+ - ``slice_qp_delta`` -+ - -+ * - __s8 -+ - ``slice_cb_qp_offset`` -+ - -+ * - __s8 -+ - ``slice_cr_qp_offset`` -+ - -+ * - __s8 -+ - ``slice_act_y_qp_offset`` -+ - -+ * - __s8 -+ - ``slice_act_cb_qp_offset`` -+ - -+ * - __s8 -+ - ``slice_act_cr_qp_offset`` -+ - -+ * - __s8 -+ - ``slice_beta_offset_div2`` -+ - -+ * - __s8 -+ - ``slice_tc_offset_div2`` -+ - -+ * - __u8 -+ - ``pic_struct`` -+ - -+ * - __u8 -+ - ``num_active_dpb_entries`` -+ - The number of entries in ``dpb``. -+ * - __u8 -+ - ``ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` -+ - The list of L0 reference elements as indices in the DPB. -+ * - __u8 -+ - ``ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` -+ - The list of L1 reference elements as indices in the DPB. -+ * - __u8 -+ - ``num_rps_poc_st_curr_before`` -+ - The number of reference pictures in the short-term set that come before -+ the current frame. -+ * - __u8 -+ - ``num_rps_poc_st_curr_after`` -+ - The number of reference pictures in the short-term set that come after -+ the current frame. -+ * - __u8 -+ - ``num_rps_poc_lt_curr`` -+ - The number of reference pictures in the long-term set. -+ * - __u8 -+ - ``padding[7]`` -+ - Applications and drivers must set this to zero. -+ * - struct :c:type:`v4l2_hevc_dpb_entry` -+ - ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` -+ - The decoded picture buffer, for meta-data about reference frames. -+ * - struct :c:type:`v4l2_hevc_pred_weight_table` -+ - ``pred_weight_table`` -+ - The prediction weight coefficients for inter-picture prediction. -+ * - __u64 -+ - ``flags`` -+ - See :ref:`Slice Parameters Flags ` -+ -+.. _hevc_slice_params_flags: -+ -+``Slice Parameters Flags`` -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA`` -+ - 0x00000001 -+ - -+ * - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA`` -+ - 0x00000002 -+ - -+ * - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED`` -+ - 0x00000004 -+ - -+ * - ``V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO`` -+ - 0x00000008 -+ - -+ * - ``V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT`` -+ - 0x00000010 -+ - -+ * - ``V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0`` -+ - 0x00000020 -+ - -+ * - ``V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV`` -+ - 0x00000040 -+ - -+ * - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED`` -+ - 0x00000080 -+ - -+ * - ``V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED`` -+ - 0x00000100 -+ - -+ -+.. c:type:: v4l2_hevc_dpb_entry -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_hevc_dpb_entry -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u64 -+ - ``timestamp`` -+ - Timestamp of the V4L2 capture buffer to use as reference, used -+ with B-coded and P-coded frames. The timestamp refers to the -+ ``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the -+ :c:func:`v4l2_timeval_to_ns()` function to convert the struct -+ :c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64. -+ * - __u8 -+ - ``rps`` -+ - The reference set for the reference frame -+ (V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_BEFORE, -+ V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_AFTER or -+ V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR) -+ * - __u8 -+ - ``field_pic`` -+ - Whether the reference is a field picture or a frame. -+ * - __u16 -+ - ``pic_order_cnt[2]`` -+ - The picture order count of the reference. Only the first element of the -+ array is used for frame pictures, while the first element identifies the -+ top field and the second the bottom field in field-coded pictures. -+ * - __u8 -+ - ``padding[2]`` -+ - Applications and drivers must set this to zero. -+ -+.. c:type:: v4l2_hevc_pred_weight_table -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_hevc_pred_weight_table -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``luma_log2_weight_denom`` -+ - -+ * - __s8 -+ - ``delta_chroma_log2_weight_denom`` -+ - -+ * - __s8 -+ - ``delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` -+ - -+ * - __s8 -+ - ``luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` -+ - -+ * - __s8 -+ - ``delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]`` -+ - -+ * - __s8 -+ - ``chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]`` -+ - -+ * - __s8 -+ - ``delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` -+ - -+ * - __s8 -+ - ``luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` -+ - -+ * - __s8 -+ - ``delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]`` -+ - -+ * - __s8 -+ - ``chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]`` -+ - -+ * - __u8 -+ - ``padding[6]`` -+ - Applications and drivers must set this to zero. -+ -+``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (enum)`` -+ Specifies the decoding mode to use. Currently exposes slice-based and -+ frame-based decoding but new modes might be added later on. -+ This control is used as a modifier for V4L2_PIX_FMT_HEVC_SLICE -+ pixel format. Applications that support V4L2_PIX_FMT_HEVC_SLICE -+ are required to set this control in order to specify the decoding mode -+ that is expected for the buffer. -+ Drivers may expose a single or multiple decoding modes, depending -+ on what they can support. -+ -+ .. note:: -+ -+ This menu control is not yet part of the public kernel API and -+ it is expected to change. -+ -+.. c:type:: v4l2_mpeg_video_hevc_decode_mode -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED`` -+ - 0 -+ - Decoding is done at the slice granularity. -+ The OUTPUT buffer must contain a single slice. -+ * - ``V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED`` -+ - 1 -+ - Decoding is done at the frame granularity. -+ The OUTPUT buffer must contain all slices needed to decode the -+ frame. The OUTPUT buffer must also contain both fields. -+ -+``V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (enum)`` -+ Specifies the HEVC slice start code expected for each slice. -+ This control is used as a modifier for V4L2_PIX_FMT_HEVC_SLICE -+ pixel format. Applications that support V4L2_PIX_FMT_HEVC_SLICE -+ are required to set this control in order to specify the start code -+ that is expected for the buffer. -+ Drivers may expose a single or multiple start codes, depending -+ on what they can support. -+ -+ .. note:: -+ -+ This menu control is not yet part of the public kernel API and -+ it is expected to change. -+ -+.. c:type:: v4l2_mpeg_video_hevc_start_code -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE`` -+ - 0 -+ - Selecting this value specifies that HEVC slices are passed -+ to the driver without any start code. -+ * - ``V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B`` -+ - 1 -+ - Selecting this value specifies that HEVC slices are expected -+ to be prefixed by Annex B start codes. According to :ref:`hevc` -+ valid start codes can be 3-bytes 0x000001 or 4-bytes 0x00000001. -diff --git a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -index 33aff21b7d11..6690928e657b 100644 ---- a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -+++ b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -@@ -479,6 +479,24 @@ See also the examples in :ref:`control`. - - n/a - - A struct :c:type:`v4l2_ctrl_h264_decode_params`, containing H264 - decode parameters for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_HEVC_SPS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_hevc_sps`, containing HEVC Sequence -+ Parameter Set for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_HEVC_PPS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_hevc_pps`, containing HEVC Picture -+ Parameter Set for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_hevc_slice_params`, containing HEVC -+ slice parameters for stateless video decoders. - - .. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.7cm}| - -diff --git a/Documentation/media/videodev2.h.rst.exceptions b/Documentation/media/videodev2.h.rst.exceptions -index c23e5ef30c78..cb6ccf91776e 100644 ---- a/Documentation/media/videodev2.h.rst.exceptions -+++ b/Documentation/media/videodev2.h.rst.exceptions -@@ -141,6 +141,9 @@ replace symbol V4L2_CTRL_TYPE_H264_PPS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_H264_SCALING_MATRIX :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_H264_SLICE_PARAMS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_H264_DECODE_PARAMS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_HEVC_SPS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_HEVC_PPS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_AREA :c:type:`v4l2_ctrl_type` - - # V4L2 capability defines -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index bf50d37ef6c1..b4caf2d4d076 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -568,6 +568,16 @@ const char * const *v4l2_ctrl_get_menu(u32 id) - "Disabled at slice boundary", - "NULL", - }; -+ static const char * const hevc_decode_mode[] = { -+ "Slice-Based", -+ "Frame-Based", -+ NULL, -+ }; -+ static const char * const hevc_start_code[] = { -+ "No Start Code", -+ "Annex B Start Code", -+ NULL, -+ }; - - switch (id) { - case V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ: -@@ -689,7 +699,10 @@ const char * const *v4l2_ctrl_get_menu(u32 id) - return hevc_tier; - case V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE: - return hevc_loop_filter_mode; -- -+ case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE: -+ return hevc_decode_mode; -+ case V4L2_CID_MPEG_VIDEO_HEVC_START_CODE: -+ return hevc_start_code; - default: - return NULL; - } -@@ -959,6 +972,11 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD: return "HEVC Size of Length Field"; - case V4L2_CID_MPEG_VIDEO_REF_NUMBER_FOR_PFRAMES: return "Reference Frames for a P-Frame"; - case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: return "Prepend SPS and PPS to IDR"; -+ case V4L2_CID_MPEG_VIDEO_HEVC_SPS: return "HEVC Sequence Parameter Set"; -+ case V4L2_CID_MPEG_VIDEO_HEVC_PPS: return "HEVC Picture Parameter Set"; -+ case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: return "HEVC Slice Parameters"; -+ case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE: return "HEVC Decode Mode"; -+ case V4L2_CID_MPEG_VIDEO_HEVC_START_CODE: return "HEVC Start Code"; - - /* CAMERA controls */ - /* Keep the order of the 'case's the same as in v4l2-controls.h! */ -@@ -1268,6 +1286,8 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD: - case V4L2_CID_MPEG_VIDEO_HEVC_TIER: - case V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE: -+ case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE: -+ case V4L2_CID_MPEG_VIDEO_HEVC_START_CODE: - *type = V4L2_CTRL_TYPE_MENU; - break; - case V4L2_CID_LINK_FREQ: -@@ -1378,6 +1398,15 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER: - *type = V4L2_CTRL_TYPE_VP8_FRAME_HEADER; - break; -+ case V4L2_CID_MPEG_VIDEO_HEVC_SPS: -+ *type = V4L2_CTRL_TYPE_HEVC_SPS; -+ break; -+ case V4L2_CID_MPEG_VIDEO_HEVC_PPS: -+ *type = V4L2_CTRL_TYPE_HEVC_PPS; -+ break; -+ case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: -+ *type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS; -+ break; - case V4L2_CID_UNIT_CELL_SIZE: - *type = V4L2_CTRL_TYPE_AREA; - *flags |= V4L2_CTRL_FLAG_READ_ONLY; -@@ -1682,8 +1711,12 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, - { - struct v4l2_ctrl_mpeg2_slice_params *p_mpeg2_slice_params; - struct v4l2_ctrl_vp8_frame_header *p_vp8_frame_header; -+ struct v4l2_ctrl_hevc_sps *p_hevc_sps; -+ struct v4l2_ctrl_hevc_pps *p_hevc_pps; -+ struct v4l2_ctrl_hevc_slice_params *p_hevc_slice_params; - struct v4l2_area *area; - void *p = ptr.p + idx * ctrl->elem_size; -+ unsigned int i; - - switch ((u32)ctrl->type) { - case V4L2_CTRL_TYPE_MPEG2_SLICE_PARAMS: -@@ -1759,11 +1792,76 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, - zero_padding(p_vp8_frame_header->entropy_header); - zero_padding(p_vp8_frame_header->coder_state); - break; -+ -+ case V4L2_CTRL_TYPE_HEVC_SPS: -+ p_hevc_sps = p; -+ -+ if (!(p_hevc_sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED)) { -+ p_hevc_sps->pcm_sample_bit_depth_luma_minus1 = 0; -+ p_hevc_sps->pcm_sample_bit_depth_chroma_minus1 = 0; -+ p_hevc_sps->log2_min_pcm_luma_coding_block_size_minus3 = 0; -+ p_hevc_sps->log2_diff_max_min_pcm_luma_coding_block_size = 0; -+ } -+ -+ if (!(p_hevc_sps->flags & -+ V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT)) -+ p_hevc_sps->num_long_term_ref_pics_sps = 0; -+ break; -+ -+ case V4L2_CTRL_TYPE_HEVC_PPS: -+ p_hevc_pps = p; -+ -+ if (!(p_hevc_pps->flags & -+ V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED)) -+ p_hevc_pps->diff_cu_qp_delta_depth = 0; -+ -+ if (!(p_hevc_pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED)) { -+ p_hevc_pps->num_tile_columns_minus1 = 0; -+ p_hevc_pps->num_tile_rows_minus1 = 0; -+ memset(&p_hevc_pps->column_width_minus1, 0, -+ sizeof(p_hevc_pps->column_width_minus1)); -+ memset(&p_hevc_pps->row_height_minus1, 0, -+ sizeof(p_hevc_pps->row_height_minus1)); -+ -+ p_hevc_pps->flags &= -+ ~V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED; -+ } -+ -+ if (p_hevc_pps->flags & -+ V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER) { -+ p_hevc_pps->pps_beta_offset_div2 = 0; -+ p_hevc_pps->pps_tc_offset_div2 = 0; -+ } -+ -+ zero_padding(*p_hevc_pps); -+ break; -+ -+ case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: -+ p_hevc_slice_params = p; -+ -+ if (p_hevc_slice_params->num_active_dpb_entries > -+ V4L2_HEVC_DPB_ENTRIES_NUM_MAX) -+ return -EINVAL; -+ -+ zero_padding(p_hevc_slice_params->pred_weight_table); -+ -+ for (i = 0; i < p_hevc_slice_params->num_active_dpb_entries; -+ i++) { -+ struct v4l2_hevc_dpb_entry *dpb_entry = -+ &p_hevc_slice_params->dpb[i]; -+ -+ zero_padding(*dpb_entry); -+ } -+ -+ zero_padding(*p_hevc_slice_params); -+ break; -+ - case V4L2_CTRL_TYPE_AREA: - area = p; - if (!area->width || !area->height) - return -EINVAL; - break; -+ - default: - return -EINVAL; - } -@@ -2438,6 +2536,15 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, - case V4L2_CTRL_TYPE_VP8_FRAME_HEADER: - elem_size = sizeof(struct v4l2_ctrl_vp8_frame_header); - break; -+ case V4L2_CTRL_TYPE_HEVC_SPS: -+ elem_size = sizeof(struct v4l2_ctrl_hevc_sps); -+ break; -+ case V4L2_CTRL_TYPE_HEVC_PPS: -+ elem_size = sizeof(struct v4l2_ctrl_hevc_pps); -+ break; -+ case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: -+ elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params); -+ break; - case V4L2_CTRL_TYPE_AREA: - elem_size = sizeof(struct v4l2_area); - break; -diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 2753073cf340..d26c83d4c255 100644 ---- a/drivers/media/v4l2-core/v4l2-ioctl.c -+++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1367,6 +1367,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) - case V4L2_PIX_FMT_VP8_FRAME: descr = "VP8 Frame"; break; - case V4L2_PIX_FMT_VP9: descr = "VP9"; break; - case V4L2_PIX_FMT_HEVC: descr = "HEVC"; break; /* aka H.265 */ -+ case V4L2_PIX_FMT_HEVC_SLICE: descr = "HEVC Parsed Slice Data"; break; - case V4L2_PIX_FMT_FWHT: descr = "FWHT"; break; /* used in vicodec */ - case V4L2_PIX_FMT_FWHT_STATELESS: descr = "FWHT Stateless"; break; /* used in vicodec */ - case V4L2_PIX_FMT_CPIA1: descr = "GSPCA CPiA YUV"; break; -diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -new file mode 100644 -index 000000000000..1009cf0891cc ---- /dev/null -+++ b/include/media/hevc-ctrls.h -@@ -0,0 +1,212 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * These are the HEVC state controls for use with stateless HEVC -+ * codec drivers. -+ * -+ * It turns out that these structs are not stable yet and will undergo -+ * more changes. So keep them private until they are stable and ready to -+ * become part of the official public API. -+ */ -+ -+#ifndef _HEVC_CTRLS_H_ -+#define _HEVC_CTRLS_H_ -+ -+#include -+ -+/* The pixel format isn't stable at the moment and will likely be renamed. */ -+#define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */ -+ -+#define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 1008) -+#define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 1009) -+#define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 1010) -+#define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_MPEG_BASE + 1015) -+#define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_MPEG_BASE + 1016) -+ -+/* enum v4l2_ctrl_type type values */ -+#define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 -+#define V4L2_CTRL_TYPE_HEVC_PPS 0x0121 -+#define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122 -+ -+enum v4l2_mpeg_video_hevc_decode_mode { -+ V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED, -+ V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED, -+}; -+ -+enum v4l2_mpeg_video_hevc_start_code { -+ V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE, -+ V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B, -+}; -+ -+#define V4L2_HEVC_SLICE_TYPE_B 0 -+#define V4L2_HEVC_SLICE_TYPE_P 1 -+#define V4L2_HEVC_SLICE_TYPE_I 2 -+ -+#define V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE (1ULL << 0) -+#define V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED (1ULL << 1) -+#define V4L2_HEVC_SPS_FLAG_AMP_ENABLED (1ULL << 2) -+#define V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET (1ULL << 3) -+#define V4L2_HEVC_SPS_FLAG_PCM_ENABLED (1ULL << 4) -+#define V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED (1ULL << 5) -+#define V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT (1ULL << 6) -+#define V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED (1ULL << 7) -+#define V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED (1ULL << 8) -+ -+/* The controls are not stable at the moment and will likely be reworked. */ -+struct v4l2_ctrl_hevc_sps { -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ -+ __u16 pic_width_in_luma_samples; -+ __u16 pic_height_in_luma_samples; -+ __u8 bit_depth_luma_minus8; -+ __u8 bit_depth_chroma_minus8; -+ __u8 log2_max_pic_order_cnt_lsb_minus4; -+ __u8 sps_max_dec_pic_buffering_minus1; -+ __u8 sps_max_num_reorder_pics; -+ __u8 sps_max_latency_increase_plus1; -+ __u8 log2_min_luma_coding_block_size_minus3; -+ __u8 log2_diff_max_min_luma_coding_block_size; -+ __u8 log2_min_luma_transform_block_size_minus2; -+ __u8 log2_diff_max_min_luma_transform_block_size; -+ __u8 max_transform_hierarchy_depth_inter; -+ __u8 max_transform_hierarchy_depth_intra; -+ __u8 pcm_sample_bit_depth_luma_minus1; -+ __u8 pcm_sample_bit_depth_chroma_minus1; -+ __u8 log2_min_pcm_luma_coding_block_size_minus3; -+ __u8 log2_diff_max_min_pcm_luma_coding_block_size; -+ __u8 num_short_term_ref_pic_sets; -+ __u8 num_long_term_ref_pics_sps; -+ __u8 chroma_format_idc; -+ -+ __u8 padding; -+ -+ __u64 flags; -+}; -+ -+#define V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT (1ULL << 0) -+#define V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT (1ULL << 1) -+#define V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED (1ULL << 2) -+#define V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT (1ULL << 3) -+#define V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED (1ULL << 4) -+#define V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED (1ULL << 5) -+#define V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED (1ULL << 6) -+#define V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT (1ULL << 7) -+#define V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED (1ULL << 8) -+#define V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED (1ULL << 9) -+#define V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED (1ULL << 10) -+#define V4L2_HEVC_PPS_FLAG_TILES_ENABLED (1ULL << 11) -+#define V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED (1ULL << 12) -+#define V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED (1ULL << 13) -+#define V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 14) -+#define V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED (1ULL << 15) -+#define V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER (1ULL << 16) -+#define V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT (1ULL << 17) -+#define V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT (1ULL << 18) -+ -+struct v4l2_ctrl_hevc_pps { -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ -+ __u8 num_extra_slice_header_bits; -+ __s8 init_qp_minus26; -+ __u8 diff_cu_qp_delta_depth; -+ __s8 pps_cb_qp_offset; -+ __s8 pps_cr_qp_offset; -+ __u8 num_tile_columns_minus1; -+ __u8 num_tile_rows_minus1; -+ __u8 column_width_minus1[20]; -+ __u8 row_height_minus1[22]; -+ __s8 pps_beta_offset_div2; -+ __s8 pps_tc_offset_div2; -+ __u8 log2_parallel_merge_level_minus2; -+ -+ __u8 padding[4]; -+ __u64 flags; -+}; -+ -+#define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_BEFORE 0x01 -+#define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_AFTER 0x02 -+#define V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR 0x03 -+ -+#define V4L2_HEVC_DPB_ENTRIES_NUM_MAX 16 -+ -+struct v4l2_hevc_dpb_entry { -+ __u64 timestamp; -+ __u8 rps; -+ __u8 field_pic; -+ __u16 pic_order_cnt[2]; -+ __u8 padding[2]; -+}; -+ -+struct v4l2_hevc_pred_weight_table { -+ __s8 delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ __s8 luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ __s8 delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]; -+ __s8 chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]; -+ -+ __s8 delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ __s8 luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ __s8 delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]; -+ __s8 chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]; -+ -+ __u8 padding[6]; -+ -+ __u8 luma_log2_weight_denom; -+ __s8 delta_chroma_log2_weight_denom; -+}; -+ -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA (1ULL << 0) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA (1ULL << 1) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED (1ULL << 2) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO (1ULL << 3) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT (1ULL << 4) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0 (1ULL << 5) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV (1ULL << 6) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED (1ULL << 7) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 8) -+ -+struct v4l2_ctrl_hevc_slice_params { -+ __u32 bit_size; -+ __u32 data_bit_offset; -+ -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */ -+ __u8 nal_unit_type; -+ __u8 nuh_temporal_id_plus1; -+ -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ -+ __u8 slice_type; -+ __u8 colour_plane_id; -+ __u16 slice_pic_order_cnt; -+ __u8 num_ref_idx_l0_active_minus1; -+ __u8 num_ref_idx_l1_active_minus1; -+ __u8 collocated_ref_idx; -+ __u8 five_minus_max_num_merge_cand; -+ __s8 slice_qp_delta; -+ __s8 slice_cb_qp_offset; -+ __s8 slice_cr_qp_offset; -+ __s8 slice_act_y_qp_offset; -+ __s8 slice_act_cb_qp_offset; -+ __s8 slice_act_cr_qp_offset; -+ __s8 slice_beta_offset_div2; -+ __s8 slice_tc_offset_div2; -+ -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture timing SEI message */ -+ __u8 pic_struct; -+ -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ -+ __u8 num_active_dpb_entries; -+ __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ -+ __u8 num_rps_poc_st_curr_before; -+ __u8 num_rps_poc_st_curr_after; -+ __u8 num_rps_poc_lt_curr; -+ -+ __u8 padding; -+ -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ -+ struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ -+ struct v4l2_hevc_pred_weight_table pred_weight_table; -+ -+ __u64 flags; -+}; -+ -+#endif -diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h -index 26205ba3a0a0..e719d56fc024 100644 ---- a/include/media/v4l2-ctrls.h -+++ b/include/media/v4l2-ctrls.h -@@ -21,6 +21,7 @@ - #include - #include - #include -+#include - - /* forward references */ - struct file; -@@ -50,6 +51,9 @@ struct poll_table_struct; - * @p_h264_slice_params: Pointer to a struct v4l2_ctrl_h264_slice_params. - * @p_h264_decode_params: Pointer to a struct v4l2_ctrl_h264_decode_params. - * @p_vp8_frame_header: Pointer to a VP8 frame header structure. -+ * @p_hevc_sps: Pointer to an HEVC sequence parameter set structure. -+ * @p_hevc_pps: Pointer to an HEVC picture parameter set structure. -+ * @p_hevc_slice_params: Pointer to an HEVC slice parameters structure. - * @p_area: Pointer to an area. - * @p: Pointer to a compound value. - */ -@@ -69,6 +73,9 @@ union v4l2_ctrl_ptr { - struct v4l2_ctrl_h264_slice_params *p_h264_slice_params; - struct v4l2_ctrl_h264_decode_params *p_h264_decode_params; - struct v4l2_ctrl_vp8_frame_header *p_vp8_frame_header; -+ struct v4l2_ctrl_hevc_sps *p_hevc_sps; -+ struct v4l2_ctrl_hevc_pps *p_hevc_pps; -+ struct v4l2_ctrl_hevc_slice_params *p_hevc_slice_params; - struct v4l2_area *p_area; - void *p; - }; --- -2.23.0 - -From f8cca8c97a63d77f48334cde81d15014f43530ef Mon Sep 17 00:00:00 2001 -From: Hans Verkuil -Date: Fri, 11 Oct 2019 06:32:41 -0300 -Subject: [PATCH] media: v4l2-mem2mem: support held capture buffers - -Check for held buffers that are ready to be returned to vb2 in -__v4l2_m2m_try_queue(). This avoids drivers having to handle this -case. - -Add v4l2_m2m_buf_done_and_job_finish() to correctly return source -and destination buffers and mark the job as finished while taking -a held destination buffer into account (i.e. that buffer won't be -returned). This has to be done while job_spinlock is held to avoid -race conditions. - -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/v4l2-core/v4l2-mem2mem.c | 130 ++++++++++++++++++------- - include/media/v4l2-mem2mem.h | 33 ++++++- - 2 files changed, 128 insertions(+), 35 deletions(-) - -diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c -index 19937dd3c6f6..79c3656f24f7 100644 ---- a/drivers/media/v4l2-core/v4l2-mem2mem.c -+++ b/drivers/media/v4l2-core/v4l2-mem2mem.c -@@ -284,7 +284,8 @@ static void v4l2_m2m_try_run(struct v4l2_m2m_dev *m2m_dev) - static void __v4l2_m2m_try_queue(struct v4l2_m2m_dev *m2m_dev, - struct v4l2_m2m_ctx *m2m_ctx) - { -- unsigned long flags_job, flags_out, flags_cap; -+ unsigned long flags_job; -+ struct vb2_v4l2_buffer *dst, *src; - - dprintk("Trying to schedule a job for m2m_ctx: %p\n", m2m_ctx); - -@@ -307,20 +308,30 @@ static void __v4l2_m2m_try_queue(struct v4l2_m2m_dev *m2m_dev, - goto job_unlock; - } - -- spin_lock_irqsave(&m2m_ctx->out_q_ctx.rdy_spinlock, flags_out); -- if (list_empty(&m2m_ctx->out_q_ctx.rdy_queue) -- && !m2m_ctx->out_q_ctx.buffered) { -+ src = v4l2_m2m_next_src_buf(m2m_ctx); -+ dst = v4l2_m2m_next_dst_buf(m2m_ctx); -+ if (!src && !m2m_ctx->out_q_ctx.buffered) { - dprintk("No input buffers available\n"); -- goto out_unlock; -+ goto job_unlock; - } -- spin_lock_irqsave(&m2m_ctx->cap_q_ctx.rdy_spinlock, flags_cap); -- if (list_empty(&m2m_ctx->cap_q_ctx.rdy_queue) -- && !m2m_ctx->cap_q_ctx.buffered) { -+ if (!dst && !m2m_ctx->cap_q_ctx.buffered) { - dprintk("No output buffers available\n"); -- goto cap_unlock; -+ goto job_unlock; -+ } -+ -+ if (src && dst && -+ dst->is_held && dst->vb2_buf.copied_timestamp && -+ dst->vb2_buf.timestamp != src->vb2_buf.timestamp) { -+ dst->is_held = false; -+ v4l2_m2m_dst_buf_remove(m2m_ctx); -+ v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE); -+ dst = v4l2_m2m_next_dst_buf(m2m_ctx); -+ -+ if (!dst && !m2m_ctx->cap_q_ctx.buffered) { -+ dprintk("No output buffers available after returning held buffer\n"); -+ goto job_unlock; -+ } - } -- spin_unlock_irqrestore(&m2m_ctx->cap_q_ctx.rdy_spinlock, flags_cap); -- spin_unlock_irqrestore(&m2m_ctx->out_q_ctx.rdy_spinlock, flags_out); - - if (m2m_dev->m2m_ops->job_ready - && (!m2m_dev->m2m_ops->job_ready(m2m_ctx->priv))) { -@@ -331,13 +342,6 @@ static void __v4l2_m2m_try_queue(struct v4l2_m2m_dev *m2m_dev, - list_add_tail(&m2m_ctx->queue, &m2m_dev->job_queue); - m2m_ctx->job_flags |= TRANS_QUEUED; - -- spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags_job); -- return; -- --cap_unlock: -- spin_unlock_irqrestore(&m2m_ctx->cap_q_ctx.rdy_spinlock, flags_cap); --out_unlock: -- spin_unlock_irqrestore(&m2m_ctx->out_q_ctx.rdy_spinlock, flags_out); - job_unlock: - spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags_job); - } -@@ -412,37 +416,97 @@ static void v4l2_m2m_cancel_job(struct v4l2_m2m_ctx *m2m_ctx) - } - } - --void v4l2_m2m_job_finish(struct v4l2_m2m_dev *m2m_dev, -- struct v4l2_m2m_ctx *m2m_ctx) -+/* -+ * Schedule the next job, called from v4l2_m2m_job_finish() or -+ * v4l2_m2m_buf_done_and_job_finish(). -+ */ -+static void v4l2_m2m_schedule_next_job(struct v4l2_m2m_dev *m2m_dev, -+ struct v4l2_m2m_ctx *m2m_ctx) - { -- unsigned long flags; -+ /* -+ * This instance might have more buffers ready, but since we do not -+ * allow more than one job on the job_queue per instance, each has -+ * to be scheduled separately after the previous one finishes. -+ */ -+ __v4l2_m2m_try_queue(m2m_dev, m2m_ctx); - -- spin_lock_irqsave(&m2m_dev->job_spinlock, flags); -+ /* -+ * We might be running in atomic context, -+ * but the job must be run in non-atomic context. -+ */ -+ schedule_work(&m2m_dev->job_work); -+} -+ -+/* -+ * Assumes job_spinlock is held, called from v4l2_m2m_job_finish() or -+ * v4l2_m2m_buf_done_and_job_finish(). -+ */ -+static bool _v4l2_m2m_job_finish(struct v4l2_m2m_dev *m2m_dev, -+ struct v4l2_m2m_ctx *m2m_ctx) -+{ - if (!m2m_dev->curr_ctx || m2m_dev->curr_ctx != m2m_ctx) { -- spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags); - dprintk("Called by an instance not currently running\n"); -- return; -+ return false; - } - - list_del(&m2m_dev->curr_ctx->queue); - m2m_dev->curr_ctx->job_flags &= ~(TRANS_QUEUED | TRANS_RUNNING); - wake_up(&m2m_dev->curr_ctx->finished); - m2m_dev->curr_ctx = NULL; -+ return true; -+} - -- spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags); -- -- /* This instance might have more buffers ready, but since we do not -- * allow more than one job on the job_queue per instance, each has -- * to be scheduled separately after the previous one finishes. */ -- __v4l2_m2m_try_queue(m2m_dev, m2m_ctx); -+void v4l2_m2m_job_finish(struct v4l2_m2m_dev *m2m_dev, -+ struct v4l2_m2m_ctx *m2m_ctx) -+{ -+ unsigned long flags; -+ bool schedule_next; - -- /* We might be running in atomic context, -- * but the job must be run in non-atomic context. -+ /* -+ * This function should not be used for drivers that support -+ * holding capture buffers. Those should use -+ * v4l2_m2m_buf_done_and_job_finish() instead. - */ -- schedule_work(&m2m_dev->job_work); -+ WARN_ON(m2m_ctx->cap_q_ctx.q.subsystem_flags & -+ VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF); -+ spin_lock_irqsave(&m2m_dev->job_spinlock, flags); -+ schedule_next = _v4l2_m2m_job_finish(m2m_dev, m2m_ctx); -+ spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags); -+ -+ if (schedule_next) -+ v4l2_m2m_schedule_next_job(m2m_dev, m2m_ctx); - } - EXPORT_SYMBOL(v4l2_m2m_job_finish); - -+void v4l2_m2m_buf_done_and_job_finish(struct v4l2_m2m_dev *m2m_dev, -+ struct v4l2_m2m_ctx *m2m_ctx, -+ enum vb2_buffer_state state) -+{ -+ struct vb2_v4l2_buffer *src_buf, *dst_buf; -+ bool schedule_next = false; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&m2m_dev->job_spinlock, flags); -+ src_buf = v4l2_m2m_src_buf_remove(m2m_ctx); -+ dst_buf = v4l2_m2m_next_dst_buf(m2m_ctx); -+ -+ if (WARN_ON(!src_buf || !dst_buf)) -+ goto unlock; -+ v4l2_m2m_buf_done(src_buf, state); -+ dst_buf->is_held = src_buf->flags & V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF; -+ if (!dst_buf->is_held) { -+ v4l2_m2m_dst_buf_remove(m2m_ctx); -+ v4l2_m2m_buf_done(dst_buf, state); -+ } -+ schedule_next = _v4l2_m2m_job_finish(m2m_dev, m2m_ctx); -+unlock: -+ spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags); -+ -+ if (schedule_next) -+ v4l2_m2m_schedule_next_job(m2m_dev, m2m_ctx); -+} -+EXPORT_SYMBOL(v4l2_m2m_buf_done_and_job_finish); -+ - int v4l2_m2m_reqbufs(struct file *file, struct v4l2_m2m_ctx *m2m_ctx, - struct v4l2_requestbuffers *reqbufs) - { -diff --git a/include/media/v4l2-mem2mem.h b/include/media/v4l2-mem2mem.h -index 0b9c3a287061..229d9f5d4370 100644 ---- a/include/media/v4l2-mem2mem.h -+++ b/include/media/v4l2-mem2mem.h -@@ -21,7 +21,8 @@ - * callback. - * The job does NOT have to end before this callback returns - * (and it will be the usual case). When the job finishes, -- * v4l2_m2m_job_finish() has to be called. -+ * v4l2_m2m_job_finish() or v4l2_m2m_buf_done_and_job_finish() -+ * has to be called. - * @job_ready: optional. Should return 0 if the driver does not have a job - * fully prepared to run yet (i.e. it will not be able to finish a - * transaction without sleeping). If not provided, it will be -@@ -33,7 +34,8 @@ - * stop the device safely; e.g. in the next interrupt handler), - * even if the transaction would not have been finished by then. - * After the driver performs the necessary steps, it has to call -- * v4l2_m2m_job_finish() (as if the transaction ended normally). -+ * v4l2_m2m_job_finish() or v4l2_m2m_buf_done_and_job_finish() as -+ * if the transaction ended normally. - * This function does not have to (and will usually not) wait - * until the device enters a state when it can be stopped. - */ -@@ -173,6 +175,33 @@ void v4l2_m2m_try_schedule(struct v4l2_m2m_ctx *m2m_ctx); - void v4l2_m2m_job_finish(struct v4l2_m2m_dev *m2m_dev, - struct v4l2_m2m_ctx *m2m_ctx); - -+/** -+ * v4l2_m2m_buf_done_and_job_finish() - return source/destination buffers with -+ * state and inform the framework that a job has been finished and have it -+ * clean up -+ * -+ * @m2m_dev: opaque pointer to the internal data to handle M2M context -+ * @m2m_ctx: m2m context assigned to the instance given by struct &v4l2_m2m_ctx -+ * @state: vb2 buffer state passed to v4l2_m2m_buf_done(). -+ * -+ * Drivers that set V4L2_BUF_CAP_SUPPORTS_M2M_HOLD_CAPTURE_BUF must use this -+ * function instead of job_finish() to take held buffers into account. It is -+ * optional for other drivers. -+ * -+ * This function removes the source buffer from the ready list and returns -+ * it with the given state. The same is done for the destination buffer, unless -+ * it is marked 'held'. In that case the buffer is kept on the ready list. -+ * -+ * After that the job is finished (see job_finish()). -+ * -+ * This allows for multiple output buffers to be used to fill in a single -+ * capture buffer. This is typically used by stateless decoders where -+ * multiple e.g. H.264 slices contribute to a single decoded frame. -+ */ -+void v4l2_m2m_buf_done_and_job_finish(struct v4l2_m2m_dev *m2m_dev, -+ struct v4l2_m2m_ctx *m2m_ctx, -+ enum vb2_buffer_state state); -+ - static inline void - v4l2_m2m_buf_done(struct vb2_v4l2_buffer *buf, enum vb2_buffer_state state) - { --- -2.23.0 - -From bef41d93aac64b54c3008ca6170bec54f85784f5 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Fri, 11 Oct 2019 06:32:43 -0300 -Subject: [PATCH] media: v4l2-mem2mem: add stateless_(try_)decoder_cmd ioctl - helpers - -These helpers are used by stateless codecs when they support multiple -slices per frame and hold capture buffer flag is set. It's expected that -all such codecs will use this code. - -Signed-off-by: Jernej Skrabec -Co-developed-by: Hans Verkuil -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/v4l2-core/v4l2-mem2mem.c | 53 ++++++++++++++++++++++++++ - include/media/v4l2-mem2mem.h | 4 ++ - 2 files changed, 57 insertions(+) - -diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c -index 79c3656f24f7..b46d2c388349 100644 ---- a/drivers/media/v4l2-core/v4l2-mem2mem.c -+++ b/drivers/media/v4l2-core/v4l2-mem2mem.c -@@ -1218,6 +1218,59 @@ int v4l2_m2m_ioctl_try_decoder_cmd(struct file *file, void *fh, - } - EXPORT_SYMBOL_GPL(v4l2_m2m_ioctl_try_decoder_cmd); - -+int v4l2_m2m_ioctl_stateless_try_decoder_cmd(struct file *file, void *fh, -+ struct v4l2_decoder_cmd *dc) -+{ -+ if (dc->cmd != V4L2_DEC_CMD_FLUSH) -+ return -EINVAL; -+ -+ dc->flags = 0; -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(v4l2_m2m_ioctl_stateless_try_decoder_cmd); -+ -+int v4l2_m2m_ioctl_stateless_decoder_cmd(struct file *file, void *priv, -+ struct v4l2_decoder_cmd *dc) -+{ -+ struct v4l2_fh *fh = file->private_data; -+ struct vb2_v4l2_buffer *out_vb, *cap_vb; -+ struct v4l2_m2m_dev *m2m_dev = fh->m2m_ctx->m2m_dev; -+ unsigned long flags; -+ int ret; -+ -+ ret = v4l2_m2m_ioctl_stateless_try_decoder_cmd(file, priv, dc); -+ if (ret < 0) -+ return ret; -+ -+ spin_lock_irqsave(&m2m_dev->job_spinlock, flags); -+ out_vb = v4l2_m2m_last_src_buf(fh->m2m_ctx); -+ cap_vb = v4l2_m2m_last_dst_buf(fh->m2m_ctx); -+ -+ /* -+ * If there is an out buffer pending, then clear any HOLD flag. -+ * -+ * By clearing this flag we ensure that when this output -+ * buffer is processed any held capture buffer will be released. -+ */ -+ if (out_vb) { -+ out_vb->flags &= ~V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF; -+ } else if (cap_vb && cap_vb->is_held) { -+ /* -+ * If there were no output buffers, but there is a -+ * capture buffer that is held, then release that -+ * buffer. -+ */ -+ cap_vb->is_held = false; -+ v4l2_m2m_dst_buf_remove(fh->m2m_ctx); -+ v4l2_m2m_buf_done(cap_vb, VB2_BUF_STATE_DONE); -+ } -+ spin_unlock_irqrestore(&m2m_dev->job_spinlock, flags); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(v4l2_m2m_ioctl_stateless_decoder_cmd); -+ - /* - * v4l2_file_operations helpers. It is assumed here same lock is used - * for the output and the capture buffer queue. -diff --git a/include/media/v4l2-mem2mem.h b/include/media/v4l2-mem2mem.h -index 229d9f5d4370..3d9e48ed8817 100644 ---- a/include/media/v4l2-mem2mem.h -+++ b/include/media/v4l2-mem2mem.h -@@ -701,6 +701,10 @@ int v4l2_m2m_ioctl_try_encoder_cmd(struct file *file, void *fh, - struct v4l2_encoder_cmd *ec); - int v4l2_m2m_ioctl_try_decoder_cmd(struct file *file, void *fh, - struct v4l2_decoder_cmd *dc); -+int v4l2_m2m_ioctl_stateless_try_decoder_cmd(struct file *file, void *fh, -+ struct v4l2_decoder_cmd *dc); -+int v4l2_m2m_ioctl_stateless_decoder_cmd(struct file *file, void *priv, -+ struct v4l2_decoder_cmd *dc); - int v4l2_m2m_fop_mmap(struct file *file, struct vm_area_struct *vma); - __poll_t v4l2_m2m_fop_poll(struct file *file, poll_table *wait); - --- -2.23.0 - -From f07602ac388723233e9e3c5a05b54baf34e0a3e9 Mon Sep 17 00:00:00 2001 -From: Hans Verkuil -Date: Fri, 11 Oct 2019 06:32:44 -0300 -Subject: [PATCH] media: v4l2-mem2mem: add new_frame detection - -Drivers that support VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF -typically want to know if a new frame is started (i.e. the first -slice is about to be processed). Add a new_frame bool to v4l2_m2m_ctx -and set it accordingly. - -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/media/v4l2-core/v4l2-mem2mem.c | 11 +++++++++-- - include/media/v4l2-mem2mem.h | 7 +++++++ - 2 files changed, 16 insertions(+), 2 deletions(-) - -diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c -index b46d2c388349..db07ef3bf3d0 100644 ---- a/drivers/media/v4l2-core/v4l2-mem2mem.c -+++ b/drivers/media/v4l2-core/v4l2-mem2mem.c -@@ -319,8 +319,10 @@ static void __v4l2_m2m_try_queue(struct v4l2_m2m_dev *m2m_dev, - goto job_unlock; - } - -- if (src && dst && -- dst->is_held && dst->vb2_buf.copied_timestamp && -+ m2m_ctx->new_frame = true; -+ -+ if (src && dst && dst->is_held && -+ dst->vb2_buf.copied_timestamp && - dst->vb2_buf.timestamp != src->vb2_buf.timestamp) { - dst->is_held = false; - v4l2_m2m_dst_buf_remove(m2m_ctx); -@@ -333,6 +335,11 @@ static void __v4l2_m2m_try_queue(struct v4l2_m2m_dev *m2m_dev, - } - } - -+ if (src && dst && (m2m_ctx->cap_q_ctx.q.subsystem_flags & -+ VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF)) -+ m2m_ctx->new_frame = !dst->vb2_buf.copied_timestamp || -+ dst->vb2_buf.timestamp != src->vb2_buf.timestamp; -+ - if (m2m_dev->m2m_ops->job_ready - && (!m2m_dev->m2m_ops->job_ready(m2m_ctx->priv))) { - dprintk("Driver not ready\n"); -diff --git a/include/media/v4l2-mem2mem.h b/include/media/v4l2-mem2mem.h -index 3d9e48ed8817..1d85e24791e4 100644 ---- a/include/media/v4l2-mem2mem.h -+++ b/include/media/v4l2-mem2mem.h -@@ -75,6 +75,11 @@ struct v4l2_m2m_queue_ctx { - * struct v4l2_m2m_ctx - Memory to memory context structure - * - * @q_lock: struct &mutex lock -+ * @new_frame: valid in the device_run callback: if true, then this -+ * starts a new frame; if false, then this is a new slice -+ * for an existing frame. This is always true unless -+ * V4L2_BUF_CAP_SUPPORTS_M2M_HOLD_CAPTURE_BUF is set, which -+ * indicates slicing support. - * @m2m_dev: opaque pointer to the internal data to handle M2M context - * @cap_q_ctx: Capture (output to memory) queue context - * @out_q_ctx: Output (input from memory) queue context -@@ -91,6 +96,8 @@ struct v4l2_m2m_ctx { - /* optional cap/out vb2 queues lock */ - struct mutex *q_lock; - -+ bool new_frame; -+ - /* internal use only */ - struct v4l2_m2m_dev *m2m_dev; - --- -2.23.0 - -From dec555256f2cb61ee94975727ec2d4a8d592ac92 Mon Sep 17 00:00:00 2001 -From: Hans Verkuil -Date: Fri, 30 Aug 2019 06:26:23 -0300 -Subject: [PATCH] media: cedrus: choose default pixelformat in try_fmt - -If an unsupported pixelformat is passed to try_fmt, then pick -the first valid pixelformat instead. This is more standard V4L2 -behavior. - -Signed-off-by: Hans Verkuil -Reviewed-by: Jernej Skrabec -Signed-off-by: Mauro Carvalho Chehab ---- - .../staging/media/sunxi/cedrus/cedrus_video.c | 46 ++++++++----------- - 1 file changed, 20 insertions(+), 26 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index eeee3efd247b..d69c9bcdb8e2 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -62,33 +62,30 @@ static inline struct cedrus_ctx *cedrus_file2ctx(struct file *file) - static struct cedrus_format *cedrus_find_format(u32 pixelformat, u32 directions, - unsigned int capabilities) - { -+ struct cedrus_format *first_valid_fmt = NULL; - struct cedrus_format *fmt; - unsigned int i; - - for (i = 0; i < CEDRUS_FORMATS_COUNT; i++) { - fmt = &cedrus_formats[i]; - -- if (fmt->capabilities && (fmt->capabilities & capabilities) != -- fmt->capabilities) -+ if ((fmt->capabilities & capabilities) != fmt->capabilities || -+ !(fmt->directions & directions)) - continue; - -- if (fmt->pixelformat == pixelformat && -- (fmt->directions & directions) != 0) -+ if (fmt->pixelformat == pixelformat) - break; -+ -+ if (!first_valid_fmt) -+ first_valid_fmt = fmt; - } - - if (i == CEDRUS_FORMATS_COUNT) -- return NULL; -+ return first_valid_fmt; - - return &cedrus_formats[i]; - } - --static bool cedrus_check_format(u32 pixelformat, u32 directions, -- unsigned int capabilities) --{ -- return cedrus_find_format(pixelformat, directions, capabilities); --} -- - static void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt) - { - unsigned int width = pix_fmt->width; -@@ -252,11 +249,14 @@ static int cedrus_try_fmt_vid_cap(struct file *file, void *priv, - struct cedrus_ctx *ctx = cedrus_file2ctx(file); - struct cedrus_dev *dev = ctx->dev; - struct v4l2_pix_format *pix_fmt = &f->fmt.pix; -+ struct cedrus_format *fmt = -+ cedrus_find_format(pix_fmt->pixelformat, CEDRUS_DECODE_DST, -+ dev->capabilities); - -- if (!cedrus_check_format(pix_fmt->pixelformat, CEDRUS_DECODE_DST, -- dev->capabilities)) -+ if (!fmt) - return -EINVAL; - -+ pix_fmt->pixelformat = fmt->pixelformat; - cedrus_prepare_format(pix_fmt); - - return 0; -@@ -268,15 +268,18 @@ static int cedrus_try_fmt_vid_out(struct file *file, void *priv, - struct cedrus_ctx *ctx = cedrus_file2ctx(file); - struct cedrus_dev *dev = ctx->dev; - struct v4l2_pix_format *pix_fmt = &f->fmt.pix; -+ struct cedrus_format *fmt = -+ cedrus_find_format(pix_fmt->pixelformat, CEDRUS_DECODE_SRC, -+ dev->capabilities); - -- if (!cedrus_check_format(pix_fmt->pixelformat, CEDRUS_DECODE_SRC, -- dev->capabilities)) -+ if (!fmt) - return -EINVAL; - - /* Source image size has to be provided by userspace. */ - if (pix_fmt->sizeimage == 0) - return -EINVAL; - -+ pix_fmt->pixelformat = fmt->pixelformat; - cedrus_prepare_format(pix_fmt); - - return 0; -@@ -364,21 +367,12 @@ static int cedrus_queue_setup(struct vb2_queue *vq, unsigned int *nbufs, - struct device *alloc_devs[]) - { - struct cedrus_ctx *ctx = vb2_get_drv_priv(vq); -- struct cedrus_dev *dev = ctx->dev; - struct v4l2_pix_format *pix_fmt; -- u32 directions; - -- if (V4L2_TYPE_IS_OUTPUT(vq->type)) { -- directions = CEDRUS_DECODE_SRC; -+ if (V4L2_TYPE_IS_OUTPUT(vq->type)) - pix_fmt = &ctx->src_fmt; -- } else { -- directions = CEDRUS_DECODE_DST; -+ else - pix_fmt = &ctx->dst_fmt; -- } -- -- if (!cedrus_check_format(pix_fmt->pixelformat, directions, -- dev->capabilities)) -- return -EINVAL; - - if (*nplanes) { - if (sizes[0] < pix_fmt->sizeimage) --- -2.23.0 - -From 965c71e8adcff315e16b58c00cd312598fc0222c Mon Sep 17 00:00:00 2001 -From: Hans Verkuil -Date: Fri, 30 Aug 2019 06:26:24 -0300 -Subject: [PATCH] media: cedrus: fix various format-related compliance issues - -Initialize the context on open() with valid capture and output -formats. It is good practice to always have valid formats internally. - -This solves one vb2 warning in the kernel log where the sizeimage -value of the output format was 0 when requesting buffers, which is -not allowed. - -It also simplifies the g_fmt ioctl implementations since they no longer -have to check if a valid format was ever set. - -cedrus_prepare_format() now also validates sizeimage for the output -formats, ensuring userspace can't set it to 0 since that would cause -the same vb2 warning. - -Finally remove the sizeimage == 0 check in cedrus_try_fmt_vid_out() -since cedrus_prepare_format() will now adjust this value. - -Signed-off-by: Hans Verkuil -Reviewed-by: Jernej Skrabec -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/sunxi/cedrus/cedrus.c | 10 +++++++ - .../staging/media/sunxi/cedrus/cedrus_video.c | 28 ++----------------- - .../staging/media/sunxi/cedrus/cedrus_video.h | 1 + - 3 files changed, 14 insertions(+), 25 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c -index 3439f6ad6338..0cf637c8a1e3 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -241,6 +241,16 @@ static int cedrus_open(struct file *file) - ret = PTR_ERR(ctx->fh.m2m_ctx); - goto err_ctrls; - } -+ ctx->dst_fmt.pixelformat = V4L2_PIX_FMT_SUNXI_TILED_NV12; -+ cedrus_prepare_format(&ctx->dst_fmt); -+ ctx->src_fmt.pixelformat = V4L2_PIX_FMT_MPEG2_SLICE; -+ /* -+ * TILED_NV12 has more strict requirements, so copy the width and -+ * height to src_fmt to ensure that is matches the dst_fmt resolution. -+ */ -+ ctx->src_fmt.width = ctx->dst_fmt.width; -+ ctx->src_fmt.height = ctx->dst_fmt.height; -+ cedrus_prepare_format(&ctx->src_fmt); - - v4l2_fh_add(&ctx->fh); - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index d69c9bcdb8e2..3ec3a2db790c 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -86,7 +86,7 @@ static struct cedrus_format *cedrus_find_format(u32 pixelformat, u32 directions, - return &cedrus_formats[i]; - } - --static void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt) -+void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt) - { - unsigned int width = pix_fmt->width; - unsigned int height = pix_fmt->height; -@@ -104,7 +104,8 @@ static void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt) - case V4L2_PIX_FMT_H264_SLICE: - /* Zero bytes per line for encoded source. */ - bytesperline = 0; -- -+ /* Choose some minimum size since this can't be 0 */ -+ sizeimage = max_t(u32, SZ_1K, sizeimage); - break; - - case V4L2_PIX_FMT_SUNXI_TILED_NV12: -@@ -211,16 +212,7 @@ static int cedrus_g_fmt_vid_cap(struct file *file, void *priv, - { - struct cedrus_ctx *ctx = cedrus_file2ctx(file); - -- /* Fall back to dummy default by lack of hardware configuration. */ -- if (!ctx->dst_fmt.width || !ctx->dst_fmt.height) { -- f->fmt.pix.pixelformat = V4L2_PIX_FMT_SUNXI_TILED_NV12; -- cedrus_prepare_format(&f->fmt.pix); -- -- return 0; -- } -- - f->fmt.pix = ctx->dst_fmt; -- - return 0; - } - -@@ -229,17 +221,7 @@ static int cedrus_g_fmt_vid_out(struct file *file, void *priv, - { - struct cedrus_ctx *ctx = cedrus_file2ctx(file); - -- /* Fall back to dummy default by lack of hardware configuration. */ -- if (!ctx->dst_fmt.width || !ctx->dst_fmt.height) { -- f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG2_SLICE; -- f->fmt.pix.sizeimage = SZ_1K; -- cedrus_prepare_format(&f->fmt.pix); -- -- return 0; -- } -- - f->fmt.pix = ctx->src_fmt; -- - return 0; - } - -@@ -275,10 +257,6 @@ static int cedrus_try_fmt_vid_out(struct file *file, void *priv, - if (!fmt) - return -EINVAL; - -- /* Source image size has to be provided by userspace. */ -- if (pix_fmt->sizeimage == 0) -- return -EINVAL; -- - pix_fmt->pixelformat = fmt->pixelformat; - cedrus_prepare_format(pix_fmt); - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.h b/drivers/staging/media/sunxi/cedrus/cedrus_video.h -index 0e4f7a8cccf2..05050c0a0921 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_video.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.h -@@ -26,5 +26,6 @@ extern const struct v4l2_ioctl_ops cedrus_ioctl_ops; - - int cedrus_queue_init(void *priv, struct vb2_queue *src_vq, - struct vb2_queue *dst_vq); -+void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt); - - #endif --- -2.23.0 - -From eabf10e5e3009e0c7e9a9b98a7f8299e690bcc55 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Fri, 11 Oct 2019 06:32:45 -0300 -Subject: [PATCH] media: cedrus: h264: Support multiple slices per frame - -With recent changes, support for decoding multi-slice frames can be -easily added now. - -Signal VPU if current slice is first in frame or not and add information -about first macroblock coordinates. - -When frame contains multiple slices and driver works in slice mode, it's -more efficient to hold capture buffer in queue until all slices of a -same frame are decoded. - -Add support for that to Cedrus driver by exposing and implementing -V4L2_BUF_CAP_SUPPORTS_M2M_HOLD_CAPTURE_BUF capability. - -Signed-off-by: Jernej Skrabec -[hverkuil-cisco@xs4all.nl: rewritten to use v4l2_m2m_buf_done_and_job_finish] -[hverkuil-cisco@xs4all.nl: removed unnecessary (u32) cast] -[hverkuil-cisco@xs4all.nl: use new_frame v4l2_m2m_ctx bool] -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 12 +++++++++++- - drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 16 ++-------------- - .../staging/media/sunxi/cedrus/cedrus_video.c | 14 ++++++++++++++ - 3 files changed, 27 insertions(+), 15 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -index d6a782703c9b..cd85668f9c80 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -@@ -301,6 +301,8 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, - dma_addr_t src_buf_addr; - u32 offset = slice->header_bit_size; - u32 len = (slice->size * 8) - offset; -+ unsigned int pic_width_in_mbs; -+ bool mbaff_pic; - u32 reg; - - cedrus_write(dev, VE_H264_VLD_LEN, len); -@@ -370,12 +372,20 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, - reg |= VE_H264_SPS_DIRECT_8X8_INFERENCE; - cedrus_write(dev, VE_H264_SPS, reg); - -+ mbaff_pic = !(slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) && -+ (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD); -+ pic_width_in_mbs = sps->pic_width_in_mbs_minus1 + 1; -+ - // slice parameters - reg = 0; -+ reg |= ((slice->first_mb_in_slice % pic_width_in_mbs) & 0xff) << 24; -+ reg |= (((slice->first_mb_in_slice / pic_width_in_mbs) * -+ (mbaff_pic + 1)) & 0xff) << 16; - reg |= decode->nal_ref_idc ? BIT(12) : 0; - reg |= (slice->slice_type & 0xf) << 8; - reg |= slice->cabac_init_idc & 0x3; -- reg |= VE_H264_SHS_FIRST_SLICE_IN_PIC; -+ if (ctx->fh.m2m_ctx->new_frame) -+ reg |= VE_H264_SHS_FIRST_SLICE_IN_PIC; - if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) - reg |= VE_H264_SHS_FIELD_PIC; - if (slice->flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -index a942cd9bed57..e7e18424bab1 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -@@ -103,7 +103,6 @@ static irqreturn_t cedrus_irq(int irq, void *data) - { - struct cedrus_dev *dev = data; - struct cedrus_ctx *ctx; -- struct vb2_v4l2_buffer *src_buf, *dst_buf; - enum vb2_buffer_state state; - enum cedrus_irq_status status; - -@@ -121,24 +120,13 @@ static irqreturn_t cedrus_irq(int irq, void *data) - dev->dec_ops[ctx->current_codec]->irq_disable(ctx); - dev->dec_ops[ctx->current_codec]->irq_clear(ctx); - -- src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); -- dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); -- -- if (!src_buf || !dst_buf) { -- v4l2_err(&dev->v4l2_dev, -- "Missing source and/or destination buffers\n"); -- return IRQ_HANDLED; -- } -- - if (status == CEDRUS_IRQ_ERROR) - state = VB2_BUF_STATE_ERROR; - else - state = VB2_BUF_STATE_DONE; - -- v4l2_m2m_buf_done(src_buf, state); -- v4l2_m2m_buf_done(dst_buf, state); -- -- v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx); -+ v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx, -+ state); - - return IRQ_HANDLED; - } -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index 3ec3a2db790c..f745f66c4440 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -303,6 +303,17 @@ static int cedrus_s_fmt_vid_out(struct file *file, void *priv, - - ctx->src_fmt = f->fmt.pix; - -+ switch (ctx->src_fmt.pixelformat) { -+ case V4L2_PIX_FMT_H264_SLICE: -+ vq->subsystem_flags |= -+ VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF; -+ break; -+ default: -+ vq->subsystem_flags &= -+ ~VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF; -+ break; -+ } -+ - /* Propagate colorspace information to capture. */ - ctx->dst_fmt.colorspace = f->fmt.pix.colorspace; - ctx->dst_fmt.xfer_func = f->fmt.pix.xfer_func; -@@ -336,6 +347,9 @@ const struct v4l2_ioctl_ops cedrus_ioctl_ops = { - .vidioc_streamon = v4l2_m2m_ioctl_streamon, - .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, - -+ .vidioc_try_decoder_cmd = v4l2_m2m_ioctl_stateless_try_decoder_cmd, -+ .vidioc_decoder_cmd = v4l2_m2m_ioctl_stateless_decoder_cmd, -+ - .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, - .vidioc_unsubscribe_event = v4l2_event_unsubscribe, - }; --- -2.23.0 - -From c3b32900fbf5178473c6b39260e891e19067edc2 Mon Sep 17 00:00:00 2001 -From: Paul Kocialkowski -Date: Tue, 22 Oct 2019 12:26:51 -0300 -Subject: [PATCH] media: cedrus: Remove unnecessary parenthesis around - DIV_ROUND_UP - -DIV_ROUND_UP's first argument doesn't need to be wrapped in parenthesis -since that is already being taken care of in the macro's definition. - -Signed-off-by: Paul Kocialkowski -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/sunxi/cedrus/cedrus_regs.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -index f9dd8cbf3458..21676a1797f1 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -@@ -101,9 +101,9 @@ - #define VE_DEC_MPEG_PICCODEDSIZE (VE_ENGINE_DEC_MPEG + 0x08) - - #define VE_DEC_MPEG_PICCODEDSIZE_WIDTH(w) \ -- SHIFT_AND_MASK_BITS(DIV_ROUND_UP((w), 16), 15, 8) -+ SHIFT_AND_MASK_BITS(DIV_ROUND_UP(w, 16), 15, 8) - #define VE_DEC_MPEG_PICCODEDSIZE_HEIGHT(h) \ -- SHIFT_AND_MASK_BITS(DIV_ROUND_UP((h), 16), 7, 0) -+ SHIFT_AND_MASK_BITS(DIV_ROUND_UP(h, 16), 7, 0) - - #define VE_DEC_MPEG_PICBOUNDSIZE (VE_ENGINE_DEC_MPEG + 0x0c) - --- -2.23.0 - -From 86caab29da78961d73e489554c8b2573fae523d5 Mon Sep 17 00:00:00 2001 -From: Paul Kocialkowski -Date: Tue, 22 Oct 2019 12:26:54 -0300 -Subject: [PATCH] media: cedrus: Add HEVC/H.265 decoding support - -This introduces support for HEVC/H.265 to the Cedrus VPU driver, with -both uni-directional and bi-directional prediction modes supported. - -Field-coded (interlaced) pictures, custom quantization matrices and -10-bit output are not supported at this point. - -Signed-off-by: Paul Kocialkowski -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/sunxi/cedrus/Makefile | 2 +- - drivers/staging/media/sunxi/cedrus/cedrus.c | 52 +- - drivers/staging/media/sunxi/cedrus/cedrus.h | 18 + - .../staging/media/sunxi/cedrus/cedrus_dec.c | 9 + - .../staging/media/sunxi/cedrus/cedrus_h265.c | 616 ++++++++++++++++++ - .../staging/media/sunxi/cedrus/cedrus_hw.c | 4 + - .../staging/media/sunxi/cedrus/cedrus_regs.h | 271 ++++++++ - .../staging/media/sunxi/cedrus/cedrus_video.c | 10 + - 8 files changed, 977 insertions(+), 5 deletions(-) - create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_h265.c - -diff --git a/drivers/staging/media/sunxi/cedrus/Makefile b/drivers/staging/media/sunxi/cedrus/Makefile -index c85ac6db0302..1bce49d3e7e2 100644 ---- a/drivers/staging/media/sunxi/cedrus/Makefile -+++ b/drivers/staging/media/sunxi/cedrus/Makefile -@@ -2,4 +2,4 @@ - obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += sunxi-cedrus.o - - sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o \ -- cedrus_mpeg2.o cedrus_h264.o -+ cedrus_mpeg2.o cedrus_h264.o cedrus_h265.o -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c -index 0cf637c8a1e3..c6ddd46eff82 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -95,6 +95,45 @@ static const struct cedrus_control cedrus_controls[] = { - .codec = CEDRUS_CODEC_H264, - .required = false, - }, -+ { -+ .cfg = { -+ .id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, -+ }, -+ .codec = CEDRUS_CODEC_H265, -+ .required = true, -+ }, -+ { -+ .cfg = { -+ .id = V4L2_CID_MPEG_VIDEO_HEVC_PPS, -+ }, -+ .codec = CEDRUS_CODEC_H265, -+ .required = true, -+ }, -+ { -+ .cfg = { -+ .id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS, -+ }, -+ .codec = CEDRUS_CODEC_H265, -+ .required = true, -+ }, -+ { -+ .cfg = { -+ .id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE, -+ .max = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED, -+ .def = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED, -+ }, -+ .codec = CEDRUS_CODEC_H265, -+ .required = false, -+ }, -+ { -+ .cfg = { -+ .id = V4L2_CID_MPEG_VIDEO_HEVC_START_CODE, -+ .max = V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE, -+ .def = V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE, -+ }, -+ .codec = CEDRUS_CODEC_H265, -+ .required = false, -+ }, - }; - - #define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls) -@@ -340,6 +379,7 @@ static int cedrus_probe(struct platform_device *pdev) - - dev->dec_ops[CEDRUS_CODEC_MPEG2] = &cedrus_dec_ops_mpeg2; - dev->dec_ops[CEDRUS_CODEC_H264] = &cedrus_dec_ops_h264; -+ dev->dec_ops[CEDRUS_CODEC_H265] = &cedrus_dec_ops_h265; - - mutex_init(&dev->dev_mutex); - -@@ -450,22 +490,26 @@ static const struct cedrus_variant sun8i_a33_cedrus_variant = { - }; - - static const struct cedrus_variant sun8i_h3_cedrus_variant = { -- .capabilities = CEDRUS_CAPABILITY_UNTILED, -+ .capabilities = CEDRUS_CAPABILITY_UNTILED | -+ CEDRUS_CAPABILITY_H265_DEC, - .mod_rate = 402000000, - }; - - static const struct cedrus_variant sun50i_a64_cedrus_variant = { -- .capabilities = CEDRUS_CAPABILITY_UNTILED, -+ .capabilities = CEDRUS_CAPABILITY_UNTILED | -+ CEDRUS_CAPABILITY_H265_DEC, - .mod_rate = 402000000, - }; - - static const struct cedrus_variant sun50i_h5_cedrus_variant = { -- .capabilities = CEDRUS_CAPABILITY_UNTILED, -+ .capabilities = CEDRUS_CAPABILITY_UNTILED | -+ CEDRUS_CAPABILITY_H265_DEC, - .mod_rate = 402000000, - }; - - static const struct cedrus_variant sun50i_h6_cedrus_variant = { -- .capabilities = CEDRUS_CAPABILITY_UNTILED, -+ .capabilities = CEDRUS_CAPABILITY_UNTILED | -+ CEDRUS_CAPABILITY_H265_DEC, - .quirks = CEDRUS_QUIRK_NO_DMA_OFFSET, - .mod_rate = 600000000, - }; -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index 2f017a651848..986e059e3202 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -27,12 +27,14 @@ - #define CEDRUS_NAME "cedrus" - - #define CEDRUS_CAPABILITY_UNTILED BIT(0) -+#define CEDRUS_CAPABILITY_H265_DEC BIT(1) - - #define CEDRUS_QUIRK_NO_DMA_OFFSET BIT(0) - - enum cedrus_codec { - CEDRUS_CODEC_MPEG2, - CEDRUS_CODEC_H264, -+ CEDRUS_CODEC_H265, - CEDRUS_CODEC_LAST, - }; - -@@ -67,6 +69,12 @@ struct cedrus_mpeg2_run { - const struct v4l2_ctrl_mpeg2_quantization *quantization; - }; - -+struct cedrus_h265_run { -+ const struct v4l2_ctrl_hevc_sps *sps; -+ const struct v4l2_ctrl_hevc_pps *pps; -+ const struct v4l2_ctrl_hevc_slice_params *slice_params; -+}; -+ - struct cedrus_run { - struct vb2_v4l2_buffer *src; - struct vb2_v4l2_buffer *dst; -@@ -74,6 +82,7 @@ struct cedrus_run { - union { - struct cedrus_h264_run h264; - struct cedrus_mpeg2_run mpeg2; -+ struct cedrus_h265_run h265; - }; - }; - -@@ -110,6 +119,14 @@ struct cedrus_ctx { - void *neighbor_info_buf; - dma_addr_t neighbor_info_buf_dma; - } h264; -+ struct { -+ void *mv_col_buf; -+ dma_addr_t mv_col_buf_addr; -+ ssize_t mv_col_buf_size; -+ ssize_t mv_col_buf_unit_size; -+ void *neighbor_info_buf; -+ dma_addr_t neighbor_info_buf_addr; -+ } h265; - } codec; - }; - -@@ -155,6 +172,7 @@ struct cedrus_dev { - - extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2; - extern struct cedrus_dec_ops cedrus_dec_ops_h264; -+extern struct cedrus_dec_ops cedrus_dec_ops_h265; - - static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val) - { -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -index 56ca4c9ad01c..4a2fc33a1d79 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -@@ -59,6 +59,15 @@ void cedrus_device_run(void *priv) - V4L2_CID_MPEG_VIDEO_H264_SPS); - break; - -+ case V4L2_PIX_FMT_HEVC_SLICE: -+ run.h265.sps = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_HEVC_SPS); -+ run.h265.pps = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_HEVC_PPS); -+ run.h265.slice_params = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS); -+ break; -+ - default: - break; - } -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -new file mode 100644 -index 000000000000..9bc921866f70 ---- /dev/null -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -@@ -0,0 +1,616 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Cedrus VPU driver -+ * -+ * Copyright (C) 2013 Jens Kuske -+ * Copyright (C) 2018 Paul Kocialkowski -+ * Copyright (C) 2018 Bootlin -+ */ -+ -+#include -+ -+#include -+ -+#include "cedrus.h" -+#include "cedrus_hw.h" -+#include "cedrus_regs.h" -+ -+/* -+ * These are the sizes for side buffers required by the hardware for storing -+ * internal decoding metadata. They match the values used by the early BSP -+ * implementations, that were initially exposed in libvdpau-sunxi. -+ * Subsequent BSP implementations seem to double the neighbor info buffer size -+ * for the H6 SoC, which may be related to 10 bit H265 support. -+ */ -+#define CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE (397 * SZ_1K) -+#define CEDRUS_H265_ENTRY_POINTS_BUF_SIZE (4 * SZ_1K) -+#define CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE 160 -+ -+struct cedrus_h265_sram_frame_info { -+ __le32 top_pic_order_cnt; -+ __le32 bottom_pic_order_cnt; -+ __le32 top_mv_col_buf_addr; -+ __le32 bottom_mv_col_buf_addr; -+ __le32 luma_addr; -+ __le32 chroma_addr; -+} __packed; -+ -+struct cedrus_h265_sram_pred_weight { -+ __s8 delta_weight; -+ __s8 offset; -+} __packed; -+ -+static enum cedrus_irq_status cedrus_h265_irq_status(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ u32 reg; -+ -+ reg = cedrus_read(dev, VE_DEC_H265_STATUS); -+ reg &= VE_DEC_H265_STATUS_CHECK_MASK; -+ -+ if (reg & VE_DEC_H265_STATUS_CHECK_ERROR || -+ !(reg & VE_DEC_H265_STATUS_SUCCESS)) -+ return CEDRUS_IRQ_ERROR; -+ -+ return CEDRUS_IRQ_OK; -+} -+ -+static void cedrus_h265_irq_clear(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_write(dev, VE_DEC_H265_STATUS, VE_DEC_H265_STATUS_CHECK_MASK); -+} -+ -+static void cedrus_h265_irq_disable(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ u32 reg = cedrus_read(dev, VE_DEC_H265_CTRL); -+ -+ reg &= ~VE_DEC_H265_CTRL_IRQ_MASK; -+ -+ cedrus_write(dev, VE_DEC_H265_CTRL, reg); -+} -+ -+static void cedrus_h265_sram_write_offset(struct cedrus_dev *dev, u32 offset) -+{ -+ cedrus_write(dev, VE_DEC_H265_SRAM_OFFSET, offset); -+} -+ -+static void cedrus_h265_sram_write_data(struct cedrus_dev *dev, void *data, -+ unsigned int size) -+{ -+ u32 *word = data; -+ -+ while (size >= sizeof(u32)) { -+ cedrus_write(dev, VE_DEC_H265_SRAM_DATA, *word++); -+ size -= sizeof(u32); -+ } -+} -+ -+static inline dma_addr_t -+cedrus_h265_frame_info_mv_col_buf_addr(struct cedrus_ctx *ctx, -+ unsigned int index, unsigned int field) -+{ -+ return ctx->codec.h265.mv_col_buf_addr + index * -+ ctx->codec.h265.mv_col_buf_unit_size + -+ field * ctx->codec.h265.mv_col_buf_unit_size / 2; -+} -+ -+static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx, -+ unsigned int index, -+ bool field_pic, -+ u32 pic_order_cnt[], -+ int buffer_index) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ dma_addr_t dst_luma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 0); -+ dma_addr_t dst_chroma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 1); -+ dma_addr_t mv_col_buf_addr[2] = { -+ cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, 0), -+ cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, -+ field_pic ? 1 : 0) -+ }; -+ u32 offset = VE_DEC_H265_SRAM_OFFSET_FRAME_INFO + -+ VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT * index; -+ struct cedrus_h265_sram_frame_info frame_info = { -+ .top_pic_order_cnt = cpu_to_le32(pic_order_cnt[0]), -+ .bottom_pic_order_cnt = cpu_to_le32(field_pic ? -+ pic_order_cnt[1] : -+ pic_order_cnt[0]), -+ .top_mv_col_buf_addr = -+ cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0])), -+ .bottom_mv_col_buf_addr = cpu_to_le32(field_pic ? -+ VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[1]) : -+ VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0])), -+ .luma_addr = cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_luma_addr)), -+ .chroma_addr = cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_chroma_addr)), -+ }; -+ -+ cedrus_h265_sram_write_offset(dev, offset); -+ cedrus_h265_sram_write_data(dev, &frame_info, sizeof(frame_info)); -+} -+ -+static void cedrus_h265_frame_info_write_dpb(struct cedrus_ctx *ctx, -+ const struct v4l2_hevc_dpb_entry *dpb, -+ u8 num_active_dpb_entries) -+{ -+ struct vb2_queue *vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, -+ V4L2_BUF_TYPE_VIDEO_CAPTURE); -+ unsigned int i; -+ -+ for (i = 0; i < num_active_dpb_entries; i++) { -+ int buffer_index = vb2_find_timestamp(vq, dpb[i].timestamp, 0); -+ u32 pic_order_cnt[2] = { -+ dpb[i].pic_order_cnt[0], -+ dpb[i].pic_order_cnt[1] -+ }; -+ -+ cedrus_h265_frame_info_write_single(ctx, i, dpb[i].field_pic, -+ pic_order_cnt, -+ buffer_index); -+ } -+} -+ -+static void cedrus_h265_ref_pic_list_write(struct cedrus_dev *dev, -+ const struct v4l2_hevc_dpb_entry *dpb, -+ const u8 list[], -+ u8 num_ref_idx_active, -+ u32 sram_offset) -+{ -+ unsigned int i; -+ u32 word = 0; -+ -+ cedrus_h265_sram_write_offset(dev, sram_offset); -+ -+ for (i = 0; i < num_ref_idx_active; i++) { -+ unsigned int shift = (i % 4) * 8; -+ unsigned int index = list[i]; -+ u8 value = list[i]; -+ -+ if (dpb[index].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR) -+ value |= VE_DEC_H265_SRAM_REF_PIC_LIST_LT_REF; -+ -+ /* Each SRAM word gathers up to 4 references. */ -+ word |= value << shift; -+ -+ /* Write the word to SRAM and clear it for the next batch. */ -+ if ((i % 4) == 3 || i == (num_ref_idx_active - 1)) { -+ cedrus_h265_sram_write_data(dev, &word, sizeof(word)); -+ word = 0; -+ } -+ } -+} -+ -+static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev, -+ const s8 delta_luma_weight[], -+ const s8 luma_offset[], -+ const s8 delta_chroma_weight[][2], -+ const s8 chroma_offset[][2], -+ u8 num_ref_idx_active, -+ u32 sram_luma_offset, -+ u32 sram_chroma_offset) -+{ -+ struct cedrus_h265_sram_pred_weight pred_weight[2] = { { 0 } }; -+ unsigned int i, j; -+ -+ cedrus_h265_sram_write_offset(dev, sram_luma_offset); -+ -+ for (i = 0; i < num_ref_idx_active; i++) { -+ unsigned int index = i % 2; -+ -+ pred_weight[index].delta_weight = delta_luma_weight[i]; -+ pred_weight[index].offset = luma_offset[i]; -+ -+ if (index == 1 || i == (num_ref_idx_active - 1)) -+ cedrus_h265_sram_write_data(dev, (u32 *)&pred_weight, -+ sizeof(pred_weight)); -+ } -+ -+ cedrus_h265_sram_write_offset(dev, sram_chroma_offset); -+ -+ for (i = 0; i < num_ref_idx_active; i++) { -+ for (j = 0; j < 2; j++) { -+ pred_weight[j].delta_weight = delta_chroma_weight[i][j]; -+ pred_weight[j].offset = chroma_offset[i][j]; -+ } -+ -+ cedrus_h265_sram_write_data(dev, &pred_weight, -+ sizeof(pred_weight)); -+ } -+} -+ -+static void cedrus_h265_setup(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ const struct v4l2_ctrl_hevc_sps *sps; -+ const struct v4l2_ctrl_hevc_pps *pps; -+ const struct v4l2_ctrl_hevc_slice_params *slice_params; -+ const struct v4l2_hevc_pred_weight_table *pred_weight_table; -+ dma_addr_t src_buf_addr; -+ dma_addr_t src_buf_end_addr; -+ u32 chroma_log2_weight_denom; -+ u32 output_pic_list_index; -+ u32 pic_order_cnt[2]; -+ u32 reg; -+ -+ sps = run->h265.sps; -+ pps = run->h265.pps; -+ slice_params = run->h265.slice_params; -+ pred_weight_table = &slice_params->pred_weight_table; -+ -+ /* MV column buffer size and allocation. */ -+ if (!ctx->codec.h265.mv_col_buf_size) { -+ unsigned int num_buffers = -+ run->dst->vb2_buf.vb2_queue->num_buffers; -+ unsigned int log2_max_luma_coding_block_size = -+ sps->log2_min_luma_coding_block_size_minus3 + 3 + -+ sps->log2_diff_max_min_luma_coding_block_size; -+ unsigned int ctb_size_luma = -+ 1UL << log2_max_luma_coding_block_size; -+ -+ /* -+ * Each CTB requires a MV col buffer with a specific unit size. -+ * Since the address is given with missing lsb bits, 1 KiB is -+ * added to each buffer to ensure proper alignment. -+ */ -+ ctx->codec.h265.mv_col_buf_unit_size = -+ DIV_ROUND_UP(ctx->src_fmt.width, ctb_size_luma) * -+ DIV_ROUND_UP(ctx->src_fmt.height, ctb_size_luma) * -+ CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE + SZ_1K; -+ -+ ctx->codec.h265.mv_col_buf_size = num_buffers * -+ ctx->codec.h265.mv_col_buf_unit_size; -+ -+ ctx->codec.h265.mv_col_buf = -+ dma_alloc_coherent(dev->dev, -+ ctx->codec.h265.mv_col_buf_size, -+ &ctx->codec.h265.mv_col_buf_addr, -+ GFP_KERNEL); -+ if (!ctx->codec.h265.mv_col_buf) { -+ ctx->codec.h265.mv_col_buf_size = 0; -+ // TODO: Abort the process here. -+ return; -+ } -+ } -+ -+ /* Activate H265 engine. */ -+ cedrus_engine_enable(dev, CEDRUS_CODEC_H265); -+ -+ /* Source offset and length in bits. */ -+ -+ reg = slice_params->data_bit_offset; -+ cedrus_write(dev, VE_DEC_H265_BITS_OFFSET, reg); -+ -+ reg = slice_params->bit_size - slice_params->data_bit_offset; -+ cedrus_write(dev, VE_DEC_H265_BITS_LEN, reg); -+ -+ /* Source beginning and end addresses. */ -+ -+ src_buf_addr = vb2_dma_contig_plane_dma_addr(&run->src->vb2_buf, 0); -+ -+ reg = VE_DEC_H265_BITS_ADDR_BASE(src_buf_addr); -+ reg |= VE_DEC_H265_BITS_ADDR_VALID_SLICE_DATA; -+ reg |= VE_DEC_H265_BITS_ADDR_LAST_SLICE_DATA; -+ reg |= VE_DEC_H265_BITS_ADDR_FIRST_SLICE_DATA; -+ -+ cedrus_write(dev, VE_DEC_H265_BITS_ADDR, reg); -+ -+ src_buf_end_addr = src_buf_addr + -+ DIV_ROUND_UP(slice_params->bit_size, 8); -+ -+ reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_end_addr); -+ cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg); -+ -+ /* Coding tree block address: start at the beginning. */ -+ reg = VE_DEC_H265_DEC_CTB_ADDR_X(0) | VE_DEC_H265_DEC_CTB_ADDR_Y(0); -+ cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg); -+ -+ cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0); -+ cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0); -+ -+ /* Clear the number of correctly-decoded coding tree blocks. */ -+ cedrus_write(dev, VE_DEC_H265_DEC_CTB_NUM, 0); -+ -+ /* Initialize bitstream access. */ -+ cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC); -+ -+ /* Bitstream parameters. */ -+ -+ reg = VE_DEC_H265_DEC_NAL_HDR_NAL_UNIT_TYPE(slice_params->nal_unit_type) | -+ VE_DEC_H265_DEC_NAL_HDR_NUH_TEMPORAL_ID_PLUS1(slice_params->nuh_temporal_id_plus1); -+ -+ cedrus_write(dev, VE_DEC_H265_DEC_NAL_HDR, reg); -+ -+ /* SPS. */ -+ -+ reg = VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(sps->max_transform_hierarchy_depth_intra) | -+ VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(sps->max_transform_hierarchy_depth_inter) | -+ VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(sps->log2_diff_max_min_luma_transform_block_size) | -+ VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(sps->log2_min_luma_transform_block_size_minus2) | -+ VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_luma_coding_block_size) | -+ VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_luma_coding_block_size_minus3) | -+ VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(sps->bit_depth_chroma_minus8) | -+ VE_DEC_H265_DEC_SPS_HDR_CHROMA_FORMAT_IDC(sps->chroma_format_idc); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_STRONG_INTRA_SMOOTHING_ENABLE, -+ V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED, -+ sps->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_SPS_TEMPORAL_MVP_ENABLED, -+ V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED, -+ sps->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_SAMPLE_ADAPTIVE_OFFSET_ENABLED, -+ V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET, -+ sps->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_AMP_ENABLED, -+ V4L2_HEVC_SPS_FLAG_AMP_ENABLED, sps->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_SEPARATE_COLOUR_PLANE, -+ V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE, -+ sps->flags); -+ -+ cedrus_write(dev, VE_DEC_H265_DEC_SPS_HDR, reg); -+ -+ reg = VE_DEC_H265_DEC_PCM_CTRL_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_pcm_luma_coding_block_size) | -+ VE_DEC_H265_DEC_PCM_CTRL_LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_pcm_luma_coding_block_size_minus3) | -+ VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_CHROMA_MINUS1(sps->pcm_sample_bit_depth_chroma_minus1) | -+ VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_LUMA_MINUS1(sps->pcm_sample_bit_depth_luma_minus1); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_ENABLED, -+ V4L2_HEVC_SPS_FLAG_PCM_ENABLED, sps->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_LOOP_FILTER_DISABLED, -+ V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED, -+ sps->flags); -+ -+ cedrus_write(dev, VE_DEC_H265_DEC_PCM_CTRL, reg); -+ -+ /* PPS. */ -+ -+ reg = VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(pps->pps_cr_qp_offset) | -+ VE_DEC_H265_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(pps->pps_cb_qp_offset) | -+ VE_DEC_H265_DEC_PPS_CTRL0_INIT_QP_MINUS26(pps->init_qp_minus26) | -+ VE_DEC_H265_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(pps->diff_cu_qp_delta_depth); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CU_QP_DELTA_ENABLED, -+ V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED, -+ pps->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_TRANSFORM_SKIP_ENABLED, -+ V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED, -+ pps->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CONSTRAINED_INTRA_PRED, -+ V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED, -+ pps->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_SIGN_DATA_HIDING_ENABLED, -+ V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED, -+ pps->flags); -+ -+ cedrus_write(dev, VE_DEC_H265_DEC_PPS_CTRL0, reg); -+ -+ reg = VE_DEC_H265_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(pps->log2_parallel_merge_level_minus2); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED, -+ V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED, -+ pps->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED, -+ V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED, -+ pps->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_ENTROPY_CODING_SYNC_ENABLED, -+ V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED, -+ pps->flags); -+ -+ /* TODO: VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED */ -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED, -+ V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED, -+ pps->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_BIPRED, -+ V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED, pps->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_PRED, -+ V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED, pps->flags); -+ -+ cedrus_write(dev, VE_DEC_H265_DEC_PPS_CTRL1, reg); -+ -+ /* Slice Parameters. */ -+ -+ reg = VE_DEC_H265_DEC_SLICE_HDR_INFO0_PICTURE_TYPE(slice_params->pic_struct) | -+ VE_DEC_H265_DEC_SLICE_HDR_INFO0_FIVE_MINUS_MAX_NUM_MERGE_CAND(slice_params->five_minus_max_num_merge_cand) | -+ VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L1_ACTIVE_MINUS1(slice_params->num_ref_idx_l1_active_minus1) | -+ VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L0_ACTIVE_MINUS1(slice_params->num_ref_idx_l0_active_minus1) | -+ VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLLOCATED_REF_IDX(slice_params->collocated_ref_idx) | -+ VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(slice_params->colour_plane_id) | -+ VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TYPE(slice_params->slice_type); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_COLLOCATED_FROM_L0, -+ V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0, -+ slice_params->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_CABAC_INIT, -+ V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT, -+ slice_params->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_MVD_L1_ZERO, -+ V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO, -+ slice_params->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_CHROMA, -+ V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA, -+ slice_params->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_LUMA, -+ V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA, -+ slice_params->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_TEMPORAL_MVP_ENABLE, -+ V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED, -+ slice_params->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_DEPENDENT_SLICE_SEGMENT, -+ V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT, -+ pps->flags); -+ -+ /* FIXME: For multi-slice support. */ -+ reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC; -+ -+ cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO0, reg); -+ -+ reg = VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(slice_params->slice_tc_offset_div2) | -+ VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(slice_params->slice_beta_offset_div2) | -+ VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(slice_params->num_rps_poc_st_curr_after == 0) | -+ VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(slice_params->slice_cr_qp_offset) | -+ VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(slice_params->slice_cb_qp_offset) | -+ VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(slice_params->slice_qp_delta); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED, -+ V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED, -+ slice_params->flags); -+ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED, -+ V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED, -+ slice_params->flags); -+ -+ cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO1, reg); -+ -+ chroma_log2_weight_denom = pred_weight_table->luma_log2_weight_denom + -+ pred_weight_table->delta_chroma_log2_weight_denom; -+ reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(0) | -+ VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(chroma_log2_weight_denom) | -+ VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(pred_weight_table->luma_log2_weight_denom); -+ -+ cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO2, reg); -+ -+ /* Decoded picture size. */ -+ -+ reg = VE_DEC_H265_DEC_PIC_SIZE_WIDTH(ctx->src_fmt.width) | -+ VE_DEC_H265_DEC_PIC_SIZE_HEIGHT(ctx->src_fmt.height); -+ -+ cedrus_write(dev, VE_DEC_H265_DEC_PIC_SIZE, reg); -+ -+ /* Scaling list. */ -+ -+ reg = VE_DEC_H265_SCALING_LIST_CTRL0_DEFAULT; -+ cedrus_write(dev, VE_DEC_H265_SCALING_LIST_CTRL0, reg); -+ -+ /* Neightbor information address. */ -+ reg = VE_DEC_H265_NEIGHBOR_INFO_ADDR_BASE(ctx->codec.h265.neighbor_info_buf_addr); -+ cedrus_write(dev, VE_DEC_H265_NEIGHBOR_INFO_ADDR, reg); -+ -+ /* Write decoded picture buffer in pic list. */ -+ cedrus_h265_frame_info_write_dpb(ctx, slice_params->dpb, -+ slice_params->num_active_dpb_entries); -+ -+ /* Output frame. */ -+ -+ output_pic_list_index = V4L2_HEVC_DPB_ENTRIES_NUM_MAX; -+ pic_order_cnt[0] = slice_params->slice_pic_order_cnt; -+ pic_order_cnt[1] = slice_params->slice_pic_order_cnt; -+ -+ cedrus_h265_frame_info_write_single(ctx, output_pic_list_index, -+ slice_params->pic_struct != 0, -+ pic_order_cnt, -+ run->dst->vb2_buf.index); -+ -+ cedrus_write(dev, VE_DEC_H265_OUTPUT_FRAME_IDX, output_pic_list_index); -+ -+ /* Reference picture list 0 (for P/B frames). */ -+ if (slice_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { -+ cedrus_h265_ref_pic_list_write(dev, slice_params->dpb, -+ slice_params->ref_idx_l0, -+ slice_params->num_ref_idx_l0_active_minus1 + 1, -+ VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0); -+ -+ if ((pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED) || -+ (pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED)) -+ cedrus_h265_pred_weight_write(dev, -+ pred_weight_table->delta_luma_weight_l0, -+ pred_weight_table->luma_offset_l0, -+ pred_weight_table->delta_chroma_weight_l0, -+ pred_weight_table->chroma_offset_l0, -+ slice_params->num_ref_idx_l0_active_minus1 + 1, -+ VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0, -+ VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0); -+ } -+ -+ /* Reference picture list 1 (for B frames). */ -+ if (slice_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) { -+ cedrus_h265_ref_pic_list_write(dev, slice_params->dpb, -+ slice_params->ref_idx_l1, -+ slice_params->num_ref_idx_l1_active_minus1 + 1, -+ VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1); -+ -+ if (pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED) -+ cedrus_h265_pred_weight_write(dev, -+ pred_weight_table->delta_luma_weight_l1, -+ pred_weight_table->luma_offset_l1, -+ pred_weight_table->delta_chroma_weight_l1, -+ pred_weight_table->chroma_offset_l1, -+ slice_params->num_ref_idx_l1_active_minus1 + 1, -+ VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1, -+ VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1); -+ } -+ -+ /* Enable appropriate interruptions. */ -+ cedrus_write(dev, VE_DEC_H265_CTRL, VE_DEC_H265_CTRL_IRQ_MASK); -+} -+ -+static int cedrus_h265_start(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ /* The buffer size is calculated at setup time. */ -+ ctx->codec.h265.mv_col_buf_size = 0; -+ -+ ctx->codec.h265.neighbor_info_buf = -+ dma_alloc_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, -+ &ctx->codec.h265.neighbor_info_buf_addr, -+ GFP_KERNEL); -+ if (!ctx->codec.h265.neighbor_info_buf) -+ return -ENOMEM; -+ -+ return 0; -+} -+ -+static void cedrus_h265_stop(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ if (ctx->codec.h265.mv_col_buf_size > 0) { -+ dma_free_coherent(dev->dev, ctx->codec.h265.mv_col_buf_size, -+ ctx->codec.h265.mv_col_buf, -+ ctx->codec.h265.mv_col_buf_addr); -+ -+ ctx->codec.h265.mv_col_buf_size = 0; -+ } -+ -+ dma_free_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, -+ ctx->codec.h265.neighbor_info_buf, -+ ctx->codec.h265.neighbor_info_buf_addr); -+} -+ -+static void cedrus_h265_trigger(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_DEC_SLICE); -+} -+ -+struct cedrus_dec_ops cedrus_dec_ops_h265 = { -+ .irq_clear = cedrus_h265_irq_clear, -+ .irq_disable = cedrus_h265_irq_disable, -+ .irq_status = cedrus_h265_irq_status, -+ .setup = cedrus_h265_setup, -+ .start = cedrus_h265_start, -+ .stop = cedrus_h265_stop, -+ .trigger = cedrus_h265_trigger, -+}; -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -index e7e18424bab1..570a9165dd5d 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -@@ -50,6 +50,10 @@ int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) - reg |= VE_MODE_DEC_H264; - break; - -+ case CEDRUS_CODEC_H265: -+ reg |= VE_MODE_DEC_H265; -+ break; -+ - default: - return -EINVAL; - } -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -index 21676a1797f1..6fc28d21a6c7 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -@@ -21,10 +21,17 @@ - * * MC: Motion Compensation - * * STCD: Start Code Detect - * * SDRT: Scale Down and Rotate -+ * * WB: Writeback -+ * * BITS/BS: Bitstream -+ * * MB: Macroblock -+ * * CTU: Coding Tree Unit -+ * * CTB: Coding Tree Block -+ * * IDX: Index - */ - - #define VE_ENGINE_DEC_MPEG 0x100 - #define VE_ENGINE_DEC_H264 0x200 -+#define VE_ENGINE_DEC_H265 0x500 - - #define VE_MODE 0x00 - -@@ -235,6 +242,270 @@ - #define VE_DEC_MPEG_ROT_LUMA (VE_ENGINE_DEC_MPEG + 0xcc) - #define VE_DEC_MPEG_ROT_CHROMA (VE_ENGINE_DEC_MPEG + 0xd0) - -+#define VE_DEC_H265_DEC_NAL_HDR (VE_ENGINE_DEC_H265 + 0x00) -+ -+#define VE_DEC_H265_DEC_NAL_HDR_NUH_TEMPORAL_ID_PLUS1(v) \ -+ SHIFT_AND_MASK_BITS(v, 8, 6) -+#define VE_DEC_H265_DEC_NAL_HDR_NAL_UNIT_TYPE(v) \ -+ SHIFT_AND_MASK_BITS(v, 5, 0) -+ -+#define VE_DEC_H265_FLAG(reg_flag, ctrl_flag, flags) \ -+ (((flags) & (ctrl_flag)) ? reg_flag : 0) -+ -+#define VE_DEC_H265_DEC_SPS_HDR (VE_ENGINE_DEC_H265 + 0x04) -+ -+#define VE_DEC_H265_DEC_SPS_HDR_FLAG_STRONG_INTRA_SMOOTHING_ENABLE BIT(26) -+#define VE_DEC_H265_DEC_SPS_HDR_FLAG_SPS_TEMPORAL_MVP_ENABLED BIT(25) -+#define VE_DEC_H265_DEC_SPS_HDR_FLAG_SAMPLE_ADAPTIVE_OFFSET_ENABLED BIT(24) -+#define VE_DEC_H265_DEC_SPS_HDR_FLAG_AMP_ENABLED BIT(23) -+#define VE_DEC_H265_DEC_SPS_HDR_FLAG_SEPARATE_COLOUR_PLANE BIT(2) -+ -+#define VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(v) \ -+ SHIFT_AND_MASK_BITS(v, 22, 20) -+#define VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(v) \ -+ SHIFT_AND_MASK_BITS(v, 19, 17) -+#define VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(v) \ -+ SHIFT_AND_MASK_BITS(v, 16, 15) -+#define VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(v) \ -+ SHIFT_AND_MASK_BITS(v, 14, 13) -+#define VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(v) \ -+ SHIFT_AND_MASK_BITS(v, 12, 11) -+#define VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(v) \ -+ SHIFT_AND_MASK_BITS(v, 10, 9) -+#define VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(v) \ -+ SHIFT_AND_MASK_BITS(v, 8, 6) -+#define VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_LUMA_MINUS8(v) \ -+ SHIFT_AND_MASK_BITS(v, 5, 3) -+#define VE_DEC_H265_DEC_SPS_HDR_CHROMA_FORMAT_IDC(v) \ -+ SHIFT_AND_MASK_BITS(v, 1, 0) -+ -+#define VE_DEC_H265_DEC_PIC_SIZE (VE_ENGINE_DEC_H265 + 0x08) -+ -+#define VE_DEC_H265_DEC_PIC_SIZE_WIDTH(w) (((w) << 0) & GENMASK(13, 0)) -+#define VE_DEC_H265_DEC_PIC_SIZE_HEIGHT(h) (((h) << 16) & GENMASK(29, 16)) -+ -+#define VE_DEC_H265_DEC_PCM_CTRL (VE_ENGINE_DEC_H265 + 0x0c) -+ -+#define VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_ENABLED BIT(15) -+#define VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_LOOP_FILTER_DISABLED BIT(14) -+ -+#define VE_DEC_H265_DEC_PCM_CTRL_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE(v) \ -+ SHIFT_AND_MASK_BITS(v, 11, 10) -+#define VE_DEC_H265_DEC_PCM_CTRL_LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3(v) \ -+ SHIFT_AND_MASK_BITS(v, 9, 8) -+#define VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_CHROMA_MINUS1(v) \ -+ SHIFT_AND_MASK_BITS(v, 7, 4) -+#define VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_LUMA_MINUS1(v) \ -+ SHIFT_AND_MASK_BITS(v, 3, 0) -+ -+#define VE_DEC_H265_DEC_PPS_CTRL0 (VE_ENGINE_DEC_H265 + 0x10) -+ -+#define VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CU_QP_DELTA_ENABLED BIT(3) -+#define VE_DEC_H265_DEC_PPS_CTRL0_FLAG_TRANSFORM_SKIP_ENABLED BIT(2) -+#define VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CONSTRAINED_INTRA_PRED BIT(1) -+#define VE_DEC_H265_DEC_PPS_CTRL0_FLAG_SIGN_DATA_HIDING_ENABLED BIT(0) -+ -+#define VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(v) \ -+ SHIFT_AND_MASK_BITS(v, 29, 24) -+#define VE_DEC_H265_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(v) \ -+ SHIFT_AND_MASK_BITS(v, 21, 16) -+#define VE_DEC_H265_DEC_PPS_CTRL0_INIT_QP_MINUS26(v) \ -+ SHIFT_AND_MASK_BITS(v, 14, 8) -+#define VE_DEC_H265_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(v) \ -+ SHIFT_AND_MASK_BITS(v, 5, 4) -+ -+#define VE_DEC_H265_DEC_PPS_CTRL1 (VE_ENGINE_DEC_H265 + 0x14) -+ -+#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED BIT(6) -+#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED BIT(5) -+#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_ENTROPY_CODING_SYNC_ENABLED BIT(4) -+#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED BIT(3) -+#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED BIT(2) -+#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_BIPRED BIT(1) -+#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_PRED BIT(0) -+ -+#define VE_DEC_H265_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(v) \ -+ SHIFT_AND_MASK_BITS(v, 10, 8) -+ -+#define VE_DEC_H265_SCALING_LIST_CTRL0 (VE_ENGINE_DEC_H265 + 0x18) -+ -+#define VE_DEC_H265_SCALING_LIST_CTRL0_FLAG_ENABLED BIT(31) -+ -+#define VE_DEC_H265_SCALING_LIST_CTRL0_SRAM (0 << 30) -+#define VE_DEC_H265_SCALING_LIST_CTRL0_DEFAULT (1 << 30) -+ -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO0 (VE_ENGINE_DEC_H265 + 0x20) -+ -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_COLLOCATED_FROM_L0 BIT(11) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_CABAC_INIT BIT(10) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_MVD_L1_ZERO BIT(9) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_CHROMA BIT(8) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_LUMA BIT(7) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_TEMPORAL_MVP_ENABLE BIT(6) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_DEPENDENT_SLICE_SEGMENT BIT(1) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC BIT(0) -+ -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_PICTURE_TYPE(v) \ -+ SHIFT_AND_MASK_BITS(v, 29, 28) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FIVE_MINUS_MAX_NUM_MERGE_CAND(v) \ -+ SHIFT_AND_MASK_BITS(v, 26, 24) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L1_ACTIVE_MINUS1(v) \ -+ SHIFT_AND_MASK_BITS(v, 23, 20) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L0_ACTIVE_MINUS1(v) \ -+ SHIFT_AND_MASK_BITS(v, 19, 16) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLLOCATED_REF_IDX(v) \ -+ SHIFT_AND_MASK_BITS(v, 15, 12) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(v) \ -+ SHIFT_AND_MASK_BITS(v, 5, 4) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TYPE(v) \ -+ SHIFT_AND_MASK_BITS(v, 3, 2) -+ -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO1 (VE_ENGINE_DEC_H265 + 0x24) -+ -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED BIT(23) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED BIT(22) -+ -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(v) \ -+ SHIFT_AND_MASK_BITS(v, 31, 28) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(v) \ -+ SHIFT_AND_MASK_BITS(v, 27, 24) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(v) \ -+ ((v) ? BIT(21) : 0) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(v) \ -+ SHIFT_AND_MASK_BITS(v, 20, 16) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(v) \ -+ SHIFT_AND_MASK_BITS(v, 12, 8) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(v) \ -+ SHIFT_AND_MASK_BITS(v, 6, 0) -+ -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO2 (VE_ENGINE_DEC_H265 + 0x28) -+ -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(v) \ -+ SHIFT_AND_MASK_BITS(v, 21, 8) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(v) \ -+ SHIFT_AND_MASK_BITS(v, 6, 4) -+#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(v) \ -+ SHIFT_AND_MASK_BITS(v, 2, 0) -+ -+#define VE_DEC_H265_DEC_CTB_ADDR (VE_ENGINE_DEC_H265 + 0x2c) -+ -+#define VE_DEC_H265_DEC_CTB_ADDR_Y(y) SHIFT_AND_MASK_BITS(y, 25, 16) -+#define VE_DEC_H265_DEC_CTB_ADDR_X(x) SHIFT_AND_MASK_BITS(x, 9, 0) -+ -+#define VE_DEC_H265_CTRL (VE_ENGINE_DEC_H265 + 0x30) -+ -+#define VE_DEC_H265_CTRL_DDR_CONSISTENCY_EN BIT(31) -+#define VE_DEC_H265_CTRL_STCD_EN BIT(25) -+#define VE_DEC_H265_CTRL_EPTB_DEC_BYPASS_EN BIT(24) -+#define VE_DEC_H265_CTRL_TQ_BYPASS_EN BIT(12) -+#define VE_DEC_H265_CTRL_VLD_BYPASS_EN BIT(11) -+#define VE_DEC_H265_CTRL_NCRI_CACHE_DISABLE BIT(10) -+#define VE_DEC_H265_CTRL_ROTATE_SCALE_OUT_EN BIT(9) -+#define VE_DEC_H265_CTRL_MC_NO_WRITEBACK BIT(8) -+#define VE_DEC_H265_CTRL_VLD_DATA_REQ_IRQ_EN BIT(2) -+#define VE_DEC_H265_CTRL_ERROR_IRQ_EN BIT(1) -+#define VE_DEC_H265_CTRL_FINISH_IRQ_EN BIT(0) -+#define VE_DEC_H265_CTRL_IRQ_MASK \ -+ (VE_DEC_H265_CTRL_FINISH_IRQ_EN | VE_DEC_H265_CTRL_ERROR_IRQ_EN | \ -+ VE_DEC_H265_CTRL_VLD_DATA_REQ_IRQ_EN) -+ -+#define VE_DEC_H265_TRIGGER (VE_ENGINE_DEC_H265 + 0x34) -+ -+#define VE_DEC_H265_TRIGGER_STCD_VC1 (0x02 << 4) -+#define VE_DEC_H265_TRIGGER_STCD_AVS (0x01 << 4) -+#define VE_DEC_H265_TRIGGER_STCD_HEVC (0x00 << 4) -+#define VE_DEC_H265_TRIGGER_DEC_SLICE (0x08 << 0) -+#define VE_DEC_H265_TRIGGER_INIT_SWDEC (0x07 << 0) -+#define VE_DEC_H265_TRIGGER_BYTE_ALIGN (0x06 << 0) -+#define VE_DEC_H265_TRIGGER_GET_VLCUE (0x05 << 0) -+#define VE_DEC_H265_TRIGGER_GET_VLCSE (0x04 << 0) -+#define VE_DEC_H265_TRIGGER_FLUSH_BITS (0x03 << 0) -+#define VE_DEC_H265_TRIGGER_GET_BITS (0x02 << 0) -+#define VE_DEC_H265_TRIGGER_SHOW_BITS (0x01 << 0) -+ -+#define VE_DEC_H265_STATUS (VE_ENGINE_DEC_H265 + 0x38) -+ -+#define VE_DEC_H265_STATUS_STCD BIT(24) -+#define VE_DEC_H265_STATUS_STCD_BUSY BIT(21) -+#define VE_DEC_H265_STATUS_WB_BUSY BIT(20) -+#define VE_DEC_H265_STATUS_BS_DMA_BUSY BIT(19) -+#define VE_DEC_H265_STATUS_IQIT_BUSY BIT(18) -+#define VE_DEC_H265_STATUS_INTER_BUSY BIT(17) -+#define VE_DEC_H265_STATUS_MORE_DATA BIT(16) -+#define VE_DEC_H265_STATUS_VLD_BUSY BIT(14) -+#define VE_DEC_H265_STATUS_DEBLOCKING_BUSY BIT(13) -+#define VE_DEC_H265_STATUS_DEBLOCKING_DRAM_BUSY BIT(12) -+#define VE_DEC_H265_STATUS_INTRA_BUSY BIT(11) -+#define VE_DEC_H265_STATUS_SAO_BUSY BIT(10) -+#define VE_DEC_H265_STATUS_MVP_BUSY BIT(9) -+#define VE_DEC_H265_STATUS_SWDEC_BUSY BIT(8) -+#define VE_DEC_H265_STATUS_OVER_TIME BIT(3) -+#define VE_DEC_H265_STATUS_VLD_DATA_REQ BIT(2) -+#define VE_DEC_H265_STATUS_ERROR BIT(1) -+#define VE_DEC_H265_STATUS_SUCCESS BIT(0) -+#define VE_DEC_H265_STATUS_STCD_TYPE_MASK GENMASK(23, 22) -+#define VE_DEC_H265_STATUS_CHECK_MASK \ -+ (VE_DEC_H265_STATUS_SUCCESS | VE_DEC_H265_STATUS_ERROR | \ -+ VE_DEC_H265_STATUS_VLD_DATA_REQ) -+#define VE_DEC_H265_STATUS_CHECK_ERROR \ -+ (VE_DEC_H265_STATUS_ERROR | VE_DEC_H265_STATUS_VLD_DATA_REQ) -+ -+#define VE_DEC_H265_DEC_CTB_NUM (VE_ENGINE_DEC_H265 + 0x3c) -+ -+#define VE_DEC_H265_BITS_ADDR (VE_ENGINE_DEC_H265 + 0x40) -+ -+#define VE_DEC_H265_BITS_ADDR_FIRST_SLICE_DATA BIT(30) -+#define VE_DEC_H265_BITS_ADDR_LAST_SLICE_DATA BIT(29) -+#define VE_DEC_H265_BITS_ADDR_VALID_SLICE_DATA BIT(28) -+#define VE_DEC_H265_BITS_ADDR_BASE(a) (((a) >> 8) & GENMASK(27, 0)) -+ -+#define VE_DEC_H265_BITS_OFFSET (VE_ENGINE_DEC_H265 + 0x44) -+#define VE_DEC_H265_BITS_LEN (VE_ENGINE_DEC_H265 + 0x48) -+ -+#define VE_DEC_H265_BITS_END_ADDR (VE_ENGINE_DEC_H265 + 0x4c) -+ -+#define VE_DEC_H265_BITS_END_ADDR_BASE(a) ((a) >> 8) -+ -+#define VE_DEC_H265_SDRT_CTRL (VE_ENGINE_DEC_H265 + 0x50) -+#define VE_DEC_H265_SDRT_LUMA_ADDR (VE_ENGINE_DEC_H265 + 0x54) -+#define VE_DEC_H265_SDRT_CHROMA_ADDR (VE_ENGINE_DEC_H265 + 0x58) -+ -+#define VE_DEC_H265_OUTPUT_FRAME_IDX (VE_ENGINE_DEC_H265 + 0x5c) -+ -+#define VE_DEC_H265_NEIGHBOR_INFO_ADDR (VE_ENGINE_DEC_H265 + 0x60) -+ -+#define VE_DEC_H265_NEIGHBOR_INFO_ADDR_BASE(a) ((a) >> 8) -+ -+#define VE_DEC_H265_ENTRY_POINT_OFFSET_ADDR (VE_ENGINE_DEC_H265 + 0x64) -+#define VE_DEC_H265_TILE_START_CTB (VE_ENGINE_DEC_H265 + 0x68) -+#define VE_DEC_H265_TILE_END_CTB (VE_ENGINE_DEC_H265 + 0x6c) -+ -+#define VE_DEC_H265_LOW_ADDR (VE_ENGINE_DEC_H265 + 0x80) -+ -+#define VE_DEC_H265_LOW_ADDR_PRIMARY_CHROMA(a) \ -+ SHIFT_AND_MASK_BITS(a, 31, 24) -+#define VE_DEC_H265_LOW_ADDR_SECONDARY_CHROMA(a) \ -+ SHIFT_AND_MASK_BITS(a, 23, 16) -+#define VE_DEC_H265_LOW_ADDR_ENTRY_POINTS_BUF(a) \ -+ SHIFT_AND_MASK_BITS(a, 7, 0) -+ -+#define VE_DEC_H265_SRAM_OFFSET (VE_ENGINE_DEC_H265 + 0xe0) -+ -+#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0 0x00 -+#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0 0x20 -+#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1 0x60 -+#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1 0x80 -+#define VE_DEC_H265_SRAM_OFFSET_FRAME_INFO 0x400 -+#define VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT 0x20 -+#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS 0x800 -+#define VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0 0xc00 -+#define VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1 0xc10 -+ -+#define VE_DEC_H265_SRAM_DATA (VE_ENGINE_DEC_H265 + 0xe4) -+ -+#define VE_DEC_H265_SRAM_DATA_ADDR_BASE(a) ((a) >> 8) -+#define VE_DEC_H265_SRAM_REF_PIC_LIST_LT_REF BIT(7) -+ - #define VE_H264_SPS 0x200 - #define VE_H264_SPS_MBS_ONLY BIT(18) - #define VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD BIT(17) -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index f745f66c4440..cc15a5cf107d 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -41,6 +41,11 @@ static struct cedrus_format cedrus_formats[] = { - .pixelformat = V4L2_PIX_FMT_H264_SLICE, - .directions = CEDRUS_DECODE_SRC, - }, -+ { -+ .pixelformat = V4L2_PIX_FMT_HEVC_SLICE, -+ .directions = CEDRUS_DECODE_SRC, -+ .capabilities = CEDRUS_CAPABILITY_H265_DEC, -+ }, - { - .pixelformat = V4L2_PIX_FMT_SUNXI_TILED_NV12, - .directions = CEDRUS_DECODE_DST, -@@ -102,6 +107,7 @@ void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt) - switch (pix_fmt->pixelformat) { - case V4L2_PIX_FMT_MPEG2_SLICE: - case V4L2_PIX_FMT_H264_SLICE: -+ case V4L2_PIX_FMT_HEVC_SLICE: - /* Zero bytes per line for encoded source. */ - bytesperline = 0; - /* Choose some minimum size since this can't be 0 */ -@@ -439,6 +445,10 @@ static int cedrus_start_streaming(struct vb2_queue *vq, unsigned int count) - ctx->current_codec = CEDRUS_CODEC_H264; - break; - -+ case V4L2_PIX_FMT_HEVC_SLICE: -+ ctx->current_codec = CEDRUS_CODEC_H265; -+ break; -+ - default: - return -EINVAL; - } --- -2.23.0 - -From 137272cdf7cc5be835f44216e6003769d1638480 Mon Sep 17 00:00:00 2001 -From: Hans Verkuil -Date: Fri, 11 Oct 2019 06:32:40 -0300 -Subject: [PATCH] media: vb2: add V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF - -This patch adds support for the V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF -flag. - -It also adds a new V4L2_BUF_CAP_SUPPORTS_M2M_HOLD_CAPTURE_BUF -capability. - -Drivers should set vb2_queue->subsystem_flags to -VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF to indicate support -for this flag. - -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - Documentation/media/uapi/v4l/buffer.rst | 13 +++++++++++++ - Documentation/media/uapi/v4l/vidioc-reqbufs.rst | 6 ++++++ - drivers/media/common/videobuf2/videobuf2-v4l2.c | 12 ++++++++++-- - include/media/videobuf2-core.h | 3 +++ - include/media/videobuf2-v4l2.h | 5 +++++ - include/uapi/linux/videodev2.h | 13 ++++++++----- - 6 files changed, 45 insertions(+), 7 deletions(-) - -diff --git a/Documentation/media/uapi/v4l/buffer.rst b/Documentation/media/uapi/v4l/buffer.rst -index 1cbd9cde57f3..9149b57728e5 100644 ---- a/Documentation/media/uapi/v4l/buffer.rst -+++ b/Documentation/media/uapi/v4l/buffer.rst -@@ -607,6 +607,19 @@ Buffer Flags - applications shall use this flag for output buffers if the data in - this buffer has not been created by the CPU but by some - DMA-capable unit, in which case caches have not been used. -+ * .. _`V4L2-BUF-FLAG-M2M-HOLD-CAPTURE-BUF`: -+ -+ - ``V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF`` -+ - 0x00000200 -+ - Only valid if ``V4L2_BUF_CAP_SUPPORTS_M2M_HOLD_CAPTURE_BUF`` is -+ set. It is typically used with stateless decoders where multiple -+ output buffers each decode to a slice of the decoded frame. -+ Applications can set this flag when queueing the output buffer -+ to prevent the driver from dequeueing the capture buffer after -+ the output buffer has been decoded (i.e. the capture buffer is -+ 'held'). If the timestamp of this output buffer differs from that -+ of the previous output buffer, then that indicates the start of a -+ new frame and the previously held capture buffer is dequeued. - * .. _`V4L2-BUF-FLAG-LAST`: - - - ``V4L2_BUF_FLAG_LAST`` -diff --git a/Documentation/media/uapi/v4l/vidioc-reqbufs.rst b/Documentation/media/uapi/v4l/vidioc-reqbufs.rst -index d7faef10e39b..d0c643db477a 100644 ---- a/Documentation/media/uapi/v4l/vidioc-reqbufs.rst -+++ b/Documentation/media/uapi/v4l/vidioc-reqbufs.rst -@@ -125,6 +125,7 @@ aborting or finishing any DMA in progress, an implicit - .. _V4L2-BUF-CAP-SUPPORTS-DMABUF: - .. _V4L2-BUF-CAP-SUPPORTS-REQUESTS: - .. _V4L2-BUF-CAP-SUPPORTS-ORPHANED-BUFS: -+.. _V4L2-BUF-CAP-SUPPORTS-M2M-HOLD-CAPTURE-BUF: - - .. cssclass:: longtable - -@@ -150,6 +151,11 @@ aborting or finishing any DMA in progress, an implicit - - The kernel allows calling :ref:`VIDIOC_REQBUFS` while buffers are still - mapped or exported via DMABUF. These orphaned buffers will be freed - when they are unmapped or when the exported DMABUF fds are closed. -+ * - ``V4L2_BUF_CAP_SUPPORTS_M2M_HOLD_CAPTURE_BUF`` -+ - 0x00000020 -+ - Only valid for stateless decoders. If set, then userspace can set the -+ ``V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF`` flag to hold off on returning the -+ capture buffer until the OUTPUT timestamp changes. - - Return Value - ============ -diff --git a/drivers/media/common/videobuf2/videobuf2-v4l2.c b/drivers/media/common/videobuf2/videobuf2-v4l2.c -index 5a9ba3846f0a..e652f4318284 100644 ---- a/drivers/media/common/videobuf2/videobuf2-v4l2.c -+++ b/drivers/media/common/videobuf2/videobuf2-v4l2.c -@@ -49,8 +49,11 @@ module_param(debug, int, 0644); - V4L2_BUF_FLAG_REQUEST_FD | \ - V4L2_BUF_FLAG_TIMESTAMP_MASK) - /* Output buffer flags that should be passed on to the driver */ --#define V4L2_BUFFER_OUT_FLAGS (V4L2_BUF_FLAG_PFRAME | V4L2_BUF_FLAG_BFRAME | \ -- V4L2_BUF_FLAG_KEYFRAME | V4L2_BUF_FLAG_TIMECODE) -+#define V4L2_BUFFER_OUT_FLAGS (V4L2_BUF_FLAG_PFRAME | \ -+ V4L2_BUF_FLAG_BFRAME | \ -+ V4L2_BUF_FLAG_KEYFRAME | \ -+ V4L2_BUF_FLAG_TIMECODE | \ -+ V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF) - - /* - * __verify_planes_array() - verify that the planes array passed in struct -@@ -194,6 +197,7 @@ static int vb2_fill_vb2_v4l2_buffer(struct vb2_buffer *vb, struct v4l2_buffer *b - } - vbuf->sequence = 0; - vbuf->request_fd = -1; -+ vbuf->is_held = false; - - if (V4L2_TYPE_IS_MULTIPLANAR(b->type)) { - switch (b->memory) { -@@ -321,6 +325,8 @@ static int vb2_fill_vb2_v4l2_buffer(struct vb2_buffer *vb, struct v4l2_buffer *b - */ - vbuf->flags &= ~V4L2_BUF_FLAG_TIMECODE; - vbuf->field = b->field; -+ if (!(q->subsystem_flags & VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF)) -+ vbuf->flags &= ~V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF; - } else { - /* Zero any output buffer flags as this is a capture buffer */ - vbuf->flags &= ~V4L2_BUFFER_OUT_FLAGS; -@@ -654,6 +660,8 @@ static void fill_buf_caps(struct vb2_queue *q, u32 *caps) - *caps |= V4L2_BUF_CAP_SUPPORTS_USERPTR; - if (q->io_modes & VB2_DMABUF) - *caps |= V4L2_BUF_CAP_SUPPORTS_DMABUF; -+ if (q->subsystem_flags & VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF) -+ *caps |= V4L2_BUF_CAP_SUPPORTS_M2M_HOLD_CAPTURE_BUF; - #ifdef CONFIG_MEDIA_CONTROLLER_REQUEST_API - if (q->supports_requests) - *caps |= V4L2_BUF_CAP_SUPPORTS_REQUESTS; -diff --git a/include/media/videobuf2-core.h b/include/media/videobuf2-core.h -index 640aabe69450..a2b2208b02da 100644 ---- a/include/media/videobuf2-core.h -+++ b/include/media/videobuf2-core.h -@@ -505,6 +505,8 @@ struct vb2_buf_ops { - * @buf_ops: callbacks to deliver buffer information. - * between user-space and kernel-space. - * @drv_priv: driver private data. -+ * @subsystem_flags: Flags specific to the subsystem (V4L2/DVB/etc.). Not used -+ * by the vb2 core. - * @buf_struct_size: size of the driver-specific buffer structure; - * "0" indicates the driver doesn't want to use a custom buffer - * structure type. for example, ``sizeof(struct vb2_v4l2_buffer)`` -@@ -571,6 +573,7 @@ struct vb2_queue { - const struct vb2_buf_ops *buf_ops; - - void *drv_priv; -+ u32 subsystem_flags; - unsigned int buf_struct_size; - u32 timestamp_flags; - gfp_t gfp_flags; -diff --git a/include/media/videobuf2-v4l2.h b/include/media/videobuf2-v4l2.h -index 8a10889dc2fd..59bf33a12648 100644 ---- a/include/media/videobuf2-v4l2.h -+++ b/include/media/videobuf2-v4l2.h -@@ -33,6 +33,7 @@ - * @timecode: frame timecode. - * @sequence: sequence count of this frame. - * @request_fd: the request_fd associated with this buffer -+ * @is_held: if true, then this capture buffer was held - * @planes: plane information (userptr/fd, length, bytesused, data_offset). - * - * Should contain enough information to be able to cover all the fields -@@ -46,9 +47,13 @@ struct vb2_v4l2_buffer { - struct v4l2_timecode timecode; - __u32 sequence; - __s32 request_fd; -+ bool is_held; - struct vb2_plane planes[VB2_MAX_PLANES]; - }; - -+/* VB2 V4L2 flags as set in vb2_queue.subsystem_flags */ -+#define VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF (1 << 0) -+ - /* - * to_vb2_v4l2_buffer() - cast struct vb2_buffer * to struct vb2_v4l2_buffer * - */ -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index b3c0961b62a0..9f4e66affac4 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -920,11 +920,12 @@ struct v4l2_requestbuffers { - }; - - /* capabilities for struct v4l2_requestbuffers and v4l2_create_buffers */ --#define V4L2_BUF_CAP_SUPPORTS_MMAP (1 << 0) --#define V4L2_BUF_CAP_SUPPORTS_USERPTR (1 << 1) --#define V4L2_BUF_CAP_SUPPORTS_DMABUF (1 << 2) --#define V4L2_BUF_CAP_SUPPORTS_REQUESTS (1 << 3) --#define V4L2_BUF_CAP_SUPPORTS_ORPHANED_BUFS (1 << 4) -+#define V4L2_BUF_CAP_SUPPORTS_MMAP (1 << 0) -+#define V4L2_BUF_CAP_SUPPORTS_USERPTR (1 << 1) -+#define V4L2_BUF_CAP_SUPPORTS_DMABUF (1 << 2) -+#define V4L2_BUF_CAP_SUPPORTS_REQUESTS (1 << 3) -+#define V4L2_BUF_CAP_SUPPORTS_ORPHANED_BUFS (1 << 4) -+#define V4L2_BUF_CAP_SUPPORTS_M2M_HOLD_CAPTURE_BUF (1 << 5) - - /** - * struct v4l2_plane - plane info for multi-planar buffers -@@ -1046,6 +1047,8 @@ static inline __u64 v4l2_timeval_to_ns(const struct timeval *tv) - #define V4L2_BUF_FLAG_IN_REQUEST 0x00000080 - /* timecode field is valid */ - #define V4L2_BUF_FLAG_TIMECODE 0x00000100 -+/* Don't return the capture buffer until OUTPUT timestamp changes */ -+#define V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF 0x00000200 - /* Buffer is prepared for queuing */ - #define V4L2_BUF_FLAG_PREPARED 0x00000400 - /* Cache handling flags */ --- -2.23.0 - -From bac06ec36ea2012ff0daa9767d0f77bf9c6064ec Mon Sep 17 00:00:00 2001 -From: Hans Verkuil -Date: Fri, 11 Oct 2019 06:32:42 -0300 -Subject: [PATCH] media: videodev2.h: add V4L2_DEC_CMD_FLUSH - -Add this new V4L2_DEC_CMD_FLUSH decoder command and document it. - -Reviewed-by: Boris Brezillon -Reviewed-by: Alexandre Courbot -Signed-off-by: Hans Verkuil -Signed-off-by: Jernej Skrabec -Signed-off-by: Mauro Carvalho Chehab ---- - Documentation/media/uapi/v4l/vidioc-decoder-cmd.rst | 10 +++++++++- - Documentation/media/videodev2.h.rst.exceptions | 1 + - include/uapi/linux/videodev2.h | 1 + - 3 files changed, 11 insertions(+), 1 deletion(-) - -diff --git a/Documentation/media/uapi/v4l/vidioc-decoder-cmd.rst b/Documentation/media/uapi/v4l/vidioc-decoder-cmd.rst -index 57f0066f4cff..f1a504836f31 100644 ---- a/Documentation/media/uapi/v4l/vidioc-decoder-cmd.rst -+++ b/Documentation/media/uapi/v4l/vidioc-decoder-cmd.rst -@@ -208,7 +208,15 @@ introduced in Linux 3.3. They are, however, mandatory for stateful mem2mem decod - been started yet, the driver will return an ``EPERM`` error code. When - the decoder is already running, this command does nothing. No - flags are defined for this command. -- -+ * - ``V4L2_DEC_CMD_FLUSH`` -+ - 4 -+ - Flush any held capture buffers. Only valid for stateless decoders. -+ This command is typically used when the application reached the -+ end of the stream and the last output buffer had the -+ ``V4L2_BUF_FLAG_M2M_HOLD_CAPTURE_BUF`` flag set. This would prevent -+ dequeueing the capture buffer containing the last decoded frame. -+ So this command can be used to explicitly flush that final decoded -+ frame. This command does nothing if there are no held capture buffers. - - Return Value - ============ -diff --git a/Documentation/media/videodev2.h.rst.exceptions b/Documentation/media/videodev2.h.rst.exceptions -index b58e381bdf7b..c23e5ef30c78 100644 ---- a/Documentation/media/videodev2.h.rst.exceptions -+++ b/Documentation/media/videodev2.h.rst.exceptions -@@ -435,6 +435,7 @@ replace define V4L2_DEC_CMD_START decoder-cmds - replace define V4L2_DEC_CMD_STOP decoder-cmds - replace define V4L2_DEC_CMD_PAUSE decoder-cmds - replace define V4L2_DEC_CMD_RESUME decoder-cmds -+replace define V4L2_DEC_CMD_FLUSH decoder-cmds - - replace define V4L2_DEC_CMD_START_MUTE_AUDIO decoder-cmds - replace define V4L2_DEC_CMD_PAUSE_TO_BLACK decoder-cmds -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index 9f4e66affac4..d969842bbfe2 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -1984,6 +1984,7 @@ struct v4l2_encoder_cmd { - #define V4L2_DEC_CMD_STOP (1) - #define V4L2_DEC_CMD_PAUSE (2) - #define V4L2_DEC_CMD_RESUME (3) -+#define V4L2_DEC_CMD_FLUSH (4) - - /* Flags for V4L2_DEC_CMD_START */ - #define V4L2_DEC_CMD_START_MUTE_AUDIO (1 << 0) --- -2.23.0 - -From de06f289283298e2938445019999cec46435375c Mon Sep 17 00:00:00 2001 -From: Paul Kocialkowski -Date: Tue, 22 Oct 2019 12:26:53 -0300 -Subject: [PATCH] media: pixfmt: Document the HEVC slice pixel format - -Document the current state of the HEVC slice pixel format. -The format will need to evolve in the future, which is why it is -not part of the public API. - -Signed-off-by: Paul Kocialkowski -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../media/uapi/v4l/pixfmt-compressed.rst | 23 +++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -index 55d8d690f22f..561bda112809 100644 ---- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst -+++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -@@ -192,6 +192,29 @@ Compressed Formats - If :ref:`VIDIOC_ENUM_FMT` reports ``V4L2_FMT_FLAG_CONTINUOUS_BYTESTREAM`` - then the decoder has no requirements since it can parse all the - information from the raw bytestream. -+ * .. _V4L2-PIX-FMT-HEVC-SLICE: -+ -+ - ``V4L2_PIX_FMT_HEVC_SLICE`` -+ - 'S265' -+ - HEVC parsed slice data, as extracted from the HEVC bitstream. -+ This format is adapted for stateless video decoders that implement a -+ HEVC pipeline (using the :ref:`mem2mem` and :ref:`media-request-api`). -+ This pixelformat has two modifiers that must be set at least once -+ through the ``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE`` -+ and ``V4L2_CID_MPEG_VIDEO_HEVC_START_CODE`` controls. -+ Metadata associated with the frame to decode is required to be passed -+ through the following controls : -+ * ``V4L2_CID_MPEG_VIDEO_HEVC_SPS`` -+ * ``V4L2_CID_MPEG_VIDEO_HEVC_PPS`` -+ * ``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS`` -+ See the :ref:`associated Codec Control IDs `. -+ Buffers associated with this pixel format must contain the appropriate -+ number of macroblocks to decode a full corresponding frame. -+ -+ .. note:: -+ -+ This format is not yet part of the public kernel API and it -+ is expected to change. - * .. _V4L2-PIX-FMT-FWHT: - - - ``V4L2_PIX_FMT_FWHT`` --- -2.23.0 - -From b4e33e09e7938513bfaba034731c7e84e73c6a5b Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 26 Oct 2019 09:27:51 +0200 -Subject: [PATCH] media: cedrus: Fix decoding for some H264 videos - -It seems that for some H264 videos at least one bitstream parsing -trigger must be called in order to be decoded correctly. There is no -explanation why this helps, but it was observed that two sample videos -with this fix are now decoded correctly and there is no regression with -others. - -Acked-by: Paul Kocialkowski -Signed-off-by: Jernej Skrabec -Signed-off-by: Hans Verkuil ---- - .../staging/media/sunxi/cedrus/cedrus_h264.c | 30 +++++++++++++++++-- - .../staging/media/sunxi/cedrus/cedrus_regs.h | 3 ++ - 2 files changed, 30 insertions(+), 3 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -index cd85668f9c80..db336449c4f2 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -@@ -6,6 +6,7 @@ - * Copyright (c) 2018 Bootlin - */ - -+#include - #include - - #include -@@ -289,6 +290,28 @@ static void cedrus_write_pred_weight_table(struct cedrus_ctx *ctx, - } - } - -+/* -+ * It turns out that using VE_H264_VLD_OFFSET to skip bits is not reliable. In -+ * rare cases frame is not decoded correctly. However, setting offset to 0 and -+ * skipping appropriate amount of bits with flush bits trigger always works. -+ */ -+static void cedrus_skip_bits(struct cedrus_dev *dev, int num) -+{ -+ int count = 0; -+ -+ while (count < num) { -+ int tmp = min(num - count, 32); -+ -+ cedrus_write(dev, VE_H264_TRIGGER_TYPE, -+ VE_H264_TRIGGER_TYPE_FLUSH_BITS | -+ VE_H264_TRIGGER_TYPE_N_BITS(tmp)); -+ while (cedrus_read(dev, VE_H264_STATUS) & VE_H264_STATUS_VLD_BUSY) -+ udelay(1); -+ -+ count += tmp; -+ } -+} -+ - static void cedrus_set_params(struct cedrus_ctx *ctx, - struct cedrus_run *run) - { -@@ -299,14 +322,13 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, - struct vb2_buffer *src_buf = &run->src->vb2_buf; - struct cedrus_dev *dev = ctx->dev; - dma_addr_t src_buf_addr; -- u32 offset = slice->header_bit_size; -- u32 len = (slice->size * 8) - offset; -+ u32 len = slice->size * 8; - unsigned int pic_width_in_mbs; - bool mbaff_pic; - u32 reg; - - cedrus_write(dev, VE_H264_VLD_LEN, len); -- cedrus_write(dev, VE_H264_VLD_OFFSET, offset); -+ cedrus_write(dev, VE_H264_VLD_OFFSET, 0); - - src_buf_addr = vb2_dma_contig_plane_dma_addr(src_buf, 0); - cedrus_write(dev, VE_H264_VLD_END, -@@ -325,6 +347,8 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, - cedrus_write(dev, VE_H264_TRIGGER_TYPE, - VE_H264_TRIGGER_TYPE_INIT_SWDEC); - -+ cedrus_skip_bits(dev, slice->header_bit_size); -+ - if (((pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && - (slice->slice_type == V4L2_H264_SLICE_TYPE_P || - slice->slice_type == V4L2_H264_SLICE_TYPE_SP)) || -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -index 6fc28d21a6c7..4275a307d282 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -@@ -541,13 +541,16 @@ - VE_H264_CTRL_SLICE_DECODE_INT) - - #define VE_H264_TRIGGER_TYPE 0x224 -+#define VE_H264_TRIGGER_TYPE_N_BITS(x) (((x) & 0x3f) << 8) - #define VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE (8 << 0) - #define VE_H264_TRIGGER_TYPE_INIT_SWDEC (7 << 0) -+#define VE_H264_TRIGGER_TYPE_FLUSH_BITS (3 << 0) - - #define VE_H264_STATUS 0x228 - #define VE_H264_STATUS_VLD_DATA_REQ_INT VE_H264_CTRL_VLD_DATA_REQ_INT - #define VE_H264_STATUS_DECODE_ERR_INT VE_H264_CTRL_DECODE_ERR_INT - #define VE_H264_STATUS_SLICE_DECODE_INT VE_H264_CTRL_SLICE_DECODE_INT -+#define VE_H264_STATUS_VLD_BUSY BIT(8) - - #define VE_H264_STATUS_INT_MASK VE_H264_CTRL_INT_MASK - --- -2.24.0 - -From 7119ecef4e5ec51e45e6fbe1b5da4385fcae8ded Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 6 Nov 2019 08:02:53 +0100 -Subject: [PATCH] media: v4l2-mem2mem: Fix hold buf flag checks - -Hold buf flag is set on output queue, not capture. Fix that. - -Fixes: f07602ac3887 ("media: v4l2-mem2mem: add new_frame detection") -Signed-off-by: Jernej Skrabec -Signed-off-by: Hans Verkuil ---- - drivers/media/v4l2-core/v4l2-mem2mem.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c -index db07ef3bf3d0..1afd9c6ad908 100644 ---- a/drivers/media/v4l2-core/v4l2-mem2mem.c -+++ b/drivers/media/v4l2-core/v4l2-mem2mem.c -@@ -335,7 +335,7 @@ static void __v4l2_m2m_try_queue(struct v4l2_m2m_dev *m2m_dev, - } - } - -- if (src && dst && (m2m_ctx->cap_q_ctx.q.subsystem_flags & -+ if (src && dst && (m2m_ctx->out_q_ctx.q.subsystem_flags & - VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF)) - m2m_ctx->new_frame = !dst->vb2_buf.copied_timestamp || - dst->vb2_buf.timestamp != src->vb2_buf.timestamp; -@@ -474,7 +474,7 @@ void v4l2_m2m_job_finish(struct v4l2_m2m_dev *m2m_dev, - * holding capture buffers. Those should use - * v4l2_m2m_buf_done_and_job_finish() instead. - */ -- WARN_ON(m2m_ctx->cap_q_ctx.q.subsystem_flags & -+ WARN_ON(m2m_ctx->out_q_ctx.q.subsystem_flags & - VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF); - spin_lock_irqsave(&m2m_dev->job_spinlock, flags); - schedule_next = _v4l2_m2m_job_finish(m2m_dev, m2m_ctx); --- -2.24.0 - -From 3aef46bd5bf24a845e05d2531ed61f53ee8c7797 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 10 Nov 2019 07:30:01 +0100 -Subject: [PATCH 1/3] media: cedrus: Properly signal size in mode register - -Mode register also holds information if video width is bigger than 2048 -and if it is equal to 4096. - -Rework cedrus_engine_enable() to properly signal this properties. - -Signed-off-by: Jernej Skrabec -Acked-by: Paul Kocialkowski -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 2 +- - drivers/staging/media/sunxi/cedrus/cedrus_h265.c | 2 +- - drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 9 +++++++-- - drivers/staging/media/sunxi/cedrus/cedrus_hw.h | 2 +- - drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c | 2 +- - drivers/staging/media/sunxi/cedrus/cedrus_regs.h | 2 ++ - 6 files changed, 13 insertions(+), 6 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -index 74e4c5e3894e..8a09a08b1af2 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -@@ -485,7 +485,7 @@ static void cedrus_h264_setup(struct cedrus_ctx *ctx, - { - struct cedrus_dev *dev = ctx->dev; - -- cedrus_engine_enable(dev, CEDRUS_CODEC_H264); -+ cedrus_engine_enable(ctx, CEDRUS_CODEC_H264); - - cedrus_write(dev, VE_H264_SDROT_CTRL, 0); - cedrus_write(dev, VE_H264_EXTRA_BUFFER1, -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -index 9bc921866f70..6945dc74e1d7 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -@@ -276,7 +276,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, - } - - /* Activate H265 engine. */ -- cedrus_engine_enable(dev, CEDRUS_CODEC_H265); -+ cedrus_engine_enable(ctx, CEDRUS_CODEC_H265); - - /* Source offset and length in bits. */ - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -index 93347d3ba360..daf5f244f93b 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -@@ -30,7 +30,7 @@ - #include "cedrus_hw.h" - #include "cedrus_regs.h" - --int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) -+int cedrus_engine_enable(struct cedrus_ctx *ctx, enum cedrus_codec codec) - { - u32 reg = 0; - -@@ -58,7 +58,12 @@ int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) - return -EINVAL; - } - -- cedrus_write(dev, VE_MODE, reg); -+ if (ctx->src_fmt.width == 4096) -+ reg |= VE_MODE_PIC_WIDTH_IS_4096; -+ if (ctx->src_fmt.width > 2048) -+ reg |= VE_MODE_PIC_WIDTH_MORE_2048; -+ -+ cedrus_write(ctx->dev, VE_MODE, reg); - - return 0; - } -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -index 27d0882397aa..604ff932fbf5 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -@@ -16,7 +16,7 @@ - #ifndef _CEDRUS_HW_H_ - #define _CEDRUS_HW_H_ - --int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec); -+int cedrus_engine_enable(struct cedrus_ctx *ctx, enum cedrus_codec codec); - void cedrus_engine_disable(struct cedrus_dev *dev); - - void cedrus_dst_format_set(struct cedrus_dev *dev, -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c b/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c -index 13c34927bad5..8bcd6b8f9e2d 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c -@@ -96,7 +96,7 @@ static void cedrus_mpeg2_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) - quantization = run->mpeg2.quantization; - - /* Activate MPEG engine. */ -- cedrus_engine_enable(dev, CEDRUS_CODEC_MPEG2); -+ cedrus_engine_enable(ctx, CEDRUS_CODEC_MPEG2); - - /* Set intra quantization matrix. */ - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -index 4275a307d282..ace3d49fcd82 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -@@ -35,6 +35,8 @@ - - #define VE_MODE 0x00 - -+#define VE_MODE_PIC_WIDTH_IS_4096 BIT(22) -+#define VE_MODE_PIC_WIDTH_MORE_2048 BIT(21) - #define VE_MODE_REC_WR_MODE_2MB (0x01 << 20) - #define VE_MODE_REC_WR_MODE_1MB (0x00 << 20) - #define VE_MODE_DDR_MODE_BW_128 (0x03 << 16) --- -2.24.0 - - -From 03e612e701a61aa9cc9fd8e25cd47d8d685ef675 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 6 Nov 2019 22:05:37 +0100 -Subject: [PATCH 2/3] media: cedrus: Fix H264 4k support - -H264 decoder needs additional or bigger buffers in order to decode 4k -videos. - -Signed-off-by: Jernej Skrabec -Acked-by: Paul Kocialkowski -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/sunxi/cedrus/cedrus.h | 7 ++ - .../staging/media/sunxi/cedrus/cedrus_h264.c | 91 +++++++++++++++++-- - .../staging/media/sunxi/cedrus/cedrus_regs.h | 11 +++ - 3 files changed, 101 insertions(+), 8 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index c45fb9a7ad07..96765555ab8a 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -116,8 +116,15 @@ struct cedrus_ctx { - ssize_t mv_col_buf_size; - void *pic_info_buf; - dma_addr_t pic_info_buf_dma; -+ ssize_t pic_info_buf_size; - void *neighbor_info_buf; - dma_addr_t neighbor_info_buf_dma; -+ void *deblk_buf; -+ dma_addr_t deblk_buf_dma; -+ ssize_t deblk_buf_size; -+ void *intra_pred_buf; -+ dma_addr_t intra_pred_buf_dma; -+ ssize_t intra_pred_buf_size; - } h264; - struct { - void *mv_col_buf; -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -index 8a09a08b1af2..bfb4a4820a67 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -@@ -39,7 +39,7 @@ struct cedrus_h264_sram_ref_pic { - #define CEDRUS_H264_FRAME_NUM 18 - - #define CEDRUS_NEIGHBOR_INFO_BUF_SIZE (16 * SZ_1K) --#define CEDRUS_PIC_INFO_BUF_SIZE (128 * SZ_1K) -+#define CEDRUS_MIN_PIC_INFO_BUF_SIZE (130 * SZ_1K) - - static void cedrus_h264_write_sram(struct cedrus_dev *dev, - enum cedrus_h264_sram_off off, -@@ -342,6 +342,20 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, - VE_H264_VLD_ADDR_FIRST | VE_H264_VLD_ADDR_VALID | - VE_H264_VLD_ADDR_LAST); - -+ if (ctx->src_fmt.width > 2048) { -+ cedrus_write(dev, VE_BUF_CTRL, -+ VE_BUF_CTRL_INTRAPRED_MIXED_RAM | -+ VE_BUF_CTRL_DBLK_MIXED_RAM); -+ cedrus_write(dev, VE_DBLK_DRAM_BUF_ADDR, -+ ctx->codec.h264.deblk_buf_dma); -+ cedrus_write(dev, VE_INTRAPRED_DRAM_BUF_ADDR, -+ ctx->codec.h264.intra_pred_buf_dma); -+ } else { -+ cedrus_write(dev, VE_BUF_CTRL, -+ VE_BUF_CTRL_INTRAPRED_INT_SRAM | -+ VE_BUF_CTRL_DBLK_INT_SRAM); -+ } -+ - /* - * FIXME: Since the bitstream parsing is done in software, and - * in userspace, this shouldn't be needed anymore. But it -@@ -502,18 +516,30 @@ static void cedrus_h264_setup(struct cedrus_ctx *ctx, - static int cedrus_h264_start(struct cedrus_ctx *ctx) - { - struct cedrus_dev *dev = ctx->dev; -+ unsigned int pic_info_size; - unsigned int field_size; - unsigned int mv_col_size; - int ret; - -+ /* Formula for picture buffer size is taken from CedarX source. */ -+ -+ if (ctx->src_fmt.width > 2048) -+ pic_info_size = CEDRUS_H264_FRAME_NUM * 0x4000; -+ else -+ pic_info_size = CEDRUS_H264_FRAME_NUM * 0x1000; -+ - /* -- * FIXME: It seems that the H6 cedarX code is using a formula -- * here based on the size of the frame, while all the older -- * code is using a fixed size, so that might need to be -- * changed at some point. -+ * FIXME: If V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY is set, -+ * there is no need to multiply by 2. - */ -+ pic_info_size += ctx->src_fmt.height * 2 * 64; -+ -+ if (pic_info_size < CEDRUS_MIN_PIC_INFO_BUF_SIZE) -+ pic_info_size = CEDRUS_MIN_PIC_INFO_BUF_SIZE; -+ -+ ctx->codec.h264.pic_info_buf_size = pic_info_size; - ctx->codec.h264.pic_info_buf = -- dma_alloc_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, -+ dma_alloc_coherent(dev->dev, ctx->codec.h264.pic_info_buf_size, - &ctx->codec.h264.pic_info_buf_dma, - GFP_KERNEL); - if (!ctx->codec.h264.pic_info_buf) -@@ -566,15 +592,56 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx) - goto err_neighbor_buf; - } - -+ if (ctx->src_fmt.width > 2048) { -+ /* -+ * Formulas for deblock and intra prediction buffer sizes -+ * are taken from CedarX source. -+ */ -+ -+ ctx->codec.h264.deblk_buf_size = -+ ALIGN(ctx->src_fmt.width, 32) * 12; -+ ctx->codec.h264.deblk_buf = -+ dma_alloc_coherent(dev->dev, -+ ctx->codec.h264.deblk_buf_size, -+ &ctx->codec.h264.deblk_buf_dma, -+ GFP_KERNEL); -+ if (!ctx->codec.h264.deblk_buf) { -+ ret = -ENOMEM; -+ goto err_mv_col_buf; -+ } -+ -+ ctx->codec.h264.intra_pred_buf_size = -+ ALIGN(ctx->src_fmt.width, 64) * 5; -+ ctx->codec.h264.intra_pred_buf = -+ dma_alloc_coherent(dev->dev, -+ ctx->codec.h264.intra_pred_buf_size, -+ &ctx->codec.h264.intra_pred_buf_dma, -+ GFP_KERNEL); -+ if (!ctx->codec.h264.intra_pred_buf) { -+ ret = -ENOMEM; -+ goto err_deblk_buf; -+ } -+ } -+ - return 0; - -+err_deblk_buf: -+ dma_free_coherent(dev->dev, ctx->codec.h264.deblk_buf_size, -+ ctx->codec.h264.deblk_buf, -+ ctx->codec.h264.deblk_buf_dma); -+ -+err_mv_col_buf: -+ dma_free_coherent(dev->dev, ctx->codec.h264.mv_col_buf_size, -+ ctx->codec.h264.mv_col_buf, -+ ctx->codec.h264.mv_col_buf_dma); -+ - err_neighbor_buf: - dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, - ctx->codec.h264.neighbor_info_buf, - ctx->codec.h264.neighbor_info_buf_dma); - - err_pic_buf: -- dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, -+ dma_free_coherent(dev->dev, ctx->codec.h264.pic_info_buf_size, - ctx->codec.h264.pic_info_buf, - ctx->codec.h264.pic_info_buf_dma); - return ret; -@@ -590,9 +657,17 @@ static void cedrus_h264_stop(struct cedrus_ctx *ctx) - dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, - ctx->codec.h264.neighbor_info_buf, - ctx->codec.h264.neighbor_info_buf_dma); -- dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, -+ dma_free_coherent(dev->dev, ctx->codec.h264.pic_info_buf_size, - ctx->codec.h264.pic_info_buf, - ctx->codec.h264.pic_info_buf_dma); -+ if (ctx->codec.h264.deblk_buf_size) -+ dma_free_coherent(dev->dev, ctx->codec.h264.deblk_buf_size, -+ ctx->codec.h264.deblk_buf, -+ ctx->codec.h264.deblk_buf_dma); -+ if (ctx->codec.h264.intra_pred_buf_size) -+ dma_free_coherent(dev->dev, ctx->codec.h264.intra_pred_buf_size, -+ ctx->codec.h264.intra_pred_buf, -+ ctx->codec.h264.intra_pred_buf_dma); - } - - static void cedrus_h264_trigger(struct cedrus_ctx *ctx) -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -index ace3d49fcd82..7beb03d3bb39 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -@@ -46,6 +46,17 @@ - #define VE_MODE_DEC_H264 (0x01 << 0) - #define VE_MODE_DEC_MPEG (0x00 << 0) - -+#define VE_BUF_CTRL 0x50 -+ -+#define VE_BUF_CTRL_INTRAPRED_EXT_RAM (0x02 << 2) -+#define VE_BUF_CTRL_INTRAPRED_MIXED_RAM (0x01 << 2) -+#define VE_BUF_CTRL_INTRAPRED_INT_SRAM (0x00 << 2) -+#define VE_BUF_CTRL_DBLK_EXT_RAM (0x02 << 0) -+#define VE_BUF_CTRL_DBLK_MIXED_RAM (0x01 << 0) -+#define VE_BUF_CTRL_DBLK_INT_SRAM (0x00 << 0) -+ -+#define VE_DBLK_DRAM_BUF_ADDR 0x54 -+#define VE_INTRAPRED_DRAM_BUF_ADDR 0x58 - #define VE_PRIMARY_CHROMA_BUF_LEN 0xc4 - #define VE_PRIMARY_FB_LINE_STRIDE 0xc8 - --- -2.24.0 - - -From 0b3e5c15f9cb8b56599c50e6bf4f46ee1c1253bc Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 6 Nov 2019 22:05:38 +0100 -Subject: [PATCH 3/3] media: cedrus: Increase maximum supported size - -There are few variations of 4k resolutions. The biggest one is -4096x2304 which is also supported by HW. It has also nice property that -both width and size are divisible by maximum HEVC CTB size, which is 64. - -Signed-off-by: Jernej Skrabec -Acked-by: Paul Kocialkowski -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/sunxi/cedrus/cedrus_video.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index cc15a5cf107d..15cf1f10221b 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -29,8 +29,8 @@ - - #define CEDRUS_MIN_WIDTH 16U - #define CEDRUS_MIN_HEIGHT 16U --#define CEDRUS_MAX_WIDTH 3840U --#define CEDRUS_MAX_HEIGHT 2160U -+#define CEDRUS_MAX_WIDTH 4096U -+#define CEDRUS_MAX_HEIGHT 2304U - - static struct cedrus_format cedrus_formats[] = { - { --- -2.24.0 - - -From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= -Subject: [PATCH v7 1/2] arm64: dts: allwinner: Add ARM Mali GPU node for H6 -Date: Wed, 30 Oct 2019 16:07:41 +0100 - -Add the mali gpu node to the H6 device-tree. - -Signed-off-by: Clément Péron ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 0d5ea19336a1..a029daf67345 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -149,6 +149,20 @@ - allwinner,sram = <&ve_sram 1>; - }; - -+ gpu: gpu@1800000 { -+ compatible = "allwinner,sun50i-h6-mali", -+ "arm,mali-t720"; -+ reg = <0x01800000 0x4000>; -+ interrupts = , -+ , -+ ; -+ interrupt-names = "job", "mmu", "gpu"; -+ clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; -+ clock-names = "core", "bus"; -+ resets = <&ccu RST_BUS_GPU>; -+ status = "disabled"; -+ }; -+ - syscon: syscon@3000000 { - compatible = "allwinner,sun50i-h6-system-control", - "allwinner,sun50i-a64-system-control"; - - -From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= -Subject: [PATCH v7 2/2] arm64: dts: allwinner: Add mali GPU supply for H6 - boards -Date: Wed, 30 Oct 2019 16:07:42 +0100 - -Enable and add supply to the Mali GPU node on all the -H6 boards. - -Regarding the datasheet the maximum time for supply to reach -its voltage is 32ms. - -Signed-off-by: Clément Péron ---- - arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 6 ++++++ - arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 6 ++++++ - arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 6 ++++++ - arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 6 ++++++ - 4 files changed, 24 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -index 1d05d570142f..e5ed1d4bfef8 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -@@ -89,6 +89,11 @@ - status = "okay"; - }; - -+&gpu { -+ mali-supply = <®_dcdcc>; -+ status = "okay"; -+}; -+ - &hdmi { - status = "okay"; - }; -@@ -225,6 +230,7 @@ - }; - - reg_dcdcc: dcdcc { -+ regulator-enable-ramp-delay = <32000>; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-gpu"; -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -index eb379cd402ac..f5ae5182f0c5 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -@@ -102,6 +102,11 @@ - status = "okay"; - }; - -+&gpu { -+ mali-supply = <®_dcdcc>; -+ status = "okay"; -+}; -+ - &hdmi { - status = "okay"; - }; -@@ -237,6 +242,7 @@ - }; - - reg_dcdcc: dcdcc { -+ regulator-enable-ramp-delay = <32000>; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-gpu"; -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -index ec9b6a578e3f..df4cbd7ef96c 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi -@@ -55,6 +55,11 @@ - status = "okay"; - }; - -+&gpu { -+ mali-supply = <®_dcdcc>; -+ status = "okay"; -+}; -+ - &mmc0 { - vmmc-supply = <®_cldo1>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; -@@ -163,6 +168,7 @@ - }; - - reg_dcdcc: dcdcc { -+ regulator-enable-ramp-delay = <32000>; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-gpu"; -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -index 30102daf83cc..74899ede00fb 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -@@ -85,6 +85,11 @@ - status = "okay"; - }; - -+&gpu { -+ mali-supply = <®_dcdcc>; -+ status = "okay"; -+}; -+ - &hdmi { - status = "okay"; - }; -@@ -221,6 +226,7 @@ - }; - - reg_dcdcc: dcdcc { -+ regulator-enable-ramp-delay = <32000>; - regulator-min-microvolt = <810000>; - regulator-max-microvolt = <1080000>; - regulator-name = "vdd-gpu"; - - -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Sat, 2 Nov 2019 13:04:27 +0100 -Subject: arm64: allwinner: h6: Enable GPU node for Tanix TX6 - -Unlike other H6 boards, Tanix TX6 doesn't have a PMIC so we can enable -the GPU without providing a specific power supply. - -Signed-off-by: Clément Péron -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -index 7e7cb10e3d96..bccfe1e65b6a 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -@@ -53,6 +53,10 @@ - status = "okay"; - }; - -+&gpu { -+ status = "okay"; -+}; -+ - &hdmi { - status = "okay"; - }; -From a228890f94586c2f8417831c228ac8ed955ef856 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Tue, 29 Oct 2019 21:17:39 +0100 -Subject: [PATCH] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 - SoC - -Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also -controlled). - -Add a driver for it. - -The register operations in this driver is mainly extracted from the BSP -USB3 driver. - -Signed-off-by: Ondrej Jirman -Signed-off-by: Icenowy Zheng -Reviewed-by: Chen-Yu Tsai -Acked-by: Maxime Ripard -Signed-off-by: Kishon Vijay Abraham I ---- - drivers/phy/allwinner/Kconfig | 11 ++ - drivers/phy/allwinner/Makefile | 1 + - drivers/phy/allwinner/phy-sun50i-usb3.c | 190 ++++++++++++++++++++++++ - 3 files changed, 202 insertions(+) - create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c - -diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig -index 215425296c77..3dab79e9d52b 100644 ---- a/drivers/phy/allwinner/Kconfig -+++ b/drivers/phy/allwinner/Kconfig -@@ -45,3 +45,14 @@ config PHY_SUN9I_USB - sun9i SoCs. - - This driver controls each individual USB 2 host PHY. -+ -+config PHY_SUN50I_USB3 -+ tristate "Allwinner H6 SoC USB3 PHY driver" -+ depends on ARCH_SUNXI && HAS_IOMEM && OF -+ depends on RESET_CONTROLLER -+ select GENERIC_PHY -+ help -+ Enable this to support the USB3.0-capable transceiver that is -+ part of Allwinner H6 SoC. -+ -+ This driver controls each individual USB 2+3 host PHY combo. -diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile -index 799a65c0b58d..bd74901a1255 100644 ---- a/drivers/phy/allwinner/Makefile -+++ b/drivers/phy/allwinner/Makefile -@@ -2,3 +2,4 @@ - obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o - obj-$(CONFIG_PHY_SUN6I_MIPI_DPHY) += phy-sun6i-mipi-dphy.o - obj-$(CONFIG_PHY_SUN9I_USB) += phy-sun9i-usb.o -+obj-$(CONFIG_PHY_SUN50I_USB3) += phy-sun50i-usb3.o -diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c b/drivers/phy/allwinner/phy-sun50i-usb3.c -new file mode 100644 -index 000000000000..1169f3e83a6f ---- /dev/null -+++ b/drivers/phy/allwinner/phy-sun50i-usb3.c -@@ -0,0 +1,190 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Allwinner sun50i(H6) USB 3.0 phy driver -+ * -+ * Copyright (C) 2017 Icenowy Zheng -+ * -+ * Based on phy-sun9i-usb.c, which is: -+ * -+ * Copyright (C) 2014-2015 Chen-Yu Tsai -+ * -+ * Based on code from Allwinner BSP, which is: -+ * -+ * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Interface Status and Control Registers */ -+#define SUNXI_ISCR 0x00 -+#define SUNXI_PIPE_CLOCK_CONTROL 0x14 -+#define SUNXI_PHY_TUNE_LOW 0x18 -+#define SUNXI_PHY_TUNE_HIGH 0x1c -+#define SUNXI_PHY_EXTERNAL_CONTROL 0x20 -+ -+/* USB2.0 Interface Status and Control Register */ -+#define SUNXI_ISCR_FORCE_VBUS (3 << 12) -+ -+/* PIPE Clock Control Register */ -+#define SUNXI_PCC_PIPE_CLK_OPEN (1 << 6) -+ -+/* PHY External Control Register */ -+#define SUNXI_PEC_EXTERN_VBUS (3 << 1) -+#define SUNXI_PEC_SSC_EN (1 << 24) -+#define SUNXI_PEC_REF_SSP_EN (1 << 26) -+ -+/* PHY Tune High Register */ -+#define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19) -+#define SUNXI_TX_DEEMPH_3P5DB_MASK GENMASK(24, 19) -+#define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13) -+#define SUNXI_TX_DEEMPH_6GB_MASK GENMASK(18, 13) -+#define SUNXI_TX_SWING_FULL(n) ((n) << 6) -+#define SUNXI_TX_SWING_FULL_MASK GENMASK(12, 6) -+#define SUNXI_LOS_BIAS(n) ((n) << 3) -+#define SUNXI_LOS_BIAS_MASK GENMASK(5, 3) -+#define SUNXI_TXVBOOSTLVL(n) ((n) << 0) -+#define SUNXI_TXVBOOSTLVL_MASK GENMASK(0, 2) -+ -+struct sun50i_usb3_phy { -+ struct phy *phy; -+ void __iomem *regs; -+ struct reset_control *reset; -+ struct clk *clk; -+}; -+ -+static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy) -+{ -+ u32 val; -+ -+ val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL); -+ val |= SUNXI_PEC_EXTERN_VBUS; -+ val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN; -+ writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL); -+ -+ val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL); -+ val |= SUNXI_PCC_PIPE_CLK_OPEN; -+ writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL); -+ -+ val = readl(phy->regs + SUNXI_ISCR); -+ val |= SUNXI_ISCR_FORCE_VBUS; -+ writel(val, phy->regs + SUNXI_ISCR); -+ -+ /* -+ * All the magic numbers written to the PHY_TUNE_{LOW_HIGH} -+ * registers are directly taken from the BSP USB3 driver from -+ * Allwiner. -+ */ -+ writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW); -+ -+ val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH); -+ val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK | -+ SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK | -+ SUNXI_TX_DEEMPH_3P5DB_MASK); -+ val |= SUNXI_TXVBOOSTLVL(0x7); -+ val |= SUNXI_LOS_BIAS(0x7); -+ val |= SUNXI_TX_SWING_FULL(0x55); -+ val |= SUNXI_TX_DEEMPH_6DB(0x20); -+ val |= SUNXI_TX_DEEMPH_3P5DB(0x15); -+ writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH); -+} -+ -+static int sun50i_usb3_phy_init(struct phy *_phy) -+{ -+ struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy); -+ int ret; -+ -+ ret = clk_prepare_enable(phy->clk); -+ if (ret) -+ return ret; -+ -+ ret = reset_control_deassert(phy->reset); -+ if (ret) { -+ clk_disable_unprepare(phy->clk); -+ return ret; -+ } -+ -+ sun50i_usb3_phy_open(phy); -+ return 0; -+} -+ -+static int sun50i_usb3_phy_exit(struct phy *_phy) -+{ -+ struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy); -+ -+ reset_control_assert(phy->reset); -+ clk_disable_unprepare(phy->clk); -+ -+ return 0; -+} -+ -+static const struct phy_ops sun50i_usb3_phy_ops = { -+ .init = sun50i_usb3_phy_init, -+ .exit = sun50i_usb3_phy_exit, -+ .owner = THIS_MODULE, -+}; -+ -+static int sun50i_usb3_phy_probe(struct platform_device *pdev) -+{ -+ struct sun50i_usb3_phy *phy; -+ struct device *dev = &pdev->dev; -+ struct phy_provider *phy_provider; -+ struct resource *res; -+ -+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); -+ if (!phy) -+ return -ENOMEM; -+ -+ phy->clk = devm_clk_get(dev, NULL); -+ if (IS_ERR(phy->clk)) { -+ if (PTR_ERR(phy->clk) != -EPROBE_DEFER) -+ dev_err(dev, "failed to get phy clock\n"); -+ return PTR_ERR(phy->clk); -+ } -+ -+ phy->reset = devm_reset_control_get(dev, NULL); -+ if (IS_ERR(phy->reset)) { -+ dev_err(dev, "failed to get reset control\n"); -+ return PTR_ERR(phy->reset); -+ } -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ phy->regs = devm_ioremap_resource(dev, res); -+ if (IS_ERR(phy->regs)) -+ return PTR_ERR(phy->regs); -+ -+ phy->phy = devm_phy_create(dev, NULL, &sun50i_usb3_phy_ops); -+ if (IS_ERR(phy->phy)) { -+ dev_err(dev, "failed to create PHY\n"); -+ return PTR_ERR(phy->phy); -+ } -+ -+ phy_set_drvdata(phy->phy, phy); -+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); -+ -+ return PTR_ERR_OR_ZERO(phy_provider); -+} -+ -+static const struct of_device_id sun50i_usb3_phy_of_match[] = { -+ { .compatible = "allwinner,sun50i-h6-usb3-phy" }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, sun50i_usb3_phy_of_match); -+ -+static struct platform_driver sun50i_usb3_phy_driver = { -+ .probe = sun50i_usb3_phy_probe, -+ .driver = { -+ .of_match_table = sun50i_usb3_phy_of_match, -+ .name = "sun50i-usb3-phy", -+ } -+}; -+module_platform_driver(sun50i_usb3_phy_driver); -+ -+MODULE_DESCRIPTION("Allwinner H6 USB 3.0 phy driver"); -+MODULE_AUTHOR("Icenowy Zheng "); -+MODULE_LICENSE("GPL"); --- -2.24.1 - -From 0b6f7014adc1cc12c7c3ba988594514602919eca Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Sun, 20 Oct 2019 15:42:28 +0200 -Subject: [PATCH] arm64: dts: allwinner: h6: add USB3 device nodes - -Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and -a custom PHY. - -Add device tree nodes for them. - -Signed-off-by: Ondrej Jirman -Signed-off-by: Icenowy Zheng -Reviewed-by: Chen-Yu Tsai -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 32 ++++++++++++++++++++ - 1 file changed, 32 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 4abfed2e9ff6..8f3f81725fb7 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -570,6 +570,38 @@ ohci0: usb@5101400 { - status = "disabled"; - }; - -+ dwc3: dwc3@5200000 { -+ compatible = "snps,dwc3"; -+ reg = <0x05200000 0x10000>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_XHCI>, -+ <&ccu CLK_BUS_XHCI>, -+ <&rtc 0>; -+ clock-names = "ref", "bus_early", "suspend"; -+ resets = <&ccu RST_BUS_XHCI>; -+ /* -+ * The datasheet of the chip doesn't declare the -+ * peripheral function, and there's no boards known -+ * to have a USB Type-B port routed to the port. -+ * In addition, no one has tested the peripheral -+ * function yet. -+ * So set the dr_mode to "host" in the DTSI file. -+ */ -+ dr_mode = "host"; -+ phys = <&usb3phy>; -+ phy-names = "usb3-phy"; -+ status = "disabled"; -+ }; -+ -+ usb3phy: phy@5210000 { -+ compatible = "allwinner,sun50i-h6-usb3-phy"; -+ reg = <0x5210000 0x10000>; -+ clocks = <&ccu CLK_USB_PHY1>; -+ resets = <&ccu RST_USB_PHY1>; -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ - ehci3: usb@5311000 { - compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; - reg = <0x05311000 0x100>; --- -2.24.1 - -From b5d84ff8ae180e443623ede8a16852f671b0bb05 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Sun, 20 Oct 2019 15:42:29 +0200 -Subject: [PATCH] arm64: dts: allwinner: orange-pi-3: Enable USB 3.0 host - support - -Enable Allwinner's USB 3.0 phy and the host controller. Orange Pi 3 -board has GL3510 USB 3.0 4-port hub connected to the SoC's USB 3.0 -port. All four ports are exposed via USB3-A connectors. VBUS is -always on, since it's powered directly from DCIN (VCC-5V) and -not switchable. - -Signed-off-by: Ondrej Jirman -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -index b99e9db35d50..4ed3fc2c7734 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts -@@ -95,6 +95,10 @@ &de { - status = "okay"; - }; - -+&dwc3 { -+ status = "okay"; -+}; -+ - &ehci0 { - status = "okay"; - }; -@@ -310,3 +314,7 @@ &usb2phy { - usb3_vbus-supply = <®_vcc5v>; - status = "okay"; - }; -+ -+&usb3phy { -+ status = "okay"; -+}; --- -2.24.1 - -From 6555431ba2c58ac3a2fccde2b92607437577cc8f Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Sun, 27 Oct 2019 21:07:38 +0100 -Subject: [PATCH] media: arm64: dts: allwinner: beelink-gs1: Add rc-beelink-gs1 - keymap -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Beelink GS1 ships with a NEC remote control. - -Add the rc keymap to the device-tree. - -Signed-off-by: Clément Péron -Signed-off-by: Sean Young -Signed-off-by: Mauro Carvalho Chehab ---- - arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -index 1d05d570142f..ce4b0679839d 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts -@@ -252,6 +252,7 @@ sw { - }; - - &r_ir { -+ linux,rc-map-name = "rc-beelink-gs1"; - status = "okay"; - }; - --- -2.24.1 - -From d2f383d6b8cd85cbb0e8ebece4ef9408237eef68 Mon Sep 17 00:00:00 2001 -From: Jisheng Zhang -Date: Fri, 11 Oct 2019 05:25:20 -0300 -Subject: [PATCH] media: rc-map: Sort rc map name MACROs - -Some MACROS such as RC_MAP_SU3000 and RC_MAP_HAUPPAUGE are not -alphabetically sorted. Sort names alphabetically. - -Signed-off-by: Jisheng Zhang -Signed-off-by: Sean Young -Signed-off-by: Mauro Carvalho Chehab ---- - include/media/rc-map.h | 22 +++++++++++----------- - 1 file changed, 11 insertions(+), 11 deletions(-) - -diff --git a/include/media/rc-map.h b/include/media/rc-map.h -index 04b5efc1fe39..0a8669daeaaa 100644 ---- a/include/media/rc-map.h -+++ b/include/media/rc-map.h -@@ -159,21 +159,21 @@ struct rc_map *rc_map_get(const char *name); - #define RC_MAP_ASUS_PS3_100 "rc-asus-ps3-100" - #define RC_MAP_ATI_TV_WONDER_HD_600 "rc-ati-tv-wonder-hd-600" - #define RC_MAP_ATI_X10 "rc-ati-x10" -+#define RC_MAP_AVERMEDIA "rc-avermedia" - #define RC_MAP_AVERMEDIA_A16D "rc-avermedia-a16d" - #define RC_MAP_AVERMEDIA_CARDBUS "rc-avermedia-cardbus" - #define RC_MAP_AVERMEDIA_DVBT "rc-avermedia-dvbt" - #define RC_MAP_AVERMEDIA_M135A "rc-avermedia-m135a" - #define RC_MAP_AVERMEDIA_M733A_RM_K6 "rc-avermedia-m733a-rm-k6" - #define RC_MAP_AVERMEDIA_RM_KS "rc-avermedia-rm-ks" --#define RC_MAP_AVERMEDIA "rc-avermedia" - #define RC_MAP_AVERTV_303 "rc-avertv-303" - #define RC_MAP_AZUREWAVE_AD_TU700 "rc-azurewave-ad-tu700" --#define RC_MAP_BEHOLD_COLUMBUS "rc-behold-columbus" - #define RC_MAP_BEHOLD "rc-behold" -+#define RC_MAP_BEHOLD_COLUMBUS "rc-behold-columbus" - #define RC_MAP_BUDGET_CI_OLD "rc-budget-ci-old" - #define RC_MAP_CEC "rc-cec" --#define RC_MAP_CINERGY_1400 "rc-cinergy-1400" - #define RC_MAP_CINERGY "rc-cinergy" -+#define RC_MAP_CINERGY_1400 "rc-cinergy-1400" - #define RC_MAP_D680_DMB "rc-d680-dmb" - #define RC_MAP_DELOCK_61959 "rc-delock-61959" - #define RC_MAP_DIB0700_NEC_TABLE "rc-dib0700-nec" -@@ -181,17 +181,17 @@ struct rc_map *rc_map_get(const char *name); - #define RC_MAP_DIGITALNOW_TINYTWIN "rc-digitalnow-tinytwin" - #define RC_MAP_DIGITTRADE "rc-digittrade" - #define RC_MAP_DM1105_NEC "rc-dm1105-nec" --#define RC_MAP_DNTV_LIVE_DVBT_PRO "rc-dntv-live-dvbt-pro" - #define RC_MAP_DNTV_LIVE_DVB_T "rc-dntv-live-dvb-t" -+#define RC_MAP_DNTV_LIVE_DVBT_PRO "rc-dntv-live-dvbt-pro" - #define RC_MAP_DTT200U "rc-dtt200u" - #define RC_MAP_DVBSKY "rc-dvbsky" - #define RC_MAP_DVICO_MCE "rc-dvico-mce" - #define RC_MAP_DVICO_PORTABLE "rc-dvico-portable" - #define RC_MAP_EMPTY "rc-empty" - #define RC_MAP_EM_TERRATEC "rc-em-terratec" -+#define RC_MAP_ENCORE_ENLTV "rc-encore-enltv" - #define RC_MAP_ENCORE_ENLTV2 "rc-encore-enltv2" - #define RC_MAP_ENCORE_ENLTV_FM53 "rc-encore-enltv-fm53" --#define RC_MAP_ENCORE_ENLTV "rc-encore-enltv" - #define RC_MAP_EVGA_INDTUBE "rc-evga-indtube" - #define RC_MAP_EZTV "rc-eztv" - #define RC_MAP_FLYDVB "rc-flydvb" -@@ -201,6 +201,7 @@ struct rc_map *rc_map_get(const char *name); - #define RC_MAP_GEEKBOX "rc-geekbox" - #define RC_MAP_GENIUS_TVGO_A11MCE "rc-genius-tvgo-a11mce" - #define RC_MAP_GOTVIEW7135 "rc-gotview7135" -+#define RC_MAP_HAUPPAUGE "rc-hauppauge" - #define RC_MAP_HAUPPAUGE_NEW "rc-hauppauge" - #define RC_MAP_HISI_POPLAR "rc-hisi-poplar" - #define RC_MAP_HISI_TV_DEMO "rc-hisi-tv-demo" -@@ -223,8 +224,8 @@ struct rc_map *rc_map_get(const char *name); - #define RC_MAP_MEDION_X10_OR2X "rc-medion-x10-or2x" - #define RC_MAP_MSI_DIGIVOX_II "rc-msi-digivox-ii" - #define RC_MAP_MSI_DIGIVOX_III "rc-msi-digivox-iii" --#define RC_MAP_MSI_TVANYWHERE_PLUS "rc-msi-tvanywhere-plus" - #define RC_MAP_MSI_TVANYWHERE "rc-msi-tvanywhere" -+#define RC_MAP_MSI_TVANYWHERE_PLUS "rc-msi-tvanywhere-plus" - #define RC_MAP_NEBULA "rc-nebula" - #define RC_MAP_NEC_TERRATEC_CINERGY_XS "rc-nec-terratec-cinergy-xs" - #define RC_MAP_NORWOOD "rc-norwood" -@@ -234,21 +235,21 @@ struct rc_map *rc_map_get(const char *name); - #define RC_MAP_PINNACLE_COLOR "rc-pinnacle-color" - #define RC_MAP_PINNACLE_GREY "rc-pinnacle-grey" - #define RC_MAP_PINNACLE_PCTV_HD "rc-pinnacle-pctv-hd" --#define RC_MAP_PIXELVIEW_NEW "rc-pixelview-new" - #define RC_MAP_PIXELVIEW "rc-pixelview" --#define RC_MAP_PIXELVIEW_002T "rc-pixelview-002t" -+#define RC_MAP_PIXELVIEW_002T "rc-pixelview-002t" - #define RC_MAP_PIXELVIEW_MK12 "rc-pixelview-mk12" -+#define RC_MAP_PIXELVIEW_NEW "rc-pixelview-new" - #define RC_MAP_POWERCOLOR_REAL_ANGEL "rc-powercolor-real-angel" - #define RC_MAP_PROTEUS_2309 "rc-proteus-2309" - #define RC_MAP_PURPLETV "rc-purpletv" - #define RC_MAP_PV951 "rc-pv951" --#define RC_MAP_HAUPPAUGE "rc-hauppauge" - #define RC_MAP_RC5_TV "rc-rc5-tv" - #define RC_MAP_RC6_MCE "rc-rc6-mce" - #define RC_MAP_REAL_AUDIO_220_32_KEYS "rc-real-audio-220-32-keys" - #define RC_MAP_REDDO "rc-reddo" - #define RC_MAP_SNAPSTREAM_FIREFLY "rc-snapstream-firefly" - #define RC_MAP_STREAMZAP "rc-streamzap" -+#define RC_MAP_SU3000 "rc-su3000" - #define RC_MAP_TANGO "rc-tango" - #define RC_MAP_TANIX_TX3MINI "rc-tanix-tx3mini" - #define RC_MAP_TANIX_TX5MAX "rc-tanix-tx5max" -@@ -276,9 +277,8 @@ struct rc_map *rc_map_get(const char *name); - #define RC_MAP_WETEK_PLAY2 "rc-wetek-play2" - #define RC_MAP_WINFAST "rc-winfast" - #define RC_MAP_WINFAST_USBII_DELUXE "rc-winfast-usbii-deluxe" --#define RC_MAP_SU3000 "rc-su3000" --#define RC_MAP_XBOX_DVD "rc-xbox-dvd" - #define RC_MAP_X96MAX "rc-x96max" -+#define RC_MAP_XBOX_DVD "rc-xbox-dvd" - #define RC_MAP_ZX_IRDEC "rc-zx-irdec" - - /* --- -2.24.1 - -From 4f0fac3b1aa5f356e0625f7d767ec71e1c198a73 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Sun, 27 Oct 2019 21:07:37 +0100 -Subject: [PATCH] media: rc: add keymap for Beelink GS1 remote control -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Beelink GS1 Andoid TV Box ships with a simple NEC remote. - -Signed-off-by: Clément Péron -Signed-off-by: Sean Young -Signed-off-by: Mauro Carvalho Chehab ---- - .../devicetree/bindings/media/rc.yaml | 1 + - drivers/media/rc/keymaps/Makefile | 1 + - drivers/media/rc/keymaps/rc-beelink-gs1.c | 84 +++++++++++++++++++ - include/media/rc-map.h | 1 + - 4 files changed, 87 insertions(+) - create mode 100644 drivers/media/rc/keymaps/rc-beelink-gs1.c - -diff --git a/Documentation/devicetree/bindings/media/rc.yaml b/Documentation/devicetree/bindings/media/rc.yaml -index 3d5c154fd230..ceb283f7888a 100644 ---- a/Documentation/devicetree/bindings/media/rc.yaml -+++ b/Documentation/devicetree/bindings/media/rc.yaml -@@ -39,6 +39,7 @@ properties: - - rc-avermedia-rm-ks - - rc-avertv-303 - - rc-azurewave-ad-tu700 -+ - rc-beelink-gs1 - - rc-behold - - rc-behold-columbus - - rc-budget-ci-old -diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile -index 4ab4af062abf..63261ef6380a 100644 ---- a/drivers/media/rc/keymaps/Makefile -+++ b/drivers/media/rc/keymaps/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_RC_MAP) += rc-adstech-dvb-t-pci.o \ - rc-avermedia-rm-ks.o \ - rc-avertv-303.o \ - rc-azurewave-ad-tu700.o \ -+ rc-beelink-gs1.o \ - rc-behold.o \ - rc-behold-columbus.o \ - rc-budget-ci-old.o \ -diff --git a/drivers/media/rc/keymaps/rc-beelink-gs1.c b/drivers/media/rc/keymaps/rc-beelink-gs1.c -new file mode 100644 -index 000000000000..cedbd5d20bc7 ---- /dev/null -+++ b/drivers/media/rc/keymaps/rc-beelink-gs1.c -@@ -0,0 +1,84 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+// Copyright (c) 2019 Clément Péron -+ -+#include -+#include -+ -+/* -+ * Keymap for the Beelink GS1 remote control -+ */ -+ -+static struct rc_map_table beelink_gs1_table[] = { -+ /* -+ * TV Keys (Power, Learn and Volume) -+ * { 0x40400d, KEY_TV }, -+ * { 0x80f1, KEY_TV }, -+ * { 0x80f3, KEY_TV }, -+ * { 0x80f4, KEY_TV }, -+ */ -+ -+ { 0x8051, KEY_POWER }, -+ { 0x804d, KEY_MUTE }, -+ { 0x8040, KEY_CONFIG }, -+ -+ { 0x8026, KEY_UP }, -+ { 0x8028, KEY_DOWN }, -+ { 0x8025, KEY_LEFT }, -+ { 0x8027, KEY_RIGHT }, -+ { 0x800d, KEY_OK }, -+ -+ { 0x8053, KEY_HOME }, -+ { 0x80bc, KEY_MEDIA }, -+ { 0x801b, KEY_BACK }, -+ { 0x8049, KEY_MENU }, -+ -+ { 0x804e, KEY_VOLUMEUP }, -+ { 0x8056, KEY_VOLUMEDOWN }, -+ -+ { 0x8054, KEY_SUBTITLE }, /* Web */ -+ { 0x8052, KEY_EPG }, /* Media */ -+ -+ { 0x8041, KEY_CHANNELUP }, -+ { 0x8042, KEY_CHANNELDOWN }, -+ -+ { 0x8031, KEY_1 }, -+ { 0x8032, KEY_2 }, -+ { 0x8033, KEY_3 }, -+ -+ { 0x8034, KEY_4 }, -+ { 0x8035, KEY_5 }, -+ { 0x8036, KEY_6 }, -+ -+ { 0x8037, KEY_7 }, -+ { 0x8038, KEY_8 }, -+ { 0x8039, KEY_9 }, -+ -+ { 0x8044, KEY_DELETE }, -+ { 0x8030, KEY_0 }, -+ { 0x8058, KEY_MODE }, /* # Input Method */ -+}; -+ -+static struct rc_map_list beelink_gs1_map = { -+ .map = { -+ .scan = beelink_gs1_table, -+ .size = ARRAY_SIZE(beelink_gs1_table), -+ .rc_proto = RC_PROTO_NEC, -+ .name = RC_MAP_BEELINK_GS1, -+ } -+}; -+ -+static int __init init_rc_map_beelink_gs1(void) -+{ -+ return rc_map_register(&beelink_gs1_map); -+} -+ -+static void __exit exit_rc_map_beelink_gs1(void) -+{ -+ rc_map_unregister(&beelink_gs1_map); -+} -+ -+module_init(init_rc_map_beelink_gs1) -+module_exit(exit_rc_map_beelink_gs1) -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Clément Péron "); -diff --git a/include/media/rc-map.h b/include/media/rc-map.h -index 0a8669daeaaa..f99575a0d29c 100644 ---- a/include/media/rc-map.h -+++ b/include/media/rc-map.h -@@ -168,6 +168,7 @@ struct rc_map *rc_map_get(const char *name); - #define RC_MAP_AVERMEDIA_RM_KS "rc-avermedia-rm-ks" - #define RC_MAP_AVERTV_303 "rc-avertv-303" - #define RC_MAP_AZUREWAVE_AD_TU700 "rc-azurewave-ad-tu700" -+#define RC_MAP_BEELINK_GS1 "rc-beelink-gs1" - #define RC_MAP_BEHOLD "rc-behold" - #define RC_MAP_BEHOLD_COLUMBUS "rc-behold-columbus" - #define RC_MAP_BUDGET_CI_OLD "rc-budget-ci-old" --- -2.24.1 - diff --git a/projects/Allwinner/patches/linux/0002-backport-from-5.6.patch b/projects/Allwinner/patches/linux/0001-backport-from-5.6.patch similarity index 89% rename from projects/Allwinner/patches/linux/0002-backport-from-5.6.patch rename to projects/Allwinner/patches/linux/0001-backport-from-5.6.patch index 073c8424b3..ab00aed2c8 100644 --- a/projects/Allwinner/patches/linux/0002-backport-from-5.6.patch +++ b/projects/Allwinner/patches/linux/0001-backport-from-5.6.patch @@ -1164,213 +1164,6 @@ index 0afea59486c2..6e68ed831015 100644 -- 2.24.1 -From 7fdf6c6a0d0e032aac2aa4537a23af1e04a397ce Mon Sep 17 00:00:00 2001 -From: Marcel Holtmann -Date: Fri, 22 Nov 2019 00:33:45 +0100 -Subject: [PATCH] Bluetooth: Allow combination of BDADDR_PROPERTY and - INVALID_BDADDR quirks - -When utilizing BDADDR_PROPERTY and INVALID_BDADDR quirks together it -results in an unconfigured controller even if the bootloader provides -a valid address. Fix this by allowing a bootloader provided address -to mark the controller as configured. - -Signed-off-by: Marcel Holtmann -Tested-by: Andre Heider -Signed-off-by: Johan Hedberg ---- - net/bluetooth/hci_core.c | 26 ++++++++++++++++++++++++-- - 1 file changed, 24 insertions(+), 2 deletions(-) - -diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c -index 0cc9ce917222..9e19d5a3aac8 100644 ---- a/net/bluetooth/hci_core.c -+++ b/net/bluetooth/hci_core.c -@@ -1444,11 +1444,20 @@ static int hci_dev_do_open(struct hci_dev *hdev) - - if (hci_dev_test_flag(hdev, HCI_SETUP) || - test_bit(HCI_QUIRK_NON_PERSISTENT_SETUP, &hdev->quirks)) { -+ bool invalid_bdaddr; -+ - hci_sock_dev_event(hdev, HCI_DEV_SETUP); - - if (hdev->setup) - ret = hdev->setup(hdev); - -+ /* The transport driver can set the quirk to mark the -+ * BD_ADDR invalid before creating the HCI device or in -+ * its setup callback. -+ */ -+ invalid_bdaddr = test_bit(HCI_QUIRK_INVALID_BDADDR, -+ &hdev->quirks); -+ - if (ret) - goto setup_failed; - -@@ -1457,20 +1466,33 @@ static int hci_dev_do_open(struct hci_dev *hdev) - hci_dev_get_bd_addr_from_property(hdev); - - if (bacmp(&hdev->public_addr, BDADDR_ANY) && -- hdev->set_bdaddr) -+ hdev->set_bdaddr) { - ret = hdev->set_bdaddr(hdev, - &hdev->public_addr); -+ -+ /* If setting of the BD_ADDR from the device -+ * property succeeds, then treat the address -+ * as valid even if the invalid BD_ADDR -+ * quirk indicates otherwise. -+ */ -+ if (!ret) -+ invalid_bdaddr = false; -+ } - } - - setup_failed: - /* The transport driver can set these quirks before - * creating the HCI device or in its setup callback. - * -+ * For the invalid BD_ADDR quirk it is possible that -+ * it becomes a valid address if the bootloader does -+ * provide it (see above). -+ * - * In case any of them is set, the controller has to - * start up as unconfigured. - */ - if (test_bit(HCI_QUIRK_EXTERNAL_CONFIG, &hdev->quirks) || -- test_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks)) -+ invalid_bdaddr) - hci_dev_set_flag(hdev, HCI_UNCONFIGURED); - - /* For an unconfigured controller it is required to --- -2.24.1 - -From a4f95f31a9f38d9bb1fd313fcc2d0c0d48116ee3 Mon Sep 17 00:00:00 2001 -From: Andre Heider -Date: Fri, 22 Nov 2019 13:31:42 +0100 -Subject: [PATCH] Bluetooth: btbcm: Use the BDADDR_PROPERTY quirk - -Some devices ship with the controller default address, like the -Orange Pi 3 (BCM4345C5). - -Allow the bootloader to set a valid address through the device tree. - -Signed-off-by: Andre Heider -Signed-off-by: Marcel Holtmann ---- - drivers/bluetooth/btbcm.c | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/drivers/bluetooth/btbcm.c b/drivers/bluetooth/btbcm.c -index 689c7f36fea2..8e05706fe5d9 100644 ---- a/drivers/bluetooth/btbcm.c -+++ b/drivers/bluetooth/btbcm.c -@@ -444,6 +444,12 @@ int btbcm_finalize(struct hci_dev *hdev) - - set_bit(HCI_QUIRK_STRICT_DUPLICATE_FILTER, &hdev->quirks); - -+ /* Some devices ship with the controller default address. -+ * Allow the bootloader to set a valid address through the -+ * device tree. -+ */ -+ set_bit(HCI_QUIRK_USE_BDADDR_PROPERTY, &hdev->quirks); -+ - return 0; - } - EXPORT_SYMBOL_GPL(btbcm_finalize); --- -2.24.1 - -From 675a6d467b432c8b4a0703ded02e6ef068e0c7e9 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sat, 28 Dec 2019 20:59:21 -0600 -Subject: [PATCH] clk: sunxi-ng: h6-r: Simplify R_APB1 clock definition - -Like the APB0 clock on previous chips, this is a simple single-parent -clock with an M divider. Use the equivalent helper macro instead of -writing out the whole clock description manually. - -Signed-off-by: Samuel Holland -Signed-off-by: Maxime Ripard ---- - drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 12 +----------- - 1 file changed, 1 insertion(+), 11 deletions(-) - -diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c -index 45a1ed3fe674..df9c01831699 100644 ---- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c -+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c -@@ -51,17 +51,7 @@ static struct ccu_div ar100_clk = { - - static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0); - --static struct ccu_div r_apb1_clk = { -- .div = _SUNXI_CCU_DIV(0, 2), -- -- .common = { -- .reg = 0x00c, -- .hw.init = CLK_HW_INIT("r-apb1", -- "r-ahb", -- &ccu_div_ops, -- 0), -- }, --}; -+static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0); - - static struct ccu_div r_apb2_clk = { - .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), --- -2.24.1 - -From 0c545240aebc2ccb8f661dc54283a14d64659804 Mon Sep 17 00:00:00 2001 -From: Samuel Holland -Date: Sat, 28 Dec 2019 20:59:22 -0600 -Subject: [PATCH] clk: sunxi-ng: h6-r: Fix AR100/R_APB2 parent order - -According to the BSP source code, both the AR100 and R_APB2 clocks have -PLL_PERIPH0 as mux index 3, not 2 as it was on previous chips. The pre- -divider used for PLL_PERIPH0 should be changed to index 3 to match. - -This was verified by running a rough benchmark on the AR100 with various -clock settings: - - | mux | pre-divider | iterations/second | clock source | - |=====|=============|===================|==============| - | 0 | 0 | 19033 (stable) | osc24M | - | 2 | 5 | 11466 (unstable) | iosc/osc16M | - | 2 | 17 | 11422 (unstable) | iosc/osc16M | - | 3 | 5 | 85338 (stable) | pll-periph0 | - | 3 | 17 | 27167 (stable) | pll-periph0 | - -The relative performance numbers all match up (with pll-periph0 running -at its default 600MHz). - -Signed-off-by: Samuel Holland -Signed-off-by: Maxime Ripard ---- - drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c -index df9c01831699..50f8d1bc7046 100644 ---- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c -+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c -@@ -23,9 +23,9 @@ - */ - - static const char * const ar100_r_apb2_parents[] = { "osc24M", "osc32k", -- "pll-periph0", "iosc" }; -+ "iosc", "pll-periph0" }; - static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = { -- { .index = 2, .shift = 0, .width = 5 }, -+ { .index = 3, .shift = 0, .width = 5 }, - }; - - static struct ccu_div ar100_clk = { --- -2.24.1 - From ec97faff743b398e21f74a54c81333f3390093aa Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 3 Jan 2020 22:35:03 -0800 diff --git a/projects/Allwinner/patches/linux/0003-hdmi-improvements.patch b/projects/Allwinner/patches/linux/0003-hdmi-improvements.patch index 6baa1ba625..59af29dd52 100644 --- a/projects/Allwinner/patches/linux/0003-hdmi-improvements.patch +++ b/projects/Allwinner/patches/linux/0003-hdmi-improvements.patch @@ -1,482 +1,3 @@ -From 99b0611417b9864ae57b6646e143f748f80964c9 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 16 Dec 2018 10:22:09 +0100 -Subject: [PATCH 01/15] drm: dw-hdmi: extract dw_hdmi_connector_update_edid() - -Extract code that updates EDID into a dw_hdmi_connector_update_edid() helper, -it will be called from dw_hdmi_connector_detect(). - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 11 +++++++++-- - 1 file changed, 9 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index ab7968c..fb35ee9 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -2059,7 +2059,8 @@ dw_hdmi_connector_detect(struct drm_connector *connector, bool force) - return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); - } - --static int dw_hdmi_connector_get_modes(struct drm_connector *connector) -+static int dw_hdmi_connector_update_edid(struct drm_connector *connector, -+ bool add_modes) - { - struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, - connector); -@@ -2078,7 +2079,8 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) - hdmi->sink_has_audio = drm_detect_monitor_audio(edid); - drm_connector_update_edid_property(connector, edid); - cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); -- ret = drm_add_edid_modes(connector, edid); -+ if (add_modes) -+ ret = drm_add_edid_modes(connector, edid); - kfree(edid); - } else { - dev_dbg(hdmi->dev, "failed to get edid\n"); -@@ -2087,6 +2089,11 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) - return ret; - } - -+static int dw_hdmi_connector_get_modes(struct drm_connector *connector) -+{ -+ return dw_hdmi_connector_update_edid(connector, true); -+} -+ - static void dw_hdmi_connector_force(struct drm_connector *connector) - { - struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, --- -2.14.1 - - -From 834da8a94754f25fdfac1995cc7ea72e569e9fbd Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 16 Dec 2018 11:38:43 +0100 -Subject: [PATCH 02/15] drm: dw-hdmi: move dw_hdmi_connector_detect() - -Move dw_hdmi_connector_detect() it will call dw_hdmi_connector_update_edid(). - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 30 +++++++++++++++--------------- - 1 file changed, 15 insertions(+), 15 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index fb35ee9..eb9e5d8 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -2044,21 +2044,6 @@ static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) - hdmi->rxsense); - } - --static enum drm_connector_status --dw_hdmi_connector_detect(struct drm_connector *connector, bool force) --{ -- struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, -- connector); -- -- mutex_lock(&hdmi->mutex); -- hdmi->force = DRM_FORCE_UNSPECIFIED; -- dw_hdmi_update_power(hdmi); -- dw_hdmi_update_phy_mask(hdmi); -- mutex_unlock(&hdmi->mutex); -- -- return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); --} -- - static int dw_hdmi_connector_update_edid(struct drm_connector *connector, - bool add_modes) - { -@@ -2089,6 +2074,21 @@ static int dw_hdmi_connector_update_edid(struct drm_connector *connector, - return ret; - } - -+static enum drm_connector_status -+dw_hdmi_connector_detect(struct drm_connector *connector, bool force) -+{ -+ struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, -+ connector); -+ -+ mutex_lock(&hdmi->mutex); -+ hdmi->force = DRM_FORCE_UNSPECIFIED; -+ dw_hdmi_update_power(hdmi); -+ dw_hdmi_update_phy_mask(hdmi); -+ mutex_unlock(&hdmi->mutex); -+ -+ return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); -+} -+ - static int dw_hdmi_connector_get_modes(struct drm_connector *connector) - { - return dw_hdmi_connector_update_edid(connector, true); --- -2.14.1 - - -From f1d41eb5ac2193f2a6c4a746a9fac27c3bfe7af5 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 16 Dec 2018 10:22:09 +0100 -Subject: [PATCH 03/15] drm: dw-hdmi: update CEC phys addr and EDID on HPD - event - -Update CEC phys addr and EDID on HPD event, fixes lost CEC phys addr and -stale EDID when HDMI cable is unplugged/replugged or AVR is powered on/off. - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 +++++++++----- - 1 file changed, 9 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index eb9e5d8..d079bde 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -2077,6 +2077,7 @@ static int dw_hdmi_connector_update_edid(struct drm_connector *connector, - static enum drm_connector_status - dw_hdmi_connector_detect(struct drm_connector *connector, bool force) - { -+ enum drm_connector_status status; - struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, - connector); - -@@ -2086,7 +2087,14 @@ dw_hdmi_connector_detect(struct drm_connector *connector, bool force) - dw_hdmi_update_phy_mask(hdmi); - mutex_unlock(&hdmi->mutex); - -- return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); -+ status = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); -+ -+ if (status == connector_status_connected) -+ dw_hdmi_connector_update_edid(connector, false); -+ else -+ cec_notifier_set_phys_addr(hdmi->cec_notifier, CEC_PHYS_ADDR_INVALID); -+ -+ return status; - } - - static int dw_hdmi_connector_get_modes(struct drm_connector *connector) -@@ -2301,12 +2309,6 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) - dw_hdmi_setup_rx_sense(hdmi, - phy_stat & HDMI_PHY_HPD, - phy_stat & HDMI_PHY_RX_SENSE); -- -- if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { -- mutex_lock(&hdmi->cec_notifier_mutex); -- cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); -- mutex_unlock(&hdmi->cec_notifier_mutex); -- } - } - - if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { --- -2.14.1 - - -From e20d93cd15aad779acfad254bac23d37ea7b7fe9 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 16 Dec 2018 10:22:09 +0100 -Subject: [PATCH 04/15] Revert "drm/edid: make drm_edid_to_eld() static" - -drm_edid_to_eld() is needed to update stale connector ELD on HPD event. - -This reverts part of commit 79436a1c9bccf5e38cb6ea26e4e4b9283baf2e20. - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/drm_edid.c | 5 +++-- - include/drm/drm_edid.h | 1 + - 2 files changed, 4 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c -index d947789..cc71a3c 100644 ---- a/drivers/gpu/drm/drm_edid.c -+++ b/drivers/gpu/drm/drm_edid.c -@@ -3970,7 +3970,7 @@ static void clear_eld(struct drm_connector *connector) - connector->audio_latency[1] = 0; - } - --/* -+/** - * drm_edid_to_eld - build ELD from EDID - * @connector: connector corresponding to the HDMI/DP sink - * @edid: EDID to parse -@@ -3978,7 +3978,7 @@ static void clear_eld(struct drm_connector *connector) - * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The - * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. - */ --static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) -+void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) - { - uint8_t *eld = connector->eld; - u8 *cea; -@@ -4063,6 +4063,7 @@ static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) - DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", - drm_eld_size(eld), total_sad_count); - } -+EXPORT_SYMBOL(drm_edid_to_eld); - - /** - * drm_edid_to_sad - extracts SADs from EDID -diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h -index 19b15fd..185870b 100644 ---- a/include/drm/drm_edid.h -+++ b/include/drm/drm_edid.h -@@ -333,6 +333,7 @@ struct drm_encoder; - struct drm_connector; - struct drm_display_mode; - -+void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid); - int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads); - int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb); - int drm_av_sync_delay(struct drm_connector *connector, --- -2.14.1 - - -From 901b76d639e09e7d829b4974c174ab8595310bcd Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 16 Dec 2018 10:22:09 +0100 -Subject: [PATCH 05/15] drm: dw-hdmi: update ELD on HPD event - -Update connector ELD on HPD event, fixes stale ELD when -HDMI cable is unplugged/replugged or AVR is powered on/off. - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index d079bde..f13ac2c 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -2066,6 +2066,8 @@ static int dw_hdmi_connector_update_edid(struct drm_connector *connector, - cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); - if (add_modes) - ret = drm_add_edid_modes(connector, edid); -+ else -+ drm_edid_to_eld(connector, edid); - kfree(edid); - } else { - dev_dbg(hdmi->dev, "failed to get edid\n"); --- -2.14.1 - - -From e77725c0dc43a3d8d8641dea4abfb92225bf6e72 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 16 Dec 2018 10:22:09 +0100 -Subject: [PATCH 06/15] ASoC: hdmi-codec: add hdmi_codec_eld_notify() - -Add helper that will notify userspace when ELD control has changed. - -Signed-off-by: Jonas Karlman ---- - include/sound/hdmi-codec.h | 2 ++ - sound/soc/codecs/hdmi-codec.c | 24 ++++++++++++++++++++---- - 2 files changed, 22 insertions(+), 4 deletions(-) - -diff --git a/include/sound/hdmi-codec.h b/include/sound/hdmi-codec.h -index 9483c55..7cf66a4 100644 ---- a/include/sound/hdmi-codec.h -+++ b/include/sound/hdmi-codec.h -@@ -107,6 +107,8 @@ struct hdmi_codec_pdata { - void *data; - }; - -+void hdmi_codec_eld_notify(struct device *dev); -+ - #define HDMI_CODEC_DRV_NAME "hdmi-audio-codec" - - #endif /* __HDMI_CODEC_H__ */ -diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c -index fb2f0ac..bfb1519 100644 ---- a/sound/soc/codecs/hdmi-codec.c -+++ b/sound/soc/codecs/hdmi-codec.c -@@ -285,6 +285,8 @@ struct hdmi_codec_priv { - struct mutex lock; - struct snd_soc_jack *jack; - unsigned int jack_status; -+ struct snd_card *snd_card; -+ struct snd_kcontrol *kctl; - }; - - static const struct snd_soc_dapm_widget hdmi_widgets[] = { -@@ -648,7 +650,6 @@ static int hdmi_codec_pcm_new(struct snd_soc_pcm_runtime *rtd, - { - struct snd_soc_dai_driver *drv = dai->driver; - struct hdmi_codec_priv *hcp = snd_soc_dai_get_drvdata(dai); -- struct snd_kcontrol *kctl; - struct snd_kcontrol_new hdmi_eld_ctl = { - .access = SNDRV_CTL_ELEM_ACCESS_READ | - SNDRV_CTL_ELEM_ACCESS_VOLATILE, -@@ -677,12 +678,27 @@ static int hdmi_codec_pcm_new(struct snd_soc_pcm_runtime *rtd, - hcp->chmap_idx = HDMI_CODEC_CHMAP_IDX_UNKNOWN; - - /* add ELD ctl with the device number corresponding to the PCM stream */ -- kctl = snd_ctl_new1(&hdmi_eld_ctl, dai->component); -- if (!kctl) -+ hcp->kctl = snd_ctl_new1(&hdmi_eld_ctl, dai->component); -+ if (!hcp->kctl) - return -ENOMEM; - -- return snd_ctl_add(rtd->card->snd_card, kctl); -+ hcp->snd_card = rtd->card->snd_card; -+ -+ return snd_ctl_add(hcp->snd_card, hcp->kctl); -+} -+ -+void hdmi_codec_eld_notify(struct device *dev) -+{ -+ struct hdmi_codec_priv *hcp = dev_get_drvdata(dev); -+ struct snd_ctl_elem_id id; -+ -+ if (!hcp->snd_card || !hcp->kctl) -+ return; -+ -+ id = hcp->kctl->id; -+ snd_ctl_notify(hcp->snd_card, SNDRV_CTL_EVENT_MASK_VALUE, &id); - } -+EXPORT_SYMBOL_GPL(hdmi_codec_eld_notify); - - static int hdmi_dai_probe(struct snd_soc_dai *dai) - { --- -2.14.1 - - -From 2f1f2bdbc0f6d02235310e87c1de7a193dcda178 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 16 Dec 2018 12:56:33 +0100 -Subject: [PATCH 07/15] drm: dw-hdmi: add dw_hdmi_update_eld() callback - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 15 +++++++++++++++ - include/drm/bridge/dw_hdmi.h | 2 ++ - 2 files changed, 17 insertions(+) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index f13ac2c..a7040c1 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -188,6 +188,7 @@ struct dw_hdmi { - struct regmap *regm; - void (*enable_audio)(struct dw_hdmi *hdmi); - void (*disable_audio)(struct dw_hdmi *hdmi); -+ void (*update_eld)(struct device *dev, u8 *eld); - - struct cec_notifier *cec_notifier; - }; -@@ -613,6 +614,19 @@ void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) - } - EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); - -+static void dw_hdmi_update_eld(struct dw_hdmi *hdmi, u8 *eld) -+{ -+ if (hdmi->audio && hdmi->update_eld) -+ hdmi->update_eld(&hdmi->audio->dev, eld); -+} -+ -+void dw_hdmi_set_update_eld(struct dw_hdmi *hdmi, -+ void (*update_eld)(struct device *dev, u8 *eld)) -+{ -+ hdmi->update_eld = update_eld; -+} -+EXPORT_SYMBOL_GPL(dw_hdmi_set_update_eld); -+ - static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) - { - switch (bus_format) { -@@ -2068,6 +2082,7 @@ static int dw_hdmi_connector_update_edid(struct drm_connector *connector, - ret = drm_add_edid_modes(connector, edid); - else - drm_edid_to_eld(connector, edid); -+ dw_hdmi_update_eld(hdmi, connector->eld); - kfree(edid); - } else { - dev_dbg(hdmi->dev, "failed to get edid\n"); -diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h -index 66e7077..323febe 100644 ---- a/include/drm/bridge/dw_hdmi.h -+++ b/include/drm/bridge/dw_hdmi.h -@@ -160,6 +160,8 @@ void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); - void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); - void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); - void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi); -+void dw_hdmi_set_update_eld(struct dw_hdmi *hdmi, -+ void (*update_eld)(struct device *dev, u8 *eld)); - - /* PHY configuration */ - void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address); --- -2.14.1 - - -From 8a20ea0cfb4c6e97d2ccde1fc77e1f4cdd03e5d2 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 16 Dec 2018 10:22:09 +0100 -Subject: [PATCH 08/15] drm: dw-hdmi-i2s: add .get_eld callback for ALSA SoC - -Add get_eld() callback and call hdmi_codec_eld_notify() when ELD has changed. - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h | 1 + - .../gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 36 +++++++++++++++++++++- - 2 files changed, 36 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -index 5cbb71a..a397505 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -@@ -84,6 +84,22 @@ static void dw_hdmi_i2s_audio_shutdown(struct device *dev, void *data) - dw_hdmi_audio_disable(hdmi); - } - -+static void dw_hdmi_i2s_update_eld(struct device *dev, u8 *eld) -+{ -+ struct dw_hdmi_i2s_audio_data *audio = dev_get_platdata(dev); -+ struct platform_device *hcpdev = dev_get_drvdata(dev); -+ -+ if (!audio || !hcpdev) -+ return; -+ -+ if (!memcmp(audio->eld, eld, sizeof(audio->eld))) -+ return; -+ -+ memcpy(audio->eld, eld, sizeof(audio->eld)); -+ -+ hdmi_codec_eld_notify(&hcpdev->dev); -+} -+ - static int dw_hdmi_i2s_get_eld(struct device *dev, void *data, uint8_t *buf, - size_t len) - { -@@ -136,13 +165,18 @@ static int snd_dw_hdmi_probe(struct platform_device *pdev) - - dev_set_drvdata(&pdev->dev, platform); - -+ dw_hdmi_set_update_eld(audio->hdmi, dw_hdmi_i2s_update_eld); -+ - return 0; - } - - static int snd_dw_hdmi_remove(struct platform_device *pdev) - { -+ struct dw_hdmi_i2s_audio_data *audio = dev_get_platdata(&pdev->dev); - struct platform_device *platform = dev_get_drvdata(&pdev->dev); - -+ dw_hdmi_set_update_eld(audio->hdmi, NULL); -+ - platform_device_unregister(platform); - - return 0; --- -2.14.1 - From e7b2f400507263f12872db06f4cd69bc80f62c2f Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 25 Mar 2018 22:17:06 +0200 @@ -624,29 +145,437 @@ index bfb1519..47632a3 100644 -- 2.14.1 -From 774d913eec1ba16c494dafefc626fa4fbd98fdac Mon Sep 17 00:00:00 2001 +From 759c992d38d1a02560687247dec7ac05f4e8b3ce Mon Sep 17 00:00:00 2001 From: Jonas Karlman -Date: Sun, 16 Dec 2018 20:31:25 +0100 -Subject: [PATCH 15/15] fixup! drm: dw-hdmi: add dw_hdmi_update_eld() callback +Date: Sun, 8 Dec 2019 13:13:46 +0000 +Subject: [PATCH] drm: dw-hdmi: rename last_connector_result +Signed-off-by: Jonas Karlman --- - sound/soc/codecs/hdmi-codec.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 20 ++++++++++---------- + 1 file changed, 10 insertions(+), 10 deletions(-) -diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c -index 47632a3..f5072dc 100644 ---- a/sound/soc/codecs/hdmi-codec.c -+++ b/sound/soc/codecs/hdmi-codec.c -@@ -683,7 +683,9 @@ void hdmi_codec_eld_notify(struct device *dev) - struct hdmi_codec_priv *hcp = dev_get_drvdata(dev); - struct snd_ctl_elem_id id; +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 0e716c40c42c..2dad989e7b4f 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -197,7 +197,7 @@ struct dw_hdmi { -- if (!hcp->snd_card || !hcp->kctl) -+ if (!hcp || -+ !hcp->snd_card || -+ !hcp->kctl) - return; + hdmi_codec_plugged_cb plugged_cb; + struct device *codec_dev; +- enum drm_connector_status last_connector_result; ++ enum drm_connector_status last_connector_status; + }; - id = hcp->kctl->id; --- -2.14.1 + #define HDMI_IH_PHY_STAT0_RX_SENSE \ +@@ -236,7 +236,7 @@ int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn, + mutex_lock(&hdmi->mutex); + hdmi->plugged_cb = fn; + hdmi->codec_dev = codec_dev; +- plugged = hdmi->last_connector_result == connector_status_connected; ++ plugged = hdmi->last_connector_status == connector_status_connected; + handle_plugged_change(hdmi, plugged); + mutex_unlock(&hdmi->mutex); + +@@ -2271,7 +2271,7 @@ dw_hdmi_connector_detect(struct drm_connector *connector, bool force) + { + struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, + connector); +- enum drm_connector_status result; ++ enum drm_connector_status status; + + mutex_lock(&hdmi->mutex); + hdmi->force = DRM_FORCE_UNSPECIFIED; +@@ -2279,18 +2279,18 @@ dw_hdmi_connector_detect(struct drm_connector *connector, bool force) + dw_hdmi_update_phy_mask(hdmi); + mutex_unlock(&hdmi->mutex); + +- result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); ++ status = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); + + mutex_lock(&hdmi->mutex); +- if (result != hdmi->last_connector_result) { +- dev_dbg(hdmi->dev, "read_hpd result: %d", result); ++ if (status != hdmi->last_connector_status) { ++ dev_dbg(hdmi->dev, "connector status: %d", status); + handle_plugged_change(hdmi, +- result == connector_status_connected); +- hdmi->last_connector_result = result; ++ status == connector_status_connected); ++ hdmi->last_connector_status = status; + } + mutex_unlock(&hdmi->mutex); + +- return result; ++ return status; + } + + static int dw_hdmi_connector_get_modes(struct drm_connector *connector) +@@ -3053,7 +3053,7 @@ __dw_hdmi_probe(struct platform_device *pdev, + hdmi->rxsense = true; + hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); + hdmi->mc_clkdis = 0x7f; +- hdmi->last_connector_result = connector_status_disconnected; ++ hdmi->last_connector_status = connector_status_disconnected; + + mutex_init(&hdmi->mutex); + mutex_init(&hdmi->audio_mutex); + +From 753bd0f066fd26f253f45ca652bb8a532c6dad90 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 1 Dec 2019 20:51:22 +0000 +Subject: [PATCH] drm: dw-hdmi: extract handle_plugged_change call + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 22 ++++++++++++++-------- + 1 file changed, 14 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 2dad989e7b4f..ac198fcaba8b 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -228,6 +228,19 @@ static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged) + hdmi->plugged_cb(hdmi->codec_dev, plugged); + } + ++static void dw_hdmi_update_connector_status(struct dw_hdmi *hdmi, ++ enum drm_connector_status status) ++{ ++ mutex_lock(&hdmi->mutex); ++ if (status != hdmi->last_connector_status) { ++ dev_dbg(hdmi->dev, "connector status: %d", status); ++ handle_plugged_change(hdmi, ++ status == connector_status_connected); ++ hdmi->last_connector_status = status; ++ } ++ mutex_unlock(&hdmi->mutex); ++} ++ + int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn, + struct device *codec_dev) + { +@@ -2281,14 +2294,7 @@ dw_hdmi_connector_detect(struct drm_connector *connector, bool force) + + status = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); + +- mutex_lock(&hdmi->mutex); +- if (status != hdmi->last_connector_status) { +- dev_dbg(hdmi->dev, "connector status: %d", status); +- handle_plugged_change(hdmi, +- status == connector_status_connected); +- hdmi->last_connector_status = status; +- } +- mutex_unlock(&hdmi->mutex); ++ dw_hdmi_update_connector_status(hdmi, status); + + return status; + } + +From fdd68a4db03fba2017a4aa65830adf3b8d5a585c Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 28 Sep 2019 13:34:46 +0000 +Subject: [PATCH] drm: dw-hdmi: remove unused struct member + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index ac198fcaba8b..7a0eb443cec6 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -41,8 +41,6 @@ + #define DDC_CI_ADDR 0x37 + #define DDC_SEGMENT_ADDR 0x30 + +-#define HDMI_EDID_LEN 512 +- + /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ + #define SCDC_MIN_SOURCE_VERSION 0x1 + +@@ -152,8 +150,6 @@ struct dw_hdmi { + + int vic; + +- u8 edid[HDMI_EDID_LEN]; +- + struct { + const struct dw_hdmi_phy_ops *ops; + const char *name; + +From 1b52bf5366035687e7e028f1320c9e2d37dd01a3 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 28 Sep 2019 13:34:46 +0000 +Subject: [PATCH] drm: dw-hdmi: read edid in detect callback + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 79 +++++++++++++++++++++++-------- + 1 file changed, 58 insertions(+), 21 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 7a0eb443cec6..363f7c5a8016 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -150,6 +150,8 @@ struct dw_hdmi { + + int vic; + ++ struct edid *cached_edid; ++ + struct { + const struct dw_hdmi_phy_ops *ops; + const char *name; +@@ -2217,9 +2219,55 @@ static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) + hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); + } + ++static void dw_hdmi_clear_edid(struct drm_connector *connector) ++{ ++ struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, ++ connector); ++ ++ if (!hdmi->cached_edid) ++ return; ++ ++ hdmi->sink_is_hdmi = false; ++ hdmi->sink_has_audio = false; ++ ++ kfree(hdmi->cached_edid); ++ hdmi->cached_edid = NULL; ++} ++ ++static void dw_hdmi_get_edid(struct drm_connector *connector) ++{ ++ struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, ++ connector); ++ struct edid *edid; ++ ++ if (!hdmi->ddc || hdmi->cached_edid) ++ return; ++ ++ edid = drm_get_edid(connector, hdmi->ddc); ++ ++ if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { ++ dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", ++ edid->width_cm, edid->height_cm); ++ ++ hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); ++ hdmi->sink_has_audio = drm_detect_monitor_audio(edid); ++ ++ hdmi->cached_edid = edid; ++ } else { ++ dev_dbg(hdmi->dev, "failed to get edid\n"); ++ ++ kfree(edid); ++ edid = NULL; ++ } ++ ++ drm_connector_update_edid_property(connector, edid); ++ cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); ++} ++ + static void dw_hdmi_poweron(struct dw_hdmi *hdmi) + { + hdmi->bridge_is_on = true; ++ dw_hdmi_get_edid(&hdmi->connector); + dw_hdmi_setup(hdmi, &hdmi->previous_mode); + } + +@@ -2290,6 +2338,11 @@ dw_hdmi_connector_detect(struct drm_connector *connector, bool force) + + status = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); + ++ if (status == connector_status_disconnected) ++ dw_hdmi_clear_edid(connector); ++ else ++ dw_hdmi_get_edid(connector); ++ + dw_hdmi_update_connector_status(hdmi, status); + + return status; +@@ -2299,28 +2352,8 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) + { + struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, + connector); +- struct edid *edid; +- int ret = 0; +- +- if (!hdmi->ddc) +- return 0; + +- edid = drm_get_edid(connector, hdmi->ddc); +- if (edid) { +- dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", +- edid->width_cm, edid->height_cm); +- +- hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); +- hdmi->sink_has_audio = drm_detect_monitor_audio(edid); +- drm_connector_update_edid_property(connector, edid); +- cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); +- ret = drm_add_edid_modes(connector, edid); +- kfree(edid); +- } else { +- dev_dbg(hdmi->dev, "failed to get edid\n"); +- } +- +- return ret; ++ return drm_add_edid_modes(connector, hdmi->cached_edid); + } + + static bool hdr_metadata_equal(const struct drm_connector_state *old_state, +@@ -2699,6 +2732,9 @@ static void dw_hdmi_bridge_detach(struct drm_bridge *bridge) + cec_notifier_conn_unregister(hdmi->cec_notifier); + hdmi->cec_notifier = NULL; + mutex_unlock(&hdmi->cec_notifier_mutex); ++ ++ kfree(hdmi->cached_edid); ++ hdmi->cached_edid = NULL; + } + + static enum drm_mode_status +@@ -3388,6 +3424,7 @@ EXPORT_SYMBOL_GPL(dw_hdmi_unbind); + + void dw_hdmi_resume(struct dw_hdmi *hdmi) + { ++ dw_hdmi_clear_edid(&hdmi->connector); + dw_hdmi_init_hw(hdmi); + } + EXPORT_SYMBOL_GPL(dw_hdmi_resume); + +From 94b8204bf9165575ee51d9e18c4a2df16e2199ed Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 28 Sep 2019 13:34:47 +0000 +Subject: [PATCH] drm: dw-hdmi: read edid in force callback + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 363f7c5a8016..dff27934287c 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -2405,6 +2405,13 @@ static void dw_hdmi_connector_force(struct drm_connector *connector) + dw_hdmi_update_power(hdmi); + dw_hdmi_update_phy_mask(hdmi); + mutex_unlock(&hdmi->mutex); ++ ++ dw_hdmi_clear_edid(connector); ++ ++ if (connector->status != connector_status_connected) ++ return; ++ ++ dw_hdmi_get_edid(connector); + } + + static const struct drm_connector_funcs dw_hdmi_connector_funcs = { + +From d2ba7dbdb7d87a1240aac2652bddb49ce147b790 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 28 Sep 2019 13:34:47 +0000 +Subject: [PATCH] drm: dw-hdmi: invalidate cec phys addr in detect callback + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 17 +++-------------- + 1 file changed, 3 insertions(+), 14 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index dff27934287c..c922639e25eb 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -190,7 +190,6 @@ struct dw_hdmi { + void (*enable_audio)(struct dw_hdmi *hdmi); + void (*disable_audio)(struct dw_hdmi *hdmi); + +- struct mutex cec_notifier_mutex; + struct cec_notifier *cec_notifier; + + hdmi_codec_plugged_cb plugged_cb; +@@ -2232,6 +2231,8 @@ static void dw_hdmi_clear_edid(struct drm_connector *connector) + + kfree(hdmi->cached_edid); + hdmi->cached_edid = NULL; ++ ++ cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); + } + + static void dw_hdmi_get_edid(struct drm_connector *connector) +@@ -2724,9 +2725,7 @@ static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) + if (!notifier) + return -ENOMEM; + +- mutex_lock(&hdmi->cec_notifier_mutex); + hdmi->cec_notifier = notifier; +- mutex_unlock(&hdmi->cec_notifier_mutex); + + return 0; + } +@@ -2735,10 +2734,8 @@ static void dw_hdmi_bridge_detach(struct drm_bridge *bridge) + { + struct dw_hdmi *hdmi = bridge->driver_private; + +- mutex_lock(&hdmi->cec_notifier_mutex); + cec_notifier_conn_unregister(hdmi->cec_notifier); + hdmi->cec_notifier = NULL; +- mutex_unlock(&hdmi->cec_notifier_mutex); + + kfree(hdmi->cached_edid); + hdmi->cached_edid = NULL; +@@ -2906,18 +2903,11 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) + * ask the source to re-read the EDID. + */ + if (intr_stat & +- (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { ++ (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) + dw_hdmi_setup_rx_sense(hdmi, + phy_stat & HDMI_PHY_HPD, + phy_stat & HDMI_PHY_RX_SENSE); + +- if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { +- mutex_lock(&hdmi->cec_notifier_mutex); +- cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); +- mutex_unlock(&hdmi->cec_notifier_mutex); +- } +- } +- + if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { + dev_dbg(hdmi->dev, "EVENT=%s\n", + phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); +@@ -3102,7 +3092,6 @@ __dw_hdmi_probe(struct platform_device *pdev, + + mutex_init(&hdmi->mutex); + mutex_init(&hdmi->audio_mutex); +- mutex_init(&hdmi->cec_notifier_mutex); + spin_lock_init(&hdmi->audio_lock); + + ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); + +From 59c0e09a4133d36772397e59224fd32f1410cc26 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 8 Dec 2019 23:41:44 +0000 +Subject: [PATCH] WIP: drm: dw-hdmi: do not force none scan mode + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index c922639e25eb..ea4f940406fc 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -1658,8 +1658,6 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) + break; + } + +- frame.scan_mode = HDMI_SCAN_MODE_NONE; +- + /* + * The Designware IP uses a different byte format from standard + * AVI info frames, though generally the bits are in the correct +