diff --git a/packages/tools/u-boot/patches/rockchip/u-boot-0005-rockchip-rk3288-get-serial-and-ethaddr-from-efuse.patch b/packages/tools/u-boot/patches/rockchip/u-boot-0005-rockchip-rk3288-get-serial-and-ethaddr-from-efuse.patch index bf14232101..193bd11e61 100644 --- a/packages/tools/u-boot/patches/rockchip/u-boot-0005-rockchip-rk3288-get-serial-and-ethaddr-from-efuse.patch +++ b/packages/tools/u-boot/patches/rockchip/u-boot-0005-rockchip-rk3288-get-serial-and-ethaddr-from-efuse.patch @@ -1,13 +1,13 @@ -From 050dd4323a9fe8515259fe855c31da6d1ad459e2 Mon Sep 17 00:00:00 2001 +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 5 Aug 2018 20:58:54 +0200 Subject: [PATCH] rockchip: rk3288: get serial and ethaddr from efuse --- arch/arm/dts/rk3288.dtsi | 5 ++--- - configs/miqi-rk3288_defconfig | 2 ++ - configs/tinker-rk3288_defconfig | 1 + - 3 files changed, 5 insertions(+), 3 deletions(-) + configs/miqi-rk3288_defconfig | 3 +++ + configs/tinker-rk3288_defconfig | 2 ++ + 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 20adb0dece..8b085ee6dc 100644 @@ -26,27 +26,29 @@ index 20adb0dece..8b085ee6dc 100644 gic: interrupt-controller@ffc01000 { diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig -index 09d5979dff..ffbe701cfd 100644 +index 09d5979dff..77d8f7dffc 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig -@@ -48,6 +48,8 @@ CONFIG_ROCKCHIP_GPIO=y +@@ -48,6 +48,9 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_DM_KEY=y CONFIG_ADC_KEY=y +CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y ++CONFIG_SHA256=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_DM_ETH=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig -index 3abf7c1088..0afc0a35e1 100644 +index 3abf7c1088..52196194c9 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig -@@ -46,6 +46,7 @@ CONFIG_SPL_CLK=y +@@ -46,6 +46,8 @@ CONFIG_SPL_CLK=y CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y +CONFIG_ROCKCHIP_EFUSE=y ++CONFIG_SHA256=y CONFIG_I2C_EEPROM=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y diff --git a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf index 8f5746419d..1bebcccdc8 100644 --- a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf +++ b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf @@ -2929,6 +2929,7 @@ CONFIG_SMS_SIANO_RC=y # CONFIG_V4L_PLATFORM_DRIVERS is not set CONFIG_V4L_MEM2MEM_DRIVERS=y # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set +CONFIG_VIDEO_ROCKCHIP_IEP=m CONFIG_VIDEO_ROCKCHIP_RGA=m # CONFIG_DVB_PLATFORM_DRIVERS is not set diff --git a/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf index 2fa064f441..bc764d6f7f 100644 --- a/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf @@ -3019,6 +3019,7 @@ CONFIG_SMS_SIANO_RC=y # CONFIG_V4L_PLATFORM_DRIVERS is not set CONFIG_V4L_MEM2MEM_DRIVERS=y # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set +CONFIG_VIDEO_ROCKCHIP_IEP=m CONFIG_VIDEO_ROCKCHIP_RGA=m # CONFIG_DVB_PLATFORM_DRIVERS is not set diff --git a/projects/Rockchip/devices/RK3399/config/kernel-firmware-any.dat b/projects/Rockchip/devices/RK3399/config/kernel-firmware-any.dat new file mode 100644 index 0000000000..5e0d28bb35 --- /dev/null +++ b/projects/Rockchip/devices/RK3399/config/kernel-firmware-any.dat @@ -0,0 +1,12 @@ +rockchip/* +ath10k/QCA6174 +ath10k/QCA9377 +ath10k/QCA9887 +ath10k/QCA9888 +ath10k/QCA988X +ath10k/QCA9984 +ath10k/QCA99X0 +iwlwifi-4965-2.ucode +iwlwifi-5* +iwlwifi-6* +mwlwifi/ diff --git a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf index 8f0ec8aed0..34f8a80793 100644 --- a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf @@ -2091,7 +2091,8 @@ CONFIG_AR5523=m # CONFIG_WIL6210 is not set CONFIG_ATH10K=m CONFIG_ATH10K_CE=y -# CONFIG_ATH10K_PCI is not set +CONFIG_ATH10K_PCI=m +# CONFIG_ATH10K_AHB is not set # CONFIG_ATH10K_SDIO is not set CONFIG_ATH10K_USB=m # CONFIG_ATH10K_DEBUG is not set @@ -2125,18 +2126,39 @@ CONFIG_BRCMUTIL=m # CONFIG_BRCMSMAC is not set CONFIG_BRCMFMAC=m CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_PROTO_MSGBUF=y CONFIG_BRCMFMAC_SDIO=y CONFIG_BRCMFMAC_USB=y -# CONFIG_BRCMFMAC_PCIE is not set +CONFIG_BRCMFMAC_PCIE=y # CONFIG_BRCM_TRACING is not set # CONFIG_BRCMDBG is not set CONFIG_WLAN_VENDOR_CISCO=y CONFIG_WLAN_VENDOR_INTEL=y # CONFIG_IPW2100 is not set # CONFIG_IPW2200 is not set -# CONFIG_IWL4965 is not set +CONFIG_IWLEGACY=m +CONFIG_IWL4965=m # CONFIG_IWL3945 is not set -# CONFIG_IWLWIFI is not set + +# +# iwl3945 / iwl4965 Debugging Options +# +# CONFIG_IWLEGACY_DEBUG is not set +# end of iwl3945 / iwl4965 Debugging Options + +CONFIG_IWLWIFI=m +CONFIG_IWLWIFI_LEDS=y +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m +CONFIG_IWLWIFI_OPMODE_MODULAR=y +# CONFIG_IWLWIFI_BCAST_FILTERING is not set + +# +# Debugging Options +# +# CONFIG_IWLWIFI_DEBUG is not set +# end of Debugging Options + CONFIG_WLAN_VENDOR_INTERSIL=y # CONFIG_HOSTAP is not set # CONFIG_HERMES is not set @@ -2158,7 +2180,7 @@ CONFIG_LIBERTAS_THINFIRM=m CONFIG_LIBERTAS_THINFIRM_USB=m CONFIG_MWIFIEX=m # CONFIG_MWIFIEX_SDIO is not set -# CONFIG_MWIFIEX_PCIE is not set +CONFIG_MWIFIEX_PCIE=m CONFIG_MWIFIEX_USB=m # CONFIG_MWL8K is not set CONFIG_WLAN_VENDOR_MEDIATEK=y @@ -2171,17 +2193,17 @@ CONFIG_MT76x02_LIB=m CONFIG_MT76x02_USB=m CONFIG_MT76x0_COMMON=m CONFIG_MT76x0U=m -# CONFIG_MT76x0E is not set +CONFIG_MT76x0E=m CONFIG_MT76x2_COMMON=m -# CONFIG_MT76x2E is not set +CONFIG_MT76x2E=m CONFIG_MT76x2U=m -# CONFIG_MT7603E is not set +CONFIG_MT7603E=m CONFIG_MT7615_COMMON=m -# CONFIG_MT7615E is not set +CONFIG_MT7615E=m CONFIG_MT7663_USB_SDIO_COMMON=m CONFIG_MT7663U=m CONFIG_MT7663S=m -# CONFIG_MT7915E is not set +CONFIG_MT7915E=m CONFIG_WLAN_VENDOR_MICROCHIP=y # CONFIG_WILC1000_SDIO is not set # CONFIG_WILC1000_SPI is not set @@ -3499,6 +3521,7 @@ CONFIG_SMS_SIANO_RC=y # CONFIG_V4L_PLATFORM_DRIVERS is not set CONFIG_V4L_MEM2MEM_DRIVERS=y # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set +CONFIG_VIDEO_ROCKCHIP_IEP=m CONFIG_VIDEO_ROCKCHIP_RGA=m # CONFIG_DVB_PLATFORM_DRIVERS is not set diff --git a/projects/Rockchip/patches/ffmpeg/ffmpeg-0002-WIP-deint-filter.patch b/projects/Rockchip/patches/ffmpeg/ffmpeg-0002-WIP-deint-filter.patch new file mode 100644 index 0000000000..34ccc5b6e0 --- /dev/null +++ b/projects/Rockchip/patches/ffmpeg/ffmpeg-0002-WIP-deint-filter.patch @@ -0,0 +1,924 @@ +From 39069d9cc03a42cd497dd6b9756116ff4b684a5d Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Tue, 3 Dec 2019 21:01:18 +0100 +Subject: [PATCH] WIP deint filter + +--- + libavfilter/Makefile | 1 + + libavfilter/allfilters.c | 1 + + libavfilter/vf_deinterlace_v4l2m2m.c | 879 +++++++++++++++++++++++++++ + 3 files changed, 881 insertions(+) + create mode 100644 libavfilter/vf_deinterlace_v4l2m2m.c + +diff --git a/libavfilter/Makefile b/libavfilter/Makefile +index 512354065305..625fd29f9313 100644 +--- a/libavfilter/Makefile ++++ b/libavfilter/Makefile +@@ -218,6 +218,7 @@ OBJS-$(CONFIG_DEFLATE_FILTER) += vf_neighbor.o + OBJS-$(CONFIG_DEFLICKER_FILTER) += vf_deflicker.o + OBJS-$(CONFIG_DEINTERLACE_QSV_FILTER) += vf_deinterlace_qsv.o + OBJS-$(CONFIG_DEINTERLACE_VAAPI_FILTER) += vf_deinterlace_vaapi.o vaapi_vpp.o ++OBJS-$(CONFIG_DEINTERLACE_V4L2M2M_FILTER) += vf_deinterlace_v4l2m2m.o + OBJS-$(CONFIG_DEJUDDER_FILTER) += vf_dejudder.o + OBJS-$(CONFIG_DELOGO_FILTER) += vf_delogo.o + OBJS-$(CONFIG_DENOISE_VAAPI_FILTER) += vf_misc_vaapi.o vaapi_vpp.o +diff --git a/libavfilter/allfilters.c b/libavfilter/allfilters.c +index 1183e4026751..fe5a2e8c02e8 100644 +--- a/libavfilter/allfilters.c ++++ b/libavfilter/allfilters.c +@@ -204,6 +204,7 @@ extern AVFilter ff_vf_dedot; + extern AVFilter ff_vf_deflate; + extern AVFilter ff_vf_deflicker; + extern AVFilter ff_vf_deinterlace_qsv; ++extern AVFilter ff_vf_deinterlace_v4l2m2m; + extern AVFilter ff_vf_deinterlace_vaapi; + extern AVFilter ff_vf_dejudder; + extern AVFilter ff_vf_delogo; +diff --git a/libavfilter/vf_deinterlace_v4l2m2m.c b/libavfilter/vf_deinterlace_v4l2m2m.c +new file mode 100644 +index 000000000000..1029e5b620fd +--- /dev/null ++++ b/libavfilter/vf_deinterlace_v4l2m2m.c +@@ -0,0 +1,879 @@ ++/* ++ * This file is part of FFmpeg. ++ * ++ * FFmpeg is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU Lesser General Public ++ * License as published by the Free Software Foundation; either ++ * version 2.1 of the License, or (at your option) any later version. ++ * ++ * FFmpeg is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * Lesser General Public License for more details. ++ * ++ * You should have received a copy of the GNU Lesser General Public ++ * License along with FFmpeg; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA ++ */ ++ ++/** ++ * @file ++ * deinterlace video filter - V4L2 M2M ++ */ ++ ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "libavutil/avassert.h" ++#include "libavutil/avstring.h" ++#include "libavutil/common.h" ++#include "libavutil/hwcontext.h" ++#include "libavutil/hwcontext_drm.h" ++#include "libavutil/internal.h" ++#include "libavutil/mathematics.h" ++#include "libavutil/opt.h" ++#include "libavutil/pixdesc.h" ++#include "libavutil/time.h" ++ ++#include "avfilter.h" ++#include "formats.h" ++#include "internal.h" ++#include "video.h" ++ ++typedef struct V4L2Queue V4L2Queue; ++typedef struct DeintV4L2M2MContextShared DeintV4L2M2MContextShared; ++ ++typedef struct V4L2PlaneInfo { ++ int bytesperline; ++ size_t length; ++} V4L2PlaneInfo; ++ ++typedef struct V4L2Buffer { ++ int enqueued; ++ int reenqueue; ++ int fd; ++ struct v4l2_buffer buffer; ++ struct v4l2_plane planes[VIDEO_MAX_PLANES]; ++ int num_planes; ++ V4L2PlaneInfo plane_info[VIDEO_MAX_PLANES]; ++ AVDRMFrameDescriptor drm_frame; ++ V4L2Queue *q; ++} V4L2Buffer; ++ ++typedef struct V4L2Queue { ++ struct v4l2_format format; ++ int num_buffers; ++ V4L2Buffer *buffers; ++ DeintV4L2M2MContextShared *ctx; ++} V4L2Queue; ++ ++typedef struct DeintV4L2M2MContextShared { ++ int fd; ++ int done; ++ int width; ++ int height; ++ int orig_width; ++ int orig_height; ++ atomic_uint refcount; ++ ++ AVBufferRef *hw_frames_ctx; ++ ++ int frame_count; ++ AVFrame *frames[2]; ++ ++ V4L2Queue output; ++ V4L2Queue capture; ++} DeintV4L2M2MContextShared; ++ ++typedef struct DeintV4L2M2MContext { ++ const AVClass *class; ++ ++ DeintV4L2M2MContextShared *shared; ++} DeintV4L2M2MContext; ++ ++static int deint_v4l2m2m_prepare_context(DeintV4L2M2MContextShared *ctx) ++{ ++ struct v4l2_capability cap; ++ int ret; ++ ++ memset(&cap, 0, sizeof(cap)); ++ ret = ioctl(ctx->fd, VIDIOC_QUERYCAP, &cap); ++ if (ret < 0) ++ return ret; ++ ++ if (!(cap.capabilities & V4L2_CAP_STREAMING)) ++ return AVERROR(EINVAL); ++ ++ if (cap.capabilities & V4L2_CAP_VIDEO_M2M) { ++ ctx->capture.format.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; ++ ctx->output.format.type = V4L2_BUF_TYPE_VIDEO_OUTPUT; ++ ++ return 0; ++ } ++ ++ if (cap.capabilities & V4L2_CAP_VIDEO_M2M_MPLANE) { ++ ctx->capture.format.type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; ++ ctx->output.format.type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; ++ ++ return 0; ++ } ++ ++ return AVERROR(EINVAL); ++} ++ ++static int deint_v4l2m2m_try_format(V4L2Queue *queue) ++{ ++ struct v4l2_format *fmt = &queue->format; ++ DeintV4L2M2MContextShared *ctx = queue->ctx; ++ int ret, field; ++ ++ ret = ioctl(ctx->fd, VIDIOC_G_FMT, fmt); ++ if (ret) ++ av_log(NULL, AV_LOG_ERROR, "VIDIOC_G_FMT failed: %d\n", ret); ++ ++ if (V4L2_TYPE_IS_OUTPUT(fmt->type)) ++ field = V4L2_FIELD_INTERLACED_TB; ++ else ++ field = V4L2_FIELD_NONE; ++ ++ if (V4L2_TYPE_IS_MULTIPLANAR(fmt->type)) { ++ fmt->fmt.pix_mp.pixelformat = V4L2_PIX_FMT_NV12; ++ fmt->fmt.pix_mp.field = field; ++ fmt->fmt.pix_mp.width = ctx->width; ++ fmt->fmt.pix_mp.height = ctx->height; ++ } else { ++ fmt->fmt.pix.pixelformat = V4L2_PIX_FMT_NV12; ++ fmt->fmt.pix.field = field; ++ fmt->fmt.pix.width = ctx->width; ++ fmt->fmt.pix.height = ctx->height; ++ } ++ ++ ret = ioctl(ctx->fd, VIDIOC_TRY_FMT, fmt); ++ if (ret) ++ return AVERROR(EINVAL); ++ ++ if (V4L2_TYPE_IS_MULTIPLANAR(fmt->type)) { ++ if (fmt->fmt.pix_mp.pixelformat != V4L2_PIX_FMT_NV12 || ++ fmt->fmt.pix_mp.field != field) { ++ av_log(NULL, AV_LOG_DEBUG, "format not supported for type %d\n", fmt->type); ++ ++ return AVERROR(EINVAL); ++ } ++ } else { ++ if (fmt->fmt.pix.pixelformat != V4L2_PIX_FMT_NV12 || ++ fmt->fmt.pix.field != field) { ++ av_log(NULL, AV_LOG_DEBUG, "format not supported for type %d\n", fmt->type); ++ ++ return AVERROR(EINVAL); ++ } ++ } ++ ++ return 0; ++} ++ ++static int deint_v4l2m2m_set_format(V4L2Queue *queue, uint32_t field, int width, int height) ++{ ++ struct v4l2_format *fmt = &queue->format; ++ DeintV4L2M2MContextShared *ctx = queue->ctx; ++ int ret; ++ ++ if (V4L2_TYPE_IS_MULTIPLANAR(fmt->type)) { ++ fmt->fmt.pix_mp.field = field; ++ fmt->fmt.pix_mp.width = width; ++ fmt->fmt.pix_mp.height = height; ++ /* TODO: bytesperline and imagesize */ ++ } else { ++ fmt->fmt.pix.field = field; ++ fmt->fmt.pix.width = width; ++ fmt->fmt.pix.height = height; ++ fmt->fmt.pix.sizeimage = 0; ++ fmt->fmt.pix.bytesperline = 0; ++ } ++ ++ ret = ioctl(ctx->fd, VIDIOC_S_FMT, fmt); ++ if (ret) ++ av_log(NULL, AV_LOG_ERROR, "VIDIOC_S_FMT failed: %d\n", ret); ++ ++ return ret; ++} ++ ++static int deint_v4l2m2m_probe_device(DeintV4L2M2MContextShared *ctx, char *node) ++{ ++ int ret; ++ ++ ctx->fd = open(node, O_RDWR | O_NONBLOCK, 0); ++ if (ctx->fd < 0) ++ return AVERROR(errno); ++ ++ ret = deint_v4l2m2m_prepare_context(ctx); ++ if (ret) ++ goto fail; ++ ++ ret = deint_v4l2m2m_try_format(&ctx->capture); ++ if (ret) ++ goto fail; ++ ++ ret = deint_v4l2m2m_try_format(&ctx->output); ++ if (ret) ++ goto fail; ++ ++ return 0; ++ ++fail: ++ close(ctx->fd); ++ ctx->fd = -1; ++ ++ return ret; ++} ++ ++static int deint_v4l2m2m_find_device(DeintV4L2M2MContextShared *ctx) ++{ ++ int ret = AVERROR(EINVAL); ++ struct dirent *entry; ++ char node[PATH_MAX]; ++ DIR *dirp; ++ ++ dirp = opendir("/dev"); ++ if (!dirp) ++ return AVERROR(errno); ++ ++ for (entry = readdir(dirp); entry; entry = readdir(dirp)) { ++ ++ if (strncmp(entry->d_name, "video", 5)) ++ continue; ++ ++ snprintf(node, sizeof(node), "/dev/%s", entry->d_name); ++ av_log(NULL, AV_LOG_DEBUG, "probing device %s\n", node); ++ ret = deint_v4l2m2m_probe_device(ctx, node); ++ if (!ret) ++ break; ++ } ++ ++ closedir(dirp); ++ ++ if (ret) { ++ av_log(NULL, AV_LOG_ERROR, "Could not find a valid device\n"); ++ ctx->fd = -1; ++ ++ return ret; ++ } ++ ++ av_log(NULL, AV_LOG_INFO, "Using device %s\n", node); ++ ++ return 0; ++} ++ ++static int deint_v4l2m2m_enqueue_buffer(V4L2Buffer *buf) ++{ ++ int ret; ++ ++ ret = ioctl(buf->q->ctx->fd, VIDIOC_QBUF, &buf->buffer); ++ if (ret < 0) ++ return AVERROR(errno); ++ ++ buf->enqueued = 1; ++ ++ return 0; ++} ++ ++static int v4l2_buffer_export_drm(V4L2Buffer* avbuf) ++{ ++ struct v4l2_exportbuffer expbuf; ++ int i, ret; ++ ++ for (i = 0; i < avbuf->num_planes; i++) { ++ memset(&expbuf, 0, sizeof(expbuf)); ++ ++ expbuf.index = avbuf->buffer.index; ++ expbuf.type = avbuf->buffer.type; ++ expbuf.plane = i; ++ ++ ret = ioctl(avbuf->q->ctx->fd, VIDIOC_EXPBUF, &expbuf); ++ if (ret < 0) ++ return AVERROR(errno); ++ ++ avbuf->fd = expbuf.fd; ++ ++ if (V4L2_TYPE_IS_MULTIPLANAR(avbuf->buffer.type)) { ++ /* drm frame */ ++ avbuf->drm_frame.objects[i].size = avbuf->buffer.m.planes[i].length; ++ avbuf->drm_frame.objects[i].fd = expbuf.fd; ++ avbuf->drm_frame.objects[i].format_modifier = DRM_FORMAT_MOD_LINEAR; ++ } else { ++ /* drm frame */ ++ avbuf->drm_frame.objects[0].size = avbuf->buffer.length; ++ avbuf->drm_frame.objects[0].fd = expbuf.fd; ++ avbuf->drm_frame.objects[0].format_modifier = DRM_FORMAT_MOD_LINEAR; ++ } ++ } ++ ++ return 0; ++} ++ ++static int deint_v4l2m2m_allocate_buffers(V4L2Queue *queue) ++{ ++ struct v4l2_format *fmt = &queue->format; ++ DeintV4L2M2MContextShared *ctx = queue->ctx; ++ struct v4l2_requestbuffers req; ++ int ret, i, j, multiplanar; ++ uint32_t memory; ++ ++ memory = V4L2_TYPE_IS_OUTPUT(fmt->type) ? ++ V4L2_MEMORY_DMABUF : V4L2_MEMORY_MMAP; ++ ++ multiplanar = V4L2_TYPE_IS_MULTIPLANAR(fmt->type); ++ ++ memset(&req, 0, sizeof(req)); ++ req.count = queue->num_buffers; ++ req.memory = memory; ++ req.type = fmt->type; ++ ++ ret = ioctl(ctx->fd, VIDIOC_REQBUFS, &req); ++ if (ret < 0) { ++ av_log(NULL, AV_LOG_ERROR, "VIDIOC_REQBUFS failed: %s\n", strerror(errno)); ++ ++ return AVERROR(errno); ++ } ++ ++ queue->num_buffers = req.count; ++ queue->buffers = av_mallocz(queue->num_buffers * sizeof(V4L2Buffer)); ++ if (!queue->buffers) { ++ av_log(NULL, AV_LOG_ERROR, "malloc enomem\n"); ++ ++ return AVERROR(ENOMEM); ++ } ++ ++ for (i = 0; i < queue->num_buffers; i++) { ++ V4L2Buffer *buf = &queue->buffers[i]; ++ ++ buf->enqueued = 0; ++ buf->fd = -1; ++ buf->q = queue; ++ ++ buf->buffer.type = fmt->type; ++ buf->buffer.memory = memory; ++ buf->buffer.index = i; ++ ++ if (multiplanar) { ++ buf->buffer.length = VIDEO_MAX_PLANES; ++ buf->buffer.m.planes = buf->planes; ++ } ++ ++ ret = ioctl(ctx->fd, VIDIOC_QUERYBUF, &buf->buffer); ++ if (ret < 0) { ++ ret = AVERROR(errno); ++ ++ goto fail; ++ } ++ ++ if (multiplanar) ++ buf->num_planes = buf->buffer.length; ++ else ++ buf->num_planes = 1; ++ ++ for (j = 0; j < buf->num_planes; j++) { ++ V4L2PlaneInfo *info = &buf->plane_info[j]; ++ ++ if (multiplanar) { ++ info->bytesperline = fmt->fmt.pix_mp.plane_fmt[j].bytesperline; ++ info->length = buf->buffer.m.planes[j].length; ++ } else { ++ info->bytesperline = fmt->fmt.pix.bytesperline; ++ info->length = buf->buffer.length; ++ } ++ } ++ ++ if (!V4L2_TYPE_IS_OUTPUT(fmt->type)) { ++ ret = deint_v4l2m2m_enqueue_buffer(buf); ++ if (ret) ++ goto fail; ++ ++ ret = v4l2_buffer_export_drm(buf); ++ if (ret) ++ goto fail; ++ } ++ } ++ ++ return 0; ++ ++fail: ++ for (i = 0; i < queue->num_buffers; i++) ++ if (queue->buffers[i].fd >= 0) ++ close(queue->buffers[i].fd); ++ av_free(queue->buffers); ++ queue->buffers = NULL; ++ ++ return ret; ++} ++ ++static int deint_v4l2m2m_streamon(V4L2Queue *queue) ++{ ++ int type = queue->format.type; ++ int ret; ++ ++ ret = ioctl(queue->ctx->fd, VIDIOC_STREAMON, &type); ++ if (ret < 0) ++ return AVERROR(errno); ++ ++ return 0; ++} ++ ++static int deint_v4l2m2m_streamoff(V4L2Queue *queue) ++{ ++ int type = queue->format.type; ++ int ret; ++ ++ ret = ioctl(queue->ctx->fd, VIDIOC_STREAMOFF, &type); ++ if (ret < 0) ++ return AVERROR(errno); ++ ++ return 0; ++} ++ ++static V4L2Buffer* deint_v4l2m2m_dequeue_buffer(V4L2Queue *queue, int timeout) ++{ ++ struct v4l2_plane planes[VIDEO_MAX_PLANES]; ++ DeintV4L2M2MContextShared *ctx = queue->ctx; ++ struct v4l2_buffer buf = { 0 }; ++ V4L2Buffer* avbuf = NULL; ++ struct pollfd pfd; ++ short events; ++ int ret; ++ ++ if (V4L2_TYPE_IS_OUTPUT(queue->format.type)) ++ events = POLLOUT | POLLWRNORM; ++ else ++ events = POLLIN | POLLRDNORM; ++ ++ pfd.events = events; ++ pfd.fd = ctx->fd; ++ ++ for (;;) { ++ ret = poll(&pfd, 1, timeout); ++ if (ret > 0) ++ break; ++ if (errno == EINTR) ++ continue; ++ return NULL; ++ } ++ ++ if (pfd.revents & POLLERR) ++ return NULL; ++ ++ if (pfd.revents & events) { ++ memset(&buf, 0, sizeof(buf)); ++ buf.memory = V4L2_MEMORY_MMAP; ++ buf.type = queue->format.type; ++ if (V4L2_TYPE_IS_MULTIPLANAR(queue->format.type)) { ++ memset(planes, 0, sizeof(planes)); ++ buf.length = VIDEO_MAX_PLANES; ++ buf.m.planes = planes; ++ } ++ ++ ret = ioctl(ctx->fd, VIDIOC_DQBUF, &buf); ++ if (ret) { ++ if (errno != EAGAIN) ++ av_log(NULL, AV_LOG_DEBUG, "VIDIOC_DQBUF, errno (%s)\n", ++ av_err2str(AVERROR(errno))); ++ return NULL; ++ } ++ ++ avbuf = &queue->buffers[buf.index]; ++ avbuf->enqueued = 0; ++ avbuf->buffer = buf; ++ if (V4L2_TYPE_IS_MULTIPLANAR(queue->format.type)) { ++ memcpy(avbuf->planes, planes, sizeof(planes)); ++ avbuf->buffer.m.planes = avbuf->planes; ++ } ++ ++ return avbuf; ++ } ++ ++ return NULL; ++} ++ ++static V4L2Buffer *deint_v4l2m2m_find_free_buf(V4L2Queue *queue) ++{ ++ int i; ++ ++ for (i = 0; i < queue->num_buffers; i++) ++ if (!queue->buffers[i].enqueued) ++ return &queue->buffers[i]; ++ ++ return NULL; ++} ++ ++static int deint_v4l2m2m_enqueue(V4L2Queue *queue, const AVFrame* frame) ++{ ++ AVDRMFrameDescriptor *drm_desc = (AVDRMFrameDescriptor *)frame->data[0]; ++ V4L2Buffer *buf; ++ int i; ++ ++ if (V4L2_TYPE_IS_OUTPUT(queue->format.type)) ++ while (deint_v4l2m2m_dequeue_buffer(queue, 0)); ++ ++ buf = deint_v4l2m2m_find_free_buf(queue); ++ if (!buf) ++ return AVERROR(ENOMEM); ++ ++ if (V4L2_TYPE_IS_MULTIPLANAR(buf->buffer.type)) ++ for (i = 0; i < drm_desc->nb_objects; i++) ++ buf->buffer.m.planes[i].m.fd = drm_desc->objects[i].fd; ++ else ++ buf->buffer.m.fd = drm_desc->objects[0].fd; ++ ++ return deint_v4l2m2m_enqueue_buffer(buf); ++} ++ ++static void deint_v4l2m2m_destroy_context(DeintV4L2M2MContextShared *ctx) ++{ ++ if (atomic_fetch_sub(&ctx->refcount, 1) == 1) { ++ V4L2Queue *capture = &ctx->capture; ++ V4L2Queue *output = &ctx->output; ++ int i; ++ ++ av_log(NULL, AV_LOG_DEBUG, "%s - destroying context\n", __func__); ++ ++ if (ctx->fd >= 0) { ++ deint_v4l2m2m_streamoff(capture); ++ deint_v4l2m2m_streamoff(output); ++ } ++ ++ if (capture->buffers) ++ for (i = 0; i < capture->num_buffers; i++) { ++ capture->buffers[i].q = NULL; ++ if (capture->buffers[i].fd >= 0) ++ close(capture->buffers[i].fd); ++ } ++ ++ for (i = 0; i < ctx->frame_count; i++) ++ av_frame_free(&ctx->frames[i]); ++ ++ av_buffer_unref(&ctx->hw_frames_ctx); ++ ++ if (capture->buffers) ++ av_free(capture->buffers); ++ ++ if (output->buffers) ++ av_free(output->buffers); ++ ++ if (ctx->fd >= 0) { ++ close(ctx->fd); ++ ctx->fd = -1; ++ } ++ ++ av_free(ctx); ++ } ++} ++ ++static void v4l2_free_buffer(void *opaque, uint8_t *unused) ++{ ++ V4L2Buffer *buf = opaque; ++ DeintV4L2M2MContextShared *ctx = buf->q->ctx; ++ ++ if (!ctx->done) ++ deint_v4l2m2m_enqueue_buffer(buf); ++ ++ deint_v4l2m2m_destroy_context(ctx); ++} ++ ++static uint8_t *v4l2_get_drm_frame(V4L2Buffer *avbuf, int height) ++{ ++ AVDRMFrameDescriptor *drm_desc = &avbuf->drm_frame; ++ AVDRMLayerDescriptor *layer; ++ ++ /* fill the DRM frame descriptor */ ++ drm_desc->nb_objects = avbuf->num_planes; ++ drm_desc->nb_layers = 1; ++ ++ layer = &drm_desc->layers[0]; ++ layer->nb_planes = avbuf->num_planes; ++ ++ for (int i = 0; i < avbuf->num_planes; i++) { ++ layer->planes[i].object_index = i; ++ layer->planes[i].offset = 0; ++ layer->planes[i].pitch = avbuf->plane_info[i].bytesperline; ++ } ++ ++ layer->format = DRM_FORMAT_NV12; ++ ++ if (avbuf->num_planes == 1) { ++ layer->nb_planes = 2; ++ ++ layer->planes[1].object_index = 0; ++ layer->planes[1].offset = avbuf->plane_info[0].bytesperline * height; ++ layer->planes[1].pitch = avbuf->plane_info[0].bytesperline; ++ } ++ ++ return (uint8_t *)drm_desc; ++} ++ ++static int deint_v4l2m2m_dequeue_frame(V4L2Queue *queue, AVFrame* frame, int timeout) ++{ ++ DeintV4L2M2MContextShared *ctx = queue->ctx; ++ V4L2Buffer* avbuf; ++ ++ avbuf = deint_v4l2m2m_dequeue_buffer(queue, timeout); ++ if (!avbuf) { ++ av_log(NULL, AV_LOG_ERROR, "dequeueing failed\n"); ++ return AVERROR(EINVAL); ++ } ++ ++ frame->buf[0] = av_buffer_create((uint8_t *) &avbuf->drm_frame, ++ sizeof(avbuf->drm_frame), v4l2_free_buffer, ++ avbuf, AV_BUFFER_FLAG_READONLY); ++ if (!frame->buf[0]) ++ return AVERROR(ENOMEM); ++ ++ atomic_fetch_add(&ctx->refcount, 1); ++ ++ frame->data[0] = (uint8_t *)v4l2_get_drm_frame(avbuf, ctx->orig_height); ++ frame->format = AV_PIX_FMT_DRM_PRIME; ++ frame->hw_frames_ctx = av_buffer_ref(ctx->hw_frames_ctx); ++ frame->height = ctx->height; ++ frame->width = ctx->width; ++ ++ if (avbuf->buffer.flags & V4L2_BUF_FLAG_ERROR) { ++ av_log(NULL, AV_LOG_ERROR, "driver decode error\n"); ++ frame->decode_error_flags |= FF_DECODE_ERROR_INVALID_BITSTREAM; ++ } ++ ++ return 0; ++} ++ ++static int deint_v4l2m2m_dequeue(AVFilterContext *avctx, AVFrame *input_frame, int field) ++{ ++ DeintV4L2M2MContext *priv = avctx->priv; ++ DeintV4L2M2MContextShared *ctx = priv->shared; ++ AVFilterLink *outlink = avctx->outputs[0]; ++ AVFrame *output_frame; ++ int err; ++ ++ output_frame = av_frame_alloc(); ++ ++ if (!output_frame) ++ return AVERROR(ENOMEM); ++ ++ err = deint_v4l2m2m_dequeue_frame(&ctx->capture, output_frame, 500); ++ if (err < 0) { ++ av_log(priv, AV_LOG_ERROR, "no frame (field %d)\n", field); ++ goto fail; ++ } ++ ++ err = av_frame_copy_props(output_frame, input_frame); ++ if (err < 0) ++ goto fail; ++ ++ output_frame->interlaced_frame = 0; ++ ++ if (field == 0) { ++ output_frame->pts *= 2; ++ } else { ++ int64_t cur_pts = ctx->frames[0]->pts; ++ int64_t next_pts = ctx->frames[1]->pts; ++ ++ if (next_pts != AV_NOPTS_VALUE && cur_pts != AV_NOPTS_VALUE) { ++ output_frame->pts = next_pts + cur_pts; ++ } else { ++ output_frame->pts = AV_NOPTS_VALUE; ++ } ++ } ++ av_log(priv, AV_LOG_DEBUG, "pts: %"PRId64" (field %d)\n", output_frame->pts, field); ++ ++ return ff_filter_frame(outlink, output_frame); ++ ++fail: ++ av_frame_free(&output_frame); ++ return err; ++} ++ ++static int deint_v4l2m2m_config_props(AVFilterLink *outlink) ++{ ++ AVFilterLink *inlink = outlink->src->inputs[0]; ++ AVFilterContext *avctx = outlink->src; ++ DeintV4L2M2MContext *priv = avctx->priv; ++ DeintV4L2M2MContextShared *ctx = priv->shared; ++ int ret; ++ ++ ctx->height = avctx->inputs[0]->h; ++ ctx->width = avctx->inputs[0]->w; ++ ++ outlink->frame_rate = av_mul_q(inlink->frame_rate, ++ (AVRational){ 2, 1 }); ++ outlink->time_base = av_mul_q(inlink->time_base, ++ (AVRational){ 1, 2 }); ++ ++ ret = deint_v4l2m2m_find_device(ctx); ++ if (ret) ++ return ret; ++ ++ if (!inlink->hw_frames_ctx) { ++ av_log(priv, AV_LOG_ERROR, "No hw context provided on input\n"); ++ return AVERROR(EINVAL); ++ } ++ ++ ctx->hw_frames_ctx = av_buffer_ref(inlink->hw_frames_ctx); ++ if (!ctx->hw_frames_ctx) ++ return AVERROR(ENOMEM); ++ ++ return 0; ++} ++ ++static int deint_v4l2m2m_query_formats(AVFilterContext *avctx) ++{ ++ static const enum AVPixelFormat pixel_formats[] = { ++ AV_PIX_FMT_DRM_PRIME, ++ AV_PIX_FMT_NONE, ++ }; ++ ++ return ff_set_common_formats(avctx, ff_make_format_list(pixel_formats)); ++} ++ ++static int deint_v4l2m2m_filter_frame(AVFilterLink *link, AVFrame *in) ++{ ++ AVFilterContext *avctx = link->dst; ++ DeintV4L2M2MContext *priv = avctx->priv; ++ DeintV4L2M2MContextShared *ctx = priv->shared; ++ V4L2Queue *capture = &ctx->capture; ++ V4L2Queue *output = &ctx->output; ++ int ret; ++ ++ av_log(priv, AV_LOG_DEBUG, "input pts: %"PRId64"\n", in->pts); ++ if (!ctx->frame_count) { ++ AVDRMFrameDescriptor *drm_desc = (AVDRMFrameDescriptor *)in->data[0]; ++ unsigned int field; ++ ++ ctx->orig_width = drm_desc->layers[0].planes[0].pitch; ++ ctx->orig_height = drm_desc->layers[0].planes[1].offset / ctx->orig_width; ++ ++ if (in->top_field_first) ++ field = V4L2_FIELD_INTERLACED_TB; ++ else ++ field = V4L2_FIELD_INTERLACED_BT; ++ ++ ret = deint_v4l2m2m_set_format(output, field, ctx->orig_width, ctx->orig_height); ++ if (ret) ++ return ret; ++ ++ ret = deint_v4l2m2m_set_format(capture, V4L2_FIELD_NONE, ctx->orig_width, ctx->orig_height); ++ if (ret) ++ return ret; ++ ++ ret = deint_v4l2m2m_allocate_buffers(capture); ++ if (ret) ++ return ret; ++ ++ ret = deint_v4l2m2m_streamon(capture); ++ if (ret) ++ return ret; ++ ++ ret = deint_v4l2m2m_allocate_buffers(output); ++ if (ret) ++ return ret; ++ ++ ret = deint_v4l2m2m_streamon(output); ++ if (ret) ++ return ret; ++ } ++ ++ if (ctx->frame_count < 2) { ++ ctx->frames[ctx->frame_count++] = in; ++ } else { ++ av_frame_free(&ctx->frames[0]); ++ ctx->frames[0] = ctx->frames[1]; ++ ctx->frames[1] = in; ++ } ++ ++ ret = deint_v4l2m2m_enqueue(output, in); ++ if (ret) ++ return ret; ++ ++ if (ctx->frame_count == 2) { ++ ret = deint_v4l2m2m_dequeue(avctx, ctx->frames[0], 0); ++ if (ret) ++ return ret; ++ ++ ret = deint_v4l2m2m_dequeue(avctx, ctx->frames[0], 1); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static av_cold int deint_v4l2m2m_init(AVFilterContext *avctx) ++{ ++ DeintV4L2M2MContext *priv = avctx->priv; ++ DeintV4L2M2MContextShared *ctx; ++ ++ ctx = av_mallocz(sizeof(DeintV4L2M2MContextShared)); ++ if (!ctx) ++ return AVERROR(ENOMEM); ++ ++ priv->shared = ctx; ++ ctx->fd = -1; ++ ctx->output.ctx = ctx; ++ ctx->output.num_buffers = 6; ++ ctx->capture.ctx = ctx; ++ ctx->capture.num_buffers = 6; ++ ctx->done = 0; ++ atomic_init(&ctx->refcount, 1); ++ ++ return 0; ++} ++ ++static void deint_v4l2m2m_uninit(AVFilterContext *avctx) ++{ ++ DeintV4L2M2MContext *priv = avctx->priv; ++ DeintV4L2M2MContextShared *ctx = priv->shared; ++ ++ ctx->done = 1; ++ deint_v4l2m2m_destroy_context(ctx); ++} ++ ++static const AVOption deinterlace_v4l2m2m_options[] = { ++ { NULL }, ++}; ++ ++AVFILTER_DEFINE_CLASS(deinterlace_v4l2m2m); ++ ++static const AVFilterPad deint_v4l2m2m_inputs[] = { ++ { ++ .name = "default", ++ .type = AVMEDIA_TYPE_VIDEO, ++ .filter_frame = deint_v4l2m2m_filter_frame, ++ }, ++ { NULL } ++}; ++ ++static const AVFilterPad deint_v4l2m2m_outputs[] = { ++ { ++ .name = "default", ++ .type = AVMEDIA_TYPE_VIDEO, ++ .config_props = deint_v4l2m2m_config_props, ++ }, ++ { NULL } ++}; ++ ++AVFilter ff_vf_deinterlace_v4l2m2m = { ++ .name = "deinterlace_v4l2m2m", ++ .description = NULL_IF_CONFIG_SMALL("V4L2 M2M deinterlacer"), ++ .priv_size = sizeof(DeintV4L2M2MContext), ++ .init = &deint_v4l2m2m_init, ++ .uninit = &deint_v4l2m2m_uninit, ++ .query_formats = &deint_v4l2m2m_query_formats, ++ .inputs = deint_v4l2m2m_inputs, ++ .outputs = deint_v4l2m2m_outputs, ++ .priv_class = &deinterlace_v4l2m2m_class, ++}; +-- +2.29.2 + diff --git a/projects/Rockchip/patches/ffmpeg/ffmpeg-0003-libavfilter-v4l2deinterlace-dequeue-both-destination.patch b/projects/Rockchip/patches/ffmpeg/ffmpeg-0003-libavfilter-v4l2deinterlace-dequeue-both-destination.patch new file mode 100644 index 0000000000..cefbd9c64d --- /dev/null +++ b/projects/Rockchip/patches/ffmpeg/ffmpeg-0003-libavfilter-v4l2deinterlace-dequeue-both-destination.patch @@ -0,0 +1,230 @@ +From 6bea46839ba23bffaa093bb9ed805d571aaa66ea Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 30 Sep 2020 21:11:34 +0200 +Subject: [PATCH] libavfilter: v4l2deinterlace: dequeue both destination + buffers on time + +Signed-off-by: Alex Bee +--- + libavfilter/vf_deinterlace_v4l2m2m.c | 140 +++++++++++++++++---------- + 1 file changed, 88 insertions(+), 52 deletions(-) + +diff --git a/libavfilter/vf_deinterlace_v4l2m2m.c b/libavfilter/vf_deinterlace_v4l2m2m.c +index 1029e5b620fd..72d28333ffa7 100644 +--- a/libavfilter/vf_deinterlace_v4l2m2m.c ++++ b/libavfilter/vf_deinterlace_v4l2m2m.c +@@ -89,8 +89,14 @@ typedef struct DeintV4L2M2MContextShared { + + AVBufferRef *hw_frames_ctx; + +- int frame_count; +- AVFrame *frames[2]; ++ /* ++ * TODO: check if its really neccessary to hold this ++ * ref, it's only used for freeing av_frame on decoding ++ * end/abort ++ */ ++ AVFrame *cur_in_frame; ++ AVFrame *prev_in_frame; ++ unsigned int field_order; + + V4L2Queue output; + V4L2Queue capture; +@@ -557,8 +563,11 @@ static void deint_v4l2m2m_destroy_context(DeintV4L2M2MContextShared *ctx) + close(capture->buffers[i].fd); + } + +- for (i = 0; i < ctx->frame_count; i++) +- av_frame_free(&ctx->frames[i]); ++ if (ctx->cur_in_frame) ++ av_frame_free(&ctx->cur_in_frame); ++ ++ if (ctx->prev_in_frame) ++ av_frame_free(&ctx->prev_in_frame); + + av_buffer_unref(&ctx->hw_frames_ctx); + +@@ -652,49 +661,79 @@ static int deint_v4l2m2m_dequeue_frame(V4L2Queue *queue, AVFrame* frame, int tim + return 0; + } + +-static int deint_v4l2m2m_dequeue(AVFilterContext *avctx, AVFrame *input_frame, int field) ++static int deint_v4l2m2m_dequeue(AVFilterContext *avctx, AVFrame *input_frame) + { + DeintV4L2M2MContext *priv = avctx->priv; + DeintV4L2M2MContextShared *ctx = priv->shared; + AVFilterLink *outlink = avctx->outputs[0]; +- AVFrame *output_frame; ++ AVFrame *output_frame_1, *output_frame_2; ++ int64_t first_pts = AV_NOPTS_VALUE; + int err; + +- output_frame = av_frame_alloc(); ++ av_log(priv, AV_LOG_DEBUG, "input pts: %"PRId64" (field %d)\n", ++ input_frame->pts, ctx->field_order); + +- if (!output_frame) ++ output_frame_1 = av_frame_alloc(); ++ if (!output_frame_1) + return AVERROR(ENOMEM); + +- err = deint_v4l2m2m_dequeue_frame(&ctx->capture, output_frame, 500); ++ err = deint_v4l2m2m_dequeue_frame(&ctx->capture, output_frame_1, 500); + if (err < 0) { +- av_log(priv, AV_LOG_ERROR, "no frame (field %d)\n", field); +- goto fail; ++ av_log(priv, AV_LOG_ERROR, "no 1st frame (field %d)\n", ctx->field_order); ++ goto fail_out1; + } + +- err = av_frame_copy_props(output_frame, input_frame); ++ err = av_frame_copy_props(output_frame_1, input_frame); + if (err < 0) +- goto fail; ++ goto fail_out1; + +- output_frame->interlaced_frame = 0; ++ output_frame_1->interlaced_frame = 0; + +- if (field == 0) { +- output_frame->pts *= 2; +- } else { +- int64_t cur_pts = ctx->frames[0]->pts; +- int64_t next_pts = ctx->frames[1]->pts; ++ output_frame_2 = av_frame_alloc(); ++ if (!output_frame_2) { ++ err = AVERROR(ENOMEM); ++ goto fail_out1; ++ } ++ ++ err = deint_v4l2m2m_dequeue_frame(&ctx->capture, output_frame_2, 500); ++ if (err < 0) { ++ av_log(priv, AV_LOG_ERROR, "no 2nd frame (field %d)\n", ctx->field_order); ++ goto fail_out2; ++ } ++ ++ err = av_frame_copy_props(output_frame_2, input_frame); ++ if (err < 0) ++ goto fail_out2; ++ ++ output_frame_2->interlaced_frame = 0; + +- if (next_pts != AV_NOPTS_VALUE && cur_pts != AV_NOPTS_VALUE) { +- output_frame->pts = next_pts + cur_pts; +- } else { +- output_frame->pts = AV_NOPTS_VALUE; +- } ++ if (ctx->prev_in_frame && ctx->prev_in_frame->pts != AV_NOPTS_VALUE ++ && input_frame->pts != AV_NOPTS_VALUE) { ++ first_pts = (ctx->prev_in_frame->pts + input_frame->pts) / 2; ++ av_log(priv, AV_LOG_DEBUG, "calculated first pts %"PRId64"\n", first_pts); + } +- av_log(priv, AV_LOG_DEBUG, "pts: %"PRId64" (field %d)\n", output_frame->pts, field); + +- return ff_filter_frame(outlink, output_frame); ++ output_frame_1->pts = first_pts; ++ ++ err = ff_filter_frame(outlink, output_frame_1); ++ if (err < 0) { ++ av_frame_free(&output_frame_2); ++ return err; ++ } ++ err = ff_filter_frame(outlink, output_frame_2); ++ ++ if (err < 0) ++ return err; ++ ++ av_log(priv, AV_LOG_DEBUG, "1st frame pts: %"PRId64" 2nd frame pts: %"PRId64" first pts: %"PRId64" (field %d)\n", ++ output_frame_1->pts, output_frame_2->pts, first_pts, ctx->field_order); ++ ++ return 0; + +-fail: +- av_frame_free(&output_frame); ++fail_out2: ++ av_frame_free(&output_frame_2); ++fail_out1: ++ av_frame_free(&output_frame_1); + return err; + } + +@@ -749,20 +788,22 @@ static int deint_v4l2m2m_filter_frame(AVFilterLink *link, AVFrame *in) + V4L2Queue *output = &ctx->output; + int ret; + +- av_log(priv, AV_LOG_DEBUG, "input pts: %"PRId64"\n", in->pts); +- if (!ctx->frame_count) { ++ av_log(priv, AV_LOG_DEBUG, "input pts: %"PRId64" field :%d interlaced: %d\n", ++ in->pts, in->top_field_first, in->interlaced_frame); ++ ++ ctx->cur_in_frame = in; ++ ++ if (ctx->field_order == V4L2_FIELD_ANY) { + AVDRMFrameDescriptor *drm_desc = (AVDRMFrameDescriptor *)in->data[0]; +- unsigned int field; +- + ctx->orig_width = drm_desc->layers[0].planes[0].pitch; + ctx->orig_height = drm_desc->layers[0].planes[1].offset / ctx->orig_width; + +- if (in->top_field_first) +- field = V4L2_FIELD_INTERLACED_TB; ++ if (in->top_field_first) ++ ctx->field_order = V4L2_FIELD_INTERLACED_TB; + else +- field = V4L2_FIELD_INTERLACED_BT; ++ ctx->field_order = V4L2_FIELD_INTERLACED_BT; + +- ret = deint_v4l2m2m_set_format(output, field, ctx->orig_width, ctx->orig_height); ++ ret = deint_v4l2m2m_set_format(output, ctx->field_order, ctx->orig_width, ctx->orig_height); + if (ret) + return ret; + +@@ -787,27 +828,19 @@ static int deint_v4l2m2m_filter_frame(AVFilterLink *link, AVFrame *in) + return ret; + } + +- if (ctx->frame_count < 2) { +- ctx->frames[ctx->frame_count++] = in; +- } else { +- av_frame_free(&ctx->frames[0]); +- ctx->frames[0] = ctx->frames[1]; +- ctx->frames[1] = in; +- } +- + ret = deint_v4l2m2m_enqueue(output, in); + if (ret) + return ret; + +- if (ctx->frame_count == 2) { +- ret = deint_v4l2m2m_dequeue(avctx, ctx->frames[0], 0); +- if (ret) +- return ret; ++ ret = deint_v4l2m2m_dequeue(avctx, in); ++ if (ret) ++ return ret; + +- ret = deint_v4l2m2m_dequeue(avctx, ctx->frames[0], 1); +- if (ret) +- return ret; +- } ++ if (ctx->prev_in_frame) ++ av_frame_free(&ctx->prev_in_frame); ++ ++ ctx->prev_in_frame = in; ++ ctx->cur_in_frame = NULL; + + return 0; + } +@@ -828,6 +861,9 @@ static av_cold int deint_v4l2m2m_init(AVFilterContext *avctx) + ctx->capture.ctx = ctx; + ctx->capture.num_buffers = 6; + ctx->done = 0; ++ ctx->field_order = V4L2_FIELD_ANY; ++ ctx->cur_in_frame = NULL; ++ ctx->prev_in_frame = NULL; + atomic_init(&ctx->refcount, 1); + + return 0; +-- +2.29.2 + diff --git a/projects/Rockchip/patches/kodi/0001-WIP-DVDVideoCodecDRMPRIME-add-support-for-filters.patch b/projects/Rockchip/patches/kodi/0001-WIP-DVDVideoCodecDRMPRIME-add-support-for-filters.patch new file mode 100644 index 0000000000..9e11fbd55c --- /dev/null +++ b/projects/Rockchip/patches/kodi/0001-WIP-DVDVideoCodecDRMPRIME-add-support-for-filters.patch @@ -0,0 +1,145 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 20 Oct 2019 17:10:07 +0000 +Subject: [PATCH] WIP: DVDVideoCodecDRMPRIME: add support for filters + +--- + .../DVDCodecs/Video/DVDVideoCodecDRMPRIME.cpp | 68 ++++++++++++++++--- + .../DVDCodecs/Video/DVDVideoCodecDRMPRIME.h | 10 +++ + 2 files changed, 69 insertions(+), 9 deletions(-) + +diff --git a/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.cpp b/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.cpp +index 8024c20816..7507c12e9a 100644 +--- a/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.cpp ++++ b/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.cpp +@@ -27,6 +27,8 @@ + extern "C" + { + #include ++#include ++#include + #include + #include + #include +@@ -525,18 +527,30 @@ void CDVDVideoCodecDRMPRIME::SetPictureParams(VideoPicture* pVideoPicture) + pVideoPicture->dts = DVD_NOPTS_VALUE; + } + +-CDVDVideoCodec::VCReturn CDVDVideoCodecDRMPRIME::GetPicture(VideoPicture* pVideoPicture) ++CDVDVideoCodec::VCReturn CDVDVideoCodecDRMPRIME::ProcessFilterIn() + { +- if (m_codecControlFlags & DVD_CODEC_CTRL_DRAIN) +- Drain(); ++ if (!m_pFilterIn) ++ return VC_PICTURE; + +- if (pVideoPicture->videoBuffer) ++ int ret = av_buffersrc_add_frame(m_pFilterIn, m_pFrame); ++ if (ret < 0) + { +- pVideoPicture->videoBuffer->Release(); +- pVideoPicture->videoBuffer = nullptr; ++ char err[AV_ERROR_MAX_STRING_SIZE] = {}; ++ av_strerror(ret, err, AV_ERROR_MAX_STRING_SIZE); ++ CLog::Log(LOGERROR, "CDVDVideoCodecDRMPRIME::{} - buffersrc add frame failed: {} ({})", ++ __FUNCTION__, err, ret); ++ return VC_ERROR; + } + +- int ret = avcodec_receive_frame(m_pCodecContext, m_pFrame); ++ return ProcessFilterOut(); ++} ++ ++CDVDVideoCodec::VCReturn CDVDVideoCodecDRMPRIME::ProcessFilterOut() ++{ ++ if (!m_pFilterOut) ++ return VC_EOF; ++ ++ int ret = av_buffersink_get_frame(m_pFilterOut, m_pFrame); + if (ret == AVERROR(EAGAIN)) + return VC_BUFFER; + else if (ret == AVERROR_EOF) +@@ -553,11 +567,47 @@ CDVDVideoCodec::VCReturn CDVDVideoCodecDRMPRIME::GetPicture(VideoPicture* pVideo + { + char err[AV_ERROR_MAX_STRING_SIZE] = {}; + av_strerror(ret, err, AV_ERROR_MAX_STRING_SIZE); +- CLog::Log(LOGERROR, "CDVDVideoCodecDRMPRIME::{} - receive frame failed: {} ({})", __FUNCTION__, +- err, ret); ++ CLog::Log(LOGERROR, "CDVDVideoCodecDRMPRIME::{} - buffersink get frame failed: {} ({})", ++ __FUNCTION__, err, ret); + return VC_ERROR; + } + ++ return VC_PICTURE; ++} ++ ++CDVDVideoCodec::VCReturn CDVDVideoCodecDRMPRIME::GetPicture(VideoPicture* pVideoPicture) ++{ ++ if (m_codecControlFlags & DVD_CODEC_CTRL_DRAIN) ++ Drain(); ++ ++ if (pVideoPicture->videoBuffer) ++ { ++ pVideoPicture->videoBuffer->Release(); ++ pVideoPicture->videoBuffer = nullptr; ++ } ++ ++ auto result = ProcessFilterOut(); ++ if (result != VC_PICTURE) ++ { ++ int ret = avcodec_receive_frame(m_pCodecContext, m_pFrame); ++ if (ret == AVERROR(EAGAIN)) ++ return VC_BUFFER; ++ else if (ret == AVERROR_EOF) ++ return VC_EOF; ++ else if (ret) ++ { ++ char err[AV_ERROR_MAX_STRING_SIZE] = {}; ++ av_strerror(ret, err, AV_ERROR_MAX_STRING_SIZE); ++ CLog::Log(LOGERROR, "CDVDVideoCodecDRMPRIME::{} - receive frame failed: {} ({})", ++ __FUNCTION__, err, ret); ++ return VC_ERROR; ++ } ++ ++ result = ProcessFilterIn(); ++ if (result != VC_PICTURE) ++ return result; ++ } ++ + SetPictureParams(pVideoPicture); + + if (IsSupportedHwFormat(static_cast(m_pFrame->format))) +diff --git a/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.h b/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.h +index 77d066c3d9..7112d1b48a 100644 +--- a/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.h ++++ b/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.h +@@ -14,6 +14,11 @@ + + #include + ++extern "C" ++{ ++#include ++} ++ + class CDVDVideoCodecDRMPRIME : public CDVDVideoCodec + { + public: +@@ -35,6 +40,8 @@ protected: + void Drain(); + void SetPictureParams(VideoPicture* pVideoPicture); + void UpdateProcessInfo(struct AVCodecContext* avctx, const enum AVPixelFormat fmt); ++ CDVDVideoCodec::VCReturn ProcessFilterIn(); ++ CDVDVideoCodec::VCReturn ProcessFilterOut(); + static enum AVPixelFormat GetFormat(struct AVCodecContext* avctx, const enum AVPixelFormat* fmt); + static int GetBuffer(struct AVCodecContext* avctx, AVFrame* frame, int flags); + +@@ -43,5 +50,8 @@ protected: + CDVDStreamInfo m_hints; + AVCodecContext* m_pCodecContext = nullptr; + AVFrame* m_pFrame = nullptr; ++ AVFilterGraph* m_pFilterGraph = nullptr; ++ AVFilterContext* m_pFilterIn = nullptr; ++ AVFilterContext* m_pFilterOut = nullptr; + std::shared_ptr m_videoBufferPool; + }; diff --git a/projects/Rockchip/patches/kodi/0002-WIP-DRMPRIME-deinterlace-filter.patch b/projects/Rockchip/patches/kodi/0002-WIP-DRMPRIME-deinterlace-filter.patch new file mode 100644 index 0000000000..0e19bb6788 --- /dev/null +++ b/projects/Rockchip/patches/kodi/0002-WIP-DRMPRIME-deinterlace-filter.patch @@ -0,0 +1,500 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Thu, 26 Dec 2019 11:01:51 +0100 +Subject: [PATCH] WIP: DRMPRIME deinterlace filter + +--- + .../DVDCodecs/Video/DVDVideoCodecDRMPRIME.cpp | 368 +++++++++++++++--- + .../DVDCodecs/Video/DVDVideoCodecDRMPRIME.h | 9 +- + 2 files changed, 322 insertions(+), 55 deletions(-) + +diff --git a/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.cpp b/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.cpp +index 7507c12e9a..4759dde3f9 100644 +--- a/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.cpp ++++ b/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.cpp +@@ -79,12 +79,15 @@ CDVDVideoCodecDRMPRIME::CDVDVideoCodecDRMPRIME(CProcessInfo& processInfo) + : CDVDVideoCodec(processInfo) + { + m_pFrame = av_frame_alloc(); ++ m_pFilterFrame = av_frame_alloc(); + m_videoBufferPool = std::make_shared(); + } + + CDVDVideoCodecDRMPRIME::~CDVDVideoCodecDRMPRIME() + { + av_frame_free(&m_pFrame); ++ av_frame_free(&m_pFilterFrame); ++ FilterClose(); + avcodec_free_context(&m_pCodecContext); + } + +@@ -341,8 +344,19 @@ bool CDVDVideoCodecDRMPRIME::Open(CDVDStreamInfo& hints, CDVDCodecOptions& optio + } + + UpdateProcessInfo(m_pCodecContext, m_pCodecContext->pix_fmt); +- m_processInfo.SetVideoDeintMethod("none"); ++ m_processInfo.SetVideoInterlaced(false); + m_processInfo.SetVideoDAR(hints.aspect); ++ m_processInfo.SetVideoDeintMethod("none"); ++ ++ FilterTest(); ++ ++ if (!m_deintFilterName.empty()) ++ { ++ std::list methods; ++ methods.push_back(EINTERLACEMETHOD::VS_INTERLACEMETHOD_DEINTERLACE); ++ m_processInfo.UpdateDeinterlacingMethods(methods); ++ m_processInfo.SetDeinterlacingMethodDefault(EINTERLACEMETHOD::VS_INTERLACEMETHOD_DEINTERLACE); ++ } + + return true; + } +@@ -405,6 +419,8 @@ void CDVDVideoCodecDRMPRIME::Reset() + return; + + Drain(); ++ m_filters.clear(); ++ FilterClose(); + + do + { +@@ -443,7 +459,7 @@ void CDVDVideoCodecDRMPRIME::Drain() + } + } + +-void CDVDVideoCodecDRMPRIME::SetPictureParams(VideoPicture* pVideoPicture) ++bool CDVDVideoCodecDRMPRIME::SetPictureParams(VideoPicture* pVideoPicture) + { + pVideoPicture->iWidth = m_pFrame->width; + pVideoPicture->iHeight = m_pFrame->height; +@@ -525,13 +541,232 @@ void CDVDVideoCodecDRMPRIME::SetPictureParams(VideoPicture* pVideoPicture) + ? DVD_NOPTS_VALUE + : static_cast(pts) * DVD_TIME_BASE / AV_TIME_BASE; + pVideoPicture->dts = DVD_NOPTS_VALUE; ++ ++ if (IsSupportedHwFormat(static_cast(m_pFrame->format))) ++ { ++ CVideoBufferDRMPRIMEFFmpeg* buffer = ++ dynamic_cast(m_videoBufferPool->Get()); ++ buffer->SetPictureParams(*pVideoPicture); ++ buffer->SetRef(m_pFrame); ++ pVideoPicture->videoBuffer = buffer; ++ } ++ else if (m_pFrame->opaque) ++ { ++ CVideoBufferDMA* buffer = static_cast(m_pFrame->opaque); ++ buffer->SetPictureParams(*pVideoPicture); ++ buffer->Acquire(); ++ buffer->SyncEnd(); ++ buffer->SetDimensions(m_pFrame->width, m_pFrame->height); ++ ++ pVideoPicture->videoBuffer = buffer; ++ av_frame_unref(m_pFrame); ++ } ++ ++ if (!pVideoPicture->videoBuffer) ++ { ++ CLog::Log(LOGERROR, "CDVDVideoCodecDRMPRIME::{} - videoBuffer:nullptr format:{}", __FUNCTION__, ++ av_get_pix_fmt_name(static_cast(m_pFrame->format))); ++ av_frame_unref(m_pFrame); ++ return false; ++ } ++ ++ return true; + } + +-CDVDVideoCodec::VCReturn CDVDVideoCodecDRMPRIME::ProcessFilterIn() ++void CDVDVideoCodecDRMPRIME::FilterTest() ++{ ++ const AVFilter* filter; ++ void* opaque{}; ++ ++ m_deintFilterName.clear(); ++ ++ while ((filter = av_filter_iterate(&opaque)) != nullptr) ++ { ++ std::string name(filter->name); ++ ++ if (name.find("deinterlace") != std::string::npos) ++ { ++ if (FilterOpen(name, true)) ++ { ++ m_deintFilterName = name; ++ ++ CLog::Log(LOGDEBUG, "CDVDVideoCodecDRMPRIME::{} - found deinterlacing filter {}", ++ __FUNCTION__, name); ++ ++ return; ++ } ++ } ++ } ++ ++ CLog::Log(LOGDEBUG, "CDVDVideoCodecDRMPRIME::{} - no deinterlacing filter found", ++ __FUNCTION__); ++} ++ ++bool CDVDVideoCodecDRMPRIME::FilterOpen(const std::string& filters, bool test) ++{ ++ int result; ++ ++ if (m_pFilterGraph) ++ FilterClose(); ++ ++ if (filters.empty()) ++ return true; ++ ++ if (!(m_pFilterGraph = avfilter_graph_alloc())) ++ { ++ CLog::Log(LOGERROR, "CDVDVideoCodecDRMPRIME::FilterOpen - unable to alloc filter graph"); ++ return false; ++ } ++ ++ const AVFilter* srcFilter = avfilter_get_by_name("buffer"); ++ const AVFilter* outFilter = avfilter_get_by_name("buffersink"); ++ enum AVPixelFormat pix_fmts[] = { AV_PIX_FMT_DRM_PRIME, AV_PIX_FMT_NONE }; ++ ++ std::string args = StringUtils::Format("video_size=%dx%d:pix_fmt=%d:time_base=%d/%d:" ++ "pixel_aspect=%d/%d:sws_param=flags=2", ++ m_pCodecContext->width, ++ m_pCodecContext->height, ++ m_pCodecContext->pix_fmt, ++ m_pCodecContext->time_base.num ? ++ m_pCodecContext->time_base.num : 1, ++ m_pCodecContext->time_base.num ? ++ m_pCodecContext->time_base.den : 1, ++ m_pCodecContext->sample_aspect_ratio.num != 0 ? ++ m_pCodecContext->sample_aspect_ratio.num : 1, ++ m_pCodecContext->sample_aspect_ratio.num != 0 ? ++ m_pCodecContext->sample_aspect_ratio.den : 1); ++ ++ result = avfilter_graph_create_filter(&m_pFilterIn, srcFilter, "src", ++ args.c_str(), NULL, m_pFilterGraph); ++ if (result < 0) ++ { ++ char err[AV_ERROR_MAX_STRING_SIZE] = {}; ++ av_strerror(result, err, AV_ERROR_MAX_STRING_SIZE); ++ CLog::Log(LOGERROR, ++ "CDVDVideoCodecDRMPRIME::FilterOpen - avfilter_graph_create_filter: src: {} ({})", ++ err, result); ++ return false; ++ } ++ ++ AVBufferSrcParameters *par = av_buffersrc_parameters_alloc(); ++ if (!par) ++ { ++ CLog::Log(LOGERROR, "CDVDVideoCodecDRMPRIME::FilterOpen - unable to alloc buffersrc"); ++ return false; ++ } ++ ++ memset(par, 0, sizeof(*par)); ++ par->format = AV_PIX_FMT_NONE; ++ par->hw_frames_ctx = m_pCodecContext->hw_device_ctx; ++ ++ result = av_buffersrc_parameters_set(m_pFilterIn, par); ++ if (result < 0) ++ { ++ char err[AV_ERROR_MAX_STRING_SIZE] = {}; ++ av_strerror(result, err, AV_ERROR_MAX_STRING_SIZE); ++ CLog::Log(LOGERROR, ++ "CDVDVideoCodecDRMPRIME::FilterOpen - av_buffersrc_parameters_set: {} ({})", ++ err, result); ++ return false; ++ } ++ av_freep(&par); ++ ++ result = avfilter_graph_create_filter(&m_pFilterOut, outFilter, "out", ++ NULL, NULL, m_pFilterGraph); ++ if (result < 0) ++ { ++ char err[AV_ERROR_MAX_STRING_SIZE] = {}; ++ av_strerror(result, err, AV_ERROR_MAX_STRING_SIZE); ++ CLog::Log(LOGERROR, ++ "CDVDVideoCodecDRMPRIME::FilterOpen - avfilter_graph_create_filter: out: {} ({})", ++ err, result); ++ return false; ++ } ++ ++ result = av_opt_set_int_list(m_pFilterOut, "pix_fmts", &pix_fmts[0], ++ AV_PIX_FMT_NONE, AV_OPT_SEARCH_CHILDREN); ++ if (result < 0) ++ { ++ CLog::Log(LOGERROR, "CDVDVideoCodecDRMPRIME::FilterOpen - failed settings pix formats"); ++ return false; ++ } ++ ++ AVFilterInOut* outputs = avfilter_inout_alloc(); ++ AVFilterInOut* inputs = avfilter_inout_alloc(); ++ ++ outputs->name = av_strdup("in"); ++ outputs->filter_ctx = m_pFilterIn; ++ outputs->pad_idx = 0; ++ outputs->next = nullptr; ++ ++ inputs->name = av_strdup("out"); ++ inputs->filter_ctx = m_pFilterOut; ++ inputs->pad_idx = 0; ++ inputs->next = nullptr; ++ ++ result = avfilter_graph_parse_ptr(m_pFilterGraph, filters.c_str(), &inputs, &outputs, NULL); ++ avfilter_inout_free(&outputs); ++ avfilter_inout_free(&inputs); ++ ++ if (result < 0) ++ { ++ CLog::Log(LOGERROR, "CDVDVideoCodecDRMPRIME::FilterOpen - avfilter_graph_parse"); ++ return false; ++ } ++ ++ if ((result = avfilter_graph_config(m_pFilterGraph, nullptr)) < 0) ++ { ++ char err[AV_ERROR_MAX_STRING_SIZE] = {}; ++ av_strerror(result, err, AV_ERROR_MAX_STRING_SIZE); ++ CLog::Log(LOGDEBUG, "CDVDVideoCodecDRMPRIME::FilterOpen - avfilter_graph_config: {} ({})", ++ err, result); ++ return false; ++ } ++ ++ if (test) ++ { ++ FilterClose(); ++ return true; ++ } ++ ++ if (filters.find("deinterlace") != std::string::npos) ++ { ++ m_processInfo.SetVideoDeintMethod(filters); ++ } ++ else ++ { ++ m_processInfo.SetVideoDeintMethod("none"); ++ } ++ ++ if (CServiceBroker::GetLogging().CanLogComponent(LOGVIDEO)) ++ { ++ char* graphDump = avfilter_graph_dump(m_pFilterGraph, nullptr); ++ if (graphDump) ++ { ++ CLog::Log(LOGDEBUG, "CDVDVideoCodecDRMPRIME::FilterOpen - Final filter graph:\n%s", ++ graphDump); ++ av_freep(&graphDump); ++ } ++ } ++ ++ return true; ++} ++ ++void CDVDVideoCodecDRMPRIME::FilterClose() + { +- if (!m_pFilterIn) +- return VC_PICTURE; ++ if (m_pFilterGraph) ++ { ++ CLog::Log(LOGDEBUG, LOGVIDEO, "CDVDVideoCodecDRMPRIME::FilterClose - Freeing filter graph"); ++ avfilter_graph_free(&m_pFilterGraph); ++ ++ // Disposed by above code ++ m_pFilterIn = nullptr; ++ m_pFilterOut = nullptr; ++ } ++} + ++CDVDVideoCodec::VCReturn CDVDVideoCodecDRMPRIME::ProcessFilterIn() ++{ + int ret = av_buffersrc_add_frame(m_pFilterIn, m_pFrame); + if (ret < 0) + { +@@ -547,21 +782,14 @@ CDVDVideoCodec::VCReturn CDVDVideoCodecDRMPRIME::ProcessFilterIn() + + CDVDVideoCodec::VCReturn CDVDVideoCodecDRMPRIME::ProcessFilterOut() + { +- if (!m_pFilterOut) +- return VC_EOF; +- +- int ret = av_buffersink_get_frame(m_pFilterOut, m_pFrame); ++ int ret = av_buffersink_get_frame(m_pFilterOut, m_pFilterFrame); + if (ret == AVERROR(EAGAIN)) + return VC_BUFFER; + else if (ret == AVERROR_EOF) + { +- if (m_codecControlFlags & DVD_CODEC_CTRL_DRAIN) +- { +- CLog::Log(LOGDEBUG, "CDVDVideoCodecDRMPRIME::{} - flush buffers", __FUNCTION__); +- avcodec_flush_buffers(m_pCodecContext); +- SetCodecControl(m_codecControlFlags & ~DVD_CODEC_CTRL_DRAIN); +- } +- return VC_EOF; ++ ret = av_buffersink_get_frame(m_pFilterOut, m_pFilterFrame); ++ if (ret < 0) ++ return VC_BUFFER; + } + else if (ret) + { +@@ -572,9 +800,27 @@ CDVDVideoCodec::VCReturn CDVDVideoCodecDRMPRIME::ProcessFilterOut() + return VC_ERROR; + } + ++ av_frame_unref(m_pFrame); ++ av_frame_move_ref(m_pFrame, m_pFilterFrame); ++ + return VC_PICTURE; + } + ++std::string CDVDVideoCodecDRMPRIME::GetFilterChain(bool interlaced) ++{ ++ // ask codec to do deinterlacing if possible ++ EINTERLACEMETHOD mInt = m_processInfo.GetVideoSettings().m_InterlaceMethod; ++ std::string filterChain; ++ ++ if (!m_processInfo.Supports(mInt)) ++ mInt = m_processInfo.GetFallbackDeintMethod(); ++ ++ if (mInt != VS_INTERLACEMETHOD_NONE && interlaced && !m_deintFilterName.empty()) ++ filterChain += m_deintFilterName; ++ ++ return filterChain; ++} ++ + CDVDVideoCodec::VCReturn CDVDVideoCodecDRMPRIME::GetPicture(VideoPicture* pVideoPicture) + { + if (m_codecControlFlags & DVD_CODEC_CTRL_DRAIN) +@@ -586,57 +832,71 @@ CDVDVideoCodec::VCReturn CDVDVideoCodecDRMPRIME::GetPicture(VideoPicture* pVideo + pVideoPicture->videoBuffer = nullptr; + } + +- auto result = ProcessFilterOut(); +- if (result != VC_PICTURE) ++ if (m_pFilterGraph) + { +- int ret = avcodec_receive_frame(m_pCodecContext, m_pFrame); +- if (ret == AVERROR(EAGAIN)) +- return VC_BUFFER; +- else if (ret == AVERROR_EOF) +- return VC_EOF; +- else if (ret) ++ auto ret = ProcessFilterOut(); ++ if (ret == VC_PICTURE) + { +- char err[AV_ERROR_MAX_STRING_SIZE] = {}; +- av_strerror(ret, err, AV_ERROR_MAX_STRING_SIZE); +- CLog::Log(LOGERROR, "CDVDVideoCodecDRMPRIME::{} - receive frame failed: {} ({})", +- __FUNCTION__, err, ret); +- return VC_ERROR; ++ if (!SetPictureParams(pVideoPicture)) ++ return VC_ERROR; ++ return VC_PICTURE; + } ++ else if (ret != VC_BUFFER) ++ { ++ return ret; ++ } ++ } + +- result = ProcessFilterIn(); +- if (result != VC_PICTURE) +- return result; ++ int ret = avcodec_receive_frame(m_pCodecContext, m_pFrame); ++ if (ret == AVERROR(EAGAIN)) ++ return VC_BUFFER; ++ else if (ret == AVERROR_EOF) ++ return VC_EOF; ++ else if (ret) ++ { ++ char err[AV_ERROR_MAX_STRING_SIZE] = {}; ++ av_strerror(ret, err, AV_ERROR_MAX_STRING_SIZE); ++ CLog::Log(LOGERROR, "CDVDVideoCodecDRMPRIME::{} - receive frame failed: {} ({})", ++ __FUNCTION__, err, ret); ++ return VC_ERROR; + } + +- SetPictureParams(pVideoPicture); ++ if (!m_processInfo.GetVideoInterlaced() && m_pFrame->interlaced_frame) ++ m_processInfo.SetVideoInterlaced(true); + +- if (IsSupportedHwFormat(static_cast(m_pFrame->format))) ++ std::string filterChain = GetFilterChain(m_pFrame->interlaced_frame); ++ if (!filterChain.empty()) + { +- CVideoBufferDRMPRIMEFFmpeg* buffer = +- dynamic_cast(m_videoBufferPool->Get()); +- buffer->SetPictureParams(*pVideoPicture); +- buffer->SetRef(m_pFrame); +- pVideoPicture->videoBuffer = buffer; ++ bool reopenFilter = false; ++ if (m_filters != filterChain) ++ reopenFilter = true; ++ ++ if (m_pFilterGraph && ++ (m_pFilterIn->outputs[0]->w != m_pCodecContext->width || ++ m_pFilterIn->outputs[0]->h != m_pCodecContext->height)) ++ reopenFilter = true; ++ ++ if (reopenFilter) ++ { ++ m_filters = filterChain; ++ if (!FilterOpen(filterChain, false)) ++ FilterClose(); ++ } ++ ++ if (m_pFilterGraph) ++ { ++ if (ProcessFilterIn() != VC_PICTURE) ++ return VC_NONE; ++ } + } +- else if (m_pFrame->opaque) ++ else + { +- CVideoBufferDMA* buffer = static_cast(m_pFrame->opaque); +- buffer->SetPictureParams(*pVideoPicture); +- buffer->Acquire(); +- buffer->SyncEnd(); +- buffer->SetDimensions(m_pFrame->width, m_pFrame->height); +- +- pVideoPicture->videoBuffer = buffer; +- av_frame_unref(m_pFrame); ++ m_filters.clear(); ++ FilterClose(); + } + +- if (!pVideoPicture->videoBuffer) +- { +- CLog::Log(LOGERROR, "CDVDVideoCodecDRMPRIME::{} - videoBuffer:nullptr format:{}", __FUNCTION__, +- av_get_pix_fmt_name(static_cast(m_pFrame->format))); +- av_frame_unref(m_pFrame); ++ if (!SetPictureParams(pVideoPicture)) + return VC_ERROR; +- } + + return VC_PICTURE; + } +diff --git a/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.h b/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.h +index 7112d1b48a..13bec95135 100644 +--- a/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.h ++++ b/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.h +@@ -38,18 +38,25 @@ public: + + protected: + void Drain(); +- void SetPictureParams(VideoPicture* pVideoPicture); ++ bool SetPictureParams(VideoPicture* pVideoPicture); + void UpdateProcessInfo(struct AVCodecContext* avctx, const enum AVPixelFormat fmt); + CDVDVideoCodec::VCReturn ProcessFilterIn(); + CDVDVideoCodec::VCReturn ProcessFilterOut(); + static enum AVPixelFormat GetFormat(struct AVCodecContext* avctx, const enum AVPixelFormat* fmt); + static int GetBuffer(struct AVCodecContext* avctx, AVFrame* frame, int flags); ++ bool FilterOpen(const std::string& filters, bool test); ++ void FilterClose(); ++ void FilterTest(); ++ std::string GetFilterChain(bool interlaced); + + std::string m_name; ++ std::string m_deintFilterName; ++ std::string m_filters; + int m_codecControlFlags = 0; + CDVDStreamInfo m_hints; + AVCodecContext* m_pCodecContext = nullptr; + AVFrame* m_pFrame = nullptr; ++ AVFrame* m_pFilterFrame = nullptr; + AVFilterGraph* m_pFilterGraph = nullptr; + AVFilterContext* m_pFilterIn = nullptr; + AVFilterContext* m_pFilterOut = nullptr; diff --git a/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch index 8a3a76e468..62d7e0f68c 100644 --- a/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch @@ -232,3 +232,456 @@ index 80053d91a301..2c55e1852c3d 100644 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), .y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22), .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Qinglang Miao +Date: Tue, 1 Dec 2020 20:54:57 +0800 +Subject: [PATCH] drm/rockchip: cdn-dp: fix reference leak when + pm_runtime_get_sync fails + +The PM reference count is not expected to be incremented on +return in cdn_dp_clk_enable. + +However, pm_runtime_get_sync will increment the PM reference +count even failed. Forgetting to putting operation will result +in a reference leak here. + +Replace it with pm_runtime_resume_and_get to keep usage +counter balanced. + +Fixes: efe0220fc2d2 ("drm/rockchip: cdn-dp: Fix error handling") +Reported-by: Hulk Robot +Signed-off-by: Qinglang Miao +--- + drivers/gpu/drm/rockchip/cdn-dp-core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c +index a4a45daf93f2..9b4406191470 100644 +--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c ++++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c +@@ -98,7 +98,7 @@ static int cdn_dp_clk_enable(struct cdn_dp_device *dp) + goto err_core_clk; + } + +- ret = pm_runtime_get_sync(dp->dev); ++ ret = pm_runtime_resume_and_get(dp->dev); + if (ret < 0) { + DRM_DEV_ERROR(dp->dev, "cannot get pm runtime %d\n", ret); + goto err_pm_runtime_get; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Qinglang Miao +Date: Tue, 1 Dec 2020 20:54:58 +0800 +Subject: [PATCH] drm/rockchip: vop: fix reference leak when + pm_runtime_get_sync fails + +The PM reference count is not expected to be incremented on +return in functions vop_enable and vop_enable. + +However, pm_runtime_get_sync will increment the PM reference +count even failed. Forgetting to putting operation will result +in a reference leak here. + +Replace it with pm_runtime_resume_and_get to keep usage +counter balanced. + +Fixes: 5e570373c015 ("drm/rockchip: vop: Enable pm domain before vop_initial") +Reported-by: Hulk Robot +Signed-off-by: Qinglang Miao +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index eb663e25ad9e..c6c76e8ab66c 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -602,7 +602,7 @@ static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) + struct vop *vop = to_vop(crtc); + int ret, i; + +- ret = pm_runtime_get_sync(vop->dev); ++ ret = pm_runtime_resume_and_get(vop->dev); + if (ret < 0) { + DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); + return ret; +@@ -1933,7 +1933,7 @@ static int vop_initial(struct vop *vop) + return PTR_ERR(vop->dclk); + } + +- ret = pm_runtime_get_sync(vop->dev); ++ ret = pm_runtime_resume_and_get(vop->dev); + if (ret < 0) { + DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); + return ret; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Qinglang Miao +Date: Tue, 1 Dec 2020 20:54:59 +0800 +Subject: [PATCH] drm/rockchip: lvds: fix reference leak when + pm_runtime_get_sync fails + +The PM reference count is not expected to be incremented on +return in functions rk3288_lvds_poweron and px30_lvds_poweron. + +However, pm_runtime_get_sync will increment the PM reference +count even failed. Forgetting to putting operation will result +in a reference leak here. + +Replace it with pm_runtime_resume_and_get to keep usage +counter balanced. + +Fixes: cca1705c3d89 ("drm/rockchip: lvds: Add PX30 support") +Reported-by: Hulk Robot +Signed-off-by: Qinglang Miao +--- + drivers/gpu/drm/rockchip/rockchip_lvds.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c +index 41edd0a421b2..4d463d50a63a 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_lvds.c ++++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c +@@ -145,7 +145,7 @@ static int rk3288_lvds_poweron(struct rockchip_lvds *lvds) + DRM_DEV_ERROR(lvds->dev, "failed to enable lvds pclk %d\n", ret); + return ret; + } +- ret = pm_runtime_get_sync(lvds->dev); ++ ret = pm_runtime_resume_and_get(lvds->dev); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); + clk_disable(lvds->pclk); +@@ -329,7 +329,7 @@ static int px30_lvds_poweron(struct rockchip_lvds *lvds) + { + int ret; + +- ret = pm_runtime_get_sync(lvds->dev); ++ ret = pm_runtime_resume_and_get(lvds->dev); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); + return ret; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Lukasz Luba +Date: Tue, 5 Jan 2021 16:41:11 +0000 +Subject: [PATCH] drm/panfrost: Use delayed timer as default in devfreq profile + +Devfreq framework supports 2 modes for monitoring devices. +Use delayed timer as default instead of deferrable timer +in order to monitor the GPU status regardless of CPU idle. + +Signed-off-by: Lukasz Luba +Reviewed-by: Steven Price +--- + drivers/gpu/drm/panfrost/panfrost_devfreq.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c b/drivers/gpu/drm/panfrost/panfrost_devfreq.c +index 913eaa6d0bc6..17d5fa6e0b83 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c ++++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c +@@ -76,6 +76,7 @@ static int panfrost_devfreq_get_dev_status(struct device *dev, + } + + static struct devfreq_dev_profile panfrost_devfreq_profile = { ++ .timer = DEVFREQ_TIMER_DELAYED, + .polling_ms = 50, /* ~3 frames */ + .target = panfrost_devfreq_target, + .get_dev_status = panfrost_devfreq_get_dev_status, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Lukasz Luba +Date: Thu, 21 Jan 2021 17:04:45 +0000 +Subject: [PATCH] drm/panfrost: Add governor data with pre-defined thresholds + +The simple_ondemand devfreq governor uses two thresholds to decide about +the frequency change: upthreshold, downdifferential. These two tunable +change the behavior of the governor decision, e.g. how fast to increase +the frequency or how rapidly limit the frequency. This patch adds needed +governor data with thresholds values gathered experimentally in different +workloads. + +Signed-off-by: Lukasz Luba +--- + drivers/gpu/drm/panfrost/panfrost_devfreq.c | 10 +++++++++- + drivers/gpu/drm/panfrost/panfrost_devfreq.h | 2 ++ + 2 files changed, 11 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c b/drivers/gpu/drm/panfrost/panfrost_devfreq.c +index 17d5fa6e0b83..53e0188ce8e8 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c ++++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c +@@ -130,8 +130,16 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev) + panfrost_devfreq_profile.initial_freq = cur_freq; + dev_pm_opp_put(opp); + ++ /* ++ * Setup default thresholds for the simple_ondemand governor. ++ * The values are chosen based on experiments. ++ */ ++ pfdevfreq->gov_data.upthreshold = 45; ++ pfdevfreq->gov_data.downdifferential = 5; ++ + devfreq = devm_devfreq_add_device(dev, &panfrost_devfreq_profile, +- DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL); ++ DEVFREQ_GOV_SIMPLE_ONDEMAND, ++ &pfdevfreq->gov_data); + if (IS_ERR(devfreq)) { + DRM_DEV_ERROR(dev, "Couldn't initialize GPU devfreq\n"); + ret = PTR_ERR(devfreq); +diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.h b/drivers/gpu/drm/panfrost/panfrost_devfreq.h +index db6ea48e21f9..1e2a4de941aa 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.h ++++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.h +@@ -4,6 +4,7 @@ + #ifndef __PANFROST_DEVFREQ_H__ + #define __PANFROST_DEVFREQ_H__ + ++#include + #include + #include + +@@ -17,6 +18,7 @@ struct panfrost_devfreq { + struct devfreq *devfreq; + struct opp_table *regulators_opp_table; + struct thermal_cooling_device *cooling; ++ struct devfreq_simple_ondemand_data gov_data; + bool opp_of_table_added; + + ktime_t busy_time; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Boris Brezillon +Date: Fri, 5 Feb 2021 12:17:55 +0100 +Subject: [PATCH] drm/panfrost: Clear MMU irqs before handling the fault + +When a fault is handled it will unblock the GPU which will continue +executing its shader and might fault almost immediately on a different +page. If we clear interrupts after handling the fault we might miss new +faults, so clear them before. + +Cc: +Fixes: 187d2929206e ("drm/panfrost: Add support for GPU heap allocations") +Signed-off-by: Boris Brezillon +Reviewed-by: Steven Price +--- + drivers/gpu/drm/panfrost/panfrost_mmu.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c +index be8d68fb0e11..e5f7f647430f 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_mmu.c ++++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c +@@ -600,6 +600,8 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) + access_type = (fault_status >> 8) & 0x3; + source_id = (fault_status >> 16); + ++ mmu_write(pfdev, MMU_INT_CLEAR, mask); ++ + /* Page fault only */ + ret = -1; + if ((status & mask) == BIT(i) && (exception_type & 0xF8) == 0xC0) +@@ -623,8 +625,6 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) + access_type, access_type_name(pfdev, fault_status), + source_id); + +- mmu_write(pfdev, MMU_INT_CLEAR, mask); +- + status &= ~mask; + } + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Boris Brezillon +Date: Fri, 5 Feb 2021 12:17:56 +0100 +Subject: [PATCH] drm/panfrost: Don't try to map pages that are already mapped + +We allocate 2MB chunks at a time, so it might appear that a page fault +has already been handled by a previous page fault when we reach +panfrost_mmu_map_fault_addr(). Bail out in that case to avoid mapping the +same area twice. + +Cc: +Fixes: 187d2929206e ("drm/panfrost: Add support for GPU heap allocations") +Signed-off-by: Boris Brezillon +Reviewed-by: Steven Price +--- + drivers/gpu/drm/panfrost/panfrost_mmu.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c +index e5f7f647430f..198686216317 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_mmu.c ++++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c +@@ -495,8 +495,14 @@ static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as, + } + bo->base.pages = pages; + bo->base.pages_use_count = 1; +- } else ++ } else { + pages = bo->base.pages; ++ if (pages[page_offset]) { ++ /* Pages are already mapped, bail out. */ ++ mutex_unlock(&bo->base.pages_lock); ++ goto out; ++ } ++ } + + mapping = bo->base.base.filp->f_mapping; + mapping_set_unevictable(mapping); +@@ -529,6 +535,7 @@ static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as, + + dev_dbg(pfdev->dev, "mapped page fault @ AS%d %llx", as, addr); + ++out: + panfrost_gem_mapping_put(bomapping); + + return 0; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Boris Brezillon +Date: Fri, 5 Feb 2021 12:17:57 +0100 +Subject: [PATCH] drm/panfrost: Stay in the threaded MMU IRQ handler until + we've handled all IRQs + +Doing a hw-irq -> threaded-irq round-trip is counter-productive, stay +in the threaded irq handler as long as we can. + +v2: +* Rework the loop to avoid a goto + +Signed-off-by: Boris Brezillon +Reviewed-by: Steven Price +Reviewed-by: Rob Herring +--- + drivers/gpu/drm/panfrost/panfrost_mmu.c | 26 +++++++++++++------------ + 1 file changed, 14 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c +index 198686216317..5a3d18c05802 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_mmu.c ++++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c +@@ -585,22 +585,20 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) + { + struct panfrost_device *pfdev = data; + u32 status = mmu_read(pfdev, MMU_INT_RAWSTAT); +- int i, ret; ++ int ret; + +- for (i = 0; status; i++) { +- u32 mask = BIT(i) | BIT(i + 16); ++ while (status) { ++ u32 as = ffs(status | (status >> 16)) - 1; ++ u32 mask = BIT(as) | BIT(as + 16); + u64 addr; + u32 fault_status; + u32 exception_type; + u32 access_type; + u32 source_id; + +- if (!(status & mask)) +- continue; +- +- fault_status = mmu_read(pfdev, AS_FAULTSTATUS(i)); +- addr = mmu_read(pfdev, AS_FAULTADDRESS_LO(i)); +- addr |= (u64)mmu_read(pfdev, AS_FAULTADDRESS_HI(i)) << 32; ++ fault_status = mmu_read(pfdev, AS_FAULTSTATUS(as)); ++ addr = mmu_read(pfdev, AS_FAULTADDRESS_LO(as)); ++ addr |= (u64)mmu_read(pfdev, AS_FAULTADDRESS_HI(as)) << 32; + + /* decode the fault status */ + exception_type = fault_status & 0xFF; +@@ -611,8 +609,8 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) + + /* Page fault only */ + ret = -1; +- if ((status & mask) == BIT(i) && (exception_type & 0xF8) == 0xC0) +- ret = panfrost_mmu_map_fault_addr(pfdev, i, addr); ++ if ((status & mask) == BIT(as) && (exception_type & 0xF8) == 0xC0) ++ ret = panfrost_mmu_map_fault_addr(pfdev, as, addr); + + if (ret) + /* terminal fault, print info about the fault */ +@@ -624,7 +622,7 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) + "exception type 0x%X: %s\n" + "access type 0x%X: %s\n" + "source id 0x%X\n", +- i, addr, ++ as, addr, + "TODO", + fault_status, + (fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"), +@@ -633,6 +631,10 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) + source_id); + + status &= ~mask; ++ ++ /* If we received new MMU interrupts, process them before returning. */ ++ if (!status) ++ status = mmu_read(pfdev, MMU_INT_RAWSTAT); + } + + mmu_write(pfdev, MMU_INT_MASK, ~0); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Wed, 27 Jan 2021 19:40:47 +0000 +Subject: [PATCH] drm/lima: add governor data with pre-defined thresholds + +This patch adapts the panfrost pre-defined thresholds change [0] to the +lima driver to improve real-world performance. The upthreshold value has +been set to ramp GPU frequency to max freq faster (compared to panfrost) +to compensate for the lower overall performance of utgard devices. + +[0] https://patchwork.kernel.org/project/dri-devel/patch/20210121170445.19761-1-lukasz.luba@arm.com/ + +Signed-off-by: Christian Hewitt +Reviewed-by: Lukasz Luba +Reviewed-by: Qiang Yu +--- + drivers/gpu/drm/lima/lima_devfreq.c | 10 +++++++++- + drivers/gpu/drm/lima/lima_devfreq.h | 2 ++ + 2 files changed, 11 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/lima/lima_devfreq.c b/drivers/gpu/drm/lima/lima_devfreq.c +index 5686ad4aaf7c..c9854315a0b5 100644 +--- a/drivers/gpu/drm/lima/lima_devfreq.c ++++ b/drivers/gpu/drm/lima/lima_devfreq.c +@@ -163,8 +163,16 @@ int lima_devfreq_init(struct lima_device *ldev) + lima_devfreq_profile.initial_freq = cur_freq; + dev_pm_opp_put(opp); + ++ /* ++ * Setup default thresholds for the simple_ondemand governor. ++ * The values are chosen based on experiments. ++ */ ++ ldevfreq->gov_data.upthreshold = 30; ++ ldevfreq->gov_data.downdifferential = 5; ++ + devfreq = devm_devfreq_add_device(dev, &lima_devfreq_profile, +- DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL); ++ DEVFREQ_GOV_SIMPLE_ONDEMAND, ++ &ldevfreq->gov_data); + if (IS_ERR(devfreq)) { + dev_err(dev, "Couldn't initialize GPU devfreq\n"); + ret = PTR_ERR(devfreq); +diff --git a/drivers/gpu/drm/lima/lima_devfreq.h b/drivers/gpu/drm/lima/lima_devfreq.h +index 2d9b3008ce77..b0c7c736e81a 100644 +--- a/drivers/gpu/drm/lima/lima_devfreq.h ++++ b/drivers/gpu/drm/lima/lima_devfreq.h +@@ -4,6 +4,7 @@ + #ifndef __LIMA_DEVFREQ_H__ + #define __LIMA_DEVFREQ_H__ + ++#include + #include + #include + +@@ -18,6 +19,7 @@ struct lima_devfreq { + struct opp_table *clkname_opp_table; + struct opp_table *regulators_opp_table; + struct thermal_cooling_device *cooling; ++ struct devfreq_simple_ondemand_data gov_data; + + ktime_t busy_time; + ktime_t idle_time; diff --git a/projects/Rockchip/patches/linux/default/linux-1003-RK3328-enable-USB3-for-supported-boards.patch b/projects/Rockchip/patches/linux/default/linux-1003-RK3328-enable-USB3-for-supported-boards.patch deleted file mode 100644 index 3d7702a4c0..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-1003-RK3328-enable-USB3-for-supported-boards.patch +++ /dev/null @@ -1,76 +0,0 @@ -From e7cc7e8e0812ce96035ad1d286d79a37f3ea81d2 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 16 Jan 2021 12:24:58 +0000 -Subject: [PATCH] ARM64: dts: rockchip: RK3328: enable USB3 for supported - boards - -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 21 +++++++++++++++++++ - .../arm64/boot/dts/rockchip/rk3328-rock64.dts | 21 +++++++++++++++++++ - 2 files changed, 42 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -index 37f307cfa4cc..4013f16bb368 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -@@ -352,6 +352,27 @@ &usb_host0_ehci { - status = "okay"; - }; - -+&usbdrd3 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb3phy { -+ status = "okay"; -+}; -+ -+&usb3phy_utmi { -+ status = "okay"; -+}; -+ -+&usb3phy_pipe { -+ status = "okay"; -+}; -+ - &vop { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -index c984662043da..89fde87f7650 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -@@ -384,6 +384,27 @@ &usb_host0_ohci { - status = "okay"; - }; - -+&usbdrd3 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb3phy { -+ status = "okay"; -+}; -+ -+&usb3phy_utmi { -+ status = "okay"; -+}; -+ -+&usb3phy_pipe { -+ status = "okay"; -+}; -+ - &vop { - status = "okay"; - }; diff --git a/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch b/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch new file mode 100644 index 0000000000..35a3c0f8a0 --- /dev/null +++ b/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch @@ -0,0 +1,452 @@ +From e7cc7e8e0812ce96035ad1d286d79a37f3ea81d2 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 16 Jan 2021 12:24:58 +0000 +Subject: [PATCH] ARM64: dts: rockchip: RK3328: enable USB3 for supported + boards + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 21 +++++++++++++++++++ + .../arm64/boot/dts/rockchip/rk3328-rock64.dts | 21 +++++++++++++++++++ + 2 files changed, 42 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +index 37f307cfa4cc..4013f16bb368 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +@@ -352,6 +352,27 @@ &usb_host0_ehci { + status = "okay"; + }; + ++&usbdrd3 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb3phy { ++ status = "okay"; ++}; ++ ++&usb3phy_utmi { ++ status = "okay"; ++}; ++ ++&usb3phy_pipe { ++ status = "okay"; ++}; ++ + &vop { + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +index c984662043da..89fde87f7650 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +@@ -384,6 +384,27 @@ &usb_host0_ohci { + status = "okay"; + }; + ++&usbdrd3 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb3phy { ++ status = "okay"; ++}; ++ ++&usb3phy_utmi { ++ status = "okay"; ++}; ++ ++&usb3phy_pipe { ++ status = "okay"; ++}; ++ + &vop { + status = "okay"; + }; +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 2 Sep 2020 19:52:02 +0200 +Subject: [PATCH] arm64: dts: rockchip: add gpu powerdomain, gpu opp-table and + cooling cell + +Note: since the regulator that supplies the GPU usually also supplies +other SoC components, we have to make sure voltage is never lower then +1050 mV. + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 33 ++++++++++++++++++++++++ + 1 file changed, 33 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index b54ff9055e5f..2fae7fa6b000 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -321,6 +321,10 @@ power: power-controller { + #address-cells = <1>; + #size-cells = <0>; + ++ pd_gpu@RK3328_PD_GPU { ++ reg = ; ++ clocks = <&cru ACLK_GPU>; ++ }; + pd_hevc@RK3328_PD_HEVC { + reg = ; + }; +@@ -546,6 +550,11 @@ map0 { + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; ++ map1 { ++ trip = <&target>; ++ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ contribution = <4096>; ++ }; + }; + }; + +@@ -627,7 +636,31 @@ gpu: gpu@ff300000 { + "ppmmu1"; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "bus", "core"; ++ operating-points-v2 = <&gpu_opp_table>; ++ power-domains = <&power RK3328_PD_GPU>; + resets = <&cru SRST_GPU_A>; ++ #cooling-cells = <2>; ++ }; ++ ++ gpu_opp_table: gpu-opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-200000000 { ++ opp-hz = /bits/ 64 <200000000>; ++ opp-microvolt = <1050000>; ++ }; ++ opp-300000000 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <1050000>; ++ }; ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <1050000>; ++ }; ++ opp-500000000 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <1150000>; ++ }; + }; + + h265e_mmu: iommu@ff330200 { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 2 Sep 2020 21:22:31 +0200 +Subject: [PATCH] arm64: dts: rockchip: add rockchip,disable-mmu-reset for vdec + iommu + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 2fae7fa6b000..3d933d74c2b3 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -731,6 +731,7 @@ rkvdec_mmu: iommu@ff360480 { + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3328_PD_VIDEO>; ++ rockchip,disable-mmu-reset; + }; + + vop: vop@ff370000 { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Mon, 10 Feb 2020 19:22:41 +0100 +Subject: [PATCH] ARM64: dts: rk3328 add sdmmc ext node + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 3d933d74c2b3..bd1e5edfbf95 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -1104,6 +1104,20 @@ usbdrd_dwc3: dwc3@ff600000 { + }; + }; + ++ sdmmc_ext: dwmmc@ff5f0000 { ++ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; ++ reg = <0x0 0xff5f0000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, ++ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; ++ fifo-depth = <0x100>; ++ max-frequency = <150000000>; ++ resets = <&cru SRST_SDMMCEXT>; ++ reset-names = "reset"; ++ status = "disabled"; ++ }; ++ + gic: interrupt-controller@ff811000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Tue, 2 Feb 2021 17:22:21 +0200 +Subject: [PATCH] arm: dts: rk3288 miqi add hdmi sound nodes + +Signed-off-by: Alex Bee +--- + arch/arm/boot/dts/rk3288-miqi.dts | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts +index 713f55e143c6..2420d8e1c66f 100644 +--- a/arch/arm/boot/dts/rk3288-miqi.dts ++++ b/arch/arm/boot/dts/rk3288-miqi.dts +@@ -78,6 +78,21 @@ vcc_sys: vsys-regulator { + regulator-always-on; + regulator-boot-on; + }; ++ ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "rockchip,miqi-codec"; ++ simple-audio-card,mclk-fs = <512>; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s>; ++ }; ++ }; + }; + + &cpu0 { +@@ -284,6 +299,11 @@ &i2c5 { + status = "okay"; + }; + ++&i2s { ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ + &io_domains { + status = "okay"; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 1 Jan 2021 12:11:12 +0200 +Subject: [PATCH] arm64: dts: rockchip: fix RK3399 vdec register witdh + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 418d16b0b648..4d5004c9c778 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1276,7 +1276,7 @@ vpu_mmu: iommu@ff650800 { + + vdec: video-codec@ff660000 { + compatible = "rockchip,rk3399-vdec"; +- reg = <0x0 0xff660000 0x0 0x400>; ++ reg = <0x0 0xff660000 0x0 0x480>; + interrupts = ; + interrupt-names = "vdpu"; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 10 Feb 2021 18:44:56 +0200 +Subject: [PATCH] HACK: drm/gem: suppress warning about missing vm_flags + +Signed-off-by: Alex Bee +--- + drivers/gpu/drm/drm_gem.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c +index 69c2c079d803..65fbffc4cbc7 100644 +--- a/drivers/gpu/drm/drm_gem.c ++++ b/drivers/gpu/drm/drm_gem.c +@@ -1093,7 +1093,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, + drm_gem_object_put(obj); + return ret; + } +- WARN_ON(!(vma->vm_flags & VM_DONTEXPAND)); ++ //WARN_ON(!(vma->vm_flags & VM_DONTEXPAND)); + } else { + if (obj->funcs && obj->funcs->vm_ops) + vma->vm_ops = obj->funcs->vm_ops; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 25 Mar 2018 22:17:06 +0200 +Subject: [PATCH] ASoC: hdmi-codec: fix channel allocation + +--- + sound/soc/codecs/hdmi-codec.c | 113 ++++++++++++++++------------------ + 1 file changed, 52 insertions(+), 61 deletions(-) + +diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c +index 403d4c6a49a8..7505c3eee4c1 100644 +--- a/sound/soc/codecs/hdmi-codec.c ++++ b/sound/soc/codecs/hdmi-codec.c +@@ -195,78 +195,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = { + */ + static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = { + { .ca_id = 0x00, .n_ch = 2, +- .mask = FL | FR}, +- /* 2.1 */ +- { .ca_id = 0x01, .n_ch = 4, +- .mask = FL | FR | LFE}, +- /* Dolby Surround */ ++ .mask = FL | FR }, ++ { .ca_id = 0x03, .n_ch = 4, ++ .mask = FL | FR | LFE | FC }, + { .ca_id = 0x02, .n_ch = 4, + .mask = FL | FR | FC }, +- /* surround51 */ ++ { .ca_id = 0x01, .n_ch = 4, ++ .mask = FL | FR | LFE }, + { .ca_id = 0x0b, .n_ch = 6, +- .mask = FL | FR | LFE | FC | RL | RR}, +- /* surround40 */ +- { .ca_id = 0x08, .n_ch = 6, +- .mask = FL | FR | RL | RR }, +- /* surround41 */ +- { .ca_id = 0x09, .n_ch = 6, +- .mask = FL | FR | LFE | RL | RR }, +- /* surround50 */ ++ .mask = FL | FR | LFE | FC | RL | RR }, + { .ca_id = 0x0a, .n_ch = 6, + .mask = FL | FR | FC | RL | RR }, +- /* 6.1 */ +- { .ca_id = 0x0f, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RL | RR | RC }, +- /* surround71 */ ++ { .ca_id = 0x09, .n_ch = 6, ++ .mask = FL | FR | LFE | RL | RR }, ++ { .ca_id = 0x08, .n_ch = 6, ++ .mask = FL | FR | RL | RR }, ++ { .ca_id = 0x07, .n_ch = 6, ++ .mask = FL | FR | LFE | FC | RC }, ++ { .ca_id = 0x06, .n_ch = 6, ++ .mask = FL | FR | FC | RC }, ++ { .ca_id = 0x05, .n_ch = 6, ++ .mask = FL | FR | LFE | RC }, ++ { .ca_id = 0x04, .n_ch = 6, ++ .mask = FL | FR | RC }, + { .ca_id = 0x13, .n_ch = 8, + .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC }, +- /* others */ +- { .ca_id = 0x03, .n_ch = 8, +- .mask = FL | FR | LFE | FC }, +- { .ca_id = 0x04, .n_ch = 8, +- .mask = FL | FR | RC}, +- { .ca_id = 0x05, .n_ch = 8, +- .mask = FL | FR | LFE | RC }, +- { .ca_id = 0x06, .n_ch = 8, +- .mask = FL | FR | FC | RC }, +- { .ca_id = 0x07, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RC }, +- { .ca_id = 0x0c, .n_ch = 8, +- .mask = FL | FR | RC | RL | RR }, +- { .ca_id = 0x0d, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | RC }, +- { .ca_id = 0x0e, .n_ch = 8, +- .mask = FL | FR | FC | RL | RR | RC }, +- { .ca_id = 0x10, .n_ch = 8, +- .mask = FL | FR | RL | RR | RLC | RRC }, +- { .ca_id = 0x11, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1f, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, + { .ca_id = 0x12, .n_ch = 8, + .mask = FL | FR | FC | RL | RR | RLC | RRC }, +- { .ca_id = 0x14, .n_ch = 8, +- .mask = FL | FR | FLC | FRC }, +- { .ca_id = 0x15, .n_ch = 8, +- .mask = FL | FR | LFE | FLC | FRC }, +- { .ca_id = 0x16, .n_ch = 8, +- .mask = FL | FR | FC | FLC | FRC }, +- { .ca_id = 0x17, .n_ch = 8, +- .mask = FL | FR | LFE | FC | FLC | FRC }, +- { .ca_id = 0x18, .n_ch = 8, +- .mask = FL | FR | RC | FLC | FRC }, +- { .ca_id = 0x19, .n_ch = 8, +- .mask = FL | FR | LFE | RC | FLC | FRC }, +- { .ca_id = 0x1a, .n_ch = 8, +- .mask = FL | FR | RC | FC | FLC | FRC }, +- { .ca_id = 0x1b, .n_ch = 8, +- .mask = FL | FR | LFE | RC | FC | FLC | FRC }, +- { .ca_id = 0x1c, .n_ch = 8, +- .mask = FL | FR | RL | RR | FLC | FRC }, +- { .ca_id = 0x1d, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | FLC | FRC }, + { .ca_id = 0x1e, .n_ch = 8, + .mask = FL | FR | FC | RL | RR | FLC | FRC }, +- { .ca_id = 0x1f, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, ++ { .ca_id = 0x11, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1d, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | FLC | FRC }, ++ { .ca_id = 0x10, .n_ch = 8, ++ .mask = FL | FR | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1c, .n_ch = 8, ++ .mask = FL | FR | RL | RR | FLC | FRC }, ++ { .ca_id = 0x0f, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | RL | RR | RC }, ++ { .ca_id = 0x1b, .n_ch = 8, ++ .mask = FL | FR | LFE | RC | FC | FLC | FRC }, ++ { .ca_id = 0x0e, .n_ch = 8, ++ .mask = FL | FR | FC | RL | RR | RC }, ++ { .ca_id = 0x1a, .n_ch = 8, ++ .mask = FL | FR | RC | FC | FLC | FRC }, ++ { .ca_id = 0x0d, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | RC }, ++ { .ca_id = 0x19, .n_ch = 8, ++ .mask = FL | FR | LFE | RC | FLC | FRC }, ++ { .ca_id = 0x0c, .n_ch = 8, ++ .mask = FL | FR | RC | RL | RR }, ++ { .ca_id = 0x18, .n_ch = 8, ++ .mask = FL | FR | RC | FLC | FRC }, ++ { .ca_id = 0x17, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | FLC | FRC }, ++ { .ca_id = 0x16, .n_ch = 8, ++ .mask = FL | FR | FC | FLC | FRC }, ++ { .ca_id = 0x15, .n_ch = 8, ++ .mask = FL | FR | LFE | FLC | FRC }, ++ { .ca_id = 0x14, .n_ch = 8, ++ .mask = FL | FR | FLC | FRC }, + }; + + struct hdmi_codec_priv { diff --git a/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch b/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch index 0aec360655..67591dddca 100644 --- a/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch +++ b/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch @@ -3085,3 +3085,368 @@ index 315894fc511b..3108d06ef7e0 100644 }, { .mandatory = true, +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 30 Jan 2021 18:16:39 +0100 +Subject: [PATCH] media: rkvdec: add variants support + +rkvdec IP has different versions which among others differ in +the supported decoding formats. +This adds an variant implementation in order support other +than the currently supported RK3399 version. + +Note: Since matching of supported codecs is index-based the +available codec options have been reordered here: from +supported by all versions to not commonly supported. This seems +the better soultion than duplicatiing code for every newly added IP. + +Signed-off-by: Alex Bee +--- + drivers/staging/media/rkvdec/rkvdec.c | 104 ++++++++++++++++++-------- + drivers/staging/media/rkvdec/rkvdec.h | 10 +++ + 2 files changed, 84 insertions(+), 30 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c +index 3108d06ef7e0..18ae1b15d0a4 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.c ++++ b/drivers/staging/media/rkvdec/rkvdec.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -270,21 +271,6 @@ static const u32 rkvdec_vp9_decoded_fmts[] = { + }; + + static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { +- { +- .fourcc = V4L2_PIX_FMT_H264_SLICE, +- .frmsize = { +- .min_width = 48, +- .max_width = 4096, +- .step_width = 16, +- .min_height = 48, +- .max_height = 2304, +- .step_height = 16, +- }, +- .ctrls = &rkvdec_h264_ctrls, +- .ops = &rkvdec_h264_fmt_ops, +- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), +- .decoded_fmts = rkvdec_h264_decoded_fmts, +- }, + { + .fourcc = V4L2_PIX_FMT_HEVC_SLICE, + .frmsize = { +@@ -299,6 +285,23 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + .ops = &rkvdec_hevc_fmt_ops, + .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), + .decoded_fmts = rkvdec_hevc_decoded_fmts, ++ .capability = RKVDEC_CAPABILITY_HEVC, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_H264_SLICE, ++ .frmsize = { ++ .min_width = 48, ++ .max_width = 4096, ++ .step_width = 16, ++ .min_height = 48, ++ .max_height = 2304, ++ .step_height = 16, ++ }, ++ .ctrls = &rkvdec_h264_ctrls, ++ .ops = &rkvdec_h264_fmt_ops, ++ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), ++ .decoded_fmts = rkvdec_h264_decoded_fmts, ++ .capability = RKVDEC_CAPABILITY_H264, + }, + { + .fourcc = V4L2_PIX_FMT_VP9_FRAME, +@@ -314,16 +317,31 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + .ops = &rkvdec_vp9_fmt_ops, + .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), + .decoded_fmts = rkvdec_vp9_decoded_fmts, +- } ++ .capability = RKVDEC_CAPABILITY_VP9, ++ }, + }; + + static const struct rkvdec_coded_fmt_desc * +-rkvdec_find_coded_fmt_desc(u32 fourcc) ++rkvdec_default_coded_fmt_desc(unsigned int capabilities) + { + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { +- if (rkvdec_coded_fmts[i].fourcc == fourcc) ++ if (rkvdec_coded_fmts[i].capability & capabilities) ++ return &rkvdec_coded_fmts[i]; ++ } ++ ++ return NULL; ++} ++ ++static const struct rkvdec_coded_fmt_desc * ++rkvdec_find_coded_fmt_desc(u32 fourcc, unsigned int capabilities) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { ++ if (rkvdec_coded_fmts[i].fourcc == fourcc && ++ (rkvdec_coded_fmts[i].capability & capabilities)) + return &rkvdec_coded_fmts[i]; + } + +@@ -346,7 +364,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) + { + struct v4l2_format *f = &ctx->coded_fmt; + +- ctx->coded_fmt_desc = &rkvdec_coded_fmts[0]; ++ ctx->coded_fmt_desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities); + rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); + + f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; +@@ -373,11 +391,13 @@ static int rkvdec_enum_framesizes(struct file *file, void *priv, + struct v4l2_frmsizeenum *fsize) + { + const struct rkvdec_coded_fmt_desc *fmt; ++ struct rkvdec_dev *rkvdec = video_drvdata(file); + + if (fsize->index != 0) + return -EINVAL; + +- fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format); ++ fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format, ++ rkvdec->capabilities); + if (!fmt) + return -EINVAL; + +@@ -448,10 +468,11 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv, + struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); + const struct rkvdec_coded_fmt_desc *desc; + +- desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat); ++ desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat, ++ ctx->dev->capabilities); + if (!desc) { +- pix_mp->pixelformat = rkvdec_coded_fmts[0].fourcc; +- desc = &rkvdec_coded_fmts[0]; ++ desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities); ++ pix_mp->pixelformat = desc->fourcc; + } + + v4l2_apply_frmsize_constraints(&pix_mp->width, +@@ -538,7 +559,8 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, + if (ret) + return ret; + +- desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat); ++ desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat, ++ ctx->dev->capabilities); + if (!desc) + return -EINVAL; + ctx->coded_fmt_desc = desc; +@@ -586,7 +608,10 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv, + static int rkvdec_enum_output_fmt(struct file *file, void *priv, + struct v4l2_fmtdesc *f) + { +- if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts)) ++ struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); ++ ++ if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts) || ++ !(ctx->dev->capabilities & rkvdec_coded_fmts[f->index].capability)) + return -EINVAL; + + f->pixelformat = rkvdec_coded_fmts[f->index].fourcc; +@@ -1012,14 +1037,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx) + int ret; + + for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) +- nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; ++ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) ++ nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; + + v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls); + + for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { +- ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); +- if (ret) +- goto err_free_handler; ++ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) { ++ ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); ++ if (ret) ++ goto err_free_handler; ++ } + } + + ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); +@@ -1217,8 +1245,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) + } + } + ++static const struct rkvdec_variant rk3399_rkvdec_variant = { ++ .capabilities = RKVDEC_CAPABILITY_H264 | ++ RKVDEC_CAPABILITY_HEVC | ++ RKVDEC_CAPABILITY_VP9 ++}; ++ + static const struct of_device_id of_rkvdec_match[] = { +- { .compatible = "rockchip,rk3399-vdec" }, ++ { ++ .compatible = "rockchip,rk3399-vdec", ++ .data = &rk3399_rkvdec_variant, ++ }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, of_rkvdec_match); +@@ -1231,6 +1268,7 @@ static int rkvdec_probe(struct platform_device *pdev) + { + struct rkvdec_dev *rkvdec; + struct resource *res; ++ const struct rkvdec_variant *variant; + unsigned int i; + int ret, irq; + +@@ -1256,6 +1294,12 @@ static int rkvdec_probe(struct platform_device *pdev) + if (ret) + return ret; + ++ variant = of_device_get_match_data(rkvdec->dev); ++ if (!variant) ++ return -EINVAL; ++ ++ rkvdec->capabilities = variant->capabilities; ++ + /* + * Bump ACLK to max. possible freq. (500 MHz) to improve performance + * When 4k video playback. +diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h +index a801668f5f7b..ff1cfd89a1e0 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.h ++++ b/drivers/staging/media/rkvdec/rkvdec.h +@@ -22,6 +22,10 @@ + #include + #include + ++#define RKVDEC_CAPABILITY_H264 BIT(0) ++#define RKVDEC_CAPABILITY_HEVC BIT(1) ++#define RKVDEC_CAPABILITY_VP9 BIT(2) ++ + struct rkvdec_ctx; + + struct rkvdec_ctrl_desc { +@@ -64,6 +68,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) + base.vb.vb2_buf); + } + ++struct rkvdec_variant { ++ unsigned int capabilities; ++}; ++ + struct rkvdec_coded_fmt_ops { + int (*adjust_fmt)(struct rkvdec_ctx *ctx, + struct v4l2_format *f); +@@ -83,6 +91,7 @@ struct rkvdec_coded_fmt_desc { + const struct rkvdec_coded_fmt_ops *ops; + unsigned int num_decoded_fmts; + const u32 *decoded_fmts; ++ unsigned int capability; + }; + + struct rkvdec_dev { +@@ -96,6 +105,7 @@ struct rkvdec_dev { + struct mutex vdev_lock; /* serializes ioctls */ + struct delayed_work watchdog_work; + bool soft_reset; ++ unsigned int capabilities; + }; + + struct rkvdec_ctx { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 30 Jan 2021 18:21:59 +0100 +Subject: [PATCH] media: rkvdec: add RK3288 variant + +This adds RK3288 variant to rkvdec driver. In this earlier version +of the IP only HEVC decoding is supported. + +Signed-off-by: Alex Bee +--- + drivers/staging/media/rkvdec/rkvdec.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c +index 18ae1b15d0a4..c3b74ac8d979 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.c ++++ b/drivers/staging/media/rkvdec/rkvdec.c +@@ -1251,11 +1251,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { + RKVDEC_CAPABILITY_VP9 + }; + ++static const struct rkvdec_variant rk3288_hevc_variant = { ++ .capabilities = RKVDEC_CAPABILITY_HEVC ++}; ++ + static const struct of_device_id of_rkvdec_match[] = { + { + .compatible = "rockchip,rk3399-vdec", + .data = &rk3399_rkvdec_variant, + }, ++ { ++ .compatible = "rockchip,rk3288-hevc", ++ .data = &rk3288_hevc_variant, ++ }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, of_rkvdec_match); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 30 Jan 2021 18:27:30 +0100 +Subject: [PATCH] ARM: dts: RK3288: add hevc node + +Signed-off-by: Alex Bee +--- + arch/arm/boot/dts/rk3288.dtsi | 19 ++++++++++++++++++- + 1 file changed, 18 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index 746acfac1e92..ba43ee6b91e8 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -1271,6 +1271,23 @@ vpu_mmu: iommu@ff9a0800 { + power-domains = <&power RK3288_PD_VIDEO>; + }; + ++ hevc: hevc@ff9c0000 { ++ compatible = "rockchip,rk3288-hevc"; ++ reg = <0x0 0xff9c0000 0x0 0x400>; ++ interrupts = ; ++ interrupt-names = "irq_dec"; ++ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, <&cru SCLK_HEVC_CABAC>, ++ <&cru SCLK_HEVC_CORE>; ++ clock-names = "axi", "ahb", "cabac", "core"; ++ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, ++ <&cru SCLK_HEVC_CORE>, ++ <&cru SCLK_HEVC_CABAC>; ++ assigned-clock-rates = <400000000>, <100000000>, ++ <300000000>, <300000000>; ++ iommus = <&hevc_mmu>; ++ power-domains = <&power RK3288_PD_HEVC>; ++ }; ++ + hevc_mmu: iommu@ff9c0440 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; +@@ -1279,7 +1296,7 @@ hevc_mmu: iommu@ff9c0440 { + clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +- status = "disabled"; ++ power-domains = <&power RK3288_PD_HEVC>; + }; + + gpu: gpu@ffa30000 { diff --git a/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch b/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch new file mode 100644 index 0000000000..ea86031d48 --- /dev/null +++ b/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch @@ -0,0 +1,1798 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sun, 11 Oct 2020 17:03:12 +0200 +Subject: [PATCH] dt-bindings: media: Add Rockchip IEP binding + +Signed-off-by: Alex Bee +--- + .../bindings/media/rockchip-iep.yaml | 73 +++++++++++++++++++ + 1 file changed, 73 insertions(+) + create mode 100644 Documentation/devicetree/bindings/media/rockchip-iep.yaml + +diff --git a/Documentation/devicetree/bindings/media/rockchip-iep.yaml b/Documentation/devicetree/bindings/media/rockchip-iep.yaml +new file mode 100644 +index 000000000000..a9efcda13fc1 +--- /dev/null ++++ b/Documentation/devicetree/bindings/media/rockchip-iep.yaml +@@ -0,0 +1,73 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/media/rockchip-iep.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Rockchip Image Enhancement Processor (IEP) ++ ++description: ++ Rockchip IEP supports various image enhancement operations for YUV and RGB domains. ++ Deinterlacing, spatial and temporal sampling noise reduction are supported by the ++ YUV block. Gamma adjustment, edge enhancement, detail enhancement are supported in ++ the RGB block. Brightness, Saturation, Contrast, Hue adjustment is supported for ++ both domains. Furthermore it supports converting RGB to YUV / YUV to RGB. ++ ++maintainers: ++ - Heiko Stuebner ++ ++properties: ++ compatible: ++ oneOf: ++ - const: rockchip,rk3228-iep ++ - items: ++ - enum: ++ - rockchip,rk3288-iep ++ - rockchip,rk3328-iep ++ - rockchip,rk3368-iep ++ - rockchip,rk3399-iep ++ - const: rockchip,rk3228-iep ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 2 ++ ++ clock-names: ++ items: ++ - const: axi ++ - const: ahb ++ ++ power-domains: ++ maxItems: 1 ++ ++ iommus: ++ maxItems: 1 ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ iep: iep@20070000 { ++ compatible = "rockchip,rk3228-iep"; ++ reg = <0x20070000 0x800>; ++ interrupts = ; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "axi", "ahb"; ++ iommus = <&iep_mmu>; ++ power-domains = <&power RK3228_PD_VIO>; ++ }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sun, 11 Oct 2020 21:24:10 +0200 +Subject: [PATCH] media: rockchip: Add Rockchip IEP driver + +Signed-off-by: Alex Bee +--- + drivers/media/platform/Kconfig | 14 + + drivers/media/platform/Makefile | 1 + + drivers/media/platform/rockchip/iep/Makefile | 5 + + .../media/platform/rockchip/iep/iep-regs.h | 291 +++++ + drivers/media/platform/rockchip/iep/iep.c | 1089 +++++++++++++++++ + drivers/media/platform/rockchip/iep/iep.h | 112 ++ + 6 files changed, 1512 insertions(+) + create mode 100644 drivers/media/platform/rockchip/iep/Makefile + create mode 100644 drivers/media/platform/rockchip/iep/iep-regs.h + create mode 100644 drivers/media/platform/rockchip/iep/iep.c + create mode 100644 drivers/media/platform/rockchip/iep/iep.h + +diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig +index 7e152bbb4fa6..eee78b20c791 100644 +--- a/drivers/media/platform/Kconfig ++++ b/drivers/media/platform/Kconfig +@@ -462,6 +462,20 @@ config VIDEO_RENESAS_VSP1 + To compile this driver as a module, choose M here: the module + will be called vsp1. + ++config VIDEO_ROCKCHIP_IEP ++ tristate "Rockchip Image Enhancement Processor" ++ depends on VIDEO_DEV && VIDEO_V4L2 ++ depends on ARCH_ROCKCHIP || COMPILE_TEST ++ select VIDEOBUF2_DMA_CONTIG ++ select V4L2_MEM2MEM_DEV ++ help ++ This is a v4l2 driver for Rockchip Image Enhancement Processor (IEP) ++ found in most Rockchip RK3xxx SoCs. ++ Rockchip IEP supports various enhancement operations for RGB and YUV ++ images. The driver currently implements YUV deinterlacing only. ++ To compile this driver as a module, choose M here: the module ++ will be called rockchip-iep ++ + config VIDEO_ROCKCHIP_RGA + tristate "Rockchip Raster 2d Graphic Acceleration Unit" + depends on VIDEO_DEV && VIDEO_V4L2 +diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile +index 62b6cdc8c730..f99a873818d5 100644 +--- a/drivers/media/platform/Makefile ++++ b/drivers/media/platform/Makefile +@@ -52,6 +52,7 @@ obj-$(CONFIG_VIDEO_RENESAS_FDP1) += rcar_fdp1.o + obj-$(CONFIG_VIDEO_RENESAS_JPU) += rcar_jpu.o + obj-$(CONFIG_VIDEO_RENESAS_VSP1) += vsp1/ + ++obj-$(CONFIG_VIDEO_ROCKCHIP_IEP) += rockchip/iep/ + obj-$(CONFIG_VIDEO_ROCKCHIP_RGA) += rockchip/rga/ + + obj-y += omap/ +diff --git a/drivers/media/platform/rockchip/iep/Makefile b/drivers/media/platform/rockchip/iep/Makefile +new file mode 100644 +index 000000000000..5c89b3277469 +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/Makefile +@@ -0,0 +1,5 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++rockchip-iep-objs := iep.o ++ ++obj-$(CONFIG_VIDEO_ROCKCHIP_IEP) += rockchip-iep.o +diff --git a/drivers/media/platform/rockchip/iep/iep-regs.h b/drivers/media/platform/rockchip/iep/iep-regs.h +new file mode 100644 +index 000000000000..a68685ef3604 +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/iep-regs.h +@@ -0,0 +1,291 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Rockchip Image Enhancement Processor (IEP) driver ++ * ++ * Copyright (C) 2020 Alex Bee ++ * ++ */ ++ ++#ifndef __IEP_REGS_H__ ++#define __IEP_REGS_H__ ++ ++/* IEP Registers addresses */ ++#define IEP_CONFIG0 0x000 /* Configuration register0 */ ++#define IEP_VOP_DIRECT_PATH BIT(0) ++#define IEP_DEIN_HIGH_FREQ_SHFT 1 ++#define IEP_DEIN_HIGH_FREQ_MASK (0x7f << IEP_DEIN_HIGH_FREQ_SHFT) ++#define IEP_DEIN_MODE_SHFT 8 ++#define IEP_DEIN_MODE_MASK (7 << IEP_DEIN_MODE_SHFT) ++#define IEP_DEIN_HIGH_FREQ_EN BIT(11) ++#define IEP_DEIN_EDGE_INTPOL_EN BIT(12) ++#define IEP_YUV_DENOISE_EN BIT(13) ++#define IEP_YUV_ENHNC_EN BIT(14) ++#define IEP_DEIN_EDGE_INTPOL_SMTH_EN BIT(15) ++#define IEP_RGB_CLR_ENHNC_EN BIT(16) ++#define IEP_RGB_CNTRST_ENHNC_EN BIT(17) ++#define IEP_RGB_ENHNC_MODE_BYPASS (0 << 18) ++#define IEP_RGB_ENHNC_MODE_DNS BIT(18) ++#define IEP_RGB_ENHNC_MODE_DTL (2 << 18) ++#define IEP_RGB_ENHNC_MODE_EDG (3 << 18) ++#define IEP_RGB_ENHNC_MODE_MASK (3 << 18) ++#define IEP_RGB_CNTRST_ENHNC_DDE_FRST BIT(20) ++#define IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT 21 ++#define IEP_DEIN_EDGE_INTPOL_RADIUS_MASK (3 << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT) ++#define IEP_DEIN_EDGE_INTPOL_SELECT BIT(23) ++ ++#define IEP_CONFIG1 0x004 /* Configuration register1 */ ++#define IEP_SRC_FMT_SHFT 0 ++#define IEP_SRC_FMT_MASK (3 << IEP_SRC_FMT_SHFT) ++#define IEP_SRC_RGB_SWP_SHFT 2 ++#define IEP_SRC_RGB_SWP_MASK (2 << IEP_SRC_RGB_SWP_SHFT) ++#define IEP_SRC_YUV_SWP_SHFT 4 ++#define IEP_SRC_YUV_SWP_MASK (3 << IEP_SRC_YUV_SWP_SHFT) ++#define IEP_DST_FMT_SHFT 8 ++#define IEP_DST_FMT_MASK (3 << IEP_DST_FMT_SHFT) ++#define IEP_DST_RGB_SWP_SHFT 10 ++#define IEP_DST_RGB_SWP_MASK (2 << IEP_DST_RGB_SWP_SHFT) ++#define IEP_DST_YUV_SWP_SHFT 12 ++#define IEP_DST_YUV_SWP_MASK (3 << IEP_DST_YUV_SWP_SHFT) ++#define IEP_DTH_UP_EN BIT(14) ++#define IEP_DTH_DWN_EN BIT(15) ++#define IEP_YUV2RGB_COE_BT601_1 (0 << 16) ++#define IEP_YUV2RGB_COE_BT601_F BIT(16) ++#define IEP_YUV2RGB_COE_BT709_1 (2 << 16) ++#define IEP_YUV2RGB_COE_BT709_F (3 << 16) ++#define IEP_YUV2RGB_COE_MASK (3 << 16) ++#define IEP_RGB2YUV_COE_BT601_1 (0 << 18) ++#define IEP_RGB2YUV_COE_BT601_F BIT(18) ++#define IEP_RGB2YUV_COE_BT709_1 (2 << 18) ++#define IEP_RGB2YUV_COE_BT709_F (3 << 18) ++#define IEP_RGB2YUV_COE_MASK (3 << 18) ++#define IEP_YUV2RGB_EN BIT(20) ++#define IEP_RGB2YUV_EN BIT(21) ++#define IEP_YUV2RGB_CLIP_EN BIT(22) ++#define IEP_RGB2YUV_CLIP_EN BIT(23) ++#define IEP_GLB_ALPHA_SHFT 24 ++#define IEP_GLB_ALPHA_MASK (0x7f << IEP_GLB_ALPHA_SHFT) ++ ++#define IEP_STATUS 0x008 /* Status register */ ++#define IEP_STATUS_YUV_DNS BIT(0) ++#define IEP_STATUS_SCL BIT(1) ++#define IEP_STATUS_DIL BIT(2) ++#define IEP_STATUS_DDE BIT(3) ++#define IEP_STATUS_DMA_WR_YUV BIT(4) ++#define IEP_STATUS_DMA_RE_YUV BIT(5) ++#define IEP_STATUS_DMA_WR_RGB BIT(6) ++#define IEP_STATUS_DMA_RE_RGB BIT(7) ++#define IEP_STATUS_VOP_DIRECT_PATH BIT(8) ++#define IEP_STATUS_DMA_IA_WR_YUV BIT(16) ++#define IEP_STATUS_DMA_IA_RE_YUV BIT(17) ++#define IEP_STATUS_DMA_IA_WR_RGB BIT(18) ++#define IEP_STATUS_DMA_IA_RE_RGB BIT(19) ++ ++#define IEP_INT 0x00c /* Interrupt register*/ ++#define IEP_INT_FRAME_DONE BIT(0) /* Frame process done interrupt */ ++#define IEP_INT_FRAME_DONE_EN BIT(8) /* Frame process done interrupt enable */ ++#define IEP_INT_FRAME_DONE_CLR BIT(16) /* Frame process done interrupt clear */ ++ ++#define IEP_FRM_START 0x010 /* Frame start */ ++#define IEP_SRST 0x014 /* Soft reset */ ++#define IEP_CONFIG_DONE 0x018 /* Configuration done */ ++#define IEP_FRM_CNT 0x01c /* Frame counter */ ++ ++#define IEP_VIR_IMG_WIDTH 0x020 /* Image virtual width */ ++#define IEP_IMG_SCL_FCT 0x024 /* Scaling factor */ ++#define IEP_SRC_IMG_SIZE 0x028 /* src image width/height */ ++#define IEP_DST_IMG_SIZE 0x02c /* dst image width/height */ ++#define IEP_DST_IMG_WIDTH_TILE0 0x030 /* dst image tile0 width */ ++#define IEP_DST_IMG_WIDTH_TILE1 0x034 /* dst image tile1 width */ ++#define IEP_DST_IMG_WIDTH_TILE2 0x038 /* dst image tile2 width */ ++#define IEP_DST_IMG_WIDTH_TILE3 0x03c /* dst image tile3 width */ ++ ++#define IEP_ENH_YUV_CNFG_0 0x040 /* Brightness, contrast, saturation adjustment */ ++#define IEP_YUV_BRIGHTNESS_SHFT 0 ++#define IEP_YUV_BRIGHTNESS_MASK (0x3f << IEP_YUV_BRIGHTNESS_SHFT) ++#define IEP_YUV_CONTRAST_SHFT 8 ++#define IEP_YUV_CONTRAST_MASK (0xff << IEP_YUV_CONTRAST_SHFT) ++#define IEP_YUV_SATURATION_SHFT 16 ++#define IEP_YUV_SATURATION_MASK (0x1ff << IEP_YUV_SATURATION_SHFT) ++ ++#define IEP_ENH_YUV_CNFG_1 0x044 /* Hue configuration */ ++#define IEP_YUV_COS_HUE_SHFT 0 ++#define IEP_YUV_COS_HUE_MASK (0xff << IEP_YUV_COS_HUE_SHFT) ++#define IEP_YUV_SIN_HUE_SHFT 8 ++#define IEP_YUV_SIN_HUE_MASK (0xff << IEP_YUV_SIN_HUE_SHFT) ++ ++#define IEP_ENH_YUV_CNFG_2 0x048 /* Color bar configuration */ ++#define IEP_YUV_COLOR_BAR_Y_SHFT 0 ++#define IEP_YUV_COLOR_BAR_Y_MASK (0xff << IEP_YUV_COLOR_BAR_Y_SHFT) ++#define IEP_YUV_COLOR_BAR_U_SHFT 8 ++#define IEP_YUV_COLOR_BAR_U_MASK (0xff << IEP_YUV_COLOR_BAR_U_SHFT) ++#define IEP_YUV_COLOR_BAR_V_SHFT 16 ++#define IEP_YUV_COLOR_BAR_V_MASK (0xff << IEP_YUV_COLOR_BAR_V_SHFT) ++#define IEP_YUV_VIDEO_MODE_SHFT 24 ++#define IEP_YUV_VIDEO_MODE_MASK (3 << IEP_YUV_VIDEO_MODE_SHFT) ++ ++#define IEP_ENH_RGB_CNFG 0x04c /* RGB enhancement configuration */ ++#define IEP_ENH_RGB_C_COE 0x050 /* RGB color enhancement coefficient */ ++ ++#define IEP_RAW_CONFIG0 0x058 /* Raw configuration register0 */ ++#define IEP_RAW_CONFIG1 0x05c /* Raw configuration register1 */ ++#define IEP_RAW_VIR_IMG_WIDTH 0x060 /* Raw image virtual width */ ++#define IEP_RAW_IMG_SCL_FCT 0x064 /* Raw scaling factor */ ++#define IEP_RAW_SRC_IMG_SIZE 0x068 /* Raw src image width/height */ ++#define IEP_RAW_DST_IMG_SIZE 0x06c /* Raw src image width/height */ ++#define IEP_RAW_ENH_YUV_CNFG_0 0x070 /* Raw brightness,contrast,saturation adjustment */ ++#define IEP_RAW_ENH_YUV_CNFG_1 0x074 /* Raw hue configuration */ ++#define IEP_RAW_ENH_YUV_CNFG_2 0x078 /* Raw color bar configuration */ ++#define IEP_RAW_ENH_RGB_CNFG 0x07c /* Raw RGB enhancement configuration */ ++ ++#define IEP_SRC_ADDR_Y_RGB 0x080 /* Start addr. of src image 0 (Y/RGB) */ ++#define IEP_SRC_ADDR_CBCR 0x084 /* Start addr. of src image 0 (Cb/Cr) */ ++#define IEP_SRC_ADDR_CR 0x088 /* Start addr. of src image 0 (Cr) */ ++#define IEP_SRC_ADDR_Y1 0x08c /* Start addr. of src image 1 (Y) */ ++#define IEP_SRC_ADDR_CBCR1 0x090 /* Start addr. of src image 1 (Cb/Cr) */ ++#define IEP_SRC_ADDR_CR1 0x094 /* Start addr. of src image 1 (Cr) */ ++#define IEP_SRC_ADDR_Y_ITEMP 0x098 /* Start addr. of src image(Y int part) */ ++#define IEP_SRC_ADDR_CBCR_ITEMP 0x09c /* Start addr. of src image(CBCR int part) */ ++#define IEP_SRC_ADDR_CR_ITEMP 0x0a0 /* Start addr. of src image(CR int part) */ ++#define IEP_SRC_ADDR_Y_FTEMP 0x0a4 /* Start addr. of src image(Y frac part) */ ++#define IEP_SRC_ADDR_CBCR_FTEMP 0x0a8 /* Start addr. of src image(CBCR frac part) */ ++#define IEP_SRC_ADDR_CR_FTEMP 0x0ac /* Start addr. of src image(CR frac part) */ ++ ++#define IEP_DST_ADDR_Y_RGB 0x0b0 /* Start addr. of dst image 0 (Y/RGB) */ ++#define IEP_DST_ADDR_CBCR 0x0b4 /* Start addr. of dst image 0 (Cb/Cr) */ ++#define IEP_DST_ADDR_CR 0x0b8 /* Start addr. of dst image 0 (Cr) */ ++#define IEP_DST_ADDR_Y1 0x0bc /* Start addr. of dst image 1 (Y) */ ++#define IEP_DST_ADDR_CBCR1 0x0c0 /* Start addr. of dst image 1 (Cb/Cr) */ ++#define IEP_DST_ADDR_CR1 0x0c4 /* Start addr. of dst image 1 (Cr) */ ++#define IEP_DST_ADDR_Y_ITEMP 0x0c8 /* Start addr. of dst image(Y int part) */ ++#define IEP_DST_ADDR_CBCR_ITEMP 0x0cc /* Start addr. of dst image(CBCR int part)*/ ++#define IEP_DST_ADDR_CR_ITEMP 0x0d0 /* Start addr. of dst image(CR int part) */ ++#define IEP_DST_ADDR_Y_FTEMP 0x0d4 /* Start addr. of dst image(Y frac part) */ ++#define IEP_DST_ADDR_CBCR_FTEMP 0x0d8 /* Start addr. of dst image(CBCR frac part) */ ++#define IEP_DST_ADDR_CR_FTEMP 0x0dc /* Start addr. of dst image(CR frac part)*/ ++ ++#define IEP_DEIN_MTN_TAB0 0x0e0 /* Deinterlace motion table0 */ ++#define IEP_DEIN_MTN_TAB1 0x0e4 /* Deinterlace motion table1 */ ++#define IEP_DEIN_MTN_TAB2 0x0e8 /* Deinterlace motion table2 */ ++#define IEP_DEIN_MTN_TAB3 0x0ec /* Deinterlace motion table3 */ ++#define IEP_DEIN_MTN_TAB4 0x0f0 /* Deinterlace motion table4 */ ++#define IEP_DEIN_MTN_TAB5 0x0f4 /* Deinterlace motion table5 */ ++#define IEP_DEIN_MTN_TAB6 0x0f8 /* Deinterlace motion table6 */ ++#define IEP_DEIN_MTN_TAB7 0x0fc /* Deinterlace motion table7 */ ++ ++#define IEP_ENH_CG_TAB 0x100 /* Contrast and gamma enhancement table */ ++#define IEP_ENH_DDE_COE0 0x400 /* Denoise,detail and edge enhancement coefficient */ ++#define IEP_ENH_DDE_COE1 0x500 /* Denoise,detail and edge enhancement coefficient1 */ ++ ++#define IEP_INT_MASK (IEP_INT_FRAME_DONE) ++ ++/* IEP colorformats */ ++#define IEP_COLOR_FMT_XRGB 0U ++#define IEP_COLOR_FMT_RGB565 1U ++#define IEP_COLOR_FMT_YUV422 2U ++#define IEP_COLOR_FMT_YUV420 3U ++ ++/* IEP YUV color swaps */ ++#define IEP_YUV_SWP_SP_UV 0U ++#define IEP_YUV_SWP_SP_VU 1U ++#define IEP_YUV_SWP_P 2U ++ ++/* IEP XRGB color swaps */ ++#define XRGB_SWP_XRGB 0U ++#define XRGB_SWP_XBGR 1U ++#define XRGB_SWP_BGRX 2U ++ ++/* IEP RGB565 color swaps */ ++#define RGB565_SWP_RGB 0U ++#define RGB565_SWP_BGR 1U ++ ++#define FMT_IS_YUV(fmt) (fmt == IEP_COLOR_FMT_XRGB || fmt == IEP_COLOR_FMT_RGB565 ? 0 : 1) ++ ++#define IEP_IMG_SIZE(w, h) (((w - 1) & 0x1fff) << 0 | \ ++ ((h - 1) & 0x1fff) << 16) ++ ++#define IEP_VIR_WIDTH(src_w, dst_w) (((src_w / 4) & 0x1fff) << 0 | \ ++ ((dst_w / 4) & 0x1fff) << 16) ++ ++#define IEP_Y_STRIDE(w, h) (w * h) ++#define IEP_UV_STRIDE(w, h, fac) (w * h + w * h / fac) ++ ++#define IEP_SRC_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_MASK : IEP_SRC_RGB_SWP_MASK) ++#define IEP_DST_FMT_SWP_MASK(f) (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_MASK : IEP_DST_RGB_SWP_MASK) ++ ++#define IEP_SRC_FMT(f, swp) (f << IEP_SRC_FMT_SHFT | \ ++ (swp << (FMT_IS_YUV(f) ? IEP_SRC_YUV_SWP_SHFT : IEP_SRC_RGB_SWP_SHFT))) ++#define IEP_DST_FMT(f, swp) (f << IEP_DST_FMT_SHFT | \ ++ (swp << (FMT_IS_YUV(f) ? IEP_DST_YUV_SWP_SHFT : IEP_DST_RGB_SWP_SHFT))) ++ ++/* IEP DEINTERLACE MODES */ ++#define IEP_DEIN_MODE_YUV 0U ++#define IEP_DEIN_MODE_I4O2 1U ++#define IEP_DEIN_MODE_I4O1B 2U ++#define IEP_DEIN_MODE_I4O1T 3U ++#define IEP_DEIN_MODE_I2O1B 4U ++#define IEP_DEIN_MODE_I2O1T 5U ++#define IEP_DEIN_MODE_BYPASS 6U ++ ++#define IEP_DEIN_IN_FIELDS_2 2U ++#define IEP_DEIN_IN_FIELDS_4 4U ++ ++#define IEP_DEIN_OUT_FRAMES_1 1U ++#define IEP_DEIN_OUT_FRAMES_2 2U ++ ++/* values taken from BSP driver */ ++static const u32 default_dein_motion_tbl[][2] = { ++ { IEP_DEIN_MTN_TAB0, 0x40404040 }, ++ { IEP_DEIN_MTN_TAB1, 0x3c3e3f3f }, ++ { IEP_DEIN_MTN_TAB2, 0x3336393b }, ++ { IEP_DEIN_MTN_TAB3, 0x272a2d31 }, ++ { IEP_DEIN_MTN_TAB4, 0x181c2023 }, ++ { IEP_DEIN_MTN_TAB5, 0x0c0e1215 }, ++ { IEP_DEIN_MTN_TAB6, 0x03040609 }, ++ { IEP_DEIN_MTN_TAB7, 0x00000001 }, ++ ++}; ++ ++#define IEP_DEIN_IN_IMG0_Y(bff) (bff ? IEP_SRC_ADDR_Y_RGB : IEP_SRC_ADDR_Y1) ++#define IEP_DEIN_IN_IMG0_CBCR(bff) (bff ? IEP_SRC_ADDR_CBCR : IEP_SRC_ADDR_CBCR1) ++#define IEP_DEIN_IN_IMG0_CR(bff) (bff ? IEP_SRC_ADDR_CR : IEP_SRC_ADDR_CR1) ++#define IEP_DEIN_IN_IMG1_Y(bff) (IEP_DEIN_IN_IMG0_Y(!bff)) ++#define IEP_DEIN_IN_IMG1_CBCR(bff) (IEP_DEIN_IN_IMG0_CBCR(!bff)) ++#define IEP_DEIN_IN_IMG1_CR(bff) (IEP_DEIN_IN_IMG0_CR(!bff)) ++ ++#define IEP_DEIN_OUT_IMG0_Y(bff) (bff ? IEP_DST_ADDR_Y1 : IEP_DST_ADDR_Y_RGB) ++#define IEP_DEIN_OUT_IMG0_CBCR(bff) (bff ? IEP_DST_ADDR_CBCR1 : IEP_DST_ADDR_CBCR) ++#define IEP_DEIN_OUT_IMG0_CR(bff) (bff ? IEP_DST_ADDR_CR1 : IEP_DST_ADDR_CR) ++#define IEP_DEIN_OUT_IMG1_Y(bff) (IEP_DEIN_OUT_IMG0_Y(!bff)) ++#define IEP_DEIN_OUT_IMG1_CBCR(bff) (IEP_DEIN_OUT_IMG0_CBCR(!bff)) ++#define IEP_DEIN_OUT_IMG1_CR(bff) (IEP_DEIN_OUT_IMG0_CR(!bff)) ++ ++#define IEP_DEIN_MODE(m) (m << IEP_DEIN_MODE_SHFT) ++ ++#define IEP_DEIN_IN_MODE_FIELDS(m) ((m == IEP_DEIN_MODE_I4O1T || m == IEP_DEIN_MODE_I4O1B \ ++ || m == IEP_DEIN_MODE_I4O2) \ ++ ? IEP_DEIN_IN_FIELDS_4 : IEP_DEIN_IN_FIELDS_2) ++ ++#define IEP_DEIN_OUT_MODE_FRAMES(m) (m == IEP_DEIN_MODE_I4O2 \ ++ ? IEP_DEIN_OUT_FRAMES_2 : IEP_DEIN_OUT_FRAMES_1) ++ ++#define IEP_DEIN_OUT_MODE_1FRM_TOP_FIELD(m) (m == IEP_DEIN_MODE_I4O1T || IEP_DEIN_MODE_I2O1T \ ++ ? 1 : 0) ++ ++#define IEP_DEIN_EDGE_INTPOL_RADIUS(r) (r << IEP_DEIN_EDGE_INTPOL_RADIUS_SHFT) ++ ++#define IEP_DEIN_HIGH_FREQ(f) (f << IEP_DEIN_HIGH_FREQ_SHFT) ++ ++/* YUV Enhance video modes */ ++#define VIDEO_MODE_BLACK_SCREEN 0U ++#define VIDEO_MODE_BLUE_SCREEN 1U ++#define VIDEO_MODE_COLOR_BARS 2U ++#define VIDEO_MODE_NORMAL_VIDEO 3U ++ ++#define YUV_VIDEO_MODE(m) ((m << IEP_YUV_VIDEO_MODE_SHFT) & IEP_YUV_VIDEO_MODE_MASK) ++#define YUV_BRIGHTNESS(v) ((v << IEP_YUV_BRIGHTNESS_SHFT) & IEP_YUV_BRIGHTNESS_MASK) ++#define YUV_CONTRAST(v) ((v << IEP_YUV_CONTRAST_SHFT) & IEP_YUV_CONTRAST_MASK) ++#define YUV_SATURATION(v) ((v << IEP_YUV_SATURATION_SHFT) & IEP_YUV_SATURATION_MASK) ++#define YUV_COS_HUE(v) ((v << IEP_YUV_COS_HUE_SHFT) & IEP_YUV_COS_HUE_MASK) ++#define YUV_SIN_HUE(v) ((v << IEP_YUV_SIN_HUE_SHFT) & IEP_YUV_SIN_HUE_MASK) ++ ++#endif +diff --git a/drivers/media/platform/rockchip/iep/iep.c b/drivers/media/platform/rockchip/iep/iep.c +new file mode 100644 +index 000000000000..f4b9320733be +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/iep.c +@@ -0,0 +1,1089 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Rockchip Image Enhancement Processor (IEP) driver ++ * ++ * Copyright (C) 2020 Alex Bee ++ * ++ * Based on Allwinner sun8i deinterlacer with scaler driver ++ * Copyright (C) 2019 Jernej Skrabec ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "iep-regs.h" ++#include "iep.h" ++ ++static struct iep_fmt formats[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_NV12, ++ .color_swap = IEP_YUV_SWP_SP_UV, ++ .hw_format = IEP_COLOR_FMT_YUV420, ++ .depth = 12, ++ .uv_factor = 4, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_NV21, ++ .color_swap = IEP_YUV_SWP_SP_VU, ++ .hw_format = IEP_COLOR_FMT_YUV420, ++ .depth = 12, ++ .uv_factor = 4, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_NV16, ++ .color_swap = IEP_YUV_SWP_SP_UV, ++ .hw_format = IEP_COLOR_FMT_YUV422, ++ .depth = 16, ++ .uv_factor = 2, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_NV61, ++ .color_swap = IEP_YUV_SWP_SP_VU, ++ .hw_format = IEP_COLOR_FMT_YUV422, ++ .depth = 16, ++ .uv_factor = 2, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUV420, ++ .color_swap = IEP_YUV_SWP_P, ++ .hw_format = IEP_COLOR_FMT_YUV420, ++ .depth = 12, ++ .uv_factor = 4, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_YUV422P, ++ .color_swap = IEP_YUV_SWP_P, ++ .hw_format = IEP_COLOR_FMT_YUV422, ++ .depth = 16, ++ .uv_factor = 2, ++ }, ++}; ++ ++static struct iep_fmt *iep_fmt_find(struct v4l2_pix_format *pix_fmt) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(formats); i++) { ++ if (formats[i].fourcc == pix_fmt->pixelformat) ++ return &formats[i]; ++ } ++ ++ return NULL; ++} ++ ++static bool iep_check_pix_format(u32 pixelformat) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(formats); i++) ++ if (formats[i].fourcc == pixelformat) ++ return true; ++ ++ return false; ++} ++ ++static struct vb2_v4l2_buffer *iep_m2m_next_dst_buf(struct iep_ctx *ctx) ++{ ++ struct vb2_v4l2_buffer *dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); ++ ++ /* application has set a dst sequence: take it as start point */ ++ if (ctx->dst_sequence == 0 && dst_buf->sequence > 0) ++ ctx->dst_sequence = dst_buf->sequence; ++ ++ dst_buf->sequence = ctx->dst_sequence++; ++ ++ return dst_buf; ++} ++ ++static void iep_m2m_dst_bufs_done(struct iep_ctx *ctx, enum vb2_buffer_state state) ++{ ++ if (ctx->dst0_buf) { ++ v4l2_m2m_buf_done(ctx->dst0_buf, state); ++ ctx->dst_buffs_done++; ++ ctx->dst0_buf = NULL; ++ } ++ ++ if (ctx->dst1_buf) { ++ v4l2_m2m_buf_done(ctx->dst1_buf, state); ++ ctx->dst_buffs_done++; ++ ctx->dst1_buf = NULL; ++ } ++} ++ ++static void iep_setup_formats(struct iep_ctx *ctx) ++{ ++ /* setup src dimensions */ ++ iep_write(ctx->iep, IEP_SRC_IMG_SIZE, ++ IEP_IMG_SIZE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height)); ++ ++ /* setup dst dimensions */ ++ iep_write(ctx->iep, IEP_DST_IMG_SIZE, ++ IEP_IMG_SIZE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height)); ++ ++ /* setup virtual width */ ++ iep_write(ctx->iep, IEP_VIR_IMG_WIDTH, ++ IEP_VIR_WIDTH(ctx->src_fmt.pix.width, ctx->dst_fmt.pix.width)); ++ ++ /* setup src format */ ++ iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1, ++ IEP_SRC_FMT_MASK | IEP_SRC_FMT_SWP_MASK(ctx->src_fmt.hw_fmt->hw_format), ++ IEP_SRC_FMT(ctx->src_fmt.hw_fmt->hw_format, ++ ctx->src_fmt.hw_fmt->color_swap)); ++ /* setup dst format */ ++ iep_shadow_mod(ctx->iep, IEP_CONFIG1, IEP_RAW_CONFIG1, ++ IEP_DST_FMT_MASK | IEP_DST_FMT_SWP_MASK(ctx->dst_fmt.hw_fmt->hw_format), ++ IEP_DST_FMT(ctx->dst_fmt.hw_fmt->hw_format, ++ ctx->dst_fmt.hw_fmt->color_swap)); ++ ++ ctx->fmt_changed = false; ++} ++ ++static void iep_dein_init(struct rockchip_iep *iep) ++{ ++ unsigned int i; ++ ++ /* values taken from BSP driver */ ++ iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0, ++ (IEP_DEIN_EDGE_INTPOL_SMTH_EN | ++ IEP_DEIN_EDGE_INTPOL_RADIUS_MASK | ++ IEP_DEIN_HIGH_FREQ_EN | ++ IEP_DEIN_HIGH_FREQ_MASK), ++ (IEP_DEIN_EDGE_INTPOL_SMTH_EN | ++ IEP_DEIN_EDGE_INTPOL_RADIUS(3) | ++ IEP_DEIN_HIGH_FREQ_EN | ++ IEP_DEIN_HIGH_FREQ(64))); ++ ++ for (i = 0; i < ARRAY_SIZE(default_dein_motion_tbl); i++) ++ iep_write(iep, default_dein_motion_tbl[i][0], ++ default_dein_motion_tbl[i][1]); ++} ++ ++static void iep_init(struct rockchip_iep *iep) ++{ ++ iep_write(iep, IEP_CONFIG0, ++ IEP_DEIN_MODE(IEP_DEIN_MODE_BYPASS) // | ++ //IEP_YUV_ENHNC_EN ++ ); ++ ++ /* TODO: B/S/C/H works ++ * only in 1-frame-out modes ++ iep_write(iep, IEP_ENH_YUV_CNFG_0, ++ YUV_BRIGHTNESS(0) | ++ YUV_CONTRAST(128) | ++ YUV_SATURATION(128)); ++ ++ iep_write(iep, IEP_ENH_YUV_CNFG_1, ++ YUV_COS_HUE(255) | ++ YUV_SIN_HUE(255)); ++ ++ iep_write(iep, IEP_ENH_YUV_CNFG_2, ++ YUV_VIDEO_MODE(VIDEO_MODE_NORMAL_VIDEO)); ++ ++ */ ++ ++ /* reset frame counter */ ++ iep_write(iep, IEP_FRM_CNT, 0); ++} ++ ++static void iep_device_run(void *priv) ++{ ++ struct iep_ctx *ctx = priv; ++ struct rockchip_iep *iep = ctx->iep; ++ struct vb2_v4l2_buffer *src, *dst; ++ unsigned int dein_mode; ++ dma_addr_t addr; ++ ++ if (ctx->fmt_changed) ++ iep_setup_formats(ctx); ++ ++ if (ctx->prev_src_buf) ++ dein_mode = IEP_DEIN_MODE_I4O2; ++ else ++ dein_mode = ctx->field_bff ? IEP_DEIN_MODE_I2O1B : IEP_DEIN_MODE_I2O1T; ++ ++ iep_shadow_mod(iep, IEP_CONFIG0, IEP_RAW_CONFIG0, ++ IEP_DEIN_MODE_MASK, IEP_DEIN_MODE(dein_mode)); ++ ++ /* sync RAW_xxx registers with actual used */ ++ iep_write(iep, IEP_CONFIG_DONE, 1); ++ ++ /* setup src buff(s)/addresses */ ++ src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); ++ addr = vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG0_Y(ctx->field_bff), addr); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG0_CBCR(ctx->field_bff), ++ addr + ctx->src_fmt.y_stride); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG0_CR(ctx->field_bff), ++ addr + ctx->src_fmt.uv_stride); ++ ++ if (IEP_DEIN_IN_MODE_FIELDS(dein_mode) == IEP_DEIN_IN_FIELDS_4) ++ addr = vb2_dma_contig_plane_dma_addr(&ctx->prev_src_buf->vb2_buf, 0); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG1_Y(ctx->field_bff), addr); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG1_CBCR(ctx->field_bff), ++ addr + ctx->src_fmt.y_stride); ++ ++ iep_write(iep, IEP_DEIN_IN_IMG1_CR(ctx->field_bff), ++ addr + ctx->src_fmt.uv_stride); ++ ++ /* setup dst buff(s)/addresses */ ++ dst = iep_m2m_next_dst_buf(ctx); ++ addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0); ++ ++ if (IEP_DEIN_OUT_MODE_FRAMES(dein_mode) == IEP_DEIN_OUT_FRAMES_2) { ++ v4l2_m2m_buf_copy_metadata(ctx->prev_src_buf, dst, true); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG0_Y(ctx->field_bff), addr); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG0_CBCR(ctx->field_bff), ++ addr + ctx->dst_fmt.y_stride); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG0_CR(ctx->field_bff), ++ addr + ctx->dst_fmt.uv_stride); ++ ++ ctx->dst0_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); ++ ++ dst = iep_m2m_next_dst_buf(ctx); ++ addr = vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0); ++ } ++ ++ v4l2_m2m_buf_copy_metadata(src, dst, true); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG1_Y(ctx->field_bff), addr); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG1_CBCR(ctx->field_bff), ++ addr + ctx->dst_fmt.y_stride); ++ ++ iep_write(iep, IEP_DEIN_OUT_IMG1_CR(ctx->field_bff), ++ addr + ctx->dst_fmt.uv_stride); ++ ++ ctx->dst1_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); ++ ++ iep_mod(ctx->iep, IEP_INT, IEP_INT_FRAME_DONE_EN, ++ IEP_INT_FRAME_DONE_EN); ++ ++ /* start HW */ ++ iep_write(iep, IEP_FRM_START, 1); ++} ++ ++static int iep_job_ready(void *priv) ++{ ++ struct iep_ctx *ctx = priv; ++ ++ return v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) >= 2 && ++ v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) >= 1; ++} ++ ++static void iep_job_abort(void *priv) ++{ ++ struct iep_ctx *ctx = priv; ++ ++ /* Will cancel the transaction in the next interrupt handler */ ++ ctx->job_abort = true; ++} ++ ++static const struct v4l2_m2m_ops iep_m2m_ops = { ++ .device_run = iep_device_run, ++ .job_ready = iep_job_ready, ++ .job_abort = iep_job_abort, ++}; ++ ++static int iep_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers, ++ unsigned int *nplanes, unsigned int sizes[], ++ struct device *alloc_devs[]) ++{ ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ struct v4l2_pix_format *pix_fmt; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ pix_fmt = &ctx->src_fmt.pix; ++ else ++ pix_fmt = &ctx->dst_fmt.pix; ++ ++ if (*nplanes) { ++ if (sizes[0] < pix_fmt->sizeimage) ++ return -EINVAL; ++ } else { ++ sizes[0] = pix_fmt->sizeimage; ++ *nplanes = 1; ++ } ++ ++ return 0; ++} ++ ++static int iep_buf_prepare(struct vb2_buffer *vb) ++{ ++ struct vb2_queue *vq = vb->vb2_queue; ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ struct v4l2_pix_format *pix_fmt; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ pix_fmt = &ctx->src_fmt.pix; ++ else ++ pix_fmt = &ctx->dst_fmt.pix; ++ ++ if (vb2_plane_size(vb, 0) < pix_fmt->sizeimage) ++ return -EINVAL; ++ ++ /* set bytesused for capture buffers */ ++ if (!V4L2_TYPE_IS_OUTPUT(vq->type)) ++ vb2_set_plane_payload(vb, 0, pix_fmt->sizeimage); ++ ++ return 0; ++} ++ ++static void iep_buf_queue(struct vb2_buffer *vb) ++{ ++ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); ++ struct iep_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); ++ ++ v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); ++} ++ ++static void iep_queue_cleanup(struct vb2_queue *vq, u32 state) ++{ ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ struct vb2_v4l2_buffer *vbuf; ++ ++ do { ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) ++ vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); ++ else ++ vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); ++ ++ if (vbuf) ++ v4l2_m2m_buf_done(vbuf, state); ++ } while (vbuf); ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type) && ctx->prev_src_buf) ++ v4l2_m2m_buf_done(ctx->prev_src_buf, state); ++ else ++ iep_m2m_dst_bufs_done(ctx, state); ++} ++ ++static int iep_start_streaming(struct vb2_queue *vq, unsigned int count) ++{ ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ struct device *dev = ctx->iep->dev; ++ int ret; ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) { ++ ret = pm_runtime_get_sync(dev); ++ if (ret < 0) { ++ dev_err(dev, "Failed to enable module\n"); ++ goto err_runtime_get; ++ } ++ ++ ctx->field_order_bff = ++ ctx->src_fmt.pix.field == V4L2_FIELD_INTERLACED_BT; ++ ctx->field_bff = ctx->field_order_bff; ++ ++ ctx->src_sequence = 0; ++ ctx->dst_sequence = 0; ++ ++ ctx->prev_src_buf = NULL; ++ ++ ctx->dst0_buf = NULL; ++ ctx->dst1_buf = NULL; ++ ctx->dst_buffs_done = 0; ++ ++ ctx->job_abort = false; ++ ++ iep_init(ctx->iep); ++ //if (ctx->src_fmt.pix.field != ctx->dst_fmt.pix.field) ++ iep_dein_init(ctx->iep); ++ } ++ ++ return 0; ++ ++err_runtime_get: ++ iep_queue_cleanup(vq, VB2_BUF_STATE_QUEUED); ++ ++ return ret; ++} ++ ++static void iep_stop_streaming(struct vb2_queue *vq) ++{ ++ struct iep_ctx *ctx = vb2_get_drv_priv(vq); ++ ++ if (V4L2_TYPE_IS_OUTPUT(vq->type)) { ++ pm_runtime_mark_last_busy(ctx->iep->dev); ++ pm_runtime_put_autosuspend(ctx->iep->dev); ++ } ++ ++ iep_queue_cleanup(vq, VB2_BUF_STATE_ERROR); ++} ++ ++static const struct vb2_ops iep_qops = { ++ .queue_setup = iep_queue_setup, ++ .buf_prepare = iep_buf_prepare, ++ .buf_queue = iep_buf_queue, ++ .start_streaming = iep_start_streaming, ++ .stop_streaming = iep_stop_streaming, ++ .wait_prepare = vb2_ops_wait_prepare, ++ .wait_finish = vb2_ops_wait_finish, ++}; ++ ++static int iep_queue_init(void *priv, struct vb2_queue *src_vq, ++ struct vb2_queue *dst_vq) ++{ ++ struct iep_ctx *ctx = priv; ++ int ret; ++ ++ src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT; ++ src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | ++ DMA_ATTR_NO_KERNEL_MAPPING; ++ src_vq->io_modes = VB2_MMAP | VB2_DMABUF; ++ src_vq->drv_priv = ctx; ++ src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); ++ src_vq->min_buffers_needed = 1; ++ src_vq->ops = &iep_qops; ++ src_vq->mem_ops = &vb2_dma_contig_memops; ++ src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ++ src_vq->lock = &ctx->iep->mutex; ++ src_vq->dev = ctx->iep->v4l2_dev.dev; ++ ++ ret = vb2_queue_init(src_vq); ++ if (ret) ++ return ret; ++ ++ dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | ++ DMA_ATTR_NO_KERNEL_MAPPING; ++ dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; ++ dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; ++ dst_vq->drv_priv = ctx; ++ dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); ++ dst_vq->min_buffers_needed = 2; ++ dst_vq->ops = &iep_qops; ++ dst_vq->mem_ops = &vb2_dma_contig_memops; ++ dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; ++ dst_vq->lock = &ctx->iep->mutex; ++ dst_vq->dev = ctx->iep->v4l2_dev.dev; ++ ++ ret = vb2_queue_init(dst_vq); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static void iep_prepare_format(struct v4l2_pix_format *pix_fmt) ++{ ++ unsigned int height = pix_fmt->height; ++ unsigned int width = pix_fmt->width; ++ unsigned int sizeimage, bytesperline; ++ ++ struct iep_fmt *hw_fmt = iep_fmt_find(pix_fmt); ++ ++ if (!hw_fmt) { ++ hw_fmt = &formats[0]; ++ pix_fmt->pixelformat = hw_fmt->fourcc; ++ } ++ ++ width = ALIGN(clamp(width, IEP_MIN_WIDTH, ++ IEP_MAX_WIDTH), 16); ++ height = ALIGN(clamp(height, IEP_MIN_HEIGHT, ++ IEP_MAX_HEIGHT), 16); ++ ++ bytesperline = FMT_IS_YUV(hw_fmt->hw_format) ++ ? width : (width * hw_fmt->depth) >> 3; ++ ++ sizeimage = height * (width * hw_fmt->depth) >> 3; ++ ++ pix_fmt->width = width; ++ pix_fmt->height = height; ++ pix_fmt->bytesperline = bytesperline; ++ pix_fmt->sizeimage = sizeimage; ++} ++ ++static int iep_open(struct file *file) ++{ ++ struct rockchip_iep *iep = video_drvdata(file); ++ struct iep_ctx *ctx = NULL; ++ ++ int ret; ++ ++ if (mutex_lock_interruptible(&iep->mutex)) ++ return -ERESTARTSYS; ++ ++ ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); ++ if (!ctx) { ++ mutex_unlock(&iep->mutex); ++ return -ENOMEM; ++ } ++ ++ /* default output format */ ++ ctx->src_fmt.pix.pixelformat = formats[0].fourcc; ++ ctx->src_fmt.pix.field = V4L2_FIELD_INTERLACED; ++ ctx->src_fmt.pix.width = IEP_DEFAULT_WIDTH; ++ ctx->src_fmt.pix.height = IEP_DEFAULT_HEIGHT; ++ iep_prepare_format(&ctx->src_fmt.pix); ++ ctx->src_fmt.hw_fmt = &formats[0]; ++ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height); ++ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->src_fmt.pix.width, ctx->src_fmt.pix.height, ++ ctx->src_fmt.hw_fmt->uv_factor); ++ ++ /* default capture format */ ++ ctx->dst_fmt.pix.pixelformat = formats[0].fourcc; ++ ctx->dst_fmt.pix.field = V4L2_FIELD_NONE; ++ ctx->dst_fmt.pix.width = IEP_DEFAULT_WIDTH; ++ ctx->dst_fmt.pix.height = IEP_DEFAULT_HEIGHT; ++ iep_prepare_format(&ctx->dst_fmt.pix); ++ ctx->dst_fmt.hw_fmt = &formats[0]; ++ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height); ++ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(ctx->dst_fmt.pix.width, ctx->dst_fmt.pix.height, ++ ctx->dst_fmt.hw_fmt->uv_factor); ++ /* ensure fmts are written to HW */ ++ ctx->fmt_changed = true; ++ ++ v4l2_fh_init(&ctx->fh, video_devdata(file)); ++ file->private_data = &ctx->fh; ++ ctx->iep = iep; ++ ++ ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(iep->m2m_dev, ctx, ++ &iep_queue_init); ++ ++ if (IS_ERR(ctx->fh.m2m_ctx)) { ++ ret = PTR_ERR(ctx->fh.m2m_ctx); ++ goto err_free; ++ } ++ ++ v4l2_fh_add(&ctx->fh); ++ ++ mutex_unlock(&iep->mutex); ++ ++ return 0; ++ ++err_free: ++ kfree(ctx); ++ mutex_unlock(&iep->mutex); ++ ++ return ret; ++} ++ ++static int iep_release(struct file *file) ++{ ++ struct rockchip_iep *iep = video_drvdata(file); ++ struct iep_ctx *ctx = container_of(file->private_data, ++ struct iep_ctx, fh); ++ ++ mutex_lock(&iep->mutex); ++ ++ v4l2_fh_del(&ctx->fh); ++ v4l2_fh_exit(&ctx->fh); ++ v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); ++ kfree(ctx); ++ ++ mutex_unlock(&iep->mutex); ++ return 0; ++} ++ ++static const struct v4l2_file_operations iep_fops = { ++ .owner = THIS_MODULE, ++ .open = iep_open, ++ .release = iep_release, ++ .poll = v4l2_m2m_fop_poll, ++ .unlocked_ioctl = video_ioctl2, ++ .mmap = v4l2_m2m_fop_mmap, ++}; ++ ++static int iep_querycap(struct file *file, void *priv, ++ struct v4l2_capability *cap) ++{ ++ strscpy(cap->driver, IEP_NAME, sizeof(cap->driver)); ++ strscpy(cap->card, IEP_NAME, sizeof(cap->card)); ++ snprintf(cap->bus_info, sizeof(cap->bus_info), ++ "platform:%s", IEP_NAME); ++ ++ return 0; ++} ++ ++static int iep_enum_fmt(struct file *file, void *priv, ++ struct v4l2_fmtdesc *f) ++{ ++ struct iep_fmt *fmt; ++ ++ if (f->index < ARRAY_SIZE(formats)) { ++ fmt = &formats[f->index]; ++ f->pixelformat = fmt->fourcc; ++ ++ return 0; ++ } ++ ++ return -EINVAL; ++} ++ ++static int iep_enum_framesizes(struct file *file, void *priv, ++ struct v4l2_frmsizeenum *fsize) ++{ ++ if (fsize->index != 0) ++ return -EINVAL; ++ ++ if (!iep_check_pix_format(fsize->pixel_format)) ++ return -EINVAL; ++ ++ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; ++ ++ fsize->stepwise.min_width = IEP_MIN_WIDTH; ++ fsize->stepwise.max_width = IEP_MAX_WIDTH; ++ fsize->stepwise.step_width = 16; ++ ++ fsize->stepwise.min_height = IEP_MIN_HEIGHT; ++ fsize->stepwise.max_height = IEP_MAX_HEIGHT; ++ fsize->stepwise.step_height = 16; ++ ++ return 0; ++} ++ ++static inline struct iep_ctx *iep_file2ctx(struct file *file) ++{ ++ return container_of(file->private_data, struct iep_ctx, fh); ++} ++ ++static int iep_g_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct iep_ctx *ctx = iep_file2ctx(file); ++ ++ f->fmt.pix = ctx->dst_fmt.pix; ++ ++ return 0; ++} ++ ++static int iep_g_fmt_vid_out(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct iep_ctx *ctx = iep_file2ctx(file); ++ ++ f->fmt.pix = ctx->src_fmt.pix; ++ ++ return 0; ++} ++ ++static int iep_try_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ f->fmt.pix.field = V4L2_FIELD_NONE; ++ iep_prepare_format(&f->fmt.pix); ++ ++ return 0; ++} ++ ++static int iep_try_fmt_vid_out(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ if (f->fmt.pix.field != V4L2_FIELD_INTERLACED_TB && ++ f->fmt.pix.field != V4L2_FIELD_INTERLACED_BT && ++ f->fmt.pix.field != V4L2_FIELD_INTERLACED) ++ f->fmt.pix.field = V4L2_FIELD_INTERLACED; ++ ++ iep_prepare_format(&f->fmt.pix); ++ ++ return 0; ++} ++ ++static int iep_s_fmt_vid_out(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct iep_ctx *ctx = iep_file2ctx(file); ++ struct vb2_queue *vq; ++ ++ int ret; ++ ++ ret = iep_try_fmt_vid_out(file, priv, f); ++ if (ret) ++ return ret; ++ ++ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); ++ if (vb2_is_busy(vq)) ++ return -EBUSY; ++ ++ ctx->src_fmt.pix = f->fmt.pix; ++ ctx->src_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix); ++ ctx->src_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); ++ ctx->src_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, ++ ctx->src_fmt.hw_fmt->uv_factor); ++ ++ /* Propagate colorspace information to capture. */ ++ ctx->dst_fmt.pix.colorspace = f->fmt.pix.colorspace; ++ ctx->dst_fmt.pix.xfer_func = f->fmt.pix.xfer_func; ++ ctx->dst_fmt.pix.ycbcr_enc = f->fmt.pix.ycbcr_enc; ++ ctx->dst_fmt.pix.quantization = f->fmt.pix.quantization; ++ ++ /* scaling is not supported */ ++ ctx->dst_fmt.pix.width = f->fmt.pix.width; ++ ctx->dst_fmt.pix.height = f->fmt.pix.height; ++ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); ++ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, ++ ctx->dst_fmt.hw_fmt->uv_factor); ++ ++ ctx->fmt_changed = true; ++ ++ return 0; ++} ++ ++static int iep_s_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct iep_ctx *ctx = iep_file2ctx(file); ++ struct vb2_queue *vq; ++ int ret; ++ ++ ret = iep_try_fmt_vid_cap(file, priv, f); ++ if (ret) ++ return ret; ++ ++ vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); ++ if (vb2_is_busy(vq)) ++ return -EBUSY; ++ ++ /* scaling is not supported */ ++ f->fmt.pix.width = ctx->src_fmt.pix.width; ++ f->fmt.pix.height = ctx->src_fmt.pix.height; ++ ++ ctx->dst_fmt.pix = f->fmt.pix; ++ ctx->dst_fmt.hw_fmt = iep_fmt_find(&f->fmt.pix); ++ ++ ctx->dst_fmt.y_stride = IEP_Y_STRIDE(f->fmt.pix.width, f->fmt.pix.height); ++ ctx->dst_fmt.uv_stride = IEP_UV_STRIDE(f->fmt.pix.width, f->fmt.pix.height, ++ ctx->dst_fmt.hw_fmt->uv_factor); ++ ++ ctx->fmt_changed = true; ++ ++ return 0; ++} ++ ++static const struct v4l2_ioctl_ops iep_ioctl_ops = { ++ .vidioc_querycap = iep_querycap, ++ ++ .vidioc_enum_framesizes = iep_enum_framesizes, ++ ++ .vidioc_enum_fmt_vid_cap = iep_enum_fmt, ++ .vidioc_g_fmt_vid_cap = iep_g_fmt_vid_cap, ++ .vidioc_try_fmt_vid_cap = iep_try_fmt_vid_cap, ++ .vidioc_s_fmt_vid_cap = iep_s_fmt_vid_cap, ++ ++ .vidioc_enum_fmt_vid_out = iep_enum_fmt, ++ .vidioc_g_fmt_vid_out = iep_g_fmt_vid_out, ++ .vidioc_try_fmt_vid_out = iep_try_fmt_vid_out, ++ .vidioc_s_fmt_vid_out = iep_s_fmt_vid_out, ++ ++ .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, ++ .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, ++ .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, ++ .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, ++ .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, ++ .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, ++ .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, ++ ++ .vidioc_streamon = v4l2_m2m_ioctl_streamon, ++ .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, ++}; ++ ++static const struct video_device iep_video_device = { ++ .name = IEP_NAME, ++ .vfl_dir = VFL_DIR_M2M, ++ .fops = &iep_fops, ++ .ioctl_ops = &iep_ioctl_ops, ++ .minor = -1, ++ .release = video_device_release_empty, ++ .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING, ++}; ++ ++static int iep_parse_dt(struct rockchip_iep *iep) ++{ ++ int ret = 0; ++ ++ iep->axi_clk = devm_clk_get(iep->dev, "axi"); ++ if (IS_ERR(iep->axi_clk)) { ++ dev_err(iep->dev, "failed to get aclk clock\n"); ++ return PTR_ERR(iep->axi_clk); ++ } ++ ++ iep->ahb_clk = devm_clk_get(iep->dev, "ahb"); ++ if (IS_ERR(iep->ahb_clk)) { ++ dev_err(iep->dev, "failed to get hclk clock\n"); ++ return PTR_ERR(iep->ahb_clk); ++ } ++ ++ ret = clk_set_rate(iep->axi_clk, 300000000); ++ ++ if (ret) ++ dev_err(iep->dev, "failed to set axi clock rate to 300 MHz\n"); ++ ++ return ret; ++} ++ ++static irqreturn_t iep_isr(int irq, void *prv) ++{ ++ struct rockchip_iep *iep = prv; ++ struct iep_ctx *ctx; ++ u32 val; ++ enum vb2_buffer_state state = VB2_BUF_STATE_DONE; ++ ++ ctx = v4l2_m2m_get_curr_priv(iep->m2m_dev); ++ if (!ctx) { ++ v4l2_err(&iep->v4l2_dev, ++ "Instance released before the end of transaction\n"); ++ return IRQ_NONE; ++ } ++ ++ /* ++ * The irq is shared with the iommu. If the runtime-pm state of the ++ * iep-device is disabled or the interrupt status doesn't match the ++ * expeceted mask the irq has been targeted to the iommu. ++ */ ++ ++ if (!pm_runtime_active(iep->dev) || ++ !(iep_read(iep, IEP_INT) & IEP_INT_MASK)) ++ return IRQ_NONE; ++ ++ /* disable interrupt - will be re-enabled at next iep_device_run */ ++ iep_mod(ctx->iep, IEP_INT, ++ IEP_INT_FRAME_DONE_EN, 0); ++ ++ iep_mod(iep, IEP_INT, IEP_INT_FRAME_DONE_CLR, ++ IEP_INT_FRAME_DONE_CLR); ++ ++ /* wait for all status regs to show "idle" */ ++ val = readl_poll_timeout(iep->regs + IEP_STATUS, val, ++ (val == 0), 100, IEP_TIMEOUT); ++ ++ if (val) { ++ dev_err(iep->dev, ++ "Failed to wait for job to finish: status: %u\n", val); ++ state = VB2_BUF_STATE_ERROR; ++ ctx->job_abort = true; ++ } ++ ++ iep_m2m_dst_bufs_done(ctx, state); ++ ++ ctx->field_bff = (ctx->dst_buffs_done % 2 == 0) ++ ? ctx->field_order_bff : !ctx->field_order_bff; ++ ++ if (ctx->dst_buffs_done == 2 || ctx->job_abort) { ++ if (ctx->prev_src_buf) ++ v4l2_m2m_buf_done(ctx->prev_src_buf, state); ++ ++ /* current src buff will be next prev */ ++ ctx->prev_src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); ++ ++ v4l2_m2m_job_finish(ctx->iep->m2m_dev, ctx->fh.m2m_ctx); ++ ctx->dst_buffs_done = 0; ++ ++ } else { ++ iep_device_run(ctx); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int iep_probe(struct platform_device *pdev) ++{ ++ struct rockchip_iep *iep; ++ struct video_device *vfd; ++ struct resource *res; ++ int ret = 0; ++ int irq; ++ ++ if (!pdev->dev.of_node) ++ return -ENODEV; ++ ++ iep = devm_kzalloc(&pdev->dev, sizeof(*iep), GFP_KERNEL); ++ if (!iep) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, iep); ++ iep->dev = &pdev->dev; ++ iep->vfd = iep_video_device; ++ ++ ret = iep_parse_dt(iep); ++ if (ret) ++ dev_err(&pdev->dev, "Unable to parse OF data\n"); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ++ iep->regs = devm_ioremap_resource(iep->dev, res); ++ if (IS_ERR(iep->regs)) { ++ ret = PTR_ERR(iep->regs); ++ goto err_put_clk; ++ } ++ ++ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ dev_err(&pdev->dev, "Could not set DMA coherent mask.\n"); ++ goto err_put_clk; ++ } ++ ++ vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ ret = irq; ++ goto err_put_clk; ++ } ++ ++ /* IRQ is shared with IOMMU */ ++ ret = devm_request_irq(iep->dev, irq, iep_isr, IRQF_SHARED, ++ dev_name(iep->dev), iep); ++ if (ret < 0) { ++ dev_err(iep->dev, "failed to request irq\n"); ++ goto err_put_clk; ++ } ++ ++ mutex_init(&iep->mutex); ++ ++ ret = v4l2_device_register(&pdev->dev, &iep->v4l2_dev); ++ if (ret) { ++ dev_err(iep->dev, "Failed to register V4L2 device\n"); ++ ++ return ret; ++ } ++ ++ vfd = &iep->vfd; ++ vfd->lock = &iep->mutex; ++ vfd->v4l2_dev = &iep->v4l2_dev; ++ ++ snprintf(vfd->name, sizeof(vfd->name), "%s", ++ iep_video_device.name); ++ ++ video_set_drvdata(vfd, iep); ++ ++ ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0); ++ if (ret) { ++ v4l2_err(&iep->v4l2_dev, "Failed to register video device\n"); ++ ++ goto err_v4l2; ++ } ++ ++ v4l2_info(&iep->v4l2_dev, ++ "Device %s registered as /dev/video%d\n", vfd->name, vfd->num); ++ ++ iep->m2m_dev = v4l2_m2m_init(&iep_m2m_ops); ++ if (IS_ERR(iep->m2m_dev)) { ++ v4l2_err(&iep->v4l2_dev, ++ "Failed to initialize V4L2 M2M device\n"); ++ ret = PTR_ERR(iep->m2m_dev); ++ ++ goto err_video; ++ } ++ ++ pm_runtime_set_autosuspend_delay(iep->dev, 100); ++ pm_runtime_use_autosuspend(iep->dev); ++ pm_runtime_enable(iep->dev); ++ ++ return ret; ++ ++err_video: ++ video_unregister_device(&iep->vfd); ++err_v4l2: ++ v4l2_device_unregister(&iep->v4l2_dev); ++err_put_clk: ++ pm_runtime_dont_use_autosuspend(iep->dev); ++ pm_runtime_disable(iep->dev); ++ ++return ret; ++} ++ ++static int iep_remove(struct platform_device *pdev) ++{ ++ struct rockchip_iep *iep = platform_get_drvdata(pdev); ++ ++ pm_runtime_dont_use_autosuspend(iep->dev); ++ pm_runtime_disable(iep->dev); ++ ++ v4l2_m2m_release(iep->m2m_dev); ++ video_unregister_device(&iep->vfd); ++ v4l2_device_unregister(&iep->v4l2_dev); ++ ++ return 0; ++} ++ ++static int __maybe_unused iep_runtime_suspend(struct device *dev) ++{ ++ struct rockchip_iep *iep = dev_get_drvdata(dev); ++ ++ clk_disable_unprepare(iep->ahb_clk); ++ clk_disable_unprepare(iep->axi_clk); ++ ++ return 0; ++} ++ ++static int __maybe_unused iep_runtime_resume(struct device *dev) ++{ ++ struct rockchip_iep *iep; ++ int ret = 0; ++ ++ iep = dev_get_drvdata(dev); ++ ++ ret = clk_prepare_enable(iep->axi_clk); ++ if (ret) { ++ dev_err(iep->dev, "Cannot enable axi clock: %d\n", ret); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(iep->ahb_clk); ++ if (ret) { ++ dev_err(iep->dev, "Cannot enable ahb clock: %d\n", ret); ++ goto err_disable_axi_clk; ++ } ++ ++ return ret; ++ ++err_disable_axi_clk: ++ clk_disable_unprepare(iep->axi_clk); ++ return ret; ++} ++ ++static const struct dev_pm_ops iep_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, ++ pm_runtime_force_resume) ++ SET_RUNTIME_PM_OPS(iep_runtime_suspend, ++ iep_runtime_resume, NULL) ++}; ++ ++static const struct of_device_id rockchip_iep_match[] = { ++ { ++ .compatible = "rockchip,rk3228-iep", ++ }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, rockchip_iep_match); ++ ++static struct platform_driver iep_pdrv = { ++ .probe = iep_probe, ++ .remove = iep_remove, ++ .driver = { ++ .name = IEP_NAME, ++ .pm = &iep_pm_ops, ++ .of_match_table = rockchip_iep_match, ++ }, ++}; ++ ++module_platform_driver(iep_pdrv); ++ ++MODULE_AUTHOR("Alex Bee "); ++MODULE_DESCRIPTION("Rockchip Image Enhancement Processor"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/media/platform/rockchip/iep/iep.h b/drivers/media/platform/rockchip/iep/iep.h +new file mode 100644 +index 000000000000..7d9fc61624b6 +--- /dev/null ++++ b/drivers/media/platform/rockchip/iep/iep.h +@@ -0,0 +1,112 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Rockchip Image Enhancement Processor (IEP) driver ++ * ++ * Copyright (C) 2020 Alex Bee ++ * ++ */ ++#ifndef __IEP_H__ ++#define __IEP_H__ ++ ++#include ++#include ++#include ++#include ++ ++#define IEP_NAME "rockchip-iep" ++ ++/* Hardware limits */ ++#define IEP_MIN_WIDTH 320U ++#define IEP_MAX_WIDTH 1920U ++ ++#define IEP_MIN_HEIGHT 240U ++#define IEP_MAX_HEIGHT 1088U ++ ++/* Hardware defaults */ ++#define IEP_DEFAULT_WIDTH 320U ++#define IEP_DEFAULT_HEIGHT 240U ++ ++//ns ++#define IEP_TIMEOUT 250000 ++ ++struct iep_fmt { ++ u32 fourcc; ++ u8 depth; ++ u8 uv_factor; ++ u8 color_swap; ++ u8 hw_format; ++}; ++ ++struct iep_frm_fmt { ++ struct iep_fmt *hw_fmt; ++ struct v4l2_pix_format pix; ++ ++ unsigned int y_stride; ++ unsigned int uv_stride; ++}; ++ ++struct iep_ctx { ++ struct v4l2_fh fh; ++ struct rockchip_iep *iep; ++ ++ struct iep_frm_fmt src_fmt; ++ struct iep_frm_fmt dst_fmt; ++ ++ struct vb2_v4l2_buffer *prev_src_buf; ++ struct vb2_v4l2_buffer *dst0_buf; ++ struct vb2_v4l2_buffer *dst1_buf; ++ ++ u32 dst_sequence; ++ u32 src_sequence; ++ ++ /* bff = bottom field first */ ++ bool field_order_bff; ++ bool field_bff; ++ ++ unsigned int dst_buffs_done; ++ ++ bool fmt_changed; ++ bool job_abort; ++}; ++ ++struct rockchip_iep { ++ struct v4l2_device v4l2_dev; ++ struct v4l2_m2m_dev *m2m_dev; ++ struct video_device vfd; ++ ++ struct device *dev; ++ ++ void __iomem *regs; ++ ++ struct clk *axi_clk; ++ struct clk *ahb_clk; ++ ++ /* vfd lock */ ++ struct mutex mutex; ++}; ++ ++static inline void iep_write(struct rockchip_iep *iep, u32 reg, u32 value) ++{ ++ writel(value, iep->regs + reg); ++}; ++ ++static inline u32 iep_read(struct rockchip_iep *iep, u32 reg) ++{ ++ return readl(iep->regs + reg); ++}; ++ ++static inline void iep_shadow_mod(struct rockchip_iep *iep, u32 reg, ++ u32 shadow_reg, u32 mask, u32 val) ++{ ++ u32 temp = iep_read(iep, shadow_reg) & ~(mask); ++ ++ temp |= val & mask; ++ iep_write(iep, reg, temp); ++}; ++ ++static inline void iep_mod(struct rockchip_iep *iep, u32 reg, u32 mask, u32 val) ++{ ++ iep_shadow_mod(iep, reg, reg, mask, val); ++}; ++ ++#endif + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 14 Oct 2020 20:22:38 +0200 +Subject: [PATCH] ARM64: dts: rockchip: Add IEP node for RK3328 + +while at that also add the mmu required + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 +++++++++++++++++++++++- + 1 file changed, 24 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index bd1e5edfbf95..b91c0bbe5ad1 100644 +@@ -767,6 +768,28 @@ vop_mmu: iommu@ff373f00 { + status = "disabled"; + }; + ++ iep: iep@ff3a0000 { ++ compatible = "rockchip,rk3328-iep", "rockchip,rk3228-iep"; ++ reg = <0x0 0xff3a0000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "iep"; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "axi", "ahb"; ++ power-domains = <&power RK3328_PD_VIDEO>; ++ iommus = <&iep_mmu>; ++ }; ++ ++ iep_mmu: iommu@ff3a0800 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff3a0800 0x0 0x40>; ++ interrupts = ; ++ interrupt-names = "iep_mmu"; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "aclk", "iface"; ++ power-domains = <&power RK3328_PD_VIDEO>; ++ #iommu-cells = <0>; ++ }; ++ + hdmi: hdmi@ff3c0000 { + compatible = "rockchip,rk3328-dw-hdmi"; + reg = <0x0 0xff3c0000 0x0 0x20000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 14 Oct 2020 20:43:12 +0200 +Subject: [PATCH] ARM64: dts: rockchip: Add IEP node for RK3399 + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 13 ++++++++++++- + 1 file changed, 12 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 4d5004c9c778..7969aeec0bd0 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1297,6 +1297,17 @@ vdec_mmu: iommu@ff660480 { + #iommu-cells = <0>; + }; + ++ iep: iep@ff670000 { ++ compatible = "rockchip,rk3399-iep", "rockchip,rk3228-iep"; ++ reg = <0x0 0xff670000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "iep"; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "axi", "ahb"; ++ power-domains = <&power RK3399_PD_IEP>; ++ iommus = <&iep_mmu>; ++ }; ++ + iep_mmu: iommu@ff670800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff670800 0x0 0x40>; +@@ -1304,8 +1315,8 @@ iep_mmu: iommu@ff670800 { + interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; ++ power-domains = <&power RK3399_PD_IEP>; + #iommu-cells = <0>; +- status = "disabled"; + }; + + rga: rga@ff680000 { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 14 Oct 2020 20:53:56 +0200 +Subject: [PATCH] ARM: dts: rockchip: Add IEP node for RK3288 + +Signed-off-by: Alex Bee +--- + arch/arm/boot/dts/rk3288.dtsi | 13 ++++++++++++- + 1 file changed, 12 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi +index ba43ee6b91e8..e9bd68cd926e 100644 +--- a/arch/arm/boot/dts/rk3288.dtsi ++++ b/arch/arm/boot/dts/rk3288.dtsi +@@ -1002,6 +1002,17 @@ crypto: cypto-controller@ff8a0000 { + status = "okay"; + }; + ++ iep: iep@ff90000 { ++ compatible = "rockchip,rk3288-iep", "rockchip,rk3228-iep"; ++ reg = <0x0 0xff900000 0x0 0x800>; ++ interrupts = ; ++ interrupt-names = "iep"; ++ clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; ++ clock-names = "axi", "ahb"; ++ power-domains = <&power RK3288_PD_VIO>; ++ iommus = <&iep_mmu>; ++ }; ++ + iep_mmu: iommu@ff900800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff900800 0x0 0x40>; +@@ -1009,8 +1020,8 @@ iep_mmu: iommu@ff900800 { + interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; ++ power-domains = <&power RK3288_PD_VIO>; + #iommu-cells = <0>; +- status = "disabled"; + }; + + isp_mmu: iommu@ff914000 {