diff --git a/projects/Allwinner/devices/A64/patches/linux/08-enable-opi-win-ir.patch b/projects/Allwinner/devices/A64/patches/linux/08-enable-opi-win-ir.patch deleted file mode 100644 index b9d63eb19f..0000000000 --- a/projects/Allwinner/devices/A64/patches/linux/08-enable-opi-win-ir.patch +++ /dev/null @@ -1,135 +0,0 @@ -From c642dca33a893b38770003f92de5708b2ef82878 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Thu, 10 Jan 2019 20:00:25 +0100 -Subject: [PATCH 1/4] media: dt: bindings: sunxi-ir: Add A64 compatible - -A64 IR is compatible with A13, so add A64 compatible with A13 as a -fallback. - -Signed-off-by: Jernej Skrabec ---- - Documentation/devicetree/bindings/media/sunxi-ir.txt | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt -index 278098987edb..ecac6964b69b 100644 ---- a/Documentation/devicetree/bindings/media/sunxi-ir.txt -+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt -@@ -1,7 +1,10 @@ - Device-Tree bindings for SUNXI IR controller found in sunXi SoC family - - Required properties: --- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir" -+- compatible : value must be one of: -+ * "allwinner,sun4i-a10-ir" -+ * "allwinner,sun5i-a13-ir" -+ * "allwinner,sun50i-a64-ir", "allwinner,sun5i-a13-ir" - - clocks : list of clock specifiers, corresponding to - entries in clock-names property; - - clock-names : should contain "apb" and "ir" entries; --- -2.20.1 - - -From 85923b765bbd31be033a7b7d8bf0018accb386dd Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Thu, 10 Jan 2019 20:50:15 +0100 -Subject: [PATCH 2/4] arm64: dts: allwinner: a64: Add IR pinmux - -IR on A64 has a dedicated pin. Add pinmux setting for it. - -Signed-off-by: Jernej Skrabec ---- - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -index 839b2ae88583..86ff1d3a4ffa 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -1043,6 +1043,11 @@ - function = "s_i2c"; - }; - -+ r_ir_pins: ir-pins { -+ pins = "PL11"; -+ function = "s_cir_rx"; -+ }; -+ - r_pwm_pin: r-pwm-pin { - pins = "PL10"; - function = "s_pwm"; --- -2.20.1 - - -From 943855104927268a641bd4f5f35c0592398e39ec Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Thu, 10 Jan 2019 20:19:32 +0100 -Subject: [PATCH 3/4] arm64: dts: allwinner: a64: Add IR node - -IR is similar to that in A13 and can use same driver. - -Signed-off-by: Jernej Skrabec ---- - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -index 86ff1d3a4ffa..8238caedd90e 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -1004,6 +1004,17 @@ - status = "disabled"; - }; - -+ r_ir: ir@1f02000 { -+ compatible = "allwinner,sun50i-a64-ir", -+ "allwinner,sun5i-a13-ir"; -+ reg = <0x01f02000 0x400>; -+ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; -+ clock-names = "apb", "ir"; -+ resets = <&r_ccu RST_APB0_IR>; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ - r_i2c: i2c@1f02400 { - compatible = "allwinner,sun50i-a64-i2c", - "allwinner,sun6i-a31-i2c"; --- -2.20.1 - - -From 3020e7d85fe574cda8e6803330ffd75fffdbbf6b Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Thu, 10 Jan 2019 20:25:18 +0100 -Subject: [PATCH 4/4] arm64: dts: allwinner: a64: Orange Pi Win: Enable IR - -OrangePi Win board contains IR receiver. Enable it. - -Signed-off-by: Jernej Skrabec ---- - arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -index b0c64f75792c..c6c759511f5e 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -@@ -144,6 +144,12 @@ - }; - }; - -+&r_ir { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&r_ir_pins>; -+ status = "okay"; -+}; -+ - &mdio { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; --- -2.20.1 - diff --git a/projects/Allwinner/patches/linux/0002-backport-from-5.3.patch b/projects/Allwinner/patches/linux/0002-backport-from-5.3.patch index 5a4442f34c..e7b67b0c89 100644 --- a/projects/Allwinner/patches/linux/0002-backport-from-5.3.patch +++ b/projects/Allwinner/patches/linux/0002-backport-from-5.3.patch @@ -3158,3 +3158,43 @@ index b9a7dc8d2a40..7628a7c83096 100644 -- 2.22.0 +From f167675486c37b88620d344fbb12d06e34f11d47 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Tue, 4 Jun 2019 17:40:36 +0200 +Subject: [PATCH] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate + register +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The current code defines W1 clock gate to be at 0x1cc, overlaying it +with the IR gate. + +Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver +causing interrupt floods on H6 (because interrupt flags can't be cleared, +due to IR module's bus being disabled). + +Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU") +Signed-off-by: Ondrej Jirman +Acked-by: Clément Péron +Signed-off-by: Maxime Ripard +--- + drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c +index 27554eaf6929..8d05d4f1f8a1 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c +@@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2", + static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1", + 0x1cc, BIT(0), 0); + static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1", +- 0x1cc, BIT(0), 0); ++ 0x1ec, BIT(0), 0); + + /* Information of IR(RX) mod clock is gathered from BSP source code */ + static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" }; +-- +2.22.0 + diff --git a/projects/Allwinner/patches/linux/0003-backport-from-5.4.patch b/projects/Allwinner/patches/linux/0003-backport-from-5.4.patch index 4aa7d6154b..2bfe873bb9 100644 --- a/projects/Allwinner/patches/linux/0003-backport-from-5.4.patch +++ b/projects/Allwinner/patches/linux/0003-backport-from-5.4.patch @@ -649,3 +649,576 @@ index 2c6807b74ff6..01bb1bafe284 100644 &mmc0 { vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + +From 6b197cb5b4dc7be463599daeb28dfb8d24674746 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Fri, 7 Jun 2019 20:10:49 -0300 +Subject: [PATCH 1/3] media: rc: Introduce sunxi_ir_quirks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This driver is used in various Allwinner SoC with different configuration. + +Introduce a quirks struct to know the fifo size and if a reset is required. + +Signed-off-by: Clément Péron +Acked-by: Maxime Ripard +Signed-off-by: Sean Young +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/rc/sunxi-cir.c | 61 +++++++++++++++++++++++++++--------- + 1 file changed, 47 insertions(+), 14 deletions(-) + +diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c +index aa719d0ae6b0..29fe152fd9bc 100644 +--- a/drivers/media/rc/sunxi-cir.c ++++ b/drivers/media/rc/sunxi-cir.c +@@ -72,6 +72,17 @@ + /* Time after which device stops sending data in ms */ + #define SUNXI_IR_TIMEOUT 120 + ++/** ++ * struct sunxi_ir_quirks - Differences between SoC variants. ++ * ++ * @has_reset: SoC needs reset deasserted. ++ * @fifo_size: size of the fifo. ++ */ ++struct sunxi_ir_quirks { ++ bool has_reset; ++ int fifo_size; ++}; ++ + struct sunxi_ir { + spinlock_t ir_lock; + struct rc_dev *rc; +@@ -134,6 +145,7 @@ static int sunxi_ir_probe(struct platform_device *pdev) + + struct device *dev = &pdev->dev; + struct device_node *dn = dev->of_node; ++ const struct sunxi_ir_quirks *quirks; + struct resource *res; + struct sunxi_ir *ir; + u32 b_clk_freq = SUNXI_IR_BASE_CLK; +@@ -142,12 +154,15 @@ static int sunxi_ir_probe(struct platform_device *pdev) + if (!ir) + return -ENOMEM; + ++ quirks = of_device_get_match_data(&pdev->dev); ++ if (!quirks) { ++ dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); ++ return -ENODEV; ++ } ++ + spin_lock_init(&ir->ir_lock); + +- if (of_device_is_compatible(dn, "allwinner,sun5i-a13-ir")) +- ir->fifo_size = 64; +- else +- ir->fifo_size = 16; ++ ir->fifo_size = quirks->fifo_size; + + /* Clock */ + ir->apb_clk = devm_clk_get(dev, "apb"); +@@ -164,13 +179,15 @@ static int sunxi_ir_probe(struct platform_device *pdev) + /* Base clock frequency (optional) */ + of_property_read_u32(dn, "clock-frequency", &b_clk_freq); + +- /* Reset (optional) */ +- ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL); +- if (IS_ERR(ir->rst)) +- return PTR_ERR(ir->rst); +- ret = reset_control_deassert(ir->rst); +- if (ret) +- return ret; ++ /* Reset */ ++ if (quirks->has_reset) { ++ ir->rst = devm_reset_control_get_exclusive(dev, NULL); ++ if (IS_ERR(ir->rst)) ++ return PTR_ERR(ir->rst); ++ ret = reset_control_deassert(ir->rst); ++ if (ret) ++ return ret; ++ } + + ret = clk_set_rate(ir->clk, b_clk_freq); + if (ret) { +@@ -306,10 +323,26 @@ static int sunxi_ir_remove(struct platform_device *pdev) + return 0; + } + ++static const struct sunxi_ir_quirks sun4i_a10_ir_quirks = { ++ .has_reset = false, ++ .fifo_size = 16, ++}; ++ ++static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = { ++ .has_reset = false, ++ .fifo_size = 64, ++}; ++ + static const struct of_device_id sunxi_ir_match[] = { +- { .compatible = "allwinner,sun4i-a10-ir", }, +- { .compatible = "allwinner,sun5i-a13-ir", }, +- {}, ++ { ++ .compatible = "allwinner,sun4i-a10-ir", ++ .data = &sun4i_a10_ir_quirks, ++ }, ++ { ++ .compatible = "allwinner,sun5i-a13-ir", ++ .data = &sun5i_a13_ir_quirks, ++ }, ++ {} + }; + MODULE_DEVICE_TABLE(of, sunxi_ir_match); + +-- +2.22.0 + + +From 87d0609801ebcdf18639bb30ec5ec9a380f15be8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Fri, 7 Jun 2019 20:10:50 -0300 +Subject: [PATCH 2/3] media: rc: sunxi: Add A31 compatible +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Allwiner A31 has a different memory mapping so add the compatible +we will need it later. + +Signed-off-by: Clément Péron +Acked-by: Maxime Ripard +Signed-off-by: Sean Young +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/rc/sunxi-cir.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c +index 29fe152fd9bc..e9b9c582f818 100644 +--- a/drivers/media/rc/sunxi-cir.c ++++ b/drivers/media/rc/sunxi-cir.c +@@ -333,6 +333,11 @@ static const struct sunxi_ir_quirks sun5i_a13_ir_quirks = { + .fifo_size = 64, + }; + ++static const struct sunxi_ir_quirks sun6i_a31_ir_quirks = { ++ .has_reset = true, ++ .fifo_size = 64, ++}; ++ + static const struct of_device_id sunxi_ir_match[] = { + { + .compatible = "allwinner,sun4i-a10-ir", +@@ -342,6 +347,10 @@ static const struct of_device_id sunxi_ir_match[] = { + .compatible = "allwinner,sun5i-a13-ir", + .data = &sun5i_a13_ir_quirks, + }, ++ { ++ .compatible = "allwinner,sun6i-a31-ir", ++ .data = &sun6i_a31_ir_quirks, ++ }, + {} + }; + MODULE_DEVICE_TABLE(of, sunxi_ir_match); +-- +2.22.0 + + +From b136d72cb89dc2bd11ba001c90cdc65b5f5a1034 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Fri, 7 Jun 2019 20:10:51 -0300 +Subject: [PATCH 3/3] media: rc: sunxi: Add RXSTA bits definition +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +We are using RXINT bits definition when looking at RXSTA register. + +These bits are equal but it's not really proper. + +Introduce the RXSTA bits and use them to have coherency. + +Signed-off-by: Clément Péron +Acked-by: Maxime Ripard +Signed-off-by: Sean Young +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/rc/sunxi-cir.c | 18 ++++++++++++------ + 1 file changed, 12 insertions(+), 6 deletions(-) + +diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c +index e9b9c582f818..f91154c2f45c 100644 +--- a/drivers/media/rc/sunxi-cir.c ++++ b/drivers/media/rc/sunxi-cir.c +@@ -39,11 +39,11 @@ + + /* Rx Interrupt Enable */ + #define SUNXI_IR_RXINT_REG 0x2C +-/* Rx FIFO Overflow */ ++/* Rx FIFO Overflow Interrupt Enable */ + #define REG_RXINT_ROI_EN BIT(0) +-/* Rx Packet End */ ++/* Rx Packet End Interrupt Enable */ + #define REG_RXINT_RPEI_EN BIT(1) +-/* Rx FIFO Data Available */ ++/* Rx FIFO Data Available Interrupt Enable */ + #define REG_RXINT_RAI_EN BIT(4) + + /* Rx FIFO available byte level */ +@@ -51,6 +51,12 @@ + + /* Rx Interrupt Status */ + #define SUNXI_IR_RXSTA_REG 0x30 ++/* Rx FIFO Overflow */ ++#define REG_RXSTA_ROI REG_RXINT_ROI_EN ++/* Rx Packet End */ ++#define REG_RXSTA_RPE REG_RXINT_RPEI_EN ++/* Rx FIFO Data Available */ ++#define REG_RXSTA_RA REG_RXINT_RAI_EN + /* RX FIFO Get Available Counter */ + #define REG_RXSTA_GET_AC(val) (((val) >> 8) & (ir->fifo_size * 2 - 1)) + /* Clear all interrupt status value */ +@@ -110,7 +116,7 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id) + /* clean all pending statuses */ + writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); + +- if (status & (REG_RXINT_RAI_EN | REG_RXINT_RPEI_EN)) { ++ if (status & (REG_RXSTA_RA | REG_RXSTA_RPE)) { + /* How many messages in fifo */ + rc = REG_RXSTA_GET_AC(status); + /* Sanity check */ +@@ -126,9 +132,9 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id) + } + } + +- if (status & REG_RXINT_ROI_EN) { ++ if (status & REG_RXSTA_ROI) { + ir_raw_event_reset(ir->rc); +- } else if (status & REG_RXINT_RPEI_EN) { ++ } else if (status & REG_RXSTA_RPE) { + ir_raw_event_set_idle(ir->rc, true); + ir_raw_event_handle(ir->rc); + } +-- +2.22.0 + +From 342d23a7dacf9c254c6b98b9b211e566820b7bad Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Sat, 8 Jun 2019 01:10:52 +0200 +Subject: [PATCH 1/6] ARM: dts: sunxi: Prefer A31 bindings for IR +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Since A31, memory mapping of the IR driver has changed. + +Prefer the A31 bindings instead of A13. + +Signed-off-by: Clément Péron +Acked-by: Sean Young +Signed-off-by: Maxime Ripard +--- + arch/arm/boot/dts/sun6i-a31.dtsi | 2 +- + arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +- + arch/arm/boot/dts/sun9i-a80.dtsi | 2 +- + 3 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi +index dcddc3392460..9ddde111f675 100644 +--- a/arch/arm/boot/dts/sun6i-a31.dtsi ++++ b/arch/arm/boot/dts/sun6i-a31.dtsi +@@ -1364,7 +1364,7 @@ + }; + + ir: ir@1f02000 { +- compatible = "allwinner,sun5i-a13-ir"; ++ compatible = "allwinner,sun6i-a31-ir"; + clocks = <&apb0_gates 1>, <&ir_clk>; + clock-names = "apb", "ir"; + resets = <&apb0_rst 1>; +diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi +index 8de139521451..13bc83191899 100644 +--- a/arch/arm/boot/dts/sun8i-a83t.dtsi ++++ b/arch/arm/boot/dts/sun8i-a83t.dtsi +@@ -1096,7 +1096,7 @@ + + r_cir: ir@1f02000 { + compatible = "allwinner,sun8i-a83t-ir", +- "allwinner,sun5i-a13-ir"; ++ "allwinner,sun6i-a31-ir"; + clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_APB0_IR>; +diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi +index 0c1eec9000e3..310cd972ee5b 100644 +--- a/arch/arm/boot/dts/sun9i-a80.dtsi ++++ b/arch/arm/boot/dts/sun9i-a80.dtsi +@@ -1167,7 +1167,7 @@ + }; + + r_ir: ir@8002000 { +- compatible = "allwinner,sun5i-a13-ir"; ++ compatible = "allwinner,sun6i-a31-ir"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_pins>; +-- +2.22.0 + + +From 8fa345e711bfdb69a18f548b717d5eb502b9892a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Sat, 8 Jun 2019 01:10:53 +0200 +Subject: [PATCH 2/6] ARM: dts: sunxi: Prefer A31 bindings for IR +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Since A31, memory mapping of the IR driver has changed. + +Prefer the A31 bindings instead of A13. + +Signed-off-by: Clément Péron +Acked-by: Sean Young +Signed-off-by: Maxime Ripard +--- + arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi +index b4a6035ae9f5..97550a40b6e1 100644 +--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi ++++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi +@@ -822,7 +822,7 @@ + }; + + ir: ir@1f02000 { +- compatible = "allwinner,sun5i-a13-ir"; ++ compatible = "allwinner,sun6i-a31-ir"; + clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_APB0_IR>; +-- +2.22.0 + + +From 44a4f416c8388449fc5f9263788857d449e2a65f Mon Sep 17 00:00:00 2001 +From: Igors Makejevs +Date: Sat, 8 Jun 2019 01:10:55 +0200 +Subject: [PATCH 3/6] arm64: dts: allwinner: a64: Add IR node +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +IR peripheral is completely compatible with A31 one. + +Signed-off-by: Igors Makejevs +Signed-off-by: Jernej Skrabec +Signed-off-by: Clément Péron +Acked-by: Sean Young +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index aa9897f270ba..ddb6f11e89df 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -1094,6 +1094,19 @@ + #size-cells = <0>; + }; + ++ r_ir: ir@1f02000 { ++ compatible = "allwinner,sun50i-a64-ir", ++ "allwinner,sun6i-a31-ir"; ++ reg = <0x01f02000 0x400>; ++ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; ++ clock-names = "apb", "ir"; ++ resets = <&r_ccu RST_APB0_IR>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&r_ir_rx_pin>; ++ status = "disabled"; ++ }; ++ + r_pwm: pwm@1f03800 { + compatible = "allwinner,sun50i-a64-pwm", + "allwinner,sun5i-a13-pwm"; +@@ -1121,6 +1134,11 @@ + function = "s_i2c"; + }; + ++ r_ir_rx_pin: r-ir-rx-pin { ++ pins = "PL11"; ++ function = "s_cir_rx"; ++ }; ++ + r_pwm_pin: r-pwm-pin { + pins = "PL10"; + function = "s_pwm"; +-- +2.22.0 + + +From 63eb1e149576294717e3e5de48e902ca9d2f080d Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 8 Jun 2019 01:10:56 +0200 +Subject: [PATCH 4/6] arm64: dts: allwinner: a64: Enable IR on Orange Pi Win +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +OrangePi Win board contains IR receiver. Enable it. + +Signed-off-by: Jernej Skrabec +Signed-off-by: Clément Péron +Acked-by: Sean Young +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +index 5ef3c62c765e..04446e4716c4 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +@@ -190,6 +190,10 @@ + status = "okay"; + }; + ++&r_ir { ++ status = "okay"; ++}; ++ + &r_rsb { + status = "okay"; + +-- +2.22.0 + + +From 9267811aad3524c857cf2e16bbadd8c569e15ab9 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Sat, 8 Jun 2019 01:10:58 +0200 +Subject: [PATCH 5/6] arm64: dts: allwinner: h6: Add IR receiver node +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Allwinner H6 IR is similar to A31 and can use same driver. + +Add support for it. + +Signed-off-by: Clément Péron +Acked-by: Sean Young +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index 35942bae0a34..e8bed58e7246 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -675,6 +675,25 @@ + pins = "PL0", "PL1"; + function = "s_i2c"; + }; ++ ++ r_ir_rx_pin: r-ir-rx-pin { ++ pins = "PL9"; ++ function = "s_cir_rx"; ++ }; ++ }; ++ ++ r_ir: ir@7040000 { ++ compatible = "allwinner,sun50i-h6-ir", ++ "allwinner,sun6i-a31-ir"; ++ reg = <0x07040000 0x400>; ++ interrupts = ; ++ clocks = <&r_ccu CLK_R_APB1_IR>, ++ <&r_ccu CLK_IR>; ++ clock-names = "apb", "ir"; ++ resets = <&r_ccu RST_R_APB1_IR>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&r_ir_rx_pin>; ++ status = "disabled"; + }; + + r_i2c: i2c@7081400 { +-- +2.22.0 + + +From 86be740845e3811c4517de1a8a36121190155e22 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= +Date: Sat, 8 Jun 2019 01:10:59 +0200 +Subject: [PATCH 6/6] arm64: dts: allwinner: h6: Enable IR on H6 boards +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Beelink GS1, OrangePi H6 boards and Pine H64 have an IR receiver. + +Enable it in their device-tree. + +Signed-off-by: Clément Péron +Signed-off-by: Maxime Ripard +--- + arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++++ + arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 4 ++++ + arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 4 ++++ + 3 files changed, 12 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +index 0dc33c90dd60..680dc29cb089 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +@@ -232,6 +232,10 @@ + }; + }; + ++&r_ir { ++ status = "okay"; ++}; ++ + &r_pio { + /* + * PL0 and PL1 are used for PMIC I2C +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +index 62e27948a3fa..ec9b6a578e3f 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +@@ -189,6 +189,10 @@ + }; + }; + ++&r_ir { ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +index 189834518391..30102daf83cc 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +@@ -255,6 +255,10 @@ + }; + }; + ++&r_ir { ++ status = "okay"; ++}; ++ + &r_pio { + vcc-pm-supply = <®_aldo1>; + }; +-- +2.22.0 +