From db23aadb87c35b9b341b57fb351eb02de80bd61c Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 1 Feb 2020 01:05:50 +0000 Subject: [PATCH 1/3] linux (Rockchip): update patches for 5.4.16 --- .../linux-0001-rockchip-from-5.5.patch | 136 +----- .../linux-0003-rockchip-from-list.patch | 47 --- .../default/linux-0011-v4l2-from-5.5.patch | 395 +----------------- 3 files changed, 16 insertions(+), 562 deletions(-) diff --git a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.5.patch b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.5.patch index 05b0bf5c7f..b1ce5ba111 100644 --- a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.5.patch +++ b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.5.patch @@ -1025,7 +1025,7 @@ diff --git a/drivers/media/cec/cec-adap.c b/drivers/media/cec/cec-adap.c index 5ef7daeb8cbd..284f9b845161 100644 --- a/drivers/media/cec/cec-adap.c +++ b/drivers/media/cec/cec-adap.c -@@ -1976,7 +1976,7 @@ static int cec_receive_notify(struct cec_adapter *adap, struct cec_msg *msg, +@@ -1990,7 +1990,7 @@ static int cec_receive_notify(struct cec_adapter *adap, struct cec_msg *msg, * Play function, this message can have variable length * depending on the specific play function that is used. */ @@ -1034,7 +1034,7 @@ index 5ef7daeb8cbd..284f9b845161 100644 if (msg->len == 2) rc_keydown(adap->rc, RC_PROTO_CEC, msg->msg[2], 0); -@@ -1993,8 +1993,12 @@ static int cec_receive_notify(struct cec_adapter *adap, struct cec_msg *msg, +@@ -2007,8 +2007,12 @@ static int cec_receive_notify(struct cec_adapter *adap, struct cec_msg *msg, * For the time being these messages are not processed by the * framework and are simply forwarded to the user space. */ @@ -2674,114 +2674,6 @@ index f161f8a493ac..985afea1ee36 100644 } -From 70c8f3b12f466b6a53e88f43f7da12ef04cb4ad2 Mon Sep 17 00:00:00 2001 -From: Douglas Anderson -Date: Thu, 3 Oct 2019 11:47:30 -0700 -Subject: [PATCH] drm/rockchip: Round up _before_ giving to the clock framework - -I'm embarassed to say that even though I've touched -vop_crtc_mode_fixup() twice and I swear I tested it, there's still a -stupid glaring bug in it. Specifically, on veyron_minnie (with all -the latest display timings) we want to be setting our pixel clock to -66,666,666.67 Hz and we tell userspace that's what we set, but we're -actually choosing 66,000,000 Hz. This is confirmed by looking at the -clock tree. - -The problem is that in drm_display_mode_from_videomode() we convert -from Hz to kHz with: - - dmode->clock = vm->pixelclock / 1000; - -...and drm_display_mode_from_videomode() is called from panel-simple -when we have an "override_mode" like we do on veyron_minnie. See -commit 123643e5c40a ("ARM: dts: rockchip: Specify -rk3288-veyron-minnie's display timings"). - -...so when the device tree specifies a clock of 66666667 for the panel -then DRM translates that to 66666000. The clock framework will always -pick a clock that is _lower_ than the one requested, so it will refuse -to pick 66666667 and we'll end up at 66000000. - -While we could try to fix drm_display_mode_from_videomode() to round -to the nearest kHz and it would fix our problem, it wouldn't help if -the clock we actually needed was 60,000,001 Hz. We could -alternatively have DRM always round up, but maybe this would break -someone else who already baked in the assumption that DRM rounds down. -Specifically note that clock drivers are not consistent about whether -they round up or round down when you call clk_set_rate(). We know how -Rockchip's clock driver works, but (for instance) you can see that on -most Qualcomm clocks the default is clk_rcg2_ops which rounds up. - -Let's solve this by just adding 999 Hz before calling -clk_round_rate(). This should be safe and work everywhere. As -discussed in more detail in comments in the commit, Rockchip's PLLs -are configured in a way that there shouldn't be another PLL setting -that is only a few kHz off so we won't get mixed up. - -NOTE: if this is picked to stable, it's probably easiest to first pick -commit 527e4ca3b6d1 ("drm/rockchip: Base adjustments of the mode based -on prev adjustments") which shouldn't hurt in stable. - -Fixes: b59b8de31497 ("drm/rockchip: return a true clock rate to adjusted_mode") -Signed-off-by: Douglas Anderson -Reviewed-by: Sean Paul -Signed-off-by: Sean Paul -Link: https://patchwork.freedesktop.org/patch/msgid/20191003114726.v2.1.Ib233b3e706cf6317858384264d5b0ed35657456e@changeid -(cherry picked from commit 287422a95fe28e05c1952de0472e0dfdffa6caae) ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 37 ++++++++++++++++++++++++++--- - 1 file changed, 34 insertions(+), 3 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 613404f86668..84e3decb17b1 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1040,10 +1040,41 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, - struct drm_display_mode *adjusted_mode) - { - struct vop *vop = to_vop(crtc); -+ unsigned long rate; - -- adjusted_mode->clock = -- DIV_ROUND_UP(clk_round_rate(vop->dclk, -- adjusted_mode->clock * 1000), 1000); -+ /* -+ * Clock craziness. -+ * -+ * Key points: -+ * -+ * - DRM works in in kHz. -+ * - Clock framework works in Hz. -+ * - Rockchip's clock driver picks the clock rate that is the -+ * same _OR LOWER_ than the one requested. -+ * -+ * Action plan: -+ * -+ * 1. When DRM gives us a mode, we should add 999 Hz to it. That way -+ * if the clock we need is 60000001 Hz (~60 MHz) and DRM tells us to -+ * make 60000 kHz then the clock framework will actually give us -+ * the right clock. -+ * -+ * NOTE: if the PLL (maybe through a divider) could actually make -+ * a clock rate 999 Hz higher instead of the one we want then this -+ * could be a problem. Unfortunately there's not much we can do -+ * since it's baked into DRM to use kHz. It shouldn't matter in -+ * practice since Rockchip PLLs are controlled by tables and -+ * even if there is a divider in the middle I wouldn't expect PLL -+ * rates in the table that are just a few kHz different. -+ * -+ * 2. Get the clock framework to round the rate for us to tell us -+ * what it will actually make. -+ * -+ * 3. Store the rounded up rate so that we don't need to worry about -+ * this in the actual clk_set_rate(). -+ */ -+ rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000 + 999); -+ adjusted_mode->clock = DIV_ROUND_UP(rate, 1000); - - return true; - } - From 437d3acd3fdb554710583675d5103f0faf64da28 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 7 Oct 2019 19:21:48 +0000 @@ -13621,27 +13513,3 @@ index 681cb590f952..c6e993e78dbd 100644 + (connector)->possible_encoders) #endif -From a819406b547a71a78fa0a3402e03e795b58a7c04 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jan 2020 10:49:11 +0000 -Subject: [PATCH] Revert "net: stmmac: platform: Fix MDIO init for platforms - without PHY" - -This reverts commit bfdbfd28f76028b960458d107dc4ae9240c928b3. ---- - drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -index 1f230bd854c4..170c3a052b14 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -@@ -320,7 +320,7 @@ static int stmmac_mtl_setup(struct platform_device *pdev, - static int stmmac_dt_phy(struct plat_stmmacenet_data *plat, - struct device_node *np, struct device *dev) - { -- bool mdio = false; -+ bool mdio = true; - static const struct of_device_id need_mdio_ids[] = { - { .compatible = "snps,dwc-qos-ethernet-4.10" }, - {}, diff --git a/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-list.patch index 3f3de75418..36dc5a08e6 100644 --- a/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-list.patch @@ -3169,50 +3169,3 @@ index 9d4d5cc47969..0b34a12c4a1c 100644 /* Vendor PHY support */ const struct dw_hdmi_phy_ops *phy_ops; -From d4cd48f629aa37e58e2e6e1e4323763702c641d0 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 23 Dec 2019 08:49:19 +0000 -Subject: [PATCH] phy/rockchip: inno-hdmi: round clock rate down to closest - 1000 Hz - -Commit 287422a95fe2 ("drm/rockchip: Round up _before_ giving to the clock framework") -changed what rate clk_round_rate() is called with, an additional 999 Hz -added to the requsted mode clock. This has caused a regression on RK3328 -and presumably also on RK3228 because the inno-hdmi-phy clock requires an -exact match of the requested rate in the pre pll config table. - -When an exact match is not found the parent clock rate (24MHz) is returned -to the clk_round_rate() caller. This cause wrong pixel clock to be used and -result in no-signal when configuring a mode on RK3328. - -Fix this by rounding the rate down to closest 1000 Hz in round_rate func, -this allows an exact match to be found in pre pll config table. - -Fixes: 287422a95fe2 ("drm/rockchip: Round up _before_ giving to the clock framework") -Signed-off-by: Jonas Karlman ---- - drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -index 2b97fb1185a0..9ca20c947283 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -@@ -603,6 +603,8 @@ static long inno_hdmi_phy_rk3228_clk_round_rate(struct clk_hw *hw, - { - const struct pre_pll_config *cfg = pre_pll_cfg_table; - -+ rate = (rate / 1000) * 1000; -+ - for (; cfg->pixclock != 0; cfg++) - if (cfg->pixclock == rate && !cfg->fracdiv) - break; -@@ -755,6 +757,8 @@ static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw, - { - const struct pre_pll_config *cfg = pre_pll_cfg_table; - -+ rate = (rate / 1000) * 1000; -+ - for (; cfg->pixclock != 0; cfg++) - if (cfg->pixclock == rate) - break; diff --git a/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-5.5.patch b/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-5.5.patch index d94f96effe..bf014118b9 100644 --- a/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-5.5.patch +++ b/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-5.5.patch @@ -2212,7 +2212,7 @@ diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/ index 0d758e0c0f99..2227b4e12067 100644 --- a/drivers/staging/media/hantro/hantro_h264.c +++ b/drivers/staging/media/hantro/hantro_h264.c -@@ -537,22 +537,18 @@ static void update_dpb(struct hantro_ctx *ctx) +@@ -530,22 +530,18 @@ static void update_dpb(struct hantro_ctx *ctx) } } @@ -2241,7 +2241,7 @@ index 0d758e0c0f99..2227b4e12067 100644 /* * If a DPB entry is unused or invalid, address of current -@@ -560,9 +556,10 @@ struct vb2_buffer *hantro_h264_get_ref_buf(struct hantro_ctx *ctx, +@@ -553,9 +549,10 @@ struct vb2_buffer *hantro_h264_get_ref_buf(struct hantro_ctx *ctx, */ dst_buf = hantro_get_dst_buf(ctx); buf = &dst_buf->vb2_buf; @@ -2348,7 +2348,7 @@ diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/ index 2227b4e12067..648c8a81efa8 100644 --- a/drivers/staging/media/hantro/hantro_h264.c +++ b/drivers/staging/media/hantro/hantro_h264.c -@@ -429,7 +429,7 @@ static int b1_ref_list_cmp(const void *ptra, const void *ptrb, const void *data) +@@ -422,7 +422,7 @@ static int b1_ref_list_cmp(const void *ptra, const void *ptrb, const void *data) /* * Short term pics with POC > cur POC first in POC ascending order @@ -2384,26 +2384,26 @@ index 648c8a81efa8..4557f148583a 100644 +++ b/drivers/staging/media/hantro/hantro_h264.c @@ -22,7 +22,7 @@ #define POC_BUFFER_SIZE 34 - #define SCALING_LIST_SIZE (6 * 16 + 6 * 64) + #define SCALING_LIST_SIZE (6 * 16 + 2 * 64) -#define POC_CMP(p0, p1) ((p0) < (p1) ? -1 : 1) +#define HANTRO_CMP(a, b) ((a) < (b) ? -1 : 1) /* Data structure describing auxiliary buffer format. */ struct hantro_h264_dec_priv_tbl { -@@ -353,9 +353,9 @@ static int p_ref_list_cmp(const void *ptra, const void *ptrb, const void *data) +@@ -346,9 +346,9 @@ static int p_ref_list_cmp(const void *ptra, const void *ptrb, const void *data) * ascending order. */ if (!(a->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)) -- return b->frame_num - a->frame_num; -+ return HANTRO_CMP(b->frame_num, a->frame_num); +- return builder->frame_nums[idxb] - builder->frame_nums[idxa]; ++ return HANTRO_CMP(builder->frame_nums[idxb], builder->frame_nums[idxa]); - return a->pic_num - b->pic_num; + return HANTRO_CMP(a->pic_num, b->pic_num); } static int b0_ref_list_cmp(const void *ptra, const void *ptrb, const void *data) -@@ -381,7 +381,7 @@ static int b0_ref_list_cmp(const void *ptra, const void *ptrb, const void *data) +@@ -374,7 +374,7 @@ static int b0_ref_list_cmp(const void *ptra, const void *ptrb, const void *data) /* Long term pics in ascending pic num order. */ if (a->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) @@ -2412,7 +2412,7 @@ index 648c8a81efa8..4557f148583a 100644 poca = builder->pocs[idxa]; pocb = builder->pocs[idxb]; -@@ -392,11 +392,11 @@ static int b0_ref_list_cmp(const void *ptra, const void *ptrb, const void *data) +@@ -385,11 +385,11 @@ static int b0_ref_list_cmp(const void *ptra, const void *ptrb, const void *data) * order. */ if ((poca < builder->curpoc) != (pocb < builder->curpoc)) @@ -2427,7 +2427,7 @@ index 648c8a81efa8..4557f148583a 100644 } static int b1_ref_list_cmp(const void *ptra, const void *ptrb, const void *data) -@@ -422,7 +422,7 @@ static int b1_ref_list_cmp(const void *ptra, const void *ptrb, const void *data) +@@ -415,7 +415,7 @@ static int b1_ref_list_cmp(const void *ptra, const void *ptrb, const void *data) /* Long term pics in ascending pic num order. */ if (a->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) @@ -2436,7 +2436,7 @@ index 648c8a81efa8..4557f148583a 100644 poca = builder->pocs[idxa]; pocb = builder->pocs[idxb]; -@@ -433,11 +433,11 @@ static int b1_ref_list_cmp(const void *ptra, const void *ptrb, const void *data) +@@ -426,11 +426,11 @@ static int b1_ref_list_cmp(const void *ptra, const void *ptrb, const void *data) * order. */ if ((poca < builder->curpoc) != (pocb < builder->curpoc)) @@ -2452,92 +2452,6 @@ index 648c8a81efa8..4557f148583a 100644 static void -From e4fa0d7dbda0552cdf9a2d4336fda5bdbab3a3d9 Mon Sep 17 00:00:00 2001 -From: Boris Brezillon -Date: Mon, 9 Sep 2019 04:28:15 -0300 -Subject: [PATCH] media: hantro: h264: Fix the frame_num wraparound case - -Step '8.2.4.1 Decoding process for picture numbers' was missing in the -reflist creation logic, leading to invalid P reflists when a -->frame_num wraparound happens. - -Fixes: a9471e25629b ("media: hantro: Add core bits to support H264 decoding") -Reported-by: Francois Buergisser -Signed-off-by: Boris Brezillon -Reviewed-by: Philipp Zabel -Tested-by: Philipp Zabel -Tested-by: Francois Buergisser -Reviewed-by: Tomasz Figa -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab -(cherry picked from commit 9db5f87f6723678a7e7e5e3165439c5c4378edbb) ---- - drivers/staging/media/hantro/hantro_h264.c | 23 ++++++++++++++++++++++- - 1 file changed, 22 insertions(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c -index 4557f148583a..02cbe7761769 100644 ---- a/drivers/staging/media/hantro/hantro_h264.c -+++ b/drivers/staging/media/hantro/hantro_h264.c -@@ -271,6 +271,7 @@ struct hantro_h264_reflist_builder { - const struct v4l2_h264_dpb_entry *dpb; - s32 pocs[HANTRO_H264_DPB_SIZE]; - u8 unordered_reflist[HANTRO_H264_DPB_SIZE]; -+ int frame_nums[HANTRO_H264_DPB_SIZE]; - s32 curpoc; - u8 num_valid; - }; -@@ -294,13 +295,20 @@ static void - init_reflist_builder(struct hantro_ctx *ctx, - struct hantro_h264_reflist_builder *b) - { -+ const struct v4l2_ctrl_h264_slice_params *slice_params; - const struct v4l2_ctrl_h264_decode_params *dec_param; -+ const struct v4l2_ctrl_h264_sps *sps; - struct vb2_v4l2_buffer *buf = hantro_get_dst_buf(ctx); - const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; - struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; -+ int cur_frame_num, max_frame_num; - unsigned int i; - - dec_param = ctx->h264_dec.ctrls.decode; -+ slice_params = &ctx->h264_dec.ctrls.slices[0]; -+ sps = ctx->h264_dec.ctrls.sps; -+ max_frame_num = 1 << (sps->log2_max_frame_num_minus4 + 4); -+ cur_frame_num = slice_params->frame_num; - - memset(b, 0, sizeof(*b)); - b->dpb = dpb; -@@ -318,6 +326,18 @@ init_reflist_builder(struct hantro_ctx *ctx, - continue; - - buf = to_vb2_v4l2_buffer(vb2_get_buffer(cap_q, buf_idx)); -+ -+ /* -+ * Handle frame_num wraparound as described in section -+ * '8.2.4.1 Decoding process for picture numbers' of the spec. -+ * TODO: This logic will have to be adjusted when we start -+ * supporting interlaced content. -+ */ -+ if (dpb[i].frame_num > cur_frame_num) -+ b->frame_nums[i] = (int)dpb[i].frame_num - max_frame_num; -+ else -+ b->frame_nums[i] = dpb[i].frame_num; -+ - b->pocs[i] = get_poc(buf->field, dpb[i].top_field_order_cnt, - dpb[i].bottom_field_order_cnt); - b->unordered_reflist[b->num_valid] = i; -@@ -353,7 +373,8 @@ static int p_ref_list_cmp(const void *ptra, const void *ptrb, const void *data) - * ascending order. - */ - if (!(a->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)) -- return HANTRO_CMP(b->frame_num, a->frame_num); -+ return HANTRO_CMP(builder->frame_nums[idxb], -+ builder->frame_nums[idxa]); - - return HANTRO_CMP(a->pic_num, b->pic_num); - } - From 89451e5248ae441638f9aa115f4d772bbb64f36b Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Tue, 10 Sep 2019 07:20:30 -0300 @@ -11291,7 +11205,7 @@ diff --git a/MAINTAINERS b/MAINTAINERS index 9d3a5c54a41d..3497e493dd6f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -8329,6 +8329,7 @@ S: Maintained +@@ -8330,6 +8330,7 @@ S: Maintained F: drivers/staging/media/ipu3/ F: Documentation/media/uapi/v4l/pixfmt-meta-intel-ipu3.rst F: Documentation/media/v4l-drivers/ipu3.rst @@ -12596,147 +12510,6 @@ index a1209f68c5e8..28313c0f4e7c 100644 ``V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS (struct)`` Specifies the slice parameters (as extracted from the bitstream) -From 4556c1fba4fad8164aa32ee2bc49c2db6d60af4c Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 29 Oct 2019 01:00:52 +0100 -Subject: [PATCH] media: cedrus: Use correct H264 8x8 scaling list - -Documentation now defines the expected order of scaling lists, -change to use correct indices. - -Fixes: 6eb9b758e307 ("media: cedrus: Add H264 decoding support") -Signed-off-by: Jonas Karlman -Reviewed-by: Philipp Zabel -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab -(cherry picked from commit a6b8feae7c88343212686120740cf7551dd16e08) ---- - drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -index 7487f6ab7576..74e4c5e3894e 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -@@ -245,8 +245,8 @@ static void cedrus_write_scaling_lists(struct cedrus_ctx *ctx, - sizeof(scaling->scaling_list_8x8[0])); - - cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_8x8_1, -- scaling->scaling_list_8x8[3], -- sizeof(scaling->scaling_list_8x8[3])); -+ scaling->scaling_list_8x8[1], -+ sizeof(scaling->scaling_list_8x8[1])); - - cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_4x4, - scaling->scaling_list_4x4, - -From 0a4e67064ec7a5e5f0567d9ee64bc0dff9594faa Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Tue, 29 Oct 2019 01:00:53 +0100 -Subject: [PATCH] media: hantro: Do not reorder H264 scaling list - -Scaling list supplied from userspace should be in matrix order -and can be used without applying the inverse scanning process. - -The HW also only support 8x8 scaling list for the Y component, indices 0 -and 1 in the scaling list supplied from userspace. - -Remove reordering and write the scaling matrix in an order expected by -the VPU, also only allocate memory for the two 8x8 lists supported. - -Fixes: a9471e25629b ("media: hantro: Add core bits to support H264 decoding") -Signed-off-by: Jonas Karlman -Reviewed-by: Philipp Zabel -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab -(cherry picked from commit e17f08e3166635d2eaa6a894afeb28ca651ddd35) ---- - drivers/staging/media/hantro/hantro_h264.c | 51 +++++++----------------------- - 1 file changed, 12 insertions(+), 39 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c -index 02cbe7761769..694a330f508e 100644 ---- a/drivers/staging/media/hantro/hantro_h264.c -+++ b/drivers/staging/media/hantro/hantro_h264.c -@@ -20,7 +20,7 @@ - /* Size with u32 units. */ - #define CABAC_INIT_BUFFER_SIZE (460 * 2) - #define POC_BUFFER_SIZE 34 --#define SCALING_LIST_SIZE (6 * 16 + 6 * 64) -+#define SCALING_LIST_SIZE (6 * 16 + 2 * 64) - - #define HANTRO_CMP(a, b) ((a) < (b) ? -1 : 1) - -@@ -194,23 +194,6 @@ static const u32 h264_cabac_table[] = { - 0x1f0c2517, 0x1f261440 - }; - --/* -- * NOTE: The scaling lists are in zig-zag order, apply inverse scanning process -- * to get the values in matrix order. In addition, the hardware requires bytes -- * swapped within each subsequent 4 bytes. Both arrays below include both -- * transformations. -- */ --static const u32 zig_zag_4x4[] = { -- 3, 2, 7, 11, 6, 1, 0, 5, 10, 15, 14, 9, 4, 8, 13, 12 --}; -- --static const u32 zig_zag_8x8[] = { -- 3, 2, 11, 19, 10, 1, 0, 9, 18, 27, 35, 26, 17, 8, 7, 6, -- 15, 16, 25, 34, 43, 51, 42, 33, 24, 23, 14, 5, 4, 13, 22, 31, -- 32, 41, 50, 59, 58, 49, 40, 39, 30, 21, 12, 20, 29, 38, 47, 48, -- 57, 56, 55, 46, 37, 28, 36, 45, 54, 63, 62, 53, 44, 52, 61, 60 --}; -- - static void - reorder_scaling_list(struct hantro_ctx *ctx) - { -@@ -218,33 +201,23 @@ reorder_scaling_list(struct hantro_ctx *ctx) - const struct v4l2_ctrl_h264_scaling_matrix *scaling = ctrls->scaling; - const size_t num_list_4x4 = ARRAY_SIZE(scaling->scaling_list_4x4); - const size_t list_len_4x4 = ARRAY_SIZE(scaling->scaling_list_4x4[0]); -- const size_t num_list_8x8 = ARRAY_SIZE(scaling->scaling_list_8x8); - const size_t list_len_8x8 = ARRAY_SIZE(scaling->scaling_list_8x8[0]); - struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu; -- u8 *dst = tbl->scaling_list; -- const u8 *src; -+ u32 *dst = (u32 *)tbl->scaling_list; -+ const u32 *src; - int i, j; - -- BUILD_BUG_ON(ARRAY_SIZE(zig_zag_4x4) != list_len_4x4); -- BUILD_BUG_ON(ARRAY_SIZE(zig_zag_8x8) != list_len_8x8); -- BUILD_BUG_ON(ARRAY_SIZE(tbl->scaling_list) != -- num_list_4x4 * list_len_4x4 + -- num_list_8x8 * list_len_8x8); -- -- src = &scaling->scaling_list_4x4[0][0]; -- for (i = 0; i < num_list_4x4; ++i) { -- for (j = 0; j < list_len_4x4; ++j) -- dst[zig_zag_4x4[j]] = src[j]; -- src += list_len_4x4; -- dst += list_len_4x4; -+ for (i = 0; i < num_list_4x4; i++) { -+ src = (u32 *)&scaling->scaling_list_4x4[i]; -+ for (j = 0; j < list_len_4x4 / 4; j++) -+ *dst++ = swab32(src[j]); - } - -- src = &scaling->scaling_list_8x8[0][0]; -- for (i = 0; i < num_list_8x8; ++i) { -- for (j = 0; j < list_len_8x8; ++j) -- dst[zig_zag_8x8[j]] = src[j]; -- src += list_len_8x8; -- dst += list_len_8x8; -+ /* Only Intra/Inter Y lists */ -+ for (i = 0; i < 2; i++) { -+ src = (u32 *)&scaling->scaling_list_8x8[i]; -+ for (j = 0; j < list_len_8x8 / 4; j++) -+ *dst++ = swab32(src[j]); - } - } - - From b82abc83697c975959f82f4f0b41762d9c7195da Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Tue, 29 Oct 2019 02:24:47 +0100 @@ -12981,112 +12754,6 @@ index 1349be188a5b..cd6b55433c9e 100644 /* Get the next device in the pipeline */ if (is_media_entity_v4l2_subdev(entity)) { -From 6587305b01463222d6eecbfa704a36d567de6a20 Mon Sep 17 00:00:00 2001 -From: Hans Verkuil -Date: Sun, 10 Nov 2019 07:27:04 +0100 -Subject: [PATCH] media: v4l2-ioctl.c: zero reserved fields for S/TRY_FMT - -v4l2_vbi_format, v4l2_sliced_vbi_format and v4l2_sdr_format -have a reserved array at the end that should be zeroed by drivers -as per the V4L2 spec. Older drivers often do not do this, so just -handle this in the core. - -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab -(cherry picked from commit ee8951e56c0f960b9621636603a822811cef3158) ---- - drivers/media/v4l2-core/v4l2-ioctl.c | 24 ++++++++++++------------ - 1 file changed, 12 insertions(+), 12 deletions(-) - -diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 60453b21a855..4e700583659b 100644 ---- a/drivers/media/v4l2-core/v4l2-ioctl.c -+++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1617,12 +1617,12 @@ static int v4l_s_fmt(const struct v4l2_ioctl_ops *ops, - case V4L2_BUF_TYPE_VBI_CAPTURE: - if (unlikely(!ops->vidioc_s_fmt_vbi_cap)) - break; -- CLEAR_AFTER_FIELD(p, fmt.vbi); -+ CLEAR_AFTER_FIELD(p, fmt.vbi.flags); - return ops->vidioc_s_fmt_vbi_cap(file, fh, arg); - case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: - if (unlikely(!ops->vidioc_s_fmt_sliced_vbi_cap)) - break; -- CLEAR_AFTER_FIELD(p, fmt.sliced); -+ CLEAR_AFTER_FIELD(p, fmt.sliced.io_size); - return ops->vidioc_s_fmt_sliced_vbi_cap(file, fh, arg); - case V4L2_BUF_TYPE_VIDEO_OUTPUT: - if (unlikely(!ops->vidioc_s_fmt_vid_out)) -@@ -1648,22 +1648,22 @@ static int v4l_s_fmt(const struct v4l2_ioctl_ops *ops, - case V4L2_BUF_TYPE_VBI_OUTPUT: - if (unlikely(!ops->vidioc_s_fmt_vbi_out)) - break; -- CLEAR_AFTER_FIELD(p, fmt.vbi); -+ CLEAR_AFTER_FIELD(p, fmt.vbi.flags); - return ops->vidioc_s_fmt_vbi_out(file, fh, arg); - case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: - if (unlikely(!ops->vidioc_s_fmt_sliced_vbi_out)) - break; -- CLEAR_AFTER_FIELD(p, fmt.sliced); -+ CLEAR_AFTER_FIELD(p, fmt.sliced.io_size); - return ops->vidioc_s_fmt_sliced_vbi_out(file, fh, arg); - case V4L2_BUF_TYPE_SDR_CAPTURE: - if (unlikely(!ops->vidioc_s_fmt_sdr_cap)) - break; -- CLEAR_AFTER_FIELD(p, fmt.sdr); -+ CLEAR_AFTER_FIELD(p, fmt.sdr.buffersize); - return ops->vidioc_s_fmt_sdr_cap(file, fh, arg); - case V4L2_BUF_TYPE_SDR_OUTPUT: - if (unlikely(!ops->vidioc_s_fmt_sdr_out)) - break; -- CLEAR_AFTER_FIELD(p, fmt.sdr); -+ CLEAR_AFTER_FIELD(p, fmt.sdr.buffersize); - return ops->vidioc_s_fmt_sdr_out(file, fh, arg); - case V4L2_BUF_TYPE_META_CAPTURE: - if (unlikely(!ops->vidioc_s_fmt_meta_cap)) -@@ -1719,12 +1719,12 @@ static int v4l_try_fmt(const struct v4l2_ioctl_ops *ops, - case V4L2_BUF_TYPE_VBI_CAPTURE: - if (unlikely(!ops->vidioc_try_fmt_vbi_cap)) - break; -- CLEAR_AFTER_FIELD(p, fmt.vbi); -+ CLEAR_AFTER_FIELD(p, fmt.vbi.flags); - return ops->vidioc_try_fmt_vbi_cap(file, fh, arg); - case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: - if (unlikely(!ops->vidioc_try_fmt_sliced_vbi_cap)) - break; -- CLEAR_AFTER_FIELD(p, fmt.sliced); -+ CLEAR_AFTER_FIELD(p, fmt.sliced.io_size); - return ops->vidioc_try_fmt_sliced_vbi_cap(file, fh, arg); - case V4L2_BUF_TYPE_VIDEO_OUTPUT: - if (unlikely(!ops->vidioc_try_fmt_vid_out)) -@@ -1750,22 +1750,22 @@ static int v4l_try_fmt(const struct v4l2_ioctl_ops *ops, - case V4L2_BUF_TYPE_VBI_OUTPUT: - if (unlikely(!ops->vidioc_try_fmt_vbi_out)) - break; -- CLEAR_AFTER_FIELD(p, fmt.vbi); -+ CLEAR_AFTER_FIELD(p, fmt.vbi.flags); - return ops->vidioc_try_fmt_vbi_out(file, fh, arg); - case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: - if (unlikely(!ops->vidioc_try_fmt_sliced_vbi_out)) - break; -- CLEAR_AFTER_FIELD(p, fmt.sliced); -+ CLEAR_AFTER_FIELD(p, fmt.sliced.io_size); - return ops->vidioc_try_fmt_sliced_vbi_out(file, fh, arg); - case V4L2_BUF_TYPE_SDR_CAPTURE: - if (unlikely(!ops->vidioc_try_fmt_sdr_cap)) - break; -- CLEAR_AFTER_FIELD(p, fmt.sdr); -+ CLEAR_AFTER_FIELD(p, fmt.sdr.buffersize); - return ops->vidioc_try_fmt_sdr_cap(file, fh, arg); - case V4L2_BUF_TYPE_SDR_OUTPUT: - if (unlikely(!ops->vidioc_try_fmt_sdr_out)) - break; -- CLEAR_AFTER_FIELD(p, fmt.sdr); -+ CLEAR_AFTER_FIELD(p, fmt.sdr.buffersize); - return ops->vidioc_try_fmt_sdr_out(file, fh, arg); - case V4L2_BUF_TYPE_META_CAPTURE: - if (unlikely(!ops->vidioc_try_fmt_meta_cap)) - From 538378c5a4b78d449f2a4003fd0bf51941aea310 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 10 Nov 2019 07:30:01 +0100 @@ -13719,7 +13386,7 @@ diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/ index 694a330f508e..568640eab3a6 100644 --- a/drivers/staging/media/hantro/hantro_h264.c +++ b/drivers/staging/media/hantro/hantro_h264.c -@@ -618,7 +618,6 @@ int hantro_h264_dec_init(struct hantro_ctx *ctx) +@@ -617,7 +617,6 @@ int hantro_h264_dec_init(struct hantro_ctx *ctx) struct hantro_h264_dec_hw_ctx *h264_dec = &ctx->h264_dec; struct hantro_aux_buf *priv = &h264_dec->priv; struct hantro_h264_dec_priv_tbl *tbl; @@ -13727,7 +13394,7 @@ index 694a330f508e..568640eab3a6 100644 priv->cpu = dma_alloc_coherent(vpu->dev, sizeof(*tbl), &priv->dma, GFP_KERNEL); -@@ -629,9 +628,5 @@ int hantro_h264_dec_init(struct hantro_ctx *ctx) +@@ -628,9 +627,5 @@ int hantro_h264_dec_init(struct hantro_ctx *ctx) tbl = priv->cpu; memcpy(tbl->cabac_table, h264_cabac_table, sizeof(tbl->cabac_table)); @@ -13758,37 +13425,3 @@ index 69b88f4d3fb3..fa91dd1848b7 100644 /** -From 06e06be61b0e2edab79c115acc2bb6b401c1cbcb Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Wed, 6 Nov 2019 23:35:11 +0100 -Subject: [PATCH] media: hantro: Set H264 FIELDPIC_FLAG_E flag correctly - -The FIELDPIC_FLAG_E bit should be set when field_pic_flag exists in stream, -it is currently set based on field_pic_flag of current frame. -The PIC_FIELDMODE_E bit is correctly set based on the field_pic_flag. - -Fix this by setting the FIELDPIC_FLAG_E bit when frame_mbs_only is not set. - -Fixes: dea0a82f3d22 ("media: hantro: Add support for H264 decoding on G1") -Signed-off-by: Jonas Karlman -Reviewed-by: Boris Brezillon -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab -(cherry picked from commit a2cbf80a842add9663522bf898cf13cb2ac4e423) ---- - drivers/staging/media/hantro/hantro_g1_h264_dec.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c -index 27d40d8d3728..3cd40a8f0daa 100644 ---- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c -+++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c -@@ -63,7 +63,7 @@ static void set_params(struct hantro_ctx *ctx) - /* always use the matrix sent from userspace */ - reg |= G1_REG_DEC_CTRL2_TYPE1_QUANT_E; - -- if (slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) -+ if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)) - reg |= G1_REG_DEC_CTRL2_FIELDPIC_FLAG_E; - vdpu_write_relaxed(vpu, reg, G1_REG_DEC_CTRL2); - From 3951a496e9280028c0edfca11e856f2cd4532862 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 1 Feb 2020 01:05:50 +0000 Subject: [PATCH 2/3] linux (Rockchip): update config for 5.4.16 --- projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf | 3 ++- .../Rockchip/devices/RK3328/linux/default/linux.aarch64.conf | 3 ++- .../Rockchip/devices/RK3399/linux/default/linux.aarch64.conf | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf index e95a1e18dd..d324008d3d 100644 --- a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf +++ b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.4.0 Kernel Configuration +# Linux/arm 5.4.16 Kernel Configuration # CONFIG_CC_IS_GCC=y @@ -635,6 +635,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_HAVE_COPY_THREAD_TLS=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_OLD_SIGACTION=y diff --git a/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf index 8a5e57ea6c..c423abb67f 100644 --- a/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.4.0 Kernel Configuration +# Linux/arm64 5.4.16 Kernel Configuration # CONFIG_CC_IS_GCC=y @@ -594,6 +594,7 @@ CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_HAVE_COPY_THREAD_TLS=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_COMPAT_OLD_SIGACTION=y diff --git a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf index d0233428fe..65bae0ddf4 100644 --- a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.4.0 Kernel Configuration +# Linux/arm64 5.4.16 Kernel Configuration # CONFIG_CC_IS_GCC=y @@ -594,6 +594,7 @@ CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_HAVE_COPY_THREAD_TLS=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_COMPAT_OLD_SIGACTION=y From 21a7af1848b34c4fdc95371dfc74b768fd253e3f Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 1 Feb 2020 01:05:50 +0000 Subject: [PATCH 3/3] Rockchip: update debug commands --- projects/Rockchip/README.md | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/projects/Rockchip/README.md b/projects/Rockchip/README.md index 5e9c7c4ef2..183eb4f695 100644 --- a/projects/Rockchip/README.md +++ b/projects/Rockchip/README.md @@ -34,9 +34,11 @@ You may have luck if your device vendor is open source friendly, otherwise keep ## Useful debug commands -* `cat /sys/kernel/debug/dri/0/summary` -* `cat /sys/kernel/debug/dw-hdmi/status` -* `cat /sys/kernel/debug/clk/clk_summary` +* `cat /sys/kernel/debug/dri/0/state` +* `cat /sys/kernel/debug/dri/0/framebuffer` +* `cat /sys/kernel/debug/dma_buf/bufinfo` +* `cat /sys/kernel/debug/cec/cec0/status` * `hexdump -C /sys/class/drm/card0-HDMI-A-1/edid` * `edid-decode /sys/class/drm/card0-HDMI-A-1/edid` -* `cat /sys/kernel/debug/dma_buf/bufinfo` +* `cat /sys/kernel/debug/clk/clk_summary` +* `cat /sys/kernel/debug/regulator/regulator_summary`