From 08b43d0651fb40d988ede3912a3c6b98ddaf998d Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 4 Mar 2018 15:57:07 +0100 Subject: [PATCH] u-boot: add patch for odroid-n1 --- ...0007-board-add-support-for-odroid-n1.patch | 1069 +++++++++++++++++ 1 file changed, 1069 insertions(+) create mode 100644 packages/tools/u-boot/patches/rockchip/u-boot-0007-board-add-support-for-odroid-n1.patch diff --git a/packages/tools/u-boot/patches/rockchip/u-boot-0007-board-add-support-for-odroid-n1.patch b/packages/tools/u-boot/patches/rockchip/u-boot-0007-board-add-support-for-odroid-n1.patch new file mode 100644 index 0000000000..a5eae75712 --- /dev/null +++ b/packages/tools/u-boot/patches/rockchip/u-boot-0007-board-add-support-for-odroid-n1.patch @@ -0,0 +1,1069 @@ +From 018af92e85f8526dbfc7b70d5cd1a7529b79d03e Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Fri, 16 Feb 2018 22:45:25 +0000 +Subject: [PATCH] board: add support for odroid-n1 + +--- + arch/arm/dts/rk3399-odroidn1.dts | 601 ++++++++++++++++++++++++++++++++++ + arch/arm/mach-rockchip/rk3399/Kconfig | 7 + + board/rockchip/odroidn1/Kconfig | 15 + + board/rockchip/odroidn1/MAINTAINERS | 6 + + board/rockchip/odroidn1/Makefile | 7 + + board/rockchip/odroidn1/odroidn1.c | 225 +++++++++++++ + configs/odroidn1_defconfig | 97 ++++++ + include/configs/odroidn1.h | 28 ++ + 8 files changed, 986 insertions(+) + create mode 100644 arch/arm/dts/rk3399-odroidn1.dts + create mode 100644 board/rockchip/odroidn1/Kconfig + create mode 100644 board/rockchip/odroidn1/MAINTAINERS + create mode 100644 board/rockchip/odroidn1/Makefile + create mode 100644 board/rockchip/odroidn1/odroidn1.c + create mode 100644 configs/odroidn1_defconfig + create mode 100644 include/configs/odroidn1.h + +diff --git a/arch/arm/dts/rk3399-odroidn1.dts b/arch/arm/dts/rk3399-odroidn1.dts +new file mode 100644 +index 0000000000..aa653d6fc6 +--- /dev/null ++++ b/arch/arm/dts/rk3399-odroidn1.dts +@@ -0,0 +1,601 @@ ++/* ++ * Copyright (c) 2017 Hardkernel Co., Ltd. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include "rk3399.dtsi" ++#include "rk3399-sdram-ddr3-1600.dtsi" ++ ++/ { ++ model = "Hardkernel ODROID-N1"; ++ compatible = "hardkernel,odroid-n1", "rockchip,rk3399"; ++ ++ chosen { ++ stdout-path = &uart2; ++ u-boot,spl-boot-order = &sdmmc, &sdhci; ++ }; ++ ++ clkin_gmac: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "clkin_gmac"; ++ #clock-cells = <0>; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk808 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_enable_h>; ++ ++ /* ++ * On the module itself this is one of these (depending ++ * on the actual card populated): ++ * - SDIO_RESET_L_WL_REG_ON ++ * - PDN (power down when low) ++ */ ++ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; ++ }; ++ ++ vcc5v0_host31: vcc5v0-host31-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&host31_vbus_drv>; ++ regulator-name = "vcc5v0_host31"; ++ }; ++ ++ vcc5v0_host32: vcc5v0-host32-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&host32_vbus_drv>; ++ regulator-name = "vcc5v0_host32"; ++ }; ++ ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_drv>; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ vcc5v0_host: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&host_vbus_drv>; ++ regulator-name = "vcc5v0_host"; ++ regulator-always-on; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc_phy: vcc-phy-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_phy"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vdd_log: vdd-log { ++ compatible = "pwm-regulator"; ++ pwms = <&pwm2 0 25000 1>; ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <430000>; ++ regulator-max-microvolt = <1400000>; ++ regulator-init-microvolt = <950000>; ++ }; ++ ++ vccadc_ref: vccadc-ref { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc1v8_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&gmac { ++ assigned-clocks = <&cru SCLK_RMII_SRC>; ++ assigned-clock-parents = <&clkin_gmac>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc_phy>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>; ++ snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ tx_delay = <0x100>; ++ rx_delay = <0x11>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ clock-frequency = <400000>; ++ i2c-scl-rising-time-ns = <168>; ++ i2c-scl-falling-time-ns = <4>; ++ status = "okay"; ++ ++ rk808: pmic@1b { ++ compatible = "rockchip,rk808"; ++ reg = <0x1b>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <23 IRQ_TYPE_LEVEL_LOW>; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk808-clkout2"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ vcc10-supply = <&vcc3v3_sys>; ++ vcc11-supply = <&vcc3v3_sys>; ++ vcc12-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc1v8_pmu>; ++ ++ regulators { ++ vdd_center: DCDC_REG1 { ++ regulator-name = "vdd_center"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_l: DCDC_REG2 { ++ regulator-name = "vdd_cpu_l"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG4 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc1v8_dvp: LDO_REG1 { ++ regulator-name = "vcc1v8_dvp"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v0_tp: LDO_REG2 { ++ regulator-name = "vcc3v0_tp"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_pmu: LDO_REG3 { ++ regulator-name = "vcc1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_sd: LDO_REG4 { ++ regulator-name = "vcc_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca3v0_codec: LDO_REG5 { ++ regulator-name = "vcca3v0_codec"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-name = "vcc_1v5"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1500000>; ++ }; ++ }; ++ ++ vcca1v8_codec: LDO_REG7 { ++ regulator-name = "vcca1v8_codec"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG8 { ++ regulator-name = "vcc_3v0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc3v3_s3: SWITCH_REG1 { ++ regulator-name = "vcc3v3_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG2 { ++ regulator-name = "vcc3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ vdd_cpu_b: regulator@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <0>; ++ regulator-name = "vdd_cpu_b"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_gpu"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ i2c-scl-rising-time-ns = <300>; ++ i2c-scl-falling-time-ns = <15>; ++ status = "okay"; ++}; ++ ++&i2c3 { ++ i2c-scl-rising-time-ns = <450>; ++ i2c-scl-falling-time-ns = <15>; ++ status = "okay"; ++}; ++ ++&i2c4 { ++ i2c-scl-rising-time-ns = <600>; ++ i2c-scl-falling-time-ns = <20>; ++ status = "okay"; ++}; ++ ++&i2s0 { ++ rockchip,playback-channels = <8>; ++ rockchip,capture-channels = <8>; ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ ++&i2s1 { ++ rockchip,playback-channels = <2>; ++ rockchip,capture-channels = <2>; ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ ++&i2s2 { ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ ++&io_domains { ++ status = "okay"; ++ ++ bt656-supply = <&vcc1v8_dvp>; ++ audio-supply = <&vcca1v8_codec>; ++ sdmmc-supply = <&vcc_sd>; ++ gpio1830-supply = <&vcc_3v0>; ++}; ++ ++&pcie_phy { ++ status = "okay"; ++}; ++ ++&pcie0 { ++ ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; ++ num-lanes = <4>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_clkreqn>; ++ status = "okay"; ++}; ++ ++&pmu_io_domains { ++ pmu1830-supply = <&vcc_3v0>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ buttons { ++ pwrbtn: pwrbtn { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pcie { ++ pcie_drv: pcie-drv { ++ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ vsel1_gpio: vsel1-gpio { ++ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ vsel2_gpio: vsel2-gpio { ++ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ sdio-pwrseq { ++ wifi_enable_h: wifi-enable-h { ++ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb2 { ++ host_vbus_drv: host-vbus-drv { ++ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ host31_vbus_drv: host31-vbus-drv { ++ rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ host32_vbus_drv: host32-vbus-drv { ++ rockchip,pins = <0 13 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm0 { ++ status = "okay"; ++}; ++ ++&pwm2 { ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vccadc_ref>; ++ status = "okay"; ++}; ++ ++&sdmmc { ++ u-boot,dm-pre-reloc; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ keep-power-in-suspend; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ non-removable; ++ status = "okay"; ++}; ++ ++&tsadc { ++ /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-mode = <1>; ++ /* tshut polarity 0:LOW 1:HIGH */ ++ rockchip,hw-tshut-polarity = <1>; ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++ ++ u2phy0_otg: otg-port { ++ phy-supply = <&vcc5v0_host31>; ++ status = "okay"; ++ }; ++ ++ u2phy0_host: host-port { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++ }; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++ ++ u2phy1_otg: otg-port { ++ phy-supply = <&vcc5v0_host32>; ++ status = "okay"; ++ }; ++ ++ u2phy1_host: host-port { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++ }; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&dwc3_typec0 { ++ status = "okay"; ++}; ++ ++&dwc3_typec1 { ++ status = "okay"; ++}; +diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig +index c4a6d46649..c17c839a6a 100644 +--- a/arch/arm/mach-rockchip/rk3399/Kconfig ++++ b/arch/arm/mach-rockchip/rk3399/Kconfig +@@ -11,6 +11,12 @@ config TARGET_EVB_RK3399 + with full function and phisical connectors support like type-C ports, + usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial... + ++config TARGET_ODROIDN1 ++ bool "Hardkernel ODROID-N1 board" ++ select BOARD_LATE_INIT ++ help ++ ODROID-N1 support ++ + config TARGET_PUMA_RK3399 + bool "Theobroma Systems RK3399-Q7 (Puma)" + help +@@ -38,6 +44,7 @@ config SYS_MALLOC_F_LEN + default 0x0800 + + source "board/rockchip/evb_rk3399/Kconfig" ++source "board/rockchip/odroidn1/Kconfig" + source "board/theobroma-systems/puma_rk3399/Kconfig" + + endif +diff --git a/board/rockchip/odroidn1/Kconfig b/board/rockchip/odroidn1/Kconfig +new file mode 100644 +index 0000000000..54744010d6 +--- /dev/null ++++ b/board/rockchip/odroidn1/Kconfig +@@ -0,0 +1,15 @@ ++if TARGET_ODROIDN1 ++ ++config SYS_BOARD ++ default "odroidn1" ++ ++config SYS_VENDOR ++ default "rockchip" ++ ++config SYS_CONFIG_NAME ++ default "odroidn1" ++ ++config BOARD_SPECIFIC_OPTIONS # dummy ++ def_bool y ++ ++endif +diff --git a/board/rockchip/odroidn1/MAINTAINERS b/board/rockchip/odroidn1/MAINTAINERS +new file mode 100644 +index 0000000000..a7f83c3283 +--- /dev/null ++++ b/board/rockchip/odroidn1/MAINTAINERS +@@ -0,0 +1,6 @@ ++ODROIDN1 ++M: Mauro Ribeiro ++S: Maintained ++F: board/rockchip/odroidn1 ++F: include/configs/odroidn1.h ++F: configs/odroidn1_defconfig +diff --git a/board/rockchip/odroidn1/Makefile b/board/rockchip/odroidn1/Makefile +new file mode 100644 +index 0000000000..bad5e036ac +--- /dev/null ++++ b/board/rockchip/odroidn1/Makefile +@@ -0,0 +1,7 @@ ++# ++# (C) Copyright 2017 Hardkernel Co., Ltd ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++obj-y += odroidn1.o +diff --git a/board/rockchip/odroidn1/odroidn1.c b/board/rockchip/odroidn1/odroidn1.c +new file mode 100644 +index 0000000000..713d076824 +--- /dev/null ++++ b/board/rockchip/odroidn1/odroidn1.c +@@ -0,0 +1,225 @@ ++/* ++ * (C) Copyright 2017 Hardkernel Co., Ltd ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define RK3399_CPUID_OFF 0x7 ++#define RK3399_CPUID_LEN 0x10 ++ ++int board_init(void) ++{ ++ struct udevice *pinctrl, *regulator; ++ int ret; ++ ++ /* ++ * The PWM do not have decicated interrupt number in dts and can ++ * not get periph_id by pinctrl framework, so let's init them here. ++ * The PWM2 and PWM3 are for pwm regulater. ++ */ ++ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); ++ if (ret) { ++ debug("%s: Cannot find pinctrl device\n", __func__); ++ goto out; ++ } ++ ++ /* Enable pwm0 for panel backlight */ ++ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM0); ++ if (ret) { ++ debug("%s PWM0 pinctrl init fail! (ret=%d)\n", __func__, ret); ++ goto out; ++ } ++ ++ /* Enable pwm2 to control regulator vdd-log */ ++ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2); ++ if (ret) { ++ debug("%s PWM2 pinctrl init fail!\n", __func__); ++ goto out; ++ } ++ ++ ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM3); ++ if (ret) { ++ debug("%s PWM3 pinctrl init fail!\n", __func__); ++ goto out; ++ } ++ ++ ret = regulators_enable_boot_on(false); ++ if (ret) ++ debug("%s: Cannot enable boot on regulator\n", __func__); ++ ++ ret = regulator_get_by_platname("vcc5v0_host", ®ulator); ++ if (ret) { ++ debug("%s vcc5v0_host init fail! ret %d\n", __func__, ret); ++ goto out; ++ } ++ ++ ret = regulator_set_enable(regulator, true); ++ if (ret) { ++ debug("%s vcc5v0-host-en set fail!\n", __func__); ++ goto out; ++ } ++ ++ /* Enable regulator vdd_log to supply LOGIC_VDD on ODROID-N1 HW */ ++ ret = regulator_get_by_platname("vdd_log", ®ulator); ++ if (ret) { ++ printf("%s vdd_log init fail! ret %d\n", __func__, ret); ++ goto out; ++ } ++ ++ ret = regulator_set_enable(regulator, true); ++ if (ret) { ++ printf("%s vdd_log set fail!\n", __func__); ++ goto out; ++ } ++ ++out: ++ return 0; ++} ++ ++static void setup_macaddr(void) ++{ ++#if CONFIG_IS_ENABLED(CMD_NET) ++ int ret; ++ const char *cpuid = env_get("cpuid#"); ++ u8 hash[SHA256_SUM_LEN]; ++ int size = sizeof(hash); ++ u8 mac_addr[6]; ++ ++ /* Only generate a MAC address, if none is set in the environment */ ++ if (env_get("ethaddr")) ++ return; ++ ++ if (!cpuid) { ++ debug("%s: could not retrieve 'cpuid#'\n", __func__); ++ return; ++ } ++ ++ ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); ++ if (ret) { ++ debug("%s: failed to calculate SHA256\n", __func__); ++ return; ++ } ++ ++ /* Copy 6 bytes of the hash to base the MAC address on */ ++ memcpy(mac_addr, hash, 6); ++ ++ /* Make this a valid MAC address and set it */ ++ mac_addr[0] &= 0xfe; /* clear multicast bit */ ++ mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ ++ eth_env_set_enetaddr("ethaddr", mac_addr); ++#endif ++ ++ return; ++} ++ ++static void setup_serial(void) ++{ ++#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE) ++ struct udevice *dev; ++ int ret, i; ++ u8 cpuid[RK3399_CPUID_LEN]; ++ u8 low[RK3399_CPUID_LEN/2], high[RK3399_CPUID_LEN/2]; ++ char cpuid_str[RK3399_CPUID_LEN * 2 + 1]; ++ u64 serialno; ++ char serialno_str[16]; ++ ++ /* retrieve the device */ ++ ret = uclass_get_device_by_driver(UCLASS_MISC, ++ DM_GET_DRIVER(rockchip_efuse), &dev); ++ if (ret) { ++ debug("%s: could not find efuse device\n", __func__); ++ return; ++ } ++ ++ /* read the cpu_id range from the efuses */ ++ ret = misc_read(dev, RK3399_CPUID_OFF, &cpuid, sizeof(cpuid)); ++ if (ret) { ++ debug("%s: reading cpuid from the efuses failed\n", ++ __func__); ++ return; ++ } ++ ++ memset(cpuid_str, 0, sizeof(cpuid_str)); ++ for (i = 0; i < 16; i++) ++ sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); ++ ++ debug("cpuid: %s\n", cpuid_str); ++ ++ /* ++ * Mix the cpuid bytes using the same rules as in ++ * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c ++ */ ++ for (i = 0; i < 8; i++) { ++ low[i] = cpuid[1 + (i << 1)]; ++ high[i] = cpuid[i << 1]; ++ } ++ ++ serialno = crc32_no_comp(0, low, 8); ++ serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; ++ snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); ++ ++ env_set("cpuid#", cpuid_str); ++ env_set("serial#", serialno_str); ++#endif ++ ++ return; ++} ++ ++int misc_init_r(void) ++{ ++ setup_serial(); ++ setup_macaddr(); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_SERIAL_TAG ++void get_board_serial(struct tag_serialnr *serialnr) ++{ ++ char *serial_string; ++ u64 serial = 0; ++ ++ serial_string = env_get("serial#"); ++ ++ if (serial_string) ++ serial = simple_strtoull(serial_string, NULL, 16); ++ ++ serialnr->high = (u32)(serial >> 32); ++ serialnr->low = (u32)(serial & 0xffffffff); ++} ++#endif ++ ++#ifdef CONFIG_USB_DWC3 ++static struct dwc3_device dwc3_device_data = { ++ .maximum_speed = USB_SPEED_HIGH, ++ .base = 0xfe800000, ++ .dr_mode = USB_DR_MODE_HOST, ++ .index = 0, ++ .dis_u2_susphy_quirk = 1, ++}; ++ ++int usb_gadget_handle_interrupts(void) ++{ ++ dwc3_uboot_handle_interrupt(0); ++ return 0; ++} ++ ++int board_usb_init(int index, enum usb_init_type init) ++{ ++ return dwc3_uboot_init(&dwc3_device_data); ++} ++#endif +diff --git a/configs/odroidn1_defconfig b/configs/odroidn1_defconfig +new file mode 100644 +index 0000000000..ee3a345181 +--- /dev/null ++++ b/configs/odroidn1_defconfig +@@ -0,0 +1,97 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_ROCKCHIP_RK3399=y ++CONFIG_TARGET_ODROIDN1=y ++CONFIG_SPL_STACK_R_ADDR=0x80000 ++CONFIG_DEFAULT_DEVICE_TREE="rk3399-odroidn1" ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_SPL_FIT_GENERATOR="board/rockchip/evb_rk3399/mk_fit_atf.sh" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_ANDROID_BOOTLOADER=y ++CONFIG_SPL_STACK_R=y ++CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 ++CONFIG_SPL_ATF_SUPPORT=y ++CONFIG_FASTBOOT_BUF_ADDR=0x00800800 ++CONFIG_FASTBOOT_BUF_SIZE=0x08000000 ++CONFIG_FASTBOOT_FLASH=y ++CONFIG_FASTBOOT_FLASH_MMC_DEV=0 ++CONFIG_CMD_BOOTZ=y ++# CONFIG_CMD_IMLS is not set ++CONFIG_CMD_GPT=y ++CONFIG_CMD_LOAD_ANDROID=y ++CONFIG_CMD_BOOT_ANDROID=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_SF=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_USB_MASS_STORAGE=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_TIME=y ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_SPL_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_MISC=y ++CONFIG_ROCKCHIP_EFUSE=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_DM_ETH=y ++CONFIG_ETH_DESIGNWARE=y ++CONFIG_GMAC_ROCKCHIP=y ++CONFIG_PINCTRL=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_PINCTRL_ROCKCHIP_RK3399=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_PWM=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_RAM=y ++CONFIG_SPL_RAM=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_BASE=0xFF1A0000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_DWC3=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GADGET=y ++CONFIG_USB_STORAGE=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_GADGET_DOWNLOAD=y ++CONFIG_G_DNL_MANUFACTURER="Rockchip" ++CONFIG_G_DNL_VENDOR_NUM=0x2207 ++CONFIG_G_DNL_PRODUCT_NUM=0x330a ++CONFIG_USB_HOST_ETHER=y ++CONFIG_USB_ETHER_ASIX=y ++CONFIG_USB_ETHER_ASIX88179=y ++CONFIG_USB_ETHER_MCS7830=y ++CONFIG_USB_ETHER_RTL8152=y ++CONFIG_USB_ETHER_SMSC95XX=y ++CONFIG_DM_VIDEO=y ++CONFIG_DISPLAY=y ++CONFIG_VIDEO_ROCKCHIP=y ++CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200 ++CONFIG_DISPLAY_ROCKCHIP_HDMI=y ++CONFIG_USE_TINY_PRINTF=y ++CONFIG_ERRNO_STR=y +diff --git a/include/configs/odroidn1.h b/include/configs/odroidn1.h +new file mode 100644 +index 0000000000..d45b673349 +--- /dev/null ++++ b/include/configs/odroidn1.h +@@ -0,0 +1,28 @@ ++/* ++ * (C) Copyright 2016 Rockchip Electronics Co., Ltd ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __ODROIDN1_H ++#define __ODROIDN1_H ++ ++#include ++ ++#define CONFIG_MMC_SDHCI_SDMA ++#define CONFIG_SYS_MMC_ENV_DEV 0 ++ ++#define SDRAM_BANK_SIZE (2UL << 30) ++#define CONFIG_MISC_INIT_R ++#define CONFIG_SERIAL_TAG ++#define CONFIG_ENV_OVERWRITE ++ ++#define CONFIG_BMP_16BPP ++#define CONFIG_BMP_24BPP ++#define CONFIG_BMP_32BPP ++ ++#define ROCKCHIP_DEVICE_SETTINGS \ ++ "stdout=serial,vidconsole\0" \ ++ "stderr=serial,vidconsole\0" ++ ++#endif