Rockchip: add mainline linux support

packages/multimedia/ffmpeg/package.mk

@@ -41,7 +41,7 @@ else
   PKG_FFMPEG_VDPAU="--disable-vdpau"
 fi
 
-if [ "${PROJECT}" = "Rockchip" ]; then
+if [ "${PROJECT}" = "Rockchip" -a "${LINUX}" = "rockchip-4.4" ]; then
   PKG_DEPENDS_TARGET+=" rkmpp"
   PKG_NEED_UNPACK+=" $(get_pkg_directory rkmpp)"
   PKG_PATCH_DIRS+=" rkmpp"
@@ -50,7 +50,7 @@ else
   PKG_FFMPEG_RKMPP="--disable-rkmpp"
 fi
 
-if [ "${PROJECT}" = "Allwinner" ]; then
+if [ "${PROJECT}" = "Allwinner" -o "${PROJECT}" = "Rockchip" ]; then
   PKG_DEPENDS_TARGET+=" libdrm systemd" # systemd is needed for libudev
   PKG_NEED_UNPACK+=" $(get_pkg_directory libdrm) $(get_pkg_directory systemd)"
   PKG_PATCH_DIRS+=" v4l2-request-api"

projects/Rockchip/README.md

@@ -5,8 +5,8 @@ This project is for Rockchip SoC devices
 ## Devices
 
 **RK3288**
-* [ASUS Tinker Board](devices/TinkerBoard)
-* [mqmaker MiQi](devices/MiQi)
+* [ASUS Tinker Board](devices/RK3288)
+* [mqmaker MiQi](devices/RK3288)
 
 **RK3328**
 * [PINE64 ROCK64](devices/RK3328)

projects/Rockchip/bootloader/install

@@ -4,7 +4,7 @@
 PKG_RKBIN="$(get_build_dir rkbin)"
 PKG_SOC=$UBOOT_SYSTEM
 
-if [ "$DEVICE" = "RK3328" -o "$DEVICE" = "RK3399" ]; then
+if [ "$DEVICE" = "RK3288" -o "$DEVICE" = "RK3328" -o "$DEVICE" = "RK3399" ]; then
   PKG_SOC="${DEVICE/RK/rk}"
 fi
 

projects/Rockchip/bootloader/release

@@ -15,8 +15,13 @@ mkdir -p $RELEASE_DIR/3rdparty/bootloader
     fi
   fi
 
+  DTB_PREFIX="$UBOOT_SYSTEM-"
+  if [ "$DEVICE" = "RK3288" -o "$DEVICE" = "RK3328" -o "$DEVICE" = "RK3399" ]; then
+    DTB_PREFIX="${DEVICE/RK/rk}-"
+  fi
+
   LINUX_DTS_DIR=$(get_build_dir linux)/arch/$TARGET_KERNEL_ARCH/boot/dts
-  for dtb in $LINUX_DTS_DIR/*.dtb $LINUX_DTS_DIR/*/*.dtb; do
+  for dtb in $LINUX_DTS_DIR/$DTB_PREFIX*.dtb $LINUX_DTS_DIR/rockchip/$DTB_PREFIX*.dtb; do
     if [ -f $dtb ]; then
       cp -a $dtb $RELEASE_DIR/3rdparty/bootloader
     fi

projects/Rockchip/devices/RK3288/README.md

@@ -0,0 +1,8 @@
+# RK3288
+
+This is a SoC device for RK3288
+
+**Build**
+
+* `PROJECT=Rockchip DEVICE=RK3288 ARCH=arm UBOOT_SYSTEM=miqi make image`
+* `PROJECT=Rockchip DEVICE=RK3288 ARCH=arm UBOOT_SYSTEM=tinker make image`

projects/Rockchip/devices/RK3288/filesystem/usr/bin/cputemp

@@ -0,0 +1,8 @@
+#!/bin/sh
+
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2009-2014 Stephan Raue (stephan@openelec.tv)
+# Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv)
+
+TEMP="$(cat /sys/class/thermal/thermal_zone1/temp)"
+echo "$(( $TEMP / 1000 )) C"

projects/Rockchip/devices/RK3288/filesystem/usr/bin/gputemp

@@ -0,0 +1,8 @@
+#!/bin/sh
+
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2009-2014 Stephan Raue (stephan@openelec.tv)
+# Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv)
+
+TEMP="$(cat /sys/class/thermal/thermal_zone2/temp)"
+echo "$(( $TEMP / 1000 )) C"

projects/Rockchip/devices/RK3288/options

@@ -0,0 +1,31 @@
+################################################################################
+# setup device defaults
+################################################################################
+
+  # The TARGET_CPU variable controls which processor should be targeted for
+  # generated code.
+    case $TARGET_ARCH in
+      arm)
+        TARGET_FLOAT="hard"
+        TARGET_CPU="cortex-a17"
+        TARGET_FPU="neon-vfpv4"
+        TARGET_FEATURES="32bit"
+        KERNEL_TOOLCHAIN="arm-linux-gnueabihf"
+        ;;
+    esac
+
+  # Kernel target
+    KERNEL_TARGET="zImage"
+
+  # Additional kernel make parameters (for example to specify the u-boot loadaddress)
+    KERNEL_MAKE_EXTRACMD=""
+    KERNEL_MAKE_EXTRACMD+=" rk3288-miqi.dtb"
+    KERNEL_MAKE_EXTRACMD+=" rk3288-tinker.dtb"
+    KERNEL_MAKE_EXTRACMD+=" rk3288-tinker-s.dtb"
+
+  # Mali GPU family
+    MALI_FAMILY="t760"
+    GRAPHIC_DRIVERS="panfrost"
+
+  # kernel serial console
+    EXTRA_CMDLINE="console=uart8250,mmio32,0xff690000 console=tty0 coherent_pool=2M cec.debounce_ms=5000"

projects/Rockchip/devices/RK3328/options

@@ -25,20 +25,22 @@
     KERNEL_TARGET="Image"
 
   # Additional kernel make parameters (for example to specify the u-boot loadaddress)
-    KERNEL_MAKE_EXTRACMD=""
-    KERNEL_MAKE_EXTRACMD+=" rockchip/rk3328-box.dtb"
-    KERNEL_MAKE_EXTRACMD+=" rockchip/rk3328-box-trn9.dtb"
-    KERNEL_MAKE_EXTRACMD+=" rockchip/rk3328-box-z28.dtb"
-    KERNEL_MAKE_EXTRACMD+=" rockchip/rk3328-roc-cc.dtb"
-    KERNEL_MAKE_EXTRACMD+=" rockchip/rk3328-rock64.dtb"
-    KERNEL_MAKE_EXTRACMD+=" rockchip/rk3328-rockbox.dtb"
+    if [ "$LINUX" = "rockchip-4.4" ]; then
+      KERNEL_MAKE_EXTRACMD=""
+      KERNEL_MAKE_EXTRACMD+=" rockchip/rk3328-box.dtb"
+      KERNEL_MAKE_EXTRACMD+=" rockchip/rk3328-box-trn9.dtb"
+      KERNEL_MAKE_EXTRACMD+=" rockchip/rk3328-box-z28.dtb"
+      KERNEL_MAKE_EXTRACMD+=" rockchip/rk3328-roc-cc.dtb"
+      KERNEL_MAKE_EXTRACMD+=" rockchip/rk3328-rock64.dtb"
+      KERNEL_MAKE_EXTRACMD+=" rockchip/rk3328-rockbox.dtb"
+    fi
 
   # Mali GPU family
     MALI_FAMILY="450"
+    GRAPHIC_DRIVERS="lima"
 
   # kernel serial console
-    if [ "$UBOOT_SYSTEM" = "box-trn9" ]; then
-      EXTRA_CMDLINE="console=tty0"
-    else
-      EXTRA_CMDLINE="console=uart8250,mmio32,0xff130000 console=tty0"
+    EXTRA_CMDLINE="console=tty0 coherent_pool=2M cec.debounce_ms=5000"
+    if [ "$UBOOT_SYSTEM" != "box-trn9" ]; then
+      EXTRA_CMDLINE="console=uart8250,mmio32,0xff130000 $EXTRA_CMDLINE"
     fi

projects/Rockchip/devices/RK3328/patches/linux/default/linux-0007-experimental.patch

@@ -0,0 +1,52 @@
+From c3bcf805d77c97fe3b0c2b5f879816cdbf0d8d39 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Tue, 31 Dec 2019 08:09:41 +0000
+Subject: [PATCH] HACK: drm/rockchip: set default win channel on rk3328
+
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 3 +++
+ drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 +
+ drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 4 ++++
+ 3 files changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+index b8c0d2fcc52a..5c2988c46cbb 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+@@ -1879,6 +1879,9 @@ static int vop_initial(struct vop *vop)
+ 		vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
+ 
+ 	VOP_REG_SET(vop, misc, global_regdone_en, 1);
++	VOP_REG_SET(vop, misc, win_channel[0], 0x12);
++	VOP_REG_SET(vop, misc, win_channel[1], 0x34);
++	VOP_REG_SET(vop, misc, win_channel[2], 0x56);
+ 	VOP_REG_SET(vop, common, dsp_blank, 0);
+ 
+ 	for (i = 0; i < vop->data->win_size; i++) {
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+index 89fe8d5c7721..09d4c937acad 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+@@ -87,6 +87,7 @@ struct vop_common {
+ 
+ struct vop_misc {
+ 	struct vop_reg global_regdone_en;
++	struct vop_reg win_channel[4];
+ };
+ 
+ struct vop_intr {
+diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+index 73d24c6bbf05..67442fa03d3f 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+@@ -908,6 +908,10 @@ static const struct vop_output rk3328_output = {
+ 
+ static const struct vop_misc rk3328_misc = {
+ 	.global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
++
++	.win_channel[0] = VOP_REG(RK3328_WIN0_CTRL2, 0xff, 0),
++	.win_channel[1] = VOP_REG(RK3328_WIN1_CTRL2, 0xff, 0),
++	.win_channel[2] = VOP_REG(RK3328_WIN2_CTRL2, 0xff, 0),
+ };
+ 
+ static const struct vop_common rk3328_common = {

projects/Rockchip/devices/RK3399/options

@@ -25,15 +25,18 @@
     KERNEL_TARGET="Image"
 
   # Additional kernel make parameters (for example to specify the u-boot loadaddress)
-    KERNEL_MAKE_EXTRACMD=""
-    KERNEL_MAKE_EXTRACMD+=" rockchip/rk3399-khadas-edge.dtb"
-    KERNEL_MAKE_EXTRACMD+=" rockchip/rk3399-rock960.dtb"
-    KERNEL_MAKE_EXTRACMD+=" rockchip/rk3399-rock-pi-4.dtb"
-    KERNEL_MAKE_EXTRACMD+=" rockchip/rk3399-rockpro64.dtb"
-    KERNEL_MAKE_EXTRACMD+=" rockchip/rk3399-sapphire.dtb"
+    if [ "$LINUX" = "rockchip-4.4" ]; then
+      KERNEL_MAKE_EXTRACMD=""
+      KERNEL_MAKE_EXTRACMD+=" rockchip/rk3399-khadas-edge.dtb"
+      KERNEL_MAKE_EXTRACMD+=" rockchip/rk3399-rock960.dtb"
+      KERNEL_MAKE_EXTRACMD+=" rockchip/rk3399-rock-pi-4.dtb"
+      KERNEL_MAKE_EXTRACMD+=" rockchip/rk3399-rockpro64.dtb"
+      KERNEL_MAKE_EXTRACMD+=" rockchip/rk3399-sapphire.dtb"
+    fi
 
   # Mali GPU family
     MALI_FAMILY="t860"
+    GRAPHIC_DRIVERS="panfrost"
 
   # kernel serial console
-    EXTRA_CMDLINE="console=uart8250,mmio32,0xff1a0000 console=tty0"
+    EXTRA_CMDLINE="console=uart8250,mmio32,0xff1a0000 console=tty0 coherent_pool=2M cec.debounce_ms=5000"

projects/Rockchip/filesystem/usr/share/alsa/cards/Analog.conf

@@ -0,0 +1,12 @@
+#
+# Configuration for Analog
+#
+
+<confdir:pcm/front.conf>
+
+Analog.pcm.front.0 {
+	@args [ CARD ]
+	@args.CARD { type string }
+	type hw
+	card $CARD
+}

projects/Rockchip/options

@@ -11,9 +11,15 @@
   # U-Boot firmware package(s) to use
     UBOOT_FIRMWARE="rkbin"
 
+  # Additional kernel make parameters (for example to specify the u-boot loadaddress)
+    KERNEL_MAKE_EXTRACMD="dtbs"
+
+  # Additional kernel dependencies
+    KERNEL_EXTRA_DEPENDS_TARGET="lz4:host"
+
   # Kernel to use. values can be:
   # default:  default mainline kernel
-    LINUX="${LINUX:-rockchip-4.4}"
+    LINUX="${LINUX:-default}"
 
 ################################################################################
 # setup build defaults
@@ -35,8 +41,8 @@
   # OpenGL(X) implementation to use (no / mesa)
     OPENGL="no"
 
-  # OpenGL-ES implementation to use (no / bcm2835-driver / gpu-viv-bin-mx6q)
-    OPENGLES="libmali"
+  # OpenGL-ES implementation to use (no / libmali / mesa)
+    OPENGLES="${OPENGLES:-libmali}"
 
   # Displayserver to use (weston / no)
     DISPLAYSERVER="no"
@@ -73,7 +79,7 @@
     SYSTEM_PART_START=32768
 
   # build and install driver addons (yes / no)
-    DRIVER_ADDONS_SUPPORT="yes"
+    DRIVER_ADDONS_SUPPORT="no"
 
   # driver addons to install:
   # for a list of additinoal drivers see packages/linux-driver-addons

projects/Rockchip/packages/systemd/scripts/cpufreq

@@ -0,0 +1,24 @@
+#!/bin/sh
+
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2009-2015 Stephan Raue (stephan@openelec.tv)
+# Copyright (C) 2019-present Team LibreELEC (https://libreelec.tv)
+
+SYS_CPUFREQ_GOV=$(cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor)
+
+if [ "${SYS_CPUFREQ_GOV}" = "ondemand" ]; then
+  for io_is_busy in $(find /sys/devices/system/cpu -name io_is_busy); do
+    echo 1 > "${io_is_busy}"
+  done
+  for up_threshold in $(find /sys/devices/system/cpu -name up_threshold); do
+    echo 50 > "${up_threshold}"
+  done
+  for sampling_rate in $(find /sys/devices/system/cpu -name sampling_rate); do
+    echo 100000 > "${sampling_rate}"
+  done
+  for sampling_down_factor in $(find /sys/devices/system/cpu -name sampling_down_factor); do
+    echo 50 > "${sampling_down_factor}"
+  done
+else
+  echo "cpufreq: settings not found for current cpu governor." | systemd-cat -p info
+fi

projects/Rockchip/patches/linux/default/linux-0013-v4l2-from-list.patch

@@ -0,0 +1,327 @@
+From f13b6014af30426eef07bb798afc98a5dbd63975 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Tue, 29 Oct 2019 01:26:01 +0000
+Subject: [PATCH] RFC: media: uapi: h264: Add DPB entry field reference flags
+
+Add DPB entry flags to help indicate when a reference frame is a field picture
+and how the DPB entry is referenced, top or bottom field or full frame.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ Documentation/media/uapi/v4l/ext-ctrls-codec.rst | 12 ++++++++++++
+ include/media/h264-ctrls.h                       |  4 ++++
+ 2 files changed, 16 insertions(+)
+
+diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst
+index 28313c0f4e7c..d472a54d1c4d 100644
+--- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst
++++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst
+@@ -2028,6 +2028,18 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type -
+     * - ``V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM``
+       - 0x00000004
+       - The DPB entry is a long term reference frame
++    * - ``V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE``
++      - 0x00000008
++      - The DPB entry is a field picture
++    * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_TOP``
++      - 0x00000010
++      - The DPB entry is a top field reference
++    * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM``
++      - 0x00000020
++      - The DPB entry is a bottom field reference
++    * - ``V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME``
++      - 0x00000030
++      - The DPB entry is a reference frame
+ 
+ ``V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE (enum)``
+     Specifies the decoding mode to use. Currently exposes slice-based and
+diff --git a/include/media/h264-ctrls.h b/include/media/h264-ctrls.h
+index e877bf1d537c..76020ebd1e6c 100644
+--- a/include/media/h264-ctrls.h
++++ b/include/media/h264-ctrls.h
+@@ -185,6 +185,10 @@ struct v4l2_ctrl_h264_slice_params {
+ #define V4L2_H264_DPB_ENTRY_FLAG_VALID		0x01
+ #define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE		0x02
+ #define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM	0x04
++#define V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE	0x08
++#define V4L2_H264_DPB_ENTRY_FLAG_REF_TOP	0x10
++#define V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM	0x20
++#define V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME	0x30
+ 
+ struct v4l2_h264_dpb_entry {
+ 	__u64 reference_ts;
+
+From 178708eae224bd680fd9d7721ffe93e51bb19852 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Tue, 29 Oct 2019 01:26:02 +0000
+Subject: [PATCH] RFC: media: hantro: Fix H264 decoding of field encoded
+ content
+
+This still need code cleanup and formatting
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/staging/media/hantro/hantro_g1_h264_dec.c |  17 +--
+ drivers/staging/media/hantro/hantro_h264.c        | 122 ++++++++++++++--------
+ drivers/staging/media/hantro/hantro_hw.h          |   2 +
+ 3 files changed, 85 insertions(+), 56 deletions(-)
+
+diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c
+index 3cd40a8f0daa..4f2923d34d41 100644
+--- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c
++++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c
+@@ -132,25 +132,12 @@ static void set_ref(struct hantro_ctx *ctx)
+ 	struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
+ 	const u8 *b0_reflist, *b1_reflist, *p_reflist;
+ 	struct hantro_dev *vpu = ctx->dev;
+-	u32 dpb_longterm = 0;
+-	u32 dpb_valid = 0;
+ 	int reg_num;
+ 	u32 reg;
+ 	int i;
+ 
+-	/*
+-	 * Set up bit maps of valid and long term DPBs.
+-	 * NOTE: The bits are reversed, i.e. MSb is DPB 0.
+-	 */
+-	for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
+-		if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
+-			dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
+-
+-		if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
+-			dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
+-	}
+-	vdpu_write_relaxed(vpu, dpb_valid << 16, G1_REG_VALID_REF);
+-	vdpu_write_relaxed(vpu, dpb_longterm << 16, G1_REG_LT_REF);
++	vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF);
++	vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF);
+ 
+ 	/*
+ 	 * Set up reference frame picture numbers.
+diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c
+index 568640eab3a6..79d96ff4e685 100644
+--- a/drivers/staging/media/hantro/hantro_h264.c
++++ b/drivers/staging/media/hantro/hantro_h264.c
+@@ -225,17 +225,65 @@ static void prepare_table(struct hantro_ctx *ctx)
+ {
+ 	const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls;
+ 	const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode;
++	const struct v4l2_ctrl_h264_slice_params *slices = ctrls->slices;
+ 	struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu;
+ 	const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
++	u32 dpb_longterm = 0;
++	u32 dpb_valid = 0;
+ 	int i;
+ 
++	/*
++	 * Set up bit maps of valid and long term DPBs.
++	 * NOTE: The bits are reversed, i.e. MSb is DPB 0.
++	 */
++	if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) || (slices[0].flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) {
++		for (i = 0; i < HANTRO_H264_DPB_SIZE * 2; ++i) {
++			// check for correct reference use
++			u32 flag = (i & 0x1) ? V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM : V4L2_H264_DPB_ENTRY_FLAG_REF_TOP;
++			if (dpb[i / 2].flags & flag)
++				dpb_valid |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i);
++
++			if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
++				dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i);
++		}
++
++		ctx->h264_dec.dpb_valid = dpb_valid;
++		ctx->h264_dec.dpb_longterm = dpb_longterm;
++	} else {
++		for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
++			if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
++				dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
++
++			if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
++				dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i);
++		}
++
++		ctx->h264_dec.dpb_valid = dpb_valid << 16;
++		ctx->h264_dec.dpb_longterm = dpb_longterm << 16;
++	}
++
+ 	for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) {
+-		tbl->poc[i * 2] = dpb[i].top_field_order_cnt;
+-		tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt;
++		if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) {
++			tbl->poc[i * 2] = dpb[i].top_field_order_cnt;
++			tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt;
++		} else {
++			tbl->poc[i * 2] = 0;
++			tbl->poc[i * 2 + 1] = 0;
++		}
+ 	}
+ 
+-	tbl->poc[32] = dec_param->top_field_order_cnt;
+-	tbl->poc[33] = dec_param->bottom_field_order_cnt;
++	if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) || !(slices[0].flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) {
++		if ((slices[0].flags & V4L2_H264_SLICE_FLAG_FIELD_PIC))
++			tbl->poc[32] = (slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) ?
++					dec_param->bottom_field_order_cnt :
++					dec_param->top_field_order_cnt;
++		else
++			tbl->poc[32] = min(dec_param->top_field_order_cnt, dec_param->bottom_field_order_cnt);
++		tbl->poc[33] = 0;
++	} else {
++		tbl->poc[32] = dec_param->top_field_order_cnt;
++		tbl->poc[33] = dec_param->bottom_field_order_cnt;
++	}
+ 
+ 	reorder_scaling_list(ctx);
+ }
+@@ -249,21 +297,6 @@ struct hantro_h264_reflist_builder {
+ 	u8 num_valid;
+ };
+ 
+-static s32 get_poc(enum v4l2_field field, s32 top_field_order_cnt,
+-		   s32 bottom_field_order_cnt)
+-{
+-	switch (field) {
+-	case V4L2_FIELD_TOP:
+-		return top_field_order_cnt;
+-	case V4L2_FIELD_BOTTOM:
+-		return bottom_field_order_cnt;
+-	default:
+-		break;
+-	}
+-
+-	return min(top_field_order_cnt, bottom_field_order_cnt);
+-}
+-
+ static void
+ init_reflist_builder(struct hantro_ctx *ctx,
+ 		     struct hantro_h264_reflist_builder *b)
+@@ -271,9 +304,7 @@ init_reflist_builder(struct hantro_ctx *ctx,
+ 	const struct v4l2_ctrl_h264_slice_params *slice_params;
+ 	const struct v4l2_ctrl_h264_decode_params *dec_param;
+ 	const struct v4l2_ctrl_h264_sps *sps;
+-	struct vb2_v4l2_buffer *buf = hantro_get_dst_buf(ctx);
+ 	const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
+-	struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q;
+ 	int cur_frame_num, max_frame_num;
+ 	unsigned int i;
+ 
+@@ -285,21 +316,15 @@ init_reflist_builder(struct hantro_ctx *ctx,
+ 
+ 	memset(b, 0, sizeof(*b));
+ 	b->dpb = dpb;
+-	b->curpoc = get_poc(buf->field, dec_param->top_field_order_cnt,
+-			    dec_param->bottom_field_order_cnt);
++	b->curpoc = (slice_params->flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) ?
++		    dec_param->bottom_field_order_cnt :
++		    dec_param->top_field_order_cnt;
+ 
+ 	for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++) {
+-		int buf_idx;
+-
+-		if (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE))
++		u32 ref_flag = dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME;
++		if (!ref_flag)
+ 			continue;
+ 
+-		buf_idx = vb2_find_timestamp(cap_q, dpb[i].reference_ts, 0);
+-		if (buf_idx < 0)
+-			continue;
+-
+-		buf = to_vb2_v4l2_buffer(vb2_get_buffer(cap_q, buf_idx));
+-
+ 		/*
+ 		 * Handle frame_num wraparound as described in section
+ 		 * '8.2.4.1 Decoding process for picture numbers' of the spec.
+@@ -311,8 +336,13 @@ init_reflist_builder(struct hantro_ctx *ctx,
+ 		else
+ 			b->frame_nums[i] = dpb[i].frame_num;
+ 
+-		b->pocs[i] = get_poc(buf->field, dpb[i].top_field_order_cnt,
+-				     dpb[i].bottom_field_order_cnt);
++		if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_FRAME)
++			b->pocs[i] = min(dpb[i].bottom_field_order_cnt, dpb[i].top_field_order_cnt);
++		else if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_BOTTOM)
++			b->pocs[i] = dpb[i].bottom_field_order_cnt;
++		else if (ref_flag == V4L2_H264_DPB_ENTRY_FLAG_REF_TOP)
++			b->pocs[i] = dpb[i].top_field_order_cnt;
++
+ 		b->unordered_reflist[b->num_valid] = i;
+ 		b->num_valid++;
+ 	}
+@@ -466,8 +496,7 @@ build_b_ref_lists(const struct hantro_h264_reflist_builder *builder,
+ static bool dpb_entry_match(const struct v4l2_h264_dpb_entry *a,
+ 			    const struct v4l2_h264_dpb_entry *b)
+ {
+-	return a->top_field_order_cnt == b->top_field_order_cnt &&
+-	       a->bottom_field_order_cnt == b->bottom_field_order_cnt;
++	return a->reference_ts == b->reference_ts;
+ }
+ 
+ static void update_dpb(struct hantro_ctx *ctx)
+@@ -481,13 +510,13 @@ static void update_dpb(struct hantro_ctx *ctx)
+ 
+ 	/* Disable all entries by default. */
+ 	for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++)
+-		ctx->h264_dec.dpb[i].flags &= ~V4L2_H264_DPB_ENTRY_FLAG_ACTIVE;
++		ctx->h264_dec.dpb[i].flags = 0;
+ 
+ 	/* Try to match new DPB entries with existing ones by their POCs. */
+ 	for (i = 0; i < ARRAY_SIZE(dec_param->dpb); i++) {
+ 		const struct v4l2_h264_dpb_entry *ndpb = &dec_param->dpb[i];
+ 
+-		if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE))
++		if (!(ndpb->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID))
+ 			continue;
+ 
+ 		/*
+@@ -498,8 +527,7 @@ static void update_dpb(struct hantro_ctx *ctx)
+ 			struct v4l2_h264_dpb_entry *cdpb;
+ 
+ 			cdpb = &ctx->h264_dec.dpb[j];
+-			if (cdpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE ||
+-			    !dpb_entry_match(cdpb, ndpb))
++			if (!dpb_entry_match(cdpb, ndpb))
+ 				continue;
+ 
+ 			*cdpb = *ndpb;
+@@ -535,7 +563,11 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,
+ 				   unsigned int dpb_idx)
+ {
+ 	struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb;
++	const struct v4l2_ctrl_h264_decode_params *dec_param = ctx->h264_dec.ctrls.decode;
++	const struct v4l2_ctrl_h264_slice_params *slices = ctx->h264_dec.ctrls.slices;
+ 	dma_addr_t dma_addr = 0;
++	s32 cur_poc;
++	u32 flags;
+ 
+ 	if (dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)
+ 		dma_addr = hantro_get_ref(ctx, dpb[dpb_idx].reference_ts);
+@@ -553,7 +585,15 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx,
+ 		dma_addr = vb2_dma_contig_plane_dma_addr(buf, 0);
+ 	}
+ 
+-	return dma_addr;
++	cur_poc = slices[0].flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD ?
++		  dec_param->bottom_field_order_cnt :
++		  dec_param->top_field_order_cnt;
++	flags = dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD_PICTURE ? 0x2 : 0;
++	flags |= abs(dpb[dpb_idx].top_field_order_cnt - cur_poc) <
++		 abs(dpb[dpb_idx].bottom_field_order_cnt - cur_poc) ?
++		 0x1 : 0;
++
++	return dma_addr | flags;
+ }
+ 
+ int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx)
+diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h
+index fa91dd1848b7..fb1451e8a80b 100644
+--- a/drivers/staging/media/hantro/hantro_hw.h
++++ b/drivers/staging/media/hantro/hantro_hw.h
+@@ -86,6 +86,8 @@ struct hantro_h264_dec_hw_ctx {
+ 	struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE];
+ 	struct hantro_h264_dec_reflists reflists;
+ 	struct hantro_h264_dec_ctrls ctrls;
++	u32 dpb_longterm;
++	u32 dpb_valid;
+ };
+ 
+ /**

scripts/uboot_helper

@@ -203,7 +203,21 @@ devices = \
         'config': 'miqi-rk3288_config'
       },
     },
+    'RK3288': {
+      'miqi': {
+        'dtb': 'rk3288-miqi.dtb',
+        'config': 'miqi-rk3288_config'
+      },
+      'tinker': {
+        'dtb': 'rk3288-tinker-s.dtb',
+        'config': 'tinker-rk3288_config'
+      },
+    },
     'RK3328': {
+      'a1': {
+        'dtb': 'rk3328-a1.dtb',
+        'config': 'evb-rk3328_defconfig'
+      },
       'box': {
         'dtb': 'rk3328-box.dtb',
         'config': 'evb-rk3328_defconfig'
@@ -230,10 +244,38 @@ devices = \
       },
     },
     'RK3399': {
+      'firefly': {
+        'dtb': 'rk3399-firefly.dtb',
+        'config': 'evb-rk3399_config'
+      },
+      'hugsun-x99': {
+        'dtb': 'rk3399-hugsun-x99.dtb',
+        'config': 'evb-rk3399_config'
+      },
       'khadas-edge': {
         'dtb': 'rk3399-khadas-edge.dtb',
         'config': 'evb-rk3399_config'
       },
+      'khadas-edge-v': {
+        'dtb': 'rk3399-khadas-edge-v.dtb',
+        'config': 'evb-rk3399_config'
+      },
+      'nanopc-t4': {
+        'dtb': 'rk3399-nanopc-t4.dtb',
+        'config': 'evb-rk3399_config'
+      },
+      'nanopi-m4': {
+        'dtb': 'rk3399-nanopi-m4.dtb',
+        'config': 'evb-rk3399_config'
+      },
+      'nanopi-neo4': {
+        'dtb': 'rk3399-nanopi-neo4.dtb',
+        'config': 'evb-rk3399_config'
+      },
+      'orangepi': {
+        'dtb': 'rk3399-orangepi.dtb',
+        'config': 'evb-rk3399_config'
+      },
       'rock960': {
         'dtb': 'rk3399-rock960.dtb',
         'config': 'evb-rk3399_config'
@@ -246,6 +288,10 @@ devices = \
         'dtb': 'rk3399-rockpro64.dtb',
         'config': 'evb-rk3399_config'
       },
+      'roc-pc': {
+        'dtb': 'rk3399-roc-pc.dtb',
+        'config': 'evb-rk3399_config'
+      },
       'sapphire': {
         'dtb': 'rk3399-sapphire.dtb',
         'config': 'evb-rk3399_config'