Merge pull request #3706 from jernejsk/aw_updates

Allwinner updates
2025-07-30 22:26:42 +00:00 · 2019-07-18 00:25:18 +02:00 · 2019-07-18 00:25:18 +02:00 · 0b827797c3
commit 0b827797c3
parent db005886dc eee66e7d5b
6 changed files with 689 additions and 132 deletions
--- a/packages/linux-drivers/mali-midgard/package.mk
+++ b/packages/linux-drivers/mali-midgard/package.mk
@ -2,8 +2,8 @@
 # Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv)

 PKG_NAME="mali-midgard"
-PKG_VERSION="e651c466df2d522dd8c98307ed0d0f1d0af6ac75" # TX011-SW-99002-r28p0-01rel0
-PKG_SHA256="0b623f61b90a5e3fc7db106b55d5b48b42ca2e04632fd28fa17dee8141177438"
+PKG_VERSION="fe58463f54e3d8b204bae7e0292a054f583cc0f7" # TX011-SW-99002-r28p0-01rel0
+PKG_SHA256="4befe8cd5494fccdbea478a5b374b7e4f1e0d10ba5e9a35b88b5edd8bde7151c"
 PKG_ARCH="arm aarch64"
 PKG_LICENSE="GPL"
 PKG_SITE="https://developer.arm.com/products/software/mali-drivers/"
--- a/projects/Allwinner/devices/H6/patches/u-boot/002-orange-pi-3-support.patch
+++ b/projects/Allwinner/devices/H6/patches/u-boot/002-orange-pi-3-support.patch
@ -347,13 +347,14 @@ new file mode 100644
 index 0000000000..9a9cd28142
 --- /dev/null
 +++ b/configs/orangepi_3_defconfig
-@@ -0,0 +1,12 @@
+@@ -0,0 +1,13 @@
 +CONFIG_ARM=y
 +CONFIG_ARCH_SUNXI=y
 +CONFIG_SPL=y
 +CONFIG_MACH_SUN50I_H6=y
 +CONFIG_MMC0_CD_PIN="PF6"
 +# CONFIG_PSCI_RESET is not set
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 +CONFIG_NR_DRAM_BANKS=1
 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 +# CONFIG_CMD_FLASH is not set
--- a/projects/Allwinner/linux/linux.aarch64.conf
+++ b/projects/Allwinner/linux/linux.aarch64.conf
@ -1243,6 +1243,7 @@ CONFIG_WIRELESS=y
 CONFIG_WIRELESS_EXT=y
 CONFIG_WEXT_CORE=y
 CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
 CONFIG_WEXT_PRIV=y
 CONFIG_CFG80211=m
 # CONFIG_NL80211_TESTMODE is not set
@ -1253,6 +1254,8 @@ CONFIG_CFG80211_DEFAULT_PS=y
 # CONFIG_CFG80211_DEBUGFS is not set
 CONFIG_CFG80211_CRDA_SUPPORT=y
 CONFIG_CFG80211_WEXT=y
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
 CONFIG_MAC80211=m
 CONFIG_MAC80211_HAS_RC=y
 CONFIG_MAC80211_RC_MINSTREL=y
@ -1487,7 +1490,7 @@ CONFIG_VEXPRESS_SYSCFG=y
 CONFIG_EEPROM_AT25=m
 # CONFIG_EEPROM_LEGACY is not set
 # CONFIG_EEPROM_MAX6875 is not set
-# CONFIG_EEPROM_93CX6 is not set
+CONFIG_EEPROM_93CX6=m
 # CONFIG_EEPROM_93XX46 is not set
 # CONFIG_EEPROM_IDT_89HPESX is not set
 # CONFIG_EEPROM_EE1004 is not set
@ -1860,7 +1863,7 @@ CONFIG_USB_NET_SMSC95XX=m
 CONFIG_USB_NET_NET1080=m
 CONFIG_USB_NET_PLUSB=m
 CONFIG_USB_NET_MCS7830=m
-# CONFIG_USB_NET_RNDIS_HOST is not set
+CONFIG_USB_NET_RNDIS_HOST=m
 CONFIG_USB_NET_CDC_SUBSET_ENABLE=m
 CONFIG_USB_NET_CDC_SUBSET=m
 # CONFIG_USB_ALI_M5632 is not set
@ -1885,20 +1888,31 @@ CONFIG_WLAN_VENDOR_ADMTEK=y
 CONFIG_ATH_COMMON=m
 CONFIG_WLAN_VENDOR_ATH=y
 # CONFIG_ATH_DEBUG is not set
+CONFIG_ATH9K_HW=m
+CONFIG_ATH9K_COMMON=m
+CONFIG_ATH9K_BTCOEX_SUPPORT=y
 # CONFIG_ATH9K is not set
-# CONFIG_ATH9K_HTC is not set
-# CONFIG_CARL9170 is not set
-# CONFIG_ATH6KL is not set
-# CONFIG_AR5523 is not set
+CONFIG_ATH9K_HTC=m
+# CONFIG_ATH9K_HTC_DEBUGFS is not set
+CONFIG_CARL9170=m
+CONFIG_CARL9170_LEDS=y
+CONFIG_CARL9170_WPC=y
+# CONFIG_CARL9170_HWRNG is not set
+CONFIG_ATH6KL=m
+# CONFIG_ATH6KL_SDIO is not set
+CONFIG_ATH6KL_USB=m
+# CONFIG_ATH6KL_DEBUG is not set
+CONFIG_AR5523=m
 CONFIG_ATH10K=m
 CONFIG_ATH10K_CE=y
 # CONFIG_ATH10K_SDIO is not set
-# CONFIG_ATH10K_USB is not set
+CONFIG_ATH10K_USB=m
 # CONFIG_ATH10K_DEBUG is not set
 # CONFIG_ATH10K_DEBUGFS is not set
-# CONFIG_WCN36XX is not set
+CONFIG_WCN36XX=m
+# CONFIG_WCN36XX_DEBUGFS is not set
 CONFIG_WLAN_VENDOR_ATMEL=y
-# CONFIG_AT76C50X_USB is not set
+CONFIG_AT76C50X_USB=m
 CONFIG_WLAN_VENDOR_BROADCOM=y
 # CONFIG_B43 is not set
 # CONFIG_B43LEGACY is not set
@ -1907,7 +1921,7 @@ CONFIG_BRCMUTIL=m
 CONFIG_BRCMFMAC=m
 CONFIG_BRCMFMAC_PROTO_BCDC=y
 CONFIG_BRCMFMAC_SDIO=y
-# CONFIG_BRCMFMAC_USB is not set
+CONFIG_BRCMFMAC_USB=y
 # CONFIG_BRCM_TRACING is not set
 # CONFIG_BRCMDBG is not set
 CONFIG_WLAN_VENDOR_CISCO=y
@ -1916,41 +1930,64 @@ CONFIG_WLAN_VENDOR_INTERSIL=y
 # CONFIG_HOSTAP is not set
 # CONFIG_P54_COMMON is not set
 CONFIG_WLAN_VENDOR_MARVELL=y
-# CONFIG_LIBERTAS is not set
-# CONFIG_LIBERTAS_THINFIRM is not set
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+# CONFIG_LIBERTAS_SDIO is not set
+# CONFIG_LIBERTAS_SPI is not set
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_LIBERTAS_MESH is not set
+CONFIG_LIBERTAS_THINFIRM=m
+# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
+CONFIG_LIBERTAS_THINFIRM_USB=m
 CONFIG_MWIFIEX=m
-# CONFIG_MWIFIEX_SDIO is not set
-# CONFIG_MWIFIEX_USB is not set
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_USB=m
 CONFIG_WLAN_VENDOR_MEDIATEK=y
-# CONFIG_MT7601U is not set
-# CONFIG_MT76x0U is not set
-# CONFIG_MT76x2U is not set
+CONFIG_MT7601U=m
+CONFIG_MT76_CORE=m
+CONFIG_MT76_LEDS=y
+CONFIG_MT76_USB=m
+CONFIG_MT76x02_LIB=m
+CONFIG_MT76x02_USB=m
+CONFIG_MT76x0_COMMON=m
+CONFIG_MT76x0U=m
+CONFIG_MT76x2_COMMON=m
+CONFIG_MT76x2U=m
 CONFIG_WLAN_VENDOR_RALINK=y
-# CONFIG_RT2X00 is not set
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+CONFIG_RT2800USB_RT3573=y
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
 CONFIG_WLAN_VENDOR_REALTEK=y
-# CONFIG_RTL8187 is not set
+CONFIG_RTL8187=m
+CONFIG_RTL8187_LEDS=y
 CONFIG_RTL_CARDS=m
 # CONFIG_RTL8192CU is not set
 # CONFIG_RTL8XXXU is not set
 # CONFIG_RTW88 is not set
-CONFIG_WLAN_VENDOR_RSI=y
-# CONFIG_RSI_91X is not set
-CONFIG_WLAN_VENDOR_ST=y
-# CONFIG_CW1200 is not set
-CONFIG_WLAN_VENDOR_TI=y
-# CONFIG_WL1251 is not set
-# CONFIG_WL12XX is not set
-CONFIG_WL18XX=m
-CONFIG_WLCORE=m
-# CONFIG_WLCORE_SPI is not set
-CONFIG_WLCORE_SDIO=m
-CONFIG_WILINK_PLATFORM_DATA=y
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
 CONFIG_WLAN_VENDOR_ZYDAS=y
-# CONFIG_USB_ZD1201 is not set
-# CONFIG_ZD1211RW is not set
-CONFIG_WLAN_VENDOR_QUANTENNA=y
+CONFIG_USB_ZD1201=m
+CONFIG_ZD1211RW=m
+# CONFIG_ZD1211RW_DEBUG is not set
+# CONFIG_WLAN_VENDOR_QUANTENNA is not set
 # CONFIG_MAC80211_HWSIM is not set
-# CONFIG_USB_NET_RNDIS_WLAN is not set
+CONFIG_USB_NET_RNDIS_WLAN=m
 # CONFIG_VIRT_WIFI is not set

 #
@ -1968,7 +2005,7 @@ CONFIG_NET_FAILOVER=y
 CONFIG_INPUT=y
 CONFIG_INPUT_LEDS=y
 CONFIG_INPUT_FF_MEMLESS=y
-CONFIG_INPUT_POLLDEV=m
+CONFIG_INPUT_POLLDEV=y
 # CONFIG_INPUT_SPARSEKMAP is not set
 CONFIG_INPUT_MATRIXKMAP=y

@ -1994,7 +2031,7 @@ CONFIG_KEYBOARD_ATKBD=y
 # CONFIG_KEYBOARD_DLINK_DIR685 is not set
 # CONFIG_KEYBOARD_LKKBD is not set
 CONFIG_KEYBOARD_GPIO=y
-# CONFIG_KEYBOARD_GPIO_POLLED is not set
+CONFIG_KEYBOARD_GPIO_POLLED=y
 # CONFIG_KEYBOARD_TCA6416 is not set
 # CONFIG_KEYBOARD_TCA8418 is not set
 # CONFIG_KEYBOARD_MATRIX is not set
@ -2116,7 +2153,19 @@ CONFIG_INPUT_UINPUT=y
 # CONFIG_INPUT_DRV260X_HAPTICS is not set
 # CONFIG_INPUT_DRV2665_HAPTICS is not set
 # CONFIG_INPUT_DRV2667_HAPTICS is not set
-# CONFIG_RMI4_CORE is not set
+CONFIG_RMI4_CORE=m
+# CONFIG_RMI4_I2C is not set
+# CONFIG_RMI4_SPI is not set
+# CONFIG_RMI4_SMB is not set
+CONFIG_RMI4_F03=y
+CONFIG_RMI4_F03_SERIO=m
+CONFIG_RMI4_2D_SENSOR=y
+CONFIG_RMI4_F11=y
+CONFIG_RMI4_F12=y
+CONFIG_RMI4_F30=y
+# CONFIG_RMI4_F34 is not set
+# CONFIG_RMI4_F54 is not set
+# CONFIG_RMI4_F55 is not set

 #
 # Hardware I/O ports
@ -3801,11 +3850,11 @@ CONFIG_HID_A4TECH=y
 # CONFIG_HID_ACRUX is not set
 CONFIG_HID_APPLE=y
 # CONFIG_HID_APPLEIR is not set
-# CONFIG_HID_ASUS is not set
-# CONFIG_HID_AUREAL is not set
-CONFIG_HID_BELKIN=y
+CONFIG_HID_ASUS=m
+CONFIG_HID_AUREAL=m
+# CONFIG_HID_BELKIN is not set
 # CONFIG_HID_BETOP_FF is not set
-# CONFIG_HID_BIGBEN_FF is not set
+CONFIG_HID_BIGBEN_FF=m
 CONFIG_HID_CHERRY=y
 CONFIG_HID_CHICONY=y
 # CONFIG_HID_CORSAIR is not set
@ -3814,7 +3863,8 @@ CONFIG_HID_CHICONY=y
 # CONFIG_HID_PRODIKEYS is not set
 # CONFIG_HID_CMEDIA is not set
 CONFIG_HID_CYPRESS=y
-# CONFIG_HID_DRAGONRISE is not set
+CONFIG_HID_DRAGONRISE=m
+CONFIG_DRAGONRISE_FF=y
 # CONFIG_HID_EMS_FF is not set
 # CONFIG_HID_ELAN is not set
 # CONFIG_HID_ELECOM is not set
@ -3825,65 +3875,68 @@ CONFIG_HID_EZKEY=y
 # CONFIG_HID_HOLTEK is not set
 # CONFIG_HID_GT683R is not set
 # CONFIG_HID_KEYTOUCH is not set
-# CONFIG_HID_KYE is not set
+CONFIG_HID_KYE=m
 # CONFIG_HID_UCLOGIC is not set
 # CONFIG_HID_WALTOP is not set
 # CONFIG_HID_VIEWSONIC is not set
-# CONFIG_HID_GYRATION is not set
+CONFIG_HID_GYRATION=m
 # CONFIG_HID_ICADE is not set
 CONFIG_HID_ITE=y
 # CONFIG_HID_JABRA is not set
-# CONFIG_HID_TWINHAN is not set
+CONFIG_HID_TWINHAN=m
 CONFIG_HID_KENSINGTON=y
 # CONFIG_HID_LCPOWER is not set
 # CONFIG_HID_LED is not set
 # CONFIG_HID_LENOVO is not set
 CONFIG_HID_LOGITECH=y
-# CONFIG_HID_LOGITECH_HIDPP is not set
-# CONFIG_LOGITECH_FF is not set
-# CONFIG_LOGIRUMBLEPAD2_FF is not set
-# CONFIG_LOGIG940_FF is not set
-# CONFIG_LOGIWHEELS_FF is not set
+CONFIG_HID_LOGITECH_HIDPP=m
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_LOGIG940_FF=y
+CONFIG_LOGIWHEELS_FF=y
 # CONFIG_HID_MAGICMOUSE is not set
 # CONFIG_HID_MALTRON is not set
 # CONFIG_HID_MAYFLASH is not set
-CONFIG_HID_REDRAGON=y
+# CONFIG_HID_REDRAGON is not set
 CONFIG_HID_MICROSOFT=y
 CONFIG_HID_MONTEREY=y
-# CONFIG_HID_MULTITOUCH is not set
+CONFIG_HID_MULTITOUCH=m
 # CONFIG_HID_NTI is not set
 # CONFIG_HID_NTRIG is not set
-# CONFIG_HID_ORTEK is not set
-# CONFIG_HID_OUYA is not set
-# CONFIG_HID_PANTHERLORD is not set
-# CONFIG_HID_PENMOUNT is not set
-# CONFIG_HID_PETALYNX is not set
+CONFIG_HID_ORTEK=m
+CONFIG_HID_OUYA=m
+CONFIG_HID_PANTHERLORD=m
+CONFIG_PANTHERLORD_FF=y
+CONFIG_HID_PENMOUNT=m
+CONFIG_HID_PETALYNX=m
 # CONFIG_HID_PICOLCD is not set
 # CONFIG_HID_PLANTRONICS is not set
 # CONFIG_HID_PRIMAX is not set
 # CONFIG_HID_RETRODE is not set
 # CONFIG_HID_ROCCAT is not set
 # CONFIG_HID_SAITEK is not set
-# CONFIG_HID_SAMSUNG is not set
-# CONFIG_HID_SONY is not set
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_SONY_FF=y
 # CONFIG_HID_SPEEDLINK is not set
 CONFIG_HID_STEAM=m
 # CONFIG_HID_STEELSERIES is not set
-# CONFIG_HID_SUNPLUS is not set
-# CONFIG_HID_RMI is not set
+CONFIG_HID_SUNPLUS=m
+CONFIG_HID_RMI=m
 # CONFIG_HID_GREENASIA is not set
-# CONFIG_HID_SMARTJOYPLUS is not set
-# CONFIG_HID_TIVO is not set
-# CONFIG_HID_TOPSEED is not set
+CONFIG_HID_SMARTJOYPLUS=m
+CONFIG_SMARTJOYPLUS_FF=y
+CONFIG_HID_TIVO=m
+CONFIG_HID_TOPSEED=m
 # CONFIG_HID_THINGM is not set
 # CONFIG_HID_THRUSTMASTER is not set
 # CONFIG_HID_UDRAW_PS3 is not set
 # CONFIG_HID_U2FZERO is not set
 # CONFIG_HID_WACOM is not set
-# CONFIG_HID_WIIMOTE is not set
-# CONFIG_HID_XINMO is not set
+CONFIG_HID_WIIMOTE=m
+CONFIG_HID_XINMO=m
 # CONFIG_HID_ZEROPLUS is not set
-# CONFIG_HID_ZYDACRON is not set
+CONFIG_HID_ZYDACRON=m
 # CONFIG_HID_SENSOR_HUB is not set
 # CONFIG_HID_ALPS is not set
 # end of Special HID drivers
@ -3893,7 +3946,7 @@ CONFIG_HID_STEAM=m
 #
 CONFIG_USB_HID=y
 # CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_HIDDEV=y
 # end of USB HID support

 #
@ -5146,7 +5199,7 @@ CONFIG_RAS=y
 # CONFIG_DAX is not set
 CONFIG_NVMEM=y
 CONFIG_NVMEM_SYSFS=y
-# CONFIG_NVMEM_SUNXI_SID is not set
+CONFIG_NVMEM_SUNXI_SID=y

 #
 # HW tracing support
@ -5666,7 +5719,7 @@ CONFIG_GENERIC_PCI_IOMAP=y
 CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
 CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
 CONFIG_INDIRECT_PIO=y
-# CONFIG_CRC_CCITT is not set
+CONFIG_CRC_CCITT=m
 CONFIG_CRC16=y
 CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=y
--- a/projects/Allwinner/linux/linux.arm.conf
+++ b/projects/Allwinner/linux/linux.arm.conf
@ -1269,6 +1269,7 @@ CONFIG_WIRELESS=y
 CONFIG_WIRELESS_EXT=y
 CONFIG_WEXT_CORE=y
 CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
 CONFIG_WEXT_PRIV=y
 CONFIG_CFG80211=m
 # CONFIG_NL80211_TESTMODE is not set
@ -1280,6 +1281,8 @@ CONFIG_CFG80211_DEFAULT_PS=y
 # CONFIG_CFG80211_DEBUGFS is not set
 CONFIG_CFG80211_CRDA_SUPPORT=y
 CONFIG_CFG80211_WEXT=y
+CONFIG_LIB80211=m
+# CONFIG_LIB80211_DEBUG is not set
 CONFIG_MAC80211=m
 CONFIG_MAC80211_HAS_RC=y
 CONFIG_MAC80211_RC_MINSTREL=y
@ -1806,13 +1809,7 @@ CONFIG_WLAN_VENDOR_ATH=y
 CONFIG_ATH9K_HW=m
 CONFIG_ATH9K_COMMON=m
 CONFIG_ATH9K_BTCOEX_SUPPORT=y
-CONFIG_ATH9K=m
-CONFIG_ATH9K_AHB=y
-# CONFIG_ATH9K_DEBUGFS is not set
-# CONFIG_ATH9K_DYNACK is not set
-# CONFIG_ATH9K_WOW is not set
-# CONFIG_ATH9K_CHANNEL_CONTEXT is not set
-CONFIG_ATH9K_PCOEM=y
+# CONFIG_ATH9K is not set
 CONFIG_ATH9K_HTC=m
 # CONFIG_ATH9K_HTC_DEBUGFS is not set
 CONFIG_CARL9170=m
@ -1826,13 +1823,13 @@ CONFIG_AR5523=m
 CONFIG_ATH10K=m
 CONFIG_ATH10K_CE=y
 # CONFIG_ATH10K_SDIO is not set
-# CONFIG_ATH10K_USB is not set
+CONFIG_ATH10K_USB=m
 # CONFIG_ATH10K_DEBUG is not set
 # CONFIG_ATH10K_DEBUGFS is not set
 CONFIG_WCN36XX=m
 # CONFIG_WCN36XX_DEBUGFS is not set
 CONFIG_WLAN_VENDOR_ATMEL=y
-# CONFIG_AT76C50X_USB is not set
+CONFIG_AT76C50X_USB=m
 CONFIG_WLAN_VENDOR_BROADCOM=y
 CONFIG_B43=m
 CONFIG_B43_BCMA=y
@ -1860,16 +1857,20 @@ CONFIG_BRCMFMAC_USB=y
 # CONFIG_BRCMDBG is not set
 CONFIG_WLAN_VENDOR_CISCO=y
 CONFIG_WLAN_VENDOR_INTEL=y
-CONFIG_WLAN_VENDOR_INTERSIL=y
-# CONFIG_HOSTAP is not set
-CONFIG_P54_COMMON=m
-CONFIG_P54_USB=m
-# CONFIG_P54_SPI is not set
-CONFIG_P54_LEDS=y
+# CONFIG_WLAN_VENDOR_INTERSIL is not set
 CONFIG_WLAN_VENDOR_MARVELL=y
-# CONFIG_LIBERTAS is not set
-# CONFIG_LIBERTAS_THINFIRM is not set
-# CONFIG_MWIFIEX is not set
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+# CONFIG_LIBERTAS_SDIO is not set
+# CONFIG_LIBERTAS_SPI is not set
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_LIBERTAS_MESH is not set
+CONFIG_LIBERTAS_THINFIRM=m
+# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_MWIFIEX=m
+# CONFIG_MWIFIEX_SDIO is not set
+CONFIG_MWIFIEX_USB=m
 CONFIG_WLAN_VENDOR_MEDIATEK=y
 CONFIG_MT7601U=m
 CONFIG_MT76_CORE=m
@ -1906,20 +1907,14 @@ CONFIG_RTL_CARDS=m
 # CONFIG_RTL8192CU is not set
 # CONFIG_RTL8XXXU is not set
 # CONFIG_RTW88 is not set
-CONFIG_WLAN_VENDOR_RSI=y
-# CONFIG_RSI_91X is not set
-CONFIG_WLAN_VENDOR_ST=y
-# CONFIG_CW1200 is not set
-CONFIG_WLAN_VENDOR_TI=y
-# CONFIG_WL1251 is not set
-# CONFIG_WL12XX is not set
-# CONFIG_WL18XX is not set
-# CONFIG_WLCORE is not set
+# CONFIG_WLAN_VENDOR_RSI is not set
+# CONFIG_WLAN_VENDOR_ST is not set
+# CONFIG_WLAN_VENDOR_TI is not set
 CONFIG_WLAN_VENDOR_ZYDAS=y
 CONFIG_USB_ZD1201=m
 CONFIG_ZD1211RW=m
 # CONFIG_ZD1211RW_DEBUG is not set
-CONFIG_WLAN_VENDOR_QUANTENNA=y
+# CONFIG_WLAN_VENDOR_QUANTENNA is not set
 # CONFIG_MAC80211_HWSIM is not set
 CONFIG_USB_NET_RNDIS_WLAN=m
 # CONFIG_VIRT_WIFI is not set
@ -2019,7 +2014,19 @@ CONFIG_INPUT_UINPUT=y
 # CONFIG_INPUT_DRV260X_HAPTICS is not set
 # CONFIG_INPUT_DRV2665_HAPTICS is not set
 # CONFIG_INPUT_DRV2667_HAPTICS is not set
-# CONFIG_RMI4_CORE is not set
+CONFIG_RMI4_CORE=m
+# CONFIG_RMI4_I2C is not set
+# CONFIG_RMI4_SPI is not set
+# CONFIG_RMI4_SMB is not set
+CONFIG_RMI4_F03=y
+CONFIG_RMI4_F03_SERIO=m
+CONFIG_RMI4_2D_SENSOR=y
+CONFIG_RMI4_F11=y
+CONFIG_RMI4_F12=y
+CONFIG_RMI4_F30=y
+# CONFIG_RMI4_F34 is not set
+# CONFIG_RMI4_F54 is not set
+# CONFIG_RMI4_F55 is not set

 #
 # Hardware I/O ports
@ -3619,11 +3626,11 @@ CONFIG_HID_A4TECH=y
 # CONFIG_HID_ACRUX is not set
 CONFIG_HID_APPLE=y
 # CONFIG_HID_APPLEIR is not set
-# CONFIG_HID_ASUS is not set
-# CONFIG_HID_AUREAL is not set
-CONFIG_HID_BELKIN=y
+CONFIG_HID_ASUS=m
+CONFIG_HID_AUREAL=m
+# CONFIG_HID_BELKIN is not set
 # CONFIG_HID_BETOP_FF is not set
-# CONFIG_HID_BIGBEN_FF is not set
+CONFIG_HID_BIGBEN_FF=m
 CONFIG_HID_CHERRY=y
 CONFIG_HID_CHICONY=y
 # CONFIG_HID_CORSAIR is not set
@ -3632,7 +3639,8 @@ CONFIG_HID_CHICONY=y
 # CONFIG_HID_PRODIKEYS is not set
 # CONFIG_HID_CMEDIA is not set
 CONFIG_HID_CYPRESS=y
-# CONFIG_HID_DRAGONRISE is not set
+CONFIG_HID_DRAGONRISE=m
+CONFIG_DRAGONRISE_FF=y
 # CONFIG_HID_EMS_FF is not set
 # CONFIG_HID_ELAN is not set
 # CONFIG_HID_ELECOM is not set
@ -3643,64 +3651,67 @@ CONFIG_HID_EZKEY=y
 # CONFIG_HID_HOLTEK is not set
 # CONFIG_HID_GT683R is not set
 # CONFIG_HID_KEYTOUCH is not set
-# CONFIG_HID_KYE is not set
+CONFIG_HID_KYE=m
 # CONFIG_HID_UCLOGIC is not set
 # CONFIG_HID_WALTOP is not set
 # CONFIG_HID_VIEWSONIC is not set
-# CONFIG_HID_GYRATION is not set
+CONFIG_HID_GYRATION=m
 # CONFIG_HID_ICADE is not set
 # CONFIG_HID_ITE is not set
 # CONFIG_HID_JABRA is not set
-# CONFIG_HID_TWINHAN is not set
+CONFIG_HID_TWINHAN=m
 CONFIG_HID_KENSINGTON=y
 # CONFIG_HID_LCPOWER is not set
 # CONFIG_HID_LED is not set
 # CONFIG_HID_LENOVO is not set
 CONFIG_HID_LOGITECH=y
-# CONFIG_HID_LOGITECH_HIDPP is not set
-# CONFIG_LOGITECH_FF is not set
-# CONFIG_LOGIRUMBLEPAD2_FF is not set
-# CONFIG_LOGIG940_FF is not set
-# CONFIG_LOGIWHEELS_FF is not set
+CONFIG_HID_LOGITECH_HIDPP=m
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_LOGIG940_FF=y
+CONFIG_LOGIWHEELS_FF=y
 # CONFIG_HID_MAGICMOUSE is not set
 # CONFIG_HID_MALTRON is not set
 # CONFIG_HID_MAYFLASH is not set
 # CONFIG_HID_REDRAGON is not set
 CONFIG_HID_MICROSOFT=y
 CONFIG_HID_MONTEREY=y
-# CONFIG_HID_MULTITOUCH is not set
+CONFIG_HID_MULTITOUCH=m
 # CONFIG_HID_NTI is not set
 # CONFIG_HID_NTRIG is not set
-# CONFIG_HID_ORTEK is not set
+CONFIG_HID_ORTEK=m
 CONFIG_HID_OUYA=y
-# CONFIG_HID_PANTHERLORD is not set
-# CONFIG_HID_PENMOUNT is not set
-# CONFIG_HID_PETALYNX is not set
+CONFIG_HID_PANTHERLORD=m
+CONFIG_PANTHERLORD_FF=y
+CONFIG_HID_PENMOUNT=m
+CONFIG_HID_PETALYNX=m
 # CONFIG_HID_PICOLCD is not set
 # CONFIG_HID_PLANTRONICS is not set
 # CONFIG_HID_PRIMAX is not set
 # CONFIG_HID_RETRODE is not set
 # CONFIG_HID_ROCCAT is not set
 # CONFIG_HID_SAITEK is not set
-# CONFIG_HID_SAMSUNG is not set
-# CONFIG_HID_SONY is not set
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_SONY_FF=y
 # CONFIG_HID_SPEEDLINK is not set
 CONFIG_HID_STEAM=m
 # CONFIG_HID_STEELSERIES is not set
-# CONFIG_HID_SUNPLUS is not set
-# CONFIG_HID_RMI is not set
+CONFIG_HID_SUNPLUS=m
+CONFIG_HID_RMI=m
 # CONFIG_HID_GREENASIA is not set
-# CONFIG_HID_SMARTJOYPLUS is not set
-# CONFIG_HID_TIVO is not set
-# CONFIG_HID_TOPSEED is not set
+CONFIG_HID_SMARTJOYPLUS=m
+CONFIG_SMARTJOYPLUS_FF=y
+CONFIG_HID_TIVO=m
+CONFIG_HID_TOPSEED=m
 # CONFIG_HID_THINGM is not set
 # CONFIG_HID_THRUSTMASTER is not set
 # CONFIG_HID_UDRAW_PS3 is not set
 # CONFIG_HID_WACOM is not set
-# CONFIG_HID_WIIMOTE is not set
-# CONFIG_HID_XINMO is not set
+CONFIG_HID_WIIMOTE=m
+CONFIG_HID_XINMO=m
 # CONFIG_HID_ZEROPLUS is not set
-# CONFIG_HID_ZYDACRON is not set
+CONFIG_HID_ZYDACRON=m
 # CONFIG_HID_SENSOR_HUB is not set
 # CONFIG_HID_ALPS is not set
 # end of Special HID drivers
@ -3710,7 +3721,7 @@ CONFIG_HID_STEAM=m
 #
 CONFIG_USB_HID=y
 # CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
+CONFIG_USB_HIDDEV=y
 # end of USB HID support

 #
--- a/projects/Allwinner/patches/linux/0013-color-range-encoding.patch
+++ b/projects/Allwinner/patches/linux/0013-color-range-encoding.patch
@ -0,0 +1,417 @@
+From fc81bf6b49bea503653e5cdba5392ffd878c1453 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Thu, 27 Jun 2019 19:30:44 +0200
+Subject: [PATCH 1/4] drm/sun4i: Introduce color encoding and range properties
+
+In order to correctly convert YUV color space to RGB, we have to know
+color encoding and range.
+
+Introduce these two properties using helper method.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+index bd0e6a52d1d8..240a800217df 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+@@ -441,6 +441,7 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+ 					       struct sun8i_mixer *mixer,
+ 					       int index)
+ {
+	u32 supported_encodings, supported_ranges;
+ 	struct sun8i_vi_layer *layer;
+ 	unsigned int plane_cnt;
+ 	int ret;
+@@ -469,6 +470,22 @@ struct sun8i_vi_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+ 		return ERR_PTR(ret);
+ 	}
+ 
+	supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) |
+			      BIT(DRM_COLOR_YCBCR_BT709);
+
+	supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
+			   BIT(DRM_COLOR_YCBCR_FULL_RANGE);
+
+	ret = drm_plane_create_color_properties(&layer->plane,
+						supported_encodings,
+						supported_ranges,
+						DRM_COLOR_YCBCR_BT709,
+						DRM_COLOR_YCBCR_LIMITED_RANGE);
+	if (ret) {
+		dev_err(drm->dev, "Couldn't add encoding and range properties!\n");
+		return ERR_PTR(ret);
+	}
+
+ 	drm_plane_helper_add(&layer->plane, &sun8i_vi_layer_helper_funcs);
+ 	layer->mixer = mixer;
+ 	layer->channel = index;
+-- 
+2.22.0
+
+
+From 0067d439358510393ac42d454a2c9efee2546cd9 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Thu, 27 Jun 2019 19:33:54 +0200
+Subject: [PATCH 2/4] drm/sun4i: sun8i_csc: Simplify register writes
+
+It turns out addition of 0x200 to constant parts (+0.5) is not really
+necessary. Besides, we can consider that before and fix value in CSC
+matrix.
+
+This simplifies register writes quiet a bit.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/gpu/drm/sun4i/sun8i_csc.c | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
+index b8c059f1a118..e07b7876d89b 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
+@@ -69,7 +69,7 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
+ 				       enum sun8i_csc_mode mode)
+ {
+ 	const u32 *table;
+-	int i, data;
+	u32 base_reg;
+ 
+ 	switch (mode) {
+ 	case SUN8I_CSC_MODE_YUV2RGB:
+@@ -83,13 +83,8 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
+ 		return;
+ 	}
+ 
+-	for (i = 0; i < 12; i++) {
+-		data = table[i];
+-		/* For some reason, 0x200 must be added to constant parts */
+-		if (((i + 1) & 3) == 0)
+-			data += 0x200;
+-		regmap_write(map, SUN8I_CSC_COEFF(base, i), data);
+-	}
+	base_reg = SUN8I_CSC_COEFF(base, 0);
+	regmap_bulk_write(map, base_reg, table, 12);
+ }
+ 
+ static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
+-- 
+2.22.0
+
+
+From b0533429bd778930fa71683f9f8b241895b9e239 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Thu, 27 Jun 2019 19:21:16 +0200
+Subject: [PATCH 3/4] drm/sun4i: sun8i-csc: Add support for color encoding and
+ range
+
+Conversion from YUV to RGB depends on range (limited or full) and
+encoding (BT.601 or BT.709). Current code doesn't consider this and
+always uses BT.601 encoding and limited range.
+
+Fix this by introducing new CSC matrices, which are selected based on
+range and encoding parameters.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/gpu/drm/sun4i/sun8i_csc.c      | 144 ++++++++++++++++++++-----
+ drivers/gpu/drm/sun4i/sun8i_csc.h      |   6 +-
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.c |   4 +-
+ 3 files changed, 126 insertions(+), 28 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
+index e07b7876d89b..70c792d052fe 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
+@@ -18,16 +18,59 @@ static const u32 ccsc_base[2][2] = {
+  * First tree values in each line are multiplication factor and last
+  * value is constant, which is added at the end.
+  */
+-static const u32 yuv2rgb[] = {
+-	0x000004A8, 0x00000000, 0x00000662, 0xFFFC845A,
+-	0x000004A8, 0xFFFFFE6F, 0xFFFFFCBF, 0x00021DF4,
+-	0x000004A8, 0x00000813, 0x00000000, 0xFFFBAC4A,
+
+static const u32 yuv2rgb[2][2][12] = {
+	[DRM_COLOR_YCBCR_LIMITED_RANGE] = {
+		[DRM_COLOR_YCBCR_BT601] = {
+			0x000004A8, 0x00000000, 0x00000662, 0xFFFC8451,
+			0x000004A8, 0xFFFFFE6F, 0xFFFFFCC0, 0x00021E4D,
+			0x000004A8, 0x00000811, 0x00000000, 0xFFFBACA9,
+		},
+		[DRM_COLOR_YCBCR_BT709] = {
+			0x000004A8, 0x00000000, 0x0000072B, 0xFFFC1F99,
+			0x000004A8, 0xFFFFFF26, 0xFFFFFDDF, 0x00013383,
+			0x000004A8, 0x00000873, 0x00000000, 0xFFFB7BEF,
+		}
+	},
+	[DRM_COLOR_YCBCR_FULL_RANGE] = {
+		[DRM_COLOR_YCBCR_BT601] = {
+			0x00000400, 0x00000000, 0x0000059B, 0xFFFD322E,
+			0x00000400, 0xFFFFFEA0, 0xFFFFFD25, 0x00021DD5,
+			0x00000400, 0x00000716, 0x00000000, 0xFFFC74BD,
+		},
+		[DRM_COLOR_YCBCR_BT709] = {
+			0x00000400, 0x00000000, 0x0000064C, 0xFFFCD9B4,
+			0x00000400, 0xFFFFFF41, 0xFFFFFE21, 0x00014F96,
+			0x00000400, 0x0000076C, 0x00000000, 0xFFFC49EF,
+		}
+	},
+ };
+ 
+-static const u32 yvu2rgb[] = {
+-	0x000004A8, 0x00000662, 0x00000000, 0xFFFC845A,
+-	0x000004A8, 0xFFFFFCBF, 0xFFFFFE6F, 0x00021DF4,
+-	0x000004A8, 0x00000000, 0x00000813, 0xFFFBAC4A,
+static const u32 yvu2rgb[2][2][12] = {
+	[DRM_COLOR_YCBCR_LIMITED_RANGE] = {
+		[DRM_COLOR_YCBCR_BT601] = {
+			0x000004A8, 0x00000662, 0x00000000, 0xFFFC8451,
+			0x000004A8, 0xFFFFFCC0, 0xFFFFFE6F, 0x00021E4D,
+			0x000004A8, 0x00000000, 0x00000811, 0xFFFBACA9,
+		},
+		[DRM_COLOR_YCBCR_BT709] = {
+			0x000004A8, 0x0000072B, 0x00000000, 0xFFFC1F99,
+			0x000004A8, 0xFFFFFDDF, 0xFFFFFF26, 0x00013383,
+			0x000004A8, 0x00000000, 0x00000873, 0xFFFB7BEF,
+		}
+	},
+	[DRM_COLOR_YCBCR_FULL_RANGE] = {
+		[DRM_COLOR_YCBCR_BT601] = {
+			0x00000400, 0x0000059B, 0x00000000, 0xFFFD322E,
+			0x00000400, 0xFFFFFD25, 0xFFFFFEA0, 0x00021DD5,
+			0x00000400, 0x00000000, 0x00000716, 0xFFFC74BD,
+		},
+		[DRM_COLOR_YCBCR_BT709] = {
+			0x00000400, 0x0000064C, 0x00000000, 0xFFFCD9B4,
+			0x00000400, 0xFFFFFE21, 0xFFFFFF41, 0x00014F96,
+			0x00000400, 0x00000000, 0x0000076C, 0xFFFC49EF,
+		}
+	},
+ };
+ 
+ /*
+@@ -53,30 +96,74 @@ static const u32 yvu2rgb[] = {
+  * c20 c21 c22 [d2 const2]
+  */
+ 
+-static const u32 yuv2rgb_de3[] = {
+-	0x0002542a, 0x00000000, 0x0003312a, 0xffc00000,
+-	0x0002542a, 0xffff376b, 0xfffe5fc3, 0xfe000000,
+-	0x0002542a, 0x000408d3, 0x00000000, 0xfe000000,
+static const u32 yuv2rgb_de3[2][2][12] = {
+	[DRM_COLOR_YCBCR_LIMITED_RANGE] = {
+		[DRM_COLOR_YCBCR_BT601] = {
+			0x0002542A, 0x00000000, 0x0003312A, 0xFFC00000,
+			0x0002542A, 0xFFFF376B, 0xFFFE5FC3, 0xFE000000,
+			0x0002542A, 0x000408D2, 0x00000000, 0xFE000000,
+		},
+		[DRM_COLOR_YCBCR_BT709] = {
+			0x0002542A, 0x00000000, 0x000395E2, 0xFFC00000,
+			0x0002542A, 0xFFFF92D2, 0xFFFEEF27, 0xFE000000,
+			0x0002542A, 0x0004398C, 0x00000000, 0xFE000000,
+		}
+	},
+	[DRM_COLOR_YCBCR_FULL_RANGE] = {
+		[DRM_COLOR_YCBCR_BT601] = {
+			0x00020000, 0x00000000, 0x0002CDD2, 0x00000000,
+			0x00020000, 0xFFFF4FCE, 0xFFFE925D, 0xFE000000,
+			0x00020000, 0x00038B43, 0x00000000, 0xFE000000,
+		},
+		[DRM_COLOR_YCBCR_BT709] = {
+			0x00020000, 0x00000000, 0x0003264C, 0x00000000,
+			0x00020000, 0xFFFFA018, 0xFFFF1053, 0xFE000000,
+			0x00020000, 0x0003B611, 0x00000000, 0xFE000000,
+		}
+	},
+ };
+ 
+-static const u32 yvu2rgb_de3[] = {
+-	0x0002542a, 0x0003312a, 0x00000000, 0xffc00000,
+-	0x0002542a, 0xfffe5fc3, 0xffff376b, 0xfe000000,
+-	0x0002542a, 0x00000000, 0x000408d3, 0xfe000000,
+static const u32 yvu2rgb_de3[2][2][12] = {
+	[DRM_COLOR_YCBCR_LIMITED_RANGE] = {
+		[DRM_COLOR_YCBCR_BT601] = {
+			0x0002542A, 0x0003312A, 0x00000000, 0xFFC00000,
+			0x0002542A, 0xFFFE5FC3, 0xFFFF376B, 0xFE000000,
+			0x0002542A, 0x00000000, 0x000408D2, 0xFE000000,
+		},
+		[DRM_COLOR_YCBCR_BT709] = {
+			0x0002542A, 0x000395E2, 0x00000000, 0xFFC00000,
+			0x0002542A, 0xFFFEEF27, 0xFFFF92D2, 0xFE000000,
+			0x0002542A, 0x00000000, 0x0004398C, 0xFE000000,
+		}
+	},
+	[DRM_COLOR_YCBCR_FULL_RANGE] = {
+		[DRM_COLOR_YCBCR_BT601] = {
+			0x00020000, 0x0002CDD2, 0x00000000, 0x00000000,
+			0x00020000, 0xFFFE925D, 0xFFFF4FCE, 0xFE000000,
+			0x00020000, 0x00000000, 0x00038B43, 0xFE000000,
+		},
+		[DRM_COLOR_YCBCR_BT709] = {
+			0x00020000, 0x0003264C, 0x00000000, 0x00000000,
+			0x00020000, 0xFFFF1053, 0xFFFFA018, 0xFE000000,
+			0x00020000, 0x00000000, 0x0003B611, 0xFE000000,
+		}
+	},
+ };
+ 
+ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
+-				       enum sun8i_csc_mode mode)
+				       enum sun8i_csc_mode mode,
+				       enum drm_color_encoding encoding,
+				       enum drm_color_range range)
+ {
+ 	const u32 *table;
+ 	u32 base_reg;
+ 
+ 	switch (mode) {
+ 	case SUN8I_CSC_MODE_YUV2RGB:
+-		table = yuv2rgb;
+		table = yuv2rgb[range][encoding];
+ 		break;
+ 	case SUN8I_CSC_MODE_YVU2RGB:
+-		table = yvu2rgb;
+		table = yvu2rgb[range][encoding];
+ 		break;
+ 	default:
+ 		DRM_WARN("Wrong CSC mode specified.\n");
+@@ -88,17 +175,19 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
+ }
+ 
+ static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
+-					    enum sun8i_csc_mode mode)
+					    enum sun8i_csc_mode mode,
+					    enum drm_color_encoding encoding,
+					    enum drm_color_range range)
+ {
+ 	const u32 *table;
+ 	u32 base_reg;
+ 
+ 	switch (mode) {
+ 	case SUN8I_CSC_MODE_YUV2RGB:
+-		table = yuv2rgb_de3;
+		table = yuv2rgb_de3[range][encoding];
+ 		break;
+ 	case SUN8I_CSC_MODE_YVU2RGB:
+-		table = yvu2rgb_de3;
+		table = yvu2rgb_de3[range][encoding];
+ 		break;
+ 	default:
+ 		DRM_WARN("Wrong CSC mode specified.\n");
+@@ -137,19 +226,22 @@ static void sun8i_de3_ccsc_enable(struct regmap *map, int layer, bool enable)
+ }
+ 
+ void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
+-				     enum sun8i_csc_mode mode)
+				     enum sun8i_csc_mode mode,
+				     enum drm_color_encoding encoding,
+				     enum drm_color_range range)
+ {
+ 	u32 base;
+ 
+ 	if (mixer->cfg->is_de3) {
+-		sun8i_de3_ccsc_set_coefficients(mixer->engine.regs,
+-						layer, mode);
+		sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer,
+						mode, encoding, range);
+ 		return;
+ 	}
+ 
+ 	base = ccsc_base[mixer->cfg->ccsc][layer];
+ 
+-	sun8i_csc_set_coefficients(mixer->engine.regs, base, mode);
+	sun8i_csc_set_coefficients(mixer->engine.regs, base,
+				   mode, encoding, range);
+ }
+ 
+ void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable)
+diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8i_csc.h
+index dce4c444bcd6..f42441b1b14d 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_csc.h
+++ b/drivers/gpu/drm/sun4i/sun8i_csc.h
+@@ -6,6 +6,8 @@
+ #ifndef _SUN8I_CSC_H_
+ #define _SUN8I_CSC_H_
+ 
+#include <drm/drm_color_mgmt.h>
+
+ struct sun8i_mixer;
+ 
+ /* VI channel CSC units offsets */
+@@ -26,7 +28,9 @@ enum sun8i_csc_mode {
+ };
+ 
+ void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
+-				     enum sun8i_csc_mode mode);
+				     enum sun8i_csc_mode mode,
+				     enum drm_color_encoding encoding,
+				     enum drm_color_range range);
+ void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+index 240a800217df..011924a75263 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+@@ -232,7 +232,9 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
+ 			   SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val);
+ 
+ 	if (fmt_info->csc != SUN8I_CSC_MODE_OFF) {
+-		sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_info->csc);
+		sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_info->csc,
+						state->color_encoding,
+						state->color_range);
+ 		sun8i_csc_enable_ccsc(mixer, channel, true);
+ 	} else {
+ 		sun8i_csc_enable_ccsc(mixer, channel, false);
+-- 
+2.22.0
+
+
+From c8217462c6c143a9fada595bf3e34af83eb15f87 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Thu, 27 Jun 2019 21:50:16 +0200
+Subject: [PATCH 4/4] HACK: Force full range
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/gpu/drm/sun4i/sun8i_csc.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
+index 70c792d052fe..7b60fce1a8c6 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
+@@ -160,10 +160,10 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
+ 
+ 	switch (mode) {
+ 	case SUN8I_CSC_MODE_YUV2RGB:
+-		table = yuv2rgb[range][encoding];
+		table = yuv2rgb[DRM_COLOR_YCBCR_FULL_RANGE][encoding];
+ 		break;
+ 	case SUN8I_CSC_MODE_YVU2RGB:
+-		table = yvu2rgb[range][encoding];
+		table = yvu2rgb[DRM_COLOR_YCBCR_FULL_RANGE][encoding];
+ 		break;
+ 	default:
+ 		DRM_WARN("Wrong CSC mode specified.\n");
+@@ -184,10 +184,10 @@ static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
+ 
+ 	switch (mode) {
+ 	case SUN8I_CSC_MODE_YUV2RGB:
+-		table = yuv2rgb_de3[range][encoding];
+		table = yuv2rgb_de3[DRM_COLOR_YCBCR_FULL_RANGE][encoding];
+ 		break;
+ 	case SUN8I_CSC_MODE_YVU2RGB:
+-		table = yvu2rgb_de3[range][encoding];
+		table = yvu2rgb_de3[DRM_COLOR_YCBCR_FULL_RANGE][encoding];
+ 		break;
+ 	default:
+ 		DRM_WARN("Wrong CSC mode specified.\n");
+-- 
+2.22.0
+
--- a/projects/Allwinner/patches/linux/0014-regulator-fixes.patch
+++ b/projects/Allwinner/patches/linux/0014-regulator-fixes.patch
@ -0,0 +1,75 @@
+From 95b579d069348a59d0fa6463a2f821089876ebfd Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Sat, 6 Jul 2019 11:07:49 +0200
+Subject: [PATCH 1/2] regulator: axp20x: fix DCDCA and DCDCD for AXP806
+
+Refactoring of the driver introduced few bugs in AXP806's DCDCA and
+DCDCD regulator definitions.
+
+Fix them.
+
+Fixes: db4a555f7c4cf ("regulator: axp20x: use defines for masks")
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/regulator/axp20x-regulator.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
+index 152053361862..c951568994a1 100644
+--- a/drivers/regulator/axp20x-regulator.c
+++ b/drivers/regulator/axp20x-regulator.c
+@@ -240,7 +240,7 @@
+ #define AXP806_DCDCA_600mV_END		\
+ 	(AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS)
+ #define AXP806_DCDCA_1120mV_START	0x33
+-#define AXP806_DCDCA_1120mV_STEPS	14
+#define AXP806_DCDCA_1120mV_STEPS	20
+ #define AXP806_DCDCA_1120mV_END		\
+ 	(AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS)
+ #define AXP806_DCDCA_NUM_VOLTAGES	72
+@@ -774,8 +774,8 @@ static const struct regulator_linear_range axp806_dcdcd_ranges[] = {
+ 			       AXP806_DCDCD_600mV_END,
+ 			       20000),
+ 	REGULATOR_LINEAR_RANGE(1600000,
+-			       AXP806_DCDCD_600mV_START,
+-			       AXP806_DCDCD_600mV_END,
+			       AXP806_DCDCD_1600mV_START,
+			       AXP806_DCDCD_1600mV_END,
+ 			       100000),
+ };
+ 
+-- 
+2.22.0
+
+From a8e790b1850f368daff2d3c35b52f8a69978be6e Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Sat, 6 Jul 2019 11:15:13 +0200
+Subject: [PATCH 2/2] regulator: axp20x: fix DCDC6 for AXP803
+
+Refactoring of axp20x driver introduced a bug in AXP803's DCDC6
+regulator definition.
+
+Fix it.
+
+Fixes: db4a555f7c4cf ("regulator: axp20x: use defines for masks")
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+---
+ drivers/regulator/axp20x-regulator.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
+index c951568994a1..29b92ce521b7 100644
+--- a/drivers/regulator/axp20x-regulator.c
+++ b/drivers/regulator/axp20x-regulator.c
+@@ -181,7 +181,7 @@
+ #define AXP803_DCDC6_600mV_END		\
+ 	(AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS)
+ #define AXP803_DCDC6_1120mV_START	0x33
+-#define AXP803_DCDC6_1120mV_STEPS	14
+#define AXP803_DCDC6_1120mV_STEPS	20
+ #define AXP803_DCDC6_1120mV_END		\
+ 	(AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS)
+ #define AXP803_DCDC6_NUM_VOLTAGES	72
+-- 
+2.22.0
+