From c8f25180bdccdc94a67effb144123c1cf73e5b8e Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Mon, 5 Sep 2022 09:43:08 +0000 Subject: [PATCH 01/29] u-boot (Allwinner): rebase patches for 2022.10-rc3 --- ...-sunxi-binman-Enable-SPL-FIT-loading-for-32-bit-SoCs.patch | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/Allwinner/patches/u-boot/0003-sunxi-binman-Enable-SPL-FIT-loading-for-32-bit-SoCs.patch b/projects/Allwinner/patches/u-boot/0003-sunxi-binman-Enable-SPL-FIT-loading-for-32-bit-SoCs.patch index eb9288e8c7..01984f8b66 100644 --- a/projects/Allwinner/patches/u-boot/0003-sunxi-binman-Enable-SPL-FIT-loading-for-32-bit-SoCs.patch +++ b/projects/Allwinner/patches/u-boot/0003-sunxi-binman-Enable-SPL-FIT-loading-for-32-bit-SoCs.patch @@ -152,8 +152,8 @@ index 8a8a971a91e1..374818c05741 100644 bool "Remove functionality from SPL FIT loading to reduce size" depends on SPL_FIT - default y if MACH_SUN50I || MACH_SUN50I_H5 || SUN50I_GEN_H6 -- default y if ARCH_IMX8M -+ default y if ARCH_IMX8M || ARCH_SUNXI +- default y if ARCH_IMX8M || ARCH_IMX9 ++ default y if ARCH_IMX8M || ARCH_IMX9 || ARCH_SUNXI help Enable this to reduce the size of the FIT image loading code in SPL, if space for the SPL binary is very tight. From 4d2eedaebad8b7de365dcc938a2a6a449133b385 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Mon, 5 Sep 2022 10:29:52 +0000 Subject: [PATCH 02/29] u-boot (Allwinner H3): rebase patches for 2022.10-rc3 --- ...i-psci-Add-support-for-H3-CPU-0-hotplug.patch | 16 ++++++++-------- ...i-Enable-support-for-SCP-firmware-on-H3.patch | 6 +++--- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/projects/Allwinner/devices/H3/patches/u-boot/0007-sunxi-psci-Add-support-for-H3-CPU-0-hotplug.patch b/projects/Allwinner/devices/H3/patches/u-boot/0007-sunxi-psci-Add-support-for-H3-CPU-0-hotplug.patch index 4b5b457110..154a616cb5 100644 --- a/projects/Allwinner/devices/H3/patches/u-boot/0007-sunxi-psci-Add-support-for-H3-CPU-0-hotplug.patch +++ b/projects/Allwinner/devices/H3/patches/u-boot/0007-sunxi-psci-Add-support-for-H3-CPU-0-hotplug.patch @@ -174,13 +174,13 @@ index ad1f97632979..a2c74da81aa9 100644 #ifdef SCP_ADDR "scp", #endif -diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h +diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 563635636624..2f0d69bdfce2 100644 ---- a/include/configs/sun8i.h -+++ b/include/configs/sun8i.h -@@ -14,6 +14,12 @@ - +--- a/include/configs/sunxi-common.h ++++ b/include/configs/sunxi-common.h +@@ -15,6 +15,12 @@ #include + #include +#ifdef SUNXI_SRAM_A2_SIZE +#define SUNXI_RESUME_BASE (CONFIG_ARMV7_SECURE_BASE + \ @@ -188,9 +188,9 @@ index 563635636624..2f0d69bdfce2 100644 +#define SUNXI_RESUME_SIZE 1024 +#endif + - /* - * Include common sunxi configuration where most the settings are - */ + /* Serial & console */ + #define CONFIG_SYS_NS16550_SERIAL + /* ns16550 reg in the low bits of cpu reg */ -- 2.33.0 diff --git a/projects/Allwinner/devices/H3/patches/u-boot/0010-sunxi-Enable-support-for-SCP-firmware-on-H3.patch b/projects/Allwinner/devices/H3/patches/u-boot/0010-sunxi-Enable-support-for-SCP-firmware-on-H3.patch index 6d360d9bc7..6c90b79842 100644 --- a/projects/Allwinner/devices/H3/patches/u-boot/0010-sunxi-Enable-support-for-SCP-firmware-on-H3.patch +++ b/projects/Allwinner/devices/H3/patches/u-boot/0010-sunxi-Enable-support-for-SCP-firmware-on-H3.patch @@ -53,10 +53,10 @@ index 2b7d655678d0..a25cd11f1124 100644 return 0; } -diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h +diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 2f0d69bdfce2..fda5b235a3e0 100644 ---- a/include/configs/sun8i.h -+++ b/include/configs/sun8i.h +--- a/include/configs/sunxi-common.h ++++ b/include/configs/sunxi-common.h @@ -26,6 +26,9 @@ #define SUNXI_RESUME_BASE (CONFIG_ARMV7_SECURE_BASE + \ CONFIG_ARMV7_SECURE_MAX_SIZE) From ae0eea5c358887ec98c1a9e3a8f4303f5d71b541 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Tue, 20 Sep 2022 13:11:43 +0000 Subject: [PATCH 03/29] u-boot (Amlogic): update patches to support u-boot 2022.10 --- ...-0007-WIP-boards-amlogic-add-WeTek-Hub-defconfig.patch | 8 +++++--- ...008-WIP-boards-amlogic-add-WeTek-Play2-defconfig.patch | 8 +++++--- ...010-WIP-boards-amlogic-add-Radxa-Zero2-defconfig.patch | 8 +++++--- ...013-WIP-boards-amlogic-add-Beelink-GT1-defconfig.patch | 8 +++++--- 4 files changed, 20 insertions(+), 12 deletions(-) diff --git a/projects/Amlogic/patches/u-boot/u-boot-0007-WIP-boards-amlogic-add-WeTek-Hub-defconfig.patch b/projects/Amlogic/patches/u-boot/u-boot-0007-WIP-boards-amlogic-add-WeTek-Hub-defconfig.patch index 19e08fc208..65bce216a1 100644 --- a/projects/Amlogic/patches/u-boot/u-boot-0007-WIP-boards-amlogic-add-WeTek-Hub-defconfig.patch +++ b/projects/Amlogic/patches/u-boot/u-boot-0007-WIP-boards-amlogic-add-WeTek-Hub-defconfig.patch @@ -5,8 +5,8 @@ Subject: [PATCH 07/15] WIP: boards: amlogic: add WeTek Hub defconfig Signed-of-by: Christian Hewitt --- - configs/wetek-hub_defconfig | 69 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 69 insertions(+) + configs/wetek-hub_defconfig | 71 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 71 insertions(+) create mode 100644 configs/wetek-hub_defconfig diff --git a/configs/wetek-hub_defconfig b/configs/wetek-hub_defconfig @@ -14,7 +14,7 @@ new file mode 100644 index 0000000000..73fd7c4211 --- /dev/null +++ b/configs/wetek-hub_defconfig -@@ -0,0 +1,69 @@ +@@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_SYS_BOARD="wetek-gxbb" +CONFIG_ARCH_MESON=y @@ -28,6 +28,8 @@ index 0000000000..73fd7c4211 +CONFIG_IDENT_STRING=" wetek-hub" +CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-wetek-hub" +CONFIG_DEBUG_UART=y ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 +CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_MISC_INIT_R=y diff --git a/projects/Amlogic/patches/u-boot/u-boot-0008-WIP-boards-amlogic-add-WeTek-Play2-defconfig.patch b/projects/Amlogic/patches/u-boot/u-boot-0008-WIP-boards-amlogic-add-WeTek-Play2-defconfig.patch index 41f6df8a6b..06b7894bef 100644 --- a/projects/Amlogic/patches/u-boot/u-boot-0008-WIP-boards-amlogic-add-WeTek-Play2-defconfig.patch +++ b/projects/Amlogic/patches/u-boot/u-boot-0008-WIP-boards-amlogic-add-WeTek-Play2-defconfig.patch @@ -5,8 +5,8 @@ Subject: [PATCH 08/15] WIP: boards: amlogic: add WeTek Play2 defconfig Signed-off-by: Christian Hewittt --- - configs/wetek-play2_defconfig | 69 +++++++++++++++++++++++++++++++++++ - 1 file changed, 69 insertions(+) + configs/wetek-play2_defconfig | 71 +++++++++++++++++++++++++++++++++++ + 1 file changed, 71 insertions(+) create mode 100644 configs/wetek-play2_defconfig diff --git a/configs/wetek-play2_defconfig b/configs/wetek-play2_defconfig @@ -14,7 +14,7 @@ new file mode 100644 index 0000000000..f218ba0e0e --- /dev/null +++ b/configs/wetek-play2_defconfig -@@ -0,0 +1,69 @@ +@@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_SYS_BOARD="wetek-gxbb" +CONFIG_ARCH_MESON=y @@ -28,6 +28,8 @@ index 0000000000..f218ba0e0e +CONFIG_IDENT_STRING=" wetek-play2" +CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-wetek-play2" +CONFIG_DEBUG_UART=y ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 +CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_MISC_INIT_R=y diff --git a/projects/Amlogic/patches/u-boot/u-boot-0010-WIP-boards-amlogic-add-Radxa-Zero2-defconfig.patch b/projects/Amlogic/patches/u-boot/u-boot-0010-WIP-boards-amlogic-add-Radxa-Zero2-defconfig.patch index 8ef99ea12c..188ea49478 100644 --- a/projects/Amlogic/patches/u-boot/u-boot-0010-WIP-boards-amlogic-add-Radxa-Zero2-defconfig.patch +++ b/projects/Amlogic/patches/u-boot/u-boot-0010-WIP-boards-amlogic-add-Radxa-Zero2-defconfig.patch @@ -8,8 +8,8 @@ Add a defconfig for the Radxa Zero2 SBC, using an Amlogic A311D chip. Signed-off-by: Christian Hewitt --- board/amlogic/w400/MAINTAINERS | 1 + - configs/radxa-zero2_defconfig | 72 ++++++++++++++++++++++++++++++++++ - 2 files changed, 73 insertions(+) + configs/radxa-zero2_defconfig | 74 ++++++++++++++++++++++++++++++++++ + 2 files changed, 75 insertions(+) create mode 100644 configs/radxa-zero2_defconfig diff --git a/board/amlogic/w400/MAINTAINERS b/board/amlogic/w400/MAINTAINERS @@ -27,7 +27,7 @@ new file mode 100644 index 0000000000..e9bd2a4f13 --- /dev/null +++ b/configs/radxa-zero2_defconfig -@@ -0,0 +1,72 @@ +@@ -0,0 +1,74 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x01000000 @@ -41,6 +41,8 @@ index 0000000000..e9bd2a4f13 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_IDENT_STRING=" radxa-zero2" +CONFIG_DEBUG_UART=y ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 +CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_MISC_INIT_R=y diff --git a/projects/Amlogic/patches/u-boot/u-boot-0013-WIP-boards-amlogic-add-Beelink-GT1-defconfig.patch b/projects/Amlogic/patches/u-boot/u-boot-0013-WIP-boards-amlogic-add-Beelink-GT1-defconfig.patch index 5c013dbc33..6cb091a49f 100644 --- a/projects/Amlogic/patches/u-boot/u-boot-0013-WIP-boards-amlogic-add-Beelink-GT1-defconfig.patch +++ b/projects/Amlogic/patches/u-boot/u-boot-0013-WIP-boards-amlogic-add-Beelink-GT1-defconfig.patch @@ -7,8 +7,8 @@ Add a board config for Beelink GT1 devices Signed-off-by: Christian Hewitt --- - configs/beelink-gt1_defconfig | 69 +++++++++++++++++++++++++++++++++++ - 1 file changed, 69 insertions(+) + configs/beelink-gt1_defconfig | 71 +++++++++++++++++++++++++++++++++++ + 1 file changed, 71 insertions(+) create mode 100644 configs/beelink-gt1_defconfig diff --git a/configs/beelink-gt1_defconfig b/configs/beelink-gt1_defconfig @@ -16,7 +16,7 @@ new file mode 100644 index 0000000000..6f6051b675 --- /dev/null +++ b/configs/beelink-gt1_defconfig -@@ -0,0 +1,69 @@ +@@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x01000000 @@ -30,6 +30,8 @@ index 0000000000..6f6051b675 +CONFIG_IDENT_STRING=" beelink-gt1" +CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_DEBUG_UART=y ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 +CONFIG_REMAKE_ELF=y +CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set From c7fe617cd28b423ac5664aee50324c5da3a2f506 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Mon, 5 Sep 2022 09:42:11 +0000 Subject: [PATCH 04/29] u-boot-tools: use u-boot download and version --- packages/tools/u-boot-tools/package.mk | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/packages/tools/u-boot-tools/package.mk b/packages/tools/u-boot-tools/package.mk index 1a5ce0b742..95918392d3 100644 --- a/packages/tools/u-boot-tools/package.mk +++ b/packages/tools/u-boot-tools/package.mk @@ -2,13 +2,18 @@ # Copyright (C) 2019-present Team LibreELEC (https://libreelec.tv) PKG_NAME="u-boot-tools" -PKG_VERSION="2022.07" -PKG_SHA256="92b08eb49c24da14c1adbf70a71ae8f37cc53eeb4230e859ad8b6733d13dcf5e" +PKG_VERSION="$(get_pkg_version u-boot)" PKG_LICENSE="GPL" PKG_SITE="https://www.denx.de/wiki/U-Boot" -PKG_URL="https://ftp.denx.de/pub/u-boot/u-boot-${PKG_VERSION}.tar.bz2" +PKG_URL="" PKG_DEPENDS_HOST="ccache:host bison:host flex:host openssl:host pkg-config:host" PKG_LONGDESC="Das U-Boot is a cross-platform bootloader for embedded systems." +PKG_DEPENDS_UNPACK+=" u-boot" + +unpack() { + mkdir -p ${PKG_BUILD} + tar --strip-components=1 -xf ${SOURCES}/u-boot/u-boot-${PKG_VERSION}.tar.bz2 -C ${PKG_BUILD} +} make_host() { make qemu-x86_64_defconfig HOSTCC="${HOST_CC}" HOSTCFLAGS="-I${TOOLCHAIN}/include" HOSTLDFLAGS="${HOST_LDFLAGS}" From 886f59472bb88a1e3db845267d5385287e0780c5 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Mon, 3 Oct 2022 10:48:55 +0000 Subject: [PATCH 05/29] u-boot: update to 2022.10 --- packages/tools/u-boot/package.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/packages/tools/u-boot/package.mk b/packages/tools/u-boot/package.mk index adf6461cff..c7c3f1424f 100644 --- a/packages/tools/u-boot/package.mk +++ b/packages/tools/u-boot/package.mk @@ -3,8 +3,8 @@ # Copyright (C) 2017-present Team LibreELEC (https://libreelec.tv) PKG_NAME="u-boot" -PKG_VERSION="2022.07" -PKG_SHA256="92b08eb49c24da14c1adbf70a71ae8f37cc53eeb4230e859ad8b6733d13dcf5e" +PKG_VERSION="2022.10" +PKG_SHA256="50b4482a505bc281ba8470c399a3c26e145e29b23500bc35c50debd7fa46bdf8" PKG_ARCH="arm aarch64" PKG_LICENSE="GPL" PKG_SITE="https://www.denx.de/wiki/U-Boot" From dfddef788f592c5f8bf493151c92c7d6726d774e Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Mon, 19 Sep 2022 00:27:26 +0000 Subject: [PATCH 06/29] Revert "linux: add ncurses as target depend" This reverts commit 202fbfc4d1ff62e122f7495ea5b0b9b4fe01c3b0. --- packages/linux/package.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/packages/linux/package.mk b/packages/linux/package.mk index 776676a01d..7f6bb124db 100644 --- a/packages/linux/package.mk +++ b/packages/linux/package.mk @@ -6,7 +6,7 @@ PKG_NAME="linux" PKG_LICENSE="GPL" PKG_SITE="http://www.kernel.org" PKG_DEPENDS_HOST="ccache:host rsync:host" -PKG_DEPENDS_TARGET="linux:host kmod:host xz:host keyutils ncurses openssl:host ${KERNEL_EXTRA_DEPENDS_TARGET}" +PKG_DEPENDS_TARGET="linux:host kmod:host xz:host keyutils openssl:host ${KERNEL_EXTRA_DEPENDS_TARGET}" PKG_NEED_UNPACK="${LINUX_DEPENDS} $(get_pkg_directory initramfs) $(get_pkg_variable initramfs PKG_NEED_UNPACK)" PKG_LONGDESC="This package contains a precompiled kernel image and the modules." PKG_IS_KERNEL_PKG="yes" From 7487a3f54bf0dcba2944422056bd81fe8995b574 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Mon, 15 Aug 2022 22:55:18 +0000 Subject: [PATCH 07/29] linux (Allwinner): rebase patches for 6.0-rc2 --- .../0019-media-cedrus-hevc-tiles-hack.patch | 175 ------------------ ...edrus-hevc-Improve-buffer-management.patch | 5 +- ...pi-hevc-add-fields-needed-for-rkvdec.patch | 61 ------ ...media-uapi-hevc-tiles-and-num_slices.patch | 23 ++- .../linux/0055-WIp-10-bit-HEVC-support.patch | 2 +- ...63-HACK-SW-CEC-implementation-for-H3.patch | 18 +- .../0092-media-Add-P010-tiled-format.patch | 52 ------ .../linux/0093-media-Add-P010-format.patch | 51 ----- ...ro-Support-format-filtering-by-depth.patch | 151 --------------- ...postproc-Fix-buffer-size-calculation.patch | 91 --------- ...stproc-Fix-legacy-regs-configuration.patch | 56 ------ ...antro-Store-VP9-bit-depth-in-context.patch | 61 ------ ...-hantro-sunxi-Enable-10-bit-decoding.patch | 60 ------ ...tproc-Properly-calculate-chroma-offs.patch | 36 ---- 14 files changed, 18 insertions(+), 824 deletions(-) delete mode 100644 projects/Allwinner/patches/linux/0019-media-cedrus-hevc-tiles-hack.patch delete mode 100644 projects/Allwinner/patches/linux/0037-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch delete mode 100644 projects/Allwinner/patches/linux/0092-media-Add-P010-tiled-format.patch delete mode 100644 projects/Allwinner/patches/linux/0093-media-Add-P010-format.patch delete mode 100644 projects/Allwinner/patches/linux/0094-media-hantro-Support-format-filtering-by-depth.patch delete mode 100644 projects/Allwinner/patches/linux/0095-media-hantro-postproc-Fix-buffer-size-calculation.patch delete mode 100644 projects/Allwinner/patches/linux/0096-media-hantro-postproc-Fix-legacy-regs-configuration.patch delete mode 100644 projects/Allwinner/patches/linux/0097-media-hantro-Store-VP9-bit-depth-in-context.patch delete mode 100644 projects/Allwinner/patches/linux/0098-media-hantro-sunxi-Enable-10-bit-decoding.patch delete mode 100644 projects/Allwinner/patches/linux/0099-media-hantro-postproc-Properly-calculate-chroma-offs.patch diff --git a/projects/Allwinner/patches/linux/0019-media-cedrus-hevc-tiles-hack.patch b/projects/Allwinner/patches/linux/0019-media-cedrus-hevc-tiles-hack.patch deleted file mode 100644 index 2a025868ee..0000000000 --- a/projects/Allwinner/patches/linux/0019-media-cedrus-hevc-tiles-hack.patch +++ /dev/null @@ -1,175 +0,0 @@ -From 9e203d78974aa445086dbe6b667e49b3f00d36d0 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 26 Oct 2019 21:23:55 +0200 -Subject: [PATCH 27/44] media: cedrus: hevc: tiles hack - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/sunxi/cedrus/cedrus.h | 2 + - .../staging/media/sunxi/cedrus/cedrus_h265.c | 93 +++++++++++++++++-- - include/media/hevc-ctrls.h | 5 +- - 3 files changed, 93 insertions(+), 7 deletions(-) - ---- a/drivers/staging/media/sunxi/cedrus/cedrus.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -144,6 +144,8 @@ struct cedrus_ctx { - ssize_t mv_col_buf_unit_size; - void *neighbor_info_buf; - dma_addr_t neighbor_info_buf_addr; -+ void *entry_points_buf; -+ dma_addr_t entry_points_buf_addr; - } h265; - struct { - unsigned int last_frame_p_type; ---- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c -@@ -301,6 +301,61 @@ static void cedrus_h265_write_scaling_li - } - } - -+static void write_entry_point_list(struct cedrus_ctx *ctx, -+ struct cedrus_run *run, -+ unsigned int ctb_addr_x, -+ unsigned int ctb_addr_y) -+{ -+ const struct v4l2_ctrl_hevc_slice_params *slice_params; -+ const struct v4l2_ctrl_hevc_pps *pps; -+ struct cedrus_dev *dev = ctx->dev; -+ int i, x, tx, y, ty; -+ u32 *entry_points; -+ -+ pps = run->h265.pps; -+ slice_params = run->h265.slice_params; -+ -+ for (x = 0, tx = 0; tx < pps->num_tile_columns_minus1 + 1; tx++) { -+ if (x + pps->column_width_minus1[tx] + 1 > ctb_addr_x) -+ break; -+ -+ x += pps->column_width_minus1[tx] + 1; -+ } -+ -+ for (y = 0, ty = 0; ty < pps->num_tile_rows_minus1 + 1; ty++) { -+ if (y + pps->row_height_minus1[ty] + 1 > ctb_addr_y) -+ break; -+ -+ y += pps->row_height_minus1[ty] + 1; -+ } -+ -+ cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, (y << 16) | (x << 0)); -+ cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, -+ ((y + pps->row_height_minus1[ty]) << 16) | -+ ((x + pps->column_width_minus1[tx]) << 0)); -+ -+ entry_points = ctx->codec.h265.entry_points_buf; -+ if (pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED) { -+ for (i = 0; i < slice_params->num_entry_point_offsets; i++) -+ entry_points[i] = slice_params->entry_point_offset_minus1[i] + 1; -+ } else { -+ for (i = 0; i < slice_params->num_entry_point_offsets; i++) { -+ if (tx + 1 >= pps->num_tile_columns_minus1 + 1) { -+ x = 0; -+ tx = 0; -+ y += pps->row_height_minus1[ty++] + 1; -+ } else { -+ x += pps->column_width_minus1[tx++] + 1; -+ } -+ -+ entry_points[i * 4 + 0] = slice_params->entry_point_offset_minus1[i] + 1; -+ entry_points[i * 4 + 1] = 0x0; -+ entry_points[i * 4 + 2] = (y << 16) | (x << 0); -+ entry_points[i * 4 + 3] = ((y + pps->row_height_minus1[ty]) << 16) | ((x + pps->column_width_minus1[tx]) << 0); -+ } -+ } -+} -+ - static void cedrus_h265_setup(struct cedrus_ctx *ctx, - struct cedrus_run *run) - { -@@ -312,6 +367,7 @@ static void cedrus_h265_setup(struct ced - const struct v4l2_hevc_pred_weight_table *pred_weight_table; - unsigned int width_in_ctb_luma, ctb_size_luma; - unsigned int log2_max_luma_coding_block_size; -+ unsigned int ctb_addr_x, ctb_addr_y; - dma_addr_t src_buf_addr; - dma_addr_t src_buf_end_addr; - u32 chroma_log2_weight_denom; -@@ -390,12 +446,19 @@ static void cedrus_h265_setup(struct ced - cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg); - - /* Coding tree block address */ -- reg = VE_DEC_H265_DEC_CTB_ADDR_X(slice_params->slice_segment_addr % width_in_ctb_luma); -- reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(slice_params->slice_segment_addr / width_in_ctb_luma); -+ ctb_addr_x = slice_params->slice_segment_addr % width_in_ctb_luma; -+ ctb_addr_y = slice_params->slice_segment_addr / width_in_ctb_luma; -+ reg = VE_DEC_H265_DEC_CTB_ADDR_X(ctb_addr_x); -+ reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(ctb_addr_y); - cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg); - -- cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0); -- cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0); -+ if ((pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) || -+ (pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED)) { -+ write_entry_point_list(ctx, run, ctb_addr_x, ctb_addr_y); -+ } else { -+ cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0); -+ cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0); -+ } - - /* Clear the number of correctly-decoded coding tree blocks. */ - if (ctx->fh.m2m_ctx->new_frame) -@@ -499,7 +562,9 @@ static void cedrus_h265_setup(struct ced - V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED, - pps->flags); - -- /* TODO: VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED */ -+ reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED, -+ V4L2_HEVC_PPS_FLAG_TILES_ENABLED, -+ pps->flags); - - reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED, - V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED, -@@ -575,12 +640,14 @@ static void cedrus_h265_setup(struct ced - - chroma_log2_weight_denom = pred_weight_table->luma_log2_weight_denom + - pred_weight_table->delta_chroma_log2_weight_denom; -- reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(0) | -+ reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(slice_params->num_entry_point_offsets) | - VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(chroma_log2_weight_denom) | - VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(pred_weight_table->luma_log2_weight_denom); - - cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO2, reg); - -+ cedrus_write(dev, VE_DEC_H265_ENTRY_POINT_OFFSET_ADDR, ctx->codec.h265.entry_points_buf_addr >> 8); -+ - /* Decoded picture size. */ - - reg = VE_DEC_H265_DEC_PIC_SIZE_WIDTH(ctx->src_fmt.width) | -@@ -674,6 +741,18 @@ static int cedrus_h265_start(struct cedr - if (!ctx->codec.h265.neighbor_info_buf) - return -ENOMEM; - -+ ctx->codec.h265.entry_points_buf = -+ dma_alloc_coherent(dev->dev, CEDRUS_H265_ENTRY_POINTS_BUF_SIZE, -+ &ctx->codec.h265.entry_points_buf_addr, -+ GFP_KERNEL); -+ if (!ctx->codec.h265.entry_points_buf) { -+ dma_free_attrs(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, -+ ctx->codec.h265.neighbor_info_buf, -+ ctx->codec.h265.neighbor_info_buf_addr, -+ DMA_ATTR_NO_KERNEL_MAPPING); -+ return -ENOMEM; -+ } -+ - return 0; - } - -@@ -693,6 +772,9 @@ static void cedrus_h265_stop(struct cedr - ctx->codec.h265.neighbor_info_buf, - ctx->codec.h265.neighbor_info_buf_addr, - DMA_ATTR_NO_KERNEL_MAPPING); -+ dma_free_coherent(dev->dev, CEDRUS_H265_ENTRY_POINTS_BUF_SIZE, -+ ctx->codec.h265.entry_points_buf, -+ ctx->codec.h265.entry_points_buf_addr); - } - - static void cedrus_h265_trigger(struct cedrus_ctx *ctx) diff --git a/projects/Allwinner/patches/linux/0021-media-cedrus-hevc-Improve-buffer-management.patch b/projects/Allwinner/patches/linux/0021-media-cedrus-hevc-Improve-buffer-management.patch index 3d13ce4333..eae69f0da3 100644 --- a/projects/Allwinner/patches/linux/0021-media-cedrus-hevc-Improve-buffer-management.patch +++ b/projects/Allwinner/patches/linux/0021-media-cedrus-hevc-Improve-buffer-management.patch @@ -133,7 +133,7 @@ index 4b01d3881214..4d425196d415 100644 } } -@@ -388,37 +428,6 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, +@@ -388,36 +428,6 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, width_in_ctb_luma = DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma); @@ -163,8 +163,7 @@ index 4b01d3881214..4d425196d415 100644 - GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING); - if (!ctx->codec.h265.mv_col_buf) { - ctx->codec.h265.mv_col_buf_size = 0; -- // TODO: Abort the process here. -- return; +- return -ENOMEM; - } - } - diff --git a/projects/Allwinner/patches/linux/0037-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch b/projects/Allwinner/patches/linux/0037-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch deleted file mode 100644 index 1ece453403..0000000000 --- a/projects/Allwinner/patches/linux/0037-WIP-media-uapi-hevc-add-fields-needed-for-rkvdec.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 15:03:46 +0000 -Subject: [PATCH] WIP: media: uapi: hevc: add fields needed for rkvdec - -NOTE: these fields are used by rkvdec hevc backend - -Signed-off-by: Jonas Karlman ---- - include/media/hevc-ctrls.h | 16 ++++++++++++---- - 1 file changed, 12 insertions(+), 4 deletions(-) - ---- a/include/media/hevc-ctrls.h -+++ b/include/media/hevc-ctrls.h -@@ -58,6 +58,8 @@ enum v4l2_mpeg_video_hevc_start_code { - /* The controls are not stable at the moment and will likely be reworked. */ - struct v4l2_ctrl_hevc_sps { - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ -+ __u8 video_parameter_set_id; -+ __u8 seq_parameter_set_id; - __u16 pic_width_in_luma_samples; - __u16 pic_height_in_luma_samples; - __u8 bit_depth_luma_minus8; -@@ -81,6 +83,8 @@ struct v4l2_ctrl_hevc_sps { - __u8 chroma_format_idc; - __u8 sps_max_sub_layers_minus1; - -+ __u8 padding[6]; -+ - __u64 flags; - }; - -@@ -108,6 +112,7 @@ struct v4l2_ctrl_hevc_sps { - - struct v4l2_ctrl_hevc_pps { - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ -+ __u8 pic_parameter_set_id; - __u8 num_extra_slice_header_bits; - __u8 num_ref_idx_l0_default_active_minus1; - __u8 num_ref_idx_l1_default_active_minus1; -@@ -123,7 +128,7 @@ struct v4l2_ctrl_hevc_pps { - __s8 pps_tc_offset_div2; - __u8 log2_parallel_merge_level_minus2; - -- __u8 padding[4]; -+ __u8 padding; - __u64 flags; - }; - -@@ -202,7 +207,10 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - -- __u8 padding; -+ __u16 short_term_ref_pic_set_size; -+ __u16 long_term_ref_pic_set_size; -+ -+ __u8 padding[4]; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ - struct v4l2_hevc_pred_weight_table pred_weight_table; diff --git a/projects/Allwinner/patches/linux/0038-HACK-media-uapi-hevc-tiles-and-num_slices.patch b/projects/Allwinner/patches/linux/0038-HACK-media-uapi-hevc-tiles-and-num_slices.patch index 0a239a86d8..a20de11186 100644 --- a/projects/Allwinner/patches/linux/0038-HACK-media-uapi-hevc-tiles-and-num_slices.patch +++ b/projects/Allwinner/patches/linux/0038-HACK-media-uapi-hevc-tiles-and-num_slices.patch @@ -4,29 +4,28 @@ Date: Sat, 23 May 2020 15:07:15 +0000 Subject: [PATCH] HACK: media: uapi: hevc: tiles and num_slices --- - include/media/hevc-ctrls.h | 8 ++++++-- + include/uapi/linux/v4l2-controls.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) ---- a/include/media/hevc-ctrls.h -+++ b/include/media/hevc-ctrls.h -@@ -83,7 +83,8 @@ struct v4l2_ctrl_hevc_sps { +--- a/include/uapi/linux/v4l2-controls.h ++++ b/include/uapi/linux/v4l2-controls.h +@@ -2118,7 +2118,8 @@ struct v4l2_ctrl_hevc_sps { __u8 chroma_format_idc; __u8 sps_max_sub_layers_minus1; -- __u8 padding[6]; +- __u8 reserved[6]; + __u8 num_slices; -+ __u8 padding[5]; - ++ __u8 reserved[5]; __u64 flags; }; -@@ -210,7 +211,9 @@ struct v4l2_ctrl_hevc_slice_params { + +@@ -2375,6 +2376,9 @@ struct v4l2_ctrl_hevc_slice_params { __u16 short_term_ref_pic_set_size; __u16 long_term_ref_pic_set_size; -- __u8 padding[4]; -+ __u32 num_entry_point_offsets; + __u32 entry_point_offset_minus1[256]; -+ __u8 padding[8]; - ++ __u8 reserved[8]; ++ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ struct v4l2_hevc_pred_weight_table pred_weight_table; + diff --git a/projects/Allwinner/patches/linux/0055-WIp-10-bit-HEVC-support.patch b/projects/Allwinner/patches/linux/0055-WIp-10-bit-HEVC-support.patch index 05fb6b6954..0dcb9fc2e5 100644 --- a/projects/Allwinner/patches/linux/0055-WIp-10-bit-HEVC-support.patch +++ b/projects/Allwinner/patches/linux/0055-WIp-10-bit-HEVC-support.patch @@ -108,7 +108,7 @@ Signed-off-by: Jernej Skrabec if (!fmt) return -EINVAL; -+ sps = cedrus_find_control_data(ctx, V4L2_CID_MPEG_VIDEO_HEVC_SPS); ++ sps = cedrus_find_control_data(ctx, V4L2_CID_STATELESS_HEVC_SPS); + + /* The 10-bitHEVC decoder needs extra size on the output buffer. */ + extended = ctx->src_fmt.pixelformat == V4L2_PIX_FMT_HEVC_SLICE && diff --git a/projects/Allwinner/patches/linux/0063-HACK-SW-CEC-implementation-for-H3.patch b/projects/Allwinner/patches/linux/0063-HACK-SW-CEC-implementation-for-H3.patch index 1204556f88..7f147e476c 100644 --- a/projects/Allwinner/patches/linux/0063-HACK-SW-CEC-implementation-for-H3.patch +++ b/projects/Allwinner/patches/linux/0063-HACK-SW-CEC-implementation-for-H3.patch @@ -66,7 +66,7 @@ index bffe1b9cd3dc..61c97619cba1 100644 @@ -174,6 +185,8 @@ struct sun8i_hdmi_phy { struct regmap *regs; struct reset_control *rst_phy; - struct sun8i_hdmi_phy_variant *variant; + const struct sun8i_hdmi_phy_variant *variant; + unsigned int disable_cec : 1; + unsigned int bit_bang_cec : 1; }; @@ -182,7 +182,7 @@ index b64d93da651d..e2936e7745b8 100644 static int sun8i_hdmi_phy_probe(struct platform_device *pdev) @@ -690,6 +758,14 @@ static int sun8i_hdmi_phy_probe(struct platform_device *pdev) - phy->variant = (struct sun8i_hdmi_phy_variant *)match->data; + phy->variant = of_device_get_match_data(dev); phy->dev = dev; + phy->disable_cec = of_machine_is_compatible("roofull,beelink-x2") || + of_machine_is_compatible("friendlyarm,nanopi-m1") || @@ -193,15 +193,5 @@ index b64d93da651d..e2936e7745b8 100644 + phy->bit_bang_cec = phy->disable_cec && + !of_machine_is_compatible("roofull,beelink-x2"); - ret = of_address_to_resource(node, 0, &res); - if (ret) { -@@ -768,6 +844,9 @@ static int sun8i_hdmi_phy_remove(struct platform_device *pdev) - { - struct sun8i_hdmi_phy *phy = platform_get_drvdata(pdev); - -+ cec_notifier_cec_adap_unregister(phy->cec_notifier, phy->cec_adapter); -+ cec_unregister_adapter(phy->cec_adapter); -+ - reset_control_put(phy->rst_phy); - - clk_put(phy->clk_pll0); + regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(regs)) diff --git a/projects/Allwinner/patches/linux/0092-media-Add-P010-tiled-format.patch b/projects/Allwinner/patches/linux/0092-media-Add-P010-tiled-format.patch deleted file mode 100644 index 4e26fc37ce..0000000000 --- a/projects/Allwinner/patches/linux/0092-media-Add-P010-tiled-format.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Sun, 27 Feb 2022 08:43:18 +0100 -Subject: [PATCH] media: Add P010 tiled format - -Add P010 tiled format - -Signed-off-by: Ezequiel Garcia -[rebased and updated pixel format name] -Signed-off-by: Jernej Skrabec ---- - drivers/media/v4l2-core/v4l2-common.c | 1 + - drivers/media/v4l2-core/v4l2-ioctl.c | 1 + - include/uapi/linux/videodev2.h | 1 + - 3 files changed, 3 insertions(+) - -diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c -index df34b2a283bc..1db0020e08c0 100644 ---- a/drivers/media/v4l2-core/v4l2-common.c -+++ b/drivers/media/v4l2-core/v4l2-common.c -@@ -277,6 +277,7 @@ const struct v4l2_format_info *v4l2_format_info(u32 format) - - /* Tiled YUV formats */ - { .format = V4L2_PIX_FMT_NV12_4L4, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 2 }, -+ { .format = V4L2_PIX_FMT_P010_4L4, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 4, 0, 0 }, .hdiv = 2, .vdiv = 2 }, - - /* YUV planar formats, non contiguous variant */ - { .format = V4L2_PIX_FMT_YUV420M, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 3, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 2, .vdiv = 2 }, -diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 9ac557b8e146..048f326c57b9 100644 ---- a/drivers/media/v4l2-core/v4l2-ioctl.c -+++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1302,6 +1302,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) - case V4L2_PIX_FMT_NV12_4L4: descr = "Y/CbCr 4:2:0 (4x4 Linear)"; break; - case V4L2_PIX_FMT_NV12_16L16: descr = "Y/CbCr 4:2:0 (16x16 Linear)"; break; - case V4L2_PIX_FMT_NV12_32L32: descr = "Y/CbCr 4:2:0 (32x32 Linear)"; break; -+ case V4L2_PIX_FMT_P010_4L4: descr = "P010 tiled"; break; - case V4L2_PIX_FMT_NV12M: descr = "Y/CbCr 4:2:0 (N-C)"; break; - case V4L2_PIX_FMT_NV21M: descr = "Y/CrCb 4:2:0 (N-C)"; break; - case V4L2_PIX_FMT_NV16M: descr = "Y/CbCr 4:2:2 (N-C)"; break; -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index df8b9c486ba1..772dbadd1a24 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -628,6 +628,7 @@ struct v4l2_pix_format { - #define V4L2_PIX_FMT_NV12_4L4 v4l2_fourcc('V', 'T', '1', '2') /* 12 Y/CbCr 4:2:0 4x4 tiles */ - #define V4L2_PIX_FMT_NV12_16L16 v4l2_fourcc('H', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 16x16 tiles */ - #define V4L2_PIX_FMT_NV12_32L32 v4l2_fourcc('S', 'T', '1', '2') /* 12 Y/CbCr 4:2:0 32x32 tiles */ -+#define V4L2_PIX_FMT_P010_4L4 v4l2_fourcc('T', '0', '1', '0') /* 12 Y/CbCr 4:2:0 10-bit 4x4 macroblocks */ - - /* Tiled YUV formats, non contiguous planes */ - #define V4L2_PIX_FMT_NV12MT v4l2_fourcc('T', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 64x32 tiles */ diff --git a/projects/Allwinner/patches/linux/0093-media-Add-P010-format.patch b/projects/Allwinner/patches/linux/0093-media-Add-P010-format.patch deleted file mode 100644 index ded6ff733f..0000000000 --- a/projects/Allwinner/patches/linux/0093-media-Add-P010-format.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 27 Feb 2022 09:01:00 +0100 -Subject: [PATCH] media: Add P010 format - -Add P010 format, which is commonly used for 10-bit videos. - -Signed-off-by: Jernej Skrabec ---- - drivers/media/v4l2-core/v4l2-common.c | 2 ++ - drivers/media/v4l2-core/v4l2-ioctl.c | 1 + - include/uapi/linux/videodev2.h | 1 + - 3 files changed, 4 insertions(+) - -diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c -index 1db0020e08c0..4ede36546e9c 100644 ---- a/drivers/media/v4l2-core/v4l2-common.c -+++ b/drivers/media/v4l2-core/v4l2-common.c -@@ -275,6 +275,8 @@ const struct v4l2_format_info *v4l2_format_info(u32 format) - { .format = V4L2_PIX_FMT_YUV422P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 2, .vdiv = 1 }, - { .format = V4L2_PIX_FMT_GREY, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 1, .bpp = { 1, 0, 0, 0 }, .hdiv = 1, .vdiv = 1 }, - -+ { .format = V4L2_PIX_FMT_P010, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 4, 0, 0 }, .hdiv = 2, .vdiv = 2 }, -+ - /* Tiled YUV formats */ - { .format = V4L2_PIX_FMT_NV12_4L4, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 2 }, - { .format = V4L2_PIX_FMT_P010_4L4, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 4, 0, 0 }, .hdiv = 2, .vdiv = 2 }, -diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 048f326c57b9..a8d999e23e5b 100644 ---- a/drivers/media/v4l2-core/v4l2-ioctl.c -+++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1295,6 +1295,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) - case V4L2_PIX_FMT_M420: descr = "YUV 4:2:0 (M420)"; break; - case V4L2_PIX_FMT_NV12: descr = "Y/CbCr 4:2:0"; break; - case V4L2_PIX_FMT_NV21: descr = "Y/CrCb 4:2:0"; break; -+ case V4L2_PIX_FMT_P010: descr = "10-bit Y/CbCr 4:2:0"; break; - case V4L2_PIX_FMT_NV16: descr = "Y/CbCr 4:2:2"; break; - case V4L2_PIX_FMT_NV61: descr = "Y/CrCb 4:2:2"; break; - case V4L2_PIX_FMT_NV24: descr = "Y/CbCr 4:4:4"; break; -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index 772dbadd1a24..211bc11a48cb 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -597,6 +597,7 @@ struct v4l2_pix_format { - /* two planes -- one Y, one Cr + Cb interleaved */ - #define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ - #define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */ -+#define V4L2_PIX_FMT_P010 v4l2_fourcc('P', '0', '1', '0') /* 24 Y/CbCr 4:2:0 10-bit */ - #define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */ - #define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */ - #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ diff --git a/projects/Allwinner/patches/linux/0094-media-hantro-Support-format-filtering-by-depth.patch b/projects/Allwinner/patches/linux/0094-media-hantro-Support-format-filtering-by-depth.patch deleted file mode 100644 index 44210226fb..0000000000 --- a/projects/Allwinner/patches/linux/0094-media-hantro-Support-format-filtering-by-depth.patch +++ /dev/null @@ -1,151 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 27 Feb 2022 14:59:04 +0100 -Subject: [PATCH] media: hantro: Support format filtering by depth - -In preparation for supporting 10-bit formats, add mechanism which will -filter formats based on pixel depth. - -Hantro G2 supports only one decoding format natively and that is based -on bit depth of current video frame. Additionally, it makes no sense to -upconvert bitness, so filter those out too. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/hantro/hantro.h | 4 ++ - drivers/staging/media/hantro/hantro_v4l2.c | 48 ++++++++++++++++++++-- - drivers/staging/media/hantro/hantro_v4l2.h | 1 + - 3 files changed, 50 insertions(+), 3 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index 06d0f3597694..c6525ee8d89a 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -227,6 +227,7 @@ struct hantro_dev { - * - * @ctrl_handler: Control handler used to register controls. - * @jpeg_quality: User-specified JPEG compression quality. -+ * @bit_depth: Bit depth of current frame - * - * @codec_ops: Set of operations related to codec mode. - * @postproc: Post-processing context. -@@ -252,6 +253,7 @@ struct hantro_ctx { - - struct v4l2_ctrl_handler ctrl_handler; - int jpeg_quality; -+ int bit_depth; - - const struct hantro_codec_ops *codec_ops; - struct hantro_postproc_ctx postproc; -@@ -278,6 +280,7 @@ struct hantro_ctx { - * @enc_fmt: Format identifier for encoder registers. - * @frmsize: Supported range of frame sizes (only for bitstream formats). - * @postprocessed: Indicates if this format needs the post-processor. -+ * @match_depth: Indicates if format bit depth must match video bit depth - */ - struct hantro_fmt { - char *name; -@@ -288,6 +291,7 @@ struct hantro_fmt { - enum hantro_enc_fmt enc_fmt; - struct v4l2_frmsize_stepwise frmsize; - bool postprocessed; -+ bool match_depth; - }; - - struct hantro_reg { -diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c -index e595905b3bd7..1214fa2f64ae 100644 ---- a/drivers/staging/media/hantro/hantro_v4l2.c -+++ b/drivers/staging/media/hantro/hantro_v4l2.c -@@ -64,6 +64,42 @@ hantro_get_postproc_formats(const struct hantro_ctx *ctx, - return ctx->dev->variant->postproc_fmts; - } - -+int hantro_get_formath_depth(u32 fourcc) -+{ -+ switch (fourcc) { -+ case V4L2_PIX_FMT_P010: -+ case V4L2_PIX_FMT_P010_4L4: -+ return 10; -+ default: -+ return 8; -+ } -+} -+ -+static bool -+hantro_check_depth_match(const struct hantro_ctx *ctx, -+ const struct hantro_fmt *fmt) -+{ -+ int fmt_depth, ctx_depth = 8; -+ -+ if (!fmt->match_depth && !fmt->postprocessed) -+ return true; -+ -+ /* 0 means default depth, which is 8 */ -+ if (ctx->bit_depth) -+ ctx_depth = ctx->bit_depth; -+ -+ fmt_depth = hantro_get_formath_depth(fmt->fourcc); -+ -+ /* -+ * Allow only downconversion for postproc formats for now. -+ * It may be possible to relax that on some HW. -+ */ -+ if (!fmt->match_depth) -+ return fmt_depth <= ctx_depth; -+ -+ return fmt_depth == ctx_depth; -+} -+ - static const struct hantro_fmt * - hantro_find_format(const struct hantro_ctx *ctx, u32 fourcc) - { -@@ -91,7 +127,8 @@ hantro_get_default_fmt(const struct hantro_ctx *ctx, bool bitstream) - formats = hantro_get_formats(ctx, &num_fmts); - for (i = 0; i < num_fmts; i++) { - if (bitstream == (formats[i].codec_mode != -- HANTRO_MODE_NONE)) -+ HANTRO_MODE_NONE) && -+ hantro_check_depth_match(ctx, &formats[i])) - return &formats[i]; - } - return NULL; -@@ -163,11 +200,13 @@ static int vidioc_enum_fmt(struct file *file, void *priv, - formats = hantro_get_formats(ctx, &num_fmts); - for (i = 0; i < num_fmts; i++) { - bool mode_none = formats[i].codec_mode == HANTRO_MODE_NONE; -+ fmt = &formats[i]; - - if (skip_mode_none == mode_none) - continue; -+ if (!hantro_check_depth_match(ctx, fmt)) -+ continue; - if (j == f->index) { -- fmt = &formats[i]; - f->pixelformat = fmt->fourcc; - return 0; - } -@@ -183,8 +222,11 @@ static int vidioc_enum_fmt(struct file *file, void *priv, - return -EINVAL; - formats = hantro_get_postproc_formats(ctx, &num_fmts); - for (i = 0; i < num_fmts; i++) { -+ fmt = &formats[i]; -+ -+ if (!hantro_check_depth_match(ctx, fmt)) -+ continue; - if (j == f->index) { -- fmt = &formats[i]; - f->pixelformat = fmt->fourcc; - return 0; - } -diff --git a/drivers/staging/media/hantro/hantro_v4l2.h b/drivers/staging/media/hantro/hantro_v4l2.h -index 18bc682c8556..f4a5905ed518 100644 ---- a/drivers/staging/media/hantro/hantro_v4l2.h -+++ b/drivers/staging/media/hantro/hantro_v4l2.h -@@ -22,5 +22,6 @@ extern const struct v4l2_ioctl_ops hantro_ioctl_ops; - extern const struct vb2_ops hantro_queue_ops; - - void hantro_reset_fmts(struct hantro_ctx *ctx); -+int hantro_get_formath_depth(u32 fourcc); - - #endif /* HANTRO_V4L2_H_ */ diff --git a/projects/Allwinner/patches/linux/0095-media-hantro-postproc-Fix-buffer-size-calculation.patch b/projects/Allwinner/patches/linux/0095-media-hantro-postproc-Fix-buffer-size-calculation.patch deleted file mode 100644 index 7e690bd58d..0000000000 --- a/projects/Allwinner/patches/linux/0095-media-hantro-postproc-Fix-buffer-size-calculation.patch +++ /dev/null @@ -1,91 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 27 Feb 2022 15:08:34 +0100 -Subject: [PATCH] media: hantro: postproc: Fix buffer size calculation - -When allocating aux buffers for postprocessing, it's assumed that base -buffer size is the same as that of output. Coincidentally, that's true -most of the time, but not always. 10-bit source also needs aux buffer -size which is appropriate for 10-bit native format, even if the output -format is 8-bit. Similarly, mv sizes and other extra buffer size also -depends on source width/height, not destination. - -Signed-off-by: Jernej Skrabec ---- - .../staging/media/hantro/hantro_postproc.c | 24 +++++++++++++------ - drivers/staging/media/hantro/hantro_v4l2.c | 2 +- - drivers/staging/media/hantro/hantro_v4l2.h | 2 ++ - 3 files changed, 20 insertions(+), 8 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index 248abe5423f0..1a76628d5754 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -12,6 +12,7 @@ - #include "hantro_hw.h" - #include "hantro_g1_regs.h" - #include "hantro_g2_regs.h" -+#include "hantro_v4l2.h" - - #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \ - { \ -@@ -137,18 +138,27 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx) - struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; - struct vb2_queue *cap_queue = &m2m_ctx->cap_q_ctx.q; - unsigned int num_buffers = cap_queue->num_buffers; -+ struct v4l2_pix_format_mplane pix_mp; -+ const struct hantro_fmt *fmt; - unsigned int i, buf_size; - -- buf_size = ctx->dst_fmt.plane_fmt[0].sizeimage; -+ /* this should always pick native format */ -+ fmt = hantro_get_default_fmt(ctx, false); -+ if (!fmt) -+ return -EINVAL; -+ v4l2_fill_pixfmt_mp(&pix_mp, fmt->fourcc, ctx->src_fmt.width, -+ ctx->src_fmt.height); -+ -+ buf_size = pix_mp.plane_fmt[0].sizeimage; - if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE) -- buf_size += hantro_h264_mv_size(ctx->dst_fmt.width, -- ctx->dst_fmt.height); -+ buf_size += hantro_h264_mv_size(pix_mp.width, -+ pix_mp.height); - else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME) -- buf_size += hantro_vp9_mv_size(ctx->dst_fmt.width, -- ctx->dst_fmt.height); -+ buf_size += hantro_vp9_mv_size(pix_mp.width, -+ pix_mp.height); - else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE) -- buf_size += hantro_hevc_mv_size(ctx->dst_fmt.width, -- ctx->dst_fmt.height); -+ buf_size += hantro_hevc_mv_size(pix_mp.width, -+ pix_mp.height); - - for (i = 0; i < num_buffers; ++i) { - struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i]; -diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c -index 1214fa2f64ae..69d2a108e1e6 100644 ---- a/drivers/staging/media/hantro/hantro_v4l2.c -+++ b/drivers/staging/media/hantro/hantro_v4l2.c -@@ -118,7 +118,7 @@ hantro_find_format(const struct hantro_ctx *ctx, u32 fourcc) - return NULL; - } - --static const struct hantro_fmt * -+const struct hantro_fmt * - hantro_get_default_fmt(const struct hantro_ctx *ctx, bool bitstream) - { - const struct hantro_fmt *formats; -diff --git a/drivers/staging/media/hantro/hantro_v4l2.h b/drivers/staging/media/hantro/hantro_v4l2.h -index f4a5905ed518..cc9a645be886 100644 ---- a/drivers/staging/media/hantro/hantro_v4l2.h -+++ b/drivers/staging/media/hantro/hantro_v4l2.h -@@ -23,5 +23,7 @@ extern const struct vb2_ops hantro_queue_ops; - - void hantro_reset_fmts(struct hantro_ctx *ctx); - int hantro_get_formath_depth(u32 fourcc); -+const struct hantro_fmt * -+hantro_get_default_fmt(const struct hantro_ctx *ctx, bool bitstream); - - #endif /* HANTRO_V4L2_H_ */ diff --git a/projects/Allwinner/patches/linux/0096-media-hantro-postproc-Fix-legacy-regs-configuration.patch b/projects/Allwinner/patches/linux/0096-media-hantro-postproc-Fix-legacy-regs-configuration.patch deleted file mode 100644 index d5dc40d44d..0000000000 --- a/projects/Allwinner/patches/linux/0096-media-hantro-postproc-Fix-legacy-regs-configuration.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 27 Feb 2022 15:17:03 +0100 -Subject: [PATCH] media: hantro: postproc: Fix legacy regs configuration - -Some postproc legacy registers were set in VP9 code. Move them to -postproc and fix their value. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/hantro/hantro_g2_vp9_dec.c | 8 -------- - drivers/staging/media/hantro/hantro_postproc.c | 10 ++++++++++ - 2 files changed, 10 insertions(+), 8 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -index 91c21b634fab..c9cb11fd95af 100644 ---- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -@@ -515,16 +515,8 @@ static void - config_bit_depth(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) - { - if (ctx->dev->variant->legacy_regs) { -- u8 pp_shift = 0; -- - hantro_reg_write(ctx->dev, &g2_bit_depth_y, dec_params->bit_depth); - hantro_reg_write(ctx->dev, &g2_bit_depth_c, dec_params->bit_depth); -- hantro_reg_write(ctx->dev, &g2_rs_out_bit_depth, dec_params->bit_depth); -- -- if (dec_params->bit_depth > 8) -- pp_shift = 16 - dec_params->bit_depth; -- -- hantro_reg_write(ctx->dev, &g2_pp_pix_shift, pp_shift); - hantro_reg_write(ctx->dev, &g2_pix_shift, 0); - } else { - hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8); -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index 1a76628d5754..11ae663f11b7 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -113,6 +113,16 @@ static void hantro_postproc_g2_enable(struct hantro_ctx *ctx) - hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma); - hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + chroma_offset); - } -+ if (ctx->dev->variant->legacy_regs) { -+ int out_depth = hantro_get_formath_depth(ctx->dst_fmt.pixelformat); -+ u8 pp_shift = 0; -+ -+ if (out_depth > 8) -+ pp_shift = 16 - out_depth; -+ -+ hantro_reg_write(ctx->dev, &g2_rs_out_bit_depth, out_depth); -+ hantro_reg_write(ctx->dev, &g2_pp_pix_shift, pp_shift); -+ } - hantro_reg_write(vpu, &g2_out_rs_e, 1); - } - diff --git a/projects/Allwinner/patches/linux/0097-media-hantro-Store-VP9-bit-depth-in-context.patch b/projects/Allwinner/patches/linux/0097-media-hantro-Store-VP9-bit-depth-in-context.patch deleted file mode 100644 index 09291d7d11..0000000000 --- a/projects/Allwinner/patches/linux/0097-media-hantro-Store-VP9-bit-depth-in-context.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 27 Feb 2022 15:19:34 +0100 -Subject: [PATCH] media: hantro: Store VP9 bit depth in context - -Now that we have proper infrastructure for postprocessing 10-bit -formats, store VP9 bit depth in context. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/hantro/hantro_drv.c | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c -index 6a51f39dde56..305090365e74 100644 ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -320,6 +320,24 @@ static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl) - return 0; - } - -+static int hantro_vp9_s_ctrl(struct v4l2_ctrl *ctrl) -+{ -+ struct hantro_ctx *ctx; -+ -+ ctx = container_of(ctrl->handler, -+ struct hantro_ctx, ctrl_handler); -+ -+ switch (ctrl->id) { -+ case V4L2_CID_STATELESS_VP9_FRAME: -+ ctx->bit_depth = ctrl->p_new.p_vp9_frame->bit_depth; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ - static const struct v4l2_ctrl_ops hantro_ctrl_ops = { - .try_ctrl = hantro_try_ctrl, - }; -@@ -332,6 +350,10 @@ static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = { - .s_ctrl = hantro_hevc_s_ctrl, - }; - -+static const struct v4l2_ctrl_ops hantro_vp9_ctrl_ops = { -+ .s_ctrl = hantro_vp9_s_ctrl, -+}; -+ - static const struct hantro_ctrl controls[] = { - { - .codec = HANTRO_JPEG_ENCODER, -@@ -478,6 +500,7 @@ static const struct hantro_ctrl controls[] = { - .codec = HANTRO_VP9_DECODER, - .cfg = { - .id = V4L2_CID_STATELESS_VP9_FRAME, -+ .ops = &hantro_vp9_ctrl_ops, - }, - }, { - .codec = HANTRO_VP9_DECODER, diff --git a/projects/Allwinner/patches/linux/0098-media-hantro-sunxi-Enable-10-bit-decoding.patch b/projects/Allwinner/patches/linux/0098-media-hantro-sunxi-Enable-10-bit-decoding.patch deleted file mode 100644 index 6065b8059b..0000000000 --- a/projects/Allwinner/patches/linux/0098-media-hantro-sunxi-Enable-10-bit-decoding.patch +++ /dev/null @@ -1,60 +0,0 @@ -From e4b8d13f19b988a17de0226f3f8a7d03e72eac37 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 6 Jul 2022 19:29:01 +0100 -Subject: [PATCH] media: hantro: sunxi: Enable 10-bit decoding - -Now that infrastructure for 10-bit decoding exists, enable it for -Allwinner H6. - -Tested-by: Benjamin Gaignard -Signed-off-by: Jernej Skrabec -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - drivers/staging/media/hantro/sunxi_vpu_hw.c | 27 +++++++++++++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/drivers/staging/media/hantro/sunxi_vpu_hw.c b/drivers/staging/media/hantro/sunxi_vpu_hw.c -index fbeac81e59e133..02ce8b064a8f0c 100644 ---- a/drivers/staging/media/hantro/sunxi_vpu_hw.c -+++ b/drivers/staging/media/hantro/sunxi_vpu_hw.c -@@ -23,12 +23,39 @@ static const struct hantro_fmt sunxi_vpu_postproc_fmts[] = { - .step_height = 32, - }, - }, -+ { -+ .fourcc = V4L2_PIX_FMT_P010, -+ .codec_mode = HANTRO_MODE_NONE, -+ .postprocessed = true, -+ .frmsize = { -+ .min_width = FMT_MIN_WIDTH, -+ .max_width = FMT_UHD_WIDTH, -+ .step_width = 32, -+ .min_height = FMT_MIN_HEIGHT, -+ .max_height = FMT_UHD_HEIGHT, -+ .step_height = 32, -+ }, -+ }, - }; - - static const struct hantro_fmt sunxi_vpu_dec_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_NV12_4L4, - .codec_mode = HANTRO_MODE_NONE, -+ .match_depth = true, -+ .frmsize = { -+ .min_width = FMT_MIN_WIDTH, -+ .max_width = FMT_UHD_WIDTH, -+ .step_width = 32, -+ .min_height = FMT_MIN_HEIGHT, -+ .max_height = FMT_UHD_HEIGHT, -+ .step_height = 32, -+ }, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_P010_4L4, -+ .codec_mode = HANTRO_MODE_NONE, -+ .match_depth = true, - .frmsize = { - .min_width = FMT_MIN_WIDTH, - .max_width = FMT_UHD_WIDTH, diff --git a/projects/Allwinner/patches/linux/0099-media-hantro-postproc-Properly-calculate-chroma-offs.patch b/projects/Allwinner/patches/linux/0099-media-hantro-postproc-Properly-calculate-chroma-offs.patch deleted file mode 100644 index b05320ce27..0000000000 --- a/projects/Allwinner/patches/linux/0099-media-hantro-postproc-Properly-calculate-chroma-offs.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 27 Feb 2022 17:59:18 +0100 -Subject: [PATCH] media: hantro: postproc: Properly calculate chroma offset - -Currently chroma offset calculation assumes only 1 byte per luma, with -no consideration for stride. - -Take necessary information from destination pixel format which makes -calculation completely universal. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/hantro/hantro_postproc.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index 11ae663f11b7..d8358d3289dc 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -105,12 +105,14 @@ static void hantro_postproc_g2_enable(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; - struct vb2_v4l2_buffer *dst_buf; -- size_t chroma_offset = ctx->dst_fmt.width * ctx->dst_fmt.height; -+ size_t chroma_offset; - int down_scale = down_scale_factor(ctx); - dma_addr_t dst_dma; - - dst_buf = hantro_get_dst_buf(ctx); - dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ chroma_offset = ctx->dst_fmt.plane_fmt[0].bytesperline * -+ ctx->dst_fmt.height; - - if (down_scale) { - hantro_reg_write(vpu, &g2_down_scale_e, 1); From b64d14528b6c0b842d1b57d93ddfe7ad460f479e Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Tue, 23 Aug 2022 14:17:54 +0000 Subject: [PATCH 08/29] linux (Allwinner): drop media-uapi-hevc-tiles-and-num_slices --- ...media-uapi-hevc-tiles-and-num_slices.patch | 31 ------------------- 1 file changed, 31 deletions(-) delete mode 100644 projects/Allwinner/patches/linux/0038-HACK-media-uapi-hevc-tiles-and-num_slices.patch diff --git a/projects/Allwinner/patches/linux/0038-HACK-media-uapi-hevc-tiles-and-num_slices.patch b/projects/Allwinner/patches/linux/0038-HACK-media-uapi-hevc-tiles-and-num_slices.patch deleted file mode 100644 index a20de11186..0000000000 --- a/projects/Allwinner/patches/linux/0038-HACK-media-uapi-hevc-tiles-and-num_slices.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 15:07:15 +0000 -Subject: [PATCH] HACK: media: uapi: hevc: tiles and num_slices - ---- - include/uapi/linux/v4l2-controls.h | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) - ---- a/include/uapi/linux/v4l2-controls.h -+++ b/include/uapi/linux/v4l2-controls.h -@@ -2118,7 +2118,8 @@ struct v4l2_ctrl_hevc_sps { - __u8 chroma_format_idc; - __u8 sps_max_sub_layers_minus1; - -- __u8 reserved[6]; -+ __u8 num_slices; -+ __u8 reserved[5]; - __u64 flags; - }; - -@@ -2375,6 +2376,9 @@ struct v4l2_ctrl_hevc_slice_params { - __u16 short_term_ref_pic_set_size; - __u16 long_term_ref_pic_set_size; - -+ __u32 entry_point_offset_minus1[256]; -+ __u8 reserved[8]; -+ - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ - struct v4l2_hevc_pred_weight_table pred_weight_table; - From b277c31796d9f8f9646b151c1a0cc82dfee98ae9 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Thu, 25 Aug 2022 12:30:58 +0000 Subject: [PATCH 09/29] linux (Allwinner): reinstate sun8i_hdmi_phy_remove() --- ...63-HACK-SW-CEC-implementation-for-H3.patch | 30 +++++++++++++++---- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/projects/Allwinner/patches/linux/0063-HACK-SW-CEC-implementation-for-H3.patch b/projects/Allwinner/patches/linux/0063-HACK-SW-CEC-implementation-for-H3.patch index 7f147e476c..1c0185c807 100644 --- a/projects/Allwinner/patches/linux/0063-HACK-SW-CEC-implementation-for-H3.patch +++ b/projects/Allwinner/patches/linux/0063-HACK-SW-CEC-implementation-for-H3.patch @@ -76,7 +76,7 @@ diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8 index b64d93da651d..e2936e7745b8 100644 --- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -@@ -498,8 +498,9 @@ static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy) +@@ -506,8 +506,9 @@ regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK, 0); @@ -88,7 +88,7 @@ index b64d93da651d..e2936e7745b8 100644 /* read calibration data */ regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val); -@@ -576,8 +577,47 @@ void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy, +@@ -584,8 +585,47 @@ plat_data->cur_ctr = variant->cur_ctr; plat_data->phy_config = variant->phy_cfg; } @@ -136,7 +136,7 @@ index b64d93da651d..e2936e7745b8 100644 static const struct regmap_config sun8i_hdmi_phy_regmap_config = { .reg_bits = 32, .val_bits = 32, -@@ -653,6 +693,7 @@ int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node) +@@ -653,6 +693,7 @@ { struct platform_device *pdev = of_find_device_by_node(node); struct sun8i_hdmi_phy *phy; @@ -144,7 +144,7 @@ index b64d93da651d..e2936e7745b8 100644 if (!pdev) return -EPROBE_DEFER; -@@ -664,8 +705,35 @@ int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node) +@@ -666,8 +707,35 @@ hdmi->phy = phy; put_device(&pdev->dev); @@ -180,7 +180,7 @@ index b64d93da651d..e2936e7745b8 100644 } static int sun8i_hdmi_phy_probe(struct platform_device *pdev) -@@ -690,6 +758,14 @@ static int sun8i_hdmi_phy_probe(struct platform_device *pdev) +@@ -682,6 +750,14 @@ phy->variant = of_device_get_match_data(dev); phy->dev = dev; @@ -195,3 +195,23 @@ index b64d93da651d..e2936e7745b8 100644 regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(regs)) +@@ -728,8 +804,19 @@ + return 0; + } + ++static int sun8i_hdmi_phy_remove(struct platform_device *pdev) ++{ ++ struct sun8i_hdmi_phy *phy = platform_get_drvdata(pdev); ++ ++ cec_notifier_cec_adap_unregister(phy->cec_notifier, phy->cec_adapter); ++ cec_unregister_adapter(phy->cec_adapter); ++ ++ return 0; ++} ++ + struct platform_driver sun8i_hdmi_phy_driver = { + .probe = sun8i_hdmi_phy_probe, ++ .remove = sun8i_hdmi_phy_remove, + .driver = { + .name = "sun8i-hdmi-phy", + .of_match_table = sun8i_hdmi_phy_of_table, From a1c0e27cf3a9de78900c9954295e01137261a436 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Tue, 23 Aug 2022 11:38:21 +0000 Subject: [PATCH 10/29] linux (NXP iMX8): rebase patches for linux 6.0-rc6 --- ...1-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch | 4 ++-- ...0-drm-imx-Add-mhdp-dp-hdmi-driver-for-imx8x-platform.patch | 4 +++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch b/projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch index 173c23ed33..43c18842b8 100644 --- a/projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch +++ b/projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch @@ -3806,8 +3806,8 @@ index a4a45daf93f2..058bc372f02b 100644 edid->width_cm, edid->height_cm); dp->sink_has_audio = drm_detect_monitor_audio(edid); -@@ -279,7 +282,8 @@ static int cdn_dp_connector_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) +@@ -279,7 +282,8 @@ cdn_dp_connector_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) { struct cdn_dp_device *dp = connector_to_dp(connector); - struct drm_display_info *display_info = &dp->connector.display_info; diff --git a/projects/NXP/devices/iMX8/patches/linux/0030-drm-imx-Add-mhdp-dp-hdmi-driver-for-imx8x-platform.patch b/projects/NXP/devices/iMX8/patches/linux/0030-drm-imx-Add-mhdp-dp-hdmi-driver-for-imx8x-platform.patch index a44d66ec6e..3d69a9a4f7 100644 --- a/projects/NXP/devices/iMX8/patches/linux/0030-drm-imx-Add-mhdp-dp-hdmi-driver-for-imx8x-platform.patch +++ b/projects/NXP/devices/iMX8/patches/linux/0030-drm-imx-Add-mhdp-dp-hdmi-driver-for-imx8x-platform.patch @@ -2114,7 +2114,7 @@ new file mode 100644 index 000000000000..3acbdf575ee2 --- /dev/null +++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c -@@ -0,0 +1,257 @@ +@@ -0,0 +1,259 @@ +/* + * copyright (c) 2019 nxp semiconductor, inc. + * @@ -2130,6 +2130,8 @@ index 000000000000..3acbdf575ee2 +#include +#include + ++#include ++ +#include "cdns-mhdp-imx.h" +#include "cdns-mhdp-phy.h" +#include "../imx-drm.h" From fcd644f0173a04df19356813c25d48a97ddb2c04 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sat, 17 Sep 2022 08:35:04 +0000 Subject: [PATCH 11/29] Rockchip: linux: rebase/add patches for linux 6.0 --- .../linux-0001-rockchip-from-6.1.patch | 5847 +++++++++++++++++ .../linux-0002-rockchip-from-list.patch | 4 +- .../default/linux-0011-v4l2-from-list.patch | 42 +- .../default/linux-0020-drm-from-list.patch | 22 +- .../default/linux-1000-drm-rockchip.patch | 436 +- .../default/linux-1001-v4l2-rockchip.patch | 113 +- .../default/linux-1002-for-libreelec.patch | 113 +- .../linux-2000-v4l2-wip-rkvdec-hevc.patch | 830 +-- .../linux-2001-v4l2-wip-iep-driver.patch | 6 +- 9 files changed, 6477 insertions(+), 936 deletions(-) create mode 100644 projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-6.1.patch diff --git a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-6.1.patch b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-6.1.patch new file mode 100644 index 0000000000..c8558662e1 --- /dev/null +++ b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-6.1.patch @@ -0,0 +1,5847 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Thu, 21 Jul 2022 10:33:00 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add analog audio output on quartz64-b + +This adds the necessary device tree changes to enable analog +audio output on the PINE64 Quartz64 Model B with its RK809 +codec. + +The headphone detection pin is left out for now because I couldn't +get it to work and am not sure if it even matters, but for future +reference: It's pin GPIO4 RK_PC4, named HP_DET_L_GPIO4_C4 in the +schematic. + +Signed-off-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20220721083301.3711-1-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3566-quartz64-b.dts | 32 ++++++++++++++++++- + 1 file changed, 31 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +index 02d5f5a8ca03..3897980d69d1 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +@@ -42,6 +42,21 @@ led-user { + }; + }; + ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "Analog RK809"; ++ simple-audio-card,mclk-fs = <256>; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1_8ch>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&rk809>; ++ }; ++ }; ++ + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; +@@ -177,11 +192,16 @@ rk809: pmic@20 { + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; ++ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; ++ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; ++ clock-names = "mclk"; ++ clocks = <&cru I2S1_MCLKOUT_TX>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int>; ++ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; + rockchip,system-power-controller; ++ #sound-dai-cells = <0>; + wakeup-source; + #clock-cells = <1>; + +@@ -420,6 +440,16 @@ &i2c5 { + status = "disabled"; + }; + ++&i2s1_8ch { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1m0_sclktx ++ &i2s1m0_lrcktx ++ &i2s1m0_sdi0 ++ &i2s1m0_sdo0>; ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ + &mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Michael Riesch +Date: Tue, 12 Jul 2022 15:32:02 +0200 +Subject: [PATCH] arm64: dts: rockchip: add vcc_cam regulator to rock-3a + +The Radxa ROCK3 Model A features a voltage regulator that provides +a 3V3 supply to the MIPI CSI connector. Add this regulator to the +device tree of the board. + +Signed-off-by: Michael Riesch +Link: https://lore.kernel.org/r/20220712133204.2524942-1-michael.riesch@wolfvision.net +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3568-rock-3a.dts | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +index 6b5093a1a6cf..a848a2a2ab68 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +@@ -131,6 +131,22 @@ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; ++ ++ vcc_cam: vcc-cam { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_cam_en>; ++ regulator-name = "vcc_cam"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; + }; + + &combphy0 { +@@ -462,6 +478,12 @@ rgmii_phy1: ethernet-phy@0 { + }; + + &pinctrl { ++ cam { ++ vcc_cam_en: vcc_cam_en { ++ rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + ethernet { + eth_phy_rst: eth_phy_rst { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Michael Riesch +Date: Tue, 12 Jul 2022 15:32:03 +0200 +Subject: [PATCH] arm64: dts: rockchip: add vcc_mipi regulator to rock-3a + +The Radxa ROCK3 Model A features a voltage regulator that provides +a 3V3 supply to the MIPI DSI connector. Add this regulator to the +device tree of the board. + +Signed-off-by: Michael Riesch +Link: https://lore.kernel.org/r/20220712133204.2524942-2-michael.riesch@wolfvision.net +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3568-rock-3a.dts | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +index a848a2a2ab68..e883afa83617 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +@@ -147,6 +147,22 @@ regulator-state-mem { + regulator-off-in-suspend; + }; + }; ++ ++ vcc_mipi: vcc-mipi { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc_mipi_en>; ++ regulator-name = "vcc_mipi"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; + }; + + &combphy0 { +@@ -484,6 +500,12 @@ vcc_cam_en: vcc_cam_en { + }; + }; + ++ display { ++ vcc_mipi_en: vcc_mipi_en { ++ rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + ethernet { + eth_phy_rst: eth_phy_rst { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Michael Riesch +Date: Tue, 12 Jul 2022 15:32:04 +0200 +Subject: [PATCH] arm64: dts: rockchip: specify pinctrl for i2c adapters on + rock-3a + +On the Radxa ROCK3 Model A the I2C adapters related to the MIPI DSI +connector and the M.2/NGFF connector use the non-default pins. +Specify the correct pinctrl but leave the adapters disabled (as +they are supposed to be activated by overlays that describe the +external hardware). + +Signed-off-by: Michael Riesch +Link: https://lore.kernel.org/r/20220712133204.2524942-3-michael.riesch@wolfvision.net +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +index e883afa83617..cd8cc0c3c68a 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +@@ -472,6 +472,18 @@ codec { + }; + }; + ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3m1_xfer>; ++ status = "disabled"; ++}; ++ ++&i2c4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c4m1_xfer>; ++ status = "disabled"; ++}; ++ + &i2s0_8ch { + status = "okay"; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Thu, 25 Aug 2022 21:38:35 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add PCIe v3 nodes to rk3568 + +Add nodes to rk356x devicetree to support PCIe v3. + +Signed-off-by: Peter Geis +Signed-off-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20220825193836.54262-5-linux@fw-web.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 122 +++++++++++++++++++++++ + 1 file changed, 122 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +index 2bdf8c7e9765..ba67b58f05b7 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -42,6 +42,128 @@ qos_sata0: qos@fe190200 { + reg = <0x0 0xfe190200 0x0 0x20>; + }; + ++ pcie30_phy_grf: syscon@fdcb8000 { ++ compatible = "rockchip,rk3568-pcie3-phy-grf", "syscon"; ++ reg = <0x0 0xfdcb8000 0x0 0x10000>; ++ }; ++ ++ pcie30phy: phy@fe8c0000 { ++ compatible = "rockchip,rk3568-pcie3-phy"; ++ reg = <0x0 0xfe8c0000 0x0 0x20000>; ++ #phy-cells = <0>; ++ clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, ++ <&cru PCLK_PCIE30PHY>; ++ clock-names = "refclk_m", "refclk_n", "pclk"; ++ resets = <&cru SRST_PCIE30PHY>; ++ reset-names = "phy"; ++ rockchip,phy-grf = <&pcie30_phy_grf>; ++ status = "disabled"; ++ }; ++ ++ pcie3x1: pcie@fe270000 { ++ compatible = "rockchip,rk3568-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ bus-range = <0x0 0xf>; ++ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, ++ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, ++ <&cru CLK_PCIE30X1_AUX_NDFT>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", "aux"; ++ device_type = "pci"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, ++ <0 0 0 2 &pcie3x1_intc 1>, ++ <0 0 0 3 &pcie3x1_intc 2>, ++ <0 0 0 4 &pcie3x1_intc 3>; ++ linux,pci-domain = <1>; ++ num-ib-windows = <6>; ++ num-ob-windows = <2>; ++ max-link-speed = <3>; ++ msi-map = <0x0 &gic 0x1000 0x1000>; ++ num-lanes = <1>; ++ phys = <&pcie30phy>; ++ phy-names = "pcie-phy"; ++ power-domains = <&power RK3568_PD_PIPE>; ++ reg = <0x3 0xc0400000 0x0 0x00400000>, ++ <0x0 0xfe270000 0x0 0x00010000>, ++ <0x3 0x7f000000 0x0 0x01000000>; ++ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>; ++ reg-names = "dbi", "apb", "config"; ++ resets = <&cru SRST_PCIE30X1_POWERUP>; ++ reset-names = "pipe"; ++ /* bifurcation; lane1 when using 1+1 */ ++ status = "disabled"; ++ ++ pcie3x1_intc: legacy-interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ }; ++ ++ pcie3x2: pcie@fe280000 { ++ compatible = "rockchip,rk3568-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ bus-range = <0x0 0xf>; ++ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, ++ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, ++ <&cru CLK_PCIE30X2_AUX_NDFT>; ++ clock-names = "aclk_mst", "aclk_slv", ++ "aclk_dbi", "pclk", "aux"; ++ device_type = "pci"; ++ interrupts = , ++ , ++ , ++ , ++ ; ++ interrupt-names = "sys", "pmc", "msg", "legacy", "err"; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, ++ <0 0 0 2 &pcie3x2_intc 1>, ++ <0 0 0 3 &pcie3x2_intc 2>, ++ <0 0 0 4 &pcie3x2_intc 3>; ++ linux,pci-domain = <2>; ++ num-ib-windows = <6>; ++ num-ob-windows = <2>; ++ max-link-speed = <3>; ++ msi-map = <0x0 &gic 0x2000 0x1000>; ++ num-lanes = <2>; ++ phys = <&pcie30phy>; ++ phy-names = "pcie-phy"; ++ power-domains = <&power RK3568_PD_PIPE>; ++ reg = <0x3 0xc0800000 0x0 0x00400000>, ++ <0x0 0xfe280000 0x0 0x00010000>, ++ <0x3 0xbf000000 0x0 0x01000000>; ++ ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>, ++ <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>; ++ reg-names = "dbi", "apb", "config"; ++ resets = <&cru SRST_PCIE30X2_POWERUP>; ++ reset-names = "pipe"; ++ /* bifurcation; lane0 when using 1+1 */ ++ status = "disabled"; ++ ++ pcie3x2_intc: legacy-interrupt-controller { ++ interrupt-controller; ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-parent = <&gic>; ++ interrupts = ; ++ }; ++ }; ++ + gmac0: ethernet@fe2a0000 { + compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe2a0000 0x0 0x10000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Thu, 25 Aug 2022 21:38:36 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add PCIe v3 nodes to BPI-R2-Pro + +Add Nodes to Bananapi-R2-Pro board to support PCIe v3 and +set PCIe related regulators to always on. + +Suggested-by: Peter Geis +Signed-off-by: Frank Wunderlich +Link: https://lore.kernel.org/r/20220825193836.54262-6-linux@fw-web.de +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 117 ++++++++++++++++++ + 1 file changed, 117 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +index 5e34bd0b214d..7a8d55a898f5 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +@@ -86,6 +86,66 @@ vcc5v0_sys: vcc5v0-sys { + vin-supply = <&dc_12v>; + }; + ++ pcie30_avdd0v9: pcie30-avdd0v9-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_avdd1v8: pcie30-avdd1v8-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ /* pi6c pcie clock generator feeds both ports */ ++ vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <200000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ ++ vcc3v3_minipcie: vcc3v3-minipcie-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_minipcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&minipcie_enable_h>; ++ startup-delay-us = <50000>; ++ vin-supply = <&vcc3v3_pi6c_05>; ++ }; ++ ++ /* actually fed by vcc3v3_sys, dependent on pi6c clock generator */ ++ vcc3v3_ngff: vcc3v3-ngff-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_ngff"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ngffpcie_enable_h>; ++ startup-delay-us = <50000>; ++ vin-supply = <&vcc3v3_pi6c_05>; ++ }; ++ + vcc5v0_usb: vcc5v0_usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; +@@ -513,6 +573,32 @@ rgmii_phy1: ethernet-phy@0 { + }; + }; + ++&pcie30phy { ++ data-lanes = <1 2>; ++ phy-supply = <&vcc3v3_pi6c_05>; ++ status = "okay"; ++}; ++ ++&pcie3x1 { ++ /* M.2 slot */ ++ num-lanes = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ngffpcie_reset_h>; ++ reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_ngff>; ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ /* mPCIe slot */ ++ num-lanes = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&minipcie_reset_h>; ++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_minipcie>; ++ status = "okay"; ++}; ++ + &pinctrl { + leds { + blue_led_pin: blue-led-pin { +@@ -529,6 +615,24 @@ hym8563_int: hym8563-int { + }; + }; + ++ pcie { ++ minipcie_enable_h: minipcie-enable-h { ++ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; ++ }; ++ ++ ngffpcie_enable_h: ngffpcie-enable-h { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; ++ }; ++ ++ minipcie_reset_h: minipcie-reset-h { ++ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; ++ }; ++ ++ ngffpcie_reset_h: ngffpcie-reset-h { ++ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>; ++ }; ++ }; ++ + pmic { + pmic_int: pmic_int { + rockchip,pins = +@@ -708,6 +812,19 @@ &usb2phy0_otg { + status = "okay"; + }; + ++&usb2phy1 { ++ /* USB for PCIe/M2 */ ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ status = "okay"; ++}; ++ + &vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Michael Riesch +Date: Wed, 20 Jul 2022 11:15:27 +0200 +Subject: [PATCH] arm64: dts: rockchip: add csi dphy node to rk356x + +Add the MIPI CSI DPHY node to the RK356x device tree. + +Signed-off-by: Michael Riesch +Link: https://lore.kernel.org/r/20220720091527.1270365-4-michael.riesch@wolfvision.net +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +index 319981c3e9f7..c66b60302803 100644 +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -1594,6 +1594,18 @@ combphy2: phy@fe840000 { + status = "disabled"; + }; + ++ csi_dphy: phy@fe870000 { ++ compatible = "rockchip,rk3568-csi-dphy"; ++ reg = <0x0 0xfe870000 0x0 0x10000>; ++ clocks = <&cru PCLK_MIPICSIPHY>; ++ clock-names = "pclk"; ++ #phy-cells = <0>; ++ resets = <&cru SRST_P_MIPICSIPHY>; ++ reset-names = "apb"; ++ rockchip,grf = <&grf>; ++ status = "disabled"; ++ }; ++ + usb2phy0: usb2phy@fe8a0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8a0000 0x0 0x10000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Andy Yan +Date: Sat, 9 Jul 2022 18:29:42 +0800 +Subject: [PATCH] dt-bindings: vendor-prefixes: Add OPEN AI LAB + +Add vendor prefixes for OPEN AI LAB. + +Signed-off-by: Andy Yan +Acked-by: Rob Herring +Link: https://lore.kernel.org/r/20220709102942.2753939-1-andyshrk@163.com +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml +index 2f0151e9f6be..dfaff2487b04 100644 +--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml ++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml +@@ -925,6 +925,8 @@ patternProperties: + description: On Tat Industrial Company + "^opalkelly,.*": + description: Opal Kelly Incorporated ++ "^openailab,.*": ++ description: openailab.com + "^opencores,.*": + description: OpenCores.org + "^openembed,.*": + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Andy Yan +Date: Sat, 9 Jul 2022 18:30:01 +0800 +Subject: [PATCH] dt-bindings: arm: rockchip: Add EAIDK-610 + +EAIDK-610 is a rk3399 based board from OPEN AI LAB +and popularly used by university students. + +Specification: +- Rockchip RK3399 +- LPDDR3 4GB +- TF sd scard slot +- eMMC +- AP6255 for WiFi + BT +- Gigabit ethernet +- HDMI out +- 40 pin header +- USB 2.0 x 2 +- USB 3.0 x 1 +- USB 3.0 Type-C x 1 +- 12V DC Power supply + +Signed-off-by: Andy Yan +Acked-by: Rob Herring +Link: https://lore.kernel.org/r/20220709103001.2753992-1-andyshrk@163.com +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index 7811ba64149c..adc06522d219 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -470,6 +470,11 @@ properties: + - const: netxeon,r89 + - const: rockchip,rk3288 + ++ - description: OPEN AI LAB EAIDK-610 ++ items: ++ - const: openailab,eaidk-610 ++ - const: rockchip,rk3399 ++ + - description: Orange Pi RK3399 board + items: + - const: rockchip,rk3399-orangepi + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Andy Yan +Date: Sat, 9 Jul 2022 18:30:16 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add dts for a rk3399 based board + EAIDK-610 + +EAIDK-610 is from OPEN AI LAB and popularly used by university +students. + +Specification: +- Rockchip RK3399 +- LPDDR3 4GB +- TF sd scard slot +- eMMC +- AP6255 for WiFi + BT +- Gigabit ethernet +- HDMI out +- 40 pin header +- USB 2.0 x 2 +- USB 3.0 x 1 +- USB 3.0 Type-C x 1 +- 12V DC Power supply + +This patch is test on Armbain and Glodroid with +HDMI/GPU/USB HOST/Type-C ADB/WIFI/BT. + +Signed-off-by: Andy Yan +Link: https://lore.kernel.org/r/20220709103016.2754044-1-andyshrk@163.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3399-eaidk-610.dts | 939 ++++++++++++++++++ + 2 files changed, 940 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index ef79a672804a..4ed7d483c864 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -21,6 +21,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-eaidk-610.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts b/arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts +new file mode 100644 +index 000000000000..d1f343345f67 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts +@@ -0,0 +1,939 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2022 Fuzhou Rockchip Electronics Co., Ltd. ++ */ ++ ++/dts-v1/; ++#include ++#include ++#include ++#include "rk3399.dtsi" ++#include "rk3399-opp.dtsi" ++ ++/ { ++ model = "OPEN AI LAB EAIDK-610"; ++ compatible = "openailab,eaidk-610", "rockchip,rk3399"; ++ ++ aliases { ++ mmc0 = &sdio0; ++ mmc1 = &sdmmc; ++ mmc2 = &sdhci; ++ }; ++ ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ pwms = <&pwm0 0 25000 0>; ++ brightness-levels = < ++ 0 1 2 3 4 5 6 7 ++ 8 9 10 11 12 13 14 15 ++ 16 17 18 19 20 21 22 23 ++ 24 25 26 27 28 29 30 31 ++ 32 33 34 35 36 37 38 39 ++ 40 41 42 43 44 45 46 47 ++ 48 49 50 51 52 53 54 55 ++ 56 57 58 59 60 61 62 63 ++ 64 65 66 67 68 69 70 71 ++ 72 73 74 75 76 77 78 79 ++ 80 81 82 83 84 85 86 87 ++ 88 89 90 91 92 93 94 95 ++ 96 97 98 99 100 101 102 103 ++ 104 105 106 107 108 109 110 111 ++ 112 113 114 115 116 117 118 119 ++ 120 121 122 123 124 125 126 127 ++ 128 129 130 131 132 133 134 135 ++ 136 137 138 139 140 141 142 143 ++ 144 145 146 147 148 149 150 151 ++ 152 153 154 155 156 157 158 159 ++ 160 161 162 163 164 165 166 167 ++ 168 169 170 171 172 173 174 175 ++ 176 177 178 179 180 181 182 183 ++ 184 185 186 187 188 189 190 191 ++ 192 193 194 195 196 197 198 199 ++ 200 201 202 203 204 205 206 207 ++ 208 209 210 211 212 213 214 215 ++ 216 217 218 219 220 221 222 223 ++ 224 225 226 227 228 229 230 231 ++ 232 233 234 235 236 237 238 239 ++ 240 241 242 243 244 245 246 247 ++ 248 249 250 251 252 253 254 255>; ++ default-brightness-level = <200>; ++ }; ++ ++ clkin_gmac: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "clkin_gmac"; ++ #clock-cells = <0>; ++ }; ++ ++ dc_12v: dc-12v { ++ compatible = "regulator-fixed"; ++ regulator-name = "dc_12v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ autorepeat; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwrbtn>; ++ ++ key-power { ++ debounce-interval = <100>; ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; ++ label = "GPIO Key Power"; ++ linux,code = ; ++ wakeup-source; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&work_led_pin>, <&user_led_pin>, ++ <&heartbeat_led_pin>, <&wlan_active_led_pin>, ++ <&bt_active_led_pin>; ++ ++ work_led: led-0 { ++ label = "blue:work"; ++ default-state = "on"; ++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ user_led: led-1 { ++ label = "read:user"; ++ default-state = "off"; ++ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ heartbeat_led: led-2 { ++ label = "green:heartbeat"; ++ linux,default-trigger = "heartbeat"; ++ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ wlan_active_led: led-3 { ++ label = "yellow:wlan"; ++ gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "phy0tx"; ++ default-state = "off"; ++ }; ++ ++ bt_active_led: led-4 { ++ label = "blue:bt"; ++ gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "hci0-power"; ++ default-state = "off"; ++ }; ++ }; ++ ++ rt5651-sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "realtek,rt5651-codec"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,widgets = ++ "Microphone", "Mic Jack", ++ "Headphone", "Headphone Jack"; ++ simple-audio-card,routing = ++ "Mic Jack", "MICBIAS1", ++ "IN1P", "Mic Jack", ++ "Headphone Jack", "HPOL", ++ "Headphone Jack", "HPOR"; ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1>; ++ }; ++ simple-audio-card,codec { ++ sound-dai = <&rt5651>; ++ }; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk808 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_enable_h>; ++ ++ /* ++ * On the module itself this is one of these (depending ++ * on the actual card populated): ++ * - SDIO_RESET_L_WL_REG_ON ++ * - PDN (power down when low) ++ */ ++ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; ++ }; ++ ++ /* switched by pmic_sleep */ ++ vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc1v8_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc_1v8>; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&dc_12v>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&dc_12v>; ++ }; ++ ++ /* For USB3.0 Port1/2 */ ++ vcc5v0_host1: vcc5v0-host1-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host1_en>; ++ regulator-name = "vcc5v0_host1"; ++ regulator-always-on; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ /* For USB2.0 Port1/2 */ ++ vcc5v0_host3: vcc5v0-host3-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host3_en>; ++ regulator-name = "vcc5v0_host3"; ++ regulator-always-on; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc5v0_typec: vcc5v0-typec-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_typec_en>; ++ regulator-name = "vcc5v0_typec"; ++ regulator-always-on; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ vdd_log: vdd-log { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd_log"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ }; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&gmac { ++ assigned-clocks = <&cru SCLK_RMII_SRC>; ++ assigned-clock-parents = <&clkin_gmac>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc_lan>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>; ++ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ tx_delay = <0x28>; ++ rx_delay = <0x11>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ ddc-i2c-bus = <&i2c3>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmi_cec>; ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ rk808: pmic@1b { ++ compatible = "rockchip,rk808"; ++ reg = <0x1b>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk808-clkout2"; ++ ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ vcc10-supply = <&vcc3v3_sys>; ++ vcc11-supply = <&vcc3v3_sys>; ++ vcc12-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc_3v0>; ++ ++ regulators { ++ vdd_center: DCDC_REG1 { ++ regulator-name = "vdd_center"; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_cpu_l: DCDC_REG2 { ++ regulator-name = "vdd_cpu_l"; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG4 { ++ regulator-name = "vcc_1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc1v8_dvp: LDO_REG1 { ++ regulator-name = "vcc1v8_dvp"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc2v8_dvp: LDO_REG2 { ++ regulator-name = "vcc2v8_dvp"; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_pmu: LDO_REG3 { ++ regulator-name = "vcc1v8_pmu"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc_sdio: LDO_REG4 { ++ regulator-name = "vcc_sdio"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcca3v0_codec: LDO_REG5 { ++ regulator-name = "vcca3v0_codec"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-name = "vcc_1v5"; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1500000>; ++ }; ++ }; ++ ++ vcca1v8_codec: LDO_REG7 { ++ regulator-name = "vcca1v8_codec"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG8 { ++ regulator-name = "vcc_3v0"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3000000>; ++ }; ++ }; ++ ++ vcc3v3_s3: vcc_lan: SWITCH_REG1 { ++ regulator-name = "vcc3v3_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG2 { ++ regulator-name = "vcc3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ vdd_cpu_b: regulator@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu_b"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vsel1_pin>; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_gpu"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vsel2_pin>; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ i2c-scl-rising-time-ns = <300>; ++ i2c-scl-falling-time-ns = <15>; ++ status = "okay"; ++ ++ rt5651: audio-codec@1a { ++ compatible = "rockchip,rt5651"; ++ reg = <0x1a>; ++ clocks = <&cru SCLK_I2S_8CH_OUT>; ++ clock-names = "mclk"; ++ hp-det-gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; ++ spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; ++ #sound-dai-cells = <0>; ++ }; ++ ++}; ++ ++&i2c3 { ++ i2c-scl-rising-time-ns = <450>; ++ i2c-scl-falling-time-ns = <15>; ++ status = "okay"; ++}; ++ ++&i2c4 { ++ i2c-scl-rising-time-ns = <600>; ++ i2c-scl-falling-time-ns = <20>; ++ status = "okay"; ++ ++ fusb0: typec-portc@22 { ++ compatible = "fcs,fusb302"; ++ reg = <0x22>; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&fusb0_int>; ++ vbus-supply = <&vcc5v0_typec>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ usbc0_role_sw: endpoint@0 { ++ remote-endpoint = <&dwc3_0_role_switch>; ++ }; ++ }; ++ }; ++ ++ connector { ++ compatible = "usb-c-connector"; ++ data-role = "dual"; ++ label = "USB-C"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ usbc_hs: endpoint { ++ remote-endpoint = <&u2phy0_typec_hs>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ usbc_ss: endpoint { ++ remote-endpoint = <&tcphy0_typec_ss>; ++ }; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&i2s1 { ++ rockchip,playback-channels = <2>; ++ rockchip,capture-channels = <2>; ++ status = "okay"; ++}; ++ ++&i2s2 { ++ status = "okay"; ++}; ++ ++&io_domains { ++ status = "okay"; ++ ++ audio-supply = <&vcca1v8_codec>; ++ bt656-supply = <&vcc_3v0>; ++ gpio1830-supply = <&vcc_3v0>; ++ sdmmc-supply = <&vcc_sdio>; ++}; ++ ++&pmu_io_domains { ++ status = "okay"; ++ ++ pmu1830-supply = <&vcc_3v0>; ++}; ++ ++&pinctrl { ++ buttons { ++ pwrbtn: pwrbtn { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ bt { ++ bt_enable_h: bt-enable-h { ++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_host_wake_l: bt-host-wake-l { ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_wake_l: bt-wake-l { ++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ fusb302x { ++ fusb0_int: fusb0-int { ++ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ lcd-panel { ++ lcd_panel_reset: lcd-panel-reset { ++ rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ leds { ++ work_led_pin: work-led-pin { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ user_led_pin: user-led-pin { ++ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ heartbeat_led_pin: heartbeat-led-pin { ++ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wlan_active_led_pin: wlan-led-pin { ++ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_active_led_pin: bt-led-pin { ++ rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ vsel1_pin: vsel1-pin { ++ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ vsel2_pin: vsel2-pin { ++ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ rt5651 { ++ rt5651_hpcon: rt5640-hpcon { ++ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdio-pwrseq { ++ wifi_enable_h: wifi-enable-h { ++ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb-typec { ++ vcc5v0_typec_en: vcc5v0_typec_en { ++ rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb2 { ++ vcc5v0_host3_en: vcc5v0-host3-en { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_host1_en: vcc5v0-host1-en { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ wifi { ++ wifi_host_wake_l: wifi-host-wake-l { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pwm0 { ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca1v8_s3>; ++ status = "okay"; ++}; ++ ++&sdio0 { ++ /* WiFi & BT combo module AMPAK AP6255 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ bus-width = <4>; ++ clock-frequency = <50000000>; ++ cap-sdio-irq; ++ cap-sd-highspeed; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; ++ sd-uhs-sdr104; ++ status = "okay"; ++ ++ brcmf: wifi@1 { ++ compatible = "brcm,bcm4329-fmac"; ++ reg = <1>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ interrupt-names = "host-wake"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_host_wake_l>; ++ }; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ max-frequency = <150000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&tcphy0 { ++ status = "okay"; ++}; ++ ++&tcphy0_usb3 { ++ orientation-switch; ++ port { ++ tcphy0_typec_ss: endpoint { ++ remote-endpoint = <&usbc_ss>; ++ }; ++ }; ++}; ++ ++&tcphy1 { ++ status = "okay"; ++}; ++ ++&tsadc { ++ /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-mode = <1>; ++ /* tshut polarity 0:LOW 1:HIGH */ ++ rockchip,hw-tshut-polarity = <1>; ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++ ++ u2phy0_otg: otg-port { ++ status = "okay"; ++ }; ++ ++ u2phy0_host: host-port { ++ phy-supply = <&vcc5v0_host3>; ++ status = "okay"; ++ }; ++ ++ port { ++ u2phy0_typec_hs: endpoint { ++ remote-endpoint = <&usbc_hs>; ++ }; ++ }; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++ ++ u2phy1_otg: otg-port { ++ status = "okay"; ++ }; ++ ++ u2phy1_host: host-port { ++ phy-supply = <&vcc5v0_host3>; ++ status = "okay"; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm4345c5"; ++ clocks = <&rk808 1>; ++ clock-names = "lpo"; ++ device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; ++ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; ++ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; ++ max-speed = <1500000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; ++ vbat-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc_1v8>; ++ }; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usbdrd3_0 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_0 { ++ status = "okay"; ++ usb-role-switch; ++ ++ port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ dwc3_0_role_switch: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&usbc0_role_sw>; ++ }; ++ }; ++}; ++ ++&usbdrd3_1 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_1 { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&vopb { ++ status = "okay"; ++}; ++ ++&vopb_mmu { ++ status = "okay"; ++}; ++ ++&vopl { ++ status = "okay"; ++}; ++ ++&vopl_mmu { ++ status = "okay"; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Tom Fitzhenry +Date: Mon, 15 Aug 2022 22:30:03 +1000 +Subject: [PATCH] dt-bindings: arm: rockchip: Add PinePhone Pro bindings + +Document board compatible names for Pine64 PinePhonePro. + +https://wiki.pine64.org/wiki/PinePhone_Pro + +Signed-off-by: Tom Fitzhenry +Reviewed-by: Caleb Connolly +Acked-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20220815123004.252014-2-tom@tom-fitzhenry.me.uk +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index adc06522d219..7295eecc6de7 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -499,6 +499,11 @@ properties: + - const: pine64,pinenote + - const: rockchip,rk3566 + ++ - description: Pine64 PinePhonePro ++ items: ++ - const: pine64,pinephone-pro ++ - const: rockchip,rk3399 ++ + - description: Pine64 Rock64 + items: + - const: pine64,rock64 + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Martijn Braam +Date: Mon, 29 Aug 2022 15:00:40 +1000 +Subject: [PATCH] arm64: dts: rockchip: Add initial support for Pine64 + PinePhone Pro +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This is a basic DT containing regulators and UART, intended to be a +base that myself and others can add additional nodes in future patches. + +Tested to work: booting from eMMC/SD, output over UART. + +https://wiki.pine64.org/wiki/PinePhone_Pro + +This is derived from the community pine64-org repo[0] with fixes from +https://megous.com/git/linux. + +0. https://gitlab.com/pine64-org/linux/-/commit/261d3b5f8ac503f97da810986d1d6422430c8531 + +Signed-off-by: Martijn Braam +Co-developed-by: Kamil Trzciński +[no SoB, but Kamil is happy for this patch to be submitted] +Co-developed-by: Ondrej Jirman +Signed-off-by: Ondrej Jirman +Co-developed-by: Tom Fitzhenry +Signed-off-by: Tom Fitzhenry +Reviewed-by: Caleb Connolly +Reviewed-by: Nícolas F. R. A. Prado +Tested-by: Nícolas F. R. A. Prado +Link: https://lore.kernel.org/r/20220829050040.17330-2-tom@tom-fitzhenry.me.uk +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../dts/rockchip/rk3399-pinephone-pro.dts | 398 ++++++++++++++++++ + 2 files changed, 399 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 4ed7d483c864..236e8ae52c70 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -43,6 +43,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinephone-pro.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +new file mode 100644 +index 000000000000..f00c80361377 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +@@ -0,0 +1,398 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2020 Martijn Braam ++ * Copyright (c) 2021 Kamil Trzciński ++ */ ++ ++/* ++ * PinePhone Pro datasheet: ++ * https://files.pine64.org/doc/PinePhonePro/PinephonePro-Schematic-V1.0-20211127.pdf ++ */ ++ ++/dts-v1/; ++#include ++#include "rk3399.dtsi" ++#include "rk3399-opp.dtsi" ++ ++/ { ++ model = "Pine64 PinePhonePro"; ++ compatible = "pine64,pinephone-pro", "rockchip,rk3399"; ++ chassis-type = "handset"; ++ ++ aliases { ++ mmc0 = &sdio0; ++ mmc1 = &sdmmc; ++ mmc2 = &sdhci; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:115200n8"; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwrbtn_pin>; ++ ++ key-power { ++ debounce-interval = <20>; ++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; ++ label = "Power"; ++ linux,code = ; ++ wakeup-source; ++ }; ++ }; ++ ++ vcc_sys: vcc-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_sys>; ++ }; ++ ++ vcca1v8_s3: vcc1v8-s3-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcca1v8_s3"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ vcc1v8_codec: vcc1v8-codec-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc1v8_codec_en>; ++ regulator-name = "vcc1v8_codec"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ clock-frequency = <400000>; ++ i2c-scl-rising-time-ns = <168>; ++ i2c-scl-falling-time-ns = <4>; ++ status = "okay"; ++ ++ rk818: pmic@1c { ++ compatible = "rockchip,rk818"; ++ reg = <0x1c>; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ #clock-cells = <1>; ++ clock-output-names = "xin32k", "rk808-clkout2"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc6-supply = <&vcc_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ ++ regulators { ++ vdd_cpu_l: DCDC_REG1 { ++ regulator-name = "vdd_cpu_l"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <875000>; ++ regulator-max-microvolt = <975000>; ++ regulator-ramp-delay = <6001>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_center: DCDC_REG2 { ++ regulator-name = "vdd_center"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-ramp-delay = <6001>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG4 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcca3v0_codec: LDO_REG1 { ++ regulator-name = "vcca3v0_codec"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ }; ++ ++ vcc3v0_touch: LDO_REG2 { ++ regulator-name = "vcc3v0_touch"; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ }; ++ ++ vcca1v8_codec: LDO_REG3 { ++ regulator-name = "vcca1v8_codec"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ ++ rk818_pwr_on: LDO_REG4 { ++ regulator-name = "rk818_pwr_on"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG5 { ++ regulator-name = "vcc_3v0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-name = "vcc_1v5"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_dvp: LDO_REG7 { ++ regulator-name = "vcc1v8_dvp"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ ++ vcc3v3_s3: LDO_REG8 { ++ regulator-name = "vcc3v3_s3"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG9 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1710000>; ++ regulator-max-microvolt = <3150000>; ++ }; ++ ++ vcc3v3_s0: SWITCH_REG { ++ regulator-name = "vcc3v3_s0"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ vdd_cpu_b: regulator@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vsel1_pin>; ++ regulator-name = "vdd_cpu_b"; ++ regulator-min-microvolt = <875000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vsel2_pin>; ++ regulator-name = "vdd_gpu"; ++ regulator-min-microvolt = <875000>; ++ regulator-max-microvolt = <975000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&cluster0_opp { ++ opp04 { ++ status = "disabled"; ++ }; ++ ++ opp05 { ++ status = "disabled"; ++ }; ++}; ++ ++&cluster1_opp { ++ opp06 { ++ opp-hz = /bits/ 64 <1500000000>; ++ opp-microvolt = <1100000 1100000 1150000>; ++ }; ++ ++ opp07 { ++ status = "disabled"; ++ }; ++}; ++ ++&io_domains { ++ bt656-supply = <&vcc1v8_dvp>; ++ audio-supply = <&vcca1v8_codec>; ++ sdmmc-supply = <&vccio_sd>; ++ gpio1830-supply = <&vcc_3v0>; ++ status = "okay"; ++}; ++ ++&pmu_io_domains { ++ pmu1830-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ buttons { ++ pwrbtn_pin: pwrbtn-pin { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ vsel1_pin: vsel1-pin { ++ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ vsel2_pin: vsel2-pin { ++ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ sound { ++ vcc1v8_codec_en: vcc1v8-codec-en { ++ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ max-frequency = <150000000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; ++ vmmc-supply = <&vcc3v3_sys>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ mmc-hs200-1_8v; ++ non-removable; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <1>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jagan Teki +Date: Fri, 2 Sep 2022 12:20:55 +0530 +Subject: [PATCH] dt-bindings: arm: rockchip: Document Radxa ROCK 4C+ +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Document the dt-bindings for Radxa ROCK 4C+ SBC. + +Key differences of 4C+ compared to previous ROCK Pi 4. +- Rockchip RK3399-T SoC +- DP from 4C replaced with micro HDMI 2K@60fps +- 4-lane MIPI DSI with 1920*1080 +- RK817 Audio codec + +Also, an official naming convention from Radxa mention to remove +Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not +Radxa ROCK Pi 4C+. + +Acked-by: Krzysztof Kozlowski +Signed-off-by: Jagan Teki +Link: https://lore.kernel.org/r/20220902065057.97425-1-jagan@amarulasolutions.com +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index 7295eecc6de7..5c1b9f0e4cc1 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -547,6 +547,11 @@ properties: + - const: radxa,rockpi4 + - const: rockchip,rk3399 + ++ - description: Radxa ROCK 4C+ ++ items: ++ - const: radxa,rock-4c-plus ++ - const: rockchip,rk3399 ++ + - description: Radxa ROCK Pi E + items: + - const: radxa,rockpi-e + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jagan Teki +Date: Fri, 2 Sep 2022 12:20:56 +0530 +Subject: [PATCH] arm64: dts: rockchip: Add RK3399-T OPP table + +RK3399-T is down-clocked version of RK3399 SoC operated at 1.5GHz. + +Add CPU operating points table for it. + +Signed-off-by: FUKAUMI Naoki +Signed-off-by: Jagan Teki +Link: https://lore.kernel.org/r/20220902065057.97425-2-jagan@amarulasolutions.com +Signed-off-by: Heiko Stuebner +--- + .../arm64/boot/dts/rockchip/rk3399-t-opp.dtsi | 114 ++++++++++++++++++ + 1 file changed, 114 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-t-opp.dtsi + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-t-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-t-opp.dtsi +new file mode 100644 +index 000000000000..1ababadda9df +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-t-opp.dtsi +@@ -0,0 +1,114 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd ++ * Copyright (c) 2022 Radxa Limited ++ */ ++ ++/ { ++ cluster0_opp: opp-table-0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <875000 875000 1250000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <875000 875000 1250000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <900000 900000 1250000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <975000 975000 1250000>; ++ }; ++ }; ++ ++ cluster1_opp: opp-table-1 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <875000 875000 1250000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <875000 875000 1250000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <875000 875000 1250000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <925000 925000 1250000>; ++ }; ++ opp04 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1000000 1000000 1250000>; ++ }; ++ opp05 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <1075000 1075000 1250000>; ++ }; ++ opp06 { ++ opp-hz = /bits/ 64 <1512000000>; ++ opp-microvolt = <1150000 1150000 1250000>; ++ }; ++ }; ++ ++ gpu_opp_table: opp-table-2 { ++ compatible = "operating-points-v2"; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <200000000>; ++ opp-microvolt = <875000 875000 1150000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <875000 875000 1150000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <875000 875000 1150000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <975000 975000 1150000>; ++ }; ++ }; ++}; ++ ++&cpu_l0 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_l1 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_l2 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_l3 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_b0 { ++ operating-points-v2 = <&cluster1_opp>; ++}; ++ ++&cpu_b1 { ++ operating-points-v2 = <&cluster1_opp>; ++}; ++ ++&gpu { ++ operating-points-v2 = <&gpu_opp_table>; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jagan Teki +Date: Fri, 2 Sep 2022 12:20:57 +0530 +Subject: [PATCH] arm64: dts: rockchip: rk3399: Radxa ROCK 4C+ +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add support for Radxa ROCK 4C+ SBC. + +Key differences of 4C+ compared to previous ROCK Pi 4. +- Rockchip RK3399-T SoC +- DP from 4C replaced with micro HDMI 2K@60fps +- 4-lane MIPI DSI with 1920*1080 +- RK817 Audio codec + +Also, an official naming convention from Radxa mention to remove +Pi from board name, so this 4C+ is named as Radxa ROCK 4C+ not +Radxa ROCK Pi 4C+. + +Signed-off-by: Stephen Chen +Signed-off-by: Manoj Sai +Signed-off-by: Jagan Teki +Link: https://lore.kernel.org/r/20220902065057.97425-3-jagan@amarulasolutions.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3399-rock-4c-plus.dts | 646 ++++++++++++++++++ + 2 files changed, 647 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 236e8ae52c70..cdd1f211496d 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-4c-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +new file mode 100644 +index 000000000000..a1c4727acfcd +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +@@ -0,0 +1,646 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd ++ * Copyright (c) 2019 Radxa Limited ++ * Copyright (c) 2022 Amarula Solutions(India) ++ */ ++ ++/dts-v1/; ++#include "rk3399.dtsi" ++#include "rk3399-t-opp.dtsi" ++ ++/ { ++ model = "Radxa ROCK 4C+"; ++ compatible = "radxa,rock-4c-plus", "rockchip,rk3399"; ++ ++ aliases { ++ mmc0 = &sdmmc; ++ mmc1 = &sdhci; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk809 1>; ++ clock-names = "ext_clock"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_enable_h>; ++ reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; ++ }; ++ ++ clkin_gmac: external-gmac-clock { ++ compatible = "fixed-clock"; ++ clock-frequency = <125000000>; ++ clock-output-names = "clkin_gmac"; ++ #clock-cells = <0>; ++ }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ vcc5v0_host1: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++ regulator-name = "vcc5v0_host1"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_host0_s0>; ++ }; ++ ++ vcc5v0_typec: vcc5v0-typec-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_typec0_en>; ++ regulator-name = "vcc5v0_typec"; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc_lan: vcc3v3-phy-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_lan"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++}; ++ ++&cpu_l0 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l1 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l2 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_l3 { ++ cpu-supply = <&vdd_cpu_l>; ++}; ++ ++&cpu_b0 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&cpu_b1 { ++ cpu-supply = <&vdd_cpu_b>; ++}; ++ ++&emmc_phy { ++ status = "okay"; ++}; ++ ++&gmac { ++ assigned-clocks = <&cru SCLK_RMII_SRC>; ++ assigned-clock-parents = <&clkin_gmac>; ++ clock_in_out = "input"; ++ phy-supply = <&vcc_lan>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rgmii_pins>; ++ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ snps,reset-delays-us = <0 10000 50000>; ++ tx_delay = <0x2a>; ++ rx_delay = <0x21>; ++ status = "okay"; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ ddc-i2c-bus = <&i2c3>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmi_cec>; ++ status = "okay"; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ i2c-scl-falling-time-ns = <30>; ++ i2c-scl-rising-time-ns = <180>; ++ clock-frequency = <400000>; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio1>; ++ interrupts = ; ++ #clock-cells = <1>; ++ clock-output-names = "rk808-clkout1", "rk808-clkout2"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc5v0_sys>; ++ vcc2-supply = <&vcc5v0_sys>; ++ vcc3-supply = <&vcc5v0_sys>; ++ vcc4-supply = <&vcc5v0_sys>; ++ vcc5-supply = <&vcc_buck5>; ++ vcc6-supply = <&vcc_buck5>; ++ vcc7-supply = <&vcc5v0_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc5v0_sys>; ++ ++ regulators { ++ vdd_log: DCDC_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vdd_log"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vdd_cpu_l: DCDC_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <750000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vdd_cpu_l"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc_ddr"; ++ regulator-initial-mode = <0x2>; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sys: DCDC_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vcc3v3_sys"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_buck5: DCDC_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_buck5"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_0v9: LDO_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vcca_0v9"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: LDO_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcc0v9_soc: LDO_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vcc0v9_soc"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca_1v8"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_mipi: LDO_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc_mipi"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v5: LDO_REG6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-name = "vcc_1v5"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v0: LDO_REG7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-name = "vcc_3v0"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vccio_sd"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_cam: LDO_REG9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_cam"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc5v0_host0_s0: SWITCH_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "vcc5v0_host0_s0"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ lcd_3v3: SWITCH_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-name = "lcd_3v3"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ vdd_cpu_b: regulator@40 { ++ compatible = "silergy,syr827"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-compatible = "fan53555-reg"; ++ pinctrl-0 = <&vsel1_gpio>; ++ vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; ++ regulator-name = "vdd_cpu_b"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_sys>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: regulator@41 { ++ compatible = "silergy,syr828"; ++ reg = <0x41>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-compatible = "fan53555-reg"; ++ pinctrl-0 = <&vsel2_gpio>; ++ vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; ++ regulator-name = "vdd_gpu"; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1500000>; ++ regulator-ramp-delay = <1000>; ++ regulator-always-on; ++ regulator-boot-on; ++ vin-supply = <&vcc5v0_sys>; ++ regulator-initial-mode = <1>; /* 1:force PWM 2:auto */ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c3 { ++ i2c-scl-rising-time-ns = <450>; ++ i2c-scl-falling-time-ns = <15>; ++ status = "okay"; ++}; ++ ++&i2s2 { ++ status = "okay"; ++}; ++ ++&io_domains { ++ bt656-supply = <&vcc_3v0>; ++ gpio1830-supply = <&vcc_3v0>; ++ sdmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ bt { ++ bt_enable_h: bt-enable-h { ++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_host_wake_l: bt-host-wake-l { ++ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_wake_l: bt-wake-l { ++ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ vsel1_gpio: vsel1-gpio { ++ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ ++ vsel2_gpio: vsel2-gpio { ++ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ sdmmc { ++ sdmmc_bus4: sdmmc-bus4 { ++ rockchip,pins = <4 8 1 &pcfg_pull_up_8ma>, ++ <4 9 1 &pcfg_pull_up_8ma>, ++ <4 10 1 &pcfg_pull_up_8ma>, ++ <4 11 1 &pcfg_pull_up_8ma>; ++ }; ++ ++ sdmmc_clk: sdmmc-clk { ++ rockchip,pins = <4 12 1 &pcfg_pull_none_18ma>; ++ }; ++ ++ sdmmc_cmd: sdmmc-cmd { ++ rockchip,pins = <4 13 1 &pcfg_pull_up_8ma>; ++ }; ++ }; ++ ++ usb-typec { ++ vcc5v0_typec0_en: vcc5v0-typec-en { ++ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ usb2 { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ wifi { ++ wifi_enable_h: wifi-enable-h { ++ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wifi_host_wake_l: wifi-host-wake-l { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmu1830-supply = <&vcc_3v0>; ++ status = "okay"; ++}; ++ ++&saradc { ++ status = "okay"; ++ vref-supply = <&vcc_1v8>; ++}; ++ ++&sdhci { ++ max-frequency = <150000000>; ++ bus-width = <8>; ++ mmc-hs400-1_8v; ++ non-removable; ++ mmc-hs400-enhanced-strobe; ++ status = "okay"; ++}; ++ ++&sdio0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ bus-width = <4>; ++ clock-frequency = <50000000>; ++ cap-sdio-irq; ++ cap-sd-highspeed; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; ++ sd-uhs-sdr104; ++ status = "okay"; ++ ++ brcmf: wifi@1 { ++ compatible = "brcm,bcm4329-fmac"; ++ reg = <1>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ interrupt-names = "host-wake"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_host_wake_l>; ++ }; ++}; ++ ++&sdmmc { ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ card-detect-delay = <800>; ++ disable-wp; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; ++ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&tcphy0 { ++ status = "okay"; ++}; ++ ++&tcphy1 { ++ status = "okay"; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++ ++ u2phy0_otg: otg-port { ++ status = "okay"; ++ }; ++ ++ u2phy0_host: host-port { ++ phy-supply = <&vcc5v0_host1>; ++ status = "okay"; ++ }; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++ ++ u2phy1_otg: otg-port { ++ status = "okay"; ++ }; ++ ++ u2phy1_host: host-port { ++ phy-supply = <&vcc5v0_host1>; ++ status = "okay"; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm4345c5"; ++ clocks = <&rk809 1>; ++ clock-names = "lpo"; ++ device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; ++ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; ++ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; ++ max-speed = <1500000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; ++ vbat-supply = <&vcc3v3_sys>; ++ vddio-supply = <&vcc_1v8>; ++ }; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usbdrd3_0 { ++ extcon = <&u2phy0>; ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_0 { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&usbdrd3_1 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_1 { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&vopb { ++ status = "okay"; ++}; ++ ++&vopb_mmu { ++ status = "okay"; ++}; ++ ++&vopl { ++ status = "okay"; ++}; ++ ++&vopl_mmu { ++ status = "okay"; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Mon, 5 Sep 2022 01:36:47 +0200 +Subject: [PATCH] arm64: dts: rockchip: Fix SD card controller probe on + Pinephone Pro + +Voltage constraints on vccio_sd are invalid. They don't match the voltages +that LDO9 can generate, and this causes rk808-regulator driver to fail +to probe with -EINVAL when it tries to apply the constraints during boot. + +Fix the constraints to something that LDO9 can be actually configured for. + +Fixes: 78a21c7d5952 ("arm64: dts: rockchip: Add initial support for Pine64 PinePhone Pro") +Signed-off-by: Ondrej Jirman +Reviewed-by: Caleb Connolly +Reviewed-by: Tom Fitzhenry +Tested-by: Tom Fitzhenry +Link: https://lore.kernel.org/r/20220904233652.3197885-1-megi@xff.cz +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +index f00c80361377..2e058c315025 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts +@@ -253,8 +253,8 @@ regulator-state-mem { + + vccio_sd: LDO_REG9 { + regulator-name = "vccio_sd"; +- regulator-min-microvolt = <1710000>; +- regulator-max-microvolt = <3150000>; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; + }; + + vcc3v3_s0: SWITCH_REG { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Fri, 26 Aug 2022 21:16:23 -0500 +Subject: [PATCH] arm64: dts: rockchip: add rk817 chg to Odroid Go Advance + +Add the new rk817 charger driver to the Odroid Go Advance. Create a +monitored battery node as well for the charger to use. All values +from monitored battery are gathered from the BSP kernel for the +Odroid Go Advance provided by HardKernel. + +Signed-off-by: Chris Morgan +Signed-off-by: Maya Matuszczyk +Link: https://lore.kernel.org/r/20220827021623.23829-5-macroalpha82@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3326-odroid-go2.dts | 26 +++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +index 415aa9ff8bd4..72899a714310 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +@@ -52,6 +52,25 @@ backlight: backlight { + pwms = <&pwm1 0 25000 0>; + }; + ++ battery: battery { ++ compatible = "simple-battery"; ++ charge-full-design-microamp-hours = <3000000>; ++ charge-term-current-microamp = <300000>; ++ constant-charge-current-max-microamp = <2000000>; ++ constant-charge-voltage-max-microvolt = <4200000>; ++ factory-internal-resistance-micro-ohms = <180000>; ++ voltage-max-design-microvolt = <4100000>; ++ voltage-min-design-microvolt = <3500000>; ++ ++ ocv-capacity-celsius = <20>; ++ ocv-capacity-table-0 = <4046950 100>, <4001920 95>, <3967900 90>, <3919950 85>, ++ <3888450 80>, <3861850 75>, <3831540 70>, <3799130 65>, ++ <3768190 60>, <3745650 55>, <3726610 50>, <3711630 45>, ++ <3696720 40>, <3685660 35>, <3674950 30>, <3663050 25>, ++ <3649470 20>, <3635260 15>, <3616920 10>, <3592440 5>, ++ <3574170 0>; ++ }; ++ + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; +@@ -472,6 +491,13 @@ usb_midu: BOOST { + }; + }; + ++ rk817_charger: charger { ++ monitored-battery = <&battery>; ++ rockchip,resistor-sense-micro-ohms = <10000>; ++ rockchip,sleep-enter-current-microamp = <300000>; ++ rockchip,sleep-filter-current-microamp = <100000>; ++ }; ++ + rk817_codec: codec { + rockchip,mic-in-differential; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: FUKAUMI Naoki +Date: Thu, 8 Sep 2022 03:17:25 +0000 +Subject: [PATCH] arm64: dts: rockchip: add LED for ROCK Pi 4A/B/C/A+/B+ + +only user_led2 (blue) is supported. + +user_led1 (green) is not connected to any gpio so it cannot be +controlled. + +Signed-off-by: FUKAUMI Naoki +Link: https://lore.kernel.org/r/20220908031726.1307105-1-naoki@radxa.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 21 +++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +index 401e1ae9d944..6464a6729729 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +@@ -6,6 +6,7 @@ + + /dts-v1/; + #include ++#include + #include + #include "rk3399.dtsi" + #include "rk3399-opp.dtsi" +@@ -27,6 +28,20 @@ clkin_gmac: external-gmac-clock { + #clock-cells = <0>; + }; + ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&user_led2>; ++ ++ /* USER_LED2 */ ++ led-0 { ++ function = LED_FUNCTION_STATUS; ++ color = ; ++ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; +@@ -553,6 +568,12 @@ hp_int: hp-int { + }; + }; + ++ leds { ++ user_led2: user-led2 { ++ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + pcie { + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: FUKAUMI Naoki +Date: Thu, 8 Sep 2022 03:17:26 +0000 +Subject: [PATCH] arm64: dts: rockchip: add LEDs for ROCK 4C+ + +add support for user LEDs on Radxa ROCK 4C+ board. + +Signed-off-by: FUKAUMI Naoki +Link: https://lore.kernel.org/r/20220908031726.1307105-2-naoki@radxa.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3399-rock-4c-plus.dts | 33 +++++++++++++++++++ + 1 file changed, 33 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +index a1c4727acfcd..3f01772c66ad 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts +@@ -6,6 +6,7 @@ + */ + + /dts-v1/; ++#include + #include "rk3399.dtsi" + #include "rk3399-t-opp.dtsi" + +@@ -38,6 +39,28 @@ clkin_gmac: external-gmac-clock { + #clock-cells = <0>; + }; + ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&user_led1 &user_led2>; ++ ++ /* USER_LED1 */ ++ led-0 { ++ function = LED_FUNCTION_POWER; ++ color = ; ++ gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; ++ linux,default-trigger = "default-on"; ++ }; ++ ++ /* USER_LED2 */ ++ led-1 { ++ function = LED_FUNCTION_STATUS; ++ color = ; ++ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; +@@ -424,6 +447,16 @@ bt_wake_l: bt-wake-l { + }; + }; + ++ leds { ++ user_led1: user-led1 { ++ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ user_led2: user-led2 { ++ rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Frank Wunderlich +Date: Tue, 6 Sep 2022 18:42:12 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add regulator suffix to BPI-R2-Pro + +Add -regulator suffix to regulator names on Banana Pi R2 Pro board as +discussed on Mailinglist + +Signed-off-by: Frank Wunderlich +Reviewed-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20220906164212.84835-1-linux@fw-web.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +index 7a8d55a898f5..950613595f42 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +@@ -46,7 +46,7 @@ green_led: led-1 { + }; + }; + +- dc_12v: dc-12v { ++ dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; +@@ -66,7 +66,7 @@ hdmi_con_in: endpoint { + }; + }; + +- vcc3v3_sys: vcc3v3-sys { ++ vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; +@@ -76,7 +76,7 @@ vcc3v3_sys: vcc3v3-sys { + vin-supply = <&dc_12v>; + }; + +- vcc5v0_sys: vcc5v0-sys { ++ vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; +@@ -146,7 +146,7 @@ vcc3v3_ngff: vcc3v3-ngff-regulator { + vin-supply = <&vcc3v3_pi6c_05>; + }; + +- vcc5v0_usb: vcc5v0_usb { ++ vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; +@@ -156,7 +156,7 @@ vcc5v0_usb: vcc5v0_usb { + vin-supply = <&dc_12v>; + }; + +- vcc5v0_usb_host: vcc5v0-usb-host { ++ vcc5v0_usb_host: vcc5v0-usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; +@@ -168,7 +168,7 @@ vcc5v0_usb_host: vcc5v0-usb-host { + vin-supply = <&vcc5v0_usb>; + }; + +- vcc5v0_usb_otg: vcc5v0-usb-otg { ++ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Tue, 6 Sep 2022 16:03:22 -0500 +Subject: [PATCH] dt-bindings: vendor-prefixes: add Anbernic + +Anbernic designs and manufactures portable gaming systems. +https://anbernic.com/ + +Signed-off-by: Chris Morgan +Acked-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20220906210324.28986-2-macroalpha82@gmail.com +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml +index dfaff2487b04..e370ffde0692 100644 +--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml ++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml +@@ -105,6 +105,8 @@ patternProperties: + description: AMS-Taos Inc. + "^analogix,.*": + description: Analogix Semiconductor, Inc. ++ "^anbernic,.*": ++ description: Anbernic + "^andestech,.*": + description: Andes Technology Corporation + "^anvo,.*": + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Tue, 6 Sep 2022 16:03:23 -0500 +Subject: [PATCH] dt-bindings: arm: rockchip: Add Anbernic RG353P and RG503 + +Add entry for the Anbernic RG353P and RG503 handheld devices. + +Signed-off-by: Chris Morgan +Acked-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20220906210324.28986-3-macroalpha82@gmail.com +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index 5c1b9f0e4cc1..ae7fe15a3b89 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -30,6 +30,16 @@ properties: + - const: amarula,vyasa-rk3288 + - const: rockchip,rk3288 + ++ - description: Anbernic RG353P ++ items: ++ - const: anbernic,rg353p ++ - const: rockchip,rk3566 ++ ++ - description: Anbernic RG503 ++ items: ++ - const: anbernic,rg503 ++ - const: rockchip,rk3566 ++ + - description: Asus Tinker board + items: + - const: asus,rk3288-tinker + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Tue, 6 Sep 2022 16:03:24 -0500 +Subject: [PATCH] arm64: dts: rockchip: add Anbernic RG353P and RG503 + +Anbernic RG353P and RG503 are both RK3566 based handheld gaming devices +from Anbernic. + +Both devices have: + - 2 SDMMC slots. + - A Realtek rtl8821cs WiFi/Bluetooth adapter. + - A mini HDMI port. + - A USB C host port and a USB C otg port (currently only working as + device). + - Multiple GPIO buttons and a single ADC button. + - Dual analog joysticks controlled via a GPIO mux. + - A headphone jack with amplified stereo speakers via a SGM4865 amp. + - A PWM based vibrator for force feedback. + +The RG353P has: + - 2GB LPDDR4 RAM. + - A 32GB eMMC. + - A 3.5 inch 640x480 4-lane DSI panel of unknown origin with an i2c + controlled touchscreen (touchscreen is a Hynitron CST340). + +The RG503 has: + - 1GB LPDDR4 RAM. + - A 5 inch 960x544 AMOLED 2-lane DSI/DBI panel manufactured by Samsung + with part number ams495qa04. Data for this panel is provided via the + DSI interface, however commands are sent via a 9-bit 3-wire SPI + interface. The MISO pin of SPI3 of the SOC is wired to the input of + the panel, so it must be bitbanged. + +This devicetree enables the following hardware: + - HDMI (plus audio). + - Analog audio, including speakers. + - All buttons. + - All SDMMC/eMMC/SDIO controllers. + - The ADC joysticks (note a pending patch is required to use them). + - WiFi/Bluetooth (note out of tree drivers are required). + - The PWM based vibrator motor. + +The following hardware is not enabled: + - The display panels (drivers are being written and there are issues + with the upstream DSI and VOP2 subsystems). + - Battery (driver pending). + - Touchscreen on the RG353P (note the i2c2 bus is enabled for it). + +Signed-off-by: Chris Morgan +Link: https://lore.kernel.org/r/20220906210324.28986-4-macroalpha82@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 2 + + .../dts/rockchip/rk3566-anbernic-rg353p.dts | 94 ++ + .../dts/rockchip/rk3566-anbernic-rg503.dts | 87 ++ + .../dts/rockchip/rk3566-anbernic-rgxx3.dtsi | 831 ++++++++++++++++++ + 4 files changed, 1014 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts + create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts + create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index cdd1f211496d..94639380ec1e 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -60,6 +60,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353p.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts +new file mode 100644 +index 000000000000..7a20e2d6876a +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts +@@ -0,0 +1,94 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include "rk3566-anbernic-rgxx3.dtsi" ++ ++/ { ++ model = "RG353P"; ++ compatible = "anbernic,rg353p", "rockchip,rk3566"; ++ ++ aliases { ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc0; ++ mmc2 = &sdmmc1; ++ mmc3 = &sdmmc2; ++ }; ++ ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ power-supply = <&vcc_sys>; ++ pwms = <&pwm4 0 25000 0>; ++ }; ++}; ++ ++&gpio_keys_control { ++ button-a { ++ gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; ++ label = "EAST"; ++ linux,code = ; ++ }; ++ ++ button-left { ++ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; ++ label = "DPAD-LEFT"; ++ linux,code = ; ++ }; ++ ++ button-r1 { ++ gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; ++ label = "TR"; ++ linux,code = ; ++ }; ++ ++ button-r2 { ++ gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; ++ label = "TR2"; ++ linux,code = ; ++ }; ++ ++ button-right { ++ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; ++ label = "DPAD-RIGHT"; ++ linux,code = ; ++ }; ++ ++ button-y { ++ gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; ++ label = "WEST"; ++ linux,code = ; ++ }; ++}; ++ ++&i2c0 { ++ /* This hardware is physically present but unused. */ ++ power-monitor@62 { ++ compatible = "cellwise,cw2015"; ++ reg = <0x62>; ++ status = "disabled"; ++ }; ++}; ++ ++&i2c2 { ++ pintctrl-names = "default"; ++ pinctrl-0 = <&i2c2m1_xfer>; ++ status = "okay"; ++}; ++ ++&pwm4 { ++ status = "okay"; ++}; ++ ++&sdhci { ++ pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, <&emmc_datastrobe>, <&emmc_rstnout>; ++ pinctrl-names = "default"; ++ bus-width = <8>; ++ mmc-hs200-1_8v; ++ non-removable; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "okay"; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts +new file mode 100644 +index 000000000000..3dc01549a5b4 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts +@@ -0,0 +1,87 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include "rk3566-anbernic-rgxx3.dtsi" ++ ++/ { ++ model = "RG503"; ++ compatible = "anbernic,rg503", "rockchip,rk3566"; ++ ++ aliases { ++ mmc0 = &sdmmc0; ++ mmc1 = &sdmmc1; ++ mmc2 = &sdmmc2; ++ }; ++ ++ gpio_spi: spi { ++ compatible = "spi-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ sck-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; ++ mosi-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; ++ cs-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; ++ num-chipselects = <0>; ++ }; ++}; ++ ++&gpio_keys_control { ++ button-a { ++ gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; ++ label = "EAST"; ++ linux,code = ; ++ }; ++ ++ button-left { ++ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; ++ label = "DPAD-LEFT"; ++ linux,code = ; ++ }; ++ ++ button-right { ++ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; ++ label = "DPAD-RIGHT"; ++ linux,code = ; ++ }; ++ ++ button-r1 { ++ gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; ++ label = "TR"; ++ linux,code = ; ++ }; ++ ++ button-r2 { ++ gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; ++ label = "TR2"; ++ linux,code = ; ++ }; ++ ++ button-right { ++ gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; ++ label = "DPAD-RIGHT"; ++ linux,code = ; ++ }; ++ ++ button-y { ++ gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; ++ label = "WEST"; ++ linux,code = ; ++ }; ++}; ++ ++&pinctrl { ++ gpio-spi { ++ spi_pins: spi-pins { ++ rockchip,pins = ++ <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, ++ <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, ++ <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi +new file mode 100644 +index 000000000000..2b455143b86d +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi +@@ -0,0 +1,831 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include ++#include ++#include "rk3566.dtsi" ++ ++/ { ++ chosen: chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ adc-joystick { ++ compatible = "adc-joystick"; ++ io-channels = <&adc_mux 0>, ++ <&adc_mux 1>, ++ <&adc_mux 2>, ++ <&adc_mux 3>; ++ pinctrl-0 = <&joy_mux_en>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ axis@0 { ++ reg = <0>; ++ abs-flat = <32>; ++ abs-fuzz = <32>; ++ abs-range = <1023 15>; ++ linux,code = ; ++ }; ++ ++ axis@1 { ++ reg = <1>; ++ abs-flat = <32>; ++ abs-fuzz = <32>; ++ abs-range = <15 1023>; ++ linux,code = ; ++ }; ++ ++ axis@2 { ++ reg = <2>; ++ abs-flat = <32>; ++ abs-fuzz = <32>; ++ abs-range = <15 1023>; ++ linux,code = ; ++ }; ++ ++ axis@3 { ++ reg = <3>; ++ abs-flat = <32>; ++ abs-fuzz = <32>; ++ abs-range = <1023 15>; ++ linux,code = ; ++ }; ++ }; ++ ++ adc_keys: adc-keys { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 0>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <1800000>; ++ poll-interval = <60>; ++ ++ /* ++ * Button is mapped to F key in BSP kernel, but ++ * according to input guidelines it should be mode. ++ */ ++ button-mode { ++ label = "MODE"; ++ linux,code = ; ++ press-threshold-microvolt = <1750>; ++ }; ++ }; ++ ++ adc_mux: adc-mux { ++ compatible = "io-channel-mux"; ++ channels = "left_x", "right_x", "left_y", "right_y"; ++ #io-channel-cells = <1>; ++ io-channels = <&saradc 3>; ++ io-channel-names = "parent"; ++ mux-controls = <&gpio_mux>; ++ settle-time-us = <100>; ++ }; ++ ++ gpio_keys_control: gpio-keys-control { ++ compatible = "gpio-keys"; ++ pinctrl-0 = <&btn_pins_ctrl>; ++ pinctrl-names = "default"; ++ ++ button-b { ++ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>; ++ label = "SOUTH"; ++ linux,code = ; ++ }; ++ ++ button-down { ++ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; ++ label = "DPAD-DOWN"; ++ linux,code = ; ++ }; ++ ++ button-l1 { ++ gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; ++ label = "TL"; ++ linux,code = ; ++ }; ++ ++ button-l2 { ++ gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; ++ label = "TL2"; ++ linux,code = ; ++ }; ++ ++ button-select { ++ gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; ++ label = "SELECT"; ++ linux,code = ; ++ }; ++ ++ button-start { ++ gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; ++ label = "START"; ++ linux,code = ; ++ }; ++ ++ button-thumbl { ++ gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; ++ label = "THUMBL"; ++ linux,code = ; ++ }; ++ ++ button-thumbr { ++ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; ++ label = "THUMBR"; ++ linux,code = ; ++ }; ++ ++ button-up { ++ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; ++ label = "DPAD-UP"; ++ linux,code = ; ++ }; ++ ++ button-x { ++ gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; ++ label = "NORTH"; ++ linux,code = ; ++ }; ++ }; ++ ++ gpio_keys_vol: gpio-keys-vol { ++ compatible = "gpio-keys"; ++ autorepeat; ++ pinctrl-0 = <&btn_pins_vol>; ++ pinctrl-names = "default"; ++ ++ button-vol-down { ++ gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; ++ label = "VOLUMEDOWN"; ++ linux,code = ; ++ }; ++ ++ button-vol-up { ++ gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; ++ label = "VOLUMEUP"; ++ linux,code = ; ++ }; ++ }; ++ ++ gpio_mux: mux-controller { ++ compatible = "gpio-mux"; ++ mux-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>, ++ <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; ++ #mux-control-cells = <0>; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ ddc-i2c-bus = <&i2c5>; ++ type = "c"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ leds: gpio-leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&led_pins>; ++ pinctrl-names = "default"; ++ ++ green_led: led-0 { ++ color = ; ++ default-state = "on"; ++ function = LED_FUNCTION_POWER; ++ gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ amber_led: led-1 { ++ color = ; ++ function = LED_FUNCTION_CHARGING; ++ gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; ++ retain-state-suspended; ++ }; ++ ++ red_led: led-2 { ++ color = ; ++ default-state = "off"; ++ function = LED_FUNCTION_STATUS; ++ gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ /* Channels reversed for both headphones and speakers. */ ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "anbernic_rk817"; ++ simple-audio-card,aux-devs = <&spk_amp>; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,widgets = ++ "Microphone", "Mic Jack", ++ "Headphone", "Headphones", ++ "Speaker", "Internal Speakers"; ++ simple-audio-card,routing = ++ "MICL", "Mic Jack", ++ "Headphones", "HPOL", ++ "Headphones", "HPOR", ++ "Internal Speakers", "Speaker Amp OUTL", ++ "Internal Speakers", "Speaker Amp OUTR", ++ "Speaker Amp INL", "HPOL", ++ "Speaker Amp INR", "HPOR"; ++ simple-audio-card,pin-switches = "Internal Speakers"; ++ ++ simple-audio-card,codec { ++ sound-dai = <&rk817>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1_8ch>; ++ }; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ clocks = <&rk817 1>; ++ clock-names = "ext_clock"; ++ pinctrl-0 = <&wifi_enable_h>; ++ pinctrl-names = "default"; ++ post-power-on-delay-ms = <200>; ++ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; ++ }; ++ ++ spk_amp: audio-amplifier { ++ compatible = "simple-audio-amplifier"; ++ enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&spk_amp_enable_h>; ++ pinctrl-names = "default"; ++ sound-name-prefix = "Speaker Amp"; ++ }; ++ ++ vcc3v3_lcd0_n: regulator-vcc3v3-lcd0 { ++ compatible = "regulator-fixed"; ++ gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ pinctrl-0 = <&vcc_lcd_h>; ++ pinctrl-names = "default"; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc3v3_lcd0_n"; ++ vin-supply = <&vcc_3v3>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_sys: regulator-vcc-sys { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3800000>; ++ regulator-max-microvolt = <3800000>; ++ regulator-name = "vcc_sys"; ++ }; ++ ++ vcc_wifi: regulator-vcc-wifi { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++ pinctrl-0 = <&vcc_wifi_h>; ++ pinctrl-names = "default"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc_wifi"; ++ }; ++ ++ vibrator: pwm-vibrator { ++ compatible = "pwm-vibrator"; ++ pwm-names = "enable"; ++ pwms = <&pwm5 0 1000000000 0>; ++ }; ++}; ++ ++&combphy1 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ ddc-i2c-bus = <&i2c5>; ++ pinctrl-0 = <&hdmitxm0_cec>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ rk817: pmic@20 { ++ compatible = "rockchip,rk817"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ clock-output-names = "rk808-clkout1", "rk808-clkout2"; ++ clock-names = "mclk"; ++ clocks = <&cru I2S1_MCLKOUT_TX>; ++ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; ++ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; ++ #clock-cells = <1>; ++ #sound-dai-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s1m0_mclk>, <&pmic_int_l>; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc_sys>; ++ vcc2-supply = <&vcc_sys>; ++ vcc3-supply = <&vcc_sys>; ++ vcc4-supply = <&vcc_sys>; ++ vcc5-supply = <&vcc_sys>; ++ vcc6-supply = <&vcc_sys>; ++ vcc7-supply = <&vcc_sys>; ++ vcc8-supply = <&vcc_sys>; ++ vcc9-supply = <&dcdc_boost>; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-init-microvolt = <900000>; ++ regulator-ramp-delay = <6001>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vdd_logic"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-init-microvolt = <900000>; ++ regulator-ramp-delay = <6001>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vdd_gpu"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vcc_ddr"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: DCDC_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-initial-mode = <0x2>; ++ regulator-name = "vcc_3v3"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG1 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcca1v8_pmu"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vdda_0v9"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ regulator-name = "vdda0v9_pmu"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vccio_acodec"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vccio_sd"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc3v3_pmu"; ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcc_1v8: LDO_REG7 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vcc_1v8"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc1v8_dvp: LDO_REG8 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc1v8_dvp"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc2v8_dvp: LDO_REG9 { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "vcc2v8_dvp"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ dcdc_boost: BOOST { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <4700000>; ++ regulator-max-microvolt = <5400000>; ++ regulator-name = "boost"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ otg_switch: OTG_SWITCH { ++ regulator-name = "otg_switch"; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++ ++ vdd_cpu: regulator@40 { ++ compatible = "fcs,fan53555"; ++ reg = <0x40>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <712500>; ++ regulator-max-microvolt = <1390000>; ++ regulator-init-microvolt = <900000>; ++ regulator-name = "vdd_cpu"; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc_sys>; ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ /* Unknown/unused device at 0x3c */ ++ status = "disabled"; ++}; ++ ++&i2c5 { ++ pinctrl-0 = <&i2c5m1_xfer>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&i2s1_8ch { ++ pinctrl-0 = <&i2s1m0_sclktx ++ &i2s1m0_lrcktx ++ &i2s1m0_sdi0 ++ &i2s1m0_sdo0>; ++ pinctrl-names = "default"; ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ audio-amplifier { ++ spk_amp_enable_h: spk-amp-enable-h { ++ rockchip,pins = ++ <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ gpio-btns { ++ btn_pins_ctrl: btn-pins-ctrl { ++ rockchip,pins = ++ <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ ++ btn_pins_vol: btn-pins-vol { ++ rockchip,pins = ++ <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, ++ <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ gpio-led { ++ led_pins: led-pins { ++ rockchip,pins = ++ <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, ++ <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, ++ <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ joy-mux { ++ joy_mux_en: joy-mux-en { ++ rockchip,pins = ++ <0 RK_PB5 RK_FUNC_GPIO &pcfg_output_low>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = ++ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ sdio-pwrseq { ++ wifi_enable_h: wifi-enable-h { ++ rockchip,pins = ++ <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ vcc3v3-lcd { ++ vcc_lcd_h: vcc-lcd-h { ++ rockchip,pins = ++ <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ vcc-wifi { ++ vcc_wifi_h: vcc-wifi-h { ++ rockchip,pins = ++ <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ status = "okay"; ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc1v8_dvp>; ++ vccio7-supply = <&vcc_3v3>; ++}; ++ ++&pwm5 { ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ pinctrl-names = "default"; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&sdmmc1 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &sdmmc1_det>; ++ pinctrl-names = "default"; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc1v8_dvp>; ++ status = "okay"; ++}; ++ ++&sdmmc2 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cap-sdio-irq; ++ keep-power-in-suspend; ++ mmc-pwrseq = <&sdio_pwrseq>; ++ non-removable; ++ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; ++ pinctrl-names = "default"; ++ vmmc-supply = <&vcc_wifi>; ++ vqmmc-supply = <&vcca1v8_pmu>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>; ++ pinctrl-names = "default"; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "realtek,rtl8821cs-bt"; ++ device-wake-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; ++ enable-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; ++ host-wake-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++/* ++ * Lack the schematics to verify, but port works as a peripheral ++ * (and not a host or OTG port). ++ */ ++&usb_host0_xhci { ++ dr_mode = "peripheral"; ++ phys = <&usb2phy0_otg>; ++ phy-names = "usb2-phy"; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ phy-names = "usb2-phy", "usb3-phy"; ++ phys = <&usb2phy1_host>, <&combphy1 PHY_TYPE_USB3>; ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Mon, 18 Jul 2022 05:31:45 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add PCIe 2 nodes to quartz64-b + +This adds the regulator node to the quartz64-b device tree, +and enables the PCIe 2 controller and combphy for it. + +Signed-off-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20220718033145.792657-1-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3566-quartz64-b.dts | 34 +++++++++++++++++++ + 1 file changed, 34 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +index 3897980d69d1..1f709e5d8a87 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts +@@ -69,6 +69,18 @@ sdio_pwrseq: sdio-pwrseq { + power-off-delay-us = <5000000>; + }; + ++ vcc3v3_pcie_p: vcc3v3-pcie-p-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_enable_h>; ++ regulator-name = "vcc3v3_pcie_p"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc_3v3>; ++ }; ++ + vcc5v0_in: vcc5v0-in-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_in"; +@@ -128,6 +140,10 @@ &combphy1 { + status = "okay"; + }; + ++&combphy2 { ++ status = "okay"; ++}; ++ + &cpu0 { + cpu-supply = <&vdd_cpu>; + }; +@@ -457,6 +473,14 @@ rgmii_phy1: ethernet-phy@1 { + }; + }; + ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_reset_h>; ++ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie_p>; ++ status = "okay"; ++}; ++ + &pinctrl { + bt { + bt_enable_h: bt-enable-h { +@@ -478,6 +502,16 @@ user_led_enable_h: user-led-enable-h { + }; + }; + ++ pcie { ++ pcie_enable_h: pcie-enable-h { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie_reset_h: pcie-reset-h { ++ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + pmic { + pmic_int: pmic_int { + rockchip,pins = + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Tue, 26 Jul 2022 10:30:46 +0800 +Subject: [PATCH] arm64: dts: rockchip: add rtc to rock3a + +Add devicetree node for hym8563 rtc to +Radxa ROCK3 Model A board. + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20220726023046.5876-1-amadeus@jmu.edu.cn +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3568-rock-3a.dts | 23 +++++++++++++++++++ + 1 file changed, 23 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +index cd8cc0c3c68a..037a2c3b1602 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +@@ -484,6 +484,23 @@ &i2c4 { + status = "disabled"; + }; + ++&i2c5 { ++ status = "okay"; ++ ++ hym8563: rtc@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <0>; ++ clock-frequency = <32768>; ++ clock-output-names = "rtcic_32kout"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ wakeup-source; ++ }; ++}; ++ + &i2s0_8ch { + status = "okay"; + }; +@@ -524,6 +541,12 @@ eth_phy_rst: eth_phy_rst { + }; + }; + ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ + leds { + led_user_en: led_user_en { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chukun Pan +Date: Tue, 26 Jul 2022 10:35:16 +0800 +Subject: [PATCH] arm64: dts: rockchip: Enable PCIe controller on rock3a + +Add the nodes to enable the PCIe controller on the +Radxa ROCK3 Model A board. Run test with the MT7921 +pcie wireless card. + +Signed-off-by: Chukun Pan +Link: https://lore.kernel.org/r/20220726023516.6487-1-amadeus@jmu.edu.cn +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3568-rock-3a.dts | 34 +++++++++++++++++++ + 1 file changed, 34 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +index 037a2c3b1602..e35f6ce812bd 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +@@ -67,6 +67,18 @@ vcc12v_dcin: vcc12v-dcin { + regulator-boot-on; + }; + ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_enable_h>; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; +@@ -173,6 +185,10 @@ &combphy1 { + status = "okay"; + }; + ++&combphy2 { ++ status = "okay"; ++}; ++ + &cpu0 { + cpu-supply = <&vdd_cpu>; + }; +@@ -522,6 +538,14 @@ rgmii_phy1: ethernet-phy@0 { + }; + }; + ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_reset_h>; ++ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ + &pinctrl { + cam { + vcc_cam_en: vcc_cam_en { +@@ -553,6 +577,16 @@ led_user_en: led_user_en { + }; + }; + ++ pcie { ++ pcie_enable_h: pcie-enable-h { ++ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie_reset_h: pcie-reset-h { ++ rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + pmic { + pmic_int: pmic_int { + rockchip,pins = + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Piotr Oniszczuk +Date: Mon, 14 Feb 2022 22:29:54 +0100 +Subject: [PATCH] arm64: dts: rockchip: Add VPU support for RK3568/RK3566 + +RK356x has Hantro G1 video decoder capable to decode MPEG2/H.264/VP8 +video formats. + +This patch enables RK356x video decoder in RK356x device-tree +include. + +Tested on [1] with FFmpeg v4l2_request code taken from [2] +with MPEG2, H.642 and VP8 samples with results [3]. + +[1] https://github.com/warpme/minimyth2 +[2] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch +[3] https://github.com/warpme/minimyth2/blob/master/video-test-summary.txt + +Signed-off-by: Piotr Oniszczuk +Reviewed-by: Ezequiel Garcia +Link: https://lore.kernel.org/r/20220214212955.1178947-2-piotr.oniszczuk@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +index c66b60302803..351797102a19 100644 +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -592,6 +592,26 @@ gpu: gpu@fde60000 { + status = "disabled"; + }; + ++ vpu: video-codec@fdea0400 { ++ compatible = "rockchip,rk3568-vpu"; ++ reg = <0x0 0xfdea0000 0x0 0x800>; ++ interrupts = ; ++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; ++ clock-names = "aclk", "hclk"; ++ iommus = <&vdpu_mmu>; ++ power-domains = <&power RK3568_PD_VPU>; ++ }; ++ ++ vdpu_mmu: iommu@fdea0800 { ++ compatible = "rockchip,rk3568-iommu"; ++ reg = <0x0 0xfdea0800 0x0 0x40>; ++ interrupts = ; ++ clock-names = "aclk", "iface"; ++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; ++ power-domains = <&power RK3568_PD_VPU>; ++ #iommu-cells = <0>; ++ }; ++ + sdmmc2: mmc@fe000000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe000000 0x0 0x4000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nicolas Frattaroli +Date: Sun, 12 Jun 2022 17:53:46 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add Hantro encoder node to rk356x + +The RK3566 and RK3568 come with a dedicated Hantro instance solely for +encoding. This patch adds a node for this to the device tree, along with +a node for its MMU. + +Signed-off-by: Nicolas Frattaroli +Link: https://lore.kernel.org/r/20220612155346.16288-4-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +index 351797102a19..fd903e697aa2 100644 +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -612,6 +612,26 @@ vdpu_mmu: iommu@fdea0800 { + #iommu-cells = <0>; + }; + ++ vepu: video-codec@fdee0000 { ++ compatible = "rockchip,rk3568-vepu"; ++ reg = <0x0 0xfdee0000 0x0 0x800>; ++ interrupts = ; ++ clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; ++ clock-names = "aclk", "hclk"; ++ iommus = <&vepu_mmu>; ++ power-domains = <&power RK3568_PD_RGA>; ++ }; ++ ++ vepu_mmu: iommu@fdee0800 { ++ compatible = "rockchip,rk3568-iommu"; ++ reg = <0x0 0xfdee0800 0x0 0x40>; ++ interrupts = ; ++ clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; ++ clock-names = "aclk", "iface"; ++ power-domains = <&power RK3568_PD_RGA>; ++ #iommu-cells = <0>; ++ }; ++ + sdmmc2: mmc@fe000000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe000000 0x0 0x4000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Judy Hsiao +Date: Fri, 8 Jul 2022 08:07:26 +0000 +Subject: [PATCH] arm64: dts: rockchip: use BCLK to GPIO switch on rk3399 + +We discoverd that the state of BCLK on, LRCLK off and SD_MODE on +may cause the speaker melting issue. Removing LRCLK while BCLK +is present can cause unexpected output behavior including a large +DC output voltage as described in the Max98357a datasheet. + +In order to: + 1. prevent BCLK from turning on by other component. + 2. keep BCLK and LRCLK being present at the same time + +This patch adjusts the device tree to allow BCLK to switch +to GPIO func before LRCLK output, and switch back during +LRCLK is output. + +Signed-off-by: Judy Hsiao +Reviewed-by: Brian Norris +Link: https://lore.kernel.org/r/20220708080726.4170711-1-judyhsiao@chromium.org +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 10 ++++++++ + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 25 ++++++++++++++++++- + 2 files changed, 34 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +index 40d4053fba80..ed3348b558f8 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +@@ -768,6 +768,16 @@ &i2s0_8ch_bus { + <4 RK_PA0 1 &pcfg_pull_none_6ma>; + }; + ++&i2s0_8ch_bus_bclk_off { ++ rockchip,pins = ++ <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none_6ma>, ++ <3 RK_PD1 1 &pcfg_pull_none_6ma>, ++ <3 RK_PD2 1 &pcfg_pull_none_6ma>, ++ <3 RK_PD3 1 &pcfg_pull_none_6ma>, ++ <3 RK_PD7 1 &pcfg_pull_none_6ma>, ++ <4 RK_PA0 1 &pcfg_pull_none_6ma>; ++}; ++ + /* there is no external pull up, so need to set this pin pull up */ + &sdmmc_cd_pin { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 9d5b0e8c9cca..f4fbd5bece0e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1664,8 +1664,9 @@ i2s0: i2s@ff880000 { + dma-names = "tx", "rx"; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; +- pinctrl-names = "default"; ++ pinctrl-names = "bclk_on", "bclk_off"; + pinctrl-0 = <&i2s0_8ch_bus>; ++ pinctrl-1 = <&i2s0_8ch_bus_bclk_off>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; +@@ -2409,6 +2410,19 @@ i2s0_8ch_bus: i2s0-8ch-bus { + <3 RK_PD7 1 &pcfg_pull_none>, + <4 RK_PA0 1 &pcfg_pull_none>; + }; ++ ++ i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off { ++ rockchip,pins = ++ <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, ++ <3 RK_PD1 1 &pcfg_pull_none>, ++ <3 RK_PD2 1 &pcfg_pull_none>, ++ <3 RK_PD3 1 &pcfg_pull_none>, ++ <3 RK_PD4 1 &pcfg_pull_none>, ++ <3 RK_PD5 1 &pcfg_pull_none>, ++ <3 RK_PD6 1 &pcfg_pull_none>, ++ <3 RK_PD7 1 &pcfg_pull_none>, ++ <4 RK_PA0 1 &pcfg_pull_none>; ++ }; + }; + + i2s1 { +@@ -2420,6 +2434,15 @@ i2s1_2ch_bus: i2s1-2ch-bus { + <4 RK_PA6 1 &pcfg_pull_none>, + <4 RK_PA7 1 &pcfg_pull_none>; + }; ++ ++ i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off { ++ rockchip,pins = ++ <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, ++ <4 RK_PA4 1 &pcfg_pull_none>, ++ <4 RK_PA5 1 &pcfg_pull_none>, ++ <4 RK_PA6 1 &pcfg_pull_none>, ++ <4 RK_PA7 1 &pcfg_pull_none>; ++ }; + }; + + sdio0 { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Furkan Kardame +Date: Mon, 27 Jun 2022 23:22:08 +0300 +Subject: [PATCH] arm64: dts: rockchip: Enable video output on rk3566-roc-pc + +Add the device tree nodes to enable video output on the Station M2. +Enable the GPU and HDMI nodes and fix the GPU regulator range. + +Signed-off-by: Furkan Kardame +Link: https://lore.kernel.org/r/20220627202208.45770-1-f.kardame@manjaro.org +Signed-off-by: Heiko Stuebner +--- + .../arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 52 +++++++++++++++++++ + 1 file changed, 52 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts +index 57759b66d44d..dba648c2f57e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts +@@ -4,6 +4,7 @@ + + #include + #include ++#include + #include "rk3566.dtsi" + + / { +@@ -27,6 +28,17 @@ gmac1_clkin: external-gmac1-clock { + #clock-cells = <0>; + }; + ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -149,6 +161,29 @@ &gmac1m0_clkinout + status = "okay"; + }; + ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &i2c0 { + status = "okay"; + +@@ -577,3 +612,20 @@ &usb_host0_ehci { + &usb_host0_ohci { + status = "okay"; + }; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Hugh Cole-Baker +Date: Tue, 19 Oct 2021 22:58:43 +0100 +Subject: [PATCH] arm64: dts: rockchip: enable gamma control on RK3399 + +Define the memory region on RK3399 VOPs containing the gamma LUT at +base+0x2000. + +Signed-off-by: Hugh Cole-Baker +Tested-by: Linus Heckemann +Link: https://lore.kernel.org/r/20211019215843.42718-4-sigmaris@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index f4fbd5bece0e..92c2207e686c 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1702,7 +1702,7 @@ i2s2: i2s@ff8a0000 { + + vopl: vop@ff8f0000 { + compatible = "rockchip,rk3399-vop-lit"; +- reg = <0x0 0xff8f0000 0x0 0x3efc>; ++ reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>; + interrupts = ; + assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + assigned-clock-rates = <400000000>, <100000000>; +@@ -1758,7 +1758,7 @@ vopl_mmu: iommu@ff8f3f00 { + + vopb: vop@ff900000 { + compatible = "rockchip,rk3399-vop-big"; +- reg = <0x0 0xff900000 0x0 0x3efc>; ++ reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>; + interrupts = ; + assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; + assigned-clock-rates = <400000000>, <100000000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Brian Norris +Date: Wed, 17 Aug 2022 12:33:55 -0700 +Subject: [PATCH] dt-bindings: arm: rockchip: Add gru-scarlet sku{2,4} variants + +The Gru-Scarlet family includes a variety of SKU identifiers, using +parts of a 3-bit space {0..7}. SKU2 and SKU4 devices (under a few +different manufacturer names) also use the Innolux display. + +For reference, the original vendor tree source: + +CHROMIUM: arm64: dts: rockchip: add sku{0,2,4} compatibility +https://chromium.googlesource.com/chromiumos/third_party/kernel/+/f6ed665c9e2eb37fb2680debbb36ec9fb0e8fb97 + +CHROMIUM: arm64: dts: rockchip: scarlet: add SKU0 device tree +https://chromium.googlesource.com/chromiumos/third_party/kernel/+/9987c8776f4b087d135d761e59f7fa6cc83fc7fc + +Signed-off-by: Brian Norris +Link: https://lore.kernel.org/r/20220817123350.1.Ibb15bab32dbfa0d89f86321c4eae7adbc8d7ad4a@changeid +Signed-off-by: Heiko Stuebner +--- + .../devicetree/bindings/arm/rockchip.yaml | 27 ++++++++++++++++++- + 1 file changed, 26 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index ae7fe15a3b89..58fc4b677321 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -373,30 +373,55 @@ properties: + - const: google,gru + - const: rockchip,rk3399 + +- - description: Google Scarlet - Innolux display (Acer Chromebook Tab 10) ++ - description: | ++ Google Scarlet - Innolux display (Acer Chromebook Tab 10 and more) + items: ++ - const: google,scarlet-rev15-sku2 ++ - const: google,scarlet-rev15-sku4 + - const: google,scarlet-rev15-sku6 + - const: google,scarlet-rev15 ++ - const: google,scarlet-rev14-sku2 ++ - const: google,scarlet-rev14-sku4 + - const: google,scarlet-rev14-sku6 + - const: google,scarlet-rev14 ++ - const: google,scarlet-rev13-sku2 ++ - const: google,scarlet-rev13-sku4 + - const: google,scarlet-rev13-sku6 + - const: google,scarlet-rev13 ++ - const: google,scarlet-rev12-sku2 ++ - const: google,scarlet-rev12-sku4 + - const: google,scarlet-rev12-sku6 + - const: google,scarlet-rev12 ++ - const: google,scarlet-rev11-sku2 ++ - const: google,scarlet-rev11-sku4 + - const: google,scarlet-rev11-sku6 + - const: google,scarlet-rev11 ++ - const: google,scarlet-rev10-sku2 ++ - const: google,scarlet-rev10-sku4 + - const: google,scarlet-rev10-sku6 + - const: google,scarlet-rev10 ++ - const: google,scarlet-rev9-sku2 ++ - const: google,scarlet-rev9-sku4 + - const: google,scarlet-rev9-sku6 + - const: google,scarlet-rev9 ++ - const: google,scarlet-rev8-sku2 ++ - const: google,scarlet-rev8-sku4 + - const: google,scarlet-rev8-sku6 + - const: google,scarlet-rev8 ++ - const: google,scarlet-rev7-sku2 ++ - const: google,scarlet-rev7-sku4 + - const: google,scarlet-rev7-sku6 + - const: google,scarlet-rev7 ++ - const: google,scarlet-rev6-sku2 ++ - const: google,scarlet-rev6-sku4 + - const: google,scarlet-rev6-sku6 + - const: google,scarlet-rev6 ++ - const: google,scarlet-rev5-sku2 ++ - const: google,scarlet-rev5-sku4 + - const: google,scarlet-rev5-sku6 + - const: google,scarlet-rev5 ++ - const: google,scarlet-rev4-sku2 ++ - const: google,scarlet-rev4-sku4 + - const: google,scarlet-rev4-sku6 + - const: google,scarlet-rev4 + - const: google,scarlet + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Brian Norris +Date: Wed, 17 Aug 2022 12:33:56 -0700 +Subject: [PATCH] arm64: dts: rockchip: Support gru-scarlet sku{2,4} variants + +The Gru-Scarlet family includes a variety of SKU identifiers, using +parts of a 3-bit space {0..7}. SKU2 and SKU4 devices (under a few +different manufacturer names) also use the Innolux display. + +Without this, a SKU2 device may non-deterministically (depending on the +matching order of DTBs and bootloader behavior) select either one of the +INX DTBs (rk3399-gru-scarlet-dumo.dtb or rk3399-gru-scarlet-inx.dtb) or +the KingDisplay DTB (rk3399-gru-scarlet-kd.dtb), to ill effect. + +For reference, the original vendor tree source: + +CHROMIUM: arm64: dts: rockchip: add sku{0,2,4} compatibility +https://chromium.googlesource.com/chromiumos/third_party/kernel/+/f6ed665c9e2eb37fb2680debbb36ec9fb0e8fb97 + +CHROMIUM: arm64: dts: rockchip: scarlet: add SKU0 device tree +https://chromium.googlesource.com/chromiumos/third_party/kernel/+/9987c8776f4b087d135d761e59f7fa6cc83fc7fc + +Signed-off-by: Brian Norris +Link: https://lore.kernel.org/r/20220817123350.2.I5f4fd0808a927b08e267c189712fb4a85931fd3b@changeid +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3399-gru-scarlet-inx.dts | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts +index 2d721a974790..5d1879033e7c 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dts +@@ -11,17 +11,29 @@ + + / { + model = "Google Scarlet"; +- compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15", ++ compatible = "google,scarlet-rev15-sku2", "google,scarlet-rev15-sku4", ++ "google,scarlet-rev15-sku6", "google,scarlet-rev15", ++ "google,scarlet-rev14-sku2", "google,scarlet-rev14-sku4", + "google,scarlet-rev14-sku6", "google,scarlet-rev14", ++ "google,scarlet-rev13-sku2", "google,scarlet-rev13-sku4", + "google,scarlet-rev13-sku6", "google,scarlet-rev13", ++ "google,scarlet-rev12-sku2", "google,scarlet-rev12-sku4", + "google,scarlet-rev12-sku6", "google,scarlet-rev12", ++ "google,scarlet-rev11-sku2", "google,scarlet-rev11-sku4", + "google,scarlet-rev11-sku6", "google,scarlet-rev11", ++ "google,scarlet-rev10-sku2", "google,scarlet-rev10-sku4", + "google,scarlet-rev10-sku6", "google,scarlet-rev10", ++ "google,scarlet-rev9-sku2", "google,scarlet-rev9-sku4", + "google,scarlet-rev9-sku6", "google,scarlet-rev9", ++ "google,scarlet-rev8-sku2", "google,scarlet-rev8-sku4", + "google,scarlet-rev8-sku6", "google,scarlet-rev8", ++ "google,scarlet-rev7-sku2", "google,scarlet-rev7-sku4", + "google,scarlet-rev7-sku6", "google,scarlet-rev7", ++ "google,scarlet-rev6-sku2", "google,scarlet-rev6-sku4", + "google,scarlet-rev6-sku6", "google,scarlet-rev6", ++ "google,scarlet-rev5-sku2", "google,scarlet-rev5-sku4", + "google,scarlet-rev5-sku6", "google,scarlet-rev5", ++ "google,scarlet-rev4-sku2", "google,scarlet-rev4-sku4", + "google,scarlet-rev4-sku6", "google,scarlet-rev4", + "google,scarlet", "google,gru", "rockchip,rk3399"; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Markus Reichl +Date: Thu, 15 Sep 2022 13:11:36 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add HDMI supplies on rk3399-roc-pc + +Add avdd-0v9-supply and avdd-1v8-supply to hdmi node for +rk3399-roc-pc to silence dmesg warning and match the name +of the 1v8 supply to the circuit sheet. + +Signed-off-by: Markus Reichl +Link: https://lore.kernel.org/r/20220915111138.1108-1-m.reichl@fivetechno.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +index acb174d3a8c5..2f4b1b2e3ac7 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +@@ -271,6 +271,8 @@ &gpu { + }; + + &hdmi { ++ avdd-0v9-supply = <&vcca0v9_hdmi>; ++ avdd-1v8-supply = <&vcca1v8_hdmi>; + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; +@@ -369,8 +371,8 @@ regulator-state-mem { + }; + }; + +- vcc1v8_hdmi: LDO_REG2 { +- regulator-name = "vcc1v8_hdmi"; ++ vcca1v8_hdmi: LDO_REG2 { ++ regulator-name = "vcca1v8_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Quentin Schulz +Date: Fri, 16 Sep 2022 11:17:46 +0200 +Subject: [PATCH] arm64: dts: rockchip: add i2s0 I2S/PDM/TDM 8ch controller to + px30 + +The Rockchip PX30 SoC has three I2S controllers, i2s1 and i2s2 are +2-channel I2S/PCM controllers handled by the same controller driver, and +i2s0 a 8-channel I2S/PCM/TDM controller handled by another controller +driver. + +This adds the device tree node required to enable I2S0 on PX30. + +This was tested in a 2-channel I2S with TX BCLK/LRCK for both TX and RX +(rockchip,trcm-sync-tx-only) setup on a soon-to-be-released board. + +Signed-off-by: Quentin Schulz +Link: https://lore.kernel.org/r/20220916091746.35108-1-foss+kernel@0leil.net +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/px30.dtsi | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi +index 214f94fea3dc..bfa3580429d1 100644 +--- a/arch/arm64/boot/dts/rockchip/px30.dtsi ++++ b/arch/arm64/boot/dts/rockchip/px30.dtsi +@@ -365,6 +365,28 @@ uart0: serial@ff030000 { + status = "disabled"; + }; + ++ i2s0_8ch: i2s@ff060000 { ++ compatible = "rockchip,px30-i2s-tdm"; ++ reg = <0x0 0xff060000 0x0 0x1000>; ++ interrupts = ; ++ clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ dmas = <&dmac 16>, <&dmac 17>; ++ dma-names = "tx", "rx"; ++ rockchip,grf = <&grf>; ++ resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; ++ reset-names = "tx-m", "rx-m"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx ++ &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx ++ &i2s0_8ch_sdo0 &i2s0_8ch_sdi0 ++ &i2s0_8ch_sdo1 &i2s0_8ch_sdi1 ++ &i2s0_8ch_sdo2 &i2s0_8ch_sdi2 ++ &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s1_2ch: i2s@ff070000 { + compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff070000 0x0 0x1000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Thu, 15 Sep 2022 10:25:10 +0800 +Subject: [PATCH] dt-bindings: Add doc for FriendlyARM NanoPi R4S Enterprise + Edition + +Add devicetree binding documentation for the FriendlyARM NanoPi R4S +Enterprise Edition. + +Signed-off-by: Tianling Shen +Acked-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20220915022511.4267-1-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index 58fc4b677321..4c64d9ff089c 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -161,6 +161,7 @@ properties: + - friendlyarm,nanopi-m4b + - friendlyarm,nanopi-neo4 + - friendlyarm,nanopi-r4s ++ - friendlyarm,nanopi-r4s-enterprise + - const: rockchip,rk3399 + + - description: GeekBuying GeekBox + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Thu, 15 Sep 2022 10:25:11 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add RK3399 NanoPi R4S Enterprise + Edition + +The only diffrence against the standrard edition is that the enterprise +one has a built-in EEPROM chip which stores a globally unique MAC address. + +Signed-off-by: Tianling Shen +Link: https://lore.kernel.org/r/20220915022511.4267-2-cnsztl@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../rockchip/rk3399-nanopi-r4s-enterprise.dts | 29 +++++++++++++++++++ + 2 files changed, 30 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 94639380ec1e..8c15593c0ca4 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -41,6 +41,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4s-enterprise.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinephone-pro.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts +new file mode 100644 +index 000000000000..a23d11ca0eb6 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s-enterprise.dts +@@ -0,0 +1,29 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++#include "rk3399-nanopi-r4s.dts" ++ ++/ { ++ model = "FriendlyElec NanoPi R4S Enterprise Edition"; ++ compatible = "friendlyarm,nanopi-r4s-enterprise", "rockchip,rk3399"; ++}; ++ ++&gmac { ++ nvmem-cells = <&mac_address>; ++ nvmem-cell-names = "mac-address"; ++}; ++ ++&i2c2 { ++ eeprom@51 { ++ compatible = "microchip,24c02", "atmel,24c02"; ++ reg = <0x51>; ++ pagesize = <16>; ++ size = <256>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ mac_address: mac-address@fa { ++ reg = <0xfa 0x06>; ++ }; ++ }; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Tue, 6 Sep 2022 12:48:21 -0500 +Subject: [PATCH] drm/rockchip: dsi: add rk3568 support + +Add the compatible and GRF definitions for the RK3568 soc. + +Signed-off-by: Chris Morgan +Signed-off-by: Heiko Stuebner +Link: https://patchwork.freedesktop.org/patch/msgid/20220906174823.28561-4-macroalpha82@gmail.com +--- + .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 51 ++++++++++++++++++- + 1 file changed, 49 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +index 110e83aad9bb..bf6948125b84 100644 +--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c ++++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +@@ -179,6 +179,23 @@ + #define RK3399_TXRX_SRC_SEL_ISP0 BIT(4) + #define RK3399_TXRX_TURNREQUEST GENMASK(3, 0) + ++#define RK3568_GRF_VO_CON2 0x0368 ++#define RK3568_DSI0_SKEWCALHS (0x1f << 11) ++#define RK3568_DSI0_FORCETXSTOPMODE (0xf << 4) ++#define RK3568_DSI0_TURNDISABLE BIT(2) ++#define RK3568_DSI0_FORCERXMODE BIT(0) ++ ++/* ++ * Note these registers do not appear in the datasheet, they are ++ * however present in the BSP driver which is where these values ++ * come from. Name GRF_VO_CON3 is assumed. ++ */ ++#define RK3568_GRF_VO_CON3 0x36c ++#define RK3568_DSI1_SKEWCALHS (0x1f << 11) ++#define RK3568_DSI1_FORCETXSTOPMODE (0xf << 4) ++#define RK3568_DSI1_TURNDISABLE BIT(2) ++#define RK3568_DSI1_FORCERXMODE BIT(0) ++ + #define HIWORD_UPDATE(val, mask) (val | (mask) << 16) + + enum { +@@ -735,8 +752,9 @@ static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) + static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, + int mux) + { +- regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, +- mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); ++ if (dsi->cdata->lcdsel_grf_reg < 0) ++ regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, ++ mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); + } + + static int +@@ -963,6 +981,8 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev, + DRM_DEV_ERROR(dev, "Failed to create drm encoder\n"); + goto out_pll_clk; + } ++ rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, ++ dev->of_node, 0, 0); + + ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); + if (ret) { +@@ -1612,6 +1632,30 @@ static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { + { /* sentinel */ } + }; + ++static const struct rockchip_dw_dsi_chip_data rk3568_chip_data[] = { ++ { ++ .reg = 0xfe060000, ++ .lcdsel_grf_reg = -1, ++ .lanecfg1_grf_reg = RK3568_GRF_VO_CON2, ++ .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI0_SKEWCALHS | ++ RK3568_DSI0_FORCETXSTOPMODE | ++ RK3568_DSI0_TURNDISABLE | ++ RK3568_DSI0_FORCERXMODE), ++ .max_data_lanes = 4, ++ }, ++ { ++ .reg = 0xfe070000, ++ .lcdsel_grf_reg = -1, ++ .lanecfg1_grf_reg = RK3568_GRF_VO_CON3, ++ .lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI1_SKEWCALHS | ++ RK3568_DSI1_FORCETXSTOPMODE | ++ RK3568_DSI1_TURNDISABLE | ++ RK3568_DSI1_FORCERXMODE), ++ .max_data_lanes = 4, ++ }, ++ { /* sentinel */ } ++}; ++ + static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { + { + .compatible = "rockchip,px30-mipi-dsi", +@@ -1622,6 +1666,9 @@ static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { + }, { + .compatible = "rockchip,rk3399-mipi-dsi", + .data = &rk3399_chip_data, ++ }, { ++ .compatible = "rockchip,rk3568-mipi-dsi", ++ .data = &rk3568_chip_data, + }, + { /* sentinel */ } + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Hugh Cole-Baker +Date: Tue, 19 Oct 2021 22:58:41 +0100 +Subject: [PATCH] drm/rockchip: define gamma registers for RK3399 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The VOP on RK3399 has a different approach from previous versions for +setting a gamma lookup table, using an update_gamma_lut register. As +this differs from RK3288, give RK3399 its own set of "common" register +definitions. + +Signed-off-by: Hugh Cole-Baker +Tested-by: "Milan P. Stanić" +Tested-by: Linus Heckemann +Signed-off-by: Heiko Stuebner +Link: https://patchwork.freedesktop.org/patch/msgid/20211019215843.42718-2-sigmaris@gmail.com +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 2 ++ + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 24 +++++++++++++++++++-- + drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 1 + + 3 files changed, 25 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +index ba88addc1a75..8502849833d9 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +@@ -113,6 +113,8 @@ struct vop_common { + struct vop_reg dither_down_en; + struct vop_reg dither_up; + struct vop_reg dsp_lut_en; ++ struct vop_reg update_gamma_lut; ++ struct vop_reg lut_buffer_index; + struct vop_reg gate_en; + struct vop_reg mmu_en; + struct vop_reg out_mode; +diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +index d03dd0402923..014f99e8928e 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c ++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +@@ -875,6 +875,24 @@ static const struct vop_output rk3399_output = { + .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), + }; + ++static const struct vop_common rk3399_common = { ++ .standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22), ++ .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23), ++ .mmu_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 20), ++ .dither_down_sel = VOP_REG(RK3399_DSP_CTRL1, 0x1, 4), ++ .dither_down_mode = VOP_REG(RK3399_DSP_CTRL1, 0x1, 3), ++ .dither_down_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 2), ++ .pre_dither_down = VOP_REG(RK3399_DSP_CTRL1, 0x1, 1), ++ .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6), ++ .dsp_lut_en = VOP_REG(RK3399_DSP_CTRL1, 0x1, 0), ++ .update_gamma_lut = VOP_REG(RK3399_DSP_CTRL1, 0x1, 7), ++ .lut_buffer_index = VOP_REG(RK3399_DBG_POST_REG1, 0x1, 1), ++ .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19), ++ .dsp_blank = VOP_REG(RK3399_DSP_CTRL0, 0x3, 18), ++ .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), ++ .cfg_done = VOP_REG_SYNC(RK3399_REG_CFG_DONE, 0x1, 0), ++}; ++ + static const struct vop_yuv2yuv_phy rk3399_yuv2yuv_win01_data = { + .y2r_coefficients = { + VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 0), +@@ -957,7 +975,7 @@ static const struct vop_data rk3399_vop_big = { + .version = VOP_VERSION(3, 5), + .feature = VOP_FEATURE_OUTPUT_RGB10, + .intr = &rk3366_vop_intr, +- .common = &rk3288_common, ++ .common = &rk3399_common, + .modeset = &rk3288_modeset, + .output = &rk3399_output, + .afbc = &rk3399_vop_afbc, +@@ -965,6 +983,7 @@ static const struct vop_data rk3399_vop_big = { + .win = rk3399_vop_win_data, + .win_size = ARRAY_SIZE(rk3399_vop_win_data), + .win_yuv2yuv = rk3399_vop_big_win_yuv2yuv_data, ++ .lut_size = 1024, + }; + + static const struct vop_win_data rk3399_vop_lit_win_data[] = { +@@ -983,13 +1002,14 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { + static const struct vop_data rk3399_vop_lit = { + .version = VOP_VERSION(3, 6), + .intr = &rk3366_vop_intr, +- .common = &rk3288_common, ++ .common = &rk3399_common, + .modeset = &rk3288_modeset, + .output = &rk3399_output, + .misc = &rk3368_misc, + .win = rk3399_vop_lit_win_data, + .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data), + .win_yuv2yuv = rk3399_vop_lit_win_yuv2yuv_data, ++ .lut_size = 256, + }; + + static const struct vop_win_data rk3228_vop_win_data[] = { +diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +index 0b3cd65ba5c1..406e981c75bd 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h ++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +@@ -628,6 +628,7 @@ + #define RK3399_YUV2YUV_WIN 0x02c0 + #define RK3399_YUV2YUV_POST 0x02c4 + #define RK3399_AUTO_GATING_EN 0x02cc ++#define RK3399_DBG_POST_REG1 0x036c + #define RK3399_WIN0_CSC_COE 0x03a0 + #define RK3399_WIN1_CSC_COE 0x03c0 + #define RK3399_WIN2_CSC_COE 0x03e0 + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Hugh Cole-Baker +Date: Tue, 19 Oct 2021 22:58:42 +0100 +Subject: [PATCH] drm/rockchip: support gamma control on RK3399 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The RK3399 has a 1024-entry gamma LUT with 10 bits per component on its +"big" VOP and a 256-entry, 8 bit per component LUT on the "little" VOP. +Compared to the RK3288, it no longer requires disabling gamma while +updating the LUT. On the RK3399, the LUT can be updated at any time as +the hardware has two LUT buffers, one can be written while the other is +in use. A swap of the buffers is triggered by writing 1 to the +update_gamma_lut register. + +Signed-off-by: Hugh Cole-Baker +Tested-by: "Milan P. Stanić" +Tested-by: Linus Heckemann +Signed-off-by: Heiko Stuebner +Link: https://patchwork.freedesktop.org/patch/msgid/20211019215843.42718-3-sigmaris@gmail.com +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 105 +++++++++++++------- + 1 file changed, 71 insertions(+), 34 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index ad3958b6f8bf..d32117633efe 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -68,6 +69,9 @@ + #define VOP_REG_SET(vop, group, name, v) \ + vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name) + ++#define VOP_HAS_REG(vop, group, name) \ ++ (!!(vop->data->group->name.mask)) ++ + #define VOP_INTR_SET_TYPE(vop, name, type, v) \ + do { \ + int i, reg = 0, mask = 0; \ +@@ -1224,17 +1228,22 @@ static bool vop_dsp_lut_is_enabled(struct vop *vop) + return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en); + } + ++static u32 vop_lut_buffer_index(struct vop *vop) ++{ ++ return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index); ++} ++ + static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc) + { + struct drm_color_lut *lut = crtc->state->gamma_lut->data; +- unsigned int i; ++ unsigned int i, bpc = ilog2(vop->data->lut_size); + + for (i = 0; i < crtc->gamma_size; i++) { + u32 word; + +- word = (drm_color_lut_extract(lut[i].red, 10) << 20) | +- (drm_color_lut_extract(lut[i].green, 10) << 10) | +- drm_color_lut_extract(lut[i].blue, 10); ++ word = (drm_color_lut_extract(lut[i].red, bpc) << (2 * bpc)) | ++ (drm_color_lut_extract(lut[i].green, bpc) << bpc) | ++ drm_color_lut_extract(lut[i].blue, bpc); + writel(word, vop->lut_regs + i * 4); + } + } +@@ -1244,38 +1253,66 @@ static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc, + { + struct drm_crtc_state *state = crtc->state; + unsigned int idle; ++ u32 lut_idx, old_idx; + int ret; + + if (!vop->lut_regs) + return; +- /* +- * To disable gamma (gamma_lut is null) or to write +- * an update to the LUT, clear dsp_lut_en. +- */ +- spin_lock(&vop->reg_lock); +- VOP_REG_SET(vop, common, dsp_lut_en, 0); +- vop_cfg_done(vop); +- spin_unlock(&vop->reg_lock); + +- /* +- * In order to write the LUT to the internal memory, +- * we need to first make sure the dsp_lut_en bit is cleared. +- */ +- ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, +- idle, !idle, 5, 30 * 1000); +- if (ret) { +- DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); +- return; +- } ++ if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) { ++ /* ++ * To disable gamma (gamma_lut is null) or to write ++ * an update to the LUT, clear dsp_lut_en. ++ */ ++ spin_lock(&vop->reg_lock); ++ VOP_REG_SET(vop, common, dsp_lut_en, 0); ++ vop_cfg_done(vop); ++ spin_unlock(&vop->reg_lock); + +- if (!state->gamma_lut) +- return; ++ /* ++ * In order to write the LUT to the internal memory, ++ * we need to first make sure the dsp_lut_en bit is cleared. ++ */ ++ ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop, ++ idle, !idle, 5, 30 * 1000); ++ if (ret) { ++ DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n"); ++ return; ++ } ++ ++ if (!state->gamma_lut) ++ return; ++ } else { ++ /* ++ * On RK3399 the gamma LUT can updated without clearing dsp_lut_en, ++ * by setting update_gamma_lut then waiting for lut_buffer_index change ++ */ ++ old_idx = vop_lut_buffer_index(vop); ++ } + + spin_lock(&vop->reg_lock); + vop_crtc_write_gamma_lut(vop, crtc); + VOP_REG_SET(vop, common, dsp_lut_en, 1); ++ VOP_REG_SET(vop, common, update_gamma_lut, 1); + vop_cfg_done(vop); + spin_unlock(&vop->reg_lock); ++ ++ if (VOP_HAS_REG(vop, common, update_gamma_lut)) { ++ ret = readx_poll_timeout(vop_lut_buffer_index, vop, ++ lut_idx, lut_idx != old_idx, 5, 30 * 1000); ++ if (ret) { ++ DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n"); ++ return; ++ } ++ ++ /* ++ * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit ++ * in our backup of the regs. ++ */ ++ spin_lock(&vop->reg_lock); ++ VOP_REG_SET(vop, common, update_gamma_lut, 0); ++ spin_unlock(&vop->reg_lock); ++ } + } + + static void vop_crtc_atomic_begin(struct drm_crtc *crtc, +@@ -1325,14 +1362,6 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, + return; + } + +- /* +- * If we have a GAMMA LUT in the state, then let's make sure +- * it's updated. We might be coming out of suspend, +- * which means the LUT internal memory needs to be re-written. +- */ +- if (crtc->state->gamma_lut) +- vop_crtc_gamma_set(vop, crtc, old_state); +- + mutex_lock(&vop->vop_lock); + + WARN_ON(vop->event); +@@ -1423,6 +1452,14 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, + + VOP_REG_SET(vop, common, standby, 0); + mutex_unlock(&vop->vop_lock); ++ ++ /* ++ * If we have a GAMMA LUT in the state, then let's make sure ++ * it's updated. We might be coming out of suspend, ++ * which means the LUT internal memory needs to be re-written. ++ */ ++ if (crtc->state->gamma_lut) ++ vop_crtc_gamma_set(vop, crtc, old_state); + } + + static bool vop_fs_irq_is_pending(struct vop *vop) +@@ -2148,8 +2185,8 @@ static int vop_bind(struct device *dev, struct device *master, void *data) + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res) { +- if (!vop_data->lut_size) { +- DRM_DEV_ERROR(dev, "no gamma LUT size defined\n"); ++ if (vop_data->lut_size != 1024 && vop_data->lut_size != 256) { ++ DRM_DEV_ERROR(dev, "unsupported gamma LUT size %d\n", vop_data->lut_size); + return -EINVAL; + } + vop->lut_regs = devm_ioremap_resource(dev, res); diff --git a/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch index 5afb775c2a..21da17d29d 100644 --- a/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch @@ -270,10 +270,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c -index 4b70cbfc6d5d..5329f983db15 100644 +index ef53a2578824..d4c53074154a 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c -@@ -1356,6 +1356,14 @@ void mmc_power_off(struct mmc_host *host) +@@ -1358,6 +1358,14 @@ void mmc_power_off(struct mmc_host *host) if (host->ios.power_mode == MMC_POWER_OFF) return; diff --git a/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch index 363d3ef7f3..c64009b7a7 100644 --- a/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch @@ -17,10 +17,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 38 insertions(+), 39 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c -index df34b2a283bc..287488016ff2 100644 +index e0fbe6ba4b6c..cb2f1acab7cf 100644 --- a/drivers/media/v4l2-core/v4l2-common.c +++ b/drivers/media/v4l2-core/v4l2-common.c -@@ -336,6 +336,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf +@@ -338,6 +338,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf return info->block_h[plane]; } @@ -54,7 +54,7 @@ index df34b2a283bc..287488016ff2 100644 void v4l2_apply_frmsize_constraints(u32 *width, u32 *height, const struct v4l2_frmsize_stepwise *frmsize) { -@@ -371,37 +398,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt, +@@ -373,37 +400,19 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt, if (info->mem_planes == 1) { plane = &pixfmt->plane_fmt[0]; @@ -99,7 +99,7 @@ index df34b2a283bc..287488016ff2 100644 } } return 0; -@@ -425,22 +434,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat, +@@ -427,22 +436,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat, pixfmt->width = width; pixfmt->height = height; pixfmt->pixelformat = pixelformat; @@ -154,12 +154,12 @@ Signed-off-by: Jonas Karlman 3 files changed, 8 insertions(+) diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c -index 287488016ff2..01f8a50586eb 100644 +index cb2f1acab7cf..8446a1deffd8 100644 --- a/drivers/media/v4l2-core/v4l2-common.c +++ b/drivers/media/v4l2-core/v4l2-common.c -@@ -267,6 +267,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format) - { .format = V4L2_PIX_FMT_NV24, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 }, +@@ -268,6 +268,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format) { .format = V4L2_PIX_FMT_NV42, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 }, + { .format = V4L2_PIX_FMT_P010, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 }, + { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 2, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } }, + { .format = V4L2_PIX_FMT_NV20, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 1, .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } }, @@ -168,25 +168,25 @@ index 287488016ff2..01f8a50586eb 100644 { .format = V4L2_PIX_FMT_YVU410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 }, { .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 1 }, diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 21470de62d72..cb7496c084f6 100644 +index c314025d977e..298cb762b8d5 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1306,6 +1306,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) - case V4L2_PIX_FMT_NV61: descr = "Y/CrCb 4:2:2"; break; +@@ -1354,6 +1354,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_NV24: descr = "Y/CbCr 4:4:4"; break; case V4L2_PIX_FMT_NV42: descr = "Y/CrCb 4:4:4"; break; + case V4L2_PIX_FMT_P010: descr = "10-bit Y/CbCr 4:2:0"; break; + case V4L2_PIX_FMT_NV15: descr = "10-bit Y/CbCr 4:2:0 (Packed)"; break; + case V4L2_PIX_FMT_NV20: descr = "10-bit Y/CbCr 4:2:2 (Packed)"; break; case V4L2_PIX_FMT_NV12_4L4: descr = "Y/CbCr 4:2:0 (4x4 Linear)"; break; case V4L2_PIX_FMT_NV12_16L16: descr = "Y/CbCr 4:2:0 (16x16 Linear)"; break; case V4L2_PIX_FMT_NV12_32L32: descr = "Y/CbCr 4:2:0 (32x32 Linear)"; break; diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index 343b95107fce..3a5d6290a379 100644 +index 01e630f2ec78..cea44992aea3 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h -@@ -603,6 +603,9 @@ struct v4l2_pix_format { - #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ +@@ -628,6 +628,9 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */ + #define V4L2_PIX_FMT_P010 v4l2_fourcc('P', '0', '1', '0') /* 24 Y/CbCr 4:2:0 10-bit per component */ +#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */ +#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/CbCr 4:2:2 10-bit packed */ @@ -212,10 +212,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 2992fb87cf72..54fc3a6d0902 100644 +index 4af5a831bde0..5590abfaa44d 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -915,9 +915,9 @@ static void config_registers(struct rkvdec_ctx *ctx, +@@ -896,9 +896,9 @@ static void config_registers(struct rkvdec_ctx *ctx, dma_addr_t rlc_addr; dma_addr_t refer_addr; u32 rlc_len; @@ -228,7 +228,7 @@ index 2992fb87cf72..54fc3a6d0902 100644 u32 yuv_virstride = 0; u32 offset; dma_addr_t dst_addr; -@@ -928,8 +928,8 @@ static void config_registers(struct rkvdec_ctx *ctx, +@@ -909,8 +909,8 @@ static void config_registers(struct rkvdec_ctx *ctx, f = &ctx->decoded_fmt; dst_fmt = &f->fmt.pix_mp; @@ -487,10 +487,10 @@ Signed-off-by: Jonas Karlman 2 files changed, 37 insertions(+), 15 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 54fc3a6d0902..af530b05a789 100644 +index 5590abfaa44d..09cab1e53377 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c -@@ -1044,19 +1044,14 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, +@@ -1031,19 +1031,14 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, { unsigned int width, height; @@ -514,7 +514,7 @@ index 54fc3a6d0902..af530b05a789 100644 return -EINVAL; width = (sps->pic_width_in_mbs_minus1 + 1) * 16; -@@ -1077,6 +1072,25 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, +@@ -1064,6 +1059,25 @@ static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, return 0; } @@ -540,7 +540,7 @@ index 54fc3a6d0902..af530b05a789 100644 static int rkvdec_h264_start(struct rkvdec_ctx *ctx) { struct rkvdec_dev *rkvdec = ctx->dev; -@@ -1198,6 +1212,7 @@ static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) +@@ -1185,6 +1199,7 @@ static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = { .adjust_fmt = rkvdec_h264_adjust_fmt, @@ -624,7 +624,7 @@ Signed-off-by: Alex Bee 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index af530b05a789..f31b7c021d82 100644 +index 09cab1e53377..6536c123a243 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -655,13 +655,14 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, diff --git a/projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch index 4b796a94e7..2c8088f906 100644 --- a/projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch @@ -43,7 +43,7 @@ index 07741b678798..5ec38456dc5d 100644 .num_planes = 3, .char_per_block = { 2, 2, 2 }, .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0, diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h -index f1972154a594..b972d0adfa2e 100644 +index 0206f812c569..fa49ee98f275 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -285,6 +285,8 @@ extern "C" { @@ -76,10 +76,10 @@ Reviewed-by: Sandy Huang 3 files changed, 54 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 74562d40f639..9560f82ce880 100644 +index d32117633efe..9e71263ac770 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -274,6 +274,18 @@ static bool has_uv_swapped(uint32_t format) +@@ -280,6 +280,18 @@ static bool has_uv_swapped(uint32_t format) } } @@ -98,7 +98,7 @@ index 74562d40f639..9560f82ce880 100644 static enum vop_data_format vop_convert_format(uint32_t format) { switch (format) { -@@ -289,12 +301,15 @@ static enum vop_data_format vop_convert_format(uint32_t format) +@@ -295,12 +307,15 @@ static enum vop_data_format vop_convert_format(uint32_t format) case DRM_FORMAT_BGR565: return VOP_FMT_RGB565; case DRM_FORMAT_NV12: @@ -114,7 +114,7 @@ index 74562d40f639..9560f82ce880 100644 case DRM_FORMAT_NV42: return VOP_FMT_YUV444SP; default: -@@ -948,7 +963,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -954,7 +969,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane, dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); @@ -128,7 +128,7 @@ index 74562d40f639..9560f82ce880 100644 offset += (src->y1 >> 16) * fb->pitches[0]; dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; -@@ -974,6 +994,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -980,6 +1000,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, } VOP_WIN_SET(vop, win, format, format); @@ -136,7 +136,7 @@ index 74562d40f639..9560f82ce880 100644 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); -@@ -990,7 +1011,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -996,7 +1017,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane, uv_obj = fb->obj[1]; rk_uv_obj = to_rockchip_obj(uv_obj); @@ -150,10 +150,10 @@ index 74562d40f639..9560f82ce880 100644 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index ba88addc1a75..567f226930b2 100644 +index 8502849833d9..b6eea31109d5 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -179,6 +179,7 @@ struct vop_win_phy { +@@ -181,6 +181,7 @@ struct vop_win_phy { struct vop_reg enable; struct vop_reg gate; struct vop_reg format; @@ -162,7 +162,7 @@ index ba88addc1a75..567f226930b2 100644 struct vop_reg uv_swap; struct vop_reg act_info; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index d03dd0402923..3b39b5a5f100 100644 +index 014f99e8928e..16e6aa01e400 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -53,6 +53,23 @@ static const uint32_t formats_win_full[] = { @@ -219,7 +219,7 @@ index d03dd0402923..3b39b5a5f100 100644 .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12), .uv_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 15), .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21), -@@ -906,11 +925,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { +@@ -924,11 +943,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { static const struct vop_win_phy rk3399_win01_data = { .scl = &rk3288_win_full_scl, diff --git a/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch b/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch index 0e9ec6c13c..74e3c96fbd 100644 --- a/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch +++ b/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch @@ -13,12 +13,12 @@ Signed-off-by: Jonas Karlman 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 9560f82ce880..c3fea637974f 100644 +index 9e71263ac770..dbe4d411b30f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1595,7 +1595,11 @@ static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) - { - struct rockchip_crtc_state *rockchip_state; +@@ -1637,7 +1637,11 @@ static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) + if (WARN_ON(!crtc->state)) + return NULL; - rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); + if (WARN_ON(!crtc->state)) @@ -47,10 +47,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 54 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index c3fea637974f..e736c735ec38 100644 +index dbe4d411b30f..8711d810b48a 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1200,6 +1200,59 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc) +@@ -1206,6 +1206,59 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc) spin_unlock_irqrestore(&vop->irq_lock, flags); } @@ -110,7 +110,7 @@ index c3fea637974f..e736c735ec38 100644 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) -@@ -1578,6 +1631,7 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, +@@ -1617,6 +1670,7 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, } static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { @@ -133,10 +133,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index e736c735ec38..2b765ec02a6e 100644 +index 8711d810b48a..ec6983494f05 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1238,6 +1238,9 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, +@@ -1244,6 +1244,9 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, if (!vop_crtc_is_tmds(crtc)) return MODE_OK; @@ -160,10 +160,10 @@ Signed-off-by: Jonas Karlman 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index 567f226930b2..8db9ea4055f6 100644 +index b6eea31109d5..ca4e2b7415fe 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -212,6 +212,11 @@ struct vop_win_data { +@@ -214,6 +214,11 @@ struct vop_win_data { enum drm_plane_type type; }; @@ -175,7 +175,7 @@ index 567f226930b2..8db9ea4055f6 100644 struct vop_data { uint32_t version; const struct vop_intr *intr; -@@ -224,6 +229,7 @@ struct vop_data { +@@ -226,6 +231,7 @@ struct vop_data { const struct vop_win_data *win; unsigned int win_size; unsigned int lut_size; @@ -200,7 +200,7 @@ index c727093a06d6..f1234a151130 100644 VOP2_SCALE_UP_NRST_NBOR, VOP2_SCALE_UP_BIL, diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 3b39b5a5f100..0a9b64a62483 100644 +index 16e6aa01e400..9b25b8ffd0ce 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -743,6 +743,7 @@ static const struct vop_intr rk3288_vop_intr = { @@ -227,23 +227,23 @@ index 3b39b5a5f100..0a9b64a62483 100644 .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -976,6 +979,7 @@ static const struct vop_afbc rk3399_vop_afbc = { +@@ -994,6 +997,7 @@ static const struct vop_afbc rk3399_vop_afbc = { static const struct vop_data rk3399_vop_big = { .version = VOP_VERSION(3, 5), .feature = VOP_FEATURE_OUTPUT_RGB10, + .max_output = { 4096, 2160 }, .intr = &rk3366_vop_intr, - .common = &rk3288_common, + .common = &rk3399_common, .modeset = &rk3288_modeset, -@@ -1002,6 +1006,7 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { +@@ -1021,6 +1025,7 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { static const struct vop_data rk3399_vop_lit = { .version = VOP_VERSION(3, 6), + .max_output = { 2560, 1600 }, .intr = &rk3366_vop_intr, - .common = &rk3288_common, + .common = &rk3399_common, .modeset = &rk3288_modeset, -@@ -1022,6 +1027,7 @@ static const struct vop_win_data rk3228_vop_win_data[] = { +@@ -1042,6 +1047,7 @@ static const struct vop_win_data rk3228_vop_win_data[] = { static const struct vop_data rk3228_vop = { .version = VOP_VERSION(3, 7), .feature = VOP_FEATURE_OUTPUT_RGB10, @@ -251,7 +251,7 @@ index 3b39b5a5f100..0a9b64a62483 100644 .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -1093,6 +1099,7 @@ static const struct vop_win_data rk3328_vop_win_data[] = { +@@ -1113,6 +1119,7 @@ static const struct vop_win_data rk3328_vop_win_data[] = { static const struct vop_data rk3328_vop = { .version = VOP_VERSION(3, 8), .feature = VOP_FEATURE_OUTPUT_RGB10, @@ -273,10 +273,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 2b765ec02a6e..92caec48ccd8 100644 +index ec6983494f05..a1a470a91169 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1232,6 +1232,7 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, +@@ -1238,6 +1238,7 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) { struct vop *vop = to_vop(crtc); @@ -284,7 +284,7 @@ index 2b765ec02a6e..92caec48ccd8 100644 long rounded_rate; long lowest, highest; -@@ -1253,6 +1254,10 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, +@@ -1259,6 +1260,10 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, if (rounded_rate > highest) return MODE_CLOCK_HIGH; @@ -295,7 +295,7 @@ index 2b765ec02a6e..92caec48ccd8 100644 return MODE_OK; } -@@ -1261,8 +1266,19 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, +@@ -1267,8 +1272,19 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *adjusted_mode) { struct vop *vop = to_vop(crtc); @@ -843,7 +843,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 0a9b64a62483..6446f2158d30 100644 +index 9b25b8ffd0ce..a2b281e290e0 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -740,7 +740,7 @@ static const struct vop_intr rk3288_vop_intr = { @@ -875,7 +875,7 @@ index 0a9b64a62483..6446f2158d30 100644 static const int rk3368_vop_intrs[] = { FS_INTR, 0, 0, -@@ -1122,8 +1135,10 @@ static const struct of_device_id vop_driver_dt_match[] = { +@@ -1142,8 +1155,10 @@ static const struct of_device_id vop_driver_dt_match[] = { .data = &rk3066_vop }, { .compatible = "rockchip,rk3188-vop", .data = &rk3188_vop }, @@ -936,10 +936,10 @@ Signed-off-by: Jonas Karlman 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 3e1be9894ed1..170d291448df 100644 +index 25a60eb4d67c..64792b597833 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -137,7 +137,8 @@ struct dw_hdmi_phy_data { +@@ -138,7 +138,8 @@ struct dw_hdmi_phy_data { bool has_svsret; int (*configure)(struct dw_hdmi *hdmi, const struct dw_hdmi_plat_data *pdata, @@ -949,7 +949,7 @@ index 3e1be9894ed1..170d291448df 100644 }; struct dw_hdmi { -@@ -1584,7 +1585,8 @@ static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) +@@ -1585,7 +1586,8 @@ static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) */ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, const struct dw_hdmi_plat_data *pdata, @@ -959,7 +959,7 @@ index 3e1be9894ed1..170d291448df 100644 { const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; -@@ -1659,9 +1661,9 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, +@@ -1660,9 +1662,9 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, /* Write to the PHY as configured by the platform */ if (pdata->configure_phy) @@ -1013,10 +1013,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 170d291448df..507b7bf4c7fd 100644 +index 64792b597833..02b954e92180 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1591,6 +1591,7 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, +@@ -1592,6 +1592,7 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; @@ -1024,7 +1024,7 @@ index 170d291448df..507b7bf4c7fd 100644 /* TOFIX Will need 420 specific PHY configuration tables */ -@@ -1600,11 +1601,11 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, +@@ -1601,11 +1602,11 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, break; for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) @@ -1038,7 +1038,7 @@ index 170d291448df..507b7bf4c7fd 100644 break; if (mpll_config->mpixelclock == ~0UL || -@@ -1612,11 +1613,17 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, +@@ -1613,11 +1614,17 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, phy_config->mpixelclock == ~0UL) return -EINVAL; @@ -1072,10 +1072,10 @@ Signed-off-by: Jonas Karlman 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 507b7bf4c7fd..2eb0f3cf1516 100644 +index 02b954e92180..6345c0759473 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1593,7 +1593,9 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, +@@ -1594,7 +1594,9 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; int depth; @@ -1295,14 +1295,22 @@ atomic_get_input_bus_fmts and support for 8-bit RGB 4:4:4. Signed-off-by: Jonas Karlman --- - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 117 +++++++++++++------- - 1 file changed, 80 insertions(+), 37 deletions(-) + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 118 ++++++++++++++------ + 1 file changed, 81 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index cb8b2135ddf0..da4a829baded 100644 +index cb8b2135ddf0..4d64305e409b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -72,6 +72,7 @@ struct rockchip_hdmi_chip_data { +@@ -5,6 +5,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -72,6 +73,7 @@ struct rockchip_hdmi_chip_data { struct rockchip_hdmi { struct device *dev; struct regmap *regmap; @@ -1310,7 +1318,7 @@ index cb8b2135ddf0..da4a829baded 100644 struct rockchip_encoder encoder; const struct rockchip_hdmi_chip_data *chip_data; struct clk *ref_clk; -@@ -82,11 +83,9 @@ struct rockchip_hdmi { +@@ -82,11 +84,9 @@ struct rockchip_hdmi { struct phy *phy; }; @@ -1324,7 +1332,7 @@ index cb8b2135ddf0..da4a829baded 100644 } static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { -@@ -335,31 +334,21 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, +@@ -335,31 +335,21 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, return drm_mode_validate_size(mode, 3840, 2160); } @@ -1365,7 +1373,7 @@ index cb8b2135ddf0..da4a829baded 100644 u32 val; int ret; -@@ -387,10 +376,21 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) +@@ -387,10 +377,21 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) ret ? "LIT" : "BIG"); } @@ -1390,7 +1398,7 @@ index cb8b2135ddf0..da4a829baded 100644 { struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); -@@ -400,12 +400,38 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, +@@ -400,12 +401,38 @@ dw_hdmi_rockchip_encoder_atomic_check(struct drm_encoder *encoder, return 0; } @@ -1435,7 +1443,7 @@ index cb8b2135ddf0..da4a829baded 100644 }; static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, -@@ -602,6 +628,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, +@@ -602,6 +629,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, struct dw_hdmi_plat_data *plat_data; const struct of_device_id *match; struct drm_device *drm = data; @@ -1443,7 +1451,7 @@ index cb8b2135ddf0..da4a829baded 100644 struct drm_encoder *encoder; struct rockchip_hdmi *hdmi; int ret; -@@ -679,20 +706,21 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, +@@ -679,20 +707,21 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, RK3568_HDMI_SCLIN_MSK)); } @@ -1469,7 +1477,7 @@ index cb8b2135ddf0..da4a829baded 100644 * which would have called the encoder cleanup. Do it manually. */ if (IS_ERR(hdmi->hdmi)) { -@@ -700,8 +728,23 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, +@@ -700,8 +729,23 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, goto err_bind; } @@ -1493,7 +1501,7 @@ index cb8b2135ddf0..da4a829baded 100644 err_bind: drm_encoder_cleanup(encoder); err_disable_clk: -@@ -719,7 +762,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, +@@ -719,7 +763,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, { struct rockchip_hdmi *hdmi = dev_get_drvdata(dev); @@ -1503,78 +1511,6 @@ index cb8b2135ddf0..da4a829baded 100644 regulator_disable(hdmi->avdd_1v8); -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Fri, 9 Oct 2020 15:24:53 +0000 -Subject: [PATCH] drm/rockchip: vop: create planes in window order - -Signed-off-by: Jonas Karlman ---- - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 36 +++------------------ - 1 file changed, 4 insertions(+), 32 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 92caec48ccd8..3e2a0ce1a137 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1894,19 +1894,10 @@ static int vop_create_crtc(struct vop *vop) - int ret; - int i; - -- /* -- * Create drm_plane for primary and cursor planes first, since we need -- * to pass them to drm_crtc_init_with_planes, which sets the -- * "possible_crtcs" to the newly initialized crtc. -- */ - for (i = 0; i < vop_data->win_size; i++) { - struct vop_win *vop_win = &vop->win[i]; - const struct vop_win_data *win_data = vop_win->data; - -- if (win_data->type != DRM_PLANE_TYPE_PRIMARY && -- win_data->type != DRM_PLANE_TYPE_CURSOR) -- continue; -- - ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, - 0, &vop_plane_funcs, - win_data->phy->data_formats, -@@ -1939,32 +1930,13 @@ static int vop_create_crtc(struct vop *vop) - drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); - } - -- /* -- * Create drm_planes for overlay windows with possible_crtcs restricted -- * to the newly created crtc. -- */ -+ /* Set possible_crtcs to the newly created crtc for overlay windows */ - for (i = 0; i < vop_data->win_size; i++) { - struct vop_win *vop_win = &vop->win[i]; -- const struct vop_win_data *win_data = vop_win->data; -- unsigned long possible_crtcs = drm_crtc_mask(crtc); -- -- if (win_data->type != DRM_PLANE_TYPE_OVERLAY) -- continue; - -- ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, -- possible_crtcs, -- &vop_plane_funcs, -- win_data->phy->data_formats, -- win_data->phy->nformats, -- win_data->phy->format_modifiers, -- win_data->type, NULL); -- if (ret) { -- DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", -- ret); -- goto err_cleanup_crtc; -- } -- drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); -- vop_plane_add_properties(&vop_win->base, win_data); -+ plane = &vop_win->base; -+ if (plane->type == DRM_PLANE_TYPE_OVERLAY) -+ plane->possible_crtcs = drm_crtc_mask(crtc); - } - - port = of_get_child_by_name(dev->of_node, "port"); - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 9 Oct 2020 15:29:27 +0000 @@ -1587,10 +1523,10 @@ Signed-off-by: Jonas Karlman 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c -index 0d2cb4f3922b..e46965d16dd0 100644 +index 092bf863110b..e2ee0d6a8d55 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c -@@ -132,6 +132,8 @@ void rockchip_drm_mode_config_init(struct drm_device *dev) +@@ -133,6 +133,8 @@ void rockchip_drm_mode_config_init(struct drm_device *dev) dev->mode_config.max_width = 4096; dev->mode_config.max_height = 4096; @@ -1600,10 +1536,10 @@ index 0d2cb4f3922b..e46965d16dd0 100644 dev->mode_config.helper_private = &rockchip_mode_config_helpers; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 3e2a0ce1a137..3c1c415b039e 100644 +index a1a470a91169..2792c7d27bec 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1871,7 +1871,7 @@ static irqreturn_t vop_isr(int irq, void *data) +@@ -1913,7 +1913,7 @@ static irqreturn_t vop_isr(int irq, void *data) return ret; } @@ -1612,7 +1548,7 @@ index 3e2a0ce1a137..3c1c415b039e 100644 const struct vop_win_data *win_data) { unsigned int flags = 0; -@@ -1881,6 +1881,8 @@ static void vop_plane_add_properties(struct drm_plane *plane, +@@ -1923,6 +1923,8 @@ static void vop_plane_add_properties(struct drm_plane *plane, if (flags) drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, DRM_MODE_ROTATE_0 | flags); @@ -1621,7 +1557,7 @@ index 3e2a0ce1a137..3c1c415b039e 100644 } static int vop_create_crtc(struct vop *vop) -@@ -1912,7 +1914,7 @@ static int vop_create_crtc(struct vop *vop) +@@ -1963,7 +1965,7 @@ static int vop_create_crtc(struct vop *vop) plane = &vop_win->base; drm_plane_helper_add(plane, &plane_helper_funcs); @@ -1642,10 +1578,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 3c1c415b039e..1df221b7007d 100644 +index 2792c7d27bec..1529d5fbc7c7 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1871,8 +1871,23 @@ static irqreturn_t vop_isr(int irq, void *data) +@@ -1913,8 +1913,23 @@ static irqreturn_t vop_isr(int irq, void *data) return ret; } @@ -1670,7 +1606,7 @@ index 3c1c415b039e..1df221b7007d 100644 { unsigned int flags = 0; -@@ -1883,6 +1898,19 @@ static void vop_plane_add_properties(struct drm_plane *plane, int zpos, +@@ -1925,6 +1940,19 @@ static void vop_plane_add_properties(struct drm_plane *plane, int zpos, DRM_MODE_ROTATE_0 | flags); drm_plane_create_zpos_immutable_property(plane, zpos); @@ -1690,7 +1626,7 @@ index 3c1c415b039e..1df221b7007d 100644 } static int vop_create_crtc(struct vop *vop) -@@ -1914,7 +1942,7 @@ static int vop_create_crtc(struct vop *vop) +@@ -1965,7 +1993,7 @@ static int vop_create_crtc(struct vop *vop) plane = &vop_win->base; drm_plane_helper_add(plane, &plane_helper_funcs); @@ -1987,10 +1923,10 @@ index d1ae42757242..7b2cde230b87 100644 }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index fbd0346624e6..b0620c45820c 100644 +index 92c2207e686c..980b12cb0a49 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1725,11 +1725,6 @@ vopl_out_edp: endpoint@1 { +@@ -1728,11 +1728,6 @@ vopl_out_edp: endpoint@1 { remote-endpoint = <&edp_in_vopl>; }; @@ -2002,7 +1938,7 @@ index fbd0346624e6..b0620c45820c 100644 vopl_out_mipi1: endpoint@3 { reg = <3>; remote-endpoint = <&mipi1_in_vopl>; -@@ -1923,10 +1918,6 @@ hdmi_in_vopb: endpoint@0 { +@@ -1926,10 +1921,6 @@ hdmi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_hdmi>; }; @@ -2025,10 +1961,10 @@ Subject: [PATCH] WIP: drm/bridge: dw-hdmi: limit mode and bus format to 1 file changed, 76 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 2eb0f3cf1516..3b0ce3f22d3e 100644 +index 6345c0759473..9a16cedc9fd2 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -2002,6 +2002,21 @@ static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, +@@ -2003,6 +2003,21 @@ static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); } @@ -2050,7 +1986,7 @@ index 2eb0f3cf1516..3b0ce3f22d3e 100644 static void hdmi_av_composer(struct dw_hdmi *hdmi, const struct drm_display_info *display, const struct drm_display_mode *mode) -@@ -2013,29 +2028,11 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, +@@ -2014,29 +2029,11 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, unsigned int vdisplay, hdisplay; vmode->mpixelclock = mode->clock * 1000; @@ -2083,7 +2019,7 @@ index 2eb0f3cf1516..3b0ce3f22d3e 100644 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock); /* Set up HDMI_FC_INVIDCONF */ -@@ -2662,8 +2659,21 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) +@@ -2663,8 +2660,21 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) * - MEDIA_BUS_FMT_RGB888_1X24, */ @@ -2107,7 +2043,7 @@ index 2eb0f3cf1516..3b0ce3f22d3e 100644 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, -@@ -2675,8 +2685,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2676,8 +2686,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, struct drm_display_info *info = &conn->display_info; struct drm_display_mode *mode = &crtc_state->mode; u8 max_bpc = conn_state->max_requested_bpc; @@ -2116,7 +2052,7 @@ index 2eb0f3cf1516..3b0ce3f22d3e 100644 u32 *output_fmts; unsigned int i = 0; -@@ -2700,29 +2708,33 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2701,29 +2709,33 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, * If the current mode enforces 4:2:0, force the output but format * to 4:2:0 and do not add the YUV422/444/RGB formats */ @@ -2158,7 +2094,7 @@ index 2eb0f3cf1516..3b0ce3f22d3e 100644 } /* -@@ -2731,40 +2743,51 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2732,40 +2744,51 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, */ if (max_bpc >= 16 && info->bpc == 16) { @@ -2221,7 +2157,7 @@ index 2eb0f3cf1516..3b0ce3f22d3e 100644 *num_output_fmts = i; -@@ -2945,11 +2968,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, +@@ -2946,11 +2969,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, struct dw_hdmi *hdmi = bridge->driver_private; const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; enum drm_mode_status mode_status = MODE_OK; @@ -2254,10 +2190,10 @@ Subject: [PATCH] WIP: drm/rockchip: dw_hdmi: add 10-bit rgb bus format 2 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index da4a829baded..66e463d58a0b 100644 +index 4d64305e409b..9068c953b843 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -83,6 +83,8 @@ struct rockchip_hdmi { +@@ -84,6 +84,8 @@ struct rockchip_hdmi { struct phy *phy; }; @@ -2266,7 +2202,7 @@ index da4a829baded..66e463d58a0b 100644 static struct rockchip_hdmi *to_rockchip_hdmi(struct drm_bridge *bridge) { return container_of(bridge, struct rockchip_hdmi, bridge); -@@ -340,6 +342,11 @@ dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, +@@ -341,6 +343,11 @@ dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, const struct drm_display_mode *adjusted_mode) { struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); @@ -2278,7 +2214,7 @@ index da4a829baded..66e463d58a0b 100644 clk_set_rate(hdmi->ref_clk, adjusted_mode->clock * 1000); } -@@ -380,6 +387,17 @@ static bool is_rgb(u32 format) +@@ -381,6 +388,17 @@ static bool is_rgb(u32 format) { switch (format) { case MEDIA_BUS_FMT_RGB888_1X24: @@ -2296,7 +2232,7 @@ index da4a829baded..66e463d58a0b 100644 return true; default: return false; -@@ -393,9 +411,24 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, +@@ -394,9 +412,24 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, struct drm_connector_state *conn_state) { struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); @@ -2321,7 +2257,7 @@ index da4a829baded..66e463d58a0b 100644 return 0; } -@@ -407,10 +440,19 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, +@@ -408,10 +441,19 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, u32 output_fmt, unsigned int *num_input_fmts) { @@ -2365,10 +2301,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 3b0ce3f22d3e..cd806742c010 100644 +index 9a16cedc9fd2..039923902d5f 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1789,6 +1789,7 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, +@@ -1790,6 +1790,7 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, const struct drm_connector *connector, const struct drm_display_mode *mode) { @@ -2376,7 +2312,7 @@ index 3b0ce3f22d3e..cd806742c010 100644 struct hdmi_avi_infoframe frame; u8 val; -@@ -1846,6 +1847,8 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, +@@ -1847,6 +1848,8 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; } @@ -2385,7 +2321,7 @@ index 3b0ce3f22d3e..cd806742c010 100644 /* * The Designware IP uses a different byte format from standard * AVI info frames, though generally the bits are in the correct -@@ -2550,7 +2553,8 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, +@@ -2551,7 +2554,8 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, if (!crtc) return 0; @@ -2395,7 +2331,7 @@ index 3b0ce3f22d3e..cd806742c010 100644 crtc_state = drm_atomic_get_crtc_state(state, crtc); if (IS_ERR(crtc_state)) return PTR_ERR(crtc_state); -@@ -2618,6 +2622,8 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) +@@ -2619,6 +2623,8 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) drm_connector_attach_max_bpc_property(connector, 8, 16); @@ -2418,10 +2354,10 @@ Subject: [PATCH] WIP: drm/rockchip: add yuv444 support 4 files changed, 77 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 66e463d58a0b..4fad844a18af 100644 +index 9068c953b843..e5b827253f47 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -67,6 +67,7 @@ struct rockchip_hdmi_chip_data { +@@ -68,6 +68,7 @@ struct rockchip_hdmi_chip_data { int lcdsel_grf_reg; u32 lcdsel_big; u32 lcdsel_lit; @@ -2429,7 +2365,7 @@ index 66e463d58a0b..4fad844a18af 100644 }; struct rockchip_hdmi { -@@ -394,10 +395,22 @@ static bool is_rgb(u32 format) +@@ -395,10 +396,22 @@ static bool is_rgb(u32 format) } } @@ -2452,7 +2388,7 @@ index 66e463d58a0b..4fad844a18af 100644 return true; default: return false; -@@ -414,12 +427,22 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, +@@ -415,12 +428,22 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, struct drm_atomic_state *state = bridge_state->base.state; struct drm_crtc_state *old_crtc_state; struct rockchip_crtc_state *old_state; @@ -2475,7 +2411,7 @@ index 66e463d58a0b..4fad844a18af 100644 s->bus_width = is_10bit(format) ? 10 : 8; old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc); -@@ -453,7 +476,10 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, +@@ -454,7 +477,10 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, if (!has_10bit && is_10bit(output_fmt)) return NULL; @@ -2487,7 +2423,7 @@ index 66e463d58a0b..4fad844a18af 100644 return NULL; input_fmt = kzalloc(sizeof(*input_fmt), GFP_KERNEL); -@@ -603,6 +629,7 @@ static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = { +@@ -604,6 +630,7 @@ static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = { static struct rockchip_hdmi_chip_data rk3328_chip_data = { .lcdsel_grf_reg = -1, @@ -2496,10 +2432,10 @@ index 66e463d58a0b..4fad844a18af 100644 static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 1df221b7007d..ac3802c3be21 100644 +index 1529d5fbc7c7..8a9875bf7977 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -341,6 +341,17 @@ static int vop_convert_afbc_format(uint32_t format) +@@ -347,6 +347,17 @@ static int vop_convert_afbc_format(uint32_t format) return -EINVAL; } @@ -2517,7 +2453,7 @@ index 1df221b7007d..ac3802c3be21 100644 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, uint32_t dst, bool is_horizontal, int vsu_mode, int *vskiplines) -@@ -1412,6 +1423,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1451,6 +1462,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, u16 vact_end = vact_st + vdisplay; uint32_t pin_pol, val; int dither_bpc = s->output_bpc ? s->output_bpc : 10; @@ -2525,7 +2461,7 @@ index 1df221b7007d..ac3802c3be21 100644 int ret; if (old_state && old_state->self_refresh_active) { -@@ -1485,6 +1497,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1516,6 +1528,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) s->output_mode = ROCKCHIP_OUT_MODE_P888; @@ -2534,7 +2470,7 @@ index 1df221b7007d..ac3802c3be21 100644 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) VOP_REG_SET(vop, common, pre_dither_down, 1); else -@@ -1500,6 +1514,21 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1531,6 +1545,21 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, VOP_REG_SET(vop, common, out_mode, s->output_mode); @@ -2557,10 +2493,10 @@ index 1df221b7007d..ac3802c3be21 100644 val = hact_st << 16; val |= hact_end; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index 8db9ea4055f6..e9f256bd8d5a 100644 +index ca4e2b7415fe..47ad74ef1afb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -117,10 +117,16 @@ struct vop_common { +@@ -119,10 +119,16 @@ struct vop_common { struct vop_reg mmu_en; struct vop_reg out_mode; struct vop_reg standby; @@ -2578,7 +2514,7 @@ index 8db9ea4055f6..e9f256bd8d5a 100644 struct vop_intr { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 6446f2158d30..7c4c3e299760 100644 +index a2b281e290e0..a8a3e9d13fe5 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -705,6 +705,11 @@ static const struct vop_common rk3288_common = { @@ -2593,7 +2529,7 @@ index 6446f2158d30..7c4c3e299760 100644 }; /* -@@ -1076,6 +1081,10 @@ static const struct vop_output rk3328_output = { +@@ -1096,6 +1101,10 @@ static const struct vop_output rk3328_output = { static const struct vop_misc rk3328_misc = { .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), @@ -2604,7 +2540,7 @@ index 6446f2158d30..7c4c3e299760 100644 }; static const struct vop_common rk3328_common = { -@@ -1088,6 +1097,11 @@ static const struct vop_common rk3328_common = { +@@ -1108,6 +1117,11 @@ static const struct vop_common rk3328_common = { .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), @@ -2624,16 +2560,16 @@ Subject: [PATCH] WIP: drm/rockchip: add yuv420 support --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 22 +++++++++++++++++++++ - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 18 ++++++++++++++++- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 19 +++++++++++++++++- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 10 ++++++---- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 2 ++ - 4 files changed, 47 insertions(+), 5 deletions(-) + 4 files changed, 48 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 4fad844a18af..d57e953ce585 100644 +index e5b827253f47..9bdf6211f15c 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -406,9 +406,21 @@ static bool is_yuv444(u32 format) +@@ -407,9 +407,21 @@ static bool is_yuv444(u32 format) } } @@ -2655,7 +2591,7 @@ index 4fad844a18af..d57e953ce585 100644 case MEDIA_BUS_FMT_RGB101010_1X30: case MEDIA_BUS_FMT_YUV10_1X30: return true; -@@ -445,6 +457,11 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, +@@ -446,6 +458,11 @@ dw_hdmi_rockchip_bridge_atomic_check(struct drm_bridge *bridge, s->bus_width = is_10bit(format) ? 10 : 8; @@ -2667,7 +2603,7 @@ index 4fad844a18af..d57e953ce585 100644 old_crtc_state = drm_atomic_get_old_crtc_state(state, conn_state->crtc); if (old_crtc_state && !crtc_state->mode_changed) { old_state = to_rockchip_crtc_state(old_crtc_state); -@@ -465,6 +482,7 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, +@@ -466,6 +483,7 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, { struct rockchip_hdmi *hdmi = to_rockchip_hdmi(bridge); struct drm_encoder *encoder = bridge->encoder; @@ -2675,7 +2611,7 @@ index 4fad844a18af..d57e953ce585 100644 u32 *input_fmt; bool has_10bit = true; -@@ -479,6 +497,9 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, +@@ -480,6 +498,9 @@ static u32 *dw_hdmi_rockchip_get_input_bus_fmts(struct drm_bridge *bridge, if (is_yuv444(output_fmt)) { if (!hdmi->chip_data->ycbcr_444_allowed) return NULL; @@ -2685,7 +2621,7 @@ index 4fad844a18af..d57e953ce585 100644 } else if (!is_rgb(output_fmt)) return NULL; -@@ -639,6 +660,7 @@ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { +@@ -640,6 +661,7 @@ static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { .phy_name = "inno_dw_hdmi_phy2", .phy_force_vendor = true, .use_drm_infoframe = true, @@ -2694,10 +2630,18 @@ index 4fad844a18af..d57e953ce585 100644 static struct rockchip_hdmi_chip_data rk3399_chip_data = { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index ac3802c3be21..04a135730b12 100644 +index 8a9875bf7977..154e08e7e47a 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -342,6 +342,19 @@ static int vop_convert_afbc_format(uint32_t format) +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -348,6 +349,19 @@ static int vop_convert_afbc_format(uint32_t format) } static bool is_yuv_output(uint32_t bus_format) @@ -2717,7 +2661,7 @@ index ac3802c3be21..04a135730b12 100644 { switch (bus_format) { case MEDIA_BUS_FMT_YUV8_1X24: -@@ -1497,7 +1510,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1528,7 +1542,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) s->output_mode = ROCKCHIP_OUT_MODE_P888; @@ -2726,7 +2670,7 @@ index ac3802c3be21..04a135730b12 100644 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) VOP_REG_SET(vop, common, pre_dither_down, 1); -@@ -1514,6 +1527,9 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1545,6 +1559,9 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, VOP_REG_SET(vop, common, out_mode, s->output_mode); @@ -2737,10 +2681,10 @@ index ac3802c3be21..04a135730b12 100644 VOP_REG_SET(vop, common, dsp_out_yuv, yuv_output); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -index e9f256bd8d5a..c5c8d3887081 100644 +index 47ad74ef1afb..94a615dca672 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h -@@ -119,6 +119,7 @@ struct vop_common { +@@ -121,6 +121,7 @@ struct vop_common { struct vop_reg standby; struct vop_reg overlay_mode; @@ -2748,7 +2692,7 @@ index e9f256bd8d5a..c5c8d3887081 100644 struct vop_reg dsp_data_swap; struct vop_reg dsp_out_yuv; struct vop_reg dsp_background; -@@ -284,11 +285,12 @@ struct vop_data { +@@ -286,11 +287,12 @@ struct vop_data { /* * display output interface supported by rockchip lcdc */ @@ -2766,7 +2710,7 @@ index e9f256bd8d5a..c5c8d3887081 100644 /* output flags */ #define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 7c4c3e299760..1aecdcf63da9 100644 +index a8a3e9d13fe5..50c157ff366b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -707,6 +707,7 @@ static const struct vop_common rk3288_common = { @@ -2777,7 +2721,7 @@ index 7c4c3e299760..1aecdcf63da9 100644 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2), .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), -@@ -1099,6 +1100,7 @@ static const struct vop_common rk3328_common = { +@@ -1119,6 +1120,7 @@ static const struct vop_common rk3328_common = { .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), @@ -2797,10 +2741,10 @@ Subject: [PATCH] drm/rockchip: enable ycbcr_420_allowed and ycbcr_444_allowed 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index d57e953ce585..42457f7d9bc9 100644 +index 9bdf6211f15c..688c99e07c69 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -615,6 +615,7 @@ static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = { +@@ -616,6 +616,7 @@ static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = { static struct rockchip_hdmi_chip_data rk3228_chip_data = { .lcdsel_grf_reg = -1, @@ -2808,7 +2752,7 @@ index d57e953ce585..42457f7d9bc9 100644 }; static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { -@@ -623,6 +624,7 @@ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { +@@ -624,6 +625,7 @@ static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { .phy_ops = &rk3228_hdmi_phy_ops, .phy_name = "inno_dw_hdmi_phy2", .phy_force_vendor = true, @@ -2832,10 +2776,10 @@ Signed-off-by: Alex Bee 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 42457f7d9bc9..90cc3b33e2a0 100644 +index 688c99e07c69..c720d1ce48a4 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -325,16 +325,30 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, +@@ -326,16 +326,30 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, const struct drm_display_mode *mode) { struct dw_hdmi_plat_data *pdata = (struct dw_hdmi_plat_data *)data; @@ -2880,7 +2824,7 @@ Subject: [PATCH] !fixup drm/rockchip: rk3368's vop does not support 10-bit 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 1aecdcf63da9..870e388c2345 100644 +index 50c157ff366b..e33c499d3041 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -794,8 +794,8 @@ static const struct vop_intr rk3368_vop_intr = { @@ -2906,10 +2850,10 @@ Signed-off-by: Alex Bee 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 870e388c2345..4ba8f79582db 100644 +index e33c499d3041..cc235baa9d50 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -1116,12 +1116,36 @@ static const struct vop_intr rk3328_vop_intr = { +@@ -1136,12 +1136,36 @@ static const struct vop_intr rk3328_vop_intr = { .clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0), }; @@ -2960,10 +2904,10 @@ Subject: [PATCH] rockchip: vop: force skip lines if image too big 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 04a135730b12..96a301501584 100644 +index 154e08e7e47a..c0f136bf74db 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -958,6 +958,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -965,6 +965,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, int format; int is_yuv = fb->format->is_yuv; int i; @@ -2971,7 +2915,7 @@ index 04a135730b12..96a301501584 100644 /* * can't update plane when vop is disabled. -@@ -976,8 +977,14 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -983,8 +984,14 @@ static void vop_plane_atomic_update(struct drm_plane *plane, obj = fb->obj[0]; rk_obj = to_rockchip_obj(obj); @@ -2987,7 +2931,7 @@ index 04a135730b12..96a301501584 100644 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); dsp_info = (drm_rect_height(dest) - 1) << 16; -@@ -1019,7 +1026,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -1026,7 +1033,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, VOP_WIN_SET(vop, win, format, format); VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format)); @@ -2996,7 +2940,7 @@ index 04a135730b12..96a301501584 100644 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); VOP_WIN_SET(vop, win, y_mir_en, -@@ -1043,7 +1050,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -1050,7 +1057,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, offset += (src->y1 >> 16) * fb->pitches[1] / vsub; dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; @@ -3091,10 +3035,10 @@ Signed-off-by: Alex Bee 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index cd806742c010..772cc629c35d 100644 +index 039923902d5f..20fc0981ef18 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -81,15 +81,15 @@ static const u16 csc_coeff_rgb_out_eitu709[3][4] = { +@@ -82,15 +82,15 @@ static const u16 csc_coeff_rgb_out_eitu709[3][4] = { }; static const u16 csc_coeff_rgb_in_eitu601[3][4] = { @@ -3451,10 +3395,10 @@ Signed-off-by: Algea Cao 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 772cc629c35d..428e057dd415 100644 +index 20fc0981ef18..3082387aa53e 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -1178,7 +1178,7 @@ static void hdmi_video_csc(struct dw_hdmi *hdmi) +@@ -1179,7 +1179,7 @@ static void hdmi_video_csc(struct dw_hdmi *hdmi) if (is_color_space_interpolation(hdmi)) interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; else if (is_color_space_decimation(hdmi)) @@ -3481,10 +3425,10 @@ Signed-off-by: Alex Bee 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 90cc3b33e2a0..3c0796c5743d 100644 +index c720d1ce48a4..1062afa26c56 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -@@ -349,7 +349,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, +@@ -350,7 +350,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, return MODE_CLOCK_HIGH; } @@ -3494,10 +3438,10 @@ index 90cc3b33e2a0..3c0796c5743d 100644 static void dw_hdmi_rockchip_bridge_mode_set(struct drm_bridge *bridge, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 96a301501584..a89f96ab3974 100644 +index c0f136bf74db..140f52fe2348 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -417,8 +417,8 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, +@@ -424,8 +424,8 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, if (info->is_yuv) is_yuv = true; @@ -3568,10 +3512,10 @@ Signed-off-by: Jonas Karlman 4 files changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/media/cec/core/cec-adap.c b/drivers/media/cec/core/cec-adap.c -index 8bf91b5a7d0e..ad8a2e5a31ac 100644 +index 41a79293ee02..542ab1425339 100644 --- a/drivers/media/cec/core/cec-adap.c +++ b/drivers/media/cec/core/cec-adap.c -@@ -1671,8 +1671,15 @@ void cec_s_phys_addr(struct cec_adapter *adap, u16 phys_addr, bool block) +@@ -1674,8 +1674,15 @@ void cec_s_phys_addr(struct cec_adapter *adap, u16 phys_addr, bool block) if (IS_ERR_OR_NULL(adap)) return; @@ -3683,10 +3627,10 @@ Signed-off-by: Alex Bee 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 428e057dd415..9f13f2aa87d1 100644 +index 3082387aa53e..b869e9d3cf93 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -3172,18 +3172,11 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) +@@ -3173,18 +3173,11 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) * ask the source to re-read the EDID. */ if (intr_stat & @@ -3706,7 +3650,7 @@ index 428e057dd415..9f13f2aa87d1 100644 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { enum drm_connector_status status = phy_int_pol & HDMI_PHY_HPD ? connector_status_connected -@@ -3197,6 +3190,14 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) +@@ -3198,6 +3191,14 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) drm_helper_hpd_irq_event(hdmi->bridge.dev); drm_bridge_hpd_notify(&hdmi->bridge, status); } @@ -3721,3 +3665,75 @@ index 428e057dd415..9f13f2aa87d1 100644 } hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Fri, 9 Oct 2020 15:24:53 +0000 +Subject: [PATCH] drm/rockchip: vop: create planes in window order + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 36 +++------------------ + 1 file changed, 4 insertions(+), 32 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index 140f52fe2348..40fdfc50b7a8 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -2019,19 +2019,10 @@ static int vop_create_crtc(struct vop *vop) + int ret; + int i; + +- /* +- * Create drm_plane for primary and cursor planes first, since we need +- * to pass them to drm_crtc_init_with_planes, which sets the +- * "possible_crtcs" to the newly initialized crtc. +- */ + for (i = 0; i < vop_data->win_size; i++) { + struct vop_win *vop_win = &vop->win[i]; + const struct vop_win_data *win_data = vop_win->data; + +- if (win_data->type != DRM_PLANE_TYPE_PRIMARY && +- win_data->type != DRM_PLANE_TYPE_CURSOR) +- continue; +- + ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, + 0, &vop_plane_funcs, + win_data->phy->data_formats, +@@ -2064,32 +2055,13 @@ static int vop_create_crtc(struct vop *vop) + drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); + } + +- /* +- * Create drm_planes for overlay windows with possible_crtcs restricted +- * to the newly created crtc. +- */ ++ /* Set possible_crtcs to the newly created crtc for overlay windows */ + for (i = 0; i < vop_data->win_size; i++) { + struct vop_win *vop_win = &vop->win[i]; +- const struct vop_win_data *win_data = vop_win->data; +- unsigned long possible_crtcs = drm_crtc_mask(crtc); +- +- if (win_data->type != DRM_PLANE_TYPE_OVERLAY) +- continue; + +- ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, +- possible_crtcs, +- &vop_plane_funcs, +- win_data->phy->data_formats, +- win_data->phy->nformats, +- win_data->phy->format_modifiers, +- win_data->type, NULL); +- if (ret) { +- DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n", +- ret); +- goto err_cleanup_crtc; +- } +- drm_plane_helper_add(&vop_win->base, &plane_helper_funcs); +- vop_plane_add_properties(&vop_win->base, win_data); ++ plane = &vop_win->base; ++ if (plane->type == DRM_PLANE_TYPE_OVERLAY) ++ plane->possible_crtcs = drm_crtc_mask(crtc); + } + + port = of_get_child_by_name(dev->of_node, "port"); diff --git a/projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch b/projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch index ecc91ff0dc..be3b737d5b 100644 --- a/projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch +++ b/projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch @@ -1,39 +1,3 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 10:18:16 +0000 -Subject: [PATCH] WIP: media: rkvdec: continue to gate clock when decoding - finish - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 4f5436c89e08..06c23512e1a7 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1016,7 +1016,8 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) - state = (status & RKVDEC_RDY_STA) ? - VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; - -- writel(0, rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ writel(RKVDEC_CONFIG_DEC_CLK_GATE_E, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); - if (cancel_delayed_work(&rkvdec->watchdog_work)) { - struct rkvdec_ctx *ctx; - -@@ -1037,7 +1038,8 @@ static void rkvdec_watchdog_func(struct work_struct *work) - ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); - if (ctx) { - dev_err(rkvdec->dev, "Frame processing timed out!\n"); -- writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ writel(RKVDEC_CONFIG_DEC_CLK_GATE_E | RKVDEC_IRQ_DIS, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); - writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL); - rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR); - } - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 23 May 2020 10:16:01 +0000 @@ -46,10 +10,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 06c23512e1a7..630ef09ab70b 100644 +index 4f5436c89e08..eaf2f133a264 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1127,9 +1127,9 @@ static int rkvdec_remove(struct platform_device *pdev) +@@ -1125,9 +1125,9 @@ static int rkvdec_remove(struct platform_device *pdev) { struct rkvdec_dev *rkvdec = platform_get_drvdata(pdev); @@ -235,7 +199,7 @@ index 15b9bee92016..3acc914888f6 100644 #define RKVDEC_REG_SYSCTRL 0x008 #define RKVDEC_IN_ENDIAN BIT(0) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 630ef09ab70b..b6d5b26a93c2 100644 +index eaf2f133a264..f55abb7c377f 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -10,12 +10,15 @@ @@ -300,7 +264,7 @@ index 630ef09ab70b..b6d5b26a93c2 100644 ret = pm_runtime_resume_and_get(rkvdec->dev); if (ret < 0) { -@@ -1021,6 +1056,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) +@@ -1020,6 +1055,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) if (cancel_delayed_work(&rkvdec->watchdog_work)) { struct rkvdec_ctx *ctx; @@ -312,15 +276,15 @@ index 630ef09ab70b..b6d5b26a93c2 100644 ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); rkvdec_job_finish(ctx, state); } -@@ -1038,6 +1078,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) +@@ -1037,6 +1077,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); if (ctx) { dev_err(rkvdec->dev, "Frame processing timed out!\n"); + rkvdec->reset_mask |= RESET_HARD; - writel(RKVDEC_CONFIG_DEC_CLK_GATE_E | RKVDEC_IRQ_DIS, - rkvdec->regs + RKVDEC_REG_INTERRUPT); + writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT); writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL); -@@ -1107,6 +1148,18 @@ static int rkvdec_probe(struct platform_device *pdev) + rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR); +@@ -1105,6 +1146,18 @@ static int rkvdec_probe(struct platform_device *pdev) return ret; } @@ -389,7 +353,7 @@ Subject: [PATCH] WIP: arm64: dts: add resets to vdec for RK3399 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index b0620c45820c..e797271ef6b4 100644 +index 980b12cb0a49..6e3149e587c5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1062,7 +1062,10 @@ power-domain@RK3399_PD_VCODEC { @@ -428,7 +392,7 @@ Signed-off-by: Alex Bee 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index e797271ef6b4..748eb7368e6a 100644 +index 6e3149e587c5..093ebe070775 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1341,7 +1341,7 @@ vpu_mmu: iommu@ff650800 { @@ -454,7 +418,7 @@ Signed-off-by: Alex Bee 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c -index fc96501f3bc8..f31550c21172 100644 +index 8de6fd2e8eef..002b1a600f93 100644 --- a/drivers/staging/media/hantro/rockchip_vpu_hw.c +++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c @@ -15,7 +15,8 @@ @@ -467,7 +431,7 @@ index fc96501f3bc8..f31550c21172 100644 /* * Supported formats. -@@ -273,13 +274,20 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu) +@@ -346,13 +347,20 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu) return 0; } @@ -489,7 +453,7 @@ index fc96501f3bc8..f31550c21172 100644 static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx) { struct hantro_dev *vpu = ctx->dev; -@@ -507,7 +515,7 @@ const struct hantro_variant rk3288_vpu_variant = { +@@ -592,7 +600,7 @@ const struct hantro_variant rk3288_vpu_variant = { .codec_ops = rk3288_vpu_codec_ops, .irqs = rockchip_vpu1_irqs, .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs), @@ -499,29 +463,6 @@ index fc96501f3bc8..f31550c21172 100644 .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) }; -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 3 Apr 2022 13:45:57 +0200 -Subject: [PATCH] media: hantro: rockchip: Enable H.264 codec for RK3399 - ---- - drivers/staging/media/hantro/rockchip_vpu_hw.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c -index f31550c21172..304d7b359295 100644 ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -544,7 +544,7 @@ const struct hantro_variant rk3399_vpu_variant = { - .dec_fmts = rk3399_vpu_dec_fmts, - .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), - .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | -- HANTRO_VP8_DECODER, -+ HANTRO_VP8_DECODER | HANTRO_H264_DECODER, - .codec_ops = rk3399_vpu_codec_ops, - .irqs = rockchip_vpu2_irqs, - .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs), - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sun, 4 Jul 2021 15:19:44 +0200 @@ -548,7 +489,7 @@ index 3acc914888f6..265f5234f4eb 100644 #define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450 diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c -index 311a12656072..ea270262bbed 100644 +index d8c1c0db15c7..a289bc968e91 100644 --- a/drivers/staging/media/rkvdec/rkvdec-vp9.c +++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c @@ -802,6 +802,7 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) @@ -574,31 +515,6 @@ index 311a12656072..ea270262bbed 100644 writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Thu, 16 Jun 2022 13:15:09 +0200 -Subject: [PATCH] arm64: dts: use correct PLL for vdec core - -vdec core should use codec pll for proper operation, by default -it uses general pll (GPLL) - as all other clocks would ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 748eb7368e6a..658ec3b00445 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1346,6 +1346,8 @@ vdec: video-codec@ff660000 { - clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, - <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; - clock-names = "axi", "ahb", "cabac", "core"; -+ assigned-clocks = <&cru ACLK_VDU>; -+ assigned-clock-parents = <&cru PLL_CPLL>; - iommus = <&vdec_mmu>; - power-domains = <&power RK3399_PD_VDU>; - resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>, - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Thu, 16 Jun 2022 13:18:22 +0200 @@ -624,3 +540,4 @@ index 5519347232f6..431c4ec198be 100644 iommus = <&vdec_mmu>; power-domains = <&power RK3328_PD_VIDEO>; }; + diff --git a/projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch b/projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch index 3e70d40a68..2892b62b64 100644 --- a/projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch +++ b/projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch @@ -6,16 +6,48 @@ Subject: [PATCH] arm64: dts: rockchip: add gpu powerdomain, gpu opp-table and Note: since the regulator that supplies the GPU usually also supplies other SoC components, we have to make sure voltage is never lower then -1050 mV - also disable 500 MHz for now, since it will crash if rkvdec +1075 mV - also disable 500 MHz for now, since it will crash if rkvdec is running at the same time (voltage to high) Signed-off-by: Alex Bee --- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 35 ++++++++++++++++++++++++ - 1 file changed, 35 insertions(+) + .../arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 4 +++ + .../arm64/boot/dts/rockchip/rk3328-rock64.dts | 4 +++ + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 35 +++++++++++++++++++ + 3 files changed, 43 insertions(+) +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +index aa22a0c22265..51c7723d6762 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +@@ -166,6 +166,10 @@ &gmac2io { + status = "okay"; + }; + ++&gpu { ++ mali-supply = <&vdd_logic>; ++}; ++ + &hdmi { + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +index f69a38f42d2d..c198a8a7f95a 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +@@ -162,6 +162,10 @@ &gmac2io { + status = "okay"; + }; + ++&gpu { ++ mali-supply = <&vdd_logic>; ++}; ++ + &hdmi { + status = "okay"; + }; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 431c4ec198be..e4977669b16a 100644 +index 431c4ec198be..eec03adf0902 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -300,6 +300,11 @@ power: power-controller { @@ -57,15 +89,15 @@ index 431c4ec198be..e4977669b16a 100644 + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; -+ opp-microvolt = <1050000>; ++ opp-microvolt = <1075000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; -+ opp-microvolt = <1050000>; ++ opp-microvolt = <1075000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <1050000>; ++ opp-microvolt = <1075000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; @@ -137,10 +169,10 @@ Signed-off-by: Alex Bee 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-tinker.dtsi b/arch/arm/boot/dts/rk3288-tinker.dtsi -index 9c1e38c54eae..ee332fc9cf1f 100644 +index 09618bb7d872..db9106a3dd22 100644 --- a/arch/arm/boot/dts/rk3288-tinker.dtsi +++ b/arch/arm/boot/dts/rk3288-tinker.dtsi -@@ -75,7 +75,7 @@ sdio_pwrseq: sdio-pwrseq { +@@ -73,7 +73,7 @@ sdio_pwrseq: sdio-pwrseq { sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; @@ -150,10 +182,10 @@ index 9c1e38c54eae..ee332fc9cf1f 100644 simple-audio-card,codec { diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 658ec3b00445..925d320dea86 100644 +index 093ebe070775..a10fe60b7680 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1892,7 +1892,7 @@ hdmi_sound: hdmi-sound { +@@ -1893,7 +1893,7 @@ hdmi_sound: hdmi-sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; simple-audio-card,mclk-fs = <256>; @@ -174,10 +206,10 @@ Signed-off-by: Alex Bee 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c -index eb0c2d041f13..9256eadb8a3e 100644 +index ad068865ba20..9deb8d1d291d 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c -@@ -1053,7 +1053,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, +@@ -1038,7 +1038,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, ret = obj->funcs->mmap(obj, vma); if (ret) goto err_drm_gem_object_put; @@ -197,7 +229,7 @@ Subject: [PATCH] ASoC: hdmi-codec: fix channel allocation 1 file changed, 52 insertions(+), 61 deletions(-) diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c -index b773466619b2..e53950e85631 100644 +index 5679102de91f..f0cd183f7873 100644 --- a/sound/soc/codecs/hdmi-codec.c +++ b/sound/soc/codecs/hdmi-codec.c @@ -194,78 +194,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = { @@ -395,7 +427,7 @@ Signed-off-by: Alex Bee 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -index aa22a0c22265..a78fbddd21df 100644 +index 51c7723d6762..cf321302daec 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts @@ -88,6 +88,13 @@ vcc_phy: vcc-phy-regulator { @@ -412,7 +444,7 @@ index aa22a0c22265..a78fbddd21df 100644 leds { compatible = "gpio-leds"; -@@ -308,6 +315,13 @@ &io_domains { +@@ -312,6 +319,13 @@ &io_domains { }; &pinctrl { @@ -553,10 +585,10 @@ Signed-off-by: Alex Bee 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 925d320dea86..037732441f92 100644 +index a10fe60b7680..dbe6a9cb98a5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1478,7 +1478,7 @@ cru: clock-controller@ff760000 { +@@ -1477,7 +1477,7 @@ cru: clock-controller@ff760000 { <1000000000>, <150000000>, <75000000>, <37500000>, @@ -609,7 +641,7 @@ Signed-off-by: Alex Bee 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -index f50b47ac11a8..d9b3c8c29e6f 100644 +index a2f0860b20bb..8961f9c7885d 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c @@ -34,9 +34,9 @@ static inline u8 hdmi_read(struct dw_hdmi_i2s_audio_data *audio, int offset) @@ -634,3 +666,46 @@ index f50b47ac11a8..d9b3c8c29e6f 100644 .audio_startup = dw_hdmi_i2s_audio_startup, .audio_shutdown = dw_hdmi_i2s_audio_shutdown, .get_eld = dw_hdmi_i2s_get_eld, +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sun, 18 Sep 2022 10:35:52 +0200 +Subject: [PATCH] arm64: dts: rockchip: Disbake fusb for rk3399-roc-pc + +As it will lead to an unbootable device in case one if those ports +is used to power up the device. +See https://lkml.org/lkml/2022/6/20/413 +--- + arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +index 2f4b1b2e3ac7..7217ead94d39 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +@@ -215,7 +215,7 @@ vdd_log: vdd-log { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; +- regulator-min-microvolt = <450000>; ++ regulator-min-microvolt = <430000>; + regulator-max-microvolt = <1400000>; + pwm-supply = <&vcc3v3_sys>; + }; +@@ -536,7 +536,7 @@ fusb1: usb-typec@22 { + pinctrl-names = "default"; + pinctrl-0 = <&fusb1_int>; + vbus-supply = <&vcc_vbus_typec1>; +- status = "okay"; ++ status = "disabled"; + }; + }; + +@@ -553,7 +553,7 @@ fusb0: usb-typec@22 { + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc_vbus_typec0>; +- status = "okay"; ++ status = "disabled"; + }; + + mp8859: regulator@66 { diff --git a/projects/Rockchip/patches/linux/default/linux-2000-v4l2-wip-rkvdec-hevc.patch b/projects/Rockchip/patches/linux/default/linux-2000-v4l2-wip-rkvdec-hevc.patch index 5553b8009b..047a23ce2f 100644 --- a/projects/Rockchip/patches/linux/default/linux-2000-v4l2-wip-rkvdec-hevc.patch +++ b/projects/Rockchip/patches/linux/default/linux-2000-v4l2-wip-rkvdec-hevc.patch @@ -1,102 +1,3 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 15:03:46 +0000 -Subject: [PATCH] WIP: media: uapi: hevc: add fields needed for rkvdec - -NOTE: these fields are used by rkvdec hevc backend - -Signed-off-by: Jonas Karlman ---- - include/media/hevc-ctrls.h | 12 ++++++++++-- - 1 file changed, 10 insertions(+), 2 deletions(-) - -diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index 01ccda48d8c5..a536dab3f8a7 100644 ---- a/include/media/hevc-ctrls.h -+++ b/include/media/hevc-ctrls.h -@@ -58,6 +58,8 @@ enum v4l2_mpeg_video_hevc_start_code { - /* The controls are not stable at the moment and will likely be reworked. */ - struct v4l2_ctrl_hevc_sps { - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ -+ __u8 video_parameter_set_id; -+ __u8 seq_parameter_set_id; - __u16 pic_width_in_luma_samples; - __u16 pic_height_in_luma_samples; - __u8 bit_depth_luma_minus8; -@@ -81,6 +83,8 @@ struct v4l2_ctrl_hevc_sps { - __u8 chroma_format_idc; - __u8 sps_max_sub_layers_minus1; - -+ __u8 padding[6]; -+ - __u64 flags; - }; - -@@ -108,6 +112,7 @@ struct v4l2_ctrl_hevc_sps { - - struct v4l2_ctrl_hevc_pps { - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ -+ __u8 pic_parameter_set_id; - __u8 num_extra_slice_header_bits; - __u8 num_ref_idx_l0_default_active_minus1; - __u8 num_ref_idx_l1_default_active_minus1; -@@ -123,7 +128,7 @@ struct v4l2_ctrl_hevc_pps { - __s8 pps_tc_offset_div2; - __u8 log2_parallel_merge_level_minus2; - -- __u8 padding[4]; -+ __u8 padding; - __u64 flags; - }; - -@@ -200,7 +205,10 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - -- __u8 padding; -+ __u16 short_term_ref_pic_set_size; -+ __u16 long_term_ref_pic_set_size; -+ -+ __u8 padding[4]; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ - struct v4l2_hevc_pred_weight_table pred_weight_table; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 15:07:15 +0000 -Subject: [PATCH] HACK: media: uapi: hevc: tiles and num_slices - ---- - include/media/hevc-ctrls.h | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - -diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index a536dab3f8a7..c8618dc68fc7 100644 ---- a/include/media/hevc-ctrls.h -+++ b/include/media/hevc-ctrls.h -@@ -83,7 +83,8 @@ struct v4l2_ctrl_hevc_sps { - __u8 chroma_format_idc; - __u8 sps_max_sub_layers_minus1; - -- __u8 padding[6]; -+ __u8 num_slices; -+ __u8 padding[5]; - - __u64 flags; - }; -@@ -208,7 +209,9 @@ struct v4l2_ctrl_hevc_slice_params { - __u16 short_term_ref_pic_set_size; - __u16 long_term_ref_pic_set_size; - -- __u8 padding[4]; -+ __u32 num_entry_point_offsets; -+ __u32 entry_point_offset_minus1[256]; -+ __u8 padding[8]; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ - struct v4l2_hevc_pred_weight_table pred_weight_table; - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 23 May 2020 15:17:45 +0000 @@ -106,13 +7,14 @@ NOTE: cabac table and scailing list code is copied 1:1 from mpp TODO: fix lowdelay flag and rework the scaling list part Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee --- drivers/staging/media/rkvdec/Makefile | 2 +- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 2522 ++++++++++++++++++++ + drivers/staging/media/rkvdec/rkvdec-hevc.c | 2573 ++++++++++++++++++++ drivers/staging/media/rkvdec/rkvdec-regs.h | 1 + - drivers/staging/media/rkvdec/rkvdec.c | 67 + + drivers/staging/media/rkvdec/rkvdec.c | 73 +- drivers/staging/media/rkvdec/rkvdec.h | 1 + - 5 files changed, 2592 insertions(+), 1 deletion(-) + 5 files changed, 2648 insertions(+), 2 deletions(-) create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile @@ -126,10 +28,10 @@ index cb86b429cfaa..a77122641d14 100644 +rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c new file mode 100644 -index 000000000000..c3cceba837c2 +index 000000000000..fd87cbf9c1f8 --- /dev/null +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -0,0 +1,2522 @@ +@@ -0,0 +1,2573 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Rockchip Video Decoder HEVC backend @@ -248,6 +150,7 @@ index 000000000000..c3cceba837c2 +struct rkvdec_hevc_run { + struct rkvdec_run base; + const struct v4l2_ctrl_hevc_slice_params *slices_params; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params; + const struct v4l2_ctrl_hevc_sps *sps; + const struct v4l2_ctrl_hevc_pps *pps; + const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; @@ -2179,7 +2082,7 @@ index 000000000000..c3cceba837c2 + /* write sps */ + WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID); + WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(1, CHROMA_FORMAT_IDC); ++ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); + WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES); + WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES); + WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA); @@ -2225,8 +2128,6 @@ index 000000000000..c3cceba837c2 + SPS_TEMPORAL_MVP_ENABLED_FLAG); + WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED), + STRONG_INTRA_SMOOTHING_ENABLED_FLAG); -+ //WRITE_PPS(0, PS_FIELD(100, 7)); -+ //WRITE_PPS(0x1fffff, PS_FIELD(107, 21)); + + /* write pps */ + WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); @@ -2284,11 +2185,8 @@ index 000000000000..c3cceba837c2 + WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL); + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT), + SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG); -+ //WRITE_PPS(0, PS_FIELD(209, 3)); + WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS); + WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS); -+ //WRITE_PPS(0x2, PS_FIELD(222, 2)); -+ //WRITE_PPS(0xffffffff, PS_FIELD(224, 32)); + + if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) { + for (i = 0; i <= pps->num_tile_columns_minus1; i++) @@ -2296,27 +2194,28 @@ index 000000000000..c3cceba837c2 + for (i = 0; i <= pps->num_tile_rows_minus1; i++) + WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i)); + } else { -+ WRITE_PPS(round_up(sps->pic_width_in_luma_samples, ctb_size_y) - 1, ++ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, + COLUMN_WIDTH(0)); -+ WRITE_PPS(round_up(sps->pic_height_in_luma_samples, ctb_size_y) - 1, ++ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, + ROW_HEIGHT(0)); + } + + scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); + scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance; + WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS); -+ //WRITE_PPS(0xffff, PS_FIELD(624, 16)); +} + +static void assemble_hw_rps(struct rkvdec_ctx *ctx, + struct rkvdec_hevc_run *run) +{ ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; + const struct v4l2_ctrl_hevc_slice_params *sl_params; + const struct v4l2_hevc_dpb_entry *dpb; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; + struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; + struct rkvdec_rps_packet *hw_ps; + int i, j; ++ unsigned int lowdelay; + +#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value) + @@ -2326,47 +2225,49 @@ index 000000000000..c3cceba837c2 +#define REF_PIC_IDX_L1(i) PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4) + +#define LOWDELAY PS_FIELD(182, 1) -+#define SHORT_TERM_REF_PIC_SET_SIZE PS_FIELD(183, 10) -+#define LONG_TERM_REF_PIC_SET_SIZE PS_FIELD(193, 9) ++#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10) ++#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9) +#define NUM_RPS_POC PS_FIELD(202, 4) + + for (j = 0; j < run->num_slices; j++) { + sl_params = &run->slices_params[j]; -+ dpb = sl_params->dpb; ++ dpb = decode_params->dpb; ++ lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1; + + hw_ps = &priv_tbl->rps[j]; + memset(hw_ps, 0, sizeof(*hw_ps)); + + for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) { -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR), ++ WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), + REF_PIC_LONG_TERM_L0(i)); + WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); ++ ++ if (dpb[sl_params->ref_idx_l0[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) ++ lowdelay = 0; ++ + } + + for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR), ++ WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), + REF_PIC_LONG_TERM_L1(i)); + WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); ++ ++ if (dpb[sl_params->ref_idx_l1[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) ++ lowdelay = 0; + } + -+ //WRITE_RPS(0xffffffff, PS_FIELD(96, 32)); ++ WRITE_RPS(lowdelay, LOWDELAY); + -+ // TODO: lowdelay -+ WRITE_RPS(0, LOWDELAY); -+ -+ // NOTE: these two differs from mpp ++ WRITE_RPS(sl_params->long_term_ref_pic_set_size + ++ sl_params->short_term_ref_pic_set_size, ++ LONG_TERM_RPS_BIT_OFFSET); + WRITE_RPS(sl_params->short_term_ref_pic_set_size, -+ SHORT_TERM_REF_PIC_SET_SIZE); -+ WRITE_RPS(sl_params->long_term_ref_pic_set_size, -+ LONG_TERM_REF_PIC_SET_SIZE); ++ SHORT_TERM_RPS_BIT_OFFSET); + -+ WRITE_RPS(sl_params->num_rps_poc_st_curr_before + -+ sl_params->num_rps_poc_st_curr_after + -+ sl_params->num_rps_poc_lt_curr, ++ WRITE_RPS(decode_params->num_poc_st_curr_before + ++ decode_params->num_poc_st_curr_after + ++ decode_params->num_poc_lt_curr, + NUM_RPS_POC); -+ -+ //WRITE_RPS(0x3ffff, PS_FIELD(206, 18)); -+ //WRITE_RPS(0xffffffff, PS_FIELD(224, 32)); + } +} + @@ -2412,12 +2313,12 @@ index 000000000000..c3cceba837c2 + unsigned int dpb_idx) +{ + struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; -+ const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; ++ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; + struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; + int buf_idx = -1; + -+ if (dpb_idx < sl_params->num_active_dpb_entries) ++ if (dpb_idx < decode_params->num_active_dpb_entries) + buf_idx = vb2_find_timestamp(cap_q, + dpb[dpb_idx].timestamp, 0); + @@ -2435,8 +2336,9 @@ index 000000000000..c3cceba837c2 + struct rkvdec_hevc_run *run) +{ + struct rkvdec_dev *rkvdec = ctx->dev; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; + const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; -+ const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb; ++ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; + dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; + const struct v4l2_pix_format_mplane *dst_fmt; @@ -2498,8 +2400,8 @@ index 000000000000..c3cceba837c2 + for (i = 0; i < 15; i++) { + struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); + -+ if (i < 4 && sl_params->num_active_dpb_entries) { -+ reg = GENMASK(sl_params->num_active_dpb_entries - 1, 0); ++ if (i < 4 && decode_params->num_active_dpb_entries) { ++ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); + reg = (reg >> (i * 4)) & 0xf; + } else + reg = 0; @@ -2508,7 +2410,7 @@ index 000000000000..c3cceba837c2 + writel_relaxed(refer_addr | reg, + rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); + -+ reg = RKVDEC_POC_REFER(i < sl_params->num_active_dpb_entries ? dpb[i].pic_order_cnt_val : 0); ++ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt_val : 0); + writel_relaxed(reg, + rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); + } @@ -2547,17 +2449,58 @@ index 000000000000..c3cceba837c2 + return 0; +} + ++static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, ++ const struct v4l2_ctrl_hevc_sps *sps) ++{ ++ if (sps->chroma_format_idc > 1) ++ /* Only 4:0:0 and 4:2:0 are supported */ ++ return -EINVAL; ++ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) ++ /* Luma and chroma bit depth mismatch */ ++ return -EINVAL; ++ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) ++ /* Only 8-bit and 10-bit is supported */ ++ return -EINVAL; ++ ++ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || ++ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) ++{ ++ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; ++ ++ if (sps->bit_depth_luma_minus8 == 2) ++ return V4L2_PIX_FMT_NV15; ++ else ++ return V4L2_PIX_FMT_NV12; ++} ++ +static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) +{ + struct rkvdec_dev *rkvdec = ctx->dev; + struct rkvdec_hevc_priv_tbl *priv_tbl; + struct rkvdec_hevc_ctx *hevc_ctx; ++ struct v4l2_ctrl *ctrl; + int ret; + ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_SPS); ++ if (!ctrl) ++ return -EINVAL; ++ ++ ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); ++ if (ret) ++ return ret; ++ + hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); + if (!hevc_ctx) + return -ENOMEM; + ++ + priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), + &hevc_ctx->priv_tbl.dma, GFP_KERNEL); + if (!priv_tbl) { @@ -2593,24 +2536,24 @@ index 000000000000..c3cceba837c2 + struct rkvdec_hevc_run *run) +{ + struct v4l2_ctrl *ctrl; -+ + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS); ++ V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); ++ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_SLICE_PARAMS); + run->slices_params = ctrl ? ctrl->p_cur.p : NULL; ++ run->num_slices = ctrl->new_elems; + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_MPEG_VIDEO_HEVC_SPS); ++ V4L2_CID_STATELESS_HEVC_SPS); + run->sps = ctrl ? ctrl->p_cur.p : NULL; + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_MPEG_VIDEO_HEVC_PPS); ++ V4L2_CID_STATELESS_HEVC_PPS); + run->pps = ctrl ? ctrl->p_cur.p : NULL; + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX); ++ V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); + run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; + + rkvdec_run_preamble(ctx, &run->base); -+ -+ // HACK: we need num slices from somewhere -+ run->num_slices = run->sps->num_slices; +} + +static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) @@ -2646,11 +2589,21 @@ index 000000000000..c3cceba837c2 + return 0; +} + ++static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) ++{ ++ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) ++ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); ++ ++ return 0; ++} ++ +const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { + .adjust_fmt = rkvdec_hevc_adjust_fmt, + .start = rkvdec_hevc_start, + .stop = rkvdec_hevc_stop, + .run = rkvdec_hevc_run, ++ .try_ctrl = rkvdec_hevc_try_ctrl, ++ .valid_fmt = rkvdec_hevc_valid_fmt, +}; diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h index 265f5234f4eb..4319ee3ccbbc 100644 @@ -2665,40 +2618,53 @@ index 265f5234f4eb..4319ee3ccbbc 100644 #define RKVDEC_MODE_VP9 2 #define RKVDEC_RPS_MODE BIT(24) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index b6d5b26a93c2..7e8674e7d501 100644 +index f55abb7c377f..00a9bf583596 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -134,6 +134,58 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { +@@ -74,7 +74,7 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) + { + struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); + +- if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) { ++ if (!ctx->valid_fmt) { + ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); + if (ctx->valid_fmt) { + struct v4l2_pix_format_mplane *pix_mp; +@@ -134,6 +134,62 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { }, }; +static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { + { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS, -+ // HACK: match ffmpeg v4l2 request api hwaccel size, -+ // we should support variable length up to 600 slices -+ .cfg.dims = { 32 }, ++ .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS, ++ .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY, ++ .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS, ++ .cfg.dims = { 600 }, + }, + { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, ++ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS, ++ .cfg.ops = &rkvdec_ctrl_ops, + }, + { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PPS, ++ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS, + }, + { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX, ++ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, + }, + { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED, ++ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, + }, + { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_START_CODE, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B, -+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B, ++ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, ++ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, ++ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, ++ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE, ++ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, ++ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, ++ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, + }, + { + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, @@ -2727,7 +2693,7 @@ index b6d5b26a93c2..7e8674e7d501 100644 static const struct rkvdec_ctrls rkvdec_h264_ctrls = { .ctrls = rkvdec_h264_ctrl_descs, .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), -@@ -187,6 +239,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { +@@ -187,6 +243,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { .decoded_fmts = rkvdec_h264_decoded_fmts, .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, }, @@ -2762,391 +2728,6 @@ index f02f79c405f0..d6222a2588be 100644 #endif /* RKVDEC_H_ */ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 21 Aug 2021 16:01:43 +0200 -Subject: [PATCH] media: rkvdec: hevc: adapt for 5.14 uAPI - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 29 +++++++++++++--------- - drivers/staging/media/rkvdec/rkvdec.c | 3 +++ - 2 files changed, 20 insertions(+), 12 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index c3cceba837c2..5c341b5fa534 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -116,6 +116,7 @@ struct rkvdec_hevc_priv_tbl { - struct rkvdec_hevc_run { - struct rkvdec_run base; - const struct v4l2_ctrl_hevc_slice_params *slices_params; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params; - const struct v4l2_ctrl_hevc_sps *sps; - const struct v4l2_ctrl_hevc_pps *pps; - const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; -@@ -2179,6 +2180,7 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, - static void assemble_hw_rps(struct rkvdec_ctx *ctx, - struct rkvdec_hevc_run *run) - { -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; - const struct v4l2_ctrl_hevc_slice_params *sl_params; - const struct v4l2_hevc_dpb_entry *dpb; - struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -@@ -2200,7 +2202,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - - for (j = 0; j < run->num_slices; j++) { - sl_params = &run->slices_params[j]; -- dpb = sl_params->dpb; -+ dpb = decode_params->dpb; - - hw_ps = &priv_tbl->rps[j]; - memset(hw_ps, 0, sizeof(*hw_ps)); -@@ -2228,9 +2230,9 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - WRITE_RPS(sl_params->long_term_ref_pic_set_size, - LONG_TERM_REF_PIC_SET_SIZE); - -- WRITE_RPS(sl_params->num_rps_poc_st_curr_before + -- sl_params->num_rps_poc_st_curr_after + -- sl_params->num_rps_poc_lt_curr, -+ WRITE_RPS(decode_params->num_poc_st_curr_before + -+ decode_params->num_poc_st_curr_after + -+ decode_params->num_poc_lt_curr, - NUM_RPS_POC); - - //WRITE_RPS(0x3ffff, PS_FIELD(206, 18)); -@@ -2280,12 +2282,12 @@ get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, - unsigned int dpb_idx) - { - struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -- const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; -- const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; - struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; - int buf_idx = -1; - -- if (dpb_idx < sl_params->num_active_dpb_entries) -+ if (dpb_idx < decode_params->num_active_dpb_entries) - buf_idx = vb2_find_timestamp(cap_q, - dpb[dpb_idx].timestamp, 0); - -@@ -2303,8 +2305,9 @@ static void config_registers(struct rkvdec_ctx *ctx, - struct rkvdec_hevc_run *run) - { - struct rkvdec_dev *rkvdec = ctx->dev; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; - const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; -- const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; - struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; - dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; - const struct v4l2_pix_format_mplane *dst_fmt; -@@ -2366,8 +2369,8 @@ static void config_registers(struct rkvdec_ctx *ctx, - for (i = 0; i < 15; i++) { - struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); - -- if (i < 4 && sl_params->num_active_dpb_entries) { -- reg = GENMASK(sl_params->num_active_dpb_entries - 1, 0); -+ if (i < 4 && decode_params->num_active_dpb_entries) { -+ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); - reg = (reg >> (i * 4)) & 0xf; - } else - reg = 0; -@@ -2376,7 +2379,7 @@ static void config_registers(struct rkvdec_ctx *ctx, - writel_relaxed(refer_addr | reg, - rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); - -- reg = RKVDEC_POC_REFER(i < sl_params->num_active_dpb_entries ? dpb[i].pic_order_cnt_val : 0); -+ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt_val : 0); - writel_relaxed(reg, - rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); - } -@@ -2461,7 +2464,9 @@ static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, - struct rkvdec_hevc_run *run) - { - struct v4l2_ctrl *ctrl; -- -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS); -+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; - ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, - V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS); - run->slices_params = ctrl ? ctrl->p_cur.p : NULL; -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 7e8674e7d501..0f877acfba27 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -150,6 +150,9 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { - { - .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX, - }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS, -+ }, - { - .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE, - .cfg.min = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 1 Aug 2020 12:24:58 +0000 -Subject: [PATCH] WIP: media: rkvdec: add HEVC format validation - ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 55 +++++++++++++++++++++- - drivers/staging/media/rkvdec/rkvdec.c | 3 +- - 2 files changed, 55 insertions(+), 3 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 5c341b5fa534..ac06039140bc 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2208,13 +2208,13 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - memset(hw_ps, 0, sizeof(*hw_ps)); - - for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) { -- WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR), -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), - REF_PIC_LONG_TERM_L0(i)); - WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); - } - - for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { -- WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR), -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), - REF_PIC_LONG_TERM_L1(i)); - WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); - } -@@ -2418,17 +2418,58 @@ static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, - return 0; - } - -+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, -+ const struct v4l2_ctrl_hevc_sps *sps) -+{ -+ if (sps->chroma_format_idc > 1) -+ /* Only 4:0:0 and 4:2:0 are supported */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -+ /* Luma and chroma bit depth mismatch */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ -+ return -EINVAL; -+ -+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || -+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; -+ -+ if (sps->bit_depth_luma_minus8 == 2) -+ return V4L2_PIX_FMT_NV15; -+ else -+ return V4L2_PIX_FMT_NV12; -+} -+ - static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) - { - struct rkvdec_dev *rkvdec = ctx->dev; - struct rkvdec_hevc_priv_tbl *priv_tbl; - struct rkvdec_hevc_ctx *hevc_ctx; -+ struct v4l2_ctrl *ctrl; - int ret; - -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_MPEG_VIDEO_HEVC_SPS); -+ if (!ctrl) -+ return -EINVAL; -+ -+ ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ if (ret) -+ return ret; -+ - hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); - if (!hevc_ctx) - return -ENOMEM; - -+ - priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), - &hevc_ctx->priv_tbl.dma, GFP_KERNEL); - if (!priv_tbl) { -@@ -2519,9 +2560,19 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) - return 0; - } - -+static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ if (ctrl->id == V4L2_CID_MPEG_VIDEO_HEVC_SPS) -+ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ -+ return 0; -+} -+ - const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { - .adjust_fmt = rkvdec_hevc_adjust_fmt, - .start = rkvdec_hevc_start, - .stop = rkvdec_hevc_stop, - .run = rkvdec_hevc_run, -+ .try_ctrl = rkvdec_hevc_try_ctrl, -+ .valid_fmt = rkvdec_hevc_valid_fmt, - }; -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 0f877acfba27..9f6a619499ab 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -74,7 +74,7 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) - { - struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); - -- if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) { -+ if (!ctx->valid_fmt) { - ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); - if (ctx->valid_fmt) { - struct v4l2_pix_format_mplane *pix_mp; -@@ -143,6 +143,7 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { - }, - { - .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, -+ .cfg.ops = &rkvdec_ctrl_ops, - }, - { - .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PPS, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 14 Apr 2021 18:01:21 +0200 -Subject: [PATCH] WIP: media: rkvdec: hevc: Fix column width / row height - calculation for no-tiled case - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index ac06039140bc..99bfb937facc 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2165,9 +2165,9 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, - for (i = 0; i <= pps->num_tile_rows_minus1; i++) - WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i)); - } else { -- WRITE_PPS(round_up(sps->pic_width_in_luma_samples, ctb_size_y) - 1, -+ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, - COLUMN_WIDTH(0)); -- WRITE_PPS(round_up(sps->pic_height_in_luma_samples, ctb_size_y) - 1, -+ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, - ROW_HEIGHT(0)); - } - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 14 Apr 2021 17:26:43 +0200 -Subject: [PATCH] WIP: media: rkvdec: hevc: fix long ref decoding - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 99bfb937facc..b5bb4c083dbc 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2196,8 +2196,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - #define REF_PIC_IDX_L1(i) PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4) - - #define LOWDELAY PS_FIELD(182, 1) --#define SHORT_TERM_REF_PIC_SET_SIZE PS_FIELD(183, 10) --#define LONG_TERM_REF_PIC_SET_SIZE PS_FIELD(193, 9) -+#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10) -+#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9) - #define NUM_RPS_POC PS_FIELD(202, 4) - - for (j = 0; j < run->num_slices; j++) { -@@ -2224,11 +2224,11 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - // TODO: lowdelay - WRITE_RPS(0, LOWDELAY); - -- // NOTE: these two differs from mpp -+ WRITE_RPS(sl_params->long_term_ref_pic_set_size + -+ sl_params->short_term_ref_pic_set_size, -+ LONG_TERM_RPS_BIT_OFFSET); - WRITE_RPS(sl_params->short_term_ref_pic_set_size, -- SHORT_TERM_REF_PIC_SET_SIZE); -- WRITE_RPS(sl_params->long_term_ref_pic_set_size, -- LONG_TERM_REF_PIC_SET_SIZE); -+ SHORT_TERM_RPS_BIT_OFFSET); - - WRITE_RPS(decode_params->num_poc_st_curr_before + - decode_params->num_poc_st_curr_after + - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Thu, 15 Apr 2021 20:22:54 +0200 -Subject: [PATCH] WIP: media: rkvdec: hevc: implement lowdelay - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 12 ++++++++++-- - 1 file changed, 10 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index b5bb4c083dbc..8467084165df 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2187,6 +2187,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; - struct rkvdec_rps_packet *hw_ps; - int i, j; -+ unsigned int lowdelay; - - #define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value) - -@@ -2203,6 +2204,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - for (j = 0; j < run->num_slices; j++) { - sl_params = &run->slices_params[j]; - dpb = decode_params->dpb; -+ lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1; - - hw_ps = &priv_tbl->rps[j]; - memset(hw_ps, 0, sizeof(*hw_ps)); -@@ -2211,18 +2213,24 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), - REF_PIC_LONG_TERM_L0(i)); - WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); -+ -+ if (dpb[sl_params->ref_idx_l0[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; -+ - } - - for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { - WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), - REF_PIC_LONG_TERM_L1(i)); - WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); -+ -+ if (dpb[sl_params->ref_idx_l1[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; - } - - //WRITE_RPS(0xffffffff, PS_FIELD(96, 32)); - -- // TODO: lowdelay -- WRITE_RPS(0, LOWDELAY); -+ WRITE_RPS(lowdelay, LOWDELAY); - - WRITE_RPS(sl_params->long_term_ref_pic_set_size + - sl_params->short_term_ref_pic_set_size, - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sat, 30 Jan 2021 18:16:39 +0100 @@ -3169,7 +2750,7 @@ Signed-off-by: Alex Bee 2 files changed, 85 insertions(+), 30 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 9f6a619499ab..2d1a388e20fe 100644 +index 00a9bf583596..955c53afe20f 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -14,6 +14,7 @@ @@ -3344,7 +2925,7 @@ index 9f6a619499ab..2d1a388e20fe 100644 } ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); -@@ -1157,8 +1185,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) +@@ -1155,8 +1183,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) } } @@ -3363,7 +2944,7 @@ index 9f6a619499ab..2d1a388e20fe 100644 { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_rkvdec_match); -@@ -1170,6 +1207,7 @@ static const char * const rkvdec_clk_names[] = { +@@ -1168,6 +1205,7 @@ static const char * const rkvdec_clk_names[] = { static int rkvdec_probe(struct platform_device *pdev) { struct rkvdec_dev *rkvdec; @@ -3371,7 +2952,7 @@ index 9f6a619499ab..2d1a388e20fe 100644 unsigned int i; int ret, irq; -@@ -1195,6 +1233,13 @@ static int rkvdec_probe(struct platform_device *pdev) +@@ -1193,6 +1231,13 @@ static int rkvdec_probe(struct platform_device *pdev) if (ret) return ret; @@ -3442,10 +3023,10 @@ Signed-off-by: Alex Bee 1 file changed, 8 insertions(+) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 2d1a388e20fe..c2de6fcb6419 100644 +index 955c53afe20f..4e228cd82f21 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1191,11 +1191,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { +@@ -1189,11 +1189,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { RKVDEC_CAPABILITY_VP9 }; @@ -3517,25 +3098,130 @@ index 7b2cde230b87..59fba3ac6aae 100644 gpu: gpu@ffa30000 { From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 3 Apr 2022 14:39:14 +0200 -Subject: [PATCH] WIP: media: rkvdec: hevc: Use chroma_format_idc from - v4l2_ctrl_hevc_sps +From: Nicolas Dufresne +Date: Tue, 10 May 2022 14:37:29 -0400 +Subject: [PATCH] media: rkvdec: Fix HEVC RPS bit offsets +The offsets from the uAPI need to be extended to include some bits +that can be calculated from the parameters. This has been compared +to match with the vendor bit sizes (which simply parse again the +data to calcualte it). + +Fixed by this change: +- LTRPSPS_A_Qualcomm_1 +- RPS_C_ericsson_5 +- RPS_D_ericsson_6 +- RPS_E_qualcomm_5 + +Signed-off-by: Nicolas Dufresne --- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) + drivers/staging/media/rkvdec/rkvdec-hevc.c | 26 +++++++++++++++++++--- + 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 8467084165df..a7dc8262f6d7 100644 +index fd87cbf9c1f8..2fbed8d49a76 100644 --- a/drivers/staging/media/rkvdec/rkvdec-hevc.c +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2048,7 +2048,7 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, - /* write sps */ - WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID); - WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); -- WRITE_PPS(1, CHROMA_FORMAT_IDC); -+ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); - WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES); - WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES); - WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA); +@@ -10,6 +10,7 @@ + */ + + #include ++#include + + #include "rkvdec.h" + #include "rkvdec-regs.h" +@@ -2175,6 +2176,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + struct rkvdec_hevc_run *run) + { + const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; ++ const struct v4l2_ctrl_hevc_sps *sps = run->sps; + const struct v4l2_ctrl_hevc_slice_params *sl_params; + const struct v4l2_hevc_dpb_entry *dpb; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; +@@ -2196,9 +2198,21 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + #define NUM_RPS_POC PS_FIELD(202, 4) + + for (j = 0; j < run->num_slices; j++) { ++ uint st_bit_offset = 0; ++ + sl_params = &run->slices_params[j]; + dpb = decode_params->dpb; +- lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1; ++ ++ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { ++ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1; ++ ++ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) ++ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1; ++ ++ lowdelay = 1; ++ } else { ++ lowdelay = 0; ++ } + + hw_ps = &priv_tbl->rps[j]; + memset(hw_ps, 0, sizeof(*hw_ps)); +@@ -2224,8 +2238,14 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + + WRITE_RPS(lowdelay, LOWDELAY); + +- WRITE_RPS(sl_params->long_term_ref_pic_set_size + +- sl_params->short_term_ref_pic_set_size, ++ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) { ++ if (sl_params->short_term_ref_pic_set_size) ++ st_bit_offset = sl_params->short_term_ref_pic_set_size; ++ else if (sps->num_short_term_ref_pic_sets > 1) ++ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1); ++ } ++ ++ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size, + LONG_TERM_RPS_BIT_OFFSET); + WRITE_RPS(sl_params->short_term_ref_pic_set_size, + SHORT_TERM_RPS_BIT_OFFSET); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nicolas Dufresne +Date: Tue, 10 May 2022 15:12:03 -0400 +Subject: [PATCH] media: rkvdec: Fix number of HEVC references being set in RPS + +The numbers from the bitstream are values between 1 - 16 (as they are +the number - 1). The difference between 0 and 1 needs to be determined +base on the slice type. I frames have no reference, P frames only have +L0 reference, and B frames have both. + +Signed-off-by: Nicolas Dufresne +--- + drivers/staging/media/rkvdec/rkvdec-hevc.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c +index 2fbed8d49a76..4a15ebb94149 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c ++++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c +@@ -2199,6 +2199,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + + for (j = 0; j < run->num_slices; j++) { + uint st_bit_offset = 0; ++ uint num_l0_refs = 0; ++ uint num_l1_refs = 0; + + sl_params = &run->slices_params[j]; + dpb = decode_params->dpb; +@@ -2217,7 +2219,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + hw_ps = &priv_tbl->rps[j]; + memset(hw_ps, 0, sizeof(*hw_ps)); + +- for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) { ++ for (i = 0; i < num_l0_refs; i++) { + WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), + REF_PIC_LONG_TERM_L0(i)); + WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); +@@ -2227,7 +2229,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + + } + +- for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { ++ for (i = 0; i < num_l1_refs; i++) { + WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), + REF_PIC_LONG_TERM_L1(i)); + WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); diff --git a/projects/Rockchip/patches/linux/default/linux-2001-v4l2-wip-iep-driver.patch b/projects/Rockchip/patches/linux/default/linux-2001-v4l2-wip-iep-driver.patch index 6ed5f6332d..058b6fc229 100644 --- a/projects/Rockchip/patches/linux/default/linux-2001-v4l2-wip-iep-driver.patch +++ b/projects/Rockchip/patches/linux/default/linux-2001-v4l2-wip-iep-driver.patch @@ -1687,7 +1687,7 @@ Signed-off-by: Alex Bee 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index e4977669b16a..6c0cbc9cea61 100644 +index eec03adf0902..5455a46c9a6b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -760,6 +760,28 @@ vop_mmu: iommu@ff373f00 { @@ -1731,10 +1731,10 @@ Signed-off-by: Alex Bee 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 037732441f92..d90c90406a49 100644 +index dbe6a9cb98a5..f0629b7a81c6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1367,14 +1367,25 @@ vdec_mmu: iommu@ff660480 { +@@ -1365,14 +1365,25 @@ vdec_mmu: iommu@ff660480 { #iommu-cells = <0>; }; From 41ad0fd3f46137d1e843d13138a70ca79c88b97e Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Mon, 22 Aug 2022 10:26:25 +0000 Subject: [PATCH 12/29] linux (Samsung): rebase patches for 6.0-rc2 --- ...IP-ARM-dma-mapping-implement-alloc_noncontiguous.patch | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/projects/Samsung/patches/linux/samsung-0008-WIP-ARM-dma-mapping-implement-alloc_noncontiguous.patch b/projects/Samsung/patches/linux/samsung-0008-WIP-ARM-dma-mapping-implement-alloc_noncontiguous.patch index e13de2e8cd..e88a4b3a65 100644 --- a/projects/Samsung/patches/linux/samsung-0008-WIP-ARM-dma-mapping-implement-alloc_noncontiguous.patch +++ b/projects/Samsung/patches/linux/samsung-0008-WIP-ARM-dma-mapping-implement-alloc_noncontiguous.patch @@ -16,7 +16,7 @@ index 059cce018570..8f867cb9fe75 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -1759,6 +1759,63 @@ static void arm_iommu_unmap_sg(struct device *dev, - __iommu_unmap_sg(dev, sg, nents, dir, attrs, false); + } } +static struct sg_table *arm_iommu_alloc_noncontiguous(struct device *dev, @@ -50,8 +50,8 @@ index 059cce018570..8f867cb9fe75 100644 + GFP_KERNEL)) + goto err_buffer; + -+ if (__iommu_map_sg(dev, sh->sgt.sgl, sh->sgt.orig_nents, dir, attrs, -+ false) < 1) ++ if (arm_iommu_map_sg(dev, sh->sgt.sgl, sh->sgt.orig_nents, dir, attrs ++ ) < 1) + goto err_free_sg; + + return &sh->sgt; @@ -70,7 +70,7 @@ index 059cce018570..8f867cb9fe75 100644 +{ + struct dma_sgt_handle *sh = sgt_handle(sgt); + -+ __iommu_unmap_sg(dev, sgt->sgl, sgt->orig_nents, dir, 0, false); ++ arm_iommu_unmap_sg(dev, sgt->sgl, sgt->orig_nents, dir, 0); + __iommu_free_buffer(dev, sh->pages, PAGE_ALIGN(size), 0); + sg_free_table(&sh->sgt); + kfree(sh); From 77c336fe1cd3adde9318de6fb5aee7e0e43fdad8 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Mon, 22 Aug 2022 13:23:14 +0000 Subject: [PATCH 13/29] linux (Allwinner aarch64): update .config for 6.0-rc4 --- projects/Allwinner/linux/linux.aarch64.conf | 63 +++++++++++++++------ 1 file changed, 45 insertions(+), 18 deletions(-) diff --git a/projects/Allwinner/linux/linux.aarch64.conf b/projects/Allwinner/linux/linux.aarch64.conf index 2c4e793a03..aa22e26609 100644 --- a/projects/Allwinner/linux/linux.aarch64.conf +++ b/projects/Allwinner/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.19.7-rc1 Kernel Configuration +# Linux/arm64 6.0.0-rc4 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-elf-gcc-12.2.0 (GCC) 12.2.0" CONFIG_CC_IS_GCC=y @@ -11,7 +11,6 @@ CONFIG_AS_VERSION=23900 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23900 CONFIG_LLD_VERSION=0 -CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y @@ -70,6 +69,8 @@ CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem @@ -163,6 +164,7 @@ CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y CONFIG_MEMCG_KMEM=y @@ -300,6 +302,7 @@ CONFIG_ARCH_SUNXI=y # CONFIG_ARCH_BCM2835 is not set # CONFIG_ARCH_BCM4908 is not set # CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BCMBCA is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_BITMAIN is not set # CONFIG_ARCH_BRCMSTB is not set @@ -314,6 +317,7 @@ CONFIG_ARCH_SUNXI=y # CONFIG_ARCH_MESON is not set # CONFIG_ARCH_MVEBU is not set # CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_NPCM is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_RENESAS is not set @@ -466,7 +470,6 @@ CONFIG_AS_HAS_ARMV8_5=y # CONFIG_ARM64_BTI is not set CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y # CONFIG_ARM64_E0PD is not set -# CONFIG_ARCH_RANDOM is not set CONFIG_ARM64_AS_HAS_MTE=y # end of ARMv8.5 architectural features @@ -506,6 +509,7 @@ CONFIG_PM_STD_PARTITION="" CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y # CONFIG_PM_DEBUG is not set @@ -539,7 +543,6 @@ CONFIG_DT_IDLE_GENPD=y # # ARM CPU Idle Drivers # -CONFIG_ARM_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y # end of ARM CPU Idle Drivers @@ -589,6 +592,7 @@ CONFIG_CRYPTO_SHA512_ARM64_CE=m # CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set # CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set CONFIG_CRYPTO_GHASH_ARM64_CE=y +# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y @@ -609,6 +613,7 @@ CONFIG_KEXEC_CORE=y CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y @@ -657,7 +662,7 @@ CONFIG_ARCH_SUPPORTS_LTO_CLANG=y CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y CONFIG_LTO_NONE=y CONFIG_ARCH_SUPPORTS_CFI_CLANG=y -CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOVE_PUD=y @@ -697,6 +702,7 @@ CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y +CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y # # GCOV-based kernel profiling @@ -842,9 +848,11 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_MEMORY_FAILURE=y # CONFIG_HWPOISON_INJECT is not set +CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +CONFIG_THP_SWAP=y # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set @@ -856,7 +864,6 @@ CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y -CONFIG_ARCH_HAS_VM_GET_PAGE_PROT=y CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ARCH_HAS_ZONE_DMA_SET=y CONFIG_ZONE_DMA=y @@ -1649,6 +1656,7 @@ CONFIG_BLK_DEV_NBD=y # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_UBLK is not set # # NVME Support @@ -1678,6 +1686,7 @@ CONFIG_SRAM=y # CONFIG_XILINX_SDFEC is not set # CONFIG_HISI_HIKEY_USB is not set # CONFIG_OPEN_DICE is not set +# CONFIG_VCPU_STALL_DETECTOR is not set # CONFIG_C2PORT is not set # @@ -1890,6 +1899,7 @@ CONFIG_HNS_ENET=y CONFIG_NET_VENDOR_HUAWEI=y CONFIG_NET_VENDOR_I825XX=y CONFIG_NET_VENDOR_INTEL=y +# CONFIG_NET_VENDOR_WANGXUN is not set # CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y CONFIG_MVMDIO=y @@ -2464,7 +2474,6 @@ CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_8250_EXTENDED=y # CONFIG_SERIAL_8250_MANY_PORTS is not set -# CONFIG_SERIAL_8250_ASPEED_VUART is not set CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_8250_DETECT_IRQ is not set # CONFIG_SERIAL_8250_RSA is not set @@ -2523,6 +2532,7 @@ CONFIG_TCG_TPM=y CONFIG_HW_RANDOM_TPM=y # CONFIG_TCG_TIS is not set # CONFIG_TCG_TIS_SPI is not set +# CONFIG_TCG_TIS_I2C is not set # CONFIG_TCG_TIS_I2C_CR50 is not set # CONFIG_TCG_TIS_I2C_ATMEL is not set CONFIG_TCG_TIS_I2C_INFINEON=y @@ -2532,6 +2542,7 @@ CONFIG_TCG_TIS_I2C_INFINEON=y # CONFIG_TCG_TIS_ST33ZP24_SPI is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set +CONFIG_RANDOM_TRUST_CPU=y # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # end of Character devices @@ -2627,6 +2638,7 @@ CONFIG_SPI_MEM=y # CONFIG_SPI_NXP_FLEXSPI is not set # CONFIG_SPI_GPIO is not set # CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_MICROCHIP_CORE is not set # CONFIG_SPI_OC_TINY is not set CONFIG_SPI_PL022=y CONFIG_SPI_ROCKCHIP=y @@ -2720,6 +2732,7 @@ CONFIG_PINCTRL_SUN8I_H3_R=y # CONFIG_PINCTRL_SUN8I_V3S is not set # CONFIG_PINCTRL_SUN9I_A80 is not set # CONFIG_PINCTRL_SUN9I_A80_R is not set +# CONFIG_PINCTRL_SUN20I_D1 is not set CONFIG_PINCTRL_SUN50I_A64=y CONFIG_PINCTRL_SUN50I_A64_R=y # CONFIG_PINCTRL_SUN50I_A100 is not set @@ -2753,7 +2766,6 @@ CONFIG_GPIO_GENERIC_PLATFORM=y # CONFIG_GPIO_LOGICVC is not set CONFIG_GPIO_MB86S7X=y CONFIG_GPIO_PL061=y -# CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SIFIVE is not set # CONFIG_GPIO_SYSCON is not set CONFIG_GPIO_XGENE=y @@ -2877,7 +2889,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AD7314 is not set # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set @@ -2940,7 +2951,6 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_MAX6620 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_MAX6697 is not set # CONFIG_SENSORS_MAX31790 is not set @@ -3409,7 +3419,6 @@ CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_USB_GSPCA is not set # CONFIG_USB_PWC is not set # CONFIG_USB_S2255 is not set -# CONFIG_USB_STKWEBCAM is not set # CONFIG_VIDEO_USBTV is not set CONFIG_USB_VIDEO_CLASS=m # CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set @@ -3653,6 +3662,7 @@ CONFIG_VIDEO_IR_I2C=y # # Camera sensor devices # +# CONFIG_VIDEO_AR0521 is not set # CONFIG_VIDEO_HI556 is not set # CONFIG_VIDEO_HI846 is not set # CONFIG_VIDEO_HI847 is not set @@ -4181,6 +4191,7 @@ CONFIG_DRM_SIMPLE_BRIDGE=y # CONFIG_DRM_TOSHIBA_TC358767 is not set # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TI_DLPC3433 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set @@ -4200,7 +4211,9 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_HISI_KIRIN is not set +# CONFIG_DRM_LOGICVC is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_IMX_LCDIF is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_PANEL_MIPI_DBI is not set @@ -4328,7 +4341,9 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set +# CONFIG_SND_CTL_INPUT_VALIDATION is not set # CONFIG_SND_SEQUENCER is not set CONFIG_SND_DRIVERS=y # CONFIG_SND_DUMMY is not set @@ -4472,6 +4487,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES8328_I2C is not set # CONFIG_SND_SOC_ES8328_SPI is not set # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_HDA is not set # CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set @@ -4521,6 +4537,7 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TAS2562 is not set # CONFIG_SND_SOC_TAS2764 is not set # CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS2780 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set @@ -4725,6 +4742,7 @@ CONFIG_USB_HIDDEV=y # I2C HID support # # CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_ELAN is not set # CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -4897,6 +4915,7 @@ CONFIG_USB_HSIC_USB3503=y # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_ONBOARD_HUB is not set # # USB Physical Layer drivers @@ -5130,6 +5149,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_HYM8563 is not set # CONFIG_RTC_DRV_MAX6900 is not set CONFIG_RTC_DRV_MAX77686=y +# CONFIG_RTC_DRV_NCT3018Y is not set CONFIG_RTC_DRV_RK808=m # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set @@ -5348,6 +5368,7 @@ CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_HANTRO_SUNXI=y # CONFIG_VIDEO_MAX96712 is not set +# CONFIG_VIDEO_STKWEBCAM is not set CONFIG_VIDEO_SUNXI=y CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_STAGING_BOARD is not set @@ -5358,10 +5379,6 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_PI433 is not set # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set - -# -# VME Device Drivers -# # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set @@ -5398,7 +5415,6 @@ CONFIG_COMMON_CLK_PWM=y # CONFIG_COMMON_CLK_RS9_PCIE is not set # CONFIG_COMMON_CLK_VC5 is not set # CONFIG_COMMON_CLK_FIXED_MMIO is not set -# CONFIG_CLK_SUNXI is not set CONFIG_SUNXI_CCU=y CONFIG_SUN50I_A64_CCU=y # CONFIG_SUN50I_A100_CCU is not set @@ -5504,6 +5520,11 @@ CONFIG_SOC_BRCMSTB=y # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + # # i.MX SoC drivers # @@ -6072,6 +6093,7 @@ CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_CLK is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_SUN4I=y @@ -6098,6 +6120,7 @@ CONFIG_RESET_CONTROLLER=y CONFIG_RESET_SIMPLE=y CONFIG_RESET_SUNXI=y # CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_TI_TPS380X is not set # # PHY Subsystem @@ -6152,7 +6175,7 @@ CONFIG_RAS=y # # Android # -# CONFIG_ANDROID is not set +# CONFIG_ANDROID_BINDER_IPC is not set # end of Android # CONFIG_LIBNVDIMM is not set @@ -6607,6 +6630,7 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_XTS is not set # CONFIG_CRYPTO_KEYWRAP is not set # CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_HCTR2 is not set # CONFIG_CRYPTO_ESSIV is not set # @@ -6657,6 +6681,7 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_KHAZAD is not set CONFIG_CRYPTO_CHACHA20=m # CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_ARIA is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_SM4_GENERIC is not set # CONFIG_CRYPTO_TEA is not set @@ -6767,6 +6792,7 @@ CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y CONFIG_CRYPTO_LIB_POLY1305=y CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines @@ -6866,10 +6892,10 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y -CONFIG_STACK_HASH_ORDER=20 CONFIG_SBITMAP=y # end of Library routines +CONFIG_GENERIC_IOREMAP=y CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y # @@ -6965,6 +6991,7 @@ CONFIG_ARCH_HAS_DEBUG_WX=y CONFIG_GENERIC_PTDUMP=y # CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set From d78c8e4c1cf99c6b8ce38a22bf6d243de6c8835a Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Mon, 22 Aug 2022 13:28:58 +0000 Subject: [PATCH 14/29] linux (Allwinner arm): update .config for 6.0-rc5 --- projects/Allwinner/linux/linux.arm.conf | 61 +++++++++++++++++++------ 1 file changed, 46 insertions(+), 15 deletions(-) diff --git a/projects/Allwinner/linux/linux.arm.conf b/projects/Allwinner/linux/linux.arm.conf index 26a20447ac..d8d8def803 100644 --- a/projects/Allwinner/linux/linux.arm.conf +++ b/projects/Allwinner/linux/linux.arm.conf @@ -1,10 +1,10 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.19.2-rc1 Kernel Configuration +# Linux/arm 6.0.0-rc5 Kernel Configuration # -CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-12.1.0 (GCC) 12.1.0" +CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-12.2.0 (GCC) 12.2.0" CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=120100 +CONFIG_GCC_VERSION=120200 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y CONFIG_AS_VERSION=23900 @@ -13,7 +13,6 @@ CONFIG_LD_VERSION=23900 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y @@ -77,6 +76,8 @@ CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem @@ -158,6 +159,7 @@ CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y CONFIG_MEMCG_KMEM=y @@ -339,6 +341,7 @@ CONFIG_ARCH_MULTI_V6_V7=y # CONFIG_PLAT_SPEAR is not set # CONFIG_ARCH_STI is not set # CONFIG_ARCH_STM32 is not set +# CONFIG_ARCH_SUNPLUS is not set CONFIG_ARCH_SUNXI=y # CONFIG_MACH_SUN4I is not set # CONFIG_MACH_SUN5I is not set @@ -487,6 +490,7 @@ CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y # CONFIG_USE_OF=y CONFIG_ATAGS=y +# CONFIG_UNUSED_BOARD_FILES is not set # CONFIG_DEPRECATED_PARAM_STRUCT is not set CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZBOOT_ROM_BSS=0 @@ -574,6 +578,7 @@ CONFIG_SUSPEND_FREEZER=y CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y # CONFIG_PM_DEBUG is not set @@ -634,13 +639,14 @@ CONFIG_SECCOMP_FILTER=y CONFIG_HAVE_STACKPROTECTOR=y # CONFIG_STACKPROTECTOR is not set CONFIG_LTO_NONE=y -CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y @@ -660,7 +666,6 @@ CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_PHYS_TO_DMA=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_HAVE_ARCH_PFN_VALID=y @@ -1471,6 +1476,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_UBLK is not set # # NVME Support @@ -1499,6 +1505,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_SRAM is not set # CONFIG_XILINX_SDFEC is not set # CONFIG_OPEN_DICE is not set +# CONFIG_VCPU_STALL_DETECTOR is not set # CONFIG_C2PORT is not set # @@ -1696,6 +1703,7 @@ CONFIG_NET_VENDOR_HISILICON=y # CONFIG_HNS_ENET is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_WANGXUN is not set # CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set @@ -2202,7 +2210,6 @@ CONFIG_SERIAL_8250_DMA=y CONFIG_SERIAL_8250_NR_UARTS=8 CONFIG_SERIAL_8250_RUNTIME_UARTS=8 # CONFIG_SERIAL_8250_EXTENDED is not set -# CONFIG_SERIAL_8250_ASPEED_VUART is not set CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_DW=y @@ -2252,6 +2259,7 @@ CONFIG_DEVMEM=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set +CONFIG_RANDOM_TRUST_CPU=y # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # end of Character devices @@ -2340,6 +2348,7 @@ CONFIG_SPI_MASTER=y # CONFIG_SPI_NXP_FLEXSPI is not set # CONFIG_SPI_GPIO is not set # CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_MICROCHIP_CORE is not set # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_ROCKCHIP is not set # CONFIG_SPI_SC18IS602 is not set @@ -2428,6 +2437,7 @@ CONFIG_PINCTRL_SUN8I_H3_R=y # CONFIG_PINCTRL_SUN8I_V3S is not set # CONFIG_PINCTRL_SUN9I_A80 is not set # CONFIG_PINCTRL_SUN9I_A80_R is not set +# CONFIG_PINCTRL_SUN20I_D1 is not set # CONFIG_PINCTRL_SUN50I_A64 is not set # CONFIG_PINCTRL_SUN50I_A64_R is not set # CONFIG_PINCTRL_SUN50I_A100 is not set @@ -2460,7 +2470,6 @@ CONFIG_GPIO_CDEV_V1=y # CONFIG_GPIO_LOGICVC is not set # CONFIG_GPIO_MB86S7X is not set # CONFIG_GPIO_MPC8XXX is not set -# CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SIFIVE is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_XILINX is not set @@ -3099,7 +3108,6 @@ CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_USB_GSPCA is not set # CONFIG_USB_PWC is not set # CONFIG_USB_S2255 is not set -# CONFIG_USB_STKWEBCAM is not set # CONFIG_VIDEO_USBTV is not set CONFIG_USB_VIDEO_CLASS=m # CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set @@ -3346,6 +3354,7 @@ CONFIG_VIDEO_IR_I2C=y # # Camera sensor devices # +# CONFIG_VIDEO_AR0521 is not set # CONFIG_VIDEO_HI556 is not set # CONFIG_VIDEO_HI846 is not set # CONFIG_VIDEO_HI847 is not set @@ -3764,6 +3773,7 @@ CONFIG_DVB_SP2=m # # Graphics support # +CONFIG_APERTURE_HELPERS=y # CONFIG_IMX_IPUV3_CORE is not set CONFIG_DRM=y CONFIG_DRM_MIPI_DSI=y @@ -3877,6 +3887,7 @@ CONFIG_DRM_SIMPLE_BRIDGE=m # CONFIG_DRM_TOSHIBA_TC358767 is not set # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TI_DLPC3433 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set @@ -3895,7 +3906,9 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_STI is not set # CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_LOGICVC is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_IMX_LCDIF is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_PANEL_MIPI_DBI is not set @@ -3997,7 +4010,9 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set +# CONFIG_SND_CTL_INPUT_VALIDATION is not set # CONFIG_SND_SEQUENCER is not set CONFIG_SND_DRIVERS=y # CONFIG_SND_DUMMY is not set @@ -4140,6 +4155,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES8328_I2C is not set # CONFIG_SND_SOC_ES8328_SPI is not set # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_HDA is not set # CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set @@ -4188,6 +4204,7 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TAS2562 is not set # CONFIG_SND_SOC_TAS2764 is not set # CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS2780 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set @@ -4392,6 +4409,7 @@ CONFIG_USB_HIDDEV=y # I2C HID support # # CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_ELAN is not set # CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -4585,6 +4603,7 @@ CONFIG_USB_SERIAL=m # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_ONBOARD_HUB is not set # # USB Physical Layer drivers @@ -4792,6 +4811,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_DS1672 is not set # CONFIG_RTC_DRV_HYM8563 is not set # CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_NCT3018Y is not set # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set # CONFIG_RTC_DRV_ISL12022 is not set @@ -4998,6 +5018,7 @@ CONFIG_R8188EU=m CONFIG_STAGING_MEDIA=y # CONFIG_VIDEO_HANTRO is not set # CONFIG_VIDEO_MAX96712 is not set +# CONFIG_VIDEO_STKWEBCAM is not set CONFIG_VIDEO_SUNXI=y CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_STAGING_BOARD is not set @@ -5008,10 +5029,6 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_PI433 is not set # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set - -# -# VME Device Drivers -# # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set @@ -5110,6 +5127,11 @@ CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + # # i.MX SoC drivers # @@ -5668,6 +5690,7 @@ CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_CLK is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_SUN4I=y @@ -5691,6 +5714,7 @@ CONFIG_RESET_CONTROLLER=y CONFIG_RESET_SIMPLE=y CONFIG_RESET_SUNXI=y # CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_TI_TPS380X is not set # # PHY Subsystem @@ -5738,7 +5762,7 @@ CONFIG_ARM_PMU=y # # Android # -# CONFIG_ANDROID is not set +# CONFIG_ANDROID_BINDER_IPC is not set # end of Android # CONFIG_DAX is not set @@ -6149,6 +6173,7 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_XTS is not set # CONFIG_CRYPTO_KEYWRAP is not set # CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_HCTR2 is not set # CONFIG_CRYPTO_ESSIV is not set # @@ -6197,6 +6222,7 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_ARIA is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_SM4_GENERIC is not set # CONFIG_CRYPTO_TEA is not set @@ -6303,6 +6329,7 @@ CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y CONFIG_CRYPTO_LIB_POLY1305=y CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines @@ -6347,6 +6374,7 @@ CONFIG_XZ_DEC_BCJ=y CONFIG_DECOMPRESS_GZIP=y CONFIG_DECOMPRESS_ZSTD=y CONFIG_GENERIC_ALLOCATOR=y +CONFIG_XARRAY_MULTI=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y @@ -6356,6 +6384,8 @@ CONFIG_NEED_DMA_MAP_STATE=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_CMA=y # CONFIG_DMA_PERNUMA_CMA is not set @@ -6391,7 +6421,6 @@ CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_STACKDEPOT=y -CONFIG_STACK_HASH_ORDER=20 CONFIG_SBITMAP=y # end of Library routines @@ -6474,6 +6503,7 @@ CONFIG_SLUB_DEBUG=y # CONFIG_DEBUG_RODATA_TEST is not set # CONFIG_DEBUG_WX is not set # CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set @@ -6486,6 +6516,7 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_KMAP_LOCAL is not set # CONFIG_DEBUG_HIGHMEM is not set CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set From c58f90fb50a3124774542a59d24293c8ce22cdfd Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Mon, 22 Aug 2022 12:00:07 +0000 Subject: [PATCH 15/29] linux (Generic): update .config for 6.0-rc5 --- projects/Generic/linux/linux.x86_64.conf | 108 +++++++++++++++-------- 1 file changed, 73 insertions(+), 35 deletions(-) diff --git a/projects/Generic/linux/linux.x86_64.conf b/projects/Generic/linux/linux.x86_64.conf index 2d231fb45b..ead7f0aeaa 100644 --- a/projects/Generic/linux/linux.x86_64.conf +++ b/projects/Generic/linux/linux.x86_64.conf @@ -1,10 +1,10 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/x86 5.19.2-rc1 Kernel Configuration +# Linux/x86 6.0.0-rc5 Kernel Configuration # -CONFIG_CC_VERSION_TEXT="x86_64-libreelec-linux-gnu-gcc-12.1.0 (GCC) 12.1.0" +CONFIG_CC_VERSION_TEXT="x86_64-libreelec-linux-gnu-gcc-12.2.0 (GCC) 12.2.0" CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=120100 +CONFIG_GCC_VERSION=120200 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y CONFIG_AS_VERSION=23900 @@ -13,7 +13,6 @@ CONFIG_LD_VERSION=23900 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y @@ -89,6 +88,8 @@ CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem @@ -178,6 +179,7 @@ CONFIG_NUMA_BALANCING=y CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y CONFIG_MEMCG_KMEM=y @@ -419,7 +421,6 @@ CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0 CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 CONFIG_X86_PAT=y CONFIG_ARCH_USES_PG_UNCACHED=y -CONFIG_ARCH_RANDOM=y CONFIG_X86_UMIP=y CONFIG_CC_HAS_IBT=y CONFIG_X86_KERNEL_IBT=y @@ -485,6 +486,7 @@ CONFIG_SUSPEND_FREEZER=y CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y CONFIG_PM_DEBUG=y @@ -547,8 +549,8 @@ CONFIG_HAVE_ACPI_APEI_NMI=y # CONFIG_ACPI_PFRUT is not set CONFIG_ACPI_PCC=y # CONFIG_PMIC_OPREGION is not set -CONFIG_X86_PM_TIMER=y CONFIG_ACPI_PRMT=y +CONFIG_X86_PM_TIMER=y # # CPU Frequency scaling @@ -700,8 +702,8 @@ CONFIG_ARCH_SUPPORTS_LTO_CLANG=y CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y CONFIG_LTO_NONE=y CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_CONTEXT_TRACKING_OFFSTACK=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y +CONFIG_HAVE_CONTEXT_TRACKING_USER_OFFSTACK=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOVE_PUD=y @@ -716,6 +718,7 @@ CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y @@ -915,7 +918,6 @@ CONFIG_MIGRATION=y CONFIG_ARCH_ENABLE_THP_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_VIRT_TO_BUS=y CONFIG_MMU_NOTIFIER=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 @@ -940,7 +942,6 @@ CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y -CONFIG_ARCH_HAS_VM_GET_PAGE_PROT=y CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ARCH_HAS_ZONE_DMA_SET=y CONFIG_ZONE_DMA=y @@ -1630,7 +1631,6 @@ CONFIG_SYSFB=y # # EFI (Extensible Firmware Interface) Support # -CONFIG_EFI_VARS=y CONFIG_EFI_ESRT=y # CONFIG_EFI_FAKE_MEMMAP is not set CONFIG_EFI_DXE_MEM_ATTRIBUTES=y @@ -1676,7 +1676,6 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 # CONFIG_BLK_DEV_DRBD is not set CONFIG_BLK_DEV_NBD=y -# CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=16384 @@ -1684,6 +1683,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 # CONFIG_ATA_OVER_ETH is not set CONFIG_VIRTIO_BLK=y # CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_UBLK is not set # # NVME Support @@ -1695,6 +1695,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVME_HWMON=y # CONFIG_NVME_FC is not set # CONFIG_NVME_TCP is not set +# CONFIG_NVME_AUTH is not set # CONFIG_NVME_TARGET is not set # end of NVME Support @@ -1818,7 +1819,6 @@ CONFIG_SCSI_MVSAS=y # CONFIG_SCSI_MVSAS_DEBUG is not set # CONFIG_SCSI_MVSAS_TASKLET is not set # CONFIG_SCSI_MVUMI is not set -# CONFIG_SCSI_DPT_I2O is not set # CONFIG_SCSI_ADVANSYS is not set # CONFIG_SCSI_ARCMSR is not set # CONFIG_SCSI_ESAS2R is not set @@ -2083,6 +2083,7 @@ CONFIG_ICE=y CONFIG_ICE_HWTS=y # CONFIG_FM10K is not set CONFIG_IGC=y +# CONFIG_NET_VENDOR_WANGXUN is not set CONFIG_JME=y # CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y @@ -2227,7 +2228,6 @@ CONFIG_MDIO_DEVRES=y # # PCS device drivers # -# CONFIG_PCS_XPCS is not set # end of PCS device drivers CONFIG_PPP=m @@ -3031,6 +3031,7 @@ CONFIG_PINCTRL_ICELAKE=y CONFIG_PINCTRL_JASPERLAKE=y # CONFIG_PINCTRL_LAKEFIELD is not set CONFIG_PINCTRL_LEWISBURG=y +# CONFIG_PINCTRL_METEORLAKE is not set CONFIG_PINCTRL_SUNRISEPOINT=y CONFIG_PINCTRL_TIGERLAKE=y # end of Intel pinctrl drivers @@ -3635,7 +3636,6 @@ CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_USB_GSPCA is not set # CONFIG_USB_PWC is not set # CONFIG_USB_S2255 is not set -# CONFIG_USB_STKWEBCAM is not set CONFIG_VIDEO_USBTV=m CONFIG_USB_VIDEO_CLASS=m # CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set @@ -3959,6 +3959,7 @@ CONFIG_VIDEO_IR_I2C=m # # Camera sensor devices # +# CONFIG_VIDEO_AR0521 is not set # CONFIG_VIDEO_HI556 is not set # CONFIG_VIDEO_HI846 is not set # CONFIG_VIDEO_HI847 is not set @@ -4356,6 +4357,7 @@ CONFIG_DVB_DUMMY_FE=m # # Graphics support # +CONFIG_APERTURE_HELPERS=y CONFIG_AGP=y # CONFIG_AGP_AMD64 is not set CONFIG_AGP_INTEL=y @@ -4623,7 +4625,9 @@ CONFIG_SND_MAX_CARDS=32 CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set +# CONFIG_SND_CTL_INPUT_VALIDATION is not set CONFIG_SND_VMASTER=y CONFIG_SND_DMA_SGBUF=y CONFIG_SND_CTL_LED=m @@ -4778,6 +4782,7 @@ CONFIG_SND_SOC_ACPI=m CONFIG_SND_SOC_AMD_ACP=m CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH=m CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m +# CONFIG_SND_SOC_AMD_ST_ES8336_MACH is not set CONFIG_SND_SOC_AMD_ACP3x=m CONFIG_SND_SOC_AMD_RENOIR=m CONFIG_SND_SOC_AMD_RENOIR_MACH=m @@ -4785,6 +4790,7 @@ CONFIG_SND_SOC_AMD_RENOIR_MACH=m # CONFIG_SND_SOC_AMD_ACP6x is not set CONFIG_SND_AMD_ACP_CONFIG=m # CONFIG_SND_SOC_AMD_ACP_COMMON is not set +# CONFIG_SND_SOC_AMD_RPL_ACP6x is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set @@ -4829,6 +4835,28 @@ CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC=y CONFIG_SND_SOC_INTEL_SKYLAKE_COMMON=m CONFIG_SND_SOC_ACPI_INTEL_MATCH=m CONFIG_SND_SOC_INTEL_AVS=m + +# +# Intel AVS Machine drivers +# + +# +# Available DSP configurations +# +# CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_RT274 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_RT286 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_RT298 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567 is not set +# end of Intel AVS Machine drivers + CONFIG_SND_SOC_INTEL_MACH=y # CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES is not set CONFIG_SND_SOC_INTEL_HDA_DSP_COMMON=m @@ -4920,6 +4948,7 @@ CONFIG_SND_SOC_ES8316=m # CONFIG_SND_SOC_GTM601 is not set CONFIG_SND_SOC_HDAC_HDMI=m CONFIG_SND_SOC_HDAC_HDA=m +CONFIG_SND_SOC_HDA=m # CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set @@ -4969,6 +4998,7 @@ CONFIG_SND_SOC_SPDIF=m # CONFIG_SND_SOC_TAS2562 is not set # CONFIG_SND_SOC_TAS2764 is not set # CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS2780 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set @@ -5451,7 +5481,6 @@ CONFIG_LEDS_CLASS_FLASH=y # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_LP3952 is not set # CONFIG_LEDS_LP50XX is not set -# CONFIG_LEDS_CLEVO_MAIL is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set # CONFIG_LEDS_REGULATOR is not set @@ -5461,6 +5490,7 @@ CONFIG_LEDS_CLASS_FLASH=y # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TLC591XX is not set # CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_IS31FL319X is not set # # LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) @@ -5677,7 +5707,6 @@ CONFIG_VIRTIO=y CONFIG_VIRTIO_PCI_LIB=y CONFIG_VIRTIO_PCI_LIB_LEGACY=y CONFIG_VIRTIO_MENU=y -# CONFIG_VIRTIO_HARDEN_NOTIFICATION is not set CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_PCI_LEGACY=y CONFIG_VIRTIO_BALLOON=y @@ -5709,22 +5738,28 @@ CONFIG_VT6656=m # CONFIG_FB_SM750 is not set CONFIG_STAGING_MEDIA=y # CONFIG_INTEL_ATOMISP is not set -# CONFIG_VIDEO_ZORAN is not set -CONFIG_VIDEO_IPU3_IMGU=m CONFIG_DVB_AV7110_IR=y CONFIG_DVB_AV7110=m CONFIG_DVB_AV7110_OSD=y CONFIG_DVB_BUDGET_PATCH=m CONFIG_DVB_SP8870=m +CONFIG_VIDEO_IPU3_IMGU=m +# CONFIG_VIDEO_STKWEBCAM is not set +# CONFIG_VIDEO_ZORAN is not set # CONFIG_LTE_GDM724X is not set # CONFIG_FIREWIRE_SERIAL is not set # CONFIG_KS7010 is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_QLGE is not set - -# -# VME Device Drivers -# +# CONFIG_VME_BUS is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_SURFACE_PLATFORMS=y +# CONFIG_SURFACE_3_POWER_OPREGION is not set +# CONFIG_SURFACE_GPE is not set +# CONFIG_SURFACE_HOTPLUG is not set +# CONFIG_SURFACE_PRO3_BUTTON is not set +# CONFIG_SURFACE_AGGREGATOR is not set CONFIG_X86_PLATFORM_DEVICES=y CONFIG_ACPI_WMI=y CONFIG_WMI_BMOF=y @@ -5810,15 +5845,7 @@ CONFIG_INTEL_ATOMISP2_PM=y # CONFIG_INTEL_SCU_PLATFORM is not set # CONFIG_SIEMENS_SIMATIC_IPC is not set # CONFIG_WINMATE_FM07_KEYS is not set -CONFIG_PMC_ATOM=y -# CONFIG_CHROME_PLATFORMS is not set -# CONFIG_MELLANOX_PLATFORM is not set -CONFIG_SURFACE_PLATFORMS=y -# CONFIG_SURFACE_3_POWER_OPREGION is not set -# CONFIG_SURFACE_GPE is not set -# CONFIG_SURFACE_HOTPLUG is not set -# CONFIG_SURFACE_PRO3_BUTTON is not set -# CONFIG_SURFACE_AGGREGATOR is not set +CONFIG_P2SB=y CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y @@ -5903,6 +5930,11 @@ CONFIG_IRQ_REMAP=y # # end of NXP/Freescale QorIQ SoC drivers +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + # # i.MX SoC drivers # @@ -5931,7 +5963,6 @@ CONFIG_IRQ_REMAP=y # CONFIG_MEMORY is not set # CONFIG_IIO is not set # CONFIG_NTB is not set -# CONFIG_VME_BUS is not set # CONFIG_PWM is not set # @@ -5941,7 +5972,9 @@ CONFIG_IRQ_REMAP=y # CONFIG_IPACK_BUS is not set CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_SIMPLE is not set # CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_TI_TPS380X is not set # # PHY Subsystem @@ -5978,7 +6011,7 @@ CONFIG_RAS=y # # Android # -# CONFIG_ANDROID is not set +# CONFIG_ANDROID_BINDER_IPC is not set # end of Android # CONFIG_LIBNVDIMM is not set @@ -6402,6 +6435,7 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set # CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set # CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_HCTR2 is not set # CONFIG_CRYPTO_ESSIV is not set # @@ -6424,6 +6458,7 @@ CONFIG_CRYPTO_BLAKE2B=y CONFIG_CRYPTO_BLAKE2S_X86=y # CONFIG_CRYPTO_CRCT10DIF is not set CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_POLYVAL_CLMUL_NI is not set # CONFIG_CRYPTO_POLY1305 is not set CONFIG_CRYPTO_POLY1305_X86_64=m CONFIG_CRYPTO_MD4=y @@ -6468,6 +6503,7 @@ CONFIG_CRYPTO_DES3_EDE_X86_64=y # CONFIG_CRYPTO_CHACHA20 is not set CONFIG_CRYPTO_CHACHA20_X86_64=m # CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_ARIA is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set # CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set @@ -6570,6 +6606,7 @@ CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines @@ -6662,7 +6699,6 @@ CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y CONFIG_ARCH_HAS_COPY_MC=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y -CONFIG_STACK_HASH_ORDER=20 CONFIG_SBITMAP=y # end of Library routines @@ -6757,6 +6793,7 @@ CONFIG_ARCH_HAS_DEBUG_WX=y CONFIG_GENERIC_PTDUMP=y # CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set @@ -6937,6 +6974,7 @@ CONFIG_FTRACE_MCOUNT_USE_CC=y # CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set # CONFIG_PREEMPTIRQ_DELAY_TEST is not set # CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_RV is not set # CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_SAMPLE_FTRACE_DIRECT=y From 847df56ceb77d407b287aa8b42222f0ea8c7e1ef Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Mon, 22 Aug 2022 11:52:15 +0000 Subject: [PATCH 16/29] linux (NXP iMX6): update .config for 6.0-rc5 --- .../NXP/devices/iMX6/linux/linux.arm.conf | 84 ++++++++++++++----- 1 file changed, 63 insertions(+), 21 deletions(-) diff --git a/projects/NXP/devices/iMX6/linux/linux.arm.conf b/projects/NXP/devices/iMX6/linux/linux.arm.conf index 12af2541f4..80215a5ccd 100644 --- a/projects/NXP/devices/iMX6/linux/linux.arm.conf +++ b/projects/NXP/devices/iMX6/linux/linux.arm.conf @@ -1,10 +1,10 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.19.2-rc1 Kernel Configuration +# Linux/arm 6.0.0-rc5 Kernel Configuration # -CONFIG_CC_VERSION_TEXT="armv7a-libreelec-linux-gnueabihf-gcc-12.1.0 (GCC) 12.1.0" +CONFIG_CC_VERSION_TEXT="armv7a-libreelec-linux-gnueabihf-gcc-12.2.0 (GCC) 12.2.0" CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=120100 +CONFIG_GCC_VERSION=120200 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y CONFIG_AS_VERSION=23900 @@ -13,7 +13,6 @@ CONFIG_LD_VERSION=23900 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y @@ -77,6 +76,8 @@ CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem @@ -153,6 +154,7 @@ CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_CGROUPS=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set # CONFIG_MEMCG is not set # CONFIG_BLK_CGROUP is not set # CONFIG_CGROUP_SCHED is not set @@ -347,6 +349,7 @@ CONFIG_SOC_IMX6UL=y # CONFIG_PLAT_SPEAR is not set # CONFIG_ARCH_STI is not set # CONFIG_ARCH_STM32 is not set +# CONFIG_ARCH_SUNPLUS is not set # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_UNIPHIER is not set @@ -491,6 +494,7 @@ CONFIG_STACKPROTECTOR_PER_TASK=y # CONFIG_USE_OF=y CONFIG_ATAGS=y +# CONFIG_UNUSED_BOARD_FILES is not set # CONFIG_DEPRECATED_PARAM_STRUCT is not set CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZBOOT_ROM_BSS=0 @@ -578,6 +582,7 @@ CONFIG_SUSPEND_FREEZER=y CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y CONFIG_PM_DEBUG=y @@ -647,13 +652,14 @@ CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_LTO_NONE=y -CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y @@ -673,7 +679,6 @@ CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_PHYS_TO_DMA=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_HAVE_ARCH_PFN_VALID=y @@ -972,6 +977,7 @@ CONFIG_NET_DSA_TAG_EDSA=y # CONFIG_NET_DSA_TAG_QCA is not set # CONFIG_NET_DSA_TAG_RTL4_A is not set # CONFIG_NET_DSA_TAG_RTL8_4 is not set +# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set # CONFIG_NET_DSA_TAG_LAN9303 is not set # CONFIG_NET_DSA_TAG_SJA1105 is not set # CONFIG_NET_DSA_TAG_TRAILER is not set @@ -1442,13 +1448,13 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_DRBD is not set # CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=65536 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_UBLK is not set # # NVME Support @@ -1485,6 +1491,7 @@ CONFIG_SRAM_EXEC=y # CONFIG_XILINX_SDFEC is not set # CONFIG_HISI_HIKEY_USB is not set # CONFIG_OPEN_DICE is not set +# CONFIG_VCPU_STALL_DETECTOR is not set # CONFIG_C2PORT is not set # @@ -1699,17 +1706,16 @@ CONFIG_NLMON=m # CONFIG_NET_DSA_LANTIQ_GSWIP is not set # CONFIG_NET_DSA_MT7530 is not set # CONFIG_NET_DSA_MV88E6060 is not set -# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set -# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set +# CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON is not set CONFIG_NET_DSA_MV88E6XXX=y CONFIG_NET_DSA_MV88E6XXX_PTP=y # CONFIG_NET_DSA_MSCC_FELIX is not set # CONFIG_NET_DSA_MSCC_SEVILLE is not set # CONFIG_NET_DSA_AR9331 is not set +# CONFIG_NET_DSA_QCA8K is not set # CONFIG_NET_DSA_SJA1105 is not set # CONFIG_NET_DSA_XRS700X_I2C is not set # CONFIG_NET_DSA_XRS700X_MDIO is not set -# CONFIG_NET_DSA_QCA8K is not set # CONFIG_NET_DSA_REALTEK is not set # CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set # CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set @@ -1811,6 +1817,7 @@ CONFIG_IGB_HWMON=y # CONFIG_ICE is not set # CONFIG_FM10K is not set # CONFIG_IGC is not set +# CONFIG_NET_VENDOR_WANGXUN is not set # CONFIG_JME is not set # CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set @@ -1832,7 +1839,6 @@ CONFIG_NET_VENDOR_NI=y # CONFIG_NET_VENDOR_NATSEMI is not set CONFIG_NET_VENDOR_NETERION=y # CONFIG_S2IO is not set -# CONFIG_VXGE is not set CONFIG_NET_VENDOR_NETRONOME=y # CONFIG_NFP is not set CONFIG_NET_VENDOR_NVIDIA=y @@ -1990,7 +1996,6 @@ CONFIG_MDIO_GPIO=y # # PCS device drivers # -# CONFIG_PCS_XPCS is not set # end of PCS device drivers # CONFIG_PPP is not set @@ -2420,6 +2425,7 @@ CONFIG_DEVPORT=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set +CONFIG_RANDOM_TRUST_CPU=y # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # end of Character devices @@ -2544,6 +2550,7 @@ CONFIG_SPI_FSL_QUADSPI=y # CONFIG_SPI_GPIO is not set CONFIG_SPI_IMX=y # CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_MICROCHIP_CORE is not set # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_PXA2XX is not set # CONFIG_SPI_ROCKCHIP is not set @@ -2656,7 +2663,6 @@ CONFIG_GPIO_GENERIC=y # CONFIG_GPIO_MB86S7X is not set # CONFIG_GPIO_MPC8XXX is not set CONFIG_GPIO_MXC=y -# CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SIFIVE is not set # CONFIG_GPIO_SYSCON is not set CONFIG_GPIO_VF610=y @@ -3373,7 +3379,6 @@ CONFIG_USB_GSPCA=m # CONFIG_USB_STV06XX is not set # CONFIG_USB_PWC is not set # CONFIG_USB_S2255 is not set -# CONFIG_USB_STKWEBCAM is not set # CONFIG_VIDEO_USBTV is not set CONFIG_USB_VIDEO_CLASS=m # CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set @@ -3508,6 +3513,7 @@ CONFIG_VIDEO_IMX_VDOA=y # # Rockchip media platform drivers # +# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set # # Samsung media platform drivers @@ -3561,9 +3567,11 @@ CONFIG_VIDEO_IR_I2C=y # # Camera sensor devices # +# CONFIG_VIDEO_AR0521 is not set # CONFIG_VIDEO_HI556 is not set # CONFIG_VIDEO_HI846 is not set # CONFIG_VIDEO_HI847 is not set +# CONFIG_VIDEO_IMX208 is not set # CONFIG_VIDEO_IMX214 is not set # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set @@ -4043,6 +4051,7 @@ CONFIG_DRM_PANEL=y CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y +# CONFIG_DRM_PANEL_EBBG_FT8719 is not set # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set @@ -4139,6 +4148,7 @@ CONFIG_DRM_PANEL_BRIDGE=y CONFIG_DRM_TOSHIBA_TC358767=y # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TI_DLPC3433 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set @@ -4148,6 +4158,10 @@ CONFIG_DRM_TOSHIBA_TC358767=y # CONFIG_DRM_ANALOGIX_ANX7625 is not set # CONFIG_DRM_I2C_ADV7511 is not set # CONFIG_DRM_CDNS_MHDP8546 is not set +# CONFIG_DRM_IMX8QM_LDB is not set +# CONFIG_DRM_IMX8QXP_LDB is not set +# CONFIG_DRM_IMX8QXP_PIXEL_COMBINER is not set +# CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI is not set CONFIG_DRM_DW_HDMI=y CONFIG_DRM_DW_HDMI_AHB_AUDIO=y CONFIG_DRM_DW_HDMI_I2S_AUDIO=y @@ -4163,7 +4177,9 @@ CONFIG_DRM_IMX_LDB=y CONFIG_DRM_IMX_HDMI=y CONFIG_DRM_ETNAVIV=y CONFIG_DRM_ETNAVIV_THERMAL=y +# CONFIG_DRM_LOGICVC is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_IMX_LCDIF is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_BOCHS is not set # CONFIG_DRM_CIRRUS_QEMU is not set @@ -4323,7 +4339,9 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set +# CONFIG_SND_CTL_INPUT_VALIDATION is not set # CONFIG_SND_SEQUENCER is not set CONFIG_SND_DRIVERS=y # CONFIG_SND_DUMMY is not set @@ -4433,6 +4451,7 @@ CONFIG_SND_SOC_FSL_ESAI=y # CONFIG_SND_SOC_FSL_EASRC is not set CONFIG_SND_SOC_FSL_XCVR=y CONFIG_SND_SOC_FSL_AUD2HTX=y +CONFIG_SND_SOC_FSL_UTILS=y CONFIG_SND_SOC_IMX_PCM_DMA=y CONFIG_SND_SOC_IMX_AUDMUX=y CONFIG_SND_IMX_SOC=y @@ -4528,6 +4547,7 @@ CONFIG_SND_SOC_ES8328=y CONFIG_SND_SOC_ES8328_I2C=y CONFIG_SND_SOC_ES8328_SPI=y # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_HDA is not set # CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set @@ -4576,6 +4596,7 @@ CONFIG_SND_SOC_SGTL5000=y # CONFIG_SND_SOC_TAS2562 is not set # CONFIG_SND_SOC_TAS2764 is not set # CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS2780 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set @@ -4774,6 +4795,7 @@ CONFIG_USB_HID=y # I2C HID support # # CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_ELAN is not set # CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -4962,6 +4984,7 @@ CONFIG_USB_EHSET_TEST_FIXTURE=m # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_ONBOARD_HUB is not set # # USB Physical Layer drivers @@ -5244,6 +5267,7 @@ CONFIG_RTC_DRV_DS1307=y # CONFIG_RTC_DRV_DS1672 is not set # CONFIG_RTC_DRV_HYM8563 is not set # CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_NCT3018Y is not set # CONFIG_RTC_DRV_RS5C372 is not set CONFIG_RTC_DRV_ISL1208=y # CONFIG_RTC_DRV_ISL12022 is not set @@ -5388,7 +5412,6 @@ CONFIG_DMABUF_HEAPS_CMA=y # CONFIG_VFIO is not set # CONFIG_VIRT_DRIVERS is not set CONFIG_VIRTIO_MENU=y -# CONFIG_VIRTIO_HARDEN_NOTIFICATION is not set # CONFIG_VIRTIO_PCI is not set # CONFIG_VIRTIO_MMIO is not set # CONFIG_VDPA is not set @@ -5480,10 +5503,7 @@ CONFIG_R8188EU=m # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_QLGE is not set - -# -# VME Device Drivers -# +# CONFIG_VME_BUS is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set @@ -5589,6 +5609,11 @@ CONFIG_IOMMU_SUPPORT=y # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + # # i.MX SoC drivers # @@ -6137,11 +6162,11 @@ CONFIG_MPL3115=y # end of Temperature sensors # CONFIG_NTB is not set -# CONFIG_VME_BUS is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_CLK is not set # CONFIG_PWM_DWC is not set CONFIG_PWM_FSL_FTM=y # CONFIG_PWM_IMX1 is not set @@ -6166,7 +6191,9 @@ CONFIG_IMX_INTMUX=y # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_SIMPLE is not set # CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_TI_TPS380X is not set # # PHY Subsystem @@ -6214,7 +6241,7 @@ CONFIG_RAS=y # # Android # -# CONFIG_ANDROID is not set +# CONFIG_ANDROID_BINDER_IPC is not set # end of Android # CONFIG_DAX is not set @@ -6604,6 +6631,7 @@ CONFIG_CRYPTO_ECB=y CONFIG_CRYPTO_XTS=y # CONFIG_CRYPTO_KEYWRAP is not set # CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_HCTR2 is not set # CONFIG_CRYPTO_ESSIV is not set # @@ -6652,6 +6680,7 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_ARIA is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_SM4_GENERIC is not set # CONFIG_CRYPTO_TEA is not set @@ -6705,6 +6734,13 @@ CONFIG_CRYPTO_DEV_SAHARA=y # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set # CONFIG_CRYPTO_DEV_MXS_DCP is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_4XXX is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set +# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set # CONFIG_CRYPTO_DEV_SAFEXCEL is not set # CONFIG_CRYPTO_DEV_CCREE is not set # CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set @@ -6763,6 +6799,7 @@ CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines @@ -6804,6 +6841,7 @@ CONFIG_XZ_DEC_BCJ=y # CONFIG_XZ_DEC_TEST is not set CONFIG_DECOMPRESS_ZSTD=y CONFIG_GENERIC_ALLOCATOR=y +CONFIG_XARRAY_MULTI=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y @@ -6813,6 +6851,8 @@ CONFIG_NEED_DMA_MAP_STATE=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_CMA=y # CONFIG_DMA_PERNUMA_CMA is not set @@ -6940,6 +6980,7 @@ CONFIG_HAVE_KCSAN_COMPILER=y # CONFIG_DEBUG_RODATA_TEST is not set # CONFIG_DEBUG_WX is not set # CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set @@ -6952,6 +6993,7 @@ CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_KMAP_LOCAL is not set # CONFIG_DEBUG_HIGHMEM is not set CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set From 17d7547ebf24dedf1fac90e220e38ca67d4ca4d2 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Tue, 23 Aug 2022 11:40:48 +0000 Subject: [PATCH 17/29] linux (NXP iMX8): update .config for 6.0-rc4 --- .../NXP/devices/iMX8/linux/linux.aarch64.conf | 70 ++++++++++++++----- 1 file changed, 52 insertions(+), 18 deletions(-) diff --git a/projects/NXP/devices/iMX8/linux/linux.aarch64.conf b/projects/NXP/devices/iMX8/linux/linux.aarch64.conf index dce9c2d1b4..6fe4f0934e 100644 --- a/projects/NXP/devices/iMX8/linux/linux.aarch64.conf +++ b/projects/NXP/devices/iMX8/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.19.7-rc1 Kernel Configuration +# Linux/arm64 6.0.0-rc4 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-elf-gcc-12.2.0 (GCC) 12.2.0" CONFIG_CC_IS_GCC=y @@ -11,7 +11,6 @@ CONFIG_AS_VERSION=23900 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23900 CONFIG_LLD_VERSION=0 -CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y @@ -69,6 +68,8 @@ CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem @@ -149,6 +150,7 @@ CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y CONFIG_MEMCG_KMEM=y @@ -282,6 +284,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_ARCH_BCM2835 is not set # CONFIG_ARCH_BCM4908 is not set # CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BCMBCA is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_BITMAIN is not set # CONFIG_ARCH_BRCMSTB is not set @@ -296,6 +299,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_ARCH_MESON is not set # CONFIG_ARCH_MVEBU is not set CONFIG_ARCH_MXC=y +# CONFIG_ARCH_NPCM is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_RENESAS is not set @@ -451,7 +455,6 @@ CONFIG_AS_HAS_ARMV8_5=y # CONFIG_ARM64_BTI is not set CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y # CONFIG_ARM64_E0PD is not set -# CONFIG_ARCH_RANDOM is not set CONFIG_ARM64_AS_HAS_MTE=y # end of ARMv8.5 architectural features @@ -488,6 +491,7 @@ CONFIG_SUSPEND_FREEZER=y CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y # CONFIG_PM_DEBUG is not set @@ -510,16 +514,13 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y # CPU Idle # CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y # CONFIG_CPU_IDLE_GOV_LADDER is not set CONFIG_CPU_IDLE_GOV_MENU=y # CONFIG_CPU_IDLE_GOV_TEO is not set -CONFIG_DT_IDLE_STATES=y # # ARM CPU Idle Drivers # -CONFIG_ARM_CPUIDLE=y # CONFIG_ARM_PSCI_CPUIDLE is not set # end of ARM CPU Idle Drivers # end of CPU Idle @@ -567,6 +568,7 @@ CONFIG_CRYPTO_SHA512_ARM64_CE=m CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y CONFIG_CRYPTO_GHASH_ARM64_CE=y +# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y @@ -584,6 +586,7 @@ CONFIG_CRYPTO_AES_ARM64_BS=y CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y @@ -632,7 +635,7 @@ CONFIG_ARCH_SUPPORTS_LTO_CLANG=y CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y CONFIG_LTO_NONE=y CONFIG_ARCH_SUPPORTS_CFI_CLANG=y -CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOVE_PUD=y @@ -672,6 +675,7 @@ CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y +CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y # # GCOV-based kernel profiling @@ -881,9 +885,11 @@ CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y # CONFIG_MEMORY_FAILURE is not set +CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +CONFIG_THP_SWAP=y # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set @@ -895,7 +901,6 @@ CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y -CONFIG_ARCH_HAS_VM_GET_PAGE_PROT=y CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ARCH_HAS_ZONE_DMA_SET=y CONFIG_ZONE_DMA=y @@ -1643,6 +1648,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_UBLK is not set # # NVME Support @@ -1672,6 +1678,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_XILINX_SDFEC is not set # CONFIG_HISI_HIKEY_USB is not set # CONFIG_OPEN_DICE is not set +# CONFIG_VCPU_STALL_DETECTOR is not set # CONFIG_C2PORT is not set # @@ -1801,6 +1808,7 @@ CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_NET_VENDOR_HISILICON is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_WANGXUN is not set # CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set @@ -2314,7 +2322,6 @@ CONFIG_SERIAL_8250_NR_UARTS=1 CONFIG_SERIAL_8250_RUNTIME_UARTS=0 CONFIG_SERIAL_8250_EXTENDED=y # CONFIG_SERIAL_8250_MANY_PORTS is not set -# CONFIG_SERIAL_8250_ASPEED_VUART is not set CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_8250_DETECT_IRQ is not set # CONFIG_SERIAL_8250_RSA is not set @@ -2373,6 +2380,7 @@ CONFIG_DEVMEM=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set +CONFIG_RANDOM_TRUST_CPU=y # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # end of Character devices @@ -2473,6 +2481,7 @@ CONFIG_SPI_BITBANG=y # CONFIG_SPI_GPIO is not set CONFIG_SPI_IMX=y # CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_MICROCHIP_CORE is not set # CONFIG_SPI_OC_TINY is not set CONFIG_SPI_PL022=y # CONFIG_SPI_ROCKCHIP is not set @@ -2582,7 +2591,6 @@ CONFIG_GPIO_GENERIC_PLATFORM=y # CONFIG_GPIO_MB86S7X is not set CONFIG_GPIO_MXC=y # CONFIG_GPIO_PL061 is not set -# CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SIFIVE is not set # CONFIG_GPIO_SYSCON is not set CONFIG_GPIO_VF610=y @@ -3193,7 +3201,6 @@ CONFIG_DVB_CORE=m # Video4Linux options # CONFIG_VIDEO_V4L2_I2C=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_TUNER=m @@ -3239,7 +3246,6 @@ CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_USB_GSPCA is not set # CONFIG_USB_PWC is not set # CONFIG_USB_S2255 is not set -# CONFIG_USB_STKWEBCAM is not set CONFIG_VIDEO_USBTV=m CONFIG_USB_VIDEO_CLASS=m # CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set @@ -3473,6 +3479,7 @@ CONFIG_VIDEO_IR_I2C=m # # Camera sensor devices # +# CONFIG_VIDEO_AR0521 is not set # CONFIG_VIDEO_HI556 is not set # CONFIG_VIDEO_HI846 is not set # CONFIG_VIDEO_HI847 is not set @@ -3999,6 +4006,7 @@ CONFIG_DRM_FSL_LDB=m # CONFIG_DRM_TOSHIBA_TC358767 is not set # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TI_DLPC3433 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set @@ -4014,6 +4022,11 @@ CONFIG_DRM_CDNS_DP=y CONFIG_DRM_CDNS_AUDIO=y CONFIG_DRM_CDNS_HDMI_HDCP=y CONFIG_DRM_CDNS_HDMI_CEC=y +# CONFIG_DRM_IMX8QM_LDB is not set +# CONFIG_DRM_IMX8QXP_LDB is not set +# CONFIG_DRM_IMX8QXP_PIXEL_COMBINER is not set +# CONFIG_DRM_IMX8QXP_PIXEL_LINK is not set +# CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI is not set # end of Display Interface Bridges CONFIG_DRM_IMX_DCSS=y @@ -4021,7 +4034,9 @@ CONFIG_DRM_IMX_CDNS_MHDP=y CONFIG_DRM_ETNAVIV=y CONFIG_DRM_ETNAVIV_THERMAL=y # CONFIG_DRM_HISI_KIRIN is not set +# CONFIG_DRM_LOGICVC is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_IMX_LCDIF is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_PANEL_MIPI_DBI is not set @@ -4138,7 +4153,9 @@ CONFIG_SND_MAX_CARDS=32 CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set +# CONFIG_SND_CTL_INPUT_VALIDATION is not set # CONFIG_SND_SEQUENCER is not set CONFIG_SND_DRIVERS=y # CONFIG_SND_DUMMY is not set @@ -4182,6 +4199,7 @@ CONFIG_SND_SOC_FSL_ESAI=y # CONFIG_SND_SOC_FSL_MICFIL is not set CONFIG_SND_SOC_FSL_XCVR=m CONFIG_SND_SOC_FSL_AUD2HTX=y +CONFIG_SND_SOC_FSL_UTILS=y CONFIG_SND_SOC_IMX_PCM_DMA=y CONFIG_SND_SOC_IMX_AUDMUX=y CONFIG_SND_IMX_SOC=y @@ -4276,6 +4294,7 @@ CONFIG_SND_SOC_ES8328=y CONFIG_SND_SOC_ES8328_I2C=y CONFIG_SND_SOC_ES8328_SPI=y # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_HDA is not set # CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set @@ -4325,6 +4344,7 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TAS2562 is not set # CONFIG_SND_SOC_TAS2764 is not set # CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS2780 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set @@ -4531,6 +4551,7 @@ CONFIG_USB_HIDDEV=y # I2C HID support # # CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_ELAN is not set # CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -4733,6 +4754,7 @@ CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_ONBOARD_HUB is not set # # USB Physical Layer drivers @@ -4952,6 +4974,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_DS1672 is not set # CONFIG_RTC_DRV_HYM8563 is not set # CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_NCT3018Y is not set # CONFIG_RTC_DRV_RK808 is not set # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set @@ -5182,6 +5205,7 @@ CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_HANTRO_IMX8M=y # CONFIG_VIDEO_IMX_MEDIA is not set # CONFIG_VIDEO_MAX96712 is not set +# CONFIG_VIDEO_STKWEBCAM is not set # CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set # CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set @@ -5190,16 +5214,13 @@ CONFIG_VIDEO_HANTRO_IMX8M=y # CONFIG_PI433 is not set # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set - -# -# VME Device Drivers -# # CONFIG_GOLDFISH is not set CONFIG_CHROME_PLATFORMS=y CONFIG_CROS_EC=y # CONFIG_CROS_EC_I2C is not set # CONFIG_CROS_EC_SPI is not set CONFIG_CROS_EC_PROTO=y +# CONFIG_CROS_KBD_LED_BACKLIGHT is not set CONFIG_CROS_EC_CHARDEV=y CONFIG_CROS_EC_LIGHTBAR=y CONFIG_CROS_EC_VBC=y @@ -5335,6 +5356,11 @@ CONFIG_FSL_GUTS=y # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + # # i.MX SoC drivers # @@ -5893,6 +5919,7 @@ CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_CLK is not set # CONFIG_PWM_CROS_EC is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_IMX1 is not set @@ -5920,7 +5947,9 @@ CONFIG_IMX_INTMUX=y # CONFIG_IPACK_BUS is not set CONFIG_RESET_CONTROLLER=y CONFIG_RESET_IMX7=y +# CONFIG_RESET_SIMPLE is not set # CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_TI_TPS380X is not set # # PHY Subsystem @@ -5941,6 +5970,7 @@ CONFIG_GENERIC_PHY=y # CONFIG_PHY_CADENCE_SIERRA is not set # CONFIG_PHY_CADENCE_SALVO is not set CONFIG_PHY_FSL_IMX8MQ_USB=y +# CONFIG_PHY_MIXEL_LVDS_PHY is not set # CONFIG_PHY_MIXEL_MIPI_DPHY is not set CONFIG_PHY_FSL_IMX8M_PCIE=y # CONFIG_PHY_PXA_28NM_HSIC is not set @@ -5972,7 +6002,7 @@ CONFIG_FSL_IMX8_DDR_PMU=y # # Android # -# CONFIG_ANDROID is not set +# CONFIG_ANDROID_BINDER_IPC is not set # end of Android # CONFIG_LIBNVDIMM is not set @@ -6385,6 +6415,7 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_XTS is not set # CONFIG_CRYPTO_KEYWRAP is not set # CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_HCTR2 is not set # CONFIG_CRYPTO_ESSIV is not set # @@ -6433,6 +6464,7 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_KHAZAD is not set CONFIG_CRYPTO_CHACHA20=y # CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_ARIA is not set # CONFIG_CRYPTO_SERPENT is not set CONFIG_CRYPTO_SM4=y # CONFIG_CRYPTO_SM4_GENERIC is not set @@ -6536,6 +6568,7 @@ CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines @@ -6630,10 +6663,10 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y -CONFIG_STACK_HASH_ORDER=20 CONFIG_SBITMAP=y # end of Library routines +CONFIG_GENERIC_IOREMAP=y CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y # @@ -6723,6 +6756,7 @@ CONFIG_ARCH_HAS_DEBUG_WX=y CONFIG_GENERIC_PTDUMP=y # CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set From b5d3c5cf404c6667d696591640bf764c79ec9b99 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Mon, 22 Aug 2022 11:52:15 +0000 Subject: [PATCH 18/29] linux (Qualcomm): update .config for 6.0-rc3 --- .../Dragonboard/linux/linux.aarch64.conf | 79 +++++++++++++++---- 1 file changed, 62 insertions(+), 17 deletions(-) diff --git a/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf b/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf index 007bf2991c..12762df83d 100644 --- a/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf +++ b/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.19.7-rc1 Kernel Configuration +# Linux/arm64 6.0.0-rc3 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-elf-gcc-12.2.0 (GCC) 12.2.0" CONFIG_CC_IS_GCC=y @@ -11,7 +11,6 @@ CONFIG_AS_VERSION=23900 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23900 CONFIG_LLD_VERSION=0 -CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y @@ -70,6 +69,8 @@ CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem @@ -161,6 +162,7 @@ CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y @@ -293,6 +295,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_ARCH_BCM2835 is not set # CONFIG_ARCH_BCM4908 is not set # CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BCMBCA is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_BITMAIN is not set # CONFIG_ARCH_BRCMSTB is not set @@ -307,6 +310,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_ARCH_MESON is not set # CONFIG_ARCH_MVEBU is not set # CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_NPCM is not set CONFIG_ARCH_QCOM=y # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_RENESAS is not set @@ -463,7 +467,6 @@ CONFIG_AS_HAS_ARMV8_5=y # CONFIG_ARM64_BTI is not set CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y # CONFIG_ARM64_E0PD is not set -# CONFIG_ARCH_RANDOM is not set CONFIG_ARM64_AS_HAS_MTE=y # end of ARMv8.5 architectural features @@ -501,6 +504,7 @@ CONFIG_SUSPEND_FREEZER=y CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y # CONFIG_PM_DEBUG is not set @@ -523,16 +527,13 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y # CPU Idle # CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y # CONFIG_CPU_IDLE_GOV_LADDER is not set CONFIG_CPU_IDLE_GOV_MENU=y # CONFIG_CPU_IDLE_GOV_TEO is not set -CONFIG_DT_IDLE_STATES=y # # ARM CPU Idle Drivers # -CONFIG_ARM_CPUIDLE=y # CONFIG_ARM_PSCI_CPUIDLE is not set # end of ARM CPU Idle Drivers # end of CPU Idle @@ -579,6 +580,7 @@ CONFIG_ACPI_SPCR_TABLE=y CONFIG_ACPI_AC=y CONFIG_ACPI_BATTERY=y CONFIG_ACPI_BUTTON=y +# CONFIG_ACPI_VIDEO is not set CONFIG_ACPI_FAN=y # CONFIG_ACPI_TAD is not set # CONFIG_ACPI_DOCK is not set @@ -604,6 +606,7 @@ CONFIG_ACPI_IORT=y CONFIG_ACPI_GTDT=y CONFIG_ACPI_PPTT=y # CONFIG_PMIC_OPREGION is not set +CONFIG_ACPI_PRMT=y CONFIG_IRQ_BYPASS_MANAGER=y CONFIG_HAVE_KVM=y CONFIG_VIRTUALIZATION=y @@ -620,6 +623,7 @@ CONFIG_CRYPTO_SHA512_ARM64_CE=y # CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set # CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_POLYVAL_ARM64_CE=y CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y @@ -640,6 +644,7 @@ CONFIG_KEXEC_CORE=y CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y @@ -688,7 +693,7 @@ CONFIG_ARCH_SUPPORTS_LTO_CLANG=y CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y CONFIG_LTO_NONE=y CONFIG_ARCH_SUPPORTS_CFI_CLANG=y -CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOVE_PUD=y @@ -729,6 +734,7 @@ CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y +CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y # # GCOV-based kernel profiling @@ -873,6 +879,7 @@ CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y # CONFIG_MEMORY_FAILURE is not set +CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set @@ -887,7 +894,6 @@ CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y -CONFIG_ARCH_HAS_VM_GET_PAGE_PROT=y CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y @@ -1841,7 +1847,6 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_DRBD is not set CONFIG_BLK_DEV_NBD=m -# CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set @@ -1849,6 +1854,7 @@ CONFIG_XEN_BLKDEV_FRONTEND=y # CONFIG_XEN_BLKDEV_BACKEND is not set CONFIG_VIRTIO_BLK=y # CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_UBLK is not set # # NVME Support @@ -1887,6 +1893,7 @@ CONFIG_SRAM=y # CONFIG_XILINX_SDFEC is not set # CONFIG_HISI_HIKEY_USB is not set # CONFIG_OPEN_DICE is not set +# CONFIG_VCPU_STALL_DETECTOR is not set # CONFIG_C2PORT is not set # @@ -1992,6 +1999,7 @@ CONFIG_SCSI_HISI_SAS=y # CONFIG_SCSI_MPI3MR is not set # CONFIG_SCSI_SMARTPQI is not set # CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_MYRB is not set # CONFIG_SCSI_MYRS is not set # CONFIG_XEN_SCSI_FRONTEND is not set @@ -2253,6 +2261,7 @@ CONFIG_IGBVF=y # CONFIG_ICE is not set # CONFIG_FM10K is not set # CONFIG_IGC is not set +# CONFIG_NET_VENDOR_WANGXUN is not set # CONFIG_JME is not set # CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y @@ -2290,7 +2299,6 @@ CONFIG_NET_VENDOR_NATSEMI=y # CONFIG_NS83820 is not set CONFIG_NET_VENDOR_NETERION=y # CONFIG_S2IO is not set -# CONFIG_VXGE is not set CONFIG_NET_VENDOR_NETRONOME=y # CONFIG_NFP is not set CONFIG_NET_VENDOR_8390=y @@ -2826,7 +2834,6 @@ CONFIG_SERIAL_8250_EXAR=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_8250_EXTENDED is not set -# CONFIG_SERIAL_8250_ASPEED_VUART is not set CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_DW=y @@ -2893,6 +2900,7 @@ CONFIG_DEVPORT=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set +CONFIG_RANDOM_TRUST_CPU=y # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # end of Character devices @@ -3020,6 +3028,7 @@ CONFIG_SPI_MEM=y # CONFIG_SPI_NXP_FLEXSPI is not set # CONFIG_SPI_GPIO is not set # CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_MICROCHIP_CORE is not set # CONFIG_SPI_OC_TINY is not set CONFIG_SPI_PL022=y # CONFIG_SPI_PXA2XX is not set @@ -3109,6 +3118,7 @@ CONFIG_PINCTRL_MSM8960=y # CONFIG_PINCTRL_MDM9607 is not set CONFIG_PINCTRL_MDM9615=y CONFIG_PINCTRL_MSM8X74=y +# CONFIG_PINCTRL_MSM8909 is not set CONFIG_PINCTRL_MSM8916=y # CONFIG_PINCTRL_MSM8953 is not set # CONFIG_PINCTRL_MSM8976 is not set @@ -3130,6 +3140,7 @@ CONFIG_PINCTRL_QCOM_SSBI_PMIC=y # CONFIG_PINCTRL_SM6115 is not set # CONFIG_PINCTRL_SM6125 is not set # CONFIG_PINCTRL_SM6350 is not set +# CONFIG_PINCTRL_SM6375 is not set # CONFIG_PINCTRL_SDX65 is not set # CONFIG_PINCTRL_SM8150 is not set # CONFIG_PINCTRL_SM8250 is not set @@ -3169,7 +3180,6 @@ CONFIG_GPIO_GENERIC_PLATFORM=y # CONFIG_GPIO_LOGICVC is not set # CONFIG_GPIO_MB86S7X is not set CONFIG_GPIO_PL061=y -# CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SIFIVE is not set # CONFIG_GPIO_SYSCON is not set CONFIG_GPIO_XGENE=y @@ -3618,7 +3628,6 @@ CONFIG_MEDIA_CONTROLLER=y # Video4Linux options # CONFIG_VIDEO_V4L2_I2C=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEOBUF_GEN=m @@ -3701,7 +3710,6 @@ CONFIG_USB_PWC=m # CONFIG_USB_PWC_DEBUG is not set CONFIG_USB_PWC_INPUT_EVDEV=y CONFIG_USB_S2255=m -CONFIG_USB_STKWEBCAM=m # CONFIG_VIDEO_USBTV is not set CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y @@ -3726,6 +3734,7 @@ CONFIG_VIDEO_IR_I2C=y # # Camera sensor devices # +# CONFIG_VIDEO_AR0521 is not set # CONFIG_VIDEO_HI556 is not set # CONFIG_VIDEO_HI846 is not set # CONFIG_VIDEO_HI847 is not set @@ -4002,6 +4011,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y +# CONFIG_DRM_PANEL_EBBG_FT8719 is not set # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set @@ -4096,6 +4106,7 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_TOSHIBA_TC358767 is not set # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TI_DLPC3433 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set @@ -4112,7 +4123,9 @@ CONFIG_DRM_I2C_ADV7511_CEC=y # CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_HISI_HIBMC is not set # CONFIG_DRM_HISI_KIRIN is not set +# CONFIG_DRM_LOGICVC is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_IMX_LCDIF is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_BOCHS is not set # CONFIG_DRM_CIRRUS_QEMU is not set @@ -4258,7 +4271,9 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set +# CONFIG_SND_CTL_INPUT_VALIDATION is not set # CONFIG_SND_SEQUENCER is not set CONFIG_SND_DRIVERS=y # CONFIG_SND_DUMMY is not set @@ -4461,6 +4476,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES8328_I2C is not set # CONFIG_SND_SOC_ES8328_SPI is not set # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_HDA is not set # CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set @@ -4510,6 +4526,7 @@ CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y # CONFIG_SND_SOC_TAS2562 is not set # CONFIG_SND_SOC_TAS2764 is not set # CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS2780 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set @@ -4711,6 +4728,7 @@ CONFIG_USB_HID=y # # CONFIG_I2C_HID_ACPI is not set # CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_ELAN is not set # CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -4936,6 +4954,7 @@ CONFIG_USB_HSIC_USB3503=y # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_ONBOARD_HUB is not set # # USB Physical Layer drivers @@ -5215,6 +5234,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_HYM8563 is not set # CONFIG_RTC_DRV_MAX6900 is not set CONFIG_RTC_DRV_MAX77686=y +# CONFIG_RTC_DRV_NCT3018Y is not set # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set # CONFIG_RTC_DRV_ISL12022 is not set @@ -5524,6 +5544,7 @@ CONFIG_MSM_MMCC_8996=y # CONFIG_SDX_GCC_55 is not set # CONFIG_SDX_GCC_65 is not set # CONFIG_SM_CAMCC_8250 is not set +# CONFIG_SM_CAMCC_8450 is not set # CONFIG_SM_GCC_6115 is not set # CONFIG_SM_GCC_6125 is not set # CONFIG_SM_GCC_6350 is not set @@ -5534,6 +5555,7 @@ CONFIG_MSM_MMCC_8996=y # CONFIG_SM_GPUCC_6350 is not set # CONFIG_SM_GPUCC_8150 is not set # CONFIG_SM_GPUCC_8250 is not set +# CONFIG_SM_GPUCC_8350 is not set # CONFIG_SM_VIDEOCC_8150 is not set # CONFIG_SM_VIDEOCC_8250 is not set # CONFIG_SPMI_PMIC_CLKDIV is not set @@ -5592,6 +5614,7 @@ CONFIG_ARM_SMMU=y # CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y CONFIG_ARM_SMMU_QCOM=y +# CONFIG_ARM_SMMU_QCOM_DEBUG is not set # CONFIG_ARM_SMMU_V3 is not set CONFIG_QCOM_IOMMU=y # CONFIG_VIRTIO_IOMMU is not set @@ -5648,6 +5671,12 @@ CONFIG_RPMSG_QCOM_SMD=y # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers +# +# fujitsu SoC drivers +# +# CONFIG_A64FX_DIAG is not set +# end of fujitsu SoC drivers + # # i.MX SoC drivers # @@ -5683,6 +5712,7 @@ CONFIG_QCOM_SPM=y CONFIG_QCOM_STATS=y CONFIG_QCOM_WCNSS_CTRL=y # CONFIG_QCOM_APR is not set +# CONFIG_QCOM_ICC_BWMON is not set # end of Qualcomm SoC drivers # CONFIG_SOC_TI is not set @@ -5820,6 +5850,7 @@ CONFIG_IIO=y # CONFIG_MCP3422 is not set # CONFIG_MCP3911 is not set # CONFIG_NAU7802 is not set +# CONFIG_QCOM_SPMI_RRADC is not set # CONFIG_QCOM_SPMI_IADC is not set # CONFIG_QCOM_SPMI_VADC is not set # CONFIG_QCOM_SPMI_ADC5 is not set @@ -6217,11 +6248,11 @@ CONFIG_IIO=y # end of Temperature sensors # CONFIG_NTB is not set -# CONFIG_VME_BUS is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_CLK is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set @@ -6250,6 +6281,7 @@ CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_QCOM_AOSS is not set # CONFIG_RESET_QCOM_PDC is not set # CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_TI_TPS380X is not set # # PHY Subsystem @@ -6311,6 +6343,7 @@ CONFIG_ARM_PMU_ACPI=y # CONFIG_ARM_DMC620_PMU is not set # CONFIG_HISI_PMU is not set # CONFIG_HISI_PCIE_PMU is not set +# CONFIG_HNS3_PMU is not set # end of Performance monitor support CONFIG_RAS=y @@ -6319,7 +6352,7 @@ CONFIG_RAS=y # # Android # -# CONFIG_ANDROID is not set +# CONFIG_ANDROID_BINDER_IPC is not set # end of Android # CONFIG_LIBNVDIMM is not set @@ -6739,6 +6772,7 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_XTS is not set # CONFIG_CRYPTO_KEYWRAP is not set # CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_HCTR2 is not set # CONFIG_CRYPTO_ESSIV is not set # @@ -6759,6 +6793,7 @@ CONFIG_CRYPTO_BLAKE2B=y CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_CRC64_ROCKSOFT=y CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_POLYVAL=y # CONFIG_CRYPTO_POLY1305 is not set CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y @@ -6788,6 +6823,7 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_ARIA is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_SM4_GENERIC is not set # CONFIG_CRYPTO_TEA is not set @@ -6826,6 +6862,13 @@ CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set # CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_4XXX is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set +# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set # CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set # CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set # CONFIG_CRYPTO_DEV_QCE is not set @@ -6897,6 +6940,7 @@ CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y CONFIG_CRYPTO_LIB_POLY1305=y CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines @@ -7001,10 +7045,10 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y -CONFIG_STACK_HASH_ORDER=20 CONFIG_SBITMAP=y # end of Library routines +CONFIG_GENERIC_IOREMAP=y CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y # @@ -7096,6 +7140,7 @@ CONFIG_ARCH_HAS_DEBUG_WX=y CONFIG_GENERIC_PTDUMP=y # CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set From 7f2ac00ea4fda48d91684db70077c9bd158e934b Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Tue, 23 Aug 2022 09:32:05 +0000 Subject: [PATCH 19/29] linux (Rockchip RK3288): update .config for 6.0-rc5 --- .../RK3288/linux/default/linux.arm.conf | 72 +++++++++++++------ 1 file changed, 50 insertions(+), 22 deletions(-) diff --git a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf index 846516e46b..f4a463411c 100644 --- a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf +++ b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf @@ -1,10 +1,10 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.19.2-rc1 Kernel Configuration +# Linux/arm 6.0.0-rc5 Kernel Configuration # -CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-12.1.0 (GCC) 12.1.0" +CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-12.2.0 (GCC) 12.2.0" CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=120100 +CONFIG_GCC_VERSION=120200 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y CONFIG_AS_VERSION=23900 @@ -13,7 +13,6 @@ CONFIG_LD_VERSION=23900 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y @@ -76,6 +75,8 @@ CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem @@ -158,6 +159,7 @@ CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y CONFIG_MEMCG_KMEM=y @@ -337,6 +339,7 @@ CONFIG_ARCH_ROCKCHIP=y # CONFIG_PLAT_SPEAR is not set # CONFIG_ARCH_STI is not set # CONFIG_ARCH_STM32 is not set +# CONFIG_ARCH_SUNPLUS is not set # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_UNIPHIER is not set @@ -481,6 +484,7 @@ CONFIG_STACKPROTECTOR_PER_TASK=y # CONFIG_USE_OF=y CONFIG_ATAGS=y +# CONFIG_UNUSED_BOARD_FILES is not set # CONFIG_DEPRECATED_PARAM_STRUCT is not set CONFIG_ZBOOT_ROM_TEXT=0 CONFIG_ZBOOT_ROM_BSS=0 @@ -568,6 +572,7 @@ CONFIG_SUSPEND_FREEZER=y CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y # CONFIG_PM_DEBUG is not set @@ -643,13 +648,14 @@ CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_LTO_NONE=y -CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y @@ -669,7 +675,6 @@ CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_PHYS_TO_DMA=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_HAVE_ARCH_PFN_VALID=y @@ -954,6 +959,7 @@ CONFIG_NET_DSA_TAG_BRCM_PREPEND=m # CONFIG_NET_DSA_TAG_QCA is not set # CONFIG_NET_DSA_TAG_RTL4_A is not set # CONFIG_NET_DSA_TAG_RTL8_4 is not set +# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set # CONFIG_NET_DSA_TAG_LAN9303 is not set # CONFIG_NET_DSA_TAG_SJA1105 is not set # CONFIG_NET_DSA_TAG_TRAILER is not set @@ -1185,6 +1191,7 @@ CONFIG_ARM_SCMI_HAVE_SHMEM=y CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y # CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set CONFIG_ARM_SCMI_POWER_DOMAIN=m +# CONFIG_ARM_SCMI_POWER_CONTROL is not set # end of ARM System Control and Management Interface Protocol CONFIG_ARM_SCPI_PROTOCOL=m @@ -1337,6 +1344,7 @@ CONFIG_BLK_DEV_RAM_SIZE=65536 # CONFIG_ATA_OVER_ETH is not set CONFIG_VIRTIO_BLK=y # CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_UBLK is not set # # NVME Support @@ -1369,6 +1377,7 @@ CONFIG_ISL29003=y # CONFIG_XILINX_SDFEC is not set # CONFIG_HISI_HIKEY_USB is not set # CONFIG_OPEN_DICE is not set +# CONFIG_VCPU_STALL_DETECTOR is not set # CONFIG_C2PORT is not set # @@ -1484,14 +1493,13 @@ CONFIG_NET_DSA_BCM_SF2=m # CONFIG_NET_DSA_LANTIQ_GSWIP is not set # CONFIG_NET_DSA_MT7530 is not set # CONFIG_NET_DSA_MV88E6060 is not set -# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set -# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set +# CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON is not set # CONFIG_NET_DSA_MV88E6XXX is not set # CONFIG_NET_DSA_AR9331 is not set +# CONFIG_NET_DSA_QCA8K is not set # CONFIG_NET_DSA_SJA1105 is not set # CONFIG_NET_DSA_XRS700X_I2C is not set # CONFIG_NET_DSA_XRS700X_MDIO is not set -# CONFIG_NET_DSA_QCA8K is not set # CONFIG_NET_DSA_REALTEK is not set # CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set # CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set @@ -1521,6 +1529,7 @@ CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_NET_VENDOR_HISILICON is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_WANGXUN is not set # CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set @@ -2041,7 +2050,6 @@ CONFIG_SERIAL_8250_NR_UARTS=5 CONFIG_SERIAL_8250_RUNTIME_UARTS=5 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y -# CONFIG_SERIAL_8250_ASPEED_VUART is not set CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_8250_DETECT_IRQ is not set # CONFIG_SERIAL_8250_RSA is not set @@ -2100,6 +2108,7 @@ CONFIG_DEVMEM=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set +CONFIG_RANDOM_TRUST_CPU=y # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # end of Character devices @@ -2195,6 +2204,7 @@ CONFIG_SPI_CADENCE=y # CONFIG_SPI_NXP_FLEXSPI is not set CONFIG_SPI_GPIO=m # CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_MICROCHIP_CORE is not set # CONFIG_SPI_OC_TINY is not set CONFIG_SPI_PL022=y CONFIG_SPI_ROCKCHIP=m @@ -2298,7 +2308,6 @@ CONFIG_GPIO_DWAPB=y # CONFIG_GPIO_MPC8XXX is not set # CONFIG_GPIO_PL061 is not set CONFIG_GPIO_ROCKCHIP=y -# CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SYSCON=y CONFIG_GPIO_XILINX=y @@ -2423,7 +2432,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AD7314 is not set # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set @@ -2486,7 +2494,6 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_MAX6620 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_MAX6697 is not set # CONFIG_SENSORS_MAX31790 is not set @@ -2942,7 +2949,6 @@ CONFIG_DVB_CORE=y # Video4Linux options # CONFIG_VIDEO_V4L2_I2C=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_TUNER=m @@ -3043,7 +3049,6 @@ CONFIG_USB_GSPCA=m # CONFIG_USB_STV06XX is not set # CONFIG_USB_PWC is not set # CONFIG_USB_S2255 is not set -# CONFIG_USB_STKWEBCAM is not set # CONFIG_VIDEO_USBTV is not set CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y @@ -3289,6 +3294,7 @@ CONFIG_VIDEO_IR_I2C=y # # Camera sensor devices # +# CONFIG_VIDEO_AR0521 is not set # CONFIG_VIDEO_HI556 is not set # CONFIG_VIDEO_HI846 is not set # CONFIG_VIDEO_HI847 is not set @@ -3706,6 +3712,7 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_TOSHIBA_TC358767 is not set # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TI_DLPC3433 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set @@ -3724,7 +3731,9 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_STI is not set # CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_LOGICVC is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_IMX_LCDIF is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_PANEL_MIPI_DBI is not set @@ -3842,7 +3851,9 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set +# CONFIG_SND_CTL_INPUT_VALIDATION is not set # CONFIG_SND_SEQUENCER is not set CONFIG_SND_DRIVERS=y # CONFIG_SND_DUMMY is not set @@ -3988,6 +3999,7 @@ CONFIG_SND_SOC_ES8328=m CONFIG_SND_SOC_ES8328_I2C=m CONFIG_SND_SOC_ES8328_SPI=m # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_HDA is not set # CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set @@ -4041,6 +4053,7 @@ CONFIG_SND_SOC_STI_SAS=m # CONFIG_SND_SOC_TAS2562 is not set # CONFIG_SND_SOC_TAS2764 is not set # CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS2780 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set @@ -4247,6 +4260,7 @@ CONFIG_USB_HIDDEV=y # I2C HID support # # CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_ELAN is not set # CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -4420,6 +4434,7 @@ CONFIG_USB_HSIC_USB3503=y # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_ONBOARD_HUB is not set # # USB Physical Layer drivers @@ -4707,6 +4722,7 @@ CONFIG_RTC_DRV_MAX8907=y CONFIG_RTC_DRV_MAX8998=m CONFIG_RTC_DRV_MAX8997=m CONFIG_RTC_DRV_MAX77686=y +# CONFIG_RTC_DRV_NCT3018Y is not set CONFIG_RTC_DRV_RK808=y CONFIG_RTC_DRV_RS5C372=m # CONFIG_RTC_DRV_ISL1208 is not set @@ -4853,7 +4869,6 @@ CONFIG_DMABUF_HEAPS_CMA=y CONFIG_VIRTIO_ANCHOR=y CONFIG_VIRTIO=y CONFIG_VIRTIO_MENU=y -# CONFIG_VIRTIO_HARDEN_NOTIFICATION is not set # CONFIG_VIRTIO_BALLOON is not set # CONFIG_VIRTIO_INPUT is not set CONFIG_VIRTIO_MMIO=y @@ -4938,6 +4953,7 @@ CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_HANTRO_ROCKCHIP=y # CONFIG_VIDEO_MAX96712 is not set CONFIG_VIDEO_ROCKCHIP_VDEC=m +# CONFIG_VIDEO_STKWEBCAM is not set # CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set # CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set @@ -4946,10 +4962,6 @@ CONFIG_VIDEO_ROCKCHIP_VDEC=m # CONFIG_PI433 is not set # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set - -# -# VME Device Drivers -# # CONFIG_GOLDFISH is not set CONFIG_CHROME_PLATFORMS=y CONFIG_CROS_EC=m @@ -4957,6 +4969,7 @@ CONFIG_CROS_EC=m # CONFIG_CROS_EC_RPMSG is not set # CONFIG_CROS_EC_SPI is not set CONFIG_CROS_EC_PROTO=y +# CONFIG_CROS_KBD_LED_BACKLIGHT is not set CONFIG_CROS_EC_CHARDEV=m CONFIG_CROS_EC_LIGHTBAR=m CONFIG_CROS_EC_VBC=m @@ -5093,6 +5106,11 @@ CONFIG_RPMSG_VIRTIO=m # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + # # i.MX SoC drivers # @@ -5680,6 +5698,7 @@ CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set CONFIG_PWM_ATMEL_HLCDC_PWM=m # CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_CLK is not set # CONFIG_PWM_CROS_EC is not set CONFIG_PWM_FSL_FTM=m # CONFIG_PWM_PCA9685 is not set @@ -5702,6 +5721,7 @@ CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_SCMI=y # CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_TI_TPS380X is not set # # PHY Subsystem @@ -5759,7 +5779,7 @@ CONFIG_ARM_PMU=y # # Android # -# CONFIG_ANDROID is not set +# CONFIG_ANDROID_BINDER_IPC is not set # end of Android # CONFIG_DAX is not set @@ -6195,6 +6215,7 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_KEYWRAP is not set CONFIG_CRYPTO_NHPOLY1305=y # CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_HCTR2 is not set # CONFIG_CRYPTO_ESSIV is not set # @@ -6243,6 +6264,7 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_ARIA is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_SM4_GENERIC is not set # CONFIG_CRYPTO_TEA is not set @@ -6342,6 +6364,7 @@ CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines @@ -6386,6 +6409,7 @@ CONFIG_GENERIC_ALLOCATOR=y CONFIG_REED_SOLOMON=y CONFIG_REED_SOLOMON_ENC8=y CONFIG_REED_SOLOMON_DEC8=y +CONFIG_XARRAY_MULTI=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y @@ -6396,6 +6420,8 @@ CONFIG_NEED_DMA_MAP_STATE=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_CMA=y # CONFIG_DMA_PERNUMA_CMA is not set @@ -6431,7 +6457,6 @@ CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_STACKDEPOT=y -CONFIG_STACK_HASH_ORDER=20 CONFIG_SBITMAP=y # end of Library routines @@ -6517,6 +6542,7 @@ CONFIG_SLUB_DEBUG=y # CONFIG_DEBUG_RODATA_TEST is not set # CONFIG_DEBUG_WX is not set # CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set @@ -6529,6 +6555,7 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_KMAP_LOCAL is not set # CONFIG_DEBUG_HIGHMEM is not set CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set @@ -6655,6 +6682,7 @@ CONFIG_PROBE_EVENTS=y # CONFIG_RING_BUFFER_STARTUP_TEST is not set # CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set # CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_RV is not set # CONFIG_SAMPLES is not set # CONFIG_STRICT_DEVMEM is not set From 9af21487c18d9e90950a5f331ccf8dd43b68c92e Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Tue, 23 Aug 2022 09:32:05 +0000 Subject: [PATCH 20/29] linux (Rockchip RK3328): update .config for 6.0-rc4 --- .../RK3328/linux/default/linux.aarch64.conf | 60 +++++++++++++------ 1 file changed, 43 insertions(+), 17 deletions(-) diff --git a/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf index b91ed5200c..b1f89f9592 100644 --- a/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.19.7-rc1 Kernel Configuration +# Linux/arm64 6.0.0-rc4 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-elf-gcc-12.2.0 (GCC) 12.2.0" CONFIG_CC_IS_GCC=y @@ -11,7 +11,6 @@ CONFIG_AS_VERSION=23900 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23900 CONFIG_LLD_VERSION=0 -CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y @@ -69,6 +68,8 @@ CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem @@ -158,6 +159,7 @@ CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y CONFIG_MEMCG_KMEM=y @@ -292,6 +294,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_ARCH_BCM2835 is not set # CONFIG_ARCH_BCM4908 is not set # CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BCMBCA is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_BITMAIN is not set # CONFIG_ARCH_BRCMSTB is not set @@ -306,6 +309,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_ARCH_MESON is not set # CONFIG_ARCH_MVEBU is not set # CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_NPCM is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_RENESAS is not set @@ -457,7 +461,6 @@ CONFIG_AS_HAS_ARMV8_5=y # CONFIG_ARM64_BTI is not set CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y # CONFIG_ARM64_E0PD is not set -# CONFIG_ARCH_RANDOM is not set CONFIG_ARM64_AS_HAS_MTE=y # end of ARMv8.5 architectural features @@ -493,6 +496,7 @@ CONFIG_SUSPEND_FREEZER=y CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y # CONFIG_PM_DEBUG is not set @@ -525,7 +529,6 @@ CONFIG_DT_IDLE_GENPD=y # # ARM CPU Idle Drivers # -CONFIG_ARM_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y # end of ARM CPU Idle Drivers @@ -574,6 +577,7 @@ CONFIG_CRYPTO_SHA512_ARM64_CE=y CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y CONFIG_CRYPTO_GHASH_ARM64_CE=y +# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y @@ -591,6 +595,7 @@ CONFIG_CRYPTO_AES_ARM64_BS=y CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y @@ -639,7 +644,7 @@ CONFIG_ARCH_SUPPORTS_LTO_CLANG=y CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y CONFIG_LTO_NONE=y CONFIG_ARCH_SUPPORTS_CFI_CLANG=y -CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOVE_PUD=y @@ -679,6 +684,7 @@ CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y +CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y # # GCOV-based kernel profiling @@ -890,9 +896,11 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_MEMORY_FAILURE=y # CONFIG_HWPOISON_INJECT is not set +CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +CONFIG_THP_SWAP=y # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set @@ -904,7 +912,6 @@ CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y -CONFIG_ARCH_HAS_VM_GET_PAGE_PROT=y CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y @@ -1571,6 +1578,7 @@ CONFIG_BLK_DEV_NBD=m # CONFIG_ATA_OVER_ETH is not set CONFIG_VIRTIO_BLK=y # CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_UBLK is not set # # NVME Support @@ -1601,6 +1609,7 @@ CONFIG_SRAM=y # CONFIG_XILINX_SDFEC is not set # CONFIG_HISI_HIKEY_USB is not set # CONFIG_OPEN_DICE is not set +# CONFIG_VCPU_STALL_DETECTOR is not set # CONFIG_C2PORT is not set # @@ -1723,6 +1732,7 @@ CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_NET_VENDOR_HISILICON is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_WANGXUN is not set # CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set @@ -2229,7 +2239,6 @@ CONFIG_SERIAL_8250_NR_UARTS=5 CONFIG_SERIAL_8250_RUNTIME_UARTS=5 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y -# CONFIG_SERIAL_8250_ASPEED_VUART is not set CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_8250_DETECT_IRQ is not set # CONFIG_SERIAL_8250_RSA is not set @@ -2286,6 +2295,7 @@ CONFIG_DEVMEM=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set +CONFIG_RANDOM_TRUST_CPU=y # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # end of Character devices @@ -2379,6 +2389,7 @@ CONFIG_SPI_BITBANG=m # CONFIG_SPI_NXP_FLEXSPI is not set CONFIG_SPI_GPIO=m # CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_MICROCHIP_CORE is not set # CONFIG_SPI_OC_TINY is not set CONFIG_SPI_PL022=y CONFIG_SPI_ROCKCHIP=m @@ -2479,7 +2490,6 @@ CONFIG_GPIO_DWAPB=y # CONFIG_GPIO_MB86S7X is not set CONFIG_GPIO_PL061=y CONFIG_GPIO_ROCKCHIP=y -# CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SYSCON=y # CONFIG_GPIO_XGENE is not set @@ -2600,7 +2610,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AD7314 is not set # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set @@ -2662,7 +2671,6 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_MAX6620 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_MAX6697 is not set # CONFIG_SENSORS_MAX31790 is not set @@ -3131,7 +3139,6 @@ CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_USB_GSPCA is not set # CONFIG_USB_PWC is not set # CONFIG_USB_S2255 is not set -# CONFIG_USB_STKWEBCAM is not set # CONFIG_VIDEO_USBTV is not set # CONFIG_USB_VIDEO_CLASS is not set # CONFIG_USB_ZR364XX is not set @@ -3376,6 +3383,7 @@ CONFIG_VIDEO_IR_I2C=y # # Camera sensor devices # +# CONFIG_VIDEO_AR0521 is not set # CONFIG_VIDEO_HI556 is not set # CONFIG_VIDEO_HI846 is not set # CONFIG_VIDEO_HI847 is not set @@ -3784,6 +3792,7 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_TOSHIBA_TC358767 is not set # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TI_DLPC3433 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set @@ -3802,7 +3811,9 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_HISI_KIRIN is not set +# CONFIG_DRM_LOGICVC is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_IMX_LCDIF is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_PANEL_MIPI_DBI is not set @@ -3918,7 +3929,9 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set +# CONFIG_SND_CTL_INPUT_VALIDATION is not set # CONFIG_SND_SEQUENCER is not set CONFIG_SND_DRIVERS=y # CONFIG_SND_DUMMY is not set @@ -4060,6 +4073,7 @@ CONFIG_SND_SOC_ES8328=m CONFIG_SND_SOC_ES8328_I2C=m CONFIG_SND_SOC_ES8328_SPI=m # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_HDA is not set # CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set @@ -4115,6 +4129,7 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TAS2562 is not set # CONFIG_SND_SOC_TAS2764 is not set # CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS2780 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set @@ -4320,6 +4335,7 @@ CONFIG_USB_HIDDEV=y # I2C HID support # # CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_ELAN is not set # CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -4493,6 +4509,7 @@ CONFIG_USB_ISP1760_DUAL_ROLE=y # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_ONBOARD_HUB is not set # # USB Physical Layer drivers @@ -4729,6 +4746,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_HYM8563 is not set # CONFIG_RTC_DRV_MAX6900 is not set CONFIG_RTC_DRV_MAX77686=y +# CONFIG_RTC_DRV_NCT3018Y is not set CONFIG_RTC_DRV_RK808=y # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set @@ -4956,6 +4974,7 @@ CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_HANTRO_ROCKCHIP=y # CONFIG_VIDEO_MAX96712 is not set CONFIG_VIDEO_ROCKCHIP_VDEC=m +# CONFIG_VIDEO_STKWEBCAM is not set # CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set # CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set @@ -4964,10 +4983,6 @@ CONFIG_VIDEO_ROCKCHIP_VDEC=m # CONFIG_PI433 is not set # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set - -# -# VME Device Drivers -# # CONFIG_GOLDFISH is not set CONFIG_CHROME_PLATFORMS=y # CONFIG_CROS_EC is not set @@ -5102,6 +5117,11 @@ CONFIG_ARM_SMMU_V3=y # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + # # i.MX SoC drivers # @@ -5673,6 +5693,7 @@ CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_CLK is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_ROCKCHIP=y @@ -5695,6 +5716,7 @@ CONFIG_PARTITION_PERCPU=y CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_TI_TPS380X is not set # # PHY Subsystem @@ -5756,7 +5778,7 @@ CONFIG_RAS=y # # Android # -# CONFIG_ANDROID is not set +# CONFIG_ANDROID_BINDER_IPC is not set # end of Android # CONFIG_LIBNVDIMM is not set @@ -6230,6 +6252,7 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_KEYWRAP is not set CONFIG_CRYPTO_NHPOLY1305=y # CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_HCTR2 is not set # CONFIG_CRYPTO_ESSIV is not set # @@ -6278,6 +6301,7 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_KHAZAD is not set CONFIG_CRYPTO_CHACHA20=m # CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_ARIA is not set # CONFIG_CRYPTO_SERPENT is not set CONFIG_CRYPTO_SM4=y # CONFIG_CRYPTO_SM4_GENERIC is not set @@ -6381,6 +6405,7 @@ CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines @@ -6481,10 +6506,10 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y -CONFIG_STACK_HASH_ORDER=20 CONFIG_SBITMAP=y # end of Library routines +CONFIG_GENERIC_IOREMAP=y CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y # @@ -6576,6 +6601,7 @@ CONFIG_ARCH_HAS_DEBUG_WX=y CONFIG_GENERIC_PTDUMP=y # CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set From f69509335360c85e60e86acf8e87fd89b2a9a7da Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Tue, 23 Aug 2022 09:32:05 +0000 Subject: [PATCH 21/29] linux (Rockchip RK3399): update .config for 6.0-rc4 and set CONFIG_PCIE_ROCKCHIP_HOST=y --- .../RK3399/linux/default/linux.aarch64.conf | 88 +++++++++++++------ 1 file changed, 62 insertions(+), 26 deletions(-) diff --git a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf index 9f5e954b22..6afdbfc7c6 100644 --- a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.19.7-rc1 Kernel Configuration +# Linux/arm64 6.0.0-rc4 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-elf-gcc-12.2.0 (GCC) 12.2.0" CONFIG_CC_IS_GCC=y @@ -11,7 +11,6 @@ CONFIG_AS_VERSION=23900 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23900 CONFIG_LLD_VERSION=0 -CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y @@ -69,6 +68,8 @@ CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem @@ -158,6 +159,7 @@ CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y CONFIG_MEMCG_KMEM=y @@ -291,6 +293,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_ARCH_BCM2835 is not set # CONFIG_ARCH_BCM4908 is not set # CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BCMBCA is not set # CONFIG_ARCH_BERLIN is not set # CONFIG_ARCH_BITMAIN is not set # CONFIG_ARCH_BRCMSTB is not set @@ -305,6 +308,7 @@ CONFIG_ARCH_PROC_KCORE_TEXT=y # CONFIG_ARCH_MESON is not set # CONFIG_ARCH_MVEBU is not set # CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_NPCM is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_RENESAS is not set @@ -457,7 +461,6 @@ CONFIG_AS_HAS_ARMV8_5=y # CONFIG_ARM64_BTI is not set CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y # CONFIG_ARM64_E0PD is not set -# CONFIG_ARCH_RANDOM is not set CONFIG_ARM64_AS_HAS_MTE=y # end of ARMv8.5 architectural features @@ -493,6 +496,7 @@ CONFIG_SUSPEND_FREEZER=y CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y # CONFIG_PM_DEBUG is not set @@ -525,7 +529,6 @@ CONFIG_DT_IDLE_GENPD=y # # ARM CPU Idle Drivers # -CONFIG_ARM_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y # end of ARM CPU Idle Drivers @@ -574,6 +577,7 @@ CONFIG_CRYPTO_SHA512_ARM64_CE=y CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y CONFIG_CRYPTO_GHASH_ARM64_CE=y +# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set CONFIG_CRYPTO_AES_ARM64=y CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y @@ -591,6 +595,7 @@ CONFIG_CRYPTO_AES_ARM64_BS=y CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y @@ -639,7 +644,7 @@ CONFIG_ARCH_SUPPORTS_LTO_CLANG=y CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y CONFIG_LTO_NONE=y CONFIG_ARCH_SUPPORTS_CFI_CLANG=y -CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOVE_PUD=y @@ -679,6 +684,7 @@ CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y +CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y # # GCOV-based kernel profiling @@ -891,9 +897,11 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_MEMORY_FAILURE=y # CONFIG_HWPOISON_INJECT is not set +CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +CONFIG_THP_SWAP=y # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set @@ -905,7 +913,6 @@ CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y -CONFIG_ARCH_HAS_VM_GET_PAGE_PROT=y CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y @@ -1397,7 +1404,7 @@ CONFIG_VGA_ARB_MAX_GPUS=16 # CONFIG_PCI_HOST_THUNDER_PEM is not set # CONFIG_PCI_HOST_THUNDER_ECAM is not set CONFIG_PCIE_ROCKCHIP=y -CONFIG_PCIE_ROCKCHIP_HOST=m +CONFIG_PCIE_ROCKCHIP_HOST=y # CONFIG_PCIE_MICROCHIP_HOST is not set # @@ -1645,12 +1652,12 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_DRBD is not set CONFIG_BLK_DEV_NBD=m -# CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set CONFIG_VIRTIO_BLK=y # CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_UBLK is not set # # NVME Support @@ -1663,12 +1670,14 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVME_FABRICS=m CONFIG_NVME_FC=m # CONFIG_NVME_TCP is not set +# CONFIG_NVME_AUTH is not set CONFIG_NVME_TARGET=m # CONFIG_NVME_TARGET_PASSTHRU is not set CONFIG_NVME_TARGET_LOOP=m CONFIG_NVME_TARGET_FC=m # CONFIG_NVME_TARGET_FCLOOP is not set # CONFIG_NVME_TARGET_TCP is not set +# CONFIG_NVME_TARGET_AUTH is not set # end of NVME Support # @@ -1697,6 +1706,7 @@ CONFIG_SRAM=y # CONFIG_XILINX_SDFEC is not set # CONFIG_HISI_HIKEY_USB is not set # CONFIG_OPEN_DICE is not set +# CONFIG_VCPU_STALL_DETECTOR is not set # CONFIG_C2PORT is not set # @@ -1799,6 +1809,7 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_MPI3MR is not set # CONFIG_SCSI_SMARTPQI is not set # CONFIG_SCSI_HPTIOP is not set +# CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_MYRB is not set # CONFIG_SCSI_MYRS is not set # CONFIG_SCSI_SNIC is not set @@ -2006,6 +2017,7 @@ CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_NET_VENDOR_HISILICON is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_WANGXUN is not set # CONFIG_JME is not set # CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set @@ -2021,7 +2033,6 @@ CONFIG_NET_VENDOR_MYRI=y # CONFIG_NET_VENDOR_NATSEMI is not set CONFIG_NET_VENDOR_NETERION=y # CONFIG_S2IO is not set -# CONFIG_VXGE is not set # CONFIG_NET_VENDOR_NETRONOME is not set CONFIG_NET_VENDOR_NVIDIA=y # CONFIG_FORCEDETH is not set @@ -2625,7 +2636,6 @@ CONFIG_SERIAL_8250_NR_UARTS=5 CONFIG_SERIAL_8250_RUNTIME_UARTS=5 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y -# CONFIG_SERIAL_8250_ASPEED_VUART is not set CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_8250_DETECT_IRQ is not set # CONFIG_SERIAL_8250_RSA is not set @@ -2689,6 +2699,7 @@ CONFIG_DEVPORT=y # CONFIG_TCG_TPM is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set +CONFIG_RANDOM_TRUST_CPU=y # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # end of Character devices @@ -2803,6 +2814,7 @@ CONFIG_SPI_BITBANG=m # CONFIG_SPI_NXP_FLEXSPI is not set CONFIG_SPI_GPIO=m # CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_MICROCHIP_CORE is not set # CONFIG_SPI_OC_TINY is not set CONFIG_SPI_PL022=y # CONFIG_SPI_PXA2XX is not set @@ -2907,7 +2919,6 @@ CONFIG_GPIO_DWAPB=y # CONFIG_GPIO_MB86S7X is not set CONFIG_GPIO_PL061=y CONFIG_GPIO_ROCKCHIP=y -# CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SYSCON=y # CONFIG_GPIO_XGENE is not set @@ -3037,7 +3048,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AD7314 is not set # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set @@ -3101,7 +3111,6 @@ CONFIG_SENSORS_ARM_SCPI=y # CONFIG_SENSORS_MAX6620 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_MAX6697 is not set # CONFIG_SENSORS_MAX31790 is not set @@ -3596,7 +3605,6 @@ CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_USB_GSPCA is not set # CONFIG_USB_PWC is not set # CONFIG_USB_S2255 is not set -# CONFIG_USB_STKWEBCAM is not set # CONFIG_VIDEO_USBTV is not set # CONFIG_USB_VIDEO_CLASS is not set # CONFIG_USB_ZR364XX is not set @@ -3901,6 +3909,7 @@ CONFIG_VIDEO_IR_I2C=y # # Camera sensor devices # +# CONFIG_VIDEO_AR0521 is not set # CONFIG_VIDEO_HI556 is not set # CONFIG_VIDEO_HI846 is not set # CONFIG_VIDEO_HI847 is not set @@ -4334,6 +4343,7 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_TOSHIBA_TC358767 is not set # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TI_DLPC3433 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set @@ -4353,7 +4363,9 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_HISI_HIBMC is not set # CONFIG_DRM_HISI_KIRIN is not set +# CONFIG_DRM_LOGICVC is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_IMX_LCDIF is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_BOCHS is not set # CONFIG_DRM_CIRRUS_QEMU is not set @@ -4497,7 +4509,9 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set +# CONFIG_SND_CTL_INPUT_VALIDATION is not set # CONFIG_SND_SEQUENCER is not set CONFIG_SND_DRIVERS=y # CONFIG_SND_DUMMY is not set @@ -4704,6 +4718,7 @@ CONFIG_SND_SOC_ES8328=m CONFIG_SND_SOC_ES8328_I2C=m CONFIG_SND_SOC_ES8328_SPI=m # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_HDA is not set # CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set @@ -4759,6 +4774,7 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TAS2562 is not set # CONFIG_SND_SOC_TAS2764 is not set # CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS2780 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set @@ -4964,6 +4980,7 @@ CONFIG_USB_HIDDEV=y # I2C HID support # # CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_ELAN is not set # CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -5145,6 +5162,7 @@ CONFIG_USB_ISP1760_DUAL_ROLE=y # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_ONBOARD_HUB is not set # # USB Physical Layer drivers @@ -5216,6 +5234,7 @@ CONFIG_TYPEC_TCPM=m CONFIG_TYPEC_FUSB302=m # CONFIG_TYPEC_UCSI is not set # CONFIG_TYPEC_TPS6598X is not set +# CONFIG_TYPEC_ANX7411 is not set # CONFIG_TYPEC_RT1719 is not set # CONFIG_TYPEC_HD3SS3220 is not set # CONFIG_TYPEC_STUSB160X is not set @@ -5416,6 +5435,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_HYM8563 is not set # CONFIG_RTC_DRV_MAX6900 is not set CONFIG_RTC_DRV_MAX77686=y +# CONFIG_RTC_DRV_NCT3018Y is not set CONFIG_RTC_DRV_RK808=y # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set @@ -5652,15 +5672,16 @@ CONFIG_R8188EU=m # CONFIG_FB_SM750 is not set CONFIG_STAGING_MEDIA=y -CONFIG_VIDEO_HANTRO=m -CONFIG_VIDEO_HANTRO_ROCKCHIP=y -# CONFIG_VIDEO_MAX96712 is not set -CONFIG_VIDEO_ROCKCHIP_VDEC=m -# CONFIG_VIDEO_ZORAN is not set CONFIG_DVB_AV7110_IR=y CONFIG_DVB_AV7110=m # CONFIG_DVB_AV7110_OSD is not set CONFIG_DVB_SP8870=m +CONFIG_VIDEO_HANTRO=m +CONFIG_VIDEO_HANTRO_ROCKCHIP=y +# CONFIG_VIDEO_MAX96712 is not set +CONFIG_VIDEO_ROCKCHIP_VDEC=m +# CONFIG_VIDEO_STKWEBCAM is not set +# CONFIG_VIDEO_ZORAN is not set # CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set # CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set @@ -5670,10 +5691,7 @@ CONFIG_DVB_SP8870=m # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_QLGE is not set - -# -# VME Device Drivers -# +# CONFIG_VME_BUS is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set @@ -5806,6 +5824,11 @@ CONFIG_ARM_SMMU_V3=y # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + # # i.MX SoC drivers # @@ -6374,11 +6397,11 @@ CONFIG_ROCKCHIP_SARADC=y # end of Temperature sensors # CONFIG_NTB is not set -# CONFIG_VME_BUS is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_CLK is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set @@ -6404,6 +6427,7 @@ CONFIG_PARTITION_PERCPU=y CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_TI_TPS380X is not set # # PHY Subsystem @@ -6460,6 +6484,7 @@ CONFIG_ARM_PMU=y # CONFIG_ARM_DSU_PMU is not set # CONFIG_ARM_SPE_PMU is not set # CONFIG_HISI_PCIE_PMU is not set +# CONFIG_HNS3_PMU is not set # end of Performance monitor support CONFIG_RAS=y @@ -6468,7 +6493,7 @@ CONFIG_RAS=y # # Android # -# CONFIG_ANDROID is not set +# CONFIG_ANDROID_BINDER_IPC is not set # end of Android # CONFIG_LIBNVDIMM is not set @@ -6942,6 +6967,7 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_KEYWRAP is not set CONFIG_CRYPTO_NHPOLY1305=y # CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_HCTR2 is not set # CONFIG_CRYPTO_ESSIV is not set # @@ -6990,6 +7016,7 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_KHAZAD is not set CONFIG_CRYPTO_CHACHA20=m # CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_ARIA is not set # CONFIG_CRYPTO_SERPENT is not set CONFIG_CRYPTO_SM4=y # CONFIG_CRYPTO_SM4_GENERIC is not set @@ -7028,6 +7055,13 @@ CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set # CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_4XXX is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set +# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set # CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set # CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set CONFIG_CRYPTO_DEV_ROCKCHIP=m @@ -7095,6 +7129,7 @@ CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y CONFIG_CRYPTO_LIB_POLY1305=m CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines @@ -7196,10 +7231,10 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y -CONFIG_STACK_HASH_ORDER=20 CONFIG_SBITMAP=y # end of Library routines +CONFIG_GENERIC_IOREMAP=y CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y # @@ -7291,6 +7326,7 @@ CONFIG_ARCH_HAS_DEBUG_WX=y CONFIG_GENERIC_PTDUMP=y # CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set From 008fffc2e8dd4ca30a057303a6b0edea1d88e58d Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Mon, 22 Aug 2022 10:36:27 +0000 Subject: [PATCH 22/29] linux (Samsung): update .config for 6.0-rc5 --- projects/Samsung/linux/linux.arm.conf | 60 +++++++++++++++++++-------- 1 file changed, 43 insertions(+), 17 deletions(-) diff --git a/projects/Samsung/linux/linux.arm.conf b/projects/Samsung/linux/linux.arm.conf index 8aeaac6e66..d9ff0b62a1 100644 --- a/projects/Samsung/linux/linux.arm.conf +++ b/projects/Samsung/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.19.4-rc1 Kernel Configuration +# Linux/arm 6.0.0-rc5 Kernel Configuration # CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-12.2.0 (GCC) 12.2.0" CONFIG_CC_IS_GCC=y @@ -13,7 +13,6 @@ CONFIG_LD_VERSION=23900 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y @@ -43,7 +42,6 @@ CONFIG_HAVE_KERNEL_LZ4=y CONFIG_KERNEL_LZ4=y CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="@DISTRONAME@" -CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set @@ -75,6 +73,8 @@ CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_ARCH_HAS_TICK_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y # # Timers subsystem @@ -153,6 +153,7 @@ CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_GCC12_NO_ARRAY_BOUNDS=y CONFIG_CC_NO_ARRAY_BOUNDS=y CONFIG_CGROUPS=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set # CONFIG_MEMCG is not set # CONFIG_BLK_CGROUP is not set # CONFIG_CGROUP_SCHED is not set @@ -346,6 +347,7 @@ CONFIG_EXYNOS_CPU_SUSPEND=y # CONFIG_PLAT_SPEAR is not set # CONFIG_ARCH_STI is not set # CONFIG_ARCH_STM32 is not set +# CONFIG_ARCH_SUNPLUS is not set # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_TEGRA is not set # CONFIG_ARCH_UNIPHIER is not set @@ -490,6 +492,7 @@ CONFIG_STACKPROTECTOR_PER_TASK=y # CONFIG_USE_OF=y CONFIG_ATAGS=y +# CONFIG_UNUSED_BOARD_FILES is not set # CONFIG_DEPRECATED_PARAM_STRUCT is not set CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 @@ -577,6 +580,7 @@ CONFIG_SUSPEND_FREEZER=y CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y # CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set # CONFIG_PM_WAKELOCKS is not set CONFIG_PM=y CONFIG_PM_DEBUG=y @@ -655,13 +659,14 @@ CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_LTO_NONE=y -CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_REL=y CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y @@ -681,7 +686,6 @@ CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_PHYS_TO_DMA=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_HAVE_ARCH_PFN_VALID=y @@ -1190,6 +1194,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_UBLK is not set # # NVME Support @@ -1220,6 +1225,7 @@ CONFIG_SRAM_EXEC=y # CONFIG_XILINX_SDFEC is not set # CONFIG_HISI_HIKEY_USB is not set # CONFIG_OPEN_DICE is not set +# CONFIG_VCPU_STALL_DETECTOR is not set # CONFIG_C2PORT is not set # @@ -1368,6 +1374,7 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_HISILICON is not set # CONFIG_NET_VENDOR_HUAWEI is not set # CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_WANGXUN is not set # CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set @@ -1472,7 +1479,6 @@ CONFIG_MDIO_DEVRES=y # # PCS device drivers # -# CONFIG_PCS_XPCS is not set # end of PCS device drivers # CONFIG_PPP is not set @@ -1853,7 +1859,6 @@ CONFIG_SERIAL_8250_NR_UARTS=1 CONFIG_SERIAL_8250_RUNTIME_UARTS=0 CONFIG_SERIAL_8250_EXTENDED=y # CONFIG_SERIAL_8250_MANY_PORTS is not set -# CONFIG_SERIAL_8250_ASPEED_VUART is not set # CONFIG_SERIAL_8250_SHARE_IRQ is not set # CONFIG_SERIAL_8250_DETECT_IRQ is not set # CONFIG_SERIAL_8250_RSA is not set @@ -1910,6 +1915,7 @@ CONFIG_TCG_TPM=y CONFIG_HW_RANDOM_TPM=y # CONFIG_TCG_TIS is not set # CONFIG_TCG_TIS_SPI is not set +# CONFIG_TCG_TIS_I2C is not set # CONFIG_TCG_TIS_I2C_CR50 is not set # CONFIG_TCG_TIS_I2C_ATMEL is not set CONFIG_TCG_TIS_I2C_INFINEON=y @@ -1920,6 +1926,7 @@ CONFIG_TCG_TIS_I2C_INFINEON=y # CONFIG_TCG_TIS_ST33ZP24_SPI is not set # CONFIG_XILLYBUS is not set # CONFIG_XILLYUSB is not set +CONFIG_RANDOM_TRUST_CPU=y # CONFIG_RANDOM_TRUST_BOOTLOADER is not set # end of Character devices @@ -2011,6 +2018,7 @@ CONFIG_SPI_BITBANG=y # CONFIG_SPI_NXP_FLEXSPI is not set CONFIG_SPI_GPIO=y # CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_MICROCHIP_CORE is not set # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_PL022 is not set # CONFIG_SPI_ROCKCHIP is not set @@ -2093,7 +2101,6 @@ CONFIG_GPIO_CDEV_V1=y # CONFIG_GPIO_MB86S7X is not set # CONFIG_GPIO_MPC8XXX is not set # CONFIG_GPIO_PL061 is not set -# CONFIG_GPIO_SAMA5D2_PIOBU is not set # CONFIG_GPIO_SIFIVE is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_XILINX is not set @@ -2217,7 +2224,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AD7314 is not set # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set @@ -2278,7 +2284,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_MAX6620 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_MAX6697 is not set # CONFIG_SENSORS_MAX31790 is not set @@ -2752,7 +2757,6 @@ CONFIG_USB_GSPCA=m # CONFIG_USB_STV06XX is not set # CONFIG_USB_PWC is not set # CONFIG_USB_S2255 is not set -# CONFIG_USB_STKWEBCAM is not set # CONFIG_VIDEO_USBTV is not set CONFIG_USB_VIDEO_CLASS=m CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y @@ -2874,6 +2878,7 @@ CONFIG_VIDEOBUF2_VMALLOC=m # # Camera sensor devices # +# CONFIG_VIDEO_AR0521 is not set # CONFIG_VIDEO_HI556 is not set # CONFIG_VIDEO_HI846 is not set # CONFIG_VIDEO_HI847 is not set @@ -3158,6 +3163,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y +# CONFIG_DRM_PANEL_EBBG_FT8719 is not set # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set @@ -3252,6 +3258,7 @@ CONFIG_DRM_TOSHIBA_TC358764=y # CONFIG_DRM_TOSHIBA_TC358767 is not set # CONFIG_DRM_TOSHIBA_TC358768 is not set # CONFIG_DRM_TOSHIBA_TC358775 is not set +# CONFIG_DRM_TI_DLPC3433 is not set # CONFIG_DRM_TI_TFP410 is not set # CONFIG_DRM_TI_SN65DSI83 is not set # CONFIG_DRM_TI_SN65DSI86 is not set @@ -3266,7 +3273,9 @@ CONFIG_DRM_ANALOGIX_DP=y # CONFIG_DRM_STI is not set # CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_LOGICVC is not set # CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_IMX_LCDIF is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_PANEL_MIPI_DBI is not set @@ -3395,7 +3404,9 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set +# CONFIG_SND_CTL_INPUT_VALIDATION is not set # CONFIG_SND_SEQUENCER is not set CONFIG_SND_DRIVERS=y # CONFIG_SND_DUMMY is not set @@ -3539,6 +3550,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES8328_I2C is not set # CONFIG_SND_SOC_ES8328_SPI is not set # CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_HDA is not set # CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set @@ -3588,6 +3600,7 @@ CONFIG_SND_SOC_RT5631=y # CONFIG_SND_SOC_TAS2562 is not set # CONFIG_SND_SOC_TAS2764 is not set # CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS2780 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TAS571X is not set # CONFIG_SND_SOC_TAS5720 is not set @@ -3786,6 +3799,7 @@ CONFIG_USB_HID=y # I2C HID support # # CONFIG_I2C_HID_OF is not set +# CONFIG_I2C_HID_OF_ELAN is not set # CONFIG_I2C_HID_OF_GOODIX is not set # end of I2C HID support # end of HID support @@ -3937,6 +3951,7 @@ CONFIG_USB_HSIC_USB3503=y # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_ONBOARD_HUB is not set # # USB Physical Layer drivers @@ -4168,6 +4183,7 @@ CONFIG_RTC_INTF_DEV=y CONFIG_RTC_DRV_MAX8998=y CONFIG_RTC_DRV_MAX8997=y CONFIG_RTC_DRV_MAX77686=y +# CONFIG_RTC_DRV_NCT3018Y is not set # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set # CONFIG_RTC_DRV_ISL12022 is not set @@ -4383,10 +4399,6 @@ CONFIG_VT6656=m # CONFIG_PI433 is not set # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set - -# -# VME Device Drivers -# # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set @@ -4494,6 +4506,11 @@ CONFIG_EXYNOS_IOMMU=y # CONFIG_FSL_RCPM is not set # end of NXP/Freescale QorIQ SoC drivers +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + # # i.MX SoC drivers # @@ -5071,6 +5088,7 @@ CONFIG_PWM=y CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL_TCB is not set +# CONFIG_PWM_CLK is not set # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_SAMSUNG=y @@ -5137,7 +5155,7 @@ CONFIG_ARM_PMU=y # # Android # -# CONFIG_ANDROID is not set +# CONFIG_ANDROID_BINDER_IPC is not set # end of Android # CONFIG_DAX is not set @@ -5547,6 +5565,7 @@ CONFIG_CRYPTO_LRW=m CONFIG_CRYPTO_XTS=m # CONFIG_CRYPTO_KEYWRAP is not set # CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_HCTR2 is not set CONFIG_CRYPTO_ESSIV=m # @@ -5595,6 +5614,7 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_ARIA is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_SM4_GENERIC is not set # CONFIG_CRYPTO_TEA is not set @@ -5693,6 +5713,7 @@ CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y CONFIG_CRYPTO_LIB_POLY1305=y CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y +CONFIG_CRYPTO_LIB_SHA1=y CONFIG_CRYPTO_LIB_SHA256=y # end of Crypto library routines @@ -5741,6 +5762,7 @@ CONFIG_DECOMPRESS_LZO=y CONFIG_DECOMPRESS_LZ4=y CONFIG_DECOMPRESS_ZSTD=y CONFIG_GENERIC_ALLOCATOR=y +CONFIG_XARRAY_MULTI=y CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y @@ -5751,6 +5773,8 @@ CONFIG_NEED_DMA_MAP_STATE=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_CMA=y # CONFIG_DMA_PERNUMA_CMA is not set @@ -5797,7 +5821,6 @@ CONFIG_FONT_7x14=y # CONFIG_FONT_6x8 is not set CONFIG_SG_POOL=y CONFIG_STACKDEPOT=y -CONFIG_STACK_HASH_ORDER=20 CONFIG_SBITMAP=y # end of Library routines @@ -5886,6 +5909,7 @@ CONFIG_SLUB_DEBUG=y # CONFIG_DEBUG_RODATA_TEST is not set # CONFIG_DEBUG_WX is not set # CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_STACK_USAGE is not set @@ -5898,6 +5922,7 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_KMAP_LOCAL is not set # CONFIG_DEBUG_HIGHMEM is not set CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set @@ -6038,6 +6063,7 @@ CONFIG_PROBE_EVENTS=y # CONFIG_RING_BUFFER_STARTUP_TEST is not set # CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set # CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_RV is not set # CONFIG_SAMPLES is not set # CONFIG_STRICT_DEVMEM is not set From 58dec31cc0fbbca8c4a6b1df5c0154ba468f2635 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Mon, 29 Aug 2022 08:57:14 +0000 Subject: [PATCH 23/29] xf86-video-nvidia-legacy: allow build with kernel 6.0 --- ...xf86-video-nvidia-legacy-100.11-kernel-6.0.patch | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 packages/x11/driver/xf86-video-nvidia-legacy/patches/xf86-video-nvidia-legacy-100.11-kernel-6.0.patch diff --git a/packages/x11/driver/xf86-video-nvidia-legacy/patches/xf86-video-nvidia-legacy-100.11-kernel-6.0.patch b/packages/x11/driver/xf86-video-nvidia-legacy/patches/xf86-video-nvidia-legacy-100.11-kernel-6.0.patch new file mode 100644 index 0000000000..16685a83a8 --- /dev/null +++ b/packages/x11/driver/xf86-video-nvidia-legacy/patches/xf86-video-nvidia-legacy-100.11-kernel-6.0.patch @@ -0,0 +1,13 @@ +--- a/kernel/nv-acpi.c 2019-12-11 22:04:24.000000000 +0000 ++++ b/kernel/nv-acpi.c 2022-08-29 08:50:01.383913160 +0000 +@@ -16,6 +16,9 @@ + #include "nv-reg.h" + +-#if defined(NV_LINUX_ACPI_EVENTS_SUPPORTED) ++#include ++// Rel.commit "ACPI: bus: Drop unused list heads from struct acpi_device" (Rafael J. Wysocki, 4 Jun 2022) ++// Disable ACPI support due to more GPL stuff (acpi_dev_for_each_child is only GPL-exported) ++#if defined(NV_LINUX_ACPI_EVENTS_SUPPORTED) && (LINUX_VERSION_CODE < KERNEL_VERSION(6, 0, 0)) + static RM_STATUS nv_acpi_extract_integer (const union acpi_object *, void *, NvU32, NvU32 *); + static RM_STATUS nv_acpi_extract_buffer (const union acpi_object *, void *, NvU32, NvU32 *); + static RM_STATUS nv_acpi_extract_package (const union acpi_object *, void *, NvU32, NvU32 *); From d4c45f7b736e1077f14986213d9bb45c1777bb11 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Mon, 29 Aug 2022 08:57:55 +0000 Subject: [PATCH 24/29] xf86-video-nvidia: allow build with kernel 6.0 --- .../patches/nvidia-470xx-fix-linux-6.0.patch | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 packages/x11/driver/xf86-video-nvidia/patches/nvidia-470xx-fix-linux-6.0.patch diff --git a/packages/x11/driver/xf86-video-nvidia/patches/nvidia-470xx-fix-linux-6.0.patch b/packages/x11/driver/xf86-video-nvidia/patches/nvidia-470xx-fix-linux-6.0.patch new file mode 100644 index 0000000000..5936e6bd0e --- /dev/null +++ b/packages/x11/driver/xf86-video-nvidia/patches/nvidia-470xx-fix-linux-6.0.patch @@ -0,0 +1,60 @@ +From 17bed78791d6f311c83ff1794d085b18c9f89730 Mon Sep 17 00:00:00 2001 +From: Joan Bruguera +Date: Wed, 3 Aug 2022 00:56:57 +0200 +Subject: [PATCH] Tentative fix for NVIDIA 470.141.03 driver for Linux 6.0-rc1 + +--- + kernel/nvidia-drm/nvidia-drm-helper.c | 5 +++++ + kernel/nvidia/nv-acpi.c | 5 ++++- + kernel/nvidia/nv.c | 3 ++- + 3 files changed, 11 insertions(+), 2 deletions(-) + +diff --git a/kernel/nvidia-drm/nvidia-drm-helper.c b/kernel/nvidia-drm/nvidia-drm-helper.c +index 3831180..fa03d51 100644 +--- a/kernel/nvidia-drm/nvidia-drm-helper.c ++++ b/kernel/nvidia-drm/nvidia-drm-helper.c +@@ -41,6 +41,11 @@ + #include + #endif + ++// Add header which is no longer indirectly referenced as of Linux 6.0-rc1 ++#if defined(NV_DRM_DRM_FRAMEBUFFER_H_PRESENT) ++#include ++#endif ++ + static void __nv_drm_framebuffer_put(struct drm_framebuffer *fb) + { + #if defined(NV_DRM_FRAMEBUFFER_GET_PRESENT) +diff --git a/kernel/nvidia/nv-acpi.c b/nvidia/nv-acpi.c +index 2b7b988..76c36fa 100644 +--- a/kernel/nvidia/nv-acpi.c ++++ b/kernel/nvidia/nv-acpi.c +@@ -16,7 +16,10 @@ + + #include + +-#if defined(NV_LINUX_ACPI_EVENTS_SUPPORTED) ++#include ++// Rel.commit "ACPI: bus: Drop unused list heads from struct acpi_device" (Rafael J. Wysocki, 4 Jun 2022) ++// Disable ACPI support due to more GPL stuff (acpi_dev_for_each_child is only GPL-exported) ++#if defined(NV_LINUX_ACPI_EVENTS_SUPPORTED) && (LINUX_VERSION_CODE < KERNEL_VERSION(6, 0, 0)) + static NV_STATUS nv_acpi_extract_integer (const union acpi_object *, void *, NvU32, NvU32 *); + static NV_STATUS nv_acpi_extract_buffer (const union acpi_object *, void *, NvU32, NvU32 *); + static NV_STATUS nv_acpi_extract_package (const union acpi_object *, void *, NvU32, NvU32 *); +diff --git a/kernel/nvidia/nv.c b/kernel/nvidia/nv.c +index ab7d17c..e313e2e 100644 +--- a/kernel/nvidia/nv.c ++++ b/kernel/nvidia/nv.c +@@ -5423,7 +5423,8 @@ NvBool NV_API_CALL nv_s2idle_pm_configured(void) + { + NvU8 buf[8]; + +-#if defined(NV_SEQ_READ_ITER_PRESENT) ++// FIXME: Avoid this code path because on Linux 6.0-rc1, init_sync_kiocb references a GPL symbol ++#if defined(NV_SEQ_READ_ITER_PRESENT) && (LINUX_VERSION_CODE < KERNEL_VERSION(6, 0, 0)) + struct file *file; + ssize_t num_read; + struct kiocb kiocb; +-- +2.37.1 + From 4fc808565bfd2952d1541b6f3145e7564788a029 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Mon, 26 Sep 2022 18:46:04 +0000 Subject: [PATCH 25/29] firmware-imx: update PKG_SHA256 --- packages/linux-firmware/firmware-imx/package.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/packages/linux-firmware/firmware-imx/package.mk b/packages/linux-firmware/firmware-imx/package.mk index 333571bea0..6445903335 100644 --- a/packages/linux-firmware/firmware-imx/package.mk +++ b/packages/linux-firmware/firmware-imx/package.mk @@ -4,7 +4,7 @@ PKG_NAME="firmware-imx" PKG_VERSION="8.17" -PKG_SHA256="289a021aa6b7ec56fa02e2d21710179dc33cd59c65cce88b7d9119efafea7a65" +PKG_SHA256="1ee3c49ad8749867487f09d6e4472536fb809b667c1bb3c56511175b8974e3c6" PKG_ARCH="arm" PKG_LICENSE="other" PKG_SITE="http://www.freescale.com" From c5cf9182c840762ab5715a9c377c93755758fdfc Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sun, 18 Sep 2022 08:45:02 +0000 Subject: [PATCH 26/29] ffmpeg: update v4l2-request patch Patch created using revisions 293e067..0b8eff4 from branch v4l2-request-hwaccel-4.4.1-Nexus-Alpha1 of https://github.com/jernejsk/FFmpeg and ffmpeg (Rockchip): drop max slices patch --- .../ffmpeg-001-v4l2-request.patch | 1180 +++++------------ ...v4l2request-hevc-increase-max-slices.patch | 25 - 2 files changed, 316 insertions(+), 889 deletions(-) delete mode 100644 projects/Rockchip/patches/ffmpeg/ffmpeg-0004-v4l2request-hevc-increase-max-slices.patch diff --git a/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch b/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch index 657eae7f63..6afdb2d738 100644 --- a/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch +++ b/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch @@ -1,7 +1,7 @@ -From b7afcc4052e9d70408adc97ee2eb3ce91d8e1baf Mon Sep 17 00:00:00 2001 +From 46ce980905101822ca824243635d10d660172570 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 3 Dec 2018 23:48:04 +0100 -Subject: [PATCH 01/17] avutil: add av_buffer_pool_flush() +Subject: [PATCH 01/12] avutil: add av_buffer_pool_flush() Used by V4L2 request API hwaccel @@ -52,19 +52,20 @@ index 241a80ed67..f41363faf1 100644 * Mark the pool as being available for freeing. It will actually be freed only * once all the allocated buffers associated with the pool are released. Thus it -From 08aeda51103a1382d5d55fa205c1795eb783217a Mon Sep 17 00:00:00 2001 +From 6f3b6c4d442a9a3322305e5600ce7f84af5971cc Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 02/17] Add common V4L2 request API code +Subject: [PATCH 02/12] Add common V4L2 request API code Signed-off-by: Jonas Karlman +Signed-off-by: Alex Bee --- - configure | 12 + - libavcodec/Makefile | 1 + - libavcodec/hwconfig.h | 2 + - libavcodec/v4l2_request.c | 984 ++++++++++++++++++++++++++++++++++++++ - libavcodec/v4l2_request.h | 77 +++ - 5 files changed, 1076 insertions(+) + configure | 12 + + libavcodec/Makefile | 1 + + libavcodec/hwconfig.h | 2 + + libavcodec/v4l2_request.c | 1027 +++++++++++++++++++++++++++++++++++++ + libavcodec/v4l2_request.h | 77 +++ + 5 files changed, 1119 insertions(+) create mode 100644 libavcodec/v4l2_request.c create mode 100644 libavcodec/v4l2_request.h @@ -167,10 +168,10 @@ index f421dc909f..ee78d8ab8e 100644 &(const AVCodecHWConfigInternal) { \ diff --git a/libavcodec/v4l2_request.c b/libavcodec/v4l2_request.c new file mode 100644 -index 0000000000..5234b5049b +index 0000000000..b57bbf29bc --- /dev/null +++ b/libavcodec/v4l2_request.c -@@ -0,0 +1,984 @@ +@@ -0,0 +1,1027 @@ +/* + * This file is part of FFmpeg. + * @@ -518,6 +519,42 @@ index 0000000000..5234b5049b + return v4l2_request_queue_decode(avctx, frame, control, count, 1, 1); +} + ++static int v4l2_request_try_framesize(AVCodecContext *avctx, uint32_t pixelformat) ++{ ++ V4L2RequestContext *ctx = avctx->internal->hwaccel_priv_data; ++ struct v4l2_frmsizeenum frmsize = { ++ .index = 0, ++ .pixel_format = pixelformat, ++ }; ++ ++ if (ioctl(ctx->video_fd, VIDIOC_ENUM_FRAMESIZES, &frmsize) < 0) ++ return 0; ++ ++ /* ++ * We only validate min/max framesize for V4L2_FRMSIZE_TYPE_STEPWISE here, since the alignment ++ * which is eventually needed will be done driver-side later in VIDIOC_S_FMT and there is no need ++ * validate step_width/step_height here ++ */ ++ ++ do { ++ ++ if (frmsize.type == V4L2_FRMSIZE_TYPE_DISCRETE && frmsize.discrete.width == avctx->coded_width && ++ frmsize.discrete.height == avctx->coded_height) ++ return 0; ++ else if ((frmsize.type == V4L2_FRMSIZE_TYPE_STEPWISE || frmsize.type == V4L2_FRMSIZE_TYPE_CONTINUOUS) && ++ avctx->coded_width >= frmsize.stepwise.min_width && avctx->coded_height >= frmsize.stepwise.min_height && ++ avctx->coded_width <= frmsize.stepwise.max_width && avctx->coded_height <= frmsize.stepwise.max_height) ++ return 0; ++ ++ frmsize.index++; ++ ++ } while (ioctl(ctx->video_fd, VIDIOC_ENUM_FRAMESIZES, &frmsize) >= 0); ++ ++ av_log(avctx, AV_LOG_INFO, "%s: pixelformat %u not supported for width %u height %u\n", __func__, pixelformat, avctx->coded_width, avctx->coded_height); ++ ++ return -1; ++} ++ +static int v4l2_request_try_format(AVCodecContext *avctx, enum v4l2_buf_type type, uint32_t pixelformat) +{ + V4L2RequestContext *ctx = avctx->internal->hwaccel_priv_data; @@ -685,6 +722,13 @@ index 0000000000..5234b5049b + goto fail; + } + ++ ret = v4l2_request_try_framesize(avctx, pixelformat); ++ if (ret < 0) { ++ av_log(avctx, AV_LOG_WARNING, "%s: try framesize failed\n", __func__); ++ ret = AVERROR(EINVAL); ++ goto fail; ++ } ++ + ret = v4l2_request_set_format(avctx, ctx->output_type, pixelformat, buffersize); + if (ret < 0) { + av_log(avctx, AV_LOG_ERROR, "%s: set output format failed, %s (%d)\n", __func__, strerror(errno), errno); @@ -1239,10 +1283,10 @@ index 0000000000..58d2aa70af + +#endif /* AVCODEC_V4L2_REQUEST_H */ -From ae79312604208dd0cceaf4c48963579056ccafee Mon Sep 17 00:00:00 2001 +From 3a8ac13e041cec840d3cd1e83e6294a1a47ac6df Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Wed, 20 Feb 2019 11:18:00 -0300 -Subject: [PATCH 03/17] h264dec: add idr_pic_id to slice context +Subject: [PATCH 03/12] h264dec: add idr_pic_id to slice context Used by V4L2 request API h264 hwaccel @@ -1279,10 +1323,10 @@ index b7b19ba4f1..0698ab95ba 100644 /** -From 5257b2741d7cfb88233ebd00a6ba3b6bda1f3cf2 Mon Sep 17 00:00:00 2001 +From e7f515597ca5f0900f3bd08ef40bb517703433bc Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Wed, 22 May 2019 14:44:22 +0200 -Subject: [PATCH 04/17] h264dec: add ref_pic_marking and pic_order_cnt bit_size +Subject: [PATCH 04/12] h264dec: add ref_pic_marking and pic_order_cnt bit_size to slice context Used by V4L2 request API h264 hwaccel @@ -1356,10 +1400,10 @@ index 0698ab95ba..2b39e82c3b 100644 /** -From bfd0f2970a9e84d049fb6a3f60051f307b4e9d69 Mon Sep 17 00:00:00 2001 +From 9f455a7adb8cabb575049204375cc3b8d97b2c86 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 05/17] Add V4L2 request API h264 hwaccel +Subject: [PATCH 05/12] Add V4L2 request API h264 hwaccel Signed-off-by: Jernej Skrabec Signed-off-by: Jonas Karlman @@ -1917,10 +1961,10 @@ index 0000000000..394bae0550 + .caps_internal = HWACCEL_CAP_ASYNC_SAFE, +}; -From fb84a34c8e4465d47946abecbf3f5df8f8920cbe Mon Sep 17 00:00:00 2001 +From 1ffea498d7e1000acbaa456bb52e26757779622a Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 06/17] Add V4L2 request API mpeg2 hwaccel +Subject: [PATCH 06/12] Add V4L2 request API mpeg2 hwaccel Signed-off-by: Jonas Karlman --- @@ -2167,10 +2211,10 @@ index 0000000000..84d53209c7 + .caps_internal = HWACCEL_CAP_ASYNC_SAFE, +}; -From bd1adf7ea2a3592eef7b2524fe0fed06a56a1771 Mon Sep 17 00:00:00 2001 +From 2190df619ea9d9cedf3d3c7442de0dc863c8b62e Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Wed, 22 May 2019 14:46:58 +0200 -Subject: [PATCH 07/17] Add V4L2 request API vp8 hwaccel +Subject: [PATCH 07/12] Add V4L2 request API vp8 hwaccel Signed-off-by: Boris Brezillon Signed-off-by: Ezequiel Garcia @@ -2440,21 +2484,22 @@ index d16e7b6aa3..8ee768d875 100644 NULL }, -From fd0b19baa147bad74b2481a53972fec1988fb9e4 Mon Sep 17 00:00:00 2001 +From 4886d1e8caeee49c6ca4d92bc1eaebcdb884924c Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 08/17] Add V4L2 request API hevc hwaccel +Subject: [PATCH 08/12] Add V4L2 request API hevc hwaccel Signed-off-by: Jernej Skrabec Signed-off-by: Jonas Karlman Signed-off-by: Benjamin Gaignard +Signed-off-by: Alex Bee --- configure | 3 + libavcodec/Makefile | 1 + libavcodec/hevcdec.c | 10 + libavcodec/hwaccels.h | 1 + - libavcodec/v4l2_request_hevc.c | 578 +++++++++++++++++++++++++++++++++ - 5 files changed, 593 insertions(+) + libavcodec/v4l2_request_hevc.c | 681 +++++++++++++++++++++++++++++++++ + 5 files changed, 696 insertions(+) create mode 100644 libavcodec/v4l2_request_hevc.c diff --git a/configure b/configure @@ -2546,10 +2591,10 @@ index 9f8d41e367..ffb9fa5087 100644 extern const AVHWAccel ff_hevc_videotoolbox_hwaccel; diff --git a/libavcodec/v4l2_request_hevc.c b/libavcodec/v4l2_request_hevc.c new file mode 100644 -index 0000000000..eaedde0d86 +index 0000000000..c12748ed03 --- /dev/null +++ b/libavcodec/v4l2_request_hevc.c -@@ -0,0 +1,578 @@ +@@ -0,0 +1,681 @@ +/* + * This file is part of FFmpeg. + * @@ -2572,7 +2617,8 @@ index 0000000000..eaedde0d86 +#include "hwconfig.h" +#include "v4l2_request.h" + -+#define MAX_SLICES 16 ++#define MAX_SLICES 600 // as per HEVC spec ? ++#define V4L2_HEVC_CONTROLS_MAX 6 + +typedef struct V4L2RequestControlsHEVC { + struct v4l2_ctrl_hevc_sps sps; @@ -2580,15 +2626,20 @@ index 0000000000..eaedde0d86 + struct v4l2_ctrl_hevc_decode_params dec_params; + struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix; + struct v4l2_ctrl_hevc_slice_params slice_params[MAX_SLICES]; ++ __u32 *entry_point_offsets; ++ unsigned int num_entry_point_offsets; + int first_slice; -+ int num_slices; //TODO: this should be in control ++ int num_slices; +} V4L2RequestControlsHEVC; + +typedef struct V4L2RequestContextHEVC { + V4L2RequestContext base; -+ int decode_mode; -+ int start_code; -+ int max_slices; ++ unsigned int decode_mode; ++ unsigned int start_code; ++ __u32 max_slices; ++ unsigned int supports_entry_point_offsets; ++ unsigned int supports_slices; ++ unsigned int supports_scaling_matrix; +} V4L2RequestContextHEVC; + +static uint8_t nalu_slice_start_code[] = { 0x00, 0x00, 0x01 }; @@ -2660,6 +2711,8 @@ index 0000000000..eaedde0d86 + + *dec_params = (struct v4l2_ctrl_hevc_decode_params) { + .pic_order_cnt_val = pic->poc, /* FIXME: is this same as slice_params->slice_pic_order_cnt ? */ ++ .short_term_ref_pic_set_size = sh->short_term_ref_pic_set_size, ++ .long_term_ref_pic_set_size = sh->long_term_ref_pic_set_size, + .num_poc_st_curr_before = h->rps[ST_CURR_BEF].nb_refs, + .num_poc_st_curr_after = h->rps[ST_CURR_AFT].nb_refs, + .num_poc_lt_curr = h->rps[LT_CURR].nb_refs, @@ -2676,7 +2729,6 @@ index 0000000000..eaedde0d86 + if (frame->flags & HEVC_FRAME_FLAG_LONG_REF) + entry->flags |= V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE; + -+ /* TODO: Interleaved: Get the POC for each field. */ + entry->pic_order_cnt_val = frame->poc; + } + } @@ -2689,7 +2741,6 @@ index 0000000000..eaedde0d86 + if (IS_IDR(h)) + dec_params->flags |= V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC; + -+ /* FIXME: is this really frame property? */ + if (sh->no_output_of_prior_pics_flag) + dec_params->flags |= V4L2_HEVC_DECODE_PARAM_FLAG_NO_OUTPUT_OF_PRIOR; + @@ -2700,10 +2751,12 @@ index 0000000000..eaedde0d86 + } +} + -+static void v4l2_request_hevc_fill_slice_params(const HEVCContext *h, -+ struct v4l2_ctrl_hevc_decode_params *dec_params, -+ struct v4l2_ctrl_hevc_slice_params *slice_params) ++static int v4l2_request_hevc_fill_slice_params(const HEVCContext *h, ++ V4L2RequestControlsHEVC *controls, ++ int slice) +{ ++ struct v4l2_ctrl_hevc_slice_params *slice_params = &controls->slice_params[slice]; ++ struct v4l2_ctrl_hevc_decode_params *dec_params = &controls->dec_params; + const HEVCFrame *pic = h->ref; + const SliceHeader *sh = &h->sh; + RefPicList *rpl; @@ -2711,10 +2764,8 @@ index 0000000000..eaedde0d86 + + *slice_params = (struct v4l2_ctrl_hevc_slice_params) { + .bit_size = 0, -+ .data_bit_offset = get_bits_count(&h->HEVClc->gb), -+ -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ -+ .slice_segment_addr = sh->slice_segment_addr, ++ .data_byte_offset = (get_bits_count(&h->HEVClc->gb) + 1 + 7) / 8, ++ .num_entry_point_offsets = sh->num_entry_point_offsets, + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */ + .nal_unit_type = h->nal_unit_type, @@ -2739,6 +2790,11 @@ index 0000000000..eaedde0d86 + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture timing SEI message */ + .pic_struct = h->sei.picture_timing.picture_struct, ++ ++ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ ++ .slice_segment_addr = sh->slice_segment_addr, ++ .short_term_ref_pic_set_size = sh->short_term_ref_pic_set_size, ++ .long_term_ref_pic_set_size = sh->long_term_ref_pic_set_size, + }; + + if (sh->slice_sample_adaptive_offset_flag[0]) @@ -2759,6 +2815,8 @@ index 0000000000..eaedde0d86 + if (sh->collocated_list == L0) + slice_params->flags |= V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0; + ++ /* TODO: V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV */ ++ + if (sh->disable_deblocking_filter_flag) + slice_params->flags |= V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED; + @@ -2781,14 +2839,30 @@ index 0000000000..eaedde0d86 + } + + v4l2_request_hevc_fill_pred_table(h, &slice_params->pred_weight_table); ++ ++ if (controls->num_entry_point_offsets < sh->num_entry_point_offsets) { ++ av_freep(&controls->entry_point_offsets); ++ controls->entry_point_offsets = av_mallocz(sizeof(*controls->entry_point_offsets) * sh->num_entry_point_offsets); ++ if (!controls->entry_point_offsets) ++ return AVERROR(ENOMEM); ++ controls->num_entry_point_offsets = sh->num_entry_point_offsets; ++ } ++ ++ for (i = 0; i < sh->num_entry_point_offsets; i++) ++ controls->entry_point_offsets[i] = sh->entry_point_offset[i]; ++ ++ return 0; +} + +static void fill_sps(struct v4l2_ctrl_hevc_sps *ctrl, const HEVCContext *h) +{ + const HEVCSPS *sps = h->ps.sps; ++ const HEVCPPS *pps = h->ps.pps; + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ + *ctrl = (struct v4l2_ctrl_hevc_sps) { ++ .video_parameter_set_id = sps->vps_id, ++ .seq_parameter_set_id = pps->sps_id, + .pic_width_in_luma_samples = sps->width, + .pic_height_in_luma_samples = sps->height, + .bit_depth_luma_minus8 = sps->bit_depth - 8, @@ -2853,6 +2927,7 @@ index 0000000000..eaedde0d86 + sps->scaling_list_enable_flag ? + &sps->scaling_list : NULL; + V4L2RequestControlsHEVC *controls = h->ref->hwaccel_picture_private; ++ const SliceHeader *sh = &h->sh; + + fill_sps(&controls->sps, h); + fill_dec_params(&controls->dec_params, h); @@ -2875,6 +2950,7 @@ index 0000000000..eaedde0d86 + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ + controls->pps = (struct v4l2_ctrl_hevc_pps) { ++ .pic_parameter_set_id = sh->pps_id, + .num_extra_slice_header_bits = pps->num_extra_slice_header_bits, + .num_ref_idx_l0_default_active_minus1 = pps->num_ref_idx_l0_default_active - 1, + .num_ref_idx_l1_default_active_minus1 = pps->num_ref_idx_l1_default_active - 1, @@ -2963,6 +3039,7 @@ index 0000000000..eaedde0d86 + + controls->first_slice = 1; + controls->num_slices = 0; ++ controls->num_entry_point_offsets = 0; + + return ff_v4l2_request_reset_frame(avctx, h->ref->frame); +} @@ -2971,40 +3048,58 @@ index 0000000000..eaedde0d86 +{ + const HEVCContext *h = avctx->priv_data; + V4L2RequestControlsHEVC *controls = h->ref->hwaccel_picture_private; ++ struct v4l2_ctrl_hevc_slice_params *first_slice_params = &controls->slice_params[0]; + V4L2RequestContextHEVC *ctx = avctx->internal->hwaccel_priv_data; ++ int num_controls = 0; + -+ struct v4l2_ext_control control[] = { -+ { -+ .id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, ++ struct v4l2_ext_control control[V4L2_HEVC_CONTROLS_MAX] = {}; ++ ++ control[num_controls++] = (struct v4l2_ext_control) { ++ .id = V4L2_CID_STATELESS_HEVC_SPS, + .ptr = &controls->sps, + .size = sizeof(controls->sps), -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_HEVC_PPS, -+ .ptr = &controls->pps, -+ .size = sizeof(controls->pps), -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS, -+ .ptr = &controls->dec_params, -+ .size = sizeof(controls->dec_params), -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX, -+ .ptr = &controls->scaling_matrix, -+ .size = sizeof(controls->scaling_matrix), -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS, -+ .ptr = &controls->slice_params, -+ .size = sizeof(controls->slice_params[0]) * FFMAX(FFMIN(controls->num_slices, MAX_SLICES), ctx->max_slices), -+ }, + }; + -+ if (ctx->decode_mode == V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED) -+ return ff_v4l2_request_decode_slice(avctx, h->ref->frame, control, FF_ARRAY_ELEMS(control), controls->first_slice, last_slice); ++ control[num_controls++] = (struct v4l2_ext_control) { ++ .id = V4L2_CID_STATELESS_HEVC_PPS, ++ .ptr = &controls->pps, ++ .size = sizeof(controls->pps), ++ }; + -+ return ff_v4l2_request_decode_frame(avctx, h->ref->frame, control, FF_ARRAY_ELEMS(control)); ++ control[num_controls++] = (struct v4l2_ext_control) { ++ .id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, ++ .ptr = &controls->dec_params, ++ .size = sizeof(controls->dec_params), ++ }; ++ ++ if (ctx->supports_scaling_matrix) { ++ control[num_controls++] = (struct v4l2_ext_control) { ++ .id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, ++ .ptr = &controls->scaling_matrix, ++ .size = sizeof(controls->scaling_matrix), ++ }; ++ } ++ ++ if (ctx->supports_slices) { ++ control[num_controls++] = (struct v4l2_ext_control) { ++ .id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS, ++ .ptr = &controls->slice_params, ++ .size = sizeof(*first_slice_params) * controls->num_slices, ++ }; ++ } ++ //this assumes that decoders supporting entry_point_offsets submit a single slice per request ++ if (ctx->supports_entry_point_offsets && first_slice_params->num_entry_point_offsets > 0) { ++ control[num_controls++] = (struct v4l2_ext_control) { ++ .id = V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS, ++ .ptr = controls->entry_point_offsets, ++ .size = sizeof(*controls->entry_point_offsets) * first_slice_params->num_entry_point_offsets, ++ }; ++ } ++ ++ if (ctx->decode_mode == V4L2_STATELESS_HEVC_DECODE_MODE_SLICE_BASED) ++ return ff_v4l2_request_decode_slice(avctx, h->ref->frame, control, num_controls, controls->first_slice, last_slice); ++ ++ return ff_v4l2_request_decode_frame(avctx, h->ref->frame, control, num_controls); +} + +static int v4l2_request_hevc_decode_slice(AVCodecContext *avctx, const uint8_t *buffer, uint32_t size) @@ -3015,7 +3110,7 @@ index 0000000000..eaedde0d86 + V4L2RequestDescriptor *req = (V4L2RequestDescriptor*)h->ref->frame->data[0]; + int ret, slice = FFMIN(controls->num_slices, MAX_SLICES - 1); + -+ if (ctx->decode_mode == V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED && slice) { ++ if (ctx->decode_mode == V4L2_STATELESS_HEVC_DECODE_MODE_SLICE_BASED && slice) { + ret = v4l2_request_hevc_queue_decode(avctx, 0); + if (ret) + return ret; @@ -3025,9 +3120,11 @@ index 0000000000..eaedde0d86 + controls->first_slice = 0; + } + -+ v4l2_request_hevc_fill_slice_params(h, &controls->dec_params, &controls->slice_params[slice]); ++ ret = v4l2_request_hevc_fill_slice_params(h, controls, slice); ++ if (ret) ++ return ret; + -+ if (ctx->start_code == V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B) { ++ if (ctx->start_code == V4L2_STATELESS_HEVC_START_CODE_ANNEX_B) { + ret = ff_v4l2_request_append_output_buffer(avctx, h->ref->frame, nalu_slice_start_code, 3); + if (ret) + return ret; @@ -3044,7 +3141,15 @@ index 0000000000..eaedde0d86 + +static int v4l2_request_hevc_end_frame(AVCodecContext *avctx) +{ -+ return v4l2_request_hevc_queue_decode(avctx, 1); ++ const HEVCContext *h = avctx->priv_data; ++ V4L2RequestControlsHEVC *controls = h->ref->hwaccel_picture_private; ++ int ret; ++ ++ ret = v4l2_request_hevc_queue_decode(avctx, 1); ++ ++ av_freep(&controls->entry_point_offsets); ++ ++ return ret; +} + +static int v4l2_request_hevc_set_controls(AVCodecContext *avctx) @@ -3053,37 +3158,80 @@ index 0000000000..eaedde0d86 + int ret; + + struct v4l2_ext_control control[] = { -+ { .id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE, }, -+ { .id = V4L2_CID_MPEG_VIDEO_HEVC_START_CODE, }, ++ { .id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, }, ++ { .id = V4L2_CID_STATELESS_HEVC_START_CODE, }, ++ }; ++ struct v4l2_query_ext_ctrl entry_point_offsets = { ++ .id = V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS, + }; + struct v4l2_query_ext_ctrl slice_params = { -+ .id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS, ++ .id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS, ++ }; ++ struct v4l2_query_ext_ctrl scaling_matrix = { ++ .id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, + }; + -+ ctx->decode_mode = ff_v4l2_request_query_control_default_value(avctx, V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE); -+ if (ctx->decode_mode != V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED && -+ ctx->decode_mode != V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED) { ++ ctx->decode_mode = ff_v4l2_request_query_control_default_value(avctx, V4L2_CID_STATELESS_HEVC_DECODE_MODE); ++ if (ctx->decode_mode != V4L2_STATELESS_HEVC_DECODE_MODE_SLICE_BASED && ++ ctx->decode_mode != V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED) { + av_log(avctx, AV_LOG_ERROR, "%s: unsupported decode mode, %d\n", __func__, ctx->decode_mode); + return AVERROR(EINVAL); + } + -+ ctx->start_code = ff_v4l2_request_query_control_default_value(avctx, V4L2_CID_MPEG_VIDEO_HEVC_START_CODE); -+ if (ctx->start_code != V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE && -+ ctx->start_code != V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B) { ++ ctx->start_code = ff_v4l2_request_query_control_default_value(avctx, V4L2_CID_STATELESS_HEVC_START_CODE); ++ if (ctx->start_code != V4L2_STATELESS_HEVC_START_CODE_NONE && ++ ctx->start_code != V4L2_STATELESS_HEVC_START_CODE_ANNEX_B) { + av_log(avctx, AV_LOG_ERROR, "%s: unsupported start code, %d\n", __func__, ctx->start_code); + return AVERROR(EINVAL); + } + -+ ret = ff_v4l2_request_query_control(avctx, &slice_params); -+ if (ret) -+ return ret; -+ -+ ctx->max_slices = slice_params.elems; -+ if (ctx->max_slices > MAX_SLICES) { -+ av_log(avctx, AV_LOG_ERROR, "%s: unsupported max slices, %d\n", __func__, ctx->max_slices); -+ return AVERROR(EINVAL); ++ ret = ff_v4l2_request_query_control(avctx, &entry_point_offsets); ++ if (ret) { ++ ctx->supports_entry_point_offsets = 0; ++ } else { ++ ctx->supports_entry_point_offsets = 1; + } + ++ ret = ff_v4l2_request_query_control(avctx, &slice_params); ++ if (ret) { ++ ctx->supports_slices = 0; ++ ctx->max_slices = 0; ++ if (ctx->decode_mode == V4L2_STATELESS_HEVC_DECODE_MODE_SLICE_BASED) { ++ av_log(avctx, AV_LOG_ERROR, "%s: decoder is slice-based, \ ++ but doesn't support V4L2_CID_STATELESS_HEVC_SLICE_PARAMS control \n", __func__); ++ return AVERROR(EINVAL); ++ } ++ ++ if (ctx->supports_entry_point_offsets) { ++ av_log(avctx, AV_LOG_ERROR, "%s: decoder supports entry_point_offsets, \ ++ but doesn't support V4L2_CID_STATELESS_HEVC_SLICE_PARAMS control \n", __func__); ++ return AVERROR(EINVAL); ++ } ++ } else { ++ ctx->supports_slices = 1; ++ ctx->max_slices = slice_params.dims[0]; ++ if (ctx->max_slices > MAX_SLICES) { ++ av_log(avctx, AV_LOG_ERROR, "%s: unsupported max slices, %u\n", __func__, ctx->max_slices); ++ return AVERROR(EINVAL); ++ } ++ } ++ ++ ret = ff_v4l2_request_query_control(avctx, &scaling_matrix); ++ if (ret) { ++ ctx->supports_scaling_matrix = 0; ++ } else { ++ ctx->supports_scaling_matrix = 1; ++ } ++ ++ av_log(avctx, AV_LOG_DEBUG, "%s: decoder is %s and supports slices %d, supports entry_point_offsets: %d supports scaling_matrix: %d max slices: %u\n", ++ __func__, ++ ctx->decode_mode == V4L2_STATELESS_HEVC_DECODE_MODE_SLICE_BASED ? "slice based" : "frame based", ++ ctx->supports_slices, ++ ctx->supports_entry_point_offsets, ++ ctx->supports_scaling_matrix, ++ ctx->max_slices ++ ); ++ + control[0].value = ctx->decode_mode; + control[1].value = ctx->start_code; + @@ -3098,7 +3246,7 @@ index 0000000000..eaedde0d86 + + struct v4l2_ext_control control[] = { + { -+ .id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, ++ .id = V4L2_CID_STATELESS_HEVC_SPS, + .ptr = &sps, + .size = sizeof(sps), + }, @@ -3129,10 +3277,10 @@ index 0000000000..eaedde0d86 + .caps_internal = HWACCEL_CAP_ASYNC_SAFE, +}; -From 9c2eaf2e2d5ee78d311ef90fc58987b528afe437 Mon Sep 17 00:00:00 2001 +From 44f20a53f2ef6ad0ecfb413ebcc95f92fc17377f Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Thu, 12 Dec 2019 16:13:55 +0100 -Subject: [PATCH 09/17] Add V4L2 request API VP9 hwaccel +Subject: [PATCH 09/12] Add V4L2 request API VP9 hwaccel Signed-off-by: Boris Brezillon Signed-off-by: Jernej Skrabec @@ -3140,11 +3288,11 @@ Signed-off-by: Jernej Skrabec configure | 3 + libavcodec/Makefile | 1 + libavcodec/hwaccels.h | 1 + - libavcodec/v4l2_request_vp9.c | 268 ++++++++++++++++++++++++++++++++++ - libavcodec/vp9.c | 192 +++++++++++++++++------- + libavcodec/v4l2_request_vp9.c | 282 ++++++++++++++++++++++++++++++++++ + libavcodec/vp9.c | 192 ++++++++++++++++------- libavcodec/vp9dec.h | 4 + libavcodec/vp9shared.h | 1 + - 7 files changed, 415 insertions(+), 55 deletions(-) + 7 files changed, 429 insertions(+), 55 deletions(-) create mode 100644 libavcodec/v4l2_request_vp9.c diff --git a/configure b/configure @@ -3194,10 +3342,10 @@ index ffb9fa5087..fc5d0b0479 100644 extern const AVHWAccel ff_wmv3_d3d11va_hwaccel; diff --git a/libavcodec/v4l2_request_vp9.c b/libavcodec/v4l2_request_vp9.c new file mode 100644 -index 0000000000..9b95c76cdb +index 0000000000..ec0300f66d --- /dev/null +++ b/libavcodec/v4l2_request_vp9.c -@@ -0,0 +1,268 @@ +@@ -0,0 +1,282 @@ +/* + * This file is part of FFmpeg. + * @@ -3222,78 +3370,62 @@ index 0000000000..9b95c76cdb + +typedef struct V4L2RequestControlsVP9 { + struct v4l2_ctrl_vp9_frame decode_params; ++ struct v4l2_ctrl_vp9_compressed_hdr chp; +} V4L2RequestControlsVP9; + -+static int v4l2_request_vp9_set_frame_ctx(AVCodecContext *avctx) ++static void v4l2_request_vp9_set_frame_ctx(AVCodecContext *avctx) +{ + VP9Context *s = avctx->priv_data; -+ struct v4l2_ctrl_vp9_compressed_hdr chp; -+ struct v4l2_ext_control control[] = { -+ { -+ .id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR, -+ .ptr = &chp, -+ .size = sizeof(chp), -+ }, -+ }; ++ const VP9Frame *f = &s->s.frames[CUR_FRAME]; ++ V4L2RequestControlsVP9 *controls = f->hwaccel_picture_private; ++ struct v4l2_ctrl_vp9_compressed_hdr *chp = &controls->chp; + -+ memset(&chp, 0, sizeof(chp)); ++ memset(chp, 0, sizeof(&chp)); + -+ chp.tx_mode = s->s.h.txfmmode; -+ memcpy(chp.tx8, s->prob_raw.p.tx8p, sizeof(s->prob_raw.p.tx8p)); -+ memcpy(chp.tx16, s->prob_raw.p.tx16p, sizeof(s->prob_raw.p.tx16p)); -+ memcpy(chp.tx32, s->prob_raw.p.tx32p, sizeof(s->prob_raw.p.tx32p)); ++ chp->tx_mode = s->s.h.txfmmode; ++ memcpy(chp->tx8, s->prob_raw.p.tx8p, sizeof(s->prob_raw.p.tx8p)); ++ memcpy(chp->tx16, s->prob_raw.p.tx16p, sizeof(s->prob_raw.p.tx16p)); ++ memcpy(chp->tx32, s->prob_raw.p.tx32p, sizeof(s->prob_raw.p.tx32p)); + for (unsigned i = 0; i < 4; i++) { + for (unsigned j = 0; j < 2; j++) { + for (unsigned k = 0; k < 2; k++) { + for (unsigned l = 0; l < 6; l++) { + for (unsigned m = 0; m < 6; m++) { -+ memcpy(chp.coef[i][j][k][l][m], s->prob_raw.coef[i][j][k][l][m], sizeof(chp.coef[0][0][0][0][0])); ++ memcpy(chp->coef[i][j][k][l][m], s->prob_raw.coef[i][j][k][l][m], sizeof(chp->coef[0][0][0][0][0])); + } + } + } + } + } -+ memcpy(chp.skip, s->prob_raw.p.skip, sizeof(s->prob_raw.p.skip)); -+ memcpy(chp.inter_mode, s->prob_raw.p.mv_mode, sizeof(s->prob_raw.p.mv_mode)); -+ memcpy(chp.interp_filter, s->prob_raw.p.filter, sizeof(s->prob_raw.p.filter)); -+ memcpy(chp.is_inter, s->prob_raw.p.intra, sizeof(s->prob_raw.p.intra)); -+ memcpy(chp.comp_mode, s->prob_raw.p.comp, sizeof(s->prob_raw.p.comp)); -+ memcpy(chp.single_ref, s->prob_raw.p.single_ref, sizeof(s->prob_raw.p.single_ref)); -+ memcpy(chp.comp_ref, s->prob_raw.p.comp_ref, sizeof(s->prob_raw.p.comp_ref)); -+ memcpy(chp.y_mode, s->prob_raw.p.y_mode, sizeof(s->prob_raw.p.y_mode)); ++ memcpy(chp->skip, s->prob_raw.p.skip, sizeof(s->prob_raw.p.skip)); ++ memcpy(chp->inter_mode, s->prob_raw.p.mv_mode, sizeof(s->prob_raw.p.mv_mode)); ++ memcpy(chp->interp_filter, s->prob_raw.p.filter, sizeof(s->prob_raw.p.filter)); ++ memcpy(chp->is_inter, s->prob_raw.p.intra, sizeof(s->prob_raw.p.intra)); ++ memcpy(chp->comp_mode, s->prob_raw.p.comp, sizeof(s->prob_raw.p.comp)); ++ memcpy(chp->single_ref, s->prob_raw.p.single_ref, sizeof(s->prob_raw.p.single_ref)); ++ memcpy(chp->comp_ref, s->prob_raw.p.comp_ref, sizeof(s->prob_raw.p.comp_ref)); ++ memcpy(chp->y_mode, s->prob_raw.p.y_mode, sizeof(s->prob_raw.p.y_mode)); + for (unsigned i = 0; i < 10; i++) -+ memcpy(chp.uv_mode[i], s->prob.p.uv_mode[i], sizeof(s->prob.p.uv_mode[0])); ++ memcpy(chp->uv_mode[i], s->prob.p.uv_mode[i], sizeof(s->prob.p.uv_mode[0])); + for (unsigned i = 0; i < 4; i++) -+ memcpy(chp.partition[i * 4], s->prob_raw.p.partition[i], sizeof(s->prob_raw.p.partition[0])); -+ memcpy(chp.mv.joint, s->prob_raw.p.mv_joint, sizeof(s->prob_raw.p.mv_joint)); ++ memcpy(chp->partition[i * 4], s->prob_raw.p.partition[i], sizeof(s->prob_raw.p.partition[0])); ++ memcpy(chp->mv.joint, s->prob_raw.p.mv_joint, sizeof(s->prob_raw.p.mv_joint)); + for (unsigned i = 0; i < 2; i++) { -+ chp.mv.sign[i] = s->prob_raw.p.mv_comp[i].sign; -+ memcpy(chp.mv.classes[i], s->prob_raw.p.mv_comp[i].classes, sizeof(s->prob_raw.p.mv_comp[0].classes)); -+ chp.mv.class0_bit[i] = s->prob_raw.p.mv_comp[i].class0; -+ memcpy(chp.mv.bits[i], s->prob_raw.p.mv_comp[i].bits, sizeof(s->prob_raw.p.mv_comp[0].bits)); -+ memcpy(chp.mv.class0_fr[i], s->prob_raw.p.mv_comp[i].class0_fp, sizeof(s->prob_raw.p.mv_comp[0].class0_fp)); -+ memcpy(chp.mv.fr[i], s->prob_raw.p.mv_comp[i].fp, sizeof(s->prob_raw.p.mv_comp[0].fp)); -+ chp.mv.class0_hp[i] = s->prob_raw.p.mv_comp[i].class0_hp; -+ chp.mv.hp[i] = s->prob_raw.p.mv_comp[i].hp; ++ chp->mv.sign[i] = s->prob_raw.p.mv_comp[i].sign; ++ memcpy(chp->mv.classes[i], s->prob_raw.p.mv_comp[i].classes, sizeof(s->prob_raw.p.mv_comp[0].classes)); ++ chp->mv.class0_bit[i] = s->prob_raw.p.mv_comp[i].class0; ++ memcpy(chp->mv.bits[i], s->prob_raw.p.mv_comp[i].bits, sizeof(s->prob_raw.p.mv_comp[0].bits)); ++ memcpy(chp->mv.class0_fr[i], s->prob_raw.p.mv_comp[i].class0_fp, sizeof(s->prob_raw.p.mv_comp[0].class0_fp)); ++ memcpy(chp->mv.fr[i], s->prob_raw.p.mv_comp[i].fp, sizeof(s->prob_raw.p.mv_comp[0].fp)); ++ chp->mv.class0_hp[i] = s->prob_raw.p.mv_comp[i].class0_hp; ++ chp->mv.hp[i] = s->prob_raw.p.mv_comp[i].hp; + } -+ -+ return ff_v4l2_request_set_controls(avctx, control, FF_ARRAY_ELEMS(control)); +} + -+static int v4l2_request_vp9_start_frame(AVCodecContext *avctx, -+ av_unused const uint8_t *buffer, -+ av_unused uint32_t size) ++static void fill_frame(struct v4l2_ctrl_vp9_frame *dec_params, AVCodecContext *avctx) +{ + const VP9Context *s = avctx->priv_data; -+ const VP9Frame *f = &s->s.frames[CUR_FRAME]; -+ V4L2RequestControlsVP9 *controls = f->hwaccel_picture_private; -+ struct v4l2_ctrl_vp9_frame *dec_params = &controls->decode_params; + const ThreadFrame *ref; -+ int ret; -+ -+ ret = v4l2_request_vp9_set_frame_ctx(avctx); -+ if (ret) -+ return ret; + + memset(dec_params, 0, sizeof(*dec_params)); + @@ -3408,6 +3540,19 @@ index 0000000000..9b95c76cdb + if (s->s.h.segmentation.feat[i].skip_enabled) + dec_params->seg.feature_enabled[i] |= 1 << V4L2_VP9_SEG_LVL_SKIP; + } ++} ++ ++static int v4l2_request_vp9_start_frame(AVCodecContext *avctx, ++ av_unused const uint8_t *buffer, ++ av_unused uint32_t size) ++{ ++ const VP9Context *s = avctx->priv_data; ++ const VP9Frame *f = &s->s.frames[CUR_FRAME]; ++ V4L2RequestControlsVP9 *controls = f->hwaccel_picture_private; ++ ++ v4l2_request_vp9_set_frame_ctx(avctx); ++ ++ fill_frame(&controls->decode_params, avctx); + + return ff_v4l2_request_reset_frame(avctx, f->tf.f); +} @@ -3433,6 +3578,11 @@ index 0000000000..9b95c76cdb + .ptr = &controls->decode_params, + .size = sizeof(controls->decode_params), + }, ++ { ++ .id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR, ++ .ptr = &controls->chp, ++ .size = sizeof(controls->chp), ++ }, + }; + + ret = ff_v4l2_request_decode_frame(avctx, f->tf.f, control, FF_ARRAY_ELEMS(control)); @@ -3447,8 +3597,20 @@ index 0000000000..9b95c76cdb + +static int v4l2_request_vp9_init(AVCodecContext *avctx) +{ ++ struct v4l2_ctrl_vp9_frame frame; ++ ++ struct v4l2_ext_control control[] = { ++ { ++ .id = V4L2_CID_STATELESS_VP9_FRAME, ++ .ptr = &frame, ++ .size = sizeof(frame), ++ }, ++ }; ++ ++ fill_frame(&frame, avctx); ++ + // TODO: check V4L2_CID_MPEG_VIDEO_VP9_PROFILE -+ return ff_v4l2_request_init(avctx, V4L2_PIX_FMT_VP9_FRAME, 3 * 1024 * 1024, NULL, 0); ++ return ff_v4l2_request_init(avctx, V4L2_PIX_FMT_VP9_FRAME, 3 * 1024 * 1024, control, FF_ARRAY_ELEMS(control)); +} + +const AVHWAccel ff_vp9_v4l2request_hwaccel = { @@ -3857,307 +4019,10 @@ index 54726df742..fee3568736 100644 uint8_t pred_prob[3]; struct { -From 7b0931f709e16f6f950475f6a0c52df6e14d38d8 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Thu, 14 Feb 2019 23:20:05 +0100 -Subject: [PATCH 10/17] Add and use private linux v5.19.2 headers for V4L2 - request API ctrls - -Signed-off-by: Jernej Skrabec -Signed-off-by: Jonas Karlman ---- - configure | 2 +- - libavcodec/hevc-ctrls.h | 250 +++++++++++++++++++++++++++++++++ - libavcodec/v4l2_request_hevc.c | 1 + - 3 files changed, 252 insertions(+), 1 deletion(-) - create mode 100644 libavcodec/hevc-ctrls.h - -diff --git a/configure b/configure -index 36a1271a6c..1b5121d972 100755 ---- a/configure -+++ b/configure -@@ -2968,7 +2968,7 @@ hevc_dxva2_hwaccel_deps="dxva2 DXVA_PicParams_HEVC" - hevc_dxva2_hwaccel_select="hevc_decoder" - hevc_nvdec_hwaccel_deps="nvdec" - hevc_nvdec_hwaccel_select="hevc_decoder" --hevc_v4l2request_hwaccel_deps="v4l2_request hevc_v4l2_request" -+hevc_v4l2request_hwaccel_deps="v4l2_request" - hevc_v4l2request_hwaccel_select="hevc_decoder" - hevc_vaapi_hwaccel_deps="vaapi VAPictureParameterBufferHEVC" - hevc_vaapi_hwaccel_select="hevc_decoder" -diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h -new file mode 100644 -index 0000000000..88e804578c ---- /dev/null -+++ b/libavcodec/hevc-ctrls.h -@@ -0,0 +1,250 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * These are the HEVC state controls for use with stateless HEVC -+ * codec drivers. -+ * -+ * It turns out that these structs are not stable yet and will undergo -+ * more changes. So keep them private until they are stable and ready to -+ * become part of the official public API. -+ */ -+ -+#ifndef _HEVC_CTRLS_H_ -+#define _HEVC_CTRLS_H_ -+ -+#include -+ -+/* The pixel format isn't stable at the moment and will likely be renamed. */ -+#define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */ -+ -+#define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_CODEC_BASE + 1008) -+#define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_CODEC_BASE + 1009) -+#define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_CODEC_BASE + 1010) -+#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_CODEC_BASE + 1011) -+#define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS (V4L2_CID_CODEC_BASE + 1012) -+#define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_CODEC_BASE + 1015) -+#define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_CODEC_BASE + 1016) -+ -+/* enum v4l2_ctrl_type type values */ -+#define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 -+#define V4L2_CTRL_TYPE_HEVC_PPS 0x0121 -+#define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122 -+#define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0123 -+#define V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS 0x0124 -+ -+enum v4l2_mpeg_video_hevc_decode_mode { -+ V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED, -+ V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED, -+}; -+ -+enum v4l2_mpeg_video_hevc_start_code { -+ V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE, -+ V4L2_MPEG_VIDEO_HEVC_START_CODE_ANNEX_B, -+}; -+ -+#define V4L2_HEVC_SLICE_TYPE_B 0 -+#define V4L2_HEVC_SLICE_TYPE_P 1 -+#define V4L2_HEVC_SLICE_TYPE_I 2 -+ -+#define V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE (1ULL << 0) -+#define V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED (1ULL << 1) -+#define V4L2_HEVC_SPS_FLAG_AMP_ENABLED (1ULL << 2) -+#define V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET (1ULL << 3) -+#define V4L2_HEVC_SPS_FLAG_PCM_ENABLED (1ULL << 4) -+#define V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED (1ULL << 5) -+#define V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT (1ULL << 6) -+#define V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED (1ULL << 7) -+#define V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED (1ULL << 8) -+ -+/* The controls are not stable at the moment and will likely be reworked. */ -+struct v4l2_ctrl_hevc_sps { -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ -+ __u16 pic_width_in_luma_samples; -+ __u16 pic_height_in_luma_samples; -+ __u8 bit_depth_luma_minus8; -+ __u8 bit_depth_chroma_minus8; -+ __u8 log2_max_pic_order_cnt_lsb_minus4; -+ __u8 sps_max_dec_pic_buffering_minus1; -+ __u8 sps_max_num_reorder_pics; -+ __u8 sps_max_latency_increase_plus1; -+ __u8 log2_min_luma_coding_block_size_minus3; -+ __u8 log2_diff_max_min_luma_coding_block_size; -+ __u8 log2_min_luma_transform_block_size_minus2; -+ __u8 log2_diff_max_min_luma_transform_block_size; -+ __u8 max_transform_hierarchy_depth_inter; -+ __u8 max_transform_hierarchy_depth_intra; -+ __u8 pcm_sample_bit_depth_luma_minus1; -+ __u8 pcm_sample_bit_depth_chroma_minus1; -+ __u8 log2_min_pcm_luma_coding_block_size_minus3; -+ __u8 log2_diff_max_min_pcm_luma_coding_block_size; -+ __u8 num_short_term_ref_pic_sets; -+ __u8 num_long_term_ref_pics_sps; -+ __u8 chroma_format_idc; -+ __u8 sps_max_sub_layers_minus1; -+ -+ __u64 flags; -+}; -+ -+#define V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED (1ULL << 0) -+#define V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT (1ULL << 1) -+#define V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED (1ULL << 2) -+#define V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT (1ULL << 3) -+#define V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED (1ULL << 4) -+#define V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED (1ULL << 5) -+#define V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED (1ULL << 6) -+#define V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT (1ULL << 7) -+#define V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED (1ULL << 8) -+#define V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED (1ULL << 9) -+#define V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED (1ULL << 10) -+#define V4L2_HEVC_PPS_FLAG_TILES_ENABLED (1ULL << 11) -+#define V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED (1ULL << 12) -+#define V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED (1ULL << 13) -+#define V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 14) -+#define V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED (1ULL << 15) -+#define V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER (1ULL << 16) -+#define V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT (1ULL << 17) -+#define V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT (1ULL << 18) -+#define V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT (1ULL << 19) -+#define V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING (1ULL << 20) -+ -+struct v4l2_ctrl_hevc_pps { -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ -+ __u8 num_extra_slice_header_bits; -+ __u8 num_ref_idx_l0_default_active_minus1; -+ __u8 num_ref_idx_l1_default_active_minus1; -+ __s8 init_qp_minus26; -+ __u8 diff_cu_qp_delta_depth; -+ __s8 pps_cb_qp_offset; -+ __s8 pps_cr_qp_offset; -+ __u8 num_tile_columns_minus1; -+ __u8 num_tile_rows_minus1; -+ __u8 column_width_minus1[20]; -+ __u8 row_height_minus1[22]; -+ __s8 pps_beta_offset_div2; -+ __s8 pps_tc_offset_div2; -+ __u8 log2_parallel_merge_level_minus2; -+ -+ __u8 padding[4]; -+ __u64 flags; -+}; -+ -+#define V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE 0x01 -+ -+#define V4L2_HEVC_DPB_ENTRIES_NUM_MAX 16 -+ -+struct v4l2_hevc_dpb_entry { -+ __u64 timestamp; -+ __u8 flags; -+ __u8 field_pic; -+ __s32 pic_order_cnt_val; -+ __u8 padding[2]; -+}; -+ -+struct v4l2_hevc_pred_weight_table { -+ __s8 delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ __s8 luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ __s8 delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]; -+ __s8 chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]; -+ -+ __s8 delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ __s8 luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ __s8 delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]; -+ __s8 chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]; -+ -+ __u8 padding[6]; -+ -+ __u8 luma_log2_weight_denom; -+ __s8 delta_chroma_log2_weight_denom; -+}; -+ -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA (1ULL << 0) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA (1ULL << 1) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED (1ULL << 2) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO (1ULL << 3) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT (1ULL << 4) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0 (1ULL << 5) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_USE_INTEGER_MV (1ULL << 6) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED (1ULL << 7) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED (1ULL << 8) -+#define V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT (1ULL << 9) -+ -+struct v4l2_ctrl_hevc_slice_params { -+ __u32 bit_size; -+ __u32 data_bit_offset; -+ -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */ -+ __u8 nal_unit_type; -+ __u8 nuh_temporal_id_plus1; -+ -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ -+ __u8 slice_type; -+ __u8 colour_plane_id; -+ __s32 slice_pic_order_cnt; -+ __u8 num_ref_idx_l0_active_minus1; -+ __u8 num_ref_idx_l1_active_minus1; -+ __u8 collocated_ref_idx; -+ __u8 five_minus_max_num_merge_cand; -+ __s8 slice_qp_delta; -+ __s8 slice_cb_qp_offset; -+ __s8 slice_cr_qp_offset; -+ __s8 slice_act_y_qp_offset; -+ __s8 slice_act_cb_qp_offset; -+ __s8 slice_act_cr_qp_offset; -+ __s8 slice_beta_offset_div2; -+ __s8 slice_tc_offset_div2; -+ -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture timing SEI message */ -+ __u8 pic_struct; -+ -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ -+ __u32 slice_segment_addr; -+ __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ -+ __u8 padding; -+ -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ -+ struct v4l2_hevc_pred_weight_table pred_weight_table; -+ -+ __u64 flags; -+}; -+ -+#define V4L2_HEVC_DECODE_PARAM_FLAG_IRAP_PIC 0x1 -+#define V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC 0x2 -+#define V4L2_HEVC_DECODE_PARAM_FLAG_NO_OUTPUT_OF_PRIOR 0x4 -+ -+struct v4l2_ctrl_hevc_decode_params { -+ __s32 pic_order_cnt_val; -+ __u8 num_active_dpb_entries; -+ struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ __u8 num_poc_st_curr_before; -+ __u8 num_poc_st_curr_after; -+ __u8 num_poc_lt_curr; -+ __u8 poc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ __u8 poc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ __u8 poc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -+ __u64 flags; -+}; -+ -+struct v4l2_ctrl_hevc_scaling_matrix { -+ __u8 scaling_list_4x4[6][16]; -+ __u8 scaling_list_8x8[6][64]; -+ __u8 scaling_list_16x16[6][64]; -+ __u8 scaling_list_32x32[2][64]; -+ __u8 scaling_list_dc_coef_16x16[6]; -+ __u8 scaling_list_dc_coef_32x32[2]; -+}; -+ -+/* MPEG-class control IDs specific to the Hantro driver as defined by V4L2 */ -+#define V4L2_CID_CODEC_HANTRO_BASE (V4L2_CTRL_CLASS_CODEC | 0x1200) -+/* -+ * V4L2_CID_HANTRO_HEVC_SLICE_HEADER_SKIP - -+ * the number of data (in bits) to skip in the -+ * slice segment header. -+ * If non-IDR, the bits to be skipped go from syntax element "pic_output_flag" -+ * to before syntax element "slice_temporal_mvp_enabled_flag". -+ * If IDR, the skipped bits are just "pic_output_flag" -+ * (separate_colour_plane_flag is not supported). -+ */ -+#define V4L2_CID_HANTRO_HEVC_SLICE_HEADER_SKIP (V4L2_CID_CODEC_HANTRO_BASE + 0) -+ -+#endif -diff --git a/libavcodec/v4l2_request_hevc.c b/libavcodec/v4l2_request_hevc.c -index eaedde0d86..3a4b2493b2 100644 ---- a/libavcodec/v4l2_request_hevc.c -+++ b/libavcodec/v4l2_request_hevc.c -@@ -19,6 +19,7 @@ - #include "hevcdec.h" - #include "hwconfig.h" - #include "v4l2_request.h" -+#include "hevc-ctrls.h" - - #define MAX_SLICES 16 - - -From 4abf972abac8a7cf1f81a544fc8b7ad82aff89e9 Mon Sep 17 00:00:00 2001 +From 0a7d6808383a5c88a690b7ba6c634970dcd33548 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 29 Apr 2019 22:08:59 +0000 -Subject: [PATCH 11/17] HACK: hwcontext_drm: do not require drm device +Subject: [PATCH 10/12] HACK: hwcontext_drm: do not require drm device Signed-off-by: Jonas Karlman --- @@ -4181,57 +4046,10 @@ index 7a9fdbd263..6297d1f9b6 100644 if (hwctx->fd < 0) return AVERROR(errno); -From 2bf038b3f3b77eeaef2b0c08e265e080c267c0a8 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 15 Dec 2018 22:32:16 +0100 -Subject: [PATCH 12/17] WIP: hevc entry point offsets - -Signed-off-by: Jernej Skrabec ---- - libavcodec/hevc-ctrls.h | 4 +++- - libavcodec/v4l2_request_hevc.c | 9 +++++++++ - 2 files changed, 12 insertions(+), 1 deletion(-) - -diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h -index 88e804578c..edf3c10080 100644 ---- a/libavcodec/hevc-ctrls.h -+++ b/libavcodec/hevc-ctrls.h -@@ -200,7 +200,9 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - -- __u8 padding; -+ __u32 num_entry_point_offsets; -+ __u32 entry_point_offset_minus1[256]; -+ __u8 padding[8]; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ - struct v4l2_hevc_pred_weight_table pred_weight_table; -diff --git a/libavcodec/v4l2_request_hevc.c b/libavcodec/v4l2_request_hevc.c -index 3a4b2493b2..59f3192c92 100644 ---- a/libavcodec/v4l2_request_hevc.c -+++ b/libavcodec/v4l2_request_hevc.c -@@ -230,6 +230,15 @@ static void v4l2_request_hevc_fill_slice_params(const HEVCContext *h, - } - - v4l2_request_hevc_fill_pred_table(h, &slice_params->pred_weight_table); -+ -+ slice_params->num_entry_point_offsets = sh->num_entry_point_offsets; -+ if (slice_params->num_entry_point_offsets > 256) { -+ slice_params->num_entry_point_offsets = 256; -+ av_log(NULL, AV_LOG_ERROR, "%s: Currently only 256 entry points are supported, but slice has %d entry points.\n", __func__, sh->num_entry_point_offsets); -+ } -+ -+ for (i = 0; i < slice_params->num_entry_point_offsets; i++) -+ slice_params->entry_point_offset_minus1[i] = sh->entry_point_offset[i] - 1; - } - - static void fill_sps(struct v4l2_ctrl_hevc_sps *ctrl, const HEVCContext *h) - -From 36f2b7c0c5245471a16563e078307088fe38c00c Mon Sep 17 00:00:00 2001 +From d82c704c262fea62250c5989d8e97cdd769d8359 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Fri, 15 May 2020 16:54:05 +0000 -Subject: [PATCH 13/17] WIP: add NV15 and NV20 support +Subject: [PATCH 11/12] WIP: add NV15 and NV20 support Signed-off-by: Jonas Karlman --- @@ -4274,7 +4092,7 @@ index 6b7f569da4..ee4c76cf41 100644 *fmt++ = AV_PIX_FMT_YUVJ422P; else diff --git a/libavcodec/v4l2_request.c b/libavcodec/v4l2_request.c -index 5234b5049b..0b294feff2 100644 +index b57bbf29bc..349ed67cb2 100644 --- a/libavcodec/v4l2_request.c +++ b/libavcodec/v4l2_request.c @@ -188,6 +188,13 @@ const uint32_t v4l2_request_capture_pixelformats[] = { @@ -4315,17 +4133,17 @@ index 5234b5049b..0b294feff2 100644 default: return -1; -From 2416dbe0c4b9d93546f88244d9fa543250daca24 Mon Sep 17 00:00:00 2001 +From 0b8eff40d910669ea03417f76468fcf2518d293e Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Mon, 27 Jul 2020 23:15:45 +0000 -Subject: [PATCH 14/17] HACK: define drm NV15 and NV20 format +Subject: [PATCH 12/12] HACK: define drm NV15 and NV20 format --- libavcodec/v4l2_request.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/libavcodec/v4l2_request.c b/libavcodec/v4l2_request.c -index 0b294feff2..a8f0ee79ee 100644 +index 349ed67cb2..824dcaa8e9 100644 --- a/libavcodec/v4l2_request.c +++ b/libavcodec/v4l2_request.c @@ -30,6 +30,14 @@ @@ -4343,369 +4161,3 @@ index 0b294feff2..a8f0ee79ee 100644 uint64_t ff_v4l2_request_get_capture_timestamp(AVFrame *frame) { V4L2RequestDescriptor *req = (V4L2RequestDescriptor*)frame->data[0]; - -From a288c02f498b1c223a81d3f9f174e3f879d75047 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Wed, 13 May 2020 22:51:21 +0000 -Subject: [PATCH 15/17] WIP: hevc rkvdec fields - -Signed-off-by: Jonas Karlman ---- - libavcodec/hevc-ctrls.h | 11 ++++++++++- - libavcodec/v4l2_request_hevc.c | 12 ++++++++++++ - 2 files changed, 22 insertions(+), 1 deletion(-) - -diff --git a/libavcodec/hevc-ctrls.h b/libavcodec/hevc-ctrls.h -index edf3c10080..9610266f3f 100644 ---- a/libavcodec/hevc-ctrls.h -+++ b/libavcodec/hevc-ctrls.h -@@ -58,6 +58,8 @@ enum v4l2_mpeg_video_hevc_start_code { - /* The controls are not stable at the moment and will likely be reworked. */ - struct v4l2_ctrl_hevc_sps { - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ -+ __u8 video_parameter_set_id; -+ __u8 seq_parameter_set_id; - __u16 pic_width_in_luma_samples; - __u16 pic_height_in_luma_samples; - __u8 bit_depth_luma_minus8; -@@ -81,6 +83,9 @@ struct v4l2_ctrl_hevc_sps { - __u8 chroma_format_idc; - __u8 sps_max_sub_layers_minus1; - -+ __u8 num_slices; -+ __u8 padding[5]; -+ - __u64 flags; - }; - -@@ -108,6 +113,7 @@ struct v4l2_ctrl_hevc_sps { - - struct v4l2_ctrl_hevc_pps { - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ -+ __u8 pic_parameter_set_id; - __u8 num_extra_slice_header_bits; - __u8 num_ref_idx_l0_default_active_minus1; - __u8 num_ref_idx_l1_default_active_minus1; -@@ -123,7 +129,7 @@ struct v4l2_ctrl_hevc_pps { - __s8 pps_tc_offset_div2; - __u8 log2_parallel_merge_level_minus2; - -- __u8 padding[4]; -+ __u8 padding; - __u64 flags; - }; - -@@ -200,6 +206,9 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; - -+ __u16 short_term_ref_pic_set_size; -+ __u16 long_term_ref_pic_set_size; -+ - __u32 num_entry_point_offsets; - __u32 entry_point_offset_minus1[256]; - __u8 padding[8]; -diff --git a/libavcodec/v4l2_request_hevc.c b/libavcodec/v4l2_request_hevc.c -index 59f3192c92..bf20b9a849 100644 ---- a/libavcodec/v4l2_request_hevc.c -+++ b/libavcodec/v4l2_request_hevc.c -@@ -188,6 +188,9 @@ static void v4l2_request_hevc_fill_slice_params(const HEVCContext *h, - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture timing SEI message */ - .pic_struct = h->sei.picture_timing.picture_struct, -+ -+ .short_term_ref_pic_set_size = sh->short_term_ref_pic_set_size, -+ .long_term_ref_pic_set_size = sh->long_term_ref_pic_set_size, - }; - - if (sh->slice_sample_adaptive_offset_flag[0]) -@@ -244,9 +247,12 @@ static void v4l2_request_hevc_fill_slice_params(const HEVCContext *h, - static void fill_sps(struct v4l2_ctrl_hevc_sps *ctrl, const HEVCContext *h) - { - const HEVCSPS *sps = h->ps.sps; -+ const HEVCPPS *pps = h->ps.pps; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ - *ctrl = (struct v4l2_ctrl_hevc_sps) { -+ .video_parameter_set_id = sps->vps_id, -+ .seq_parameter_set_id = pps->sps_id, - .pic_width_in_luma_samples = sps->width, - .pic_height_in_luma_samples = sps->height, - .bit_depth_luma_minus8 = sps->bit_depth - 8, -@@ -310,6 +316,7 @@ static int v4l2_request_hevc_start_frame(AVCodecContext *avctx, - &pps->scaling_list : - sps->scaling_list_enable_flag ? - &sps->scaling_list : NULL; -+ const SliceHeader *sh = &h->sh; - V4L2RequestControlsHEVC *controls = h->ref->hwaccel_picture_private; - - fill_sps(&controls->sps, h); -@@ -333,6 +340,9 @@ static int v4l2_request_hevc_start_frame(AVCodecContext *avctx, - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ - controls->pps = (struct v4l2_ctrl_hevc_pps) { -+ .pic_parameter_set_id = sh->pps_id, -+ .num_ref_idx_l0_default_active_minus1 = pps->num_ref_idx_l0_default_active - 1, -+ .num_ref_idx_l1_default_active_minus1 = pps->num_ref_idx_l1_default_active - 1, - .num_extra_slice_header_bits = pps->num_extra_slice_header_bits, - .num_ref_idx_l0_default_active_minus1 = pps->num_ref_idx_l0_default_active - 1, - .num_ref_idx_l1_default_active_minus1 = pps->num_ref_idx_l1_default_active - 1, -@@ -462,6 +472,8 @@ static int v4l2_request_hevc_queue_decode(AVCodecContext *avctx, int last_slice) - if (ctx->decode_mode == V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED) - return ff_v4l2_request_decode_slice(avctx, h->ref->frame, control, FF_ARRAY_ELEMS(control), controls->first_slice, last_slice); - -+ controls->sps.num_slices = controls->num_slices; -+ - return ff_v4l2_request_decode_frame(avctx, h->ref->frame, control, FF_ARRAY_ELEMS(control)); - } - - -From 69ca076a72c32c687bddb611d3a70e4f1c13184a Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 19 Sep 2021 13:10:55 +0200 -Subject: [PATCH 16/17] v4l2_request: validate supported framesizes - -Signed-off-by: Alex Bee ---- - libavcodec/v4l2_request.c | 43 +++++++++++++++++++++++++++++++++++++++ - 1 file changed, 43 insertions(+) - -diff --git a/libavcodec/v4l2_request.c b/libavcodec/v4l2_request.c -index a8f0ee79ee..824dcaa8e9 100644 ---- a/libavcodec/v4l2_request.c -+++ b/libavcodec/v4l2_request.c -@@ -376,6 +376,42 @@ int ff_v4l2_request_decode_frame(AVCodecContext *avctx, AVFrame *frame, struct v - return v4l2_request_queue_decode(avctx, frame, control, count, 1, 1); - } - -+static int v4l2_request_try_framesize(AVCodecContext *avctx, uint32_t pixelformat) -+{ -+ V4L2RequestContext *ctx = avctx->internal->hwaccel_priv_data; -+ struct v4l2_frmsizeenum frmsize = { -+ .index = 0, -+ .pixel_format = pixelformat, -+ }; -+ -+ if (ioctl(ctx->video_fd, VIDIOC_ENUM_FRAMESIZES, &frmsize) < 0) -+ return 0; -+ -+ /* -+ * We only validate min/max framesize for V4L2_FRMSIZE_TYPE_STEPWISE here, since the alignment -+ * which is eventually needed will be done driver-side later in VIDIOC_S_FMT and there is no need -+ * validate step_width/step_height here -+ */ -+ -+ do { -+ -+ if (frmsize.type == V4L2_FRMSIZE_TYPE_DISCRETE && frmsize.discrete.width == avctx->coded_width && -+ frmsize.discrete.height == avctx->coded_height) -+ return 0; -+ else if ((frmsize.type == V4L2_FRMSIZE_TYPE_STEPWISE || frmsize.type == V4L2_FRMSIZE_TYPE_CONTINUOUS) && -+ avctx->coded_width >= frmsize.stepwise.min_width && avctx->coded_height >= frmsize.stepwise.min_height && -+ avctx->coded_width <= frmsize.stepwise.max_width && avctx->coded_height <= frmsize.stepwise.max_height) -+ return 0; -+ -+ frmsize.index++; -+ -+ } while (ioctl(ctx->video_fd, VIDIOC_ENUM_FRAMESIZES, &frmsize) >= 0); -+ -+ av_log(avctx, AV_LOG_INFO, "%s: pixelformat %u not supported for width %u height %u\n", __func__, pixelformat, avctx->coded_width, avctx->coded_height); -+ -+ return -1; -+} -+ - static int v4l2_request_try_format(AVCodecContext *avctx, enum v4l2_buf_type type, uint32_t pixelformat) - { - V4L2RequestContext *ctx = avctx->internal->hwaccel_priv_data; -@@ -543,6 +579,13 @@ static int v4l2_request_probe_video_device(struct udev_device *device, AVCodecCo - goto fail; - } - -+ ret = v4l2_request_try_framesize(avctx, pixelformat); -+ if (ret < 0) { -+ av_log(avctx, AV_LOG_WARNING, "%s: try framesize failed\n", __func__); -+ ret = AVERROR(EINVAL); -+ goto fail; -+ } -+ - ret = v4l2_request_set_format(avctx, ctx->output_type, pixelformat, buffersize); - if (ret < 0) { - av_log(avctx, AV_LOG_ERROR, "%s: set output format failed, %s (%d)\n", __func__, strerror(errno), errno); - -From 237847d27938132c5bb9d137a2829bc34aab50d6 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 27 Feb 2022 18:54:21 +0100 -Subject: [PATCH 17/17] Improve VP9 decoding - ---- - libavcodec/v4l2_request_vp9.c | 110 +++++++++++++++++++--------------- - 1 file changed, 62 insertions(+), 48 deletions(-) - -diff --git a/libavcodec/v4l2_request_vp9.c b/libavcodec/v4l2_request_vp9.c -index 9b95c76cdb..ec0300f66d 100644 ---- a/libavcodec/v4l2_request_vp9.c -+++ b/libavcodec/v4l2_request_vp9.c -@@ -22,78 +22,62 @@ - - typedef struct V4L2RequestControlsVP9 { - struct v4l2_ctrl_vp9_frame decode_params; -+ struct v4l2_ctrl_vp9_compressed_hdr chp; - } V4L2RequestControlsVP9; - --static int v4l2_request_vp9_set_frame_ctx(AVCodecContext *avctx) -+static void v4l2_request_vp9_set_frame_ctx(AVCodecContext *avctx) - { - VP9Context *s = avctx->priv_data; -- struct v4l2_ctrl_vp9_compressed_hdr chp; -- struct v4l2_ext_control control[] = { -- { -- .id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR, -- .ptr = &chp, -- .size = sizeof(chp), -- }, -- }; -+ const VP9Frame *f = &s->s.frames[CUR_FRAME]; -+ V4L2RequestControlsVP9 *controls = f->hwaccel_picture_private; -+ struct v4l2_ctrl_vp9_compressed_hdr *chp = &controls->chp; - -- memset(&chp, 0, sizeof(chp)); -+ memset(chp, 0, sizeof(&chp)); - -- chp.tx_mode = s->s.h.txfmmode; -- memcpy(chp.tx8, s->prob_raw.p.tx8p, sizeof(s->prob_raw.p.tx8p)); -- memcpy(chp.tx16, s->prob_raw.p.tx16p, sizeof(s->prob_raw.p.tx16p)); -- memcpy(chp.tx32, s->prob_raw.p.tx32p, sizeof(s->prob_raw.p.tx32p)); -+ chp->tx_mode = s->s.h.txfmmode; -+ memcpy(chp->tx8, s->prob_raw.p.tx8p, sizeof(s->prob_raw.p.tx8p)); -+ memcpy(chp->tx16, s->prob_raw.p.tx16p, sizeof(s->prob_raw.p.tx16p)); -+ memcpy(chp->tx32, s->prob_raw.p.tx32p, sizeof(s->prob_raw.p.tx32p)); - for (unsigned i = 0; i < 4; i++) { - for (unsigned j = 0; j < 2; j++) { - for (unsigned k = 0; k < 2; k++) { - for (unsigned l = 0; l < 6; l++) { - for (unsigned m = 0; m < 6; m++) { -- memcpy(chp.coef[i][j][k][l][m], s->prob_raw.coef[i][j][k][l][m], sizeof(chp.coef[0][0][0][0][0])); -+ memcpy(chp->coef[i][j][k][l][m], s->prob_raw.coef[i][j][k][l][m], sizeof(chp->coef[0][0][0][0][0])); - } - } - } - } - } -- memcpy(chp.skip, s->prob_raw.p.skip, sizeof(s->prob_raw.p.skip)); -- memcpy(chp.inter_mode, s->prob_raw.p.mv_mode, sizeof(s->prob_raw.p.mv_mode)); -- memcpy(chp.interp_filter, s->prob_raw.p.filter, sizeof(s->prob_raw.p.filter)); -- memcpy(chp.is_inter, s->prob_raw.p.intra, sizeof(s->prob_raw.p.intra)); -- memcpy(chp.comp_mode, s->prob_raw.p.comp, sizeof(s->prob_raw.p.comp)); -- memcpy(chp.single_ref, s->prob_raw.p.single_ref, sizeof(s->prob_raw.p.single_ref)); -- memcpy(chp.comp_ref, s->prob_raw.p.comp_ref, sizeof(s->prob_raw.p.comp_ref)); -- memcpy(chp.y_mode, s->prob_raw.p.y_mode, sizeof(s->prob_raw.p.y_mode)); -+ memcpy(chp->skip, s->prob_raw.p.skip, sizeof(s->prob_raw.p.skip)); -+ memcpy(chp->inter_mode, s->prob_raw.p.mv_mode, sizeof(s->prob_raw.p.mv_mode)); -+ memcpy(chp->interp_filter, s->prob_raw.p.filter, sizeof(s->prob_raw.p.filter)); -+ memcpy(chp->is_inter, s->prob_raw.p.intra, sizeof(s->prob_raw.p.intra)); -+ memcpy(chp->comp_mode, s->prob_raw.p.comp, sizeof(s->prob_raw.p.comp)); -+ memcpy(chp->single_ref, s->prob_raw.p.single_ref, sizeof(s->prob_raw.p.single_ref)); -+ memcpy(chp->comp_ref, s->prob_raw.p.comp_ref, sizeof(s->prob_raw.p.comp_ref)); -+ memcpy(chp->y_mode, s->prob_raw.p.y_mode, sizeof(s->prob_raw.p.y_mode)); - for (unsigned i = 0; i < 10; i++) -- memcpy(chp.uv_mode[i], s->prob.p.uv_mode[i], sizeof(s->prob.p.uv_mode[0])); -+ memcpy(chp->uv_mode[i], s->prob.p.uv_mode[i], sizeof(s->prob.p.uv_mode[0])); - for (unsigned i = 0; i < 4; i++) -- memcpy(chp.partition[i * 4], s->prob_raw.p.partition[i], sizeof(s->prob_raw.p.partition[0])); -- memcpy(chp.mv.joint, s->prob_raw.p.mv_joint, sizeof(s->prob_raw.p.mv_joint)); -+ memcpy(chp->partition[i * 4], s->prob_raw.p.partition[i], sizeof(s->prob_raw.p.partition[0])); -+ memcpy(chp->mv.joint, s->prob_raw.p.mv_joint, sizeof(s->prob_raw.p.mv_joint)); - for (unsigned i = 0; i < 2; i++) { -- chp.mv.sign[i] = s->prob_raw.p.mv_comp[i].sign; -- memcpy(chp.mv.classes[i], s->prob_raw.p.mv_comp[i].classes, sizeof(s->prob_raw.p.mv_comp[0].classes)); -- chp.mv.class0_bit[i] = s->prob_raw.p.mv_comp[i].class0; -- memcpy(chp.mv.bits[i], s->prob_raw.p.mv_comp[i].bits, sizeof(s->prob_raw.p.mv_comp[0].bits)); -- memcpy(chp.mv.class0_fr[i], s->prob_raw.p.mv_comp[i].class0_fp, sizeof(s->prob_raw.p.mv_comp[0].class0_fp)); -- memcpy(chp.mv.fr[i], s->prob_raw.p.mv_comp[i].fp, sizeof(s->prob_raw.p.mv_comp[0].fp)); -- chp.mv.class0_hp[i] = s->prob_raw.p.mv_comp[i].class0_hp; -- chp.mv.hp[i] = s->prob_raw.p.mv_comp[i].hp; -+ chp->mv.sign[i] = s->prob_raw.p.mv_comp[i].sign; -+ memcpy(chp->mv.classes[i], s->prob_raw.p.mv_comp[i].classes, sizeof(s->prob_raw.p.mv_comp[0].classes)); -+ chp->mv.class0_bit[i] = s->prob_raw.p.mv_comp[i].class0; -+ memcpy(chp->mv.bits[i], s->prob_raw.p.mv_comp[i].bits, sizeof(s->prob_raw.p.mv_comp[0].bits)); -+ memcpy(chp->mv.class0_fr[i], s->prob_raw.p.mv_comp[i].class0_fp, sizeof(s->prob_raw.p.mv_comp[0].class0_fp)); -+ memcpy(chp->mv.fr[i], s->prob_raw.p.mv_comp[i].fp, sizeof(s->prob_raw.p.mv_comp[0].fp)); -+ chp->mv.class0_hp[i] = s->prob_raw.p.mv_comp[i].class0_hp; -+ chp->mv.hp[i] = s->prob_raw.p.mv_comp[i].hp; - } -- -- return ff_v4l2_request_set_controls(avctx, control, FF_ARRAY_ELEMS(control)); - } - --static int v4l2_request_vp9_start_frame(AVCodecContext *avctx, -- av_unused const uint8_t *buffer, -- av_unused uint32_t size) -+static void fill_frame(struct v4l2_ctrl_vp9_frame *dec_params, AVCodecContext *avctx) - { - const VP9Context *s = avctx->priv_data; -- const VP9Frame *f = &s->s.frames[CUR_FRAME]; -- V4L2RequestControlsVP9 *controls = f->hwaccel_picture_private; -- struct v4l2_ctrl_vp9_frame *dec_params = &controls->decode_params; - const ThreadFrame *ref; -- int ret; -- -- ret = v4l2_request_vp9_set_frame_ctx(avctx); -- if (ret) -- return ret; - - memset(dec_params, 0, sizeof(*dec_params)); - -@@ -208,6 +192,19 @@ static int v4l2_request_vp9_start_frame(AVCodecContext *avctx, - if (s->s.h.segmentation.feat[i].skip_enabled) - dec_params->seg.feature_enabled[i] |= 1 << V4L2_VP9_SEG_LVL_SKIP; - } -+} -+ -+static int v4l2_request_vp9_start_frame(AVCodecContext *avctx, -+ av_unused const uint8_t *buffer, -+ av_unused uint32_t size) -+{ -+ const VP9Context *s = avctx->priv_data; -+ const VP9Frame *f = &s->s.frames[CUR_FRAME]; -+ V4L2RequestControlsVP9 *controls = f->hwaccel_picture_private; -+ -+ v4l2_request_vp9_set_frame_ctx(avctx); -+ -+ fill_frame(&controls->decode_params, avctx); - - return ff_v4l2_request_reset_frame(avctx, f->tf.f); - } -@@ -233,6 +230,11 @@ static int v4l2_request_vp9_end_frame(AVCodecContext *avctx) - .ptr = &controls->decode_params, - .size = sizeof(controls->decode_params), - }, -+ { -+ .id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR, -+ .ptr = &controls->chp, -+ .size = sizeof(controls->chp), -+ }, - }; - - ret = ff_v4l2_request_decode_frame(avctx, f->tf.f, control, FF_ARRAY_ELEMS(control)); -@@ -247,8 +249,20 @@ static int v4l2_request_vp9_end_frame(AVCodecContext *avctx) - - static int v4l2_request_vp9_init(AVCodecContext *avctx) - { -+ struct v4l2_ctrl_vp9_frame frame; -+ -+ struct v4l2_ext_control control[] = { -+ { -+ .id = V4L2_CID_STATELESS_VP9_FRAME, -+ .ptr = &frame, -+ .size = sizeof(frame), -+ }, -+ }; -+ -+ fill_frame(&frame, avctx); -+ - // TODO: check V4L2_CID_MPEG_VIDEO_VP9_PROFILE -- return ff_v4l2_request_init(avctx, V4L2_PIX_FMT_VP9_FRAME, 3 * 1024 * 1024, NULL, 0); -+ return ff_v4l2_request_init(avctx, V4L2_PIX_FMT_VP9_FRAME, 3 * 1024 * 1024, control, FF_ARRAY_ELEMS(control)); - } - - const AVHWAccel ff_vp9_v4l2request_hwaccel = { diff --git a/projects/Rockchip/patches/ffmpeg/ffmpeg-0004-v4l2request-hevc-increase-max-slices.patch b/projects/Rockchip/patches/ffmpeg/ffmpeg-0004-v4l2request-hevc-increase-max-slices.patch deleted file mode 100644 index 4b665817f0..0000000000 --- a/projects/Rockchip/patches/ffmpeg/ffmpeg-0004-v4l2request-hevc-increase-max-slices.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 20 Jun 2021 20:19:19 +0200 -Subject: [PATCH] v4l2request: hevc: increase max slices - -It's required by some HEVC confromance tests - -Signed-off-by: Alex Bee ---- - libavcodec/v4l2_request_hevc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/libavcodec/v4l2_request_hevc.c b/libavcodec/v4l2_request_hevc.c -index be78382444..35ec87e310 100644 ---- a/libavcodec/v4l2_request_hevc.c -+++ b/libavcodec/v4l2_request_hevc.c -@@ -21,7 +21,7 @@ - #include "v4l2_request.h" - #include "hevc-ctrls.h" - --#define MAX_SLICES 16 -+#define MAX_SLICES 32 - - typedef struct V4L2RequestControlsHEVC { - struct v4l2_ctrl_hevc_sps sps; From a1f6078f0e054f605091977f0ad266464ccc1a72 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Tue, 30 Aug 2022 09:00:28 +0000 Subject: [PATCH 27/29] linux: update to 6.0 Co-authored-by: CvH <1355173+CvH@users.noreply.github.com> --- packages/linux/package.mk | 6 +- ...nux-100-kernel-5-19-io-series-664369.patch | 1350 ----------------- 2 files changed, 3 insertions(+), 1353 deletions(-) delete mode 100644 packages/linux/patches/default/linux-100-kernel-5-19-io-series-664369.patch diff --git a/packages/linux/package.mk b/packages/linux/package.mk index 7f6bb124db..cc389dbb9d 100644 --- a/packages/linux/package.mk +++ b/packages/linux/package.mk @@ -28,9 +28,9 @@ case "${LINUX}" in PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz" ;; *) - PKG_VERSION="5.19.7" - PKG_SHA256="b8bb6019d4255f39196726f9d0f82f76179d1c3d7c6b603431ef04b38201199f" - PKG_URL="https://www.kernel.org/pub/linux/kernel/v5.x/${PKG_NAME}-${PKG_VERSION}.tar.xz" + PKG_VERSION="6.0" + PKG_SHA256="5c2443a5538de52688efb55c27ab0539c1f5eb58c0cfd16a2b9fbb08fd81788e" + PKG_URL="https://www.kernel.org/pub/linux/kernel/v${PKG_VERSION/.*/}.x/${PKG_NAME}-${PKG_VERSION}.tar.xz" PKG_PATCH_DIRS="default" ;; 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Sun, - 31 Jul 2022 21:38:36 -0400 (EDT) -From: Andres Freund -To: bpf@vger.kernel.org, linux-kernel@vger.kernel.org -Cc: Alexei Starovoitov , - Arnaldo Carvalho de Melo , - Jiri Olsa , - Sedat Dilek , - Quentin Monnet , - Ben Hutchings -Subject: [PATCH v3 1/8] tools build: Add feature test for - init_disassemble_info API changes -Date: Sun, 31 Jul 2022 18:38:27 -0700 -Message-Id: <20220801013834.156015-2-andres@anarazel.de> -X-Mailer: git-send-email 2.37.0.3.g30cc8d0f14 -In-Reply-To: <20220801013834.156015-1-andres@anarazel.de> -References: <20220622231624.t63bkmkzphqvh3kx@alap3.anarazel.de> - <20220801013834.156015-1-andres@anarazel.de> -MIME-Version: 1.0 -Precedence: bulk -List-ID: -X-Mailing-List: bpf@vger.kernel.org - -binutils changed the signature of init_disassemble_info(), which now causes -compilation failures for tools/{perf,bpf}, e.g. on debian unstable. -Relevant binutils commit: -https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=60a3da00bd5407f07 - -This commit adds a feature test to detect the new signature. Subsequent -commits will use it to fix the build failures. - -Cc: Alexei Starovoitov -Cc: Arnaldo Carvalho de Melo -Cc: Sedat Dilek -Cc: Quentin Monnet -Link: http://lore.kernel.org/lkml/20220622181918.ykrs5rsnmx3og4sv@alap3.anarazel.de -Signed-off-by: Andres Freund ---- - tools/build/Makefile.feature | 1 + - tools/build/feature/Makefile | 4 ++++ - tools/build/feature/test-all.c | 4 ++++ - tools/build/feature/test-disassembler-init-styled.c | 13 +++++++++++++ - 4 files changed, 22 insertions(+) - create mode 100644 tools/build/feature/test-disassembler-init-styled.c - -diff --git a/tools/build/Makefile.feature b/tools/build/Makefile.feature -index 888a0421d43b..8f6578e4d324 100644 ---- a/tools/build/Makefile.feature -+++ b/tools/build/Makefile.feature -@@ -70,6 +70,7 @@ FEATURE_TESTS_BASIC := \ - libaio \ - libzstd \ - disassembler-four-args \ -+ disassembler-init-styled \ - file-handle - - # FEATURE_TESTS_BASIC + FEATURE_TESTS_EXTRA is the complete list -diff --git a/tools/build/feature/Makefile b/tools/build/feature/Makefile -index 7c2a17e23c30..c3059739318a 100644 ---- a/tools/build/feature/Makefile -+++ b/tools/build/feature/Makefile -@@ -18,6 +18,7 @@ FILES= \ - test-libbfd.bin \ - test-libbfd-buildid.bin \ - test-disassembler-four-args.bin \ -+ test-disassembler-init-styled.bin \ - test-reallocarray.bin \ - test-libbfd-liberty.bin \ - test-libbfd-liberty-z.bin \ -@@ -248,6 +249,9 @@ $(OUTPUT)test-libbfd-buildid.bin: - $(OUTPUT)test-disassembler-four-args.bin: - $(BUILD) -DPACKAGE='"perf"' -lbfd -lopcodes - -+$(OUTPUT)test-disassembler-init-styled.bin: -+ $(BUILD) -DPACKAGE='"perf"' -lbfd -lopcodes -+ - $(OUTPUT)test-reallocarray.bin: - $(BUILD) - -diff --git a/tools/build/feature/test-all.c b/tools/build/feature/test-all.c -index 5ffafb967b6e..957c02c7b163 100644 ---- a/tools/build/feature/test-all.c -+++ b/tools/build/feature/test-all.c -@@ -166,6 +166,10 @@ - # include "test-disassembler-four-args.c" - #undef main - -+#define main main_test_disassembler_init_styled -+# include "test-disassembler-init-styled.c" -+#undef main -+ - #define main main_test_libzstd - # include "test-libzstd.c" - #undef main -diff --git a/tools/build/feature/test-disassembler-init-styled.c b/tools/build/feature/test-disassembler-init-styled.c -new file mode 100644 -index 000000000000..f1ce0ec3bee9 ---- /dev/null -+++ b/tools/build/feature/test-disassembler-init-styled.c -@@ -0,0 +1,13 @@ -+// SPDX-License-Identifier: GPL-2.0 -+#include -+#include -+ -+int main(void) -+{ -+ struct disassemble_info info; -+ -+ init_disassemble_info(&info, stdout, -+ NULL, NULL); -+ -+ return 0; -+} - -From patchwork Mon Aug 1 01:38:28 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Andres Freund -X-Patchwork-Id: 12933314 -X-Patchwork-Delegate: bpf@iogearbox.net -Return-Path: -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) - by smtp.lore.kernel.org (Postfix) with ESMTP id C6F33C00140 - for ; Mon, 1 Aug 2022 01:38:46 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S238800AbiHABio (ORCPT ); - Sun, 31 Jul 2022 21:38:44 -0400 -Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48014 "EHLO - lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S238763AbiHABil (ORCPT ); - Sun, 31 Jul 2022 21:38:41 -0400 -Received: from wout1-smtp.messagingengine.com (wout1-smtp.messagingengine.com - [64.147.123.24]) - by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 352FFD117; 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Sun, - 31 Jul 2022 21:38:36 -0400 (EDT) -From: Andres Freund -To: bpf@vger.kernel.org, linux-kernel@vger.kernel.org -Cc: Alexei Starovoitov , - Arnaldo Carvalho de Melo , - Jiri Olsa , - Sedat Dilek , - Quentin Monnet , - Ben Hutchings -Subject: [PATCH v3 2/8] tools build: Don't display disassembler-four-args - feature test -Date: Sun, 31 Jul 2022 18:38:28 -0700 -Message-Id: <20220801013834.156015-3-andres@anarazel.de> -X-Mailer: git-send-email 2.37.0.3.g30cc8d0f14 -In-Reply-To: <20220801013834.156015-1-andres@anarazel.de> -References: <20220622231624.t63bkmkzphqvh3kx@alap3.anarazel.de> - <20220801013834.156015-1-andres@anarazel.de> -MIME-Version: 1.0 -Precedence: bulk -List-ID: -X-Mailing-List: bpf@vger.kernel.org - -The feature check does not seem important enough to display. Suggested by -Jiri Olsa. - -Cc: Jiri Olsa -Cc: Alexei Starovoitov -Cc: Arnaldo Carvalho de Melo -Cc: Sedat Dilek -Cc: Quentin Monnet -Link: http://lore.kernel.org/lkml/20220622181918.ykrs5rsnmx3og4sv@alap3.anarazel.de -Signed-off-by: Andres Freund ---- - tools/build/Makefile.feature | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/tools/build/Makefile.feature b/tools/build/Makefile.feature -index 8f6578e4d324..fc6ce0b2535a 100644 ---- a/tools/build/Makefile.feature -+++ b/tools/build/Makefile.feature -@@ -135,8 +135,7 @@ FEATURE_DISPLAY ?= \ - get_cpuid \ - bpf \ - libaio \ -- libzstd \ -- disassembler-four-args -+ libzstd - - # Set FEATURE_CHECK_(C|LD)FLAGS-all for all FEATURE_TESTS features. - # If in the future we need per-feature checks/flags for features not - -From patchwork Mon Aug 1 01:38:29 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Andres Freund -X-Patchwork-Id: 12933312 -X-Patchwork-Delegate: bpf@iogearbox.net -Return-Path: -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) - by smtp.lore.kernel.org (Postfix) with ESMTP id 66A9CC19F2D - for ; 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Sun, - 31 Jul 2022 21:38:36 -0400 (EDT) -From: Andres Freund -To: bpf@vger.kernel.org, linux-kernel@vger.kernel.org -Cc: Alexei Starovoitov , - Arnaldo Carvalho de Melo , - Jiri Olsa , - Sedat Dilek , - Quentin Monnet , - Ben Hutchings -Subject: [PATCH v3 3/8] tools include: add dis-asm-compat.h to handle version - differences -Date: Sun, 31 Jul 2022 18:38:29 -0700 -Message-Id: <20220801013834.156015-4-andres@anarazel.de> -X-Mailer: git-send-email 2.37.0.3.g30cc8d0f14 -In-Reply-To: <20220801013834.156015-1-andres@anarazel.de> -References: <20220622231624.t63bkmkzphqvh3kx@alap3.anarazel.de> - <20220801013834.156015-1-andres@anarazel.de> -MIME-Version: 1.0 -Precedence: bulk -List-ID: -X-Mailing-List: bpf@vger.kernel.org - -binutils changed the signature of init_disassemble_info(), which now causes -compilation failures for tools/{perf,bpf}, e.g. on debian unstable. -Relevant binutils commit: -https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=60a3da00bd5407f07 - -This commit introduces a wrapper for init_disassemble_info(), to avoid -spreading #ifdef DISASM_INIT_STYLED to a bunch of places. Subsequent -commits will use it to fix the build failures. - -It likely is worth adding a wrapper for disassember(), to avoid the already -existing DISASM_FOUR_ARGS_SIGNATURE ifdefery. - -Cc: Alexei Starovoitov -Cc: Arnaldo Carvalho de Melo -Cc: Sedat Dilek -Cc: Quentin Monnet -Cc: Ben Hutchings -Link: http://lore.kernel.org/lkml/20220622181918.ykrs5rsnmx3og4sv@alap3.anarazel.de -Signed-off-by: Andres Freund -Signed-off-by: Ben Hutchings ---- - tools/include/tools/dis-asm-compat.h | 55 ++++++++++++++++++++++++++++ - 1 file changed, 55 insertions(+) - create mode 100644 tools/include/tools/dis-asm-compat.h - -diff --git a/tools/include/tools/dis-asm-compat.h b/tools/include/tools/dis-asm-compat.h -new file mode 100644 -index 000000000000..70f331e23ed3 ---- /dev/null -+++ b/tools/include/tools/dis-asm-compat.h -@@ -0,0 +1,55 @@ -+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -+#ifndef _TOOLS_DIS_ASM_COMPAT_H -+#define _TOOLS_DIS_ASM_COMPAT_H -+ -+#include -+#include -+ -+/* define types for older binutils version, to centralize ifdef'ery a bit */ -+#ifndef DISASM_INIT_STYLED -+enum disassembler_style {DISASSEMBLER_STYLE_NOT_EMPTY}; -+typedef int (*fprintf_styled_ftype) (void *, enum disassembler_style, const char*, ...); -+#endif -+ -+/* -+ * Trivial fprintf wrapper to be used as the fprintf_styled_func argument to -+ * init_disassemble_info_compat() when normal fprintf suffices. -+ */ -+static inline int fprintf_styled(void *out, -+ enum disassembler_style style, -+ const char *fmt, ...) -+{ -+ va_list args; -+ int r; -+ -+ (void)style; -+ -+ va_start(args, fmt); -+ r = vfprintf(out, fmt, args); -+ va_end(args); -+ -+ return r; -+} -+ -+/* -+ * Wrapper for init_disassemble_info() that hides version -+ * differences. Depending on binutils version and architecture either -+ * fprintf_func or fprintf_styled_func will be called. -+ */ -+static inline void init_disassemble_info_compat(struct disassemble_info *info, -+ void *stream, -+ fprintf_ftype unstyled_func, -+ fprintf_styled_ftype styled_func) -+{ -+#ifdef DISASM_INIT_STYLED -+ init_disassemble_info(info, stream, -+ unstyled_func, -+ styled_func); -+#else -+ (void)styled_func; -+ init_disassemble_info(info, stream, -+ unstyled_func); -+#endif -+} -+ -+#endif /* _TOOLS_DIS_ASM_COMPAT_H */ - -From patchwork Mon Aug 1 01:38:30 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Andres Freund -X-Patchwork-Id: 12933311 -X-Patchwork-Delegate: bpf@iogearbox.net -Return-Path: -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) - by smtp.lore.kernel.org (Postfix) with ESMTP id 7EA44C19F2A - for ; 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Sun, - 31 Jul 2022 21:38:36 -0400 (EDT) -From: Andres Freund -To: bpf@vger.kernel.org, linux-kernel@vger.kernel.org -Cc: Alexei Starovoitov , - Arnaldo Carvalho de Melo , - Jiri Olsa , - Sedat Dilek , - Quentin Monnet , - Ben Hutchings -Subject: [PATCH v3 4/8] tools perf: Fix compilation error with new binutils -Date: Sun, 31 Jul 2022 18:38:30 -0700 -Message-Id: <20220801013834.156015-5-andres@anarazel.de> -X-Mailer: git-send-email 2.37.0.3.g30cc8d0f14 -In-Reply-To: <20220801013834.156015-1-andres@anarazel.de> -References: <20220622231624.t63bkmkzphqvh3kx@alap3.anarazel.de> - <20220801013834.156015-1-andres@anarazel.de> -MIME-Version: 1.0 -Precedence: bulk -List-ID: -X-Mailing-List: bpf@vger.kernel.org - -binutils changed the signature of init_disassemble_info(), which now causes -compilation failures for tools/perf/util/annotate.c, e.g. on debian -unstable. Relevant binutils commit: -https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=60a3da00bd5407f07 - -Wire up the feature test and switch to init_disassemble_info_compat(), -which were introduced in prior commits, fixing the compilation failure. - -I verified that perf can still disassemble bpf programs by using bpftrace -under load, recording a perf trace, and then annotating the bpf "function" -with and without the changes. With old binutils there's no change in output -before/after this patch. When comparing the output from old binutils (2.35) -to new bintuils with the patch (upstream snapshot) there are a few output -differences, but they are unrelated to this patch. An example hunk is: - - 1.15 : 55:mov %rbp,%rdx - 0.00 : 58:add $0xfffffffffffffff8,%rdx - 0.00 : 5c:xor %ecx,%ecx -- 1.03 : 5e:callq 0xffffffffe12aca3c -+ 1.03 : 5e:call 0xffffffffe12aca3c - 0.00 : 63:xor %eax,%eax -- 2.18 : 65:leaveq -- 2.82 : 66:retq -+ 2.18 : 65:leave -+ 2.82 : 66:ret - -Cc: Arnaldo Carvalho de Melo -Cc: Sedat Dilek -Link: http://lore.kernel.org/lkml/20220622181918.ykrs5rsnmx3og4sv@alap3.anarazel.de -Signed-off-by: Andres Freund ---- - tools/perf/Makefile.config | 8 ++++++++ - tools/perf/util/annotate.c | 7 ++++--- - 2 files changed, 12 insertions(+), 3 deletions(-) - -diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config -index 73e0762092fe..ee417c321adb 100644 ---- a/tools/perf/Makefile.config -+++ b/tools/perf/Makefile.config -@@ -298,6 +298,7 @@ FEATURE_CHECK_LDFLAGS-libpython := $(PYTHON_EMBED_LDOPTS) - FEATURE_CHECK_LDFLAGS-libaio = -lrt - - FEATURE_CHECK_LDFLAGS-disassembler-four-args = -lbfd -lopcodes -ldl -+FEATURE_CHECK_LDFLAGS-disassembler-init-styled = -lbfd -lopcodes -ldl - - CORE_CFLAGS += -fno-omit-frame-pointer - CORE_CFLAGS += -ggdb3 -@@ -905,13 +906,16 @@ ifndef NO_LIBBFD - ifeq ($(feature-libbfd-liberty), 1) - EXTLIBS += -lbfd -lopcodes -liberty - FEATURE_CHECK_LDFLAGS-disassembler-four-args += -liberty -ldl -+ FEATURE_CHECK_LDFLAGS-disassembler-init-styled += -liberty -ldl - else - ifeq ($(feature-libbfd-liberty-z), 1) - EXTLIBS += -lbfd -lopcodes -liberty -lz - FEATURE_CHECK_LDFLAGS-disassembler-four-args += -liberty -lz -ldl -+ FEATURE_CHECK_LDFLAGS-disassembler-init-styled += -liberty -lz -ldl - endif - endif - $(call feature_check,disassembler-four-args) -+ $(call feature_check,disassembler-init-styled) - endif - - ifeq ($(feature-libbfd-buildid), 1) -@@ -1025,6 +1029,10 @@ ifeq ($(feature-disassembler-four-args), 1) - CFLAGS += -DDISASM_FOUR_ARGS_SIGNATURE - endif - -+ifeq ($(feature-disassembler-init-styled), 1) -+ CFLAGS += -DDISASM_INIT_STYLED -+endif -+ - ifeq (${IS_64_BIT}, 1) - ifndef NO_PERF_READ_VDSO32 - $(call feature_check,compile-32) -diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c -index 82cc396ef516..2c6a485c3de5 100644 ---- a/tools/perf/util/annotate.c -+++ b/tools/perf/util/annotate.c -@@ -1720,6 +1720,7 @@ static int dso__disassemble_filename(struct dso *dso, char *filename, size_t fil - #include - #include - #include -+#include - - static int symbol__disassemble_bpf(struct symbol *sym, - struct annotate_args *args) -@@ -1762,9 +1763,9 @@ static int symbol__disassemble_bpf(struct symbol *sym, - ret = errno; - goto out; - } -- init_disassemble_info(&info, s, -- (fprintf_ftype) fprintf); -- -+ init_disassemble_info_compat(&info, s, -+ (fprintf_ftype) fprintf, -+ fprintf_styled); - info.arch = bfd_get_arch(bfdf); - info.mach = bfd_get_mach(bfdf); - - -From patchwork Mon Aug 1 01:38:31 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Andres Freund -X-Patchwork-Id: 12933317 -X-Patchwork-Delegate: bpf@iogearbox.net -Return-Path: -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) - by smtp.lore.kernel.org (Postfix) with ESMTP id C8AE6C00140 - for ; Mon, 1 Aug 2022 01:38:51 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S238834AbiHABit (ORCPT ); - Sun, 31 Jul 2022 21:38:49 -0400 -Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48012 "EHLO - lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S238774AbiHABim (ORCPT ); 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Sun, - 31 Jul 2022 21:38:38 -0400 (EDT) -From: Andres Freund -To: bpf@vger.kernel.org, linux-kernel@vger.kernel.org -Cc: Alexei Starovoitov , - Arnaldo Carvalho de Melo , - Jiri Olsa , - Sedat Dilek , - Quentin Monnet , - Ben Hutchings , - Daniel Borkmann -Subject: [PATCH v3 5/8] tools bpf_jit_disasm: Fix compilation error with new - binutils -Date: Sun, 31 Jul 2022 18:38:31 -0700 -Message-Id: <20220801013834.156015-6-andres@anarazel.de> -X-Mailer: git-send-email 2.37.0.3.g30cc8d0f14 -In-Reply-To: <20220801013834.156015-1-andres@anarazel.de> -References: <20220622231624.t63bkmkzphqvh3kx@alap3.anarazel.de> - <20220801013834.156015-1-andres@anarazel.de> -MIME-Version: 1.0 -Precedence: bulk -List-ID: -X-Mailing-List: bpf@vger.kernel.org -X-Patchwork-Delegate: bpf@iogearbox.net - -binutils changed the signature of init_disassemble_info(), which now causes -compilation to fail for tools/bpf/bpf_jit_disasm.c, e.g. on debian -unstable. Relevant binutils commit: -https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=60a3da00bd5407f07 - -Wire up the feature test and switch to init_disassemble_info_compat(), -which were introduced in prior commits, fixing the compilation failure. - -I verified that bpf_jit_disasm can still disassemble bpf programs, both -with the old and new dis-asm.h API. With old binutils there's no change in -output before/after this patch. When comparing the output from old -binutils (2.35) to new bintuils with the patch (upstream snapshot) there -are a few output differences, but they are unrelated to this patch. An -example hunk is: - f4: mov %r14,%rsi - f7: mov %r15,%rdx - fa: mov $0x2a,%ecx -- ff: callq 0xffffffffea8c4988 -+ ff: call 0xffffffffea8c4988 - 104: test %rax,%rax - 107: jge 0x0000000000000110 - 109: xor %eax,%eax -- 10b: jmpq 0x0000000000000073 -+ 10b: jmp 0x0000000000000073 - 110: cmp $0x16,%rax - -However, I had to use an older kernel to generate the bpf_jit_enabled = 2 -output, as that has been broken since 5.18 / 1022a5498f6f: -https://lore.kernel.org/20220703030210.pmjft7qc2eajzi6c@alap3.anarazel.de - -Cc: Alexei Starovoitov -Cc: Daniel Borkmann -Cc: Sedat Dilek -Cc: Quentin Monnet -Link: http://lore.kernel.org/lkml/20220622181918.ykrs5rsnmx3og4sv@alap3.anarazel.de -Signed-off-by: Andres Freund ---- - tools/bpf/Makefile | 5 ++++- - tools/bpf/bpf_jit_disasm.c | 5 ++++- - 2 files changed, 8 insertions(+), 2 deletions(-) - -diff --git a/tools/bpf/Makefile b/tools/bpf/Makefile -index b11cfc86a3d0..664601ab1705 100644 ---- a/tools/bpf/Makefile -+++ b/tools/bpf/Makefile -@@ -34,7 +34,7 @@ else - endif - - FEATURE_USER = .bpf --FEATURE_TESTS = libbfd disassembler-four-args -+FEATURE_TESTS = libbfd disassembler-four-args disassembler-init-styled - FEATURE_DISPLAY = libbfd disassembler-four-args - - check_feat := 1 -@@ -56,6 +56,9 @@ endif - ifeq ($(feature-disassembler-four-args), 1) - CFLAGS += -DDISASM_FOUR_ARGS_SIGNATURE - endif -+ifeq ($(feature-disassembler-init-styled), 1) -+CFLAGS += -DDISASM_INIT_STYLED -+endif - - $(OUTPUT)%.yacc.c: $(srctree)/tools/bpf/%.y - $(QUIET_BISON)$(YACC) -o $@ -d $< -diff --git a/tools/bpf/bpf_jit_disasm.c b/tools/bpf/bpf_jit_disasm.c -index c8ae95804728..a90a5d110f92 100644 ---- a/tools/bpf/bpf_jit_disasm.c -+++ b/tools/bpf/bpf_jit_disasm.c -@@ -28,6 +28,7 @@ - #include - #include - #include -+#include - - #define CMD_ACTION_SIZE_BUFFER 10 - #define CMD_ACTION_READ_ALL 3 -@@ -64,7 +65,9 @@ static void get_asm_insns(uint8_t *image, size_t len, int opcodes) - assert(bfdf); - assert(bfd_check_format(bfdf, bfd_object)); - -- init_disassemble_info(&info, stdout, (fprintf_ftype) fprintf); -+ init_disassemble_info_compat(&info, stdout, -+ (fprintf_ftype) fprintf, -+ fprintf_styled); - info.arch = bfd_get_arch(bfdf); - info.mach = bfd_get_mach(bfdf); - info.buffer = image; - -From patchwork Mon Aug 1 01:38:32 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Andres Freund -X-Patchwork-Id: 12933315 -X-Patchwork-Delegate: bpf@iogearbox.net -Return-Path: -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) - by smtp.lore.kernel.org (Postfix) with ESMTP id 96658C19F2A - for ; Mon, 1 Aug 2022 01:38:48 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S238807AbiHABip (ORCPT ); - Sun, 31 Jul 2022 21:38:45 -0400 -Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48024 "EHLO - lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org - with ESMTP id S238765AbiHABil (ORCPT ); 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Sun, - 31 Jul 2022 21:38:38 -0400 (EDT) -From: Andres Freund -To: bpf@vger.kernel.org, linux-kernel@vger.kernel.org -Cc: Alexei Starovoitov , - Arnaldo Carvalho de Melo , - Jiri Olsa , - Sedat Dilek , - Quentin Monnet , - Ben Hutchings , - Daniel Borkmann -Subject: [PATCH v3 6/8] tools bpf_jit_disasm: Don't display - disassembler-four-args feature test -Date: Sun, 31 Jul 2022 18:38:32 -0700 -Message-Id: <20220801013834.156015-7-andres@anarazel.de> -X-Mailer: git-send-email 2.37.0.3.g30cc8d0f14 -In-Reply-To: <20220801013834.156015-1-andres@anarazel.de> -References: <20220622231624.t63bkmkzphqvh3kx@alap3.anarazel.de> - <20220801013834.156015-1-andres@anarazel.de> -MIME-Version: 1.0 -Precedence: bulk -List-ID: -X-Mailing-List: bpf@vger.kernel.org -X-Patchwork-Delegate: bpf@iogearbox.net - -The feature check does not seem important enough to display. Suggested by -Jiri Olsa. - -Cc: Jiri Olsa -Cc: Alexei Starovoitov -Cc: Daniel Borkmann -Cc: Sedat Dilek -Cc: Quentin Monnet -Link: http://lore.kernel.org/lkml/20220622181918.ykrs5rsnmx3og4sv@alap3.anarazel.de -Signed-off-by: Andres Freund ---- - tools/bpf/Makefile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/tools/bpf/Makefile b/tools/bpf/Makefile -index 664601ab1705..243b79f2b451 100644 ---- a/tools/bpf/Makefile -+++ b/tools/bpf/Makefile -@@ -35,7 +35,7 @@ endif - - FEATURE_USER = .bpf - FEATURE_TESTS = libbfd disassembler-four-args disassembler-init-styled --FEATURE_DISPLAY = libbfd disassembler-four-args -+FEATURE_DISPLAY = libbfd - - check_feat := 1 - NON_CHECK_FEAT_TARGETS := clean bpftool_clean runqslower_clean resolve_btfids_clean - -From patchwork Mon Aug 1 01:38:33 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Andres Freund -X-Patchwork-Id: 12933318 -X-Patchwork-Delegate: bpf@iogearbox.net -Return-Path: -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) - by smtp.lore.kernel.org (Postfix) with ESMTP id E29C6C19F2D - for ; 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Sun, - 31 Jul 2022 21:38:38 -0400 (EDT) -From: Andres Freund -To: bpf@vger.kernel.org, linux-kernel@vger.kernel.org -Cc: Alexei Starovoitov , - Arnaldo Carvalho de Melo , - Jiri Olsa , - Sedat Dilek , - Quentin Monnet , - Ben Hutchings -Subject: [PATCH v3 7/8] tools bpftool: Fix compilation error with new binutils -Date: Sun, 31 Jul 2022 18:38:33 -0700 -Message-Id: <20220801013834.156015-8-andres@anarazel.de> -X-Mailer: git-send-email 2.37.0.3.g30cc8d0f14 -In-Reply-To: <20220801013834.156015-1-andres@anarazel.de> -References: <20220622231624.t63bkmkzphqvh3kx@alap3.anarazel.de> - <20220801013834.156015-1-andres@anarazel.de> -MIME-Version: 1.0 -Precedence: bulk -List-ID: -X-Mailing-List: bpf@vger.kernel.org -X-Patchwork-Delegate: bpf@iogearbox.net - -binutils changed the signature of init_disassemble_info(), which now causes -compilation to fail for tools/bpf/bpftool/jit_disasm.c, e.g. on debian -unstable. Relevant binutils commit: -https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=60a3da00bd5407f07 - -Wire up the feature test and switch to init_disassemble_info_compat(), -which were introduced in prior commits, fixing the compilation failure. - -I verified that bpftool can still disassemble bpf programs, both with an -old and new dis-asm.h API. There are no output changes for plain and json -formats. When comparing the output from old binutils (2.35) -to new bintuils with the patch (upstream snapshot) there are a few output -differences, but they are unrelated to this patch. An example hunk is: - 2f: pop %r14 - 31: pop %r13 - 33: pop %rbx -- 34: leaveq -- 35: retq -+ 34: leave -+ 35: ret - -Cc: Alexei Starovoitov -Cc: Sedat Dilek -Cc: Quentin Monnet -Link: http://lore.kernel.org/lkml/20220622181918.ykrs5rsnmx3og4sv@alap3.anarazel.de -Signed-off-by: Andres Freund ---- - tools/bpf/bpftool/Makefile | 5 +++- - tools/bpf/bpftool/jit_disasm.c | 42 +++++++++++++++++++++++++++------- - 2 files changed, 38 insertions(+), 9 deletions(-) - -diff --git a/tools/bpf/bpftool/Makefile b/tools/bpf/bpftool/Makefile -index c6d2c77d0252..436e671b2657 100644 ---- a/tools/bpf/bpftool/Makefile -+++ b/tools/bpf/bpftool/Makefile -@@ -93,7 +93,7 @@ INSTALL ?= install - RM ?= rm -f - - FEATURE_USER = .bpftool --FEATURE_TESTS = libbfd disassembler-four-args zlib libcap \ -+FEATURE_TESTS = libbfd disassembler-four-args disassembler-init-styled zlib libcap \ - clang-bpf-co-re - FEATURE_DISPLAY = libbfd disassembler-four-args zlib libcap \ - clang-bpf-co-re -@@ -117,6 +117,9 @@ endif - ifeq ($(feature-disassembler-four-args), 1) - CFLAGS += -DDISASM_FOUR_ARGS_SIGNATURE - endif -+ifeq ($(feature-disassembler-init-styled), 1) -+ CFLAGS += -DDISASM_INIT_STYLED -+endif - - LIBS = $(LIBBPF) -lelf -lz - LIBS_BOOTSTRAP = $(LIBBPF_BOOTSTRAP) -lelf -lz -diff --git a/tools/bpf/bpftool/jit_disasm.c b/tools/bpf/bpftool/jit_disasm.c -index 24734f2249d6..aaf99a0168c9 100644 ---- a/tools/bpf/bpftool/jit_disasm.c -+++ b/tools/bpf/bpftool/jit_disasm.c -@@ -24,6 +24,7 @@ - #include - #include - #include -+#include - - #include "json_writer.h" - #include "main.h" -@@ -39,15 +40,12 @@ static void get_exec_path(char *tpath, size_t size) - } - - static int oper_count; --static int fprintf_json(void *out, const char *fmt, ...) -+static int printf_json(void *out, const char *fmt, va_list ap) - { -- va_list ap; - char *s; - int err; - -- va_start(ap, fmt); - err = vasprintf(&s, fmt, ap); -- va_end(ap); - if (err < 0) - return -1; - -@@ -73,6 +71,32 @@ static int fprintf_json(void *out, const char *fmt, ...) - return 0; - } - -+static int fprintf_json(void *out, const char *fmt, ...) -+{ -+ va_list ap; -+ int r; -+ -+ va_start(ap, fmt); -+ r = printf_json(out, fmt, ap); -+ va_end(ap); -+ -+ return r; -+} -+ -+static int fprintf_json_styled(void *out, -+ enum disassembler_style style __maybe_unused, -+ const char *fmt, ...) -+{ -+ va_list ap; -+ int r; -+ -+ va_start(ap, fmt); -+ r = printf_json(out, fmt, ap); -+ va_end(ap); -+ -+ return r; -+} -+ - void disasm_print_insn(unsigned char *image, ssize_t len, int opcodes, - const char *arch, const char *disassembler_options, - const struct btf *btf, -@@ -99,11 +123,13 @@ void disasm_print_insn(unsigned char *image, ssize_t len, int opcodes, - assert(bfd_check_format(bfdf, bfd_object)); - - if (json_output) -- init_disassemble_info(&info, stdout, -- (fprintf_ftype) fprintf_json); -+ init_disassemble_info_compat(&info, stdout, -+ (fprintf_ftype) fprintf_json, -+ fprintf_json_styled); - else -- init_disassemble_info(&info, stdout, -- (fprintf_ftype) fprintf); -+ init_disassemble_info_compat(&info, stdout, -+ (fprintf_ftype) fprintf, -+ fprintf_styled); - - /* Update architecture info for offload. */ - if (arch) { - -From patchwork Mon Aug 1 01:38:34 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Andres Freund -X-Patchwork-Id: 12933316 -X-Patchwork-Delegate: bpf@iogearbox.net -Return-Path: -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) - by smtp.lore.kernel.org (Postfix) with ESMTP id A8B94C00140 - for ; Mon, 1 Aug 2022 01:38:49 +0000 (UTC) -Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand - id S238562AbiHABir (ORCPT ); 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Sun, - 31 Jul 2022 21:38:38 -0400 (EDT) -From: Andres Freund -To: bpf@vger.kernel.org, linux-kernel@vger.kernel.org -Cc: Alexei Starovoitov , - Arnaldo Carvalho de Melo , - Jiri Olsa , - Sedat Dilek , - Quentin Monnet , - Ben Hutchings -Subject: [PATCH v3 8/8] tools bpftool: Don't display disassembler-four-args - feature test -Date: Sun, 31 Jul 2022 18:38:34 -0700 -Message-Id: <20220801013834.156015-9-andres@anarazel.de> -X-Mailer: git-send-email 2.37.0.3.g30cc8d0f14 -In-Reply-To: <20220801013834.156015-1-andres@anarazel.de> -References: <20220622231624.t63bkmkzphqvh3kx@alap3.anarazel.de> - <20220801013834.156015-1-andres@anarazel.de> -MIME-Version: 1.0 -Precedence: bulk -List-ID: -X-Mailing-List: bpf@vger.kernel.org -X-Patchwork-Delegate: bpf@iogearbox.net - -The feature check does not seem important enough to display. Requested by -Jiri Olsa. - -Cc: Jiri Olsa -Cc: Alexei Starovoitov -Cc: Sedat Dilek -Cc: Quentin Monnet -Link: http://lore.kernel.org/lkml/20220622181918.ykrs5rsnmx3og4sv@alap3.anarazel.de -Signed-off-by: Andres Freund ---- - tools/bpf/bpftool/Makefile | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/tools/bpf/bpftool/Makefile b/tools/bpf/bpftool/Makefile -index 436e671b2657..517df016d54a 100644 ---- a/tools/bpf/bpftool/Makefile -+++ b/tools/bpf/bpftool/Makefile -@@ -95,8 +95,7 @@ RM ?= rm -f - FEATURE_USER = .bpftool - FEATURE_TESTS = libbfd disassembler-four-args disassembler-init-styled zlib libcap \ - clang-bpf-co-re --FEATURE_DISPLAY = libbfd disassembler-four-args zlib libcap \ -- clang-bpf-co-re -+FEATURE_DISPLAY = libbfd zlib libcap clang-bpf-co-re - - check_feat := 1 - NON_CHECK_FEAT_TARGETS := clean uninstall doc doc-clean doc-install doc-uninstall From f1bea96ff50c846d640b23601adf265a07b54378 Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Thu, 29 Sep 2022 10:57:46 +0000 Subject: [PATCH 28/29] linux (Allwinner): new patch to support kernel 6.0 --- .../0066-temporary-disable-iommu-on-H6.patch | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 projects/Allwinner/patches/linux/0066-temporary-disable-iommu-on-H6.patch diff --git a/projects/Allwinner/patches/linux/0066-temporary-disable-iommu-on-H6.patch b/projects/Allwinner/patches/linux/0066-temporary-disable-iommu-on-H6.patch new file mode 100644 index 0000000000..8096bf6b2a --- /dev/null +++ b/projects/Allwinner/patches/linux/0066-temporary-disable-iommu-on-H6.patch @@ -0,0 +1,37 @@ +From 708274855501cfb1cf4ed01d4e68758d94a4c506 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Wed, 28 Sep 2022 22:23:34 +0200 +Subject: [PATCH] HACK: temporary disable iommu on H6 + +Since driver is not enabled, peripherals with iommu phandle are probed +very late. Workaround that by removing iommu phandles until driver is +enabled. + +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index fbe94abbb1f9..4a8abc3ace16 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -136,7 +136,6 @@ mixer0: mixer@100000 { + clock-names = "bus", + "mod"; + resets = <&display_clocks RST_MIXER0>; +- iommus = <&iommu 0>; + + ports { + #address-cells = <1>; +@@ -171,7 +170,6 @@ video-codec@1c0e000 { + resets = <&ccu RST_BUS_VE>; + interrupts = ; + allwinner,sram = <&ve_sram 1>; +- iommus = <&iommu 3>; + }; + + gpu: gpu@1800000 { +-- +2.37.3 + From 3a3b2bd6dec5f3fd14ca1afe429fdb07d3a2b77e Mon Sep 17 00:00:00 2001 From: Rudi Heitbaum Date: Tue, 4 Oct 2022 19:48:20 +0000 Subject: [PATCH 29/29] linux (Allwinner): cedrus fixes for Linux 6.0 --- ...cedrus--Don-t-CPU-map-source-buffers.patch | 26 ++++++ ...cedrus--hevc--Fix-offset-adjustments.patch | 91 +++++++++++++++++++ ...-cedrus--Fix-watchdog-race-condition.patch | 62 +++++++++++++ 3 files changed, 179 insertions(+) create mode 100644 projects/Allwinner/patches/linux/0061-media--cedrus--Don-t-CPU-map-source-buffers.patch create mode 100644 projects/Allwinner/patches/linux/0062-media--cedrus--hevc--Fix-offset-adjustments.patch create mode 100644 projects/Allwinner/patches/linux/0064-media--cedrus--Fix-watchdog-race-condition.patch diff --git a/projects/Allwinner/patches/linux/0061-media--cedrus--Don-t-CPU-map-source-buffers.patch b/projects/Allwinner/patches/linux/0061-media--cedrus--Don-t-CPU-map-source-buffers.patch new file mode 100644 index 0000000000..1aeb3d60f2 --- /dev/null +++ b/projects/Allwinner/patches/linux/0061-media--cedrus--Don-t-CPU-map-source-buffers.patch @@ -0,0 +1,26 @@ +From 566615d14dd8b4a5dbc06f158cb35450b1105e35 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Tue, 4 Oct 2022 20:36:18 +0200 +Subject: [PATCH] media: cedrus: Don't CPU map source buffers + +There is no need to access source buffers via CPU, so let's disable +that. This will lower amount of virtual memory needed on 32-bit ARM +SoCs. + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus_video.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +index f1eb94197a3d6c..8967f221f359f9 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +@@ -601,6 +601,7 @@ int cedrus_queue_init(void *priv, struct vb2_queue *src_vq, + + src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT; + src_vq->io_modes = VB2_MMAP | VB2_DMABUF; ++ src_vq->dma_attrs = DMA_ATTR_NO_KERNEL_MAPPING; + src_vq->drv_priv = ctx; + src_vq->buf_struct_size = sizeof(struct cedrus_buffer); + src_vq->ops = &cedrus_qops; diff --git a/projects/Allwinner/patches/linux/0062-media--cedrus--hevc--Fix-offset-adjustments.patch b/projects/Allwinner/patches/linux/0062-media--cedrus--hevc--Fix-offset-adjustments.patch new file mode 100644 index 0000000000..97d93e3864 --- /dev/null +++ b/projects/Allwinner/patches/linux/0062-media--cedrus--hevc--Fix-offset-adjustments.patch @@ -0,0 +1,91 @@ +From e85edafea5122a1357c884559db1a00046102807 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Tue, 4 Oct 2022 20:28:44 +0200 +Subject: [PATCH] media: cedrus: hevc: Fix offset adjustments + +As it turns out, current padding size check works fine in theory but it +doesn't in practice. Most probable reason are caching issues. + +Let's rework reading data from bitstream using Cedrus engine instead of +CPU. That way we avoid all cache issues and make sure that we're reading +same data as Cedrus. + +Fixes: e7060d9a78c2 ("media: uapi: Change data_bit_offset definition") +Signed-off-by: Jernej Skrabec +--- + .../staging/media/sunxi/cedrus/cedrus_h265.c | 24 ++++++++++++++----- + .../staging/media/sunxi/cedrus/cedrus_regs.h | 2 ++ + 2 files changed, 20 insertions(+), 6 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +index 82e2e510e62509..400a7bc1670df3 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +@@ -281,6 +281,17 @@ static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num) + } + } + ++static u32 cedrus_h265_show_bits(struct cedrus_dev *dev, int num) ++{ ++ cedrus_write(dev, VE_DEC_H265_TRIGGER, ++ VE_DEC_H265_TRIGGER_SHOW_BITS | ++ VE_DEC_H265_TRIGGER_TYPE_N_BITS(num)); ++ while (cedrus_read(dev, VE_DEC_H265_STATUS) & VE_DEC_H265_STATUS_VLD_BUSY) ++ udelay(1); ++ ++ return cedrus_read(dev, VE_DEC_H265_READED_BITS); ++} ++ + static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx, + struct cedrus_run *run) + { +@@ -445,7 +456,7 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) + u32 num_entry_point_offsets; + u32 output_pic_list_index; + u32 pic_order_cnt[2]; +- u8 *padding; ++ u8 padding; + int count; + u32 reg; + +@@ -529,21 +540,22 @@ static int cedrus_h265_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) + if (slice_params->data_byte_offset == 0) + return -EOPNOTSUPP; + +- padding = (u8 *)vb2_plane_vaddr(&run->src->vb2_buf, 0) + +- slice_params->data_byte_offset - 1; ++ cedrus_h265_skip_bits(dev, (slice_params->data_byte_offset - 1) * 8); ++ ++ padding = cedrus_h265_show_bits(dev, 8); + + /* at least one bit must be set in that byte */ +- if (*padding == 0) ++ if (padding == 0) + return -EINVAL; + + for (count = 0; count < 8; count++) +- if (*padding & (1 << count)) ++ if (padding & (1 << count)) + break; + + /* Include the one bit. */ + count++; + +- cedrus_h265_skip_bits(dev, slice_params->data_byte_offset * 8 - count); ++ cedrus_h265_skip_bits(dev, 8 - count); + + /* Bitstream parameters. */ + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +index 2f7dbd8b8896e9..424049f567c465 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +@@ -509,6 +509,8 @@ + #define VE_DEC_H265_LOW_ADDR_ENTRY_POINTS_BUF(a) \ + SHIFT_AND_MASK_BITS(a, 7, 0) + ++#define VE_DEC_H265_READED_BITS (VE_ENGINE_DEC_H265 + 0xdc) ++ + #define VE_DEC_H265_SRAM_OFFSET (VE_ENGINE_DEC_H265 + 0xe0) + + #define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0 0x00 diff --git a/projects/Allwinner/patches/linux/0064-media--cedrus--Fix-watchdog-race-condition.patch b/projects/Allwinner/patches/linux/0064-media--cedrus--Fix-watchdog-race-condition.patch new file mode 100644 index 0000000000..9904bd7184 --- /dev/null +++ b/projects/Allwinner/patches/linux/0064-media--cedrus--Fix-watchdog-race-condition.patch @@ -0,0 +1,62 @@ +From: Nicolas Dufresne +To: linux-media@vger.kernel.org, Maxime Ripard , + Paul Kocialkowski , + Mauro Carvalho Chehab , + Greg Kroah-Hartman , + Chen-Yu Tsai , + Jernej Skrabec , + Samuel Holland , + Ezequiel Garcia , + Hans Verkuil +Cc: kernel@collabora.com, + Nicolas Dufresne , + stable@vger.kernel.org, linux-staging@lists.linux.dev, + linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, + linux-kernel@vger.kernel.org +Subject: [PATCH v1 1/3] media: cedrus: Fix watchdog race condition +Date: Thu, 18 Aug 2022 16:33:06 -0400 +Message-Id: <20220818203308.439043-2-nicolas.dufresne@collabora.com> +X-Mailer: git-send-email 2.37.2 +In-Reply-To: <20220818203308.439043-1-nicolas.dufresne@collabora.com> +References: <20220818203308.439043-1-nicolas.dufresne@collabora.com> +MIME-Version: 1.0 + +The watchdog needs to be schedule before we trigger the decode +operation, otherwise there is a risk that the decoder IRQ will be +called before we have schedule the watchdog. As a side effect, the +watchdog would never be cancelled and its function would be called +at an inappropriate time. + +This was observed while running Fluster with GStreamer as a backend. +Some programming error would cause the decoder IRQ to be call very +quickly after the trigger. Later calls into the driver would deadlock +due to the unbalanced state. + +Cc: stable@vger.kernel.org +Fixes: 7c38a551bda1 ("media: cedrus: Add watchdog for job completion") +Signed-off-by: Nicolas Dufresne +Reviewed-by: Paul Kocialkowski +Reviewed-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus_dec.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +index 3b6aa78a2985f..e7f7602a5ab40 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +@@ -106,11 +106,11 @@ void cedrus_device_run(void *priv) + + /* Trigger decoding if setup went well, bail out otherwise. */ + if (!error) { +- dev->dec_ops[ctx->current_codec]->trigger(ctx); +- + /* Start the watchdog timer. */ + schedule_delayed_work(&dev->watchdog_work, + msecs_to_jiffies(2000)); ++ ++ dev->dec_ops[ctx->current_codec]->trigger(ctx); + } else { + v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, + ctx->fh.m2m_ctx, +