From 10e9dfdcbb5fbd092ad15f9debd43a5bacfcd570 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Mon, 8 Feb 2021 10:32:41 +0000 Subject: [PATCH] Allwinner: linux: Remove patches included in 5.10.17 --- .../0021-media-cedrus-Fix-H264-decoding.patch | 33 -------- ...mp-fix-parent-rate-change-flag-check.patch | 25 ------ ...-set-sync-polarity-for-tcon1-channel.patch | 84 ------------------- ...-sun4i-dw-hdmi-always-set-clock-rate.patch | 49 ----------- ...-sun4i-Fix-H6-HDMI-PHY-configuration.patch | 24 ------ ...4i-dw-hdmi-Fix-max.-frequency-for-H6.patch | 34 -------- 6 files changed, 249 deletions(-) delete mode 100644 projects/Allwinner/patches/linux/0021-media-cedrus-Fix-H264-decoding.patch delete mode 100644 projects/Allwinner/patches/linux/0050-clk-sunxi-ng-mp-fix-parent-rate-change-flag-check.patch delete mode 100644 projects/Allwinner/patches/linux/0051-drm-sun4i-tcon-set-sync-polarity-for-tcon1-channel.patch delete mode 100644 projects/Allwinner/patches/linux/0052-drm-sun4i-dw-hdmi-always-set-clock-rate.patch delete mode 100644 projects/Allwinner/patches/linux/0053-drm-sun4i-Fix-H6-HDMI-PHY-configuration.patch delete mode 100644 projects/Allwinner/patches/linux/0054-drm-sun4i-dw-hdmi-Fix-max.-frequency-for-H6.patch diff --git a/projects/Allwinner/patches/linux/0021-media-cedrus-Fix-H264-decoding.patch b/projects/Allwinner/patches/linux/0021-media-cedrus-Fix-H264-decoding.patch deleted file mode 100644 index f2af6e6cab..0000000000 --- a/projects/Allwinner/patches/linux/0021-media-cedrus-Fix-H264-decoding.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 3a9d4fe5b89c783d2162c84db3cabf00c3bca983 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 23 Dec 2020 11:23:40 +0100 -Subject: [PATCH 21/44] media: cedrus: Fix H264 decoding - -During H264 API overhaul subtle bug was introduced Cedrus driver. -Progressive references have both, top and bottom reference flags set. -Cedrus reference list expects only bottom reference flag and only when -interlaced frames are decoded. However, due to a bug in Cedrus check, -exclusivity is not tested and that flag is set also for progressive -references. That causes "jumpy" background with many videos. - -Fix that by checking that only bottom reference flag is set in control -and nothing else. - -Tested-by: Andre Heider -Fixes: cfc8c3ed533e ("media: cedrus: h264: Properly configure reference field") -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -@@ -203,7 +203,7 @@ static void _cedrus_write_ref_list(struc - position = cedrus_buf->codec.h264.position; - - sram_array[i] |= position << 1; -- if (ref_list[i].fields & V4L2_H264_BOTTOM_FIELD_REF) -+ if (ref_list[i].fields == V4L2_H264_BOTTOM_FIELD_REF) - sram_array[i] |= BIT(0); - } - diff --git a/projects/Allwinner/patches/linux/0050-clk-sunxi-ng-mp-fix-parent-rate-change-flag-check.patch b/projects/Allwinner/patches/linux/0050-clk-sunxi-ng-mp-fix-parent-rate-change-flag-check.patch deleted file mode 100644 index 36aa86d14d..0000000000 --- a/projects/Allwinner/patches/linux/0050-clk-sunxi-ng-mp-fix-parent-rate-change-flag-check.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 3 Feb 2021 23:09:31 +0100 -Subject: [PATCH] clk: sunxi-ng: mp: fix parent rate change flag check - -CLK_SET_RATE_PARENT flag is checked on parent clock instead of current -one. Fix that. - -Fixes: 3f790433c3cb ("clk: sunxi-ng: Adjust MP clock parent rate when allowed") -Signed-off-by: Jernej Skrabec ---- - drivers/clk/sunxi-ng/ccu_mp.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/clk/sunxi-ng/ccu_mp.c -+++ b/drivers/clk/sunxi-ng/ccu_mp.c -@@ -108,7 +108,7 @@ static unsigned long ccu_mp_round_rate(s - max_m = cmp->m.max ?: 1 << cmp->m.width; - max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); - -- if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { -+ if (!(clk_hw_get_flags(&cmp->common.hw) & CLK_SET_RATE_PARENT)) { - ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p); - rate = *parent_rate / p / m; - } else { diff --git a/projects/Allwinner/patches/linux/0051-drm-sun4i-tcon-set-sync-polarity-for-tcon1-channel.patch b/projects/Allwinner/patches/linux/0051-drm-sun4i-tcon-set-sync-polarity-for-tcon1-channel.patch deleted file mode 100644 index 69f67da4b1..0000000000 --- a/projects/Allwinner/patches/linux/0051-drm-sun4i-tcon-set-sync-polarity-for-tcon1-channel.patch +++ /dev/null @@ -1,84 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 3 Feb 2021 23:16:42 +0100 -Subject: [PATCH] drm/sun4i: tcon: set sync polarity for tcon1 channel - -Channel 1 has polarity bits for vsync and hsync signals but driver never -sets them. It turns out that with pre-HDMI2 controllers seemingly there -is no issue if polarity is not set. However, with HDMI2 controllers -(H6) there often comes to de-synchronization due to phase shift. This -causes flickering screen. It's safe to assume that similar issues might -happen also with pre-HDMI2 controllers. - -Solve issue with setting vsync and hsync polarity. Note that display -stacks with tcon top have polarity bits actually in tcon0 polarity -register. - -Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support") -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun4i_tcon.c | 24 ++++++++++++++++++++++++ - drivers/gpu/drm/sun4i/sun4i_tcon.h | 5 +++++ - 2 files changed, 29 insertions(+) - ---- a/drivers/gpu/drm/sun4i/sun4i_tcon.c -+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c -@@ -689,6 +689,29 @@ static void sun4i_tcon1_mode_set(struct - SUN4I_TCON1_BASIC5_V_SYNC(vsync) | - SUN4I_TCON1_BASIC5_H_SYNC(hsync)); - -+ /* Setup the polarity of sync signals */ -+ if (tcon->quirks->polarity_in_ch0) { -+ val = 0; -+ -+ if (mode->flags & DRM_MODE_FLAG_PHSYNC) -+ val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE; -+ -+ if (mode->flags & DRM_MODE_FLAG_PVSYNC) -+ val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; -+ -+ regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); -+ } else { -+ val = SUN4I_TCON1_IO_POL_UNKNOWN; -+ -+ if (mode->flags & DRM_MODE_FLAG_PHSYNC) -+ val |= SUN4I_TCON1_IO_POL_HSYNC_POSITIVE; -+ -+ if (mode->flags & DRM_MODE_FLAG_PVSYNC) -+ val |= SUN4I_TCON1_IO_POL_VSYNC_POSITIVE; -+ -+ regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val); -+ } -+ - /* Map output pins to channel 1 */ - regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, - SUN4I_TCON_GCTL_IOMAP_MASK, -@@ -1517,6 +1540,7 @@ static const struct sun4i_tcon_quirks su - - static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = { - .has_channel_1 = true, -+ .polarity_in_ch0 = true, - .set_mux = sun8i_r40_tcon_tv_set_mux, - }; - ---- a/drivers/gpu/drm/sun4i/sun4i_tcon.h -+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h -@@ -153,6 +153,10 @@ - #define SUN4I_TCON1_BASIC5_V_SYNC(height) (((height) - 1) & 0x3ff) - - #define SUN4I_TCON1_IO_POL_REG 0xf0 -+#define SUN4I_TCON1_IO_POL_UNKNOWN BIT(26) -+#define SUN4I_TCON1_IO_POL_HSYNC_POSITIVE BIT(25) -+#define SUN4I_TCON1_IO_POL_VSYNC_POSITIVE BIT(24) -+ - #define SUN4I_TCON1_IO_TRI_REG 0xf4 - - #define SUN4I_TCON_ECC_FIFO_REG 0xf8 -@@ -235,6 +239,7 @@ struct sun4i_tcon_quirks { - bool needs_de_be_mux; /* sun6i needs mux to select backend */ - bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */ - bool supports_lvds; /* Does the TCON support an LVDS output? */ -+ bool polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */ - u8 dclk_min_div; /* minimum divider for TCON0 DCLK */ - - /* callback to handle tcon muxing options */ diff --git a/projects/Allwinner/patches/linux/0052-drm-sun4i-dw-hdmi-always-set-clock-rate.patch b/projects/Allwinner/patches/linux/0052-drm-sun4i-dw-hdmi-always-set-clock-rate.patch deleted file mode 100644 index 602b3ab78a..0000000000 --- a/projects/Allwinner/patches/linux/0052-drm-sun4i-dw-hdmi-always-set-clock-rate.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 3 Feb 2021 23:25:13 +0100 -Subject: [PATCH] drm/sun4i: dw-hdmi: always set clock rate - -As expected, HDMI controller clock should always match pixel clock. In -the past, changing HDMI controller rate would seemingly worsen -situation. However, that was the result of other bugs which are now -fixed. - -Fix that by removing set_rate quirk and always set clock rate. - -Fixes: 40bb9d3147b2 ("drm/sun4i: Add support for H6 DW HDMI controller") -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 4 +--- - drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 - - 2 files changed, 1 insertion(+), 4 deletions(-) - ---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -@@ -21,8 +21,7 @@ static void sun8i_dw_hdmi_encoder_mode_s - { - struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder); - -- if (hdmi->quirks->set_rate) -- clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000); -+ clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000); - } - - static const struct drm_encoder_helper_funcs -@@ -295,7 +294,6 @@ static int sun8i_dw_hdmi_remove(struct p - - static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = { - .mode_valid = sun8i_dw_hdmi_mode_valid_a83t, -- .set_rate = true, - }; - - static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = { ---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -@@ -179,7 +179,6 @@ struct sun8i_dw_hdmi_quirks { - enum drm_mode_status (*mode_valid)(struct dw_hdmi *hdmi, void *data, - const struct drm_display_info *info, - const struct drm_display_mode *mode); -- unsigned int set_rate : 1; - unsigned int use_drm_infoframe : 1; - }; - diff --git a/projects/Allwinner/patches/linux/0053-drm-sun4i-Fix-H6-HDMI-PHY-configuration.patch b/projects/Allwinner/patches/linux/0053-drm-sun4i-Fix-H6-HDMI-PHY-configuration.patch deleted file mode 100644 index 1cc6c8285b..0000000000 --- a/projects/Allwinner/patches/linux/0053-drm-sun4i-Fix-H6-HDMI-PHY-configuration.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 3 Feb 2021 23:29:47 +0100 -Subject: [PATCH] drm/sun4i: Fix H6 HDMI PHY configuration - -cpce value for 594 MHz is set differently in BSP driver. Fix that. - -Fixes: c71c9b2fee17 ("drm/sun4i: Add support for Synopsys HDMI PHY") -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -@@ -89,7 +89,7 @@ static const struct dw_hdmi_mpll_config - }, - }, { - 594000000, { -- { 0x1a40, 0x0003 }, -+ { 0x1a7c, 0x0003 }, - { 0x3b4c, 0x0003 }, - { 0x5a64, 0x0003 }, - }, diff --git a/projects/Allwinner/patches/linux/0054-drm-sun4i-dw-hdmi-Fix-max.-frequency-for-H6.patch b/projects/Allwinner/patches/linux/0054-drm-sun4i-dw-hdmi-Fix-max.-frequency-for-H6.patch deleted file mode 100644 index fc4d41a8ba..0000000000 --- a/projects/Allwinner/patches/linux/0054-drm-sun4i-dw-hdmi-Fix-max.-frequency-for-H6.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Wed, 3 Feb 2021 23:32:16 +0100 -Subject: [PATCH] drm/sun4i: dw-hdmi: Fix max. frequency for H6 - -It turns out that reasoning for lowering max. supported frequency is -wrong. Scrambling works just fine. Several now fixed bugs prevented -proper functioning, even with rates lower than 340 MHz. Issues were just -more pronounced with higher frequencies. - -Fix that by allowing max. supported frequency in HW and fix the comment. - -Fixes: cd9063757a22 ("drm/sun4i: DW HDMI: Lower max. supported rate for H6") -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 6 ++---- - 1 file changed, 2 insertions(+), 4 deletions(-) - ---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c -@@ -47,11 +47,9 @@ sun8i_dw_hdmi_mode_valid_h6(struct dw_hd - { - /* - * Controller support maximum of 594 MHz, which correlates to -- * 4K@60Hz 4:4:4 or RGB. However, for frequencies greater than -- * 340 MHz scrambling has to be enabled. Because scrambling is -- * not yet implemented, just limit to 340 MHz for now. -+ * 4K@60Hz 4:4:4 or RGB. - */ -- if (mode->clock > 340000) -+ if (mode->clock > 594000) - return MODE_CLOCK_HIGH; - - return MODE_OK;