From 2475fc61115ec62423f9e3fffe44ff94cf6325a2 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Fri, 15 Nov 2024 00:00:37 +0100 Subject: [PATCH 1/9] linux (RPi): update to 6.12-rc7-2ac3d76 Signed-off-by: Matthias Reichl --- packages/linux/package.mk | 6 +-- ...ept-read-buffers-of-length-1-in-anys.patch | 49 ------------------- 2 files changed, 3 insertions(+), 52 deletions(-) delete mode 100644 packages/linux/patches/raspberrypi/linux-999.90-media-anysee-accept-read-buffers-of-length-1-in-anys.patch diff --git a/packages/linux/package.mk b/packages/linux/package.mk index b2aeee9f23..79238c3691 100644 --- a/packages/linux/package.mk +++ b/packages/linux/package.mk @@ -23,11 +23,11 @@ case "${LINUX}" in PKG_PATCH_DIRS="default rtlwifi/after-6.12" ;; raspberrypi) - PKG_VERSION="66aef6ce3557edd9d58d794e4a800c5be49ca0e7" # 6.6.60 - PKG_SHA256="6e9843b8954faa1e5195aaf3a76a43fcc2ddb6cd152f628605d0e2ce61f551ea" + PKG_VERSION="2ac3d763e26c01e287b77353e2158594e0910778" # 6.12-rc7 + PKG_SHA256="8f17e885c7649639f8e6e35c0e436f22029af02d875f594b453a3d832ff1619c" PKG_URL="https://github.com/raspberrypi/linux/archive/${PKG_VERSION}.tar.gz" PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz" - PKG_PATCH_DIRS="raspberrypi rtlwifi/6.9 rtlwifi/6.10 rtlwifi/6.11 rtlwifi/6.11.2 rtlwifi/6.12 rtlwifi/after-6.12" + PKG_PATCH_DIRS="raspberrypi rtlwifi/after-6.12" ;; *) PKG_VERSION="6.12" diff --git a/packages/linux/patches/raspberrypi/linux-999.90-media-anysee-accept-read-buffers-of-length-1-in-anys.patch b/packages/linux/patches/raspberrypi/linux-999.90-media-anysee-accept-read-buffers-of-length-1-in-anys.patch deleted file mode 100644 index 3115837283..0000000000 --- a/packages/linux/patches/raspberrypi/linux-999.90-media-anysee-accept-read-buffers-of-length-1-in-anys.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 826beca0ce76876507372349da860a986078eacd Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Istv=C3=A1n=20V=C3=A1radi?= -Date: Tue, 13 Feb 2024 21:20:32 +0100 -Subject: [PATCH] media: anysee: accept read buffers of length 1 in - anysee_master_xfer -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -anysee_master_xfer currently accepts read messages of length 2 only. -However, several frontends, e.g. tda10023 send buffers of length 1, -containing an 8-bit register number (see tda10023_readreg). -These buffers are rejected currently, making many Anysee variants -to not work. In these cases the "Unsupported Anysee version" -message is logged. - -This patch alters the function to accept buffers of a length of 1 too. - -Signed-off-by: István Váradi -Signed-off-by: Hans Verkuil -[hverkuil: add spaces around '<', fix typo in 'sevaral'] ---- - drivers/media/usb/dvb-usb-v2/anysee.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/media/usb/dvb-usb-v2/anysee.c b/drivers/media/usb/dvb-usb-v2/anysee.c -index a1235d0cce92..8699846eb416 100644 ---- a/drivers/media/usb/dvb-usb-v2/anysee.c -+++ b/drivers/media/usb/dvb-usb-v2/anysee.c -@@ -202,14 +202,14 @@ static int anysee_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, - - while (i < num) { - if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) { -- if (msg[i].len != 2 || msg[i + 1].len > 60) { -+ if (msg[i].len < 1 || msg[i].len > 2 || msg[i + 1].len > 60) { - ret = -EOPNOTSUPP; - break; - } - buf[0] = CMD_I2C_READ; - buf[1] = (msg[i].addr << 1) | 0x01; - buf[2] = msg[i].buf[0]; -- buf[3] = msg[i].buf[1]; -+ buf[3] = (msg[i].len < 2) ? 0 : msg[i].buf[1]; - buf[4] = msg[i].len-1; - buf[5] = msg[i+1].len; - ret = anysee_ctrl_msg(d, buf, 6, msg[i+1].buf, --- -2.34.1 - From ad6183fa0bc0397c807ad88a9337f773ce615e80 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Fri, 15 Nov 2024 00:00:37 +0100 Subject: [PATCH 2/9] linux (RPi): config options for 6.12-rc7-2ac3d76 Signed-off-by: Matthias Reichl --- projects/RPi/devices/RPi/linux/linux.arm.conf | 323 +++++++++++---- .../RPi/devices/RPi2/linux/linux.arm.conf | 338 ++++++++++----- .../RPi/devices/RPi4/linux/linux.aarch64.conf | 392 +++++++++++++----- .../RPi/devices/RPi5/linux/linux.aarch64.conf | 387 ++++++++++++----- 4 files changed, 1039 insertions(+), 401 deletions(-) diff --git a/projects/RPi/devices/RPi/linux/linux.arm.conf b/projects/RPi/devices/RPi/linux/linux.arm.conf index 55e5d2885f..1b264e2b48 100644 --- a/projects/RPi/devices/RPi/linux/linux.arm.conf +++ b/projects/RPi/devices/RPi/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 6.6.59 Kernel Configuration +# Linux/arm 6.12.0-rc7 Kernel Configuration # CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GCC) 13.0.0 20220604 (experimental) [master revision aec868578d8515763d75693c1fdfbc30ff0a1e68]" CONFIG_CC_IS_GCC=y @@ -11,11 +11,11 @@ CONFIG_AS_VERSION=23850 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23850 CONFIG_LLD_VERSION=0 +CONFIG_RUSTC_VERSION=0 +CONFIG_RUSTC_LLVM_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y -CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y -CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y +CONFIG_GCC_ASM_GOTO_OUTPUT_BROKEN=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=0 @@ -118,6 +118,7 @@ CONFIG_TINY_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_TINY_SRCU=y CONFIG_TASKS_RCU_GENERIC=y +CONFIG_NEED_TASKS_RCU=y CONFIG_TASKS_RUDE_RCU=y CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_NEED_SEGCBLIST=y @@ -138,11 +139,14 @@ CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_GCC10_NO_ARRAY_BOUNDS=y CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_GCC_NO_STRINGOP_OVERFLOW=y +CONFIG_CC_NO_STRINGOP_OVERFLOW=y +CONFIG_SLAB_OBJ_EXT=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y # CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y -CONFIG_MEMCG_KMEM=y +# CONFIG_MEMCG_V1 is not set CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y CONFIG_CGROUP_SCHED=y @@ -185,6 +189,8 @@ CONFIG_BOOT_CONFIG=y CONFIG_INITRAMFS_PRESERVE_MTIME=y CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +# CONFIG_LD_DEAD_CODE_DATA_ELIMINATION is not set CONFIG_LD_ORPHAN_WARN=y CONFIG_LD_ORPHAN_WARN_LEVEL="warn" CONFIG_SYSCTL=y @@ -199,7 +205,7 @@ CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y +# CONFIG_BASE_SMALL is not set CONFIG_FUTEX=y CONFIG_FUTEX_PI=y CONFIG_EPOLL=y @@ -211,18 +217,17 @@ CONFIG_AIO=y CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y +CONFIG_KCMP=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +CONFIG_CACHESTAT_SYSCALL=y +# CONFIG_PC104 is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_SELFTEST is not set # CONFIG_KALLSYMS_ALL is not set -CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -CONFIG_KCMP=y -CONFIG_RSEQ=y -CONFIG_CACHESTAT_SYSCALL=y -# CONFIG_DEBUG_RSEQ is not set CONFIG_HAVE_PERF_EVENTS=y CONFIG_PERF_USE_VMALLOC=y -# CONFIG_PC104 is not set # # Kernel Performance Events And Counters @@ -239,7 +244,6 @@ CONFIG_TRACEPOINTS=y # Kexec and crash features # # CONFIG_KEXEC is not set -# CONFIG_CRASH_DUMP is not set # end of Kexec and crash features # end of General setup @@ -375,7 +379,8 @@ CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y # CONFIG_HIGHMEM is not set -# CONFIG_CPU_SW_DOMAIN_PAN is not set +CONFIG_ARM_PAN=y +CONFIG_CPU_SW_DOMAIN_PAN=y CONFIG_HW_PERF_EVENTS=y CONFIG_ARM_MODULE_PLTS=y CONFIG_ARCH_FORCE_MAX_ORDER=11 @@ -479,6 +484,7 @@ CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_AS_VFP_VMRS_FPINST=y CONFIG_CPU_MITIGATIONS=y +CONFIG_ARCH_HAS_DMA_OPS=y # # General architecture-dependent options @@ -521,10 +527,12 @@ CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y # CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_LTO_NONE=y +CONFIG_ARCH_SUPPORTS_CFI_CLANG=y CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y @@ -537,8 +545,11 @@ CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 +CONFIG_HAVE_PAGE_SIZE_4KB=y +CONFIG_PAGE_SIZE_4KB=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SHIFT=12 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y @@ -569,7 +580,6 @@ CONFIG_FUNCTION_ALIGNMENT=0 # end of General architecture-dependent options CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_DEBUG is not set # CONFIG_MODULE_FORCE_LOAD is not set @@ -579,10 +589,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set -CONFIG_MODULE_COMPRESS_NONE=y -# CONFIG_MODULE_COMPRESS_GZIP is not set -# CONFIG_MODULE_COMPRESS_XZ is not set -# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_COMPRESS is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set @@ -594,6 +601,7 @@ CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_ICQ=y CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_DEV_INTEGRITY is not set +CONFIG_BLK_DEV_WRITE_MOUNTED=y # CONFIG_BLK_DEV_ZONED is not set # CONFIG_BLK_DEV_THROTTLING is not set # CONFIG_BLK_WBT is not set @@ -673,17 +681,17 @@ CONFIG_SWAP=y # CONFIG_ZSWAP is not set # -# SLAB allocator options +# Slab allocator options # -# CONFIG_SLAB_DEPRECATED is not set CONFIG_SLUB=y # CONFIG_SLUB_TINY is not set CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_FREELIST_HARDENED is not set +CONFIG_SLAB_BUCKETS=y # CONFIG_SLUB_STATS is not set # CONFIG_RANDOM_KMALLOC_CACHES is not set -# end of SLAB allocator options +# end of Slab allocator options # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set # CONFIG_COMPAT_BRK is not set @@ -693,7 +701,6 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y -CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_COMPACTION=y CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 # CONFIG_PAGE_REPORTING is not set @@ -705,12 +712,12 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_NEED_PER_CPU_KM=y CONFIG_CMA=y -# CONFIG_CMA_DEBUG is not set CONFIG_CMA_DEBUGFS=y # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CPU_CACHE_ALIASING=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y CONFIG_VM_EVENT_COUNTERS=y # CONFIG_PERCPU_STATS is not set @@ -722,7 +729,9 @@ CONFIG_MEMFD_CREATE=y CONFIG_LRU_GEN=y # CONFIG_LRU_GEN_ENABLED is not set # CONFIG_LRU_GEN_STATS is not set +CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y CONFIG_LOCK_MM_AND_FIND_VMA=y +CONFIG_EXECMEM=y # # Data Access Monitoring @@ -736,6 +745,7 @@ CONFIG_NET_INGRESS=y CONFIG_NET_EGRESS=y CONFIG_NET_XGRESS=y CONFIG_SKB_EXTENSIONS=y +CONFIG_NET_DEVMEM=y # # Networking options @@ -743,7 +753,6 @@ CONFIG_SKB_EXTENSIONS=y CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y -CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set @@ -962,6 +971,7 @@ CONFIG_NETFILTER_XT_MATCH_STATE=m # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=m +CONFIG_IP_NF_IPTABLES_LEGACY=m # CONFIG_NF_SOCKET_IPV4 is not set # CONFIG_NF_TPROXY_IPV4 is not set # CONFIG_NF_DUP_IPV4 is not set @@ -984,12 +994,13 @@ CONFIG_IP_NF_MANGLE=m # CONFIG_IP_NF_TARGET_ECN is not set # CONFIG_IP_NF_TARGET_TTL is not set # CONFIG_IP_NF_RAW is not set -# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_ARPFILTER is not set # end of IP: Netfilter Configuration # # IPv6: Netfilter Configuration # +CONFIG_IP6_NF_IPTABLES_LEGACY=m # CONFIG_NF_SOCKET_IPV6 is not set # CONFIG_NF_TPROXY_IPV6 is not set # CONFIG_NF_DUP_IPV6 is not set @@ -1020,7 +1031,6 @@ CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_NF_DEFRAG_IPV6=m # CONFIG_NF_CONNTRACK_BRIDGE is not set # CONFIG_BRIDGE_NF_EBTABLES is not set -# CONFIG_BPFILTER is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set # CONFIG_RDS is not set @@ -1166,6 +1176,7 @@ CONFIG_BT_HCIUART_BCM=y # CONFIG_BT_HCIUART_QCA is not set # CONFIG_BT_HCIUART_AG6XX is not set # CONFIG_BT_HCIUART_MRVL is not set +# CONFIG_BT_HCIUART_AML is not set CONFIG_BT_HCIBCM203X=m # CONFIG_BT_HCIBPA10X is not set CONFIG_BT_HCIBFUSB=m @@ -1203,7 +1214,6 @@ CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" # CONFIG_MAC80211_MESH is not set CONFIG_MAC80211_LEDS=y -# CONFIG_MAC80211_DEBUGFS is not set # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 @@ -1232,6 +1242,7 @@ CONFIG_ETHTOOL_NETLINK=y # CONFIG_ARM_AMBA=y CONFIG_HAVE_PCI=y +CONFIG_GENERIC_PCI_IOMAP=y # CONFIG_PCI is not set # CONFIG_PCCARD is not set @@ -1262,6 +1273,7 @@ CONFIG_WANT_DEV_COREDUMP=y # CONFIG_DEBUG_DEVRES is not set # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_DEVICES=y CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=y @@ -1276,7 +1288,6 @@ CONFIG_DMA_SHARED_BUFFER=y # # Bus devices # -# CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_MOXTET is not set # CONFIG_VEXPRESS_CONFIG is not set # CONFIG_MHI_BUS is not set @@ -1307,6 +1318,11 @@ CONFIG_RASPBERRYPI_FIRMWARE=y CONFIG_FW_CS_DSP=m # CONFIG_GOOGLE_FIRMWARE is not set +# +# Qualcomm firmware drivers +# +# end of Qualcomm firmware drivers + # # Tegra firmware driver # @@ -1334,6 +1350,7 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_NULL_BLK is not set CONFIG_CDROM=y # CONFIG_ZRAM is not set +CONFIG_ZRAM_DEF_COMP="unset-value" CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 # CONFIG_BLK_DEV_DRBD is not set @@ -1360,6 +1377,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 CONFIG_BCM2835_SMI=m # CONFIG_AD525X_DPOT is not set # CONFIG_DUMMY_IRQ is not set +# CONFIG_RPMB is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_APDS9802ALS is not set @@ -1383,7 +1401,6 @@ CONFIG_MISC_RTSX=y # # CONFIG_EEPROM_AT24 is not set # CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set # CONFIG_EEPROM_MAX6875 is not set CONFIG_EEPROM_93CX6=m # CONFIG_EEPROM_93XX46 is not set @@ -1465,6 +1482,7 @@ CONFIG_MACVLAN=m # CONFIG_GENEVE is not set # CONFIG_BAREUDP is not set # CONFIG_GTP is not set +# CONFIG_PFCP is not set # CONFIG_AMT is not set # CONFIG_MACSEC is not set CONFIG_NETCONSOLE=y @@ -1476,6 +1494,7 @@ CONFIG_TUN=y # CONFIG_TUN_VNET_CROSS_LE is not set CONFIG_VETH=m CONFIG_NLMON=m +# CONFIG_NETKIT is not set # CONFIG_ETHERNET is not set CONFIG_PHYLINK=m CONFIG_PHYLIB=y @@ -1488,6 +1507,7 @@ CONFIG_FIXED_PHY=y # # MII PHY device drivers # +# CONFIG_AIR_EN8811H_PHY is not set # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set # CONFIG_ADIN1100_PHY is not set @@ -1523,6 +1543,9 @@ CONFIG_MICROCHIP_PHY=y # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_NCN26000_PHY is not set # CONFIG_AT803X_PHY is not set +# CONFIG_QCA83XX_PHY is not set +# CONFIG_QCA808X_PHY is not set +# CONFIG_QCA807X_PHY is not set # CONFIG_QSEMI_PHY is not set # CONFIG_REALTEK_PHY is not set # CONFIG_RENESAS_PHY is not set @@ -1536,6 +1559,7 @@ CONFIG_SMSC_PHY=y # CONFIG_DP83867_PHY is not set # CONFIG_DP83869_PHY is not set # CONFIG_DP83TD510_PHY is not set +# CONFIG_DP83TG720_PHY is not set # CONFIG_VITESSE_PHY is not set # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set @@ -1562,6 +1586,7 @@ CONFIG_MDIO_DEVRES=y # # PCS device drivers # +# CONFIG_PCS_XPCS is not set # end of PCS device drivers CONFIG_PPP=m @@ -1628,7 +1653,6 @@ CONFIG_ATH9K_COMMON=m CONFIG_ATH9K_BTCOEX_SUPPORT=y CONFIG_ATH9K=m CONFIG_ATH9K_AHB=y -# CONFIG_ATH9K_DEBUGFS is not set # CONFIG_ATH9K_DYNACK is not set # CONFIG_ATH9K_WOW is not set CONFIG_ATH9K_RFKILL=y @@ -1650,6 +1674,7 @@ CONFIG_AR5523=m # CONFIG_ATH10K is not set CONFIG_WCN36XX=m # CONFIG_WCN36XX_DEBUGFS is not set +# CONFIG_ATH11K is not set CONFIG_WLAN_VENDOR_ATMEL=y # CONFIG_AT76C50X_USB is not set CONFIG_WLAN_VENDOR_BROADCOM=y @@ -1678,10 +1703,8 @@ CONFIG_BRCMFMAC_SDIO=y CONFIG_BRCMFMAC_USB=y # CONFIG_BRCM_TRACING is not set # CONFIG_BRCMDBG is not set -CONFIG_WLAN_VENDOR_CISCO=y CONFIG_WLAN_VENDOR_INTEL=y CONFIG_WLAN_VENDOR_INTERSIL=y -# CONFIG_HOSTAP is not set CONFIG_P54_COMMON=m CONFIG_P54_USB=m # CONFIG_P54_SPI is not set @@ -1711,6 +1734,7 @@ CONFIG_MT7663U=m CONFIG_MT7921_COMMON=m # CONFIG_MT7921S is not set CONFIG_MT7921U=m +# CONFIG_MT7925U is not set CONFIG_WLAN_VENDOR_MICROCHIP=y # CONFIG_WILC1000_SDIO is not set # CONFIG_WILC1000_SPI is not set @@ -1762,6 +1786,7 @@ CONFIG_RTW88_8822BU=m # CONFIG_RTW88_8822CS is not set CONFIG_RTW88_8822CU=m # CONFIG_RTW88_8723DS is not set +# CONFIG_RTW88_8723CS is not set CONFIG_RTW88_8723DU=m # CONFIG_RTW88_8821CS is not set CONFIG_RTW88_8821CU=m @@ -1782,11 +1807,9 @@ CONFIG_WLAN_VENDOR_TI=y # CONFIG_WL18XX is not set # CONFIG_WLCORE is not set CONFIG_WLAN_VENDOR_ZYDAS=y -CONFIG_USB_ZD1201=m CONFIG_ZD1211RW=m # CONFIG_ZD1211RW_DEBUG is not set # CONFIG_WLAN_VENDOR_QUANTENNA is not set -CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_MAC80211_HWSIM is not set # CONFIG_VIRT_WIFI is not set # CONFIG_WAN is not set @@ -1841,7 +1864,6 @@ CONFIG_KEYBOARD_GPIO=m # CONFIG_KEYBOARD_LM8323 is not set # CONFIG_KEYBOARD_LM8333 is not set # CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_MCS is not set # CONFIG_KEYBOARD_MPR121 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set @@ -1887,6 +1909,7 @@ CONFIG_JOYSTICK_PSXPAD_SPI_FF=y # CONFIG_JOYSTICK_QWIIC is not set # CONFIG_JOYSTICK_FSIA6B is not set # CONFIG_JOYSTICK_SENSEHAT is not set +# CONFIG_JOYSTICK_SEESAW is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=m @@ -1901,7 +1924,6 @@ CONFIG_TOUCHSCREEN_ADS7846=m # CONFIG_TOUCHSCREEN_CY8CTMA140 is not set # CONFIG_TOUCHSCREEN_CY8CTMG110 is not set # CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set -# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set # CONFIG_TOUCHSCREEN_CYTTSP5 is not set # CONFIG_TOUCHSCREEN_DYNAPRO is not set # CONFIG_TOUCHSCREEN_HAMPSHIRE is not set @@ -1911,6 +1933,8 @@ CONFIG_TOUCHSCREEN_EGALAX=m # CONFIG_TOUCHSCREEN_EXC3000 is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI is not set # CONFIG_TOUCHSCREEN_HIDEEP is not set # CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set # CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set @@ -1924,7 +1948,6 @@ CONFIG_TOUCHSCREEN_EGALAX=m # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set # CONFIG_TOUCHSCREEN_WACOM_I2C is not set # CONFIG_TOUCHSCREEN_MAX11801 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set # CONFIG_TOUCHSCREEN_MMS114 is not set # CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set # CONFIG_TOUCHSCREEN_MSG2638 is not set @@ -2055,7 +2078,6 @@ CONFIG_TTY=y CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set @@ -2141,7 +2163,6 @@ CONFIG_RASPBERRYPI_GPIOMEM=y # CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y -# CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y @@ -2175,7 +2196,7 @@ CONFIG_I2C_BCM2708_BAUDRATE=100000 CONFIG_I2C_BCM2835=y # CONFIG_I2C_BRCMSTB is not set # CONFIG_I2C_CBUS_GPIO is not set -# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_CORE is not set # CONFIG_I2C_EMEV2 is not set CONFIG_I2C_GPIO=y # CONFIG_I2C_GPIO_FAULT_INJECTOR is not set @@ -2225,6 +2246,7 @@ CONFIG_SPI_BCM2835AUX=m # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_DESIGNWARE is not set # CONFIG_SPI_GPIO is not set # CONFIG_SPI_FSL_SPI is not set @@ -2273,6 +2295,7 @@ CONFIG_PINMUX=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_AW9523 is not set # CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_MCP23S08 is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set @@ -2370,15 +2393,23 @@ CONFIG_GPIO_FSM=m # CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers +# +# GPIO Debugging utilities +# +# CONFIG_GPIO_VIRTUSER is not set +# end of GPIO Debugging utilities + CONFIG_W1=m # # 1-wire Bus Masters # +# CONFIG_W1_MASTER_AMD_AXI is not set # CONFIG_W1_MASTER_DS2490 is not set # CONFIG_W1_MASTER_DS2482 is not set CONFIG_W1_MASTER_GPIO=m # CONFIG_W1_MASTER_SGI is not set +# CONFIG_W1_MASTER_UART is not set # end of 1-wire Bus Masters # @@ -2413,6 +2444,7 @@ CONFIG_POWER_RESET_RESTART=y # CONFIG_POWER_RESET_SYSCON is not set # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_NVMEM_REBOOT_MODE is not set +# CONFIG_POWER_SEQUENCING is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y @@ -2430,8 +2462,8 @@ CONFIG_RPI_POE_POWER=m # CONFIG_CHARGER_SBS is not set # CONFIG_MANAGER_SBS is not set # CONFIG_BATTERY_BQ27XXX is not set -# CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_MAX1721X is not set # CONFIG_CHARGER_ISP1704 is not set # CONFIG_CHARGER_MAX8903 is not set @@ -2460,6 +2492,7 @@ CONFIG_RPI_POE_POWER=m # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set # CONFIG_BATTERY_UG3105 is not set +# CONFIG_FUEL_GAUGE_MM8013 is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set @@ -2469,7 +2502,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AD7314 is not set # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set @@ -2486,8 +2518,10 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CHIPCAP2 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set # CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DS620 is not set @@ -2496,6 +2530,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_F75375S is not set # CONFIG_SENSORS_FTSTEUTATES is not set +# CONFIG_SENSORS_GIGABYTE_WATERFORCE is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_G760A is not set @@ -2505,12 +2540,14 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_HS3001 is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWERZ is not set # CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LINEAGE is not set # CONFIG_SENSORS_LTC2945 is not set # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2991 is not set # CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set @@ -2518,6 +2555,7 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LTC4282 is not set # CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set @@ -2531,7 +2569,6 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_MAX6620 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_MAX6697 is not set # CONFIG_SENSORS_MAX31790 is not set @@ -2565,10 +2602,12 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_KRAKEN3 is not set # CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set +# CONFIG_SENSORS_PT5161L is not set CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_RASPBERRYPI_HWMON=y # CONFIG_SENSORS_SBTSI is not set @@ -2597,6 +2636,7 @@ CONFIG_SENSORS_RASPBERRYPI_HWMON=y # CONFIG_SENSORS_INA2XX is not set # CONFIG_SENSORS_INA238 is not set # CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP102 is not set @@ -2620,10 +2660,11 @@ CONFIG_SENSORS_RASPBERRYPI_HWMON=y CONFIG_THERMAL=y # CONFIG_THERMAL_NETLINK is not set # CONFIG_THERMAL_STATISTICS is not set +# CONFIG_THERMAL_DEBUGFS is not set +# CONFIG_THERMAL_CORE_TESTING is not set CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y -# CONFIG_THERMAL_WRITABLE_TRIPS is not set CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set @@ -2691,6 +2732,7 @@ CONFIG_BCMA_DRIVER_GMAC_CMN=y # Multifunction device drivers # CONFIG_MFD_CORE=y +# CONFIG_MFD_ADP5585 is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_AS3711 is not set # CONFIG_MFD_SMPRO is not set @@ -2723,6 +2765,7 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_MAX14577 is not set # CONFIG_MFD_MAX77541 is not set # CONFIG_MFD_MAX77620 is not set @@ -2806,10 +2849,13 @@ CONFIG_MFD_WM5102=y # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set # CONFIG_MFD_ATC260X_I2C is not set # CONFIG_MFD_QCOM_PM8008 is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC_SPI is not set # CONFIG_MFD_RSMU_I2C is not set @@ -2821,6 +2867,7 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_NETLINK_EVENTS is not set # CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set @@ -2842,6 +2889,7 @@ CONFIG_REGULATOR_ARIZONA_MICSUPP=m # CONFIG_REGULATOR_LTC3589 is not set # CONFIG_REGULATOR_LTC3676 is not set # CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX77503 is not set # CONFIG_REGULATOR_MAX77857 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set @@ -3123,6 +3171,7 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # # Atmel media platform drivers # +# CONFIG_VIDEO_BCM2835_UNICAM_LEGACY is not set # CONFIG_VIDEO_BCM2835_UNICAM is not set # @@ -3151,6 +3200,10 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # Microchip Technology, Inc. media platform drivers # +# +# Nuvoton media platform drivers +# + # # NVidia media platform drivers # @@ -3241,7 +3294,12 @@ CONFIG_MEDIA_ATTACH=y # CONFIG_VIDEO_IR_I2C=m CONFIG_VIDEO_CAMERA_SENSOR=y +# CONFIG_VIDEO_ALVIUM_CSI2 is not set # CONFIG_VIDEO_AR0521 is not set +# CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set +# CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_ARDUCAM_64MP is not set # CONFIG_VIDEO_ARDUCAM_PIVARIETY is not set # CONFIG_VIDEO_HI556 is not set @@ -3252,6 +3310,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -3266,6 +3325,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_IMX708 is not set # CONFIG_VIDEO_MT9M001 is not set # CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9M114 is not set # CONFIG_VIDEO_MT9P031 is not set # CONFIG_VIDEO_MT9T112 is not set # CONFIG_VIDEO_MT9V011 is not set @@ -3311,10 +3371,16 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_S5C73M3 is not set # CONFIG_VIDEO_S5K5BAF is not set # CONFIG_VIDEO_S5K6A3 is not set -# CONFIG_VIDEO_ST_VGXY61 is not set +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set +# +# Camera ISPs +# +# CONFIG_VIDEO_THP7312 is not set +# end of Camera ISPs + # # Lens drivers # @@ -3386,6 +3452,7 @@ CONFIG_VIDEO_SAA711X=m # CONFIG_VIDEO_TVP5150 is not set # CONFIG_VIDEO_TVP7002 is not set # CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9900 is not set # CONFIG_VIDEO_TW9903 is not set # CONFIG_VIDEO_TW9906 is not set # CONFIG_VIDEO_TW9910 is not set @@ -3447,6 +3514,8 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_DS90UB913 is not set # CONFIG_VIDEO_DS90UB953 is not set # CONFIG_VIDEO_DS90UB960 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # end of Video serializers and deserializers # @@ -3674,13 +3743,13 @@ CONFIG_DVB_SP2=m # # Graphics support # -CONFIG_VIDEO_CMDLINE=y -CONFIG_VIDEO_NOMODESET=y +CONFIG_VIDEO=y # CONFIG_AUXDISPLAY is not set CONFIG_DRM=y CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DEBUG_MM is not set CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_PANIC is not set # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set # CONFIG_DRM_DEBUG_MODESET_LOCK is not set CONFIG_DRM_FBDEV_EMULATION=y @@ -3688,9 +3757,10 @@ CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set CONFIG_DRM_LOAD_EDID_FIRMWARE=y CONFIG_DRM_DISPLAY_HELPER=y +# CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set +# CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set CONFIG_DRM_DISPLAY_HDMI_HELPER=y -# CONFIG_DRM_DP_AUX_CHARDEV is not set -# CONFIG_DRM_DP_CEC is not set +CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER=y CONFIG_DRM_GEM_DMA_HELPER=y # @@ -3726,33 +3796,40 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_AUO_A030JTN01 is not set # CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set # CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set # CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set -# CONFIG_DRM_PANEL_DSI_CM is not set -# CONFIG_DRM_PANEL_LVDS is not set -CONFIG_DRM_PANEL_SIMPLE=y -# CONFIG_DRM_PANEL_EDP is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 is not set # CONFIG_DRM_PANEL_EBBG_FT8719 is not set # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_DSI_CM is not set +# CONFIG_DRM_PANEL_LVDS is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set +# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set # CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set +# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set # CONFIG_DRM_PANEL_JDI_R63452 is not set # CONFIG_DRM_PANEL_KHADAS_TS050 is not set # CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set -# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_LG_SW43408 is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set # CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set @@ -3761,8 +3838,8 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set # CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set # CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set -# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set # CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set # CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set @@ -3771,16 +3848,20 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set # CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set # CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set # CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set # CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set @@ -3795,15 +3876,18 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set # CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set # CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set +# CONFIG_DRM_PANEL_EDP is not set +CONFIG_DRM_PANEL_SIMPLE=y +# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set # CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set # CONFIG_DRM_PANEL_TPO_Y17P is not set # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set # CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set -# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN is not set # CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set # CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set @@ -3876,11 +3960,12 @@ CONFIG_DRM_VC4_HDMI_CEC=y # CONFIG_DRM_TVE200 is not set # CONFIG_DRM_LIMA is not set # CONFIG_DRM_PANFROST is not set +# CONFIG_DRM_PANTHOR is not set # CONFIG_DRM_MCDE is not set # CONFIG_DRM_TIDSS is not set # CONFIG_DRM_GUD is not set # CONFIG_DRM_SSD130X is not set -# CONFIG_DRM_LEGACY is not set +# CONFIG_DRM_WERROR is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y # @@ -3888,7 +3973,6 @@ CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y # CONFIG_FB=y CONFIG_FB_BCM2708=y -# CONFIG_FB_ARMCLCD is not set # CONFIG_FB_OPENCORES is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_SMSCUFX is not set @@ -3910,10 +3994,9 @@ CONFIG_FB_SYS_FILLRECT=y CONFIG_FB_SYS_COPYAREA=y CONFIG_FB_SYS_IMAGEBLIT=y # CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_SYS_FOPS=y +CONFIG_FB_SYSMEM_FOPS=y CONFIG_FB_DEFERRED_IO=y CONFIG_FB_DMAMEM_HELPERS=y -CONFIG_FB_IOMEM_FOPS=y CONFIG_FB_SYSMEM_HELPERS=y CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y # CONFIG_FB_MODE_HELPERS is not set @@ -3938,15 +4021,18 @@ CONFIG_LCD_CLASS_DEVICE=y # CONFIG_LCD_OTM3225A is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set # CONFIG_BACKLIGHT_PWM is not set CONFIG_BACKLIGHT_RPI=y # CONFIG_BACKLIGHT_QCOM_WLED is not set # CONFIG_BACKLIGHT_ADP8860 is not set # CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set # CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_BACKLIGHT_MP3309C is not set CONFIG_BACKLIGHT_GPIO=y # CONFIG_BACKLIGHT_LV5207LP is not set # CONFIG_BACKLIGHT_BD6107 is not set @@ -3961,6 +4047,8 @@ CONFIG_HDMI=y # Console display driver support # CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=30 CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y @@ -3992,10 +4080,10 @@ CONFIG_SND_MAX_CARDS=32 # CONFIG_SND_SUPPORT_OLD_API is not set CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set # CONFIG_SND_CTL_INPUT_VALIDATION is not set +# CONFIG_SND_UTIMER is not set CONFIG_SND_VMASTER=y # CONFIG_SND_SEQUENCER is not set # CONFIG_SND_DRIVERS is not set @@ -4136,6 +4224,7 @@ CONFIG_SND_SOC_ADAU7002=m # CONFIG_SND_SOC_AK4458 is not set CONFIG_SND_SOC_AK4554=m # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -4143,6 +4232,8 @@ CONFIG_SND_SOC_AK4554=m # CONFIG_SND_SOC_AW8738 is not set # CONFIG_SND_SOC_AW88395 is not set # CONFIG_SND_SOC_AW88261 is not set +# CONFIG_SND_SOC_AW87390 is not set +# CONFIG_SND_SOC_AW88399 is not set # CONFIG_SND_SOC_BD28623 is not set # CONFIG_SND_SOC_BT_SCO is not set # CONFIG_SND_SOC_CHV3_CODEC is not set @@ -4175,12 +4266,14 @@ CONFIG_SND_SOC_CS42XX8_I2C=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set # CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CX2072X is not set CONFIG_SND_SOC_DA7213=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8326 is not set # CONFIG_SND_SOC_ES8328_I2C is not set @@ -4189,7 +4282,6 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_HDA is not set # CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_IDT821034 is not set -# CONFIG_SND_SOC_INNO_RK3036 is not set CONFIG_SND_SOC_MA120X0P=m # CONFIG_SND_SOC_MAX98088 is not set # CONFIG_SND_SOC_MAX98090 is not set @@ -4220,14 +4312,15 @@ CONFIG_SND_SOC_PCM5102A=m CONFIG_SND_SOC_PCM512x=m CONFIG_SND_SOC_PCM512x_I2C=m # CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_PCM6240 is not set # CONFIG_SND_SOC_PEB2466 is not set -# CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RT5616 is not set CONFIG_SND_SOC_PCM1794A=m # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5640 is not set # CONFIG_SND_SOC_RT5659 is not set # CONFIG_SND_SOC_RT9120 is not set +# CONFIG_SND_SOC_RTQ9128 is not set CONFIG_SND_SOC_SGTL5000=m CONFIG_SND_SOC_SIGMADSP=m CONFIG_SND_SOC_SIGMADSP_I2C=m @@ -4307,6 +4400,7 @@ CONFIG_SND_SOC_WM8960=m # CONFIG_SND_SOC_ZL38060 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6357 is not set # CONFIG_SND_SOC_MT6358 is not set # CONFIG_SND_SOC_MT6660 is not set # CONFIG_SND_SOC_NAU8315 is not set @@ -4371,6 +4465,7 @@ CONFIG_HID_EZKEY=y # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set # CONFIG_HID_HOLTEK is not set +# CONFIG_HID_GOODIX_SPI is not set # CONFIG_HID_GOOGLE_STADIA_FF is not set # CONFIG_HID_VIVALDI is not set # CONFIG_HID_GT683R is not set @@ -4412,7 +4507,6 @@ CONFIG_NINTENDO_FF=y # CONFIG_HID_NTRIG is not set # CONFIG_HID_NVIDIA_SHIELD is not set CONFIG_HID_ORTEK=y -CONFIG_HID_OUYA=y CONFIG_HID_PANTHERLORD=y CONFIG_PANTHERLORD_FF=y CONFIG_HID_PENMOUNT=y @@ -4450,6 +4544,7 @@ CONFIG_HID_TOPSEED=y # CONFIG_HID_U2FZERO is not set # CONFIG_HID_WACOM is not set CONFIG_HID_WIIMOTE=m +# CONFIG_HID_WINWING is not set CONFIG_HID_XINMO=y # CONFIG_HID_ZEROPLUS is not set CONFIG_HID_ZYDACRON=y @@ -4497,6 +4592,7 @@ CONFIG_USB_DEFAULT_PERSIST=y # CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 CONFIG_USB_MON=m # @@ -4648,7 +4744,7 @@ CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set -# CONFIG_USB_ONBOARD_HUB is not set +# CONFIG_USB_ONBOARD_DEV is not set # # USB Physical Layer drivers @@ -4700,6 +4796,7 @@ CONFIG_MMC_REALTEK_USB=m CONFIG_MMC_HSQ=y # CONFIG_MMC_BCM2835 is not set # CONFIG_MMC_MTK is not set +# CONFIG_MMC_SDHCI_BRCMSTB is not set # CONFIG_MMC_SDHCI_XENON is not set # CONFIG_SCSI_UFSHCD is not set # CONFIG_MEMSTICK is not set @@ -4764,11 +4861,14 @@ CONFIG_LEDS_GPIO=y # CONFIG_LEDS_RT4505 is not set # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set +# CONFIG_LEDS_SY7802 is not set # # RGB LED drivers # # CONFIG_LEDS_GROUP_MULTICOLOR is not set +# CONFIG_LEDS_KTD202X is not set +# CONFIG_LEDS_NCP5623 is not set # CONFIG_LEDS_PWM_MULTICOLOR is not set # @@ -4781,6 +4881,7 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CPU=y # CONFIG_LEDS_TRIGGER_ACTIVITY is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set CONFIG_LEDS_TRIGGER_DEFAULT_ON=y # @@ -4792,8 +4893,8 @@ CONFIG_LEDS_TRIGGER_INPUT=y # CONFIG_LEDS_TRIGGER_PANIC is not set # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set -# CONFIG_LEDS_TRIGGER_AUDIO is not set # CONFIG_LEDS_TRIGGER_TTY is not set +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set CONFIG_LEDS_TRIGGER_ACTPWR=y # @@ -4833,6 +4934,7 @@ CONFIG_RTC_DRV_DS1307=m # CONFIG_RTC_DRV_DS1672 is not set # CONFIG_RTC_DRV_HYM8563 is not set # CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_MAX31335 is not set # CONFIG_RTC_DRV_NCT3018Y is not set # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set @@ -4849,12 +4951,14 @@ CONFIG_RTC_DRV_PCF8563=m # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8111 is not set # CONFIG_RTC_DRV_RX8581 is not set # CONFIG_RTC_DRV_RX8025 is not set # CONFIG_RTC_DRV_EM3027 is not set # CONFIG_RTC_DRV_RV3028 is not set # CONFIG_RTC_DRV_RV3032 is not set # CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD2405AL is not set # CONFIG_RTC_DRV_SD3078 is not set # @@ -4938,6 +5042,7 @@ CONFIG_DMA_BCM2708=y # CONFIG_XILINX_DMA is not set # CONFIG_XILINX_XDMA is not set # CONFIG_XILINX_ZYNQMP_DPDMA is not set +# CONFIG_AMD_QDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_DW_DMAC is not set @@ -4981,7 +5086,6 @@ CONFIG_VHOST_MENU=y # CONFIG_GREYBUS is not set # CONFIG_COMEDI is not set CONFIG_STAGING=y -# CONFIG_PRISM2_USB is not set # CONFIG_RTLLIB is not set CONFIG_RTL8723BS=m CONFIG_R8712U=m @@ -4989,11 +5093,13 @@ CONFIG_VT6656=m CONFIG_STAGING_MEDIA=y # CONFIG_VIDEO_MAX96712 is not set # CONFIG_VIDEO_RPIVID is not set + +# +# StarFive media platform drivers +# # CONFIG_STAGING_MEDIA_DEPRECATED is not set -# CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set # CONFIG_FB_TFT is not set -# CONFIG_KS7010 is not set CONFIG_BCM_VIDEOCORE=y CONFIG_BCM2835_VCHIQ=y CONFIG_VCHIQ_CDEV=y @@ -5003,11 +5109,11 @@ CONFIG_BCM_VC_SM_CMA=y CONFIG_VIDEO_CODEC_BCM2835=m CONFIG_VIDEO_ISP_BCM2835=m CONFIG_BCM2835_VCHIQ_MMAL=y -# CONFIG_PI433 is not set # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y @@ -5095,9 +5201,6 @@ CONFIG_BCM2835_MBOX=y # # Broadcom SoC drivers # -CONFIG_BCM2835_POWER=y -CONFIG_RASPBERRYPI_POWER=y -# CONFIG_SOC_BRCMSTB is not set # end of Broadcom SoC drivers # @@ -5137,6 +5240,33 @@ CONFIG_RASPBERRYPI_POWER=y # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers +# +# PM Domains +# + +# +# Amlogic PM Domains +# +# end of Amlogic PM Domains + +# +# Broadcom PM Domains +# +CONFIG_BCM2835_POWER=y +CONFIG_RASPBERRYPI_POWER=y +# end of Broadcom PM Domains + +# +# i.MX PM Domains +# +# end of i.MX PM Domains + +# +# Qualcomm PM Domains +# +# end of Qualcomm PM Domains +# end of PM Domains + # CONFIG_PM_DEVFREQ is not set CONFIG_EXTCON=y @@ -5145,6 +5275,7 @@ CONFIG_EXTCON=y # # CONFIG_EXTCON_FSA9480 is not set # CONFIG_EXTCON_GPIO is not set +# CONFIG_EXTCON_LC824206XA is not set # CONFIG_EXTCON_MAX3355 is not set # CONFIG_EXTCON_PTN5150 is not set # CONFIG_EXTCON_RT8973A is not set @@ -5153,7 +5284,6 @@ CONFIG_EXTCON=y # CONFIG_MEMORY is not set # CONFIG_IIO is not set CONFIG_PWM=y -CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL_TCB is not set CONFIG_PWM_BCM2835=m @@ -5171,12 +5301,14 @@ CONFIG_PWM_RASPBERRYPI_POE=m CONFIG_IRQCHIP=y # CONFIG_AL_FIC is not set CONFIG_BRCMSTB_L2_IRQ=y +# CONFIG_LAN966X_OIC is not set # CONFIG_XILINX_INTC is not set # end of IRQ chip support # CONFIG_IPACK_BUS is not set CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_BRCMSTB is not set +# CONFIG_RESET_GPIO is not set # CONFIG_RESET_RASPBERRYPI is not set # CONFIG_RESET_SIMPLE is not set # CONFIG_RESET_TI_SYSCON is not set @@ -5213,6 +5345,7 @@ CONFIG_RESET_CONTROLLER=y # # CONFIG_ARM_CCN is not set CONFIG_ARM_PMU=y +CONFIG_ARM_V6_PMU=y CONFIG_RPI_AXIPERF=m # end of Performance monitor support @@ -5227,12 +5360,14 @@ CONFIG_RPI_AXIPERF=m # CONFIG_DAX is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y +CONFIG_NVMEM_LAYOUTS=y # # Layout Types # # CONFIG_NVMEM_LAYOUT_SL28_VPD is not set # CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set +# CONFIG_NVMEM_LAYOUT_U_BOOT_ENV is not set # end of Layout Types CONFIG_NVMEM_RASPBERRYPI_OTP=y @@ -5263,6 +5398,7 @@ CONFIG_PM_OPP=y CONFIG_DCACHE_WORD_ACCESS=y CONFIG_VALIDATE_FS_PARSER=y CONFIG_FS_IOMAP=y +CONFIG_FS_STACK=y CONFIG_BUFFER_HEAD=y CONFIG_LEGACY_DIRECT_IO=y # CONFIG_EXT2_FS is not set @@ -5294,7 +5430,6 @@ CONFIG_XFS_SUPPORT_ASCII_CI=y # CONFIG_OCFS2_FS is not set CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y -# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set # CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set # CONFIG_BTRFS_DEBUG is not set # CONFIG_BTRFS_ASSERT is not set @@ -5308,6 +5443,7 @@ CONFIG_F2FS_CHECK_FS=y # CONFIG_F2FS_FS_COMPRESSION is not set CONFIG_F2FS_IOSTAT=y # CONFIG_F2FS_UNFAIR_RWSEM is not set +# CONFIG_BCACHEFS_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set @@ -5323,6 +5459,7 @@ CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m # CONFIG_CUSE is not set # CONFIG_VIRTIO_FS is not set +CONFIG_FUSE_PASSTHROUGH=y CONFIG_OVERLAY_FS=m # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -5335,9 +5472,9 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # CONFIG_NETFS_SUPPORT=y # CONFIG_NETFS_STATS is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set -# CONFIG_FSCACHE_DEBUG is not set # CONFIG_CACHEFILES is not set # end of Caches @@ -5361,10 +5498,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" -# CONFIG_NTFS_FS is not set CONFIG_NTFS3_FS=m # CONFIG_NTFS3_LZX_XPRESS is not set # CONFIG_NTFS3_FS_POSIX_ACL is not set +# CONFIG_NTFS_FS is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -5475,6 +5612,7 @@ CONFIG_CIFS_DEBUG=y # CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y # CONFIG_CIFS_ROOT is not set +# CONFIG_CIFS_COMPRESSION is not set # CONFIG_SMB_SERVER is not set CONFIG_SMBFS=y # CONFIG_CODA_FS is not set @@ -5570,6 +5708,7 @@ CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y CONFIG_INIT_STACK_NONE=y # CONFIG_INIT_STACK_ALL_PATTERN is not set # CONFIG_INIT_STACK_ALL_ZERO is not set +# CONFIG_GCC_PLUGIN_STACKLEAK is not set # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y @@ -5634,7 +5773,6 @@ CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m # CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set -# CONFIG_CRYPTO_SM2 is not set # CONFIG_CRYPTO_CURVE25519 is not set # end of Public-key cryptography @@ -5666,14 +5804,12 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_ARC4 is not set # CONFIG_CRYPTO_CHACHA20 is not set CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CFB=m CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_HCTR2 is not set # CONFIG_CRYPTO_KEYWRAP is not set # CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_OFB is not set # CONFIG_CRYPTO_PCBC is not set # CONFIG_CRYPTO_XTS is not set # end of Length-preserving ciphers and modes @@ -5744,7 +5880,9 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y -# CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE is not set +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 CONFIG_CRYPTO_KDF800108_CTR=y # end of Random number generation @@ -5809,7 +5947,6 @@ CONFIG_GENERIC_NET_UTILS=y CONFIG_CORDIC=m # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y -CONFIG_GENERIC_PCI_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y # @@ -5862,11 +5999,13 @@ CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y # CONFIG_XZ_DEC_X86 is not set # CONFIG_XZ_DEC_POWERPC is not set -# CONFIG_XZ_DEC_IA64 is not set # CONFIG_XZ_DEC_ARM is not set # CONFIG_XZ_DEC_ARMTHUMB is not set +CONFIG_XZ_DEC_ARM64=y # CONFIG_XZ_DEC_SPARC is not set +CONFIG_XZ_DEC_RISCV=y # CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_BCJ=y # CONFIG_XZ_DEC_TEST is not set CONFIG_GENERIC_ALLOCATOR=y CONFIG_REED_SOLOMON=y @@ -5878,14 +6017,16 @@ CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y -CONFIG_DMA_OPS=y +CONFIG_DMA_OPS_HELPERS=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_DMA_NEED_SYNC=y CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_ARCH_HAS_DMA_ALLOC=y CONFIG_DMA_CMA=y # @@ -5908,6 +6049,7 @@ CONFIG_NLATTR=y CONFIG_CLZ_TAB=y # CONFIG_IRQ_POLL is not set CONFIG_MPILIB=y +CONFIG_DIMLIB=y CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_FONT_SUPPORT=y @@ -5917,7 +6059,9 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y +CONFIG_STACKDEPOT_MAX_FRAMES=64 CONFIG_SBITMAP=y +# CONFIG_LWQ_TEST is not set # end of Library routines CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y @@ -5948,7 +6092,7 @@ CONFIG_DEBUG_MISC=y # # Compile-time checks and compiler options # -CONFIG_AS_HAS_NON_CONST_LEB128=y +CONFIG_AS_HAS_NON_CONST_ULEB128=y CONFIG_DEBUG_INFO_NONE=y # CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set # CONFIG_DEBUG_INFO_DWARF4 is not set @@ -5978,7 +6122,7 @@ CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +CONFIG_ARCH_HAS_UBSAN=y # CONFIG_UBSAN is not set CONFIG_HAVE_KCSAN_COMPILER=y # end of Generic Kernel Debugging Instruments @@ -6001,7 +6145,6 @@ CONFIG_SLUB_DEBUG=y # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_PAGE_REF is not set -# CONFIG_DEBUG_WX is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_OBJECTS is not set @@ -6012,6 +6155,7 @@ CONFIG_HAVE_DEBUG_KMEMLEAK=y CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set # CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y @@ -6161,6 +6305,7 @@ CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT=y # arm Debugging # # CONFIG_ARM_PTDUMP_DEBUGFS is not set +# CONFIG_ARM_DEBUG_WX is not set CONFIG_UNWINDER_FRAME_POINTER=y # CONFIG_UNWINDER_ARM is not set # CONFIG_BACKTRACE_VERBOSE is not set diff --git a/projects/RPi/devices/RPi2/linux/linux.arm.conf b/projects/RPi/devices/RPi2/linux/linux.arm.conf index 8edd40aad7..c4591fca08 100644 --- a/projects/RPi/devices/RPi2/linux/linux.arm.conf +++ b/projects/RPi/devices/RPi2/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 6.6.59 Kernel Configuration +# Linux/arm 6.12.0-rc7 Kernel Configuration # CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GCC) 13.0.0 20220604 (experimental) [master revision aec868578d8515763d75693c1fdfbc30ff0a1e68]" CONFIG_CC_IS_GCC=y @@ -11,11 +11,11 @@ CONFIG_AS_VERSION=23850 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23850 CONFIG_LLD_VERSION=0 +CONFIG_RUSTC_VERSION=0 +CONFIG_RUSTC_LLVM_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y -CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y -CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y +CONFIG_GCC_ASM_GOTO_OUTPUT_BROKEN=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=0 @@ -129,6 +129,7 @@ CONFIG_TREE_RCU=y CONFIG_TREE_SRCU=y CONFIG_NEED_SRCU_NMI_SAFE=y CONFIG_TASKS_RCU_GENERIC=y +CONFIG_NEED_TASKS_RCU=y CONFIG_TASKS_RUDE_RCU=y CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y @@ -151,14 +152,18 @@ CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_GCC10_NO_ARRAY_BOUNDS=y CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_GCC_NO_STRINGOP_OVERFLOW=y +CONFIG_CC_NO_STRINGOP_OVERFLOW=y +CONFIG_SLAB_OBJ_EXT=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y # CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y -CONFIG_MEMCG_KMEM=y +# CONFIG_MEMCG_V1 is not set CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y CONFIG_CGROUP_SCHED=y +CONFIG_GROUP_SCHED_WEIGHT=y CONFIG_FAIR_GROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y # CONFIG_RT_GROUP_SCHED is not set @@ -167,6 +172,7 @@ CONFIG_CGROUP_PIDS=y # CONFIG_CGROUP_RDMA is not set CONFIG_CGROUP_FREEZER=y CONFIG_CPUSETS=y +# CONFIG_CPUSETS_V1 is not set CONFIG_PROC_PID_CPUSET=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y @@ -202,6 +208,8 @@ CONFIG_BOOT_CONFIG=y CONFIG_INITRAMFS_PRESERVE_MTIME=y CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +# CONFIG_LD_DEAD_CODE_DATA_ELIMINATION is not set CONFIG_LD_ORPHAN_WARN=y CONFIG_LD_ORPHAN_WARN_LEVEL="warn" CONFIG_SYSCTL=y @@ -216,7 +224,7 @@ CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y +# CONFIG_BASE_SMALL is not set CONFIG_FUTEX=y CONFIG_FUTEX_PI=y CONFIG_EPOLL=y @@ -228,18 +236,17 @@ CONFIG_AIO=y CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y +CONFIG_KCMP=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +CONFIG_CACHESTAT_SYSCALL=y +# CONFIG_PC104 is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_SELFTEST is not set # CONFIG_KALLSYMS_ALL is not set -CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -CONFIG_KCMP=y -CONFIG_RSEQ=y -CONFIG_CACHESTAT_SYSCALL=y -# CONFIG_DEBUG_RSEQ is not set CONFIG_HAVE_PERF_EVENTS=y CONFIG_PERF_USE_VMALLOC=y -# CONFIG_PC104 is not set # # Kernel Performance Events And Counters @@ -255,7 +262,6 @@ CONFIG_TRACEPOINTS=y # # Kexec and crash features # -# CONFIG_CRASH_DUMP is not set # end of Kexec and crash features # end of General setup @@ -296,6 +302,9 @@ CONFIG_ARCH_MULTI_V6_V7=y # CONFIG_ARCH_VIRT is not set # CONFIG_ARCH_AIROHA is not set +# CONFIG_ARCH_RDA is not set +# CONFIG_ARCH_SUNPLUS is not set +# CONFIG_ARCH_UNIPHIER is not set # CONFIG_ARCH_ACTIONS is not set # CONFIG_ARCH_ALPINE is not set # CONFIG_ARCH_ARTPEC is not set @@ -358,7 +367,6 @@ CONFIG_ARCH_BCM2835=y # end of TI OMAP/AM/DM/DRA Family # CONFIG_ARCH_QCOM is not set -# CONFIG_ARCH_RDA is not set # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_ROCKCHIP is not set # CONFIG_ARCH_S5PV210 is not set @@ -367,10 +375,8 @@ CONFIG_ARCH_BCM2835=y # CONFIG_PLAT_SPEAR is not set # CONFIG_ARCH_STI is not set # CONFIG_ARCH_STM32 is not set -# CONFIG_ARCH_SUNPLUS is not set # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_TEGRA is not set -# CONFIG_ARCH_UNIPHIER is not set # CONFIG_ARCH_U8500 is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VEXPRESS is not set @@ -482,7 +488,8 @@ CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_SPARSEMEM_ENABLE=y # CONFIG_HIGHMEM is not set -# CONFIG_CPU_SW_DOMAIN_PAN is not set +CONFIG_ARM_PAN=y +CONFIG_CPU_SW_DOMAIN_PAN=y CONFIG_HW_PERF_EVENTS=y CONFIG_ARM_MODULE_PLTS=y CONFIG_ARCH_FORCE_MAX_ORDER=11 @@ -592,6 +599,7 @@ CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_AS_VFP_VMRS_FPINST=y CONFIG_CPU_MITIGATIONS=y +CONFIG_ARCH_HAS_DMA_OPS=y # # General architecture-dependent options @@ -634,10 +642,12 @@ CONFIG_HAVE_ARCH_SECCOMP_FILTER=y CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y # CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_LTO_NONE=y +CONFIG_ARCH_SUPPORTS_CFI_CLANG=y CONFIG_HAVE_CONTEXT_TRACKING_USER=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y @@ -650,8 +660,11 @@ CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 +CONFIG_HAVE_PAGE_SIZE_4KB=y +CONFIG_PAGE_SIZE_4KB=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SHIFT=12 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y @@ -683,7 +696,6 @@ CONFIG_FUNCTION_ALIGNMENT=0 # end of General architecture-dependent options CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_DEBUG is not set # CONFIG_MODULE_FORCE_LOAD is not set @@ -693,10 +705,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set -CONFIG_MODULE_COMPRESS_NONE=y -# CONFIG_MODULE_COMPRESS_GZIP is not set -# CONFIG_MODULE_COMPRESS_XZ is not set -# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_COMPRESS is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set @@ -709,9 +718,9 @@ CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_ICQ=y CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_DEV_INTEGRITY is not set +CONFIG_BLK_DEV_WRITE_MOUNTED=y # CONFIG_BLK_DEV_ZONED is not set CONFIG_BLK_DEV_THROTTLING=y -# CONFIG_BLK_DEV_THROTTLING_LOW is not set # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_IOCOST is not set @@ -794,18 +803,18 @@ CONFIG_SWAP=y # CONFIG_ZSWAP is not set # -# SLAB allocator options +# Slab allocator options # -# CONFIG_SLAB_DEPRECATED is not set CONFIG_SLUB=y # CONFIG_SLUB_TINY is not set CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_FREELIST_HARDENED is not set +CONFIG_SLAB_BUCKETS=y # CONFIG_SLUB_STATS is not set CONFIG_SLUB_CPU_PARTIAL=y # CONFIG_RANDOM_KMALLOC_CACHES is not set -# end of SLAB allocator options +# end of Slab allocator options # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set # CONFIG_COMPAT_BRK is not set @@ -815,7 +824,7 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y -CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_SPLIT_PTE_PTLOCKS=y CONFIG_COMPACTION=y CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 # CONFIG_PAGE_REPORTING is not set @@ -826,12 +835,12 @@ CONFIG_PCP_BATCH_SCALE_MAX=5 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_CMA=y -# CONFIG_CMA_DEBUG is not set CONFIG_CMA_DEBUGFS=y # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CPU_CACHE_ALIASING=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y CONFIG_ZONE_DMA=y CONFIG_VM_EVENT_COUNTERS=y @@ -844,7 +853,10 @@ CONFIG_MEMFD_CREATE=y CONFIG_LRU_GEN=y # CONFIG_LRU_GEN_ENABLED is not set # CONFIG_LRU_GEN_STATS is not set +CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y +CONFIG_PER_VMA_LOCK=y CONFIG_LOCK_MM_AND_FIND_VMA=y +CONFIG_EXECMEM=y # # Data Access Monitoring @@ -858,6 +870,7 @@ CONFIG_NET_INGRESS=y CONFIG_NET_EGRESS=y CONFIG_NET_XGRESS=y CONFIG_SKB_EXTENSIONS=y +CONFIG_NET_DEVMEM=y # # Networking options @@ -865,7 +878,6 @@ CONFIG_SKB_EXTENSIONS=y CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y -CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set @@ -1144,6 +1156,7 @@ CONFIG_IP_VS_NFCT=y # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=m +CONFIG_IP_NF_IPTABLES_LEGACY=m # CONFIG_NF_SOCKET_IPV4 is not set # CONFIG_NF_TPROXY_IPV4 is not set # CONFIG_NF_DUP_IPV4 is not set @@ -1166,12 +1179,13 @@ CONFIG_IP_NF_MANGLE=m # CONFIG_IP_NF_TARGET_ECN is not set # CONFIG_IP_NF_TARGET_TTL is not set # CONFIG_IP_NF_RAW is not set -# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_ARPFILTER is not set # end of IP: Netfilter Configuration # # IPv6: Netfilter Configuration # +CONFIG_IP6_NF_IPTABLES_LEGACY=m # CONFIG_NF_SOCKET_IPV6 is not set # CONFIG_NF_TPROXY_IPV6 is not set # CONFIG_NF_DUP_IPV6 is not set @@ -1202,7 +1216,6 @@ CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_NF_DEFRAG_IPV6=m # CONFIG_NF_CONNTRACK_BRIDGE is not set # CONFIG_BRIDGE_NF_EBTABLES is not set -# CONFIG_BPFILTER is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set # CONFIG_RDS is not set @@ -1355,6 +1368,7 @@ CONFIG_BT_HCIUART_BCM=y # CONFIG_BT_HCIUART_QCA is not set # CONFIG_BT_HCIUART_AG6XX is not set # CONFIG_BT_HCIUART_MRVL is not set +# CONFIG_BT_HCIUART_AML is not set CONFIG_BT_HCIBCM203X=m # CONFIG_BT_HCIBPA10X is not set CONFIG_BT_HCIBFUSB=m @@ -1392,7 +1406,6 @@ CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" # CONFIG_MAC80211_MESH is not set CONFIG_MAC80211_LEDS=y -# CONFIG_MAC80211_DEBUGFS is not set # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 @@ -1421,6 +1434,7 @@ CONFIG_ETHTOOL_NETLINK=y # CONFIG_ARM_AMBA=y CONFIG_HAVE_PCI=y +CONFIG_GENERIC_PCI_IOMAP=y # CONFIG_PCI is not set # CONFIG_PCCARD is not set @@ -1451,6 +1465,7 @@ CONFIG_WANT_DEV_COREDUMP=y # CONFIG_DEBUG_DEVRES is not set # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_DEVICES=y CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_REGMAP=y @@ -1467,7 +1482,6 @@ CONFIG_GENERIC_ARCH_TOPOLOGY=y # # Bus devices # -# CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_MOXTET is not set # CONFIG_VEXPRESS_CONFIG is not set # CONFIG_MHI_BUS is not set @@ -1498,6 +1512,12 @@ CONFIG_RASPBERRYPI_FIRMWARE=y # CONFIG_TRUSTED_FOUNDATIONS is not set CONFIG_FW_CS_DSP=m # CONFIG_GOOGLE_FIRMWARE is not set + +# +# Qualcomm firmware drivers +# +# end of Qualcomm firmware drivers + CONFIG_HAVE_ARM_SMCCC=y # @@ -1527,6 +1547,7 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_NULL_BLK is not set CONFIG_CDROM=y # CONFIG_ZRAM is not set +CONFIG_ZRAM_DEF_COMP="unset-value" CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 # CONFIG_BLK_DEV_DRBD is not set @@ -1553,6 +1574,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 CONFIG_BCM2835_SMI=m # CONFIG_AD525X_DPOT is not set # CONFIG_DUMMY_IRQ is not set +# CONFIG_RPMB is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_APDS9802ALS is not set @@ -1576,7 +1598,6 @@ CONFIG_MISC_RTSX=y # # CONFIG_EEPROM_AT24 is not set # CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set # CONFIG_EEPROM_MAX6875 is not set CONFIG_EEPROM_93CX6=m # CONFIG_EEPROM_93XX46 is not set @@ -1691,6 +1712,7 @@ CONFIG_VXLAN=m # CONFIG_GENEVE is not set # CONFIG_BAREUDP is not set # CONFIG_GTP is not set +# CONFIG_PFCP is not set # CONFIG_AMT is not set # CONFIG_MACSEC is not set CONFIG_NETCONSOLE=y @@ -1702,6 +1724,7 @@ CONFIG_TUN=y # CONFIG_TUN_VNET_CROSS_LE is not set CONFIG_VETH=m CONFIG_NLMON=m +# CONFIG_NETKIT is not set # CONFIG_NET_VRF is not set # CONFIG_ETHERNET is not set CONFIG_PHYLINK=m @@ -1715,6 +1738,7 @@ CONFIG_FIXED_PHY=y # # MII PHY device drivers # +# CONFIG_AIR_EN8811H_PHY is not set # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set # CONFIG_ADIN1100_PHY is not set @@ -1750,6 +1774,9 @@ CONFIG_MICROCHIP_PHY=y # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_NCN26000_PHY is not set # CONFIG_AT803X_PHY is not set +# CONFIG_QCA83XX_PHY is not set +# CONFIG_QCA808X_PHY is not set +# CONFIG_QCA807X_PHY is not set # CONFIG_QSEMI_PHY is not set # CONFIG_REALTEK_PHY is not set # CONFIG_RENESAS_PHY is not set @@ -1763,6 +1790,7 @@ CONFIG_SMSC_PHY=y # CONFIG_DP83867_PHY is not set # CONFIG_DP83869_PHY is not set # CONFIG_DP83TD510_PHY is not set +# CONFIG_DP83TG720_PHY is not set # CONFIG_VITESSE_PHY is not set # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set @@ -1790,6 +1818,7 @@ CONFIG_MDIO_DEVRES=y # # PCS device drivers # +# CONFIG_PCS_XPCS is not set # end of PCS device drivers CONFIG_PPP=m @@ -1856,7 +1885,6 @@ CONFIG_ATH9K_COMMON=m CONFIG_ATH9K_BTCOEX_SUPPORT=y CONFIG_ATH9K=m CONFIG_ATH9K_AHB=y -# CONFIG_ATH9K_DEBUGFS is not set # CONFIG_ATH9K_DYNACK is not set # CONFIG_ATH9K_WOW is not set CONFIG_ATH9K_RFKILL=y @@ -1878,6 +1906,7 @@ CONFIG_AR5523=m # CONFIG_ATH10K is not set CONFIG_WCN36XX=m # CONFIG_WCN36XX_DEBUGFS is not set +# CONFIG_ATH11K is not set CONFIG_WLAN_VENDOR_ATMEL=y # CONFIG_AT76C50X_USB is not set CONFIG_WLAN_VENDOR_BROADCOM=y @@ -1906,10 +1935,8 @@ CONFIG_BRCMFMAC_SDIO=y CONFIG_BRCMFMAC_USB=y # CONFIG_BRCM_TRACING is not set # CONFIG_BRCMDBG is not set -CONFIG_WLAN_VENDOR_CISCO=y CONFIG_WLAN_VENDOR_INTEL=y CONFIG_WLAN_VENDOR_INTERSIL=y -# CONFIG_HOSTAP is not set CONFIG_P54_COMMON=m CONFIG_P54_USB=m # CONFIG_P54_SPI is not set @@ -1939,6 +1966,7 @@ CONFIG_MT7663U=m CONFIG_MT7921_COMMON=m # CONFIG_MT7921S is not set CONFIG_MT7921U=m +# CONFIG_MT7925U is not set CONFIG_WLAN_VENDOR_MICROCHIP=y # CONFIG_WILC1000_SDIO is not set # CONFIG_WILC1000_SPI is not set @@ -1990,6 +2018,7 @@ CONFIG_RTW88_8822BU=m # CONFIG_RTW88_8822CS is not set CONFIG_RTW88_8822CU=m # CONFIG_RTW88_8723DS is not set +# CONFIG_RTW88_8723CS is not set CONFIG_RTW88_8723DU=m # CONFIG_RTW88_8821CS is not set CONFIG_RTW88_8821CU=m @@ -2010,11 +2039,9 @@ CONFIG_WLAN_VENDOR_TI=y # CONFIG_WL18XX is not set # CONFIG_WLCORE is not set CONFIG_WLAN_VENDOR_ZYDAS=y -CONFIG_USB_ZD1201=m CONFIG_ZD1211RW=m # CONFIG_ZD1211RW_DEBUG is not set # CONFIG_WLAN_VENDOR_QUANTENNA is not set -CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_MAC80211_HWSIM is not set # CONFIG_VIRT_WIFI is not set # CONFIG_WAN is not set @@ -2069,7 +2096,6 @@ CONFIG_KEYBOARD_GPIO=m # CONFIG_KEYBOARD_LM8323 is not set # CONFIG_KEYBOARD_LM8333 is not set # CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_MCS is not set # CONFIG_KEYBOARD_MPR121 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set @@ -2115,6 +2141,7 @@ CONFIG_JOYSTICK_PSXPAD_SPI_FF=y # CONFIG_JOYSTICK_QWIIC is not set # CONFIG_JOYSTICK_FSIA6B is not set # CONFIG_JOYSTICK_SENSEHAT is not set +# CONFIG_JOYSTICK_SEESAW is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=m @@ -2129,7 +2156,6 @@ CONFIG_TOUCHSCREEN_ADS7846=m # CONFIG_TOUCHSCREEN_CY8CTMA140 is not set # CONFIG_TOUCHSCREEN_CY8CTMG110 is not set # CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set -# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set # CONFIG_TOUCHSCREEN_CYTTSP5 is not set # CONFIG_TOUCHSCREEN_DYNAPRO is not set # CONFIG_TOUCHSCREEN_HAMPSHIRE is not set @@ -2139,6 +2165,8 @@ CONFIG_TOUCHSCREEN_EGALAX=m # CONFIG_TOUCHSCREEN_EXC3000 is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI is not set # CONFIG_TOUCHSCREEN_HIDEEP is not set # CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set # CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set @@ -2152,7 +2180,6 @@ CONFIG_TOUCHSCREEN_EGALAX=m # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set # CONFIG_TOUCHSCREEN_WACOM_I2C is not set # CONFIG_TOUCHSCREEN_MAX11801 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set # CONFIG_TOUCHSCREEN_MMS114 is not set # CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set # CONFIG_TOUCHSCREEN_MSG2638 is not set @@ -2283,7 +2310,6 @@ CONFIG_TTY=y CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set @@ -2369,7 +2395,6 @@ CONFIG_RASPBERRYPI_GPIOMEM=y # CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y -# CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y @@ -2403,7 +2428,7 @@ CONFIG_I2C_BCM2708_BAUDRATE=100000 CONFIG_I2C_BCM2835=y # CONFIG_I2C_BRCMSTB is not set # CONFIG_I2C_CBUS_GPIO is not set -# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_CORE is not set # CONFIG_I2C_EMEV2 is not set CONFIG_I2C_GPIO=y # CONFIG_I2C_GPIO_FAULT_INJECTOR is not set @@ -2453,6 +2478,7 @@ CONFIG_SPI_BCM2835AUX=m # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_DESIGNWARE is not set # CONFIG_SPI_GPIO is not set # CONFIG_SPI_FSL_SPI is not set @@ -2501,6 +2527,7 @@ CONFIG_PINMUX=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_AW9523 is not set # CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_MCP23S08 is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set @@ -2600,15 +2627,24 @@ CONFIG_GPIO_FSM=m # CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers +# +# GPIO Debugging utilities +# +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set +# CONFIG_GPIO_VIRTUSER is not set +# end of GPIO Debugging utilities + CONFIG_W1=m # # 1-wire Bus Masters # +# CONFIG_W1_MASTER_AMD_AXI is not set # CONFIG_W1_MASTER_DS2490 is not set # CONFIG_W1_MASTER_DS2482 is not set CONFIG_W1_MASTER_GPIO=m # CONFIG_W1_MASTER_SGI is not set +# CONFIG_W1_MASTER_UART is not set # end of 1-wire Bus Masters # @@ -2635,7 +2671,6 @@ CONFIG_W1_SLAVE_THERM=m CONFIG_POWER_RESET=y # CONFIG_POWER_RESET_BRCMKONA is not set -# CONFIG_POWER_RESET_BRCMSTB is not set CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_GPIO_RESTART=y # CONFIG_POWER_RESET_LTC2952 is not set @@ -2646,6 +2681,7 @@ CONFIG_POWER_RESET_RESTART=y # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_SYSCON_REBOOT_MODE is not set # CONFIG_NVMEM_REBOOT_MODE is not set +# CONFIG_POWER_SEQUENCING is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y @@ -2663,8 +2699,8 @@ CONFIG_RPI_POE_POWER=m # CONFIG_CHARGER_SBS is not set # CONFIG_MANAGER_SBS is not set # CONFIG_BATTERY_BQ27XXX is not set -# CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_MAX1721X is not set # CONFIG_CHARGER_ISP1704 is not set # CONFIG_CHARGER_MAX8903 is not set @@ -2693,6 +2729,7 @@ CONFIG_RPI_POE_POWER=m # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set # CONFIG_BATTERY_UG3105 is not set +# CONFIG_FUEL_GAUGE_MM8013 is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set @@ -2702,7 +2739,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AD7314 is not set # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set @@ -2719,8 +2755,10 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CHIPCAP2 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set # CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DS620 is not set @@ -2729,6 +2767,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_F75375S is not set # CONFIG_SENSORS_FTSTEUTATES is not set +# CONFIG_SENSORS_GIGABYTE_WATERFORCE is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_G760A is not set @@ -2738,12 +2777,14 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_HS3001 is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWERZ is not set # CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LINEAGE is not set # CONFIG_SENSORS_LTC2945 is not set # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2991 is not set # CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set @@ -2751,6 +2792,7 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LTC4282 is not set # CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set @@ -2764,7 +2806,6 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_MAX6620 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_MAX6697 is not set # CONFIG_SENSORS_MAX31790 is not set @@ -2798,10 +2839,12 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_KRAKEN3 is not set # CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set +# CONFIG_SENSORS_PT5161L is not set CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_RASPBERRYPI_HWMON=y # CONFIG_SENSORS_SBTSI is not set @@ -2830,6 +2873,7 @@ CONFIG_SENSORS_RASPBERRYPI_HWMON=y # CONFIG_SENSORS_INA2XX is not set # CONFIG_SENSORS_INA238 is not set # CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP102 is not set @@ -2853,10 +2897,11 @@ CONFIG_SENSORS_RASPBERRYPI_HWMON=y CONFIG_THERMAL=y # CONFIG_THERMAL_NETLINK is not set # CONFIG_THERMAL_STATISTICS is not set +# CONFIG_THERMAL_DEBUGFS is not set +# CONFIG_THERMAL_CORE_TESTING is not set CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y -# CONFIG_THERMAL_WRITABLE_TRIPS is not set CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set @@ -2926,6 +2971,7 @@ CONFIG_BCMA_DRIVER_GMAC_CMN=y # Multifunction device drivers # CONFIG_MFD_CORE=y +# CONFIG_MFD_ADP5585 is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_AS3711 is not set # CONFIG_MFD_SMPRO is not set @@ -2958,6 +3004,7 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_MAX14577 is not set # CONFIG_MFD_MAX77541 is not set # CONFIG_MFD_MAX77620 is not set @@ -3041,10 +3088,13 @@ CONFIG_MFD_WM5102=y # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set # CONFIG_MFD_ATC260X_I2C is not set # CONFIG_MFD_QCOM_PM8008 is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC_SPI is not set # CONFIG_MFD_RSMU_I2C is not set @@ -3056,6 +3106,7 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_NETLINK_EVENTS is not set # CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set @@ -3077,6 +3128,7 @@ CONFIG_REGULATOR_ARIZONA_MICSUPP=m # CONFIG_REGULATOR_LTC3589 is not set # CONFIG_REGULATOR_LTC3676 is not set # CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX77503 is not set # CONFIG_REGULATOR_MAX77857 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set @@ -3358,6 +3410,7 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # # Atmel media platform drivers # +# CONFIG_VIDEO_BCM2835_UNICAM_LEGACY is not set # CONFIG_VIDEO_BCM2835_UNICAM is not set # @@ -3386,6 +3439,10 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # Microchip Technology, Inc. media platform drivers # +# +# Nuvoton media platform drivers +# + # # NVidia media platform drivers # @@ -3476,7 +3533,12 @@ CONFIG_MEDIA_ATTACH=y # CONFIG_VIDEO_IR_I2C=m CONFIG_VIDEO_CAMERA_SENSOR=y +# CONFIG_VIDEO_ALVIUM_CSI2 is not set # CONFIG_VIDEO_AR0521 is not set +# CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set +# CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_ARDUCAM_64MP is not set # CONFIG_VIDEO_ARDUCAM_PIVARIETY is not set # CONFIG_VIDEO_HI556 is not set @@ -3487,6 +3549,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -3501,6 +3564,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_IMX708 is not set # CONFIG_VIDEO_MT9M001 is not set # CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9M114 is not set # CONFIG_VIDEO_MT9P031 is not set # CONFIG_VIDEO_MT9T112 is not set # CONFIG_VIDEO_MT9V011 is not set @@ -3546,10 +3610,16 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_S5C73M3 is not set # CONFIG_VIDEO_S5K5BAF is not set # CONFIG_VIDEO_S5K6A3 is not set -# CONFIG_VIDEO_ST_VGXY61 is not set +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set +# +# Camera ISPs +# +# CONFIG_VIDEO_THP7312 is not set +# end of Camera ISPs + # # Lens drivers # @@ -3621,6 +3691,7 @@ CONFIG_VIDEO_SAA711X=m # CONFIG_VIDEO_TVP5150 is not set # CONFIG_VIDEO_TVP7002 is not set # CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9900 is not set # CONFIG_VIDEO_TW9903 is not set # CONFIG_VIDEO_TW9906 is not set # CONFIG_VIDEO_TW9910 is not set @@ -3682,6 +3753,8 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_DS90UB913 is not set # CONFIG_VIDEO_DS90UB953 is not set # CONFIG_VIDEO_DS90UB960 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # end of Video serializers and deserializers # @@ -3909,13 +3982,13 @@ CONFIG_DVB_SP2=m # # Graphics support # -CONFIG_VIDEO_CMDLINE=y -CONFIG_VIDEO_NOMODESET=y +CONFIG_VIDEO=y # CONFIG_AUXDISPLAY is not set CONFIG_DRM=y CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DEBUG_MM is not set CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_PANIC is not set # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set # CONFIG_DRM_DEBUG_MODESET_LOCK is not set CONFIG_DRM_FBDEV_EMULATION=y @@ -3923,9 +3996,10 @@ CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set CONFIG_DRM_LOAD_EDID_FIRMWARE=y CONFIG_DRM_DISPLAY_HELPER=y +# CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set +# CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set CONFIG_DRM_DISPLAY_HDMI_HELPER=y -# CONFIG_DRM_DP_AUX_CHARDEV is not set -# CONFIG_DRM_DP_CEC is not set +CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER=y CONFIG_DRM_GEM_DMA_HELPER=y # @@ -3962,33 +4036,40 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_AUO_A030JTN01 is not set # CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set # CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set # CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set -# CONFIG_DRM_PANEL_DSI_CM is not set -# CONFIG_DRM_PANEL_LVDS is not set -CONFIG_DRM_PANEL_SIMPLE=y -# CONFIG_DRM_PANEL_EDP is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 is not set # CONFIG_DRM_PANEL_EBBG_FT8719 is not set # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_DSI_CM is not set +# CONFIG_DRM_PANEL_LVDS is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set +# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set # CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set +# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set # CONFIG_DRM_PANEL_JDI_R63452 is not set # CONFIG_DRM_PANEL_KHADAS_TS050 is not set # CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set -# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_LG_SW43408 is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set # CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set @@ -3997,8 +4078,8 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set # CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set # CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set -# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set # CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set # CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set @@ -4007,16 +4088,20 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set # CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set # CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set # CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set # CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set @@ -4031,15 +4116,18 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set # CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set # CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set +# CONFIG_DRM_PANEL_EDP is not set +CONFIG_DRM_PANEL_SIMPLE=y +# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set # CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set # CONFIG_DRM_PANEL_TPO_Y17P is not set # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set # CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set -# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN is not set # CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set # CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set @@ -4112,11 +4200,12 @@ CONFIG_DRM_VC4_HDMI_CEC=y # CONFIG_DRM_TVE200 is not set # CONFIG_DRM_LIMA is not set # CONFIG_DRM_PANFROST is not set +# CONFIG_DRM_PANTHOR is not set # CONFIG_DRM_MCDE is not set # CONFIG_DRM_TIDSS is not set # CONFIG_DRM_GUD is not set # CONFIG_DRM_SSD130X is not set -# CONFIG_DRM_LEGACY is not set +# CONFIG_DRM_WERROR is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y # @@ -4124,7 +4213,6 @@ CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y # CONFIG_FB=y CONFIG_FB_BCM2708=y -# CONFIG_FB_ARMCLCD is not set # CONFIG_FB_OPENCORES is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_SMSCUFX is not set @@ -4146,10 +4234,9 @@ CONFIG_FB_SYS_FILLRECT=y CONFIG_FB_SYS_COPYAREA=y CONFIG_FB_SYS_IMAGEBLIT=y # CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_SYS_FOPS=y +CONFIG_FB_SYSMEM_FOPS=y CONFIG_FB_DEFERRED_IO=y CONFIG_FB_DMAMEM_HELPERS=y -CONFIG_FB_IOMEM_FOPS=y CONFIG_FB_SYSMEM_HELPERS=y CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y # CONFIG_FB_MODE_HELPERS is not set @@ -4174,15 +4261,18 @@ CONFIG_LCD_CLASS_DEVICE=m # CONFIG_LCD_OTM3225A is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set # CONFIG_BACKLIGHT_PWM is not set CONFIG_BACKLIGHT_RPI=y # CONFIG_BACKLIGHT_QCOM_WLED is not set # CONFIG_BACKLIGHT_ADP8860 is not set # CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set # CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_BACKLIGHT_MP3309C is not set CONFIG_BACKLIGHT_GPIO=y # CONFIG_BACKLIGHT_LV5207LP is not set # CONFIG_BACKLIGHT_BD6107 is not set @@ -4197,6 +4287,8 @@ CONFIG_HDMI=y # Console display driver support # CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=30 CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y @@ -4228,10 +4320,10 @@ CONFIG_SND_MAX_CARDS=32 # CONFIG_SND_SUPPORT_OLD_API is not set CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set # CONFIG_SND_CTL_INPUT_VALIDATION is not set +# CONFIG_SND_UTIMER is not set CONFIG_SND_VMASTER=y # CONFIG_SND_SEQUENCER is not set # CONFIG_SND_DRIVERS is not set @@ -4372,6 +4464,7 @@ CONFIG_SND_SOC_ADAU7002=m # CONFIG_SND_SOC_AK4458 is not set CONFIG_SND_SOC_AK4554=m # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -4379,6 +4472,8 @@ CONFIG_SND_SOC_AK4554=m # CONFIG_SND_SOC_AW8738 is not set # CONFIG_SND_SOC_AW88395 is not set # CONFIG_SND_SOC_AW88261 is not set +# CONFIG_SND_SOC_AW87390 is not set +# CONFIG_SND_SOC_AW88399 is not set # CONFIG_SND_SOC_BD28623 is not set # CONFIG_SND_SOC_BT_SCO is not set # CONFIG_SND_SOC_CHV3_CODEC is not set @@ -4411,12 +4506,14 @@ CONFIG_SND_SOC_CS42XX8_I2C=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set # CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CX2072X is not set CONFIG_SND_SOC_DA7213=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8326 is not set # CONFIG_SND_SOC_ES8328_I2C is not set @@ -4425,7 +4522,6 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_HDA is not set # CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_IDT821034 is not set -# CONFIG_SND_SOC_INNO_RK3036 is not set CONFIG_SND_SOC_MA120X0P=m # CONFIG_SND_SOC_MAX98088 is not set # CONFIG_SND_SOC_MAX98090 is not set @@ -4456,14 +4552,15 @@ CONFIG_SND_SOC_PCM5102A=m CONFIG_SND_SOC_PCM512x=m CONFIG_SND_SOC_PCM512x_I2C=m # CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_PCM6240 is not set # CONFIG_SND_SOC_PEB2466 is not set -# CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RT5616 is not set CONFIG_SND_SOC_PCM1794A=m # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5640 is not set # CONFIG_SND_SOC_RT5659 is not set # CONFIG_SND_SOC_RT9120 is not set +# CONFIG_SND_SOC_RTQ9128 is not set CONFIG_SND_SOC_SGTL5000=m CONFIG_SND_SOC_SIGMADSP=m CONFIG_SND_SOC_SIGMADSP_I2C=m @@ -4543,6 +4640,7 @@ CONFIG_SND_SOC_WM8960=m # CONFIG_SND_SOC_ZL38060 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6357 is not set # CONFIG_SND_SOC_MT6358 is not set # CONFIG_SND_SOC_MT6660 is not set # CONFIG_SND_SOC_NAU8315 is not set @@ -4607,6 +4705,7 @@ CONFIG_HID_EZKEY=y # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set # CONFIG_HID_HOLTEK is not set +# CONFIG_HID_GOODIX_SPI is not set # CONFIG_HID_GOOGLE_STADIA_FF is not set # CONFIG_HID_VIVALDI is not set # CONFIG_HID_GT683R is not set @@ -4648,7 +4747,6 @@ CONFIG_NINTENDO_FF=y # CONFIG_HID_NTRIG is not set # CONFIG_HID_NVIDIA_SHIELD is not set CONFIG_HID_ORTEK=y -CONFIG_HID_OUYA=y CONFIG_HID_PANTHERLORD=y CONFIG_PANTHERLORD_FF=y CONFIG_HID_PENMOUNT=y @@ -4686,6 +4784,7 @@ CONFIG_HID_TOPSEED=y # CONFIG_HID_U2FZERO is not set # CONFIG_HID_WACOM is not set CONFIG_HID_WIIMOTE=m +# CONFIG_HID_WINWING is not set CONFIG_HID_XINMO=y # CONFIG_HID_ZEROPLUS is not set CONFIG_HID_ZYDACRON=y @@ -4733,6 +4832,7 @@ CONFIG_USB_DEFAULT_PERSIST=y # CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 CONFIG_USB_MON=m # @@ -4884,7 +4984,7 @@ CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set -# CONFIG_USB_ONBOARD_HUB is not set +# CONFIG_USB_ONBOARD_DEV is not set # # USB Physical Layer drivers @@ -4936,6 +5036,7 @@ CONFIG_MMC_REALTEK_USB=m CONFIG_MMC_HSQ=y # CONFIG_MMC_BCM2835 is not set # CONFIG_MMC_MTK is not set +# CONFIG_MMC_SDHCI_BRCMSTB is not set # CONFIG_MMC_SDHCI_XENON is not set # CONFIG_SCSI_UFSHCD is not set # CONFIG_MEMSTICK is not set @@ -5001,11 +5102,14 @@ CONFIG_LEDS_GPIO=y # CONFIG_LEDS_RT4505 is not set # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set +# CONFIG_LEDS_SY7802 is not set # # RGB LED drivers # # CONFIG_LEDS_GROUP_MULTICOLOR is not set +# CONFIG_LEDS_KTD202X is not set +# CONFIG_LEDS_NCP5623 is not set # CONFIG_LEDS_PWM_MULTICOLOR is not set # @@ -5018,6 +5122,7 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CPU=y # CONFIG_LEDS_TRIGGER_ACTIVITY is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set CONFIG_LEDS_TRIGGER_DEFAULT_ON=y # @@ -5029,8 +5134,8 @@ CONFIG_LEDS_TRIGGER_INPUT=y # CONFIG_LEDS_TRIGGER_PANIC is not set # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set -# CONFIG_LEDS_TRIGGER_AUDIO is not set # CONFIG_LEDS_TRIGGER_TTY is not set +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set CONFIG_LEDS_TRIGGER_ACTPWR=y # @@ -5070,6 +5175,7 @@ CONFIG_RTC_DRV_DS1307=m # CONFIG_RTC_DRV_DS1672 is not set # CONFIG_RTC_DRV_HYM8563 is not set # CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_MAX31335 is not set # CONFIG_RTC_DRV_NCT3018Y is not set # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set @@ -5086,12 +5192,14 @@ CONFIG_RTC_DRV_PCF8563=m # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8111 is not set # CONFIG_RTC_DRV_RX8581 is not set # CONFIG_RTC_DRV_RX8025 is not set # CONFIG_RTC_DRV_EM3027 is not set # CONFIG_RTC_DRV_RV3028 is not set # CONFIG_RTC_DRV_RV3032 is not set # CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD2405AL is not set # CONFIG_RTC_DRV_SD3078 is not set # @@ -5175,6 +5283,7 @@ CONFIG_DMA_BCM2708=y # CONFIG_XILINX_DMA is not set # CONFIG_XILINX_XDMA is not set # CONFIG_XILINX_ZYNQMP_DPDMA is not set +# CONFIG_AMD_QDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_DW_DMAC is not set @@ -5218,7 +5327,6 @@ CONFIG_VHOST_MENU=y # CONFIG_GREYBUS is not set # CONFIG_COMEDI is not set CONFIG_STAGING=y -# CONFIG_PRISM2_USB is not set # CONFIG_RTLLIB is not set CONFIG_RTL8723BS=m CONFIG_R8712U=m @@ -5226,11 +5334,13 @@ CONFIG_VT6656=m CONFIG_STAGING_MEDIA=y # CONFIG_VIDEO_MAX96712 is not set # CONFIG_VIDEO_RPIVID is not set + +# +# StarFive media platform drivers +# # CONFIG_STAGING_MEDIA_DEPRECATED is not set -# CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set # CONFIG_FB_TFT is not set -# CONFIG_KS7010 is not set CONFIG_BCM_VIDEOCORE=y CONFIG_BCM2835_VCHIQ=y CONFIG_VCHIQ_CDEV=y @@ -5240,11 +5350,11 @@ CONFIG_BCM_VC_SM_CMA=y CONFIG_VIDEO_CODEC_BCM2835=m CONFIG_VIDEO_ISP_BCM2835=m CONFIG_BCM2835_VCHIQ_MMAL=y -# CONFIG_PI433 is not set # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y @@ -5334,9 +5444,6 @@ CONFIG_BCM2835_MBOX=y # # Broadcom SoC drivers # -CONFIG_BCM2835_POWER=y -CONFIG_RASPBERRYPI_POWER=y -# CONFIG_SOC_BRCMSTB is not set # end of Broadcom SoC drivers # @@ -5376,6 +5483,33 @@ CONFIG_RASPBERRYPI_POWER=y # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers +# +# PM Domains +# + +# +# Amlogic PM Domains +# +# end of Amlogic PM Domains + +# +# Broadcom PM Domains +# +CONFIG_BCM2835_POWER=y +CONFIG_RASPBERRYPI_POWER=y +# end of Broadcom PM Domains + +# +# i.MX PM Domains +# +# end of i.MX PM Domains + +# +# Qualcomm PM Domains +# +# end of Qualcomm PM Domains +# end of PM Domains + # CONFIG_PM_DEVFREQ is not set CONFIG_EXTCON=y @@ -5384,6 +5518,7 @@ CONFIG_EXTCON=y # # CONFIG_EXTCON_FSA9480 is not set # CONFIG_EXTCON_GPIO is not set +# CONFIG_EXTCON_LC824206XA is not set # CONFIG_EXTCON_MAX3355 is not set # CONFIG_EXTCON_PTN5150 is not set # CONFIG_EXTCON_RT8973A is not set @@ -5392,7 +5527,6 @@ CONFIG_EXTCON=y # CONFIG_MEMORY is not set # CONFIG_IIO is not set CONFIG_PWM=y -CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL_TCB is not set CONFIG_PWM_BCM2835=m @@ -5413,12 +5547,14 @@ CONFIG_ARM_GIC_MAX_NR=1 # CONFIG_AL_FIC is not set # CONFIG_BCM2712_MIP is not set CONFIG_BRCMSTB_L2_IRQ=y +# CONFIG_LAN966X_OIC is not set # CONFIG_XILINX_INTC is not set # end of IRQ chip support # CONFIG_IPACK_BUS is not set CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_BRCMSTB is not set +# CONFIG_RESET_GPIO is not set # CONFIG_RESET_RASPBERRYPI is not set # CONFIG_RESET_SIMPLE is not set # CONFIG_RESET_TI_SYSCON is not set @@ -5458,6 +5594,7 @@ CONFIG_RESET_CONTROLLER=y # CONFIG_ARM_CCI_PMU is not set # CONFIG_ARM_CCN is not set CONFIG_ARM_PMU=y +CONFIG_ARM_V7_PMU=y # CONFIG_ARM_PMUV3 is not set CONFIG_RPI_AXIPERF=m # end of Performance monitor support @@ -5473,12 +5610,14 @@ CONFIG_RPI_AXIPERF=m # CONFIG_DAX is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y +CONFIG_NVMEM_LAYOUTS=y # # Layout Types # # CONFIG_NVMEM_LAYOUT_SL28_VPD is not set # CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set +# CONFIG_NVMEM_LAYOUT_U_BOOT_ENV is not set # end of Layout Types CONFIG_NVMEM_RASPBERRYPI_OTP=y @@ -5510,6 +5649,7 @@ CONFIG_PM_OPP=y CONFIG_DCACHE_WORD_ACCESS=y CONFIG_VALIDATE_FS_PARSER=y CONFIG_FS_IOMAP=y +CONFIG_FS_STACK=y CONFIG_BUFFER_HEAD=y CONFIG_LEGACY_DIRECT_IO=y # CONFIG_EXT2_FS is not set @@ -5541,7 +5681,6 @@ CONFIG_XFS_SUPPORT_ASCII_CI=y # CONFIG_OCFS2_FS is not set CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y -# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set # CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set # CONFIG_BTRFS_DEBUG is not set # CONFIG_BTRFS_ASSERT is not set @@ -5555,6 +5694,7 @@ CONFIG_F2FS_CHECK_FS=y # CONFIG_F2FS_FS_COMPRESSION is not set CONFIG_F2FS_IOSTAT=y # CONFIG_F2FS_UNFAIR_RWSEM is not set +# CONFIG_BCACHEFS_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set @@ -5570,6 +5710,7 @@ CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m # CONFIG_CUSE is not set # CONFIG_VIRTIO_FS is not set +CONFIG_FUSE_PASSTHROUGH=y CONFIG_OVERLAY_FS=m # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -5582,9 +5723,9 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # CONFIG_NETFS_SUPPORT=y # CONFIG_NETFS_STATS is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set -# CONFIG_FSCACHE_DEBUG is not set # CONFIG_CACHEFILES is not set # end of Caches @@ -5608,10 +5749,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" -# CONFIG_NTFS_FS is not set CONFIG_NTFS3_FS=m # CONFIG_NTFS3_LZX_XPRESS is not set # CONFIG_NTFS3_FS_POSIX_ACL is not set +# CONFIG_NTFS_FS is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -5723,6 +5864,7 @@ CONFIG_CIFS_DEBUG=y # CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y # CONFIG_CIFS_ROOT is not set +# CONFIG_CIFS_COMPRESSION is not set # CONFIG_SMB_SERVER is not set CONFIG_SMBFS=y # CONFIG_CODA_FS is not set @@ -5818,6 +5960,7 @@ CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y CONFIG_INIT_STACK_NONE=y # CONFIG_INIT_STACK_ALL_PATTERN is not set # CONFIG_INIT_STACK_ALL_ZERO is not set +# CONFIG_GCC_PLUGIN_STACKLEAK is not set # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y @@ -5884,7 +6027,6 @@ CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m # CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set -# CONFIG_CRYPTO_SM2 is not set # CONFIG_CRYPTO_CURVE25519 is not set # end of Public-key cryptography @@ -5916,14 +6058,12 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_ARC4 is not set # CONFIG_CRYPTO_CHACHA20 is not set CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CFB=m CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_HCTR2 is not set # CONFIG_CRYPTO_KEYWRAP is not set # CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_OFB is not set # CONFIG_CRYPTO_PCBC is not set # CONFIG_CRYPTO_XTS is not set # end of Length-preserving ciphers and modes @@ -5994,7 +6134,9 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y -# CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE is not set +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 CONFIG_CRYPTO_KDF800108_CTR=y # end of Random number generation @@ -6070,7 +6212,6 @@ CONFIG_GENERIC_NET_UTILS=y CONFIG_CORDIC=m # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y -CONFIG_GENERIC_PCI_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y # @@ -6124,11 +6265,13 @@ CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y # CONFIG_XZ_DEC_X86 is not set # CONFIG_XZ_DEC_POWERPC is not set -# CONFIG_XZ_DEC_IA64 is not set # CONFIG_XZ_DEC_ARM is not set # CONFIG_XZ_DEC_ARMTHUMB is not set +CONFIG_XZ_DEC_ARM64=y # CONFIG_XZ_DEC_SPARC is not set +CONFIG_XZ_DEC_RISCV=y # CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_BCJ=y # CONFIG_XZ_DEC_TEST is not set CONFIG_GENERIC_ALLOCATOR=y CONFIG_REED_SOLOMON=y @@ -6140,14 +6283,16 @@ CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y -CONFIG_DMA_OPS=y +CONFIG_DMA_OPS_HELPERS=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_DMA_NEED_SYNC=y CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_ARCH_HAS_DMA_ALLOC=y CONFIG_DMA_CMA=y # @@ -6170,6 +6315,7 @@ CONFIG_NLATTR=y CONFIG_CLZ_TAB=y # CONFIG_IRQ_POLL is not set CONFIG_MPILIB=y +CONFIG_DIMLIB=y CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_HAVE_GENERIC_VDSO=y @@ -6182,7 +6328,9 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y +CONFIG_STACKDEPOT_MAX_FRAMES=64 CONFIG_SBITMAP=y +# CONFIG_LWQ_TEST is not set # end of Library routines CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y @@ -6213,7 +6361,7 @@ CONFIG_DEBUG_MISC=y # # Compile-time checks and compiler options # -CONFIG_AS_HAS_NON_CONST_LEB128=y +CONFIG_AS_HAS_NON_CONST_ULEB128=y CONFIG_DEBUG_INFO_NONE=y # CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set # CONFIG_DEBUG_INFO_DWARF4 is not set @@ -6243,7 +6391,7 @@ CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +CONFIG_ARCH_HAS_UBSAN=y # CONFIG_UBSAN is not set CONFIG_HAVE_KCSAN_COMPILER=y # end of Generic Kernel Debugging Instruments @@ -6267,9 +6415,9 @@ CONFIG_SLUB_DEBUG=y # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_PAGE_REF is not set # CONFIG_DEBUG_RODATA_TEST is not set -# CONFIG_DEBUG_WX is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_PER_VMA_LOCK_STATS is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SHRINKER_DEBUG is not set # CONFIG_DEBUG_STACK_USAGE is not set @@ -6279,6 +6427,7 @@ CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y @@ -6433,6 +6582,7 @@ CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT=y # arm Debugging # # CONFIG_ARM_PTDUMP_DEBUGFS is not set +# CONFIG_ARM_DEBUG_WX is not set CONFIG_UNWINDER_FRAME_POINTER=y # CONFIG_UNWINDER_ARM is not set # CONFIG_BACKTRACE_VERBOSE is not set diff --git a/projects/RPi/devices/RPi4/linux/linux.aarch64.conf b/projects/RPi/devices/RPi4/linux/linux.aarch64.conf index 3707d6245d..bc216a5430 100644 --- a/projects/RPi/devices/RPi4/linux/linux.aarch64.conf +++ b/projects/RPi/devices/RPi4/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.6.59 Kernel Configuration +# Linux/arm64 6.12.0-rc7 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GCC) 13.0.0 20220604 (experimental) [master revision aec868578d8515763d75693c1fdfbc30ff0a1e68]" CONFIG_CC_IS_GCC=y @@ -11,11 +11,11 @@ CONFIG_AS_VERSION=23850 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23850 CONFIG_LLD_VERSION=0 +CONFIG_RUSTC_VERSION=0 +CONFIG_RUSTC_LLVM_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y -CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y -CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y +CONFIG_GCC_ASM_GOTO_OUTPUT_BROKEN=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=0 @@ -101,6 +101,7 @@ CONFIG_PREEMPT_VOLUNTARY_BUILD=y # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set +# CONFIG_PREEMPT_RT is not set # CONFIG_PREEMPT_DYNAMIC is not set # @@ -123,6 +124,7 @@ CONFIG_TREE_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU_GENERIC=y +CONFIG_NEED_TASKS_RCU=y CONFIG_TASKS_RUDE_RCU=y CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y @@ -148,16 +150,20 @@ CONFIG_CC_HAS_INT128=y CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_GCC10_NO_ARRAY_BOUNDS=y CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_GCC_NO_STRINGOP_OVERFLOW=y +CONFIG_CC_NO_STRINGOP_OVERFLOW=y CONFIG_ARCH_SUPPORTS_INT128=y # CONFIG_NUMA_BALANCING is not set +CONFIG_SLAB_OBJ_EXT=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y # CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y -CONFIG_MEMCG_KMEM=y +# CONFIG_MEMCG_V1 is not set CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y CONFIG_CGROUP_SCHED=y +CONFIG_GROUP_SCHED_WEIGHT=y CONFIG_FAIR_GROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y # CONFIG_RT_GROUP_SCHED is not set @@ -166,6 +172,7 @@ CONFIG_CGROUP_PIDS=y # CONFIG_CGROUP_RDMA is not set CONFIG_CGROUP_FREEZER=y CONFIG_CPUSETS=y +# CONFIG_CPUSETS_V1 is not set CONFIG_PROC_PID_CPUSET=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y @@ -217,7 +224,7 @@ CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y +# CONFIG_BASE_SMALL is not set CONFIG_FUTEX=y CONFIG_FUTEX_PI=y CONFIG_EPOLL=y @@ -229,17 +236,16 @@ CONFIG_AIO=y CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y +CONFIG_KCMP=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +CONFIG_CACHESTAT_SYSCALL=y +# CONFIG_PC104 is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_SELFTEST is not set # CONFIG_KALLSYMS_ALL is not set -CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -CONFIG_KCMP=y -CONFIG_RSEQ=y -CONFIG_CACHESTAT_SYSCALL=y -# CONFIG_DEBUG_RSEQ is not set CONFIG_HAVE_PERF_EVENTS=y -# CONFIG_PC104 is not set # # Kernel Performance Events And Counters @@ -256,15 +262,14 @@ CONFIG_TRACEPOINTS=y # Kexec and crash features # # CONFIG_KEXEC_FILE is not set -# CONFIG_CRASH_DUMP is not set # end of Kexec and crash features # end of General setup CONFIG_ARM64=y +CONFIG_RUSTC_SUPPORTS_ARM64=y CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_64BIT=y CONFIG_MMU=y -CONFIG_ARM64_PAGE_SHIFT=12 CONFIG_ARM64_CONT_PTE_SHIFT=4 CONFIG_ARM64_CONT_PMD_SHIFT=4 CONFIG_ARCH_MMAP_RND_BITS_MIN=18 @@ -291,6 +296,7 @@ CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y # Platform selection # # CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_AIROHA is not set # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_ALPINE is not set # CONFIG_ARCH_APPLE is not set @@ -313,6 +319,7 @@ CONFIG_ARCH_BCM2835=y # CONFIG_ARCH_NXP is not set # CONFIG_ARCH_MA35 is not set # CONFIG_ARCH_NPCM is not set +# CONFIG_ARCH_PENSANDO is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_RENESAS is not set @@ -397,6 +404,7 @@ CONFIG_ARM64_4K_PAGES=y # CONFIG_ARM64_64K_PAGES is not set CONFIG_ARM64_VA_BITS_39=y # CONFIG_ARM64_VA_BITS_48 is not set +# CONFIG_ARM64_VA_BITS_52 is not set CONFIG_ARM64_VA_BITS=39 CONFIG_ARM64_PA_BITS_48=y CONFIG_ARM64_PA_BITS=48 @@ -409,7 +417,6 @@ CONFIG_NR_CPUS=256 # CONFIG_HOTPLUG_CPU is not set CONFIG_NUMA=y CONFIG_NODES_SHIFT=4 -CONFIG_NUMA_EMULATION=y # CONFIG_HZ_100 is not set # CONFIG_HZ_250 is not set CONFIG_HZ_300=y @@ -498,8 +505,14 @@ CONFIG_ARM64_MTE=y CONFIG_ARM64_EPAN=y # end of ARMv8.7 architectural features +# +# ARMv8.9 architectural features +# +CONFIG_ARM64_POE=y +CONFIG_ARCH_PKEY_BITS=3 +# end of ARMv8.9 architectural features + CONFIG_ARM64_SVE=y -CONFIG_ARM64_SME=y # CONFIG_ARM64_PSEUDO_NMI is not set CONFIG_RELOCATABLE=y # CONFIG_RANDOMIZE_BASE is not set @@ -513,6 +526,7 @@ CONFIG_STACKPROTECTOR_PER_TASK=y CONFIG_CMDLINE="" CONFIG_EFI_STUB=y CONFIG_EFI=y +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_DMI=y # end of Boot options @@ -583,7 +597,6 @@ CONFIG_ARM_RASPBERRYPI_CPUFREQ=y CONFIG_ARCH_SUPPORTS_ACPI=y # CONFIG_ACPI is not set -CONFIG_HAVE_KVM=y # CONFIG_VIRTUALIZATION is not set CONFIG_CPU_MITIGATIONS=y @@ -617,6 +630,7 @@ CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_RUST=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_PERF_REGS=y @@ -658,6 +672,7 @@ CONFIG_HAVE_ARCH_HUGE_VMALLOC=y CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_WANTS_EXECMEM_LATE=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y @@ -665,13 +680,17 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_HAVE_PAGE_SIZE_4KB=y +CONFIG_PAGE_SIZE_4KB=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SHIFT=12 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_COMPAT_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y +CONFIG_ARCH_SUPPORTS_RT=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y @@ -686,12 +705,15 @@ CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y CONFIG_ARCH_USE_MEMREMAP_PROT=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_HAS_RELR=y +CONFIG_ARCH_HAS_MEM_ENCRYPT=y CONFIG_HAVE_PREEMPT_DYNAMIC=y CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y +CONFIG_ARCH_HAS_HW_PTE_YOUNG=y +CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT=y # # GCOV-based kernel profiling @@ -709,7 +731,6 @@ CONFIG_FUNCTION_ALIGNMENT=8 # end of General architecture-dependent options CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_DEBUG is not set # CONFIG_MODULE_FORCE_LOAD is not set @@ -719,10 +740,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set -CONFIG_MODULE_COMPRESS_NONE=y -# CONFIG_MODULE_COMPRESS_GZIP is not set -# CONFIG_MODULE_COMPRESS_XZ is not set -# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_COMPRESS is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set @@ -735,9 +753,9 @@ CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_ICQ=y CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_DEV_INTEGRITY is not set +CONFIG_BLK_DEV_WRITE_MOUNTED=y # CONFIG_BLK_DEV_ZONED is not set CONFIG_BLK_DEV_THROTTLING=y -# CONFIG_BLK_DEV_THROTTLING_LOW is not set # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_IOCOST is not set @@ -873,18 +891,18 @@ CONFIG_SWAP=y # CONFIG_ZSWAP is not set # -# SLAB allocator options +# Slab allocator options # -# CONFIG_SLAB_DEPRECATED is not set CONFIG_SLUB=y # CONFIG_SLUB_TINY is not set CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_FREELIST_HARDENED is not set +CONFIG_SLAB_BUCKETS=y # CONFIG_SLUB_STATS is not set CONFIG_SLUB_CPU_PARTIAL=y # CONFIG_RANDOM_KMALLOC_CACHES is not set -# end of SLAB allocator options +# end of Slab allocator options # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set # CONFIG_COMPAT_BRK is not set @@ -892,7 +910,7 @@ CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_HAVE_FAST_GUP=y +CONFIG_HAVE_GUP_FAST=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y CONFIG_EXCLUSIVE_SYSTEM_RAM=y @@ -900,8 +918,9 @@ CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y # CONFIG_MEMORY_HOTPLUG is not set CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_SPLIT_PTE_PTLOCKS=y CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_SPLIT_PMD_PTLOCKS=y CONFIG_COMPACTION=y CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 # CONFIG_PAGE_REPORTING is not set @@ -920,7 +939,6 @@ CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y CONFIG_USE_PERCPU_NUMA_NODE_ID=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_CMA=y -# CONFIG_CMA_DEBUG is not set CONFIG_CMA_DEBUGFS=y # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 @@ -934,7 +952,9 @@ CONFIG_ARCH_HAS_ZONE_DMA_SET=y CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y -CONFIG_ARCH_USES_PG_ARCH_X=y +CONFIG_ARCH_HAS_PKEYS=y +CONFIG_ARCH_USES_PG_ARCH_2=y +CONFIG_ARCH_USES_PG_ARCH_3=y CONFIG_VM_EVENT_COUNTERS=y # CONFIG_PERCPU_STATS is not set # CONFIG_GUP_TEST is not set @@ -947,9 +967,13 @@ CONFIG_SECRETMEM=y CONFIG_LRU_GEN=y # CONFIG_LRU_GEN_ENABLED is not set # CONFIG_LRU_GEN_STATS is not set +CONFIG_LRU_GEN_WALKS_MMU=y CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y CONFIG_PER_VMA_LOCK=y CONFIG_LOCK_MM_AND_FIND_VMA=y +CONFIG_EXECMEM=y +CONFIG_NUMA_MEMBLKS=y +CONFIG_NUMA_EMU=y # # Data Access Monitoring @@ -964,6 +988,7 @@ CONFIG_NET_INGRESS=y CONFIG_NET_EGRESS=y CONFIG_NET_XGRESS=y CONFIG_SKB_EXTENSIONS=y +CONFIG_NET_DEVMEM=y # # Networking options @@ -971,7 +996,6 @@ CONFIG_SKB_EXTENSIONS=y CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y -CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set @@ -1038,6 +1062,7 @@ CONFIG_TCP_CONG_CDG=m CONFIG_DEFAULT_CUBIC=y # CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_AO is not set # CONFIG_TCP_MD5SIG is not set CONFIG_IPV6=y # CONFIG_IPV6_ROUTER_PREF is not set @@ -1251,6 +1276,7 @@ CONFIG_IP_VS_NFCT=y # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=m +CONFIG_IP_NF_IPTABLES_LEGACY=m # CONFIG_NF_SOCKET_IPV4 is not set # CONFIG_NF_TPROXY_IPV4 is not set # CONFIG_NF_DUP_IPV4 is not set @@ -1273,12 +1299,13 @@ CONFIG_IP_NF_MANGLE=m # CONFIG_IP_NF_TARGET_ECN is not set # CONFIG_IP_NF_TARGET_TTL is not set # CONFIG_IP_NF_RAW is not set -# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_ARPFILTER is not set # end of IP: Netfilter Configuration # # IPv6: Netfilter Configuration # +CONFIG_IP6_NF_IPTABLES_LEGACY=m # CONFIG_NF_SOCKET_IPV6 is not set # CONFIG_NF_TPROXY_IPV6 is not set # CONFIG_NF_DUP_IPV6 is not set @@ -1309,7 +1336,6 @@ CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_NF_DEFRAG_IPV6=m # CONFIG_NF_CONNTRACK_BRIDGE is not set # CONFIG_BRIDGE_NF_EBTABLES is not set -# CONFIG_BPFILTER is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set # CONFIG_RDS is not set @@ -1462,6 +1488,7 @@ CONFIG_BT_HCIUART_BCM=y # CONFIG_BT_HCIUART_QCA is not set # CONFIG_BT_HCIUART_AG6XX is not set # CONFIG_BT_HCIUART_MRVL is not set +# CONFIG_BT_HCIUART_AML is not set CONFIG_BT_HCIBCM203X=m # CONFIG_BT_HCIBCM4377 is not set # CONFIG_BT_HCIBPA10X is not set @@ -1472,6 +1499,7 @@ CONFIG_BT_ATH3K=m # CONFIG_BT_MTKSDIO is not set # CONFIG_BT_MTKUART is not set # CONFIG_BT_NXPUART is not set +# CONFIG_BT_INTEL_PCIE is not set # end of Bluetooth device drivers # CONFIG_AF_RXRPC is not set @@ -1500,7 +1528,6 @@ CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" # CONFIG_MAC80211_MESH is not set CONFIG_MAC80211_LEDS=y -# CONFIG_MAC80211_DEBUGFS is not set # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 @@ -1529,6 +1556,7 @@ CONFIG_ETHTOOL_NETLINK=y # CONFIG_ARM_AMBA=y CONFIG_HAVE_PCI=y +CONFIG_GENERIC_PCI_IOMAP=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_DOMAINS_GENERIC=y @@ -1546,6 +1574,7 @@ CONFIG_PCI_QUIRKS=y # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCI_IOV is not set +# CONFIG_PCI_NPEM is not set # CONFIG_PCI_PRI is not set # CONFIG_PCI_PASID is not set CONFIG_PCI_LABEL=y @@ -1568,7 +1597,6 @@ CONFIG_PCIE_BRCMSTB=y # CONFIG_PCI_HOST_THUNDER_ECAM is not set # CONFIG_PCI_FTPCI100 is not set # CONFIG_PCI_HOST_GENERIC is not set -# CONFIG_PCIE_MICROCHIP_HOST is not set # CONFIG_PCI_XGENE is not set # CONFIG_PCIE_XILINX is not set @@ -1576,7 +1604,6 @@ CONFIG_PCIE_BRCMSTB=y # Cadence-based PCIe controllers # # CONFIG_PCIE_CADENCE_PLAT_HOST is not set -# CONFIG_PCI_J721E_HOST is not set # end of Cadence-based PCIe controllers # @@ -1593,6 +1620,12 @@ CONFIG_PCIE_BRCMSTB=y # Mobiveil-based PCIe controllers # # end of Mobiveil-based PCIe controllers + +# +# PLDA-based PCIe controllers +# +# CONFIG_PCIE_MICROCHIP_HOST is not set +# end of PLDA-based PCIe controllers # end of PCI controller drivers # @@ -1638,6 +1671,7 @@ CONFIG_WANT_DEV_COREDUMP=y # CONFIG_DEBUG_DEVRES is not set # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_DEVICES=y CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_SOC_BUS=y @@ -1650,14 +1684,12 @@ CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set CONFIG_GENERIC_ARCH_TOPOLOGY=y CONFIG_GENERIC_ARCH_NUMA=y -CONFIG_GENERIC_ARCH_NUMA_EMULATION=y # CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set # end of Generic Driver Options # # Bus devices # -# CONFIG_BRCMSTB_GISB_ARB is not set # CONFIG_MOXTET is not set # CONFIG_VEXPRESS_CONFIG is not set # CONFIG_MHI_BUS is not set @@ -1713,6 +1745,12 @@ CONFIG_EFI_EARLYCON=y # end of EFI (Extensible Firmware Interface) Support CONFIG_ARM_PSCI_FW=y + +# +# Qualcomm firmware drivers +# +# end of Qualcomm firmware drivers + CONFIG_HAVE_ARM_SMCCC=y CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y CONFIG_ARM_SMCCC_SOC_ID=y @@ -1745,6 +1783,7 @@ CONFIG_BLK_DEV=y CONFIG_CDROM=y # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set # CONFIG_ZRAM is not set +CONFIG_ZRAM_DEF_COMP="unset-value" CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 # CONFIG_BLK_DEV_DRBD is not set @@ -1767,7 +1806,7 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_NVME_HWMON is not set # CONFIG_NVME_FC is not set # CONFIG_NVME_TCP is not set -# CONFIG_NVME_AUTH is not set +# CONFIG_NVME_HOST_AUTH is not set # CONFIG_NVME_TARGET is not set # end of NVME Support @@ -1778,6 +1817,7 @@ CONFIG_BCM2835_SMI=m # CONFIG_AD525X_DPOT is not set # CONFIG_DUMMY_IRQ is not set # CONFIG_PHANTOM is not set +# CONFIG_RPMB is not set # CONFIG_TIFM_CORE is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set @@ -1805,7 +1845,6 @@ CONFIG_MISC_RTSX=y # # CONFIG_EEPROM_AT24 is not set # CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set # CONFIG_EEPROM_MAX6875 is not set CONFIG_EEPROM_93CX6=m # CONFIG_EEPROM_93XX46 is not set @@ -1833,6 +1872,7 @@ CONFIG_EEPROM_93CX6=m CONFIG_MISC_RTSX_USB=y # CONFIG_PVPANIC is not set # CONFIG_GP_PCI1XXXX is not set +# CONFIG_KEBA_CP500 is not set # end of Misc devices # @@ -1954,6 +1994,7 @@ CONFIG_DM_THIN_PROVISIONING=m # CONFIG_DM_SWITCH is not set # CONFIG_DM_LOG_WRITES is not set # CONFIG_DM_INTEGRITY is not set +# CONFIG_DM_VDO is not set # CONFIG_TARGET_CORE is not set # CONFIG_FUSION is not set @@ -1983,6 +2024,7 @@ CONFIG_VXLAN=m # CONFIG_GENEVE is not set # CONFIG_BAREUDP is not set # CONFIG_GTP is not set +# CONFIG_PFCP is not set # CONFIG_AMT is not set # CONFIG_MACSEC is not set CONFIG_NETCONSOLE=y @@ -1994,6 +2036,7 @@ CONFIG_TUN=y # CONFIG_TUN_VNET_CROSS_LE is not set CONFIG_VETH=m CONFIG_NLMON=m +# CONFIG_NETKIT is not set # CONFIG_NET_VRF is not set # CONFIG_ARCNET is not set CONFIG_ETHERNET=y @@ -2095,6 +2138,7 @@ CONFIG_NET_VENDOR_INTEL=y # CONFIG_ICE is not set # CONFIG_FM10K is not set # CONFIG_IGC is not set +# CONFIG_IDPF is not set # CONFIG_JME is not set CONFIG_NET_VENDOR_ADI=y CONFIG_NET_VENDOR_LITEX=y @@ -2106,11 +2150,13 @@ CONFIG_NET_VENDOR_MARVELL=y # CONFIG_OCTEONTX2_AF is not set # CONFIG_OCTEONTX2_PF is not set # CONFIG_OCTEON_EP is not set +# CONFIG_OCTEON_EP_VF is not set CONFIG_NET_VENDOR_MELLANOX=y # CONFIG_MLX4_EN is not set # CONFIG_MLX5_CORE is not set # CONFIG_MLXSW_CORE is not set # CONFIG_MLXFW is not set +CONFIG_NET_VENDOR_META=y CONFIG_NET_VENDOR_MICREL=y # CONFIG_KS8842 is not set # CONFIG_KS8851 is not set @@ -2120,6 +2166,7 @@ CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set # CONFIG_LAN743X is not set +# CONFIG_LAN865X is not set # CONFIG_VCAP is not set CONFIG_NET_VENDOR_MICROSEMI=y CONFIG_NET_VENDOR_MICROSOFT=y @@ -2141,6 +2188,7 @@ CONFIG_NET_VENDOR_NVIDIA=y # CONFIG_FORCEDETH is not set CONFIG_NET_VENDOR_OKI=y # CONFIG_ETHOC is not set +# CONFIG_OA_TC6 is not set CONFIG_NET_VENDOR_PACKET_ENGINES=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set @@ -2163,6 +2211,7 @@ CONFIG_NET_VENDOR_REALTEK=y # CONFIG_8139CP is not set # CONFIG_8139TOO is not set # CONFIG_R8169 is not set +# CONFIG_RTASE is not set CONFIG_NET_VENDOR_RENESAS=y CONFIG_NET_VENDOR_ROCKER=y CONFIG_NET_VENDOR_SAMSUNG=y @@ -2193,6 +2242,7 @@ CONFIG_NET_VENDOR_SYNOPSYS=y # CONFIG_DWC_XLGMAC is not set CONFIG_NET_VENDOR_TEHUTI=y # CONFIG_TEHUTI is not set +# CONFIG_TEHUTI_TN40 is not set CONFIG_NET_VENDOR_TI=y # CONFIG_TI_CPSW_PHY_SEL is not set # CONFIG_TLAN is not set @@ -2203,13 +2253,11 @@ CONFIG_NET_VENDOR_VIA=y # CONFIG_VIA_VELOCITY is not set CONFIG_NET_VENDOR_WANGXUN=y # CONFIG_NGBE is not set -# CONFIG_TXGBE is not set CONFIG_NET_VENDOR_WIZNET=y # CONFIG_WIZNET_W5100 is not set # CONFIG_WIZNET_W5300 is not set CONFIG_NET_VENDOR_XILINX=y # CONFIG_XILINX_EMACLITE is not set -# CONFIG_XILINX_AXI_EMAC is not set # CONFIG_XILINX_LL_TEMAC is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set @@ -2224,6 +2272,7 @@ CONFIG_FIXED_PHY=y # # MII PHY device drivers # +# CONFIG_AIR_EN8811H_PHY is not set # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set # CONFIG_ADIN1100_PHY is not set @@ -2260,6 +2309,9 @@ CONFIG_MICROCHIP_PHY=y # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_NCN26000_PHY is not set # CONFIG_AT803X_PHY is not set +# CONFIG_QCA83XX_PHY is not set +# CONFIG_QCA808X_PHY is not set +# CONFIG_QCA807X_PHY is not set # CONFIG_QSEMI_PHY is not set # CONFIG_REALTEK_PHY is not set # CONFIG_RENESAS_PHY is not set @@ -2273,6 +2325,7 @@ CONFIG_SMSC_PHY=y # CONFIG_DP83867_PHY is not set # CONFIG_DP83869_PHY is not set # CONFIG_DP83TD510_PHY is not set +# CONFIG_DP83TG720_PHY is not set # CONFIG_VITESSE_PHY is not set # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set @@ -2302,6 +2355,7 @@ CONFIG_MDIO_BCM_UNIMAC=y # # PCS device drivers # +# CONFIG_PCS_XPCS is not set # end of PCS device drivers CONFIG_PPP=m @@ -2372,7 +2426,6 @@ CONFIG_ATH9K_BTCOEX_SUPPORT=y CONFIG_ATH9K=m CONFIG_ATH9K_PCI=y CONFIG_ATH9K_AHB=y -# CONFIG_ATH9K_DEBUGFS is not set # CONFIG_ATH9K_DYNACK is not set # CONFIG_ATH9K_WOW is not set CONFIG_ATH9K_RFKILL=y @@ -2396,8 +2449,9 @@ CONFIG_AR5523=m # CONFIG_ATH10K is not set CONFIG_WCN36XX=m # CONFIG_WCN36XX_DEBUGFS is not set +# CONFIG_ATH11K is not set +# CONFIG_ATH12K is not set CONFIG_WLAN_VENDOR_ATMEL=y -# CONFIG_ATMEL is not set # CONFIG_AT76C50X_USB is not set CONFIG_WLAN_VENDOR_BROADCOM=y CONFIG_B43=m @@ -2428,8 +2482,6 @@ CONFIG_BRCMFMAC_USB=y # CONFIG_BRCMFMAC_PCIE is not set # CONFIG_BRCM_TRACING is not set CONFIG_BRCMDBG=y -CONFIG_WLAN_VENDOR_CISCO=y -# CONFIG_AIRO is not set CONFIG_WLAN_VENDOR_INTEL=y # CONFIG_IPW2100 is not set # CONFIG_IPW2200 is not set @@ -2437,8 +2489,6 @@ CONFIG_WLAN_VENDOR_INTEL=y # CONFIG_IWL3945 is not set # CONFIG_IWLWIFI is not set CONFIG_WLAN_VENDOR_INTERSIL=y -# CONFIG_HOSTAP is not set -# CONFIG_HERMES is not set CONFIG_P54_COMMON=m CONFIG_P54_USB=m # CONFIG_P54_PCI is not set @@ -2477,6 +2527,8 @@ CONFIG_MT7921_COMMON=m # CONFIG_MT7921S is not set CONFIG_MT7921U=m # CONFIG_MT7996E is not set +# CONFIG_MT7925E is not set +# CONFIG_MT7925U is not set CONFIG_WLAN_VENDOR_MICROCHIP=y # CONFIG_WILC1000_SDIO is not set # CONFIG_WILC1000_SPI is not set @@ -2544,6 +2596,7 @@ CONFIG_RTW88_8822BU=m CONFIG_RTW88_8822CU=m # CONFIG_RTW88_8723DE is not set # CONFIG_RTW88_8723DS is not set +# CONFIG_RTW88_8723CS is not set CONFIG_RTW88_8723DU=m # CONFIG_RTW88_8821CE is not set # CONFIG_RTW88_8821CS is not set @@ -2565,11 +2618,9 @@ CONFIG_WLAN_VENDOR_TI=y # CONFIG_WL18XX is not set # CONFIG_WLCORE is not set CONFIG_WLAN_VENDOR_ZYDAS=y -CONFIG_USB_ZD1201=m CONFIG_ZD1211RW=m # CONFIG_ZD1211RW_DEBUG is not set # CONFIG_WLAN_VENDOR_QUANTENNA is not set -CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_MAC80211_HWSIM is not set # CONFIG_VIRT_WIFI is not set # CONFIG_WAN is not set @@ -2625,7 +2676,6 @@ CONFIG_KEYBOARD_GPIO=m # CONFIG_KEYBOARD_LM8323 is not set # CONFIG_KEYBOARD_LM8333 is not set # CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_MCS is not set # CONFIG_KEYBOARD_MPR121 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set @@ -2671,6 +2721,7 @@ CONFIG_JOYSTICK_PSXPAD_SPI_FF=y # CONFIG_JOYSTICK_QWIIC is not set # CONFIG_JOYSTICK_FSIA6B is not set # CONFIG_JOYSTICK_SENSEHAT is not set +# CONFIG_JOYSTICK_SEESAW is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=m @@ -2685,7 +2736,6 @@ CONFIG_TOUCHSCREEN_ADS7846=m # CONFIG_TOUCHSCREEN_CY8CTMA140 is not set # CONFIG_TOUCHSCREEN_CY8CTMG110 is not set # CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set -# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set # CONFIG_TOUCHSCREEN_CYTTSP5 is not set # CONFIG_TOUCHSCREEN_DYNAPRO is not set # CONFIG_TOUCHSCREEN_HAMPSHIRE is not set @@ -2695,6 +2745,8 @@ CONFIG_TOUCHSCREEN_EGALAX=m # CONFIG_TOUCHSCREEN_EXC3000 is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI is not set # CONFIG_TOUCHSCREEN_HIDEEP is not set # CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set # CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set @@ -2708,7 +2760,6 @@ CONFIG_TOUCHSCREEN_EGALAX=m # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set # CONFIG_TOUCHSCREEN_WACOM_I2C is not set # CONFIG_TOUCHSCREEN_MAX11801 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set # CONFIG_TOUCHSCREEN_MMS114 is not set # CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set # CONFIG_TOUCHSCREEN_MSG2638 is not set @@ -2840,7 +2891,6 @@ CONFIG_TTY=y CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set @@ -2936,7 +2986,6 @@ CONFIG_RASPBERRYPI_GPIOMEM=y # CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y -# CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y @@ -2990,8 +3039,7 @@ CONFIG_I2C_BCM2835=y CONFIG_I2C_BRCMSTB=y # CONFIG_I2C_CADENCE is not set # CONFIG_I2C_CBUS_GPIO is not set -# CONFIG_I2C_DESIGNWARE_PLATFORM is not set -# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_DESIGNWARE_CORE is not set # CONFIG_I2C_EMEV2 is not set CONFIG_I2C_GPIO=y # CONFIG_I2C_GPIO_FAULT_INJECTOR is not set @@ -3044,6 +3092,7 @@ CONFIG_SPI_BCM2835AUX=m # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_DESIGNWARE is not set # CONFIG_SPI_GPIO is not set # CONFIG_SPI_FSL_SPI is not set @@ -3052,7 +3101,6 @@ CONFIG_SPI_BCM2835AUX=m # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_PCI1XXXX is not set # CONFIG_SPI_PL022 is not set -# CONFIG_SPI_PXA2XX is not set # CONFIG_SPI_RP2040_GPIO_BRIDGE is not set # CONFIG_SPI_SC18IS602 is not set # CONFIG_SPI_SIFIVE is not set @@ -3095,6 +3143,7 @@ CONFIG_PINMUX=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_AW9523 is not set # CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_MCP23S08 is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set @@ -3203,16 +3252,25 @@ CONFIG_GPIO_FSM=m # CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers +# +# GPIO Debugging utilities +# +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set +# CONFIG_GPIO_VIRTUSER is not set +# end of GPIO Debugging utilities + CONFIG_W1=m # # 1-wire Bus Masters # +# CONFIG_W1_MASTER_AMD_AXI is not set # CONFIG_W1_MASTER_MATROX is not set # CONFIG_W1_MASTER_DS2490 is not set # CONFIG_W1_MASTER_DS2482 is not set CONFIG_W1_MASTER_GPIO=m # CONFIG_W1_MASTER_SGI is not set +# CONFIG_W1_MASTER_UART is not set # end of 1-wire Bus Masters # @@ -3238,7 +3296,6 @@ CONFIG_W1_SLAVE_THERM=m # end of 1-wire Slaves CONFIG_POWER_RESET=y -# CONFIG_POWER_RESET_BRCMSTB is not set CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_GPIO_RESTART=y # CONFIG_POWER_RESET_LTC2952 is not set @@ -3249,6 +3306,7 @@ CONFIG_POWER_RESET_RESTART=y # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_SYSCON_REBOOT_MODE is not set # CONFIG_NVMEM_REBOOT_MODE is not set +# CONFIG_POWER_SEQUENCING is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y @@ -3266,8 +3324,8 @@ CONFIG_RPI_POE_POWER=m # CONFIG_CHARGER_SBS is not set # CONFIG_MANAGER_SBS is not set # CONFIG_BATTERY_BQ27XXX is not set -# CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_MAX1721X is not set # CONFIG_CHARGER_ISP1704 is not set # CONFIG_CHARGER_MAX8903 is not set @@ -3296,6 +3354,7 @@ CONFIG_RPI_POE_POWER=m # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set # CONFIG_BATTERY_UG3105 is not set +# CONFIG_FUEL_GAUGE_MM8013 is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set @@ -3305,7 +3364,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AD7314 is not set # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set @@ -3322,8 +3380,10 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CHIPCAP2 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set # CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DS620 is not set @@ -3333,6 +3393,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_F75375S is not set # CONFIG_SENSORS_FTSTEUTATES is not set +# CONFIG_SENSORS_GIGABYTE_WATERFORCE is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_G760A is not set @@ -3342,12 +3403,14 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_HS3001 is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWERZ is not set # CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LINEAGE is not set # CONFIG_SENSORS_LTC2945 is not set # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2991 is not set # CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set @@ -3355,6 +3418,7 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LTC4282 is not set # CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set @@ -3368,7 +3432,6 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_MAX6620 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_MAX6697 is not set # CONFIG_SENSORS_MAX31790 is not set @@ -3403,10 +3466,12 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_KRAKEN3 is not set # CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set +# CONFIG_SENSORS_PT5161L is not set CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_RASPBERRYPI_HWMON=y # CONFIG_SENSORS_SBTSI is not set @@ -3436,6 +3501,7 @@ CONFIG_SENSORS_RASPBERRYPI_HWMON=y # CONFIG_SENSORS_INA2XX is not set # CONFIG_SENSORS_INA238 is not set # CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP102 is not set @@ -3461,10 +3527,11 @@ CONFIG_SENSORS_RASPBERRYPI_HWMON=y CONFIG_THERMAL=y # CONFIG_THERMAL_NETLINK is not set # CONFIG_THERMAL_STATISTICS is not set +# CONFIG_THERMAL_DEBUGFS is not set +# CONFIG_THERMAL_CORE_TESTING is not set CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y -# CONFIG_THERMAL_WRITABLE_TRIPS is not set CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set @@ -3553,6 +3620,7 @@ CONFIG_BCMA_DRIVER_GMAC_CMN=y # Multifunction device drivers # CONFIG_MFD_CORE=y +# CONFIG_MFD_ADP5585 is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_AS3711 is not set # CONFIG_MFD_SMPRO is not set @@ -3588,6 +3656,7 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_MAX14577 is not set # CONFIG_MFD_MAX77541 is not set # CONFIG_MFD_MAX77620 is not set @@ -3672,10 +3741,13 @@ CONFIG_MFD_WM5102=y # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set # CONFIG_MFD_ATC260X_I2C is not set # CONFIG_MFD_QCOM_PM8008 is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC_SPI is not set # CONFIG_MFD_RP1 is not set @@ -3688,6 +3760,7 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_NETLINK_EVENTS is not set # CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set @@ -3709,6 +3782,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_LTC3589 is not set # CONFIG_REGULATOR_LTC3676 is not set # CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX77503 is not set # CONFIG_REGULATOR_MAX77857 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set @@ -3845,7 +3919,6 @@ CONFIG_V4L2_ASYNC=m # Media controller options # CONFIG_MEDIA_CONTROLLER_DVB=y -CONFIG_MEDIA_CONTROLLER_REQUEST_API=y # end of Media controller options # @@ -3994,6 +4067,7 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # # Atmel media platform drivers # +# CONFIG_VIDEO_BCM2835_UNICAM_LEGACY is not set # CONFIG_VIDEO_BCM2835_UNICAM is not set # @@ -4022,6 +4096,10 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # Microchip Technology, Inc. media platform drivers # +# +# Nuvoton media platform drivers +# + # # NVidia media platform drivers # @@ -4112,7 +4190,12 @@ CONFIG_MEDIA_ATTACH=y # CONFIG_VIDEO_IR_I2C=m CONFIG_VIDEO_CAMERA_SENSOR=y +# CONFIG_VIDEO_ALVIUM_CSI2 is not set # CONFIG_VIDEO_AR0521 is not set +# CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set +# CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_ARDUCAM_64MP is not set # CONFIG_VIDEO_ARDUCAM_PIVARIETY is not set # CONFIG_VIDEO_HI556 is not set @@ -4123,6 +4206,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -4137,6 +4221,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_IMX708 is not set # CONFIG_VIDEO_MT9M001 is not set # CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9M114 is not set # CONFIG_VIDEO_MT9P031 is not set # CONFIG_VIDEO_MT9T112 is not set # CONFIG_VIDEO_MT9V011 is not set @@ -4182,10 +4267,16 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_S5C73M3 is not set # CONFIG_VIDEO_S5K5BAF is not set # CONFIG_VIDEO_S5K6A3 is not set -# CONFIG_VIDEO_ST_VGXY61 is not set +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set +# +# Camera ISPs +# +# CONFIG_VIDEO_THP7312 is not set +# end of Camera ISPs + # # Lens drivers # @@ -4257,6 +4348,7 @@ CONFIG_VIDEO_SAA711X=m # CONFIG_VIDEO_TVP5150 is not set # CONFIG_VIDEO_TVP7002 is not set # CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9900 is not set # CONFIG_VIDEO_TW9903 is not set # CONFIG_VIDEO_TW9906 is not set # CONFIG_VIDEO_TW9910 is not set @@ -4318,6 +4410,8 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_DS90UB913 is not set # CONFIG_VIDEO_DS90UB953 is not set # CONFIG_VIDEO_DS90UB960 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # end of Video serializers and deserializers # @@ -4545,13 +4639,13 @@ CONFIG_DVB_SP2=m # # Graphics support # -CONFIG_VIDEO_CMDLINE=y -CONFIG_VIDEO_NOMODESET=y +CONFIG_VIDEO=y # CONFIG_AUXDISPLAY is not set CONFIG_DRM=y CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DEBUG_MM is not set CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_PANIC is not set # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set # CONFIG_DRM_DEBUG_MODESET_LOCK is not set CONFIG_DRM_FBDEV_EMULATION=y @@ -4559,9 +4653,10 @@ CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set CONFIG_DRM_LOAD_EDID_FIRMWARE=y CONFIG_DRM_DISPLAY_HELPER=y +# CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set +# CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set CONFIG_DRM_DISPLAY_HDMI_HELPER=y -# CONFIG_DRM_DP_AUX_CHARDEV is not set -# CONFIG_DRM_DP_CEC is not set +CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER=y CONFIG_DRM_GEM_DMA_HELPER=y CONFIG_DRM_GEM_SHMEM_HELPER=y CONFIG_DRM_SCHED=y @@ -4586,6 +4681,7 @@ CONFIG_DRM_SCHED=y # CONFIG_DRM_RADEON is not set # CONFIG_DRM_AMDGPU is not set # CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_XE is not set # CONFIG_DRM_VGEM is not set # CONFIG_DRM_VKMS is not set # CONFIG_DRM_VMWGFX is not set @@ -4604,33 +4700,40 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_AUO_A030JTN01 is not set # CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set # CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set # CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set -# CONFIG_DRM_PANEL_DSI_CM is not set -# CONFIG_DRM_PANEL_LVDS is not set -CONFIG_DRM_PANEL_SIMPLE=y -# CONFIG_DRM_PANEL_EDP is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 is not set # CONFIG_DRM_PANEL_EBBG_FT8719 is not set # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_DSI_CM is not set +# CONFIG_DRM_PANEL_LVDS is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set +# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set # CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set +# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set # CONFIG_DRM_PANEL_JDI_R63452 is not set # CONFIG_DRM_PANEL_KHADAS_TS050 is not set # CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set -# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_LG_SW43408 is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set # CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set @@ -4639,8 +4742,8 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set # CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set # CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set -# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set # CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set # CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set @@ -4649,16 +4752,20 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set # CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set # CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set # CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set # CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set @@ -4673,15 +4780,18 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set # CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set # CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set +# CONFIG_DRM_PANEL_EDP is not set +CONFIG_DRM_PANEL_SIMPLE=y +# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set # CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set # CONFIG_DRM_PANEL_TPO_Y17P is not set # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set # CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set -# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN is not set # CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set # CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set @@ -4735,7 +4845,6 @@ CONFIG_DRM_TOSHIBA_TC358762=y CONFIG_DRM_V3D=y CONFIG_DRM_VC4=y CONFIG_DRM_VC4_HDMI_CEC=y -# CONFIG_DRM_LOONGSON is not set # CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_HISI_HIBMC is not set # CONFIG_DRM_HISI_KIRIN is not set @@ -4758,10 +4867,12 @@ CONFIG_DRM_VC4_HDMI_CEC=y # CONFIG_DRM_PL111 is not set # CONFIG_DRM_LIMA is not set # CONFIG_DRM_PANFROST is not set +# CONFIG_DRM_PANTHOR is not set # CONFIG_DRM_TIDSS is not set # CONFIG_DRM_GUD is not set # CONFIG_DRM_SSD130X is not set -# CONFIG_DRM_LEGACY is not set +# CONFIG_DRM_POWERVR is not set +# CONFIG_DRM_WERROR is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y # @@ -4771,7 +4882,6 @@ CONFIG_FB=y # CONFIG_FB_BCM2708 is not set # CONFIG_FB_CIRRUS is not set # CONFIG_FB_PM2 is not set -# CONFIG_FB_ARMCLCD is not set # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_ASILIANT is not set # CONFIG_FB_IMSTT is not set @@ -4815,10 +4925,9 @@ CONFIG_FB_SYS_FILLRECT=y CONFIG_FB_SYS_COPYAREA=y CONFIG_FB_SYS_IMAGEBLIT=y # CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_SYS_FOPS=y +CONFIG_FB_SYSMEM_FOPS=y CONFIG_FB_DEFERRED_IO=y CONFIG_FB_DMAMEM_HELPERS=y -CONFIG_FB_IOMEM_FOPS=y CONFIG_FB_SYSMEM_HELPERS=y CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y # CONFIG_FB_MODE_HELPERS is not set @@ -4843,15 +4952,18 @@ CONFIG_LCD_CLASS_DEVICE=m # CONFIG_LCD_OTM3225A is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set # CONFIG_BACKLIGHT_PWM is not set CONFIG_BACKLIGHT_RPI=y # CONFIG_BACKLIGHT_QCOM_WLED is not set # CONFIG_BACKLIGHT_ADP8860 is not set # CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set # CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_BACKLIGHT_MP3309C is not set CONFIG_BACKLIGHT_GPIO=y # CONFIG_BACKLIGHT_LV5207LP is not set # CONFIG_BACKLIGHT_BD6107 is not set @@ -4899,10 +5011,10 @@ CONFIG_SND_MAX_CARDS=32 # CONFIG_SND_SUPPORT_OLD_API is not set CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set # CONFIG_SND_CTL_INPUT_VALIDATION is not set +# CONFIG_SND_UTIMER is not set CONFIG_SND_VMASTER=y # CONFIG_SND_SEQUENCER is not set # CONFIG_SND_DRIVERS is not set @@ -5106,6 +5218,7 @@ CONFIG_SND_SOC_ADAU7002=m # CONFIG_SND_SOC_AK4458 is not set CONFIG_SND_SOC_AK4554=m # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -5113,6 +5226,8 @@ CONFIG_SND_SOC_AK4554=m # CONFIG_SND_SOC_AW8738 is not set # CONFIG_SND_SOC_AW88395 is not set # CONFIG_SND_SOC_AW88261 is not set +# CONFIG_SND_SOC_AW87390 is not set +# CONFIG_SND_SOC_AW88399 is not set # CONFIG_SND_SOC_BD28623 is not set # CONFIG_SND_SOC_BT_SCO is not set # CONFIG_SND_SOC_CHV3_CODEC is not set @@ -5145,12 +5260,14 @@ CONFIG_SND_SOC_CS42XX8_I2C=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set # CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CX2072X is not set CONFIG_SND_SOC_DA7213=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8326 is not set # CONFIG_SND_SOC_ES8328_I2C is not set @@ -5159,7 +5276,6 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_HDA is not set # CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_IDT821034 is not set -# CONFIG_SND_SOC_INNO_RK3036 is not set CONFIG_SND_SOC_MA120X0P=m # CONFIG_SND_SOC_MAX98088 is not set # CONFIG_SND_SOC_MAX98090 is not set @@ -5190,14 +5306,15 @@ CONFIG_SND_SOC_PCM5102A=m CONFIG_SND_SOC_PCM512x=m CONFIG_SND_SOC_PCM512x_I2C=m # CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_PCM6240 is not set # CONFIG_SND_SOC_PEB2466 is not set -# CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RT5616 is not set CONFIG_SND_SOC_PCM1794A=m # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5640 is not set # CONFIG_SND_SOC_RT5659 is not set # CONFIG_SND_SOC_RT9120 is not set +# CONFIG_SND_SOC_RTQ9128 is not set CONFIG_SND_SOC_SGTL5000=m CONFIG_SND_SOC_SIGMADSP=m CONFIG_SND_SOC_SIGMADSP_I2C=m @@ -5277,6 +5394,7 @@ CONFIG_SND_SOC_WM8960=m # CONFIG_SND_SOC_ZL38060 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6357 is not set # CONFIG_SND_SOC_MT6358 is not set # CONFIG_SND_SOC_MT6660 is not set # CONFIG_SND_SOC_NAU8315 is not set @@ -5341,6 +5459,7 @@ CONFIG_HID_EZKEY=y # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set # CONFIG_HID_HOLTEK is not set +# CONFIG_HID_GOODIX_SPI is not set # CONFIG_HID_GOOGLE_STADIA_FF is not set # CONFIG_HID_VIVALDI is not set # CONFIG_HID_GT683R is not set @@ -5382,7 +5501,6 @@ CONFIG_NINTENDO_FF=y # CONFIG_HID_NTRIG is not set # CONFIG_HID_NVIDIA_SHIELD is not set CONFIG_HID_ORTEK=y -CONFIG_HID_OUYA=y CONFIG_HID_PANTHERLORD=y CONFIG_PANTHERLORD_FF=y CONFIG_HID_PENMOUNT=y @@ -5420,6 +5538,7 @@ CONFIG_HID_TOPSEED=y # CONFIG_HID_U2FZERO is not set # CONFIG_HID_WACOM is not set CONFIG_HID_WIIMOTE=m +# CONFIG_HID_WINWING is not set CONFIG_HID_XINMO=y # CONFIG_HID_ZEROPLUS is not set CONFIG_HID_ZYDACRON=y @@ -5432,7 +5551,6 @@ CONFIG_HID_ZYDACRON=y # # HID-BPF support # -# CONFIG_HID_BPF is not set # end of HID-BPF support # @@ -5456,6 +5574,7 @@ CONFIG_USB_COMMON=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y CONFIG_USB_PCI=y +# CONFIG_USB_PCI_AMD is not set CONFIG_USB_ANNOUNCE_NEW_DEVICES=y # @@ -5469,6 +5588,7 @@ CONFIG_USB_DEFAULT_PERSIST=y # CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 CONFIG_USB_MON=m # @@ -5625,7 +5745,7 @@ CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set -# CONFIG_USB_ONBOARD_HUB is not set +# CONFIG_USB_ONBOARD_DEV is not set # # USB Physical Layer drivers @@ -5682,6 +5802,7 @@ CONFIG_MMC_HSQ=y # CONFIG_MMC_TOSHIBA_PCI is not set # CONFIG_MMC_BCM2835 is not set # CONFIG_MMC_MTK is not set +# CONFIG_MMC_SDHCI_BRCMSTB is not set # CONFIG_MMC_SDHCI_XENON is not set # CONFIG_SCSI_UFSHCD is not set # CONFIG_MEMSTICK is not set @@ -5747,11 +5868,14 @@ CONFIG_LEDS_GPIO=y # CONFIG_LEDS_RT4505 is not set # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set +# CONFIG_LEDS_SY7802 is not set # # RGB LED drivers # # CONFIG_LEDS_GROUP_MULTICOLOR is not set +# CONFIG_LEDS_KTD202X is not set +# CONFIG_LEDS_NCP5623 is not set # CONFIG_LEDS_PWM_MULTICOLOR is not set # @@ -5764,6 +5888,7 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CPU=y # CONFIG_LEDS_TRIGGER_ACTIVITY is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set CONFIG_LEDS_TRIGGER_DEFAULT_ON=y # @@ -5775,8 +5900,8 @@ CONFIG_LEDS_TRIGGER_INPUT=y # CONFIG_LEDS_TRIGGER_PANIC is not set # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set -# CONFIG_LEDS_TRIGGER_AUDIO is not set # CONFIG_LEDS_TRIGGER_TTY is not set +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set CONFIG_LEDS_TRIGGER_ACTPWR=y # @@ -5816,6 +5941,7 @@ CONFIG_RTC_DRV_DS1307=m # CONFIG_RTC_DRV_DS1672 is not set # CONFIG_RTC_DRV_HYM8563 is not set # CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_MAX31335 is not set # CONFIG_RTC_DRV_NCT3018Y is not set # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set @@ -5832,12 +5958,14 @@ CONFIG_RTC_DRV_PCF8563=m # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8111 is not set # CONFIG_RTC_DRV_RX8581 is not set # CONFIG_RTC_DRV_RX8025 is not set # CONFIG_RTC_DRV_EM3027 is not set # CONFIG_RTC_DRV_RV3028 is not set # CONFIG_RTC_DRV_RV3032 is not set # CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD2405AL is not set # CONFIG_RTC_DRV_SD3078 is not set # @@ -5924,6 +6052,7 @@ CONFIG_DMA_BCM2835=y # CONFIG_XILINX_XDMA is not set # CONFIG_XILINX_ZYNQMP_DMA is not set # CONFIG_XILINX_ZYNQMP_DPDMA is not set +# CONFIG_AMD_QDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_DW_DMAC is not set @@ -5969,8 +6098,6 @@ CONFIG_VHOST_MENU=y # CONFIG_GREYBUS is not set # CONFIG_COMEDI is not set CONFIG_STAGING=y -# CONFIG_PRISM2_USB is not set -# CONFIG_RTL8192U is not set # CONFIG_RTLLIB is not set CONFIG_RTL8723BS=m CONFIG_R8712U=m @@ -5982,11 +6109,13 @@ CONFIG_STAGING_MEDIA=y # CONFIG_DVB_AV7110 is not set # CONFIG_VIDEO_MAX96712 is not set CONFIG_VIDEO_RPIVID=m + +# +# StarFive media platform drivers +# # CONFIG_STAGING_MEDIA_DEPRECATED is not set -# CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set # CONFIG_FB_TFT is not set -# CONFIG_KS7010 is not set CONFIG_BCM_VIDEOCORE=y CONFIG_BCM2835_VCHIQ=y CONFIG_VCHIQ_CDEV=y @@ -5996,15 +6125,15 @@ CONFIG_BCM_VC_SM_CMA=y CONFIG_VIDEO_CODEC_BCM2835=m CONFIG_VIDEO_ISP_BCM2835=m CONFIG_BCM2835_VCHIQ_MMAL=m -# CONFIG_PI433 is not set # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set -# CONFIG_QLGE is not set # CONFIG_VME_BUS is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_SURFACE_PLATFORMS=y +CONFIG_ARM64_PLATFORM_DEVICES=y CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y @@ -6063,6 +6192,7 @@ CONFIG_ARM_TIMER_SP804=y CONFIG_MAILBOX=y # CONFIG_ARM_MHU is not set # CONFIG_ARM_MHU_V2 is not set +# CONFIG_ARM_MHU_V3 is not set # CONFIG_PLATFORM_MHU is not set # CONFIG_PL320_MBOX is not set # CONFIG_ALTERA_MBOX is not set @@ -6097,9 +6227,6 @@ CONFIG_BCM2835_MBOX=y # # Broadcom SoC drivers # -CONFIG_BCM2835_POWER=y -CONFIG_RASPBERRYPI_POWER=y -# CONFIG_SOC_BRCMSTB is not set # end of Broadcom SoC drivers # @@ -6139,6 +6266,33 @@ CONFIG_RASPBERRYPI_POWER=y # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers +# +# PM Domains +# + +# +# Amlogic PM Domains +# +# end of Amlogic PM Domains + +# +# Broadcom PM Domains +# +CONFIG_BCM2835_POWER=y +CONFIG_RASPBERRYPI_POWER=y +# end of Broadcom PM Domains + +# +# i.MX PM Domains +# +# end of i.MX PM Domains + +# +# Qualcomm PM Domains +# +# end of Qualcomm PM Domains +# end of PM Domains + # CONFIG_PM_DEVFREQ is not set CONFIG_EXTCON=y @@ -6147,6 +6301,7 @@ CONFIG_EXTCON=y # # CONFIG_EXTCON_FSA9480 is not set # CONFIG_EXTCON_GPIO is not set +# CONFIG_EXTCON_LC824206XA is not set # CONFIG_EXTCON_MAX3355 is not set # CONFIG_EXTCON_PTN5150 is not set # CONFIG_EXTCON_RT8973A is not set @@ -6156,7 +6311,6 @@ CONFIG_EXTCON=y # CONFIG_IIO is not set # CONFIG_NTB is not set CONFIG_PWM=y -CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL_TCB is not set CONFIG_PWM_BCM2835=m @@ -6178,10 +6332,11 @@ CONFIG_ARM_GIC_MAX_NR=1 CONFIG_ARM_GIC_V2M=y CONFIG_ARM_GIC_V3=y CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y +CONFIG_IRQ_MSI_LIB=y # CONFIG_AL_FIC is not set # CONFIG_BCM2712_MIP is not set CONFIG_BRCMSTB_L2_IRQ=y +# CONFIG_LAN966X_OIC is not set # CONFIG_XILINX_INTC is not set CONFIG_PARTITION_PERCPU=y # end of IRQ chip support @@ -6189,6 +6344,7 @@ CONFIG_PARTITION_PERCPU=y # CONFIG_IPACK_BUS is not set CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_BRCMSTB is not set +# CONFIG_RESET_GPIO is not set CONFIG_RESET_RASPBERRYPI=y CONFIG_RESET_SIMPLE=y # CONFIG_RESET_TI_SYSCON is not set @@ -6228,6 +6384,7 @@ CONFIG_RESET_SIMPLE=y # CONFIG_ARM_CCI_PMU is not set # CONFIG_ARM_CCN is not set # CONFIG_ARM_CMN is not set +# CONFIG_ARM_NI is not set CONFIG_ARM_PMU=y # CONFIG_ARM_SMMU_V3_PMU is not set CONFIG_ARM_PMUV3=y @@ -6236,6 +6393,7 @@ CONFIG_ARM_PMUV3=y CONFIG_RPI_AXIPERF=m # CONFIG_HISI_PCIE_PMU is not set # CONFIG_HNS3_PMU is not set +# CONFIG_DWC_PCIE_PMU is not set # CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set # end of Performance monitor support @@ -6252,12 +6410,14 @@ CONFIG_RAS=y # CONFIG_DAX is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y +CONFIG_NVMEM_LAYOUTS=y # # Layout Types # # CONFIG_NVMEM_LAYOUT_SL28_VPD is not set # CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set +# CONFIG_NVMEM_LAYOUT_U_BOOT_ENV is not set # end of Layout Types CONFIG_NVMEM_RASPBERRYPI_OTP=y @@ -6291,6 +6451,7 @@ CONFIG_PM_OPP=y CONFIG_DCACHE_WORD_ACCESS=y CONFIG_VALIDATE_FS_PARSER=y CONFIG_FS_IOMAP=y +CONFIG_FS_STACK=y CONFIG_BUFFER_HEAD=y CONFIG_LEGACY_DIRECT_IO=y # CONFIG_EXT2_FS is not set @@ -6322,7 +6483,6 @@ CONFIG_XFS_SUPPORT_ASCII_CI=y # CONFIG_OCFS2_FS is not set CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y -# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set # CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set # CONFIG_BTRFS_DEBUG is not set # CONFIG_BTRFS_ASSERT is not set @@ -6336,6 +6496,7 @@ CONFIG_F2FS_CHECK_FS=y # CONFIG_F2FS_FS_COMPRESSION is not set CONFIG_F2FS_IOSTAT=y # CONFIG_F2FS_UNFAIR_RWSEM is not set +# CONFIG_BCACHEFS_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set @@ -6351,6 +6512,7 @@ CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m # CONFIG_CUSE is not set # CONFIG_VIRTIO_FS is not set +CONFIG_FUSE_PASSTHROUGH=y CONFIG_OVERLAY_FS=m # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -6364,9 +6526,9 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # CONFIG_NETFS_SUPPORT=y # CONFIG_NETFS_STATS is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set -# CONFIG_FSCACHE_DEBUG is not set # CONFIG_CACHEFILES is not set # end of Caches @@ -6390,11 +6552,11 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" -# CONFIG_NTFS_FS is not set CONFIG_NTFS3_FS=m # CONFIG_NTFS3_64BIT_CLUSTER is not set # CONFIG_NTFS3_LZX_XPRESS is not set # CONFIG_NTFS3_FS_POSIX_ACL is not set +# CONFIG_NTFS_FS is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -6512,6 +6674,7 @@ CONFIG_CIFS_DEBUG=y # CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y # CONFIG_CIFS_ROOT is not set +# CONFIG_CIFS_COMPRESSION is not set # CONFIG_SMB_SERVER is not set CONFIG_SMBFS=y # CONFIG_CODA_FS is not set @@ -6674,7 +6837,6 @@ CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m # CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set -# CONFIG_CRYPTO_SM2 is not set # CONFIG_CRYPTO_CURVE25519 is not set # end of Public-key cryptography @@ -6706,14 +6868,12 @@ CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_ARC4 is not set # CONFIG_CRYPTO_CHACHA20 is not set CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CFB=m CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_HCTR2 is not set # CONFIG_CRYPTO_KEYWRAP is not set # CONFIG_CRYPTO_LRW is not set -CONFIG_CRYPTO_OFB=m # CONFIG_CRYPTO_PCBC is not set # CONFIG_CRYPTO_XTS is not set # end of Length-preserving ciphers and modes @@ -6784,7 +6944,9 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y -# CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE is not set +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 CONFIG_CRYPTO_KDF800108_CTR=y # end of Random number generation @@ -6867,7 +7029,6 @@ CONFIG_GENERIC_NET_UTILS=y CONFIG_CORDIC=m # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y -CONFIG_GENERIC_PCI_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y @@ -6926,11 +7087,13 @@ CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y # CONFIG_XZ_DEC_X86 is not set # CONFIG_XZ_DEC_POWERPC is not set -# CONFIG_XZ_DEC_IA64 is not set # CONFIG_XZ_DEC_ARM is not set # CONFIG_XZ_DEC_ARMTHUMB is not set +CONFIG_XZ_DEC_ARM64=y # CONFIG_XZ_DEC_SPARC is not set +CONFIG_XZ_DEC_RISCV=y # CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_BCJ=y # CONFIG_XZ_DEC_TEST is not set CONFIG_GENERIC_ALLOCATOR=y CONFIG_REED_SOLOMON=y @@ -6952,6 +7115,7 @@ CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y CONFIG_SWIOTLB=y # CONFIG_SWIOTLB_DYNAMIC is not set +CONFIG_DMA_NEED_SYNC=y # CONFIG_DMA_RESTRICTED_POOL is not set CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_COHERENT_POOL=y @@ -6986,6 +7150,7 @@ CONFIG_UCS2_STRING=y CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_VDSO_TIME_NS=y +CONFIG_VDSO_GETRANDOM=y CONFIG_FONT_SUPPORT=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y @@ -6993,7 +7158,9 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y +CONFIG_STACKDEPOT_MAX_FRAMES=64 CONFIG_SBITMAP=y +# CONFIG_LWQ_TEST is not set # end of Library routines CONFIG_GENERIC_IOREMAP=y @@ -7025,7 +7192,7 @@ CONFIG_DEBUG_MISC=y # # Compile-time checks and compiler options # -CONFIG_AS_HAS_NON_CONST_LEB128=y +CONFIG_AS_HAS_NON_CONST_ULEB128=y CONFIG_DEBUG_INFO_NONE=y # CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set # CONFIG_DEBUG_INFO_DWARF4 is not set @@ -7056,7 +7223,7 @@ CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +CONFIG_ARCH_HAS_UBSAN=y # CONFIG_UBSAN is not set CONFIG_HAVE_ARCH_KCSAN=y CONFIG_HAVE_KCSAN_COMPILER=y @@ -7101,6 +7268,7 @@ CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y @@ -7190,6 +7358,7 @@ CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set # CONFIG_LATENCYTOP is not set # CONFIG_DEBUG_CGROUP_REF is not set +CONFIG_USER_STACKTRACE_SUPPORT=y CONFIG_NOP_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y @@ -7250,6 +7419,7 @@ CONFIG_FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY=y # CONFIG_RING_BUFFER_BENCHMARK is not set # CONFIG_TRACE_EVAL_MAP_FILE is not set # CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_VALIDATE_RCU_IS_WATCHING is not set # CONFIG_FTRACE_STARTUP_TEST is not set # CONFIG_RING_BUFFER_STARTUP_TEST is not set # CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set diff --git a/projects/RPi/devices/RPi5/linux/linux.aarch64.conf b/projects/RPi/devices/RPi5/linux/linux.aarch64.conf index b0cd14403d..eb82e53057 100644 --- a/projects/RPi/devices/RPi5/linux/linux.aarch64.conf +++ b/projects/RPi/devices/RPi5/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.6.59 Kernel Configuration +# Linux/arm64 6.12.0-rc7 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GCC) 13.0.0 20220604 (experimental) [master revision aec868578d8515763d75693c1fdfbc30ff0a1e68]" CONFIG_CC_IS_GCC=y @@ -11,11 +11,11 @@ CONFIG_AS_VERSION=23850 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23850 CONFIG_LLD_VERSION=0 +CONFIG_RUSTC_VERSION=0 +CONFIG_RUSTC_LLVM_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y -CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y -CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y +CONFIG_GCC_ASM_GOTO_OUTPUT_BROKEN=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y CONFIG_PAHOLE_VERSION=0 @@ -102,6 +102,7 @@ CONFIG_PREEMPT_VOLUNTARY_BUILD=y # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set +# CONFIG_PREEMPT_RT is not set # CONFIG_PREEMPT_DYNAMIC is not set # @@ -124,6 +125,7 @@ CONFIG_TREE_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_TREE_SRCU=y CONFIG_TASKS_RCU_GENERIC=y +CONFIG_NEED_TASKS_RCU=y CONFIG_TASKS_RUDE_RCU=y CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y @@ -149,16 +151,20 @@ CONFIG_CC_HAS_INT128=y CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" CONFIG_GCC10_NO_ARRAY_BOUNDS=y CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_GCC_NO_STRINGOP_OVERFLOW=y +CONFIG_CC_NO_STRINGOP_OVERFLOW=y CONFIG_ARCH_SUPPORTS_INT128=y # CONFIG_NUMA_BALANCING is not set +CONFIG_SLAB_OBJ_EXT=y CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y # CONFIG_CGROUP_FAVOR_DYNMODS is not set CONFIG_MEMCG=y -CONFIG_MEMCG_KMEM=y +# CONFIG_MEMCG_V1 is not set CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y CONFIG_CGROUP_SCHED=y +CONFIG_GROUP_SCHED_WEIGHT=y CONFIG_FAIR_GROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y # CONFIG_RT_GROUP_SCHED is not set @@ -167,6 +173,7 @@ CONFIG_CGROUP_PIDS=y # CONFIG_CGROUP_RDMA is not set CONFIG_CGROUP_FREEZER=y CONFIG_CPUSETS=y +# CONFIG_CPUSETS_V1 is not set CONFIG_PROC_PID_CPUSET=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y @@ -218,7 +225,7 @@ CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y +# CONFIG_BASE_SMALL is not set CONFIG_FUTEX=y CONFIG_FUTEX_PI=y CONFIG_EPOLL=y @@ -230,17 +237,16 @@ CONFIG_AIO=y CONFIG_IO_URING=y CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y +CONFIG_KCMP=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +CONFIG_CACHESTAT_SYSCALL=y +# CONFIG_PC104 is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_SELFTEST is not set # CONFIG_KALLSYMS_ALL is not set -CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -CONFIG_KCMP=y -CONFIG_RSEQ=y -CONFIG_CACHESTAT_SYSCALL=y -# CONFIG_DEBUG_RSEQ is not set CONFIG_HAVE_PERF_EVENTS=y -# CONFIG_PC104 is not set # # Kernel Performance Events And Counters @@ -257,15 +263,14 @@ CONFIG_TRACEPOINTS=y # Kexec and crash features # # CONFIG_KEXEC_FILE is not set -# CONFIG_CRASH_DUMP is not set # end of Kexec and crash features # end of General setup CONFIG_ARM64=y +CONFIG_RUSTC_SUPPORTS_ARM64=y CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_64BIT=y CONFIG_MMU=y -CONFIG_ARM64_PAGE_SHIFT=14 CONFIG_ARM64_CONT_PTE_SHIFT=7 CONFIG_ARM64_CONT_PMD_SHIFT=5 CONFIG_ARCH_MMAP_RND_BITS_MIN=16 @@ -292,6 +297,7 @@ CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y # Platform selection # # CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_AIROHA is not set # CONFIG_ARCH_SUNXI is not set # CONFIG_ARCH_ALPINE is not set # CONFIG_ARCH_APPLE is not set @@ -314,6 +320,7 @@ CONFIG_ARCH_BRCMSTB=y # CONFIG_ARCH_NXP is not set # CONFIG_ARCH_MA35 is not set # CONFIG_ARCH_NPCM is not set +# CONFIG_ARCH_PENSANDO is not set # CONFIG_ARCH_QCOM is not set # CONFIG_ARCH_REALTEK is not set # CONFIG_ARCH_RENESAS is not set @@ -399,6 +406,7 @@ CONFIG_ARM64_16K_PAGES=y # CONFIG_ARM64_VA_BITS_36 is not set CONFIG_ARM64_VA_BITS_47=y # CONFIG_ARM64_VA_BITS_48 is not set +# CONFIG_ARM64_VA_BITS_52 is not set CONFIG_ARM64_VA_BITS=47 CONFIG_ARM64_PA_BITS_48=y CONFIG_ARM64_PA_BITS=48 @@ -411,7 +419,6 @@ CONFIG_NR_CPUS=256 # CONFIG_HOTPLUG_CPU is not set CONFIG_NUMA=y CONFIG_NODES_SHIFT=4 -CONFIG_NUMA_EMULATION=y # CONFIG_HZ_100 is not set # CONFIG_HZ_250 is not set CONFIG_HZ_300=y @@ -500,8 +507,14 @@ CONFIG_ARM64_MTE=y CONFIG_ARM64_EPAN=y # end of ARMv8.7 architectural features +# +# ARMv8.9 architectural features +# +CONFIG_ARM64_POE=y +CONFIG_ARCH_PKEY_BITS=3 +# end of ARMv8.9 architectural features + CONFIG_ARM64_SVE=y -CONFIG_ARM64_SME=y # CONFIG_ARM64_PSEUDO_NMI is not set CONFIG_RELOCATABLE=y # CONFIG_RANDOMIZE_BASE is not set @@ -515,6 +528,7 @@ CONFIG_STACKPROTECTOR_PER_TASK=y CONFIG_CMDLINE="" CONFIG_EFI_STUB=y CONFIG_EFI=y +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_DMI=y # end of Boot options @@ -586,7 +600,6 @@ CONFIG_ARM_RASPBERRYPI_CPUFREQ=y CONFIG_ARCH_SUPPORTS_ACPI=y # CONFIG_ACPI is not set -CONFIG_HAVE_KVM=y # CONFIG_VIRTUALIZATION is not set CONFIG_CPU_MITIGATIONS=y @@ -620,6 +633,7 @@ CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_RUST=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_PERF_REGS=y @@ -661,6 +675,7 @@ CONFIG_HAVE_ARCH_HUGE_VMALLOC=y CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_WANTS_EXECMEM_LATE=y CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y CONFIG_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y @@ -668,13 +683,17 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_HAVE_PAGE_SIZE_16KB=y +CONFIG_PAGE_SIZE_16KB=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SHIFT=14 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_COMPAT_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y +CONFIG_ARCH_SUPPORTS_RT=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y @@ -689,12 +708,15 @@ CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y CONFIG_ARCH_USE_MEMREMAP_PROT=y # CONFIG_LOCK_EVENT_COUNTS is not set CONFIG_ARCH_HAS_RELR=y +CONFIG_ARCH_HAS_MEM_ENCRYPT=y CONFIG_HAVE_PREEMPT_DYNAMIC=y CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y +CONFIG_ARCH_HAS_HW_PTE_YOUNG=y +CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT=y # # GCOV-based kernel profiling @@ -712,7 +734,6 @@ CONFIG_FUNCTION_ALIGNMENT=8 # end of General architecture-dependent options CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_DEBUG is not set # CONFIG_MODULE_FORCE_LOAD is not set @@ -722,10 +743,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set # CONFIG_MODULE_SIG is not set -CONFIG_MODULE_COMPRESS_NONE=y -# CONFIG_MODULE_COMPRESS_GZIP is not set -# CONFIG_MODULE_COMPRESS_XZ is not set -# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_COMPRESS is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set @@ -738,9 +756,9 @@ CONFIG_BLK_DEV_BSG_COMMON=y CONFIG_BLK_ICQ=y CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_DEV_INTEGRITY is not set +CONFIG_BLK_DEV_WRITE_MOUNTED=y # CONFIG_BLK_DEV_ZONED is not set CONFIG_BLK_DEV_THROTTLING=y -# CONFIG_BLK_DEV_THROTTLING_LOW is not set # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set # CONFIG_BLK_CGROUP_IOCOST is not set @@ -876,18 +894,18 @@ CONFIG_SWAP=y # CONFIG_ZSWAP is not set # -# SLAB allocator options +# Slab allocator options # -# CONFIG_SLAB_DEPRECATED is not set CONFIG_SLUB=y # CONFIG_SLUB_TINY is not set CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_FREELIST_HARDENED is not set +CONFIG_SLAB_BUCKETS=y # CONFIG_SLUB_STATS is not set CONFIG_SLUB_CPU_PARTIAL=y # CONFIG_RANDOM_KMALLOC_CACHES is not set -# end of SLAB allocator options +# end of Slab allocator options # CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set # CONFIG_COMPAT_BRK is not set @@ -895,15 +913,16 @@ CONFIG_SPARSEMEM=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_HAVE_FAST_GUP=y +CONFIG_HAVE_GUP_FAST=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y # CONFIG_MEMORY_HOTPLUG is not set CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_SPLIT_PTE_PTLOCKS=y CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_SPLIT_PMD_PTLOCKS=y CONFIG_COMPACTION=y CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 # CONFIG_PAGE_REPORTING is not set @@ -921,7 +940,6 @@ CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y CONFIG_USE_PERCPU_NUMA_NODE_ID=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_CMA=y -# CONFIG_CMA_DEBUG is not set CONFIG_CMA_DEBUGFS=y # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 @@ -935,7 +953,9 @@ CONFIG_ARCH_HAS_ZONE_DMA_SET=y CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y -CONFIG_ARCH_USES_PG_ARCH_X=y +CONFIG_ARCH_HAS_PKEYS=y +CONFIG_ARCH_USES_PG_ARCH_2=y +CONFIG_ARCH_USES_PG_ARCH_3=y CONFIG_VM_EVENT_COUNTERS=y # CONFIG_PERCPU_STATS is not set # CONFIG_GUP_TEST is not set @@ -948,9 +968,13 @@ CONFIG_SECRETMEM=y CONFIG_LRU_GEN=y # CONFIG_LRU_GEN_ENABLED is not set # CONFIG_LRU_GEN_STATS is not set +CONFIG_LRU_GEN_WALKS_MMU=y CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y CONFIG_PER_VMA_LOCK=y CONFIG_LOCK_MM_AND_FIND_VMA=y +CONFIG_EXECMEM=y +CONFIG_NUMA_MEMBLKS=y +CONFIG_NUMA_EMU=y # # Data Access Monitoring @@ -965,6 +989,7 @@ CONFIG_NET_INGRESS=y CONFIG_NET_EGRESS=y CONFIG_NET_XGRESS=y CONFIG_SKB_EXTENSIONS=y +CONFIG_NET_DEVMEM=y # # Networking options @@ -972,7 +997,6 @@ CONFIG_SKB_EXTENSIONS=y CONFIG_PACKET=y # CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y -CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y # CONFIG_UNIX_DIAG is not set # CONFIG_TLS is not set @@ -1039,6 +1063,7 @@ CONFIG_TCP_CONG_CDG=m CONFIG_DEFAULT_CUBIC=y # CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_AO is not set # CONFIG_TCP_MD5SIG is not set CONFIG_IPV6=y # CONFIG_IPV6_ROUTER_PREF is not set @@ -1252,6 +1277,7 @@ CONFIG_IP_VS_NFCT=y # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=m +CONFIG_IP_NF_IPTABLES_LEGACY=m # CONFIG_NF_SOCKET_IPV4 is not set # CONFIG_NF_TPROXY_IPV4 is not set # CONFIG_NF_DUP_IPV4 is not set @@ -1274,12 +1300,13 @@ CONFIG_IP_NF_MANGLE=m # CONFIG_IP_NF_TARGET_ECN is not set # CONFIG_IP_NF_TARGET_TTL is not set # CONFIG_IP_NF_RAW is not set -# CONFIG_IP_NF_ARPTABLES is not set +# CONFIG_IP_NF_ARPFILTER is not set # end of IP: Netfilter Configuration # # IPv6: Netfilter Configuration # +CONFIG_IP6_NF_IPTABLES_LEGACY=m # CONFIG_NF_SOCKET_IPV6 is not set # CONFIG_NF_TPROXY_IPV6 is not set # CONFIG_NF_DUP_IPV6 is not set @@ -1310,7 +1337,6 @@ CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_NF_DEFRAG_IPV6=m # CONFIG_NF_CONNTRACK_BRIDGE is not set # CONFIG_BRIDGE_NF_EBTABLES is not set -# CONFIG_BPFILTER is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set # CONFIG_RDS is not set @@ -1463,6 +1489,7 @@ CONFIG_BT_HCIUART_BCM=y # CONFIG_BT_HCIUART_QCA is not set # CONFIG_BT_HCIUART_AG6XX is not set # CONFIG_BT_HCIUART_MRVL is not set +# CONFIG_BT_HCIUART_AML is not set CONFIG_BT_HCIBCM203X=m # CONFIG_BT_HCIBCM4377 is not set # CONFIG_BT_HCIBPA10X is not set @@ -1473,6 +1500,7 @@ CONFIG_BT_ATH3K=m # CONFIG_BT_MTKSDIO is not set # CONFIG_BT_MTKUART is not set # CONFIG_BT_NXPUART is not set +# CONFIG_BT_INTEL_PCIE is not set # end of Bluetooth device drivers # CONFIG_AF_RXRPC is not set @@ -1501,7 +1529,6 @@ CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" # CONFIG_MAC80211_MESH is not set CONFIG_MAC80211_LEDS=y -# CONFIG_MAC80211_DEBUGFS is not set # CONFIG_MAC80211_MESSAGE_TRACING is not set # CONFIG_MAC80211_DEBUG_MENU is not set CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 @@ -1530,6 +1557,7 @@ CONFIG_ETHTOOL_NETLINK=y # CONFIG_ARM_AMBA=y CONFIG_HAVE_PCI=y +CONFIG_GENERIC_PCI_IOMAP=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_DOMAINS_GENERIC=y @@ -1551,6 +1579,7 @@ CONFIG_PCI_QUIRKS=y # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set # CONFIG_PCI_IOV is not set +# CONFIG_PCI_NPEM is not set # CONFIG_PCI_PRI is not set # CONFIG_PCI_PASID is not set CONFIG_PCI_LABEL=y @@ -1573,7 +1602,6 @@ CONFIG_PCIE_BRCMSTB=y # CONFIG_PCI_HOST_THUNDER_ECAM is not set # CONFIG_PCI_FTPCI100 is not set # CONFIG_PCI_HOST_GENERIC is not set -# CONFIG_PCIE_MICROCHIP_HOST is not set # CONFIG_PCI_XGENE is not set # CONFIG_PCIE_XILINX is not set @@ -1581,7 +1609,6 @@ CONFIG_PCIE_BRCMSTB=y # Cadence-based PCIe controllers # # CONFIG_PCIE_CADENCE_PLAT_HOST is not set -# CONFIG_PCI_J721E_HOST is not set # end of Cadence-based PCIe controllers # @@ -1598,6 +1625,12 @@ CONFIG_PCIE_BRCMSTB=y # Mobiveil-based PCIe controllers # # end of Mobiveil-based PCIe controllers + +# +# PLDA-based PCIe controllers +# +# CONFIG_PCIE_MICROCHIP_HOST is not set +# end of PLDA-based PCIe controllers # end of PCI controller drivers # @@ -1643,6 +1676,7 @@ CONFIG_WANT_DEV_COREDUMP=y # CONFIG_DEBUG_DEVRES is not set # CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_DEVICES=y CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y CONFIG_SOC_BUS=y @@ -1655,7 +1689,6 @@ CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set CONFIG_GENERIC_ARCH_TOPOLOGY=y CONFIG_GENERIC_ARCH_NUMA=y -CONFIG_GENERIC_ARCH_NUMA_EMULATION=y # CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set # end of Generic Driver Options @@ -1718,6 +1751,12 @@ CONFIG_EFI_EARLYCON=y # end of EFI (Extensible Firmware Interface) Support CONFIG_ARM_PSCI_FW=y + +# +# Qualcomm firmware drivers +# +# end of Qualcomm firmware drivers + CONFIG_HAVE_ARM_SMCCC=y CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y CONFIG_ARM_SMCCC_SOC_ID=y @@ -1750,6 +1789,7 @@ CONFIG_BLK_DEV=y CONFIG_CDROM=y # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set # CONFIG_ZRAM is not set +CONFIG_ZRAM_DEF_COMP="unset-value" CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 # CONFIG_BLK_DEV_DRBD is not set @@ -1772,7 +1812,7 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_NVME_HWMON is not set # CONFIG_NVME_FC is not set # CONFIG_NVME_TCP is not set -# CONFIG_NVME_AUTH is not set +# CONFIG_NVME_HOST_AUTH is not set # CONFIG_NVME_TARGET is not set # end of NVME Support @@ -1783,6 +1823,7 @@ CONFIG_BCM2835_SMI=m # CONFIG_AD525X_DPOT is not set # CONFIG_DUMMY_IRQ is not set # CONFIG_PHANTOM is not set +# CONFIG_RPMB is not set # CONFIG_TIFM_CORE is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set @@ -1811,7 +1852,6 @@ CONFIG_MISC_RTSX=y # # CONFIG_EEPROM_AT24 is not set # CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set # CONFIG_EEPROM_MAX6875 is not set CONFIG_EEPROM_93CX6=m # CONFIG_EEPROM_93XX46 is not set @@ -1840,6 +1880,7 @@ CONFIG_MISC_RTSX_USB=y # CONFIG_UACCE is not set # CONFIG_PVPANIC is not set # CONFIG_GP_PCI1XXXX is not set +# CONFIG_KEBA_CP500 is not set # end of Misc devices # @@ -1961,6 +2002,7 @@ CONFIG_DM_THIN_PROVISIONING=m # CONFIG_DM_SWITCH is not set # CONFIG_DM_LOG_WRITES is not set # CONFIG_DM_INTEGRITY is not set +# CONFIG_DM_VDO is not set # CONFIG_TARGET_CORE is not set # CONFIG_FUSION is not set @@ -1990,6 +2032,7 @@ CONFIG_VXLAN=m # CONFIG_GENEVE is not set # CONFIG_BAREUDP is not set # CONFIG_GTP is not set +# CONFIG_PFCP is not set # CONFIG_AMT is not set # CONFIG_MACSEC is not set CONFIG_NETCONSOLE=y @@ -2001,6 +2044,7 @@ CONFIG_TUN=y # CONFIG_TUN_VNET_CROSS_LE is not set CONFIG_VETH=m CONFIG_NLMON=m +# CONFIG_NETKIT is not set # CONFIG_NET_VRF is not set # CONFIG_ARCNET is not set CONFIG_ETHERNET=y @@ -2104,6 +2148,7 @@ CONFIG_NET_VENDOR_INTEL=y # CONFIG_ICE is not set # CONFIG_FM10K is not set # CONFIG_IGC is not set +# CONFIG_IDPF is not set # CONFIG_JME is not set CONFIG_NET_VENDOR_ADI=y CONFIG_NET_VENDOR_LITEX=y @@ -2115,11 +2160,13 @@ CONFIG_NET_VENDOR_MARVELL=y # CONFIG_OCTEONTX2_AF is not set # CONFIG_OCTEONTX2_PF is not set # CONFIG_OCTEON_EP is not set +# CONFIG_OCTEON_EP_VF is not set CONFIG_NET_VENDOR_MELLANOX=y # CONFIG_MLX4_EN is not set # CONFIG_MLX5_CORE is not set # CONFIG_MLXSW_CORE is not set # CONFIG_MLXFW is not set +CONFIG_NET_VENDOR_META=y CONFIG_NET_VENDOR_MICREL=y # CONFIG_KS8842 is not set # CONFIG_KS8851 is not set @@ -2129,6 +2176,7 @@ CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_ENC28J60 is not set # CONFIG_ENCX24J600 is not set # CONFIG_LAN743X is not set +# CONFIG_LAN865X is not set # CONFIG_VCAP is not set CONFIG_NET_VENDOR_MICROSEMI=y CONFIG_NET_VENDOR_MICROSOFT=y @@ -2150,6 +2198,7 @@ CONFIG_NET_VENDOR_NVIDIA=y # CONFIG_FORCEDETH is not set CONFIG_NET_VENDOR_OKI=y # CONFIG_ETHOC is not set +# CONFIG_OA_TC6 is not set CONFIG_NET_VENDOR_PACKET_ENGINES=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set @@ -2172,6 +2221,7 @@ CONFIG_NET_VENDOR_REALTEK=y # CONFIG_8139CP is not set # CONFIG_8139TOO is not set # CONFIG_R8169 is not set +# CONFIG_RTASE is not set CONFIG_NET_VENDOR_RENESAS=y CONFIG_NET_VENDOR_ROCKER=y CONFIG_NET_VENDOR_SAMSUNG=y @@ -2202,6 +2252,7 @@ CONFIG_NET_VENDOR_SYNOPSYS=y # CONFIG_DWC_XLGMAC is not set CONFIG_NET_VENDOR_TEHUTI=y # CONFIG_TEHUTI is not set +# CONFIG_TEHUTI_TN40 is not set CONFIG_NET_VENDOR_TI=y # CONFIG_TI_CPSW_PHY_SEL is not set # CONFIG_TLAN is not set @@ -2218,7 +2269,6 @@ CONFIG_NET_VENDOR_WIZNET=y # CONFIG_WIZNET_W5300 is not set CONFIG_NET_VENDOR_XILINX=y # CONFIG_XILINX_EMACLITE is not set -# CONFIG_XILINX_AXI_EMAC is not set # CONFIG_XILINX_LL_TEMAC is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set @@ -2233,6 +2283,7 @@ CONFIG_FIXED_PHY=y # # MII PHY device drivers # +# CONFIG_AIR_EN8811H_PHY is not set # CONFIG_AMD_PHY is not set # CONFIG_ADIN_PHY is not set # CONFIG_ADIN1100_PHY is not set @@ -2269,6 +2320,9 @@ CONFIG_MICROCHIP_PHY=y # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_NCN26000_PHY is not set # CONFIG_AT803X_PHY is not set +# CONFIG_QCA83XX_PHY is not set +# CONFIG_QCA808X_PHY is not set +# CONFIG_QCA807X_PHY is not set # CONFIG_QSEMI_PHY is not set # CONFIG_REALTEK_PHY is not set # CONFIG_RENESAS_PHY is not set @@ -2282,6 +2336,7 @@ CONFIG_SMSC_PHY=y # CONFIG_DP83867_PHY is not set # CONFIG_DP83869_PHY is not set # CONFIG_DP83TD510_PHY is not set +# CONFIG_DP83TG720_PHY is not set # CONFIG_VITESSE_PHY is not set # CONFIG_XILINX_GMII2RGMII is not set # CONFIG_MICREL_KS8995MA is not set @@ -2311,6 +2366,7 @@ CONFIG_MDIO_BCM_UNIMAC=y # # PCS device drivers # +# CONFIG_PCS_XPCS is not set # end of PCS device drivers CONFIG_PPP=m @@ -2381,7 +2437,6 @@ CONFIG_ATH9K_BTCOEX_SUPPORT=y CONFIG_ATH9K=m CONFIG_ATH9K_PCI=y CONFIG_ATH9K_AHB=y -# CONFIG_ATH9K_DEBUGFS is not set # CONFIG_ATH9K_DYNACK is not set # CONFIG_ATH9K_WOW is not set CONFIG_ATH9K_RFKILL=y @@ -2405,8 +2460,9 @@ CONFIG_AR5523=m # CONFIG_ATH10K is not set CONFIG_WCN36XX=m # CONFIG_WCN36XX_DEBUGFS is not set +# CONFIG_ATH11K is not set +# CONFIG_ATH12K is not set CONFIG_WLAN_VENDOR_ATMEL=y -# CONFIG_ATMEL is not set # CONFIG_AT76C50X_USB is not set CONFIG_WLAN_VENDOR_BROADCOM=y CONFIG_B43=m @@ -2437,8 +2493,6 @@ CONFIG_BRCMFMAC_USB=y # CONFIG_BRCMFMAC_PCIE is not set # CONFIG_BRCM_TRACING is not set CONFIG_BRCMDBG=y -CONFIG_WLAN_VENDOR_CISCO=y -# CONFIG_AIRO is not set CONFIG_WLAN_VENDOR_INTEL=y # CONFIG_IPW2100 is not set # CONFIG_IPW2200 is not set @@ -2446,8 +2500,6 @@ CONFIG_WLAN_VENDOR_INTEL=y # CONFIG_IWL3945 is not set # CONFIG_IWLWIFI is not set CONFIG_WLAN_VENDOR_INTERSIL=y -# CONFIG_HOSTAP is not set -# CONFIG_HERMES is not set CONFIG_P54_COMMON=m CONFIG_P54_USB=m # CONFIG_P54_PCI is not set @@ -2486,6 +2538,8 @@ CONFIG_MT7921_COMMON=m # CONFIG_MT7921S is not set CONFIG_MT7921U=m # CONFIG_MT7996E is not set +# CONFIG_MT7925E is not set +# CONFIG_MT7925U is not set CONFIG_WLAN_VENDOR_MICROCHIP=y # CONFIG_WILC1000_SDIO is not set # CONFIG_WILC1000_SPI is not set @@ -2553,6 +2607,7 @@ CONFIG_RTW88_8822BU=m CONFIG_RTW88_8822CU=m # CONFIG_RTW88_8723DE is not set # CONFIG_RTW88_8723DS is not set +# CONFIG_RTW88_8723CS is not set CONFIG_RTW88_8723DU=m # CONFIG_RTW88_8821CE is not set # CONFIG_RTW88_8821CS is not set @@ -2574,11 +2629,9 @@ CONFIG_WLAN_VENDOR_TI=y # CONFIG_WL18XX is not set # CONFIG_WLCORE is not set CONFIG_WLAN_VENDOR_ZYDAS=y -CONFIG_USB_ZD1201=m CONFIG_ZD1211RW=m # CONFIG_ZD1211RW_DEBUG is not set # CONFIG_WLAN_VENDOR_QUANTENNA is not set -CONFIG_USB_NET_RNDIS_WLAN=m # CONFIG_MAC80211_HWSIM is not set # CONFIG_VIRT_WIFI is not set # CONFIG_WAN is not set @@ -2634,7 +2687,6 @@ CONFIG_KEYBOARD_GPIO=m # CONFIG_KEYBOARD_LM8323 is not set # CONFIG_KEYBOARD_LM8333 is not set # CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_MCS is not set # CONFIG_KEYBOARD_MPR121 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set @@ -2680,6 +2732,7 @@ CONFIG_JOYSTICK_PSXPAD_SPI_FF=y # CONFIG_JOYSTICK_QWIIC is not set # CONFIG_JOYSTICK_FSIA6B is not set # CONFIG_JOYSTICK_SENSEHAT is not set +# CONFIG_JOYSTICK_SEESAW is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=m @@ -2694,7 +2747,6 @@ CONFIG_TOUCHSCREEN_ADS7846=m # CONFIG_TOUCHSCREEN_CY8CTMA140 is not set # CONFIG_TOUCHSCREEN_CY8CTMG110 is not set # CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set -# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set # CONFIG_TOUCHSCREEN_CYTTSP5 is not set # CONFIG_TOUCHSCREEN_DYNAPRO is not set # CONFIG_TOUCHSCREEN_HAMPSHIRE is not set @@ -2704,6 +2756,8 @@ CONFIG_TOUCHSCREEN_EGALAX=m # CONFIG_TOUCHSCREEN_EXC3000 is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI is not set # CONFIG_TOUCHSCREEN_HIDEEP is not set # CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set # CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set @@ -2717,7 +2771,6 @@ CONFIG_TOUCHSCREEN_EGALAX=m # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set # CONFIG_TOUCHSCREEN_WACOM_I2C is not set # CONFIG_TOUCHSCREEN_MAX11801 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set # CONFIG_TOUCHSCREEN_MMS114 is not set # CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set # CONFIG_TOUCHSCREEN_MSG2638 is not set @@ -2849,7 +2902,6 @@ CONFIG_TTY=y CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set @@ -2946,7 +2998,6 @@ CONFIG_RASPBERRYPI_GPIOMEM=y # CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y -# CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y @@ -3056,6 +3107,7 @@ CONFIG_SPI_BCM2835AUX=m # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CH341 is not set CONFIG_SPI_DESIGNWARE=m CONFIG_SPI_DW_DMA=y # CONFIG_SPI_DW_PCI is not set @@ -3067,7 +3119,6 @@ CONFIG_SPI_DW_MMIO=m # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_PCI1XXXX is not set # CONFIG_SPI_PL022 is not set -# CONFIG_SPI_PXA2XX is not set # CONFIG_SPI_RP2040_GPIO_BRIDGE is not set # CONFIG_SPI_SC18IS602 is not set # CONFIG_SPI_SIFIVE is not set @@ -3110,6 +3161,7 @@ CONFIG_PINMUX=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_AW9523 is not set # CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_MCP23S08 is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set @@ -3219,16 +3271,25 @@ CONFIG_GPIO_FSM=y # CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers +# +# GPIO Debugging utilities +# +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set +# CONFIG_GPIO_VIRTUSER is not set +# end of GPIO Debugging utilities + CONFIG_W1=m # # 1-wire Bus Masters # +# CONFIG_W1_MASTER_AMD_AXI is not set # CONFIG_W1_MASTER_MATROX is not set # CONFIG_W1_MASTER_DS2490 is not set # CONFIG_W1_MASTER_DS2482 is not set CONFIG_W1_MASTER_GPIO=m # CONFIG_W1_MASTER_SGI is not set +# CONFIG_W1_MASTER_UART is not set # end of 1-wire Bus Masters # @@ -3265,6 +3326,7 @@ CONFIG_POWER_RESET_RESTART=y # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_SYSCON_REBOOT_MODE is not set # CONFIG_NVMEM_REBOOT_MODE is not set +# CONFIG_POWER_SEQUENCING is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y @@ -3282,8 +3344,8 @@ CONFIG_RPI_POE_POWER=m # CONFIG_CHARGER_SBS is not set # CONFIG_MANAGER_SBS is not set # CONFIG_BATTERY_BQ27XXX is not set -# CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_MAX1721X is not set # CONFIG_CHARGER_ISP1704 is not set # CONFIG_CHARGER_MAX8903 is not set @@ -3312,6 +3374,7 @@ CONFIG_RPI_POE_POWER=m # CONFIG_CHARGER_UCS1002 is not set # CONFIG_CHARGER_BD99954 is not set # CONFIG_BATTERY_UG3105 is not set +# CONFIG_FUEL_GAUGE_MM8013 is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set @@ -3321,7 +3384,6 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AD7314 is not set # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set @@ -3338,8 +3400,10 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CHIPCAP2 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set # CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DS620 is not set @@ -3349,6 +3413,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_F75375S is not set # CONFIG_SENSORS_FTSTEUTATES is not set +# CONFIG_SENSORS_GIGABYTE_WATERFORCE is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_G760A is not set @@ -3358,12 +3423,14 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_HS3001 is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWERZ is not set # CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LINEAGE is not set # CONFIG_SENSORS_LTC2945 is not set # CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2947_SPI is not set # CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2991 is not set # CONFIG_SENSORS_LTC2992 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set @@ -3371,6 +3438,7 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LTC4282 is not set # CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set @@ -3384,7 +3452,6 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_MAX6620 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_MAX6697 is not set # CONFIG_SENSORS_MAX31790 is not set @@ -3419,10 +3486,12 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_KRAKEN3 is not set # CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set +# CONFIG_SENSORS_PT5161L is not set CONFIG_SENSORS_PWM_FAN=y CONFIG_SENSORS_RASPBERRYPI_HWMON=y # CONFIG_SENSORS_SBTSI is not set @@ -3452,6 +3521,7 @@ CONFIG_SENSORS_RASPBERRYPI_HWMON=y # CONFIG_SENSORS_INA2XX is not set # CONFIG_SENSORS_INA238 is not set # CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP102 is not set @@ -3478,10 +3548,11 @@ CONFIG_SENSORS_RP1_ADC=m CONFIG_THERMAL=y # CONFIG_THERMAL_NETLINK is not set # CONFIG_THERMAL_STATISTICS is not set +# CONFIG_THERMAL_DEBUGFS is not set +# CONFIG_THERMAL_CORE_TESTING is not set CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y -# CONFIG_THERMAL_WRITABLE_TRIPS is not set CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set @@ -3572,6 +3643,7 @@ CONFIG_BCMA_DRIVER_GMAC_CMN=y # Multifunction device drivers # CONFIG_MFD_CORE=y +# CONFIG_MFD_ADP5585 is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_AS3711 is not set # CONFIG_MFD_SMPRO is not set @@ -3607,6 +3679,7 @@ CONFIG_MFD_CORE=y # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_MAX14577 is not set # CONFIG_MFD_MAX77541 is not set # CONFIG_MFD_MAX77620 is not set @@ -3691,10 +3764,13 @@ CONFIG_MFD_WM5102=y # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set # CONFIG_MFD_ATC260X_I2C is not set # CONFIG_MFD_QCOM_PM8008 is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_RAVE_SP_CORE is not set # CONFIG_MFD_INTEL_M10_BMC_SPI is not set CONFIG_MFD_RP1=y @@ -3707,6 +3783,7 @@ CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_NETLINK_EVENTS is not set # CONFIG_REGULATOR_88PG86X is not set # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set @@ -3728,6 +3805,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_LTC3589 is not set # CONFIG_REGULATOR_LTC3676 is not set # CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX77503 is not set # CONFIG_REGULATOR_MAX77857 is not set # CONFIG_REGULATOR_MAX8649 is not set # CONFIG_REGULATOR_MAX8660 is not set @@ -3864,7 +3942,6 @@ CONFIG_V4L2_ASYNC=m # Media controller options # CONFIG_MEDIA_CONTROLLER_DVB=y -CONFIG_MEDIA_CONTROLLER_REQUEST_API=y # end of Media controller options # @@ -4013,6 +4090,7 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # # Atmel media platform drivers # +# CONFIG_VIDEO_BCM2835_UNICAM_LEGACY is not set # CONFIG_VIDEO_BCM2835_UNICAM is not set # @@ -4041,6 +4119,10 @@ CONFIG_MEDIA_PLATFORM_DRIVERS=y # Microchip Technology, Inc. media platform drivers # +# +# Nuvoton media platform drivers +# + # # NVidia media platform drivers # @@ -4131,7 +4213,12 @@ CONFIG_MEDIA_ATTACH=y # CONFIG_VIDEO_IR_I2C=m CONFIG_VIDEO_CAMERA_SENSOR=y +# CONFIG_VIDEO_ALVIUM_CSI2 is not set # CONFIG_VIDEO_AR0521 is not set +# CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set +# CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_ARDUCAM_64MP is not set # CONFIG_VIDEO_ARDUCAM_PIVARIETY is not set # CONFIG_VIDEO_HI556 is not set @@ -4142,6 +4229,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -4156,6 +4244,7 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_IMX708 is not set # CONFIG_VIDEO_MT9M001 is not set # CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9M114 is not set # CONFIG_VIDEO_MT9P031 is not set # CONFIG_VIDEO_MT9T112 is not set # CONFIG_VIDEO_MT9V011 is not set @@ -4201,10 +4290,16 @@ CONFIG_VIDEO_CAMERA_SENSOR=y # CONFIG_VIDEO_S5C73M3 is not set # CONFIG_VIDEO_S5K5BAF is not set # CONFIG_VIDEO_S5K6A3 is not set -# CONFIG_VIDEO_ST_VGXY61 is not set +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_CCS is not set # CONFIG_VIDEO_ET8EK8 is not set +# +# Camera ISPs +# +# CONFIG_VIDEO_THP7312 is not set +# end of Camera ISPs + # # Lens drivers # @@ -4276,6 +4371,7 @@ CONFIG_VIDEO_SAA711X=m # CONFIG_VIDEO_TVP5150 is not set # CONFIG_VIDEO_TVP7002 is not set # CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9900 is not set # CONFIG_VIDEO_TW9903 is not set # CONFIG_VIDEO_TW9906 is not set # CONFIG_VIDEO_TW9910 is not set @@ -4337,6 +4433,8 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_DS90UB913 is not set # CONFIG_VIDEO_DS90UB953 is not set # CONFIG_VIDEO_DS90UB960 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # end of Video serializers and deserializers # @@ -4564,13 +4662,13 @@ CONFIG_DVB_SP2=m # # Graphics support # -CONFIG_VIDEO_CMDLINE=y -CONFIG_VIDEO_NOMODESET=y +CONFIG_VIDEO=y # CONFIG_AUXDISPLAY is not set CONFIG_DRM=y CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DEBUG_MM is not set CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_PANIC is not set # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set # CONFIG_DRM_DEBUG_MODESET_LOCK is not set CONFIG_DRM_FBDEV_EMULATION=y @@ -4578,9 +4676,10 @@ CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set CONFIG_DRM_LOAD_EDID_FIRMWARE=y CONFIG_DRM_DISPLAY_HELPER=y +# CONFIG_DRM_DISPLAY_DP_AUX_CEC is not set +# CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is not set CONFIG_DRM_DISPLAY_HDMI_HELPER=y -# CONFIG_DRM_DP_AUX_CHARDEV is not set -# CONFIG_DRM_DP_CEC is not set +CONFIG_DRM_DISPLAY_HDMI_STATE_HELPER=y CONFIG_DRM_TTM=y CONFIG_DRM_VRAM_HELPER=y CONFIG_DRM_TTM_HELPER=y @@ -4608,6 +4707,7 @@ CONFIG_DRM_SCHED=y # CONFIG_DRM_RADEON is not set # CONFIG_DRM_AMDGPU is not set # CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_XE is not set # CONFIG_DRM_VGEM is not set # CONFIG_DRM_VKMS is not set # CONFIG_DRM_VMWGFX is not set @@ -4626,33 +4726,40 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_AUO_A030JTN01 is not set # CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set # CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set # CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set -# CONFIG_DRM_PANEL_DSI_CM is not set -# CONFIG_DRM_PANEL_LVDS is not set -CONFIG_DRM_PANEL_SIMPLE=y -# CONFIG_DRM_PANEL_EDP is not set +# CONFIG_DRM_PANEL_BOE_TV101WUM_LL2 is not set # CONFIG_DRM_PANEL_EBBG_FT8719 is not set # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_DSI_CM is not set +# CONFIG_DRM_PANEL_LVDS is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set +# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set # CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set +# CONFIG_DRM_PANEL_JDI_LPM102A188A is not set # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set # CONFIG_DRM_PANEL_JDI_R63452 is not set # CONFIG_DRM_PANEL_KHADAS_TS050 is not set # CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set -# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_LG_SW43408 is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set # CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set @@ -4661,8 +4768,8 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set # CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set # CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set -# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set # CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set # CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set @@ -4671,16 +4778,20 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set # CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set # CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM69380 is not set # CONFIG_DRM_PANEL_RONBO_RB070D30 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set # CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set @@ -4695,15 +4806,18 @@ CONFIG_DRM_PANEL_SIMPLE=y # CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set # CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set # CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set +# CONFIG_DRM_PANEL_EDP is not set +CONFIG_DRM_PANEL_SIMPLE=y +# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set # CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set # CONFIG_DRM_PANEL_TPO_Y17P is not set # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set # CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set # CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set -# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN is not set # CONFIG_DRM_PANEL_WIDECHIPS_WS2401 is not set # CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set @@ -4760,7 +4874,6 @@ CONFIG_DRM_VC4_HDMI_CEC=y CONFIG_DRM_RP1_DSI=y CONFIG_DRM_RP1_DPI=y CONFIG_DRM_RP1_VEC=y -# CONFIG_DRM_LOONGSON is not set # CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_HISI_HIBMC is not set # CONFIG_DRM_HISI_KIRIN is not set @@ -4783,10 +4896,12 @@ CONFIG_DRM_RP1_VEC=y # CONFIG_DRM_PL111 is not set # CONFIG_DRM_LIMA is not set # CONFIG_DRM_PANFROST is not set +# CONFIG_DRM_PANTHOR is not set # CONFIG_DRM_TIDSS is not set # CONFIG_DRM_GUD is not set # CONFIG_DRM_SSD130X is not set -# CONFIG_DRM_LEGACY is not set +# CONFIG_DRM_POWERVR is not set +# CONFIG_DRM_WERROR is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y # @@ -4796,7 +4911,6 @@ CONFIG_FB=y # CONFIG_FB_BCM2708 is not set # CONFIG_FB_CIRRUS is not set # CONFIG_FB_PM2 is not set -# CONFIG_FB_ARMCLCD is not set # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_ASILIANT is not set # CONFIG_FB_IMSTT is not set @@ -4840,10 +4954,9 @@ CONFIG_FB_SYS_FILLRECT=y CONFIG_FB_SYS_COPYAREA=y CONFIG_FB_SYS_IMAGEBLIT=y # CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_SYS_FOPS=y +CONFIG_FB_SYSMEM_FOPS=y CONFIG_FB_DEFERRED_IO=y CONFIG_FB_DMAMEM_HELPERS=y -CONFIG_FB_IOMEM_FOPS=y CONFIG_FB_SYSMEM_HELPERS=y CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y # CONFIG_FB_MODE_HELPERS is not set @@ -4868,15 +4981,18 @@ CONFIG_LCD_CLASS_DEVICE=m # CONFIG_LCD_OTM3225A is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set # CONFIG_BACKLIGHT_PWM is not set CONFIG_BACKLIGHT_RPI=y # CONFIG_BACKLIGHT_QCOM_WLED is not set # CONFIG_BACKLIGHT_ADP8860 is not set # CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set # CONFIG_BACKLIGHT_LP855X is not set +# CONFIG_BACKLIGHT_MP3309C is not set CONFIG_BACKLIGHT_GPIO=y # CONFIG_BACKLIGHT_LV5207LP is not set # CONFIG_BACKLIGHT_BD6107 is not set @@ -4924,10 +5040,10 @@ CONFIG_SND_MAX_CARDS=32 # CONFIG_SND_SUPPORT_OLD_API is not set CONFIG_SND_PROC_FS=y CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set CONFIG_SND_CTL_FAST_LOOKUP=y # CONFIG_SND_DEBUG is not set # CONFIG_SND_CTL_INPUT_VALIDATION is not set +# CONFIG_SND_UTIMER is not set CONFIG_SND_VMASTER=y # CONFIG_SND_SEQUENCER is not set # CONFIG_SND_DRIVERS is not set @@ -5132,6 +5248,7 @@ CONFIG_SND_SOC_ADAU7002=m # CONFIG_SND_SOC_AK4458 is not set CONFIG_SND_SOC_AK4554=m # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -5139,6 +5256,8 @@ CONFIG_SND_SOC_AK4554=m # CONFIG_SND_SOC_AW8738 is not set # CONFIG_SND_SOC_AW88395 is not set # CONFIG_SND_SOC_AW88261 is not set +# CONFIG_SND_SOC_AW87390 is not set +# CONFIG_SND_SOC_AW88399 is not set # CONFIG_SND_SOC_BD28623 is not set # CONFIG_SND_SOC_BT_SCO is not set # CONFIG_SND_SOC_CHV3_CODEC is not set @@ -5171,12 +5290,14 @@ CONFIG_SND_SOC_CS42XX8_I2C=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set # CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CX2072X is not set CONFIG_SND_SOC_DA7213=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8326 is not set # CONFIG_SND_SOC_ES8328_I2C is not set @@ -5185,7 +5306,6 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_HDA is not set # CONFIG_SND_SOC_ICS43432 is not set # CONFIG_SND_SOC_IDT821034 is not set -# CONFIG_SND_SOC_INNO_RK3036 is not set CONFIG_SND_SOC_MA120X0P=m # CONFIG_SND_SOC_MAX98088 is not set # CONFIG_SND_SOC_MAX98090 is not set @@ -5216,14 +5336,15 @@ CONFIG_SND_SOC_PCM5102A=m CONFIG_SND_SOC_PCM512x=m CONFIG_SND_SOC_PCM512x_I2C=m # CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_PCM6240 is not set # CONFIG_SND_SOC_PEB2466 is not set -# CONFIG_SND_SOC_RK3328 is not set # CONFIG_SND_SOC_RT5616 is not set CONFIG_SND_SOC_PCM1794A=m # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5640 is not set # CONFIG_SND_SOC_RT5659 is not set # CONFIG_SND_SOC_RT9120 is not set +# CONFIG_SND_SOC_RTQ9128 is not set CONFIG_SND_SOC_SGTL5000=m CONFIG_SND_SOC_SIGMADSP=m CONFIG_SND_SOC_SIGMADSP_I2C=m @@ -5303,6 +5424,7 @@ CONFIG_SND_SOC_WM8960=m # CONFIG_SND_SOC_ZL38060 is not set # CONFIG_SND_SOC_MAX9759 is not set # CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6357 is not set # CONFIG_SND_SOC_MT6358 is not set # CONFIG_SND_SOC_MT6660 is not set # CONFIG_SND_SOC_NAU8315 is not set @@ -5367,6 +5489,7 @@ CONFIG_HID_EZKEY=y # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set # CONFIG_HID_HOLTEK is not set +# CONFIG_HID_GOODIX_SPI is not set # CONFIG_HID_GOOGLE_STADIA_FF is not set # CONFIG_HID_VIVALDI is not set # CONFIG_HID_GT683R is not set @@ -5408,7 +5531,6 @@ CONFIG_NINTENDO_FF=y # CONFIG_HID_NTRIG is not set # CONFIG_HID_NVIDIA_SHIELD is not set CONFIG_HID_ORTEK=y -CONFIG_HID_OUYA=y CONFIG_HID_PANTHERLORD=y CONFIG_PANTHERLORD_FF=y CONFIG_HID_PENMOUNT=y @@ -5446,6 +5568,7 @@ CONFIG_HID_TOPSEED=y # CONFIG_HID_U2FZERO is not set # CONFIG_HID_WACOM is not set CONFIG_HID_WIIMOTE=m +# CONFIG_HID_WINWING is not set CONFIG_HID_XINMO=y # CONFIG_HID_ZEROPLUS is not set CONFIG_HID_ZYDACRON=y @@ -5458,7 +5581,6 @@ CONFIG_HID_ZYDACRON=y # # HID-BPF support # -# CONFIG_HID_BPF is not set # end of HID-BPF support # @@ -5482,6 +5604,7 @@ CONFIG_USB_COMMON=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y CONFIG_USB_PCI=y +# CONFIG_USB_PCI_AMD is not set CONFIG_USB_ANNOUNCE_NEW_DEVICES=y # @@ -5495,6 +5618,7 @@ CONFIG_USB_DEFAULT_PERSIST=y # CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 CONFIG_USB_MON=m # @@ -5668,7 +5792,7 @@ CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_LINK_LAYER_TEST is not set # CONFIG_USB_CHAOSKEY is not set CONFIG_BRCM_USB_PINMAP=y -# CONFIG_USB_ONBOARD_HUB is not set +# CONFIG_USB_ONBOARD_DEV is not set # # USB Physical Layer drivers @@ -5789,11 +5913,14 @@ CONFIG_LEDS_PWM=y # CONFIG_LEDS_RT4505 is not set # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set +# CONFIG_LEDS_SY7802 is not set # # RGB LED drivers # # CONFIG_LEDS_GROUP_MULTICOLOR is not set +# CONFIG_LEDS_KTD202X is not set +# CONFIG_LEDS_NCP5623 is not set # CONFIG_LEDS_PWM_MULTICOLOR is not set # @@ -5806,6 +5933,7 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_BACKLIGHT=y CONFIG_LEDS_TRIGGER_CPU=y # CONFIG_LEDS_TRIGGER_ACTIVITY is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set CONFIG_LEDS_TRIGGER_DEFAULT_ON=y # @@ -5817,8 +5945,8 @@ CONFIG_LEDS_TRIGGER_INPUT=y # CONFIG_LEDS_TRIGGER_PANIC is not set # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set -# CONFIG_LEDS_TRIGGER_AUDIO is not set # CONFIG_LEDS_TRIGGER_TTY is not set +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set CONFIG_LEDS_TRIGGER_ACTPWR=y # @@ -5860,6 +5988,7 @@ CONFIG_RTC_DRV_DS1307=m # CONFIG_RTC_DRV_DS1672 is not set # CONFIG_RTC_DRV_HYM8563 is not set # CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_MAX31335 is not set # CONFIG_RTC_DRV_NCT3018Y is not set # CONFIG_RTC_DRV_RS5C372 is not set # CONFIG_RTC_DRV_ISL1208 is not set @@ -5876,12 +6005,14 @@ CONFIG_RTC_DRV_PCF8563=m # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8111 is not set # CONFIG_RTC_DRV_RX8581 is not set # CONFIG_RTC_DRV_RX8025 is not set # CONFIG_RTC_DRV_EM3027 is not set # CONFIG_RTC_DRV_RV3028 is not set # CONFIG_RTC_DRV_RV3032 is not set # CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD2405AL is not set # CONFIG_RTC_DRV_SD3078 is not set # @@ -5968,6 +6099,7 @@ CONFIG_DW_AXI_DMAC=y # CONFIG_XILINX_XDMA is not set # CONFIG_XILINX_ZYNQMP_DMA is not set # CONFIG_XILINX_ZYNQMP_DPDMA is not set +# CONFIG_AMD_QDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set # CONFIG_DW_DMAC is not set @@ -6013,8 +6145,6 @@ CONFIG_VHOST_MENU=y # CONFIG_GREYBUS is not set # CONFIG_COMEDI is not set CONFIG_STAGING=y -# CONFIG_PRISM2_USB is not set -# CONFIG_RTL8192U is not set # CONFIG_RTLLIB is not set CONFIG_RTL8723BS=m CONFIG_R8712U=m @@ -6026,21 +6156,23 @@ CONFIG_STAGING_MEDIA=y # CONFIG_DVB_AV7110 is not set # CONFIG_VIDEO_MAX96712 is not set CONFIG_VIDEO_RPIVID=m + +# +# StarFive media platform drivers +# # CONFIG_STAGING_MEDIA_DEPRECATED is not set -# CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set # CONFIG_FB_TFT is not set -# CONFIG_KS7010 is not set # CONFIG_BCM_VIDEOCORE is not set -# CONFIG_PI433 is not set # CONFIG_XIL_AXIS_FIFO is not set # CONFIG_FIELDBUS_DEV is not set -# CONFIG_QLGE is not set # CONFIG_VME_BUS is not set # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set CONFIG_SURFACE_PLATFORMS=y +CONFIG_ARM64_PLATFORM_DEVICES=y CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y @@ -6100,6 +6232,7 @@ CONFIG_ARM_TIMER_SP804=y CONFIG_MAILBOX=y # CONFIG_ARM_MHU is not set # CONFIG_ARM_MHU_V2 is not set +# CONFIG_ARM_MHU_V3 is not set # CONFIG_PLATFORM_MHU is not set # CONFIG_PL320_MBOX is not set # CONFIG_ALTERA_MBOX is not set @@ -6155,8 +6288,6 @@ CONFIG_BCM2712_IOMMU=y # # Broadcom SoC drivers # -CONFIG_BCM2835_POWER=y -CONFIG_RASPBERRYPI_POWER=y CONFIG_SOC_BRCMSTB=y # end of Broadcom SoC drivers @@ -6197,6 +6328,33 @@ CONFIG_SOC_BRCMSTB=y # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers +# +# PM Domains +# + +# +# Amlogic PM Domains +# +# end of Amlogic PM Domains + +# +# Broadcom PM Domains +# +CONFIG_BCM2835_POWER=y +CONFIG_RASPBERRYPI_POWER=y +# end of Broadcom PM Domains + +# +# i.MX PM Domains +# +# end of i.MX PM Domains + +# +# Qualcomm PM Domains +# +# end of Qualcomm PM Domains +# end of PM Domains + # CONFIG_PM_DEVFREQ is not set CONFIG_EXTCON=y @@ -6205,6 +6363,7 @@ CONFIG_EXTCON=y # # CONFIG_EXTCON_FSA9480 is not set # CONFIG_EXTCON_GPIO is not set +# CONFIG_EXTCON_LC824206XA is not set # CONFIG_EXTCON_MAX3355 is not set # CONFIG_EXTCON_PTN5150 is not set # CONFIG_EXTCON_RT8973A is not set @@ -6214,7 +6373,6 @@ CONFIG_EXTCON=y # CONFIG_IIO is not set # CONFIG_NTB is not set CONFIG_PWM=y -CONFIG_PWM_SYSFS=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL_TCB is not set CONFIG_PWM_BCM2835=m @@ -6237,12 +6395,13 @@ CONFIG_ARM_GIC_MAX_NR=1 CONFIG_ARM_GIC_V2M=y CONFIG_ARM_GIC_V3=y CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y +CONFIG_IRQ_MSI_LIB=y # CONFIG_AL_FIC is not set CONFIG_BCM2712_MIP=y CONFIG_BCM7038_L1_IRQ=y CONFIG_BCM7120_L2_IRQ=y CONFIG_BRCMSTB_L2_IRQ=y +# CONFIG_LAN966X_OIC is not set # CONFIG_XILINX_INTC is not set CONFIG_PARTITION_PERCPU=y # end of IRQ chip support @@ -6252,6 +6411,7 @@ CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y CONFIG_RESET_BRCMSTB=y CONFIG_RESET_BRCMSTB_RESCAL=y +# CONFIG_RESET_GPIO is not set CONFIG_RESET_RASPBERRYPI=y CONFIG_RESET_SIMPLE=y # CONFIG_RESET_TI_SYSCON is not set @@ -6294,6 +6454,7 @@ CONFIG_PHY_BRCM_USB=y # CONFIG_ARM_CCI_PMU is not set # CONFIG_ARM_CCN is not set # CONFIG_ARM_CMN is not set +# CONFIG_ARM_NI is not set CONFIG_ARM_PMU=y # CONFIG_ARM_SMMU_V3_PMU is not set CONFIG_ARM_PMUV3=y @@ -6302,6 +6463,7 @@ CONFIG_ARM_PMUV3=y CONFIG_RPI_AXIPERF=m # CONFIG_HISI_PCIE_PMU is not set # CONFIG_HNS3_PMU is not set +# CONFIG_DWC_PCIE_PMU is not set # CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set # end of Performance monitor support @@ -6318,12 +6480,14 @@ CONFIG_RAS=y # CONFIG_DAX is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y +CONFIG_NVMEM_LAYOUTS=y # # Layout Types # # CONFIG_NVMEM_LAYOUT_SL28_VPD is not set # CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set +# CONFIG_NVMEM_LAYOUT_U_BOOT_ENV is not set # end of Layout Types CONFIG_NVMEM_RASPBERRYPI_OTP=y @@ -6357,6 +6521,7 @@ CONFIG_PM_OPP=y CONFIG_DCACHE_WORD_ACCESS=y CONFIG_VALIDATE_FS_PARSER=y CONFIG_FS_IOMAP=y +CONFIG_FS_STACK=y CONFIG_BUFFER_HEAD=y CONFIG_LEGACY_DIRECT_IO=y # CONFIG_EXT2_FS is not set @@ -6391,13 +6556,13 @@ CONFIG_XFS_SUPPORT_ASCII_CI=y # CONFIG_OCFS2_FS is not set CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y -# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set # CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set # CONFIG_BTRFS_DEBUG is not set # CONFIG_BTRFS_ASSERT is not set # CONFIG_BTRFS_FS_REF_VERIFY is not set # CONFIG_NILFS2_FS is not set # CONFIG_F2FS_FS is not set +# CONFIG_BCACHEFS_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y # CONFIG_EXPORTFS_BLOCK_OPS is not set @@ -6413,6 +6578,7 @@ CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m # CONFIG_CUSE is not set # CONFIG_VIRTIO_FS is not set +CONFIG_FUSE_PASSTHROUGH=y CONFIG_OVERLAY_FS=m # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -6426,9 +6592,9 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # CONFIG_NETFS_SUPPORT=y # CONFIG_NETFS_STATS is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set -# CONFIG_FSCACHE_DEBUG is not set # CONFIG_CACHEFILES is not set # end of Caches @@ -6452,11 +6618,11 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" -# CONFIG_NTFS_FS is not set CONFIG_NTFS3_FS=m # CONFIG_NTFS3_64BIT_CLUSTER is not set # CONFIG_NTFS3_LZX_XPRESS is not set # CONFIG_NTFS3_FS_POSIX_ACL is not set +# CONFIG_NTFS_FS is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -6574,6 +6740,7 @@ CONFIG_CIFS_DEBUG=y # CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y # CONFIG_CIFS_ROOT is not set +# CONFIG_CIFS_COMPRESSION is not set # CONFIG_SMB_SERVER is not set CONFIG_SMBFS=y # CONFIG_CODA_FS is not set @@ -6736,7 +6903,6 @@ CONFIG_CRYPTO_ECC=m CONFIG_CRYPTO_ECDH=m # CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set -# CONFIG_CRYPTO_SM2 is not set # CONFIG_CRYPTO_CURVE25519 is not set # end of Public-key cryptography @@ -6769,14 +6935,12 @@ CONFIG_CRYPTO_SM4=m # CONFIG_CRYPTO_ARC4 is not set # CONFIG_CRYPTO_CHACHA20 is not set CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CFB=m CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_CTS=m CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_HCTR2 is not set # CONFIG_CRYPTO_KEYWRAP is not set # CONFIG_CRYPTO_LRW is not set -CONFIG_CRYPTO_OFB=m # CONFIG_CRYPTO_PCBC is not set # CONFIG_CRYPTO_XTS is not set # end of Length-preserving ciphers and modes @@ -6848,7 +7012,9 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y -# CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE is not set +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64 +CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32 +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 CONFIG_CRYPTO_KDF800108_CTR=y # end of Random number generation @@ -6931,7 +7097,6 @@ CONFIG_GENERIC_NET_UTILS=y CONFIG_CORDIC=m # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y -CONFIG_GENERIC_PCI_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y @@ -6990,11 +7155,13 @@ CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y # CONFIG_XZ_DEC_X86 is not set # CONFIG_XZ_DEC_POWERPC is not set -# CONFIG_XZ_DEC_IA64 is not set # CONFIG_XZ_DEC_ARM is not set # CONFIG_XZ_DEC_ARMTHUMB is not set +CONFIG_XZ_DEC_ARM64=y # CONFIG_XZ_DEC_SPARC is not set +CONFIG_XZ_DEC_RISCV=y # CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_BCJ=y # CONFIG_XZ_DEC_TEST is not set CONFIG_GENERIC_ALLOCATOR=y CONFIG_REED_SOLOMON=y @@ -7006,19 +7173,19 @@ CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y -CONFIG_DMA_OPS=y +CONFIG_DMA_OPS_HELPERS=y CONFIG_NEED_SG_DMA_FLAGS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_DMA_DECLARE_COHERENT=y CONFIG_ARCH_HAS_SETUP_DMA_OPS=y -CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y CONFIG_SWIOTLB=y # CONFIG_SWIOTLB_DYNAMIC is not set +CONFIG_DMA_NEED_SYNC=y # CONFIG_DMA_RESTRICTED_POOL is not set CONFIG_DMA_NONCOHERENT_MMAP=y CONFIG_DMA_COHERENT_POOL=y @@ -7053,6 +7220,7 @@ CONFIG_UCS2_STRING=y CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y CONFIG_GENERIC_VDSO_TIME_NS=y +CONFIG_VDSO_GETRANDOM=y CONFIG_FONT_SUPPORT=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y @@ -7060,7 +7228,9 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_STACKWALK=y CONFIG_STACKDEPOT=y +CONFIG_STACKDEPOT_MAX_FRAMES=64 CONFIG_SBITMAP=y +# CONFIG_LWQ_TEST is not set # end of Library routines CONFIG_GENERIC_IOREMAP=y @@ -7092,7 +7262,7 @@ CONFIG_DEBUG_MISC=y # # Compile-time checks and compiler options # -CONFIG_AS_HAS_NON_CONST_LEB128=y +CONFIG_AS_HAS_NON_CONST_ULEB128=y CONFIG_DEBUG_INFO_NONE=y # CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set # CONFIG_DEBUG_INFO_DWARF4 is not set @@ -7123,7 +7293,7 @@ CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +CONFIG_ARCH_HAS_UBSAN=y # CONFIG_UBSAN is not set CONFIG_HAVE_ARCH_KCSAN=y CONFIG_HAVE_KCSAN_COMPILER=y @@ -7167,6 +7337,7 @@ CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y @@ -7256,6 +7427,7 @@ CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set # CONFIG_LATENCYTOP is not set # CONFIG_DEBUG_CGROUP_REF is not set +CONFIG_USER_STACKTRACE_SUPPORT=y CONFIG_NOP_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y @@ -7316,6 +7488,7 @@ CONFIG_FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY=y # CONFIG_RING_BUFFER_BENCHMARK is not set # CONFIG_TRACE_EVAL_MAP_FILE is not set # CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_VALIDATE_RCU_IS_WATCHING is not set # CONFIG_FTRACE_STARTUP_TEST is not set # CONFIG_RING_BUFFER_STARTUP_TEST is not set # CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set From f0d6755d4d03b6a93d0cc3dc60874239db8be482 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Mon, 18 Nov 2024 15:59:27 +0100 Subject: [PATCH 3/9] linux (RPi): update to 6.12-12856cc Signed-off-by: Matthias Reichl --- packages/linux/package.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/packages/linux/package.mk b/packages/linux/package.mk index 79238c3691..4cb9e174ea 100644 --- a/packages/linux/package.mk +++ b/packages/linux/package.mk @@ -23,8 +23,8 @@ case "${LINUX}" in PKG_PATCH_DIRS="default rtlwifi/after-6.12" ;; raspberrypi) - PKG_VERSION="2ac3d763e26c01e287b77353e2158594e0910778" # 6.12-rc7 - PKG_SHA256="8f17e885c7649639f8e6e35c0e436f22029af02d875f594b453a3d832ff1619c" + PKG_VERSION="12856cc6850854a062b7aa2ee55786257e266168" # 6.12 + PKG_SHA256="6c356294ca761559eda1670f11d6c0e4ee39c07795092bdafc255b4e62aee7e1" PKG_URL="https://github.com/raspberrypi/linux/archive/${PKG_VERSION}.tar.gz" PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz" PKG_PATCH_DIRS="raspberrypi rtlwifi/after-6.12" From f279aa836a58709b28821d9d83771cb297e51102 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Mon, 18 Nov 2024 15:59:27 +0100 Subject: [PATCH 4/9] linux (RPi): config options for 6.12-12856cc Signed-off-by: Matthias Reichl --- projects/RPi/devices/RPi/linux/linux.arm.conf | 3 ++- projects/RPi/devices/RPi2/linux/linux.arm.conf | 3 ++- projects/RPi/devices/RPi4/linux/linux.aarch64.conf | 3 ++- projects/RPi/devices/RPi5/linux/linux.aarch64.conf | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/projects/RPi/devices/RPi/linux/linux.arm.conf b/projects/RPi/devices/RPi/linux/linux.arm.conf index 1b264e2b48..c7cbf20fd3 100644 --- a/projects/RPi/devices/RPi/linux/linux.arm.conf +++ b/projects/RPi/devices/RPi/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 6.12.0-rc7 Kernel Configuration +# Linux/arm 6.12.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GCC) 13.0.0 20220604 (experimental) [master revision aec868578d8515763d75693c1fdfbc30ff0a1e68]" CONFIG_CC_IS_GCC=y @@ -405,6 +405,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="" CONFIG_ARCH_SUPPORTS_KEXEC=y CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y +CONFIG_ARCH_DEFAULT_CRASH_DUMP=y CONFIG_AUTO_ZRELADDR=y # CONFIG_EFI is not set # end of Boot options diff --git a/projects/RPi/devices/RPi2/linux/linux.arm.conf b/projects/RPi/devices/RPi2/linux/linux.arm.conf index c4591fca08..cb96e92cc2 100644 --- a/projects/RPi/devices/RPi2/linux/linux.arm.conf +++ b/projects/RPi/devices/RPi2/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 6.12.0-rc7 Kernel Configuration +# Linux/arm 6.12.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GCC) 13.0.0 20220604 (experimental) [master revision aec868578d8515763d75693c1fdfbc30ff0a1e68]" CONFIG_CC_IS_GCC=y @@ -514,6 +514,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0 # CONFIG_ARM_APPENDED_DTB is not set CONFIG_CMDLINE="" CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y +CONFIG_ARCH_DEFAULT_CRASH_DUMP=y CONFIG_AUTO_ZRELADDR=y # CONFIG_EFI is not set # end of Boot options diff --git a/projects/RPi/devices/RPi4/linux/linux.aarch64.conf b/projects/RPi/devices/RPi4/linux/linux.aarch64.conf index bc216a5430..3f34ea0190 100644 --- a/projects/RPi/devices/RPi4/linux/linux.aarch64.conf +++ b/projects/RPi/devices/RPi4/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.12.0-rc7 Kernel Configuration +# Linux/arm64 6.12.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GCC) 13.0.0 20220604 (experimental) [master revision aec868578d8515763d75693c1fdfbc30ff0a1e68]" CONFIG_CC_IS_GCC=y @@ -433,6 +433,7 @@ CONFIG_ARCH_SUPPORTS_KEXEC_SIG=y CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG=y CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y +CONFIG_ARCH_DEFAULT_CRASH_DUMP=y # CONFIG_XEN is not set CONFIG_ARCH_FORCE_MAX_ORDER=10 CONFIG_UNMAP_KERNEL_AT_EL0=y diff --git a/projects/RPi/devices/RPi5/linux/linux.aarch64.conf b/projects/RPi/devices/RPi5/linux/linux.aarch64.conf index eb82e53057..ad980e4a93 100644 --- a/projects/RPi/devices/RPi5/linux/linux.aarch64.conf +++ b/projects/RPi/devices/RPi5/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.12.0-rc7 Kernel Configuration +# Linux/arm64 6.12.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (GCC) 13.0.0 20220604 (experimental) [master revision aec868578d8515763d75693c1fdfbc30ff0a1e68]" CONFIG_CC_IS_GCC=y @@ -435,6 +435,7 @@ CONFIG_ARCH_SUPPORTS_KEXEC_SIG=y CONFIG_ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG=y CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y CONFIG_ARCH_SUPPORTS_CRASH_DUMP=y +CONFIG_ARCH_DEFAULT_CRASH_DUMP=y # CONFIG_XEN is not set CONFIG_ARCH_FORCE_MAX_ORDER=11 CONFIG_UNMAP_KERNEL_AT_EL0=y From 9cf1dde50cb3d1297fdda12bdf840a874f4abfa8 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Thu, 21 Nov 2024 20:07:34 +0100 Subject: [PATCH 5/9] linux (RPi): update to 6.12-ab9bb48 Signed-off-by: Matthias Reichl --- packages/linux/package.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/packages/linux/package.mk b/packages/linux/package.mk index 4cb9e174ea..bdcecba34e 100644 --- a/packages/linux/package.mk +++ b/packages/linux/package.mk @@ -23,8 +23,8 @@ case "${LINUX}" in PKG_PATCH_DIRS="default rtlwifi/after-6.12" ;; raspberrypi) - PKG_VERSION="12856cc6850854a062b7aa2ee55786257e266168" # 6.12 - PKG_SHA256="6c356294ca761559eda1670f11d6c0e4ee39c07795092bdafc255b4e62aee7e1" + PKG_VERSION="ab9bb48bcf5bebc8a75df84fc992096ed9d1c57b" # 6.12 + PKG_SHA256="1478648c5527c7d13a5612bdeaae7a31f9e957ea411ca4d361b4fdb738009339" PKG_URL="https://github.com/raspberrypi/linux/archive/${PKG_VERSION}.tar.gz" PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz" PKG_PATCH_DIRS="raspberrypi rtlwifi/after-6.12" From 149564e19cc8d8c0f444a0872d559f31f820c94e Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Thu, 21 Nov 2024 20:07:34 +0100 Subject: [PATCH 6/9] linux (RPi): update to 6.12-ab9bb48 Signed-off-by: Matthias Reichl --- projects/RPi/devices/RPi/linux/linux.arm.conf | 1 + projects/RPi/devices/RPi2/linux/linux.arm.conf | 1 + projects/RPi/devices/RPi4/linux/linux.aarch64.conf | 1 + projects/RPi/devices/RPi5/linux/linux.aarch64.conf | 4 ++++ 4 files changed, 7 insertions(+) diff --git a/projects/RPi/devices/RPi/linux/linux.arm.conf b/projects/RPi/devices/RPi/linux/linux.arm.conf index c7cbf20fd3..3ed7d73c94 100644 --- a/projects/RPi/devices/RPi/linux/linux.arm.conf +++ b/projects/RPi/devices/RPi/linux/linux.arm.conf @@ -1376,6 +1376,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # Misc devices # CONFIG_BCM2835_SMI=m +# CONFIG_RP1_PIO is not set # CONFIG_AD525X_DPOT is not set # CONFIG_DUMMY_IRQ is not set # CONFIG_RPMB is not set diff --git a/projects/RPi/devices/RPi2/linux/linux.arm.conf b/projects/RPi/devices/RPi2/linux/linux.arm.conf index cb96e92cc2..518f3f0ba5 100644 --- a/projects/RPi/devices/RPi2/linux/linux.arm.conf +++ b/projects/RPi/devices/RPi2/linux/linux.arm.conf @@ -1573,6 +1573,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # Misc devices # CONFIG_BCM2835_SMI=m +# CONFIG_RP1_PIO is not set # CONFIG_AD525X_DPOT is not set # CONFIG_DUMMY_IRQ is not set # CONFIG_RPMB is not set diff --git a/projects/RPi/devices/RPi4/linux/linux.aarch64.conf b/projects/RPi/devices/RPi4/linux/linux.aarch64.conf index 3f34ea0190..bb6debb4fc 100644 --- a/projects/RPi/devices/RPi4/linux/linux.aarch64.conf +++ b/projects/RPi/devices/RPi4/linux/linux.aarch64.conf @@ -1815,6 +1815,7 @@ CONFIG_BLK_DEV_NVME=y # Misc devices # CONFIG_BCM2835_SMI=m +# CONFIG_RP1_PIO is not set # CONFIG_AD525X_DPOT is not set # CONFIG_DUMMY_IRQ is not set # CONFIG_PHANTOM is not set diff --git a/projects/RPi/devices/RPi5/linux/linux.aarch64.conf b/projects/RPi/devices/RPi5/linux/linux.aarch64.conf index ad980e4a93..a84ecfa5f9 100644 --- a/projects/RPi/devices/RPi5/linux/linux.aarch64.conf +++ b/projects/RPi/devices/RPi5/linux/linux.aarch64.conf @@ -1725,6 +1725,7 @@ CONFIG_GENERIC_ARCH_NUMA=y CONFIG_DMIID=y # CONFIG_DMI_SYSFS is not set CONFIG_RASPBERRYPI_FIRMWARE=y +CONFIG_FIRMWARE_RP1=m # CONFIG_FW_CFG_SYSFS is not set # CONFIG_SYSFB_SIMPLEFB is not set # CONFIG_ARM_FFA_TRANSPORT is not set @@ -1821,6 +1822,7 @@ CONFIG_BLK_DEV_NVME=y # Misc devices # CONFIG_BCM2835_SMI=m +CONFIG_RP1_PIO=m # CONFIG_AD525X_DPOT is not set # CONFIG_DUMMY_IRQ is not set # CONFIG_PHANTOM is not set @@ -6239,6 +6241,7 @@ CONFIG_MAILBOX=y # CONFIG_ALTERA_MBOX is not set CONFIG_BCM2835_MBOX=y # CONFIG_MAILBOX_TEST is not set +CONFIG_MBOX_RP1=m CONFIG_IOMMU_IOVA=y CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y @@ -6383,6 +6386,7 @@ CONFIG_PWM_BRCMSTB=y # CONFIG_PWM_FSL_FTM is not set CONFIG_PWM_GPIO=m # CONFIG_PWM_PCA9685 is not set +CONFIG_PWM_PIO_RP1=m CONFIG_PWM_RASPBERRYPI_POE=m CONFIG_PWM_RP1=y # CONFIG_PWM_XILINX is not set From 21a079f70b727db6cb80a5f0d70ffbd1a6fff5f5 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Fri, 22 Nov 2024 21:41:33 +0100 Subject: [PATCH 7/9] linux (RPi): update to 6.12-521f2ba Signed-off-by: Matthias Reichl --- packages/linux/package.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/packages/linux/package.mk b/packages/linux/package.mk index bdcecba34e..6ae5ac1e10 100644 --- a/packages/linux/package.mk +++ b/packages/linux/package.mk @@ -23,8 +23,8 @@ case "${LINUX}" in PKG_PATCH_DIRS="default rtlwifi/after-6.12" ;; raspberrypi) - PKG_VERSION="ab9bb48bcf5bebc8a75df84fc992096ed9d1c57b" # 6.12 - PKG_SHA256="1478648c5527c7d13a5612bdeaae7a31f9e957ea411ca4d361b4fdb738009339" + PKG_VERSION="521f2baed818c04981fd61b275c996a8ef03b833" # 6.12 + PKG_SHA256="7dc120ed828ab5d9adff848f699865c776c291f80af90f0d9b81d8905601a4a0" PKG_URL="https://github.com/raspberrypi/linux/archive/${PKG_VERSION}.tar.gz" PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz" PKG_PATCH_DIRS="raspberrypi rtlwifi/after-6.12" From 2fea27fd89d86115b5fd45e320c725d84557a6b4 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Fri, 22 Nov 2024 22:38:20 +0100 Subject: [PATCH 8/9] linux: drop old rtlwifi patches RPi was the last project using those Signed-off-by: Matthias Reichl --- ...i-rtlwifi-Move-code-from-rtl8192de-t.patch | 11050 ---------------- ...i-rtlwifi-Clean-up-rtl8192d-common-a.patch | 1749 --- ...i-rtlwifi-Adjust-rtl8192d-common-for.patch | 683 - ...i-rtlwifi-Ignore-IEEE80211_CONF_CHAN.patch | 52 - ...8-Shared-module-for-rtw8723x-devices.patch | 2324 ---- ...tw88-Debug-output-for-rtw8723x-EFUSE.patch | 231 - ...rtw88-Add-definitions-for-8703b-chip.patch | 106 - .../0011-6.10-wifi-rtw88-Add-rtw8703b.c.patch | 2132 --- ...w88-8703b-Fix-reported-RX-band-width.patch | 36 - ...i-rtlwifi-rtl8192d-Use-rtl92d-prefix.patch | 701 - ...ifi-rtlwifi-Add-rtl8192du-table.-c-h.patch | 1735 --- ...i-rtlwifi-Add-new-members-to-struct-.patch | 39 - ...1-wifi-rtlwifi-Add-rtl8192du-hw.-c-h.patch | 1264 -- ...-wifi-rtlwifi-Add-rtl8192du-phy.-c-h.patch | 3186 ----- ...-wifi-rtlwifi-Add-rtl8192du-trx.-c-h.patch | 462 - ...1-wifi-rtlwifi-Add-rtl8192du-rf.-c-h.patch | 282 - ...i-rtlwifi-Add-rtl8192du-fw.-c-h-and-.patch | 139 - ...1-wifi-rtlwifi-Add-rtl8192du-dm.-c-h.patch | 161 - ...i-rtlwifi-Constify-rtl_hal_cfg.-ops-.patch | 106 - ...6.11-wifi-rtlwifi-Add-rtl8192du-sw.c.patch | 417 - ...i-rtlwifi-Enable-the-new-rtl8192du-d.patch | 92 - ...usb-Further-limit-the-TX-aggregation.patch | 164 - ...tw88-usb-Simplify-rtw_usb_write_data.patch | 51 - ...upport-USB-3-with-RTL8822CU-RTL8822B.patch | 303 - ...-Parse-channel-from-IE-to-correct-in.patch | 168 - ...nit-RX-burst-length-according-to-USB.patch | 81 - ...pdate-the-RX-stats-after-every-frame.patch | 36 - ...ifi-rtw88-usb-Support-RX-aggregation.patch | 123 - ...e-USB-RX-aggregation-for-8822c-8822b.patch | 182 - ...anup-few-rtlxxxx_set_hw_reg-routines.patch | 142 - ...ove-unreachable-code-in-rtl92d_dm_ch.patch | 62 - ...i-simplify-TX-command-fill-callbacks.patch | 413 - ...tlwifi-drop-unused-const_amdpci_aspm.patch | 182 - ...8192de-Don-t-read-register-in-_rtl92.patch | 50 - ...-Remove-rtl_intf_ops.read_efuse_byte.patch | 66 - ...rtl_usb-Store-the-endpoint-addresses.patch | 259 - ...tweak-CCK-TX-filter-setting-for-SRRC.patch | 156 - ...fine-power-parameters-for-RFE-type-5.patch | 52 - ...dd-to-check-if-debug-mask-is-enabled.patch | 46 - ...-debug-information-in-abnormal-state.patch | 234 - 40 files changed, 29717 deletions(-) delete mode 100644 packages/linux/patches/rtlwifi/6.10/0004-6.10-wifi-rtlwifi-Move-code-from-rtl8192de-t.patch delete mode 100644 packages/linux/patches/rtlwifi/6.10/0005-6.10-wifi-rtlwifi-Clean-up-rtl8192d-common-a.patch delete mode 100644 packages/linux/patches/rtlwifi/6.10/0006-6.10-wifi-rtlwifi-Adjust-rtl8192d-common-for.patch delete mode 100644 packages/linux/patches/rtlwifi/6.10/0007-6.10-wifi-rtlwifi-Ignore-IEEE80211_CONF_CHAN.patch delete mode 100644 packages/linux/patches/rtlwifi/6.10/0008-6.10-wifi-rtw88-Shared-module-for-rtw8723x-devices.patch delete mode 100644 packages/linux/patches/rtlwifi/6.10/0009-6.10-wifi-rtw88-Debug-output-for-rtw8723x-EFUSE.patch delete mode 100644 packages/linux/patches/rtlwifi/6.10/0010-6.10-wifi-rtw88-Add-definitions-for-8703b-chip.patch delete mode 100644 packages/linux/patches/rtlwifi/6.10/0011-6.10-wifi-rtw88-Add-rtw8703b.c.patch delete mode 100644 packages/linux/patches/rtlwifi/6.11.2/0001-6.11.2-wifi-rtw88-8703b-Fix-reported-RX-band-width.patch delete mode 100644 packages/linux/patches/rtlwifi/6.11/0001-6.11-wifi-rtlwifi-rtl8192d-Use-rtl92d-prefix.patch delete mode 100644 packages/linux/patches/rtlwifi/6.11/0002-6.11-wifi-rtlwifi-Add-rtl8192du-table.-c-h.patch delete mode 100644 packages/linux/patches/rtlwifi/6.11/0003-6.11-wifi-rtlwifi-Add-new-members-to-struct-.patch delete mode 100644 packages/linux/patches/rtlwifi/6.11/0004-6.11-wifi-rtlwifi-Add-rtl8192du-hw.-c-h.patch delete mode 100644 packages/linux/patches/rtlwifi/6.11/0005-6.11-wifi-rtlwifi-Add-rtl8192du-phy.-c-h.patch delete mode 100644 packages/linux/patches/rtlwifi/6.11/0006-6.11-wifi-rtlwifi-Add-rtl8192du-trx.-c-h.patch delete mode 100644 packages/linux/patches/rtlwifi/6.11/0007-6.11-wifi-rtlwifi-Add-rtl8192du-rf.-c-h.patch delete mode 100644 packages/linux/patches/rtlwifi/6.11/0008-6.11-wifi-rtlwifi-Add-rtl8192du-fw.-c-h-and-.patch delete mode 100644 packages/linux/patches/rtlwifi/6.11/0009-6.11-wifi-rtlwifi-Add-rtl8192du-dm.-c-h.patch delete mode 100644 packages/linux/patches/rtlwifi/6.11/0010-6.11-wifi-rtlwifi-Constify-rtl_hal_cfg.-ops-.patch delete mode 100644 packages/linux/patches/rtlwifi/6.11/0011-6.11-wifi-rtlwifi-Add-rtl8192du-sw.c.patch delete mode 100644 packages/linux/patches/rtlwifi/6.11/0012-6.11-wifi-rtlwifi-Enable-the-new-rtl8192du-d.patch delete mode 100644 packages/linux/patches/rtlwifi/6.11/0013-6.11-wifi-rtw88-usb-Further-limit-the-TX-aggregation.patch delete mode 100644 packages/linux/patches/rtlwifi/6.11/0014-6.11-wifi-rtw88-usb-Simplify-rtw_usb_write_data.patch delete mode 100644 packages/linux/patches/rtlwifi/6.12/0001-6.12-wifi-rtw88-usb-Support-USB-3-with-RTL8822CU-RTL8822B.patch delete mode 100644 packages/linux/patches/rtlwifi/6.12/0003-6.12-wifi-rtw88-8822c-Parse-channel-from-IE-to-correct-in.patch delete mode 100644 packages/linux/patches/rtlwifi/6.12/0004-6.12-wifi-rtw88-usb-Init-RX-burst-length-according-to-USB.patch delete mode 100644 packages/linux/patches/rtlwifi/6.12/0005-6.12-wifi-rtw88-usb-Update-the-RX-stats-after-every-frame.patch delete mode 100644 packages/linux/patches/rtlwifi/6.12/0006-6.12-wifi-rtw88-usb-Support-RX-aggregation.patch delete mode 100644 packages/linux/patches/rtlwifi/6.12/0007-6.12-wifi-rtw88-Enable-USB-RX-aggregation-for-8822c-8822b.patch delete mode 100644 packages/linux/patches/rtlwifi/6.9/0001-wifi-rtlwifi-cleanup-few-rtlxxxx_set_hw_reg-routines.patch delete mode 100644 packages/linux/patches/rtlwifi/6.9/0002-wifi-rtlwifi-remove-unreachable-code-in-rtl92d_dm_ch.patch delete mode 100644 packages/linux/patches/rtlwifi/6.9/0003-wifi-rtlwifi-simplify-TX-command-fill-callbacks.patch delete mode 100644 packages/linux/patches/rtlwifi/6.9/0004-wifi-rtlwifi-drop-unused-const_amdpci_aspm.patch delete mode 100644 packages/linux/patches/rtlwifi/6.9/0005-wifi-rtlwifi-rtl8192de-Don-t-read-register-in-_rtl92.patch delete mode 100644 packages/linux/patches/rtlwifi/6.9/0006-wifi-rtlwifi-Remove-rtl_intf_ops.read_efuse_byte.patch delete mode 100644 packages/linux/patches/rtlwifi/6.9/0007-wifi-rtlwifi-rtl_usb-Store-the-endpoint-addresses.patch delete mode 100644 packages/linux/patches/rtlwifi/6.9/0008-wifi-rtw88-8821c-tweak-CCK-TX-filter-setting-for-SRRC.patch delete mode 100644 packages/linux/patches/rtlwifi/6.9/0009-wifi-rtw88-8822ce-refine-power-parameters-for-RFE-type-5.patch delete mode 100644 packages/linux/patches/rtlwifi/6.9/0010-wifi-rtw88-debug-add-to-check-if-debug-mask-is-enabled.patch delete mode 100644 packages/linux/patches/rtlwifi/6.9/0011-wifi-rtw88-dump-firmware-debug-information-in-abnormal-state.patch diff --git a/packages/linux/patches/rtlwifi/6.10/0004-6.10-wifi-rtlwifi-Move-code-from-rtl8192de-t.patch b/packages/linux/patches/rtlwifi/6.10/0004-6.10-wifi-rtlwifi-Move-code-from-rtl8192de-t.patch deleted file mode 100644 index db97f4d1a4..0000000000 --- a/packages/linux/patches/rtlwifi/6.10/0004-6.10-wifi-rtlwifi-Move-code-from-rtl8192de-t.patch +++ /dev/null @@ -1,11050 +0,0 @@ -From eb9c40199ae9ae29f43705a11b7a0dba79dcfb8b Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 25 Apr 2024 21:14:04 +0300 -Subject: [PATCH 04/07] 6.10: wifi: rtlwifi: Move code from rtl8192de - to rtl8192d-common - -Create the new module rtl8192d-common and move some code into it from -rtl8192de. Now the rtl8192de driver (PCI) and the new rtl8192du driver -(USB) can share some of the code. - -This is mostly the code that required little effort to make it -shareable. There are a few more functions which they could share, with -more changes. - -Add phy_iq_calibrate member to struct rtl_hal_ops to allow moving the -TX power tracking code from dm.c. - -The other changes in this patch are adjusting whitespace, renaming some -functions, making some arrays const, and making checkpatch.pl less -unhappy. - -rtl8192de is compile-tested only. rtl8192d-common is tested with the -new rtl8192du driver. - -Signed-off-by: Bitterblue Smith -Signed-off-by: Ping-Ke Shih -Link: https://msgid.link/69c4358a-6fbf-4433-92a6-341c83e9dd48@gmail.com ---- - drivers/net/wireless/realtek/rtlwifi/Kconfig | 4 + - drivers/net/wireless/realtek/rtlwifi/Makefile | 1 + - drivers/net/wireless/realtek/rtlwifi/cam.c | 5 +- - drivers/net/wireless/realtek/rtlwifi/cam.h | 6 +- - .../realtek/rtlwifi/rtl8192d/Makefile | 11 + - .../rtlwifi/{rtl8192de => rtl8192d}/def.h | 0 - .../realtek/rtlwifi/rtl8192d/dm_common.c | 1079 +++++++++++++++ - .../realtek/rtlwifi/rtl8192d/dm_common.h | 100 ++ - .../realtek/rtlwifi/rtl8192d/fw_common.c | 369 +++++ - .../realtek/rtlwifi/rtl8192d/fw_common.h | 39 + - .../realtek/rtlwifi/rtl8192d/hw_common.c | 1191 +++++++++++++++++ - .../realtek/rtlwifi/rtl8192d/hw_common.h | 24 + - .../wireless/realtek/rtlwifi/rtl8192d/main.c | 9 + - .../realtek/rtlwifi/rtl8192d/phy_common.c | 846 ++++++++++++ - .../realtek/rtlwifi/rtl8192d/phy_common.h | 87 ++ - .../rtlwifi/{rtl8192de => rtl8192d}/reg.h | 0 - .../realtek/rtlwifi/rtl8192d/rf_common.c | 353 +++++ - .../realtek/rtlwifi/rtl8192d/rf_common.h | 13 + - .../realtek/rtlwifi/rtl8192d/trx_common.c | 515 +++++++ - .../realtek/rtlwifi/rtl8192d/trx_common.h | 405 ++++++ - .../wireless/realtek/rtlwifi/rtl8192de/dm.c | 1072 +-------------- - .../wireless/realtek/rtlwifi/rtl8192de/dm.h | 91 +- - .../wireless/realtek/rtlwifi/rtl8192de/fw.c | 375 +----- - .../wireless/realtek/rtlwifi/rtl8192de/fw.h | 37 - - .../wireless/realtek/rtlwifi/rtl8192de/hw.c | 1168 +--------------- - .../wireless/realtek/rtlwifi/rtl8192de/hw.h | 11 - - .../wireless/realtek/rtlwifi/rtl8192de/led.c | 2 +- - .../wireless/realtek/rtlwifi/rtl8192de/phy.c | 918 +------------ - .../wireless/realtek/rtlwifi/rtl8192de/phy.h | 59 +- - .../wireless/realtek/rtlwifi/rtl8192de/rf.c | 375 +----- - .../wireless/realtek/rtlwifi/rtl8192de/rf.h | 5 - - .../wireless/realtek/rtlwifi/rtl8192de/sw.c | 12 +- - .../wireless/realtek/rtlwifi/rtl8192de/trx.c | 514 +------ - .../wireless/realtek/rtlwifi/rtl8192de/trx.h | 396 ------ - drivers/net/wireless/realtek/rtlwifi/wifi.h | 1 + - 35 files changed, 5166 insertions(+), 4927 deletions(-) - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/Makefile - rename drivers/net/wireless/realtek/rtlwifi/{rtl8192de => rtl8192d}/def.h (100%) - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.c - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.h - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.h - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/main.c - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.h - rename drivers/net/wireless/realtek/rtlwifi/{rtl8192de => rtl8192d}/reg.h (100%) - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.c - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.h - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h - -diff --git a/drivers/net/wireless/realtek/rtlwifi/Kconfig b/drivers/net/wireless/realtek/rtlwifi/Kconfig -index 9f6a4e35543c..cfe63f7b28d9 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/Kconfig -+++ b/drivers/net/wireless/realtek/rtlwifi/Kconfig -@@ -37,6 +37,7 @@ config RTL8192SE - config RTL8192DE - tristate "Realtek RTL8192DE/RTL8188DE PCIe Wireless Network Adapter" - depends on PCI -+ select RTL8192D_COMMON - select RTLWIFI - select RTLWIFI_PCI - help -@@ -142,6 +143,9 @@ config RTL8192C_COMMON - depends on RTL8192CE || RTL8192CU - default y - -+config RTL8192D_COMMON -+ tristate -+ - config RTL8723_COMMON - tristate - depends on RTL8723AE || RTL8723BE -diff --git a/drivers/net/wireless/realtek/rtlwifi/Makefile b/drivers/net/wireless/realtek/rtlwifi/Makefile -index 09c30e428375..423981b148df 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/Makefile -+++ b/drivers/net/wireless/realtek/rtlwifi/Makefile -@@ -23,6 +23,7 @@ obj-$(CONFIG_RTL8192C_COMMON) += rtl8192c/ - obj-$(CONFIG_RTL8192CE) += rtl8192ce/ - obj-$(CONFIG_RTL8192CU) += rtl8192cu/ - obj-$(CONFIG_RTL8192SE) += rtl8192se/ -+obj-$(CONFIG_RTL8192D_COMMON) += rtl8192d/ - obj-$(CONFIG_RTL8192DE) += rtl8192de/ - obj-$(CONFIG_RTL8723AE) += rtl8723ae/ - obj-$(CONFIG_RTL8723BE) += rtl8723be/ -diff --git a/drivers/net/wireless/realtek/rtlwifi/cam.c b/drivers/net/wireless/realtek/rtlwifi/cam.c -index 32970ea4b4e7..f9d0d1394442 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/cam.c -+++ b/drivers/net/wireless/realtek/rtlwifi/cam.c -@@ -18,7 +18,8 @@ void rtl_cam_reset_sec_info(struct ieee80211_hw *hw) - } - - static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no, -- u8 *mac_addr, u8 *key_cont_128, u16 us_config) -+ const u8 *mac_addr, u8 *key_cont_128, -+ u16 us_config) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - -@@ -94,7 +95,7 @@ static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no, - "after set key, usconfig:%x\n", us_config); - } - --u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr, -+u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, const u8 *mac_addr, - u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg, - u32 ul_default_key, u8 *key_content) - { -diff --git a/drivers/net/wireless/realtek/rtlwifi/cam.h b/drivers/net/wireless/realtek/rtlwifi/cam.h -index 2461fa9afda0..144807a405b7 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/cam.h -+++ b/drivers/net/wireless/realtek/rtlwifi/cam.h -@@ -14,9 +14,9 @@ - #define CAM_CONFIG_NO_USEDK 0 - - void rtl_cam_reset_all_entry(struct ieee80211_hw *hw); --u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr, -- u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg, -- u32 ul_default_key, u8 *key_content); -+u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, const u8 *mac_addr, -+ u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg, -+ u32 ul_default_key, u8 *key_content); - int rtl_cam_delete_one_entry(struct ieee80211_hw *hw, u8 *mac_addr, - u32 ul_key_id); - void rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/Makefile b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/Makefile -new file mode 100644 -index 000000000000..beebdfa3f7ff ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/Makefile -@@ -0,0 +1,11 @@ -+# SPDX-License-Identifier: GPL-2.0 -+rtl8192d-common-objs := \ -+ dm_common.o \ -+ fw_common.o \ -+ hw_common.o \ -+ main.o \ -+ phy_common.o \ -+ rf_common.o \ -+ trx_common.o -+ -+obj-$(CONFIG_RTL8192D_COMMON) += rtl8192d-common.o -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/def.h -similarity index 100% -rename from drivers/net/wireless/realtek/rtlwifi/rtl8192de/def.h -rename to drivers/net/wireless/realtek/rtlwifi/rtl8192d/def.h -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.c -new file mode 100644 -index 000000000000..d376e4584454 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.c -@@ -0,0 +1,1079 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright(c) 2009-2012 Realtek Corporation.*/ -+ -+#include "../wifi.h" -+#include "../base.h" -+#include "../core.h" -+#include "reg.h" -+#include "def.h" -+#include "phy_common.h" -+#include "dm_common.h" -+ -+#define UNDEC_SM_PWDB entry_min_undec_sm_pwdb -+ -+static const u32 ofdmswing_table[OFDM_TABLE_SIZE_92D] = { -+ 0x7f8001fe, /* 0, +6.0dB */ -+ 0x788001e2, /* 1, +5.5dB */ -+ 0x71c001c7, /* 2, +5.0dB */ -+ 0x6b8001ae, /* 3, +4.5dB */ -+ 0x65400195, /* 4, +4.0dB */ -+ 0x5fc0017f, /* 5, +3.5dB */ -+ 0x5a400169, /* 6, +3.0dB */ -+ 0x55400155, /* 7, +2.5dB */ -+ 0x50800142, /* 8, +2.0dB */ -+ 0x4c000130, /* 9, +1.5dB */ -+ 0x47c0011f, /* 10, +1.0dB */ -+ 0x43c0010f, /* 11, +0.5dB */ -+ 0x40000100, /* 12, +0dB */ -+ 0x3c8000f2, /* 13, -0.5dB */ -+ 0x390000e4, /* 14, -1.0dB */ -+ 0x35c000d7, /* 15, -1.5dB */ -+ 0x32c000cb, /* 16, -2.0dB */ -+ 0x300000c0, /* 17, -2.5dB */ -+ 0x2d4000b5, /* 18, -3.0dB */ -+ 0x2ac000ab, /* 19, -3.5dB */ -+ 0x288000a2, /* 20, -4.0dB */ -+ 0x26000098, /* 21, -4.5dB */ -+ 0x24000090, /* 22, -5.0dB */ -+ 0x22000088, /* 23, -5.5dB */ -+ 0x20000080, /* 24, -6.0dB */ -+ 0x1e400079, /* 25, -6.5dB */ -+ 0x1c800072, /* 26, -7.0dB */ -+ 0x1b00006c, /* 27. -7.5dB */ -+ 0x19800066, /* 28, -8.0dB */ -+ 0x18000060, /* 29, -8.5dB */ -+ 0x16c0005b, /* 30, -9.0dB */ -+ 0x15800056, /* 31, -9.5dB */ -+ 0x14400051, /* 32, -10.0dB */ -+ 0x1300004c, /* 33, -10.5dB */ -+ 0x12000048, /* 34, -11.0dB */ -+ 0x11000044, /* 35, -11.5dB */ -+ 0x10000040, /* 36, -12.0dB */ -+ 0x0f00003c, /* 37, -12.5dB */ -+ 0x0e400039, /* 38, -13.0dB */ -+ 0x0d800036, /* 39, -13.5dB */ -+ 0x0cc00033, /* 40, -14.0dB */ -+ 0x0c000030, /* 41, -14.5dB */ -+ 0x0b40002d, /* 42, -15.0dB */ -+}; -+ -+static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = { -+ {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ -+ {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ -+ {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ -+ {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ -+ {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ -+ {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ -+ {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ -+ {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ -+ {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ -+ {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ -+ {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ -+ {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ -+ {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ -+ {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ -+ {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ -+ {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ -+ {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ -+ {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ -+ {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ -+ {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ -+ {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ -+ {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ -+ {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ -+ {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ -+ {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ -+ {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ -+ {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ -+ {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ -+ {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ -+ {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ -+ {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ -+ {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ -+ {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ -+}; -+ -+static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = { -+ {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ -+ {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ -+ {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ -+ {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ -+ {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ -+ {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ -+ {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ -+ {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ -+ {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ -+ {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ -+ {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ -+ {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ -+ {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */ -+ {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ -+ {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ -+ {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ -+ {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ -+ {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ -+ {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ -+ {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ -+ {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ -+ {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ -+ {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ -+ {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ -+ {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ -+ {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ -+ {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ -+ {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ -+ {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ -+ {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ -+ {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ -+ {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ -+ {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ -+}; -+ -+static void rtl92d_dm_rxgain_tracking_thermalmeter(struct ieee80211_hw *hw) -+{ -+ static const u8 index_mapping[RX_INDEX_MAPPING_NUM] = { -+ 0x0f, 0x0f, 0x0d, 0x0c, 0x0b, -+ 0x0a, 0x09, 0x08, 0x07, 0x06, -+ 0x05, 0x04, 0x04, 0x03, 0x02 -+ }; -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 u4tmp; -+ int i; -+ -+ u4tmp = (index_mapping[(rtlpriv->efuse.eeprom_thermalmeter - -+ rtlpriv->dm.thermalvalue_rxgain)]) << 12; -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -+ "===> Rx Gain %x\n", u4tmp); -+ for (i = RF90_PATH_A; i < rtlpriv->phy.num_total_rfpath; i++) -+ rtl_set_rfreg(hw, i, 0x3C, RFREG_OFFSET_MASK, -+ (rtlpriv->phy.reg_rf3c[i] & (~(0xF000))) | u4tmp); -+} -+ -+static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg, -+ u8 *cck_index_old) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ unsigned long flag = 0; -+ const u8 *cckswing; -+ long temp_cck; -+ int i; -+ -+ /* Query CCK default setting From 0xa24 */ -+ rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); -+ temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2, -+ MASKDWORD) & MASKCCK; -+ rtl92d_release_cckandrw_pagea_ctl(hw, &flag); -+ for (i = 0; i < CCK_TABLE_LENGTH; i++) { -+ if (rtlpriv->dm.cck_inch14) -+ cckswing = &cckswing_table_ch14[i][2]; -+ else -+ cckswing = &cckswing_table_ch1ch13[i][2]; -+ -+ if (temp_cck == le32_to_cpu(*((__le32 *)cckswing))) { -+ *cck_index_old = (u8)i; -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -+ "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch14 %d\n", -+ RCCK0_TXFILTER2, temp_cck, -+ *cck_index_old, -+ rtlpriv->dm.cck_inch14); -+ break; -+ } -+ } -+ *temp_cckg = temp_cck; -+} -+ -+static void rtl92d_bandtype_5G(struct rtl_hal *rtlhal, u8 *ofdm_index, -+ bool *internal_pa, u8 thermalvalue, u8 delta, -+ u8 rf, struct rtl_efuse *rtlefuse, -+ struct rtl_priv *rtlpriv, struct rtl_phy *rtlphy, -+ const u8 index_mapping[5][INDEX_MAPPING_NUM], -+ const u8 index_mapping_pa[8][INDEX_MAPPING_NUM]) -+{ -+ u8 offset = 0; -+ u8 index; -+ int i; -+ -+ for (i = 0; i < rf; i++) { -+ if (rtlhal->macphymode == DUALMAC_DUALPHY && -+ rtlhal->interfaceindex == 1) /* MAC 1 5G */ -+ *internal_pa = rtlefuse->internal_pa_5g[1]; -+ else -+ *internal_pa = rtlefuse->internal_pa_5g[i]; -+ if (*internal_pa) { -+ if (rtlhal->interfaceindex == 1 || i == rf) -+ offset = 4; -+ else -+ offset = 0; -+ if (rtlphy->current_channel >= 100 && -+ rtlphy->current_channel <= 165) -+ offset += 2; -+ } else { -+ if (rtlhal->interfaceindex == 1 || i == rf) -+ offset = 2; -+ else -+ offset = 0; -+ } -+ if (thermalvalue > rtlefuse->eeprom_thermalmeter) -+ offset++; -+ if (*internal_pa) { -+ if (delta > INDEX_MAPPING_NUM - 1) -+ index = index_mapping_pa[offset] -+ [INDEX_MAPPING_NUM - 1]; -+ else -+ index = -+ index_mapping_pa[offset][delta]; -+ } else { -+ if (delta > INDEX_MAPPING_NUM - 1) -+ index = -+ index_mapping[offset][INDEX_MAPPING_NUM - 1]; -+ else -+ index = index_mapping[offset][delta]; -+ } -+ if (thermalvalue > rtlefuse->eeprom_thermalmeter) { -+ if (*internal_pa && thermalvalue > 0x12) { -+ ofdm_index[i] = rtlpriv->dm.ofdm_index[i] - -+ ((delta / 2) * 3 + (delta % 2)); -+ } else { -+ ofdm_index[i] -= index; -+ } -+ } else { -+ ofdm_index[i] += index; -+ } -+ } -+} -+ -+static void -+rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) -+{ -+ static const u8 index_mapping[5][INDEX_MAPPING_NUM] = { -+ /* 5G, path A/MAC 0, decrease power */ -+ {0, 1, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, -+ /* 5G, path A/MAC 0, increase power */ -+ {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, -+ /* 5G, path B/MAC 1, decrease power */ -+ {0, 2, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, -+ /* 5G, path B/MAC 1, increase power */ -+ {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, -+ /* 2.4G, for decreas power */ -+ {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10}, -+ }; -+ static const u8 index_mapping_internal_pa[8][INDEX_MAPPING_NUM] = { -+ /* 5G, path A/MAC 0, ch36-64, decrease power */ -+ {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, -+ /* 5G, path A/MAC 0, ch36-64, increase power */ -+ {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, -+ /* 5G, path A/MAC 0, ch100-165, decrease power */ -+ {0, 1, 2, 3, 5, 6, 8, 10, 11, 13, 14, 15, 15}, -+ /* 5G, path A/MAC 0, ch100-165, increase power */ -+ {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, -+ /* 5G, path B/MAC 1, ch36-64, decrease power */ -+ {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, -+ /* 5G, path B/MAC 1, ch36-64, increase power */ -+ {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, -+ /* 5G, path B/MAC 1, ch100-165, decrease power */ -+ {0, 1, 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 14}, -+ /* 5G, path B/MAC 1, ch100-165, increase power */ -+ {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, -+ }; -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u8 thermalvalue, delta, delta_lck, delta_iqk, delta_rxgain; -+ u8 offset, thermalvalue_avg_count = 0; -+ u32 thermalvalue_avg = 0; -+ bool internal_pa = false; -+ long ele_a = 0, ele_d, temp_cck, val_x, value32; -+ long val_y, ele_c = 0; -+ u8 ofdm_index[2]; -+ s8 cck_index = 0; -+ u8 ofdm_index_old[2] = {0, 0}; -+ s8 cck_index_old = 0; -+ u8 index; -+ int i; -+ bool is2t = IS_92D_SINGLEPHY(rtlhal->version); -+ u8 ofdm_min_index = 6, ofdm_min_index_internal_pa = 3, rf; -+ u8 indexforchannel = -+ rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel); -+ -+ rtlpriv->dm.txpower_trackinginit = true; -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "\n"); -+ thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0xf800); -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -+ "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n", -+ thermalvalue, -+ rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter); -+ -+ if (!thermalvalue) -+ goto exit; -+ -+ if (is2t) -+ rf = 2; -+ else -+ rf = 1; -+ -+ if (rtlpriv->dm.thermalvalue && !rtlhal->reloadtxpowerindex) -+ goto old_index_done; -+ -+ ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) & MASKOFDM_D; -+ for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { -+ if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) { -+ ofdm_index_old[0] = (u8)i; -+ -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -+ "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n", -+ ROFDM0_XATXIQIMBALANCE, -+ ele_d, ofdm_index_old[0]); -+ break; -+ } -+ } -+ if (is2t) { -+ ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, -+ MASKDWORD) & MASKOFDM_D; -+ for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { -+ if (ele_d == -+ (ofdmswing_table[i] & MASKOFDM_D)) { -+ ofdm_index_old[1] = (u8)i; -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, -+ DBG_LOUD, -+ "Initial pathB ele_d reg 0x%x = 0x%lx, ofdm_index = 0x%x\n", -+ ROFDM0_XBTXIQIMBALANCE, ele_d, -+ ofdm_index_old[1]); -+ break; -+ } -+ } -+ } -+ if (rtlhal->current_bandtype == BAND_ON_2_4G) { -+ rtl92d_bandtype_2_4G(hw, &temp_cck, &cck_index_old); -+ } else { -+ temp_cck = 0x090e1317; -+ cck_index_old = 12; -+ } -+ -+ if (!rtlpriv->dm.thermalvalue) { -+ rtlpriv->dm.thermalvalue = rtlefuse->eeprom_thermalmeter; -+ rtlpriv->dm.thermalvalue_lck = thermalvalue; -+ rtlpriv->dm.thermalvalue_iqk = thermalvalue; -+ rtlpriv->dm.thermalvalue_rxgain = rtlefuse->eeprom_thermalmeter; -+ for (i = 0; i < rf; i++) -+ rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; -+ rtlpriv->dm.cck_index = cck_index_old; -+ } -+ if (rtlhal->reloadtxpowerindex) { -+ for (i = 0; i < rf; i++) -+ rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; -+ rtlpriv->dm.cck_index = cck_index_old; -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -+ "reload ofdm index for band switch\n"); -+ } -+old_index_done: -+ for (i = 0; i < rf; i++) -+ ofdm_index[i] = rtlpriv->dm.ofdm_index[i]; -+ -+ rtlpriv->dm.thermalvalue_avg -+ [rtlpriv->dm.thermalvalue_avg_index] = thermalvalue; -+ rtlpriv->dm.thermalvalue_avg_index++; -+ if (rtlpriv->dm.thermalvalue_avg_index == AVG_THERMAL_NUM) -+ rtlpriv->dm.thermalvalue_avg_index = 0; -+ for (i = 0; i < AVG_THERMAL_NUM; i++) { -+ if (rtlpriv->dm.thermalvalue_avg[i]) { -+ thermalvalue_avg += rtlpriv->dm.thermalvalue_avg[i]; -+ thermalvalue_avg_count++; -+ } -+ } -+ if (thermalvalue_avg_count) -+ thermalvalue = (u8)(thermalvalue_avg / thermalvalue_avg_count); -+ if (rtlhal->reloadtxpowerindex) { -+ delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? -+ (thermalvalue - rtlefuse->eeprom_thermalmeter) : -+ (rtlefuse->eeprom_thermalmeter - thermalvalue); -+ rtlhal->reloadtxpowerindex = false; -+ rtlpriv->dm.done_txpower = false; -+ } else if (rtlpriv->dm.done_txpower) { -+ delta = (thermalvalue > rtlpriv->dm.thermalvalue) ? -+ (thermalvalue - rtlpriv->dm.thermalvalue) : -+ (rtlpriv->dm.thermalvalue - thermalvalue); -+ } else { -+ delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? -+ (thermalvalue - rtlefuse->eeprom_thermalmeter) : -+ (rtlefuse->eeprom_thermalmeter - thermalvalue); -+ } -+ delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ? -+ (thermalvalue - rtlpriv->dm.thermalvalue_lck) : -+ (rtlpriv->dm.thermalvalue_lck - thermalvalue); -+ delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ? -+ (thermalvalue - rtlpriv->dm.thermalvalue_iqk) : -+ (rtlpriv->dm.thermalvalue_iqk - thermalvalue); -+ delta_rxgain = -+ (thermalvalue > rtlpriv->dm.thermalvalue_rxgain) ? -+ (thermalvalue - rtlpriv->dm.thermalvalue_rxgain) : -+ (rtlpriv->dm.thermalvalue_rxgain - thermalvalue); -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -+ "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n", -+ thermalvalue, rtlpriv->dm.thermalvalue, -+ rtlefuse->eeprom_thermalmeter, delta, delta_lck, -+ delta_iqk); -+ if (delta_lck > rtlefuse->delta_lck && rtlefuse->delta_lck != 0) { -+ rtlpriv->dm.thermalvalue_lck = thermalvalue; -+ rtlpriv->cfg->ops->phy_lc_calibrate(hw, is2t); -+ } -+ -+ if (delta == 0 || !rtlpriv->dm.txpower_track_control) -+ goto check_delta; -+ -+ rtlpriv->dm.done_txpower = true; -+ delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? -+ (thermalvalue - rtlefuse->eeprom_thermalmeter) : -+ (rtlefuse->eeprom_thermalmeter - thermalvalue); -+ if (rtlhal->current_bandtype == BAND_ON_2_4G) { -+ offset = 4; -+ if (delta > INDEX_MAPPING_NUM - 1) -+ index = index_mapping[offset][INDEX_MAPPING_NUM - 1]; -+ else -+ index = index_mapping[offset][delta]; -+ if (thermalvalue > rtlpriv->dm.thermalvalue) { -+ for (i = 0; i < rf; i++) -+ ofdm_index[i] -= delta; -+ cck_index -= delta; -+ } else { -+ for (i = 0; i < rf; i++) -+ ofdm_index[i] += index; -+ cck_index += index; -+ } -+ } else if (rtlhal->current_bandtype == BAND_ON_5G) { -+ rtl92d_bandtype_5G(rtlhal, ofdm_index, -+ &internal_pa, thermalvalue, -+ delta, rf, rtlefuse, rtlpriv, -+ rtlphy, index_mapping, -+ index_mapping_internal_pa); -+ } -+ if (is2t) { -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -+ "temp OFDM_A_index=0x%x, OFDM_B_index = 0x%x,cck_index=0x%x\n", -+ rtlpriv->dm.ofdm_index[0], -+ rtlpriv->dm.ofdm_index[1], -+ rtlpriv->dm.cck_index); -+ } else { -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -+ "temp OFDM_A_index=0x%x,cck_index = 0x%x\n", -+ rtlpriv->dm.ofdm_index[0], -+ rtlpriv->dm.cck_index); -+ } -+ for (i = 0; i < rf; i++) { -+ if (ofdm_index[i] > OFDM_TABLE_SIZE_92D - 1) { -+ ofdm_index[i] = OFDM_TABLE_SIZE_92D - 1; -+ } else if (internal_pa || -+ rtlhal->current_bandtype == BAND_ON_2_4G) { -+ if (ofdm_index[i] < ofdm_min_index_internal_pa) -+ ofdm_index[i] = ofdm_min_index_internal_pa; -+ } else if (ofdm_index[i] < ofdm_min_index) { -+ ofdm_index[i] = ofdm_min_index; -+ } -+ } -+ if (rtlhal->current_bandtype == BAND_ON_2_4G) { -+ if (cck_index > CCK_TABLE_SIZE - 1) -+ cck_index = CCK_TABLE_SIZE - 1; -+ else if (cck_index < 0) -+ cck_index = 0; -+ } -+ if (is2t) { -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -+ "new OFDM_A_index=0x%x, OFDM_B_index = 0x%x, cck_index=0x%x\n", -+ ofdm_index[0], ofdm_index[1], -+ cck_index); -+ } else { -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -+ "new OFDM_A_index=0x%x,cck_index = 0x%x\n", -+ ofdm_index[0], cck_index); -+ } -+ ele_d = (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22; -+ val_x = rtlphy->iqk_matrix[indexforchannel].value[0][0]; -+ val_y = rtlphy->iqk_matrix[indexforchannel].value[0][1]; -+ if (val_x != 0) { -+ if ((val_x & 0x00000200) != 0) -+ val_x = val_x | 0xFFFFFC00; -+ ele_a = ((val_x * ele_d) >> 8) & 0x000003FF; -+ -+ /* new element C = element D x Y */ -+ if ((val_y & 0x00000200) != 0) -+ val_y = val_y | 0xFFFFFC00; -+ ele_c = ((val_y * ele_d) >> 8) & 0x000003FF; -+ -+ /* write new elements A, C, D to regC80 and -+ * regC94, element B is always 0 -+ */ -+ value32 = (ele_d << 22) | ((ele_c & 0x3F) << 16) | ele_a; -+ rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, -+ MASKDWORD, value32); -+ -+ value32 = (ele_c & 0x000003C0) >> 6; -+ rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, -+ value32); -+ -+ value32 = ((val_x * ele_d) >> 7) & 0x01; -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), -+ value32); -+ -+ } else { -+ rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, -+ MASKDWORD, -+ ofdmswing_table[(u8)ofdm_index[0]]); -+ rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, -+ 0x00); -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, -+ BIT(24), 0x00); -+ } -+ -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -+ "TxPwrTracking for interface %d path A: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xe94 = 0x%lx 0xe9c = 0x%lx\n", -+ rtlhal->interfaceindex, -+ val_x, val_y, ele_a, ele_c, ele_d, -+ val_x, val_y); -+ -+ if (cck_index >= CCK_TABLE_SIZE) -+ cck_index = CCK_TABLE_SIZE - 1; -+ if (cck_index < 0) -+ cck_index = 0; -+ if (rtlhal->current_bandtype == BAND_ON_2_4G) { -+ /* Adjust CCK according to IQK result */ -+ if (!rtlpriv->dm.cck_inch14) { -+ rtl_write_byte(rtlpriv, 0xa22, -+ cckswing_table_ch1ch13[cck_index][0]); -+ rtl_write_byte(rtlpriv, 0xa23, -+ cckswing_table_ch1ch13[cck_index][1]); -+ rtl_write_byte(rtlpriv, 0xa24, -+ cckswing_table_ch1ch13[cck_index][2]); -+ rtl_write_byte(rtlpriv, 0xa25, -+ cckswing_table_ch1ch13[cck_index][3]); -+ rtl_write_byte(rtlpriv, 0xa26, -+ cckswing_table_ch1ch13[cck_index][4]); -+ rtl_write_byte(rtlpriv, 0xa27, -+ cckswing_table_ch1ch13[cck_index][5]); -+ rtl_write_byte(rtlpriv, 0xa28, -+ cckswing_table_ch1ch13[cck_index][6]); -+ rtl_write_byte(rtlpriv, 0xa29, -+ cckswing_table_ch1ch13[cck_index][7]); -+ } else { -+ rtl_write_byte(rtlpriv, 0xa22, -+ cckswing_table_ch14[cck_index][0]); -+ rtl_write_byte(rtlpriv, 0xa23, -+ cckswing_table_ch14[cck_index][1]); -+ rtl_write_byte(rtlpriv, 0xa24, -+ cckswing_table_ch14[cck_index][2]); -+ rtl_write_byte(rtlpriv, 0xa25, -+ cckswing_table_ch14[cck_index][3]); -+ rtl_write_byte(rtlpriv, 0xa26, -+ cckswing_table_ch14[cck_index][4]); -+ rtl_write_byte(rtlpriv, 0xa27, -+ cckswing_table_ch14[cck_index][5]); -+ rtl_write_byte(rtlpriv, 0xa28, -+ cckswing_table_ch14[cck_index][6]); -+ rtl_write_byte(rtlpriv, 0xa29, -+ cckswing_table_ch14[cck_index][7]); -+ } -+ } -+ if (is2t) { -+ ele_d = (ofdmswing_table[ofdm_index[1]] & 0xFFC00000) >> 22; -+ val_x = rtlphy->iqk_matrix[indexforchannel].value[0][4]; -+ val_y = rtlphy->iqk_matrix[indexforchannel].value[0][5]; -+ if (val_x != 0) { -+ if ((val_x & 0x00000200) != 0) -+ /* consider minus */ -+ val_x = val_x | 0xFFFFFC00; -+ ele_a = ((val_x * ele_d) >> 8) & 0x000003FF; -+ /* new element C = element D x Y */ -+ if ((val_y & 0x00000200) != 0) -+ val_y = val_y | 0xFFFFFC00; -+ ele_c = ((val_y * ele_d) >> 8) & 0x00003FF; -+ /* write new elements A, C, D to regC88 -+ * and regC9C, element B is always 0 -+ */ -+ value32 = (ele_d << 22) | ((ele_c & 0x3F) << 16) | ele_a; -+ rtl_set_bbreg(hw, -+ ROFDM0_XBTXIQIMBALANCE, -+ MASKDWORD, value32); -+ value32 = (ele_c & 0x000003C0) >> 6; -+ rtl_set_bbreg(hw, ROFDM0_XDTXAFE, -+ MASKH4BITS, value32); -+ value32 = ((val_x * ele_d) >> 7) & 0x01; -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, -+ BIT(28), value32); -+ } else { -+ rtl_set_bbreg(hw, -+ ROFDM0_XBTXIQIMBALANCE, -+ MASKDWORD, -+ ofdmswing_table[ofdm_index[1]]); -+ rtl_set_bbreg(hw, ROFDM0_XDTXAFE, -+ MASKH4BITS, 0x00); -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, -+ BIT(28), 0x00); -+ } -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -+ "TxPwrTracking path B: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xeb4 = 0x%lx 0xebc = 0x%lx\n", -+ val_x, val_y, ele_a, ele_c, -+ ele_d, val_x, val_y); -+ } -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -+ "TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", -+ rtl_get_bbreg(hw, 0xc80, MASKDWORD), -+ rtl_get_bbreg(hw, 0xc94, MASKDWORD), -+ rtl_get_rfreg(hw, RF90_PATH_A, 0x24, -+ RFREG_OFFSET_MASK)); -+ -+check_delta: -+ if (delta_iqk > rtlefuse->delta_iqk && rtlefuse->delta_iqk != 0) { -+ rtl92d_phy_reset_iqk_result(hw); -+ rtlpriv->dm.thermalvalue_iqk = thermalvalue; -+ rtlpriv->cfg->ops->phy_iq_calibrate(hw); -+ } -+ if (delta_rxgain > 0 && rtlhal->current_bandtype == BAND_ON_5G && -+ thermalvalue <= rtlefuse->eeprom_thermalmeter) { -+ rtlpriv->dm.thermalvalue_rxgain = thermalvalue; -+ rtl92d_dm_rxgain_tracking_thermalmeter(hw); -+ } -+ if (rtlpriv->dm.txpower_track_control) -+ rtlpriv->dm.thermalvalue = thermalvalue; -+ -+exit: -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n"); -+} -+ -+void rtl92d_dm_initialize_txpower_tracking(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ rtlpriv->dm.txpower_tracking = true; -+ rtlpriv->dm.txpower_trackinginit = false; -+ rtlpriv->dm.txpower_track_control = true; -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -+ "pMgntInfo->txpower_tracking = %d\n", -+ rtlpriv->dm.txpower_tracking); -+} -+EXPORT_SYMBOL_GPL(rtl92d_dm_initialize_txpower_tracking); -+ -+void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ if (!rtlpriv->dm.txpower_tracking) -+ return; -+ -+ if (!rtlpriv->dm.tm_trigger) { -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17) | -+ BIT(16), 0x03); -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -+ "Trigger 92S Thermal Meter!!\n"); -+ rtlpriv->dm.tm_trigger = 1; -+ } else { -+ rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -+ "Schedule TxPowerTracking direct call!!\n"); -+ rtl92d_dm_txpower_tracking_callback_thermalmeter(hw); -+ rtlpriv->dm.tm_trigger = 0; -+ } -+} -+EXPORT_SYMBOL_GPL(rtl92d_dm_check_txpower_tracking_thermal_meter); -+ -+void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) -+{ -+ u32 ret_value; -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt; -+ unsigned long flag = 0; -+ -+ /* hold ofdm counter */ -+ rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */ -+ rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */ -+ -+ ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD); -+ falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff); -+ falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); -+ ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); -+ falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); -+ ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); -+ falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); -+ falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); -+ ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); -+ falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); -+ falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + -+ falsealm_cnt->cnt_rate_illegal + -+ falsealm_cnt->cnt_crc8_fail + -+ falsealm_cnt->cnt_mcs_fail + -+ falsealm_cnt->cnt_fast_fsync_fail + -+ falsealm_cnt->cnt_sb_search_fail; -+ -+ if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) { -+ /* hold cck counter */ -+ rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); -+ ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); -+ falsealm_cnt->cnt_cck_fail = ret_value; -+ ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3); -+ falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; -+ rtl92d_release_cckandrw_pagea_ctl(hw, &flag); -+ } else { -+ falsealm_cnt->cnt_cck_fail = 0; -+ } -+ -+ /* reset false alarm counter registers */ -+ falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail + -+ falsealm_cnt->cnt_sb_search_fail + -+ falsealm_cnt->cnt_parity_fail + -+ falsealm_cnt->cnt_rate_illegal + -+ falsealm_cnt->cnt_crc8_fail + -+ falsealm_cnt->cnt_mcs_fail + -+ falsealm_cnt->cnt_cck_fail; -+ -+ rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1); -+ /* update ofdm counter */ -+ rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0); -+ /* update page C counter */ -+ rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0); -+ /* update page D counter */ -+ rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0); -+ if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) { -+ /* reset cck counter */ -+ rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); -+ rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0); -+ /* enable cck counter */ -+ rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2); -+ rtl92d_release_cckandrw_pagea_ctl(hw, &flag); -+ } -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -+ "Cnt_Fast_Fsync_fail = %x, Cnt_SB_Search_fail = %x\n", -+ falsealm_cnt->cnt_fast_fsync_fail, -+ falsealm_cnt->cnt_sb_search_fail); -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -+ "Cnt_Parity_Fail = %x, Cnt_Rate_Illegal = %x, Cnt_Crc8_fail = %x, Cnt_Mcs_fail = %x\n", -+ falsealm_cnt->cnt_parity_fail, -+ falsealm_cnt->cnt_rate_illegal, -+ falsealm_cnt->cnt_crc8_fail, -+ falsealm_cnt->cnt_mcs_fail); -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -+ "Cnt_Ofdm_fail = %x, Cnt_Cck_fail = %x, Cnt_all = %x\n", -+ falsealm_cnt->cnt_ofdm_fail, -+ falsealm_cnt->cnt_cck_fail, -+ falsealm_cnt->cnt_all); -+} -+EXPORT_SYMBOL_GPL(rtl92d_dm_false_alarm_counter_statistics); -+ -+void rtl92d_dm_find_minimum_rssi(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct dig_t *de_digtable = &rtlpriv->dm_digtable; -+ struct rtl_mac *mac = rtl_mac(rtlpriv); -+ -+ /* Determine the minimum RSSI */ -+ if (mac->link_state < MAC80211_LINKED && -+ rtlpriv->dm.UNDEC_SM_PWDB == 0) { -+ de_digtable->min_undec_pwdb_for_dm = 0; -+ rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, -+ "Not connected to any\n"); -+ } -+ if (mac->link_state >= MAC80211_LINKED) { -+ if (mac->opmode == NL80211_IFTYPE_AP || -+ mac->opmode == NL80211_IFTYPE_ADHOC) { -+ de_digtable->min_undec_pwdb_for_dm = -+ rtlpriv->dm.UNDEC_SM_PWDB; -+ rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, -+ "AP Client PWDB = 0x%lx\n", -+ rtlpriv->dm.UNDEC_SM_PWDB); -+ } else { -+ de_digtable->min_undec_pwdb_for_dm = -+ rtlpriv->dm.undec_sm_pwdb; -+ rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, -+ "STA Default Port PWDB = 0x%x\n", -+ de_digtable->min_undec_pwdb_for_dm); -+ } -+ } else { -+ de_digtable->min_undec_pwdb_for_dm = rtlpriv->dm.UNDEC_SM_PWDB; -+ rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, -+ "AP Ext Port or disconnect PWDB = 0x%x\n", -+ de_digtable->min_undec_pwdb_for_dm); -+ } -+ -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "MinUndecoratedPWDBForDM =%d\n", -+ de_digtable->min_undec_pwdb_for_dm); -+} -+EXPORT_SYMBOL_GPL(rtl92d_dm_find_minimum_rssi); -+ -+static void rtl92d_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct dig_t *de_digtable = &rtlpriv->dm_digtable; -+ unsigned long flag = 0; -+ -+ if (de_digtable->cursta_cstate == DIG_STA_CONNECT) { -+ if (de_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { -+ if (de_digtable->min_undec_pwdb_for_dm <= 25) -+ de_digtable->cur_cck_pd_state = -+ CCK_PD_STAGE_LOWRSSI; -+ else -+ de_digtable->cur_cck_pd_state = -+ CCK_PD_STAGE_HIGHRSSI; -+ } else { -+ if (de_digtable->min_undec_pwdb_for_dm <= 20) -+ de_digtable->cur_cck_pd_state = -+ CCK_PD_STAGE_LOWRSSI; -+ else -+ de_digtable->cur_cck_pd_state = -+ CCK_PD_STAGE_HIGHRSSI; -+ } -+ } else { -+ de_digtable->cur_cck_pd_state = CCK_PD_STAGE_LOWRSSI; -+ } -+ if (de_digtable->pre_cck_pd_state != de_digtable->cur_cck_pd_state) { -+ if (de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { -+ rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); -+ rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83); -+ rtl92d_release_cckandrw_pagea_ctl(hw, &flag); -+ } else { -+ rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); -+ rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); -+ rtl92d_release_cckandrw_pagea_ctl(hw, &flag); -+ } -+ de_digtable->pre_cck_pd_state = de_digtable->cur_cck_pd_state; -+ } -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "CurSTAConnectState=%s\n", -+ de_digtable->cursta_cstate == DIG_STA_CONNECT ? -+ "DIG_STA_CONNECT " : "DIG_STA_DISCONNECT"); -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "CCKPDStage=%s\n", -+ de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI ? -+ "Low RSSI " : "High RSSI "); -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "is92d single phy =%x\n", -+ IS_92D_SINGLEPHY(rtlpriv->rtlhal.version)); -+} -+ -+void rtl92d_dm_write_dig(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct dig_t *de_digtable = &rtlpriv->dm_digtable; -+ -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -+ "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n", -+ de_digtable->cur_igvalue, de_digtable->pre_igvalue, -+ de_digtable->back_val); -+ if (!de_digtable->dig_enable_flag) { -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "DIG is disabled\n"); -+ de_digtable->pre_igvalue = 0x17; -+ return; -+ } -+ if (de_digtable->pre_igvalue != de_digtable->cur_igvalue) { -+ rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, -+ de_digtable->cur_igvalue); -+ rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, -+ de_digtable->cur_igvalue); -+ de_digtable->pre_igvalue = de_digtable->cur_igvalue; -+ } -+} -+EXPORT_SYMBOL_GPL(rtl92d_dm_write_dig); -+ -+static void rtl92d_early_mode_enabled(struct rtl_priv *rtlpriv) -+{ -+ struct dig_t *de_digtable = &rtlpriv->dm_digtable; -+ -+ if (rtlpriv->mac80211.link_state >= MAC80211_LINKED && -+ rtlpriv->mac80211.vendor == PEER_CISCO) { -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "IOT_PEER = CISCO\n"); -+ if (de_digtable->last_min_undec_pwdb_for_dm >= 50 && -+ de_digtable->min_undec_pwdb_for_dm < 50) { -+ rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x00); -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -+ "Early Mode Off\n"); -+ } else if (de_digtable->last_min_undec_pwdb_for_dm <= 55 && -+ de_digtable->min_undec_pwdb_for_dm > 55) { -+ rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f); -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -+ "Early Mode On\n"); -+ } -+ } else if (!(rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL) & 0xf)) { -+ rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f); -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "Early Mode On\n"); -+ } -+} -+ -+void rtl92d_dm_dig(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct dig_t *de_digtable = &rtlpriv->dm_digtable; -+ u8 value_igi = de_digtable->cur_igvalue; -+ struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt; -+ -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "==>\n"); -+ if (rtlpriv->rtlhal.earlymode_enable) { -+ rtl92d_early_mode_enabled(rtlpriv); -+ de_digtable->last_min_undec_pwdb_for_dm = -+ de_digtable->min_undec_pwdb_for_dm; -+ } -+ if (!rtlpriv->dm.dm_initialgain_enable) -+ return; -+ -+ /* because we will send data pkt when scanning -+ * this will cause some ap like gear-3700 wep TP -+ * lower if we return here, this is the diff of -+ * mac80211 driver vs ieee80211 driver -+ */ -+ /* if (rtlpriv->mac80211.act_scanning) -+ * return; -+ */ -+ -+ /* Not STA mode return tmp */ -+ if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION) -+ return; -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "progress\n"); -+ /* Decide the current status and if modify initial gain or not */ -+ if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) -+ de_digtable->cursta_cstate = DIG_STA_CONNECT; -+ else -+ de_digtable->cursta_cstate = DIG_STA_DISCONNECT; -+ -+ /* adjust initial gain according to false alarm counter */ -+ if (falsealm_cnt->cnt_all < DM_DIG_FA_TH0) -+ value_igi--; -+ else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH1) -+ value_igi += 0; -+ else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH2) -+ value_igi++; -+ else if (falsealm_cnt->cnt_all >= DM_DIG_FA_TH2) -+ value_igi += 2; -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -+ "dm_DIG() Before: large_fa_hit=%d, forbidden_igi=%x\n", -+ de_digtable->large_fa_hit, de_digtable->forbidden_igi); -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -+ "dm_DIG() Before: Recover_cnt=%d, rx_gain_min=%x\n", -+ de_digtable->recover_cnt, de_digtable->rx_gain_min); -+ -+ /* deal with abnormally large false alarm */ -+ if (falsealm_cnt->cnt_all > 10000) { -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -+ "dm_DIG(): Abnormally false alarm case\n"); -+ -+ de_digtable->large_fa_hit++; -+ if (de_digtable->forbidden_igi < de_digtable->cur_igvalue) { -+ de_digtable->forbidden_igi = de_digtable->cur_igvalue; -+ de_digtable->large_fa_hit = 1; -+ } -+ if (de_digtable->large_fa_hit >= 3) { -+ if ((de_digtable->forbidden_igi + 1) > DM_DIG_MAX) -+ de_digtable->rx_gain_min = DM_DIG_MAX; -+ else -+ de_digtable->rx_gain_min = -+ (de_digtable->forbidden_igi + 1); -+ de_digtable->recover_cnt = 3600; /* 3600=2hr */ -+ } -+ } else { -+ /* Recovery mechanism for IGI lower bound */ -+ if (de_digtable->recover_cnt != 0) { -+ de_digtable->recover_cnt--; -+ } else { -+ if (de_digtable->large_fa_hit == 0) { -+ if ((de_digtable->forbidden_igi - 1) < -+ DM_DIG_FA_LOWER) { -+ de_digtable->forbidden_igi = -+ DM_DIG_FA_LOWER; -+ de_digtable->rx_gain_min = -+ DM_DIG_FA_LOWER; -+ -+ } else { -+ de_digtable->forbidden_igi--; -+ de_digtable->rx_gain_min = -+ (de_digtable->forbidden_igi + 1); -+ } -+ } else if (de_digtable->large_fa_hit == 3) { -+ de_digtable->large_fa_hit = 0; -+ } -+ } -+ } -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -+ "dm_DIG() After: large_fa_hit=%d, forbidden_igi=%x\n", -+ de_digtable->large_fa_hit, de_digtable->forbidden_igi); -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -+ "dm_DIG() After: recover_cnt=%d, rx_gain_min=%x\n", -+ de_digtable->recover_cnt, de_digtable->rx_gain_min); -+ -+ if (value_igi > DM_DIG_MAX) -+ value_igi = DM_DIG_MAX; -+ else if (value_igi < de_digtable->rx_gain_min) -+ value_igi = de_digtable->rx_gain_min; -+ de_digtable->cur_igvalue = value_igi; -+ rtl92d_dm_write_dig(hw); -+ if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) -+ rtl92d_dm_cck_packet_detection_thresh(hw); -+ rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "<<==\n"); -+} -+EXPORT_SYMBOL_GPL(rtl92d_dm_dig); -+ -+void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ rtlpriv->dm.current_turbo_edca = false; -+ rtlpriv->dm.is_any_nonbepkts = false; -+ rtlpriv->dm.is_cur_rdlstate = false; -+} -+EXPORT_SYMBOL_GPL(rtl92d_dm_init_edca_turbo); -+ -+void rtl92d_dm_check_edca_turbo(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -+ const u32 edca_be_ul = 0x5ea42b; -+ const u32 edca_be_dl = 0x5ea42b; -+ static u64 last_txok_cnt; -+ static u64 last_rxok_cnt; -+ u64 cur_txok_cnt; -+ u64 cur_rxok_cnt; -+ -+ if (mac->link_state != MAC80211_LINKED) { -+ rtlpriv->dm.current_turbo_edca = false; -+ goto exit; -+ } -+ -+ if (!rtlpriv->dm.is_any_nonbepkts && -+ !rtlpriv->dm.disable_framebursting) { -+ cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt; -+ cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt; -+ if (cur_rxok_cnt > 4 * cur_txok_cnt) { -+ if (!rtlpriv->dm.is_cur_rdlstate || -+ !rtlpriv->dm.current_turbo_edca) { -+ rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, -+ edca_be_dl); -+ rtlpriv->dm.is_cur_rdlstate = true; -+ } -+ } else { -+ if (rtlpriv->dm.is_cur_rdlstate || -+ !rtlpriv->dm.current_turbo_edca) { -+ rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, -+ edca_be_ul); -+ rtlpriv->dm.is_cur_rdlstate = false; -+ } -+ } -+ rtlpriv->dm.current_turbo_edca = true; -+ } else { -+ if (rtlpriv->dm.current_turbo_edca) { -+ u8 tmp = AC0_BE; -+ -+ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, -+ &tmp); -+ rtlpriv->dm.current_turbo_edca = false; -+ } -+ } -+ -+exit: -+ rtlpriv->dm.is_any_nonbepkts = false; -+ last_txok_cnt = rtlpriv->stats.txbytesunicast; -+ last_rxok_cnt = rtlpriv->stats.rxbytesunicast; -+} -+EXPORT_SYMBOL_GPL(rtl92d_dm_check_edca_turbo); -+ -+void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rate_adaptive *ra = &rtlpriv->ra; -+ -+ ra->ratr_state = DM_RATR_STA_INIT; -+ ra->pre_ratr_state = DM_RATR_STA_INIT; -+ if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) -+ rtlpriv->dm.useramask = true; -+ else -+ rtlpriv->dm.useramask = false; -+} -+EXPORT_SYMBOL_GPL(rtl92d_dm_init_rate_adaptive_mask); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.h -new file mode 100644 -index 000000000000..9dc0df5bb068 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.h -@@ -0,0 +1,100 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* Copyright(c) 2009-2012 Realtek Corporation.*/ -+ -+#ifndef __RTL92D_DM_COMMON_H__ -+#define __RTL92D_DM_COMMON_H__ -+ -+#define HAL_DM_DIG_DISABLE BIT(0) -+#define HAL_DM_HIPWR_DISABLE BIT(1) -+ -+#define OFDM_TABLE_LENGTH 37 -+#define OFDM_TABLE_SIZE_92D 43 -+#define CCK_TABLE_LENGTH 33 -+ -+#define CCK_TABLE_SIZE 33 -+ -+#define BW_AUTO_SWITCH_HIGH_LOW 25 -+#define BW_AUTO_SWITCH_LOW_HIGH 30 -+ -+#define DM_DIG_FA_UPPER 0x32 -+#define DM_DIG_FA_LOWER 0x20 -+#define DM_DIG_FA_TH0 0x100 -+#define DM_DIG_FA_TH1 0x400 -+#define DM_DIG_FA_TH2 0x600 -+ -+#define RXPATHSELECTION_SS_TH_LOW 30 -+#define RXPATHSELECTION_DIFF_TH 18 -+ -+#define DM_RATR_STA_INIT 0 -+#define DM_RATR_STA_HIGH 1 -+#define DM_RATR_STA_MIDDLE 2 -+#define DM_RATR_STA_LOW 3 -+ -+#define CTS2SELF_THVAL 30 -+#define REGC38_TH 20 -+ -+#define WAIOTTHVAL 25 -+ -+#define TXHIGHPWRLEVEL_NORMAL 0 -+#define TXHIGHPWRLEVEL_LEVEL1 1 -+#define TXHIGHPWRLEVEL_LEVEL2 2 -+#define TXHIGHPWRLEVEL_BT1 3 -+#define TXHIGHPWRLEVEL_BT2 4 -+ -+#define DM_TYPE_BYFW 0 -+#define DM_TYPE_BYDRIVER 1 -+ -+#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 -+#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 -+#define INDEX_MAPPING_NUM 13 -+ -+struct swat { -+ u8 failure_cnt; -+ u8 try_flag; -+ u8 stop_trying; -+ long pre_rssi; -+ long trying_threshold; -+ u8 cur_antenna; -+ u8 pre_antenna; -+}; -+ -+enum tag_dynamic_init_gain_operation_type_definition { -+ DIG_TYPE_THRESH_HIGH = 0, -+ DIG_TYPE_THRESH_LOW = 1, -+ DIG_TYPE_BACKOFF = 2, -+ DIG_TYPE_RX_GAIN_MIN = 3, -+ DIG_TYPE_RX_GAIN_MAX = 4, -+ DIG_TYPE_ENABLE = 5, -+ DIG_TYPE_DISABLE = 6, -+ DIG_OP_TYPE_MAX -+}; -+ -+enum dm_1r_cca { -+ CCA_1R = 0, -+ CCA_2R = 1, -+ CCA_MAX = 2, -+}; -+ -+enum dm_rf { -+ RF_SAVE = 0, -+ RF_NORMAL = 1, -+ RF_MAX = 2, -+}; -+ -+enum dm_sw_ant_switch { -+ ANS_ANTENNA_B = 1, -+ ANS_ANTENNA_A = 2, -+ ANS_ANTENNA_MAX = 3, -+}; -+ -+void rtl92d_dm_initialize_txpower_tracking(struct ieee80211_hw *hw); -+void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw); -+void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw); -+void rtl92d_dm_find_minimum_rssi(struct ieee80211_hw *hw); -+void rtl92d_dm_write_dig(struct ieee80211_hw *hw); -+void rtl92d_dm_dig(struct ieee80211_hw *hw); -+void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw); -+void rtl92d_dm_check_edca_turbo(struct ieee80211_hw *hw); -+void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw); -+ -+#endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c -new file mode 100644 -index 000000000000..73cfa9ad78ae ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c -@@ -0,0 +1,369 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright(c) 2009-2012 Realtek Corporation.*/ -+ -+#include "../wifi.h" -+#include "../pci.h" -+#include "../base.h" -+#include "../efuse.h" -+#include "def.h" -+#include "reg.h" -+#include "fw_common.h" -+ -+bool rtl92d_is_fw_downloaded(struct rtl_priv *rtlpriv) -+{ -+ return (rtl_read_dword(rtlpriv, REG_MCUFWDL) & MCUFWDL_RDY) ? -+ true : false; -+} -+EXPORT_SYMBOL_GPL(rtl92d_is_fw_downloaded); -+ -+void rtl92d_enable_fw_download(struct ieee80211_hw *hw, bool enable) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u8 tmp; -+ -+ if (enable) { -+ tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); -+ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp | 0x04); -+ tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL); -+ rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01); -+ tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2); -+ rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7); -+ } else { -+ tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL); -+ rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe); -+ /* Reserved for fw extension. -+ * 0x81[7] is used for mac0 status , -+ * so don't write this reg here -+ * rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00); -+ */ -+ } -+} -+EXPORT_SYMBOL_GPL(rtl92d_enable_fw_download); -+ -+void rtl92d_write_fw(struct ieee80211_hw *hw, -+ enum version_8192d version, u8 *buffer, u32 size) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ u8 *bufferptr = buffer; -+ u32 pagenums, remainsize; -+ u32 page, offset; -+ -+ rtl_dbg(rtlpriv, COMP_FW, DBG_TRACE, "FW size is %d bytes,\n", size); -+ if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) -+ rtl_fill_dummy(bufferptr, &size); -+ pagenums = size / FW_8192D_PAGE_SIZE; -+ remainsize = size % FW_8192D_PAGE_SIZE; -+ if (pagenums > 8) -+ pr_err("Page numbers should not greater then 8\n"); -+ for (page = 0; page < pagenums; page++) { -+ offset = page * FW_8192D_PAGE_SIZE; -+ rtl_fw_page_write(hw, page, (bufferptr + offset), -+ FW_8192D_PAGE_SIZE); -+ } -+ if (remainsize) { -+ offset = pagenums * FW_8192D_PAGE_SIZE; -+ page = pagenums; -+ rtl_fw_page_write(hw, page, (bufferptr + offset), remainsize); -+ } -+} -+EXPORT_SYMBOL_GPL(rtl92d_write_fw); -+ -+int rtl92d_fw_free_to_go(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 counter = 0; -+ u32 value32; -+ -+ do { -+ value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL); -+ } while ((counter++ < FW_8192D_POLLING_TIMEOUT_COUNT) && -+ (!(value32 & FWDL_CHKSUM_RPT))); -+ if (counter >= FW_8192D_POLLING_TIMEOUT_COUNT) { -+ pr_err("chksum report fail! REG_MCUFWDL:0x%08x\n", -+ value32); -+ return -EIO; -+ } -+ value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL); -+ value32 |= MCUFWDL_RDY; -+ rtl_write_dword(rtlpriv, REG_MCUFWDL, value32); -+ return 0; -+} -+EXPORT_SYMBOL_GPL(rtl92d_fw_free_to_go); -+ -+void rtl92d_firmware_selfreset(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u8 u1b_tmp; -+ u8 delay = 100; -+ -+ /* Set (REG_HMETFR + 3) to 0x20 is reset 8051 */ -+ rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20); -+ u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); -+ while (u1b_tmp & BIT(2)) { -+ delay--; -+ if (delay == 0) -+ break; -+ udelay(50); -+ u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); -+ } -+ WARN_ONCE((delay <= 0), "rtl8192de: 8051 reset failed!\n"); -+ rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, -+ "=====> 8051 reset success (%d)\n", delay); -+} -+EXPORT_SYMBOL_GPL(rtl92d_firmware_selfreset); -+ -+int rtl92d_fw_init(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ u32 counter; -+ -+ rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, "FW already have download\n"); -+ /* polling for FW ready */ -+ counter = 0; -+ do { -+ if (rtlhal->interfaceindex == 0) { -+ if (rtl_read_byte(rtlpriv, FW_MAC0_READY) & -+ MAC0_READY) { -+ rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, -+ "Polling FW ready success!! REG_MCUFWDL: 0x%x\n", -+ rtl_read_byte(rtlpriv, -+ FW_MAC0_READY)); -+ return 0; -+ } -+ udelay(5); -+ } else { -+ if (rtl_read_byte(rtlpriv, FW_MAC1_READY) & -+ MAC1_READY) { -+ rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, -+ "Polling FW ready success!! REG_MCUFWDL: 0x%x\n", -+ rtl_read_byte(rtlpriv, -+ FW_MAC1_READY)); -+ return 0; -+ } -+ udelay(5); -+ } -+ } while (counter++ < POLLING_READY_TIMEOUT_COUNT); -+ -+ if (rtlhal->interfaceindex == 0) { -+ rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, -+ "Polling FW ready fail!! MAC0 FW init not ready: 0x%x\n", -+ rtl_read_byte(rtlpriv, FW_MAC0_READY)); -+ } else { -+ rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, -+ "Polling FW ready fail!! MAC1 FW init not ready: 0x%x\n", -+ rtl_read_byte(rtlpriv, FW_MAC1_READY)); -+ } -+ rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, -+ "Polling FW ready fail!! REG_MCUFWDL:0x%08x\n", -+ rtl_read_dword(rtlpriv, REG_MCUFWDL)); -+ return -1; -+} -+EXPORT_SYMBOL_GPL(rtl92d_fw_init); -+ -+static bool _rtl92d_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u8 val_hmetfr; -+ bool result = false; -+ -+ val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR); -+ if (((val_hmetfr >> boxnum) & BIT(0)) == 0) -+ result = true; -+ return result; -+} -+ -+static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw, -+ u8 element_id, u32 cmd_len, u8 *cmdbuffer) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); -+ u8 boxnum; -+ u16 box_reg = 0, box_extreg = 0; -+ u8 u1b_tmp; -+ bool isfw_read = false; -+ u8 buf_index = 0; -+ bool bwrite_success = false; -+ u8 wait_h2c_limmit = 100; -+ u8 wait_writeh2c_limmit = 100; -+ u8 boxcontent[4], boxextcontent[2]; -+ u32 h2c_waitcounter = 0; -+ unsigned long flag; -+ u8 idx; -+ -+ if (ppsc->rfpwr_state == ERFOFF || ppsc->inactive_pwrstate == ERFOFF) { -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, -+ "Return as RF is off!!!\n"); -+ return; -+ } -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n"); -+ while (true) { -+ spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag); -+ if (rtlhal->h2c_setinprogress) { -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, -+ "H2C set in progress! Wait to set..element_id(%d)\n", -+ element_id); -+ -+ while (rtlhal->h2c_setinprogress) { -+ spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, -+ flag); -+ h2c_waitcounter++; -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, -+ "Wait 100 us (%d times)...\n", -+ h2c_waitcounter); -+ udelay(100); -+ -+ if (h2c_waitcounter > 1000) -+ return; -+ -+ spin_lock_irqsave(&rtlpriv->locks.h2c_lock, -+ flag); -+ } -+ spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); -+ } else { -+ rtlhal->h2c_setinprogress = true; -+ spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); -+ break; -+ } -+ } -+ while (!bwrite_success) { -+ wait_writeh2c_limmit--; -+ if (wait_writeh2c_limmit == 0) { -+ pr_err("Write H2C fail because no trigger for FW INT!\n"); -+ break; -+ } -+ boxnum = rtlhal->last_hmeboxnum; -+ switch (boxnum) { -+ case 0: -+ box_reg = REG_HMEBOX_0; -+ box_extreg = REG_HMEBOX_EXT_0; -+ break; -+ case 1: -+ box_reg = REG_HMEBOX_1; -+ box_extreg = REG_HMEBOX_EXT_1; -+ break; -+ case 2: -+ box_reg = REG_HMEBOX_2; -+ box_extreg = REG_HMEBOX_EXT_2; -+ break; -+ case 3: -+ box_reg = REG_HMEBOX_3; -+ box_extreg = REG_HMEBOX_EXT_3; -+ break; -+ default: -+ pr_err("switch case %#x not processed\n", -+ boxnum); -+ break; -+ } -+ isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum); -+ while (!isfw_read) { -+ wait_h2c_limmit--; -+ if (wait_h2c_limmit == 0) { -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, -+ "Waiting too long for FW read clear HMEBox(%d)!\n", -+ boxnum); -+ break; -+ } -+ udelay(10); -+ isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum); -+ u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF); -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, -+ "Waiting for FW read clear HMEBox(%d)!!! 0x1BF = %2x\n", -+ boxnum, u1b_tmp); -+ } -+ if (!isfw_read) { -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, -+ "Write H2C register BOX[%d] fail!!!!! Fw do not read.\n", -+ boxnum); -+ break; -+ } -+ memset(boxcontent, 0, sizeof(boxcontent)); -+ memset(boxextcontent, 0, sizeof(boxextcontent)); -+ boxcontent[0] = element_id; -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, -+ "Write element_id box_reg(%4x) = %2x\n", -+ box_reg, element_id); -+ switch (cmd_len) { -+ case 1: -+ boxcontent[0] &= ~(BIT(7)); -+ memcpy(boxcontent + 1, cmdbuffer + buf_index, 1); -+ for (idx = 0; idx < 4; idx++) -+ rtl_write_byte(rtlpriv, box_reg + idx, -+ boxcontent[idx]); -+ break; -+ case 2: -+ boxcontent[0] &= ~(BIT(7)); -+ memcpy(boxcontent + 1, cmdbuffer + buf_index, 2); -+ for (idx = 0; idx < 4; idx++) -+ rtl_write_byte(rtlpriv, box_reg + idx, -+ boxcontent[idx]); -+ break; -+ case 3: -+ boxcontent[0] &= ~(BIT(7)); -+ memcpy(boxcontent + 1, cmdbuffer + buf_index, 3); -+ for (idx = 0; idx < 4; idx++) -+ rtl_write_byte(rtlpriv, box_reg + idx, -+ boxcontent[idx]); -+ break; -+ case 4: -+ boxcontent[0] |= (BIT(7)); -+ memcpy(boxextcontent, cmdbuffer + buf_index, 2); -+ memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 2); -+ for (idx = 0; idx < 2; idx++) -+ rtl_write_byte(rtlpriv, box_extreg + idx, -+ boxextcontent[idx]); -+ for (idx = 0; idx < 4; idx++) -+ rtl_write_byte(rtlpriv, box_reg + idx, -+ boxcontent[idx]); -+ break; -+ case 5: -+ boxcontent[0] |= (BIT(7)); -+ memcpy(boxextcontent, cmdbuffer + buf_index, 2); -+ memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 3); -+ for (idx = 0; idx < 2; idx++) -+ rtl_write_byte(rtlpriv, box_extreg + idx, -+ boxextcontent[idx]); -+ for (idx = 0; idx < 4; idx++) -+ rtl_write_byte(rtlpriv, box_reg + idx, -+ boxcontent[idx]); -+ break; -+ default: -+ pr_err("switch case %#x not processed\n", -+ cmd_len); -+ break; -+ } -+ bwrite_success = true; -+ rtlhal->last_hmeboxnum = boxnum + 1; -+ if (rtlhal->last_hmeboxnum == 4) -+ rtlhal->last_hmeboxnum = 0; -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, -+ "pHalData->last_hmeboxnum = %d\n", -+ rtlhal->last_hmeboxnum); -+ } -+ spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag); -+ rtlhal->h2c_setinprogress = false; -+ spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n"); -+} -+ -+void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, -+ u8 element_id, u32 cmd_len, u8 *cmdbuffer) -+{ -+ u32 tmp_cmdbuf[2]; -+ -+ memset(tmp_cmdbuf, 0, 8); -+ memcpy(tmp_cmdbuf, cmdbuffer, cmd_len); -+ _rtl92d_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf); -+} -+EXPORT_SYMBOL_GPL(rtl92d_fill_h2c_cmd); -+ -+void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus) -+{ -+ u8 u1_joinbssrpt_parm[1] = {0}; -+ -+ u1_joinbssrpt_parm[0] = mstatus; -+ rtl92d_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm); -+} -+EXPORT_SYMBOL_GPL(rtl92d_set_fw_joinbss_report_cmd); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h -new file mode 100644 -index 000000000000..4e8e2b716f88 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h -@@ -0,0 +1,39 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* Copyright(c) 2009-2012 Realtek Corporation.*/ -+ -+#ifndef __RTL92D_FW_COMMON_H__ -+#define __RTL92D_FW_COMMON_H__ -+ -+#define FW_8192D_START_ADDRESS 0x1000 -+#define FW_8192D_PAGE_SIZE 4096 -+#define FW_8192D_POLLING_TIMEOUT_COUNT 1000 -+ -+#define IS_FW_HEADER_EXIST(_pfwhdr) \ -+ ((GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFF0) == 0x92C0 || \ -+ (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFF0) == 0x88C0 || \ -+ (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D0 || \ -+ (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D1 || \ -+ (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D2 || \ -+ (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D3) -+ -+/* Firmware Header(8-byte alinment required) */ -+/* --- LONG WORD 0 ---- */ -+#define GET_FIRMWARE_HDR_SIGNATURE(__fwhdr) \ -+ le32_get_bits(*(__le32 *)__fwhdr, GENMASK(15, 0)) -+#define GET_FIRMWARE_HDR_VERSION(__fwhdr) \ -+ le32_get_bits(*(__le32 *)((__fwhdr) + 4), GENMASK(15, 0)) -+#define GET_FIRMWARE_HDR_SUB_VER(__fwhdr) \ -+ le32_get_bits(*(__le32 *)((__fwhdr) + 4), GENMASK(23, 16)) -+ -+bool rtl92d_is_fw_downloaded(struct rtl_priv *rtlpriv); -+void rtl92d_enable_fw_download(struct ieee80211_hw *hw, bool enable); -+void rtl92d_write_fw(struct ieee80211_hw *hw, -+ enum version_8192d version, u8 *buffer, u32 size); -+int rtl92d_fw_free_to_go(struct ieee80211_hw *hw); -+void rtl92d_firmware_selfreset(struct ieee80211_hw *hw); -+int rtl92d_fw_init(struct ieee80211_hw *hw); -+void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id, -+ u32 cmd_len, u8 *p_cmdbuffer); -+void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus); -+ -+#endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c -new file mode 100644 -index 000000000000..e70e83252e16 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c -@@ -0,0 +1,1191 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright(c) 2009-2012 Realtek Corporation.*/ -+ -+#include "../wifi.h" -+#include "../base.h" -+#include "../cam.h" -+#include "../efuse.h" -+#include "../pci.h" -+#include "../regd.h" -+#include "def.h" -+#include "reg.h" -+#include "dm_common.h" -+#include "fw_common.h" -+#include "hw_common.h" -+#include "phy_common.h" -+ -+void rtl92de_stop_tx_beacon(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u8 tmp1byte; -+ -+ tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); -+ rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); -+ rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); -+ rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); -+ tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); -+ tmp1byte &= ~(BIT(0)); -+ rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); -+} -+EXPORT_SYMBOL_GPL(rtl92de_stop_tx_beacon); -+ -+void rtl92de_resume_tx_beacon(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u8 tmp1byte; -+ -+ tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); -+ rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); -+ rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); -+ rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); -+ tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); -+ tmp1byte |= BIT(0); -+ rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); -+} -+EXPORT_SYMBOL_GPL(rtl92de_resume_tx_beacon); -+ -+void rtl92d_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); -+ -+ switch (variable) { -+ case HW_VAR_RF_STATE: -+ *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; -+ break; -+ case HW_VAR_FWLPS_RF_ON:{ -+ enum rf_pwrstate rfstate; -+ u32 val_rcr; -+ -+ rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, -+ (u8 *)(&rfstate)); -+ if (rfstate == ERFOFF) { -+ *((bool *)(val)) = true; -+ } else { -+ val_rcr = rtl_read_dword(rtlpriv, REG_RCR); -+ val_rcr &= 0x00070000; -+ if (val_rcr) -+ *((bool *)(val)) = false; -+ else -+ *((bool *)(val)) = true; -+ } -+ break; -+ } -+ case HW_VAR_FW_PSMODE_STATUS: -+ *((bool *)(val)) = ppsc->fw_current_inpsmode; -+ break; -+ case HW_VAR_CORRECT_TSF:{ -+ u64 tsf; -+ u32 *ptsf_low = (u32 *)&tsf; -+ u32 *ptsf_high = ((u32 *)&tsf) + 1; -+ -+ *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); -+ *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); -+ *((u64 *)(val)) = tsf; -+ break; -+ } -+ case HW_VAR_INT_MIGRATION: -+ *((bool *)(val)) = rtlpriv->dm.interrupt_migration; -+ break; -+ case HW_VAR_INT_AC: -+ *((bool *)(val)) = rtlpriv->dm.disable_tx_int; -+ break; -+ case HAL_DEF_WOWLAN: -+ break; -+ default: -+ pr_err("switch case %#x not processed\n", variable); -+ break; -+ } -+} -+EXPORT_SYMBOL_GPL(rtl92d_get_hw_reg); -+ -+void rtl92d_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -+ struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); -+ u8 idx; -+ -+ switch (variable) { -+ case HW_VAR_ETHER_ADDR: -+ for (idx = 0; idx < ETH_ALEN; idx++) { -+ rtl_write_byte(rtlpriv, (REG_MACID + idx), -+ val[idx]); -+ } -+ break; -+ case HW_VAR_BASIC_RATE: { -+ u16 rate_cfg = ((u16 *)val)[0]; -+ u8 rate_index = 0; -+ -+ rate_cfg = rate_cfg & 0x15f; -+ if (mac->vendor == PEER_CISCO && -+ ((rate_cfg & 0x150) == 0)) -+ rate_cfg |= 0x01; -+ rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); -+ rtl_write_byte(rtlpriv, REG_RRSR + 1, -+ (rate_cfg >> 8) & 0xff); -+ while (rate_cfg > 0x1) { -+ rate_cfg = (rate_cfg >> 1); -+ rate_index++; -+ } -+ if (rtlhal->fw_version > 0xe) -+ rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, -+ rate_index); -+ break; -+ } -+ case HW_VAR_BSSID: -+ for (idx = 0; idx < ETH_ALEN; idx++) { -+ rtl_write_byte(rtlpriv, (REG_BSSID + idx), -+ val[idx]); -+ } -+ break; -+ case HW_VAR_SIFS: -+ rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); -+ rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); -+ rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); -+ rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); -+ if (!mac->ht_enable) -+ rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, -+ 0x0e0e); -+ else -+ rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, -+ *((u16 *)val)); -+ break; -+ case HW_VAR_SLOT_TIME: { -+ u8 e_aci; -+ -+ rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, -+ "HW_VAR_SLOT_TIME %x\n", val[0]); -+ rtl_write_byte(rtlpriv, REG_SLOT, val[0]); -+ for (e_aci = 0; e_aci < AC_MAX; e_aci++) -+ rtlpriv->cfg->ops->set_hw_reg(hw, -+ HW_VAR_AC_PARAM, -+ (&e_aci)); -+ break; -+ } -+ case HW_VAR_ACK_PREAMBLE: { -+ u8 reg_tmp; -+ u8 short_preamble = (bool)(*val); -+ -+ reg_tmp = (mac->cur_40_prime_sc) << 5; -+ if (short_preamble) -+ reg_tmp |= 0x80; -+ rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); -+ break; -+ } -+ case HW_VAR_AMPDU_MIN_SPACE: { -+ u8 min_spacing_to_set; -+ -+ min_spacing_to_set = *val; -+ if (min_spacing_to_set <= 7) { -+ mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) | -+ min_spacing_to_set); -+ *val = min_spacing_to_set; -+ rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, -+ "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", -+ mac->min_space_cfg); -+ rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, -+ mac->min_space_cfg); -+ } -+ break; -+ } -+ case HW_VAR_SHORTGI_DENSITY: { -+ u8 density_to_set; -+ -+ density_to_set = *val; -+ mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg; -+ mac->min_space_cfg |= (density_to_set << 3); -+ rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, -+ "Set HW_VAR_SHORTGI_DENSITY: %#x\n", -+ mac->min_space_cfg); -+ rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, -+ mac->min_space_cfg); -+ break; -+ } -+ case HW_VAR_AMPDU_FACTOR: { -+ u8 factor_toset; -+ u32 regtoset; -+ u8 *ptmp_byte = NULL; -+ u8 index; -+ -+ if (rtlhal->macphymode == DUALMAC_DUALPHY) -+ regtoset = 0xb9726641; -+ else if (rtlhal->macphymode == DUALMAC_SINGLEPHY) -+ regtoset = 0x66626641; -+ else -+ regtoset = 0xb972a841; -+ factor_toset = *val; -+ if (factor_toset <= 3) { -+ factor_toset = (1 << (factor_toset + 2)); -+ if (factor_toset > 0xf) -+ factor_toset = 0xf; -+ for (index = 0; index < 4; index++) { -+ ptmp_byte = (u8 *)(®toset) + index; -+ if ((*ptmp_byte & 0xf0) > -+ (factor_toset << 4)) -+ *ptmp_byte = (*ptmp_byte & 0x0f) -+ | (factor_toset << 4); -+ if ((*ptmp_byte & 0x0f) > factor_toset) -+ *ptmp_byte = (*ptmp_byte & 0xf0) -+ | (factor_toset); -+ } -+ rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoset); -+ rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, -+ "Set HW_VAR_AMPDU_FACTOR: %#x\n", -+ factor_toset); -+ } -+ break; -+ } -+ case HW_VAR_RETRY_LIMIT: { -+ u8 retry_limit = val[0]; -+ -+ rtl_write_word(rtlpriv, REG_RL, -+ retry_limit << RETRY_LIMIT_SHORT_SHIFT | -+ retry_limit << RETRY_LIMIT_LONG_SHIFT); -+ break; -+ } -+ case HW_VAR_DUAL_TSF_RST: -+ rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); -+ break; -+ case HW_VAR_EFUSE_BYTES: -+ rtlefuse->efuse_usedbytes = *((u16 *)val); -+ break; -+ case HW_VAR_EFUSE_USAGE: -+ rtlefuse->efuse_usedpercentage = *val; -+ break; -+ case HW_VAR_IO_CMD: -+ rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val)); -+ break; -+ case HW_VAR_WPA_CONFIG: -+ rtl_write_byte(rtlpriv, REG_SECCFG, *val); -+ break; -+ case HW_VAR_SET_RPWM: -+ rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (val)); -+ break; -+ case HW_VAR_H2C_FW_PWRMODE: -+ break; -+ case HW_VAR_FW_PSMODE_STATUS: -+ ppsc->fw_current_inpsmode = *((bool *)val); -+ break; -+ case HW_VAR_AID: { -+ u16 u2btmp; -+ -+ u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); -+ u2btmp &= 0xC000; -+ rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | -+ mac->assoc_id)); -+ break; -+ } -+ default: -+ pr_err("switch case %#x not processed\n", variable); -+ break; -+ } -+} -+EXPORT_SYMBOL_GPL(rtl92d_set_hw_reg); -+ -+bool rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ bool status = true; -+ long count = 0; -+ u32 value = _LLT_INIT_ADDR(address) | -+ _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); -+ -+ rtl_write_dword(rtlpriv, REG_LLT_INIT, value); -+ do { -+ value = rtl_read_dword(rtlpriv, REG_LLT_INIT); -+ if (_LLT_OP_VALUE(value) == _LLT_NO_ACTIVE) -+ break; -+ if (count > POLLING_LLT_THRESHOLD) { -+ pr_err("Failed to polling write LLT done at address %d!\n", -+ address); -+ status = false; -+ break; -+ } -+ } while (++count); -+ return status; -+} -+EXPORT_SYMBOL_GPL(rtl92de_llt_write); -+ -+void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u8 sec_reg_value; -+ -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", -+ rtlpriv->sec.pairwise_enc_algorithm, -+ rtlpriv->sec.group_enc_algorithm); -+ if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { -+ rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, -+ "not open hw encryption\n"); -+ return; -+ } -+ sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE; -+ if (rtlpriv->sec.use_defaultkey) { -+ sec_reg_value |= SCR_TXUSEDK; -+ sec_reg_value |= SCR_RXUSEDK; -+ } -+ sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); -+ rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); -+ rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, -+ "The SECR-value %x\n", sec_reg_value); -+ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); -+} -+EXPORT_SYMBOL_GPL(rtl92de_enable_hw_security_config); -+ -+/* don't set REG_EDCA_BE_PARAM here because -+ * mac80211 will send pkt when scan -+ */ -+void rtl92de_set_qos(struct ieee80211_hw *hw, int aci) -+{ -+ rtl92d_dm_init_edca_turbo(hw); -+} -+EXPORT_SYMBOL_GPL(rtl92de_set_qos); -+ -+static enum version_8192d _rtl92d_read_chip_version(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY; -+ u32 value32; -+ -+ value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); -+ if (!(value32 & 0x000f0000)) { -+ version = VERSION_TEST_CHIP_92D_SINGLEPHY; -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n"); -+ } else { -+ version = VERSION_NORMAL_CHIP_92D_SINGLEPHY; -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n"); -+ } -+ return version; -+} -+ -+static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo, -+ u8 *rom_content, bool autoloadfail) -+{ -+ u32 rfpath, eeaddr, group, offset1, offset2; -+ u8 i; -+ -+ memset(pwrinfo, 0, sizeof(struct txpower_info)); -+ if (autoloadfail) { -+ for (group = 0; group < CHANNEL_GROUP_MAX; group++) { -+ for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { -+ if (group < CHANNEL_GROUP_MAX_2G) { -+ pwrinfo->cck_index[rfpath][group] = -+ EEPROM_DEFAULT_TXPOWERLEVEL_2G; -+ pwrinfo->ht40_1sindex[rfpath][group] = -+ EEPROM_DEFAULT_TXPOWERLEVEL_2G; -+ } else { -+ pwrinfo->ht40_1sindex[rfpath][group] = -+ EEPROM_DEFAULT_TXPOWERLEVEL_5G; -+ } -+ pwrinfo->ht40_2sindexdiff[rfpath][group] = -+ EEPROM_DEFAULT_HT40_2SDIFF; -+ pwrinfo->ht20indexdiff[rfpath][group] = -+ EEPROM_DEFAULT_HT20_DIFF; -+ pwrinfo->ofdmindexdiff[rfpath][group] = -+ EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; -+ pwrinfo->ht40maxoffset[rfpath][group] = -+ EEPROM_DEFAULT_HT40_PWRMAXOFFSET; -+ pwrinfo->ht20maxoffset[rfpath][group] = -+ EEPROM_DEFAULT_HT20_PWRMAXOFFSET; -+ } -+ } -+ for (i = 0; i < 3; i++) { -+ pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI; -+ pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI; -+ } -+ return; -+ } -+ -+ /* Maybe autoload OK,buf the tx power index value is not filled. -+ * If we find it, we set it to default value. -+ */ -+ for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { -+ for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) { -+ eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3) -+ + group; -+ pwrinfo->cck_index[rfpath][group] = -+ (rom_content[eeaddr] == 0xFF) ? -+ (eeaddr > 0x7B ? -+ EEPROM_DEFAULT_TXPOWERLEVEL_5G : -+ EEPROM_DEFAULT_TXPOWERLEVEL_2G) : -+ rom_content[eeaddr]; -+ } -+ } -+ for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { -+ for (group = 0; group < CHANNEL_GROUP_MAX; group++) { -+ offset1 = group / 3; -+ offset2 = group % 3; -+ eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) + -+ offset2 + offset1 * 21; -+ pwrinfo->ht40_1sindex[rfpath][group] = -+ (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ? -+ EEPROM_DEFAULT_TXPOWERLEVEL_5G : -+ EEPROM_DEFAULT_TXPOWERLEVEL_2G) : -+ rom_content[eeaddr]; -+ } -+ } -+ /* These just for 92D efuse offset. */ -+ for (group = 0; group < CHANNEL_GROUP_MAX; group++) { -+ for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { -+ int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G; -+ -+ offset1 = group / 3; -+ offset2 = group % 3; -+ -+ if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF) -+ pwrinfo->ht40_2sindexdiff[rfpath][group] = -+ (rom_content[base1 + -+ offset2 + offset1 * 21] >> (rfpath * 4)) -+ & 0xF; -+ else -+ pwrinfo->ht40_2sindexdiff[rfpath][group] = -+ EEPROM_DEFAULT_HT40_2SDIFF; -+ if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2 -+ + offset1 * 21] != 0xFF) -+ pwrinfo->ht20indexdiff[rfpath][group] = -+ (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G -+ + offset2 + offset1 * 21] >> (rfpath * 4)) -+ & 0xF; -+ else -+ pwrinfo->ht20indexdiff[rfpath][group] = -+ EEPROM_DEFAULT_HT20_DIFF; -+ if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2 -+ + offset1 * 21] != 0xFF) -+ pwrinfo->ofdmindexdiff[rfpath][group] = -+ (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G -+ + offset2 + offset1 * 21] >> (rfpath * 4)) -+ & 0xF; -+ else -+ pwrinfo->ofdmindexdiff[rfpath][group] = -+ EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; -+ if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2 -+ + offset1 * 21] != 0xFF) -+ pwrinfo->ht40maxoffset[rfpath][group] = -+ (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G -+ + offset2 + offset1 * 21] >> (rfpath * 4)) -+ & 0xF; -+ else -+ pwrinfo->ht40maxoffset[rfpath][group] = -+ EEPROM_DEFAULT_HT40_PWRMAXOFFSET; -+ if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2 -+ + offset1 * 21] != 0xFF) -+ pwrinfo->ht20maxoffset[rfpath][group] = -+ (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + -+ offset2 + offset1 * 21] >> (rfpath * 4)) & -+ 0xF; -+ else -+ pwrinfo->ht20maxoffset[rfpath][group] = -+ EEPROM_DEFAULT_HT20_PWRMAXOFFSET; -+ } -+ } -+ if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) { -+ /* 5GL */ -+ pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F; -+ pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F; -+ /* 5GM */ -+ pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F; -+ pwrinfo->tssi_b[1] = -+ (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 | -+ (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2; -+ /* 5GH */ -+ pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] & -+ 0xF0) >> 4 | -+ (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4; -+ pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] & -+ 0xFC) >> 2; -+ } else { -+ for (i = 0; i < 3; i++) { -+ pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI; -+ pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI; -+ } -+ } -+} -+ -+static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw, -+ bool autoload_fail, u8 *hwinfo) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -+ struct txpower_info pwrinfo; -+ u8 tempval[2], i, pwr, diff; -+ u32 ch, rfpath, group; -+ -+ _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail); -+ if (!autoload_fail) { -+ /* bit0~2 */ -+ rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7); -+ rtlefuse->eeprom_thermalmeter = -+ hwinfo[EEPROM_THERMAL_METER] & 0x1f; -+ rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K]; -+ tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03; -+ tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2; -+ rtlefuse->txpwr_fromeprom = true; -+ if (IS_92D_D_CUT(rtlpriv->rtlhal.version) || -+ IS_92D_E_CUT(rtlpriv->rtlhal.version)) { -+ rtlefuse->internal_pa_5g[0] = -+ !((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6); -+ rtlefuse->internal_pa_5g[1] = -+ !((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6); -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, -+ "Is D cut,Internal PA0 %d Internal PA1 %d\n", -+ rtlefuse->internal_pa_5g[0], -+ rtlefuse->internal_pa_5g[1]); -+ } -+ rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6]; -+ rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7]; -+ } else { -+ rtlefuse->eeprom_regulatory = 0; -+ rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; -+ rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP; -+ tempval[0] = 3; -+ tempval[1] = tempval[0]; -+ } -+ -+ /* Use default value to fill parameters if -+ * efuse is not filled on some place. -+ */ -+ -+ /* ThermalMeter from EEPROM */ -+ if (rtlefuse->eeprom_thermalmeter < 0x06 || -+ rtlefuse->eeprom_thermalmeter > 0x1c) -+ rtlefuse->eeprom_thermalmeter = 0x12; -+ rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; -+ -+ /* check XTAL_K */ -+ if (rtlefuse->crystalcap == 0xFF) -+ rtlefuse->crystalcap = 0; -+ if (rtlefuse->eeprom_regulatory > 3) -+ rtlefuse->eeprom_regulatory = 0; -+ -+ for (i = 0; i < 2; i++) { -+ switch (tempval[i]) { -+ case 0: -+ tempval[i] = 5; -+ break; -+ case 1: -+ tempval[i] = 4; -+ break; -+ case 2: -+ tempval[i] = 3; -+ break; -+ case 3: -+ default: -+ tempval[i] = 0; -+ break; -+ } -+ } -+ -+ rtlefuse->delta_iqk = tempval[0]; -+ if (tempval[1] > 0) -+ rtlefuse->delta_lck = tempval[1] - 1; -+ if (rtlefuse->eeprom_c9 == 0xFF) -+ rtlefuse->eeprom_c9 = 0x00; -+ rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, -+ "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory); -+ rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, -+ "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); -+ rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, -+ "CrystalCap = 0x%x\n", rtlefuse->crystalcap); -+ rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, -+ "Delta_IQK = 0x%x Delta_LCK = 0x%x\n", -+ rtlefuse->delta_iqk, rtlefuse->delta_lck); -+ -+ for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { -+ for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) { -+ group = rtl92d_get_chnlgroup_fromarray((u8)ch); -+ if (ch < CHANNEL_MAX_NUMBER_2G) -+ rtlefuse->txpwrlevel_cck[rfpath][ch] = -+ pwrinfo.cck_index[rfpath][group]; -+ rtlefuse->txpwrlevel_ht40_1s[rfpath][ch] = -+ pwrinfo.ht40_1sindex[rfpath][group]; -+ rtlefuse->txpwr_ht20diff[rfpath][ch] = -+ pwrinfo.ht20indexdiff[rfpath][group]; -+ rtlefuse->txpwr_legacyhtdiff[rfpath][ch] = -+ pwrinfo.ofdmindexdiff[rfpath][group]; -+ rtlefuse->pwrgroup_ht20[rfpath][ch] = -+ pwrinfo.ht20maxoffset[rfpath][group]; -+ rtlefuse->pwrgroup_ht40[rfpath][ch] = -+ pwrinfo.ht40maxoffset[rfpath][group]; -+ pwr = pwrinfo.ht40_1sindex[rfpath][group]; -+ diff = pwrinfo.ht40_2sindexdiff[rfpath][group]; -+ rtlefuse->txpwrlevel_ht40_2s[rfpath][ch] = -+ (pwr > diff) ? (pwr - diff) : 0; -+ } -+ } -+} -+ -+static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw, -+ u8 *content) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION]; -+ -+ if (macphy_crvalue & BIT(3)) { -+ rtlhal->macphymode = SINGLEMAC_SINGLEPHY; -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "MacPhyMode SINGLEMAC_SINGLEPHY\n"); -+ } else { -+ rtlhal->macphymode = DUALMAC_DUALPHY; -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "MacPhyMode DUALMAC_DUALPHY\n"); -+ } -+} -+ -+static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw, -+ u8 *content) -+{ -+ _rtl92de_read_macphymode_from_prom(hw, content); -+ rtl92d_phy_config_macphymode(hw); -+ rtl92d_phy_config_macphymode_info(hw); -+} -+ -+static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ enum version_8192d chipver = rtlpriv->rtlhal.version; -+ u8 cutvalue[2]; -+ u16 chipvalue; -+ -+ read_efuse_byte(hw, EEPROME_CHIP_VERSION_H, &cutvalue[1]); -+ read_efuse_byte(hw, EEPROME_CHIP_VERSION_L, &cutvalue[0]); -+ chipvalue = (cutvalue[1] << 8) | cutvalue[0]; -+ switch (chipvalue) { -+ case 0xAA55: -+ chipver |= CHIP_92D_C_CUT; -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n"); -+ break; -+ case 0x9966: -+ chipver |= CHIP_92D_D_CUT; -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n"); -+ break; -+ case 0xCC33: -+ chipver |= CHIP_92D_E_CUT; -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n"); -+ break; -+ default: -+ chipver |= CHIP_92D_D_CUT; -+ pr_err("Unknown CUT!\n"); -+ break; -+ } -+ rtlpriv->rtlhal.version = chipver; -+} -+ -+static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, -+ EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D, -+ EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, -+ COUNTRY_CODE_WORLD_WIDE_13}; -+ int i; -+ u16 usvalue; -+ u8 *hwinfo; -+ -+ hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); -+ if (!hwinfo) -+ return; -+ -+ if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) -+ goto exit; -+ -+ _rtl92de_efuse_update_chip_version(hw); -+ _rtl92de_read_macphymode_and_bandtype(hw, hwinfo); -+ -+ /* Read Permanent MAC address for 2nd interface */ -+ if (rtlhal->interfaceindex != 0) { -+ for (i = 0; i < 6; i += 2) { -+ usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i]; -+ *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue; -+ } -+ } -+ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, -+ rtlefuse->dev_addr); -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); -+ _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo); -+ -+ /* Read Channel Plan */ -+ switch (rtlhal->bandset) { -+ case BAND_ON_2_4G: -+ rtlefuse->channel_plan = COUNTRY_CODE_TELEC; -+ break; -+ case BAND_ON_5G: -+ rtlefuse->channel_plan = COUNTRY_CODE_FCC; -+ break; -+ case BAND_ON_BOTH: -+ rtlefuse->channel_plan = COUNTRY_CODE_FCC; -+ break; -+ default: -+ rtlefuse->channel_plan = COUNTRY_CODE_FCC; -+ break; -+ } -+ rtlefuse->txpwr_fromeprom = true; -+exit: -+ kfree(hwinfo); -+} -+ -+void rtl92de_read_eeprom_info(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ u8 tmp_u1b; -+ -+ rtlhal->version = _rtl92d_read_chip_version(hw); -+ tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); -+ rtlefuse->autoload_status = tmp_u1b; -+ if (tmp_u1b & BIT(4)) { -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); -+ rtlefuse->epromtype = EEPROM_93C46; -+ } else { -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); -+ rtlefuse->epromtype = EEPROM_BOOT_EFUSE; -+ } -+ if (tmp_u1b & BIT(5)) { -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); -+ -+ rtlefuse->autoload_failflag = false; -+ _rtl92de_read_adapter_info(hw); -+ } else { -+ pr_err("Autoload ERR!!\n"); -+ } -+} -+EXPORT_SYMBOL_GPL(rtl92de_read_eeprom_info); -+ -+static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw, -+ struct ieee80211_sta *sta) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ u32 ratr_value; -+ u8 ratr_index = 0; -+ u8 nmode = mac->ht_enable; -+ u8 mimo_ps = IEEE80211_SMPS_OFF; -+ u16 shortgi_rate; -+ u32 tmp_ratr_value; -+ u8 curtxbw_40mhz = mac->bw_40; -+ u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? -+ 1 : 0; -+ u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? -+ 1 : 0; -+ enum wireless_mode wirelessmode = mac->mode; -+ -+ if (rtlhal->current_bandtype == BAND_ON_5G) -+ ratr_value = sta->deflink.supp_rates[1] << 4; -+ else -+ ratr_value = sta->deflink.supp_rates[0]; -+ ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | -+ sta->deflink.ht_cap.mcs.rx_mask[0] << 12); -+ switch (wirelessmode) { -+ case WIRELESS_MODE_A: -+ ratr_value &= 0x00000FF0; -+ break; -+ case WIRELESS_MODE_B: -+ if (ratr_value & 0x0000000c) -+ ratr_value &= 0x0000000d; -+ else -+ ratr_value &= 0x0000000f; -+ break; -+ case WIRELESS_MODE_G: -+ ratr_value &= 0x00000FF5; -+ break; -+ case WIRELESS_MODE_N_24G: -+ case WIRELESS_MODE_N_5G: -+ nmode = 1; -+ if (mimo_ps == IEEE80211_SMPS_STATIC) { -+ ratr_value &= 0x0007F005; -+ } else { -+ u32 ratr_mask; -+ -+ if (get_rf_type(rtlphy) == RF_1T2R || -+ get_rf_type(rtlphy) == RF_1T1R) { -+ ratr_mask = 0x000ff005; -+ } else { -+ ratr_mask = 0x0f0ff005; -+ } -+ -+ ratr_value &= ratr_mask; -+ } -+ break; -+ default: -+ if (rtlphy->rf_type == RF_1T2R) -+ ratr_value &= 0x000ff0ff; -+ else -+ ratr_value &= 0x0f0ff0ff; -+ -+ break; -+ } -+ ratr_value &= 0x0FFFFFFF; -+ if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) || -+ (!curtxbw_40mhz && curshortgi_20mhz))) { -+ ratr_value |= 0x10000000; -+ tmp_ratr_value = (ratr_value >> 12); -+ for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { -+ if ((1 << shortgi_rate) & tmp_ratr_value) -+ break; -+ } -+ shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | -+ (shortgi_rate << 4) | (shortgi_rate); -+ } -+ rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); -+ rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", -+ rtl_read_dword(rtlpriv, REG_ARFR0)); -+} -+ -+static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, -+ struct ieee80211_sta *sta, -+ u8 rssi_level, bool update_bw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ struct rtl_sta_info *sta_entry = NULL; -+ u32 ratr_bitmap; -+ u8 ratr_index; -+ u8 curtxbw_40mhz = (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; -+ u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? -+ 1 : 0; -+ u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? -+ 1 : 0; -+ enum wireless_mode wirelessmode = 0; -+ bool shortgi = false; -+ u32 value[2]; -+ u8 macid = 0; -+ u8 mimo_ps = IEEE80211_SMPS_OFF; -+ -+ sta_entry = (struct rtl_sta_info *)sta->drv_priv; -+ mimo_ps = sta_entry->mimo_ps; -+ wirelessmode = sta_entry->wireless_mode; -+ if (mac->opmode == NL80211_IFTYPE_STATION) -+ curtxbw_40mhz = mac->bw_40; -+ else if (mac->opmode == NL80211_IFTYPE_AP || -+ mac->opmode == NL80211_IFTYPE_ADHOC) -+ macid = sta->aid + 1; -+ -+ if (rtlhal->current_bandtype == BAND_ON_5G) -+ ratr_bitmap = sta->deflink.supp_rates[1] << 4; -+ else -+ ratr_bitmap = sta->deflink.supp_rates[0]; -+ ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | -+ sta->deflink.ht_cap.mcs.rx_mask[0] << 12); -+ switch (wirelessmode) { -+ case WIRELESS_MODE_B: -+ ratr_index = RATR_INX_WIRELESS_B; -+ if (ratr_bitmap & 0x0000000c) -+ ratr_bitmap &= 0x0000000d; -+ else -+ ratr_bitmap &= 0x0000000f; -+ break; -+ case WIRELESS_MODE_G: -+ ratr_index = RATR_INX_WIRELESS_GB; -+ -+ if (rssi_level == 1) -+ ratr_bitmap &= 0x00000f00; -+ else if (rssi_level == 2) -+ ratr_bitmap &= 0x00000ff0; -+ else -+ ratr_bitmap &= 0x00000ff5; -+ break; -+ case WIRELESS_MODE_A: -+ ratr_index = RATR_INX_WIRELESS_G; -+ ratr_bitmap &= 0x00000ff0; -+ break; -+ case WIRELESS_MODE_N_24G: -+ case WIRELESS_MODE_N_5G: -+ if (wirelessmode == WIRELESS_MODE_N_24G) -+ ratr_index = RATR_INX_WIRELESS_NGB; -+ else -+ ratr_index = RATR_INX_WIRELESS_NG; -+ if (mimo_ps == IEEE80211_SMPS_STATIC) { -+ if (rssi_level == 1) -+ ratr_bitmap &= 0x00070000; -+ else if (rssi_level == 2) -+ ratr_bitmap &= 0x0007f000; -+ else -+ ratr_bitmap &= 0x0007f005; -+ } else { -+ if (rtlphy->rf_type == RF_1T2R || -+ rtlphy->rf_type == RF_1T1R) { -+ if (curtxbw_40mhz) { -+ if (rssi_level == 1) -+ ratr_bitmap &= 0x000f0000; -+ else if (rssi_level == 2) -+ ratr_bitmap &= 0x000ff000; -+ else -+ ratr_bitmap &= 0x000ff015; -+ } else { -+ if (rssi_level == 1) -+ ratr_bitmap &= 0x000f0000; -+ else if (rssi_level == 2) -+ ratr_bitmap &= 0x000ff000; -+ else -+ ratr_bitmap &= 0x000ff005; -+ } -+ } else { -+ if (curtxbw_40mhz) { -+ if (rssi_level == 1) -+ ratr_bitmap &= 0x0f0f0000; -+ else if (rssi_level == 2) -+ ratr_bitmap &= 0x0f0ff000; -+ else -+ ratr_bitmap &= 0x0f0ff015; -+ } else { -+ if (rssi_level == 1) -+ ratr_bitmap &= 0x0f0f0000; -+ else if (rssi_level == 2) -+ ratr_bitmap &= 0x0f0ff000; -+ else -+ ratr_bitmap &= 0x0f0ff005; -+ } -+ } -+ } -+ if ((curtxbw_40mhz && curshortgi_40mhz) || -+ (!curtxbw_40mhz && curshortgi_20mhz)) { -+ if (macid == 0) -+ shortgi = true; -+ else if (macid == 1) -+ shortgi = false; -+ } -+ break; -+ default: -+ ratr_index = RATR_INX_WIRELESS_NGB; -+ -+ if (rtlphy->rf_type == RF_1T2R) -+ ratr_bitmap &= 0x000ff0ff; -+ else -+ ratr_bitmap &= 0x0f0ff0ff; -+ break; -+ } -+ -+ value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28); -+ value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80; -+ rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, -+ "ratr_bitmap :%x value0:%x value1:%x\n", -+ ratr_bitmap, value[0], value[1]); -+ rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *)value); -+ if (macid != 0) -+ sta_entry->ratr_index = ratr_index; -+} -+ -+void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw, -+ struct ieee80211_sta *sta, -+ u8 rssi_level, bool update_bw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ if (rtlpriv->dm.useramask) -+ rtl92de_update_hal_rate_mask(hw, sta, rssi_level, update_bw); -+ else -+ rtl92de_update_hal_rate_table(hw, sta); -+} -+EXPORT_SYMBOL_GPL(rtl92de_update_hal_rate_tbl); -+ -+void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -+ u16 sifs_timer; -+ -+ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, -+ &mac->slot_time); -+ if (!mac->ht_enable) -+ sifs_timer = 0x0a0a; -+ else -+ sifs_timer = 0x1010; -+ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); -+} -+EXPORT_SYMBOL_GPL(rtl92de_update_channel_access_setting); -+ -+bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); -+ struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); -+ enum rf_pwrstate e_rfpowerstate_toset; -+ u8 u1tmp; -+ bool actuallyset = false; -+ unsigned long flag; -+ -+ if (rtlpci->being_init_adapter) -+ return false; -+ if (ppsc->swrf_processing) -+ return false; -+ spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); -+ if (ppsc->rfchange_inprogress) { -+ spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); -+ return false; -+ } -+ -+ ppsc->rfchange_inprogress = true; -+ spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); -+ -+ rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, -+ rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG) & ~(BIT(3))); -+ u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); -+ e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; -+ if (ppsc->hwradiooff && e_rfpowerstate_toset == ERFON) { -+ rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, -+ "GPIOChangeRF - HW Radio ON, RF ON\n"); -+ e_rfpowerstate_toset = ERFON; -+ ppsc->hwradiooff = false; -+ actuallyset = true; -+ } else if (!ppsc->hwradiooff && e_rfpowerstate_toset == ERFOFF) { -+ rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, -+ "GPIOChangeRF - HW Radio OFF, RF OFF\n"); -+ e_rfpowerstate_toset = ERFOFF; -+ ppsc->hwradiooff = true; -+ actuallyset = true; -+ } -+ if (actuallyset) { -+ spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); -+ ppsc->rfchange_inprogress = false; -+ spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); -+ } else { -+ if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) -+ RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); -+ spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); -+ ppsc->rfchange_inprogress = false; -+ spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); -+ } -+ *valid = 1; -+ return !ppsc->hwradiooff; -+} -+EXPORT_SYMBOL_GPL(rtl92de_gpio_radio_on_off_checking); -+ -+void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, -+ u8 *p_macaddr, bool is_group, u8 enc_algo, -+ bool is_wepkey, bool clear_all) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -+ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -+ const u8 *macaddr = p_macaddr; -+ u32 entry_id; -+ bool is_pairwise = false; -+ static const u8 cam_const_addr[4][6] = { -+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, -+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, -+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, -+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} -+ }; -+ static const u8 cam_const_broad[] = { -+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff -+ }; -+ -+ if (clear_all) { -+ u8 idx; -+ u8 cam_offset = 0; -+ u8 clear_number = 5; -+ -+ rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); -+ for (idx = 0; idx < clear_number; idx++) { -+ rtl_cam_mark_invalid(hw, cam_offset + idx); -+ rtl_cam_empty_entry(hw, cam_offset + idx); -+ -+ if (idx < 5) { -+ memset(rtlpriv->sec.key_buf[idx], 0, -+ MAX_KEY_LEN); -+ rtlpriv->sec.key_len[idx] = 0; -+ } -+ } -+ -+ return; -+ } -+ -+ switch (enc_algo) { -+ case WEP40_ENCRYPTION: -+ enc_algo = CAM_WEP40; -+ break; -+ case WEP104_ENCRYPTION: -+ enc_algo = CAM_WEP104; -+ break; -+ case TKIP_ENCRYPTION: -+ enc_algo = CAM_TKIP; -+ break; -+ case AESCCMP_ENCRYPTION: -+ enc_algo = CAM_AES; -+ break; -+ default: -+ pr_err("switch case %#x not processed\n", -+ enc_algo); -+ enc_algo = CAM_TKIP; -+ break; -+ } -+ if (is_wepkey || rtlpriv->sec.use_defaultkey) { -+ macaddr = cam_const_addr[key_index]; -+ entry_id = key_index; -+ } else { -+ if (is_group) { -+ macaddr = cam_const_broad; -+ entry_id = key_index; -+ } else { -+ if (mac->opmode == NL80211_IFTYPE_AP) { -+ entry_id = rtl_cam_get_free_entry(hw, p_macaddr); -+ if (entry_id >= TOTAL_CAM_ENTRY) { -+ pr_err("Can not find free hw security cam entry\n"); -+ return; -+ } -+ } else { -+ entry_id = CAM_PAIRWISE_KEY_POSITION; -+ } -+ key_index = PAIRWISE_KEYIDX; -+ is_pairwise = true; -+ } -+ } -+ if (rtlpriv->sec.key_len[key_index] == 0) { -+ rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, -+ "delete one entry, entry_id is %d\n", -+ entry_id); -+ if (mac->opmode == NL80211_IFTYPE_AP) -+ rtl_cam_del_entry(hw, p_macaddr); -+ rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); -+ } else { -+ rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, -+ "The insert KEY length is %d\n", -+ rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); -+ rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, -+ "The insert KEY is %x %x\n", -+ rtlpriv->sec.key_buf[0][0], -+ rtlpriv->sec.key_buf[0][1]); -+ rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, -+ "add one entry\n"); -+ if (is_pairwise) { -+ RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, -+ "Pairwise Key content", -+ rtlpriv->sec.pairwise_key, -+ rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); -+ rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, -+ "set Pairwise key\n"); -+ rtl_cam_add_one_entry(hw, macaddr, key_index, -+ entry_id, enc_algo, -+ CAM_CONFIG_NO_USEDK, -+ rtlpriv->sec.key_buf[key_index]); -+ } else { -+ rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, -+ "set group key\n"); -+ if (mac->opmode == NL80211_IFTYPE_ADHOC) { -+ rtl_cam_add_one_entry(hw, -+ rtlefuse->dev_addr, -+ PAIRWISE_KEYIDX, -+ CAM_PAIRWISE_KEY_POSITION, -+ enc_algo, CAM_CONFIG_NO_USEDK, -+ rtlpriv->sec.key_buf[entry_id]); -+ } -+ rtl_cam_add_one_entry(hw, macaddr, key_index, -+ entry_id, enc_algo, -+ CAM_CONFIG_NO_USEDK, -+ rtlpriv->sec.key_buf -+ [entry_id]); -+ } -+ } -+} -+EXPORT_SYMBOL_GPL(rtl92de_set_key); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.h -new file mode 100644 -index 000000000000..2c07f5cc5766 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.h -@@ -0,0 +1,24 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* Copyright(c) 2009-2012 Realtek Corporation.*/ -+ -+#ifndef __RTL92D_HW_COMMON_H__ -+#define __RTL92D_HW_COMMON_H__ -+ -+void rtl92de_stop_tx_beacon(struct ieee80211_hw *hw); -+void rtl92de_resume_tx_beacon(struct ieee80211_hw *hw); -+void rtl92d_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); -+void rtl92d_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); -+bool rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data); -+void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw); -+void rtl92de_set_qos(struct ieee80211_hw *hw, int aci); -+void rtl92de_read_eeprom_info(struct ieee80211_hw *hw); -+void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw, -+ struct ieee80211_sta *sta, -+ u8 rssi_level, bool update_bw); -+void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw); -+bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid); -+void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, -+ u8 *p_macaddr, bool is_group, u8 enc_algo, -+ bool is_wepkey, bool clear_all); -+ -+#endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/main.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/main.c -new file mode 100644 -index 000000000000..e58dc4000c19 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/main.c -@@ -0,0 +1,9 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright(c) 2009-2012 Realtek Corporation.*/ -+ -+#include "../wifi.h" -+#include -+ -+MODULE_AUTHOR("Realtek WlanFAE "); -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("Realtek 8192D 802.11n common routines"); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c -new file mode 100644 -index 000000000000..87c458b27f4f ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c -@@ -0,0 +1,846 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright(c) 2009-2012 Realtek Corporation.*/ -+ -+#include "../wifi.h" -+#include "../core.h" -+#include "def.h" -+#include "reg.h" -+#include "dm_common.h" -+#include "phy_common.h" -+#include "rf_common.h" -+ -+static const u8 channel_all[59] = { -+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, -+ 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, -+ 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, -+ 114, 116, 118, 120, 122, 124, 126, 128, 130, -+ 132, 134, 136, 138, 140, 149, 151, 153, 155, -+ 157, 159, 161, 163, 165 -+}; -+ -+static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw, -+ enum radio_path rfpath, u32 offset) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; -+ u32 newoffset; -+ u32 tmplong, tmplong2; -+ u8 rfpi_enable = 0; -+ u32 retvalue; -+ -+ newoffset = offset; -+ tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); -+ if (rfpath == RF90_PATH_A) -+ tmplong2 = tmplong; -+ else -+ tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); -+ tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | -+ (newoffset << 23) | BLSSIREADEDGE; -+ rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, -+ tmplong & (~BLSSIREADEDGE)); -+ udelay(10); -+ rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); -+ udelay(50); -+ udelay(50); -+ rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, -+ tmplong | BLSSIREADEDGE); -+ udelay(10); -+ if (rfpath == RF90_PATH_A) -+ rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, -+ BIT(8)); -+ else if (rfpath == RF90_PATH_B) -+ rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, -+ BIT(8)); -+ if (rfpi_enable) -+ retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, -+ BLSSIREADBACKDATA); -+ else -+ retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, -+ BLSSIREADBACKDATA); -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n", -+ rfpath, pphyreg->rf_rb, retvalue); -+ return retvalue; -+} -+ -+static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw, -+ enum radio_path rfpath, -+ u32 offset, u32 data) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; -+ u32 data_and_addr; -+ u32 newoffset; -+ -+ newoffset = offset; -+ /* T65 RF */ -+ data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; -+ rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", -+ rfpath, pphyreg->rf3wire_offset, data_and_addr); -+} -+ -+u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, -+ u32 regaddr, u32 bitmask) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 original_value, readback_value, bitshift; -+ -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, -+ "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", -+ regaddr, rfpath, bitmask); -+ spin_lock(&rtlpriv->locks.rf_lock); -+ original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr); -+ bitshift = calculate_bit_shift(bitmask); -+ readback_value = (original_value & bitmask) >> bitshift; -+ spin_unlock(&rtlpriv->locks.rf_lock); -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, -+ "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", -+ regaddr, rfpath, bitmask, original_value); -+ return readback_value; -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_query_rf_reg); -+ -+void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, -+ u32 regaddr, u32 bitmask, u32 data) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u32 original_value, bitshift; -+ -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, -+ "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", -+ regaddr, bitmask, data, rfpath); -+ if (bitmask == 0) -+ return; -+ spin_lock(&rtlpriv->locks.rf_lock); -+ if (rtlphy->rf_mode != RF_OP_BY_FW) { -+ if (bitmask != RFREG_OFFSET_MASK) { -+ original_value = _rtl92d_phy_rf_serial_read(hw, -+ rfpath, -+ regaddr); -+ bitshift = calculate_bit_shift(bitmask); -+ data = ((original_value & (~bitmask)) | -+ (data << bitshift)); -+ } -+ _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data); -+ } -+ spin_unlock(&rtlpriv->locks.rf_lock); -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, -+ "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", -+ regaddr, bitmask, data, rfpath); -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_set_rf_reg); -+ -+void rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ -+ /* RF Interface Sowrtware Control */ -+ /* 16 LSBs if read 32-bit from 0x870 */ -+ rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; -+ /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ -+ rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; -+ /* 16 LSBs if read 32-bit from 0x874 */ -+ rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; -+ /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ -+ -+ rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; -+ /* RF Interface Readback Value */ -+ /* 16 LSBs if read 32-bit from 0x8E0 */ -+ rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; -+ /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ -+ rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; -+ /* 16 LSBs if read 32-bit from 0x8E4 */ -+ rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; -+ /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ -+ rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; -+ -+ /* RF Interface Output (and Enable) */ -+ /* 16 LSBs if read 32-bit from 0x860 */ -+ rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; -+ /* 16 LSBs if read 32-bit from 0x864 */ -+ rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; -+ -+ /* RF Interface (Output and) Enable */ -+ /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ -+ rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; -+ /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ -+ rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; -+ -+ /* Addr of LSSI. Write RF register by driver */ -+ /* LSSI Parameter */ -+ rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = -+ RFPGA0_XA_LSSIPARAMETER; -+ rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = -+ RFPGA0_XB_LSSIPARAMETER; -+ -+ /* RF parameter */ -+ /* BB Band Select */ -+ rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; -+ rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; -+ rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; -+ rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; -+ -+ /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ -+ /* Tx gain stage */ -+ rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; -+ /* Tx gain stage */ -+ rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; -+ /* Tx gain stage */ -+ rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; -+ /* Tx gain stage */ -+ rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; -+ -+ /* Transceiver A~D HSSI Parameter-1 */ -+ /* wire control parameter1 */ -+ rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; -+ /* wire control parameter1 */ -+ rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; -+ -+ /* Transceiver A~D HSSI Parameter-2 */ -+ /* wire control parameter2 */ -+ rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; -+ /* wire control parameter2 */ -+ rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; -+ -+ /* RF switch Control */ -+ /* TR/Ant switch control */ -+ rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; -+ rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; -+ rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; -+ rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; -+ -+ /* AGC control 1 */ -+ rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; -+ rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; -+ rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; -+ rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; -+ -+ /* AGC control 2 */ -+ rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; -+ rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; -+ rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; -+ rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; -+ -+ /* RX AFE control 1 */ -+ rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; -+ rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; -+ rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE; -+ rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; -+ -+ /*RX AFE control 1 */ -+ rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; -+ rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; -+ rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; -+ rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; -+ -+ /* Tx AFE control 1 */ -+ rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; -+ rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; -+ rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; -+ rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; -+ -+ /* Tx AFE control 2 */ -+ rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; -+ rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; -+ rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE; -+ rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE; -+ -+ /* Transceiver LSSI Readback SI mode */ -+ rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; -+ rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; -+ rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; -+ rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; -+ -+ /* Transceiver LSSI Readback PI mode */ -+ rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK; -+ rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK; -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_init_bb_rf_register_definition); -+ -+void rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, -+ u32 regaddr, u32 bitmask, u32 data) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ int index; -+ -+ if (regaddr == RTXAGC_A_RATE18_06) -+ index = 0; -+ else if (regaddr == RTXAGC_A_RATE54_24) -+ index = 1; -+ else if (regaddr == RTXAGC_A_CCK1_MCS32) -+ index = 6; -+ else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) -+ index = 7; -+ else if (regaddr == RTXAGC_A_MCS03_MCS00) -+ index = 2; -+ else if (regaddr == RTXAGC_A_MCS07_MCS04) -+ index = 3; -+ else if (regaddr == RTXAGC_A_MCS11_MCS08) -+ index = 4; -+ else if (regaddr == RTXAGC_A_MCS15_MCS12) -+ index = 5; -+ else if (regaddr == RTXAGC_B_RATE18_06) -+ index = 8; -+ else if (regaddr == RTXAGC_B_RATE54_24) -+ index = 9; -+ else if (regaddr == RTXAGC_B_CCK1_55_MCS32) -+ index = 14; -+ else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) -+ index = 15; -+ else if (regaddr == RTXAGC_B_MCS03_MCS00) -+ index = 10; -+ else if (regaddr == RTXAGC_B_MCS07_MCS04) -+ index = 11; -+ else if (regaddr == RTXAGC_B_MCS11_MCS08) -+ index = 12; -+ else if (regaddr == RTXAGC_B_MCS15_MCS12) -+ index = 13; -+ else -+ return; -+ -+ rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, -+ "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", -+ rtlphy->pwrgroup_cnt, index, -+ rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]); -+ if (index == 13) -+ rtlphy->pwrgroup_cnt++; -+} -+EXPORT_SYMBOL_GPL(rtl92d_store_pwrindex_diffrate_offset); -+ -+void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ -+ rtlphy->default_initialgain[0] = -+ (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); -+ rtlphy->default_initialgain[1] = -+ (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); -+ rtlphy->default_initialgain[2] = -+ (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); -+ rtlphy->default_initialgain[3] = -+ (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, -+ "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", -+ rtlphy->default_initialgain[0], -+ rtlphy->default_initialgain[1], -+ rtlphy->default_initialgain[2], -+ rtlphy->default_initialgain[3]); -+ rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, -+ MASKBYTE0); -+ rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, -+ MASKDWORD); -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, -+ "Default framesync (0x%x) = 0x%x\n", -+ ROFDM0_RXDETECTOR3, rtlphy->framesync); -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_get_hw_reg_originalvalue); -+ -+static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel, -+ u8 *cckpowerlevel, u8 *ofdmpowerlevel) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; -+ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -+ u8 index = (channel - 1); -+ -+ /* 1. CCK */ -+ if (rtlhal->current_bandtype == BAND_ON_2_4G) { -+ /* RF-A */ -+ cckpowerlevel[RF90_PATH_A] = -+ rtlefuse->txpwrlevel_cck[RF90_PATH_A][index]; -+ /* RF-B */ -+ cckpowerlevel[RF90_PATH_B] = -+ rtlefuse->txpwrlevel_cck[RF90_PATH_B][index]; -+ } else { -+ cckpowerlevel[RF90_PATH_A] = 0; -+ cckpowerlevel[RF90_PATH_B] = 0; -+ } -+ /* 2. OFDM for 1S or 2S */ -+ if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) { -+ /* Read HT 40 OFDM TX power */ -+ ofdmpowerlevel[RF90_PATH_A] = -+ rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index]; -+ ofdmpowerlevel[RF90_PATH_B] = -+ rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index]; -+ } else if (rtlphy->rf_type == RF_2T2R) { -+ /* Read HT 40 OFDM TX power */ -+ ofdmpowerlevel[RF90_PATH_A] = -+ rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index]; -+ ofdmpowerlevel[RF90_PATH_B] = -+ rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index]; -+ } -+} -+ -+static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw, -+ u8 channel, u8 *cckpowerlevel, -+ u8 *ofdmpowerlevel) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ -+ rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; -+ rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; -+} -+ -+static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl) -+{ -+ u8 place = chnl; -+ -+ if (chnl > 14) { -+ for (place = 14; place < ARRAY_SIZE(channel_all); place++) { -+ if (channel_all[place] == chnl) { -+ place++; -+ break; -+ } -+ } -+ } -+ return place; -+} -+ -+void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) -+{ -+ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u8 cckpowerlevel[2], ofdmpowerlevel[2]; -+ -+ if (!rtlefuse->txpwr_fromeprom) -+ return; -+ channel = _rtl92c_phy_get_rightchnlplace(channel); -+ _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0], -+ &ofdmpowerlevel[0]); -+ if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) -+ _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0], -+ &ofdmpowerlevel[0]); -+ if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) -+ rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); -+ rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel); -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_set_txpower_level); -+ -+void rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw, u8 rfpath, -+ u32 *pu4_regval) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; -+ -+ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "====>\n"); -+ /*----Store original RFENV control type----*/ -+ switch (rfpath) { -+ case RF90_PATH_A: -+ case RF90_PATH_C: -+ *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV); -+ break; -+ case RF90_PATH_B: -+ case RF90_PATH_D: -+ *pu4_regval = -+ rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16); -+ break; -+ } -+ /*----Set RF_ENV enable----*/ -+ rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); -+ udelay(1); -+ /*----Set RF_ENV output high----*/ -+ rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); -+ udelay(1); -+ /* Set bit number of Address and Data for RF register */ -+ /* Set 1 to 4 bits for 8255 */ -+ rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0); -+ udelay(1); -+ /*Set 0 to 12 bits for 8255 */ -+ rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); -+ udelay(1); -+ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<====\n"); -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_enable_rf_env); -+ -+void rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath, -+ u32 *pu4_regval) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; -+ -+ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n"); -+ /*----Restore RFENV control type----*/ -+ switch (rfpath) { -+ case RF90_PATH_A: -+ case RF90_PATH_C: -+ rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval); -+ break; -+ case RF90_PATH_B: -+ case RF90_PATH_D: -+ rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16, -+ *pu4_regval); -+ break; -+ } -+ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n"); -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_restore_rf_env); -+ -+u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl) -+{ -+ u8 place; -+ -+ if (chnl > 14) { -+ for (place = 14; place < ARRAY_SIZE(channel_all); place++) { -+ if (channel_all[place] == chnl) -+ return place - 13; -+ } -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(rtl92d_get_rightchnlplace_for_iqk); -+ -+void rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw, const u32 *adda_reg, -+ u32 *adda_backup, u32 regnum) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 i; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n"); -+ for (i = 0; i < regnum; i++) -+ adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD); -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_save_adda_registers); -+ -+void rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw, -+ const u32 *macreg, u32 *macbackup) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 i; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save MAC parameters.\n"); -+ for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) -+ macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]); -+ macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]); -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_save_mac_registers); -+ -+void rtl92d_phy_path_adda_on(struct ieee80211_hw *hw, -+ const u32 *adda_reg, bool patha_on, bool is2t) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 pathon; -+ u32 i; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "ADDA ON.\n"); -+ pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4; -+ if (patha_on) -+ pathon = rtlpriv->rtlhal.interfaceindex == 0 ? -+ 0x04db25a4 : 0x0b1b25a4; -+ for (i = 0; i < IQK_ADDA_REG_NUM; i++) -+ rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon); -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_path_adda_on); -+ -+void rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw, -+ const u32 *macreg, u32 *macbackup) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 i; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "MAC settings for Calibration.\n"); -+ rtl_write_byte(rtlpriv, macreg[0], 0x3F); -+ -+ for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) -+ rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & -+ (~BIT(3)))); -+ rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & (~BIT(5)))); -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_mac_setting_calibration); -+ -+static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2) -+{ -+ u32 ret; -+ -+ if (val1 >= val2) -+ ret = val1 - val2; -+ else -+ ret = val2 - val1; -+ return ret; -+} -+ -+static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(channel5g); i++) -+ if (channel == channel5g[i]) -+ return true; -+ return false; -+} -+ -+void rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw, -+ const u32 *targetchnl, u32 *curvecount_val, -+ bool is5g, u32 *curveindex) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 smallest_abs_val = 0xffffffff, u4tmp; -+ u8 i, j; -+ u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G; -+ -+ for (i = 0; i < chnl_num; i++) { -+ if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1)) -+ continue; -+ curveindex[i] = 0; -+ for (j = 0; j < (CV_CURVE_CNT * 2); j++) { -+ u4tmp = _rtl92d_phy_get_abs(targetchnl[i], -+ curvecount_val[j]); -+ -+ if (u4tmp < smallest_abs_val) { -+ curveindex[i] = j; -+ smallest_abs_val = u4tmp; -+ } -+ } -+ smallest_abs_val = 0xffffffff; -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n", -+ i, curveindex[i]); -+ } -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_calc_curvindex); -+ -+void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u8 i; -+ -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "settings regs %zu default regs %d\n", -+ ARRAY_SIZE(rtlphy->iqk_matrix), -+ IQK_MATRIX_REG_NUM); -+ /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */ -+ for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) { -+ rtlphy->iqk_matrix[i].value[0][0] = 0x100; -+ rtlphy->iqk_matrix[i].value[0][2] = 0x100; -+ rtlphy->iqk_matrix[i].value[0][4] = 0x100; -+ rtlphy->iqk_matrix[i].value[0][6] = 0x100; -+ rtlphy->iqk_matrix[i].value[0][1] = 0x0; -+ rtlphy->iqk_matrix[i].value[0][3] = 0x0; -+ rtlphy->iqk_matrix[i].value[0][5] = 0x0; -+ rtlphy->iqk_matrix[i].value[0][7] = 0x0; -+ rtlphy->iqk_matrix[i].iqk_done = false; -+ } -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_reset_iqk_result); -+ -+static void rtl92d_phy_set_io(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct dig_t *de_digtable = &rtlpriv->dm_digtable; -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, -+ "--->Cmd(%#x), set_io_inprogress(%d)\n", -+ rtlphy->current_io_type, rtlphy->set_io_inprogress); -+ switch (rtlphy->current_io_type) { -+ case IO_CMD_RESUME_DM_BY_SCAN: -+ de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; -+ rtl92d_dm_write_dig(hw); -+ rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel); -+ break; -+ case IO_CMD_PAUSE_DM_BY_SCAN: -+ rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue; -+ de_digtable->cur_igvalue = 0x37; -+ rtl92d_dm_write_dig(hw); -+ break; -+ default: -+ pr_err("switch case %#x not processed\n", -+ rtlphy->current_io_type); -+ break; -+ } -+ rtlphy->set_io_inprogress = false; -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n", -+ rtlphy->current_io_type); -+} -+ -+bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ bool postprocessing = false; -+ -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, -+ "-->IO Cmd(%#x), set_io_inprogress(%d)\n", -+ iotype, rtlphy->set_io_inprogress); -+ do { -+ switch (iotype) { -+ case IO_CMD_RESUME_DM_BY_SCAN: -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, -+ "[IO CMD] Resume DM after scan\n"); -+ postprocessing = true; -+ break; -+ case IO_CMD_PAUSE_DM_BY_SCAN: -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, -+ "[IO CMD] Pause DM before scan\n"); -+ postprocessing = true; -+ break; -+ default: -+ pr_err("switch case %#x not processed\n", -+ iotype); -+ break; -+ } -+ } while (false); -+ if (postprocessing && !rtlphy->set_io_inprogress) { -+ rtlphy->set_io_inprogress = true; -+ rtlphy->current_io_type = iotype; -+ } else { -+ return false; -+ } -+ rtl92d_phy_set_io(hw); -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype); -+ return true; -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_set_io_cmd); -+ -+void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ u8 offset = REG_MAC_PHY_CTRL_NORMAL; -+ -+ switch (rtlhal->macphymode) { -+ case DUALMAC_DUALPHY: -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "MacPhyMode: DUALMAC_DUALPHY\n"); -+ rtl_write_byte(rtlpriv, offset, 0xF3); -+ break; -+ case SINGLEMAC_SINGLEPHY: -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "MacPhyMode: SINGLEMAC_SINGLEPHY\n"); -+ rtl_write_byte(rtlpriv, offset, 0xF4); -+ break; -+ case DUALMAC_SINGLEPHY: -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "MacPhyMode: DUALMAC_SINGLEPHY\n"); -+ rtl_write_byte(rtlpriv, offset, 0xF1); -+ break; -+ } -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_config_macphymode); -+ -+void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ -+ switch (rtlhal->macphymode) { -+ case DUALMAC_SINGLEPHY: -+ rtlphy->rf_type = RF_2T2R; -+ rtlhal->version |= RF_TYPE_2T2R; -+ rtlhal->bandset = BAND_ON_BOTH; -+ rtlhal->current_bandtype = BAND_ON_2_4G; -+ break; -+ -+ case SINGLEMAC_SINGLEPHY: -+ rtlphy->rf_type = RF_2T2R; -+ rtlhal->version |= RF_TYPE_2T2R; -+ rtlhal->bandset = BAND_ON_BOTH; -+ rtlhal->current_bandtype = BAND_ON_2_4G; -+ break; -+ -+ case DUALMAC_DUALPHY: -+ rtlphy->rf_type = RF_1T1R; -+ rtlhal->version &= RF_TYPE_1T1R; -+ /* Now we let MAC0 run on 5G band. */ -+ if (rtlhal->interfaceindex == 0) { -+ rtlhal->bandset = BAND_ON_5G; -+ rtlhal->current_bandtype = BAND_ON_5G; -+ } else { -+ rtlhal->bandset = BAND_ON_2_4G; -+ rtlhal->current_bandtype = BAND_ON_2_4G; -+ } -+ break; -+ default: -+ break; -+ } -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_config_macphymode_info); -+ -+u8 rtl92d_get_chnlgroup_fromarray(u8 chnl) -+{ -+ u8 group; -+ -+ if (channel_all[chnl] <= 3) -+ group = 0; -+ else if (channel_all[chnl] <= 9) -+ group = 1; -+ else if (channel_all[chnl] <= 14) -+ group = 2; -+ else if (channel_all[chnl] <= 44) -+ group = 3; -+ else if (channel_all[chnl] <= 54) -+ group = 4; -+ else if (channel_all[chnl] <= 64) -+ group = 5; -+ else if (channel_all[chnl] <= 112) -+ group = 6; -+ else if (channel_all[chnl] <= 126) -+ group = 7; -+ else if (channel_all[chnl] <= 140) -+ group = 8; -+ else if (channel_all[chnl] <= 153) -+ group = 9; -+ else if (channel_all[chnl] <= 159) -+ group = 10; -+ else -+ group = 11; -+ return group; -+} -+EXPORT_SYMBOL_GPL(rtl92d_get_chnlgroup_fromarray); -+ -+u8 rtl92d_phy_get_chnlgroup_bypg(u8 chnlindex) -+{ -+ u8 group; -+ -+ if (channel_all[chnlindex] <= 3) /* Chanel 1-3 */ -+ group = 0; -+ else if (channel_all[chnlindex] <= 9) /* Channel 4-9 */ -+ group = 1; -+ else if (channel_all[chnlindex] <= 14) /* Channel 10-14 */ -+ group = 2; -+ else if (channel_all[chnlindex] <= 64) -+ group = 6; -+ else if (channel_all[chnlindex] <= 140) -+ group = 7; -+ else -+ group = 8; -+ return group; -+} -+ -+void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ switch (rtlpriv->rtlhal.macphymode) { -+ case DUALMAC_DUALPHY: -+ rtl_write_byte(rtlpriv, REG_DMC, 0x0); -+ rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); -+ rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); -+ break; -+ case DUALMAC_SINGLEPHY: -+ rtl_write_byte(rtlpriv, REG_DMC, 0xf8); -+ rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); -+ rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); -+ break; -+ case SINGLEMAC_SINGLEPHY: -+ rtl_write_byte(rtlpriv, REG_DMC, 0x0); -+ rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10); -+ rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); -+ break; -+ default: -+ break; -+ } -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_config_maccoexist_rfpage); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.h -new file mode 100644 -index 000000000000..f9b5d0d3a7e6 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.h -@@ -0,0 +1,87 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* Copyright(c) 2009-2012 Realtek Corporation.*/ -+ -+#ifndef __RTL92D_PHY_COMMON_H__ -+#define __RTL92D_PHY_COMMON_H__ -+ -+#define TARGET_CHNL_NUM_5G 221 -+#define TARGET_CHNL_NUM_2G 14 -+#define CV_CURVE_CNT 64 -+#define RT_CANNOT_IO(hw) false -+#define RX_INDEX_MAPPING_NUM 15 -+#define IQK_BB_REG_NUM 10 -+ -+#define IQK_DELAY_TIME 1 -+#define MAX_TOLERANCE 5 -+#define MAX_TOLERANCE_92D 3 -+ -+enum baseband_config_type { -+ BASEBAND_CONFIG_PHY_REG = 0, -+ BASEBAND_CONFIG_AGC_TAB = 1, -+}; -+ -+enum rf_content { -+ radioa_txt = 0, -+ radiob_txt = 1, -+ radioc_txt = 2, -+ radiod_txt = 3 -+}; -+ -+static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw, -+ unsigned long *flag) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ if (rtlpriv->rtlhal.interfaceindex == 1) -+ spin_lock_irqsave(&rtlpriv->locks.cck_and_rw_pagea_lock, *flag); -+} -+ -+static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw, -+ unsigned long *flag) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ if (rtlpriv->rtlhal.interfaceindex == 1) -+ spin_unlock_irqrestore(&rtlpriv->locks.cck_and_rw_pagea_lock, -+ *flag); -+} -+ -+u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, -+ u32 regaddr, u32 bitmask); -+void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, -+ u32 regaddr, u32 bitmask, u32 data); -+void rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw); -+void rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, -+ u32 regaddr, u32 bitmask, u32 data); -+void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw); -+void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel); -+void rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw, u8 rfpath, -+ u32 *pu4_regval); -+void rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath, -+ u32 *pu4_regval); -+u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl); -+void rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw, const u32 *adda_reg, -+ u32 *adda_backup, u32 regnum); -+void rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw, -+ const u32 *macreg, u32 *macbackup); -+void rtl92d_phy_path_adda_on(struct ieee80211_hw *hw, -+ const u32 *adda_reg, bool patha_on, bool is2t); -+void rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw, -+ const u32 *macreg, u32 *macbackup); -+void rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw, -+ const u32 *targetchnl, u32 *curvecount_val, -+ bool is5g, u32 *curveindex); -+void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw); -+bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype); -+void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw); -+void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw); -+u8 rtl92d_get_chnlgroup_fromarray(u8 chnl); -+u8 rtl92d_phy_get_chnlgroup_bypg(u8 chnlindex); -+void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw); -+/* Without these declarations sparse warns about context imbalance. */ -+void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw, -+ unsigned long *flag); -+void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw, -+ unsigned long *flag); -+ -+#endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h -similarity index 100% -rename from drivers/net/wireless/realtek/rtlwifi/rtl8192de/reg.h -rename to drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.c -new file mode 100644 -index 000000000000..8af166183688 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.c -@@ -0,0 +1,353 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright(c) 2009-2012 Realtek Corporation.*/ -+ -+#include "../wifi.h" -+#include "def.h" -+#include "reg.h" -+#include "phy_common.h" -+#include "rf_common.h" -+ -+void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u8 rfpath; -+ -+ switch (bandwidth) { -+ case HT_CHANNEL_WIDTH_20: -+ for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { -+ rtlphy->rfreg_chnlval[rfpath] = ((rtlphy->rfreg_chnlval -+ [rfpath] & 0xfffff3ff) | 0x0400); -+ rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | -+ BIT(11), 0x01); -+ -+ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, -+ "20M RF 0x18 = 0x%x\n", -+ rtlphy->rfreg_chnlval[rfpath]); -+ } -+ -+ break; -+ case HT_CHANNEL_WIDTH_20_40: -+ for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { -+ rtlphy->rfreg_chnlval[rfpath] = -+ ((rtlphy->rfreg_chnlval[rfpath] & 0xfffff3ff)); -+ rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | BIT(11), -+ 0x00); -+ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, -+ "40M RF 0x18 = 0x%x\n", -+ rtlphy->rfreg_chnlval[rfpath]); -+ } -+ break; -+ default: -+ pr_err("unknown bandwidth: %#X\n", bandwidth); -+ break; -+ } -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_rf6052_set_bandwidth); -+ -+void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw, -+ u8 *ppowerlevel) -+{ -+ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u32 tx_agc[2] = {0, 0}, tmpval; -+ bool turbo_scanoff = false; -+ u8 idx1, idx2; -+ u8 *ptr; -+ -+ if (rtlefuse->eeprom_regulatory != 0) -+ turbo_scanoff = true; -+ if (mac->act_scanning) { -+ tx_agc[RF90_PATH_A] = 0x3f3f3f3f; -+ tx_agc[RF90_PATH_B] = 0x3f3f3f3f; -+ if (turbo_scanoff) { -+ for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { -+ tx_agc[idx1] = ppowerlevel[idx1] | -+ (ppowerlevel[idx1] << 8) | -+ (ppowerlevel[idx1] << 16) | -+ (ppowerlevel[idx1] << 24); -+ } -+ } -+ } else { -+ for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { -+ tx_agc[idx1] = ppowerlevel[idx1] | -+ (ppowerlevel[idx1] << 8) | -+ (ppowerlevel[idx1] << 16) | -+ (ppowerlevel[idx1] << 24); -+ } -+ if (rtlefuse->eeprom_regulatory == 0) { -+ tmpval = (rtlphy->mcs_offset[0][6]) + -+ (rtlphy->mcs_offset[0][7] << 8); -+ tx_agc[RF90_PATH_A] += tmpval; -+ tmpval = (rtlphy->mcs_offset[0][14]) + -+ (rtlphy->mcs_offset[0][15] << 24); -+ tx_agc[RF90_PATH_B] += tmpval; -+ } -+ } -+ -+ for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { -+ ptr = (u8 *)(&tx_agc[idx1]); -+ for (idx2 = 0; idx2 < 4; idx2++) { -+ if (*ptr > RF6052_MAX_TX_PWR) -+ *ptr = RF6052_MAX_TX_PWR; -+ ptr++; -+ } -+ } -+ -+ tmpval = tx_agc[RF90_PATH_A] & 0xff; -+ rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval); -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -+ "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", -+ tmpval, RTXAGC_A_CCK1_MCS32); -+ tmpval = tx_agc[RF90_PATH_A] >> 8; -+ rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -+ "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", -+ tmpval, RTXAGC_B_CCK11_A_CCK2_11); -+ tmpval = tx_agc[RF90_PATH_B] >> 24; -+ rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval); -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -+ "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", -+ tmpval, RTXAGC_B_CCK11_A_CCK2_11); -+ tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff; -+ rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval); -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -+ "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", -+ tmpval, RTXAGC_B_CCK1_55_MCS32); -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_rf6052_set_cck_txpower); -+ -+static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw, -+ u8 *ppowerlevel, u8 channel, -+ u32 *ofdmbase, u32 *mcsbase) -+{ -+ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u32 powerbase0, powerbase1; -+ u8 legacy_pwrdiff, ht20_pwrdiff; -+ u8 i, powerlevel[2]; -+ -+ for (i = 0; i < 2; i++) { -+ powerlevel[i] = ppowerlevel[i]; -+ legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1]; -+ powerbase0 = powerlevel[i] + legacy_pwrdiff; -+ powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) | -+ (powerbase0 << 8) | powerbase0; -+ *(ofdmbase + i) = powerbase0; -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -+ " [OFDM power base index rf(%c) = 0x%x]\n", -+ i == 0 ? 'A' : 'B', *(ofdmbase + i)); -+ } -+ -+ for (i = 0; i < 2; i++) { -+ if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) { -+ ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1]; -+ powerlevel[i] += ht20_pwrdiff; -+ } -+ powerbase1 = powerlevel[i]; -+ powerbase1 = (powerbase1 << 24) | (powerbase1 << 16) | -+ (powerbase1 << 8) | powerbase1; -+ *(mcsbase + i) = powerbase1; -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -+ " [MCS power base index rf(%c) = 0x%x]\n", -+ i == 0 ? 'A' : 'B', *(mcsbase + i)); -+ } -+} -+ -+static void _rtl92d_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw, -+ u8 channel, u8 index, -+ u32 *powerbase0, -+ u32 *powerbase1, -+ u32 *p_outwriteval) -+{ -+ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u8 i, chnlgroup = 0, pwr_diff_limit[4]; -+ u32 writeval = 0, customer_limit, rf; -+ -+ for (rf = 0; rf < 2; rf++) { -+ switch (rtlefuse->eeprom_regulatory) { -+ case 0: -+ chnlgroup = 0; -+ writeval = rtlphy->mcs_offset -+ [chnlgroup][index + -+ (rf ? 8 : 0)] + ((index < 2) ? -+ powerbase0[rf] : -+ powerbase1[rf]); -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -+ "RTK better performance, writeval(%c) = 0x%x\n", -+ rf == 0 ? 'A' : 'B', writeval); -+ break; -+ case 1: -+ if (rtlphy->pwrgroup_cnt == 1) -+ chnlgroup = 0; -+ if (rtlphy->pwrgroup_cnt >= MAX_PG_GROUP) { -+ chnlgroup = rtl92d_phy_get_chnlgroup_bypg(channel - 1); -+ if (rtlphy->current_chan_bw == -+ HT_CHANNEL_WIDTH_20) -+ chnlgroup++; -+ else -+ chnlgroup += 4; -+ writeval = rtlphy->mcs_offset -+ [chnlgroup][index + -+ (rf ? 8 : 0)] + ((index < 2) ? -+ powerbase0[rf] : -+ powerbase1[rf]); -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -+ "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n", -+ rf == 0 ? 'A' : 'B', writeval); -+ } -+ break; -+ case 2: -+ writeval = ((index < 2) ? powerbase0[rf] : -+ powerbase1[rf]); -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -+ "Better regulatory, writeval(%c) = 0x%x\n", -+ rf == 0 ? 'A' : 'B', writeval); -+ break; -+ case 3: -+ chnlgroup = 0; -+ if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -+ "customer's limit, 40MHz rf(%c) = 0x%x\n", -+ rf == 0 ? 'A' : 'B', -+ rtlefuse->pwrgroup_ht40[rf] -+ [channel - 1]); -+ } else { -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -+ "customer's limit, 20MHz rf(%c) = 0x%x\n", -+ rf == 0 ? 'A' : 'B', -+ rtlefuse->pwrgroup_ht20[rf] -+ [channel - 1]); -+ } -+ for (i = 0; i < 4; i++) { -+ pwr_diff_limit[i] = (u8)((rtlphy->mcs_offset -+ [chnlgroup][index + (rf ? 8 : 0)] & -+ (0x7f << (i * 8))) >> (i * 8)); -+ if (rtlphy->current_chan_bw == -+ HT_CHANNEL_WIDTH_20_40) { -+ if (pwr_diff_limit[i] > -+ rtlefuse->pwrgroup_ht40[rf] -+ [channel - 1]) -+ pwr_diff_limit[i] = -+ rtlefuse->pwrgroup_ht40 -+ [rf][channel - 1]; -+ } else { -+ if (pwr_diff_limit[i] > -+ rtlefuse->pwrgroup_ht20[rf][channel - 1]) -+ pwr_diff_limit[i] = -+ rtlefuse->pwrgroup_ht20[rf] -+ [channel - 1]; -+ } -+ } -+ customer_limit = (pwr_diff_limit[3] << 24) | -+ (pwr_diff_limit[2] << 16) | -+ (pwr_diff_limit[1] << 8) | -+ (pwr_diff_limit[0]); -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -+ "Customer's limit rf(%c) = 0x%x\n", -+ rf == 0 ? 'A' : 'B', customer_limit); -+ writeval = customer_limit + ((index < 2) ? -+ powerbase0[rf] : powerbase1[rf]); -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -+ "Customer, writeval rf(%c)= 0x%x\n", -+ rf == 0 ? 'A' : 'B', writeval); -+ break; -+ default: -+ chnlgroup = 0; -+ writeval = rtlphy->mcs_offset[chnlgroup][index + -+ (rf ? 8 : 0)] + ((index < 2) ? -+ powerbase0[rf] : powerbase1[rf]); -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -+ "RTK better performance, writeval rf(%c) = 0x%x\n", -+ rf == 0 ? 'A' : 'B', writeval); -+ break; -+ } -+ *(p_outwriteval + rf) = writeval; -+ } -+} -+ -+static void _rtl92d_write_ofdm_power_reg(struct ieee80211_hw *hw, -+ u8 index, u32 *pvalue) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ static const u16 regoffset_a[6] = { -+ RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24, -+ RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04, -+ RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12 -+ }; -+ static const u16 regoffset_b[6] = { -+ RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24, -+ RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04, -+ RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12 -+ }; -+ u8 i, rf, pwr_val[4]; -+ u32 writeval; -+ u16 regoffset; -+ -+ for (rf = 0; rf < 2; rf++) { -+ writeval = pvalue[rf]; -+ for (i = 0; i < 4; i++) { -+ pwr_val[i] = (u8)((writeval & (0x7f << -+ (i * 8))) >> (i * 8)); -+ if (pwr_val[i] > RF6052_MAX_TX_PWR) -+ pwr_val[i] = RF6052_MAX_TX_PWR; -+ } -+ writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) | -+ (pwr_val[1] << 8) | pwr_val[0]; -+ if (rf == 0) -+ regoffset = regoffset_a[index]; -+ else -+ regoffset = regoffset_b[index]; -+ rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval); -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -+ "Set 0x%x = %08x\n", regoffset, writeval); -+ if (((get_rf_type(rtlphy) == RF_2T2R) && -+ (regoffset == RTXAGC_A_MCS15_MCS12 || -+ regoffset == RTXAGC_B_MCS15_MCS12)) || -+ ((get_rf_type(rtlphy) != RF_2T2R) && -+ (regoffset == RTXAGC_A_MCS07_MCS04 || -+ regoffset == RTXAGC_B_MCS07_MCS04))) { -+ writeval = pwr_val[3]; -+ if (regoffset == RTXAGC_A_MCS15_MCS12 || -+ regoffset == RTXAGC_A_MCS07_MCS04) -+ regoffset = 0xc90; -+ if (regoffset == RTXAGC_B_MCS15_MCS12 || -+ regoffset == RTXAGC_B_MCS07_MCS04) -+ regoffset = 0xc98; -+ for (i = 0; i < 3; i++) { -+ if (i != 2) -+ writeval = (writeval > 8) ? -+ (writeval - 8) : 0; -+ else -+ writeval = (writeval > 6) ? -+ (writeval - 6) : 0; -+ rtl_write_byte(rtlpriv, (u32)(regoffset + i), -+ (u8)writeval); -+ } -+ } -+ } -+} -+ -+void rtl92d_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw, -+ u8 *ppowerlevel, u8 channel) -+{ -+ u32 writeval[2], powerbase0[2], powerbase1[2]; -+ u8 index; -+ -+ _rtl92d_phy_get_power_base(hw, ppowerlevel, channel, -+ &powerbase0[0], &powerbase1[0]); -+ for (index = 0; index < 6; index++) { -+ _rtl92d_get_txpower_writeval_by_regulatory(hw, channel, index, -+ &powerbase0[0], -+ &powerbase1[0], -+ &writeval[0]); -+ _rtl92d_write_ofdm_power_reg(hw, index, &writeval[0]); -+ } -+} -+EXPORT_SYMBOL_GPL(rtl92d_phy_rf6052_set_ofdm_txpower); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.h -new file mode 100644 -index 000000000000..c243ec08369b ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.h -@@ -0,0 +1,13 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* Copyright(c) 2009-2012 Realtek Corporation.*/ -+ -+#ifndef __RTL92D_RF_COMMON_H__ -+#define __RTL92D_RF_COMMON_H__ -+ -+void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth); -+void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw, -+ u8 *ppowerlevel); -+void rtl92d_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw, -+ u8 *ppowerlevel, u8 channel); -+ -+#endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c -new file mode 100644 -index 000000000000..5b8f404373ea ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c -@@ -0,0 +1,515 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright(c) 2009-2012 Realtek Corporation.*/ -+ -+#include "../wifi.h" -+#include "../base.h" -+#include "../stats.h" -+#include "def.h" -+#include "trx_common.h" -+ -+static long _rtl92de_translate_todbm(struct ieee80211_hw *hw, -+ u8 signal_strength_index) -+{ -+ long signal_power; -+ -+ signal_power = (long)((signal_strength_index + 1) >> 1); -+ signal_power -= 95; -+ return signal_power; -+} -+ -+static void _rtl92de_query_rxphystatus(struct ieee80211_hw *hw, -+ struct rtl_stats *pstats, -+ __le32 *pdesc, -+ struct rx_fwinfo_92d *p_drvinfo, -+ bool packet_match_bssid, -+ bool packet_toself, -+ bool packet_beacon) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); -+ struct phy_sts_cck_8192d *cck_buf; -+ s8 rx_pwr_all, rx_pwr[4]; -+ u8 rf_rx_num = 0, evm, pwdb_all; -+ u8 i, max_spatial_stream; -+ u32 rssi, total_rssi = 0; -+ bool is_cck_rate; -+ u8 rxmcs; -+ -+ rxmcs = get_rx_desc_rxmcs(pdesc); -+ is_cck_rate = rxmcs <= DESC_RATE11M; -+ pstats->packet_matchbssid = packet_match_bssid; -+ pstats->packet_toself = packet_toself; -+ pstats->packet_beacon = packet_beacon; -+ pstats->is_cck = is_cck_rate; -+ pstats->rx_mimo_sig_qual[0] = -1; -+ pstats->rx_mimo_sig_qual[1] = -1; -+ -+ if (is_cck_rate) { -+ u8 report, cck_highpwr; -+ -+ cck_buf = (struct phy_sts_cck_8192d *)p_drvinfo; -+ if (ppsc->rfpwr_state == ERFON) -+ cck_highpwr = rtlphy->cck_high_power; -+ else -+ cck_highpwr = false; -+ if (!cck_highpwr) { -+ u8 cck_agc_rpt = cck_buf->cck_agc_rpt; -+ -+ report = cck_buf->cck_agc_rpt & 0xc0; -+ report = report >> 6; -+ switch (report) { -+ case 0x3: -+ rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); -+ break; -+ case 0x2: -+ rx_pwr_all = -26 - (cck_agc_rpt & 0x3e); -+ break; -+ case 0x1: -+ rx_pwr_all = -12 - (cck_agc_rpt & 0x3e); -+ break; -+ case 0x0: -+ rx_pwr_all = 16 - (cck_agc_rpt & 0x3e); -+ break; -+ } -+ } else { -+ u8 cck_agc_rpt = cck_buf->cck_agc_rpt; -+ -+ report = p_drvinfo->cfosho[0] & 0x60; -+ report = report >> 5; -+ switch (report) { -+ case 0x3: -+ rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1); -+ break; -+ case 0x2: -+ rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1); -+ break; -+ case 0x1: -+ rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1); -+ break; -+ case 0x0: -+ rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1); -+ break; -+ } -+ } -+ pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all); -+ /* CCK gain is smaller than OFDM/MCS gain, */ -+ /* so we add gain diff by experiences, the val is 6 */ -+ pwdb_all += 6; -+ if (pwdb_all > 100) -+ pwdb_all = 100; -+ /* modify the offset to make the same gain index with OFDM. */ -+ if (pwdb_all > 34 && pwdb_all <= 42) -+ pwdb_all -= 2; -+ else if (pwdb_all > 26 && pwdb_all <= 34) -+ pwdb_all -= 6; -+ else if (pwdb_all > 14 && pwdb_all <= 26) -+ pwdb_all -= 8; -+ else if (pwdb_all > 4 && pwdb_all <= 14) -+ pwdb_all -= 4; -+ pstats->rx_pwdb_all = pwdb_all; -+ pstats->recvsignalpower = rx_pwr_all; -+ if (packet_match_bssid) { -+ u8 sq; -+ -+ if (pstats->rx_pwdb_all > 40) { -+ sq = 100; -+ } else { -+ sq = cck_buf->sq_rpt; -+ if (sq > 64) -+ sq = 0; -+ else if (sq < 20) -+ sq = 100; -+ else -+ sq = ((64 - sq) * 100) / 44; -+ } -+ pstats->signalquality = sq; -+ pstats->rx_mimo_sig_qual[0] = sq; -+ pstats->rx_mimo_sig_qual[1] = -1; -+ } -+ } else { -+ rtlpriv->dm.rfpath_rxenable[0] = true; -+ rtlpriv->dm.rfpath_rxenable[1] = true; -+ for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) { -+ if (rtlpriv->dm.rfpath_rxenable[i]) -+ rf_rx_num++; -+ rx_pwr[i] = ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) -+ - 110; -+ rssi = rtl_query_rxpwrpercentage(rx_pwr[i]); -+ total_rssi += rssi; -+ rtlpriv->stats.rx_snr_db[i] = -+ (long)(p_drvinfo->rxsnr[i] / 2); -+ if (packet_match_bssid) -+ pstats->rx_mimo_signalstrength[i] = (u8)rssi; -+ } -+ rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 106; -+ pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all); -+ pstats->rx_pwdb_all = pwdb_all; -+ pstats->rxpower = rx_pwr_all; -+ pstats->recvsignalpower = rx_pwr_all; -+ if (get_rx_desc_rxht(pdesc) && rxmcs >= DESC_RATEMCS8 && -+ rxmcs <= DESC_RATEMCS15) -+ max_spatial_stream = 2; -+ else -+ max_spatial_stream = 1; -+ for (i = 0; i < max_spatial_stream; i++) { -+ evm = rtl_evm_db_to_percentage(p_drvinfo->rxevm[i]); -+ if (packet_match_bssid) { -+ if (i == 0) -+ pstats->signalquality = -+ (u8)(evm & 0xff); -+ pstats->rx_mimo_sig_qual[i] = -+ (u8)(evm & 0xff); -+ } -+ } -+ } -+ if (is_cck_rate) -+ pstats->signalstrength = (u8)(rtl_signal_scale_mapping(hw, -+ pwdb_all)); -+ else if (rf_rx_num != 0) -+ pstats->signalstrength = (u8)(rtl_signal_scale_mapping(hw, -+ total_rssi /= rf_rx_num)); -+} -+ -+static void rtl92d_loop_over_paths(struct ieee80211_hw *hw, -+ struct rtl_stats *pstats) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u8 rfpath; -+ -+ for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; -+ rfpath++) { -+ if (rtlpriv->stats.rx_rssi_percentage[rfpath] == 0) { -+ rtlpriv->stats.rx_rssi_percentage[rfpath] = -+ pstats->rx_mimo_signalstrength[rfpath]; -+ } -+ if (pstats->rx_mimo_signalstrength[rfpath] > -+ rtlpriv->stats.rx_rssi_percentage[rfpath]) { -+ rtlpriv->stats.rx_rssi_percentage[rfpath] = -+ ((rtlpriv->stats.rx_rssi_percentage[rfpath] * -+ (RX_SMOOTH_FACTOR - 1)) + -+ (pstats->rx_mimo_signalstrength[rfpath])) / -+ (RX_SMOOTH_FACTOR); -+ rtlpriv->stats.rx_rssi_percentage[rfpath] = -+ rtlpriv->stats.rx_rssi_percentage[rfpath] + 1; -+ } else { -+ rtlpriv->stats.rx_rssi_percentage[rfpath] = -+ ((rtlpriv->stats.rx_rssi_percentage[rfpath] * -+ (RX_SMOOTH_FACTOR - 1)) + -+ (pstats->rx_mimo_signalstrength[rfpath])) / -+ (RX_SMOOTH_FACTOR); -+ } -+ } -+} -+ -+static void _rtl92de_process_ui_rssi(struct ieee80211_hw *hw, -+ struct rtl_stats *pstats) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rt_smooth_data *ui_rssi; -+ u32 last_rssi, tmpval; -+ -+ if (!pstats->packet_toself && !pstats->packet_beacon) -+ return; -+ -+ ui_rssi = &rtlpriv->stats.ui_rssi; -+ -+ rtlpriv->stats.rssi_calculate_cnt++; -+ if (ui_rssi->total_num++ >= PHY_RSSI_SLID_WIN_MAX) { -+ ui_rssi->total_num = PHY_RSSI_SLID_WIN_MAX; -+ last_rssi = ui_rssi->elements[ui_rssi->index]; -+ ui_rssi->total_val -= last_rssi; -+ } -+ ui_rssi->total_val += pstats->signalstrength; -+ ui_rssi->elements[ui_rssi->index++] = pstats->signalstrength; -+ if (ui_rssi->index >= PHY_RSSI_SLID_WIN_MAX) -+ ui_rssi->index = 0; -+ tmpval = ui_rssi->total_val / ui_rssi->total_num; -+ rtlpriv->stats.signal_strength = _rtl92de_translate_todbm(hw, (u8)tmpval); -+ pstats->rssi = rtlpriv->stats.signal_strength; -+ -+ if (!pstats->is_cck && pstats->packet_toself) -+ rtl92d_loop_over_paths(hw, pstats); -+} -+ -+static void _rtl92de_update_rxsignalstatistics(struct ieee80211_hw *hw, -+ struct rtl_stats *pstats) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ int weighting = 0; -+ -+ if (rtlpriv->stats.recv_signal_power == 0) -+ rtlpriv->stats.recv_signal_power = pstats->recvsignalpower; -+ if (pstats->recvsignalpower > rtlpriv->stats.recv_signal_power) -+ weighting = 5; -+ else if (pstats->recvsignalpower < rtlpriv->stats.recv_signal_power) -+ weighting = (-5); -+ rtlpriv->stats.recv_signal_power = (rtlpriv->stats.recv_signal_power * -+ 5 + pstats->recvsignalpower + weighting) / 6; -+} -+ -+static void _rtl92de_process_pwdb(struct ieee80211_hw *hw, -+ struct rtl_stats *pstats) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -+ long undec_sm_pwdb; -+ -+ if (mac->opmode == NL80211_IFTYPE_ADHOC || -+ mac->opmode == NL80211_IFTYPE_AP) -+ return; -+ -+ undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb; -+ -+ if (pstats->packet_toself || pstats->packet_beacon) { -+ if (undec_sm_pwdb < 0) -+ undec_sm_pwdb = pstats->rx_pwdb_all; -+ if (pstats->rx_pwdb_all > (u32)undec_sm_pwdb) { -+ undec_sm_pwdb = (((undec_sm_pwdb) * -+ (RX_SMOOTH_FACTOR - 1)) + -+ (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); -+ undec_sm_pwdb = undec_sm_pwdb + 1; -+ } else { -+ undec_sm_pwdb = (((undec_sm_pwdb) * -+ (RX_SMOOTH_FACTOR - 1)) + -+ (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); -+ } -+ rtlpriv->dm.undec_sm_pwdb = undec_sm_pwdb; -+ _rtl92de_update_rxsignalstatistics(hw, pstats); -+ } -+} -+ -+static void rtl92d_loop_over_streams(struct ieee80211_hw *hw, -+ struct rtl_stats *pstats) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ int stream; -+ -+ for (stream = 0; stream < 2; stream++) { -+ if (pstats->rx_mimo_sig_qual[stream] != -1) { -+ if (rtlpriv->stats.rx_evm_percentage[stream] == 0) { -+ rtlpriv->stats.rx_evm_percentage[stream] = -+ pstats->rx_mimo_sig_qual[stream]; -+ } -+ rtlpriv->stats.rx_evm_percentage[stream] = -+ ((rtlpriv->stats.rx_evm_percentage[stream] -+ * (RX_SMOOTH_FACTOR - 1)) + -+ (pstats->rx_mimo_sig_qual[stream] * 1)) / -+ (RX_SMOOTH_FACTOR); -+ } -+ } -+} -+ -+static void _rtl92de_process_ui_link_quality(struct ieee80211_hw *hw, -+ struct rtl_stats *pstats) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rt_smooth_data *ui_link_quality; -+ u32 last_evm, tmpval; -+ -+ if (pstats->signalquality == 0) -+ return; -+ if (!pstats->packet_toself && !pstats->packet_beacon) -+ return; -+ -+ ui_link_quality = &rtlpriv->stats.ui_link_quality; -+ -+ if (ui_link_quality->total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) { -+ ui_link_quality->total_num = PHY_LINKQUALITY_SLID_WIN_MAX; -+ last_evm = ui_link_quality->elements[ui_link_quality->index]; -+ ui_link_quality->total_val -= last_evm; -+ } -+ ui_link_quality->total_val += pstats->signalquality; -+ ui_link_quality->elements[ui_link_quality->index++] = pstats->signalquality; -+ if (ui_link_quality->index >= PHY_LINKQUALITY_SLID_WIN_MAX) -+ ui_link_quality->index = 0; -+ tmpval = ui_link_quality->total_val / ui_link_quality->total_num; -+ rtlpriv->stats.signal_quality = tmpval; -+ rtlpriv->stats.last_sigstrength_inpercent = tmpval; -+ rtl92d_loop_over_streams(hw, pstats); -+} -+ -+static void _rtl92de_process_phyinfo(struct ieee80211_hw *hw, -+ u8 *buffer, -+ struct rtl_stats *pcurrent_stats) -+{ -+ if (!pcurrent_stats->packet_matchbssid && -+ !pcurrent_stats->packet_beacon) -+ return; -+ -+ _rtl92de_process_ui_rssi(hw, pcurrent_stats); -+ _rtl92de_process_pwdb(hw, pcurrent_stats); -+ _rtl92de_process_ui_link_quality(hw, pcurrent_stats); -+} -+ -+static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw, -+ struct sk_buff *skb, -+ struct rtl_stats *pstats, -+ __le32 *pdesc, -+ struct rx_fwinfo_92d *p_drvinfo) -+{ -+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -+ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -+ struct ieee80211_hdr *hdr; -+ u8 *tmp_buf; -+ u8 *praddr; -+ u16 type, cfc; -+ __le16 fc; -+ bool packet_matchbssid, packet_toself, packet_beacon = false; -+ -+ tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift; -+ hdr = (struct ieee80211_hdr *)tmp_buf; -+ fc = hdr->frame_control; -+ cfc = le16_to_cpu(fc); -+ type = WLAN_FC_GET_TYPE(fc); -+ praddr = hdr->addr1; -+ packet_matchbssid = ((type != IEEE80211_FTYPE_CTL) && -+ ether_addr_equal(mac->bssid, -+ (cfc & IEEE80211_FCTL_TODS) ? hdr->addr1 : -+ (cfc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 : -+ hdr->addr3) && -+ (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv)); -+ packet_toself = packet_matchbssid && -+ ether_addr_equal(praddr, rtlefuse->dev_addr); -+ if (ieee80211_is_beacon(fc)) -+ packet_beacon = true; -+ _rtl92de_query_rxphystatus(hw, pstats, pdesc, p_drvinfo, -+ packet_matchbssid, packet_toself, -+ packet_beacon); -+ _rtl92de_process_phyinfo(hw, tmp_buf, pstats); -+} -+ -+bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, -+ struct ieee80211_rx_status *rx_status, -+ u8 *pdesc8, struct sk_buff *skb) -+{ -+ __le32 *pdesc = (__le32 *)pdesc8; -+ struct rx_fwinfo_92d *p_drvinfo; -+ u32 phystatus = get_rx_desc_physt(pdesc); -+ -+ stats->length = (u16)get_rx_desc_pkt_len(pdesc); -+ stats->rx_drvinfo_size = (u8)get_rx_desc_drv_info_size(pdesc) * -+ RX_DRV_INFO_SIZE_UNIT; -+ stats->rx_bufshift = (u8)(get_rx_desc_shift(pdesc) & 0x03); -+ stats->icv = (u16)get_rx_desc_icv(pdesc); -+ stats->crc = (u16)get_rx_desc_crc32(pdesc); -+ stats->hwerror = (stats->crc | stats->icv); -+ stats->decrypted = !get_rx_desc_swdec(pdesc) && -+ get_rx_desc_enc_type(pdesc) != RX_DESC_ENC_NONE; -+ stats->rate = (u8)get_rx_desc_rxmcs(pdesc); -+ stats->shortpreamble = (u16)get_rx_desc_splcp(pdesc); -+ stats->isampdu = (bool)(get_rx_desc_paggr(pdesc) == 1); -+ stats->isfirst_ampdu = (bool)((get_rx_desc_paggr(pdesc) == 1) && -+ (get_rx_desc_faggr(pdesc) == 1)); -+ stats->timestamp_low = get_rx_desc_tsfl(pdesc); -+ stats->rx_is40mhzpacket = (bool)get_rx_desc_bw(pdesc); -+ stats->is_ht = (bool)get_rx_desc_rxht(pdesc); -+ rx_status->freq = hw->conf.chandef.chan->center_freq; -+ rx_status->band = hw->conf.chandef.chan->band; -+ if (get_rx_desc_crc32(pdesc)) -+ rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; -+ if (get_rx_desc_bw(pdesc)) -+ rx_status->bw = RATE_INFO_BW_40; -+ if (get_rx_desc_rxht(pdesc)) -+ rx_status->encoding = RX_ENC_HT; -+ rx_status->flag |= RX_FLAG_MACTIME_START; -+ if (stats->decrypted) -+ rx_status->flag |= RX_FLAG_DECRYPTED; -+ rx_status->rate_idx = rtlwifi_rate_mapping(hw, stats->is_ht, -+ false, stats->rate); -+ rx_status->mactime = get_rx_desc_tsfl(pdesc); -+ if (phystatus) { -+ p_drvinfo = (struct rx_fwinfo_92d *)(skb->data + -+ stats->rx_bufshift); -+ _rtl92de_translate_rx_signal_stuff(hw, skb, stats, pdesc, -+ p_drvinfo); -+ } -+ /*rx_status->qual = stats->signal; */ -+ rx_status->signal = stats->recvsignalpower + 10; -+ return true; -+} -+EXPORT_SYMBOL_GPL(rtl92de_rx_query_desc); -+ -+void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc8, bool istx, -+ u8 desc_name, u8 *val) -+{ -+ __le32 *pdesc = (__le32 *)pdesc8; -+ -+ if (istx) { -+ switch (desc_name) { -+ case HW_DESC_OWN: -+ wmb(); -+ set_tx_desc_own(pdesc, 1); -+ break; -+ case HW_DESC_TX_NEXTDESC_ADDR: -+ set_tx_desc_next_desc_address(pdesc, *(u32 *)val); -+ break; -+ default: -+ WARN_ONCE(true, "rtl8192de: ERR txdesc :%d not processed\n", -+ desc_name); -+ break; -+ } -+ } else { -+ switch (desc_name) { -+ case HW_DESC_RXOWN: -+ wmb(); -+ set_rx_desc_own(pdesc, 1); -+ break; -+ case HW_DESC_RXBUFF_ADDR: -+ set_rx_desc_buff_addr(pdesc, *(u32 *)val); -+ break; -+ case HW_DESC_RXPKT_LEN: -+ set_rx_desc_pkt_len(pdesc, *(u32 *)val); -+ break; -+ case HW_DESC_RXERO: -+ set_rx_desc_eor(pdesc, 1); -+ break; -+ default: -+ WARN_ONCE(true, "rtl8192de: ERR rxdesc :%d not processed\n", -+ desc_name); -+ break; -+ } -+ } -+} -+EXPORT_SYMBOL_GPL(rtl92de_set_desc); -+ -+u64 rtl92de_get_desc(struct ieee80211_hw *hw, -+ u8 *p_desc8, bool istx, u8 desc_name) -+{ -+ __le32 *p_desc = (__le32 *)p_desc8; -+ u32 ret = 0; -+ -+ if (istx) { -+ switch (desc_name) { -+ case HW_DESC_OWN: -+ ret = get_tx_desc_own(p_desc); -+ break; -+ case HW_DESC_TXBUFF_ADDR: -+ ret = get_tx_desc_tx_buffer_address(p_desc); -+ break; -+ default: -+ WARN_ONCE(true, "rtl8192de: ERR txdesc :%d not processed\n", -+ desc_name); -+ break; -+ } -+ } else { -+ switch (desc_name) { -+ case HW_DESC_OWN: -+ ret = get_rx_desc_own(p_desc); -+ break; -+ case HW_DESC_RXPKT_LEN: -+ ret = get_rx_desc_pkt_len(p_desc); -+ break; -+ case HW_DESC_RXBUFF_ADDR: -+ ret = get_rx_desc_buff_addr(p_desc); -+ break; -+ default: -+ WARN_ONCE(true, "rtl8192de: ERR rxdesc :%d not processed\n", -+ desc_name); -+ break; -+ } -+ } -+ return ret; -+} -+EXPORT_SYMBOL_GPL(rtl92de_get_desc); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h -new file mode 100644 -index 000000000000..87d956d771eb ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h -@@ -0,0 +1,405 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* Copyright(c) 2009-2012 Realtek Corporation.*/ -+ -+#ifndef __RTL92D_TRX_COMMON_H__ -+#define __RTL92D_TRX_COMMON_H__ -+ -+#define RX_DRV_INFO_SIZE_UNIT 8 -+ -+enum rtl92d_rx_desc_enc { -+ RX_DESC_ENC_NONE = 0, -+ RX_DESC_ENC_WEP40 = 1, -+ RX_DESC_ENC_TKIP_WO_MIC = 2, -+ RX_DESC_ENC_TKIP_MIC = 3, -+ RX_DESC_ENC_AES = 4, -+ RX_DESC_ENC_WEP104 = 5, -+}; -+ -+/* macros to read/write various fields in RX or TX descriptors */ -+ -+static inline void set_tx_desc_pkt_size(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits(__pdesc, __val, GENMASK(15, 0)); -+} -+ -+static inline void set_tx_desc_offset(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits(__pdesc, __val, GENMASK(23, 16)); -+} -+ -+static inline void set_tx_desc_htc(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits(__pdesc, __val, BIT(25)); -+} -+ -+static inline void set_tx_desc_last_seg(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits(__pdesc, __val, BIT(26)); -+} -+ -+static inline void set_tx_desc_first_seg(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits(__pdesc, __val, BIT(27)); -+} -+ -+static inline void set_tx_desc_linip(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits(__pdesc, __val, BIT(28)); -+} -+ -+static inline void set_tx_desc_own(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits(__pdesc, __val, BIT(31)); -+} -+ -+static inline u32 get_tx_desc_own(__le32 *__pdesc) -+{ -+ return le32_get_bits(*__pdesc, BIT(31)); -+} -+ -+static inline void set_tx_desc_macid(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0)); -+} -+ -+static inline void set_tx_desc_agg_enable(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 1), __val, BIT(5)); -+} -+ -+static inline void set_tx_desc_rdg_enable(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 1), __val, BIT(7)); -+} -+ -+static inline void set_tx_desc_queue_sel(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8)); -+} -+ -+static inline void set_tx_desc_rate_id(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 1), __val, GENMASK(19, 16)); -+} -+ -+static inline void set_tx_desc_sec_type(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22)); -+} -+ -+static inline void set_tx_desc_pkt_offset(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 1), __val, GENMASK(30, 26)); -+} -+ -+static inline void set_tx_desc_more_frag(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 2), __val, BIT(17)); -+} -+ -+static inline void set_tx_desc_ampdu_density(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20)); -+} -+ -+static inline void set_tx_desc_seq(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16)); -+} -+ -+static inline void set_tx_desc_pkt_id(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 3), __val, GENMASK(31, 28)); -+} -+ -+static inline void set_tx_desc_rts_rate(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 4), __val, GENMASK(4, 0)); -+} -+ -+static inline void set_tx_desc_qos(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 4), __val, BIT(6)); -+} -+ -+static inline void set_tx_desc_hwseq_en(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 4), __val, BIT(7)); -+} -+ -+static inline void set_tx_desc_use_rate(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 4), __val, BIT(8)); -+} -+ -+static inline void set_tx_desc_disable_fb(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 4), __val, BIT(10)); -+} -+ -+static inline void set_tx_desc_cts2self(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 4), __val, BIT(11)); -+} -+ -+static inline void set_tx_desc_rts_enable(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 4), __val, BIT(12)); -+} -+ -+static inline void set_tx_desc_hw_rts_enable(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 4), __val, BIT(13)); -+} -+ -+static inline void set_tx_desc_tx_sub_carrier(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 4), __val, GENMASK(21, 20)); -+} -+ -+static inline void set_tx_desc_data_bw(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 4), __val, BIT(25)); -+} -+ -+static inline void set_tx_desc_rts_short(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 4), __val, BIT(26)); -+} -+ -+static inline void set_tx_desc_rts_bw(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 4), __val, BIT(27)); -+} -+ -+static inline void set_tx_desc_rts_sc(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 4), __val, GENMASK(29, 28)); -+} -+ -+static inline void set_tx_desc_rts_stbc(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 4), __val, GENMASK(31, 30)); -+} -+ -+static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0)); -+} -+ -+static inline void set_tx_desc_data_shortgi(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 5), __val, BIT(6)); -+} -+ -+static inline void set_tx_desc_data_rate_fb_limit(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 5), __val, GENMASK(12, 8)); -+} -+ -+static inline void set_tx_desc_rts_rate_fb_limit(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13)); -+} -+ -+static inline void set_tx_desc_max_agg_num(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 6), __val, GENMASK(15, 11)); -+} -+ -+static inline void set_tx_desc_tx_buffer_size(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0)); -+} -+ -+static inline void set_tx_desc_tx_buffer_address(__le32 *__pdesc, u32 __val) -+{ -+ *(__pdesc + 8) = cpu_to_le32(__val); -+} -+ -+static inline u32 get_tx_desc_tx_buffer_address(__le32 *__pdesc) -+{ -+ return le32_to_cpu(*(__pdesc + 8)); -+} -+ -+static inline void set_tx_desc_next_desc_address(__le32 *__pdesc, u32 __val) -+{ -+ *(__pdesc + 10) = cpu_to_le32(__val); -+} -+ -+static inline u32 get_rx_desc_pkt_len(__le32 *__pdesc) -+{ -+ return le32_get_bits(*__pdesc, GENMASK(13, 0)); -+} -+ -+static inline u32 get_rx_desc_crc32(__le32 *__pdesc) -+{ -+ return le32_get_bits(*__pdesc, BIT(14)); -+} -+ -+static inline u32 get_rx_desc_icv(__le32 *__pdesc) -+{ -+ return le32_get_bits(*__pdesc, BIT(15)); -+} -+ -+static inline u32 get_rx_desc_drv_info_size(__le32 *__pdesc) -+{ -+ return le32_get_bits(*__pdesc, GENMASK(19, 16)); -+} -+ -+static inline u32 get_rx_desc_enc_type(__le32 *__pdesc) -+{ -+ return le32_get_bits(*__pdesc, GENMASK(22, 20)); -+} -+ -+static inline u32 get_rx_desc_shift(__le32 *__pdesc) -+{ -+ return le32_get_bits(*__pdesc, GENMASK(25, 24)); -+} -+ -+static inline u32 get_rx_desc_physt(__le32 *__pdesc) -+{ -+ return le32_get_bits(*__pdesc, BIT(26)); -+} -+ -+static inline u32 get_rx_desc_swdec(__le32 *__pdesc) -+{ -+ return le32_get_bits(*__pdesc, BIT(27)); -+} -+ -+static inline u32 get_rx_desc_own(__le32 *__pdesc) -+{ -+ return le32_get_bits(*__pdesc, BIT(31)); -+} -+ -+static inline void set_rx_desc_pkt_len(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits(__pdesc, __val, GENMASK(13, 0)); -+} -+ -+static inline void set_rx_desc_eor(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits(__pdesc, __val, BIT(30)); -+} -+ -+static inline void set_rx_desc_own(__le32 *__pdesc, u32 __val) -+{ -+ le32p_replace_bits(__pdesc, __val, BIT(31)); -+} -+ -+static inline u32 get_rx_desc_paggr(__le32 *__pdesc) -+{ -+ return le32_get_bits(*(__pdesc + 1), BIT(14)); -+} -+ -+static inline u32 get_rx_desc_faggr(__le32 *__pdesc) -+{ -+ return le32_get_bits(*(__pdesc + 1), BIT(15)); -+} -+ -+static inline u32 get_rx_desc_rxmcs(__le32 *__pdesc) -+{ -+ return le32_get_bits(*(__pdesc + 3), GENMASK(5, 0)); -+} -+ -+static inline u32 get_rx_desc_rxht(__le32 *__pdesc) -+{ -+ return le32_get_bits(*(__pdesc + 3), BIT(6)); -+} -+ -+static inline u32 get_rx_desc_splcp(__le32 *__pdesc) -+{ -+ return le32_get_bits(*(__pdesc + 3), BIT(8)); -+} -+ -+static inline u32 get_rx_desc_bw(__le32 *__pdesc) -+{ -+ return le32_get_bits(*(__pdesc + 3), BIT(9)); -+} -+ -+static inline u32 get_rx_desc_tsfl(__le32 *__pdesc) -+{ -+ return le32_to_cpu(*(__pdesc + 5)); -+} -+ -+static inline u32 get_rx_desc_buff_addr(__le32 *__pdesc) -+{ -+ return le32_to_cpu(*(__pdesc + 6)); -+} -+ -+static inline void set_rx_desc_buff_addr(__le32 *__pdesc, u32 __val) -+{ -+ *(__pdesc + 6) = cpu_to_le32(__val); -+} -+ -+/* For 92D early mode */ -+static inline void set_earlymode_pktnum(__le32 *__paddr, u32 __value) -+{ -+ le32p_replace_bits(__paddr, __value, GENMASK(2, 0)); -+} -+ -+static inline void set_earlymode_len0(__le32 *__paddr, u32 __value) -+{ -+ le32p_replace_bits(__paddr, __value, GENMASK(15, 4)); -+} -+ -+static inline void set_earlymode_len1(__le32 *__paddr, u32 __value) -+{ -+ le32p_replace_bits(__paddr, __value, GENMASK(27, 16)); -+} -+ -+static inline void set_earlymode_len2_1(__le32 *__paddr, u32 __value) -+{ -+ le32p_replace_bits(__paddr, __value, GENMASK(31, 28)); -+} -+ -+static inline void set_earlymode_len2_2(__le32 *__paddr, u32 __value) -+{ -+ le32p_replace_bits((__paddr + 1), __value, GENMASK(7, 0)); -+} -+ -+static inline void set_earlymode_len3(__le32 *__paddr, u32 __value) -+{ -+ le32p_replace_bits((__paddr + 1), __value, GENMASK(19, 8)); -+} -+ -+static inline void set_earlymode_len4(__le32 *__paddr, u32 __value) -+{ -+ le32p_replace_bits((__paddr + 1), __value, GENMASK(31, 20)); -+} -+ -+struct rx_fwinfo_92d { -+ u8 gain_trsw[4]; -+ u8 pwdb_all; -+ u8 cfosho[4]; -+ u8 cfotail[4]; -+ s8 rxevm[2]; -+ s8 rxsnr[4]; -+ u8 pdsnr[2]; -+ u8 csi_current[2]; -+ u8 csi_target[2]; -+ u8 sigevm; -+ u8 max_ex_pwr; -+#ifdef __LITTLE_ENDIAN -+ u8 ex_intf_flag:1; -+ u8 sgi_en:1; -+ u8 rxsc:2; -+ u8 reserve:4; -+#else -+ u8 reserve:4; -+ u8 rxsc:2; -+ u8 sgi_en:1; -+ u8 ex_intf_flag:1; -+#endif -+} __packed; -+ -+bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, -+ struct rtl_stats *stats, -+ struct ieee80211_rx_status *rx_status, -+ u8 *pdesc, struct sk_buff *skb); -+void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, -+ u8 desc_name, u8 *val); -+u64 rtl92de_get_desc(struct ieee80211_hw *hw, -+ u8 *p_desc, bool istx, u8 desc_name); -+ -+#endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c -index cf4aca83bd05..c6a2e8b22fa0 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c -@@ -4,455 +4,16 @@ - #include "../wifi.h" - #include "../base.h" - #include "../core.h" --#include "reg.h" --#include "def.h" -+#include "../rtl8192d/reg.h" -+#include "../rtl8192d/def.h" -+#include "../rtl8192d/dm_common.h" -+#include "../rtl8192d/phy_common.h" -+#include "../rtl8192d/fw_common.h" - #include "phy.h" - #include "dm.h" --#include "fw.h" - - #define UNDEC_SM_PWDB entry_min_undec_sm_pwdb - --static const u32 ofdmswing_table[OFDM_TABLE_SIZE_92D] = { -- 0x7f8001fe, /* 0, +6.0dB */ -- 0x788001e2, /* 1, +5.5dB */ -- 0x71c001c7, /* 2, +5.0dB */ -- 0x6b8001ae, /* 3, +4.5dB */ -- 0x65400195, /* 4, +4.0dB */ -- 0x5fc0017f, /* 5, +3.5dB */ -- 0x5a400169, /* 6, +3.0dB */ -- 0x55400155, /* 7, +2.5dB */ -- 0x50800142, /* 8, +2.0dB */ -- 0x4c000130, /* 9, +1.5dB */ -- 0x47c0011f, /* 10, +1.0dB */ -- 0x43c0010f, /* 11, +0.5dB */ -- 0x40000100, /* 12, +0dB */ -- 0x3c8000f2, /* 13, -0.5dB */ -- 0x390000e4, /* 14, -1.0dB */ -- 0x35c000d7, /* 15, -1.5dB */ -- 0x32c000cb, /* 16, -2.0dB */ -- 0x300000c0, /* 17, -2.5dB */ -- 0x2d4000b5, /* 18, -3.0dB */ -- 0x2ac000ab, /* 19, -3.5dB */ -- 0x288000a2, /* 20, -4.0dB */ -- 0x26000098, /* 21, -4.5dB */ -- 0x24000090, /* 22, -5.0dB */ -- 0x22000088, /* 23, -5.5dB */ -- 0x20000080, /* 24, -6.0dB */ -- 0x1e400079, /* 25, -6.5dB */ -- 0x1c800072, /* 26, -7.0dB */ -- 0x1b00006c, /* 27. -7.5dB */ -- 0x19800066, /* 28, -8.0dB */ -- 0x18000060, /* 29, -8.5dB */ -- 0x16c0005b, /* 30, -9.0dB */ -- 0x15800056, /* 31, -9.5dB */ -- 0x14400051, /* 32, -10.0dB */ -- 0x1300004c, /* 33, -10.5dB */ -- 0x12000048, /* 34, -11.0dB */ -- 0x11000044, /* 35, -11.5dB */ -- 0x10000040, /* 36, -12.0dB */ -- 0x0f00003c, /* 37, -12.5dB */ -- 0x0e400039, /* 38, -13.0dB */ -- 0x0d800036, /* 39, -13.5dB */ -- 0x0cc00033, /* 40, -14.0dB */ -- 0x0c000030, /* 41, -14.5dB */ -- 0x0b40002d, /* 42, -15.0dB */ --}; -- --static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = { -- {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ -- {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ -- {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */ -- {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */ -- {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ -- {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */ -- {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */ -- {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */ -- {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ -- {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */ -- {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ -- {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */ -- {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */ -- {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */ -- {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ -- {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */ -- {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ -- {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */ -- {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ -- {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */ -- {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */ -- {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */ -- {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */ -- {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */ -- {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */ -- {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */ -- {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */ -- {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */ -- {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */ -- {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */ -- {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */ -- {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */ -- {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */ --}; -- --static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = { -- {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ -- {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ -- {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ -- {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */ -- {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ -- {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */ -- {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ -- {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ -- {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ -- {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */ -- {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ -- {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */ -- {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */ -- {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ -- {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ -- {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */ -- {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ -- {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */ -- {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ -- {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */ -- {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */ -- {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */ -- {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */ -- {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */ -- {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */ -- {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */ -- {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */ -- {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */ -- {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */ -- {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */ -- {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */ -- {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */ -- {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */ --}; -- --static void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) --{ -- u32 ret_value; -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt); -- unsigned long flag = 0; -- -- /* hold ofdm counter */ -- rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */ -- rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */ -- -- ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD); -- falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff); -- falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); -- ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); -- falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); -- ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); -- falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); -- falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); -- ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); -- falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); -- falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + -- falsealm_cnt->cnt_rate_illegal + -- falsealm_cnt->cnt_crc8_fail + -- falsealm_cnt->cnt_mcs_fail + -- falsealm_cnt->cnt_fast_fsync_fail + -- falsealm_cnt->cnt_sb_search_fail; -- -- if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) { -- /* hold cck counter */ -- rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); -- ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); -- falsealm_cnt->cnt_cck_fail = ret_value; -- ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3); -- falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8; -- rtl92d_release_cckandrw_pagea_ctl(hw, &flag); -- } else { -- falsealm_cnt->cnt_cck_fail = 0; -- } -- -- /* reset false alarm counter registers */ -- falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail + -- falsealm_cnt->cnt_sb_search_fail + -- falsealm_cnt->cnt_parity_fail + -- falsealm_cnt->cnt_rate_illegal + -- falsealm_cnt->cnt_crc8_fail + -- falsealm_cnt->cnt_mcs_fail + -- falsealm_cnt->cnt_cck_fail; -- -- rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1); -- /* update ofdm counter */ -- rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0); -- /* update page C counter */ -- rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0); -- /* update page D counter */ -- rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0); -- if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) { -- /* reset cck counter */ -- rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); -- rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0); -- /* enable cck counter */ -- rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2); -- rtl92d_release_cckandrw_pagea_ctl(hw, &flag); -- } -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -- "Cnt_Fast_Fsync_fail = %x, Cnt_SB_Search_fail = %x\n", -- falsealm_cnt->cnt_fast_fsync_fail, -- falsealm_cnt->cnt_sb_search_fail); -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -- "Cnt_Parity_Fail = %x, Cnt_Rate_Illegal = %x, Cnt_Crc8_fail = %x, Cnt_Mcs_fail = %x\n", -- falsealm_cnt->cnt_parity_fail, -- falsealm_cnt->cnt_rate_illegal, -- falsealm_cnt->cnt_crc8_fail, -- falsealm_cnt->cnt_mcs_fail); -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -- "Cnt_Ofdm_fail = %x, Cnt_Cck_fail = %x, Cnt_all = %x\n", -- falsealm_cnt->cnt_ofdm_fail, -- falsealm_cnt->cnt_cck_fail, -- falsealm_cnt->cnt_all); --} -- --static void rtl92d_dm_find_minimum_rssi(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct dig_t *de_digtable = &rtlpriv->dm_digtable; -- struct rtl_mac *mac = rtl_mac(rtlpriv); -- -- /* Determine the minimum RSSI */ -- if ((mac->link_state < MAC80211_LINKED) && -- (rtlpriv->dm.UNDEC_SM_PWDB == 0)) { -- de_digtable->min_undec_pwdb_for_dm = 0; -- rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, -- "Not connected to any\n"); -- } -- if (mac->link_state >= MAC80211_LINKED) { -- if (mac->opmode == NL80211_IFTYPE_AP || -- mac->opmode == NL80211_IFTYPE_ADHOC) { -- de_digtable->min_undec_pwdb_for_dm = -- rtlpriv->dm.UNDEC_SM_PWDB; -- rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, -- "AP Client PWDB = 0x%lx\n", -- rtlpriv->dm.UNDEC_SM_PWDB); -- } else { -- de_digtable->min_undec_pwdb_for_dm = -- rtlpriv->dm.undec_sm_pwdb; -- rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, -- "STA Default Port PWDB = 0x%x\n", -- de_digtable->min_undec_pwdb_for_dm); -- } -- } else { -- de_digtable->min_undec_pwdb_for_dm = rtlpriv->dm.UNDEC_SM_PWDB; -- rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, -- "AP Ext Port or disconnect PWDB = 0x%x\n", -- de_digtable->min_undec_pwdb_for_dm); -- } -- -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "MinUndecoratedPWDBForDM =%d\n", -- de_digtable->min_undec_pwdb_for_dm); --} -- --static void rtl92d_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct dig_t *de_digtable = &rtlpriv->dm_digtable; -- unsigned long flag = 0; -- -- if (de_digtable->cursta_cstate == DIG_STA_CONNECT) { -- if (de_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { -- if (de_digtable->min_undec_pwdb_for_dm <= 25) -- de_digtable->cur_cck_pd_state = -- CCK_PD_STAGE_LOWRSSI; -- else -- de_digtable->cur_cck_pd_state = -- CCK_PD_STAGE_HIGHRSSI; -- } else { -- if (de_digtable->min_undec_pwdb_for_dm <= 20) -- de_digtable->cur_cck_pd_state = -- CCK_PD_STAGE_LOWRSSI; -- else -- de_digtable->cur_cck_pd_state = -- CCK_PD_STAGE_HIGHRSSI; -- } -- } else { -- de_digtable->cur_cck_pd_state = CCK_PD_STAGE_LOWRSSI; -- } -- if (de_digtable->pre_cck_pd_state != de_digtable->cur_cck_pd_state) { -- if (de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) { -- rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); -- rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83); -- rtl92d_release_cckandrw_pagea_ctl(hw, &flag); -- } else { -- rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); -- rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd); -- rtl92d_release_cckandrw_pagea_ctl(hw, &flag); -- } -- de_digtable->pre_cck_pd_state = de_digtable->cur_cck_pd_state; -- } -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "CurSTAConnectState=%s\n", -- de_digtable->cursta_cstate == DIG_STA_CONNECT ? -- "DIG_STA_CONNECT " : "DIG_STA_DISCONNECT"); -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "CCKPDStage=%s\n", -- de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI ? -- "Low RSSI " : "High RSSI "); -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "is92d single phy =%x\n", -- IS_92D_SINGLEPHY(rtlpriv->rtlhal.version)); -- --} -- --void rtl92d_dm_write_dig(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct dig_t *de_digtable = &rtlpriv->dm_digtable; -- -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -- "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n", -- de_digtable->cur_igvalue, de_digtable->pre_igvalue, -- de_digtable->back_val); -- if (de_digtable->dig_enable_flag == false) { -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "DIG is disabled\n"); -- de_digtable->pre_igvalue = 0x17; -- return; -- } -- if (de_digtable->pre_igvalue != de_digtable->cur_igvalue) { -- rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, -- de_digtable->cur_igvalue); -- rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, -- de_digtable->cur_igvalue); -- de_digtable->pre_igvalue = de_digtable->cur_igvalue; -- } --} -- --static void rtl92d_early_mode_enabled(struct rtl_priv *rtlpriv) --{ -- struct dig_t *de_digtable = &rtlpriv->dm_digtable; -- -- if ((rtlpriv->mac80211.link_state >= MAC80211_LINKED) && -- (rtlpriv->mac80211.vendor == PEER_CISCO)) { -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "IOT_PEER = CISCO\n"); -- if (de_digtable->last_min_undec_pwdb_for_dm >= 50 -- && de_digtable->min_undec_pwdb_for_dm < 50) { -- rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x00); -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -- "Early Mode Off\n"); -- } else if (de_digtable->last_min_undec_pwdb_for_dm <= 55 && -- de_digtable->min_undec_pwdb_for_dm > 55) { -- rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f); -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -- "Early Mode On\n"); -- } -- } else if (!(rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL) & 0xf)) { -- rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f); -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "Early Mode On\n"); -- } --} -- --static void rtl92d_dm_dig(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct dig_t *de_digtable = &rtlpriv->dm_digtable; -- u8 value_igi = de_digtable->cur_igvalue; -- struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt); -- -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "==>\n"); -- if (rtlpriv->rtlhal.earlymode_enable) { -- rtl92d_early_mode_enabled(rtlpriv); -- de_digtable->last_min_undec_pwdb_for_dm = -- de_digtable->min_undec_pwdb_for_dm; -- } -- if (!rtlpriv->dm.dm_initialgain_enable) -- return; -- -- /* because we will send data pkt when scanning -- * this will cause some ap like gear-3700 wep TP -- * lower if we return here, this is the diff of -- * mac80211 driver vs ieee80211 driver */ -- /* if (rtlpriv->mac80211.act_scanning) -- * return; */ -- -- /* Not STA mode return tmp */ -- if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION) -- return; -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "progress\n"); -- /* Decide the current status and if modify initial gain or not */ -- if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) -- de_digtable->cursta_cstate = DIG_STA_CONNECT; -- else -- de_digtable->cursta_cstate = DIG_STA_DISCONNECT; -- -- /* adjust initial gain according to false alarm counter */ -- if (falsealm_cnt->cnt_all < DM_DIG_FA_TH0) -- value_igi--; -- else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH1) -- value_igi += 0; -- else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH2) -- value_igi++; -- else if (falsealm_cnt->cnt_all >= DM_DIG_FA_TH2) -- value_igi += 2; -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -- "dm_DIG() Before: large_fa_hit=%d, forbidden_igi=%x\n", -- de_digtable->large_fa_hit, de_digtable->forbidden_igi); -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -- "dm_DIG() Before: Recover_cnt=%d, rx_gain_min=%x\n", -- de_digtable->recover_cnt, de_digtable->rx_gain_min); -- -- /* deal with abnormally large false alarm */ -- if (falsealm_cnt->cnt_all > 10000) { -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -- "dm_DIG(): Abnormally false alarm case\n"); -- -- de_digtable->large_fa_hit++; -- if (de_digtable->forbidden_igi < de_digtable->cur_igvalue) { -- de_digtable->forbidden_igi = de_digtable->cur_igvalue; -- de_digtable->large_fa_hit = 1; -- } -- if (de_digtable->large_fa_hit >= 3) { -- if ((de_digtable->forbidden_igi + 1) > DM_DIG_MAX) -- de_digtable->rx_gain_min = DM_DIG_MAX; -- else -- de_digtable->rx_gain_min = -- (de_digtable->forbidden_igi + 1); -- de_digtable->recover_cnt = 3600; /* 3600=2hr */ -- } -- } else { -- /* Recovery mechanism for IGI lower bound */ -- if (de_digtable->recover_cnt != 0) { -- de_digtable->recover_cnt--; -- } else { -- if (de_digtable->large_fa_hit == 0) { -- if ((de_digtable->forbidden_igi - 1) < -- DM_DIG_FA_LOWER) { -- de_digtable->forbidden_igi = -- DM_DIG_FA_LOWER; -- de_digtable->rx_gain_min = -- DM_DIG_FA_LOWER; -- -- } else { -- de_digtable->forbidden_igi--; -- de_digtable->rx_gain_min = -- (de_digtable->forbidden_igi + 1); -- } -- } else if (de_digtable->large_fa_hit == 3) { -- de_digtable->large_fa_hit = 0; -- } -- } -- } -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -- "dm_DIG() After: large_fa_hit=%d, forbidden_igi=%x\n", -- de_digtable->large_fa_hit, de_digtable->forbidden_igi); -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, -- "dm_DIG() After: recover_cnt=%d, rx_gain_min=%x\n", -- de_digtable->recover_cnt, de_digtable->rx_gain_min); -- -- if (value_igi > DM_DIG_MAX) -- value_igi = DM_DIG_MAX; -- else if (value_igi < de_digtable->rx_gain_min) -- value_igi = de_digtable->rx_gain_min; -- de_digtable->cur_igvalue = value_igi; -- rtl92d_dm_write_dig(hw); -- if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) -- rtl92d_dm_cck_packet_detection_thresh(hw); -- rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "<<==\n"); --} -- - static void rtl92d_dm_init_dynamic_txpower(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -@@ -579,626 +140,7 @@ static void rtl92d_dm_pwdb_monitor(struct ieee80211_hw *hw) - } - } - --void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- -- rtlpriv->dm.current_turbo_edca = false; -- rtlpriv->dm.is_any_nonbepkts = false; -- rtlpriv->dm.is_cur_rdlstate = false; --} -- --static void rtl92d_dm_check_edca_turbo(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -- const u32 edca_be_ul = 0x5ea42b; -- const u32 edca_be_dl = 0x5ea42b; -- static u64 last_txok_cnt; -- static u64 last_rxok_cnt; -- u64 cur_txok_cnt; -- u64 cur_rxok_cnt; -- -- if (mac->link_state != MAC80211_LINKED) { -- rtlpriv->dm.current_turbo_edca = false; -- goto exit; -- } -- -- if ((!rtlpriv->dm.is_any_nonbepkts) && -- (!rtlpriv->dm.disable_framebursting)) { -- cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt; -- cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt; -- if (cur_rxok_cnt > 4 * cur_txok_cnt) { -- if (!rtlpriv->dm.is_cur_rdlstate || -- !rtlpriv->dm.current_turbo_edca) { -- rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, -- edca_be_dl); -- rtlpriv->dm.is_cur_rdlstate = true; -- } -- } else { -- if (rtlpriv->dm.is_cur_rdlstate || -- !rtlpriv->dm.current_turbo_edca) { -- rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, -- edca_be_ul); -- rtlpriv->dm.is_cur_rdlstate = false; -- } -- } -- rtlpriv->dm.current_turbo_edca = true; -- } else { -- if (rtlpriv->dm.current_turbo_edca) { -- u8 tmp = AC0_BE; -- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, -- &tmp); -- rtlpriv->dm.current_turbo_edca = false; -- } -- } -- --exit: -- rtlpriv->dm.is_any_nonbepkts = false; -- last_txok_cnt = rtlpriv->stats.txbytesunicast; -- last_rxok_cnt = rtlpriv->stats.rxbytesunicast; --} -- --static void rtl92d_dm_rxgain_tracking_thermalmeter(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u8 index_mapping[RX_INDEX_MAPPING_NUM] = { -- 0x0f, 0x0f, 0x0d, 0x0c, 0x0b, -- 0x0a, 0x09, 0x08, 0x07, 0x06, -- 0x05, 0x04, 0x04, 0x03, 0x02 -- }; -- int i; -- u32 u4tmp; -- -- u4tmp = (index_mapping[(rtlpriv->efuse.eeprom_thermalmeter - -- rtlpriv->dm.thermalvalue_rxgain)]) << 12; -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "===> Rx Gain %x\n", u4tmp); -- for (i = RF90_PATH_A; i < rtlpriv->phy.num_total_rfpath; i++) -- rtl_set_rfreg(hw, i, 0x3C, RFREG_OFFSET_MASK, -- (rtlpriv->phy.reg_rf3c[i] & (~(0xF000))) | u4tmp); --} -- --static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg, -- u8 *cck_index_old) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- int i; -- unsigned long flag = 0; -- long temp_cck; -- const u8 *cckswing; -- -- /* Query CCK default setting From 0xa24 */ -- rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); -- temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2, -- MASKDWORD) & MASKCCK; -- rtl92d_release_cckandrw_pagea_ctl(hw, &flag); -- for (i = 0; i < CCK_TABLE_LENGTH; i++) { -- if (rtlpriv->dm.cck_inch14) -- cckswing = &cckswing_table_ch14[i][2]; -- else -- cckswing = &cckswing_table_ch1ch13[i][2]; -- -- if (temp_cck == le32_to_cpu(*((__le32 *)cckswing))) { -- *cck_index_old = (u8)i; -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch14 %d\n", -- RCCK0_TXFILTER2, temp_cck, -- *cck_index_old, -- rtlpriv->dm.cck_inch14); -- break; -- } -- } -- *temp_cckg = temp_cck; --} -- --static void rtl92d_bandtype_5G(struct rtl_hal *rtlhal, u8 *ofdm_index, -- bool *internal_pa, u8 thermalvalue, u8 delta, -- u8 rf, struct rtl_efuse *rtlefuse, -- struct rtl_priv *rtlpriv, struct rtl_phy *rtlphy, -- const u8 index_mapping[5][INDEX_MAPPING_NUM], -- const u8 index_mapping_pa[8][INDEX_MAPPING_NUM]) --{ -- int i; -- u8 index; -- u8 offset = 0; -- -- for (i = 0; i < rf; i++) { -- if (rtlhal->macphymode == DUALMAC_DUALPHY && -- rtlhal->interfaceindex == 1) /* MAC 1 5G */ -- *internal_pa = rtlefuse->internal_pa_5g[1]; -- else -- *internal_pa = rtlefuse->internal_pa_5g[i]; -- if (*internal_pa) { -- if (rtlhal->interfaceindex == 1 || i == rf) -- offset = 4; -- else -- offset = 0; -- if (rtlphy->current_channel >= 100 && -- rtlphy->current_channel <= 165) -- offset += 2; -- } else { -- if (rtlhal->interfaceindex == 1 || i == rf) -- offset = 2; -- else -- offset = 0; -- } -- if (thermalvalue > rtlefuse->eeprom_thermalmeter) -- offset++; -- if (*internal_pa) { -- if (delta > INDEX_MAPPING_NUM - 1) -- index = index_mapping_pa[offset] -- [INDEX_MAPPING_NUM - 1]; -- else -- index = -- index_mapping_pa[offset][delta]; -- } else { -- if (delta > INDEX_MAPPING_NUM - 1) -- index = -- index_mapping[offset][INDEX_MAPPING_NUM - 1]; -- else -- index = index_mapping[offset][delta]; -- } -- if (thermalvalue > rtlefuse->eeprom_thermalmeter) { -- if (*internal_pa && thermalvalue > 0x12) { -- ofdm_index[i] = rtlpriv->dm.ofdm_index[i] - -- ((delta / 2) * 3 + (delta % 2)); -- } else { -- ofdm_index[i] -= index; -- } -- } else { -- ofdm_index[i] += index; -- } -- } --} -- --static void rtl92d_dm_txpower_tracking_callback_thermalmeter( -- struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -- u8 thermalvalue, delta, delta_lck, delta_iqk, delta_rxgain; -- u8 offset, thermalvalue_avg_count = 0; -- u32 thermalvalue_avg = 0; -- bool internal_pa = false; -- long ele_a = 0, ele_d, temp_cck, val_x, value32; -- long val_y, ele_c = 0; -- u8 ofdm_index[2]; -- s8 cck_index = 0; -- u8 ofdm_index_old[2] = {0, 0}; -- s8 cck_index_old = 0; -- u8 index; -- int i; -- bool is2t = IS_92D_SINGLEPHY(rtlhal->version); -- u8 ofdm_min_index = 6, ofdm_min_index_internal_pa = 3, rf; -- u8 indexforchannel = -- rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel); -- static const u8 index_mapping[5][INDEX_MAPPING_NUM] = { -- /* 5G, path A/MAC 0, decrease power */ -- {0, 1, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, -- /* 5G, path A/MAC 0, increase power */ -- {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, -- /* 5G, path B/MAC 1, decrease power */ -- {0, 2, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, -- /* 5G, path B/MAC 1, increase power */ -- {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, -- /* 2.4G, for decreas power */ -- {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10}, -- }; -- static const u8 index_mapping_internal_pa[8][INDEX_MAPPING_NUM] = { -- /* 5G, path A/MAC 0, ch36-64, decrease power */ -- {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, -- /* 5G, path A/MAC 0, ch36-64, increase power */ -- {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, -- /* 5G, path A/MAC 0, ch100-165, decrease power */ -- {0, 1, 2, 3, 5, 6, 8, 10, 11, 13, 14, 15, 15}, -- /* 5G, path A/MAC 0, ch100-165, increase power */ -- {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, -- /* 5G, path B/MAC 1, ch36-64, decrease power */ -- {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, -- /* 5G, path B/MAC 1, ch36-64, increase power */ -- {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, -- /* 5G, path B/MAC 1, ch100-165, decrease power */ -- {0, 1, 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 14}, -- /* 5G, path B/MAC 1, ch100-165, increase power */ -- {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, -- }; -- -- rtlpriv->dm.txpower_trackinginit = true; -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "\n"); -- thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0xf800); -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n", -- thermalvalue, -- rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter); -- rtl92d_phy_ap_calibrate(hw, (thermalvalue - -- rtlefuse->eeprom_thermalmeter)); -- -- if (!thermalvalue) -- goto exit; -- -- if (is2t) -- rf = 2; -- else -- rf = 1; -- -- if (rtlpriv->dm.thermalvalue && !rtlhal->reloadtxpowerindex) -- goto old_index_done; -- -- ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) & MASKOFDM_D; -- for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { -- if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) { -- ofdm_index_old[0] = (u8)i; -- -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n", -- ROFDM0_XATXIQIMBALANCE, -- ele_d, ofdm_index_old[0]); -- break; -- } -- } -- if (is2t) { -- ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, -- MASKDWORD) & MASKOFDM_D; -- for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { -- if (ele_d == -- (ofdmswing_table[i] & MASKOFDM_D)) { -- ofdm_index_old[1] = (u8)i; -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, -- DBG_LOUD, -- "Initial pathB ele_d reg 0x%x = 0x%lx, ofdm_index = 0x%x\n", -- ROFDM0_XBTXIQIMBALANCE, ele_d, -- ofdm_index_old[1]); -- break; -- } -- } -- } -- if (rtlhal->current_bandtype == BAND_ON_2_4G) { -- rtl92d_bandtype_2_4G(hw, &temp_cck, &cck_index_old); -- } else { -- temp_cck = 0x090e1317; -- cck_index_old = 12; -- } -- -- if (!rtlpriv->dm.thermalvalue) { -- rtlpriv->dm.thermalvalue = rtlefuse->eeprom_thermalmeter; -- rtlpriv->dm.thermalvalue_lck = thermalvalue; -- rtlpriv->dm.thermalvalue_iqk = thermalvalue; -- rtlpriv->dm.thermalvalue_rxgain = rtlefuse->eeprom_thermalmeter; -- for (i = 0; i < rf; i++) -- rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; -- rtlpriv->dm.cck_index = cck_index_old; -- } -- if (rtlhal->reloadtxpowerindex) { -- for (i = 0; i < rf; i++) -- rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; -- rtlpriv->dm.cck_index = cck_index_old; -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "reload ofdm index for band switch\n"); -- } --old_index_done: -- for (i = 0; i < rf; i++) -- ofdm_index[i] = rtlpriv->dm.ofdm_index[i]; -- -- rtlpriv->dm.thermalvalue_avg -- [rtlpriv->dm.thermalvalue_avg_index] = thermalvalue; -- rtlpriv->dm.thermalvalue_avg_index++; -- if (rtlpriv->dm.thermalvalue_avg_index == AVG_THERMAL_NUM) -- rtlpriv->dm.thermalvalue_avg_index = 0; -- for (i = 0; i < AVG_THERMAL_NUM; i++) { -- if (rtlpriv->dm.thermalvalue_avg[i]) { -- thermalvalue_avg += rtlpriv->dm.thermalvalue_avg[i]; -- thermalvalue_avg_count++; -- } -- } -- if (thermalvalue_avg_count) -- thermalvalue = (u8)(thermalvalue_avg / thermalvalue_avg_count); -- if (rtlhal->reloadtxpowerindex) { -- delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? -- (thermalvalue - rtlefuse->eeprom_thermalmeter) : -- (rtlefuse->eeprom_thermalmeter - thermalvalue); -- rtlhal->reloadtxpowerindex = false; -- rtlpriv->dm.done_txpower = false; -- } else if (rtlpriv->dm.done_txpower) { -- delta = (thermalvalue > rtlpriv->dm.thermalvalue) ? -- (thermalvalue - rtlpriv->dm.thermalvalue) : -- (rtlpriv->dm.thermalvalue - thermalvalue); -- } else { -- delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? -- (thermalvalue - rtlefuse->eeprom_thermalmeter) : -- (rtlefuse->eeprom_thermalmeter - thermalvalue); -- } -- delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ? -- (thermalvalue - rtlpriv->dm.thermalvalue_lck) : -- (rtlpriv->dm.thermalvalue_lck - thermalvalue); -- delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ? -- (thermalvalue - rtlpriv->dm.thermalvalue_iqk) : -- (rtlpriv->dm.thermalvalue_iqk - thermalvalue); -- delta_rxgain = -- (thermalvalue > rtlpriv->dm.thermalvalue_rxgain) ? -- (thermalvalue - rtlpriv->dm.thermalvalue_rxgain) : -- (rtlpriv->dm.thermalvalue_rxgain - thermalvalue); -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n", -- thermalvalue, rtlpriv->dm.thermalvalue, -- rtlefuse->eeprom_thermalmeter, delta, delta_lck, -- delta_iqk); -- if (delta_lck > rtlefuse->delta_lck && rtlefuse->delta_lck != 0) { -- rtlpriv->dm.thermalvalue_lck = thermalvalue; -- rtl92d_phy_lc_calibrate(hw); -- } -- -- if (delta == 0 || !rtlpriv->dm.txpower_track_control) -- goto check_delta; -- -- rtlpriv->dm.done_txpower = true; -- delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? -- (thermalvalue - rtlefuse->eeprom_thermalmeter) : -- (rtlefuse->eeprom_thermalmeter - thermalvalue); -- if (rtlhal->current_bandtype == BAND_ON_2_4G) { -- offset = 4; -- if (delta > INDEX_MAPPING_NUM - 1) -- index = index_mapping[offset][INDEX_MAPPING_NUM - 1]; -- else -- index = index_mapping[offset][delta]; -- if (thermalvalue > rtlpriv->dm.thermalvalue) { -- for (i = 0; i < rf; i++) -- ofdm_index[i] -= delta; -- cck_index -= delta; -- } else { -- for (i = 0; i < rf; i++) -- ofdm_index[i] += index; -- cck_index += index; -- } -- } else if (rtlhal->current_bandtype == BAND_ON_5G) { -- rtl92d_bandtype_5G(rtlhal, ofdm_index, -- &internal_pa, thermalvalue, -- delta, rf, rtlefuse, rtlpriv, -- rtlphy, index_mapping, -- index_mapping_internal_pa); -- } -- if (is2t) { -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "temp OFDM_A_index=0x%x, OFDM_B_index = 0x%x,cck_index=0x%x\n", -- rtlpriv->dm.ofdm_index[0], -- rtlpriv->dm.ofdm_index[1], -- rtlpriv->dm.cck_index); -- } else { -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "temp OFDM_A_index=0x%x,cck_index = 0x%x\n", -- rtlpriv->dm.ofdm_index[0], -- rtlpriv->dm.cck_index); -- } -- for (i = 0; i < rf; i++) { -- if (ofdm_index[i] > OFDM_TABLE_SIZE_92D - 1) { -- ofdm_index[i] = OFDM_TABLE_SIZE_92D - 1; -- } else if (internal_pa || -- rtlhal->current_bandtype == BAND_ON_2_4G) { -- if (ofdm_index[i] < ofdm_min_index_internal_pa) -- ofdm_index[i] = ofdm_min_index_internal_pa; -- } else if (ofdm_index[i] < ofdm_min_index) { -- ofdm_index[i] = ofdm_min_index; -- } -- } -- if (rtlhal->current_bandtype == BAND_ON_2_4G) { -- if (cck_index > CCK_TABLE_SIZE - 1) { -- cck_index = CCK_TABLE_SIZE - 1; -- } else if (cck_index < 0) { -- cck_index = 0; -- } -- } -- if (is2t) { -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "new OFDM_A_index=0x%x, OFDM_B_index = 0x%x, cck_index=0x%x\n", -- ofdm_index[0], ofdm_index[1], -- cck_index); -- } else { -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "new OFDM_A_index=0x%x,cck_index = 0x%x\n", -- ofdm_index[0], cck_index); -- } -- ele_d = (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22; -- val_x = rtlphy->iqk_matrix[indexforchannel].value[0][0]; -- val_y = rtlphy->iqk_matrix[indexforchannel].value[0][1]; -- if (val_x != 0) { -- if ((val_x & 0x00000200) != 0) -- val_x = val_x | 0xFFFFFC00; -- ele_a = ((val_x * ele_d) >> 8) & 0x000003FF; -- -- /* new element C = element D x Y */ -- if ((val_y & 0x00000200) != 0) -- val_y = val_y | 0xFFFFFC00; -- ele_c = ((val_y * ele_d) >> 8) & 0x000003FF; -- -- /* write new elements A, C, D to regC80 and -- * regC94, element B is always 0 -- */ -- value32 = (ele_d << 22) | ((ele_c & 0x3F) << 16) | ele_a; -- rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, -- MASKDWORD, value32); -- -- value32 = (ele_c & 0x000003C0) >> 6; -- rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, -- value32); -- -- value32 = ((val_x * ele_d) >> 7) & 0x01; -- rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), -- value32); -- -- } else { -- rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, -- MASKDWORD, -- ofdmswing_table[(u8)ofdm_index[0]]); -- rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, -- 0x00); -- rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, -- BIT(24), 0x00); -- } -- -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "TxPwrTracking for interface %d path A: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xe94 = 0x%lx 0xe9c = 0x%lx\n", -- rtlhal->interfaceindex, -- val_x, val_y, ele_a, ele_c, ele_d, -- val_x, val_y); -- -- if (cck_index >= CCK_TABLE_SIZE) -- cck_index = CCK_TABLE_SIZE - 1; -- if (cck_index < 0) -- cck_index = 0; -- if (rtlhal->current_bandtype == BAND_ON_2_4G) { -- /* Adjust CCK according to IQK result */ -- if (!rtlpriv->dm.cck_inch14) { -- rtl_write_byte(rtlpriv, 0xa22, -- cckswing_table_ch1ch13[cck_index][0]); -- rtl_write_byte(rtlpriv, 0xa23, -- cckswing_table_ch1ch13[cck_index][1]); -- rtl_write_byte(rtlpriv, 0xa24, -- cckswing_table_ch1ch13[cck_index][2]); -- rtl_write_byte(rtlpriv, 0xa25, -- cckswing_table_ch1ch13[cck_index][3]); -- rtl_write_byte(rtlpriv, 0xa26, -- cckswing_table_ch1ch13[cck_index][4]); -- rtl_write_byte(rtlpriv, 0xa27, -- cckswing_table_ch1ch13[cck_index][5]); -- rtl_write_byte(rtlpriv, 0xa28, -- cckswing_table_ch1ch13[cck_index][6]); -- rtl_write_byte(rtlpriv, 0xa29, -- cckswing_table_ch1ch13[cck_index][7]); -- } else { -- rtl_write_byte(rtlpriv, 0xa22, -- cckswing_table_ch14[cck_index][0]); -- rtl_write_byte(rtlpriv, 0xa23, -- cckswing_table_ch14[cck_index][1]); -- rtl_write_byte(rtlpriv, 0xa24, -- cckswing_table_ch14[cck_index][2]); -- rtl_write_byte(rtlpriv, 0xa25, -- cckswing_table_ch14[cck_index][3]); -- rtl_write_byte(rtlpriv, 0xa26, -- cckswing_table_ch14[cck_index][4]); -- rtl_write_byte(rtlpriv, 0xa27, -- cckswing_table_ch14[cck_index][5]); -- rtl_write_byte(rtlpriv, 0xa28, -- cckswing_table_ch14[cck_index][6]); -- rtl_write_byte(rtlpriv, 0xa29, -- cckswing_table_ch14[cck_index][7]); -- } -- } -- if (is2t) { -- ele_d = (ofdmswing_table[ofdm_index[1]] & 0xFFC00000) >> 22; -- val_x = rtlphy->iqk_matrix[indexforchannel].value[0][4]; -- val_y = rtlphy->iqk_matrix[indexforchannel].value[0][5]; -- if (val_x != 0) { -- if ((val_x & 0x00000200) != 0) -- /* consider minus */ -- val_x = val_x | 0xFFFFFC00; -- ele_a = ((val_x * ele_d) >> 8) & 0x000003FF; -- /* new element C = element D x Y */ -- if ((val_y & 0x00000200) != 0) -- val_y = val_y | 0xFFFFFC00; -- ele_c = ((val_y * ele_d) >> 8) & 0x00003FF; -- /* write new elements A, C, D to regC88 -- * and regC9C, element B is always 0 -- */ -- value32 = (ele_d << 22) | ((ele_c & 0x3F) << 16) | ele_a; -- rtl_set_bbreg(hw, -- ROFDM0_XBTXIQIMBALANCE, -- MASKDWORD, value32); -- value32 = (ele_c & 0x000003C0) >> 6; -- rtl_set_bbreg(hw, ROFDM0_XDTXAFE, -- MASKH4BITS, value32); -- value32 = ((val_x * ele_d) >> 7) & 0x01; -- rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, -- BIT(28), value32); -- } else { -- rtl_set_bbreg(hw, -- ROFDM0_XBTXIQIMBALANCE, -- MASKDWORD, -- ofdmswing_table[ofdm_index[1]]); -- rtl_set_bbreg(hw, ROFDM0_XDTXAFE, -- MASKH4BITS, 0x00); -- rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, -- BIT(28), 0x00); -- } -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "TxPwrTracking path B: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xeb4 = 0x%lx 0xebc = 0x%lx\n", -- val_x, val_y, ele_a, ele_c, -- ele_d, val_x, val_y); -- } -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", -- rtl_get_bbreg(hw, 0xc80, MASKDWORD), -- rtl_get_bbreg(hw, 0xc94, MASKDWORD), -- rtl_get_rfreg(hw, RF90_PATH_A, 0x24, -- RFREG_OFFSET_MASK)); -- --check_delta: -- if (delta_iqk > rtlefuse->delta_iqk && rtlefuse->delta_iqk != 0) { -- rtl92d_phy_reset_iqk_result(hw); -- rtlpriv->dm.thermalvalue_iqk = thermalvalue; -- rtl92d_phy_iq_calibrate(hw); -- } -- if (delta_rxgain > 0 && rtlhal->current_bandtype == BAND_ON_5G && -- thermalvalue <= rtlefuse->eeprom_thermalmeter) { -- rtlpriv->dm.thermalvalue_rxgain = thermalvalue; -- rtl92d_dm_rxgain_tracking_thermalmeter(hw); -- } -- if (rtlpriv->dm.txpower_track_control) -- rtlpriv->dm.thermalvalue = thermalvalue; -- --exit: -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n"); --} -- --static void rtl92d_dm_initialize_txpower_tracking(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- -- rtlpriv->dm.txpower_tracking = true; -- rtlpriv->dm.txpower_trackinginit = false; -- rtlpriv->dm.txpower_track_control = true; -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "pMgntInfo->txpower_tracking = %d\n", -- rtlpriv->dm.txpower_tracking); --} -- --void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- -- if (!rtlpriv->dm.txpower_tracking) -- return; -- -- if (!rtlpriv->dm.tm_trigger) { -- rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17) | -- BIT(16), 0x03); -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "Trigger 92S Thermal Meter!!\n"); -- rtlpriv->dm.tm_trigger = 1; -- return; -- } else { -- rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "Schedule TxPowerTracking direct call!!\n"); -- rtl92d_dm_txpower_tracking_callback_thermalmeter(hw); -- rtlpriv->dm.tm_trigger = 0; -- } --} -- --void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rate_adaptive *ra = &(rtlpriv->ra); -- -- ra->ratr_state = DM_RATR_STA_INIT; -- ra->pre_ratr_state = DM_RATR_STA_INIT; -- if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER) -- rtlpriv->dm.useramask = true; -- else -- rtlpriv->dm.useramask = false; --} -- --void rtl92d_dm_init(struct ieee80211_hw *hw) -+void rtl92de_dm_init(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - -@@ -1212,7 +154,7 @@ void rtl92d_dm_init(struct ieee80211_hw *hw) - rtl92d_dm_initialize_txpower_tracking(hw); - } - --void rtl92d_dm_watchdog(struct ieee80211_hw *hw) -+void rtl92de_dm_watchdog(struct ieee80211_hw *hw) - { - struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); - bool fw_current_inpsmode = false; -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.h -index 939cc45bfebd..beade227b442 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.h -@@ -4,94 +4,7 @@ - #ifndef __RTL92C_DM_H__ - #define __RTL92C_DM_H__ - --#define HAL_DM_DIG_DISABLE BIT(0) --#define HAL_DM_HIPWR_DISABLE BIT(1) -- --#define OFDM_TABLE_LENGTH 37 --#define OFDM_TABLE_SIZE_92D 43 --#define CCK_TABLE_LENGTH 33 -- --#define CCK_TABLE_SIZE 33 -- --#define BW_AUTO_SWITCH_HIGH_LOW 25 --#define BW_AUTO_SWITCH_LOW_HIGH 30 -- --#define DM_DIG_FA_UPPER 0x32 --#define DM_DIG_FA_LOWER 0x20 --#define DM_DIG_FA_TH0 0x100 --#define DM_DIG_FA_TH1 0x400 --#define DM_DIG_FA_TH2 0x600 -- --#define RXPATHSELECTION_SS_TH_LOW 30 --#define RXPATHSELECTION_DIFF_TH 18 -- --#define DM_RATR_STA_INIT 0 --#define DM_RATR_STA_HIGH 1 --#define DM_RATR_STA_MIDDLE 2 --#define DM_RATR_STA_LOW 3 -- --#define CTS2SELF_THVAL 30 --#define REGC38_TH 20 -- --#define WAIOTTHVAL 25 -- --#define TXHIGHPWRLEVEL_NORMAL 0 --#define TXHIGHPWRLEVEL_LEVEL1 1 --#define TXHIGHPWRLEVEL_LEVEL2 2 --#define TXHIGHPWRLEVEL_BT1 3 --#define TXHIGHPWRLEVEL_BT2 4 -- --#define DM_TYPE_BYFW 0 --#define DM_TYPE_BYDRIVER 1 -- --#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 --#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 --#define INDEX_MAPPING_NUM 13 -- --struct swat { -- u8 failure_cnt; -- u8 try_flag; -- u8 stop_trying; -- long pre_rssi; -- long trying_threshold; -- u8 cur_antenna; -- u8 pre_antenna; --}; -- --enum tag_dynamic_init_gain_operation_type_definition { -- DIG_TYPE_THRESH_HIGH = 0, -- DIG_TYPE_THRESH_LOW = 1, -- DIG_TYPE_BACKOFF = 2, -- DIG_TYPE_RX_GAIN_MIN = 3, -- DIG_TYPE_RX_GAIN_MAX = 4, -- DIG_TYPE_ENABLE = 5, -- DIG_TYPE_DISABLE = 6, -- DIG_OP_TYPE_MAX --}; -- --enum dm_1r_cca { -- CCA_1R = 0, -- CCA_2R = 1, -- CCA_MAX = 2, --}; -- --enum dm_rf { -- RF_SAVE = 0, -- RF_NORMAL = 1, -- RF_MAX = 2, --}; -- --enum dm_sw_ant_switch { -- ANS_ANTENNA_B = 1, -- ANS_ANTENNA_A = 2, -- ANS_ANTENNA_MAX = 3, --}; -- --void rtl92d_dm_init(struct ieee80211_hw *hw); --void rtl92d_dm_watchdog(struct ieee80211_hw *hw); --void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw); --void rtl92d_dm_write_dig(struct ieee80211_hw *hw); --void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw); --void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw); -+void rtl92de_dm_init(struct ieee80211_hw *hw); -+void rtl92de_dm_watchdog(struct ieee80211_hw *hw); - - #endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c -index e1fb29962801..c8444a72ff69 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c -@@ -5,157 +5,12 @@ - #include "../pci.h" - #include "../base.h" - #include "../efuse.h" --#include "reg.h" --#include "def.h" -+#include "../rtl8192d/reg.h" -+#include "../rtl8192d/def.h" -+#include "../rtl8192d/fw_common.h" - #include "fw.h" - #include "sw.h" - --static bool _rtl92d_is_fw_downloaded(struct rtl_priv *rtlpriv) --{ -- return (rtl_read_dword(rtlpriv, REG_MCUFWDL) & MCUFWDL_RDY) ? -- true : false; --} -- --static void _rtl92d_enable_fw_download(struct ieee80211_hw *hw, bool enable) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u8 tmp; -- -- if (enable) { -- tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); -- rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp | 0x04); -- tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL); -- rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01); -- tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2); -- rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7); -- } else { -- tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL); -- rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe); -- /* Reserved for fw extension. -- * 0x81[7] is used for mac0 status , -- * so don't write this reg here -- * rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00);*/ -- } --} -- --static void _rtl92d_write_fw(struct ieee80211_hw *hw, -- enum version_8192d version, u8 *buffer, u32 size) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -- u8 *bufferptr = buffer; -- u32 pagenums, remainsize; -- u32 page, offset; -- -- rtl_dbg(rtlpriv, COMP_FW, DBG_TRACE, "FW size is %d bytes,\n", size); -- if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) -- rtl_fill_dummy(bufferptr, &size); -- pagenums = size / FW_8192D_PAGE_SIZE; -- remainsize = size % FW_8192D_PAGE_SIZE; -- if (pagenums > 8) -- pr_err("Page numbers should not greater then 8\n"); -- for (page = 0; page < pagenums; page++) { -- offset = page * FW_8192D_PAGE_SIZE; -- rtl_fw_page_write(hw, page, (bufferptr + offset), -- FW_8192D_PAGE_SIZE); -- } -- if (remainsize) { -- offset = pagenums * FW_8192D_PAGE_SIZE; -- page = pagenums; -- rtl_fw_page_write(hw, page, (bufferptr + offset), remainsize); -- } --} -- --static int _rtl92d_fw_free_to_go(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u32 counter = 0; -- u32 value32; -- -- do { -- value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL); -- } while ((counter++ < FW_8192D_POLLING_TIMEOUT_COUNT) && -- (!(value32 & FWDL_CHKSUM_RPT))); -- if (counter >= FW_8192D_POLLING_TIMEOUT_COUNT) { -- pr_err("chksum report fail! REG_MCUFWDL:0x%08x\n", -- value32); -- return -EIO; -- } -- value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL); -- value32 |= MCUFWDL_RDY; -- rtl_write_dword(rtlpriv, REG_MCUFWDL, value32); -- return 0; --} -- --void rtl92d_firmware_selfreset(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u8 u1b_tmp; -- u8 delay = 100; -- -- /* Set (REG_HMETFR + 3) to 0x20 is reset 8051 */ -- rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20); -- u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); -- while (u1b_tmp & BIT(2)) { -- delay--; -- if (delay == 0) -- break; -- udelay(50); -- u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); -- } -- WARN_ONCE((delay <= 0), "rtl8192de: 8051 reset failed!\n"); -- rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, -- "=====> 8051 reset success (%d)\n", delay); --} -- --static int _rtl92d_fw_init(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -- u32 counter; -- -- rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, "FW already have download\n"); -- /* polling for FW ready */ -- counter = 0; -- do { -- if (rtlhal->interfaceindex == 0) { -- if (rtl_read_byte(rtlpriv, FW_MAC0_READY) & -- MAC0_READY) { -- rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, -- "Polling FW ready success!! REG_MCUFWDL: 0x%x\n", -- rtl_read_byte(rtlpriv, -- FW_MAC0_READY)); -- return 0; -- } -- udelay(5); -- } else { -- if (rtl_read_byte(rtlpriv, FW_MAC1_READY) & -- MAC1_READY) { -- rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, -- "Polling FW ready success!! REG_MCUFWDL: 0x%x\n", -- rtl_read_byte(rtlpriv, -- FW_MAC1_READY)); -- return 0; -- } -- udelay(5); -- } -- } while (counter++ < POLLING_READY_TIMEOUT_COUNT); -- -- if (rtlhal->interfaceindex == 0) { -- rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, -- "Polling FW ready fail!! MAC0 FW init not ready: 0x%x\n", -- rtl_read_byte(rtlpriv, FW_MAC0_READY)); -- } else { -- rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, -- "Polling FW ready fail!! MAC1 FW init not ready: 0x%x\n", -- rtl_read_byte(rtlpriv, FW_MAC1_READY)); -- } -- rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, -- "Polling FW ready fail!! REG_MCUFWDL:0x%08x\n", -- rtl_read_dword(rtlpriv, REG_MCUFWDL)); -- return -1; --} -- - int rtl92d_download_fw(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -@@ -189,7 +44,7 @@ int rtl92d_download_fw(struct ieee80211_hw *hw) - } - - spin_lock_irqsave(&globalmutex_for_fwdownload, flags); -- fw_downloaded = _rtl92d_is_fw_downloaded(rtlpriv); -+ fw_downloaded = rtl92d_is_fw_downloaded(rtlpriv); - if ((rtl_read_byte(rtlpriv, 0x1f) & BIT(5)) == BIT(5)) - fwdl_in_process = true; - else -@@ -202,7 +57,7 @@ int rtl92d_download_fw(struct ieee80211_hw *hw) - for (count = 0; count < 5000; count++) { - udelay(500); - spin_lock_irqsave(&globalmutex_for_fwdownload, flags); -- fw_downloaded = _rtl92d_is_fw_downloaded(rtlpriv); -+ fw_downloaded = rtl92d_is_fw_downloaded(rtlpriv); - if ((rtl_read_byte(rtlpriv, 0x1f) & BIT(5)) == BIT(5)) - fwdl_in_process = true; - else -@@ -237,11 +92,11 @@ int rtl92d_download_fw(struct ieee80211_hw *hw) - rtl92d_firmware_selfreset(hw); - rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); - } -- _rtl92d_enable_fw_download(hw, true); -- _rtl92d_write_fw(hw, version, pfwdata, fwsize); -- _rtl92d_enable_fw_download(hw, false); -+ rtl92d_enable_fw_download(hw, true); -+ rtl92d_write_fw(hw, version, pfwdata, fwsize); -+ rtl92d_enable_fw_download(hw, false); - spin_lock_irqsave(&globalmutex_for_fwdownload, flags); -- err = _rtl92d_fw_free_to_go(hw); -+ err = rtl92d_fw_free_to_go(hw); - /* download fw over,clear 0x1f[5] */ - value = rtl_read_byte(rtlpriv, 0x1f); - value &= (~BIT(5)); -@@ -250,207 +105,10 @@ int rtl92d_download_fw(struct ieee80211_hw *hw) - if (err) - pr_err("fw is not ready to run!\n"); - exit: -- err = _rtl92d_fw_init(hw); -+ err = rtl92d_fw_init(hw); - return err; - } - --static bool _rtl92d_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u8 val_hmetfr; -- bool result = false; -- -- val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR); -- if (((val_hmetfr >> boxnum) & BIT(0)) == 0) -- result = true; -- return result; --} -- --static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw, -- u8 element_id, u32 cmd_len, u8 *cmdbuffer) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); -- u8 boxnum; -- u16 box_reg = 0, box_extreg = 0; -- u8 u1b_tmp; -- bool isfw_read = false; -- u8 buf_index = 0; -- bool bwrite_success = false; -- u8 wait_h2c_limmit = 100; -- u8 wait_writeh2c_limmit = 100; -- u8 boxcontent[4], boxextcontent[2]; -- u32 h2c_waitcounter = 0; -- unsigned long flag; -- u8 idx; -- -- if (ppsc->rfpwr_state == ERFOFF || ppsc->inactive_pwrstate == ERFOFF) { -- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, -- "Return as RF is off!!!\n"); -- return; -- } -- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n"); -- while (true) { -- spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag); -- if (rtlhal->h2c_setinprogress) { -- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, -- "H2C set in progress! Wait to set..element_id(%d)\n", -- element_id); -- -- while (rtlhal->h2c_setinprogress) { -- spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, -- flag); -- h2c_waitcounter++; -- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, -- "Wait 100 us (%d times)...\n", -- h2c_waitcounter); -- udelay(100); -- -- if (h2c_waitcounter > 1000) -- return; -- -- spin_lock_irqsave(&rtlpriv->locks.h2c_lock, -- flag); -- } -- spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); -- } else { -- rtlhal->h2c_setinprogress = true; -- spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); -- break; -- } -- } -- while (!bwrite_success) { -- wait_writeh2c_limmit--; -- if (wait_writeh2c_limmit == 0) { -- pr_err("Write H2C fail because no trigger for FW INT!\n"); -- break; -- } -- boxnum = rtlhal->last_hmeboxnum; -- switch (boxnum) { -- case 0: -- box_reg = REG_HMEBOX_0; -- box_extreg = REG_HMEBOX_EXT_0; -- break; -- case 1: -- box_reg = REG_HMEBOX_1; -- box_extreg = REG_HMEBOX_EXT_1; -- break; -- case 2: -- box_reg = REG_HMEBOX_2; -- box_extreg = REG_HMEBOX_EXT_2; -- break; -- case 3: -- box_reg = REG_HMEBOX_3; -- box_extreg = REG_HMEBOX_EXT_3; -- break; -- default: -- pr_err("switch case %#x not processed\n", -- boxnum); -- break; -- } -- isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum); -- while (!isfw_read) { -- wait_h2c_limmit--; -- if (wait_h2c_limmit == 0) { -- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, -- "Waiting too long for FW read clear HMEBox(%d)!\n", -- boxnum); -- break; -- } -- udelay(10); -- isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum); -- u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF); -- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, -- "Waiting for FW read clear HMEBox(%d)!!! 0x1BF = %2x\n", -- boxnum, u1b_tmp); -- } -- if (!isfw_read) { -- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, -- "Write H2C register BOX[%d] fail!!!!! Fw do not read.\n", -- boxnum); -- break; -- } -- memset(boxcontent, 0, sizeof(boxcontent)); -- memset(boxextcontent, 0, sizeof(boxextcontent)); -- boxcontent[0] = element_id; -- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, -- "Write element_id box_reg(%4x) = %2x\n", -- box_reg, element_id); -- switch (cmd_len) { -- case 1: -- boxcontent[0] &= ~(BIT(7)); -- memcpy(boxcontent + 1, cmdbuffer + buf_index, 1); -- for (idx = 0; idx < 4; idx++) -- rtl_write_byte(rtlpriv, box_reg + idx, -- boxcontent[idx]); -- break; -- case 2: -- boxcontent[0] &= ~(BIT(7)); -- memcpy(boxcontent + 1, cmdbuffer + buf_index, 2); -- for (idx = 0; idx < 4; idx++) -- rtl_write_byte(rtlpriv, box_reg + idx, -- boxcontent[idx]); -- break; -- case 3: -- boxcontent[0] &= ~(BIT(7)); -- memcpy(boxcontent + 1, cmdbuffer + buf_index, 3); -- for (idx = 0; idx < 4; idx++) -- rtl_write_byte(rtlpriv, box_reg + idx, -- boxcontent[idx]); -- break; -- case 4: -- boxcontent[0] |= (BIT(7)); -- memcpy(boxextcontent, cmdbuffer + buf_index, 2); -- memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 2); -- for (idx = 0; idx < 2; idx++) -- rtl_write_byte(rtlpriv, box_extreg + idx, -- boxextcontent[idx]); -- for (idx = 0; idx < 4; idx++) -- rtl_write_byte(rtlpriv, box_reg + idx, -- boxcontent[idx]); -- break; -- case 5: -- boxcontent[0] |= (BIT(7)); -- memcpy(boxextcontent, cmdbuffer + buf_index, 2); -- memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 3); -- for (idx = 0; idx < 2; idx++) -- rtl_write_byte(rtlpriv, box_extreg + idx, -- boxextcontent[idx]); -- for (idx = 0; idx < 4; idx++) -- rtl_write_byte(rtlpriv, box_reg + idx, -- boxcontent[idx]); -- break; -- default: -- pr_err("switch case %#x not processed\n", -- cmd_len); -- break; -- } -- bwrite_success = true; -- rtlhal->last_hmeboxnum = boxnum + 1; -- if (rtlhal->last_hmeboxnum == 4) -- rtlhal->last_hmeboxnum = 0; -- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, -- "pHalData->last_hmeboxnum = %d\n", -- rtlhal->last_hmeboxnum); -- } -- spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag); -- rtlhal->h2c_setinprogress = false; -- spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); -- rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n"); --} -- --void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, -- u8 element_id, u32 cmd_len, u8 *cmdbuffer) --{ -- u32 tmp_cmdbuf[2]; -- -- memset(tmp_cmdbuf, 0, 8); -- memcpy(tmp_cmdbuf, cmdbuffer, cmd_len); -- _rtl92d_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf); -- return; --} -- - static bool _rtl92d_cmd_send_packet(struct ieee80211_hw *hw, - struct sk_buff *skb) - { -@@ -599,7 +257,7 @@ void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished) - struct sk_buff *skb = NULL; - u32 totalpacketlen; - bool rtstatus; -- u8 u1rsvdpageloc[3] = { 0 }; -+ u8 u1rsvdpageloc[3] = { PROBERSP_PG, PSPOLL_PG, NULL_PG }; - bool dlok = false; - u8 *beacon; - u8 *p_pspoll; -@@ -618,7 +276,6 @@ void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished) - SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000)); - SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid); - SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr); -- SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1rsvdpageloc, PSPOLL_PG); - /*-------------------------------------------------------- - (3) null data - ---------------------------------------------------------*/ -@@ -626,7 +283,6 @@ void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished) - SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid); - SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr); - SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid); -- SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1rsvdpageloc, NULL_PG); - /*--------------------------------------------------------- - (4) probe response - ----------------------------------------------------------*/ -@@ -634,7 +290,6 @@ void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished) - SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid); - SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr); - SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid); -- SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1rsvdpageloc, PROBERSP_PG); - totalpacketlen = TOTAL_RESERVED_PKT_LEN; - RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD, - "rtl92d_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL", -@@ -663,11 +318,3 @@ void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished) - rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, - "Set RSVD page location to Fw FAIL!!!!!!\n"); - } -- --void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus) --{ -- u8 u1_joinbssrpt_parm[1] = {0}; -- -- SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus); -- rtl92d_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm); --} -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.h -index 7f0a17c1a9ea..9e1385ac17b1 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.h -@@ -4,44 +4,7 @@ - #ifndef __RTL92D__FW__H__ - #define __RTL92D__FW__H__ - --#define FW_8192D_START_ADDRESS 0x1000 --#define FW_8192D_PAGE_SIZE 4096 --#define FW_8192D_POLLING_TIMEOUT_COUNT 1000 -- --#define IS_FW_HEADER_EXIST(_pfwhdr) \ -- ((GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFF0) == 0x92C0 || \ -- (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFF0) == 0x88C0 || \ -- (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D0 || \ -- (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D1 || \ -- (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D2 || \ -- (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D3) -- --/* Firmware Header(8-byte alinment required) */ --/* --- LONG WORD 0 ---- */ --#define GET_FIRMWARE_HDR_SIGNATURE(__fwhdr) \ -- le32_get_bits(*(__le32 *)__fwhdr, GENMASK(15, 0)) --#define GET_FIRMWARE_HDR_VERSION(__fwhdr) \ -- le32_get_bits(*(__le32 *)(__fwhdr + 4), GENMASK(15, 0)) --#define GET_FIRMWARE_HDR_SUB_VER(__fwhdr) \ -- le32_get_bits(*(__le32 *)(__fwhdr + 4), GENMASK(23, 16)) -- --#define pagenum_128(_len) \ -- (u32)(((_len) >> 7) + ((_len) & 0x7F ? 1 : 0)) -- --#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__ph2ccmd, __val) \ -- *(u8 *)__ph2ccmd = __val; --#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val) \ -- *(u8 *)__ph2ccmd = __val; --#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \ -- *(u8 *)(__ph2ccmd + 1) = __val; --#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \ -- *(u8 *)(__ph2ccmd + 2) = __val; -- - int rtl92d_download_fw(struct ieee80211_hw *hw); --void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id, -- u32 cmd_len, u8 *p_cmdbuffer); --void rtl92d_firmware_selfreset(struct ieee80211_hw *hw); - void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished); --void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus); - - #endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c -index 4ba42f6be3f2..73b81e60cfa9 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c -@@ -8,8 +8,12 @@ - #include "../cam.h" - #include "../ps.h" - #include "../pci.h" --#include "reg.h" --#include "def.h" -+#include "../rtl8192d/reg.h" -+#include "../rtl8192d/def.h" -+#include "../rtl8192d/dm_common.h" -+#include "../rtl8192d/fw_common.h" -+#include "../rtl8192d/hw_common.h" -+#include "../rtl8192d/phy_common.h" - #include "phy.h" - #include "dm.h" - #include "fw.h" -@@ -50,34 +54,6 @@ static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw, - rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val); - } - --static void _rtl92de_stop_tx_beacon(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u8 tmp1byte; -- -- tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); -- rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6))); -- rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); -- rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); -- tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); -- tmp1byte &= ~(BIT(0)); -- rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); --} -- --static void _rtl92de_resume_tx_beacon(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u8 tmp1byte; -- -- tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); -- rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6)); -- rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a); -- rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); -- tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); -- tmp1byte |= BIT(0); -- rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); --} -- - static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw) - { - _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1)); -@@ -90,58 +66,14 @@ static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw) - - void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) - { -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); - - switch (variable) { - case HW_VAR_RCR: - *((u32 *) (val)) = rtlpci->receive_config; - break; -- case HW_VAR_RF_STATE: -- *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state; -- break; -- case HW_VAR_FWLPS_RF_ON:{ -- enum rf_pwrstate rfstate; -- u32 val_rcr; -- -- rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, -- (u8 *)(&rfstate)); -- if (rfstate == ERFOFF) { -- *((bool *) (val)) = true; -- } else { -- val_rcr = rtl_read_dword(rtlpriv, REG_RCR); -- val_rcr &= 0x00070000; -- if (val_rcr) -- *((bool *) (val)) = false; -- else -- *((bool *) (val)) = true; -- } -- break; -- } -- case HW_VAR_FW_PSMODE_STATUS: -- *((bool *) (val)) = ppsc->fw_current_inpsmode; -- break; -- case HW_VAR_CORRECT_TSF:{ -- u64 tsf; -- u32 *ptsf_low = (u32 *)&tsf; -- u32 *ptsf_high = ((u32 *)&tsf) + 1; -- -- *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); -- *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); -- *((u64 *) (val)) = tsf; -- break; -- } -- case HW_VAR_INT_MIGRATION: -- *((bool *)(val)) = rtlpriv->dm.interrupt_migration; -- break; -- case HW_VAR_INT_AC: -- *((bool *)(val)) = rtlpriv->dm.disable_tx_int; -- break; -- case HAL_DEF_WOWLAN: -- break; - default: -- pr_err("switch case %#x not processed\n", variable); -+ rtl92d_get_hw_reg(hw, variable, val); - break; - } - } -@@ -151,141 +83,8 @@ void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); - struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); -- u8 idx; - - switch (variable) { -- case HW_VAR_ETHER_ADDR: -- for (idx = 0; idx < ETH_ALEN; idx++) { -- rtl_write_byte(rtlpriv, (REG_MACID + idx), -- val[idx]); -- } -- break; -- case HW_VAR_BASIC_RATE: { -- u16 rate_cfg = ((u16 *) val)[0]; -- u8 rate_index = 0; -- -- rate_cfg = rate_cfg & 0x15f; -- if (mac->vendor == PEER_CISCO && -- ((rate_cfg & 0x150) == 0)) -- rate_cfg |= 0x01; -- rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff); -- rtl_write_byte(rtlpriv, REG_RRSR + 1, -- (rate_cfg >> 8) & 0xff); -- while (rate_cfg > 0x1) { -- rate_cfg = (rate_cfg >> 1); -- rate_index++; -- } -- if (rtlhal->fw_version > 0xe) -- rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, -- rate_index); -- break; -- } -- case HW_VAR_BSSID: -- for (idx = 0; idx < ETH_ALEN; idx++) { -- rtl_write_byte(rtlpriv, (REG_BSSID + idx), -- val[idx]); -- } -- break; -- case HW_VAR_SIFS: -- rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); -- rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); -- rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); -- rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); -- if (!mac->ht_enable) -- rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, -- 0x0e0e); -- else -- rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, -- *((u16 *) val)); -- break; -- case HW_VAR_SLOT_TIME: { -- u8 e_aci; -- -- rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, -- "HW_VAR_SLOT_TIME %x\n", val[0]); -- rtl_write_byte(rtlpriv, REG_SLOT, val[0]); -- for (e_aci = 0; e_aci < AC_MAX; e_aci++) -- rtlpriv->cfg->ops->set_hw_reg(hw, -- HW_VAR_AC_PARAM, -- (&e_aci)); -- break; -- } -- case HW_VAR_ACK_PREAMBLE: { -- u8 reg_tmp; -- u8 short_preamble = (bool) (*val); -- -- reg_tmp = (mac->cur_40_prime_sc) << 5; -- if (short_preamble) -- reg_tmp |= 0x80; -- rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); -- break; -- } -- case HW_VAR_AMPDU_MIN_SPACE: { -- u8 min_spacing_to_set; -- -- min_spacing_to_set = *val; -- if (min_spacing_to_set <= 7) { -- mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) | -- min_spacing_to_set); -- *val = min_spacing_to_set; -- rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, -- "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", -- mac->min_space_cfg); -- rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, -- mac->min_space_cfg); -- } -- break; -- } -- case HW_VAR_SHORTGI_DENSITY: { -- u8 density_to_set; -- -- density_to_set = *val; -- mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg; -- mac->min_space_cfg |= (density_to_set << 3); -- rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, -- "Set HW_VAR_SHORTGI_DENSITY: %#x\n", -- mac->min_space_cfg); -- rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, -- mac->min_space_cfg); -- break; -- } -- case HW_VAR_AMPDU_FACTOR: { -- u8 factor_toset; -- u32 regtoset; -- u8 *ptmp_byte = NULL; -- u8 index; -- -- if (rtlhal->macphymode == DUALMAC_DUALPHY) -- regtoset = 0xb9726641; -- else if (rtlhal->macphymode == DUALMAC_SINGLEPHY) -- regtoset = 0x66626641; -- else -- regtoset = 0xb972a841; -- factor_toset = *val; -- if (factor_toset <= 3) { -- factor_toset = (1 << (factor_toset + 2)); -- if (factor_toset > 0xf) -- factor_toset = 0xf; -- for (index = 0; index < 4; index++) { -- ptmp_byte = (u8 *)(®toset) + index; -- if ((*ptmp_byte & 0xf0) > -- (factor_toset << 4)) -- *ptmp_byte = (*ptmp_byte & 0x0f) -- | (factor_toset << 4); -- if ((*ptmp_byte & 0x0f) > factor_toset) -- *ptmp_byte = (*ptmp_byte & 0xf0) -- | (factor_toset); -- } -- rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoset); -- rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, -- "Set HW_VAR_AMPDU_FACTOR: %#x\n", -- factor_toset); -- } -- break; -- } - case HW_VAR_AC_PARAM: { - u8 e_aci = *val; - rtl92d_dm_init_edca_turbo(hw); -@@ -346,37 +145,6 @@ void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) - rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]); - rtlpci->receive_config = ((u32 *) (val))[0]; - break; -- case HW_VAR_RETRY_LIMIT: { -- u8 retry_limit = val[0]; -- -- rtl_write_word(rtlpriv, REG_RL, -- retry_limit << RETRY_LIMIT_SHORT_SHIFT | -- retry_limit << RETRY_LIMIT_LONG_SHIFT); -- break; -- } -- case HW_VAR_DUAL_TSF_RST: -- rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); -- break; -- case HW_VAR_EFUSE_BYTES: -- rtlefuse->efuse_usedbytes = *((u16 *) val); -- break; -- case HW_VAR_EFUSE_USAGE: -- rtlefuse->efuse_usedpercentage = *val; -- break; -- case HW_VAR_IO_CMD: -- rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val)); -- break; -- case HW_VAR_WPA_CONFIG: -- rtl_write_byte(rtlpriv, REG_SECCFG, *val); -- break; -- case HW_VAR_SET_RPWM: -- rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (val)); -- break; -- case HW_VAR_H2C_FW_PWRMODE: -- break; -- case HW_VAR_FW_PSMODE_STATUS: -- ppsc->fw_current_inpsmode = *((bool *) val); -- break; - case HW_VAR_H2C_FW_JOINBSSRPT: { - u8 mstatus = (*val); - u8 tmp_regcr, tmp_reg422; -@@ -409,19 +177,11 @@ void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) - rtl92d_set_fw_joinbss_report_cmd(hw, (*val)); - break; - } -- case HW_VAR_AID: { -- u16 u2btmp; -- u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); -- u2btmp &= 0xC000; -- rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp | -- mac->assoc_id)); -- break; -- } - case HW_VAR_CORRECT_TSF: { - u8 btype_ibss = val[0]; - - if (btype_ibss) -- _rtl92de_stop_tx_beacon(hw); -+ rtl92de_stop_tx_beacon(hw); - _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3)); - rtl_write_dword(rtlpriv, REG_TSFTR, - (u32) (mac->tsf & 0xffffffff)); -@@ -429,7 +189,7 @@ void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) - (u32) ((mac->tsf >> 32) & 0xffffffff)); - _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0); - if (btype_ibss) -- _rtl92de_resume_tx_beacon(hw); -+ rtl92de_resume_tx_beacon(hw); - - break; - } -@@ -472,34 +232,11 @@ void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) - break; - } - default: -- pr_err("switch case %#x not processed\n", variable); -+ rtl92d_set_hw_reg(hw, variable, val); - break; - } - } - --static bool _rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- bool status = true; -- long count = 0; -- u32 value = _LLT_INIT_ADDR(address) | -- _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); -- -- rtl_write_dword(rtlpriv, REG_LLT_INIT, value); -- do { -- value = rtl_read_dword(rtlpriv, REG_LLT_INIT); -- if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) -- break; -- if (count > POLLING_LLT_THRESHOLD) { -- pr_err("Failed to polling write LLT done at address %d!\n", -- address); -- status = false; -- break; -- } -- } while (++count); -- return status; --} -- - static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -@@ -558,13 +295,13 @@ static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw) - - /* 18. LLT_table_init(Adapter); */ - for (i = 0; i < (txpktbuf_bndy - 1); i++) { -- status = _rtl92de_llt_write(hw, i, i + 1); -+ status = rtl92de_llt_write(hw, i, i + 1); - if (!status) - return status; - } - - /* end of list */ -- status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); -+ status = rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); - if (!status) - return status; - -@@ -573,13 +310,13 @@ static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw) - /* config this MAC as two MAC transfer. */ - /* Otherwise used as local loopback buffer. */ - for (i = txpktbuf_bndy; i < maxpage; i++) { -- status = _rtl92de_llt_write(hw, i, (i + 1)); -+ status = rtl92de_llt_write(hw, i, (i + 1)); - if (!status) - return status; - } - - /* Let last entry point to the start entry of ring buffer */ -- status = _rtl92de_llt_write(hw, maxpage, txpktbuf_bndy); -+ status = rtl92de_llt_write(hw, maxpage, txpktbuf_bndy); - if (!status) - return status; - -@@ -842,32 +579,6 @@ static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw) - rtl_write_byte(rtlpriv, 0x352, 0x1); - } - --void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u8 sec_reg_value; -- -- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -- "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n", -- rtlpriv->sec.pairwise_enc_algorithm, -- rtlpriv->sec.group_enc_algorithm); -- if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { -- rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, -- "not open hw encryption\n"); -- return; -- } -- sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE; -- if (rtlpriv->sec.use_defaultkey) { -- sec_reg_value |= SCR_TXUSEDK; -- sec_reg_value |= SCR_RXUSEDK; -- } -- sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK); -- rtl_write_byte(rtlpriv, REG_CR + 1, 0x02); -- rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, -- "The SECR-value %x\n", sec_reg_value); -- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); --} -- - int rtl92de_hw_init(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -@@ -991,11 +702,11 @@ int rtl92de_hw_init(struct ieee80211_hw *hw) - _rtl92de_enable_aspm_back_door(hw); - /* rtlpriv->intf_ops->enable_aspm(hw); */ - -- rtl92d_dm_init(hw); -+ rtl92de_dm_init(hw); - rtlpci->being_init_adapter = false; - - if (ppsc->rfpwr_state == ERFON) { -- rtl92d_phy_lc_calibrate(hw); -+ rtl92d_phy_lc_calibrate(hw, IS_92D_SINGLEPHY(rtlhal->version)); - /* 5G and 2.4G must wait sometime to let RF LO ready */ - if (rtlhal->macphymode == DUALMAC_DUALPHY) { - u32 tmp_rega; -@@ -1020,23 +731,6 @@ int rtl92de_hw_init(struct ieee80211_hw *hw) - return err; - } - --static enum version_8192d _rtl92de_read_chip_version(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY; -- u32 value32; -- -- value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG); -- if (!(value32 & 0x000f0000)) { -- version = VERSION_TEST_CHIP_92D_SINGLEPHY; -- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n"); -- } else { -- version = VERSION_NORMAL_CHIP_92D_SINGLEPHY; -- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n"); -- } -- return version; --} -- - static int _rtl92de_set_media_status(struct ieee80211_hw *hw, - enum nl80211_iftype type) - { -@@ -1048,11 +742,11 @@ static int _rtl92de_set_media_status(struct ieee80211_hw *hw, - - if (type == NL80211_IFTYPE_UNSPECIFIED || - type == NL80211_IFTYPE_STATION) { -- _rtl92de_stop_tx_beacon(hw); -+ rtl92de_stop_tx_beacon(hw); - _rtl92de_enable_bcn_sub_func(hw); - } else if (type == NL80211_IFTYPE_ADHOC || - type == NL80211_IFTYPE_AP) { -- _rtl92de_resume_tx_beacon(hw); -+ rtl92de_resume_tx_beacon(hw); - _rtl92de_disable_bcn_sub_func(hw); - } else { - rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, -@@ -1152,13 +846,6 @@ void rtl92d_linked_set_reg(struct ieee80211_hw *hw) - } - } - --/* don't set REG_EDCA_BE_PARAM here because -- * mac80211 will send pkt when scan */ --void rtl92de_set_qos(struct ieee80211_hw *hw, int aci) --{ -- rtl92d_dm_init_edca_turbo(hw); --} -- - void rtl92de_enable_interrupt(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -@@ -1383,825 +1070,6 @@ void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw, - rtl92de_enable_interrupt(hw); - } - --static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo, -- u8 *rom_content, bool autoloadfail) --{ -- u32 rfpath, eeaddr, group, offset1, offset2; -- u8 i; -- -- memset(pwrinfo, 0, sizeof(struct txpower_info)); -- if (autoloadfail) { -- for (group = 0; group < CHANNEL_GROUP_MAX; group++) { -- for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { -- if (group < CHANNEL_GROUP_MAX_2G) { -- pwrinfo->cck_index[rfpath][group] = -- EEPROM_DEFAULT_TXPOWERLEVEL_2G; -- pwrinfo->ht40_1sindex[rfpath][group] = -- EEPROM_DEFAULT_TXPOWERLEVEL_2G; -- } else { -- pwrinfo->ht40_1sindex[rfpath][group] = -- EEPROM_DEFAULT_TXPOWERLEVEL_5G; -- } -- pwrinfo->ht40_2sindexdiff[rfpath][group] = -- EEPROM_DEFAULT_HT40_2SDIFF; -- pwrinfo->ht20indexdiff[rfpath][group] = -- EEPROM_DEFAULT_HT20_DIFF; -- pwrinfo->ofdmindexdiff[rfpath][group] = -- EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; -- pwrinfo->ht40maxoffset[rfpath][group] = -- EEPROM_DEFAULT_HT40_PWRMAXOFFSET; -- pwrinfo->ht20maxoffset[rfpath][group] = -- EEPROM_DEFAULT_HT20_PWRMAXOFFSET; -- } -- } -- for (i = 0; i < 3; i++) { -- pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI; -- pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI; -- } -- return; -- } -- -- /* Maybe autoload OK,buf the tx power index value is not filled. -- * If we find it, we set it to default value. */ -- for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { -- for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) { -- eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3) -- + group; -- pwrinfo->cck_index[rfpath][group] = -- (rom_content[eeaddr] == 0xFF) ? -- (eeaddr > 0x7B ? -- EEPROM_DEFAULT_TXPOWERLEVEL_5G : -- EEPROM_DEFAULT_TXPOWERLEVEL_2G) : -- rom_content[eeaddr]; -- } -- } -- for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { -- for (group = 0; group < CHANNEL_GROUP_MAX; group++) { -- offset1 = group / 3; -- offset2 = group % 3; -- eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) + -- offset2 + offset1 * 21; -- pwrinfo->ht40_1sindex[rfpath][group] = -- (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ? -- EEPROM_DEFAULT_TXPOWERLEVEL_5G : -- EEPROM_DEFAULT_TXPOWERLEVEL_2G) : -- rom_content[eeaddr]; -- } -- } -- /* These just for 92D efuse offset. */ -- for (group = 0; group < CHANNEL_GROUP_MAX; group++) { -- for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { -- int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G; -- -- offset1 = group / 3; -- offset2 = group % 3; -- -- if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF) -- pwrinfo->ht40_2sindexdiff[rfpath][group] = -- (rom_content[base1 + -- offset2 + offset1 * 21] >> (rfpath * 4)) -- & 0xF; -- else -- pwrinfo->ht40_2sindexdiff[rfpath][group] = -- EEPROM_DEFAULT_HT40_2SDIFF; -- if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2 -- + offset1 * 21] != 0xFF) -- pwrinfo->ht20indexdiff[rfpath][group] = -- (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G -- + offset2 + offset1 * 21] >> (rfpath * 4)) -- & 0xF; -- else -- pwrinfo->ht20indexdiff[rfpath][group] = -- EEPROM_DEFAULT_HT20_DIFF; -- if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2 -- + offset1 * 21] != 0xFF) -- pwrinfo->ofdmindexdiff[rfpath][group] = -- (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G -- + offset2 + offset1 * 21] >> (rfpath * 4)) -- & 0xF; -- else -- pwrinfo->ofdmindexdiff[rfpath][group] = -- EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; -- if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2 -- + offset1 * 21] != 0xFF) -- pwrinfo->ht40maxoffset[rfpath][group] = -- (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G -- + offset2 + offset1 * 21] >> (rfpath * 4)) -- & 0xF; -- else -- pwrinfo->ht40maxoffset[rfpath][group] = -- EEPROM_DEFAULT_HT40_PWRMAXOFFSET; -- if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2 -- + offset1 * 21] != 0xFF) -- pwrinfo->ht20maxoffset[rfpath][group] = -- (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + -- offset2 + offset1 * 21] >> (rfpath * 4)) & -- 0xF; -- else -- pwrinfo->ht20maxoffset[rfpath][group] = -- EEPROM_DEFAULT_HT20_PWRMAXOFFSET; -- } -- } -- if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) { -- /* 5GL */ -- pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F; -- pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F; -- /* 5GM */ -- pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F; -- pwrinfo->tssi_b[1] = -- (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 | -- (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2; -- /* 5GH */ -- pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] & -- 0xF0) >> 4 | -- (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4; -- pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] & -- 0xFC) >> 2; -- } else { -- for (i = 0; i < 3; i++) { -- pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI; -- pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI; -- } -- } --} -- --static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw, -- bool autoload_fail, u8 *hwinfo) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -- struct txpower_info pwrinfo; -- u8 tempval[2], i, pwr, diff; -- u32 ch, rfpath, group; -- -- _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail); -- if (!autoload_fail) { -- /* bit0~2 */ -- rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7); -- rtlefuse->eeprom_thermalmeter = -- hwinfo[EEPROM_THERMAL_METER] & 0x1f; -- rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K]; -- tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03; -- tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2; -- rtlefuse->txpwr_fromeprom = true; -- if (IS_92D_D_CUT(rtlpriv->rtlhal.version) || -- IS_92D_E_CUT(rtlpriv->rtlhal.version)) { -- rtlefuse->internal_pa_5g[0] = -- !((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6); -- rtlefuse->internal_pa_5g[1] = -- !((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6); -- rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, -- "Is D cut,Internal PA0 %d Internal PA1 %d\n", -- rtlefuse->internal_pa_5g[0], -- rtlefuse->internal_pa_5g[1]); -- } -- rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6]; -- rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7]; -- } else { -- rtlefuse->eeprom_regulatory = 0; -- rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER; -- rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP; -- tempval[0] = tempval[1] = 3; -- } -- -- /* Use default value to fill parameters if -- * efuse is not filled on some place. */ -- -- /* ThermalMeter from EEPROM */ -- if (rtlefuse->eeprom_thermalmeter < 0x06 || -- rtlefuse->eeprom_thermalmeter > 0x1c) -- rtlefuse->eeprom_thermalmeter = 0x12; -- rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; -- -- /* check XTAL_K */ -- if (rtlefuse->crystalcap == 0xFF) -- rtlefuse->crystalcap = 0; -- if (rtlefuse->eeprom_regulatory > 3) -- rtlefuse->eeprom_regulatory = 0; -- -- for (i = 0; i < 2; i++) { -- switch (tempval[i]) { -- case 0: -- tempval[i] = 5; -- break; -- case 1: -- tempval[i] = 4; -- break; -- case 2: -- tempval[i] = 3; -- break; -- case 3: -- default: -- tempval[i] = 0; -- break; -- } -- } -- -- rtlefuse->delta_iqk = tempval[0]; -- if (tempval[1] > 0) -- rtlefuse->delta_lck = tempval[1] - 1; -- if (rtlefuse->eeprom_c9 == 0xFF) -- rtlefuse->eeprom_c9 = 0x00; -- rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, -- "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory); -- rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, -- "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter); -- rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, -- "CrystalCap = 0x%x\n", rtlefuse->crystalcap); -- rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, -- "Delta_IQK = 0x%x Delta_LCK = 0x%x\n", -- rtlefuse->delta_iqk, rtlefuse->delta_lck); -- -- for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { -- for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) { -- group = rtl92d_get_chnlgroup_fromarray((u8) ch); -- if (ch < CHANNEL_MAX_NUMBER_2G) -- rtlefuse->txpwrlevel_cck[rfpath][ch] = -- pwrinfo.cck_index[rfpath][group]; -- rtlefuse->txpwrlevel_ht40_1s[rfpath][ch] = -- pwrinfo.ht40_1sindex[rfpath][group]; -- rtlefuse->txpwr_ht20diff[rfpath][ch] = -- pwrinfo.ht20indexdiff[rfpath][group]; -- rtlefuse->txpwr_legacyhtdiff[rfpath][ch] = -- pwrinfo.ofdmindexdiff[rfpath][group]; -- rtlefuse->pwrgroup_ht20[rfpath][ch] = -- pwrinfo.ht20maxoffset[rfpath][group]; -- rtlefuse->pwrgroup_ht40[rfpath][ch] = -- pwrinfo.ht40maxoffset[rfpath][group]; -- pwr = pwrinfo.ht40_1sindex[rfpath][group]; -- diff = pwrinfo.ht40_2sindexdiff[rfpath][group]; -- rtlefuse->txpwrlevel_ht40_2s[rfpath][ch] = -- (pwr > diff) ? (pwr - diff) : 0; -- } -- } --} -- --static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw, -- u8 *content) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -- u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION]; -- -- if (macphy_crvalue & BIT(3)) { -- rtlhal->macphymode = SINGLEMAC_SINGLEPHY; -- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -- "MacPhyMode SINGLEMAC_SINGLEPHY\n"); -- } else { -- rtlhal->macphymode = DUALMAC_DUALPHY; -- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -- "MacPhyMode DUALMAC_DUALPHY\n"); -- } --} -- --static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw, -- u8 *content) --{ -- _rtl92de_read_macphymode_from_prom(hw, content); -- rtl92d_phy_config_macphymode(hw); -- rtl92d_phy_config_macphymode_info(hw); --} -- --static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- enum version_8192d chipver = rtlpriv->rtlhal.version; -- u8 cutvalue[2]; -- u16 chipvalue; -- -- read_efuse_byte(hw, EEPROME_CHIP_VERSION_H, &cutvalue[1]); -- read_efuse_byte(hw, EEPROME_CHIP_VERSION_L, &cutvalue[0]); -- chipvalue = (cutvalue[1] << 8) | cutvalue[0]; -- switch (chipvalue) { -- case 0xAA55: -- chipver |= CHIP_92D_C_CUT; -- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n"); -- break; -- case 0x9966: -- chipver |= CHIP_92D_D_CUT; -- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n"); -- break; -- case 0xCC33: -- chipver |= CHIP_92D_E_CUT; -- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n"); -- break; -- default: -- chipver |= CHIP_92D_D_CUT; -- pr_err("Unknown CUT!\n"); -- break; -- } -- rtlpriv->rtlhal.version = chipver; --} -- --static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -- int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, -- EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D, -- EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, -- COUNTRY_CODE_WORLD_WIDE_13}; -- int i; -- u16 usvalue; -- u8 *hwinfo; -- -- hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); -- if (!hwinfo) -- return; -- -- if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) -- goto exit; -- -- _rtl92de_efuse_update_chip_version(hw); -- _rtl92de_read_macphymode_and_bandtype(hw, hwinfo); -- -- /* Read Permanent MAC address for 2nd interface */ -- if (rtlhal->interfaceindex != 0) { -- for (i = 0; i < 6; i += 2) { -- usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i]; -- *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue; -- } -- } -- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, -- rtlefuse->dev_addr); -- rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); -- _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo); -- -- /* Read Channel Plan */ -- switch (rtlhal->bandset) { -- case BAND_ON_2_4G: -- rtlefuse->channel_plan = COUNTRY_CODE_TELEC; -- break; -- case BAND_ON_5G: -- rtlefuse->channel_plan = COUNTRY_CODE_FCC; -- break; -- case BAND_ON_BOTH: -- rtlefuse->channel_plan = COUNTRY_CODE_FCC; -- break; -- default: -- rtlefuse->channel_plan = COUNTRY_CODE_FCC; -- break; -- } -- rtlefuse->txpwr_fromeprom = true; --exit: -- kfree(hwinfo); --} -- --void rtl92de_read_eeprom_info(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -- u8 tmp_u1b; -- -- rtlhal->version = _rtl92de_read_chip_version(hw); -- tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); -- rtlefuse->autoload_status = tmp_u1b; -- if (tmp_u1b & BIT(4)) { -- rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); -- rtlefuse->epromtype = EEPROM_93C46; -- } else { -- rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); -- rtlefuse->epromtype = EEPROM_BOOT_EFUSE; -- } -- if (tmp_u1b & BIT(5)) { -- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); -- -- rtlefuse->autoload_failflag = false; -- _rtl92de_read_adapter_info(hw); -- } else { -- pr_err("Autoload ERR!!\n"); -- } -- return; --} -- --static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw, -- struct ieee80211_sta *sta) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -- u32 ratr_value; -- u8 ratr_index = 0; -- u8 nmode = mac->ht_enable; -- u8 mimo_ps = IEEE80211_SMPS_OFF; -- u16 shortgi_rate; -- u32 tmp_ratr_value; -- u8 curtxbw_40mhz = mac->bw_40; -- u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? -- 1 : 0; -- u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? -- 1 : 0; -- enum wireless_mode wirelessmode = mac->mode; -- -- if (rtlhal->current_bandtype == BAND_ON_5G) -- ratr_value = sta->deflink.supp_rates[1] << 4; -- else -- ratr_value = sta->deflink.supp_rates[0]; -- ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | -- sta->deflink.ht_cap.mcs.rx_mask[0] << 12); -- switch (wirelessmode) { -- case WIRELESS_MODE_A: -- ratr_value &= 0x00000FF0; -- break; -- case WIRELESS_MODE_B: -- if (ratr_value & 0x0000000c) -- ratr_value &= 0x0000000d; -- else -- ratr_value &= 0x0000000f; -- break; -- case WIRELESS_MODE_G: -- ratr_value &= 0x00000FF5; -- break; -- case WIRELESS_MODE_N_24G: -- case WIRELESS_MODE_N_5G: -- nmode = 1; -- if (mimo_ps == IEEE80211_SMPS_STATIC) { -- ratr_value &= 0x0007F005; -- } else { -- u32 ratr_mask; -- -- if (get_rf_type(rtlphy) == RF_1T2R || -- get_rf_type(rtlphy) == RF_1T1R) { -- ratr_mask = 0x000ff005; -- } else { -- ratr_mask = 0x0f0ff005; -- } -- -- ratr_value &= ratr_mask; -- } -- break; -- default: -- if (rtlphy->rf_type == RF_1T2R) -- ratr_value &= 0x000ff0ff; -- else -- ratr_value &= 0x0f0ff0ff; -- -- break; -- } -- ratr_value &= 0x0FFFFFFF; -- if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) || -- (!curtxbw_40mhz && curshortgi_20mhz))) { -- ratr_value |= 0x10000000; -- tmp_ratr_value = (ratr_value >> 12); -- for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) { -- if ((1 << shortgi_rate) & tmp_ratr_value) -- break; -- } -- shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) | -- (shortgi_rate << 4) | (shortgi_rate); -- } -- rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value); -- rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n", -- rtl_read_dword(rtlpriv, REG_ARFR0)); --} -- --static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, -- struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -- struct rtl_sta_info *sta_entry = NULL; -- u32 ratr_bitmap; -- u8 ratr_index; -- u8 curtxbw_40mhz = (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; -- u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? -- 1 : 0; -- u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? -- 1 : 0; -- enum wireless_mode wirelessmode = 0; -- bool shortgi = false; -- u32 value[2]; -- u8 macid = 0; -- u8 mimo_ps = IEEE80211_SMPS_OFF; -- -- sta_entry = (struct rtl_sta_info *) sta->drv_priv; -- mimo_ps = sta_entry->mimo_ps; -- wirelessmode = sta_entry->wireless_mode; -- if (mac->opmode == NL80211_IFTYPE_STATION) -- curtxbw_40mhz = mac->bw_40; -- else if (mac->opmode == NL80211_IFTYPE_AP || -- mac->opmode == NL80211_IFTYPE_ADHOC) -- macid = sta->aid + 1; -- -- if (rtlhal->current_bandtype == BAND_ON_5G) -- ratr_bitmap = sta->deflink.supp_rates[1] << 4; -- else -- ratr_bitmap = sta->deflink.supp_rates[0]; -- ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | -- sta->deflink.ht_cap.mcs.rx_mask[0] << 12); -- switch (wirelessmode) { -- case WIRELESS_MODE_B: -- ratr_index = RATR_INX_WIRELESS_B; -- if (ratr_bitmap & 0x0000000c) -- ratr_bitmap &= 0x0000000d; -- else -- ratr_bitmap &= 0x0000000f; -- break; -- case WIRELESS_MODE_G: -- ratr_index = RATR_INX_WIRELESS_GB; -- -- if (rssi_level == 1) -- ratr_bitmap &= 0x00000f00; -- else if (rssi_level == 2) -- ratr_bitmap &= 0x00000ff0; -- else -- ratr_bitmap &= 0x00000ff5; -- break; -- case WIRELESS_MODE_A: -- ratr_index = RATR_INX_WIRELESS_G; -- ratr_bitmap &= 0x00000ff0; -- break; -- case WIRELESS_MODE_N_24G: -- case WIRELESS_MODE_N_5G: -- if (wirelessmode == WIRELESS_MODE_N_24G) -- ratr_index = RATR_INX_WIRELESS_NGB; -- else -- ratr_index = RATR_INX_WIRELESS_NG; -- if (mimo_ps == IEEE80211_SMPS_STATIC) { -- if (rssi_level == 1) -- ratr_bitmap &= 0x00070000; -- else if (rssi_level == 2) -- ratr_bitmap &= 0x0007f000; -- else -- ratr_bitmap &= 0x0007f005; -- } else { -- if (rtlphy->rf_type == RF_1T2R || -- rtlphy->rf_type == RF_1T1R) { -- if (curtxbw_40mhz) { -- if (rssi_level == 1) -- ratr_bitmap &= 0x000f0000; -- else if (rssi_level == 2) -- ratr_bitmap &= 0x000ff000; -- else -- ratr_bitmap &= 0x000ff015; -- } else { -- if (rssi_level == 1) -- ratr_bitmap &= 0x000f0000; -- else if (rssi_level == 2) -- ratr_bitmap &= 0x000ff000; -- else -- ratr_bitmap &= 0x000ff005; -- } -- } else { -- if (curtxbw_40mhz) { -- if (rssi_level == 1) -- ratr_bitmap &= 0x0f0f0000; -- else if (rssi_level == 2) -- ratr_bitmap &= 0x0f0ff000; -- else -- ratr_bitmap &= 0x0f0ff015; -- } else { -- if (rssi_level == 1) -- ratr_bitmap &= 0x0f0f0000; -- else if (rssi_level == 2) -- ratr_bitmap &= 0x0f0ff000; -- else -- ratr_bitmap &= 0x0f0ff005; -- } -- } -- } -- if ((curtxbw_40mhz && curshortgi_40mhz) || -- (!curtxbw_40mhz && curshortgi_20mhz)) { -- -- if (macid == 0) -- shortgi = true; -- else if (macid == 1) -- shortgi = false; -- } -- break; -- default: -- ratr_index = RATR_INX_WIRELESS_NGB; -- -- if (rtlphy->rf_type == RF_1T2R) -- ratr_bitmap &= 0x000ff0ff; -- else -- ratr_bitmap &= 0x0f0ff0ff; -- break; -- } -- -- value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28); -- value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80; -- rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, -- "ratr_bitmap :%x value0:%x value1:%x\n", -- ratr_bitmap, value[0], value[1]); -- rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value); -- if (macid != 0) -- sta_entry->ratr_index = ratr_index; --} -- --void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw, -- struct ieee80211_sta *sta, u8 rssi_level, bool update_bw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- -- if (rtlpriv->dm.useramask) -- rtl92de_update_hal_rate_mask(hw, sta, rssi_level, update_bw); -- else -- rtl92de_update_hal_rate_table(hw, sta); --} -- --void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -- u16 sifs_timer; -- -- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, -- &mac->slot_time); -- if (!mac->ht_enable) -- sifs_timer = 0x0a0a; -- else -- sifs_timer = 0x1010; -- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); --} -- --bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); -- struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); -- enum rf_pwrstate e_rfpowerstate_toset; -- u8 u1tmp; -- bool actuallyset = false; -- unsigned long flag; -- -- if (rtlpci->being_init_adapter) -- return false; -- if (ppsc->swrf_processing) -- return false; -- spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); -- if (ppsc->rfchange_inprogress) { -- spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); -- return false; -- } else { -- ppsc->rfchange_inprogress = true; -- spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); -- } -- rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv, -- REG_MAC_PINMUX_CFG) & ~(BIT(3))); -- u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); -- e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; -- if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) { -- rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, -- "GPIOChangeRF - HW Radio ON, RF ON\n"); -- e_rfpowerstate_toset = ERFON; -- ppsc->hwradiooff = false; -- actuallyset = true; -- } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) { -- rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, -- "GPIOChangeRF - HW Radio OFF, RF OFF\n"); -- e_rfpowerstate_toset = ERFOFF; -- ppsc->hwradiooff = true; -- actuallyset = true; -- } -- if (actuallyset) { -- spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); -- ppsc->rfchange_inprogress = false; -- spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); -- } else { -- if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) -- RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); -- spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); -- ppsc->rfchange_inprogress = false; -- spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); -- } -- *valid = 1; -- return !ppsc->hwradiooff; --} -- --void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, -- u8 *p_macaddr, bool is_group, u8 enc_algo, -- bool is_wepkey, bool clear_all) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -- u8 *macaddr = p_macaddr; -- u32 entry_id; -- bool is_pairwise = false; -- static u8 cam_const_addr[4][6] = { -- {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, -- {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, -- {0x00, 0x00, 0x00, 0x00, 0x00, 0x02}, -- {0x00, 0x00, 0x00, 0x00, 0x00, 0x03} -- }; -- static u8 cam_const_broad[] = { -- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff -- }; -- -- if (clear_all) { -- u8 idx; -- u8 cam_offset = 0; -- u8 clear_number = 5; -- rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); -- for (idx = 0; idx < clear_number; idx++) { -- rtl_cam_mark_invalid(hw, cam_offset + idx); -- rtl_cam_empty_entry(hw, cam_offset + idx); -- -- if (idx < 5) { -- memset(rtlpriv->sec.key_buf[idx], 0, -- MAX_KEY_LEN); -- rtlpriv->sec.key_len[idx] = 0; -- } -- } -- } else { -- switch (enc_algo) { -- case WEP40_ENCRYPTION: -- enc_algo = CAM_WEP40; -- break; -- case WEP104_ENCRYPTION: -- enc_algo = CAM_WEP104; -- break; -- case TKIP_ENCRYPTION: -- enc_algo = CAM_TKIP; -- break; -- case AESCCMP_ENCRYPTION: -- enc_algo = CAM_AES; -- break; -- default: -- pr_err("switch case %#x not processed\n", -- enc_algo); -- enc_algo = CAM_TKIP; -- break; -- } -- if (is_wepkey || rtlpriv->sec.use_defaultkey) { -- macaddr = cam_const_addr[key_index]; -- entry_id = key_index; -- } else { -- if (is_group) { -- macaddr = cam_const_broad; -- entry_id = key_index; -- } else { -- if (mac->opmode == NL80211_IFTYPE_AP) { -- entry_id = rtl_cam_get_free_entry(hw, -- p_macaddr); -- if (entry_id >= TOTAL_CAM_ENTRY) { -- pr_err("Can not find free hw security cam entry\n"); -- return; -- } -- } else { -- entry_id = CAM_PAIRWISE_KEY_POSITION; -- } -- key_index = PAIRWISE_KEYIDX; -- is_pairwise = true; -- } -- } -- if (rtlpriv->sec.key_len[key_index] == 0) { -- rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, -- "delete one entry, entry_id is %d\n", -- entry_id); -- if (mac->opmode == NL80211_IFTYPE_AP) -- rtl_cam_del_entry(hw, p_macaddr); -- rtl_cam_delete_one_entry(hw, p_macaddr, entry_id); -- } else { -- rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, -- "The insert KEY length is %d\n", -- rtlpriv->sec.key_len[PAIRWISE_KEYIDX]); -- rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, -- "The insert KEY is %x %x\n", -- rtlpriv->sec.key_buf[0][0], -- rtlpriv->sec.key_buf[0][1]); -- rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, -- "add one entry\n"); -- if (is_pairwise) { -- RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD, -- "Pairwise Key content", -- rtlpriv->sec.pairwise_key, -- rtlpriv-> -- sec.key_len[PAIRWISE_KEYIDX]); -- rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, -- "set Pairwise key\n"); -- rtl_cam_add_one_entry(hw, macaddr, key_index, -- entry_id, enc_algo, -- CAM_CONFIG_NO_USEDK, -- rtlpriv-> -- sec.key_buf[key_index]); -- } else { -- rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, -- "set group key\n"); -- if (mac->opmode == NL80211_IFTYPE_ADHOC) { -- rtl_cam_add_one_entry(hw, -- rtlefuse->dev_addr, -- PAIRWISE_KEYIDX, -- CAM_PAIRWISE_KEY_POSITION, -- enc_algo, CAM_CONFIG_NO_USEDK, -- rtlpriv->sec.key_buf[entry_id]); -- } -- rtl_cam_add_one_entry(hw, macaddr, key_index, -- entry_id, enc_algo, -- CAM_CONFIG_NO_USEDK, -- rtlpriv->sec.key_buf -- [entry_id]); -- } -- } -- } --} -- - void rtl92de_suspend(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.h -index ea495216d394..bda4a1a7c91d 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.h -@@ -5,7 +5,6 @@ - #define __RTL92DE_HW_H__ - - void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); --void rtl92de_read_eeprom_info(struct ieee80211_hw *hw); - void rtl92de_interrupt_recognized(struct ieee80211_hw *hw, - struct rtl_int *int_vec); - int rtl92de_hw_init(struct ieee80211_hw *hw); -@@ -14,21 +13,11 @@ void rtl92de_enable_interrupt(struct ieee80211_hw *hw); - void rtl92de_disable_interrupt(struct ieee80211_hw *hw); - int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type); - void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid); --void rtl92de_set_qos(struct ieee80211_hw *hw, int aci); - void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw); - void rtl92de_set_beacon_interval(struct ieee80211_hw *hw); - void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw, - u32 add_msr, u32 rm_msr); - void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); --void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw, -- struct ieee80211_sta *sta, u8 rssi_level, -- bool update_bw); --void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw); --bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid); --void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw); --void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, -- u8 *p_macaddr, bool is_group, u8 enc_algo, -- bool is_wepkey, bool clear_all); - - void rtl92de_write_dword_dbi(struct ieee80211_hw *hw, u16 offset, u32 value, - u8 direct); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c -index 4bd708570992..33aede56c81b 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/led.c -@@ -3,7 +3,7 @@ - - #include "../wifi.h" - #include "../pci.h" --#include "reg.h" -+#include "../rtl8192d/reg.h" - #include "led.h" - - void rtl92de_sw_led_on(struct ieee80211_hw *hw, enum rtl_led_pin pin) -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c -index 56b5cd032a9a..d429560009bb 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c -@@ -5,8 +5,11 @@ - #include "../pci.h" - #include "../ps.h" - #include "../core.h" --#include "reg.h" --#include "def.h" -+#include "../rtl8192d/reg.h" -+#include "../rtl8192d/def.h" -+#include "../rtl8192d/dm_common.h" -+#include "../rtl8192d/phy_common.h" -+#include "../rtl8192d/rf_common.h" - #include "phy.h" - #include "rf.h" - #include "dm.h" -@@ -21,9 +24,6 @@ - #define RF_REG_NUM_FOR_C_CUT_2G 5 - #define RF_CHNL_NUM_5G 19 - #define RF_CHNL_NUM_5G_40M 17 --#define TARGET_CHNL_NUM_5G 221 --#define TARGET_CHNL_NUM_2G 14 --#define CV_CURVE_CNT 64 - - static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = { - 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0 -@@ -160,15 +160,6 @@ static u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = { - 25711, 25658, 25606, 25554, 25502, 25451, 25328 - }; - --static const u8 channel_all[59] = { -- 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, -- 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, -- 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, -- 114, 116, 118, 120, 122, 124, 126, 128, 130, -- 132, 134, 136, 138, 140, 149, 151, 153, 155, -- 157, 159, 161, 163, 165 --}; -- - u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -@@ -235,119 +226,6 @@ void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw, - regaddr, bitmask, data); - } - --static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw, -- enum radio_path rfpath, u32 offset) --{ -- -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; -- u32 newoffset; -- u32 tmplong, tmplong2; -- u8 rfpi_enable = 0; -- u32 retvalue; -- -- newoffset = offset; -- tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD); -- if (rfpath == RF90_PATH_A) -- tmplong2 = tmplong; -- else -- tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD); -- tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) | -- (newoffset << 23) | BLSSIREADEDGE; -- rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, -- tmplong & (~BLSSIREADEDGE)); -- udelay(10); -- rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); -- udelay(50); -- udelay(50); -- rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, -- tmplong | BLSSIREADEDGE); -- udelay(10); -- if (rfpath == RF90_PATH_A) -- rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, -- BIT(8)); -- else if (rfpath == RF90_PATH_B) -- rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, -- BIT(8)); -- if (rfpi_enable) -- retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi, -- BLSSIREADBACKDATA); -- else -- retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb, -- BLSSIREADBACKDATA); -- rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n", -- rfpath, pphyreg->rf_rb, retvalue); -- return retvalue; --} -- --static void _rtl92d_phy_rf_serial_write(struct ieee80211_hw *hw, -- enum radio_path rfpath, -- u32 offset, u32 data) --{ -- u32 data_and_addr; -- u32 newoffset; -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; -- -- newoffset = offset; -- /* T65 RF */ -- data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; -- rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr); -- rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", -- rfpath, pphyreg->rf3wire_offset, data_and_addr); --} -- --u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, -- enum radio_path rfpath, u32 regaddr, u32 bitmask) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u32 original_value, readback_value, bitshift; -- -- rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, -- "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", -- regaddr, rfpath, bitmask); -- spin_lock(&rtlpriv->locks.rf_lock); -- original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr); -- bitshift = calculate_bit_shift(bitmask); -- readback_value = (original_value & bitmask) >> bitshift; -- spin_unlock(&rtlpriv->locks.rf_lock); -- rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, -- "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", -- regaddr, rfpath, bitmask, original_value); -- return readback_value; --} -- --void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, -- u32 regaddr, u32 bitmask, u32 data) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- u32 original_value, bitshift; -- -- rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, -- "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", -- regaddr, bitmask, data, rfpath); -- if (bitmask == 0) -- return; -- spin_lock(&rtlpriv->locks.rf_lock); -- if (rtlphy->rf_mode != RF_OP_BY_FW) { -- if (bitmask != RFREG_OFFSET_MASK) { -- original_value = _rtl92d_phy_rf_serial_read(hw, -- rfpath, regaddr); -- bitshift = calculate_bit_shift(bitmask); -- data = ((original_value & (~bitmask)) | -- (data << bitshift)); -- } -- _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data); -- } -- spin_unlock(&rtlpriv->locks.rf_lock); -- rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, -- "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", -- regaddr, bitmask, data, rfpath); --} -- - bool rtl92d_phy_mac_config(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -@@ -374,133 +252,6 @@ bool rtl92d_phy_mac_config(struct ieee80211_hw *hw) - return true; - } - --static void _rtl92d_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- -- /* RF Interface Sowrtware Control */ -- /* 16 LSBs if read 32-bit from 0x870 */ -- rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW; -- /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ -- rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW; -- /* 16 LSBs if read 32-bit from 0x874 */ -- rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW; -- /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ -- -- rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW; -- /* RF Interface Readback Value */ -- /* 16 LSBs if read 32-bit from 0x8E0 */ -- rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB; -- /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ -- rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB; -- /* 16 LSBs if read 32-bit from 0x8E4 */ -- rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB; -- /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ -- rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB; -- -- /* RF Interface Output (and Enable) */ -- /* 16 LSBs if read 32-bit from 0x860 */ -- rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE; -- /* 16 LSBs if read 32-bit from 0x864 */ -- rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE; -- -- /* RF Interface (Output and) Enable */ -- /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ -- rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE; -- /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ -- rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE; -- -- /* Addr of LSSI. Wirte RF register by driver */ -- /* LSSI Parameter */ -- rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset = -- RFPGA0_XA_LSSIPARAMETER; -- rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset = -- RFPGA0_XB_LSSIPARAMETER; -- -- /* RF parameter */ -- /* BB Band Select */ -- rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER; -- rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER; -- rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER; -- rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER; -- -- /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ -- /* Tx gain stage */ -- rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE; -- /* Tx gain stage */ -- rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE; -- /* Tx gain stage */ -- rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE; -- /* Tx gain stage */ -- rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE; -- -- /* Tranceiver A~D HSSI Parameter-1 */ -- /* wire control parameter1 */ -- rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1; -- /* wire control parameter1 */ -- rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1; -- -- /* Tranceiver A~D HSSI Parameter-2 */ -- /* wire control parameter2 */ -- rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2; -- /* wire control parameter2 */ -- rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2; -- -- /* RF switch Control */ -- /* TR/Ant switch control */ -- rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; -- rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL; -- rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; -- rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL; -- -- /* AGC control 1 */ -- rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1; -- rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1; -- rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1; -- rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1; -- -- /* AGC control 2 */ -- rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2; -- rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2; -- rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2; -- rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2; -- -- /* RX AFE control 1 */ -- rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE; -- rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE; -- rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE; -- rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE; -- -- /*RX AFE control 1 */ -- rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE; -- rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE; -- rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE; -- rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE; -- -- /* Tx AFE control 1 */ -- rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE; -- rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE; -- rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE; -- rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE; -- -- /* Tx AFE control 2 */ -- rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE; -- rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE; -- rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE; -- rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE; -- -- /* Tranceiver LSSI Readback SI mode */ -- rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK; -- rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK; -- rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK; -- rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK; -- -- /* Tranceiver LSSI Readback PI mode */ -- rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK; -- rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK; --} -- - static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, - u8 configtype) - { -@@ -601,58 +352,6 @@ static bool _rtl92d_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, - return true; - } - --static void _rtl92d_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, -- u32 regaddr, u32 bitmask, -- u32 data) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- int index; -- -- if (regaddr == RTXAGC_A_RATE18_06) -- index = 0; -- else if (regaddr == RTXAGC_A_RATE54_24) -- index = 1; -- else if (regaddr == RTXAGC_A_CCK1_MCS32) -- index = 6; -- else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) -- index = 7; -- else if (regaddr == RTXAGC_A_MCS03_MCS00) -- index = 2; -- else if (regaddr == RTXAGC_A_MCS07_MCS04) -- index = 3; -- else if (regaddr == RTXAGC_A_MCS11_MCS08) -- index = 4; -- else if (regaddr == RTXAGC_A_MCS15_MCS12) -- index = 5; -- else if (regaddr == RTXAGC_B_RATE18_06) -- index = 8; -- else if (regaddr == RTXAGC_B_RATE54_24) -- index = 9; -- else if (regaddr == RTXAGC_B_CCK1_55_MCS32) -- index = 14; -- else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) -- index = 15; -- else if (regaddr == RTXAGC_B_MCS03_MCS00) -- index = 10; -- else if (regaddr == RTXAGC_B_MCS07_MCS04) -- index = 11; -- else if (regaddr == RTXAGC_B_MCS11_MCS08) -- index = 12; -- else if (regaddr == RTXAGC_B_MCS15_MCS12) -- index = 13; -- else -- return; -- -- rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data; -- rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, -- "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", -- rtlphy->pwrgroup_cnt, index, -- rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index]); -- if (index == 13) -- rtlphy->pwrgroup_cnt++; --} -- - static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, - u8 configtype) - { -@@ -666,7 +365,7 @@ static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, - if (configtype == BASEBAND_CONFIG_PHY_REG) { - for (i = 0; i < phy_regarray_pg_len; i = i + 3) { - rtl_addr_delay(phy_regarray_table_pg[i]); -- _rtl92d_store_pwrindex_diffrate_offset(hw, -+ rtl92d_store_pwrindex_diffrate_offset(hw, - phy_regarray_table_pg[i], - phy_regarray_table_pg[i + 1], - phy_regarray_table_pg[i + 2]); -@@ -726,7 +425,7 @@ bool rtl92d_phy_bb_config(struct ieee80211_hw *hw) - u32 regvaldw; - u8 value; - -- _rtl92d_phy_init_bb_rf_register_definition(hw); -+ rtl92d_phy_init_bb_rf_register_definition(hw); - regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); - rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, - regval | BIT(13) | BIT(0) | BIT(1)); -@@ -812,115 +511,6 @@ bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, - return true; - } - --void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- -- rtlphy->default_initialgain[0] = -- (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); -- rtlphy->default_initialgain[1] = -- (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); -- rtlphy->default_initialgain[2] = -- (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); -- rtlphy->default_initialgain[3] = -- (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); -- rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, -- "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", -- rtlphy->default_initialgain[0], -- rtlphy->default_initialgain[1], -- rtlphy->default_initialgain[2], -- rtlphy->default_initialgain[3]); -- rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, -- MASKBYTE0); -- rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, -- MASKDWORD); -- rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, -- "Default framesync (0x%x) = 0x%x\n", -- ROFDM0_RXDETECTOR3, rtlphy->framesync); --} -- --static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel, -- u8 *cckpowerlevel, u8 *ofdmpowerlevel) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); -- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -- u8 index = (channel - 1); -- -- /* 1. CCK */ -- if (rtlhal->current_bandtype == BAND_ON_2_4G) { -- /* RF-A */ -- cckpowerlevel[RF90_PATH_A] = -- rtlefuse->txpwrlevel_cck[RF90_PATH_A][index]; -- /* RF-B */ -- cckpowerlevel[RF90_PATH_B] = -- rtlefuse->txpwrlevel_cck[RF90_PATH_B][index]; -- } else { -- cckpowerlevel[RF90_PATH_A] = 0; -- cckpowerlevel[RF90_PATH_B] = 0; -- } -- /* 2. OFDM for 1S or 2S */ -- if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) { -- /* Read HT 40 OFDM TX power */ -- ofdmpowerlevel[RF90_PATH_A] = -- rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index]; -- ofdmpowerlevel[RF90_PATH_B] = -- rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index]; -- } else if (rtlphy->rf_type == RF_2T2R) { -- /* Read HT 40 OFDM TX power */ -- ofdmpowerlevel[RF90_PATH_A] = -- rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index]; -- ofdmpowerlevel[RF90_PATH_B] = -- rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index]; -- } --} -- --static void _rtl92d_ccxpower_index_check(struct ieee80211_hw *hw, -- u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- -- rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; -- rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; --} -- --static u8 _rtl92c_phy_get_rightchnlplace(u8 chnl) --{ -- u8 place = chnl; -- -- if (chnl > 14) { -- for (place = 14; place < ARRAY_SIZE(channel_all); place++) { -- if (channel_all[place] == chnl) { -- place++; -- break; -- } -- } -- } -- return place; --} -- --void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel) --{ -- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u8 cckpowerlevel[2], ofdmpowerlevel[2]; -- -- if (!rtlefuse->txpwr_fromeprom) -- return; -- channel = _rtl92c_phy_get_rightchnlplace(channel); -- _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0], -- &ofdmpowerlevel[0]); -- if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) -- _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0], -- &ofdmpowerlevel[0]); -- if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) -- rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); -- rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel); --} -- - void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw, - enum nl80211_channel_type ch_type) - { -@@ -1122,65 +712,6 @@ static void _rtl92d_phy_reload_imr_setting(struct ieee80211_hw *hw, - rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); - } - --static void _rtl92d_phy_enable_rf_env(struct ieee80211_hw *hw, -- u8 rfpath, u32 *pu4_regval) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; -- -- rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "====>\n"); -- /*----Store original RFENV control type----*/ -- switch (rfpath) { -- case RF90_PATH_A: -- case RF90_PATH_C: -- *pu4_regval = rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV); -- break; -- case RF90_PATH_B: -- case RF90_PATH_D: -- *pu4_regval = -- rtl_get_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16); -- break; -- } -- /*----Set RF_ENV enable----*/ -- rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); -- udelay(1); -- /*----Set RF_ENV output high----*/ -- rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); -- udelay(1); -- /* Set bit number of Address and Data for RF register */ -- /* Set 1 to 4 bits for 8255 */ -- rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0); -- udelay(1); -- /*Set 0 to 12 bits for 8255 */ -- rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); -- udelay(1); -- rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<====\n"); --} -- --static void _rtl92d_phy_restore_rf_env(struct ieee80211_hw *hw, u8 rfpath, -- u32 *pu4_regval) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath]; -- -- rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "=====>\n"); -- /*----Restore RFENV control type----*/ -- switch (rfpath) { -- case RF90_PATH_A: -- case RF90_PATH_C: -- rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, *pu4_regval); -- break; -- case RF90_PATH_B: -- case RF90_PATH_D: -- rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16, -- *pu4_regval); -- break; -- } -- rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<=====\n"); --} -- - static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -@@ -1221,8 +752,8 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) - rtlhal->during_mac1init_radioa = true; - /* asume no this case */ - if (need_pwr_down) -- _rtl92d_phy_enable_rf_env(hw, path, -- &u4regvalue); -+ rtl92d_phy_enable_rf_env(hw, path, -+ &u4regvalue); - } - for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) { - if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) { -@@ -1253,7 +784,7 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) - RFREG_OFFSET_MASK)); - } - if (need_pwr_down) -- _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); -+ rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); - if (rtlhal->during_mac1init_radioa) - rtl92d_phy_powerdown_anotherphy(hw, false); - if (channel < 149) -@@ -1313,8 +844,8 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) - rtlhal->during_mac0init_radiob = true; - - if (need_pwr_down) -- _rtl92d_phy_enable_rf_env(hw, path, -- &u4regvalue); -+ rtl92d_phy_enable_rf_env(hw, path, -+ &u4regvalue); - } - } - for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) { -@@ -1347,31 +878,13 @@ static void _rtl92d_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) - RFREG_OFFSET_MASK, - rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); - if (need_pwr_down) -- _rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); -+ rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); - if (rtlhal->during_mac0init_radiob) - rtl92d_phy_powerdown_anotherphy(hw, true); - } - rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); - } - --u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl) --{ -- u8 place; -- -- if (chnl > 14) { -- for (place = 14; place < ARRAY_SIZE(channel_all); place++) { -- if (channel_all[place] == chnl) -- return place - 13; -- } -- } -- -- return 0; --} -- --#define MAX_TOLERANCE 5 --#define IQK_DELAY_TIME 1 /* ms */ --#define MAX_TOLERANCE_92D 3 -- - /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ - static u8 _rtl92d_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb) - { -@@ -1636,30 +1149,6 @@ static u8 _rtl92d_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw) - return result; - } - --static void _rtl92d_phy_save_adda_registers(struct ieee80211_hw *hw, -- u32 *adda_reg, u32 *adda_backup, -- u32 regnum) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u32 i; -- -- RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save ADDA parameters.\n"); -- for (i = 0; i < regnum; i++) -- adda_backup[i] = rtl_get_bbreg(hw, adda_reg[i], MASKDWORD); --} -- --static void _rtl92d_phy_save_mac_registers(struct ieee80211_hw *hw, -- u32 *macreg, u32 *macbackup) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u32 i; -- -- RTPRINT(rtlpriv, FINIT, INIT_IQK, "Save MAC parameters.\n"); -- for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) -- macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]); -- macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]); --} -- - static void _rtl92d_phy_reload_adda_registers(struct ieee80211_hw *hw, - u32 *adda_reg, u32 *adda_backup, - u32 regnum) -@@ -1685,37 +1174,6 @@ static void _rtl92d_phy_reload_mac_registers(struct ieee80211_hw *hw, - rtl_write_byte(rtlpriv, macreg[i], macbackup[i]); - } - --static void _rtl92d_phy_path_adda_on(struct ieee80211_hw *hw, -- u32 *adda_reg, bool patha_on, bool is2t) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u32 pathon; -- u32 i; -- -- RTPRINT(rtlpriv, FINIT, INIT_IQK, "ADDA ON.\n"); -- pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4; -- if (patha_on) -- pathon = rtlpriv->rtlhal.interfaceindex == 0 ? -- 0x04db25a4 : 0x0b1b25a4; -- for (i = 0; i < IQK_ADDA_REG_NUM; i++) -- rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, pathon); --} -- --static void _rtl92d_phy_mac_setting_calibration(struct ieee80211_hw *hw, -- u32 *macreg, u32 *macbackup) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u32 i; -- -- RTPRINT(rtlpriv, FINIT, INIT_IQK, "MAC settings for Calibration.\n"); -- rtl_write_byte(rtlpriv, macreg[0], 0x3F); -- -- for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) -- rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & -- (~BIT(3)))); -- rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5)))); --} -- - static void _rtl92d_phy_patha_standby(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -@@ -1772,14 +1230,16 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], - is2t ? "2T2R" : "1T1R"); - - /* Save ADDA parameters, turn Path A ADDA on */ -- _rtl92d_phy_save_adda_registers(hw, adda_reg, -- rtlphy->adda_backup, IQK_ADDA_REG_NUM); -- _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, -- rtlphy->iqk_mac_backup); -- _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, -- rtlphy->iqk_bb_backup, IQK_BB_REG_NUM); -- } -- _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); -+ rtl92d_phy_save_adda_registers(hw, adda_reg, -+ rtlphy->adda_backup, -+ IQK_ADDA_REG_NUM); -+ rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, -+ rtlphy->iqk_mac_backup); -+ rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, -+ rtlphy->iqk_bb_backup, -+ IQK_BB_REG_NUM); -+ } -+ rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); - if (t == 0) - rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, - RFPGA0_XA_HSSIPARAMETER1, BIT(8)); -@@ -1800,8 +1260,8 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], - 0x00010000); - } - /* MAC settings */ -- _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, -- rtlphy->iqk_mac_backup); -+ rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, -+ rtlphy->iqk_mac_backup); - /* Page B init */ - rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); - if (is2t) -@@ -1841,7 +1301,7 @@ static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], - if (is2t) { - _rtl92d_phy_patha_standby(hw); - /* Turn Path B ADDA on */ -- _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); -+ rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); - for (i = 0; i < retrycount; i++) { - pathb_ok = _rtl92d_phy_pathb_iqk(hw); - if (pathb_ok == 0x03) { -@@ -1938,24 +1398,24 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw, - RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", - is2t ? "2T2R" : "1T1R"); - /* Save ADDA parameters, turn Path A ADDA on */ -- _rtl92d_phy_save_adda_registers(hw, adda_reg, -- rtlphy->adda_backup, -- IQK_ADDA_REG_NUM); -- _rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, -- rtlphy->iqk_mac_backup); -+ rtl92d_phy_save_adda_registers(hw, adda_reg, -+ rtlphy->adda_backup, -+ IQK_ADDA_REG_NUM); -+ rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, -+ rtlphy->iqk_mac_backup); - if (is2t) -- _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, -- rtlphy->iqk_bb_backup, -- IQK_BB_REG_NUM); -+ rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, -+ rtlphy->iqk_bb_backup, -+ IQK_BB_REG_NUM); - else -- _rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, -- rtlphy->iqk_bb_backup, -- IQK_BB_REG_NUM - 1); -+ rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, -+ rtlphy->iqk_bb_backup, -+ IQK_BB_REG_NUM - 1); - } -- _rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); -+ rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); - /* MAC settings */ -- _rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, -- rtlphy->iqk_mac_backup); -+ rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, -+ rtlphy->iqk_mac_backup); - if (t == 0) - rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, - RFPGA0_XA_HSSIPARAMETER1, BIT(8)); -@@ -2002,7 +1462,7 @@ static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw, - if (is2t) { - /* _rtl92d_phy_patha_standby(hw); */ - /* Turn Path B ADDA on */ -- _rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); -+ rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); - pathb_ok = _rtl92d_phy_pathb_iqk_5g_normal(hw); - if (pathb_ok == 0x03) { - RTPRINT(rtlpriv, FINIT, INIT_IQK, -@@ -2401,56 +1861,6 @@ void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel) - rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); - } - --static u32 _rtl92d_phy_get_abs(u32 val1, u32 val2) --{ -- u32 ret; -- -- if (val1 >= val2) -- ret = val1 - val2; -- else -- ret = val2 - val1; -- return ret; --} -- --static bool _rtl92d_is_legal_5g_channel(struct ieee80211_hw *hw, u8 channel) --{ -- -- int i; -- -- for (i = 0; i < ARRAY_SIZE(channel5g); i++) -- if (channel == channel5g[i]) -- return true; -- return false; --} -- --static void _rtl92d_phy_calc_curvindex(struct ieee80211_hw *hw, -- u32 *targetchnl, u32 * curvecount_val, -- bool is5g, u32 *curveindex) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u32 smallest_abs_val = 0xffffffff, u4tmp; -- u8 i, j; -- u8 chnl_num = is5g ? TARGET_CHNL_NUM_5G : TARGET_CHNL_NUM_2G; -- -- for (i = 0; i < chnl_num; i++) { -- if (is5g && !_rtl92d_is_legal_5g_channel(hw, i + 1)) -- continue; -- curveindex[i] = 0; -- for (j = 0; j < (CV_CURVE_CNT * 2); j++) { -- u4tmp = _rtl92d_phy_get_abs(targetchnl[i], -- curvecount_val[j]); -- -- if (u4tmp < smallest_abs_val) { -- curveindex[i] = j; -- smallest_abs_val = u4tmp; -- } -- } -- smallest_abs_val = 0xffffffff; -- RTPRINT(rtlpriv, FINIT, INIT_IQK, "curveindex[%d] = %x\n", -- i, curveindex[i]); -- } --} -- - static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw, - u8 channel) - { -@@ -2477,12 +1887,12 @@ static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw, - rtlpriv->rtlhal.during_mac1init_radioa = true; - /* asume no this case */ - if (bneed_powerdown_radio) -- _rtl92d_phy_enable_rf_env(hw, erfpath, -- &u4regvalue); -+ rtl92d_phy_enable_rf_env(hw, erfpath, -+ &u4regvalue); - } - rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); - if (bneed_powerdown_radio) -- _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); -+ rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); - if (rtlpriv->rtlhal.during_mac1init_radioa) - rtl92d_phy_powerdown_anotherphy(hw, false); - } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) { -@@ -2495,15 +1905,15 @@ static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw, - rtl92d_phy_enable_anotherphy(hw, true); - rtlpriv->rtlhal.during_mac0init_radiob = true; - if (bneed_powerdown_radio) -- _rtl92d_phy_enable_rf_env(hw, erfpath, -- &u4regvalue); -+ rtl92d_phy_enable_rf_env(hw, erfpath, -+ &u4regvalue); - } - rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); - RTPRINT(rtlpriv, FINIT, INIT_IQK, - "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", - rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)); - if (bneed_powerdown_radio) -- _rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); -+ rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); - if (rtlpriv->rtlhal.during_mac0init_radiob) - rtl92d_phy_powerdown_anotherphy(hw, true); - } -@@ -2588,13 +1998,13 @@ static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t) - readval2); - } - if (index == 0 && rtlhal->interfaceindex == 0) -- _rtl92d_phy_calc_curvindex(hw, targetchnl_5g, -- curvecount_val, -- true, curveindex_5g); -+ rtl92d_phy_calc_curvindex(hw, targetchnl_5g, -+ curvecount_val, -+ true, curveindex_5g); - else -- _rtl92d_phy_calc_curvindex(hw, targetchnl_2g, -- curvecount_val, -- false, curveindex_2g); -+ rtl92d_phy_calc_curvindex(hw, targetchnl_2g, -+ curvecount_val, -+ false, curveindex_2g); - /* switch CV-curve control mode */ - rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, - BIT(17), 0x1); -@@ -2622,7 +2032,7 @@ static void _rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) - _rtl92d_phy_lc_calibrate_sw(hw, is2t); - } - --void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw) -+void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_phy *rtlphy = &(rtlpriv->phy); -@@ -2638,12 +2048,9 @@ void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw) - RTPRINT(rtlpriv, FINIT, INIT_IQK, - "LCK:Start!!! currentband %x delay %d ms\n", - rtlhal->current_bandtype, timecount); -- if (IS_92D_SINGLEPHY(rtlhal->version)) { -- _rtl92d_phy_lc_calibrate(hw, true); -- } else { -- /* For 1T1R */ -- _rtl92d_phy_lc_calibrate(hw, false); -- } -+ -+ _rtl92d_phy_lc_calibrate(hw, is2t); -+ - rtlphy->lck_inprogress = false; - RTPRINT(rtlpriv, FINIT, INIT_IQK, "LCK:Finish!!!\n"); - } -@@ -2674,30 +2081,6 @@ static bool _rtl92d_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, - return true; - } - --void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- u8 i; -- -- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -- "settings regs %zu default regs %d\n", -- ARRAY_SIZE(rtlphy->iqk_matrix), -- IQK_MATRIX_REG_NUM); -- /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */ -- for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) { -- rtlphy->iqk_matrix[i].value[0][0] = 0x100; -- rtlphy->iqk_matrix[i].value[0][2] = 0x100; -- rtlphy->iqk_matrix[i].value[0][4] = 0x100; -- rtlphy->iqk_matrix[i].value[0][6] = 0x100; -- rtlphy->iqk_matrix[i].value[0][1] = 0x0; -- rtlphy->iqk_matrix[i].value[0][3] = 0x0; -- rtlphy->iqk_matrix[i].value[0][5] = 0x0; -- rtlphy->iqk_matrix[i].value[0][7] = 0x0; -- rtlphy->iqk_matrix[i].iqk_done = false; -- } --} -- - static bool _rtl92d_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, - u8 channel, u8 *stage, u8 *step, - u32 *delay) -@@ -2891,74 +2274,6 @@ u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw) - return 1; - } - --static void rtl92d_phy_set_io(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct dig_t *de_digtable = &rtlpriv->dm_digtable; -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- -- rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, -- "--->Cmd(%#x), set_io_inprogress(%d)\n", -- rtlphy->current_io_type, rtlphy->set_io_inprogress); -- switch (rtlphy->current_io_type) { -- case IO_CMD_RESUME_DM_BY_SCAN: -- de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; -- rtl92d_dm_write_dig(hw); -- rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel); -- break; -- case IO_CMD_PAUSE_DM_BY_SCAN: -- rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue; -- de_digtable->cur_igvalue = 0x37; -- rtl92d_dm_write_dig(hw); -- break; -- default: -- pr_err("switch case %#x not processed\n", -- rtlphy->current_io_type); -- break; -- } -- rtlphy->set_io_inprogress = false; -- rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n", -- rtlphy->current_io_type); --} -- --bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- bool postprocessing = false; -- -- rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, -- "-->IO Cmd(%#x), set_io_inprogress(%d)\n", -- iotype, rtlphy->set_io_inprogress); -- do { -- switch (iotype) { -- case IO_CMD_RESUME_DM_BY_SCAN: -- rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, -- "[IO CMD] Resume DM after scan\n"); -- postprocessing = true; -- break; -- case IO_CMD_PAUSE_DM_BY_SCAN: -- rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, -- "[IO CMD] Pause DM before scan\n"); -- postprocessing = true; -- break; -- default: -- pr_err("switch case %#x not processed\n", -- iotype); -- break; -- } -- } while (false); -- if (postprocessing && !rtlphy->set_io_inprogress) { -- rtlphy->set_io_inprogress = true; -- rtlphy->current_io_type = iotype; -- } else { -- return false; -- } -- rtl92d_phy_set_io(hw); -- rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype); -- return true; --} -- - static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -@@ -3141,100 +2456,6 @@ bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw, - return bresult; - } - --void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -- u8 offset = REG_MAC_PHY_CTRL_NORMAL; -- -- switch (rtlhal->macphymode) { -- case DUALMAC_DUALPHY: -- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -- "MacPhyMode: DUALMAC_DUALPHY\n"); -- rtl_write_byte(rtlpriv, offset, 0xF3); -- break; -- case SINGLEMAC_SINGLEPHY: -- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -- "MacPhyMode: SINGLEMAC_SINGLEPHY\n"); -- rtl_write_byte(rtlpriv, offset, 0xF4); -- break; -- case DUALMAC_SINGLEPHY: -- rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -- "MacPhyMode: DUALMAC_SINGLEPHY\n"); -- rtl_write_byte(rtlpriv, offset, 0xF1); -- break; -- } --} -- --void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- -- switch (rtlhal->macphymode) { -- case DUALMAC_SINGLEPHY: -- rtlphy->rf_type = RF_2T2R; -- rtlhal->version |= RF_TYPE_2T2R; -- rtlhal->bandset = BAND_ON_BOTH; -- rtlhal->current_bandtype = BAND_ON_2_4G; -- break; -- -- case SINGLEMAC_SINGLEPHY: -- rtlphy->rf_type = RF_2T2R; -- rtlhal->version |= RF_TYPE_2T2R; -- rtlhal->bandset = BAND_ON_BOTH; -- rtlhal->current_bandtype = BAND_ON_2_4G; -- break; -- -- case DUALMAC_DUALPHY: -- rtlphy->rf_type = RF_1T1R; -- rtlhal->version &= RF_TYPE_1T1R; -- /* Now we let MAC0 run on 5G band. */ -- if (rtlhal->interfaceindex == 0) { -- rtlhal->bandset = BAND_ON_5G; -- rtlhal->current_bandtype = BAND_ON_5G; -- } else { -- rtlhal->bandset = BAND_ON_2_4G; -- rtlhal->current_bandtype = BAND_ON_2_4G; -- } -- break; -- default: -- break; -- } --} -- --u8 rtl92d_get_chnlgroup_fromarray(u8 chnl) --{ -- u8 group; -- -- if (channel_all[chnl] <= 3) -- group = 0; -- else if (channel_all[chnl] <= 9) -- group = 1; -- else if (channel_all[chnl] <= 14) -- group = 2; -- else if (channel_all[chnl] <= 44) -- group = 3; -- else if (channel_all[chnl] <= 54) -- group = 4; -- else if (channel_all[chnl] <= 64) -- group = 5; -- else if (channel_all[chnl] <= 112) -- group = 6; -- else if (channel_all[chnl] <= 126) -- group = 7; -- else if (channel_all[chnl] <= 140) -- group = 8; -- else if (channel_all[chnl] <= 153) -- group = 9; -- else if (channel_all[chnl] <= 159) -- group = 10; -- else -- group = 11; -- return group; --} -- - void rtl92d_phy_set_poweron(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -@@ -3286,31 +2507,6 @@ void rtl92d_phy_set_poweron(struct ieee80211_hw *hw) - } - } - --void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- -- switch (rtlpriv->rtlhal.macphymode) { -- case DUALMAC_DUALPHY: -- rtl_write_byte(rtlpriv, REG_DMC, 0x0); -- rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); -- rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); -- break; -- case DUALMAC_SINGLEPHY: -- rtl_write_byte(rtlpriv, REG_DMC, 0xf8); -- rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); -- rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); -- break; -- case SINGLEMAC_SINGLEPHY: -- rtl_write_byte(rtlpriv, REG_DMC, 0x0); -- rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10); -- rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); -- break; -- default: -- break; -- } --} -- - void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.h -index 8d07c783a023..bbe9ef77225e 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.h -@@ -10,11 +10,8 @@ - - #define MAX_DOZE_WAITING_TIMES_9x 64 - --#define RT_CANNOT_IO(hw) false - #define HIGHPOWER_RADIOA_ARRAYLEN 22 - --#define MAX_TOLERANCE 5 -- - #define APK_BB_REG_NUM 5 - #define APK_AFE_REG_NUM 16 - #define APK_CURVE_REG_NUM 4 -@@ -27,12 +24,8 @@ - #define RESET_CNT_LIMIT 3 - - #define IQK_ADDA_REG_NUM 16 --#define IQK_BB_REG_NUM 10 - #define IQK_BB_REG_NUM_test 6 - #define IQK_MAC_REG_NUM 4 --#define RX_INDEX_MAPPING_NUM 15 -- --#define IQK_DELAY_TIME 1 - - #define CT_OFFSET_MAC_ADDR 0X16 - -@@ -68,80 +61,30 @@ struct swchnlcmd { - u32 msdelay; - }; - --enum baseband_config_type { -- BASEBAND_CONFIG_PHY_REG = 0, -- BASEBAND_CONFIG_AGC_TAB = 1, --}; -- --enum rf_content { -- radioa_txt = 0, -- radiob_txt = 1, -- radioc_txt = 2, -- radiod_txt = 3 --}; -- --static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw, -- unsigned long *flag) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- -- if (rtlpriv->rtlhal.interfaceindex == 1) -- spin_lock_irqsave(&rtlpriv->locks.cck_and_rw_pagea_lock, *flag); --} -- --static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw, -- unsigned long *flag) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- -- if (rtlpriv->rtlhal.interfaceindex == 1) -- spin_unlock_irqrestore(&rtlpriv->locks.cck_and_rw_pagea_lock, -- *flag); --} -- - u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, - u32 regaddr, u32 bitmask); - void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw, - u32 regaddr, u32 bitmask, u32 data); --u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, -- enum radio_path rfpath, u32 regaddr, -- u32 bitmask); --void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, -- enum radio_path rfpath, u32 regaddr, -- u32 bitmask, u32 data); - bool rtl92d_phy_mac_config(struct ieee80211_hw *hw); - bool rtl92d_phy_bb_config(struct ieee80211_hw *hw); - bool rtl92d_phy_rf_config(struct ieee80211_hw *hw); - bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw, - enum radio_path rfpath); --void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw); --void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel); - void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw, - enum nl80211_channel_type ch_type); - u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw); - bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, - enum rf_content content, - enum radio_path rfpath); --bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype); - bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw, - enum rf_pwrstate rfpwr_state); - --void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw); --void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw); --u8 rtl92d_get_chnlgroup_fromarray(u8 chnl); - void rtl92d_phy_set_poweron(struct ieee80211_hw *hw); --void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw); - bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw); --void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw); -+void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t); - void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw); - void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta); - void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw); --void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw); --void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw, -- unsigned long *flag); --void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw, -- unsigned long *flag); --u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl); - void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel); - - #endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.c -index 83787fd293de..eb7d8b070cc7 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.c -@@ -2,383 +2,14 @@ - /* Copyright(c) 2009-2012 Realtek Corporation.*/ - - #include "../wifi.h" --#include "reg.h" --#include "def.h" -+#include "../rtl8192d/reg.h" -+#include "../rtl8192d/def.h" -+#include "../rtl8192d/phy_common.h" - #include "phy.h" - #include "rf.h" - #include "dm.h" - #include "hw.h" - --void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- u8 rfpath; -- -- switch (bandwidth) { -- case HT_CHANNEL_WIDTH_20: -- for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { -- rtlphy->rfreg_chnlval[rfpath] = ((rtlphy->rfreg_chnlval -- [rfpath] & 0xfffff3ff) | 0x0400); -- rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | -- BIT(11), 0x01); -- -- rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, -- "20M RF 0x18 = 0x%x\n", -- rtlphy->rfreg_chnlval[rfpath]); -- } -- -- break; -- case HT_CHANNEL_WIDTH_20_40: -- for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { -- rtlphy->rfreg_chnlval[rfpath] = -- ((rtlphy->rfreg_chnlval[rfpath] & 0xfffff3ff)); -- rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | BIT(11), -- 0x00); -- rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, -- "40M RF 0x18 = 0x%x\n", -- rtlphy->rfreg_chnlval[rfpath]); -- } -- break; -- default: -- pr_err("unknown bandwidth: %#X\n", bandwidth); -- break; -- } --} -- --void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw, -- u8 *ppowerlevel) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -- u32 tx_agc[2] = {0, 0}, tmpval; -- bool turbo_scanoff = false; -- u8 idx1, idx2; -- u8 *ptr; -- -- if (rtlefuse->eeprom_regulatory != 0) -- turbo_scanoff = true; -- if (mac->act_scanning) { -- tx_agc[RF90_PATH_A] = 0x3f3f3f3f; -- tx_agc[RF90_PATH_B] = 0x3f3f3f3f; -- if (turbo_scanoff) { -- for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { -- tx_agc[idx1] = ppowerlevel[idx1] | -- (ppowerlevel[idx1] << 8) | -- (ppowerlevel[idx1] << 16) | -- (ppowerlevel[idx1] << 24); -- } -- } -- } else { -- for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { -- tx_agc[idx1] = ppowerlevel[idx1] | -- (ppowerlevel[idx1] << 8) | -- (ppowerlevel[idx1] << 16) | -- (ppowerlevel[idx1] << 24); -- } -- if (rtlefuse->eeprom_regulatory == 0) { -- tmpval = (rtlphy->mcs_offset[0][6]) + -- (rtlphy->mcs_offset[0][7] << 8); -- tx_agc[RF90_PATH_A] += tmpval; -- tmpval = (rtlphy->mcs_offset[0][14]) + -- (rtlphy->mcs_offset[0][15] << 24); -- tx_agc[RF90_PATH_B] += tmpval; -- } -- } -- -- for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) { -- ptr = (u8 *) (&(tx_agc[idx1])); -- for (idx2 = 0; idx2 < 4; idx2++) { -- if (*ptr > RF6052_MAX_TX_PWR) -- *ptr = RF6052_MAX_TX_PWR; -- ptr++; -- } -- } -- -- tmpval = tx_agc[RF90_PATH_A] & 0xff; -- rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval); -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", -- tmpval, RTXAGC_A_CCK1_MCS32); -- tmpval = tx_agc[RF90_PATH_A] >> 8; -- rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", -- tmpval, RTXAGC_B_CCK11_A_CCK2_11); -- tmpval = tx_agc[RF90_PATH_B] >> 24; -- rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval); -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", -- tmpval, RTXAGC_B_CCK11_A_CCK2_11); -- tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff; -- rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval); -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", -- tmpval, RTXAGC_B_CCK1_55_MCS32); --} -- --static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw, -- u8 *ppowerlevel, u8 channel, -- u32 *ofdmbase, u32 *mcsbase) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -- u32 powerbase0, powerbase1; -- u8 legacy_pwrdiff, ht20_pwrdiff; -- u8 i, powerlevel[2]; -- -- for (i = 0; i < 2; i++) { -- powerlevel[i] = ppowerlevel[i]; -- legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1]; -- powerbase0 = powerlevel[i] + legacy_pwrdiff; -- powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) | -- (powerbase0 << 8) | powerbase0; -- *(ofdmbase + i) = powerbase0; -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- " [OFDM power base index rf(%c) = 0x%x]\n", -- i == 0 ? 'A' : 'B', *(ofdmbase + i)); -- } -- -- for (i = 0; i < 2; i++) { -- if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) { -- ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1]; -- powerlevel[i] += ht20_pwrdiff; -- } -- powerbase1 = powerlevel[i]; -- powerbase1 = (powerbase1 << 24) | (powerbase1 << 16) | -- (powerbase1 << 8) | powerbase1; -- *(mcsbase + i) = powerbase1; -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- " [MCS power base index rf(%c) = 0x%x]\n", -- i == 0 ? 'A' : 'B', *(mcsbase + i)); -- } --} -- --static u8 _rtl92d_phy_get_chnlgroup_bypg(u8 chnlindex) --{ -- u8 group; -- u8 channel_info[59] = { -- 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, -- 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, -- 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, -- 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, -- 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, -- 161, 163, 165 -- }; -- -- if (channel_info[chnlindex] <= 3) /* Chanel 1-3 */ -- group = 0; -- else if (channel_info[chnlindex] <= 9) /* Channel 4-9 */ -- group = 1; -- else if (channel_info[chnlindex] <= 14) /* Channel 10-14 */ -- group = 2; -- else if (channel_info[chnlindex] <= 64) -- group = 6; -- else if (channel_info[chnlindex] <= 140) -- group = 7; -- else -- group = 8; -- return group; --} -- --static void _rtl92d_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw, -- u8 channel, u8 index, -- u32 *powerbase0, -- u32 *powerbase1, -- u32 *p_outwriteval) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -- u8 i, chnlgroup = 0, pwr_diff_limit[4]; -- u32 writeval = 0, customer_limit, rf; -- -- for (rf = 0; rf < 2; rf++) { -- switch (rtlefuse->eeprom_regulatory) { -- case 0: -- chnlgroup = 0; -- writeval = rtlphy->mcs_offset -- [chnlgroup][index + -- (rf ? 8 : 0)] + ((index < 2) ? -- powerbase0[rf] : -- powerbase1[rf]); -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "RTK better performance, writeval(%c) = 0x%x\n", -- rf == 0 ? 'A' : 'B', writeval); -- break; -- case 1: -- if (rtlphy->pwrgroup_cnt == 1) -- chnlgroup = 0; -- if (rtlphy->pwrgroup_cnt >= MAX_PG_GROUP) { -- chnlgroup = _rtl92d_phy_get_chnlgroup_bypg( -- channel - 1); -- if (rtlphy->current_chan_bw == -- HT_CHANNEL_WIDTH_20) -- chnlgroup++; -- else -- chnlgroup += 4; -- writeval = rtlphy->mcs_offset -- [chnlgroup][index + -- (rf ? 8 : 0)] + ((index < 2) ? -- powerbase0[rf] : -- powerbase1[rf]); -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n", -- rf == 0 ? 'A' : 'B', writeval); -- } -- break; -- case 2: -- writeval = ((index < 2) ? powerbase0[rf] : -- powerbase1[rf]); -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "Better regulatory, writeval(%c) = 0x%x\n", -- rf == 0 ? 'A' : 'B', writeval); -- break; -- case 3: -- chnlgroup = 0; -- if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "customer's limit, 40MHz rf(%c) = 0x%x\n", -- rf == 0 ? 'A' : 'B', -- rtlefuse->pwrgroup_ht40[rf] -- [channel - 1]); -- } else { -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "customer's limit, 20MHz rf(%c) = 0x%x\n", -- rf == 0 ? 'A' : 'B', -- rtlefuse->pwrgroup_ht20[rf] -- [channel - 1]); -- } -- for (i = 0; i < 4; i++) { -- pwr_diff_limit[i] = (u8)((rtlphy->mcs_offset -- [chnlgroup][index + (rf ? 8 : 0)] & -- (0x7f << (i * 8))) >> (i * 8)); -- if (rtlphy->current_chan_bw == -- HT_CHANNEL_WIDTH_20_40) { -- if (pwr_diff_limit[i] > -- rtlefuse->pwrgroup_ht40[rf] -- [channel - 1]) -- pwr_diff_limit[i] = -- rtlefuse->pwrgroup_ht40 -- [rf][channel - 1]; -- } else { -- if (pwr_diff_limit[i] > -- rtlefuse->pwrgroup_ht20[rf][ -- channel - 1]) -- pwr_diff_limit[i] = -- rtlefuse->pwrgroup_ht20[rf] -- [channel - 1]; -- } -- } -- customer_limit = (pwr_diff_limit[3] << 24) | -- (pwr_diff_limit[2] << 16) | -- (pwr_diff_limit[1] << 8) | -- (pwr_diff_limit[0]); -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "Customer's limit rf(%c) = 0x%x\n", -- rf == 0 ? 'A' : 'B', customer_limit); -- writeval = customer_limit + ((index < 2) ? -- powerbase0[rf] : powerbase1[rf]); -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "Customer, writeval rf(%c)= 0x%x\n", -- rf == 0 ? 'A' : 'B', writeval); -- break; -- default: -- chnlgroup = 0; -- writeval = rtlphy->mcs_offset[chnlgroup][index + -- (rf ? 8 : 0)] + ((index < 2) ? -- powerbase0[rf] : powerbase1[rf]); -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "RTK better performance, writeval rf(%c) = 0x%x\n", -- rf == 0 ? 'A' : 'B', writeval); -- break; -- } -- *(p_outwriteval + rf) = writeval; -- } --} -- --static void _rtl92d_write_ofdm_power_reg(struct ieee80211_hw *hw, -- u8 index, u32 *pvalue) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- static u16 regoffset_a[6] = { -- RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24, -- RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04, -- RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12 -- }; -- static u16 regoffset_b[6] = { -- RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24, -- RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04, -- RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12 -- }; -- u8 i, rf, pwr_val[4]; -- u32 writeval; -- u16 regoffset; -- -- for (rf = 0; rf < 2; rf++) { -- writeval = pvalue[rf]; -- for (i = 0; i < 4; i++) { -- pwr_val[i] = (u8) ((writeval & (0x7f << -- (i * 8))) >> (i * 8)); -- if (pwr_val[i] > RF6052_MAX_TX_PWR) -- pwr_val[i] = RF6052_MAX_TX_PWR; -- } -- writeval = (pwr_val[3] << 24) | (pwr_val[2] << 16) | -- (pwr_val[1] << 8) | pwr_val[0]; -- if (rf == 0) -- regoffset = regoffset_a[index]; -- else -- regoffset = regoffset_b[index]; -- rtl_set_bbreg(hw, regoffset, MASKDWORD, writeval); -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "Set 0x%x = %08x\n", regoffset, writeval); -- if (((get_rf_type(rtlphy) == RF_2T2R) && -- (regoffset == RTXAGC_A_MCS15_MCS12 || -- regoffset == RTXAGC_B_MCS15_MCS12)) || -- ((get_rf_type(rtlphy) != RF_2T2R) && -- (regoffset == RTXAGC_A_MCS07_MCS04 || -- regoffset == RTXAGC_B_MCS07_MCS04))) { -- writeval = pwr_val[3]; -- if (regoffset == RTXAGC_A_MCS15_MCS12 || -- regoffset == RTXAGC_A_MCS07_MCS04) -- regoffset = 0xc90; -- if (regoffset == RTXAGC_B_MCS15_MCS12 || -- regoffset == RTXAGC_B_MCS07_MCS04) -- regoffset = 0xc98; -- for (i = 0; i < 3; i++) { -- if (i != 2) -- writeval = (writeval > 8) ? -- (writeval - 8) : 0; -- else -- writeval = (writeval > 6) ? -- (writeval - 6) : 0; -- rtl_write_byte(rtlpriv, (u32) (regoffset + i), -- (u8) writeval); -- } -- } -- } --} -- --void rtl92d_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw, -- u8 *ppowerlevel, u8 channel) --{ -- u32 writeval[2], powerbase0[2], powerbase1[2]; -- u8 index; -- -- _rtl92d_phy_get_power_base(hw, ppowerlevel, channel, -- &powerbase0[0], &powerbase1[0]); -- for (index = 0; index < 6; index++) { -- _rtl92d_get_txpower_writeval_by_regulatory(hw, -- channel, index, &powerbase0[0], -- &powerbase1[0], &writeval[0]); -- _rtl92d_write_ofdm_power_reg(hw, index, &writeval[0]); -- } --} -- - bool rtl92d_phy_enable_anotherphy(struct ieee80211_hw *hw, bool bmac0) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.h -index 4e646cc9ebc0..c097d90cc99c 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/rf.h -@@ -4,11 +4,6 @@ - #ifndef __RTL92D_RF_H__ - #define __RTL92D_RF_H__ - --void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth); --void rtl92d_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw, -- u8 *ppowerlevel); --void rtl92d_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw, -- u8 *ppowerlevel, u8 channel); - bool rtl92d_phy_rf6052_config(struct ieee80211_hw *hw); - bool rtl92d_phy_enable_anotherphy(struct ieee80211_hw *hw, bool bmac0); - void rtl92d_phy_powerdown_anotherphy(struct ieee80211_hw *hw, bool bmac0); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c -index afd685ed460a..5f6311c2aac4 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c -@@ -5,8 +5,12 @@ - #include "../core.h" - #include "../pci.h" - #include "../base.h" --#include "reg.h" --#include "def.h" -+#include "../rtl8192d/reg.h" -+#include "../rtl8192d/def.h" -+#include "../rtl8192d/dm_common.h" -+#include "../rtl8192d/hw_common.h" -+#include "../rtl8192d/phy_common.h" -+#include "../rtl8192d/trx_common.h" - #include "phy.h" - #include "dm.h" - #include "hw.h" -@@ -207,7 +211,7 @@ static struct rtl_hal_ops rtl8192de_hal_ops = { - .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking, - .set_bw_mode = rtl92d_phy_set_bw_mode, - .switch_channel = rtl92d_phy_sw_chnl, -- .dm_watchdog = rtl92d_dm_watchdog, -+ .dm_watchdog = rtl92de_dm_watchdog, - .scan_operation_backup = rtl_phy_scan_operation_backup, - .set_rf_power_state = rtl92d_phy_set_rf_power_state, - .led_control = rtl92de_led_control, -@@ -223,6 +227,8 @@ static struct rtl_hal_ops rtl8192de_hal_ops = { - .set_rfreg = rtl92d_phy_set_rf_reg, - .linked_set_reg = rtl92d_linked_set_reg, - .get_btc_status = rtl_btc_status_false, -+ .phy_iq_calibrate = rtl92d_phy_iq_calibrate, -+ .phy_lc_calibrate = rtl92d_phy_lc_calibrate, - }; - - static struct rtl_mod_params rtl92de_mod_params = { -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c -index cbc7b4dbea9a..2b9b352f7783 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c -@@ -5,8 +5,10 @@ - #include "../pci.h" - #include "../base.h" - #include "../stats.h" --#include "reg.h" --#include "def.h" -+#include "../rtl8192d/reg.h" -+#include "../rtl8192d/def.h" -+#include "../rtl8192d/phy_common.h" -+#include "../rtl8192d/trx_common.h" - #include "phy.h" - #include "trx.h" - #include "led.h" -@@ -23,433 +25,6 @@ static u8 _rtl92de_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue) - return skb->priority; - } - --static long _rtl92de_translate_todbm(struct ieee80211_hw *hw, -- u8 signal_strength_index) --{ -- long signal_power; -- -- signal_power = (long)((signal_strength_index + 1) >> 1); -- signal_power -= 95; -- return signal_power; --} -- --static void _rtl92de_query_rxphystatus(struct ieee80211_hw *hw, -- struct rtl_stats *pstats, -- __le32 *pdesc, -- struct rx_fwinfo_92d *p_drvinfo, -- bool packet_match_bssid, -- bool packet_toself, -- bool packet_beacon) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); -- struct phy_sts_cck_8192d *cck_buf; -- s8 rx_pwr_all, rx_pwr[4]; -- u8 rf_rx_num = 0, evm, pwdb_all; -- u8 i, max_spatial_stream; -- u32 rssi, total_rssi = 0; -- bool is_cck_rate; -- u8 rxmcs; -- -- rxmcs = get_rx_desc_rxmcs(pdesc); -- is_cck_rate = rxmcs <= DESC_RATE11M; -- pstats->packet_matchbssid = packet_match_bssid; -- pstats->packet_toself = packet_toself; -- pstats->packet_beacon = packet_beacon; -- pstats->is_cck = is_cck_rate; -- pstats->rx_mimo_sig_qual[0] = -1; -- pstats->rx_mimo_sig_qual[1] = -1; -- -- if (is_cck_rate) { -- u8 report, cck_highpwr; -- cck_buf = (struct phy_sts_cck_8192d *)p_drvinfo; -- if (ppsc->rfpwr_state == ERFON) -- cck_highpwr = rtlphy->cck_high_power; -- else -- cck_highpwr = false; -- if (!cck_highpwr) { -- u8 cck_agc_rpt = cck_buf->cck_agc_rpt; -- report = cck_buf->cck_agc_rpt & 0xc0; -- report = report >> 6; -- switch (report) { -- case 0x3: -- rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); -- break; -- case 0x2: -- rx_pwr_all = -26 - (cck_agc_rpt & 0x3e); -- break; -- case 0x1: -- rx_pwr_all = -12 - (cck_agc_rpt & 0x3e); -- break; -- case 0x0: -- rx_pwr_all = 16 - (cck_agc_rpt & 0x3e); -- break; -- } -- } else { -- u8 cck_agc_rpt = cck_buf->cck_agc_rpt; -- report = p_drvinfo->cfosho[0] & 0x60; -- report = report >> 5; -- switch (report) { -- case 0x3: -- rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1); -- break; -- case 0x2: -- rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1); -- break; -- case 0x1: -- rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1); -- break; -- case 0x0: -- rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1); -- break; -- } -- } -- pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all); -- /* CCK gain is smaller than OFDM/MCS gain, */ -- /* so we add gain diff by experiences, the val is 6 */ -- pwdb_all += 6; -- if (pwdb_all > 100) -- pwdb_all = 100; -- /* modify the offset to make the same gain index with OFDM. */ -- if (pwdb_all > 34 && pwdb_all <= 42) -- pwdb_all -= 2; -- else if (pwdb_all > 26 && pwdb_all <= 34) -- pwdb_all -= 6; -- else if (pwdb_all > 14 && pwdb_all <= 26) -- pwdb_all -= 8; -- else if (pwdb_all > 4 && pwdb_all <= 14) -- pwdb_all -= 4; -- pstats->rx_pwdb_all = pwdb_all; -- pstats->recvsignalpower = rx_pwr_all; -- if (packet_match_bssid) { -- u8 sq; -- if (pstats->rx_pwdb_all > 40) { -- sq = 100; -- } else { -- sq = cck_buf->sq_rpt; -- if (sq > 64) -- sq = 0; -- else if (sq < 20) -- sq = 100; -- else -- sq = ((64 - sq) * 100) / 44; -- } -- pstats->signalquality = sq; -- pstats->rx_mimo_sig_qual[0] = sq; -- pstats->rx_mimo_sig_qual[1] = -1; -- } -- } else { -- rtlpriv->dm.rfpath_rxenable[0] = true; -- rtlpriv->dm.rfpath_rxenable[1] = true; -- for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) { -- if (rtlpriv->dm.rfpath_rxenable[i]) -- rf_rx_num++; -- rx_pwr[i] = ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) -- - 110; -- rssi = rtl_query_rxpwrpercentage(rx_pwr[i]); -- total_rssi += rssi; -- rtlpriv->stats.rx_snr_db[i] = -- (long)(p_drvinfo->rxsnr[i] / 2); -- if (packet_match_bssid) -- pstats->rx_mimo_signalstrength[i] = (u8) rssi; -- } -- rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 106; -- pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all); -- pstats->rx_pwdb_all = pwdb_all; -- pstats->rxpower = rx_pwr_all; -- pstats->recvsignalpower = rx_pwr_all; -- if (get_rx_desc_rxht(pdesc) && rxmcs >= DESC_RATEMCS8 && -- rxmcs <= DESC_RATEMCS15) -- max_spatial_stream = 2; -- else -- max_spatial_stream = 1; -- for (i = 0; i < max_spatial_stream; i++) { -- evm = rtl_evm_db_to_percentage(p_drvinfo->rxevm[i]); -- if (packet_match_bssid) { -- if (i == 0) -- pstats->signalquality = -- (u8)(evm & 0xff); -- pstats->rx_mimo_sig_qual[i] = -- (u8)(evm & 0xff); -- } -- } -- } -- if (is_cck_rate) -- pstats->signalstrength = (u8)(rtl_signal_scale_mapping(hw, -- pwdb_all)); -- else if (rf_rx_num != 0) -- pstats->signalstrength = (u8)(rtl_signal_scale_mapping(hw, -- total_rssi /= rf_rx_num)); --} -- --static void rtl92d_loop_over_paths(struct ieee80211_hw *hw, -- struct rtl_stats *pstats) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_phy *rtlphy = &(rtlpriv->phy); -- u8 rfpath; -- -- for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; -- rfpath++) { -- if (rtlpriv->stats.rx_rssi_percentage[rfpath] == 0) { -- rtlpriv->stats.rx_rssi_percentage[rfpath] = -- pstats->rx_mimo_signalstrength[rfpath]; -- -- } -- if (pstats->rx_mimo_signalstrength[rfpath] > -- rtlpriv->stats.rx_rssi_percentage[rfpath]) { -- rtlpriv->stats.rx_rssi_percentage[rfpath] = -- ((rtlpriv->stats.rx_rssi_percentage[rfpath] * -- (RX_SMOOTH_FACTOR - 1)) + -- (pstats->rx_mimo_signalstrength[rfpath])) / -- (RX_SMOOTH_FACTOR); -- rtlpriv->stats.rx_rssi_percentage[rfpath] = -- rtlpriv->stats.rx_rssi_percentage[rfpath] + 1; -- } else { -- rtlpriv->stats.rx_rssi_percentage[rfpath] = -- ((rtlpriv->stats.rx_rssi_percentage[rfpath] * -- (RX_SMOOTH_FACTOR - 1)) + -- (pstats->rx_mimo_signalstrength[rfpath])) / -- (RX_SMOOTH_FACTOR); -- } -- } --} -- --static void _rtl92de_process_ui_rssi(struct ieee80211_hw *hw, -- struct rtl_stats *pstats) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u32 last_rssi, tmpval; -- -- if (pstats->packet_toself || pstats->packet_beacon) { -- rtlpriv->stats.rssi_calculate_cnt++; -- if (rtlpriv->stats.ui_rssi.total_num++ >= -- PHY_RSSI_SLID_WIN_MAX) { -- rtlpriv->stats.ui_rssi.total_num = -- PHY_RSSI_SLID_WIN_MAX; -- last_rssi = rtlpriv->stats.ui_rssi.elements[ -- rtlpriv->stats.ui_rssi.index]; -- rtlpriv->stats.ui_rssi.total_val -= last_rssi; -- } -- rtlpriv->stats.ui_rssi.total_val += pstats->signalstrength; -- rtlpriv->stats.ui_rssi.elements -- [rtlpriv->stats.ui_rssi.index++] = -- pstats->signalstrength; -- if (rtlpriv->stats.ui_rssi.index >= PHY_RSSI_SLID_WIN_MAX) -- rtlpriv->stats.ui_rssi.index = 0; -- tmpval = rtlpriv->stats.ui_rssi.total_val / -- rtlpriv->stats.ui_rssi.total_num; -- rtlpriv->stats.signal_strength = _rtl92de_translate_todbm(hw, -- (u8) tmpval); -- pstats->rssi = rtlpriv->stats.signal_strength; -- } -- if (!pstats->is_cck && pstats->packet_toself) -- rtl92d_loop_over_paths(hw, pstats); --} -- --static void _rtl92de_update_rxsignalstatistics(struct ieee80211_hw *hw, -- struct rtl_stats *pstats) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- int weighting = 0; -- -- if (rtlpriv->stats.recv_signal_power == 0) -- rtlpriv->stats.recv_signal_power = pstats->recvsignalpower; -- if (pstats->recvsignalpower > rtlpriv->stats.recv_signal_power) -- weighting = 5; -- else if (pstats->recvsignalpower < rtlpriv->stats.recv_signal_power) -- weighting = (-5); -- rtlpriv->stats.recv_signal_power = (rtlpriv->stats.recv_signal_power * -- 5 + pstats->recvsignalpower + weighting) / 6; --} -- --static void _rtl92de_process_pwdb(struct ieee80211_hw *hw, -- struct rtl_stats *pstats) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -- long undec_sm_pwdb; -- -- if (mac->opmode == NL80211_IFTYPE_ADHOC || -- mac->opmode == NL80211_IFTYPE_AP) -- return; -- else -- undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb; -- -- if (pstats->packet_toself || pstats->packet_beacon) { -- if (undec_sm_pwdb < 0) -- undec_sm_pwdb = pstats->rx_pwdb_all; -- if (pstats->rx_pwdb_all > (u32) undec_sm_pwdb) { -- undec_sm_pwdb = (((undec_sm_pwdb) * -- (RX_SMOOTH_FACTOR - 1)) + -- (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); -- undec_sm_pwdb = undec_sm_pwdb + 1; -- } else { -- undec_sm_pwdb = (((undec_sm_pwdb) * -- (RX_SMOOTH_FACTOR - 1)) + -- (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); -- } -- rtlpriv->dm.undec_sm_pwdb = undec_sm_pwdb; -- _rtl92de_update_rxsignalstatistics(hw, pstats); -- } --} -- --static void rtl92d_loop_over_streams(struct ieee80211_hw *hw, -- struct rtl_stats *pstats) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- int stream; -- -- for (stream = 0; stream < 2; stream++) { -- if (pstats->rx_mimo_sig_qual[stream] != -1) { -- if (rtlpriv->stats.rx_evm_percentage[stream] == 0) { -- rtlpriv->stats.rx_evm_percentage[stream] = -- pstats->rx_mimo_sig_qual[stream]; -- } -- rtlpriv->stats.rx_evm_percentage[stream] = -- ((rtlpriv->stats.rx_evm_percentage[stream] -- * (RX_SMOOTH_FACTOR - 1)) + -- (pstats->rx_mimo_sig_qual[stream] * 1)) / -- (RX_SMOOTH_FACTOR); -- } -- } --} -- --static void _rtl92de_process_ui_link_quality(struct ieee80211_hw *hw, -- struct rtl_stats *pstats) --{ -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- u32 last_evm, tmpval; -- -- if (pstats->signalquality == 0) -- return; -- if (pstats->packet_toself || pstats->packet_beacon) { -- if (rtlpriv->stats.ui_link_quality.total_num++ >= -- PHY_LINKQUALITY_SLID_WIN_MAX) { -- rtlpriv->stats.ui_link_quality.total_num = -- PHY_LINKQUALITY_SLID_WIN_MAX; -- last_evm = rtlpriv->stats.ui_link_quality.elements[ -- rtlpriv->stats.ui_link_quality.index]; -- rtlpriv->stats.ui_link_quality.total_val -= last_evm; -- } -- rtlpriv->stats.ui_link_quality.total_val += -- pstats->signalquality; -- rtlpriv->stats.ui_link_quality.elements[ -- rtlpriv->stats.ui_link_quality.index++] = -- pstats->signalquality; -- if (rtlpriv->stats.ui_link_quality.index >= -- PHY_LINKQUALITY_SLID_WIN_MAX) -- rtlpriv->stats.ui_link_quality.index = 0; -- tmpval = rtlpriv->stats.ui_link_quality.total_val / -- rtlpriv->stats.ui_link_quality.total_num; -- rtlpriv->stats.signal_quality = tmpval; -- rtlpriv->stats.last_sigstrength_inpercent = tmpval; -- rtl92d_loop_over_streams(hw, pstats); -- } --} -- --static void _rtl92de_process_phyinfo(struct ieee80211_hw *hw, -- u8 *buffer, -- struct rtl_stats *pcurrent_stats) --{ -- -- if (!pcurrent_stats->packet_matchbssid && -- !pcurrent_stats->packet_beacon) -- return; -- -- _rtl92de_process_ui_rssi(hw, pcurrent_stats); -- _rtl92de_process_pwdb(hw, pcurrent_stats); -- _rtl92de_process_ui_link_quality(hw, pcurrent_stats); --} -- --static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw, -- struct sk_buff *skb, -- struct rtl_stats *pstats, -- __le32 *pdesc, -- struct rx_fwinfo_92d *p_drvinfo) --{ -- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -- struct ieee80211_hdr *hdr; -- u8 *tmp_buf; -- u8 *praddr; -- u16 type, cfc; -- __le16 fc; -- bool packet_matchbssid, packet_toself, packet_beacon = false; -- -- tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift; -- hdr = (struct ieee80211_hdr *)tmp_buf; -- fc = hdr->frame_control; -- cfc = le16_to_cpu(fc); -- type = WLAN_FC_GET_TYPE(fc); -- praddr = hdr->addr1; -- packet_matchbssid = ((IEEE80211_FTYPE_CTL != type) && -- ether_addr_equal(mac->bssid, -- (cfc & IEEE80211_FCTL_TODS) ? hdr->addr1 : -- (cfc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 : -- hdr->addr3) && -- (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv)); -- packet_toself = packet_matchbssid && -- ether_addr_equal(praddr, rtlefuse->dev_addr); -- if (ieee80211_is_beacon(fc)) -- packet_beacon = true; -- _rtl92de_query_rxphystatus(hw, pstats, pdesc, p_drvinfo, -- packet_matchbssid, packet_toself, -- packet_beacon); -- _rtl92de_process_phyinfo(hw, tmp_buf, pstats); --} -- --bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, -- struct ieee80211_rx_status *rx_status, -- u8 *pdesc8, struct sk_buff *skb) --{ -- __le32 *pdesc = (__le32 *)pdesc8; -- struct rx_fwinfo_92d *p_drvinfo; -- u32 phystatus = get_rx_desc_physt(pdesc); -- -- stats->length = (u16)get_rx_desc_pkt_len(pdesc); -- stats->rx_drvinfo_size = (u8)get_rx_desc_drv_info_size(pdesc) * -- RX_DRV_INFO_SIZE_UNIT; -- stats->rx_bufshift = (u8)(get_rx_desc_shift(pdesc) & 0x03); -- stats->icv = (u16)get_rx_desc_icv(pdesc); -- stats->crc = (u16)get_rx_desc_crc32(pdesc); -- stats->hwerror = (stats->crc | stats->icv); -- stats->decrypted = !get_rx_desc_swdec(pdesc) && -- get_rx_desc_enc_type(pdesc) != RX_DESC_ENC_NONE; -- stats->rate = (u8)get_rx_desc_rxmcs(pdesc); -- stats->shortpreamble = (u16)get_rx_desc_splcp(pdesc); -- stats->isampdu = (bool)(get_rx_desc_paggr(pdesc) == 1); -- stats->isfirst_ampdu = (bool)((get_rx_desc_paggr(pdesc) == 1) && -- (get_rx_desc_faggr(pdesc) == 1)); -- stats->timestamp_low = get_rx_desc_tsfl(pdesc); -- stats->rx_is40mhzpacket = (bool)get_rx_desc_bw(pdesc); -- stats->is_ht = (bool)get_rx_desc_rxht(pdesc); -- rx_status->freq = hw->conf.chandef.chan->center_freq; -- rx_status->band = hw->conf.chandef.chan->band; -- if (get_rx_desc_crc32(pdesc)) -- rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; -- if (get_rx_desc_bw(pdesc)) -- rx_status->bw = RATE_INFO_BW_40; -- if (get_rx_desc_rxht(pdesc)) -- rx_status->encoding = RX_ENC_HT; -- rx_status->flag |= RX_FLAG_MACTIME_START; -- if (stats->decrypted) -- rx_status->flag |= RX_FLAG_DECRYPTED; -- rx_status->rate_idx = rtlwifi_rate_mapping(hw, stats->is_ht, -- false, stats->rate); -- rx_status->mactime = get_rx_desc_tsfl(pdesc); -- if (phystatus) { -- p_drvinfo = (struct rx_fwinfo_92d *)(skb->data + -- stats->rx_bufshift); -- _rtl92de_translate_rx_signal_stuff(hw, skb, stats, pdesc, -- p_drvinfo); -- } -- /*rx_status->qual = stats->signal; */ -- rx_status->signal = stats->recvsignalpower + 10; -- return true; --} -- - static void _rtl92de_insert_emcontent(struct rtl_tcb_desc *ptcb_desc, - u8 *virtualaddress8) - { -@@ -711,87 +286,6 @@ void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc8, - set_tx_desc_own(pdesc, 1); - } - --void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc8, bool istx, -- u8 desc_name, u8 *val) --{ -- __le32 *pdesc = (__le32 *)pdesc8; -- -- if (istx) { -- switch (desc_name) { -- case HW_DESC_OWN: -- wmb(); -- set_tx_desc_own(pdesc, 1); -- break; -- case HW_DESC_TX_NEXTDESC_ADDR: -- set_tx_desc_next_desc_address(pdesc, *(u32 *)val); -- break; -- default: -- WARN_ONCE(true, "rtl8192de: ERR txdesc :%d not processed\n", -- desc_name); -- break; -- } -- } else { -- switch (desc_name) { -- case HW_DESC_RXOWN: -- wmb(); -- set_rx_desc_own(pdesc, 1); -- break; -- case HW_DESC_RXBUFF_ADDR: -- set_rx_desc_buff_addr(pdesc, *(u32 *)val); -- break; -- case HW_DESC_RXPKT_LEN: -- set_rx_desc_pkt_len(pdesc, *(u32 *)val); -- break; -- case HW_DESC_RXERO: -- set_rx_desc_eor(pdesc, 1); -- break; -- default: -- WARN_ONCE(true, "rtl8192de: ERR rxdesc :%d not processed\n", -- desc_name); -- break; -- } -- } --} -- --u64 rtl92de_get_desc(struct ieee80211_hw *hw, -- u8 *p_desc8, bool istx, u8 desc_name) --{ -- __le32 *p_desc = (__le32 *)p_desc8; -- u32 ret = 0; -- -- if (istx) { -- switch (desc_name) { -- case HW_DESC_OWN: -- ret = get_tx_desc_own(p_desc); -- break; -- case HW_DESC_TXBUFF_ADDR: -- ret = get_tx_desc_tx_buffer_address(p_desc); -- break; -- default: -- WARN_ONCE(true, "rtl8192de: ERR txdesc :%d not processed\n", -- desc_name); -- break; -- } -- } else { -- switch (desc_name) { -- case HW_DESC_OWN: -- ret = get_rx_desc_own(p_desc); -- break; -- case HW_DESC_RXPKT_LEN: -- ret = get_rx_desc_pkt_len(p_desc); -- break; -- case HW_DESC_RXBUFF_ADDR: -- ret = get_rx_desc_buff_addr(p_desc); -- break; -- default: -- WARN_ONCE(true, "rtl8192de: ERR rxdesc :%d not processed\n", -- desc_name); -- break; -- } -- } -- return ret; --} -- - bool rtl92de_is_tx_desc_closed(struct ieee80211_hw *hw, - u8 hw_queue, u16 index) - { -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h -index 2d4887490f00..d3c480c75678 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h -@@ -8,405 +8,17 @@ - #define TX_DESC_AGGR_SUBFRAME_SIZE 32 - - #define RX_DESC_SIZE 32 --#define RX_DRV_INFO_SIZE_UNIT 8 - - #define TX_DESC_NEXT_DESC_OFFSET 40 - #define USB_HWDESC_HEADER_LEN 32 - #define CRCLENGTH 4 - --enum rtl92d_rx_desc_enc { -- RX_DESC_ENC_NONE = 0, -- RX_DESC_ENC_WEP40 = 1, -- RX_DESC_ENC_TKIP_WO_MIC = 2, -- RX_DESC_ENC_TKIP_MIC = 3, -- RX_DESC_ENC_AES = 4, -- RX_DESC_ENC_WEP104 = 5, --}; -- --/* macros to read/write various fields in RX or TX descriptors */ -- --static inline void set_tx_desc_pkt_size(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits(__pdesc, __val, GENMASK(15, 0)); --} -- --static inline void set_tx_desc_offset(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits(__pdesc, __val, GENMASK(23, 16)); --} -- --static inline void set_tx_desc_htc(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits(__pdesc, __val, BIT(25)); --} -- --static inline void set_tx_desc_last_seg(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits(__pdesc, __val, BIT(26)); --} -- --static inline void set_tx_desc_first_seg(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits(__pdesc, __val, BIT(27)); --} -- --static inline void set_tx_desc_linip(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits(__pdesc, __val, BIT(28)); --} -- --static inline void set_tx_desc_own(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits(__pdesc, __val, BIT(31)); --} -- --static inline u32 get_tx_desc_own(__le32 *__pdesc) --{ -- return le32_get_bits(*__pdesc, BIT(31)); --} -- --static inline void set_tx_desc_macid(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0)); --} -- --static inline void set_tx_desc_agg_enable(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 1), __val, BIT(5)); --} -- --static inline void set_tx_desc_rdg_enable(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 1), __val, BIT(7)); --} -- --static inline void set_tx_desc_queue_sel(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8)); --} -- --static inline void set_tx_desc_rate_id(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 1), __val, GENMASK(19, 16)); --} -- --static inline void set_tx_desc_sec_type(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22)); --} -- --static inline void set_tx_desc_pkt_offset(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 1), __val, GENMASK(30, 26)); --} -- --static inline void set_tx_desc_more_frag(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 2), __val, BIT(17)); --} -- --static inline void set_tx_desc_ampdu_density(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 2), __val, GENMASK(22, 20)); --} -- --static inline void set_tx_desc_seq(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16)); --} -- --static inline void set_tx_desc_pkt_id(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 3), __val, GENMASK(31, 28)); --} -- --static inline void set_tx_desc_rts_rate(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 4), __val, GENMASK(4, 0)); --} -- --static inline void set_tx_desc_qos(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 4), __val, BIT(6)); --} -- --static inline void set_tx_desc_hwseq_en(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 4), __val, BIT(7)); --} -- --static inline void set_tx_desc_use_rate(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 4), __val, BIT(8)); --} -- --static inline void set_tx_desc_disable_fb(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 4), __val, BIT(10)); --} -- --static inline void set_tx_desc_cts2self(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 4), __val, BIT(11)); --} -- --static inline void set_tx_desc_rts_enable(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 4), __val, BIT(12)); --} -- --static inline void set_tx_desc_hw_rts_enable(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 4), __val, BIT(13)); --} -- --static inline void set_tx_desc_tx_sub_carrier(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 4), __val, GENMASK(21, 20)); --} -- --static inline void set_tx_desc_data_bw(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 4), __val, BIT(25)); --} -- --static inline void set_tx_desc_rts_short(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 4), __val, BIT(26)); --} -- --static inline void set_tx_desc_rts_bw(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 4), __val, BIT(27)); --} -- --static inline void set_tx_desc_rts_sc(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 4), __val, GENMASK(29, 28)); --} -- --static inline void set_tx_desc_rts_stbc(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 4), __val, GENMASK(31, 30)); --} -- --static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 5), __val, GENMASK(5, 0)); --} -- --static inline void set_tx_desc_data_shortgi(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 5), __val, BIT(6)); --} -- --static inline void set_tx_desc_data_rate_fb_limit(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 5), __val, GENMASK(12, 8)); --} -- --static inline void set_tx_desc_rts_rate_fb_limit(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 5), __val, GENMASK(16, 13)); --} -- --static inline void set_tx_desc_max_agg_num(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 6), __val, GENMASK(15, 11)); --} -- --static inline void set_tx_desc_tx_buffer_size(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0)); --} -- --static inline void set_tx_desc_tx_buffer_address(__le32 *__pdesc, u32 __val) --{ -- *(__pdesc + 8) = cpu_to_le32(__val); --} -- --static inline u32 get_tx_desc_tx_buffer_address(__le32 *__pdesc) --{ -- return le32_to_cpu(*(__pdesc + 8)); --} -- --static inline void set_tx_desc_next_desc_address(__le32 *__pdesc, u32 __val) --{ -- *(__pdesc + 10) = cpu_to_le32(__val); --} -- --static inline u32 get_rx_desc_pkt_len(__le32 *__pdesc) --{ -- return le32_get_bits(*__pdesc, GENMASK(13, 0)); --} -- --static inline u32 get_rx_desc_crc32(__le32 *__pdesc) --{ -- return le32_get_bits(*__pdesc, BIT(14)); --} -- --static inline u32 get_rx_desc_icv(__le32 *__pdesc) --{ -- return le32_get_bits(*__pdesc, BIT(15)); --} -- --static inline u32 get_rx_desc_drv_info_size(__le32 *__pdesc) --{ -- return le32_get_bits(*__pdesc, GENMASK(19, 16)); --} -- --static inline u32 get_rx_desc_enc_type(__le32 *__pdesc) --{ -- return le32_get_bits(*__pdesc, GENMASK(22, 20)); --} -- --static inline u32 get_rx_desc_shift(__le32 *__pdesc) --{ -- return le32_get_bits(*__pdesc, GENMASK(25, 24)); --} -- --static inline u32 get_rx_desc_physt(__le32 *__pdesc) --{ -- return le32_get_bits(*__pdesc, BIT(26)); --} -- --static inline u32 get_rx_desc_swdec(__le32 *__pdesc) --{ -- return le32_get_bits(*__pdesc, BIT(27)); --} -- --static inline u32 get_rx_desc_own(__le32 *__pdesc) --{ -- return le32_get_bits(*__pdesc, BIT(31)); --} -- --static inline void set_rx_desc_pkt_len(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits(__pdesc, __val, GENMASK(13, 0)); --} -- --static inline void set_rx_desc_eor(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits(__pdesc, __val, BIT(30)); --} -- --static inline void set_rx_desc_own(__le32 *__pdesc, u32 __val) --{ -- le32p_replace_bits(__pdesc, __val, BIT(31)); --} -- --static inline u32 get_rx_desc_paggr(__le32 *__pdesc) --{ -- return le32_get_bits(*(__pdesc + 1), BIT(14)); --} -- --static inline u32 get_rx_desc_faggr(__le32 *__pdesc) --{ -- return le32_get_bits(*(__pdesc + 1), BIT(15)); --} -- --static inline u32 get_rx_desc_rxmcs(__le32 *__pdesc) --{ -- return le32_get_bits(*(__pdesc + 3), GENMASK(5, 0)); --} -- --static inline u32 get_rx_desc_rxht(__le32 *__pdesc) --{ -- return le32_get_bits(*(__pdesc + 3), BIT(6)); --} -- --static inline u32 get_rx_desc_splcp(__le32 *__pdesc) --{ -- return le32_get_bits(*(__pdesc + 3), BIT(8)); --} -- --static inline u32 get_rx_desc_bw(__le32 *__pdesc) --{ -- return le32_get_bits(*(__pdesc + 3), BIT(9)); --} -- --static inline u32 get_rx_desc_tsfl(__le32 *__pdesc) --{ -- return le32_to_cpu(*(__pdesc + 5)); --} -- --static inline u32 get_rx_desc_buff_addr(__le32 *__pdesc) --{ -- return le32_to_cpu(*(__pdesc + 6)); --} -- --static inline void set_rx_desc_buff_addr(__le32 *__pdesc, u32 __val) --{ -- *(__pdesc + 6) = cpu_to_le32(__val); --} -- - static inline void clear_pci_tx_desc_content(__le32 *__pdesc, u32 _size) - { - memset((void *)__pdesc, 0, - min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET)); - } - --/* For 92D early mode */ --static inline void set_earlymode_pktnum(__le32 *__paddr, u32 __value) --{ -- le32p_replace_bits(__paddr, __value, GENMASK(2, 0)); --} -- --static inline void set_earlymode_len0(__le32 *__paddr, u32 __value) --{ -- le32p_replace_bits(__paddr, __value, GENMASK(15, 4)); --} -- --static inline void set_earlymode_len1(__le32 *__paddr, u32 __value) --{ -- le32p_replace_bits(__paddr, __value, GENMASK(27, 16)); --} -- --static inline void set_earlymode_len2_1(__le32 *__paddr, u32 __value) --{ -- le32p_replace_bits(__paddr, __value, GENMASK(31, 28)); --} -- --static inline void set_earlymode_len2_2(__le32 *__paddr, u32 __value) --{ -- le32p_replace_bits((__paddr + 1), __value, GENMASK(7, 0)); --} -- --static inline void set_earlymode_len3(__le32 *__paddr, u32 __value) --{ -- le32p_replace_bits((__paddr + 1), __value, GENMASK(19, 8)); --} -- --static inline void set_earlymode_len4(__le32 *__paddr, u32 __value) --{ -- le32p_replace_bits((__paddr + 1), __value, GENMASK(31, 20)); --} -- --struct rx_fwinfo_92d { -- u8 gain_trsw[4]; -- u8 pwdb_all; -- u8 cfosho[4]; -- u8 cfotail[4]; -- s8 rxevm[2]; -- s8 rxsnr[4]; -- u8 pdsnr[2]; -- u8 csi_current[2]; -- u8 csi_target[2]; -- u8 sigevm; -- u8 max_ex_pwr; --#ifdef __LITTLE_ENDIAN -- u8 ex_intf_flag:1; -- u8 sgi_en:1; -- u8 rxsc:2; -- u8 reserve:4; --#else -- u8 reserve:4; -- u8 rxsc:2; -- u8 sgi_en:1; -- u8 ex_intf_flag:1; --#endif --} __packed; -- - struct tx_desc_92d { - u32 pktsize:16; - u32 offset:8; -@@ -515,14 +127,6 @@ void rtl92de_tx_fill_desc(struct ieee80211_hw *hw, - struct ieee80211_sta *sta, - struct sk_buff *skb, u8 hw_queue, - struct rtl_tcb_desc *ptcb_desc); --bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, -- struct rtl_stats *stats, -- struct ieee80211_rx_status *rx_status, -- u8 *pdesc, struct sk_buff *skb); --void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, -- u8 desc_name, u8 *val); --u64 rtl92de_get_desc(struct ieee80211_hw *hw, -- u8 *p_desc, bool istx, u8 desc_name); - bool rtl92de_is_tx_desc_closed(struct ieee80211_hw *hw, - u8 hw_queue, u16 index); - void rtl92de_tx_polling(struct ieee80211_hw *hw, u8 hw_queue); -diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h -index 9fabf597cfd6..098db85e381c 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/wifi.h -+++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h -@@ -2268,6 +2268,7 @@ struct rtl_hal_ops { - bool (*config_bb_with_pgheaderfile)(struct ieee80211_hw *hw, - u8 configtype); - void (*phy_lc_calibrate)(struct ieee80211_hw *hw, bool is2t); -+ void (*phy_iq_calibrate)(struct ieee80211_hw *hw); - void (*phy_set_bw_mode_callback)(struct ieee80211_hw *hw); - void (*dm_dynamic_txpower)(struct ieee80211_hw *hw); - void (*c2h_command_handle)(struct ieee80211_hw *hw); --- -2.34.1 - diff --git a/packages/linux/patches/rtlwifi/6.10/0005-6.10-wifi-rtlwifi-Clean-up-rtl8192d-common-a.patch b/packages/linux/patches/rtlwifi/6.10/0005-6.10-wifi-rtlwifi-Clean-up-rtl8192d-common-a.patch deleted file mode 100644 index 533ccb5879..0000000000 --- a/packages/linux/patches/rtlwifi/6.10/0005-6.10-wifi-rtlwifi-Clean-up-rtl8192d-common-a.patch +++ /dev/null @@ -1,1749 +0,0 @@ -From 01596bb6b5fa383bd37590981b6cf660ad5d51f4 Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 25 Apr 2024 21:14:35 +0300 -Subject: [PATCH 05/07] 6.10: wifi: rtlwifi: Clean up rtl8192d-common - a bit - -Improve readability: - * add empty lines - * use abs_diff in rtl92d_dm_txpower_tracking_callback_thermalmeter - * roll up repeated statements into a for loop in - rtl92d_dm_txpower_tracking_callback_thermalmeter - * shorten lines by replacing many instances of "rtlpriv->dm" with "dm" - pointer in rtl92d_dm_txpower_tracking_callback_thermalmeter - * sort some declarations by length - * refactor _rtl92d_get_txpower_writeval_by_regulatory a little - * refactor _rtl92de_readpowervalue_fromprom a little - -Delete unused structs tag_dynamic_init_gain_operation_type_definition -and swat. - -Simplify rtl92d_fill_h2c_cmd a little and delete a pointless wrapper -function. - -Tested with a single MAC single PHY USB dongle from Aliexpress labelled -"CC&C WL-6210-V3". - -Signed-off-by: Bitterblue Smith -Acked-by: Ping-Ke Shih -Signed-off-by: Ping-Ke Shih -Link: https://msgid.link/f6acfa78-2f4e-47f1-95d4-65aa77510113@gmail.com ---- - .../realtek/rtlwifi/rtl8192d/dm_common.c | 368 +++++++++--------- - .../realtek/rtlwifi/rtl8192d/dm_common.h | 21 - - .../realtek/rtlwifi/rtl8192d/fw_common.c | 132 +++---- - .../realtek/rtlwifi/rtl8192d/hw_common.c | 179 +++++---- - .../realtek/rtlwifi/rtl8192d/phy_common.c | 24 +- - .../wireless/realtek/rtlwifi/rtl8192d/reg.h | 2 + - .../realtek/rtlwifi/rtl8192d/rf_common.c | 156 ++++---- - .../realtek/rtlwifi/rtl8192d/trx_common.c | 11 +- - 8 files changed, 422 insertions(+), 471 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.c -index d376e4584454..20373ce998bf 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.c -@@ -9,8 +9,6 @@ - #include "phy_common.h" - #include "dm_common.h" - --#define UNDEC_SM_PWDB entry_min_undec_sm_pwdb -- - static const u32 ofdmswing_table[OFDM_TABLE_SIZE_92D] = { - 0x7f8001fe, /* 0, +6.0dB */ - 0x788001e2, /* 1, +5.5dB */ -@@ -137,16 +135,18 @@ static void rtl92d_dm_rxgain_tracking_thermalmeter(struct ieee80211_hw *hw) - 0x05, 0x04, 0x04, 0x03, 0x02 - }; - struct rtl_priv *rtlpriv = rtl_priv(hw); -+ int i, idx; - u32 u4tmp; -- int i; - -- u4tmp = (index_mapping[(rtlpriv->efuse.eeprom_thermalmeter - -- rtlpriv->dm.thermalvalue_rxgain)]) << 12; -+ idx = rtlpriv->efuse.eeprom_thermalmeter - rtlpriv->dm.thermalvalue_rxgain; -+ u4tmp = index_mapping[idx] << 12; -+ - rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, - "===> Rx Gain %x\n", u4tmp); -+ - for (i = RF90_PATH_A; i < rtlpriv->phy.num_total_rfpath; i++) - rtl_set_rfreg(hw, i, 0x3C, RFREG_OFFSET_MASK, -- (rtlpriv->phy.reg_rf3c[i] & (~(0xF000))) | u4tmp); -+ (rtlpriv->phy.reg_rf3c[i] & ~0xF000) | u4tmp); - } - - static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg, -@@ -163,6 +163,7 @@ static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg, - temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2, - MASKDWORD) & MASKCCK; - rtl92d_release_cckandrw_pagea_ctl(hw, &flag); -+ - for (i = 0; i < CCK_TABLE_LENGTH; i++) { - if (rtlpriv->dm.cck_inch14) - cckswing = &cckswing_table_ch14[i][2]; -@@ -199,6 +200,7 @@ static void rtl92d_bandtype_5G(struct rtl_hal *rtlhal, u8 *ofdm_index, - *internal_pa = rtlefuse->internal_pa_5g[1]; - else - *internal_pa = rtlefuse->internal_pa_5g[i]; -+ - if (*internal_pa) { - if (rtlhal->interfaceindex == 1 || i == rf) - offset = 4; -@@ -213,8 +215,10 @@ static void rtl92d_bandtype_5G(struct rtl_hal *rtlhal, u8 *ofdm_index, - else - offset = 0; - } -+ - if (thermalvalue > rtlefuse->eeprom_thermalmeter) - offset++; -+ - if (*internal_pa) { - if (delta > INDEX_MAPPING_NUM - 1) - index = index_mapping_pa[offset] -@@ -229,6 +233,7 @@ static void rtl92d_bandtype_5G(struct rtl_hal *rtlhal, u8 *ofdm_index, - else - index = index_mapping[offset][delta]; - } -+ - if (thermalvalue > rtlefuse->eeprom_thermalmeter) { - if (*internal_pa && thermalvalue > 0x12) { - ofdm_index[i] = rtlpriv->dm.ofdm_index[i] - -@@ -247,62 +252,67 @@ rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) - { - static const u8 index_mapping[5][INDEX_MAPPING_NUM] = { - /* 5G, path A/MAC 0, decrease power */ -- {0, 1, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, -+ {0, 1, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, - /* 5G, path A/MAC 0, increase power */ -- {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, -+ {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, - /* 5G, path B/MAC 1, decrease power */ -- {0, 2, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, -+ {0, 2, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18}, - /* 5G, path B/MAC 1, increase power */ -- {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, -+ {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, - /* 2.4G, for decreas power */ -- {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10}, -+ {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10}, - }; - static const u8 index_mapping_internal_pa[8][INDEX_MAPPING_NUM] = { - /* 5G, path A/MAC 0, ch36-64, decrease power */ -- {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, -+ {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, - /* 5G, path A/MAC 0, ch36-64, increase power */ -- {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, -+ {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, - /* 5G, path A/MAC 0, ch100-165, decrease power */ -- {0, 1, 2, 3, 5, 6, 8, 10, 11, 13, 14, 15, 15}, -+ {0, 1, 2, 3, 5, 6, 8, 10, 11, 13, 14, 15, 15}, - /* 5G, path A/MAC 0, ch100-165, increase power */ -- {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, -+ {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18}, - /* 5G, path B/MAC 1, ch36-64, decrease power */ -- {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, -+ {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16}, - /* 5G, path B/MAC 1, ch36-64, increase power */ -- {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, -+ {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, - /* 5G, path B/MAC 1, ch100-165, decrease power */ -- {0, 1, 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 14}, -+ {0, 1, 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 14}, - /* 5G, path B/MAC 1, ch100-165, increase power */ -- {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, -+ {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18}, - }; - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); - struct rtl_hal *rtlhal = rtl_hal(rtlpriv); - struct rtl_phy *rtlphy = &rtlpriv->phy; -+ struct rtl_dm *dm = &rtlpriv->dm; - u8 thermalvalue, delta, delta_lck, delta_iqk, delta_rxgain; -+ u8 ofdm_min_index = 6, ofdm_min_index_internal_pa = 3, rf; -+ long ele_a = 0, ele_d, temp_cck, val_x, value32; -+ bool is2t = IS_92D_SINGLEPHY(rtlhal->version); - u8 offset, thermalvalue_avg_count = 0; -+ u8 ofdm_index_old[2] = {0, 0}; - u32 thermalvalue_avg = 0; - bool internal_pa = false; -- long ele_a = 0, ele_d, temp_cck, val_x, value32; - long val_y, ele_c = 0; -+ s8 cck_index_old = 0; -+ u8 indexforchannel; - u8 ofdm_index[2]; - s8 cck_index = 0; -- u8 ofdm_index_old[2] = {0, 0}; -- s8 cck_index_old = 0; -- u8 index; -+ u8 index, swing; - int i; -- bool is2t = IS_92D_SINGLEPHY(rtlhal->version); -- u8 ofdm_min_index = 6, ofdm_min_index_internal_pa = 3, rf; -- u8 indexforchannel = -- rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel); - -- rtlpriv->dm.txpower_trackinginit = true; -+ indexforchannel = rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel); -+ -+ dm->txpower_trackinginit = true; -+ - rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "\n"); -+ - thermalvalue = (u8)rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0xf800); -+ - rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, - "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n", - thermalvalue, -- rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter); -+ dm->thermalvalue, rtlefuse->eeprom_thermalmeter); - - if (!thermalvalue) - goto exit; -@@ -312,10 +322,11 @@ rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) - else - rf = 1; - -- if (rtlpriv->dm.thermalvalue && !rtlhal->reloadtxpowerindex) -+ if (dm->thermalvalue && !rtlhal->reloadtxpowerindex) - goto old_index_done; - -- ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) & MASKOFDM_D; -+ ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) & MASKOFDM_D; -+ - for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { - if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) { - ofdm_index_old[0] = (u8)i; -@@ -327,13 +338,15 @@ rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) - break; - } - } -+ - if (is2t) { -- ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, -- MASKDWORD) & MASKOFDM_D; -+ ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD); -+ ele_d &= MASKOFDM_D; -+ - for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) { -- if (ele_d == -- (ofdmswing_table[i] & MASKOFDM_D)) { -+ if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) { - ofdm_index_old[1] = (u8)i; -+ - rtl_dbg(rtlpriv, COMP_POWER_TRACKING, - DBG_LOUD, - "Initial pathB ele_d reg 0x%x = 0x%lx, ofdm_index = 0x%x\n", -@@ -343,6 +356,7 @@ rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) - } - } - } -+ - if (rtlhal->current_bandtype == BAND_ON_2_4G) { - rtl92d_bandtype_2_4G(hw, &temp_cck, &cck_index_old); - } else { -@@ -350,115 +364,113 @@ rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) - cck_index_old = 12; - } - -- if (!rtlpriv->dm.thermalvalue) { -- rtlpriv->dm.thermalvalue = rtlefuse->eeprom_thermalmeter; -- rtlpriv->dm.thermalvalue_lck = thermalvalue; -- rtlpriv->dm.thermalvalue_iqk = thermalvalue; -- rtlpriv->dm.thermalvalue_rxgain = rtlefuse->eeprom_thermalmeter; -+ if (!dm->thermalvalue) { -+ dm->thermalvalue = rtlefuse->eeprom_thermalmeter; -+ dm->thermalvalue_lck = thermalvalue; -+ dm->thermalvalue_iqk = thermalvalue; -+ dm->thermalvalue_rxgain = rtlefuse->eeprom_thermalmeter; -+ - for (i = 0; i < rf; i++) -- rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; -- rtlpriv->dm.cck_index = cck_index_old; -+ dm->ofdm_index[i] = ofdm_index_old[i]; -+ -+ dm->cck_index = cck_index_old; - } -+ - if (rtlhal->reloadtxpowerindex) { - for (i = 0; i < rf; i++) -- rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i]; -- rtlpriv->dm.cck_index = cck_index_old; -+ dm->ofdm_index[i] = ofdm_index_old[i]; -+ -+ dm->cck_index = cck_index_old; -+ - rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, - "reload ofdm index for band switch\n"); - } -+ - old_index_done: - for (i = 0; i < rf; i++) -- ofdm_index[i] = rtlpriv->dm.ofdm_index[i]; -+ ofdm_index[i] = dm->ofdm_index[i]; -+ -+ dm->thermalvalue_avg[dm->thermalvalue_avg_index] = thermalvalue; -+ dm->thermalvalue_avg_index++; -+ -+ if (dm->thermalvalue_avg_index == AVG_THERMAL_NUM) -+ dm->thermalvalue_avg_index = 0; - -- rtlpriv->dm.thermalvalue_avg -- [rtlpriv->dm.thermalvalue_avg_index] = thermalvalue; -- rtlpriv->dm.thermalvalue_avg_index++; -- if (rtlpriv->dm.thermalvalue_avg_index == AVG_THERMAL_NUM) -- rtlpriv->dm.thermalvalue_avg_index = 0; - for (i = 0; i < AVG_THERMAL_NUM; i++) { -- if (rtlpriv->dm.thermalvalue_avg[i]) { -- thermalvalue_avg += rtlpriv->dm.thermalvalue_avg[i]; -+ if (dm->thermalvalue_avg[i]) { -+ thermalvalue_avg += dm->thermalvalue_avg[i]; - thermalvalue_avg_count++; - } - } -+ - if (thermalvalue_avg_count) - thermalvalue = (u8)(thermalvalue_avg / thermalvalue_avg_count); -+ - if (rtlhal->reloadtxpowerindex) { -- delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? -- (thermalvalue - rtlefuse->eeprom_thermalmeter) : -- (rtlefuse->eeprom_thermalmeter - thermalvalue); -+ delta = abs_diff(thermalvalue, rtlefuse->eeprom_thermalmeter); - rtlhal->reloadtxpowerindex = false; -- rtlpriv->dm.done_txpower = false; -- } else if (rtlpriv->dm.done_txpower) { -- delta = (thermalvalue > rtlpriv->dm.thermalvalue) ? -- (thermalvalue - rtlpriv->dm.thermalvalue) : -- (rtlpriv->dm.thermalvalue - thermalvalue); -+ dm->done_txpower = false; -+ } else if (dm->done_txpower) { -+ delta = abs_diff(thermalvalue, dm->thermalvalue); - } else { -- delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? -- (thermalvalue - rtlefuse->eeprom_thermalmeter) : -- (rtlefuse->eeprom_thermalmeter - thermalvalue); -+ delta = abs_diff(thermalvalue, rtlefuse->eeprom_thermalmeter); - } -- delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ? -- (thermalvalue - rtlpriv->dm.thermalvalue_lck) : -- (rtlpriv->dm.thermalvalue_lck - thermalvalue); -- delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ? -- (thermalvalue - rtlpriv->dm.thermalvalue_iqk) : -- (rtlpriv->dm.thermalvalue_iqk - thermalvalue); -- delta_rxgain = -- (thermalvalue > rtlpriv->dm.thermalvalue_rxgain) ? -- (thermalvalue - rtlpriv->dm.thermalvalue_rxgain) : -- (rtlpriv->dm.thermalvalue_rxgain - thermalvalue); -+ -+ delta_lck = abs_diff(thermalvalue, dm->thermalvalue_lck); -+ delta_iqk = abs_diff(thermalvalue, dm->thermalvalue_iqk); -+ delta_rxgain = abs_diff(thermalvalue, dm->thermalvalue_rxgain); -+ - rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, - "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n", -- thermalvalue, rtlpriv->dm.thermalvalue, -- rtlefuse->eeprom_thermalmeter, delta, delta_lck, -- delta_iqk); -+ thermalvalue, dm->thermalvalue, rtlefuse->eeprom_thermalmeter, -+ delta, delta_lck, delta_iqk); -+ - if (delta_lck > rtlefuse->delta_lck && rtlefuse->delta_lck != 0) { -- rtlpriv->dm.thermalvalue_lck = thermalvalue; -+ dm->thermalvalue_lck = thermalvalue; - rtlpriv->cfg->ops->phy_lc_calibrate(hw, is2t); - } - -- if (delta == 0 || !rtlpriv->dm.txpower_track_control) -+ if (delta == 0 || !dm->txpower_track_control) - goto check_delta; - -- rtlpriv->dm.done_txpower = true; -- delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ? -- (thermalvalue - rtlefuse->eeprom_thermalmeter) : -- (rtlefuse->eeprom_thermalmeter - thermalvalue); -+ dm->done_txpower = true; -+ delta = abs_diff(thermalvalue, rtlefuse->eeprom_thermalmeter); -+ - if (rtlhal->current_bandtype == BAND_ON_2_4G) { - offset = 4; - if (delta > INDEX_MAPPING_NUM - 1) - index = index_mapping[offset][INDEX_MAPPING_NUM - 1]; - else - index = index_mapping[offset][delta]; -- if (thermalvalue > rtlpriv->dm.thermalvalue) { -+ -+ if (thermalvalue > dm->thermalvalue) { - for (i = 0; i < rf; i++) - ofdm_index[i] -= delta; -+ - cck_index -= delta; - } else { - for (i = 0; i < rf; i++) - ofdm_index[i] += index; -+ - cck_index += index; - } - } else if (rtlhal->current_bandtype == BAND_ON_5G) { -- rtl92d_bandtype_5G(rtlhal, ofdm_index, -- &internal_pa, thermalvalue, -- delta, rf, rtlefuse, rtlpriv, -+ rtl92d_bandtype_5G(rtlhal, ofdm_index, &internal_pa, -+ thermalvalue, delta, rf, rtlefuse, rtlpriv, - rtlphy, index_mapping, - index_mapping_internal_pa); - } -+ - if (is2t) { - rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "temp OFDM_A_index=0x%x, OFDM_B_index = 0x%x,cck_index=0x%x\n", -- rtlpriv->dm.ofdm_index[0], -- rtlpriv->dm.ofdm_index[1], -- rtlpriv->dm.cck_index); -+ "temp OFDM_A_index=0x%x, OFDM_B_index = 0x%x, cck_index=0x%x\n", -+ dm->ofdm_index[0], dm->ofdm_index[1], dm->cck_index); - } else { - rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "temp OFDM_A_index=0x%x,cck_index = 0x%x\n", -- rtlpriv->dm.ofdm_index[0], -- rtlpriv->dm.cck_index); -+ "temp OFDM_A_index=0x%x, cck_index = 0x%x\n", -+ dm->ofdm_index[0], dm->cck_index); - } -+ - for (i = 0; i < rf; i++) { - if (ofdm_index[i] > OFDM_TABLE_SIZE_92D - 1) { - ofdm_index[i] = OFDM_TABLE_SIZE_92D - 1; -@@ -470,25 +482,28 @@ rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) - ofdm_index[i] = ofdm_min_index; - } - } -+ - if (rtlhal->current_bandtype == BAND_ON_2_4G) { - if (cck_index > CCK_TABLE_SIZE - 1) - cck_index = CCK_TABLE_SIZE - 1; - else if (cck_index < 0) - cck_index = 0; - } -+ - if (is2t) { - rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, - "new OFDM_A_index=0x%x, OFDM_B_index = 0x%x, cck_index=0x%x\n", -- ofdm_index[0], ofdm_index[1], -- cck_index); -+ ofdm_index[0], ofdm_index[1], cck_index); - } else { - rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -- "new OFDM_A_index=0x%x,cck_index = 0x%x\n", -+ "new OFDM_A_index=0x%x, cck_index = 0x%x\n", - ofdm_index[0], cck_index); - } -+ - ele_d = (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22; - val_x = rtlphy->iqk_matrix[indexforchannel].value[0][0]; - val_y = rtlphy->iqk_matrix[indexforchannel].value[0][1]; -+ - if (val_x != 0) { - if ((val_x & 0x00000200) != 0) - val_x = val_x | 0xFFFFFC00; -@@ -507,21 +522,16 @@ rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) - MASKDWORD, value32); - - value32 = (ele_c & 0x000003C0) >> 6; -- rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, -- value32); -+ rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, value32); - - value32 = ((val_x * ele_d) >> 7) & 0x01; -- rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), -- value32); -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), value32); - - } else { -- rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, -- MASKDWORD, -- ofdmswing_table[(u8)ofdm_index[0]]); -- rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, -- 0x00); -- rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, -- BIT(24), 0x00); -+ rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, -+ ofdmswing_table[ofdm_index[0]]); -+ rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS, 0x00); -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), 0x00); - } - - rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, -@@ -530,109 +540,79 @@ rtl92d_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw) - val_x, val_y, ele_a, ele_c, ele_d, - val_x, val_y); - -- if (cck_index >= CCK_TABLE_SIZE) -- cck_index = CCK_TABLE_SIZE - 1; -- if (cck_index < 0) -- cck_index = 0; - if (rtlhal->current_bandtype == BAND_ON_2_4G) { - /* Adjust CCK according to IQK result */ -- if (!rtlpriv->dm.cck_inch14) { -- rtl_write_byte(rtlpriv, 0xa22, -- cckswing_table_ch1ch13[cck_index][0]); -- rtl_write_byte(rtlpriv, 0xa23, -- cckswing_table_ch1ch13[cck_index][1]); -- rtl_write_byte(rtlpriv, 0xa24, -- cckswing_table_ch1ch13[cck_index][2]); -- rtl_write_byte(rtlpriv, 0xa25, -- cckswing_table_ch1ch13[cck_index][3]); -- rtl_write_byte(rtlpriv, 0xa26, -- cckswing_table_ch1ch13[cck_index][4]); -- rtl_write_byte(rtlpriv, 0xa27, -- cckswing_table_ch1ch13[cck_index][5]); -- rtl_write_byte(rtlpriv, 0xa28, -- cckswing_table_ch1ch13[cck_index][6]); -- rtl_write_byte(rtlpriv, 0xa29, -- cckswing_table_ch1ch13[cck_index][7]); -- } else { -- rtl_write_byte(rtlpriv, 0xa22, -- cckswing_table_ch14[cck_index][0]); -- rtl_write_byte(rtlpriv, 0xa23, -- cckswing_table_ch14[cck_index][1]); -- rtl_write_byte(rtlpriv, 0xa24, -- cckswing_table_ch14[cck_index][2]); -- rtl_write_byte(rtlpriv, 0xa25, -- cckswing_table_ch14[cck_index][3]); -- rtl_write_byte(rtlpriv, 0xa26, -- cckswing_table_ch14[cck_index][4]); -- rtl_write_byte(rtlpriv, 0xa27, -- cckswing_table_ch14[cck_index][5]); -- rtl_write_byte(rtlpriv, 0xa28, -- cckswing_table_ch14[cck_index][6]); -- rtl_write_byte(rtlpriv, 0xa29, -- cckswing_table_ch14[cck_index][7]); -+ for (i = 0; i < 8; i++) { -+ if (dm->cck_inch14) -+ swing = cckswing_table_ch14[cck_index][i]; -+ else -+ swing = cckswing_table_ch1ch13[cck_index][i]; -+ -+ rtl_write_byte(rtlpriv, 0xa22 + i, swing); - } - } -+ - if (is2t) { - ele_d = (ofdmswing_table[ofdm_index[1]] & 0xFFC00000) >> 22; - val_x = rtlphy->iqk_matrix[indexforchannel].value[0][4]; - val_y = rtlphy->iqk_matrix[indexforchannel].value[0][5]; -+ - if (val_x != 0) { - if ((val_x & 0x00000200) != 0) - /* consider minus */ - val_x = val_x | 0xFFFFFC00; - ele_a = ((val_x * ele_d) >> 8) & 0x000003FF; -+ - /* new element C = element D x Y */ - if ((val_y & 0x00000200) != 0) - val_y = val_y | 0xFFFFFC00; - ele_c = ((val_y * ele_d) >> 8) & 0x00003FF; -+ - /* write new elements A, C, D to regC88 - * and regC9C, element B is always 0 - */ - value32 = (ele_d << 22) | ((ele_c & 0x3F) << 16) | ele_a; -- rtl_set_bbreg(hw, -- ROFDM0_XBTXIQIMBALANCE, -+ rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, - MASKDWORD, value32); -+ - value32 = (ele_c & 0x000003C0) >> 6; -- rtl_set_bbreg(hw, ROFDM0_XDTXAFE, -- MASKH4BITS, value32); -+ rtl_set_bbreg(hw, ROFDM0_XDTXAFE, MASKH4BITS, value32); -+ - value32 = ((val_x * ele_d) >> 7) & 0x01; -- rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, -- BIT(28), value32); -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), value32); - } else { -- rtl_set_bbreg(hw, -- ROFDM0_XBTXIQIMBALANCE, -- MASKDWORD, -- ofdmswing_table[ofdm_index[1]]); -- rtl_set_bbreg(hw, ROFDM0_XDTXAFE, -- MASKH4BITS, 0x00); -- rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, -- BIT(28), 0x00); -+ rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, -+ MASKDWORD, ofdmswing_table[ofdm_index[1]]); -+ rtl_set_bbreg(hw, ROFDM0_XDTXAFE, MASKH4BITS, 0x00); -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), 0x00); - } -+ - rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, - "TxPwrTracking path B: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xeb4 = 0x%lx 0xebc = 0x%lx\n", -- val_x, val_y, ele_a, ele_c, -- ele_d, val_x, val_y); -+ val_x, val_y, ele_a, ele_c, ele_d, val_x, val_y); - } -+ - rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, - "TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", - rtl_get_bbreg(hw, 0xc80, MASKDWORD), - rtl_get_bbreg(hw, 0xc94, MASKDWORD), -- rtl_get_rfreg(hw, RF90_PATH_A, 0x24, -- RFREG_OFFSET_MASK)); -+ rtl_get_rfreg(hw, RF90_PATH_A, 0x24, RFREG_OFFSET_MASK)); - - check_delta: - if (delta_iqk > rtlefuse->delta_iqk && rtlefuse->delta_iqk != 0) { - rtl92d_phy_reset_iqk_result(hw); -- rtlpriv->dm.thermalvalue_iqk = thermalvalue; -+ dm->thermalvalue_iqk = thermalvalue; - rtlpriv->cfg->ops->phy_iq_calibrate(hw); - } -+ - if (delta_rxgain > 0 && rtlhal->current_bandtype == BAND_ON_5G && - thermalvalue <= rtlefuse->eeprom_thermalmeter) { -- rtlpriv->dm.thermalvalue_rxgain = thermalvalue; -+ dm->thermalvalue_rxgain = thermalvalue; - rtl92d_dm_rxgain_tracking_thermalmeter(hw); - } -- if (rtlpriv->dm.txpower_track_control) -- rtlpriv->dm.thermalvalue = thermalvalue; -+ -+ if (dm->txpower_track_control) -+ dm->thermalvalue = thermalvalue; - - exit: - rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n"); -@@ -675,25 +655,29 @@ EXPORT_SYMBOL_GPL(rtl92d_dm_check_txpower_tracking_thermal_meter); - - void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) - { -- u32 ret_value; - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt; - unsigned long flag = 0; -+ u32 ret_value; - - /* hold ofdm counter */ - rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1); /* hold page C counter */ -- rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /*hold page D counter */ -+ rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1); /* hold page D counter */ - - ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD); -- falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff); -- falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16); -+ falsealm_cnt->cnt_fast_fsync_fail = ret_value & 0xffff; -+ falsealm_cnt->cnt_sb_search_fail = (ret_value & 0xffff0000) >> 16; -+ - ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD); -- falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16); -+ falsealm_cnt->cnt_parity_fail = (ret_value & 0xffff0000) >> 16; -+ - ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD); -- falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff); -- falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16); -+ falsealm_cnt->cnt_rate_illegal = ret_value & 0xffff; -+ falsealm_cnt->cnt_crc8_fail = (ret_value & 0xffff0000) >> 16; -+ - ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD); -- falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff); -+ falsealm_cnt->cnt_mcs_fail = ret_value & 0xffff; -+ - falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail + - falsealm_cnt->cnt_rate_illegal + - falsealm_cnt->cnt_crc8_fail + -@@ -702,7 +686,6 @@ void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) - falsealm_cnt->cnt_sb_search_fail; - - if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) { -- /* hold cck counter */ - rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); - ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0); - falsealm_cnt->cnt_cck_fail = ret_value; -@@ -713,22 +696,17 @@ void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) - falsealm_cnt->cnt_cck_fail = 0; - } - -- /* reset false alarm counter registers */ -- falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail + -- falsealm_cnt->cnt_sb_search_fail + -- falsealm_cnt->cnt_parity_fail + -- falsealm_cnt->cnt_rate_illegal + -- falsealm_cnt->cnt_crc8_fail + -- falsealm_cnt->cnt_mcs_fail + -+ falsealm_cnt->cnt_all = falsealm_cnt->cnt_ofdm_fail + - falsealm_cnt->cnt_cck_fail; - -+ /* reset false alarm counter registers */ - rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1); -- /* update ofdm counter */ - rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0); -- /* update page C counter */ -- rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0); -- /* update page D counter */ -- rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0); -+ -+ /* update ofdm counter */ -+ rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0); /* update page C counter */ -+ rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0); /* update page D counter */ -+ - if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) { - /* reset cck counter */ - rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag); -@@ -737,16 +715,19 @@ void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw) - rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2); - rtl92d_release_cckandrw_pagea_ctl(hw, &flag); - } -+ - rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, - "Cnt_Fast_Fsync_fail = %x, Cnt_SB_Search_fail = %x\n", - falsealm_cnt->cnt_fast_fsync_fail, - falsealm_cnt->cnt_sb_search_fail); -+ - rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, - "Cnt_Parity_Fail = %x, Cnt_Rate_Illegal = %x, Cnt_Crc8_fail = %x, Cnt_Mcs_fail = %x\n", - falsealm_cnt->cnt_parity_fail, - falsealm_cnt->cnt_rate_illegal, - falsealm_cnt->cnt_crc8_fail, - falsealm_cnt->cnt_mcs_fail); -+ - rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, - "Cnt_Ofdm_fail = %x, Cnt_Cck_fail = %x, Cnt_all = %x\n", - falsealm_cnt->cnt_ofdm_fail, -@@ -763,7 +744,7 @@ void rtl92d_dm_find_minimum_rssi(struct ieee80211_hw *hw) - - /* Determine the minimum RSSI */ - if (mac->link_state < MAC80211_LINKED && -- rtlpriv->dm.UNDEC_SM_PWDB == 0) { -+ rtlpriv->dm.entry_min_undec_sm_pwdb == 0) { - de_digtable->min_undec_pwdb_for_dm = 0; - rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, - "Not connected to any\n"); -@@ -772,19 +753,20 @@ void rtl92d_dm_find_minimum_rssi(struct ieee80211_hw *hw) - if (mac->opmode == NL80211_IFTYPE_AP || - mac->opmode == NL80211_IFTYPE_ADHOC) { - de_digtable->min_undec_pwdb_for_dm = -- rtlpriv->dm.UNDEC_SM_PWDB; -+ rtlpriv->dm.entry_min_undec_sm_pwdb; - rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, - "AP Client PWDB = 0x%lx\n", -- rtlpriv->dm.UNDEC_SM_PWDB); -+ rtlpriv->dm.entry_min_undec_sm_pwdb); - } else { - de_digtable->min_undec_pwdb_for_dm = -- rtlpriv->dm.undec_sm_pwdb; -+ rtlpriv->dm.undec_sm_pwdb; - rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, - "STA Default Port PWDB = 0x%x\n", - de_digtable->min_undec_pwdb_for_dm); - } - } else { -- de_digtable->min_undec_pwdb_for_dm = rtlpriv->dm.UNDEC_SM_PWDB; -+ de_digtable->min_undec_pwdb_for_dm = -+ rtlpriv->dm.entry_min_undec_sm_pwdb; - rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD, - "AP Ext Port or disconnect PWDB = 0x%x\n", - de_digtable->min_undec_pwdb_for_dm); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.h -index 9dc0df5bb068..a146fc975421 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/dm_common.h -@@ -48,27 +48,6 @@ - #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 - #define INDEX_MAPPING_NUM 13 - --struct swat { -- u8 failure_cnt; -- u8 try_flag; -- u8 stop_trying; -- long pre_rssi; -- long trying_threshold; -- u8 cur_antenna; -- u8 pre_antenna; --}; -- --enum tag_dynamic_init_gain_operation_type_definition { -- DIG_TYPE_THRESH_HIGH = 0, -- DIG_TYPE_THRESH_LOW = 1, -- DIG_TYPE_BACKOFF = 2, -- DIG_TYPE_RX_GAIN_MIN = 3, -- DIG_TYPE_RX_GAIN_MAX = 4, -- DIG_TYPE_ENABLE = 5, -- DIG_TYPE_DISABLE = 6, -- DIG_OP_TYPE_MAX --}; -- - enum dm_1r_cca { - CCA_1R = 0, - CCA_2R = 1, -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c -index 73cfa9ad78ae..ecdbe3cd5161 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c -@@ -11,8 +11,7 @@ - - bool rtl92d_is_fw_downloaded(struct rtl_priv *rtlpriv) - { -- return (rtl_read_dword(rtlpriv, REG_MCUFWDL) & MCUFWDL_RDY) ? -- true : false; -+ return !!(rtl_read_dword(rtlpriv, REG_MCUFWDL) & MCUFWDL_RDY); - } - EXPORT_SYMBOL_GPL(rtl92d_is_fw_downloaded); - -@@ -50,17 +49,22 @@ void rtl92d_write_fw(struct ieee80211_hw *hw, - u32 page, offset; - - rtl_dbg(rtlpriv, COMP_FW, DBG_TRACE, "FW size is %d bytes,\n", size); -+ - if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) - rtl_fill_dummy(bufferptr, &size); -+ - pagenums = size / FW_8192D_PAGE_SIZE; - remainsize = size % FW_8192D_PAGE_SIZE; -+ - if (pagenums > 8) - pr_err("Page numbers should not greater then 8\n"); -+ - for (page = 0; page < pagenums; page++) { - offset = page * FW_8192D_PAGE_SIZE; - rtl_fw_page_write(hw, page, (bufferptr + offset), - FW_8192D_PAGE_SIZE); - } -+ - if (remainsize) { - offset = pagenums * FW_8192D_PAGE_SIZE; - page = pagenums; -@@ -79,14 +83,17 @@ int rtl92d_fw_free_to_go(struct ieee80211_hw *hw) - value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL); - } while ((counter++ < FW_8192D_POLLING_TIMEOUT_COUNT) && - (!(value32 & FWDL_CHKSUM_RPT))); -+ - if (counter >= FW_8192D_POLLING_TIMEOUT_COUNT) { - pr_err("chksum report fail! REG_MCUFWDL:0x%08x\n", - value32); - return -EIO; - } -+ - value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL); - value32 |= MCUFWDL_RDY; - rtl_write_dword(rtlpriv, REG_MCUFWDL, value32); -+ - return 0; - } - EXPORT_SYMBOL_GPL(rtl92d_fw_free_to_go); -@@ -99,7 +106,9 @@ void rtl92d_firmware_selfreset(struct ieee80211_hw *hw) - - /* Set (REG_HMETFR + 3) to 0x20 is reset 8051 */ - rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20); -+ - u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); -+ - while (u1b_tmp & BIT(2)) { - delay--; - if (delay == 0) -@@ -174,23 +183,22 @@ static bool _rtl92d_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum) - return result; - } - --static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw, -- u8 element_id, u32 cmd_len, u8 *cmdbuffer) -+void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, -+ u8 element_id, u32 cmd_len, u8 *cmdbuffer) - { -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); - struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); -- u8 boxnum; -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u8 boxcontent[4], boxextcontent[2]; - u16 box_reg = 0, box_extreg = 0; -- u8 u1b_tmp; -- bool isfw_read = false; -- u8 buf_index = 0; -+ u8 wait_writeh2c_limmit = 100; - bool bwrite_success = false; - u8 wait_h2c_limmit = 100; -- u8 wait_writeh2c_limmit = 100; -- u8 boxcontent[4], boxextcontent[2]; - u32 h2c_waitcounter = 0; -+ bool isfw_read = false; - unsigned long flag; -+ u8 u1b_tmp; -+ u8 boxnum; - u8 idx; - - if (ppsc->rfpwr_state == ERFOFF || ppsc->inactive_pwrstate == ERFOFF) { -@@ -198,7 +206,9 @@ static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw, - "Return as RF is off!!!\n"); - return; - } -+ - rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n"); -+ - while (true) { - spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag); - if (rtlhal->h2c_setinprogress) { -@@ -228,35 +238,23 @@ static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw, - break; - } - } -+ - while (!bwrite_success) { - wait_writeh2c_limmit--; - if (wait_writeh2c_limmit == 0) { - pr_err("Write H2C fail because no trigger for FW INT!\n"); - break; - } -+ - boxnum = rtlhal->last_hmeboxnum; -- switch (boxnum) { -- case 0: -- box_reg = REG_HMEBOX_0; -- box_extreg = REG_HMEBOX_EXT_0; -- break; -- case 1: -- box_reg = REG_HMEBOX_1; -- box_extreg = REG_HMEBOX_EXT_1; -- break; -- case 2: -- box_reg = REG_HMEBOX_2; -- box_extreg = REG_HMEBOX_EXT_2; -- break; -- case 3: -- box_reg = REG_HMEBOX_3; -- box_extreg = REG_HMEBOX_EXT_3; -- break; -- default: -- pr_err("switch case %#x not processed\n", -- boxnum); -+ if (boxnum > 3) { -+ pr_err("boxnum %#x too big\n", boxnum); - break; - } -+ -+ box_reg = REG_HMEBOX_0 + boxnum * SIZE_OF_REG_HMEBOX; -+ box_extreg = REG_HMEBOX_EXT_0 + boxnum * SIZE_OF_REG_HMEBOX_EXT; -+ - isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum); - while (!isfw_read) { - wait_h2c_limmit--; -@@ -266,78 +264,70 @@ static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw, - boxnum); - break; - } -+ - udelay(10); -+ - isfw_read = _rtl92d_check_fw_read_last_h2c(hw, boxnum); - u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF); - rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, - "Waiting for FW read clear HMEBox(%d)!!! 0x1BF = %2x\n", - boxnum, u1b_tmp); - } -+ - if (!isfw_read) { - rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, - "Write H2C register BOX[%d] fail!!!!! Fw do not read.\n", - boxnum); - break; - } -+ - memset(boxcontent, 0, sizeof(boxcontent)); - memset(boxextcontent, 0, sizeof(boxextcontent)); - boxcontent[0] = element_id; -+ - rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, - "Write element_id box_reg(%4x) = %2x\n", - box_reg, element_id); -+ - switch (cmd_len) { -- case 1: -- boxcontent[0] &= ~(BIT(7)); -- memcpy(boxcontent + 1, cmdbuffer + buf_index, 1); -- for (idx = 0; idx < 4; idx++) -- rtl_write_byte(rtlpriv, box_reg + idx, -- boxcontent[idx]); -- break; -- case 2: -- boxcontent[0] &= ~(BIT(7)); -- memcpy(boxcontent + 1, cmdbuffer + buf_index, 2); -- for (idx = 0; idx < 4; idx++) -- rtl_write_byte(rtlpriv, box_reg + idx, -- boxcontent[idx]); -- break; -- case 3: -- boxcontent[0] &= ~(BIT(7)); -- memcpy(boxcontent + 1, cmdbuffer + buf_index, 3); -- for (idx = 0; idx < 4; idx++) -- rtl_write_byte(rtlpriv, box_reg + idx, -- boxcontent[idx]); -- break; -- case 4: -- boxcontent[0] |= (BIT(7)); -- memcpy(boxextcontent, cmdbuffer + buf_index, 2); -- memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 2); -- for (idx = 0; idx < 2; idx++) -- rtl_write_byte(rtlpriv, box_extreg + idx, -- boxextcontent[idx]); -+ case 1 ... 3: -+ /* BOX: | ID | A0 | A1 | A2 | -+ * BOX_EXT: --- N/A ------ -+ */ -+ boxcontent[0] &= ~BIT(7); -+ memcpy(boxcontent + 1, cmdbuffer, cmd_len); -+ - for (idx = 0; idx < 4; idx++) - rtl_write_byte(rtlpriv, box_reg + idx, - boxcontent[idx]); - break; -- case 5: -- boxcontent[0] |= (BIT(7)); -- memcpy(boxextcontent, cmdbuffer + buf_index, 2); -- memcpy(boxcontent + 1, cmdbuffer + buf_index + 2, 3); -+ case 4 ... 5: -+ /* * ID ext = ID | BIT(7) -+ * BOX: | ID ext | A2 | A3 | A4 | -+ * BOX_EXT: | A0 | A1 | -+ */ -+ boxcontent[0] |= BIT(7); -+ memcpy(boxextcontent, cmdbuffer, 2); -+ memcpy(boxcontent + 1, cmdbuffer + 2, cmd_len - 2); -+ - for (idx = 0; idx < 2; idx++) - rtl_write_byte(rtlpriv, box_extreg + idx, - boxextcontent[idx]); -+ - for (idx = 0; idx < 4; idx++) - rtl_write_byte(rtlpriv, box_reg + idx, - boxcontent[idx]); - break; - default: -- pr_err("switch case %#x not processed\n", -- cmd_len); -+ pr_err("switch case %#x not processed\n", cmd_len); - break; - } -+ - bwrite_success = true; - rtlhal->last_hmeboxnum = boxnum + 1; - if (rtlhal->last_hmeboxnum == 4) - rtlhal->last_hmeboxnum = 0; -+ - rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, - "pHalData->last_hmeboxnum = %d\n", - rtlhal->last_hmeboxnum); -@@ -347,16 +337,6 @@ static void _rtl92d_fill_h2c_command(struct ieee80211_hw *hw, - spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); - rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "go out\n"); - } -- --void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, -- u8 element_id, u32 cmd_len, u8 *cmdbuffer) --{ -- u32 tmp_cmdbuf[2]; -- -- memset(tmp_cmdbuf, 0, 8); -- memcpy(tmp_cmdbuf, cmdbuffer, cmd_len); -- _rtl92d_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf); --} - EXPORT_SYMBOL_GPL(rtl92d_fill_h2c_cmd); - - void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus) -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c -index e70e83252e16..40aadb9c4609 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c -@@ -363,10 +363,10 @@ static enum version_8192d _rtl92d_read_chip_version(struct ieee80211_hw *hw) - } - - static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo, -- u8 *rom_content, bool autoloadfail) -+ u8 *efuse, bool autoloadfail) - { -- u32 rfpath, eeaddr, group, offset1, offset2; -- u8 i; -+ u32 rfpath, eeaddr, group, offset, offset1, offset2; -+ u8 i, val8; - - memset(pwrinfo, 0, sizeof(struct txpower_info)); - if (autoloadfail) { -@@ -405,98 +405,93 @@ static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo, - */ - for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { - for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) { -- eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3) -- + group; -+ eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3) + group; -+ - pwrinfo->cck_index[rfpath][group] = -- (rom_content[eeaddr] == 0xFF) ? -- (eeaddr > 0x7B ? -- EEPROM_DEFAULT_TXPOWERLEVEL_5G : -- EEPROM_DEFAULT_TXPOWERLEVEL_2G) : -- rom_content[eeaddr]; -+ efuse[eeaddr] == 0xFF ? -+ (eeaddr > 0x7B ? -+ EEPROM_DEFAULT_TXPOWERLEVEL_5G : -+ EEPROM_DEFAULT_TXPOWERLEVEL_2G) : -+ efuse[eeaddr]; - } - } - for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { - for (group = 0; group < CHANNEL_GROUP_MAX; group++) { - offset1 = group / 3; - offset2 = group % 3; -- eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) + -- offset2 + offset1 * 21; -+ eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3); -+ eeaddr += offset2 + offset1 * 21; -+ - pwrinfo->ht40_1sindex[rfpath][group] = -- (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ? -- EEPROM_DEFAULT_TXPOWERLEVEL_5G : -- EEPROM_DEFAULT_TXPOWERLEVEL_2G) : -- rom_content[eeaddr]; -+ efuse[eeaddr] == 0xFF ? -+ (eeaddr > 0x7B ? -+ EEPROM_DEFAULT_TXPOWERLEVEL_5G : -+ EEPROM_DEFAULT_TXPOWERLEVEL_2G) : -+ efuse[eeaddr]; - } - } -+ - /* These just for 92D efuse offset. */ - for (group = 0; group < CHANNEL_GROUP_MAX; group++) { - for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) { -- int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G; -- - offset1 = group / 3; - offset2 = group % 3; -+ offset = offset2 + offset1 * 21; - -- if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF) -+ val8 = efuse[EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G + offset]; -+ if (val8 != 0xFF) - pwrinfo->ht40_2sindexdiff[rfpath][group] = -- (rom_content[base1 + -- offset2 + offset1 * 21] >> (rfpath * 4)) -- & 0xF; -+ (val8 >> (rfpath * 4)) & 0xF; - else - pwrinfo->ht40_2sindexdiff[rfpath][group] = - EEPROM_DEFAULT_HT40_2SDIFF; -- if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2 -- + offset1 * 21] != 0xFF) -+ -+ val8 = efuse[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset]; -+ if (val8 != 0xFF) - pwrinfo->ht20indexdiff[rfpath][group] = -- (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G -- + offset2 + offset1 * 21] >> (rfpath * 4)) -- & 0xF; -+ (val8 >> (rfpath * 4)) & 0xF; - else - pwrinfo->ht20indexdiff[rfpath][group] = - EEPROM_DEFAULT_HT20_DIFF; -- if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2 -- + offset1 * 21] != 0xFF) -+ -+ val8 = efuse[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset]; -+ if (val8 != 0xFF) - pwrinfo->ofdmindexdiff[rfpath][group] = -- (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G -- + offset2 + offset1 * 21] >> (rfpath * 4)) -- & 0xF; -+ (val8 >> (rfpath * 4)) & 0xF; - else - pwrinfo->ofdmindexdiff[rfpath][group] = - EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF; -- if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2 -- + offset1 * 21] != 0xFF) -+ -+ val8 = efuse[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset]; -+ if (val8 != 0xFF) - pwrinfo->ht40maxoffset[rfpath][group] = -- (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G -- + offset2 + offset1 * 21] >> (rfpath * 4)) -- & 0xF; -+ (val8 >> (rfpath * 4)) & 0xF; - else - pwrinfo->ht40maxoffset[rfpath][group] = - EEPROM_DEFAULT_HT40_PWRMAXOFFSET; -- if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2 -- + offset1 * 21] != 0xFF) -+ -+ val8 = efuse[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset]; -+ if (val8 != 0xFF) - pwrinfo->ht20maxoffset[rfpath][group] = -- (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + -- offset2 + offset1 * 21] >> (rfpath * 4)) & -- 0xF; -+ (val8 >> (rfpath * 4)) & 0xF; - else - pwrinfo->ht20maxoffset[rfpath][group] = - EEPROM_DEFAULT_HT20_PWRMAXOFFSET; - } - } -- if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) { -+ -+ if (efuse[EEPROM_TSSI_A_5G] != 0xFF) { - /* 5GL */ -- pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F; -- pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F; -+ pwrinfo->tssi_a[0] = efuse[EEPROM_TSSI_A_5G] & 0x3F; -+ pwrinfo->tssi_b[0] = efuse[EEPROM_TSSI_B_5G] & 0x3F; - /* 5GM */ -- pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F; -- pwrinfo->tssi_b[1] = -- (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 | -- (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2; -+ pwrinfo->tssi_a[1] = efuse[EEPROM_TSSI_AB_5G] & 0x3F; -+ pwrinfo->tssi_b[1] = (efuse[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 | -+ (efuse[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2; - /* 5GH */ -- pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] & -- 0xF0) >> 4 | -- (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4; -- pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] & -- 0xFC) >> 2; -+ pwrinfo->tssi_a[2] = (efuse[EEPROM_TSSI_AB_5G + 1] & 0xF0) >> 4 | -+ (efuse[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4; -+ pwrinfo->tssi_b[2] = (efuse[EEPROM_TSSI_AB_5G + 2] & 0xFC) >> 2; - } else { - for (i = 0; i < 3; i++) { - pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI; -@@ -684,8 +679,6 @@ static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) - EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D, - EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, - COUNTRY_CODE_WORLD_WIDE_13}; -- int i; -- u16 usvalue; - u8 *hwinfo; - - hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); -@@ -699,12 +692,10 @@ static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) - _rtl92de_read_macphymode_and_bandtype(hw, hwinfo); - - /* Read Permanent MAC address for 2nd interface */ -- if (rtlhal->interfaceindex != 0) { -- for (i = 0; i < 6; i += 2) { -- usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i]; -- *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue; -- } -- } -+ if (rtlhal->interfaceindex != 0) -+ ether_addr_copy(rtlefuse->dev_addr, -+ &hwinfo[EEPROM_MAC_ADDR_MAC1_92D]); -+ - rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, - rtlefuse->dev_addr); - rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); -@@ -761,22 +752,24 @@ EXPORT_SYMBOL_GPL(rtl92de_read_eeprom_info); - static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw, - struct ieee80211_sta *sta) - { -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_phy *rtlphy = &rtlpriv->phy; -- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -- u32 ratr_value; -- u8 ratr_index = 0; -- u8 nmode = mac->ht_enable; -+ enum wireless_mode wirelessmode; - u8 mimo_ps = IEEE80211_SMPS_OFF; -- u16 shortgi_rate; -- u32 tmp_ratr_value; - u8 curtxbw_40mhz = mac->bw_40; -- u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? -- 1 : 0; -- u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? -- 1 : 0; -- enum wireless_mode wirelessmode = mac->mode; -+ u8 nmode = mac->ht_enable; -+ u8 curshortgi_40mhz; -+ u8 curshortgi_20mhz; -+ u32 tmp_ratr_value; -+ u8 ratr_index = 0; -+ u16 shortgi_rate; -+ u32 ratr_value; -+ -+ curshortgi_40mhz = !!(sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); -+ curshortgi_20mhz = !!(sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); -+ wirelessmode = mac->mode; - - if (rtlhal->current_bandtype == BAND_ON_5G) - ratr_value = sta->deflink.supp_rates[1] << 4; -@@ -844,27 +837,30 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, - struct ieee80211_sta *sta, - u8 rssi_level, bool update_bw) - { -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_phy *rtlphy = &rtlpriv->phy; -- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -- struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); - struct rtl_sta_info *sta_entry = NULL; -+ enum wireless_mode wirelessmode; -+ bool shortgi = false; -+ u8 curshortgi_40mhz; -+ u8 curshortgi_20mhz; -+ u8 curtxbw_40mhz; - u32 ratr_bitmap; - u8 ratr_index; -- u8 curtxbw_40mhz = (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0; -- u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ? -- 1 : 0; -- u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ? -- 1 : 0; -- enum wireless_mode wirelessmode = 0; -- bool shortgi = false; - u32 value[2]; - u8 macid = 0; -- u8 mimo_ps = IEEE80211_SMPS_OFF; -+ u8 mimo_ps; -+ -+ curtxbw_40mhz = sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40; -+ curshortgi_40mhz = !!(sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); -+ curshortgi_20mhz = !!(sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); - - sta_entry = (struct rtl_sta_info *)sta->drv_priv; - mimo_ps = sta_entry->mimo_ps; - wirelessmode = sta_entry->wireless_mode; -+ - if (mac->opmode == NL80211_IFTYPE_STATION) - curtxbw_40mhz = mac->bw_40; - else if (mac->opmode == NL80211_IFTYPE_AP || -@@ -877,6 +873,7 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, - ratr_bitmap = sta->deflink.supp_rates[0]; - ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 | - sta->deflink.ht_cap.mcs.rx_mask[0] << 12); -+ - switch (wirelessmode) { - case WIRELESS_MODE_B: - ratr_index = RATR_INX_WIRELESS_B; -@@ -905,6 +902,7 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, - ratr_index = RATR_INX_WIRELESS_NGB; - else - ratr_index = RATR_INX_WIRELESS_NG; -+ - if (mimo_ps == IEEE80211_SMPS_STATIC) { - if (rssi_level == 1) - ratr_bitmap &= 0x00070000; -@@ -948,6 +946,7 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, - } - } - } -+ - if ((curtxbw_40mhz && curshortgi_40mhz) || - (!curtxbw_40mhz && curshortgi_20mhz)) { - if (macid == 0) -@@ -1065,12 +1064,6 @@ void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, - u8 *p_macaddr, bool is_group, u8 enc_algo, - bool is_wepkey, bool clear_all) - { -- struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -- struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -- const u8 *macaddr = p_macaddr; -- u32 entry_id; -- bool is_pairwise = false; - static const u8 cam_const_addr[4][6] = { - {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, - {0x00, 0x00, 0x00, 0x00, 0x00, 0x01}, -@@ -1080,6 +1073,12 @@ void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, - static const u8 cam_const_broad[] = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff - }; -+ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ const u8 *macaddr = p_macaddr; -+ bool is_pairwise = false; -+ u32 entry_id; - - if (clear_all) { - u8 idx; -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c -index 87c458b27f4f..dbc8ea39d6fc 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c -@@ -41,8 +41,7 @@ static u32 _rtl92d_phy_rf_serial_read(struct ieee80211_hw *hw, - tmplong & (~BLSSIREADEDGE)); - udelay(10); - rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2); -- udelay(50); -- udelay(50); -+ udelay(100); - rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, - tmplong | BLSSIREADEDGE); - udelay(10); -@@ -319,23 +318,21 @@ void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) - struct rtl_phy *rtlphy = &rtlpriv->phy; - - rtlphy->default_initialgain[0] = -- (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); -+ rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0); - rtlphy->default_initialgain[1] = -- (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); -+ rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0); - rtlphy->default_initialgain[2] = -- (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); -+ rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0); - rtlphy->default_initialgain[3] = -- (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); -+ rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0); - rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, - "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", - rtlphy->default_initialgain[0], - rtlphy->default_initialgain[1], - rtlphy->default_initialgain[2], - rtlphy->default_initialgain[3]); -- rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, -- MASKBYTE0); -- rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, -- MASKDWORD); -+ rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0); -+ rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2, MASKDWORD); - rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, - "Default framesync (0x%x) = 0x%x\n", - ROFDM0_RXDETECTOR3, rtlphy->framesync); -@@ -349,7 +346,7 @@ static void _rtl92d_get_txpower_index(struct ieee80211_hw *hw, u8 channel, - struct rtl_phy *rtlphy = &rtlpriv->phy; - struct rtl_hal *rtlhal = &rtlpriv->rtlhal; - struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -- u8 index = (channel - 1); -+ u8 index = channel - 1; - - /* 1. CCK */ - if (rtlhal->current_bandtype == BAND_ON_2_4G) { -@@ -643,6 +640,7 @@ static void rtl92d_phy_set_io(struct ieee80211_hw *hw) - rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, - "--->Cmd(%#x), set_io_inprogress(%d)\n", - rtlphy->current_io_type, rtlphy->set_io_inprogress); -+ - switch (rtlphy->current_io_type) { - case IO_CMD_RESUME_DM_BY_SCAN: - de_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1; -@@ -659,6 +657,7 @@ static void rtl92d_phy_set_io(struct ieee80211_hw *hw) - rtlphy->current_io_type); - break; - } -+ - rtlphy->set_io_inprogress = false; - rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<---(%#x)\n", - rtlphy->current_io_type); -@@ -673,6 +672,7 @@ bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) - rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, - "-->IO Cmd(%#x), set_io_inprogress(%d)\n", - iotype, rtlphy->set_io_inprogress); -+ - do { - switch (iotype) { - case IO_CMD_RESUME_DM_BY_SCAN: -@@ -691,12 +691,14 @@ bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype) - break; - } - } while (false); -+ - if (postprocessing && !rtlphy->set_io_inprogress) { - rtlphy->set_io_inprogress = true; - rtlphy->current_io_type = iotype; - } else { - return false; - } -+ - rtl92d_phy_set_io(hw); - rtl_dbg(rtlpriv, COMP_CMD, DBG_TRACE, "<--IO Type(%#x)\n", iotype); - return true; -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h -index 2783d7e7b227..1dc52abe3d0d 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h -@@ -50,6 +50,7 @@ - #define REG_HMEBOX_EXT_1 0x008A - #define REG_HMEBOX_EXT_2 0x008C - #define REG_HMEBOX_EXT_3 0x008E -+#define SIZE_OF_REG_HMEBOX_EXT 2 - - #define REG_BIST_SCAN 0x00D0 - #define REG_BIST_RPT 0x00D4 -@@ -109,6 +110,7 @@ - #define REG_HMEBOX_1 0x01D4 - #define REG_HMEBOX_2 0x01D8 - #define REG_HMEBOX_3 0x01DC -+#define SIZE_OF_REG_HMEBOX 4 - - #define REG_LLT_INIT 0x01E0 - #define REG_BB_ACCEESS_CTRL 0x01E8 -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.c -index 8af166183688..427d1877f431 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/rf_common.c -@@ -16,10 +16,11 @@ void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth) - switch (bandwidth) { - case HT_CHANNEL_WIDTH_20: - for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { -- rtlphy->rfreg_chnlval[rfpath] = ((rtlphy->rfreg_chnlval -- [rfpath] & 0xfffff3ff) | 0x0400); -- rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | -- BIT(11), 0x01); -+ rtlphy->rfreg_chnlval[rfpath] &= 0xfffff3ff; -+ rtlphy->rfreg_chnlval[rfpath] |= 0x0400; -+ -+ rtl_set_rfreg(hw, rfpath, RF_CHNLBW, -+ BIT(10) | BIT(11), 0x01); - - rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, - "20M RF 0x18 = 0x%x\n", -@@ -29,10 +30,11 @@ void rtl92d_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth) - break; - case HT_CHANNEL_WIDTH_20_40: - for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { -- rtlphy->rfreg_chnlval[rfpath] = -- ((rtlphy->rfreg_chnlval[rfpath] & 0xfffff3ff)); -- rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(10) | BIT(11), -- 0x00); -+ rtlphy->rfreg_chnlval[rfpath] &= 0xfffff3ff; -+ -+ rtl_set_rfreg(hw, rfpath, RF_CHNLBW, -+ BIT(10) | BIT(11), 0x00); -+ - rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, - "40M RF 0x18 = 0x%x\n", - rtlphy->rfreg_chnlval[rfpath]); -@@ -135,7 +137,7 @@ static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw, - legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1]; - powerbase0 = powerlevel[i] + legacy_pwrdiff; - powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) | -- (powerbase0 << 8) | powerbase0; -+ (powerbase0 << 8) | powerbase0; - *(ofdmbase + i) = powerbase0; - RTPRINT(rtlpriv, FPHY, PHY_TXPWR, - " [OFDM power base index rf(%c) = 0x%x]\n", -@@ -157,6 +159,31 @@ static void _rtl92d_phy_get_power_base(struct ieee80211_hw *hw, - } - } - -+static void _rtl92d_get_pwr_diff_limit(struct ieee80211_hw *hw, u8 channel, -+ u8 index, u8 rf, u8 pwr_diff_limit[4]) -+{ -+ struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u32 mcs_offset; -+ u8 limit; -+ int i; -+ -+ mcs_offset = rtlphy->mcs_offset[0][index + (rf ? 8 : 0)]; -+ -+ for (i = 0; i < 4; i++) { -+ pwr_diff_limit[i] = (mcs_offset >> (i * 8)) & 0x7f; -+ -+ if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) -+ limit = rtlefuse->pwrgroup_ht40[rf][channel - 1]; -+ else -+ limit = rtlefuse->pwrgroup_ht20[rf][channel - 1]; -+ -+ if (pwr_diff_limit[i] > limit) -+ pwr_diff_limit[i] = limit; -+ } -+} -+ - static void _rtl92d_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw, - u8 channel, u8 index, - u32 *powerbase0, -@@ -166,107 +193,86 @@ static void _rtl92d_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw, - struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_phy *rtlphy = &rtlpriv->phy; -- u8 i, chnlgroup = 0, pwr_diff_limit[4]; - u32 writeval = 0, customer_limit, rf; -+ u8 chnlgroup = 0, pwr_diff_limit[4]; - - for (rf = 0; rf < 2; rf++) { - switch (rtlefuse->eeprom_regulatory) { - case 0: -- chnlgroup = 0; -- writeval = rtlphy->mcs_offset -- [chnlgroup][index + -- (rf ? 8 : 0)] + ((index < 2) ? -- powerbase0[rf] : -- powerbase1[rf]); -+ writeval = rtlphy->mcs_offset[0][index + (rf ? 8 : 0)]; -+ - RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "RTK better performance, writeval(%c) = 0x%x\n", -- rf == 0 ? 'A' : 'B', writeval); -+ "RTK better performance\n"); - break; - case 1: - if (rtlphy->pwrgroup_cnt == 1) - chnlgroup = 0; -- if (rtlphy->pwrgroup_cnt >= MAX_PG_GROUP) { -- chnlgroup = rtl92d_phy_get_chnlgroup_bypg(channel - 1); -- if (rtlphy->current_chan_bw == -- HT_CHANNEL_WIDTH_20) -- chnlgroup++; -- else -- chnlgroup += 4; -- writeval = rtlphy->mcs_offset -- [chnlgroup][index + -- (rf ? 8 : 0)] + ((index < 2) ? -- powerbase0[rf] : -- powerbase1[rf]); -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n", -- rf == 0 ? 'A' : 'B', writeval); -- } -+ -+ if (rtlphy->pwrgroup_cnt < MAX_PG_GROUP) -+ break; -+ -+ chnlgroup = rtl92d_phy_get_chnlgroup_bypg(channel - 1); -+ if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) -+ chnlgroup++; -+ else -+ chnlgroup += 4; -+ -+ writeval = rtlphy->mcs_offset -+ [chnlgroup][index + (rf ? 8 : 0)]; -+ -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -+ "Realtek regulatory, 20MHz\n"); - break; - case 2: -- writeval = ((index < 2) ? powerbase0[rf] : -- powerbase1[rf]); -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "Better regulatory, writeval(%c) = 0x%x\n", -- rf == 0 ? 'A' : 'B', writeval); -+ writeval = 0; -+ -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, "Better regulatory\n"); - break; - case 3: -- chnlgroup = 0; - if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) { - RTPRINT(rtlpriv, FPHY, PHY_TXPWR, - "customer's limit, 40MHz rf(%c) = 0x%x\n", - rf == 0 ? 'A' : 'B', -- rtlefuse->pwrgroup_ht40[rf] -- [channel - 1]); -+ rtlefuse->pwrgroup_ht40[rf][channel - 1]); - } else { - RTPRINT(rtlpriv, FPHY, PHY_TXPWR, - "customer's limit, 20MHz rf(%c) = 0x%x\n", - rf == 0 ? 'A' : 'B', -- rtlefuse->pwrgroup_ht20[rf] -- [channel - 1]); -- } -- for (i = 0; i < 4; i++) { -- pwr_diff_limit[i] = (u8)((rtlphy->mcs_offset -- [chnlgroup][index + (rf ? 8 : 0)] & -- (0x7f << (i * 8))) >> (i * 8)); -- if (rtlphy->current_chan_bw == -- HT_CHANNEL_WIDTH_20_40) { -- if (pwr_diff_limit[i] > -- rtlefuse->pwrgroup_ht40[rf] -- [channel - 1]) -- pwr_diff_limit[i] = -- rtlefuse->pwrgroup_ht40 -- [rf][channel - 1]; -- } else { -- if (pwr_diff_limit[i] > -- rtlefuse->pwrgroup_ht20[rf][channel - 1]) -- pwr_diff_limit[i] = -- rtlefuse->pwrgroup_ht20[rf] -- [channel - 1]; -- } -+ rtlefuse->pwrgroup_ht20[rf][channel - 1]); - } -+ -+ _rtl92d_get_pwr_diff_limit(hw, channel, index, rf, -+ pwr_diff_limit); -+ - customer_limit = (pwr_diff_limit[3] << 24) | - (pwr_diff_limit[2] << 16) | - (pwr_diff_limit[1] << 8) | - (pwr_diff_limit[0]); -+ - RTPRINT(rtlpriv, FPHY, PHY_TXPWR, - "Customer's limit rf(%c) = 0x%x\n", - rf == 0 ? 'A' : 'B', customer_limit); -- writeval = customer_limit + ((index < 2) ? -- powerbase0[rf] : powerbase1[rf]); -- RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "Customer, writeval rf(%c)= 0x%x\n", -- rf == 0 ? 'A' : 'B', writeval); -+ -+ writeval = customer_limit; -+ -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, "Customer\n"); - break; - default: -- chnlgroup = 0; -- writeval = rtlphy->mcs_offset[chnlgroup][index + -- (rf ? 8 : 0)] + ((index < 2) ? -- powerbase0[rf] : powerbase1[rf]); -+ writeval = rtlphy->mcs_offset[0][index + (rf ? 8 : 0)]; -+ - RTPRINT(rtlpriv, FPHY, PHY_TXPWR, -- "RTK better performance, writeval rf(%c) = 0x%x\n", -- rf == 0 ? 'A' : 'B', writeval); -+ "RTK better performance\n"); - break; - } -+ -+ if (index < 2) -+ writeval += powerbase0[rf]; -+ else -+ writeval += powerbase1[rf]; -+ -+ RTPRINT(rtlpriv, FPHY, PHY_TXPWR, "writeval rf(%c)= 0x%x\n", -+ rf == 0 ? 'A' : 'B', writeval); -+ - *(p_outwriteval + rf) = writeval; - } - } -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c -index 5b8f404373ea..72d2b7426d82 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c -@@ -349,14 +349,16 @@ static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw, - __le32 *pdesc, - struct rx_fwinfo_92d *p_drvinfo) - { -- struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); - struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); - struct ieee80211_hdr *hdr; -+ bool packet_matchbssid; -+ bool packet_beacon; -+ bool packet_toself; -+ u16 type, cfc; - u8 *tmp_buf; - u8 *praddr; -- u16 type, cfc; - __le16 fc; -- bool packet_matchbssid, packet_toself, packet_beacon = false; - - tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift; - hdr = (struct ieee80211_hdr *)tmp_buf; -@@ -372,8 +374,7 @@ static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw, - (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv)); - packet_toself = packet_matchbssid && - ether_addr_equal(praddr, rtlefuse->dev_addr); -- if (ieee80211_is_beacon(fc)) -- packet_beacon = true; -+ packet_beacon = ieee80211_is_beacon(fc); - _rtl92de_query_rxphystatus(hw, pstats, pdesc, p_drvinfo, - packet_matchbssid, packet_toself, - packet_beacon); --- -2.34.1 - diff --git a/packages/linux/patches/rtlwifi/6.10/0006-6.10-wifi-rtlwifi-Adjust-rtl8192d-common-for.patch b/packages/linux/patches/rtlwifi/6.10/0006-6.10-wifi-rtlwifi-Adjust-rtl8192d-common-for.patch deleted file mode 100644 index 8e7d431c8f..0000000000 --- a/packages/linux/patches/rtlwifi/6.10/0006-6.10-wifi-rtlwifi-Adjust-rtl8192d-common-for.patch +++ /dev/null @@ -1,683 +0,0 @@ -From 7335e62025a7cfe186aab54609b23c4f24d838e0 Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 25 Apr 2024 21:15:20 +0300 -Subject: [PATCH 06/07] 6.10: wifi: rtlwifi: Adjust rtl8192d-common - for USB - -A few of the shared functions need small changes for the USB driver: - - firmware loading - - efuse reading - - rate mask updating - - rf register reading - - initial gain for scanning - -Also, add a few macros to wifi.h and initialise rtlhal.interfaceindex -for USB devices. - -Signed-off-by: Bitterblue Smith -Acked-by: Ping-Ke Shih -Signed-off-by: Ping-Ke Shih -Link: https://msgid.link/28100330-f421-4b85-b41b-f1045380cef2@gmail.com ---- - drivers/net/wireless/realtek/rtlwifi/efuse.c | 2 +- - drivers/net/wireless/realtek/rtlwifi/efuse.h | 2 +- - .../realtek/rtlwifi/rtl8192d/fw_common.c | 23 ++- - .../realtek/rtlwifi/rtl8192d/fw_common.h | 10 ++ - .../realtek/rtlwifi/rtl8192d/hw_common.c | 61 +++++-- - .../realtek/rtlwifi/rtl8192d/phy_common.c | 22 ++- - .../realtek/rtlwifi/rtl8192d/phy_common.h | 24 +++ - .../wireless/realtek/rtlwifi/rtl8192d/reg.h | 160 +++++++++++++++--- - drivers/net/wireless/realtek/rtlwifi/usb.c | 3 + - drivers/net/wireless/realtek/rtlwifi/wifi.h | 5 + - 10 files changed, 268 insertions(+), 44 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtlwifi/efuse.c b/drivers/net/wireless/realtek/rtlwifi/efuse.c -index c1fbc29d5ca1..82cf5fb5175f 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/efuse.c -+++ b/drivers/net/wireless/realtek/rtlwifi/efuse.c -@@ -1211,7 +1211,7 @@ static u8 efuse_calculate_word_cnts(u8 word_en) - } - - int rtl_get_hwinfo(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv, -- int max_size, u8 *hwinfo, int *params) -+ int max_size, u8 *hwinfo, const int *params) - { - struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); - struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw); -diff --git a/drivers/net/wireless/realtek/rtlwifi/efuse.h b/drivers/net/wireless/realtek/rtlwifi/efuse.h -index 4821625ad1e5..e250ffb0f4b2 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/efuse.h -+++ b/drivers/net/wireless/realtek/rtlwifi/efuse.h -@@ -89,7 +89,7 @@ void efuse_force_write_vendor_id(struct ieee80211_hw *hw); - void efuse_re_pg_section(struct ieee80211_hw *hw, u8 section_idx); - void efuse_power_switch(struct ieee80211_hw *hw, u8 write, u8 pwrstate); - int rtl_get_hwinfo(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv, -- int max_size, u8 *hwinfo, int *params); -+ int max_size, u8 *hwinfo, const int *params); - void rtl_fill_dummy(u8 *pfwbuf, u32 *pfwlen); - void rtl_fw_page_write(struct ieee80211_hw *hw, u32 page, u8 *buffer, - u32 size); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c -index ecdbe3cd5161..aa54dbde6ea8 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c -@@ -98,24 +98,45 @@ int rtl92d_fw_free_to_go(struct ieee80211_hw *hw) - } - EXPORT_SYMBOL_GPL(rtl92d_fw_free_to_go); - -+#define RTL_USB_DELAY_FACTOR 60 -+ - void rtl92d_firmware_selfreset(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); - u8 u1b_tmp; - u8 delay = 100; - -+ if (rtlhal->interface == INTF_USB) { -+ delay *= RTL_USB_DELAY_FACTOR; -+ -+ rtl_write_byte(rtlpriv, REG_FSIMR, 0); -+ -+ /* We need to disable other HRCV INT to influence 8051 reset. */ -+ rtl_write_byte(rtlpriv, REG_FWIMR, 0x20); -+ -+ /* Close mask to prevent incorrect FW write operation. */ -+ rtl_write_byte(rtlpriv, REG_FTIMR, 0); -+ } -+ - /* Set (REG_HMETFR + 3) to 0x20 is reset 8051 */ - rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20); - - u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); - -- while (u1b_tmp & BIT(2)) { -+ while (u1b_tmp & (FEN_CPUEN >> 8)) { - delay--; - if (delay == 0) - break; - udelay(50); - u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); - } -+ -+ if (rtlhal->interface == INTF_USB) { -+ if ((u1b_tmp & (FEN_CPUEN >> 8)) && delay == 0) -+ rtl_write_byte(rtlpriv, REG_FWIMR, 0); -+ } -+ - WARN_ONCE((delay <= 0), "rtl8192de: 8051 reset failed!\n"); - rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, - "=====> 8051 reset success (%d)\n", delay); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h -index 4e8e2b716f88..4b73e0bd4ac4 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.h -@@ -25,6 +25,16 @@ - #define GET_FIRMWARE_HDR_SUB_VER(__fwhdr) \ - le32_get_bits(*(__le32 *)((__fwhdr) + 4), GENMASK(23, 16)) - -+#define RAID_MASK GENMASK(31, 28) -+#define RATE_MASK_MASK GENMASK(27, 0) -+#define SHORT_GI_MASK BIT(5) -+#define MACID_MASK GENMASK(4, 0) -+ -+struct rtl92d_rate_mask_h2c { -+ __le32 rate_mask_and_raid; -+ u8 macid_and_short_gi; -+} __packed; -+ - bool rtl92d_is_fw_downloaded(struct rtl_priv *rtlpriv); - void rtl92d_enable_fw_download(struct ieee80211_hw *hw, bool enable); - void rtl92d_write_fw(struct ieee80211_hw *hw, -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c -index 40aadb9c4609..920bfb4eaaef 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c -@@ -618,9 +618,14 @@ static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw, - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -- u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION]; -+ bool is_single_mac = true; - -- if (macphy_crvalue & BIT(3)) { -+ if (rtlhal->interface == INTF_PCI) -+ is_single_mac = !!(content[EEPROM_MAC_FUNCTION] & BIT(3)); -+ else if (rtlhal->interface == INTF_USB) -+ is_single_mac = !(content[EEPROM_ENDPOINT_SETTING] & BIT(0)); -+ -+ if (is_single_mac) { - rtlhal->macphymode = SINGLEMAC_SINGLEPHY; - rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, - "MacPhyMode SINGLEMAC_SINGLEPHY\n"); -@@ -659,6 +664,7 @@ static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) - rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n"); - break; - case 0xCC33: -+ case 0x33CC: - chipver |= CHIP_92D_E_CUT; - rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n"); - break; -@@ -672,15 +678,27 @@ static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) - - static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) - { -+ static const int params_pci[] = { -+ RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, -+ EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D, -+ EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, -+ COUNTRY_CODE_WORLD_WIDE_13 -+ }; -+ static const int params_usb[] = { -+ RTL8190_EEPROM_ID, EEPROM_VID_USB, EEPROM_PID_USB, -+ EEPROM_VID_USB, EEPROM_PID_USB, EEPROM_MAC_ADDR_MAC0_92DU, -+ EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, -+ COUNTRY_CODE_WORLD_WIDE_13 -+ }; - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); - struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -- int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, -- EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D, -- EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID, -- COUNTRY_CODE_WORLD_WIDE_13}; -+ const int *params = params_pci; - u8 *hwinfo; - -+ if (rtlhal->interface == INTF_USB) -+ params = params_usb; -+ - hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL); - if (!hwinfo) - return; -@@ -842,6 +860,7 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_phy *rtlphy = &rtlpriv->phy; - struct rtl_sta_info *sta_entry = NULL; -+ struct rtl92d_rate_mask_h2c rate_mask; - enum wireless_mode wirelessmode; - bool shortgi = false; - u8 curshortgi_40mhz; -@@ -849,7 +868,6 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, - u8 curtxbw_40mhz; - u32 ratr_bitmap; - u8 ratr_index; -- u32 value[2]; - u8 macid = 0; - u8 mimo_ps; - -@@ -965,12 +983,28 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, - break; - } - -- value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28); -- value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80; -+ le32p_replace_bits(&rate_mask.rate_mask_and_raid, ratr_bitmap, RATE_MASK_MASK); -+ le32p_replace_bits(&rate_mask.rate_mask_and_raid, ratr_index, RAID_MASK); -+ u8p_replace_bits(&rate_mask.macid_and_short_gi, macid, MACID_MASK); -+ u8p_replace_bits(&rate_mask.macid_and_short_gi, shortgi, SHORT_GI_MASK); -+ u8p_replace_bits(&rate_mask.macid_and_short_gi, 1, BIT(7)); -+ - rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, -- "ratr_bitmap :%x value0:%x value1:%x\n", -- ratr_bitmap, value[0], value[1]); -- rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *)value); -+ "Rate_index:%x, ratr_val:%x, %5phC\n", -+ ratr_index, ratr_bitmap, &rate_mask); -+ -+ if (rtlhal->interface == INTF_PCI) { -+ rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, sizeof(rate_mask), -+ (u8 *)&rate_mask); -+ } else { -+ /* rtl92d_fill_h2c_cmd() does USB I/O and will result in a -+ * "scheduled while atomic" if called directly -+ */ -+ memcpy(rtlpriv->rate_mask, &rate_mask, -+ sizeof(rtlpriv->rate_mask)); -+ schedule_work(&rtlpriv->works.fill_h2c_cmd); -+ } -+ - if (macid != 0) - sta_entry->ratr_index = ratr_index; - } -@@ -1014,7 +1048,8 @@ bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) - bool actuallyset = false; - unsigned long flag; - -- if (rtlpci->being_init_adapter) -+ if (rtlpriv->rtlhal.interface == INTF_PCI && -+ rtlpci->being_init_adapter) - return false; - if (ppsc->swrf_processing) - return false; -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c -index dbc8ea39d6fc..228c84ab5b90 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.c -@@ -89,11 +89,11 @@ u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, - rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, - "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n", - regaddr, rfpath, bitmask); -- spin_lock(&rtlpriv->locks.rf_lock); -+ rtl92d_pci_lock(rtlpriv); - original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr); - bitshift = calculate_bit_shift(bitmask); - readback_value = (original_value & bitmask) >> bitshift; -- spin_unlock(&rtlpriv->locks.rf_lock); -+ rtl92d_pci_unlock(rtlpriv); - rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, - "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", - regaddr, rfpath, bitmask, original_value); -@@ -113,7 +113,7 @@ void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, - regaddr, bitmask, data, rfpath); - if (bitmask == 0) - return; -- spin_lock(&rtlpriv->locks.rf_lock); -+ rtl92d_pci_lock(rtlpriv); - if (rtlphy->rf_mode != RF_OP_BY_FW) { - if (bitmask != RFREG_OFFSET_MASK) { - original_value = _rtl92d_phy_rf_serial_read(hw, -@@ -125,7 +125,7 @@ void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, - } - _rtl92d_phy_rf_serial_write(hw, rfpath, regaddr, data); - } -- spin_unlock(&rtlpriv->locks.rf_lock); -+ rtl92d_pci_unlock(rtlpriv); - rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, - "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n", - regaddr, bitmask, data, rfpath); -@@ -650,6 +650,8 @@ static void rtl92d_phy_set_io(struct ieee80211_hw *hw) - case IO_CMD_PAUSE_DM_BY_SCAN: - rtlphy->initgain_backup.xaagccore1 = de_digtable->cur_igvalue; - de_digtable->cur_igvalue = 0x37; -+ if (rtlpriv->rtlhal.interface == INTF_USB) -+ de_digtable->cur_igvalue = 0x17; - rtl92d_dm_write_dig(hw); - break; - default: -@@ -710,22 +712,28 @@ void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw) - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); - u8 offset = REG_MAC_PHY_CTRL_NORMAL; -+ u8 phy_ctrl = 0xf0; -+ -+ if (rtlhal->interface == INTF_USB) { -+ phy_ctrl = rtl_read_byte(rtlpriv, offset); -+ phy_ctrl &= ~(BIT(0) | BIT(1) | BIT(2)); -+ } - - switch (rtlhal->macphymode) { - case DUALMAC_DUALPHY: - rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, - "MacPhyMode: DUALMAC_DUALPHY\n"); -- rtl_write_byte(rtlpriv, offset, 0xF3); -+ rtl_write_byte(rtlpriv, offset, phy_ctrl | BIT(0) | BIT(1)); - break; - case SINGLEMAC_SINGLEPHY: - rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, - "MacPhyMode: SINGLEMAC_SINGLEPHY\n"); -- rtl_write_byte(rtlpriv, offset, 0xF4); -+ rtl_write_byte(rtlpriv, offset, phy_ctrl | BIT(2)); - break; - case DUALMAC_SINGLEPHY: - rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, - "MacPhyMode: DUALMAC_SINGLEPHY\n"); -- rtl_write_byte(rtlpriv, offset, 0xF1); -+ rtl_write_byte(rtlpriv, offset, phy_ctrl | BIT(0)); - break; - } - } -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.h -index f9b5d0d3a7e6..0f794557af47 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/phy_common.h -@@ -32,6 +32,9 @@ static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw, - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - -+ if (rtlpriv->rtlhal.interface == INTF_USB) -+ return; -+ - if (rtlpriv->rtlhal.interfaceindex == 1) - spin_lock_irqsave(&rtlpriv->locks.cck_and_rw_pagea_lock, *flag); - } -@@ -41,6 +44,9 @@ static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw, - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - -+ if (rtlpriv->rtlhal.interface == INTF_USB) -+ return; -+ - if (rtlpriv->rtlhal.interfaceindex == 1) - spin_unlock_irqrestore(&rtlpriv->locks.cck_and_rw_pagea_lock, - *flag); -@@ -84,4 +90,22 @@ void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw, - void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw, - unsigned long *flag); - -+/* Without these helpers and the declarations sparse warns about -+ * context imbalance. -+ */ -+static inline void rtl92d_pci_lock(struct rtl_priv *rtlpriv) -+{ -+ if (rtlpriv->rtlhal.interface == INTF_PCI) -+ spin_lock(&rtlpriv->locks.rf_lock); -+} -+ -+static inline void rtl92d_pci_unlock(struct rtl_priv *rtlpriv) -+{ -+ if (rtlpriv->rtlhal.interface == INTF_PCI) -+ spin_unlock(&rtlpriv->locks.rf_lock); -+} -+ -+void rtl92d_pci_lock(struct rtl_priv *rtlpriv); -+void rtl92d_pci_unlock(struct rtl_priv *rtlpriv); -+ - #endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h -index 1dc52abe3d0d..b5b906b799cb 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/reg.h -@@ -52,6 +52,8 @@ - #define REG_HMEBOX_EXT_3 0x008E - #define SIZE_OF_REG_HMEBOX_EXT 2 - -+#define REG_EFUSE_ACCESS 0x00CF -+ - #define REG_BIST_SCAN 0x00D0 - #define REG_BIST_RPT 0x00D4 - #define REG_BIST_ROM_RPT 0x00D8 -@@ -87,6 +89,7 @@ - #define REG_CPWM 0x012F - #define REG_FWIMR 0x0130 - #define REG_FWISR 0x0134 -+#define REG_FTIMR 0x0138 - #define REG_PKTBUF_DBG_CTRL 0x0140 - #define REG_PKTBUF_DBG_DATA_L 0x0144 - #define REG_PKTBUF_DBG_DATA_H 0x0148 -@@ -199,6 +202,8 @@ - #define REG_POWER_STAGE1 0x04B4 - #define REG_POWER_STAGE2 0x04B8 - #define REG_PKT_LIFE_TIME 0x04C0 -+#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 -+#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 - #define REG_STBC_SETTING 0x04C4 - #define REG_PROT_MODE_CTRL 0x04C8 - #define REG_MAX_AGGR_NUM 0x04CA -@@ -235,6 +240,7 @@ - #define REG_RD_NAV_NXT 0x0544 - #define REG_NAV_PROT_LEN 0x0546 - #define REG_BCN_CTRL 0x0550 -+#define REG_BCN_CTRL_1 0x0551 - #define REG_MBID_NUM 0x0552 - #define REG_DUAL_TSF_RST 0x0553 - #define REG_BCN_INTERVAL 0x0554 -@@ -321,6 +327,8 @@ - #define REG_BT_COEX_TABLE 0x06C0 - #define REG_WMAC_RESP_TXINFO 0x06D8 - -+#define REG_USB_Queue_Select_MAC0 0xFE44 -+#define REG_USB_Queue_Select_MAC1 0xFE47 - - /* ----------------------------------------------------- */ - /* Redifine 8192C register definition for compatibility */ -@@ -357,27 +365,27 @@ - #define RRSR_RSC_UPSUBCHNL 0x400000 - #define RRSR_RSC_LOWSUBCHNL 0x200000 - #define RRSR_SHORT 0x800000 --#define RRSR_1M BIT0 --#define RRSR_2M BIT1 --#define RRSR_5_5M BIT2 --#define RRSR_11M BIT3 --#define RRSR_6M BIT4 --#define RRSR_9M BIT5 --#define RRSR_12M BIT6 --#define RRSR_18M BIT7 --#define RRSR_24M BIT8 --#define RRSR_36M BIT9 --#define RRSR_48M BIT10 --#define RRSR_54M BIT11 --#define RRSR_MCS0 BIT12 --#define RRSR_MCS1 BIT13 --#define RRSR_MCS2 BIT14 --#define RRSR_MCS3 BIT15 --#define RRSR_MCS4 BIT16 --#define RRSR_MCS5 BIT17 --#define RRSR_MCS6 BIT18 --#define RRSR_MCS7 BIT19 --#define BRSR_ACKSHORTPMB BIT23 -+#define RRSR_1M BIT(0) -+#define RRSR_2M BIT(1) -+#define RRSR_5_5M BIT(2) -+#define RRSR_11M BIT(3) -+#define RRSR_6M BIT(4) -+#define RRSR_9M BIT(5) -+#define RRSR_12M BIT(6) -+#define RRSR_18M BIT(7) -+#define RRSR_24M BIT(8) -+#define RRSR_36M BIT(9) -+#define RRSR_48M BIT(10) -+#define RRSR_54M BIT(11) -+#define RRSR_MCS0 BIT(12) -+#define RRSR_MCS1 BIT(13) -+#define RRSR_MCS2 BIT(14) -+#define RRSR_MCS3 BIT(15) -+#define RRSR_MCS4 BIT(16) -+#define RRSR_MCS5 BIT(17) -+#define RRSR_MCS6 BIT(18) -+#define RRSR_MCS7 BIT(19) -+#define BRSR_ACKSHORTPMB BIT(23) - - /* ----------------------------------------------------- */ - /* 8192C Rate Definition */ -@@ -602,7 +610,11 @@ - #define EEPROM_SVID 0x2C /* SE Vendor ID.E-F */ - #define EEPROM_SMID 0x2E /* SE PCI Subsystem ID. 10-11 */ - -+#define EEPROM_VID_USB 0xC -+#define EEPROM_PID_USB 0xE -+#define EEPROM_ENDPOINT_SETTING 0x10 - #define EEPROM_MAC_ADDR 0x16 /* SEMAC Address. 12-17 */ -+#define EEPROM_MAC_ADDR_MAC0_92DU 0x19 - #define EEPROM_MAC_ADDR_MAC0_92D 0x55 - #define EEPROM_MAC_ADDR_MAC1_92D 0x5B - -@@ -917,6 +929,42 @@ - #define BD_HCI_SEL BIT(26) - #define TYPE_ID BIT(27) - -+#define HCI_TXDMA_EN BIT(0) -+#define HCI_RXDMA_EN BIT(1) -+#define TXDMA_EN BIT(2) -+#define RXDMA_EN BIT(3) -+#define PROTOCOL_EN BIT(4) -+#define SCHEDULE_EN BIT(5) -+#define MACTXEN BIT(6) -+#define MACRXEN BIT(7) -+#define ENSWBCN BIT(8) -+#define ENSEC BIT(9) -+ -+#define HQSEL_VOQ BIT(0) -+#define HQSEL_VIQ BIT(1) -+#define HQSEL_BEQ BIT(2) -+#define HQSEL_BKQ BIT(3) -+#define HQSEL_MGTQ BIT(4) -+#define HQSEL_HIQ BIT(5) -+ -+#define TXDMA_HIQ_MAP GENMASK(15, 14) -+#define TXDMA_MGQ_MAP GENMASK(13, 12) -+#define TXDMA_BKQ_MAP GENMASK(11, 10) -+#define TXDMA_BEQ_MAP GENMASK(9, 8) -+#define TXDMA_VIQ_MAP GENMASK(7, 6) -+#define TXDMA_VOQ_MAP GENMASK(5, 4) -+ -+#define QUEUE_LOW 1 -+#define QUEUE_NORMAL 2 -+#define QUEUE_HIGH 3 -+ -+#define HPQ_MASK GENMASK(7, 0) -+#define LPQ_MASK GENMASK(15, 8) -+#define PUBQ_MASK GENMASK(23, 16) -+#define LD_RQPN BIT(31) -+ -+#define DROP_DATA_EN BIT(9) -+ - /* LLT_INIT */ - #define _LLT_NO_ACTIVE 0x0 - #define _LLT_WRITE_ACCESS 0x1 -@@ -931,6 +979,10 @@ - /* ----------------------------------------------------- */ - /* 0x0400h ~ 0x047Fh Protocol Configuration */ - /* ----------------------------------------------------- */ -+/* FWHW_TXQ_CTRL */ -+#define EN_AMPDU_RTY_NEW BIT(7) -+#define EN_BCNQ_DL BIT(22) -+ - #define RETRY_LIMIT_SHORT_SHIFT 8 - #define RETRY_LIMIT_LONG_SHIFT 0 - -@@ -944,6 +996,13 @@ - #define AC_PARAM_ECW_MIN_OFFSET 8 - #define AC_PARAM_AIFS_OFFSET 0 - -+/* REG_RD_CTRL */ -+#define DIS_EDCA_CNT_DWN BIT(11) -+ -+/* REG_BCN_CTRL */ -+#define EN_BCN_FUNCTION BIT(3) -+#define DIS_TSF_UDT BIT(4) -+ - /* ACMHWCTRL */ - #define ACMHW_HWEN BIT(0) - #define ACMHW_BEQEN BIT(1) -@@ -1075,6 +1134,11 @@ - #define RCCK0_FACOUNTERLOWER 0xa5c - #define RCCK0_FACOUNTERUPPER 0xa58 - -+#define RPDP_ANTA 0xb00 -+#define RCONFIG_ANTA 0xb68 -+#define RCONFIG_ANTB 0xb6c -+#define RPDP_ANTB 0xb70 -+ - /* 6. PageC(0xC00) */ - #define ROFDM0_LSTF 0xc00 - -@@ -1128,6 +1192,7 @@ - #define ROFDM0_TXPSEUDONOISEWGT 0xce4 - #define ROFDM0_FRAMESYNC 0xcf0 - #define ROFDM0_DFSREPORT 0xcf4 -+#define ROFDM0_RXIQEXTANTA 0xca0 - #define ROFDM0_TXCOEFF1 0xca4 - #define ROFDM0_TXCOEFF2 0xca8 - #define ROFDM0_TXCOEFF3 0xcac -@@ -1186,17 +1251,70 @@ - #define RTXAGC_B_MCS15_MCS12 0x868 - #define RTXAGC_B_CCK11_A_CCK2_11 0x86c - -+#define RFPGA0_IQK 0xe28 -+#define RTX_IQK_TONE_A 0xe30 -+#define RRX_IQK_TONE_A 0xe34 -+#define RTX_IQK_PI_A 0xe38 -+#define RRX_IQK_PI_A 0xe3c -+ -+#define RTX_IQK 0xe40 -+#define RRX_IQK 0xe44 -+#define RIQK_AGC_PTS 0xe48 -+#define RIQK_AGC_RSP 0xe4c -+#define RTX_IQK_TONE_B 0xe50 -+#define RRX_IQK_TONE_B 0xe54 -+#define RTX_IQK_PI_B 0xe58 -+#define RRX_IQK_PI_B 0xe5c -+#define RIQK_AGC_CONT 0xe60 -+ -+#define RBLUE_TOOTH 0xe6c -+#define RRX_WAIT_CCA 0xe70 -+#define RTX_CCK_RFON 0xe74 -+#define RTX_CCK_BBON 0xe78 -+#define RTX_OFDM_RFON 0xe7c -+#define RTX_OFDM_BBON 0xe80 -+#define RTX_TO_RX 0xe84 -+#define RTX_TO_TX 0xe88 -+#define RRX_CCK 0xe8c -+ -+#define RTX_POWER_BEFORE_IQK_A 0xe94 -+#define RTX_POWER_AFTER_IQK_A 0xe9c -+ -+#define RRX_POWER_BEFORE_IQK_A 0xea0 -+#define RRX_POWER_BEFORE_IQK_A_2 0xea4 -+#define RRX_POWER_AFTER_IQK_A 0xea8 -+#define RRX_POWER_AFTER_IQK_A_2 0xeac -+ -+#define RTX_POWER_BEFORE_IQK_B 0xeb4 -+#define RTX_POWER_AFTER_IQK_B 0xebc -+ -+#define RRX_POWER_BEFORE_IQK_B 0xec0 -+#define RRX_POWER_BEFORE_IQK_B_2 0xec4 -+#define RRX_POWER_AFTER_IQK_B 0xec8 -+#define RRX_POWER_AFTER_IQK_B_2 0xecc -+ -+#define MASK_IQK_RESULT 0x03ff0000 -+ -+#define RRX_OFDM 0xed0 -+#define RRX_WAIT_RIFS 0xed4 -+#define RRX_TO_RX 0xed8 -+#define RSTANDBY 0xedc -+#define RSLEEP 0xee0 -+#define RPMPD_ANAEN 0xeec -+ - /* RL6052 Register definition */ - #define RF_AC 0x00 - - #define RF_IQADJ_G1 0x01 - #define RF_IQADJ_G2 0x02 -+#define RF_BS_PA_APSET_G1_G4 0x03 - #define RF_POW_TRSW 0x05 - - #define RF_GAIN_RX 0x06 - #define RF_GAIN_TX 0x07 - - #define RF_TXM_IDAC 0x08 -+#define RF_TXPA_AG 0x0B - #define RF_BS_IQGEN 0x0F - - #define RF_MODE1 0x10 -diff --git a/drivers/net/wireless/realtek/rtlwifi/usb.c b/drivers/net/wireless/realtek/rtlwifi/usb.c -index 6e8c87a2fae4..2ea72d9e3957 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/usb.c -+++ b/drivers/net/wireless/realtek/rtlwifi/usb.c -@@ -979,6 +979,9 @@ int rtl_usb_probe(struct usb_interface *intf, - usb_priv->dev.intf = intf; - usb_priv->dev.udev = udev; - usb_set_intfdata(intf, hw); -+ /* For dual MAC RTL8192DU, which has two interfaces. */ -+ rtlpriv->rtlhal.interfaceindex = -+ intf->altsetting[0].desc.bInterfaceNumber; - /* init cfg & intf_ops */ - rtlpriv->rtlhal.interface = INTF_USB; - rtlpriv->cfg = rtl_hal_cfg; -diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h -index 098db85e381c..4f1c21c130f4 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/wifi.h -+++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h -@@ -20,6 +20,7 @@ - #define MASKBYTE1 0xff00 - #define MASKBYTE2 0xff0000 - #define MASKBYTE3 0xff000000 -+#define MASKH3BYTES 0xffffff00 - #define MASKHWORD 0xffff0000 - #define MASKLWORD 0x0000ffff - #define MASKDWORD 0xffffffff -@@ -48,6 +49,10 @@ - #define MASK20BITS 0xfffff - #define RFREG_OFFSET_MASK 0xfffff - -+/* For dual MAC RTL8192DU */ -+#define MAC0_ACCESS_PHY1 0x4000 -+#define MAC1_ACCESS_PHY0 0x2000 -+ - #define RF_CHANGE_BY_INIT 0 - #define RF_CHANGE_BY_IPS BIT(28) - #define RF_CHANGE_BY_PS BIT(29) --- -2.34.1 - diff --git a/packages/linux/patches/rtlwifi/6.10/0007-6.10-wifi-rtlwifi-Ignore-IEEE80211_CONF_CHAN.patch b/packages/linux/patches/rtlwifi/6.10/0007-6.10-wifi-rtlwifi-Ignore-IEEE80211_CONF_CHAN.patch deleted file mode 100644 index 2d3e89a7cc..0000000000 --- a/packages/linux/patches/rtlwifi/6.10/0007-6.10-wifi-rtlwifi-Ignore-IEEE80211_CONF_CHAN.patch +++ /dev/null @@ -1,52 +0,0 @@ -From d34a7e456b723f5b5b11834abd39f46352d2b776 Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Wed, 29 May 2024 20:19:47 +0300 -Subject: [PATCH 07/07] 6.10: wifi: rtlwifi: Ignore - IEEE80211_CONF_CHANGE_RETRY_LIMITS - -Since commit 0a44dfc07074 ("wifi: mac80211: simplify non-chanctx -drivers") ieee80211_hw_config() is no longer called with changed = ~0. -rtlwifi relied on ~0 in order to ignore the default retry limits of -4/7, preferring 48/48 in station mode and 7/7 in AP/IBSS. - -RTL8192DU has a lot of packet loss with the default limits from -mac80211. Fix it by ignoring IEEE80211_CONF_CHANGE_RETRY_LIMITS -completely, because it's the simplest solution. - -Link: https://lore.kernel.org/linux-wireless/cedd13d7691f4692b2a2fa5a24d44a22@realtek.com/ -Cc: stable@vger.kernel.org # 6.9.x -Signed-off-by: Bitterblue Smith -Acked-by: Ping-Ke Shih ---- - drivers/net/wireless/realtek/rtlwifi/core.c | 15 --------------- - 1 file changed, 15 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtlwifi/core.c b/drivers/net/wireless/realtek/rtlwifi/core.c -index 2e60a6991ca1..42b7db12b1bd 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/core.c -+++ b/drivers/net/wireless/realtek/rtlwifi/core.c -@@ -633,21 +633,6 @@ static int rtl_op_config(struct ieee80211_hw *hw, u32 changed) - } - } - -- if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) { -- rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, -- "IEEE80211_CONF_CHANGE_RETRY_LIMITS %x\n", -- hw->conf.long_frame_max_tx_count); -- /* brought up everything changes (changed == ~0) indicates first -- * open, so use our default value instead of that of wiphy. -- */ -- if (changed != ~0) { -- mac->retry_long = hw->conf.long_frame_max_tx_count; -- mac->retry_short = hw->conf.long_frame_max_tx_count; -- rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, -- (u8 *)(&hw->conf.long_frame_max_tx_count)); -- } -- } -- - if (changed & IEEE80211_CONF_CHANGE_CHANNEL && - !rtlpriv->proximity.proxim_on) { - struct ieee80211_channel *channel = hw->conf.chandef.chan; --- -2.34.1 - diff --git a/packages/linux/patches/rtlwifi/6.10/0008-6.10-wifi-rtw88-Shared-module-for-rtw8723x-devices.patch b/packages/linux/patches/rtlwifi/6.10/0008-6.10-wifi-rtw88-Shared-module-for-rtw8723x-devices.patch deleted file mode 100644 index f3b0f9d7ec..0000000000 --- a/packages/linux/patches/rtlwifi/6.10/0008-6.10-wifi-rtw88-Shared-module-for-rtw8723x-devices.patch +++ /dev/null @@ -1,2324 +0,0 @@ -From ff88b74882669e8b1931730b2401dbc2bece1355 Mon Sep 17 00:00:00 2001 -From: Fiona Klute -Date: Mon, 11 Mar 2024 11:37:05 +0100 -Subject: [PATCH] wifi: rtw88: Shared module for rtw8723x devices - -The already supported 8723d chip is very similar to 8703b/8723cs, -split code that can be shared into a new module. The spec definition -tables are combined into a struct so we only need one EXPORT_SYMBOL -for them all. - -Acked-by: Ping-Ke Shih -Tested-by: Pavel Machek -Signed-off-by: Fiona Klute -Signed-off-by: Kalle Valo -Link: https://msgid.link/20240311103735.615541-2-fiona.klute@gmx.de ---- - drivers/net/wireless/realtek/rtw88/Kconfig | 4 + - drivers/net/wireless/realtek/rtw88/Makefile | 3 + - drivers/net/wireless/realtek/rtw88/rtw8723d.c | 673 ++---------------- - drivers/net/wireless/realtek/rtw88/rtw8723d.h | 269 +------ - drivers/net/wireless/realtek/rtw88/rtw8723x.c | 562 +++++++++++++++ - drivers/net/wireless/realtek/rtw88/rtw8723x.h | 496 +++++++++++++ - 6 files changed, 1107 insertions(+), 900 deletions(-) - create mode 100644 drivers/net/wireless/realtek/rtw88/rtw8723x.c - create mode 100644 drivers/net/wireless/realtek/rtw88/rtw8723x.h - -diff --git a/drivers/net/wireless/realtek/rtw88/Kconfig b/drivers/net/wireless/realtek/rtw88/Kconfig -index cffad1c012499e..07b5b2f6eef704 100644 ---- a/drivers/net/wireless/realtek/rtw88/Kconfig -+++ b/drivers/net/wireless/realtek/rtw88/Kconfig -@@ -28,8 +28,12 @@ config RTW88_8822B - config RTW88_8822C - tristate - -+config RTW88_8723X -+ tristate -+ - config RTW88_8723D - tristate -+ select RTW88_8723X - - config RTW88_8821C - tristate -diff --git a/drivers/net/wireless/realtek/rtw88/Makefile b/drivers/net/wireless/realtek/rtw88/Makefile -index fd212c09d88a9e..22516c984608f3 100644 ---- a/drivers/net/wireless/realtek/rtw88/Makefile -+++ b/drivers/net/wireless/realtek/rtw88/Makefile -@@ -44,6 +44,9 @@ rtw88_8822cs-objs := rtw8822cs.o - obj-$(CONFIG_RTW88_8822CU) += rtw88_8822cu.o - rtw88_8822cu-objs := rtw8822cu.o - -+obj-$(CONFIG_RTW88_8723X) += rtw88_8723x.o -+rtw88_8723x-objs := rtw8723x.o -+ - obj-$(CONFIG_RTW88_8723D) += rtw88_8723d.o - rtw88_8723d-objs := rtw8723d.o rtw8723d_table.o - -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8723d.c b/drivers/net/wireless/realtek/rtw88/rtw8723d.c -index c575476a002079..f8df4c84d39f73 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8723d.c -+++ b/drivers/net/wireless/realtek/rtw88/rtw8723d.c -@@ -9,36 +9,13 @@ - #include "tx.h" - #include "rx.h" - #include "phy.h" -+#include "rtw8723x.h" - #include "rtw8723d.h" - #include "rtw8723d_table.h" - #include "mac.h" - #include "reg.h" - #include "debug.h" - --static const struct rtw_hw_reg rtw8723d_txagc[] = { -- [DESC_RATE1M] = { .addr = 0xe08, .mask = 0x0000ff00 }, -- [DESC_RATE2M] = { .addr = 0x86c, .mask = 0x0000ff00 }, -- [DESC_RATE5_5M] = { .addr = 0x86c, .mask = 0x00ff0000 }, -- [DESC_RATE11M] = { .addr = 0x86c, .mask = 0xff000000 }, -- [DESC_RATE6M] = { .addr = 0xe00, .mask = 0x000000ff }, -- [DESC_RATE9M] = { .addr = 0xe00, .mask = 0x0000ff00 }, -- [DESC_RATE12M] = { .addr = 0xe00, .mask = 0x00ff0000 }, -- [DESC_RATE18M] = { .addr = 0xe00, .mask = 0xff000000 }, -- [DESC_RATE24M] = { .addr = 0xe04, .mask = 0x000000ff }, -- [DESC_RATE36M] = { .addr = 0xe04, .mask = 0x0000ff00 }, -- [DESC_RATE48M] = { .addr = 0xe04, .mask = 0x00ff0000 }, -- [DESC_RATE54M] = { .addr = 0xe04, .mask = 0xff000000 }, -- [DESC_RATEMCS0] = { .addr = 0xe10, .mask = 0x000000ff }, -- [DESC_RATEMCS1] = { .addr = 0xe10, .mask = 0x0000ff00 }, -- [DESC_RATEMCS2] = { .addr = 0xe10, .mask = 0x00ff0000 }, -- [DESC_RATEMCS3] = { .addr = 0xe10, .mask = 0xff000000 }, -- [DESC_RATEMCS4] = { .addr = 0xe14, .mask = 0x000000ff }, -- [DESC_RATEMCS5] = { .addr = 0xe14, .mask = 0x0000ff00 }, -- [DESC_RATEMCS6] = { .addr = 0xe14, .mask = 0x00ff0000 }, -- [DESC_RATEMCS7] = { .addr = 0xe14, .mask = 0xff000000 }, --}; -- --#define WLAN_TXQ_RPT_EN 0x1F - #define WLAN_SLOT_TIME 0x09 - #define WLAN_RL_VAL 0x3030 - #define WLAN_BAR_VAL 0x0201ffff -@@ -65,34 +42,6 @@ static const struct rtw_hw_reg rtw8723d_txagc[] = { - #define WLAN_LTR_CTRL1 0xCB004010 - #define WLAN_LTR_CTRL2 0x01233425 - --static void rtw8723d_lck(struct rtw_dev *rtwdev) --{ -- u32 lc_cal; -- u8 val_ctx, rf_val; -- int ret; -- -- val_ctx = rtw_read8(rtwdev, REG_CTX); -- if ((val_ctx & BIT_MASK_CTX_TYPE) != 0) -- rtw_write8(rtwdev, REG_CTX, val_ctx & ~BIT_MASK_CTX_TYPE); -- else -- rtw_write8(rtwdev, REG_TXPAUSE, 0xFF); -- lc_cal = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); -- -- rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal | BIT_LCK); -- -- ret = read_poll_timeout(rtw_read_rf, rf_val, rf_val != 0x1, -- 10000, 1000000, false, -- rtwdev, RF_PATH_A, RF_CFGCH, BIT_LCK); -- if (ret) -- rtw_warn(rtwdev, "failed to poll LCK status bit\n"); -- -- rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal); -- if ((val_ctx & BIT_MASK_CTX_TYPE) != 0) -- rtw_write8(rtwdev, REG_CTX, val_ctx); -- else -- rtw_write8(rtwdev, REG_TXPAUSE, 0x00); --} -- - static const u32 rtw8723d_ofdm_swing_table[] = { - 0x0b40002d, 0x0c000030, 0x0cc00033, 0x0d800036, 0x0e400039, 0x0f00003c, - 0x10000040, 0x11000044, 0x12000048, 0x1300004c, 0x14400051, 0x15800056, -@@ -196,7 +145,7 @@ static void rtw8723d_phy_set_param(struct rtw_dev *rtwdev) - - rtw_write16_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN); - -- rtw8723d_lck(rtwdev); -+ rtw8723x_lck(rtwdev); - - rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); - rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20); -@@ -204,67 +153,6 @@ static void rtw8723d_phy_set_param(struct rtw_dev *rtwdev) - rtw8723d_pwrtrack_init(rtwdev); - } - --static void rtw8723de_efuse_parsing(struct rtw_efuse *efuse, -- struct rtw8723d_efuse *map) --{ -- ether_addr_copy(efuse->addr, map->e.mac_addr); --} -- --static void rtw8723du_efuse_parsing(struct rtw_efuse *efuse, -- struct rtw8723d_efuse *map) --{ -- ether_addr_copy(efuse->addr, map->u.mac_addr); --} -- --static void rtw8723ds_efuse_parsing(struct rtw_efuse *efuse, -- struct rtw8723d_efuse *map) --{ -- ether_addr_copy(efuse->addr, map->s.mac_addr); --} -- --static int rtw8723d_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) --{ -- struct rtw_efuse *efuse = &rtwdev->efuse; -- struct rtw8723d_efuse *map; -- int i; -- -- map = (struct rtw8723d_efuse *)log_map; -- -- efuse->rfe_option = 0; -- efuse->rf_board_option = map->rf_board_option; -- efuse->crystal_cap = map->xtal_k; -- efuse->pa_type_2g = map->pa_type; -- efuse->lna_type_2g = map->lna_type_2g[0]; -- efuse->channel_plan = map->channel_plan; -- efuse->country_code[0] = map->country_code[0]; -- efuse->country_code[1] = map->country_code[1]; -- efuse->bt_setting = map->rf_bt_setting; -- efuse->regd = map->rf_board_option & 0x7; -- efuse->thermal_meter[0] = map->thermal_meter; -- efuse->thermal_meter_k = map->thermal_meter; -- efuse->afe = map->afe; -- -- for (i = 0; i < 4; i++) -- efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; -- -- switch (rtw_hci_type(rtwdev)) { -- case RTW_HCI_TYPE_PCIE: -- rtw8723de_efuse_parsing(efuse, map); -- break; -- case RTW_HCI_TYPE_USB: -- rtw8723du_efuse_parsing(efuse, map); -- break; -- case RTW_HCI_TYPE_SDIO: -- rtw8723ds_efuse_parsing(efuse, map); -- break; -- default: -- /* unsupported now */ -- return -ENOTSUPP; -- } -- -- return 0; --} -- - static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, - struct rtw_rx_pkt_stat *pkt_stat) - { -@@ -540,297 +428,11 @@ static void rtw8723d_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, - rtw8723d_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); - } - --#define BIT_CFENDFORM BIT(9) --#define BIT_WMAC_TCR_ERR0 BIT(12) --#define BIT_WMAC_TCR_ERR1 BIT(13) --#define BIT_TCR_CFG (BIT_CFENDFORM | BIT_WMAC_TCR_ERR0 | \ -- BIT_WMAC_TCR_ERR1) --#define WLAN_RX_FILTER0 0xFFFF --#define WLAN_RX_FILTER1 0x400 --#define WLAN_RX_FILTER2 0xFFFF --#define WLAN_RCR_CFG 0x700060CE -- --static int rtw8723d_mac_init(struct rtw_dev *rtwdev) --{ -- rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); -- rtw_write32(rtwdev, REG_TCR, BIT_TCR_CFG); -- -- rtw_write16(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); -- rtw_write16(rtwdev, REG_RXFLTMAP1, WLAN_RX_FILTER1); -- rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); -- rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); -- -- rtw_write32(rtwdev, REG_INT_MIG, 0); -- rtw_write32(rtwdev, REG_MCUTST_1, 0x0); -- -- rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA); -- rtw_write8(rtwdev, REG_2ND_CCA_CTRL, 0); -- -- return 0; --} -- - static void rtw8723d_shutdown(struct rtw_dev *rtwdev) - { - rtw_write16_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS); - } - --static void rtw8723d_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) --{ -- u8 ldo_pwr; -- -- ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); -- if (enable) { -- ldo_pwr &= ~BIT_MASK_LDO25_VOLTAGE; -- ldo_pwr |= (BIT_LDO25_VOLTAGE_V25 << 4) | BIT_LDO25_EN; -- } else { -- ldo_pwr &= ~BIT_LDO25_EN; -- } -- rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); --} -- --static void --rtw8723d_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) --{ -- struct rtw_hal *hal = &rtwdev->hal; -- const struct rtw_hw_reg *txagc; -- u8 rate, pwr_index; -- int j; -- -- for (j = 0; j < rtw_rate_size[rs]; j++) { -- rate = rtw_rate_section[rs][j]; -- pwr_index = hal->tx_pwr_tbl[path][rate]; -- -- if (rate >= ARRAY_SIZE(rtw8723d_txagc)) { -- rtw_warn(rtwdev, "rate 0x%x isn't supported\n", rate); -- continue; -- } -- txagc = &rtw8723d_txagc[rate]; -- if (!txagc->addr) { -- rtw_warn(rtwdev, "rate 0x%x isn't defined\n", rate); -- continue; -- } -- -- rtw_write32_mask(rtwdev, txagc->addr, txagc->mask, pwr_index); -- } --} -- --static void rtw8723d_set_tx_power_index(struct rtw_dev *rtwdev) --{ -- struct rtw_hal *hal = &rtwdev->hal; -- int rs, path; -- -- for (path = 0; path < hal->rf_path_num; path++) { -- for (rs = 0; rs <= RTW_RATE_SECTION_HT_1S; rs++) -- rtw8723d_set_tx_power_index_by_rate(rtwdev, path, rs); -- } --} -- --static void rtw8723d_efuse_grant(struct rtw_dev *rtwdev, bool on) --{ -- if (on) { -- rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); -- -- rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR); -- rtw_write16_set(rtwdev, REG_SYS_CLKR, BIT_LOADER_CLK_EN | BIT_ANA8M); -- } else { -- rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); -- } --} -- --static void rtw8723d_false_alarm_statistics(struct rtw_dev *rtwdev) --{ -- struct rtw_dm_info *dm_info = &rtwdev->dm_info; -- u32 cck_fa_cnt; -- u32 ofdm_fa_cnt; -- u32 crc32_cnt; -- u32 val32; -- -- /* hold counter */ -- rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 1); -- rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 1); -- rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KEEP, 1); -- rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KEEP, 1); -- -- cck_fa_cnt = rtw_read32_mask(rtwdev, REG_CCK_FA_LSB_11N, MASKBYTE0); -- cck_fa_cnt += rtw_read32_mask(rtwdev, REG_CCK_FA_MSB_11N, MASKBYTE3) << 8; -- -- val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE1_11N); -- ofdm_fa_cnt = u32_get_bits(val32, BIT_MASK_OFDM_FF_CNT); -- ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_SF_CNT); -- val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE2_11N); -- dm_info->ofdm_cca_cnt = u32_get_bits(val32, BIT_MASK_OFDM_CCA_CNT); -- ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_PF_CNT); -- val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE3_11N); -- ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_RI_CNT); -- ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_CRC_CNT); -- val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE4_11N); -- ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_MNS_CNT); -- -- dm_info->cck_fa_cnt = cck_fa_cnt; -- dm_info->ofdm_fa_cnt = ofdm_fa_cnt; -- dm_info->total_fa_cnt = cck_fa_cnt + ofdm_fa_cnt; -- -- dm_info->cck_err_cnt = rtw_read32(rtwdev, REG_IGI_C_11N); -- dm_info->cck_ok_cnt = rtw_read32(rtwdev, REG_IGI_D_11N); -- crc32_cnt = rtw_read32(rtwdev, REG_OFDM_CRC32_CNT_11N); -- dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_ERR); -- dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_OK); -- crc32_cnt = rtw_read32(rtwdev, REG_HT_CRC32_CNT_11N); -- dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_ERR); -- dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_OK); -- dm_info->vht_err_cnt = 0; -- dm_info->vht_ok_cnt = 0; -- -- val32 = rtw_read32(rtwdev, REG_CCK_CCA_CNT_11N); -- dm_info->cck_cca_cnt = (u32_get_bits(val32, BIT_MASK_CCK_FA_MSB) << 8) | -- u32_get_bits(val32, BIT_MASK_CCK_FA_LSB); -- dm_info->total_cca_cnt = dm_info->cck_cca_cnt + dm_info->ofdm_cca_cnt; -- -- /* reset counter */ -- rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 1); -- rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0); -- rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 1); -- rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0); -- rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0); -- rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 0); -- rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 0); -- rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 2); -- rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 0); -- rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 2); -- rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 1); -- rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 0); --} -- --static const u32 iqk_adda_regs[] = { -- 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, -- 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec --}; -- --static const u32 iqk_mac8_regs[] = {0x522, 0x550, 0x551}; --static const u32 iqk_mac32_regs[] = {0x40}; -- --static const u32 iqk_bb_regs[] = { -- 0xc04, 0xc08, 0x874, 0xb68, 0xb6c, 0x870, 0x860, 0x864, 0xa04 --}; -- --#define IQK_ADDA_REG_NUM ARRAY_SIZE(iqk_adda_regs) --#define IQK_MAC8_REG_NUM ARRAY_SIZE(iqk_mac8_regs) --#define IQK_MAC32_REG_NUM ARRAY_SIZE(iqk_mac32_regs) --#define IQK_BB_REG_NUM ARRAY_SIZE(iqk_bb_regs) -- --struct iqk_backup_regs { -- u32 adda[IQK_ADDA_REG_NUM]; -- u8 mac8[IQK_MAC8_REG_NUM]; -- u32 mac32[IQK_MAC32_REG_NUM]; -- u32 bb[IQK_BB_REG_NUM]; -- -- u32 lte_path; -- u32 lte_gnt; -- -- u32 bb_sel_btg; -- u8 btg_sel; -- -- u8 igia; -- u8 igib; --}; -- --static void rtw8723d_iqk_backup_regs(struct rtw_dev *rtwdev, -- struct iqk_backup_regs *backup) --{ -- int i; -- -- for (i = 0; i < IQK_ADDA_REG_NUM; i++) -- backup->adda[i] = rtw_read32(rtwdev, iqk_adda_regs[i]); -- -- for (i = 0; i < IQK_MAC8_REG_NUM; i++) -- backup->mac8[i] = rtw_read8(rtwdev, iqk_mac8_regs[i]); -- for (i = 0; i < IQK_MAC32_REG_NUM; i++) -- backup->mac32[i] = rtw_read32(rtwdev, iqk_mac32_regs[i]); -- -- for (i = 0; i < IQK_BB_REG_NUM; i++) -- backup->bb[i] = rtw_read32(rtwdev, iqk_bb_regs[i]); -- -- backup->igia = rtw_read32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0); -- backup->igib = rtw_read32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0); -- -- backup->bb_sel_btg = rtw_read32(rtwdev, REG_BB_SEL_BTG); --} -- --static void rtw8723d_iqk_restore_regs(struct rtw_dev *rtwdev, -- const struct iqk_backup_regs *backup) --{ -- int i; -- -- for (i = 0; i < IQK_ADDA_REG_NUM; i++) -- rtw_write32(rtwdev, iqk_adda_regs[i], backup->adda[i]); -- -- for (i = 0; i < IQK_MAC8_REG_NUM; i++) -- rtw_write8(rtwdev, iqk_mac8_regs[i], backup->mac8[i]); -- for (i = 0; i < IQK_MAC32_REG_NUM; i++) -- rtw_write32(rtwdev, iqk_mac32_regs[i], backup->mac32[i]); -- -- for (i = 0; i < IQK_BB_REG_NUM; i++) -- rtw_write32(rtwdev, iqk_bb_regs[i], backup->bb[i]); -- -- rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); -- rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, backup->igia); -- -- rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, 0x50); -- rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, backup->igib); -- -- rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x01008c00); -- rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x01008c00); --} -- --static void rtw8723d_iqk_backup_path_ctrl(struct rtw_dev *rtwdev, -- struct iqk_backup_regs *backup) --{ -- backup->btg_sel = rtw_read8(rtwdev, REG_BTG_SEL); -- rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] original 0x67 = 0x%x\n", -- backup->btg_sel); --} -- --static void rtw8723d_iqk_config_path_ctrl(struct rtw_dev *rtwdev) --{ -- rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1); -- rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] set 0x67 = 0x%x\n", -- rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); --} -- --static void rtw8723d_iqk_restore_path_ctrl(struct rtw_dev *rtwdev, -- const struct iqk_backup_regs *backup) --{ -- rtw_write8(rtwdev, REG_BTG_SEL, backup->btg_sel); -- rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] restore 0x67 = 0x%x\n", -- rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); --} -- --static void rtw8723d_iqk_backup_lte_path_gnt(struct rtw_dev *rtwdev, -- struct iqk_backup_regs *backup) --{ -- backup->lte_path = rtw_read32(rtwdev, REG_LTECOEX_PATH_CONTROL); -- rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0038); -- mdelay(1); -- backup->lte_gnt = rtw_read32(rtwdev, REG_LTECOEX_READ_DATA); -- rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] OriginalGNT = 0x%x\n", -- backup->lte_gnt); --} -- --static void rtw8723d_iqk_config_lte_path_gnt(struct rtw_dev *rtwdev) --{ -- rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, 0x0000ff00); -- rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc0020038); -- rtw_write32_mask(rtwdev, REG_LTECOEX_PATH_CONTROL, BIT_LTE_MUX_CTRL_PATH, 0x1); --} -- --static void rtw8723d_iqk_restore_lte_path_gnt(struct rtw_dev *rtwdev, -- const struct iqk_backup_regs *bak) --{ -- rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, bak->lte_gnt); -- rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc00f0038); -- rtw_write32(rtwdev, REG_LTECOEX_PATH_CONTROL, bak->lte_path); --} -- - struct rtw_8723d_iqk_cfg { - const char *name; - u32 val_bb_sel_btg; -@@ -930,6 +532,8 @@ static u8 rtw8723d_iqk_check_rx_failed(struct rtw_dev *rtwdev, - return 0; - } - -+#define IQK_LTE_WRITE_VAL_8723D 0x0000ff00 -+ - static void rtw8723d_iqk_one_shot(struct rtw_dev *rtwdev, bool tx, - const struct rtw_8723d_iqk_cfg *iqk_cfg) - { -@@ -937,7 +541,7 @@ static void rtw8723d_iqk_one_shot(struct rtw_dev *rtwdev, bool tx, - - /* enter IQK mode */ - rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); -- rtw8723d_iqk_config_lte_path_gnt(rtwdev); -+ rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8723D); - - rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0054); - mdelay(1); -@@ -959,9 +563,9 @@ static void rtw8723d_iqk_one_shot(struct rtw_dev *rtwdev, bool tx, - - static void rtw8723d_iqk_txrx_path_post(struct rtw_dev *rtwdev, - const struct rtw_8723d_iqk_cfg *iqk_cfg, -- const struct iqk_backup_regs *backup) -+ const struct rtw8723x_iqk_backup_regs *backup) - { -- rtw8723d_iqk_restore_lte_path_gnt(rtwdev, backup); -+ rtw8723x_iqk_restore_lte_path_gnt(rtwdev, backup); - rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg); - - /* leave IQK mode */ -@@ -974,7 +578,7 @@ static void rtw8723d_iqk_txrx_path_post(struct rtw_dev *rtwdev, - - static u8 rtw8723d_iqk_tx_path(struct rtw_dev *rtwdev, - const struct rtw_8723d_iqk_cfg *iqk_cfg, -- const struct iqk_backup_regs *backup) -+ const struct rtw8723x_iqk_backup_regs *backup) - { - u8 status; - -@@ -1033,7 +637,7 @@ static u8 rtw8723d_iqk_tx_path(struct rtw_dev *rtwdev, - - static u8 rtw8723d_iqk_rx_path(struct rtw_dev *rtwdev, - const struct rtw_8723d_iqk_cfg *iqk_cfg, -- const struct iqk_backup_regs *backup) -+ const struct rtw8723x_iqk_backup_regs *backup) - { - u32 tx_x, tx_y; - u8 status; -@@ -1220,14 +824,6 @@ void rtw8723d_iqk_fill_s0_matrix(struct rtw_dev *rtwdev, const s32 result[]) - result[IQK_S0_RX_Y]); - } - --static void rtw8723d_iqk_path_adda_on(struct rtw_dev *rtwdev) --{ -- int i; -- -- for (i = 0; i < IQK_ADDA_REG_NUM; i++) -- rtw_write32(rtwdev, iqk_adda_regs[i], 0x03c00016); --} -- - static void rtw8723d_iqk_config_mac(struct rtw_dev *rtwdev) - { - rtw_write8(rtwdev, REG_TXPAUSE, 0xff); -@@ -1245,70 +841,14 @@ void rtw8723d_iqk_rf_standby(struct rtw_dev *rtwdev, enum rtw_rf_path path) - rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); - } - --static --bool rtw8723d_iqk_similarity_cmp(struct rtw_dev *rtwdev, s32 result[][IQK_NR], -- u8 c1, u8 c2) --{ -- u32 i, j, diff; -- u32 bitmap = 0; -- u8 candidate[PATH_NR] = {IQK_ROUND_INVALID, IQK_ROUND_INVALID}; -- bool ret = true; -- -- s32 tmp1, tmp2; -- -- for (i = 0; i < IQK_NR; i++) { -- tmp1 = iqkxy_to_s32(result[c1][i]); -- tmp2 = iqkxy_to_s32(result[c2][i]); -- -- diff = abs(tmp1 - tmp2); -- -- if (diff <= MAX_TOLERANCE) -- continue; -- -- if ((i == IQK_S1_RX_X || i == IQK_S0_RX_X) && !bitmap) { -- if (result[c1][i] + result[c1][i + 1] == 0) -- candidate[i / IQK_SX_NR] = c2; -- else if (result[c2][i] + result[c2][i + 1] == 0) -- candidate[i / IQK_SX_NR] = c1; -- else -- bitmap |= BIT(i); -- } else { -- bitmap |= BIT(i); -- } -- } -- -- if (bitmap != 0) -- goto check_sim; -- -- for (i = 0; i < PATH_NR; i++) { -- if (candidate[i] == IQK_ROUND_INVALID) -- continue; -- -- for (j = i * IQK_SX_NR; j < i * IQK_SX_NR + 2; j++) -- result[IQK_ROUND_HYBRID][j] = result[candidate[i]][j]; -- ret = false; -- } -- -- return ret; -- --check_sim: -- for (i = 0; i < IQK_NR; i++) { -- j = i & ~1; /* 2 bits are a pair for IQ[X, Y] */ -- if (bitmap & GENMASK(j + 1, j)) -- continue; -- -- result[IQK_ROUND_HYBRID][i] = result[c1][i]; -- } -- -- return false; --} -+#define ADDA_ON_VAL_8723D 0x03c00016 - - static --void rtw8723d_iqk_precfg_path(struct rtw_dev *rtwdev, enum rtw8723d_path path) -+void rtw8723d_iqk_precfg_path(struct rtw_dev *rtwdev, enum rtw8723x_path path) - { - if (path == PATH_S0) { - rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_A); -- rtw8723d_iqk_path_adda_on(rtwdev); -+ rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8723D); - } - - rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); -@@ -1317,13 +857,13 @@ void rtw8723d_iqk_precfg_path(struct rtw_dev *rtwdev, enum rtw8723d_path path) - - if (path == PATH_S1) { - rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_B); -- rtw8723d_iqk_path_adda_on(rtwdev); -+ rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8723D); - } - } - - static - void rtw8723d_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t, -- const struct iqk_backup_regs *backup) -+ const struct rtw8723x_iqk_backup_regs *backup) - { - u32 i; - u8 s1_ok, s0_ok; -@@ -1331,7 +871,7 @@ void rtw8723d_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t, - rtw_dbg(rtwdev, RTW_DBG_RFK, - "[IQK] IQ Calibration for 1T1R_S0/S1 for %d times\n", t); - -- rtw8723d_iqk_path_adda_on(rtwdev); -+ rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8723D); - rtw8723d_iqk_config_mac(rtwdev); - rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf); - rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05611); -@@ -1427,7 +967,7 @@ static void rtw8723d_phy_calibration(struct rtw_dev *rtwdev) - { - struct rtw_dm_info *dm_info = &rtwdev->dm_info; - s32 result[IQK_ROUND_SIZE][IQK_NR]; -- struct iqk_backup_regs backup; -+ struct rtw8723x_iqk_backup_regs backup; - u8 i, j; - u8 final_candidate = IQK_ROUND_INVALID; - bool good; -@@ -1436,23 +976,23 @@ static void rtw8723d_phy_calibration(struct rtw_dev *rtwdev) - - memset(result, 0, sizeof(result)); - -- rtw8723d_iqk_backup_path_ctrl(rtwdev, &backup); -- rtw8723d_iqk_backup_lte_path_gnt(rtwdev, &backup); -- rtw8723d_iqk_backup_regs(rtwdev, &backup); -+ rtw8723x_iqk_backup_path_ctrl(rtwdev, &backup); -+ rtw8723x_iqk_backup_lte_path_gnt(rtwdev, &backup); -+ rtw8723x_iqk_backup_regs(rtwdev, &backup); - - for (i = IQK_ROUND_0; i <= IQK_ROUND_2; i++) { -- rtw8723d_iqk_config_path_ctrl(rtwdev); -- rtw8723d_iqk_config_lte_path_gnt(rtwdev); -+ rtw8723x_iqk_config_path_ctrl(rtwdev); -+ rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8723D); - - rtw8723d_iqk_one_round(rtwdev, result, i, &backup); - - if (i > IQK_ROUND_0) -- rtw8723d_iqk_restore_regs(rtwdev, &backup); -- rtw8723d_iqk_restore_lte_path_gnt(rtwdev, &backup); -- rtw8723d_iqk_restore_path_ctrl(rtwdev, &backup); -+ rtw8723x_iqk_restore_regs(rtwdev, &backup); -+ rtw8723x_iqk_restore_lte_path_gnt(rtwdev, &backup); -+ rtw8723x_iqk_restore_path_ctrl(rtwdev, &backup); - - for (j = IQK_ROUND_0; j < i; j++) { -- good = rtw8723d_iqk_similarity_cmp(rtwdev, result, j, i); -+ good = rtw8723x_iqk_similarity_cmp(rtwdev, result, j, i); - - if (good) { - final_candidate = j; -@@ -1546,26 +1086,6 @@ static void rtw8723d_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) - } - - /* for coex */ --static void rtw8723d_coex_cfg_init(struct rtw_dev *rtwdev) --{ -- /* enable TBTT nterrupt */ -- rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); -- -- /* BT report packet sample rate */ -- /* 0x790[5:0]=0x5 */ -- rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); -- -- /* enable BT counter statistics */ -- rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); -- -- /* enable PTA (3-wire function form BT side) */ -- rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); -- rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); -- -- /* enable PTA (tx/rx signal form WiFi side) */ -- rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); --} -- - static void rtw8723d_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) - { - } -@@ -1671,39 +1191,6 @@ static void rtw8723d_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) - } - } - --static u8 rtw8723d_pwrtrack_get_limit_ofdm(struct rtw_dev *rtwdev) --{ -- struct rtw_dm_info *dm_info = &rtwdev->dm_info; -- u8 tx_rate = dm_info->tx_rate; -- u8 limit_ofdm = 30; -- -- switch (tx_rate) { -- case DESC_RATE1M...DESC_RATE5_5M: -- case DESC_RATE11M: -- break; -- case DESC_RATE6M...DESC_RATE48M: -- limit_ofdm = 36; -- break; -- case DESC_RATE54M: -- limit_ofdm = 34; -- break; -- case DESC_RATEMCS0...DESC_RATEMCS2: -- limit_ofdm = 38; -- break; -- case DESC_RATEMCS3...DESC_RATEMCS4: -- limit_ofdm = 36; -- break; -- case DESC_RATEMCS5...DESC_RATEMCS7: -- limit_ofdm = 34; -- break; -- default: -- rtw_warn(rtwdev, "pwrtrack unhandled tx_rate 0x%x\n", tx_rate); -- break; -- } -- -- return limit_ofdm; --} -- - static void rtw8723d_set_iqk_matrix_by_result(struct rtw_dev *rtwdev, - u32 ofdm_swing, u8 rf_path) - { -@@ -1845,7 +1332,7 @@ static void rtw8723d_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) - s8 final_ofdm_swing_index; - s8 final_cck_swing_index; - -- limit_ofdm = rtw8723d_pwrtrack_get_limit_ofdm(rtwdev); -+ limit_ofdm = rtw8723x_pwrtrack_get_limit_ofdm(rtwdev); - - final_ofdm_swing_index = RTW_DEF_OFDM_SWING_INDEX + - dm_info->delta_power_index[path]; -@@ -1873,26 +1360,6 @@ static void rtw8723d_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) - rtw_phy_set_tx_power_level(rtwdev, hal->current_channel); - } - --static void rtw8723d_pwrtrack_set_xtal(struct rtw_dev *rtwdev, u8 therm_path, -- u8 delta) --{ -- struct rtw_dm_info *dm_info = &rtwdev->dm_info; -- const struct rtw_pwr_track_tbl *tbl = rtwdev->chip->pwr_track_tbl; -- const s8 *pwrtrk_xtal; -- s8 xtal_cap; -- -- if (dm_info->thermal_avg[therm_path] > -- rtwdev->efuse.thermal_meter[therm_path]) -- pwrtrk_xtal = tbl->pwrtrk_xtal_p; -- else -- pwrtrk_xtal = tbl->pwrtrk_xtal_n; -- -- xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; -- xtal_cap = clamp_t(s8, xtal_cap + pwrtrk_xtal[delta], 0, 0x3F); -- rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, -- xtal_cap | (xtal_cap << 6)); --} -- - static void rtw8723d_phy_pwrtrack(struct rtw_dev *rtwdev) - { - struct rtw_dm_info *dm_info = &rtwdev->dm_info; -@@ -1912,7 +1379,7 @@ static void rtw8723d_phy_pwrtrack(struct rtw_dev *rtwdev) - do_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev); - - if (do_iqk) -- rtw8723d_lck(rtwdev); -+ rtw8723x_lck(rtwdev); - - if (dm_info->pwr_trk_init_trigger) - dm_info->pwr_trk_init_trigger = false; -@@ -1937,7 +1404,7 @@ static void rtw8723d_phy_pwrtrack(struct rtw_dev *rtwdev) - rtw8723d_pwrtrack_set(rtwdev, path); - } - -- rtw8723d_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta); -+ rtw8723x_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta); - - iqk: - if (do_iqk) -@@ -1963,49 +1430,29 @@ static void rtw8723d_pwr_track(struct rtw_dev *rtwdev) - dm_info->pwr_trk_triggered = false; - } - --static void rtw8723d_fill_txdesc_checksum(struct rtw_dev *rtwdev, -- struct rtw_tx_pkt_info *pkt_info, -- u8 *txdesc) --{ -- size_t words = 32 / 2; /* calculate the first 32 bytes (16 words) */ -- __le16 chksum = 0; -- __le16 *data = (__le16 *)(txdesc); -- struct rtw_tx_desc *tx_desc = (struct rtw_tx_desc *)txdesc; -- -- le32p_replace_bits(&tx_desc->w7, 0, RTW_TX_DESC_W7_TXDESC_CHECKSUM); -- -- while (words--) -- chksum ^= *data++; -- -- chksum = ~chksum; -- -- le32p_replace_bits(&tx_desc->w7, __le16_to_cpu(chksum), -- RTW_TX_DESC_W7_TXDESC_CHECKSUM); --} -- - static struct rtw_chip_ops rtw8723d_ops = { - .phy_set_param = rtw8723d_phy_set_param, -- .read_efuse = rtw8723d_read_efuse, -+ .read_efuse = rtw8723x_read_efuse, - .query_rx_desc = rtw8723d_query_rx_desc, - .set_channel = rtw8723d_set_channel, -- .mac_init = rtw8723d_mac_init, -+ .mac_init = rtw8723x_mac_init, - .shutdown = rtw8723d_shutdown, - .read_rf = rtw_phy_read_rf_sipi, - .write_rf = rtw_phy_write_rf_reg_sipi, -- .set_tx_power_index = rtw8723d_set_tx_power_index, -+ .set_tx_power_index = rtw8723x_set_tx_power_index, - .set_antenna = NULL, -- .cfg_ldo25 = rtw8723d_cfg_ldo25, -- .efuse_grant = rtw8723d_efuse_grant, -- .false_alarm_statistics = rtw8723d_false_alarm_statistics, -+ .cfg_ldo25 = rtw8723x_cfg_ldo25, -+ .efuse_grant = rtw8723x_efuse_grant, -+ .false_alarm_statistics = rtw8723x_false_alarm_statistics, - .phy_calibration = rtw8723d_phy_calibration, - .cck_pd_set = rtw8723d_phy_cck_pd_set, - .pwr_track = rtw8723d_pwr_track, - .config_bfee = NULL, - .set_gid_table = NULL, - .cfg_csi_rate = NULL, -- .fill_txdesc_checksum = rtw8723d_fill_txdesc_checksum, -+ .fill_txdesc_checksum = rtw8723x_fill_txdesc_checksum, - -- .coex_set_init = rtw8723d_coex_cfg_init, -+ .coex_set_init = rtw8723x_coex_cfg_init, - .coex_set_ant_switch = NULL, - .coex_set_gnt_fix = rtw8723d_coex_cfg_gnt_fix, - .coex_set_gnt_debug = rtw8723d_coex_cfg_gnt_debug, -@@ -2592,22 +2039,6 @@ static const struct rtw_rqpn rqpn_table_8723d[] = { - RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, - }; - --static const struct rtw_prioq_addrs prioq_addrs_8723d = { -- .prio[RTW_DMA_MAPPING_EXTRA] = { -- .rsvd = REG_RQPN_NPQ + 2, .avail = REG_RQPN_NPQ + 3, -- }, -- .prio[RTW_DMA_MAPPING_LOW] = { -- .rsvd = REG_RQPN + 1, .avail = REG_FIFOPAGE_CTRL_2 + 1, -- }, -- .prio[RTW_DMA_MAPPING_NORMAL] = { -- .rsvd = REG_RQPN_NPQ, .avail = REG_RQPN_NPQ + 1, -- }, -- .prio[RTW_DMA_MAPPING_HIGH] = { -- .rsvd = REG_RQPN, .avail = REG_FIFOPAGE_CTRL_2, -- }, -- .wsize = false, --}; -- - static const struct rtw_intf_phy_para pcie_gen1_param_8723d[] = { - {0x0008, 0x4a22, - RTW_IP_SEL_PHY, -@@ -2628,28 +2059,6 @@ static const struct rtw_intf_phy_para_table phy_para_table_8723d = { - .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8723d), - }; - --static const struct rtw_hw_reg rtw8723d_dig[] = { -- [0] = { .addr = 0xc50, .mask = 0x7f }, -- [1] = { .addr = 0xc50, .mask = 0x7f }, --}; -- --static const struct rtw_hw_reg rtw8723d_dig_cck[] = { -- [0] = { .addr = 0xa0c, .mask = 0x3f00 }, --}; -- --static const struct rtw_rf_sipi_addr rtw8723d_rf_sipi_addr[] = { -- [RF_PATH_A] = { .hssi_1 = 0x820, .lssi_read = 0x8a0, -- .hssi_2 = 0x824, .lssi_read_pi = 0x8b8}, -- [RF_PATH_B] = { .hssi_1 = 0x828, .lssi_read = 0x8a4, -- .hssi_2 = 0x82c, .lssi_read_pi = 0x8bc}, --}; -- --static const struct rtw_ltecoex_addr rtw8723d_ltecoex_addr = { -- .ctrl = REG_LTECOEX_CTRL, -- .wdata = REG_LTECOEX_WRITE_DATA, -- .rdata = REG_LTECOEX_READ_DATA, --}; -- - static const struct rtw_rfe_def rtw8723d_rfe_defs[] = { - [0] = { .phy_pg_tbl = &rtw8723d_bb_pg_tbl, - .txpwr_lmt_tbl = &rtw8723d_txpwr_lmt_tbl,}, -@@ -2770,14 +2179,14 @@ const struct rtw_chip_info rtw8723d_hw_spec = { - .pwr_off_seq = card_disable_flow_8723d, - .page_table = page_table_8723d, - .rqpn_table = rqpn_table_8723d, -- .prioq_addrs = &prioq_addrs_8723d, -+ .prioq_addrs = &rtw8723x_common.prioq_addrs, - .intf_table = &phy_para_table_8723d, -- .dig = rtw8723d_dig, -- .dig_cck = rtw8723d_dig_cck, -+ .dig = rtw8723x_common.dig, -+ .dig_cck = rtw8723x_common.dig_cck, - .rf_sipi_addr = {0x840, 0x844}, -- .rf_sipi_read_addr = rtw8723d_rf_sipi_addr, -+ .rf_sipi_read_addr = rtw8723x_common.rf_sipi_addr, - .fix_rf_phy_num = 2, -- .ltecoex_addr = &rtw8723d_ltecoex_addr, -+ .ltecoex_addr = &rtw8723x_common.ltecoex_addr, - .mac_tbl = &rtw8723d_mac_tbl, - .agc_tbl = &rtw8723d_agc_tbl, - .bb_tbl = &rtw8723d_bb_tbl, -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8723d.h b/drivers/net/wireless/realtek/rtw88/rtw8723d.h -index 2434e2480cbe27..fba06c9f480e55 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8723d.h -+++ b/drivers/net/wireless/realtek/rtw88/rtw8723d.h -@@ -5,90 +5,7 @@ - #ifndef __RTW8723D_H__ - #define __RTW8723D_H__ - --enum rtw8723d_path { -- PATH_S1, -- PATH_S0, -- PATH_NR, --}; -- --enum rtw8723d_iqk_round { -- IQK_ROUND_0, -- IQK_ROUND_1, -- IQK_ROUND_2, -- IQK_ROUND_HYBRID, -- IQK_ROUND_SIZE, -- IQK_ROUND_INVALID = 0xff, --}; -- --enum rtw8723d_iqk_result { -- IQK_S1_TX_X, -- IQK_S1_TX_Y, -- IQK_S1_RX_X, -- IQK_S1_RX_Y, -- IQK_S0_TX_X, -- IQK_S0_TX_Y, -- IQK_S0_RX_X, -- IQK_S0_RX_Y, -- IQK_NR, -- IQK_SX_NR = IQK_NR / PATH_NR, --}; -- --struct rtw8723de_efuse { -- u8 mac_addr[ETH_ALEN]; /* 0xd0 */ -- u8 vender_id[2]; -- u8 device_id[2]; -- u8 sub_vender_id[2]; -- u8 sub_device_id[2]; --}; -- --struct rtw8723du_efuse { -- u8 res4[48]; /* 0xd0 */ -- u8 vender_id[2]; /* 0x100 */ -- u8 product_id[2]; /* 0x102 */ -- u8 usb_option; /* 0x104 */ -- u8 res5[2]; /* 0x105 */ -- u8 mac_addr[ETH_ALEN]; /* 0x107 */ --}; -- --struct rtw8723ds_efuse { -- u8 res4[0x4a]; /* 0xd0 */ -- u8 mac_addr[ETH_ALEN]; /* 0x11a */ --}; -- --struct rtw8723d_efuse { -- __le16 rtl_id; -- u8 rsvd[2]; -- u8 afe; -- u8 rsvd1[11]; -- -- /* power index for four RF paths */ -- struct rtw_txpwr_idx txpwr_idx_table[4]; -- -- u8 channel_plan; /* 0xb8 */ -- u8 xtal_k; -- u8 thermal_meter; -- u8 iqk_lck; -- u8 pa_type; /* 0xbc */ -- u8 lna_type_2g[2]; /* 0xbd */ -- u8 lna_type_5g[2]; -- u8 rf_board_option; -- u8 rf_feature_option; -- u8 rf_bt_setting; -- u8 eeprom_version; -- u8 eeprom_customer_id; -- u8 tx_bb_swing_setting_2g; -- u8 res_c7; -- u8 tx_pwr_calibrate_rate; -- u8 rf_antenna_option; /* 0xc9 */ -- u8 rfe_option; -- u8 country_code[2]; -- u8 res[3]; -- union { -- struct rtw8723de_efuse e; -- struct rtw8723du_efuse u; -- struct rtw8723ds_efuse s; -- }; --}; -+#include "rtw8723x.h" - - extern const struct rtw_chip_info rtw8723d_hw_spec; - -@@ -114,193 +31,9 @@ extern const struct rtw_chip_info rtw8723d_hw_spec; - #define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \ - le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0)) - --static inline s32 iqkxy_to_s32(s32 val) --{ -- /* val is Q10.8 */ -- return sign_extend32(val, 9); --} -- --static inline s32 iqk_mult(s32 x, s32 y, s32 *ext) --{ -- /* x, y and return value are Q10.8 */ -- s32 t; -- -- t = x * y; -- if (ext) -- *ext = (t >> 7) & 0x1; /* Q.16 --> Q.9; get LSB of Q.9 */ -- -- return (t >> 8); /* Q.16 --> Q.8 */ --} -- --#define OFDM_SWING_A(swing) FIELD_GET(GENMASK(9, 0), swing) --#define OFDM_SWING_B(swing) FIELD_GET(GENMASK(15, 10), swing) --#define OFDM_SWING_C(swing) FIELD_GET(GENMASK(21, 16), swing) --#define OFDM_SWING_D(swing) FIELD_GET(GENMASK(31, 22), swing) - #define RTW_DEF_OFDM_SWING_INDEX 28 - #define RTW_DEF_CCK_SWING_INDEX 28 - --#define MAX_TOLERANCE 5 --#define IQK_TX_X_ERR 0x142 --#define IQK_TX_Y_ERR 0x42 --#define IQK_RX_X_UPPER 0x11a --#define IQK_RX_X_LOWER 0xe6 --#define IQK_RX_Y_LMT 0x1a --#define IQK_TX_OK BIT(0) --#define IQK_RX_OK BIT(1) --#define PATH_IQK_RETRY 2 -- --#define SPUR_THRES 0x16 - #define CCK_DFIR_NR 3 --#define DIS_3WIRE 0xccf000c0 --#define EN_3WIRE 0xccc000c0 --#define START_PSD 0x400000 --#define FREQ_CH13 0xfccd --#define FREQ_CH14 0xff9a --#define RFCFGCH_CHANNEL_MASK GENMASK(7, 0) --#define RFCFGCH_BW_MASK (BIT(11) | BIT(10)) --#define RFCFGCH_BW_20M (BIT(11) | BIT(10)) --#define RFCFGCH_BW_40M BIT(10) --#define BIT_MASK_RFMOD BIT(0) --#define BIT_LCK BIT(15) -- --#define REG_GPIO_INTM 0x0048 --#define REG_BTG_SEL 0x0067 --#define BIT_MASK_BTG_WL BIT(7) --#define REG_LTECOEX_PATH_CONTROL 0x0070 --#define REG_LTECOEX_CTRL 0x07c0 --#define REG_LTECOEX_WRITE_DATA 0x07c4 --#define REG_LTECOEX_READ_DATA 0x07c8 --#define REG_PSDFN 0x0808 --#define REG_BB_PWR_SAV1_11N 0x0874 --#define REG_ANA_PARAM1 0x0880 --#define REG_ANALOG_P4 0x088c --#define REG_PSDRPT 0x08b4 --#define REG_FPGA1_RFMOD 0x0900 --#define REG_BB_SEL_BTG 0x0948 --#define REG_BBRX_DFIR 0x0954 --#define BIT_MASK_RXBB_DFIR GENMASK(27, 24) --#define BIT_RXBB_DFIR_EN BIT(19) --#define REG_CCK0_SYS 0x0a00 --#define BIT_CCK_SIDE_BAND BIT(4) --#define REG_CCK_ANT_SEL_11N 0x0a04 --#define REG_PWRTH 0x0a08 --#define REG_CCK_FA_RST_11N 0x0a2c --#define BIT_MASK_CCK_CNT_KEEP BIT(12) --#define BIT_MASK_CCK_CNT_EN BIT(13) --#define BIT_MASK_CCK_CNT_KPEN (BIT_MASK_CCK_CNT_KEEP | BIT_MASK_CCK_CNT_EN) --#define BIT_MASK_CCK_FA_KEEP BIT(14) --#define BIT_MASK_CCK_FA_EN BIT(15) --#define BIT_MASK_CCK_FA_KPEN (BIT_MASK_CCK_FA_KEEP | BIT_MASK_CCK_FA_EN) --#define REG_CCK_FA_LSB_11N 0x0a5c --#define REG_CCK_FA_MSB_11N 0x0a58 --#define REG_CCK_CCA_CNT_11N 0x0a60 --#define BIT_MASK_CCK_FA_MSB GENMASK(7, 0) --#define BIT_MASK_CCK_FA_LSB GENMASK(15, 8) --#define REG_PWRTH2 0x0aa8 --#define REG_CSRATIO 0x0aaa --#define REG_OFDM_FA_HOLDC_11N 0x0c00 --#define BIT_MASK_OFDM_FA_KEEP BIT(31) --#define REG_BB_RX_PATH_11N 0x0c04 --#define REG_TRMUX_11N 0x0c08 --#define REG_OFDM_FA_RSTC_11N 0x0c0c --#define BIT_MASK_OFDM_FA_RST BIT(31) --#define REG_A_RXIQI 0x0c14 --#define BIT_MASK_RXIQ_S1_X 0x000003FF --#define BIT_MASK_RXIQ_S1_Y1 0x0000FC00 --#define BIT_SET_RXIQ_S1_Y1(y) ((y) & 0x3F) --#define REG_OFDM0_RXDSP 0x0c40 --#define BIT_MASK_RXDSP GENMASK(28, 24) --#define BIT_EN_RXDSP BIT(9) --#define REG_OFDM_0_ECCA_THRESHOLD 0x0c4c --#define BIT_MASK_OFDM0_EXT_A BIT(31) --#define BIT_MASK_OFDM0_EXT_C BIT(29) --#define BIT_MASK_OFDM0_EXTS (BIT(31) | BIT(29) | BIT(28)) --#define BIT_SET_OFDM0_EXTS(a, c, d) (((a) << 31) | ((c) << 29) | ((d) << 28)) --#define REG_OFDM0_XAAGC1 0x0c50 --#define REG_OFDM0_XBAGC1 0x0c58 --#define REG_AGCRSSI 0x0c78 --#define REG_OFDM_0_XA_TX_IQ_IMBALANCE 0x0c80 --#define BIT_MASK_TXIQ_ELM_A 0x03ff --#define BIT_SET_TXIQ_ELM_ACD(a, c, d) (((d) << 22) | (((c) & 0x3F) << 16) | \ -- ((a) & 0x03ff)) --#define BIT_MASK_TXIQ_ELM_C GENMASK(21, 16) --#define BIT_SET_TXIQ_ELM_C2(c) ((c) & 0x3F) --#define BIT_MASK_TXIQ_ELM_D GENMASK(31, 22) --#define REG_TXIQK_MATRIXA_LSB2_11N 0x0c94 --#define BIT_SET_TXIQ_ELM_C1(c) (((c) & 0x000003C0) >> 6) --#define REG_RXIQK_MATRIX_LSB_11N 0x0ca0 --#define BIT_MASK_RXIQ_S1_Y2 0xF0000000 --#define BIT_SET_RXIQ_S1_Y2(y) (((y) >> 6) & 0xF) --#define REG_TXIQ_AB_S0 0x0cd0 --#define BIT_MASK_TXIQ_A_S0 0x000007FE --#define BIT_MASK_TXIQ_A_EXT_S0 BIT(0) --#define BIT_MASK_TXIQ_B_S0 0x0007E000 --#define REG_TXIQ_CD_S0 0x0cd4 --#define BIT_MASK_TXIQ_C_S0 0x000007FE --#define BIT_MASK_TXIQ_C_EXT_S0 BIT(0) --#define BIT_MASK_TXIQ_D_S0 GENMASK(22, 13) --#define BIT_MASK_TXIQ_D_EXT_S0 BIT(12) --#define REG_RXIQ_AB_S0 0x0cd8 --#define BIT_MASK_RXIQ_X_S0 0x000003FF --#define BIT_MASK_RXIQ_Y_S0 0x003FF000 --#define REG_OFDM_FA_TYPE1_11N 0x0cf0 --#define BIT_MASK_OFDM_FF_CNT GENMASK(15, 0) --#define BIT_MASK_OFDM_SF_CNT GENMASK(31, 16) --#define REG_OFDM_FA_RSTD_11N 0x0d00 --#define BIT_MASK_OFDM_FA_RST1 BIT(27) --#define BIT_MASK_OFDM_FA_KEEP1 BIT(31) --#define REG_CTX 0x0d03 --#define BIT_MASK_CTX_TYPE GENMASK(6, 4) --#define REG_OFDM1_CFOTRK 0x0d2c --#define BIT_EN_CFOTRK BIT(28) --#define REG_OFDM1_CSI1 0x0d40 --#define REG_OFDM1_CSI2 0x0d44 --#define REG_OFDM1_CSI3 0x0d48 --#define REG_OFDM1_CSI4 0x0d4c --#define REG_OFDM_FA_TYPE2_11N 0x0da0 --#define BIT_MASK_OFDM_CCA_CNT GENMASK(15, 0) --#define BIT_MASK_OFDM_PF_CNT GENMASK(31, 16) --#define REG_OFDM_FA_TYPE3_11N 0x0da4 --#define BIT_MASK_OFDM_RI_CNT GENMASK(15, 0) --#define BIT_MASK_OFDM_CRC_CNT GENMASK(31, 16) --#define REG_OFDM_FA_TYPE4_11N 0x0da8 --#define BIT_MASK_OFDM_MNS_CNT GENMASK(15, 0) --#define REG_FPGA0_IQK_11N 0x0e28 --#define BIT_MASK_IQK_MOD 0xffffff00 --#define EN_IQK 0x808000 --#define RST_IQK 0x000000 --#define REG_TXIQK_TONE_A_11N 0x0e30 --#define REG_RXIQK_TONE_A_11N 0x0e34 --#define REG_TXIQK_PI_A_11N 0x0e38 --#define REG_RXIQK_PI_A_11N 0x0e3c --#define REG_TXIQK_11N 0x0e40 --#define BIT_SET_TXIQK_11N(x, y) (0x80007C00 | ((x) << 16) | (y)) --#define REG_RXIQK_11N 0x0e44 --#define REG_IQK_AGC_PTS_11N 0x0e48 --#define REG_IQK_AGC_RSP_11N 0x0e4c --#define REG_TX_IQK_TONE_B 0x0e50 --#define REG_RX_IQK_TONE_B 0x0e54 --#define REG_IQK_RES_TX 0x0e94 --#define BIT_MASK_RES_TX GENMASK(25, 16) --#define REG_IQK_RES_TY 0x0e9c --#define BIT_MASK_RES_TY GENMASK(25, 16) --#define REG_IQK_RES_RX 0x0ea4 --#define BIT_MASK_RES_RX GENMASK(25, 16) --#define REG_IQK_RES_RY 0x0eac --#define BIT_IQK_TX_FAIL BIT(28) --#define BIT_IQK_RX_FAIL BIT(27) --#define BIT_IQK_DONE BIT(26) --#define BIT_MASK_RES_RY GENMASK(25, 16) --#define REG_PAGE_F_RST_11N 0x0f14 --#define BIT_MASK_F_RST_ALL BIT(16) --#define REG_IGI_C_11N 0x0f84 --#define REG_IGI_D_11N 0x0f88 --#define REG_HT_CRC32_CNT_11N 0x0f90 --#define BIT_MASK_HT_CRC_OK GENMASK(15, 0) --#define BIT_MASK_HT_CRC_ERR GENMASK(31, 16) --#define REG_OFDM_CRC32_CNT_11N 0x0f94 --#define BIT_MASK_OFDM_LCRC_OK GENMASK(15, 0) --#define BIT_MASK_OFDM_LCRC_ERR GENMASK(31, 16) --#define REG_HT_CRC32_CNT_11N_AGG 0x0fb8 - - #endif -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8723x.c b/drivers/net/wireless/realtek/rtw88/rtw8723x.c -new file mode 100644 -index 00000000000000..c23650c5a20080 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtw88/rtw8723x.c -@@ -0,0 +1,562 @@ -+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause -+/* Copyright 2024 Fiona Klute -+ * -+ * Based on code originally in rtw8723d.[ch], -+ * Copyright(c) 2018-2019 Realtek Corporation -+ */ -+ -+#include "main.h" -+#include "debug.h" -+#include "phy.h" -+#include "reg.h" -+#include "tx.h" -+#include "rtw8723x.h" -+ -+static const struct rtw_hw_reg rtw8723x_txagc[] = { -+ [DESC_RATE1M] = { .addr = 0xe08, .mask = 0x0000ff00 }, -+ [DESC_RATE2M] = { .addr = 0x86c, .mask = 0x0000ff00 }, -+ [DESC_RATE5_5M] = { .addr = 0x86c, .mask = 0x00ff0000 }, -+ [DESC_RATE11M] = { .addr = 0x86c, .mask = 0xff000000 }, -+ [DESC_RATE6M] = { .addr = 0xe00, .mask = 0x000000ff }, -+ [DESC_RATE9M] = { .addr = 0xe00, .mask = 0x0000ff00 }, -+ [DESC_RATE12M] = { .addr = 0xe00, .mask = 0x00ff0000 }, -+ [DESC_RATE18M] = { .addr = 0xe00, .mask = 0xff000000 }, -+ [DESC_RATE24M] = { .addr = 0xe04, .mask = 0x000000ff }, -+ [DESC_RATE36M] = { .addr = 0xe04, .mask = 0x0000ff00 }, -+ [DESC_RATE48M] = { .addr = 0xe04, .mask = 0x00ff0000 }, -+ [DESC_RATE54M] = { .addr = 0xe04, .mask = 0xff000000 }, -+ [DESC_RATEMCS0] = { .addr = 0xe10, .mask = 0x000000ff }, -+ [DESC_RATEMCS1] = { .addr = 0xe10, .mask = 0x0000ff00 }, -+ [DESC_RATEMCS2] = { .addr = 0xe10, .mask = 0x00ff0000 }, -+ [DESC_RATEMCS3] = { .addr = 0xe10, .mask = 0xff000000 }, -+ [DESC_RATEMCS4] = { .addr = 0xe14, .mask = 0x000000ff }, -+ [DESC_RATEMCS5] = { .addr = 0xe14, .mask = 0x0000ff00 }, -+ [DESC_RATEMCS6] = { .addr = 0xe14, .mask = 0x00ff0000 }, -+ [DESC_RATEMCS7] = { .addr = 0xe14, .mask = 0xff000000 }, -+}; -+ -+static void __rtw8723x_lck(struct rtw_dev *rtwdev) -+{ -+ u32 lc_cal; -+ u8 val_ctx, rf_val; -+ int ret; -+ -+ val_ctx = rtw_read8(rtwdev, REG_CTX); -+ if ((val_ctx & BIT_MASK_CTX_TYPE) != 0) -+ rtw_write8(rtwdev, REG_CTX, val_ctx & ~BIT_MASK_CTX_TYPE); -+ else -+ rtw_write8(rtwdev, REG_TXPAUSE, 0xFF); -+ lc_cal = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); -+ -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal | BIT_LCK); -+ -+ ret = read_poll_timeout(rtw_read_rf, rf_val, rf_val != 0x1, -+ 10000, 1000000, false, -+ rtwdev, RF_PATH_A, RF_CFGCH, BIT_LCK); -+ if (ret) -+ rtw_warn(rtwdev, "failed to poll LCK status bit\n"); -+ -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal); -+ if ((val_ctx & BIT_MASK_CTX_TYPE) != 0) -+ rtw_write8(rtwdev, REG_CTX, val_ctx); -+ else -+ rtw_write8(rtwdev, REG_TXPAUSE, 0x00); -+} -+ -+static void rtw8723xe_efuse_parsing(struct rtw_efuse *efuse, -+ struct rtw8723x_efuse *map) -+{ -+ ether_addr_copy(efuse->addr, map->e.mac_addr); -+} -+ -+static void rtw8723xu_efuse_parsing(struct rtw_efuse *efuse, -+ struct rtw8723x_efuse *map) -+{ -+ ether_addr_copy(efuse->addr, map->u.mac_addr); -+} -+ -+static void rtw8723xs_efuse_parsing(struct rtw_efuse *efuse, -+ struct rtw8723x_efuse *map) -+{ -+ ether_addr_copy(efuse->addr, map->s.mac_addr); -+} -+ -+static int __rtw8723x_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) -+{ -+ struct rtw_efuse *efuse = &rtwdev->efuse; -+ struct rtw8723x_efuse *map; -+ int i; -+ -+ map = (struct rtw8723x_efuse *)log_map; -+ -+ efuse->rfe_option = 0; -+ efuse->rf_board_option = map->rf_board_option; -+ efuse->crystal_cap = map->xtal_k; -+ efuse->pa_type_2g = map->pa_type; -+ efuse->lna_type_2g = map->lna_type_2g[0]; -+ efuse->channel_plan = map->channel_plan; -+ efuse->country_code[0] = map->country_code[0]; -+ efuse->country_code[1] = map->country_code[1]; -+ efuse->bt_setting = map->rf_bt_setting; -+ efuse->regd = map->rf_board_option & 0x7; -+ efuse->thermal_meter[0] = map->thermal_meter; -+ efuse->thermal_meter_k = map->thermal_meter; -+ efuse->afe = map->afe; -+ -+ for (i = 0; i < 4; i++) -+ efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; -+ -+ switch (rtw_hci_type(rtwdev)) { -+ case RTW_HCI_TYPE_PCIE: -+ rtw8723xe_efuse_parsing(efuse, map); -+ break; -+ case RTW_HCI_TYPE_USB: -+ rtw8723xu_efuse_parsing(efuse, map); -+ break; -+ case RTW_HCI_TYPE_SDIO: -+ rtw8723xs_efuse_parsing(efuse, map); -+ break; -+ default: -+ /* unsupported now */ -+ return -EOPNOTSUPP; -+ } -+ -+ return 0; -+} -+ -+#define BIT_CFENDFORM BIT(9) -+#define BIT_WMAC_TCR_ERR0 BIT(12) -+#define BIT_WMAC_TCR_ERR1 BIT(13) -+#define BIT_TCR_CFG (BIT_CFENDFORM | BIT_WMAC_TCR_ERR0 | \ -+ BIT_WMAC_TCR_ERR1) -+#define WLAN_RX_FILTER0 0xFFFF -+#define WLAN_RX_FILTER1 0x400 -+#define WLAN_RX_FILTER2 0xFFFF -+#define WLAN_RCR_CFG 0x700060CE -+ -+static int __rtw8723x_mac_init(struct rtw_dev *rtwdev) -+{ -+ rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); -+ rtw_write32(rtwdev, REG_TCR, BIT_TCR_CFG); -+ -+ rtw_write16(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); -+ rtw_write16(rtwdev, REG_RXFLTMAP1, WLAN_RX_FILTER1); -+ rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); -+ rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); -+ -+ rtw_write32(rtwdev, REG_INT_MIG, 0); -+ rtw_write32(rtwdev, REG_MCUTST_1, 0x0); -+ -+ rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA); -+ rtw_write8(rtwdev, REG_2ND_CCA_CTRL, 0); -+ -+ return 0; -+} -+ -+static void __rtw8723x_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) -+{ -+ u8 ldo_pwr; -+ -+ ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); -+ if (enable) { -+ ldo_pwr &= ~BIT_MASK_LDO25_VOLTAGE; -+ ldo_pwr |= (BIT_LDO25_VOLTAGE_V25 << 4) | BIT_LDO25_EN; -+ } else { -+ ldo_pwr &= ~BIT_LDO25_EN; -+ } -+ rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); -+} -+ -+static void -+rtw8723x_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) -+{ -+ struct rtw_hal *hal = &rtwdev->hal; -+ const struct rtw_hw_reg *txagc; -+ u8 rate, pwr_index; -+ int j; -+ -+ for (j = 0; j < rtw_rate_size[rs]; j++) { -+ rate = rtw_rate_section[rs][j]; -+ pwr_index = hal->tx_pwr_tbl[path][rate]; -+ -+ if (rate >= ARRAY_SIZE(rtw8723x_txagc)) { -+ rtw_warn(rtwdev, "rate 0x%x isn't supported\n", rate); -+ continue; -+ } -+ txagc = &rtw8723x_txagc[rate]; -+ if (!txagc->addr) { -+ rtw_warn(rtwdev, "rate 0x%x isn't defined\n", rate); -+ continue; -+ } -+ -+ rtw_write32_mask(rtwdev, txagc->addr, txagc->mask, pwr_index); -+ } -+} -+ -+static void __rtw8723x_set_tx_power_index(struct rtw_dev *rtwdev) -+{ -+ struct rtw_hal *hal = &rtwdev->hal; -+ int rs, path; -+ -+ for (path = 0; path < hal->rf_path_num; path++) { -+ for (rs = 0; rs <= RTW_RATE_SECTION_HT_1S; rs++) -+ rtw8723x_set_tx_power_index_by_rate(rtwdev, path, rs); -+ } -+} -+ -+static void __rtw8723x_efuse_grant(struct rtw_dev *rtwdev, bool on) -+{ -+ if (on) { -+ rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); -+ -+ rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR); -+ rtw_write16_set(rtwdev, REG_SYS_CLKR, BIT_LOADER_CLK_EN | BIT_ANA8M); -+ } else { -+ rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); -+ } -+} -+ -+static void __rtw8723x_false_alarm_statistics(struct rtw_dev *rtwdev) -+{ -+ struct rtw_dm_info *dm_info = &rtwdev->dm_info; -+ u32 cck_fa_cnt; -+ u32 ofdm_fa_cnt; -+ u32 crc32_cnt; -+ u32 val32; -+ -+ /* hold counter */ -+ rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 1); -+ rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 1); -+ rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KEEP, 1); -+ rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KEEP, 1); -+ -+ cck_fa_cnt = rtw_read32_mask(rtwdev, REG_CCK_FA_LSB_11N, MASKBYTE0); -+ cck_fa_cnt += rtw_read32_mask(rtwdev, REG_CCK_FA_MSB_11N, MASKBYTE3) << 8; -+ -+ val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE1_11N); -+ ofdm_fa_cnt = u32_get_bits(val32, BIT_MASK_OFDM_FF_CNT); -+ ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_SF_CNT); -+ val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE2_11N); -+ dm_info->ofdm_cca_cnt = u32_get_bits(val32, BIT_MASK_OFDM_CCA_CNT); -+ ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_PF_CNT); -+ val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE3_11N); -+ ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_RI_CNT); -+ ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_CRC_CNT); -+ val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE4_11N); -+ ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_MNS_CNT); -+ -+ dm_info->cck_fa_cnt = cck_fa_cnt; -+ dm_info->ofdm_fa_cnt = ofdm_fa_cnt; -+ dm_info->total_fa_cnt = cck_fa_cnt + ofdm_fa_cnt; -+ -+ dm_info->cck_err_cnt = rtw_read32(rtwdev, REG_IGI_C_11N); -+ dm_info->cck_ok_cnt = rtw_read32(rtwdev, REG_IGI_D_11N); -+ crc32_cnt = rtw_read32(rtwdev, REG_OFDM_CRC32_CNT_11N); -+ dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_ERR); -+ dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_OK); -+ crc32_cnt = rtw_read32(rtwdev, REG_HT_CRC32_CNT_11N); -+ dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_ERR); -+ dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_OK); -+ dm_info->vht_err_cnt = 0; -+ dm_info->vht_ok_cnt = 0; -+ -+ val32 = rtw_read32(rtwdev, REG_CCK_CCA_CNT_11N); -+ dm_info->cck_cca_cnt = (u32_get_bits(val32, BIT_MASK_CCK_FA_MSB) << 8) | -+ u32_get_bits(val32, BIT_MASK_CCK_FA_LSB); -+ dm_info->total_cca_cnt = dm_info->cck_cca_cnt + dm_info->ofdm_cca_cnt; -+ -+ /* reset counter */ -+ rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 1); -+ rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0); -+ rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 1); -+ rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0); -+ rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0); -+ rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 0); -+ rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 0); -+ rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 2); -+ rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 0); -+ rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 2); -+ rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 1); -+ rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 0); -+} -+ -+/* IQK (IQ calibration) */ -+ -+static -+void __rtw8723x_iqk_backup_regs(struct rtw_dev *rtwdev, -+ struct rtw8723x_iqk_backup_regs *backup) -+{ -+ int i; -+ -+ for (i = 0; i < RTW8723X_IQK_ADDA_REG_NUM; i++) -+ backup->adda[i] = rtw_read32(rtwdev, -+ rtw8723x_common.iqk_adda_regs[i]); -+ -+ for (i = 0; i < RTW8723X_IQK_MAC8_REG_NUM; i++) -+ backup->mac8[i] = rtw_read8(rtwdev, -+ rtw8723x_common.iqk_mac8_regs[i]); -+ for (i = 0; i < RTW8723X_IQK_MAC32_REG_NUM; i++) -+ backup->mac32[i] = rtw_read32(rtwdev, -+ rtw8723x_common.iqk_mac32_regs[i]); -+ -+ for (i = 0; i < RTW8723X_IQK_BB_REG_NUM; i++) -+ backup->bb[i] = rtw_read32(rtwdev, -+ rtw8723x_common.iqk_bb_regs[i]); -+ -+ backup->igia = rtw_read32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0); -+ backup->igib = rtw_read32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0); -+ -+ backup->bb_sel_btg = rtw_read32(rtwdev, REG_BB_SEL_BTG); -+} -+ -+static -+void __rtw8723x_iqk_restore_regs(struct rtw_dev *rtwdev, -+ const struct rtw8723x_iqk_backup_regs *backup) -+{ -+ int i; -+ -+ for (i = 0; i < RTW8723X_IQK_ADDA_REG_NUM; i++) -+ rtw_write32(rtwdev, rtw8723x_common.iqk_adda_regs[i], -+ backup->adda[i]); -+ -+ for (i = 0; i < RTW8723X_IQK_MAC8_REG_NUM; i++) -+ rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[i], -+ backup->mac8[i]); -+ for (i = 0; i < RTW8723X_IQK_MAC32_REG_NUM; i++) -+ rtw_write32(rtwdev, rtw8723x_common.iqk_mac32_regs[i], -+ backup->mac32[i]); -+ -+ for (i = 0; i < RTW8723X_IQK_BB_REG_NUM; i++) -+ rtw_write32(rtwdev, rtw8723x_common.iqk_bb_regs[i], -+ backup->bb[i]); -+ -+ rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); -+ rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, backup->igia); -+ -+ rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, 0x50); -+ rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, backup->igib); -+ -+ rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x01008c00); -+ rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x01008c00); -+} -+ -+static -+bool __rtw8723x_iqk_similarity_cmp(struct rtw_dev *rtwdev, -+ s32 result[][IQK_NR], -+ u8 c1, u8 c2) -+{ -+ u32 i, j, diff; -+ u32 bitmap = 0; -+ u8 candidate[PATH_NR] = {IQK_ROUND_INVALID, IQK_ROUND_INVALID}; -+ bool ret = true; -+ -+ s32 tmp1, tmp2; -+ -+ for (i = 0; i < IQK_NR; i++) { -+ tmp1 = iqkxy_to_s32(result[c1][i]); -+ tmp2 = iqkxy_to_s32(result[c2][i]); -+ -+ diff = abs(tmp1 - tmp2); -+ -+ if (diff <= MAX_TOLERANCE) -+ continue; -+ -+ if ((i == IQK_S1_RX_X || i == IQK_S0_RX_X) && !bitmap) { -+ if (result[c1][i] + result[c1][i + 1] == 0) -+ candidate[i / IQK_SX_NR] = c2; -+ else if (result[c2][i] + result[c2][i + 1] == 0) -+ candidate[i / IQK_SX_NR] = c1; -+ else -+ bitmap |= BIT(i); -+ } else { -+ bitmap |= BIT(i); -+ } -+ } -+ -+ if (bitmap != 0) -+ goto check_sim; -+ -+ for (i = 0; i < PATH_NR; i++) { -+ if (candidate[i] == IQK_ROUND_INVALID) -+ continue; -+ -+ for (j = i * IQK_SX_NR; j < i * IQK_SX_NR + 2; j++) -+ result[IQK_ROUND_HYBRID][j] = result[candidate[i]][j]; -+ ret = false; -+ } -+ -+ return ret; -+ -+check_sim: -+ for (i = 0; i < IQK_NR; i++) { -+ j = i & ~1; /* 2 bits are a pair for IQ[X, Y] */ -+ if (bitmap & GENMASK(j + 1, j)) -+ continue; -+ -+ result[IQK_ROUND_HYBRID][i] = result[c1][i]; -+ } -+ -+ return false; -+} -+ -+static u8 __rtw8723x_pwrtrack_get_limit_ofdm(struct rtw_dev *rtwdev) -+{ -+ struct rtw_dm_info *dm_info = &rtwdev->dm_info; -+ u8 tx_rate = dm_info->tx_rate; -+ u8 limit_ofdm = 30; -+ -+ switch (tx_rate) { -+ case DESC_RATE1M...DESC_RATE5_5M: -+ case DESC_RATE11M: -+ break; -+ case DESC_RATE6M...DESC_RATE48M: -+ limit_ofdm = 36; -+ break; -+ case DESC_RATE54M: -+ limit_ofdm = 34; -+ break; -+ case DESC_RATEMCS0...DESC_RATEMCS2: -+ limit_ofdm = 38; -+ break; -+ case DESC_RATEMCS3...DESC_RATEMCS4: -+ limit_ofdm = 36; -+ break; -+ case DESC_RATEMCS5...DESC_RATEMCS7: -+ limit_ofdm = 34; -+ break; -+ default: -+ rtw_warn(rtwdev, "pwrtrack unhandled tx_rate 0x%x\n", tx_rate); -+ break; -+ } -+ -+ return limit_ofdm; -+} -+ -+static -+void __rtw8723x_pwrtrack_set_xtal(struct rtw_dev *rtwdev, u8 therm_path, -+ u8 delta) -+{ -+ struct rtw_dm_info *dm_info = &rtwdev->dm_info; -+ const struct rtw_pwr_track_tbl *tbl = rtwdev->chip->pwr_track_tbl; -+ const s8 *pwrtrk_xtal; -+ s8 xtal_cap; -+ -+ if (dm_info->thermal_avg[therm_path] > -+ rtwdev->efuse.thermal_meter[therm_path]) -+ pwrtrk_xtal = tbl->pwrtrk_xtal_p; -+ else -+ pwrtrk_xtal = tbl->pwrtrk_xtal_n; -+ -+ xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; -+ xtal_cap = clamp_t(s8, xtal_cap + pwrtrk_xtal[delta], 0, 0x3F); -+ rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, -+ xtal_cap | (xtal_cap << 6)); -+} -+ -+static -+void __rtw8723x_fill_txdesc_checksum(struct rtw_dev *rtwdev, -+ struct rtw_tx_pkt_info *pkt_info, -+ u8 *txdesc) -+{ -+ size_t words = 32 / 2; /* calculate the first 32 bytes (16 words) */ -+ __le16 chksum = 0; -+ __le16 *data = (__le16 *)(txdesc); -+ struct rtw_tx_desc *tx_desc = (struct rtw_tx_desc *)txdesc; -+ -+ le32p_replace_bits(&tx_desc->w7, 0, RTW_TX_DESC_W7_TXDESC_CHECKSUM); -+ -+ while (words--) -+ chksum ^= *data++; -+ -+ chksum = ~chksum; -+ -+ le32p_replace_bits(&tx_desc->w7, __le16_to_cpu(chksum), -+ RTW_TX_DESC_W7_TXDESC_CHECKSUM); -+} -+ -+static void __rtw8723x_coex_cfg_init(struct rtw_dev *rtwdev) -+{ -+ /* enable TBTT nterrupt */ -+ rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); -+ -+ /* BT report packet sample rate */ -+ /* 0x790[5:0]=0x5 */ -+ rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); -+ -+ /* enable BT counter statistics */ -+ rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); -+ -+ /* enable PTA (3-wire function form BT side) */ -+ rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); -+ rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); -+ -+ /* enable PTA (tx/rx signal form WiFi side) */ -+ rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); -+} -+ -+const struct rtw8723x_common rtw8723x_common = { -+ .iqk_adda_regs = { -+ 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, -+ 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec -+ }, -+ .iqk_mac8_regs = {0x522, 0x550, 0x551}, -+ .iqk_mac32_regs = {0x40}, -+ .iqk_bb_regs = { -+ 0xc04, 0xc08, 0x874, 0xb68, 0xb6c, 0x870, 0x860, 0x864, 0xa04 -+ }, -+ -+ .ltecoex_addr = { -+ .ctrl = REG_LTECOEX_CTRL, -+ .wdata = REG_LTECOEX_WRITE_DATA, -+ .rdata = REG_LTECOEX_READ_DATA, -+ }, -+ .rf_sipi_addr = { -+ [RF_PATH_A] = { .hssi_1 = 0x820, .lssi_read = 0x8a0, -+ .hssi_2 = 0x824, .lssi_read_pi = 0x8b8}, -+ [RF_PATH_B] = { .hssi_1 = 0x828, .lssi_read = 0x8a4, -+ .hssi_2 = 0x82c, .lssi_read_pi = 0x8bc}, -+ }, -+ .dig = { -+ [0] = { .addr = 0xc50, .mask = 0x7f }, -+ [1] = { .addr = 0xc50, .mask = 0x7f }, -+ }, -+ .dig_cck = { -+ [0] = { .addr = 0xa0c, .mask = 0x3f00 }, -+ }, -+ .prioq_addrs = { -+ .prio[RTW_DMA_MAPPING_EXTRA] = { -+ .rsvd = REG_RQPN_NPQ + 2, .avail = REG_RQPN_NPQ + 3, -+ }, -+ .prio[RTW_DMA_MAPPING_LOW] = { -+ .rsvd = REG_RQPN + 1, .avail = REG_FIFOPAGE_CTRL_2 + 1, -+ }, -+ .prio[RTW_DMA_MAPPING_NORMAL] = { -+ .rsvd = REG_RQPN_NPQ, .avail = REG_RQPN_NPQ + 1, -+ }, -+ .prio[RTW_DMA_MAPPING_HIGH] = { -+ .rsvd = REG_RQPN, .avail = REG_FIFOPAGE_CTRL_2, -+ }, -+ .wsize = false, -+ }, -+ -+ .lck = __rtw8723x_lck, -+ .read_efuse = __rtw8723x_read_efuse, -+ .mac_init = __rtw8723x_mac_init, -+ .cfg_ldo25 = __rtw8723x_cfg_ldo25, -+ .set_tx_power_index = __rtw8723x_set_tx_power_index, -+ .efuse_grant = __rtw8723x_efuse_grant, -+ .false_alarm_statistics = __rtw8723x_false_alarm_statistics, -+ .iqk_backup_regs = __rtw8723x_iqk_backup_regs, -+ .iqk_restore_regs = __rtw8723x_iqk_restore_regs, -+ .iqk_similarity_cmp = __rtw8723x_iqk_similarity_cmp, -+ .pwrtrack_get_limit_ofdm = __rtw8723x_pwrtrack_get_limit_ofdm, -+ .pwrtrack_set_xtal = __rtw8723x_pwrtrack_set_xtal, -+ .coex_cfg_init = __rtw8723x_coex_cfg_init, -+ .fill_txdesc_checksum = __rtw8723x_fill_txdesc_checksum, -+}; -+EXPORT_SYMBOL(rtw8723x_common); -+ -+MODULE_AUTHOR("Realtek Corporation"); -+MODULE_AUTHOR("Fiona Klute "); -+MODULE_DESCRIPTION("Common functions for Realtek 802.11n wireless 8723x drivers"); -+MODULE_LICENSE("Dual BSD/GPL"); -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8723x.h b/drivers/net/wireless/realtek/rtw88/rtw8723x.h -new file mode 100644 -index 00000000000000..cace285fc03397 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtw88/rtw8723x.h -@@ -0,0 +1,496 @@ -+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -+/* Copyright 2024 Fiona Klute -+ * -+ * Based on code originally in rtw8723d.[ch], -+ * Copyright(c) 2018-2019 Realtek Corporation -+ */ -+ -+#ifndef __RTW8723X_H__ -+#define __RTW8723X_H__ -+ -+#include "main.h" -+#include "debug.h" -+#include "phy.h" -+#include "reg.h" -+ -+enum rtw8723x_path { -+ PATH_S1, -+ PATH_S0, -+ PATH_NR, -+}; -+ -+enum rtw8723x_iqk_round { -+ IQK_ROUND_0, -+ IQK_ROUND_1, -+ IQK_ROUND_2, -+ IQK_ROUND_HYBRID, -+ IQK_ROUND_SIZE, -+ IQK_ROUND_INVALID = 0xff, -+}; -+ -+enum rtw8723x_iqk_result { -+ IQK_S1_TX_X, -+ IQK_S1_TX_Y, -+ IQK_S1_RX_X, -+ IQK_S1_RX_Y, -+ IQK_S0_TX_X, -+ IQK_S0_TX_Y, -+ IQK_S0_RX_X, -+ IQK_S0_RX_Y, -+ IQK_NR, -+ IQK_SX_NR = IQK_NR / PATH_NR, -+}; -+ -+struct rtw8723xe_efuse { -+ u8 mac_addr[ETH_ALEN]; /* 0xd0 */ -+ u8 vendor_id[2]; -+ u8 device_id[2]; -+ u8 sub_vendor_id[2]; -+ u8 sub_device_id[2]; -+}; -+ -+struct rtw8723xu_efuse { -+ u8 res4[48]; /* 0xd0 */ -+ u8 vendor_id[2]; /* 0x100 */ -+ u8 product_id[2]; /* 0x102 */ -+ u8 usb_option; /* 0x104 */ -+ u8 res5[2]; /* 0x105 */ -+ u8 mac_addr[ETH_ALEN]; /* 0x107 */ -+}; -+ -+struct rtw8723xs_efuse { -+ u8 res4[0x4a]; /* 0xd0 */ -+ u8 mac_addr[ETH_ALEN]; /* 0x11a */ -+}; -+ -+struct rtw8723x_efuse { -+ __le16 rtl_id; -+ u8 rsvd[2]; -+ u8 afe; -+ u8 rsvd1[11]; -+ -+ /* power index for four RF paths */ -+ struct rtw_txpwr_idx txpwr_idx_table[4]; -+ -+ u8 channel_plan; /* 0xb8 */ -+ u8 xtal_k; -+ u8 thermal_meter; -+ u8 iqk_lck; -+ u8 pa_type; /* 0xbc */ -+ u8 lna_type_2g[2]; /* 0xbd */ -+ u8 lna_type_5g[2]; -+ u8 rf_board_option; -+ u8 rf_feature_option; -+ u8 rf_bt_setting; -+ u8 eeprom_version; -+ u8 eeprom_customer_id; -+ u8 tx_bb_swing_setting_2g; -+ u8 res_c7; -+ u8 tx_pwr_calibrate_rate; -+ u8 rf_antenna_option; /* 0xc9 */ -+ u8 rfe_option; -+ u8 country_code[2]; -+ u8 res[3]; -+ union { -+ struct rtw8723xe_efuse e; -+ struct rtw8723xu_efuse u; -+ struct rtw8723xs_efuse s; -+ }; -+}; -+ -+#define RTW8723X_IQK_ADDA_REG_NUM 16 -+#define RTW8723X_IQK_MAC8_REG_NUM 3 -+#define RTW8723X_IQK_MAC32_REG_NUM 1 -+#define RTW8723X_IQK_BB_REG_NUM 9 -+ -+struct rtw8723x_iqk_backup_regs { -+ u32 adda[RTW8723X_IQK_ADDA_REG_NUM]; -+ u8 mac8[RTW8723X_IQK_MAC8_REG_NUM]; -+ u32 mac32[RTW8723X_IQK_MAC32_REG_NUM]; -+ u32 bb[RTW8723X_IQK_BB_REG_NUM]; -+ -+ u32 lte_path; -+ u32 lte_gnt; -+ -+ u32 bb_sel_btg; -+ u8 btg_sel; -+ -+ u8 igia; -+ u8 igib; -+}; -+ -+struct rtw8723x_common { -+ /* registers that must be backed up before IQK and restored after */ -+ u32 iqk_adda_regs[RTW8723X_IQK_ADDA_REG_NUM]; -+ u32 iqk_mac8_regs[RTW8723X_IQK_MAC8_REG_NUM]; -+ u32 iqk_mac32_regs[RTW8723X_IQK_MAC32_REG_NUM]; -+ u32 iqk_bb_regs[RTW8723X_IQK_BB_REG_NUM]; -+ -+ /* chip register definitions */ -+ struct rtw_ltecoex_addr ltecoex_addr; -+ struct rtw_rf_sipi_addr rf_sipi_addr[2]; -+ struct rtw_hw_reg dig[2]; -+ struct rtw_hw_reg dig_cck[1]; -+ struct rtw_prioq_addrs prioq_addrs; -+ -+ /* common functions */ -+ void (*lck)(struct rtw_dev *rtwdev); -+ int (*read_efuse)(struct rtw_dev *rtwdev, u8 *log_map); -+ int (*mac_init)(struct rtw_dev *rtwdev); -+ void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); -+ void (*set_tx_power_index)(struct rtw_dev *rtwdev); -+ void (*efuse_grant)(struct rtw_dev *rtwdev, bool on); -+ void (*false_alarm_statistics)(struct rtw_dev *rtwdev); -+ void (*iqk_backup_regs)(struct rtw_dev *rtwdev, -+ struct rtw8723x_iqk_backup_regs *backup); -+ void (*iqk_restore_regs)(struct rtw_dev *rtwdev, -+ const struct rtw8723x_iqk_backup_regs *backup); -+ bool (*iqk_similarity_cmp)(struct rtw_dev *rtwdev, s32 result[][IQK_NR], -+ u8 c1, u8 c2); -+ u8 (*pwrtrack_get_limit_ofdm)(struct rtw_dev *rtwdev); -+ void (*pwrtrack_set_xtal)(struct rtw_dev *rtwdev, u8 therm_path, -+ u8 delta); -+ void (*coex_cfg_init)(struct rtw_dev *rtwdev); -+ void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev, -+ struct rtw_tx_pkt_info *pkt_info, -+ u8 *txdesc); -+}; -+ -+extern const struct rtw8723x_common rtw8723x_common; -+ -+#define PATH_IQK_RETRY 2 -+#define MAX_TOLERANCE 5 -+#define IQK_TX_X_ERR 0x142 -+#define IQK_TX_Y_ERR 0x42 -+#define IQK_RX_X_UPPER 0x11a -+#define IQK_RX_X_LOWER 0xe6 -+#define IQK_RX_Y_LMT 0x1a -+#define IQK_TX_OK BIT(0) -+#define IQK_RX_OK BIT(1) -+ -+#define WLAN_TXQ_RPT_EN 0x1F -+ -+#define SPUR_THRES 0x16 -+#define DIS_3WIRE 0xccf000c0 -+#define EN_3WIRE 0xccc000c0 -+#define START_PSD 0x400000 -+#define FREQ_CH13 0xfccd -+#define FREQ_CH14 0xff9a -+#define RFCFGCH_CHANNEL_MASK GENMASK(7, 0) -+#define RFCFGCH_BW_MASK (BIT(11) | BIT(10)) -+#define RFCFGCH_BW_20M (BIT(11) | BIT(10)) -+#define RFCFGCH_BW_40M BIT(10) -+#define BIT_MASK_RFMOD BIT(0) -+#define BIT_LCK BIT(15) -+ -+#define REG_GPIO_INTM 0x0048 -+#define REG_BTG_SEL 0x0067 -+#define BIT_MASK_BTG_WL BIT(7) -+#define REG_LTECOEX_PATH_CONTROL 0x0070 -+#define REG_LTECOEX_CTRL 0x07c0 -+#define REG_LTECOEX_WRITE_DATA 0x07c4 -+#define REG_LTECOEX_READ_DATA 0x07c8 -+#define REG_PSDFN 0x0808 -+#define REG_BB_PWR_SAV1_11N 0x0874 -+#define REG_ANA_PARAM1 0x0880 -+#define REG_ANALOG_P4 0x088c -+#define REG_PSDRPT 0x08b4 -+#define REG_FPGA1_RFMOD 0x0900 -+#define REG_BB_SEL_BTG 0x0948 -+#define REG_BBRX_DFIR 0x0954 -+#define BIT_MASK_RXBB_DFIR GENMASK(27, 24) -+#define BIT_RXBB_DFIR_EN BIT(19) -+#define REG_CCK0_SYS 0x0a00 -+#define BIT_CCK_SIDE_BAND BIT(4) -+#define REG_CCK_ANT_SEL_11N 0x0a04 -+#define REG_PWRTH 0x0a08 -+#define REG_CCK_FA_RST_11N 0x0a2c -+#define BIT_MASK_CCK_CNT_KEEP BIT(12) -+#define BIT_MASK_CCK_CNT_EN BIT(13) -+#define BIT_MASK_CCK_CNT_KPEN (BIT_MASK_CCK_CNT_KEEP | BIT_MASK_CCK_CNT_EN) -+#define BIT_MASK_CCK_FA_KEEP BIT(14) -+#define BIT_MASK_CCK_FA_EN BIT(15) -+#define BIT_MASK_CCK_FA_KPEN (BIT_MASK_CCK_FA_KEEP | BIT_MASK_CCK_FA_EN) -+#define REG_CCK_FA_LSB_11N 0x0a5c -+#define REG_CCK_FA_MSB_11N 0x0a58 -+#define REG_CCK_CCA_CNT_11N 0x0a60 -+#define BIT_MASK_CCK_FA_MSB GENMASK(7, 0) -+#define BIT_MASK_CCK_FA_LSB GENMASK(15, 8) -+#define REG_PWRTH2 0x0aa8 -+#define REG_CSRATIO 0x0aaa -+#define REG_OFDM_FA_HOLDC_11N 0x0c00 -+#define BIT_MASK_OFDM_FA_KEEP BIT(31) -+#define REG_BB_RX_PATH_11N 0x0c04 -+#define REG_TRMUX_11N 0x0c08 -+#define REG_OFDM_FA_RSTC_11N 0x0c0c -+#define BIT_MASK_OFDM_FA_RST BIT(31) -+#define REG_A_RXIQI 0x0c14 -+#define BIT_MASK_RXIQ_S1_X 0x000003FF -+#define BIT_MASK_RXIQ_S1_Y1 0x0000FC00 -+#define BIT_SET_RXIQ_S1_Y1(y) ((y) & 0x3F) -+#define REG_OFDM0_RXDSP 0x0c40 -+#define BIT_MASK_RXDSP GENMASK(28, 24) -+#define BIT_EN_RXDSP BIT(9) -+#define REG_OFDM_0_ECCA_THRESHOLD 0x0c4c -+#define BIT_MASK_OFDM0_EXT_A BIT(31) -+#define BIT_MASK_OFDM0_EXT_C BIT(29) -+#define BIT_MASK_OFDM0_EXTS (BIT(31) | BIT(29) | BIT(28)) -+#define BIT_SET_OFDM0_EXTS(a, c, d) (((a) << 31) | ((c) << 29) | ((d) << 28)) -+#define REG_OFDM0_XAAGC1 0x0c50 -+#define REG_OFDM0_XBAGC1 0x0c58 -+#define REG_AGCRSSI 0x0c78 -+#define REG_OFDM_0_XA_TX_IQ_IMBALANCE 0x0c80 -+#define BIT_MASK_TXIQ_ELM_A 0x03ff -+#define BIT_SET_TXIQ_ELM_ACD(a, c, d) (((d) << 22) | (((c) & 0x3F) << 16) | \ -+ ((a) & 0x03ff)) -+#define BIT_MASK_TXIQ_ELM_C GENMASK(21, 16) -+#define BIT_SET_TXIQ_ELM_C2(c) ((c) & 0x3F) -+#define BIT_MASK_TXIQ_ELM_D GENMASK(31, 22) -+#define REG_TXIQK_MATRIXA_LSB2_11N 0x0c94 -+#define BIT_SET_TXIQ_ELM_C1(c) (((c) & 0x000003C0) >> 6) -+#define REG_RXIQK_MATRIX_LSB_11N 0x0ca0 -+#define BIT_MASK_RXIQ_S1_Y2 0xF0000000 -+#define BIT_SET_RXIQ_S1_Y2(y) (((y) >> 6) & 0xF) -+#define REG_TXIQ_AB_S0 0x0cd0 -+#define BIT_MASK_TXIQ_A_S0 0x000007FE -+#define BIT_MASK_TXIQ_A_EXT_S0 BIT(0) -+#define BIT_MASK_TXIQ_B_S0 0x0007E000 -+#define REG_TXIQ_CD_S0 0x0cd4 -+#define BIT_MASK_TXIQ_C_S0 0x000007FE -+#define BIT_MASK_TXIQ_C_EXT_S0 BIT(0) -+#define BIT_MASK_TXIQ_D_S0 GENMASK(22, 13) -+#define BIT_MASK_TXIQ_D_EXT_S0 BIT(12) -+#define REG_RXIQ_AB_S0 0x0cd8 -+#define BIT_MASK_RXIQ_X_S0 0x000003FF -+#define BIT_MASK_RXIQ_Y_S0 0x003FF000 -+#define REG_OFDM_FA_TYPE1_11N 0x0cf0 -+#define BIT_MASK_OFDM_FF_CNT GENMASK(15, 0) -+#define BIT_MASK_OFDM_SF_CNT GENMASK(31, 16) -+#define REG_OFDM_FA_RSTD_11N 0x0d00 -+#define BIT_MASK_OFDM_FA_RST1 BIT(27) -+#define BIT_MASK_OFDM_FA_KEEP1 BIT(31) -+#define REG_CTX 0x0d03 -+#define BIT_MASK_CTX_TYPE GENMASK(6, 4) -+#define REG_OFDM1_CFOTRK 0x0d2c -+#define BIT_EN_CFOTRK BIT(28) -+#define REG_OFDM1_CSI1 0x0d40 -+#define REG_OFDM1_CSI2 0x0d44 -+#define REG_OFDM1_CSI3 0x0d48 -+#define REG_OFDM1_CSI4 0x0d4c -+#define REG_OFDM_FA_TYPE2_11N 0x0da0 -+#define BIT_MASK_OFDM_CCA_CNT GENMASK(15, 0) -+#define BIT_MASK_OFDM_PF_CNT GENMASK(31, 16) -+#define REG_OFDM_FA_TYPE3_11N 0x0da4 -+#define BIT_MASK_OFDM_RI_CNT GENMASK(15, 0) -+#define BIT_MASK_OFDM_CRC_CNT GENMASK(31, 16) -+#define REG_OFDM_FA_TYPE4_11N 0x0da8 -+#define BIT_MASK_OFDM_MNS_CNT GENMASK(15, 0) -+#define REG_FPGA0_IQK_11N 0x0e28 -+#define BIT_MASK_IQK_MOD 0xffffff00 -+#define EN_IQK 0x808000 -+#define RST_IQK 0x000000 -+#define REG_TXIQK_TONE_A_11N 0x0e30 -+#define REG_RXIQK_TONE_A_11N 0x0e34 -+#define REG_TXIQK_PI_A_11N 0x0e38 -+#define REG_RXIQK_PI_A_11N 0x0e3c -+#define REG_TXIQK_11N 0x0e40 -+#define BIT_SET_TXIQK_11N(x, y) (0x80007C00 | ((x) << 16) | (y)) -+#define REG_RXIQK_11N 0x0e44 -+#define REG_IQK_AGC_PTS_11N 0x0e48 -+#define REG_IQK_AGC_RSP_11N 0x0e4c -+#define REG_TX_IQK_TONE_B 0x0e50 -+#define REG_RX_IQK_TONE_B 0x0e54 -+#define REG_IQK_RES_TX 0x0e94 -+#define BIT_MASK_RES_TX GENMASK(25, 16) -+#define REG_IQK_RES_TY 0x0e9c -+#define BIT_MASK_RES_TY GENMASK(25, 16) -+#define REG_IQK_RES_RX 0x0ea4 -+#define BIT_MASK_RES_RX GENMASK(25, 16) -+#define REG_IQK_RES_RY 0x0eac -+#define BIT_IQK_TX_FAIL BIT(28) -+#define BIT_IQK_RX_FAIL BIT(27) -+#define BIT_IQK_DONE BIT(26) -+#define BIT_MASK_RES_RY GENMASK(25, 16) -+#define REG_PAGE_F_RST_11N 0x0f14 -+#define BIT_MASK_F_RST_ALL BIT(16) -+#define REG_IGI_C_11N 0x0f84 -+#define REG_IGI_D_11N 0x0f88 -+#define REG_HT_CRC32_CNT_11N 0x0f90 -+#define BIT_MASK_HT_CRC_OK GENMASK(15, 0) -+#define BIT_MASK_HT_CRC_ERR GENMASK(31, 16) -+#define REG_OFDM_CRC32_CNT_11N 0x0f94 -+#define BIT_MASK_OFDM_LCRC_OK GENMASK(15, 0) -+#define BIT_MASK_OFDM_LCRC_ERR GENMASK(31, 16) -+#define REG_HT_CRC32_CNT_11N_AGG 0x0fb8 -+ -+#define OFDM_SWING_A(swing) FIELD_GET(GENMASK(9, 0), swing) -+#define OFDM_SWING_B(swing) FIELD_GET(GENMASK(15, 10), swing) -+#define OFDM_SWING_C(swing) FIELD_GET(GENMASK(21, 16), swing) -+#define OFDM_SWING_D(swing) FIELD_GET(GENMASK(31, 22), swing) -+ -+static inline s32 iqkxy_to_s32(s32 val) -+{ -+ /* val is Q10.8 */ -+ return sign_extend32(val, 9); -+} -+ -+static inline s32 iqk_mult(s32 x, s32 y, s32 *ext) -+{ -+ /* x, y and return value are Q10.8 */ -+ s32 t; -+ -+ t = x * y; -+ if (ext) -+ *ext = (t >> 7) & 0x1; /* Q.16 --> Q.9; get LSB of Q.9 */ -+ -+ return (t >> 8); /* Q.16 --> Q.8 */ -+} -+ -+static inline void rtw8723x_lck(struct rtw_dev *rtwdev) -+{ -+ rtw8723x_common.lck(rtwdev); -+} -+ -+static inline int rtw8723x_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) -+{ -+ return rtw8723x_common.read_efuse(rtwdev, log_map); -+} -+ -+static inline int rtw8723x_mac_init(struct rtw_dev *rtwdev) -+{ -+ return rtw8723x_common.mac_init(rtwdev); -+} -+ -+static inline void rtw8723x_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) -+{ -+ rtw8723x_common.cfg_ldo25(rtwdev, enable); -+} -+ -+static inline void rtw8723x_set_tx_power_index(struct rtw_dev *rtwdev) -+{ -+ rtw8723x_common.set_tx_power_index(rtwdev); -+} -+ -+static inline void rtw8723x_efuse_grant(struct rtw_dev *rtwdev, bool on) -+{ -+ rtw8723x_common.efuse_grant(rtwdev, on); -+} -+ -+static inline void rtw8723x_false_alarm_statistics(struct rtw_dev *rtwdev) -+{ -+ rtw8723x_common.false_alarm_statistics(rtwdev); -+} -+ -+static inline -+void rtw8723x_iqk_backup_regs(struct rtw_dev *rtwdev, -+ struct rtw8723x_iqk_backup_regs *backup) -+{ -+ rtw8723x_common.iqk_backup_regs(rtwdev, backup); -+} -+ -+static inline -+void rtw8723x_iqk_restore_regs(struct rtw_dev *rtwdev, -+ const struct rtw8723x_iqk_backup_regs *backup) -+{ -+ rtw8723x_common.iqk_restore_regs(rtwdev, backup); -+} -+ -+static inline -+bool rtw8723x_iqk_similarity_cmp(struct rtw_dev *rtwdev, s32 result[][IQK_NR], -+ u8 c1, u8 c2) -+{ -+ return rtw8723x_common.iqk_similarity_cmp(rtwdev, result, c1, c2); -+} -+ -+static inline u8 rtw8723x_pwrtrack_get_limit_ofdm(struct rtw_dev *rtwdev) -+{ -+ return rtw8723x_common.pwrtrack_get_limit_ofdm(rtwdev); -+} -+ -+static inline -+void rtw8723x_pwrtrack_set_xtal(struct rtw_dev *rtwdev, u8 therm_path, -+ u8 delta) -+{ -+ rtw8723x_common.pwrtrack_set_xtal(rtwdev, therm_path, delta); -+} -+ -+static inline void rtw8723x_coex_cfg_init(struct rtw_dev *rtwdev) -+{ -+ rtw8723x_common.coex_cfg_init(rtwdev); -+} -+ -+static inline -+void rtw8723x_fill_txdesc_checksum(struct rtw_dev *rtwdev, -+ struct rtw_tx_pkt_info *pkt_info, -+ u8 *txdesc) -+{ -+ rtw8723x_common.fill_txdesc_checksum(rtwdev, pkt_info, txdesc); -+} -+ -+/* IQK helper functions, defined as inline so they can be shared -+ * without needing an EXPORT_SYMBOL each. -+ */ -+static inline void -+rtw8723x_iqk_backup_path_ctrl(struct rtw_dev *rtwdev, -+ struct rtw8723x_iqk_backup_regs *backup) -+{ -+ backup->btg_sel = rtw_read8(rtwdev, REG_BTG_SEL); -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] original 0x67 = 0x%x\n", -+ backup->btg_sel); -+} -+ -+static inline void rtw8723x_iqk_config_path_ctrl(struct rtw_dev *rtwdev) -+{ -+ rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1); -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] set 0x67 = 0x%x\n", -+ rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); -+} -+ -+static inline void -+rtw8723x_iqk_restore_path_ctrl(struct rtw_dev *rtwdev, -+ const struct rtw8723x_iqk_backup_regs *backup) -+{ -+ rtw_write8(rtwdev, REG_BTG_SEL, backup->btg_sel); -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] restore 0x67 = 0x%x\n", -+ rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); -+} -+ -+static inline void -+rtw8723x_iqk_backup_lte_path_gnt(struct rtw_dev *rtwdev, -+ struct rtw8723x_iqk_backup_regs *backup) -+{ -+ backup->lte_path = rtw_read32(rtwdev, REG_LTECOEX_PATH_CONTROL); -+ rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0038); -+ mdelay(1); -+ backup->lte_gnt = rtw_read32(rtwdev, REG_LTECOEX_READ_DATA); -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] OriginalGNT = 0x%x\n", -+ backup->lte_gnt); -+} -+ -+static inline void -+rtw8723x_iqk_config_lte_path_gnt(struct rtw_dev *rtwdev, -+ u32 write_data) -+{ -+ rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, write_data); -+ rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc0020038); -+ rtw_write32_mask(rtwdev, REG_LTECOEX_PATH_CONTROL, -+ BIT_LTE_MUX_CTRL_PATH, 0x1); -+} -+ -+static inline void -+rtw8723x_iqk_restore_lte_path_gnt(struct rtw_dev *rtwdev, -+ const struct rtw8723x_iqk_backup_regs *bak) -+{ -+ rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, bak->lte_gnt); -+ rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc00f0038); -+ rtw_write32(rtwdev, REG_LTECOEX_PATH_CONTROL, bak->lte_path); -+} -+ -+/* set all ADDA registers to the given value */ -+static inline void rtw8723x_iqk_path_adda_on(struct rtw_dev *rtwdev, u32 value) -+{ -+ for (int i = 0; i < RTW8723X_IQK_ADDA_REG_NUM; i++) -+ rtw_write32(rtwdev, rtw8723x_common.iqk_adda_regs[i], value); -+} -+ -+#endif /* __RTW8723X_H__ */ diff --git a/packages/linux/patches/rtlwifi/6.10/0009-6.10-wifi-rtw88-Debug-output-for-rtw8723x-EFUSE.patch b/packages/linux/patches/rtlwifi/6.10/0009-6.10-wifi-rtw88-Debug-output-for-rtw8723x-EFUSE.patch deleted file mode 100644 index e4c869b89e..0000000000 --- a/packages/linux/patches/rtlwifi/6.10/0009-6.10-wifi-rtw88-Debug-output-for-rtw8723x-EFUSE.patch +++ /dev/null @@ -1,231 +0,0 @@ -From da2abdcdbbb8c498fcfb2bc88ba56028bccdbc8a Mon Sep 17 00:00:00 2001 -From: Fiona Klute -Date: Mon, 11 Mar 2024 11:37:06 +0100 -Subject: [PATCH] wifi: rtw88: Debug output for rtw8723x EFUSE - -Some 8703b chips contain invalid EFUSE data, getting detailed -information is critical when analyzing issues caused by that. - -Acked-by: Ping-Ke Shih -Tested-by: Pavel Machek -Signed-off-by: Fiona Klute -Signed-off-by: Kalle Valo -Link: https://msgid.link/20240311103735.615541-3-fiona.klute@gmx.de ---- - drivers/net/wireless/realtek/rtw88/rtw8723x.c | 159 ++++++++++++++++++ - drivers/net/wireless/realtek/rtw88/rtw8723x.h | 11 ++ - 2 files changed, 170 insertions(+) - -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8723x.c b/drivers/net/wireless/realtek/rtw88/rtw8723x.c -index c23650c5a20080..0d0b6c2cb9aa19 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8723x.c -+++ b/drivers/net/wireless/realtek/rtw88/rtw8723x.c -@@ -63,6 +63,163 @@ static void __rtw8723x_lck(struct rtw_dev *rtwdev) - rtw_write8(rtwdev, REG_TXPAUSE, 0x00); - } - -+#define DBG_EFUSE_VAL(rtwdev, map, name) \ -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, # name "=0x%02x\n", \ -+ (map)->name) -+#define DBG_EFUSE_2BYTE(rtwdev, map, name) \ -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, # name "=0x%02x%02x\n", \ -+ (map)->name[0], (map)->name[1]) -+ -+static void rtw8723xe_efuse_debug(struct rtw_dev *rtwdev, -+ struct rtw8723x_efuse *map) -+{ -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "mac_addr=%pM\n", map->e.mac_addr); -+ DBG_EFUSE_2BYTE(rtwdev, map, e.vendor_id); -+ DBG_EFUSE_2BYTE(rtwdev, map, e.device_id); -+ DBG_EFUSE_2BYTE(rtwdev, map, e.sub_vendor_id); -+ DBG_EFUSE_2BYTE(rtwdev, map, e.sub_device_id); -+} -+ -+static void rtw8723xu_efuse_debug(struct rtw_dev *rtwdev, -+ struct rtw8723x_efuse *map) -+{ -+ DBG_EFUSE_2BYTE(rtwdev, map, u.vendor_id); -+ DBG_EFUSE_2BYTE(rtwdev, map, u.product_id); -+ DBG_EFUSE_VAL(rtwdev, map, u.usb_option); -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "mac_addr=%pM\n", map->u.mac_addr); -+} -+ -+static void rtw8723xs_efuse_debug(struct rtw_dev *rtwdev, -+ struct rtw8723x_efuse *map) -+{ -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "mac_addr=%pM\n", map->s.mac_addr); -+} -+ -+static void __rtw8723x_debug_txpwr_limit(struct rtw_dev *rtwdev, -+ struct rtw_txpwr_idx *table, -+ int tx_path_count) -+{ -+ if (!rtw_dbg_is_enabled(rtwdev, RTW_DBG_EFUSE)) -+ return; -+ -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, -+ "Power index table (2.4G):\n"); -+ /* CCK base */ -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "CCK base\n"); -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF G0 G1 G2 G3 G4 G5\n"); -+ for (int i = 0; i < tx_path_count; i++) -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, -+ "[%c]: %3u %3u %3u %3u %3u %3u\n", -+ 'A' + i, -+ table[i].pwr_idx_2g.cck_base[0], -+ table[i].pwr_idx_2g.cck_base[1], -+ table[i].pwr_idx_2g.cck_base[2], -+ table[i].pwr_idx_2g.cck_base[3], -+ table[i].pwr_idx_2g.cck_base[4], -+ table[i].pwr_idx_2g.cck_base[5]); -+ /* CCK diff */ -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "CCK diff\n"); -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF 1S 2S 3S 4S\n"); -+ for (int i = 0; i < tx_path_count; i++) -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, -+ "[%c]: %2d %2d %2d %2d\n", -+ 'A' + i, 0 /* no diff for 1S */, -+ table[i].pwr_idx_2g.ht_2s_diff.cck, -+ table[i].pwr_idx_2g.ht_3s_diff.cck, -+ table[i].pwr_idx_2g.ht_4s_diff.cck); -+ /* BW40-1S base */ -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "BW40-1S base\n"); -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF G0 G1 G2 G3 G4\n"); -+ for (int i = 0; i < tx_path_count; i++) -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, -+ "[%c]: %3u %3u %3u %3u %3u\n", -+ 'A' + i, -+ table[i].pwr_idx_2g.bw40_base[0], -+ table[i].pwr_idx_2g.bw40_base[1], -+ table[i].pwr_idx_2g.bw40_base[2], -+ table[i].pwr_idx_2g.bw40_base[3], -+ table[i].pwr_idx_2g.bw40_base[4]); -+ /* OFDM diff */ -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "OFDM diff\n"); -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF 1S 2S 3S 4S\n"); -+ for (int i = 0; i < tx_path_count; i++) -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, -+ "[%c]: %2d %2d %2d %2d\n", -+ 'A' + i, -+ table[i].pwr_idx_2g.ht_1s_diff.ofdm, -+ table[i].pwr_idx_2g.ht_2s_diff.ofdm, -+ table[i].pwr_idx_2g.ht_3s_diff.ofdm, -+ table[i].pwr_idx_2g.ht_4s_diff.ofdm); -+ /* BW20 diff */ -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "BW20 diff\n"); -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF 1S 2S 3S 4S\n"); -+ for (int i = 0; i < tx_path_count; i++) -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, -+ "[%c]: %2d %2d %2d %2d\n", -+ 'A' + i, -+ table[i].pwr_idx_2g.ht_1s_diff.bw20, -+ table[i].pwr_idx_2g.ht_2s_diff.bw20, -+ table[i].pwr_idx_2g.ht_3s_diff.bw20, -+ table[i].pwr_idx_2g.ht_4s_diff.bw20); -+ /* BW40 diff */ -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "BW40 diff\n"); -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF 1S 2S 3S 4S\n"); -+ for (int i = 0; i < tx_path_count; i++) -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, -+ "[%c]: %2d %2d %2d %2d\n", -+ 'A' + i, 0 /* no diff for 1S */, -+ table[i].pwr_idx_2g.ht_2s_diff.bw40, -+ table[i].pwr_idx_2g.ht_3s_diff.bw40, -+ table[i].pwr_idx_2g.ht_4s_diff.bw40); -+} -+ -+static void efuse_debug_dump(struct rtw_dev *rtwdev, -+ struct rtw8723x_efuse *map) -+{ -+ if (!rtw_dbg_is_enabled(rtwdev, RTW_DBG_EFUSE)) -+ return; -+ -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "EFUSE raw logical map:\n"); -+ print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1, -+ (u8 *)map, sizeof(struct rtw8723x_efuse), false); -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "Parsed rtw8723x EFUSE data:\n"); -+ DBG_EFUSE_VAL(rtwdev, map, rtl_id); -+ DBG_EFUSE_VAL(rtwdev, map, afe); -+ rtw8723x_debug_txpwr_limit(rtwdev, map->txpwr_idx_table, 4); -+ DBG_EFUSE_VAL(rtwdev, map, channel_plan); -+ DBG_EFUSE_VAL(rtwdev, map, xtal_k); -+ DBG_EFUSE_VAL(rtwdev, map, thermal_meter); -+ DBG_EFUSE_VAL(rtwdev, map, iqk_lck); -+ DBG_EFUSE_VAL(rtwdev, map, pa_type); -+ DBG_EFUSE_2BYTE(rtwdev, map, lna_type_2g); -+ DBG_EFUSE_2BYTE(rtwdev, map, lna_type_5g); -+ DBG_EFUSE_VAL(rtwdev, map, rf_board_option); -+ DBG_EFUSE_VAL(rtwdev, map, rf_feature_option); -+ DBG_EFUSE_VAL(rtwdev, map, rf_bt_setting); -+ DBG_EFUSE_VAL(rtwdev, map, eeprom_version); -+ DBG_EFUSE_VAL(rtwdev, map, eeprom_customer_id); -+ DBG_EFUSE_VAL(rtwdev, map, tx_bb_swing_setting_2g); -+ DBG_EFUSE_VAL(rtwdev, map, tx_pwr_calibrate_rate); -+ DBG_EFUSE_VAL(rtwdev, map, rf_antenna_option); -+ DBG_EFUSE_VAL(rtwdev, map, rfe_option); -+ DBG_EFUSE_2BYTE(rtwdev, map, country_code); -+ -+ switch (rtw_hci_type(rtwdev)) { -+ case RTW_HCI_TYPE_PCIE: -+ rtw8723xe_efuse_debug(rtwdev, map); -+ break; -+ case RTW_HCI_TYPE_USB: -+ rtw8723xu_efuse_debug(rtwdev, map); -+ break; -+ case RTW_HCI_TYPE_SDIO: -+ rtw8723xs_efuse_debug(rtwdev, map); -+ break; -+ default: -+ /* unsupported now */ -+ break; -+ } -+} -+ - static void rtw8723xe_efuse_parsing(struct rtw_efuse *efuse, - struct rtw8723x_efuse *map) - { -@@ -88,6 +245,7 @@ static int __rtw8723x_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) - int i; - - map = (struct rtw8723x_efuse *)log_map; -+ efuse_debug_dump(rtwdev, map); - - efuse->rfe_option = 0; - efuse->rf_board_option = map->rf_board_option; -@@ -553,6 +711,7 @@ const struct rtw8723x_common rtw8723x_common = { - .pwrtrack_set_xtal = __rtw8723x_pwrtrack_set_xtal, - .coex_cfg_init = __rtw8723x_coex_cfg_init, - .fill_txdesc_checksum = __rtw8723x_fill_txdesc_checksum, -+ .debug_txpwr_limit = __rtw8723x_debug_txpwr_limit, - }; - EXPORT_SYMBOL(rtw8723x_common); - -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8723x.h b/drivers/net/wireless/realtek/rtw88/rtw8723x.h -index cace285fc03397..d6dfee5a1806e2 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8723x.h -+++ b/drivers/net/wireless/realtek/rtw88/rtw8723x.h -@@ -154,6 +154,9 @@ struct rtw8723x_common { - void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev, - struct rtw_tx_pkt_info *pkt_info, - u8 *txdesc); -+ void (*debug_txpwr_limit)(struct rtw_dev *rtwdev, -+ struct rtw_txpwr_idx *table, -+ int tx_path_count); - }; - - extern const struct rtw8723x_common rtw8723x_common; -@@ -346,6 +349,14 @@ static inline s32 iqk_mult(s32 x, s32 y, s32 *ext) - return (t >> 8); /* Q.16 --> Q.8 */ - } - -+static inline -+void rtw8723x_debug_txpwr_limit(struct rtw_dev *rtwdev, -+ struct rtw_txpwr_idx *table, -+ int tx_path_count) -+{ -+ rtw8723x_common.debug_txpwr_limit(rtwdev, table, tx_path_count); -+} -+ - static inline void rtw8723x_lck(struct rtw_dev *rtwdev) - { - rtw8723x_common.lck(rtwdev); diff --git a/packages/linux/patches/rtlwifi/6.10/0010-6.10-wifi-rtw88-Add-definitions-for-8703b-chip.patch b/packages/linux/patches/rtlwifi/6.10/0010-6.10-wifi-rtw88-Add-definitions-for-8703b-chip.patch deleted file mode 100644 index 72035689a5..0000000000 --- a/packages/linux/patches/rtlwifi/6.10/0010-6.10-wifi-rtw88-Add-definitions-for-8703b-chip.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 9bb762b3a957faffb4ba596165525521c07ad2eb Mon Sep 17 00:00:00 2001 -From: Fiona Klute -Date: Mon, 11 Mar 2024 11:37:07 +0100 -Subject: [PATCH] wifi: rtw88: Add definitions for 8703b chip - -default_cck_index is used in power track, the rx_cck_agc_report_type -for RX PHY status. GET_RX_DESC_BW is an RX descriptor field not used -by the other chip drivers. - -Acked-by: Ping-Ke Shih -Tested-by: Pavel Machek -Signed-off-by: Fiona Klute -Signed-off-by: Kalle Valo -Link: https://msgid.link/20240311103735.615541-4-fiona.klute@gmx.de ---- - drivers/net/wireless/realtek/rtw88/main.h | 3 +++ - drivers/net/wireless/realtek/rtw88/rtw8723x.h | 11 +++++++++++ - drivers/net/wireless/realtek/rtw88/rx.h | 2 ++ - 3 files changed, 16 insertions(+) - -diff --git a/drivers/net/wireless/realtek/rtw88/main.h b/drivers/net/wireless/realtek/rtw88/main.h -index e14d1da43940fa..49894331f7b495 100644 ---- a/drivers/net/wireless/realtek/rtw88/main.h -+++ b/drivers/net/wireless/realtek/rtw88/main.h -@@ -187,6 +187,7 @@ enum rtw_chip_type { - RTW_CHIP_TYPE_8822C, - RTW_CHIP_TYPE_8723D, - RTW_CHIP_TYPE_8821C, -+ RTW_CHIP_TYPE_8703B, - }; - - enum rtw_tx_queue_type { -@@ -1700,11 +1701,13 @@ struct rtw_dm_info { - s8 delta_power_index[RTW_RF_PATH_MAX]; - s8 delta_power_index_last[RTW_RF_PATH_MAX]; - u8 default_ofdm_index; -+ u8 default_cck_index; - bool pwr_trk_triggered; - bool pwr_trk_init_trigger; - struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; - s8 txagc_remnant_cck; - s8 txagc_remnant_ofdm; -+ u8 rx_cck_agc_report_type; - - /* backup dack results for each path and I/Q */ - u32 dack_adck[RTW_RF_PATH_MAX]; -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8723x.h b/drivers/net/wireless/realtek/rtw88/rtw8723x.h -index d6dfee5a1806e2..e93bfce994bf82 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8723x.h -+++ b/drivers/net/wireless/realtek/rtw88/rtw8723x.h -@@ -165,6 +165,8 @@ extern const struct rtw8723x_common rtw8723x_common; - #define MAX_TOLERANCE 5 - #define IQK_TX_X_ERR 0x142 - #define IQK_TX_Y_ERR 0x42 -+#define IQK_RX_X_ERR 0x132 -+#define IQK_RX_Y_ERR 0x36 - #define IQK_RX_X_UPPER 0x11a - #define IQK_RX_X_LOWER 0xe6 - #define IQK_RX_Y_LMT 0x1a -@@ -177,6 +179,10 @@ extern const struct rtw8723x_common rtw8723x_common; - #define DIS_3WIRE 0xccf000c0 - #define EN_3WIRE 0xccc000c0 - #define START_PSD 0x400000 -+#define FREQ_CH5 0xfccd -+#define FREQ_CH6 0xfc4d -+#define FREQ_CH7 0xffcd -+#define FREQ_CH8 0xff4d - #define FREQ_CH13 0xfccd - #define FREQ_CH14 0xff9a - #define RFCFGCH_CHANNEL_MASK GENMASK(7, 0) -@@ -239,10 +245,13 @@ extern const struct rtw8723x_common rtw8723x_common; - #define BIT_MASK_OFDM0_EXT_C BIT(29) - #define BIT_MASK_OFDM0_EXTS (BIT(31) | BIT(29) | BIT(28)) - #define BIT_SET_OFDM0_EXTS(a, c, d) (((a) << 31) | ((c) << 29) | ((d) << 28)) -+#define BIT_MASK_OFDM0_EXTS_B (BIT(27) | BIT(25) | BIT(24)) -+#define BIT_SET_OFDM0_EXTS_B(a, c, d) (((a) << 27) | ((c) << 25) | ((d) << 24)) - #define REG_OFDM0_XAAGC1 0x0c50 - #define REG_OFDM0_XBAGC1 0x0c58 - #define REG_AGCRSSI 0x0c78 - #define REG_OFDM_0_XA_TX_IQ_IMBALANCE 0x0c80 -+#define REG_OFDM_0_XB_TX_IQ_IMBALANCE 0x0c88 - #define BIT_MASK_TXIQ_ELM_A 0x03ff - #define BIT_SET_TXIQ_ELM_ACD(a, c, d) (((d) << 22) | (((c) & 0x3F) << 16) | \ - ((a) & 0x03ff)) -@@ -303,6 +312,8 @@ extern const struct rtw8723x_common rtw8723x_common; - #define REG_IQK_AGC_RSP_11N 0x0e4c - #define REG_TX_IQK_TONE_B 0x0e50 - #define REG_RX_IQK_TONE_B 0x0e54 -+#define REG_TXIQK_PI_B 0x0e58 -+#define REG_RXIQK_PI_B 0x0e5c - #define REG_IQK_RES_TX 0x0e94 - #define BIT_MASK_RES_TX GENMASK(25, 16) - #define REG_IQK_RES_TY 0x0e9c -diff --git a/drivers/net/wireless/realtek/rtw88/rx.h b/drivers/net/wireless/realtek/rtw88/rx.h -index 3342e37612813a..d3668c4efc24d5 100644 ---- a/drivers/net/wireless/realtek/rtw88/rx.h -+++ b/drivers/net/wireless/realtek/rtw88/rx.h -@@ -40,6 +40,8 @@ enum rtw_rx_desc_enc { - le32_get_bits(*((__le32 *)(rxdesc) + 0x02), GENMASK(30, 29)) - #define GET_RX_DESC_TSFL(rxdesc) \ - le32_get_bits(*((__le32 *)(rxdesc) + 0x05), GENMASK(31, 0)) -+#define GET_RX_DESC_BW(rxdesc) \ -+ (le32_get_bits(*((__le32 *)(rxdesc) + 0x04), GENMASK(31, 24))) - - void rtw_rx_stats(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, - struct sk_buff *skb); diff --git a/packages/linux/patches/rtlwifi/6.10/0011-6.10-wifi-rtw88-Add-rtw8703b.c.patch b/packages/linux/patches/rtlwifi/6.10/0011-6.10-wifi-rtw88-Add-rtw8703b.c.patch deleted file mode 100644 index 8476c24e9c..0000000000 --- a/packages/linux/patches/rtlwifi/6.10/0011-6.10-wifi-rtw88-Add-rtw8703b.c.patch +++ /dev/null @@ -1,2132 +0,0 @@ -From 61a486bcd7820ddaa4adc110bfa96f0b3ec3fd8c Mon Sep 17 00:00:00 2001 -From: Fiona Klute -Date: Mon, 11 Mar 2024 11:37:09 +0100 -Subject: [PATCH] wifi: rtw88: Add rtw8703b.c - -This is the main source for the new rtw88_8703b chip driver. - -Acked-by: Ping-Ke Shih -Tested-by: Pavel Machek -Signed-off-by: Fiona Klute -Signed-off-by: Kalle Valo -Link: https://msgid.link/20240311103735.615541-6-fiona.klute@gmx.de ---- - drivers/net/wireless/realtek/rtw88/rtw8703b.c | 2109 +++++++++++++++++ - 1 file changed, 2109 insertions(+) - create mode 100644 drivers/net/wireless/realtek/rtw88/rtw8703b.c - -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8703b.c b/drivers/net/wireless/realtek/rtw88/rtw8703b.c -new file mode 100644 -index 00000000000000..8919f9e11f0378 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtw88/rtw8703b.c -@@ -0,0 +1,2109 @@ -+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause -+/* Copyright Fiona Klute */ -+ -+#include -+#include "main.h" -+#include "coex.h" -+#include "debug.h" -+#include "mac.h" -+#include "phy.h" -+#include "reg.h" -+#include "rx.h" -+#include "rtw8703b.h" -+#include "rtw8703b_tables.h" -+#include "rtw8723x.h" -+ -+#define BIT_MASK_TXQ_INIT (BIT(7)) -+#define WLAN_RL_VAL 0x3030 -+/* disable BAR */ -+#define WLAN_BAR_VAL 0x0201ffff -+#define WLAN_PIFS_VAL 0 -+#define WLAN_RX_PKT_LIMIT 0x18 -+#define WLAN_SLOT_TIME 0x09 -+#define WLAN_SPEC_SIFS 0x100a -+#define WLAN_MAX_AGG_NR 0x1f -+#define WLAN_AMPDU_MAX_TIME 0x70 -+ -+/* unit is 32us */ -+#define TBTT_PROHIBIT_SETUP_TIME 0x04 -+#define TBTT_PROHIBIT_HOLD_TIME 0x80 -+#define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64 -+ -+/* raw pkt_stat->drv_info_sz is in unit of 8-bytes */ -+#define RX_DRV_INFO_SZ_UNIT_8703B 8 -+ -+#define TRANS_SEQ_END \ -+ 0xFFFF, \ -+ RTW_PWR_CUT_ALL_MSK, \ -+ RTW_PWR_INTF_ALL_MSK, \ -+ 0, \ -+ RTW_PWR_CMD_END, 0, 0 -+ -+/* rssi in percentage % (dbm = % - 100) */ -+/* These are used to select simple signal quality levels, might need -+ * tweaking. Same for rf_para tables below. -+ */ -+static const u8 wl_rssi_step_8703b[] = {60, 50, 44, 30}; -+static const u8 bt_rssi_step_8703b[] = {30, 30, 30, 30}; -+static const struct coex_5g_afh_map afh_5g_8703b[] = { {0, 0, 0} }; -+ -+/* Actually decreasing wifi TX power/RX gain isn't implemented in -+ * rtw8703b, but hopefully adjusting the BT side helps. -+ */ -+static const struct coex_rf_para rf_para_tx_8703b[] = { -+ {0, 0, false, 7}, /* for normal */ -+ {0, 10, false, 7}, /* for WL-CPT */ -+ {1, 0, true, 4}, -+ {1, 2, true, 4}, -+ {1, 10, true, 4}, -+ {1, 15, true, 4} -+}; -+ -+static const struct coex_rf_para rf_para_rx_8703b[] = { -+ {0, 0, false, 7}, /* for normal */ -+ {0, 10, false, 7}, /* for WL-CPT */ -+ {1, 0, true, 5}, -+ {1, 2, true, 5}, -+ {1, 10, true, 5}, -+ {1, 15, true, 5} -+}; -+ -+static const u32 rtw8703b_ofdm_swing_table[] = { -+ 0x0b40002d, /* 0, -15.0dB */ -+ 0x0c000030, /* 1, -14.5dB */ -+ 0x0cc00033, /* 2, -14.0dB */ -+ 0x0d800036, /* 3, -13.5dB */ -+ 0x0e400039, /* 4, -13.0dB */ -+ 0x0f00003c, /* 5, -12.5dB */ -+ 0x10000040, /* 6, -12.0dB */ -+ 0x11000044, /* 7, -11.5dB */ -+ 0x12000048, /* 8, -11.0dB */ -+ 0x1300004c, /* 9, -10.5dB */ -+ 0x14400051, /* 10, -10.0dB */ -+ 0x15800056, /* 11, -9.5dB */ -+ 0x16c0005b, /* 12, -9.0dB */ -+ 0x18000060, /* 13, -8.5dB */ -+ 0x19800066, /* 14, -8.0dB */ -+ 0x1b00006c, /* 15, -7.5dB */ -+ 0x1c800072, /* 16, -7.0dB */ -+ 0x1e400079, /* 17, -6.5dB */ -+ 0x20000080, /* 18, -6.0dB */ -+ 0x22000088, /* 19, -5.5dB */ -+ 0x24000090, /* 20, -5.0dB */ -+ 0x26000098, /* 21, -4.5dB */ -+ 0x288000a2, /* 22, -4.0dB */ -+ 0x2ac000ab, /* 23, -3.5dB */ -+ 0x2d4000b5, /* 24, -3.0dB */ -+ 0x300000c0, /* 25, -2.5dB */ -+ 0x32c000cb, /* 26, -2.0dB */ -+ 0x35c000d7, /* 27, -1.5dB */ -+ 0x390000e4, /* 28, -1.0dB */ -+ 0x3c8000f2, /* 29, -0.5dB */ -+ 0x40000100, /* 30, +0dB */ -+ 0x43c0010f, /* 31, +0.5dB */ -+ 0x47c0011f, /* 32, +1.0dB */ -+ 0x4c000130, /* 33, +1.5dB */ -+ 0x50800142, /* 34, +2.0dB */ -+ 0x55400155, /* 35, +2.5dB */ -+ 0x5a400169, /* 36, +3.0dB */ -+ 0x5fc0017f, /* 37, +3.5dB */ -+ 0x65400195, /* 38, +4.0dB */ -+ 0x6b8001ae, /* 39, +4.5dB */ -+ 0x71c001c7, /* 40, +5.0dB */ -+ 0x788001e2, /* 41, +5.5dB */ -+ 0x7f8001fe /* 42, +6.0dB */ -+}; -+ -+static const u32 rtw8703b_cck_pwr_regs[] = { -+ 0x0a22, 0x0a23, 0x0a24, 0x0a25, 0x0a26, 0x0a27, 0x0a28, 0x0a29, -+ 0x0a9a, 0x0a9b, 0x0a9c, 0x0a9d, 0x0aa0, 0x0aa1, 0x0aa2, 0x0aa3, -+}; -+ -+static const u8 rtw8703b_cck_swing_table[][16] = { -+ {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ -+ {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ -+ {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ -+ {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ -+ {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ -+ {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ -+ {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ -+ {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ -+ {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ -+ {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ -+ {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ -+ {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ -+ {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ -+ {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ -+ {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ -+ {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ -+ {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ -+ {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ -+ {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ -+ {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ -+ {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ -+}; -+ -+#define RTW_OFDM_SWING_TABLE_SIZE ARRAY_SIZE(rtw8703b_ofdm_swing_table) -+#define RTW_CCK_SWING_TABLE_SIZE ARRAY_SIZE(rtw8703b_cck_swing_table) -+ -+static const struct rtw_pwr_seq_cmd trans_pre_enable_8703b[] = { -+ /* set up external crystal (XTAL) */ -+ {REG_PAD_CTRL1 + 2, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, -+ /* set CLK_REQ to high active */ -+ {0x0069, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, -+ /* unlock ISO/CLK/power control register */ -+ {REG_RSV_CTRL, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, 0xff, 0}, -+ {TRANS_SEQ_END}, -+}; -+ -+static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8703b[] = { -+ {0x0005, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(7), 0}, -+ {TRANS_SEQ_END}, -+}; -+ -+static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8703b[] = { -+ {0x0023, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_SDIO_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, -+ {0x0007, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_SDIO_MSK | RTW_PWR_INTF_USB_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, 0xFF, 0x20}, -+ {0x0006, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(0), 0}, -+ {0x0005, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, -+ {TRANS_SEQ_END}, -+}; -+ -+static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8703b[] = { -+ {0x0020, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, -+ {0x0067, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(4), 0}, -+ {0x0001, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, -+ {0x0000, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(5), 0}, -+ {0x0005, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, -+ {0x0075, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_PCI_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, -+ {0x0004, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_PCI_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, -+ {0x0004, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_PCI_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(3), 0}, -+ /* wait for power ready */ -+ {0x0006, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, -+ {0x0075, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_PCI_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(0), 0}, -+ {0x0006, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, -+ {0x0005, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(7), 0}, -+ {0x0005, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, -+ {0x0005, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, -+ {0x0005, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_POLLING, BIT(0), 0}, -+ {0x0010, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, -+ {0x0049, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, -+ {0x0063, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, -+ {0x0062, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(1), 0}, -+ {0x0058, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, -+ {0x005A, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, -+ {0x0068, -+ RTW_PWR_CUT_TEST_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, -+ {0x0069, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, -+ {TRANS_SEQ_END}, -+}; -+ -+static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8703b[] = { -+ {0x001f, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, 0xff, 0}, -+ {0x0049, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(1), 0}, -+ {0x0006, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, -+ {0x0005, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, -+ {0x0005, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_POLLING, BIT(1), 0}, -+ {0x0010, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(6), 0}, -+ {0x0000, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, -+ {0x0020, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(0), 0}, -+ {TRANS_SEQ_END}, -+}; -+ -+static const struct rtw_pwr_seq_cmd trans_act_to_reset_mcu_8703b[] = { -+ {REG_SYS_FUNC_EN + 1, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_SDIO_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT_FEN_CPUEN, 0}, -+ /* reset MCU ready */ -+ {REG_MCUFW_CTRL, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_SDIO_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, 0xff, 0}, -+ /* reset MCU IO wrapper */ -+ {REG_RSV_CTRL + 1, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_SDIO_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(0), 0}, -+ {REG_RSV_CTRL + 1, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_SDIO_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(0), 1}, -+ {TRANS_SEQ_END}, -+}; -+ -+static const struct rtw_pwr_seq_cmd trans_act_to_lps_8703b[] = { -+ {0x0301, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, 0xff, 0xff}, -+ {0x0522, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, 0xff, 0xff}, -+ {0x05f8, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_POLLING, 0xff, 0}, -+ {0x05f9, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_POLLING, 0xff, 0}, -+ {0x05fa, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_POLLING, 0xff, 0}, -+ {0x05fb, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_POLLING, 0xff, 0}, -+ {0x0002, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(0), 0}, -+ {0x0002, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US}, -+ {0x0002, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(1), 0}, -+ {0x0100, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, 0xff, 0x03}, -+ {0x0101, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(1), 0}, -+ {0x0093, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_SDIO_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, 0xff, 0}, -+ {0x0553, -+ RTW_PWR_CUT_ALL_MSK, -+ RTW_PWR_INTF_ALL_MSK, -+ RTW_PWR_ADDR_MAC, -+ RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, -+ {TRANS_SEQ_END}, -+}; -+ -+static const struct rtw_pwr_seq_cmd *card_enable_flow_8703b[] = { -+ trans_pre_enable_8703b, -+ trans_carddis_to_cardemu_8703b, -+ trans_cardemu_to_act_8703b, -+ NULL -+}; -+ -+static const struct rtw_pwr_seq_cmd *card_disable_flow_8703b[] = { -+ trans_act_to_lps_8703b, -+ trans_act_to_reset_mcu_8703b, -+ trans_act_to_cardemu_8703b, -+ trans_cardemu_to_carddis_8703b, -+ NULL -+}; -+ -+static const struct rtw_rfe_def rtw8703b_rfe_defs[] = { -+ [0] = { .phy_pg_tbl = &rtw8703b_bb_pg_tbl, -+ .txpwr_lmt_tbl = &rtw8703b_txpwr_lmt_tbl,}, -+}; -+ -+static const struct rtw_page_table page_table_8703b[] = { -+ {12, 2, 2, 0, 1}, -+ {12, 2, 2, 0, 1}, -+ {12, 2, 2, 0, 1}, -+ {12, 2, 2, 0, 1}, -+ {12, 2, 2, 0, 1}, -+}; -+ -+static const struct rtw_rqpn rqpn_table_8703b[] = { -+ {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, -+ RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, -+ RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, -+ {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, -+ RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, -+ RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, -+ {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, -+ RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, -+ RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, -+ {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, -+ RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, -+ RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, -+ {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, -+ RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, -+ RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, -+}; -+ -+/* Default power index table for RTL8703B, used if EFUSE does not -+ * contain valid data. Replaces EFUSE data from offset 0x10 (start of -+ * txpwr_idx_table). -+ */ -+static const u8 rtw8703b_txpwr_idx_table[] = { -+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, -+ 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02 -+}; -+ -+static void try_mac_from_devicetree(struct rtw_dev *rtwdev) -+{ -+ struct device_node *node = rtwdev->dev->of_node; -+ struct rtw_efuse *efuse = &rtwdev->efuse; -+ int ret; -+ -+ if (node) { -+ ret = of_get_mac_address(node, efuse->addr); -+ if (ret == 0) { -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, -+ "got wifi mac address from DT: %pM\n", -+ efuse->addr); -+ } -+ } -+} -+ -+#define DBG_EFUSE_FIX(rtwdev, name) \ -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, "Fixed invalid EFUSE value: " \ -+ # name "=0x%x\n", rtwdev->efuse.name) -+ -+static int rtw8703b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) -+{ -+ struct rtw_efuse *efuse = &rtwdev->efuse; -+ u8 *pwr = (u8 *)efuse->txpwr_idx_table; -+ bool valid = false; -+ int ret; -+ -+ ret = rtw8723x_read_efuse(rtwdev, log_map); -+ if (ret != 0) -+ return ret; -+ -+ if (!is_valid_ether_addr(efuse->addr)) -+ try_mac_from_devicetree(rtwdev); -+ -+ /* If TX power index table in EFUSE is invalid, fall back to -+ * built-in table. -+ */ -+ for (int i = 0; i < ARRAY_SIZE(rtw8703b_txpwr_idx_table); i++) -+ if (pwr[i] != 0xff) { -+ valid = true; -+ break; -+ } -+ if (!valid) { -+ for (int i = 0; i < ARRAY_SIZE(rtw8703b_txpwr_idx_table); i++) -+ pwr[i] = rtw8703b_txpwr_idx_table[i]; -+ rtw_dbg(rtwdev, RTW_DBG_EFUSE, -+ "Replaced invalid EFUSE TX power index table."); -+ rtw8723x_debug_txpwr_limit(rtwdev, -+ efuse->txpwr_idx_table, 2); -+ } -+ -+ /* Override invalid antenna settings. */ -+ if (efuse->bt_setting == 0xff) { -+ /* shared antenna */ -+ efuse->bt_setting |= BIT(0); -+ /* RF path A */ -+ efuse->bt_setting &= ~BIT(6); -+ DBG_EFUSE_FIX(rtwdev, bt_setting); -+ } -+ -+ /* Override invalid board options: The coex code incorrectly -+ * assumes that if bits 6 & 7 are set the board doesn't -+ * support coex. Regd is also derived from rf_board_option and -+ * should be 0 if there's no valid data. -+ */ -+ if (efuse->rf_board_option == 0xff) { -+ efuse->regd = 0; -+ efuse->rf_board_option &= GENMASK(5, 0); -+ DBG_EFUSE_FIX(rtwdev, rf_board_option); -+ } -+ -+ /* Override invalid crystal cap setting, default comes from -+ * vendor driver. Chip specific. -+ */ -+ if (efuse->crystal_cap == 0xff) { -+ efuse->crystal_cap = 0x20; -+ DBG_EFUSE_FIX(rtwdev, crystal_cap); -+ } -+ -+ return 0; -+} -+ -+static void rtw8703b_pwrtrack_init(struct rtw_dev *rtwdev) -+{ -+ struct rtw_dm_info *dm_info = &rtwdev->dm_info; -+ u8 path; -+ -+ /* TODO: The vendor driver selects these using tables in -+ * halrf_powertracking_ce.c, functions are called -+ * get_swing_index and get_cck_swing_index. There the current -+ * fixed values are only the defaults in case no match is -+ * found. -+ */ -+ dm_info->default_ofdm_index = 30; -+ dm_info->default_cck_index = 20; -+ -+ for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { -+ ewma_thermal_init(&dm_info->avg_thermal[path]); -+ dm_info->delta_power_index[path] = 0; -+ } -+ dm_info->pwr_trk_triggered = false; -+ dm_info->pwr_trk_init_trigger = true; -+ dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; -+ dm_info->txagc_remnant_cck = 0; -+ dm_info->txagc_remnant_ofdm = 0; -+} -+ -+static void rtw8703b_phy_set_param(struct rtw_dev *rtwdev) -+{ -+ u8 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; -+ -+ /* power on BB/RF domain */ -+ rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, -+ BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); -+ rtw_write8_set(rtwdev, REG_RF_CTRL, -+ BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, 0x0780); -+ rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80); -+ -+ rtw_phy_load_tables(rtwdev); -+ -+ rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF); -+ /* 0xff is from vendor driver, rtw8723d uses -+ * BIT_HIQ_NO_LMT_EN_ROOT. Comment in vendor driver: "Packet -+ * in Hi Queue Tx immediately". I wonder if setting all bits -+ * is really necessary. -+ */ -+ rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, 0xff); -+ rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN); -+ -+ rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, -+ xtal_cap | (xtal_cap << 6)); -+ rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN); -+ -+ /* Init EDCA */ -+ rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SPEC_SIFS); -+ rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS); -+ rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS); /* CCK */ -+ rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS); /* OFDM */ -+ /* TXOP */ -+ rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226); -+ rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324); -+ rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B); -+ rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F); -+ -+ /* Init retry */ -+ rtw_write8(rtwdev, REG_ACKTO, 0x40); -+ -+ /* Set up RX aggregation. sdio.c also sets DMA mode, but not -+ * the burst parameters. -+ */ -+ rtw_write8(rtwdev, REG_RXDMA_MODE, -+ BIT_DMA_MODE | -+ FIELD_PREP_CONST(BIT_MASK_AGG_BURST_NUM, AGG_BURST_NUM) | -+ FIELD_PREP_CONST(BIT_MASK_AGG_BURST_SIZE, AGG_BURST_SIZE)); -+ -+ /* Init beacon parameters */ -+ rtw_write8(rtwdev, REG_BCN_CTRL, -+ BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT); -+ rtw_write8(rtwdev, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME); -+ rtw_write8(rtwdev, REG_TBTT_PROHIBIT + 1, -+ TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF); -+ rtw_write8(rtwdev, REG_TBTT_PROHIBIT + 2, -+ (rtw_read8(rtwdev, REG_TBTT_PROHIBIT + 2) & 0xF0) -+ | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8)); -+ -+ /* configure packet burst */ -+ rtw_write8_set(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU); -+ rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT); -+ rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR); -+ rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL); -+ rtw_write8_clr(rtwdev, REG_FWHW_TXQ_CTRL, BIT_MASK_TXQ_INIT); -+ rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME); -+ -+ rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); -+ rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL); -+ rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL); -+ rtw_write16(rtwdev, REG_ATIMWND, 0x2); -+ -+ rtw_phy_init(rtwdev); -+ -+ if (rtw_read32_mask(rtwdev, REG_BB_AMP, BIT_MASK_RX_LNA) != 0) { -+ rtwdev->dm_info.rx_cck_agc_report_type = 1; -+ } else { -+ rtwdev->dm_info.rx_cck_agc_report_type = 0; -+ rtw_warn(rtwdev, "unexpected cck agc report type"); -+ } -+ -+ rtw8723x_lck(rtwdev); -+ -+ rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); -+ rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20); -+ -+ rtw8703b_pwrtrack_init(rtwdev); -+} -+ -+static bool rtw8703b_check_spur_ov_thres(struct rtw_dev *rtwdev, -+ u32 freq, u32 thres) -+{ -+ bool ret = false; -+ -+ rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE); -+ rtw_write32(rtwdev, REG_PSDFN, freq); -+ rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq); -+ -+ msleep(30); -+ if (rtw_read32(rtwdev, REG_PSDRPT) >= thres) -+ ret = true; -+ -+ rtw_write32(rtwdev, REG_PSDFN, freq); -+ rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE); -+ -+ return ret; -+} -+ -+static void rtw8703b_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch) -+{ -+ if (!notch) { -+ rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f); -+ rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); -+ rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); -+ rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); -+ return; -+ } -+ -+ switch (channel) { -+ case 5: -+ fallthrough; -+ case 13: -+ rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb); -+ rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); -+ rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x06000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); -+ rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); -+ break; -+ case 6: -+ rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x4); -+ rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); -+ rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000600); -+ rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); -+ rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); -+ break; -+ case 7: -+ rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x3); -+ rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); -+ rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x06000000); -+ rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); -+ break; -+ case 8: -+ rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xa); -+ rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); -+ rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000380); -+ rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); -+ break; -+ case 14: -+ rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5); -+ rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); -+ rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); -+ rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00180000); -+ rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); -+ break; -+ default: -+ rtw_warn(rtwdev, -+ "Bug: Notch filter enable called for channel %u!", -+ channel); -+ rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); -+ rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); -+ break; -+ } -+} -+ -+static void rtw8703b_spur_cal(struct rtw_dev *rtwdev, u8 channel) -+{ -+ bool notch; -+ u32 freq; -+ -+ if (channel == 5) { -+ freq = FREQ_CH5; -+ } else if (channel == 6) { -+ freq = FREQ_CH6; -+ } else if (channel == 7) { -+ freq = FREQ_CH7; -+ } else if (channel == 8) { -+ freq = FREQ_CH8; -+ } else if (channel == 13) { -+ freq = FREQ_CH13; -+ } else if (channel == 14) { -+ freq = FREQ_CH14; -+ } else { -+ rtw8703b_cfg_notch(rtwdev, channel, false); -+ return; -+ } -+ -+ notch = rtw8703b_check_spur_ov_thres(rtwdev, freq, SPUR_THRES); -+ rtw8703b_cfg_notch(rtwdev, channel, notch); -+} -+ -+static void rtw8703b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) -+{ -+ u32 rf_cfgch_a; -+ u32 rf_cfgch_b; -+ /* default value for 20M */ -+ u32 rf_rck = 0x00000C08; -+ -+ rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); -+ rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK); -+ -+ rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK; -+ rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK; -+ rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK); -+ rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK); -+ -+ rf_cfgch_a &= ~RFCFGCH_BW_MASK; -+ switch (bw) { -+ case RTW_CHANNEL_WIDTH_20: -+ rf_cfgch_a |= RFCFGCH_BW_20M; -+ break; -+ case RTW_CHANNEL_WIDTH_40: -+ rf_cfgch_a |= RFCFGCH_BW_40M; -+ rf_rck = 0x00000C4C; -+ break; -+ default: -+ break; -+ } -+ -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a); -+ rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b); -+ -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK1, RFREG_MASK, rf_rck); -+ rtw8703b_spur_cal(rtwdev, channel); -+} -+ -+#define CCK_DFIR_NR_8703B 2 -+static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR_8703B] = { -+ [0] = { -+ { .len = 4, .reg = REG_CCK_TXSF2, .val = 0x5A7DA0BD }, -+ { .len = 4, .reg = REG_CCK_DBG, .val = 0x0000223B }, -+ }, -+ [1] = { -+ { .len = 4, .reg = REG_CCK_TXSF2, .val = 0x00000000 }, -+ { .len = 4, .reg = REG_CCK_DBG, .val = 0x00000000 }, -+ }, -+}; -+ -+static void rtw8703b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, -+ u8 primary_ch_idx) -+{ -+ const struct rtw_backup_info *cck_dfir; -+ int i; -+ -+ cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1]; -+ -+ for (i = 0; i < CCK_DFIR_NR_8703B; i++, cck_dfir++) -+ rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val); -+ -+ switch (bw) { -+ case RTW_CHANNEL_WIDTH_20: -+ rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0); -+ rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0); -+ rtw_write32_mask(rtwdev, REG_OFDM0_TX_PSD_NOISE, -+ GENMASK(31, 20), 0x0); -+ rtw_write32(rtwdev, REG_BBRX_DFIR, 0x4A880000); -+ rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x19F60000); -+ break; -+ case RTW_CHANNEL_WIDTH_40: -+ rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1); -+ rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1); -+ rtw_write32(rtwdev, REG_BBRX_DFIR, 0x40100000); -+ rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x51F60000); -+ rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND, -+ primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0); -+ rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, 0xC00, -+ primary_ch_idx == RTW_SC_20_UPPER ? 2 : 1); -+ -+ rtw_write32_mask(rtwdev, REG_BB_PWR_SAV5_11N, GENMASK(27, 26), -+ primary_ch_idx == RTW_SC_20_UPPER ? 1 : 2); -+ break; -+ default: -+ break; -+ } -+} -+ -+static void rtw8703b_set_channel(struct rtw_dev *rtwdev, u8 channel, -+ u8 bw, u8 primary_chan_idx) -+{ -+ rtw8703b_set_channel_rf(rtwdev, channel, bw); -+ rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); -+ rtw8703b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); -+} -+ -+/* Not all indices are valid, based on available data. None of the -+ * known valid values are positive, so use 0x7f as "invalid". -+ */ -+#define LNA_IDX_INVALID 0x7f -+static const s8 lna_gain_table[16] = { -+ -2, LNA_IDX_INVALID, LNA_IDX_INVALID, LNA_IDX_INVALID, -+ -6, LNA_IDX_INVALID, LNA_IDX_INVALID, -19, -+ -32, LNA_IDX_INVALID, -36, -42, -+ LNA_IDX_INVALID, LNA_IDX_INVALID, LNA_IDX_INVALID, -48, -+}; -+ -+static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx) -+{ -+ s8 lna_gain = 0; -+ -+ if (lna_idx < ARRAY_SIZE(lna_gain_table)) -+ lna_gain = lna_gain_table[lna_idx]; -+ -+ if (lna_gain >= 0) { -+ rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx); -+ return -120; -+ } -+ -+ return lna_gain - 2 * vga_idx; -+} -+ -+static void query_phy_status_cck(struct rtw_dev *rtwdev, u8 *phy_raw, -+ struct rtw_rx_pkt_stat *pkt_stat) -+{ -+ struct phy_status_8703b *phy_status = (struct phy_status_8703b *)phy_raw; -+ u8 vga_idx = phy_status->cck_agc_rpt_ofdm_cfosho_a & VGA_BITS; -+ u8 lna_idx = phy_status->cck_agc_rpt_ofdm_cfosho_a & LNA_L_BITS; -+ s8 rx_power; -+ -+ if (rtwdev->dm_info.rx_cck_agc_report_type == 1) -+ lna_idx = FIELD_PREP(BIT_LNA_H_MASK, -+ phy_status->cck_rpt_b_ofdm_cfosho_b & LNA_H_BIT) -+ | FIELD_PREP(BIT_LNA_L_MASK, lna_idx); -+ else -+ lna_idx = FIELD_PREP(BIT_LNA_L_MASK, lna_idx); -+ rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx); -+ -+ pkt_stat->rx_power[RF_PATH_A] = rx_power; -+ pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); -+ rtwdev->dm_info.rssi[RF_PATH_A] = pkt_stat->rssi; -+ pkt_stat->signal_power = rx_power; -+} -+ -+static void query_phy_status_ofdm(struct rtw_dev *rtwdev, u8 *phy_raw, -+ struct rtw_rx_pkt_stat *pkt_stat) -+{ -+ struct phy_status_8703b *phy_status = (struct phy_status_8703b *)phy_raw; -+ struct rtw_dm_info *dm_info = &rtwdev->dm_info; -+ s8 val_s8; -+ -+ val_s8 = phy_status->path_agc[RF_PATH_A].gain & 0x3F; -+ pkt_stat->rx_power[RF_PATH_A] = (val_s8 * 2) - 110; -+ pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); -+ pkt_stat->rx_snr[RF_PATH_A] = (s8)(phy_status->path_rxsnr[RF_PATH_A] / 2); -+ -+ /* signal power reported by HW */ -+ val_s8 = phy_status->cck_sig_qual_ofdm_pwdb_all >> 1; -+ pkt_stat->signal_power = (val_s8 & 0x7f) - 110; -+ -+ pkt_stat->rx_evm[RF_PATH_A] = phy_status->stream_rxevm[RF_PATH_A]; -+ pkt_stat->cfo_tail[RF_PATH_A] = phy_status->path_cfotail[RF_PATH_A]; -+ -+ dm_info->curr_rx_rate = pkt_stat->rate; -+ dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; -+ dm_info->rx_snr[RF_PATH_A] = pkt_stat->rx_snr[RF_PATH_A] >> 1; -+ /* convert to KHz (used only for debugfs) */ -+ dm_info->cfo_tail[RF_PATH_A] = (pkt_stat->cfo_tail[RF_PATH_A] * 5) >> 1; -+ -+ /* (EVM value as s8 / 2) is dbm, should usually be in -33 to 0 -+ * range. rx_evm_dbm needs the absolute (positive) value. -+ */ -+ val_s8 = (s8)pkt_stat->rx_evm[RF_PATH_A]; -+ val_s8 = clamp_t(s8, -val_s8 >> 1, 0, 64); -+ val_s8 &= 0x3F; /* 64->0: second path of 1SS rate is 64 */ -+ dm_info->rx_evm_dbm[RF_PATH_A] = val_s8; -+} -+ -+static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, -+ struct rtw_rx_pkt_stat *pkt_stat) -+{ -+ if (pkt_stat->rate <= DESC_RATE11M) -+ query_phy_status_cck(rtwdev, phy_status, pkt_stat); -+ else -+ query_phy_status_ofdm(rtwdev, phy_status, pkt_stat); -+} -+ -+static void rtw8703b_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, -+ struct rtw_rx_pkt_stat *pkt_stat, -+ struct ieee80211_rx_status *rx_status) -+{ -+ struct ieee80211_hdr *hdr; -+ u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; -+ u8 *phy_status = NULL; -+ -+ memset(pkt_stat, 0, sizeof(*pkt_stat)); -+ -+ pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); -+ pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); -+ pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); -+ pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && -+ GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; -+ pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); -+ pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); -+ pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); -+ pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); -+ pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); -+ pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); -+ pkt_stat->ppdu_cnt = 0; -+ pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); -+ -+ pkt_stat->drv_info_sz *= RX_DRV_INFO_SZ_UNIT_8703B; -+ -+ if (pkt_stat->is_c2h) -+ return; -+ -+ hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + -+ pkt_stat->drv_info_sz); -+ -+ pkt_stat->bw = GET_RX_DESC_BW(rx_desc); -+ -+ if (pkt_stat->phy_status) { -+ phy_status = rx_desc + desc_sz + pkt_stat->shift; -+ query_phy_status(rtwdev, phy_status, pkt_stat); -+ } -+ -+ rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); -+ -+ /* Rtl8723cs driver checks for size < 14 or size > 8192 and -+ * simply drops the packet. Maybe this should go into -+ * rtw_rx_fill_rx_status()? -+ */ -+ if (pkt_stat->pkt_len == 0) { -+ rx_status->flag |= RX_FLAG_NO_PSDU; -+ rtw_dbg(rtwdev, RTW_DBG_RX, "zero length packet"); -+ } -+} -+ -+#define ADDA_ON_VAL_8703B 0x03c00014 -+ -+static -+void rtw8703b_iqk_config_mac(struct rtw_dev *rtwdev, -+ const struct rtw8723x_iqk_backup_regs *backup) -+{ -+ rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[0], 0x3F); -+ for (int i = 1; i < RTW8723X_IQK_MAC8_REG_NUM; i++) -+ rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[i], -+ backup->mac8[i] & (~BIT(3))); -+} -+ -+#define IQK_LTE_WRITE_VAL_8703B 0x00007700 -+#define IQK_DELAY_TIME_8703B 4 -+ -+static void rtw8703b_iqk_one_shot(struct rtw_dev *rtwdev, bool tx) -+{ -+ u32 regval; -+ ktime_t t; -+ s64 dur; -+ int ret; -+ -+ /* enter IQK mode */ -+ rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); -+ rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8703B); -+ -+ /* One shot, LOK & IQK */ -+ rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf9000000); -+ rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000); -+ -+ t = ktime_get(); -+ msleep(IQK_DELAY_TIME_8703B); -+ ret = read_poll_timeout(rtw_read32, regval, regval != 0, 1000, -+ 100000, false, rtwdev, -+ REG_IQK_RDY); -+ dur = ktime_us_delta(ktime_get(), t); -+ -+ if (ret) -+ rtw_warn(rtwdev, "[IQK] %s timed out after %lldus!\n", -+ tx ? "TX" : "RX", dur); -+ else -+ rtw_dbg(rtwdev, RTW_DBG_RFK, -+ "[IQK] %s done after %lldus\n", -+ tx ? "TX" : "RX", dur); -+} -+ -+static void rtw8703b_iqk_txrx_path_post(struct rtw_dev *rtwdev, -+ const struct rtw8723x_iqk_backup_regs *backup) -+{ -+ rtw8723x_iqk_restore_lte_path_gnt(rtwdev, backup); -+ rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg); -+ -+ /* leave IQK mode */ -+ rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x0); -+} -+ -+static u8 rtw8703b_iqk_check_tx_failed(struct rtw_dev *rtwdev) -+{ -+ s32 tx_x, tx_y; -+ u32 tx_fail; -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n", -+ rtw_read32(rtwdev, REG_IQK_RES_RY)); -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n", -+ rtw_read32(rtwdev, REG_IQK_RES_TX), -+ rtw_read32(rtwdev, REG_IQK_RES_TY)); -+ rtw_dbg(rtwdev, RTW_DBG_RFK, -+ "[IQK] 0xe90(before IQK) = 0x%x, 0xe98(after IQK) = 0x%x\n", -+ rtw_read32(rtwdev, REG_IQK_RDY), -+ rtw_read32(rtwdev, 0xe98)); -+ -+ tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL); -+ tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); -+ tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); -+ -+ if (!tx_fail && tx_x != IQK_TX_X_ERR && tx_y != IQK_TX_Y_ERR) -+ return IQK_TX_OK; -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] A TX IQK failed\n"); -+ -+ return 0; -+} -+ -+static u8 rtw8703b_iqk_check_rx_failed(struct rtw_dev *rtwdev) -+{ -+ s32 rx_x, rx_y; -+ u32 rx_fail; -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n", -+ rtw_read32(rtwdev, REG_IQK_RES_RX), -+ rtw_read32(rtwdev, REG_IQK_RES_RY)); -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, -+ "[IQK] 0xea0(before IQK) = 0x%x, 0xea8(after IQK) = 0x%x\n", -+ rtw_read32(rtwdev, 0xea0), -+ rtw_read32(rtwdev, 0xea8)); -+ -+ rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL); -+ rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); -+ rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); -+ rx_y = abs(iqkxy_to_s32(rx_y)); -+ -+ if (!rx_fail && rx_x != IQK_RX_X_ERR && rx_y != IQK_RX_Y_ERR && -+ rx_x < IQK_RX_X_UPPER && rx_x > IQK_RX_X_LOWER && -+ rx_y < IQK_RX_Y_LMT) -+ return IQK_RX_OK; -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] A RX IQK failed\n"); -+ -+ return 0; -+} -+ -+static u8 rtw8703b_iqk_tx_path(struct rtw_dev *rtwdev, -+ const struct rtw8723x_iqk_backup_regs *backup) -+{ -+ u8 status; -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A TX IQK!\n"); -+ -+ /* IQK setting */ -+ rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); -+ rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); -+ rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c); -+ rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); -+ rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); -+ rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); -+ rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8214030f); -+ rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000); -+ rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000); -+ rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000); -+ -+ /* LO calibration setting */ -+ rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911); -+ -+ /* leave IQK mode */ -+ rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000); -+ -+ /* PA, PAD setting */ -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1); -+ rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x7); -+ rtw_write_rf(rtwdev, RF_PATH_A, 0x7f, RFREG_MASK, 0xd400); -+ -+ rtw8703b_iqk_one_shot(rtwdev, true); -+ status = rtw8703b_iqk_check_tx_failed(rtwdev); -+ -+ rtw8703b_iqk_txrx_path_post(rtwdev, backup); -+ -+ return status; -+} -+ -+static u8 rtw8703b_iqk_rx_path(struct rtw_dev *rtwdev, -+ const struct rtw8723x_iqk_backup_regs *backup) -+{ -+ u8 status; -+ u32 tx_x, tx_y; -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK step 1!\n"); -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK1 = 0x%x\n", -+ rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); -+ rtw_write32(rtwdev, REG_BB_SEL_BTG, 0x99000000); -+ -+ /* disable IQC mode */ -+ rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); -+ -+ /* IQK setting */ -+ rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); -+ rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); -+ -+ /* path IQK setting */ -+ rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c); -+ rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); -+ rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); -+ rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); -+ rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8216000f); -+ rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000); -+ rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x28110000); -+ rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000); -+ -+ /* LOK setting */ -+ rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911); -+ -+ /* RX IQK mode */ -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1); -+ rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000); -+ rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007); -+ rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0x57db7); -+ -+ rtw8703b_iqk_one_shot(rtwdev, true); -+ /* leave IQK mode */ -+ rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000); -+ status = rtw8703b_iqk_check_tx_failed(rtwdev); -+ -+ if (!status) -+ goto restore; -+ -+ /* second round */ -+ tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); -+ tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); -+ -+ rtw_write32(rtwdev, REG_TXIQK_11N, BIT_SET_TXIQK_11N(tx_x, tx_y)); -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n", -+ rtw_read32(rtwdev, REG_TXIQK_11N), -+ BIT_SET_TXIQK_11N(tx_x, tx_y)); -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK step 2!\n"); -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK 2 = 0x%x\n", -+ rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); -+ -+ /* IQK setting */ -+ rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); -+ rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c); -+ rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c); -+ rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); -+ rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); -+ rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82110000); -+ rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160c1f); -+ rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000); -+ rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000); -+ -+ /* LO calibration setting */ -+ rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1); -+ -+ /* leave IQK mode */ -+ rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000); -+ /* modify RX IQK mode table */ -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1); -+ /* RF_RCK_OS, RF_TXPA_G1, RF_TXPA_G2 */ -+ rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000); -+ rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007); -+ rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0xf7d77); -+ -+ /* PA, PAD setting */ -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1); -+ rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x5); -+ -+ rtw8703b_iqk_one_shot(rtwdev, false); -+ status |= rtw8703b_iqk_check_rx_failed(rtwdev); -+ -+restore: -+ rtw8703b_iqk_txrx_path_post(rtwdev, backup); -+ -+ return status; -+} -+ -+static -+void rtw8703b_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t, -+ const struct rtw8723x_iqk_backup_regs *backup) -+{ -+ u32 i; -+ u8 a_ok; -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, -+ "[IQK] IQ Calibration for 1T1R_S0/S1 for %d times\n", t); -+ -+ rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8703B); -+ rtw8703b_iqk_config_mac(rtwdev, backup); -+ rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf); -+ rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05600); -+ rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4); -+ rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204000); -+ -+ for (i = 0; i < PATH_IQK_RETRY; i++) { -+ a_ok = rtw8703b_iqk_tx_path(rtwdev, backup); -+ if (a_ok == IQK_TX_OK) { -+ rtw_dbg(rtwdev, RTW_DBG_RFK, -+ "[IQK] path A TX IQK success!\n"); -+ result[t][IQK_S1_TX_X] = -+ rtw_read32_mask(rtwdev, REG_IQK_RES_TX, -+ BIT_MASK_RES_TX); -+ result[t][IQK_S1_TX_Y] = -+ rtw_read32_mask(rtwdev, REG_IQK_RES_TY, -+ BIT_MASK_RES_TY); -+ break; -+ } -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A TX IQK fail!\n"); -+ result[t][IQK_S1_TX_X] = 0x100; -+ result[t][IQK_S1_TX_Y] = 0x0; -+ } -+ -+ for (i = 0; i < PATH_IQK_RETRY; i++) { -+ a_ok = rtw8703b_iqk_rx_path(rtwdev, backup); -+ if (a_ok == (IQK_TX_OK | IQK_RX_OK)) { -+ rtw_dbg(rtwdev, RTW_DBG_RFK, -+ "[IQK] path A RX IQK success!\n"); -+ result[t][IQK_S1_RX_X] = -+ rtw_read32_mask(rtwdev, REG_IQK_RES_RX, -+ BIT_MASK_RES_RX); -+ result[t][IQK_S1_RX_Y] = -+ rtw_read32_mask(rtwdev, REG_IQK_RES_RY, -+ BIT_MASK_RES_RY); -+ break; -+ } -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK fail!\n"); -+ result[t][IQK_S1_RX_X] = 0x100; -+ result[t][IQK_S1_RX_Y] = 0x0; -+ } -+ -+ if (a_ok == 0x0) -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A IQK fail!\n"); -+ -+ rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); -+ mdelay(1); -+} -+ -+static -+void rtw8703b_iqk_fill_a_matrix(struct rtw_dev *rtwdev, const s32 result[]) -+{ -+ u32 tmp_rx_iqi = 0x40000100 & GENMASK(31, 16); -+ s32 tx1_a, tx1_a_ext; -+ s32 tx1_c, tx1_c_ext; -+ s32 oldval_1; -+ s32 x, y; -+ -+ if (result[IQK_S1_TX_X] == 0) -+ return; -+ -+ oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, -+ BIT_MASK_TXIQ_ELM_D); -+ -+ x = iqkxy_to_s32(result[IQK_S1_TX_X]); -+ tx1_a = iqk_mult(x, oldval_1, &tx1_a_ext); -+ rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, -+ BIT_MASK_TXIQ_ELM_A, tx1_a); -+ rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, -+ BIT_MASK_OFDM0_EXT_A, tx1_a_ext); -+ -+ y = iqkxy_to_s32(result[IQK_S1_TX_Y]); -+ tx1_c = iqk_mult(y, oldval_1, &tx1_c_ext); -+ rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, -+ BIT_SET_TXIQ_ELM_C1(tx1_c)); -+ rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, -+ BIT_MASK_TXIQ_ELM_C, BIT_SET_TXIQ_ELM_C2(tx1_c)); -+ rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, -+ BIT_MASK_OFDM0_EXT_C, tx1_c_ext); -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, -+ "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n", -+ x, tx1_a, oldval_1); -+ rtw_dbg(rtwdev, RTW_DBG_RFK, -+ "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c); -+ -+ if (result[IQK_S1_RX_X] == 0) -+ return; -+ -+ tmp_rx_iqi |= FIELD_PREP(BIT_MASK_RXIQ_S1_X, result[IQK_S1_RX_X]); -+ tmp_rx_iqi |= FIELD_PREP(BIT_MASK_RXIQ_S1_Y1, result[IQK_S1_RX_X]); -+ rtw_write32(rtwdev, REG_A_RXIQI, tmp_rx_iqi); -+ rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2, -+ BIT_SET_RXIQ_S1_Y2(result[IQK_S1_RX_Y])); -+} -+ -+static void rtw8703b_phy_calibration(struct rtw_dev *rtwdev) -+{ -+ /* For some reason path A is called S1 and B S0 in shared -+ * rtw88 calibration data. -+ */ -+ struct rtw_dm_info *dm_info = &rtwdev->dm_info; -+ struct rtw8723x_iqk_backup_regs backup; -+ u8 final_candidate = IQK_ROUND_INVALID; -+ s32 result[IQK_ROUND_SIZE][IQK_NR]; -+ bool good; -+ u8 i, j; -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Start!\n"); -+ -+ memset(result, 0, sizeof(result)); -+ -+ rtw8723x_iqk_backup_path_ctrl(rtwdev, &backup); -+ rtw8723x_iqk_backup_lte_path_gnt(rtwdev, &backup); -+ rtw8723x_iqk_backup_regs(rtwdev, &backup); -+ -+ for (i = IQK_ROUND_0; i <= IQK_ROUND_2; i++) { -+ rtw8723x_iqk_config_path_ctrl(rtwdev); -+ rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8703B); -+ -+ rtw8703b_iqk_one_round(rtwdev, result, i, &backup); -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, -+ "[IQK] back to BB mode, load original values!\n"); -+ if (i > IQK_ROUND_0) -+ rtw8723x_iqk_restore_regs(rtwdev, &backup); -+ rtw8723x_iqk_restore_lte_path_gnt(rtwdev, &backup); -+ rtw8723x_iqk_restore_path_ctrl(rtwdev, &backup); -+ -+ for (j = IQK_ROUND_0; j < i; j++) { -+ good = rtw8723x_iqk_similarity_cmp(rtwdev, result, j, i); -+ -+ if (good) { -+ final_candidate = j; -+ rtw_dbg(rtwdev, RTW_DBG_RFK, -+ "[IQK] cmp %d:%d final_candidate is %x\n", -+ j, i, final_candidate); -+ goto iqk_done; -+ } -+ } -+ } -+ -+ if (final_candidate == IQK_ROUND_INVALID) { -+ s32 reg_tmp = 0; -+ -+ for (i = 0; i < IQK_NR; i++) -+ reg_tmp += result[IQK_ROUND_HYBRID][i]; -+ -+ if (reg_tmp != 0) { -+ final_candidate = IQK_ROUND_HYBRID; -+ } else { -+ WARN(1, "IQK failed\n"); -+ goto out; -+ } -+ } -+ -+iqk_done: -+ /* only path A is calibrated in rtl8703b */ -+ rtw8703b_iqk_fill_a_matrix(rtwdev, result[final_candidate]); -+ -+ dm_info->iqk.result.s1_x = result[final_candidate][IQK_S1_TX_X]; -+ dm_info->iqk.result.s1_y = result[final_candidate][IQK_S1_TX_Y]; -+ dm_info->iqk.result.s0_x = result[final_candidate][IQK_S0_TX_X]; -+ dm_info->iqk.result.s0_y = result[final_candidate][IQK_S0_TX_Y]; -+ dm_info->iqk.done = true; -+ -+out: -+ rtw_write32(rtwdev, REG_BB_SEL_BTG, backup.bb_sel_btg); -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] final_candidate is %x\n", -+ final_candidate); -+ -+ for (i = IQK_ROUND_0; i < IQK_ROUND_SIZE; i++) -+ rtw_dbg(rtwdev, RTW_DBG_RFK, -+ "[IQK] Result %u: rege94_s1=%x rege9c_s1=%x regea4_s1=%x regeac_s1=%x rege94_s0=%x rege9c_s0=%x regea4_s0=%x regeac_s0=%x %s\n", -+ i, -+ result[i][0], result[i][1], result[i][2], result[i][3], -+ result[i][4], result[i][5], result[i][6], result[i][7], -+ final_candidate == i ? "(final candidate)" : ""); -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, -+ "[IQK] 0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n", -+ rtw_read32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE), -+ rtw_read32(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N), -+ rtw_read32(rtwdev, REG_A_RXIQI), -+ rtw_read32(rtwdev, REG_RXIQK_MATRIX_LSB_11N)); -+ rtw_dbg(rtwdev, RTW_DBG_RFK, -+ "[IQK] 0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n", -+ rtw_read32(rtwdev, REG_TXIQ_AB_S0), -+ rtw_read32(rtwdev, REG_TXIQ_CD_S0), -+ rtw_read32(rtwdev, REG_RXIQ_AB_S0)); -+ -+ rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Finished.\n"); -+} -+ -+static void rtw8703b_set_iqk_matrix_by_result(struct rtw_dev *rtwdev, -+ u32 ofdm_swing, u8 rf_path) -+{ -+ struct rtw_dm_info *dm_info = &rtwdev->dm_info; -+ s32 ele_A, ele_D, ele_C; -+ s32 ele_A_ext, ele_C_ext, ele_D_ext; -+ s32 iqk_result_x; -+ s32 iqk_result_y; -+ s32 value32; -+ -+ switch (rf_path) { -+ default: -+ case RF_PATH_A: -+ iqk_result_x = dm_info->iqk.result.s1_x; -+ iqk_result_y = dm_info->iqk.result.s1_y; -+ break; -+ case RF_PATH_B: -+ iqk_result_x = dm_info->iqk.result.s0_x; -+ iqk_result_y = dm_info->iqk.result.s0_y; -+ break; -+ } -+ -+ /* new element D */ -+ ele_D = OFDM_SWING_D(ofdm_swing); -+ iqk_mult(iqk_result_x, ele_D, &ele_D_ext); -+ /* new element A */ -+ iqk_result_x = iqkxy_to_s32(iqk_result_x); -+ ele_A = iqk_mult(iqk_result_x, ele_D, &ele_A_ext); -+ /* new element C */ -+ iqk_result_y = iqkxy_to_s32(iqk_result_y); -+ ele_C = iqk_mult(iqk_result_y, ele_D, &ele_C_ext); -+ -+ switch (rf_path) { -+ case RF_PATH_A: -+ default: -+ /* write new elements A, C, D, and element B is always 0 */ -+ value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D); -+ rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, value32); -+ value32 = BIT_SET_TXIQ_ELM_C1(ele_C); -+ rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, -+ value32); -+ value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); -+ value32 &= ~BIT_MASK_OFDM0_EXTS; -+ value32 |= BIT_SET_OFDM0_EXTS(ele_A_ext, ele_C_ext, ele_D_ext); -+ rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); -+ break; -+ -+ case RF_PATH_B: -+ /* write new elements A, C, D, and element B is always 0 */ -+ value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D); -+ rtw_write32(rtwdev, REG_OFDM_0_XB_TX_IQ_IMBALANCE, value32); -+ value32 = BIT_SET_TXIQ_ELM_C1(ele_C); -+ rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXB_LSB2_11N, MASKH4BITS, -+ value32); -+ value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); -+ value32 &= ~BIT_MASK_OFDM0_EXTS_B; -+ value32 |= BIT_SET_OFDM0_EXTS_B(ele_A_ext, ele_C_ext, ele_D_ext); -+ rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); -+ break; -+ } -+} -+ -+static void rtw8703b_set_iqk_matrix(struct rtw_dev *rtwdev, s8 ofdm_index, -+ u8 rf_path) -+{ -+ struct rtw_dm_info *dm_info = &rtwdev->dm_info; -+ s32 value32; -+ u32 ofdm_swing; -+ -+ ofdm_index = clamp_t(s8, ofdm_index, 0, RTW_OFDM_SWING_TABLE_SIZE - 1); -+ -+ ofdm_swing = rtw8703b_ofdm_swing_table[ofdm_index]; -+ -+ if (dm_info->iqk.done) { -+ rtw8703b_set_iqk_matrix_by_result(rtwdev, ofdm_swing, rf_path); -+ return; -+ } -+ -+ switch (rf_path) { -+ case RF_PATH_A: -+ default: -+ rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, ofdm_swing); -+ rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, -+ 0x00); -+ -+ value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); -+ value32 &= ~BIT_MASK_OFDM0_EXTS; -+ rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); -+ break; -+ -+ case RF_PATH_B: -+ rtw_write32(rtwdev, REG_OFDM_0_XB_TX_IQ_IMBALANCE, ofdm_swing); -+ rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXB_LSB2_11N, MASKH4BITS, -+ 0x00); -+ -+ value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); -+ value32 &= ~BIT_MASK_OFDM0_EXTS_B; -+ rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); -+ break; -+ } -+} -+ -+static void rtw8703b_pwrtrack_set_ofdm_pwr(struct rtw_dev *rtwdev, s8 swing_idx, -+ s8 txagc_idx) -+{ -+ struct rtw_dm_info *dm_info = &rtwdev->dm_info; -+ -+ dm_info->txagc_remnant_ofdm = txagc_idx; -+ -+ /* Only path A is calibrated for rtl8703b */ -+ rtw8703b_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_A); -+} -+ -+static void rtw8703b_pwrtrack_set_cck_pwr(struct rtw_dev *rtwdev, s8 swing_idx, -+ s8 txagc_idx) -+{ -+ struct rtw_dm_info *dm_info = &rtwdev->dm_info; -+ -+ dm_info->txagc_remnant_cck = txagc_idx; -+ -+ swing_idx = clamp_t(s8, swing_idx, 0, RTW_CCK_SWING_TABLE_SIZE - 1); -+ -+ BUILD_BUG_ON(ARRAY_SIZE(rtw8703b_cck_pwr_regs) -+ != ARRAY_SIZE(rtw8703b_cck_swing_table[0])); -+ -+ for (int i = 0; i < ARRAY_SIZE(rtw8703b_cck_pwr_regs); i++) -+ rtw_write8(rtwdev, rtw8703b_cck_pwr_regs[i], -+ rtw8703b_cck_swing_table[swing_idx][i]); -+} -+ -+static void rtw8703b_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) -+{ -+ struct rtw_dm_info *dm_info = &rtwdev->dm_info; -+ struct rtw_hal *hal = &rtwdev->hal; -+ u8 limit_ofdm; -+ u8 limit_cck = 21; -+ s8 final_ofdm_swing_index; -+ s8 final_cck_swing_index; -+ -+ limit_ofdm = rtw8723x_pwrtrack_get_limit_ofdm(rtwdev); -+ -+ final_ofdm_swing_index = dm_info->default_ofdm_index + -+ dm_info->delta_power_index[path]; -+ final_cck_swing_index = dm_info->default_cck_index + -+ dm_info->delta_power_index[path]; -+ -+ if (final_ofdm_swing_index > limit_ofdm) -+ rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, limit_ofdm, -+ final_ofdm_swing_index - limit_ofdm); -+ else if (final_ofdm_swing_index < 0) -+ rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, 0, -+ final_ofdm_swing_index); -+ else -+ rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0); -+ -+ if (final_cck_swing_index > limit_cck) -+ rtw8703b_pwrtrack_set_cck_pwr(rtwdev, limit_cck, -+ final_cck_swing_index - limit_cck); -+ else if (final_cck_swing_index < 0) -+ rtw8703b_pwrtrack_set_cck_pwr(rtwdev, 0, -+ final_cck_swing_index); -+ else -+ rtw8703b_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0); -+ -+ rtw_phy_set_tx_power_level(rtwdev, hal->current_channel); -+} -+ -+static void rtw8703b_phy_pwrtrack(struct rtw_dev *rtwdev) -+{ -+ struct rtw_dm_info *dm_info = &rtwdev->dm_info; -+ struct rtw_swing_table swing_table; -+ u8 thermal_value, delta, path; -+ bool do_iqk = false; -+ -+ rtw_phy_config_swing_table(rtwdev, &swing_table); -+ -+ if (rtwdev->efuse.thermal_meter[0] == 0xff) -+ return; -+ -+ thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); -+ -+ rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); -+ -+ do_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev); -+ -+ if (do_iqk) -+ rtw8723x_lck(rtwdev); -+ -+ if (dm_info->pwr_trk_init_trigger) -+ dm_info->pwr_trk_init_trigger = false; -+ else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, -+ RF_PATH_A)) -+ goto iqk; -+ -+ delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); -+ -+ delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); -+ -+ for (path = 0; path < rtwdev->hal.rf_path_num; path++) { -+ s8 delta_cur, delta_last; -+ -+ delta_last = dm_info->delta_power_index[path]; -+ delta_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, -+ path, RF_PATH_A, delta); -+ if (delta_last == delta_cur) -+ continue; -+ -+ dm_info->delta_power_index[path] = delta_cur; -+ rtw8703b_pwrtrack_set(rtwdev, path); -+ } -+ -+ rtw8723x_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta); -+ -+iqk: -+ if (do_iqk) -+ rtw8703b_phy_calibration(rtwdev); -+} -+ -+static void rtw8703b_pwr_track(struct rtw_dev *rtwdev) -+{ -+ struct rtw_efuse *efuse = &rtwdev->efuse; -+ struct rtw_dm_info *dm_info = &rtwdev->dm_info; -+ -+ if (efuse->power_track_type != 0) { -+ rtw_warn(rtwdev, "unsupported power track type"); -+ return; -+ } -+ -+ if (!dm_info->pwr_trk_triggered) { -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, -+ GENMASK(17, 16), 0x03); -+ dm_info->pwr_trk_triggered = true; -+ return; -+ } -+ -+ rtw8703b_phy_pwrtrack(rtwdev); -+ dm_info->pwr_trk_triggered = false; -+} -+ -+static void rtw8703b_coex_set_gnt_fix(struct rtw_dev *rtwdev) -+{ -+} -+ -+static void rtw8703b_coex_set_gnt_debug(struct rtw_dev *rtwdev) -+{ -+} -+ -+static void rtw8703b_coex_set_rfe_type(struct rtw_dev *rtwdev) -+{ -+ struct rtw_coex *coex = &rtwdev->coex; -+ struct rtw_coex_rfe *coex_rfe = &coex->rfe; -+ -+ coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; -+ coex_rfe->ant_switch_polarity = 0; -+ coex_rfe->ant_switch_exist = false; -+ coex_rfe->ant_switch_with_bt = false; -+ coex_rfe->ant_switch_diversity = false; -+ coex_rfe->wlg_at_btg = true; -+ -+ /* disable LTE coex on wifi side */ -+ rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); -+ rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); -+ rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); -+} -+ -+static void rtw8703b_coex_set_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) -+{ -+} -+ -+static void rtw8703b_coex_set_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) -+{ -+} -+ -+static const u8 rtw8703b_pwrtrk_2gb_n[] = { -+ 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, -+ 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 -+}; -+ -+static const u8 rtw8703b_pwrtrk_2gb_p[] = { -+ 0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, -+ 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15 -+}; -+ -+static const u8 rtw8703b_pwrtrk_2ga_n[] = { -+ 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, -+ 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 -+}; -+ -+static const u8 rtw8703b_pwrtrk_2ga_p[] = { -+ 0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, -+ 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15 -+}; -+ -+static const u8 rtw8703b_pwrtrk_2g_cck_b_n[] = { -+ 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, -+ 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 -+}; -+ -+static const u8 rtw8703b_pwrtrk_2g_cck_b_p[] = { -+ 0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, -+ 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13 -+}; -+ -+static const u8 rtw8703b_pwrtrk_2g_cck_a_n[] = { -+ 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, -+ 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 -+}; -+ -+static const u8 rtw8703b_pwrtrk_2g_cck_a_p[] = { -+ 0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, -+ 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13 -+}; -+ -+static const s8 rtw8703b_pwrtrk_xtal_n[] = { -+ 0, 0, 0, -1, -1, -1, -1, -2, -2, -2, -3, -3, -3, -3, -3, -+ -4, -2, -2, -1, -1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1 -+}; -+ -+static const s8 rtw8703b_pwrtrk_xtal_p[] = { -+ 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 1, 0, -1, -1, -1, -+ -2, -3, -7, -9, -10, -11, -14, -16, -18, -20, -22, -24, -26, -28, -30 -+}; -+ -+static const struct rtw_pwr_track_tbl rtw8703b_rtw_pwr_track_tbl = { -+ .pwrtrk_2gb_n = rtw8703b_pwrtrk_2gb_n, -+ .pwrtrk_2gb_p = rtw8703b_pwrtrk_2gb_p, -+ .pwrtrk_2ga_n = rtw8703b_pwrtrk_2ga_n, -+ .pwrtrk_2ga_p = rtw8703b_pwrtrk_2ga_p, -+ .pwrtrk_2g_cckb_n = rtw8703b_pwrtrk_2g_cck_b_n, -+ .pwrtrk_2g_cckb_p = rtw8703b_pwrtrk_2g_cck_b_p, -+ .pwrtrk_2g_ccka_n = rtw8703b_pwrtrk_2g_cck_a_n, -+ .pwrtrk_2g_ccka_p = rtw8703b_pwrtrk_2g_cck_a_p, -+ .pwrtrk_xtal_n = rtw8703b_pwrtrk_xtal_n, -+ .pwrtrk_xtal_p = rtw8703b_pwrtrk_xtal_p, -+}; -+ -+/* Shared-Antenna Coex Table */ -+static const struct coex_table_para table_sant_8703b[] = { -+ {0xffffffff, 0xffffffff}, /* case-0 */ -+ {0x55555555, 0x55555555}, -+ {0x66555555, 0x66555555}, -+ {0xaaaaaaaa, 0xaaaaaaaa}, -+ {0x5a5a5a5a, 0x5a5a5a5a}, -+ {0xfafafafa, 0xfafafafa}, /* case-5 */ -+ {0x6a5a5555, 0xaaaaaaaa}, -+ {0x6a5a56aa, 0x6a5a56aa}, -+ {0x6a5a5a5a, 0x6a5a5a5a}, -+ {0x66555555, 0x5a5a5a5a}, -+ {0x66555555, 0x6a5a5a5a}, /* case-10 */ -+ {0x66555555, 0x6a5a5aaa}, -+ {0x66555555, 0x5a5a5aaa}, -+ {0x66555555, 0x6aaa5aaa}, -+ {0x66555555, 0xaaaa5aaa}, -+ {0x66555555, 0xaaaaaaaa}, /* case-15 */ -+ {0xffff55ff, 0xfafafafa}, -+ {0xffff55ff, 0x6afa5afa}, -+ {0xaaffffaa, 0xfafafafa}, -+ {0xaa5555aa, 0x5a5a5a5a}, -+ {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ -+ {0xaa5555aa, 0xaaaaaaaa}, -+ {0xffffffff, 0x5a5a5a5a}, -+ {0xffffffff, 0x5a5a5a5a}, -+ {0xffffffff, 0x55555555}, -+ {0xffffffff, 0x5a5a5aaa}, /* case-25 */ -+ {0x55555555, 0x5a5a5a5a}, -+ {0x55555555, 0xaaaaaaaa}, -+ {0x55555555, 0x6a5a6a5a}, -+ {0x66556655, 0x66556655}, -+ {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ -+ {0xffffffff, 0x5aaa5aaa}, -+ {0x56555555, 0x5a5a5aaa}, -+}; -+ -+/* Shared-Antenna TDMA */ -+static const struct coex_tdma_para tdma_sant_8703b[] = { -+ { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ -+ { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ -+ { {0x61, 0x3a, 0x03, 0x11, 0x11} }, -+ { {0x61, 0x30, 0x03, 0x11, 0x11} }, -+ { {0x61, 0x20, 0x03, 0x11, 0x11} }, -+ { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ -+ { {0x61, 0x45, 0x03, 0x11, 0x10} }, -+ { {0x61, 0x3a, 0x03, 0x11, 0x10} }, -+ { {0x61, 0x30, 0x03, 0x11, 0x10} }, -+ { {0x61, 0x20, 0x03, 0x11, 0x10} }, -+ { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ -+ { {0x61, 0x08, 0x03, 0x11, 0x14} }, -+ { {0x61, 0x08, 0x03, 0x10, 0x14} }, -+ { {0x51, 0x08, 0x03, 0x10, 0x54} }, -+ { {0x51, 0x08, 0x03, 0x10, 0x55} }, -+ { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ -+ { {0x51, 0x45, 0x03, 0x10, 0x50} }, -+ { {0x51, 0x3a, 0x03, 0x10, 0x50} }, -+ { {0x51, 0x30, 0x03, 0x10, 0x50} }, -+ { {0x51, 0x20, 0x03, 0x10, 0x50} }, -+ { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ -+ { {0x51, 0x4a, 0x03, 0x10, 0x50} }, -+ { {0x51, 0x0c, 0x03, 0x10, 0x54} }, -+ { {0x55, 0x08, 0x03, 0x10, 0x54} }, -+ { {0x65, 0x10, 0x03, 0x11, 0x10} }, -+ { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ -+ { {0x51, 0x08, 0x03, 0x10, 0x50} }, -+ { {0x61, 0x08, 0x03, 0x11, 0x11} }, -+}; -+ -+static struct rtw_chip_ops rtw8703b_ops = { -+ .mac_init = rtw8723x_mac_init, -+ .dump_fw_crash = NULL, -+ .shutdown = NULL, -+ .read_efuse = rtw8703b_read_efuse, -+ .phy_set_param = rtw8703b_phy_set_param, -+ .set_channel = rtw8703b_set_channel, -+ .query_rx_desc = rtw8703b_query_rx_desc, -+ .read_rf = rtw_phy_read_rf_sipi, -+ .write_rf = rtw_phy_write_rf_reg_sipi, -+ .set_tx_power_index = rtw8723x_set_tx_power_index, -+ .set_antenna = NULL, -+ .cfg_ldo25 = rtw8723x_cfg_ldo25, -+ .efuse_grant = rtw8723x_efuse_grant, -+ .false_alarm_statistics = rtw8723x_false_alarm_statistics, -+ .phy_calibration = rtw8703b_phy_calibration, -+ .dpk_track = NULL, -+ /* 8723d uses REG_CSRATIO to set dm_info.cck_pd_default, which -+ * is used in its cck_pd_set function. According to comments -+ * in the vendor driver code it doesn't exist in this chip -+ * generation, only 0xa0a ("ODM_CCK_PD_THRESH", which is only -+ * *written* to). -+ */ -+ .cck_pd_set = NULL, -+ .pwr_track = rtw8703b_pwr_track, -+ .config_bfee = NULL, -+ .set_gid_table = NULL, -+ .cfg_csi_rate = NULL, -+ .adaptivity_init = NULL, -+ .adaptivity = NULL, -+ .cfo_init = NULL, -+ .cfo_track = NULL, -+ .config_tx_path = NULL, -+ .config_txrx_mode = NULL, -+ .fill_txdesc_checksum = rtw8723x_fill_txdesc_checksum, -+ -+ /* for coex */ -+ .coex_set_init = rtw8723x_coex_cfg_init, -+ .coex_set_ant_switch = NULL, -+ .coex_set_gnt_fix = rtw8703b_coex_set_gnt_fix, -+ .coex_set_gnt_debug = rtw8703b_coex_set_gnt_debug, -+ .coex_set_rfe_type = rtw8703b_coex_set_rfe_type, -+ .coex_set_wl_tx_power = rtw8703b_coex_set_wl_tx_power, -+ .coex_set_wl_rx_gain = rtw8703b_coex_set_wl_rx_gain, -+}; -+ -+const struct rtw_chip_info rtw8703b_hw_spec = { -+ .ops = &rtw8703b_ops, -+ .id = RTW_CHIP_TYPE_8703B, -+ -+ .fw_name = "rtw88/rtw8703b_fw.bin", -+ .wlan_cpu = RTW_WCPU_11N, -+ .tx_pkt_desc_sz = 40, -+ .tx_buf_desc_sz = 16, -+ .rx_pkt_desc_sz = 24, -+ .rx_buf_desc_sz = 8, -+ .phy_efuse_size = 256, -+ .log_efuse_size = 512, -+ .ptct_efuse_size = 15, -+ .txff_size = 32768, -+ .rxff_size = 16384, -+ .rsvd_drv_pg_num = 8, -+ .band = RTW_BAND_2G, -+ .page_size = TX_PAGE_SIZE, -+ .csi_buf_pg_num = 0, -+ .dig_min = 0x20, -+ .txgi_factor = 1, -+ .is_pwr_by_rate_dec = true, -+ .rx_ldpc = false, -+ .tx_stbc = false, -+ .max_power_index = 0x3f, -+ .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, -+ -+ .path_div_supported = false, -+ .ht_supported = true, -+ .vht_supported = false, -+ .lps_deep_mode_supported = 0, -+ -+ .sys_func_en = 0xFD, -+ .pwr_on_seq = card_enable_flow_8703b, -+ .pwr_off_seq = card_disable_flow_8703b, -+ .rqpn_table = rqpn_table_8703b, -+ .prioq_addrs = &rtw8723x_common.prioq_addrs, -+ .page_table = page_table_8703b, -+ /* used only in pci.c, not needed for SDIO devices */ -+ .intf_table = NULL, -+ -+ .dig = rtw8723x_common.dig, -+ .dig_cck = rtw8723x_common.dig_cck, -+ -+ .rf_sipi_addr = {0x840, 0x844}, -+ .rf_sipi_read_addr = rtw8723x_common.rf_sipi_addr, -+ .fix_rf_phy_num = 2, -+ .ltecoex_addr = &rtw8723x_common.ltecoex_addr, -+ -+ .mac_tbl = &rtw8703b_mac_tbl, -+ .agc_tbl = &rtw8703b_agc_tbl, -+ .bb_tbl = &rtw8703b_bb_tbl, -+ .rf_tbl = {&rtw8703b_rf_a_tbl}, -+ -+ .rfe_defs = rtw8703b_rfe_defs, -+ .rfe_defs_size = ARRAY_SIZE(rtw8703b_rfe_defs), -+ -+ .iqk_threshold = 8, -+ .pwr_track_tbl = &rtw8703b_rtw_pwr_track_tbl, -+ -+ /* WOWLAN firmware exists, but not implemented yet */ -+ .wow_fw_name = "rtw88/rtw8703b_wow_fw.bin", -+ .wowlan_stub = NULL, -+ .max_scan_ie_len = IEEE80211_MAX_DATA_LEN, -+ -+ /* Vendor driver has a time-based format, converted from -+ * 20180330 -+ */ -+ .coex_para_ver = 0x0133ed6a, -+ .bt_desired_ver = 0x1c, -+ .scbd_support = true, -+ .new_scbd10_def = true, -+ .ble_hid_profile_support = false, -+ .wl_mimo_ps_support = false, -+ .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, -+ .bt_rssi_type = COEX_BTRSSI_RATIO, -+ .ant_isolation = 15, -+ .rssi_tolerance = 2, -+ .bt_rssi_step = bt_rssi_step_8703b, -+ .wl_rssi_step = wl_rssi_step_8703b, -+ /* sant -> shared antenna, nsant -> non-shared antenna -+ * Not sure if 8703b versions with non-shard antenna even exist. -+ */ -+ .table_sant_num = ARRAY_SIZE(table_sant_8703b), -+ .table_sant = table_sant_8703b, -+ .table_nsant_num = 0, -+ .table_nsant = NULL, -+ .tdma_sant_num = ARRAY_SIZE(tdma_sant_8703b), -+ .tdma_sant = tdma_sant_8703b, -+ .tdma_nsant_num = 0, -+ .tdma_nsant = NULL, -+ .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8703b), -+ .wl_rf_para_tx = rf_para_tx_8703b, -+ .wl_rf_para_rx = rf_para_rx_8703b, -+ .bt_afh_span_bw20 = 0x20, -+ .bt_afh_span_bw40 = 0x30, -+ .afh_5g_num = ARRAY_SIZE(afh_5g_8703b), -+ .afh_5g = afh_5g_8703b, -+ /* REG_BTG_SEL doesn't seem to have a counterpart in the -+ * vendor driver. Mathematically it's REG_PAD_CTRL1 + 3. -+ * -+ * It is used in the cardemu_to_act power sequence by though -+ * (by address, 0x0067), comment: "0x67[0] = 0 to disable -+ * BT_GPS_SEL pins" That seems to fit. -+ */ -+ .btg_reg = NULL, -+ /* These registers are used to read (and print) from if -+ * CONFIG_RTW88_DEBUGFS is enabled. -+ */ -+ .coex_info_hw_regs_num = 0, -+ .coex_info_hw_regs = NULL, -+}; -+EXPORT_SYMBOL(rtw8703b_hw_spec); -+ -+MODULE_FIRMWARE("rtw88/rtw8703b_fw.bin"); -+MODULE_FIRMWARE("rtw88/rtw8703b_wow_fw.bin"); -+ -+MODULE_AUTHOR("Fiona Klute "); -+MODULE_DESCRIPTION("Realtek 802.11n wireless 8703b driver"); -+MODULE_LICENSE("Dual BSD/GPL"); diff --git a/packages/linux/patches/rtlwifi/6.11.2/0001-6.11.2-wifi-rtw88-8703b-Fix-reported-RX-band-width.patch b/packages/linux/patches/rtlwifi/6.11.2/0001-6.11.2-wifi-rtw88-8703b-Fix-reported-RX-band-width.patch deleted file mode 100644 index e369a89285..0000000000 --- a/packages/linux/patches/rtlwifi/6.11.2/0001-6.11.2-wifi-rtw88-8703b-Fix-reported-RX-band-width.patch +++ /dev/null @@ -1,36 +0,0 @@ -From aefa7a3a7cbe6c7de08fd7a7447c797a97c2e0cf Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Tue, 23 Jul 2024 22:32:59 +0300 -Subject: [PATCH 2/7] wifi: rtw88: 8703b: Fix reported RX band width - -The definition of GET_RX_DESC_BW is incorrect. Fix it according to the -GET_RX_STATUS_DESC_BW_8703B macro from the official driver. - -Tested only with RTL8812AU, which uses the same bits. - -Cc: stable@vger.kernel.org -Fixes: 9bb762b3a957 ("wifi: rtw88: Add definitions for 8703b chip") -Signed-off-by: Bitterblue Smith -Tested-by: Fiona Klute -Signed-off-by: Ping-Ke Shih -Link: https://patch.msgid.link/1cfed9d5-4304-4b96-84c5-c347f59fedb9@gmail.com ---- - drivers/net/wireless/realtek/rtw88/rx.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/net/wireless/realtek/rtw88/rx.h b/drivers/net/wireless/realtek/rtw88/rx.h -index d3668c4efc24..8a072dd3d73c 100644 ---- a/drivers/net/wireless/realtek/rtw88/rx.h -+++ b/drivers/net/wireless/realtek/rtw88/rx.h -@@ -41,7 +41,7 @@ enum rtw_rx_desc_enc { - #define GET_RX_DESC_TSFL(rxdesc) \ - le32_get_bits(*((__le32 *)(rxdesc) + 0x05), GENMASK(31, 0)) - #define GET_RX_DESC_BW(rxdesc) \ -- (le32_get_bits(*((__le32 *)(rxdesc) + 0x04), GENMASK(31, 24))) -+ (le32_get_bits(*((__le32 *)(rxdesc) + 0x04), GENMASK(5, 4))) - - void rtw_rx_stats(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, - struct sk_buff *skb); --- -2.43.0 - diff --git a/packages/linux/patches/rtlwifi/6.11/0001-6.11-wifi-rtlwifi-rtl8192d-Use-rtl92d-prefix.patch b/packages/linux/patches/rtlwifi/6.11/0001-6.11-wifi-rtlwifi-rtl8192d-Use-rtl92d-prefix.patch deleted file mode 100644 index 61b4429d20..0000000000 --- a/packages/linux/patches/rtlwifi/6.11/0001-6.11-wifi-rtlwifi-rtl8192d-Use-rtl92d-prefix.patch +++ /dev/null @@ -1,701 +0,0 @@ -From dec5fc45e4b69ac5c4c628fa9e482199d6e5ad71 Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 23 May 2024 17:43:37 +0300 -Subject: [PATCH 01/12] 6.11: wifi: rtlwifi: rtl8192d: Use "rtl92d" - prefix - -Some functions moved from rtl8192de still use the "rtl92de" prefix. -Rename them. - -Signed-off-by: Bitterblue Smith ---- - .../realtek/rtlwifi/rtl8192d/hw_common.c | 94 +++++++++---------- - .../realtek/rtlwifi/rtl8192d/hw_common.h | 28 +++--- - .../realtek/rtlwifi/rtl8192d/trx_common.c | 92 +++++++++--------- - .../realtek/rtlwifi/rtl8192d/trx_common.h | 16 ++-- - .../wireless/realtek/rtlwifi/rtl8192de/hw.c | 18 ++-- - .../wireless/realtek/rtlwifi/rtl8192de/sw.c | 20 ++-- - .../wireless/realtek/rtlwifi/rtl8192de/trx.c | 2 +- - 7 files changed, 135 insertions(+), 135 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c -index 920bfb4eaaef..3b14eec08b64 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c -@@ -14,7 +14,7 @@ - #include "hw_common.h" - #include "phy_common.h" - --void rtl92de_stop_tx_beacon(struct ieee80211_hw *hw) -+void rtl92d_stop_tx_beacon(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - u8 tmp1byte; -@@ -27,9 +27,9 @@ void rtl92de_stop_tx_beacon(struct ieee80211_hw *hw) - tmp1byte &= ~(BIT(0)); - rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); - } --EXPORT_SYMBOL_GPL(rtl92de_stop_tx_beacon); -+EXPORT_SYMBOL_GPL(rtl92d_stop_tx_beacon); - --void rtl92de_resume_tx_beacon(struct ieee80211_hw *hw) -+void rtl92d_resume_tx_beacon(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - u8 tmp1byte; -@@ -42,7 +42,7 @@ void rtl92de_resume_tx_beacon(struct ieee80211_hw *hw) - tmp1byte |= BIT(0); - rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte); - } --EXPORT_SYMBOL_GPL(rtl92de_resume_tx_beacon); -+EXPORT_SYMBOL_GPL(rtl92d_resume_tx_beacon); - - void rtl92d_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) - { -@@ -285,7 +285,7 @@ void rtl92d_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) - } - EXPORT_SYMBOL_GPL(rtl92d_set_hw_reg); - --bool rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) -+bool rtl92d_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - bool status = true; -@@ -307,9 +307,9 @@ bool rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data) - } while (++count); - return status; - } --EXPORT_SYMBOL_GPL(rtl92de_llt_write); -+EXPORT_SYMBOL_GPL(rtl92d_llt_write); - --void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw) -+void rtl92d_enable_hw_security_config(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - u8 sec_reg_value; -@@ -334,16 +334,16 @@ void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw) - "The SECR-value %x\n", sec_reg_value); - rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); - } --EXPORT_SYMBOL_GPL(rtl92de_enable_hw_security_config); -+EXPORT_SYMBOL_GPL(rtl92d_enable_hw_security_config); - - /* don't set REG_EDCA_BE_PARAM here because - * mac80211 will send pkt when scan - */ --void rtl92de_set_qos(struct ieee80211_hw *hw, int aci) -+void rtl92d_set_qos(struct ieee80211_hw *hw, int aci) - { - rtl92d_dm_init_edca_turbo(hw); - } --EXPORT_SYMBOL_GPL(rtl92de_set_qos); -+EXPORT_SYMBOL_GPL(rtl92d_set_qos); - - static enum version_8192d _rtl92d_read_chip_version(struct ieee80211_hw *hw) - { -@@ -362,8 +362,8 @@ static enum version_8192d _rtl92d_read_chip_version(struct ieee80211_hw *hw) - return version; - } - --static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo, -- u8 *efuse, bool autoloadfail) -+static void _rtl92d_readpowervalue_fromprom(struct txpower_info *pwrinfo, -+ u8 *efuse, bool autoloadfail) - { - u32 rfpath, eeaddr, group, offset, offset1, offset2; - u8 i, val8; -@@ -500,8 +500,8 @@ static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo, - } - } - --static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw, -- bool autoload_fail, u8 *hwinfo) -+static void _rtl92d_read_txpower_info(struct ieee80211_hw *hw, -+ bool autoload_fail, u8 *hwinfo) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -@@ -509,7 +509,7 @@ static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw, - u8 tempval[2], i, pwr, diff; - u32 ch, rfpath, group; - -- _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail); -+ _rtl92d_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail); - if (!autoload_fail) { - /* bit0~2 */ - rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7); -@@ -613,8 +613,8 @@ static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw, - } - } - --static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw, -- u8 *content) -+static void _rtl92d_read_macphymode_from_prom(struct ieee80211_hw *hw, -+ u8 *content) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -@@ -636,15 +636,15 @@ static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw, - } - } - --static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw, -- u8 *content) -+static void _rtl92d_read_macphymode_and_bandtype(struct ieee80211_hw *hw, -+ u8 *content) - { -- _rtl92de_read_macphymode_from_prom(hw, content); -+ _rtl92d_read_macphymode_from_prom(hw, content); - rtl92d_phy_config_macphymode(hw); - rtl92d_phy_config_macphymode_info(hw); - } - --static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) -+static void _rtl92d_efuse_update_chip_version(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - enum version_8192d chipver = rtlpriv->rtlhal.version; -@@ -676,7 +676,7 @@ static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) - rtlpriv->rtlhal.version = chipver; - } - --static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) -+static void _rtl92d_read_adapter_info(struct ieee80211_hw *hw) - { - static const int params_pci[] = { - RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID, -@@ -706,8 +706,8 @@ static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) - if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) - goto exit; - -- _rtl92de_efuse_update_chip_version(hw); -- _rtl92de_read_macphymode_and_bandtype(hw, hwinfo); -+ _rtl92d_efuse_update_chip_version(hw); -+ _rtl92d_read_macphymode_and_bandtype(hw, hwinfo); - - /* Read Permanent MAC address for 2nd interface */ - if (rtlhal->interfaceindex != 0) -@@ -717,7 +717,7 @@ static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) - rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, - rtlefuse->dev_addr); - rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); -- _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo); -+ _rtl92d_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo); - - /* Read Channel Plan */ - switch (rtlhal->bandset) { -@@ -739,7 +739,7 @@ static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw) - kfree(hwinfo); - } - --void rtl92de_read_eeprom_info(struct ieee80211_hw *hw) -+void rtl92d_read_eeprom_info(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); -@@ -760,15 +760,15 @@ void rtl92de_read_eeprom_info(struct ieee80211_hw *hw) - rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); - - rtlefuse->autoload_failflag = false; -- _rtl92de_read_adapter_info(hw); -+ _rtl92d_read_adapter_info(hw); - } else { - pr_err("Autoload ERR!!\n"); - } - } --EXPORT_SYMBOL_GPL(rtl92de_read_eeprom_info); -+EXPORT_SYMBOL_GPL(rtl92d_read_eeprom_info); - --static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw, -- struct ieee80211_sta *sta) -+static void rtl92d_update_hal_rate_table(struct ieee80211_hw *hw, -+ struct ieee80211_sta *sta) - { - struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); - struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -@@ -851,9 +851,9 @@ static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw, - rtl_read_dword(rtlpriv, REG_ARFR0)); - } - --static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, -- struct ieee80211_sta *sta, -- u8 rssi_level, bool update_bw) -+static void rtl92d_update_hal_rate_mask(struct ieee80211_hw *hw, -+ struct ieee80211_sta *sta, -+ u8 rssi_level, bool update_bw) - { - struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); - struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -@@ -1009,20 +1009,20 @@ static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw, - sta_entry->ratr_index = ratr_index; - } - --void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw, -- struct ieee80211_sta *sta, -- u8 rssi_level, bool update_bw) -+void rtl92d_update_hal_rate_tbl(struct ieee80211_hw *hw, -+ struct ieee80211_sta *sta, -+ u8 rssi_level, bool update_bw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - - if (rtlpriv->dm.useramask) -- rtl92de_update_hal_rate_mask(hw, sta, rssi_level, update_bw); -+ rtl92d_update_hal_rate_mask(hw, sta, rssi_level, update_bw); - else -- rtl92de_update_hal_rate_table(hw, sta); -+ rtl92d_update_hal_rate_table(hw, sta); - } --EXPORT_SYMBOL_GPL(rtl92de_update_hal_rate_tbl); -+EXPORT_SYMBOL_GPL(rtl92d_update_hal_rate_tbl); - --void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw) -+void rtl92d_update_channel_access_setting(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -@@ -1036,9 +1036,9 @@ void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw) - sifs_timer = 0x1010; - rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); - } --EXPORT_SYMBOL_GPL(rtl92de_update_channel_access_setting); -+EXPORT_SYMBOL_GPL(rtl92d_update_channel_access_setting); - --bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) -+bool rtl92d_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); -@@ -1093,11 +1093,11 @@ bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid) - *valid = 1; - return !ppsc->hwradiooff; - } --EXPORT_SYMBOL_GPL(rtl92de_gpio_radio_on_off_checking); -+EXPORT_SYMBOL_GPL(rtl92d_gpio_radio_on_off_checking); - --void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, -- u8 *p_macaddr, bool is_group, u8 enc_algo, -- bool is_wepkey, bool clear_all) -+void rtl92d_set_key(struct ieee80211_hw *hw, u32 key_index, -+ u8 *p_macaddr, bool is_group, u8 enc_algo, -+ bool is_wepkey, bool clear_all) - { - static const u8 cam_const_addr[4][6] = { - {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, -@@ -1222,4 +1222,4 @@ void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, - } - } - } --EXPORT_SYMBOL_GPL(rtl92de_set_key); -+EXPORT_SYMBOL_GPL(rtl92d_set_key); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.h -index 2c07f5cc5766..4da1bab15f36 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.h -@@ -4,21 +4,21 @@ - #ifndef __RTL92D_HW_COMMON_H__ - #define __RTL92D_HW_COMMON_H__ - --void rtl92de_stop_tx_beacon(struct ieee80211_hw *hw); --void rtl92de_resume_tx_beacon(struct ieee80211_hw *hw); -+void rtl92d_stop_tx_beacon(struct ieee80211_hw *hw); -+void rtl92d_resume_tx_beacon(struct ieee80211_hw *hw); - void rtl92d_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); - void rtl92d_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); --bool rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data); --void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw); --void rtl92de_set_qos(struct ieee80211_hw *hw, int aci); --void rtl92de_read_eeprom_info(struct ieee80211_hw *hw); --void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw, -- struct ieee80211_sta *sta, -- u8 rssi_level, bool update_bw); --void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw); --bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid); --void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index, -- u8 *p_macaddr, bool is_group, u8 enc_algo, -- bool is_wepkey, bool clear_all); -+bool rtl92d_llt_write(struct ieee80211_hw *hw, u32 address, u32 data); -+void rtl92d_enable_hw_security_config(struct ieee80211_hw *hw); -+void rtl92d_set_qos(struct ieee80211_hw *hw, int aci); -+void rtl92d_read_eeprom_info(struct ieee80211_hw *hw); -+void rtl92d_update_hal_rate_tbl(struct ieee80211_hw *hw, -+ struct ieee80211_sta *sta, -+ u8 rssi_level, bool update_bw); -+void rtl92d_update_channel_access_setting(struct ieee80211_hw *hw); -+bool rtl92d_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid); -+void rtl92d_set_key(struct ieee80211_hw *hw, u32 key_index, -+ u8 *p_macaddr, bool is_group, u8 enc_algo, -+ bool is_wepkey, bool clear_all); - - #endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c -index 72d2b7426d82..9f9a34492030 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.c -@@ -7,8 +7,8 @@ - #include "def.h" - #include "trx_common.h" - --static long _rtl92de_translate_todbm(struct ieee80211_hw *hw, -- u8 signal_strength_index) -+static long _rtl92d_translate_todbm(struct ieee80211_hw *hw, -+ u8 signal_strength_index) - { - long signal_power; - -@@ -17,13 +17,13 @@ static long _rtl92de_translate_todbm(struct ieee80211_hw *hw, - return signal_power; - } - --static void _rtl92de_query_rxphystatus(struct ieee80211_hw *hw, -- struct rtl_stats *pstats, -- __le32 *pdesc, -- struct rx_fwinfo_92d *p_drvinfo, -- bool packet_match_bssid, -- bool packet_toself, -- bool packet_beacon) -+static void _rtl92d_query_rxphystatus(struct ieee80211_hw *hw, -+ struct rtl_stats *pstats, -+ __le32 *pdesc, -+ struct rx_fwinfo_92d *p_drvinfo, -+ bool packet_match_bssid, -+ bool packet_toself, -+ bool packet_beacon) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_phy *rtlphy = &rtlpriv->phy; -@@ -203,8 +203,8 @@ static void rtl92d_loop_over_paths(struct ieee80211_hw *hw, - } - } - --static void _rtl92de_process_ui_rssi(struct ieee80211_hw *hw, -- struct rtl_stats *pstats) -+static void _rtl92d_process_ui_rssi(struct ieee80211_hw *hw, -+ struct rtl_stats *pstats) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rt_smooth_data *ui_rssi; -@@ -226,15 +226,15 @@ static void _rtl92de_process_ui_rssi(struct ieee80211_hw *hw, - if (ui_rssi->index >= PHY_RSSI_SLID_WIN_MAX) - ui_rssi->index = 0; - tmpval = ui_rssi->total_val / ui_rssi->total_num; -- rtlpriv->stats.signal_strength = _rtl92de_translate_todbm(hw, (u8)tmpval); -+ rtlpriv->stats.signal_strength = _rtl92d_translate_todbm(hw, (u8)tmpval); - pstats->rssi = rtlpriv->stats.signal_strength; - - if (!pstats->is_cck && pstats->packet_toself) - rtl92d_loop_over_paths(hw, pstats); - } - --static void _rtl92de_update_rxsignalstatistics(struct ieee80211_hw *hw, -- struct rtl_stats *pstats) -+static void _rtl92d_update_rxsignalstatistics(struct ieee80211_hw *hw, -+ struct rtl_stats *pstats) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - int weighting = 0; -@@ -249,8 +249,8 @@ static void _rtl92de_update_rxsignalstatistics(struct ieee80211_hw *hw, - 5 + pstats->recvsignalpower + weighting) / 6; - } - --static void _rtl92de_process_pwdb(struct ieee80211_hw *hw, -- struct rtl_stats *pstats) -+static void _rtl92d_process_pwdb(struct ieee80211_hw *hw, -+ struct rtl_stats *pstats) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -@@ -276,7 +276,7 @@ static void _rtl92de_process_pwdb(struct ieee80211_hw *hw, - (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); - } - rtlpriv->dm.undec_sm_pwdb = undec_sm_pwdb; -- _rtl92de_update_rxsignalstatistics(hw, pstats); -+ _rtl92d_update_rxsignalstatistics(hw, pstats); - } - } - -@@ -301,8 +301,8 @@ static void rtl92d_loop_over_streams(struct ieee80211_hw *hw, - } - } - --static void _rtl92de_process_ui_link_quality(struct ieee80211_hw *hw, -- struct rtl_stats *pstats) -+static void _rtl92d_process_ui_link_quality(struct ieee80211_hw *hw, -+ struct rtl_stats *pstats) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rt_smooth_data *ui_link_quality; -@@ -330,24 +330,24 @@ static void _rtl92de_process_ui_link_quality(struct ieee80211_hw *hw, - rtl92d_loop_over_streams(hw, pstats); - } - --static void _rtl92de_process_phyinfo(struct ieee80211_hw *hw, -- u8 *buffer, -- struct rtl_stats *pcurrent_stats) -+static void _rtl92d_process_phyinfo(struct ieee80211_hw *hw, -+ u8 *buffer, -+ struct rtl_stats *pcurrent_stats) - { - if (!pcurrent_stats->packet_matchbssid && - !pcurrent_stats->packet_beacon) - return; - -- _rtl92de_process_ui_rssi(hw, pcurrent_stats); -- _rtl92de_process_pwdb(hw, pcurrent_stats); -- _rtl92de_process_ui_link_quality(hw, pcurrent_stats); -+ _rtl92d_process_ui_rssi(hw, pcurrent_stats); -+ _rtl92d_process_pwdb(hw, pcurrent_stats); -+ _rtl92d_process_ui_link_quality(hw, pcurrent_stats); - } - --static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw, -- struct sk_buff *skb, -- struct rtl_stats *pstats, -- __le32 *pdesc, -- struct rx_fwinfo_92d *p_drvinfo) -+static void _rtl92d_translate_rx_signal_stuff(struct ieee80211_hw *hw, -+ struct sk_buff *skb, -+ struct rtl_stats *pstats, -+ __le32 *pdesc, -+ struct rx_fwinfo_92d *p_drvinfo) - { - struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); - struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -@@ -375,15 +375,15 @@ static void _rtl92de_translate_rx_signal_stuff(struct ieee80211_hw *hw, - packet_toself = packet_matchbssid && - ether_addr_equal(praddr, rtlefuse->dev_addr); - packet_beacon = ieee80211_is_beacon(fc); -- _rtl92de_query_rxphystatus(hw, pstats, pdesc, p_drvinfo, -- packet_matchbssid, packet_toself, -- packet_beacon); -- _rtl92de_process_phyinfo(hw, tmp_buf, pstats); -+ _rtl92d_query_rxphystatus(hw, pstats, pdesc, p_drvinfo, -+ packet_matchbssid, packet_toself, -+ packet_beacon); -+ _rtl92d_process_phyinfo(hw, tmp_buf, pstats); - } - --bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, -- struct ieee80211_rx_status *rx_status, -- u8 *pdesc8, struct sk_buff *skb) -+bool rtl92d_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, -+ struct ieee80211_rx_status *rx_status, -+ u8 *pdesc8, struct sk_buff *skb) - { - __le32 *pdesc = (__le32 *)pdesc8; - struct rx_fwinfo_92d *p_drvinfo; -@@ -423,17 +423,17 @@ bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, - if (phystatus) { - p_drvinfo = (struct rx_fwinfo_92d *)(skb->data + - stats->rx_bufshift); -- _rtl92de_translate_rx_signal_stuff(hw, skb, stats, pdesc, -- p_drvinfo); -+ _rtl92d_translate_rx_signal_stuff(hw, skb, stats, pdesc, -+ p_drvinfo); - } - /*rx_status->qual = stats->signal; */ - rx_status->signal = stats->recvsignalpower + 10; - return true; - } --EXPORT_SYMBOL_GPL(rtl92de_rx_query_desc); -+EXPORT_SYMBOL_GPL(rtl92d_rx_query_desc); - --void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc8, bool istx, -- u8 desc_name, u8 *val) -+void rtl92d_set_desc(struct ieee80211_hw *hw, u8 *pdesc8, bool istx, -+ u8 desc_name, u8 *val) - { - __le32 *pdesc = (__le32 *)pdesc8; - -@@ -473,10 +473,10 @@ void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc8, bool istx, - } - } - } --EXPORT_SYMBOL_GPL(rtl92de_set_desc); -+EXPORT_SYMBOL_GPL(rtl92d_set_desc); - --u64 rtl92de_get_desc(struct ieee80211_hw *hw, -- u8 *p_desc8, bool istx, u8 desc_name) -+u64 rtl92d_get_desc(struct ieee80211_hw *hw, -+ u8 *p_desc8, bool istx, u8 desc_name) - { - __le32 *p_desc = (__le32 *)p_desc8; - u32 ret = 0; -@@ -513,4 +513,4 @@ u64 rtl92de_get_desc(struct ieee80211_hw *hw, - } - return ret; - } --EXPORT_SYMBOL_GPL(rtl92de_get_desc); -+EXPORT_SYMBOL_GPL(rtl92d_get_desc); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h -index 87d956d771eb..528182b1eba6 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192d/trx_common.h -@@ -393,13 +393,13 @@ struct rx_fwinfo_92d { - #endif - } __packed; - --bool rtl92de_rx_query_desc(struct ieee80211_hw *hw, -- struct rtl_stats *stats, -- struct ieee80211_rx_status *rx_status, -- u8 *pdesc, struct sk_buff *skb); --void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, -- u8 desc_name, u8 *val); --u64 rtl92de_get_desc(struct ieee80211_hw *hw, -- u8 *p_desc, bool istx, u8 desc_name); -+bool rtl92d_rx_query_desc(struct ieee80211_hw *hw, -+ struct rtl_stats *stats, -+ struct ieee80211_rx_status *rx_status, -+ u8 *pdesc, struct sk_buff *skb); -+void rtl92d_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, -+ u8 desc_name, u8 *val); -+u64 rtl92d_get_desc(struct ieee80211_hw *hw, -+ u8 *p_desc, bool istx, u8 desc_name); - - #endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c -index 73b81e60cfa9..03f4314bdb2e 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c -@@ -181,7 +181,7 @@ void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) - u8 btype_ibss = val[0]; - - if (btype_ibss) -- rtl92de_stop_tx_beacon(hw); -+ rtl92d_stop_tx_beacon(hw); - _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3)); - rtl_write_dword(rtlpriv, REG_TSFTR, - (u32) (mac->tsf & 0xffffffff)); -@@ -189,7 +189,7 @@ void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) - (u32) ((mac->tsf >> 32) & 0xffffffff)); - _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0); - if (btype_ibss) -- rtl92de_resume_tx_beacon(hw); -+ rtl92d_resume_tx_beacon(hw); - - break; - } -@@ -295,13 +295,13 @@ static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw) - - /* 18. LLT_table_init(Adapter); */ - for (i = 0; i < (txpktbuf_bndy - 1); i++) { -- status = rtl92de_llt_write(hw, i, i + 1); -+ status = rtl92d_llt_write(hw, i, i + 1); - if (!status) - return status; - } - - /* end of list */ -- status = rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); -+ status = rtl92d_llt_write(hw, (txpktbuf_bndy - 1), 0xFF); - if (!status) - return status; - -@@ -310,13 +310,13 @@ static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw) - /* config this MAC as two MAC transfer. */ - /* Otherwise used as local loopback buffer. */ - for (i = txpktbuf_bndy; i < maxpage; i++) { -- status = rtl92de_llt_write(hw, i, (i + 1)); -+ status = rtl92d_llt_write(hw, i, (i + 1)); - if (!status) - return status; - } - - /* Let last entry point to the start entry of ring buffer */ -- status = rtl92de_llt_write(hw, maxpage, txpktbuf_bndy); -+ status = rtl92d_llt_write(hw, maxpage, txpktbuf_bndy); - if (!status) - return status; - -@@ -688,7 +688,7 @@ int rtl92de_hw_init(struct ieee80211_hw *hw) - - /* reset hw sec */ - rtl_cam_reset_all_entry(hw); -- rtl92de_enable_hw_security_config(hw); -+ rtl92d_enable_hw_security_config(hw); - - /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */ - /* TX power index for different rate set. */ -@@ -742,11 +742,11 @@ static int _rtl92de_set_media_status(struct ieee80211_hw *hw, - - if (type == NL80211_IFTYPE_UNSPECIFIED || - type == NL80211_IFTYPE_STATION) { -- rtl92de_stop_tx_beacon(hw); -+ rtl92d_stop_tx_beacon(hw); - _rtl92de_enable_bcn_sub_func(hw); - } else if (type == NL80211_IFTYPE_ADHOC || - type == NL80211_IFTYPE_AP) { -- rtl92de_resume_tx_beacon(hw); -+ rtl92d_resume_tx_beacon(hw); - _rtl92de_disable_bcn_sub_func(hw); - } else { - rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c -index 5f6311c2aac4..f5ce4889523e 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c -@@ -187,7 +187,7 @@ static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw) - static struct rtl_hal_ops rtl8192de_hal_ops = { - .init_sw_vars = rtl92d_init_sw_vars, - .deinit_sw_vars = rtl92d_deinit_sw_vars, -- .read_eeprom_info = rtl92de_read_eeprom_info, -+ .read_eeprom_info = rtl92d_read_eeprom_info, - .interrupt_recognized = rtl92de_interrupt_recognized, - .hw_init = rtl92de_hw_init, - .hw_disable = rtl92de_card_disable, -@@ -197,30 +197,30 @@ static struct rtl_hal_ops rtl8192de_hal_ops = { - .disable_interrupt = rtl92de_disable_interrupt, - .set_network_type = rtl92de_set_network_type, - .set_chk_bssid = rtl92de_set_check_bssid, -- .set_qos = rtl92de_set_qos, -+ .set_qos = rtl92d_set_qos, - .set_bcn_reg = rtl92de_set_beacon_related_registers, - .set_bcn_intv = rtl92de_set_beacon_interval, - .update_interrupt_mask = rtl92de_update_interrupt_mask, - .get_hw_reg = rtl92de_get_hw_reg, - .set_hw_reg = rtl92de_set_hw_reg, -- .update_rate_tbl = rtl92de_update_hal_rate_tbl, -+ .update_rate_tbl = rtl92d_update_hal_rate_tbl, - .fill_tx_desc = rtl92de_tx_fill_desc, - .fill_tx_cmddesc = rtl92de_tx_fill_cmddesc, -- .query_rx_desc = rtl92de_rx_query_desc, -- .set_channel_access = rtl92de_update_channel_access_setting, -- .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking, -+ .query_rx_desc = rtl92d_rx_query_desc, -+ .set_channel_access = rtl92d_update_channel_access_setting, -+ .radio_onoff_checking = rtl92d_gpio_radio_on_off_checking, - .set_bw_mode = rtl92d_phy_set_bw_mode, - .switch_channel = rtl92d_phy_sw_chnl, - .dm_watchdog = rtl92de_dm_watchdog, - .scan_operation_backup = rtl_phy_scan_operation_backup, - .set_rf_power_state = rtl92d_phy_set_rf_power_state, - .led_control = rtl92de_led_control, -- .set_desc = rtl92de_set_desc, -- .get_desc = rtl92de_get_desc, -+ .set_desc = rtl92d_set_desc, -+ .get_desc = rtl92d_get_desc, - .is_tx_desc_closed = rtl92de_is_tx_desc_closed, - .tx_polling = rtl92de_tx_polling, -- .enable_hw_sec = rtl92de_enable_hw_security_config, -- .set_key = rtl92de_set_key, -+ .enable_hw_sec = rtl92d_enable_hw_security_config, -+ .set_key = rtl92d_set_key, - .get_bbreg = rtl92d_phy_query_bb_reg, - .set_bbreg = rtl92d_phy_set_bb_reg, - .get_rfreg = rtl92d_phy_query_rf_reg, -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c -index 2b9b352f7783..91bf399c9ef1 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c -@@ -292,7 +292,7 @@ bool rtl92de_is_tx_desc_closed(struct ieee80211_hw *hw, - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); - struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; - u8 *entry = (u8 *)(&ring->desc[ring->idx]); -- u8 own = (u8)rtl92de_get_desc(hw, entry, true, HW_DESC_OWN); -+ u8 own = (u8)rtl92d_get_desc(hw, entry, true, HW_DESC_OWN); - - /* a beacon packet will only use the first - * descriptor by defaut, and the own bit may not --- -2.34.1 - diff --git a/packages/linux/patches/rtlwifi/6.11/0002-6.11-wifi-rtlwifi-Add-rtl8192du-table.-c-h.patch b/packages/linux/patches/rtlwifi/6.11/0002-6.11-wifi-rtlwifi-Add-rtl8192du-table.-c-h.patch deleted file mode 100644 index b3eb25fbae..0000000000 --- a/packages/linux/patches/rtlwifi/6.11/0002-6.11-wifi-rtlwifi-Add-rtl8192du-table.-c-h.patch +++ /dev/null @@ -1,1735 +0,0 @@ -From 76b9d3316e2d5db38de05e1ad8fe3c6acaabf21a Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 23 May 2024 17:44:09 +0300 -Subject: [PATCH 02/12] 6.11: wifi: rtlwifi: Add rtl8192du/table.{c,h} - -These contain the MAC, BB, RF, and AGC initialisation tables for -RTL8192DU. - -Signed-off-by: Bitterblue Smith ---- - .../realtek/rtlwifi/rtl8192du/table.c | 1675 +++++++++++++++++ - .../realtek/rtlwifi/rtl8192du/table.h | 29 + - 2 files changed, 1704 insertions(+) - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/table.c - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/table.h - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/table.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/table.c -new file mode 100644 -index 000000000000..036701433d85 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/table.c -@@ -0,0 +1,1675 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#include -+ -+#include "table.h" -+ -+const u32 rtl8192du_phy_reg_2tarray[PHY_REG_2T_ARRAYLENGTH] = { -+ 0x800, 0x80040002, -+ 0x804, 0x00000003, -+ 0x808, 0x0000fc00, -+ 0x80c, 0x0000000a, -+ 0x810, 0x10001331, -+ 0x814, 0x020c3d10, -+ 0x818, 0x02200385, -+ 0x81c, 0x00000000, -+ 0x820, 0x01000100, -+ 0x824, 0x00390004, -+ 0x828, 0x01000100, -+ 0x82c, 0x00390004, -+ 0x830, 0x27272727, -+ 0x834, 0x27272727, -+ 0x838, 0x27272727, -+ 0x83c, 0x27272727, -+ 0x840, 0x00010000, -+ 0x844, 0x00010000, -+ 0x848, 0x27272727, -+ 0x84c, 0x27272727, -+ 0x850, 0x00000000, -+ 0x854, 0x00000000, -+ 0x858, 0x569a569a, -+ 0x85c, 0x0c1b25a4, -+ 0x860, 0x66e60250, -+ 0x864, 0x061f0150, -+ 0x868, 0x27272727, -+ 0x86c, 0x272b2b2b, -+ 0x870, 0x07000700, -+ 0x874, 0x22188000, -+ 0x878, 0x08080808, -+ 0x87c, 0x0001fff8, -+ 0x880, 0xc0083070, -+ 0x884, 0x00000cd5, -+ 0x888, 0x00000000, -+ 0x88c, 0xcc0000c0, -+ 0x890, 0x00000800, -+ 0x894, 0xfffffffe, -+ 0x898, 0x40302010, -+ 0x89c, 0x00706050, -+ 0x900, 0x00000000, -+ 0x904, 0x00000023, -+ 0x908, 0x00000000, -+ 0x90c, 0x81121313, -+ 0xa00, 0x00d047c8, -+ 0xa04, 0x80ff000c, -+ 0xa08, 0x8c8a8300, -+ 0xa0c, 0x2e68120f, -+ 0xa10, 0x9500bb78, -+ 0xa14, 0x11144028, -+ 0xa18, 0x00881117, -+ 0xa1c, 0x89140f00, -+ 0xa20, 0x1a1b0000, -+ 0xa24, 0x090e1317, -+ 0xa28, 0x00000204, -+ 0xa2c, 0x00d30000, -+ 0xa70, 0x101fff00, -+ 0xa74, 0x00000007, -+ 0xc00, 0x40071d40, -+ 0xc04, 0x03a05633, -+ 0xc08, 0x001000e4, -+ 0xc0c, 0x6c6c6c6c, -+ 0xc10, 0x08800000, -+ 0xc14, 0x40000100, -+ 0xc18, 0x08800000, -+ 0xc1c, 0x40000100, -+ 0xc20, 0x00000000, -+ 0xc24, 0x00000000, -+ 0xc28, 0x00000000, -+ 0xc2c, 0x00000000, -+ 0xc30, 0x69e9ac44, -+ 0xc34, 0x469652af, -+ 0xc38, 0x49795994, -+ 0xc3c, 0x0a979718, -+ 0xc40, 0x1f7c403f, -+ 0xc44, 0x000100b7, -+ 0xc48, 0xec020107, -+ 0xc4c, 0x007f037f, -+ 0xc50, 0x69543420, -+ 0xc54, 0x43bc009e, -+ 0xc58, 0x69543420, -+ 0xc5c, 0x433c00a8, -+ 0xc60, 0x00000000, -+ 0xc64, 0x7112848b, -+ 0xc68, 0x47c00bff, -+ 0xc6c, 0x00000036, -+ 0xc70, 0x2c7f000d, -+ 0xc74, 0x258610db, -+ 0xc78, 0x0000001f, -+ 0xc7c, 0x40b95612, -+ 0xc80, 0x40000100, -+ 0xc84, 0x20f60000, -+ 0xc88, 0x40000100, -+ 0xc8c, 0xa0e40000, -+ 0xc90, 0x00121820, -+ 0xc94, 0x00000007, -+ 0xc98, 0x00121820, -+ 0xc9c, 0x00007f7f, -+ 0xca0, 0x00000000, -+ 0xca4, 0x00000080, -+ 0xca8, 0x00000000, -+ 0xcac, 0x00000000, -+ 0xcb0, 0x00000000, -+ 0xcb4, 0x00000000, -+ 0xcb8, 0x00000000, -+ 0xcbc, 0x28000000, -+ 0xcc0, 0x00000000, -+ 0xcc4, 0x00000000, -+ 0xcc8, 0x00000000, -+ 0xccc, 0x00000000, -+ 0xcd0, 0x00000000, -+ 0xcd4, 0x00000000, -+ 0xcd8, 0x64b11e20, -+ 0xcdc, 0xe0767533, -+ 0xce0, 0x00222222, -+ 0xce4, 0x00000000, -+ 0xce8, 0x37644302, -+ 0xcec, 0x2f97d40c, -+ 0xd00, 0x00080740, -+ 0xd04, 0x00020403, -+ 0xd08, 0x0000907f, -+ 0xd0c, 0x20010201, -+ 0xd10, 0xa0633333, -+ 0xd14, 0x3333bc43, -+ 0xd18, 0x7a8f5b6b, -+ 0xd2c, 0xcc979975, -+ 0xd30, 0x00000000, -+ 0xd34, 0x80608404, -+ 0xd38, 0x00000000, -+ 0xd3c, 0x00027353, -+ 0xd40, 0x00000000, -+ 0xd44, 0x00000000, -+ 0xd48, 0x00000000, -+ 0xd4c, 0x00000000, -+ 0xd50, 0x6437140a, -+ 0xd54, 0x00000000, -+ 0xd58, 0x00000000, -+ 0xd5c, 0x30032064, -+ 0xd60, 0x4653de68, -+ 0xd64, 0x04518a3c, -+ 0xd68, 0x00002101, -+ 0xd6c, 0x2a201c16, -+ 0xd70, 0x1812362e, -+ 0xd74, 0x322c2220, -+ 0xd78, 0x000e3c24, -+ 0xe00, 0x2a2a2a2a, -+ 0xe04, 0x2a2a2a2a, -+ 0xe08, 0x03902a2a, -+ 0xe10, 0x2a2a2a2a, -+ 0xe14, 0x2a2a2a2a, -+ 0xe18, 0x2a2a2a2a, -+ 0xe1c, 0x2a2a2a2a, -+ 0xe28, 0x00000000, -+ 0xe30, 0x1000dc1f, -+ 0xe34, 0x10008c1f, -+ 0xe38, 0x02140102, -+ 0xe3c, 0x681604c2, -+ 0xe40, 0x01007c00, -+ 0xe44, 0x01004800, -+ 0xe48, 0xfb000000, -+ 0xe4c, 0x000028d1, -+ 0xe50, 0x1000dc1f, -+ 0xe54, 0x10008c1f, -+ 0xe58, 0x02140102, -+ 0xe5c, 0x28160d05, -+ 0xe60, 0x00000010, -+ 0xe68, 0x001b25a4, -+ 0xe6c, 0x63db25a4, -+ 0xe70, 0x63db25a4, -+ 0xe74, 0x0c126da4, -+ 0xe78, 0x0c126da4, -+ 0xe7c, 0x0c126da4, -+ 0xe80, 0x0c126da4, -+ 0xe84, 0x63db25a4, -+ 0xe88, 0x0c126da4, -+ 0xe8c, 0x63db25a4, -+ 0xed0, 0x63db25a4, -+ 0xed4, 0x63db25a4, -+ 0xed8, 0x63db25a4, -+ 0xedc, 0x001b25a4, -+ 0xee0, 0x001b25a4, -+ 0xeec, 0x6fdb25a4, -+ 0xf14, 0x00000003, -+ 0xf1c, 0x00000064, -+ 0xf4c, 0x00000004, -+ 0xf00, 0x00000300, -+}; -+ -+const u32 rtl8192du_phy_reg_array_pg[PHY_REG_ARRAY_PG_LENGTH] = { -+ 0xe00, 0xffffffff, 0x07090c0c, -+ 0xe04, 0xffffffff, 0x01020405, -+ 0xe08, 0x0000ff00, 0x00000000, -+ 0x86c, 0xffffff00, 0x00000000, -+ 0xe10, 0xffffffff, 0x0b0c0c0e, -+ 0xe14, 0xffffffff, 0x01030506, -+ 0xe18, 0xffffffff, 0x0b0c0d0e, -+ 0xe1c, 0xffffffff, 0x01030509, -+ 0x830, 0xffffffff, 0x07090c0c, -+ 0x834, 0xffffffff, 0x01020405, -+ 0x838, 0xffffff00, 0x00000000, -+ 0x86c, 0x000000ff, 0x00000000, -+ 0x83c, 0xffffffff, 0x0b0c0c0e, -+ 0x848, 0xffffffff, 0x01030506, -+ 0x84c, 0xffffffff, 0x0b0c0d0e, -+ 0x868, 0xffffffff, 0x01030509, -+ 0xe00, 0xffffffff, 0x00000000, -+ 0xe04, 0xffffffff, 0x00000000, -+ 0xe08, 0x0000ff00, 0x00000000, -+ 0x86c, 0xffffff00, 0x00000000, -+ 0xe10, 0xffffffff, 0x00000000, -+ 0xe14, 0xffffffff, 0x00000000, -+ 0xe18, 0xffffffff, 0x00000000, -+ 0xe1c, 0xffffffff, 0x00000000, -+ 0x830, 0xffffffff, 0x00000000, -+ 0x834, 0xffffffff, 0x00000000, -+ 0x838, 0xffffff00, 0x00000000, -+ 0x86c, 0x000000ff, 0x00000000, -+ 0x83c, 0xffffffff, 0x00000000, -+ 0x848, 0xffffffff, 0x00000000, -+ 0x84c, 0xffffffff, 0x00000000, -+ 0x868, 0xffffffff, 0x00000000, -+ 0xe00, 0xffffffff, 0x04040404, -+ 0xe04, 0xffffffff, 0x00020204, -+ 0xe08, 0x0000ff00, 0x00000000, -+ 0x86c, 0xffffff00, 0x00000000, -+ 0xe10, 0xffffffff, 0x06060606, -+ 0xe14, 0xffffffff, 0x00020406, -+ 0xe18, 0xffffffff, 0x00000000, -+ 0xe1c, 0xffffffff, 0x00000000, -+ 0x830, 0xffffffff, 0x04040404, -+ 0x834, 0xffffffff, 0x00020204, -+ 0x838, 0xffffff00, 0x00000000, -+ 0x86c, 0x000000ff, 0x00000000, -+ 0x83c, 0xffffffff, 0x06060606, -+ 0x848, 0xffffffff, 0x00020406, -+ 0x84c, 0xffffffff, 0x00000000, -+ 0x868, 0xffffffff, 0x00000000, -+ 0xe00, 0xffffffff, 0x00000000, -+ 0xe04, 0xffffffff, 0x00000000, -+ 0xe08, 0x0000ff00, 0x00000000, -+ 0x86c, 0xffffff00, 0x00000000, -+ 0xe10, 0xffffffff, 0x00000000, -+ 0xe14, 0xffffffff, 0x00000000, -+ 0xe18, 0xffffffff, 0x00000000, -+ 0xe1c, 0xffffffff, 0x00000000, -+ 0x830, 0xffffffff, 0x00000000, -+ 0x834, 0xffffffff, 0x00000000, -+ 0x838, 0xffffff00, 0x00000000, -+ 0x86c, 0x000000ff, 0x00000000, -+ 0x83c, 0xffffffff, 0x00000000, -+ 0x848, 0xffffffff, 0x00000000, -+ 0x84c, 0xffffffff, 0x00000000, -+ 0x868, 0xffffffff, 0x00000000, -+ 0xe00, 0xffffffff, 0x00000000, -+ 0xe04, 0xffffffff, 0x00000000, -+ 0xe08, 0x0000ff00, 0x00000000, -+ 0x86c, 0xffffff00, 0x00000000, -+ 0xe10, 0xffffffff, 0x00000000, -+ 0xe14, 0xffffffff, 0x00000000, -+ 0xe18, 0xffffffff, 0x00000000, -+ 0xe1c, 0xffffffff, 0x00000000, -+ 0x830, 0xffffffff, 0x00000000, -+ 0x834, 0xffffffff, 0x00000000, -+ 0x838, 0xffffff00, 0x00000000, -+ 0x86c, 0x000000ff, 0x00000000, -+ 0x83c, 0xffffffff, 0x00000000, -+ 0x848, 0xffffffff, 0x00000000, -+ 0x84c, 0xffffffff, 0x00000000, -+ 0x868, 0xffffffff, 0x00000000, -+ 0xe00, 0xffffffff, 0x04040404, -+ 0xe04, 0xffffffff, 0x00020204, -+ 0xe08, 0x0000ff00, 0x00000000, -+ 0x86c, 0xffffff00, 0x00000000, -+ 0xe10, 0xffffffff, 0x00000000, -+ 0xe14, 0xffffffff, 0x00000000, -+ 0xe18, 0xffffffff, 0x00000000, -+ 0xe1c, 0xffffffff, 0x00000000, -+ 0x830, 0xffffffff, 0x04040404, -+ 0x834, 0xffffffff, 0x00020204, -+ 0x838, 0xffffff00, 0x00000000, -+ 0x86c, 0x000000ff, 0x00000000, -+ 0x83c, 0xffffffff, 0x00000000, -+ 0x848, 0xffffffff, 0x00000000, -+ 0x84c, 0xffffffff, 0x00000000, -+ 0x868, 0xffffffff, 0x00000000, -+ 0xe00, 0xffffffff, 0x00000000, -+ 0xe04, 0xffffffff, 0x00000000, -+ 0xe08, 0x0000ff00, 0x00000000, -+ 0x86c, 0xffffff00, 0x00000000, -+ 0xe10, 0xffffffff, 0x00000000, -+ 0xe14, 0xffffffff, 0x00000000, -+ 0xe18, 0xffffffff, 0x00000000, -+ 0xe1c, 0xffffffff, 0x00000000, -+ 0x830, 0xffffffff, 0x00000000, -+ 0x834, 0xffffffff, 0x00000000, -+ 0x838, 0xffffff00, 0x00000000, -+ 0x86c, 0x000000ff, 0x00000000, -+ 0x83c, 0xffffffff, 0x00000000, -+ 0x848, 0xffffffff, 0x00000000, -+ 0x84c, 0xffffffff, 0x00000000, -+ 0x868, 0xffffffff, 0x00000000, -+ 0xe00, 0xffffffff, 0x04040404, -+ 0xe04, 0xffffffff, 0x00020204, -+ 0xe08, 0x0000ff00, 0x00000000, -+ 0x86c, 0xffffff00, 0x00000000, -+ 0xe10, 0xffffffff, 0x08080808, -+ 0xe14, 0xffffffff, 0x00040408, -+ 0xe18, 0xffffffff, 0x00000000, -+ 0xe1c, 0xffffffff, 0x00000000, -+ 0x830, 0xffffffff, 0x04040404, -+ 0x834, 0xffffffff, 0x00020204, -+ 0x838, 0xffffff00, 0x00000000, -+ 0x86c, 0x000000ff, 0x00000000, -+ 0x83c, 0xffffffff, 0x08080808, -+ 0x848, 0xffffffff, 0x00040408, -+ 0x84c, 0xffffffff, 0x00000000, -+ 0x868, 0xffffffff, 0x00000000, -+ 0xe00, 0xffffffff, 0x04040404, -+ 0xe04, 0xffffffff, 0x00020204, -+ 0xe08, 0x0000ff00, 0x00000000, -+ 0x86c, 0xffffff00, 0x00000000, -+ 0xe10, 0xffffffff, 0x08080808, -+ 0xe14, 0xffffffff, 0x00040408, -+ 0xe18, 0xffffffff, 0x00000000, -+ 0xe1c, 0xffffffff, 0x00000000, -+ 0x830, 0xffffffff, 0x04040404, -+ 0x834, 0xffffffff, 0x00020204, -+ 0x838, 0xffffff00, 0x00000000, -+ 0x86c, 0x000000ff, 0x00000000, -+ 0x83c, 0xffffffff, 0x08080808, -+ 0x848, 0xffffffff, 0x00040408, -+ 0x84c, 0xffffffff, 0x00000000, -+ 0x868, 0xffffffff, 0x00000000, -+ 0xe00, 0xffffffff, 0x04040404, -+ 0xe04, 0xffffffff, 0x00020204, -+ 0xe08, 0x0000ff00, 0x00000000, -+ 0x86c, 0xffffff00, 0x00000000, -+ 0xe10, 0xffffffff, 0x08080808, -+ 0xe14, 0xffffffff, 0x00040408, -+ 0xe18, 0xffffffff, 0x00000000, -+ 0xe1c, 0xffffffff, 0x00000000, -+ 0x830, 0xffffffff, 0x04040404, -+ 0x834, 0xffffffff, 0x00020204, -+ 0x838, 0xffffff00, 0x00000000, -+ 0x86c, 0x000000ff, 0x00000000, -+ 0x83c, 0xffffffff, 0x08080808, -+ 0x848, 0xffffffff, 0x00040408, -+ 0x84c, 0xffffffff, 0x00000000, -+ 0x868, 0xffffffff, 0x00000000, -+ 0xe00, 0xffffffff, 0x04040404, -+ 0xe04, 0xffffffff, 0x00020204, -+ 0xe08, 0x0000ff00, 0x00000000, -+ 0x86c, 0xffffff00, 0x00000000, -+ 0xe10, 0xffffffff, 0x08080808, -+ 0xe14, 0xffffffff, 0x00040408, -+ 0xe18, 0xffffffff, 0x00000000, -+ 0xe1c, 0xffffffff, 0x00000000, -+ 0x830, 0xffffffff, 0x04040404, -+ 0x834, 0xffffffff, 0x00020204, -+ 0x838, 0xffffff00, 0x00000000, -+ 0x86c, 0x000000ff, 0x00000000, -+ 0x83c, 0xffffffff, 0x08080808, -+ 0x848, 0xffffffff, 0x00040408, -+ 0x84c, 0xffffffff, 0x00000000, -+ 0x868, 0xffffffff, 0x00000000, -+ 0xe00, 0xffffffff, 0x04040404, -+ 0xe04, 0xffffffff, 0x00020204, -+ 0xe08, 0x0000ff00, 0x00000000, -+ 0x86c, 0xffffff00, 0x00000000, -+ 0xe10, 0xffffffff, 0x08080808, -+ 0xe14, 0xffffffff, 0x00040408, -+ 0xe18, 0xffffffff, 0x00000000, -+ 0xe1c, 0xffffffff, 0x00000000, -+ 0x830, 0xffffffff, 0x04040404, -+ 0x834, 0xffffffff, 0x00020204, -+ 0x838, 0xffffff00, 0x00000000, -+ 0x86c, 0x000000ff, 0x00000000, -+ 0x83c, 0xffffffff, 0x08080808, -+ 0x848, 0xffffffff, 0x00040408, -+ 0x84c, 0xffffffff, 0x00000000, -+ 0x868, 0xffffffff, 0x00000000, -+ 0xe00, 0xffffffff, 0x04040404, -+ 0xe04, 0xffffffff, 0x00020204, -+ 0xe08, 0x0000ff00, 0x00000000, -+ 0x86c, 0xffffff00, 0x00000000, -+ 0xe10, 0xffffffff, 0x08080808, -+ 0xe14, 0xffffffff, 0x00040408, -+ 0xe18, 0xffffffff, 0x00000000, -+ 0xe1c, 0xffffffff, 0x00000000, -+ 0x830, 0xffffffff, 0x04040404, -+ 0x834, 0xffffffff, 0x00020204, -+ 0x838, 0xffffff00, 0x00000000, -+ 0x86c, 0x000000ff, 0x00000000, -+ 0x83c, 0xffffffff, 0x08080808, -+ 0x848, 0xffffffff, 0x00040408, -+ 0x84c, 0xffffffff, 0x00000000, -+ 0x868, 0xffffffff, 0x00000000, -+}; -+ -+const u32 rtl8192du_radioa_2tarray[RADIOA_2T_ARRAYLENGTH] = { -+ 0x000, 0x00030000, -+ 0x001, 0x00030000, -+ 0x002, 0x00000000, -+ 0x003, 0x00018c63, -+ 0x004, 0x00018c63, -+ 0x008, 0x00084000, -+ 0x00b, 0x0001c000, -+ 0x00e, 0x00018c67, -+ 0x00f, 0x00000851, -+ 0x014, 0x00021440, -+ 0x018, 0x00017524, -+ 0x019, 0x00000000, -+ 0x01d, 0x000a1290, -+ 0x023, 0x00001558, -+ 0x01a, 0x00030a99, -+ 0x01b, 0x00040b00, -+ 0x01c, 0x000fc339, -+ 0x03a, 0x000a57eb, -+ 0x03b, 0x00020000, -+ 0x03c, 0x000ff454, -+ 0x020, 0x0000aa52, -+ 0x021, 0x00054000, -+ 0x040, 0x0000aa52, -+ 0x041, 0x00014000, -+ 0x025, 0x000803be, -+ 0x026, 0x000fc638, -+ 0x027, 0x00077c18, -+ 0x028, 0x000de471, -+ 0x029, 0x000d7110, -+ 0x02a, 0x0008cb04, -+ 0x02b, 0x0004128b, -+ 0x02c, 0x00001840, -+ 0x043, 0x0002444f, -+ 0x044, 0x0001adb0, -+ 0x045, 0x00056467, -+ 0x046, 0x0008992c, -+ 0x047, 0x0000452c, -+ 0x048, 0x000f9c43, -+ 0x049, 0x00002e0c, -+ 0x04a, 0x000546eb, -+ 0x04b, 0x0008966c, -+ 0x04c, 0x0000dde9, -+ 0x018, 0x00007401, -+ 0x000, 0x00070000, -+ 0x012, 0x000dc000, -+ 0x012, 0x00090000, -+ 0x012, 0x00051000, -+ 0x012, 0x00012000, -+ 0x013, 0x000287b7, -+ 0x013, 0x000247ab, -+ 0x013, 0x0002079f, -+ 0x013, 0x0001c793, -+ 0x013, 0x0001839b, -+ 0x013, 0x00014392, -+ 0x013, 0x0001019a, -+ 0x013, 0x0000c191, -+ 0x013, 0x00008194, -+ 0x013, 0x000040a0, -+ 0x013, 0x00000018, -+ 0x015, 0x0000f424, -+ 0x015, 0x0004f424, -+ 0x015, 0x0008f424, -+ 0x016, 0x000e1330, -+ 0x016, 0x000a1330, -+ 0x016, 0x00061330, -+ 0x016, 0x00021330, -+ 0x018, 0x00017524, -+ 0x000, 0x00070000, -+ 0x012, 0x000cf000, -+ 0x012, 0x000bc000, -+ 0x012, 0x00078000, -+ 0x012, 0x00000000, -+ 0x013, 0x000287bc, -+ 0x013, 0x000247b0, -+ 0x013, 0x000203b4, -+ 0x013, 0x0001c3a8, -+ 0x013, 0x000181b4, -+ 0x013, 0x000141a8, -+ 0x013, 0x000100b4, -+ 0x013, 0x0000c0a8, -+ 0x013, 0x0000b030, -+ 0x013, 0x00004024, -+ 0x013, 0x00000018, -+ 0x015, 0x0000f4c3, -+ 0x015, 0x0004f4c3, -+ 0x015, 0x0008f4c3, -+ 0x016, 0x000e085f, -+ 0x016, 0x000a085f, -+ 0x016, 0x0006085f, -+ 0x016, 0x0002085f, -+ 0x018, 0x00037524, -+ 0x000, 0x00070000, -+ 0x012, 0x000cf000, -+ 0x012, 0x000bc000, -+ 0x012, 0x00078000, -+ 0x012, 0x00000000, -+ 0x013, 0x000287bc, -+ 0x013, 0x000247b0, -+ 0x013, 0x000203b4, -+ 0x013, 0x0001c3a8, -+ 0x013, 0x000181b4, -+ 0x013, 0x000141a8, -+ 0x013, 0x000100b4, -+ 0x013, 0x0000c0a8, -+ 0x013, 0x0000b030, -+ 0x013, 0x00004024, -+ 0x013, 0x00000018, -+ 0x015, 0x0000f4c3, -+ 0x015, 0x0004f4c3, -+ 0x015, 0x0008f4c3, -+ 0x016, 0x000e085f, -+ 0x016, 0x000a085f, -+ 0x016, 0x0006085f, -+ 0x016, 0x0002085f, -+ 0x018, 0x00057568, -+ 0x000, 0x00070000, -+ 0x012, 0x000cf000, -+ 0x012, 0x000bc000, -+ 0x012, 0x00078000, -+ 0x012, 0x00000000, -+ 0x013, 0x000287bc, -+ 0x013, 0x000247b0, -+ 0x013, 0x000203b4, -+ 0x013, 0x0001c3a8, -+ 0x013, 0x000181b4, -+ 0x013, 0x000141a8, -+ 0x013, 0x000100b4, -+ 0x013, 0x0000c0a8, -+ 0x013, 0x0000b030, -+ 0x013, 0x00004024, -+ 0x013, 0x00000018, -+ 0x015, 0x0000f4c3, -+ 0x015, 0x0004f4c3, -+ 0x015, 0x0008f4c3, -+ 0x016, 0x000e085f, -+ 0x016, 0x000a085f, -+ 0x016, 0x0006085f, -+ 0x016, 0x0002085f, -+ 0x030, 0x0004470f, -+ 0x031, 0x00044ff0, -+ 0x032, 0x00000070, -+ 0x033, 0x000dd480, -+ 0x034, 0x000ffac0, -+ 0x035, 0x000b80c0, -+ 0x036, 0x00077000, -+ 0x037, 0x00064ff2, -+ 0x038, 0x000e7661, -+ 0x039, 0x00000e90, -+ 0x000, 0x00030000, -+ 0x018, 0x0000f401, -+ 0x0fe, 0x00000000, -+ 0x0fe, 0x00000000, -+ 0x01e, 0x00088009, -+ 0x01f, 0x00080003, -+ 0x0fe, 0x00000000, -+ 0x01e, 0x00088001, -+ 0x01f, 0x00080000, -+ 0x0fe, 0x00000000, -+ 0x018, 0x00097524, -+ 0x0fe, 0x00000000, -+ 0x0fe, 0x00000000, -+ 0x0fe, 0x00000000, -+ 0x0fe, 0x00000000, -+ 0x02b, 0x00041289, -+ 0x0fe, 0x00000000, -+ 0x02d, 0x0006aaaa, -+ 0x02e, 0x000b4d01, -+ 0x02d, 0x00080000, -+ 0x02e, 0x00004d02, -+ 0x02d, 0x00095555, -+ 0x02e, 0x00054d03, -+ 0x02d, 0x000aaaaa, -+ 0x02e, 0x000b4d04, -+ 0x02d, 0x000c0000, -+ 0x02e, 0x00004d05, -+ 0x02d, 0x000d5555, -+ 0x02e, 0x00054d06, -+ 0x02d, 0x000eaaaa, -+ 0x02e, 0x000b4d07, -+ 0x02d, 0x00000000, -+ 0x02e, 0x00005108, -+ 0x02d, 0x00015555, -+ 0x02e, 0x00055109, -+ 0x02d, 0x0002aaaa, -+ 0x02e, 0x000b510a, -+ 0x02d, 0x00040000, -+ 0x02e, 0x0000510b, -+ 0x02d, 0x00055555, -+ 0x02e, 0x0005510c, -+}; -+ -+const u32 rtl8192du_radiob_2tarray[RADIOB_2T_ARRAYLENGTH] = { -+ 0x000, 0x00030000, -+ 0x001, 0x00030000, -+ 0x002, 0x00000000, -+ 0x003, 0x00018c63, -+ 0x004, 0x00018c63, -+ 0x008, 0x00084000, -+ 0x00b, 0x0001c000, -+ 0x00e, 0x00018c67, -+ 0x00f, 0x00000851, -+ 0x014, 0x00021440, -+ 0x018, 0x00007401, -+ 0x019, 0x00000060, -+ 0x01d, 0x000a1290, -+ 0x023, 0x00001558, -+ 0x01a, 0x00030a99, -+ 0x01b, 0x00040b00, -+ 0x01c, 0x000fc339, -+ 0x03a, 0x000a57eb, -+ 0x03b, 0x00020000, -+ 0x03c, 0x000ff454, -+ 0x020, 0x0000aa52, -+ 0x021, 0x00054000, -+ 0x040, 0x0000aa52, -+ 0x041, 0x00014000, -+ 0x025, 0x000803be, -+ 0x026, 0x000fc638, -+ 0x027, 0x00077c18, -+ 0x028, 0x000d1c31, -+ 0x029, 0x000d7110, -+ 0x02a, 0x000aeb04, -+ 0x02b, 0x0004128b, -+ 0x02c, 0x00001840, -+ 0x043, 0x0002444f, -+ 0x044, 0x0001adb0, -+ 0x045, 0x00056467, -+ 0x046, 0x0008992c, -+ 0x047, 0x0000452c, -+ 0x048, 0x000f9c43, -+ 0x049, 0x00002e0c, -+ 0x04a, 0x000546eb, -+ 0x04b, 0x0008966c, -+ 0x04c, 0x0000dde9, -+ 0x018, 0x00007401, -+ 0x000, 0x00070000, -+ 0x012, 0x000dc000, -+ 0x012, 0x00090000, -+ 0x012, 0x00051000, -+ 0x012, 0x00012000, -+ 0x013, 0x000287b7, -+ 0x013, 0x000247ab, -+ 0x013, 0x0002079f, -+ 0x013, 0x0001c793, -+ 0x013, 0x0001839b, -+ 0x013, 0x00014392, -+ 0x013, 0x0001019a, -+ 0x013, 0x0000c191, -+ 0x013, 0x00008194, -+ 0x013, 0x000040a0, -+ 0x013, 0x00000018, -+ 0x015, 0x0000f424, -+ 0x015, 0x0004f424, -+ 0x015, 0x0008f424, -+ 0x016, 0x000e1330, -+ 0x016, 0x000a1330, -+ 0x016, 0x00061330, -+ 0x016, 0x00021330, -+ 0x018, 0x00017524, -+ 0x000, 0x00070000, -+ 0x012, 0x000cf000, -+ 0x012, 0x000bc000, -+ 0x012, 0x00078000, -+ 0x012, 0x00000000, -+ 0x013, 0x000287bc, -+ 0x013, 0x000247b0, -+ 0x013, 0x000203b4, -+ 0x013, 0x0001c3a8, -+ 0x013, 0x000181b4, -+ 0x013, 0x000141a8, -+ 0x013, 0x000100b4, -+ 0x013, 0x0000c0a8, -+ 0x013, 0x0000b030, -+ 0x013, 0x00004024, -+ 0x013, 0x00000018, -+ 0x015, 0x0000f4c3, -+ 0x015, 0x0004f4c3, -+ 0x015, 0x0008f4c3, -+ 0x016, 0x000e085f, -+ 0x016, 0x000a085f, -+ 0x016, 0x0006085f, -+ 0x016, 0x0002085f, -+ 0x018, 0x00037524, -+ 0x000, 0x00070000, -+ 0x012, 0x000cf000, -+ 0x012, 0x000bc000, -+ 0x012, 0x00078000, -+ 0x012, 0x00000000, -+ 0x013, 0x000287bc, -+ 0x013, 0x000247b0, -+ 0x013, 0x000203b4, -+ 0x013, 0x0001c3a8, -+ 0x013, 0x000181b4, -+ 0x013, 0x000141a8, -+ 0x013, 0x000100b4, -+ 0x013, 0x0000c0a8, -+ 0x013, 0x0000b030, -+ 0x013, 0x00004024, -+ 0x013, 0x00000018, -+ 0x015, 0x0000f4c3, -+ 0x015, 0x0004f4c3, -+ 0x015, 0x0008f4c3, -+ 0x016, 0x000e085f, -+ 0x016, 0x000a085f, -+ 0x016, 0x0006085f, -+ 0x016, 0x0002085f, -+ 0x018, 0x00057524, -+ 0x000, 0x00070000, -+ 0x012, 0x000cf000, -+ 0x012, 0x000bc000, -+ 0x012, 0x00078000, -+ 0x012, 0x00000000, -+ 0x013, 0x000287bc, -+ 0x013, 0x000247b0, -+ 0x013, 0x000203b4, -+ 0x013, 0x0001c3a8, -+ 0x013, 0x000181b4, -+ 0x013, 0x000141a8, -+ 0x013, 0x000100b4, -+ 0x013, 0x0000c0a8, -+ 0x013, 0x0000b030, -+ 0x013, 0x00004024, -+ 0x013, 0x00000018, -+ 0x015, 0x0000f4c3, -+ 0x015, 0x0004f4c3, -+ 0x015, 0x0008f4c3, -+ 0x016, 0x000e085f, -+ 0x016, 0x000a085f, -+ 0x016, 0x0006085f, -+ 0x016, 0x0002085f, -+ 0x030, 0x0004470f, -+ 0x031, 0x00044ff0, -+ 0x032, 0x00000070, -+ 0x033, 0x000dd480, -+ 0x034, 0x000ffac0, -+ 0x035, 0x000b80c0, -+ 0x036, 0x00077000, -+ 0x037, 0x00064ff2, -+ 0x038, 0x000e7661, -+ 0x039, 0x00000e90, -+ 0x000, 0x00030000, -+ 0x018, 0x0000f401, -+ 0x0fe, 0x00000000, -+ 0x0fe, 0x00000000, -+ 0x01e, 0x00088009, -+ 0x01f, 0x00080003, -+ 0x0fe, 0x00000000, -+ 0x01e, 0x00088001, -+ 0x01f, 0x00080000, -+ 0x0fe, 0x00000000, -+ 0x018, 0x00087401, -+ 0x0fe, 0x00000000, -+ 0x0fe, 0x00000000, -+ 0x0fe, 0x00000000, -+ 0x02b, 0x00041289, -+ 0x0fe, 0x00000000, -+ 0x02d, 0x00066666, -+ 0x02e, 0x00064001, -+ 0x02d, 0x00091111, -+ 0x02e, 0x00014002, -+ 0x02d, 0x000bbbbb, -+ 0x02e, 0x000b4003, -+ 0x02d, 0x000e6666, -+ 0x02e, 0x00064004, -+ 0x02d, 0x00088888, -+ 0x02e, 0x00084005, -+ 0x02d, 0x0009dddd, -+ 0x02e, 0x000d4006, -+ 0x02d, 0x000b3333, -+ 0x02e, 0x00034007, -+ 0x02d, 0x00048888, -+ 0x02e, 0x00084408, -+ 0x02d, 0x000bbbbb, -+ 0x02e, 0x000b4409, -+ 0x02d, 0x000e6666, -+ 0x02e, 0x0006440a, -+ 0x02d, 0x00011111, -+ 0x02e, 0x0001480b, -+ 0x02d, 0x0003bbbb, -+ 0x02e, 0x000b480c, -+ 0x02d, 0x00066666, -+ 0x02e, 0x0006480d, -+ 0x02d, 0x000ccccc, -+ 0x02e, 0x000c480e, -+}; -+ -+const u32 rtl8192du_radioa_2t_int_paarray[RADIOA_2T_INT_PA_ARRAYLENGTH] = { -+ 0x000, 0x00030000, -+ 0x001, 0x00030000, -+ 0x002, 0x00000000, -+ 0x003, 0x00018c63, -+ 0x004, 0x00018c63, -+ 0x008, 0x00084000, -+ 0x00b, 0x0001c000, -+ 0x00e, 0x00018c67, -+ 0x00f, 0x00000851, -+ 0x014, 0x00021440, -+ 0x018, 0x00017524, -+ 0x019, 0x00000000, -+ 0x01d, 0x000a1290, -+ 0x023, 0x00001558, -+ 0x01a, 0x00030a99, -+ 0x01b, 0x00040b00, -+ 0x01c, 0x000fc339, -+ 0x03a, 0x000a57eb, -+ 0x03b, 0x00020000, -+ 0x03c, 0x000ff455, -+ 0x020, 0x0000aa52, -+ 0x021, 0x00054000, -+ 0x040, 0x0000aa52, -+ 0x041, 0x00014000, -+ 0x025, 0x000803be, -+ 0x026, 0x000fc638, -+ 0x027, 0x00077c18, -+ 0x028, 0x000de471, -+ 0x029, 0x000d7110, -+ 0x02a, 0x0008eb04, -+ 0x02b, 0x0004128b, -+ 0x02c, 0x00001840, -+ 0x043, 0x0002444f, -+ 0x044, 0x0001adb0, -+ 0x045, 0x00056467, -+ 0x046, 0x0008992c, -+ 0x047, 0x0000452c, -+ 0x048, 0x000c0443, -+ 0x049, 0x00000730, -+ 0x04a, 0x00050f0f, -+ 0x04b, 0x000896ef, -+ 0x04c, 0x0000ddee, -+ 0x018, 0x00007401, -+ 0x000, 0x00070000, -+ 0x012, 0x000dc000, -+ 0x012, 0x00090000, -+ 0x012, 0x00051000, -+ 0x012, 0x00012000, -+ 0x013, 0x000287b7, -+ 0x013, 0x000247ab, -+ 0x013, 0x0002079f, -+ 0x013, 0x0001c793, -+ 0x013, 0x0001839b, -+ 0x013, 0x00014392, -+ 0x013, 0x0001019a, -+ 0x013, 0x0000c191, -+ 0x013, 0x00008194, -+ 0x013, 0x000040a0, -+ 0x013, 0x00000018, -+ 0x015, 0x0000f424, -+ 0x015, 0x0004f424, -+ 0x015, 0x0008f424, -+ 0x016, 0x000e1330, -+ 0x016, 0x000a1330, -+ 0x016, 0x00061330, -+ 0x016, 0x00021330, -+ 0x018, 0x00017524, -+ 0x000, 0x00070000, -+ 0x012, 0x000cf000, -+ 0x012, 0x000bc000, -+ 0x012, 0x00078000, -+ 0x012, 0x00000000, -+ 0x013, 0x000287bf, -+ 0x013, 0x000247b3, -+ 0x013, 0x000207a7, -+ 0x013, 0x0001c79b, -+ 0x013, 0x0001839f, -+ 0x013, 0x00014393, -+ 0x013, 0x00010399, -+ 0x013, 0x0000c38d, -+ 0x013, 0x00008199, -+ 0x013, 0x0000418d, -+ 0x013, 0x00000099, -+ 0x015, 0x0000f495, -+ 0x015, 0x0004f495, -+ 0x015, 0x0008f495, -+ 0x016, 0x000e1874, -+ 0x016, 0x000a1874, -+ 0x016, 0x00061874, -+ 0x016, 0x00021874, -+ 0x018, 0x00037564, -+ 0x000, 0x00070000, -+ 0x012, 0x000cf000, -+ 0x012, 0x000bc000, -+ 0x012, 0x00078000, -+ 0x012, 0x00000000, -+ 0x013, 0x000287bf, -+ 0x013, 0x000247b3, -+ 0x013, 0x000207a7, -+ 0x013, 0x0001c79b, -+ 0x013, 0x0001839f, -+ 0x013, 0x00014393, -+ 0x013, 0x00010399, -+ 0x013, 0x0000c38d, -+ 0x013, 0x00008199, -+ 0x013, 0x0000418d, -+ 0x013, 0x00000099, -+ 0x015, 0x0000f495, -+ 0x015, 0x0004f495, -+ 0x015, 0x0008f495, -+ 0x016, 0x000e1874, -+ 0x016, 0x000a1874, -+ 0x016, 0x00061874, -+ 0x016, 0x00021874, -+ 0x018, 0x00057595, -+ 0x000, 0x00070000, -+ 0x012, 0x000cf000, -+ 0x012, 0x000bc000, -+ 0x012, 0x00078000, -+ 0x012, 0x00000000, -+ 0x013, 0x000287bf, -+ 0x013, 0x000247b3, -+ 0x013, 0x000207a7, -+ 0x013, 0x0001c79b, -+ 0x013, 0x0001839f, -+ 0x013, 0x00014393, -+ 0x013, 0x00010399, -+ 0x013, 0x0000c38d, -+ 0x013, 0x00008199, -+ 0x013, 0x0000418d, -+ 0x013, 0x00000099, -+ 0x015, 0x0000f495, -+ 0x015, 0x0004f495, -+ 0x015, 0x0008f495, -+ 0x016, 0x000e1874, -+ 0x016, 0x000a1874, -+ 0x016, 0x00061874, -+ 0x016, 0x00021874, -+ 0x030, 0x0004470f, -+ 0x031, 0x00044ff0, -+ 0x032, 0x00000070, -+ 0x033, 0x000dd480, -+ 0x034, 0x000ffac0, -+ 0x035, 0x000b80c0, -+ 0x036, 0x00077000, -+ 0x037, 0x00064ff2, -+ 0x038, 0x000e7661, -+ 0x039, 0x00000e90, -+ 0x000, 0x00030000, -+ 0x018, 0x0000f401, -+ 0x0fe, 0x00000000, -+ 0x0fe, 0x00000000, -+ 0x01e, 0x00088009, -+ 0x01f, 0x00080003, -+ 0x0fe, 0x00000000, -+ 0x01e, 0x00088001, -+ 0x01f, 0x00080000, -+ 0x0fe, 0x00000000, -+ 0x018, 0x00097524, -+ 0x0fe, 0x00000000, -+ 0x0fe, 0x00000000, -+ 0x0fe, 0x00000000, -+ 0x0fe, 0x00000000, -+ 0x02b, 0x00041289, -+ 0x0fe, 0x00000000, -+ 0x02d, 0x0006aaaa, -+ 0x02e, 0x000b4d01, -+ 0x02d, 0x00080000, -+ 0x02e, 0x00004d02, -+ 0x02d, 0x00095555, -+ 0x02e, 0x00054d03, -+ 0x02d, 0x000aaaaa, -+ 0x02e, 0x000b4d04, -+ 0x02d, 0x000c0000, -+ 0x02e, 0x00004d05, -+ 0x02d, 0x000d5555, -+ 0x02e, 0x00054d06, -+ 0x02d, 0x000eaaaa, -+ 0x02e, 0x000b4d07, -+ 0x02d, 0x00000000, -+ 0x02e, 0x00005108, -+ 0x02d, 0x00015555, -+ 0x02e, 0x00055109, -+ 0x02d, 0x0002aaaa, -+ 0x02e, 0x000b510a, -+ 0x02d, 0x00040000, -+ 0x02e, 0x0000510b, -+ 0x02d, 0x00055555, -+ 0x02e, 0x0005510c, -+}; -+ -+const u32 rtl8192du_radiob_2t_int_paarray[RADIOB_2T_INT_PA_ARRAYLENGTH] = { -+ 0x000, 0x00030000, -+ 0x001, 0x00030000, -+ 0x002, 0x00000000, -+ 0x003, 0x00018c63, -+ 0x004, 0x00018c63, -+ 0x008, 0x00084000, -+ 0x00b, 0x0001c000, -+ 0x00e, 0x00018c67, -+ 0x00f, 0x00000851, -+ 0x014, 0x00021440, -+ 0x018, 0x00007401, -+ 0x019, 0x00000060, -+ 0x01d, 0x000a1290, -+ 0x023, 0x00001558, -+ 0x01a, 0x00030a99, -+ 0x01b, 0x00040b00, -+ 0x01c, 0x000fc339, -+ 0x03a, 0x000a57eb, -+ 0x03b, 0x00020000, -+ 0x03c, 0x000ff455, -+ 0x020, 0x0000aa52, -+ 0x021, 0x00054000, -+ 0x040, 0x0000aa52, -+ 0x041, 0x00014000, -+ 0x025, 0x000803be, -+ 0x026, 0x000fc638, -+ 0x027, 0x00077c18, -+ 0x028, 0x000d1c31, -+ 0x029, 0x000d7110, -+ 0x02a, 0x000aeb04, -+ 0x02b, 0x0004128b, -+ 0x02c, 0x00001840, -+ 0x043, 0x0002444f, -+ 0x044, 0x0001adb0, -+ 0x045, 0x00056467, -+ 0x046, 0x0008992c, -+ 0x047, 0x0000452c, -+ 0x048, 0x000c0443, -+ 0x049, 0x00000730, -+ 0x04a, 0x00050f0f, -+ 0x04b, 0x000896ef, -+ 0x04c, 0x0000ddee, -+ 0x018, 0x00007401, -+ 0x000, 0x00070000, -+ 0x012, 0x000dc000, -+ 0x012, 0x00090000, -+ 0x012, 0x00051000, -+ 0x012, 0x00012000, -+ 0x013, 0x000287b7, -+ 0x013, 0x000247ab, -+ 0x013, 0x0002079f, -+ 0x013, 0x0001c793, -+ 0x013, 0x0001839b, -+ 0x013, 0x00014392, -+ 0x013, 0x0001019a, -+ 0x013, 0x0000c191, -+ 0x013, 0x00008194, -+ 0x013, 0x000040a0, -+ 0x013, 0x00000018, -+ 0x015, 0x0000f424, -+ 0x015, 0x0004f424, -+ 0x015, 0x0008f424, -+ 0x016, 0x000e1330, -+ 0x016, 0x000a1330, -+ 0x016, 0x00061330, -+ 0x016, 0x00021330, -+ 0x018, 0x00017524, -+ 0x000, 0x00070000, -+ 0x012, 0x000cf000, -+ 0x012, 0x000bc000, -+ 0x012, 0x00078000, -+ 0x012, 0x00000000, -+ 0x013, 0x000287bf, -+ 0x013, 0x000247b3, -+ 0x013, 0x000207a7, -+ 0x013, 0x0001c79b, -+ 0x013, 0x0001839f, -+ 0x013, 0x00014393, -+ 0x013, 0x00010399, -+ 0x013, 0x0000c38d, -+ 0x013, 0x00008199, -+ 0x013, 0x0000418d, -+ 0x013, 0x00000099, -+ 0x015, 0x0000f495, -+ 0x015, 0x0004f495, -+ 0x015, 0x0008f495, -+ 0x016, 0x000e1874, -+ 0x016, 0x000a1874, -+ 0x016, 0x00061874, -+ 0x016, 0x00021874, -+ 0x018, 0x00037564, -+ 0x000, 0x00070000, -+ 0x012, 0x000cf000, -+ 0x012, 0x000bc000, -+ 0x012, 0x00078000, -+ 0x012, 0x00000000, -+ 0x013, 0x000287bf, -+ 0x013, 0x000247b3, -+ 0x013, 0x000207a7, -+ 0x013, 0x0001c79b, -+ 0x013, 0x0001839f, -+ 0x013, 0x00014393, -+ 0x013, 0x00010399, -+ 0x013, 0x0000c38d, -+ 0x013, 0x00008199, -+ 0x013, 0x0000418d, -+ 0x013, 0x00000099, -+ 0x015, 0x0000f495, -+ 0x015, 0x0004f495, -+ 0x015, 0x0008f495, -+ 0x016, 0x000e1874, -+ 0x016, 0x000a1874, -+ 0x016, 0x00061874, -+ 0x016, 0x00021874, -+ 0x018, 0x00057595, -+ 0x000, 0x00070000, -+ 0x012, 0x000cf000, -+ 0x012, 0x000bc000, -+ 0x012, 0x00078000, -+ 0x012, 0x00000000, -+ 0x013, 0x000287bf, -+ 0x013, 0x000247b3, -+ 0x013, 0x000207a7, -+ 0x013, 0x0001c79b, -+ 0x013, 0x0001839f, -+ 0x013, 0x00014393, -+ 0x013, 0x00010399, -+ 0x013, 0x0000c38d, -+ 0x013, 0x00008199, -+ 0x013, 0x0000418d, -+ 0x013, 0x00000099, -+ 0x015, 0x0000f495, -+ 0x015, 0x0004f495, -+ 0x015, 0x0008f495, -+ 0x016, 0x000e1874, -+ 0x016, 0x000a1874, -+ 0x016, 0x00061874, -+ 0x016, 0x00021874, -+ 0x030, 0x0004470f, -+ 0x031, 0x00044ff0, -+ 0x032, 0x00000070, -+ 0x033, 0x000dd480, -+ 0x034, 0x000ffac0, -+ 0x035, 0x000b80c0, -+ 0x036, 0x00077000, -+ 0x037, 0x00064ff2, -+ 0x038, 0x000e7661, -+ 0x039, 0x00000e90, -+ 0x000, 0x00030000, -+ 0x018, 0x0000f401, -+ 0x0fe, 0x00000000, -+ 0x0fe, 0x00000000, -+ 0x01e, 0x00088009, -+ 0x01f, 0x00080003, -+ 0x0fe, 0x00000000, -+ 0x01e, 0x00088001, -+ 0x01f, 0x00080000, -+ 0x0fe, 0x00000000, -+ 0x018, 0x00087401, -+ 0x0fe, 0x00000000, -+ 0x0fe, 0x00000000, -+ 0x0fe, 0x00000000, -+ 0x02b, 0x00041289, -+ 0x0fe, 0x00000000, -+ 0x02d, 0x00066666, -+ 0x02e, 0x00064001, -+ 0x02d, 0x00091111, -+ 0x02e, 0x00014002, -+ 0x02d, 0x000bbbbb, -+ 0x02e, 0x000b4003, -+ 0x02d, 0x000e6666, -+ 0x02e, 0x00064004, -+ 0x02d, 0x00088888, -+ 0x02e, 0x00084005, -+ 0x02d, 0x0009dddd, -+ 0x02e, 0x000d4006, -+ 0x02d, 0x000b3333, -+ 0x02e, 0x00034007, -+ 0x02d, 0x00048888, -+ 0x02e, 0x00084408, -+ 0x02d, 0x000bbbbb, -+ 0x02e, 0x000b4409, -+ 0x02d, 0x000e6666, -+ 0x02e, 0x0006440a, -+ 0x02d, 0x00011111, -+ 0x02e, 0x0001480b, -+ 0x02d, 0x0003bbbb, -+ 0x02e, 0x000b480c, -+ 0x02d, 0x00066666, -+ 0x02e, 0x0006480d, -+ 0x02d, 0x000ccccc, -+ 0x02e, 0x000c480e, -+}; -+ -+const u32 rtl8192du_mac_2tarray[MAC_2T_ARRAYLENGTH] = { -+ 0x420, 0x00000080, -+ 0x423, 0x00000000, -+ 0x430, 0x00000000, -+ 0x431, 0x00000000, -+ 0x432, 0x00000000, -+ 0x433, 0x00000001, -+ 0x434, 0x00000004, -+ 0x435, 0x00000005, -+ 0x436, 0x00000006, -+ 0x437, 0x00000007, -+ 0x438, 0x00000000, -+ 0x439, 0x00000000, -+ 0x43a, 0x00000000, -+ 0x43b, 0x00000001, -+ 0x43c, 0x00000004, -+ 0x43d, 0x00000005, -+ 0x43e, 0x00000006, -+ 0x43f, 0x00000007, -+ 0x440, 0x00000050, -+ 0x441, 0x00000001, -+ 0x442, 0x00000000, -+ 0x444, 0x00000015, -+ 0x445, 0x000000f0, -+ 0x446, 0x0000000f, -+ 0x447, 0x00000000, -+ 0x462, 0x00000008, -+ 0x463, 0x00000003, -+ 0x4c8, 0x000000ff, -+ 0x4c9, 0x00000008, -+ 0x4cc, 0x000000ff, -+ 0x4cd, 0x000000ff, -+ 0x4ce, 0x00000001, -+ 0x500, 0x00000026, -+ 0x501, 0x000000a2, -+ 0x502, 0x0000002f, -+ 0x503, 0x00000000, -+ 0x504, 0x00000028, -+ 0x505, 0x000000a3, -+ 0x506, 0x0000005e, -+ 0x507, 0x00000000, -+ 0x508, 0x0000002b, -+ 0x509, 0x000000a4, -+ 0x50a, 0x0000005e, -+ 0x50b, 0x00000000, -+ 0x50c, 0x0000004f, -+ 0x50d, 0x000000a4, -+ 0x50e, 0x00000000, -+ 0x50f, 0x00000000, -+ 0x512, 0x0000001c, -+ 0x514, 0x0000000a, -+ 0x515, 0x00000010, -+ 0x516, 0x0000000a, -+ 0x517, 0x00000010, -+ 0x51a, 0x00000016, -+ 0x524, 0x0000000f, -+ 0x525, 0x0000004f, -+ 0x546, 0x00000040, -+ 0x547, 0x00000000, -+ 0x550, 0x00000010, -+ 0x551, 0x00000010, -+ 0x559, 0x00000002, -+ 0x55a, 0x00000002, -+ 0x55d, 0x000000ff, -+ 0x605, 0x00000080, -+ 0x608, 0x0000000e, -+ 0x609, 0x0000002a, -+ 0x652, 0x00000020, -+ 0x63c, 0x0000000a, -+ 0x63d, 0x0000000a, -+ 0x63e, 0x0000000e, -+ 0x63f, 0x0000000e, -+ 0x66e, 0x00000005, -+ 0x700, 0x00000021, -+ 0x701, 0x00000043, -+ 0x702, 0x00000065, -+ 0x703, 0x00000087, -+ 0x708, 0x00000021, -+ 0x709, 0x00000043, -+ 0x70a, 0x00000065, -+ 0x70b, 0x00000087, -+ 0x024, 0x0000000d, -+ 0x025, 0x00000080, -+ 0x026, 0x00000011, -+ 0x027, 0x00000000, -+ 0x028, 0x00000083, -+ 0x029, 0x000000db, -+ 0x02a, 0x000000ff, -+ 0x02b, 0x00000000, -+ 0x014, 0x00000055, -+ 0x015, 0x000000a9, -+ 0x016, 0x0000008b, -+ 0x017, 0x00000008, -+ 0x010, 0x00000003, -+ 0x011, 0x0000002b, -+ 0x012, 0x00000002, -+ 0x013, 0x00000049, -+}; -+ -+const u32 rtl8192du_agctab_array[AGCTAB_ARRAYLENGTH] = { -+ 0xc78, 0x7b000001, -+ 0xc78, 0x7b010001, -+ 0xc78, 0x7b020001, -+ 0xc78, 0x7b030001, -+ 0xc78, 0x7b040001, -+ 0xc78, 0x7b050001, -+ 0xc78, 0x7b060001, -+ 0xc78, 0x7a070001, -+ 0xc78, 0x79080001, -+ 0xc78, 0x78090001, -+ 0xc78, 0x770a0001, -+ 0xc78, 0x760b0001, -+ 0xc78, 0x750c0001, -+ 0xc78, 0x740d0001, -+ 0xc78, 0x730e0001, -+ 0xc78, 0x720f0001, -+ 0xc78, 0x71100001, -+ 0xc78, 0x70110001, -+ 0xc78, 0x6f120001, -+ 0xc78, 0x6e130001, -+ 0xc78, 0x6d140001, -+ 0xc78, 0x6c150001, -+ 0xc78, 0x6b160001, -+ 0xc78, 0x6a170001, -+ 0xc78, 0x69180001, -+ 0xc78, 0x68190001, -+ 0xc78, 0x671a0001, -+ 0xc78, 0x661b0001, -+ 0xc78, 0x651c0001, -+ 0xc78, 0x641d0001, -+ 0xc78, 0x631e0001, -+ 0xc78, 0x621f0001, -+ 0xc78, 0x61200001, -+ 0xc78, 0x60210001, -+ 0xc78, 0x49220001, -+ 0xc78, 0x48230001, -+ 0xc78, 0x47240001, -+ 0xc78, 0x46250001, -+ 0xc78, 0x45260001, -+ 0xc78, 0x44270001, -+ 0xc78, 0x43280001, -+ 0xc78, 0x42290001, -+ 0xc78, 0x412a0001, -+ 0xc78, 0x402b0001, -+ 0xc78, 0x262c0001, -+ 0xc78, 0x252d0001, -+ 0xc78, 0x242e0001, -+ 0xc78, 0x232f0001, -+ 0xc78, 0x22300001, -+ 0xc78, 0x21310001, -+ 0xc78, 0x20320001, -+ 0xc78, 0x06330001, -+ 0xc78, 0x05340001, -+ 0xc78, 0x04350001, -+ 0xc78, 0x03360001, -+ 0xc78, 0x02370001, -+ 0xc78, 0x01380001, -+ 0xc78, 0x00390001, -+ 0xc78, 0x003a0001, -+ 0xc78, 0x003b0001, -+ 0xc78, 0x003c0001, -+ 0xc78, 0x003d0001, -+ 0xc78, 0x003e0001, -+ 0xc78, 0x003f0001, -+ 0xc78, 0x7b400001, -+ 0xc78, 0x7b410001, -+ 0xc78, 0x7a420001, -+ 0xc78, 0x79430001, -+ 0xc78, 0x78440001, -+ 0xc78, 0x77450001, -+ 0xc78, 0x76460001, -+ 0xc78, 0x75470001, -+ 0xc78, 0x74480001, -+ 0xc78, 0x73490001, -+ 0xc78, 0x724a0001, -+ 0xc78, 0x714b0001, -+ 0xc78, 0x704c0001, -+ 0xc78, 0x6f4d0001, -+ 0xc78, 0x6e4e0001, -+ 0xc78, 0x6d4f0001, -+ 0xc78, 0x6c500001, -+ 0xc78, 0x6b510001, -+ 0xc78, 0x6a520001, -+ 0xc78, 0x69530001, -+ 0xc78, 0x68540001, -+ 0xc78, 0x67550001, -+ 0xc78, 0x66560001, -+ 0xc78, 0x65570001, -+ 0xc78, 0x64580001, -+ 0xc78, 0x63590001, -+ 0xc78, 0x625a0001, -+ 0xc78, 0x615b0001, -+ 0xc78, 0x605c0001, -+ 0xc78, 0x485d0001, -+ 0xc78, 0x475e0001, -+ 0xc78, 0x465f0001, -+ 0xc78, 0x45600001, -+ 0xc78, 0x44610001, -+ 0xc78, 0x43620001, -+ 0xc78, 0x42630001, -+ 0xc78, 0x41640001, -+ 0xc78, 0x40650001, -+ 0xc78, 0x27660001, -+ 0xc78, 0x26670001, -+ 0xc78, 0x25680001, -+ 0xc78, 0x24690001, -+ 0xc78, 0x236a0001, -+ 0xc78, 0x226b0001, -+ 0xc78, 0x216c0001, -+ 0xc78, 0x206d0001, -+ 0xc78, 0x206e0001, -+ 0xc78, 0x206f0001, -+ 0xc78, 0x20700001, -+ 0xc78, 0x20710001, -+ 0xc78, 0x20720001, -+ 0xc78, 0x20730001, -+ 0xc78, 0x20740001, -+ 0xc78, 0x20750001, -+ 0xc78, 0x20760001, -+ 0xc78, 0x20770001, -+ 0xc78, 0x20780001, -+ 0xc78, 0x20790001, -+ 0xc78, 0x207a0001, -+ 0xc78, 0x207b0001, -+ 0xc78, 0x207c0001, -+ 0xc78, 0x207d0001, -+ 0xc78, 0x207e0001, -+ 0xc78, 0x207f0001, -+ 0xc78, 0x38000002, -+ 0xc78, 0x38010002, -+ 0xc78, 0x38020002, -+ 0xc78, 0x38030002, -+ 0xc78, 0x38040002, -+ 0xc78, 0x38050002, -+ 0xc78, 0x38060002, -+ 0xc78, 0x38070002, -+ 0xc78, 0x38080002, -+ 0xc78, 0x3c090002, -+ 0xc78, 0x3e0a0002, -+ 0xc78, 0x400b0002, -+ 0xc78, 0x440c0002, -+ 0xc78, 0x480d0002, -+ 0xc78, 0x4c0e0002, -+ 0xc78, 0x500f0002, -+ 0xc78, 0x52100002, -+ 0xc78, 0x56110002, -+ 0xc78, 0x5a120002, -+ 0xc78, 0x5e130002, -+ 0xc78, 0x60140002, -+ 0xc78, 0x60150002, -+ 0xc78, 0x60160002, -+ 0xc78, 0x62170002, -+ 0xc78, 0x62180002, -+ 0xc78, 0x62190002, -+ 0xc78, 0x621a0002, -+ 0xc78, 0x621b0002, -+ 0xc78, 0x621c0002, -+ 0xc78, 0x621d0002, -+ 0xc78, 0x621e0002, -+ 0xc78, 0x621f0002, -+ 0xc78, 0x32000044, -+ 0xc78, 0x32010044, -+ 0xc78, 0x32020044, -+ 0xc78, 0x32030044, -+ 0xc78, 0x32040044, -+ 0xc78, 0x32050044, -+ 0xc78, 0x32060044, -+ 0xc78, 0x34070044, -+ 0xc78, 0x35080044, -+ 0xc78, 0x36090044, -+ 0xc78, 0x370a0044, -+ 0xc78, 0x380b0044, -+ 0xc78, 0x390c0044, -+ 0xc78, 0x3a0d0044, -+ 0xc78, 0x3e0e0044, -+ 0xc78, 0x420f0044, -+ 0xc78, 0x44100044, -+ 0xc78, 0x46110044, -+ 0xc78, 0x4a120044, -+ 0xc78, 0x4e130044, -+ 0xc78, 0x50140044, -+ 0xc78, 0x55150044, -+ 0xc78, 0x5a160044, -+ 0xc78, 0x5e170044, -+ 0xc78, 0x64180044, -+ 0xc78, 0x6e190044, -+ 0xc78, 0x6e1a0044, -+ 0xc78, 0x6e1b0044, -+ 0xc78, 0x6e1c0044, -+ 0xc78, 0x6e1d0044, -+ 0xc78, 0x6e1e0044, -+ 0xc78, 0x6e1f0044, -+ 0xc78, 0x6e1f0000, -+}; -+ -+const u32 rtl8192du_agctab_5garray[AGCTAB_5G_ARRAYLENGTH] = { -+ 0xc78, 0x7b000001, -+ 0xc78, 0x7b010001, -+ 0xc78, 0x7a020001, -+ 0xc78, 0x79030001, -+ 0xc78, 0x78040001, -+ 0xc78, 0x77050001, -+ 0xc78, 0x76060001, -+ 0xc78, 0x75070001, -+ 0xc78, 0x74080001, -+ 0xc78, 0x73090001, -+ 0xc78, 0x720a0001, -+ 0xc78, 0x710b0001, -+ 0xc78, 0x700c0001, -+ 0xc78, 0x6f0d0001, -+ 0xc78, 0x6e0e0001, -+ 0xc78, 0x6d0f0001, -+ 0xc78, 0x6c100001, -+ 0xc78, 0x6b110001, -+ 0xc78, 0x6a120001, -+ 0xc78, 0x69130001, -+ 0xc78, 0x68140001, -+ 0xc78, 0x67150001, -+ 0xc78, 0x66160001, -+ 0xc78, 0x65170001, -+ 0xc78, 0x64180001, -+ 0xc78, 0x63190001, -+ 0xc78, 0x621a0001, -+ 0xc78, 0x611b0001, -+ 0xc78, 0x601c0001, -+ 0xc78, 0x481d0001, -+ 0xc78, 0x471e0001, -+ 0xc78, 0x461f0001, -+ 0xc78, 0x45200001, -+ 0xc78, 0x44210001, -+ 0xc78, 0x43220001, -+ 0xc78, 0x42230001, -+ 0xc78, 0x41240001, -+ 0xc78, 0x40250001, -+ 0xc78, 0x27260001, -+ 0xc78, 0x26270001, -+ 0xc78, 0x25280001, -+ 0xc78, 0x24290001, -+ 0xc78, 0x232a0001, -+ 0xc78, 0x222b0001, -+ 0xc78, 0x212c0001, -+ 0xc78, 0x202d0001, -+ 0xc78, 0x202e0001, -+ 0xc78, 0x202f0001, -+ 0xc78, 0x20300001, -+ 0xc78, 0x20310001, -+ 0xc78, 0x20320001, -+ 0xc78, 0x20330001, -+ 0xc78, 0x20340001, -+ 0xc78, 0x20350001, -+ 0xc78, 0x20360001, -+ 0xc78, 0x20370001, -+ 0xc78, 0x20380001, -+ 0xc78, 0x20390001, -+ 0xc78, 0x203a0001, -+ 0xc78, 0x203b0001, -+ 0xc78, 0x203c0001, -+ 0xc78, 0x203d0001, -+ 0xc78, 0x203e0001, -+ 0xc78, 0x203f0001, -+ 0xc78, 0x32000044, -+ 0xc78, 0x32010044, -+ 0xc78, 0x32020044, -+ 0xc78, 0x32030044, -+ 0xc78, 0x32040044, -+ 0xc78, 0x32050044, -+ 0xc78, 0x32060044, -+ 0xc78, 0x34070044, -+ 0xc78, 0x35080044, -+ 0xc78, 0x36090044, -+ 0xc78, 0x370a0044, -+ 0xc78, 0x380b0044, -+ 0xc78, 0x390c0044, -+ 0xc78, 0x3a0d0044, -+ 0xc78, 0x3e0e0044, -+ 0xc78, 0x420f0044, -+ 0xc78, 0x44100044, -+ 0xc78, 0x46110044, -+ 0xc78, 0x4a120044, -+ 0xc78, 0x4e130044, -+ 0xc78, 0x50140044, -+ 0xc78, 0x55150044, -+ 0xc78, 0x5a160044, -+ 0xc78, 0x5e170044, -+ 0xc78, 0x64180044, -+ 0xc78, 0x6e190044, -+ 0xc78, 0x6e1a0044, -+ 0xc78, 0x6e1b0044, -+ 0xc78, 0x6e1c0044, -+ 0xc78, 0x6e1d0044, -+ 0xc78, 0x6e1e0044, -+ 0xc78, 0x6e1f0044, -+ 0xc78, 0x6e1f0000, -+}; -+ -+const u32 rtl8192du_agctab_2garray[AGCTAB_2G_ARRAYLENGTH] = { -+ 0xc78, 0x7b000001, -+ 0xc78, 0x7b010001, -+ 0xc78, 0x7b020001, -+ 0xc78, 0x7b030001, -+ 0xc78, 0x7b040001, -+ 0xc78, 0x7b050001, -+ 0xc78, 0x7b060001, -+ 0xc78, 0x7a070001, -+ 0xc78, 0x79080001, -+ 0xc78, 0x78090001, -+ 0xc78, 0x770a0001, -+ 0xc78, 0x760b0001, -+ 0xc78, 0x750c0001, -+ 0xc78, 0x740d0001, -+ 0xc78, 0x730e0001, -+ 0xc78, 0x720f0001, -+ 0xc78, 0x71100001, -+ 0xc78, 0x70110001, -+ 0xc78, 0x6f120001, -+ 0xc78, 0x6e130001, -+ 0xc78, 0x6d140001, -+ 0xc78, 0x6c150001, -+ 0xc78, 0x6b160001, -+ 0xc78, 0x6a170001, -+ 0xc78, 0x69180001, -+ 0xc78, 0x68190001, -+ 0xc78, 0x671a0001, -+ 0xc78, 0x661b0001, -+ 0xc78, 0x651c0001, -+ 0xc78, 0x641d0001, -+ 0xc78, 0x631e0001, -+ 0xc78, 0x621f0001, -+ 0xc78, 0x61200001, -+ 0xc78, 0x60210001, -+ 0xc78, 0x49220001, -+ 0xc78, 0x48230001, -+ 0xc78, 0x47240001, -+ 0xc78, 0x46250001, -+ 0xc78, 0x45260001, -+ 0xc78, 0x44270001, -+ 0xc78, 0x43280001, -+ 0xc78, 0x42290001, -+ 0xc78, 0x412a0001, -+ 0xc78, 0x402b0001, -+ 0xc78, 0x262c0001, -+ 0xc78, 0x252d0001, -+ 0xc78, 0x242e0001, -+ 0xc78, 0x232f0001, -+ 0xc78, 0x22300001, -+ 0xc78, 0x21310001, -+ 0xc78, 0x20320001, -+ 0xc78, 0x06330001, -+ 0xc78, 0x05340001, -+ 0xc78, 0x04350001, -+ 0xc78, 0x03360001, -+ 0xc78, 0x02370001, -+ 0xc78, 0x01380001, -+ 0xc78, 0x00390001, -+ 0xc78, 0x003a0001, -+ 0xc78, 0x003b0001, -+ 0xc78, 0x003c0001, -+ 0xc78, 0x003d0001, -+ 0xc78, 0x003e0001, -+ 0xc78, 0x003f0001, -+ 0xc78, 0x38000002, -+ 0xc78, 0x38010002, -+ 0xc78, 0x38020002, -+ 0xc78, 0x38030002, -+ 0xc78, 0x38040002, -+ 0xc78, 0x38050002, -+ 0xc78, 0x38060002, -+ 0xc78, 0x38070002, -+ 0xc78, 0x38080002, -+ 0xc78, 0x3c090002, -+ 0xc78, 0x3e0a0002, -+ 0xc78, 0x400b0002, -+ 0xc78, 0x440c0002, -+ 0xc78, 0x480d0002, -+ 0xc78, 0x4c0e0002, -+ 0xc78, 0x500f0002, -+ 0xc78, 0x52100002, -+ 0xc78, 0x56110002, -+ 0xc78, 0x5a120002, -+ 0xc78, 0x5e130002, -+ 0xc78, 0x60140002, -+ 0xc78, 0x60150002, -+ 0xc78, 0x60160002, -+ 0xc78, 0x62170002, -+ 0xc78, 0x62180002, -+ 0xc78, 0x62190002, -+ 0xc78, 0x621a0002, -+ 0xc78, 0x621b0002, -+ 0xc78, 0x621c0002, -+ 0xc78, 0x621d0002, -+ 0xc78, 0x621e0002, -+ 0xc78, 0x621f0002, -+ 0xc78, 0x6e1f0000, -+}; -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/table.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/table.h -new file mode 100644 -index 000000000000..b809ba511320 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/table.h -@@ -0,0 +1,29 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#ifndef __RTL92DU_TABLE_H__ -+#define __RTL92DU_TABLE_H__ -+ -+#define PHY_REG_2T_ARRAYLENGTH 372 -+#define PHY_REG_ARRAY_PG_LENGTH 624 -+#define RADIOA_2T_ARRAYLENGTH 378 -+#define RADIOB_2T_ARRAYLENGTH 384 -+#define RADIOA_2T_INT_PA_ARRAYLENGTH 378 -+#define RADIOB_2T_INT_PA_ARRAYLENGTH 384 -+#define MAC_2T_ARRAYLENGTH 192 -+#define AGCTAB_ARRAYLENGTH 386 -+#define AGCTAB_5G_ARRAYLENGTH 194 -+#define AGCTAB_2G_ARRAYLENGTH 194 -+ -+extern const u32 rtl8192du_phy_reg_2tarray[PHY_REG_2T_ARRAYLENGTH]; -+extern const u32 rtl8192du_phy_reg_array_pg[PHY_REG_ARRAY_PG_LENGTH]; -+extern const u32 rtl8192du_radioa_2tarray[RADIOA_2T_ARRAYLENGTH]; -+extern const u32 rtl8192du_radiob_2tarray[RADIOB_2T_ARRAYLENGTH]; -+extern const u32 rtl8192du_radioa_2t_int_paarray[RADIOA_2T_INT_PA_ARRAYLENGTH]; -+extern const u32 rtl8192du_radiob_2t_int_paarray[RADIOB_2T_INT_PA_ARRAYLENGTH]; -+extern const u32 rtl8192du_mac_2tarray[MAC_2T_ARRAYLENGTH]; -+extern const u32 rtl8192du_agctab_array[AGCTAB_ARRAYLENGTH]; -+extern const u32 rtl8192du_agctab_5garray[AGCTAB_5G_ARRAYLENGTH]; -+extern const u32 rtl8192du_agctab_2garray[AGCTAB_2G_ARRAYLENGTH]; -+ -+#endif --- -2.34.1 - diff --git a/packages/linux/patches/rtlwifi/6.11/0003-6.11-wifi-rtlwifi-Add-new-members-to-struct-.patch b/packages/linux/patches/rtlwifi/6.11/0003-6.11-wifi-rtlwifi-Add-new-members-to-struct-.patch deleted file mode 100644 index e54b44831f..0000000000 --- a/packages/linux/patches/rtlwifi/6.11/0003-6.11-wifi-rtlwifi-Add-new-members-to-struct-.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 34ddbe7398b1e23d78192999dcc88a7f57bcaae5 Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 23 May 2024 17:44:39 +0300 -Subject: [PATCH 03/12] 6.11: wifi: rtlwifi: Add new members to struct - rtl_priv for RTL8192DU - -These are needed for the dual MAC version of RTL8192DU. - -The two mutexes are used to avoid concurrent access to the hardware -from the two USB interfaces. - -The two arrays are filled by one interface during LC calibration and -accessed by the other interface during channel switching. - -Signed-off-by: Bitterblue Smith ---- - drivers/net/wireless/realtek/rtlwifi/wifi.h | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h -index 4f1c21c130f4..2e88359ba917 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/wifi.h -+++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h -@@ -2773,6 +2773,12 @@ struct rtl_priv { - */ - bool use_new_trx_flow; - -+ /* For dual MAC RTL8192DU, things shared by the 2 USB interfaces */ -+ u32 *curveindex_2g; -+ u32 *curveindex_5g; -+ struct mutex *mutex_for_power_on_off; /* for power on/off */ -+ struct mutex *mutex_for_hw_init; /* for hardware init */ -+ - #ifdef CONFIG_PM - struct wiphy_wowlan_support wowlan; - #endif --- -2.34.1 - diff --git a/packages/linux/patches/rtlwifi/6.11/0004-6.11-wifi-rtlwifi-Add-rtl8192du-hw.-c-h.patch b/packages/linux/patches/rtlwifi/6.11/0004-6.11-wifi-rtlwifi-Add-rtl8192du-hw.-c-h.patch deleted file mode 100644 index c517f267eb..0000000000 --- a/packages/linux/patches/rtlwifi/6.11/0004-6.11-wifi-rtlwifi-Add-rtl8192du-hw.-c-h.patch +++ /dev/null @@ -1,1264 +0,0 @@ -From 37626e4f236435875f40fd3e8a463aac1cd47c8b Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 23 May 2024 17:45:31 +0300 -Subject: [PATCH 04/12] 6.11: wifi: rtlwifi: Add rtl8192du/hw.{c,h} - -These contain mostly hardware init/deinit routines for RTL8192DU. - -Signed-off-by: Bitterblue Smith ---- - .../wireless/realtek/rtlwifi/rtl8192du/hw.c | 1212 +++++++++++++++++ - .../wireless/realtek/rtlwifi/rtl8192du/hw.h | 22 + - 2 files changed, 1234 insertions(+) - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/hw.c - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/hw.h - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/hw.c -new file mode 100644 -index 000000000000..700c6e2bcad1 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/hw.c -@@ -0,0 +1,1212 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#include "../wifi.h" -+#include "../cam.h" -+#include "../usb.h" -+#include "../rtl8192d/reg.h" -+#include "../rtl8192d/def.h" -+#include "../rtl8192d/dm_common.h" -+#include "../rtl8192d/fw_common.h" -+#include "../rtl8192d/hw_common.h" -+#include "../rtl8192d/phy_common.h" -+#include "phy.h" -+#include "dm.h" -+#include "fw.h" -+#include "hw.h" -+#include "trx.h" -+ -+static void _rtl92du_set_bcn_ctrl_reg(struct ieee80211_hw *hw, -+ u8 set_bits, u8 clear_bits) -+{ -+ struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ rtlusb->reg_bcn_ctrl_val |= set_bits; -+ rtlusb->reg_bcn_ctrl_val &= ~clear_bits; -+ rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val); -+} -+ -+static void _rtl92du_enable_bcn_sub_func(struct ieee80211_hw *hw) -+{ -+ _rtl92du_set_bcn_ctrl_reg(hw, 0, BIT(1)); -+} -+ -+static void _rtl92du_disable_bcn_sub_func(struct ieee80211_hw *hw) -+{ -+ _rtl92du_set_bcn_ctrl_reg(hw, BIT(1), 0); -+} -+ -+void rtl92du_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) -+{ -+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -+ -+ switch (variable) { -+ case HW_VAR_RCR: -+ *((u32 *)val) = mac->rx_conf; -+ break; -+ default: -+ rtl92d_get_hw_reg(hw, variable, val); -+ break; -+ } -+} -+ -+void rtl92du_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_mac *mac = rtl_mac(rtlpriv); -+ -+ switch (variable) { -+ case HW_VAR_AC_PARAM: -+ rtl92d_dm_init_edca_turbo(hw); -+ break; -+ case HW_VAR_ACM_CTRL: { -+ u8 e_aci = *val; -+ union aci_aifsn *p_aci_aifsn = -+ (union aci_aifsn *)(&mac->ac[0].aifs); -+ u8 acm = p_aci_aifsn->f.acm; -+ u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); -+ -+ if (acm) { -+ switch (e_aci) { -+ case AC0_BE: -+ acm_ctrl |= ACMHW_BEQEN; -+ break; -+ case AC2_VI: -+ acm_ctrl |= ACMHW_VIQEN; -+ break; -+ case AC3_VO: -+ acm_ctrl |= ACMHW_VOQEN; -+ break; -+ default: -+ rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, -+ "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n", -+ acm); -+ break; -+ } -+ } else { -+ switch (e_aci) { -+ case AC0_BE: -+ acm_ctrl &= (~ACMHW_BEQEN); -+ break; -+ case AC2_VI: -+ acm_ctrl &= (~ACMHW_VIQEN); -+ break; -+ case AC3_VO: -+ acm_ctrl &= (~ACMHW_VOQEN); -+ break; -+ default: -+ pr_err("%s:%d switch case %#x not processed\n", -+ __func__, __LINE__, e_aci); -+ break; -+ } -+ } -+ rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE, -+ "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", -+ acm_ctrl); -+ rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); -+ break; -+ } -+ case HW_VAR_RCR: -+ mac->rx_conf = ((u32 *)val)[0]; -+ rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf); -+ break; -+ case HW_VAR_H2C_FW_JOINBSSRPT: { -+ u8 tmp_regcr, tmp_reg422; -+ bool recover = false; -+ u8 mstatus = *val; -+ -+ if (mstatus == RT_MEDIA_CONNECT) { -+ rtlpriv->cfg->ops->set_hw_reg(hw, -+ HW_VAR_AID, NULL); -+ tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); -+ rtl_write_byte(rtlpriv, REG_CR + 1, -+ tmp_regcr | ENSWBCN); -+ _rtl92du_set_bcn_ctrl_reg(hw, 0, EN_BCN_FUNCTION); -+ _rtl92du_set_bcn_ctrl_reg(hw, DIS_TSF_UDT, 0); -+ tmp_reg422 = rtl_read_byte(rtlpriv, -+ REG_FWHW_TXQ_CTRL + 2); -+ if (tmp_reg422 & (EN_BCNQ_DL >> 16)) -+ recover = true; -+ rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, -+ tmp_reg422 & ~(EN_BCNQ_DL >> 16)); -+ -+ /* We don't implement FW LPS so this is not needed. */ -+ /* rtl92d_set_fw_rsvdpagepkt(hw, 0); */ -+ -+ _rtl92du_set_bcn_ctrl_reg(hw, EN_BCN_FUNCTION, 0); -+ _rtl92du_set_bcn_ctrl_reg(hw, 0, DIS_TSF_UDT); -+ if (recover) -+ rtl_write_byte(rtlpriv, -+ REG_FWHW_TXQ_CTRL + 2, -+ tmp_reg422); -+ rtl_write_byte(rtlpriv, REG_CR + 1, -+ tmp_regcr & ~ENSWBCN); -+ } -+ rtl92d_set_fw_joinbss_report_cmd(hw, (*val)); -+ break; -+ } -+ case HW_VAR_CORRECT_TSF: { -+ u8 btype_ibss = val[0]; -+ -+ if (btype_ibss) -+ rtl92d_stop_tx_beacon(hw); -+ _rtl92du_set_bcn_ctrl_reg(hw, 0, EN_BCN_FUNCTION); -+ rtl_write_dword(rtlpriv, REG_TSFTR, -+ (u32)(mac->tsf & 0xffffffff)); -+ rtl_write_dword(rtlpriv, REG_TSFTR + 4, -+ (u32)((mac->tsf >> 32) & 0xffffffff)); -+ _rtl92du_set_bcn_ctrl_reg(hw, EN_BCN_FUNCTION, 0); -+ if (btype_ibss) -+ rtl92d_resume_tx_beacon(hw); -+ -+ break; -+ } -+ case HW_VAR_KEEP_ALIVE: -+ /* Avoid "switch case not processed" error. RTL8192DU doesn't -+ * need to do anything here, maybe. -+ */ -+ break; -+ default: -+ rtl92d_set_hw_reg(hw, variable, val); -+ break; -+ } -+} -+ -+static void _rtl92du_init_queue_reserved_page(struct ieee80211_hw *hw, -+ u8 out_ep_num, -+ u8 queue_sel) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ u32 txqpagenum, txqpageunit; -+ u32 txqremainingpage; -+ u32 numhq = 0; -+ u32 numlq = 0; -+ u32 numnq = 0; -+ u32 numpubq; -+ u32 value32; -+ -+ if (rtlhal->macphymode != SINGLEMAC_SINGLEPHY) { -+ numpubq = NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC; -+ txqpagenum = TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC - numpubq; -+ } else { -+ numpubq = TEST_PAGE_NUM_PUBQ_92DU; -+ txqpagenum = TX_TOTAL_PAGE_NUMBER_92DU - numpubq; -+ } -+ -+ if (rtlhal->macphymode != SINGLEMAC_SINGLEPHY && out_ep_num == 3) { -+ numhq = NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC; -+ numlq = NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC; -+ numnq = NORMAL_PAGE_NUM_NORMALQ_92D_DUAL_MAC; -+ } else { -+ txqpageunit = txqpagenum / out_ep_num; -+ txqremainingpage = txqpagenum % out_ep_num; -+ -+ if (queue_sel & TX_SELE_HQ) -+ numhq = txqpageunit; -+ if (queue_sel & TX_SELE_LQ) -+ numlq = txqpageunit; -+ if (queue_sel & TX_SELE_NQ) -+ numnq = txqpageunit; -+ -+ /* HIGH priority queue always present in the -+ * configuration of 2 or 3 out-ep. Remainder pages -+ * assigned to High queue -+ */ -+ if (out_ep_num > 1 && txqremainingpage) -+ numhq += txqremainingpage; -+ } -+ -+ /* NOTE: This step done before writing REG_RQPN. */ -+ rtl_write_byte(rtlpriv, REG_RQPN_NPQ, (u8)numnq); -+ -+ /* TX DMA */ -+ u32p_replace_bits(&value32, numhq, HPQ_MASK); -+ u32p_replace_bits(&value32, numlq, LPQ_MASK); -+ u32p_replace_bits(&value32, numpubq, PUBQ_MASK); -+ value32 |= LD_RQPN; -+ rtl_write_dword(rtlpriv, REG_RQPN, value32); -+} -+ -+static void _rtl92du_init_tx_buffer_boundary(struct ieee80211_hw *hw, -+ u8 txpktbuf_bndy) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); -+ rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); -+ -+ rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy); -+ -+ /* TXRKTBUG_PG_BNDY */ -+ rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy); -+ -+ /* Beacon Head for TXDMA */ -+ rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy); -+} -+ -+static bool _rtl92du_llt_table_init(struct ieee80211_hw *hw, u8 txpktbuf_bndy) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ unsigned short i; -+ bool status; -+ u8 maxpage; -+ -+ if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) -+ maxpage = 255; -+ else -+ maxpage = 127; -+ -+ for (i = 0; i < (txpktbuf_bndy - 1); i++) { -+ status = rtl92d_llt_write(hw, i, i + 1); -+ if (!status) -+ return status; -+ } -+ -+ /* end of list */ -+ status = rtl92d_llt_write(hw, txpktbuf_bndy - 1, 0xFF); -+ if (!status) -+ return status; -+ -+ /* Make the other pages as ring buffer -+ * This ring buffer is used as beacon buffer if we -+ * config this MAC as two MAC transfer. -+ * Otherwise used as local loopback buffer. -+ */ -+ for (i = txpktbuf_bndy; i < maxpage; i++) { -+ status = rtl92d_llt_write(hw, i, i + 1); -+ if (!status) -+ return status; -+ } -+ -+ /* Let last entry point to the start entry of ring buffer */ -+ status = rtl92d_llt_write(hw, maxpage, txpktbuf_bndy); -+ if (!status) -+ return status; -+ -+ return true; -+} -+ -+static void _rtl92du_init_chipn_reg_priority(struct ieee80211_hw *hw, u16 beq, -+ u16 bkq, u16 viq, u16 voq, -+ u16 mgtq, u16 hiq) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u16 value16; -+ -+ value16 = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7; -+ u16p_replace_bits(&value16, beq, TXDMA_BEQ_MAP); -+ u16p_replace_bits(&value16, bkq, TXDMA_BKQ_MAP); -+ u16p_replace_bits(&value16, viq, TXDMA_VIQ_MAP); -+ u16p_replace_bits(&value16, voq, TXDMA_VOQ_MAP); -+ u16p_replace_bits(&value16, mgtq, TXDMA_MGQ_MAP); -+ u16p_replace_bits(&value16, hiq, TXDMA_HIQ_MAP); -+ rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16); -+} -+ -+static void _rtl92du_init_chipn_one_out_ep_priority(struct ieee80211_hw *hw, -+ u8 queue_sel) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u16 value; -+ -+ switch (queue_sel) { -+ case TX_SELE_HQ: -+ value = QUEUE_HIGH; -+ break; -+ case TX_SELE_LQ: -+ value = QUEUE_LOW; -+ break; -+ case TX_SELE_NQ: -+ value = QUEUE_NORMAL; -+ break; -+ default: -+ WARN_ON(1); /* Shall not reach here! */ -+ return; -+ } -+ _rtl92du_init_chipn_reg_priority(hw, value, value, value, value, -+ value, value); -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "Tx queue select: 0x%02x\n", queue_sel); -+} -+ -+static void _rtl92du_init_chipn_two_out_ep_priority(struct ieee80211_hw *hw, -+ u8 queue_sel) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u16 beq, bkq, viq, voq, mgtq, hiq; -+ u16 valuehi, valuelow; -+ -+ switch (queue_sel) { -+ default: -+ WARN_ON(1); -+ fallthrough; -+ case (TX_SELE_HQ | TX_SELE_LQ): -+ valuehi = QUEUE_HIGH; -+ valuelow = QUEUE_LOW; -+ break; -+ case (TX_SELE_NQ | TX_SELE_LQ): -+ valuehi = QUEUE_NORMAL; -+ valuelow = QUEUE_LOW; -+ break; -+ case (TX_SELE_HQ | TX_SELE_NQ): -+ valuehi = QUEUE_HIGH; -+ valuelow = QUEUE_NORMAL; -+ break; -+ } -+ -+ beq = valuelow; -+ bkq = valuelow; -+ viq = valuehi; -+ voq = valuehi; -+ mgtq = valuehi; -+ hiq = valuehi; -+ -+ _rtl92du_init_chipn_reg_priority(hw, beq, bkq, viq, voq, mgtq, hiq); -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "Tx queue select: 0x%02x\n", queue_sel); -+} -+ -+static void _rtl92du_init_chipn_three_out_ep_priority(struct ieee80211_hw *hw, -+ u8 queue_sel) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u16 beq, bkq, viq, voq, mgtq, hiq; -+ -+ beq = QUEUE_LOW; -+ bkq = QUEUE_LOW; -+ viq = QUEUE_NORMAL; -+ voq = QUEUE_HIGH; -+ mgtq = QUEUE_HIGH; -+ hiq = QUEUE_HIGH; -+ -+ _rtl92du_init_chipn_reg_priority(hw, beq, bkq, viq, voq, mgtq, hiq); -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "Tx queue select: 0x%02x\n", queue_sel); -+} -+ -+static void _rtl92du_init_queue_priority(struct ieee80211_hw *hw, -+ u8 out_ep_num, -+ u8 queue_sel) -+{ -+ switch (out_ep_num) { -+ case 1: -+ _rtl92du_init_chipn_one_out_ep_priority(hw, queue_sel); -+ break; -+ case 2: -+ _rtl92du_init_chipn_two_out_ep_priority(hw, queue_sel); -+ break; -+ case 3: -+ _rtl92du_init_chipn_three_out_ep_priority(hw, queue_sel); -+ break; -+ default: -+ WARN_ON(1); /* Shall not reach here! */ -+ break; -+ } -+} -+ -+static void _rtl92du_init_wmac_setting(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_mac *mac = rtl_mac(rtlpriv); -+ -+ mac->rx_conf = RCR_APM | RCR_AM | RCR_AB | RCR_ADF | RCR_APP_ICV | -+ RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | -+ RCR_APP_PHYST_RXFF | RCR_APPFCS; -+ -+ rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf); -+ -+ /* Set Multicast Address. */ -+ rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); -+ rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); -+} -+ -+static void _rtl92du_init_adaptive_ctrl(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 val32; -+ -+ val32 = rtl_read_dword(rtlpriv, REG_RRSR); -+ val32 &= ~0xfffff; -+ if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) -+ val32 |= 0xffff0; /* No CCK */ -+ else -+ val32 |= 0xffff1; -+ rtl_write_dword(rtlpriv, REG_RRSR, val32); -+ -+ /* Set Spec SIFS (used in NAV) */ -+ rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010); -+ -+ /* Retry limit 0x30 */ -+ rtl_write_word(rtlpriv, REG_RL, 0x3030); -+} -+ -+static void _rtl92du_init_edca(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u16 val16; -+ -+ /* Disable EDCCA count down, to reduce collison and retry */ -+ val16 = rtl_read_word(rtlpriv, REG_RD_CTRL); -+ val16 |= DIS_EDCA_CNT_DWN; -+ rtl_write_word(rtlpriv, REG_RD_CTRL, val16); -+ -+ /* CCK SIFS shall always be 10us. */ -+ rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x0a0a); -+ /* Set SIFS for OFDM */ -+ rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010); -+ -+ rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0204); -+ -+ rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004); -+ -+ /* TXOP */ -+ rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B); -+ rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F); -+ rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324); -+ rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226); -+ -+ rtl_write_byte(rtlpriv, REG_PIFS, 0x1C); -+ -+ rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); -+ -+ rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); -+ -+ rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x2); -+ rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); -+} -+ -+static void _rtl92du_init_retry_function(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u8 val8; -+ -+ val8 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL); -+ val8 |= EN_AMPDU_RTY_NEW; -+ rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL, val8); -+ -+ rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); -+} -+ -+static void _rtl92du_init_operation_mode(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ -+ rtl_write_byte(rtlpriv, REG_BWOPMODE, BW_OPMODE_20MHZ); -+ -+ switch (rtlpriv->phy.rf_type) { -+ case RF_1T2R: -+ case RF_1T1R: -+ rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3); -+ break; -+ case RF_2T2R: -+ case RF_2T2R_GREEN: -+ rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3); -+ break; -+ } -+ rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, rtlhal->minspace_cfg); -+} -+ -+static void _rtl92du_init_beacon_parameters(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010); -+ -+ rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x3c02); -+ rtl_write_byte(rtlpriv, REG_DRVERLYINT, 0x05); -+ rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x03); -+ -+ rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); -+} -+ -+static void _rtl92du_init_ampdu_aggregation(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ -+ /* Aggregation threshold */ -+ if (rtlhal->macphymode == DUALMAC_DUALPHY) -+ rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66525541); -+ else if (rtlhal->macphymode == DUALMAC_SINGLEPHY) -+ rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x44444441); -+ else -+ rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x88728841); -+ -+ rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); -+} -+ -+static bool _rtl92du_init_power_on(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ unsigned short wordtmp; -+ unsigned char bytetmp; -+ u16 retry = 0; -+ -+ do { -+ if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) -+ break; -+ -+ if (retry++ > 1000) -+ return false; -+ } while (true); -+ -+ /* Unlock ISO/CLK/Power control register */ -+ rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); -+ -+ /* SPS0_CTRL 0x11[7:0] = 0x2b enable SPS into PWM mode */ -+ rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); -+ -+ msleep(1); -+ -+ bytetmp = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL); -+ if ((bytetmp & LDV12_EN) == 0) { -+ bytetmp |= LDV12_EN; -+ rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, bytetmp); -+ -+ msleep(1); -+ -+ bytetmp = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL); -+ bytetmp &= ~ISO_MD2PP; -+ rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, bytetmp); -+ } -+ -+ /* Auto enable WLAN */ -+ wordtmp = rtl_read_word(rtlpriv, REG_APS_FSMCO); -+ wordtmp |= APFM_ONMAC; -+ rtl_write_word(rtlpriv, REG_APS_FSMCO, wordtmp); -+ -+ wordtmp = rtl_read_word(rtlpriv, REG_APS_FSMCO); -+ retry = 0; -+ while ((wordtmp & APFM_ONMAC) && retry < 1000) { -+ retry++; -+ wordtmp = rtl_read_word(rtlpriv, REG_APS_FSMCO); -+ } -+ -+ /* Release RF digital isolation */ -+ wordtmp = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL); -+ wordtmp &= ~ISO_DIOR; -+ rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, wordtmp); -+ -+ /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ -+ wordtmp = rtl_read_word(rtlpriv, REG_CR); -+ wordtmp |= HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN | -+ PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC; -+ rtl_write_word(rtlpriv, REG_CR, wordtmp); -+ -+ return true; -+} -+ -+static bool _rtl92du_init_mac(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u8 val8; -+ -+ rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00); -+ -+ val8 = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); -+ val8 &= ~(FEN_MREGEN >> 8); -+ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, val8); -+ -+ /* For s3/s4 may reset mac, Reg0xf8 may be set to 0, -+ * so reset macphy control reg here. -+ */ -+ rtl92d_phy_config_macphymode(hw); -+ -+ rtl92du_phy_set_poweron(hw); -+ -+ if (!_rtl92du_init_power_on(hw)) { -+ pr_err("Failed to init power on!\n"); -+ return false; -+ } -+ -+ rtl92d_phy_config_maccoexist_rfpage(hw); -+ -+ return true; -+} -+ -+int rtl92du_hw_init(struct ieee80211_hw *hw) -+{ -+ struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw); -+ struct rtl_usb *rtlusb = rtl_usbdev(usb_priv); -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ struct rtl_mac *mac = rtl_mac(rtlpriv); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u8 val8, txpktbuf_bndy; -+ int err, i; -+ u32 val32; -+ u16 val16; -+ -+ mutex_lock(rtlpriv->mutex_for_hw_init); -+ -+ /* we should do iqk after disable/enable */ -+ rtl92d_phy_reset_iqk_result(hw); -+ -+ if (!_rtl92du_init_mac(hw)) { -+ pr_err("Init MAC failed\n"); -+ mutex_unlock(rtlpriv->mutex_for_hw_init); -+ return 1; -+ } -+ -+ if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) -+ txpktbuf_bndy = 249; -+ else -+ txpktbuf_bndy = 123; -+ -+ if (!_rtl92du_llt_table_init(hw, txpktbuf_bndy)) { -+ pr_err("Init LLT failed\n"); -+ mutex_unlock(rtlpriv->mutex_for_hw_init); -+ return 1; -+ } -+ -+ err = rtl92du_download_fw(hw); -+ -+ /* return fail only when part number check fail */ -+ if (err && rtl_read_byte(rtlpriv, 0x1c5) == 0xe0) { -+ rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, -+ "Failed to download FW. Init HW without FW..\n"); -+ mutex_unlock(rtlpriv->mutex_for_hw_init); -+ return 1; -+ } -+ rtlhal->last_hmeboxnum = 0; -+ rtlpriv->psc.fw_current_inpsmode = false; -+ -+ rtl92du_phy_mac_config(hw); -+ -+ /* Set reserved page for each queue */ -+ _rtl92du_init_queue_reserved_page(hw, rtlusb->out_ep_nums, -+ rtlusb->out_queue_sel); -+ -+ _rtl92du_init_tx_buffer_boundary(hw, txpktbuf_bndy); -+ -+ _rtl92du_init_queue_priority(hw, rtlusb->out_ep_nums, -+ rtlusb->out_queue_sel); -+ -+ /* Set Tx/Rx page size (Tx must be 128 Bytes, -+ * Rx can be 64, 128, 256, 512, 1024 bytes) -+ */ -+ rtl_write_byte(rtlpriv, REG_PBP, 0x11); -+ -+ /* Get Rx PHY status in order to report RSSI and others. */ -+ rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); -+ -+ rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); -+ rtl_write_dword(rtlpriv, REG_HIMR, 0xffffffff); -+ -+ val8 = rtl_read_byte(rtlpriv, MSR); -+ val8 &= ~MSR_MASK; -+ val8 |= MSR_INFRA; -+ rtl_write_byte(rtlpriv, MSR, val8); -+ -+ _rtl92du_init_wmac_setting(hw); -+ _rtl92du_init_adaptive_ctrl(hw); -+ _rtl92du_init_edca(hw); -+ -+ rtl_write_dword(rtlpriv, REG_DARFRC, 0x00000000); -+ rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x10080404); -+ rtl_write_dword(rtlpriv, REG_RARFRC, 0x04030201); -+ rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x08070605); -+ -+ _rtl92du_init_retry_function(hw); -+ /* _InitUsbAggregationSetting(padapter); no aggregation for now */ -+ _rtl92du_init_operation_mode(hw); -+ _rtl92du_init_beacon_parameters(hw); -+ _rtl92du_init_ampdu_aggregation(hw); -+ -+ rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); -+ -+ /* unit: 256us. 256ms */ -+ rtl_write_word(rtlpriv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); -+ rtl_write_word(rtlpriv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); -+ -+ /* Hardware-controlled blinking. */ -+ rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8282); -+ rtl_write_byte(rtlpriv, REG_LEDCFG2, 0x82); -+ -+ val32 = rtl_read_dword(rtlpriv, REG_TXDMA_OFFSET_CHK); -+ val32 |= DROP_DATA_EN; -+ rtl_write_dword(rtlpriv, REG_TXDMA_OFFSET_CHK, val32); -+ -+ if (mac->rdg_en) { -+ rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff); -+ rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200); -+ rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05); -+ } -+ -+ for (i = 0; i < 4; i++) -+ rtl_write_dword(rtlpriv, REG_ARFR0 + i * 4, 0x1f8ffff0); -+ -+ if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { -+ if (rtlusb->out_ep_nums == 2) -+ rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03066666); -+ else -+ rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x8888); -+ } else { -+ rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x5555); -+ } -+ -+ val8 = rtl_read_byte(rtlpriv, 0x605); -+ val8 |= 0xf0; -+ rtl_write_byte(rtlpriv, 0x605, val8); -+ -+ rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x30); -+ rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30); -+ rtl_write_byte(rtlpriv, 0x606, 0x30); -+ -+ /* temp for high queue and mgnt Queue corrupt in time; it may -+ * cause hang when sw beacon use high_Q, other frame use mgnt_Q; -+ * or, sw beacon use mgnt_Q, other frame use high_Q; -+ */ -+ rtl_write_byte(rtlpriv, REG_DIS_TXREQ_CLR, 0x10); -+ val16 = rtl_read_word(rtlpriv, REG_RD_CTRL); -+ val16 |= BIT(12); -+ rtl_write_word(rtlpriv, REG_RD_CTRL, val16); -+ -+ rtl_write_byte(rtlpriv, REG_TXPAUSE, 0); -+ -+ /* usb suspend idle time count for bitfile0927 */ -+ val8 = rtl_read_byte(rtlpriv, 0xfe56); -+ val8 |= BIT(0) | BIT(1); -+ rtl_write_byte(rtlpriv, 0xfe56, val8); -+ -+ if (rtlhal->earlymode_enable) { -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "EarlyMode Enabled!!!\n"); -+ -+ val8 = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL); -+ val8 |= 0x1f; -+ rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, val8); -+ -+ rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL + 3, 0x80); -+ -+ val8 = rtl_read_byte(rtlpriv, 0x605); -+ val8 |= 0x40; -+ rtl_write_byte(rtlpriv, 0x605, val8); -+ } else { -+ rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0); -+ } -+ -+ rtl92du_phy_bb_config(hw); -+ -+ rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; -+ /* set before initialize RF */ -+ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); -+ -+ /* config RF */ -+ rtl92du_phy_rf_config(hw); -+ -+ /* set default value after initialize RF */ -+ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); -+ -+ /* After load BB, RF params, we need to do more for 92D. */ -+ rtl92du_update_bbrf_configuration(hw); -+ -+ rtlphy->rfreg_chnlval[0] = -+ rtl_get_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK); -+ rtlphy->rfreg_chnlval[1] = -+ rtl_get_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK); -+ -+ /*---- Set CCK and OFDM Block "ON"----*/ -+ if (rtlhal->current_bandtype == BAND_ON_2_4G) -+ rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); -+ rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); -+ -+ /* reset hw sec */ -+ rtl_cam_reset_all_entry(hw); -+ rtl92d_enable_hw_security_config(hw); -+ -+ rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF); -+ -+ /* schmitt trigger, improve tx evm for 92du */ -+ val8 = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL); -+ val8 |= BIT(1); -+ rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, val8); -+ -+ /* Disable bar */ -+ rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0xffff); -+ -+ /* Nav limit */ -+ rtl_write_byte(rtlpriv, REG_NAV_CTRL + 2, 0); -+ rtl_write_byte(rtlpriv, ROFDM0_XATXAFE + 3, 0x50); -+ -+ /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct -+ * TX power index for different rate set. -+ */ -+ rtl92d_phy_get_hw_reg_originalvalue(hw); -+ -+ ppsc->rfpwr_state = ERFON; -+ -+ /* do IQK for 2.4G for better scan result */ -+ if (rtlhal->current_bandtype == BAND_ON_2_4G) -+ rtl92du_phy_iq_calibrate(hw); -+ -+ rtl92du_phy_lc_calibrate(hw, IS_92D_SINGLEPHY(rtlhal->version)); -+ -+ rtl92du_phy_init_pa_bias(hw); -+ -+ mutex_unlock(rtlpriv->mutex_for_hw_init); -+ -+ rtl92du_dm_init(hw); -+ -+ /* For 2 PORT TSF SYNC */ -+ rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1818); -+ rtlusb->reg_bcn_ctrl_val = 0x18; -+ -+ udelay(500); -+ -+ if (rtlhal->macphymode != DUALMAC_DUALPHY) { -+ rtl_write_dword(rtlpriv, RFPGA1_TXINFO, -+ rtl_read_dword(rtlpriv, RFPGA1_TXINFO) & ~BIT(30)); -+ -+ rtl_write_dword(rtlpriv, RFPGA0_TXGAINSTAGE, -+ rtl_read_dword(rtlpriv, RFPGA0_TXGAINSTAGE) & ~BIT(31)); -+ -+ rtl_write_dword(rtlpriv, ROFDM0_XBTXAFE, 0xa0e40000); -+ } -+ -+ val32 = rtl_read_dword(rtlpriv, REG_FWHW_TXQ_CTRL); -+ val32 |= BIT(12); -+ rtl_write_dword(rtlpriv, REG_FWHW_TXQ_CTRL, val32); -+ -+ return err; -+} -+ -+static int _rtl92du_set_media_status(struct ieee80211_hw *hw, -+ enum nl80211_iftype type) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ enum led_ctl_mode ledaction = LED_CTL_NO_LINK; -+ u8 bt_msr = rtl_read_byte(rtlpriv, MSR); -+ -+ bt_msr &= 0xfc; -+ -+ if (type == NL80211_IFTYPE_UNSPECIFIED || -+ type == NL80211_IFTYPE_STATION) { -+ rtl92d_stop_tx_beacon(hw); -+ _rtl92du_enable_bcn_sub_func(hw); -+ } else if (type == NL80211_IFTYPE_ADHOC || -+ type == NL80211_IFTYPE_AP) { -+ rtl92d_resume_tx_beacon(hw); -+ _rtl92du_disable_bcn_sub_func(hw); -+ } else { -+ rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, -+ "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n", -+ type); -+ } -+ -+ switch (type) { -+ case NL80211_IFTYPE_UNSPECIFIED: -+ bt_msr |= MSR_NOLINK; -+ ledaction = LED_CTL_LINK; -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, -+ "Set Network type to NO LINK!\n"); -+ break; -+ case NL80211_IFTYPE_ADHOC: -+ bt_msr |= MSR_ADHOC; -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, -+ "Set Network type to Ad Hoc!\n"); -+ break; -+ case NL80211_IFTYPE_STATION: -+ bt_msr |= MSR_INFRA; -+ ledaction = LED_CTL_LINK; -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, -+ "Set Network type to STA!\n"); -+ break; -+ case NL80211_IFTYPE_AP: -+ bt_msr |= MSR_AP; -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, -+ "Set Network type to AP!\n"); -+ break; -+ default: -+ pr_err("Network type %d not supported!\n", type); -+ return 1; -+ } -+ rtl_write_byte(rtlpriv, MSR, bt_msr); -+ -+ rtlpriv->cfg->ops->led_control(hw, ledaction); -+ -+ if ((bt_msr & MSR_MASK) == MSR_AP) -+ rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); -+ else -+ rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); -+ -+ return 0; -+} -+ -+void rtl92du_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 reg_rcr; -+ -+ if (rtlpriv->psc.rfpwr_state != ERFON) -+ return; -+ -+ rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr)); -+ -+ if (check_bssid) { -+ reg_rcr |= RCR_CBSSID_DATA | RCR_CBSSID_BCN; -+ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)®_rcr); -+ _rtl92du_set_bcn_ctrl_reg(hw, 0, DIS_TSF_UDT); -+ } else if (!check_bssid) { -+ reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN); -+ _rtl92du_set_bcn_ctrl_reg(hw, DIS_TSF_UDT, 0); -+ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)®_rcr); -+ } -+} -+ -+int rtl92du_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ if (_rtl92du_set_media_status(hw, type)) -+ return -EOPNOTSUPP; -+ -+ /* check bssid */ -+ if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { -+ if (type != NL80211_IFTYPE_AP) -+ rtl92du_set_check_bssid(hw, true); -+ } else { -+ rtl92du_set_check_bssid(hw, false); -+ } -+ -+ return 0; -+} -+ -+/* do iqk or reload iqk */ -+/* windows just rtl92d_phy_reload_iqk_setting in set channel, -+ * but it's very strict for time sequence so we add -+ * rtl92d_phy_reload_iqk_setting here -+ */ -+void rtl92du_linked_set_reg(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u8 channel = rtlphy->current_channel; -+ u8 indexforchannel; -+ -+ indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel); -+ if (!rtlphy->iqk_matrix[indexforchannel].iqk_done) { -+ rtl_dbg(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG, -+ "Do IQK for channel:%d\n", channel); -+ rtl92du_phy_iq_calibrate(hw); -+ } -+} -+ -+void rtl92du_enable_interrupt(struct ieee80211_hw *hw) -+{ -+ /* Nothing to do. */ -+} -+ -+void rtl92du_disable_interrupt(struct ieee80211_hw *hw) -+{ -+ /* Nothing to do. */ -+} -+ -+static void _rtl92du_poweroff_adapter(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u8 retry = 100; -+ u8 u1b_tmp; -+ u16 val16; -+ u32 val32; -+ -+ rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04); -+ -+ rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); -+ -+ /* IF fw in RAM code, do reset */ -+ if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & MCUFWDL_RDY) { -+ rtl_write_byte(rtlpriv, REG_FSIMR, 0); -+ -+ /* We need to disable other HRCV INT to influence 8051 reset. */ -+ rtl_write_byte(rtlpriv, REG_FWIMR, 0x20); -+ -+ /* Close mask to prevent incorrect FW write operation. */ -+ rtl_write_byte(rtlpriv, REG_FTIMR, 0); -+ -+ rtl_write_byte(rtlpriv, REG_MCUFWDL, 0); -+ -+ /* Set (REG_HMETFR + 3) to 0x20 is reset 8051 */ -+ rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20); -+ val16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); -+ while (val16 & FEN_CPUEN) { -+ retry--; -+ if (retry == 0) -+ break; -+ udelay(50); -+ val16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); -+ } -+ -+ if (retry == 0) { -+ rtl_write_byte(rtlpriv, REG_FWIMR, 0); -+ -+ /* if 8051 reset fail, reset MAC directly. */ -+ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x50); -+ -+ mdelay(10); -+ } -+ } -+ -+ /* reset MCU, MAC register, DCORE */ -+ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54); -+ -+ /* reset MCU ready status */ -+ rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); -+ -+ /* Pull GPIO PIN to balance level and LED control */ -+ -+ /* Disable GPIO[7:0] */ -+ rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL + 2, 0x0000); -+ val32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL); -+ u32p_replace_bits(&val32, val32 & 0xff, 0x0000ff00); -+ u32p_replace_bits(&val32, 0xff, 0x00ff0000); -+ rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, val32); -+ -+ /* Disable GPIO[10:8] */ -+ rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, 0); -+ val16 = rtl_read_word(rtlpriv, REG_GPIO_IO_SEL); -+ u16p_replace_bits(&val16, val16 & 0xf, 0x00f0); -+ u16p_replace_bits(&val16, 0xf, 0x0780); -+ rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, val16); -+ -+ /* Disable LED 0, 1, and 2 */ -+ rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8888); -+ rtl_write_byte(rtlpriv, REG_LEDCFG2, 0x88); -+ -+ /* Disable analog sequence */ -+ -+ /* enter PFM mode */ -+ rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23); -+ -+ rtl_write_word(rtlpriv, REG_APS_FSMCO, -+ APDM_HOST | AFSM_HSUS | PFM_ALDN); -+ -+ /* lock ISO/CLK/Power control register */ -+ rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e); -+ -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "In PowerOff,reg0x%x=%X\n", -+ REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL)); -+ -+ /* 0x17[7] 1b': power off in process 0b' : power off over */ -+ if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) { -+ mutex_lock(rtlpriv->mutex_for_power_on_off); -+ u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); -+ u1b_tmp &= ~BIT(7); -+ rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp); -+ mutex_unlock(rtlpriv->mutex_for_power_on_off); -+ } -+ -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n"); -+} -+ -+void rtl92du_card_disable(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -+ enum nl80211_iftype opmode; -+ u32 val32; -+ u16 val16; -+ u8 val8; -+ -+ mac->link_state = MAC80211_NOLINK; -+ opmode = NL80211_IFTYPE_UNSPECIFIED; -+ _rtl92du_set_media_status(hw, opmode); -+ -+ RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); -+ /* Power sequence for each MAC. */ -+ /* a. stop tx DMA */ -+ /* b. close RF */ -+ /* c. clear rx buf */ -+ /* d. stop rx DMA */ -+ /* e. reset MAC */ -+ -+ val16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG); -+ val16 &= ~BIT(12); -+ rtl_write_word(rtlpriv, REG_GPIO_MUXCFG, val16); -+ -+ rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xff); -+ udelay(500); -+ rtl_write_byte(rtlpriv, REG_CR, 0); -+ -+ /* RF OFF sequence */ -+ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x00); -+ -+ rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); -+ -+ val8 = FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTN; -+ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, val8); -+ -+ /* Mac0 can not do Global reset. Mac1 can do. */ -+ if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY || -+ rtlhal->interfaceindex == 1) { -+ /* before BB reset should do clock gated */ -+ val32 = rtl_read_dword(rtlpriv, RFPGA0_XCD_RFPARAMETER); -+ val32 |= BIT(31); -+ rtl_write_dword(rtlpriv, RFPGA0_XCD_RFPARAMETER, val32); -+ -+ val8 &= ~FEN_BB_GLB_RSTN; -+ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, val8); -+ } -+ -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n"); -+ if (!rtl92du_phy_check_poweroff(hw)) -+ return; -+ -+ _rtl92du_poweroff_adapter(hw); -+} -+ -+void rtl92du_set_beacon_related_registers(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_mac *mac = rtl_mac(rtlpriv); -+ u16 bcn_interval, atim_window; -+ -+ bcn_interval = mac->beacon_interval; -+ atim_window = 2; -+ rtl92du_disable_interrupt(hw); -+ rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); -+ rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); -+ rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); -+ rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20); -+ if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) -+ rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30); -+ else -+ rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20); -+ rtl_write_byte(rtlpriv, 0x606, 0x30); -+} -+ -+void rtl92du_set_beacon_interval(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -+ u16 bcn_interval = mac->beacon_interval; -+ -+ rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG, -+ "beacon_interval:%d\n", bcn_interval); -+ rtl92du_disable_interrupt(hw); -+ rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); -+ rtl92du_enable_interrupt(hw); -+} -+ -+void rtl92du_update_interrupt_mask(struct ieee80211_hw *hw, -+ u32 add_msr, u32 rm_msr) -+{ -+ /* Nothing to do here. */ -+} -+ -+void rtl92du_read_chip_version(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ /* Chip version reading is done in rtl92d_read_eeprom_info. */ -+ -+ rtlpriv->rtlhal.hw_type = HARDWARE_TYPE_RTL8192DU; -+} -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/hw.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/hw.h -new file mode 100644 -index 000000000000..80ed00c90c16 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/hw.h -@@ -0,0 +1,22 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#ifndef __RTL92DU_HW_H__ -+#define __RTL92DU_HW_H__ -+ -+void rtl92du_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); -+void rtl92du_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); -+void rtl92du_read_chip_version(struct ieee80211_hw *hw); -+int rtl92du_hw_init(struct ieee80211_hw *hw); -+void rtl92du_card_disable(struct ieee80211_hw *hw); -+void rtl92du_enable_interrupt(struct ieee80211_hw *hw); -+void rtl92du_disable_interrupt(struct ieee80211_hw *hw); -+int rtl92du_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type); -+void rtl92du_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid); -+void rtl92du_set_beacon_related_registers(struct ieee80211_hw *hw); -+void rtl92du_set_beacon_interval(struct ieee80211_hw *hw); -+void rtl92du_update_interrupt_mask(struct ieee80211_hw *hw, -+ u32 add_msr, u32 rm_msr); -+void rtl92du_linked_set_reg(struct ieee80211_hw *hw); -+ -+#endif --- -2.34.1 - diff --git a/packages/linux/patches/rtlwifi/6.11/0005-6.11-wifi-rtlwifi-Add-rtl8192du-phy.-c-h.patch b/packages/linux/patches/rtlwifi/6.11/0005-6.11-wifi-rtlwifi-Add-rtl8192du-phy.-c-h.patch deleted file mode 100644 index 9679b288fc..0000000000 --- a/packages/linux/patches/rtlwifi/6.11/0005-6.11-wifi-rtlwifi-Add-rtl8192du-phy.-c-h.patch +++ /dev/null @@ -1,3186 +0,0 @@ -From 40249d26740fceb059f121dde0922de1f9ec209a Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 23 May 2024 17:46:02 +0300 -Subject: [PATCH 05/12] 6.11: wifi: rtlwifi: Add rtl8192du/phy.{c,h} - -These contain mostly the calibration and channel switching routines -for RTL8192DU. - -Signed-off-by: Bitterblue Smith ---- - .../wireless/realtek/rtlwifi/rtl8192du/phy.c | 3123 +++++++++++++++++ - .../wireless/realtek/rtlwifi/rtl8192du/phy.h | 32 + - 2 files changed, 3155 insertions(+) - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.h - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c -new file mode 100644 -index 000000000000..289ec71ce3e5 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c -@@ -0,0 +1,3123 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#include "../wifi.h" -+#include "../ps.h" -+#include "../core.h" -+#include "../efuse.h" -+#include "../usb.h" -+#include "../rtl8192d/reg.h" -+#include "../rtl8192d/def.h" -+#include "../rtl8192d/phy_common.h" -+#include "../rtl8192d/rf_common.h" -+#include "phy.h" -+#include "rf.h" -+#include "table.h" -+ -+#define MAX_RF_IMR_INDEX 12 -+#define MAX_RF_IMR_INDEX_NORMAL 13 -+#define RF_REG_NUM_FOR_C_CUT_5G 6 -+#define RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA 7 -+#define RF_REG_NUM_FOR_C_CUT_2G 5 -+#define RF_CHNL_NUM_5G 19 -+#define RF_CHNL_NUM_5G_40M 17 -+#define CV_CURVE_CNT 64 -+ -+static const u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = { -+ 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0 -+}; -+ -+static const u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = { -+ RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6 -+}; -+ -+static const u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = { -+ RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8 -+}; -+ -+static const u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = { -+ 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E -+}; -+ -+static const u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = { -+ BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1), -+ BIT(10) | BIT(9), -+ BIT(18) | BIT(17) | BIT(16) | BIT(1), -+ BIT(2) | BIT(1), -+ BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11) -+}; -+ -+static const u8 rf_chnl_5g[RF_CHNL_NUM_5G] = { -+ 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, -+ 112, 116, 120, 124, 128, 132, 136, 140 -+}; -+ -+static const u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = { -+ 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114, -+ 118, 122, 126, 130, 134, 138 -+}; -+ -+static const u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = { -+ {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04}, -+ {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04}, -+ {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04}, -+ {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04}, -+ {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04} -+}; -+ -+static const u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = { -+ {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}, -+ {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840}, -+ {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41} -+}; -+ -+static const u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF; -+ -+static const u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = { -+ {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12}, -+ {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52}, -+ {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12} -+}; -+ -+/* [patha+b][reg] */ -+static const u32 rf_imr_param_normal[3][MAX_RF_IMR_INDEX_NORMAL] = { -+ /* channels 1-14. */ -+ { -+ 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0, -+ 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff -+ }, -+ /* channels 36-64 */ -+ { -+ 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000, -+ 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090, -+ 0x32c9a -+ }, -+ /* channels 100-165 */ -+ { -+ 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000, -+ 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a -+ } -+}; -+ -+static const u32 targetchnl_5g[TARGET_CHNL_NUM_5G] = { -+ 25141, 25116, 25091, 25066, 25041, -+ 25016, 24991, 24966, 24941, 24917, -+ 24892, 24867, 24843, 24818, 24794, -+ 24770, 24765, 24721, 24697, 24672, -+ 24648, 24624, 24600, 24576, 24552, -+ 24528, 24504, 24480, 24457, 24433, -+ 24409, 24385, 24362, 24338, 24315, -+ 24291, 24268, 24245, 24221, 24198, -+ 24175, 24151, 24128, 24105, 24082, -+ 24059, 24036, 24013, 23990, 23967, -+ 23945, 23922, 23899, 23876, 23854, -+ 23831, 23809, 23786, 23764, 23741, -+ 23719, 23697, 23674, 23652, 23630, -+ 23608, 23586, 23564, 23541, 23519, -+ 23498, 23476, 23454, 23432, 23410, -+ 23388, 23367, 23345, 23323, 23302, -+ 23280, 23259, 23237, 23216, 23194, -+ 23173, 23152, 23130, 23109, 23088, -+ 23067, 23046, 23025, 23003, 22982, -+ 22962, 22941, 22920, 22899, 22878, -+ 22857, 22837, 22816, 22795, 22775, -+ 22754, 22733, 22713, 22692, 22672, -+ 22652, 22631, 22611, 22591, 22570, -+ 22550, 22530, 22510, 22490, 22469, -+ 22449, 22429, 22409, 22390, 22370, -+ 22350, 22336, 22310, 22290, 22271, -+ 22251, 22231, 22212, 22192, 22173, -+ 22153, 22134, 22114, 22095, 22075, -+ 22056, 22037, 22017, 21998, 21979, -+ 21960, 21941, 21921, 21902, 21883, -+ 21864, 21845, 21826, 21807, 21789, -+ 21770, 21751, 21732, 21713, 21695, -+ 21676, 21657, 21639, 21620, 21602, -+ 21583, 21565, 21546, 21528, 21509, -+ 21491, 21473, 21454, 21436, 21418, -+ 21400, 21381, 21363, 21345, 21327, -+ 21309, 21291, 21273, 21255, 21237, -+ 21219, 21201, 21183, 21166, 21148, -+ 21130, 21112, 21095, 21077, 21059, -+ 21042, 21024, 21007, 20989, 20972, -+ 25679, 25653, 25627, 25601, 25575, -+ 25549, 25523, 25497, 25471, 25446, -+ 25420, 25394, 25369, 25343, 25318, -+ 25292, 25267, 25242, 25216, 25191, -+ 25166 -+}; -+ -+/* channel 1~14 */ -+static const u32 targetchnl_2g[TARGET_CHNL_NUM_2G] = { -+ 26084, 26030, 25976, 25923, 25869, 25816, 25764, -+ 25711, 25658, 25606, 25554, 25502, 25451, 25328 -+}; -+ -+u32 rtl92du_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ u32 returnvalue, originalvalue, bitshift; -+ -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n", -+ regaddr, bitmask); -+ -+ if (rtlhal->during_mac1init_radioa) -+ regaddr |= MAC1_ACCESS_PHY0; -+ else if (rtlhal->during_mac0init_radiob) -+ regaddr |= MAC0_ACCESS_PHY1; -+ -+ originalvalue = rtl_read_dword(rtlpriv, regaddr); -+ bitshift = calculate_bit_shift(bitmask); -+ returnvalue = (originalvalue & bitmask) >> bitshift; -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, -+ "BBR MASK=0x%x Addr[0x%x]=0x%x\n", -+ bitmask, regaddr, originalvalue); -+ return returnvalue; -+} -+ -+void rtl92du_phy_set_bb_reg(struct ieee80211_hw *hw, -+ u32 regaddr, u32 bitmask, u32 data) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ u32 originalvalue, bitshift; -+ -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, -+ "regaddr(%#x), bitmask(%#x), data(%#x)\n", -+ regaddr, bitmask, data); -+ -+ if (rtlhal->during_mac1init_radioa) -+ regaddr |= MAC1_ACCESS_PHY0; -+ else if (rtlhal->during_mac0init_radiob) -+ regaddr |= MAC0_ACCESS_PHY1; -+ -+ if (bitmask != MASKDWORD) { -+ originalvalue = rtl_read_dword(rtlpriv, regaddr); -+ bitshift = calculate_bit_shift(bitmask); -+ data = (originalvalue & (~bitmask)) | -+ ((data << bitshift) & bitmask); -+ } -+ -+ rtl_write_dword(rtlpriv, regaddr, data); -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, -+ "regaddr(%#x), bitmask(%#x), data(%#x)\n", -+ regaddr, bitmask, data); -+} -+ -+/* To avoid miswrite Reg0x800 for 92D */ -+static void rtl92du_phy_set_bb_reg_1byte(struct ieee80211_hw *hw, -+ u32 regaddr, u32 bitmask, u32 data) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 originalvalue, bitshift, offset; -+ u8 value; -+ -+ /* BitMask only support bit0~bit7 or bit8~bit15, bit16~bit23, -+ * bit24~bit31, should be in 1 byte scale; -+ */ -+ bitshift = calculate_bit_shift(bitmask); -+ offset = bitshift / 8; -+ -+ originalvalue = rtl_read_dword(rtlpriv, regaddr); -+ data = (originalvalue & (~bitmask)) | ((data << bitshift) & bitmask); -+ -+ value = data >> (8 * offset); -+ -+ rtl_write_byte(rtlpriv, regaddr + offset, value); -+} -+ -+bool rtl92du_phy_mac_config(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 arraylength; -+ const u32 *ptrarray; -+ u32 i; -+ -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n"); -+ -+ arraylength = MAC_2T_ARRAYLENGTH; -+ ptrarray = rtl8192du_mac_2tarray; -+ -+ for (i = 0; i < arraylength; i = i + 2) -+ rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]); -+ -+ if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) { -+ /* improve 2-stream TX EVM */ -+ /* rtl_write_byte(rtlpriv, 0x14,0x71); */ -+ /* AMPDU aggregation number 9 */ -+ /* rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); */ -+ rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B); -+ } else { -+ /* 92D need to test to decide the num. */ -+ rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07); -+ } -+ -+ return true; -+} -+ -+static bool _rtl92du_phy_config_bb(struct ieee80211_hw *hw, u8 configtype) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ u16 phy_reg_arraylen, agctab_arraylen = 0; -+ const u32 *agctab_array_table = NULL; -+ const u32 *phy_regarray_table; -+ int i; -+ -+ /* Normal chip, Mac0 use AGC_TAB.txt for 2G and 5G band. */ -+ if (rtlhal->interfaceindex == 0) { -+ agctab_arraylen = AGCTAB_ARRAYLENGTH; -+ agctab_array_table = rtl8192du_agctab_array; -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ " ===> phy:MAC0, Rtl819XAGCTAB_Array\n"); -+ } else { -+ if (rtlhal->current_bandtype == BAND_ON_2_4G) { -+ agctab_arraylen = AGCTAB_2G_ARRAYLENGTH; -+ agctab_array_table = rtl8192du_agctab_2garray; -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ " ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n"); -+ } else { -+ agctab_arraylen = AGCTAB_5G_ARRAYLENGTH; -+ agctab_array_table = rtl8192du_agctab_5garray; -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ " ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n"); -+ } -+ } -+ phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH; -+ phy_regarray_table = rtl8192du_phy_reg_2tarray; -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ " ===> phy:Rtl819XPHY_REG_Array_PG\n"); -+ -+ if (configtype == BASEBAND_CONFIG_PHY_REG) { -+ for (i = 0; i < phy_reg_arraylen; i = i + 2) { -+ rtl_addr_delay(phy_regarray_table[i]); -+ rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD, -+ phy_regarray_table[i + 1]); -+ udelay(1); -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, -+ "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", -+ phy_regarray_table[i], -+ phy_regarray_table[i + 1]); -+ } -+ } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { -+ for (i = 0; i < agctab_arraylen; i = i + 2) { -+ rtl_set_bbreg(hw, agctab_array_table[i], -+ MASKDWORD, agctab_array_table[i + 1]); -+ -+ /* Add 1us delay between BB/RF register setting. */ -+ udelay(1); -+ -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, -+ "AGC table %u %u\n", -+ agctab_array_table[i], -+ agctab_array_table[i + 1]); -+ } -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "Normal Chip, loaded AGC table\n"); -+ } -+ return true; -+} -+ -+static bool _rtl92du_phy_config_bb_pg(struct ieee80211_hw *hw, u8 configtype) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ const u32 *phy_regarray_table_pg; -+ u16 phy_regarray_pg_len; -+ int i; -+ -+ phy_regarray_pg_len = PHY_REG_ARRAY_PG_LENGTH; -+ phy_regarray_table_pg = rtl8192du_phy_reg_array_pg; -+ -+ if (configtype == BASEBAND_CONFIG_PHY_REG) { -+ for (i = 0; i < phy_regarray_pg_len; i = i + 3) { -+ rtl_addr_delay(phy_regarray_table_pg[i]); -+ rtl92d_store_pwrindex_diffrate_offset(hw, -+ phy_regarray_table_pg[i], -+ phy_regarray_table_pg[i + 1], -+ phy_regarray_table_pg[i + 2]); -+ } -+ } else { -+ rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, -+ "configtype != BaseBand_Config_PHY_REG\n"); -+ } -+ return true; -+} -+ -+static bool _rtl92du_phy_bb_config(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ bool ret; -+ -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "==>\n"); -+ ret = _rtl92du_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG); -+ if (!ret) { -+ pr_err("Write BB Reg Fail!!\n"); -+ return false; -+ } -+ -+ if (!rtlefuse->autoload_failflag) { -+ rtlphy->pwrgroup_cnt = 0; -+ ret = _rtl92du_phy_config_bb_pg(hw, BASEBAND_CONFIG_PHY_REG); -+ } -+ if (!ret) { -+ pr_err("BB_PG Reg Fail!!\n"); -+ return false; -+ } -+ -+ ret = _rtl92du_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB); -+ if (!ret) { -+ pr_err("AGC Table Fail\n"); -+ return false; -+ } -+ -+ rtlphy->cck_high_power = (bool)rtl_get_bbreg(hw, -+ RFPGA0_XA_HSSIPARAMETER2, -+ 0x200); -+ -+ return true; -+} -+ -+bool rtl92du_phy_bb_config(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ bool rtstatus; -+ u32 regvaldw; -+ u16 regval; -+ u8 value; -+ -+ rtl92d_phy_init_bb_rf_register_definition(hw); -+ -+ regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); -+ rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, -+ regval | BIT(13) | BIT(0) | BIT(1)); -+ -+ rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83); -+ rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb); -+ -+ /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */ -+ value = rtl_read_byte(rtlpriv, REG_RF_CTRL); -+ rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB | -+ RF_SDMRSTB); -+ -+ value = FEN_BB_GLB_RSTN | FEN_BBRSTB; -+ if (rtlhal->interface == INTF_PCI) -+ value |= FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE; -+ else if (rtlhal->interface == INTF_USB) -+ value |= FEN_USBA | FEN_USBD; -+ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value); -+ -+ regvaldw = rtl_read_dword(rtlpriv, RFPGA0_XCD_RFPARAMETER); -+ regvaldw &= ~BIT(31); -+ rtl_write_dword(rtlpriv, RFPGA0_XCD_RFPARAMETER, regvaldw); -+ -+ /* To Fix MAC loopback mode fail. */ -+ rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f); -+ rtl_write_byte(rtlpriv, 0x15, 0xe9); -+ -+ rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); -+ if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version)) && -+ rtlhal->interface == INTF_PCI) { -+ regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0); -+ rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23)); -+ } -+ -+ rtstatus = _rtl92du_phy_bb_config(hw); -+ -+ /* Crystal calibration */ -+ rtl_set_bbreg(hw, REG_AFE_XTAL_CTRL, 0xf0, -+ rtlpriv->efuse.crystalcap & 0x0f); -+ rtl_set_bbreg(hw, REG_AFE_PLL_CTRL, 0xf0000000, -+ (rtlpriv->efuse.crystalcap & 0xf0) >> 4); -+ -+ return rtstatus; -+} -+ -+bool rtl92du_phy_rf_config(struct ieee80211_hw *hw) -+{ -+ return rtl92du_phy_rf6052_config(hw); -+} -+ -+bool rtl92du_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, -+ enum rf_content content, -+ enum radio_path rfpath) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u16 radioa_arraylen, radiob_arraylen; -+ const u32 *radioa_array_table; -+ const u32 *radiob_array_table; -+ int i; -+ -+ radioa_arraylen = RADIOA_2T_ARRAYLENGTH; -+ radioa_array_table = rtl8192du_radioa_2tarray; -+ radiob_arraylen = RADIOB_2T_ARRAYLENGTH; -+ radiob_array_table = rtl8192du_radiob_2tarray; -+ if (rtlpriv->efuse.internal_pa_5g[0]) { -+ radioa_arraylen = RADIOA_2T_INT_PA_ARRAYLENGTH; -+ radioa_array_table = rtl8192du_radioa_2t_int_paarray; -+ } -+ if (rtlpriv->efuse.internal_pa_5g[1]) { -+ radiob_arraylen = RADIOB_2T_INT_PA_ARRAYLENGTH; -+ radiob_array_table = rtl8192du_radiob_2t_int_paarray; -+ } -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "PHY_ConfigRFWithHeaderFile() Radio_A:Rtl819XRadioA_1TArray\n"); -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "PHY_ConfigRFWithHeaderFile() Radio_B:Rtl819XRadioB_1TArray\n"); -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath); -+ -+ /* this only happens when DMDP, mac0 start on 2.4G, -+ * mac1 start on 5G, mac 0 has to set phy0 & phy1 -+ * pathA or mac1 has to set phy0 & phy1 pathA -+ */ -+ if (content == radiob_txt && rfpath == RF90_PATH_A) { -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ " ===> althougth Path A, we load radiob.txt\n"); -+ radioa_arraylen = radiob_arraylen; -+ radioa_array_table = radiob_array_table; -+ } -+ -+ switch (rfpath) { -+ case RF90_PATH_A: -+ for (i = 0; i < radioa_arraylen; i = i + 2) { -+ rtl_rfreg_delay(hw, rfpath, radioa_array_table[i], -+ RFREG_OFFSET_MASK, -+ radioa_array_table[i + 1]); -+ } -+ break; -+ case RF90_PATH_B: -+ for (i = 0; i < radiob_arraylen; i = i + 2) { -+ rtl_rfreg_delay(hw, rfpath, radiob_array_table[i], -+ RFREG_OFFSET_MASK, -+ radiob_array_table[i + 1]); -+ } -+ break; -+ case RF90_PATH_C: -+ case RF90_PATH_D: -+ pr_err("switch case %#x not processed\n", rfpath); -+ break; -+ } -+ -+ return true; -+} -+ -+void rtl92du_phy_set_bw_mode(struct ieee80211_hw *hw, -+ enum nl80211_channel_type ch_type) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ struct rtl_mac *mac = rtl_mac(rtlpriv); -+ u8 reg_bw_opmode; -+ u8 reg_prsr_rsc; -+ -+ if (rtlphy->set_bwmode_inprogress) -+ return; -+ -+ if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { -+ rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, -+ "FALSE driver sleep or unload\n"); -+ return; -+ } -+ -+ rtlphy->set_bwmode_inprogress = true; -+ -+ rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n", -+ rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ? -+ "20MHz" : "40MHz"); -+ -+ reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE); -+ reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2); -+ -+ switch (rtlphy->current_chan_bw) { -+ case HT_CHANNEL_WIDTH_20: -+ reg_bw_opmode |= BW_OPMODE_20MHZ; -+ rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); -+ break; -+ case HT_CHANNEL_WIDTH_20_40: -+ reg_bw_opmode &= ~BW_OPMODE_20MHZ; -+ rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode); -+ -+ reg_prsr_rsc = (reg_prsr_rsc & 0x90) | -+ (mac->cur_40_prime_sc << 5); -+ rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc); -+ break; -+ default: -+ pr_err("unknown bandwidth: %#X\n", -+ rtlphy->current_chan_bw); -+ break; -+ } -+ -+ switch (rtlphy->current_chan_bw) { -+ case HT_CHANNEL_WIDTH_20: -+ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BRFMOD, 0x0); -+ rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); -+ /* SET BIT10 BIT11 for receive cck */ -+ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) | BIT(11), 3); -+ break; -+ case HT_CHANNEL_WIDTH_20_40: -+ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BRFMOD, 0x1); -+ rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); -+ /* Set Control channel to upper or lower. -+ * These settings are required only for 40MHz -+ */ -+ if (rtlhal->current_bandtype == BAND_ON_2_4G) -+ rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCKSIDEBAND, -+ mac->cur_40_prime_sc >> 1); -+ rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); -+ /* SET BIT10 BIT11 for receive cck */ -+ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, -+ BIT(10) | BIT(11), 0); -+ rtl_set_bbreg(hw, 0x818, BIT(26) | BIT(27), -+ mac->cur_40_prime_sc == -+ HAL_PRIME_CHNL_OFFSET_LOWER ? 2 : 1); -+ break; -+ default: -+ pr_err("unknown bandwidth: %#X\n", -+ rtlphy->current_chan_bw); -+ break; -+ } -+ -+ rtl92d_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw); -+ -+ rtlphy->set_bwmode_inprogress = false; -+ rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); -+} -+ -+static void _rtl92du_phy_stop_trx_before_changeband(struct ieee80211_hw *hw) -+{ -+ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BCCKEN | BOFDMEN, 0); -+ rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); -+ rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); -+} -+ -+static void rtl92du_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ u16 basic_rates; -+ u32 reg_mac; -+ u8 value8; -+ -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n"); -+ rtlhal->bandset = band; -+ rtlhal->current_bandtype = band; -+ if (IS_92D_SINGLEPHY(rtlhal->version)) -+ rtlhal->bandset = BAND_ON_BOTH; -+ -+ /* stop RX/Tx */ -+ _rtl92du_phy_stop_trx_before_changeband(hw); -+ -+ /* reconfig BB/RF according to wireless mode */ -+ if (rtlhal->current_bandtype == BAND_ON_2_4G) -+ /* BB & RF Config */ -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>2.4G\n"); -+ else -+ /* 5G band */ -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "====>5G\n"); -+ -+ if (rtlhal->interfaceindex == 1) -+ _rtl92du_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB); -+ -+ rtl92du_update_bbrf_configuration(hw); -+ -+ basic_rates = RRSR_6M | RRSR_12M | RRSR_24M; -+ if (rtlhal->current_bandtype == BAND_ON_2_4G) -+ basic_rates |= RRSR_1M | RRSR_2M | RRSR_5_5M | RRSR_11M; -+ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE, -+ (u8 *)&basic_rates); -+ -+ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BCCKEN | BOFDMEN, 0x3); -+ -+ /* 20M BW. */ -+ /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1); */ -+ rtlhal->reloadtxpowerindex = true; -+ -+ reg_mac = rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1; -+ -+ /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ -+ if (rtlhal->current_bandtype == BAND_ON_2_4G) { -+ value8 = rtl_read_byte(rtlpriv, reg_mac); -+ value8 |= BIT(1); -+ rtl_write_byte(rtlpriv, reg_mac, value8); -+ } else { -+ value8 = rtl_read_byte(rtlpriv, reg_mac); -+ value8 &= ~BIT(1); -+ rtl_write_byte(rtlpriv, reg_mac, value8); -+ } -+ mdelay(1); -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n"); -+} -+ -+static void _rtl92du_phy_reload_imr_setting(struct ieee80211_hw *hw, -+ u8 channel, u8 rfpath) -+{ -+ struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u8 group, i; -+ -+ if (rtlusb->udev->speed != USB_SPEED_HIGH) -+ return; -+ -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>path %d\n", rfpath); -+ if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) { -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); -+ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, -+ BOFDMEN | BCCKEN, 0); -+ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); -+ -+ /* fc area 0xd2c */ -+ if (channel >= 149) -+ rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | -+ BIT(14), 2); -+ else -+ rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(13) | -+ BIT(14), 1); -+ -+ /* leave 0 for channel1-14. */ -+ group = channel <= 64 ? 1 : 2; -+ for (i = 0; i < MAX_RF_IMR_INDEX_NORMAL; i++) -+ rtl_set_rfreg(hw, (enum radio_path)rfpath, -+ rf_reg_for_5g_swchnl_normal[i], -+ RFREG_OFFSET_MASK, -+ rf_imr_param_normal[group][i]); -+ -+ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); -+ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, -+ BOFDMEN | BCCKEN, 3); -+ } else { -+ /* G band. */ -+ rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, -+ "Load RF IMR parameters for G band. IMR already setting %d\n", -+ rtlpriv->rtlhal.load_imrandiqk_setting_for2g); -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); -+ -+ if (!rtlpriv->rtlhal.load_imrandiqk_setting_for2g) { -+ rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, -+ "Load RF IMR parameters for G band. %d\n", -+ rfpath); -+ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, -+ BOFDMEN | BCCKEN, 0); -+ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, -+ 0x00f00000, 0xf); -+ -+ for (i = 0; i < MAX_RF_IMR_INDEX_NORMAL; i++) { -+ rtl_set_rfreg(hw, (enum radio_path)rfpath, -+ rf_reg_for_5g_swchnl_normal[i], -+ RFREG_OFFSET_MASK, -+ rf_imr_param_normal[0][i]); -+ } -+ -+ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, -+ 0x00f00000, 0); -+ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, -+ BOFDMEN | BCCKEN, 3); -+ } -+ } -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); -+} -+ -+static void _rtl92du_phy_switch_rf_setting(struct ieee80211_hw *hw, u8 channel) -+{ -+ struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u8 path = rtlhal->current_bandtype == BAND_ON_5G ? RF90_PATH_A -+ : RF90_PATH_B; -+ u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2; -+ bool need_pwr_down = false, internal_pa = false; -+ u32 regb30 = rtl_get_bbreg(hw, 0xb30, BIT(27)); -+ u8 index = 0, i, rfpath; -+ -+ if (rtlusb->udev->speed != USB_SPEED_HIGH) -+ return; -+ -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>\n"); -+ /* config path A for 5G */ -+ if (rtlhal->current_bandtype == BAND_ON_5G) { -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>5G\n"); -+ u4tmp = rtlpriv->curveindex_5g[channel - 1]; -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); -+ -+ for (i = 0; i < RF_CHNL_NUM_5G; i++) { -+ if (channel == rf_chnl_5g[i] && channel <= 140) -+ index = 0; -+ } -+ for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) { -+ if (channel == rf_chnl_5g_40m[i] && channel <= 140) -+ index = 1; -+ } -+ if (channel == 149 || channel == 155 || channel == 161) -+ index = 2; -+ else if (channel == 151 || channel == 153 || channel == 163 || -+ channel == 165) -+ index = 3; -+ else if (channel == 157 || channel == 159) -+ index = 4; -+ -+ if (rtlhal->macphymode == DUALMAC_DUALPHY && -+ rtlhal->interfaceindex == 1) { -+ need_pwr_down = rtl92du_phy_enable_anotherphy(hw, false); -+ rtlhal->during_mac1init_radioa = true; -+ /* asume no this case */ -+ if (need_pwr_down) -+ rtl92d_phy_enable_rf_env(hw, path, -+ &u4regvalue); -+ } -+ -+ /* DMDP, if band = 5G, Mac0 need to set PHY1 when regB30[27]=1 */ -+ if (regb30 && rtlhal->interfaceindex == 0) { -+ need_pwr_down = rtl92du_phy_enable_anotherphy(hw, true); -+ rtlhal->during_mac0init_radiob = true; -+ if (need_pwr_down) -+ rtl92d_phy_enable_rf_env(hw, path, -+ &u4regvalue); -+ } -+ -+ for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) { -+ if (i == 0 && rtlhal->macphymode == DUALMAC_DUALPHY) { -+ rtl_set_rfreg(hw, (enum radio_path)path, -+ rf_reg_for_c_cut_5g[i], -+ RFREG_OFFSET_MASK, 0xE439D); -+ } else if (rf_reg_for_c_cut_5g[i] == RF_SYN_G4) { -+ u4tmp2 = (rf_reg_pram_c_5g[index][i] & -+ 0x7FF) | (u4tmp << 11); -+ if (channel == 36) -+ u4tmp2 &= ~(BIT(7) | BIT(6)); -+ rtl_set_rfreg(hw, (enum radio_path)path, -+ rf_reg_for_c_cut_5g[i], -+ RFREG_OFFSET_MASK, u4tmp2); -+ } else { -+ rtl_set_rfreg(hw, (enum radio_path)path, -+ rf_reg_for_c_cut_5g[i], -+ RFREG_OFFSET_MASK, -+ rf_reg_pram_c_5g[index][i]); -+ } -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, -+ "offset 0x%x value 0x%x path %d index %d readback 0x%x\n", -+ rf_reg_for_c_cut_5g[i], -+ rf_reg_pram_c_5g[index][i], -+ path, index, -+ rtl_get_rfreg(hw, (enum radio_path)path, -+ rf_reg_for_c_cut_5g[i], -+ RFREG_OFFSET_MASK)); -+ } -+ if (rtlhal->macphymode == DUALMAC_DUALPHY && -+ rtlhal->interfaceindex == 1) { -+ if (need_pwr_down) -+ rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); -+ -+ rtl92du_phy_powerdown_anotherphy(hw, false); -+ } -+ -+ if (regb30 && rtlhal->interfaceindex == 0) { -+ if (need_pwr_down) -+ rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); -+ -+ rtl92du_phy_powerdown_anotherphy(hw, true); -+ } -+ -+ if (channel < 149) -+ value = 0x07; -+ else if (channel >= 149) -+ value = 0x02; -+ if (channel >= 36 && channel <= 64) -+ index = 0; -+ else if (channel >= 100 && channel <= 140) -+ index = 1; -+ else -+ index = 2; -+ -+ for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; -+ rfpath++) { -+ if (rtlhal->macphymode == DUALMAC_DUALPHY && -+ rtlhal->interfaceindex == 1) /* MAC 1 5G */ -+ internal_pa = rtlpriv->efuse.internal_pa_5g[1]; -+ else -+ internal_pa = -+ rtlpriv->efuse.internal_pa_5g[rfpath]; -+ -+ if (internal_pa) { -+ for (i = 0; -+ i < RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA; -+ i++) { -+ if (rf_for_c_cut_5g_internal_pa[i] == 0x03 && -+ channel >= 36 && channel <= 64) -+ rtl_set_rfreg(hw, rfpath, -+ rf_for_c_cut_5g_internal_pa[i], -+ RFREG_OFFSET_MASK, -+ 0x7bdef); -+ else -+ rtl_set_rfreg(hw, rfpath, -+ rf_for_c_cut_5g_internal_pa[i], -+ RFREG_OFFSET_MASK, -+ rf_pram_c_5g_int_pa[index][i]); -+ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, -+ "offset 0x%x value 0x%x path %d index %d\n", -+ rf_for_c_cut_5g_internal_pa[i], -+ rf_pram_c_5g_int_pa[index][i], -+ rfpath, index); -+ } -+ } else { -+ rtl_set_rfreg(hw, (enum radio_path)rfpath, RF_TXPA_AG, -+ mask, value); -+ } -+ } -+ } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "====>2.4G\n"); -+ u4tmp = rtlpriv->curveindex_2g[channel - 1]; -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); -+ -+ if (channel == 1 || channel == 2 || channel == 4 || -+ channel == 9 || channel == 10 || channel == 11 || -+ channel == 12) -+ index = 0; -+ else if (channel == 3 || channel == 13 || channel == 14) -+ index = 1; -+ else if (channel >= 5 && channel <= 8) -+ index = 2; -+ -+ if (rtlhal->macphymode == DUALMAC_DUALPHY) { -+ path = RF90_PATH_A; -+ if (rtlhal->interfaceindex == 0) { -+ need_pwr_down = -+ rtl92du_phy_enable_anotherphy(hw, true); -+ rtlhal->during_mac0init_radiob = true; -+ -+ if (need_pwr_down) -+ rtl92d_phy_enable_rf_env(hw, path, -+ &u4regvalue); -+ } -+ -+ /* DMDP, if band = 2G, MAC1 need to set PHY0 when regB30[27]=1 */ -+ if (regb30 && rtlhal->interfaceindex == 1) { -+ need_pwr_down = -+ rtl92du_phy_enable_anotherphy(hw, false); -+ rtlhal->during_mac1init_radioa = true; -+ -+ if (need_pwr_down) -+ rtl92d_phy_enable_rf_env(hw, path, -+ &u4regvalue); -+ } -+ } -+ -+ for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) { -+ if (rf_reg_for_c_cut_2g[i] == RF_SYN_G7) -+ rtl_set_rfreg(hw, (enum radio_path)path, -+ rf_reg_for_c_cut_2g[i], -+ RFREG_OFFSET_MASK, -+ rf_reg_param_for_c_cut_2g[index][i] | -+ BIT(17)); -+ else -+ rtl_set_rfreg(hw, (enum radio_path)path, -+ rf_reg_for_c_cut_2g[i], -+ RFREG_OFFSET_MASK, -+ rf_reg_param_for_c_cut_2g -+ [index][i]); -+ -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, -+ "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n", -+ rf_reg_for_c_cut_2g[i], -+ rf_reg_param_for_c_cut_2g[index][i], -+ rf_reg_mask_for_c_cut_2g[i], path, index, -+ rtl_get_rfreg(hw, (enum radio_path)path, -+ rf_reg_for_c_cut_2g[i], -+ RFREG_OFFSET_MASK)); -+ } -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", -+ rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); -+ -+ rtl_set_rfreg(hw, (enum radio_path)path, RF_SYN_G4, -+ RFREG_OFFSET_MASK, -+ rf_syn_g4_for_c_cut_2g | (u4tmp << 11)); -+ -+ if (rtlhal->macphymode == DUALMAC_DUALPHY && -+ rtlhal->interfaceindex == 0) { -+ if (need_pwr_down) -+ rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); -+ -+ rtl92du_phy_powerdown_anotherphy(hw, true); -+ } -+ -+ if (regb30 && rtlhal->interfaceindex == 1) { -+ if (need_pwr_down) -+ rtl92d_phy_restore_rf_env(hw, path, &u4regvalue); -+ -+ rtl92du_phy_powerdown_anotherphy(hw, false); -+ } -+ } -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); -+} -+ -+/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ -+static u8 _rtl92du_phy_patha_iqk(struct ieee80211_hw *hw, bool configpathb) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ u32 regeac, rege94, rege9c, regea4; -+ u8 result = 0; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); -+ -+ if (rtlhal->interfaceindex == 0) { -+ rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1f); -+ rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1f); -+ } else { -+ rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c22); -+ rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c22); -+ } -+ rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140102); -+ rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, -+ configpathb ? 0x28160202 : 0x28160502); -+ /* path-B IQK setting */ -+ if (configpathb) { -+ rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x10008c22); -+ rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x10008c22); -+ rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82140102); -+ rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160206); -+ } -+ -+ /* LO calibration setting */ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); -+ rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); -+ -+ /* One shot, path A LOK & IQK */ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path A LOK & IQK!\n"); -+ rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); -+ rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Delay %d ms for One shot, path A LOK & IQK\n", -+ IQK_DELAY_TIME); -+ mdelay(IQK_DELAY_TIME); -+ -+ /* Check failed */ -+ regeac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); -+ rege94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); -+ rege9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); -+ regea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); -+ -+ if (!(regeac & BIT(28)) && -+ (((rege94 & 0x03FF0000) >> 16) != 0x142) && -+ (((rege9c & 0x03FF0000) >> 16) != 0x42)) -+ result |= 0x01; -+ else /* if Tx not OK, ignore Rx */ -+ return result; -+ -+ /* if Tx is OK, check whether Rx is OK */ -+ if (!(regeac & BIT(27)) && -+ (((regea4 & 0x03FF0000) >> 16) != 0x132) && -+ (((regeac & 0x03FF0000) >> 16) != 0x36)) -+ result |= 0x02; -+ else -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A Rx IQK fail!!\n"); -+ -+ return result; -+} -+ -+/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ -+static u8 _rtl92du_phy_patha_iqk_5g_normal(struct ieee80211_hw *hw, -+ bool configpathb) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u32 TXOKBIT = BIT(28), RXOKBIT = BIT(27); -+ u32 regeac, rege94, rege9c, regea4; -+ u8 timeout = 20, timecount = 0; -+ u8 retrycount = 2; -+ u8 result = 0; -+ u8 i; -+ -+ if (rtlhal->interfaceindex == 1) { /* PHY1 */ -+ TXOKBIT = BIT(31); -+ RXOKBIT = BIT(30); -+ } -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n"); -+ rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1f); -+ rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1f); -+ rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140307); -+ rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160960); -+ /* path-B IQK setting */ -+ if (configpathb) { -+ rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c2f); -+ rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c2f); -+ rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82110000); -+ rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68110000); -+ } -+ -+ /* LO calibration setting */ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); -+ rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); -+ -+ /* path-A PA on */ -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); -+ rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); -+ -+ for (i = 0; i < retrycount; i++) { -+ /* One shot, path A LOK & IQK */ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "One shot, path A LOK & IQK!\n"); -+ rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); -+ rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Delay %d ms for One shot, path A LOK & IQK.\n", -+ IQK_DELAY_TIME); -+ mdelay(IQK_DELAY_TIME * 10); -+ -+ while (timecount < timeout && -+ rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, BIT(26)) == 0) { -+ udelay(IQK_DELAY_TIME * 1000 * 2); -+ timecount++; -+ } -+ -+ timecount = 0; -+ while (timecount < timeout && -+ rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASK_IQK_RESULT) == 0) { -+ udelay(IQK_DELAY_TIME * 1000 * 2); -+ timecount++; -+ } -+ -+ /* Check failed */ -+ regeac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); -+ rege94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); -+ rege9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); -+ regea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); -+ -+ if (!(regeac & TXOKBIT) && -+ (((rege94 & 0x03FF0000) >> 16) != 0x142)) { -+ result |= 0x01; -+ } else { /* if Tx not OK, ignore Rx */ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Path A Tx IQK fail!!\n"); -+ continue; -+ } -+ -+ /* if Tx is OK, check whether Rx is OK */ -+ if (!(regeac & RXOKBIT) && -+ (((regea4 & 0x03FF0000) >> 16) != 0x132)) { -+ result |= 0x02; -+ break; -+ } -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A Rx IQK fail!!\n"); -+ } -+ -+ /* path A PA off */ -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, -+ rtlphy->iqk_bb_backup[0]); -+ rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, -+ rtlphy->iqk_bb_backup[1]); -+ -+ if (!(result & 0x01)) /* Tx IQK fail */ -+ rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x19008c00); -+ -+ if (!(result & 0x02)) { /* Rx IQK fail */ -+ rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); -+ rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x19008c00); -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Path A Rx IQK fail!! 0xe34 = %#x\n", -+ rtl_get_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD)); -+ } -+ -+ return result; -+} -+ -+/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ -+static u8 _rtl92du_phy_pathb_iqk(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 regeac, regeb4, regebc, regec4, regecc; -+ u8 result = 0; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "One shot, path B LOK & IQK!\n"); -+ rtl_set_bbreg(hw, RIQK_AGC_CONT, MASKDWORD, 0x00000002); -+ rtl_set_bbreg(hw, RIQK_AGC_CONT, MASKDWORD, 0x00000000); -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Delay %d ms for One shot, path B LOK & IQK\n", IQK_DELAY_TIME); -+ mdelay(IQK_DELAY_TIME); -+ -+ /* Check failed */ -+ regeac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); -+ regeb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); -+ regebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); -+ regec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); -+ regecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); -+ -+ if (!(regeac & BIT(31)) && -+ (((regeb4 & 0x03FF0000) >> 16) != 0x142) && -+ (((regebc & 0x03FF0000) >> 16) != 0x42)) -+ result |= 0x01; -+ else -+ return result; -+ -+ if (!(regeac & BIT(30)) && -+ (((regec4 & 0x03FF0000) >> 16) != 0x132) && -+ (((regecc & 0x03FF0000) >> 16) != 0x36)) -+ result |= 0x02; -+ else -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B Rx IQK fail!!\n"); -+ -+ return result; -+} -+ -+/* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ -+static u8 _rtl92du_phy_pathb_iqk_5g_normal(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u32 regeac, regeb4, regebc, regec4, regecc; -+ u8 timeout = 20, timecount = 0; -+ u8 retrycount = 2; -+ u8 result = 0; -+ u8 i; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-B IQK setting!\n"); -+ rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1f); -+ rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1f); -+ rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82110000); -+ rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68110000); -+ -+ /* path-B IQK setting */ -+ rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c2f); -+ rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c2f); -+ rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82140307); -+ rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160960); -+ -+ /* LO calibration setting */ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "LO calibration setting!\n"); -+ rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); -+ -+ /* path-B PA on */ -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); -+ rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); -+ -+ for (i = 0; i < retrycount; i++) { -+ /* One shot, path B LOK & IQK */ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "One shot, path A LOK & IQK!\n"); -+ rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); -+ rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Delay %d ms for One shot, path B LOK & IQK.\n", 10); -+ mdelay(IQK_DELAY_TIME * 10); -+ -+ while (timecount < timeout && -+ rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, BIT(29)) == 0) { -+ udelay(IQK_DELAY_TIME * 1000 * 2); -+ timecount++; -+ } -+ -+ timecount = 0; -+ while (timecount < timeout && -+ rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASK_IQK_RESULT) == 0) { -+ udelay(IQK_DELAY_TIME * 1000 * 2); -+ timecount++; -+ } -+ -+ /* Check failed */ -+ regeac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); -+ regeb4 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); -+ regebc = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); -+ regec4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); -+ regecc = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); -+ -+ if (!(regeac & BIT(31)) && -+ (((regeb4 & 0x03FF0000) >> 16) != 0x142)) -+ result |= 0x01; -+ else -+ continue; -+ -+ if (!(regeac & BIT(30)) && -+ (((regec4 & 0x03FF0000) >> 16) != 0x132)) { -+ result |= 0x02; -+ break; -+ } -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B Rx IQK fail!!\n"); -+ } -+ -+ /* path B PA off */ -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, -+ rtlphy->iqk_bb_backup[0]); -+ rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, -+ rtlphy->iqk_bb_backup[2]); -+ -+ if (!(result & 0x01)) -+ rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x19008c00); -+ -+ if (!(result & 0x02)) { -+ rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); -+ rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x19008c00); -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Path B Rx IQK fail!! 0xe54 = %#x\n", -+ rtl_get_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD)); -+ } -+ -+ return result; -+} -+ -+static void _rtl92du_phy_reload_adda_registers(struct ieee80211_hw *hw, -+ const u32 *adda_reg, -+ u32 *adda_backup, u32 regnum) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 i; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Reload ADDA power saving parameters !\n"); -+ for (i = 0; i < regnum; i++) { -+ /* path-A/B BB to initial gain */ -+ if (adda_reg[i] == ROFDM0_XAAGCCORE1 || -+ adda_reg[i] == ROFDM0_XBAGCCORE1) -+ rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, 0x50); -+ -+ rtl_set_bbreg(hw, adda_reg[i], MASKDWORD, adda_backup[i]); -+ } -+} -+ -+static void _rtl92du_phy_reload_mac_registers(struct ieee80211_hw *hw, -+ const u32 *macreg, u32 *macbackup) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 i; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Reload MAC parameters !\n"); -+ for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) -+ rtl_write_byte(rtlpriv, macreg[i], (u8)macbackup[i]); -+ rtl_write_dword(rtlpriv, macreg[i], macbackup[i]); -+} -+ -+static void _rtl92du_phy_patha_standby(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A standby mode!\n"); -+ -+ rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x0); -+ rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); -+ rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000); -+} -+ -+static void _rtl92du_phy_pimode_switch(struct ieee80211_hw *hw, bool pi_mode) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 mode; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "BB Switch to %s mode!\n", pi_mode ? "PI" : "SI"); -+ mode = pi_mode ? 0x01000100 : 0x01000000; -+ rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, MASKDWORD, mode); -+ rtl_set_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1, MASKDWORD, mode); -+} -+ -+static void _rtl92du_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8], -+ u8 t, bool is2t) -+{ -+ static const u32 adda_reg[IQK_ADDA_REG_NUM] = { -+ RFPGA0_XCD_SWITCHCONTROL, RBLUE_TOOTH, RRX_WAIT_CCA, -+ RTX_CCK_RFON, RTX_CCK_BBON, RTX_OFDM_RFON, RTX_OFDM_BBON, -+ RTX_TO_RX, RTX_TO_TX, RRX_CCK, RRX_OFDM, RRX_WAIT_RIFS, -+ RRX_TO_RX, RSTANDBY, RSLEEP, RPMPD_ANAEN -+ }; -+ static const u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { -+ REG_TXPAUSE, REG_BCN_CTRL, REG_BCN_CTRL_1, REG_GPIO_MUXCFG -+ }; -+ static const u32 iqk_bb_reg[IQK_BB_REG_NUM] = { -+ RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE, -+ RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR, -+ RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE, -+ RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4, -+ ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1 -+ }; -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ const u32 retrycount = 2; -+ u8 patha_ok, pathb_ok; -+ u32 bbvalue; -+ u32 i; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 2.4G :Start!!!\n"); -+ if (t == 0) { -+ bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", -+ is2t ? "2T2R" : "1T1R"); -+ -+ /* Save ADDA parameters, turn Path A ADDA on */ -+ rtl92d_phy_save_adda_registers(hw, adda_reg, -+ rtlphy->adda_backup, -+ IQK_ADDA_REG_NUM); -+ rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, -+ rtlphy->iqk_mac_backup); -+ rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, -+ rtlphy->iqk_bb_backup, -+ IQK_BB_REG_NUM); -+ } -+ rtl92d_phy_path_adda_on(hw, adda_reg, true, is2t); -+ -+ rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038); -+ -+ if (t == 0) -+ rtlphy->rfpi_enable = (u8)rtl_get_bbreg(hw, -+ RFPGA0_XA_HSSIPARAMETER1, BIT(8)); -+ -+ /* Switch BB to PI mode to do IQ Calibration. */ -+ if (!rtlphy->rfpi_enable) -+ _rtl92du_phy_pimode_switch(hw, true); -+ -+ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BCCKEN, 0x00); -+ rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); -+ rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); -+ rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); -+ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); -+ if (is2t) { -+ rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, -+ 0x00010000); -+ rtl_set_bbreg(hw, RFPGA0_XB_LSSIPARAMETER, MASKDWORD, -+ 0x00010000); -+ } -+ -+ /* MAC settings */ -+ rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, -+ rtlphy->iqk_mac_backup); -+ -+ /* Page B init */ -+ rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000); -+ if (is2t) -+ rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x0f600000); -+ -+ /* IQ calibration setting */ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); -+ rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000); -+ rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); -+ rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); -+ -+ for (i = 0; i < retrycount; i++) { -+ patha_ok = _rtl92du_phy_patha_iqk(hw, is2t); -+ if (patha_ok == 0x03) { -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Path A IQK Success!!\n"); -+ result[t][0] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, -+ MASK_IQK_RESULT); -+ result[t][1] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, -+ MASK_IQK_RESULT); -+ result[t][2] = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, -+ MASK_IQK_RESULT); -+ result[t][3] = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, -+ MASK_IQK_RESULT); -+ break; -+ } else if (i == (retrycount - 1) && patha_ok == 0x01) { -+ /* Tx IQK OK */ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Path A IQK Only Tx Success!!\n"); -+ -+ result[t][0] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, -+ MASK_IQK_RESULT); -+ result[t][1] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, -+ MASK_IQK_RESULT); -+ } -+ } -+ if (patha_ok == 0x00) -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK failed!!\n"); -+ -+ if (is2t) { -+ _rtl92du_phy_patha_standby(hw); -+ /* Turn Path B ADDA on */ -+ rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); -+ -+ for (i = 0; i < retrycount; i++) { -+ pathb_ok = _rtl92du_phy_pathb_iqk(hw); -+ if (pathb_ok == 0x03) { -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Path B IQK Success!!\n"); -+ result[t][4] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, -+ MASK_IQK_RESULT); -+ result[t][5] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, -+ MASK_IQK_RESULT); -+ result[t][6] = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, -+ MASK_IQK_RESULT); -+ result[t][7] = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, -+ MASK_IQK_RESULT); -+ break; -+ } else if (i == (retrycount - 1) && pathb_ok == 0x01) { -+ /* Tx IQK OK */ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Path B Only Tx IQK Success!!\n"); -+ result[t][4] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, -+ MASK_IQK_RESULT); -+ result[t][5] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, -+ MASK_IQK_RESULT); -+ } -+ } -+ if (pathb_ok == 0x00) -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Path B IQK failed!!\n"); -+ } -+ -+ /* Back to BB mode, load original value */ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "IQK:Back to BB mode, load original value!\n"); -+ -+ rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x000000); -+ -+ if (t != 0) { -+ /* Switch back BB to SI mode after finish IQ Calibration. */ -+ if (!rtlphy->rfpi_enable) -+ _rtl92du_phy_pimode_switch(hw, false); -+ -+ /* Reload ADDA power saving parameters */ -+ _rtl92du_phy_reload_adda_registers(hw, adda_reg, -+ rtlphy->adda_backup, -+ IQK_ADDA_REG_NUM); -+ -+ /* Reload MAC parameters */ -+ _rtl92du_phy_reload_mac_registers(hw, iqk_mac_reg, -+ rtlphy->iqk_mac_backup); -+ -+ if (is2t) -+ _rtl92du_phy_reload_adda_registers(hw, iqk_bb_reg, -+ rtlphy->iqk_bb_backup, -+ IQK_BB_REG_NUM); -+ else -+ _rtl92du_phy_reload_adda_registers(hw, iqk_bb_reg, -+ rtlphy->iqk_bb_backup, -+ IQK_BB_REG_NUM - 1); -+ -+ /* load 0xe30 IQC default value */ -+ rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00); -+ rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00); -+ } -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); -+} -+ -+static void _rtl92du_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw, -+ long result[][8], u8 t) -+{ -+ static const u32 adda_reg[IQK_ADDA_REG_NUM] = { -+ RFPGA0_XCD_SWITCHCONTROL, RBLUE_TOOTH, RRX_WAIT_CCA, -+ RTX_CCK_RFON, RTX_CCK_BBON, RTX_OFDM_RFON, RTX_OFDM_BBON, -+ RTX_TO_RX, RTX_TO_TX, RRX_CCK, RRX_OFDM, RRX_WAIT_RIFS, -+ RRX_TO_RX, RSTANDBY, RSLEEP, RPMPD_ANAEN -+ }; -+ static const u32 iqk_mac_reg[IQK_MAC_REG_NUM] = { -+ REG_TXPAUSE, REG_BCN_CTRL, REG_BCN_CTRL_1, REG_GPIO_MUXCFG -+ }; -+ static const u32 iqk_bb_reg[IQK_BB_REG_NUM] = { -+ RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE, -+ RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR, -+ RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE, -+ RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4, -+ ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1 -+ }; -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; -+ bool is2t = IS_92D_SINGLEPHY(rtlhal->version); -+ u8 patha_ok, pathb_ok; -+ bool rf_path_div; -+ u32 bbvalue; -+ -+ /* Note: IQ calibration must be performed after loading -+ * PHY_REG.txt , and radio_a, radio_b.txt -+ */ -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK for 5G NORMAL:Start!!!\n"); -+ -+ mdelay(IQK_DELAY_TIME * 20); -+ -+ if (t == 0) { -+ bbvalue = rtl_get_bbreg(hw, RFPGA0_RFMOD, MASKDWORD); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQ Calibration for %s\n", -+ is2t ? "2T2R" : "1T1R"); -+ -+ /* Save ADDA parameters, turn Path A ADDA on */ -+ rtl92d_phy_save_adda_registers(hw, adda_reg, -+ rtlphy->adda_backup, -+ IQK_ADDA_REG_NUM); -+ rtl92d_phy_save_mac_registers(hw, iqk_mac_reg, -+ rtlphy->iqk_mac_backup); -+ if (is2t) -+ rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, -+ rtlphy->iqk_bb_backup, -+ IQK_BB_REG_NUM); -+ else -+ rtl92d_phy_save_adda_registers(hw, iqk_bb_reg, -+ rtlphy->iqk_bb_backup, -+ IQK_BB_REG_NUM - 1); -+ } -+ -+ rf_path_div = rtl_get_bbreg(hw, 0xb30, BIT(27)); -+ rtl92d_phy_path_adda_on(hw, adda_reg, !rf_path_div, is2t); -+ -+ if (t == 0) -+ rtlphy->rfpi_enable = rtl_get_bbreg(hw, -+ RFPGA0_XA_HSSIPARAMETER1, -+ BIT(8)); -+ -+ /* Switch BB to PI mode to do IQ Calibration. */ -+ if (!rtlphy->rfpi_enable) -+ _rtl92du_phy_pimode_switch(hw, true); -+ -+ /* MAC settings */ -+ rtl92d_phy_mac_setting_calibration(hw, iqk_mac_reg, -+ rtlphy->iqk_mac_backup); -+ -+ rtl92du_phy_set_bb_reg_1byte(hw, RFPGA0_RFMOD, BCCKEN, 0x00); -+ rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); -+ rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); -+ rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); -+ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); -+ -+ /* Page A AP setting for IQK */ -+ rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0); -+ rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000); -+ if (is2t) { -+ /* Page B AP setting for IQK */ -+ rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0); -+ rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x20000000); -+ } -+ -+ /* IQ calibration setting */ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "IQK setting!\n"); -+ rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000); -+ rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x10007c00); -+ rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); -+ -+ patha_ok = _rtl92du_phy_patha_iqk_5g_normal(hw, is2t); -+ if (patha_ok == 0x03) { -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Success!!\n"); -+ result[t][0] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, -+ MASK_IQK_RESULT); -+ result[t][1] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, -+ MASK_IQK_RESULT); -+ result[t][2] = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, -+ MASK_IQK_RESULT); -+ result[t][3] = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, -+ MASK_IQK_RESULT); -+ } else if (patha_ok == 0x01) { /* Tx IQK OK */ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Path A IQK Only Tx Success!!\n"); -+ -+ result[t][0] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, -+ MASK_IQK_RESULT); -+ result[t][1] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, -+ MASK_IQK_RESULT); -+ } else { -+ rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x000000); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe70 = %#x\n", -+ rtl_get_bbreg(hw, RRX_WAIT_CCA, MASKDWORD)); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "RF path A 0x0 = %#x\n", -+ rtl_get_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK)); -+ rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0x808000); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK Fail!!\n"); -+ } -+ -+ if (is2t) { -+ /* _rtl92d_phy_patha_standby(hw); */ -+ /* Turn Path B ADDA on */ -+ rtl92d_phy_path_adda_on(hw, adda_reg, false, is2t); -+ -+ pathb_ok = _rtl92du_phy_pathb_iqk_5g_normal(hw); -+ if (pathb_ok == 0x03) { -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Path B IQK Success!!\n"); -+ result[t][4] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, -+ MASK_IQK_RESULT); -+ result[t][5] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, -+ MASK_IQK_RESULT); -+ result[t][6] = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_B_2, -+ MASK_IQK_RESULT); -+ result[t][7] = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_B_2, -+ MASK_IQK_RESULT); -+ } else if (pathb_ok == 0x01) { /* Tx IQK OK */ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Path B Only Tx IQK Success!!\n"); -+ result[t][4] = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_B, -+ MASK_IQK_RESULT); -+ result[t][5] = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_B, -+ MASK_IQK_RESULT); -+ } else { -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Path B IQK failed!!\n"); -+ } -+ } -+ -+ /* Back to BB mode, load original value */ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "IQK:Back to BB mode, load original value!\n"); -+ rtl_set_bbreg(hw, RFPGA0_IQK, MASKH3BYTES, 0); -+ -+ if (is2t) -+ _rtl92du_phy_reload_adda_registers(hw, iqk_bb_reg, -+ rtlphy->iqk_bb_backup, -+ IQK_BB_REG_NUM); -+ else -+ _rtl92du_phy_reload_adda_registers(hw, iqk_bb_reg, -+ rtlphy->iqk_bb_backup, -+ IQK_BB_REG_NUM - 1); -+ -+ /* path A IQ path to DP block */ -+ rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x010170b8); -+ if (is2t) /* path B IQ path to DP block */ -+ rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x010170b8); -+ -+ /* Reload MAC parameters */ -+ _rtl92du_phy_reload_mac_registers(hw, iqk_mac_reg, -+ rtlphy->iqk_mac_backup); -+ -+ /* Switch back BB to SI mode after finish IQ Calibration. */ -+ if (!rtlphy->rfpi_enable) -+ _rtl92du_phy_pimode_switch(hw, false); -+ -+ /* Reload ADDA power saving parameters */ -+ _rtl92du_phy_reload_adda_registers(hw, adda_reg, -+ rtlphy->adda_backup, -+ IQK_ADDA_REG_NUM); -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "<==\n"); -+} -+ -+static bool _rtl92du_phy_simularity_compare(struct ieee80211_hw *hw, -+ long result[][8], u8 c1, u8 c2) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; -+ u32 i, j, diff, sim_bitmap, bound, u4temp = 0; -+ u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ -+ bool is2t = IS_92D_SINGLEPHY(rtlhal->version); -+ bool bresult = true; -+ -+ if (is2t) -+ bound = 8; -+ else -+ bound = 4; -+ -+ sim_bitmap = 0; -+ -+ for (i = 0; i < bound; i++) { -+ diff = abs_diff(result[c1][i], result[c2][i]); -+ -+ if (diff > MAX_TOLERANCE_92D) { -+ if ((i == 2 || i == 6) && !sim_bitmap) { -+ if (result[c1][i] + result[c1][i + 1] == 0) -+ final_candidate[(i / 4)] = c2; -+ else if (result[c2][i] + result[c2][i + 1] == 0) -+ final_candidate[(i / 4)] = c1; -+ else -+ sim_bitmap = sim_bitmap | (1 << i); -+ } else { -+ sim_bitmap = sim_bitmap | (1 << i); -+ } -+ } -+ } -+ -+ if (sim_bitmap == 0) { -+ for (i = 0; i < (bound / 4); i++) { -+ if (final_candidate[i] != 0xFF) { -+ for (j = i * 4; j < (i + 1) * 4 - 2; j++) -+ result[3][j] = -+ result[final_candidate[i]][j]; -+ bresult = false; -+ } -+ } -+ -+ for (i = 0; i < bound; i++) -+ u4temp += result[c1][i] + result[c2][i]; -+ -+ if (u4temp == 0) /* IQK fail for c1 & c2 */ -+ bresult = false; -+ -+ return bresult; -+ } -+ -+ if (!(sim_bitmap & 0x0F)) { /* path A OK */ -+ for (i = 0; i < 4; i++) -+ result[3][i] = result[c1][i]; -+ } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */ -+ for (i = 0; i < 2; i++) -+ result[3][i] = result[c1][i]; -+ } -+ -+ if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */ -+ for (i = 4; i < 8; i++) -+ result[3][i] = result[c1][i]; -+ } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */ -+ for (i = 4; i < 6; i++) -+ result[3][i] = result[c1][i]; -+ } -+ -+ return false; -+} -+ -+static void _rtl92du_phy_patha_fill_iqk_matrix_5g_normal(struct ieee80211_hw *hw, -+ bool iqk_ok, -+ long result[][8], -+ u8 final_candidate, -+ bool txonly) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; -+ u32 val_x, reg; -+ int val_y; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed"); -+ if (iqk_ok && final_candidate != 0xFF) { -+ val_x = result[final_candidate][0]; -+ if ((val_x & 0x00000200) != 0) -+ val_x = val_x | 0xFFFFFC00; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x\n", val_x); -+ rtl_set_bbreg(hw, RTX_IQK_TONE_A, 0x3FF0000, val_x); -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), 0); -+ -+ val_y = result[final_candidate][1]; -+ if ((val_y & 0x00000200) != 0) -+ val_y = val_y | 0xFFFFFC00; -+ -+ /* path B IQK result + 3 */ -+ if (rtlhal->current_bandtype == BAND_ON_5G) -+ val_y += 3; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%x\n", val_y); -+ -+ rtl_set_bbreg(hw, RTX_IQK_TONE_A, 0x3FF, val_y); -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), 0); -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe30 = 0x%x\n", -+ rtl_get_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD)); -+ -+ if (txonly) { -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n"); -+ return; -+ } -+ -+ reg = result[final_candidate][2]; -+ rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); -+ reg = result[final_candidate][3] & 0x3F; -+ rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); -+ reg = (result[final_candidate][3] >> 6) & 0xF; -+ rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg); -+ } else { -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "%s: Tx/Rx fail restore default value\n", __func__); -+ -+ rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x19008c00); -+ rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); -+ rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x19008c00); -+ } -+} -+ -+static void _rtl92du_phy_patha_fill_iqk_matrix(struct ieee80211_hw *hw, -+ bool iqk_ok, long result[][8], -+ u8 final_candidate, bool txonly) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; -+ u32 oldval_0, val_x, tx0_a, reg; -+ long val_y, tx0_c; -+ bool is2t = IS_92D_SINGLEPHY(rtlhal->version) || -+ rtlhal->macphymode == DUALMAC_DUALPHY; -+ -+ if (rtlhal->current_bandtype == BAND_ON_5G) { -+ _rtl92du_phy_patha_fill_iqk_matrix_5g_normal(hw, iqk_ok, result, -+ final_candidate, -+ txonly); -+ return; -+ } -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed"); -+ if (final_candidate == 0xFF || !iqk_ok) -+ return; -+ -+ /* OFDM0_D */ -+ oldval_0 = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0xffc00000); -+ -+ val_x = result[final_candidate][0]; -+ if ((val_x & 0x00000200) != 0) -+ val_x = val_x | 0xFFFFFC00; -+ -+ tx0_a = (val_x * oldval_0) >> 8; -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n", -+ val_x, tx0_a, oldval_0); -+ rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24), -+ ((val_x * oldval_0 >> 7) & 0x1)); -+ -+ val_y = result[final_candidate][1]; -+ if ((val_y & 0x00000200) != 0) -+ val_y = val_y | 0xFFFFFC00; -+ -+ /* path B IQK result + 3 */ -+ if (rtlhal->interfaceindex == 1 && -+ rtlhal->current_bandtype == BAND_ON_5G) -+ val_y += 3; -+ -+ tx0_c = (val_y * oldval_0) >> 8; -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Y = 0x%lx, tx0_c = 0x%lx\n", -+ val_y, tx0_c); -+ -+ rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, (tx0_c & 0x3C0) >> 6); -+ rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, tx0_c & 0x3F); -+ if (is2t) -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26), -+ (val_y * oldval_0 >> 7) & 0x1); -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n", -+ rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, -+ MASKDWORD)); -+ -+ if (txonly) { -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n"); -+ return; -+ } -+ -+ reg = result[final_candidate][2]; -+ rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); -+ reg = result[final_candidate][3] & 0x3F; -+ rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); -+ reg = (result[final_candidate][3] >> 6) & 0xF; -+ rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg); -+} -+ -+static void _rtl92du_phy_pathb_fill_iqk_matrix_5g_normal(struct ieee80211_hw *hw, -+ bool iqk_ok, -+ long result[][8], -+ u8 final_candidate, -+ bool txonly) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; -+ u32 val_x, reg; -+ int val_y; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "Path B IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed"); -+ if (iqk_ok && final_candidate != 0xFF) { -+ val_x = result[final_candidate][4]; -+ if ((val_x & 0x00000200) != 0) -+ val_x = val_x | 0xFFFFFC00; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x\n", val_x); -+ rtl_set_bbreg(hw, RTX_IQK_TONE_B, 0x3FF0000, val_x); -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), 0); -+ -+ val_y = result[final_candidate][5]; -+ if ((val_y & 0x00000200) != 0) -+ val_y = val_y | 0xFFFFFC00; -+ -+ /* path B IQK result + 3 */ -+ if (rtlhal->current_bandtype == BAND_ON_5G) -+ val_y += 3; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%x\n", val_y); -+ -+ rtl_set_bbreg(hw, RTX_IQK_TONE_B, 0x3FF, val_y); -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), 0); -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe50 = 0x%x\n", -+ rtl_get_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD)); -+ -+ if (txonly) { -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n"); -+ return; -+ } -+ -+ reg = result[final_candidate][6]; -+ rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); -+ reg = result[final_candidate][7] & 0x3F; -+ rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); -+ reg = (result[final_candidate][7] >> 6) & 0xF; -+ rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); -+ } else { -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "%s: Tx/Rx fail restore default value\n", __func__); -+ -+ rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x19008c00); -+ rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); -+ rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x19008c00); -+ } -+} -+ -+static void _rtl92du_phy_pathb_fill_iqk_matrix(struct ieee80211_hw *hw, -+ bool iqk_ok, long result[][8], -+ u8 final_candidate, bool txonly) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; -+ u32 oldval_1, val_x, tx1_a, reg; -+ long val_y, tx1_c; -+ -+ if (rtlhal->current_bandtype == BAND_ON_5G) { -+ _rtl92du_phy_pathb_fill_iqk_matrix_5g_normal(hw, iqk_ok, result, -+ final_candidate, -+ txonly); -+ return; -+ } -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n", -+ iqk_ok ? "Success" : "Failed"); -+ -+ if (final_candidate == 0xFF || !iqk_ok) -+ return; -+ -+ oldval_1 = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0xffc00000); -+ -+ val_x = result[final_candidate][4]; -+ if ((val_x & 0x00000200) != 0) -+ val_x = val_x | 0xFFFFFC00; -+ -+ tx1_a = (val_x * oldval_1) >> 8; -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n", -+ val_x, tx1_a); -+ rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28), -+ (val_x * oldval_1 >> 7) & 0x1); -+ -+ val_y = result[final_candidate][5]; -+ if ((val_y & 0x00000200) != 0) -+ val_y = val_y | 0xFFFFFC00; -+ -+ if (rtlhal->current_bandtype == BAND_ON_5G) -+ val_y += 3; -+ -+ tx1_c = (val_y * oldval_1) >> 8; -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n", -+ val_y, tx1_c); -+ -+ rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, (tx1_c & 0x3C0) >> 6); -+ rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, tx1_c & 0x3F); -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30), -+ (val_y * oldval_1 >> 7) & 0x1); -+ -+ if (txonly) -+ return; -+ -+ reg = result[final_candidate][6]; -+ rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); -+ reg = result[final_candidate][7] & 0x3F; -+ rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); -+ reg = (result[final_candidate][7] >> 6) & 0xF; -+ rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); -+} -+ -+void rtl92du_phy_iq_calibrate(struct ieee80211_hw *hw) -+{ -+ long rege94, rege9c, regea4, regeac, regeb4; -+ bool is12simular, is13simular, is23simular; -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; -+ long regebc, regec4, regecc, regtmp = 0; -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u8 i, final_candidate, indexforchannel; -+ bool patha_ok, pathb_ok; -+ long result[4][8] = {}; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "IQK:Start!!!channel %d\n", rtlphy->current_channel); -+ -+ final_candidate = 0xff; -+ patha_ok = false; -+ pathb_ok = false; -+ is12simular = false; -+ is23simular = false; -+ is13simular = false; -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "IQK !!!currentband %d\n", rtlhal->current_bandtype); -+ -+ for (i = 0; i < 3; i++) { -+ if (rtlhal->current_bandtype == BAND_ON_5G) { -+ _rtl92du_phy_iq_calibrate_5g_normal(hw, result, i); -+ } else if (rtlhal->current_bandtype == BAND_ON_2_4G) { -+ if (IS_92D_SINGLEPHY(rtlhal->version)) -+ _rtl92du_phy_iq_calibrate(hw, result, i, true); -+ else -+ _rtl92du_phy_iq_calibrate(hw, result, i, false); -+ } -+ -+ if (i == 1) { -+ is12simular = _rtl92du_phy_simularity_compare(hw, result, -+ 0, 1); -+ if (is12simular) { -+ final_candidate = 0; -+ break; -+ } -+ } -+ -+ if (i == 2) { -+ is13simular = _rtl92du_phy_simularity_compare(hw, result, -+ 0, 2); -+ if (is13simular) { -+ final_candidate = 0; -+ break; -+ } -+ -+ is23simular = _rtl92du_phy_simularity_compare(hw, result, -+ 1, 2); -+ if (is23simular) { -+ final_candidate = 1; -+ } else { -+ for (i = 0; i < 8; i++) -+ regtmp += result[3][i]; -+ -+ if (regtmp != 0) -+ final_candidate = 3; -+ else -+ final_candidate = 0xFF; -+ } -+ } -+ } -+ -+ for (i = 0; i < 4; i++) { -+ rege94 = result[i][0]; -+ rege9c = result[i][1]; -+ regea4 = result[i][2]; -+ regeac = result[i][3]; -+ regeb4 = result[i][4]; -+ regebc = result[i][5]; -+ regec4 = result[i][6]; -+ regecc = result[i][7]; -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n", -+ rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, -+ regecc); -+ } -+ -+ if (final_candidate != 0xff) { -+ rege94 = result[final_candidate][0]; -+ rtlphy->reg_e94 = rege94; -+ rege9c = result[final_candidate][1]; -+ rtlphy->reg_e9c = rege9c; -+ regea4 = result[final_candidate][2]; -+ regeac = result[final_candidate][3]; -+ regeb4 = result[final_candidate][4]; -+ rtlphy->reg_eb4 = regeb4; -+ regebc = result[final_candidate][5]; -+ rtlphy->reg_ebc = regebc; -+ regec4 = result[final_candidate][6]; -+ regecc = result[final_candidate][7]; -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "IQK: final_candidate is %x\n", final_candidate); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "IQK: rege94=%lx rege9c=%lx regea4=%lx regeac=%lx regeb4=%lx regebc=%lx regec4=%lx regecc=%lx\n", -+ rege94, rege9c, regea4, regeac, regeb4, regebc, regec4, -+ regecc); -+ -+ patha_ok = true; -+ pathb_ok = true; -+ } else { -+ rtlphy->reg_e94 = 0x100; -+ rtlphy->reg_eb4 = 0x100; /* X default value */ -+ rtlphy->reg_e9c = 0x0; -+ rtlphy->reg_ebc = 0x0; /* Y default value */ -+ } -+ if (rege94 != 0 /*&& regea4 != 0*/) -+ _rtl92du_phy_patha_fill_iqk_matrix(hw, patha_ok, result, -+ final_candidate, -+ regea4 == 0); -+ if (IS_92D_SINGLEPHY(rtlhal->version) && -+ regeb4 != 0 /*&& regec4 != 0*/) -+ _rtl92du_phy_pathb_fill_iqk_matrix(hw, pathb_ok, result, -+ final_candidate, -+ regec4 == 0); -+ -+ if (final_candidate != 0xFF) { -+ indexforchannel = -+ rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel); -+ -+ for (i = 0; i < IQK_MATRIX_REG_NUM; i++) -+ rtlphy->iqk_matrix[indexforchannel].value[0][i] = -+ result[final_candidate][i]; -+ -+ rtlphy->iqk_matrix[indexforchannel].iqk_done = true; -+ -+ rtl_dbg(rtlpriv, COMP_SCAN | COMP_MLME, DBG_LOUD, -+ "IQK OK indexforchannel %d\n", indexforchannel); -+ } -+} -+ -+void rtl92du_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ struct rtl_mac *mac = rtl_mac(rtlpriv); -+ u8 indexforchannel; -+ bool need_iqk; -+ -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "channel %d\n", channel); -+ /*------Do IQK for normal chip and test chip 5G band------- */ -+ -+ indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel); -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "indexforchannel %d done %d\n", -+ indexforchannel, -+ rtlphy->iqk_matrix[indexforchannel].iqk_done); -+ -+ /* We need to do IQK if we're about to connect to a network on 5 GHz. -+ * On 5 GHz a channel switch outside of scanning happens only before -+ * connecting. -+ */ -+ need_iqk = !mac->act_scanning; -+ -+ if (!rtlphy->iqk_matrix[indexforchannel].iqk_done && need_iqk) { -+ rtl_dbg(rtlpriv, COMP_SCAN | COMP_INIT, DBG_LOUD, -+ "Do IQK Matrix reg for channel:%d....\n", channel); -+ rtl92du_phy_iq_calibrate(hw); -+ return; -+ } -+ -+ /* Just load the value. */ -+ /* 2G band just load once. */ -+ if ((!rtlhal->load_imrandiqk_setting_for2g && indexforchannel == 0) || -+ indexforchannel > 0) { -+ rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, -+ "Just Read IQK Matrix reg for channel:%d....\n", -+ channel); -+ -+ if (rtlphy->iqk_matrix[indexforchannel].value[0][0] != 0) -+ _rtl92du_phy_patha_fill_iqk_matrix(hw, true, -+ rtlphy->iqk_matrix[indexforchannel].value, 0, -+ rtlphy->iqk_matrix[indexforchannel].value[0][2] == 0); -+ -+ if (IS_92D_SINGLEPHY(rtlhal->version) && -+ rtlphy->iqk_matrix[indexforchannel].value[0][4] != 0) -+ _rtl92du_phy_pathb_fill_iqk_matrix(hw, true, -+ rtlphy->iqk_matrix[indexforchannel].value, 0, -+ rtlphy->iqk_matrix[indexforchannel].value[0][6] == 0); -+ } -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); -+} -+ -+static void _rtl92du_phy_reload_lck_setting(struct ieee80211_hw *hw, u8 channel) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; -+ u8 erfpath = rtlhal->current_bandtype == BAND_ON_5G ? RF90_PATH_A : -+ IS_92D_SINGLEPHY(rtlhal->version) ? RF90_PATH_B : RF90_PATH_A; -+ bool bneed_powerdown_radio = false; -+ u32 u4tmp, u4regvalue; -+ -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "path %d\n", erfpath); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "band type = %d\n", -+ rtlpriv->rtlhal.current_bandtype); -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "channel = %d\n", channel); -+ -+ if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) {/* Path-A for 5G */ -+ u4tmp = rtlpriv->curveindex_5g[channel - 1]; -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); -+ -+ if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && -+ rtlpriv->rtlhal.interfaceindex == 1) { -+ bneed_powerdown_radio = -+ rtl92du_phy_enable_anotherphy(hw, false); -+ rtlpriv->rtlhal.during_mac1init_radioa = true; -+ /* asume no this case */ -+ if (bneed_powerdown_radio) -+ rtl92d_phy_enable_rf_env(hw, erfpath, -+ &u4regvalue); -+ } -+ -+ rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); -+ -+ if (bneed_powerdown_radio) { -+ rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); -+ rtl92du_phy_powerdown_anotherphy(hw, false); -+ } -+ } else if (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) { -+ u4tmp = rtlpriv->curveindex_2g[channel - 1]; -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); -+ -+ if (rtlpriv->rtlhal.macphymode == DUALMAC_DUALPHY && -+ rtlpriv->rtlhal.interfaceindex == 0) { -+ bneed_powerdown_radio = -+ rtl92du_phy_enable_anotherphy(hw, true); -+ rtlpriv->rtlhal.during_mac0init_radiob = true; -+ if (bneed_powerdown_radio) -+ rtl92d_phy_enable_rf_env(hw, erfpath, -+ &u4regvalue); -+ } -+ -+ rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", -+ rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)); -+ -+ if (bneed_powerdown_radio) { -+ rtl92d_phy_restore_rf_env(hw, erfpath, &u4regvalue); -+ rtl92du_phy_powerdown_anotherphy(hw, true); -+ } -+ } -+ rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "<====\n"); -+} -+ -+static void _rtl92du_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; -+ u32 curvecount_val[CV_CURVE_CNT * 2]; -+ u16 timeout = 800, timecount = 0; -+ u32 u4tmp, offset, rf_syn_g4[2]; -+ u8 tmpreg, index, rf_mode[2]; -+ u8 path = is2t ? 2 : 1; -+ u8 i; -+ -+ /* Check continuous TX and Packet TX */ -+ tmpreg = rtl_read_byte(rtlpriv, 0xd03); -+ if ((tmpreg & 0x70) != 0) -+ /* if Deal with contisuous TX case, disable all continuous TX */ -+ rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); -+ else -+ /* if Deal with Packet TX case, block all queues */ -+ rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); -+ -+ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); -+ -+ for (index = 0; index < path; index++) { -+ /* 1. Read original RF mode */ -+ offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; -+ rf_mode[index] = rtl_read_byte(rtlpriv, offset); -+ -+ /* 2. Set RF mode = standby mode */ -+ rtl_set_rfreg(hw, (enum radio_path)index, RF_AC, -+ RFREG_OFFSET_MASK, 0x010000); -+ -+ rf_syn_g4[index] = rtl_get_rfreg(hw, index, RF_SYN_G4, -+ RFREG_OFFSET_MASK); -+ rtl_set_rfreg(hw, index, RF_SYN_G4, 0x700, 0x7); -+ -+ /* switch CV-curve control by LC-calibration */ -+ rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, -+ BIT(17), 0x0); -+ -+ /* 4. Set LC calibration begin */ -+ rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, -+ 0x08000, 0x01); -+ } -+ -+ for (index = 0; index < path; index++) { -+ u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, RF_SYN_G6, -+ RFREG_OFFSET_MASK); -+ -+ while ((!(u4tmp & BIT(11))) && timecount <= timeout) { -+ mdelay(50); -+ timecount += 50; -+ u4tmp = rtl_get_rfreg(hw, (enum radio_path)index, -+ RF_SYN_G6, RFREG_OFFSET_MASK); -+ } -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "PHY_LCK finish delay for %d ms=2\n", timecount); -+ } -+ -+ if ((tmpreg & 0x70) != 0) -+ rtl_write_byte(rtlpriv, 0xd03, tmpreg); -+ else /* Deal with Packet TX case */ -+ rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); -+ -+ rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); -+ -+ for (index = 0; index < path; index++) { -+ rtl_get_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK); -+ -+ if (index == 0 && rtlhal->interfaceindex == 0) { -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "path-A / 5G LCK\n"); -+ } else { -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "path-B / 2.4G LCK\n"); -+ } -+ -+ memset(curvecount_val, 0, sizeof(curvecount_val)); -+ -+ /* Set LC calibration off */ -+ rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW, -+ 0x08000, 0x0); -+ -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n"); -+ -+ /* save Curve-counting number */ -+ for (i = 0; i < CV_CURVE_CNT; i++) { -+ u32 readval = 0, readval2 = 0; -+ -+ rtl_set_rfreg(hw, (enum radio_path)index, 0x3F, -+ 0x7f, i); -+ -+ rtl_set_rfreg(hw, (enum radio_path)index, 0x4D, -+ RFREG_OFFSET_MASK, 0x0); -+ -+ readval = rtl_get_rfreg(hw, (enum radio_path)index, -+ 0x4F, RFREG_OFFSET_MASK); -+ curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5; -+ -+ /* reg 0x4f [4:0] */ -+ /* reg 0x50 [19:10] */ -+ readval2 = rtl_get_rfreg(hw, (enum radio_path)index, -+ 0x50, 0xffc00); -+ curvecount_val[2 * i] = (((readval & 0x1F) << 10) | -+ readval2); -+ } -+ -+ if (index == 0 && rtlhal->interfaceindex == 0) -+ rtl92d_phy_calc_curvindex(hw, targetchnl_5g, -+ curvecount_val, -+ true, rtlpriv->curveindex_5g); -+ else -+ rtl92d_phy_calc_curvindex(hw, targetchnl_2g, -+ curvecount_val, -+ false, rtlpriv->curveindex_2g); -+ -+ /* switch CV-curve control mode */ -+ rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7, -+ BIT(17), 0x1); -+ } -+ -+ /* Restore original situation */ -+ for (index = 0; index < path; index++) { -+ rtl_set_rfreg(hw, index, RF_SYN_G4, RFREG_OFFSET_MASK, -+ rf_syn_g4[index]); -+ -+ offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; -+ rtl_write_byte(rtlpriv, offset, 0x50); -+ rtl_write_byte(rtlpriv, offset, rf_mode[index]); -+ } -+ -+ _rtl92du_phy_reload_lck_setting(hw, rtlpriv->phy.current_channel); -+} -+ -+void rtl92du_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u32 timeout = 2000, timecount = 0; -+ -+ while (rtlpriv->mac80211.act_scanning && timecount < timeout) { -+ udelay(50); -+ timecount += 50; -+ } -+ -+ rtlphy->lck_inprogress = true; -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, -+ "LCK:Start!!! currentband %x delay %d ms\n", -+ rtlhal->current_bandtype, timecount); -+ -+ _rtl92du_phy_lc_calibrate_sw(hw, is2t); -+ -+ rtlphy->lck_inprogress = false; -+ RTPRINT(rtlpriv, FINIT, INIT_IQK, "LCK:Finish!!!\n"); -+} -+ -+void rtl92du_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta) -+{ -+ /* Nothing to do. */ -+} -+ -+u8 rtl92du_phy_sw_chnl(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u8 num_total_rfpath = rtlphy->num_total_rfpath; -+ u8 channel = rtlphy->current_channel; -+ u32 timeout = 1000, timecount = 0; -+ u32 ret_value; -+ u8 rfpath; -+ -+ if (rtlphy->sw_chnl_inprogress) -+ return 0; -+ if (rtlphy->set_bwmode_inprogress) -+ return 0; -+ -+ if ((is_hal_stop(rtlhal)) || (RT_CANNOT_IO(hw))) { -+ rtl_dbg(rtlpriv, COMP_CHAN, DBG_LOUD, -+ "sw_chnl_inprogress false driver sleep or unload\n"); -+ return 0; -+ } -+ -+ while (rtlphy->lck_inprogress && timecount < timeout) { -+ mdelay(50); -+ timecount += 50; -+ } -+ -+ if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY && -+ rtlhal->bandset == BAND_ON_BOTH) { -+ ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER, -+ MASKDWORD); -+ if (rtlphy->current_channel > 14 && !(ret_value & BIT(0))) -+ rtl92du_phy_switch_wirelessband(hw, BAND_ON_5G); -+ else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0))) -+ rtl92du_phy_switch_wirelessband(hw, BAND_ON_2_4G); -+ } -+ -+ switch (rtlhal->current_bandtype) { -+ case BAND_ON_5G: -+ /* Get first channel error when change between -+ * 5G and 2.4G band. -+ */ -+ if (WARN_ONCE(channel <= 14, "rtl8192du: 5G but channel<=14\n")) -+ return 0; -+ break; -+ case BAND_ON_2_4G: -+ /* Get first channel error when change between -+ * 5G and 2.4G band. -+ */ -+ if (WARN_ONCE(channel > 14, "rtl8192du: 2G but channel>14\n")) -+ return 0; -+ break; -+ default: -+ WARN_ONCE(true, "rtl8192du: Invalid WirelessMode(%#x)!!\n", -+ rtlpriv->mac80211.mode); -+ break; -+ } -+ -+ rtlphy->sw_chnl_inprogress = true; -+ -+ rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, -+ "switch to channel%d\n", rtlphy->current_channel); -+ -+ rtl92d_phy_set_txpower_level(hw, channel); -+ -+ for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { -+ u32p_replace_bits(&rtlphy->rfreg_chnlval[rfpath], -+ channel, 0xff); -+ -+ if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) { -+ if (channel > 99) -+ rtlphy->rfreg_chnlval[rfpath] |= (BIT(18)); -+ else -+ rtlphy->rfreg_chnlval[rfpath] &= ~BIT(18); -+ rtlphy->rfreg_chnlval[rfpath] |= (BIT(16) | BIT(8)); -+ } else { -+ rtlphy->rfreg_chnlval[rfpath] &= -+ ~(BIT(8) | BIT(16) | BIT(18)); -+ } -+ rtl_set_rfreg(hw, rfpath, RF_CHNLBW, RFREG_OFFSET_MASK, -+ rtlphy->rfreg_chnlval[rfpath]); -+ -+ _rtl92du_phy_reload_imr_setting(hw, channel, rfpath); -+ } -+ -+ _rtl92du_phy_switch_rf_setting(hw, channel); -+ -+ /* do IQK when all parameters are ready */ -+ rtl92du_phy_reload_iqk_setting(hw, channel); -+ -+ rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n"); -+ rtlphy->sw_chnl_inprogress = false; -+ return 1; -+} -+ -+static void _rtl92du_phy_set_rfon(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */ -+ /* b. SPS_CTRL 0x11[7:0] = 0x2b */ -+ if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) -+ rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); -+ -+ /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */ -+ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); -+ -+ /* RF_ON_EXCEP(d~g): */ -+ /* d. APSD_CTRL 0x600[7:0] = 0x00 */ -+ rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); -+ -+ /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */ -+ /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/ -+ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); -+ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); -+ -+ /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */ -+ rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); -+} -+ -+static void _rtl92du_phy_set_rfsleep(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ u32 u4btmp; -+ u8 retry = 5; -+ -+ /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ -+ rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); -+ -+ /* b. RF path 0 offset 0x00 = 0x00 disable RF */ -+ rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); -+ -+ /* c. APSD_CTRL 0x600[7:0] = 0x40 */ -+ rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); -+ -+ /* d. APSD_CTRL 0x600[7:0] = 0x00 -+ * APSD_CTRL 0x600[7:0] = 0x00 -+ * RF path 0 offset 0x00 = 0x00 -+ * APSD_CTRL 0x600[7:0] = 0x40 -+ */ -+ u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); -+ while (u4btmp != 0 && retry > 0) { -+ rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); -+ rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); -+ rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); -+ u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); -+ retry--; -+ } -+ if (retry == 0) { -+ /* Jump out the LPS turn off sequence to RF_ON_EXCEP */ -+ rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); -+ -+ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); -+ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); -+ rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); -+ rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, -+ "Fail !!! Switch RF timeout\n"); -+ return; -+ } -+ -+ /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */ -+ rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); -+ -+ /* f. SPS_CTRL 0x11[7:0] = 0x22 */ -+ if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) -+ rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); -+} -+ -+bool rtl92du_phy_set_rf_power_state(struct ieee80211_hw *hw, -+ enum rf_pwrstate rfpwr_state) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); -+ struct rtl_mac *mac = rtl_mac(rtlpriv); -+ bool bresult = true; -+ -+ if (rfpwr_state == ppsc->rfpwr_state) -+ return false; -+ -+ switch (rfpwr_state) { -+ case ERFON: -+ if (ppsc->rfpwr_state == ERFOFF && -+ RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) { -+ u32 initializecount = 0; -+ bool rtstatus; -+ -+ do { -+ initializecount++; -+ rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, -+ "IPS Set eRf nic enable\n"); -+ rtstatus = rtl_ps_enable_nic(hw); -+ } while (!rtstatus && (initializecount < 10)); -+ -+ RT_CLEAR_PS_LEVEL(ppsc, -+ RT_RF_OFF_LEVL_HALT_NIC); -+ } else { -+ rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, -+ "awake, slept:%d ms state_inap:%x\n", -+ jiffies_to_msecs(jiffies - -+ ppsc->last_sleep_jiffies), -+ rtlpriv->psc.state_inap); -+ ppsc->last_awake_jiffies = jiffies; -+ _rtl92du_phy_set_rfon(hw); -+ } -+ -+ if (mac->link_state == MAC80211_LINKED) -+ rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK); -+ else -+ rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK); -+ break; -+ case ERFOFF: -+ if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) { -+ rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, -+ "IPS Set eRf nic disable\n"); -+ rtl_ps_disable_nic(hw); -+ RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); -+ } else { -+ if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) -+ rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK); -+ else -+ rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); -+ } -+ break; -+ case ERFSLEEP: -+ if (ppsc->rfpwr_state == ERFOFF) -+ return false; -+ -+ rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, -+ "sleep awakened:%d ms state_inap:%x\n", -+ jiffies_to_msecs(jiffies - -+ ppsc->last_awake_jiffies), -+ rtlpriv->psc.state_inap); -+ ppsc->last_sleep_jiffies = jiffies; -+ _rtl92du_phy_set_rfsleep(hw); -+ break; -+ default: -+ pr_err("switch case %#x not processed\n", -+ rfpwr_state); -+ return false; -+ } -+ -+ if (bresult) -+ ppsc->rfpwr_state = rfpwr_state; -+ -+ return bresult; -+} -+ -+void rtl92du_phy_set_poweron(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1); -+ u8 value8; -+ u16 i; -+ -+ /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ -+ if (rtlhal->current_bandtype == BAND_ON_2_4G) { -+ value8 = rtl_read_byte(rtlpriv, mac_reg); -+ value8 |= BIT(1); -+ rtl_write_byte(rtlpriv, mac_reg, value8); -+ } else { -+ value8 = rtl_read_byte(rtlpriv, mac_reg); -+ value8 &= ~BIT(1); -+ rtl_write_byte(rtlpriv, mac_reg, value8); -+ } -+ -+ if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { -+ value8 = rtl_read_byte(rtlpriv, REG_MAC0); -+ rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); -+ } else { -+ mutex_lock(rtlpriv->mutex_for_power_on_off); -+ if (rtlhal->interfaceindex == 0) { -+ value8 = rtl_read_byte(rtlpriv, REG_MAC0); -+ rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON); -+ } else { -+ value8 = rtl_read_byte(rtlpriv, REG_MAC1); -+ rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON); -+ } -+ value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); -+ mutex_unlock(rtlpriv->mutex_for_power_on_off); -+ -+ for (i = 0; i < 200; i++) { -+ if ((value8 & BIT(7)) == 0) -+ break; -+ -+ udelay(500); -+ mutex_lock(rtlpriv->mutex_for_power_on_off); -+ value8 = rtl_read_byte(rtlpriv, -+ REG_POWER_OFF_IN_PROCESS); -+ mutex_unlock(rtlpriv->mutex_for_power_on_off); -+ } -+ if (i == 200) -+ WARN_ONCE(true, "rtl8192du: Another mac power off over time\n"); -+ } -+} -+ -+void rtl92du_update_bbrf_configuration(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ u8 rfpath, i; -+ -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n"); -+ /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */ -+ if (rtlhal->current_bandtype == BAND_ON_2_4G) { -+ /* r_select_5G for path_A/B, 0x878 */ -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); -+ if (rtlhal->macphymode != DUALMAC_DUALPHY) { -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); -+ } -+ -+ /* rssi_table_select: index 0 for 2.4G. 1~3 for 5G, 0xc78 */ -+ rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); -+ -+ /* fc_area 0xd2c */ -+ rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); -+ -+ /* 5G LAN ON */ -+ rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); -+ -+ /* TX BB gain shift*1, Just for testchip, 0xc80, 0xc88 */ -+ rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, 0x40000100); -+ rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD, 0x40000100); -+ if (rtlhal->macphymode == DUALMAC_DUALPHY) { -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, -+ BIT(10) | BIT(6) | BIT(5), -+ ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | -+ (rtlefuse->eeprom_c9 & BIT(1)) | -+ ((rtlefuse->eeprom_cc & BIT(1)) << 4)); -+ rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, -+ BIT(10) | BIT(6) | BIT(5), -+ ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | -+ ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | -+ ((rtlefuse->eeprom_cc & BIT(0)) << 5)); -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); -+ -+ rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038); -+ rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000); -+ } else { -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, -+ BIT(26) | BIT(22) | BIT(21) | BIT(10) | -+ BIT(6) | BIT(5), -+ ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) | -+ (rtlefuse->eeprom_c9 & BIT(1)) | -+ ((rtlefuse->eeprom_cc & BIT(1)) << 4) | -+ ((rtlefuse->eeprom_c9 & BIT(7)) << 9) | -+ ((rtlefuse->eeprom_c9 & BIT(5)) << 12) | -+ ((rtlefuse->eeprom_cc & BIT(3)) << 18)); -+ rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, -+ BIT(10) | BIT(6) | BIT(5), -+ ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) | -+ ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | -+ ((rtlefuse->eeprom_cc & BIT(0)) << 5)); -+ rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, -+ BIT(10) | BIT(6) | BIT(5), -+ ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) | -+ ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) | -+ ((rtlefuse->eeprom_cc & BIT(2)) << 3)); -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, -+ BIT(31) | BIT(15), 0); -+ -+ rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038); -+ rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x01017038); -+ rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000); -+ rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x0f600000); -+ } -+ /* 1.5V_LDO */ -+ } else { -+ /* r_select_5G for path_A/B */ -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); -+ if (rtlhal->macphymode != DUALMAC_DUALPHY) { -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); -+ } -+ -+ /* rssi_table_select: index 0 for 2.4G. 1~3 for 5G */ -+ rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); -+ -+ /* fc_area */ -+ rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); -+ -+ /* 5G LAN ON */ -+ rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); -+ -+ /* TX BB gain shift, Just for testchip, 0xc80, 0xc88 */ -+ if (rtlefuse->internal_pa_5g[rtlhal->interfaceindex]) -+ rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, -+ 0x2d4000b5); -+ else -+ rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD, -+ 0x20000080); -+ -+ if (rtlhal->macphymode != DUALMAC_DUALPHY) { -+ if (rtlefuse->internal_pa_5g[1]) -+ rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, -+ MASKDWORD, 0x2d4000b5); -+ else -+ rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, -+ MASKDWORD, 0x20000080); -+ } -+ -+ rtl_set_bbreg(hw, 0xB30, BIT(27), 0); -+ -+ if (rtlhal->macphymode == DUALMAC_DUALPHY) { -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, -+ BIT(10) | BIT(6) | BIT(5), -+ (rtlefuse->eeprom_cc & BIT(5))); -+ rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), -+ ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), -+ (rtlefuse->eeprom_cc & BIT(4)) >> 4); -+ -+ rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017098); -+ rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000); -+ } else { -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, -+ BIT(26) | BIT(22) | BIT(21) | BIT(10) | -+ BIT(6) | BIT(5), -+ (rtlefuse->eeprom_cc & BIT(5)) | -+ ((rtlefuse->eeprom_cc & BIT(7)) << 14)); -+ rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), -+ ((rtlefuse->eeprom_cc & BIT(4)) >> 4)); -+ rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), -+ ((rtlefuse->eeprom_cc & BIT(6)) >> 6)); -+ rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, -+ BIT(31) | BIT(15), -+ ((rtlefuse->eeprom_cc & BIT(4)) >> 4) | -+ ((rtlefuse->eeprom_cc & BIT(6)) << 10)); -+ -+ rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017098); -+ rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x01017098); -+ rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x20000000); -+ rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x20000000); -+ } -+ } -+ -+ /* update IQK related settings */ -+ rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); -+ rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); -+ rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00); -+ rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) | -+ BIT(26) | BIT(24), 0x00); -+ rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00); -+ rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, 0x00); -+ rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); -+ -+ /* Update RF */ -+ for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; -+ rfpath++) { -+ if (rtlhal->current_bandtype == BAND_ON_2_4G) { -+ /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ -+ rtl_set_rfreg(hw, rfpath, RF_CHNLBW, BIT(8) | BIT(16) | -+ BIT(18) | 0xff, 1); -+ -+ /* RF0x0b[16:14] =3b'111 */ -+ rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, -+ 0x1c000, 0x07); -+ } else { -+ /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, -+ 0x97524); -+ } -+ -+ /* Set right channel on RF reg0x18 for another mac. */ -+ if (rtlhal->interfaceindex == 0 && rtlhal->bandset == BAND_ON_2_4G) { -+ /* Set MAC1 default channel if MAC1 not up. */ -+ if (!(rtl_read_byte(rtlpriv, REG_MAC1) & MAC1_ON)) { -+ rtl92du_phy_enable_anotherphy(hw, true); -+ rtlhal->during_mac0init_radiob = true; -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, -+ RFREG_OFFSET_MASK, 0x97524); -+ rtl92du_phy_powerdown_anotherphy(hw, true); -+ } -+ } else if (rtlhal->interfaceindex == 1 && rtlhal->bandset == BAND_ON_5G) { -+ /* Set MAC0 default channel */ -+ if (!(rtl_read_byte(rtlpriv, REG_MAC0) & MAC0_ON)) { -+ rtl92du_phy_enable_anotherphy(hw, false); -+ rtlhal->during_mac1init_radioa = true; -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, -+ RFREG_OFFSET_MASK, 0x87401); -+ rtl92du_phy_powerdown_anotherphy(hw, false); -+ } -+ } -+ } -+ -+ /* Update for all band. */ -+ /* DMDP */ -+ if (rtlphy->rf_type == RF_1T1R) { -+ /* Use antenna 0, 0xc04, 0xd04 */ -+ rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); -+ rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); -+ -+ /* enable ad/da clock1 for dual-phy reg0x888 */ -+ if (rtlhal->interfaceindex == 0) { -+ rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | -+ BIT(13), 0x3); -+ } else if (rtl92du_phy_enable_anotherphy(hw, false)) { -+ rtlhal->during_mac1init_radioa = true; -+ rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, -+ BIT(12) | BIT(13), 0x3); -+ rtl92du_phy_powerdown_anotherphy(hw, false); -+ } -+ -+ rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(19) | BIT(20), 0x0); -+ } else { -+ /* Single PHY */ -+ /* Use antenna 0 & 1, 0xc04, 0xd04 */ -+ rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); -+ rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); -+ /* disable ad/da clock1,0x888 */ -+ rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); -+ -+ rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(19) | BIT(20), 0x1); -+ } -+ -+ for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; -+ rfpath++) { -+ rtlphy->rfreg_chnlval[rfpath] = rtl_get_rfreg(hw, rfpath, -+ RF_CHNLBW, -+ RFREG_OFFSET_MASK); -+ rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C, -+ RFREG_OFFSET_MASK); -+ } -+ -+ for (i = 0; i < 2; i++) -+ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n", -+ rtlphy->rfreg_chnlval[i]); -+ -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==\n"); -+} -+ -+bool rtl92du_phy_check_poweroff(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); -+ u8 u1btmp; -+ -+ if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) { -+ u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); -+ rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & ~MAC0_ON); -+ return true; -+ } -+ -+ mutex_lock(rtlpriv->mutex_for_power_on_off); -+ if (rtlhal->interfaceindex == 0) { -+ u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); -+ rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & ~MAC0_ON); -+ u1btmp = rtl_read_byte(rtlpriv, REG_MAC1); -+ u1btmp &= MAC1_ON; -+ } else { -+ u1btmp = rtl_read_byte(rtlpriv, REG_MAC1); -+ rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & ~MAC1_ON); -+ u1btmp = rtl_read_byte(rtlpriv, REG_MAC0); -+ u1btmp &= MAC0_ON; -+ } -+ if (u1btmp) { -+ mutex_unlock(rtlpriv->mutex_for_power_on_off); -+ return false; -+ } -+ u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS); -+ u1btmp |= BIT(7); -+ rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp); -+ mutex_unlock(rtlpriv->mutex_for_power_on_off); -+ -+ return true; -+} -+ -+void rtl92du_phy_init_pa_bias(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ bool is_single_mac = rtlhal->macphymode == SINGLEMAC_SINGLEPHY; -+ enum radio_path rf_path; -+ u8 val8; -+ -+ read_efuse_byte(hw, 0x3FA, &val8); -+ -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "%s: 0x3FA %#x\n", -+ __func__, val8); -+ -+ if (!(val8 & BIT(0)) && (is_single_mac || rtlhal->interfaceindex == 0)) { -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 0x07401); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x70000); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x0F425); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x4F425); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x8F425); -+ -+ /* Back to RX Mode */ -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x30000); -+ -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "2G PA BIAS path A\n"); -+ } -+ -+ if (!(val8 & BIT(1)) && (is_single_mac || rtlhal->interfaceindex == 1)) { -+ rf_path = rtlhal->interfaceindex == 1 ? RF90_PATH_A : RF90_PATH_B; -+ -+ rtl_set_rfreg(hw, rf_path, RF_CHNLBW, RFREG_OFFSET_MASK, 0x07401); -+ rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x70000); -+ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x0F425); -+ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x4F425); -+ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x8F425); -+ -+ /* Back to RX Mode */ -+ rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x30000); -+ -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "2G PA BIAS path B\n"); -+ } -+ -+ if (!(val8 & BIT(2)) && (is_single_mac || rtlhal->interfaceindex == 0)) { -+ /* 5GL_channel */ -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 0x17524); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x70000); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); -+ -+ /* 5GM_channel */ -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 0x37564); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x70000); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); -+ -+ /* 5GH_channel */ -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK, 0x57595); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x70000); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); -+ -+ /* Back to RX Mode */ -+ rtl_set_rfreg(hw, RF90_PATH_A, RF_AC, RFREG_OFFSET_MASK, 0x30000); -+ -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "5G PA BIAS path A\n"); -+ } -+ -+ if (!(val8 & BIT(3)) && (is_single_mac || rtlhal->interfaceindex == 1)) { -+ rf_path = rtlhal->interfaceindex == 1 ? RF90_PATH_A : RF90_PATH_B; -+ -+ /* 5GL_channel */ -+ rtl_set_rfreg(hw, rf_path, RF_CHNLBW, RFREG_OFFSET_MASK, 0x17524); -+ rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x70000); -+ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); -+ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); -+ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); -+ -+ /* 5GM_channel */ -+ rtl_set_rfreg(hw, rf_path, RF_CHNLBW, RFREG_OFFSET_MASK, 0x37564); -+ rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x70000); -+ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); -+ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); -+ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); -+ -+ /* 5GH_channel */ -+ rtl_set_rfreg(hw, rf_path, RF_CHNLBW, RFREG_OFFSET_MASK, 0x57595); -+ rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x70000); -+ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x0F496); -+ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x4F496); -+ rtl_set_rfreg(hw, rf_path, RF_IPA, RFREG_OFFSET_MASK, 0x8F496); -+ -+ /* Back to RX Mode */ -+ rtl_set_rfreg(hw, rf_path, RF_AC, RFREG_OFFSET_MASK, 0x30000); -+ -+ rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "5G PA BIAS path B\n"); -+ } -+} -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.h -new file mode 100644 -index 000000000000..090a6203db7e ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.h -@@ -0,0 +1,32 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#ifndef __RTL92DU_PHY_H__ -+#define __RTL92DU_PHY_H__ -+ -+u32 rtl92du_phy_query_bb_reg(struct ieee80211_hw *hw, -+ u32 regaddr, u32 bitmask); -+void rtl92du_phy_set_bb_reg(struct ieee80211_hw *hw, -+ u32 regaddr, u32 bitmask, u32 data); -+bool rtl92du_phy_mac_config(struct ieee80211_hw *hw); -+bool rtl92du_phy_bb_config(struct ieee80211_hw *hw); -+bool rtl92du_phy_rf_config(struct ieee80211_hw *hw); -+void rtl92du_phy_set_bw_mode(struct ieee80211_hw *hw, -+ enum nl80211_channel_type ch_type); -+u8 rtl92du_phy_sw_chnl(struct ieee80211_hw *hw); -+bool rtl92du_phy_config_rf_with_headerfile(struct ieee80211_hw *hw, -+ enum rf_content content, -+ enum radio_path rfpath); -+bool rtl92du_phy_set_rf_power_state(struct ieee80211_hw *hw, -+ enum rf_pwrstate rfpwr_state); -+ -+void rtl92du_phy_set_poweron(struct ieee80211_hw *hw); -+bool rtl92du_phy_check_poweroff(struct ieee80211_hw *hw); -+void rtl92du_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t); -+void rtl92du_update_bbrf_configuration(struct ieee80211_hw *hw); -+void rtl92du_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta); -+void rtl92du_phy_iq_calibrate(struct ieee80211_hw *hw); -+void rtl92du_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel); -+void rtl92du_phy_init_pa_bias(struct ieee80211_hw *hw); -+ -+#endif --- -2.34.1 - diff --git a/packages/linux/patches/rtlwifi/6.11/0006-6.11-wifi-rtlwifi-Add-rtl8192du-trx.-c-h.patch b/packages/linux/patches/rtlwifi/6.11/0006-6.11-wifi-rtlwifi-Add-rtl8192du-trx.-c-h.patch deleted file mode 100644 index 338addb7cb..0000000000 --- a/packages/linux/patches/rtlwifi/6.11/0006-6.11-wifi-rtlwifi-Add-rtl8192du-trx.-c-h.patch +++ /dev/null @@ -1,462 +0,0 @@ -From 8125d619567b9a3620244251b8eab25074cafcfa Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 23 May 2024 17:46:26 +0300 -Subject: [PATCH 06/12] 6.11: wifi: rtlwifi: Add rtl8192du/trx.{c,h} - -These contain routines related to sending frames to the chip. - -Signed-off-by: Bitterblue Smith ---- - .../wireless/realtek/rtlwifi/rtl8192du/trx.c | 372 ++++++++++++++++++ - .../wireless/realtek/rtlwifi/rtl8192du/trx.h | 60 +++ - 2 files changed, 432 insertions(+) - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.c - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.h - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.c -new file mode 100644 -index 000000000000..743ce0cfffe6 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.c -@@ -0,0 +1,372 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#include "../wifi.h" -+#include "../base.h" -+#include "../usb.h" -+#include "../rtl8192d/reg.h" -+#include "../rtl8192d/def.h" -+#include "../rtl8192d/trx_common.h" -+#include "trx.h" -+ -+void rtl92du_tx_cleanup(struct ieee80211_hw *hw, struct sk_buff *skb) -+{ -+} -+ -+int rtl92du_tx_post_hdl(struct ieee80211_hw *hw, struct urb *urb, -+ struct sk_buff *skb) -+{ -+ return 0; -+} -+ -+struct sk_buff *rtl92du_tx_aggregate_hdl(struct ieee80211_hw *hw, -+ struct sk_buff_head *list) -+{ -+ return skb_dequeue(list); -+} -+ -+static enum rtl_desc_qsel _rtl92du_hwq_to_descq(u16 queue_index) -+{ -+ switch (queue_index) { -+ case RTL_TXQ_BCN: -+ return QSLT_BEACON; -+ case RTL_TXQ_MGT: -+ return QSLT_MGNT; -+ case RTL_TXQ_VO: -+ return QSLT_VO; -+ case RTL_TXQ_VI: -+ return QSLT_VI; -+ case RTL_TXQ_BK: -+ return QSLT_BK; -+ default: -+ case RTL_TXQ_BE: -+ return QSLT_BE; -+ } -+} -+ -+/* For HW recovery information */ -+static void _rtl92du_tx_desc_checksum(__le32 *txdesc) -+{ -+ __le16 *ptr = (__le16 *)txdesc; -+ u16 checksum = 0; -+ u32 index; -+ -+ /* Clear first */ -+ set_tx_desc_tx_desc_checksum(txdesc, 0); -+ for (index = 0; index < 16; index++) -+ checksum = checksum ^ le16_to_cpu(*(ptr + index)); -+ set_tx_desc_tx_desc_checksum(txdesc, checksum); -+} -+ -+void rtl92du_tx_fill_desc(struct ieee80211_hw *hw, -+ struct ieee80211_hdr *hdr, u8 *pdesc_tx, -+ u8 *pbd_desc_tx, struct ieee80211_tx_info *info, -+ struct ieee80211_sta *sta, -+ struct sk_buff *skb, -+ u8 queue_index, -+ struct rtl_tcb_desc *tcb_desc) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ struct rtl_mac *mac = rtl_mac(rtlpriv); -+ struct rtl_sta_info *sta_entry; -+ __le16 fc = hdr->frame_control; -+ u8 agg_state = RTL_AGG_STOP; -+ u16 pktlen = skb->len; -+ u32 rts_en, hw_rts_en; -+ u8 ampdu_density = 0; -+ u16 seq_number; -+ __le32 *txdesc; -+ u8 rate_flag; -+ u8 tid; -+ -+ rtl_get_tcb_desc(hw, info, sta, skb, tcb_desc); -+ -+ txdesc = (__le32 *)skb_push(skb, RTL_TX_HEADER_SIZE); -+ memset(txdesc, 0, RTL_TX_HEADER_SIZE); -+ -+ set_tx_desc_pkt_size(txdesc, pktlen); -+ set_tx_desc_linip(txdesc, 0); -+ set_tx_desc_pkt_offset(txdesc, RTL_DUMMY_OFFSET); -+ set_tx_desc_offset(txdesc, RTL_TX_HEADER_SIZE); -+ /* 5G have no CCK rate */ -+ if (rtlhal->current_bandtype == BAND_ON_5G) -+ if (tcb_desc->hw_rate < DESC_RATE6M) -+ tcb_desc->hw_rate = DESC_RATE6M; -+ -+ set_tx_desc_tx_rate(txdesc, tcb_desc->hw_rate); -+ if (tcb_desc->use_shortgi || tcb_desc->use_shortpreamble) -+ set_tx_desc_data_shortgi(txdesc, 1); -+ -+ if (rtlhal->macphymode == DUALMAC_DUALPHY && -+ tcb_desc->hw_rate == DESC_RATEMCS7) -+ set_tx_desc_data_shortgi(txdesc, 1); -+ -+ if (sta) { -+ sta_entry = (struct rtl_sta_info *)sta->drv_priv; -+ tid = ieee80211_get_tid(hdr); -+ agg_state = sta_entry->tids[tid].agg.agg_state; -+ ampdu_density = sta->deflink.ht_cap.ampdu_density; -+ } -+ -+ if (agg_state == RTL_AGG_OPERATIONAL && -+ info->flags & IEEE80211_TX_CTL_AMPDU) { -+ set_tx_desc_agg_enable(txdesc, 1); -+ set_tx_desc_max_agg_num(txdesc, 0x14); -+ set_tx_desc_ampdu_density(txdesc, ampdu_density); -+ tcb_desc->rts_enable = 1; -+ tcb_desc->rts_rate = DESC_RATE24M; -+ } else { -+ set_tx_desc_agg_break(txdesc, 1); -+ } -+ seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; -+ set_tx_desc_seq(txdesc, seq_number); -+ -+ rts_en = tcb_desc->rts_enable && !tcb_desc->cts_enable; -+ hw_rts_en = tcb_desc->rts_enable || tcb_desc->cts_enable; -+ set_tx_desc_rts_enable(txdesc, rts_en); -+ set_tx_desc_hw_rts_enable(txdesc, hw_rts_en); -+ set_tx_desc_cts2self(txdesc, tcb_desc->cts_enable); -+ set_tx_desc_rts_stbc(txdesc, tcb_desc->rts_stbc); -+ /* 5G have no CCK rate */ -+ if (rtlhal->current_bandtype == BAND_ON_5G) -+ if (tcb_desc->rts_rate < DESC_RATE6M) -+ tcb_desc->rts_rate = DESC_RATE6M; -+ set_tx_desc_rts_rate(txdesc, tcb_desc->rts_rate); -+ set_tx_desc_rts_bw(txdesc, 0); -+ set_tx_desc_rts_sc(txdesc, tcb_desc->rts_sc); -+ set_tx_desc_rts_short(txdesc, tcb_desc->rts_use_shortpreamble); -+ -+ rate_flag = info->control.rates[0].flags; -+ if (mac->bw_40) { -+ if (rate_flag & IEEE80211_TX_RC_DUP_DATA) { -+ set_tx_desc_data_bw(txdesc, 1); -+ set_tx_desc_tx_sub_carrier(txdesc, 3); -+ } else if (rate_flag & IEEE80211_TX_RC_40_MHZ_WIDTH) { -+ set_tx_desc_data_bw(txdesc, 1); -+ set_tx_desc_tx_sub_carrier(txdesc, mac->cur_40_prime_sc); -+ } else { -+ set_tx_desc_data_bw(txdesc, 0); -+ set_tx_desc_tx_sub_carrier(txdesc, 0); -+ } -+ } else { -+ set_tx_desc_data_bw(txdesc, 0); -+ set_tx_desc_tx_sub_carrier(txdesc, 0); -+ } -+ -+ if (info->control.hw_key) { -+ struct ieee80211_key_conf *keyconf = info->control.hw_key; -+ -+ switch (keyconf->cipher) { -+ case WLAN_CIPHER_SUITE_WEP40: -+ case WLAN_CIPHER_SUITE_WEP104: -+ case WLAN_CIPHER_SUITE_TKIP: -+ set_tx_desc_sec_type(txdesc, 0x1); -+ break; -+ case WLAN_CIPHER_SUITE_CCMP: -+ set_tx_desc_sec_type(txdesc, 0x3); -+ break; -+ default: -+ set_tx_desc_sec_type(txdesc, 0x0); -+ break; -+ } -+ } -+ -+ set_tx_desc_pkt_id(txdesc, 0); -+ set_tx_desc_queue_sel(txdesc, _rtl92du_hwq_to_descq(queue_index)); -+ set_tx_desc_data_rate_fb_limit(txdesc, 0x1F); -+ set_tx_desc_rts_rate_fb_limit(txdesc, 0xF); -+ set_tx_desc_disable_fb(txdesc, 0); -+ set_tx_desc_use_rate(txdesc, tcb_desc->use_driver_rate); -+ -+ if (ieee80211_is_data_qos(fc)) { -+ if (mac->rdg_en) { -+ rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, -+ "Enable RDG function\n"); -+ set_tx_desc_rdg_enable(txdesc, 1); -+ set_tx_desc_htc(txdesc, 1); -+ } -+ set_tx_desc_qos(txdesc, 1); -+ } -+ -+ if (rtlpriv->dm.useramask) { -+ set_tx_desc_rate_id(txdesc, tcb_desc->ratr_index); -+ set_tx_desc_macid(txdesc, tcb_desc->mac_id); -+ } else { -+ set_tx_desc_rate_id(txdesc, 0xC + tcb_desc->ratr_index); -+ set_tx_desc_macid(txdesc, tcb_desc->ratr_index); -+ } -+ -+ if (!ieee80211_is_data_qos(fc) && ppsc->leisure_ps && -+ ppsc->fwctrl_lps) { -+ set_tx_desc_hwseq_en(txdesc, 1); -+ set_tx_desc_pkt_id(txdesc, 8); -+ } -+ -+ if (ieee80211_has_morefrags(fc)) -+ set_tx_desc_more_frag(txdesc, 1); -+ if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || -+ is_broadcast_ether_addr(ieee80211_get_DA(hdr))) -+ set_tx_desc_bmc(txdesc, 1); -+ -+ set_tx_desc_own(txdesc, 1); -+ set_tx_desc_last_seg(txdesc, 1); -+ set_tx_desc_first_seg(txdesc, 1); -+ _rtl92du_tx_desc_checksum(txdesc); -+ -+ rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, "==>\n"); -+} -+ -+static void _rtl92du_config_out_ep(struct ieee80211_hw *hw, u8 num_out_pipe) -+{ -+ struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ u16 ep_cfg; -+ -+ rtlusb->out_queue_sel = 0; -+ rtlusb->out_ep_nums = 0; -+ -+ if (rtlhal->interfaceindex == 0) -+ ep_cfg = rtl_read_word(rtlpriv, REG_USB_Queue_Select_MAC0); -+ else -+ ep_cfg = rtl_read_word(rtlpriv, REG_USB_Queue_Select_MAC1); -+ -+ if (ep_cfg & 0x00f) { -+ rtlusb->out_queue_sel |= TX_SELE_HQ; -+ rtlusb->out_ep_nums++; -+ } -+ if (ep_cfg & 0x0f0) { -+ rtlusb->out_queue_sel |= TX_SELE_NQ; -+ rtlusb->out_ep_nums++; -+ } -+ if (ep_cfg & 0xf00) { -+ rtlusb->out_queue_sel |= TX_SELE_LQ; -+ rtlusb->out_ep_nums++; -+ } -+ -+ switch (num_out_pipe) { -+ case 3: -+ rtlusb->out_queue_sel = TX_SELE_HQ | TX_SELE_NQ | TX_SELE_LQ; -+ rtlusb->out_ep_nums = 3; -+ break; -+ case 2: -+ rtlusb->out_queue_sel = TX_SELE_HQ | TX_SELE_NQ; -+ rtlusb->out_ep_nums = 2; -+ break; -+ case 1: -+ rtlusb->out_queue_sel = TX_SELE_HQ; -+ rtlusb->out_ep_nums = 1; -+ break; -+ default: -+ break; -+ } -+} -+ -+static void _rtl92du_one_out_ep_mapping(struct rtl_usb *rtlusb, -+ struct rtl_ep_map *ep_map) -+{ -+ ep_map->ep_mapping[RTL_TXQ_BE] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_BK] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_VI] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_VO] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_MGT] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_BCN] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_HI] = rtlusb->out_eps[0]; -+} -+ -+static void _rtl92du_two_out_ep_mapping(struct rtl_usb *rtlusb, -+ struct rtl_ep_map *ep_map) -+{ -+ ep_map->ep_mapping[RTL_TXQ_BE] = rtlusb->out_eps[1]; -+ ep_map->ep_mapping[RTL_TXQ_BK] = rtlusb->out_eps[1]; -+ ep_map->ep_mapping[RTL_TXQ_VI] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_VO] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_MGT] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_BCN] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_HI] = rtlusb->out_eps[0]; -+} -+ -+static void _rtl92du_three_out_ep_mapping(struct rtl_usb *rtlusb, -+ struct rtl_ep_map *ep_map) -+{ -+ ep_map->ep_mapping[RTL_TXQ_BE] = rtlusb->out_eps[2]; -+ ep_map->ep_mapping[RTL_TXQ_BK] = rtlusb->out_eps[2]; -+ ep_map->ep_mapping[RTL_TXQ_VI] = rtlusb->out_eps[1]; -+ ep_map->ep_mapping[RTL_TXQ_VO] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_MGT] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_BCN] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_HI] = rtlusb->out_eps[0]; -+} -+ -+static int _rtl92du_out_ep_mapping(struct ieee80211_hw *hw) -+{ -+ struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); -+ struct rtl_ep_map *ep_map = &rtlusb->ep_map; -+ -+ switch (rtlusb->out_ep_nums) { -+ case 1: -+ _rtl92du_one_out_ep_mapping(rtlusb, ep_map); -+ break; -+ case 2: -+ _rtl92du_two_out_ep_mapping(rtlusb, ep_map); -+ break; -+ case 3: -+ _rtl92du_three_out_ep_mapping(rtlusb, ep_map); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+int rtl92du_endpoint_mapping(struct ieee80211_hw *hw) -+{ -+ struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw)); -+ -+ _rtl92du_config_out_ep(hw, rtlusb->out_ep_nums); -+ -+ /* Normal chip with one IN and one OUT doesn't have interrupt IN EP. */ -+ if (rtlusb->out_ep_nums == 1 && rtlusb->in_ep_nums != 1) -+ return -EINVAL; -+ -+ return _rtl92du_out_ep_mapping(hw); -+} -+ -+u16 rtl92du_mq_to_hwq(__le16 fc, u16 mac80211_queue_index) -+{ -+ u16 hw_queue_index; -+ -+ if (unlikely(ieee80211_is_beacon(fc))) { -+ hw_queue_index = RTL_TXQ_BCN; -+ goto out; -+ } -+ if (ieee80211_is_mgmt(fc)) { -+ hw_queue_index = RTL_TXQ_MGT; -+ goto out; -+ } -+ -+ switch (mac80211_queue_index) { -+ case 0: -+ hw_queue_index = RTL_TXQ_VO; -+ break; -+ case 1: -+ hw_queue_index = RTL_TXQ_VI; -+ break; -+ case 2: -+ hw_queue_index = RTL_TXQ_BE; -+ break; -+ case 3: -+ hw_queue_index = RTL_TXQ_BK; -+ break; -+ default: -+ hw_queue_index = RTL_TXQ_BE; -+ WARN_ONCE(true, "rtl8192du: QSLT_BE queue, skb_queue:%d\n", -+ mac80211_queue_index); -+ break; -+ } -+out: -+ return hw_queue_index; -+} -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.h -new file mode 100644 -index 000000000000..8c3d24622fa7 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/trx.h -@@ -0,0 +1,60 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#ifndef __RTL92DU_TRX_H__ -+#define __RTL92DU_TRX_H__ -+ -+#define TX_SELE_HQ BIT(0) /* High Queue */ -+#define TX_SELE_LQ BIT(1) /* Low Queue */ -+#define TX_SELE_NQ BIT(2) /* Normal Queue */ -+ -+#define TX_TOTAL_PAGE_NUMBER_92DU 0xF8 -+#define TEST_PAGE_NUM_PUBQ_92DU 0x89 -+#define TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC 0x7A -+#define NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0x5A -+#define NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0x10 -+#define NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0x10 -+#define NORMAL_PAGE_NUM_NORMALQ_92D_DUAL_MAC 0 -+ -+#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5 -+ -+#define WMM_NORMAL_PAGE_NUM_PUBQ_92D 0x65 -+#define WMM_NORMAL_PAGE_NUM_HPQ_92D 0x30 -+#define WMM_NORMAL_PAGE_NUM_LPQ_92D 0x30 -+#define WMM_NORMAL_PAGE_NUM_NPQ_92D 0x30 -+ -+#define WMM_NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0x32 -+#define WMM_NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0x18 -+#define WMM_NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0x18 -+#define WMM_NORMAL_PAGE_NUM_NPQ_92D_DUAL_MAC 0x18 -+ -+static inline void set_tx_desc_bmc(__le32 *__txdesc, u32 __value) -+{ -+ le32p_replace_bits(__txdesc, __value, BIT(24)); -+} -+ -+static inline void set_tx_desc_agg_break(__le32 *__txdesc, u32 __value) -+{ -+ le32p_replace_bits((__txdesc + 1), __value, BIT(6)); -+} -+ -+static inline void set_tx_desc_tx_desc_checksum(__le32 *__txdesc, u32 __value) -+{ -+ le32p_replace_bits((__txdesc + 7), __value, GENMASK(15, 0)); -+} -+ -+void rtl92du_tx_fill_desc(struct ieee80211_hw *hw, -+ struct ieee80211_hdr *hdr, u8 *pdesc, -+ u8 *pbd_desc_tx, struct ieee80211_tx_info *info, -+ struct ieee80211_sta *sta, -+ struct sk_buff *skb, u8 hw_queue, -+ struct rtl_tcb_desc *ptcb_desc); -+int rtl92du_endpoint_mapping(struct ieee80211_hw *hw); -+u16 rtl92du_mq_to_hwq(__le16 fc, u16 mac80211_queue_index); -+struct sk_buff *rtl92du_tx_aggregate_hdl(struct ieee80211_hw *hw, -+ struct sk_buff_head *list); -+void rtl92du_tx_cleanup(struct ieee80211_hw *hw, struct sk_buff *skb); -+int rtl92du_tx_post_hdl(struct ieee80211_hw *hw, struct urb *urb, -+ struct sk_buff *skb); -+ -+#endif --- -2.34.1 - diff --git a/packages/linux/patches/rtlwifi/6.11/0007-6.11-wifi-rtlwifi-Add-rtl8192du-rf.-c-h.patch b/packages/linux/patches/rtlwifi/6.11/0007-6.11-wifi-rtlwifi-Add-rtl8192du-rf.-c-h.patch deleted file mode 100644 index 675e4b883b..0000000000 --- a/packages/linux/patches/rtlwifi/6.11/0007-6.11-wifi-rtlwifi-Add-rtl8192du-rf.-c-h.patch +++ /dev/null @@ -1,282 +0,0 @@ -From f42c4cb0031563e684a66ea2e21072387d9fcc7f Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 23 May 2024 17:46:51 +0300 -Subject: [PATCH 07/12] 6.11: wifi: rtlwifi: Add rtl8192du/rf.{c,h} - -These contain one RF configuration function and some functions related -to dual MAC operation. - -Signed-off-by: Bitterblue Smith ---- - .../wireless/realtek/rtlwifi/rtl8192du/rf.c | 240 ++++++++++++++++++ - .../wireless/realtek/rtlwifi/rtl8192du/rf.h | 11 + - 2 files changed, 251 insertions(+) - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/rf.c - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/rf.h - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/rf.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/rf.c -new file mode 100644 -index 000000000000..044dd65eafd0 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/rf.c -@@ -0,0 +1,240 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#include "../wifi.h" -+#include "../rtl8192d/reg.h" -+#include "../rtl8192d/phy_common.h" -+#include "phy.h" -+#include "rf.h" -+ -+bool rtl92du_phy_enable_anotherphy(struct ieee80211_hw *hw, bool bmac0) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; -+ u8 mac_on_bit = bmac0 ? MAC1_ON : MAC0_ON; -+ u8 mac_reg = bmac0 ? REG_MAC1 : REG_MAC0; -+ bool bresult = true; /* true: need to enable BB/RF power */ -+ u32 maskforphyset = 0; -+ u16 val16; -+ u8 u1btmp; -+ -+ rtlhal->during_mac0init_radiob = false; -+ rtlhal->during_mac1init_radioa = false; -+ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "===>\n"); -+ -+ /* MAC0 Need PHY1 load radio_b.txt . Driver use DBI to write. */ -+ u1btmp = rtl_read_byte(rtlpriv, mac_reg); -+ if (!(u1btmp & mac_on_bit)) { -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable BB & RF\n"); -+ /* Enable BB and RF power */ -+ -+ maskforphyset = bmac0 ? MAC0_ACCESS_PHY1 : MAC1_ACCESS_PHY0; -+ -+ val16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN | maskforphyset); -+ val16 &= 0xfffc; -+ rtl_write_word(rtlpriv, REG_SYS_FUNC_EN | maskforphyset, val16); -+ -+ val16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN | maskforphyset); -+ val16 |= BIT(13) | BIT(0) | BIT(1); -+ rtl_write_word(rtlpriv, REG_SYS_FUNC_EN | maskforphyset, val16); -+ } else { -+ /* We think if MAC1 is ON,then radio_a.txt -+ * and radio_b.txt has been load. -+ */ -+ bresult = false; -+ } -+ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<===\n"); -+ return bresult; -+} -+ -+void rtl92du_phy_powerdown_anotherphy(struct ieee80211_hw *hw, bool bmac0) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; -+ u8 mac_on_bit = bmac0 ? MAC1_ON : MAC0_ON; -+ u8 mac_reg = bmac0 ? REG_MAC1 : REG_MAC0; -+ u32 maskforphyset = 0; -+ u8 u1btmp; -+ -+ rtlhal->during_mac0init_radiob = false; -+ rtlhal->during_mac1init_radioa = false; -+ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "====>\n"); -+ -+ /* check MAC0 enable or not again now, if -+ * enabled, not power down radio A. -+ */ -+ u1btmp = rtl_read_byte(rtlpriv, mac_reg); -+ if (!(u1btmp & mac_on_bit)) { -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "power down\n"); -+ /* power down RF radio A according to YuNan's advice. */ -+ maskforphyset = bmac0 ? MAC0_ACCESS_PHY1 : MAC1_ACCESS_PHY0; -+ rtl_write_dword(rtlpriv, RFPGA0_XA_LSSIPARAMETER | maskforphyset, -+ 0x00000000); -+ } -+ rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "<====\n"); -+} -+ -+bool rtl92du_phy_rf6052_config(struct ieee80211_hw *hw) -+{ -+ bool mac1_initradioa_first = false, mac0_initradiob_first = false; -+ bool need_pwrdown_radioa = false, need_pwrdown_radiob = false; -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = &rtlpriv->rtlhal; -+ struct rtl_phy *rtlphy = &rtlpriv->phy; -+ struct bb_reg_def *pphyreg; -+ bool true_bpath = false; -+ bool rtstatus = true; -+ u32 u4_regvalue = 0; -+ u8 rfpath; -+ -+ if (rtlphy->rf_type == RF_1T1R) -+ rtlphy->num_total_rfpath = 1; -+ else -+ rtlphy->num_total_rfpath = 2; -+ -+ /* Single phy mode: use radio_a radio_b config path_A path_B -+ * separately by MAC0, and MAC1 needn't configure RF; -+ * Dual PHY mode: MAC0 use radio_a config 1st phy path_A, -+ * MAC1 use radio_b config 2nd PHY path_A. -+ * DMDP, MAC0 on G band, MAC1 on A band. -+ */ -+ if (rtlhal->macphymode == DUALMAC_DUALPHY) { -+ if (rtlhal->current_bandtype == BAND_ON_2_4G && -+ rtlhal->interfaceindex == 0) { -+ /* MAC0 needs PHY1 load radio_b.txt. */ -+ if (rtl92du_phy_enable_anotherphy(hw, true)) { -+ rtlphy->num_total_rfpath = 2; -+ mac0_initradiob_first = true; -+ } else { -+ /* We think if MAC1 is ON,then radio_a.txt and -+ * radio_b.txt has been load. -+ */ -+ return rtstatus; -+ } -+ } else if (rtlhal->current_bandtype == BAND_ON_5G && -+ rtlhal->interfaceindex == 1) { -+ /* MAC1 needs PHY0 load radio_a.txt. */ -+ if (rtl92du_phy_enable_anotherphy(hw, false)) { -+ rtlphy->num_total_rfpath = 2; -+ mac1_initradioa_first = true; -+ } else { -+ /* We think if MAC0 is ON, then radio_a.txt and -+ * radio_b.txt has been load. -+ */ -+ return rtstatus; -+ } -+ } else if (rtlhal->interfaceindex == 1) { -+ /* MAC0 enabled, only init radia B. */ -+ true_bpath = true; -+ } -+ } -+ -+ for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) { -+ /* Mac1 use PHY0 write */ -+ if (mac1_initradioa_first) { -+ if (rfpath == RF90_PATH_A) { -+ rtlhal->during_mac1init_radioa = true; -+ need_pwrdown_radioa = true; -+ } else if (rfpath == RF90_PATH_B) { -+ rtlhal->during_mac1init_radioa = false; -+ mac1_initradioa_first = false; -+ rfpath = RF90_PATH_A; -+ true_bpath = true; -+ rtlphy->num_total_rfpath = 1; -+ } -+ } else if (mac0_initradiob_first) { -+ /* Mac0 use PHY1 write */ -+ if (rfpath == RF90_PATH_A) -+ rtlhal->during_mac0init_radiob = false; -+ if (rfpath == RF90_PATH_B) { -+ rtlhal->during_mac0init_radiob = true; -+ mac0_initradiob_first = false; -+ need_pwrdown_radiob = true; -+ rfpath = RF90_PATH_A; -+ true_bpath = true; -+ rtlphy->num_total_rfpath = 1; -+ } -+ } -+ -+ pphyreg = &rtlphy->phyreg_def[rfpath]; -+ -+ switch (rfpath) { -+ case RF90_PATH_A: -+ case RF90_PATH_C: -+ u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs, -+ BRFSI_RFENV); -+ break; -+ case RF90_PATH_B: -+ case RF90_PATH_D: -+ u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs, -+ BRFSI_RFENV << 16); -+ break; -+ } -+ -+ rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); -+ udelay(1); -+ rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); -+ udelay(1); -+ -+ /* Set bit number of Address and Data for RF register */ -+ rtl_set_bbreg(hw, pphyreg->rfhssi_para2, -+ B3WIREADDRESSLENGTH, 0x0); -+ udelay(1); -+ rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); -+ udelay(1); -+ -+ switch (rfpath) { -+ case RF90_PATH_A: -+ if (true_bpath) -+ rtstatus = rtl92du_phy_config_rf_with_headerfile( -+ hw, radiob_txt, -+ (enum radio_path)rfpath); -+ else -+ rtstatus = rtl92du_phy_config_rf_with_headerfile( -+ hw, radioa_txt, -+ (enum radio_path)rfpath); -+ break; -+ case RF90_PATH_B: -+ rtstatus = -+ rtl92du_phy_config_rf_with_headerfile(hw, radiob_txt, -+ (enum radio_path)rfpath); -+ break; -+ case RF90_PATH_C: -+ break; -+ case RF90_PATH_D: -+ break; -+ } -+ -+ switch (rfpath) { -+ case RF90_PATH_A: -+ case RF90_PATH_C: -+ rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, -+ u4_regvalue); -+ break; -+ case RF90_PATH_B: -+ case RF90_PATH_D: -+ rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16, -+ u4_regvalue); -+ break; -+ } -+ -+ if (!rtstatus) { -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, -+ "Radio[%d] Fail!!\n", rfpath); -+ return rtstatus; -+ } -+ } -+ -+ /* check MAC0 enable or not again, if enabled, -+ * not power down radio A. -+ * check MAC1 enable or not again, if enabled, -+ * not power down radio B. -+ */ -+ if (need_pwrdown_radioa) -+ rtl92du_phy_powerdown_anotherphy(hw, false); -+ else if (need_pwrdown_radiob) -+ rtl92du_phy_powerdown_anotherphy(hw, true); -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "<---\n"); -+ -+ return rtstatus; -+} -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/rf.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/rf.h -new file mode 100644 -index 000000000000..4a92cbdd00c0 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/rf.h -@@ -0,0 +1,11 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#ifndef __RTL92DU_RF_H__ -+#define __RTL92DU_RF_H__ -+ -+bool rtl92du_phy_rf6052_config(struct ieee80211_hw *hw); -+bool rtl92du_phy_enable_anotherphy(struct ieee80211_hw *hw, bool bmac0); -+void rtl92du_phy_powerdown_anotherphy(struct ieee80211_hw *hw, bool bmac0); -+ -+#endif --- -2.34.1 - diff --git a/packages/linux/patches/rtlwifi/6.11/0008-6.11-wifi-rtlwifi-Add-rtl8192du-fw.-c-h-and-.patch b/packages/linux/patches/rtlwifi/6.11/0008-6.11-wifi-rtlwifi-Add-rtl8192du-fw.-c-h-and-.patch deleted file mode 100644 index 2e767d66b4..0000000000 --- a/packages/linux/patches/rtlwifi/6.11/0008-6.11-wifi-rtlwifi-Add-rtl8192du-fw.-c-h-and-.patch +++ /dev/null @@ -1,139 +0,0 @@ -From 07d8e12d4523008675013f91d46a8a8d133a41c2 Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 23 May 2024 17:47:19 +0300 -Subject: [PATCH 08/12] 6.11: wifi: rtlwifi: Add rtl8192du/fw.{c,h} - and rtl8192du/led.{c,h} - -fw.c contains a function for loading the firmware. -led.c contains a function for controlling the LED. - -Signed-off-by: Bitterblue Smith ---- - .../wireless/realtek/rtlwifi/rtl8192du/fw.c | 63 +++++++++++++++++++ - .../wireless/realtek/rtlwifi/rtl8192du/fw.h | 9 +++ - .../wireless/realtek/rtlwifi/rtl8192du/led.c | 10 +++ - .../wireless/realtek/rtlwifi/rtl8192du/led.h | 9 +++ - 4 files changed, 91 insertions(+) - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/fw.c - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/fw.h - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/led.c - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/led.h - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/fw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/fw.c -new file mode 100644 -index 000000000000..f74e4e84fe39 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/fw.c -@@ -0,0 +1,63 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#include "../wifi.h" -+#include "../rtl8192d/reg.h" -+#include "../rtl8192d/def.h" -+#include "../rtl8192d/fw_common.h" -+#include "fw.h" -+ -+int rtl92du_download_fw(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ enum version_8192d version = rtlhal->version; -+ u8 *pfwheader; -+ u8 *pfwdata; -+ u32 fwsize; -+ int err; -+ -+ if (rtlpriv->max_fw_size == 0 || !rtlhal->pfirmware) -+ return 1; -+ -+ fwsize = rtlhal->fwsize; -+ pfwheader = rtlhal->pfirmware; -+ pfwdata = rtlhal->pfirmware; -+ rtlhal->fw_version = (u16)GET_FIRMWARE_HDR_VERSION(pfwheader); -+ rtlhal->fw_subversion = (u16)GET_FIRMWARE_HDR_SUB_VER(pfwheader); -+ -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "FirmwareVersion(%d), FirmwareSubVersion(%d), Signature(%#x)\n", -+ rtlhal->fw_version, rtlhal->fw_subversion, -+ GET_FIRMWARE_HDR_SIGNATURE(pfwheader)); -+ -+ if (IS_FW_HEADER_EXIST(pfwheader)) { -+ rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, -+ "Shift 32 bytes for FW header!!\n"); -+ pfwdata = pfwdata + 32; -+ fwsize = fwsize - 32; -+ } -+ -+ if (rtl92d_is_fw_downloaded(rtlpriv)) -+ goto exit; -+ -+ /* If 8051 is running in RAM code, driver should -+ * inform Fw to reset by itself, or it will cause -+ * download Fw fail. -+ */ -+ if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) { -+ rtl92d_firmware_selfreset(hw); -+ rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); -+ } -+ -+ rtl92d_enable_fw_download(hw, true); -+ rtl92d_write_fw(hw, version, pfwdata, fwsize); -+ rtl92d_enable_fw_download(hw, false); -+ -+ err = rtl92d_fw_free_to_go(hw); -+ if (err) -+ pr_err("fw is not ready to run!\n"); -+exit: -+ err = rtl92d_fw_init(hw); -+ return err; -+} -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/fw.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/fw.h -new file mode 100644 -index 000000000000..7904bfbda4ba ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/fw.h -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#ifndef __RTL92DU_FW_H__ -+#define __RTL92DU_FW_H__ -+ -+int rtl92du_download_fw(struct ieee80211_hw *hw); -+ -+#endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/led.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/led.c -new file mode 100644 -index 000000000000..6c12dfbd6367 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/led.c -@@ -0,0 +1,10 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#include "../wifi.h" -+#include "led.h" -+ -+void rtl92du_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction) -+{ -+ /* The hardware has control. */ -+} -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/led.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/led.h -new file mode 100644 -index 000000000000..d7ebc8afcc7b ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/led.h -@@ -0,0 +1,9 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#ifndef __RTL92DU_LED_H__ -+#define __RTL92DU_LED_H__ -+ -+void rtl92du_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction); -+ -+#endif --- -2.34.1 - diff --git a/packages/linux/patches/rtlwifi/6.11/0009-6.11-wifi-rtlwifi-Add-rtl8192du-dm.-c-h.patch b/packages/linux/patches/rtlwifi/6.11/0009-6.11-wifi-rtlwifi-Add-rtl8192du-dm.-c-h.patch deleted file mode 100644 index e50395d93b..0000000000 --- a/packages/linux/patches/rtlwifi/6.11/0009-6.11-wifi-rtlwifi-Add-rtl8192du-dm.-c-h.patch +++ /dev/null @@ -1,161 +0,0 @@ -From e4592b803eb8ff3eda15c030906cc33226cc794e Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 23 May 2024 17:47:40 +0300 -Subject: [PATCH 09/12] 6.11: wifi: rtlwifi: Add rtl8192du/dm.{c,h} - -These contain functions related to the dynamic mechanism, which runs -every two seconds to adjust to changes in the environment. - -Signed-off-by: Bitterblue Smith ---- - .../wireless/realtek/rtlwifi/rtl8192du/dm.c | 120 ++++++++++++++++++ - .../wireless/realtek/rtlwifi/rtl8192du/dm.h | 10 ++ - 2 files changed, 130 insertions(+) - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/dm.c - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/dm.h - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/dm.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/dm.c -new file mode 100644 -index 000000000000..dd57707a9184 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/dm.c -@@ -0,0 +1,120 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#include "../wifi.h" -+#include "../core.h" -+#include "../rtl8192d/reg.h" -+#include "../rtl8192d/def.h" -+#include "../rtl8192d/dm_common.h" -+#include "../rtl8192d/fw_common.h" -+#include "dm.h" -+ -+static void rtl92du_dm_init_1r_cca(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct ps_t *dm_pstable = &rtlpriv->dm_pstable; -+ -+ dm_pstable->pre_ccastate = CCA_MAX; -+ dm_pstable->cur_ccasate = CCA_MAX; -+} -+ -+static void rtl92du_dm_1r_cca(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct ps_t *dm_pstable = &rtlpriv->dm_pstable; -+ struct rtl_hal *rtlhal = rtl_hal(rtlpriv); -+ int pwdb = rtlpriv->dm_digtable.min_undec_pwdb_for_dm; -+ -+ if (rtlhal->macphymode != SINGLEMAC_SINGLEPHY || -+ rtlhal->current_bandtype != BAND_ON_5G) -+ return; -+ -+ if (pwdb != 0) { -+ if (dm_pstable->pre_ccastate == CCA_2R || -+ dm_pstable->pre_ccastate == CCA_MAX) -+ dm_pstable->cur_ccasate = (pwdb >= 35) ? CCA_1R : CCA_2R; -+ else -+ dm_pstable->cur_ccasate = (pwdb <= 30) ? CCA_2R : CCA_1R; -+ } else { -+ dm_pstable->cur_ccasate = CCA_MAX; -+ } -+ -+ if (dm_pstable->pre_ccastate == dm_pstable->cur_ccasate) -+ return; -+ -+ rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_TRACE, -+ "Old CCA state: %d new CCA state: %d\n", -+ dm_pstable->pre_ccastate, dm_pstable->cur_ccasate); -+ -+ if (dm_pstable->cur_ccasate == CCA_1R) { -+ if (rtlpriv->phy.rf_type == RF_2T2R) -+ rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x13); -+ else /* Is this branch reachable? */ -+ rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23); -+ } else { /* CCA_2R or CCA_MAX */ -+ rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); -+ } -+} -+ -+static void rtl92du_dm_pwdb_monitor(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ const u32 max_macid = 32; -+ u32 temp; -+ -+ /* AP & ADHOC & MESH will return tmp */ -+ if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION) -+ return; -+ -+ /* Indicate Rx signal strength to FW. */ -+ if (rtlpriv->dm.useramask) { -+ temp = rtlpriv->dm.undec_sm_pwdb << 16; -+ temp |= max_macid << 8; -+ -+ rtl92d_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, (u8 *)(&temp)); -+ } else { -+ rtl_write_byte(rtlpriv, 0x4fe, (u8)rtlpriv->dm.undec_sm_pwdb); -+ } -+} -+ -+void rtl92du_dm_init(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER; -+ rtl_dm_diginit(hw, 0x20); -+ rtlpriv->dm_digtable.rx_gain_max = DM_DIG_FA_UPPER; -+ rtlpriv->dm_digtable.rx_gain_min = DM_DIG_FA_LOWER; -+ rtl92d_dm_init_edca_turbo(hw); -+ rtl92du_dm_init_1r_cca(hw); -+ rtl92d_dm_init_rate_adaptive_mask(hw); -+ rtl92d_dm_initialize_txpower_tracking(hw); -+} -+ -+void rtl92du_dm_watchdog(struct ieee80211_hw *hw) -+{ -+ struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); -+ bool fw_current_inpsmode = false; -+ bool fwps_awake = true; -+ -+ /* 1. RF is OFF. (No need to do DM.) -+ * 2. Fw is under power saving mode for FwLPS. -+ * (Prevent from SW/FW I/O racing.) -+ * 3. IPS workitem is scheduled. (Prevent from IPS sequence -+ * to be swapped with DM. -+ * 4. RFChangeInProgress is TRUE. -+ * (Prevent from broken by IPS/HW/SW Rf off.) -+ */ -+ -+ if (ppsc->rfpwr_state != ERFON || fw_current_inpsmode || -+ !fwps_awake || ppsc->rfchange_inprogress) -+ return; -+ -+ rtl92du_dm_pwdb_monitor(hw); -+ rtl92d_dm_false_alarm_counter_statistics(hw); -+ rtl92d_dm_find_minimum_rssi(hw); -+ rtl92d_dm_dig(hw); -+ rtl92d_dm_check_txpower_tracking_thermal_meter(hw); -+ rtl92d_dm_check_edca_turbo(hw); -+ rtl92du_dm_1r_cca(hw); -+} -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/dm.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/dm.h -new file mode 100644 -index 000000000000..2f283bf1e4d8 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/dm.h -@@ -0,0 +1,10 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#ifndef __RTL92DU_DM_H__ -+#define __RTL92DU_DM_H__ -+ -+void rtl92du_dm_init(struct ieee80211_hw *hw); -+void rtl92du_dm_watchdog(struct ieee80211_hw *hw); -+ -+#endif --- -2.34.1 - diff --git a/packages/linux/patches/rtlwifi/6.11/0010-6.11-wifi-rtlwifi-Constify-rtl_hal_cfg.-ops-.patch b/packages/linux/patches/rtlwifi/6.11/0010-6.11-wifi-rtlwifi-Constify-rtl_hal_cfg.-ops-.patch deleted file mode 100644 index 714abd1376..0000000000 --- a/packages/linux/patches/rtlwifi/6.11/0010-6.11-wifi-rtlwifi-Constify-rtl_hal_cfg.-ops-.patch +++ /dev/null @@ -1,106 +0,0 @@ -From c791ad6e48ba58f4473b899ba7bf2de1d1536d17 Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 23 May 2024 17:48:02 +0300 -Subject: [PATCH 10/12] 6.11: wifi: rtlwifi: Constify - rtl_hal_cfg.{ops,usb_interface_cfg} and rtl_priv.cfg - -This allows the drivers to declare the structs rtl_hal_cfg, rtl_hal_ops, -and rtl_hal_usbint_cfg as const. - -Signed-off-by: Bitterblue Smith ---- - drivers/net/wireless/realtek/rtlwifi/base.c | 2 +- - drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c | 3 +-- - drivers/net/wireless/realtek/rtlwifi/usb.c | 2 +- - drivers/net/wireless/realtek/rtlwifi/usb.h | 2 +- - drivers/net/wireless/realtek/rtlwifi/wifi.h | 6 +++--- - 5 files changed, 7 insertions(+), 8 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtlwifi/base.c b/drivers/net/wireless/realtek/rtlwifi/base.c -index 1a8d715b7c07..aab4605de9c4 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/base.c -+++ b/drivers/net/wireless/realtek/rtlwifi/base.c -@@ -2272,7 +2272,7 @@ static void rtl_c2h_content_parsing(struct ieee80211_hw *hw, - struct sk_buff *skb) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -- struct rtl_hal_ops *hal_ops = rtlpriv->cfg->ops; -+ const struct rtl_hal_ops *hal_ops = rtlpriv->cfg->ops; - const struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops; - u8 cmd_id, cmd_len; - u8 *cmd_buf = NULL; -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c -index 48be7e346efc..c9b9e2bc90cc 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c -@@ -53,8 +53,6 @@ static int rtl92cu_init_sw_vars(struct ieee80211_hw *hw) - } else { - fw_name = "rtlwifi/rtl8192cufw_TMSC.bin"; - } -- /* provide name of alternative file */ -- rtlpriv->cfg->alt_fw_name = "rtlwifi/rtl8192cufw.bin"; - pr_info("Loading firmware %s\n", fw_name); - rtlpriv->max_fw_size = 0x4000; - err = request_firmware_nowait(THIS_MODULE, 1, -@@ -160,6 +158,7 @@ static struct rtl_hal_usbint_cfg rtl92cu_interface_cfg = { - - static struct rtl_hal_cfg rtl92cu_hal_cfg = { - .name = "rtl92c_usb", -+ .alt_fw_name = "rtlwifi/rtl8192cufw.bin", - .ops = &rtl8192cu_hal_ops, - .mod_params = &rtl92cu_mod_params, - .usb_interface_cfg = &rtl92cu_interface_cfg, -diff --git a/drivers/net/wireless/realtek/rtlwifi/usb.c b/drivers/net/wireless/realtek/rtlwifi/usb.c -index 2ea72d9e3957..b6d300bec1e9 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/usb.c -+++ b/drivers/net/wireless/realtek/rtlwifi/usb.c -@@ -937,7 +937,7 @@ static const struct rtl_intf_ops rtl_usb_ops = { - - int rtl_usb_probe(struct usb_interface *intf, - const struct usb_device_id *id, -- struct rtl_hal_cfg *rtl_hal_cfg) -+ const struct rtl_hal_cfg *rtl_hal_cfg) - { - int err; - struct ieee80211_hw *hw = NULL; -diff --git a/drivers/net/wireless/realtek/rtlwifi/usb.h b/drivers/net/wireless/realtek/rtlwifi/usb.h -index 12529afc0510..b66d6f9ae564 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/usb.h -+++ b/drivers/net/wireless/realtek/rtlwifi/usb.h -@@ -136,7 +136,7 @@ struct rtl_usb_priv { - - int rtl_usb_probe(struct usb_interface *intf, - const struct usb_device_id *id, -- struct rtl_hal_cfg *rtl92cu_hal_cfg); -+ const struct rtl_hal_cfg *rtl92cu_hal_cfg); - void rtl_usb_disconnect(struct usb_interface *intf); - int rtl_usb_suspend(struct usb_interface *pusb_intf, pm_message_t message); - int rtl_usb_resume(struct usb_interface *pusb_intf); -diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h -index 2e88359ba917..940df771a764 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/wifi.h -+++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h -@@ -2383,9 +2383,9 @@ struct rtl_hal_cfg { - bool write_readback; - char *name; - char *alt_fw_name; -- struct rtl_hal_ops *ops; -+ const struct rtl_hal_ops *ops; - struct rtl_mod_params *mod_params; -- struct rtl_hal_usbint_cfg *usb_interface_cfg; -+ const struct rtl_hal_usbint_cfg *usb_interface_cfg; - enum rtl_spec_ver spec_ver; - - /*this map used for some registers or vars -@@ -2734,7 +2734,7 @@ struct rtl_priv { - /* hal_cfg : for diff cards - * intf_ops : for diff interrface usb/pcie - */ -- struct rtl_hal_cfg *cfg; -+ const struct rtl_hal_cfg *cfg; - const struct rtl_intf_ops *intf_ops; - - /* this var will be set by set_bit, --- -2.34.1 - diff --git a/packages/linux/patches/rtlwifi/6.11/0011-6.11-wifi-rtlwifi-Add-rtl8192du-sw.c.patch b/packages/linux/patches/rtlwifi/6.11/0011-6.11-wifi-rtlwifi-Add-rtl8192du-sw.c.patch deleted file mode 100644 index 1b009ca93a..0000000000 --- a/packages/linux/patches/rtlwifi/6.11/0011-6.11-wifi-rtlwifi-Add-rtl8192du-sw.c.patch +++ /dev/null @@ -1,417 +0,0 @@ -From 11fc9ecc1d73fd506a3bd359bf3f8b9a94ca59df Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 23 May 2024 17:48:32 +0300 -Subject: [PATCH 11/12] 6.11: wifi: rtlwifi: Add rtl8192du/sw.c - -This contains the new module's entry point. - -Signed-off-by: Bitterblue Smith ---- - .../wireless/realtek/rtlwifi/rtl8192du/sw.c | 395 ++++++++++++++++++ - 1 file changed, 395 insertions(+) - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/sw.c - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/sw.c -new file mode 100644 -index 000000000000..d069a81ac617 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/sw.c -@@ -0,0 +1,395 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* Copyright(c) 2024 Realtek Corporation.*/ -+ -+#include "../wifi.h" -+#include "../core.h" -+#include "../usb.h" -+#include "../base.h" -+#include "../rtl8192d/reg.h" -+#include "../rtl8192d/def.h" -+#include "../rtl8192d/fw_common.h" -+#include "../rtl8192d/hw_common.h" -+#include "../rtl8192d/phy_common.h" -+#include "../rtl8192d/trx_common.h" -+#include "phy.h" -+#include "dm.h" -+#include "hw.h" -+#include "trx.h" -+#include "led.h" -+ -+#include -+ -+static struct usb_interface *rtl92du_get_other_intf(struct ieee80211_hw *hw) -+{ -+ struct usb_interface *intf; -+ struct usb_device *udev; -+ u8 other_interfaceindex; -+ -+ /* See SET_IEEE80211_DEV(hw, &intf->dev); in usb.c */ -+ intf = container_of_const(wiphy_dev(hw->wiphy), struct usb_interface, dev); -+ -+ if (intf->altsetting[0].desc.bInterfaceNumber == 0) -+ other_interfaceindex = 1; -+ else -+ other_interfaceindex = 0; -+ -+ udev = interface_to_usbdev(intf); -+ -+ return usb_ifnum_to_if(udev, other_interfaceindex); -+} -+ -+static int rtl92du_init_shared_data(struct ieee80211_hw *hw) -+{ -+ struct usb_interface *other_intf = rtl92du_get_other_intf(hw); -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_priv *other_rtlpriv = NULL; -+ struct ieee80211_hw *other_hw = NULL; -+ -+ if (other_intf) -+ other_hw = usb_get_intfdata(other_intf); -+ -+ if (other_hw) { -+ /* The other interface was already probed. */ -+ other_rtlpriv = rtl_priv(other_hw); -+ rtlpriv->curveindex_2g = other_rtlpriv->curveindex_2g; -+ rtlpriv->curveindex_5g = other_rtlpriv->curveindex_5g; -+ rtlpriv->mutex_for_power_on_off = other_rtlpriv->mutex_for_power_on_off; -+ rtlpriv->mutex_for_hw_init = other_rtlpriv->mutex_for_hw_init; -+ -+ if (!rtlpriv->curveindex_2g || !rtlpriv->curveindex_5g || -+ !rtlpriv->mutex_for_power_on_off || !rtlpriv->mutex_for_hw_init) -+ return -ENOMEM; -+ -+ return 0; -+ } -+ -+ /* The other interface doesn't exist or was not probed yet. */ -+ rtlpriv->curveindex_2g = kcalloc(TARGET_CHNL_NUM_2G, -+ sizeof(*rtlpriv->curveindex_2g), -+ GFP_KERNEL); -+ rtlpriv->curveindex_5g = kcalloc(TARGET_CHNL_NUM_5G, -+ sizeof(*rtlpriv->curveindex_5g), -+ GFP_KERNEL); -+ rtlpriv->mutex_for_power_on_off = -+ kzalloc(sizeof(*rtlpriv->mutex_for_power_on_off), GFP_KERNEL); -+ rtlpriv->mutex_for_hw_init = -+ kzalloc(sizeof(*rtlpriv->mutex_for_hw_init), GFP_KERNEL); -+ -+ if (!rtlpriv->curveindex_2g || !rtlpriv->curveindex_5g || -+ !rtlpriv->mutex_for_power_on_off || !rtlpriv->mutex_for_hw_init) { -+ kfree(rtlpriv->curveindex_2g); -+ kfree(rtlpriv->curveindex_5g); -+ kfree(rtlpriv->mutex_for_power_on_off); -+ kfree(rtlpriv->mutex_for_hw_init); -+ rtlpriv->curveindex_2g = NULL; -+ rtlpriv->curveindex_5g = NULL; -+ rtlpriv->mutex_for_power_on_off = NULL; -+ rtlpriv->mutex_for_hw_init = NULL; -+ return -ENOMEM; -+ } -+ -+ mutex_init(rtlpriv->mutex_for_power_on_off); -+ mutex_init(rtlpriv->mutex_for_hw_init); -+ -+ return 0; -+} -+ -+static void rtl92du_deinit_shared_data(struct ieee80211_hw *hw) -+{ -+ struct usb_interface *other_intf = rtl92du_get_other_intf(hw); -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ if (!other_intf || !usb_get_intfdata(other_intf)) { -+ /* The other interface doesn't exist or was already disconnected. */ -+ kfree(rtlpriv->curveindex_2g); -+ kfree(rtlpriv->curveindex_5g); -+ if (rtlpriv->mutex_for_power_on_off) -+ mutex_destroy(rtlpriv->mutex_for_power_on_off); -+ if (rtlpriv->mutex_for_hw_init) -+ mutex_destroy(rtlpriv->mutex_for_hw_init); -+ kfree(rtlpriv->mutex_for_power_on_off); -+ kfree(rtlpriv->mutex_for_hw_init); -+ } -+} -+ -+static int rtl92du_init_sw_vars(struct ieee80211_hw *hw) -+{ -+ const char *fw_name = "rtlwifi/rtl8192dufw.bin"; -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ int err; -+ -+ err = rtl92du_init_shared_data(hw); -+ if (err) -+ return err; -+ -+ rtlpriv->dm.dm_initialgain_enable = true; -+ rtlpriv->dm.dm_flag = 0; -+ rtlpriv->dm.disable_framebursting = false; -+ rtlpriv->dm.thermalvalue = 0; -+ rtlpriv->dm.useramask = true; -+ -+ /* dual mac */ -+ if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G) -+ rtlpriv->phy.current_channel = 36; -+ else -+ rtlpriv->phy.current_channel = 1; -+ -+ if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) -+ rtlpriv->rtlhal.disable_amsdu_8k = true; -+ -+ /* for LPS & IPS */ -+ rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps; -+ rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps; -+ rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps; -+ -+ /* for early mode */ -+ rtlpriv->rtlhal.earlymode_enable = false; -+ -+ /* for firmware buf */ -+ rtlpriv->rtlhal.pfirmware = kmalloc(0x8000, GFP_KERNEL); -+ if (!rtlpriv->rtlhal.pfirmware) -+ return -ENOMEM; -+ -+ rtlpriv->max_fw_size = 0x8000; -+ pr_info("Driver for Realtek RTL8192DU WLAN interface\n"); -+ pr_info("Loading firmware file %s\n", fw_name); -+ -+ /* request fw */ -+ err = request_firmware_nowait(THIS_MODULE, 1, fw_name, -+ rtlpriv->io.dev, GFP_KERNEL, hw, -+ rtl_fw_cb); -+ if (err) { -+ pr_err("Failed to request firmware!\n"); -+ kfree(rtlpriv->rtlhal.pfirmware); -+ rtlpriv->rtlhal.pfirmware = NULL; -+ return err; -+ } -+ -+ return 0; -+} -+ -+static void rtl92du_deinit_sw_vars(struct ieee80211_hw *hw) -+{ -+ struct rtl_priv *rtlpriv = rtl_priv(hw); -+ -+ kfree(rtlpriv->rtlhal.pfirmware); -+ rtlpriv->rtlhal.pfirmware = NULL; -+ -+ rtl92du_deinit_shared_data(hw); -+} -+ -+static const struct rtl_hal_ops rtl8192du_hal_ops = { -+ .init_sw_vars = rtl92du_init_sw_vars, -+ .deinit_sw_vars = rtl92du_deinit_sw_vars, -+ .read_chip_version = rtl92du_read_chip_version, -+ .read_eeprom_info = rtl92d_read_eeprom_info, -+ .hw_init = rtl92du_hw_init, -+ .hw_disable = rtl92du_card_disable, -+ .enable_interrupt = rtl92du_enable_interrupt, -+ .disable_interrupt = rtl92du_disable_interrupt, -+ .set_network_type = rtl92du_set_network_type, -+ .set_chk_bssid = rtl92du_set_check_bssid, -+ .set_qos = rtl92d_set_qos, -+ .set_bcn_reg = rtl92du_set_beacon_related_registers, -+ .set_bcn_intv = rtl92du_set_beacon_interval, -+ .update_interrupt_mask = rtl92du_update_interrupt_mask, -+ .get_hw_reg = rtl92du_get_hw_reg, -+ .set_hw_reg = rtl92du_set_hw_reg, -+ .update_rate_tbl = rtl92d_update_hal_rate_tbl, -+ .fill_tx_desc = rtl92du_tx_fill_desc, -+ .query_rx_desc = rtl92d_rx_query_desc, -+ .set_channel_access = rtl92d_update_channel_access_setting, -+ .radio_onoff_checking = rtl92d_gpio_radio_on_off_checking, -+ .set_bw_mode = rtl92du_phy_set_bw_mode, -+ .switch_channel = rtl92du_phy_sw_chnl, -+ .dm_watchdog = rtl92du_dm_watchdog, -+ .scan_operation_backup = rtl_phy_scan_operation_backup, -+ .set_rf_power_state = rtl92du_phy_set_rf_power_state, -+ .led_control = rtl92du_led_control, -+ .set_desc = rtl92d_set_desc, -+ .get_desc = rtl92d_get_desc, -+ .enable_hw_sec = rtl92d_enable_hw_security_config, -+ .set_key = rtl92d_set_key, -+ .get_bbreg = rtl92du_phy_query_bb_reg, -+ .set_bbreg = rtl92du_phy_set_bb_reg, -+ .get_rfreg = rtl92d_phy_query_rf_reg, -+ .set_rfreg = rtl92d_phy_set_rf_reg, -+ .linked_set_reg = rtl92du_linked_set_reg, -+ .fill_h2c_cmd = rtl92d_fill_h2c_cmd, -+ .get_btc_status = rtl_btc_status_false, -+ .phy_iq_calibrate = rtl92du_phy_iq_calibrate, -+ .phy_lc_calibrate = rtl92du_phy_lc_calibrate, -+}; -+ -+static struct rtl_mod_params rtl92du_mod_params = { -+ .sw_crypto = false, -+ .inactiveps = false, -+ .swctrl_lps = false, -+ .debug_level = 0, -+ .debug_mask = 0, -+}; -+ -+static const struct rtl_hal_usbint_cfg rtl92du_interface_cfg = { -+ /* rx */ -+ .rx_urb_num = 8, -+ .rx_max_size = 15360, -+ .usb_rx_hdl = NULL, -+ .usb_rx_segregate_hdl = NULL, -+ /* tx */ -+ .usb_tx_cleanup = rtl92du_tx_cleanup, -+ .usb_tx_post_hdl = rtl92du_tx_post_hdl, -+ .usb_tx_aggregate_hdl = rtl92du_tx_aggregate_hdl, -+ .usb_endpoint_mapping = rtl92du_endpoint_mapping, -+ .usb_mq_to_hwq = rtl92du_mq_to_hwq, -+}; -+ -+static const struct rtl_hal_cfg rtl92du_hal_cfg = { -+ .name = "rtl8192du", -+ .ops = &rtl8192du_hal_ops, -+ .mod_params = &rtl92du_mod_params, -+ .usb_interface_cfg = &rtl92du_interface_cfg, -+ -+ .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL, -+ .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN, -+ .maps[SYS_CLK] = REG_SYS_CLKR, -+ .maps[MAC_RCR_AM] = RCR_AM, -+ .maps[MAC_RCR_AB] = RCR_AB, -+ .maps[MAC_RCR_ACRC32] = RCR_ACRC32, -+ .maps[MAC_RCR_ACF] = RCR_ACF, -+ .maps[MAC_RCR_AAP] = RCR_AAP, -+ -+ .maps[EFUSE_TEST] = REG_EFUSE_TEST, -+ .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS, -+ .maps[EFUSE_CTRL] = REG_EFUSE_CTRL, -+ .maps[EFUSE_CLK] = 0, /* just for 92se */ -+ .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL, -+ .maps[EFUSE_PWC_EV12V] = PWC_EV12V, -+ .maps[EFUSE_FEN_ELDR] = FEN_ELDR, -+ .maps[EFUSE_LOADER_CLK_EN] = 0, -+ .maps[EFUSE_ANA8M] = 0, /* just for 92se */ -+ .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE, -+ .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION, -+ .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN, -+ -+ .maps[RWCAM] = REG_CAMCMD, -+ .maps[WCAMI] = REG_CAMWRITE, -+ .maps[RCAMO] = REG_CAMREAD, -+ .maps[CAMDBG] = REG_CAMDBG, -+ .maps[SECR] = REG_SECCFG, -+ .maps[SEC_CAM_NONE] = CAM_NONE, -+ .maps[SEC_CAM_WEP40] = CAM_WEP40, -+ .maps[SEC_CAM_TKIP] = CAM_TKIP, -+ .maps[SEC_CAM_AES] = CAM_AES, -+ .maps[SEC_CAM_WEP104] = CAM_WEP104, -+ -+ .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6, -+ .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5, -+ .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4, -+ .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3, -+ .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2, -+ .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1, -+ .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8, -+ .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7, -+ .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6, -+ .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5, -+ .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4, -+ .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3, -+ .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2, -+ .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1, -+ .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2, -+ .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1, -+ -+ .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW, -+ .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT, -+ .maps[RTL_IMR_BCNINT] = IMR_BCNINT, -+ .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW, -+ .maps[RTL_IMR_RDU] = IMR_RDU, -+ .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND, -+ .maps[RTL_IMR_BDOK] = IMR_BDOK, -+ .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK, -+ .maps[RTL_IMR_TBDER] = IMR_TBDER, -+ .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK, -+ .maps[RTL_IMR_TBDOK] = IMR_TBDOK, -+ .maps[RTL_IMR_BKDOK] = IMR_BKDOK, -+ .maps[RTL_IMR_BEDOK] = IMR_BEDOK, -+ .maps[RTL_IMR_VIDOK] = IMR_VIDOK, -+ .maps[RTL_IMR_VODOK] = IMR_VODOK, -+ .maps[RTL_IMR_ROK] = IMR_ROK, -+ .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER), -+ -+ .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M, -+ .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M, -+ .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M, -+ .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M, -+ .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M, -+ .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M, -+ .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M, -+ .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M, -+ .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M, -+ .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M, -+ .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M, -+ .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M, -+ -+ .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7, -+ .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15, -+}; -+ -+module_param_named(swenc, rtl92du_mod_params.sw_crypto, bool, 0444); -+module_param_named(debug_level, rtl92du_mod_params.debug_level, int, 0644); -+module_param_named(ips, rtl92du_mod_params.inactiveps, bool, 0444); -+module_param_named(swlps, rtl92du_mod_params.swctrl_lps, bool, 0444); -+module_param_named(debug_mask, rtl92du_mod_params.debug_mask, ullong, 0644); -+MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n"); -+MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 0)\n"); -+MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n"); -+MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)"); -+MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)"); -+ -+#define USB_VENDOR_ID_REALTEK 0x0bda -+ -+static const struct usb_device_id rtl8192d_usb_ids[] = { -+ {RTL_USB_DEVICE(USB_VENDOR_ID_REALTEK, 0x8193, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(USB_VENDOR_ID_REALTEK, 0x8194, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(USB_VENDOR_ID_REALTEK, 0x8111, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(USB_VENDOR_ID_REALTEK, 0x0193, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(USB_VENDOR_ID_REALTEK, 0x8171, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(USB_VENDOR_ID_REALTEK, 0xe194, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(0x2019, 0xab2c, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(0x2019, 0xab2d, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(0x2019, 0x4903, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(0x2019, 0x4904, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(0x07b8, 0x8193, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(0x20f4, 0x664b, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(0x04dd, 0x954f, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(0x04dd, 0x96a6, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(0x050d, 0x110a, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(0x050d, 0x1105, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(0x050d, 0x120a, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(0x1668, 0x8102, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(0x0930, 0x0a0a, rtl92du_hal_cfg)}, -+ {RTL_USB_DEVICE(0x2001, 0x330c, rtl92du_hal_cfg)}, -+ {} -+}; -+ -+MODULE_DEVICE_TABLE(usb, rtl8192d_usb_ids); -+ -+static int rtl8192du_probe(struct usb_interface *intf, -+ const struct usb_device_id *id) -+{ -+ return rtl_usb_probe(intf, id, &rtl92du_hal_cfg); -+} -+ -+static struct usb_driver rtl8192du_driver = { -+ .name = "rtl8192du", -+ .probe = rtl8192du_probe, -+ .disconnect = rtl_usb_disconnect, -+ .id_table = rtl8192d_usb_ids, -+ .disable_hub_initiated_lpm = 1, -+}; -+ -+module_usb_driver(rtl8192du_driver); -+ -+MODULE_AUTHOR("Bitterblue Smith "); -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("Realtek 8192DU 802.11n Dual Mac USB wireless"); -+MODULE_FIRMWARE("rtlwifi/rtl8192dufw.bin"); --- -2.34.1 - diff --git a/packages/linux/patches/rtlwifi/6.11/0012-6.11-wifi-rtlwifi-Enable-the-new-rtl8192du-d.patch b/packages/linux/patches/rtlwifi/6.11/0012-6.11-wifi-rtlwifi-Enable-the-new-rtl8192du-d.patch deleted file mode 100644 index 5af2cc7c72..0000000000 --- a/packages/linux/patches/rtlwifi/6.11/0012-6.11-wifi-rtlwifi-Enable-the-new-rtl8192du-d.patch +++ /dev/null @@ -1,92 +0,0 @@ -From da2287b41888e02866f1416caa36c148c5723f8b Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 23 May 2024 17:49:00 +0300 -Subject: [PATCH 12/12] 6.11: wifi: rtlwifi: Enable the new rtl8192du - driver - -The RTL8192DU is an older Wifi 4 dual band chip. It comes in two -flavours: single MAC single PHY (like most Realtek Wifi 4 USB devices), -and dual MAC dual PHY. - -The single MAC single PHY version is 2T2R and can work either in the -2.4 GHz band or the 5 GHz band. - -The dual MAC dual PHY version has two USB interfaces and appears to the -system as two separate 1T1R Wifi devices, one working in the 2.4 GHz -band, the other in the 5 GHz band. - -This was tested only with a single MAC single PHY device, mostly in -station mode. The speeds in the 2.4 GHz band with 20 MHz channel width -are similar to the out-of-tree driver: 85/51 megabits/second. - -Stefan Lippers-Hollmann tested the speed in the 5 GHz band with 40 MHz -channel width: 173/99 megabits/second. - -It was also tested briefly in AP mode. It's emitting beacons and my -phone can connect to it. - -Signed-off-by: Bitterblue Smith ---- - drivers/net/wireless/realtek/rtlwifi/Kconfig | 12 ++++++++++++ - drivers/net/wireless/realtek/rtlwifi/Makefile | 1 + - .../net/wireless/realtek/rtlwifi/rtl8192du/Makefile | 13 +++++++++++++ - 3 files changed, 26 insertions(+) - create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/Makefile - -diff --git a/drivers/net/wireless/realtek/rtlwifi/Kconfig b/drivers/net/wireless/realtek/rtlwifi/Kconfig -index cfe63f7b28d9..1e66c1bf7c8b 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/Kconfig -+++ b/drivers/net/wireless/realtek/rtlwifi/Kconfig -@@ -119,6 +119,18 @@ config RTL8192CU - - If you choose to build it as a module, it will be called rtl8192cu - -+config RTL8192DU -+ tristate "Realtek RTL8192DU USB Wireless Network Adapter" -+ depends on USB -+ select RTLWIFI -+ select RTLWIFI_USB -+ select RTL8192D_COMMON -+ help -+ This is the driver for Realtek RTL8192DU 802.11n USB -+ wireless network adapters. -+ -+ If you choose to build it as a module, it will be called rtl8192du -+ - config RTLWIFI - tristate - select FW_LOADER -diff --git a/drivers/net/wireless/realtek/rtlwifi/Makefile b/drivers/net/wireless/realtek/rtlwifi/Makefile -index 423981b148df..9cf32277c7f1 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/Makefile -+++ b/drivers/net/wireless/realtek/rtlwifi/Makefile -@@ -25,6 +25,7 @@ obj-$(CONFIG_RTL8192CU) += rtl8192cu/ - obj-$(CONFIG_RTL8192SE) += rtl8192se/ - obj-$(CONFIG_RTL8192D_COMMON) += rtl8192d/ - obj-$(CONFIG_RTL8192DE) += rtl8192de/ -+obj-$(CONFIG_RTL8192DU) += rtl8192du/ - obj-$(CONFIG_RTL8723AE) += rtl8723ae/ - obj-$(CONFIG_RTL8723BE) += rtl8723be/ - obj-$(CONFIG_RTL8188EE) += rtl8188ee/ -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/Makefile b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/Makefile -new file mode 100644 -index 000000000000..569bfd3d5030 ---- /dev/null -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/Makefile -@@ -0,0 +1,13 @@ -+# SPDX-License-Identifier: GPL-2.0 -+rtl8192du-objs := \ -+ dm.o \ -+ fw.o \ -+ hw.o \ -+ led.o \ -+ phy.o \ -+ rf.o \ -+ sw.o \ -+ table.o \ -+ trx.o -+ -+obj-$(CONFIG_RTL8192DU) += rtl8192du.o --- -2.34.1 - diff --git a/packages/linux/patches/rtlwifi/6.11/0013-6.11-wifi-rtw88-usb-Further-limit-the-TX-aggregation.patch b/packages/linux/patches/rtlwifi/6.11/0013-6.11-wifi-rtw88-usb-Further-limit-the-TX-aggregation.patch deleted file mode 100644 index ed8c0296ce..0000000000 --- a/packages/linux/patches/rtlwifi/6.11/0013-6.11-wifi-rtw88-usb-Further-limit-the-TX-aggregation.patch +++ /dev/null @@ -1,164 +0,0 @@ -From d7dd13ea54af8496aca2762a758d817d6813e81c Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Sun, 16 Jun 2024 22:27:34 +0300 -Subject: [PATCH] wifi: rtw88: usb: Further limit the TX aggregation - -Currently the number of frames sent to the chip in a single USB Request -Block is limited only by the size of the TX buffer, which is 20 KiB. -Testing reveals that as many as 13 frames get aggregated. This is more -than what any of the chips would like to receive. RTL8822CU, RTL8822BU, -and RTL8821CU want at most 3 frames, and RTL8723DU wants only 1 frame -per URB. - -RTL8723DU in particular reliably malfunctions during a speed test if it -receives more than 1 frame per URB. All traffic seems to stop. Pinging -the AP no longer works. - -Fix this problem by limiting the number of frames sent to the chip in a -single URB according to what each chip likes. - -Also configure RTL8822CU, RTL8822BU, and RTL8821CU to expect 3 frames -per URB. - -RTL8703B may or may not be found in USB devices. Declare that it wants -only 1 frame per URB, just in case. - -Tested with RTL8723DU and RTL8811CU. - -Cc: stable@vger.kernel.org -Signed-off-by: Bitterblue Smith -Acked-by: Ping-Ke Shih -Signed-off-by: Ping-Ke Shih -Link: https://patch.msgid.link/cb46ea35-7e59-4742-9c1f-01ceeaad36fb@gmail.com ---- - drivers/net/wireless/realtek/rtw88/mac.c | 9 +++++++++ - drivers/net/wireless/realtek/rtw88/main.h | 2 ++ - drivers/net/wireless/realtek/rtw88/reg.h | 1 + - drivers/net/wireless/realtek/rtw88/rtw8703b.c | 1 + - drivers/net/wireless/realtek/rtw88/rtw8723d.c | 1 + - drivers/net/wireless/realtek/rtw88/rtw8821c.c | 1 + - drivers/net/wireless/realtek/rtw88/rtw8822b.c | 1 + - drivers/net/wireless/realtek/rtw88/rtw8822c.c | 1 + - drivers/net/wireless/realtek/rtw88/usb.c | 4 +++- - 9 files changed, 20 insertions(+), 1 deletion(-) - -diff --git a/drivers/net/wireless/realtek/rtw88/mac.c b/drivers/net/wireless/realtek/rtw88/mac.c -index 0dba8aae771603..564f5988ee82a7 100644 ---- a/drivers/net/wireless/realtek/rtw88/mac.c -+++ b/drivers/net/wireless/realtek/rtw88/mac.c -@@ -1201,6 +1201,15 @@ static int __priority_queue_cfg(struct rtw_dev *rtwdev, - rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary); - rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary); - rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1); -+ -+ if (rtwdev->hci.type == RTW_HCI_TYPE_USB) { -+ rtw_write8_mask(rtwdev, REG_AUTO_LLT_V1, BIT_MASK_BLK_DESC_NUM, -+ chip->usb_tx_agg_desc_num); -+ -+ rtw_write8(rtwdev, REG_AUTO_LLT_V1 + 3, chip->usb_tx_agg_desc_num); -+ rtw_write8_set(rtwdev, REG_TXDMA_OFFSET_CHK + 1, BIT(1)); -+ } -+ - rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1); - - if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0)) -diff --git a/drivers/net/wireless/realtek/rtw88/main.h b/drivers/net/wireless/realtek/rtw88/main.h -index 49894331f7b495..49a3fd4fb7dcdc 100644 ---- a/drivers/net/wireless/realtek/rtw88/main.h -+++ b/drivers/net/wireless/realtek/rtw88/main.h -@@ -1197,6 +1197,8 @@ struct rtw_chip_info { - u16 fw_fifo_addr[RTW_FW_FIFO_MAX]; - const struct rtw_fwcd_segs *fwcd_segs; - -+ u8 usb_tx_agg_desc_num; -+ - u8 default_1ss_tx_path; - - bool path_div_supported; -diff --git a/drivers/net/wireless/realtek/rtw88/reg.h b/drivers/net/wireless/realtek/rtw88/reg.h -index b122f226924be5..02ef9a77316b48 100644 ---- a/drivers/net/wireless/realtek/rtw88/reg.h -+++ b/drivers/net/wireless/realtek/rtw88/reg.h -@@ -270,6 +270,7 @@ - #define BIT_MASK_BCN_HEAD_1_V1 0xfff - #define REG_AUTO_LLT_V1 0x0208 - #define BIT_AUTO_INIT_LLT_V1 BIT(0) -+#define BIT_MASK_BLK_DESC_NUM GENMASK(7, 4) - #define REG_DWBCN0_CTRL 0x0208 - #define BIT_BCN_VALID BIT(16) - #define REG_TXDMA_OFFSET_CHK 0x020C -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8703b.c b/drivers/net/wireless/realtek/rtw88/rtw8703b.c -index 8919f9e11f0378..222608de33cdec 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8703b.c -+++ b/drivers/net/wireless/realtek/rtw88/rtw8703b.c -@@ -2013,6 +2013,7 @@ const struct rtw_chip_info rtw8703b_hw_spec = { - .tx_stbc = false, - .max_power_index = 0x3f, - .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, -+ .usb_tx_agg_desc_num = 1, /* Not sure if this chip has USB interface */ - - .path_div_supported = false, - .ht_supported = true, -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8723d.c b/drivers/net/wireless/realtek/rtw88/rtw8723d.c -index f8df4c84d39f73..3fba4054d45f49 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8723d.c -+++ b/drivers/net/wireless/realtek/rtw88/rtw8723d.c -@@ -2171,6 +2171,7 @@ const struct rtw_chip_info rtw8723d_hw_spec = { - .band = RTW_BAND_2G, - .page_size = TX_PAGE_SIZE, - .dig_min = 0x20, -+ .usb_tx_agg_desc_num = 1, - .ht_supported = true, - .vht_supported = false, - .lps_deep_mode_supported = 0, -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8821c.c b/drivers/net/wireless/realtek/rtw88/rtw8821c.c -index fe5d8e18835093..526e8de77b3e82 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8821c.c -+++ b/drivers/net/wireless/realtek/rtw88/rtw8821c.c -@@ -2008,6 +2008,7 @@ const struct rtw_chip_info rtw8821c_hw_spec = { - .band = RTW_BAND_2G | RTW_BAND_5G, - .page_size = TX_PAGE_SIZE, - .dig_min = 0x1c, -+ .usb_tx_agg_desc_num = 3, - .ht_supported = true, - .vht_supported = true, - .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8822b.c b/drivers/net/wireless/realtek/rtw88/rtw8822b.c -index 3017a9760da8dc..2456ff24281801 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8822b.c -+++ b/drivers/net/wireless/realtek/rtw88/rtw8822b.c -@@ -2548,6 +2548,7 @@ const struct rtw_chip_info rtw8822b_hw_spec = { - .band = RTW_BAND_2G | RTW_BAND_5G, - .page_size = TX_PAGE_SIZE, - .dig_min = 0x1c, -+ .usb_tx_agg_desc_num = 3, - .ht_supported = true, - .vht_supported = true, - .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8822c.c b/drivers/net/wireless/realtek/rtw88/rtw8822c.c -index cd965edc29cea3..62376d1cca22fc 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8822c.c -+++ b/drivers/net/wireless/realtek/rtw88/rtw8822c.c -@@ -5366,6 +5366,7 @@ const struct rtw_chip_info rtw8822c_hw_spec = { - .band = RTW_BAND_2G | RTW_BAND_5G, - .page_size = TX_PAGE_SIZE, - .dig_min = 0x20, -+ .usb_tx_agg_desc_num = 3, - .default_1ss_tx_path = BB_PATH_A, - .path_div_supported = true, - .ht_supported = true, -diff --git a/drivers/net/wireless/realtek/rtw88/usb.c b/drivers/net/wireless/realtek/rtw88/usb.c -index d204d138afe298..057c0ffbe94472 100644 ---- a/drivers/net/wireless/realtek/rtw88/usb.c -+++ b/drivers/net/wireless/realtek/rtw88/usb.c -@@ -379,7 +379,9 @@ static bool rtw_usb_tx_agg_skb(struct rtw_usb *rtwusb, struct sk_buff_head *list - - skb_iter = skb_peek(list); - -- if (skb_iter && skb_iter->len + skb_head->len <= RTW_USB_MAX_XMITBUF_SZ) -+ if (skb_iter && -+ skb_iter->len + skb_head->len <= RTW_USB_MAX_XMITBUF_SZ && -+ agg_num < rtwdev->chip->usb_tx_agg_desc_num) - __skb_unlink(skb_iter, list); - else - skb_iter = NULL; diff --git a/packages/linux/patches/rtlwifi/6.11/0014-6.11-wifi-rtw88-usb-Simplify-rtw_usb_write_data.patch b/packages/linux/patches/rtlwifi/6.11/0014-6.11-wifi-rtw88-usb-Simplify-rtw_usb_write_data.patch deleted file mode 100644 index e4f035833e..0000000000 --- a/packages/linux/patches/rtlwifi/6.11/0014-6.11-wifi-rtw88-usb-Simplify-rtw_usb_write_data.patch +++ /dev/null @@ -1,51 +0,0 @@ -From a892f6ffbec7a1a25c639534bee62200418242f9 Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Fri, 3 May 2024 13:53:28 +0300 -Subject: [PATCH] wifi: rtw88: usb: Simplify rtw_usb_write_data - -The skb created in this function always has the same headroom, -the chip's TX descriptor size. (pkt_info->offset is set by -rtw_usb_write_data_rsvd_page() to chip->tx_pkt_desc_sz.) Use -chip->tx_pkt_desc_sz directly. - -Signed-off-by: Bitterblue Smith -Tested-by: Larry Finger -Signed-off-by: Ping-Ke Shih -Link: https://msgid.link/2479507e-3946-492f-857e-83e54969aad2@gmail.com ---- - drivers/net/wireless/realtek/rtw88/usb.c | 12 +++++------- - 1 file changed, 5 insertions(+), 7 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtw88/usb.c b/drivers/net/wireless/realtek/rtw88/usb.c -index a0188511099a1b..90afeefe002f37 100644 ---- a/drivers/net/wireless/realtek/rtw88/usb.c -+++ b/drivers/net/wireless/realtek/rtw88/usb.c -@@ -433,23 +433,21 @@ static int rtw_usb_write_data(struct rtw_dev *rtwdev, - { - const struct rtw_chip_info *chip = rtwdev->chip; - struct sk_buff *skb; -- unsigned int desclen, headsize, size; -+ unsigned int size; - u8 qsel; - int ret = 0; - - size = pkt_info->tx_pkt_size; - qsel = pkt_info->qsel; -- desclen = chip->tx_pkt_desc_sz; -- headsize = pkt_info->offset ? pkt_info->offset : desclen; - -- skb = dev_alloc_skb(headsize + size); -+ skb = dev_alloc_skb(chip->tx_pkt_desc_sz + size); - if (unlikely(!skb)) - return -ENOMEM; - -- skb_reserve(skb, headsize); -+ skb_reserve(skb, chip->tx_pkt_desc_sz); - skb_put_data(skb, buf, size); -- skb_push(skb, headsize); -- memset(skb->data, 0, headsize); -+ skb_push(skb, chip->tx_pkt_desc_sz); -+ memset(skb->data, 0, chip->tx_pkt_desc_sz); - rtw_tx_fill_tx_desc(pkt_info, skb); - rtw_tx_fill_txdesc_checksum(rtwdev, pkt_info, skb->data); - diff --git a/packages/linux/patches/rtlwifi/6.12/0001-6.12-wifi-rtw88-usb-Support-USB-3-with-RTL8822CU-RTL8822B.patch b/packages/linux/patches/rtlwifi/6.12/0001-6.12-wifi-rtw88-usb-Support-USB-3-with-RTL8822CU-RTL8822B.patch deleted file mode 100644 index 6091e6a612..0000000000 --- a/packages/linux/patches/rtlwifi/6.12/0001-6.12-wifi-rtw88-usb-Support-USB-3-with-RTL8822CU-RTL8822B.patch +++ /dev/null @@ -1,303 +0,0 @@ -From 3c64d161a450d62330ad79d2b5f92c115b11622d Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 11 Jul 2024 01:11:33 +0300 -Subject: [PATCH 1/7] wifi: rtw88: usb: Support USB 3 with RTL8822CU/RTL8822BU - -The Realtek wifi 5 devices which support USB 3 are weird: when first -plugged in, they pretend to be USB 2. The driver needs to send some -commands to the device, which make it disappear and come back as a -USB 3 device. - -Implement the required commands in rtw88. - -When a USB 3 device is plugged into a USB 2 port, rtw88 will try to -switch it to USB 3 mode only once. The device will disappear and come -back still in USB 2 mode, of course. - -Some people experience heavy interference in the 2.4 GHz band in -USB 3 mode, so add a module parameter switch_usb_mode with the -default value 1 to let people disable the switching. - -Signed-off-by: Bitterblue Smith -Acked-by: Ping-Ke Shih -Signed-off-by: Ping-Ke Shih -Link: https://patch.msgid.link/77906c62-5674-426f-bde1-1b2a12a0339d@gmail.com ---- - drivers/net/wireless/realtek/rtw88/debug.h | 1 + - drivers/net/wireless/realtek/rtw88/main.h | 2 + - drivers/net/wireless/realtek/rtw88/reg.h | 11 +++ - drivers/net/wireless/realtek/rtw88/rtw8822b.c | 1 + - drivers/net/wireless/realtek/rtw88/rtw8822b.h | 4 +- - drivers/net/wireless/realtek/rtw88/rtw8822c.c | 1 + - drivers/net/wireless/realtek/rtw88/rtw8822c.h | 24 +++--- - drivers/net/wireless/realtek/rtw88/usb.c | 84 +++++++++++++++++++ - 8 files changed, 116 insertions(+), 12 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtw88/debug.h b/drivers/net/wireless/realtek/rtw88/debug.h -index eb69006c463e..9a1e0e85a13c 100644 ---- a/drivers/net/wireless/realtek/rtw88/debug.h -+++ b/drivers/net/wireless/realtek/rtw88/debug.h -@@ -25,6 +25,7 @@ enum rtw_debug_mask { - RTW_DBG_HW_SCAN = 0x00010000, - RTW_DBG_STATE = 0x00020000, - RTW_DBG_SDIO = 0x00040000, -+ RTW_DBG_USB = 0x00080000, - - RTW_DBG_UNEXP = 0x80000000, - RTW_DBG_ALL = 0xffffffff -diff --git a/drivers/net/wireless/realtek/rtw88/main.h b/drivers/net/wireless/realtek/rtw88/main.h -index 49a3fd4fb7dc..9d21637cf5d5 100644 ---- a/drivers/net/wireless/realtek/rtw88/main.h -+++ b/drivers/net/wireless/realtek/rtw88/main.h -@@ -1785,6 +1785,8 @@ struct rtw_efuse { - bool share_ant; - u8 bt_setting; - -+ u8 usb_mode_switch; -+ - struct { - u8 hci; - u8 bw; -diff --git a/drivers/net/wireless/realtek/rtw88/reg.h b/drivers/net/wireless/realtek/rtw88/reg.h -index 02ef9a77316b..e7b24465f549 100644 ---- a/drivers/net/wireless/realtek/rtw88/reg.h -+++ b/drivers/net/wireless/realtek/rtw88/reg.h -@@ -15,6 +15,7 @@ - #define BIT_WLOCK_1C_B6 BIT(5) - #define REG_SYS_PW_CTRL 0x0004 - #define BIT_PFM_WOWL BIT(3) -+#define BIT_APFM_OFFMAC BIT(9) - #define REG_SYS_CLK_CTRL 0x0008 - #define BIT_CPU_CLK_EN BIT(14) - -@@ -133,6 +134,14 @@ - #define REG_PMC_DBG_CTRL1 0xa8 - #define BITS_PMC_BT_IQK_STS GENMASK(22, 21) - -+#define REG_PAD_CTRL2 0x00C4 -+#define BIT_RSM_EN_V1 BIT(16) -+#define BIT_NO_PDN_CHIPOFF_V1 BIT(17) -+#define BIT_MASK_USB23_SW_MODE_V1 GENMASK(19, 18) -+#define BIT_USB3_USB2_TRANSITION BIT(20) -+#define BIT_USB_MODE_U2 1 -+#define BIT_USB_MODE_U3 2 -+ - #define REG_EFUSE_ACCESS 0x00CF - #define EFUSE_ACCESS_ON 0x69 - #define EFUSE_ACCESS_OFF 0x00 -@@ -568,6 +577,8 @@ - #define BIT_WL_SECURITY_CLK BIT(15) - #define BIT_DDMA_EN BIT(8) - -+#define REG_SW_MDIO 0x10C0 -+ - #define REG_H2C_PKT_READADDR 0x10D0 - #define REG_H2C_PKT_WRITEADDR 0x10D4 - #define REG_FW_DBG6 0x10F8 -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8822b.c b/drivers/net/wireless/realtek/rtw88/rtw8822b.c -index 2456ff242818..6edb17aea90e 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8822b.c -+++ b/drivers/net/wireless/realtek/rtw88/rtw8822b.c -@@ -46,6 +46,7 @@ static int rtw8822b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) - - map = (struct rtw8822b_efuse *)log_map; - -+ efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(7)); - efuse->rfe_option = map->rfe_option; - efuse->rf_board_option = map->rf_board_option; - efuse->crystal_cap = map->xtal_k; -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8822b.h b/drivers/net/wireless/realtek/rtw88/rtw8822b.h -index 2dc3a6660f06..cf85e63966a1 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8822b.h -+++ b/drivers/net/wireless/realtek/rtw88/rtw8822b.h -@@ -72,7 +72,9 @@ struct rtw8822bs_efuse { - - struct rtw8822b_efuse { - __le16 rtl_id; -- u8 res0[0x0e]; -+ u8 res0[4]; -+ u8 usb_mode; -+ u8 res1[0x09]; - - /* power index for four RF paths */ - struct rtw_txpwr_idx txpwr_idx_table[4]; -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8822c.c b/drivers/net/wireless/realtek/rtw88/rtw8822c.c -index 62376d1cca22..bc807b13e9ce 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8822c.c -+++ b/drivers/net/wireless/realtek/rtw88/rtw8822c.c -@@ -49,6 +49,7 @@ static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) - - map = (struct rtw8822c_efuse *)log_map; - -+ efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(7)); - efuse->rfe_option = map->rfe_option; - efuse->rf_board_option = map->rf_board_option; - efuse->crystal_cap = map->xtal_k & XCAP_MASK; -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8822c.h b/drivers/net/wireless/realtek/rtw88/rtw8822c.h -index 1bc0e7f5d6bb..e2b383d633cd 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8822c.h -+++ b/drivers/net/wireless/realtek/rtw88/rtw8822c.h -@@ -59,16 +59,18 @@ struct rtw8822ce_efuse { - - struct rtw8822c_efuse { - __le16 rtl_id; -- u8 res0[0x0e]; -+ u8 res0[4]; -+ u8 usb_mode; -+ u8 res1[0x09]; - - /* power index for four RF paths */ - struct rtw_txpwr_idx txpwr_idx_table[4]; - - u8 channel_plan; /* 0xb8 */ - u8 xtal_k; -- u8 res1; -+ u8 res2; - u8 iqk_lck; -- u8 res2[5]; /* 0xbc */ -+ u8 res3[5]; /* 0xbc */ - u8 rf_board_option; - u8 rf_feature_option; - u8 rf_bt_setting; -@@ -80,21 +82,21 @@ struct rtw8822c_efuse { - u8 rf_antenna_option; /* 0xc9 */ - u8 rfe_option; - u8 country_code[2]; -- u8 res3[3]; -+ u8 res4[3]; - u8 path_a_thermal; /* 0xd0 */ - u8 path_b_thermal; -- u8 res4[2]; -+ u8 res5[2]; - u8 rx_gain_gap_2g_ofdm; -- u8 res5; -- u8 rx_gain_gap_2g_cck; - u8 res6; -- u8 rx_gain_gap_5gl; -+ u8 rx_gain_gap_2g_cck; - u8 res7; -- u8 rx_gain_gap_5gm; -+ u8 rx_gain_gap_5gl; - u8 res8; -- u8 rx_gain_gap_5gh; -+ u8 rx_gain_gap_5gm; - u8 res9; -- u8 res10[0x42]; -+ u8 rx_gain_gap_5gh; -+ u8 res10; -+ u8 res11[0x42]; - union { - struct rtw8822ce_efuse e; - struct rtw8822cu_efuse u; -diff --git a/drivers/net/wireless/realtek/rtw88/usb.c b/drivers/net/wireless/realtek/rtw88/usb.c -index a55ca5a24227..251a5726f3ee 100644 ---- a/drivers/net/wireless/realtek/rtw88/usb.c -+++ b/drivers/net/wireless/realtek/rtw88/usb.c -@@ -14,6 +14,11 @@ - #include "ps.h" - #include "usb.h" - -+static bool rtw_switch_usb_mode = true; -+module_param_named(switch_usb_mode, rtw_switch_usb_mode, bool, 0644); -+MODULE_PARM_DESC(switch_usb_mode, -+ "Set to N to disable switching to USB 3 mode to avoid potential interference in the 2.4 GHz band (default: Y)"); -+ - #define RTW_USB_MAX_RXQ_LEN 512 - - struct rtw_usb_txcb { -@@ -841,6 +846,77 @@ static void rtw_usb_intf_deinit(struct rtw_dev *rtwdev, - usb_set_intfdata(intf, NULL); - } - -+static int rtw_usb_switch_mode_new(struct rtw_dev *rtwdev) -+{ -+ enum usb_device_speed cur_speed; -+ u8 id = rtwdev->chip->id; -+ bool can_switch; -+ u32 pad_ctrl2; -+ -+ if (rtw_read8(rtwdev, REG_SYS_CFG2 + 3) == 0x20) -+ cur_speed = USB_SPEED_SUPER; -+ else -+ cur_speed = USB_SPEED_HIGH; -+ -+ if (cur_speed == USB_SPEED_SUPER) -+ return 0; -+ -+ pad_ctrl2 = rtw_read32(rtwdev, REG_PAD_CTRL2); -+ -+ can_switch = !!(pad_ctrl2 & (BIT_MASK_USB23_SW_MODE_V1 | -+ BIT_USB3_USB2_TRANSITION)); -+ -+ if (!can_switch) { -+ rtw_dbg(rtwdev, RTW_DBG_USB, -+ "Switching to USB 3 mode unsupported by the chip\n"); -+ return 0; -+ } -+ -+ /* At this point cur_speed is USB_SPEED_HIGH. If we already tried -+ * to switch don't try again - it's a USB 2 port. -+ */ -+ if (u32_get_bits(pad_ctrl2, BIT_MASK_USB23_SW_MODE_V1) == BIT_USB_MODE_U3) -+ return 0; -+ -+ /* Enable IO wrapper timeout */ -+ if (id == RTW_CHIP_TYPE_8822B || id == RTW_CHIP_TYPE_8821C) -+ rtw_write8_clr(rtwdev, REG_SW_MDIO + 3, BIT(0)); -+ -+ u32p_replace_bits(&pad_ctrl2, BIT_USB_MODE_U3, BIT_MASK_USB23_SW_MODE_V1); -+ pad_ctrl2 |= BIT_RSM_EN_V1; -+ -+ rtw_write32(rtwdev, REG_PAD_CTRL2, pad_ctrl2); -+ rtw_write8(rtwdev, REG_PAD_CTRL2 + 1, 4); -+ -+ rtw_write16_set(rtwdev, REG_SYS_PW_CTRL, BIT_APFM_OFFMAC); -+ usleep_range(1000, 1001); -+ rtw_write32_set(rtwdev, REG_PAD_CTRL2, BIT_NO_PDN_CHIPOFF_V1); -+ -+ return 1; -+} -+ -+static int rtw_usb_switch_mode(struct rtw_dev *rtwdev) -+{ -+ u8 id = rtwdev->chip->id; -+ -+ if (id != RTW_CHIP_TYPE_8822C && id != RTW_CHIP_TYPE_8822B) -+ return 0; -+ -+ if (!rtwdev->efuse.usb_mode_switch) { -+ rtw_dbg(rtwdev, RTW_DBG_USB, -+ "Switching to USB 3 mode disabled by chip's efuse\n"); -+ return 0; -+ } -+ -+ if (!rtw_switch_usb_mode) { -+ rtw_dbg(rtwdev, RTW_DBG_USB, -+ "Switching to USB 3 mode disabled by module parameter\n"); -+ return 0; -+ } -+ -+ return rtw_usb_switch_mode_new(rtwdev); -+} -+ - int rtw_usb_probe(struct usb_interface *intf, const struct usb_device_id *id) - { - struct rtw_dev *rtwdev; -@@ -896,6 +972,14 @@ int rtw_usb_probe(struct usb_interface *intf, const struct usb_device_id *id) - goto err_destroy_rxwq; - } - -+ ret = rtw_usb_switch_mode(rtwdev); -+ if (ret) { -+ /* Not a fail, but we do need to skip rtw_register_hw. */ -+ rtw_dbg(rtwdev, RTW_DBG_USB, "switching to USB 3 mode\n"); -+ ret = 0; -+ goto err_destroy_rxwq; -+ } -+ - ret = rtw_register_hw(rtwdev, rtwdev->hw); - if (ret) { - rtw_err(rtwdev, "failed to register hw\n"); --- -2.43.0 - diff --git a/packages/linux/patches/rtlwifi/6.12/0003-6.12-wifi-rtw88-8822c-Parse-channel-from-IE-to-correct-in.patch b/packages/linux/patches/rtlwifi/6.12/0003-6.12-wifi-rtw88-8822c-Parse-channel-from-IE-to-correct-in.patch deleted file mode 100644 index b3f01e5bf6..0000000000 --- a/packages/linux/patches/rtlwifi/6.12/0003-6.12-wifi-rtw88-8822c-Parse-channel-from-IE-to-correct-in.patch +++ /dev/null @@ -1,168 +0,0 @@ -From c1ca6ece1a989240c04f9a77230592cc92ff823c Mon Sep 17 00:00:00 2001 -From: Po-Hao Huang -Date: Wed, 24 Jul 2024 13:05:01 +0800 -Subject: [PATCH 3/7] wifi: rtw88: 8822c: Parse channel from IE to correct - invalid hardware reports - -For CCK packets we could get incorrect reports from hardware. -And this causes wrong frequencies being reported. Parse the channel -information from IE if provided by AP to fix this. - -Signed-off-by: Po-Hao Huang -Signed-off-by: Ping-Ke Shih -Link: https://patch.msgid.link/20240724050501.7550-1-pkshih@realtek.com ---- - drivers/net/wireless/realtek/rtw88/main.h | 1 + - drivers/net/wireless/realtek/rtw88/pci.c | 1 + - drivers/net/wireless/realtek/rtw88/rtw8822c.c | 7 ++-- - drivers/net/wireless/realtek/rtw88/rx.c | 41 +++++++++++++++++++ - drivers/net/wireless/realtek/rtw88/rx.h | 13 ++++++ - drivers/net/wireless/realtek/rtw88/sdio.c | 1 + - drivers/net/wireless/realtek/rtw88/usb.c | 2 + - 7 files changed, 63 insertions(+), 3 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtw88/main.h b/drivers/net/wireless/realtek/rtw88/main.h -index 9d21637cf5d5..37912dded128 100644 ---- a/drivers/net/wireless/realtek/rtw88/main.h -+++ b/drivers/net/wireless/realtek/rtw88/main.h -@@ -622,6 +622,7 @@ struct rtw_rx_pkt_stat { - bool crc_err; - bool decrypted; - bool is_c2h; -+ bool channel_invalid; - - s32 signal_power; - u16 pkt_len; -diff --git a/drivers/net/wireless/realtek/rtw88/pci.c b/drivers/net/wireless/realtek/rtw88/pci.c -index a5b9d6c7be37..5d0580da13fb 100644 ---- a/drivers/net/wireless/realtek/rtw88/pci.c -+++ b/drivers/net/wireless/realtek/rtw88/pci.c -@@ -1088,6 +1088,7 @@ static u32 rtw_pci_rx_napi(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci, - /* remove rx_desc */ - skb_pull(new, pkt_offset); - -+ rtw_update_rx_freq_for_invalid(rtwdev, new, &rx_status, &pkt_stat); - rtw_rx_stats(rtwdev, pkt_stat.vif, new); - memcpy(new->cb, &rx_status, sizeof(rx_status)); - ieee80211_rx_napi(rtwdev->hw, NULL, new, napi); -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8822c.c b/drivers/net/wireless/realtek/rtw88/rtw8822c.c -index bc807b13e9ce..96a233079e02 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8822c.c -+++ b/drivers/net/wireless/realtek/rtw88/rtw8822c.c -@@ -2576,9 +2576,10 @@ static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, - rx_power[RF_PATH_B] -= 110; - - channel = GET_PHY_STAT_P0_CHANNEL(phy_status); -- if (channel == 0) -- channel = rtwdev->hal.current_channel; -- rtw_set_rx_freq_band(pkt_stat, channel); -+ if (channel != 0) -+ rtw_set_rx_freq_band(pkt_stat, channel); -+ else -+ pkt_stat->channel_invalid = true; - - pkt_stat->rx_power[RF_PATH_A] = rx_power[RF_PATH_A]; - pkt_stat->rx_power[RF_PATH_B] = rx_power[RF_PATH_B]; -diff --git a/drivers/net/wireless/realtek/rtw88/rx.c b/drivers/net/wireless/realtek/rtw88/rx.c -index 84aedabdf285..66f9419588cf 100644 ---- a/drivers/net/wireless/realtek/rtw88/rx.c -+++ b/drivers/net/wireless/realtek/rtw88/rx.c -@@ -146,6 +146,47 @@ static void rtw_set_rx_freq_by_pktstat(struct rtw_rx_pkt_stat *pkt_stat, - rx_status->band = pkt_stat->band; - } - -+void rtw_update_rx_freq_from_ie(struct rtw_dev *rtwdev, struct sk_buff *skb, -+ struct ieee80211_rx_status *rx_status, -+ struct rtw_rx_pkt_stat *pkt_stat) -+{ -+ struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; -+ int channel = rtwdev->hal.current_channel; -+ size_t hdr_len, ielen; -+ int channel_number; -+ u8 *variable; -+ -+ if (!test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) -+ goto fill_rx_status; -+ -+ if (ieee80211_is_beacon(mgmt->frame_control)) { -+ variable = mgmt->u.beacon.variable; -+ hdr_len = offsetof(struct ieee80211_mgmt, -+ u.beacon.variable); -+ } else if (ieee80211_is_probe_resp(mgmt->frame_control)) { -+ variable = mgmt->u.probe_resp.variable; -+ hdr_len = offsetof(struct ieee80211_mgmt, -+ u.probe_resp.variable); -+ } else { -+ goto fill_rx_status; -+ } -+ -+ if (skb->len > hdr_len) -+ ielen = skb->len - hdr_len; -+ else -+ goto fill_rx_status; -+ -+ channel_number = cfg80211_get_ies_channel_number(variable, ielen, -+ NL80211_BAND_2GHZ); -+ if (channel_number != -1) -+ channel = channel_number; -+ -+fill_rx_status: -+ rtw_set_rx_freq_band(pkt_stat, channel); -+ rtw_set_rx_freq_by_pktstat(pkt_stat, rx_status); -+} -+EXPORT_SYMBOL(rtw_update_rx_freq_from_ie); -+ - void rtw_rx_fill_rx_status(struct rtw_dev *rtwdev, - struct rtw_rx_pkt_stat *pkt_stat, - struct ieee80211_hdr *hdr, -diff --git a/drivers/net/wireless/realtek/rtw88/rx.h b/drivers/net/wireless/realtek/rtw88/rx.h -index 8a072dd3d73c..9f0019112987 100644 ---- a/drivers/net/wireless/realtek/rtw88/rx.h -+++ b/drivers/net/wireless/realtek/rtw88/rx.h -@@ -50,5 +50,18 @@ void rtw_rx_fill_rx_status(struct rtw_dev *rtwdev, - struct ieee80211_hdr *hdr, - struct ieee80211_rx_status *rx_status, - u8 *phy_status); -+void rtw_update_rx_freq_from_ie(struct rtw_dev *rtwdev, struct sk_buff *skb, -+ struct ieee80211_rx_status *rx_status, -+ struct rtw_rx_pkt_stat *pkt_stat); -+ -+static inline -+void rtw_update_rx_freq_for_invalid(struct rtw_dev *rtwdev, struct sk_buff *skb, -+ struct ieee80211_rx_status *rx_status, -+ struct rtw_rx_pkt_stat *pkt_stat) -+{ -+ if (pkt_stat->channel_invalid) -+ rtw_update_rx_freq_from_ie(rtwdev, skb, rx_status, pkt_stat); -+} -+ - - #endif -diff --git a/drivers/net/wireless/realtek/rtw88/sdio.c b/drivers/net/wireless/realtek/rtw88/sdio.c -index 0cae5746f540..763aa8212a4b 100644 ---- a/drivers/net/wireless/realtek/rtw88/sdio.c -+++ b/drivers/net/wireless/realtek/rtw88/sdio.c -@@ -948,6 +948,7 @@ static void rtw_sdio_rx_skb(struct rtw_dev *rtwdev, struct sk_buff *skb, - skb_put(skb, pkt_stat->pkt_len); - skb_reserve(skb, pkt_offset); - -+ rtw_update_rx_freq_for_invalid(rtwdev, skb, rx_status, pkt_stat); - rtw_rx_stats(rtwdev, pkt_stat->vif, skb); - - ieee80211_rx_irqsafe(rtwdev->hw, skb); -diff --git a/drivers/net/wireless/realtek/rtw88/usb.c b/drivers/net/wireless/realtek/rtw88/usb.c -index 251a5726f3ee..9145c11a063e 100644 ---- a/drivers/net/wireless/realtek/rtw88/usb.c -+++ b/drivers/net/wireless/realtek/rtw88/usb.c -@@ -579,6 +579,8 @@ static void rtw_usb_rx_handler(struct work_struct *work) - - skb_put(skb, pkt_stat.pkt_len); - skb_reserve(skb, pkt_offset); -+ -+ rtw_update_rx_freq_for_invalid(rtwdev, skb, &rx_status, &pkt_stat); - memcpy(skb->cb, &rx_status, sizeof(rx_status)); - ieee80211_rx_irqsafe(rtwdev->hw, skb); - } --- -2.43.0 - diff --git a/packages/linux/patches/rtlwifi/6.12/0004-6.12-wifi-rtw88-usb-Init-RX-burst-length-according-to-USB.patch b/packages/linux/patches/rtlwifi/6.12/0004-6.12-wifi-rtw88-usb-Init-RX-burst-length-according-to-USB.patch deleted file mode 100644 index 9182801008..0000000000 --- a/packages/linux/patches/rtlwifi/6.12/0004-6.12-wifi-rtw88-usb-Init-RX-burst-length-according-to-USB.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 93523589d4dae8567b471743e8c6a88bf80750c4 Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 8 Aug 2024 01:19:36 +0300 -Subject: [PATCH 4/7] wifi: rtw88: usb: Init RX burst length according to USB - speed - -This is needed in order to make USB RX aggregation work with RTL8811CU -(and presumably RTL8822BU and RTL8822CU also). - -I don't know what BIT_DMA_BURST_CNT, BIT_DMA_MODE, and BIT_DROP_DATA_EN -are doing. - -Tested with RTL8822CU, RTL8811CU, and RTL8723DU. - -The RX speed is unchanged in my tests. - -Tested-by: Sascha Hauer -Signed-off-by: Bitterblue Smith -Signed-off-by: Ping-Ke Shih -Link: https://patch.msgid.link/ac569c6f-7129-4341-b523-901fe10cabff@gmail.com ---- - drivers/net/wireless/realtek/rtw88/reg.h | 6 ++++++ - drivers/net/wireless/realtek/rtw88/usb.c | 23 ++++++++++++++++++++++- - 2 files changed, 28 insertions(+), 1 deletion(-) - -diff --git a/drivers/net/wireless/realtek/rtw88/reg.h b/drivers/net/wireless/realtek/rtw88/reg.h -index e7b24465f549..4d9b8668e8b0 100644 ---- a/drivers/net/wireless/realtek/rtw88/reg.h -+++ b/drivers/net/wireless/realtek/rtw88/reg.h -@@ -322,6 +322,12 @@ - #define REG_RXDMA_DPR 0x028C - #define REG_RXDMA_MODE 0x0290 - #define BIT_DMA_MODE BIT(1) -+#define BIT_DMA_BURST_CNT GENMASK(3, 2) -+#define BIT_DMA_BURST_SIZE GENMASK(5, 4) -+#define BIT_DMA_BURST_SIZE_64 2 -+#define BIT_DMA_BURST_SIZE_512 1 -+#define BIT_DMA_BURST_SIZE_1024 0 -+ - #define REG_RXPKTNUM 0x02B0 - - #define REG_INT_MIG 0x0304 -diff --git a/drivers/net/wireless/realtek/rtw88/usb.c b/drivers/net/wireless/realtek/rtw88/usb.c -index 9145c11a063e..1c40d46a7eb4 100644 ---- a/drivers/net/wireless/realtek/rtw88/usb.c -+++ b/drivers/net/wireless/realtek/rtw88/usb.c -@@ -720,9 +720,30 @@ static void rtw_usb_link_ps(struct rtw_dev *rtwdev, bool enter) - /* empty function for rtw_hci_ops */ - } - -+static void rtw_usb_init_burst_pkt_len(struct rtw_dev *rtwdev) -+{ -+ struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev); -+ enum usb_device_speed speed = rtwusb->udev->speed; -+ u8 rxdma, burst_size; -+ -+ rxdma = BIT_DMA_BURST_CNT | BIT_DMA_MODE; -+ -+ if (speed == USB_SPEED_SUPER) -+ burst_size = BIT_DMA_BURST_SIZE_1024; -+ else if (speed == USB_SPEED_HIGH) -+ burst_size = BIT_DMA_BURST_SIZE_512; -+ else -+ burst_size = BIT_DMA_BURST_SIZE_64; -+ -+ u8p_replace_bits(&rxdma, burst_size, BIT_DMA_BURST_SIZE); -+ -+ rtw_write8(rtwdev, REG_RXDMA_MODE, rxdma); -+ rtw_write16_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN); -+} -+ - static void rtw_usb_interface_cfg(struct rtw_dev *rtwdev) - { -- /* empty function for rtw_hci_ops */ -+ rtw_usb_init_burst_pkt_len(rtwdev); - } - - static struct rtw_hci_ops rtw_usb_ops = { --- -2.43.0 - diff --git a/packages/linux/patches/rtlwifi/6.12/0005-6.12-wifi-rtw88-usb-Update-the-RX-stats-after-every-frame.patch b/packages/linux/patches/rtlwifi/6.12/0005-6.12-wifi-rtw88-usb-Update-the-RX-stats-after-every-frame.patch deleted file mode 100644 index add2d9da6f..0000000000 --- a/packages/linux/patches/rtlwifi/6.12/0005-6.12-wifi-rtw88-usb-Update-the-RX-stats-after-every-frame.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 7198cca8f07045773f92befd8861bb5b3f8bd83d Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 8 Aug 2024 01:20:36 +0300 -Subject: [PATCH 5/7] wifi: rtw88: usb: Update the RX stats after every frame - -Update the number of received unicast data frames and bytes every time -a frame is received. This is what the PCI and SDIO drivers do. - -This has an influence on the power saving, bluetooth coexistence, and -(in a future patch) the use of RX aggregation. - -Tested with RTL8822CU, RTL8811CU, and RTL8723DU. - -Tested-by: Sascha Hauer -Signed-off-by: Bitterblue Smith -Signed-off-by: Ping-Ke Shih -Link: https://patch.msgid.link/75a2ca52-8f01-45c5-926f-d3a68ae3b284@gmail.com ---- - drivers/net/wireless/realtek/rtw88/usb.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/net/wireless/realtek/rtw88/usb.c b/drivers/net/wireless/realtek/rtw88/usb.c -index 1c40d46a7eb4..10f1d724370e 100644 ---- a/drivers/net/wireless/realtek/rtw88/usb.c -+++ b/drivers/net/wireless/realtek/rtw88/usb.c -@@ -581,6 +581,7 @@ static void rtw_usb_rx_handler(struct work_struct *work) - skb_reserve(skb, pkt_offset); - - rtw_update_rx_freq_for_invalid(rtwdev, skb, &rx_status, &pkt_stat); -+ rtw_rx_stats(rtwdev, pkt_stat.vif, skb); - memcpy(skb->cb, &rx_status, sizeof(rx_status)); - ieee80211_rx_irqsafe(rtwdev->hw, skb); - } --- -2.43.0 - diff --git a/packages/linux/patches/rtlwifi/6.12/0006-6.12-wifi-rtw88-usb-Support-RX-aggregation.patch b/packages/linux/patches/rtlwifi/6.12/0006-6.12-wifi-rtw88-usb-Support-RX-aggregation.patch deleted file mode 100644 index b42de702b3..0000000000 --- a/packages/linux/patches/rtlwifi/6.12/0006-6.12-wifi-rtw88-usb-Support-RX-aggregation.patch +++ /dev/null @@ -1,123 +0,0 @@ -From 8e07253c6c1c00d2dc5fc8937f3ab15c23be5367 Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 8 Aug 2024 01:21:36 +0300 -Subject: [PATCH 6/7] wifi: rtw88: usb: Support RX aggregation - -The chips can be configured to aggregate several frames into a single -USB transfer. Modify rtw_usb_rx_handler() to support this case. - -RX aggregation improves the RX speed of RTL8811CU on certain ARM -systems, like the NanoPi NEO Core2. It also improves the RX speed of -RTL8822CU on some x86_64 systems. - -Currently none of the chips are configured to aggregate frames. - -Tested with RTL8822CU, RTL8811CU, and RTL8723DU. - -Reviewed-by: Sascha Hauer -Tested-by: Sascha Hauer -Signed-off-by: Bitterblue Smith -Signed-off-by: Ping-Ke Shih -Link: https://patch.msgid.link/f845826d-de71-492d-9a22-e48c07989a1f@gmail.com ---- - drivers/net/wireless/realtek/rtw88/usb.c | 61 ++++++++++++++++-------- - 1 file changed, 40 insertions(+), 21 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtw88/usb.c b/drivers/net/wireless/realtek/rtw88/usb.c -index 10f1d724370e..64d68366812c 100644 ---- a/drivers/net/wireless/realtek/rtw88/usb.c -+++ b/drivers/net/wireless/realtek/rtw88/usb.c -@@ -546,11 +546,12 @@ static void rtw_usb_rx_handler(struct work_struct *work) - struct rtw_usb *rtwusb = container_of(work, struct rtw_usb, rx_work); - struct rtw_dev *rtwdev = rtwusb->rtwdev; - const struct rtw_chip_info *chip = rtwdev->chip; -- struct rtw_rx_pkt_stat pkt_stat; -+ u32 pkt_desc_sz = chip->rx_pkt_desc_sz; - struct ieee80211_rx_status rx_status; -+ u32 pkt_offset, next_pkt, urb_len; -+ struct rtw_rx_pkt_stat pkt_stat; -+ struct sk_buff *next_skb; - struct sk_buff *skb; -- u32 pkt_desc_sz = chip->rx_pkt_desc_sz; -- u32 pkt_offset; - u8 *rx_desc; - int limit; - -@@ -559,31 +560,48 @@ static void rtw_usb_rx_handler(struct work_struct *work) - if (!skb) - break; - -- rx_desc = skb->data; -- chip->ops->query_rx_desc(rtwdev, rx_desc, &pkt_stat, -- &rx_status); -- pkt_offset = pkt_desc_sz + pkt_stat.drv_info_sz + -- pkt_stat.shift; -- -- if (pkt_stat.is_c2h) { -- skb_put(skb, pkt_stat.pkt_len + pkt_offset); -- rtw_fw_c2h_cmd_rx_irqsafe(rtwdev, pkt_offset, skb); -- continue; -- } -- - if (skb_queue_len(&rtwusb->rx_queue) >= RTW_USB_MAX_RXQ_LEN) { - dev_dbg_ratelimited(rtwdev->dev, "failed to get rx_queue, overflow\n"); - dev_kfree_skb_any(skb); - continue; - } - -- skb_put(skb, pkt_stat.pkt_len); -- skb_reserve(skb, pkt_offset); -+ urb_len = skb->len; -+ -+ do { -+ rx_desc = skb->data; -+ chip->ops->query_rx_desc(rtwdev, rx_desc, &pkt_stat, -+ &rx_status); -+ pkt_offset = pkt_desc_sz + pkt_stat.drv_info_sz + -+ pkt_stat.shift; -+ -+ next_pkt = round_up(pkt_stat.pkt_len + pkt_offset, 8); -+ -+ if (urb_len >= next_pkt + pkt_desc_sz) -+ next_skb = skb_clone(skb, GFP_KERNEL); -+ else -+ next_skb = NULL; -+ -+ if (pkt_stat.is_c2h) { -+ skb_trim(skb, pkt_stat.pkt_len + pkt_offset); -+ rtw_fw_c2h_cmd_rx_irqsafe(rtwdev, pkt_offset, skb); -+ } else { -+ skb_pull(skb, pkt_offset); -+ skb_trim(skb, pkt_stat.pkt_len); -+ rtw_update_rx_freq_for_invalid(rtwdev, skb, -+ &rx_status, -+ &pkt_stat); -+ rtw_rx_stats(rtwdev, pkt_stat.vif, skb); -+ memcpy(skb->cb, &rx_status, sizeof(rx_status)); -+ ieee80211_rx_irqsafe(rtwdev->hw, skb); -+ } -+ -+ skb = next_skb; -+ if (skb) -+ skb_pull(skb, next_pkt); - -- rtw_update_rx_freq_for_invalid(rtwdev, skb, &rx_status, &pkt_stat); -- rtw_rx_stats(rtwdev, pkt_stat.vif, skb); -- memcpy(skb->cb, &rx_status, sizeof(rx_status)); -- ieee80211_rx_irqsafe(rtwdev->hw, skb); -+ urb_len -= next_pkt; -+ } while (skb); - } - } - -@@ -627,6 +645,7 @@ static void rtw_usb_read_port_complete(struct urb *urb) - if (skb) - dev_kfree_skb_any(skb); - } else { -+ skb_put(skb, urb->actual_length); - skb_queue_tail(&rtwusb->rx_queue, skb); - queue_work(rtwusb->rxwq, &rtwusb->rx_work); - } --- -2.43.0 - diff --git a/packages/linux/patches/rtlwifi/6.12/0007-6.12-wifi-rtw88-Enable-USB-RX-aggregation-for-8822c-8822b.patch b/packages/linux/patches/rtlwifi/6.12/0007-6.12-wifi-rtw88-Enable-USB-RX-aggregation-for-8822c-8822b.patch deleted file mode 100644 index 12757ddbdb..0000000000 --- a/packages/linux/patches/rtlwifi/6.12/0007-6.12-wifi-rtw88-Enable-USB-RX-aggregation-for-8822c-8822b.patch +++ /dev/null @@ -1,182 +0,0 @@ -From 3e36db62ff52667d63497da45b6cae4cd8382721 Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Thu, 8 Aug 2024 01:23:06 +0300 -Subject: [PATCH 7/7] wifi: rtw88: Enable USB RX aggregation for - 8822c/8822b/8821c - -Enable USB RX aggregation when there is at least 1 Mbps RX or TX -traffic, otherwise disable it. - -USB RX aggregation improves the RX speed of RTL8811CU on certain ARM -systems, like the NanoPi NEO Core2. Before: 28 Mbps, after: 231 Mbps. - -It also improves the RX speed of RTL8822CU on some x86_64 systems. -Before: ~200 Mbps, after: ~300 Mbps. - -The official drivers for these chips use the same logic for SDIO, but -for some reason the SDIO driver in rtw88 always enables RX aggregation, -so this patch only toggles aggregation for USB devices. - -RTL8703B is likely not found in USB devices, and RTL8723DU doesn't like -aggregation. - -Tested-by: Sascha Hauer -Signed-off-by: Bitterblue Smith -Signed-off-by: Ping-Ke Shih -Link: https://patch.msgid.link/b4c0d54c-6755-4b0f-9dd7-f9196fd74b68@gmail.com ---- - drivers/net/wireless/realtek/rtw88/hci.h | 7 ++++ - drivers/net/wireless/realtek/rtw88/main.c | 13 +++++--- - drivers/net/wireless/realtek/rtw88/pci.c | 1 + - drivers/net/wireless/realtek/rtw88/sdio.c | 1 + - drivers/net/wireless/realtek/rtw88/usb.c | 40 +++++++++++++++++++++++ - 5 files changed, 58 insertions(+), 4 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtw88/hci.h b/drivers/net/wireless/realtek/rtw88/hci.h -index 830d7532f2a3..96aeda26014e 100644 ---- a/drivers/net/wireless/realtek/rtw88/hci.h -+++ b/drivers/net/wireless/realtek/rtw88/hci.h -@@ -18,6 +18,7 @@ struct rtw_hci_ops { - void (*deep_ps)(struct rtw_dev *rtwdev, bool enter); - void (*link_ps)(struct rtw_dev *rtwdev, bool enter); - void (*interface_cfg)(struct rtw_dev *rtwdev); -+ void (*dynamic_rx_agg)(struct rtw_dev *rtwdev, bool enable); - - int (*write_data_rsvd_page)(struct rtw_dev *rtwdev, u8 *buf, u32 size); - int (*write_data_h2c)(struct rtw_dev *rtwdev, u8 *buf, u32 size); -@@ -72,6 +73,12 @@ static inline void rtw_hci_interface_cfg(struct rtw_dev *rtwdev) - rtwdev->hci.ops->interface_cfg(rtwdev); - } - -+static inline void rtw_hci_dynamic_rx_agg(struct rtw_dev *rtwdev, bool enable) -+{ -+ if (rtwdev->hci.ops->dynamic_rx_agg) -+ rtwdev->hci.ops->dynamic_rx_agg(rtwdev, enable); -+} -+ - static inline int - rtw_hci_write_data_rsvd_page(struct rtw_dev *rtwdev, u8 *buf, u32 size) - { -diff --git a/drivers/net/wireless/realtek/rtw88/main.c b/drivers/net/wireless/realtek/rtw88/main.c -index 7ab7a988b123..22b39b3acc6c 100644 ---- a/drivers/net/wireless/realtek/rtw88/main.c -+++ b/drivers/net/wireless/realtek/rtw88/main.c -@@ -212,6 +212,7 @@ static void rtw_watch_dog_work(struct work_struct *work) - struct rtw_traffic_stats *stats = &rtwdev->stats; - struct rtw_watch_dog_iter_data data = {}; - bool busy_traffic = test_bit(RTW_FLAG_BUSY_TRAFFIC, rtwdev->flags); -+ u32 tx_unicast_mbps, rx_unicast_mbps; - bool ps_active; - - mutex_lock(&rtwdev->mutex); -@@ -236,10 +237,11 @@ static void rtw_watch_dog_work(struct work_struct *work) - else - ps_active = false; - -- ewma_tp_add(&stats->tx_ewma_tp, -- (u32)(stats->tx_unicast >> RTW_TP_SHIFT)); -- ewma_tp_add(&stats->rx_ewma_tp, -- (u32)(stats->rx_unicast >> RTW_TP_SHIFT)); -+ tx_unicast_mbps = stats->tx_unicast >> RTW_TP_SHIFT; -+ rx_unicast_mbps = stats->rx_unicast >> RTW_TP_SHIFT; -+ -+ ewma_tp_add(&stats->tx_ewma_tp, tx_unicast_mbps); -+ ewma_tp_add(&stats->rx_ewma_tp, rx_unicast_mbps); - stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); - stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); - -@@ -259,6 +261,9 @@ static void rtw_watch_dog_work(struct work_struct *work) - - rtw_phy_dynamic_mechanism(rtwdev); - -+ rtw_hci_dynamic_rx_agg(rtwdev, -+ tx_unicast_mbps >= 1 || rx_unicast_mbps >= 1); -+ - data.rtwdev = rtwdev; - /* rtw_iterate_vifs internally uses an atomic iterator which is needed - * to avoid taking local->iflist_mtx mutex -diff --git a/drivers/net/wireless/realtek/rtw88/pci.c b/drivers/net/wireless/realtek/rtw88/pci.c -index 5d0580da13fb..0b9b8807af2c 100644 ---- a/drivers/net/wireless/realtek/rtw88/pci.c -+++ b/drivers/net/wireless/realtek/rtw88/pci.c -@@ -1601,6 +1601,7 @@ static struct rtw_hci_ops rtw_pci_ops = { - .deep_ps = rtw_pci_deep_ps, - .link_ps = rtw_pci_link_ps, - .interface_cfg = rtw_pci_interface_cfg, -+ .dynamic_rx_agg = NULL, - - .read8 = rtw_pci_read8, - .read16 = rtw_pci_read16, -diff --git a/drivers/net/wireless/realtek/rtw88/sdio.c b/drivers/net/wireless/realtek/rtw88/sdio.c -index 763aa8212a4b..21d0754dd7f6 100644 ---- a/drivers/net/wireless/realtek/rtw88/sdio.c -+++ b/drivers/net/wireless/realtek/rtw88/sdio.c -@@ -1157,6 +1157,7 @@ static struct rtw_hci_ops rtw_sdio_ops = { - .deep_ps = rtw_sdio_deep_ps, - .link_ps = rtw_sdio_link_ps, - .interface_cfg = rtw_sdio_interface_cfg, -+ .dynamic_rx_agg = NULL, - - .read8 = rtw_sdio_read8, - .read16 = rtw_sdio_read16, -diff --git a/drivers/net/wireless/realtek/rtw88/usb.c b/drivers/net/wireless/realtek/rtw88/usb.c -index 64d68366812c..e83ab6fb83f5 100644 ---- a/drivers/net/wireless/realtek/rtw88/usb.c -+++ b/drivers/net/wireless/realtek/rtw88/usb.c -@@ -766,6 +766,45 @@ static void rtw_usb_interface_cfg(struct rtw_dev *rtwdev) - rtw_usb_init_burst_pkt_len(rtwdev); - } - -+static void rtw_usb_dynamic_rx_agg_v1(struct rtw_dev *rtwdev, bool enable) -+{ -+ u8 size, timeout; -+ u16 val16; -+ -+ rtw_write32_set(rtwdev, REG_RXDMA_AGG_PG_TH, BIT_EN_PRE_CALC); -+ rtw_write8_set(rtwdev, REG_TXDMA_PQ_MAP, BIT_RXDMA_AGG_EN); -+ rtw_write8_clr(rtwdev, REG_RXDMA_AGG_PG_TH + 3, BIT(7)); -+ -+ if (enable) { -+ size = 0x5; -+ timeout = 0x20; -+ } else { -+ size = 0x0; -+ timeout = 0x1; -+ } -+ val16 = u16_encode_bits(size, BIT_RXDMA_AGG_PG_TH) | -+ u16_encode_bits(timeout, BIT_DMA_AGG_TO_V1); -+ -+ rtw_write16(rtwdev, REG_RXDMA_AGG_PG_TH, val16); -+} -+ -+static void rtw_usb_dynamic_rx_agg(struct rtw_dev *rtwdev, bool enable) -+{ -+ switch (rtwdev->chip->id) { -+ case RTW_CHIP_TYPE_8822C: -+ case RTW_CHIP_TYPE_8822B: -+ case RTW_CHIP_TYPE_8821C: -+ rtw_usb_dynamic_rx_agg_v1(rtwdev, enable); -+ break; -+ case RTW_CHIP_TYPE_8723D: -+ /* Doesn't like aggregation. */ -+ break; -+ case RTW_CHIP_TYPE_8703B: -+ /* Likely not found in USB devices. */ -+ break; -+ } -+} -+ - static struct rtw_hci_ops rtw_usb_ops = { - .tx_write = rtw_usb_tx_write, - .tx_kick_off = rtw_usb_tx_kick_off, -@@ -775,6 +814,7 @@ static struct rtw_hci_ops rtw_usb_ops = { - .deep_ps = rtw_usb_deep_ps, - .link_ps = rtw_usb_link_ps, - .interface_cfg = rtw_usb_interface_cfg, -+ .dynamic_rx_agg = rtw_usb_dynamic_rx_agg, - - .write8 = rtw_usb_write8, - .write16 = rtw_usb_write16, --- -2.43.0 - diff --git a/packages/linux/patches/rtlwifi/6.9/0001-wifi-rtlwifi-cleanup-few-rtlxxxx_set_hw_reg-routines.patch b/packages/linux/patches/rtlwifi/6.9/0001-wifi-rtlwifi-cleanup-few-rtlxxxx_set_hw_reg-routines.patch deleted file mode 100644 index b445f0299b..0000000000 --- a/packages/linux/patches/rtlwifi/6.9/0001-wifi-rtlwifi-cleanup-few-rtlxxxx_set_hw_reg-routines.patch +++ /dev/null @@ -1,142 +0,0 @@ -From 624934a7cfabca7dea2b2c1d10b029c1ff4c1f3f Mon Sep 17 00:00:00 2001 -From: Dmitry Antipov -Date: Mon, 25 Sep 2023 12:04:48 +0300 -Subject: [PATCH 1/7] wifi: rtlwifi: cleanup few rtlxxxx_set_hw_reg() routines - -Since 'u8' comparison against zero is always false, drop the -corresponding branches of AMPDU_MIN_SPACE adjustment within -'rtlxxxx_set_hw_reg()' for rtl8188ee, rtl8192ce, rtl8192de, -rtl8723ae, rtl8723be, and rtl8821ae. Compile tested only. - -Found by Linux Verification Center (linuxtesting.org) with SVACE. - -Signed-off-by: Dmitry Antipov -Acked-by: Ping-Ke Shih -Signed-off-by: Kalle Valo -Link: https://lore.kernel.org/r/20230925090452.25633-1-dmantipov@yandex.ru ---- - drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c | 5 ----- - drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c | 5 ----- - drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c | 4 ---- - drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c | 5 ----- - drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c | 6 ------ - drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c | 5 ----- - 6 files changed, 30 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c -index 58b1a46066b5..27f6c35ba0f9 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c -@@ -433,14 +433,9 @@ void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) - break; - case HW_VAR_AMPDU_MIN_SPACE:{ - u8 min_spacing_to_set; -- u8 sec_min_space; - - min_spacing_to_set = *val; - if (min_spacing_to_set <= 7) { -- sec_min_space = 0; -- -- if (min_spacing_to_set < sec_min_space) -- min_spacing_to_set = sec_min_space; - - mac->min_space_cfg = ((mac->min_space_cfg & - 0xf8) | -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c -index 049c4fe9eeed..0bc915723b93 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/hw.c -@@ -208,14 +208,9 @@ void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) - } - case HW_VAR_AMPDU_MIN_SPACE:{ - u8 min_spacing_to_set; -- u8 sec_min_space; - - min_spacing_to_set = *val; - if (min_spacing_to_set <= 7) { -- sec_min_space = 0; -- -- if (min_spacing_to_set < sec_min_space) -- min_spacing_to_set = sec_min_space; - - mac->min_space_cfg = ((mac->min_space_cfg & - 0xf8) | -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c -index 31a18bbface9..743ac6871bf4 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c -@@ -225,13 +225,9 @@ void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) - } - case HW_VAR_AMPDU_MIN_SPACE: { - u8 min_spacing_to_set; -- u8 sec_min_space; - - min_spacing_to_set = *val; - if (min_spacing_to_set <= 7) { -- sec_min_space = 0; -- if (min_spacing_to_set < sec_min_space) -- min_spacing_to_set = sec_min_space; - mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) | - min_spacing_to_set); - *val = min_spacing_to_set; -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c -index d26d4c4314a3..6991713a66d0 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/hw.c -@@ -212,14 +212,9 @@ void rtl8723e_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) - } - case HW_VAR_AMPDU_MIN_SPACE:{ - u8 min_spacing_to_set; -- u8 sec_min_space; - - min_spacing_to_set = *((u8 *)val); - if (min_spacing_to_set <= 7) { -- sec_min_space = 0; -- -- if (min_spacing_to_set < sec_min_space) -- min_spacing_to_set = sec_min_space; - - mac->min_space_cfg = ((mac->min_space_cfg & - 0xf8) | -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c -index 15575644551f..0e77de1baaf8 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c -@@ -468,15 +468,9 @@ void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) - break; - case HW_VAR_AMPDU_MIN_SPACE:{ - u8 min_spacing_to_set; -- u8 sec_min_space; - - min_spacing_to_set = *((u8 *)val); - if (min_spacing_to_set <= 7) { -- sec_min_space = 0; -- -- if (min_spacing_to_set < sec_min_space) -- min_spacing_to_set = sec_min_space; -- - mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) | - min_spacing_to_set); - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c -index 3f8f6da33b12..1633328bc3d1 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/hw.c -@@ -546,14 +546,9 @@ void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val) - break; - case HW_VAR_AMPDU_MIN_SPACE:{ - u8 min_spacing_to_set; -- u8 sec_min_space; - - min_spacing_to_set = *((u8 *)val); - if (min_spacing_to_set <= 7) { -- sec_min_space = 0; -- -- if (min_spacing_to_set < sec_min_space) -- min_spacing_to_set = sec_min_space; - - mac->min_space_cfg = ((mac->min_space_cfg & - 0xf8) | --- -2.43.0 - diff --git a/packages/linux/patches/rtlwifi/6.9/0002-wifi-rtlwifi-remove-unreachable-code-in-rtl92d_dm_ch.patch b/packages/linux/patches/rtlwifi/6.9/0002-wifi-rtlwifi-remove-unreachable-code-in-rtl92d_dm_ch.patch deleted file mode 100644 index c552f1ff58..0000000000 --- a/packages/linux/patches/rtlwifi/6.9/0002-wifi-rtlwifi-remove-unreachable-code-in-rtl92d_dm_ch.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 583494febbdd6a76b6c2a3fad704082f4f9f4d75 Mon Sep 17 00:00:00 2001 -From: Dmitry Antipov -Date: Tue, 3 Oct 2023 07:33:16 +0300 -Subject: [PATCH 2/7] wifi: rtlwifi: remove unreachable code in - rtl92d_dm_check_edca_turbo() - -Since '!(0x5ea42b & 0xffff0000)' is always false, remove unreachable -block in 'rtl92d_dm_check_edca_turbo()' and convert EDCA limits to -constant variables. Compile tested only. - -Found by Linux Verification Center (linuxtesting.org) with SVACE. - -Signed-off-by: Dmitry Antipov -Acked-by: Ping-Ke Shih -Signed-off-by: Kalle Valo -Link: https://lore.kernel.org/r/20231003043318.11370-1-dmantipov@yandex.ru ---- - .../wireless/realtek/rtlwifi/rtl8192de/dm.c | 18 ++---------------- - 1 file changed, 2 insertions(+), 16 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c -index 6cc9c7649eda..cf4aca83bd05 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c -@@ -592,32 +592,18 @@ static void rtl92d_dm_check_edca_turbo(struct ieee80211_hw *hw) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); -+ const u32 edca_be_ul = 0x5ea42b; -+ const u32 edca_be_dl = 0x5ea42b; - static u64 last_txok_cnt; - static u64 last_rxok_cnt; - u64 cur_txok_cnt; - u64 cur_rxok_cnt; -- u32 edca_be_ul = 0x5ea42b; -- u32 edca_be_dl = 0x5ea42b; - - if (mac->link_state != MAC80211_LINKED) { - rtlpriv->dm.current_turbo_edca = false; - goto exit; - } - -- /* Enable BEQ TxOP limit configuration in wireless G-mode. */ -- /* To check whether we shall force turn on TXOP configuration. */ -- if ((!rtlpriv->dm.disable_framebursting) && -- (rtlpriv->sec.pairwise_enc_algorithm == WEP40_ENCRYPTION || -- rtlpriv->sec.pairwise_enc_algorithm == WEP104_ENCRYPTION || -- rtlpriv->sec.pairwise_enc_algorithm == TKIP_ENCRYPTION)) { -- /* Force TxOP limit to 0x005e for UL. */ -- if (!(edca_be_ul & 0xffff0000)) -- edca_be_ul |= 0x005e0000; -- /* Force TxOP limit to 0x005e for DL. */ -- if (!(edca_be_dl & 0xffff0000)) -- edca_be_dl |= 0x005e0000; -- } -- - if ((!rtlpriv->dm.is_any_nonbepkts) && - (!rtlpriv->dm.disable_framebursting)) { - cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt; --- -2.43.0 - diff --git a/packages/linux/patches/rtlwifi/6.9/0003-wifi-rtlwifi-simplify-TX-command-fill-callbacks.patch b/packages/linux/patches/rtlwifi/6.9/0003-wifi-rtlwifi-simplify-TX-command-fill-callbacks.patch deleted file mode 100644 index 754669891b..0000000000 --- a/packages/linux/patches/rtlwifi/6.9/0003-wifi-rtlwifi-simplify-TX-command-fill-callbacks.patch +++ /dev/null @@ -1,413 +0,0 @@ -From bc77b0b9adf81b9d4b7a33de3246f75fe756fd32 Mon Sep 17 00:00:00 2001 -From: Dmitry Antipov -Date: Wed, 11 Oct 2023 18:44:37 +0300 -Subject: [PATCH 3/7] wifi: rtlwifi: simplify TX command fill callbacks - -Since 'rtlpriv->cfg->ops->fill_tx_cmddesc()' is always called -with 'firstseg' and 'lastseg' set to 1 (and the latter is -never actually used), all of the relevant chip-specific -routines may be simplified. Compile tested only. - -Signed-off-by: Dmitry Antipov -Acked-by: Ping-Ke Shih -Signed-off-by: Kalle Valo -Link: https://lore.kernel.org/r/20231011154442.52457-2-dmantipov@yandex.ru ---- - drivers/net/wireless/realtek/rtlwifi/core.c | 2 +- - drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c | 8 +++----- - drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h | 1 - - drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c | 9 +++------ - drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h | 1 - - drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c | 2 +- - drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c | 8 +++----- - drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h | 5 ++--- - drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c | 2 +- - drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c | 8 +++----- - drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h | 1 - - drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.c | 8 +++----- - drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h | 1 - - drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.c | 2 +- - drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.c | 2 +- - drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.h | 4 ++-- - drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c | 8 +++----- - drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h | 1 - - drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.c | 1 - - drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h | 1 - - drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.c | 5 ++--- - drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h | 1 - - drivers/net/wireless/realtek/rtlwifi/wifi.h | 1 - - 23 files changed, 29 insertions(+), 53 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtlwifi/core.c b/drivers/net/wireless/realtek/rtlwifi/core.c -index 3835b639d453..cc9b2a459386 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/core.c -+++ b/drivers/net/wireless/realtek/rtlwifi/core.c -@@ -1897,7 +1897,7 @@ bool rtl_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb) - /*this is wrong, fill_tx_cmddesc needs update*/ - pdesc = &ring->desc[0]; - -- rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb); -+ rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, skb); - - __skb_queue_tail(&ring->queue, skb); - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c -index 65ebe52883d3..d094163a9a71 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.c -@@ -665,9 +665,8 @@ void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw, - rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, "\n"); - } - --void rtl88ee_tx_fill_cmddesc(struct ieee80211_hw *hw, -- u8 *pdesc8, bool firstseg, -- bool lastseg, struct sk_buff *skb) -+void rtl88ee_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc8, -+ struct sk_buff *skb) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); -@@ -687,8 +686,7 @@ void rtl88ee_tx_fill_cmddesc(struct ieee80211_hw *hw, - } - clear_pci_tx_desc_content(pdesc, TX_DESC_SIZE); - -- if (firstseg) -- set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN); -+ set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN); - - set_tx_desc_tx_rate(pdesc, DESC92C_RATE1M); - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h -index e17f70b4d199..aae654b0e3ba 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/trx.h -@@ -797,6 +797,5 @@ bool rtl88ee_is_tx_desc_closed(struct ieee80211_hw *hw, - u8 hw_queue, u16 index); - void rtl88ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue); - void rtl88ee_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, -- bool firstseg, bool lastseg, - struct sk_buff *skb); - #endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c -index 5376bb34251f..50e139186a93 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.c -@@ -518,9 +518,8 @@ void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw, - rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, "\n"); - } - --void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw, -- u8 *pdesc8, bool firstseg, -- bool lastseg, struct sk_buff *skb) -+void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc8, -+ struct sk_buff *skb) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); -@@ -540,9 +539,7 @@ void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw, - } - clear_pci_tx_desc_content(pdesc, TX_DESC_SIZE); - -- if (firstseg) -- set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN); -- -+ set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN); - set_tx_desc_tx_rate(pdesc, DESC_RATE1M); - - set_tx_desc_seq(pdesc, 0); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h -index b45b05a6a523..f3ffe3d9883c 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/trx.h -@@ -527,6 +527,5 @@ bool rtl92ce_is_tx_desc_closed(struct ieee80211_hw *hw, - u8 hw_queue, u16 index); - void rtl92ce_tx_polling(struct ieee80211_hw *hw, u8 hw_queue); - void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, -- bool b_firstseg, bool b_lastseg, - struct sk_buff *skb); - #endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c -index a040c07791d1..5ec0eb8773a5 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c -@@ -1539,7 +1539,7 @@ static bool usb_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb) - * if its "here". - * - * This is maybe necessary: -- * rtlpriv->cfg->ops->fill_tx_cmddesc(hw, buffer, 1, 1, skb); -+ * rtlpriv->cfg->ops->fill_tx_cmddesc(hw, buffer, skb); - */ - dev_kfree_skb(skb); - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c -index b70767e72f3d..9969e9d1fc4b 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c -@@ -626,9 +626,8 @@ void rtl92cu_fill_fake_txdesc(struct ieee80211_hw *hw, u8 *pdesc8, - _rtl_tx_desc_checksum(pdesc); - } - --void rtl92cu_tx_fill_cmddesc(struct ieee80211_hw *hw, -- u8 *pdesc8, bool firstseg, -- bool lastseg, struct sk_buff *skb) -+void rtl92cu_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc8, -+ struct sk_buff *skb) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - u8 fw_queue = QSLT_BEACON; -@@ -637,8 +636,7 @@ void rtl92cu_tx_fill_cmddesc(struct ieee80211_hw *hw, - __le32 *pdesc = (__le32 *)pdesc8; - - memset((void *)pdesc, 0, RTL_TX_HEADER_SIZE); -- if (firstseg) -- set_tx_desc_offset(pdesc, RTL_TX_HEADER_SIZE); -+ set_tx_desc_offset(pdesc, RTL_TX_HEADER_SIZE); - set_tx_desc_tx_rate(pdesc, DESC_RATE1M); - set_tx_desc_seq(pdesc, 0); - set_tx_desc_linip(pdesc, 0); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h -index 171fe39dfb0c..cc4ef2bfd2e7 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h -@@ -396,8 +396,7 @@ void rtl92cu_tx_fill_desc(struct ieee80211_hw *hw, - struct rtl_tcb_desc *tcb_desc); - void rtl92cu_fill_fake_txdesc(struct ieee80211_hw *hw, u8 *pdesc, - u32 buffer_len, bool ispspoll); --void rtl92cu_tx_fill_cmddesc(struct ieee80211_hw *hw, -- u8 *pdesc, bool b_firstseg, -- bool b_lastseg, struct sk_buff *skb); -+void rtl92cu_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, -+ struct sk_buff *skb); - - #endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c -index 9ddb8478784b..e1fb29962801 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/fw.c -@@ -469,7 +469,7 @@ static bool _rtl92d_cmd_send_packet(struct ieee80211_hw *hw, - pdesc = &ring->desc[idx]; - /* discard output from call below */ - rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN); -- rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb); -+ rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, skb); - __skb_queue_tail(&ring->queue, skb); - spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); - rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c -index c09c0c312665..02ac69c08ed3 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c -@@ -655,9 +655,8 @@ void rtl92de_tx_fill_desc(struct ieee80211_hw *hw, - rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, "\n"); - } - --void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, -- u8 *pdesc8, bool firstseg, -- bool lastseg, struct sk_buff *skb) -+void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc8, -+ struct sk_buff *skb) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); -@@ -678,8 +677,7 @@ void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, - return; - } - clear_pci_tx_desc_content(pdesc, TX_DESC_SIZE); -- if (firstseg) -- set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN); -+ set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN); - /* 5G have no CCK rate - * Caution: The macros below are multi-line expansions. - * The braces are needed no matter what checkpatch says -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h -index d01578875cd5..2992668c156c 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.h -@@ -564,7 +564,6 @@ bool rtl92de_is_tx_desc_closed(struct ieee80211_hw *hw, - u8 hw_queue, u16 index); - void rtl92de_tx_polling(struct ieee80211_hw *hw, u8 hw_queue); - void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, -- bool b_firstseg, bool b_lastseg, - struct sk_buff *skb); - - #endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.c -index a182cdeb58e2..67388e0b3fa0 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.c -@@ -827,9 +827,8 @@ void rtl92ee_tx_fill_desc(struct ieee80211_hw *hw, - rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, "\n"); - } - --void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw, -- u8 *pdesc8, bool firstseg, -- bool lastseg, struct sk_buff *skb) -+void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc8, -+ struct sk_buff *skb) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); -@@ -846,8 +845,7 @@ void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw, - } - clear_pci_tx_desc_content(pdesc, txdesc_len); - -- if (firstseg) -- set_tx_desc_offset(pdesc, txdesc_len); -+ set_tx_desc_offset(pdesc, txdesc_len); - - set_tx_desc_tx_rate(pdesc, DESC_RATE1M); - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h -index 967cef3a9cbf..3852a50a688b 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/trx.h -@@ -743,6 +743,5 @@ u64 rtl92ee_get_desc(struct ieee80211_hw *hw, - bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index); - void rtl92ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue); - void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, -- bool firstseg, bool lastseg, - struct sk_buff *skb); - #endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.c -index f570495af044..579b1789d6d1 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/fw.c -@@ -122,7 +122,7 @@ static bool _rtl92s_cmd_send_packet(struct ieee80211_hw *hw, - - idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries; - pdesc = &ring->desc[idx]; -- rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb); -+ rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, skb); - __skb_queue_tail(&ring->queue, skb); - - spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.c -index a5853a170b58..f104cdb649f8 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.c -@@ -492,7 +492,7 @@ void rtl92se_tx_fill_desc(struct ieee80211_hw *hw, - } - - void rtl92se_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc8, -- bool firstseg, bool lastseg, struct sk_buff *skb) -+ struct sk_buff *skb) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.h -index 90aa12fc6a7f..40291a6a15d0 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/trx.h -@@ -10,8 +10,8 @@ void rtl92se_tx_fill_desc(struct ieee80211_hw *hw, - struct ieee80211_sta *sta, - struct sk_buff *skb, u8 hw_queue, - struct rtl_tcb_desc *ptcb_desc); --void rtl92se_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, bool firstseg, -- bool lastseg, struct sk_buff *skb); -+void rtl92se_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, -+ struct sk_buff *skb); - bool rtl92se_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *stats, - struct ieee80211_rx_status *rx_status, u8 *pdesc, - struct sk_buff *skb); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c -index 7f294e698994..d9823ddab7be 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.c -@@ -519,9 +519,8 @@ void rtl8723e_tx_fill_desc(struct ieee80211_hw *hw, - rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, "\n"); - } - --void rtl8723e_tx_fill_cmddesc(struct ieee80211_hw *hw, -- u8 *pdesc8, bool firstseg, -- bool lastseg, struct sk_buff *skb) -+void rtl8723e_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc8, -+ struct sk_buff *skb) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); -@@ -541,8 +540,7 @@ void rtl8723e_tx_fill_cmddesc(struct ieee80211_hw *hw, - } - clear_pci_tx_desc_content(pdesc, TX_DESC_SIZE); - -- if (firstseg) -- set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN); -+ set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN); - - set_tx_desc_tx_rate(pdesc, DESC92C_RATE1M); - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h -index 2d25f62a4d52..f352fddfff32 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/trx.h -@@ -530,6 +530,5 @@ bool rtl8723e_is_tx_desc_closed(struct ieee80211_hw *hw, - u8 hw_queue, u16 index); - void rtl8723e_tx_polling(struct ieee80211_hw *hw, u8 hw_queue); - void rtl8723e_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, -- bool firstseg, bool lastseg, - struct sk_buff *skb); - #endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.c -index 24ef7cc52e99..8b6352f7f93b 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.c -@@ -585,7 +585,6 @@ void rtl8723be_tx_fill_desc(struct ieee80211_hw *hw, - } - - void rtl8723be_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc8, -- bool firstseg, bool lastseg, - struct sk_buff *skb) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h -index 174aca20c7e1..da027f915cf4 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/trx.h -@@ -642,6 +642,5 @@ bool rtl8723be_is_tx_desc_closed(struct ieee80211_hw *hw, - u8 hw_queue, u16 index); - void rtl8723be_tx_polling(struct ieee80211_hw *hw, u8 hw_queue); - void rtl8723be_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, -- bool firstseg, bool lastseg, - struct sk_buff *skb); - #endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.c -index d7cb3319d885..bd71592fe26a 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.c -@@ -828,9 +828,8 @@ void rtl8821ae_tx_fill_desc(struct ieee80211_hw *hw, - rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, "\n"); - } - --void rtl8821ae_tx_fill_cmddesc(struct ieee80211_hw *hw, -- u8 *pdesc8, bool firstseg, -- bool lastseg, struct sk_buff *skb) -+void rtl8821ae_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc8, -+ struct sk_buff *skb) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h -index a9ed6fd41089..1155365348f3 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/trx.h -@@ -648,6 +648,5 @@ bool rtl8821ae_is_tx_desc_closed(struct ieee80211_hw *hw, - u8 hw_queue, u16 index); - void rtl8821ae_tx_polling(struct ieee80211_hw *hw, u8 hw_queue); - void rtl8821ae_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, -- bool firstseg, bool lastseg, - struct sk_buff *skb); - #endif -diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h -index 2e7e04f91279..600b33905cab 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/wifi.h -+++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h -@@ -2249,7 +2249,6 @@ struct rtl_hal_ops { - void (*fill_fake_txdesc)(struct ieee80211_hw *hw, u8 *pdesc, - u32 buffer_len, bool bsspspoll); - void (*fill_tx_cmddesc)(struct ieee80211_hw *hw, u8 *pdesc, -- bool firstseg, bool lastseg, - struct sk_buff *skb); - void (*fill_tx_special_desc)(struct ieee80211_hw *hw, - u8 *pdesc, u8 *pbd_desc, --- -2.43.0 - diff --git a/packages/linux/patches/rtlwifi/6.9/0004-wifi-rtlwifi-drop-unused-const_amdpci_aspm.patch b/packages/linux/patches/rtlwifi/6.9/0004-wifi-rtlwifi-drop-unused-const_amdpci_aspm.patch deleted file mode 100644 index 5955a05317..0000000000 --- a/packages/linux/patches/rtlwifi/6.9/0004-wifi-rtlwifi-drop-unused-const_amdpci_aspm.patch +++ /dev/null @@ -1,182 +0,0 @@ -From 1705e79a096e605b9f9da5442024f05c5e240694 Mon Sep 17 00:00:00 2001 -From: Bjorn Helgaas -Date: Thu, 16 Nov 2023 12:05:29 -0600 -Subject: [PATCH 4/7] wifi: rtlwifi: drop unused const_amdpci_aspm -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Remove the unused "const_amdpci_aspm" member of struct rtl_pci and -struct rtl_ps_ctl. - -Signed-off-by: Bjorn Helgaas -Acked-by: Ping-Ke Shih -Reviewed-by: Ilpo Järvinen -Signed-off-by: Kalle Valo -Link: https://lore.kernel.org/r/20231116180529.52752-1-helgaas@kernel.org ---- - drivers/net/wireless/realtek/rtlwifi/pci.c | 1 - - drivers/net/wireless/realtek/rtlwifi/pci.h | 1 - - drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c | 3 --- - drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c | 3 --- - drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c | 3 --- - drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.c | 3 --- - drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c | 3 --- - drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.c | 3 --- - drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c | 3 --- - drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.c | 3 --- - drivers/net/wireless/realtek/rtlwifi/wifi.h | 2 -- - 11 files changed, 28 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtlwifi/pci.c b/drivers/net/wireless/realtek/rtlwifi/pci.c -index 9886e719739b..b163a069660b 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/pci.c -+++ b/drivers/net/wireless/realtek/rtlwifi/pci.c -@@ -70,7 +70,6 @@ static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) - ppsc->support_aspm = false; - - /*Update PCI ASPM setting */ -- ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm; - switch (rtlpci->const_pci_aspm) { - case 0: - /*No ASPM */ -diff --git a/drivers/net/wireless/realtek/rtlwifi/pci.h b/drivers/net/wireless/realtek/rtlwifi/pci.h -index 866861626a0a..4725d43609fd 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/pci.h -+++ b/drivers/net/wireless/realtek/rtlwifi/pci.h -@@ -195,7 +195,6 @@ struct rtl_pci { - u32 reg_bcn_ctrl_val; - - /*ASPM*/ u8 const_pci_aspm; -- u8 const_amdpci_aspm; - u8 const_hwsw_rfoff_d3; - u8 const_support_pciaspm; - /*pci-e bridge */ -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c -index b77937fe2448..37bb59fa8bfa 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/sw.c -@@ -21,9 +21,6 @@ static void rtl88e_init_aspm_vars(struct ieee80211_hw *hw) - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); - -- /*close ASPM for AMD defaultly */ -- rtlpci->const_amdpci_aspm = 0; -- - /* ASPM PS mode. - * 0 - Disable ASPM, - * 1 - Enable ASPM without Clock Req, -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c -index e452275d8789..e20f2bec45c4 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/sw.c -@@ -24,9 +24,6 @@ static void rtl92c_init_aspm_vars(struct ieee80211_hw *hw) - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); - -- /*close ASPM for AMD defaultly */ -- rtlpci->const_amdpci_aspm = 0; -- - /* - * ASPM PS mode. - * 0 - Disable ASPM, -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c -index 11f319c97124..afd685ed460a 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/sw.c -@@ -21,9 +21,6 @@ static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw) - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); - -- /*close ASPM for AMD defaultly */ -- rtlpci->const_amdpci_aspm = 0; -- - /* - * ASPM PS mode. - * 0 - Disable ASPM, -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.c -index 616a47d8d97a..a5ea2b44a97c 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.c -@@ -24,9 +24,6 @@ static void rtl92ee_init_aspm_vars(struct ieee80211_hw *hw) - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); - -- /*close ASPM for AMD defaultly */ -- rtlpci->const_amdpci_aspm = 0; -- - /** - * ASPM PS mode. - * 0 - Disable ASPM, -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c -index 30bce381c3bb..675bdd32feb1 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c -@@ -21,9 +21,6 @@ static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw) - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); - -- /*close ASPM for AMD defaultly */ -- rtlpci->const_amdpci_aspm = 0; -- - /* ASPM PS mode. - * 0 - Disable ASPM, - * 1 - Enable ASPM without Clock Req, -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.c -index c821436a1991..dd7505e2f22c 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/sw.c -@@ -26,9 +26,6 @@ static void rtl8723e_init_aspm_vars(struct ieee80211_hw *hw) - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); - -- /*close ASPM for AMD defaultly */ -- rtlpci->const_amdpci_aspm = 0; -- - /** - * ASPM PS mode. - * 0 - Disable ASPM, -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c -index 43b611d5288d..162c34f0e9b7 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/sw.c -@@ -26,9 +26,6 @@ static void rtl8723be_init_aspm_vars(struct ieee80211_hw *hw) - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); - -- /*close ASPM for AMD defaultly */ -- rtlpci->const_amdpci_aspm = 0; -- - /* ASPM PS mode. - * 0 - Disable ASPM, - * 1 - Enable ASPM without Clock Req, -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.c -index 0bca542e103f..7b911695db33 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/sw.c -@@ -23,9 +23,6 @@ static void rtl8821ae_init_aspm_vars(struct ieee80211_hw *hw) - struct rtl_priv *rtlpriv = rtl_priv(hw); - struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); - -- /*close ASPM for AMD defaultly */ -- rtlpci->const_amdpci_aspm = 0; -- - /** - * ASPM PS mode. - * 0 - Disable ASPM, -diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h -index 600b33905cab..b105c713e35f 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/wifi.h -+++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h -@@ -2023,8 +2023,6 @@ struct rtl_ps_ctl { - u32 cur_ps_level; - u32 reg_rfps_level; - -- /*just for PCIE ASPM */ -- u8 const_amdpci_aspm; - bool pwrdown_mode; - - enum rf_pwrstate inactive_pwrstate; --- -2.43.0 - diff --git a/packages/linux/patches/rtlwifi/6.9/0005-wifi-rtlwifi-rtl8192de-Don-t-read-register-in-_rtl92.patch b/packages/linux/patches/rtlwifi/6.9/0005-wifi-rtlwifi-rtl8192de-Don-t-read-register-in-_rtl92.patch deleted file mode 100644 index 4ddd97b32d..0000000000 --- a/packages/linux/patches/rtlwifi/6.9/0005-wifi-rtlwifi-rtl8192de-Don-t-read-register-in-_rtl92.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 366e361d988e0d62cc2b27e1e6255651b0353f3c Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Sat, 13 Jan 2024 01:42:29 +0200 -Subject: [PATCH 5/7] wifi: rtlwifi: rtl8192de: Don't read register in - _rtl92de_query_rxphystatus - -Instead of reading bit 9 of RFPGA0_XA_HSSIPARAMETER2 every time a frame -is received, just use rtlphy->cck_high_power, which is initialised in -_rtl92d_phy_bb_config(). That bit never changes anyway. - -With this change _rtl92de_query_rxphystatus() can be shared with the -upcoming USB driver. The USB driver can't read registers in this -function because register reading can sleep. - -Compile tested only. - -Signed-off-by: Bitterblue Smith -Acked-by: Ping-Ke Shih -Signed-off-by: Kalle Valo -Link: https://msgid.link/19a3e023-0eaa-4096-9f78-a2c8e909cb54@gmail.com ---- - drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c | 5 ++--- - 1 file changed, 2 insertions(+), 3 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c -index 02ac69c08ed3..192982ec8152 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/trx.c -@@ -42,6 +42,7 @@ static void _rtl92de_query_rxphystatus(struct ieee80211_hw *hw, - bool packet_beacon) - { - struct rtl_priv *rtlpriv = rtl_priv(hw); -+ struct rtl_phy *rtlphy = &(rtlpriv->phy); - struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv); - struct phy_sts_cck_8192d *cck_buf; - s8 rx_pwr_all, rx_pwr[4]; -@@ -62,9 +63,7 @@ static void _rtl92de_query_rxphystatus(struct ieee80211_hw *hw, - u8 report, cck_highpwr; - cck_buf = (struct phy_sts_cck_8192d *)p_drvinfo; - if (ppsc->rfpwr_state == ERFON) -- cck_highpwr = (u8) rtl_get_bbreg(hw, -- RFPGA0_XA_HSSIPARAMETER2, -- BIT(9)); -+ cck_highpwr = rtlphy->cck_high_power; - else - cck_highpwr = false; - if (!cck_highpwr) { --- -2.43.0 - diff --git a/packages/linux/patches/rtlwifi/6.9/0006-wifi-rtlwifi-Remove-rtl_intf_ops.read_efuse_byte.patch b/packages/linux/patches/rtlwifi/6.9/0006-wifi-rtlwifi-Remove-rtl_intf_ops.read_efuse_byte.patch deleted file mode 100644 index dd865f08ef..0000000000 --- a/packages/linux/patches/rtlwifi/6.9/0006-wifi-rtlwifi-Remove-rtl_intf_ops.read_efuse_byte.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 5c051c716329a26d66f893e9415f22f65381a77a Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Tue, 27 Feb 2024 14:15:52 +0200 -Subject: [PATCH 6/7] wifi: rtlwifi: Remove rtl_intf_ops.read_efuse_byte - -PCI drivers and USB drivers can both use the same function, -read_efuse_byte(), and they can call it directly. - -rtl8192de was the only user. - -Tested only with the upcoming rtl8192du driver. - -Signed-off-by: Bitterblue Smith -Acked-by: Ping-Ke Shih -Signed-off-by: Kalle Valo -Link: https://msgid.link/4e2c968d-f25c-4a40-be97-4fdcbdde69cf@gmail.com ---- - drivers/net/wireless/realtek/rtlwifi/pci.c | 1 - - drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c | 6 ++---- - drivers/net/wireless/realtek/rtlwifi/wifi.h | 1 - - 3 files changed, 2 insertions(+), 6 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtlwifi/pci.c b/drivers/net/wireless/realtek/rtlwifi/pci.c -index b163a069660b..6f57bf8f404e 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/pci.c -+++ b/drivers/net/wireless/realtek/rtlwifi/pci.c -@@ -2422,7 +2422,6 @@ EXPORT_SYMBOL(rtl_pci_resume); - #endif /* CONFIG_PM_SLEEP */ - - const struct rtl_intf_ops rtl_pci_ops = { -- .read_efuse_byte = read_efuse_byte, - .adapter_start = rtl_pci_start, - .adapter_stop = rtl_pci_stop, - .check_buddy_priv = rtl_pci_check_buddy_priv, -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c -index 743ac6871bf4..4ba42f6be3f2 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/hw.c -@@ -1669,10 +1669,8 @@ static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw) - u8 cutvalue[2]; - u16 chipvalue; - -- rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H, -- &cutvalue[1]); -- rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L, -- &cutvalue[0]); -+ read_efuse_byte(hw, EEPROME_CHIP_VERSION_H, &cutvalue[1]); -+ read_efuse_byte(hw, EEPROME_CHIP_VERSION_L, &cutvalue[0]); - chipvalue = (cutvalue[1] << 8) | cutvalue[0]; - switch (chipvalue) { - case 0xAA55: -diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h -index b105c713e35f..3cd95dd4e711 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/wifi.h -+++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h -@@ -2315,7 +2315,6 @@ struct rtl_hal_ops { - - struct rtl_intf_ops { - /*com */ -- void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf); - int (*adapter_start)(struct ieee80211_hw *hw); - void (*adapter_stop)(struct ieee80211_hw *hw); - bool (*check_buddy_priv)(struct ieee80211_hw *hw, --- -2.43.0 - diff --git a/packages/linux/patches/rtlwifi/6.9/0007-wifi-rtlwifi-rtl_usb-Store-the-endpoint-addresses.patch b/packages/linux/patches/rtlwifi/6.9/0007-wifi-rtlwifi-rtl_usb-Store-the-endpoint-addresses.patch deleted file mode 100644 index 78506f47c5..0000000000 --- a/packages/linux/patches/rtlwifi/6.9/0007-wifi-rtlwifi-rtl_usb-Store-the-endpoint-addresses.patch +++ /dev/null @@ -1,259 +0,0 @@ -From 548fc9fe36544db208afb45c4ce6e85c7a548fad Mon Sep 17 00:00:00 2001 -From: Bitterblue Smith -Date: Tue, 13 Feb 2024 16:33:11 +0200 -Subject: [PATCH 7/7] wifi: rtlwifi: rtl_usb: Store the endpoint addresses - -And use the stored addresses in rtl8192cu instead of hardcoding them. - -This is what the vendor drivers do. - -Perhaps this is not strictly necessary for RTL8192CU devices. However, -the dual mac version of RTL8192DU has two USB interfaces, each with its -own set of endpoints. Hardcoding their addresses in the upcoming -rtl8192du driver would require making some assumptions which I'm not -qualified to make. - -Signed-off-by: Bitterblue Smith -Acked-by: Ping-Ke Shih -Signed-off-by: Kalle Valo -Link: https://msgid.link/7b6a602a-6101-4bab-958d-bcff4d565b40@gmail.com ---- - .../wireless/realtek/rtlwifi/rtl8192cu/sw.c | 1 - - .../wireless/realtek/rtlwifi/rtl8192cu/trx.c | 77 ++++++++++--------- - .../wireless/realtek/rtlwifi/rtl8192cu/trx.h | 1 - - drivers/net/wireless/realtek/rtlwifi/usb.c | 31 ++++++-- - drivers/net/wireless/realtek/rtlwifi/usb.h | 2 + - drivers/net/wireless/realtek/rtlwifi/wifi.h | 1 - - 6 files changed, 68 insertions(+), 45 deletions(-) - -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c -index e6403d4c937c..bf63c060c985 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/sw.c -@@ -146,7 +146,6 @@ MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)"); - - static struct rtl_hal_usbint_cfg rtl92cu_interface_cfg = { - /* rx */ -- .in_ep_num = RTL92C_USB_BULK_IN_NUM, - .rx_urb_num = RTL92C_NUM_RX_URBS, - .rx_max_size = RTL92C_SIZE_MAX_RX_BUFFER, - .usb_rx_hdl = rtl8192cu_rx_hdl, -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c -index 9969e9d1fc4b..e051295ea596 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.c -@@ -79,68 +79,75 @@ static int configvernoutep(struct ieee80211_hw *hw) - static void twooutepmapping(struct ieee80211_hw *hw, bool is_chip8, - bool bwificfg, struct rtl_ep_map *ep_map) - { -+ struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw); -+ struct rtl_usb *rtlusb = rtl_usbdev(usb_priv); - struct rtl_priv *rtlpriv = rtl_priv(hw); - - if (bwificfg) { /* for WMM */ - rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, - "USB Chip-B & WMM Setting.....\n"); -- ep_map->ep_mapping[RTL_TXQ_BE] = 2; -- ep_map->ep_mapping[RTL_TXQ_BK] = 3; -- ep_map->ep_mapping[RTL_TXQ_VI] = 3; -- ep_map->ep_mapping[RTL_TXQ_VO] = 2; -- ep_map->ep_mapping[RTL_TXQ_MGT] = 2; -- ep_map->ep_mapping[RTL_TXQ_BCN] = 2; -- ep_map->ep_mapping[RTL_TXQ_HI] = 2; -+ ep_map->ep_mapping[RTL_TXQ_BE] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_BK] = rtlusb->out_eps[1]; -+ ep_map->ep_mapping[RTL_TXQ_VI] = rtlusb->out_eps[1]; -+ ep_map->ep_mapping[RTL_TXQ_VO] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_MGT] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_BCN] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_HI] = rtlusb->out_eps[0]; - } else { /* typical setting */ - rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, - "USB typical Setting.....\n"); -- ep_map->ep_mapping[RTL_TXQ_BE] = 3; -- ep_map->ep_mapping[RTL_TXQ_BK] = 3; -- ep_map->ep_mapping[RTL_TXQ_VI] = 2; -- ep_map->ep_mapping[RTL_TXQ_VO] = 2; -- ep_map->ep_mapping[RTL_TXQ_MGT] = 2; -- ep_map->ep_mapping[RTL_TXQ_BCN] = 2; -- ep_map->ep_mapping[RTL_TXQ_HI] = 2; -+ ep_map->ep_mapping[RTL_TXQ_BE] = rtlusb->out_eps[1]; -+ ep_map->ep_mapping[RTL_TXQ_BK] = rtlusb->out_eps[1]; -+ ep_map->ep_mapping[RTL_TXQ_VI] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_VO] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_MGT] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_BCN] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_HI] = rtlusb->out_eps[0]; - } - } - - static void threeoutepmapping(struct ieee80211_hw *hw, bool bwificfg, - struct rtl_ep_map *ep_map) - { -+ struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw); -+ struct rtl_usb *rtlusb = rtl_usbdev(usb_priv); - struct rtl_priv *rtlpriv = rtl_priv(hw); - - if (bwificfg) { /* for WMM */ - rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, - "USB 3EP Setting for WMM.....\n"); -- ep_map->ep_mapping[RTL_TXQ_BE] = 5; -- ep_map->ep_mapping[RTL_TXQ_BK] = 3; -- ep_map->ep_mapping[RTL_TXQ_VI] = 3; -- ep_map->ep_mapping[RTL_TXQ_VO] = 2; -- ep_map->ep_mapping[RTL_TXQ_MGT] = 2; -- ep_map->ep_mapping[RTL_TXQ_BCN] = 2; -- ep_map->ep_mapping[RTL_TXQ_HI] = 2; -+ ep_map->ep_mapping[RTL_TXQ_BE] = rtlusb->out_eps[2]; -+ ep_map->ep_mapping[RTL_TXQ_BK] = rtlusb->out_eps[1]; -+ ep_map->ep_mapping[RTL_TXQ_VI] = rtlusb->out_eps[1]; -+ ep_map->ep_mapping[RTL_TXQ_VO] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_MGT] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_BCN] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_HI] = rtlusb->out_eps[0]; - } else { /* typical setting */ - rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, - "USB 3EP Setting for typical.....\n"); -- ep_map->ep_mapping[RTL_TXQ_BE] = 5; -- ep_map->ep_mapping[RTL_TXQ_BK] = 5; -- ep_map->ep_mapping[RTL_TXQ_VI] = 3; -- ep_map->ep_mapping[RTL_TXQ_VO] = 2; -- ep_map->ep_mapping[RTL_TXQ_MGT] = 2; -- ep_map->ep_mapping[RTL_TXQ_BCN] = 2; -- ep_map->ep_mapping[RTL_TXQ_HI] = 2; -+ ep_map->ep_mapping[RTL_TXQ_BE] = rtlusb->out_eps[2]; -+ ep_map->ep_mapping[RTL_TXQ_BK] = rtlusb->out_eps[2]; -+ ep_map->ep_mapping[RTL_TXQ_VI] = rtlusb->out_eps[1]; -+ ep_map->ep_mapping[RTL_TXQ_VO] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_MGT] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_BCN] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_HI] = rtlusb->out_eps[0]; - } - } - - static void oneoutepmapping(struct ieee80211_hw *hw, struct rtl_ep_map *ep_map) - { -- ep_map->ep_mapping[RTL_TXQ_BE] = 2; -- ep_map->ep_mapping[RTL_TXQ_BK] = 2; -- ep_map->ep_mapping[RTL_TXQ_VI] = 2; -- ep_map->ep_mapping[RTL_TXQ_VO] = 2; -- ep_map->ep_mapping[RTL_TXQ_MGT] = 2; -- ep_map->ep_mapping[RTL_TXQ_BCN] = 2; -- ep_map->ep_mapping[RTL_TXQ_HI] = 2; -+ struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw); -+ struct rtl_usb *rtlusb = rtl_usbdev(usb_priv); -+ -+ ep_map->ep_mapping[RTL_TXQ_BE] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_BK] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_VI] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_VO] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_MGT] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_BCN] = rtlusb->out_eps[0]; -+ ep_map->ep_mapping[RTL_TXQ_HI] = rtlusb->out_eps[0]; - } - - static int _out_ep_mapping(struct ieee80211_hw *hw) -diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h -index cc4ef2bfd2e7..31ec9deae7fb 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h -+++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/trx.h -@@ -4,7 +4,6 @@ - #ifndef __RTL92CU_TRX_H__ - #define __RTL92CU_TRX_H__ - --#define RTL92C_USB_BULK_IN_NUM 1 - #define RTL92C_NUM_RX_URBS 8 - #define RTL92C_NUM_TX_URBS 32 - -diff --git a/drivers/net/wireless/realtek/rtlwifi/usb.c b/drivers/net/wireless/realtek/rtlwifi/usb.c -index 30bf2775a335..706909a50790 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/usb.c -+++ b/drivers/net/wireless/realtek/rtlwifi/usb.c -@@ -280,7 +280,6 @@ static int _rtl_usb_init_rx(struct ieee80211_hw *hw) - - rtlusb->rx_max_size = rtlpriv->cfg->usb_interface_cfg->rx_max_size; - rtlusb->rx_urb_num = rtlpriv->cfg->usb_interface_cfg->rx_urb_num; -- rtlusb->in_ep = rtlpriv->cfg->usb_interface_cfg->in_ep_num; - rtlusb->usb_rx_hdl = rtlpriv->cfg->usb_interface_cfg->usb_rx_hdl; - rtlusb->usb_rx_segregate_hdl = - rtlpriv->cfg->usb_interface_cfg->usb_rx_segregate_hdl; -@@ -312,20 +311,38 @@ static int _rtl_usb_init(struct ieee80211_hw *hw) - - pep_desc = &usb_intf->cur_altsetting->endpoint[epidx].desc; - -- if (usb_endpoint_dir_in(pep_desc)) -+ if (usb_endpoint_dir_in(pep_desc)) { -+ if (usb_endpoint_xfer_bulk(pep_desc)) { -+ /* The vendor drivers assume there is only one -+ * bulk in ep and that it's the first in ep. -+ */ -+ if (rtlusb->in_ep_nums == 0) -+ rtlusb->in_ep = usb_endpoint_num(pep_desc); -+ else -+ pr_warn("%s: bulk in endpoint is not the first in endpoint\n", -+ __func__); -+ } -+ - rtlusb->in_ep_nums++; -- else if (usb_endpoint_dir_out(pep_desc)) -+ } else if (usb_endpoint_dir_out(pep_desc)) { -+ if (rtlusb->out_ep_nums < RTL_USB_MAX_BULKOUT_NUM) { -+ if (usb_endpoint_xfer_bulk(pep_desc)) -+ rtlusb->out_eps[rtlusb->out_ep_nums] = -+ usb_endpoint_num(pep_desc); -+ } else { -+ pr_warn("%s: found more bulk out endpoints than the expected %d\n", -+ __func__, RTL_USB_MAX_BULKOUT_NUM); -+ } -+ - rtlusb->out_ep_nums++; -+ } - - rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, - "USB EP(0x%02x), MaxPacketSize=%d, Interval=%d\n", - pep_desc->bEndpointAddress, pep_desc->wMaxPacketSize, - pep_desc->bInterval); - } -- if (rtlusb->in_ep_nums < rtlpriv->cfg->usb_interface_cfg->in_ep_num) { -- pr_err("Too few input end points found\n"); -- return -EINVAL; -- } -+ - if (rtlusb->out_ep_nums == 0) { - pr_err("No output end points found\n"); - return -EINVAL; -diff --git a/drivers/net/wireless/realtek/rtlwifi/usb.h b/drivers/net/wireless/realtek/rtlwifi/usb.h -index 3bf85b23eec1..12529afc0510 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/usb.h -+++ b/drivers/net/wireless/realtek/rtlwifi/usb.h -@@ -19,6 +19,7 @@ - - #define RTL_USB_MAX_TXQ_NUM 4 /* max tx queue */ - #define RTL_USB_MAX_EP_NUM 6 /* max ep number */ -+#define RTL_USB_MAX_BULKOUT_NUM 4 - #define RTL_USB_MAX_TX_URBS_NUM 8 - - enum rtl_txq { -@@ -94,6 +95,7 @@ struct rtl_usb { - - /* Tx */ - u8 out_ep_nums ; -+ u8 out_eps[RTL_USB_MAX_BULKOUT_NUM]; - u8 out_queue_sel; - struct rtl_ep_map ep_map; - -diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h -index 3cd95dd4e711..b2179fd1d709 100644 ---- a/drivers/net/wireless/realtek/rtlwifi/wifi.h -+++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h -@@ -2378,7 +2378,6 @@ struct rtl_mod_params { - - struct rtl_hal_usbint_cfg { - /* data - rx */ -- u32 in_ep_num; - u32 rx_urb_num; - u32 rx_max_size; - --- -2.43.0 - diff --git a/packages/linux/patches/rtlwifi/6.9/0008-wifi-rtw88-8821c-tweak-CCK-TX-filter-setting-for-SRRC.patch b/packages/linux/patches/rtlwifi/6.9/0008-wifi-rtw88-8821c-tweak-CCK-TX-filter-setting-for-SRRC.patch deleted file mode 100644 index 975efdd07a..0000000000 --- a/packages/linux/patches/rtlwifi/6.9/0008-wifi-rtw88-8821c-tweak-CCK-TX-filter-setting-for-SRRC.patch +++ /dev/null @@ -1,156 +0,0 @@ -From 14a5b11532e850e7a748cbb4c74ac5c5abf18211 Mon Sep 17 00:00:00 2001 -From: Zong-Zhe Yang -Date: Wed, 4 Oct 2023 16:50:51 +0800 -Subject: [PATCH] wifi: rtw88: 8821c: tweak CCK TX filter setting for SRRC - regulation - -Since new criterion released by SRRC (State Radio Regulatory Commission, -China) is stricter, we have adjusted TX power limit tables for it. But, -due to RTL8821C HW characteristic, we still need to use specific parameter -in CCK TX filter when set channel to avoid violations in some corner cases. - -Signed-off-by: Zong-Zhe Yang -Signed-off-by: Ping-Ke Shih -Signed-off-by: Kalle Valo -Link: https://lore.kernel.org/r/20231004085051.205683-6-pkshih@realtek.com ---- - drivers/net/wireless/realtek/rtw88/regd.c | 8 +++ - drivers/net/wireless/realtek/rtw88/regd.h | 2 + - drivers/net/wireless/realtek/rtw88/rtw8821c.c | 67 +++++++++++++++++++ - drivers/net/wireless/realtek/rtw88/rtw8821c.h | 1 + - 4 files changed, 78 insertions(+) - -diff --git a/drivers/net/wireless/realtek/rtw88/regd.c b/drivers/net/wireless/realtek/rtw88/regd.c -index 124fc7ae6a1476..7f3b2ea3f2a560 100644 ---- a/drivers/net/wireless/realtek/rtw88/regd.c -+++ b/drivers/net/wireless/realtek/rtw88/regd.c -@@ -502,6 +502,14 @@ u8 rtw_regd_get(struct rtw_dev *rtwdev) - } - EXPORT_SYMBOL(rtw_regd_get); - -+bool rtw_regd_srrc(struct rtw_dev *rtwdev) -+{ -+ struct rtw_regd *regd = &rtwdev->regd; -+ -+ return rtw_reg_match(regd->regulatory, "CN"); -+} -+EXPORT_SYMBOL(rtw_regd_srrc); -+ - struct rtw_regd_alternative_t { - bool set; - u8 alt; -diff --git a/drivers/net/wireless/realtek/rtw88/regd.h b/drivers/net/wireless/realtek/rtw88/regd.h -index 34cb13d0cd9ebc..3c5a6fd8e6ddd8 100644 ---- a/drivers/net/wireless/realtek/rtw88/regd.h -+++ b/drivers/net/wireless/realtek/rtw88/regd.h -@@ -68,4 +68,6 @@ int rtw_regd_init(struct rtw_dev *rtwdev); - int rtw_regd_hint(struct rtw_dev *rtwdev); - u8 rtw_regd_get(struct rtw_dev *rtwdev); - bool rtw_regd_has_alt(u8 regd, u8 *regd_alt); -+bool rtw_regd_srrc(struct rtw_dev *rtwdev); -+ - #endif -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8821c.c b/drivers/net/wireless/realtek/rtw88/rtw8821c.c -index adf224618a2a6f..429bb420b0563e 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8821c.c -+++ b/drivers/net/wireless/realtek/rtw88/rtw8821c.c -@@ -381,6 +381,65 @@ static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw) - } - } - -+static void rtw8821c_cck_tx_filter_srrc(struct rtw_dev *rtwdev, u8 channel, u8 bw) -+{ -+ struct rtw_hal *hal = &rtwdev->hal; -+ -+ if (channel == 14) { -+ rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xe82c); -+ rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); -+ rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); -+ rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); -+ -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000); -+ } else if (channel == 13 || -+ (channel == 11 && bw == RTW_CHANNEL_WIDTH_40)) { -+ rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xf8fe); -+ rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x64b80c1c); -+ rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x8810); -+ rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x01235667); -+ -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00027); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00027); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00029); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00026); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000); -+ } else { -+ rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xe82c); -+ rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, -+ hal->ch_param[0]); -+ rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, -+ hal->ch_param[1] & MASKLWORD); -+ rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, -+ hal->ch_param[2]); -+ -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); -+ rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000); -+ } -+} -+ - static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, - u8 primary_ch_idx) - { -@@ -395,6 +454,13 @@ static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, - - rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0); - rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); -+ -+ if (rtw_regd_srrc(rtwdev)) { -+ rtw8821c_cck_tx_filter_srrc(rtwdev, channel, bw); -+ goto set_bw; -+ } -+ -+ /* CCK TX filter parameters for default case */ - if (channel == 14) { - rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); - rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); -@@ -430,6 +496,7 @@ static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, - rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); - } - -+set_bw: - switch (bw) { - case RTW_CHANNEL_WIDTH_20: - default: -diff --git a/drivers/net/wireless/realtek/rtw88/rtw8821c.h b/drivers/net/wireless/realtek/rtw88/rtw8821c.h -index fcff31688c453a..91ed921407bbe7 100644 ---- a/drivers/net/wireless/realtek/rtw88/rtw8821c.h -+++ b/drivers/net/wireless/realtek/rtw88/rtw8821c.h -@@ -238,6 +238,7 @@ extern const struct rtw_chip_info rtw8821c_hw_spec; - #define REG_RXSB 0xa00 - #define REG_ADCINI 0xa04 - #define REG_PWRTH 0xa08 -+#define REG_CCA_FLTR 0xa20 - #define REG_TXSF2 0xa24 - #define REG_TXSF6 0xa28 - #define REG_FA_CCK 0xa5c diff --git a/packages/linux/patches/rtlwifi/6.9/0009-wifi-rtw88-8822ce-refine-power-parameters-for-RFE-type-5.patch b/packages/linux/patches/rtlwifi/6.9/0009-wifi-rtw88-8822ce-refine-power-parameters-for-RFE-type-5.patch deleted file mode 100644 index 32bd7cb44a..0000000000 --- a/packages/linux/patches/rtlwifi/6.9/0009-wifi-rtw88-8822ce-refine-power-parameters-for-RFE-type-5.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 8d101b15f86dae41fcf1afe448d5a52c1956c465 Mon Sep 17 00:00:00 2001 -From: Ping-Ke Shih -Date: Wed, 3 Jan 2024 15:01:55 +0800 -Subject: [PATCH] wifi: rtw88: 8822ce: refine power parameters for RFE type 5 - -Refine the power parameters for better step response especially at high -current ramp case that is caused by power inductor variation. - -Signed-off-by: Ping-Ke Shih -Signed-off-by: Kalle Valo -Link: https://msgid.link/20240103070155.119488-1-pkshih@realtek.com ---- - drivers/net/wireless/realtek/rtw88/pci.c | 4 ++++ - drivers/net/wireless/realtek/rtw88/reg.h | 3 +++ - 2 files changed, 7 insertions(+) - -diff --git a/drivers/net/wireless/realtek/rtw88/pci.c b/drivers/net/wireless/realtek/rtw88/pci.c -index 2bfc0e822b8d0b..9986a4cb37eb2b 100644 ---- a/drivers/net/wireless/realtek/rtw88/pci.c -+++ b/drivers/net/wireless/realtek/rtw88/pci.c -@@ -1450,6 +1450,7 @@ static void rtw_pci_phy_cfg(struct rtw_dev *rtwdev) - { - struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; - const struct rtw_chip_info *chip = rtwdev->chip; -+ struct rtw_efuse *efuse = &rtwdev->efuse; - struct pci_dev *pdev = rtwpci->pdev; - const struct rtw_intf_phy_para *para; - u16 cut; -@@ -1498,6 +1499,9 @@ static void rtw_pci_phy_cfg(struct rtw_dev *rtwdev) - rtw_err(rtwdev, "failed to set PCI cap, ret = %d\n", - ret); - } -+ -+ if (chip->id == RTW_CHIP_TYPE_8822C && efuse->rfe_option == 5) -+ rtw_write32_mask(rtwdev, REG_ANAPARSW_MAC_0, BIT_CF_L_V2, 0x1); - } - - static int __maybe_unused rtw_pci_suspend(struct device *dev) -diff --git a/drivers/net/wireless/realtek/rtw88/reg.h b/drivers/net/wireless/realtek/rtw88/reg.h -index 1634f03784f171..b122f226924be5 100644 ---- a/drivers/net/wireless/realtek/rtw88/reg.h -+++ b/drivers/net/wireless/realtek/rtw88/reg.h -@@ -557,6 +557,9 @@ - #define REG_RFE_INV16 0x0cbe - #define BIT_RFE_BUF_EN BIT(3) - -+#define REG_ANAPARSW_MAC_0 0x1010 -+#define BIT_CF_L_V2 GENMASK(29, 28) -+ - #define REG_ANAPAR_XTAL_0 0x1040 - #define BIT_XCAP_0 GENMASK(23, 10) - #define REG_CPU_DMEM_CON 0x1080 diff --git a/packages/linux/patches/rtlwifi/6.9/0010-wifi-rtw88-debug-add-to-check-if-debug-mask-is-enabled.patch b/packages/linux/patches/rtlwifi/6.9/0010-wifi-rtw88-debug-add-to-check-if-debug-mask-is-enabled.patch deleted file mode 100644 index 94de3f7490..0000000000 --- a/packages/linux/patches/rtlwifi/6.9/0010-wifi-rtw88-debug-add-to-check-if-debug-mask-is-enabled.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 1926a27299db00239d6bdc4c3f2bd3f842277d0d Mon Sep 17 00:00:00 2001 -From: Chin-Yen Lee -Date: Mon, 16 Oct 2023 13:35:53 +0800 -Subject: [PATCH] wifi: rtw88: debug: add to check if debug mask is enabled - -The coming dump function for FW malfunction will add a function to -dump registers to reflect status. However, if we are not debugging -the mechanism, we don't print anything, so avoid reading registers by -checking debug mask to reduce IO. - -Signed-off-by: Chin-Yen Lee -Signed-off-by: Ping-Ke Shih -Signed-off-by: Kalle Valo -Link: https://lore.kernel.org/r/20231016053554.744180-2-pkshih@realtek.com ---- - drivers/net/wireless/realtek/rtw88/debug.h | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/drivers/net/wireless/realtek/rtw88/debug.h b/drivers/net/wireless/realtek/rtw88/debug.h -index a9149c6c2b48c5..a03ced11bbe042 100644 ---- a/drivers/net/wireless/realtek/rtw88/debug.h -+++ b/drivers/net/wireless/realtek/rtw88/debug.h -@@ -48,11 +48,23 @@ void __rtw_dbg(struct rtw_dev *rtwdev, enum rtw_debug_mask mask, - - #define rtw_dbg(rtwdev, a...) __rtw_dbg(rtwdev, ##a) - -+static inline bool rtw_dbg_is_enabled(struct rtw_dev *rtwdev, -+ enum rtw_debug_mask mask) -+{ -+ return !!(rtw_debug_mask & mask); -+} -+ - #else - - static inline void rtw_dbg(struct rtw_dev *rtwdev, enum rtw_debug_mask mask, - const char *fmt, ...) {} - -+static inline bool rtw_dbg_is_enabled(struct rtw_dev *rtwdev, -+ enum rtw_debug_mask mask) -+{ -+ return false; -+} -+ - #endif /* CONFIG_RTW88_DEBUG */ - - #define rtw_info(rtwdev, a...) dev_info(rtwdev->dev, ##a) diff --git a/packages/linux/patches/rtlwifi/6.9/0011-wifi-rtw88-dump-firmware-debug-information-in-abnormal-state.patch b/packages/linux/patches/rtlwifi/6.9/0011-wifi-rtw88-dump-firmware-debug-information-in-abnormal-state.patch deleted file mode 100644 index 30c227fdb9..0000000000 --- a/packages/linux/patches/rtlwifi/6.9/0011-wifi-rtw88-dump-firmware-debug-information-in-abnormal-state.patch +++ /dev/null @@ -1,234 +0,0 @@ -From 20907fc069976fcf972239b7b253cf7c59c08a14 Mon Sep 17 00:00:00 2001 -From: Chin-Yen Lee -Date: Mon, 16 Oct 2023 13:35:54 +0800 -Subject: [PATCH] wifi: rtw88: dump firmware debug information in abnormal - state - -Sometimes firmware may enter strange state or infinite -loop due to unknown bug, and then it will lead critical -function fail, such as sending H2C command or changing -power mode. In these abnormal states, we add more debug -information, including hardware register status, to help -further investigation. - -Signed-off-by: Chin-Yen Lee -Signed-off-by: Ping-Ke Shih -Signed-off-by: Kalle Valo -Link: https://lore.kernel.org/r/20231016053554.744180-3-pkshih@realtek.com ---- - drivers/net/wireless/realtek/rtw88/fw.c | 74 +++++++++++++++++++++++ - drivers/net/wireless/realtek/rtw88/fw.h | 3 + - drivers/net/wireless/realtek/rtw88/main.h | 6 ++ - drivers/net/wireless/realtek/rtw88/ps.c | 2 + - drivers/net/wireless/realtek/rtw88/reg.h | 23 +++++++ - 5 files changed, 108 insertions(+) - -diff --git a/drivers/net/wireless/realtek/rtw88/fw.c b/drivers/net/wireless/realtek/rtw88/fw.c -index a1b674e3caaa3c..acd78311c8c4a1 100644 ---- a/drivers/net/wireless/realtek/rtw88/fw.c -+++ b/drivers/net/wireless/realtek/rtw88/fw.c -@@ -17,6 +17,79 @@ - #include "phy.h" - #include "mac.h" - -+static const struct rtw_hw_reg_desc fw_h2c_regs[] = { -+ {REG_FWIMR, MASKDWORD, "FWIMR"}, -+ {REG_FWIMR, BIT_FS_H2CCMD_INT_EN, "FWIMR enable"}, -+ {REG_FWISR, MASKDWORD, "FWISR"}, -+ {REG_FWISR, BIT_FS_H2CCMD_INT, "FWISR enable"}, -+ {REG_HMETFR, BIT_INT_BOX_ALL, "BoxBitMap"}, -+ {REG_HMEBOX0, MASKDWORD, "MSG 0"}, -+ {REG_HMEBOX0_EX, MASKDWORD, "MSG_EX 0"}, -+ {REG_HMEBOX1, MASKDWORD, "MSG 1"}, -+ {REG_HMEBOX1_EX, MASKDWORD, "MSG_EX 1"}, -+ {REG_HMEBOX2, MASKDWORD, "MSG 2"}, -+ {REG_HMEBOX2_EX, MASKDWORD, "MSG_EX 2"}, -+ {REG_HMEBOX3, MASKDWORD, "MSG 3"}, -+ {REG_HMEBOX3_EX, MASKDWORD, "MSG_EX 3"}, -+ {REG_FT1IMR, MASKDWORD, "FT1IMR"}, -+ {REG_FT1IMR, BIT_FS_H2C_CMD_OK_INT_EN, "FT1IMR enable"}, -+ {REG_FT1ISR, MASKDWORD, "FT1ISR"}, -+ {REG_FT1ISR, BIT_FS_H2C_CMD_OK_INT, "FT1ISR enable "}, -+}; -+ -+static const struct rtw_hw_reg_desc fw_c2h_regs[] = { -+ {REG_FWIMR, MASKDWORD, "FWIMR"}, -+ {REG_FWIMR, BIT_FS_H2CCMD_INT_EN, "CPWM"}, -+ {REG_FWIMR, BIT_FS_HRCV_INT_EN, "HRECV"}, -+ {REG_FWISR, MASKDWORD, "FWISR"}, -+ {REG_FWISR, BIT_FS_H2CCMD_INT, "CPWM"}, -+ {REG_FWISR, BIT_FS_HRCV_INT, "HRECV"}, -+ {REG_CPWM, MASKDWORD, "REG_CPWM"}, -+}; -+ -+static const struct rtw_hw_reg_desc fw_core_regs[] = { -+ {REG_ARFR2_V1, MASKDWORD, "EPC"}, -+ {REG_ARFRH2_V1, MASKDWORD, "BADADDR"}, -+ {REG_ARFR3_V1, MASKDWORD, "CAUSE"}, -+ {REG_ARFR3_V1, BIT_EXC_CODE, "ExcCode"}, -+ {REG_ARFRH3_V1, MASKDWORD, "Status"}, -+ {REG_ARFR4, MASKDWORD, "SP"}, -+ {REG_ARFRH4, MASKDWORD, "RA"}, -+ {REG_FW_DBG6, MASKDWORD, "DBG 6"}, -+ {REG_FW_DBG7, MASKDWORD, "DBG 7"}, -+}; -+ -+static void _rtw_fw_dump_dbg_info(struct rtw_dev *rtwdev, -+ const struct rtw_hw_reg_desc regs[], u32 size) -+{ -+ const struct rtw_hw_reg_desc *reg; -+ u32 val; -+ int i; -+ -+ for (i = 0; i < size; i++) { -+ reg = ®s[i]; -+ val = rtw_read32_mask(rtwdev, reg->addr, reg->mask); -+ -+ rtw_dbg(rtwdev, RTW_DBG_FW, "[%s]addr:0x%x mask:0x%x value:0x%x\n", -+ reg->desc, reg->addr, reg->mask, val); -+ } -+} -+ -+void rtw_fw_dump_dbg_info(struct rtw_dev *rtwdev) -+{ -+ int i; -+ -+ if (!rtw_dbg_is_enabled(rtwdev, RTW_DBG_FW)) -+ return; -+ -+ _rtw_fw_dump_dbg_info(rtwdev, fw_h2c_regs, ARRAY_SIZE(fw_h2c_regs)); -+ _rtw_fw_dump_dbg_info(rtwdev, fw_c2h_regs, ARRAY_SIZE(fw_c2h_regs)); -+ for (i = 0 ; i < RTW_DEBUG_DUMP_TIMES; i++) { -+ rtw_dbg(rtwdev, RTW_DBG_FW, "Firmware Coredump %dth\n", i + 1); -+ _rtw_fw_dump_dbg_info(rtwdev, fw_core_regs, ARRAY_SIZE(fw_core_regs)); -+ } -+} -+ - static void rtw_fw_c2h_cmd_handle_ext(struct rtw_dev *rtwdev, - struct sk_buff *skb) - { -@@ -349,6 +422,7 @@ static void rtw_fw_send_h2c_command_register(struct rtw_dev *rtwdev, - - if (ret) { - rtw_err(rtwdev, "failed to send h2c command\n"); -+ rtw_fw_dump_dbg_info(rtwdev); - return; - } - -diff --git a/drivers/net/wireless/realtek/rtw88/fw.h b/drivers/net/wireless/realtek/rtw88/fw.h -index 43ccdf9965ac46..84e47c71ea1255 100644 ---- a/drivers/net/wireless/realtek/rtw88/fw.h -+++ b/drivers/net/wireless/realtek/rtw88/fw.h -@@ -44,6 +44,8 @@ - #define RTW_OLD_PROBE_PG_CNT 2 - #define RTW_PROBE_PG_CNT 4 - -+#define RTW_DEBUG_DUMP_TIMES 10 -+ - enum rtw_c2h_cmd_id { - C2H_CCX_TX_RPT = 0x03, - C2H_BT_INFO = 0x09, -@@ -808,6 +810,7 @@ static inline bool rtw_fw_feature_ext_check(struct rtw_fw_state *fw, - return !!(fw->feature_ext & feature); - } - -+void rtw_fw_dump_dbg_info(struct rtw_dev *rtwdev); - void rtw_fw_c2h_cmd_rx_irqsafe(struct rtw_dev *rtwdev, u32 pkt_offset, - struct sk_buff *skb); - void rtw_fw_c2h_cmd_handle(struct rtw_dev *rtwdev, struct sk_buff *skb); -diff --git a/drivers/net/wireless/realtek/rtw88/main.h b/drivers/net/wireless/realtek/rtw88/main.h -index 86dc1516effade..b6bfd4c02e2db3 100644 ---- a/drivers/net/wireless/realtek/rtw88/main.h -+++ b/drivers/net/wireless/realtek/rtw88/main.h -@@ -524,6 +524,12 @@ struct rtw_hw_reg { - u32 mask; - }; - -+struct rtw_hw_reg_desc { -+ u32 addr; -+ u32 mask; -+ const char *desc; -+}; -+ - struct rtw_ltecoex_addr { - u32 ctrl; - u32 wdata; -diff --git a/drivers/net/wireless/realtek/rtw88/ps.c b/drivers/net/wireless/realtek/rtw88/ps.c -index 07e8cbd436cd81..add5a20b84320f 100644 ---- a/drivers/net/wireless/realtek/rtw88/ps.c -+++ b/drivers/net/wireless/realtek/rtw88/ps.c -@@ -104,6 +104,7 @@ void rtw_power_mode_change(struct rtw_dev *rtwdev, bool enter) - */ - WARN(1, "firmware failed to ack driver for %s Deep Power mode\n", - enter ? "entering" : "leaving"); -+ rtw_fw_dump_dbg_info(rtwdev); - } - } - EXPORT_SYMBOL(rtw_power_mode_change); -@@ -164,6 +165,7 @@ static void rtw_fw_leave_lps_check(struct rtw_dev *rtwdev) - if (ret) { - rtw_write32_clr(rtwdev, REG_TCR, BIT_PWRMGT_HWDATA_EN); - rtw_warn(rtwdev, "firmware failed to leave lps state\n"); -+ rtw_fw_dump_dbg_info(rtwdev); - } - } - -diff --git a/drivers/net/wireless/realtek/rtw88/reg.h b/drivers/net/wireless/realtek/rtw88/reg.h -index 7c6c11d50ff30f..1634f03784f171 100644 ---- a/drivers/net/wireless/realtek/rtw88/reg.h -+++ b/drivers/net/wireless/realtek/rtw88/reg.h -@@ -224,12 +224,25 @@ - #define REG_RXFF_BNDY 0x011C - #define REG_FE1IMR 0x0120 - #define BIT_FS_RXDONE BIT(16) -+#define REG_CPWM 0x012C -+#define REG_FWIMR 0x0130 -+#define BIT_FS_H2CCMD_INT_EN BIT(4) -+#define BIT_FS_HRCV_INT_EN BIT(5) -+#define REG_FWISR 0x0134 -+#define BIT_FS_H2CCMD_INT BIT(4) -+#define BIT_FS_HRCV_INT BIT(5) - #define REG_PKTBUF_DBG_CTRL 0x0140 - #define REG_C2HEVT 0x01A0 - #define REG_MCUTST_1 0x01C0 - #define REG_MCUTST_II 0x01C4 - #define REG_WOWLAN_WAKE_REASON 0x01C7 - #define REG_HMETFR 0x01CC -+#define BIT_INT_BOX0 BIT(0) -+#define BIT_INT_BOX1 BIT(1) -+#define BIT_INT_BOX2 BIT(2) -+#define BIT_INT_BOX3 BIT(3) -+#define BIT_INT_BOX_ALL (BIT_INT_BOX0 | BIT_INT_BOX1 | BIT_INT_BOX2 | \ -+ BIT_INT_BOX3) - #define REG_HMEBOX0 0x01D0 - #define REG_HMEBOX1 0x01D4 - #define REG_HMEBOX2 0x01D8 -@@ -338,6 +351,11 @@ - #define BIT_EN_GNT_BT_AWAKE BIT(3) - #define BIT_EN_EOF_V1 BIT(2) - #define REG_DATA_SC 0x0483 -+#define REG_ARFR2_V1 0x048C -+#define REG_ARFRH2_V1 0x0490 -+#define REG_ARFR3_V1 0x0494 -+#define BIT_EXC_CODE GENMASK(6, 2) -+#define REG_ARFRH3_V1 0x0498 - #define REG_ARFR4 0x049C - #define BIT_WL_RFK BIT(0) - #define REG_ARFRH4 0x04A0 -@@ -548,11 +566,16 @@ - - #define REG_H2C_PKT_READADDR 0x10D0 - #define REG_H2C_PKT_WRITEADDR 0x10D4 -+#define REG_FW_DBG6 0x10F8 - #define REG_FW_DBG7 0x10FC - #define FW_KEY_MASK 0xffffff00 - - #define REG_CR_EXT 0x1100 - -+#define REG_FT1IMR 0x1138 -+#define BIT_FS_H2C_CMD_OK_INT_EN BIT(25) -+#define REG_FT1ISR 0x113c -+#define BIT_FS_H2C_CMD_OK_INT BIT(25) - #define REG_DDMA_CH0SA 0x1200 - #define REG_DDMA_CH0DA 0x1204 - #define REG_DDMA_CH0CTRL 0x1208 From 5b6e3b69637e39805e6b5be1755567ab6fa9eb6b Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Fri, 22 Nov 2024 23:31:18 +0100 Subject: [PATCH 9/9] rpi-eeprom: update to eefb7b8 Signed-off-by: Matthias Reichl --- packages/tools/rpi-eeprom/package.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/packages/tools/rpi-eeprom/package.mk b/packages/tools/rpi-eeprom/package.mk index 8cd144df37..20ef64eb1a 100644 --- a/packages/tools/rpi-eeprom/package.mk +++ b/packages/tools/rpi-eeprom/package.mk @@ -2,8 +2,8 @@ # Copyright (C) 2019-present Team LibreELEC (https://libreelec.tv) PKG_NAME="rpi-eeprom" -PKG_VERSION="cc0ad4698ee2c1b415285270a4e91229c63e19b5" -PKG_SHA256="fb9ba96ad8d80e164dd75ea51e7b2d98da033d708ce4e97ebe684badbb843208" +PKG_VERSION="eefb7b83bc9b602455d9eaf34a51149a6e9cca96" +PKG_SHA256="962a5403277705a96df2dcaee1a3cdde80f10b06cdd556453fe92f82e6a07485" PKG_LICENSE="BSD-3/custom" PKG_SITE="https://github.com/raspberrypi/rpi-eeprom" PKG_URL="https://github.com/raspberrypi/rpi-eeprom/archive/${PKG_VERSION}.tar.gz"