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linux (RPi): update to 5.10.7-c077470
drop LBM and scaler pos patches which are now in RPi kernel tree Signed-off-by: Matthias Reichl <hias@horus.com>
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19675d422d
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@ -22,8 +22,8 @@ case "${LINUX}" in
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PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz"
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;;
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raspberrypi)
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PKG_VERSION="e9505f4612646533f53813aabef5ca040b0ea49d" # 5.10.7
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PKG_SHA256="2d6e3637dbe328161161cbdede2902e0aaaa979bd0179a40e14d2960a61de593"
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PKG_VERSION="c07747092a602a1e36dfae545c604c31e602362a" # 5.10.7
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PKG_SHA256="2d68653fc14fb06fa1dce69954c006cef93fd91b092319075361bcc3ff894d1d"
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PKG_URL="https://github.com/raspberrypi/linux/archive/${PKG_VERSION}.tar.gz"
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PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz"
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;;
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@ -1,70 +0,0 @@
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From 20076ee25ac4a9ddc26dfbb508570c85c88ba6ef Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Thu, 14 Jan 2021 16:01:50 +0000
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Subject: [PATCH] vc4: Correct lbm size and calculation
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LBM base address is measured in units of pixels per cycle.
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That is 4 for 2711 (hvs5) and 2 for 2708.
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We are wasting 75% of lbm by indexing without the scaling.
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But we were also using too high a size for the lbm resulting
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in partial corruption (right hand side) of vertically
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scaled images, usually at 4K or lower resolutions with more layers.
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The physical RAM of LBM on 2711 is 8 * 1920 * 16 * 12-bit
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(pixels are stored 12-bits per component regardless of format).
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The LBM adress indexes work in units of pixels per clock,
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so for 4 pixels per clock that means we have 32 * 1920 = 60K
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_hvs.c | 8 ++++----
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drivers/gpu/drm/vc4/vc4_plane.c | 7 ++++++-
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2 files changed, 10 insertions(+), 5 deletions(-)
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diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
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index f2a99579a8d0f..3ceda2ff072bb 100644
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--- a/drivers/gpu/drm/vc4/vc4_hvs.c
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+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
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@@ -661,11 +661,11 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
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* for now we just allocate globally.
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*/
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if (!hvs->hvs5)
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- /* 96kB */
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- drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
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+ /* 48k words of 2x12-bit pixels */
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+ drm_mm_init(&hvs->lbm_mm, 0, 48 * 1024);
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else
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- /* 70k words */
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- drm_mm_init(&hvs->lbm_mm, 0, 70 * 2 * 1024);
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+ /* 60k words of 4x12-bit pixels */
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+ drm_mm_init(&hvs->lbm_mm, 0, 60 * 1024);
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/* Upload filter kernels. We only have the one for now, so we
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* keep it around for the lifetime of the driver.
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diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
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index 100b3541bc6ef..6bdfc1ba7b46d 100644
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -444,6 +444,7 @@ static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
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static u32 vc4_lbm_size(struct drm_plane_state *state)
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{
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struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
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+ struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev);
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u32 pix_per_line;
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u32 lbm;
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@@ -479,7 +480,11 @@ static u32 vc4_lbm_size(struct drm_plane_state *state)
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lbm = pix_per_line * 16;
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}
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- lbm = roundup(lbm, 32);
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+ /* Align it to 64 or 128 (hvs5) bytes */
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+ lbm = roundup(lbm, vc4->hvs->hvs5 ? 128 : 64);
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+
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+ /* Each "word" of the LBM memory contains 2 or 4 (hvs5) pixels */
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+ lbm /= vc4->hvs->hvs5 ? 4 : 2;
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return lbm;
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}
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@ -1,27 +0,0 @@
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From 21ed5c49de516d496f9820dc1ddaa4027daa8823 Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Sun, 17 Jan 2021 17:07:02 +0000
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Subject: [PATCH] vc4: Correct POS1_SCL for hvs5
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Fixes: c54619b0bfb35c4153b3fb34916a6fa50dcf2dc1
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_plane.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
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index 6bdfc1ba7b46d..b5586c92bfe54 100644
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -984,9 +984,9 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
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if (!vc4_state->is_unity) {
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vc4_dlist_write(vc4_state,
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VC4_SET_FIELD(vc4_state->crtc_w,
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- SCALER_POS1_SCL_WIDTH) |
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+ SCALER5_POS1_SCL_WIDTH) |
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VC4_SET_FIELD(vc4_state->crtc_h,
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- SCALER_POS1_SCL_HEIGHT));
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+ SCALER5_POS1_SCL_HEIGHT));
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}
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/* Position Word 2: Source Image Size */
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