diff --git a/packages/linux/patches/linux-2.6.38-rc8-300-linux_omap_dss2_20110309.patch b/packages/linux/patches/linux-2.6.38-rc8-300-linux_omap_dss2_20110309.patch deleted file mode 100644 index 6ccc3f801e..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc8-300-linux_omap_dss2_20110309.patch +++ /dev/null @@ -1,29939 +0,0 @@ -diff -Naur linux-2.6.38-rc7/arch/arm/configs/omap2plus_defconfig linux-2.6.38-rc7-linux-omap-dss2/arch/arm/configs/omap2plus_defconfig ---- linux-2.6.38-rc7/arch/arm/configs/omap2plus_defconfig 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/configs/omap2plus_defconfig 2011-03-09 13:19:09.493514052 +0100 -@@ -58,6 +58,7 @@ - CONFIG_NO_HZ=y - CONFIG_HIGH_RES_TIMERS=y - CONFIG_SMP=y -+CONFIG_NR_CPUS=2 - # CONFIG_LOCAL_TIMERS is not set - CONFIG_AEABI=y - CONFIG_LEDS=y -@@ -192,6 +193,17 @@ - CONFIG_FB_MODE_HELPERS=y - CONFIG_FB_TILEBLITTING=y - CONFIG_FB_OMAP_LCD_VGA=y -+CONFIG_OMAP2_DSS=m -+CONFIG_OMAP2_DSS_RFBI=y -+CONFIG_OMAP2_DSS_SDI=y -+CONFIG_OMAP2_DSS_DSI=y -+CONFIG_FB_OMAP2=m -+CONFIG_PANEL_GENERIC_DPI=m -+CONFIG_PANEL_SHARP_LS037V7DW01=m -+CONFIG_PANEL_NEC_NL8048HL11_01B=m -+CONFIG_PANEL_TAAL=m -+CONFIG_PANEL_TPO_TD043MTEA1=m -+CONFIG_PANEL_ACX565AKM=m - CONFIG_BACKLIGHT_LCD_SUPPORT=y - CONFIG_LCD_CLASS_DEVICE=y - CONFIG_LCD_PLATFORM=y -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-ams-delta.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-ams-delta.c ---- linux-2.6.38-rc7/arch/arm/mach-omap1/board-ams-delta.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-ams-delta.c 2011-03-09 13:19:09.778508271 +0100 -@@ -165,7 +165,7 @@ - } - }; - --static struct omap_lcd_config ams_delta_lcd_config __initdata = { -+static struct omap_lcd_config ams_delta_lcd_config = { - .ctrl_name = "internal", - }; - -@@ -175,7 +175,7 @@ - .pins[0] = 2, - }; - --static struct omap_board_config_kernel ams_delta_config[] = { -+static struct omap_board_config_kernel ams_delta_config[] __initdata = { - { OMAP_TAG_LCD, &ams_delta_lcd_config }, - }; - -@@ -208,14 +208,14 @@ - .keymap_size = ARRAY_SIZE(ams_delta_keymap), - }; - --static struct omap_kp_platform_data ams_delta_kp_data = { -+static struct omap_kp_platform_data ams_delta_kp_data __initdata = { - .rows = 8, - .cols = 8, - .keymap_data = &ams_delta_keymap_data, - .delay = 9, - }; - --static struct platform_device ams_delta_kp_device = { -+static struct platform_device ams_delta_kp_device __initdata = { - .name = "omap-keypad", - .id = -1, - .dev = { -@@ -225,12 +225,12 @@ - .resource = ams_delta_kp_resources, - }; - --static struct platform_device ams_delta_lcd_device = { -+static struct platform_device ams_delta_lcd_device __initdata = { - .name = "lcd_ams_delta", - .id = -1, - }; - --static struct platform_device ams_delta_led_device = { -+static struct platform_device ams_delta_led_device __initdata = { - .name = "ams-delta-led", - .id = -1 - }; -@@ -259,7 +259,7 @@ - #define ams_delta_camera_power NULL - #endif - --static struct soc_camera_link __initdata ams_delta_iclink = { -+static struct soc_camera_link ams_delta_iclink = { - .bus_id = 0, /* OMAP1 SoC camera bus */ - .i2c_adapter_id = 1, - .board_info = &ams_delta_camera_board_info[0], -@@ -267,7 +267,7 @@ - .power = ams_delta_camera_power, - }; - --static struct platform_device ams_delta_camera_device = { -+static struct platform_device ams_delta_camera_device __initdata = { - .name = "soc-camera-pdrv", - .id = 0, - .dev = { -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-fsample.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-fsample.c ---- linux-2.6.38-rc7/arch/arm/mach-omap1/board-fsample.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-fsample.c 2011-03-09 13:19:09.779508251 +0100 -@@ -287,11 +287,11 @@ - &lcd_device, - }; - --static struct omap_lcd_config fsample_lcd_config __initdata = { -+static struct omap_lcd_config fsample_lcd_config = { - .ctrl_name = "internal", - }; - --static struct omap_board_config_kernel fsample_config[] = { -+static struct omap_board_config_kernel fsample_config[] __initdata = { - { OMAP_TAG_LCD, &fsample_lcd_config }, - }; - -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-h2.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-h2.c ---- linux-2.6.38-rc7/arch/arm/mach-omap1/board-h2.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-h2.c 2011-03-09 13:19:09.779508251 +0100 -@@ -202,7 +202,7 @@ - - static const char *h2_part_probes[] = { "cmdlinepart", NULL }; - --struct platform_nand_data h2_nand_platdata = { -+static struct platform_nand_data h2_nand_platdata = { - .chip = { - .nr_chips = 1, - .chip_offset = 0, -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-h3.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-h3.c ---- linux-2.6.38-rc7/arch/arm/mach-omap1/board-h3.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-h3.c 2011-03-09 13:19:09.780508231 +0100 -@@ -204,7 +204,7 @@ - - static const char *part_probes[] = { "cmdlinepart", NULL }; - --struct platform_nand_data nand_platdata = { -+static struct platform_nand_data nand_platdata = { - .chip = { - .nr_chips = 1, - .chip_offset = 0, -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-htcherald.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-htcherald.c ---- linux-2.6.38-rc7/arch/arm/mach-omap1/board-htcherald.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-htcherald.c 2011-03-09 13:19:09.780508231 +0100 -@@ -331,7 +331,7 @@ - }, - }; - --struct htcpld_chip_platform_data htcpld_chips[] = { -+static struct htcpld_chip_platform_data htcpld_chips[] = { - [0] = { - .addr = 0x03, - .reset = 0x04, -@@ -366,7 +366,7 @@ - }, - }; - --struct htcpld_core_platform_data htcpld_pfdata = { -+static struct htcpld_core_platform_data htcpld_pfdata = { - .int_reset_gpio_hi = HTCPLD_GPIO_INT_RESET_HI, - .int_reset_gpio_lo = HTCPLD_GPIO_INT_RESET_LO, - .i2c_adapter_id = 1, -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-innovator.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-innovator.c ---- linux-2.6.38-rc7/arch/arm/mach-omap1/board-innovator.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-innovator.c 2011-03-09 13:19:09.781508211 +0100 -@@ -365,7 +365,7 @@ - - static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC]; - --void __init innovator_mmc_init(void) -+static void __init innovator_mmc_init(void) - { - mmc_data[0] = &mmc1_data; - omap1_init_mmc(mmc_data, OMAP15XX_NR_MMC); -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-nokia770.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-nokia770.c ---- linux-2.6.38-rc7/arch/arm/mach-omap1/board-nokia770.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-nokia770.c 2011-03-09 13:19:09.781508211 +0100 -@@ -115,7 +115,7 @@ - .shutdown = mipid_shutdown, - }; - --static void mipid_dev_init(void) -+static void __init mipid_dev_init(void) - { - const struct omap_lcd_config *conf; - -@@ -126,7 +126,7 @@ - } - } - --static void ads7846_dev_init(void) -+static void __init ads7846_dev_init(void) - { - if (gpio_request(ADS7846_PENDOWN_GPIO, "ADS7846 pendown") < 0) - printk(KERN_ERR "can't get ads7846 pen down GPIO\n"); -@@ -170,7 +170,7 @@ - .te_connected = 1, - }; - --static void hwa742_dev_init(void) -+static void __init hwa742_dev_init(void) - { - clk_add_alias("hwa_sys_ck", NULL, "bclk", NULL); - omapfb_set_ctrl_platform_data(&nokia770_hwa742_platform_data); -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-palmte.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-palmte.c ---- linux-2.6.38-rc7/arch/arm/mach-omap1/board-palmte.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-palmte.c 2011-03-09 13:19:09.781508211 +0100 -@@ -230,19 +230,6 @@ - }, - }; - --static void palmte_headphones_detect(void *data, int state) --{ -- if (state) { -- /* Headphones connected, disable speaker */ -- gpio_set_value(PALMTE_SPEAKER_GPIO, 0); -- printk(KERN_INFO "PM: speaker off\n"); -- } else { -- /* Headphones unplugged, re-enable speaker */ -- gpio_set_value(PALMTE_SPEAKER_GPIO, 1); -- printk(KERN_INFO "PM: speaker on\n"); -- } --} -- - static void __init palmte_misc_gpio_setup(void) - { - /* Set TSC2102 PINTDAV pin as input (used by TSC2102 driver) */ -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/board-voiceblue.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-voiceblue.c ---- linux-2.6.38-rc7/arch/arm/mach-omap1/board-voiceblue.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/board-voiceblue.c 2011-03-09 13:19:09.783508169 +0100 -@@ -26,10 +26,12 @@ - #include - - #include -+#include - #include - #include - #include - -+#include - #include - #include - #include -@@ -163,52 +165,6 @@ - omap_init_irq(); - } - --static void __init voiceblue_init(void) --{ -- /* mux pins for uarts */ -- omap_cfg_reg(UART1_TX); -- omap_cfg_reg(UART1_RTS); -- omap_cfg_reg(UART2_TX); -- omap_cfg_reg(UART2_RTS); -- omap_cfg_reg(UART3_TX); -- omap_cfg_reg(UART3_RX); -- -- /* Watchdog */ -- gpio_request(0, "Watchdog"); -- /* smc91x reset */ -- gpio_request(7, "SMC91x reset"); -- gpio_direction_output(7, 1); -- udelay(2); /* wait at least 100ns */ -- gpio_set_value(7, 0); -- mdelay(50); /* 50ms until PHY ready */ -- /* smc91x interrupt pin */ -- gpio_request(8, "SMC91x irq"); -- /* 16C554 reset*/ -- gpio_request(6, "16C554 reset"); -- gpio_direction_output(6, 0); -- /* 16C554 interrupt pins */ -- gpio_request(12, "16C554 irq"); -- gpio_request(13, "16C554 irq"); -- gpio_request(14, "16C554 irq"); -- gpio_request(15, "16C554 irq"); -- set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); -- set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); -- set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); -- set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); -- -- platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); -- omap_board_config = voiceblue_config; -- omap_board_config_size = ARRAY_SIZE(voiceblue_config); -- omap_serial_init(); -- omap1_usb_init(&voiceblue_usb_config); -- omap_register_i2c_bus(1, 100, NULL, 0); -- -- /* There is a good chance board is going up, so enable power LED -- * (it is connected through invertor) */ -- omap_writeb(0x00, OMAP_LPG1_LCR); -- omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */ --} -- - static void __init voiceblue_map_io(void) - { - omap1_map_common_io(); -@@ -275,8 +231,17 @@ - gpio_set_value(0, wdt_gpio_state); - } - --void voiceblue_reset(void) -+static void voiceblue_reset(char mode, const char *cmd) - { -+ /* -+ * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 -+ * "Global Software Reset Affects Traffic Controller Frequency". -+ */ -+ if (cpu_is_omap5912()) { -+ omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); -+ omap_writew(0x8, ARM_RSTCT1); -+ } -+ - set_bit(MACHINE_REBOOT, &machine_state); - voiceblue_wdt_enable(); - while (1) ; -@@ -286,6 +251,54 @@ - EXPORT_SYMBOL(voiceblue_wdt_disable); - EXPORT_SYMBOL(voiceblue_wdt_ping); - -+static void __init voiceblue_init(void) -+{ -+ /* mux pins for uarts */ -+ omap_cfg_reg(UART1_TX); -+ omap_cfg_reg(UART1_RTS); -+ omap_cfg_reg(UART2_TX); -+ omap_cfg_reg(UART2_RTS); -+ omap_cfg_reg(UART3_TX); -+ omap_cfg_reg(UART3_RX); -+ -+ /* Watchdog */ -+ gpio_request(0, "Watchdog"); -+ /* smc91x reset */ -+ gpio_request(7, "SMC91x reset"); -+ gpio_direction_output(7, 1); -+ udelay(2); /* wait at least 100ns */ -+ gpio_set_value(7, 0); -+ mdelay(50); /* 50ms until PHY ready */ -+ /* smc91x interrupt pin */ -+ gpio_request(8, "SMC91x irq"); -+ /* 16C554 reset*/ -+ gpio_request(6, "16C554 reset"); -+ gpio_direction_output(6, 0); -+ /* 16C554 interrupt pins */ -+ gpio_request(12, "16C554 irq"); -+ gpio_request(13, "16C554 irq"); -+ gpio_request(14, "16C554 irq"); -+ gpio_request(15, "16C554 irq"); -+ set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); -+ set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); -+ set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); -+ set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); -+ -+ platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); -+ omap_board_config = voiceblue_config; -+ omap_board_config_size = ARRAY_SIZE(voiceblue_config); -+ omap_serial_init(); -+ omap1_usb_init(&voiceblue_usb_config); -+ omap_register_i2c_bus(1, 100, NULL, 0); -+ -+ /* There is a good chance board is going up, so enable power LED -+ * (it is connected through invertor) */ -+ omap_writeb(0x00, OMAP_LPG1_LCR); -+ omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */ -+ -+ arch_reset = voiceblue_reset; -+} -+ - MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910") - /* Maintainer: Ladislav Michl */ - .boot_params = 0x10000100, -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/Makefile linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/Makefile ---- linux-2.6.38-rc7/arch/arm/mach-omap1/Makefile 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/Makefile 2011-03-09 13:19:09.778508271 +0100 -@@ -4,7 +4,7 @@ - - # Common support - obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o --obj-y += clock.o clock_data.o opp_data.o -+obj-y += clock.o clock_data.o opp_data.o reset.o - - obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o - -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/mcbsp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/mcbsp.c ---- linux-2.6.38-rc7/arch/arm/mach-omap1/mcbsp.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/mcbsp.c 2011-03-09 13:19:09.789508048 +0100 -@@ -10,6 +10,7 @@ - * - * Multichannel mode not supported. - */ -+#include - #include - #include - #include -@@ -78,100 +79,288 @@ - }; - - #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+struct resource omap7xx_mcbsp_res[][6] = { -+ { -+ { -+ .start = OMAP7XX_MCBSP1_BASE, -+ .end = OMAP7XX_MCBSP1_BASE + SZ_256, -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "rx", -+ .start = INT_7XX_McBSP1RX, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "tx", -+ .start = INT_7XX_McBSP1TX, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "rx", -+ .start = OMAP_DMA_MCBSP1_RX, -+ .flags = IORESOURCE_DMA, -+ }, -+ { -+ .name = "tx", -+ .start = OMAP_DMA_MCBSP1_TX, -+ .flags = IORESOURCE_DMA, -+ }, -+ }, -+ { -+ { -+ .start = OMAP7XX_MCBSP2_BASE, -+ .end = OMAP7XX_MCBSP2_BASE + SZ_256, -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "rx", -+ .start = INT_7XX_McBSP2RX, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "tx", -+ .start = INT_7XX_McBSP2TX, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "rx", -+ .start = OMAP_DMA_MCBSP3_RX, -+ .flags = IORESOURCE_DMA, -+ }, -+ { -+ .name = "tx", -+ .start = OMAP_DMA_MCBSP3_TX, -+ .flags = IORESOURCE_DMA, -+ }, -+ }, -+}; -+ - static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = { - { -- .phys_base = OMAP7XX_MCBSP1_BASE, -- .dma_rx_sync = OMAP_DMA_MCBSP1_RX, -- .dma_tx_sync = OMAP_DMA_MCBSP1_TX, -- .rx_irq = INT_7XX_McBSP1RX, -- .tx_irq = INT_7XX_McBSP1TX, - .ops = &omap1_mcbsp_ops, - }, - { -- .phys_base = OMAP7XX_MCBSP2_BASE, -- .dma_rx_sync = OMAP_DMA_MCBSP3_RX, -- .dma_tx_sync = OMAP_DMA_MCBSP3_TX, -- .rx_irq = INT_7XX_McBSP2RX, -- .tx_irq = INT_7XX_McBSP2TX, - .ops = &omap1_mcbsp_ops, - }, - }; --#define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata) --#define OMAP7XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) -+#define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1]) -+#define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res) - #else -+#define omap7xx_mcbsp_res NULL - #define omap7xx_mcbsp_pdata NULL --#define OMAP7XX_MCBSP_PDATA_SZ 0 --#define OMAP7XX_MCBSP_REG_NUM 0 -+#define OMAP7XX_MCBSP_RES_SZ 0 -+#define OMAP7XX_MCBSP_COUNT 0 - #endif - - #ifdef CONFIG_ARCH_OMAP15XX -+struct resource omap15xx_mcbsp_res[][6] = { -+ { -+ { -+ .start = OMAP1510_MCBSP1_BASE, -+ .end = OMAP1510_MCBSP1_BASE + SZ_256, -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "rx", -+ .start = INT_McBSP1RX, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "tx", -+ .start = INT_McBSP1TX, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "rx", -+ .start = OMAP_DMA_MCBSP1_RX, -+ .flags = IORESOURCE_DMA, -+ }, -+ { -+ .name = "tx", -+ .start = OMAP_DMA_MCBSP1_TX, -+ .flags = IORESOURCE_DMA, -+ }, -+ }, -+ { -+ { -+ .start = OMAP1510_MCBSP2_BASE, -+ .end = OMAP1510_MCBSP2_BASE + SZ_256, -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "rx", -+ .start = INT_1510_SPI_RX, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "tx", -+ .start = INT_1510_SPI_TX, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "rx", -+ .start = OMAP_DMA_MCBSP2_RX, -+ .flags = IORESOURCE_DMA, -+ }, -+ { -+ .name = "tx", -+ .start = OMAP_DMA_MCBSP2_TX, -+ .flags = IORESOURCE_DMA, -+ }, -+ }, -+ { -+ { -+ .start = OMAP1510_MCBSP3_BASE, -+ .end = OMAP1510_MCBSP3_BASE + SZ_256, -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "rx", -+ .start = INT_McBSP3RX, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "tx", -+ .start = INT_McBSP3TX, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "rx", -+ .start = OMAP_DMA_MCBSP3_RX, -+ .flags = IORESOURCE_DMA, -+ }, -+ { -+ .name = "tx", -+ .start = OMAP_DMA_MCBSP3_TX, -+ .flags = IORESOURCE_DMA, -+ }, -+ }, -+}; -+ - static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { - { -- .phys_base = OMAP1510_MCBSP1_BASE, -- .dma_rx_sync = OMAP_DMA_MCBSP1_RX, -- .dma_tx_sync = OMAP_DMA_MCBSP1_TX, -- .rx_irq = INT_McBSP1RX, -- .tx_irq = INT_McBSP1TX, - .ops = &omap1_mcbsp_ops, - }, - { -- .phys_base = OMAP1510_MCBSP2_BASE, -- .dma_rx_sync = OMAP_DMA_MCBSP2_RX, -- .dma_tx_sync = OMAP_DMA_MCBSP2_TX, -- .rx_irq = INT_1510_SPI_RX, -- .tx_irq = INT_1510_SPI_TX, - .ops = &omap1_mcbsp_ops, - }, - { -- .phys_base = OMAP1510_MCBSP3_BASE, -- .dma_rx_sync = OMAP_DMA_MCBSP3_RX, -- .dma_tx_sync = OMAP_DMA_MCBSP3_TX, -- .rx_irq = INT_McBSP3RX, -- .tx_irq = INT_McBSP3TX, - .ops = &omap1_mcbsp_ops, - }, - }; --#define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata) --#define OMAP15XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) -+#define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1]) -+#define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res) - #else -+#define omap15xx_mcbsp_res NULL - #define omap15xx_mcbsp_pdata NULL --#define OMAP15XX_MCBSP_PDATA_SZ 0 --#define OMAP15XX_MCBSP_REG_NUM 0 -+#define OMAP15XX_MCBSP_RES_SZ 0 -+#define OMAP15XX_MCBSP_COUNT 0 - #endif - - #ifdef CONFIG_ARCH_OMAP16XX -+struct resource omap16xx_mcbsp_res[][6] = { -+ { -+ { -+ .start = OMAP1610_MCBSP1_BASE, -+ .end = OMAP1610_MCBSP1_BASE + SZ_256, -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "rx", -+ .start = INT_McBSP1RX, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "tx", -+ .start = INT_McBSP1TX, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "rx", -+ .start = OMAP_DMA_MCBSP1_RX, -+ .flags = IORESOURCE_DMA, -+ }, -+ { -+ .name = "tx", -+ .start = OMAP_DMA_MCBSP1_TX, -+ .flags = IORESOURCE_DMA, -+ }, -+ }, -+ { -+ { -+ .start = OMAP1610_MCBSP2_BASE, -+ .end = OMAP1610_MCBSP2_BASE + SZ_256, -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "rx", -+ .start = INT_1610_McBSP2_RX, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "tx", -+ .start = INT_1610_McBSP2_TX, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "rx", -+ .start = OMAP_DMA_MCBSP2_RX, -+ .flags = IORESOURCE_DMA, -+ }, -+ { -+ .name = "tx", -+ .start = OMAP_DMA_MCBSP2_TX, -+ .flags = IORESOURCE_DMA, -+ }, -+ }, -+ { -+ { -+ .start = OMAP1610_MCBSP3_BASE, -+ .end = OMAP1610_MCBSP3_BASE + SZ_256, -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .name = "rx", -+ .start = INT_McBSP3RX, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "tx", -+ .start = INT_McBSP3TX, -+ .flags = IORESOURCE_IRQ, -+ }, -+ { -+ .name = "rx", -+ .start = OMAP_DMA_MCBSP3_RX, -+ .flags = IORESOURCE_DMA, -+ }, -+ { -+ .name = "tx", -+ .start = OMAP_DMA_MCBSP3_TX, -+ .flags = IORESOURCE_DMA, -+ }, -+ }, -+}; -+ - static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { - { -- .phys_base = OMAP1610_MCBSP1_BASE, -- .dma_rx_sync = OMAP_DMA_MCBSP1_RX, -- .dma_tx_sync = OMAP_DMA_MCBSP1_TX, -- .rx_irq = INT_McBSP1RX, -- .tx_irq = INT_McBSP1TX, - .ops = &omap1_mcbsp_ops, - }, - { -- .phys_base = OMAP1610_MCBSP2_BASE, -- .dma_rx_sync = OMAP_DMA_MCBSP2_RX, -- .dma_tx_sync = OMAP_DMA_MCBSP2_TX, -- .rx_irq = INT_1610_McBSP2_RX, -- .tx_irq = INT_1610_McBSP2_TX, - .ops = &omap1_mcbsp_ops, - }, - { -- .phys_base = OMAP1610_MCBSP3_BASE, -- .dma_rx_sync = OMAP_DMA_MCBSP3_RX, -- .dma_tx_sync = OMAP_DMA_MCBSP3_TX, -- .rx_irq = INT_McBSP3RX, -- .tx_irq = INT_McBSP3TX, - .ops = &omap1_mcbsp_ops, - }, - }; --#define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata) --#define OMAP16XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) -+#define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1]) -+#define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res) - #else -+#define omap16xx_mcbsp_res NULL - #define omap16xx_mcbsp_pdata NULL --#define OMAP16XX_MCBSP_PDATA_SZ 0 --#define OMAP16XX_MCBSP_REG_NUM 0 -+#define OMAP16XX_MCBSP_RES_SZ 0 -+#define OMAP16XX_MCBSP_COUNT 0 - #endif - - static int __init omap1_mcbsp_init(void) -@@ -179,16 +368,12 @@ - if (!cpu_class_is_omap1()) - return -ENODEV; - -- if (cpu_is_omap7xx()) { -- omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ; -- omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16); -- } else if (cpu_is_omap15xx()) { -- omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ; -- omap_mcbsp_cache_size = OMAP15XX_MCBSP_REG_NUM * sizeof(u16); -- } else if (cpu_is_omap16xx()) { -- omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ; -- omap_mcbsp_cache_size = OMAP16XX_MCBSP_REG_NUM * sizeof(u16); -- } -+ if (cpu_is_omap7xx()) -+ omap_mcbsp_count = OMAP7XX_MCBSP_COUNT; -+ else if (cpu_is_omap15xx()) -+ omap_mcbsp_count = OMAP15XX_MCBSP_COUNT; -+ else if (cpu_is_omap16xx()) -+ omap_mcbsp_count = OMAP16XX_MCBSP_COUNT; - - mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), - GFP_KERNEL); -@@ -196,16 +381,22 @@ - return -ENOMEM; - - if (cpu_is_omap7xx()) -- omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata, -- OMAP7XX_MCBSP_PDATA_SZ); -+ omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res[0], -+ OMAP7XX_MCBSP_RES_SZ, -+ omap7xx_mcbsp_pdata, -+ OMAP7XX_MCBSP_COUNT); - - if (cpu_is_omap15xx()) -- omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata, -- OMAP15XX_MCBSP_PDATA_SZ); -+ omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res[0], -+ OMAP15XX_MCBSP_RES_SZ, -+ omap15xx_mcbsp_pdata, -+ OMAP15XX_MCBSP_COUNT); - - if (cpu_is_omap16xx()) -- omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata, -- OMAP16XX_MCBSP_PDATA_SZ); -+ omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res[0], -+ OMAP16XX_MCBSP_RES_SZ, -+ omap16xx_mcbsp_pdata, -+ OMAP16XX_MCBSP_COUNT); - - return omap_mcbsp_init(); - } -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap1/reset.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/reset.c ---- linux-2.6.38-rc7/arch/arm/mach-omap1/reset.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap1/reset.c 2011-03-09 13:19:09.791508008 +0100 -@@ -0,0 +1,25 @@ -+/* -+ * OMAP1 reset support -+ */ -+#include -+#include -+ -+#include -+#include -+#include -+ -+void omap1_arch_reset(char mode, const char *cmd) -+{ -+ /* -+ * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 -+ * "Global Software Reset Affects Traffic Controller Frequency". -+ */ -+ if (cpu_is_omap5912()) { -+ omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); -+ omap_writew(0x8, ARM_RSTCT1); -+ } -+ -+ omap_writew(1, ARM_RSTCT1); -+} -+ -+void (*arch_reset)(char, const char *) = omap1_arch_reset; -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-2430sdp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-2430sdp.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-2430sdp.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-2430sdp.c 2011-03-09 13:19:09.793507967 +0100 -@@ -22,6 +22,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -139,15 +140,31 @@ - {OMAP_TAG_LCD, &sdp2430_lcd_config}, - }; - --static void __init omap_2430sdp_init_irq(void) -+static void __init omap_2430sdp_init_early(void) - { -- omap_board_config = sdp2430_config; -- omap_board_config_size = ARRAY_SIZE(sdp2430_config); - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -- omap_init_irq(); - } - -+static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = { -+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), -+}; -+ -+/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ -+static struct regulator_init_data sdp2430_vmmc1 = { -+ .constraints = { -+ .min_uV = 1850000, -+ .max_uV = 3150000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL -+ | REGULATOR_MODE_STANDBY, -+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE -+ | REGULATOR_CHANGE_MODE -+ | REGULATOR_CHANGE_STATUS, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(sdp2430_vmmc1_supplies), -+ .consumer_supplies = &sdp2430_vmmc1_supplies[0], -+}; -+ - static struct twl4030_gpio_platform_data sdp2430_gpio_data = { - .gpio_base = OMAP_MAX_GPIO_LINES, - .irq_base = TWL4030_GPIO_IRQ_BASE, -@@ -160,6 +177,7 @@ - - /* platform_data for children goes here */ - .gpio = &sdp2430_gpio_data, -+ .vmmc1 = &sdp2430_vmmc1, - }; - - static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = { -@@ -226,6 +244,9 @@ - - omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC); - -+ omap_board_config = sdp2430_config; -+ omap_board_config_size = ARRAY_SIZE(sdp2430_config); -+ - omap2430_i2c_init(); - - platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); -@@ -253,9 +274,10 @@ - MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") - /* Maintainer: Syed Khasim - Texas Instruments Inc */ - .boot_params = 0x80000100, -- .map_io = omap_2430sdp_map_io, - .reserve = omap_reserve, -- .init_irq = omap_2430sdp_init_irq, -+ .map_io = omap_2430sdp_map_io, -+ .init_early = omap_2430sdp_init_early, -+ .init_irq = omap_init_irq, - .init_machine = omap_2430sdp_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-3430sdp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-3430sdp.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-3430sdp.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-3430sdp.c 2011-03-09 13:19:09.793507967 +0100 -@@ -307,34 +307,13 @@ - .default_device = &sdp3430_lcd_device, - }; - --static struct platform_device sdp3430_dss_device = { -- .name = "omapdss", -- .id = -1, -- .dev = { -- .platform_data = &sdp3430_dss_data, -- }, --}; -- --static struct regulator_consumer_supply sdp3430_vdda_dac_supply = { -- .supply = "vdda_dac", -- .dev = &sdp3430_dss_device.dev, --}; -- --static struct platform_device *sdp3430_devices[] __initdata = { -- &sdp3430_dss_device, --}; -- - static struct omap_board_config_kernel sdp3430_config[] __initdata = { - }; - --static void __init omap_3430sdp_init_irq(void) -+static void __init omap_3430sdp_init_early(void) - { -- omap_board_config = sdp3430_config; -- omap_board_config_size = ARRAY_SIZE(sdp3430_config); -- omap3_pm_init_cpuidle(omap3_cpuidle_params_table); - omap2_init_common_infrastructure(); - omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL); -- omap_init_irq(); - } - - static int sdp3430_batt_table[] = { -@@ -370,18 +349,6 @@ - {} /* Terminator */ - }; - --static struct regulator_consumer_supply sdp3430_vmmc1_supply = { -- .supply = "vmmc", --}; -- --static struct regulator_consumer_supply sdp3430_vsim_supply = { -- .supply = "vmmc_aux", --}; -- --static struct regulator_consumer_supply sdp3430_vmmc2_supply = { -- .supply = "vmmc", --}; -- - static int sdp3430_twl_gpio_setup(struct device *dev, - unsigned gpio, unsigned ngpio) - { -@@ -392,13 +359,6 @@ - mmc[1].gpio_cd = gpio + 1; - omap2_hsmmc_init(mmc); - -- /* link regulators to MMC adapters ... we "know" the -- * regulators will be set up only *after* we return. -- */ -- sdp3430_vmmc1_supply.dev = mmc[0].dev; -- sdp3430_vsim_supply.dev = mmc[0].dev; -- sdp3430_vmmc2_supply.dev = mmc[1].dev; -- - /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */ - gpio_request(gpio + 7, "sub_lcd_en_bkl"); - gpio_direction_output(gpio + 7, 0); -@@ -427,6 +387,35 @@ - .irq_line = 1, - }; - -+/* regulator consumer mappings */ -+ -+/* ads7846 on SPI */ -+static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = { -+ REGULATOR_SUPPLY("vcc", "spi1.0"), -+}; -+ -+static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = { -+ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"), -+}; -+ -+/* VPLL2 for digital video outputs */ -+static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = { -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss"), -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), -+}; -+ -+static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = { -+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), -+}; -+ -+static struct regulator_consumer_supply sdp3430_vsim_supplies[] = { -+ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"), -+}; -+ -+static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = { -+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), -+}; -+ - /* - * Apply all the fixed voltages since most versions of U-Boot - * don't bother with that initialization. -@@ -469,6 +458,8 @@ - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -+ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies), -+ .consumer_supplies = sdp3430_vaux3_supplies, - }; - - /* VAUX4 for OMAP VDD_CSI2 (camera) */ -@@ -495,8 +486,8 @@ - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -- .num_consumer_supplies = 1, -- .consumer_supplies = &sdp3430_vmmc1_supply, -+ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies), -+ .consumer_supplies = sdp3430_vmmc1_supplies, - }; - - /* VMMC2 for MMC2 card */ -@@ -510,8 +501,8 @@ - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -- .num_consumer_supplies = 1, -- .consumer_supplies = &sdp3430_vmmc2_supply, -+ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies), -+ .consumer_supplies = sdp3430_vmmc2_supplies, - }; - - /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ -@@ -525,8 +516,8 @@ - | REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -- .num_consumer_supplies = 1, -- .consumer_supplies = &sdp3430_vsim_supply, -+ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies), -+ .consumer_supplies = sdp3430_vsim_supplies, - }; - - /* VDAC for DSS driving S-Video */ -@@ -540,16 +531,8 @@ - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -- .num_consumer_supplies = 1, -- .consumer_supplies = &sdp3430_vdda_dac_supply, --}; -- --/* VPLL2 for digital video outputs */ --static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = { -- { -- .supply = "vdds_dsi", -- .dev = &sdp3430_dss_device.dev, -- } -+ .num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies), -+ .consumer_supplies = sdp3430_vdda_dac_supplies, - }; - - static struct regulator_init_data sdp3430_vpll2 = { -@@ -567,9 +550,7 @@ - .consumer_supplies = sdp3430_vpll2_supplies, - }; - --static struct twl4030_codec_audio_data sdp3430_audio = { -- .audio_mclk = 26000000, --}; -+static struct twl4030_codec_audio_data sdp3430_audio; - - static struct twl4030_codec_data sdp3430_codec = { - .audio_mclk = 26000000, -@@ -800,8 +781,11 @@ - static void __init omap_3430sdp_init(void) - { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); -+ omap_board_config = sdp3430_config; -+ omap_board_config_size = ARRAY_SIZE(sdp3430_config); -+ omap3_pm_init_cpuidle(omap3_cpuidle_params_table); - omap3430_i2c_init(); -- platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices)); -+ omap_display_init(&sdp3430_dss_data); - if (omap_rev() > OMAP3430_REV_ES1_0) - ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2; - else -@@ -813,7 +797,7 @@ - omap_serial_init(); - usb_musb_init(&musb_board_data); - board_smc91x_init(); -- board_flash_init(sdp_flash_partitions, chip_sel_3430); -+ board_flash_init(sdp_flash_partitions, chip_sel_3430, 0); - sdp3430_display_init(); - enable_board_wakeup_source(); - usb_ehci_init(&ehci_pdata); -@@ -822,9 +806,10 @@ - MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") - /* Maintainer: Syed Khasim - Texas Instruments Inc */ - .boot_params = 0x80000100, -- .map_io = omap3_map_io, - .reserve = omap_reserve, -- .init_irq = omap_3430sdp_init_irq, -+ .map_io = omap3_map_io, -+ .init_early = omap_3430sdp_init_early, -+ .init_irq = omap_init_irq, - .init_machine = omap_3430sdp_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-3630sdp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-3630sdp.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-3630sdp.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-3630sdp.c 2011-03-09 13:19:09.793507967 +0100 -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -69,14 +70,11 @@ - static struct omap_board_config_kernel sdp_config[] __initdata = { - }; - --static void __init omap_sdp_init_irq(void) -+static void __init omap_sdp_init_early(void) - { -- omap_board_config = sdp_config; -- omap_board_config_size = ARRAY_SIZE(sdp_config); - omap2_init_common_infrastructure(); - omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params, - h8mbx00u0mer0em_sdrc_params); -- omap_init_irq(); - } - - #ifdef CONFIG_OMAP_MUX -@@ -206,19 +204,22 @@ - static void __init omap_sdp_init(void) - { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); -+ omap_board_config = sdp_config; -+ omap_board_config_size = ARRAY_SIZE(sdp_config); - zoom_peripherals_init(); - zoom_display_init(); - board_smc91x_init(); -- board_flash_init(sdp_flash_partitions, chip_sel_sdp); -+ board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16); - enable_board_wakeup_source(); - usb_ehci_init(&ehci_pdata); - } - - MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board") - .boot_params = 0x80000100, -- .map_io = omap3_map_io, - .reserve = omap_reserve, -- .init_irq = omap_sdp_init_irq, -+ .map_io = omap3_map_io, -+ .init_early = omap_sdp_init_early, -+ .init_irq = omap_init_irq, - .init_machine = omap_sdp_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-4430sdp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-4430sdp.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-4430sdp.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-4430sdp.c 2011-03-09 13:19:09.794507946 +0100 -@@ -35,6 +35,7 @@ - #include - #include - #include -+#include - - #include "mux.h" - #include "hsmmc.h" -@@ -44,10 +45,93 @@ - #define ETH_KS8851_IRQ 34 - #define ETH_KS8851_POWER_ON 48 - #define ETH_KS8851_QUART 138 --#define OMAP4SDP_MDM_PWR_EN_GPIO 157 - #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 - #define OMAP4_SFH7741_ENABLE_GPIO 188 - -+static const int sdp4430_keymap[] = { -+ KEY(0, 0, KEY_E), -+ KEY(0, 1, KEY_R), -+ KEY(0, 2, KEY_T), -+ KEY(0, 3, KEY_HOME), -+ KEY(0, 4, KEY_F5), -+ KEY(0, 5, KEY_UNKNOWN), -+ KEY(0, 6, KEY_I), -+ KEY(0, 7, KEY_LEFTSHIFT), -+ -+ KEY(1, 0, KEY_D), -+ KEY(1, 1, KEY_F), -+ KEY(1, 2, KEY_G), -+ KEY(1, 3, KEY_SEND), -+ KEY(1, 4, KEY_F6), -+ KEY(1, 5, KEY_UNKNOWN), -+ KEY(1, 6, KEY_K), -+ KEY(1, 7, KEY_ENTER), -+ -+ KEY(2, 0, KEY_X), -+ KEY(2, 1, KEY_C), -+ KEY(2, 2, KEY_V), -+ KEY(2, 3, KEY_END), -+ KEY(2, 4, KEY_F7), -+ KEY(2, 5, KEY_UNKNOWN), -+ KEY(2, 6, KEY_DOT), -+ KEY(2, 7, KEY_CAPSLOCK), -+ -+ KEY(3, 0, KEY_Z), -+ KEY(3, 1, KEY_KPPLUS), -+ KEY(3, 2, KEY_B), -+ KEY(3, 3, KEY_F1), -+ KEY(3, 4, KEY_F8), -+ KEY(3, 5, KEY_UNKNOWN), -+ KEY(3, 6, KEY_O), -+ KEY(3, 7, KEY_SPACE), -+ -+ KEY(4, 0, KEY_W), -+ KEY(4, 1, KEY_Y), -+ KEY(4, 2, KEY_U), -+ KEY(4, 3, KEY_F2), -+ KEY(4, 4, KEY_VOLUMEUP), -+ KEY(4, 5, KEY_UNKNOWN), -+ KEY(4, 6, KEY_L), -+ KEY(4, 7, KEY_LEFT), -+ -+ KEY(5, 0, KEY_S), -+ KEY(5, 1, KEY_H), -+ KEY(5, 2, KEY_J), -+ KEY(5, 3, KEY_F3), -+ KEY(5, 4, KEY_F9), -+ KEY(5, 5, KEY_VOLUMEDOWN), -+ KEY(5, 6, KEY_M), -+ KEY(5, 7, KEY_RIGHT), -+ -+ KEY(6, 0, KEY_Q), -+ KEY(6, 1, KEY_A), -+ KEY(6, 2, KEY_N), -+ KEY(6, 3, KEY_BACK), -+ KEY(6, 4, KEY_BACKSPACE), -+ KEY(6, 5, KEY_UNKNOWN), -+ KEY(6, 6, KEY_P), -+ KEY(6, 7, KEY_UP), -+ -+ KEY(7, 0, KEY_PROG1), -+ KEY(7, 1, KEY_PROG2), -+ KEY(7, 2, KEY_PROG3), -+ KEY(7, 3, KEY_PROG4), -+ KEY(7, 4, KEY_F4), -+ KEY(7, 5, KEY_UNKNOWN), -+ KEY(7, 6, KEY_OK), -+ KEY(7, 7, KEY_DOWN), -+}; -+ -+static struct matrix_keymap_data sdp4430_keymap_data = { -+ .keymap = sdp4430_keymap, -+ .keymap_size = ARRAY_SIZE(sdp4430_keymap), -+}; -+ -+static struct omap4_keypad_platform_data sdp4430_keypad_data = { -+ .keymap_data = &sdp4430_keymap_data, -+ .rows = 8, -+ .cols = 8, -+}; - static struct gpio_led sdp4430_gpio_leds[] = { - { - .name = "omap4:green:debug0", -@@ -239,28 +323,15 @@ - { OMAP_TAG_LCD, &sdp4430_lcd_config }, - }; - --static void __init omap_4430sdp_init_irq(void) -+static void __init omap_4430sdp_init_early(void) - { -- omap_board_config = sdp4430_config; -- omap_board_config_size = ARRAY_SIZE(sdp4430_config); - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); - #ifdef CONFIG_OMAP_32K_TIMER - omap2_gp_clockevent_set_gptimer(1); - #endif -- gic_init_irq(); - } - --static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { -- .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, -- .port_mode[1] = EHCI_HCD_OMAP_MODE_UNKNOWN, -- .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, -- .phy_reset = false, -- .reset_gpio_port[0] = -EINVAL, -- .reset_gpio_port[1] = -EINVAL, -- .reset_gpio_port[2] = -EINVAL, --}; -- - static struct omap_musb_board_data musb_board_data = { - .interface_type = MUSB_INTERFACE_UTMI, - .mode = MUSB_OTG, -@@ -276,11 +347,6 @@ - - static struct omap2_hsmmc_info mmc[] = { - { -- .mmc = 1, -- .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, -- .gpio_wp = -EINVAL, -- }, -- { - .mmc = 2, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, - .gpio_cd = -EINVAL, -@@ -288,19 +354,24 @@ - .nonremovable = true, - .ocr_mask = MMC_VDD_29_30, - }, -+ { -+ .mmc = 1, -+ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, -+ .gpio_wp = -EINVAL, -+ }, - {} /* Terminator */ - }; - - static struct regulator_consumer_supply sdp4430_vaux_supply[] = { - { - .supply = "vmmc", -- .dev_name = "mmci-omap-hs.1", -+ .dev_name = "omap_hsmmc.1", - }, - }; - static struct regulator_consumer_supply sdp4430_vmmc_supply[] = { - { - .supply = "vmmc", -- .dev_name = "mmci-omap-hs.0", -+ .dev_name = "omap_hsmmc.0", - }, - }; - -@@ -434,7 +505,6 @@ - .constraints = { - .min_uV = 2100000, - .max_uV = 2100000, -- .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE -@@ -446,7 +516,6 @@ - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, -- .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE -@@ -458,7 +527,6 @@ - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, -- .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE -@@ -570,20 +638,15 @@ - package = OMAP_PACKAGE_CBL; - omap4_mux_init(board_mux, package); - -+ omap_board_config = sdp4430_config; -+ omap_board_config_size = ARRAY_SIZE(sdp4430_config); -+ - omap4_i2c_init(); - omap_sfh7741prox_init(); - platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); - omap_serial_init(); - omap4_twl6030_hsmmc_init(mmc); - -- /* Power on the ULPI PHY */ -- status = gpio_request(OMAP4SDP_MDM_PWR_EN_GPIO, "USBB1 PHY VMDM_3V3"); -- if (status) -- pr_err("%s: Could not get USBB1 PHY GPIO\n", __func__); -- else -- gpio_direction_output(OMAP4SDP_MDM_PWR_EN_GPIO, 1); -- -- usb_ehci_init(&ehci_pdata); - usb_musb_init(&musb_board_data); - - status = omap_ethernet_init(); -@@ -594,6 +657,10 @@ - spi_register_board_info(sdp4430_spi_board_info, - ARRAY_SIZE(sdp4430_spi_board_info)); - } -+ -+ status = omap4_keyboard_init(&sdp4430_keypad_data); -+ if (status) -+ pr_err("Keypad initialization failed: %d\n", status); - } - - static void __init omap_4430sdp_map_io(void) -@@ -605,9 +672,10 @@ - MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") - /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */ - .boot_params = 0x80000100, -- .map_io = omap_4430sdp_map_io, - .reserve = omap_reserve, -- .init_irq = omap_4430sdp_init_irq, -+ .map_io = omap_4430sdp_map_io, -+ .init_early = omap_4430sdp_init_early, -+ .init_irq = gic_init_irq, - .init_machine = omap_4430sdp_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-am3517crane.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-am3517crane.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-am3517crane.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-am3517crane.c 2011-03-09 13:19:09.794507946 +0100 -@@ -49,14 +49,10 @@ - #define board_mux NULL - #endif - --static void __init am3517_crane_init_irq(void) -+static void __init am3517_crane_init_early(void) - { -- omap_board_config = am3517_crane_config; -- omap_board_config_size = ARRAY_SIZE(am3517_crane_config); -- - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -- omap_init_irq(); - } - - static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { -@@ -77,6 +73,9 @@ - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap_serial_init(); - -+ omap_board_config = am3517_crane_config; -+ omap_board_config_size = ARRAY_SIZE(am3517_crane_config); -+ - /* Configure GPIO for EHCI port */ - if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) { - pr_err("Can not configure mux for GPIO_USB_NRESET %d\n", -@@ -108,9 +107,10 @@ - - MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") - .boot_params = 0x80000100, -- .map_io = omap3_map_io, - .reserve = omap_reserve, -- .init_irq = am3517_crane_init_irq, -+ .map_io = omap3_map_io, -+ .init_early = am3517_crane_init_early, -+ .init_irq = omap_init_irq, - .init_machine = am3517_crane_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-am3517evm.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-am3517evm.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-am3517evm.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-am3517evm.c 2011-03-09 13:19:09.794507946 +0100 -@@ -378,37 +378,23 @@ - .default_device = &am3517_evm_lcd_device, - }; - --static struct platform_device am3517_evm_dss_device = { -- .name = "omapdss", -- .id = -1, -- .dev = { -- .platform_data = &am3517_evm_dss_data, -- }, --}; -- - /* - * Board initialization - */ --static struct omap_board_config_kernel am3517_evm_config[] __initdata = { --}; -- --static struct platform_device *am3517_evm_devices[] __initdata = { -- &am3517_evm_dss_device, --}; -- --static void __init am3517_evm_init_irq(void) -+static void __init am3517_evm_init_early(void) - { -- omap_board_config = am3517_evm_config; -- omap_board_config_size = ARRAY_SIZE(am3517_evm_config); - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -- omap_init_irq(); - } - - static struct omap_musb_board_data musb_board_data = { - .interface_type = MUSB_INTERFACE_ULPI, - .mode = MUSB_OTG, - .power = 500, -+ .set_phy_power = am35x_musb_phy_power, -+ .clear_irq = am35x_musb_clear_irq, -+ .set_mode = am35x_musb_set_mode, -+ .reset = am35x_musb_reset, - }; - - static __init void am3517_evm_musb_init(void) -@@ -490,14 +476,17 @@ - platform_device_register(&am3517_hecc_device); - } - -+static struct omap_board_config_kernel am3517_evm_config[] __initdata = { -+}; -+ - static void __init am3517_evm_init(void) - { -+ omap_board_config = am3517_evm_config; -+ omap_board_config_size = ARRAY_SIZE(am3517_evm_config); - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - - am3517_evm_i2c_init(); -- platform_add_devices(am3517_evm_devices, -- ARRAY_SIZE(am3517_evm_devices)); -- -+ omap_display_init(&am3517_evm_dss_data); - omap_serial_init(); - - /* Configure GPIO for EHCI port */ -@@ -521,9 +510,10 @@ - - MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") - .boot_params = 0x80000100, -- .map_io = omap3_map_io, - .reserve = omap_reserve, -- .init_irq = am3517_evm_init_irq, -+ .map_io = omap3_map_io, -+ .init_early = am3517_evm_init_early, -+ .init_irq = omap_init_irq, - .init_machine = am3517_evm_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-apollon.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-apollon.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-apollon.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-apollon.c 2011-03-09 13:19:09.794507946 +0100 -@@ -274,13 +274,10 @@ - { OMAP_TAG_LCD, &apollon_lcd_config }, - }; - --static void __init omap_apollon_init_irq(void) -+static void __init omap_apollon_init_early(void) - { -- omap_board_config = apollon_config; -- omap_board_config_size = ARRAY_SIZE(apollon_config); - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -- omap_init_irq(); - } - - static void __init apollon_led_init(void) -@@ -320,6 +317,8 @@ - u32 v; - - omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); -+ omap_board_config = apollon_config; -+ omap_board_config_size = ARRAY_SIZE(apollon_config); - - apollon_init_smc91x(); - apollon_led_init(); -@@ -355,9 +354,10 @@ - MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") - /* Maintainer: Kyungmin Park */ - .boot_params = 0x80000100, -- .map_io = omap_apollon_map_io, - .reserve = omap_reserve, -- .init_irq = omap_apollon_init_irq, -+ .map_io = omap_apollon_map_io, -+ .init_early = omap_apollon_init_early, -+ .init_irq = omap_init_irq, - .init_machine = omap_apollon_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-cm-t3517.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-cm-t3517.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-cm-t3517.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-cm-t3517.c 2011-03-09 13:19:09.795507925 +0100 -@@ -254,14 +254,10 @@ - static struct omap_board_config_kernel cm_t3517_config[] __initdata = { - }; - --static void __init cm_t3517_init_irq(void) -+static void __init cm_t3517_init_early(void) - { -- omap_board_config = cm_t3517_config; -- omap_board_config_size = ARRAY_SIZE(cm_t3517_config); -- - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -- omap_init_irq(); - } - - static struct omap_board_mux board_mux[] __initdata = { -@@ -294,6 +290,8 @@ - { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - omap_serial_init(); -+ omap_board_config = cm_t3517_config; -+ omap_board_config_size = ARRAY_SIZE(cm_t3517_config); - cm_t3517_init_leds(); - cm_t3517_init_nand(); - cm_t3517_init_rtc(); -@@ -303,9 +301,10 @@ - - MACHINE_START(CM_T3517, "Compulab CM-T3517") - .boot_params = 0x80000100, -- .map_io = omap3_map_io, - .reserve = omap_reserve, -- .init_irq = cm_t3517_init_irq, -+ .map_io = omap3_map_io, -+ .init_early = cm_t3517_init_early, -+ .init_irq = omap_init_irq, - .init_machine = cm_t3517_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-cm-t35.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-cm-t35.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-cm-t35.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-cm-t35.c 2011-03-09 13:19:09.795507925 +0100 -@@ -401,14 +401,6 @@ - .default_device = &cm_t35_dvi_device, - }; - --static struct platform_device cm_t35_dss_device = { -- .name = "omapdss", -- .id = -1, -- .dev = { -- .platform_data = &cm_t35_dss_data, -- }, --}; -- - static struct omap2_mcspi_device_config tdo24m_mcspi_config = { - .turbo_mode = 0, - .single_channel = 1, /* 0: slave, 1: master */ -@@ -468,7 +460,7 @@ - msleep(50); - gpio_set_value(lcd_en_gpio, 1); - -- err = platform_device_register(&cm_t35_dss_device); -+ err = omap_display_init(&cm_t35_dss_data); - if (err) { - pr_err("CM-T35: failed to register DSS device\n"); - goto err_dev_reg; -@@ -495,15 +487,11 @@ - .supply = "vmmc_aux", - }; - --static struct regulator_consumer_supply cm_t35_vdac_supply = { -- .supply = "vdda_dac", -- .dev = &cm_t35_dss_device.dev, --}; -+static struct regulator_consumer_supply cm_t35_vdac_supply = -+ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); - --static struct regulator_consumer_supply cm_t35_vdvi_supply = { -- .supply = "vdvi", -- .dev = &cm_t35_dss_device.dev, --}; -+static struct regulator_consumer_supply cm_t35_vdvi_supply = -+ REGULATOR_SUPPLY("vdvi", "omapdss"); - - /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ - static struct regulator_init_data cm_t35_vmmc1 = { -@@ -680,18 +668,11 @@ - ARRAY_SIZE(cm_t35_i2c_boardinfo)); - } - --static struct omap_board_config_kernel cm_t35_config[] __initdata = { --}; -- --static void __init cm_t35_init_irq(void) -+static void __init cm_t35_init_early(void) - { -- omap_board_config = cm_t35_config; -- omap_board_config_size = ARRAY_SIZE(cm_t35_config); -- - omap2_init_common_infrastructure(); - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); -- omap_init_irq(); - } - - static struct omap_board_mux board_mux[] __initdata = { -@@ -798,8 +779,13 @@ - .power = 100, - }; - -+static struct omap_board_config_kernel cm_t35_config[] __initdata = { -+}; -+ - static void __init cm_t35_init(void) - { -+ omap_board_config = cm_t35_config; -+ omap_board_config_size = ARRAY_SIZE(cm_t35_config); - omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); - omap_serial_init(); - cm_t35_init_i2c(); -@@ -815,9 +801,10 @@ - - MACHINE_START(CM_T35, "Compulab CM-T35") - .boot_params = 0x80000100, -- .map_io = omap3_map_io, - .reserve = omap_reserve, -- .init_irq = cm_t35_init_irq, -+ .map_io = omap3_map_io, -+ .init_early = cm_t35_init_early, -+ .init_irq = omap_init_irq, - .init_machine = cm_t35_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-devkit8000.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-devkit8000.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-devkit8000.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-devkit8000.c 2011-03-09 13:19:09.795507925 +0100 -@@ -140,7 +140,7 @@ - } - - static struct regulator_consumer_supply devkit8000_vmmc1_supply = -- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); -+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); - - - /* ads7846 on SPI */ -@@ -195,16 +195,8 @@ - .default_device = &devkit8000_lcd_device, - }; - --static struct platform_device devkit8000_dss_device = { -- .name = "omapdss", -- .id = -1, -- .dev = { -- .platform_data = &devkit8000_dss_data, -- }, --}; -- - static struct regulator_consumer_supply devkit8000_vdda_dac_supply = -- REGULATOR_SUPPLY("vdda_dac", "omapdss"); -+ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); - - static uint32_t board_keymap[] = { - KEY(0, 0, KEY_1), -@@ -285,8 +277,10 @@ - .setup = devkit8000_twl_gpio_setup, - }; - --static struct regulator_consumer_supply devkit8000_vpll1_supply = -- REGULATOR_SUPPLY("vdds_dsi", "omapdss"); -+static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = { -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss"), -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), -+}; - - /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ - static struct regulator_init_data devkit8000_vmmc1 = { -@@ -327,8 +321,8 @@ - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -- .num_consumer_supplies = 1, -- .consumer_supplies = &devkit8000_vpll1_supply, -+ .num_consumer_supplies = ARRAY_SIZE(devkit8000_vpll1_supplies), -+ .consumer_supplies = devkit8000_vpll1_supplies, - }; - - /* VAUX4 for ads7846 and nubs */ -@@ -350,9 +344,7 @@ - .usb_mode = T2_USB_MODE_ULPI, - }; - --static struct twl4030_codec_audio_data devkit8000_audio_data = { -- .audio_mclk = 26000000, --}; -+static struct twl4030_codec_audio_data devkit8000_audio_data; - - static struct twl4030_codec_data devkit8000_codec_data = { - .audio_mclk = 26000000, -@@ -456,11 +448,15 @@ - }; - - --static void __init devkit8000_init_irq(void) -+static void __init devkit8000_init_early(void) - { - omap2_init_common_infrastructure(); - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); -+} -+ -+static void __init devkit8000_init_irq(void) -+{ - omap_init_irq(); - #ifdef CONFIG_OMAP_32K_TIMER - omap2_gp_clockevent_set_gptimer(12); -@@ -575,7 +571,6 @@ - } - - static struct platform_device *devkit8000_devices[] __initdata = { -- &devkit8000_dss_device, - &leds_gpio, - &keys_gpio, - &omap_dm9000_dev, -@@ -797,6 +792,7 @@ - platform_add_devices(devkit8000_devices, - ARRAY_SIZE(devkit8000_devices)); - -+ omap_display_init(&devkit8000_dss_data); - spi_register_board_info(devkit8000_spi_board_info, - ARRAY_SIZE(devkit8000_spi_board_info)); - -@@ -813,8 +809,9 @@ - - MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000") - .boot_params = 0x80000100, -- .map_io = omap3_map_io, - .reserve = omap_reserve, -+ .map_io = omap3_map_io, -+ .init_early = devkit8000_init_early, - .init_irq = devkit8000_init_irq, - .init_machine = devkit8000_init, - .timer = &omap_timer, -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-flash.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-flash.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-flash.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-flash.c 2011-03-09 13:19:09.796507904 +0100 -@@ -1,5 +1,5 @@ - /* -- * board-sdp-flash.c -+ * board-flash.c - * Modified from mach-omap2/board-3430sdp-flash.c - * - * Copyright (C) 2009 Nokia Corporation -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -73,11 +74,11 @@ - + FLASH_SIZE_SDPV1 - 1; - } - if (err < 0) { -- printk(KERN_ERR "NOR: Can't request GPMC CS\n"); -+ pr_err("NOR: Can't request GPMC CS\n"); - return; - } - if (platform_device_register(&board_nor_device) < 0) -- printk(KERN_ERR "Unable to register NOR device\n"); -+ pr_err("Unable to register NOR device\n"); - } - - #if defined(CONFIG_MTD_ONENAND_OMAP2) || \ -@@ -139,17 +140,21 @@ - }; - - void --__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) -+__init board_nand_init(struct mtd_partition *nand_parts, -+ u8 nr_parts, u8 cs, int nand_type) - { - board_nand_data.cs = cs; - board_nand_data.parts = nand_parts; -- board_nand_data.nr_parts = nr_parts; -+ board_nand_data.nr_parts = nr_parts; -+ board_nand_data.devsize = nand_type; - -+ board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT; -+ board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs; - gpmc_nand_init(&board_nand_data); - } - #else - void --__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) -+__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, int nand_type) - { - } - #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ -@@ -189,12 +194,12 @@ - } - - /** -- * sdp3430_flash_init - Identify devices connected to GPMC and register. -+ * board_flash_init - Identify devices connected to GPMC and register. - * - * @return - void. - */ - void board_flash_init(struct flash_partitions partition_info[], -- char chip_sel_board[][GPMC_CS_NUM]) -+ char chip_sel_board[][GPMC_CS_NUM], int nand_type) - { - u8 cs = 0; - u8 norcs = GPMC_CS_NUM + 1; -@@ -208,7 +213,7 @@ - */ - idx = get_gpmc0_type(); - if (idx >= MAX_SUPPORTED_GPMC_CONFIG) { -- printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs); -+ pr_err("%s: Invalid chip select: %d\n", __func__, cs); - return; - } - config_sel = (unsigned char *)(chip_sel_board[idx]); -@@ -232,23 +237,20 @@ - } - - if (norcs > GPMC_CS_NUM) -- printk(KERN_INFO "NOR: Unable to find configuration " -- "in GPMC\n"); -+ pr_err("NOR: Unable to find configuration in GPMC\n"); - else - board_nor_init(partition_info[0].parts, - partition_info[0].nr_parts, norcs); - - if (onenandcs > GPMC_CS_NUM) -- printk(KERN_INFO "OneNAND: Unable to find configuration " -- "in GPMC\n"); -+ pr_err("OneNAND: Unable to find configuration in GPMC\n"); - else - board_onenand_init(partition_info[1].parts, - partition_info[1].nr_parts, onenandcs); - - if (nandcs > GPMC_CS_NUM) -- printk(KERN_INFO "NAND: Unable to find configuration " -- "in GPMC\n"); -+ pr_err("NAND: Unable to find configuration in GPMC\n"); - else - board_nand_init(partition_info[2].parts, -- partition_info[2].nr_parts, nandcs); -+ partition_info[2].nr_parts, nandcs, nand_type); - } -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-flash.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-flash.h ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-flash.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-flash.h 2011-03-09 13:19:09.796507904 +0100 -@@ -25,6 +25,6 @@ - }; - - extern void board_flash_init(struct flash_partitions [], -- char chip_sel[][GPMC_CS_NUM]); -+ char chip_sel[][GPMC_CS_NUM], int nand_type); - extern void board_nand_init(struct mtd_partition *nand_parts, -- u8 nr_parts, u8 cs); -+ u8 nr_parts, u8 cs, int nand_type); -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-generic.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-generic.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-generic.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-generic.c 2011-03-09 13:19:09.796507904 +0100 -@@ -33,18 +33,17 @@ - static struct omap_board_config_kernel generic_config[] = { - }; - --static void __init omap_generic_init_irq(void) -+static void __init omap_generic_init_early(void) - { -- omap_board_config = generic_config; -- omap_board_config_size = ARRAY_SIZE(generic_config); - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -- omap_init_irq(); - } - - static void __init omap_generic_init(void) - { - omap_serial_init(); -+ omap_board_config = generic_config; -+ omap_board_config_size = ARRAY_SIZE(generic_config); - } - - static void __init omap_generic_map_io(void) -@@ -68,9 +67,10 @@ - MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") - /* Maintainer: Paul Mundt */ - .boot_params = 0x80000100, -- .map_io = omap_generic_map_io, - .reserve = omap_reserve, -- .init_irq = omap_generic_init_irq, -+ .map_io = omap_generic_map_io, -+ .init_early = omap_generic_init_early, -+ .init_irq = omap_init_irq, - .init_machine = omap_generic_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-h4.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-h4.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-h4.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-h4.c 2011-03-09 13:19:09.796507904 +0100 -@@ -290,12 +290,14 @@ - { OMAP_TAG_LCD, &h4_lcd_config }, - }; - --static void __init omap_h4_init_irq(void) -+static void __init omap_h4_init_early(void) - { -- omap_board_config = h4_config; -- omap_board_config_size = ARRAY_SIZE(h4_config); - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -+} -+ -+static void __init omap_h4_init_irq(void) -+{ - omap_init_irq(); - h4_init_flash(); - } -@@ -330,6 +332,9 @@ - { - omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF); - -+ omap_board_config = h4_config; -+ omap_board_config_size = ARRAY_SIZE(h4_config); -+ - /* - * Make sure the serial ports are muxed on at this point. - * You have to mux them off in device drivers later on -@@ -378,8 +383,9 @@ - MACHINE_START(OMAP_H4, "OMAP2420 H4 board") - /* Maintainer: Paul Mundt */ - .boot_params = 0x80000100, -- .map_io = omap_h4_map_io, - .reserve = omap_reserve, -+ .map_io = omap_h4_map_io, -+ .init_early = omap_h4_init_early, - .init_irq = omap_h4_init_irq, - .init_machine = omap_h4_init, - .timer = &omap_timer, -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-igep0020.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-igep0020.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-igep0020.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-igep0020.c 2011-03-09 13:19:09.796507904 +0100 -@@ -250,7 +250,7 @@ - #endif - - static struct regulator_consumer_supply igep2_vmmc1_supply = -- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); -+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); - - /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ - static struct regulator_init_data igep2_vmmc1 = { -@@ -268,7 +268,7 @@ - }; - - static struct regulator_consumer_supply igep2_vio_supply = -- REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); -+ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"); - - static struct regulator_init_data igep2_vio = { - .constraints = { -@@ -286,7 +286,7 @@ - }; - - static struct regulator_consumer_supply igep2_vmmc2_supply = -- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); -+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); - - static struct regulator_init_data igep2_vmmc2 = { - .constraints = { -@@ -485,17 +485,9 @@ - .default_device = &igep2_dvi_device, - }; - --static struct platform_device igep2_dss_device = { -- .name = "omapdss", -- .id = -1, -- .dev = { -- .platform_data = &igep2_dss_data, -- }, --}; -- --static struct regulator_consumer_supply igep2_vpll2_supply = { -- .supply = "vdds_dsi", -- .dev = &igep2_dss_device.dev, -+static struct regulator_consumer_supply igep2_vpll2_supplies[] = { -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss"), -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), - }; - - static struct regulator_init_data igep2_vpll2 = { -@@ -509,8 +501,8 @@ - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -- .num_consumer_supplies = 1, -- .consumer_supplies = &igep2_vpll2_supply, -+ .num_consumer_supplies = ARRAY_SIZE(igep2_vpll2_supplies), -+ .consumer_supplies = igep2_vpll2_supplies, - }; - - static void __init igep2_display_init(void) -@@ -521,21 +513,17 @@ - } - - static struct platform_device *igep2_devices[] __initdata = { -- &igep2_dss_device, - &igep2_vwlan_device, - }; - --static void __init igep2_init_irq(void) -+static void __init igep2_init_early(void) - { - omap2_init_common_infrastructure(); - omap2_init_common_devices(m65kxxxxam_sdrc_params, - m65kxxxxam_sdrc_params); -- omap_init_irq(); - } - --static struct twl4030_codec_audio_data igep2_audio_data = { -- .audio_mclk = 26000000, --}; -+static struct twl4030_codec_audio_data igep2_audio_data; - - static struct twl4030_codec_data igep2_codec_data = { - .audio_mclk = 26000000, -@@ -697,6 +685,7 @@ - /* Register I2C busses and drivers */ - igep2_i2c_init(); - platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices)); -+ omap_display_init(&igep2_dss_data); - omap_serial_init(); - usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); -@@ -716,9 +705,10 @@ - - MACHINE_START(IGEP0020, "IGEP v2 board") - .boot_params = 0x80000100, -- .map_io = omap3_map_io, - .reserve = omap_reserve, -- .init_irq = igep2_init_irq, -+ .map_io = omap3_map_io, -+ .init_early = igep2_init_early, -+ .init_irq = omap_init_irq, - .init_machine = igep2_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-igep0030.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-igep0030.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-igep0030.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-igep0030.c 2011-03-09 13:19:09.797507884 +0100 -@@ -142,7 +142,7 @@ - #endif - - static struct regulator_consumer_supply igep3_vmmc1_supply = -- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); -+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); - - /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ - static struct regulator_init_data igep3_vmmc1 = { -@@ -160,7 +160,7 @@ - }; - - static struct regulator_consumer_supply igep3_vio_supply = -- REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); -+ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"); - - static struct regulator_init_data igep3_vio = { - .constraints = { -@@ -178,7 +178,7 @@ - }; - - static struct regulator_consumer_supply igep3_vmmc2_supply = -- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); -+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); - - static struct regulator_init_data igep3_vmmc2 = { - .constraints = { -@@ -331,12 +331,11 @@ - &igep3_vwlan_device, - }; - --static void __init igep3_init_irq(void) -+static void __init igep3_init_early(void) - { - omap2_init_common_infrastructure(); - omap2_init_common_devices(m65kxxxxam_sdrc_params, - m65kxxxxam_sdrc_params); -- omap_init_irq(); - } - - static struct twl4030_platform_data igep3_twl4030_pdata = { -@@ -452,7 +451,8 @@ - .boot_params = 0x80000100, - .reserve = omap_reserve, - .map_io = omap3_map_io, -- .init_irq = igep3_init_irq, -+ .init_early = igep3_init_early, -+ .init_irq = omap_init_irq, - .init_machine = igep3_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-ldp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-ldp.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-ldp.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-ldp.c 2011-03-09 13:19:09.797507884 +0100 -@@ -288,13 +288,10 @@ - { OMAP_TAG_LCD, &ldp_lcd_config }, - }; - --static void __init omap_ldp_init_irq(void) -+static void __init omap_ldp_init_early(void) - { -- omap_board_config = ldp_config; -- omap_board_config_size = ARRAY_SIZE(ldp_config); - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -- omap_init_irq(); - } - - static struct twl4030_usb_data ldp_usb_data = { -@@ -330,6 +327,26 @@ - .consumer_supplies = &ldp_vmmc1_supply, - }; - -+/* ads7846 on SPI */ -+static struct regulator_consumer_supply ldp_vaux1_supplies[] = { -+ REGULATOR_SUPPLY("vcc", "spi1.0"), -+}; -+ -+/* VAUX1 */ -+static struct regulator_init_data ldp_vaux1 = { -+ .constraints = { -+ .min_uV = 3000000, -+ .max_uV = 3000000, -+ .apply_uV = true, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL -+ | REGULATOR_MODE_STANDBY, -+ .valid_ops_mask = REGULATOR_CHANGE_MODE -+ | REGULATOR_CHANGE_STATUS, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(ldp_vaux1_supplies), -+ .consumer_supplies = ldp_vaux1_supplies, -+}; -+ - static struct twl4030_platform_data ldp_twldata = { - .irq_base = TWL4030_IRQ_BASE, - .irq_end = TWL4030_IRQ_END, -@@ -338,6 +355,7 @@ - .madc = &ldp_madc_data, - .usb = &ldp_usb_data, - .vmmc1 = &ldp_vmmc1, -+ .vaux1 = &ldp_vaux1, - .gpio = &ldp_gpio_data, - .keypad = &ldp_kp_twl4030_data, - }; -@@ -423,6 +441,8 @@ - static void __init omap_ldp_init(void) - { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); -+ omap_board_config = ldp_config; -+ omap_board_config_size = ARRAY_SIZE(ldp_config); - ldp_init_smsc911x(); - omap_i2c_init(); - platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices)); -@@ -434,7 +454,7 @@ - omap_serial_init(); - usb_musb_init(&musb_board_data); - board_nand_init(ldp_nand_partitions, -- ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS); -+ ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0); - - omap2_hsmmc_init(mmc); - /* link regulators to MMC adapters */ -@@ -443,9 +463,10 @@ - - MACHINE_START(OMAP_LDP, "OMAP LDP board") - .boot_params = 0x80000100, -- .map_io = omap3_map_io, - .reserve = omap_reserve, -- .init_irq = omap_ldp_init_irq, -+ .map_io = omap3_map_io, -+ .init_early = omap_ldp_init_early, -+ .init_irq = omap_init_irq, - .init_machine = omap_ldp_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-n8x0.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-n8x0.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-n8x0.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-n8x0.c 2011-03-09 13:19:09.797507884 +0100 -@@ -536,7 +536,7 @@ - } - - mmc_data[0] = &mmc1_data; -- omap2_init_mmc(mmc_data, OMAP24XX_NR_MMC); -+ omap242x_init_mmc(mmc_data); - } - #else - -@@ -628,11 +628,10 @@ - omap242x_map_common_io(); - } - --static void __init n8x0_init_irq(void) -+static void __init n8x0_init_early(void) - { - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -- omap_init_irq(); - } - - #ifdef CONFIG_OMAP_MUX -@@ -703,27 +702,30 @@ - - MACHINE_START(NOKIA_N800, "Nokia N800") - .boot_params = 0x80000100, -- .map_io = n8x0_map_io, - .reserve = omap_reserve, -- .init_irq = n8x0_init_irq, -+ .map_io = n8x0_map_io, -+ .init_early = n8x0_init_early, -+ .init_irq = omap_init_irq, - .init_machine = n8x0_init_machine, - .timer = &omap_timer, - MACHINE_END - - MACHINE_START(NOKIA_N810, "Nokia N810") - .boot_params = 0x80000100, -- .map_io = n8x0_map_io, - .reserve = omap_reserve, -- .init_irq = n8x0_init_irq, -+ .map_io = n8x0_map_io, -+ .init_early = n8x0_init_early, -+ .init_irq = omap_init_irq, - .init_machine = n8x0_init_machine, - .timer = &omap_timer, - MACHINE_END - - MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") - .boot_params = 0x80000100, -- .map_io = n8x0_map_io, - .reserve = omap_reserve, -- .init_irq = n8x0_init_irq, -+ .map_io = n8x0_map_io, -+ .init_early = n8x0_init_early, -+ .init_irq = omap_init_irq, - .init_machine = n8x0_init_machine, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3beagle.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3beagle.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3beagle.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3beagle.c 2011-03-09 13:19:09.797507884 +0100 -@@ -228,19 +228,13 @@ - .default_device = &beagle_dvi_device, - }; - --static struct platform_device beagle_dss_device = { -- .name = "omapdss", -- .id = -1, -- .dev = { -- .platform_data = &beagle_dss_data, -- }, --}; -- - static struct regulator_consumer_supply beagle_vdac_supply = -- REGULATOR_SUPPLY("vdda_dac", "omapdss"); -+ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); - --static struct regulator_consumer_supply beagle_vdvi_supply = -- REGULATOR_SUPPLY("vdds_dsi", "omapdss"); -+static struct regulator_consumer_supply beagle_vdvi_supplies[] = { -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss"), -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), -+}; - - static void __init beagle_display_init(void) - { -@@ -427,17 +421,15 @@ - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -- .num_consumer_supplies = 1, -- .consumer_supplies = &beagle_vdvi_supply, -+ .num_consumer_supplies = ARRAY_SIZE(beagle_vdvi_supplies), -+ .consumer_supplies = beagle_vdvi_supplies, - }; - - static struct twl4030_usb_data beagle_usb_data = { - .usb_mode = T2_USB_MODE_ULPI, - }; - --static struct twl4030_codec_audio_data beagle_audio_data = { -- .audio_mclk = 26000000, --}; -+static struct twl4030_codec_audio_data beagle_audio_data; - - static struct twl4030_codec_data beagle_codec_data = { - .audio_mclk = 26000000, -@@ -536,11 +528,15 @@ - }, - }; - --static void __init omap3_beagle_init_irq(void) -+static void __init omap3_beagle_init_early(void) - { - omap2_init_common_infrastructure(); - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); -+} -+ -+static void __init omap3_beagle_init_irq(void) -+{ - omap_init_irq(); - #ifdef CONFIG_OMAP_32K_TIMER - omap2_gp_clockevent_set_gptimer(12); -@@ -550,7 +546,6 @@ - static struct platform_device *omap3_beagle_devices[] __initdata = { - &leds_gpio, - &keys_gpio, -- &beagle_dss_device, - }; - - static void __init omap3beagle_flash_init(void) -@@ -617,6 +612,7 @@ - omap3_beagle_i2c_init(); - platform_add_devices(omap3_beagle_devices, - ARRAY_SIZE(omap3_beagle_devices)); -+ omap_display_init(&beagle_dss_data); - omap_serial_init(); - - omap_mux_init_gpio(170, OMAP_PIN_INPUT); -@@ -638,8 +634,9 @@ - MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") - /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */ - .boot_params = 0x80000100, -- .map_io = omap3_map_io, - .reserve = omap_reserve, -+ .map_io = omap3_map_io, -+ .init_early = omap3_beagle_init_early, - .init_irq = omap3_beagle_init_irq, - .init_machine = omap3_beagle_init, - .timer = &omap_timer, -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3evm.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3evm.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3evm.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3evm.c 2011-03-09 13:19:09.798507865 +0100 -@@ -30,6 +30,8 @@ - #include - #include - -+#include -+#include - #include - #include - -@@ -58,6 +60,13 @@ - #define OMAP3EVM_ETHR_ID_REV 0x50 - #define OMAP3EVM_ETHR_GPIO_IRQ 176 - #define OMAP3EVM_SMSC911X_CS 5 -+/* -+ * Eth Reset signal -+ * 64 = Generation 1 (<=RevD) -+ * 7 = Generation 2 (>=RevE) -+ */ -+#define OMAP3EVM_GEN1_ETHR_GPIO_RST 64 -+#define OMAP3EVM_GEN2_ETHR_GPIO_RST 7 - - static u8 omap3_evm_version; - -@@ -124,10 +133,15 @@ - - static inline void __init omap3evm_init_smsc911x(void) - { -- int eth_cs; -+ int eth_cs, eth_rst; - struct clk *l3ck; - unsigned int rate; - -+ if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) -+ eth_rst = OMAP3EVM_GEN1_ETHR_GPIO_RST; -+ else -+ eth_rst = OMAP3EVM_GEN2_ETHR_GPIO_RST; -+ - eth_cs = OMAP3EVM_SMSC911X_CS; - - l3ck = clk_get(NULL, "l3_ck"); -@@ -136,6 +150,27 @@ - else - rate = clk_get_rate(l3ck); - -+ /* Configure ethernet controller reset gpio */ -+ if (cpu_is_omap3430()) { -+ if (gpio_request(eth_rst, "SMSC911x gpio") < 0) { -+ pr_err(KERN_ERR "Failed to request %d for smsc911x\n", -+ eth_rst); -+ return; -+ } -+ -+ if (gpio_direction_output(eth_rst, 1) < 0) { -+ pr_err(KERN_ERR "Failed to set direction of %d for" \ -+ " smsc911x\n", eth_rst); -+ return; -+ } -+ /* reset pulse to ethernet controller*/ -+ usleep_range(150, 220); -+ gpio_set_value(eth_rst, 0); -+ usleep_range(150, 220); -+ gpio_set_value(eth_rst, 1); -+ usleep_range(1, 2); -+ } -+ - if (gpio_request(OMAP3EVM_ETHR_GPIO_IRQ, "SMSC911x irq") < 0) { - printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n", - OMAP3EVM_ETHR_GPIO_IRQ); -@@ -235,9 +270,9 @@ - gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0); - - if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) -- gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); -+ gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); - else -- gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); -+ gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); - - lcd_enabled = 1; - return 0; -@@ -248,9 +283,9 @@ - gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1); - - if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) -- gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); -+ gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1); - else -- gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); -+ gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0); - - lcd_enabled = 0; - } -@@ -289,7 +324,7 @@ - return -EINVAL; - } - -- gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 1); -+ gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1); - - dvi_enabled = 1; - return 0; -@@ -297,7 +332,7 @@ - - static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev) - { -- gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 0); -+ gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0); - - dvi_enabled = 0; - } -@@ -328,14 +363,6 @@ - .default_device = &omap3_evm_lcd_device, - }; - --static struct platform_device omap3_evm_dss_device = { -- .name = "omapdss", -- .id = -1, -- .dev = { -- .platform_data = &omap3_evm_dss_data, -- }, --}; -- - static struct regulator_consumer_supply omap3evm_vmmc1_supply = { - .supply = "vmmc", - }; -@@ -381,6 +408,16 @@ - .gpio_cd = -EINVAL, - .gpio_wp = 63, - }, -+#ifdef CONFIG_WL12XX_PLATFORM_DATA -+ { -+ .name = "wl1271", -+ .mmc = 2, -+ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, -+ .gpio_wp = -EINVAL, -+ .gpio_cd = -EINVAL, -+ .nonremovable = true, -+ }, -+#endif - {} /* Terminator */ - }; - -@@ -411,6 +448,8 @@ - static int omap3evm_twl_gpio_setup(struct device *dev, - unsigned gpio, unsigned ngpio) - { -+ int r; -+ - /* gpio + 0 is "mmc0_cd" (input/IRQ) */ - omap_mux_init_gpio(63, OMAP_PIN_INPUT); - mmc[0].gpio_cd = gpio + 0; -@@ -426,8 +465,12 @@ - */ - - /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */ -- gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL"); -- gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0); -+ r = gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL"); -+ if (!r) -+ r = gpio_direction_output(gpio + TWL4030_GPIO_MAX, -+ (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) ? 1 : 0); -+ if (r) -+ printk(KERN_ERR "failed to get/set lcd_bkl gpio\n"); - - /* gpio + 7 == DVI Enable */ - gpio_request(gpio + 7, "EN_DVI"); -@@ -491,19 +534,15 @@ - .irq_line = 1, - }; - --static struct twl4030_codec_audio_data omap3evm_audio_data = { -- .audio_mclk = 26000000, --}; -+static struct twl4030_codec_audio_data omap3evm_audio_data; - - static struct twl4030_codec_data omap3evm_codec_data = { - .audio_mclk = 26000000, - .audio = &omap3evm_audio_data, - }; - --static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = { -- .supply = "vdda_dac", -- .dev = &omap3_evm_dss_device.dev, --}; -+static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = -+ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); - - /* VDAC for DSS driving S-Video */ - static struct regulator_init_data omap3_evm_vdac = { -@@ -521,8 +560,10 @@ - }; - - /* VPLL2 for digital video outputs */ --static struct regulator_consumer_supply omap3_evm_vpll2_supply = -- REGULATOR_SUPPLY("vdds_dsi", "omapdss"); -+static struct regulator_consumer_supply omap3_evm_vpll2_supplies[] = { -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss"), -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), -+}; - - static struct regulator_init_data omap3_evm_vpll2 = { - .constraints = { -@@ -534,10 +575,70 @@ - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -+ .num_consumer_supplies = ARRAY_SIZE(omap3_evm_vpll2_supplies), -+ .consumer_supplies = omap3_evm_vpll2_supplies, -+}; -+ -+/* ads7846 on SPI */ -+static struct regulator_consumer_supply omap3evm_vio_supply = -+ REGULATOR_SUPPLY("vcc", "spi1.0"); -+ -+/* VIO for ads7846 */ -+static struct regulator_init_data omap3evm_vio = { -+ .constraints = { -+ .min_uV = 1800000, -+ .max_uV = 1800000, -+ .apply_uV = true, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL -+ | REGULATOR_MODE_STANDBY, -+ .valid_ops_mask = REGULATOR_CHANGE_MODE -+ | REGULATOR_CHANGE_STATUS, -+ }, - .num_consumer_supplies = 1, -- .consumer_supplies = &omap3_evm_vpll2_supply, -+ .consumer_supplies = &omap3evm_vio_supply, - }; - -+#ifdef CONFIG_WL12XX_PLATFORM_DATA -+ -+#define OMAP3EVM_WLAN_PMENA_GPIO (150) -+#define OMAP3EVM_WLAN_IRQ_GPIO (149) -+ -+static struct regulator_consumer_supply omap3evm_vmmc2_supply = -+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); -+ -+/* VMMC2 for driving the WL12xx module */ -+static struct regulator_init_data omap3evm_vmmc2 = { -+ .constraints = { -+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, -+ }, -+ .num_consumer_supplies = 1, -+ .consumer_supplies = &omap3evm_vmmc2_supply, -+}; -+ -+static struct fixed_voltage_config omap3evm_vwlan = { -+ .supply_name = "vwl1271", -+ .microvolts = 1800000, /* 1.80V */ -+ .gpio = OMAP3EVM_WLAN_PMENA_GPIO, -+ .startup_delay = 70000, /* 70ms */ -+ .enable_high = 1, -+ .enabled_at_boot = 0, -+ .init_data = &omap3evm_vmmc2, -+}; -+ -+static struct platform_device omap3evm_wlan_regulator = { -+ .name = "reg-fixed-voltage", -+ .id = 1, -+ .dev = { -+ .platform_data = &omap3evm_vwlan, -+ }, -+}; -+ -+struct wl12xx_platform_data omap3evm_wlan_data __initdata = { -+ .irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO), -+ .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */ -+}; -+#endif -+ - static struct twl4030_platform_data omap3evm_twldata = { - .irq_base = TWL4030_IRQ_BASE, - .irq_end = TWL4030_IRQ_END, -@@ -550,6 +651,7 @@ - .codec = &omap3evm_codec_data, - .vdac = &omap3_evm_vdac, - .vpll2 = &omap3_evm_vpll2, -+ .vio = &omap3evm_vio, - }; - - static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = { -@@ -625,19 +727,12 @@ - static struct omap_board_config_kernel omap3_evm_config[] __initdata = { - }; - --static void __init omap3_evm_init_irq(void) -+static void __init omap3_evm_init_early(void) - { -- omap_board_config = omap3_evm_config; -- omap_board_config_size = ARRAY_SIZE(omap3_evm_config); - omap2_init_common_infrastructure(); - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); -- omap_init_irq(); - } - --static struct platform_device *omap3_evm_devices[] __initdata = { -- &omap3_evm_dss_device, --}; -- - static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { - - .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, -@@ -652,14 +747,76 @@ - }; - - #ifdef CONFIG_OMAP_MUX --static struct omap_board_mux board_mux[] __initdata = { -+static struct omap_board_mux omap35x_board_mux[] __initdata = { -+ OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | -+ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | -+ OMAP_PIN_OFF_WAKEUPENABLE), -+ OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | -+ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | -+ OMAP_PIN_OFF_WAKEUPENABLE), -+ OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | -+ OMAP_PIN_OFF_NONE), -+ OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | -+ OMAP_PIN_OFF_NONE), -+#ifdef CONFIG_WL12XX_PLATFORM_DATA -+ /* WLAN IRQ - GPIO 149 */ -+ OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), -+ -+ /* WLAN POWER ENABLE - GPIO 150 */ -+ OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), -+ -+ /* MMC2 SDIO pin muxes for WL12xx */ -+ OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+ OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+ OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+ OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+ OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+ OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+#endif -+ { .reg_offset = OMAP_MUX_TERMINATOR }, -+}; -+ -+static struct omap_board_mux omap36x_board_mux[] __initdata = { - OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP | - OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | - OMAP_PIN_OFF_WAKEUPENABLE), - OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP | -- OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW), -+ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW | -+ OMAP_PIN_OFF_WAKEUPENABLE), -+ /* AM/DM37x EVM: DSS data bus muxed with sys_boot */ -+ OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), -+ OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), -+ OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), -+ OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), -+ OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), -+ OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), -+ OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), -+ OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), -+ OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), -+ OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), -+ OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), -+ OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE), -+#ifdef CONFIG_WL12XX_PLATFORM_DATA -+ /* WLAN IRQ - GPIO 149 */ -+ OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), -+ -+ /* WLAN POWER ENABLE - GPIO 150 */ -+ OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), -+ -+ /* MMC2 SDIO pin muxes for WL12xx */ -+ OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+ OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+ OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+ OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+ OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+ OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+#endif -+ - { .reg_offset = OMAP_MUX_TERMINATOR }, - }; -+#else -+#define omap35x_board_mux NULL -+#define omap36x_board_mux NULL - #endif - - static struct omap_musb_board_data musb_board_data = { -@@ -671,11 +828,18 @@ - static void __init omap3_evm_init(void) - { - omap3_evm_get_revision(); -- omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); -+ -+ if (cpu_is_omap3630()) -+ omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB); -+ else -+ omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB); -+ -+ omap_board_config = omap3_evm_config; -+ omap_board_config_size = ARRAY_SIZE(omap3_evm_config); - - omap3_evm_i2c_init(); - -- platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices)); -+ omap_display_init(&omap3_evm_dss_data); - - spi_register_board_info(omap3evm_spi_board_info, - ARRAY_SIZE(omap3evm_spi_board_info)); -@@ -715,14 +879,22 @@ - ads7846_dev_init(); - omap3evm_init_smsc911x(); - omap3_evm_display_init(); -+ -+#ifdef CONFIG_WL12XX_PLATFORM_DATA -+ /* WL12xx WLAN Init */ -+ if (wl12xx_set_platform_data(&omap3evm_wlan_data)) -+ pr_err("error setting wl12xx data\n"); -+ platform_device_register(&omap3evm_wlan_regulator); -+#endif - } - - MACHINE_START(OMAP3EVM, "OMAP3 EVM") - /* Maintainer: Syed Mohammed Khasim - Texas Instruments */ - .boot_params = 0x80000100, -- .map_io = omap3_map_io, - .reserve = omap_reserve, -- .init_irq = omap3_evm_init_irq, -+ .map_io = omap3_map_io, -+ .init_early = omap3_evm_init_early, -+ .init_irq = omap_init_irq, - .init_machine = omap3_evm_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3logic.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3logic.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3logic.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3logic.c 2011-03-09 13:19:09.798507865 +0100 -@@ -195,11 +195,10 @@ - gpmc_smsc911x_init(&board_smsc911x_data); - } - --static void __init omap3logic_init_irq(void) -+static void __init omap3logic_init_early(void) - { - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -- omap_init_irq(); - } - - #ifdef CONFIG_OMAP_MUX -@@ -225,7 +224,8 @@ - MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board") - .boot_params = 0x80000100, - .map_io = omap3_map_io, -- .init_irq = omap3logic_init_irq, -+ .init_early = omap3logic_init_early, -+ .init_irq = omap_init_irq, - .init_machine = omap3logic_init, - .timer = &omap_timer, - MACHINE_END -@@ -233,7 +233,8 @@ - MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") - .boot_params = 0x80000100, - .map_io = omap3_map_io, -- .init_irq = omap3logic_init_irq, -+ .init_early = omap3logic_init_early, -+ .init_irq = omap_init_irq, - .init_machine = omap3logic_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3pandora.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3pandora.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3pandora.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3pandora.c 2011-03-09 13:19:09.798507865 +0100 -@@ -253,14 +253,6 @@ - .default_device = &pandora_lcd_device, - }; - --static struct platform_device pandora_dss_device = { -- .name = "omapdss", -- .id = -1, -- .dev = { -- .platform_data = &pandora_dss_data, -- }, --}; -- - static void pandora_wl1251_init_card(struct mmc_card *card) - { - /* -@@ -341,20 +333,21 @@ - }; - - static struct regulator_consumer_supply pandora_vmmc1_supply = -- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); -+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); - - static struct regulator_consumer_supply pandora_vmmc2_supply = -- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); -+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); - - static struct regulator_consumer_supply pandora_vmmc3_supply = -- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.2"); -+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"); - - static struct regulator_consumer_supply pandora_vdda_dac_supply = -- REGULATOR_SUPPLY("vdda_dac", "omapdss"); -+ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); - - static struct regulator_consumer_supply pandora_vdds_supplies[] = { - REGULATOR_SUPPLY("vdds_sdi", "omapdss"), - REGULATOR_SUPPLY("vdds_dsi", "omapdss"), -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), - }; - - static struct regulator_consumer_supply pandora_vcc_lcd_supply = -@@ -524,9 +517,7 @@ - .usb_mode = T2_USB_MODE_ULPI, - }; - --static struct twl4030_codec_audio_data omap3pandora_audio_data = { -- .audio_mclk = 26000000, --}; -+static struct twl4030_codec_audio_data omap3pandora_audio_data; - - static struct twl4030_codec_data omap3pandora_codec_data = { - .audio_mclk = 26000000, -@@ -634,12 +625,11 @@ - } - }; - --static void __init omap3pandora_init_irq(void) -+static void __init omap3pandora_init_early(void) - { - omap2_init_common_infrastructure(); - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); -- omap_init_irq(); - } - - static void __init pandora_wl1251_init(void) -@@ -677,7 +667,6 @@ - static struct platform_device *omap3pandora_devices[] __initdata = { - &pandora_leds_gpio, - &pandora_keys_gpio, -- &pandora_dss_device, - &pandora_vwlan_device, - }; - -@@ -712,6 +701,7 @@ - pandora_wl1251_init(); - platform_add_devices(omap3pandora_devices, - ARRAY_SIZE(omap3pandora_devices)); -+ omap_display_init(&pandora_dss_data); - omap_serial_init(); - spi_register_board_info(omap3pandora_spi_board_info, - ARRAY_SIZE(omap3pandora_spi_board_info)); -@@ -727,9 +717,10 @@ - - MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") - .boot_params = 0x80000100, -- .map_io = omap3_map_io, - .reserve = omap_reserve, -- .init_irq = omap3pandora_init_irq, -+ .map_io = omap3_map_io, -+ .init_early = omap3pandora_init_early, -+ .init_irq = omap_init_irq, - .init_machine = omap3pandora_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3stalker.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3stalker.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3stalker.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3stalker.c 2011-03-09 13:19:09.799507845 +0100 -@@ -240,14 +240,6 @@ - .default_device = &omap3_stalker_dvi_device, - }; - --static struct platform_device omap3_stalker_dss_device = { -- .name = "omapdss", -- .id = -1, -- .dev = { -- .platform_data = &omap3_stalker_dss_data, -- }, --}; -- - static struct regulator_consumer_supply omap3stalker_vmmc1_supply = { - .supply = "vmmc", - }; -@@ -439,19 +431,15 @@ - .irq_line = 1, - }; - --static struct twl4030_codec_audio_data omap3stalker_audio_data = { -- .audio_mclk = 26000000, --}; -+static struct twl4030_codec_audio_data omap3stalker_audio_data; - - static struct twl4030_codec_data omap3stalker_codec_data = { - .audio_mclk = 26000000, - .audio = &omap3stalker_audio_data, - }; - --static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = { -- .supply = "vdda_dac", -- .dev = &omap3_stalker_dss_device.dev, --}; -+static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = -+ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); - - /* VDAC for DSS driving S-Video */ - static struct regulator_init_data omap3_stalker_vdac = { -@@ -469,9 +457,9 @@ - }; - - /* VPLL2 for digital video outputs */ --static struct regulator_consumer_supply omap3_stalker_vpll2_supply = { -- .supply = "vdds_dsi", -- .dev = &omap3_stalker_lcd_device.dev, -+static struct regulator_consumer_supply omap3_stalker_vpll2_supplies[] = { -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss"), -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), - }; - - static struct regulator_init_data omap3_stalker_vpll2 = { -@@ -485,8 +473,8 @@ - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -- .num_consumer_supplies = 1, -- .consumer_supplies = &omap3_stalker_vpll2_supply, -+ .num_consumer_supplies = ARRAY_SIZE(omap3_stalker_vpll2_supplies), -+ .consumer_supplies = omap3_stalker_vpll2_supplies, - }; - - static struct twl4030_platform_data omap3stalker_twldata = { -@@ -591,12 +579,14 @@ - static struct omap_board_config_kernel omap3_stalker_config[] __initdata = { - }; - --static void __init omap3_stalker_init_irq(void) -+static void __init omap3_stalker_init_early(void) - { -- omap_board_config = omap3_stalker_config; -- omap_board_config_size = ARRAY_SIZE(omap3_stalker_config); - omap2_init_common_infrastructure(); - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); -+} -+ -+static void __init omap3_stalker_init_irq(void) -+{ - omap_init_irq(); - #ifdef CONFIG_OMAP_32K_TIMER - omap2_gp_clockevent_set_gptimer(12); -@@ -604,7 +594,6 @@ - } - - static struct platform_device *omap3_stalker_devices[] __initdata = { -- &omap3_stalker_dss_device, - &keys_gpio, - }; - -@@ -638,12 +627,15 @@ - static void __init omap3_stalker_init(void) - { - omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); -+ omap_board_config = omap3_stalker_config; -+ omap_board_config_size = ARRAY_SIZE(omap3_stalker_config); - - omap3_stalker_i2c_init(); - - platform_add_devices(omap3_stalker_devices, - ARRAY_SIZE(omap3_stalker_devices)); - -+ omap_display_init(&omap3_stalker_dss_data); - spi_register_board_info(omap3stalker_spi_board_info, - ARRAY_SIZE(omap3stalker_spi_board_info)); - -@@ -666,6 +658,7 @@ - /* Maintainer: Jason Lam -lzg@ema-tech.com */ - .boot_params = 0x80000100, - .map_io = omap3_map_io, -+ .init_early = omap3_stalker_init_early, - .init_irq = omap3_stalker_init_irq, - .init_machine = omap3_stalker_init, - .timer = &omap_timer, -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3touchbook.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3touchbook.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap3touchbook.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap3touchbook.c 2011-03-09 13:19:09.799507845 +0100 -@@ -252,9 +252,7 @@ - .usb_mode = T2_USB_MODE_ULPI, - }; - --static struct twl4030_codec_audio_data touchbook_audio_data = { -- .audio_mclk = 26000000, --}; -+static struct twl4030_codec_audio_data touchbook_audio_data; - - static struct twl4030_codec_data touchbook_codec_data = { - .audio_mclk = 26000000, -@@ -415,14 +413,15 @@ - }; - #endif - --static void __init omap3_touchbook_init_irq(void) -+static void __init omap3_touchbook_init_early(void) - { -- omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); -- omap_board_config = omap3_touchbook_config; -- omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config); - omap2_init_common_infrastructure(); - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); -+} -+ -+static void __init omap3_touchbook_init_irq(void) -+{ - omap_init_irq(); - #ifdef CONFIG_OMAP_32K_TIMER - omap2_gp_clockevent_set_gptimer(12); -@@ -510,6 +509,10 @@ - - static void __init omap3_touchbook_init(void) - { -+ omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); -+ omap_board_config = omap3_touchbook_config; -+ omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config); -+ - pm_power_off = omap3_touchbook_poweroff; - - omap3_touchbook_i2c_init(); -@@ -538,8 +541,9 @@ - MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") - /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */ - .boot_params = 0x80000100, -- .map_io = omap3_map_io, - .reserve = omap_reserve, -+ .map_io = omap3_map_io, -+ .init_early = omap3_touchbook_init_early, - .init_irq = omap3_touchbook_init_irq, - .init_machine = omap3_touchbook_init, - .timer = &omap_timer, -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap4panda.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap4panda.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-omap4panda.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-omap4panda.c 2011-03-09 13:19:09.799507845 +0100 -@@ -26,6 +26,8 @@ - #include - #include - #include -+#include -+#include - - #include - #include -@@ -45,6 +47,18 @@ - - #define GPIO_HUB_POWER 1 - #define GPIO_HUB_NRESET 62 -+#define GPIO_WIFI_PMENA 43 -+#define GPIO_WIFI_IRQ 53 -+ -+/* wl127x BT, FM, GPS connectivity chip */ -+static int wl1271_gpios[] = {46, -1, -1}; -+static struct platform_device wl1271_device = { -+ .name = "kim", -+ .id = -1, -+ .dev = { -+ .platform_data = &wl1271_gpios, -+ }, -+}; - - static struct gpio_led gpio_leds[] = { - { -@@ -74,13 +88,13 @@ - - static struct platform_device *panda_devices[] __initdata = { - &leds_gpio, -+ &wl1271_device, - }; - --static void __init omap4_panda_init_irq(void) -+static void __init omap4_panda_init_early(void) - { - omap2_init_common_infrastructure(); - omap2_init_common_devices(NULL, NULL); -- gic_init_irq(); - } - - static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { -@@ -162,16 +176,62 @@ - .gpio_wp = -EINVAL, - .gpio_cd = -EINVAL, - }, -+ { -+ .name = "wl1271", -+ .mmc = 5, -+ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD, -+ .gpio_wp = -EINVAL, -+ .gpio_cd = -EINVAL, -+ .ocr_mask = MMC_VDD_165_195, -+ .nonremovable = true, -+ }, - {} /* Terminator */ - }; - - static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = { - { - .supply = "vmmc", -- .dev_name = "mmci-omap-hs.0", -+ .dev_name = "omap_hsmmc.0", -+ }, -+}; -+ -+static struct regulator_consumer_supply omap4_panda_vmmc5_supply = { -+ .supply = "vmmc", -+ .dev_name = "omap_hsmmc.4", -+}; -+ -+static struct regulator_init_data panda_vmmc5 = { -+ .constraints = { -+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, -+ }, -+ .num_consumer_supplies = 1, -+ .consumer_supplies = &omap4_panda_vmmc5_supply, -+}; -+ -+static struct fixed_voltage_config panda_vwlan = { -+ .supply_name = "vwl1271", -+ .microvolts = 1800000, /* 1.8V */ -+ .gpio = GPIO_WIFI_PMENA, -+ .startup_delay = 70000, /* 70msec */ -+ .enable_high = 1, -+ .enabled_at_boot = 0, -+ .init_data = &panda_vmmc5, -+}; -+ -+static struct platform_device omap_vwlan_device = { -+ .name = "reg-fixed-voltage", -+ .id = 1, -+ .dev = { -+ .platform_data = &panda_vwlan, - }, - }; - -+struct wl12xx_platform_data omap_panda_wlan_data __initdata = { -+ .irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ), -+ /* PANDA ref clock is 38.4 MHz */ -+ .board_ref_clock = 2, -+}; -+ - static int omap4_twl6030_hsmmc_late_init(struct device *dev) - { - int ret = 0; -@@ -305,7 +365,6 @@ - .constraints = { - .min_uV = 2100000, - .max_uV = 2100000, -- .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE -@@ -317,7 +376,6 @@ - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, -- .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE -@@ -329,7 +387,6 @@ - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, -- .apply_uV = true, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE -@@ -391,6 +448,19 @@ - - #ifdef CONFIG_OMAP_MUX - static struct omap_board_mux board_mux[] __initdata = { -+ /* WLAN IRQ - GPIO 53 */ -+ OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT), -+ /* WLAN POWER ENABLE - GPIO 43 */ -+ OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT), -+ /* WLAN SDIO: MMC5 CMD */ -+ OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+ /* WLAN SDIO: MMC5 CLK */ -+ OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+ /* WLAN SDIO: MMC5 DAT[0-3] */ -+ OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+ OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+ OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), -+ OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP), - { .reg_offset = OMAP_MUX_TERMINATOR }, - }; - #else -@@ -405,8 +475,12 @@ - package = OMAP_PACKAGE_CBL; - omap4_mux_init(board_mux, package); - -+ if (wl12xx_set_platform_data(&omap_panda_wlan_data)) -+ pr_err("error setting wl12xx data\n"); -+ - omap4_panda_i2c_init(); - platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); -+ platform_device_register(&omap_vwlan_device); - omap_serial_init(); - omap4_twl6030_hsmmc_init(mmc); - omap4_ehci_init(); -@@ -424,7 +498,8 @@ - .boot_params = 0x80000100, - .reserve = omap_reserve, - .map_io = omap4_panda_map_io, -- .init_irq = omap4_panda_init_irq, -+ .init_early = omap4_panda_init_early, -+ .init_irq = gic_init_irq, - .init_machine = omap4_panda_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-overo.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-overo.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-overo.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-overo.c 2011-03-09 13:19:09.799507845 +0100 -@@ -28,6 +28,8 @@ - #include - #include - #include -+#include -+#include - - #include - #include -@@ -41,10 +43,14 @@ - - #include - #include -+#include -+#include - #include - #include - #include - #include -+#include -+#include - #include - - #include "mux.h" -@@ -68,8 +74,6 @@ - #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ - defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) - --#include --#include - #include - - static struct omap2_mcspi_device_config ads7846_mcspi_config = { -@@ -94,16 +98,32 @@ - .keep_vref_on = 1, - }; - --static struct spi_board_info overo_spi_board_info[] __initdata = { -- { -- .modalias = "ads7846", -- .bus_num = 1, -- .chip_select = 0, -- .max_speed_hz = 1500000, -- .controller_data = &ads7846_mcspi_config, -- .irq = OMAP_GPIO_IRQ(OVERO_GPIO_PENDOWN), -- .platform_data = &ads7846_config, -- } -+/* fixed regulator for ads7846 */ -+static struct regulator_consumer_supply ads7846_supply = -+ REGULATOR_SUPPLY("vcc", "spi1.0"); -+ -+static struct regulator_init_data vads7846_regulator = { -+ .constraints = { -+ .valid_ops_mask = REGULATOR_CHANGE_STATUS, -+ }, -+ .num_consumer_supplies = 1, -+ .consumer_supplies = &ads7846_supply, -+}; -+ -+static struct fixed_voltage_config vads7846 = { -+ .supply_name = "vads7846", -+ .microvolts = 3300000, /* 3.3V */ -+ .gpio = -EINVAL, -+ .startup_delay = 0, -+ .init_data = &vads7846_regulator, -+}; -+ -+static struct platform_device vads7846_device = { -+ .name = "reg-fixed-voltage", -+ .id = 1, -+ .dev = { -+ .platform_data = &vads7846, -+ }, - }; - - static void __init overo_ads7846_init(void) -@@ -116,8 +136,7 @@ - return; - } - -- spi_register_board_info(overo_spi_board_info, -- ARRAY_SIZE(overo_spi_board_info)); -+ platform_device_register(&vads7846_device); - } - - #else -@@ -233,6 +252,137 @@ - static inline void __init overo_init_smsc911x(void) { return; } - #endif - -+/* DSS */ -+static int lcd_enabled; -+static int dvi_enabled; -+ -+#define OVERO_GPIO_LCD_EN 144 -+#define OVERO_GPIO_LCD_BL 145 -+ -+static void __init overo_display_init(void) -+{ -+ if ((gpio_request(OVERO_GPIO_LCD_EN, "OVERO_GPIO_LCD_EN") == 0) && -+ (gpio_direction_output(OVERO_GPIO_LCD_EN, 1) == 0)) -+ gpio_export(OVERO_GPIO_LCD_EN, 0); -+ else -+ printk(KERN_ERR "could not obtain gpio for " -+ "OVERO_GPIO_LCD_EN\n"); -+ -+ if ((gpio_request(OVERO_GPIO_LCD_BL, "OVERO_GPIO_LCD_BL") == 0) && -+ (gpio_direction_output(OVERO_GPIO_LCD_BL, 1) == 0)) -+ gpio_export(OVERO_GPIO_LCD_BL, 0); -+ else -+ printk(KERN_ERR "could not obtain gpio for " -+ "OVERO_GPIO_LCD_BL\n"); -+} -+ -+static int overo_panel_enable_dvi(struct omap_dss_device *dssdev) -+{ -+ if (lcd_enabled) { -+ printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); -+ return -EINVAL; -+ } -+ dvi_enabled = 1; -+ -+ return 0; -+} -+ -+static void overo_panel_disable_dvi(struct omap_dss_device *dssdev) -+{ -+ dvi_enabled = 0; -+} -+ -+static struct panel_generic_dpi_data dvi_panel = { -+ .name = "generic", -+ .platform_enable = overo_panel_enable_dvi, -+ .platform_disable = overo_panel_disable_dvi, -+}; -+ -+static struct omap_dss_device overo_dvi_device = { -+ .name = "dvi", -+ .type = OMAP_DISPLAY_TYPE_DPI, -+ .driver_name = "generic_dpi_panel", -+ .data = &dvi_panel, -+ .phy.dpi.data_lines = 24, -+}; -+ -+static struct omap_dss_device overo_tv_device = { -+ .name = "tv", -+ .driver_name = "venc", -+ .type = OMAP_DISPLAY_TYPE_VENC, -+ .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, -+}; -+ -+static int overo_panel_enable_lcd(struct omap_dss_device *dssdev) -+{ -+ if (dvi_enabled) { -+ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); -+ return -EINVAL; -+ } -+ -+ gpio_set_value(OVERO_GPIO_LCD_EN, 1); -+ gpio_set_value(OVERO_GPIO_LCD_BL, 1); -+ lcd_enabled = 1; -+ return 0; -+} -+ -+static void overo_panel_disable_lcd(struct omap_dss_device *dssdev) -+{ -+ gpio_set_value(OVERO_GPIO_LCD_EN, 0); -+ gpio_set_value(OVERO_GPIO_LCD_BL, 0); -+ lcd_enabled = 0; -+} -+ -+static struct panel_generic_dpi_data lcd43_panel = { -+ .name = "samsung_lte430wq_f0c", -+ .platform_enable = overo_panel_enable_lcd, -+ .platform_disable = overo_panel_disable_lcd, -+}; -+ -+static struct omap_dss_device overo_lcd43_device = { -+ .name = "lcd43", -+ .type = OMAP_DISPLAY_TYPE_DPI, -+ .driver_name = "generic_dpi_panel", -+ .data = &lcd43_panel, -+ .phy.dpi.data_lines = 24, -+}; -+ -+#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ -+ defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) -+static struct omap_dss_device overo_lcd35_device = { -+ .type = OMAP_DISPLAY_TYPE_DPI, -+ .name = "lcd35", -+ .driver_name = "lgphilips_lb035q02_panel", -+ .phy.dpi.data_lines = 24, -+ .platform_enable = overo_panel_enable_lcd, -+ .platform_disable = overo_panel_disable_lcd, -+}; -+#endif -+ -+static struct omap_dss_device *overo_dss_devices[] = { -+ &overo_dvi_device, -+ &overo_tv_device, -+#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ -+ defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) -+ &overo_lcd35_device, -+#endif -+ &overo_lcd43_device, -+}; -+ -+static struct omap_dss_board_info overo_dss_data = { -+ .num_devices = ARRAY_SIZE(overo_dss_devices), -+ .devices = overo_dss_devices, -+ .default_device = &overo_dvi_device, -+}; -+ -+static struct regulator_consumer_supply overo_vdda_dac_supply = -+ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); -+ -+static struct regulator_consumer_supply overo_vdds_dsi_supply[] = { -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss"), -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), -+}; -+ - static struct mtd_partition overo_nand_partitions[] = { - { - .name = "xloader", -@@ -358,17 +508,42 @@ - .consumer_supplies = &overo_vmmc1_supply, - }; - --static struct twl4030_codec_audio_data overo_audio_data = { -- .audio_mclk = 26000000, -+/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ -+static struct regulator_init_data overo_vdac = { -+ .constraints = { -+ .min_uV = 1800000, -+ .max_uV = 1800000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL -+ | REGULATOR_MODE_STANDBY, -+ .valid_ops_mask = REGULATOR_CHANGE_MODE -+ | REGULATOR_CHANGE_STATUS, -+ }, -+ .num_consumer_supplies = 1, -+ .consumer_supplies = &overo_vdda_dac_supply, - }; - -+/* VPLL2 for digital video outputs */ -+static struct regulator_init_data overo_vpll2 = { -+ .constraints = { -+ .name = "VDVI", -+ .min_uV = 1800000, -+ .max_uV = 1800000, -+ .valid_modes_mask = REGULATOR_MODE_NORMAL -+ | REGULATOR_MODE_STANDBY, -+ .valid_ops_mask = REGULATOR_CHANGE_MODE -+ | REGULATOR_CHANGE_STATUS, -+ }, -+ .num_consumer_supplies = ARRAY_SIZE(overo_vdds_dsi_supply), -+ .consumer_supplies = overo_vdds_dsi_supply, -+}; -+ -+static struct twl4030_codec_audio_data overo_audio_data; -+ - static struct twl4030_codec_data overo_codec_data = { - .audio_mclk = 26000000, - .audio = &overo_audio_data, - }; - --/* mmc2 (WLAN) and Bluetooth don't use twl4030 regulators */ -- - static struct twl4030_platform_data overo_twldata = { - .irq_base = TWL4030_IRQ_BASE, - .irq_end = TWL4030_IRQ_END, -@@ -376,6 +551,8 @@ - .usb = &overo_usb_data, - .codec = &overo_codec_data, - .vmmc1 = &overo_vmmc1, -+ .vdac = &overo_vdac, -+ .vpll2 = &overo_vpll2, - }; - - static struct i2c_board_info __initdata overo_i2c_boardinfo[] = { -@@ -396,33 +573,46 @@ - return 0; - } - --static struct platform_device overo_lcd_device = { -- .name = "overo_lcd", -- .id = -1, --}; -- --static struct omap_lcd_config overo_lcd_config __initdata = { -- .ctrl_name = "internal", -+static struct spi_board_info overo_spi_board_info[] __initdata = { -+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ -+ defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) -+ { -+ .modalias = "ads7846", -+ .bus_num = 1, -+ .chip_select = 0, -+ .max_speed_hz = 1500000, -+ .controller_data = &ads7846_mcspi_config, -+ .irq = OMAP_GPIO_IRQ(OVERO_GPIO_PENDOWN), -+ .platform_data = &ads7846_config, -+ }, -+#endif -+#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ -+ defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) -+ { -+ .modalias = "lgphilips_lb035q02_panel-spi", -+ .bus_num = 1, -+ .chip_select = 1, -+ .max_speed_hz = 500000, -+ .mode = SPI_MODE_3, -+ }, -+#endif - }; - --static struct omap_board_config_kernel overo_config[] __initdata = { -- { OMAP_TAG_LCD, &overo_lcd_config }, --}; -+static int __init overo_spi_init(void) -+{ -+ overo_ads7846_init(); -+ spi_register_board_info(overo_spi_board_info, -+ ARRAY_SIZE(overo_spi_board_info)); -+ return 0; -+} - --static void __init overo_init_irq(void) -+static void __init overo_init_early(void) - { -- omap_board_config = overo_config; -- omap_board_config_size = ARRAY_SIZE(overo_config); - omap2_init_common_infrastructure(); - omap2_init_common_devices(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); -- omap_init_irq(); - } - --static struct platform_device *overo_devices[] __initdata = { -- &overo_lcd_device, --}; -- - static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, -@@ -450,13 +640,14 @@ - { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - overo_i2c_init(); -- platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices)); -+ omap_display_init(&overo_dss_data); - omap_serial_init(); - overo_flash_init(); - usb_musb_init(&musb_board_data); - usb_ehci_init(&ehci_pdata); -- overo_ads7846_init(); -+ overo_spi_init(); - overo_init_smsc911x(); -+ overo_display_init(); - - /* Ensure SDRC pins are mux'd for self-refresh */ - omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); -@@ -501,9 +692,10 @@ - - MACHINE_START(OVERO, "Gumstix Overo") - .boot_params = 0x80000100, -- .map_io = omap3_map_io, - .reserve = omap_reserve, -- .init_irq = overo_init_irq, -+ .map_io = omap3_map_io, -+ .init_early = overo_init_early, -+ .init_irq = omap_init_irq, - .init_machine = overo_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-rm680.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-rm680.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-rm680.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-rm680.c 2011-03-09 13:19:09.800507825 +0100 -@@ -33,7 +33,7 @@ - #include "sdram-nokia.h" - - static struct regulator_consumer_supply rm680_vemmc_consumers[] = { -- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), -+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), - }; - - /* Fixed regulator for internal eMMC */ -@@ -138,14 +138,13 @@ - omap2_hsmmc_init(mmc); - } - --static void __init rm680_init_irq(void) -+static void __init rm680_init_early(void) - { - struct omap_sdrc_params *sdrc_params; - - omap2_init_common_infrastructure(); - sdrc_params = nokia_get_sdram_timings(); - omap2_init_common_devices(sdrc_params, sdrc_params); -- omap_init_irq(); - } - - #ifdef CONFIG_OMAP_MUX -@@ -176,9 +175,10 @@ - - MACHINE_START(NOKIA_RM680, "Nokia RM-680 board") - .boot_params = 0x80000100, -- .map_io = rm680_map_io, - .reserve = omap_reserve, -- .init_irq = rm680_init_irq, -+ .map_io = rm680_map_io, -+ .init_early = rm680_init_early, -+ .init_irq = omap_init_irq, - .init_machine = rm680_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-rx51.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-rx51.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-rx51.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-rx51.c 2011-03-09 13:19:09.800507825 +0100 -@@ -98,17 +98,13 @@ - { OMAP_TAG_LCD, &rx51_lcd_config }, - }; - --static void __init rx51_init_irq(void) -+static void __init rx51_init_early(void) - { - struct omap_sdrc_params *sdrc_params; - -- omap_board_config = rx51_config; -- omap_board_config_size = ARRAY_SIZE(rx51_config); -- omap3_pm_init_cpuidle(rx51_cpuidle_params); - omap2_init_common_infrastructure(); - sdrc_params = nokia_get_sdram_timings(); - omap2_init_common_devices(sdrc_params, sdrc_params); -- omap_init_irq(); - } - - extern void __init rx51_peripherals_init(void); -@@ -128,6 +124,9 @@ - static void __init rx51_init(void) - { - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); -+ omap_board_config = rx51_config; -+ omap_board_config_size = ARRAY_SIZE(rx51_config); -+ omap3_pm_init_cpuidle(rx51_cpuidle_params); - omap_serial_init(); - usb_musb_init(&musb_board_data); - rx51_peripherals_init(); -@@ -149,9 +148,10 @@ - MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") - /* Maintainer: Lauri Leukkunen */ - .boot_params = 0x80000100, -- .map_io = rx51_map_io, - .reserve = omap_reserve, -- .init_irq = rx51_init_irq, -+ .map_io = rx51_map_io, -+ .init_early = rx51_init_early, -+ .init_irq = omap_init_irq, - .init_machine = rx51_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-rx51-peripherals.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-rx51-peripherals.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-rx51-peripherals.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-rx51-peripherals.c 2011-03-09 13:19:09.800507825 +0100 -@@ -36,6 +36,8 @@ - - #include - #include -+#include -+#include - - #include <../drivers/staging/iio/light/tsl2563.h> - -@@ -47,6 +49,8 @@ - - #define RX51_WL1251_POWER_GPIO 87 - #define RX51_WL1251_IRQ_GPIO 42 -+#define RX51_FMTX_RESET_GPIO 163 -+#define RX51_FMTX_IRQ 53 - - /* list all spi devices here */ - enum { -@@ -331,13 +335,13 @@ - }; - - static struct regulator_consumer_supply rx51_vmmc1_supply = -- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); -+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"); - - static struct regulator_consumer_supply rx51_vaux3_supply = -- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); -+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"); - - static struct regulator_consumer_supply rx51_vsim_supply = -- REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); -+ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"); - - static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { - /* tlv320aic3x analog supplies */ -@@ -348,7 +352,7 @@ - /* tpa6130a2 */ - REGULATOR_SUPPLY("Vdd", "2-0060"), - /* Keep vmmc as last item. It is not iterated for newer boards */ -- REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), -+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), - }; - - static struct regulator_consumer_supply rx51_vio_supplies[] = { -@@ -357,14 +361,18 @@ - REGULATOR_SUPPLY("DVDD", "2-0018"), - REGULATOR_SUPPLY("IOVDD", "2-0019"), - REGULATOR_SUPPLY("DVDD", "2-0019"), -+ /* Si4713 IO supply */ -+ REGULATOR_SUPPLY("vio", "2-0063"), - }; - - static struct regulator_consumer_supply rx51_vaux1_consumers[] = { - REGULATOR_SUPPLY("vdds_sdi", "omapdss"), -+ /* Si4713 supply */ -+ REGULATOR_SUPPLY("vdd", "2-0063"), - }; - - static struct regulator_consumer_supply rx51_vdac_supply[] = { -- REGULATOR_SUPPLY("vdda_dac", "omapdss"), -+ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"), - }; - - static struct regulator_init_data rx51_vaux1 = { -@@ -511,6 +519,41 @@ - .consumer_supplies = rx51_vio_supplies, - }; - -+static struct si4713_platform_data rx51_si4713_i2c_data __initdata_or_module = { -+ .gpio_reset = RX51_FMTX_RESET_GPIO, -+}; -+ -+static struct i2c_board_info rx51_si4713_board_info __initdata_or_module = { -+ I2C_BOARD_INFO("si4713", SI4713_I2C_ADDR_BUSEN_HIGH), -+ .platform_data = &rx51_si4713_i2c_data, -+}; -+ -+static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module = { -+ .i2c_bus = 2, -+ .subdev_board_info = &rx51_si4713_board_info, -+}; -+ -+static struct platform_device rx51_si4713_dev __initdata_or_module = { -+ .name = "radio-si4713", -+ .id = -1, -+ .dev = { -+ .platform_data = &rx51_si4713_data, -+ }, -+}; -+ -+static __init void rx51_init_si4713(void) -+{ -+ int err; -+ -+ err = gpio_request_one(RX51_FMTX_IRQ, GPIOF_DIR_IN, "si4713 irq"); -+ if (err) { -+ printk(KERN_ERR "Cannot request si4713 irq gpio. %d\n", err); -+ return; -+ } -+ rx51_si4713_board_info.irq = gpio_to_irq(RX51_FMTX_IRQ); -+ platform_device_register(&rx51_si4713_dev); -+} -+ - static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n) - { - /* FIXME this gpio setup is just a placeholder for now */ -@@ -699,6 +742,14 @@ - .resource_config = twl4030_rconfig, - }; - -+struct twl4030_codec_vibra_data rx51_vibra_data __initdata = { -+ .coexist = 0, -+}; -+ -+struct twl4030_codec_data rx51_codec_data __initdata = { -+ .audio_mclk = 26000000, -+ .vibra = &rx51_vibra_data, -+}; - - static struct twl4030_platform_data rx51_twldata __initdata = { - .irq_base = TWL4030_IRQ_BASE, -@@ -710,6 +761,7 @@ - .madc = &rx51_madc_data, - .usb = &rx51_usb_data, - .power = &rx51_t2scripts_data, -+ .codec = &rx51_codec_data, - - .vaux1 = &rx51_vaux1, - .vaux2 = &rx51_vaux2, -@@ -921,6 +973,7 @@ - board_smc91x_init(); - rx51_add_gpio_keys(); - rx51_init_wl1251(); -+ rx51_init_si4713(); - spi_register_board_info(rx51_peripherals_spi_board_info, - ARRAY_SIZE(rx51_peripherals_spi_board_info)); - -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-rx51-video.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-rx51-video.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-rx51-video.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-rx51-video.c 2011-03-09 13:19:09.800507825 +0100 -@@ -66,18 +66,6 @@ - .default_device = &rx51_lcd_device, - }; - --struct platform_device rx51_display_device = { -- .name = "omapdss", -- .id = -1, -- .dev = { -- .platform_data = &rx51_dss_board_info, -- }, --}; -- --static struct platform_device *rx51_video_devices[] __initdata = { -- &rx51_display_device, --}; -- - static int __init rx51_video_init(void) - { - if (!machine_is_nokia_rx51()) -@@ -95,8 +83,7 @@ - - gpio_direction_output(RX51_LCD_RESET_GPIO, 1); - -- platform_add_devices(rx51_video_devices, -- ARRAY_SIZE(rx51_video_devices)); -+ omap_display_init(&rx51_dss_board_info); - return 0; - } - -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-ti8168evm.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-ti8168evm.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-ti8168evm.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-ti8168evm.c 2011-03-09 13:19:09.800507825 +0100 -@@ -0,0 +1,62 @@ -+/* -+ * Code for TI8168 EVM. -+ * -+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation version 2. -+ * -+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any -+ * kind, whether express or implied; without even the implied warranty -+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+static struct omap_board_config_kernel ti8168_evm_config[] __initdata = { -+}; -+ -+static void __init ti8168_init_early(void) -+{ -+ omap2_init_common_infrastructure(); -+ omap2_init_common_devices(NULL, NULL); -+} -+ -+static void __init ti8168_evm_init_irq(void) -+{ -+ omap_init_irq(); -+} -+ -+static void __init ti8168_evm_init(void) -+{ -+ omap_serial_init(); -+ omap_board_config = ti8168_evm_config; -+ omap_board_config_size = ARRAY_SIZE(ti8168_evm_config); -+} -+ -+static void __init ti8168_evm_map_io(void) -+{ -+ omap2_set_globals_ti816x(); -+ omapti816x_map_common_io(); -+} -+ -+MACHINE_START(TI8168EVM, "ti8168evm") -+ /* Maintainer: Texas Instruments */ -+ .boot_params = 0x80000100, -+ .map_io = ti8168_evm_map_io, -+ .init_early = ti8168_init_early, -+ .init_irq = ti8168_evm_init_irq, -+ .timer = &omap_timer, -+ .init_machine = ti8168_evm_init, -+MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-zoom.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-zoom.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-zoom.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-zoom.c 2011-03-09 13:19:09.801507805 +0100 -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -33,7 +34,7 @@ - - #define ZOOM3_EHCI_RESET_GPIO 64 - --static void __init omap_zoom_init_irq(void) -+static void __init omap_zoom_init_early(void) - { - omap2_init_common_infrastructure(); - if (machine_is_omap_zoom2()) -@@ -42,8 +43,6 @@ - else if (machine_is_omap_zoom3()) - omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params, - h8mbx00u0mer0em_sdrc_params); -- -- omap_init_irq(); - } - - #ifdef CONFIG_OMAP_MUX -@@ -126,8 +125,8 @@ - usb_ehci_init(&ehci_pdata); - } - -- board_nand_init(zoom_nand_partitions, -- ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); -+ board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions), -+ ZOOM_NAND_CS, NAND_BUSWIDTH_16); - zoom_debugboard_init(); - zoom_peripherals_init(); - zoom_display_init(); -@@ -135,18 +134,20 @@ - - MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") - .boot_params = 0x80000100, -- .map_io = omap3_map_io, - .reserve = omap_reserve, -- .init_irq = omap_zoom_init_irq, -+ .map_io = omap3_map_io, -+ .init_early = omap_zoom_init_early, -+ .init_irq = omap_init_irq, - .init_machine = omap_zoom_init, - .timer = &omap_timer, - MACHINE_END - - MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") - .boot_params = 0x80000100, -- .map_io = omap3_map_io, - .reserve = omap_reserve, -- .init_irq = omap_zoom_init_irq, -+ .map_io = omap3_map_io, -+ .init_early = omap_zoom_init_early, -+ .init_irq = omap_init_irq, - .init_machine = omap_zoom_init, - .timer = &omap_timer, - MACHINE_END -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-zoom-display.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-zoom-display.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-zoom-display.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-zoom-display.c 2011-03-09 13:19:09.801507805 +0100 -@@ -130,14 +130,6 @@ - .default_device = &zoom_lcd_device, - }; - --static struct platform_device zoom_dss_device = { -- .name = "omapdss", -- .id = -1, -- .dev = { -- .platform_data = &zoom_dss_data, -- }, --}; -- - static struct omap2_mcspi_device_config dss_lcd_mcspi_config = { - .turbo_mode = 1, - .single_channel = 1, /* 0: slave, 1: master */ -@@ -153,14 +145,9 @@ - }, - }; - --static struct platform_device *zoom_display_devices[] __initdata = { -- &zoom_dss_device, --}; -- - void __init zoom_display_init(void) - { -- platform_add_devices(zoom_display_devices, -- ARRAY_SIZE(zoom_display_devices)); -+ omap_display_init(&zoom_dss_data); - spi_register_board_info(nec_8048_spi_board_info, - ARRAY_SIZE(nec_8048_spi_board_info)); - zoom_lcd_panel_init(); -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/board-zoom-peripherals.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-zoom-peripherals.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/board-zoom-peripherals.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/board-zoom-peripherals.c 2011-03-09 13:19:09.801507805 +0100 -@@ -118,7 +118,7 @@ - - static struct regulator_consumer_supply zoom_vmmc3_supply = { - .supply = "vmmc", -- .dev_name = "mmci-omap-hs.2", -+ .dev_name = "omap_hsmmc.2", - }; - - /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ -@@ -226,11 +226,13 @@ - {} /* Terminator */ - }; - --static struct regulator_consumer_supply zoom_vpll2_supply = -- REGULATOR_SUPPLY("vdds_dsi", "omapdss"); -+static struct regulator_consumer_supply zoom_vpll2_supplies[] = { -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss"), -+ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), -+}; - - static struct regulator_consumer_supply zoom_vdda_dac_supply = -- REGULATOR_SUPPLY("vdda_dac", "omapdss"); -+ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); - - static struct regulator_init_data zoom_vpll2 = { - .constraints = { -@@ -241,8 +243,8 @@ - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS, - }, -- .num_consumer_supplies = 1, -- .consumer_supplies = &zoom_vpll2_supply, -+ .num_consumer_supplies = ARRAY_SIZE(zoom_vpll2_supplies), -+ .consumer_supplies = zoom_vpll2_supplies, - }; - - static struct regulator_init_data zoom_vdac = { -@@ -322,9 +324,7 @@ - .irq_line = 1, - }; - --static struct twl4030_codec_audio_data zoom_audio_data = { -- .audio_mclk = 26000000, --}; -+static struct twl4030_codec_audio_data zoom_audio_data; - - static struct twl4030_codec_data zoom_codec_data = { - .audio_mclk = 26000000, -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/clkt_clksel.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clkt_clksel.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/clkt_clksel.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clkt_clksel.c 2011-03-09 13:19:09.802507785 +0100 -@@ -97,7 +97,7 @@ - u32 *field_val) - { - const struct clksel *clks; -- const struct clksel_rate *clkr, *max_clkr; -+ const struct clksel_rate *clkr, *max_clkr = NULL; - u8 max_div = 0; - - clks = _get_clksel_by_parent(clk, src_clk); -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/clock2420_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock2420_data.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/clock2420_data.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock2420_data.c 2011-03-09 13:19:09.804507743 +0100 -@@ -1786,10 +1786,10 @@ - CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_242X), - CLK(NULL, "gfx_ick", &gfx_ick, CK_242X), - /* DSS domain clocks */ -- CLK("omapdss", "ick", &dss_ick, CK_242X), -- CLK("omapdss", "dss1_fck", &dss1_fck, CK_242X), -- CLK("omapdss", "dss2_fck", &dss2_fck, CK_242X), -- CLK("omapdss", "tv_fck", &dss_54m_fck, CK_242X), -+ CLK("omapdss_dss", "ick", &dss_ick, CK_242X), -+ CLK("omapdss_dss", "fck", &dss1_fck, CK_242X), -+ CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_242X), -+ CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_242X), - /* L3 domain clocks */ - CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X), - CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X), -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/clock2430_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock2430_data.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/clock2430_data.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock2430_data.c 2011-03-09 13:19:09.804507743 +0100 -@@ -1890,10 +1890,10 @@ - CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), - CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), - /* DSS domain clocks */ -- CLK("omapdss", "ick", &dss_ick, CK_243X), -- CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X), -- CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X), -- CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X), -+ CLK("omapdss_dss", "ick", &dss_ick, CK_243X), -+ CLK("omapdss_dss", "fck", &dss1_fck, CK_243X), -+ CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_243X), -+ CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_243X), - /* L3 domain clocks */ - CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X), - CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X), -@@ -1984,15 +1984,15 @@ - CLK(NULL, "pka_ick", &pka_ick, CK_243X), - CLK(NULL, "usb_fck", &usb_fck, CK_243X), - CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), -- CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), -- CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), -- CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), -- CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), -+ CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X), -+ CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_243X), -+ CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X), -+ CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_243X), - CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), - CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), - CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), -- CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), -- CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), -+ CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), -+ CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), - }; - - /* -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/clock2xxx.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock2xxx.h ---- linux-2.6.38-rc7/arch/arm/mach-omap2/clock2xxx.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock2xxx.h 2011-03-09 13:19:09.805507722 +0100 -@@ -20,13 +20,13 @@ - u32 omap2xxx_get_sysclkdiv(void); - void omap2xxx_clk_prepare_for_reboot(void); - --#ifdef CONFIG_ARCH_OMAP2420 -+#ifdef CONFIG_SOC_OMAP2420 - int omap2420_clk_init(void); - #else - #define omap2420_clk_init() 0 - #endif - --#ifdef CONFIG_ARCH_OMAP2430 -+#ifdef CONFIG_SOC_OMAP2430 - int omap2430_clk_init(void); - #else - #define omap2430_clk_init() 0 -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/clock3xxx_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock3xxx_data.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/clock3xxx_data.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock3xxx_data.c 2011-03-09 13:19:09.807507681 +0100 -@@ -3290,10 +3290,10 @@ - CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), - CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), - CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), -- CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), -- CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), -+ CLK("omap_hsmmc.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), -+ CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_3XXX), - CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), -- CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX), -+ CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_3XXX), - CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX), - CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX), - CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX), -@@ -3323,13 +3323,13 @@ - CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), - CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK("ehci-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), -- CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), -+ CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), - CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), - CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), - CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), -- CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), -- CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX), -+ CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX), -+ CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX), - CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), - CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), - CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), -@@ -3357,13 +3357,13 @@ - CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX), - CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX), - CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX), -- CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), -- CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), -- CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX), -- CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX), -- CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX), -- CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), -- CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), -+ CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es1, CK_3430ES1), -+ CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), -+ CLK("omapdss_dss", "tv_clk", &dss_tv_fck, CK_3XXX), -+ CLK("omapdss_dss", "video_clk", &dss_96m_fck, CK_3XXX), -+ CLK("omapdss_dss", "sys_clk", &dss2_alwon_fck, CK_3XXX), -+ CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1), -+ CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), - CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX), - CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX), - CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX), -@@ -3471,6 +3471,9 @@ - } else if (cpu_is_omap3630()) { - cpu_mask = (RATE_IN_34XX | RATE_IN_36XX); - cpu_clkflg = CK_36XX; -+ } else if (cpu_is_ti816x()) { -+ cpu_mask = RATE_IN_TI816X; -+ cpu_clkflg = CK_TI816X; - } else if (cpu_is_omap34xx()) { - if (omap_rev() == OMAP3430_REV_ES1_0) { - cpu_mask = RATE_IN_3430ES1; -@@ -3550,7 +3553,7 @@ - /* - * Lock DPLL5 and put it in autoidle. - */ -- if (omap_rev() >= OMAP3430_REV_ES2_0) -+ if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0)) - omap3_clk_lock_dpll5(); - - /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/clock44xx_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock44xx_data.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/clock44xx_data.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clock44xx_data.c 2011-03-09 13:19:09.808507662 +0100 -@@ -3106,11 +3106,16 @@ - CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), - CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), - CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), -- CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), -- CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), -- CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), -- CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), -- CLK(NULL, "dss_fck", &dss_fck, CK_443X), -+ CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X), -+ CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X), -+ CLK("omapdss_dss", "dss_clk", &dss_dss_clk, CK_443X), -+ CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X), -+ CLK("omapdss_dss", "fck", &dss_fck, CK_443X), -+ /* -+ * On OMAP4, DSS ick is a dummy clock; this is needed for compatibility -+ * with OMAP2/3. -+ */ -+ CLK("omapdss_dss", "ick", &dummy_ck, CK_443X), - CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), - CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), - CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), -@@ -3158,11 +3163,11 @@ - CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), - CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), - CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X), -- CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X), -- CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X), -- CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), -- CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), -- CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), -+ CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X), -+ CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X), -+ CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X), -+ CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X), -+ CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X), - CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), - CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), - CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), -@@ -3245,11 +3250,11 @@ - CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), - CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), - CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), -- CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), -- CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), -- CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), -- CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X), -- CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X), -+ CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), -+ CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), -+ CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), -+ CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), -+ CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), - CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c 2011-03-09 13:19:09.809507642 +0100 -@@ -171,7 +171,7 @@ - - /* 2430-specific possible wakeup dependencies */ - --#ifdef CONFIG_ARCH_OMAP2430 -+#ifdef CONFIG_SOC_OMAP2430 - - /* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */ - static struct clkdm_dep mdm_2430_wkdeps[] = { -@@ -194,7 +194,7 @@ - { NULL }, - }; - --#endif /* CONFIG_ARCH_OMAP2430 */ -+#endif /* CONFIG_SOC_OMAP2430 */ - - - /* OMAP3-specific possible dependencies */ -@@ -450,7 +450,7 @@ - * 2420-only clockdomains - */ - --#if defined(CONFIG_ARCH_OMAP2420) -+#if defined(CONFIG_SOC_OMAP2420) - - static struct clockdomain mpu_2420_clkdm = { - .name = "mpu_clkdm", -@@ -514,14 +514,14 @@ - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), - }; - --#endif /* CONFIG_ARCH_OMAP2420 */ -+#endif /* CONFIG_SOC_OMAP2420 */ - - - /* - * 2430-only clockdomains - */ - --#if defined(CONFIG_ARCH_OMAP2430) -+#if defined(CONFIG_SOC_OMAP2430) - - static struct clockdomain mpu_2430_clkdm = { - .name = "mpu_clkdm", -@@ -600,7 +600,7 @@ - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), - }; - --#endif /* CONFIG_ARCH_OMAP2430 */ -+#endif /* CONFIG_SOC_OMAP2430 */ - - - /* -@@ -811,7 +811,7 @@ - &cm_clkdm, - &prm_clkdm, - --#ifdef CONFIG_ARCH_OMAP2420 -+#ifdef CONFIG_SOC_OMAP2420 - &mpu_2420_clkdm, - &iva1_2420_clkdm, - &dsp_2420_clkdm, -@@ -821,7 +821,7 @@ - &dss_2420_clkdm, - #endif - --#ifdef CONFIG_ARCH_OMAP2430 -+#ifdef CONFIG_SOC_OMAP2430 - &mpu_2430_clkdm, - &mdm_clkdm, - &dsp_2430_clkdm, -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/common.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/common.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/common.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/common.c 2011-03-09 13:19:09.813507562 +0100 -@@ -40,7 +40,7 @@ - - #endif - --#if defined(CONFIG_ARCH_OMAP2420) -+#if defined(CONFIG_SOC_OMAP2420) - - static struct omap_globals omap242x_globals = { - .class = OMAP242X_CLASS, -@@ -61,7 +61,7 @@ - } - #endif - --#if defined(CONFIG_ARCH_OMAP2430) -+#if defined(CONFIG_SOC_OMAP2430) - - static struct omap_globals omap243x_globals = { - .class = OMAP243X_CLASS, -@@ -108,6 +108,27 @@ - omap2_set_globals_3xxx(); - omap34xx_map_common_io(); - } -+ -+/* -+ * Adjust TAP register base such that omap3_check_revision accesses the correct -+ * TI816X register for checking device ID (it adds 0x204 to tap base while -+ * TI816X DEVICE ID register is at offset 0x600 from control base). -+ */ -+#define TI816X_TAP_BASE (TI816X_CTRL_BASE + \ -+ TI816X_CONTROL_DEVICE_ID - 0x204) -+ -+static struct omap_globals ti816x_globals = { -+ .class = OMAP343X_CLASS, -+ .tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE), -+ .ctrl = TI816X_CTRL_BASE, -+ .prm = TI816X_PRCM_BASE, -+ .cm = TI816X_PRCM_BASE, -+}; -+ -+void __init omap2_set_globals_ti816x(void) -+{ -+ __omap2_set_globals(&ti816x_globals); -+} - #endif - - #if defined(CONFIG_ARCH_OMAP4) -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/control.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/control.h ---- linux-2.6.38-rc7/arch/arm/mach-omap2/control.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/control.h 2011-03-09 13:19:09.813507562 +0100 -@@ -52,6 +52,9 @@ - #define OMAP343X_CONTROL_PADCONFS_WKUP 0xa00 - #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 - -+/* TI816X spefic control submodules */ -+#define TI816X_CONTROL_DEVCONF 0x600 -+ - /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ - - #define OMAP2_CONTROL_SYSCONFIG (OMAP2_CONTROL_INTERFACE + 0x10) -@@ -241,6 +244,9 @@ - #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 - #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 - -+/* TI816X CONTROL_DEVCONF register offsets */ -+#define TI816X_CONTROL_DEVICE_ID (TI816X_CONTROL_DEVCONF + 0x000) -+ - /* - * REVISIT: This list of registers is not comprehensive - there are more - * that should be added. -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/devices.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/devices.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/devices.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/devices.c 2011-03-09 13:19:09.814507541 +0100 -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -30,6 +31,7 @@ - #include - #include - #include -+#include - - #include "mux.h" - #include "control.h" -@@ -141,96 +143,70 @@ - } - #endif - --#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) -- --#define MBOX_REG_SIZE 0x120 -- --#ifdef CONFIG_ARCH_OMAP2 --static struct resource omap2_mbox_resources[] = { -+struct omap_device_pm_latency omap_keyboard_latency[] = { - { -- .start = OMAP24XX_MAILBOX_BASE, -- .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, -- .flags = IORESOURCE_MEM, -- }, -- { -- .start = INT_24XX_MAIL_U0_MPU, -- .flags = IORESOURCE_IRQ, -- .name = "dsp", -- }, -- { -- .start = INT_24XX_MAIL_U3_MPU, -- .flags = IORESOURCE_IRQ, -- .name = "iva", -+ .deactivate_func = omap_device_idle_hwmods, -+ .activate_func = omap_device_enable_hwmods, -+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, - }, - }; --static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources); --#else --#define omap2_mbox_resources NULL --#define omap2_mbox_resources_sz 0 --#endif - --#ifdef CONFIG_ARCH_OMAP3 --static struct resource omap3_mbox_resources[] = { -- { -- .start = OMAP34XX_MAILBOX_BASE, -- .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, -- .flags = IORESOURCE_MEM, -- }, -- { -- .start = INT_24XX_MAIL_U0_MPU, -- .flags = IORESOURCE_IRQ, -- .name = "dsp", -- }, --}; --static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources); --#else --#define omap3_mbox_resources NULL --#define omap3_mbox_resources_sz 0 --#endif -+int __init omap4_keyboard_init(struct omap4_keypad_platform_data -+ *sdp4430_keypad_data) -+{ -+ struct omap_device *od; -+ struct omap_hwmod *oh; -+ struct omap4_keypad_platform_data *keypad_data; -+ unsigned int id = -1; -+ char *oh_name = "kbd"; -+ char *name = "omap4-keypad"; - --#ifdef CONFIG_ARCH_OMAP4 -+ oh = omap_hwmod_lookup(oh_name); -+ if (!oh) { -+ pr_err("Could not look up %s\n", oh_name); -+ return -ENODEV; -+ } - --#define OMAP4_MBOX_REG_SIZE 0x130 --static struct resource omap4_mbox_resources[] = { -- { -- .start = OMAP44XX_MAILBOX_BASE, -- .end = OMAP44XX_MAILBOX_BASE + -- OMAP4_MBOX_REG_SIZE - 1, -- .flags = IORESOURCE_MEM, -- }, -- { -- .start = OMAP44XX_IRQ_MAIL_U0, -- .flags = IORESOURCE_IRQ, -- .name = "mbox", -- }, --}; --static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources); --#else --#define omap4_mbox_resources NULL --#define omap4_mbox_resources_sz 0 --#endif -+ keypad_data = sdp4430_keypad_data; - --static struct platform_device mbox_device = { -- .name = "omap-mailbox", -- .id = -1, -+ od = omap_device_build(name, id, oh, keypad_data, -+ sizeof(struct omap4_keypad_platform_data), -+ omap_keyboard_latency, -+ ARRAY_SIZE(omap_keyboard_latency), 0); -+ -+ if (IS_ERR(od)) { -+ WARN(1, "Cant build omap_device for %s:%s.\n", -+ name, oh->name); -+ return PTR_ERR(od); -+ } -+ -+ return 0; -+} -+ -+#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) -+static struct omap_device_pm_latency mbox_latencies[] = { -+ [0] = { -+ .activate_func = omap_device_enable_hwmods, -+ .deactivate_func = omap_device_idle_hwmods, -+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, -+ }, - }; - - static inline void omap_init_mbox(void) - { -- if (cpu_is_omap24xx()) { -- mbox_device.resource = omap2_mbox_resources; -- mbox_device.num_resources = omap2_mbox_resources_sz; -- } else if (cpu_is_omap34xx()) { -- mbox_device.resource = omap3_mbox_resources; -- mbox_device.num_resources = omap3_mbox_resources_sz; -- } else if (cpu_is_omap44xx()) { -- mbox_device.resource = omap4_mbox_resources; -- mbox_device.num_resources = omap4_mbox_resources_sz; -- } else { -- pr_err("%s: platform not supported\n", __func__); -+ struct omap_hwmod *oh; -+ struct omap_device *od; -+ -+ oh = omap_hwmod_lookup("mailbox"); -+ if (!oh) { -+ pr_err("%s: unable to find hwmod\n", __func__); - return; - } -- platform_device_register(&mbox_device); -+ -+ od = omap_device_build("omap-mailbox", -1, oh, NULL, 0, -+ mbox_latencies, ARRAY_SIZE(mbox_latencies), 0); -+ WARN(IS_ERR(od), "%s: could not build device, err %ld\n", -+ __func__, PTR_ERR(od)); - } - #else - static inline void omap_init_mbox(void) { } -@@ -279,163 +255,55 @@ - - #include - --#define OMAP2_MCSPI1_BASE 0x48098000 --#define OMAP2_MCSPI2_BASE 0x4809a000 --#define OMAP2_MCSPI3_BASE 0x480b8000 --#define OMAP2_MCSPI4_BASE 0x480ba000 -- --#define OMAP4_MCSPI1_BASE 0x48098100 --#define OMAP4_MCSPI2_BASE 0x4809a100 --#define OMAP4_MCSPI3_BASE 0x480b8100 --#define OMAP4_MCSPI4_BASE 0x480ba100 -- --static struct omap2_mcspi_platform_config omap2_mcspi1_config = { -- .num_cs = 4, --}; -- --static struct resource omap2_mcspi1_resources[] = { -- { -- .start = OMAP2_MCSPI1_BASE, -- .end = OMAP2_MCSPI1_BASE + 0xff, -- .flags = IORESOURCE_MEM, -- }, --}; -- --static struct platform_device omap2_mcspi1 = { -- .name = "omap2_mcspi", -- .id = 1, -- .num_resources = ARRAY_SIZE(omap2_mcspi1_resources), -- .resource = omap2_mcspi1_resources, -- .dev = { -- .platform_data = &omap2_mcspi1_config, -- }, --}; -- --static struct omap2_mcspi_platform_config omap2_mcspi2_config = { -- .num_cs = 2, --}; -- --static struct resource omap2_mcspi2_resources[] = { -- { -- .start = OMAP2_MCSPI2_BASE, -- .end = OMAP2_MCSPI2_BASE + 0xff, -- .flags = IORESOURCE_MEM, -- }, --}; -- --static struct platform_device omap2_mcspi2 = { -- .name = "omap2_mcspi", -- .id = 2, -- .num_resources = ARRAY_SIZE(omap2_mcspi2_resources), -- .resource = omap2_mcspi2_resources, -- .dev = { -- .platform_data = &omap2_mcspi2_config, -- }, --}; -- --#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ -- defined(CONFIG_ARCH_OMAP4) --static struct omap2_mcspi_platform_config omap2_mcspi3_config = { -- .num_cs = 2, --}; -- --static struct resource omap2_mcspi3_resources[] = { -- { -- .start = OMAP2_MCSPI3_BASE, -- .end = OMAP2_MCSPI3_BASE + 0xff, -- .flags = IORESOURCE_MEM, -- }, --}; -- --static struct platform_device omap2_mcspi3 = { -- .name = "omap2_mcspi", -- .id = 3, -- .num_resources = ARRAY_SIZE(omap2_mcspi3_resources), -- .resource = omap2_mcspi3_resources, -- .dev = { -- .platform_data = &omap2_mcspi3_config, -- }, --}; --#endif -- --#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) --static struct omap2_mcspi_platform_config omap2_mcspi4_config = { -- .num_cs = 1, --}; -- --static struct resource omap2_mcspi4_resources[] = { -- { -- .start = OMAP2_MCSPI4_BASE, -- .end = OMAP2_MCSPI4_BASE + 0xff, -- .flags = IORESOURCE_MEM, -- }, --}; -- --static struct platform_device omap2_mcspi4 = { -- .name = "omap2_mcspi", -- .id = 4, -- .num_resources = ARRAY_SIZE(omap2_mcspi4_resources), -- .resource = omap2_mcspi4_resources, -- .dev = { -- .platform_data = &omap2_mcspi4_config, -+struct omap_device_pm_latency omap_mcspi_latency[] = { -+ [0] = { -+ .deactivate_func = omap_device_idle_hwmods, -+ .activate_func = omap_device_enable_hwmods, -+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, - }, - }; --#endif - --#ifdef CONFIG_ARCH_OMAP4 --static inline void omap4_mcspi_fixup(void) --{ -- omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE; -- omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff; -- omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE; -- omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff; -- omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE; -- omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff; -- omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE; -- omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff; --} --#else --static inline void omap4_mcspi_fixup(void) --{ --} --#endif -- --#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ -- defined(CONFIG_ARCH_OMAP4) --static inline void omap2_mcspi3_init(void) --{ -- platform_device_register(&omap2_mcspi3); --} --#else --static inline void omap2_mcspi3_init(void) -+static int omap_mcspi_init(struct omap_hwmod *oh, void *unused) - { --} --#endif -+ struct omap_device *od; -+ char *name = "omap2_mcspi"; -+ struct omap2_mcspi_platform_config *pdata; -+ static int spi_num; -+ struct omap2_mcspi_dev_attr *mcspi_attrib = oh->dev_attr; -+ -+ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); -+ if (!pdata) { -+ pr_err("Memory allocation for McSPI device failed\n"); -+ return -ENOMEM; -+ } -+ -+ pdata->num_cs = mcspi_attrib->num_chipselect; -+ switch (oh->class->rev) { -+ case OMAP2_MCSPI_REV: -+ case OMAP3_MCSPI_REV: -+ pdata->regs_offset = 0; -+ break; -+ case OMAP4_MCSPI_REV: -+ pdata->regs_offset = OMAP4_MCSPI_REG_OFFSET; -+ break; -+ default: -+ pr_err("Invalid McSPI Revision value\n"); -+ return -EINVAL; -+ } - --#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) --static inline void omap2_mcspi4_init(void) --{ -- platform_device_register(&omap2_mcspi4); --} --#else --static inline void omap2_mcspi4_init(void) --{ -+ spi_num++; -+ od = omap_device_build(name, spi_num, oh, pdata, -+ sizeof(*pdata), omap_mcspi_latency, -+ ARRAY_SIZE(omap_mcspi_latency), 0); -+ WARN(IS_ERR(od), "Cant build omap_device for %s:%s\n", -+ name, oh->name); -+ kfree(pdata); -+ return 0; - } --#endif - - static void omap_init_mcspi(void) - { -- if (cpu_is_omap44xx()) -- omap4_mcspi_fixup(); -- -- platform_device_register(&omap2_mcspi1); -- platform_device_register(&omap2_mcspi2); -- -- if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx()) -- omap2_mcspi3_init(); -- -- if (cpu_is_omap343x() || cpu_is_omap44xx()) -- omap2_mcspi4_init(); -+ omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL); - } - - #else -@@ -610,117 +478,10 @@ - - /*-------------------------------------------------------------------------*/ - --#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) -- --#define MMCHS_SYSCONFIG 0x0010 --#define MMCHS_SYSCONFIG_SWRESET (1 << 1) --#define MMCHS_SYSSTATUS 0x0014 --#define MMCHS_SYSSTATUS_RESETDONE (1 << 0) -- --static struct platform_device dummy_pdev = { -- .dev = { -- .bus = &platform_bus_type, -- }, --}; -+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) - --/** -- * omap_hsmmc_reset() - Full reset of each HS-MMC controller -- * -- * Ensure that each MMC controller is fully reset. Controllers -- * left in an unknown state (by bootloader) may prevent retention -- * or OFF-mode. This is especially important in cases where the -- * MMC driver is not enabled, _or_ built as a module. -- * -- * In order for reset to work, interface, functional and debounce -- * clocks must be enabled. The debounce clock comes from func_32k_clk -- * and is not under SW control, so we only enable i- and f-clocks. -- **/ --static void __init omap_hsmmc_reset(void) --{ -- u32 i, nr_controllers; -- struct clk *iclk, *fclk; -- -- if (cpu_is_omap242x()) -- return; -- -- nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC : -- (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC); -- -- for (i = 0; i < nr_controllers; i++) { -- u32 v, base = 0; -- struct device *dev = &dummy_pdev.dev; -- -- switch (i) { -- case 0: -- base = OMAP2_MMC1_BASE; -- break; -- case 1: -- base = OMAP2_MMC2_BASE; -- break; -- case 2: -- base = OMAP3_MMC3_BASE; -- break; -- case 3: -- if (!cpu_is_omap44xx()) -- return; -- base = OMAP4_MMC4_BASE; -- break; -- case 4: -- if (!cpu_is_omap44xx()) -- return; -- base = OMAP4_MMC5_BASE; -- break; -- } -- -- if (cpu_is_omap44xx()) -- base += OMAP4_MMC_REG_OFFSET; -- -- dummy_pdev.id = i; -- dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i); -- iclk = clk_get(dev, "ick"); -- if (IS_ERR(iclk)) -- goto err1; -- if (clk_enable(iclk)) -- goto err2; -- -- fclk = clk_get(dev, "fck"); -- if (IS_ERR(fclk)) -- goto err3; -- if (clk_enable(fclk)) -- goto err4; -- -- omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG); -- v = omap_readl(base + MMCHS_SYSSTATUS); -- while (!(omap_readl(base + MMCHS_SYSSTATUS) & -- MMCHS_SYSSTATUS_RESETDONE)) -- cpu_relax(); -- -- clk_disable(fclk); -- clk_put(fclk); -- clk_disable(iclk); -- clk_put(iclk); -- } -- return; -- --err4: -- clk_put(fclk); --err3: -- clk_disable(iclk); --err2: -- clk_put(iclk); --err1: -- printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, " -- "cannot reset.\n", __func__, i); --} --#else --static inline void omap_hsmmc_reset(void) {} --#endif -- --#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ -- defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) -- --static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller, -- int controller_nr) -+static inline void omap242x_mmc_mux(struct omap_mmc_platform_data -+ *mmc_controller) - { - if ((mmc_controller->slots[0].switch_pin > 0) && \ - (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) -@@ -731,163 +492,44 @@ - omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, - OMAP_PIN_INPUT_PULLUP); - -- if (cpu_is_omap2420() && controller_nr == 0) { -- omap_mux_init_signal("sdmmc_cmd", 0); -- omap_mux_init_signal("sdmmc_clki", 0); -- omap_mux_init_signal("sdmmc_clko", 0); -- omap_mux_init_signal("sdmmc_dat0", 0); -- omap_mux_init_signal("sdmmc_dat_dir0", 0); -- omap_mux_init_signal("sdmmc_cmd_dir", 0); -- if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { -- omap_mux_init_signal("sdmmc_dat1", 0); -- omap_mux_init_signal("sdmmc_dat2", 0); -- omap_mux_init_signal("sdmmc_dat3", 0); -- omap_mux_init_signal("sdmmc_dat_dir1", 0); -- omap_mux_init_signal("sdmmc_dat_dir2", 0); -- omap_mux_init_signal("sdmmc_dat_dir3", 0); -- } -- -- /* -- * Use internal loop-back in MMC/SDIO Module Input Clock -- * selection -- */ -- if (mmc_controller->slots[0].internal_clock) { -- u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); -- v |= (1 << 24); -- omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); -- } -- } -- -- if (cpu_is_omap34xx()) { -- if (controller_nr == 0) { -- omap_mux_init_signal("sdmmc1_clk", -- OMAP_PIN_INPUT_PULLUP); -- omap_mux_init_signal("sdmmc1_cmd", -- OMAP_PIN_INPUT_PULLUP); -- omap_mux_init_signal("sdmmc1_dat0", -- OMAP_PIN_INPUT_PULLUP); -- if (mmc_controller->slots[0].caps & -- (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { -- omap_mux_init_signal("sdmmc1_dat1", -- OMAP_PIN_INPUT_PULLUP); -- omap_mux_init_signal("sdmmc1_dat2", -- OMAP_PIN_INPUT_PULLUP); -- omap_mux_init_signal("sdmmc1_dat3", -- OMAP_PIN_INPUT_PULLUP); -- } -- if (mmc_controller->slots[0].caps & -- MMC_CAP_8_BIT_DATA) { -- omap_mux_init_signal("sdmmc1_dat4", -- OMAP_PIN_INPUT_PULLUP); -- omap_mux_init_signal("sdmmc1_dat5", -- OMAP_PIN_INPUT_PULLUP); -- omap_mux_init_signal("sdmmc1_dat6", -- OMAP_PIN_INPUT_PULLUP); -- omap_mux_init_signal("sdmmc1_dat7", -- OMAP_PIN_INPUT_PULLUP); -- } -- } -- if (controller_nr == 1) { -- /* MMC2 */ -- omap_mux_init_signal("sdmmc2_clk", -- OMAP_PIN_INPUT_PULLUP); -- omap_mux_init_signal("sdmmc2_cmd", -- OMAP_PIN_INPUT_PULLUP); -- omap_mux_init_signal("sdmmc2_dat0", -- OMAP_PIN_INPUT_PULLUP); -- -- /* -- * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed -- * in the board-*.c files -- */ -- if (mmc_controller->slots[0].caps & -- (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { -- omap_mux_init_signal("sdmmc2_dat1", -- OMAP_PIN_INPUT_PULLUP); -- omap_mux_init_signal("sdmmc2_dat2", -- OMAP_PIN_INPUT_PULLUP); -- omap_mux_init_signal("sdmmc2_dat3", -- OMAP_PIN_INPUT_PULLUP); -- } -- if (mmc_controller->slots[0].caps & -- MMC_CAP_8_BIT_DATA) { -- omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", -- OMAP_PIN_INPUT_PULLUP); -- omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", -- OMAP_PIN_INPUT_PULLUP); -- omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6", -- OMAP_PIN_INPUT_PULLUP); -- omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7", -- OMAP_PIN_INPUT_PULLUP); -- } -- } -+ omap_mux_init_signal("sdmmc_cmd", 0); -+ omap_mux_init_signal("sdmmc_clki", 0); -+ omap_mux_init_signal("sdmmc_clko", 0); -+ omap_mux_init_signal("sdmmc_dat0", 0); -+ omap_mux_init_signal("sdmmc_dat_dir0", 0); -+ omap_mux_init_signal("sdmmc_cmd_dir", 0); -+ if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { -+ omap_mux_init_signal("sdmmc_dat1", 0); -+ omap_mux_init_signal("sdmmc_dat2", 0); -+ omap_mux_init_signal("sdmmc_dat3", 0); -+ omap_mux_init_signal("sdmmc_dat_dir1", 0); -+ omap_mux_init_signal("sdmmc_dat_dir2", 0); -+ omap_mux_init_signal("sdmmc_dat_dir3", 0); -+ } - -- /* -- * For MMC3 the pins need to be muxed in the board-*.c files -- */ -+ /* -+ * Use internal loop-back in MMC/SDIO Module Input Clock -+ * selection -+ */ -+ if (mmc_controller->slots[0].internal_clock) { -+ u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); -+ v |= (1 << 24); -+ omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); - } - } - --void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, -- int nr_controllers) -+void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) - { -- int i; -- char *name; -- -- for (i = 0; i < nr_controllers; i++) { -- unsigned long base, size; -- unsigned int irq = 0; -- -- if (!mmc_data[i]) -- continue; -+ char *name = "mmci-omap"; - -- omap2_mmc_mux(mmc_data[i], i); -+ if (!mmc_data[0]) { -+ pr_err("%s fails: Incomplete platform data\n", __func__); -+ return; -+ } - -- switch (i) { -- case 0: -- base = OMAP2_MMC1_BASE; -- irq = INT_24XX_MMC_IRQ; -- break; -- case 1: -- base = OMAP2_MMC2_BASE; -- irq = INT_24XX_MMC2_IRQ; -- break; -- case 2: -- if (!cpu_is_omap44xx() && !cpu_is_omap34xx()) -- return; -- base = OMAP3_MMC3_BASE; -- irq = INT_34XX_MMC3_IRQ; -- break; -- case 3: -- if (!cpu_is_omap44xx()) -- return; -- base = OMAP4_MMC4_BASE; -- irq = OMAP44XX_IRQ_MMC4; -- break; -- case 4: -- if (!cpu_is_omap44xx()) -- return; -- base = OMAP4_MMC5_BASE; -- irq = OMAP44XX_IRQ_MMC5; -- break; -- default: -- continue; -- } -- -- if (cpu_is_omap2420()) { -- size = OMAP2420_MMC_SIZE; -- name = "mmci-omap"; -- } else if (cpu_is_omap44xx()) { -- if (i < 3) -- irq += OMAP44XX_IRQ_GIC_START; -- size = OMAP4_HSMMC_SIZE; -- name = "mmci-omap-hs"; -- } else { -- size = OMAP3_HSMMC_SIZE; -- name = "mmci-omap-hs"; -- } -- omap_mmc_add(name, i, base, size, irq, mmc_data[i]); -- }; -+ omap242x_mmc_mux(mmc_data[0]); -+ omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE, -+ INT_24XX_MMC_IRQ, mmc_data[0]); - } - - #endif -@@ -895,7 +537,7 @@ - /*-------------------------------------------------------------------------*/ - - #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE) --#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) -+#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) - #define OMAP_HDQ_BASE 0x480B2000 - #endif - static struct resource omap_hdq_resources[] = { -@@ -961,7 +603,6 @@ - * please keep these calls, and their implementations above, - * in alphabetical order so they're easier to sort through. - */ -- omap_hsmmc_reset(); - omap_init_audio(); - omap_init_camera(); - omap_init_mbox(); -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/display.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/display.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/display.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/display.c 2011-03-09 13:19:09.814507541 +0100 -@@ -0,0 +1,125 @@ -+/* -+ * OMAP2plus display device setup / initialization. -+ * -+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -+ * Senthilvadivu Guruswamy -+ * Sumit Semwal -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any -+ * kind, whether express or implied; without even the implied warranty -+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+static struct platform_device omap_display_device = { -+ .name = "omapdss", -+ .id = -1, -+ .dev = { -+ .platform_data = NULL, -+ }, -+}; -+ -+static struct omap_device_pm_latency omap_dss_latency[] = { -+ [0] = { -+ .deactivate_func = omap_device_idle_hwmods, -+ .activate_func = omap_device_enable_hwmods, -+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, -+ }, -+}; -+ -+/* oh_core is used for getting opt-clocks */ -+static struct omap_hwmod *oh_core; -+ -+static bool opt_clock_available(const char *clk_role) -+{ -+ int i; -+ -+ for (i = 0; i < oh_core->opt_clks_cnt; i++) { -+ if (!strcmp(oh_core->opt_clks[i].role, clk_role)) -+ return true; -+ } -+ return false; -+} -+ -+int __init omap_display_init(struct omap_dss_board_info *board_data) -+{ -+ int r = 0; -+ struct omap_hwmod *oh; -+ struct omap_device *od; -+ int i; -+ struct omap_display_platform_data pdata; -+ -+ /* -+ * omap: valid DSS hwmod names -+ * omap2,3,4: dss_core, dss_dispc, dss_rfbi, dss_venc -+ * omap3,4: dss_dsi1 -+ * omap4: dss_dsi2, dss_hdmi -+ */ -+ char *oh_name[] = { "dss_core", "dss_dispc", "dss_rfbi", "dss_venc", -+ "dss_dsi1", "dss_dsi2", "dss_hdmi" }; -+ char *dev_name[] = { "omapdss_dss", "omapdss_dispc", "omapdss_rfbi", -+ "omapdss_venc", "omapdss_dsi1", "omapdss_dsi2", -+ "omapdss_hdmi" }; -+ int oh_count; -+ -+ memset(&pdata, 0, sizeof(pdata)); -+ -+ if (cpu_is_omap24xx()) -+ oh_count = ARRAY_SIZE(oh_name) - 3; -+ /* last 3 hwmod dev in oh_name are not available for omap2 */ -+ else if (cpu_is_omap44xx()) -+ oh_count = ARRAY_SIZE(oh_name); -+ else -+ oh_count = ARRAY_SIZE(oh_name) - 2; -+ /* last 2 hwmod dev in oh_name are not available for omap3 */ -+ -+ /* opt_clks are always associated with dss hwmod */ -+ oh_core = omap_hwmod_lookup("dss_core"); -+ if (!oh_core) { -+ pr_err("Could not look up dss_core.\n"); -+ return -ENODEV; -+ } -+ -+ pdata.board_data = board_data; -+ pdata.board_data->get_last_off_on_transaction_id = NULL; -+ pdata.opt_clock_available = opt_clock_available; -+ -+ for (i = 0; i < oh_count; i++) { -+ oh = omap_hwmod_lookup(oh_name[i]); -+ if (!oh) { -+ pr_err("Could not look up %s\n", oh_name[i]); -+ return -ENODEV; -+ } -+ -+ od = omap_device_build(dev_name[i], -1, oh, &pdata, -+ sizeof(struct omap_display_platform_data), -+ omap_dss_latency, -+ ARRAY_SIZE(omap_dss_latency), 0); -+ -+ if (WARN((IS_ERR(od)), "Could not build omap_device for %s\n", -+ oh_name[i])) -+ return -ENODEV; -+ } -+ omap_display_device.dev.platform_data = board_data; -+ -+ r = platform_device_register(&omap_display_device); -+ if (r < 0) -+ printk(KERN_ERR "Unable to register OMAP-Display device\n"); -+ -+ return r; -+} -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/gpmc.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/gpmc.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/gpmc.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/gpmc.c 2011-03-09 13:19:09.816507499 +0100 -@@ -14,6 +14,7 @@ - */ - #undef DEBUG - -+#include - #include - #include - #include -@@ -22,6 +23,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -58,7 +60,6 @@ - #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ - #define GPMC_SECTION_SHIFT 28 /* 128 MB */ - --#define PREFETCH_FIFOTHRESHOLD (0x40 << 8) - #define CS_NUM_SHIFT 24 - #define ENABLE_PREFETCH (0x1 << 7) - #define DMA_MPU_MODE 2 -@@ -100,6 +101,8 @@ - - static struct clk *gpmc_l3_clk; - -+static irqreturn_t gpmc_handle_irq(int irq, void *dev); -+ - static void gpmc_write_reg(int idx, u32 val) - { - __raw_writel(val, gpmc_base + idx); -@@ -497,6 +500,10 @@ - u32 regval = 0; - - switch (cmd) { -+ case GPMC_ENABLE_IRQ: -+ gpmc_write_reg(GPMC_IRQENABLE, wval); -+ break; -+ - case GPMC_SET_IRQ_STATUS: - gpmc_write_reg(GPMC_IRQSTATUS, wval); - break; -@@ -598,15 +605,19 @@ - /** - * gpmc_prefetch_enable - configures and starts prefetch transfer - * @cs: cs (chip select) number -+ * @fifo_th: fifo threshold to be used for read/ write - * @dma_mode: dma mode enable (1) or disable (0) - * @u32_count: number of bytes to be transferred - * @is_write: prefetch read(0) or write post(1) mode - */ --int gpmc_prefetch_enable(int cs, int dma_mode, -+int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, - unsigned int u32_count, int is_write) - { - -- if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { -+ if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) { -+ pr_err("gpmc: fifo threshold is not supported\n"); -+ return -1; -+ } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) { - /* Set the amount of bytes to be prefetched */ - gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count); - -@@ -614,7 +625,7 @@ - * enable the engine. Set which cs is has requested for. - */ - gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) | -- PREFETCH_FIFOTHRESHOLD | -+ PREFETCH_FIFOTHRESHOLD(fifo_th) | - ENABLE_PREFETCH | - (dma_mode << DMA_MPU_MODE) | - (0x1 & is_write))); -@@ -678,9 +689,10 @@ - } - } - --void __init gpmc_init(void) -+static int __init gpmc_init(void) - { -- u32 l; -+ u32 l, irq; -+ int cs, ret = -EINVAL; - char *ck = NULL; - - if (cpu_is_omap24xx()) { -@@ -698,7 +710,7 @@ - } - - if (WARN_ON(!ck)) -- return; -+ return ret; - - gpmc_l3_clk = clk_get(NULL, ck); - if (IS_ERR(gpmc_l3_clk)) { -@@ -723,6 +735,36 @@ - l |= (0x02 << 3) | (1 << 0); - gpmc_write_reg(GPMC_SYSCONFIG, l); - gpmc_mem_init(); -+ -+ /* initalize the irq_chained */ -+ irq = OMAP_GPMC_IRQ_BASE; -+ for (cs = 0; cs < GPMC_CS_NUM; cs++) { -+ set_irq_handler(irq, handle_simple_irq); -+ set_irq_flags(irq, IRQF_VALID); -+ irq++; -+ } -+ -+ ret = request_irq(INT_34XX_GPMC_IRQ, -+ gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base); -+ if (ret) -+ pr_err("gpmc: irq-%d could not claim: err %d\n", -+ INT_34XX_GPMC_IRQ, ret); -+ return ret; -+} -+postcore_initcall(gpmc_init); -+ -+static irqreturn_t gpmc_handle_irq(int irq, void *dev) -+{ -+ u8 cs; -+ -+ if (irq != INT_34XX_GPMC_IRQ) -+ return IRQ_HANDLED; -+ /* check cs to invoke the irq */ -+ cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7; -+ if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END) -+ generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs); -+ -+ return IRQ_HANDLED; - } - - #ifdef CONFIG_ARCH_OMAP3 -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/gpmc-nand.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/gpmc-nand.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/gpmc-nand.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/gpmc-nand.c 2011-03-09 13:19:09.815507520 +0100 -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - - #include - -@@ -69,8 +70,10 @@ - t.wr_cycle = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle); - - /* Configure GPMC */ -- gpmc_cs_configure(gpmc_nand_data->cs, -- GPMC_CONFIG_DEV_SIZE, gpmc_nand_data->devsize); -+ if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) -+ gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1); -+ else -+ gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0); - gpmc_cs_configure(gpmc_nand_data->cs, - GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND); - err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t); -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/gpmc-onenand.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/gpmc-onenand.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/gpmc-onenand.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/gpmc-onenand.c 2011-03-09 13:19:09.815507520 +0100 -@@ -94,7 +94,7 @@ - } - - static void set_onenand_cfg(void __iomem *onenand_base, int latency, -- int sync_read, int sync_write, int hf) -+ int sync_read, int sync_write, int hf, int vhf) - { - u32 reg; - -@@ -114,12 +114,57 @@ - reg |= ONENAND_SYS_CFG1_HF; - else - reg &= ~ONENAND_SYS_CFG1_HF; -+ if (vhf) -+ reg |= ONENAND_SYS_CFG1_VHF; -+ else -+ reg &= ~ONENAND_SYS_CFG1_VHF; - writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); - } - -+static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg, -+ void __iomem *onenand_base, bool *clk_dep) -+{ -+ u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID); -+ int freq = 0; -+ -+ if (cfg->get_freq) { -+ struct onenand_freq_info fi; -+ -+ fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID); -+ fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID); -+ fi.ver_id = ver; -+ freq = cfg->get_freq(&fi, clk_dep); -+ if (freq) -+ return freq; -+ } -+ -+ switch ((ver >> 4) & 0xf) { -+ case 0: -+ freq = 40; -+ break; -+ case 1: -+ freq = 54; -+ break; -+ case 2: -+ freq = 66; -+ break; -+ case 3: -+ freq = 83; -+ break; -+ case 4: -+ freq = 104; -+ break; -+ default: -+ freq = 54; -+ break; -+ } -+ -+ return freq; -+} -+ - static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, - void __iomem *onenand_base, -- int freq) -+ int *freq_ptr) - { - struct gpmc_timings t; - const int t_cer = 15; -@@ -130,10 +175,11 @@ - const int t_wph = 30; - int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; - int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency; -- int first_time = 0, hf = 0, sync_read = 0, sync_write = 0; -+ int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0; - int err, ticks_cez; -- int cs = cfg->cs; -+ int cs = cfg->cs, freq = *freq_ptr; - u32 reg; -+ bool clk_dep = false; - - if (cfg->flags & ONENAND_SYNC_READ) { - sync_read = 1; -@@ -148,27 +194,7 @@ - err = omap2_onenand_set_async_mode(cs, onenand_base); - if (err) - return err; -- reg = readw(onenand_base + ONENAND_REG_VERSION_ID); -- switch ((reg >> 4) & 0xf) { -- case 0: -- freq = 40; -- break; -- case 1: -- freq = 54; -- break; -- case 2: -- freq = 66; -- break; -- case 3: -- freq = 83; -- break; -- case 4: -- freq = 104; -- break; -- default: -- freq = 54; -- break; -- } -+ freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep); - first_time = 1; - } - -@@ -180,7 +206,7 @@ - t_avdh = 2; - t_ach = 3; - t_aavdh = 6; -- t_rdyo = 9; -+ t_rdyo = 6; - break; - case 83: - min_gpmc_clk_period = 12000; /* 83 MHz */ -@@ -217,16 +243,36 @@ - gpmc_clk_ns = gpmc_ticks_to_ns(div); - if (gpmc_clk_ns < 15) /* >66Mhz */ - hf = 1; -- if (hf) -+ if (gpmc_clk_ns < 12) /* >83Mhz */ -+ vhf = 1; -+ if (vhf) -+ latency = 8; -+ else if (hf) - latency = 6; - else if (gpmc_clk_ns >= 25) /* 40 MHz*/ - latency = 3; - else - latency = 4; - -+ if (clk_dep) { -+ if (gpmc_clk_ns < 12) { /* >83Mhz */ -+ t_ces = 3; -+ t_avds = 4; -+ } else if (gpmc_clk_ns < 15) { /* >66Mhz */ -+ t_ces = 5; -+ t_avds = 4; -+ } else if (gpmc_clk_ns < 25) { /* >40Mhz */ -+ t_ces = 6; -+ t_avds = 5; -+ } else { -+ t_ces = 7; -+ t_avds = 7; -+ } -+ } -+ - if (first_time) - set_onenand_cfg(onenand_base, latency, -- sync_read, sync_write, hf); -+ sync_read, sync_write, hf, vhf); - - if (div == 1) { - reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2); -@@ -264,6 +310,9 @@ - /* Read */ - t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh)); - t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach)); -+ /* Force at least 1 clk between AVD High to OE Low */ -+ if (t.oe_on <= t.adv_rd_off) -+ t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1); - t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div); - t.oe_off = t.access + gpmc_round_ns_to_ticks(1); - t.cs_rd_off = t.oe_off; -@@ -317,18 +366,20 @@ - if (err) - return err; - -- set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf); -+ set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf); -+ -+ *freq_ptr = freq; - - return 0; - } - --static int gpmc_onenand_setup(void __iomem *onenand_base, int freq) -+static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) - { - struct device *dev = &gpmc_onenand_device.dev; - - /* Set sync timings in GPMC */ - if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base, -- freq) < 0) { -+ freq_ptr) < 0) { - dev_err(dev, "Unable to set synchronous mode\n"); - return -EINVAL; - } -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/hsmmc.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/hsmmc.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/hsmmc.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/hsmmc.c 2011-03-09 13:19:09.816507499 +0100 -@@ -16,7 +16,10 @@ - #include - #include - #include -+#include -+#include - -+#include "mux.h" - #include "hsmmc.h" - #include "control.h" - -@@ -28,10 +31,6 @@ - - #define HSMMC_NAME_LEN 9 - --static struct hsmmc_controller { -- char name[HSMMC_NAME_LEN + 1]; --} hsmmc[OMAP34XX_NR_MMC]; -- - #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) - - static int hsmmc_get_context_loss(struct device *dev) -@@ -204,13 +203,284 @@ - return 0; - } - --static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; -+static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller, -+ int controller_nr) -+{ -+ if ((mmc_controller->slots[0].switch_pin > 0) && \ -+ (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) -+ omap_mux_init_gpio(mmc_controller->slots[0].switch_pin, -+ OMAP_PIN_INPUT_PULLUP); -+ if ((mmc_controller->slots[0].gpio_wp > 0) && \ -+ (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES)) -+ omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, -+ OMAP_PIN_INPUT_PULLUP); -+ if (cpu_is_omap34xx()) { -+ if (controller_nr == 0) { -+ omap_mux_init_signal("sdmmc1_clk", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("sdmmc1_cmd", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("sdmmc1_dat0", -+ OMAP_PIN_INPUT_PULLUP); -+ if (mmc_controller->slots[0].caps & -+ (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { -+ omap_mux_init_signal("sdmmc1_dat1", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("sdmmc1_dat2", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("sdmmc1_dat3", -+ OMAP_PIN_INPUT_PULLUP); -+ } -+ if (mmc_controller->slots[0].caps & -+ MMC_CAP_8_BIT_DATA) { -+ omap_mux_init_signal("sdmmc1_dat4", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("sdmmc1_dat5", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("sdmmc1_dat6", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("sdmmc1_dat7", -+ OMAP_PIN_INPUT_PULLUP); -+ } -+ } -+ if (controller_nr == 1) { -+ /* MMC2 */ -+ omap_mux_init_signal("sdmmc2_clk", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("sdmmc2_cmd", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("sdmmc2_dat0", -+ OMAP_PIN_INPUT_PULLUP); -+ -+ /* -+ * For 8 wire configurations, Lines DAT4, 5, 6 and 7 -+ * need to be muxed in the board-*.c files -+ */ -+ if (mmc_controller->slots[0].caps & -+ (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) { -+ omap_mux_init_signal("sdmmc2_dat1", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("sdmmc2_dat2", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("sdmmc2_dat3", -+ OMAP_PIN_INPUT_PULLUP); -+ } -+ if (mmc_controller->slots[0].caps & -+ MMC_CAP_8_BIT_DATA) { -+ omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7", -+ OMAP_PIN_INPUT_PULLUP); -+ } -+ } -+ -+ /* -+ * For MMC3 the pins need to be muxed in the board-*.c files -+ */ -+ } -+} -+ -+static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c, -+ struct omap_mmc_platform_data *mmc) -+{ -+ char *hc_name; -+ -+ hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL); -+ if (!hc_name) { -+ pr_err("Cannot allocate memory for controller slot name\n"); -+ kfree(hc_name); -+ return -ENOMEM; -+ } -+ -+ if (c->name) -+ strncpy(hc_name, c->name, HSMMC_NAME_LEN); -+ else -+ snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i", -+ c->mmc, 1); -+ mmc->slots[0].name = hc_name; -+ mmc->nr_slots = 1; -+ mmc->slots[0].caps = c->caps; -+ mmc->slots[0].internal_clock = !c->ext_clock; -+ mmc->dma_mask = 0xffffffff; -+ if (cpu_is_omap44xx()) -+ mmc->reg_offset = OMAP4_MMC_REG_OFFSET; -+ else -+ mmc->reg_offset = 0; -+ -+ mmc->get_context_loss_count = hsmmc_get_context_loss; -+ -+ mmc->slots[0].switch_pin = c->gpio_cd; -+ mmc->slots[0].gpio_wp = c->gpio_wp; -+ -+ mmc->slots[0].remux = c->remux; -+ mmc->slots[0].init_card = c->init_card; -+ -+ if (c->cover_only) -+ mmc->slots[0].cover = 1; -+ -+ if (c->nonremovable) -+ mmc->slots[0].nonremovable = 1; -+ -+ if (c->power_saving) -+ mmc->slots[0].power_saving = 1; -+ -+ if (c->no_off) -+ mmc->slots[0].no_off = 1; -+ -+ if (c->vcc_aux_disable_is_sleep) -+ mmc->slots[0].vcc_aux_disable_is_sleep = 1; -+ -+ /* -+ * NOTE: MMC slots should have a Vcc regulator set up. -+ * This may be from a TWL4030-family chip, another -+ * controllable regulator, or a fixed supply. -+ * -+ * temporary HACK: ocr_mask instead of fixed supply -+ */ -+ mmc->slots[0].ocr_mask = c->ocr_mask; -+ -+ if (cpu_is_omap3517() || cpu_is_omap3505()) -+ mmc->slots[0].set_power = nop_mmc_set_power; -+ else -+ mmc->slots[0].features |= HSMMC_HAS_PBIAS; -+ -+ if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) -+ mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; -+ -+ switch (c->mmc) { -+ case 1: -+ if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { -+ /* on-chip level shifting via PBIAS0/PBIAS1 */ -+ if (cpu_is_omap44xx()) { -+ mmc->slots[0].before_set_reg = -+ omap4_hsmmc1_before_set_reg; -+ mmc->slots[0].after_set_reg = -+ omap4_hsmmc1_after_set_reg; -+ } else { -+ mmc->slots[0].before_set_reg = -+ omap_hsmmc1_before_set_reg; -+ mmc->slots[0].after_set_reg = -+ omap_hsmmc1_after_set_reg; -+ } -+ } -+ -+ /* OMAP3630 HSMMC1 supports only 4-bit */ -+ if (cpu_is_omap3630() && -+ (c->caps & MMC_CAP_8_BIT_DATA)) { -+ c->caps &= ~MMC_CAP_8_BIT_DATA; -+ c->caps |= MMC_CAP_4_BIT_DATA; -+ mmc->slots[0].caps = c->caps; -+ } -+ break; -+ case 2: -+ if (c->ext_clock) -+ c->transceiver = 1; -+ if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { -+ c->caps &= ~MMC_CAP_8_BIT_DATA; -+ c->caps |= MMC_CAP_4_BIT_DATA; -+ } -+ /* FALLTHROUGH */ -+ case 3: -+ if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { -+ /* off-chip level shifting, or none */ -+ mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; -+ mmc->slots[0].after_set_reg = NULL; -+ } -+ break; -+ case 4: -+ case 5: -+ mmc->slots[0].before_set_reg = NULL; -+ mmc->slots[0].after_set_reg = NULL; -+ break; -+ default: -+ pr_err("MMC%d configuration not supported!\n", c->mmc); -+ kfree(hc_name); -+ return -ENODEV; -+ } -+ return 0; -+} -+ -+static struct omap_device_pm_latency omap_hsmmc_latency[] = { -+ [0] = { -+ .deactivate_func = omap_device_idle_hwmods, -+ .activate_func = omap_device_enable_hwmods, -+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, -+ }, -+ /* -+ * XXX There should also be an entry here to power off/on the -+ * MMC regulators/PBIAS cells, etc. -+ */ -+}; -+ -+#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16 -+ -+void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) -+{ -+ struct omap_hwmod *oh; -+ struct omap_device *od; -+ struct omap_device_pm_latency *ohl; -+ char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN]; -+ struct omap_mmc_platform_data *mmc_data; -+ struct omap_mmc_dev_attr *mmc_dev_attr; -+ char *name; -+ int l; -+ int ohl_cnt = 0; -+ -+ mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); -+ if (!mmc_data) { -+ pr_err("Cannot allocate memory for mmc device!\n"); -+ goto done; -+ } -+ -+ if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) { -+ pr_err("%s fails!\n", __func__); -+ goto done; -+ } -+ omap_hsmmc_mux(mmc_data, (ctrl_nr - 1)); -+ -+ name = "omap_hsmmc"; -+ ohl = omap_hsmmc_latency; -+ ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency); -+ -+ l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN, -+ "mmc%d", ctrl_nr); -+ WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN, -+ "String buffer overflow in MMC%d device setup\n", ctrl_nr); -+ oh = omap_hwmod_lookup(oh_name); -+ if (!oh) { -+ pr_err("Could not look up %s\n", oh_name); -+ kfree(mmc_data->slots[0].name); -+ goto done; -+ } -+ -+ if (oh->dev_attr != NULL) { -+ mmc_dev_attr = oh->dev_attr; -+ mmc_data->controller_flags = mmc_dev_attr->flags; -+ } -+ -+ od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data, -+ sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false); -+ if (IS_ERR(od)) { -+ WARN(1, "Cant build omap_device for %s:%s.\n", name, oh->name); -+ kfree(mmc_data->slots[0].name); -+ goto done; -+ } -+ /* -+ * return device handle to board setup code -+ * required to populate for regulator framework structure -+ */ -+ hsmmcinfo->dev = &od->pdev.dev; -+ -+done: -+ kfree(mmc_data); -+} - - void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers) - { -- struct omap2_hsmmc_info *c; -- int nr_hsmmc = ARRAY_SIZE(hsmmc_data); -- int i; - u32 reg; - - if (!cpu_is_omap44xx()) { -@@ -236,142 +506,9 @@ - omap4_ctrl_pad_writel(reg, control_mmc1); - } - -- for (c = controllers; c->mmc; c++) { -- struct hsmmc_controller *hc = hsmmc + c->mmc - 1; -- struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; -- -- if (!c->mmc || c->mmc > nr_hsmmc) { -- pr_debug("MMC%d: no such controller\n", c->mmc); -- continue; -- } -- if (mmc) { -- pr_debug("MMC%d: already configured\n", c->mmc); -- continue; -- } -- -- mmc = kzalloc(sizeof(struct omap_mmc_platform_data), -- GFP_KERNEL); -- if (!mmc) { -- pr_err("Cannot allocate memory for mmc device!\n"); -- goto done; -- } -- -- if (c->name) -- strncpy(hc->name, c->name, HSMMC_NAME_LEN); -- else -- snprintf(hc->name, ARRAY_SIZE(hc->name), -- "mmc%islot%i", c->mmc, 1); -- mmc->slots[0].name = hc->name; -- mmc->nr_slots = 1; -- mmc->slots[0].caps = c->caps; -- mmc->slots[0].internal_clock = !c->ext_clock; -- mmc->dma_mask = 0xffffffff; -- if (cpu_is_omap44xx()) -- mmc->reg_offset = OMAP4_MMC_REG_OFFSET; -- else -- mmc->reg_offset = 0; -- -- mmc->get_context_loss_count = hsmmc_get_context_loss; -- -- mmc->slots[0].switch_pin = c->gpio_cd; -- mmc->slots[0].gpio_wp = c->gpio_wp; -- -- mmc->slots[0].remux = c->remux; -- mmc->slots[0].init_card = c->init_card; -- -- if (c->cover_only) -- mmc->slots[0].cover = 1; -- -- if (c->nonremovable) -- mmc->slots[0].nonremovable = 1; -- -- if (c->power_saving) -- mmc->slots[0].power_saving = 1; -- -- if (c->no_off) -- mmc->slots[0].no_off = 1; -- -- if (c->vcc_aux_disable_is_sleep) -- mmc->slots[0].vcc_aux_disable_is_sleep = 1; -- -- /* NOTE: MMC slots should have a Vcc regulator set up. -- * This may be from a TWL4030-family chip, another -- * controllable regulator, or a fixed supply. -- * -- * temporary HACK: ocr_mask instead of fixed supply -- */ -- mmc->slots[0].ocr_mask = c->ocr_mask; -- -- if (cpu_is_omap3517() || cpu_is_omap3505()) -- mmc->slots[0].set_power = nop_mmc_set_power; -- else -- mmc->slots[0].features |= HSMMC_HAS_PBIAS; -- -- if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) -- mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; -- -- switch (c->mmc) { -- case 1: -- if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { -- /* on-chip level shifting via PBIAS0/PBIAS1 */ -- if (cpu_is_omap44xx()) { -- mmc->slots[0].before_set_reg = -- omap4_hsmmc1_before_set_reg; -- mmc->slots[0].after_set_reg = -- omap4_hsmmc1_after_set_reg; -- } else { -- mmc->slots[0].before_set_reg = -- omap_hsmmc1_before_set_reg; -- mmc->slots[0].after_set_reg = -- omap_hsmmc1_after_set_reg; -- } -- } -- -- /* Omap3630 HSMMC1 supports only 4-bit */ -- if (cpu_is_omap3630() && -- (c->caps & MMC_CAP_8_BIT_DATA)) { -- c->caps &= ~MMC_CAP_8_BIT_DATA; -- c->caps |= MMC_CAP_4_BIT_DATA; -- mmc->slots[0].caps = c->caps; -- } -- break; -- case 2: -- if (c->ext_clock) -- c->transceiver = 1; -- if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { -- c->caps &= ~MMC_CAP_8_BIT_DATA; -- c->caps |= MMC_CAP_4_BIT_DATA; -- } -- /* FALLTHROUGH */ -- case 3: -- if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { -- /* off-chip level shifting, or none */ -- mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; -- mmc->slots[0].after_set_reg = NULL; -- } -- break; -- default: -- pr_err("MMC%d configuration not supported!\n", c->mmc); -- kfree(mmc); -- continue; -- } -- hsmmc_data[c->mmc - 1] = mmc; -- } -- -- omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); -- -- /* pass the device nodes back to board setup code */ -- for (c = controllers; c->mmc; c++) { -- struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; -+ for (; controllers->mmc; controllers++) -+ omap_init_hsmmc(controllers, controllers->mmc); - -- if (!c->mmc || c->mmc > nr_hsmmc) -- continue; -- c->dev = mmc->dev; -- } -- --done: -- for (i = 0; i < nr_hsmmc; i++) -- kfree(hsmmc_data[i]); - } - - #endif -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/hwspinlock.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/hwspinlock.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/hwspinlock.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/hwspinlock.c 2011-03-09 13:19:09.817507478 +0100 -@@ -0,0 +1,63 @@ -+/* -+ * OMAP hardware spinlock device initialization -+ * -+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com -+ * -+ * Contact: Simon Que -+ * Hari Kanigeri -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+ -+struct omap_device_pm_latency omap_spinlock_latency[] = { -+ { -+ .deactivate_func = omap_device_idle_hwmods, -+ .activate_func = omap_device_enable_hwmods, -+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, -+ } -+}; -+ -+int __init hwspinlocks_init(void) -+{ -+ int retval = 0; -+ struct omap_hwmod *oh; -+ struct omap_device *od; -+ const char *oh_name = "spinlock"; -+ const char *dev_name = "omap_hwspinlock"; -+ -+ /* -+ * Hwmod lookup will fail in case our platform doesn't support the -+ * hardware spinlock module, so it is safe to run this initcall -+ * on all omaps -+ */ -+ oh = omap_hwmod_lookup(oh_name); -+ if (oh == NULL) -+ return -EINVAL; -+ -+ od = omap_device_build(dev_name, 0, oh, NULL, 0, -+ omap_spinlock_latency, -+ ARRAY_SIZE(omap_spinlock_latency), false); -+ if (IS_ERR(od)) { -+ pr_err("Can't build omap_device for %s:%s\n", dev_name, -+ oh_name); -+ retval = PTR_ERR(od); -+ } -+ -+ return retval; -+} -+/* early board code might need to reserve specific hwspinlock instances */ -+postcore_initcall(hwspinlocks_init); -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/id.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/id.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/id.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/id.c 2011-03-09 13:19:09.817507478 +0100 -@@ -6,7 +6,7 @@ - * Copyright (C) 2005 Nokia Corporation - * Written by Tony Lindgren - * -- * Copyright (C) 2009 Texas Instruments -+ * Copyright (C) 2009-11 Texas Instruments - * Added OMAP4 support - Santosh Shilimkar - * - * This program is free software; you can redistribute it and/or modify -@@ -191,12 +191,19 @@ - if (!cpu_is_omap3505() && !cpu_is_omap3517()) - omap3_features |= OMAP3_HAS_IO_WAKEUP; - -+ omap3_features |= OMAP3_HAS_SDRC; -+ - /* - * TODO: Get additional info (where applicable) - * e.g. Size of L2 cache. - */ - } - -+static void __init ti816x_check_features(void) -+{ -+ omap3_features = OMAP3_HAS_NEON; -+} -+ - static void __init omap3_check_revision(void) - { - u32 cpuid, idcode; -@@ -287,6 +294,20 @@ - omap_chip.oc |= CHIP_IS_OMAP3630ES1_2; - } - break; -+ case 0xb81e: -+ omap_chip.oc = CHIP_IS_TI816X; -+ -+ switch (rev) { -+ case 0: -+ omap_revision = TI8168_REV_ES1_0; -+ break; -+ case 1: -+ omap_revision = TI8168_REV_ES1_1; -+ break; -+ default: -+ omap_revision = TI8168_REV_ES1_1; -+ } -+ break; - default: - /* Unknown default to latest silicon rev as default*/ - omap_revision = OMAP3630_REV_ES1_2; -@@ -307,7 +328,7 @@ - */ - idcode = read_tap_reg(OMAP_TAP_IDCODE); - hawkeye = (idcode >> 12) & 0xffff; -- rev = (idcode >> 28) & 0xff; -+ rev = (idcode >> 28) & 0xf; - - /* - * Few initial ES2.0 samples IDCODE is same as ES1.0 -@@ -326,22 +347,31 @@ - omap_chip.oc |= CHIP_IS_OMAP4430ES1; - break; - case 1: -+ default: - omap_revision = OMAP4430_REV_ES2_0; - omap_chip.oc |= CHIP_IS_OMAP4430ES2; -+ } -+ break; -+ case 0xb95c: -+ switch (rev) { -+ case 3: -+ omap_revision = OMAP4430_REV_ES2_1; -+ omap_chip.oc |= CHIP_IS_OMAP4430ES2_1; - break; -+ case 4: - default: -- omap_revision = OMAP4430_REV_ES2_0; -- omap_chip.oc |= CHIP_IS_OMAP4430ES2; -- } -- break; -+ omap_revision = OMAP4430_REV_ES2_2; -+ omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; -+ } -+ break; - default: -- /* Unknown default to latest silicon rev as default*/ -- omap_revision = OMAP4430_REV_ES2_0; -- omap_chip.oc |= CHIP_IS_OMAP4430ES2; -+ /* Unknown default to latest silicon rev as default */ -+ omap_revision = OMAP4430_REV_ES2_2; -+ omap_chip.oc |= CHIP_IS_OMAP4430ES2_2; - } - -- pr_info("OMAP%04x ES%d.0\n", -- omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1); -+ pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16, -+ ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf)); - } - - #define OMAP3_SHOW_FEATURE(feat) \ -@@ -372,6 +402,8 @@ - /* Already set in omap3_check_revision() */ - strcpy(cpu_name, "AM3505"); - } -+ } else if (cpu_is_ti816x()) { -+ strcpy(cpu_name, "TI816X"); - } else if (omap3_has_iva() && omap3_has_sgx()) { - /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */ - strcpy(cpu_name, "OMAP3430/3530"); -@@ -386,7 +418,7 @@ - strcpy(cpu_name, "OMAP3503"); - } - -- if (cpu_is_omap3630()) { -+ if (cpu_is_omap3630() || cpu_is_ti816x()) { - switch (rev) { - case OMAP_REVBITS_00: - strcpy(cpu_rev, "1.0"); -@@ -462,7 +494,13 @@ - omap24xx_check_revision(); - } else if (cpu_is_omap34xx()) { - omap3_check_revision(); -- omap3_check_features(); -+ -+ /* TI816X doesn't have feature register */ -+ if (!cpu_is_ti816x()) -+ omap3_check_features(); -+ else -+ ti816x_check_features(); -+ - omap3_cpuinfo(); - return; - } else if (cpu_is_omap44xx()) { -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/include/mach/debug-macro.S linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/include/mach/debug-macro.S ---- linux-2.6.38-rc7/arch/arm/mach-omap2/include/mach/debug-macro.S 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/include/mach/debug-macro.S 2011-03-09 13:19:09.819507439 +0100 -@@ -69,6 +69,12 @@ - beq 34f @ configure OMAP3UART4 - cmp \rp, #OMAP4UART4 @ only on 44xx - beq 44f @ configure OMAP4UART4 -+ cmp \rp, #TI816XUART1 @ ti816x UART offsets different -+ beq 81f @ configure UART1 -+ cmp \rp, #TI816XUART2 @ ti816x UART offsets different -+ beq 82f @ configure UART2 -+ cmp \rp, #TI816XUART3 @ ti816x UART offsets different -+ beq 83f @ configure UART3 - cmp \rp, #ZOOM_UART @ only on zoom2/3 - beq 95f @ configure ZOOM_UART - -@@ -91,6 +97,12 @@ - b 98f - 44: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE) - b 98f -+81: mov \rp, #UART_OFFSET(TI816X_UART1_BASE) -+ b 98f -+82: mov \rp, #UART_OFFSET(TI816X_UART2_BASE) -+ b 98f -+83: mov \rp, #UART_OFFSET(TI816X_UART3_BASE) -+ b 98f - 95: ldr \rp, =ZOOM_UART_BASE - mrc p15, 0, \rv, c1, c0 - tst \rv, #1 @ MMU enabled? -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/include/mach/entry-macro.S linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/include/mach/entry-macro.S ---- linux-2.6.38-rc7/arch/arm/mach-omap2/include/mach/entry-macro.S 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/include/mach/entry-macro.S 2011-03-09 13:19:09.819507439 +0100 -@@ -61,6 +61,14 @@ - bne 9998f - ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ - cmp \irqnr, #0x0 -+ bne 9998f -+ -+ /* -+ * ti816x has additional IRQ pending register. Checking this -+ * register on omap2 & omap3 has no effect (read as 0). -+ */ -+ ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */ -+ cmp \irqnr, #0x0 - 9998: - ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] - and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ -@@ -133,6 +141,11 @@ - bne 9999f - ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ - cmp \irqnr, #0x0 -+#ifdef CONFIG_SOC_OMAPTI816X -+ bne 9999f -+ ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */ -+ cmp \irqnr, #0x0 -+#endif - 9999: - ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] - and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/io.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/io.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/io.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/io.c 2011-03-09 13:19:09.820507420 +0100 -@@ -30,7 +30,6 @@ - - #include - #include --#include - #include - - #include "clock2xxx.h" -@@ -66,7 +65,7 @@ - }, - }; - --#ifdef CONFIG_ARCH_OMAP2420 -+#ifdef CONFIG_SOC_OMAP2420 - static struct map_desc omap242x_io_desc[] __initdata = { - { - .virtual = DSP_MEM_2420_VIRT, -@@ -90,7 +89,7 @@ - - #endif - --#ifdef CONFIG_ARCH_OMAP2430 -+#ifdef CONFIG_SOC_OMAP2430 - static struct map_desc omap243x_io_desc[] __initdata = { - { - .virtual = L4_WK_243X_VIRT, -@@ -175,6 +174,18 @@ - #endif - }; - #endif -+ -+#ifdef CONFIG_SOC_OMAPTI816X -+static struct map_desc omapti816x_io_desc[] __initdata = { -+ { -+ .virtual = L4_34XX_VIRT, -+ .pfn = __phys_to_pfn(L4_34XX_PHYS), -+ .length = L4_34XX_SIZE, -+ .type = MT_DEVICE -+ }, -+}; -+#endif -+ - #ifdef CONFIG_ARCH_OMAP4 - static struct map_desc omap44xx_io_desc[] __initdata = { - { -@@ -241,7 +252,7 @@ - omap_sram_init(); - } - --#ifdef CONFIG_ARCH_OMAP2420 -+#ifdef CONFIG_SOC_OMAP2420 - void __init omap242x_map_common_io(void) - { - iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); -@@ -250,7 +261,7 @@ - } - #endif - --#ifdef CONFIG_ARCH_OMAP2430 -+#ifdef CONFIG_SOC_OMAP2430 - void __init omap243x_map_common_io(void) - { - iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); -@@ -267,6 +278,14 @@ - } - #endif - -+#ifdef CONFIG_SOC_OMAPTI816X -+void __init omapti816x_map_common_io(void) -+{ -+ iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc)); -+ _omap2_map_common_io(); -+} -+#endif -+ - #ifdef CONFIG_ARCH_OMAP4 - void __init omap44xx_map_common_io(void) - { -@@ -398,15 +417,10 @@ - void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0, - struct omap_sdrc_params *sdrc_cs1) - { -- omap_serial_early_init(); -- -- omap_hwmod_late_init(); -- -- if (cpu_is_omap24xx() || cpu_is_omap34xx()) { -+ if (cpu_is_omap24xx() || omap3_has_sdrc()) { - omap2_sdrc_init(sdrc_cs0, sdrc_cs1); - _omap2_init_reprogram_sdrc(); - } -- gpmc_init(); - - omap_irq_base_init(); - } -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/iommu2.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/iommu2.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/iommu2.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/iommu2.c 2011-03-09 13:19:09.821507400 +0100 -@@ -145,35 +145,32 @@ - - static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) - { -- int i; - u32 stat, da; -- const char *err_msg[] = { -- "tlb miss", -- "translation fault", -- "emulation miss", -- "table walk fault", -- "multi hit fault", -- }; -+ u32 errs = 0; - - stat = iommu_read_reg(obj, MMU_IRQSTATUS); - stat &= MMU_IRQ_MASK; -- if (!stat) -+ if (!stat) { -+ *ra = 0; - return 0; -+ } - - da = iommu_read_reg(obj, MMU_FAULT_AD); - *ra = da; - -- dev_err(obj->dev, "%s:\tda:%08x ", __func__, da); -- -- for (i = 0; i < ARRAY_SIZE(err_msg); i++) { -- if (stat & (1 << i)) -- printk("%s ", err_msg[i]); -- } -- printk("\n"); -- -+ if (stat & MMU_IRQ_TLBMISS) -+ errs |= OMAP_IOMMU_ERR_TLB_MISS; -+ if (stat & MMU_IRQ_TRANSLATIONFAULT) -+ errs |= OMAP_IOMMU_ERR_TRANS_FAULT; -+ if (stat & MMU_IRQ_EMUMISS) -+ errs |= OMAP_IOMMU_ERR_EMU_MISS; -+ if (stat & MMU_IRQ_TABLEWALKFAULT) -+ errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT; -+ if (stat & MMU_IRQ_MULTIHITFAULT) -+ errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT; - iommu_write_reg(obj, stat, MMU_IRQSTATUS); - -- return stat; -+ return errs; - } - - static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr) -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/irq.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/irq.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/irq.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/irq.c 2011-03-09 13:19:09.821507400 +0100 -@@ -61,8 +61,6 @@ - u32 mir[INTCPS_NR_MIR_REGS]; - }; - --static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; -- - /* INTC bank register get/set */ - - static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg) -@@ -110,7 +108,7 @@ - unsigned int irq = d->irq; - int offset = irq & (~(IRQ_BITS_PER_REG - 1)); - -- if (cpu_is_omap34xx()) { -+ if (cpu_is_omap34xx() && !cpu_is_ti816x()) { - int spurious = 0; - - /* -@@ -205,6 +203,9 @@ - - BUG_ON(!base); - -+ if (cpu_is_ti816x()) -+ bank->nr_irqs = 128; -+ - /* Static mapping, never released */ - bank->base_reg = ioremap(base, SZ_4K); - if (!bank->base_reg) { -@@ -229,6 +230,8 @@ - } - - #ifdef CONFIG_ARCH_OMAP3 -+static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; -+ - void omap_intc_save_context(void) - { - int ind = 0, i = 0; -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/Kconfig linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/Kconfig ---- linux-2.6.38-rc7/arch/arm/mach-omap2/Kconfig 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/Kconfig 2011-03-09 13:19:09.792507988 +0100 -@@ -53,25 +53,30 @@ - comment "OMAP Core Type" - depends on ARCH_OMAP2 - --config ARCH_OMAP2420 -+config SOC_OMAP2420 - bool "OMAP2420 support" - depends on ARCH_OMAP2 - default y - select OMAP_DM_TIMER - select ARCH_OMAP_OTG - --config ARCH_OMAP2430 -+config SOC_OMAP2430 - bool "OMAP2430 support" - depends on ARCH_OMAP2 - default y - select ARCH_OMAP_OTG - --config ARCH_OMAP3430 -+config SOC_OMAP3430 - bool "OMAP3430 support" - depends on ARCH_OMAP3 - default y - select ARCH_OMAP_OTG - -+config SOC_OMAPTI816X -+ bool "TI816X support" -+ depends on ARCH_OMAP3 -+ default y -+ - config OMAP_PACKAGE_ZAF - bool - -@@ -106,25 +111,25 @@ - - config MACH_OMAP2_TUSB6010 - bool -- depends on ARCH_OMAP2 && ARCH_OMAP2420 -+ depends on ARCH_OMAP2 && SOC_OMAP2420 - default y if MACH_NOKIA_N8X0 - - config MACH_OMAP_H4 - bool "OMAP 2420 H4 board" -- depends on ARCH_OMAP2420 -+ depends on SOC_OMAP2420 - default y - select OMAP_PACKAGE_ZAF - select OMAP_DEBUG_DEVICES - - config MACH_OMAP_APOLLON - bool "OMAP 2420 Apollon board" -- depends on ARCH_OMAP2420 -+ depends on SOC_OMAP2420 - default y - select OMAP_PACKAGE_ZAC - - config MACH_OMAP_2430SDP - bool "OMAP 2430 SDP board" -- depends on ARCH_OMAP2430 -+ depends on SOC_OMAP2430 - default y - select OMAP_PACKAGE_ZAC - -@@ -219,7 +224,7 @@ - - config MACH_NOKIA_N8X0 - bool "Nokia N800/N810" -- depends on ARCH_OMAP2420 -+ depends on SOC_OMAP2420 - default y - select OMAP_PACKAGE_ZAC - select MACH_NOKIA_N800 -@@ -294,12 +299,18 @@ - default y - select OMAP_PACKAGE_CBP - -+config MACH_TI8168EVM -+ bool "TI8168 Evaluation Module" -+ depends on SOC_OMAPTI816X -+ default y -+ - config MACH_OMAP_4430SDP - bool "OMAP 4430 SDP board" - default y - depends on ARCH_OMAP4 - select OMAP_PACKAGE_CBL - select OMAP_PACKAGE_CBS -+ select REGULATOR_FIXED_VOLTAGE - - config MACH_OMAP4_PANDA - bool "OMAP4 Panda Board" -@@ -307,6 +318,7 @@ - depends on ARCH_OMAP4 - select OMAP_PACKAGE_CBL - select OMAP_PACKAGE_CBS -+ select REGULATOR_FIXED_VOLTAGE - - config OMAP3_EMU - bool "OMAP3 debugging peripherals" -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/mailbox.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/mailbox.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/mailbox.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/mailbox.c 2011-03-09 13:19:09.821507400 +0100 -@@ -14,12 +14,11 @@ - #include - #include - #include -+#include - #include - #include - - #define MAILBOX_REVISION 0x000 --#define MAILBOX_SYSCONFIG 0x010 --#define MAILBOX_SYSSTATUS 0x014 - #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) - #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) - #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m)) -@@ -33,17 +32,6 @@ - #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m))) - #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1)) - --/* SYSCONFIG: register bit definition */ --#define AUTOIDLE (1 << 0) --#define SOFTRESET (1 << 1) --#define SMARTIDLE (2 << 3) --#define OMAP4_SOFTRESET (1 << 0) --#define OMAP4_NOIDLE (1 << 2) --#define OMAP4_SMARTIDLE (2 << 2) -- --/* SYSSTATUS: register bit definition */ --#define RESETDONE (1 << 0) -- - #define MBOX_REG_SIZE 0x120 - - #define OMAP4_MBOX_REG_SIZE 0x130 -@@ -70,8 +58,6 @@ - unsigned long irqdisable; - }; - --static struct clk *mbox_ick_handle; -- - static void omap2_mbox_enable_irq(struct omap_mbox *mbox, - omap_mbox_type_t irq); - -@@ -89,53 +75,13 @@ - static int omap2_mbox_startup(struct omap_mbox *mbox) - { - u32 l; -- unsigned long timeout; - -- mbox_ick_handle = clk_get(NULL, "mailboxes_ick"); -- if (IS_ERR(mbox_ick_handle)) { -- printk(KERN_ERR "Could not get mailboxes_ick: %ld\n", -- PTR_ERR(mbox_ick_handle)); -- return PTR_ERR(mbox_ick_handle); -- } -- clk_enable(mbox_ick_handle); -- -- if (cpu_is_omap44xx()) { -- mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG); -- timeout = jiffies + msecs_to_jiffies(20); -- do { -- l = mbox_read_reg(MAILBOX_SYSCONFIG); -- if (!(l & OMAP4_SOFTRESET)) -- break; -- } while (!time_after(jiffies, timeout)); -- -- if (l & OMAP4_SOFTRESET) { -- pr_err("Can't take mailbox out of reset\n"); -- return -ENODEV; -- } -- } else { -- mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG); -- timeout = jiffies + msecs_to_jiffies(20); -- do { -- l = mbox_read_reg(MAILBOX_SYSSTATUS); -- if (l & RESETDONE) -- break; -- } while (!time_after(jiffies, timeout)); -- -- if (!(l & RESETDONE)) { -- pr_err("Can't take mailbox out of reset\n"); -- return -ENODEV; -- } -- } -+ pm_runtime_enable(mbox->dev->parent); -+ pm_runtime_get_sync(mbox->dev->parent); - - l = mbox_read_reg(MAILBOX_REVISION); - pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); - -- if (cpu_is_omap44xx()) -- l = OMAP4_SMARTIDLE; -- else -- l = SMARTIDLE | AUTOIDLE; -- mbox_write_reg(l, MAILBOX_SYSCONFIG); -- - omap2_mbox_enable_irq(mbox, IRQ_RX); - - return 0; -@@ -143,9 +89,8 @@ - - static void omap2_mbox_shutdown(struct omap_mbox *mbox) - { -- clk_disable(mbox_ick_handle); -- clk_put(mbox_ick_handle); -- mbox_ick_handle = NULL; -+ pm_runtime_put_sync(mbox->dev->parent); -+ pm_runtime_disable(mbox->dev->parent); - } - - /* Mailbox FIFO handle functions */ -@@ -310,7 +255,7 @@ - struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL }; - #endif - --#if defined(CONFIG_ARCH_OMAP2420) -+#if defined(CONFIG_SOC_OMAP2420) - /* IVA */ - static struct omap_mbox2_priv omap2_mbox_iva_priv = { - .tx_fifo = { -@@ -398,14 +343,14 @@ - else if (cpu_is_omap34xx()) { - list = omap3_mboxes; - -- list[0]->irq = platform_get_irq_byname(pdev, "dsp"); -+ list[0]->irq = platform_get_irq(pdev, 0); - } - #endif - #if defined(CONFIG_ARCH_OMAP2) - else if (cpu_is_omap2430()) { - list = omap2_mboxes; - -- list[0]->irq = platform_get_irq_byname(pdev, "dsp"); -+ list[0]->irq = platform_get_irq(pdev, 0); - } else if (cpu_is_omap2420()) { - list = omap2_mboxes; - -@@ -417,8 +362,7 @@ - else if (cpu_is_omap44xx()) { - list = omap4_mboxes; - -- list[0]->irq = list[1]->irq = -- platform_get_irq_byname(pdev, "mbox"); -+ list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0); - } - #endif - else { -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/Makefile linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/Makefile ---- linux-2.6.38-rc7/arch/arm/mach-omap2/Makefile 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/Makefile 2011-03-09 13:19:09.793507967 +0100 -@@ -31,8 +31,8 @@ - AFLAGS_omap44xx-smc.o :=-Wa,-march=armv7-a$(plus_sec) - - # Functions loaded to SRAM --obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o --obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o -+obj-$(CONFIG_SOC_OMAP2420) += sram242x.o -+obj-$(CONFIG_SOC_OMAP2430) += sram243x.o - obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o - - AFLAGS_sram242x.o :=-Wa,-march=armv6 -@@ -40,8 +40,8 @@ - AFLAGS_sram34xx.o :=-Wa,-march=armv7-a - - # Pin multiplexing --obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o --obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o -+obj-$(CONFIG_SOC_OMAP2420) += mux2420.o -+obj-$(CONFIG_SOC_OMAP2430) += mux2430.o - obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o - obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o - -@@ -113,8 +113,8 @@ - clkt2xxx_dpllcore.o \ - clkt2xxx_virt_prcm_set.o \ - clkt2xxx_apll.o clkt2xxx_osc.o --obj-$(CONFIG_ARCH_OMAP2420) += clock2420_data.o --obj-$(CONFIG_ARCH_OMAP2430) += clock2430.o clock2430_data.o -+obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o -+obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o - obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \ - clock34xx.o clkt34xx_dpll3m2.o \ - clock3517.o clock36xx.o \ -@@ -123,12 +123,12 @@ - dpll3xxx.o - - # OMAP2 clock rate set data (old "OPP" data) --obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o --obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o -+obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o -+obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o - - # hwmod data --obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o --obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o -+obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o -+obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o - obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o - obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o - -@@ -218,12 +218,14 @@ - hsmmc.o \ - omap_phy_internal.o - --obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o -+obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o \ -+ omap_phy_internal.o \ - - obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o - - obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \ - hsmmc.o -+obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o - # Platform specific device init code - usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o - obj-y += $(usbfs-m) $(usbfs-y) -@@ -242,3 +244,7 @@ - - smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o - obj-y += $(smsc911x-m) $(smsc911x-y) -+obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o -+ -+disp-$(CONFIG_OMAP2_DSS) := display.o -+obj-y += $(disp-m) $(disp-y) -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/mcbsp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/mcbsp.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/mcbsp.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/mcbsp.c 2011-03-09 13:19:09.821507400 +0100 -@@ -22,10 +22,11 @@ - #include - #include - #include -+#include -+#include - - #include "control.h" - -- - /* McBSP internal signal muxing functions */ - - void omap2_mcbsp1_mux_clkr_src(u8 mux) -@@ -83,7 +84,7 @@ - return -EINVAL; - } - -- clk_disable(mcbsp->fclk); -+ pm_runtime_put_sync(mcbsp->dev); - - r = clk_set_parent(mcbsp->fclk, fck_src); - if (IS_ERR_VALUE(r)) { -@@ -93,7 +94,7 @@ - return -EINVAL; - } - -- clk_enable(mcbsp->fclk); -+ pm_runtime_get_sync(mcbsp->dev); - - clk_put(fck_src); - -@@ -101,196 +102,70 @@ - } - EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); - -- --/* Platform data */ -- --#ifdef CONFIG_ARCH_OMAP2420 --static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { -+struct omap_device_pm_latency omap2_mcbsp_latency[] = { - { -- .phys_base = OMAP24XX_MCBSP1_BASE, -- .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, -- .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, -- .rx_irq = INT_24XX_MCBSP1_IRQ_RX, -- .tx_irq = INT_24XX_MCBSP1_IRQ_TX, -- }, -- { -- .phys_base = OMAP24XX_MCBSP2_BASE, -- .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, -- .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, -- .rx_irq = INT_24XX_MCBSP2_IRQ_RX, -- .tx_irq = INT_24XX_MCBSP2_IRQ_TX, -+ .deactivate_func = omap_device_idle_hwmods, -+ .activate_func = omap_device_enable_hwmods, -+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, - }, - }; --#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) --#define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) --#else --#define omap2420_mcbsp_pdata NULL --#define OMAP2420_MCBSP_PDATA_SZ 0 --#define OMAP2420_MCBSP_REG_NUM 0 --#endif - --#ifdef CONFIG_ARCH_OMAP2430 --static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { -- { -- .phys_base = OMAP24XX_MCBSP1_BASE, -- .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, -- .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, -- .rx_irq = INT_24XX_MCBSP1_IRQ_RX, -- .tx_irq = INT_24XX_MCBSP1_IRQ_TX, -- }, -- { -- .phys_base = OMAP24XX_MCBSP2_BASE, -- .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, -- .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, -- .rx_irq = INT_24XX_MCBSP2_IRQ_RX, -- .tx_irq = INT_24XX_MCBSP2_IRQ_TX, -- }, -- { -- .phys_base = OMAP2430_MCBSP3_BASE, -- .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, -- .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, -- .rx_irq = INT_24XX_MCBSP3_IRQ_RX, -- .tx_irq = INT_24XX_MCBSP3_IRQ_TX, -- }, -- { -- .phys_base = OMAP2430_MCBSP4_BASE, -- .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX, -- .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, -- .rx_irq = INT_24XX_MCBSP4_IRQ_RX, -- .tx_irq = INT_24XX_MCBSP4_IRQ_TX, -- }, -- { -- .phys_base = OMAP2430_MCBSP5_BASE, -- .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX, -- .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, -- .rx_irq = INT_24XX_MCBSP5_IRQ_RX, -- .tx_irq = INT_24XX_MCBSP5_IRQ_TX, -- }, --}; --#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) --#define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) --#else --#define omap2430_mcbsp_pdata NULL --#define OMAP2430_MCBSP_PDATA_SZ 0 --#define OMAP2430_MCBSP_REG_NUM 0 --#endif -+static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused) -+{ -+ int id, count = 1; -+ char *name = "omap-mcbsp"; -+ struct omap_hwmod *oh_device[2]; -+ struct omap_mcbsp_platform_data *pdata = NULL; -+ struct omap_device *od; -+ -+ sscanf(oh->name, "mcbsp%d", &id); -+ -+ pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL); -+ if (!pdata) { -+ pr_err("%s: No memory for mcbsp\n", __func__); -+ return -ENOMEM; -+ } - --#ifdef CONFIG_ARCH_OMAP3 --static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { -- { -- .phys_base = OMAP34XX_MCBSP1_BASE, -- .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, -- .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, -- .rx_irq = INT_24XX_MCBSP1_IRQ_RX, -- .tx_irq = INT_24XX_MCBSP1_IRQ_TX, -- .buffer_size = 0x80, /* The FIFO has 128 locations */ -- }, -- { -- .phys_base = OMAP34XX_MCBSP2_BASE, -- .phys_base_st = OMAP34XX_MCBSP2_ST_BASE, -- .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX, -- .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX, -- .rx_irq = INT_24XX_MCBSP2_IRQ_RX, -- .tx_irq = INT_24XX_MCBSP2_IRQ_TX, -- .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */ -- }, -- { -- .phys_base = OMAP34XX_MCBSP3_BASE, -- .phys_base_st = OMAP34XX_MCBSP3_ST_BASE, -- .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX, -- .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX, -- .rx_irq = INT_24XX_MCBSP3_IRQ_RX, -- .tx_irq = INT_24XX_MCBSP3_IRQ_TX, -- .buffer_size = 0x80, /* The FIFO has 128 locations */ -- }, -- { -- .phys_base = OMAP34XX_MCBSP4_BASE, -- .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX, -- .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX, -- .rx_irq = INT_24XX_MCBSP4_IRQ_RX, -- .tx_irq = INT_24XX_MCBSP4_IRQ_TX, -- .buffer_size = 0x80, /* The FIFO has 128 locations */ -- }, -- { -- .phys_base = OMAP34XX_MCBSP5_BASE, -- .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX, -- .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX, -- .rx_irq = INT_24XX_MCBSP5_IRQ_RX, -- .tx_irq = INT_24XX_MCBSP5_IRQ_TX, -- .buffer_size = 0x80, /* The FIFO has 128 locations */ -- }, --}; --#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) --#define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) --#else --#define omap34xx_mcbsp_pdata NULL --#define OMAP34XX_MCBSP_PDATA_SZ 0 --#define OMAP34XX_MCBSP_REG_NUM 0 --#endif -+ pdata->mcbsp_config_type = oh->class->rev; - --static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { -- { -- .phys_base = OMAP44XX_MCBSP1_BASE, -- .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, -- .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, -- .tx_irq = OMAP44XX_IRQ_MCBSP1, -- }, -- { -- .phys_base = OMAP44XX_MCBSP2_BASE, -- .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, -- .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, -- .tx_irq = OMAP44XX_IRQ_MCBSP2, -- }, -- { -- .phys_base = OMAP44XX_MCBSP3_BASE, -- .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, -- .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, -- .tx_irq = OMAP44XX_IRQ_MCBSP3, -- }, -- { -- .phys_base = OMAP44XX_MCBSP4_BASE, -- .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, -- .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, -- .tx_irq = OMAP44XX_IRQ_MCBSP4, -- }, --}; --#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) --#define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) -+ if (oh->class->rev == MCBSP_CONFIG_TYPE3) { -+ if (id == 2) -+ /* The FIFO has 1024 + 256 locations */ -+ pdata->buffer_size = 0x500; -+ else -+ /* The FIFO has 128 locations */ -+ pdata->buffer_size = 0x80; -+ } -+ -+ oh_device[0] = oh; -+ -+ if (oh->dev_attr) { -+ oh_device[1] = omap_hwmod_lookup(( -+ (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone); -+ count++; -+ } -+ od = omap_device_build_ss(name, id, oh_device, count, pdata, -+ sizeof(*pdata), omap2_mcbsp_latency, -+ ARRAY_SIZE(omap2_mcbsp_latency), false); -+ kfree(pdata); -+ if (IS_ERR(od)) { -+ pr_err("%s: Cant build omap_device for %s:%s.\n", __func__, -+ name, oh->name); -+ return PTR_ERR(od); -+ } -+ omap_mcbsp_count++; -+ return 0; -+} - - static int __init omap2_mcbsp_init(void) - { -- if (cpu_is_omap2420()) { -- omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ; -- omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16); -- } else if (cpu_is_omap2430()) { -- omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ; -- omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32); -- } else if (cpu_is_omap34xx()) { -- omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ; -- omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32); -- } else if (cpu_is_omap44xx()) { -- omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ; -- omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32); -- } -+ omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL); - - mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), - GFP_KERNEL); - if (!mcbsp_ptr) - return -ENOMEM; - -- if (cpu_is_omap2420()) -- omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata, -- OMAP2420_MCBSP_PDATA_SZ); -- if (cpu_is_omap2430()) -- omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata, -- OMAP2430_MCBSP_PDATA_SZ); -- if (cpu_is_omap34xx()) -- omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata, -- OMAP34XX_MCBSP_PDATA_SZ); -- if (cpu_is_omap44xx()) -- omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata, -- OMAP44XX_MCBSP_PDATA_SZ); -- - return omap_mcbsp_init(); - } - arch_initcall(omap2_mcbsp_init); -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod_2420_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod_2420_data.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod_2420_data.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod_2420_data.c 2011-03-09 13:19:09.827507277 +0100 -@@ -18,6 +18,10 @@ - #include - #include - #include -+#include -+#include -+#include -+#include - - #include "omap_hwmod_common_data.h" - -@@ -38,12 +42,18 @@ - static struct omap_hwmod omap2420_iva_hwmod; - static struct omap_hwmod omap2420_l3_main_hwmod; - static struct omap_hwmod omap2420_l4_core_hwmod; -+static struct omap_hwmod omap2420_dss_core_hwmod; -+static struct omap_hwmod omap2420_dss_dispc_hwmod; -+static struct omap_hwmod omap2420_dss_rfbi_hwmod; -+static struct omap_hwmod omap2420_dss_venc_hwmod; - static struct omap_hwmod omap2420_wd_timer2_hwmod; - static struct omap_hwmod omap2420_gpio1_hwmod; - static struct omap_hwmod omap2420_gpio2_hwmod; - static struct omap_hwmod omap2420_gpio3_hwmod; - static struct omap_hwmod omap2420_gpio4_hwmod; - static struct omap_hwmod omap2420_dma_system_hwmod; -+static struct omap_hwmod omap2420_mcspi1_hwmod; -+static struct omap_hwmod omap2420_mcspi2_hwmod; - - /* L3 -> L4_CORE interface */ - static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { -@@ -64,6 +74,19 @@ - &omap2420_mpu__l3_main, - }; - -+/* DSS -> l3 */ -+static struct omap_hwmod_ocp_if omap2420_dss__l3 = { -+ .master = &omap2420_dss_core_hwmod, -+ .slave = &omap2420_l3_main_hwmod, -+ .fw = { -+ .omap2 = { -+ .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, -+ .flags = OMAP_FIREWALL_L3, -+ } -+ }, -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ - /* Master interfaces on the L3 interconnect */ - static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = { - &omap2420_l3_main__l4_core, -@@ -87,6 +110,44 @@ - static struct omap_hwmod omap2420_uart3_hwmod; - static struct omap_hwmod omap2420_i2c1_hwmod; - static struct omap_hwmod omap2420_i2c2_hwmod; -+static struct omap_hwmod omap2420_mcbsp1_hwmod; -+static struct omap_hwmod omap2420_mcbsp2_hwmod; -+ -+/* l4 core -> mcspi1 interface */ -+static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = { -+ { -+ .pa_start = 0x48098000, -+ .pa_end = 0x480980ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_mcspi1_hwmod, -+ .clk = "mcspi1_ick", -+ .addr = omap2420_mcspi1_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* l4 core -> mcspi2 interface */ -+static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = { -+ { -+ .pa_start = 0x4809a000, -+ .pa_end = 0x4809a0ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_mcspi2_hwmod, -+ .clk = "mcspi2_ick", -+ .addr = omap2420_mcspi2_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; - - /* L4_CORE -> L4_WKUP interface */ - static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { -@@ -279,6 +340,625 @@ - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) - }; - -+/* Timer Common */ -+static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap2420_timer_hwmod_class = { -+ .name = "timer", -+ .sysc = &omap2420_timer_sysc, -+ .rev = OMAP_TIMER_IP_VERSION_1, -+}; -+ -+/* timer1 */ -+static struct omap_hwmod omap2420_timer1_hwmod; -+static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = { -+ { .irq = 37, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { -+ { -+ .pa_start = 0x48028000, -+ .pa_end = 0x48028000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_wkup -> timer1 */ -+static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { -+ .master = &omap2420_l4_wkup_hwmod, -+ .slave = &omap2420_timer1_hwmod, -+ .clk = "gpt1_ick", -+ .addr = omap2420_timer1_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer1 slave port */ -+static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = { -+ &omap2420_l4_wkup__timer1, -+}; -+ -+/* timer1 hwmod */ -+static struct omap_hwmod omap2420_timer1_hwmod = { -+ .name = "timer1", -+ .mpu_irqs = omap2420_timer1_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs), -+ .main_clk = "gpt1_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT1_SHIFT, -+ .module_offs = WKUP_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_timer1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), -+ .class = &omap2420_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) -+}; -+ -+/* timer2 */ -+static struct omap_hwmod omap2420_timer2_hwmod; -+static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = { -+ { .irq = 38, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = { -+ { -+ .pa_start = 0x4802a000, -+ .pa_end = 0x4802a000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> timer2 */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_timer2_hwmod, -+ .clk = "gpt2_ick", -+ .addr = omap2420_timer2_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer2 slave port */ -+static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = { -+ &omap2420_l4_core__timer2, -+}; -+ -+/* timer2 hwmod */ -+static struct omap_hwmod omap2420_timer2_hwmod = { -+ .name = "timer2", -+ .mpu_irqs = omap2420_timer2_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs), -+ .main_clk = "gpt2_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT2_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_timer2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), -+ .class = &omap2420_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) -+}; -+ -+/* timer3 */ -+static struct omap_hwmod omap2420_timer3_hwmod; -+static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = { -+ { .irq = 39, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = { -+ { -+ .pa_start = 0x48078000, -+ .pa_end = 0x48078000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> timer3 */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_timer3_hwmod, -+ .clk = "gpt3_ick", -+ .addr = omap2420_timer3_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer3 slave port */ -+static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = { -+ &omap2420_l4_core__timer3, -+}; -+ -+/* timer3 hwmod */ -+static struct omap_hwmod omap2420_timer3_hwmod = { -+ .name = "timer3", -+ .mpu_irqs = omap2420_timer3_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs), -+ .main_clk = "gpt3_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT3_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_timer3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), -+ .class = &omap2420_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) -+}; -+ -+/* timer4 */ -+static struct omap_hwmod omap2420_timer4_hwmod; -+static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = { -+ { .irq = 40, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = { -+ { -+ .pa_start = 0x4807a000, -+ .pa_end = 0x4807a000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> timer4 */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_timer4_hwmod, -+ .clk = "gpt4_ick", -+ .addr = omap2420_timer4_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer4 slave port */ -+static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = { -+ &omap2420_l4_core__timer4, -+}; -+ -+/* timer4 hwmod */ -+static struct omap_hwmod omap2420_timer4_hwmod = { -+ .name = "timer4", -+ .mpu_irqs = omap2420_timer4_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs), -+ .main_clk = "gpt4_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT4_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_timer4_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), -+ .class = &omap2420_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) -+}; -+ -+/* timer5 */ -+static struct omap_hwmod omap2420_timer5_hwmod; -+static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = { -+ { .irq = 41, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = { -+ { -+ .pa_start = 0x4807c000, -+ .pa_end = 0x4807c000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> timer5 */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_timer5_hwmod, -+ .clk = "gpt5_ick", -+ .addr = omap2420_timer5_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer5 slave port */ -+static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = { -+ &omap2420_l4_core__timer5, -+}; -+ -+/* timer5 hwmod */ -+static struct omap_hwmod omap2420_timer5_hwmod = { -+ .name = "timer5", -+ .mpu_irqs = omap2420_timer5_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs), -+ .main_clk = "gpt5_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT5_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_timer5_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), -+ .class = &omap2420_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) -+}; -+ -+ -+/* timer6 */ -+static struct omap_hwmod omap2420_timer6_hwmod; -+static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = { -+ { .irq = 42, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = { -+ { -+ .pa_start = 0x4807e000, -+ .pa_end = 0x4807e000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> timer6 */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_timer6_hwmod, -+ .clk = "gpt6_ick", -+ .addr = omap2420_timer6_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer6 slave port */ -+static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = { -+ &omap2420_l4_core__timer6, -+}; -+ -+/* timer6 hwmod */ -+static struct omap_hwmod omap2420_timer6_hwmod = { -+ .name = "timer6", -+ .mpu_irqs = omap2420_timer6_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs), -+ .main_clk = "gpt6_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT6_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_timer6_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), -+ .class = &omap2420_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) -+}; -+ -+/* timer7 */ -+static struct omap_hwmod omap2420_timer7_hwmod; -+static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = { -+ { .irq = 43, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = { -+ { -+ .pa_start = 0x48080000, -+ .pa_end = 0x48080000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> timer7 */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_timer7_hwmod, -+ .clk = "gpt7_ick", -+ .addr = omap2420_timer7_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer7 slave port */ -+static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = { -+ &omap2420_l4_core__timer7, -+}; -+ -+/* timer7 hwmod */ -+static struct omap_hwmod omap2420_timer7_hwmod = { -+ .name = "timer7", -+ .mpu_irqs = omap2420_timer7_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs), -+ .main_clk = "gpt7_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT7_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_timer7_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), -+ .class = &omap2420_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) -+}; -+ -+/* timer8 */ -+static struct omap_hwmod omap2420_timer8_hwmod; -+static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = { -+ { .irq = 44, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = { -+ { -+ .pa_start = 0x48082000, -+ .pa_end = 0x48082000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> timer8 */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_timer8_hwmod, -+ .clk = "gpt8_ick", -+ .addr = omap2420_timer8_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer8 slave port */ -+static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = { -+ &omap2420_l4_core__timer8, -+}; -+ -+/* timer8 hwmod */ -+static struct omap_hwmod omap2420_timer8_hwmod = { -+ .name = "timer8", -+ .mpu_irqs = omap2420_timer8_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs), -+ .main_clk = "gpt8_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT8_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_timer8_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), -+ .class = &omap2420_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) -+}; -+ -+/* timer9 */ -+static struct omap_hwmod omap2420_timer9_hwmod; -+static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = { -+ { .irq = 45, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = { -+ { -+ .pa_start = 0x48084000, -+ .pa_end = 0x48084000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> timer9 */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_timer9_hwmod, -+ .clk = "gpt9_ick", -+ .addr = omap2420_timer9_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer9 slave port */ -+static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = { -+ &omap2420_l4_core__timer9, -+}; -+ -+/* timer9 hwmod */ -+static struct omap_hwmod omap2420_timer9_hwmod = { -+ .name = "timer9", -+ .mpu_irqs = omap2420_timer9_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs), -+ .main_clk = "gpt9_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT9_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_timer9_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), -+ .class = &omap2420_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) -+}; -+ -+/* timer10 */ -+static struct omap_hwmod omap2420_timer10_hwmod; -+static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = { -+ { .irq = 46, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = { -+ { -+ .pa_start = 0x48086000, -+ .pa_end = 0x48086000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> timer10 */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_timer10_hwmod, -+ .clk = "gpt10_ick", -+ .addr = omap2420_timer10_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer10 slave port */ -+static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = { -+ &omap2420_l4_core__timer10, -+}; -+ -+/* timer10 hwmod */ -+static struct omap_hwmod omap2420_timer10_hwmod = { -+ .name = "timer10", -+ .mpu_irqs = omap2420_timer10_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs), -+ .main_clk = "gpt10_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT10_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_timer10_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), -+ .class = &omap2420_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) -+}; -+ -+/* timer11 */ -+static struct omap_hwmod omap2420_timer11_hwmod; -+static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = { -+ { .irq = 47, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = { -+ { -+ .pa_start = 0x48088000, -+ .pa_end = 0x48088000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> timer11 */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_timer11_hwmod, -+ .clk = "gpt11_ick", -+ .addr = omap2420_timer11_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer11 slave port */ -+static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = { -+ &omap2420_l4_core__timer11, -+}; -+ -+/* timer11 hwmod */ -+static struct omap_hwmod omap2420_timer11_hwmod = { -+ .name = "timer11", -+ .mpu_irqs = omap2420_timer11_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs), -+ .main_clk = "gpt11_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT11_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_timer11_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), -+ .class = &omap2420_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) -+}; -+ -+/* timer12 */ -+static struct omap_hwmod omap2420_timer12_hwmod; -+static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = { -+ { .irq = 48, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = { -+ { -+ .pa_start = 0x4808a000, -+ .pa_end = 0x4808a000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> timer12 */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_timer12_hwmod, -+ .clk = "gpt12_ick", -+ .addr = omap2420_timer12_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer12 slave port */ -+static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = { -+ &omap2420_l4_core__timer12, -+}; -+ -+/* timer12 hwmod */ -+static struct omap_hwmod omap2420_timer12_hwmod = { -+ .name = "timer12", -+ .mpu_irqs = omap2420_timer12_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs), -+ .main_clk = "gpt12_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT12_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_timer12_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), -+ .class = &omap2420_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) -+}; -+ - /* l4_wkup -> wd_timer2 */ - static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { - { -@@ -354,120 +1034,404 @@ - .sysc_fields = &omap_hwmod_sysc_type1, - }; - --static struct omap_hwmod_class uart_class = { -- .name = "uart", -- .sysc = &uart_sysc, -+static struct omap_hwmod_class uart_class = { -+ .name = "uart", -+ .sysc = &uart_sysc, -+}; -+ -+/* UART1 */ -+ -+static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { -+ { .irq = INT_24XX_UART1_IRQ, }, -+}; -+ -+static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { -+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, -+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { -+ &omap2_l4_core__uart1, -+}; -+ -+static struct omap_hwmod omap2420_uart1_hwmod = { -+ .name = "uart1", -+ .mpu_irqs = uart1_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), -+ .sdma_reqs = uart1_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), -+ .main_clk = "uart1_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_UART1_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_uart1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), -+ .class = &uart_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -+}; -+ -+/* UART2 */ -+ -+static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { -+ { .irq = INT_24XX_UART2_IRQ, }, -+}; -+ -+static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { -+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, -+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { -+ &omap2_l4_core__uart2, -+}; -+ -+static struct omap_hwmod omap2420_uart2_hwmod = { -+ .name = "uart2", -+ .mpu_irqs = uart2_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), -+ .sdma_reqs = uart2_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), -+ .main_clk = "uart2_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_UART2_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_uart2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), -+ .class = &uart_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -+}; -+ -+/* UART3 */ -+ -+static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { -+ { .irq = INT_24XX_UART3_IRQ, }, -+}; -+ -+static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { -+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, -+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { -+ &omap2_l4_core__uart3, -+}; -+ -+static struct omap_hwmod omap2420_uart3_hwmod = { -+ .name = "uart3", -+ .mpu_irqs = uart3_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), -+ .sdma_reqs = uart3_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), -+ .main_clk = "uart3_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 2, -+ .module_bit = OMAP24XX_EN_UART3_SHIFT, -+ .idlest_reg_id = 2, -+ .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_uart3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), -+ .class = &uart_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -+}; -+ -+/* -+ * 'dss' class -+ * display sub-system -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap2420_dss_hwmod_class = { -+ .name = "dss", -+ .sysc = &omap2420_dss_sysc, -+}; -+ -+static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = { -+ { .name = "dispc", .dma_req = 5 }, -+}; -+ -+/* dss */ -+/* dss master ports */ -+static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { -+ &omap2420_dss__l3, -+}; -+ -+static struct omap_hwmod_addr_space omap2420_dss_addrs[] = { -+ { -+ .pa_start = 0x48050000, -+ .pa_end = 0x480503FF, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> dss */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_dss_core_hwmod, -+ .clk = "dss_ick", -+ .addr = omap2420_dss_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_dss_addrs), -+ .fw = { -+ .omap2 = { -+ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, -+ .flags = OMAP_FIREWALL_L4, -+ } -+ }, -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* dss slave ports */ -+static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = { -+ &omap2420_l4_core__dss, -+}; -+ -+static struct omap_hwmod_opt_clk dss_opt_clks[] = { -+ { .role = "tv_clk", .clk = "dss_54m_fck" }, -+ { .role = "sys_clk", .clk = "dss2_fck" }, -+}; -+ -+static struct omap_hwmod omap2420_dss_core_hwmod = { -+ .name = "dss_core", -+ .class = &omap2420_dss_hwmod_class, -+ .main_clk = "dss1_fck", /* instead of dss_fck */ -+ .sdma_reqs = omap2420_dss_sdma_chs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs), -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_DSS1_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, -+ }, -+ }, -+ .opt_clks = dss_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), -+ .slaves = omap2420_dss_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_dss_slaves), -+ .masters = omap2420_dss_masters, -+ .masters_cnt = ARRAY_SIZE(omap2420_dss_masters), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -+ .flags = HWMOD_NO_IDLEST, -+}; -+ -+/* -+ * 'dispc' class -+ * display controller -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | -+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap2420_dispc_hwmod_class = { -+ .name = "dispc", -+ .sysc = &omap2420_dispc_sysc, - }; - --/* UART1 */ -+static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = { -+ { .irq = 25 }, -+}; - --static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { -- { .irq = INT_24XX_UART1_IRQ, }, -+static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = { -+ { -+ .pa_start = 0x48050400, -+ .pa_end = 0x480507FF, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { -- { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, -- { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, -+/* l4_core -> dss_dispc */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_dss_dispc_hwmod, -+ .clk = "dss_ick", -+ .addr = omap2420_dss_dispc_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs), -+ .fw = { -+ .omap2 = { -+ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, -+ .flags = OMAP_FIREWALL_L4, -+ } -+ }, -+ .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { -- &omap2_l4_core__uart1, -+/* dss_dispc slave ports */ -+static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = { -+ &omap2420_l4_core__dss_dispc, - }; - --static struct omap_hwmod omap2420_uart1_hwmod = { -- .name = "uart1", -- .mpu_irqs = uart1_mpu_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), -- .sdma_reqs = uart1_sdma_reqs, -- .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), -- .main_clk = "uart1_fck", -+static struct omap_hwmod omap2420_dss_dispc_hwmod = { -+ .name = "dss_dispc", -+ .class = &omap2420_dispc_hwmod_class, -+ .mpu_irqs = omap2420_dispc_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dispc_irqs), -+ .main_clk = "dss1_fck", - .prcm = { - .omap2 = { -- .module_offs = CORE_MOD, - .prcm_reg_id = 1, -- .module_bit = OMAP24XX_EN_UART1_SHIFT, -+ .module_bit = OMAP24XX_EN_DSS1_SHIFT, -+ .module_offs = CORE_MOD, - .idlest_reg_id = 1, -- .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, -+ .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, - }, - }, -- .slaves = omap2420_uart1_slaves, -- .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), -- .class = &uart_class, -+ .slaves = omap2420_dss_dispc_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_dss_dispc_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -+ .flags = HWMOD_NO_IDLEST, - }; - --/* UART2 */ -+/* -+ * 'rfbi' class -+ * remote frame buffer interface -+ */ - --static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { -- { .irq = INT_24XX_UART2_IRQ, }, -+static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, - }; - --static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { -- { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, -- { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, -+static struct omap_hwmod_class omap2420_rfbi_hwmod_class = { -+ .name = "rfbi", -+ .sysc = &omap2420_rfbi_sysc, - }; - --static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { -- &omap2_l4_core__uart2, -+static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = { -+ { -+ .pa_start = 0x48050800, -+ .pa_end = 0x48050BFF, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod omap2420_uart2_hwmod = { -- .name = "uart2", -- .mpu_irqs = uart2_mpu_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), -- .sdma_reqs = uart2_sdma_reqs, -- .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), -- .main_clk = "uart2_fck", -+/* l4_core -> dss_rfbi */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_dss_rfbi_hwmod, -+ .clk = "dss_ick", -+ .addr = omap2420_dss_rfbi_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs), -+ .fw = { -+ .omap2 = { -+ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, -+ .flags = OMAP_FIREWALL_L4, -+ } -+ }, -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* dss_rfbi slave ports */ -+static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = { -+ &omap2420_l4_core__dss_rfbi, -+}; -+ -+static struct omap_hwmod omap2420_dss_rfbi_hwmod = { -+ .name = "dss_rfbi", -+ .class = &omap2420_rfbi_hwmod_class, -+ .main_clk = "dss1_fck", - .prcm = { - .omap2 = { -- .module_offs = CORE_MOD, - .prcm_reg_id = 1, -- .module_bit = OMAP24XX_EN_UART2_SHIFT, -- .idlest_reg_id = 1, -- .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, -+ .module_bit = OMAP24XX_EN_DSS1_SHIFT, -+ .module_offs = CORE_MOD, - }, - }, -- .slaves = omap2420_uart2_slaves, -- .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), -- .class = &uart_class, -+ .slaves = omap2420_dss_rfbi_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_dss_rfbi_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -+ .flags = HWMOD_NO_IDLEST, - }; - --/* UART3 */ -+/* -+ * 'venc' class -+ * video encoder -+ */ - --static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { -- { .irq = INT_24XX_UART3_IRQ, }, -+static struct omap_hwmod_class omap2420_venc_hwmod_class = { -+ .name = "venc", - }; - --static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { -- { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, -- { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, -+/* dss_venc */ -+static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = { -+ { -+ .pa_start = 0x48050C00, -+ .pa_end = 0x48050FFF, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { -- &omap2_l4_core__uart3, -+/* l4_core -> dss_venc */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_dss_venc_hwmod, -+ .clk = "dss_54m_fck", -+ .addr = omap2420_dss_venc_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs), -+ .fw = { -+ .omap2 = { -+ .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, -+ .flags = OMAP_FIREWALL_L4, -+ } -+ }, -+ .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --static struct omap_hwmod omap2420_uart3_hwmod = { -- .name = "uart3", -- .mpu_irqs = uart3_mpu_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), -- .sdma_reqs = uart3_sdma_reqs, -- .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), -- .main_clk = "uart3_fck", -+/* dss_venc slave ports */ -+static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = { -+ &omap2420_l4_core__dss_venc, -+}; -+ -+static struct omap_hwmod omap2420_dss_venc_hwmod = { -+ .name = "dss_venc", -+ .class = &omap2420_venc_hwmod_class, -+ .main_clk = "dss1_fck", - .prcm = { - .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_DSS1_SHIFT, - .module_offs = CORE_MOD, -- .prcm_reg_id = 2, -- .module_bit = OMAP24XX_EN_UART3_SHIFT, -- .idlest_reg_id = 2, -- .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, - }, - }, -- .slaves = omap2420_uart3_slaves, -- .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), -- .class = &uart_class, -+ .slaves = omap2420_dss_venc_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_dss_venc_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -+ .flags = HWMOD_NO_IDLEST, - }; - - /* I2C common */ -@@ -864,16 +1828,342 @@ - .flags = HWMOD_NO_IDLEST, - }; - -+/* -+ * 'mailbox' class -+ * mailbox module allowing communication between the on-chip processors -+ * using a queued mailbox-interrupt mechanism. -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = { -+ .rev_offs = 0x000, -+ .sysc_offs = 0x010, -+ .syss_offs = 0x014, -+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap2420_mailbox_hwmod_class = { -+ .name = "mailbox", -+ .sysc = &omap2420_mailbox_sysc, -+}; -+ -+/* mailbox */ -+static struct omap_hwmod omap2420_mailbox_hwmod; -+static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { -+ { .name = "dsp", .irq = 26 }, -+ { .name = "iva", .irq = 34 }, -+}; -+ -+static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = { -+ { -+ .pa_start = 0x48094000, -+ .pa_end = 0x480941ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+/* l4_core -> mailbox */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_mailbox_hwmod, -+ .addr = omap2420_mailbox_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mailbox slave ports */ -+static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = { -+ &omap2420_l4_core__mailbox, -+}; -+ -+static struct omap_hwmod omap2420_mailbox_hwmod = { -+ .name = "mailbox", -+ .class = &omap2420_mailbox_hwmod_class, -+ .mpu_irqs = omap2420_mailbox_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs), -+ .main_clk = "mailboxes_ick", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_mailbox_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -+}; -+ -+/* -+ * 'mcspi' class -+ * multichannel serial port interface (mcspi) / master/slave synchronous serial -+ * bus -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap2420_mcspi_class = { -+ .name = "mcspi", -+ .sysc = &omap2420_mcspi_sysc, -+ .rev = OMAP2_MCSPI_REV, -+}; -+ -+/* mcspi1 */ -+static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = { -+ { .irq = 65 }, -+}; -+ -+static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = { -+ { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ -+ { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ -+ { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ -+ { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ -+ { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ -+ { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ -+ { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ -+ { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ -+}; -+ -+static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { -+ &omap2420_l4_core__mcspi1, -+}; -+ -+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { -+ .num_chipselect = 4, -+}; -+ -+static struct omap_hwmod omap2420_mcspi1_hwmod = { -+ .name = "mcspi1_hwmod", -+ .mpu_irqs = omap2420_mcspi1_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs), -+ .sdma_reqs = omap2420_mcspi1_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs), -+ .main_clk = "mcspi1_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_mcspi1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), -+ .class = &omap2420_mcspi_class, -+ .dev_attr = &omap_mcspi1_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -+}; -+ -+/* mcspi2 */ -+static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = { -+ { .irq = 66 }, -+}; -+ -+static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = { -+ { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ -+ { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ -+ { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ -+ { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ -+}; -+ -+static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { -+ &omap2420_l4_core__mcspi2, -+}; -+ -+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { -+ .num_chipselect = 2, -+}; -+ -+static struct omap_hwmod omap2420_mcspi2_hwmod = { -+ .name = "mcspi2_hwmod", -+ .mpu_irqs = omap2420_mcspi2_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs), -+ .sdma_reqs = omap2420_mcspi2_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs), -+ .main_clk = "mcspi2_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_mcspi2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), -+ .class = &omap2420_mcspi_class, -+ .dev_attr = &omap_mcspi2_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -+}; -+ -+/* -+ * 'mcbsp' class -+ * multi channel buffered serial port controller -+ */ -+ -+static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { -+ .name = "mcbsp", -+}; -+ -+/* mcbsp1 */ -+static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { -+ { .name = "tx", .irq = 59 }, -+ { .name = "rx", .irq = 60 }, -+}; -+ -+static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = { -+ { .name = "rx", .dma_req = 32 }, -+ { .name = "tx", .dma_req = 31 }, -+}; -+ -+static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = { -+ { -+ .name = "mpu", -+ .pa_start = 0x48074000, -+ .pa_end = 0x480740ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> mcbsp1 */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_mcbsp1_hwmod, -+ .clk = "mcbsp1_ick", -+ .addr = omap2420_mcbsp1_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_mcbsp1_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mcbsp1 slave ports */ -+static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = { -+ &omap2420_l4_core__mcbsp1, -+}; -+ -+static struct omap_hwmod omap2420_mcbsp1_hwmod = { -+ .name = "mcbsp1", -+ .class = &omap2420_mcbsp_hwmod_class, -+ .mpu_irqs = omap2420_mcbsp1_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_irqs), -+ .sdma_reqs = omap2420_mcbsp1_sdma_chs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs), -+ .main_clk = "mcbsp1_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_mcbsp1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -+}; -+ -+/* mcbsp2 */ -+static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { -+ { .name = "tx", .irq = 62 }, -+ { .name = "rx", .irq = 63 }, -+}; -+ -+static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = { -+ { .name = "rx", .dma_req = 34 }, -+ { .name = "tx", .dma_req = 33 }, -+}; -+ -+static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = { -+ { -+ .name = "mpu", -+ .pa_start = 0x48076000, -+ .pa_end = 0x480760ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> mcbsp2 */ -+static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { -+ .master = &omap2420_l4_core_hwmod, -+ .slave = &omap2420_mcbsp2_hwmod, -+ .clk = "mcbsp2_ick", -+ .addr = omap2420_mcbsp2_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2420_mcbsp2_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mcbsp2 slave ports */ -+static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = { -+ &omap2420_l4_core__mcbsp2, -+}; -+ -+static struct omap_hwmod omap2420_mcbsp2_hwmod = { -+ .name = "mcbsp2", -+ .class = &omap2420_mcbsp_hwmod_class, -+ .mpu_irqs = omap2420_mcbsp2_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_irqs), -+ .sdma_reqs = omap2420_mcbsp2_sdma_chs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs), -+ .main_clk = "mcbsp2_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, -+ }, -+ }, -+ .slaves = omap2420_mcbsp2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), -+}; -+ - static __initdata struct omap_hwmod *omap2420_hwmods[] = { - &omap2420_l3_main_hwmod, - &omap2420_l4_core_hwmod, - &omap2420_l4_wkup_hwmod, - &omap2420_mpu_hwmod, - &omap2420_iva_hwmod, -+ -+ &omap2420_timer1_hwmod, -+ &omap2420_timer2_hwmod, -+ &omap2420_timer3_hwmod, -+ &omap2420_timer4_hwmod, -+ &omap2420_timer5_hwmod, -+ &omap2420_timer6_hwmod, -+ &omap2420_timer7_hwmod, -+ &omap2420_timer8_hwmod, -+ &omap2420_timer9_hwmod, -+ &omap2420_timer10_hwmod, -+ &omap2420_timer11_hwmod, -+ &omap2420_timer12_hwmod, -+ - &omap2420_wd_timer2_hwmod, - &omap2420_uart1_hwmod, - &omap2420_uart2_hwmod, - &omap2420_uart3_hwmod, -+ /* dss class */ -+ &omap2420_dss_core_hwmod, -+ &omap2420_dss_dispc_hwmod, -+ &omap2420_dss_rfbi_hwmod, -+ &omap2420_dss_venc_hwmod, -+ /* i2c class */ - &omap2420_i2c1_hwmod, - &omap2420_i2c2_hwmod, - -@@ -885,10 +2175,21 @@ - - /* dma_system class*/ - &omap2420_dma_system_hwmod, -+ -+ /* mailbox class */ -+ &omap2420_mailbox_hwmod, -+ -+ /* mcbsp class */ -+ &omap2420_mcbsp1_hwmod, -+ &omap2420_mcbsp2_hwmod, -+ -+ /* mcspi class */ -+ &omap2420_mcspi1_hwmod, -+ &omap2420_mcspi2_hwmod, - NULL, - }; - - int __init omap2420_hwmod_init(void) - { -- return omap_hwmod_init(omap2420_hwmods); -+ return omap_hwmod_register(omap2420_hwmods); - } -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod_2430_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod_2430_data.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod_2430_data.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod_2430_data.c 2011-03-09 13:19:09.828507257 +0100 -@@ -18,6 +18,11 @@ - #include - #include - #include -+#include -+#include -+#include -+#include -+#include - - #include "omap_hwmod_common_data.h" - -@@ -38,6 +43,10 @@ - static struct omap_hwmod omap2430_iva_hwmod; - static struct omap_hwmod omap2430_l3_main_hwmod; - static struct omap_hwmod omap2430_l4_core_hwmod; -+static struct omap_hwmod omap2430_dss_core_hwmod; -+static struct omap_hwmod omap2430_dss_dispc_hwmod; -+static struct omap_hwmod omap2430_dss_rfbi_hwmod; -+static struct omap_hwmod omap2430_dss_venc_hwmod; - static struct omap_hwmod omap2430_wd_timer2_hwmod; - static struct omap_hwmod omap2430_gpio1_hwmod; - static struct omap_hwmod omap2430_gpio2_hwmod; -@@ -45,6 +54,16 @@ - static struct omap_hwmod omap2430_gpio4_hwmod; - static struct omap_hwmod omap2430_gpio5_hwmod; - static struct omap_hwmod omap2430_dma_system_hwmod; -+static struct omap_hwmod omap2430_mcbsp1_hwmod; -+static struct omap_hwmod omap2430_mcbsp2_hwmod; -+static struct omap_hwmod omap2430_mcbsp3_hwmod; -+static struct omap_hwmod omap2430_mcbsp4_hwmod; -+static struct omap_hwmod omap2430_mcbsp5_hwmod; -+static struct omap_hwmod omap2430_mcspi1_hwmod; -+static struct omap_hwmod omap2430_mcspi2_hwmod; -+static struct omap_hwmod omap2430_mcspi3_hwmod; -+static struct omap_hwmod omap2430_mmc1_hwmod; -+static struct omap_hwmod omap2430_mmc2_hwmod; - - /* L3 -> L4_CORE interface */ - static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { -@@ -65,6 +84,19 @@ - &omap2430_mpu__l3_main, - }; - -+/* DSS -> l3 */ -+static struct omap_hwmod_ocp_if omap2430_dss__l3 = { -+ .master = &omap2430_dss_core_hwmod, -+ .slave = &omap2430_l3_main_hwmod, -+ .fw = { -+ .omap2 = { -+ .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, -+ .flags = OMAP_FIREWALL_L3, -+ } -+ }, -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ - /* Master interfaces on the L3 interconnect */ - static struct omap_hwmod_ocp_if *omap2430_l3_main_masters[] = { - &omap2430_l3_main__l4_core, -@@ -89,6 +121,16 @@ - static struct omap_hwmod omap2430_i2c1_hwmod; - static struct omap_hwmod omap2430_i2c2_hwmod; - -+static struct omap_hwmod omap2430_usbhsotg_hwmod; -+ -+/* l3_core -> usbhsotg interface */ -+static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { -+ .master = &omap2430_usbhsotg_hwmod, -+ .slave = &omap2430_l3_main_hwmod, -+ .clk = "core_l3_ck", -+ .user = OCP_USER_MPU, -+}; -+ - /* I2C IP block address space length (in bytes) */ - #define OMAP2_I2C_AS_LEN 128 - -@@ -189,6 +231,71 @@ - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - -+/* -+* usbhsotg interface data -+*/ -+static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = { -+ { -+ .pa_start = OMAP243X_HS_BASE, -+ .pa_end = OMAP243X_HS_BASE + SZ_4K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core ->usbhsotg interface */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_usbhsotg_hwmod, -+ .clk = "usb_l4_ick", -+ .addr = omap2430_usbhsotg_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_usbhsotg_addrs), -+ .user = OCP_USER_MPU, -+}; -+ -+static struct omap_hwmod_ocp_if *omap2430_usbhsotg_masters[] = { -+ &omap2430_usbhsotg__l3, -+}; -+ -+static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = { -+ &omap2430_l4_core__usbhsotg, -+}; -+ -+/* L4 CORE -> MMC1 interface */ -+static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = { -+ { -+ .pa_start = 0x4809c000, -+ .pa_end = 0x4809c1ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_mmc1_hwmod, -+ .clk = "mmchs1_ick", -+ .addr = omap2430_mmc1_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap2430_mmc1_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* L4 CORE -> MMC2 interface */ -+static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = { -+ { -+ .pa_start = 0x480b4000, -+ .pa_end = 0x480b41ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_mmc2_hwmod, -+ .addr = omap2430_mmc2_addr_space, -+ .clk = "mmchs2_ick", -+ .addr_cnt = ARRAY_SIZE(omap2430_mmc2_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ - /* Slave interfaces on the L4_CORE interconnect */ - static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { - &omap2430_l3_main__l4_core, -@@ -197,6 +304,8 @@ - /* Master interfaces on the L4_CORE interconnect */ - static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { - &omap2430_l4_core__l4_wkup, -+ &omap2430_l4_core__mmc1, -+ &omap2430_l4_core__mmc2, - }; - - /* L4 CORE */ -@@ -223,6 +332,60 @@ - static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = { - }; - -+/* l4 core -> mcspi1 interface */ -+static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = { -+ { -+ .pa_start = 0x48098000, -+ .pa_end = 0x480980ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_mcspi1_hwmod, -+ .clk = "mcspi1_ick", -+ .addr = omap2430_mcspi1_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* l4 core -> mcspi2 interface */ -+static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = { -+ { -+ .pa_start = 0x4809a000, -+ .pa_end = 0x4809a0ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_mcspi2_hwmod, -+ .clk = "mcspi2_ick", -+ .addr = omap2430_mcspi2_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* l4 core -> mcspi3 interface */ -+static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = { -+ { -+ .pa_start = 0x480b8000, -+ .pa_end = 0x480b80ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_mcspi3_hwmod, -+ .clk = "mcspi3_ick", -+ .addr = omap2430_mcspi3_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ - /* L4 WKUP */ - static struct omap_hwmod omap2430_l4_wkup_hwmod = { - .name = "l4_wkup", -@@ -278,645 +441,2224 @@ - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) - }; - --/* l4_wkup -> wd_timer2 */ --static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { -- { -- .pa_start = 0x49016000, -- .pa_end = 0x4901607f, -- .flags = ADDR_TYPE_RT -- }, -+/* Timer Common */ -+static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, - }; - --static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { -- .master = &omap2430_l4_wkup_hwmod, -- .slave = &omap2430_wd_timer2_hwmod, -- .clk = "mpu_wdt_ick", -- .addr = omap2430_wd_timer2_addrs, -- .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs), -- .user = OCP_USER_MPU | OCP_USER_SDMA, -+static struct omap_hwmod_class omap2430_timer_hwmod_class = { -+ .name = "timer", -+ .sysc = &omap2430_timer_sysc, -+ .rev = OMAP_TIMER_IP_VERSION_1, - }; - --/* -- * 'wd_timer' class -- * 32-bit watchdog upward counter that generates a pulse on the reset pin on -- * overflow condition -- */ -+/* timer1 */ -+static struct omap_hwmod omap2430_timer1_hwmod; -+static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = { -+ { .irq = 37, }, -+}; - --static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { -- .rev_offs = 0x0, -- .sysc_offs = 0x0010, -- .syss_offs = 0x0014, -- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | -- SYSC_HAS_AUTOIDLE), -- .sysc_fields = &omap_hwmod_sysc_type1, -+static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { -+ { -+ .pa_start = 0x49018000, -+ .pa_end = 0x49018000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { -- .name = "wd_timer", -- .sysc = &omap2430_wd_timer_sysc, -- .pre_shutdown = &omap2_wd_timer_disable -+/* l4_wkup -> timer1 */ -+static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = { -+ .master = &omap2430_l4_wkup_hwmod, -+ .slave = &omap2430_timer1_hwmod, -+ .clk = "gpt1_ick", -+ .addr = omap2430_timer1_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --/* wd_timer2 */ --static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { -- &omap2430_l4_wkup__wd_timer2, -+/* timer1 slave port */ -+static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = { -+ &omap2430_l4_wkup__timer1, - }; - --static struct omap_hwmod omap2430_wd_timer2_hwmod = { -- .name = "wd_timer2", -- .class = &omap2430_wd_timer_hwmod_class, -- .main_clk = "mpu_wdt_fck", -+/* timer1 hwmod */ -+static struct omap_hwmod omap2430_timer1_hwmod = { -+ .name = "timer1", -+ .mpu_irqs = omap2430_timer1_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs), -+ .main_clk = "gpt1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, -- .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, -+ .module_bit = OMAP24XX_EN_GPT1_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, -- .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, -+ .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, - }, - }, -- .slaves = omap2430_wd_timer2_slaves, -- .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), -- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), --}; -- --/* UART */ -- --static struct omap_hwmod_class_sysconfig uart_sysc = { -- .rev_offs = 0x50, -- .sysc_offs = 0x54, -- .syss_offs = 0x58, -- .sysc_flags = (SYSC_HAS_SIDLEMODE | -- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -- SYSC_HAS_AUTOIDLE), -- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -- .sysc_fields = &omap_hwmod_sysc_type1, -+ .slaves = omap2430_timer1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves), -+ .class = &omap2430_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) - }; - --static struct omap_hwmod_class uart_class = { -- .name = "uart", -- .sysc = &uart_sysc, -+/* timer2 */ -+static struct omap_hwmod omap2430_timer2_hwmod; -+static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = { -+ { .irq = 38, }, - }; - --/* UART1 */ -- --static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { -- { .irq = INT_24XX_UART1_IRQ, }, -+static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = { -+ { -+ .pa_start = 0x4802a000, -+ .pa_end = 0x4802a000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { -- { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, -- { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, -+/* l4_core -> timer2 */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_timer2_hwmod, -+ .clk = "gpt2_ick", -+ .addr = omap2430_timer2_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { -- &omap2_l4_core__uart1, -+/* timer2 slave port */ -+static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = { -+ &omap2430_l4_core__timer2, - }; - --static struct omap_hwmod omap2430_uart1_hwmod = { -- .name = "uart1", -- .mpu_irqs = uart1_mpu_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), -- .sdma_reqs = uart1_sdma_reqs, -- .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), -- .main_clk = "uart1_fck", -+/* timer2 hwmod */ -+static struct omap_hwmod omap2430_timer2_hwmod = { -+ .name = "timer2", -+ .mpu_irqs = omap2430_timer2_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs), -+ .main_clk = "gpt2_fck", - .prcm = { - .omap2 = { -- .module_offs = CORE_MOD, - .prcm_reg_id = 1, -- .module_bit = OMAP24XX_EN_UART1_SHIFT, -+ .module_bit = OMAP24XX_EN_GPT2_SHIFT, -+ .module_offs = CORE_MOD, - .idlest_reg_id = 1, -- .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, -+ .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, - }, - }, -- .slaves = omap2430_uart1_slaves, -- .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), -- .class = &uart_class, -- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+ .slaves = omap2430_timer2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves), -+ .class = &omap2430_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) - }; - --/* UART2 */ -+/* timer3 */ -+static struct omap_hwmod omap2430_timer3_hwmod; -+static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = { -+ { .irq = 39, }, -+}; - --static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { -- { .irq = INT_24XX_UART2_IRQ, }, -+static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = { -+ { -+ .pa_start = 0x48078000, -+ .pa_end = 0x48078000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { -- { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, -- { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, -+/* l4_core -> timer3 */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_timer3_hwmod, -+ .clk = "gpt3_ick", -+ .addr = omap2430_timer3_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_timer3_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { -- &omap2_l4_core__uart2, -+/* timer3 slave port */ -+static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = { -+ &omap2430_l4_core__timer3, - }; - --static struct omap_hwmod omap2430_uart2_hwmod = { -- .name = "uart2", -- .mpu_irqs = uart2_mpu_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), -- .sdma_reqs = uart2_sdma_reqs, -- .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), -- .main_clk = "uart2_fck", -+/* timer3 hwmod */ -+static struct omap_hwmod omap2430_timer3_hwmod = { -+ .name = "timer3", -+ .mpu_irqs = omap2430_timer3_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs), -+ .main_clk = "gpt3_fck", - .prcm = { - .omap2 = { -- .module_offs = CORE_MOD, - .prcm_reg_id = 1, -- .module_bit = OMAP24XX_EN_UART2_SHIFT, -+ .module_bit = OMAP24XX_EN_GPT3_SHIFT, -+ .module_offs = CORE_MOD, - .idlest_reg_id = 1, -- .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, -+ .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, - }, - }, -- .slaves = omap2430_uart2_slaves, -- .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), -- .class = &uart_class, -- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+ .slaves = omap2430_timer3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves), -+ .class = &omap2430_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) - }; - --/* UART3 */ -+/* timer4 */ -+static struct omap_hwmod omap2430_timer4_hwmod; -+static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = { -+ { .irq = 40, }, -+}; - --static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { -- { .irq = INT_24XX_UART3_IRQ, }, -+static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = { -+ { -+ .pa_start = 0x4807a000, -+ .pa_end = 0x4807a000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { -- { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, -- { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, -+/* l4_core -> timer4 */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_timer4_hwmod, -+ .clk = "gpt4_ick", -+ .addr = omap2430_timer4_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_timer4_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { -- &omap2_l4_core__uart3, -+/* timer4 slave port */ -+static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = { -+ &omap2430_l4_core__timer4, - }; - --static struct omap_hwmod omap2430_uart3_hwmod = { -- .name = "uart3", -- .mpu_irqs = uart3_mpu_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), -- .sdma_reqs = uart3_sdma_reqs, -- .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), -- .main_clk = "uart3_fck", -+/* timer4 hwmod */ -+static struct omap_hwmod omap2430_timer4_hwmod = { -+ .name = "timer4", -+ .mpu_irqs = omap2430_timer4_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs), -+ .main_clk = "gpt4_fck", - .prcm = { - .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT4_SHIFT, - .module_offs = CORE_MOD, -- .prcm_reg_id = 2, -- .module_bit = OMAP24XX_EN_UART3_SHIFT, -- .idlest_reg_id = 2, -- .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, - }, - }, -- .slaves = omap2430_uart3_slaves, -- .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), -- .class = &uart_class, -- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+ .slaves = omap2430_timer4_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves), -+ .class = &omap2430_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) - }; - --/* I2C common */ --static struct omap_hwmod_class_sysconfig i2c_sysc = { -- .rev_offs = 0x00, -- .sysc_offs = 0x20, -- .syss_offs = 0x10, -- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), -- .sysc_fields = &omap_hwmod_sysc_type1, -+/* timer5 */ -+static struct omap_hwmod omap2430_timer5_hwmod; -+static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = { -+ { .irq = 41, }, - }; - --static struct omap_hwmod_class i2c_class = { -- .name = "i2c", -- .sysc = &i2c_sysc, -+static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = { -+ { -+ .pa_start = 0x4807c000, -+ .pa_end = 0x4807c000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_i2c_dev_attr i2c_dev_attr = { -- .fifo_depth = 8, /* bytes */ -+/* l4_core -> timer5 */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_timer5_hwmod, -+ .clk = "gpt5_ick", -+ .addr = omap2430_timer5_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_timer5_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --/* I2C1 */ -- --static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { -- { .irq = INT_24XX_I2C1_IRQ, }, -+/* timer5 slave port */ -+static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = { -+ &omap2430_l4_core__timer5, - }; - --static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { -- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, -- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, -+/* timer5 hwmod */ -+static struct omap_hwmod omap2430_timer5_hwmod = { -+ .name = "timer5", -+ .mpu_irqs = omap2430_timer5_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs), -+ .main_clk = "gpt5_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT5_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_timer5_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves), -+ .class = &omap2430_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) - }; - --static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { -- &omap2430_l4_core__i2c1, -+/* timer6 */ -+static struct omap_hwmod omap2430_timer6_hwmod; -+static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = { -+ { .irq = 42, }, - }; - --static struct omap_hwmod omap2430_i2c1_hwmod = { -- .name = "i2c1", -- .mpu_irqs = i2c1_mpu_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), -- .sdma_reqs = i2c1_sdma_reqs, -- .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), -- .main_clk = "i2chs1_fck", -+static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = { -+ { -+ .pa_start = 0x4807e000, -+ .pa_end = 0x4807e000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> timer6 */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_timer6_hwmod, -+ .clk = "gpt6_ick", -+ .addr = omap2430_timer6_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_timer6_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer6 slave port */ -+static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = { -+ &omap2430_l4_core__timer6, -+}; -+ -+/* timer6 hwmod */ -+static struct omap_hwmod omap2430_timer6_hwmod = { -+ .name = "timer6", -+ .mpu_irqs = omap2430_timer6_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs), -+ .main_clk = "gpt6_fck", - .prcm = { - .omap2 = { -- /* -- * NOTE: The CM_FCLKEN* and CM_ICLKEN* for -- * I2CHS IP's do not follow the usual pattern. -- * prcm_reg_id alone cannot be used to program -- * the iclk and fclk. Needs to be handled using -- * additonal flags when clk handling is moved -- * to hwmod framework. -- */ -- .module_offs = CORE_MOD, - .prcm_reg_id = 1, -- .module_bit = OMAP2430_EN_I2CHS1_SHIFT, -+ .module_bit = OMAP24XX_EN_GPT6_SHIFT, -+ .module_offs = CORE_MOD, - .idlest_reg_id = 1, -- .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, -+ .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, - }, - }, -- .slaves = omap2430_i2c1_slaves, -- .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), -- .class = &i2c_class, -- .dev_attr = &i2c_dev_attr, -- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+ .slaves = omap2430_timer6_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves), -+ .class = &omap2430_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) - }; - --/* I2C2 */ -+/* timer7 */ -+static struct omap_hwmod omap2430_timer7_hwmod; -+static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = { -+ { .irq = 43, }, -+}; - --static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { -- { .irq = INT_24XX_I2C2_IRQ, }, -+static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = { -+ { -+ .pa_start = 0x48080000, -+ .pa_end = 0x48080000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { -- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, -- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, -+/* l4_core -> timer7 */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_timer7_hwmod, -+ .clk = "gpt7_ick", -+ .addr = omap2430_timer7_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_timer7_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { -- &omap2430_l4_core__i2c2, -+/* timer7 slave port */ -+static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = { -+ &omap2430_l4_core__timer7, - }; - --static struct omap_hwmod omap2430_i2c2_hwmod = { -- .name = "i2c2", -- .mpu_irqs = i2c2_mpu_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), -- .sdma_reqs = i2c2_sdma_reqs, -- .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), -- .main_clk = "i2chs2_fck", -+/* timer7 hwmod */ -+static struct omap_hwmod omap2430_timer7_hwmod = { -+ .name = "timer7", -+ .mpu_irqs = omap2430_timer7_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs), -+ .main_clk = "gpt7_fck", - .prcm = { - .omap2 = { -- .module_offs = CORE_MOD, - .prcm_reg_id = 1, -- .module_bit = OMAP2430_EN_I2CHS2_SHIFT, -+ .module_bit = OMAP24XX_EN_GPT7_SHIFT, -+ .module_offs = CORE_MOD, - .idlest_reg_id = 1, -- .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, -+ .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, - }, - }, -- .slaves = omap2430_i2c2_slaves, -- .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), -- .class = &i2c_class, -- .dev_attr = &i2c_dev_attr, -- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+ .slaves = omap2430_timer7_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves), -+ .class = &omap2430_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) - }; - --/* l4_wkup -> gpio1 */ --static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { -+/* timer8 */ -+static struct omap_hwmod omap2430_timer8_hwmod; -+static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = { -+ { .irq = 44, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = { - { -- .pa_start = 0x4900C000, -- .pa_end = 0x4900C1ff, -+ .pa_start = 0x48082000, -+ .pa_end = 0x48082000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - }; - --static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { -- .master = &omap2430_l4_wkup_hwmod, -- .slave = &omap2430_gpio1_hwmod, -- .clk = "gpios_ick", -- .addr = omap2430_gpio1_addr_space, -- .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space), -+/* l4_core -> timer8 */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_timer8_hwmod, -+ .clk = "gpt8_ick", -+ .addr = omap2430_timer8_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_timer8_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --/* l4_wkup -> gpio2 */ --static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { -+/* timer8 slave port */ -+static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = { -+ &omap2430_l4_core__timer8, -+}; -+ -+/* timer8 hwmod */ -+static struct omap_hwmod omap2430_timer8_hwmod = { -+ .name = "timer8", -+ .mpu_irqs = omap2430_timer8_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs), -+ .main_clk = "gpt8_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT8_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_timer8_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves), -+ .class = &omap2430_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) -+}; -+ -+/* timer9 */ -+static struct omap_hwmod omap2430_timer9_hwmod; -+static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = { -+ { .irq = 45, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = { - { -- .pa_start = 0x4900E000, -- .pa_end = 0x4900E1ff, -+ .pa_start = 0x48084000, -+ .pa_end = 0x48084000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - }; - --static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { -- .master = &omap2430_l4_wkup_hwmod, -- .slave = &omap2430_gpio2_hwmod, -- .clk = "gpios_ick", -- .addr = omap2430_gpio2_addr_space, -- .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space), -+/* l4_core -> timer9 */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_timer9_hwmod, -+ .clk = "gpt9_ick", -+ .addr = omap2430_timer9_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_timer9_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --/* l4_wkup -> gpio3 */ --static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { -+/* timer9 slave port */ -+static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = { -+ &omap2430_l4_core__timer9, -+}; -+ -+/* timer9 hwmod */ -+static struct omap_hwmod omap2430_timer9_hwmod = { -+ .name = "timer9", -+ .mpu_irqs = omap2430_timer9_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs), -+ .main_clk = "gpt9_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT9_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_timer9_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves), -+ .class = &omap2430_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) -+}; -+ -+/* timer10 */ -+static struct omap_hwmod omap2430_timer10_hwmod; -+static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = { -+ { .irq = 46, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = { - { -- .pa_start = 0x49010000, -- .pa_end = 0x490101ff, -+ .pa_start = 0x48086000, -+ .pa_end = 0x48086000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - }; - --static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { -- .master = &omap2430_l4_wkup_hwmod, -- .slave = &omap2430_gpio3_hwmod, -- .clk = "gpios_ick", -- .addr = omap2430_gpio3_addr_space, -- .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space), -+/* l4_core -> timer10 */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_timer10_hwmod, -+ .clk = "gpt10_ick", -+ .addr = omap2430_timer10_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_timer10_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --/* l4_wkup -> gpio4 */ --static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { -+/* timer10 slave port */ -+static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = { -+ &omap2430_l4_core__timer10, -+}; -+ -+/* timer10 hwmod */ -+static struct omap_hwmod omap2430_timer10_hwmod = { -+ .name = "timer10", -+ .mpu_irqs = omap2430_timer10_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs), -+ .main_clk = "gpt10_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT10_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_timer10_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves), -+ .class = &omap2430_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) -+}; -+ -+/* timer11 */ -+static struct omap_hwmod omap2430_timer11_hwmod; -+static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = { -+ { .irq = 47, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = { - { -- .pa_start = 0x49012000, -- .pa_end = 0x490121ff, -+ .pa_start = 0x48088000, -+ .pa_end = 0x48088000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - }; - --static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { -- .master = &omap2430_l4_wkup_hwmod, -- .slave = &omap2430_gpio4_hwmod, -- .clk = "gpios_ick", -- .addr = omap2430_gpio4_addr_space, -- .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space), -+/* l4_core -> timer11 */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_timer11_hwmod, -+ .clk = "gpt11_ick", -+ .addr = omap2430_timer11_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_timer11_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --/* l4_core -> gpio5 */ --static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { -+/* timer11 slave port */ -+static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = { -+ &omap2430_l4_core__timer11, -+}; -+ -+/* timer11 hwmod */ -+static struct omap_hwmod omap2430_timer11_hwmod = { -+ .name = "timer11", -+ .mpu_irqs = omap2430_timer11_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs), -+ .main_clk = "gpt11_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT11_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_timer11_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves), -+ .class = &omap2430_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) -+}; -+ -+/* timer12 */ -+static struct omap_hwmod omap2430_timer12_hwmod; -+static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = { -+ { .irq = 48, }, -+}; -+ -+static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = { - { -- .pa_start = 0x480B6000, -- .pa_end = 0x480B61ff, -+ .pa_start = 0x4808a000, -+ .pa_end = 0x4808a000 + SZ_1K - 1, - .flags = ADDR_TYPE_RT - }, - }; - --static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { -+/* l4_core -> timer12 */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { - .master = &omap2430_l4_core_hwmod, -- .slave = &omap2430_gpio5_hwmod, -- .clk = "gpio5_ick", -- .addr = omap2430_gpio5_addr_space, -- .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space), -+ .slave = &omap2430_timer12_hwmod, -+ .clk = "gpt12_ick", -+ .addr = omap2430_timer12_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_timer12_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer12 slave port */ -+static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = { -+ &omap2430_l4_core__timer12, -+}; -+ -+/* timer12 hwmod */ -+static struct omap_hwmod omap2430_timer12_hwmod = { -+ .name = "timer12", -+ .mpu_irqs = omap2430_timer12_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs), -+ .main_clk = "gpt12_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPT12_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_timer12_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves), -+ .class = &omap2430_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) -+}; -+ -+/* l4_wkup -> wd_timer2 */ -+static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = { -+ { -+ .pa_start = 0x49016000, -+ .pa_end = 0x4901607f, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { -+ .master = &omap2430_l4_wkup_hwmod, -+ .slave = &omap2430_wd_timer2_hwmod, -+ .clk = "mpu_wdt_ick", -+ .addr = omap2430_wd_timer2_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --/* gpio dev_attr */ --static struct omap_gpio_dev_attr gpio_dev_attr = { -- .bank_width = 32, -- .dbck_flag = false, -+/* -+ * 'wd_timer' class -+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on -+ * overflow condition -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = { -+ .rev_offs = 0x0, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = { -+ .name = "wd_timer", -+ .sysc = &omap2430_wd_timer_sysc, -+ .pre_shutdown = &omap2_wd_timer_disable -+}; -+ -+/* wd_timer2 */ -+static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { -+ &omap2430_l4_wkup__wd_timer2, -+}; -+ -+static struct omap_hwmod omap2430_wd_timer2_hwmod = { -+ .name = "wd_timer2", -+ .class = &omap2430_wd_timer_hwmod_class, -+ .main_clk = "mpu_wdt_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, -+ .module_offs = WKUP_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_wd_timer2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_wd_timer2_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+}; -+ -+/* UART */ -+ -+static struct omap_hwmod_class_sysconfig uart_sysc = { -+ .rev_offs = 0x50, -+ .sysc_offs = 0x54, -+ .syss_offs = 0x58, -+ .sysc_flags = (SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class uart_class = { -+ .name = "uart", -+ .sysc = &uart_sysc, -+}; -+ -+/* UART1 */ -+ -+static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { -+ { .irq = INT_24XX_UART1_IRQ, }, -+}; -+ -+static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { -+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, -+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { -+ &omap2_l4_core__uart1, -+}; -+ -+static struct omap_hwmod omap2430_uart1_hwmod = { -+ .name = "uart1", -+ .mpu_irqs = uart1_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), -+ .sdma_reqs = uart1_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), -+ .main_clk = "uart1_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_UART1_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_uart1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), -+ .class = &uart_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+}; -+ -+/* UART2 */ -+ -+static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { -+ { .irq = INT_24XX_UART2_IRQ, }, -+}; -+ -+static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { -+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, -+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { -+ &omap2_l4_core__uart2, -+}; -+ -+static struct omap_hwmod omap2430_uart2_hwmod = { -+ .name = "uart2", -+ .mpu_irqs = uart2_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), -+ .sdma_reqs = uart2_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), -+ .main_clk = "uart2_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_UART2_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_uart2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), -+ .class = &uart_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+}; -+ -+/* UART3 */ -+ -+static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { -+ { .irq = INT_24XX_UART3_IRQ, }, -+}; -+ -+static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { -+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, -+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { -+ &omap2_l4_core__uart3, -+}; -+ -+static struct omap_hwmod omap2430_uart3_hwmod = { -+ .name = "uart3", -+ .mpu_irqs = uart3_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), -+ .sdma_reqs = uart3_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), -+ .main_clk = "uart3_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 2, -+ .module_bit = OMAP24XX_EN_UART3_SHIFT, -+ .idlest_reg_id = 2, -+ .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_uart3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), -+ .class = &uart_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+}; -+ -+/* -+ * 'dss' class -+ * display sub-system -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap2430_dss_hwmod_class = { -+ .name = "dss", -+ .sysc = &omap2430_dss_sysc, -+}; -+ -+static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = { -+ { .name = "dispc", .dma_req = 5 }, -+}; -+ -+/* dss */ -+/* dss master ports */ -+static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = { -+ &omap2430_dss__l3, -+}; -+ -+static struct omap_hwmod_addr_space omap2430_dss_addrs[] = { -+ { -+ .pa_start = 0x48050000, -+ .pa_end = 0x480503FF, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> dss */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_dss_core_hwmod, -+ .clk = "dss_ick", -+ .addr = omap2430_dss_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_dss_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* dss slave ports */ -+static struct omap_hwmod_ocp_if *omap2430_dss_slaves[] = { -+ &omap2430_l4_core__dss, -+}; -+ -+static struct omap_hwmod_opt_clk dss_opt_clks[] = { -+ { .role = "tv_clk", .clk = "dss_54m_fck" }, -+ { .role = "sys_clk", .clk = "dss2_fck" }, -+}; -+ -+static struct omap_hwmod omap2430_dss_core_hwmod = { -+ .name = "dss_core", -+ .class = &omap2430_dss_hwmod_class, -+ .main_clk = "dss1_fck", /* instead of dss_fck */ -+ .sdma_reqs = omap2430_dss_sdma_chs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_dss_sdma_chs), -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_DSS1_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, -+ }, -+ }, -+ .opt_clks = dss_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), -+ .slaves = omap2430_dss_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_dss_slaves), -+ .masters = omap2430_dss_masters, -+ .masters_cnt = ARRAY_SIZE(omap2430_dss_masters), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+ .flags = HWMOD_NO_IDLEST, -+}; -+ -+/* -+ * 'dispc' class -+ * display controller -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | -+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap2430_dispc_hwmod_class = { -+ .name = "dispc", -+ .sysc = &omap2430_dispc_sysc, -+}; -+ -+static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = { -+ { .irq = 25 }, -+}; -+ -+static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = { -+ { -+ .pa_start = 0x48050400, -+ .pa_end = 0x480507FF, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> dss_dispc */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_dss_dispc_hwmod, -+ .clk = "dss_ick", -+ .addr = omap2430_dss_dispc_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_dss_dispc_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* dss_dispc slave ports */ -+static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = { -+ &omap2430_l4_core__dss_dispc, -+}; -+ -+static struct omap_hwmod omap2430_dss_dispc_hwmod = { -+ .name = "dss_dispc", -+ .class = &omap2430_dispc_hwmod_class, -+ .mpu_irqs = omap2430_dispc_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dispc_irqs), -+ .main_clk = "dss1_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_DSS1_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_dss_dispc_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_dss_dispc_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+ .flags = HWMOD_NO_IDLEST, -+}; -+ -+/* -+ * 'rfbi' class -+ * remote frame buffer interface -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap2430_rfbi_hwmod_class = { -+ .name = "rfbi", -+ .sysc = &omap2430_rfbi_sysc, -+}; -+ -+static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = { -+ { -+ .pa_start = 0x48050800, -+ .pa_end = 0x48050BFF, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> dss_rfbi */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_dss_rfbi_hwmod, -+ .clk = "dss_ick", -+ .addr = omap2430_dss_rfbi_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_dss_rfbi_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* dss_rfbi slave ports */ -+static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = { -+ &omap2430_l4_core__dss_rfbi, -+}; -+ -+static struct omap_hwmod omap2430_dss_rfbi_hwmod = { -+ .name = "dss_rfbi", -+ .class = &omap2430_rfbi_hwmod_class, -+ .main_clk = "dss1_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_DSS1_SHIFT, -+ .module_offs = CORE_MOD, -+ }, -+ }, -+ .slaves = omap2430_dss_rfbi_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_dss_rfbi_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+ .flags = HWMOD_NO_IDLEST, -+}; -+ -+/* -+ * 'venc' class -+ * video encoder -+ */ -+ -+static struct omap_hwmod_class omap2430_venc_hwmod_class = { -+ .name = "venc", -+}; -+ -+/* dss_venc */ -+static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = { -+ { -+ .pa_start = 0x48050C00, -+ .pa_end = 0x48050FFF, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> dss_venc */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_dss_venc_hwmod, -+ .clk = "dss_54m_fck", -+ .addr = omap2430_dss_venc_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* dss_venc slave ports */ -+static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = { -+ &omap2430_l4_core__dss_venc, -+}; -+ -+static struct omap_hwmod omap2430_dss_venc_hwmod = { -+ .name = "dss_venc", -+ .class = &omap2430_venc_hwmod_class, -+ .main_clk = "dss1_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_DSS1_SHIFT, -+ .module_offs = CORE_MOD, -+ }, -+ }, -+ .slaves = omap2430_dss_venc_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_dss_venc_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+ .flags = HWMOD_NO_IDLEST, -+}; -+ -+/* I2C common */ -+static struct omap_hwmod_class_sysconfig i2c_sysc = { -+ .rev_offs = 0x00, -+ .sysc_offs = 0x20, -+ .syss_offs = 0x10, -+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class i2c_class = { -+ .name = "i2c", -+ .sysc = &i2c_sysc, -+}; -+ -+static struct omap_i2c_dev_attr i2c_dev_attr = { -+ .fifo_depth = 8, /* bytes */ -+}; -+ -+/* I2C1 */ -+ -+static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { -+ { .irq = INT_24XX_I2C1_IRQ, }, -+}; -+ -+static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { -+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, -+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { -+ &omap2430_l4_core__i2c1, -+}; -+ -+static struct omap_hwmod omap2430_i2c1_hwmod = { -+ .name = "i2c1", -+ .mpu_irqs = i2c1_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), -+ .sdma_reqs = i2c1_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), -+ .main_clk = "i2chs1_fck", -+ .prcm = { -+ .omap2 = { -+ /* -+ * NOTE: The CM_FCLKEN* and CM_ICLKEN* for -+ * I2CHS IP's do not follow the usual pattern. -+ * prcm_reg_id alone cannot be used to program -+ * the iclk and fclk. Needs to be handled using -+ * additonal flags when clk handling is moved -+ * to hwmod framework. -+ */ -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP2430_EN_I2CHS1_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_i2c1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), -+ .class = &i2c_class, -+ .dev_attr = &i2c_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+}; -+ -+/* I2C2 */ -+ -+static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { -+ { .irq = INT_24XX_I2C2_IRQ, }, -+}; -+ -+static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { -+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, -+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { -+ &omap2430_l4_core__i2c2, -+}; -+ -+static struct omap_hwmod omap2430_i2c2_hwmod = { -+ .name = "i2c2", -+ .mpu_irqs = i2c2_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), -+ .sdma_reqs = i2c2_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), -+ .main_clk = "i2chs2_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP2430_EN_I2CHS2_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_i2c2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), -+ .class = &i2c_class, -+ .dev_attr = &i2c_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+}; -+ -+/* l4_wkup -> gpio1 */ -+static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = { -+ { -+ .pa_start = 0x4900C000, -+ .pa_end = 0x4900C1ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { -+ .master = &omap2430_l4_wkup_hwmod, -+ .slave = &omap2430_gpio1_hwmod, -+ .clk = "gpios_ick", -+ .addr = omap2430_gpio1_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* l4_wkup -> gpio2 */ -+static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = { -+ { -+ .pa_start = 0x4900E000, -+ .pa_end = 0x4900E1ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { -+ .master = &omap2430_l4_wkup_hwmod, -+ .slave = &omap2430_gpio2_hwmod, -+ .clk = "gpios_ick", -+ .addr = omap2430_gpio2_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* l4_wkup -> gpio3 */ -+static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = { -+ { -+ .pa_start = 0x49010000, -+ .pa_end = 0x490101ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { -+ .master = &omap2430_l4_wkup_hwmod, -+ .slave = &omap2430_gpio3_hwmod, -+ .clk = "gpios_ick", -+ .addr = omap2430_gpio3_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* l4_wkup -> gpio4 */ -+static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = { -+ { -+ .pa_start = 0x49012000, -+ .pa_end = 0x490121ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { -+ .master = &omap2430_l4_wkup_hwmod, -+ .slave = &omap2430_gpio4_hwmod, -+ .clk = "gpios_ick", -+ .addr = omap2430_gpio4_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* l4_core -> gpio5 */ -+static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = { -+ { -+ .pa_start = 0x480B6000, -+ .pa_end = 0x480B61ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_gpio5_hwmod, -+ .clk = "gpio5_ick", -+ .addr = omap2430_gpio5_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* gpio dev_attr */ -+static struct omap_gpio_dev_attr gpio_dev_attr = { -+ .bank_width = 32, -+ .dbck_flag = false, -+}; -+ -+static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+/* -+ * 'gpio' class -+ * general purpose io module -+ */ -+static struct omap_hwmod_class omap243x_gpio_hwmod_class = { -+ .name = "gpio", -+ .sysc = &omap243x_gpio_sysc, -+ .rev = 0, -+}; -+ -+/* gpio1 */ -+static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = { -+ { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ -+}; -+ -+static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { -+ &omap2430_l4_wkup__gpio1, -+}; -+ -+static struct omap_hwmod omap2430_gpio1_hwmod = { -+ .name = "gpio1", -+ .mpu_irqs = omap243x_gpio1_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), -+ .main_clk = "gpios_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPIOS_SHIFT, -+ .module_offs = WKUP_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_gpio1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), -+ .class = &omap243x_gpio_hwmod_class, -+ .dev_attr = &gpio_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+}; -+ -+/* gpio2 */ -+static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = { -+ { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ -+}; -+ -+static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { -+ &omap2430_l4_wkup__gpio2, -+}; -+ -+static struct omap_hwmod omap2430_gpio2_hwmod = { -+ .name = "gpio2", -+ .mpu_irqs = omap243x_gpio2_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs), -+ .main_clk = "gpios_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPIOS_SHIFT, -+ .module_offs = WKUP_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_gpio2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), -+ .class = &omap243x_gpio_hwmod_class, -+ .dev_attr = &gpio_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+}; -+ -+/* gpio3 */ -+static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = { -+ { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ -+}; -+ -+static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { -+ &omap2430_l4_wkup__gpio3, -+}; -+ -+static struct omap_hwmod omap2430_gpio3_hwmod = { -+ .name = "gpio3", -+ .mpu_irqs = omap243x_gpio3_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs), -+ .main_clk = "gpios_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPIOS_SHIFT, -+ .module_offs = WKUP_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_gpio3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), -+ .class = &omap243x_gpio_hwmod_class, -+ .dev_attr = &gpio_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+}; -+ -+/* gpio4 */ -+static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = { -+ { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ -+}; -+ -+static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { -+ &omap2430_l4_wkup__gpio4, -+}; -+ -+static struct omap_hwmod omap2430_gpio4_hwmod = { -+ .name = "gpio4", -+ .mpu_irqs = omap243x_gpio4_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs), -+ .main_clk = "gpios_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_GPIOS_SHIFT, -+ .module_offs = WKUP_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_gpio4_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), -+ .class = &omap243x_gpio_hwmod_class, -+ .dev_attr = &gpio_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+}; -+ -+/* gpio5 */ -+static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { -+ { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ -+}; -+ -+static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { -+ &omap2430_l4_core__gpio5, -+}; -+ -+static struct omap_hwmod omap2430_gpio5_hwmod = { -+ .name = "gpio5", -+ .mpu_irqs = omap243x_gpio5_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs), -+ .main_clk = "gpio5_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 2, -+ .module_bit = OMAP2430_EN_GPIO5_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 2, -+ .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_gpio5_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), -+ .class = &omap243x_gpio_hwmod_class, -+ .dev_attr = &gpio_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+}; -+ -+/* dma_system */ -+static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x002c, -+ .syss_offs = 0x0028, -+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | -+ SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | -+ SYSC_HAS_AUTOIDLE), -+ .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap2430_dma_hwmod_class = { -+ .name = "dma", -+ .sysc = &omap2430_dma_sysc, -+}; -+ -+/* dma attributes */ -+static struct omap_dma_dev_attr dma_dev_attr = { -+ .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | -+ IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, -+ .lch_count = 32, -+}; -+ -+static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = { -+ { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ -+ { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ -+ { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ -+ { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ -+}; -+ -+static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = { -+ { -+ .pa_start = 0x48056000, -+ .pa_end = 0x4a0560ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* dma_system -> L3 */ -+static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { -+ .master = &omap2430_dma_system_hwmod, -+ .slave = &omap2430_l3_main_hwmod, -+ .clk = "core_l3_ck", -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* dma_system master ports */ -+static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { -+ &omap2430_dma_system__l3, -+}; -+ -+/* l4_core -> dma_system */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_dma_system_hwmod, -+ .clk = "sdma_ick", -+ .addr = omap2430_dma_system_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* dma_system slave ports */ -+static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { -+ &omap2430_l4_core__dma_system, -+}; -+ -+static struct omap_hwmod omap2430_dma_system_hwmod = { -+ .name = "dma", -+ .class = &omap2430_dma_hwmod_class, -+ .mpu_irqs = omap2430_dma_system_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs), -+ .main_clk = "core_l3_ck", -+ .slaves = omap2430_dma_system_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), -+ .masters = omap2430_dma_system_masters, -+ .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), -+ .dev_attr = &dma_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+ .flags = HWMOD_NO_IDLEST, -+}; -+ -+/* -+ * 'mailbox' class -+ * mailbox module allowing communication between the on-chip processors -+ * using a queued mailbox-interrupt mechanism. -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = { -+ .rev_offs = 0x000, -+ .sysc_offs = 0x010, -+ .syss_offs = 0x014, -+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap2430_mailbox_hwmod_class = { -+ .name = "mailbox", -+ .sysc = &omap2430_mailbox_sysc, -+}; -+ -+/* mailbox */ -+static struct omap_hwmod omap2430_mailbox_hwmod; -+static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { -+ { .irq = 26 }, -+}; -+ -+static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = { -+ { -+ .pa_start = 0x48094000, -+ .pa_end = 0x480941ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+/* l4_core -> mailbox */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_mailbox_hwmod, -+ .addr = omap2430_mailbox_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_mailbox_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mailbox slave ports */ -+static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = { -+ &omap2430_l4_core__mailbox, -+}; -+ -+static struct omap_hwmod omap2430_mailbox_hwmod = { -+ .name = "mailbox", -+ .class = &omap2430_mailbox_hwmod_class, -+ .mpu_irqs = omap2430_mailbox_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mailbox_irqs), -+ .main_clk = "mailboxes_ick", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_mailbox_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+}; -+ -+/* -+ * 'mcspi' class -+ * multichannel serial port interface (mcspi) / master/slave synchronous serial -+ * bus -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap2430_mcspi_class = { -+ .name = "mcspi", -+ .sysc = &omap2430_mcspi_sysc, -+ .rev = OMAP2_MCSPI_REV, -+}; -+ -+/* mcspi1 */ -+static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = { -+ { .irq = 65 }, -+}; -+ -+static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = { -+ { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */ -+ { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */ -+ { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */ -+ { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */ -+ { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */ -+ { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */ -+ { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */ -+ { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */ -+}; -+ -+static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { -+ &omap2430_l4_core__mcspi1, -+}; -+ -+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { -+ .num_chipselect = 4, -+}; -+ -+static struct omap_hwmod omap2430_mcspi1_hwmod = { -+ .name = "mcspi1_hwmod", -+ .mpu_irqs = omap2430_mcspi1_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs), -+ .sdma_reqs = omap2430_mcspi1_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs), -+ .main_clk = "mcspi1_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_mcspi1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), -+ .class = &omap2430_mcspi_class, -+ .dev_attr = &omap_mcspi1_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+}; -+ -+/* mcspi2 */ -+static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = { -+ { .irq = 66 }, -+}; -+ -+static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = { -+ { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */ -+ { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */ -+ { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */ -+ { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */ -+}; -+ -+static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { -+ &omap2430_l4_core__mcspi2, -+}; -+ -+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { -+ .num_chipselect = 2, -+}; -+ -+static struct omap_hwmod omap2430_mcspi2_hwmod = { -+ .name = "mcspi2_hwmod", -+ .mpu_irqs = omap2430_mcspi2_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs), -+ .sdma_reqs = omap2430_mcspi2_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs), -+ .main_clk = "mcspi2_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_mcspi2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), -+ .class = &omap2430_mcspi_class, -+ .dev_attr = &omap_mcspi2_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+}; -+ -+/* mcspi3 */ -+static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { -+ { .irq = 91 }, -+}; -+ -+static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { -+ { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */ -+ { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ -+ { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ -+ { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ -+}; -+ -+static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { -+ &omap2430_l4_core__mcspi3, -+}; -+ -+static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { -+ .num_chipselect = 2, -+}; -+ -+static struct omap_hwmod omap2430_mcspi3_hwmod = { -+ .name = "mcspi3_hwmod", -+ .mpu_irqs = omap2430_mcspi3_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs), -+ .sdma_reqs = omap2430_mcspi3_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs), -+ .main_clk = "mcspi3_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 2, -+ .module_bit = OMAP2430_EN_MCSPI3_SHIFT, -+ .idlest_reg_id = 2, -+ .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_mcspi3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), -+ .class = &omap2430_mcspi_class, -+ .dev_attr = &omap_mcspi3_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -+}; -+ -+/* -+ * usbhsotg -+ */ -+static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { -+ .rev_offs = 0x0400, -+ .sysc_offs = 0x0404, -+ .syss_offs = 0x0408, -+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class usbotg_class = { -+ .name = "usbotg", -+ .sysc = &omap2430_usbhsotg_sysc, -+}; -+ -+/* usb_otg_hs */ -+static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = { -+ -+ { .name = "mc", .irq = 92 }, -+ { .name = "dma", .irq = 93 }, -+}; -+ -+static struct omap_hwmod omap2430_usbhsotg_hwmod = { -+ .name = "usb_otg_hs", -+ .mpu_irqs = omap2430_usbhsotg_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs), -+ .main_clk = "usbhs_ick", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP2430_EN_USBHS_MASK, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, -+ }, -+ }, -+ .masters = omap2430_usbhsotg_masters, -+ .masters_cnt = ARRAY_SIZE(omap2430_usbhsotg_masters), -+ .slaves = omap2430_usbhsotg_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_usbhsotg_slaves), -+ .class = &usbotg_class, -+ /* -+ * Erratum ID: i479 idle_req / idle_ack mechanism potentially -+ * broken when autoidle is enabled -+ * workaround is to disable the autoidle bit at module level. -+ */ -+ .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE -+ | HWMOD_SWSUP_MSTANDBY, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) -+}; -+ -+/* -+ * 'mcbsp' class -+ * multi channel buffered serial port controller -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { -+ .rev_offs = 0x007C, -+ .sysc_offs = 0x008C, -+ .sysc_flags = (SYSC_HAS_SOFTRESET), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { -+ .name = "mcbsp", -+ .sysc = &omap2430_mcbsp_sysc, -+ .rev = MCBSP_CONFIG_TYPE2, - }; - --static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = { -- .rev_offs = 0x0000, -- .sysc_offs = 0x0010, -- .syss_offs = 0x0014, -- .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | -- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), -- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -- .sysc_fields = &omap_hwmod_sysc_type1, -+/* mcbsp1 */ -+static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { -+ { .name = "tx", .irq = 59 }, -+ { .name = "rx", .irq = 60 }, -+ { .name = "ovr", .irq = 61 }, -+ { .name = "common", .irq = 64 }, - }; - --/* -- * 'gpio' class -- * general purpose io module -- */ --static struct omap_hwmod_class omap243x_gpio_hwmod_class = { -- .name = "gpio", -- .sysc = &omap243x_gpio_sysc, -- .rev = 0, -+static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = { -+ { .name = "rx", .dma_req = 32 }, -+ { .name = "tx", .dma_req = 31 }, - }; - --/* gpio1 */ --static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = { -- { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */ -+static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = { -+ { -+ .name = "mpu", -+ .pa_start = 0x48074000, -+ .pa_end = 0x480740ff, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { -- &omap2430_l4_wkup__gpio1, -+/* l4_core -> mcbsp1 */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_mcbsp1_hwmod, -+ .clk = "mcbsp1_ick", -+ .addr = omap2430_mcbsp1_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_mcbsp1_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --static struct omap_hwmod omap2430_gpio1_hwmod = { -- .name = "gpio1", -- .mpu_irqs = omap243x_gpio1_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs), -- .main_clk = "gpios_fck", -+/* mcbsp1 slave ports */ -+static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = { -+ &omap2430_l4_core__mcbsp1, -+}; -+ -+static struct omap_hwmod omap2430_mcbsp1_hwmod = { -+ .name = "mcbsp1", -+ .class = &omap2430_mcbsp_hwmod_class, -+ .mpu_irqs = omap2430_mcbsp1_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_irqs), -+ .sdma_reqs = omap2430_mcbsp1_sdma_chs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs), -+ .main_clk = "mcbsp1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, -- .module_bit = OMAP24XX_EN_GPIOS_SHIFT, -- .module_offs = WKUP_MOD, -+ .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, -+ .module_offs = CORE_MOD, - .idlest_reg_id = 1, -- .idlest_idle_bit = OMAP24XX_EN_GPIOS_SHIFT, -+ .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, - }, - }, -- .slaves = omap2430_gpio1_slaves, -- .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), -- .class = &omap243x_gpio_hwmod_class, -- .dev_attr = &gpio_dev_attr, -+ .slaves = omap2430_mcbsp1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), - }; - --/* gpio2 */ --static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = { -- { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */ -+/* mcbsp2 */ -+static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = { -+ { .name = "tx", .irq = 62 }, -+ { .name = "rx", .irq = 63 }, -+ { .name = "common", .irq = 16 }, - }; - --static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { -- &omap2430_l4_wkup__gpio2, -+static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = { -+ { .name = "rx", .dma_req = 34 }, -+ { .name = "tx", .dma_req = 33 }, - }; - --static struct omap_hwmod omap2430_gpio2_hwmod = { -- .name = "gpio2", -- .mpu_irqs = omap243x_gpio2_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs), -- .main_clk = "gpios_fck", -+static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = { -+ { -+ .name = "mpu", -+ .pa_start = 0x48076000, -+ .pa_end = 0x480760ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> mcbsp2 */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_mcbsp2_hwmod, -+ .clk = "mcbsp2_ick", -+ .addr = omap2430_mcbsp2_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_mcbsp2_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mcbsp2 slave ports */ -+static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = { -+ &omap2430_l4_core__mcbsp2, -+}; -+ -+static struct omap_hwmod omap2430_mcbsp2_hwmod = { -+ .name = "mcbsp2", -+ .class = &omap2430_mcbsp_hwmod_class, -+ .mpu_irqs = omap2430_mcbsp2_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_irqs), -+ .sdma_reqs = omap2430_mcbsp2_sdma_chs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs), -+ .main_clk = "mcbsp2_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, -- .module_bit = OMAP24XX_EN_GPIOS_SHIFT, -- .module_offs = WKUP_MOD, -+ .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, -+ .module_offs = CORE_MOD, - .idlest_reg_id = 1, -- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, -+ .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, - }, - }, -- .slaves = omap2430_gpio2_slaves, -- .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), -- .class = &omap243x_gpio_hwmod_class, -- .dev_attr = &gpio_dev_attr, -+ .slaves = omap2430_mcbsp2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), - }; - --/* gpio3 */ --static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = { -- { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */ -+/* mcbsp3 */ -+static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = { -+ { .name = "tx", .irq = 89 }, -+ { .name = "rx", .irq = 90 }, -+ { .name = "common", .irq = 17 }, - }; - --static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { -- &omap2430_l4_wkup__gpio3, -+static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = { -+ { .name = "rx", .dma_req = 18 }, -+ { .name = "tx", .dma_req = 17 }, - }; - --static struct omap_hwmod omap2430_gpio3_hwmod = { -- .name = "gpio3", -- .mpu_irqs = omap243x_gpio3_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs), -- .main_clk = "gpios_fck", -+static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { -+ { -+ .name = "mpu", -+ .pa_start = 0x4808C000, -+ .pa_end = 0x4808C0ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> mcbsp3 */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_mcbsp3_hwmod, -+ .clk = "mcbsp3_ick", -+ .addr = omap2430_mcbsp3_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_mcbsp3_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mcbsp3 slave ports */ -+static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = { -+ &omap2430_l4_core__mcbsp3, -+}; -+ -+static struct omap_hwmod omap2430_mcbsp3_hwmod = { -+ .name = "mcbsp3", -+ .class = &omap2430_mcbsp_hwmod_class, -+ .mpu_irqs = omap2430_mcbsp3_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_irqs), -+ .sdma_reqs = omap2430_mcbsp3_sdma_chs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs), -+ .main_clk = "mcbsp3_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, -- .module_bit = OMAP24XX_EN_GPIOS_SHIFT, -- .module_offs = WKUP_MOD, -- .idlest_reg_id = 1, -- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, -+ .module_bit = OMAP2430_EN_MCBSP3_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 2, -+ .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, - }, - }, -- .slaves = omap2430_gpio3_slaves, -- .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), -- .class = &omap243x_gpio_hwmod_class, -- .dev_attr = &gpio_dev_attr, -+ .slaves = omap2430_mcbsp3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), - }; - --/* gpio4 */ --static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = { -- { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */ -+/* mcbsp4 */ -+static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = { -+ { .name = "tx", .irq = 54 }, -+ { .name = "rx", .irq = 55 }, -+ { .name = "common", .irq = 18 }, - }; - --static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { -- &omap2430_l4_wkup__gpio4, -+static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { -+ { .name = "rx", .dma_req = 20 }, -+ { .name = "tx", .dma_req = 19 }, - }; - --static struct omap_hwmod omap2430_gpio4_hwmod = { -- .name = "gpio4", -- .mpu_irqs = omap243x_gpio4_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs), -- .main_clk = "gpios_fck", -+static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { -+ { -+ .name = "mpu", -+ .pa_start = 0x4808E000, -+ .pa_end = 0x4808E0ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> mcbsp4 */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_mcbsp4_hwmod, -+ .clk = "mcbsp4_ick", -+ .addr = omap2430_mcbsp4_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_mcbsp4_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mcbsp4 slave ports */ -+static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = { -+ &omap2430_l4_core__mcbsp4, -+}; -+ -+static struct omap_hwmod omap2430_mcbsp4_hwmod = { -+ .name = "mcbsp4", -+ .class = &omap2430_mcbsp_hwmod_class, -+ .mpu_irqs = omap2430_mcbsp4_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_irqs), -+ .sdma_reqs = omap2430_mcbsp4_sdma_chs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs), -+ .main_clk = "mcbsp4_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, -- .module_bit = OMAP24XX_EN_GPIOS_SHIFT, -- .module_offs = WKUP_MOD, -- .idlest_reg_id = 1, -- .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, -+ .module_bit = OMAP2430_EN_MCBSP4_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 2, -+ .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, - }, - }, -- .slaves = omap2430_gpio4_slaves, -- .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), -- .class = &omap243x_gpio_hwmod_class, -- .dev_attr = &gpio_dev_attr, -+ .slaves = omap2430_mcbsp4_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), - }; - --/* gpio5 */ --static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { -- { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ -+/* mcbsp5 */ -+static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = { -+ { .name = "tx", .irq = 81 }, -+ { .name = "rx", .irq = 82 }, -+ { .name = "common", .irq = 19 }, - }; - --static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { -- &omap2430_l4_core__gpio5, -+static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { -+ { .name = "rx", .dma_req = 22 }, -+ { .name = "tx", .dma_req = 21 }, - }; - --static struct omap_hwmod omap2430_gpio5_hwmod = { -- .name = "gpio5", -- .mpu_irqs = omap243x_gpio5_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs), -- .main_clk = "gpio5_fck", -+static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { -+ { -+ .name = "mpu", -+ .pa_start = 0x48096000, -+ .pa_end = 0x480960ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> mcbsp5 */ -+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { -+ .master = &omap2430_l4_core_hwmod, -+ .slave = &omap2430_mcbsp5_hwmod, -+ .clk = "mcbsp5_ick", -+ .addr = omap2430_mcbsp5_addrs, -+ .addr_cnt = ARRAY_SIZE(omap2430_mcbsp5_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mcbsp5 slave ports */ -+static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = { -+ &omap2430_l4_core__mcbsp5, -+}; -+ -+static struct omap_hwmod omap2430_mcbsp5_hwmod = { -+ .name = "mcbsp5", -+ .class = &omap2430_mcbsp_hwmod_class, -+ .mpu_irqs = omap2430_mcbsp5_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_irqs), -+ .sdma_reqs = omap2430_mcbsp5_sdma_chs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs), -+ .main_clk = "mcbsp5_fck", - .prcm = { - .omap2 = { -- .prcm_reg_id = 2, -- .module_bit = OMAP2430_EN_GPIO5_SHIFT, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP2430_EN_MCBSP5_SHIFT, - .module_offs = CORE_MOD, - .idlest_reg_id = 2, -- .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, -+ .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, - }, - }, -- .slaves = omap2430_gpio5_slaves, -- .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), -- .class = &omap243x_gpio_hwmod_class, -- .dev_attr = &gpio_dev_attr, -+ .slaves = omap2430_mcbsp5_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), - }; - --/* dma_system */ --static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = { -- .rev_offs = 0x0000, -- .sysc_offs = 0x002c, -- .syss_offs = 0x0028, -- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | -- SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | -- SYSC_HAS_AUTOIDLE), -- .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), -- .sysc_fields = &omap_hwmod_sysc_type1, -+/* MMC/SD/SDIO common */ -+ -+static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { -+ .rev_offs = 0x1fc, -+ .sysc_offs = 0x10, -+ .syss_offs = 0x14, -+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, - }; - --static struct omap_hwmod_class omap2430_dma_hwmod_class = { -- .name = "dma", -- .sysc = &omap2430_dma_sysc, -+static struct omap_hwmod_class omap2430_mmc_class = { -+ .name = "mmc", -+ .sysc = &omap2430_mmc_sysc, - }; - --/* dma attributes */ --static struct omap_dma_dev_attr dma_dev_attr = { -- .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | -- IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, -- .lch_count = 32, -+/* MMC/SD/SDIO1 */ -+ -+static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { -+ { .irq = 83 }, - }; - --static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = { -- { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */ -- { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */ -- { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */ -- { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */ -+static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ -+ { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ - }; - --static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = { -- { -- .pa_start = 0x48056000, -- .pa_end = 0x4a0560ff, -- .flags = ADDR_TYPE_RT -+static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { -+ { .role = "dbck", .clk = "mmchsdb1_fck" }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = { -+ &omap2430_l4_core__mmc1, -+}; -+ -+static struct omap_mmc_dev_attr mmc1_dev_attr = { -+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, -+}; -+ -+static struct omap_hwmod omap2430_mmc1_hwmod = { -+ .name = "mmc1", -+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, -+ .mpu_irqs = omap2430_mmc1_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc1_mpu_irqs), -+ .sdma_reqs = omap2430_mmc1_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc1_sdma_reqs), -+ .opt_clks = omap2430_mmc1_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), -+ .main_clk = "mmchs1_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 2, -+ .module_bit = OMAP2430_EN_MMCHS1_SHIFT, -+ .idlest_reg_id = 2, -+ .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, -+ }, - }, -+ .dev_attr = &mmc1_dev_attr, -+ .slaves = omap2430_mmc1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves), -+ .class = &omap2430_mmc_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), - }; - --/* dma_system -> L3 */ --static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { -- .master = &omap2430_dma_system_hwmod, -- .slave = &omap2430_l3_main_hwmod, -- .clk = "core_l3_ck", -- .user = OCP_USER_MPU | OCP_USER_SDMA, -+/* MMC/SD/SDIO2 */ -+ -+static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { -+ { .irq = 86 }, - }; - --/* dma_system master ports */ --static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = { -- &omap2430_dma_system__l3, -+static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ -+ { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ - }; - --/* l4_core -> dma_system */ --static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = { -- .master = &omap2430_l4_core_hwmod, -- .slave = &omap2430_dma_system_hwmod, -- .clk = "sdma_ick", -- .addr = omap2430_dma_system_addrs, -- .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs), -- .user = OCP_USER_MPU | OCP_USER_SDMA, -+static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { -+ { .role = "dbck", .clk = "mmchsdb2_fck" }, - }; - --/* dma_system slave ports */ --static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = { -- &omap2430_l4_core__dma_system, -+static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = { -+ &omap2430_l4_core__mmc2, - }; - --static struct omap_hwmod omap2430_dma_system_hwmod = { -- .name = "dma", -- .class = &omap2430_dma_hwmod_class, -- .mpu_irqs = omap2430_dma_system_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs), -- .main_clk = "core_l3_ck", -- .slaves = omap2430_dma_system_slaves, -- .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), -- .masters = omap2430_dma_system_masters, -- .masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters), -- .dev_attr = &dma_dev_attr, -+static struct omap_hwmod omap2430_mmc2_hwmod = { -+ .name = "mmc2", -+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, -+ .mpu_irqs = omap2430_mmc2_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc2_mpu_irqs), -+ .sdma_reqs = omap2430_mmc2_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc2_sdma_reqs), -+ .opt_clks = omap2430_mmc2_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), -+ .main_clk = "mmchs2_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 2, -+ .module_bit = OMAP2430_EN_MMCHS2_SHIFT, -+ .idlest_reg_id = 2, -+ .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, -+ }, -+ }, -+ .slaves = omap2430_mmc2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves), -+ .class = &omap2430_mmc_class, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), -- .flags = HWMOD_NO_IDLEST, - }; - - static __initdata struct omap_hwmod *omap2430_hwmods[] = { -@@ -925,12 +2667,34 @@ - &omap2430_l4_wkup_hwmod, - &omap2430_mpu_hwmod, - &omap2430_iva_hwmod, -+ -+ &omap2430_timer1_hwmod, -+ &omap2430_timer2_hwmod, -+ &omap2430_timer3_hwmod, -+ &omap2430_timer4_hwmod, -+ &omap2430_timer5_hwmod, -+ &omap2430_timer6_hwmod, -+ &omap2430_timer7_hwmod, -+ &omap2430_timer8_hwmod, -+ &omap2430_timer9_hwmod, -+ &omap2430_timer10_hwmod, -+ &omap2430_timer11_hwmod, -+ &omap2430_timer12_hwmod, -+ - &omap2430_wd_timer2_hwmod, - &omap2430_uart1_hwmod, - &omap2430_uart2_hwmod, - &omap2430_uart3_hwmod, -+ /* dss class */ -+ &omap2430_dss_core_hwmod, -+ &omap2430_dss_dispc_hwmod, -+ &omap2430_dss_rfbi_hwmod, -+ &omap2430_dss_venc_hwmod, -+ /* i2c class */ - &omap2430_i2c1_hwmod, - &omap2430_i2c2_hwmod, -+ &omap2430_mmc1_hwmod, -+ &omap2430_mmc2_hwmod, - - /* gpio class */ - &omap2430_gpio1_hwmod, -@@ -941,10 +2705,29 @@ - - /* dma_system class*/ - &omap2430_dma_system_hwmod, -+ -+ /* mcbsp class */ -+ &omap2430_mcbsp1_hwmod, -+ &omap2430_mcbsp2_hwmod, -+ &omap2430_mcbsp3_hwmod, -+ &omap2430_mcbsp4_hwmod, -+ &omap2430_mcbsp5_hwmod, -+ -+ /* mailbox class */ -+ &omap2430_mailbox_hwmod, -+ -+ /* mcspi class */ -+ &omap2430_mcspi1_hwmod, -+ &omap2430_mcspi2_hwmod, -+ &omap2430_mcspi3_hwmod, -+ -+ /* usbotg class*/ -+ &omap2430_usbhsotg_hwmod, -+ - NULL, - }; - - int __init omap2430_hwmod_init(void) - { -- return omap_hwmod_init(omap2430_hwmods); -+ return omap_hwmod_register(omap2430_hwmods); - } -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c 2011-03-09 13:19:09.829507237 +0100 -@@ -18,16 +18,22 @@ - #include - #include - #include -+#include - #include - #include - #include -+#include - #include -+#include -+#include -+#include - - #include "omap_hwmod_common_data.h" - - #include "prm-regbits-34xx.h" - #include "cm-regbits-34xx.h" - #include "wd_timer.h" -+#include - - /* - * OMAP3xxx hardware module integration data -@@ -44,6 +50,12 @@ - static struct omap_hwmod omap3xxx_l4_core_hwmod; - static struct omap_hwmod omap3xxx_l4_per_hwmod; - static struct omap_hwmod omap3xxx_wd_timer2_hwmod; -+static struct omap_hwmod omap3430es1_dss_core_hwmod; -+static struct omap_hwmod omap3xxx_dss_core_hwmod; -+static struct omap_hwmod omap3xxx_dss_dispc_hwmod; -+static struct omap_hwmod omap3xxx_dss_dsi1_hwmod; -+static struct omap_hwmod omap3xxx_dss_rfbi_hwmod; -+static struct omap_hwmod omap3xxx_dss_venc_hwmod; - static struct omap_hwmod omap3xxx_i2c1_hwmod; - static struct omap_hwmod omap3xxx_i2c2_hwmod; - static struct omap_hwmod omap3xxx_i2c3_hwmod; -@@ -55,9 +67,25 @@ - static struct omap_hwmod omap3xxx_gpio6_hwmod; - static struct omap_hwmod omap34xx_sr1_hwmod; - static struct omap_hwmod omap34xx_sr2_hwmod; -+static struct omap_hwmod omap34xx_mcspi1; -+static struct omap_hwmod omap34xx_mcspi2; -+static struct omap_hwmod omap34xx_mcspi3; -+static struct omap_hwmod omap34xx_mcspi4; -+static struct omap_hwmod omap3xxx_mmc1_hwmod; -+static struct omap_hwmod omap3xxx_mmc2_hwmod; -+static struct omap_hwmod omap3xxx_mmc3_hwmod; -+static struct omap_hwmod am35xx_usbhsotg_hwmod; - - static struct omap_hwmod omap3xxx_dma_system_hwmod; - -+static struct omap_hwmod omap3xxx_mcbsp1_hwmod; -+static struct omap_hwmod omap3xxx_mcbsp2_hwmod; -+static struct omap_hwmod omap3xxx_mcbsp3_hwmod; -+static struct omap_hwmod omap3xxx_mcbsp4_hwmod; -+static struct omap_hwmod omap3xxx_mcbsp5_hwmod; -+static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod; -+static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod; -+ - /* L3 -> L4_CORE interface */ - static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { - .master = &omap3xxx_l3_main_hwmod, -@@ -84,6 +112,19 @@ - &omap3xxx_mpu__l3_main, - }; - -+/* DSS -> l3 */ -+static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = { -+ .master = &omap3xxx_dss_core_hwmod, -+ .slave = &omap3xxx_l3_main_hwmod, -+ .fw = { -+ .omap2 = { -+ .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS, -+ .flags = OMAP_FIREWALL_L3, -+ } -+ }, -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ - /* Master interfaces on the L3 interconnect */ - static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = { - &omap3xxx_l3_main__l4_core, -@@ -107,7 +148,23 @@ - static struct omap_hwmod omap3xxx_uart2_hwmod; - static struct omap_hwmod omap3xxx_uart3_hwmod; - static struct omap_hwmod omap3xxx_uart4_hwmod; -+static struct omap_hwmod omap3xxx_usbhsotg_hwmod; -+ -+/* l3_core -> usbhsotg interface */ -+static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { -+ .master = &omap3xxx_usbhsotg_hwmod, -+ .slave = &omap3xxx_l3_main_hwmod, -+ .clk = "core_l3_ick", -+ .user = OCP_USER_MPU, -+}; - -+/* l3_core -> am35xx_usbhsotg interface */ -+static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { -+ .master = &am35xx_usbhsotg_hwmod, -+ .slave = &omap3xxx_l3_main_hwmod, -+ .clk = "core_l3_ick", -+ .user = OCP_USER_MPU, -+}; - /* L4_CORE -> L4_WKUP interface */ - static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { - .master = &omap3xxx_l4_core_hwmod, -@@ -115,6 +172,63 @@ - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - -+/* L4 CORE -> MMC1 interface */ -+static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = { -+ { -+ .pa_start = 0x4809c000, -+ .pa_end = 0x4809c1ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap3xxx_mmc1_hwmod, -+ .clk = "mmchs1_ick", -+ .addr = omap3xxx_mmc1_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_mmc1_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+ .flags = OMAP_FIREWALL_L4 -+}; -+ -+/* L4 CORE -> MMC2 interface */ -+static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = { -+ { -+ .pa_start = 0x480b4000, -+ .pa_end = 0x480b41ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap3xxx_mmc2_hwmod, -+ .clk = "mmchs2_ick", -+ .addr = omap3xxx_mmc2_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_mmc2_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+ .flags = OMAP_FIREWALL_L4 -+}; -+ -+/* L4 CORE -> MMC3 interface */ -+static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = { -+ { -+ .pa_start = 0x480ad000, -+ .pa_end = 0x480ad1ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap3xxx_mmc3_hwmod, -+ .clk = "mmchs3_ick", -+ .addr = omap3xxx_mmc3_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_mmc3_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+ .flags = OMAP_FIREWALL_L4 -+}; -+ - /* L4 CORE -> UART1 interface */ - static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { - { -@@ -301,6 +415,61 @@ - .user = OCP_USER_MPU, - }; - -+/* -+* usbhsotg interface data -+*/ -+ -+static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = { -+ { -+ .pa_start = OMAP34XX_HSUSB_OTG_BASE, -+ .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> usbhsotg */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap3xxx_usbhsotg_hwmod, -+ .clk = "l4_ick", -+ .addr = omap3xxx_usbhsotg_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs), -+ .user = OCP_USER_MPU, -+}; -+ -+static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = { -+ &omap3xxx_usbhsotg__l3, -+}; -+ -+static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = { -+ &omap3xxx_l4_core__usbhsotg, -+}; -+ -+static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { -+ { -+ .pa_start = AM35XX_IPSS_USBOTGSS_BASE, -+ .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> usbhsotg */ -+static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &am35xx_usbhsotg_hwmod, -+ .clk = "l4_ick", -+ .addr = am35xx_usbhsotg_addrs, -+ .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs), -+ .user = OCP_USER_MPU, -+}; -+ -+static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = { -+ &am35xx_usbhsotg__l3, -+}; -+ -+static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = { -+ &am35xx_l4_core__usbhsotg, -+}; - /* Slave interfaces on the L4_CORE interconnect */ - static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { - &omap3xxx_l3_main__l4_core, -@@ -417,251 +586,1292 @@ - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }; - --/* l4_wkup -> wd_timer2 */ --static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { -- { -- .pa_start = 0x48314000, -- .pa_end = 0x4831407f, -- .flags = ADDR_TYPE_RT -- }, -+/* timer class */ -+static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, - }; - --static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { -- .master = &omap3xxx_l4_wkup_hwmod, -- .slave = &omap3xxx_wd_timer2_hwmod, -- .clk = "wdt2_ick", -- .addr = omap3xxx_wd_timer2_addrs, -- .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs), -- .user = OCP_USER_MPU | OCP_USER_SDMA, -+static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = { -+ .name = "timer", -+ .sysc = &omap3xxx_timer_1ms_sysc, -+ .rev = OMAP_TIMER_IP_VERSION_1, - }; - --/* -- * 'wd_timer' class -- * 32-bit watchdog upward counter that generates a pulse on the reset pin on -- * overflow condition -- */ -- --static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { -+static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { - .rev_offs = 0x0000, - .sysc_offs = 0x0010, - .syss_offs = 0x0014, -- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | -- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -- SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY), -+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | -+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), - .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -- .sysc_fields = &omap_hwmod_sysc_type1, -+ .sysc_fields = &omap_hwmod_sysc_type1, - }; - --/* I2C common */ --static struct omap_hwmod_class_sysconfig i2c_sysc = { -- .rev_offs = 0x00, -- .sysc_offs = 0x20, -- .syss_offs = 0x10, -- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | -- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -- SYSC_HAS_AUTOIDLE), -- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -- .sysc_fields = &omap_hwmod_sysc_type1, -+static struct omap_hwmod_class omap3xxx_timer_hwmod_class = { -+ .name = "timer", -+ .sysc = &omap3xxx_timer_sysc, -+ .rev = OMAP_TIMER_IP_VERSION_1, - }; - --static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { -- .name = "wd_timer", -- .sysc = &omap3xxx_wd_timer_sysc, -- .pre_shutdown = &omap2_wd_timer_disable -+/* timer1 */ -+static struct omap_hwmod omap3xxx_timer1_hwmod; -+static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = { -+ { .irq = 37, }, - }; - --/* wd_timer2 */ --static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { -- &omap3xxx_l4_wkup__wd_timer2, -+static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { -+ { -+ .pa_start = 0x48318000, -+ .pa_end = 0x48318000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { -- .name = "wd_timer2", -- .class = &omap3xxx_wd_timer_hwmod_class, -- .main_clk = "wdt2_fck", -+/* l4_wkup -> timer1 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = { -+ .master = &omap3xxx_l4_wkup_hwmod, -+ .slave = &omap3xxx_timer1_hwmod, -+ .clk = "gpt1_ick", -+ .addr = omap3xxx_timer1_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer1 slave port */ -+static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = { -+ &omap3xxx_l4_wkup__timer1, -+}; -+ -+/* timer1 hwmod */ -+static struct omap_hwmod omap3xxx_timer1_hwmod = { -+ .name = "timer1", -+ .mpu_irqs = omap3xxx_timer1_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs), -+ .main_clk = "gpt1_fck", - .prcm = { - .omap2 = { - .prcm_reg_id = 1, -- .module_bit = OMAP3430_EN_WDT2_SHIFT, -+ .module_bit = OMAP3430_EN_GPT1_SHIFT, - .module_offs = WKUP_MOD, - .idlest_reg_id = 1, -- .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, -+ .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT, - }, - }, -- .slaves = omap3xxx_wd_timer2_slaves, -- .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), -- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), --}; -- --/* UART common */ -- --static struct omap_hwmod_class_sysconfig uart_sysc = { -- .rev_offs = 0x50, -- .sysc_offs = 0x54, -- .syss_offs = 0x58, -- .sysc_flags = (SYSC_HAS_SIDLEMODE | -- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -- SYSC_HAS_AUTOIDLE), -- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -- .sysc_fields = &omap_hwmod_sysc_type1, -+ .slaves = omap3xxx_timer1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves), -+ .class = &omap3xxx_timer_1ms_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }; - --static struct omap_hwmod_class uart_class = { -- .name = "uart", -- .sysc = &uart_sysc, -+/* timer2 */ -+static struct omap_hwmod omap3xxx_timer2_hwmod; -+static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = { -+ { .irq = 38, }, - }; - --/* UART1 */ -- --static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { -- { .irq = INT_24XX_UART1_IRQ, }, -+static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { -+ { -+ .pa_start = 0x49032000, -+ .pa_end = 0x49032000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { -- { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, -- { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, -+/* l4_per -> timer2 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = { -+ .master = &omap3xxx_l4_per_hwmod, -+ .slave = &omap3xxx_timer2_hwmod, -+ .clk = "gpt2_ick", -+ .addr = omap3xxx_timer2_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { -- &omap3_l4_core__uart1, -+/* timer2 slave port */ -+static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = { -+ &omap3xxx_l4_per__timer2, - }; - --static struct omap_hwmod omap3xxx_uart1_hwmod = { -- .name = "uart1", -- .mpu_irqs = uart1_mpu_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), -- .sdma_reqs = uart1_sdma_reqs, -- .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), -- .main_clk = "uart1_fck", -+/* timer2 hwmod */ -+static struct omap_hwmod omap3xxx_timer2_hwmod = { -+ .name = "timer2", -+ .mpu_irqs = omap3xxx_timer2_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs), -+ .main_clk = "gpt2_fck", - .prcm = { - .omap2 = { -- .module_offs = CORE_MOD, - .prcm_reg_id = 1, -- .module_bit = OMAP3430_EN_UART1_SHIFT, -+ .module_bit = OMAP3430_EN_GPT2_SHIFT, -+ .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, -- .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, -+ .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, - }, - }, -- .slaves = omap3xxx_uart1_slaves, -- .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), -- .class = &uart_class, -- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+ .slaves = omap3xxx_timer2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves), -+ .class = &omap3xxx_timer_1ms_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }; - --/* UART2 */ -+/* timer3 */ -+static struct omap_hwmod omap3xxx_timer3_hwmod; -+static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = { -+ { .irq = 39, }, -+}; - --static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { -- { .irq = INT_24XX_UART2_IRQ, }, -+static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { -+ { -+ .pa_start = 0x49034000, -+ .pa_end = 0x49034000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { -- { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, -- { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, -+/* l4_per -> timer3 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = { -+ .master = &omap3xxx_l4_per_hwmod, -+ .slave = &omap3xxx_timer3_hwmod, -+ .clk = "gpt3_ick", -+ .addr = omap3xxx_timer3_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { -- &omap3_l4_core__uart2, -+/* timer3 slave port */ -+static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = { -+ &omap3xxx_l4_per__timer3, - }; - --static struct omap_hwmod omap3xxx_uart2_hwmod = { -- .name = "uart2", -- .mpu_irqs = uart2_mpu_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), -- .sdma_reqs = uart2_sdma_reqs, -- .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), -- .main_clk = "uart2_fck", -+/* timer3 hwmod */ -+static struct omap_hwmod omap3xxx_timer3_hwmod = { -+ .name = "timer3", -+ .mpu_irqs = omap3xxx_timer3_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs), -+ .main_clk = "gpt3_fck", - .prcm = { - .omap2 = { -- .module_offs = CORE_MOD, - .prcm_reg_id = 1, -- .module_bit = OMAP3430_EN_UART2_SHIFT, -+ .module_bit = OMAP3430_EN_GPT3_SHIFT, -+ .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, -- .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, -+ .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT, - }, - }, -- .slaves = omap3xxx_uart2_slaves, -- .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), -- .class = &uart_class, -- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+ .slaves = omap3xxx_timer3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves), -+ .class = &omap3xxx_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }; - --/* UART3 */ -+/* timer4 */ -+static struct omap_hwmod omap3xxx_timer4_hwmod; -+static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = { -+ { .irq = 40, }, -+}; - --static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { -- { .irq = INT_24XX_UART3_IRQ, }, -+static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { -+ { -+ .pa_start = 0x49036000, -+ .pa_end = 0x49036000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { -- { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, -- { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, -+/* l4_per -> timer4 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = { -+ .master = &omap3xxx_l4_per_hwmod, -+ .slave = &omap3xxx_timer4_hwmod, -+ .clk = "gpt4_ick", -+ .addr = omap3xxx_timer4_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { -- &omap3_l4_per__uart3, -+/* timer4 slave port */ -+static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = { -+ &omap3xxx_l4_per__timer4, - }; - --static struct omap_hwmod omap3xxx_uart3_hwmod = { -- .name = "uart3", -- .mpu_irqs = uart3_mpu_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), -- .sdma_reqs = uart3_sdma_reqs, -- .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), -- .main_clk = "uart3_fck", -+/* timer4 hwmod */ -+static struct omap_hwmod omap3xxx_timer4_hwmod = { -+ .name = "timer4", -+ .mpu_irqs = omap3xxx_timer4_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs), -+ .main_clk = "gpt4_fck", - .prcm = { - .omap2 = { -- .module_offs = OMAP3430_PER_MOD, - .prcm_reg_id = 1, -- .module_bit = OMAP3430_EN_UART3_SHIFT, -+ .module_bit = OMAP3430_EN_GPT4_SHIFT, -+ .module_offs = OMAP3430_PER_MOD, - .idlest_reg_id = 1, -- .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, -+ .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT, - }, - }, -- .slaves = omap3xxx_uart3_slaves, -- .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), -- .class = &uart_class, -- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+ .slaves = omap3xxx_timer4_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves), -+ .class = &omap3xxx_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) - }; - --/* UART4 */ -+/* timer5 */ -+static struct omap_hwmod omap3xxx_timer5_hwmod; -+static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = { -+ { .irq = 41, }, -+}; - --static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { -- { .irq = INT_36XX_UART4_IRQ, }, -+static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { -+ { -+ .pa_start = 0x49038000, -+ .pa_end = 0x49038000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { -- { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, -+/* l4_per -> timer5 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = { -+ .master = &omap3xxx_l4_per_hwmod, -+ .slave = &omap3xxx_timer5_hwmod, -+ .clk = "gpt5_ick", -+ .addr = omap3xxx_timer5_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer5 slave port */ -+static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = { -+ &omap3xxx_l4_per__timer5, -+}; -+ -+/* timer5 hwmod */ -+static struct omap_hwmod omap3xxx_timer5_hwmod = { -+ .name = "timer5", -+ .mpu_irqs = omap3xxx_timer5_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs), -+ .main_clk = "gpt5_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_GPT5_SHIFT, -+ .module_offs = OMAP3430_PER_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_timer5_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves), -+ .class = &omap3xxx_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) -+}; -+ -+/* timer6 */ -+static struct omap_hwmod omap3xxx_timer6_hwmod; -+static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = { -+ { .irq = 42, }, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { -+ { -+ .pa_start = 0x4903A000, -+ .pa_end = 0x4903A000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> timer6 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = { -+ .master = &omap3xxx_l4_per_hwmod, -+ .slave = &omap3xxx_timer6_hwmod, -+ .clk = "gpt6_ick", -+ .addr = omap3xxx_timer6_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer6 slave port */ -+static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = { -+ &omap3xxx_l4_per__timer6, -+}; -+ -+/* timer6 hwmod */ -+static struct omap_hwmod omap3xxx_timer6_hwmod = { -+ .name = "timer6", -+ .mpu_irqs = omap3xxx_timer6_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs), -+ .main_clk = "gpt6_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_GPT6_SHIFT, -+ .module_offs = OMAP3430_PER_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_timer6_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves), -+ .class = &omap3xxx_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) -+}; -+ -+/* timer7 */ -+static struct omap_hwmod omap3xxx_timer7_hwmod; -+static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = { -+ { .irq = 43, }, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { -+ { -+ .pa_start = 0x4903C000, -+ .pa_end = 0x4903C000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> timer7 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = { -+ .master = &omap3xxx_l4_per_hwmod, -+ .slave = &omap3xxx_timer7_hwmod, -+ .clk = "gpt7_ick", -+ .addr = omap3xxx_timer7_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer7 slave port */ -+static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = { -+ &omap3xxx_l4_per__timer7, -+}; -+ -+/* timer7 hwmod */ -+static struct omap_hwmod omap3xxx_timer7_hwmod = { -+ .name = "timer7", -+ .mpu_irqs = omap3xxx_timer7_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs), -+ .main_clk = "gpt7_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_GPT7_SHIFT, -+ .module_offs = OMAP3430_PER_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_timer7_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves), -+ .class = &omap3xxx_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) -+}; -+ -+/* timer8 */ -+static struct omap_hwmod omap3xxx_timer8_hwmod; -+static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = { -+ { .irq = 44, }, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { -+ { -+ .pa_start = 0x4903E000, -+ .pa_end = 0x4903E000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> timer8 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = { -+ .master = &omap3xxx_l4_per_hwmod, -+ .slave = &omap3xxx_timer8_hwmod, -+ .clk = "gpt8_ick", -+ .addr = omap3xxx_timer8_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer8 slave port */ -+static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = { -+ &omap3xxx_l4_per__timer8, -+}; -+ -+/* timer8 hwmod */ -+static struct omap_hwmod omap3xxx_timer8_hwmod = { -+ .name = "timer8", -+ .mpu_irqs = omap3xxx_timer8_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs), -+ .main_clk = "gpt8_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_GPT8_SHIFT, -+ .module_offs = OMAP3430_PER_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_timer8_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves), -+ .class = &omap3xxx_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) -+}; -+ -+/* timer9 */ -+static struct omap_hwmod omap3xxx_timer9_hwmod; -+static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = { -+ { .irq = 45, }, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { -+ { -+ .pa_start = 0x49040000, -+ .pa_end = 0x49040000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> timer9 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = { -+ .master = &omap3xxx_l4_per_hwmod, -+ .slave = &omap3xxx_timer9_hwmod, -+ .clk = "gpt9_ick", -+ .addr = omap3xxx_timer9_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer9 slave port */ -+static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = { -+ &omap3xxx_l4_per__timer9, -+}; -+ -+/* timer9 hwmod */ -+static struct omap_hwmod omap3xxx_timer9_hwmod = { -+ .name = "timer9", -+ .mpu_irqs = omap3xxx_timer9_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs), -+ .main_clk = "gpt9_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_GPT9_SHIFT, -+ .module_offs = OMAP3430_PER_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_timer9_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves), -+ .class = &omap3xxx_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) -+}; -+ -+/* timer10 */ -+static struct omap_hwmod omap3xxx_timer10_hwmod; -+static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = { -+ { .irq = 46, }, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = { -+ { -+ .pa_start = 0x48086000, -+ .pa_end = 0x48086000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> timer10 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap3xxx_timer10_hwmod, -+ .clk = "gpt10_ick", -+ .addr = omap3xxx_timer10_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer10 slave port */ -+static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = { -+ &omap3xxx_l4_core__timer10, -+}; -+ -+/* timer10 hwmod */ -+static struct omap_hwmod omap3xxx_timer10_hwmod = { -+ .name = "timer10", -+ .mpu_irqs = omap3xxx_timer10_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs), -+ .main_clk = "gpt10_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_GPT10_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_timer10_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves), -+ .class = &omap3xxx_timer_1ms_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) -+}; -+ -+/* timer11 */ -+static struct omap_hwmod omap3xxx_timer11_hwmod; -+static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = { -+ { .irq = 47, }, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = { -+ { -+ .pa_start = 0x48088000, -+ .pa_end = 0x48088000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> timer11 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap3xxx_timer11_hwmod, -+ .clk = "gpt11_ick", -+ .addr = omap3xxx_timer11_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer11 slave port */ -+static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = { -+ &omap3xxx_l4_core__timer11, -+}; -+ -+/* timer11 hwmod */ -+static struct omap_hwmod omap3xxx_timer11_hwmod = { -+ .name = "timer11", -+ .mpu_irqs = omap3xxx_timer11_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs), -+ .main_clk = "gpt11_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_GPT11_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_timer11_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves), -+ .class = &omap3xxx_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) -+}; -+ -+/* timer12*/ -+static struct omap_hwmod omap3xxx_timer12_hwmod; -+static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { -+ { .irq = 95, }, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { -+ { -+ .pa_start = 0x48304000, -+ .pa_end = 0x48304000 + SZ_1K - 1, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> timer12 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap3xxx_timer12_hwmod, -+ .clk = "gpt12_ick", -+ .addr = omap3xxx_timer12_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* timer12 slave port */ -+static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = { -+ &omap3xxx_l4_core__timer12, -+}; -+ -+/* timer12 hwmod */ -+static struct omap_hwmod omap3xxx_timer12_hwmod = { -+ .name = "timer12", -+ .mpu_irqs = omap3xxx_timer12_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs), -+ .main_clk = "gpt12_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_GPT12_SHIFT, -+ .module_offs = WKUP_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_timer12_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves), -+ .class = &omap3xxx_timer_hwmod_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) -+}; -+ -+/* l4_wkup -> wd_timer2 */ -+static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = { -+ { -+ .pa_start = 0x48314000, -+ .pa_end = 0x4831407f, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { -+ .master = &omap3xxx_l4_wkup_hwmod, -+ .slave = &omap3xxx_wd_timer2_hwmod, -+ .clk = "wdt2_ick", -+ .addr = omap3xxx_wd_timer2_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* -+ * 'wd_timer' class -+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on -+ * overflow condition -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE | -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+/* I2C common */ -+static struct omap_hwmod_class_sysconfig i2c_sysc = { -+ .rev_offs = 0x00, -+ .sysc_offs = 0x20, -+ .syss_offs = 0x10, -+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { -+ .name = "wd_timer", -+ .sysc = &omap3xxx_wd_timer_sysc, -+ .pre_shutdown = &omap2_wd_timer_disable -+}; -+ -+/* wd_timer2 */ -+static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = { -+ &omap3xxx_l4_wkup__wd_timer2, -+}; -+ -+static struct omap_hwmod omap3xxx_wd_timer2_hwmod = { -+ .name = "wd_timer2", -+ .class = &omap3xxx_wd_timer_hwmod_class, -+ .main_clk = "wdt2_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_WDT2_SHIFT, -+ .module_offs = WKUP_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_wd_timer2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ -+/* UART common */ -+ -+static struct omap_hwmod_class_sysconfig uart_sysc = { -+ .rev_offs = 0x50, -+ .sysc_offs = 0x54, -+ .syss_offs = 0x58, -+ .sysc_flags = (SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class uart_class = { -+ .name = "uart", -+ .sysc = &uart_sysc, -+}; -+ -+/* UART1 */ -+ -+static struct omap_hwmod_irq_info uart1_mpu_irqs[] = { -+ { .irq = INT_24XX_UART1_IRQ, }, -+}; -+ -+static struct omap_hwmod_dma_info uart1_sdma_reqs[] = { -+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, }, -+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { -+ &omap3_l4_core__uart1, -+}; -+ -+static struct omap_hwmod omap3xxx_uart1_hwmod = { -+ .name = "uart1", -+ .mpu_irqs = uart1_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), -+ .sdma_reqs = uart1_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs), -+ .main_clk = "uart1_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_UART1_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_uart1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), -+ .class = &uart_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ -+/* UART2 */ -+ -+static struct omap_hwmod_irq_info uart2_mpu_irqs[] = { -+ { .irq = INT_24XX_UART2_IRQ, }, -+}; -+ -+static struct omap_hwmod_dma_info uart2_sdma_reqs[] = { -+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, }, -+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { -+ &omap3_l4_core__uart2, -+}; -+ -+static struct omap_hwmod omap3xxx_uart2_hwmod = { -+ .name = "uart2", -+ .mpu_irqs = uart2_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), -+ .sdma_reqs = uart2_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs), -+ .main_clk = "uart2_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_UART2_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_uart2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), -+ .class = &uart_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ -+/* UART3 */ -+ -+static struct omap_hwmod_irq_info uart3_mpu_irqs[] = { -+ { .irq = INT_24XX_UART3_IRQ, }, -+}; -+ -+static struct omap_hwmod_dma_info uart3_sdma_reqs[] = { -+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, }, -+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { -+ &omap3_l4_per__uart3, -+}; -+ -+static struct omap_hwmod omap3xxx_uart3_hwmod = { -+ .name = "uart3", -+ .mpu_irqs = uart3_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), -+ .sdma_reqs = uart3_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs), -+ .main_clk = "uart3_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = OMAP3430_PER_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_UART3_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_uart3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), -+ .class = &uart_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ -+/* UART4 */ -+ -+static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { -+ { .irq = INT_36XX_UART4_IRQ, }, -+}; -+ -+static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { -+ { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, - { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, - }; - --static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { -- &omap3_l4_per__uart4, -+static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { -+ &omap3_l4_per__uart4, -+}; -+ -+static struct omap_hwmod omap3xxx_uart4_hwmod = { -+ .name = "uart4", -+ .mpu_irqs = uart4_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs), -+ .sdma_reqs = uart4_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs), -+ .main_clk = "uart4_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = OMAP3430_PER_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3630_EN_UART4_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_uart4_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), -+ .class = &uart_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), -+}; -+ -+static struct omap_hwmod_class i2c_class = { -+ .name = "i2c", -+ .sysc = &i2c_sysc, -+}; -+ -+/* -+ * 'dss' class -+ * display sub-system -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap3xxx_dss_hwmod_class = { -+ .name = "dss", -+ .sysc = &omap3xxx_dss_sysc, -+}; -+ -+static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { -+ { .name = "dispc", .dma_req = 5 }, -+ { .name = "dsi1", .dma_req = 74 }, -+}; -+ -+/* dss */ -+/* dss master ports */ -+static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = { -+ &omap3xxx_dss__l3, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = { -+ { -+ .pa_start = 0x48050000, -+ .pa_end = 0x480503FF, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> dss */ -+static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap3430es1_dss_core_hwmod, -+ .clk = "dss_ick", -+ .addr = omap3xxx_dss_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs), -+ .fw = { -+ .omap2 = { -+ .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, -+ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, -+ .flags = OMAP_FIREWALL_L4, -+ } -+ }, -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap3xxx_dss_core_hwmod, -+ .clk = "dss_ick", -+ .addr = omap3xxx_dss_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs), -+ .fw = { -+ .omap2 = { -+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, -+ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, -+ .flags = OMAP_FIREWALL_L4, -+ } -+ }, -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* dss slave ports */ -+static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = { -+ &omap3430es1_l4_core__dss, -+}; -+ -+static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = { -+ &omap3xxx_l4_core__dss, -+}; -+ -+static struct omap_hwmod_opt_clk dss_opt_clks[] = { -+ { .role = "tv_clk", .clk = "dss_tv_fck" }, -+ { .role = "video_clk", .clk = "dss_96m_fck" }, -+ { .role = "sys_clk", .clk = "dss2_alwon_fck" }, -+}; -+ -+static struct omap_hwmod omap3430es1_dss_core_hwmod = { -+ .name = "dss_core", -+ .class = &omap3xxx_dss_hwmod_class, -+ .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ -+ .sdma_reqs = omap3xxx_dss_sdma_chs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs), -+ -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_DSS1_SHIFT, -+ .module_offs = OMAP3430_DSS_MOD, -+ .idlest_reg_id = 1, -+ .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT, -+ }, -+ }, -+ .opt_clks = dss_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), -+ .slaves = omap3430es1_dss_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves), -+ .masters = omap3xxx_dss_masters, -+ .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), -+ .flags = HWMOD_NO_IDLEST, -+}; -+ -+static struct omap_hwmod omap3xxx_dss_core_hwmod = { -+ .name = "dss_core", -+ .class = &omap3xxx_dss_hwmod_class, -+ .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ -+ .sdma_reqs = omap3xxx_dss_sdma_chs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs), -+ -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_DSS1_SHIFT, -+ .module_offs = OMAP3430_DSS_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT, -+ .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT, -+ }, -+ }, -+ .opt_clks = dss_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), -+ .slaves = omap3xxx_dss_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves), -+ .masters = omap3xxx_dss_masters, -+ .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 | -+ CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1), -+}; -+ -+/* -+ * 'dispc' class -+ * display controller -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | -+ SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP | -+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = { -+ .name = "dispc", -+ .sysc = &omap3xxx_dispc_sysc, -+}; -+ -+static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = { -+ { .irq = 25 }, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = { -+ { -+ .pa_start = 0x48050400, -+ .pa_end = 0x480507FF, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> dss_dispc */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap3xxx_dss_dispc_hwmod, -+ .clk = "dss_ick", -+ .addr = omap3xxx_dss_dispc_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs), -+ .fw = { -+ .omap2 = { -+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, -+ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, -+ .flags = OMAP_FIREWALL_L4, -+ } -+ }, -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* dss_dispc slave ports */ -+static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = { -+ &omap3xxx_l4_core__dss_dispc, -+}; -+ -+static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { -+ .name = "dss_dispc", -+ .class = &omap3xxx_dispc_hwmod_class, -+ .mpu_irqs = omap3xxx_dispc_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dispc_irqs), -+ .main_clk = "dss1_alwon_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_DSS1_SHIFT, -+ .module_offs = OMAP3430_DSS_MOD, -+ }, -+ }, -+ .slaves = omap3xxx_dss_dispc_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | -+ CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | -+ CHIP_GE_OMAP3630ES1_1), -+ .flags = HWMOD_NO_IDLEST, -+}; -+ -+/* -+ * 'dsi' class -+ * display serial interface controller -+ */ -+ -+static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = { -+ .name = "dsi", -+}; -+ -+static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { -+ { .irq = 25 }, -+}; -+ -+/* dss_dsi1 */ -+static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = { -+ { -+ .pa_start = 0x4804FC00, -+ .pa_end = 0x4804FFFF, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> dss_dsi1 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap3xxx_dss_dsi1_hwmod, -+ .addr = omap3xxx_dss_dsi1_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs), -+ .fw = { -+ .omap2 = { -+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, -+ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, -+ .flags = OMAP_FIREWALL_L4, -+ } -+ }, -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* dss_dsi1 slave ports */ -+static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = { -+ &omap3xxx_l4_core__dss_dsi1, -+}; -+ -+static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = { -+ .name = "dss_dsi1", -+ .class = &omap3xxx_dsi_hwmod_class, -+ .mpu_irqs = omap3xxx_dsi1_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dsi1_irqs), -+ .main_clk = "dss1_alwon_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_DSS1_SHIFT, -+ .module_offs = OMAP3430_DSS_MOD, -+ }, -+ }, -+ .slaves = omap3xxx_dss_dsi1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | -+ CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | -+ CHIP_GE_OMAP3630ES1_1), -+ .flags = HWMOD_NO_IDLEST, -+}; -+ -+/* -+ * 'rfbi' class -+ * remote frame buffer interface -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = { -+ .name = "rfbi", -+ .sysc = &omap3xxx_rfbi_sysc, - }; - --static struct omap_hwmod omap3xxx_uart4_hwmod = { -- .name = "uart4", -- .mpu_irqs = uart4_mpu_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs), -- .sdma_reqs = uart4_sdma_reqs, -- .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs), -- .main_clk = "uart4_fck", -+static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = { -+ { -+ .pa_start = 0x48050800, -+ .pa_end = 0x48050BFF, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> dss_rfbi */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap3xxx_dss_rfbi_hwmod, -+ .clk = "dss_ick", -+ .addr = omap3xxx_dss_rfbi_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs), -+ .fw = { -+ .omap2 = { -+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, -+ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP , -+ .flags = OMAP_FIREWALL_L4, -+ } -+ }, -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* dss_rfbi slave ports */ -+static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = { -+ &omap3xxx_l4_core__dss_rfbi, -+}; -+ -+static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { -+ .name = "dss_rfbi", -+ .class = &omap3xxx_rfbi_hwmod_class, -+ .main_clk = "dss1_alwon_fck", - .prcm = { - .omap2 = { -- .module_offs = OMAP3430_PER_MOD, - .prcm_reg_id = 1, -- .module_bit = OMAP3630_EN_UART4_SHIFT, -- .idlest_reg_id = 1, -- .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT, -+ .module_bit = OMAP3430_EN_DSS1_SHIFT, -+ .module_offs = OMAP3430_DSS_MOD, - }, - }, -- .slaves = omap3xxx_uart4_slaves, -- .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), -- .class = &uart_class, -- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), -+ .slaves = omap3xxx_dss_rfbi_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | -+ CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | -+ CHIP_GE_OMAP3630ES1_1), -+ .flags = HWMOD_NO_IDLEST, - }; - --static struct omap_hwmod_class i2c_class = { -- .name = "i2c", -- .sysc = &i2c_sysc, -+/* -+ * 'venc' class -+ * video encoder -+ */ -+ -+static struct omap_hwmod_class omap3xxx_venc_hwmod_class = { -+ .name = "venc", -+}; -+ -+/* dss_venc */ -+static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = { -+ { -+ .pa_start = 0x48050C00, -+ .pa_end = 0x48050FFF, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> dss_venc */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap3xxx_dss_venc_hwmod, -+ .clk = "dss_tv_fck", -+ .addr = omap3xxx_dss_venc_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs), -+ .fw = { -+ .omap2 = { -+ .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, -+ .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP, -+ .flags = OMAP_FIREWALL_L4, -+ } -+ }, -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* dss_venc slave ports */ -+static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = { -+ &omap3xxx_l4_core__dss_venc, -+}; -+ -+static struct omap_hwmod omap3xxx_dss_venc_hwmod = { -+ .name = "dss_venc", -+ .class = &omap3xxx_venc_hwmod_class, -+ .main_clk = "dss1_alwon_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_DSS1_SHIFT, -+ .module_offs = OMAP3430_DSS_MOD, -+ }, -+ }, -+ .slaves = omap3xxx_dss_venc_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | -+ CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 | -+ CHIP_GE_OMAP3630ES1_1), -+ .flags = HWMOD_NO_IDLEST, - }; - - /* I2C1 */ -@@ -1224,9 +2434,440 @@ - .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters), - .dev_attr = &dma_dev_attr, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -- .flags = HWMOD_NO_IDLEST, -+ .flags = HWMOD_NO_IDLEST, -+}; -+ -+/* -+ * 'mcbsp' class -+ * multi channel buffered serial port controller -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = { -+ .sysc_offs = 0x008c, -+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | -+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+ .clockact = 0x2, -+}; -+ -+static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { -+ .name = "mcbsp", -+ .sysc = &omap3xxx_mcbsp_sysc, -+ .rev = MCBSP_CONFIG_TYPE3, -+}; -+ -+/* mcbsp1 */ -+static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { -+ { .name = "irq", .irq = 16 }, -+ { .name = "tx", .irq = 59 }, -+ { .name = "rx", .irq = 60 }, -+}; -+ -+static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = { -+ { .name = "rx", .dma_req = 32 }, -+ { .name = "tx", .dma_req = 31 }, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { -+ { -+ .name = "mpu", -+ .pa_start = 0x48074000, -+ .pa_end = 0x480740ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> mcbsp1 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap3xxx_mcbsp1_hwmod, -+ .clk = "mcbsp1_ick", -+ .addr = omap3xxx_mcbsp1_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mcbsp1 slave ports */ -+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = { -+ &omap3xxx_l4_core__mcbsp1, -+}; -+ -+static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { -+ .name = "mcbsp1", -+ .class = &omap3xxx_mcbsp_hwmod_class, -+ .mpu_irqs = omap3xxx_mcbsp1_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs), -+ .sdma_reqs = omap3xxx_mcbsp1_sdma_chs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs), -+ .main_clk = "mcbsp1_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_MCBSP1_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_mcbsp1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ -+/* mcbsp2 */ -+static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = { -+ { .name = "irq", .irq = 17 }, -+ { .name = "tx", .irq = 62 }, -+ { .name = "rx", .irq = 63 }, -+}; -+ -+static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = { -+ { .name = "rx", .dma_req = 34 }, -+ { .name = "tx", .dma_req = 33 }, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { -+ { -+ .name = "mpu", -+ .pa_start = 0x49022000, -+ .pa_end = 0x490220ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> mcbsp2 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = { -+ .master = &omap3xxx_l4_per_hwmod, -+ .slave = &omap3xxx_mcbsp2_hwmod, -+ .clk = "mcbsp2_ick", -+ .addr = omap3xxx_mcbsp2_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mcbsp2 slave ports */ -+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = { -+ &omap3xxx_l4_per__mcbsp2, -+}; -+ -+static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = { -+ .sidetone = "mcbsp2_sidetone", -+}; -+ -+static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { -+ .name = "mcbsp2", -+ .class = &omap3xxx_mcbsp_hwmod_class, -+ .mpu_irqs = omap3xxx_mcbsp2_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs), -+ .sdma_reqs = omap3xxx_mcbsp2_sdma_chs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs), -+ .main_clk = "mcbsp2_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_MCBSP2_SHIFT, -+ .module_offs = OMAP3430_PER_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_mcbsp2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves), -+ .dev_attr = &omap34xx_mcbsp2_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ -+/* mcbsp3 */ -+static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = { -+ { .name = "irq", .irq = 22 }, -+ { .name = "tx", .irq = 89 }, -+ { .name = "rx", .irq = 90 }, -+}; -+ -+static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = { -+ { .name = "rx", .dma_req = 18 }, -+ { .name = "tx", .dma_req = 17 }, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { -+ { -+ .name = "mpu", -+ .pa_start = 0x49024000, -+ .pa_end = 0x490240ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> mcbsp3 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = { -+ .master = &omap3xxx_l4_per_hwmod, -+ .slave = &omap3xxx_mcbsp3_hwmod, -+ .clk = "mcbsp3_ick", -+ .addr = omap3xxx_mcbsp3_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mcbsp3 slave ports */ -+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = { -+ &omap3xxx_l4_per__mcbsp3, -+}; -+ -+static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = { -+ .sidetone = "mcbsp3_sidetone", -+}; -+ -+static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { -+ .name = "mcbsp3", -+ .class = &omap3xxx_mcbsp_hwmod_class, -+ .mpu_irqs = omap3xxx_mcbsp3_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs), -+ .sdma_reqs = omap3xxx_mcbsp3_sdma_chs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs), -+ .main_clk = "mcbsp3_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_MCBSP3_SHIFT, -+ .module_offs = OMAP3430_PER_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_mcbsp3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves), -+ .dev_attr = &omap34xx_mcbsp3_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ -+/* mcbsp4 */ -+static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = { -+ { .name = "irq", .irq = 23 }, -+ { .name = "tx", .irq = 54 }, -+ { .name = "rx", .irq = 55 }, -+}; -+ -+static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { -+ { .name = "rx", .dma_req = 20 }, -+ { .name = "tx", .dma_req = 19 }, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { -+ { -+ .name = "mpu", -+ .pa_start = 0x49026000, -+ .pa_end = 0x490260ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> mcbsp4 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = { -+ .master = &omap3xxx_l4_per_hwmod, -+ .slave = &omap3xxx_mcbsp4_hwmod, -+ .clk = "mcbsp4_ick", -+ .addr = omap3xxx_mcbsp4_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mcbsp4 slave ports */ -+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = { -+ &omap3xxx_l4_per__mcbsp4, -+}; -+ -+static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { -+ .name = "mcbsp4", -+ .class = &omap3xxx_mcbsp_hwmod_class, -+ .mpu_irqs = omap3xxx_mcbsp4_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs), -+ .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs), -+ .main_clk = "mcbsp4_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_MCBSP4_SHIFT, -+ .module_offs = OMAP3430_PER_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_mcbsp4_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ -+/* mcbsp5 */ -+static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = { -+ { .name = "irq", .irq = 27 }, -+ { .name = "tx", .irq = 81 }, -+ { .name = "rx", .irq = 82 }, -+}; -+ -+static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { -+ { .name = "rx", .dma_req = 22 }, -+ { .name = "tx", .dma_req = 21 }, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { -+ { -+ .name = "mpu", -+ .pa_start = 0x48096000, -+ .pa_end = 0x480960ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_core -> mcbsp5 */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap3xxx_mcbsp5_hwmod, -+ .clk = "mcbsp5_ick", -+ .addr = omap3xxx_mcbsp5_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mcbsp5 slave ports */ -+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = { -+ &omap3xxx_l4_core__mcbsp5, -+}; -+ -+static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { -+ .name = "mcbsp5", -+ .class = &omap3xxx_mcbsp_hwmod_class, -+ .mpu_irqs = omap3xxx_mcbsp5_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs), -+ .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs), -+ .main_clk = "mcbsp5_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_MCBSP5_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_mcbsp5_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+/* 'mcbsp sidetone' class */ -+ -+static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = { -+ .sysc_offs = 0x0010, -+ .sysc_flags = SYSC_HAS_AUTOIDLE, -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = { -+ .name = "mcbsp_sidetone", -+ .sysc = &omap3xxx_mcbsp_sidetone_sysc, -+}; -+ -+/* mcbsp2_sidetone */ -+static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { -+ { .name = "irq", .irq = 4 }, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { -+ { -+ .name = "sidetone", -+ .pa_start = 0x49028000, -+ .pa_end = 0x490280ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> mcbsp2_sidetone */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = { -+ .master = &omap3xxx_l4_per_hwmod, -+ .slave = &omap3xxx_mcbsp2_sidetone_hwmod, -+ .clk = "mcbsp2_ick", -+ .addr = omap3xxx_mcbsp2_sidetone_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs), -+ .user = OCP_USER_MPU, -+}; -+ -+/* mcbsp2_sidetone slave ports */ -+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = { -+ &omap3xxx_l4_per__mcbsp2_sidetone, -+}; -+ -+static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = { -+ .name = "mcbsp2_sidetone", -+ .class = &omap3xxx_mcbsp_sidetone_hwmod_class, -+ .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs), -+ .main_clk = "mcbsp2_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_MCBSP2_SHIFT, -+ .module_offs = OMAP3430_PER_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_mcbsp2_sidetone_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ -+/* mcbsp3_sidetone */ -+static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { -+ { .name = "irq", .irq = 5 }, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { -+ { -+ .name = "sidetone", -+ .pa_start = 0x4902A000, -+ .pa_end = 0x4902A0ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> mcbsp3_sidetone */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = { -+ .master = &omap3xxx_l4_per_hwmod, -+ .slave = &omap3xxx_mcbsp3_sidetone_hwmod, -+ .clk = "mcbsp3_ick", -+ .addr = omap3xxx_mcbsp3_sidetone_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs), -+ .user = OCP_USER_MPU, -+}; -+ -+/* mcbsp3_sidetone slave ports */ -+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = { -+ &omap3xxx_l4_per__mcbsp3_sidetone, -+}; -+ -+static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = { -+ .name = "mcbsp3_sidetone", -+ .class = &omap3xxx_mcbsp_sidetone_hwmod_class, -+ .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs), -+ .main_clk = "mcbsp3_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_MCBSP3_SHIFT, -+ .module_offs = OMAP3430_PER_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_mcbsp3_sidetone_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), - }; - -+ - /* SR common */ - static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { - .clkact_shift = 20, -@@ -1356,18 +2997,617 @@ - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), - }; - -+/* -+ * 'mailbox' class -+ * mailbox module allowing communication between the on-chip processors -+ * using a queued mailbox-interrupt mechanism. -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = { -+ .rev_offs = 0x000, -+ .sysc_offs = 0x010, -+ .syss_offs = 0x014, -+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = { -+ .name = "mailbox", -+ .sysc = &omap3xxx_mailbox_sysc, -+}; -+ -+static struct omap_hwmod omap3xxx_mailbox_hwmod; -+static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { -+ { .irq = 26 }, -+}; -+ -+static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { -+ { -+ .pa_start = 0x48094000, -+ .pa_end = 0x480941ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+/* l4_core -> mailbox */ -+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap3xxx_mailbox_hwmod, -+ .addr = omap3xxx_mailbox_addrs, -+ .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mailbox slave ports */ -+static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = { -+ &omap3xxx_l4_core__mailbox, -+}; -+ -+static struct omap_hwmod omap3xxx_mailbox_hwmod = { -+ .name = "mailbox", -+ .class = &omap3xxx_mailbox_hwmod_class, -+ .mpu_irqs = omap3xxx_mailbox_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs), -+ .main_clk = "mailboxes_ick", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_MAILBOXES_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_mailbox_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ -+/* l4 core -> mcspi1 interface */ -+static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = { -+ { -+ .pa_start = 0x48098000, -+ .pa_end = 0x480980ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap34xx_mcspi1, -+ .clk = "mcspi1_ick", -+ .addr = omap34xx_mcspi1_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* l4 core -> mcspi2 interface */ -+static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = { -+ { -+ .pa_start = 0x4809a000, -+ .pa_end = 0x4809a0ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap34xx_mcspi2, -+ .clk = "mcspi2_ick", -+ .addr = omap34xx_mcspi2_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* l4 core -> mcspi3 interface */ -+static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = { -+ { -+ .pa_start = 0x480b8000, -+ .pa_end = 0x480b80ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap34xx_mcspi3, -+ .clk = "mcspi3_ick", -+ .addr = omap34xx_mcspi3_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* l4 core -> mcspi4 interface */ -+static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = { -+ { -+ .pa_start = 0x480ba000, -+ .pa_end = 0x480ba0ff, -+ .flags = ADDR_TYPE_RT, -+ }, -+}; -+ -+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { -+ .master = &omap3xxx_l4_core_hwmod, -+ .slave = &omap34xx_mcspi4, -+ .clk = "mcspi4_ick", -+ .addr = omap34xx_mcspi4_addr_space, -+ .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* -+ * 'mcspi' class -+ * multichannel serial port interface (mcspi) / master/slave synchronous serial -+ * bus -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap34xx_mcspi_class = { -+ .name = "mcspi", -+ .sysc = &omap34xx_mcspi_sysc, -+ .rev = OMAP3_MCSPI_REV, -+}; -+ -+/* mcspi1 */ -+static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = { -+ { .name = "irq", .irq = 65 }, -+}; -+ -+static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = { -+ { .name = "tx0", .dma_req = 35 }, -+ { .name = "rx0", .dma_req = 36 }, -+ { .name = "tx1", .dma_req = 37 }, -+ { .name = "rx1", .dma_req = 38 }, -+ { .name = "tx2", .dma_req = 39 }, -+ { .name = "rx2", .dma_req = 40 }, -+ { .name = "tx3", .dma_req = 41 }, -+ { .name = "rx3", .dma_req = 42 }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = { -+ &omap34xx_l4_core__mcspi1, -+}; -+ -+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { -+ .num_chipselect = 4, -+}; -+ -+static struct omap_hwmod omap34xx_mcspi1 = { -+ .name = "mcspi1", -+ .mpu_irqs = omap34xx_mcspi1_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs), -+ .sdma_reqs = omap34xx_mcspi1_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs), -+ .main_clk = "mcspi1_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_MCSPI1_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT, -+ }, -+ }, -+ .slaves = omap34xx_mcspi1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves), -+ .class = &omap34xx_mcspi_class, -+ .dev_attr = &omap_mcspi1_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ -+/* mcspi2 */ -+static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = { -+ { .name = "irq", .irq = 66 }, -+}; -+ -+static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = { -+ { .name = "tx0", .dma_req = 43 }, -+ { .name = "rx0", .dma_req = 44 }, -+ { .name = "tx1", .dma_req = 45 }, -+ { .name = "rx1", .dma_req = 46 }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = { -+ &omap34xx_l4_core__mcspi2, -+}; -+ -+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { -+ .num_chipselect = 2, -+}; -+ -+static struct omap_hwmod omap34xx_mcspi2 = { -+ .name = "mcspi2", -+ .mpu_irqs = omap34xx_mcspi2_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs), -+ .sdma_reqs = omap34xx_mcspi2_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs), -+ .main_clk = "mcspi2_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_MCSPI2_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT, -+ }, -+ }, -+ .slaves = omap34xx_mcspi2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves), -+ .class = &omap34xx_mcspi_class, -+ .dev_attr = &omap_mcspi2_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ -+/* mcspi3 */ -+static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { -+ { .name = "irq", .irq = 91 }, /* 91 */ -+}; -+ -+static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { -+ { .name = "tx0", .dma_req = 15 }, -+ { .name = "rx0", .dma_req = 16 }, -+ { .name = "tx1", .dma_req = 23 }, -+ { .name = "rx1", .dma_req = 24 }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = { -+ &omap34xx_l4_core__mcspi3, -+}; -+ -+static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = { -+ .num_chipselect = 2, -+}; -+ -+static struct omap_hwmod omap34xx_mcspi3 = { -+ .name = "mcspi3", -+ .mpu_irqs = omap34xx_mcspi3_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs), -+ .sdma_reqs = omap34xx_mcspi3_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs), -+ .main_clk = "mcspi3_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_MCSPI3_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT, -+ }, -+ }, -+ .slaves = omap34xx_mcspi3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves), -+ .class = &omap34xx_mcspi_class, -+ .dev_attr = &omap_mcspi3_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ -+/* SPI4 */ -+static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { -+ { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ -+}; -+ -+static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { -+ { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ -+ { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ -+}; -+ -+static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = { -+ &omap34xx_l4_core__mcspi4, -+}; -+ -+static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = { -+ .num_chipselect = 1, -+}; -+ -+static struct omap_hwmod omap34xx_mcspi4 = { -+ .name = "mcspi4", -+ .mpu_irqs = omap34xx_mcspi4_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs), -+ .sdma_reqs = omap34xx_mcspi4_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs), -+ .main_clk = "mcspi4_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_MCSPI4_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT, -+ }, -+ }, -+ .slaves = omap34xx_mcspi4_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves), -+ .class = &omap34xx_mcspi_class, -+ .dev_attr = &omap_mcspi4_dev_attr, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ -+/* -+ * usbhsotg -+ */ -+static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = { -+ .rev_offs = 0x0400, -+ .sysc_offs = 0x0404, -+ .syss_offs = 0x0408, -+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class usbotg_class = { -+ .name = "usbotg", -+ .sysc = &omap3xxx_usbhsotg_sysc, -+}; -+/* usb_otg_hs */ -+static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = { -+ -+ { .name = "mc", .irq = 92 }, -+ { .name = "dma", .irq = 93 }, -+}; -+ -+static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { -+ .name = "usb_otg_hs", -+ .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs), -+ .main_clk = "hsotgusb_ick", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT, -+ .module_offs = CORE_MOD, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT, -+ .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT -+ }, -+ }, -+ .masters = omap3xxx_usbhsotg_masters, -+ .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters), -+ .slaves = omap3xxx_usbhsotg_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves), -+ .class = &usbotg_class, -+ -+ /* -+ * Erratum ID: i479 idle_req / idle_ack mechanism potentially -+ * broken when autoidle is enabled -+ * workaround is to disable the autoidle bit at module level. -+ */ -+ .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE -+ | HWMOD_SWSUP_MSTANDBY, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) -+}; -+ -+/* usb_otg_hs */ -+static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { -+ -+ { .name = "mc", .irq = 71 }, -+}; -+ -+static struct omap_hwmod_class am35xx_usbotg_class = { -+ .name = "am35xx_usbotg", -+ .sysc = NULL, -+}; -+ -+static struct omap_hwmod am35xx_usbhsotg_hwmod = { -+ .name = "am35x_otg_hs", -+ .mpu_irqs = am35xx_usbhsotg_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs), -+ .main_clk = NULL, -+ .prcm = { -+ .omap2 = { -+ }, -+ }, -+ .masters = am35xx_usbhsotg_masters, -+ .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters), -+ .slaves = am35xx_usbhsotg_slaves, -+ .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves), -+ .class = &am35xx_usbotg_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1) -+}; -+ -+/* MMC/SD/SDIO common */ -+ -+static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = { -+ .rev_offs = 0x1fc, -+ .sysc_offs = 0x10, -+ .syss_offs = 0x14, -+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | -+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap34xx_mmc_class = { -+ .name = "mmc", -+ .sysc = &omap34xx_mmc_sysc, -+}; -+ -+/* MMC/SD/SDIO1 */ -+ -+static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { -+ { .irq = 83, }, -+}; -+ -+static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 61, }, -+ { .name = "rx", .dma_req = 62, }, -+}; -+ -+static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { -+ { .role = "dbck", .clk = "omap_32k_fck", }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = { -+ &omap3xxx_l4_core__mmc1, -+}; -+ -+static struct omap_mmc_dev_attr mmc1_dev_attr = { -+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, -+}; -+ -+static struct omap_hwmod omap3xxx_mmc1_hwmod = { -+ .name = "mmc1", -+ .mpu_irqs = omap34xx_mmc1_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs), -+ .sdma_reqs = omap34xx_mmc1_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs), -+ .opt_clks = omap34xx_mmc1_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), -+ .main_clk = "mmchs1_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_MMC1_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT, -+ }, -+ }, -+ .dev_attr = &mmc1_dev_attr, -+ .slaves = omap3xxx_mmc1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves), -+ .class = &omap34xx_mmc_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ -+/* MMC/SD/SDIO2 */ -+ -+static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { -+ { .irq = INT_24XX_MMC2_IRQ, }, -+}; -+ -+static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 47, }, -+ { .name = "rx", .dma_req = 48, }, -+}; -+ -+static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { -+ { .role = "dbck", .clk = "omap_32k_fck", }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = { -+ &omap3xxx_l4_core__mmc2, -+}; -+ -+static struct omap_hwmod omap3xxx_mmc2_hwmod = { -+ .name = "mmc2", -+ .mpu_irqs = omap34xx_mmc2_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs), -+ .sdma_reqs = omap34xx_mmc2_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs), -+ .opt_clks = omap34xx_mmc2_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), -+ .main_clk = "mmchs2_fck", -+ .prcm = { -+ .omap2 = { -+ .module_offs = CORE_MOD, -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_MMC2_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_mmc2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves), -+ .class = &omap34xx_mmc_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ -+/* MMC/SD/SDIO3 */ -+ -+static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { -+ { .irq = 94, }, -+}; -+ -+static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 77, }, -+ { .name = "rx", .dma_req = 78, }, -+}; -+ -+static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { -+ { .role = "dbck", .clk = "omap_32k_fck", }, -+}; -+ -+static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = { -+ &omap3xxx_l4_core__mmc3, -+}; -+ -+static struct omap_hwmod omap3xxx_mmc3_hwmod = { -+ .name = "mmc3", -+ .mpu_irqs = omap34xx_mmc3_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs), -+ .sdma_reqs = omap34xx_mmc3_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs), -+ .opt_clks = omap34xx_mmc3_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), -+ .main_clk = "mmchs3_fck", -+ .prcm = { -+ .omap2 = { -+ .prcm_reg_id = 1, -+ .module_bit = OMAP3430_EN_MMC3_SHIFT, -+ .idlest_reg_id = 1, -+ .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT, -+ }, -+ }, -+ .slaves = omap3xxx_mmc3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves), -+ .class = &omap34xx_mmc_class, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), -+}; -+ - static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { - &omap3xxx_l3_main_hwmod, - &omap3xxx_l4_core_hwmod, - &omap3xxx_l4_per_hwmod, - &omap3xxx_l4_wkup_hwmod, -+ &omap3xxx_mmc1_hwmod, -+ &omap3xxx_mmc2_hwmod, -+ &omap3xxx_mmc3_hwmod, - &omap3xxx_mpu_hwmod, - &omap3xxx_iva_hwmod, -+ -+ &omap3xxx_timer1_hwmod, -+ &omap3xxx_timer2_hwmod, -+ &omap3xxx_timer3_hwmod, -+ &omap3xxx_timer4_hwmod, -+ &omap3xxx_timer5_hwmod, -+ &omap3xxx_timer6_hwmod, -+ &omap3xxx_timer7_hwmod, -+ &omap3xxx_timer8_hwmod, -+ &omap3xxx_timer9_hwmod, -+ &omap3xxx_timer10_hwmod, -+ &omap3xxx_timer11_hwmod, -+ &omap3xxx_timer12_hwmod, -+ - &omap3xxx_wd_timer2_hwmod, - &omap3xxx_uart1_hwmod, - &omap3xxx_uart2_hwmod, - &omap3xxx_uart3_hwmod, - &omap3xxx_uart4_hwmod, -+ /* dss class */ -+ &omap3430es1_dss_core_hwmod, -+ &omap3xxx_dss_core_hwmod, -+ &omap3xxx_dss_dispc_hwmod, -+ &omap3xxx_dss_dsi1_hwmod, -+ &omap3xxx_dss_rfbi_hwmod, -+ &omap3xxx_dss_venc_hwmod, -+ -+ /* i2c class */ - &omap3xxx_i2c1_hwmod, - &omap3xxx_i2c2_hwmod, - &omap3xxx_i2c3_hwmod, -@@ -1387,10 +3627,35 @@ - - /* dma_system class*/ - &omap3xxx_dma_system_hwmod, -+ -+ /* mcbsp class */ -+ &omap3xxx_mcbsp1_hwmod, -+ &omap3xxx_mcbsp2_hwmod, -+ &omap3xxx_mcbsp3_hwmod, -+ &omap3xxx_mcbsp4_hwmod, -+ &omap3xxx_mcbsp5_hwmod, -+ &omap3xxx_mcbsp2_sidetone_hwmod, -+ &omap3xxx_mcbsp3_sidetone_hwmod, -+ -+ /* mailbox class */ -+ &omap3xxx_mailbox_hwmod, -+ -+ /* mcspi class */ -+ &omap34xx_mcspi1, -+ &omap34xx_mcspi2, -+ &omap34xx_mcspi3, -+ &omap34xx_mcspi4, -+ -+ /* usbotg class */ -+ &omap3xxx_usbhsotg_hwmod, -+ -+ /* usbotg for am35x */ -+ &am35xx_usbhsotg_hwmod, -+ - NULL, - }; - - int __init omap3xxx_hwmod_init(void) - { -- return omap_hwmod_init(omap3xxx_hwmods); -+ return omap_hwmod_register(omap3xxx_hwmods); - } -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod_44xx_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod_44xx_data.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod_44xx_data.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod_44xx_data.c 2011-03-09 13:19:09.830507217 +0100 -@@ -1,7 +1,7 @@ - /* - * Hardware modules present on the OMAP44xx chips - * -- * Copyright (C) 2009-2010 Texas Instruments, Inc. -+ * Copyright (C) 2009-2011 Texas Instruments, Inc. - * Copyright (C) 2009-2010 Nokia Corporation - * - * Paul Walmsley -@@ -24,6 +24,9 @@ - #include - #include - #include -+#include -+#include -+#include - - #include "omap_hwmod_common_data.h" - -@@ -40,10 +43,15 @@ - #define OMAP44XX_DMA_REQ_START 1 - - /* Backward references (IPs with Bus Master capability) */ -+static struct omap_hwmod omap44xx_aess_hwmod; - static struct omap_hwmod omap44xx_dma_system_hwmod; - static struct omap_hwmod omap44xx_dmm_hwmod; - static struct omap_hwmod omap44xx_dsp_hwmod; -+static struct omap_hwmod omap44xx_dss_hwmod; - static struct omap_hwmod omap44xx_emif_fw_hwmod; -+static struct omap_hwmod omap44xx_hsi_hwmod; -+static struct omap_hwmod omap44xx_ipu_hwmod; -+static struct omap_hwmod omap44xx_iss_hwmod; - static struct omap_hwmod omap44xx_iva_hwmod; - static struct omap_hwmod omap44xx_l3_instr_hwmod; - static struct omap_hwmod omap44xx_l3_main_1_hwmod; -@@ -53,8 +61,11 @@ - static struct omap_hwmod omap44xx_l4_cfg_hwmod; - static struct omap_hwmod omap44xx_l4_per_hwmod; - static struct omap_hwmod omap44xx_l4_wkup_hwmod; -+static struct omap_hwmod omap44xx_mmc1_hwmod; -+static struct omap_hwmod omap44xx_mmc2_hwmod; - static struct omap_hwmod omap44xx_mpu_hwmod; - static struct omap_hwmod omap44xx_mpu_private_hwmod; -+static struct omap_hwmod omap44xx_usb_otg_hs_hwmod; - - /* - * Interconnects omap_hwmod structures -@@ -213,6 +224,14 @@ - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - -+/* dss -> l3_main_1 */ -+static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { -+ .master = &omap44xx_dss_hwmod, -+ .slave = &omap44xx_l3_main_1_hwmod, -+ .clk = "l3_div_ck", -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ - /* l3_main_2 -> l3_main_1 */ - static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { - .master = &omap44xx_l3_main_2_hwmod, -@@ -229,6 +248,22 @@ - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - -+/* mmc1 -> l3_main_1 */ -+static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { -+ .master = &omap44xx_mmc1_hwmod, -+ .slave = &omap44xx_l3_main_1_hwmod, -+ .clk = "l3_div_ck", -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mmc2 -> l3_main_1 */ -+static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { -+ .master = &omap44xx_mmc2_hwmod, -+ .slave = &omap44xx_l3_main_1_hwmod, -+ .clk = "l3_div_ck", -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ - /* mpu -> l3_main_1 */ - static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { - .master = &omap44xx_mpu_hwmod, -@@ -240,8 +275,11 @@ - /* l3_main_1 slave ports */ - static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = { - &omap44xx_dsp__l3_main_1, -+ &omap44xx_dss__l3_main_1, - &omap44xx_l3_main_2__l3_main_1, - &omap44xx_l4_cfg__l3_main_1, -+ &omap44xx_mmc1__l3_main_1, -+ &omap44xx_mmc2__l3_main_1, - &omap44xx_mpu__l3_main_1, - }; - -@@ -262,6 +300,30 @@ - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - -+/* hsi -> l3_main_2 */ -+static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { -+ .master = &omap44xx_hsi_hwmod, -+ .slave = &omap44xx_l3_main_2_hwmod, -+ .clk = "l3_div_ck", -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* ipu -> l3_main_2 */ -+static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { -+ .master = &omap44xx_ipu_hwmod, -+ .slave = &omap44xx_l3_main_2_hwmod, -+ .clk = "l3_div_ck", -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* iss -> l3_main_2 */ -+static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { -+ .master = &omap44xx_iss_hwmod, -+ .slave = &omap44xx_l3_main_2_hwmod, -+ .clk = "l3_div_ck", -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ - /* iva -> l3_main_2 */ - static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { - .master = &omap44xx_iva_hwmod, -@@ -286,12 +348,24 @@ - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - -+/* usb_otg_hs -> l3_main_2 */ -+static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { -+ .master = &omap44xx_usb_otg_hs_hwmod, -+ .slave = &omap44xx_l3_main_2_hwmod, -+ .clk = "l3_div_ck", -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ - /* l3_main_2 slave ports */ - static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = { - &omap44xx_dma_system__l3_main_2, -+ &omap44xx_hsi__l3_main_2, -+ &omap44xx_ipu__l3_main_2, -+ &omap44xx_iss__l3_main_2, - &omap44xx_iva__l3_main_2, - &omap44xx_l3_main_1__l3_main_2, - &omap44xx_l4_cfg__l3_main_2, -+ &omap44xx_usb_otg_hs__l3_main_2, - }; - - static struct omap_hwmod omap44xx_l3_main_2_hwmod = { -@@ -351,6 +425,14 @@ - }; - - /* l4_abe interface data */ -+/* aess -> l4_abe */ -+static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { -+ .master = &omap44xx_aess_hwmod, -+ .slave = &omap44xx_l4_abe_hwmod, -+ .clk = "ocp_abe_iclk", -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ - /* dsp -> l4_abe */ - static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { - .master = &omap44xx_dsp_hwmod, -@@ -377,6 +459,7 @@ - - /* l4_abe slave ports */ - static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = { -+ &omap44xx_aess__l4_abe, - &omap44xx_dsp__l4_abe, - &omap44xx_l3_main_1__l4_abe, - &omap44xx_mpu__l4_abe, -@@ -494,26 +577,15 @@ - * - They still need to be validated with the driver - * properly adapted to omap_hwmod / omap_device - * -- * aess -- * bandgap - * c2c - * c2c_target_fw - * cm_core - * cm_core_aon -- * counter_32k - * ctrl_module_core - * ctrl_module_pad_core - * ctrl_module_pad_wkup - * ctrl_module_wkup - * debugss -- * dmic -- * dss -- * dss_dispc -- * dss_dsi1 -- * dss_dsi2 -- * dss_hdmi -- * dss_rfbi -- * dss_venc - * efuse_ctrl_cust - * efuse_ctrl_std - * elm -@@ -524,58 +596,211 @@ - * gpu - * hdq1w - * hsi -- * ipu -- * iss -- * kbd -- * mailbox -- * mcasp -- * mcbsp1 -- * mcbsp2 -- * mcbsp3 -- * mcbsp4 -- * mcpdm -- * mcspi1 -- * mcspi2 -- * mcspi3 -- * mcspi4 -- * mmc1 -- * mmc2 -- * mmc3 -- * mmc4 -- * mmc5 -- * mpu_c0 -- * mpu_c1 - * ocmc_ram - * ocp2scp_usb_phy - * ocp_wp_noc -- * prcm - * prcm_mpu - * prm - * scrm - * sl2if - * slimbus1 - * slimbus2 -- * spinlock -- * timer1 -- * timer10 -- * timer11 -- * timer2 -- * timer3 -- * timer4 -- * timer5 -- * timer6 -- * timer7 -- * timer8 -- * timer9 - * usb_host_fs - * usb_host_hs -- * usb_otg_hs - * usb_phy_cm - * usb_tll_hs - * usim - */ - - /* -+ * 'aess' class -+ * audio engine sub system -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type2, -+}; -+ -+static struct omap_hwmod_class omap44xx_aess_hwmod_class = { -+ .name = "aess", -+ .sysc = &omap44xx_aess_sysc, -+}; -+ -+/* aess */ -+static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { -+ { .irq = 99 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { -+ { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, -+ { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, -+ { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, -+ { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, -+ { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, -+ { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, -+ { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, -+ { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+/* aess master ports */ -+static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = { -+ &omap44xx_aess__l4_abe, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { -+ { -+ .pa_start = 0x401f1000, -+ .pa_end = 0x401f13ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_abe -> aess */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_aess_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_aess_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_aess_addrs), -+ .user = OCP_USER_MPU, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { -+ { -+ .pa_start = 0x490f1000, -+ .pa_end = 0x490f13ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_abe -> aess (dma) */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_aess_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_aess_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_aess_dma_addrs), -+ .user = OCP_USER_SDMA, -+}; -+ -+/* aess slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = { -+ &omap44xx_l4_abe__aess, -+ &omap44xx_l4_abe__aess_dma, -+}; -+ -+static struct omap_hwmod omap44xx_aess_hwmod = { -+ .name = "aess", -+ .class = &omap44xx_aess_hwmod_class, -+ .mpu_irqs = omap44xx_aess_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs), -+ .sdma_reqs = omap44xx_aess_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs), -+ .main_clk = "aess_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_aess_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves), -+ .masters = omap44xx_aess_masters, -+ .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'bandgap' class -+ * bangap reference for ldo regulators -+ */ -+ -+static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = { -+ .name = "bandgap", -+}; -+ -+/* bandgap */ -+static struct omap_hwmod_opt_clk bandgap_opt_clks[] = { -+ { .role = "fclk", .clk = "bandgap_fclk" }, -+}; -+ -+static struct omap_hwmod omap44xx_bandgap_hwmod = { -+ .name = "bandgap", -+ .class = &omap44xx_bandgap_hwmod_class, -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, -+ }, -+ }, -+ .opt_clks = bandgap_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'counter' class -+ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0004, -+ .sysc_flags = SYSC_HAS_SIDLEMODE, -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ SIDLE_SMART_WKUP), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap44xx_counter_hwmod_class = { -+ .name = "counter", -+ .sysc = &omap44xx_counter_sysc, -+}; -+ -+/* counter_32k */ -+static struct omap_hwmod omap44xx_counter_32k_hwmod; -+static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { -+ { -+ .pa_start = 0x4a304000, -+ .pa_end = 0x4a30401f, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_wkup -> counter_32k */ -+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { -+ .master = &omap44xx_l4_wkup_hwmod, -+ .slave = &omap44xx_counter_32k_hwmod, -+ .clk = "l4_wkup_clk_mux_ck", -+ .addr = omap44xx_counter_32k_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_counter_32k_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* counter_32k slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = { -+ &omap44xx_l4_wkup__counter_32k, -+}; -+ -+static struct omap_hwmod omap44xx_counter_32k_hwmod = { -+ .name = "counter_32k", -+ .class = &omap44xx_counter_hwmod_class, -+ .flags = HWMOD_SWSUP_SIDLE, -+ .main_clk = "sys_32k_ck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_counter_32k_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* - * 'dma' class - * dma controller for data exchange between memory to memory (i.e. internal or - * external memory) and gp peripherals to memory or memory to gp peripherals -@@ -662,6 +887,96 @@ - }; - - /* -+ * 'dmic' class -+ * digital microphone controller -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | -+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ SIDLE_SMART_WKUP), -+ .sysc_fields = &omap_hwmod_sysc_type2, -+}; -+ -+static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { -+ .name = "dmic", -+ .sysc = &omap44xx_dmic_sysc, -+}; -+ -+/* dmic */ -+static struct omap_hwmod omap44xx_dmic_hwmod; -+static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { -+ { .irq = 114 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { -+ { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { -+ { -+ .pa_start = 0x4012e000, -+ .pa_end = 0x4012e07f, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_abe -> dmic */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_dmic_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_dmic_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_dmic_addrs), -+ .user = OCP_USER_MPU, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { -+ { -+ .pa_start = 0x4902e000, -+ .pa_end = 0x4902e07f, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_abe -> dmic (dma) */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_dmic_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_dmic_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_dmic_dma_addrs), -+ .user = OCP_USER_SDMA, -+}; -+ -+/* dmic slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = { -+ &omap44xx_l4_abe__dmic, -+ &omap44xx_l4_abe__dmic_dma, -+}; -+ -+static struct omap_hwmod omap44xx_dmic_hwmod = { -+ .name = "dmic", -+ .class = &omap44xx_dmic_hwmod_class, -+ .mpu_irqs = omap44xx_dmic_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmic_irqs), -+ .sdma_reqs = omap44xx_dmic_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs), -+ .main_clk = "dmic_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_dmic_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* - * 'dsp' class - * dsp sub-system - */ -@@ -747,894 +1062,3485 @@ - }; - - /* -- * 'gpio' class -- * general purpose io module -+ * 'dss' class -+ * display sub-system - */ - --static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { -+static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { - .rev_offs = 0x0000, -- .sysc_offs = 0x0010, -- .syss_offs = 0x0114, -- .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | -- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | -- SYSS_HAS_RESET_STATUS), -- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -- SIDLE_SMART_WKUP), -- .sysc_fields = &omap_hwmod_sysc_type1, --}; -- --static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { -- .name = "gpio", -- .sysc = &omap44xx_gpio_sysc, -- .rev = 2, -+ .syss_offs = 0x0014, -+ .sysc_flags = SYSS_HAS_RESET_STATUS, - }; - --/* gpio dev_attr */ --static struct omap_gpio_dev_attr gpio_dev_attr = { -- .bank_width = 32, -- .dbck_flag = true, -+static struct omap_hwmod_class omap44xx_dss_hwmod_class = { -+ .name = "dss", -+ .sysc = &omap44xx_dss_sysc, - }; - --/* gpio1 */ --static struct omap_hwmod omap44xx_gpio1_hwmod; --static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { -- { .irq = 29 + OMAP44XX_IRQ_GIC_START }, -+/* dss */ -+/* dss master ports */ -+static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = { -+ &omap44xx_dss__l3_main_1, - }; - --static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { -+static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { - { -- .pa_start = 0x4a310000, -- .pa_end = 0x4a3101ff, -+ .pa_start = 0x58000000, -+ .pa_end = 0x5800007f, - .flags = ADDR_TYPE_RT - }, - }; - --/* l4_wkup -> gpio1 */ --static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { -- .master = &omap44xx_l4_wkup_hwmod, -- .slave = &omap44xx_gpio1_hwmod, -- .clk = "l4_wkup_clk_mux_ck", -- .addr = omap44xx_gpio1_addrs, -- .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs), -- .user = OCP_USER_MPU | OCP_USER_SDMA, -+/* l3_main_2 -> dss */ -+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { -+ .master = &omap44xx_l3_main_2_hwmod, -+ .slave = &omap44xx_dss_hwmod, -+ .clk = "l3_div_ck", -+ .addr = omap44xx_dss_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs), -+ .user = OCP_USER_SDMA, - }; - --/* gpio1 slave ports */ --static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { -- &omap44xx_l4_wkup__gpio1, -+static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { -+ { -+ .pa_start = 0x48040000, -+ .pa_end = 0x4804007f, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { -- { .role = "dbclk", .clk = "gpio1_dbclk" }, -+/* l4_per -> dss */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_dss_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_dss_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs), -+ .user = OCP_USER_MPU, - }; - --static struct omap_hwmod omap44xx_gpio1_hwmod = { -- .name = "gpio1", -- .class = &omap44xx_gpio_hwmod_class, -- .mpu_irqs = omap44xx_gpio1_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs), -- .main_clk = "gpio1_ick", -+/* dss slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = { -+ &omap44xx_l3_main_2__dss, -+ &omap44xx_l4_per__dss, -+}; -+ -+static struct omap_hwmod_opt_clk dss_opt_clks[] = { -+ { .role = "sys_clk", .clk = "dss_sys_clk" }, -+ { .role = "tv_clk", .clk = "dss_tv_clk" }, -+ { .role = "dss_clk", .clk = "dss_dss_clk" }, -+ { .role = "video_clk", .clk = "dss_48mhz_clk" }, -+}; -+ -+static struct omap_hwmod omap44xx_dss_hwmod = { -+ .name = "dss_core", -+ .class = &omap44xx_dss_hwmod_class, -+ .main_clk = "dss_fck", - .prcm = { - .omap4 = { -- .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, -+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - }, - }, -- .opt_clks = gpio1_opt_clks, -- .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), -- .dev_attr = &gpio_dev_attr, -- .slaves = omap44xx_gpio1_slaves, -- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), -+ .opt_clks = dss_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), -+ .slaves = omap44xx_dss_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves), -+ .masters = omap44xx_dss_masters, -+ .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - --/* gpio2 */ --static struct omap_hwmod omap44xx_gpio2_hwmod; --static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { -- { .irq = 30 + OMAP44XX_IRQ_GIC_START }, -+/* -+ * 'dispc' class -+ * display controller -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | -+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | -+ SYSS_HAS_RESET_STATUS), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, - }; - --static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { -- { -- .pa_start = 0x48055000, -- .pa_end = 0x480551ff, -- .flags = ADDR_TYPE_RT -- }, -+static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { -+ .name = "dispc", -+ .sysc = &omap44xx_dispc_sysc, - }; - --/* l4_per -> gpio2 */ --static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { -- .master = &omap44xx_l4_per_hwmod, -- .slave = &omap44xx_gpio2_hwmod, -- .clk = "l4_div_ck", -- .addr = omap44xx_gpio2_addrs, -- .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs), -- .user = OCP_USER_MPU | OCP_USER_SDMA, -+/* dss_dispc */ -+static struct omap_hwmod omap44xx_dss_dispc_hwmod; -+static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { -+ { .irq = 25 + OMAP44XX_IRQ_GIC_START }, - }; - --/* gpio2 slave ports */ --static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { -- &omap44xx_l4_per__gpio2, -+static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { -+ { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, - }; - --static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { -- { .role = "dbclk", .clk = "gpio2_dbclk" }, -+static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { -+ { -+ .pa_start = 0x58001000, -+ .pa_end = 0x58001fff, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod omap44xx_gpio2_hwmod = { -- .name = "gpio2", -- .class = &omap44xx_gpio_hwmod_class, -- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, -- .mpu_irqs = omap44xx_gpio2_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs), -- .main_clk = "gpio2_ick", -+/* l3_main_2 -> dss_dispc */ -+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { -+ .master = &omap44xx_l3_main_2_hwmod, -+ .slave = &omap44xx_dss_dispc_hwmod, -+ .clk = "l3_div_ck", -+ .addr = omap44xx_dss_dispc_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs), -+ .user = OCP_USER_SDMA, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { -+ { -+ .pa_start = 0x48041000, -+ .pa_end = 0x48041fff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> dss_dispc */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_dss_dispc_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_dss_dispc_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs), -+ .user = OCP_USER_MPU, -+}; -+ -+/* dss_dispc slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = { -+ &omap44xx_l3_main_2__dss_dispc, -+ &omap44xx_l4_per__dss_dispc, -+}; -+ -+static struct omap_hwmod omap44xx_dss_dispc_hwmod = { -+ .name = "dss_dispc", -+ .class = &omap44xx_dispc_hwmod_class, -+ .mpu_irqs = omap44xx_dss_dispc_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs), -+ .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs), -+ .main_clk = "dss_fck", - .prcm = { - .omap4 = { -- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, -+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - }, - }, -- .opt_clks = gpio2_opt_clks, -- .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), -- .dev_attr = &gpio_dev_attr, -- .slaves = omap44xx_gpio2_slaves, -- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), -+ .slaves = omap44xx_dss_dispc_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - --/* gpio3 */ --static struct omap_hwmod omap44xx_gpio3_hwmod; --static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { -- { .irq = 31 + OMAP44XX_IRQ_GIC_START }, -+/* -+ * 'dsi' class -+ * display serial interface controller -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, - }; - --static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { -+static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { -+ .name = "dsi", -+ .sysc = &omap44xx_dsi_sysc, -+}; -+ -+/* dss_dsi1 */ -+static struct omap_hwmod omap44xx_dss_dsi1_hwmod; -+static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { -+ { .irq = 53 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { -+ { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { - { -- .pa_start = 0x48057000, -- .pa_end = 0x480571ff, -+ .pa_start = 0x58004000, -+ .pa_end = 0x580041ff, - .flags = ADDR_TYPE_RT - }, - }; - --/* l4_per -> gpio3 */ --static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { -- .master = &omap44xx_l4_per_hwmod, -- .slave = &omap44xx_gpio3_hwmod, -- .clk = "l4_div_ck", -- .addr = omap44xx_gpio3_addrs, -- .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs), -- .user = OCP_USER_MPU | OCP_USER_SDMA, -+/* l3_main_2 -> dss_dsi1 */ -+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { -+ .master = &omap44xx_l3_main_2_hwmod, -+ .slave = &omap44xx_dss_dsi1_hwmod, -+ .clk = "l3_div_ck", -+ .addr = omap44xx_dss_dsi1_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs), -+ .user = OCP_USER_SDMA, - }; - --/* gpio3 slave ports */ --static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { -- &omap44xx_l4_per__gpio3, -+static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { -+ { -+ .pa_start = 0x48044000, -+ .pa_end = 0x480441ff, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { -- { .role = "dbclk", .clk = "gpio3_dbclk" }, -+/* l4_per -> dss_dsi1 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_dss_dsi1_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_dss_dsi1_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs), -+ .user = OCP_USER_MPU, - }; - --static struct omap_hwmod omap44xx_gpio3_hwmod = { -- .name = "gpio3", -- .class = &omap44xx_gpio_hwmod_class, -- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, -- .mpu_irqs = omap44xx_gpio3_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs), -- .main_clk = "gpio3_ick", -+/* dss_dsi1 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = { -+ &omap44xx_l3_main_2__dss_dsi1, -+ &omap44xx_l4_per__dss_dsi1, -+}; -+ -+static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { -+ .name = "dss_dsi1", -+ .class = &omap44xx_dsi_hwmod_class, -+ .mpu_irqs = omap44xx_dss_dsi1_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs), -+ .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs), -+ .main_clk = "dss_fck", - .prcm = { - .omap4 = { -- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, -+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - }, - }, -- .opt_clks = gpio3_opt_clks, -- .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), -- .dev_attr = &gpio_dev_attr, -- .slaves = omap44xx_gpio3_slaves, -- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), -+ .slaves = omap44xx_dss_dsi1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - --/* gpio4 */ --static struct omap_hwmod omap44xx_gpio4_hwmod; --static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { -- { .irq = 32 + OMAP44XX_IRQ_GIC_START }, -+/* dss_dsi2 */ -+static struct omap_hwmod omap44xx_dss_dsi2_hwmod; -+static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { -+ { .irq = 84 + OMAP44XX_IRQ_GIC_START }, - }; - --static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { -+static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { -+ { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { - { -- .pa_start = 0x48059000, -- .pa_end = 0x480591ff, -+ .pa_start = 0x58005000, -+ .pa_end = 0x580051ff, - .flags = ADDR_TYPE_RT - }, - }; - --/* l4_per -> gpio4 */ --static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { -- .master = &omap44xx_l4_per_hwmod, -- .slave = &omap44xx_gpio4_hwmod, -- .clk = "l4_div_ck", -- .addr = omap44xx_gpio4_addrs, -- .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs), -- .user = OCP_USER_MPU | OCP_USER_SDMA, -+/* l3_main_2 -> dss_dsi2 */ -+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { -+ .master = &omap44xx_l3_main_2_hwmod, -+ .slave = &omap44xx_dss_dsi2_hwmod, -+ .clk = "l3_div_ck", -+ .addr = omap44xx_dss_dsi2_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs), -+ .user = OCP_USER_SDMA, - }; - --/* gpio4 slave ports */ --static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { -- &omap44xx_l4_per__gpio4, -+static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { -+ { -+ .pa_start = 0x48045000, -+ .pa_end = 0x480451ff, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { -- { .role = "dbclk", .clk = "gpio4_dbclk" }, -+/* l4_per -> dss_dsi2 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_dss_dsi2_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_dss_dsi2_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs), -+ .user = OCP_USER_MPU, - }; - --static struct omap_hwmod omap44xx_gpio4_hwmod = { -- .name = "gpio4", -- .class = &omap44xx_gpio_hwmod_class, -- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, -- .mpu_irqs = omap44xx_gpio4_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs), -- .main_clk = "gpio4_ick", -+/* dss_dsi2 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = { -+ &omap44xx_l3_main_2__dss_dsi2, -+ &omap44xx_l4_per__dss_dsi2, -+}; -+ -+static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { -+ .name = "dss_dsi2", -+ .class = &omap44xx_dsi_hwmod_class, -+ .mpu_irqs = omap44xx_dss_dsi2_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs), -+ .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs), -+ .main_clk = "dss_fck", - .prcm = { - .omap4 = { -- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, -+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - }, - }, -- .opt_clks = gpio4_opt_clks, -- .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), -- .dev_attr = &gpio_dev_attr, -- .slaves = omap44xx_gpio4_slaves, -- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), -+ .slaves = omap44xx_dss_dsi2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - --/* gpio5 */ --static struct omap_hwmod omap44xx_gpio5_hwmod; --static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { -- { .irq = 33 + OMAP44XX_IRQ_GIC_START }, -+/* -+ * 'hdmi' class -+ * hdmi controller -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_SOFTRESET), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ SIDLE_SMART_WKUP), -+ .sysc_fields = &omap_hwmod_sysc_type2, - }; - --static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { -+static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { -+ .name = "hdmi", -+ .sysc = &omap44xx_hdmi_sysc, -+}; -+ -+/* dss_hdmi */ -+static struct omap_hwmod omap44xx_dss_hdmi_hwmod; -+static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { -+ { .irq = 101 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { -+ { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { - { -- .pa_start = 0x4805b000, -- .pa_end = 0x4805b1ff, -+ .pa_start = 0x58006000, -+ .pa_end = 0x58006fff, - .flags = ADDR_TYPE_RT - }, - }; - --/* l4_per -> gpio5 */ --static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { -+/* l3_main_2 -> dss_hdmi */ -+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { -+ .master = &omap44xx_l3_main_2_hwmod, -+ .slave = &omap44xx_dss_hdmi_hwmod, -+ .clk = "l3_div_ck", -+ .addr = omap44xx_dss_hdmi_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs), -+ .user = OCP_USER_SDMA, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { -+ { -+ .pa_start = 0x48046000, -+ .pa_end = 0x48046fff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> dss_hdmi */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { - .master = &omap44xx_l4_per_hwmod, -- .slave = &omap44xx_gpio5_hwmod, -+ .slave = &omap44xx_dss_hdmi_hwmod, - .clk = "l4_div_ck", -- .addr = omap44xx_gpio5_addrs, -- .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs), -- .user = OCP_USER_MPU | OCP_USER_SDMA, -+ .addr = omap44xx_dss_hdmi_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_addrs), -+ .user = OCP_USER_MPU, - }; - --/* gpio5 slave ports */ --static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { -- &omap44xx_l4_per__gpio5, -+/* dss_hdmi slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = { -+ &omap44xx_l3_main_2__dss_hdmi, -+ &omap44xx_l4_per__dss_hdmi, - }; - --static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { -- { .role = "dbclk", .clk = "gpio5_dbclk" }, -+static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { -+ .name = "dss_hdmi", -+ .class = &omap44xx_hdmi_hwmod_class, -+ .mpu_irqs = omap44xx_dss_hdmi_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs), -+ .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs), -+ .main_clk = "dss_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_dss_hdmi_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - --static struct omap_hwmod omap44xx_gpio5_hwmod = { -- .name = "gpio5", -- .class = &omap44xx_gpio_hwmod_class, -- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, -- .mpu_irqs = omap44xx_gpio5_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs), -- .main_clk = "gpio5_ick", -+/* -+ * 'rfbi' class -+ * remote frame buffer interface -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { -+ .name = "rfbi", -+ .sysc = &omap44xx_rfbi_sysc, -+}; -+ -+/* dss_rfbi */ -+static struct omap_hwmod omap44xx_dss_rfbi_hwmod; -+static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { -+ { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { -+ { -+ .pa_start = 0x58002000, -+ .pa_end = 0x580020ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l3_main_2 -> dss_rfbi */ -+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { -+ .master = &omap44xx_l3_main_2_hwmod, -+ .slave = &omap44xx_dss_rfbi_hwmod, -+ .clk = "l3_div_ck", -+ .addr = omap44xx_dss_rfbi_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs), -+ .user = OCP_USER_SDMA, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { -+ { -+ .pa_start = 0x48042000, -+ .pa_end = 0x480420ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> dss_rfbi */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_dss_rfbi_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_dss_rfbi_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs), -+ .user = OCP_USER_MPU, -+}; -+ -+/* dss_rfbi slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = { -+ &omap44xx_l3_main_2__dss_rfbi, -+ &omap44xx_l4_per__dss_rfbi, -+}; -+ -+static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { -+ .name = "dss_rfbi", -+ .class = &omap44xx_rfbi_hwmod_class, -+ .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs), -+ .main_clk = "dss_fck", - .prcm = { - .omap4 = { -- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, -+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, - }, - }, -- .opt_clks = gpio5_opt_clks, -- .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), -- .dev_attr = &gpio_dev_attr, -- .slaves = omap44xx_gpio5_slaves, -- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), -+ .slaves = omap44xx_dss_rfbi_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - --/* gpio6 */ --static struct omap_hwmod omap44xx_gpio6_hwmod; --static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { -- { .irq = 34 + OMAP44XX_IRQ_GIC_START }, -+/* -+ * 'venc' class -+ * video encoder -+ */ -+ -+static struct omap_hwmod_class omap44xx_venc_hwmod_class = { -+ .name = "venc", -+}; -+ -+/* dss_venc */ -+static struct omap_hwmod omap44xx_dss_venc_hwmod; -+static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { -+ { -+ .pa_start = 0x58003000, -+ .pa_end = 0x580030ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l3_main_2 -> dss_venc */ -+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { -+ .master = &omap44xx_l3_main_2_hwmod, -+ .slave = &omap44xx_dss_venc_hwmod, -+ .clk = "l3_div_ck", -+ .addr = omap44xx_dss_venc_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs), -+ .user = OCP_USER_SDMA, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { -+ { -+ .pa_start = 0x48043000, -+ .pa_end = 0x480430ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> dss_venc */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_dss_venc_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_dss_venc_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs), -+ .user = OCP_USER_MPU, -+}; -+ -+/* dss_venc slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = { -+ &omap44xx_l3_main_2__dss_venc, -+ &omap44xx_l4_per__dss_venc, -+}; -+ -+static struct omap_hwmod omap44xx_dss_venc_hwmod = { -+ .name = "dss_venc", -+ .class = &omap44xx_venc_hwmod_class, -+ .main_clk = "dss_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_dss_venc_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'gpio' class -+ * general purpose io module -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0114, -+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | -+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | -+ SYSS_HAS_RESET_STATUS), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ SIDLE_SMART_WKUP), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { -+ .name = "gpio", -+ .sysc = &omap44xx_gpio_sysc, -+ .rev = 2, -+}; -+ -+/* gpio dev_attr */ -+static struct omap_gpio_dev_attr gpio_dev_attr = { -+ .bank_width = 32, -+ .dbck_flag = true, -+}; -+ -+/* gpio1 */ -+static struct omap_hwmod omap44xx_gpio1_hwmod; -+static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { -+ { .irq = 29 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { -+ { -+ .pa_start = 0x4a310000, -+ .pa_end = 0x4a3101ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_wkup -> gpio1 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { -+ .master = &omap44xx_l4_wkup_hwmod, -+ .slave = &omap44xx_gpio1_hwmod, -+ .clk = "l4_wkup_clk_mux_ck", -+ .addr = omap44xx_gpio1_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* gpio1 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { -+ &omap44xx_l4_wkup__gpio1, -+}; -+ -+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { -+ { .role = "dbclk", .clk = "gpio1_dbclk" }, -+}; -+ -+static struct omap_hwmod omap44xx_gpio1_hwmod = { -+ .name = "gpio1", -+ .class = &omap44xx_gpio_hwmod_class, -+ .mpu_irqs = omap44xx_gpio1_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs), -+ .main_clk = "gpio1_ick", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, -+ }, -+ }, -+ .opt_clks = gpio1_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), -+ .dev_attr = &gpio_dev_attr, -+ .slaves = omap44xx_gpio1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* gpio2 */ -+static struct omap_hwmod omap44xx_gpio2_hwmod; -+static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { -+ { .irq = 30 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { -+ { -+ .pa_start = 0x48055000, -+ .pa_end = 0x480551ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> gpio2 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_gpio2_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_gpio2_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* gpio2 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { -+ &omap44xx_l4_per__gpio2, -+}; -+ -+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { -+ { .role = "dbclk", .clk = "gpio2_dbclk" }, -+}; -+ -+static struct omap_hwmod omap44xx_gpio2_hwmod = { -+ .name = "gpio2", -+ .class = &omap44xx_gpio_hwmod_class, -+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, -+ .mpu_irqs = omap44xx_gpio2_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs), -+ .main_clk = "gpio2_ick", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, -+ }, -+ }, -+ .opt_clks = gpio2_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), -+ .dev_attr = &gpio_dev_attr, -+ .slaves = omap44xx_gpio2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* gpio3 */ -+static struct omap_hwmod omap44xx_gpio3_hwmod; -+static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { -+ { .irq = 31 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { -+ { -+ .pa_start = 0x48057000, -+ .pa_end = 0x480571ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> gpio3 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_gpio3_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_gpio3_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* gpio3 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { -+ &omap44xx_l4_per__gpio3, -+}; -+ -+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { -+ { .role = "dbclk", .clk = "gpio3_dbclk" }, -+}; -+ -+static struct omap_hwmod omap44xx_gpio3_hwmod = { -+ .name = "gpio3", -+ .class = &omap44xx_gpio_hwmod_class, -+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, -+ .mpu_irqs = omap44xx_gpio3_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs), -+ .main_clk = "gpio3_ick", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, -+ }, -+ }, -+ .opt_clks = gpio3_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), -+ .dev_attr = &gpio_dev_attr, -+ .slaves = omap44xx_gpio3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* gpio4 */ -+static struct omap_hwmod omap44xx_gpio4_hwmod; -+static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { -+ { .irq = 32 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { -+ { -+ .pa_start = 0x48059000, -+ .pa_end = 0x480591ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> gpio4 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_gpio4_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_gpio4_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* gpio4 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { -+ &omap44xx_l4_per__gpio4, -+}; -+ -+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { -+ { .role = "dbclk", .clk = "gpio4_dbclk" }, -+}; -+ -+static struct omap_hwmod omap44xx_gpio4_hwmod = { -+ .name = "gpio4", -+ .class = &omap44xx_gpio_hwmod_class, -+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, -+ .mpu_irqs = omap44xx_gpio4_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs), -+ .main_clk = "gpio4_ick", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, -+ }, -+ }, -+ .opt_clks = gpio4_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), -+ .dev_attr = &gpio_dev_attr, -+ .slaves = omap44xx_gpio4_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* gpio5 */ -+static struct omap_hwmod omap44xx_gpio5_hwmod; -+static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { -+ { .irq = 33 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { -+ { -+ .pa_start = 0x4805b000, -+ .pa_end = 0x4805b1ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> gpio5 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_gpio5_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_gpio5_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* gpio5 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { -+ &omap44xx_l4_per__gpio5, -+}; -+ -+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { -+ { .role = "dbclk", .clk = "gpio5_dbclk" }, -+}; -+ -+static struct omap_hwmod omap44xx_gpio5_hwmod = { -+ .name = "gpio5", -+ .class = &omap44xx_gpio_hwmod_class, -+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, -+ .mpu_irqs = omap44xx_gpio5_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs), -+ .main_clk = "gpio5_ick", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, -+ }, -+ }, -+ .opt_clks = gpio5_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), -+ .dev_attr = &gpio_dev_attr, -+ .slaves = omap44xx_gpio5_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* gpio6 */ -+static struct omap_hwmod omap44xx_gpio6_hwmod; -+static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { -+ { .irq = 34 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { -+ { -+ .pa_start = 0x4805d000, -+ .pa_end = 0x4805d1ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> gpio6 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_gpio6_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_gpio6_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* gpio6 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { -+ &omap44xx_l4_per__gpio6, -+}; -+ -+static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { -+ { .role = "dbclk", .clk = "gpio6_dbclk" }, -+}; -+ -+static struct omap_hwmod omap44xx_gpio6_hwmod = { -+ .name = "gpio6", -+ .class = &omap44xx_gpio_hwmod_class, -+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, -+ .mpu_irqs = omap44xx_gpio6_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs), -+ .main_clk = "gpio6_ick", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, -+ }, -+ }, -+ .opt_clks = gpio6_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), -+ .dev_attr = &gpio_dev_attr, -+ .slaves = omap44xx_gpio6_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'hsi' class -+ * mipi high-speed synchronous serial interface (multichannel and full-duplex -+ * serial if) -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | -+ SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | -+ MSTANDBY_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { -+ .name = "hsi", -+ .sysc = &omap44xx_hsi_sysc, -+}; -+ -+/* hsi */ -+static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { -+ { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, -+ { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, -+ { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+/* hsi master ports */ -+static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = { -+ &omap44xx_hsi__l3_main_2, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { -+ { -+ .pa_start = 0x4a058000, -+ .pa_end = 0x4a05bfff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_cfg -> hsi */ -+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { -+ .master = &omap44xx_l4_cfg_hwmod, -+ .slave = &omap44xx_hsi_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_hsi_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_hsi_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* hsi slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = { -+ &omap44xx_l4_cfg__hsi, -+}; -+ -+static struct omap_hwmod omap44xx_hsi_hwmod = { -+ .name = "hsi", -+ .class = &omap44xx_hsi_hwmod_class, -+ .mpu_irqs = omap44xx_hsi_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs), -+ .main_clk = "hsi_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_hsi_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves), -+ .masters = omap44xx_hsi_masters, -+ .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'i2c' class -+ * multimaster high-speed i2c controller -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0090, -+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ SIDLE_SMART_WKUP), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { -+ .name = "i2c", -+ .sysc = &omap44xx_i2c_sysc, -+}; -+ -+/* i2c1 */ -+static struct omap_hwmod omap44xx_i2c1_hwmod; -+static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { -+ { .irq = 56 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { -+ { -+ .pa_start = 0x48070000, -+ .pa_end = 0x480700ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> i2c1 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_i2c1_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_i2c1_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* i2c1 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { -+ &omap44xx_l4_per__i2c1, -+}; -+ -+static struct omap_hwmod omap44xx_i2c1_hwmod = { -+ .name = "i2c1", -+ .class = &omap44xx_i2c_hwmod_class, -+ .flags = HWMOD_INIT_NO_RESET, -+ .mpu_irqs = omap44xx_i2c1_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs), -+ .sdma_reqs = omap44xx_i2c1_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs), -+ .main_clk = "i2c1_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_i2c1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* i2c2 */ -+static struct omap_hwmod omap44xx_i2c2_hwmod; -+static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { -+ { .irq = 57 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { -+ { -+ .pa_start = 0x48072000, -+ .pa_end = 0x480720ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> i2c2 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_i2c2_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_i2c2_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* i2c2 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { -+ &omap44xx_l4_per__i2c2, -+}; -+ -+static struct omap_hwmod omap44xx_i2c2_hwmod = { -+ .name = "i2c2", -+ .class = &omap44xx_i2c_hwmod_class, -+ .flags = HWMOD_INIT_NO_RESET, -+ .mpu_irqs = omap44xx_i2c2_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs), -+ .sdma_reqs = omap44xx_i2c2_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs), -+ .main_clk = "i2c2_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_i2c2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* i2c3 */ -+static struct omap_hwmod omap44xx_i2c3_hwmod; -+static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { -+ { .irq = 61 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { -+ { -+ .pa_start = 0x48060000, -+ .pa_end = 0x480600ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> i2c3 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_i2c3_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_i2c3_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* i2c3 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { -+ &omap44xx_l4_per__i2c3, -+}; -+ -+static struct omap_hwmod omap44xx_i2c3_hwmod = { -+ .name = "i2c3", -+ .class = &omap44xx_i2c_hwmod_class, -+ .flags = HWMOD_INIT_NO_RESET, -+ .mpu_irqs = omap44xx_i2c3_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs), -+ .sdma_reqs = omap44xx_i2c3_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs), -+ .main_clk = "i2c3_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_i2c3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* i2c4 */ -+static struct omap_hwmod omap44xx_i2c4_hwmod; -+static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { -+ { .irq = 62 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { -+ { -+ .pa_start = 0x48350000, -+ .pa_end = 0x483500ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> i2c4 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_i2c4_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_i2c4_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* i2c4 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { -+ &omap44xx_l4_per__i2c4, -+}; -+ -+static struct omap_hwmod omap44xx_i2c4_hwmod = { -+ .name = "i2c4", -+ .class = &omap44xx_i2c_hwmod_class, -+ .flags = HWMOD_INIT_NO_RESET, -+ .mpu_irqs = omap44xx_i2c4_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs), -+ .sdma_reqs = omap44xx_i2c4_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs), -+ .main_clk = "i2c4_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_i2c4_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'ipu' class -+ * imaging processor unit -+ */ -+ -+static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { -+ .name = "ipu", -+}; -+ -+/* ipu */ -+static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { -+ { .irq = 100 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { -+ { .name = "cpu0", .rst_shift = 0 }, -+}; -+ -+static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = { -+ { .name = "cpu1", .rst_shift = 1 }, -+}; -+ -+static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { -+ { .name = "mmu_cache", .rst_shift = 2 }, -+}; -+ -+/* ipu master ports */ -+static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = { -+ &omap44xx_ipu__l3_main_2, -+}; -+ -+/* l3_main_2 -> ipu */ -+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { -+ .master = &omap44xx_l3_main_2_hwmod, -+ .slave = &omap44xx_ipu_hwmod, -+ .clk = "l3_div_ck", -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* ipu slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = { -+ &omap44xx_l3_main_2__ipu, -+}; -+ -+/* Pseudo hwmod for reset control purpose only */ -+static struct omap_hwmod omap44xx_ipu_c0_hwmod = { -+ .name = "ipu_c0", -+ .class = &omap44xx_ipu_hwmod_class, -+ .flags = HWMOD_INIT_NO_RESET, -+ .rst_lines = omap44xx_ipu_c0_resets, -+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets), -+ .prcm = { -+ .omap4 = { -+ .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, -+ }, -+ }, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* Pseudo hwmod for reset control purpose only */ -+static struct omap_hwmod omap44xx_ipu_c1_hwmod = { -+ .name = "ipu_c1", -+ .class = &omap44xx_ipu_hwmod_class, -+ .flags = HWMOD_INIT_NO_RESET, -+ .rst_lines = omap44xx_ipu_c1_resets, -+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets), -+ .prcm = { -+ .omap4 = { -+ .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, -+ }, -+ }, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+static struct omap_hwmod omap44xx_ipu_hwmod = { -+ .name = "ipu", -+ .class = &omap44xx_ipu_hwmod_class, -+ .mpu_irqs = omap44xx_ipu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs), -+ .rst_lines = omap44xx_ipu_resets, -+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), -+ .main_clk = "ipu_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, -+ .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, -+ }, -+ }, -+ .slaves = omap44xx_ipu_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves), -+ .masters = omap44xx_ipu_masters, -+ .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'iss' class -+ * external images sensor pixel data processor -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | -+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | -+ MSTANDBY_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type2, -+}; -+ -+static struct omap_hwmod_class omap44xx_iss_hwmod_class = { -+ .name = "iss", -+ .sysc = &omap44xx_iss_sysc, -+}; -+ -+/* iss */ -+static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { -+ { .irq = 24 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { -+ { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, -+ { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, -+ { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, -+ { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+/* iss master ports */ -+static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = { -+ &omap44xx_iss__l3_main_2, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { -+ { -+ .pa_start = 0x52000000, -+ .pa_end = 0x520000ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l3_main_2 -> iss */ -+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { -+ .master = &omap44xx_l3_main_2_hwmod, -+ .slave = &omap44xx_iss_hwmod, -+ .clk = "l3_div_ck", -+ .addr = omap44xx_iss_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_iss_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* iss slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = { -+ &omap44xx_l3_main_2__iss, -+}; -+ -+static struct omap_hwmod_opt_clk iss_opt_clks[] = { -+ { .role = "ctrlclk", .clk = "iss_ctrlclk" }, -+}; -+ -+static struct omap_hwmod omap44xx_iss_hwmod = { -+ .name = "iss", -+ .class = &omap44xx_iss_hwmod_class, -+ .mpu_irqs = omap44xx_iss_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs), -+ .sdma_reqs = omap44xx_iss_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs), -+ .main_clk = "iss_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, -+ }, -+ }, -+ .opt_clks = iss_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), -+ .slaves = omap44xx_iss_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves), -+ .masters = omap44xx_iss_masters, -+ .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'iva' class -+ * multi-standard video encoder/decoder hardware accelerator -+ */ -+ -+static struct omap_hwmod_class omap44xx_iva_hwmod_class = { -+ .name = "iva", -+}; -+ -+/* iva */ -+static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { -+ { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, -+ { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, -+ { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { -+ { .name = "logic", .rst_shift = 2 }, -+}; -+ -+static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = { -+ { .name = "seq0", .rst_shift = 0 }, -+}; -+ -+static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = { -+ { .name = "seq1", .rst_shift = 1 }, -+}; -+ -+/* iva master ports */ -+static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = { -+ &omap44xx_iva__l3_main_2, -+ &omap44xx_iva__l3_instr, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { -+ { -+ .pa_start = 0x5a000000, -+ .pa_end = 0x5a07ffff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l3_main_2 -> iva */ -+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { -+ .master = &omap44xx_l3_main_2_hwmod, -+ .slave = &omap44xx_iva_hwmod, -+ .clk = "l3_div_ck", -+ .addr = omap44xx_iva_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs), -+ .user = OCP_USER_MPU, -+}; -+ -+/* iva slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = { -+ &omap44xx_dsp__iva, -+ &omap44xx_l3_main_2__iva, -+}; -+ -+/* Pseudo hwmod for reset control purpose only */ -+static struct omap_hwmod omap44xx_iva_seq0_hwmod = { -+ .name = "iva_seq0", -+ .class = &omap44xx_iva_hwmod_class, -+ .flags = HWMOD_INIT_NO_RESET, -+ .rst_lines = omap44xx_iva_seq0_resets, -+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets), -+ .prcm = { -+ .omap4 = { -+ .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, -+ }, -+ }, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* Pseudo hwmod for reset control purpose only */ -+static struct omap_hwmod omap44xx_iva_seq1_hwmod = { -+ .name = "iva_seq1", -+ .class = &omap44xx_iva_hwmod_class, -+ .flags = HWMOD_INIT_NO_RESET, -+ .rst_lines = omap44xx_iva_seq1_resets, -+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets), -+ .prcm = { -+ .omap4 = { -+ .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, -+ }, -+ }, -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+static struct omap_hwmod omap44xx_iva_hwmod = { -+ .name = "iva", -+ .class = &omap44xx_iva_hwmod_class, -+ .mpu_irqs = omap44xx_iva_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs), -+ .rst_lines = omap44xx_iva_resets, -+ .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), -+ .main_clk = "iva_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, -+ .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, -+ }, -+ }, -+ .slaves = omap44xx_iva_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves), -+ .masters = omap44xx_iva_masters, -+ .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'kbd' class -+ * keyboard controller -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | -+ SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | -+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | -+ SYSS_HAS_RESET_STATUS), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { -+ .name = "kbd", -+ .sysc = &omap44xx_kbd_sysc, -+}; -+ -+/* kbd */ -+static struct omap_hwmod omap44xx_kbd_hwmod; -+static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { -+ { .irq = 120 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { -+ { -+ .pa_start = 0x4a31c000, -+ .pa_end = 0x4a31c07f, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_wkup -> kbd */ -+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { -+ .master = &omap44xx_l4_wkup_hwmod, -+ .slave = &omap44xx_kbd_hwmod, -+ .clk = "l4_wkup_clk_mux_ck", -+ .addr = omap44xx_kbd_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_kbd_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* kbd slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = { -+ &omap44xx_l4_wkup__kbd, -+}; -+ -+static struct omap_hwmod omap44xx_kbd_hwmod = { -+ .name = "kbd", -+ .class = &omap44xx_kbd_hwmod_class, -+ .mpu_irqs = omap44xx_kbd_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs), -+ .main_clk = "kbd_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_kbd_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'mailbox' class -+ * mailbox module allowing communication between the on-chip processors using a -+ * queued mailbox-interrupt mechanism. -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_SOFTRESET), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type2, -+}; -+ -+static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { -+ .name = "mailbox", -+ .sysc = &omap44xx_mailbox_sysc, -+}; -+ -+/* mailbox */ -+static struct omap_hwmod omap44xx_mailbox_hwmod; -+static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { -+ { .irq = 26 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { -+ { -+ .pa_start = 0x4a0f4000, -+ .pa_end = 0x4a0f41ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_cfg -> mailbox */ -+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { -+ .master = &omap44xx_l4_cfg_hwmod, -+ .slave = &omap44xx_mailbox_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_mailbox_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mailbox slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = { -+ &omap44xx_l4_cfg__mailbox, -+}; -+ -+static struct omap_hwmod omap44xx_mailbox_hwmod = { -+ .name = "mailbox", -+ .class = &omap44xx_mailbox_hwmod_class, -+ .mpu_irqs = omap44xx_mailbox_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs), -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_mailbox_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'mcbsp' class -+ * multi channel buffered serial port controller -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { -+ .sysc_offs = 0x008c, -+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | -+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { -+ .name = "mcbsp", -+ .sysc = &omap44xx_mcbsp_sysc, -+ .rev = MCBSP_CONFIG_TYPE4, -+}; -+ -+/* mcbsp1 */ -+static struct omap_hwmod omap44xx_mcbsp1_hwmod; -+static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { -+ { .irq = 17 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { -+ { -+ .name = "mpu", -+ .pa_start = 0x40122000, -+ .pa_end = 0x401220ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_abe -> mcbsp1 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_mcbsp1_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_mcbsp1_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_addrs), -+ .user = OCP_USER_MPU, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { -+ { -+ .name = "dma", -+ .pa_start = 0x49022000, -+ .pa_end = 0x490220ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_abe -> mcbsp1 (dma) */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_mcbsp1_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_mcbsp1_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs), -+ .user = OCP_USER_SDMA, -+}; -+ -+/* mcbsp1 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = { -+ &omap44xx_l4_abe__mcbsp1, -+ &omap44xx_l4_abe__mcbsp1_dma, -+}; -+ -+static struct omap_hwmod omap44xx_mcbsp1_hwmod = { -+ .name = "mcbsp1", -+ .class = &omap44xx_mcbsp_hwmod_class, -+ .mpu_irqs = omap44xx_mcbsp1_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs), -+ .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs), -+ .main_clk = "mcbsp1_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_mcbsp1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* mcbsp2 */ -+static struct omap_hwmod omap44xx_mcbsp2_hwmod; -+static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { -+ { .irq = 22 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { -+ { -+ .name = "mpu", -+ .pa_start = 0x40124000, -+ .pa_end = 0x401240ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_abe -> mcbsp2 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_mcbsp2_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_mcbsp2_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_addrs), -+ .user = OCP_USER_MPU, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { -+ { -+ .name = "dma", -+ .pa_start = 0x49024000, -+ .pa_end = 0x490240ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_abe -> mcbsp2 (dma) */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_mcbsp2_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_mcbsp2_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs), -+ .user = OCP_USER_SDMA, -+}; -+ -+/* mcbsp2 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = { -+ &omap44xx_l4_abe__mcbsp2, -+ &omap44xx_l4_abe__mcbsp2_dma, -+}; -+ -+static struct omap_hwmod omap44xx_mcbsp2_hwmod = { -+ .name = "mcbsp2", -+ .class = &omap44xx_mcbsp_hwmod_class, -+ .mpu_irqs = omap44xx_mcbsp2_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs), -+ .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs), -+ .main_clk = "mcbsp2_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_mcbsp2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* mcbsp3 */ -+static struct omap_hwmod omap44xx_mcbsp3_hwmod; -+static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { -+ { .irq = 23 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { -+ { -+ .name = "mpu", -+ .pa_start = 0x40126000, -+ .pa_end = 0x401260ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_abe -> mcbsp3 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_mcbsp3_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_mcbsp3_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_addrs), -+ .user = OCP_USER_MPU, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { -+ { -+ .name = "dma", -+ .pa_start = 0x49026000, -+ .pa_end = 0x490260ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_abe -> mcbsp3 (dma) */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_mcbsp3_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_mcbsp3_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs), -+ .user = OCP_USER_SDMA, -+}; -+ -+/* mcbsp3 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = { -+ &omap44xx_l4_abe__mcbsp3, -+ &omap44xx_l4_abe__mcbsp3_dma, -+}; -+ -+static struct omap_hwmod omap44xx_mcbsp3_hwmod = { -+ .name = "mcbsp3", -+ .class = &omap44xx_mcbsp_hwmod_class, -+ .mpu_irqs = omap44xx_mcbsp3_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs), -+ .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs), -+ .main_clk = "mcbsp3_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_mcbsp3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* mcbsp4 */ -+static struct omap_hwmod omap44xx_mcbsp4_hwmod; -+static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { -+ { .irq = 16 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { -+ { -+ .pa_start = 0x48096000, -+ .pa_end = 0x480960ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> mcbsp4 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_mcbsp4_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_mcbsp4_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp4_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mcbsp4 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = { -+ &omap44xx_l4_per__mcbsp4, -+}; -+ -+static struct omap_hwmod omap44xx_mcbsp4_hwmod = { -+ .name = "mcbsp4", -+ .class = &omap44xx_mcbsp_hwmod_class, -+ .mpu_irqs = omap44xx_mcbsp4_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs), -+ .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs), -+ .main_clk = "mcbsp4_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_mcbsp4_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'mcpdm' class -+ * multi channel pdm controller (proprietary interface with phoenix power -+ * ic) -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | -+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ SIDLE_SMART_WKUP), -+ .sysc_fields = &omap_hwmod_sysc_type2, -+}; -+ -+static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { -+ .name = "mcpdm", -+ .sysc = &omap44xx_mcpdm_sysc, -+}; -+ -+/* mcpdm */ -+static struct omap_hwmod omap44xx_mcpdm_hwmod; -+static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { -+ { .irq = 112 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { -+ { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, -+ { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { -+ { -+ .pa_start = 0x40132000, -+ .pa_end = 0x4013207f, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_abe -> mcpdm */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_mcpdm_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_mcpdm_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_addrs), -+ .user = OCP_USER_MPU, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { -+ { -+ .pa_start = 0x49032000, -+ .pa_end = 0x4903207f, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_abe -> mcpdm (dma) */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_mcpdm_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_mcpdm_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs), -+ .user = OCP_USER_SDMA, -+}; -+ -+/* mcpdm slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = { -+ &omap44xx_l4_abe__mcpdm, -+ &omap44xx_l4_abe__mcpdm_dma, -+}; -+ -+static struct omap_hwmod omap44xx_mcpdm_hwmod = { -+ .name = "mcpdm", -+ .class = &omap44xx_mcpdm_hwmod_class, -+ .mpu_irqs = omap44xx_mcpdm_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs), -+ .sdma_reqs = omap44xx_mcpdm_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs), -+ .main_clk = "mcpdm_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_mcpdm_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'mcspi' class -+ * multichannel serial port interface (mcspi) / master/slave synchronous serial -+ * bus -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | -+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ SIDLE_SMART_WKUP), -+ .sysc_fields = &omap_hwmod_sysc_type2, -+}; -+ -+static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { -+ .name = "mcspi", -+ .sysc = &omap44xx_mcspi_sysc, -+ .rev = OMAP4_MCSPI_REV, -+}; -+ -+/* mcspi1 */ -+static struct omap_hwmod omap44xx_mcspi1_hwmod; -+static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { -+ { .irq = 65 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { -+ { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, -+ { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, -+ { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, -+ { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { -+ { -+ .pa_start = 0x48098000, -+ .pa_end = 0x480981ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> mcspi1 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_mcspi1_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_mcspi1_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mcspi1 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = { -+ &omap44xx_l4_per__mcspi1, -+}; -+ -+/* mcspi1 dev_attr */ -+static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { -+ .num_chipselect = 4, -+}; -+ -+static struct omap_hwmod omap44xx_mcspi1_hwmod = { -+ .name = "mcspi1", -+ .class = &omap44xx_mcspi_hwmod_class, -+ .mpu_irqs = omap44xx_mcspi1_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs), -+ .sdma_reqs = omap44xx_mcspi1_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs), -+ .main_clk = "mcspi1_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, -+ }, -+ }, -+ .dev_attr = &mcspi1_dev_attr, -+ .slaves = omap44xx_mcspi1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* mcspi2 */ -+static struct omap_hwmod omap44xx_mcspi2_hwmod; -+static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { -+ { .irq = 66 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { -+ { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, -+ { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { -+ { -+ .pa_start = 0x4809a000, -+ .pa_end = 0x4809a1ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> mcspi2 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_mcspi2_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_mcspi2_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mcspi2 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = { -+ &omap44xx_l4_per__mcspi2, -+}; -+ -+/* mcspi2 dev_attr */ -+static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { -+ .num_chipselect = 2, -+}; -+ -+static struct omap_hwmod omap44xx_mcspi2_hwmod = { -+ .name = "mcspi2", -+ .class = &omap44xx_mcspi_hwmod_class, -+ .mpu_irqs = omap44xx_mcspi2_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs), -+ .sdma_reqs = omap44xx_mcspi2_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs), -+ .main_clk = "mcspi2_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, -+ }, -+ }, -+ .dev_attr = &mcspi2_dev_attr, -+ .slaves = omap44xx_mcspi2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* mcspi3 */ -+static struct omap_hwmod omap44xx_mcspi3_hwmod; -+static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { -+ { .irq = 91 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { -+ { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, -+ { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { -+ { -+ .pa_start = 0x480b8000, -+ .pa_end = 0x480b81ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> mcspi3 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_mcspi3_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_mcspi3_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mcspi3 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = { -+ &omap44xx_l4_per__mcspi3, -+}; -+ -+/* mcspi3 dev_attr */ -+static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { -+ .num_chipselect = 2, -+}; -+ -+static struct omap_hwmod omap44xx_mcspi3_hwmod = { -+ .name = "mcspi3", -+ .class = &omap44xx_mcspi_hwmod_class, -+ .mpu_irqs = omap44xx_mcspi3_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs), -+ .sdma_reqs = omap44xx_mcspi3_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs), -+ .main_clk = "mcspi3_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, -+ }, -+ }, -+ .dev_attr = &mcspi3_dev_attr, -+ .slaves = omap44xx_mcspi3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* mcspi4 */ -+static struct omap_hwmod omap44xx_mcspi4_hwmod; -+static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { -+ { .irq = 48 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { -+ { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { -+ { -+ .pa_start = 0x480ba000, -+ .pa_end = 0x480ba1ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> mcspi4 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_mcspi4_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_mcspi4_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mcspi4 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = { -+ &omap44xx_l4_per__mcspi4, -+}; -+ -+/* mcspi4 dev_attr */ -+static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { -+ .num_chipselect = 1, -+}; -+ -+static struct omap_hwmod omap44xx_mcspi4_hwmod = { -+ .name = "mcspi4", -+ .class = &omap44xx_mcspi_hwmod_class, -+ .mpu_irqs = omap44xx_mcspi4_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs), -+ .sdma_reqs = omap44xx_mcspi4_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs), -+ .main_clk = "mcspi4_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, -+ }, -+ }, -+ .dev_attr = &mcspi4_dev_attr, -+ .slaves = omap44xx_mcspi4_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'mmc' class -+ * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | -+ SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_SOFTRESET), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | -+ MSTANDBY_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type2, -+}; -+ -+static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { -+ .name = "mmc", -+ .sysc = &omap44xx_mmc_sysc, -+}; -+ -+/* mmc1 */ -+ -+static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { -+ { .irq = 83 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+/* mmc1 master ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = { -+ &omap44xx_mmc1__l3_main_1, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { -+ { -+ .pa_start = 0x4809c000, -+ .pa_end = 0x4809c3ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> mmc1 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_mmc1_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_mmc1_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mmc1_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mmc1 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = { -+ &omap44xx_l4_per__mmc1, -+}; -+ -+/* mmc1 dev_attr */ -+static struct omap_mmc_dev_attr mmc1_dev_attr = { -+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, -+}; -+ -+static struct omap_hwmod omap44xx_mmc1_hwmod = { -+ .name = "mmc1", -+ .class = &omap44xx_mmc_hwmod_class, -+ .mpu_irqs = omap44xx_mmc1_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs), -+ .sdma_reqs = omap44xx_mmc1_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs), -+ .main_clk = "mmc1_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, -+ }, -+ }, -+ .dev_attr = &mmc1_dev_attr, -+ .slaves = omap44xx_mmc1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves), -+ .masters = omap44xx_mmc1_masters, -+ .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* mmc2 */ -+static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { -+ { .irq = 86 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+/* mmc2 master ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = { -+ &omap44xx_mmc2__l3_main_1, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { -+ { -+ .pa_start = 0x480b4000, -+ .pa_end = 0x480b43ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> mmc2 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_mmc2_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_mmc2_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mmc2_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mmc2 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = { -+ &omap44xx_l4_per__mmc2, -+}; -+ -+static struct omap_hwmod omap44xx_mmc2_hwmod = { -+ .name = "mmc2", -+ .class = &omap44xx_mmc_hwmod_class, -+ .mpu_irqs = omap44xx_mmc2_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs), -+ .sdma_reqs = omap44xx_mmc2_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs), -+ .main_clk = "mmc2_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_mmc2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves), -+ .masters = omap44xx_mmc2_masters, -+ .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* mmc3 */ -+static struct omap_hwmod omap44xx_mmc3_hwmod; -+static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { -+ { .irq = 94 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { -+ { -+ .pa_start = 0x480ad000, -+ .pa_end = 0x480ad3ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> mmc3 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_mmc3_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_mmc3_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mmc3_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mmc3 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = { -+ &omap44xx_l4_per__mmc3, -+}; -+ -+static struct omap_hwmod omap44xx_mmc3_hwmod = { -+ .name = "mmc3", -+ .class = &omap44xx_mmc_hwmod_class, -+ .mpu_irqs = omap44xx_mmc3_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs), -+ .sdma_reqs = omap44xx_mmc3_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs), -+ .main_clk = "mmc3_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_mmc3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* mmc4 */ -+static struct omap_hwmod omap44xx_mmc4_hwmod; -+static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { -+ { .irq = 96 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { -+ { -+ .pa_start = 0x480d1000, -+ .pa_end = 0x480d13ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> mmc4 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_mmc4_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_mmc4_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mmc4_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mmc4 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = { -+ &omap44xx_l4_per__mmc4, -+}; -+ -+static struct omap_hwmod omap44xx_mmc4_hwmod = { -+ .name = "mmc4", -+ .class = &omap44xx_mmc_hwmod_class, -+ .mpu_irqs = omap44xx_mmc4_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs), -+ .sdma_reqs = omap44xx_mmc4_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs), -+ .main_clk = "mmc4_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_mmc4_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* mmc5 */ -+static struct omap_hwmod omap44xx_mmc5_hwmod; -+static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { -+ { .irq = 59 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { -+ { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, -+ { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { -+ { -+ .pa_start = 0x480d5000, -+ .pa_end = 0x480d53ff, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_per -> mmc5 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_mmc5_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_mmc5_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_mmc5_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* mmc5 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = { -+ &omap44xx_l4_per__mmc5, -+}; -+ -+static struct omap_hwmod omap44xx_mmc5_hwmod = { -+ .name = "mmc5", -+ .class = &omap44xx_mmc_hwmod_class, -+ .mpu_irqs = omap44xx_mmc5_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs), -+ .sdma_reqs = omap44xx_mmc5_sdma_reqs, -+ .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs), -+ .main_clk = "mmc5_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_mmc5_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'mpu' class -+ * mpu sub-system -+ */ -+ -+static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { -+ .name = "mpu", -+}; -+ -+/* mpu */ -+static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { -+ { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, -+ { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, -+ { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+/* mpu master ports */ -+static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { -+ &omap44xx_mpu__l3_main_1, -+ &omap44xx_mpu__l4_abe, -+ &omap44xx_mpu__dmm, -+}; -+ -+static struct omap_hwmod omap44xx_mpu_hwmod = { -+ .name = "mpu", -+ .class = &omap44xx_mpu_hwmod_class, -+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), -+ .mpu_irqs = omap44xx_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs), -+ .main_clk = "dpll_mpu_m2_ck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL, -+ }, -+ }, -+ .masters = omap44xx_mpu_masters, -+ .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'smartreflex' class -+ * smartreflex module (monitor silicon performance and outputs a measure of -+ * performance error) -+ */ -+ -+/* The IP is not compliant to type1 / type2 scheme */ -+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { -+ .sidle_shift = 24, -+ .enwkup_shift = 26, -+}; -+ -+static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { -+ .sysc_offs = 0x0038, -+ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ SIDLE_SMART_WKUP), -+ .sysc_fields = &omap_hwmod_sysc_type_smartreflex, -+}; -+ -+static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { -+ .name = "smartreflex", -+ .sysc = &omap44xx_smartreflex_sysc, -+ .rev = 2, -+}; -+ -+/* smartreflex_core */ -+static struct omap_hwmod omap44xx_smartreflex_core_hwmod; -+static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { -+ { .irq = 19 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { -+ { -+ .pa_start = 0x4a0dd000, -+ .pa_end = 0x4a0dd03f, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_cfg -> smartreflex_core */ -+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { -+ .master = &omap44xx_l4_cfg_hwmod, -+ .slave = &omap44xx_smartreflex_core_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_smartreflex_core_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* smartreflex_core slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = { -+ &omap44xx_l4_cfg__smartreflex_core, -+}; -+ -+static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { -+ .name = "smartreflex_core", -+ .class = &omap44xx_smartreflex_hwmod_class, -+ .mpu_irqs = omap44xx_smartreflex_core_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs), -+ .main_clk = "smartreflex_core_fck", -+ .vdd_name = "core", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_smartreflex_core_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* smartreflex_iva */ -+static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; -+static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { -+ { .irq = 102 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { -+ { -+ .pa_start = 0x4a0db000, -+ .pa_end = 0x4a0db03f, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_cfg -> smartreflex_iva */ -+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { -+ .master = &omap44xx_l4_cfg_hwmod, -+ .slave = &omap44xx_smartreflex_iva_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_smartreflex_iva_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* smartreflex_iva slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = { -+ &omap44xx_l4_cfg__smartreflex_iva, -+}; -+ -+static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { -+ .name = "smartreflex_iva", -+ .class = &omap44xx_smartreflex_hwmod_class, -+ .mpu_irqs = omap44xx_smartreflex_iva_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs), -+ .main_clk = "smartreflex_iva_fck", -+ .vdd_name = "iva", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_smartreflex_iva_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* smartreflex_mpu */ -+static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; -+static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { -+ { .irq = 18 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { -+ { -+ .pa_start = 0x4a0d9000, -+ .pa_end = 0x4a0d903f, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_cfg -> smartreflex_mpu */ -+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { -+ .master = &omap44xx_l4_cfg_hwmod, -+ .slave = &omap44xx_smartreflex_mpu_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_smartreflex_mpu_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* smartreflex_mpu slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = { -+ &omap44xx_l4_cfg__smartreflex_mpu, -+}; -+ -+static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { -+ .name = "smartreflex_mpu", -+ .class = &omap44xx_smartreflex_hwmod_class, -+ .mpu_irqs = omap44xx_smartreflex_mpu_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs), -+ .main_clk = "smartreflex_mpu_fck", -+ .vdd_name = "mpu", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_smartreflex_mpu_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* -+ * 'spinlock' class -+ * spinlock provides hardware assistance for synchronizing the processes -+ * running on multiple processors -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .syss_offs = 0x0014, -+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | -+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ SIDLE_SMART_WKUP), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { -+ .name = "spinlock", -+ .sysc = &omap44xx_spinlock_sysc, - }; - --static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { -+/* spinlock */ -+static struct omap_hwmod omap44xx_spinlock_hwmod; -+static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { - { -- .pa_start = 0x4805d000, -- .pa_end = 0x4805d1ff, -+ .pa_start = 0x4a0f6000, -+ .pa_end = 0x4a0f6fff, - .flags = ADDR_TYPE_RT - }, - }; - --/* l4_per -> gpio6 */ --static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { -- .master = &omap44xx_l4_per_hwmod, -- .slave = &omap44xx_gpio6_hwmod, -+/* l4_cfg -> spinlock */ -+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { -+ .master = &omap44xx_l4_cfg_hwmod, -+ .slave = &omap44xx_spinlock_hwmod, - .clk = "l4_div_ck", -- .addr = omap44xx_gpio6_addrs, -- .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs), -+ .addr = omap44xx_spinlock_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --/* gpio6 slave ports */ --static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { -- &omap44xx_l4_per__gpio6, --}; -- --static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { -- { .role = "dbclk", .clk = "gpio6_dbclk" }, -+/* spinlock slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = { -+ &omap44xx_l4_cfg__spinlock, - }; - --static struct omap_hwmod omap44xx_gpio6_hwmod = { -- .name = "gpio6", -- .class = &omap44xx_gpio_hwmod_class, -- .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, -- .mpu_irqs = omap44xx_gpio6_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs), -- .main_clk = "gpio6_ick", -+static struct omap_hwmod omap44xx_spinlock_hwmod = { -+ .name = "spinlock", -+ .class = &omap44xx_spinlock_hwmod_class, - .prcm = { - .omap4 = { -- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, -+ .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL, - }, - }, -- .opt_clks = gpio6_opt_clks, -- .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), -- .dev_attr = &gpio_dev_attr, -- .slaves = omap44xx_gpio6_slaves, -- .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves), -+ .slaves = omap44xx_spinlock_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - - /* -- * 'i2c' class -- * multimaster high-speed i2c controller -+ * 'timer' class -+ * general purpose timer module with accurate 1ms tick -+ * This class contains several variants: ['timer_1ms', 'timer'] - */ - --static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { -+static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { -+ .rev_offs = 0x0000, - .sysc_offs = 0x0010, -- .syss_offs = 0x0090, -+ .syss_offs = 0x0014, - .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | -- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | -- SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), -- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -- SIDLE_SMART_WKUP), -+ SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | -+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | -+ SYSS_HAS_RESET_STATUS), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), - .sysc_fields = &omap_hwmod_sysc_type1, - }; - --static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { -- .name = "i2c", -- .sysc = &omap44xx_i2c_sysc, -+static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { -+ .name = "timer", -+ .sysc = &omap44xx_timer_1ms_sysc, - }; - --/* i2c1 */ --static struct omap_hwmod omap44xx_i2c1_hwmod; --static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { -- { .irq = 56 + OMAP44XX_IRQ_GIC_START }, -+static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { -+ .rev_offs = 0x0000, -+ .sysc_offs = 0x0010, -+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | -+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ SIDLE_SMART_WKUP), -+ .sysc_fields = &omap_hwmod_sysc_type2, - }; - --static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { -- { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, -- { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, -+static struct omap_hwmod_class omap44xx_timer_hwmod_class = { -+ .name = "timer", -+ .sysc = &omap44xx_timer_sysc, - }; - --static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { -+/* timer1 */ -+static struct omap_hwmod omap44xx_timer1_hwmod; -+static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { -+ { .irq = 37 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { - { -- .pa_start = 0x48070000, -- .pa_end = 0x480700ff, -+ .pa_start = 0x4a318000, -+ .pa_end = 0x4a31807f, - .flags = ADDR_TYPE_RT - }, - }; - --/* l4_per -> i2c1 */ --static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { -- .master = &omap44xx_l4_per_hwmod, -- .slave = &omap44xx_i2c1_hwmod, -- .clk = "l4_div_ck", -- .addr = omap44xx_i2c1_addrs, -- .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs), -+/* l4_wkup -> timer1 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { -+ .master = &omap44xx_l4_wkup_hwmod, -+ .slave = &omap44xx_timer1_hwmod, -+ .clk = "l4_wkup_clk_mux_ck", -+ .addr = omap44xx_timer1_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --/* i2c1 slave ports */ --static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { -- &omap44xx_l4_per__i2c1, -+/* timer1 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = { -+ &omap44xx_l4_wkup__timer1, - }; - --static struct omap_hwmod omap44xx_i2c1_hwmod = { -- .name = "i2c1", -- .class = &omap44xx_i2c_hwmod_class, -- .flags = HWMOD_INIT_NO_RESET, -- .mpu_irqs = omap44xx_i2c1_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs), -- .sdma_reqs = omap44xx_i2c1_sdma_reqs, -- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs), -- .main_clk = "i2c1_fck", -+static struct omap_hwmod omap44xx_timer1_hwmod = { -+ .name = "timer1", -+ .class = &omap44xx_timer_1ms_hwmod_class, -+ .mpu_irqs = omap44xx_timer1_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs), -+ .main_clk = "timer1_fck", - .prcm = { - .omap4 = { -- .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, -+ .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, - }, - }, -- .slaves = omap44xx_i2c1_slaves, -- .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), -+ .slaves = omap44xx_timer1_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - --/* i2c2 */ --static struct omap_hwmod omap44xx_i2c2_hwmod; --static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { -- { .irq = 57 + OMAP44XX_IRQ_GIC_START }, --}; -- --static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { -- { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, -- { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, -+/* timer2 */ -+static struct omap_hwmod omap44xx_timer2_hwmod; -+static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { -+ { .irq = 38 + OMAP44XX_IRQ_GIC_START }, - }; - --static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { -+static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { - { -- .pa_start = 0x48072000, -- .pa_end = 0x480720ff, -+ .pa_start = 0x48032000, -+ .pa_end = 0x4803207f, - .flags = ADDR_TYPE_RT - }, - }; - --/* l4_per -> i2c2 */ --static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { -+/* l4_per -> timer2 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { - .master = &omap44xx_l4_per_hwmod, -- .slave = &omap44xx_i2c2_hwmod, -+ .slave = &omap44xx_timer2_hwmod, - .clk = "l4_div_ck", -- .addr = omap44xx_i2c2_addrs, -- .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs), -+ .addr = omap44xx_timer2_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --/* i2c2 slave ports */ --static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { -- &omap44xx_l4_per__i2c2, -+/* timer2 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = { -+ &omap44xx_l4_per__timer2, - }; - --static struct omap_hwmod omap44xx_i2c2_hwmod = { -- .name = "i2c2", -- .class = &omap44xx_i2c_hwmod_class, -- .flags = HWMOD_INIT_NO_RESET, -- .mpu_irqs = omap44xx_i2c2_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs), -- .sdma_reqs = omap44xx_i2c2_sdma_reqs, -- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs), -- .main_clk = "i2c2_fck", -+static struct omap_hwmod omap44xx_timer2_hwmod = { -+ .name = "timer2", -+ .class = &omap44xx_timer_1ms_hwmod_class, -+ .mpu_irqs = omap44xx_timer2_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs), -+ .main_clk = "timer2_fck", - .prcm = { - .omap4 = { -- .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, -+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, - }, - }, -- .slaves = omap44xx_i2c2_slaves, -- .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), -+ .slaves = omap44xx_timer2_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - --/* i2c3 */ --static struct omap_hwmod omap44xx_i2c3_hwmod; --static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { -- { .irq = 61 + OMAP44XX_IRQ_GIC_START }, --}; -- --static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { -- { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, -- { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, -+/* timer3 */ -+static struct omap_hwmod omap44xx_timer3_hwmod; -+static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { -+ { .irq = 39 + OMAP44XX_IRQ_GIC_START }, - }; - --static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { -+static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { - { -- .pa_start = 0x48060000, -- .pa_end = 0x480600ff, -+ .pa_start = 0x48034000, -+ .pa_end = 0x4803407f, - .flags = ADDR_TYPE_RT - }, - }; - --/* l4_per -> i2c3 */ --static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { -+/* l4_per -> timer3 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { - .master = &omap44xx_l4_per_hwmod, -- .slave = &omap44xx_i2c3_hwmod, -+ .slave = &omap44xx_timer3_hwmod, - .clk = "l4_div_ck", -- .addr = omap44xx_i2c3_addrs, -- .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs), -+ .addr = omap44xx_timer3_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --/* i2c3 slave ports */ --static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { -- &omap44xx_l4_per__i2c3, -+/* timer3 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = { -+ &omap44xx_l4_per__timer3, - }; - --static struct omap_hwmod omap44xx_i2c3_hwmod = { -- .name = "i2c3", -- .class = &omap44xx_i2c_hwmod_class, -- .flags = HWMOD_INIT_NO_RESET, -- .mpu_irqs = omap44xx_i2c3_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs), -- .sdma_reqs = omap44xx_i2c3_sdma_reqs, -- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs), -- .main_clk = "i2c3_fck", -+static struct omap_hwmod omap44xx_timer3_hwmod = { -+ .name = "timer3", -+ .class = &omap44xx_timer_hwmod_class, -+ .mpu_irqs = omap44xx_timer3_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs), -+ .main_clk = "timer3_fck", - .prcm = { - .omap4 = { -- .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, -+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, - }, - }, -- .slaves = omap44xx_i2c3_slaves, -- .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), -+ .slaves = omap44xx_timer3_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - --/* i2c4 */ --static struct omap_hwmod omap44xx_i2c4_hwmod; --static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { -- { .irq = 62 + OMAP44XX_IRQ_GIC_START }, --}; -- --static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { -- { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, -- { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, -+/* timer4 */ -+static struct omap_hwmod omap44xx_timer4_hwmod; -+static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { -+ { .irq = 40 + OMAP44XX_IRQ_GIC_START }, - }; - --static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { -+static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { - { -- .pa_start = 0x48350000, -- .pa_end = 0x483500ff, -+ .pa_start = 0x48036000, -+ .pa_end = 0x4803607f, - .flags = ADDR_TYPE_RT - }, - }; - --/* l4_per -> i2c4 */ --static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { -+/* l4_per -> timer4 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { - .master = &omap44xx_l4_per_hwmod, -- .slave = &omap44xx_i2c4_hwmod, -+ .slave = &omap44xx_timer4_hwmod, - .clk = "l4_div_ck", -- .addr = omap44xx_i2c4_addrs, -- .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs), -+ .addr = omap44xx_timer4_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --/* i2c4 slave ports */ --static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { -- &omap44xx_l4_per__i2c4, -+/* timer4 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = { -+ &omap44xx_l4_per__timer4, - }; - --static struct omap_hwmod omap44xx_i2c4_hwmod = { -- .name = "i2c4", -- .class = &omap44xx_i2c_hwmod_class, -- .flags = HWMOD_INIT_NO_RESET, -- .mpu_irqs = omap44xx_i2c4_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs), -- .sdma_reqs = omap44xx_i2c4_sdma_reqs, -- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs), -- .main_clk = "i2c4_fck", -+static struct omap_hwmod omap44xx_timer4_hwmod = { -+ .name = "timer4", -+ .class = &omap44xx_timer_hwmod_class, -+ .mpu_irqs = omap44xx_timer4_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs), -+ .main_clk = "timer4_fck", - .prcm = { - .omap4 = { -- .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, -+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, - }, - }, -- .slaves = omap44xx_i2c4_slaves, -- .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), -+ .slaves = omap44xx_timer4_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - --/* -- * 'iva' class -- * multi-standard video encoder/decoder hardware accelerator -- */ -+/* timer5 */ -+static struct omap_hwmod omap44xx_timer5_hwmod; -+static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { -+ { .irq = 41 + OMAP44XX_IRQ_GIC_START }, -+}; - --static struct omap_hwmod_class omap44xx_iva_hwmod_class = { -- .name = "iva", -+static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { -+ { -+ .pa_start = 0x40138000, -+ .pa_end = 0x4013807f, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --/* iva */ --static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { -- { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, -- { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, -- { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, -+/* l4_abe -> timer5 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_timer5_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_timer5_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs), -+ .user = OCP_USER_MPU, - }; - --static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { -- { .name = "logic", .rst_shift = 2 }, -+static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { -+ { -+ .pa_start = 0x49038000, -+ .pa_end = 0x4903807f, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = { -- { .name = "seq0", .rst_shift = 0 }, -+/* l4_abe -> timer5 (dma) */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_timer5_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_timer5_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs), -+ .user = OCP_USER_SDMA, - }; - --static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = { -- { .name = "seq1", .rst_shift = 1 }, -+/* timer5 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = { -+ &omap44xx_l4_abe__timer5, -+ &omap44xx_l4_abe__timer5_dma, - }; - --/* iva master ports */ --static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = { -- &omap44xx_iva__l3_main_2, -- &omap44xx_iva__l3_instr, -+static struct omap_hwmod omap44xx_timer5_hwmod = { -+ .name = "timer5", -+ .class = &omap44xx_timer_hwmod_class, -+ .mpu_irqs = omap44xx_timer5_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs), -+ .main_clk = "timer5_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_timer5_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - --static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { -+/* timer6 */ -+static struct omap_hwmod omap44xx_timer6_hwmod; -+static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { -+ { .irq = 42 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { - { -- .pa_start = 0x5a000000, -- .pa_end = 0x5a07ffff, -+ .pa_start = 0x4013a000, -+ .pa_end = 0x4013a07f, - .flags = ADDR_TYPE_RT - }, - }; - --/* l3_main_2 -> iva */ --static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { -- .master = &omap44xx_l3_main_2_hwmod, -- .slave = &omap44xx_iva_hwmod, -- .clk = "l3_div_ck", -- .addr = omap44xx_iva_addrs, -- .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs), -+/* l4_abe -> timer6 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_timer6_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_timer6_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs), - .user = OCP_USER_MPU, - }; - --/* iva slave ports */ --static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = { -- &omap44xx_dsp__iva, -- &omap44xx_l3_main_2__iva, -+static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { -+ { -+ .pa_start = 0x4903a000, -+ .pa_end = 0x4903a07f, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_abe -> timer6 (dma) */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_timer6_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_timer6_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs), -+ .user = OCP_USER_SDMA, -+}; -+ -+/* timer6 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = { -+ &omap44xx_l4_abe__timer6, -+ &omap44xx_l4_abe__timer6_dma, - }; - --/* Pseudo hwmod for reset control purpose only */ --static struct omap_hwmod omap44xx_iva_seq0_hwmod = { -- .name = "iva_seq0", -- .class = &omap44xx_iva_hwmod_class, -- .flags = HWMOD_INIT_NO_RESET, -- .rst_lines = omap44xx_iva_seq0_resets, -- .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets), -+static struct omap_hwmod omap44xx_timer6_hwmod = { -+ .name = "timer6", -+ .class = &omap44xx_timer_hwmod_class, -+ .mpu_irqs = omap44xx_timer6_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs), -+ .main_clk = "timer6_fck", - .prcm = { - .omap4 = { -- .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, -+ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, - }, - }, -+ .slaves = omap44xx_timer6_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - --/* Pseudo hwmod for reset control purpose only */ --static struct omap_hwmod omap44xx_iva_seq1_hwmod = { -- .name = "iva_seq1", -- .class = &omap44xx_iva_hwmod_class, -- .flags = HWMOD_INIT_NO_RESET, -- .rst_lines = omap44xx_iva_seq1_resets, -- .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets), -- .prcm = { -- .omap4 = { -- .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, -- }, -- }, -- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+/* timer7 */ -+static struct omap_hwmod omap44xx_timer7_hwmod; -+static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { -+ { .irq = 43 + OMAP44XX_IRQ_GIC_START }, - }; - --static struct omap_hwmod omap44xx_iva_hwmod = { -- .name = "iva", -- .class = &omap44xx_iva_hwmod_class, -- .mpu_irqs = omap44xx_iva_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs), -- .rst_lines = omap44xx_iva_resets, -- .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), -- .main_clk = "iva_fck", -- .prcm = { -- .omap4 = { -- .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, -- .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL, -- }, -+static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { -+ { -+ .pa_start = 0x4013c000, -+ .pa_end = 0x4013c07f, -+ .flags = ADDR_TYPE_RT - }, -- .slaves = omap44xx_iva_slaves, -- .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves), -- .masters = omap44xx_iva_masters, -- .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters), -- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - --/* -- * 'mpu' class -- * mpu sub-system -- */ -+/* l4_abe -> timer7 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_timer7_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_timer7_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs), -+ .user = OCP_USER_MPU, -+}; - --static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { -- .name = "mpu", -+static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { -+ { -+ .pa_start = 0x4903c000, -+ .pa_end = 0x4903c07f, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --/* mpu */ --static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { -- { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, -- { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, -- { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, -+/* l4_abe -> timer7 (dma) */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_timer7_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_timer7_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs), -+ .user = OCP_USER_SDMA, - }; - --/* mpu master ports */ --static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = { -- &omap44xx_mpu__l3_main_1, -- &omap44xx_mpu__l4_abe, -- &omap44xx_mpu__dmm, -+/* timer7 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = { -+ &omap44xx_l4_abe__timer7, -+ &omap44xx_l4_abe__timer7_dma, - }; - --static struct omap_hwmod omap44xx_mpu_hwmod = { -- .name = "mpu", -- .class = &omap44xx_mpu_hwmod_class, -- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), -- .mpu_irqs = omap44xx_mpu_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs), -- .main_clk = "dpll_mpu_m2_ck", -+static struct omap_hwmod omap44xx_timer7_hwmod = { -+ .name = "timer7", -+ .class = &omap44xx_timer_hwmod_class, -+ .mpu_irqs = omap44xx_timer7_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs), -+ .main_clk = "timer7_fck", - .prcm = { - .omap4 = { -- .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL, -+ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, - }, - }, -- .masters = omap44xx_mpu_masters, -- .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters), -+ .slaves = omap44xx_timer7_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - --/* -- * 'smartreflex' class -- * smartreflex module (monitor silicon performance and outputs a measure of -- * performance error) -- */ -+/* timer8 */ -+static struct omap_hwmod omap44xx_timer8_hwmod; -+static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { -+ { .irq = 44 + OMAP44XX_IRQ_GIC_START }, -+}; - --/* The IP is not compliant to type1 / type2 scheme */ --static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { -- .sidle_shift = 24, -- .enwkup_shift = 26, -+static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { -+ { -+ .pa_start = 0x4013e000, -+ .pa_end = 0x4013e07f, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { -- .sysc_offs = 0x0038, -- .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), -- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -- SIDLE_SMART_WKUP), -- .sysc_fields = &omap_hwmod_sysc_type_smartreflex, -+/* l4_abe -> timer8 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_timer8_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_timer8_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs), -+ .user = OCP_USER_MPU, - }; - --static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { -- .name = "smartreflex", -- .sysc = &omap44xx_smartreflex_sysc, -- .rev = 2, -+static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { -+ { -+ .pa_start = 0x4903e000, -+ .pa_end = 0x4903e07f, -+ .flags = ADDR_TYPE_RT -+ }, - }; - --/* smartreflex_core */ --static struct omap_hwmod omap44xx_smartreflex_core_hwmod; --static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { -- { .irq = 19 + OMAP44XX_IRQ_GIC_START }, -+/* l4_abe -> timer8 (dma) */ -+static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { -+ .master = &omap44xx_l4_abe_hwmod, -+ .slave = &omap44xx_timer8_hwmod, -+ .clk = "ocp_abe_iclk", -+ .addr = omap44xx_timer8_dma_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs), -+ .user = OCP_USER_SDMA, - }; - --static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { -+/* timer8 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = { -+ &omap44xx_l4_abe__timer8, -+ &omap44xx_l4_abe__timer8_dma, -+}; -+ -+static struct omap_hwmod omap44xx_timer8_hwmod = { -+ .name = "timer8", -+ .class = &omap44xx_timer_hwmod_class, -+ .mpu_irqs = omap44xx_timer8_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs), -+ .main_clk = "timer8_fck", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, -+ }, -+ }, -+ .slaves = omap44xx_timer8_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* timer9 */ -+static struct omap_hwmod omap44xx_timer9_hwmod; -+static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { -+ { .irq = 45 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { - { -- .pa_start = 0x4a0dd000, -- .pa_end = 0x4a0dd03f, -+ .pa_start = 0x4803e000, -+ .pa_end = 0x4803e07f, - .flags = ADDR_TYPE_RT - }, - }; - --/* l4_cfg -> smartreflex_core */ --static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { -- .master = &omap44xx_l4_cfg_hwmod, -- .slave = &omap44xx_smartreflex_core_hwmod, -+/* l4_per -> timer9 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_timer9_hwmod, - .clk = "l4_div_ck", -- .addr = omap44xx_smartreflex_core_addrs, -- .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs), -+ .addr = omap44xx_timer9_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --/* smartreflex_core slave ports */ --static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = { -- &omap44xx_l4_cfg__smartreflex_core, -+/* timer9 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = { -+ &omap44xx_l4_per__timer9, - }; - --static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { -- .name = "smartreflex_core", -- .class = &omap44xx_smartreflex_hwmod_class, -- .mpu_irqs = omap44xx_smartreflex_core_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs), -- .main_clk = "smartreflex_core_fck", -- .vdd_name = "core", -+static struct omap_hwmod omap44xx_timer9_hwmod = { -+ .name = "timer9", -+ .class = &omap44xx_timer_hwmod_class, -+ .mpu_irqs = omap44xx_timer9_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs), -+ .main_clk = "timer9_fck", - .prcm = { - .omap4 = { -- .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, -+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, - }, - }, -- .slaves = omap44xx_smartreflex_core_slaves, -- .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves), -+ .slaves = omap44xx_timer9_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - --/* smartreflex_iva */ --static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; --static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { -- { .irq = 102 + OMAP44XX_IRQ_GIC_START }, -+/* timer10 */ -+static struct omap_hwmod omap44xx_timer10_hwmod; -+static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { -+ { .irq = 46 + OMAP44XX_IRQ_GIC_START }, - }; - --static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { -+static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { - { -- .pa_start = 0x4a0db000, -- .pa_end = 0x4a0db03f, -+ .pa_start = 0x48086000, -+ .pa_end = 0x4808607f, - .flags = ADDR_TYPE_RT - }, - }; - --/* l4_cfg -> smartreflex_iva */ --static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { -- .master = &omap44xx_l4_cfg_hwmod, -- .slave = &omap44xx_smartreflex_iva_hwmod, -+/* l4_per -> timer10 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_timer10_hwmod, - .clk = "l4_div_ck", -- .addr = omap44xx_smartreflex_iva_addrs, -- .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs), -+ .addr = omap44xx_timer10_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --/* smartreflex_iva slave ports */ --static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = { -- &omap44xx_l4_cfg__smartreflex_iva, -+/* timer10 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = { -+ &omap44xx_l4_per__timer10, - }; - --static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { -- .name = "smartreflex_iva", -- .class = &omap44xx_smartreflex_hwmod_class, -- .mpu_irqs = omap44xx_smartreflex_iva_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs), -- .main_clk = "smartreflex_iva_fck", -- .vdd_name = "iva", -+static struct omap_hwmod omap44xx_timer10_hwmod = { -+ .name = "timer10", -+ .class = &omap44xx_timer_1ms_hwmod_class, -+ .mpu_irqs = omap44xx_timer10_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs), -+ .main_clk = "timer10_fck", - .prcm = { - .omap4 = { -- .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, -+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, - }, - }, -- .slaves = omap44xx_smartreflex_iva_slaves, -- .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves), -+ .slaves = omap44xx_timer10_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - --/* smartreflex_mpu */ --static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; --static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { -- { .irq = 18 + OMAP44XX_IRQ_GIC_START }, -+/* timer11 */ -+static struct omap_hwmod omap44xx_timer11_hwmod; -+static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { -+ { .irq = 47 + OMAP44XX_IRQ_GIC_START }, - }; - --static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { -+static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { - { -- .pa_start = 0x4a0d9000, -- .pa_end = 0x4a0d903f, -+ .pa_start = 0x48088000, -+ .pa_end = 0x4808807f, - .flags = ADDR_TYPE_RT - }, - }; - --/* l4_cfg -> smartreflex_mpu */ --static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { -- .master = &omap44xx_l4_cfg_hwmod, -- .slave = &omap44xx_smartreflex_mpu_hwmod, -+/* l4_per -> timer11 */ -+static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { -+ .master = &omap44xx_l4_per_hwmod, -+ .slave = &omap44xx_timer11_hwmod, - .clk = "l4_div_ck", -- .addr = omap44xx_smartreflex_mpu_addrs, -- .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs), -+ .addr = omap44xx_timer11_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs), - .user = OCP_USER_MPU | OCP_USER_SDMA, - }; - --/* smartreflex_mpu slave ports */ --static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = { -- &omap44xx_l4_cfg__smartreflex_mpu, -+/* timer11 slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = { -+ &omap44xx_l4_per__timer11, - }; - --static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { -- .name = "smartreflex_mpu", -- .class = &omap44xx_smartreflex_hwmod_class, -- .mpu_irqs = omap44xx_smartreflex_mpu_irqs, -- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs), -- .main_clk = "smartreflex_mpu_fck", -- .vdd_name = "mpu", -+static struct omap_hwmod omap44xx_timer11_hwmod = { -+ .name = "timer11", -+ .class = &omap44xx_timer_hwmod_class, -+ .mpu_irqs = omap44xx_timer11_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs), -+ .main_clk = "timer11_fck", - .prcm = { - .omap4 = { -- .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, -+ .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, - }, - }, -- .slaves = omap44xx_smartreflex_mpu_slaves, -- .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves), -+ .slaves = omap44xx_timer11_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves), - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), - }; - -@@ -1870,6 +4776,88 @@ - }; - - /* -+ * 'usb_otg_hs' class -+ * high-speed on-the-go universal serial bus (usb_otg_hs) controller -+ */ -+ -+static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { -+ .rev_offs = 0x0400, -+ .sysc_offs = 0x0404, -+ .syss_offs = 0x0408, -+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | -+ SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | -+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), -+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | -+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | -+ MSTANDBY_SMART), -+ .sysc_fields = &omap_hwmod_sysc_type1, -+}; -+ -+static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { -+ .name = "usb_otg_hs", -+ .sysc = &omap44xx_usb_otg_hs_sysc, -+}; -+ -+/* usb_otg_hs */ -+static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { -+ { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, -+ { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, -+}; -+ -+/* usb_otg_hs master ports */ -+static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = { -+ &omap44xx_usb_otg_hs__l3_main_2, -+}; -+ -+static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { -+ { -+ .pa_start = 0x4a0ab000, -+ .pa_end = 0x4a0ab003, -+ .flags = ADDR_TYPE_RT -+ }, -+}; -+ -+/* l4_cfg -> usb_otg_hs */ -+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { -+ .master = &omap44xx_l4_cfg_hwmod, -+ .slave = &omap44xx_usb_otg_hs_hwmod, -+ .clk = "l4_div_ck", -+ .addr = omap44xx_usb_otg_hs_addrs, -+ .addr_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs), -+ .user = OCP_USER_MPU | OCP_USER_SDMA, -+}; -+ -+/* usb_otg_hs slave ports */ -+static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = { -+ &omap44xx_l4_cfg__usb_otg_hs, -+}; -+ -+static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { -+ { .role = "xclk", .clk = "usb_otg_hs_xclk" }, -+}; -+ -+static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { -+ .name = "usb_otg_hs", -+ .class = &omap44xx_usb_otg_hs_hwmod_class, -+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, -+ .mpu_irqs = omap44xx_usb_otg_hs_irqs, -+ .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs), -+ .main_clk = "usb_otg_hs_ick", -+ .prcm = { -+ .omap4 = { -+ .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, -+ }, -+ }, -+ .opt_clks = usb_otg_hs_opt_clks, -+ .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), -+ .slaves = omap44xx_usb_otg_hs_slaves, -+ .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), -+ .masters = omap44xx_usb_otg_hs_masters, -+ .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters), -+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), -+}; -+ -+/* - * 'wd_timer' class - * 32-bit watchdog upward counter that generates a pulse on the reset pin on - * overflow condition -@@ -2024,13 +5012,34 @@ - /* mpu_bus class */ - &omap44xx_mpu_private_hwmod, - -+ /* aess class */ -+/* &omap44xx_aess_hwmod, */ -+ -+ /* bandgap class */ -+ &omap44xx_bandgap_hwmod, -+ -+ /* counter class */ -+/* &omap44xx_counter_32k_hwmod, */ -+ - /* dma class */ - &omap44xx_dma_system_hwmod, - -+ /* dmic class */ -+ &omap44xx_dmic_hwmod, -+ - /* dsp class */ - &omap44xx_dsp_hwmod, - &omap44xx_dsp_c0_hwmod, - -+ /* dss class */ -+ &omap44xx_dss_hwmod, -+ &omap44xx_dss_dispc_hwmod, -+ &omap44xx_dss_dsi1_hwmod, -+ &omap44xx_dss_dsi2_hwmod, -+ &omap44xx_dss_hdmi_hwmod, -+ &omap44xx_dss_rfbi_hwmod, -+ &omap44xx_dss_venc_hwmod, -+ - /* gpio class */ - &omap44xx_gpio1_hwmod, - &omap44xx_gpio2_hwmod, -@@ -2039,17 +5048,56 @@ - &omap44xx_gpio5_hwmod, - &omap44xx_gpio6_hwmod, - -+ /* hsi class */ -+/* &omap44xx_hsi_hwmod, */ -+ - /* i2c class */ - &omap44xx_i2c1_hwmod, - &omap44xx_i2c2_hwmod, - &omap44xx_i2c3_hwmod, - &omap44xx_i2c4_hwmod, - -+ /* ipu class */ -+ &omap44xx_ipu_hwmod, -+ &omap44xx_ipu_c0_hwmod, -+ &omap44xx_ipu_c1_hwmod, -+ -+ /* iss class */ -+/* &omap44xx_iss_hwmod, */ -+ - /* iva class */ - &omap44xx_iva_hwmod, - &omap44xx_iva_seq0_hwmod, - &omap44xx_iva_seq1_hwmod, - -+ /* kbd class */ -+/* &omap44xx_kbd_hwmod, */ -+ -+ /* mailbox class */ -+ &omap44xx_mailbox_hwmod, -+ -+ /* mcbsp class */ -+ &omap44xx_mcbsp1_hwmod, -+ &omap44xx_mcbsp2_hwmod, -+ &omap44xx_mcbsp3_hwmod, -+ &omap44xx_mcbsp4_hwmod, -+ -+ /* mcpdm class */ -+/* &omap44xx_mcpdm_hwmod, */ -+ -+ /* mcspi class */ -+ &omap44xx_mcspi1_hwmod, -+ &omap44xx_mcspi2_hwmod, -+ &omap44xx_mcspi3_hwmod, -+ &omap44xx_mcspi4_hwmod, -+ -+ /* mmc class */ -+ &omap44xx_mmc1_hwmod, -+ &omap44xx_mmc2_hwmod, -+ &omap44xx_mmc3_hwmod, -+ &omap44xx_mmc4_hwmod, -+ &omap44xx_mmc5_hwmod, -+ - /* mpu class */ - &omap44xx_mpu_hwmod, - -@@ -2058,12 +5106,31 @@ - &omap44xx_smartreflex_iva_hwmod, - &omap44xx_smartreflex_mpu_hwmod, - -+ /* spinlock class */ -+ &omap44xx_spinlock_hwmod, -+ -+ /* timer class */ -+ &omap44xx_timer1_hwmod, -+ &omap44xx_timer2_hwmod, -+ &omap44xx_timer3_hwmod, -+ &omap44xx_timer4_hwmod, -+ &omap44xx_timer5_hwmod, -+ &omap44xx_timer6_hwmod, -+ &omap44xx_timer7_hwmod, -+ &omap44xx_timer8_hwmod, -+ &omap44xx_timer9_hwmod, -+ &omap44xx_timer10_hwmod, -+ &omap44xx_timer11_hwmod, -+ - /* uart class */ - &omap44xx_uart1_hwmod, - &omap44xx_uart2_hwmod, - &omap44xx_uart3_hwmod, - &omap44xx_uart4_hwmod, - -+ /* usb_otg_hs class */ -+ &omap44xx_usb_otg_hs_hwmod, -+ - /* wd_timer class */ - &omap44xx_wd_timer2_hwmod, - &omap44xx_wd_timer3_hwmod, -@@ -2073,6 +5140,6 @@ - - int __init omap44xx_hwmod_init(void) - { -- return omap_hwmod_init(omap44xx_hwmods); -+ return omap_hwmod_register(omap44xx_hwmods); - } - -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/omap_hwmod.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_hwmod.c 2011-03-09 13:19:09.827507277 +0100 -@@ -1,7 +1,7 @@ - /* - * omap_hwmod implementation for OMAP2/3/4 - * -- * Copyright (C) 2009-2010 Nokia Corporation -+ * Copyright (C) 2009-2011 Nokia Corporation - * - * Paul Walmsley, Benoît Cousson, Kevin Hilman - * -@@ -162,9 +162,6 @@ - /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ - static struct omap_hwmod *mpu_oh; - --/* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */ --static u8 inited; -- - - /* Private functions */ - -@@ -904,18 +901,16 @@ - * @oh: struct omap_hwmod * - * @data: not used; pass NULL - * -- * Called by omap_hwmod_late_init() (after omap2_clk_init()). -- * Resolves all clock names embedded in the hwmod. Returns -EINVAL if -- * the omap_hwmod has not yet been registered or if the clocks have -- * already been initialized, 0 on success, or a non-zero error on -- * failure. -+ * Called by omap_hwmod_setup_*() (after omap2_clk_init()). -+ * Resolves all clock names embedded in the hwmod. Returns 0 on -+ * success, or a negative error code on failure. - */ - static int _init_clocks(struct omap_hwmod *oh, void *data) - { - int ret = 0; - -- if (!oh || (oh->_state != _HWMOD_STATE_REGISTERED)) -- return -EINVAL; -+ if (oh->_state != _HWMOD_STATE_REGISTERED) -+ return 0; - - pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); - -@@ -1354,14 +1349,16 @@ - * @oh: struct omap_hwmod * - * - * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh -- * OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the -- * wrong state or returns 0. -+ * OCP_SYSCONFIG register. Returns 0. - */ - static int _setup(struct omap_hwmod *oh, void *data) - { - int i, r; - u8 postsetup_state; - -+ if (oh->_state != _HWMOD_STATE_CLKS_INITED) -+ return 0; -+ - /* Set iclk autoidle mode */ - if (oh->slaves_cnt > 0) { - for (i = 0; i < oh->slaves_cnt; i++) { -@@ -1455,7 +1452,7 @@ - */ - static int __init _register(struct omap_hwmod *oh) - { -- int ret, ms_id; -+ int ms_id; - - if (!oh || !oh->name || !oh->class || !oh->class->name || - (oh->_state != _HWMOD_STATE_UNKNOWN)) -@@ -1467,12 +1464,10 @@ - return -EEXIST; - - ms_id = _find_mpu_port_index(oh); -- if (!IS_ERR_VALUE(ms_id)) { -+ if (!IS_ERR_VALUE(ms_id)) - oh->_mpu_port_index = ms_id; -- oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); -- } else { -+ else - oh->_int_flags |= _HWMOD_NO_MPU_PORT; -- } - - list_add_tail(&oh->node, &omap_hwmod_list); - -@@ -1480,9 +1475,14 @@ - - oh->_state = _HWMOD_STATE_REGISTERED; - -- ret = 0; -+ /* -+ * XXX Rather than doing a strcmp(), this should test a flag -+ * set in the hwmod data, inserted by the autogenerator code. -+ */ -+ if (!strcmp(oh->name, MPU_INITIATOR_NAME)) -+ mpu_oh = oh; - -- return ret; -+ return 0; - } - - -@@ -1585,65 +1585,132 @@ - return ret; - } - -- - /** -- * omap_hwmod_init - init omap_hwmod code and register hwmods -+ * omap_hwmod_register - register an array of hwmods - * @ohs: pointer to an array of omap_hwmods to register - * - * Intended to be called early in boot before the clock framework is - * initialized. If @ohs is not null, will register all omap_hwmods -- * listed in @ohs that are valid for this chip. Returns -EINVAL if -- * omap_hwmod_init() has already been called or 0 otherwise. -+ * listed in @ohs that are valid for this chip. Returns 0. -+ */ -+int __init omap_hwmod_register(struct omap_hwmod **ohs) -+{ -+ int r, i; -+ -+ if (!ohs) -+ return 0; -+ -+ i = 0; -+ do { -+ if (!omap_chip_is(ohs[i]->omap_chip)) -+ continue; -+ -+ r = _register(ohs[i]); -+ WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name, -+ r); -+ } while (ohs[++i]); -+ -+ return 0; -+} -+ -+/* -+ * _populate_mpu_rt_base - populate the virtual address for a hwmod -+ * -+ * Must be called only from omap_hwmod_setup_*() so ioremap works properly. -+ * Assumes the caller takes care of locking if needed. - */ --int __init omap_hwmod_init(struct omap_hwmod **ohs) -+static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) -+{ -+ if (oh->_state != _HWMOD_STATE_REGISTERED) -+ return 0; -+ -+ if (oh->_int_flags & _HWMOD_NO_MPU_PORT) -+ return 0; -+ -+ oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); -+ if (!oh->_mpu_rt_va) -+ pr_warning("omap_hwmod: %s found no _mpu_rt_va for %s\n", -+ __func__, oh->name); -+ -+ return 0; -+} -+ -+/** -+ * omap_hwmod_setup_one - set up a single hwmod -+ * @oh_name: const char * name of the already-registered hwmod to set up -+ * -+ * Must be called after omap2_clk_init(). Resolves the struct clk -+ * names to struct clk pointers for each registered omap_hwmod. Also -+ * calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon -+ * success. -+ */ -+int __init omap_hwmod_setup_one(const char *oh_name) - { - struct omap_hwmod *oh; - int r; - -- if (inited) -+ pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); -+ -+ if (!mpu_oh) { -+ pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n", -+ oh_name, MPU_INITIATOR_NAME); - return -EINVAL; -+ } - -- inited = 1; -+ oh = _lookup(oh_name); -+ if (!oh) { -+ WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); -+ return -EINVAL; -+ } - -- if (!ohs) -- return 0; -+ if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) -+ omap_hwmod_setup_one(MPU_INITIATOR_NAME); - -- oh = *ohs; -- while (oh) { -- if (omap_chip_is(oh->omap_chip)) { -- r = _register(oh); -- WARN(r, "omap_hwmod: %s: _register returned " -- "%d\n", oh->name, r); -- } -- oh = *++ohs; -+ r = _populate_mpu_rt_base(oh, NULL); -+ if (IS_ERR_VALUE(r)) { -+ WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name); -+ return -EINVAL; -+ } -+ -+ r = _init_clocks(oh, NULL); -+ if (IS_ERR_VALUE(r)) { -+ WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name); -+ return -EINVAL; - } - -+ _setup(oh, NULL); -+ - return 0; - } - - /** -- * omap_hwmod_late_init - do some post-clock framework initialization -+ * omap_hwmod_setup - do some post-clock framework initialization - * - * Must be called after omap2_clk_init(). Resolves the struct clk names - * to struct clk pointers for each registered omap_hwmod. Also calls -- * _setup() on each hwmod. Returns 0. -+ * _setup() on each hwmod. Returns 0 upon success. - */ --int omap_hwmod_late_init(void) -+static int __init omap_hwmod_setup_all(void) - { - int r; - -- /* XXX check return value */ -- r = omap_hwmod_for_each(_init_clocks, NULL); -- WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n"); -+ if (!mpu_oh) { -+ pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", -+ __func__, MPU_INITIATOR_NAME); -+ return -EINVAL; -+ } -+ -+ r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL); - -- mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME); -- WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n", -- MPU_INITIATOR_NAME); -+ r = omap_hwmod_for_each(_init_clocks, NULL); -+ WARN(IS_ERR_VALUE(r), -+ "omap_hwmod: %s: _init_clocks failed\n", __func__); - - omap_hwmod_for_each(_setup, NULL); - - return 0; - } -+core_initcall(omap_hwmod_setup_all); - - /** - * omap_hwmod_enable - enable an omap_hwmod -@@ -1862,6 +1929,7 @@ - os = oh->slaves[i]; - - for (j = 0; j < os->addr_cnt; j++) { -+ (res + r)->name = (os->addr + j)->name; - (res + r)->start = (os->addr + j)->pa_start; - (res + r)->end = (os->addr + j)->pa_end; - (res + r)->flags = IORESOURCE_MEM; -@@ -2162,11 +2230,11 @@ - * @oh: struct omap_hwmod * - * @state: state that _setup() should leave the hwmod in - * -- * Sets the hwmod state that @oh will enter at the end of _setup() (called by -- * omap_hwmod_late_init()). Only valid to call between calls to -- * omap_hwmod_init() and omap_hwmod_late_init(). Returns 0 upon success or -- * -EINVAL if there is a problem with the arguments or if the hwmod is -- * in the wrong state. -+ * Sets the hwmod state that @oh will enter at the end of _setup() -+ * (called by omap_hwmod_setup_*()). Only valid to call between -+ * calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns -+ * 0 upon success or -EINVAL if there is a problem with the arguments -+ * or if the hwmod is in the wrong state. - */ - int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) - { -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/omap_phy_internal.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_phy_internal.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/omap_phy_internal.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/omap_phy_internal.c 2011-03-09 13:19:09.830507217 +0100 -@@ -29,6 +29,7 @@ - #include - - #include -+#include "control.h" - - /* OMAP control module register for UTMI PHY */ - #define CONTROL_DEV_CONF 0x300 -@@ -147,3 +148,95 @@ - - return 0; - } -+ -+void am35x_musb_reset(void) -+{ -+ u32 regval; -+ -+ /* Reset the musb interface */ -+ regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); -+ -+ regval |= AM35XX_USBOTGSS_SW_RST; -+ omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); -+ -+ regval &= ~AM35XX_USBOTGSS_SW_RST; -+ omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); -+ -+ regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); -+} -+ -+void am35x_musb_phy_power(u8 on) -+{ -+ unsigned long timeout = jiffies + msecs_to_jiffies(100); -+ u32 devconf2; -+ -+ if (on) { -+ /* -+ * Start the on-chip PHY and its PLL. -+ */ -+ devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); -+ -+ devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN); -+ devconf2 |= CONF2_PHY_PLLON; -+ -+ omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); -+ -+ pr_info(KERN_INFO "Waiting for PHY clock good...\n"); -+ while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2) -+ & CONF2_PHYCLKGD)) { -+ cpu_relax(); -+ -+ if (time_after(jiffies, timeout)) { -+ pr_err(KERN_ERR "musb PHY clock good timed out\n"); -+ break; -+ } -+ } -+ } else { -+ /* -+ * Power down the on-chip PHY. -+ */ -+ devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); -+ -+ devconf2 &= ~CONF2_PHY_PLLON; -+ devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN; -+ omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); -+ } -+} -+ -+void am35x_musb_clear_irq(void) -+{ -+ u32 regval; -+ -+ regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); -+ regval |= AM35XX_USBOTGSS_INT_CLR; -+ omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); -+ regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); -+} -+ -+void am35x_musb_set_mode(u8 musb_mode) -+{ -+ u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); -+ -+ devconf2 &= ~CONF2_OTGMODE; -+ switch (musb_mode) { -+#ifdef CONFIG_USB_MUSB_HDRC_HCD -+ case MUSB_HOST: /* Force VBUS valid, ID = 0 */ -+ devconf2 |= CONF2_FORCE_HOST; -+ break; -+#endif -+#ifdef CONFIG_USB_GADGET_MUSB_HDRC -+ case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ -+ devconf2 |= CONF2_FORCE_DEVICE; -+ break; -+#endif -+#ifdef CONFIG_USB_MUSB_OTG -+ case MUSB_OTG: /* Don't override the VBUS/ID comparators */ -+ devconf2 |= CONF2_NO_OVERRIDE; -+ break; -+#endif -+ default: -+ pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode); -+ } -+ -+ omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); -+} -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/opp2xxx.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/opp2xxx.h ---- linux-2.6.38-rc7/arch/arm/mach-omap2/opp2xxx.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/opp2xxx.h 2011-03-09 13:19:09.831507196 +0100 -@@ -418,7 +418,7 @@ - - extern const struct prcm_config omap2420_rate_table[]; - --#ifdef CONFIG_ARCH_OMAP2430 -+#ifdef CONFIG_SOC_OMAP2430 - extern const struct prcm_config omap2430_rate_table[]; - #else - #define omap2430_rate_table NULL -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/powerdomains2xxx_data.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/powerdomains2xxx_data.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/powerdomains2xxx_data.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/powerdomains2xxx_data.c 2011-03-09 13:19:09.835507113 +0100 -@@ -78,7 +78,7 @@ - * 2430-specific powerdomains - */ - --#ifdef CONFIG_ARCH_OMAP2430 -+#ifdef CONFIG_SOC_OMAP2430 - - /* XXX 2430 KILLDOMAINWKUP bit? No current users apparently */ - -@@ -97,7 +97,7 @@ - }, - }; - --#endif /* CONFIG_ARCH_OMAP2430 */ -+#endif /* CONFIG_SOC_OMAP2430 */ - - /* As powerdomains are added or removed above, this list must also be changed */ - static struct powerdomain *powerdomains_omap2xxx[] __initdata = { -@@ -111,7 +111,7 @@ - &core_24xx_pwrdm, - #endif - --#ifdef CONFIG_ARCH_OMAP2430 -+#ifdef CONFIG_SOC_OMAP2430 - &mdm_pwrdm, - #endif - NULL -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/prcm.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/prcm.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/prcm.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/prcm.c 2011-03-09 13:19:09.836507094 +0100 -@@ -24,6 +24,7 @@ - #include - #include - -+#include - #include - #include - #include -@@ -57,7 +58,7 @@ - EXPORT_SYMBOL(omap_prcm_get_reset_sources); - - /* Resets clock rates and reboots the system. Only called from system.h */ --void omap_prcm_arch_reset(char mode, const char *cmd) -+static void omap_prcm_arch_reset(char mode, const char *cmd) - { - s16 prcm_offs = 0; - -@@ -108,6 +109,8 @@ - omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */ - } - -+void (*arch_reset)(char, const char *) = omap_prcm_arch_reset; -+ - /** - * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness - * @reg: physical address of module IDLEST register -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/prcm-common.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/prcm-common.h ---- linux-2.6.38-rc7/arch/arm/mach-omap2/prcm-common.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/prcm-common.h 2011-03-09 13:19:09.836507094 +0100 -@@ -121,6 +121,10 @@ - #define OMAP24XX_ST_MCSPI2_MASK (1 << 18) - #define OMAP24XX_ST_MCSPI1_SHIFT 17 - #define OMAP24XX_ST_MCSPI1_MASK (1 << 17) -+#define OMAP24XX_ST_MCBSP2_SHIFT 16 -+#define OMAP24XX_ST_MCBSP2_MASK (1 << 16) -+#define OMAP24XX_ST_MCBSP1_SHIFT 15 -+#define OMAP24XX_ST_MCBSP1_MASK (1 << 15) - #define OMAP24XX_ST_GPT12_SHIFT 14 - #define OMAP24XX_ST_GPT12_MASK (1 << 14) - #define OMAP24XX_ST_GPT11_SHIFT 13 -@@ -191,6 +195,8 @@ - #define OMAP3430_AUTOIDLE_MASK (1 << 0) - - /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ -+#define OMAP3430_EN_MMC3_MASK (1 << 30) -+#define OMAP3430_EN_MMC3_SHIFT 30 - #define OMAP3430_EN_MMC2_MASK (1 << 25) - #define OMAP3430_EN_MMC2_SHIFT 25 - #define OMAP3430_EN_MMC1_MASK (1 << 24) -@@ -231,6 +237,8 @@ - #define OMAP3430_EN_HSOTGUSB_SHIFT 4 - - /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ -+#define OMAP3430_ST_MMC3_SHIFT 30 -+#define OMAP3430_ST_MMC3_MASK (1 << 30) - #define OMAP3430_ST_MMC2_SHIFT 25 - #define OMAP3430_ST_MMC2_MASK (1 << 25) - #define OMAP3430_ST_MMC1_SHIFT 24 -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/serial.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/serial.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/serial.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/serial.c 2011-03-09 13:19:09.841506993 +0100 -@@ -486,7 +486,7 @@ - mod_timer(&uart->timer, jiffies + uart->timeout); - omap_uart_smart_idle_enable(uart, 0); - -- if (cpu_is_omap34xx()) { -+ if (cpu_is_omap34xx() && !cpu_is_ti816x()) { - u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD; - u32 wk_mask = 0; - u32 padconf = 0; -@@ -655,7 +655,7 @@ - } - #endif - --void __init omap_serial_early_init(void) -+static int __init omap_serial_early_init(void) - { - int i = 0; - -@@ -672,7 +672,7 @@ - - uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL); - if (WARN_ON(!uart)) -- return; -+ return -ENODEV; - - uart->oh = oh; - uart->num = i++; -@@ -680,7 +680,7 @@ - num_uarts++; - - /* -- * NOTE: omap_hwmod_init() has not yet been called, -+ * NOTE: omap_hwmod_setup*() has not yet been called, - * so no hwmod functions will work yet. - */ - -@@ -691,7 +691,10 @@ - */ - uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET; - } while (1); -+ -+ return 0; - } -+core_initcall(omap_serial_early_init); - - /** - * omap_serial_init_port() - initialize single serial port -@@ -759,13 +762,13 @@ - p->private_data = uart; - - /* -- * omap44xx: Never read empty UART fifo -+ * omap44xx, ti816x: Never read empty UART fifo - * omap3xxx: Never read empty UART fifo on UARTs - * with IP rev >=0x52 - */ - uart->regshift = p->regshift; - uart->membase = p->membase; -- if (cpu_is_omap44xx()) -+ if (cpu_is_omap44xx() || cpu_is_ti816x()) - uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; - else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF) - >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) -@@ -847,7 +850,7 @@ - } - - /* Enable the MDR1 errata for OMAP3 */ -- if (cpu_is_omap34xx()) -+ if (cpu_is_omap34xx() && !cpu_is_ti816x()) - uart->errata |= UART_ERRATA_i202_MDR1_ACCESS; - } - -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/timer-gp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/timer-gp.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/timer-gp.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/timer-gp.c 2011-03-09 13:19:09.844506932 +0100 -@@ -40,10 +40,11 @@ - #include - #include - #include -+#include -+#include - - #include "timer-gp.h" - --#include - - /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */ - #define MAX_GPTIMER_ID 12 -@@ -133,9 +134,13 @@ - { - u32 tick_rate; - int src; -+ char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */ - - inited = 1; - -+ sprintf(clockevent_hwmod_name, "timer%d", gptimer_id); -+ omap_hwmod_setup_one(clockevent_hwmod_name); -+ - gptimer = omap_dm_timer_request_specific(gptimer_id); - BUG_ON(gptimer == NULL); - gptimer_wakeup = gptimer; -diff -Naur linux-2.6.38-rc7/arch/arm/mach-omap2/usb-musb.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/usb-musb.c ---- linux-2.6.38-rc7/arch/arm/mach-omap2/usb-musb.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/mach-omap2/usb-musb.c 2011-03-09 13:19:09.844506932 +0100 -@@ -30,118 +30,11 @@ - #include - #include - #include --#include "control.h" -+#include -+#include "mux.h" - - #if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X) - --static void am35x_musb_reset(void) --{ -- u32 regval; -- -- /* Reset the musb interface */ -- regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); -- -- regval |= AM35XX_USBOTGSS_SW_RST; -- omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); -- -- regval &= ~AM35XX_USBOTGSS_SW_RST; -- omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); -- -- regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); --} -- --static void am35x_musb_phy_power(u8 on) --{ -- unsigned long timeout = jiffies + msecs_to_jiffies(100); -- u32 devconf2; -- -- if (on) { -- /* -- * Start the on-chip PHY and its PLL. -- */ -- devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); -- -- devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN); -- devconf2 |= CONF2_PHY_PLLON; -- -- omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); -- -- pr_info(KERN_INFO "Waiting for PHY clock good...\n"); -- while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2) -- & CONF2_PHYCLKGD)) { -- cpu_relax(); -- -- if (time_after(jiffies, timeout)) { -- pr_err(KERN_ERR "musb PHY clock good timed out\n"); -- break; -- } -- } -- } else { -- /* -- * Power down the on-chip PHY. -- */ -- devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); -- -- devconf2 &= ~CONF2_PHY_PLLON; -- devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN; -- omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); -- } --} -- --static void am35x_musb_clear_irq(void) --{ -- u32 regval; -- -- regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); -- regval |= AM35XX_USBOTGSS_INT_CLR; -- omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); -- regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); --} -- --static void am35x_musb_set_mode(u8 musb_mode) --{ -- u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); -- -- devconf2 &= ~CONF2_OTGMODE; -- switch (musb_mode) { --#ifdef CONFIG_USB_MUSB_HDRC_HCD -- case MUSB_HOST: /* Force VBUS valid, ID = 0 */ -- devconf2 |= CONF2_FORCE_HOST; -- break; --#endif --#ifdef CONFIG_USB_GADGET_MUSB_HDRC -- case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ -- devconf2 |= CONF2_FORCE_DEVICE; -- break; --#endif --#ifdef CONFIG_USB_MUSB_OTG -- case MUSB_OTG: /* Don't override the VBUS/ID comparators */ -- devconf2 |= CONF2_NO_OVERRIDE; -- break; --#endif -- default: -- pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode); -- } -- -- omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); --} -- --static struct resource musb_resources[] = { -- [0] = { /* start and end set dynamically */ -- .flags = IORESOURCE_MEM, -- }, -- [1] = { /* general IRQ */ -- .start = INT_243X_HS_USB_MC, -- .flags = IORESOURCE_IRQ, -- .name = "mc", -- }, -- [2] = { /* DMA IRQ */ -- .start = INT_243X_HS_USB_DMA, -- .flags = IORESOURCE_IRQ, -- .name = "dma", -- }, --}; -- - static struct musb_hdrc_config musb_config = { - .multipoint = 1, - .dyn_fifo = 1, -@@ -169,38 +62,65 @@ - - static u64 musb_dmamask = DMA_BIT_MASK(32); - --static struct platform_device musb_device = { -- .name = "musb-omap2430", -- .id = -1, -- .dev = { -- .dma_mask = &musb_dmamask, -- .coherent_dma_mask = DMA_BIT_MASK(32), -- .platform_data = &musb_plat, -+static struct omap_device_pm_latency omap_musb_latency[] = { -+ { -+ .deactivate_func = omap_device_idle_hwmods, -+ .activate_func = omap_device_enable_hwmods, -+ .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, - }, -- .num_resources = ARRAY_SIZE(musb_resources), -- .resource = musb_resources, - }; - -+static void usb_musb_mux_init(struct omap_musb_board_data *board_data) -+{ -+ switch (board_data->interface_type) { -+ case MUSB_INTERFACE_UTMI: -+ omap_mux_init_signal("usba0_otg_dp", OMAP_PIN_INPUT); -+ omap_mux_init_signal("usba0_otg_dm", OMAP_PIN_INPUT); -+ break; -+ case MUSB_INTERFACE_ULPI: -+ omap_mux_init_signal("usba0_ulpiphy_clk", -+ OMAP_PIN_INPUT_PULLDOWN); -+ omap_mux_init_signal("usba0_ulpiphy_stp", -+ OMAP_PIN_INPUT_PULLDOWN); -+ omap_mux_init_signal("usba0_ulpiphy_dir", -+ OMAP_PIN_INPUT_PULLDOWN); -+ omap_mux_init_signal("usba0_ulpiphy_nxt", -+ OMAP_PIN_INPUT_PULLDOWN); -+ omap_mux_init_signal("usba0_ulpiphy_dat0", -+ OMAP_PIN_INPUT_PULLDOWN); -+ omap_mux_init_signal("usba0_ulpiphy_dat1", -+ OMAP_PIN_INPUT_PULLDOWN); -+ omap_mux_init_signal("usba0_ulpiphy_dat2", -+ OMAP_PIN_INPUT_PULLDOWN); -+ omap_mux_init_signal("usba0_ulpiphy_dat3", -+ OMAP_PIN_INPUT_PULLDOWN); -+ omap_mux_init_signal("usba0_ulpiphy_dat4", -+ OMAP_PIN_INPUT_PULLDOWN); -+ omap_mux_init_signal("usba0_ulpiphy_dat5", -+ OMAP_PIN_INPUT_PULLDOWN); -+ omap_mux_init_signal("usba0_ulpiphy_dat6", -+ OMAP_PIN_INPUT_PULLDOWN); -+ omap_mux_init_signal("usba0_ulpiphy_dat7", -+ OMAP_PIN_INPUT_PULLDOWN); -+ break; -+ default: -+ break; -+ } -+} -+ - void __init usb_musb_init(struct omap_musb_board_data *board_data) - { -- if (cpu_is_omap243x()) { -- musb_resources[0].start = OMAP243X_HS_BASE; -- } else if (cpu_is_omap3517() || cpu_is_omap3505()) { -- musb_device.name = "musb-am35x"; -- musb_resources[0].start = AM35XX_IPSS_USBOTGSS_BASE; -- musb_resources[1].start = INT_35XX_USBOTG_IRQ; -- board_data->set_phy_power = am35x_musb_phy_power; -- board_data->clear_irq = am35x_musb_clear_irq; -- board_data->set_mode = am35x_musb_set_mode; -- board_data->reset = am35x_musb_reset; -- } else if (cpu_is_omap34xx()) { -- musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; -+ struct omap_hwmod *oh; -+ struct omap_device *od; -+ struct platform_device *pdev; -+ struct device *dev; -+ int bus_id = -1; -+ const char *oh_name, *name; -+ -+ if (cpu_is_omap3517() || cpu_is_omap3505()) { - } else if (cpu_is_omap44xx()) { -- musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE; -- musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N; -- musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N; -+ usb_musb_mux_init(board_data); - } -- musb_resources[0].end = musb_resources[0].start + SZ_4K - 1; - - /* - * REVISIT: This line can be removed once all the platforms using -@@ -212,8 +132,35 @@ - musb_plat.mode = board_data->mode; - musb_plat.extvbus = board_data->extvbus; - -- if (platform_device_register(&musb_device) < 0) -- printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); -+ if (cpu_is_omap3517() || cpu_is_omap3505()) { -+ oh_name = "am35x_otg_hs"; -+ name = "musb-am35x"; -+ } else { -+ oh_name = "usb_otg_hs"; -+ name = "musb-omap2430"; -+ } -+ -+ oh = omap_hwmod_lookup(oh_name); -+ if (!oh) { -+ pr_err("Could not look up %s\n", oh_name); -+ return; -+ } -+ -+ od = omap_device_build(name, bus_id, oh, &musb_plat, -+ sizeof(musb_plat), omap_musb_latency, -+ ARRAY_SIZE(omap_musb_latency), false); -+ if (IS_ERR(od)) { -+ pr_err("Could not build omap_device for %s %s\n", -+ name, oh_name); -+ return; -+ } -+ -+ pdev = &od->pdev; -+ dev = &pdev->dev; -+ get_device(dev); -+ dev->dma_mask = &musb_dmamask; -+ dev->coherent_dma_mask = musb_dmamask; -+ put_device(dev); - } - - #else -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/common.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/common.c ---- linux-2.6.38-rc7/arch/arm/plat-omap/common.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/common.c 2011-03-09 13:19:10.088501983 +0100 -@@ -24,10 +24,11 @@ - - #define NO_LENGTH_CHECK 0xffffffff - --struct omap_board_config_kernel *omap_board_config; -+struct omap_board_config_kernel *omap_board_config __initdata; - int omap_board_config_size; - --static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out) -+static const void *__init get_config(u16 tag, size_t len, -+ int skip, size_t *len_out) - { - struct omap_board_config_kernel *kinfo = NULL; - int i; -@@ -49,17 +50,15 @@ - return kinfo->data; - } - --const void *__omap_get_config(u16 tag, size_t len, int nr) -+const void *__init __omap_get_config(u16 tag, size_t len, int nr) - { - return get_config(tag, len, nr, NULL); - } --EXPORT_SYMBOL(__omap_get_config); - --const void *omap_get_var_config(u16 tag, size_t *len) -+const void *__init omap_get_var_config(u16 tag, size_t *len) - { - return get_config(tag, NO_LENGTH_CHECK, 0, len); - } --EXPORT_SYMBOL(omap_get_var_config); - - void __init omap_reserve(void) - { -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/counter_32k.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/counter_32k.c ---- linux-2.6.38-rc7/arch/arm/plat-omap/counter_32k.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/counter_32k.c 2011-03-09 13:19:10.088501983 +0100 -@@ -54,7 +54,7 @@ - #define omap16xx_32k_read NULL - #endif - --#ifdef CONFIG_ARCH_OMAP2420 -+#ifdef CONFIG_SOC_OMAP2420 - static cycle_t notrace omap2420_32k_read(struct clocksource *cs) - { - return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k; -@@ -63,7 +63,7 @@ - #define omap2420_32k_read NULL - #endif - --#ifdef CONFIG_ARCH_OMAP2430 -+#ifdef CONFIG_SOC_OMAP2430 - static cycle_t notrace omap2430_32k_read(struct clocksource *cs) - { - return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k; -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/cpu-omap.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/cpu-omap.c ---- linux-2.6.38-rc7/arch/arm/plat-omap/cpu-omap.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/cpu-omap.c 2011-03-09 13:19:10.088501983 +0100 -@@ -101,7 +101,7 @@ - return ret; - } - --static int __init omap_cpu_init(struct cpufreq_policy *policy) -+static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy) - { - int result = 0; - -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/devices.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/devices.c ---- linux-2.6.38-rc7/arch/arm/plat-omap/devices.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/devices.c 2011-03-09 13:19:10.089501963 +0100 -@@ -35,8 +35,8 @@ - - static struct platform_device **omap_mcbsp_devices; - --void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, -- int size) -+void omap_mcbsp_register_board_cfg(struct resource *res, int res_count, -+ struct omap_mcbsp_platform_data *config, int size) - { - int i; - -@@ -54,6 +54,8 @@ - new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1); - if (!new_mcbsp) - continue; -+ platform_device_add_resources(new_mcbsp, &res[i * res_count], -+ res_count); - new_mcbsp->dev.platform_data = &config[i]; - ret = platform_device_add(new_mcbsp); - if (ret) { -@@ -65,8 +67,8 @@ - } - - #else --void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, -- int size) -+void omap_mcbsp_register_board_cfg(struct resource *res, int res_count, -+ struct omap_mcbsp_platform_data *config, int size) - { } - #endif - -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/dma.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/dma.c ---- linux-2.6.38-rc7/arch/arm/plat-omap/dma.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/dma.c 2011-03-09 13:19:10.090501943 +0100 -@@ -134,7 +134,7 @@ - - #ifdef CONFIG_ARCH_OMAP15XX - /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ --int omap_dma_in_1510_mode(void) -+static int omap_dma_in_1510_mode(void) - { - return enable_1510_mode; - } -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/i2c.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/i2c.c ---- linux-2.6.38-rc7/arch/arm/plat-omap/i2c.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/i2c.c 2011-03-09 13:19:10.091501922 +0100 -@@ -112,6 +112,7 @@ - } - - -+#ifdef CONFIG_ARCH_OMAP2PLUS - /* - * XXX This function is a temporary compatibility wrapper - only - * needed until the I2C driver can be converted to call -@@ -130,7 +131,6 @@ - }, - }; - --#ifdef CONFIG_ARCH_OMAP2PLUS - static inline int omap2_i2c_add_bus(int bus_id) - { - int l; -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/board.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/board.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/board.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/board.h 2011-03-09 13:19:10.092501901 +0100 -@@ -151,14 +151,14 @@ - const void *data; - }; - --extern const void *__omap_get_config(u16 tag, size_t len, int nr); -+extern const void *__init __omap_get_config(u16 tag, size_t len, int nr); - - #define omap_get_config(tag, type) \ - ((const type *) __omap_get_config((tag), sizeof(type), 0)) - #define omap_get_nr_config(tag, type, nr) \ - ((const type *) __omap_get_config((tag), sizeof(type), (nr))) - --extern const void *omap_get_var_config(u16 tag, size_t *len); -+extern const void *__init omap_get_var_config(u16 tag, size_t *len); - - extern struct omap_board_config_kernel *omap_board_config; - extern int omap_board_config_size; -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/clkdev_omap.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/clkdev_omap.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/clkdev_omap.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/clkdev_omap.h 2011-03-09 13:19:10.093501880 +0100 -@@ -38,6 +38,7 @@ - #define CK_3517 (1 << 9) - #define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */ - #define CK_443X (1 << 11) -+#define CK_TI816X (1 << 12) - - - #define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS) -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/clock.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/clock.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/clock.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/clock.h 2011-03-09 13:19:10.093501880 +0100 -@@ -53,6 +53,7 @@ - #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ - #define RATE_IN_36XX (1 << 4) - #define RATE_IN_4430 (1 << 5) -+#define RATE_IN_TI816X (1 << 6) - - #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) - #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/common.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/common.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/common.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/common.h 2011-03-09 13:19:10.093501880 +0100 -@@ -66,6 +66,7 @@ - void omap2_set_globals_243x(void); - void omap2_set_globals_3xxx(void); - void omap2_set_globals_443x(void); -+void omap2_set_globals_ti816x(void); - - /* These get called from omap2_set_globals_xxxx(), do not call these */ - void omap2_set_globals_tap(struct omap_globals *); -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/cpu.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/cpu.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/cpu.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/cpu.h 2011-03-09 13:19:10.093501880 +0100 -@@ -5,7 +5,7 @@ - * - * Copyright (C) 2004, 2008 Nokia Corporation - * -- * Copyright (C) 2009 Texas Instruments. -+ * Copyright (C) 2009-11 Texas Instruments. - * - * Written by Tony Lindgren - * -@@ -105,6 +105,12 @@ - return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ - } - -+#define IS_TI_SUBCLASS(subclass, id) \ -+static inline int is_ti ##subclass (void) \ -+{ \ -+ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ -+} -+ - IS_OMAP_CLASS(7xx, 0x07) - IS_OMAP_CLASS(15xx, 0x15) - IS_OMAP_CLASS(16xx, 0x16) -@@ -118,6 +124,8 @@ - IS_OMAP_SUBCLASS(363x, 0x363) - IS_OMAP_SUBCLASS(443x, 0x443) - -+IS_TI_SUBCLASS(816x, 0x816) -+ - #define cpu_is_omap7xx() 0 - #define cpu_is_omap15xx() 0 - #define cpu_is_omap16xx() 0 -@@ -126,6 +134,7 @@ - #define cpu_is_omap243x() 0 - #define cpu_is_omap34xx() 0 - #define cpu_is_omap343x() 0 -+#define cpu_is_ti816x() 0 - #define cpu_is_omap44xx() 0 - #define cpu_is_omap443x() 0 - -@@ -170,11 +179,11 @@ - # undef cpu_is_omap24xx - # define cpu_is_omap24xx() is_omap24xx() - # endif --# if defined (CONFIG_ARCH_OMAP2420) -+# if defined (CONFIG_SOC_OMAP2420) - # undef cpu_is_omap242x - # define cpu_is_omap242x() is_omap242x() - # endif --# if defined (CONFIG_ARCH_OMAP2430) -+# if defined (CONFIG_SOC_OMAP2430) - # undef cpu_is_omap243x - # define cpu_is_omap243x() is_omap243x() - # endif -@@ -189,11 +198,11 @@ - # undef cpu_is_omap24xx - # define cpu_is_omap24xx() 1 - # endif --# if defined(CONFIG_ARCH_OMAP2420) -+# if defined(CONFIG_SOC_OMAP2420) - # undef cpu_is_omap242x - # define cpu_is_omap242x() 1 - # endif --# if defined(CONFIG_ARCH_OMAP2430) -+# if defined(CONFIG_SOC_OMAP2430) - # undef cpu_is_omap243x - # define cpu_is_omap243x() 1 - # endif -@@ -201,7 +210,7 @@ - # undef cpu_is_omap34xx - # define cpu_is_omap34xx() 1 - # endif --# if defined(CONFIG_ARCH_OMAP3430) -+# if defined(CONFIG_SOC_OMAP3430) - # undef cpu_is_omap343x - # define cpu_is_omap343x() 1 - # endif -@@ -330,6 +339,7 @@ - # undef cpu_is_omap3530 - # undef cpu_is_omap3505 - # undef cpu_is_omap3517 -+# undef cpu_is_ti816x - # define cpu_is_omap3430() is_omap3430() - # define cpu_is_omap3503() (cpu_is_omap3430() && \ - (!omap3_has_iva()) && \ -@@ -345,6 +355,7 @@ - # define cpu_is_omap3517() is_omap3517() - # undef cpu_is_omap3630 - # define cpu_is_omap3630() is_omap363x() -+# define cpu_is_ti816x() is_ti816x() - #endif - - # if defined(CONFIG_ARCH_OMAP4) -@@ -389,9 +400,15 @@ - #define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8)) - #define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8)) - -+#define TI816X_CLASS 0x81600034 -+#define TI8168_REV_ES1_0 TI816X_CLASS -+#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8)) -+ - #define OMAP443X_CLASS 0x44300044 --#define OMAP4430_REV_ES1_0 OMAP443X_CLASS --#define OMAP4430_REV_ES2_0 0x44301044 -+#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) -+#define OMAP4430_REV_ES2_0 (OMAP443X_CLASS | (0x20 << 8)) -+#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8)) -+#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8)) - - /* - * omap_chip bits -@@ -419,11 +436,16 @@ - #define CHIP_IS_OMAP3630ES1_1 (1 << 9) - #define CHIP_IS_OMAP3630ES1_2 (1 << 10) - #define CHIP_IS_OMAP4430ES2 (1 << 11) -+#define CHIP_IS_OMAP4430ES2_1 (1 << 12) -+#define CHIP_IS_OMAP4430ES2_2 (1 << 13) -+#define CHIP_IS_TI816X (1 << 14) - - #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) - --#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ -- CHIP_IS_OMAP4430ES2) -+#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \ -+ CHIP_IS_OMAP4430ES2 | \ -+ CHIP_IS_OMAP4430ES2_1 | \ -+ CHIP_IS_OMAP4430ES2_2) - - /* - * "GE" here represents "greater than or equal to" in terms of ES -@@ -455,6 +477,7 @@ - #define OMAP3_HAS_ISP BIT(4) - #define OMAP3_HAS_192MHZ_CLK BIT(5) - #define OMAP3_HAS_IO_WAKEUP BIT(6) -+#define OMAP3_HAS_SDRC BIT(7) - - #define OMAP3_HAS_FEATURE(feat,flag) \ - static inline unsigned int omap3_has_ ##feat(void) \ -@@ -469,5 +492,6 @@ - OMAP3_HAS_FEATURE(isp, ISP) - OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK) - OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP) -+OMAP3_HAS_FEATURE(sdrc, SDRC) - - #endif -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/display.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/display.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/display.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/display.h 2011-03-09 13:19:10.094501859 +0100 -@@ -23,6 +23,7 @@ - #include - #include - #include -+#include - #include - - #define DISPC_IRQ_FRAMEDONE (1 << 0) -@@ -226,6 +227,23 @@ - struct omap_dss_device *default_device; - }; - -+#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS) -+/* Init with the board info */ -+extern int omap_display_init(struct omap_dss_board_info *board_data); -+#else -+static inline int omap_display_init(struct omap_dss_board_info *board_data) -+{ -+ return 0; -+} -+#endif -+ -+struct omap_display_platform_data { -+ struct omap_dss_board_info *board_data; -+ /* TODO: Additional members to be added when PM is considered */ -+ -+ bool (*opt_clock_available)(const char *clk_role); -+}; -+ - struct omap_video_timings { - /* Unit: pixels */ - u16 x_res; -@@ -385,8 +403,8 @@ - struct { - u16 regn; - u16 regm; -- u16 regm3; -- u16 regm4; -+ u16 regm_dispc; -+ u16 regm_dsi; - - u16 lp_clk_div; - -@@ -544,6 +562,9 @@ - int channel, - u16 x, u16 y, u16 w, u16 h, - void (*callback)(int, void *), void *data); -+int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel); -+int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id); -+void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel); - - int omapdss_dsi_display_enable(struct omap_dss_device *dssdev); - void omapdss_dsi_display_disable(struct omap_dss_device *dssdev); -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/dmtimer.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/dmtimer.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/dmtimer.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/dmtimer.h 2011-03-09 13:19:10.094501859 +0100 -@@ -3,6 +3,12 @@ - * - * OMAP Dual-Mode Timers - * -+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -+ * Tarun Kanti DebBarma -+ * Thara Gopinath -+ * -+ * Platform device conversion and hwmod support. -+ * - * Copyright (C) 2005 Nokia Corporation - * Author: Lauri Leukkunen - * PWM and clock framwork support by Timo Teras. -@@ -44,6 +50,11 @@ - #define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 - #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 - -+/* -+ * IP revision identifier so that Highlander IP -+ * in OMAP4 can be distinguished. -+ */ -+#define OMAP_TIMER_IP_VERSION_1 0x1 - struct omap_dm_timer; - extern struct omap_dm_timer *gptimer_wakeup; - extern struct sys_timer omap_timer; -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/fpga.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/fpga.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/fpga.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/fpga.h 2011-03-09 13:19:10.095501839 +0100 -@@ -30,18 +30,18 @@ - * --------------------------------------------------------------------------- - */ - /* maps in the FPGA registers and the ETHR registers */ --#define H2P2_DBG_FPGA_BASE IOMEM(0xE8000000) /* VA */ -+#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ - #define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ - #define H2P2_DBG_FPGA_START 0x04000000 /* PA */ - - #define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) --#define H2P2_DBG_FPGA_FPGA_REV (H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ --#define H2P2_DBG_FPGA_BOARD_REV (H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ --#define H2P2_DBG_FPGA_GPIO (H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ --#define H2P2_DBG_FPGA_LEDS (H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ --#define H2P2_DBG_FPGA_MISC_INPUTS (H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ --#define H2P2_DBG_FPGA_LAN_STATUS (H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ --#define H2P2_DBG_FPGA_LAN_RESET (H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ -+#define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ -+#define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ -+#define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ -+#define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ -+#define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ -+#define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ -+#define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ - - /* NOTE: most boards don't have a static mapping for the FPGA ... */ - struct h2p2_dbg_fpga { -@@ -81,55 +81,55 @@ - * OMAP-1510 FPGA - * --------------------------------------------------------------------------- - */ --#define OMAP1510_FPGA_BASE IOMEM(0xE8000000) /* VA */ -+#define OMAP1510_FPGA_BASE 0xE8000000 /* VA */ - #define OMAP1510_FPGA_SIZE SZ_4K - #define OMAP1510_FPGA_START 0x08000000 /* PA */ - - /* Revision */ --#define OMAP1510_FPGA_REV_LOW (OMAP1510_FPGA_BASE + 0x0) --#define OMAP1510_FPGA_REV_HIGH (OMAP1510_FPGA_BASE + 0x1) -+#define OMAP1510_FPGA_REV_LOW IOMEM(OMAP1510_FPGA_BASE + 0x0) -+#define OMAP1510_FPGA_REV_HIGH IOMEM(OMAP1510_FPGA_BASE + 0x1) - --#define OMAP1510_FPGA_LCD_PANEL_CONTROL (OMAP1510_FPGA_BASE + 0x2) --#define OMAP1510_FPGA_LED_DIGIT (OMAP1510_FPGA_BASE + 0x3) --#define INNOVATOR_FPGA_HID_SPI (OMAP1510_FPGA_BASE + 0x4) --#define OMAP1510_FPGA_POWER (OMAP1510_FPGA_BASE + 0x5) -+#define OMAP1510_FPGA_LCD_PANEL_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x2) -+#define OMAP1510_FPGA_LED_DIGIT IOMEM(OMAP1510_FPGA_BASE + 0x3) -+#define INNOVATOR_FPGA_HID_SPI IOMEM(OMAP1510_FPGA_BASE + 0x4) -+#define OMAP1510_FPGA_POWER IOMEM(OMAP1510_FPGA_BASE + 0x5) - - /* Interrupt status */ --#define OMAP1510_FPGA_ISR_LO (OMAP1510_FPGA_BASE + 0x6) --#define OMAP1510_FPGA_ISR_HI (OMAP1510_FPGA_BASE + 0x7) -+#define OMAP1510_FPGA_ISR_LO IOMEM(OMAP1510_FPGA_BASE + 0x6) -+#define OMAP1510_FPGA_ISR_HI IOMEM(OMAP1510_FPGA_BASE + 0x7) - - /* Interrupt mask */ --#define OMAP1510_FPGA_IMR_LO (OMAP1510_FPGA_BASE + 0x8) --#define OMAP1510_FPGA_IMR_HI (OMAP1510_FPGA_BASE + 0x9) -+#define OMAP1510_FPGA_IMR_LO IOMEM(OMAP1510_FPGA_BASE + 0x8) -+#define OMAP1510_FPGA_IMR_HI IOMEM(OMAP1510_FPGA_BASE + 0x9) - - /* Reset registers */ --#define OMAP1510_FPGA_HOST_RESET (OMAP1510_FPGA_BASE + 0xa) --#define OMAP1510_FPGA_RST (OMAP1510_FPGA_BASE + 0xb) -+#define OMAP1510_FPGA_HOST_RESET IOMEM(OMAP1510_FPGA_BASE + 0xa) -+#define OMAP1510_FPGA_RST IOMEM(OMAP1510_FPGA_BASE + 0xb) - --#define OMAP1510_FPGA_AUDIO (OMAP1510_FPGA_BASE + 0xc) --#define OMAP1510_FPGA_DIP (OMAP1510_FPGA_BASE + 0xe) --#define OMAP1510_FPGA_FPGA_IO (OMAP1510_FPGA_BASE + 0xf) --#define OMAP1510_FPGA_UART1 (OMAP1510_FPGA_BASE + 0x14) --#define OMAP1510_FPGA_UART2 (OMAP1510_FPGA_BASE + 0x15) --#define OMAP1510_FPGA_OMAP1510_STATUS (OMAP1510_FPGA_BASE + 0x16) --#define OMAP1510_FPGA_BOARD_REV (OMAP1510_FPGA_BASE + 0x18) --#define OMAP1510P1_PPT_DATA (OMAP1510_FPGA_BASE + 0x100) --#define OMAP1510P1_PPT_STATUS (OMAP1510_FPGA_BASE + 0x101) --#define OMAP1510P1_PPT_CONTROL (OMAP1510_FPGA_BASE + 0x102) -- --#define OMAP1510_FPGA_TOUCHSCREEN (OMAP1510_FPGA_BASE + 0x204) -- --#define INNOVATOR_FPGA_INFO (OMAP1510_FPGA_BASE + 0x205) --#define INNOVATOR_FPGA_LCD_BRIGHT_LO (OMAP1510_FPGA_BASE + 0x206) --#define INNOVATOR_FPGA_LCD_BRIGHT_HI (OMAP1510_FPGA_BASE + 0x207) --#define INNOVATOR_FPGA_LED_GRN_LO (OMAP1510_FPGA_BASE + 0x208) --#define INNOVATOR_FPGA_LED_GRN_HI (OMAP1510_FPGA_BASE + 0x209) --#define INNOVATOR_FPGA_LED_RED_LO (OMAP1510_FPGA_BASE + 0x20a) --#define INNOVATOR_FPGA_LED_RED_HI (OMAP1510_FPGA_BASE + 0x20b) --#define INNOVATOR_FPGA_CAM_USB_CONTROL (OMAP1510_FPGA_BASE + 0x20c) --#define INNOVATOR_FPGA_EXP_CONTROL (OMAP1510_FPGA_BASE + 0x20d) --#define INNOVATOR_FPGA_ISR2 (OMAP1510_FPGA_BASE + 0x20e) --#define INNOVATOR_FPGA_IMR2 (OMAP1510_FPGA_BASE + 0x210) -+#define OMAP1510_FPGA_AUDIO IOMEM(OMAP1510_FPGA_BASE + 0xc) -+#define OMAP1510_FPGA_DIP IOMEM(OMAP1510_FPGA_BASE + 0xe) -+#define OMAP1510_FPGA_FPGA_IO IOMEM(OMAP1510_FPGA_BASE + 0xf) -+#define OMAP1510_FPGA_UART1 IOMEM(OMAP1510_FPGA_BASE + 0x14) -+#define OMAP1510_FPGA_UART2 IOMEM(OMAP1510_FPGA_BASE + 0x15) -+#define OMAP1510_FPGA_OMAP1510_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x16) -+#define OMAP1510_FPGA_BOARD_REV IOMEM(OMAP1510_FPGA_BASE + 0x18) -+#define OMAP1510P1_PPT_DATA IOMEM(OMAP1510_FPGA_BASE + 0x100) -+#define OMAP1510P1_PPT_STATUS IOMEM(OMAP1510_FPGA_BASE + 0x101) -+#define OMAP1510P1_PPT_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x102) -+ -+#define OMAP1510_FPGA_TOUCHSCREEN IOMEM(OMAP1510_FPGA_BASE + 0x204) -+ -+#define INNOVATOR_FPGA_INFO IOMEM(OMAP1510_FPGA_BASE + 0x205) -+#define INNOVATOR_FPGA_LCD_BRIGHT_LO IOMEM(OMAP1510_FPGA_BASE + 0x206) -+#define INNOVATOR_FPGA_LCD_BRIGHT_HI IOMEM(OMAP1510_FPGA_BASE + 0x207) -+#define INNOVATOR_FPGA_LED_GRN_LO IOMEM(OMAP1510_FPGA_BASE + 0x208) -+#define INNOVATOR_FPGA_LED_GRN_HI IOMEM(OMAP1510_FPGA_BASE + 0x209) -+#define INNOVATOR_FPGA_LED_RED_LO IOMEM(OMAP1510_FPGA_BASE + 0x20a) -+#define INNOVATOR_FPGA_LED_RED_HI IOMEM(OMAP1510_FPGA_BASE + 0x20b) -+#define INNOVATOR_FPGA_CAM_USB_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20c) -+#define INNOVATOR_FPGA_EXP_CONTROL IOMEM(OMAP1510_FPGA_BASE + 0x20d) -+#define INNOVATOR_FPGA_ISR2 IOMEM(OMAP1510_FPGA_BASE + 0x20e) -+#define INNOVATOR_FPGA_IMR2 IOMEM(OMAP1510_FPGA_BASE + 0x210) - - #define OMAP1510_FPGA_ETHR_START (OMAP1510_FPGA_START + 0x300) - -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/gpmc.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/gpmc.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/gpmc.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/gpmc.h 2011-03-09 13:19:10.095501839 +0100 -@@ -41,6 +41,8 @@ - #define GPMC_NAND_ADDRESS 0x0000000b - #define GPMC_NAND_DATA 0x0000000c - -+#define GPMC_ENABLE_IRQ 0x0000000d -+ - /* ECC commands */ - #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ - #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ -@@ -78,6 +80,19 @@ - #define WR_RD_PIN_MONITORING 0x00600000 - #define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F) - #define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff) -+#define GPMC_IRQ_FIFOEVENTENABLE 0x01 -+#define GPMC_IRQ_COUNT_EVENT 0x02 -+ -+#define PREFETCH_FIFOTHRESHOLD_MAX 0x40 -+#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8) -+ -+enum omap_ecc { -+ /* 1-bit ecc: stored at end of spare area */ -+ OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */ -+ OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */ -+ /* 1-bit ecc: stored at begining of spare area as romcode */ -+ OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */ -+}; - - /* - * Note that all values in this struct are in nanoseconds except sync_clk -@@ -130,12 +145,11 @@ - extern void gpmc_cs_free(int cs); - extern int gpmc_cs_set_reserved(int cs, int reserved); - extern int gpmc_cs_reserved(int cs); --extern int gpmc_prefetch_enable(int cs, int dma_mode, -+extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode, - unsigned int u32_count, int is_write); - extern int gpmc_prefetch_reset(int cs); - extern void omap3_gpmc_save_context(void); - extern void omap3_gpmc_restore_context(void); --extern void gpmc_init(void); - extern int gpmc_read_status(int cmd); - extern int gpmc_cs_configure(int cs, int cmd, int wval); - extern int gpmc_nand_read(int cs, int cmd); -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/hardware.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/hardware.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/hardware.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/hardware.h 2011-03-09 13:19:10.096501820 +0100 -@@ -286,5 +286,6 @@ - #include - #include - #include -+#include - - #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/io.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/io.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/io.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/io.h 2011-03-09 13:19:10.096501820 +0100 -@@ -259,7 +259,7 @@ - extern void omap1_map_common_io(void); - extern void omap1_init_common_hw(void); - --#ifdef CONFIG_ARCH_OMAP2420 -+#ifdef CONFIG_SOC_OMAP2420 - extern void omap242x_map_common_io(void); - #else - static inline void omap242x_map_common_io(void) -@@ -267,7 +267,7 @@ - } - #endif - --#ifdef CONFIG_ARCH_OMAP2430 -+#ifdef CONFIG_SOC_OMAP2430 - extern void omap243x_map_common_io(void); - #else - static inline void omap243x_map_common_io(void) -@@ -283,6 +283,14 @@ - } - #endif - -+#ifdef CONFIG_SOC_OMAPTI816X -+extern void omapti816x_map_common_io(void); -+#else -+static inline void omapti816x_map_common_io(void) -+{ -+} -+#endif -+ - #ifdef CONFIG_ARCH_OMAP4 - extern void omap44xx_map_common_io(void); - #else -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/iommu.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/iommu.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/iommu.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/iommu.h 2011-03-09 13:19:10.096501820 +0100 -@@ -31,6 +31,7 @@ - struct clk *clk; - void __iomem *regbase; - struct device *dev; -+ void *isr_priv; - - unsigned int refcount; - struct mutex iommu_lock; /* global for this whole object */ -@@ -47,7 +48,7 @@ - struct list_head mmap; - struct mutex mmap_lock; /* protect mmap */ - -- int (*isr)(struct iommu *obj); -+ int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, void *priv); - - void *ctx; /* iommu context: registres saved area */ - u32 da_start; -@@ -109,6 +110,13 @@ - u32 da_end; - }; - -+/* IOMMU errors */ -+#define OMAP_IOMMU_ERR_TLB_MISS (1 << 0) -+#define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1) -+#define OMAP_IOMMU_ERR_EMU_MISS (1 << 2) -+#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 << 3) -+#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 << 4) -+ - #if defined(CONFIG_ARCH_OMAP1) - #error "iommu for this processor not implemented yet" - #else -@@ -154,11 +162,17 @@ - extern void flush_iotlb_all(struct iommu *obj); - - extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e); -+extern void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, -+ u32 **ppte); - extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova); - - extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end); - extern struct iommu *iommu_get(const char *name); - extern void iommu_put(struct iommu *obj); -+extern int iommu_set_isr(const char *name, -+ int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, -+ void *priv), -+ void *isr_priv); - - extern void iommu_save_ctx(struct iommu *obj); - extern void iommu_restore_ctx(struct iommu *obj); -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/irqs.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/irqs.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/irqs.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/irqs.h 2011-03-09 13:19:10.097501800 +0100 -@@ -318,6 +318,7 @@ - #define INT_34XX_PRCM_MPU_IRQ 11 - #define INT_34XX_MCBSP1_IRQ 16 - #define INT_34XX_MCBSP2_IRQ 17 -+#define INT_34XX_GPMC_IRQ 20 - #define INT_34XX_MCBSP3_IRQ 22 - #define INT_34XX_MCBSP4_IRQ 23 - #define INT_34XX_CAM_IRQ 24 -@@ -411,7 +412,13 @@ - #define TWL_IRQ_END TWL6030_IRQ_END - #endif - --#define NR_IRQS TWL_IRQ_END -+/* GPMC related */ -+#define OMAP_GPMC_IRQ_BASE (TWL_IRQ_END) -+#define OMAP_GPMC_NR_IRQS 7 -+#define OMAP_GPMC_IRQ_END (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS) -+ -+ -+#define NR_IRQS OMAP_GPMC_IRQ_END - - #define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) - -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/l3_2xxx.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/l3_2xxx.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/l3_2xxx.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/l3_2xxx.h 2011-03-09 13:19:10.097501800 +0100 -@@ -0,0 +1,20 @@ -+/* -+ * arch/arm/plat-omap/include/plat/l3_2xxx.h - L3 firewall definitions -+ * -+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -+ * Sumit Semwal -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ */ -+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H -+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_2XXX_H -+ -+/* L3 CONNIDs */ -+/* Display Sub system (DSS) */ -+#define OMAP2_L3_CORE_FW_CONNID_DSS 8 -+ -+#endif -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/l3_3xxx.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/l3_3xxx.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/l3_3xxx.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/l3_3xxx.h 2011-03-09 13:19:10.098501780 +0100 -@@ -0,0 +1,20 @@ -+/* -+ * arch/arm/plat-omap/include/plat/l3_3xxx.h - L3 firewall definitions -+ * -+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -+ * Sumit Semwal -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ */ -+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H -+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L3_3XXX_H -+ -+/* L3 Initiator IDs */ -+/* Display Sub system (DSS) */ -+#define OMAP3_L3_CORE_FW_INIT_ID_DSS 29 -+ -+#endif -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/l4_2xxx.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/l4_2xxx.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/l4_2xxx.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/l4_2xxx.h 2011-03-09 13:19:10.098501780 +0100 -@@ -0,0 +1,24 @@ -+/* -+ * arch/arm/plat-omap/include/plat/l4_2xxx.h - L4 firewall definitions -+ * -+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ -+ * Sumit Semwal -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ */ -+#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H -+#define __ARCH_ARM_PLAT_OMAP_INCLUDE_PLAT_L4_2XXX_H -+ -+/* L4 CORE */ -+/* Display Sub system (DSS) */ -+#define OMAP2420_L4_CORE_FW_DSS_CORE_REGION 28 -+#define OMAP2420_L4_CORE_FW_DSS_DISPC_REGION 29 -+#define OMAP2420_L4_CORE_FW_DSS_RFBI_REGION 30 -+#define OMAP2420_L4_CORE_FW_DSS_VENC_REGION 31 -+#define OMAP2420_L4_CORE_FW_DSS_TA_REGION 32 -+ -+#endif -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/l4_3xxx.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/l4_3xxx.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/l4_3xxx.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/l4_3xxx.h 2011-03-09 13:19:10.098501780 +0100 -@@ -21,4 +21,14 @@ - #define OMAP3_L4_CORE_FW_I2C3_REGION 73 - #define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74 - -+/* Display Sub system (DSS) */ -+#define OMAP3_L4_CORE_FW_DSS_PROT_GROUP 2 -+ -+#define OMAP3_L4_CORE_FW_DSS_DSI_REGION 104 -+#define OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION 3 -+#define OMAP3_L4_CORE_FW_DSS_CORE_REGION 4 -+#define OMAP3_L4_CORE_FW_DSS_DISPC_REGION 4 -+#define OMAP3_L4_CORE_FW_DSS_RFBI_REGION 5 -+#define OMAP3_L4_CORE_FW_DSS_VENC_REGION 6 -+#define OMAP3_L4_CORE_FW_DSS_TA_REGION 7 - #endif -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/mcbsp.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/mcbsp.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/mcbsp.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/mcbsp.h 2011-03-09 13:19:10.098501780 +0100 -@@ -37,6 +37,10 @@ - .id = OMAP_MCBSP##port_nr, \ - } - -+#define MCBSP_CONFIG_TYPE2 0x2 -+#define MCBSP_CONFIG_TYPE3 0x3 -+#define MCBSP_CONFIG_TYPE4 0x4 -+ - #define OMAP7XX_MCBSP1_BASE 0xfffb1000 - #define OMAP7XX_MCBSP2_BASE 0xfffb1800 - -@@ -48,32 +52,14 @@ - #define OMAP1610_MCBSP2_BASE 0xfffb1000 - #define OMAP1610_MCBSP3_BASE 0xe1017000 - --#define OMAP24XX_MCBSP1_BASE 0x48074000 --#define OMAP24XX_MCBSP2_BASE 0x48076000 --#define OMAP2430_MCBSP3_BASE 0x4808c000 --#define OMAP2430_MCBSP4_BASE 0x4808e000 --#define OMAP2430_MCBSP5_BASE 0x48096000 -- --#define OMAP34XX_MCBSP1_BASE 0x48074000 --#define OMAP34XX_MCBSP2_BASE 0x49022000 --#define OMAP34XX_MCBSP2_ST_BASE 0x49028000 --#define OMAP34XX_MCBSP3_BASE 0x49024000 --#define OMAP34XX_MCBSP3_ST_BASE 0x4902A000 --#define OMAP34XX_MCBSP3_BASE 0x49024000 --#define OMAP34XX_MCBSP4_BASE 0x49026000 --#define OMAP34XX_MCBSP5_BASE 0x48096000 -- --#define OMAP44XX_MCBSP1_BASE 0x49022000 --#define OMAP44XX_MCBSP2_BASE 0x49024000 --#define OMAP44XX_MCBSP3_BASE 0x49026000 --#define OMAP44XX_MCBSP4_BASE 0x48096000 -- --#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -+#ifdef CONFIG_ARCH_OMAP1 - - #define OMAP_MCBSP_REG_DRR2 0x00 - #define OMAP_MCBSP_REG_DRR1 0x02 - #define OMAP_MCBSP_REG_DXR2 0x04 - #define OMAP_MCBSP_REG_DXR1 0x06 -+#define OMAP_MCBSP_REG_DRR 0x02 -+#define OMAP_MCBSP_REG_DXR 0x06 - #define OMAP_MCBSP_REG_SPCR2 0x08 - #define OMAP_MCBSP_REG_SPCR1 0x0a - #define OMAP_MCBSP_REG_RCR2 0x0c -@@ -106,13 +92,6 @@ - #define OMAP_MCBSP_REG_XCCR 0x00 - #define OMAP_MCBSP_REG_RCCR 0x00 - --#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1) --#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1) -- --#define AUDIO_MCBSP OMAP_MCBSP1 --#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX --#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX -- - #else - - #define OMAP_MCBSP_REG_DRR2 0x00 -@@ -168,13 +147,6 @@ - #define OMAP_ST_REG_SFIRCR 0x28 - #define OMAP_ST_REG_SSELCR 0x2C - --#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) --#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) -- --#define AUDIO_MCBSP OMAP_MCBSP2 --#define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX --#define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX -- - #endif - - /************************** McBSP SPCR1 bit definitions ***********************/ -@@ -428,8 +400,9 @@ - #ifdef CONFIG_ARCH_OMAP3 - /* Sidetone block for McBSP 2 and 3 */ - unsigned long phys_base_st; -- u16 buffer_size; - #endif -+ u16 buffer_size; -+ unsigned int mcbsp_config_type; - }; - - struct omap_mcbsp_st_data { -@@ -445,6 +418,7 @@ - struct omap_mcbsp { - struct device *dev; - unsigned long phys_base; -+ unsigned long phys_dma_base; - void __iomem *io_base; - u8 id; - u8 free; -@@ -471,7 +445,6 @@ - /* Protect the field .free, while checking if the mcbsp is in use */ - spinlock_t lock; - struct omap_mcbsp_platform_data *pdata; -- struct clk *iclk; - struct clk *fclk; - #ifdef CONFIG_ARCH_OMAP3 - struct omap_mcbsp_st_data *st_data; -@@ -480,7 +453,17 @@ - u16 max_rx_thres; - #endif - void *reg_cache; -+ unsigned int mcbsp_config_type; -+}; -+ -+/** -+ * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod -+ * @sidetone: name of the sidetone device -+ */ -+struct omap_mcbsp_dev_attr { -+ const char *sidetone; - }; -+ - extern struct omap_mcbsp **mcbsp_ptr; - extern int omap_mcbsp_count, omap_mcbsp_cache_size; - -@@ -488,8 +471,8 @@ - #define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; - - int omap_mcbsp_init(void); --void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, -- int size); -+void omap_mcbsp_register_board_cfg(struct resource *res, int res_count, -+ struct omap_mcbsp_platform_data *config, int size); - void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); - #ifdef CONFIG_ARCH_OMAP3 - void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); -@@ -539,6 +522,9 @@ - void omap2_mcbsp1_mux_clkr_src(u8 mux); - void omap2_mcbsp1_mux_fsr_src(u8 mux); - -+int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream); -+int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream); -+ - #ifdef CONFIG_ARCH_OMAP3 - /* Sidetone specific API */ - int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/mcspi.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/mcspi.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/mcspi.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/mcspi.h 2011-03-09 13:19:10.098501780 +0100 -@@ -1,8 +1,19 @@ - #ifndef _OMAP2_MCSPI_H - #define _OMAP2_MCSPI_H - -+#define OMAP2_MCSPI_REV 0 -+#define OMAP3_MCSPI_REV 1 -+#define OMAP4_MCSPI_REV 2 -+ -+#define OMAP4_MCSPI_REG_OFFSET 0x100 -+ - struct omap2_mcspi_platform_config { - unsigned short num_cs; -+ unsigned int regs_offset; -+}; -+ -+struct omap2_mcspi_dev_attr { -+ unsigned short num_chipselect; - }; - - struct omap2_mcspi_device_config { -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/mmc.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/mmc.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/mmc.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/mmc.h 2011-03-09 13:19:10.099501760 +0100 -@@ -24,25 +24,19 @@ - #define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */ - - #define OMAP24XX_NR_MMC 2 --#define OMAP34XX_NR_MMC 3 --#define OMAP44XX_NR_MMC 5 - #define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE --#define OMAP3_HSMMC_SIZE 0x200 --#define OMAP4_HSMMC_SIZE 0x1000 - #define OMAP2_MMC1_BASE 0x4809c000 --#define OMAP2_MMC2_BASE 0x480b4000 --#define OMAP3_MMC3_BASE 0x480ad000 --#define OMAP4_MMC4_BASE 0x480d1000 --#define OMAP4_MMC5_BASE 0x480d5000 -+ - #define OMAP4_MMC_REG_OFFSET 0x100 --#define HSMMC5 (1 << 4) --#define HSMMC4 (1 << 3) --#define HSMMC3 (1 << 2) --#define HSMMC2 (1 << 1) --#define HSMMC1 (1 << 0) - - #define OMAP_MMC_MAX_SLOTS 2 - -+#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(1) -+ -+struct omap_mmc_dev_attr { -+ u8 flags; -+}; -+ - struct omap_mmc_platform_data { - /* back-link to device */ - struct device *dev; -@@ -71,6 +65,9 @@ - - u64 dma_mask; - -+ /* Integrating attributes from the omap_hwmod layer */ -+ u8 controller_flags; -+ - /* Register offset deviation */ - u16 reg_offset; - -@@ -159,8 +156,7 @@ - defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) - void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, - int nr_controllers); --void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, -- int nr_controllers); -+void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data); - int omap_mmc_add(const char *name, int id, unsigned long base, - unsigned long size, unsigned int irq, - struct omap_mmc_platform_data *data); -@@ -169,8 +165,7 @@ - int nr_controllers) - { - } --static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, -- int nr_controllers) -+static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data) - { - } - static inline int omap_mmc_add(const char *name, int id, unsigned long base, -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/multi.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/multi.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/multi.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/multi.h 2011-03-09 13:19:10.099501760 +0100 -@@ -66,7 +66,7 @@ - # error "OMAP1 and OMAP2PLUS can't be selected at the same time" - # endif - #endif --#ifdef CONFIG_ARCH_OMAP2420 -+#ifdef CONFIG_SOC_OMAP2420 - # ifdef OMAP_NAME - # undef MULTI_OMAP2 - # define MULTI_OMAP2 -@@ -74,7 +74,7 @@ - # define OMAP_NAME omap2420 - # endif - #endif --#ifdef CONFIG_ARCH_OMAP2430 -+#ifdef CONFIG_SOC_OMAP2430 - # ifdef OMAP_NAME - # undef MULTI_OMAP2 - # define MULTI_OMAP2 -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/nand.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/nand.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/nand.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/nand.h 2011-03-09 13:19:10.100501740 +0100 -@@ -8,8 +8,16 @@ - * published by the Free Software Foundation. - */ - -+#include - #include - -+enum nand_io { -+ NAND_OMAP_PREFETCH_POLLED = 0, /* prefetch polled mode, default */ -+ NAND_OMAP_POLLED, /* polled mode, without prefetch */ -+ NAND_OMAP_PREFETCH_DMA, /* prefetch enabled sDMA mode */ -+ NAND_OMAP_PREFETCH_IRQ /* prefetch enabled irq mode */ -+}; -+ - struct omap_nand_platform_data { - unsigned int options; - int cs; -@@ -20,8 +28,11 @@ - int (*nand_setup)(void); - int (*dev_ready)(struct omap_nand_platform_data *); - int dma_channel; -+ int gpmc_irq; -+ enum nand_io xfer_type; - unsigned long phys_base; - int devsize; -+ enum omap_ecc ecc_opt; - }; - - /* minimum size for IO mapping */ -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/omap_hwmod.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/omap_hwmod.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/omap_hwmod.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/omap_hwmod.h 2011-03-09 13:19:10.102501700 +0100 -@@ -1,7 +1,7 @@ - /* - * omap_hwmod macros, structures - * -- * Copyright (C) 2009-2010 Nokia Corporation -+ * Copyright (C) 2009-2011 Nokia Corporation - * Paul Walmsley - * - * Created in collaboration with (alphabetical order): Benoît Cousson, -@@ -30,6 +30,7 @@ - #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H - - #include -+#include - #include - #include - #include -@@ -178,7 +179,8 @@ - #define ADDR_TYPE_RT (1 << 1) - - /** -- * struct omap_hwmod_addr_space - MPU address space handled by the hwmod -+ * struct omap_hwmod_addr_space - address space handled by the hwmod -+ * @name: name of the address space - * @pa_start: starting physical address - * @pa_end: ending physical address - * @flags: (see omap_hwmod_addr_space.flags macros above) -@@ -187,6 +189,7 @@ - * structure. GPMC is one example. - */ - struct omap_hwmod_addr_space { -+ const char *name; - u32 pa_start; - u32 pa_end; - u8 flags; -@@ -370,8 +373,10 @@ - * of standby, rather than relying on module smart-standby - * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for - * SDRAM controller, etc. XXX probably belongs outside the main hwmod file -+ * XXX Should be HWMOD_SETUP_NO_RESET - * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM - * controller, etc. XXX probably belongs outside the main hwmod file -+ * XXX Should be HWMOD_SETUP_NO_IDLE - * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE) - * when module is enabled, rather than the default, which is to - * enable autoidle -@@ -535,11 +540,12 @@ - const struct omap_chip_id omap_chip; - }; - --int omap_hwmod_init(struct omap_hwmod **ohs); -+int omap_hwmod_register(struct omap_hwmod **ohs); - struct omap_hwmod *omap_hwmod_lookup(const char *name); - int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), - void *data); --int omap_hwmod_late_init(void); -+ -+int __init omap_hwmod_setup_one(const char *name); - - int omap_hwmod_enable(struct omap_hwmod *oh); - int _omap_hwmod_enable(struct omap_hwmod *oh); -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/onenand.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/onenand.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/onenand.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/onenand.h 2011-03-09 13:19:10.102501700 +0100 -@@ -15,12 +15,20 @@ - #define ONENAND_SYNC_READ (1 << 0) - #define ONENAND_SYNC_READWRITE (1 << 1) - -+struct onenand_freq_info { -+ u16 maf_id; -+ u16 dev_id; -+ u16 ver_id; -+}; -+ - struct omap_onenand_platform_data { - int cs; - int gpio_irq; - struct mtd_partition *parts; - int nr_parts; -- int (*onenand_setup)(void __iomem *, int freq); -+ int (*onenand_setup)(void __iomem *, int *freq_ptr); -+ int (*get_freq)(const struct onenand_freq_info *freq_info, -+ bool *clk_dep); - int dma_channel; - u8 flags; - u8 regulator_can_sleep; -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/prcm.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/prcm.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/prcm.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/prcm.h 2011-03-09 13:19:10.102501700 +0100 -@@ -28,7 +28,6 @@ - #define __ASM_ARM_ARCH_OMAP_PRCM_H - - u32 omap_prcm_get_reset_sources(void); --void omap_prcm_arch_reset(char mode, const char *cmd); - int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, - const char *name); - -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/sdrc.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/sdrc.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/sdrc.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/sdrc.h 2011-03-09 13:19:10.102501700 +0100 -@@ -124,8 +124,14 @@ - u32 mr; - }; - --void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, -+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) -+void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, - struct omap_sdrc_params *sdrc_cs1); -+#else -+static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, -+ struct omap_sdrc_params *sdrc_cs1) {}; -+#endif -+ - int omap2_sdrc_get_params(unsigned long r, - struct omap_sdrc_params **sdrc_cs0, - struct omap_sdrc_params **sdrc_cs1); -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/serial.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/serial.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/serial.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/serial.h 2011-03-09 13:19:10.103501679 +0100 -@@ -51,6 +51,11 @@ - #define OMAP4_UART3_BASE 0x48020000 - #define OMAP4_UART4_BASE 0x4806e000 - -+/* TI816X serial ports */ -+#define TI816X_UART1_BASE 0x48020000 -+#define TI816X_UART2_BASE 0x48022000 -+#define TI816X_UART3_BASE 0x48024000 -+ - /* External port on Zoom2/3 */ - #define ZOOM_UART_BASE 0x10000000 - #define ZOOM_UART_VIRT 0xfa400000 -@@ -81,6 +86,9 @@ - #define OMAP4UART2 OMAP2UART2 - #define OMAP4UART3 43 - #define OMAP4UART4 44 -+#define TI816XUART1 81 -+#define TI816XUART2 82 -+#define TI816XUART3 83 - #define ZOOM_UART 95 /* Only on zoom2/3 */ - - /* This is only used by 8250.c for omap1510 */ -@@ -96,7 +104,6 @@ - - struct omap_board_data; - --extern void __init omap_serial_early_init(void); - extern void omap_serial_init(void); - extern void omap_serial_init_port(struct omap_board_data *bdata); - extern int omap_uart_can_sleep(void); -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/system.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/system.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/system.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/system.h 2011-03-09 13:19:10.103501679 +0100 -@@ -4,48 +4,14 @@ - */ - #ifndef __ASM_ARCH_SYSTEM_H - #define __ASM_ARCH_SYSTEM_H --#include - --#include --#include -- --#include -- --#ifndef CONFIG_MACH_VOICEBLUE --#define voiceblue_reset() do {} while (0) --#else --extern void voiceblue_reset(void); --#endif -+#include - - static inline void arch_idle(void) - { - cpu_do_idle(); - } - --static inline void omap1_arch_reset(char mode, const char *cmd) --{ -- /* -- * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28 -- * "Global Software Reset Affects Traffic Controller Frequency". -- */ -- if (cpu_is_omap5912()) { -- omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), -- DPLL_CTL); -- omap_writew(0x8, ARM_RSTCT1); -- } -- -- if (machine_is_voiceblue()) -- voiceblue_reset(); -- else -- omap_writew(1, ARM_RSTCT1); --} -- --static inline void arch_reset(char mode, const char *cmd) --{ -- if (!cpu_class_is_omap2()) -- omap1_arch_reset(mode, cmd); -- else -- omap_prcm_arch_reset(mode, cmd); --} -+extern void (*arch_reset)(char, const char *); - - #endif -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/ti816x.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/ti816x.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/ti816x.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/ti816x.h 2011-03-09 13:19:10.103501679 +0100 -@@ -0,0 +1,27 @@ -+/* -+ * This file contains the address data for various TI816X modules. -+ * -+ * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation version 2. -+ * -+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any -+ * kind, whether express or implied; without even the implied warranty -+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef __ASM_ARCH_TI816X_H -+#define __ASM_ARCH_TI816X_H -+ -+#define L4_SLOW_TI816X_BASE 0x48000000 -+ -+#define TI816X_SCM_BASE 0x48140000 -+#define TI816X_CTRL_BASE TI816X_SCM_BASE -+#define TI816X_PRCM_BASE 0x48180000 -+ -+#define TI816X_ARM_INTC_BASE 0x48200000 -+ -+#endif /* __ASM_ARCH_TI816X_H */ -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/uncompress.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/uncompress.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/uncompress.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/uncompress.h 2011-03-09 13:19:10.104501658 +0100 -@@ -93,6 +93,10 @@ - #define DEBUG_LL_ZOOM(mach) \ - _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART) - -+#define DEBUG_LL_TI816X(p, mach) \ -+ _DEBUG_LL_ENTRY(mach, TI816X_UART##p##_BASE, OMAP_PORT_SHIFT, \ -+ TI816XUART##p) -+ - static inline void __arch_decomp_setup(unsigned long arch_id) - { - int port = 0; -@@ -166,6 +170,9 @@ - DEBUG_LL_ZOOM(omap_zoom2); - DEBUG_LL_ZOOM(omap_zoom3); - -+ /* TI8168 base boards using UART3 */ -+ DEBUG_LL_TI816X(3, ti8168evm); -+ - } while (0); - } - -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/usb.h linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/usb.h ---- linux-2.6.38-rc7/arch/arm/plat-omap/include/plat/usb.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/include/plat/usb.h 2011-03-09 13:19:10.104501658 +0100 -@@ -91,6 +91,10 @@ - - #endif - -+extern void am35x_musb_reset(void); -+extern void am35x_musb_phy_power(u8 on); -+extern void am35x_musb_clear_irq(void); -+extern void am35x_musb_set_mode(u8 musb_mode); - - /* - * FIXME correct answer depends on hmc_mode, -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/io.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/io.c ---- linux-2.6.38-rc7/arch/arm/plat-omap/io.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/io.c 2011-03-09 13:19:10.104501658 +0100 -@@ -85,7 +85,10 @@ - } - #endif - #ifdef CONFIG_ARCH_OMAP3 -- if (cpu_is_omap34xx()) { -+ if (cpu_is_ti816x()) { -+ if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE)) -+ return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT); -+ } else if (cpu_is_omap34xx()) { - if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE)) - return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT); - if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE)) -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/iommu.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/iommu.c ---- linux-2.6.38-rc7/arch/arm/plat-omap/iommu.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/iommu.c 2011-03-09 13:19:10.105501637 +0100 -@@ -104,6 +104,9 @@ - if (!obj) - return -EINVAL; - -+ if (!arch_iommu) -+ return -ENODEV; -+ - clk_enable(obj->clk); - - err = arch_iommu->enable(obj); -@@ -780,25 +783,19 @@ - */ - static irqreturn_t iommu_fault_handler(int irq, void *data) - { -- u32 stat, da; -+ u32 da, errs; - u32 *iopgd, *iopte; -- int err = -EIO; - struct iommu *obj = data; - - if (!obj->refcount) - return IRQ_NONE; - -- /* Dynamic loading TLB or PTE */ -- if (obj->isr) -- err = obj->isr(obj); -- -- if (!err) -- return IRQ_HANDLED; -- - clk_enable(obj->clk); -- stat = iommu_report_fault(obj, &da); -+ errs = iommu_report_fault(obj, &da); - clk_disable(obj->clk); -- if (!stat) -+ -+ /* Fault callback or TLB/PTE Dynamic loading */ -+ if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv)) - return IRQ_HANDLED; - - iommu_disable(obj); -@@ -806,15 +803,16 @@ - iopgd = iopgd_offset(obj, da); - - if (!iopgd_is_table(*iopgd)) { -- dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__, -- da, iopgd, *iopgd); -+ dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p " -+ "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd); - return IRQ_NONE; - } - - iopte = iopte_offset(iopgd, da); - -- dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", -- __func__, da, iopgd, *iopgd, iopte, *iopte); -+ dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x " -+ "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd, -+ iopte, *iopte); - - return IRQ_NONE; - } -@@ -917,6 +915,33 @@ - } - EXPORT_SYMBOL_GPL(iommu_put); - -+int iommu_set_isr(const char *name, -+ int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, -+ void *priv), -+ void *isr_priv) -+{ -+ struct device *dev; -+ struct iommu *obj; -+ -+ dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name, -+ device_match_by_alias); -+ if (!dev) -+ return -ENODEV; -+ -+ obj = to_iommu(dev); -+ mutex_lock(&obj->iommu_lock); -+ if (obj->refcount != 0) { -+ mutex_unlock(&obj->iommu_lock); -+ return -EBUSY; -+ } -+ obj->isr = isr; -+ obj->isr_priv = isr_priv; -+ mutex_unlock(&obj->iommu_lock); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(iommu_set_isr); -+ - /* - * OMAP Device MMU(IOMMU) detection - */ -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/mcbsp.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/mcbsp.c ---- linux-2.6.38-rc7/arch/arm/plat-omap/mcbsp.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/mcbsp.c 2011-03-09 13:19:10.106501616 +0100 -@@ -27,6 +27,8 @@ - - #include - #include -+#include -+#include - - /* XXX These "sideways" includes are a sign that something is wrong */ - #include "../mach-omap2/cm2xxx_3xxx.h" -@@ -227,10 +229,83 @@ - } - EXPORT_SYMBOL(omap_mcbsp_config); - -+/** -+ * omap_mcbsp_dma_params - returns the dma channel number -+ * @id - mcbsp id -+ * @stream - indicates the direction of data flow (rx or tx) -+ * -+ * Returns the dma channel number for the rx channel or tx channel -+ * based on the value of @stream for the requested mcbsp given by @id -+ */ -+int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream) -+{ -+ struct omap_mcbsp *mcbsp; -+ -+ if (!omap_mcbsp_check_valid_id(id)) { -+ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); -+ return -ENODEV; -+ } -+ mcbsp = id_to_mcbsp_ptr(id); -+ -+ if (stream) -+ return mcbsp->dma_rx_sync; -+ else -+ return mcbsp->dma_tx_sync; -+} -+EXPORT_SYMBOL(omap_mcbsp_dma_ch_params); -+ -+/** -+ * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register -+ * @id - mcbsp id -+ * @stream - indicates the direction of data flow (rx or tx) -+ * -+ * Returns the address of mcbsp data transmit register or data receive register -+ * to be used by DMA for transferring/receiving data based on the value of -+ * @stream for the requested mcbsp given by @id -+ */ -+int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream) -+{ -+ struct omap_mcbsp *mcbsp; -+ int data_reg; -+ -+ if (!omap_mcbsp_check_valid_id(id)) { -+ printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); -+ return -ENODEV; -+ } -+ mcbsp = id_to_mcbsp_ptr(id); -+ -+ data_reg = mcbsp->phys_dma_base; -+ -+ if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) { -+ if (stream) -+ data_reg += OMAP_MCBSP_REG_DRR1; -+ else -+ data_reg += OMAP_MCBSP_REG_DXR1; -+ } else { -+ if (stream) -+ data_reg += OMAP_MCBSP_REG_DRR; -+ else -+ data_reg += OMAP_MCBSP_REG_DXR; -+ } -+ -+ return data_reg; -+} -+EXPORT_SYMBOL(omap_mcbsp_dma_reg_params); -+ - #ifdef CONFIG_ARCH_OMAP3 -+static struct omap_device *find_omap_device_by_dev(struct device *dev) -+{ -+ struct platform_device *pdev = container_of(dev, -+ struct platform_device, dev); -+ return container_of(pdev, struct omap_device, pdev); -+} -+ - static void omap_st_on(struct omap_mcbsp *mcbsp) - { - unsigned int w; -+ struct omap_device *od; -+ -+ od = find_omap_device_by_dev(mcbsp->dev); - - /* - * Sidetone uses McBSP ICLK - which must not idle when sidetones -@@ -244,9 +319,6 @@ - w = MCBSP_READ(mcbsp, SSELCR); - MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN); - -- w = MCBSP_ST_READ(mcbsp, SYSCONFIG); -- MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE)); -- - /* Enable Sidetone from Sidetone Core */ - w = MCBSP_ST_READ(mcbsp, SSELCR); - MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN); -@@ -255,13 +327,13 @@ - static void omap_st_off(struct omap_mcbsp *mcbsp) - { - unsigned int w; -+ struct omap_device *od; -+ -+ od = find_omap_device_by_dev(mcbsp->dev); - - w = MCBSP_ST_READ(mcbsp, SSELCR); - MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN)); - -- w = MCBSP_ST_READ(mcbsp, SYSCONFIG); -- MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE); -- - w = MCBSP_READ(mcbsp, SSELCR); - MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN)); - -@@ -273,9 +345,9 @@ - static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir) - { - u16 val, i; -+ struct omap_device *od; - -- val = MCBSP_ST_READ(mcbsp, SYSCONFIG); -- MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE)); -+ od = find_omap_device_by_dev(mcbsp->dev); - - val = MCBSP_ST_READ(mcbsp, SSELCR); - -@@ -303,9 +375,9 @@ - { - u16 w; - struct omap_mcbsp_st_data *st_data = mcbsp->st_data; -+ struct omap_device *od; - -- w = MCBSP_ST_READ(mcbsp, SYSCONFIG); -- MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE)); -+ od = find_omap_device_by_dev(mcbsp->dev); - - w = MCBSP_ST_READ(mcbsp, SSELCR); - -@@ -648,48 +720,33 @@ - - static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) - { -+ struct omap_device *od; -+ -+ od = find_omap_device_by_dev(mcbsp->dev); - /* - * Enable wakup behavior, smart idle and all wakeups - * REVISIT: some wakeups may be unnecessary - */ - if (cpu_is_omap34xx() || cpu_is_omap44xx()) { -- u16 syscon; -- -- syscon = MCBSP_READ(mcbsp, SYSCON); -- syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); -- -- if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) { -- syscon |= (ENAWAKEUP | SIDLEMODE(0x02) | -- CLOCKACTIVITY(0x02)); -- MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN); -- } else { -- syscon |= SIDLEMODE(0x01); -- } -- -- MCBSP_WRITE(mcbsp, SYSCON, syscon); -+ MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN); - } - } - - static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) - { -+ struct omap_device *od; -+ -+ od = find_omap_device_by_dev(mcbsp->dev); -+ - /* - * Disable wakup behavior, smart idle and all wakeups - */ - if (cpu_is_omap34xx() || cpu_is_omap44xx()) { -- u16 syscon; -- -- syscon = MCBSP_READ(mcbsp, SYSCON); -- syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03)); - /* - * HW bug workaround - If no_idle mode is taken, we need to - * go to smart_idle before going to always_idle, or the - * device will not hit retention anymore. - */ -- syscon |= SIDLEMODE(0x02); -- MCBSP_WRITE(mcbsp, SYSCON, syscon); -- -- syscon &= ~(SIDLEMODE(0x03)); -- MCBSP_WRITE(mcbsp, SYSCON, syscon); - - MCBSP_WRITE(mcbsp, WAKEUPEN, 0); - } -@@ -764,8 +821,7 @@ - if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request) - mcbsp->pdata->ops->request(id); - -- clk_enable(mcbsp->iclk); -- clk_enable(mcbsp->fclk); -+ pm_runtime_get_sync(mcbsp->dev); - - /* Do procedure specific to omap34xx arch, if applicable */ - omap34xx_mcbsp_request(mcbsp); -@@ -813,8 +869,7 @@ - /* Do procedure specific to omap34xx arch, if applicable */ - omap34xx_mcbsp_free(mcbsp); - -- clk_disable(mcbsp->fclk); -- clk_disable(mcbsp->iclk); -+ pm_runtime_put_sync(mcbsp->dev); - - spin_lock(&mcbsp->lock); - mcbsp->free = true; -@@ -844,8 +899,7 @@ - /* Do procedure specific to omap34xx arch, if applicable */ - omap34xx_mcbsp_free(mcbsp); - -- clk_disable(mcbsp->fclk); -- clk_disable(mcbsp->iclk); -+ pm_runtime_put_sync(mcbsp->dev); - - if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { - /* Free IRQs */ -@@ -1649,7 +1703,8 @@ - - static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) - { -- struct omap_mcbsp_platform_data *pdata = mcbsp->pdata; -+ struct platform_device *pdev; -+ struct resource *res; - struct omap_mcbsp_st_data *st_data; - int err; - -@@ -1659,7 +1714,10 @@ - goto err1; - } - -- st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K); -+ pdev = container_of(mcbsp->dev, struct platform_device, dev); -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone"); -+ st_data->io_base_st = ioremap(res->start, resource_size(res)); - if (!st_data->io_base_st) { - err = -ENOMEM; - goto err2; -@@ -1748,6 +1806,7 @@ - struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data; - struct omap_mcbsp *mcbsp; - int id = pdev->id - 1; -+ struct resource *res; - int ret = 0; - - if (!pdata) { -@@ -1777,47 +1836,78 @@ - mcbsp->dma_tx_lch = -1; - mcbsp->dma_rx_lch = -1; - -- mcbsp->phys_base = pdata->phys_base; -- mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K); -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); -+ if (!res) { -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory" -+ "resource\n", __func__, pdev->id); -+ ret = -ENOMEM; -+ goto exit; -+ } -+ } -+ mcbsp->phys_base = res->start; -+ omap_mcbsp_cache_size = resource_size(res); -+ mcbsp->io_base = ioremap(res->start, resource_size(res)); - if (!mcbsp->io_base) { - ret = -ENOMEM; - goto err_ioremap; - } - -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma"); -+ if (!res) -+ mcbsp->phys_dma_base = mcbsp->phys_base; -+ else -+ mcbsp->phys_dma_base = res->start; -+ - /* Default I/O is IRQ based */ - mcbsp->io_type = OMAP_MCBSP_IRQ_IO; -- mcbsp->tx_irq = pdata->tx_irq; -- mcbsp->rx_irq = pdata->rx_irq; -- mcbsp->dma_rx_sync = pdata->dma_rx_sync; -- mcbsp->dma_tx_sync = pdata->dma_tx_sync; -- -- mcbsp->iclk = clk_get(&pdev->dev, "ick"); -- if (IS_ERR(mcbsp->iclk)) { -- ret = PTR_ERR(mcbsp->iclk); -- dev_err(&pdev->dev, "unable to get ick: %d\n", ret); -- goto err_iclk; -+ -+ mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx"); -+ mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx"); -+ -+ /* From OMAP4 there will be a single irq line */ -+ if (mcbsp->tx_irq == -ENXIO) -+ mcbsp->tx_irq = platform_get_irq(pdev, 0); -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); -+ if (!res) { -+ dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n", -+ __func__, pdev->id); -+ ret = -ENODEV; -+ goto err_res; -+ } -+ mcbsp->dma_rx_sync = res->start; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); -+ if (!res) { -+ dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n", -+ __func__, pdev->id); -+ ret = -ENODEV; -+ goto err_res; - } -+ mcbsp->dma_tx_sync = res->start; - - mcbsp->fclk = clk_get(&pdev->dev, "fck"); - if (IS_ERR(mcbsp->fclk)) { - ret = PTR_ERR(mcbsp->fclk); - dev_err(&pdev->dev, "unable to get fck: %d\n", ret); -- goto err_fclk; -+ goto err_res; - } - - mcbsp->pdata = pdata; - mcbsp->dev = &pdev->dev; - mcbsp_ptr[id] = mcbsp; -+ mcbsp->mcbsp_config_type = pdata->mcbsp_config_type; - platform_set_drvdata(pdev, mcbsp); -+ pm_runtime_enable(mcbsp->dev); - - /* Initialize mcbsp properties for OMAP34XX if needed / applicable */ - omap34xx_device_init(mcbsp); - - return 0; - --err_fclk: -- clk_put(mcbsp->iclk); --err_iclk: -+err_res: - iounmap(mcbsp->io_base); - err_ioremap: - kfree(mcbsp); -@@ -1839,7 +1929,6 @@ - omap34xx_device_exit(mcbsp); - - clk_put(mcbsp->fclk); -- clk_put(mcbsp->iclk); - - iounmap(mcbsp->io_base); - kfree(mcbsp); -diff -Naur linux-2.6.38-rc7/arch/arm/plat-omap/sram.c linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/sram.c ---- linux-2.6.38-rc7/arch/arm/plat-omap/sram.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/arch/arm/plat-omap/sram.c 2011-03-09 13:19:10.107501596 +0100 -@@ -312,7 +312,7 @@ - } - #endif - --#ifdef CONFIG_ARCH_OMAP2420 -+#ifdef CONFIG_SOC_OMAP2420 - static int __init omap242x_sram_init(void) - { - _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init, -@@ -333,7 +333,7 @@ - } - #endif - --#ifdef CONFIG_ARCH_OMAP2430 -+#ifdef CONFIG_SOC_OMAP2430 - static int __init omap243x_sram_init(void) - { - _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init, -@@ -405,20 +405,6 @@ - } - #endif - --#ifdef CONFIG_ARCH_OMAP4 --static int __init omap44xx_sram_init(void) --{ -- printk(KERN_ERR "FIXME: %s not implemented\n", __func__); -- -- return -ENODEV; --} --#else --static inline int omap44xx_sram_init(void) --{ -- return 0; --} --#endif -- - int __init omap_sram_init(void) - { - omap_detect_sram(); -@@ -432,8 +418,6 @@ - omap243x_sram_init(); - else if (cpu_is_omap34xx()) - omap34xx_sram_init(); -- else if (cpu_is_omap44xx()) -- omap44xx_sram_init(); - - return 0; - } -diff -Naur linux-2.6.38-rc7/Documentation/hwspinlock.txt linux-2.6.38-rc7-linux-omap-dss2/Documentation/hwspinlock.txt ---- linux-2.6.38-rc7/Documentation/hwspinlock.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/Documentation/hwspinlock.txt 2011-03-09 13:19:09.179520421 +0100 -@@ -0,0 +1,293 @@ -+Hardware Spinlock Framework -+ -+1. Introduction -+ -+Hardware spinlock modules provide hardware assistance for synchronization -+and mutual exclusion between heterogeneous processors and those not operating -+under a single, shared operating system. -+ -+For example, OMAP4 has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP, -+each of which is running a different Operating System (the master, A9, -+is usually running Linux and the slave processors, the M3 and the DSP, -+are running some flavor of RTOS). -+ -+A generic hwspinlock framework allows platform-independent drivers to use -+the hwspinlock device in order to access data structures that are shared -+between remote processors, that otherwise have no alternative mechanism -+to accomplish synchronization and mutual exclusion operations. -+ -+This is necessary, for example, for Inter-processor communications: -+on OMAP4, cpu-intensive multimedia tasks are offloaded by the host to the -+remote M3 and/or C64x+ slave processors (by an IPC subsystem called Syslink). -+ -+To achieve fast message-based communications, a minimal kernel support -+is needed to deliver messages arriving from a remote processor to the -+appropriate user process. -+ -+This communication is based on simple data structures that is shared between -+the remote processors, and access to it is synchronized using the hwspinlock -+module (remote processor directly places new messages in this shared data -+structure). -+ -+A common hwspinlock interface makes it possible to have generic, platform- -+independent, drivers. -+ -+2. User API -+ -+ struct hwspinlock *hwspin_lock_request(void); -+ - dynamically assign an hwspinlock and return its address, or NULL -+ in case an unused hwspinlock isn't available. Users of this -+ API will usually want to communicate the lock's id to the remote core -+ before it can be used to achieve synchronization. -+ Can be called from an atomic context (this function will not sleep) but -+ not from within interrupt context. -+ -+ struct hwspinlock *hwspin_lock_request_specific(unsigned int id); -+ - assign a specific hwspinlock id and return its address, or NULL -+ if that hwspinlock is already in use. Usually board code will -+ be calling this function in order to reserve specific hwspinlock -+ ids for predefined purposes. -+ Can be called from an atomic context (this function will not sleep) but -+ not from within interrupt context. -+ -+ int hwspin_lock_free(struct hwspinlock *hwlock); -+ - free a previously-assigned hwspinlock; returns 0 on success, or an -+ appropriate error code on failure (e.g. -EINVAL if the hwspinlock -+ is already free). -+ Can be called from an atomic context (this function will not sleep) but -+ not from within interrupt context. -+ -+ int hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int timeout); -+ - lock a previously-assigned hwspinlock with a timeout limit (specified in -+ msecs). If the hwspinlock is already taken, the function will busy loop -+ waiting for it to be released, but give up when the timeout elapses. -+ Upon a successful return from this function, preemption is disabled so -+ the caller must not sleep, and is advised to release the hwspinlock as -+ soon as possible, in order to minimize remote cores polling on the -+ hardware interconnect. -+ Returns 0 when successful and an appropriate error code otherwise (most -+ notably -ETIMEDOUT if the hwspinlock is still busy after timeout msecs). -+ The function will never sleep. -+ -+ int hwspin_lock_timeout_irq(struct hwspinlock *hwlock, unsigned int timeout); -+ - lock a previously-assigned hwspinlock with a timeout limit (specified in -+ msecs). If the hwspinlock is already taken, the function will busy loop -+ waiting for it to be released, but give up when the timeout elapses. -+ Upon a successful return from this function, preemption and the local -+ interrupts are disabled, so the caller must not sleep, and is advised to -+ release the hwspinlock as soon as possible. -+ Returns 0 when successful and an appropriate error code otherwise (most -+ notably -ETIMEDOUT if the hwspinlock is still busy after timeout msecs). -+ The function will never sleep. -+ -+ int hwspin_lock_timeout_irqsave(struct hwspinlock *hwlock, unsigned int to, -+ unsigned long *flags); -+ - lock a previously-assigned hwspinlock with a timeout limit (specified in -+ msecs). If the hwspinlock is already taken, the function will busy loop -+ waiting for it to be released, but give up when the timeout elapses. -+ Upon a successful return from this function, preemption is disabled, -+ local interrupts are disabled and their previous state is saved at the -+ given flags placeholder. The caller must not sleep, and is advised to -+ release the hwspinlock as soon as possible. -+ Returns 0 when successful and an appropriate error code otherwise (most -+ notably -ETIMEDOUT if the hwspinlock is still busy after timeout msecs). -+ The function will never sleep. -+ -+ int hwspin_trylock(struct hwspinlock *hwlock); -+ - attempt to lock a previously-assigned hwspinlock, but immediately fail if -+ it is already taken. -+ Upon a successful return from this function, preemption is disabled so -+ caller must not sleep, and is advised to release the hwspinlock as soon as -+ possible, in order to minimize remote cores polling on the hardware -+ interconnect. -+ Returns 0 on success and an appropriate error code otherwise (most -+ notably -EBUSY if the hwspinlock was already taken). -+ The function will never sleep. -+ -+ int hwspin_trylock_irq(struct hwspinlock *hwlock); -+ - attempt to lock a previously-assigned hwspinlock, but immediately fail if -+ it is already taken. -+ Upon a successful return from this function, preemption and the local -+ interrupts are disabled so caller must not sleep, and is advised to -+ release the hwspinlock as soon as possible. -+ Returns 0 on success and an appropriate error code otherwise (most -+ notably -EBUSY if the hwspinlock was already taken). -+ The function will never sleep. -+ -+ int hwspin_trylock_irqsave(struct hwspinlock *hwlock, unsigned long *flags); -+ - attempt to lock a previously-assigned hwspinlock, but immediately fail if -+ it is already taken. -+ Upon a successful return from this function, preemption is disabled, -+ the local interrupts are disabled and their previous state is saved -+ at the given flags placeholder. The caller must not sleep, and is advised -+ to release the hwspinlock as soon as possible. -+ Returns 0 on success and an appropriate error code otherwise (most -+ notably -EBUSY if the hwspinlock was already taken). -+ The function will never sleep. -+ -+ void hwspin_unlock(struct hwspinlock *hwlock); -+ - unlock a previously-locked hwspinlock. Always succeed, and can be called -+ from any context (the function never sleeps). Note: code should _never_ -+ unlock an hwspinlock which is already unlocked (there is no protection -+ against this). -+ -+ void hwspin_unlock_irq(struct hwspinlock *hwlock); -+ - unlock a previously-locked hwspinlock and enable local interrupts. -+ The caller should _never_ unlock an hwspinlock which is already unlocked. -+ Doing so is considered a bug (there is no protection against this). -+ Upon a successful return from this function, preemption and local -+ interrupts are enabled. This function will never sleep. -+ -+ void -+ hwspin_unlock_irqrestore(struct hwspinlock *hwlock, unsigned long *flags); -+ - unlock a previously-locked hwspinlock. -+ The caller should _never_ unlock an hwspinlock which is already unlocked. -+ Doing so is considered a bug (there is no protection against this). -+ Upon a successful return from this function, preemption is reenabled, -+ and the state of the local interrupts is restored to the state saved at -+ the given flags. This function will never sleep. -+ -+ int hwspin_lock_get_id(struct hwspinlock *hwlock); -+ - retrieve id number of a given hwspinlock. This is needed when an -+ hwspinlock is dynamically assigned: before it can be used to achieve -+ mutual exclusion with a remote cpu, the id number should be communicated -+ to the remote task with which we want to synchronize. -+ Returns the hwspinlock id number, or -EINVAL if hwlock is null. -+ -+3. Typical usage -+ -+#include -+#include -+ -+int hwspinlock_example1(void) -+{ -+ struct hwspinlock *hwlock; -+ int ret; -+ -+ /* dynamically assign a hwspinlock */ -+ hwlock = hwspin_lock_request(); -+ if (!hwlock) -+ ... -+ -+ id = hwspin_lock_get_id(hwlock); -+ /* probably need to communicate id to a remote processor now */ -+ -+ /* take the lock, spin for 1 sec if it's already taken */ -+ ret = hwspin_lock_timeout(hwlock, 1000); -+ if (ret) -+ ... -+ -+ /* -+ * we took the lock, do our thing now, but do NOT sleep -+ */ -+ -+ /* release the lock */ -+ hwspin_unlock(hwlock); -+ -+ /* free the lock */ -+ ret = hwspin_lock_free(hwlock); -+ if (ret) -+ ... -+ -+ return ret; -+} -+ -+int hwspinlock_example2(void) -+{ -+ struct hwspinlock *hwlock; -+ int ret; -+ -+ /* -+ * assign a specific hwspinlock id - this should be called early -+ * by board init code. -+ */ -+ hwlock = hwspin_lock_request_specific(PREDEFINED_LOCK_ID); -+ if (!hwlock) -+ ... -+ -+ /* try to take it, but don't spin on it */ -+ ret = hwspin_trylock(hwlock); -+ if (!ret) { -+ pr_info("lock is already taken\n"); -+ return -EBUSY; -+ } -+ -+ /* -+ * we took the lock, do our thing now, but do NOT sleep -+ */ -+ -+ /* release the lock */ -+ hwspin_unlock(hwlock); -+ -+ /* free the lock */ -+ ret = hwspin_lock_free(hwlock); -+ if (ret) -+ ... -+ -+ return ret; -+} -+ -+ -+4. API for implementors -+ -+ int hwspin_lock_register(struct hwspinlock *hwlock); -+ - to be called from the underlying platform-specific implementation, in -+ order to register a new hwspinlock instance. Can be called from an atomic -+ context (this function will not sleep) but not from within interrupt -+ context. Returns 0 on success, or appropriate error code on failure. -+ -+ struct hwspinlock *hwspin_lock_unregister(unsigned int id); -+ - to be called from the underlying vendor-specific implementation, in order -+ to unregister an existing (and unused) hwspinlock instance. -+ Can be called from an atomic context (will not sleep) but not from -+ within interrupt context. -+ Returns the address of hwspinlock on success, or NULL on error (e.g. -+ if the hwspinlock is sill in use). -+ -+5. struct hwspinlock -+ -+This struct represents an hwspinlock instance. It is registered by the -+underlying hwspinlock implementation using the hwspin_lock_register() API. -+ -+/** -+ * struct hwspinlock - vendor-specific hwspinlock implementation -+ * -+ * @dev: underlying device, will be used with runtime PM api -+ * @ops: vendor-specific hwspinlock handlers -+ * @id: a global, unique, system-wide, index of the lock. -+ * @lock: initialized and used by hwspinlock core -+ * @owner: underlying implementation module, used to maintain module ref count -+ */ -+struct hwspinlock { -+ struct device *dev; -+ const struct hwspinlock_ops *ops; -+ int id; -+ spinlock_t lock; -+ struct module *owner; -+}; -+ -+The underlying implementation is responsible to assign the dev, ops, id and -+owner members. The lock member, OTOH, is initialized and used by the hwspinlock -+core. -+ -+6. Implementation callbacks -+ -+There are three possible callbacks defined in 'struct hwspinlock_ops': -+ -+struct hwspinlock_ops { -+ int (*trylock)(struct hwspinlock *lock); -+ void (*unlock)(struct hwspinlock *lock); -+ void (*relax)(struct hwspinlock *lock); -+}; -+ -+The first two callbacks are mandatory: -+ -+The ->trylock() callback should make a single attempt to take the lock, and -+return 0 on failure and 1 on success. This callback may _not_ sleep. -+ -+The ->unlock() callback releases the lock. It always succeed, and it, too, -+may _not_ sleep. -+ -+The ->relax() callback is optional. It is called by hwspinlock core while -+spinning on a lock, and can be used by the underlying implementation to force -+a delay between two successive invocations of ->trylock(). It may _not_ sleep. -diff -Naur linux-2.6.38-rc7/drivers/hwspinlock/hwspinlock_core.c linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/hwspinlock_core.c ---- linux-2.6.38-rc7/drivers/hwspinlock/hwspinlock_core.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/hwspinlock_core.c 2011-03-09 13:19:13.374435328 +0100 -@@ -0,0 +1,548 @@ -+/* -+ * Hardware spinlock framework -+ * -+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com -+ * -+ * Contact: Ohad Ben-Cohen -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#define pr_fmt(fmt) "%s: " fmt, __func__ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "hwspinlock_internal.h" -+ -+/* radix tree tags */ -+#define HWSPINLOCK_UNUSED (0) /* tags an hwspinlock as unused */ -+ -+/* -+ * A radix tree is used to maintain the available hwspinlock instances. -+ * The tree associates hwspinlock pointers with their integer key id, -+ * and provides easy-to-use API which makes the hwspinlock core code simple -+ * and easy to read. -+ * -+ * Radix trees are quick on lookups, and reasonably efficient in terms of -+ * storage, especially with high density usages such as this framework -+ * requires (a continuous range of integer keys, beginning with zero, is -+ * used as the ID's of the hwspinlock instances). -+ * -+ * The radix tree API supports tagging items in the tree, which this -+ * framework uses to mark unused hwspinlock instances (see the -+ * HWSPINLOCK_UNUSED tag above). As a result, the process of querying the -+ * tree, looking for an unused hwspinlock instance, is now reduced to a -+ * single radix tree API call. -+ */ -+static RADIX_TREE(hwspinlock_tree, GFP_KERNEL); -+ -+/* -+ * Synchronization of access to the tree is achieved using this spinlock, -+ * as the radix-tree API requires that users provide all synchronisation. -+ */ -+static DEFINE_SPINLOCK(hwspinlock_tree_lock); -+ -+/** -+ * __hwspin_trylock() - attempt to lock a specific hwspinlock -+ * @hwlock: an hwspinlock which we want to trylock -+ * @mode: controls whether local interrupts are disabled or not -+ * @flags: a pointer where the caller's interrupt state will be saved at (if -+ * requested) -+ * -+ * This function attempts to lock an hwspinlock, and will immediately -+ * fail if the hwspinlock is already taken. -+ * -+ * Upon a successful return from this function, preemption (and possibly -+ * interrupts) is disabled, so the caller must not sleep, and is advised to -+ * release the hwspinlock as soon as possible. This is required in order to -+ * minimize remote cores polling on the hardware interconnect. -+ * -+ * The user decides whether local interrupts are disabled or not, and if yes, -+ * whether he wants their previous state to be saved. It is up to the user -+ * to choose the appropriate @mode of operation, exactly the same way users -+ * should decide between spin_trylock, spin_trylock_irq and -+ * spin_trylock_irqsave. -+ * -+ * Returns 0 if we successfully locked the hwspinlock or -EBUSY if -+ * the hwspinlock was already taken. -+ * This function will never sleep. -+ */ -+int __hwspin_trylock(struct hwspinlock *hwlock, int mode, unsigned long *flags) -+{ -+ int ret; -+ -+ BUG_ON(!hwlock); -+ BUG_ON(!flags && mode == HWLOCK_IRQSTATE); -+ -+ /* -+ * This spin_lock{_irq, _irqsave} serves three purposes: -+ * -+ * 1. Disable preemption, in order to minimize the period of time -+ * in which the hwspinlock is taken. This is important in order -+ * to minimize the possible polling on the hardware interconnect -+ * by a remote user of this lock. -+ * 2. Make the hwspinlock SMP-safe (so we can take it from -+ * additional contexts on the local host). -+ * 3. Ensure that in_atomic/might_sleep checks catch potential -+ * problems with hwspinlock usage (e.g. scheduler checks like -+ * 'scheduling while atomic' etc.) -+ */ -+ if (mode == HWLOCK_IRQSTATE) -+ ret = spin_trylock_irqsave(&hwlock->lock, *flags); -+ else if (mode == HWLOCK_IRQ) -+ ret = spin_trylock_irq(&hwlock->lock); -+ else -+ ret = spin_trylock(&hwlock->lock); -+ -+ /* is lock already taken by another context on the local cpu ? */ -+ if (!ret) -+ return -EBUSY; -+ -+ /* try to take the hwspinlock device */ -+ ret = hwlock->ops->trylock(hwlock); -+ -+ /* if hwlock is already taken, undo spin_trylock_* and exit */ -+ if (!ret) { -+ if (mode == HWLOCK_IRQSTATE) -+ spin_unlock_irqrestore(&hwlock->lock, *flags); -+ else if (mode == HWLOCK_IRQ) -+ spin_unlock_irq(&hwlock->lock); -+ else -+ spin_unlock(&hwlock->lock); -+ -+ return -EBUSY; -+ } -+ -+ /* -+ * We can be sure the other core's memory operations -+ * are observable to us only _after_ we successfully take -+ * the hwspinlock, and we must make sure that subsequent memory -+ * operations (both reads and writes) will not be reordered before -+ * we actually took the hwspinlock. -+ * -+ * Note: the implicit memory barrier of the spinlock above is too -+ * early, so we need this additional explicit memory barrier. -+ */ -+ mb(); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(__hwspin_trylock); -+ -+/** -+ * __hwspin_lock_timeout() - lock an hwspinlock with timeout limit -+ * @hwlock: the hwspinlock to be locked -+ * @timeout: timeout value in msecs -+ * @mode: mode which controls whether local interrupts are disabled or not -+ * @flags: a pointer to where the caller's interrupt state will be saved at (if -+ * requested) -+ * -+ * This function locks the given @hwlock. If the @hwlock -+ * is already taken, the function will busy loop waiting for it to -+ * be released, but give up after @timeout msecs have elapsed. -+ * -+ * Upon a successful return from this function, preemption is disabled -+ * (and possibly local interrupts, too), so the caller must not sleep, -+ * and is advised to release the hwspinlock as soon as possible. -+ * This is required in order to minimize remote cores polling on the -+ * hardware interconnect. -+ * -+ * The user decides whether local interrupts are disabled or not, and if yes, -+ * whether he wants their previous state to be saved. It is up to the user -+ * to choose the appropriate @mode of operation, exactly the same way users -+ * should decide between spin_lock, spin_lock_irq and spin_lock_irqsave. -+ * -+ * Returns 0 when the @hwlock was successfully taken, and an appropriate -+ * error code otherwise (most notably -ETIMEDOUT if the @hwlock is still -+ * busy after @timeout msecs). The function will never sleep. -+ */ -+int __hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int to, -+ int mode, unsigned long *flags) -+{ -+ int ret; -+ unsigned long expire; -+ -+ expire = msecs_to_jiffies(to) + jiffies; -+ -+ for (;;) { -+ /* Try to take the hwspinlock */ -+ ret = __hwspin_trylock(hwlock, mode, flags); -+ if (ret != -EBUSY) -+ break; -+ -+ /* -+ * The lock is already taken, let's check if the user wants -+ * us to try again -+ */ -+ if (time_is_before_eq_jiffies(expire)) -+ return -ETIMEDOUT; -+ -+ /* -+ * Allow platform-specific relax handlers to prevent -+ * hogging the interconnect (no sleeping, though) -+ */ -+ if (hwlock->ops->relax) -+ hwlock->ops->relax(hwlock); -+ } -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(__hwspin_lock_timeout); -+ -+/** -+ * __hwspin_unlock() - unlock a specific hwspinlock -+ * @hwlock: a previously-acquired hwspinlock which we want to unlock -+ * @mode: controls whether local interrupts needs to be restored or not -+ * @flags: previous caller's interrupt state to restore (if requested) -+ * -+ * This function will unlock a specific hwspinlock, enable preemption and -+ * (possibly) enable interrupts or restore their previous state. -+ * @hwlock must be already locked before calling this function: it is a bug -+ * to call unlock on a @hwlock that is already unlocked. -+ * -+ * The user decides whether local interrupts should be enabled or not, and -+ * if yes, whether he wants their previous state to be restored. It is up -+ * to the user to choose the appropriate @mode of operation, exactly the -+ * same way users decide between spin_unlock, spin_unlock_irq and -+ * spin_unlock_irqrestore. -+ * -+ * The function will never sleep. -+ */ -+void __hwspin_unlock(struct hwspinlock *hwlock, int mode, unsigned long *flags) -+{ -+ BUG_ON(!hwlock); -+ BUG_ON(!flags && mode == HWLOCK_IRQSTATE); -+ -+ /* -+ * We must make sure that memory operations (both reads and writes), -+ * done before unlocking the hwspinlock, will not be reordered -+ * after the lock is released. -+ * -+ * That's the purpose of this explicit memory barrier. -+ * -+ * Note: the memory barrier induced by the spin_unlock below is too -+ * late; the other core is going to access memory soon after it will -+ * take the hwspinlock, and by then we want to be sure our memory -+ * operations are already observable. -+ */ -+ mb(); -+ -+ hwlock->ops->unlock(hwlock); -+ -+ /* Undo the spin_trylock{_irq, _irqsave} called while locking */ -+ if (mode == HWLOCK_IRQSTATE) -+ spin_unlock_irqrestore(&hwlock->lock, *flags); -+ else if (mode == HWLOCK_IRQ) -+ spin_unlock_irq(&hwlock->lock); -+ else -+ spin_unlock(&hwlock->lock); -+} -+EXPORT_SYMBOL_GPL(__hwspin_unlock); -+ -+/** -+ * hwspin_lock_register() - register a new hw spinlock -+ * @hwlock: hwspinlock to register. -+ * -+ * This function should be called from the underlying platform-specific -+ * implementation, to register a new hwspinlock instance. -+ * -+ * Can be called from an atomic context (will not sleep) but not from -+ * within interrupt context. -+ * -+ * Returns 0 on success, or an appropriate error code on failure -+ */ -+int hwspin_lock_register(struct hwspinlock *hwlock) -+{ -+ struct hwspinlock *tmp; -+ int ret; -+ -+ if (!hwlock || !hwlock->ops || -+ !hwlock->ops->trylock || !hwlock->ops->unlock) { -+ pr_err("invalid parameters\n"); -+ return -EINVAL; -+ } -+ -+ spin_lock_init(&hwlock->lock); -+ -+ spin_lock(&hwspinlock_tree_lock); -+ -+ ret = radix_tree_insert(&hwspinlock_tree, hwlock->id, hwlock); -+ if (ret) -+ goto out; -+ -+ /* mark this hwspinlock as available */ -+ tmp = radix_tree_tag_set(&hwspinlock_tree, hwlock->id, -+ HWSPINLOCK_UNUSED); -+ -+ /* self-sanity check which should never fail */ -+ WARN_ON(tmp != hwlock); -+ -+out: -+ spin_unlock(&hwspinlock_tree_lock); -+ return ret; -+} -+EXPORT_SYMBOL_GPL(hwspin_lock_register); -+ -+/** -+ * hwspin_lock_unregister() - unregister an hw spinlock -+ * @id: index of the specific hwspinlock to unregister -+ * -+ * This function should be called from the underlying platform-specific -+ * implementation, to unregister an existing (and unused) hwspinlock. -+ * -+ * Can be called from an atomic context (will not sleep) but not from -+ * within interrupt context. -+ * -+ * Returns the address of hwspinlock @id on success, or NULL on failure -+ */ -+struct hwspinlock *hwspin_lock_unregister(unsigned int id) -+{ -+ struct hwspinlock *hwlock = NULL; -+ int ret; -+ -+ spin_lock(&hwspinlock_tree_lock); -+ -+ /* make sure the hwspinlock is not in use (tag is set) */ -+ ret = radix_tree_tag_get(&hwspinlock_tree, id, HWSPINLOCK_UNUSED); -+ if (ret == 0) { -+ pr_err("hwspinlock %d still in use (or not present)\n", id); -+ goto out; -+ } -+ -+ hwlock = radix_tree_delete(&hwspinlock_tree, id); -+ if (!hwlock) { -+ pr_err("failed to delete hwspinlock %d\n", id); -+ goto out; -+ } -+ -+out: -+ spin_unlock(&hwspinlock_tree_lock); -+ return hwlock; -+} -+EXPORT_SYMBOL_GPL(hwspin_lock_unregister); -+ -+/** -+ * __hwspin_lock_request() - tag an hwspinlock as used and power it up -+ * -+ * This is an internal function that prepares an hwspinlock instance -+ * before it is given to the user. The function assumes that -+ * hwspinlock_tree_lock is taken. -+ * -+ * Returns 0 or positive to indicate success, and a negative value to -+ * indicate an error (with the appropriate error code) -+ */ -+static int __hwspin_lock_request(struct hwspinlock *hwlock) -+{ -+ struct hwspinlock *tmp; -+ int ret; -+ -+ /* prevent underlying implementation from being removed */ -+ if (!try_module_get(hwlock->owner)) { -+ dev_err(hwlock->dev, "%s: can't get owner\n", __func__); -+ return -EINVAL; -+ } -+ -+ /* notify PM core that power is now needed */ -+ ret = pm_runtime_get_sync(hwlock->dev); -+ if (ret < 0) { -+ dev_err(hwlock->dev, "%s: can't power on device\n", __func__); -+ return ret; -+ } -+ -+ /* mark hwspinlock as used, should not fail */ -+ tmp = radix_tree_tag_clear(&hwspinlock_tree, hwlock->id, -+ HWSPINLOCK_UNUSED); -+ -+ /* self-sanity check that should never fail */ -+ WARN_ON(tmp != hwlock); -+ -+ return ret; -+} -+ -+/** -+ * hwspin_lock_get_id() - retrieve id number of a given hwspinlock -+ * @hwlock: a valid hwspinlock instance -+ * -+ * Returns the id number of a given @hwlock, or -EINVAL if @hwlock is invalid. -+ */ -+int hwspin_lock_get_id(struct hwspinlock *hwlock) -+{ -+ if (!hwlock) { -+ pr_err("invalid hwlock\n"); -+ return -EINVAL; -+ } -+ -+ return hwlock->id; -+} -+EXPORT_SYMBOL_GPL(hwspin_lock_get_id); -+ -+/** -+ * hwspin_lock_request() - request an hwspinlock -+ * -+ * This function should be called by users of the hwspinlock device, -+ * in order to dynamically assign them an unused hwspinlock. -+ * Usually the user of this lock will then have to communicate the lock's id -+ * to the remote core before it can be used for synchronization (to get the -+ * id of a given hwlock, use hwspin_lock_get_id()). -+ * -+ * Can be called from an atomic context (will not sleep) but not from -+ * within interrupt context (simply because there is no use case for -+ * that yet). -+ * -+ * Returns the address of the assigned hwspinlock, or NULL on error -+ */ -+struct hwspinlock *hwspin_lock_request(void) -+{ -+ struct hwspinlock *hwlock; -+ int ret; -+ -+ spin_lock(&hwspinlock_tree_lock); -+ -+ /* look for an unused lock */ -+ ret = radix_tree_gang_lookup_tag(&hwspinlock_tree, (void **)&hwlock, -+ 0, 1, HWSPINLOCK_UNUSED); -+ if (ret == 0) { -+ pr_warn("a free hwspinlock is not available\n"); -+ hwlock = NULL; -+ goto out; -+ } -+ -+ /* sanity check that should never fail */ -+ WARN_ON(ret > 1); -+ -+ /* mark as used and power up */ -+ ret = __hwspin_lock_request(hwlock); -+ if (ret < 0) -+ hwlock = NULL; -+ -+out: -+ spin_unlock(&hwspinlock_tree_lock); -+ return hwlock; -+} -+EXPORT_SYMBOL_GPL(hwspin_lock_request); -+ -+/** -+ * hwspin_lock_request_specific() - request for a specific hwspinlock -+ * @id: index of the specific hwspinlock that is requested -+ * -+ * This function should be called by users of the hwspinlock module, -+ * in order to assign them a specific hwspinlock. -+ * Usually early board code will be calling this function in order to -+ * reserve specific hwspinlock ids for predefined purposes. -+ * -+ * Can be called from an atomic context (will not sleep) but not from -+ * within interrupt context (simply because there is no use case for -+ * that yet). -+ * -+ * Returns the address of the assigned hwspinlock, or NULL on error -+ */ -+struct hwspinlock *hwspin_lock_request_specific(unsigned int id) -+{ -+ struct hwspinlock *hwlock; -+ int ret; -+ -+ spin_lock(&hwspinlock_tree_lock); -+ -+ /* make sure this hwspinlock exists */ -+ hwlock = radix_tree_lookup(&hwspinlock_tree, id); -+ if (!hwlock) { -+ pr_warn("hwspinlock %u does not exist\n", id); -+ goto out; -+ } -+ -+ /* sanity check (this shouldn't happen) */ -+ WARN_ON(hwlock->id != id); -+ -+ /* make sure this hwspinlock is unused */ -+ ret = radix_tree_tag_get(&hwspinlock_tree, id, HWSPINLOCK_UNUSED); -+ if (ret == 0) { -+ pr_warn("hwspinlock %u is already in use\n", id); -+ hwlock = NULL; -+ goto out; -+ } -+ -+ /* mark as used and power up */ -+ ret = __hwspin_lock_request(hwlock); -+ if (ret < 0) -+ hwlock = NULL; -+ -+out: -+ spin_unlock(&hwspinlock_tree_lock); -+ return hwlock; -+} -+EXPORT_SYMBOL_GPL(hwspin_lock_request_specific); -+ -+/** -+ * hwspin_lock_free() - free a specific hwspinlock -+ * @hwlock: the specific hwspinlock to free -+ * -+ * This function mark @hwlock as free again. -+ * Should only be called with an @hwlock that was retrieved from -+ * an earlier call to omap_hwspin_lock_request{_specific}. -+ * -+ * Can be called from an atomic context (will not sleep) but not from -+ * within interrupt context (simply because there is no use case for -+ * that yet). -+ * -+ * Returns 0 on success, or an appropriate error code on failure -+ */ -+int hwspin_lock_free(struct hwspinlock *hwlock) -+{ -+ struct hwspinlock *tmp; -+ int ret; -+ -+ if (!hwlock) { -+ pr_err("invalid hwlock\n"); -+ return -EINVAL; -+ } -+ -+ spin_lock(&hwspinlock_tree_lock); -+ -+ /* make sure the hwspinlock is used */ -+ ret = radix_tree_tag_get(&hwspinlock_tree, hwlock->id, -+ HWSPINLOCK_UNUSED); -+ if (ret == 1) { -+ dev_err(hwlock->dev, "%s: hwlock is already free\n", __func__); -+ dump_stack(); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ /* notify the underlying device that power is not needed */ -+ ret = pm_runtime_put(hwlock->dev); -+ if (ret < 0) -+ goto out; -+ -+ /* mark this hwspinlock as available */ -+ tmp = radix_tree_tag_set(&hwspinlock_tree, hwlock->id, -+ HWSPINLOCK_UNUSED); -+ -+ /* sanity check (this shouldn't happen) */ -+ WARN_ON(tmp != hwlock); -+ -+ module_put(hwlock->owner); -+ -+out: -+ spin_unlock(&hwspinlock_tree_lock); -+ return ret; -+} -+EXPORT_SYMBOL_GPL(hwspin_lock_free); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_DESCRIPTION("Hardware spinlock interface"); -+MODULE_AUTHOR("Ohad Ben-Cohen "); -diff -Naur linux-2.6.38-rc7/drivers/hwspinlock/hwspinlock_internal.h linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/hwspinlock_internal.h ---- linux-2.6.38-rc7/drivers/hwspinlock/hwspinlock_internal.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/hwspinlock_internal.h 2011-03-09 13:19:13.374435328 +0100 -@@ -0,0 +1,61 @@ -+/* -+ * Hardware spinlocks internal header -+ * -+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com -+ * -+ * Contact: Ohad Ben-Cohen -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef __HWSPINLOCK_HWSPINLOCK_H -+#define __HWSPINLOCK_HWSPINLOCK_H -+ -+#include -+#include -+ -+/** -+ * struct hwspinlock_ops - platform-specific hwspinlock handlers -+ * -+ * @trylock: make a single attempt to take the lock. returns 0 on -+ * failure and true on success. may _not_ sleep. -+ * @unlock: release the lock. always succeed. may _not_ sleep. -+ * @relax: optional, platform-specific relax handler, called by hwspinlock -+ * core while spinning on a lock, between two successive -+ * invocations of @trylock. may _not_ sleep. -+ */ -+struct hwspinlock_ops { -+ int (*trylock)(struct hwspinlock *lock); -+ void (*unlock)(struct hwspinlock *lock); -+ void (*relax)(struct hwspinlock *lock); -+}; -+ -+/** -+ * struct hwspinlock - this struct represents a single hwspinlock instance -+ * -+ * @dev: underlying device, will be used to invoke runtime PM api -+ * @ops: platform-specific hwspinlock handlers -+ * @id: a global, unique, system-wide, index of the lock. -+ * @lock: initialized and used by hwspinlock core -+ * @owner: underlying implementation module, used to maintain module ref count -+ * -+ * Note: currently simplicity was opted for, but later we can squeeze some -+ * memory bytes by grouping the dev, ops and owner members in a single -+ * per-platform struct, and have all hwspinlocks point at it. -+ */ -+struct hwspinlock { -+ struct device *dev; -+ const struct hwspinlock_ops *ops; -+ int id; -+ spinlock_t lock; -+ struct module *owner; -+}; -+ -+#endif /* __HWSPINLOCK_HWSPINLOCK_H */ -diff -Naur linux-2.6.38-rc7/drivers/hwspinlock/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/Kconfig ---- linux-2.6.38-rc7/drivers/hwspinlock/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/Kconfig 2011-03-09 13:19:13.373435348 +0100 -@@ -0,0 +1,22 @@ -+# -+# Generic HWSPINLOCK framework -+# -+ -+config HWSPINLOCK -+ tristate "Generic Hardware Spinlock framework" -+ help -+ Say y here to support the generic hardware spinlock framework. -+ You only need to enable this if you have hardware spinlock module -+ on your system (usually only relevant if your system has remote slave -+ coprocessors). -+ -+ If unsure, say N. -+ -+config HWSPINLOCK_OMAP -+ tristate "OMAP Hardware Spinlock device" -+ depends on HWSPINLOCK && ARCH_OMAP4 -+ help -+ Say y here to support the OMAP Hardware Spinlock device (firstly -+ introduced in OMAP4). -+ -+ If unsure, say N. -diff -Naur linux-2.6.38-rc7/drivers/hwspinlock/Makefile linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/Makefile ---- linux-2.6.38-rc7/drivers/hwspinlock/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/Makefile 2011-03-09 13:19:13.374435328 +0100 -@@ -0,0 +1,6 @@ -+# -+# Generic Hardware Spinlock framework -+# -+ -+obj-$(CONFIG_HWSPINLOCK) += hwspinlock_core.o -+obj-$(CONFIG_HWSPINLOCK_OMAP) += omap_hwspinlock.o -diff -Naur linux-2.6.38-rc7/drivers/hwspinlock/omap_hwspinlock.c linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/omap_hwspinlock.c ---- linux-2.6.38-rc7/drivers/hwspinlock/omap_hwspinlock.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/hwspinlock/omap_hwspinlock.c 2011-03-09 13:19:13.374435328 +0100 -@@ -0,0 +1,231 @@ -+/* -+ * OMAP hardware spinlock driver -+ * -+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com -+ * -+ * Contact: Simon Que -+ * Hari Kanigeri -+ * Ohad Ben-Cohen -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "hwspinlock_internal.h" -+ -+/* Spinlock register offsets */ -+#define SYSSTATUS_OFFSET 0x0014 -+#define LOCK_BASE_OFFSET 0x0800 -+ -+#define SPINLOCK_NUMLOCKS_BIT_OFFSET (24) -+ -+/* Possible values of SPINLOCK_LOCK_REG */ -+#define SPINLOCK_NOTTAKEN (0) /* free */ -+#define SPINLOCK_TAKEN (1) /* locked */ -+ -+#define to_omap_hwspinlock(lock) \ -+ container_of(lock, struct omap_hwspinlock, lock) -+ -+struct omap_hwspinlock { -+ struct hwspinlock lock; -+ void __iomem *addr; -+}; -+ -+struct omap_hwspinlock_state { -+ int num_locks; /* Total number of locks in system */ -+ void __iomem *io_base; /* Mapped base address */ -+}; -+ -+static int omap_hwspinlock_trylock(struct hwspinlock *lock) -+{ -+ struct omap_hwspinlock *omap_lock = to_omap_hwspinlock(lock); -+ -+ /* attempt to acquire the lock by reading its value */ -+ return (SPINLOCK_NOTTAKEN == readl(omap_lock->addr)); -+} -+ -+static void omap_hwspinlock_unlock(struct hwspinlock *lock) -+{ -+ struct omap_hwspinlock *omap_lock = to_omap_hwspinlock(lock); -+ -+ /* release the lock by writing 0 to it */ -+ writel(SPINLOCK_NOTTAKEN, omap_lock->addr); -+} -+ -+/* -+ * relax the OMAP interconnect while spinning on it. -+ * -+ * The specs recommended that the retry delay time will be -+ * just over half of the time that a requester would be -+ * expected to hold the lock. -+ * -+ * The number below is taken from an hardware specs example, -+ * obviously it is somewhat arbitrary. -+ */ -+static void omap_hwspinlock_relax(struct hwspinlock *lock) -+{ -+ ndelay(50); -+} -+ -+static const struct hwspinlock_ops omap_hwspinlock_ops = { -+ .trylock = omap_hwspinlock_trylock, -+ .unlock = omap_hwspinlock_unlock, -+ .relax = omap_hwspinlock_relax, -+}; -+ -+static int __devinit omap_hwspinlock_probe(struct platform_device *pdev) -+{ -+ struct omap_hwspinlock *omap_lock; -+ struct omap_hwspinlock_state *state; -+ struct hwspinlock *lock; -+ struct resource *res; -+ void __iomem *io_base; -+ int i, ret; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) -+ return -ENODEV; -+ -+ state = kzalloc(sizeof(*state), GFP_KERNEL); -+ if (!state) -+ return -ENOMEM; -+ -+ io_base = ioremap(res->start, resource_size(res)); -+ if (!io_base) { -+ ret = -ENOMEM; -+ goto free_state; -+ } -+ -+ /* Determine number of locks */ -+ i = readl(io_base + SYSSTATUS_OFFSET); -+ i >>= SPINLOCK_NUMLOCKS_BIT_OFFSET; -+ -+ /* one of the four lsb's must be set, and nothing else */ -+ if (hweight_long(i & 0xf) != 1 || i > 8) { -+ ret = -EINVAL; -+ goto iounmap_base; -+ } -+ -+ state->num_locks = i * 32; -+ state->io_base = io_base; -+ -+ platform_set_drvdata(pdev, state); -+ -+ /* -+ * runtime PM will make sure the clock of this module is -+ * enabled iff at least one lock is requested -+ */ -+ pm_runtime_enable(&pdev->dev); -+ -+ for (i = 0; i < state->num_locks; i++) { -+ omap_lock = kzalloc(sizeof(*omap_lock), GFP_KERNEL); -+ if (!omap_lock) { -+ ret = -ENOMEM; -+ goto free_locks; -+ } -+ -+ omap_lock->lock.dev = &pdev->dev; -+ omap_lock->lock.owner = THIS_MODULE; -+ omap_lock->lock.id = i; -+ omap_lock->lock.ops = &omap_hwspinlock_ops; -+ omap_lock->addr = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i; -+ -+ ret = hwspin_lock_register(&omap_lock->lock); -+ if (ret) { -+ kfree(omap_lock); -+ goto free_locks; -+ } -+ } -+ -+ return 0; -+ -+free_locks: -+ while (--i >= 0) { -+ lock = hwspin_lock_unregister(i); -+ /* this should't happen, but let's give our best effort */ -+ if (!lock) { -+ dev_err(&pdev->dev, "%s: cleanups failed\n", __func__); -+ continue; -+ } -+ omap_lock = to_omap_hwspinlock(lock); -+ kfree(omap_lock); -+ } -+ pm_runtime_disable(&pdev->dev); -+iounmap_base: -+ iounmap(io_base); -+free_state: -+ kfree(state); -+ return ret; -+} -+ -+static int omap_hwspinlock_remove(struct platform_device *pdev) -+{ -+ struct omap_hwspinlock_state *state = platform_get_drvdata(pdev); -+ struct hwspinlock *lock; -+ struct omap_hwspinlock *omap_lock; -+ int i; -+ -+ for (i = 0; i < state->num_locks; i++) { -+ lock = hwspin_lock_unregister(i); -+ /* this shouldn't happen at this point. if it does, at least -+ * don't continue with the remove */ -+ if (!lock) { -+ dev_err(&pdev->dev, "%s: failed on %d\n", __func__, i); -+ return -EBUSY; -+ } -+ -+ omap_lock = to_omap_hwspinlock(lock); -+ kfree(omap_lock); -+ } -+ -+ pm_runtime_disable(&pdev->dev); -+ iounmap(state->io_base); -+ kfree(state); -+ -+ return 0; -+} -+ -+static struct platform_driver omap_hwspinlock_driver = { -+ .probe = omap_hwspinlock_probe, -+ .remove = omap_hwspinlock_remove, -+ .driver = { -+ .name = "omap_hwspinlock", -+ }, -+}; -+ -+static int __init omap_hwspinlock_init(void) -+{ -+ return platform_driver_register(&omap_hwspinlock_driver); -+} -+/* board init code might need to reserve hwspinlocks for predefined purposes */ -+postcore_initcall(omap_hwspinlock_init); -+ -+static void __exit omap_hwspinlock_exit(void) -+{ -+ platform_driver_unregister(&omap_hwspinlock_driver); -+} -+module_exit(omap_hwspinlock_exit); -+ -+MODULE_LICENSE("GPL v2"); -+MODULE_DESCRIPTION("Hardware spinlock driver for OMAP"); -+MODULE_AUTHOR("Simon Que "); -+MODULE_AUTHOR("Hari Kanigeri "); -+MODULE_AUTHOR("Ohad Ben-Cohen "); -diff -Naur linux-2.6.38-rc7/drivers/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/Kconfig ---- linux-2.6.38-rc7/drivers/Kconfig 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/Kconfig 2011-03-09 13:19:12.865445652 +0100 -@@ -117,4 +117,6 @@ - source "drivers/platform/Kconfig" - - source "drivers/clk/Kconfig" -+ -+source "drivers/hwspinlock/Kconfig" - endmenu -diff -Naur linux-2.6.38-rc7/drivers/Makefile linux-2.6.38-rc7-linux-omap-dss2/drivers/Makefile ---- linux-2.6.38-rc7/drivers/Makefile 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/Makefile 2011-03-09 13:19:12.865445652 +0100 -@@ -117,3 +117,5 @@ - obj-y += ieee802154/ - #common clk code - obj-y += clk/ -+ -+obj-$(CONFIG_HWSPINLOCK) += hwspinlock/ -diff -Naur linux-2.6.38-rc7/drivers/mmc/host/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/mmc/host/Kconfig ---- linux-2.6.38-rc7/drivers/mmc/host/Kconfig 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/mmc/host/Kconfig 2011-03-09 13:19:15.003402284 +0100 -@@ -225,7 +225,7 @@ - - config MMC_OMAP_HS - tristate "TI OMAP High Speed Multimedia Card Interface support" -- depends on ARCH_OMAP2430 || ARCH_OMAP3 || ARCH_OMAP4 -+ depends on SOC_OMAP2430 || ARCH_OMAP3 || ARCH_OMAP4 - help - This selects the TI OMAP High Speed Multimedia card Interface. - If you have an OMAP2430 or OMAP3 board or OMAP4 board with a -diff -Naur linux-2.6.38-rc7/drivers/mmc/host/omap_hsmmc.c linux-2.6.38-rc7-linux-omap-dss2/drivers/mmc/host/omap_hsmmc.c ---- linux-2.6.38-rc7/drivers/mmc/host/omap_hsmmc.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/mmc/host/omap_hsmmc.c 2011-03-09 13:19:15.011402121 +0100 -@@ -118,7 +118,7 @@ - - #define MMC_TIMEOUT_MS 20 - #define OMAP_MMC_MASTER_CLOCK 96000000 --#define DRIVER_NAME "mmci-omap-hs" -+#define DRIVER_NAME "omap_hsmmc" - - /* Timeouts for entering power saving states on inactivity, msec */ - #define OMAP_MMC_DISABLED_TIMEOUT 100 -@@ -260,7 +260,7 @@ - return ret; - } - --static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on, -+static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on, - int vdd) - { - struct omap_hsmmc_host *host = -@@ -316,6 +316,12 @@ - return ret; - } - -+static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on, -+ int vdd) -+{ -+ return 0; -+} -+ - static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, - int vdd, int cardsleep) - { -@@ -326,7 +332,7 @@ - return regulator_set_mode(host->vcc, mode); - } - --static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep, -+static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep, - int vdd, int cardsleep) - { - struct omap_hsmmc_host *host = -@@ -365,6 +371,12 @@ - return regulator_enable(host->vcc_aux); - } - -+static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep, -+ int vdd, int cardsleep) -+{ -+ return 0; -+} -+ - static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) - { - struct regulator *reg; -@@ -379,10 +391,14 @@ - break; - case OMAP_MMC2_DEVID: - case OMAP_MMC3_DEVID: -+ case OMAP_MMC5_DEVID: - /* Off-chip level shifting, or none */ -- mmc_slot(host).set_power = omap_hsmmc_23_set_power; -- mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep; -+ mmc_slot(host).set_power = omap_hsmmc_235_set_power; -+ mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep; - break; -+ case OMAP_MMC4_DEVID: -+ mmc_slot(host).set_power = omap_hsmmc_4_set_power; -+ mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep; - default: - pr_err("MMC%d configuration not supported!\n", host->id); - return -EINVAL; -@@ -1555,7 +1571,7 @@ - break; - } - -- if (host->id == OMAP_MMC1_DEVID) { -+ if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { - /* Only MMC1 can interface at 3V without some flavor - * of external transceiver; but they all handle 1.8V. - */ -@@ -1647,7 +1663,7 @@ - u32 hctl, capa, value; - - /* Only MMC1 supports 3.0V */ -- if (host->id == OMAP_MMC1_DEVID) { -+ if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { - hctl = SDVS30; - capa = VS30 | VS18; - } else { -diff -Naur linux-2.6.38-rc7/drivers/mtd/nand/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/mtd/nand/Kconfig ---- linux-2.6.38-rc7/drivers/mtd/nand/Kconfig 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/mtd/nand/Kconfig 2011-03-09 13:19:15.269396887 +0100 -@@ -106,23 +106,6 @@ - help - Support for NAND flash on Texas Instruments OMAP2 and OMAP3 platforms. - --config MTD_NAND_OMAP_PREFETCH -- bool "GPMC prefetch support for NAND Flash device" -- depends on MTD_NAND_OMAP2 -- default y -- help -- The NAND device can be accessed for Read/Write using GPMC PREFETCH engine -- to improve the performance. -- --config MTD_NAND_OMAP_PREFETCH_DMA -- depends on MTD_NAND_OMAP_PREFETCH -- bool "DMA mode" -- default n -- help -- The GPMC PREFETCH engine can be configured eigther in MPU interrupt mode -- or in DMA interrupt mode. -- Say y for DMA mode or MPU mode will be used -- - config MTD_NAND_IDS - tristate - -diff -Naur linux-2.6.38-rc7/drivers/mtd/nand/omap2.c linux-2.6.38-rc7-linux-omap-dss2/drivers/mtd/nand/omap2.c ---- linux-2.6.38-rc7/drivers/mtd/nand/omap2.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/mtd/nand/omap2.c 2011-03-09 13:19:15.281396643 +0100 -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -24,6 +25,7 @@ - #include - - #define DRIVER_NAME "omap2-nand" -+#define OMAP_NAND_TIMEOUT_MS 5000 - - #define NAND_Ecc_P1e (1 << 0) - #define NAND_Ecc_P2e (1 << 1) -@@ -96,26 +98,19 @@ - static const char *part_probes[] = { "cmdlinepart", NULL }; - #endif - --#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH --static int use_prefetch = 1; -+/* oob info generated runtime depending on ecc algorithm and layout selected */ -+static struct nand_ecclayout omap_oobinfo; -+/* Define some generic bad / good block scan pattern which are used -+ * while scanning a device for factory marked good / bad blocks -+ */ -+static uint8_t scan_ff_pattern[] = { 0xff }; -+static struct nand_bbt_descr bb_descrip_flashbased = { -+ .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES, -+ .offs = 0, -+ .len = 1, -+ .pattern = scan_ff_pattern, -+}; - --/* "modprobe ... use_prefetch=0" etc */ --module_param(use_prefetch, bool, 0); --MODULE_PARM_DESC(use_prefetch, "enable/disable use of PREFETCH"); -- --#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA --static int use_dma = 1; -- --/* "modprobe ... use_dma=0" etc */ --module_param(use_dma, bool, 0); --MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); --#else --static const int use_dma; --#endif --#else --const int use_prefetch; --static const int use_dma; --#endif - - struct omap_nand_info { - struct nand_hw_control controller; -@@ -129,6 +124,13 @@ - unsigned long phys_base; - struct completion comp; - int dma_ch; -+ int gpmc_irq; -+ enum { -+ OMAP_NAND_IO_READ = 0, /* read */ -+ OMAP_NAND_IO_WRITE, /* write */ -+ } iomode; -+ u_char *buf; -+ int buf_len; - }; - - /** -@@ -256,7 +258,8 @@ - } - - /* configure and start prefetch transfer */ -- ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x0); -+ ret = gpmc_prefetch_enable(info->gpmc_cs, -+ PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0); - if (ret) { - /* PFPW engine is busy, use cpu copy method */ - if (info->nand.options & NAND_BUSWIDTH_16) -@@ -288,9 +291,10 @@ - { - struct omap_nand_info *info = container_of(mtd, - struct omap_nand_info, mtd); -- uint32_t pref_count = 0, w_count = 0; -+ uint32_t w_count = 0; - int i = 0, ret = 0; - u16 *p; -+ unsigned long tim, limit; - - /* take care of subpage writes */ - if (len % 2 != 0) { -@@ -300,7 +304,8 @@ - } - - /* configure and start prefetch transfer */ -- ret = gpmc_prefetch_enable(info->gpmc_cs, 0x0, len, 0x1); -+ ret = gpmc_prefetch_enable(info->gpmc_cs, -+ PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1); - if (ret) { - /* PFPW engine is busy, use cpu copy method */ - if (info->nand.options & NAND_BUSWIDTH_16) -@@ -316,15 +321,17 @@ - iowrite16(*p++, info->nand.IO_ADDR_W); - } - /* wait for data to flushed-out before reset the prefetch */ -- do { -- pref_count = gpmc_read_status(GPMC_PREFETCH_COUNT); -- } while (pref_count); -+ tim = 0; -+ limit = (loops_per_jiffy * -+ msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); -+ while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) -+ cpu_relax(); -+ - /* disable and stop the PFPW engine */ - gpmc_prefetch_reset(info->gpmc_cs); - } - } - --#ifdef CONFIG_MTD_NAND_OMAP_PREFETCH_DMA - /* - * omap_nand_dma_cb: callback on the completion of dma transfer - * @lch: logical channel -@@ -348,14 +355,15 @@ - { - struct omap_nand_info *info = container_of(mtd, - struct omap_nand_info, mtd); -- uint32_t prefetch_status = 0; - enum dma_data_direction dir = is_write ? DMA_TO_DEVICE : - DMA_FROM_DEVICE; - dma_addr_t dma_addr; - int ret; -+ unsigned long tim, limit; - -- /* The fifo depth is 64 bytes. We have a sync at each frame and frame -- * length is 64 bytes. -+ /* The fifo depth is 64 bytes max. -+ * But configure the FIFO-threahold to 32 to get a sync at each frame -+ * and frame length is 32 bytes. - */ - int buf_len = len >> 6; - -@@ -396,9 +404,10 @@ - OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC); - } - /* configure and start prefetch transfer */ -- ret = gpmc_prefetch_enable(info->gpmc_cs, 0x1, len, is_write); -+ ret = gpmc_prefetch_enable(info->gpmc_cs, -+ PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write); - if (ret) -- /* PFPW engine is busy, use cpu copy methode */ -+ /* PFPW engine is busy, use cpu copy method */ - goto out_copy; - - init_completion(&info->comp); -@@ -407,10 +416,11 @@ - - /* setup and start DMA using dma_addr */ - wait_for_completion(&info->comp); -+ tim = 0; -+ limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); -+ while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) -+ cpu_relax(); - -- do { -- prefetch_status = gpmc_read_status(GPMC_PREFETCH_COUNT); -- } while (prefetch_status); - /* disable and stop the PFPW engine */ - gpmc_prefetch_reset(info->gpmc_cs); - -@@ -426,14 +436,6 @@ - : omap_write_buf8(mtd, (u_char *) addr, len); - return 0; - } --#else --static void omap_nand_dma_cb(int lch, u16 ch_status, void *data) {} --static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr, -- unsigned int len, int is_write) --{ -- return 0; --} --#endif - - /** - * omap_read_buf_dma_pref - read data from NAND controller into buffer -@@ -466,6 +468,157 @@ - omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1); - } - -+/* -+ * omap_nand_irq - GMPC irq handler -+ * @this_irq: gpmc irq number -+ * @dev: omap_nand_info structure pointer is passed here -+ */ -+static irqreturn_t omap_nand_irq(int this_irq, void *dev) -+{ -+ struct omap_nand_info *info = (struct omap_nand_info *) dev; -+ u32 bytes; -+ u32 irq_stat; -+ -+ irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS); -+ bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT); -+ bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ -+ if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ -+ if (irq_stat & 0x2) -+ goto done; -+ -+ if (info->buf_len && (info->buf_len < bytes)) -+ bytes = info->buf_len; -+ else if (!info->buf_len) -+ bytes = 0; -+ iowrite32_rep(info->nand.IO_ADDR_W, -+ (u32 *)info->buf, bytes >> 2); -+ info->buf = info->buf + bytes; -+ info->buf_len -= bytes; -+ -+ } else { -+ ioread32_rep(info->nand.IO_ADDR_R, -+ (u32 *)info->buf, bytes >> 2); -+ info->buf = info->buf + bytes; -+ -+ if (irq_stat & 0x2) -+ goto done; -+ } -+ gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); -+ -+ return IRQ_HANDLED; -+ -+done: -+ complete(&info->comp); -+ /* disable irq */ -+ gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0); -+ -+ /* clear status */ -+ gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); -+ -+ return IRQ_HANDLED; -+} -+ -+/* -+ * omap_read_buf_irq_pref - read data from NAND controller into buffer -+ * @mtd: MTD device structure -+ * @buf: buffer to store date -+ * @len: number of bytes to read -+ */ -+static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len) -+{ -+ struct omap_nand_info *info = container_of(mtd, -+ struct omap_nand_info, mtd); -+ int ret = 0; -+ -+ if (len <= mtd->oobsize) { -+ omap_read_buf_pref(mtd, buf, len); -+ return; -+ } -+ -+ info->iomode = OMAP_NAND_IO_READ; -+ info->buf = buf; -+ init_completion(&info->comp); -+ -+ /* configure and start prefetch transfer */ -+ ret = gpmc_prefetch_enable(info->gpmc_cs, -+ PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0); -+ if (ret) -+ /* PFPW engine is busy, use cpu copy method */ -+ goto out_copy; -+ -+ info->buf_len = len; -+ /* enable irq */ -+ gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, -+ (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); -+ -+ /* waiting for read to complete */ -+ wait_for_completion(&info->comp); -+ -+ /* disable and stop the PFPW engine */ -+ gpmc_prefetch_reset(info->gpmc_cs); -+ return; -+ -+out_copy: -+ if (info->nand.options & NAND_BUSWIDTH_16) -+ omap_read_buf16(mtd, buf, len); -+ else -+ omap_read_buf8(mtd, buf, len); -+} -+ -+/* -+ * omap_write_buf_irq_pref - write buffer to NAND controller -+ * @mtd: MTD device structure -+ * @buf: data buffer -+ * @len: number of bytes to write -+ */ -+static void omap_write_buf_irq_pref(struct mtd_info *mtd, -+ const u_char *buf, int len) -+{ -+ struct omap_nand_info *info = container_of(mtd, -+ struct omap_nand_info, mtd); -+ int ret = 0; -+ unsigned long tim, limit; -+ -+ if (len <= mtd->oobsize) { -+ omap_write_buf_pref(mtd, buf, len); -+ return; -+ } -+ -+ info->iomode = OMAP_NAND_IO_WRITE; -+ info->buf = (u_char *) buf; -+ init_completion(&info->comp); -+ -+ /* configure and start prefetch transfer : size=24 */ -+ ret = gpmc_prefetch_enable(info->gpmc_cs, -+ (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1); -+ if (ret) -+ /* PFPW engine is busy, use cpu copy method */ -+ goto out_copy; -+ -+ info->buf_len = len; -+ /* enable irq */ -+ gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, -+ (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); -+ -+ /* waiting for write to complete */ -+ wait_for_completion(&info->comp); -+ /* wait for data to flushed-out before reset the prefetch */ -+ tim = 0; -+ limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); -+ while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) -+ cpu_relax(); -+ -+ /* disable and stop the PFPW engine */ -+ gpmc_prefetch_reset(info->gpmc_cs); -+ return; -+ -+out_copy: -+ if (info->nand.options & NAND_BUSWIDTH_16) -+ omap_write_buf16(mtd, buf, len); -+ else -+ omap_write_buf8(mtd, buf, len); -+} -+ - /** - * omap_verify_buf - Verify chip data against buffer - * @mtd: MTD device structure -@@ -487,8 +640,6 @@ - return 0; - } - --#ifdef CONFIG_MTD_NAND_OMAP_HWECC -- - /** - * gen_true_ecc - This function will generate true ECC value - * @ecc_buf: buffer to store ecc code -@@ -708,8 +859,6 @@ - gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size); - } - --#endif -- - /** - * omap_wait - wait until the command is done - * @mtd: MTD device structure -@@ -779,6 +928,7 @@ - struct omap_nand_info *info; - struct omap_nand_platform_data *pdata; - int err; -+ int i, offset; - - pdata = pdev->dev.platform_data; - if (pdata == NULL) { -@@ -804,7 +954,7 @@ - info->mtd.name = dev_name(&pdev->dev); - info->mtd.owner = THIS_MODULE; - -- info->nand.options |= pdata->devsize ? NAND_BUSWIDTH_16 : 0; -+ info->nand.options = pdata->devsize; - info->nand.options |= NAND_SKIP_BBTSCAN; - - /* NAND write protect off */ -@@ -842,28 +992,13 @@ - info->nand.chip_delay = 50; - } - -- if (use_prefetch) { -- -+ switch (pdata->xfer_type) { -+ case NAND_OMAP_PREFETCH_POLLED: - info->nand.read_buf = omap_read_buf_pref; - info->nand.write_buf = omap_write_buf_pref; -- if (use_dma) { -- err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND", -- omap_nand_dma_cb, &info->comp, &info->dma_ch); -- if (err < 0) { -- info->dma_ch = -1; -- printk(KERN_WARNING "DMA request failed." -- " Non-dma data transfer mode\n"); -- } else { -- omap_set_dma_dest_burst_mode(info->dma_ch, -- OMAP_DMA_DATA_BURST_16); -- omap_set_dma_src_burst_mode(info->dma_ch, -- OMAP_DMA_DATA_BURST_16); -- -- info->nand.read_buf = omap_read_buf_dma_pref; -- info->nand.write_buf = omap_write_buf_dma_pref; -- } -- } -- } else { -+ break; -+ -+ case NAND_OMAP_POLLED: - if (info->nand.options & NAND_BUSWIDTH_16) { - info->nand.read_buf = omap_read_buf16; - info->nand.write_buf = omap_write_buf16; -@@ -871,20 +1006,61 @@ - info->nand.read_buf = omap_read_buf8; - info->nand.write_buf = omap_write_buf8; - } -+ break; -+ -+ case NAND_OMAP_PREFETCH_DMA: -+ err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND", -+ omap_nand_dma_cb, &info->comp, &info->dma_ch); -+ if (err < 0) { -+ info->dma_ch = -1; -+ dev_err(&pdev->dev, "DMA request failed!\n"); -+ goto out_release_mem_region; -+ } else { -+ omap_set_dma_dest_burst_mode(info->dma_ch, -+ OMAP_DMA_DATA_BURST_16); -+ omap_set_dma_src_burst_mode(info->dma_ch, -+ OMAP_DMA_DATA_BURST_16); -+ -+ info->nand.read_buf = omap_read_buf_dma_pref; -+ info->nand.write_buf = omap_write_buf_dma_pref; -+ } -+ break; -+ -+ case NAND_OMAP_PREFETCH_IRQ: -+ err = request_irq(pdata->gpmc_irq, -+ omap_nand_irq, IRQF_SHARED, "gpmc-nand", info); -+ if (err) { -+ dev_err(&pdev->dev, "requesting irq(%d) error:%d", -+ pdata->gpmc_irq, err); -+ goto out_release_mem_region; -+ } else { -+ info->gpmc_irq = pdata->gpmc_irq; -+ info->nand.read_buf = omap_read_buf_irq_pref; -+ info->nand.write_buf = omap_write_buf_irq_pref; -+ } -+ break; -+ -+ default: -+ dev_err(&pdev->dev, -+ "xfer_type(%d) not supported!\n", pdata->xfer_type); -+ err = -EINVAL; -+ goto out_release_mem_region; - } -- info->nand.verify_buf = omap_verify_buf; - --#ifdef CONFIG_MTD_NAND_OMAP_HWECC -- info->nand.ecc.bytes = 3; -- info->nand.ecc.size = 512; -- info->nand.ecc.calculate = omap_calculate_ecc; -- info->nand.ecc.hwctl = omap_enable_hwecc; -- info->nand.ecc.correct = omap_correct_data; -- info->nand.ecc.mode = NAND_ECC_HW; -+ info->nand.verify_buf = omap_verify_buf; - --#else -- info->nand.ecc.mode = NAND_ECC_SOFT; --#endif -+ /* selsect the ecc type */ -+ if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT) -+ info->nand.ecc.mode = NAND_ECC_SOFT; -+ else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) || -+ (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) { -+ info->nand.ecc.bytes = 3; -+ info->nand.ecc.size = 512; -+ info->nand.ecc.calculate = omap_calculate_ecc; -+ info->nand.ecc.hwctl = omap_enable_hwecc; -+ info->nand.ecc.correct = omap_correct_data; -+ info->nand.ecc.mode = NAND_ECC_HW; -+ } - - /* DIP switches on some boards change between 8 and 16 bit - * bus widths for flash. Try the other width if the first try fails. -@@ -897,6 +1073,26 @@ - } - } - -+ /* rom code layout */ -+ if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) { -+ -+ if (info->nand.options & NAND_BUSWIDTH_16) -+ offset = 2; -+ else { -+ offset = 1; -+ info->nand.badblock_pattern = &bb_descrip_flashbased; -+ } -+ omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16); -+ for (i = 0; i < omap_oobinfo.eccbytes; i++) -+ omap_oobinfo.eccpos[i] = i+offset; -+ -+ omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes; -+ omap_oobinfo.oobfree->length = info->mtd.oobsize - -+ (offset + omap_oobinfo.eccbytes); -+ -+ info->nand.ecc.layout = &omap_oobinfo; -+ } -+ - #ifdef CONFIG_MTD_PARTITIONS - err = parse_mtd_partitions(&info->mtd, part_probes, &info->parts, 0); - if (err > 0) -@@ -926,9 +1122,12 @@ - mtd); - - platform_set_drvdata(pdev, NULL); -- if (use_dma) -+ if (info->dma_ch != -1) - omap_free_dma(info->dma_ch); - -+ if (info->gpmc_irq) -+ free_irq(info->gpmc_irq, info); -+ - /* Release NAND device, its internal structures and partitions */ - nand_release(&info->mtd); - iounmap(info->nand.IO_ADDR_R); -@@ -947,16 +1146,8 @@ - - static int __init omap_nand_init(void) - { -- printk(KERN_INFO "%s driver initializing\n", DRIVER_NAME); -+ pr_info("%s driver initializing\n", DRIVER_NAME); - -- /* This check is required if driver is being -- * loaded run time as a module -- */ -- if ((1 == use_dma) && (0 == use_prefetch)) { -- printk(KERN_INFO"Wrong parameters: 'use_dma' can not be 1 " -- "without use_prefetch'. Prefetch will not be" -- " used in either mode (mpu or dma)\n"); -- } - return platform_driver_register(&omap_nand_driver); - } - -diff -Naur linux-2.6.38-rc7/drivers/mtd/onenand/omap2.c linux-2.6.38-rc7-linux-omap-dss2/drivers/mtd/onenand/omap2.c ---- linux-2.6.38-rc7/drivers/mtd/onenand/omap2.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/mtd/onenand/omap2.c 2011-03-09 13:19:15.286396542 +0100 -@@ -63,7 +63,7 @@ - struct completion dma_done; - int dma_channel; - int freq; -- int (*setup)(void __iomem *base, int freq); -+ int (*setup)(void __iomem *base, int *freq_ptr); - struct regulator *regulator; - }; - -@@ -148,11 +148,9 @@ - wait_err("controller error", state, ctrl, intr); - return -EIO; - } -- if ((intr & intr_flags) != intr_flags) { -- wait_err("timeout", state, ctrl, intr); -- return -EIO; -- } -- return 0; -+ if ((intr & intr_flags) == intr_flags) -+ return 0; -+ /* Continue in wait for interrupt branch */ - } - - if (state != FL_READING) { -@@ -581,7 +579,7 @@ - - /* DMA is not in use so this is all that is needed */ - /* Revisit for OMAP3! */ -- ret = c->setup(c->onenand.base, c->freq); -+ ret = c->setup(c->onenand.base, &c->freq); - - return ret; - } -@@ -673,7 +671,7 @@ - } - - if (pdata->onenand_setup != NULL) { -- r = pdata->onenand_setup(c->onenand.base, c->freq); -+ r = pdata->onenand_setup(c->onenand.base, &c->freq); - if (r < 0) { - dev_err(&pdev->dev, "Onenand platform setup failed: " - "%d\n", r); -@@ -718,8 +716,8 @@ - } - - dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual " -- "base %p\n", c->gpmc_cs, c->phys_base, -- c->onenand.base); -+ "base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base, -+ c->onenand.base, c->freq); - - c->pdev = pdev; - c->mtd.name = dev_name(&pdev->dev); -@@ -754,24 +752,6 @@ - if ((r = onenand_scan(&c->mtd, 1)) < 0) - goto err_release_regulator; - -- switch ((c->onenand.version_id >> 4) & 0xf) { -- case 0: -- c->freq = 40; -- break; -- case 1: -- c->freq = 54; -- break; -- case 2: -- c->freq = 66; -- break; -- case 3: -- c->freq = 83; -- break; -- case 4: -- c->freq = 104; -- break; -- } -- - #ifdef CONFIG_MTD_PARTITIONS - r = parse_mtd_partitions(&c->mtd, part_probes, &c->parts, 0); - if (r > 0) -diff -Naur linux-2.6.38-rc7/drivers/spi/omap2_mcspi.c linux-2.6.38-rc7-linux-omap-dss2/drivers/spi/omap2_mcspi.c ---- linux-2.6.38-rc7/drivers/spi/omap2_mcspi.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/spi/omap2_mcspi.c 2011-03-09 13:19:17.550350615 +0100 -@@ -3,7 +3,7 @@ - * - * Copyright (C) 2005, 2006 Nokia Corporation - * Author: Samuel Ortiz and -- * Juha Yrjölä -+ * Juha Yrj�l� - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by -@@ -33,6 +33,7 @@ - #include - #include - #include -+#include - - #include - -@@ -46,7 +47,6 @@ - #define OMAP2_MCSPI_MAX_CTRL 4 - - #define OMAP2_MCSPI_REVISION 0x00 --#define OMAP2_MCSPI_SYSCONFIG 0x10 - #define OMAP2_MCSPI_SYSSTATUS 0x14 - #define OMAP2_MCSPI_IRQSTATUS 0x18 - #define OMAP2_MCSPI_IRQENABLE 0x1c -@@ -63,13 +63,6 @@ - - /* per-register bitmasks: */ - --#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4) --#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2) --#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0) --#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1) -- --#define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0) -- - #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0) - #define OMAP2_MCSPI_MODULCTRL_MS BIT(2) - #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3) -@@ -122,13 +115,12 @@ - spinlock_t lock; - struct list_head msg_queue; - struct spi_master *master; -- struct clk *ick; -- struct clk *fck; - /* Virtual base address of the controller */ - void __iomem *base; - unsigned long phys; - /* SPI1 has 4 channels, while SPI2 has 2 */ - struct omap2_mcspi_dma *dma_channels; -+ struct device *dev; - }; - - struct omap2_mcspi_cs { -@@ -144,7 +136,6 @@ - * corresponding registers are modified. - */ - struct omap2_mcspi_regs { -- u32 sysconfig; - u32 modulctrl; - u32 wakeupenable; - struct list_head cs; -@@ -268,9 +259,6 @@ - mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, - omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl); - -- mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG, -- omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig); -- - mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, - omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable); - -@@ -280,20 +268,12 @@ - } - static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi) - { -- clk_disable(mcspi->ick); -- clk_disable(mcspi->fck); -+ pm_runtime_put_sync(mcspi->dev); - } - - static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi) - { -- if (clk_enable(mcspi->ick)) -- return -ENODEV; -- if (clk_enable(mcspi->fck)) -- return -ENODEV; -- -- omap2_mcspi_restore_ctx(mcspi); -- -- return 0; -+ return pm_runtime_get_sync(mcspi->dev); - } - - static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit) -@@ -819,8 +799,9 @@ - return ret; - } - -- if (omap2_mcspi_enable_clocks(mcspi)) -- return -ENODEV; -+ ret = omap2_mcspi_enable_clocks(mcspi); -+ if (ret < 0) -+ return ret; - - ret = omap2_mcspi_setup_transfer(spi, NULL); - omap2_mcspi_disable_clocks(mcspi); -@@ -863,10 +844,11 @@ - struct omap2_mcspi *mcspi; - - mcspi = container_of(work, struct omap2_mcspi, work); -- spin_lock_irq(&mcspi->lock); - -- if (omap2_mcspi_enable_clocks(mcspi)) -- goto out; -+ if (omap2_mcspi_enable_clocks(mcspi) < 0) -+ return; -+ -+ spin_lock_irq(&mcspi->lock); - - /* We only enable one channel at a time -- the one whose message is - * at the head of the queue -- although this controller would gladly -@@ -979,10 +961,9 @@ - spin_lock_irq(&mcspi->lock); - } - -- omap2_mcspi_disable_clocks(mcspi); -- --out: - spin_unlock_irq(&mcspi->lock); -+ -+ omap2_mcspi_disable_clocks(mcspi); - } - - static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m) -@@ -1058,25 +1039,15 @@ - return 0; - } - --static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi) -+static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) - { - struct spi_master *master = mcspi->master; - u32 tmp; -+ int ret = 0; - -- if (omap2_mcspi_enable_clocks(mcspi)) -- return -1; -- -- mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, -- OMAP2_MCSPI_SYSCONFIG_SOFTRESET); -- do { -- tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS); -- } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE)); -- -- tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE | -- OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP | -- OMAP2_MCSPI_SYSCONFIG_SMARTIDLE; -- mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp); -- omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp; -+ ret = omap2_mcspi_enable_clocks(mcspi); -+ if (ret < 0) -+ return ret; - - tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN; - mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp); -@@ -1087,91 +1058,26 @@ - return 0; - } - --static u8 __initdata spi1_rxdma_id [] = { -- OMAP24XX_DMA_SPI1_RX0, -- OMAP24XX_DMA_SPI1_RX1, -- OMAP24XX_DMA_SPI1_RX2, -- OMAP24XX_DMA_SPI1_RX3, --}; -- --static u8 __initdata spi1_txdma_id [] = { -- OMAP24XX_DMA_SPI1_TX0, -- OMAP24XX_DMA_SPI1_TX1, -- OMAP24XX_DMA_SPI1_TX2, -- OMAP24XX_DMA_SPI1_TX3, --}; -- --static u8 __initdata spi2_rxdma_id[] = { -- OMAP24XX_DMA_SPI2_RX0, -- OMAP24XX_DMA_SPI2_RX1, --}; -- --static u8 __initdata spi2_txdma_id[] = { -- OMAP24XX_DMA_SPI2_TX0, -- OMAP24XX_DMA_SPI2_TX1, --}; -- --#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \ -- || defined(CONFIG_ARCH_OMAP4) --static u8 __initdata spi3_rxdma_id[] = { -- OMAP24XX_DMA_SPI3_RX0, -- OMAP24XX_DMA_SPI3_RX1, --}; -+static int omap_mcspi_runtime_resume(struct device *dev) -+{ -+ struct omap2_mcspi *mcspi; -+ struct spi_master *master; - --static u8 __initdata spi3_txdma_id[] = { -- OMAP24XX_DMA_SPI3_TX0, -- OMAP24XX_DMA_SPI3_TX1, --}; --#endif -+ master = dev_get_drvdata(dev); -+ mcspi = spi_master_get_devdata(master); -+ omap2_mcspi_restore_ctx(mcspi); - --#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) --static u8 __initdata spi4_rxdma_id[] = { -- OMAP34XX_DMA_SPI4_RX0, --}; -+ return 0; -+} - --static u8 __initdata spi4_txdma_id[] = { -- OMAP34XX_DMA_SPI4_TX0, --}; --#endif - - static int __init omap2_mcspi_probe(struct platform_device *pdev) - { - struct spi_master *master; -+ struct omap2_mcspi_platform_config *pdata = pdev->dev.platform_data; - struct omap2_mcspi *mcspi; - struct resource *r; - int status = 0, i; -- const u8 *rxdma_id, *txdma_id; -- unsigned num_chipselect; -- -- switch (pdev->id) { -- case 1: -- rxdma_id = spi1_rxdma_id; -- txdma_id = spi1_txdma_id; -- num_chipselect = 4; -- break; -- case 2: -- rxdma_id = spi2_rxdma_id; -- txdma_id = spi2_txdma_id; -- num_chipselect = 2; -- break; --#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \ -- || defined(CONFIG_ARCH_OMAP4) -- case 3: -- rxdma_id = spi3_rxdma_id; -- txdma_id = spi3_txdma_id; -- num_chipselect = 2; -- break; --#endif --#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) -- case 4: -- rxdma_id = spi4_rxdma_id; -- txdma_id = spi4_txdma_id; -- num_chipselect = 1; -- break; --#endif -- default: -- return -EINVAL; -- } - - master = spi_alloc_master(&pdev->dev, sizeof *mcspi); - if (master == NULL) { -@@ -1188,7 +1094,7 @@ - master->setup = omap2_mcspi_setup; - master->transfer = omap2_mcspi_transfer; - master->cleanup = omap2_mcspi_cleanup; -- master->num_chipselect = num_chipselect; -+ master->num_chipselect = pdata->num_cs; - - dev_set_drvdata(&pdev->dev, master); - -@@ -1206,49 +1112,62 @@ - goto err1; - } - -+ r->start += pdata->regs_offset; -+ r->end += pdata->regs_offset; - mcspi->phys = r->start; - mcspi->base = ioremap(r->start, r->end - r->start + 1); - if (!mcspi->base) { - dev_dbg(&pdev->dev, "can't ioremap MCSPI\n"); - status = -ENOMEM; -- goto err1aa; -+ goto err2; - } - -+ mcspi->dev = &pdev->dev; - INIT_WORK(&mcspi->work, omap2_mcspi_work); - - spin_lock_init(&mcspi->lock); - INIT_LIST_HEAD(&mcspi->msg_queue); - INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs); - -- mcspi->ick = clk_get(&pdev->dev, "ick"); -- if (IS_ERR(mcspi->ick)) { -- dev_dbg(&pdev->dev, "can't get mcspi_ick\n"); -- status = PTR_ERR(mcspi->ick); -- goto err1a; -- } -- mcspi->fck = clk_get(&pdev->dev, "fck"); -- if (IS_ERR(mcspi->fck)) { -- dev_dbg(&pdev->dev, "can't get mcspi_fck\n"); -- status = PTR_ERR(mcspi->fck); -- goto err2; -- } -- - mcspi->dma_channels = kcalloc(master->num_chipselect, - sizeof(struct omap2_mcspi_dma), - GFP_KERNEL); - - if (mcspi->dma_channels == NULL) -- goto err3; -+ goto err2; -+ -+ for (i = 0; i < master->num_chipselect; i++) { -+ char dma_ch_name[14]; -+ struct resource *dma_res; -+ -+ sprintf(dma_ch_name, "rx%d", i); -+ dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, -+ dma_ch_name); -+ if (!dma_res) { -+ dev_dbg(&pdev->dev, "cannot get DMA RX channel\n"); -+ status = -ENODEV; -+ break; -+ } - -- for (i = 0; i < num_chipselect; i++) { - mcspi->dma_channels[i].dma_rx_channel = -1; -- mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i]; -+ mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start; -+ sprintf(dma_ch_name, "tx%d", i); -+ dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA, -+ dma_ch_name); -+ if (!dma_res) { -+ dev_dbg(&pdev->dev, "cannot get DMA TX channel\n"); -+ status = -ENODEV; -+ break; -+ } -+ - mcspi->dma_channels[i].dma_tx_channel = -1; -- mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i]; -+ mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start; - } - -- if (omap2_mcspi_reset(mcspi) < 0) -- goto err4; -+ pm_runtime_enable(&pdev->dev); -+ -+ if (status || omap2_mcspi_master_setup(mcspi) < 0) -+ goto err3; - - status = spi_register_master(master); - if (status < 0) -@@ -1257,17 +1176,13 @@ - return status; - - err4: -- kfree(mcspi->dma_channels); -+ spi_master_put(master); - err3: -- clk_put(mcspi->fck); -+ kfree(mcspi->dma_channels); - err2: -- clk_put(mcspi->ick); --err1a: -- iounmap(mcspi->base); --err1aa: - release_mem_region(r->start, (r->end - r->start) + 1); -+ iounmap(mcspi->base); - err1: -- spi_master_put(master); - return status; - } - -@@ -1283,9 +1198,7 @@ - mcspi = spi_master_get_devdata(master); - dma_channels = mcspi->dma_channels; - -- clk_put(mcspi->fck); -- clk_put(mcspi->ick); -- -+ omap2_mcspi_disable_clocks(mcspi); - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - release_mem_region(r->start, (r->end - r->start) + 1); - -@@ -1336,6 +1249,7 @@ - - static const struct dev_pm_ops omap2_mcspi_pm_ops = { - .resume = omap2_mcspi_resume, -+ .runtime_resume = omap_mcspi_runtime_resume, - }; - - static struct platform_driver omap2_mcspi_driver = { -diff -Naur linux-2.6.38-rc7/drivers/usb/musb/musb_core.c linux-2.6.38-rc7-linux-omap-dss2/drivers/usb/musb/musb_core.c ---- linux-2.6.38-rc7/drivers/usb/musb/musb_core.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/usb/musb/musb_core.c 2011-03-09 13:19:19.480311463 +0100 -@@ -1530,7 +1530,7 @@ - - /*-------------------------------------------------------------------------*/ - --#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) || \ -+#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \ - defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) || \ - defined(CONFIG_ARCH_U5500) - -diff -Naur linux-2.6.38-rc7/drivers/usb/musb/musb_core.h linux-2.6.38-rc7-linux-omap-dss2/drivers/usb/musb/musb_core.h ---- linux-2.6.38-rc7/drivers/usb/musb/musb_core.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/usb/musb/musb_core.h 2011-03-09 13:19:19.480311463 +0100 -@@ -212,8 +212,8 @@ - * directly with the "flat" model, or after setting up an index register. - */ - --#if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_ARCH_OMAP2430) \ -- || defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_BLACKFIN) \ -+#if defined(CONFIG_ARCH_DAVINCI) || defined(CONFIG_SOC_OMAP2430) \ -+ || defined(CONFIG_SOC_OMAP3430) || defined(CONFIG_BLACKFIN) \ - || defined(CONFIG_ARCH_OMAP4) - /* REVISIT indexed access seemed to - * misbehave (on DaVinci) for at least peripheral IN ... -@@ -358,7 +358,7 @@ - - struct musb_context_registers { - --#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ -+#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \ - defined(CONFIG_ARCH_OMAP4) - u32 otg_sysconfig, otg_forcestandby; - #endif -diff -Naur linux-2.6.38-rc7/drivers/usb/musb/musbhsdma.h linux-2.6.38-rc7-linux-omap-dss2/drivers/usb/musb/musbhsdma.h ---- linux-2.6.38-rc7/drivers/usb/musb/musbhsdma.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/usb/musb/musbhsdma.h 2011-03-09 13:19:19.484311381 +0100 -@@ -31,7 +31,7 @@ - * - */ - --#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430) -+#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) - #include "omap2430.h" - #endif - -diff -Naur linux-2.6.38-rc7/drivers/usb/otg/isp1301_omap.c linux-2.6.38-rc7-linux-omap-dss2/drivers/usb/otg/isp1301_omap.c ---- linux-2.6.38-rc7/drivers/usb/otg/isp1301_omap.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/usb/otg/isp1301_omap.c 2011-03-09 13:19:19.487311321 +0100 -@@ -1510,7 +1510,7 @@ - - /*-------------------------------------------------------------------------*/ - --static int __init -+static int __devinit - isp1301_probe(struct i2c_client *i2c, const struct i2c_device_id *id) - { - int status; -diff -Naur linux-2.6.38-rc7/drivers/video/omap/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap/Kconfig ---- linux-2.6.38-rc7/drivers/video/omap/Kconfig 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap/Kconfig 2011-03-09 13:19:21.072279166 +0100 -@@ -5,13 +5,18 @@ - select FB_CFB_FILLRECT - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT -+ select TWL4030_CORE if MACH_OMAP_2430SDP - help - Frame buffer driver for OMAP based boards. - - config FB_OMAP_LCD_VGA - bool "Use LCD in VGA mode" - depends on MACH_OMAP_3430SDP || MACH_OMAP_LDP -- -+ help -+ Set LCD resolution as VGA (640 X 480). -+ Default resolution without this option is QVGA(320 X 240). -+ Please take a look at drivers/video/omap/lcd_ldp.c file -+ for lcd driver code. - choice - depends on FB_OMAP && MACH_OVERO - prompt "Screen resolution" -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/displays/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/Kconfig ---- linux-2.6.38-rc7/drivers/video/omap2/displays/Kconfig 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/Kconfig 2011-03-09 13:19:21.079279025 +0100 -@@ -9,6 +9,12 @@ - Supports LCD Panel used in TI SDP3430 and EVM boards, - OMAP3517 EVM boards and CM-T35. - -+config PANEL_LGPHILIPS_LB035Q02 -+ tristate "LG.Philips LB035Q02 LCD Panel" -+ depends on OMAP2_DSS && SPI -+ help -+ LCD Panel used on the Gumstix Overo Palo35 -+ - config PANEL_SHARP_LS037V7DW01 - tristate "Sharp LS037V7DW01 LCD Panel" - depends on OMAP2_DSS -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/displays/Makefile linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/Makefile ---- linux-2.6.38-rc7/drivers/video/omap2/displays/Makefile 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/Makefile 2011-03-09 13:19:21.079279025 +0100 -@@ -1,4 +1,5 @@ - obj-$(CONFIG_PANEL_GENERIC_DPI) += panel-generic-dpi.o -+obj-$(CONFIG_PANEL_LGPHILIPS_LB035Q02) += panel-lgphilips-lb035q02.o - obj-$(CONFIG_PANEL_SHARP_LS037V7DW01) += panel-sharp-ls037v7dw01.o - obj-$(CONFIG_PANEL_NEC_NL8048HL11_01B) += panel-nec-nl8048hl11-01b.o - -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/displays/panel-generic-dpi.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/panel-generic-dpi.c ---- linux-2.6.38-rc7/drivers/video/omap2/displays/panel-generic-dpi.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/panel-generic-dpi.c 2011-03-09 13:19:21.080279004 +0100 -@@ -156,6 +156,31 @@ - .power_off_delay = 0, - .name = "toppoly_tdo35s", - }, -+ -+ /* Samsung LTE430WQ-F0C */ -+ { -+ { -+ .x_res = 480, -+ .y_res = 272, -+ -+ .pixel_clock = 9200, -+ -+ .hfp = 8, -+ .hsw = 41, -+ .hbp = 45 - 41, -+ -+ .vfp = 4, -+ .vsw = 10, -+ .vbp = 12 - 10, -+ }, -+ .acbi = 0x0, -+ .acb = 0x0, -+ .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | -+ OMAP_DSS_LCD_IHS, -+ .power_on_delay = 0, -+ .power_off_delay = 0, -+ .name = "samsung_lte430wq_f0c", -+ }, - }; - - struct panel_drv_data { -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c ---- linux-2.6.38-rc7/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c 2011-03-09 13:19:21.080279004 +0100 -@@ -0,0 +1,279 @@ -+/* -+ * LCD panel driver for LG.Philips LB035Q02 -+ * -+ * Author: Steve Sakoman -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+struct lb035q02_data { -+ struct mutex lock; -+}; -+ -+static struct omap_video_timings lb035q02_timings = { -+ .x_res = 320, -+ .y_res = 240, -+ -+ .pixel_clock = 6500, -+ -+ .hsw = 2, -+ .hfp = 20, -+ .hbp = 68, -+ -+ .vsw = 2, -+ .vfp = 4, -+ .vbp = 18, -+}; -+ -+static int lb035q02_panel_power_on(struct omap_dss_device *dssdev) -+{ -+ int r; -+ -+ if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) -+ return 0; -+ -+ r = omapdss_dpi_display_enable(dssdev); -+ if (r) -+ goto err0; -+ -+ if (dssdev->platform_enable) { -+ r = dssdev->platform_enable(dssdev); -+ if (r) -+ goto err1; -+ } -+ -+ return 0; -+err1: -+ omapdss_dpi_display_disable(dssdev); -+err0: -+ return r; -+} -+ -+static void lb035q02_panel_power_off(struct omap_dss_device *dssdev) -+{ -+ if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) -+ return; -+ -+ if (dssdev->platform_disable) -+ dssdev->platform_disable(dssdev); -+ -+ omapdss_dpi_display_disable(dssdev); -+} -+ -+static int lb035q02_panel_probe(struct omap_dss_device *dssdev) -+{ -+ struct lb035q02_data *ld; -+ int r; -+ -+ dssdev->panel.config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | -+ OMAP_DSS_LCD_IHS; -+ dssdev->panel.timings = lb035q02_timings; -+ -+ ld = kzalloc(sizeof(*ld), GFP_KERNEL); -+ if (!ld) { -+ r = -ENOMEM; -+ goto err; -+ } -+ mutex_init(&ld->lock); -+ dev_set_drvdata(&dssdev->dev, ld); -+ return 0; -+err: -+ return r; -+} -+ -+static void lb035q02_panel_remove(struct omap_dss_device *dssdev) -+{ -+ struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev); -+ -+ kfree(ld); -+} -+ -+static int lb035q02_panel_enable(struct omap_dss_device *dssdev) -+{ -+ struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev); -+ int r; -+ -+ mutex_lock(&ld->lock); -+ -+ r = lb035q02_panel_power_on(dssdev); -+ if (r) -+ goto err; -+ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; -+ -+ mutex_unlock(&ld->lock); -+ return 0; -+err: -+ mutex_unlock(&ld->lock); -+ return r; -+} -+ -+static void lb035q02_panel_disable(struct omap_dss_device *dssdev) -+{ -+ struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev); -+ -+ mutex_lock(&ld->lock); -+ -+ lb035q02_panel_power_off(dssdev); -+ dssdev->state = OMAP_DSS_DISPLAY_DISABLED; -+ -+ mutex_unlock(&ld->lock); -+} -+ -+static int lb035q02_panel_suspend(struct omap_dss_device *dssdev) -+{ -+ struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev); -+ -+ mutex_lock(&ld->lock); -+ -+ lb035q02_panel_power_off(dssdev); -+ dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED; -+ -+ mutex_unlock(&ld->lock); -+ return 0; -+} -+ -+static int lb035q02_panel_resume(struct omap_dss_device *dssdev) -+{ -+ struct lb035q02_data *ld = dev_get_drvdata(&dssdev->dev); -+ int r; -+ -+ mutex_lock(&ld->lock); -+ -+ r = lb035q02_panel_power_on(dssdev); -+ if (r) -+ goto err; -+ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; -+ -+ mutex_unlock(&ld->lock); -+ return 0; -+err: -+ mutex_unlock(&ld->lock); -+ return r; -+} -+ -+static struct omap_dss_driver lb035q02_driver = { -+ .probe = lb035q02_panel_probe, -+ .remove = lb035q02_panel_remove, -+ -+ .enable = lb035q02_panel_enable, -+ .disable = lb035q02_panel_disable, -+ .suspend = lb035q02_panel_suspend, -+ .resume = lb035q02_panel_resume, -+ -+ .driver = { -+ .name = "lgphilips_lb035q02_panel", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int lb035q02_write_reg(struct spi_device *spi, u8 reg, u16 val) -+{ -+ struct spi_message msg; -+ struct spi_transfer index_xfer = { -+ .len = 3, -+ .cs_change = 1, -+ }; -+ struct spi_transfer value_xfer = { -+ .len = 3, -+ }; -+ u8 buffer[16]; -+ -+ spi_message_init(&msg); -+ -+ /* register index */ -+ buffer[0] = 0x70; -+ buffer[1] = 0x00; -+ buffer[2] = reg & 0x7f; -+ index_xfer.tx_buf = buffer; -+ spi_message_add_tail(&index_xfer, &msg); -+ -+ /* register value */ -+ buffer[4] = 0x72; -+ buffer[5] = val >> 8; -+ buffer[6] = val; -+ value_xfer.tx_buf = buffer + 4; -+ spi_message_add_tail(&value_xfer, &msg); -+ -+ return spi_sync(spi, &msg); -+} -+ -+static void init_lb035q02_panel(struct spi_device *spi) -+{ -+ /* Init sequence from page 28 of the lb035q02 spec */ -+ lb035q02_write_reg(spi, 0x01, 0x6300); -+ lb035q02_write_reg(spi, 0x02, 0x0200); -+ lb035q02_write_reg(spi, 0x03, 0x0177); -+ lb035q02_write_reg(spi, 0x04, 0x04c7); -+ lb035q02_write_reg(spi, 0x05, 0xffc0); -+ lb035q02_write_reg(spi, 0x06, 0xe806); -+ lb035q02_write_reg(spi, 0x0a, 0x4008); -+ lb035q02_write_reg(spi, 0x0b, 0x0000); -+ lb035q02_write_reg(spi, 0x0d, 0x0030); -+ lb035q02_write_reg(spi, 0x0e, 0x2800); -+ lb035q02_write_reg(spi, 0x0f, 0x0000); -+ lb035q02_write_reg(spi, 0x16, 0x9f80); -+ lb035q02_write_reg(spi, 0x17, 0x0a0f); -+ lb035q02_write_reg(spi, 0x1e, 0x00c1); -+ lb035q02_write_reg(spi, 0x30, 0x0300); -+ lb035q02_write_reg(spi, 0x31, 0x0007); -+ lb035q02_write_reg(spi, 0x32, 0x0000); -+ lb035q02_write_reg(spi, 0x33, 0x0000); -+ lb035q02_write_reg(spi, 0x34, 0x0707); -+ lb035q02_write_reg(spi, 0x35, 0x0004); -+ lb035q02_write_reg(spi, 0x36, 0x0302); -+ lb035q02_write_reg(spi, 0x37, 0x0202); -+ lb035q02_write_reg(spi, 0x3a, 0x0a0d); -+ lb035q02_write_reg(spi, 0x3b, 0x0806); -+} -+ -+static int __devinit lb035q02_panel_spi_probe(struct spi_device *spi) -+{ -+ init_lb035q02_panel(spi); -+ return omap_dss_register_driver(&lb035q02_driver); -+} -+ -+static int __devexit lb035q02_panel_spi_remove(struct spi_device *spi) -+{ -+ omap_dss_unregister_driver(&lb035q02_driver); -+ return 0; -+} -+ -+static struct spi_driver lb035q02_spi_driver = { -+ .driver = { -+ .name = "lgphilips_lb035q02_panel-spi", -+ .owner = THIS_MODULE, -+ }, -+ .probe = lb035q02_panel_spi_probe, -+ .remove = __devexit_p(lb035q02_panel_spi_remove), -+}; -+ -+static int __init lb035q02_panel_drv_init(void) -+{ -+ return spi_register_driver(&lb035q02_spi_driver); -+} -+ -+static void __exit lb035q02_panel_drv_exit(void) -+{ -+ spi_unregister_driver(&lb035q02_spi_driver); -+} -+ -+module_init(lb035q02_panel_drv_init); -+module_exit(lb035q02_panel_drv_exit); -+MODULE_LICENSE("GPL"); -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/displays/panel-taal.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/panel-taal.c ---- linux-2.6.38-rc7/drivers/video/omap2/displays/panel-taal.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/displays/panel-taal.c 2011-03-09 13:19:21.081278983 +0100 -@@ -218,6 +218,8 @@ - u16 w; - u16 h; - } update_region; -+ int channel; -+ - struct delayed_work te_timeout_work; - - bool use_dsi_bl; -@@ -257,12 +259,12 @@ - } - } - --static int taal_dcs_read_1(u8 dcs_cmd, u8 *data) -+static int taal_dcs_read_1(struct taal_data *td, u8 dcs_cmd, u8 *data) - { - int r; - u8 buf[1]; - -- r = dsi_vc_dcs_read(TCH, dcs_cmd, buf, 1); -+ r = dsi_vc_dcs_read(td->channel, dcs_cmd, buf, 1); - - if (r < 0) - return r; -@@ -272,17 +274,17 @@ - return 0; - } - --static int taal_dcs_write_0(u8 dcs_cmd) -+static int taal_dcs_write_0(struct taal_data *td, u8 dcs_cmd) - { -- return dsi_vc_dcs_write(TCH, &dcs_cmd, 1); -+ return dsi_vc_dcs_write(td->channel, &dcs_cmd, 1); - } - --static int taal_dcs_write_1(u8 dcs_cmd, u8 param) -+static int taal_dcs_write_1(struct taal_data *td, u8 dcs_cmd, u8 param) - { - u8 buf[2]; - buf[0] = dcs_cmd; - buf[1] = param; -- return dsi_vc_dcs_write(TCH, buf, 2); -+ return dsi_vc_dcs_write(td->channel, buf, 2); - } - - static int taal_sleep_in(struct taal_data *td) -@@ -294,7 +296,7 @@ - hw_guard_wait(td); - - cmd = DCS_SLEEP_IN; -- r = dsi_vc_dcs_write_nosync(TCH, &cmd, 1); -+ r = dsi_vc_dcs_write_nosync(td->channel, &cmd, 1); - if (r) - return r; - -@@ -312,7 +314,7 @@ - - hw_guard_wait(td); - -- r = taal_dcs_write_0(DCS_SLEEP_OUT); -+ r = taal_dcs_write_0(td, DCS_SLEEP_OUT); - if (r) - return r; - -@@ -324,30 +326,30 @@ - return 0; - } - --static int taal_get_id(u8 *id1, u8 *id2, u8 *id3) -+static int taal_get_id(struct taal_data *td, u8 *id1, u8 *id2, u8 *id3) - { - int r; - -- r = taal_dcs_read_1(DCS_GET_ID1, id1); -+ r = taal_dcs_read_1(td, DCS_GET_ID1, id1); - if (r) - return r; -- r = taal_dcs_read_1(DCS_GET_ID2, id2); -+ r = taal_dcs_read_1(td, DCS_GET_ID2, id2); - if (r) - return r; -- r = taal_dcs_read_1(DCS_GET_ID3, id3); -+ r = taal_dcs_read_1(td, DCS_GET_ID3, id3); - if (r) - return r; - - return 0; - } - --static int taal_set_addr_mode(u8 rotate, bool mirror) -+static int taal_set_addr_mode(struct taal_data *td, u8 rotate, bool mirror) - { - int r; - u8 mode; - int b5, b6, b7; - -- r = taal_dcs_read_1(DCS_READ_MADCTL, &mode); -+ r = taal_dcs_read_1(td, DCS_READ_MADCTL, &mode); - if (r) - return r; - -@@ -381,10 +383,11 @@ - mode &= ~((1<<7) | (1<<6) | (1<<5)); - mode |= (b7 << 7) | (b6 << 6) | (b5 << 5); - -- return taal_dcs_write_1(DCS_MEM_ACC_CTRL, mode); -+ return taal_dcs_write_1(td, DCS_MEM_ACC_CTRL, mode); - } - --static int taal_set_update_window(u16 x, u16 y, u16 w, u16 h) -+static int taal_set_update_window(struct taal_data *td, -+ u16 x, u16 y, u16 w, u16 h) - { - int r; - u16 x1 = x; -@@ -399,7 +402,7 @@ - buf[3] = (x2 >> 8) & 0xff; - buf[4] = (x2 >> 0) & 0xff; - -- r = dsi_vc_dcs_write_nosync(TCH, buf, sizeof(buf)); -+ r = dsi_vc_dcs_write_nosync(td->channel, buf, sizeof(buf)); - if (r) - return r; - -@@ -409,11 +412,11 @@ - buf[3] = (y2 >> 8) & 0xff; - buf[4] = (y2 >> 0) & 0xff; - -- r = dsi_vc_dcs_write_nosync(TCH, buf, sizeof(buf)); -+ r = dsi_vc_dcs_write_nosync(td->channel, buf, sizeof(buf)); - if (r) - return r; - -- dsi_vc_send_bta_sync(TCH); -+ dsi_vc_send_bta_sync(td->channel); - - return r; - } -@@ -439,7 +442,7 @@ - if (td->use_dsi_bl) { - if (td->enabled) { - dsi_bus_lock(); -- r = taal_dcs_write_1(DCS_BRIGHTNESS, level); -+ r = taal_dcs_write_1(td, DCS_BRIGHTNESS, level); - dsi_bus_unlock(); - } else { - r = 0; -@@ -502,7 +505,7 @@ - - if (td->enabled) { - dsi_bus_lock(); -- r = taal_dcs_read_1(DCS_READ_NUM_ERRORS, &errors); -+ r = taal_dcs_read_1(td, DCS_READ_NUM_ERRORS, &errors); - dsi_bus_unlock(); - } else { - r = -ENODEV; -@@ -528,7 +531,7 @@ - - if (td->enabled) { - dsi_bus_lock(); -- r = taal_get_id(&id1, &id2, &id3); -+ r = taal_get_id(td, &id1, &id2, &id3); - dsi_bus_unlock(); - } else { - r = -ENODEV; -@@ -590,7 +593,7 @@ - if (td->enabled) { - dsi_bus_lock(); - if (!td->cabc_broken) -- taal_dcs_write_1(DCS_WRITE_CABC, i); -+ taal_dcs_write_1(td, DCS_WRITE_CABC, i); - dsi_bus_unlock(); - } - -@@ -774,14 +777,29 @@ - dev_dbg(&dssdev->dev, "Using GPIO TE\n"); - } - -+ r = omap_dsi_request_vc(dssdev, &td->channel); -+ if (r) { -+ dev_err(&dssdev->dev, "failed to get virtual channel\n"); -+ goto err_req_vc; -+ } -+ -+ r = omap_dsi_set_vc_id(dssdev, td->channel, TCH); -+ if (r) { -+ dev_err(&dssdev->dev, "failed to set VC_ID\n"); -+ goto err_vc_id; -+ } -+ - r = sysfs_create_group(&dssdev->dev.kobj, &taal_attr_group); - if (r) { - dev_err(&dssdev->dev, "failed to create sysfs files\n"); -- goto err_sysfs; -+ goto err_vc_id; - } - - return 0; --err_sysfs: -+ -+err_vc_id: -+ omap_dsi_release_vc(dssdev, td->channel); -+err_req_vc: - if (panel_data->use_ext_te) - free_irq(gpio_to_irq(panel_data->ext_te_gpio), dssdev); - err_irq: -@@ -808,6 +826,7 @@ - dev_dbg(&dssdev->dev, "remove\n"); - - sysfs_remove_group(&dssdev->dev.kobj, &taal_attr_group); -+ omap_dsi_release_vc(dssdev, td->channel); - - if (panel_data->use_ext_te) { - int gpio = panel_data->ext_te_gpio; -@@ -846,13 +865,13 @@ - - taal_hw_reset(dssdev); - -- omapdss_dsi_vc_enable_hs(TCH, false); -+ omapdss_dsi_vc_enable_hs(td->channel, false); - - r = taal_sleep_out(td); - if (r) - goto err; - -- r = taal_get_id(&id1, &id2, &id3); -+ r = taal_get_id(td, &id1, &id2, &id3); - if (r) - goto err; - -@@ -861,30 +880,30 @@ - (id2 == 0x00 || id2 == 0xff || id2 == 0x81)) - td->cabc_broken = true; - -- r = taal_dcs_write_1(DCS_BRIGHTNESS, 0xff); -+ r = taal_dcs_write_1(td, DCS_BRIGHTNESS, 0xff); - if (r) - goto err; - -- r = taal_dcs_write_1(DCS_CTRL_DISPLAY, -+ r = taal_dcs_write_1(td, DCS_CTRL_DISPLAY, - (1<<2) | (1<<5)); /* BL | BCTRL */ - if (r) - goto err; - -- r = taal_dcs_write_1(DCS_PIXEL_FORMAT, 0x7); /* 24bit/pixel */ -+ r = taal_dcs_write_1(td, DCS_PIXEL_FORMAT, 0x7); /* 24bit/pixel */ - if (r) - goto err; - -- r = taal_set_addr_mode(td->rotate, td->mirror); -+ r = taal_set_addr_mode(td, td->rotate, td->mirror); - if (r) - goto err; - - if (!td->cabc_broken) { -- r = taal_dcs_write_1(DCS_WRITE_CABC, td->cabc_mode); -+ r = taal_dcs_write_1(td, DCS_WRITE_CABC, td->cabc_mode); - if (r) - goto err; - } - -- r = taal_dcs_write_0(DCS_DISPLAY_ON); -+ r = taal_dcs_write_0(td, DCS_DISPLAY_ON); - if (r) - goto err; - -@@ -903,7 +922,7 @@ - td->intro_printed = true; - } - -- omapdss_dsi_vc_enable_hs(TCH, true); -+ omapdss_dsi_vc_enable_hs(td->channel, true); - - return 0; - err: -@@ -921,7 +940,7 @@ - struct taal_data *td = dev_get_drvdata(&dssdev->dev); - int r; - -- r = taal_dcs_write_0(DCS_DISPLAY_OFF); -+ r = taal_dcs_write_0(td, DCS_DISPLAY_OFF); - if (!r) { - r = taal_sleep_in(td); - /* HACK: wait a bit so that the message goes through */ -@@ -1089,7 +1108,7 @@ - if (old) { - cancel_delayed_work(&td->te_timeout_work); - -- r = omap_dsi_update(dssdev, TCH, -+ r = omap_dsi_update(dssdev, td->channel, - td->update_region.x, - td->update_region.y, - td->update_region.w, -@@ -1139,7 +1158,7 @@ - if (r) - goto err; - -- r = taal_set_update_window(x, y, w, h); -+ r = taal_set_update_window(td, x, y, w, h); - if (r) - goto err; - -@@ -1153,7 +1172,7 @@ - msecs_to_jiffies(250)); - atomic_set(&td->do_update, 1); - } else { -- r = omap_dsi_update(dssdev, TCH, x, y, w, h, -+ r = omap_dsi_update(dssdev, td->channel, x, y, w, h, - taal_framedone_cb, dssdev); - if (r) - goto err; -@@ -1191,9 +1210,9 @@ - int r; - - if (enable) -- r = taal_dcs_write_1(DCS_TEAR_ON, 0); -+ r = taal_dcs_write_1(td, DCS_TEAR_ON, 0); - else -- r = taal_dcs_write_0(DCS_TEAR_OFF); -+ r = taal_dcs_write_0(td, DCS_TEAR_OFF); - - if (!panel_data->use_ext_te) - omapdss_dsi_enable_te(dssdev, enable); -@@ -1263,7 +1282,7 @@ - dsi_bus_lock(); - - if (td->enabled) { -- r = taal_set_addr_mode(rotate, td->mirror); -+ r = taal_set_addr_mode(td, rotate, td->mirror); - if (r) - goto err; - } -@@ -1306,7 +1325,7 @@ - - dsi_bus_lock(); - if (td->enabled) { -- r = taal_set_addr_mode(td->rotate, enable); -+ r = taal_set_addr_mode(td, td->rotate, enable); - if (r) - goto err; - } -@@ -1350,13 +1369,13 @@ - - dsi_bus_lock(); - -- r = taal_dcs_read_1(DCS_GET_ID1, &id1); -+ r = taal_dcs_read_1(td, DCS_GET_ID1, &id1); - if (r) - goto err2; -- r = taal_dcs_read_1(DCS_GET_ID2, &id2); -+ r = taal_dcs_read_1(td, DCS_GET_ID2, &id2); - if (r) - goto err2; -- r = taal_dcs_read_1(DCS_GET_ID3, &id3); -+ r = taal_dcs_read_1(td, DCS_GET_ID3, &id3); - if (r) - goto err2; - -@@ -1404,9 +1423,9 @@ - else - plen = 2; - -- taal_set_update_window(x, y, w, h); -+ taal_set_update_window(td, x, y, w, h); - -- r = dsi_vc_set_max_rx_packet_size(TCH, plen); -+ r = dsi_vc_set_max_rx_packet_size(td->channel, plen); - if (r) - goto err2; - -@@ -1414,7 +1433,7 @@ - u8 dcs_cmd = first ? 0x2e : 0x3e; - first = 0; - -- r = dsi_vc_dcs_read(TCH, dcs_cmd, -+ r = dsi_vc_dcs_read(td->channel, dcs_cmd, - buf + buf_used, size - buf_used); - - if (r < 0) { -@@ -1440,7 +1459,7 @@ - r = buf_used; - - err3: -- dsi_vc_set_max_rx_packet_size(TCH, 1); -+ dsi_vc_set_max_rx_packet_size(td->channel, 1); - err2: - dsi_bus_unlock(); - err1: -@@ -1466,7 +1485,7 @@ - - dsi_bus_lock(); - -- r = taal_dcs_read_1(DCS_RDDSDR, &state1); -+ r = taal_dcs_read_1(td, DCS_RDDSDR, &state1); - if (r) { - dev_err(&dssdev->dev, "failed to read Taal status\n"); - goto err; -@@ -1479,7 +1498,7 @@ - goto err; - } - -- r = taal_dcs_read_1(DCS_RDDSDR, &state2); -+ r = taal_dcs_read_1(td, DCS_RDDSDR, &state2); - if (r) { - dev_err(&dssdev->dev, "failed to read Taal status\n"); - goto err; -@@ -1495,7 +1514,7 @@ - /* Self-diagnostics result is also shown on TE GPIO line. We need - * to re-enable TE after self diagnostics */ - if (td->te_enabled && panel_data->use_ext_te) { -- r = taal_dcs_write_1(DCS_TEAR_ON, 0); -+ r = taal_dcs_write_1(td, DCS_TEAR_ON, 0); - if (r) - goto err; - } -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/core.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/core.c ---- linux-2.6.38-rc7/drivers/video/omap2/dss/core.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/core.c 2011-03-09 13:19:21.083278942 +0100 -@@ -34,332 +34,26 @@ - #include - - #include --#include - - #include "dss.h" - #include "dss_features.h" - - static struct { - struct platform_device *pdev; -- int ctx_id; -- -- struct clk *dss_ick; -- struct clk *dss1_fck; -- struct clk *dss2_fck; -- struct clk *dss_54m_fck; -- struct clk *dss_96m_fck; -- unsigned num_clks_enabled; - - struct regulator *vdds_dsi_reg; - struct regulator *vdds_sdi_reg; -- struct regulator *vdda_dac_reg; - } core; - --static void dss_clk_enable_all_no_ctx(void); --static void dss_clk_disable_all_no_ctx(void); --static void dss_clk_enable_no_ctx(enum dss_clock clks); --static void dss_clk_disable_no_ctx(enum dss_clock clks); -- - static char *def_disp_name; - module_param_named(def_disp, def_disp_name, charp, 0); --MODULE_PARM_DESC(def_disp_name, "default display name"); -+MODULE_PARM_DESC(def_disp, "default display name"); - - #ifdef DEBUG - unsigned int dss_debug; - module_param_named(debug, dss_debug, bool, 0644); - #endif - --/* CONTEXT */ --static int dss_get_ctx_id(void) --{ -- struct omap_dss_board_info *pdata = core.pdev->dev.platform_data; -- int r; -- -- if (!pdata->get_last_off_on_transaction_id) -- return 0; -- r = pdata->get_last_off_on_transaction_id(&core.pdev->dev); -- if (r < 0) { -- dev_err(&core.pdev->dev, "getting transaction ID failed, " -- "will force context restore\n"); -- r = -1; -- } -- return r; --} -- --int dss_need_ctx_restore(void) --{ -- int id = dss_get_ctx_id(); -- -- if (id < 0 || id != core.ctx_id) { -- DSSDBG("ctx id %d -> id %d\n", -- core.ctx_id, id); -- core.ctx_id = id; -- return 1; -- } else { -- return 0; -- } --} -- --static void save_all_ctx(void) --{ -- DSSDBG("save context\n"); -- -- dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); -- -- dss_save_context(); -- dispc_save_context(); --#ifdef CONFIG_OMAP2_DSS_DSI -- dsi_save_context(); --#endif -- -- dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1); --} -- --static void restore_all_ctx(void) --{ -- DSSDBG("restore context\n"); -- -- dss_clk_enable_all_no_ctx(); -- -- dss_restore_context(); -- dispc_restore_context(); --#ifdef CONFIG_OMAP2_DSS_DSI -- dsi_restore_context(); --#endif -- -- dss_clk_disable_all_no_ctx(); --} -- --#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) --/* CLOCKS */ --static void core_dump_clocks(struct seq_file *s) --{ -- int i; -- struct clk *clocks[5] = { -- core.dss_ick, -- core.dss1_fck, -- core.dss2_fck, -- core.dss_54m_fck, -- core.dss_96m_fck -- }; -- -- seq_printf(s, "- CORE -\n"); -- -- seq_printf(s, "internal clk count\t\t%u\n", core.num_clks_enabled); -- -- for (i = 0; i < 5; i++) { -- if (!clocks[i]) -- continue; -- seq_printf(s, "%-15s\t%lu\t%d\n", -- clocks[i]->name, -- clk_get_rate(clocks[i]), -- clocks[i]->usecount); -- } --} --#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */ -- --static int dss_get_clock(struct clk **clock, const char *clk_name) --{ -- struct clk *clk; -- -- clk = clk_get(&core.pdev->dev, clk_name); -- -- if (IS_ERR(clk)) { -- DSSERR("can't get clock %s", clk_name); -- return PTR_ERR(clk); -- } -- -- *clock = clk; -- -- DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk)); -- -- return 0; --} -- --static int dss_get_clocks(void) --{ -- int r; -- -- core.dss_ick = NULL; -- core.dss1_fck = NULL; -- core.dss2_fck = NULL; -- core.dss_54m_fck = NULL; -- core.dss_96m_fck = NULL; -- -- r = dss_get_clock(&core.dss_ick, "ick"); -- if (r) -- goto err; -- -- r = dss_get_clock(&core.dss1_fck, "dss1_fck"); -- if (r) -- goto err; -- -- r = dss_get_clock(&core.dss2_fck, "dss2_fck"); -- if (r) -- goto err; -- -- r = dss_get_clock(&core.dss_54m_fck, "tv_fck"); -- if (r) -- goto err; -- -- r = dss_get_clock(&core.dss_96m_fck, "video_fck"); -- if (r) -- goto err; -- -- return 0; -- --err: -- if (core.dss_ick) -- clk_put(core.dss_ick); -- if (core.dss1_fck) -- clk_put(core.dss1_fck); -- if (core.dss2_fck) -- clk_put(core.dss2_fck); -- if (core.dss_54m_fck) -- clk_put(core.dss_54m_fck); -- if (core.dss_96m_fck) -- clk_put(core.dss_96m_fck); -- -- return r; --} -- --static void dss_put_clocks(void) --{ -- if (core.dss_96m_fck) -- clk_put(core.dss_96m_fck); -- clk_put(core.dss_54m_fck); -- clk_put(core.dss1_fck); -- clk_put(core.dss2_fck); -- clk_put(core.dss_ick); --} -- --unsigned long dss_clk_get_rate(enum dss_clock clk) --{ -- switch (clk) { -- case DSS_CLK_ICK: -- return clk_get_rate(core.dss_ick); -- case DSS_CLK_FCK1: -- return clk_get_rate(core.dss1_fck); -- case DSS_CLK_FCK2: -- return clk_get_rate(core.dss2_fck); -- case DSS_CLK_54M: -- return clk_get_rate(core.dss_54m_fck); -- case DSS_CLK_96M: -- return clk_get_rate(core.dss_96m_fck); -- } -- -- BUG(); -- return 0; --} -- --static unsigned count_clk_bits(enum dss_clock clks) --{ -- unsigned num_clks = 0; -- -- if (clks & DSS_CLK_ICK) -- ++num_clks; -- if (clks & DSS_CLK_FCK1) -- ++num_clks; -- if (clks & DSS_CLK_FCK2) -- ++num_clks; -- if (clks & DSS_CLK_54M) -- ++num_clks; -- if (clks & DSS_CLK_96M) -- ++num_clks; -- -- return num_clks; --} -- --static void dss_clk_enable_no_ctx(enum dss_clock clks) --{ -- unsigned num_clks = count_clk_bits(clks); -- -- if (clks & DSS_CLK_ICK) -- clk_enable(core.dss_ick); -- if (clks & DSS_CLK_FCK1) -- clk_enable(core.dss1_fck); -- if (clks & DSS_CLK_FCK2) -- clk_enable(core.dss2_fck); -- if (clks & DSS_CLK_54M) -- clk_enable(core.dss_54m_fck); -- if (clks & DSS_CLK_96M) -- clk_enable(core.dss_96m_fck); -- -- core.num_clks_enabled += num_clks; --} -- --void dss_clk_enable(enum dss_clock clks) --{ -- bool check_ctx = core.num_clks_enabled == 0; -- -- dss_clk_enable_no_ctx(clks); -- -- if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore()) -- restore_all_ctx(); --} -- --static void dss_clk_disable_no_ctx(enum dss_clock clks) --{ -- unsigned num_clks = count_clk_bits(clks); -- -- if (clks & DSS_CLK_ICK) -- clk_disable(core.dss_ick); -- if (clks & DSS_CLK_FCK1) -- clk_disable(core.dss1_fck); -- if (clks & DSS_CLK_FCK2) -- clk_disable(core.dss2_fck); -- if (clks & DSS_CLK_54M) -- clk_disable(core.dss_54m_fck); -- if (clks & DSS_CLK_96M) -- clk_disable(core.dss_96m_fck); -- -- core.num_clks_enabled -= num_clks; --} -- --void dss_clk_disable(enum dss_clock clks) --{ -- if (cpu_is_omap34xx()) { -- unsigned num_clks = count_clk_bits(clks); -- -- BUG_ON(core.num_clks_enabled < num_clks); -- -- if (core.num_clks_enabled == num_clks) -- save_all_ctx(); -- } -- -- dss_clk_disable_no_ctx(clks); --} -- --static void dss_clk_enable_all_no_ctx(void) --{ -- enum dss_clock clks; -- -- clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; -- if (cpu_is_omap34xx()) -- clks |= DSS_CLK_96M; -- dss_clk_enable_no_ctx(clks); --} -- --static void dss_clk_disable_all_no_ctx(void) --{ -- enum dss_clock clks; -- -- clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; -- if (cpu_is_omap34xx()) -- clks |= DSS_CLK_96M; -- dss_clk_disable_no_ctx(clks); --} -- --static void dss_clk_disable_all(void) --{ -- enum dss_clock clks; -- -- clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M; -- if (cpu_is_omap34xx()) -- clks |= DSS_CLK_96M; -- dss_clk_disable(clks); --} -- - /* REGULATORS */ - - struct regulator *dss_get_vdds_dsi(void) -@@ -390,32 +84,7 @@ - return reg; - } - --struct regulator *dss_get_vdda_dac(void) --{ -- struct regulator *reg; -- -- if (core.vdda_dac_reg != NULL) -- return core.vdda_dac_reg; -- -- reg = regulator_get(&core.pdev->dev, "vdda_dac"); -- if (!IS_ERR(reg)) -- core.vdda_dac_reg = reg; -- -- return reg; --} -- --/* DEBUGFS */ - #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) --static void dss_debug_dump_clocks(struct seq_file *s) --{ -- core_dump_clocks(s); -- dss_dump_clocks(s); -- dispc_dump_clocks(s); --#ifdef CONFIG_OMAP2_DSS_DSI -- dsi_dump_clocks(s); --#endif --} -- - static int dss_debug_show(struct seq_file *s, void *unused) - { - void (*func)(struct seq_file *) = s->private; -@@ -497,7 +166,6 @@ - static int omap_dss_probe(struct platform_device *pdev) - { - struct omap_dss_board_info *pdata = pdev->dev.platform_data; -- int skip_init = 0; - int r; - int i; - -@@ -508,63 +176,37 @@ - dss_init_overlay_managers(pdev); - dss_init_overlays(pdev); - -- r = dss_get_clocks(); -- if (r) -- goto err_clocks; -- -- dss_clk_enable_all_no_ctx(); -- -- core.ctx_id = dss_get_ctx_id(); -- DSSDBG("initial ctx id %u\n", core.ctx_id); -- --#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT -- /* DISPC_CONTROL */ -- if (omap_readl(0x48050440) & 1) /* LCD enabled? */ -- skip_init = 1; --#endif -- -- r = dss_init(skip_init); -+ r = dss_init_platform_driver(); - if (r) { -- DSSERR("Failed to initialize DSS\n"); -+ DSSERR("Failed to initialize DSS platform driver\n"); - goto err_dss; - } - -- r = rfbi_init(); -- if (r) { -- DSSERR("Failed to initialize rfbi\n"); -- goto err_rfbi; -- } -+ /* keep clocks enabled to prevent context saves/restores during init */ -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); - -- r = dpi_init(pdev); -+ r = rfbi_init_platform_driver(); - if (r) { -- DSSERR("Failed to initialize dpi\n"); -- goto err_dpi; -+ DSSERR("Failed to initialize rfbi platform driver\n"); -+ goto err_rfbi; - } - -- r = dispc_init(); -+ r = dispc_init_platform_driver(); - if (r) { -- DSSERR("Failed to initialize dispc\n"); -+ DSSERR("Failed to initialize dispc platform driver\n"); - goto err_dispc; - } - -- r = venc_init(pdev); -+ r = venc_init_platform_driver(); - if (r) { -- DSSERR("Failed to initialize venc\n"); -+ DSSERR("Failed to initialize venc platform driver\n"); - goto err_venc; - } - -- if (cpu_is_omap34xx()) { -- r = sdi_init(skip_init); -- if (r) { -- DSSERR("Failed to initialize SDI\n"); -- goto err_sdi; -- } -- -- r = dsi_init(pdev); -- if (r) { -- DSSERR("Failed to initialize DSI\n"); -- goto err_dsi; -- } -+ r = dsi_init_platform_driver(); -+ if (r) { -+ DSSERR("Failed to initialize DSI platform driver\n"); -+ goto err_dsi; - } - - r = dss_initialize_debugfs(); -@@ -589,32 +231,23 @@ - pdata->default_device = dssdev; - } - -- dss_clk_disable_all(); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); - - return 0; - - err_register: - dss_uninitialize_debugfs(); - err_debugfs: -- if (cpu_is_omap34xx()) -- dsi_exit(); -+ dsi_uninit_platform_driver(); - err_dsi: -- if (cpu_is_omap34xx()) -- sdi_exit(); --err_sdi: -- venc_exit(); -+ venc_uninit_platform_driver(); - err_venc: -- dispc_exit(); -+ dispc_uninit_platform_driver(); - err_dispc: -- dpi_exit(); --err_dpi: -- rfbi_exit(); -+ rfbi_uninit_platform_driver(); - err_rfbi: -- dss_exit(); -+ dss_uninit_platform_driver(); - err_dss: -- dss_clk_disable_all_no_ctx(); -- dss_put_clocks(); --err_clocks: - - return r; - } -@@ -623,61 +256,14 @@ - { - struct omap_dss_board_info *pdata = pdev->dev.platform_data; - int i; -- int c; - - dss_uninitialize_debugfs(); - -- venc_exit(); -- dispc_exit(); -- dpi_exit(); -- rfbi_exit(); -- if (cpu_is_omap34xx()) { -- dsi_exit(); -- sdi_exit(); -- } -- -- dss_exit(); -- -- /* these should be removed at some point */ -- c = core.dss_ick->usecount; -- if (c > 0) { -- DSSERR("warning: dss_ick usecount %d, disabling\n", c); -- while (c-- > 0) -- clk_disable(core.dss_ick); -- } -- -- c = core.dss1_fck->usecount; -- if (c > 0) { -- DSSERR("warning: dss1_fck usecount %d, disabling\n", c); -- while (c-- > 0) -- clk_disable(core.dss1_fck); -- } -- -- c = core.dss2_fck->usecount; -- if (c > 0) { -- DSSERR("warning: dss2_fck usecount %d, disabling\n", c); -- while (c-- > 0) -- clk_disable(core.dss2_fck); -- } -- -- c = core.dss_54m_fck->usecount; -- if (c > 0) { -- DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c); -- while (c-- > 0) -- clk_disable(core.dss_54m_fck); -- } -- -- if (core.dss_96m_fck) { -- c = core.dss_96m_fck->usecount; -- if (c > 0) { -- DSSERR("warning: dss_96m_fck usecount %d, disabling\n", -- c); -- while (c-- > 0) -- clk_disable(core.dss_96m_fck); -- } -- } -- -- dss_put_clocks(); -+ venc_uninit_platform_driver(); -+ dispc_uninit_platform_driver(); -+ rfbi_uninit_platform_driver(); -+ dsi_uninit_platform_driver(); -+ dss_uninit_platform_driver(); - - dss_uninit_overlays(pdev); - dss_uninit_overlay_managers(pdev); -@@ -965,11 +551,6 @@ - core.vdds_sdi_reg = NULL; - } - -- if (core.vdda_dac_reg != NULL) { -- regulator_put(core.vdda_dac_reg); -- core.vdda_dac_reg = NULL; -- } -- - platform_driver_unregister(&omap_dss_driver); - - omap_dss_bus_unregister(); -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/dispc.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dispc.c ---- linux-2.6.38-rc7/drivers/video/omap2/dss/dispc.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dispc.c 2011-03-09 13:19:21.083278942 +0100 -@@ -32,6 +32,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -42,8 +43,6 @@ - #include "dss_features.h" - - /* DISPC */ --#define DISPC_BASE 0x48050400 -- - #define DISPC_SZ_REGS SZ_4K - - struct dispc_reg { u16 idx; }; -@@ -74,7 +73,7 @@ - #define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400) - #define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404) - #define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408) --#define DISPC_DIVISOR(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C) -+#define DISPC_DIVISORo(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C) - #define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074) - #define DISPC_SIZE_DIG DISPC_REG(0x0078) - #define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC) -@@ -129,6 +128,7 @@ - - #define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04) - -+#define DISPC_DIVISOR DISPC_REG(0x0804) - - #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \ - DISPC_IRQ_OCP_ERR | \ -@@ -178,7 +178,9 @@ - }; - - static struct { -+ struct platform_device *pdev; - void __iomem *base; -+ int irq; - - u32 fifo_size[3]; - -@@ -230,7 +232,7 @@ - SR(TIMING_H(0)); - SR(TIMING_V(0)); - SR(POL_FREQ(0)); -- SR(DIVISOR(0)); -+ SR(DIVISORo(0)); - SR(GLOBAL_ALPHA); - SR(SIZE_DIG); - SR(SIZE_LCD(0)); -@@ -242,7 +244,7 @@ - SR(TIMING_H(2)); - SR(TIMING_V(2)); - SR(POL_FREQ(2)); -- SR(DIVISOR(2)); -+ SR(DIVISORo(2)); - SR(CONFIG2); - } - -@@ -373,6 +375,9 @@ - SR(VID_FIR_COEF_V(1, 7)); - - SR(VID_PRELOAD(1)); -+ -+ if (dss_has_feature(FEAT_CORE_CLK_DIV)) -+ SR(DIVISOR); - } - - void dispc_restore_context(void) -@@ -389,7 +394,7 @@ - RR(TIMING_H(0)); - RR(TIMING_V(0)); - RR(POL_FREQ(0)); -- RR(DIVISOR(0)); -+ RR(DIVISORo(0)); - RR(GLOBAL_ALPHA); - RR(SIZE_DIG); - RR(SIZE_LCD(0)); -@@ -400,7 +405,7 @@ - RR(TIMING_H(2)); - RR(TIMING_V(2)); - RR(POL_FREQ(2)); -- RR(DIVISOR(2)); -+ RR(DIVISORo(2)); - RR(CONFIG2); - } - -@@ -532,6 +537,9 @@ - - RR(VID_PRELOAD(1)); - -+ if (dss_has_feature(FEAT_CORE_CLK_DIV)) -+ RR(DIVISOR); -+ - /* enable last, because LCD & DIGIT enable are here */ - RR(CONTROL); - if (dss_has_feature(FEAT_MGR_LCD2)) -@@ -552,9 +560,9 @@ - static inline void enable_clocks(bool enable) - { - if (enable) -- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); - else -- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); - } - - bool dispc_go_busy(enum omap_channel channel) -@@ -1129,10 +1137,16 @@ - u32 val; - const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0), - DISPC_VID_ACCU0(1) }; -+ u8 hor_start, hor_end, vert_start, vert_end; - - BUG_ON(plane == OMAP_DSS_GFX); - -- val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); -+ dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); -+ dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); -+ -+ val = FLD_VAL(vaccu, vert_start, vert_end) | -+ FLD_VAL(haccu, hor_start, hor_end); -+ - dispc_write_reg(ac0_reg[plane-1], val); - } - -@@ -1141,10 +1155,16 @@ - u32 val; - const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0), - DISPC_VID_ACCU1(1) }; -+ u8 hor_start, hor_end, vert_start, vert_end; - - BUG_ON(plane == OMAP_DSS_GFX); - -- val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0); -+ dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); -+ dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); -+ -+ val = FLD_VAL(vaccu, vert_start, vert_end) | -+ FLD_VAL(haccu, hor_start, hor_end); -+ - dispc_write_reg(ac1_reg[plane-1], val); - } - -@@ -1182,16 +1202,25 @@ - _dispc_set_fir(plane, fir_hinc, fir_vinc); - - l = dispc_read_reg(dispc_reg_att[plane]); -- l &= ~((0x0f << 5) | (0x3 << 21)); - -+ /* RESIZEENABLE and VERTICALTAPS */ -+ l &= ~((0x3 << 5) | (0x1 << 21)); - l |= fir_hinc ? (1 << 5) : 0; - l |= fir_vinc ? (1 << 6) : 0; -+ l |= five_taps ? (1 << 21) : 0; - -- l |= hscaleup ? 0 : (1 << 7); -- l |= vscaleup ? 0 : (1 << 8); -+ /* VRESIZECONF and HRESIZECONF */ -+ if (dss_has_feature(FEAT_RESIZECONF)) { -+ l &= ~(0x3 << 7); -+ l |= hscaleup ? 0 : (1 << 7); -+ l |= vscaleup ? 0 : (1 << 8); -+ } - -- l |= five_taps ? (1 << 21) : 0; -- l |= five_taps ? (1 << 22) : 0; -+ /* LINEBUFFERSPLIT */ -+ if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) { -+ l &= ~(0x1 << 22); -+ l |= five_taps ? (1 << 22) : 0; -+ } - - dispc_write_reg(dispc_reg_att[plane], l); - -@@ -1215,9 +1244,11 @@ - static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation, - bool mirroring, enum omap_color_mode color_mode) - { -+ bool row_repeat = false; -+ int vidrot = 0; -+ - if (color_mode == OMAP_DSS_COLOR_YUV2 || - color_mode == OMAP_DSS_COLOR_UYVY) { -- int vidrot = 0; - - if (mirroring) { - switch (rotation) { -@@ -1251,16 +1282,15 @@ - } - } - -- REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12); -- - if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270) -- REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18); -+ row_repeat = true; - else -- REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18); -- } else { -- REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12); -- REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18); -+ row_repeat = false; - } -+ -+ REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12); -+ if (dss_has_feature(FEAT_ROWREPEATENABLE)) -+ REG_FLD_MOD(dispc_reg_att[plane], row_repeat ? 1 : 0, 18, 18); - } - - static int color_mode_to_bpp(enum omap_color_mode color_mode) -@@ -2293,7 +2323,7 @@ - BUG_ON(pck_div < 2); - - enable_clocks(1); -- dispc_write_reg(DISPC_DIVISOR(channel), -+ dispc_write_reg(DISPC_DIVISORo(channel), - FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); - enable_clocks(0); - } -@@ -2302,7 +2332,7 @@ - int *pck_div) - { - u32 l; -- l = dispc_read_reg(DISPC_DIVISOR(channel)); -+ l = dispc_read_reg(DISPC_DIVISORo(channel)); - *lck_div = FLD_GET(l, 23, 16); - *pck_div = FLD_GET(l, 7, 0); - } -@@ -2311,14 +2341,17 @@ - { - unsigned long r = 0; - -- if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) -- r = dss_clk_get_rate(DSS_CLK_FCK1); -- else --#ifdef CONFIG_OMAP2_DSS_DSI -- r = dsi_get_dsi1_pll_rate(); --#else -- BUG(); --#endif -+ switch (dss_get_dispc_clk_source()) { -+ case DSS_CLK_SRC_FCK: -+ r = dss_clk_get_rate(DSS_CLK_FCK); -+ break; -+ case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: -+ r = dsi_get_pll_hsdiv_dispc_rate(); -+ break; -+ default: -+ BUG(); -+ } -+ - return r; - } - -@@ -2328,47 +2361,72 @@ - unsigned long r; - u32 l; - -- l = dispc_read_reg(DISPC_DIVISOR(channel)); -+ l = dispc_read_reg(DISPC_DIVISORo(channel)); - - lcd = FLD_GET(l, 23, 16); - -- r = dispc_fclk_rate(); -+ switch (dss_get_lcd_clk_source(channel)) { -+ case DSS_CLK_SRC_FCK: -+ r = dss_clk_get_rate(DSS_CLK_FCK); -+ break; -+ case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: -+ r = dsi_get_pll_hsdiv_dispc_rate(); -+ break; -+ default: -+ BUG(); -+ } - - return r / lcd; - } - - unsigned long dispc_pclk_rate(enum omap_channel channel) - { -- int lcd, pcd; -+ int pcd; - unsigned long r; - u32 l; - -- l = dispc_read_reg(DISPC_DIVISOR(channel)); -+ l = dispc_read_reg(DISPC_DIVISORo(channel)); - -- lcd = FLD_GET(l, 23, 16); - pcd = FLD_GET(l, 7, 0); - -- r = dispc_fclk_rate(); -+ r = dispc_lclk_rate(channel); - -- return r / lcd / pcd; -+ return r / pcd; - } - - void dispc_dump_clocks(struct seq_file *s) - { - int lcd, pcd; -+ u32 l; -+ enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); -+ enum dss_clk_source lcd_clk_src; - - enable_clocks(1); - - seq_printf(s, "- DISPC -\n"); - -- seq_printf(s, "dispc fclk source = %s\n", -- dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? -- "dss1_alwon_fclk" : "dsi1_pll_fclk"); -+ seq_printf(s, "dispc fclk source = %s (%s)\n", -+ dss_get_generic_clk_source_name(dispc_clk_src), -+ dss_feat_get_clk_source_name(dispc_clk_src)); - - seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); - -+ if (dss_has_feature(FEAT_CORE_CLK_DIV)) { -+ seq_printf(s, "- DISPC-CORE-CLK -\n"); -+ l = dispc_read_reg(DISPC_DIVISOR); -+ lcd = FLD_GET(l, 23, 16); -+ -+ seq_printf(s, "lck\t\t%-16lulck div\t%u\n", -+ (dispc_fclk_rate()/lcd), lcd); -+ } - seq_printf(s, "- LCD1 -\n"); - -+ lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD); -+ -+ seq_printf(s, "lcd1_clk source = %s (%s)\n", -+ dss_get_generic_clk_source_name(lcd_clk_src), -+ dss_feat_get_clk_source_name(lcd_clk_src)); -+ - dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd); - - seq_printf(s, "lck\t\t%-16lulck div\t%u\n", -@@ -2378,6 +2436,12 @@ - if (dss_has_feature(FEAT_MGR_LCD2)) { - seq_printf(s, "- LCD2 -\n"); - -+ lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2); -+ -+ seq_printf(s, "lcd2_clk source = %s (%s)\n", -+ dss_get_generic_clk_source_name(lcd_clk_src), -+ dss_feat_get_clk_source_name(lcd_clk_src)); -+ - dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd); - - seq_printf(s, "lck\t\t%-16lulck div\t%u\n", -@@ -2440,7 +2504,7 @@ - { - #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r)) - -- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); - - DUMPREG(DISPC_REVISION); - DUMPREG(DISPC_SYSCONFIG); -@@ -2459,7 +2523,7 @@ - DUMPREG(DISPC_TIMING_H(0)); - DUMPREG(DISPC_TIMING_V(0)); - DUMPREG(DISPC_POL_FREQ(0)); -- DUMPREG(DISPC_DIVISOR(0)); -+ DUMPREG(DISPC_DIVISORo(0)); - DUMPREG(DISPC_GLOBAL_ALPHA); - DUMPREG(DISPC_SIZE_DIG); - DUMPREG(DISPC_SIZE_LCD(0)); -@@ -2471,7 +2535,7 @@ - DUMPREG(DISPC_TIMING_H(2)); - DUMPREG(DISPC_TIMING_V(2)); - DUMPREG(DISPC_POL_FREQ(2)); -- DUMPREG(DISPC_DIVISOR(2)); -+ DUMPREG(DISPC_DIVISORo(2)); - DUMPREG(DISPC_SIZE_LCD(2)); - } - -@@ -2597,7 +2661,7 @@ - DUMPREG(DISPC_VID_PRELOAD(0)); - DUMPREG(DISPC_VID_PRELOAD(1)); - -- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); - #undef DUMPREG - } - -@@ -2713,8 +2777,8 @@ - - fck = dispc_fclk_rate(); - -- cinfo->lck_div = REG_GET(DISPC_DIVISOR(channel), 23, 16); -- cinfo->pck_div = REG_GET(DISPC_DIVISOR(channel), 7, 0); -+ cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); -+ cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0); - - cinfo->lck = fck / cinfo->lck_div; - cinfo->pck = cinfo->lck / cinfo->pck_div; -@@ -2791,6 +2855,9 @@ - break; - } - -+ if (ret) -+ goto err; -+ - _omap_dispc_set_irqs(); - - spin_unlock_irqrestore(&dispc.irq_lock, flags); -@@ -2866,10 +2933,10 @@ - * but we presume they are on because we got an IRQ. However, - * an irq handler may turn the clocks off, so we may not have - * clock later in the function. */ --void dispc_irq_handler(void) -+static irqreturn_t omap_dispc_irq_handler(int irq, void *arg) - { - int i; -- u32 irqstatus; -+ u32 irqstatus, irqenable; - u32 handledirqs = 0; - u32 unhandled_errors; - struct omap_dispc_isr_data *isr_data; -@@ -2878,6 +2945,13 @@ - spin_lock(&dispc.irq_lock); - - irqstatus = dispc_read_reg(DISPC_IRQSTATUS); -+ irqenable = dispc_read_reg(DISPC_IRQENABLE); -+ -+ /* IRQ is not for us */ -+ if (!(irqstatus & irqenable)) { -+ spin_unlock(&dispc.irq_lock); -+ return IRQ_NONE; -+ } - - #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS - spin_lock(&dispc.irq_stats_lock); -@@ -2929,6 +3003,8 @@ - } - - spin_unlock(&dispc.irq_lock); -+ -+ return IRQ_HANDLED; - } - - static void dispc_error_worker(struct work_struct *work) -@@ -3253,6 +3329,15 @@ - l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */ - dispc_write_reg(DISPC_SYSCONFIG, l); - -+ /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ -+ if (dss_has_feature(FEAT_CORE_CLK_DIV)) { -+ l = dispc_read_reg(DISPC_DIVISOR); -+ /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ -+ l = FLD_MOD(l, 1, 0, 0); -+ l = FLD_MOD(l, 1, 23, 16); -+ dispc_write_reg(DISPC_DIVISOR, l); -+ } -+ - /* FUNCGATED */ - if (dss_has_feature(FEAT_FUNCGATED)) - REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); -@@ -3269,47 +3354,6 @@ - dispc_read_plane_fifo_sizes(); - } - --int dispc_init(void) --{ -- u32 rev; -- -- spin_lock_init(&dispc.irq_lock); -- --#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS -- spin_lock_init(&dispc.irq_stats_lock); -- dispc.irq_stats.last_reset = jiffies; --#endif -- -- INIT_WORK(&dispc.error_work, dispc_error_worker); -- -- dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS); -- if (!dispc.base) { -- DSSERR("can't ioremap DISPC\n"); -- return -ENOMEM; -- } -- -- enable_clocks(1); -- -- _omap_dispc_initial_config(); -- -- _omap_dispc_initialize_irq(); -- -- dispc_save_context(); -- -- rev = dispc_read_reg(DISPC_REVISION); -- printk(KERN_INFO "OMAP DISPC rev %d.%d\n", -- FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); -- -- enable_clocks(0); -- -- return 0; --} -- --void dispc_exit(void) --{ -- iounmap(dispc.base); --} -- - int dispc_enable_plane(enum omap_plane plane, bool enable) - { - DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); -@@ -3359,3 +3403,94 @@ - - return r; - } -+ -+/* DISPC HW IP initialisation */ -+static int omap_dispchw_probe(struct platform_device *pdev) -+{ -+ u32 rev; -+ int r = 0; -+ struct resource *dispc_mem; -+ -+ dispc.pdev = pdev; -+ -+ spin_lock_init(&dispc.irq_lock); -+ -+#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS -+ spin_lock_init(&dispc.irq_stats_lock); -+ dispc.irq_stats.last_reset = jiffies; -+#endif -+ -+ INIT_WORK(&dispc.error_work, dispc_error_worker); -+ -+ dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); -+ if (!dispc_mem) { -+ DSSERR("can't get IORESOURCE_MEM DISPC\n"); -+ r = -EINVAL; -+ goto fail0; -+ } -+ dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem)); -+ if (!dispc.base) { -+ DSSERR("can't ioremap DISPC\n"); -+ r = -ENOMEM; -+ goto fail0; -+ } -+ dispc.irq = platform_get_irq(dispc.pdev, 0); -+ if (dispc.irq < 0) { -+ DSSERR("platform_get_irq failed\n"); -+ r = -ENODEV; -+ goto fail1; -+ } -+ -+ r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED, -+ "OMAP DISPC", dispc.pdev); -+ if (r < 0) { -+ DSSERR("request_irq failed\n"); -+ goto fail1; -+ } -+ -+ enable_clocks(1); -+ -+ _omap_dispc_initial_config(); -+ -+ _omap_dispc_initialize_irq(); -+ -+ dispc_save_context(); -+ -+ rev = dispc_read_reg(DISPC_REVISION); -+ dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", -+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); -+ -+ enable_clocks(0); -+ -+ return 0; -+fail1: -+ iounmap(dispc.base); -+fail0: -+ return r; -+} -+ -+static int omap_dispchw_remove(struct platform_device *pdev) -+{ -+ free_irq(dispc.irq, dispc.pdev); -+ iounmap(dispc.base); -+ return 0; -+} -+ -+static struct platform_driver omap_dispchw_driver = { -+ .probe = omap_dispchw_probe, -+ .remove = omap_dispchw_remove, -+ .driver = { -+ .name = "omapdss_dispc", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+int dispc_init_platform_driver(void) -+{ -+ return platform_driver_register(&omap_dispchw_driver); -+} -+ -+void dispc_uninit_platform_driver(void) -+{ -+ return platform_driver_unregister(&omap_dispchw_driver); -+} -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/display.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/display.c ---- linux-2.6.38-rc7/drivers/video/omap2/dss/display.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/display.c 2011-03-09 13:19:21.083278943 +0100 -@@ -25,14 +25,11 @@ - #include - #include - #include --#include - #include - - #include - #include "dss.h" - --static LIST_HEAD(display_list); -- - static ssize_t display_enabled_show(struct device *dev, - struct device_attribute *attr, char *buf) - { -@@ -396,29 +393,6 @@ - switch (dssdev->type) { - #ifdef CONFIG_OMAP2_DSS_DPI - case OMAP_DISPLAY_TYPE_DPI: --#endif --#ifdef CONFIG_OMAP2_DSS_RFBI -- case OMAP_DISPLAY_TYPE_DBI: --#endif --#ifdef CONFIG_OMAP2_DSS_SDI -- case OMAP_DISPLAY_TYPE_SDI: --#endif --#ifdef CONFIG_OMAP2_DSS_DSI -- case OMAP_DISPLAY_TYPE_DSI: --#endif --#ifdef CONFIG_OMAP2_DSS_VENC -- case OMAP_DISPLAY_TYPE_VENC: --#endif -- break; -- default: -- DSSERR("Support for display '%s' not compiled in.\n", -- dssdev->name); -- return; -- } -- -- switch (dssdev->type) { --#ifdef CONFIG_OMAP2_DSS_DPI -- case OMAP_DISPLAY_TYPE_DPI: - r = dpi_init_display(dssdev); - break; - #endif -@@ -443,7 +417,9 @@ - break; - #endif - default: -- BUG(); -+ DSSERR("Support for display '%s' not compiled in.\n", -+ dssdev->name); -+ return; - } - - if (r) { -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/dpi.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dpi.c ---- linux-2.6.38-rc7/drivers/video/omap2/dss/dpi.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dpi.c 2011-03-09 13:19:21.083278943 +0100 -@@ -57,13 +57,13 @@ - if (r) - return r; - -- dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK); -+ dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC); - - r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo); - if (r) - return r; - -- *fck = dsi_cinfo.dsi1_pll_fclk; -+ *fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk; - *lck_div = dispc_cinfo.lck_div; - *pck_div = dispc_cinfo.pck_div; - -@@ -107,7 +107,7 @@ - bool is_tft; - int r = 0; - -- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); - - dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config, - dssdev->panel.acbi, dssdev->panel.acb); -@@ -137,7 +137,7 @@ - dispc_set_lcd_timings(dssdev->manager->id, t); - - err0: -- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); - return r; - } - -@@ -173,14 +173,14 @@ - goto err1; - } - -- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); - - r = dpi_basic_init(dssdev); - if (r) - goto err2; - - #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL -- dss_clk_enable(DSS_CLK_FCK2); -+ dss_clk_enable(DSS_CLK_SYSCK); - r = dsi_pll_init(dssdev, 0, 1); - if (r) - goto err3; -@@ -199,10 +199,10 @@ - #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL - dsi_pll_uninit(); - err3: -- dss_clk_disable(DSS_CLK_FCK2); -+ dss_clk_disable(DSS_CLK_SYSCK); - #endif - err2: -- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); - if (cpu_is_omap34xx()) - regulator_disable(dpi.vdds_dsi_reg); - err1: -@@ -217,12 +217,12 @@ - dssdev->manager->disable(dssdev->manager); - - #ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL -- dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); -+ dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); - dsi_pll_uninit(); -- dss_clk_disable(DSS_CLK_FCK2); -+ dss_clk_disable(DSS_CLK_SYSCK); - #endif - -- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); - - if (cpu_is_omap34xx()) - regulator_disable(dpi.vdds_dsi_reg); -@@ -271,7 +271,7 @@ - if (r) - return r; - -- fck = dsi_cinfo.dsi1_pll_fclk; -+ fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk; - lck_div = dispc_cinfo.lck_div; - pck_div = dispc_cinfo.pck_div; - } -@@ -303,22 +303,27 @@ - { - DSSDBG("init_display\n"); - -- return 0; --} -+ if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) { -+ struct regulator *vdds_dsi; - --int dpi_init(struct platform_device *pdev) --{ -- if (cpu_is_omap34xx()) { -- dpi.vdds_dsi_reg = dss_get_vdds_dsi(); -- if (IS_ERR(dpi.vdds_dsi_reg)) { -+ vdds_dsi = dss_get_vdds_dsi(); -+ -+ if (IS_ERR(vdds_dsi)) { - DSSERR("can't get VDDS_DSI regulator\n"); -- return PTR_ERR(dpi.vdds_dsi_reg); -+ return PTR_ERR(vdds_dsi); - } -+ -+ dpi.vdds_dsi_reg = vdds_dsi; - } - - return 0; - } - -+int dpi_init(void) -+{ -+ return 0; -+} -+ - void dpi_exit(void) - { - } -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/dsi.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dsi.c ---- linux-2.6.38-rc7/drivers/video/omap2/dss/dsi.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dsi.c 2011-03-09 13:19:21.084278923 +0100 -@@ -38,12 +38,11 @@ - #include - - #include "dss.h" -+#include "dss_features.h" - - /*#define VERBOSE_IRQ*/ - #define DSI_CATCH_MISSING_TE - --#define DSI_BASE 0x4804FC00 -- - struct dsi_reg { u16 idx; }; - - #define DSI_REG(idx) ((const struct dsi_reg) { idx }) -@@ -190,8 +189,8 @@ - #define FINT_MIN 750000 - #define REGN_MAX (1 << 7) - #define REGM_MAX ((1 << 11) - 1) --#define REGM3_MAX (1 << 4) --#define REGM4_MAX (1 << 4) -+#define REGM_DISPC_MAX (1 << 4) -+#define REGM_DSI_MAX (1 << 4) - #define LP_DIV_MAX ((1 << 13) - 1) - - enum fifo_size { -@@ -222,7 +221,9 @@ - - static struct - { -+ struct platform_device *pdev; - void __iomem *base; -+ int irq; - - struct dsi_clock_info current_cinfo; - -@@ -232,6 +233,7 @@ - enum dsi_vc_mode mode; - struct omap_dss_device *dssdev; - enum fifo_size fifo_size; -+ int vc_id; - } vc[4]; - - struct mutex lock; -@@ -481,13 +483,17 @@ - static int debug_irq; - - /* called from dss */ --void dsi_irq_handler(void) -+static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) - { - u32 irqstatus, vcstatus, ciostatus; - int i; - - irqstatus = dsi_read_reg(DSI_IRQSTATUS); - -+ /* IRQ is not for us */ -+ if (!irqstatus) -+ return IRQ_NONE; -+ - #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS - spin_lock(&dsi.irq_stats_lock); - dsi.irq_stats.irq_count++; -@@ -565,9 +571,9 @@ - #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS - spin_unlock(&dsi.irq_stats_lock); - #endif -+ return IRQ_HANDLED; - } - -- - static void _dsi_initialize_irq(void) - { - u32 l; -@@ -637,22 +643,22 @@ - dsi_write_reg(DSI_VC_IRQENABLE(channel), l); - } - --/* DSI func clock. this could also be DSI2_PLL_FCLK */ -+/* DSI func clock. this could also be dsi_pll_hsdiv_dsi_clk */ - static inline void enable_clocks(bool enable) - { - if (enable) -- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); - else -- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); - } - - /* source clock for DSI PLL. this could also be PCLKFREE */ - static inline void dsi_enable_pll_clock(bool enable) - { - if (enable) -- dss_clk_enable(DSS_CLK_FCK2); -+ dss_clk_enable(DSS_CLK_SYSCK); - else -- dss_clk_disable(DSS_CLK_FCK2); -+ dss_clk_disable(DSS_CLK_SYSCK); - - if (enable && dsi.pll_locked) { - if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) -@@ -707,14 +713,14 @@ - return 0; - } - --unsigned long dsi_get_dsi1_pll_rate(void) -+unsigned long dsi_get_pll_hsdiv_dispc_rate(void) - { -- return dsi.current_cinfo.dsi1_pll_fclk; -+ return dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk; - } - --static unsigned long dsi_get_dsi2_pll_rate(void) -+static unsigned long dsi_get_pll_hsdiv_dsi_rate(void) - { -- return dsi.current_cinfo.dsi2_pll_fclk; -+ return dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk; - } - - static unsigned long dsi_get_txbyteclkhs(void) -@@ -726,12 +732,12 @@ - { - unsigned long r; - -- if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) { -- /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */ -- r = dss_clk_get_rate(DSS_CLK_FCK1); -+ if (dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK) { -+ /* DSI FCLK source is DSS_CLK_FCK */ -+ r = dss_clk_get_rate(DSS_CLK_FCK); - } else { -- /* DSI FCLK source is DSI2_PLL_FCLK */ -- r = dsi_get_dsi2_pll_rate(); -+ /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ -+ r = dsi_get_pll_hsdiv_dsi_rate(); - } - - return r; -@@ -801,16 +807,16 @@ - if (cinfo->regm == 0 || cinfo->regm > REGM_MAX) - return -EINVAL; - -- if (cinfo->regm3 > REGM3_MAX) -+ if (cinfo->regm_dispc > REGM_DISPC_MAX) - return -EINVAL; - -- if (cinfo->regm4 > REGM4_MAX) -+ if (cinfo->regm_dsi > REGM_DSI_MAX) - return -EINVAL; - -- if (cinfo->use_dss2_fck) { -- cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2); -+ if (cinfo->use_sys_clk) { -+ cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK); - /* XXX it is unclear if highfreq should be used -- * with DSS2_FCK source also */ -+ * with DSS_SYS_CLK source also */ - cinfo->highfreq = 0; - } else { - cinfo->clkin = dispc_pclk_rate(dssdev->manager->id); -@@ -831,15 +837,17 @@ - if (cinfo->clkin4ddr > 1800 * 1000 * 1000) - return -EINVAL; - -- if (cinfo->regm3 > 0) -- cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3; -+ if (cinfo->regm_dispc > 0) -+ cinfo->dsi_pll_hsdiv_dispc_clk = -+ cinfo->clkin4ddr / cinfo->regm_dispc; - else -- cinfo->dsi1_pll_fclk = 0; -+ cinfo->dsi_pll_hsdiv_dispc_clk = 0; - -- if (cinfo->regm4 > 0) -- cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4; -+ if (cinfo->regm_dsi > 0) -+ cinfo->dsi_pll_hsdiv_dsi_clk = -+ cinfo->clkin4ddr / cinfo->regm_dsi; - else -- cinfo->dsi2_pll_fclk = 0; -+ cinfo->dsi_pll_hsdiv_dsi_clk = 0; - - return 0; - } -@@ -852,23 +860,25 @@ - struct dispc_clock_info best_dispc; - int min_fck_per_pck; - int match = 0; -- unsigned long dss_clk_fck2; -+ unsigned long dss_sys_clk, max_dss_fck; - -- dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2); -+ dss_sys_clk = dss_clk_get_rate(DSS_CLK_SYSCK); -+ -+ max_dss_fck = dss_feat_get_max_dss_fck(); - - if (req_pck == dsi.cache_req_pck && -- dsi.cache_cinfo.clkin == dss_clk_fck2) { -+ dsi.cache_cinfo.clkin == dss_sys_clk) { - DSSDBG("DSI clock info found from cache\n"); - *dsi_cinfo = dsi.cache_cinfo; -- dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk, -- dispc_cinfo); -+ dispc_find_clk_divs(is_tft, req_pck, -+ dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo); - return 0; - } - - min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; - - if (min_fck_per_pck && -- req_pck * min_fck_per_pck > DISPC_MAX_FCK) { -+ req_pck * min_fck_per_pck > max_dss_fck) { - DSSERR("Requested pixel clock not possible with the current " - "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " - "the constraint off.\n"); -@@ -882,8 +892,8 @@ - memset(&best_dispc, 0, sizeof(best_dispc)); - - memset(&cur, 0, sizeof(cur)); -- cur.clkin = dss_clk_fck2; -- cur.use_dss2_fck = 1; -+ cur.clkin = dss_sys_clk; -+ cur.use_sys_clk = 1; - cur.highfreq = 0; - - /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ -@@ -909,30 +919,32 @@ - if (cur.clkin4ddr > 1800 * 1000 * 1000) - break; - -- /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */ -- for (cur.regm3 = 1; cur.regm3 < REGM3_MAX; -- ++cur.regm3) { -+ /* dsi_pll_hsdiv_dispc_clk(MHz) = -+ * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */ -+ for (cur.regm_dispc = 1; cur.regm_dispc < REGM_DISPC_MAX; -+ ++cur.regm_dispc) { - struct dispc_clock_info cur_dispc; -- cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3; -+ cur.dsi_pll_hsdiv_dispc_clk = -+ cur.clkin4ddr / cur.regm_dispc; - - /* this will narrow down the search a bit, - * but still give pixclocks below what was - * requested */ -- if (cur.dsi1_pll_fclk < req_pck) -+ if (cur.dsi_pll_hsdiv_dispc_clk < req_pck) - break; - -- if (cur.dsi1_pll_fclk > DISPC_MAX_FCK) -+ if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck) - continue; - - if (min_fck_per_pck && -- cur.dsi1_pll_fclk < -+ cur.dsi_pll_hsdiv_dispc_clk < - req_pck * min_fck_per_pck) - continue; - - match = 1; - - dispc_find_clk_divs(is_tft, req_pck, -- cur.dsi1_pll_fclk, -+ cur.dsi_pll_hsdiv_dispc_clk, - &cur_dispc); - - if (abs(cur_dispc.pck - req_pck) < -@@ -961,9 +973,9 @@ - return -EINVAL; - } - -- /* DSI2_PLL_FCLK (regm4) is not used */ -- best.regm4 = 0; -- best.dsi2_pll_fclk = 0; -+ /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */ -+ best.regm_dsi = 0; -+ best.dsi_pll_hsdiv_dsi_clk = 0; - - if (dsi_cinfo) - *dsi_cinfo = best; -@@ -987,18 +999,20 @@ - - dsi.current_cinfo.fint = cinfo->fint; - dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr; -- dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk; -- dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk; -+ dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk = -+ cinfo->dsi_pll_hsdiv_dispc_clk; -+ dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk = -+ cinfo->dsi_pll_hsdiv_dsi_clk; - - dsi.current_cinfo.regn = cinfo->regn; - dsi.current_cinfo.regm = cinfo->regm; -- dsi.current_cinfo.regm3 = cinfo->regm3; -- dsi.current_cinfo.regm4 = cinfo->regm4; -+ dsi.current_cinfo.regm_dispc = cinfo->regm_dispc; -+ dsi.current_cinfo.regm_dsi = cinfo->regm_dsi; - - DSSDBG("DSI Fint %ld\n", cinfo->fint); - - DSSDBG("clkin (%s) rate %ld, highfreq %d\n", -- cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree", -+ cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree", - cinfo->clkin, - cinfo->highfreq); - -@@ -1015,10 +1029,14 @@ - - DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); - -- DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n", -- cinfo->regm3, cinfo->dsi1_pll_fclk); -- DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n", -- cinfo->regm4, cinfo->dsi2_pll_fclk); -+ DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc, -+ dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), -+ dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), -+ cinfo->dsi_pll_hsdiv_dispc_clk); -+ DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi, -+ dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), -+ dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), -+ cinfo->dsi_pll_hsdiv_dsi_clk); - - REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ - -@@ -1026,9 +1044,9 @@ - l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ - l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */ - l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */ -- l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0, -+ l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0, - 22, 19); /* DSI_CLOCK_DIV */ -- l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0, -+ l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0, - 26, 23); /* DSIPROTO_CLOCK_DIV */ - dsi_write_reg(DSI_PLL_CONFIGURATION1, l); - -@@ -1046,7 +1064,7 @@ - - l = dsi_read_reg(DSI_PLL_CONFIGURATION2); - l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ -- l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1, -+ l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1, - 11, 11); /* DSI_PLL_CLKSEL */ - l = FLD_MOD(l, cinfo->highfreq, - 12, 12); /* DSI_PLL_HIGHFREQ */ -@@ -1101,6 +1119,26 @@ - - DSSDBG("PLL init\n"); - -+#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL -+ /* -+ * HACK: this is just a quick hack to get the USE_DSI_PLL -+ * option working. USE_DSI_PLL is itself a big hack, and -+ * should be removed. -+ */ -+ if (dsi.vdds_dsi_reg == NULL) { -+ struct regulator *vdds_dsi; -+ -+ vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi"); -+ -+ if (IS_ERR(vdds_dsi)) { -+ DSSERR("can't get VDDS_DSI regulator\n"); -+ return PTR_ERR(vdds_dsi); -+ } -+ -+ dsi.vdds_dsi_reg = vdds_dsi; -+ } -+#endif -+ - enable_clocks(1); - dsi_enable_pll_clock(1); - -@@ -1162,6 +1200,10 @@ - { - int clksel; - struct dsi_clock_info *cinfo = &dsi.current_cinfo; -+ enum dss_clk_source dispc_clk_src, dsi_clk_src; -+ -+ dispc_clk_src = dss_get_dispc_clk_source(); -+ dsi_clk_src = dss_get_dsi_clk_source(); - - enable_clocks(1); - -@@ -1171,30 +1213,34 @@ - - seq_printf(s, "dsi pll source = %s\n", - clksel == 0 ? -- "dss2_alwon_fclk" : "pclkfree"); -+ "dss_sys_clk" : "pclkfree"); - - seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn); - - seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", - cinfo->clkin4ddr, cinfo->regm); - -- seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n", -- cinfo->dsi1_pll_fclk, -- cinfo->regm3, -- dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? -+ seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n", -+ dss_get_generic_clk_source_name(dispc_clk_src), -+ dss_feat_get_clk_source_name(dispc_clk_src), -+ cinfo->dsi_pll_hsdiv_dispc_clk, -+ cinfo->regm_dispc, -+ dispc_clk_src == DSS_CLK_SRC_FCK ? - "off" : "on"); - -- seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n", -- cinfo->dsi2_pll_fclk, -- cinfo->regm4, -- dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? -+ seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n", -+ dss_get_generic_clk_source_name(dsi_clk_src), -+ dss_feat_get_clk_source_name(dsi_clk_src), -+ cinfo->dsi_pll_hsdiv_dsi_clk, -+ cinfo->regm_dsi, -+ dsi_clk_src == DSS_CLK_SRC_FCK ? - "off" : "on"); - - seq_printf(s, "- DSI -\n"); - -- seq_printf(s, "dsi fclk source = %s\n", -- dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ? -- "dss1_alwon_fclk" : "dsi2_pll_fclk"); -+ seq_printf(s, "dsi fclk source = %s (%s)\n", -+ dss_get_generic_clk_source_name(dsi_clk_src), -+ dss_feat_get_clk_source_name(dsi_clk_src)); - - seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate()); - -@@ -1306,7 +1352,7 @@ - { - #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r)) - -- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); - - DUMPREG(DSI_REVISION); - DUMPREG(DSI_SYSCONFIG); -@@ -1378,7 +1424,7 @@ - DUMPREG(DSI_PLL_CONFIGURATION1); - DUMPREG(DSI_PLL_CONFIGURATION2); - -- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); - #undef DUMPREG - } - -@@ -1622,20 +1668,6 @@ - return _dsi_wait_reset(); - } - --static void dsi_reset_tx_fifo(int channel) --{ -- u32 mask; -- u32 l; -- -- /* set fifosize of the channel to 0, then return the old size */ -- l = dsi_read_reg(DSI_TX_FIFO_VC_SIZE); -- -- mask = FLD_MASK((8 * channel) + 7, (8 * channel) + 4); -- dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l & ~mask); -- -- dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l); --} -- - static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2, - enum fifo_size size3, enum fifo_size size4) - { -@@ -1753,8 +1785,6 @@ - r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ - - dsi_write_reg(DSI_VC_CTRL(channel), r); -- -- dsi.vc[channel].mode = DSI_VC_MODE_L4; - } - - static int dsi_vc_config_l4(int channel) -@@ -1961,7 +1991,7 @@ - - WARN_ON(!dsi_bus_is_locked()); - -- data_id = data_type | channel << 6; -+ data_id = data_type | dsi.vc[channel].vc_id << 6; - - val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | - FLD_VAL(ecc, 31, 24); -@@ -2064,7 +2094,7 @@ - return -EINVAL; - } - -- data_id = data_type | channel << 6; -+ data_id = data_type | dsi.vc[channel].vc_id << 6; - - r = (data_id << 0) | (data << 8) | (ecc << 24); - -@@ -2984,12 +3014,12 @@ - struct dsi_clock_info cinfo; - int r; - -- /* we always use DSS2_FCK as input clock */ -- cinfo.use_dss2_fck = true; -+ /* we always use DSS_CLK_SYSCK as input clock */ -+ cinfo.use_sys_clk = true; - cinfo.regn = dssdev->phy.dsi.div.regn; - cinfo.regm = dssdev->phy.dsi.div.regm; -- cinfo.regm3 = dssdev->phy.dsi.div.regm3; -- cinfo.regm4 = dssdev->phy.dsi.div.regm4; -+ cinfo.regm_dispc = dssdev->phy.dsi.div.regm_dispc; -+ cinfo.regm_dsi = dssdev->phy.dsi.div.regm_dsi; - r = dsi_calc_clock_rates(dssdev, &cinfo); - if (r) { - DSSERR("Failed to calc dsi clocks\n"); -@@ -3011,7 +3041,7 @@ - int r; - unsigned long long fck; - -- fck = dsi_get_dsi1_pll_rate(); -+ fck = dsi_get_pll_hsdiv_dispc_rate(); - - dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div; - dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div; -@@ -3045,8 +3075,8 @@ - if (r) - goto err1; - -- dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK); -- dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK); -+ dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC); -+ dss_select_dsi_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI); - - DSSDBG("PLL OK\n"); - -@@ -3082,8 +3112,8 @@ - err3: - dsi_complexio_uninit(); - err2: -- dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); -- dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK); -+ dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); -+ dss_select_dsi_clk_source(DSS_CLK_SRC_FCK); - err1: - dsi_pll_uninit(); - err0: -@@ -3099,8 +3129,8 @@ - dsi_vc_enable(2, 0); - dsi_vc_enable(3, 0); - -- dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK); -- dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK); -+ dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); -+ dss_select_dsi_clk_source(DSS_CLK_SRC_FCK); - dsi_complexio_uninit(); - dsi_pll_uninit(); - } -@@ -3220,28 +3250,94 @@ - dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE | - OMAP_DSS_DISPLAY_CAP_TEAR_ELIM; - -- dsi.vc[0].dssdev = dssdev; -- dsi.vc[1].dssdev = dssdev; -+ if (dsi.vdds_dsi_reg == NULL) { -+ struct regulator *vdds_dsi; -+ -+ vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi"); -+ -+ if (IS_ERR(vdds_dsi)) { -+ DSSERR("can't get VDDS_DSI regulator\n"); -+ return PTR_ERR(vdds_dsi); -+ } -+ -+ dsi.vdds_dsi_reg = vdds_dsi; -+ } -+ -+ return 0; -+} -+ -+int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) { -+ if (!dsi.vc[i].dssdev) { -+ dsi.vc[i].dssdev = dssdev; -+ *channel = i; -+ return 0; -+ } -+ } -+ -+ DSSERR("cannot get VC for display %s", dssdev->name); -+ return -ENOSPC; -+} -+EXPORT_SYMBOL(omap_dsi_request_vc); -+ -+int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) -+{ -+ if (vc_id < 0 || vc_id > 3) { -+ DSSERR("VC ID out of range\n"); -+ return -EINVAL; -+ } -+ -+ if (channel < 0 || channel > 3) { -+ DSSERR("Virtual Channel out of range\n"); -+ return -EINVAL; -+ } -+ -+ if (dsi.vc[channel].dssdev != dssdev) { -+ DSSERR("Virtual Channel not allocated to display %s\n", -+ dssdev->name); -+ return -EINVAL; -+ } -+ -+ dsi.vc[channel].vc_id = vc_id; - - return 0; - } -+EXPORT_SYMBOL(omap_dsi_set_vc_id); - --void dsi_wait_dsi1_pll_active(void) -+void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel) -+{ -+ if ((channel >= 0 && channel <= 3) && -+ dsi.vc[channel].dssdev == dssdev) { -+ dsi.vc[channel].dssdev = NULL; -+ dsi.vc[channel].vc_id = 0; -+ } -+} -+EXPORT_SYMBOL(omap_dsi_release_vc); -+ -+void dsi_wait_pll_hsdiv_dispc_active(void) - { - if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1) -- DSSERR("DSI1 PLL clock not active\n"); -+ DSSERR("%s (%s) not active\n", -+ dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), -+ dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)); - } - --void dsi_wait_dsi2_pll_active(void) -+void dsi_wait_pll_hsdiv_dsi_active(void) - { - if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1) -- DSSERR("DSI2 PLL clock not active\n"); -+ DSSERR("%s (%s) not active\n", -+ dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), -+ dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)); - } - --int dsi_init(struct platform_device *pdev) -+static int dsi_init(struct platform_device *pdev) - { - u32 rev; -- int r; -+ int r, i; -+ struct resource *dsi_mem; - - spin_lock_init(&dsi.errors_lock); - dsi.errors = 0; -@@ -3268,24 +3364,43 @@ - dsi.te_timer.function = dsi_te_timeout; - dsi.te_timer.data = 0; - #endif -- dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS); -+ dsi_mem = platform_get_resource(dsi.pdev, IORESOURCE_MEM, 0); -+ if (!dsi_mem) { -+ DSSERR("can't get IORESOURCE_MEM DSI\n"); -+ r = -EINVAL; -+ goto err1; -+ } -+ dsi.base = ioremap(dsi_mem->start, resource_size(dsi_mem)); - if (!dsi.base) { - DSSERR("can't ioremap DSI\n"); - r = -ENOMEM; - goto err1; - } -+ dsi.irq = platform_get_irq(dsi.pdev, 0); -+ if (dsi.irq < 0) { -+ DSSERR("platform_get_irq failed\n"); -+ r = -ENODEV; -+ goto err2; -+ } - -- dsi.vdds_dsi_reg = dss_get_vdds_dsi(); -- if (IS_ERR(dsi.vdds_dsi_reg)) { -- DSSERR("can't get VDDS_DSI regulator\n"); -- r = PTR_ERR(dsi.vdds_dsi_reg); -+ r = request_irq(dsi.irq, omap_dsi_irq_handler, IRQF_SHARED, -+ "OMAP DSI1", dsi.pdev); -+ if (r < 0) { -+ DSSERR("request_irq failed\n"); - goto err2; - } - -+ /* DSI VCs initialization */ -+ for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) { -+ dsi.vc[i].mode = DSI_VC_MODE_L4; -+ dsi.vc[i].dssdev = NULL; -+ dsi.vc[i].vc_id = 0; -+ } -+ - enable_clocks(1); - - rev = dsi_read_reg(DSI_REVISION); -- printk(KERN_INFO "OMAP DSI rev %d.%d\n", -+ dev_dbg(&pdev->dev, "OMAP DSI rev %d.%d\n", - FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); - - enable_clocks(0); -@@ -3298,8 +3413,14 @@ - return r; - } - --void dsi_exit(void) -+static void dsi_exit(void) - { -+ if (dsi.vdds_dsi_reg != NULL) { -+ regulator_put(dsi.vdds_dsi_reg); -+ dsi.vdds_dsi_reg = NULL; -+ } -+ -+ free_irq(dsi.irq, dsi.pdev); - iounmap(dsi.base); - - destroy_workqueue(dsi.workqueue); -@@ -3307,3 +3428,41 @@ - DSSDBG("omap_dsi_exit\n"); - } - -+/* DSI1 HW IP initialisation */ -+static int omap_dsi1hw_probe(struct platform_device *pdev) -+{ -+ int r; -+ dsi.pdev = pdev; -+ r = dsi_init(pdev); -+ if (r) { -+ DSSERR("Failed to initialize DSI\n"); -+ goto err_dsi; -+ } -+err_dsi: -+ return r; -+} -+ -+static int omap_dsi1hw_remove(struct platform_device *pdev) -+{ -+ dsi_exit(); -+ return 0; -+} -+ -+static struct platform_driver omap_dsi1hw_driver = { -+ .probe = omap_dsi1hw_probe, -+ .remove = omap_dsi1hw_remove, -+ .driver = { -+ .name = "omapdss_dsi1", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+int dsi_init_platform_driver(void) -+{ -+ return platform_driver_register(&omap_dsi1hw_driver); -+} -+ -+void dsi_uninit_platform_driver(void) -+{ -+ return platform_driver_unregister(&omap_dsi1hw_driver); -+} -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/dss.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dss.c ---- linux-2.6.38-rc7/drivers/video/omap2/dss/dss.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dss.c 2011-03-09 13:19:21.085278903 +0100 -@@ -26,14 +26,13 @@ - #include - #include - #include --#include - #include - #include - - #include -+#include - #include "dss.h" -- --#define DSS_BASE 0x48050000 -+#include "dss_features.h" - - #define DSS_SZ_REGS SZ_512 - -@@ -59,9 +58,17 @@ - dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) - - static struct { -+ struct platform_device *pdev; - void __iomem *base; -+ int ctx_id; - - struct clk *dpll4_m4_ck; -+ struct clk *dss_ick; -+ struct clk *dss_fck; -+ struct clk *dss_sys_clk; -+ struct clk *dss_tv_fck; -+ struct clk *dss_video_fck; -+ unsigned num_clks_enabled; - - unsigned long cache_req_pck; - unsigned long cache_prate; -@@ -70,10 +77,22 @@ - - enum dss_clk_source dsi_clk_source; - enum dss_clk_source dispc_clk_source; -+ enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; - - u32 ctx[DSS_SZ_REGS / sizeof(u32)]; - } dss; - -+static const struct dss_clk_source_name dss_generic_clk_source_names[] = { -+ { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI_PLL_HSDIV_DISPC" }, -+ { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI_PLL_HSDIV_DSI" }, -+ { DSS_CLK_SRC_FCK, "DSS_FCK" }, -+}; -+ -+static void dss_clk_enable_all_no_ctx(void); -+static void dss_clk_disable_all_no_ctx(void); -+static void dss_clk_enable_no_ctx(enum dss_clock clks); -+static void dss_clk_disable_no_ctx(enum dss_clock clks); -+ - static int _omap_dss_wait_reset(void); - - static inline void dss_write_reg(const struct dss_reg idx, u32 val) -@@ -99,10 +118,11 @@ - SR(SYSCONFIG); - SR(CONTROL); - --#ifdef CONFIG_OMAP2_DSS_SDI -- SR(SDI_CONTROL); -- SR(PLL_CONTROL); --#endif -+ if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & -+ OMAP_DISPLAY_TYPE_SDI) { -+ SR(SDI_CONTROL); -+ SR(PLL_CONTROL); -+ } - } - - void dss_restore_context(void) -@@ -113,10 +133,11 @@ - RR(SYSCONFIG); - RR(CONTROL); - --#ifdef CONFIG_OMAP2_DSS_SDI -- RR(SDI_CONTROL); -- RR(PLL_CONTROL); --#endif -+ if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & -+ OMAP_DISPLAY_TYPE_SDI) { -+ RR(SDI_CONTROL); -+ RR(PLL_CONTROL); -+ } - } - - #undef SR -@@ -209,12 +230,17 @@ - REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ - } - -+const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src) -+{ -+ return dss_generic_clk_source_names[clk_src].clksrc_name; -+} -+ - void dss_dump_clocks(struct seq_file *s) - { - unsigned long dpll4_ck_rate; - unsigned long dpll4_m4_ck_rate; - -- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); - - dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck)); - dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck); -@@ -224,51 +250,66 @@ - seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate); - - if (cpu_is_omap3630()) -- seq_printf(s, "dss1_alwon_fclk = %lu / %lu = %lu\n", -+ seq_printf(s, "%s (%s) = %lu / %lu = %lu\n", -+ dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK), -+ dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK), - dpll4_ck_rate, - dpll4_ck_rate / dpll4_m4_ck_rate, -- dss_clk_get_rate(DSS_CLK_FCK1)); -+ dss_clk_get_rate(DSS_CLK_FCK)); - else -- seq_printf(s, "dss1_alwon_fclk = %lu / %lu * 2 = %lu\n", -+ seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n", -+ dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK), -+ dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK), - dpll4_ck_rate, - dpll4_ck_rate / dpll4_m4_ck_rate, -- dss_clk_get_rate(DSS_CLK_FCK1)); -+ dss_clk_get_rate(DSS_CLK_FCK)); - -- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); - } - - void dss_dump_regs(struct seq_file *s) - { - #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) - -- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); - - DUMPREG(DSS_REVISION); - DUMPREG(DSS_SYSCONFIG); - DUMPREG(DSS_SYSSTATUS); - DUMPREG(DSS_IRQSTATUS); - DUMPREG(DSS_CONTROL); -- DUMPREG(DSS_SDI_CONTROL); -- DUMPREG(DSS_PLL_CONTROL); -- DUMPREG(DSS_SDI_STATUS); - -- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) & -+ OMAP_DISPLAY_TYPE_SDI) { -+ DUMPREG(DSS_SDI_CONTROL); -+ DUMPREG(DSS_PLL_CONTROL); -+ DUMPREG(DSS_SDI_STATUS); -+ } -+ -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); - #undef DUMPREG - } - - void dss_select_dispc_clk_source(enum dss_clk_source clk_src) - { - int b; -+ u8 start, end; - -- BUG_ON(clk_src != DSS_SRC_DSI1_PLL_FCLK && -- clk_src != DSS_SRC_DSS1_ALWON_FCLK); -- -- b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1; -+ switch (clk_src) { -+ case DSS_CLK_SRC_FCK: -+ b = 0; -+ break; -+ case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: -+ b = 1; -+ dsi_wait_pll_hsdiv_dispc_active(); -+ break; -+ default: -+ BUG(); -+ } - -- if (clk_src == DSS_SRC_DSI1_PLL_FCLK) -- dsi_wait_dsi1_pll_active(); -+ dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end); - -- REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */ -+ REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ - - dss.dispc_clk_source = clk_src; - } -@@ -277,19 +318,51 @@ - { - int b; - -- BUG_ON(clk_src != DSS_SRC_DSI2_PLL_FCLK && -- clk_src != DSS_SRC_DSS1_ALWON_FCLK); -- -- b = clk_src == DSS_SRC_DSS1_ALWON_FCLK ? 0 : 1; -- -- if (clk_src == DSS_SRC_DSI2_PLL_FCLK) -- dsi_wait_dsi2_pll_active(); -+ switch (clk_src) { -+ case DSS_CLK_SRC_FCK: -+ b = 0; -+ break; -+ case DSS_CLK_SRC_DSI_PLL_HSDIV_DSI: -+ b = 1; -+ dsi_wait_pll_hsdiv_dsi_active(); -+ break; -+ default: -+ BUG(); -+ } - - REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */ - - dss.dsi_clk_source = clk_src; - } - -+void dss_select_lcd_clk_source(enum omap_channel channel, -+ enum dss_clk_source clk_src) -+{ -+ int b, ix, pos; -+ -+ if (!dss_has_feature(FEAT_LCD_CLK_SRC)) -+ return; -+ -+ switch (clk_src) { -+ case DSS_CLK_SRC_FCK: -+ b = 0; -+ break; -+ case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: -+ BUG_ON(channel != OMAP_DSS_CHANNEL_LCD); -+ b = 1; -+ dsi_wait_pll_hsdiv_dispc_active(); -+ break; -+ default: -+ BUG(); -+ } -+ -+ pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12; -+ REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ -+ -+ ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1; -+ dss.lcd_clk_source[ix] = clk_src; -+} -+ - enum dss_clk_source dss_get_dispc_clk_source(void) - { - return dss.dispc_clk_source; -@@ -300,6 +373,12 @@ - return dss.dsi_clk_source; - } - -+enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) -+{ -+ int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1; -+ return dss.lcd_clk_source[ix]; -+} -+ - /* calculate clock rates using dividers in cinfo */ - int dss_calc_clock_rates(struct dss_clock_info *cinfo) - { -@@ -337,7 +416,7 @@ - - int dss_get_clock_div(struct dss_clock_info *cinfo) - { -- cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK1); -+ cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK); - - if (cpu_is_omap34xx()) { - unsigned long prate; -@@ -369,7 +448,7 @@ - struct dss_clock_info best_dss; - struct dispc_clock_info best_dispc; - -- unsigned long fck; -+ unsigned long fck, max_dss_fck; - - u16 fck_div; - -@@ -378,7 +457,9 @@ - - prate = dss_get_dpll4_rate(); - -- fck = dss_clk_get_rate(DSS_CLK_FCK1); -+ max_dss_fck = dss_feat_get_max_dss_fck(); -+ -+ fck = dss_clk_get_rate(DSS_CLK_FCK); - if (req_pck == dss.cache_req_pck && - ((cpu_is_omap34xx() && prate == dss.cache_prate) || - dss.cache_dss_cinfo.fck == fck)) { -@@ -391,7 +472,7 @@ - min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; - - if (min_fck_per_pck && -- req_pck * min_fck_per_pck > DISPC_MAX_FCK) { -+ req_pck * min_fck_per_pck > max_dss_fck) { - DSSERR("Requested pixel clock not possible with the current " - "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " - "the constraint off.\n"); -@@ -405,7 +486,7 @@ - if (cpu_is_omap24xx()) { - struct dispc_clock_info cur_dispc; - /* XXX can we change the clock on omap2? */ -- fck = dss_clk_get_rate(DSS_CLK_FCK1); -+ fck = dss_clk_get_rate(DSS_CLK_FCK); - fck_div = 1; - - dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc); -@@ -427,7 +508,7 @@ - else - fck = prate / fck_div * 2; - -- if (fck > DISPC_MAX_FCK) -+ if (fck > max_dss_fck) - continue; - - if (min_fck_per_pck && -@@ -482,31 +563,6 @@ - return 0; - } - -- -- --static irqreturn_t dss_irq_handler_omap2(int irq, void *arg) --{ -- dispc_irq_handler(); -- -- return IRQ_HANDLED; --} -- --static irqreturn_t dss_irq_handler_omap3(int irq, void *arg) --{ -- u32 irqstatus; -- -- irqstatus = dss_read_reg(DSS_IRQSTATUS); -- -- if (irqstatus & (1<<0)) /* DISPC_IRQ */ -- dispc_irq_handler(); --#ifdef CONFIG_OMAP2_DSS_DSI -- if (irqstatus & (1<<1)) /* DSI_IRQ */ -- dsi_irq_handler(); --#endif -- -- return IRQ_HANDLED; --} -- - static int _omap_dss_wait_reset(void) - { - int t = 0; -@@ -549,34 +605,39 @@ - REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ - } - --int dss_init(bool skip_init) -+static int dss_init(void) - { - int r; - u32 rev; -+ struct resource *dss_mem; - -- dss.base = ioremap(DSS_BASE, DSS_SZ_REGS); -+ dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); -+ if (!dss_mem) { -+ DSSERR("can't get IORESOURCE_MEM DSS\n"); -+ r = -EINVAL; -+ goto fail0; -+ } -+ dss.base = ioremap(dss_mem->start, resource_size(dss_mem)); - if (!dss.base) { - DSSERR("can't ioremap DSS\n"); - r = -ENOMEM; - goto fail0; - } - -- if (!skip_init) { -- /* disable LCD and DIGIT output. This seems to fix the synclost -- * problem that we get, if the bootloader starts the DSS and -- * the kernel resets it */ -- omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); -- -- /* We need to wait here a bit, otherwise we sometimes start to -- * get synclost errors, and after that only power cycle will -- * restore DSS functionality. I have no idea why this happens. -- * And we have to wait _before_ resetting the DSS, but after -- * enabling clocks. -- */ -- msleep(50); -+ /* disable LCD and DIGIT output. This seems to fix the synclost -+ * problem that we get, if the bootloader starts the DSS and -+ * the kernel resets it */ -+ omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440); -+ -+ /* We need to wait here a bit, otherwise we sometimes start to -+ * get synclost errors, and after that only power cycle will -+ * restore DSS functionality. I have no idea why this happens. -+ * And we have to wait _before_ resetting the DSS, but after -+ * enabling clocks. -+ */ -+ msleep(50); - -- _omap_dss_reset(); -- } -+ _omap_dss_reset(); - - /* autoidle */ - REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0); -@@ -590,28 +651,19 @@ - REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ - #endif - -- r = request_irq(INT_24XX_DSS_IRQ, -- cpu_is_omap24xx() -- ? dss_irq_handler_omap2 -- : dss_irq_handler_omap3, -- 0, "OMAP DSS", NULL); -- -- if (r < 0) { -- DSSERR("omap2 dss: request_irq failed\n"); -- goto fail1; -- } -- - if (cpu_is_omap34xx()) { - dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck"); - if (IS_ERR(dss.dpll4_m4_ck)) { - DSSERR("Failed to get dpll4_m4_ck\n"); - r = PTR_ERR(dss.dpll4_m4_ck); -- goto fail2; -+ goto fail1; - } - } - -- dss.dsi_clk_source = DSS_SRC_DSS1_ALWON_FCLK; -- dss.dispc_clk_source = DSS_SRC_DSS1_ALWON_FCLK; -+ dss.dsi_clk_source = DSS_CLK_SRC_FCK; -+ dss.dispc_clk_source = DSS_CLK_SRC_FCK; -+ dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK; -+ dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK; - - dss_save_context(); - -@@ -621,21 +673,416 @@ - - return 0; - --fail2: -- free_irq(INT_24XX_DSS_IRQ, NULL); - fail1: - iounmap(dss.base); - fail0: - return r; - } - --void dss_exit(void) -+static void dss_exit(void) - { - if (cpu_is_omap34xx()) - clk_put(dss.dpll4_m4_ck); - -- free_irq(INT_24XX_DSS_IRQ, NULL); -- - iounmap(dss.base); - } - -+/* CONTEXT */ -+static int dss_get_ctx_id(void) -+{ -+ struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data; -+ int r; -+ -+ if (!pdata->board_data->get_last_off_on_transaction_id) -+ return 0; -+ r = pdata->board_data->get_last_off_on_transaction_id(&dss.pdev->dev); -+ if (r < 0) { -+ dev_err(&dss.pdev->dev, "getting transaction ID failed, " -+ "will force context restore\n"); -+ r = -1; -+ } -+ return r; -+} -+ -+int dss_need_ctx_restore(void) -+{ -+ int id = dss_get_ctx_id(); -+ -+ if (id < 0 || id != dss.ctx_id) { -+ DSSDBG("ctx id %d -> id %d\n", -+ dss.ctx_id, id); -+ dss.ctx_id = id; -+ return 1; -+ } else { -+ return 0; -+ } -+} -+ -+static void save_all_ctx(void) -+{ -+ DSSDBG("save context\n"); -+ -+ dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK); -+ -+ dss_save_context(); -+ dispc_save_context(); -+#ifdef CONFIG_OMAP2_DSS_DSI -+ dsi_save_context(); -+#endif -+ -+ dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK); -+} -+ -+static void restore_all_ctx(void) -+{ -+ DSSDBG("restore context\n"); -+ -+ dss_clk_enable_all_no_ctx(); -+ -+ dss_restore_context(); -+ dispc_restore_context(); -+#ifdef CONFIG_OMAP2_DSS_DSI -+ dsi_restore_context(); -+#endif -+ -+ dss_clk_disable_all_no_ctx(); -+} -+ -+static int dss_get_clock(struct clk **clock, const char *clk_name) -+{ -+ struct clk *clk; -+ -+ clk = clk_get(&dss.pdev->dev, clk_name); -+ -+ if (IS_ERR(clk)) { -+ DSSERR("can't get clock %s", clk_name); -+ return PTR_ERR(clk); -+ } -+ -+ *clock = clk; -+ -+ DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk)); -+ -+ return 0; -+} -+ -+static int dss_get_clocks(void) -+{ -+ int r; -+ struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data; -+ -+ dss.dss_ick = NULL; -+ dss.dss_fck = NULL; -+ dss.dss_sys_clk = NULL; -+ dss.dss_tv_fck = NULL; -+ dss.dss_video_fck = NULL; -+ -+ r = dss_get_clock(&dss.dss_ick, "ick"); -+ if (r) -+ goto err; -+ -+ r = dss_get_clock(&dss.dss_fck, "fck"); -+ if (r) -+ goto err; -+ -+ if (!pdata->opt_clock_available) { -+ r = -ENODEV; -+ goto err; -+ } -+ -+ if (pdata->opt_clock_available("sys_clk")) { -+ r = dss_get_clock(&dss.dss_sys_clk, "sys_clk"); -+ if (r) -+ goto err; -+ } -+ -+ if (pdata->opt_clock_available("tv_clk")) { -+ r = dss_get_clock(&dss.dss_tv_fck, "tv_clk"); -+ if (r) -+ goto err; -+ } -+ -+ if (pdata->opt_clock_available("video_clk")) { -+ r = dss_get_clock(&dss.dss_video_fck, "video_clk"); -+ if (r) -+ goto err; -+ } -+ -+ return 0; -+ -+err: -+ if (dss.dss_ick) -+ clk_put(dss.dss_ick); -+ if (dss.dss_fck) -+ clk_put(dss.dss_fck); -+ if (dss.dss_sys_clk) -+ clk_put(dss.dss_sys_clk); -+ if (dss.dss_tv_fck) -+ clk_put(dss.dss_tv_fck); -+ if (dss.dss_video_fck) -+ clk_put(dss.dss_video_fck); -+ -+ return r; -+} -+ -+static void dss_put_clocks(void) -+{ -+ if (dss.dss_video_fck) -+ clk_put(dss.dss_video_fck); -+ if (dss.dss_tv_fck) -+ clk_put(dss.dss_tv_fck); -+ if (dss.dss_sys_clk) -+ clk_put(dss.dss_sys_clk); -+ clk_put(dss.dss_fck); -+ clk_put(dss.dss_ick); -+} -+ -+unsigned long dss_clk_get_rate(enum dss_clock clk) -+{ -+ switch (clk) { -+ case DSS_CLK_ICK: -+ return clk_get_rate(dss.dss_ick); -+ case DSS_CLK_FCK: -+ return clk_get_rate(dss.dss_fck); -+ case DSS_CLK_SYSCK: -+ return clk_get_rate(dss.dss_sys_clk); -+ case DSS_CLK_TVFCK: -+ return clk_get_rate(dss.dss_tv_fck); -+ case DSS_CLK_VIDFCK: -+ return clk_get_rate(dss.dss_video_fck); -+ } -+ -+ BUG(); -+ return 0; -+} -+ -+static unsigned count_clk_bits(enum dss_clock clks) -+{ -+ unsigned num_clks = 0; -+ -+ if (clks & DSS_CLK_ICK) -+ ++num_clks; -+ if (clks & DSS_CLK_FCK) -+ ++num_clks; -+ if (clks & DSS_CLK_SYSCK) -+ ++num_clks; -+ if (clks & DSS_CLK_TVFCK) -+ ++num_clks; -+ if (clks & DSS_CLK_VIDFCK) -+ ++num_clks; -+ -+ return num_clks; -+} -+ -+static void dss_clk_enable_no_ctx(enum dss_clock clks) -+{ -+ unsigned num_clks = count_clk_bits(clks); -+ -+ if (clks & DSS_CLK_ICK) -+ clk_enable(dss.dss_ick); -+ if (clks & DSS_CLK_FCK) -+ clk_enable(dss.dss_fck); -+ if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk) -+ clk_enable(dss.dss_sys_clk); -+ if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck) -+ clk_enable(dss.dss_tv_fck); -+ if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck) -+ clk_enable(dss.dss_video_fck); -+ -+ dss.num_clks_enabled += num_clks; -+} -+ -+void dss_clk_enable(enum dss_clock clks) -+{ -+ bool check_ctx = dss.num_clks_enabled == 0; -+ -+ dss_clk_enable_no_ctx(clks); -+ -+ /* -+ * HACK: On omap4 the registers may not be accessible right after -+ * enabling the clocks. At some point this will be handled by -+ * pm_runtime, but for the time begin this should make things work. -+ */ -+ if (cpu_is_omap44xx() && check_ctx) -+ udelay(10); -+ -+ if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore()) -+ restore_all_ctx(); -+} -+ -+static void dss_clk_disable_no_ctx(enum dss_clock clks) -+{ -+ unsigned num_clks = count_clk_bits(clks); -+ -+ if (clks & DSS_CLK_ICK) -+ clk_disable(dss.dss_ick); -+ if (clks & DSS_CLK_FCK) -+ clk_disable(dss.dss_fck); -+ if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk) -+ clk_disable(dss.dss_sys_clk); -+ if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck) -+ clk_disable(dss.dss_tv_fck); -+ if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck) -+ clk_disable(dss.dss_video_fck); -+ -+ dss.num_clks_enabled -= num_clks; -+} -+ -+void dss_clk_disable(enum dss_clock clks) -+{ -+ if (cpu_is_omap34xx()) { -+ unsigned num_clks = count_clk_bits(clks); -+ -+ BUG_ON(dss.num_clks_enabled < num_clks); -+ -+ if (dss.num_clks_enabled == num_clks) -+ save_all_ctx(); -+ } -+ -+ dss_clk_disable_no_ctx(clks); -+} -+ -+static void dss_clk_enable_all_no_ctx(void) -+{ -+ enum dss_clock clks; -+ -+ clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK; -+ if (cpu_is_omap34xx()) -+ clks |= DSS_CLK_VIDFCK; -+ dss_clk_enable_no_ctx(clks); -+} -+ -+static void dss_clk_disable_all_no_ctx(void) -+{ -+ enum dss_clock clks; -+ -+ clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK; -+ if (cpu_is_omap34xx()) -+ clks |= DSS_CLK_VIDFCK; -+ dss_clk_disable_no_ctx(clks); -+} -+ -+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) -+/* CLOCKS */ -+static void core_dump_clocks(struct seq_file *s) -+{ -+ int i; -+ struct clk *clocks[5] = { -+ dss.dss_ick, -+ dss.dss_fck, -+ dss.dss_sys_clk, -+ dss.dss_tv_fck, -+ dss.dss_video_fck -+ }; -+ -+ seq_printf(s, "- CORE -\n"); -+ -+ seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled); -+ -+ for (i = 0; i < 5; i++) { -+ if (!clocks[i]) -+ continue; -+ seq_printf(s, "%-15s\t%lu\t%d\n", -+ clocks[i]->name, -+ clk_get_rate(clocks[i]), -+ clocks[i]->usecount); -+ } -+} -+#endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */ -+ -+/* DEBUGFS */ -+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) -+void dss_debug_dump_clocks(struct seq_file *s) -+{ -+ core_dump_clocks(s); -+ dss_dump_clocks(s); -+ dispc_dump_clocks(s); -+#ifdef CONFIG_OMAP2_DSS_DSI -+ dsi_dump_clocks(s); -+#endif -+} -+#endif -+ -+ -+/* DSS HW IP initialisation */ -+static int omap_dsshw_probe(struct platform_device *pdev) -+{ -+ int r; -+ -+ dss.pdev = pdev; -+ -+ r = dss_get_clocks(); -+ if (r) -+ goto err_clocks; -+ -+ dss_clk_enable_all_no_ctx(); -+ -+ dss.ctx_id = dss_get_ctx_id(); -+ DSSDBG("initial ctx id %u\n", dss.ctx_id); -+ -+ r = dss_init(); -+ if (r) { -+ DSSERR("Failed to initialize DSS\n"); -+ goto err_dss; -+ } -+ -+ r = dpi_init(); -+ if (r) { -+ DSSERR("Failed to initialize DPI\n"); -+ goto err_dpi; -+ } -+ -+ r = sdi_init(); -+ if (r) { -+ DSSERR("Failed to initialize SDI\n"); -+ goto err_sdi; -+ } -+ -+ dss_clk_disable_all_no_ctx(); -+ return 0; -+err_sdi: -+ dpi_exit(); -+err_dpi: -+ dss_exit(); -+err_dss: -+ dss_clk_disable_all_no_ctx(); -+ dss_put_clocks(); -+err_clocks: -+ return r; -+} -+ -+static int omap_dsshw_remove(struct platform_device *pdev) -+{ -+ -+ dss_exit(); -+ -+ /* -+ * As part of hwmod changes, DSS is not the only controller of dss -+ * clocks; hwmod framework itself will also enable clocks during hwmod -+ * init for dss, and autoidle is set in h/w for DSS. Hence, there's no -+ * need to disable clocks if their usecounts > 1. -+ */ -+ WARN_ON(dss.num_clks_enabled > 0); -+ -+ dss_put_clocks(); -+ return 0; -+} -+ -+static struct platform_driver omap_dsshw_driver = { -+ .probe = omap_dsshw_probe, -+ .remove = omap_dsshw_remove, -+ .driver = { -+ .name = "omapdss_dss", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+int dss_init_platform_driver(void) -+{ -+ return platform_driver_register(&omap_dsshw_driver); -+} -+ -+void dss_uninit_platform_driver(void) -+{ -+ return platform_driver_unregister(&omap_dsshw_driver); -+} -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/dss_features.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dss_features.c ---- linux-2.6.38-rc7/drivers/video/omap2/dss/dss_features.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dss_features.c 2011-03-09 13:19:21.085278903 +0100 -@@ -25,6 +25,7 @@ - #include - #include - -+#include "dss.h" - #include "dss_features.h" - - /* Defines a generic omap register field */ -@@ -41,8 +42,10 @@ - - const int num_mgrs; - const int num_ovls; -+ const unsigned long max_dss_fck; - const enum omap_display_type *supported_displays; - const enum omap_color_mode *supported_color_modes; -+ const struct dss_clk_source_name *clksrc_names; - }; - - /* This struct is assigned to one of the below during initialization */ -@@ -54,6 +57,9 @@ - { FEAT_REG_FIFOLOWTHRESHOLD, 8, 0 }, - { FEAT_REG_FIFOHIGHTHRESHOLD, 24, 16 }, - { FEAT_REG_FIFOSIZE, 8, 0 }, -+ { FEAT_REG_HORIZONTALACCU, 9, 0 }, -+ { FEAT_REG_VERTICALACCU, 25, 16 }, -+ { FEAT_REG_DISPC_CLK_SWITCH, 0, 0 }, - }; - - static const struct dss_reg_field omap3_dss_reg_fields[] = { -@@ -62,10 +68,32 @@ - { FEAT_REG_FIFOLOWTHRESHOLD, 11, 0 }, - { FEAT_REG_FIFOHIGHTHRESHOLD, 27, 16 }, - { FEAT_REG_FIFOSIZE, 10, 0 }, -+ { FEAT_REG_HORIZONTALACCU, 9, 0 }, -+ { FEAT_REG_VERTICALACCU, 25, 16 }, -+ { FEAT_REG_DISPC_CLK_SWITCH, 0, 0 }, -+}; -+ -+static const struct dss_reg_field omap4_dss_reg_fields[] = { -+ { FEAT_REG_FIRHINC, 12, 0 }, -+ { FEAT_REG_FIRVINC, 28, 16 }, -+ { FEAT_REG_FIFOLOWTHRESHOLD, 15, 0 }, -+ { FEAT_REG_FIFOHIGHTHRESHOLD, 31, 16 }, -+ { FEAT_REG_FIFOSIZE, 15, 0 }, -+ { FEAT_REG_HORIZONTALACCU, 10, 0 }, -+ { FEAT_REG_VERTICALACCU, 26, 16 }, -+ { FEAT_REG_DISPC_CLK_SWITCH, 9, 8 }, - }; - - static const enum omap_display_type omap2_dss_supported_displays[] = { - /* OMAP_DSS_CHANNEL_LCD */ -+ OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI, -+ -+ /* OMAP_DSS_CHANNEL_DIGIT */ -+ OMAP_DISPLAY_TYPE_VENC, -+}; -+ -+static const enum omap_display_type omap3430_dss_supported_displays[] = { -+ /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | - OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI, - -@@ -73,10 +101,10 @@ - OMAP_DISPLAY_TYPE_VENC, - }; - --static const enum omap_display_type omap3_dss_supported_displays[] = { -+static const enum omap_display_type omap3630_dss_supported_displays[] = { - /* OMAP_DSS_CHANNEL_LCD */ - OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | -- OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI, -+ OMAP_DISPLAY_TYPE_DSI, - - /* OMAP_DSS_CHANNEL_DIGIT */ - OMAP_DISPLAY_TYPE_VENC, -@@ -134,6 +162,24 @@ - OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32, - }; - -+static const struct dss_clk_source_name omap2_dss_clk_source_names[] = { -+ { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "N/A" }, -+ { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "N/A" }, -+ { DSS_CLK_SRC_FCK, "DSS_FCLK1" }, -+}; -+ -+static const struct dss_clk_source_name omap3_dss_clk_source_names[] = { -+ { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI1_PLL_FCLK" }, -+ { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI2_PLL_FCLK" }, -+ { DSS_CLK_SRC_FCK, "DSS1_ALWON_FCLK" }, -+}; -+ -+static const struct dss_clk_source_name omap4_dss_clk_source_names[] = { -+ { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "PLL1_CLK1" }, -+ { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "PLL1_CLK2" }, -+ { DSS_CLK_SRC_FCK, "DSS_FCLK" }, -+}; -+ - /* OMAP2 DSS Features */ - static struct omap_dss_features omap2_dss_features = { - .reg_fields = omap2_dss_reg_fields, -@@ -141,12 +187,15 @@ - - .has_feature = - FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL | -- FEAT_PCKFREEENABLE | FEAT_FUNCGATED, -+ FEAT_PCKFREEENABLE | FEAT_FUNCGATED | -+ FEAT_ROWREPEATENABLE | FEAT_RESIZECONF, - - .num_mgrs = 2, - .num_ovls = 3, -+ .max_dss_fck = 173000000, - .supported_displays = omap2_dss_supported_displays, - .supported_color_modes = omap2_dss_supported_color_modes, -+ .clksrc_names = omap2_dss_clk_source_names, - }; - - /* OMAP3 DSS Features */ -@@ -157,12 +206,15 @@ - .has_feature = - FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL | - FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE | -- FEAT_FUNCGATED, -+ FEAT_FUNCGATED | FEAT_ROWREPEATENABLE | -+ FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF, - - .num_mgrs = 2, - .num_ovls = 3, -- .supported_displays = omap3_dss_supported_displays, -+ .max_dss_fck = 173000000, -+ .supported_displays = omap3430_dss_supported_displays, - .supported_color_modes = omap3_dss_supported_color_modes, -+ .clksrc_names = omap3_dss_clk_source_names, - }; - - static struct omap_dss_features omap3630_dss_features = { -@@ -172,27 +224,34 @@ - .has_feature = - FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL | - FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE | -- FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED, -+ FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED | -+ FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT | -+ FEAT_RESIZECONF, - - .num_mgrs = 2, - .num_ovls = 3, -- .supported_displays = omap3_dss_supported_displays, -+ .max_dss_fck = 173000000, -+ .supported_displays = omap3630_dss_supported_displays, - .supported_color_modes = omap3_dss_supported_color_modes, -+ .clksrc_names = omap3_dss_clk_source_names, - }; - - /* OMAP4 DSS Features */ - static struct omap_dss_features omap4_dss_features = { -- .reg_fields = omap3_dss_reg_fields, -- .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), -+ .reg_fields = omap4_dss_reg_fields, -+ .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields), - - .has_feature = - FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA | -- FEAT_MGR_LCD2, -+ FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 | -+ FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC, - - .num_mgrs = 3, - .num_ovls = 3, -+ .max_dss_fck = 186000000, - .supported_displays = omap4_dss_supported_displays, - .supported_color_modes = omap3_dss_supported_color_modes, -+ .clksrc_names = omap4_dss_clk_source_names, - }; - - /* Functions returning values related to a DSS feature */ -@@ -206,6 +265,12 @@ - return omap_current_dss_features->num_ovls; - } - -+/* Max supported DSS FCK in Hz */ -+unsigned long dss_feat_get_max_dss_fck(void) -+{ -+ return omap_current_dss_features->max_dss_fck; -+} -+ - enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel) - { - return omap_current_dss_features->supported_displays[channel]; -@@ -223,6 +288,11 @@ - color_mode; - } - -+const char *dss_feat_get_clk_source_name(enum dss_clk_source id) -+{ -+ return omap_current_dss_features->clksrc_names[id].clksrc_name; -+} -+ - /* DSS has_feature check */ - bool dss_has_feature(enum dss_feat_id id) - { -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/dss_features.h linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dss_features.h ---- linux-2.6.38-rc7/drivers/video/omap2/dss/dss_features.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dss_features.h 2011-03-09 13:19:21.085278903 +0100 -@@ -22,6 +22,7 @@ - - #define MAX_DSS_MANAGERS 3 - #define MAX_DSS_OVERLAYS 3 -+#define MAX_DSS_LCD_MANAGERS 2 - - /* DSS has feature id */ - enum dss_feat_id { -@@ -33,6 +34,12 @@ - FEAT_PCKFREEENABLE = 1 << 5, - FEAT_FUNCGATED = 1 << 6, - FEAT_MGR_LCD2 = 1 << 7, -+ FEAT_LINEBUFFERSPLIT = 1 << 8, -+ FEAT_ROWREPEATENABLE = 1 << 9, -+ FEAT_RESIZECONF = 1 << 10, -+ /* Independent core clk divider */ -+ FEAT_CORE_CLK_DIV = 1 << 11, -+ FEAT_LCD_CLK_SRC = 1 << 12, - }; - - /* DSS register field id */ -@@ -42,15 +49,20 @@ - FEAT_REG_FIFOHIGHTHRESHOLD, - FEAT_REG_FIFOLOWTHRESHOLD, - FEAT_REG_FIFOSIZE, -+ FEAT_REG_HORIZONTALACCU, -+ FEAT_REG_VERTICALACCU, -+ FEAT_REG_DISPC_CLK_SWITCH, - }; - - /* DSS Feature Functions */ - int dss_feat_get_num_mgrs(void); - int dss_feat_get_num_ovls(void); -+unsigned long dss_feat_get_max_dss_fck(void); - enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel); - enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); - bool dss_feat_color_mode_supported(enum omap_plane plane, - enum omap_color_mode color_mode); -+const char *dss_feat_get_clk_source_name(enum dss_clk_source id); - - bool dss_has_feature(enum dss_feat_id id); - void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/dss.h linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dss.h ---- linux-2.6.38-rc7/drivers/video/omap2/dss/dss.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/dss.h 2011-03-09 13:19:21.085278903 +0100 -@@ -97,8 +97,6 @@ - #define FLD_MOD(orig, val, start, end) \ - (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) - --#define DISPC_MAX_FCK 173000000 -- - enum omap_burst_size { - OMAP_DSS_BURST_4x32 = 0, - OMAP_DSS_BURST_8x32 = 1, -@@ -112,17 +110,26 @@ - }; - - enum dss_clock { -- DSS_CLK_ICK = 1 << 0, -- DSS_CLK_FCK1 = 1 << 1, -- DSS_CLK_FCK2 = 1 << 2, -- DSS_CLK_54M = 1 << 3, -- DSS_CLK_96M = 1 << 4, -+ DSS_CLK_ICK = 1 << 0, /* DSS_L3_ICLK and DSS_L4_ICLK */ -+ DSS_CLK_FCK = 1 << 1, /* DSS1_ALWON_FCLK */ -+ DSS_CLK_SYSCK = 1 << 2, /* DSS2_ALWON_FCLK */ -+ DSS_CLK_TVFCK = 1 << 3, /* DSS_TV_FCLK */ -+ DSS_CLK_VIDFCK = 1 << 4, /* DSS_96M_FCLK*/ - }; - - enum dss_clk_source { -- DSS_SRC_DSI1_PLL_FCLK, -- DSS_SRC_DSI2_PLL_FCLK, -- DSS_SRC_DSS1_ALWON_FCLK, -+ DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK -+ * OMAP4: PLL1_CLK1 */ -+ DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK -+ * OMAP4: PLL1_CLK2 */ -+ DSS_CLK_SRC_FCK, /* OMAP2/3: DSS1_ALWON_FCLK -+ * OMAP4: DSS_FCLK */ -+}; -+ -+/* Correlates clock source name and dss_clk_source member */ -+struct dss_clk_source_name { -+ enum dss_clk_source clksrc; -+ const char *clksrc_name; - }; - - struct dss_clock_info { -@@ -148,36 +155,32 @@ - unsigned long fint; - unsigned long clkin4ddr; - unsigned long clkin; -- unsigned long dsi1_pll_fclk; -- unsigned long dsi2_pll_fclk; -- -+ unsigned long dsi_pll_hsdiv_dispc_clk; /* OMAP3: DSI1_PLL_CLK -+ * OMAP4: PLLx_CLK1 */ -+ unsigned long dsi_pll_hsdiv_dsi_clk; /* OMAP3: DSI2_PLL_CLK -+ * OMAP4: PLLx_CLK2 */ - unsigned long lp_clk; - - /* dividers */ - u16 regn; - u16 regm; -- u16 regm3; -- u16 regm4; -- -+ u16 regm_dispc; /* OMAP3: REGM3 -+ * OMAP4: REGM4 */ -+ u16 regm_dsi; /* OMAP3: REGM4 -+ * OMAP4: REGM5 */ - u16 lp_clk_div; - - u8 highfreq; -- bool use_dss2_fck; -+ bool use_sys_clk; - }; - - struct seq_file; - struct platform_device; - - /* core */ --void dss_clk_enable(enum dss_clock clks); --void dss_clk_disable(enum dss_clock clks); --unsigned long dss_clk_get_rate(enum dss_clock clk); --int dss_need_ctx_restore(void); --void dss_dump_clocks(struct seq_file *s); - struct bus_type *dss_get_bus(void); - struct regulator *dss_get_vdds_dsi(void); - struct regulator *dss_get_vdds_sdi(void); --struct regulator *dss_get_vdda_dac(void); - - /* display */ - int dss_suspend_all_devices(void); -@@ -214,13 +217,22 @@ - void dss_recheck_connections(struct omap_dss_device *dssdev, bool force); - - /* DSS */ --int dss_init(bool skip_init); --void dss_exit(void); -+int dss_init_platform_driver(void); -+void dss_uninit_platform_driver(void); - - void dss_save_context(void); - void dss_restore_context(void); -+void dss_clk_enable(enum dss_clock clks); -+void dss_clk_disable(enum dss_clock clks); -+unsigned long dss_clk_get_rate(enum dss_clock clk); -+int dss_need_ctx_restore(void); -+const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src); -+void dss_dump_clocks(struct seq_file *s); - - void dss_dump_regs(struct seq_file *s); -+#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) -+void dss_debug_dump_clocks(struct seq_file *s); -+#endif - - void dss_sdi_init(u8 datapairs); - int dss_sdi_enable(void); -@@ -228,8 +240,11 @@ - - void dss_select_dispc_clk_source(enum dss_clk_source clk_src); - void dss_select_dsi_clk_source(enum dss_clk_source clk_src); -+void dss_select_lcd_clk_source(enum omap_channel channel, -+ enum dss_clk_source clk_src); - enum dss_clk_source dss_get_dispc_clk_source(void); - enum dss_clk_source dss_get_dsi_clk_source(void); -+enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel); - - void dss_set_venc_output(enum omap_dss_venc_type type); - void dss_set_dac_pwrdn_bgz(bool enable); -@@ -244,11 +259,11 @@ - - /* SDI */ - #ifdef CONFIG_OMAP2_DSS_SDI --int sdi_init(bool skip_init); -+int sdi_init(void); - void sdi_exit(void); - int sdi_init_display(struct omap_dss_device *display); - #else --static inline int sdi_init(bool skip_init) -+static inline int sdi_init(void) - { - return 0; - } -@@ -259,8 +274,8 @@ - - /* DSI */ - #ifdef CONFIG_OMAP2_DSS_DSI --int dsi_init(struct platform_device *pdev); --void dsi_exit(void); -+int dsi_init_platform_driver(void); -+void dsi_uninit_platform_driver(void); - - void dsi_dump_clocks(struct seq_file *s); - void dsi_dump_irqs(struct seq_file *s); -@@ -271,7 +286,7 @@ - - int dsi_init_display(struct omap_dss_device *display); - void dsi_irq_handler(void); --unsigned long dsi_get_dsi1_pll_rate(void); -+unsigned long dsi_get_pll_hsdiv_dispc_rate(void); - int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo); - int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck, - struct dsi_clock_info *cinfo, -@@ -282,31 +297,36 @@ - void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, - u32 fifo_size, enum omap_burst_size *burst_size, - u32 *fifo_low, u32 *fifo_high); --void dsi_wait_dsi1_pll_active(void); --void dsi_wait_dsi2_pll_active(void); -+void dsi_wait_pll_hsdiv_dispc_active(void); -+void dsi_wait_pll_hsdiv_dsi_active(void); - #else --static inline int dsi_init(struct platform_device *pdev) -+static inline int dsi_init_platform_driver(void) - { - return 0; - } --static inline void dsi_exit(void) -+static inline void dsi_uninit_platform_driver(void) -+{ -+} -+static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(void) - { -+ WARN("%s: DSI not compiled in, returning rate as 0\n", __func__); -+ return 0; - } --static inline void dsi_wait_dsi1_pll_active(void) -+static inline void dsi_wait_pll_hsdiv_dispc_active(void) - { - } --static inline void dsi_wait_dsi2_pll_active(void) -+static inline void dsi_wait_pll_hsdiv_dsi_active(void) - { - } - #endif - - /* DPI */ - #ifdef CONFIG_OMAP2_DSS_DPI --int dpi_init(struct platform_device *pdev); -+int dpi_init(void); - void dpi_exit(void); - int dpi_init_display(struct omap_dss_device *dssdev); - #else --static inline int dpi_init(struct platform_device *pdev) -+static inline int dpi_init(void) - { - return 0; - } -@@ -316,8 +336,8 @@ - #endif - - /* DISPC */ --int dispc_init(void); --void dispc_exit(void); -+int dispc_init_platform_driver(void); -+void dispc_uninit_platform_driver(void); - void dispc_dump_clocks(struct seq_file *s); - void dispc_dump_irqs(struct seq_file *s); - void dispc_dump_regs(struct seq_file *s); -@@ -409,24 +429,24 @@ - - /* VENC */ - #ifdef CONFIG_OMAP2_DSS_VENC --int venc_init(struct platform_device *pdev); --void venc_exit(void); -+int venc_init_platform_driver(void); -+void venc_uninit_platform_driver(void); - void venc_dump_regs(struct seq_file *s); - int venc_init_display(struct omap_dss_device *display); - #else --static inline int venc_init(struct platform_device *pdev) -+static inline int venc_init_platform_driver(void) - { - return 0; - } --static inline void venc_exit(void) -+static inline void venc_uninit_platform_driver(void) - { - } - #endif - - /* RFBI */ - #ifdef CONFIG_OMAP2_DSS_RFBI --int rfbi_init(void); --void rfbi_exit(void); -+int rfbi_init_platform_driver(void); -+void rfbi_uninit_platform_driver(void); - void rfbi_dump_regs(struct seq_file *s); - - int rfbi_configure(int rfbi_module, int bpp, int lines); -@@ -437,11 +457,11 @@ - unsigned long rfbi_get_max_tx_rate(void); - int rfbi_init_display(struct omap_dss_device *display); - #else --static inline int rfbi_init(void) -+static inline int rfbi_init_platform_driver(void) - { - return 0; - } --static inline void rfbi_exit(void) -+static inline void rfbi_uninit_platform_driver(void) - { - } - #endif -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/Kconfig ---- linux-2.6.38-rc7/drivers/video/omap2/dss/Kconfig 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/Kconfig 2011-03-09 13:19:21.081278983 +0100 -@@ -1,8 +1,8 @@ - menuconfig OMAP2_DSS -- tristate "OMAP2/3 Display Subsystem support (EXPERIMENTAL)" -- depends on ARCH_OMAP2 || ARCH_OMAP3 -+ tristate "OMAP2+ Display Subsystem support (EXPERIMENTAL)" -+ depends on ARCH_OMAP2PLUS - help -- OMAP2/3 Display Subsystem support. -+ OMAP2+ Display Subsystem support. - - if OMAP2_DSS - -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/manager.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/manager.c ---- linux-2.6.38-rc7/drivers/video/omap2/dss/manager.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/manager.c 2011-03-09 13:19:21.086278883 +0100 -@@ -1394,7 +1394,7 @@ - } - - r = 0; -- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); - if (!dss_cache.irq_enabled) { - u32 mask; - -@@ -1407,7 +1407,7 @@ - dss_cache.irq_enabled = true; - } - configure_dispc(); -- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); - - spin_unlock_irqrestore(&dss_cache.lock, flags); - -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/overlay.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/overlay.c ---- linux-2.6.38-rc7/drivers/video/omap2/dss/overlay.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/overlay.c 2011-03-09 13:19:21.086278883 +0100 -@@ -490,7 +490,7 @@ - - ovl->manager = mgr; - -- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); - /* XXX: on manual update display, in auto update mode, a bug happens - * here. When an overlay is first enabled on LCD, then it's disabled, - * and the manager is changed to TV, we sometimes get SYNC_LOST_DIGIT -@@ -499,7 +499,7 @@ - * but I don't understand how or why. */ - msleep(40); - dispc_set_channel_out(ovl->id, mgr->id); -- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); - - return 0; - } -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/rfbi.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/rfbi.c ---- linux-2.6.38-rc7/drivers/video/omap2/dss/rfbi.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/rfbi.c 2011-03-09 13:19:21.086278883 +0100 -@@ -36,8 +36,6 @@ - #include - #include "dss.h" - --#define RFBI_BASE 0x48050800 -- - struct rfbi_reg { u16 idx; }; - - #define RFBI_REG(idx) ((const struct rfbi_reg) { idx }) -@@ -100,6 +98,7 @@ - static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div); - - static struct { -+ struct platform_device *pdev; - void __iomem *base; - - unsigned long l4_khz; -@@ -142,9 +141,9 @@ - static void rfbi_enable_clocks(bool enable) - { - if (enable) -- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); - else -- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); - } - - void omap_rfbi_write_command(const void *buf, u32 len) -@@ -497,7 +496,7 @@ - }; - - l4_rate = rfbi.l4_khz / 1000; -- dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000; -+ dss1_rate = dss_clk_get_rate(DSS_CLK_FCK) / 1000000; - - for (i = 0; i < ARRAY_SIZE(ftab); i++) { - /* Use a window instead of an exact match, to account -@@ -922,7 +921,7 @@ - { - #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r)) - -- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); - - DUMPREG(RFBI_REVISION); - DUMPREG(RFBI_SYSCONFIG); -@@ -953,54 +952,10 @@ - DUMPREG(RFBI_VSYNC_WIDTH); - DUMPREG(RFBI_HSYNC_WIDTH); - -- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); - #undef DUMPREG - } - --int rfbi_init(void) --{ -- u32 rev; -- u32 l; -- -- spin_lock_init(&rfbi.cmd_lock); -- -- init_completion(&rfbi.cmd_done); -- atomic_set(&rfbi.cmd_fifo_full, 0); -- atomic_set(&rfbi.cmd_pending, 0); -- -- rfbi.base = ioremap(RFBI_BASE, SZ_256); -- if (!rfbi.base) { -- DSSERR("can't ioremap RFBI\n"); -- return -ENOMEM; -- } -- -- rfbi_enable_clocks(1); -- -- msleep(10); -- -- rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000; -- -- /* Enable autoidle and smart-idle */ -- l = rfbi_read_reg(RFBI_SYSCONFIG); -- l |= (1 << 0) | (2 << 3); -- rfbi_write_reg(RFBI_SYSCONFIG, l); -- -- rev = rfbi_read_reg(RFBI_REVISION); -- printk(KERN_INFO "OMAP RFBI rev %d.%d\n", -- FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); -- -- rfbi_enable_clocks(0); -- -- return 0; --} -- --void rfbi_exit(void) --{ -- DSSDBG("rfbi_exit\n"); -- -- iounmap(rfbi.base); --} -- - int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev) - { - int r; -@@ -1056,3 +1011,74 @@ - dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE; - return 0; - } -+ -+/* RFBI HW IP initialisation */ -+static int omap_rfbihw_probe(struct platform_device *pdev) -+{ -+ u32 rev; -+ u32 l; -+ struct resource *rfbi_mem; -+ -+ rfbi.pdev = pdev; -+ -+ spin_lock_init(&rfbi.cmd_lock); -+ -+ init_completion(&rfbi.cmd_done); -+ atomic_set(&rfbi.cmd_fifo_full, 0); -+ atomic_set(&rfbi.cmd_pending, 0); -+ -+ rfbi_mem = platform_get_resource(rfbi.pdev, IORESOURCE_MEM, 0); -+ if (!rfbi_mem) { -+ DSSERR("can't get IORESOURCE_MEM RFBI\n"); -+ return -EINVAL; -+ } -+ rfbi.base = ioremap(rfbi_mem->start, resource_size(rfbi_mem)); -+ if (!rfbi.base) { -+ DSSERR("can't ioremap RFBI\n"); -+ return -ENOMEM; -+ } -+ -+ rfbi_enable_clocks(1); -+ -+ msleep(10); -+ -+ rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000; -+ -+ /* Enable autoidle and smart-idle */ -+ l = rfbi_read_reg(RFBI_SYSCONFIG); -+ l |= (1 << 0) | (2 << 3); -+ rfbi_write_reg(RFBI_SYSCONFIG, l); -+ -+ rev = rfbi_read_reg(RFBI_REVISION); -+ dev_dbg(&pdev->dev, "OMAP RFBI rev %d.%d\n", -+ FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); -+ -+ rfbi_enable_clocks(0); -+ -+ return 0; -+} -+ -+static int omap_rfbihw_remove(struct platform_device *pdev) -+{ -+ iounmap(rfbi.base); -+ return 0; -+} -+ -+static struct platform_driver omap_rfbihw_driver = { -+ .probe = omap_rfbihw_probe, -+ .remove = omap_rfbihw_remove, -+ .driver = { -+ .name = "omapdss_rfbi", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+int rfbi_init_platform_driver(void) -+{ -+ return platform_driver_register(&omap_rfbihw_driver); -+} -+ -+void rfbi_uninit_platform_driver(void) -+{ -+ return platform_driver_unregister(&omap_rfbihw_driver); -+} -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/sdi.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/sdi.c ---- linux-2.6.38-rc7/drivers/video/omap2/dss/sdi.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/sdi.c 2011-03-09 13:19:21.086278883 +0100 -@@ -30,7 +30,6 @@ - #include "dss.h" - - static struct { -- bool skip_init; - bool update_enabled; - struct regulator *vdds_sdi_reg; - } sdi; -@@ -68,9 +67,7 @@ - if (r) - goto err1; - -- /* In case of skip_init sdi_init has already enabled the clocks */ -- if (!sdi.skip_init) -- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); - - sdi_basic_init(dssdev); - -@@ -80,14 +77,8 @@ - dispc_set_pol_freq(dssdev->manager->id, dssdev->panel.config, - dssdev->panel.acbi, dssdev->panel.acb); - -- if (!sdi.skip_init) { -- r = dss_calc_clock_div(1, t->pixel_clock * 1000, -- &dss_cinfo, &dispc_cinfo); -- } else { -- r = dss_get_clock_div(&dss_cinfo); -- r = dispc_get_clock_div(dssdev->manager->id, &dispc_cinfo); -- } -- -+ r = dss_calc_clock_div(1, t->pixel_clock * 1000, -+ &dss_cinfo, &dispc_cinfo); - if (r) - goto err2; - -@@ -116,21 +107,17 @@ - if (r) - goto err2; - -- if (!sdi.skip_init) { -- dss_sdi_init(dssdev->phy.sdi.datapairs); -- r = dss_sdi_enable(); -- if (r) -- goto err1; -- mdelay(2); -- } -+ dss_sdi_init(dssdev->phy.sdi.datapairs); -+ r = dss_sdi_enable(); -+ if (r) -+ goto err1; -+ mdelay(2); - - dssdev->manager->enable(dssdev->manager); - -- sdi.skip_init = 0; -- - return 0; - err2: -- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); - regulator_disable(sdi.vdds_sdi_reg); - err1: - omap_dss_stop_device(dssdev); -@@ -145,7 +132,7 @@ - - dss_sdi_disable(); - -- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); - - regulator_disable(sdi.vdds_sdi_reg); - -@@ -157,25 +144,24 @@ - { - DSSDBG("SDI init\n"); - -+ if (sdi.vdds_sdi_reg == NULL) { -+ struct regulator *vdds_sdi; -+ -+ vdds_sdi = dss_get_vdds_sdi(); -+ -+ if (IS_ERR(vdds_sdi)) { -+ DSSERR("can't get VDDS_SDI regulator\n"); -+ return PTR_ERR(vdds_sdi); -+ } -+ -+ sdi.vdds_sdi_reg = vdds_sdi; -+ } -+ - return 0; - } - --int sdi_init(bool skip_init) -+int sdi_init(void) - { -- /* we store this for first display enable, then clear it */ -- sdi.skip_init = skip_init; -- -- sdi.vdds_sdi_reg = dss_get_vdds_sdi(); -- if (IS_ERR(sdi.vdds_sdi_reg)) { -- DSSERR("can't get VDDS_SDI regulator\n"); -- return PTR_ERR(sdi.vdds_sdi_reg); -- } -- /* -- * Enable clocks already here, otherwise there would be a toggle -- * of them until sdi_display_enable is called. -- */ -- if (skip_init) -- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); - return 0; - } - -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/dss/venc.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/venc.c ---- linux-2.6.38-rc7/drivers/video/omap2/dss/venc.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/dss/venc.c 2011-03-09 13:19:21.087278863 +0100 -@@ -39,8 +39,6 @@ - - #include "dss.h" - --#define VENC_BASE 0x48050C00 -- - /* Venc registers */ - #define VENC_REV_ID 0x00 - #define VENC_STATUS 0x04 -@@ -289,6 +287,7 @@ - EXPORT_SYMBOL(omap_dss_ntsc_timings); - - static struct { -+ struct platform_device *pdev; - void __iomem *base; - struct mutex venc_lock; - u32 wss_data; -@@ -381,11 +380,11 @@ - static void venc_enable_clocks(int enable) - { - if (enable) -- dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M | -- DSS_CLK_96M); -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK | -+ DSS_CLK_VIDFCK); - else -- dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_54M | -- DSS_CLK_96M); -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_TVFCK | -+ DSS_CLK_VIDFCK); - } - - static const struct venc_config *venc_timings_to_config( -@@ -641,50 +640,23 @@ - }; - /* driver end */ - -- -- --int venc_init(struct platform_device *pdev) -+int venc_init_display(struct omap_dss_device *dssdev) - { -- u8 rev_id; -+ DSSDBG("init_display\n"); - -- mutex_init(&venc.venc_lock); -+ if (venc.vdda_dac_reg == NULL) { -+ struct regulator *vdda_dac; - -- venc.wss_data = 0; -+ vdda_dac = regulator_get(&venc.pdev->dev, "vdda_dac"); - -- venc.base = ioremap(VENC_BASE, SZ_1K); -- if (!venc.base) { -- DSSERR("can't ioremap VENC\n"); -- return -ENOMEM; -- } -+ if (IS_ERR(vdda_dac)) { -+ DSSERR("can't get VDDA_DAC regulator\n"); -+ return PTR_ERR(vdda_dac); -+ } - -- venc.vdda_dac_reg = dss_get_vdda_dac(); -- if (IS_ERR(venc.vdda_dac_reg)) { -- iounmap(venc.base); -- DSSERR("can't get VDDA_DAC regulator\n"); -- return PTR_ERR(venc.vdda_dac_reg); -+ venc.vdda_dac_reg = vdda_dac; - } - -- venc_enable_clocks(1); -- -- rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); -- printk(KERN_INFO "OMAP VENC rev %d\n", rev_id); -- -- venc_enable_clocks(0); -- -- return omap_dss_register_driver(&venc_driver); --} -- --void venc_exit(void) --{ -- omap_dss_unregister_driver(&venc_driver); -- -- iounmap(venc.base); --} -- --int venc_init_display(struct omap_dss_device *dssdev) --{ -- DSSDBG("init_display\n"); -- - return 0; - } - -@@ -740,3 +712,67 @@ - - #undef DUMPREG - } -+ -+/* VENC HW IP initialisation */ -+static int omap_venchw_probe(struct platform_device *pdev) -+{ -+ u8 rev_id; -+ struct resource *venc_mem; -+ -+ venc.pdev = pdev; -+ -+ mutex_init(&venc.venc_lock); -+ -+ venc.wss_data = 0; -+ -+ venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0); -+ if (!venc_mem) { -+ DSSERR("can't get IORESOURCE_MEM VENC\n"); -+ return -EINVAL; -+ } -+ venc.base = ioremap(venc_mem->start, resource_size(venc_mem)); -+ if (!venc.base) { -+ DSSERR("can't ioremap VENC\n"); -+ return -ENOMEM; -+ } -+ -+ venc_enable_clocks(1); -+ -+ rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); -+ dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id); -+ -+ venc_enable_clocks(0); -+ -+ return omap_dss_register_driver(&venc_driver); -+} -+ -+static int omap_venchw_remove(struct platform_device *pdev) -+{ -+ if (venc.vdda_dac_reg != NULL) { -+ regulator_put(venc.vdda_dac_reg); -+ venc.vdda_dac_reg = NULL; -+ } -+ omap_dss_unregister_driver(&venc_driver); -+ -+ iounmap(venc.base); -+ return 0; -+} -+ -+static struct platform_driver omap_venchw_driver = { -+ .probe = omap_venchw_probe, -+ .remove = omap_venchw_remove, -+ .driver = { -+ .name = "omapdss_venc", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+int venc_init_platform_driver(void) -+{ -+ return platform_driver_register(&omap_venchw_driver); -+} -+ -+void venc_uninit_platform_driver(void) -+{ -+ return platform_driver_unregister(&omap_venchw_driver); -+} -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/omapfb/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/omapfb/Kconfig ---- linux-2.6.38-rc7/drivers/video/omap2/omapfb/Kconfig 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/omapfb/Kconfig 2011-03-09 13:19:21.087278863 +0100 -@@ -1,5 +1,5 @@ - menuconfig FB_OMAP2 -- tristate "OMAP2/3 frame buffer support (EXPERIMENTAL)" -+ tristate "OMAP2+ frame buffer support (EXPERIMENTAL)" - depends on FB && OMAP2_DSS - - select OMAP2_VRAM -@@ -8,10 +8,10 @@ - select FB_CFB_COPYAREA - select FB_CFB_IMAGEBLIT - help -- Frame buffer driver for OMAP2/3 based boards. -+ Frame buffer driver for OMAP2+ based boards. - - config FB_OMAP2_DEBUG_SUPPORT -- bool "Debug support for OMAP2/3 FB" -+ bool "Debug support for OMAP2+ FB" - default y - depends on FB_OMAP2 - help -diff -Naur linux-2.6.38-rc7/drivers/video/omap2/omapfb/omapfb-main.c linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/omapfb/omapfb-main.c ---- linux-2.6.38-rc7/drivers/video/omap2/omapfb/omapfb-main.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/video/omap2/omapfb/omapfb-main.c 2011-03-09 13:19:21.088278842 +0100 -@@ -2090,7 +2090,7 @@ - { - int r; - u8 bpp; -- struct omap_video_timings timings; -+ struct omap_video_timings timings, temp_timings; - - r = omapfb_mode_to_timings(mode_str, &timings, &bpp); - if (r) -@@ -2100,14 +2100,23 @@ - fbdev->bpp_overrides[fbdev->num_bpp_overrides].bpp = bpp; - ++fbdev->num_bpp_overrides; - -- if (!display->driver->check_timings || !display->driver->set_timings) -- return -EINVAL; -- -- r = display->driver->check_timings(display, &timings); -- if (r) -- return r; -+ if (display->driver->check_timings) { -+ r = display->driver->check_timings(display, &timings); -+ if (r) -+ return r; -+ } else { -+ /* If check_timings is not present compare xres and yres */ -+ if (display->driver->get_timings) { -+ display->driver->get_timings(display, &temp_timings); -+ -+ if (temp_timings.x_res != timings.x_res || -+ temp_timings.y_res != timings.y_res) -+ return -EINVAL; -+ } -+ } - -- display->driver->set_timings(display, &timings); -+ if (display->driver->set_timings) -+ display->driver->set_timings(display, &timings); - - return 0; - } -diff -Naur linux-2.6.38-rc7/drivers/w1/masters/Kconfig linux-2.6.38-rc7-linux-omap-dss2/drivers/w1/masters/Kconfig ---- linux-2.6.38-rc7/drivers/w1/masters/Kconfig 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/drivers/w1/masters/Kconfig 2011-03-09 13:19:21.142277747 +0100 -@@ -60,7 +60,7 @@ - - config HDQ_MASTER_OMAP - tristate "OMAP HDQ driver" -- depends on ARCH_OMAP2430 || ARCH_OMAP3 -+ depends on SOC_OMAP2430 || ARCH_OMAP3 - help - Say Y here if you want support for the 1-wire or HDQ Interface - on an OMAP processor. -diff -Naur linux-2.6.38-rc7/include/linux/hwspinlock.h linux-2.6.38-rc7-linux-omap-dss2/include/linux/hwspinlock.h ---- linux-2.6.38-rc7/include/linux/hwspinlock.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/include/linux/hwspinlock.h 2011-03-09 13:19:21.851263363 +0100 -@@ -0,0 +1,292 @@ -+/* -+ * Hardware spinlock public header -+ * -+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com -+ * -+ * Contact: Ohad Ben-Cohen -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef __LINUX_HWSPINLOCK_H -+#define __LINUX_HWSPINLOCK_H -+ -+#include -+#include -+ -+/* hwspinlock mode argument */ -+#define HWLOCK_IRQSTATE 0x01 /* Disable interrupts, save state */ -+#define HWLOCK_IRQ 0x02 /* Disable interrupts, don't save state */ -+ -+struct hwspinlock; -+ -+#if defined(CONFIG_HWSPINLOCK) || defined(CONFIG_HWSPINLOCK_MODULE) -+ -+int hwspin_lock_register(struct hwspinlock *lock); -+struct hwspinlock *hwspin_lock_unregister(unsigned int id); -+struct hwspinlock *hwspin_lock_request(void); -+struct hwspinlock *hwspin_lock_request_specific(unsigned int id); -+int hwspin_lock_free(struct hwspinlock *hwlock); -+int hwspin_lock_get_id(struct hwspinlock *hwlock); -+int __hwspin_lock_timeout(struct hwspinlock *, unsigned int, int, -+ unsigned long *); -+int __hwspin_trylock(struct hwspinlock *, int, unsigned long *); -+void __hwspin_unlock(struct hwspinlock *, int, unsigned long *); -+ -+#else /* !CONFIG_HWSPINLOCK */ -+ -+/* -+ * We don't want these functions to fail if CONFIG_HWSPINLOCK is not -+ * enabled. We prefer to silently succeed in this case, and let the -+ * code path get compiled away. This way, if CONFIG_HWSPINLOCK is not -+ * required on a given setup, users will still work. -+ * -+ * The only exception is hwspin_lock_register/hwspin_lock_unregister, with which -+ * we _do_ want users to fail (no point in registering hwspinlock instances if -+ * the framework is not available). -+ * -+ * Note: ERR_PTR(-ENODEV) will still be considered a success for NULL-checking -+ * users. Others, which care, can still check this with IS_ERR. -+ */ -+static inline struct hwspinlock *hwspin_lock_request(void) -+{ -+ return ERR_PTR(-ENODEV); -+} -+ -+static inline struct hwspinlock *hwspin_lock_request_specific(unsigned int id) -+{ -+ return ERR_PTR(-ENODEV); -+} -+ -+static inline int hwspin_lock_free(struct hwspinlock *hwlock) -+{ -+ return 0; -+} -+ -+static inline -+int __hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int to, -+ int mode, unsigned long *flags) -+{ -+ return 0; -+} -+ -+static inline -+int __hwspin_trylock(struct hwspinlock *hwlock, int mode, unsigned long *flags) -+{ -+ return 0; -+} -+ -+static inline -+void __hwspin_unlock(struct hwspinlock *hwlock, int mode, unsigned long *flags) -+{ -+ return 0; -+} -+ -+static inline int hwspin_lock_get_id(struct hwspinlock *hwlock) -+{ -+ return 0; -+} -+ -+static inline int hwspin_lock_register(struct hwspinlock *hwlock) -+{ -+ return -ENODEV; -+} -+ -+static inline struct hwspinlock *hwspin_lock_unregister(unsigned int id) -+{ -+ return NULL; -+} -+ -+#endif /* !CONFIG_HWSPINLOCK */ -+ -+/** -+ * hwspin_trylock_irqsave() - try to lock an hwspinlock, disable interrupts -+ * @hwlock: an hwspinlock which we want to trylock -+ * @flags: a pointer to where the caller's interrupt state will be saved at -+ * -+ * This function attempts to lock the underlying hwspinlock, and will -+ * immediately fail if the hwspinlock is already locked. -+ * -+ * Upon a successful return from this function, preemption and local -+ * interrupts are disabled (previous interrupts state is saved at @flags), -+ * so the caller must not sleep, and is advised to release the hwspinlock -+ * as soon as possible. -+ * -+ * Returns 0 if we successfully locked the hwspinlock, -EBUSY if -+ * the hwspinlock was already taken, and -EINVAL if @hwlock is invalid. -+ */ -+static inline -+int hwspin_trylock_irqsave(struct hwspinlock *hwlock, unsigned long *flags) -+{ -+ return __hwspin_trylock(hwlock, HWLOCK_IRQSTATE, flags); -+} -+ -+/** -+ * hwspin_trylock_irq() - try to lock an hwspinlock, disable interrupts -+ * @hwlock: an hwspinlock which we want to trylock -+ * -+ * This function attempts to lock the underlying hwspinlock, and will -+ * immediately fail if the hwspinlock is already locked. -+ * -+ * Upon a successful return from this function, preemption and local -+ * interrupts are disabled, so the caller must not sleep, and is advised -+ * to release the hwspinlock as soon as possible. -+ * -+ * Returns 0 if we successfully locked the hwspinlock, -EBUSY if -+ * the hwspinlock was already taken, and -EINVAL if @hwlock is invalid. -+ */ -+static inline int hwspin_trylock_irq(struct hwspinlock *hwlock) -+{ -+ return __hwspin_trylock(hwlock, HWLOCK_IRQ, NULL); -+} -+ -+/** -+ * hwspin_trylock() - attempt to lock a specific hwspinlock -+ * @hwlock: an hwspinlock which we want to trylock -+ * -+ * This function attempts to lock an hwspinlock, and will immediately fail -+ * if the hwspinlock is already taken. -+ * -+ * Upon a successful return from this function, preemption is disabled, -+ * so the caller must not sleep, and is advised to release the hwspinlock -+ * as soon as possible. This is required in order to minimize remote cores -+ * polling on the hardware interconnect. -+ * -+ * Returns 0 if we successfully locked the hwspinlock, -EBUSY if -+ * the hwspinlock was already taken, and -EINVAL if @hwlock is invalid. -+ */ -+static inline int hwspin_trylock(struct hwspinlock *hwlock) -+{ -+ return __hwspin_trylock(hwlock, 0, NULL); -+} -+ -+/** -+ * hwspin_lock_timeout_irqsave() - lock hwspinlock, with timeout, disable irqs -+ * @hwlock: the hwspinlock to be locked -+ * @to: timeout value in msecs -+ * @flags: a pointer to where the caller's interrupt state will be saved at -+ * -+ * This function locks the underlying @hwlock. If the @hwlock -+ * is already taken, the function will busy loop waiting for it to -+ * be released, but give up when @timeout msecs have elapsed. -+ * -+ * Upon a successful return from this function, preemption and local interrupts -+ * are disabled (plus previous interrupt state is saved), so the caller must -+ * not sleep, and is advised to release the hwspinlock as soon as possible. -+ * -+ * Returns 0 when the @hwlock was successfully taken, and an appropriate -+ * error code otherwise (most notably an -ETIMEDOUT if the @hwlock is still -+ * busy after @timeout msecs). The function will never sleep. -+ */ -+static inline int hwspin_lock_timeout_irqsave(struct hwspinlock *hwlock, -+ unsigned int to, unsigned long *flags) -+{ -+ return __hwspin_lock_timeout(hwlock, to, HWLOCK_IRQSTATE, flags); -+} -+ -+/** -+ * hwspin_lock_timeout_irq() - lock hwspinlock, with timeout, disable irqs -+ * @hwlock: the hwspinlock to be locked -+ * @to: timeout value in msecs -+ * -+ * This function locks the underlying @hwlock. If the @hwlock -+ * is already taken, the function will busy loop waiting for it to -+ * be released, but give up when @timeout msecs have elapsed. -+ * -+ * Upon a successful return from this function, preemption and local interrupts -+ * are disabled so the caller must not sleep, and is advised to release the -+ * hwspinlock as soon as possible. -+ * -+ * Returns 0 when the @hwlock was successfully taken, and an appropriate -+ * error code otherwise (most notably an -ETIMEDOUT if the @hwlock is still -+ * busy after @timeout msecs). The function will never sleep. -+ */ -+static inline -+int hwspin_lock_timeout_irq(struct hwspinlock *hwlock, unsigned int to) -+{ -+ return __hwspin_lock_timeout(hwlock, to, HWLOCK_IRQ, NULL); -+} -+ -+/** -+ * hwspin_lock_timeout() - lock an hwspinlock with timeout limit -+ * @hwlock: the hwspinlock to be locked -+ * @to: timeout value in msecs -+ * -+ * This function locks the underlying @hwlock. If the @hwlock -+ * is already taken, the function will busy loop waiting for it to -+ * be released, but give up when @timeout msecs have elapsed. -+ * -+ * Upon a successful return from this function, preemption is disabled -+ * so the caller must not sleep, and is advised to release the hwspinlock -+ * as soon as possible. -+ * This is required in order to minimize remote cores polling on the -+ * hardware interconnect. -+ * -+ * Returns 0 when the @hwlock was successfully taken, and an appropriate -+ * error code otherwise (most notably an -ETIMEDOUT if the @hwlock is still -+ * busy after @timeout msecs). The function will never sleep. -+ */ -+static inline -+int hwspin_lock_timeout(struct hwspinlock *hwlock, unsigned int to) -+{ -+ return __hwspin_lock_timeout(hwlock, to, 0, NULL); -+} -+ -+/** -+ * hwspin_unlock_irqrestore() - unlock hwspinlock, restore irq state -+ * @hwlock: a previously-acquired hwspinlock which we want to unlock -+ * @flags: previous caller's interrupt state to restore -+ * -+ * This function will unlock a specific hwspinlock, enable preemption and -+ * restore the previous state of the local interrupts. It should be used -+ * to undo, e.g., hwspin_trylock_irqsave(). -+ * -+ * @hwlock must be already locked before calling this function: it is a bug -+ * to call unlock on a @hwlock that is already unlocked. -+ */ -+static inline void hwspin_unlock_irqrestore(struct hwspinlock *hwlock, -+ unsigned long *flags) -+{ -+ __hwspin_unlock(hwlock, HWLOCK_IRQSTATE, flags); -+} -+ -+/** -+ * hwspin_unlock_irq() - unlock hwspinlock, enable interrupts -+ * @hwlock: a previously-acquired hwspinlock which we want to unlock -+ * -+ * This function will unlock a specific hwspinlock, enable preemption and -+ * enable local interrupts. Should be used to undo hwspin_lock_irq(). -+ * -+ * @hwlock must be already locked (e.g. by hwspin_trylock_irq()) before -+ * calling this function: it is a bug to call unlock on a @hwlock that is -+ * already unlocked. -+ */ -+static inline void hwspin_unlock_irq(struct hwspinlock *hwlock) -+{ -+ __hwspin_unlock(hwlock, HWLOCK_IRQ, NULL); -+} -+ -+/** -+ * hwspin_unlock() - unlock hwspinlock -+ * @hwlock: a previously-acquired hwspinlock which we want to unlock -+ * -+ * This function will unlock a specific hwspinlock and enable preemption -+ * back. -+ * -+ * @hwlock must be already locked (e.g. by hwspin_trylock()) before calling -+ * this function: it is a bug to call unlock on a @hwlock that is already -+ * unlocked. -+ */ -+static inline void hwspin_unlock(struct hwspinlock *hwlock) -+{ -+ __hwspin_unlock(hwlock, 0, NULL); -+} -+ -+#endif /* __LINUX_HWSPINLOCK_H */ -diff -Naur linux-2.6.38-rc7/include/linux/i2c/twl.h linux-2.6.38-rc7-linux-omap-dss2/include/linux/i2c/twl.h ---- linux-2.6.38-rc7/include/linux/i2c/twl.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/include/linux/i2c/twl.h 2011-03-09 13:19:21.857263241 +0100 -@@ -637,7 +637,6 @@ - extern int twl4030_remove_script(u8 flags); - - struct twl4030_codec_audio_data { -- unsigned int audio_mclk; /* not used, will be removed */ - unsigned int digimic_delay; /* in ms */ - unsigned int ramp_delay_value; - unsigned int offset_cncl_path; -@@ -648,7 +647,6 @@ - }; - - struct twl4030_codec_vibra_data { -- unsigned int audio_mclk; - unsigned int coexist; - }; - -diff -Naur linux-2.6.38-rc7/include/linux/mtd/onenand_regs.h linux-2.6.38-rc7-linux-omap-dss2/include/linux/mtd/onenand_regs.h ---- linux-2.6.38-rc7/include/linux/mtd/onenand_regs.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/include/linux/mtd/onenand_regs.h 2011-03-09 13:19:21.975260847 +0100 -@@ -168,6 +168,7 @@ - #define ONENAND_SYS_CFG1_INT (1 << 6) - #define ONENAND_SYS_CFG1_IOBE (1 << 5) - #define ONENAND_SYS_CFG1_RDY_CONF (1 << 4) -+#define ONENAND_SYS_CFG1_VHF (1 << 3) - #define ONENAND_SYS_CFG1_HF (1 << 2) - #define ONENAND_SYS_CFG1_SYNC_WRITE (1 << 1) - -diff -Naur linux-2.6.38-rc7/MAINTAINERS linux-2.6.38-rc7-linux-omap-dss2/MAINTAINERS ---- linux-2.6.38-rc7/MAINTAINERS 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/MAINTAINERS 2011-03-09 13:19:09.391516121 +0100 -@@ -4504,14 +4504,14 @@ - F: sound/soc/omap/ - - OMAP FRAMEBUFFER SUPPORT --M: Tomi Valkeinen -+M: Tomi Valkeinen - L: linux-fbdev@vger.kernel.org - L: linux-omap@vger.kernel.org - S: Maintained - F: drivers/video/omap/ - - OMAP DISPLAY SUBSYSTEM and FRAMEBUFFER SUPPORT (DSS2) --M: Tomi Valkeinen -+M: Tomi Valkeinen - L: linux-omap@vger.kernel.org - L: linux-fbdev@vger.kernel.org - S: Maintained -diff -Naur linux-2.6.38-rc7/sound/soc/omap/omap-mcbsp.c linux-2.6.38-rc7-linux-omap-dss2/sound/soc/omap/omap-mcbsp.c ---- linux-2.6.38-rc7/sound/soc/omap/omap-mcbsp.c 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/sound/soc/omap/omap-mcbsp.c 2011-03-09 13:19:23.525229402 +0100 -@@ -69,110 +69,6 @@ - */ - static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2]; - --#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) --static const int omap1_dma_reqs[][2] = { -- { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX }, -- { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX }, -- { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX }, --}; --static const unsigned long omap1_mcbsp_port[][2] = { -- { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1, -- OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 }, -- { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1, -- OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 }, -- { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1, -- OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 }, --}; --#else --static const int omap1_dma_reqs[][2] = {}; --static const unsigned long omap1_mcbsp_port[][2] = {}; --#endif -- --#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) --static const int omap24xx_dma_reqs[][2] = { -- { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX }, -- { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX }, --#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) -- { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX }, -- { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX }, -- { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX }, --#endif --}; --#else --static const int omap24xx_dma_reqs[][2] = {}; --#endif -- --#if defined(CONFIG_ARCH_OMAP4) --static const int omap44xx_dma_reqs[][2] = { -- { OMAP44XX_DMA_MCBSP1_TX, OMAP44XX_DMA_MCBSP1_RX }, -- { OMAP44XX_DMA_MCBSP2_TX, OMAP44XX_DMA_MCBSP2_RX }, -- { OMAP44XX_DMA_MCBSP3_TX, OMAP44XX_DMA_MCBSP3_RX }, -- { OMAP44XX_DMA_MCBSP4_TX, OMAP44XX_DMA_MCBSP4_RX }, --}; --#else --static const int omap44xx_dma_reqs[][2] = {}; --#endif -- --#if defined(CONFIG_ARCH_OMAP2420) --static const unsigned long omap2420_mcbsp_port[][2] = { -- { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1, -- OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 }, -- { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1, -- OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 }, --}; --#else --static const unsigned long omap2420_mcbsp_port[][2] = {}; --#endif -- --#if defined(CONFIG_ARCH_OMAP2430) --static const unsigned long omap2430_mcbsp_port[][2] = { -- { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR, -- OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR }, -- { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR, -- OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR }, -- { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR, -- OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR }, -- { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR, -- OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR }, -- { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR, -- OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR }, --}; --#else --static const unsigned long omap2430_mcbsp_port[][2] = {}; --#endif -- --#if defined(CONFIG_ARCH_OMAP3) --static const unsigned long omap34xx_mcbsp_port[][2] = { -- { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR, -- OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR }, -- { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR, -- OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR }, -- { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR, -- OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR }, -- { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR, -- OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR }, -- { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR, -- OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR }, --}; --#else --static const unsigned long omap34xx_mcbsp_port[][2] = {}; --#endif -- --#if defined(CONFIG_ARCH_OMAP4) --static const unsigned long omap44xx_mcbsp_port[][2] = { -- { OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR, -- OMAP44XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR }, -- { OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR, -- OMAP44XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR }, -- { OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR, -- OMAP44XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR }, -- { OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR, -- OMAP44XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR }, --}; --#else --static const unsigned long omap44xx_mcbsp_port[][2] = {}; --#endif -- - static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream) - { - struct snd_soc_pcm_runtime *rtd = substream->private_data; -@@ -346,24 +242,10 @@ - unsigned int format, div, framesize, master; - - dma_data = &omap_mcbsp_dai_dma_params[cpu_dai->id][substream->stream]; -- if (cpu_class_is_omap1()) { -- dma = omap1_dma_reqs[bus_id][substream->stream]; -- port = omap1_mcbsp_port[bus_id][substream->stream]; -- } else if (cpu_is_omap2420()) { -- dma = omap24xx_dma_reqs[bus_id][substream->stream]; -- port = omap2420_mcbsp_port[bus_id][substream->stream]; -- } else if (cpu_is_omap2430()) { -- dma = omap24xx_dma_reqs[bus_id][substream->stream]; -- port = omap2430_mcbsp_port[bus_id][substream->stream]; -- } else if (cpu_is_omap343x()) { -- dma = omap24xx_dma_reqs[bus_id][substream->stream]; -- port = omap34xx_mcbsp_port[bus_id][substream->stream]; -- } else if (cpu_is_omap44xx()) { -- dma = omap44xx_dma_reqs[bus_id][substream->stream]; -- port = omap44xx_mcbsp_port[bus_id][substream->stream]; -- } else { -- return -ENODEV; -- } -+ -+ dma = omap_mcbsp_dma_ch_params(bus_id, substream->stream); -+ port = omap_mcbsp_dma_reg_params(bus_id, substream->stream); -+ - switch (params_format(params)) { - case SNDRV_PCM_FORMAT_S16_LE: - dma_data->data_type = OMAP_DMA_DATA_TYPE_S16; -diff -Naur linux-2.6.38-rc7/sound/soc/omap/omap-mcbsp.h linux-2.6.38-rc7-linux-omap-dss2/sound/soc/omap/omap-mcbsp.h ---- linux-2.6.38-rc7/sound/soc/omap/omap-mcbsp.h 2011-03-01 22:55:12.000000000 +0100 -+++ linux-2.6.38-rc7-linux-omap-dss2/sound/soc/omap/omap-mcbsp.h 2011-03-09 13:19:23.525229402 +0100 -@@ -43,7 +43,7 @@ - OMAP_MCBSP_CLKGDV, /* Sample rate generator divider */ - }; - --#if defined(CONFIG_ARCH_OMAP2420) -+#if defined(CONFIG_SOC_OMAP2420) - #define NUM_LINKS 2 - #endif - #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) -@@ -54,7 +54,7 @@ - #undef NUM_LINKS - #define NUM_LINKS 4 - #endif --#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) -+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_OMAP2430) - #undef NUM_LINKS - #define NUM_LINKS 5 - #endif diff --git a/packages/linux/patches/linux-2.6.38-rc8-301-V5_Add_display_type_HDMI_to_DSS2.patch b/packages/linux/patches/linux-2.6.38-rc8-301-V5_Add_display_type_HDMI_to_DSS2.patch deleted file mode 100644 index 4a2b1280e4..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc8-301-V5_Add_display_type_HDMI_to_DSS2.patch +++ /dev/null @@ -1,123 +0,0 @@ -Adding HDMI type in dss_features , overlay and -the manager so that HDMI type of display will be recognized. - -Signed-off-by: Mythri P K ---- - arch/arm/plat-omap/include/plat/display.h | 1 + - drivers/video/omap2/dss/display.c | 2 ++ - drivers/video/omap2/dss/dss_features.c | 2 +- - drivers/video/omap2/dss/manager.c | 9 +++++++-- - drivers/video/omap2/dss/overlay.c | 6 ++++-- - 5 files changed, 15 insertions(+), 5 deletions(-) - -diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h -index e81ca66..5e04ddc 100644 ---- a/arch/arm/plat-omap/include/plat/display.h -+++ b/arch/arm/plat-omap/include/plat/display.h -@@ -58,6 +58,7 @@ enum omap_display_type { - OMAP_DISPLAY_TYPE_SDI = 1 << 2, - OMAP_DISPLAY_TYPE_DSI = 1 << 3, - OMAP_DISPLAY_TYPE_VENC = 1 << 4, -+ OMAP_DISPLAY_TYPE_HDMI = 1 << 5, - }; - - enum omap_plane { -diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c -index 7d96b72..c40bcbd 100644 ---- a/drivers/video/omap2/dss/display.c -+++ b/drivers/video/omap2/dss/display.c -@@ -342,6 +342,7 @@ int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev) - return 16; - case OMAP_DISPLAY_TYPE_VENC: - case OMAP_DISPLAY_TYPE_SDI: -+ case OMAP_DISPLAY_TYPE_HDMI: - return 24; - default: - BUG(); -@@ -368,6 +369,7 @@ bool dss_use_replication(struct omap_dss_device *dssdev, - case OMAP_DISPLAY_TYPE_DPI: - bpp = dssdev->phy.dpi.data_lines; - break; -+ case OMAP_DISPLAY_TYPE_HDMI: - case OMAP_DISPLAY_TYPE_VENC: - case OMAP_DISPLAY_TYPE_SDI: - bpp = 24; -diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c -index 6eb6ec6..86dc848 100644 ---- a/drivers/video/omap2/dss/dss_features.c -+++ b/drivers/video/omap2/dss/dss_features.c -@@ -115,7 +115,7 @@ static const enum omap_display_type omap4_dss_supported_displays[] = { - OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI, - - /* OMAP_DSS_CHANNEL_DIGIT */ -- OMAP_DISPLAY_TYPE_VENC, -+ OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI, - - /* OMAP_DSS_CHANNEL_LCD2 */ - OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI | -diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c -index 1f53bf2..bcd37ec 100644 ---- a/drivers/video/omap2/dss/manager.c -+++ b/drivers/video/omap2/dss/manager.c -@@ -515,6 +515,8 @@ static int dss_mgr_wait_for_vsync(struct omap_overlay_manager *mgr) - - if (mgr->device->type == OMAP_DISPLAY_TYPE_VENC) { - irq = DISPC_IRQ_EVSYNC_ODD; -+ } else if (mgr->device->type == OMAP_DISPLAY_TYPE_HDMI) { -+ irq = DISPC_IRQ_EVSYNC_EVEN; - } else { - if (mgr->id == OMAP_DSS_CHANNEL_LCD) - irq = DISPC_IRQ_VSYNC; -@@ -536,7 +538,8 @@ static int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr) - if (!dssdev || dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) - return 0; - -- if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) { -+ if (dssdev->type == OMAP_DISPLAY_TYPE_VENC -+ || dssdev->type == OMAP_DISPLAY_TYPE_HDMI) { - irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN; - } else { - if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) { -@@ -613,7 +616,8 @@ int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl) - if (!dssdev || dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) - return 0; - -- if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) { -+ if (dssdev->type == OMAP_DISPLAY_TYPE_VENC -+ || dssdev->type == OMAP_DISPLAY_TYPE_HDMI) { - irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN; - } else { - if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) { -@@ -1377,6 +1381,7 @@ static int omap_dss_mgr_apply(struct omap_overlay_manager *mgr) - case OMAP_DISPLAY_TYPE_DBI: - case OMAP_DISPLAY_TYPE_SDI: - case OMAP_DISPLAY_TYPE_VENC: -+ case OMAP_DISPLAY_TYPE_HDMI: - default_get_overlay_fifo_thresholds(ovl->id, size, - &oc->burst_size, &oc->fifo_low, - &oc->fifo_high); -diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c -index 996e9a4..f1aca6d 100644 ---- a/drivers/video/omap2/dss/overlay.c -+++ b/drivers/video/omap2/dss/overlay.c -@@ -679,7 +679,8 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force) - lcd2_mgr->set_device(lcd2_mgr, dssdev); - mgr = lcd2_mgr; - } -- } else if (dssdev->type != OMAP_DISPLAY_TYPE_VENC) { -+ } else if (dssdev->type != OMAP_DISPLAY_TYPE_VENC -+ && dssdev->type != OMAP_DISPLAY_TYPE_HDMI) { - if (!lcd_mgr->device || force) { - if (lcd_mgr->device) - lcd_mgr->unset_device(lcd_mgr); -@@ -688,7 +689,8 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force) - } - } - -- if (dssdev->type == OMAP_DISPLAY_TYPE_VENC) { -+ if (dssdev->type == OMAP_DISPLAY_TYPE_VENC -+ || dssdev->type == OMAP_DISPLAY_TYPE_HDMI) { - if (!tv_mgr->device || force) { - if (tv_mgr->device) - tv_mgr->unset_device(tv_mgr); --- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-302-V5_Select_between_HDMI_VENC_clock_source.patch b/packages/linux/patches/linux-2.6.38-rc8-302-V5_Select_between_HDMI_VENC_clock_source.patch deleted file mode 100644 index 663f5fe18e..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc8-302-V5_Select_between_HDMI_VENC_clock_source.patch +++ /dev/null @@ -1,47 +0,0 @@ -Signed-off-by: Mythri P K ---- - drivers/video/omap2/dss/dss.c | 5 +++++ - drivers/video/omap2/dss/dss.h | 6 ++++++ - 2 files changed, 11 insertions(+), 0 deletions(-) - -diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c -index aed9345..0be83c8 100644 ---- a/drivers/video/omap2/dss/dss.c -+++ b/drivers/video/omap2/dss/dss.c -@@ -605,6 +605,11 @@ void dss_set_dac_pwrdn_bgz(bool enable) - REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ - } - -+void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi) -+{ -+ REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */ -+} -+ - static int dss_init(void) - { - int r; -diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h -index b845468..c2c0fcf 100644 ---- a/drivers/video/omap2/dss/dss.h -+++ b/drivers/video/omap2/dss/dss.h -@@ -132,6 +132,11 @@ struct dss_clk_source_name { - const char *clksrc_name; - }; - -+enum dss_hdmi_venc_clk_source_select { -+ DSS_VENC_TV_CLK = 0, -+ DSS_HDMI_M_PCLK = 1, -+}; -+ - struct dss_clock_info { - /* rates that we get with dividers below */ - unsigned long fck; -@@ -220,6 +225,7 @@ void dss_recheck_connections(struct omap_dss_device *dssdev, bool force); - int dss_init_platform_driver(void); - void dss_uninit_platform_driver(void); - -+void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select); - void dss_save_context(void); - void dss_restore_context(void); - void dss_clk_enable(enum dss_clock clks); --- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-303-V5_Dispc_gamma_enable_set-reset_function_for_TV.patch b/packages/linux/patches/linux-2.6.38-rc8-303-V5_Dispc_gamma_enable_set-reset_function_for_TV.patch deleted file mode 100644 index 60a995f9e1..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc8-303-V5_Dispc_gamma_enable_set-reset_function_for_TV.patch +++ /dev/null @@ -1,46 +0,0 @@ -Adding function to reset/set gamma table bit for TV interface -currentl only support for disabled is added. - -Signed-off-by: Mythri P K ---- - drivers/video/omap2/dss/dispc.c | 13 +++++++++++++ - drivers/video/omap2/dss/dss.h | 1 + - 2 files changed, 14 insertions(+), 0 deletions(-) - -diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c -index b8c576a..9b86f5f 100644 ---- a/drivers/video/omap2/dss/dispc.c -+++ b/drivers/video/omap2/dss/dispc.c -@@ -1008,6 +1008,19 @@ void dispc_set_burst_size(enum omap_plane plane, - enable_clocks(0); - } - -+void dispc_enable_gamma_table(bool enable) -+{ -+ /* This is partially implemented to support only -+ * disabling of the gamma table. -+ */ -+ if (enable) { -+ DSSWARN("Gamma table enabling for TV not yet supported"); -+ return; -+ } -+ -+ REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9); -+} -+ - static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable) - { - u32 val; -diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h -index c2c0fcf..9f563a6 100644 ---- a/drivers/video/omap2/dss/dss.h -+++ b/drivers/video/omap2/dss/dss.h -@@ -376,6 +376,7 @@ void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height); - void dispc_set_channel_out(enum omap_plane plane, - enum omap_channel channel_out); - -+void dispc_enable_gamma_table(bool enable); - int dispc_setup_plane(enum omap_plane plane, - u32 paddr, u16 screen_width, - u16 pos_x, u16 pos_y, --- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-304-V5_HDMI_driver_header_file_addition.patch b/packages/linux/patches/linux-2.6.38-rc8-304-V5_HDMI_driver_header_file_addition.patch deleted file mode 100644 index 4cde7027ea..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc8-304-V5_HDMI_driver_header_file_addition.patch +++ /dev/null @@ -1,431 +0,0 @@ -Adding the hdmi interface driver header file (hdmi.h) to the dss driver. -Register and structure declaration done here. - -Signed-off-by: Mythri P K ---- - drivers/video/omap2/dss/hdmi.h | 415 ++++++++++++++++++++++++++++++++++++++++ - 1 files changed, 415 insertions(+), 0 deletions(-) - create mode 100644 drivers/video/omap2/dss/hdmi.h - -diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h -new file mode 100644 -index 0000000..9887ab9 ---- /dev/null -+++ b/drivers/video/omap2/dss/hdmi.h -@@ -0,0 +1,415 @@ -+/* -+ * hdmi.h -+ * -+ * HDMI driver definition for TI OMAP4 processors. -+ * -+ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#ifndef _OMAP4_DSS_HDMI_H_ -+#define _OMAP4_DSS_HDMI_H_ -+ -+#include -+#include -+ -+#define HDMI_WP 0x0 -+#define HDMI_CORE_SYS 0x400 -+#define HDMI_CORE_AV 0x900 -+#define HDMI_PLLCTRL 0x200 -+#define HDMI_PHY 0x300 -+ -+struct hdmi_reg { u16 idx; }; -+ -+#define HDMI_REG(idx) ((const struct hdmi_reg) { idx }) -+ -+/* HDMI Wrapper */ -+#define HDMI_WP_REG(idx) HDMI_REG(HDMI_WP + idx) -+ -+#define HDMI_WP_REVISION HDMI_WP_REG(0x0) -+#define HDMI_WP_SYSCONFIG HDMI_WP_REG(0x10) -+#define HDMI_WP_IRQSTATUS_RAW HDMI_WP_REG(0x24) -+#define HDMI_WP_IRQSTATUS HDMI_WP_REG(0x28) -+#define HDMI_WP_PWR_CTRL HDMI_WP_REG(0x40) -+#define HDMI_WP_IRQENABLE_SET HDMI_WP_REG(0x2C) -+#define HDMI_WP_VIDEO_CFG HDMI_WP_REG(0x50) -+#define HDMI_WP_VIDEO_SIZE HDMI_WP_REG(0x60) -+#define HDMI_WP_VIDEO_TIMING_H HDMI_WP_REG(0x68) -+#define HDMI_WP_VIDEO_TIMING_V HDMI_WP_REG(0x6C) -+#define HDMI_WP_WP_CLK HDMI_WP_REG(0x70) -+ -+/* HDMI IP Core System */ -+#define HDMI_CORE_SYS_REG(idx) HDMI_REG(HDMI_CORE_SYS + idx) -+ -+#define HDMI_CORE_SYS_VND_IDL HDMI_CORE_SYS_REG(0x0) -+#define HDMI_CORE_SYS_DEV_IDL HDMI_CORE_SYS_REG(0x8) -+#define HDMI_CORE_SYS_DEV_IDH HDMI_CORE_SYS_REG(0xC) -+#define HDMI_CORE_SYS_DEV_REV HDMI_CORE_SYS_REG(0x10) -+#define HDMI_CORE_SYS_SRST HDMI_CORE_SYS_REG(0x14) -+#define HDMI_CORE_CTRL1 HDMI_CORE_SYS_REG(0x20) -+#define HDMI_CORE_SYS_SYS_STAT HDMI_CORE_SYS_REG(0x24) -+#define HDMI_CORE_SYS_VID_ACEN HDMI_CORE_SYS_REG(0x124) -+#define HDMI_CORE_SYS_VID_MODE HDMI_CORE_SYS_REG(0x128) -+#define HDMI_CORE_SYS_INTR_STATE HDMI_CORE_SYS_REG(0x1C0) -+#define HDMI_CORE_SYS_INTR1 HDMI_CORE_SYS_REG(0x1C4) -+#define HDMI_CORE_SYS_INTR2 HDMI_CORE_SYS_REG(0x1C8) -+#define HDMI_CORE_SYS_INTR3 HDMI_CORE_SYS_REG(0x1CC) -+#define HDMI_CORE_SYS_INTR4 HDMI_CORE_SYS_REG(0x1D0) -+#define HDMI_CORE_SYS_UMASK1 HDMI_CORE_SYS_REG(0x1D4) -+#define HDMI_CORE_SYS_TMDS_CTRL HDMI_CORE_SYS_REG(0x208) -+#define HDMI_CORE_SYS_DE_DLY HDMI_CORE_SYS_REG(0xC8) -+#define HDMI_CORE_SYS_DE_CTRL HDMI_CORE_SYS_REG(0xCC) -+#define HDMI_CORE_SYS_DE_TOP HDMI_CORE_SYS_REG(0xD0) -+#define HDMI_CORE_SYS_DE_CNTL HDMI_CORE_SYS_REG(0xD8) -+#define HDMI_CORE_SYS_DE_CNTH HDMI_CORE_SYS_REG(0xDC) -+#define HDMI_CORE_SYS_DE_LINL HDMI_CORE_SYS_REG(0xE0) -+#define HDMI_CORE_SYS_DE_LINH_1 HDMI_CORE_SYS_REG(0xE4) -+#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1 -+#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1 -+#define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1 -+#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1 -+ -+/* HDMI DDC E-DID */ -+#define HDMI_CORE_DDC_CMD HDMI_CORE_SYS_REG(0x3CC) -+#define HDMI_CORE_DDC_STATUS HDMI_CORE_SYS_REG(0x3C8) -+#define HDMI_CORE_DDC_ADDR HDMI_CORE_SYS_REG(0x3B4) -+#define HDMI_CORE_DDC_OFFSET HDMI_CORE_SYS_REG(0x3BC) -+#define HDMI_CORE_DDC_COUNT1 HDMI_CORE_SYS_REG(0x3C0) -+#define HDMI_CORE_DDC_COUNT2 HDMI_CORE_SYS_REG(0x3C4) -+#define HDMI_CORE_DDC_DATA HDMI_CORE_SYS_REG(0x3D0) -+#define HDMI_CORE_DDC_SEGM HDMI_CORE_SYS_REG(0x3B8) -+ -+/* HDMI IP Core Audio Video */ -+#define HDMI_CORE_AV_REG(idx) HDMI_REG(HDMI_CORE_AV + idx) -+ -+#define HDMI_CORE_AV_HDMI_CTRL HDMI_CORE_AV_REG(0xBC) -+#define HDMI_CORE_AV_DPD HDMI_CORE_AV_REG(0xF4) -+#define HDMI_CORE_AV_PB_CTRL1 HDMI_CORE_AV_REG(0xF8) -+#define HDMI_CORE_AV_PB_CTRL2 HDMI_CORE_AV_REG(0xFC) -+#define HDMI_CORE_AV_AVI_TYPE HDMI_CORE_AV_REG(0x100) -+#define HDMI_CORE_AV_AVI_VERS HDMI_CORE_AV_REG(0x104) -+#define HDMI_CORE_AV_AVI_LEN HDMI_CORE_AV_REG(0x108) -+#define HDMI_CORE_AV_AVI_CHSUM HDMI_CORE_AV_REG(0x10C) -+#define HDMI_CORE_AV_AVI_DBYTE(n) HDMI_CORE_AV_REG(n * 4 + 0x110) -+#define HDMI_CORE_AV_AVI_DBYTE_NELEMS HDMI_CORE_AV_REG(15) -+#define HDMI_CORE_AV_SPD_DBYTE HDMI_CORE_AV_REG(0x190) -+#define HDMI_CORE_AV_SPD_DBYTE_NELEMS HDMI_CORE_AV_REG(27) -+#define HDMI_CORE_AV_MPEG_DBYTE HDMI_CORE_AV_REG(0x290) -+#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS HDMI_CORE_AV_REG(27) -+#define HDMI_CORE_AV_GEN_DBYTE HDMI_CORE_AV_REG(0x300) -+#define HDMI_CORE_AV_GEN_DBYTE_NELEMS HDMI_CORE_AV_REG(31) -+#define HDMI_CORE_AV_GEN2_DBYTE HDMI_CORE_AV_REG(0x380) -+#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS HDMI_CORE_AV_REG(31) -+#define HDMI_CORE_AV_ACR_CTRL HDMI_CORE_AV_REG(0x4) -+#define HDMI_CORE_AV_FREQ_SVAL HDMI_CORE_AV_REG(0x8) -+#define HDMI_CORE_AV_N_SVAL1 HDMI_CORE_AV_REG(0xC) -+#define HDMI_CORE_AV_N_SVAL2 HDMI_CORE_AV_REG(0x10) -+#define HDMI_CORE_AV_N_SVAL3 HDMI_CORE_AV_REG(0x14) -+#define HDMI_CORE_AV_CTS_SVAL1 HDMI_CORE_AV_REG(0x18) -+#define HDMI_CORE_AV_CTS_SVAL2 HDMI_CORE_AV_REG(0x1C) -+#define HDMI_CORE_AV_CTS_SVAL3 HDMI_CORE_AV_REG(0x20) -+#define HDMI_CORE_AV_CTS_HVAL1 HDMI_CORE_AV_REG(0x24) -+#define HDMI_CORE_AV_CTS_HVAL2 HDMI_CORE_AV_REG(0x28) -+#define HDMI_CORE_AV_CTS_HVAL3 HDMI_CORE_AV_REG(0x2C) -+#define HDMI_CORE_AV_AUD_MODE HDMI_CORE_AV_REG(0x50) -+#define HDMI_CORE_AV_SPDIF_CTRL HDMI_CORE_AV_REG(0x54) -+#define HDMI_CORE_AV_HW_SPDIF_FS HDMI_CORE_AV_REG(0x60) -+#define HDMI_CORE_AV_SWAP_I2S HDMI_CORE_AV_REG(0x64) -+#define HDMI_CORE_AV_SPDIF_ERTH HDMI_CORE_AV_REG(0x6C) -+#define HDMI_CORE_AV_I2S_IN_MAP HDMI_CORE_AV_REG(0x70) -+#define HDMI_CORE_AV_I2S_IN_CTRL HDMI_CORE_AV_REG(0x74) -+#define HDMI_CORE_AV_I2S_CHST0 HDMI_CORE_AV_REG(0x78) -+#define HDMI_CORE_AV_I2S_CHST1 HDMI_CORE_AV_REG(0x7C) -+#define HDMI_CORE_AV_I2S_CHST2 HDMI_CORE_AV_REG(0x80) -+#define HDMI_CORE_AV_I2S_CHST4 HDMI_CORE_AV_REG(0x84) -+#define HDMI_CORE_AV_I2S_CHST5 HDMI_CORE_AV_REG(0x88) -+#define HDMI_CORE_AV_ASRC HDMI_CORE_AV_REG(0x8C) -+#define HDMI_CORE_AV_I2S_IN_LEN HDMI_CORE_AV_REG(0x90) -+#define HDMI_CORE_AV_HDMI_CTRL HDMI_CORE_AV_REG(0xBC) -+#define HDMI_CORE_AV_AUDO_TXSTAT HDMI_CORE_AV_REG(0xC0) -+#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 HDMI_CORE_AV_REG(0xCC) -+#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 HDMI_CORE_AV_REG(0xD0) -+#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 HDMI_CORE_AV_REG(0xD4) -+#define HDMI_CORE_AV_TEST_TXCTRL HDMI_CORE_AV_REG(0xF0) -+#define HDMI_CORE_AV_DPD HDMI_CORE_AV_REG(0xF4) -+#define HDMI_CORE_AV_PB_CTRL1 HDMI_CORE_AV_REG(0xF8) -+#define HDMI_CORE_AV_PB_CTRL2 HDMI_CORE_AV_REG(0xFC) -+#define HDMI_CORE_AV_AVI_TYPE HDMI_CORE_AV_REG(0x100) -+#define HDMI_CORE_AV_AVI_VERS HDMI_CORE_AV_REG(0x104) -+#define HDMI_CORE_AV_AVI_LEN HDMI_CORE_AV_REG(0x108) -+#define HDMI_CORE_AV_AVI_CHSUM HDMI_CORE_AV_REG(0x10C) -+#define HDMI_CORE_AV_SPD_TYPE HDMI_CORE_AV_REG(0x180) -+#define HDMI_CORE_AV_SPD_VERS HDMI_CORE_AV_REG(0x184) -+#define HDMI_CORE_AV_SPD_LEN HDMI_CORE_AV_REG(0x188) -+#define HDMI_CORE_AV_SPD_CHSUM HDMI_CORE_AV_REG(0x18C) -+#define HDMI_CORE_AV_MPEG_TYPE HDMI_CORE_AV_REG(0x280) -+#define HDMI_CORE_AV_MPEG_VERS HDMI_CORE_AV_REG(0x284) -+#define HDMI_CORE_AV_MPEG_LEN HDMI_CORE_AV_REG(0x288) -+#define HDMI_CORE_AV_MPEG_CHSUM HDMI_CORE_AV_REG(0x28C) -+#define HDMI_CORE_AV_CP_BYTE1 HDMI_CORE_AV_REG(0x37C) -+#define HDMI_CORE_AV_CEC_ADDR_ID HDMI_CORE_AV_REG(0x3FC) -+#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4 -+#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4 -+#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4 -+#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE 0x4 -+ -+/* PLL */ -+#define HDMI_PLL_REG(idx) HDMI_REG(HDMI_PLLCTRL + idx) -+ -+#define PLLCTRL_PLL_CONTROL HDMI_PLL_REG(0x0) -+#define PLLCTRL_PLL_STATUS HDMI_PLL_REG(0x4) -+#define PLLCTRL_PLL_GO HDMI_PLL_REG(0x8) -+#define PLLCTRL_CFG1 HDMI_PLL_REG(0xC) -+#define PLLCTRL_CFG2 HDMI_PLL_REG(0x10) -+#define PLLCTRL_CFG3 HDMI_PLL_REG(0x14) -+#define PLLCTRL_CFG4 HDMI_PLL_REG(0x20) -+ -+/* HDMI PHY */ -+#define HDMI_PHY_REG(idx) HDMI_REG(HDMI_PHY + idx) -+ -+#define HDMI_TXPHY_TX_CTRL HDMI_PHY_REG(0x0) -+#define HDMI_TXPHY_DIGITAL_CTRL HDMI_PHY_REG(0x4) -+#define HDMI_TXPHY_POWER_CTRL HDMI_PHY_REG(0x8) -+#define HDMI_TXPHY_PAD_CFG_CTRL HDMI_PHY_REG(0xC) -+ -+/* HDMI EDID Length */ -+#define HDMI_EDID_MAX_LENGTH 256 -+#define EDID_TIMING_DESCRIPTOR_SIZE 0x12 -+#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 -+#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 -+#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 -+#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 -+ -+#define OMAP_HDMI_TIMINGS_NB 34 -+ -+#define REG_FLD_MOD(idx, val, start, end) \ -+ hdmi_write_reg(idx, FLD_MOD(hdmi_read_reg(idx), val, start, end)) -+#define REG_GET(idx, start, end) \ -+ FLD_GET(hdmi_read_reg(idx), start, end) -+ -+/* HDMI timing structure */ -+struct hdmi_timings { -+ struct omap_video_timings timings; -+ int vsync_pol; -+ int hsync_pol; -+}; -+ -+enum hdmi_phy_pwr { -+ HDMI_PHYPWRCMD_OFF = 0, -+ HDMI_PHYPWRCMD_LDOON = 1, -+ HDMI_PHYPWRCMD_TXON = 2 -+}; -+ -+enum hdmi_pll_pwr { -+ HDMI_PLLPWRCMD_ALLOFF = 0, -+ HDMI_PLLPWRCMD_PLLONLY = 1, -+ HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2, -+ HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 -+}; -+ -+enum hdmi_clk_refsel { -+ HDMI_REFSEL_PCLK = 0, -+ HDMI_REFSEL_REF1 = 1, -+ HDMI_REFSEL_REF2 = 2, -+ HDMI_REFSEL_SYSCLK = 3 -+}; -+ -+enum hdmi_core_inputbus_width { -+ HDMI_INPUT_8BIT = 0, -+ HDMI_INPUT_10BIT = 1, -+ HDMI_INPUT_12BIT = 2 -+}; -+ -+enum hdmi_core_dither_trunc { -+ HDMI_OUTPUTTRUNCATION_8BIT = 0, -+ HDMI_OUTPUTTRUNCATION_10BIT = 1, -+ HDMI_OUTPUTTRUNCATION_12BIT = 2, -+ HDMI_OUTPUTDITHER_8BIT = 3, -+ HDMI_OUTPUTDITHER_10BIT = 4, -+ HDMI_OUTPUTDITHER_12BIT = 5 -+}; -+ -+enum hdmi_core_deepcolor_ed { -+ HDMI_DEEPCOLORPACKECTDISABLE = 0, -+ HDMI_DEEPCOLORPACKECTENABLE = 1 -+}; -+ -+enum hdmi_core_packet_mode { -+ HDMI_PACKETMODERESERVEDVALUE = 0, -+ HDMI_PACKETMODE24BITPERPIXEL = 4, -+ HDMI_PACKETMODE30BITPERPIXEL = 5, -+ HDMI_PACKETMODE36BITPERPIXEL = 6, -+ HDMI_PACKETMODE48BITPERPIXEL = 7 -+}; -+ -+enum hdmi_core_hdmi_dvi { -+ HDMI_DVI = 0, -+ HDMI_HDMI = 1 -+}; -+ -+enum hdmi_core_tclkselclkmult { -+ HDMI_FPLL05IDCK = 0, -+ HDMI_FPLL10IDCK = 1, -+ HDMI_FPLL20IDCK = 2, -+ HDMI_FPLL40IDCK = 3 -+}; -+ -+enum hdmi_core_packet_ctrl { -+ HDMI_PACKETENABLE = 1, -+ HDMI_PACKETDISABLE = 0, -+ HDMI_PACKETREPEATON = 1, -+ HDMI_PACKETREPEATOFF = 0 -+}; -+ -+/* INFOFRAME_AVI_ definitions */ -+enum hdmi_core_infoframe { -+ HDMI_INFOFRAME_AVI_DB1Y_RGB = 0, -+ HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1, -+ HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2, -+ HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0, -+ HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1, -+ HDMI_INFOFRAME_AVI_DB1B_NO = 0, -+ HDMI_INFOFRAME_AVI_DB1B_VERT = 1, -+ HDMI_INFOFRAME_AVI_DB1B_HORI = 2, -+ HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3, -+ HDMI_INFOFRAME_AVI_DB1S_0 = 0, -+ HDMI_INFOFRAME_AVI_DB1S_1 = 1, -+ HDMI_INFOFRAME_AVI_DB1S_2 = 2, -+ HDMI_INFOFRAME_AVI_DB2C_NO = 0, -+ HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1, -+ HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2, -+ HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3, -+ HDMI_INFOFRAME_AVI_DB2M_NO = 0, -+ HDMI_INFOFRAME_AVI_DB2M_43 = 1, -+ HDMI_INFOFRAME_AVI_DB2M_169 = 2, -+ HDMI_INFOFRAME_AVI_DB2R_SAME = 8, -+ HDMI_INFOFRAME_AVI_DB2R_43 = 9, -+ HDMI_INFOFRAME_AVI_DB2R_169 = 10, -+ HDMI_INFOFRAME_AVI_DB2R_149 = 11, -+ HDMI_INFOFRAME_AVI_DB3ITC_NO = 0, -+ HDMI_INFOFRAME_AVI_DB3ITC_YES = 1, -+ HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0, -+ HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1, -+ HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0, -+ HDMI_INFOFRAME_AVI_DB3Q_LR = 1, -+ HDMI_INFOFRAME_AVI_DB3Q_FR = 2, -+ HDMI_INFOFRAME_AVI_DB3SC_NO = 0, -+ HDMI_INFOFRAME_AVI_DB3SC_HORI = 1, -+ HDMI_INFOFRAME_AVI_DB3SC_VERT = 2, -+ HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3, -+ HDMI_INFOFRAME_AVI_DB5PR_NO = 0, -+ HDMI_INFOFRAME_AVI_DB5PR_2 = 1, -+ HDMI_INFOFRAME_AVI_DB5PR_3 = 2, -+ HDMI_INFOFRAME_AVI_DB5PR_4 = 3, -+ HDMI_INFOFRAME_AVI_DB5PR_5 = 4, -+ HDMI_INFOFRAME_AVI_DB5PR_6 = 5, -+ HDMI_INFOFRAME_AVI_DB5PR_7 = 6, -+ HDMI_INFOFRAME_AVI_DB5PR_8 = 7, -+ HDMI_INFOFRAME_AVI_DB5PR_9 = 8, -+ HDMI_INFOFRAME_AVI_DB5PR_10 = 9 -+}; -+ -+enum hdmi_packing_mode { -+ HDMI_PACK_10b_RGB_YUV444 = 0, -+ HDMI_PACK_24b_RGB_YUV444_YUV422 = 1, -+ HDMI_PACK_20b_YUV422 = 2, -+ HDMI_PACK_ALREADYPACKED = 7 -+}; -+ -+struct hdmi_core_video_config { -+ enum hdmi_core_inputbus_width ip_bus_width; -+ enum hdmi_core_dither_trunc op_dither_truc; -+ enum hdmi_core_deepcolor_ed deep_color_pkt; -+ enum hdmi_core_packet_mode pkt_mode; -+ enum hdmi_core_hdmi_dvi hdmi_dvi; -+ enum hdmi_core_tclkselclkmult tclk_sel_clkmult; -+}; -+ -+/* -+ * Refer to section 8.2 in HDMI 1.3 specification for -+ * details about infoframe databytes -+ */ -+struct hdmi_core_infoframe_avi { -+ u8 db1_format; -+ /* Y0, Y1 rgb,yCbCr */ -+ u8 db1_active_info; -+ /* A0 Active information Present */ -+ u8 db1_bar_info_dv; -+ /* B0, B1 Bar info data valid */ -+ u8 db1_scan_info; -+ /* S0, S1 scan information */ -+ u8 db2_colorimetry; -+ /* C0, C1 colorimetry */ -+ u8 db2_aspect_ratio; -+ /* M0, M1 Aspect ratio (4:3, 16:9) */ -+ u8 db2_active_fmt_ar; -+ /* R0...R3 Active format aspect ratio */ -+ u8 db3_itc; -+ /* ITC IT content. */ -+ u8 db3_ec; -+ /* EC0, EC1, EC2 Extended colorimetry */ -+ u8 db3_q_range; -+ /* Q1, Q0 Quantization range */ -+ u8 db3_nup_scaling; -+ /* SC1, SC0 Non-uniform picture scaling */ -+ u8 db4_videocode; -+ /* VIC0..6 Video format identification */ -+ u8 db5_pixel_repeat; -+ /* PR0..PR3 Pixel repetition factor */ -+ u16 db6_7_line_eoftop; -+ /* Line number end of top bar */ -+ u16 db8_9_line_sofbottom; -+ /* Line number start of bottom bar */ -+ u16 db10_11_pixel_eofleft; -+ /* Pixel number end of left bar */ -+ u16 db12_13_pixel_sofright; -+ /* Pixel number start of right bar */ -+}; -+ -+struct hdmi_core_packet_enable_repeat { -+ u32 audio_pkt; -+ u32 audio_pkt_repeat; -+ u32 avi_infoframe; -+ u32 avi_infoframe_repeat; -+ u32 gen_cntrl_pkt; -+ u32 gen_cntrl_pkt_repeat; -+ u32 generic_pkt; -+ u32 generic_pkt_repeat; -+}; -+ -+struct hdmi_video_format { -+ enum hdmi_packing_mode packing_mode; -+ u32 y_res; /* Line per panel */ -+ u32 x_res; /* pixel per line */ -+}; -+ -+struct hdmi_video_interface { -+ int vsp; /* Vsync polarity */ -+ int hsp; /* Hsync polarity */ -+ int interlacing; -+ int tm; /* Timing mode */ -+}; -+ -+struct hdmi_cm { -+ int code; -+ int mode; -+}; -+ -+struct hdmi_config { -+ struct hdmi_timings timings; -+ u16 interlace; -+ struct hdmi_cm cm; -+}; -+ -+#endif --- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-305-V5_HDMI_driver_addition_in_the_DSS.patch b/packages/linux/patches/linux-2.6.38-rc8-305-V5_HDMI_driver_addition_in_the_DSS.patch deleted file mode 100644 index 37d58f9b98..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc8-305-V5_HDMI_driver_addition_in_the_DSS.patch +++ /dev/null @@ -1,1418 +0,0 @@ -Adding the hdmi interface driver(hdmi.c) to the dss driver. -It configures the audio and video portion of HDMI based on -functionality called by the panel driver. - -Signed-off-by: Mythri P K - Yong Zhi ---- - drivers/video/omap2/dss/display.c | 3 + - drivers/video/omap2/dss/dss.h | 34 + - drivers/video/omap2/dss/hdmi.c | 1332 +++++++++++++++++++++++++++++++++++++ - 3 files changed, 1369 insertions(+), 0 deletions(-) - create mode 100644 drivers/video/omap2/dss/hdmi.c - -diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c -index c40bcbd..a85a6f3 100644 ---- a/drivers/video/omap2/dss/display.c -+++ b/drivers/video/omap2/dss/display.c -@@ -418,6 +418,9 @@ void dss_init_device(struct platform_device *pdev, - r = dsi_init_display(dssdev); - break; - #endif -+ case OMAP_DISPLAY_TYPE_HDMI: -+ r = hdmi_init_display(dssdev); -+ break; - default: - DSSERR("Support for display '%s' not compiled in.\n", - dssdev->name); -diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h -index 9f563a6..6bf923c 100644 ---- a/drivers/video/omap2/dss/dss.h -+++ b/drivers/video/omap2/dss/dss.h -@@ -179,6 +179,16 @@ struct dsi_clock_info { - bool use_sys_clk; - }; - -+/* HDMI PLL structure */ -+struct hdmi_pll_info { -+ u16 regn; -+ u16 regm; -+ u32 regmf; -+ u16 regm2; -+ u16 regsd; -+ u16 dcofreq; -+}; -+ - struct seq_file; - struct platform_device; - -@@ -450,6 +460,30 @@ static inline void venc_uninit_platform_driver(void) - } - #endif - -+/* HDMI */ -+#ifdef CONFIG_OMAP4_DSS_HDMI -+int hdmi_init_platform_driver(void); -+void hdmi_uninit_platform_driver(void); -+int hdmi_init_display(struct omap_dss_device *dssdev); -+#else -+static inline int hdmi_init_display(struct omap_dss_device *dssdev) -+{ -+ return 0; -+} -+static inline int hdmi_init_platform_driver(void) -+{ -+ return 0; -+} -+static inline void hdmi_uninit_platform_driver(void) -+{ -+} -+#endif -+int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev); -+void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev); -+void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev); -+int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, -+ struct omap_video_timings *timings); -+ - /* RFBI */ - #ifdef CONFIG_OMAP2_DSS_RFBI - int rfbi_init_platform_driver(void); -diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c -new file mode 100644 -index 0000000..e0e2cbb ---- /dev/null -+++ b/drivers/video/omap2/dss/hdmi.c -@@ -0,0 +1,1332 @@ -+/* -+ * hdmi.c -+ * -+ * HDMI interface DSS driver setting for TI's OMAP4 family of processor. -+ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ -+ * Authors: Yong Zhi -+ * Mythri pk -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#define DSS_SUBSYS_NAME "HDMI" -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "dss.h" -+#include "hdmi.h" -+ -+static struct { -+ struct mutex lock; -+ struct omap_display_platform_data *pdata; -+ struct platform_device *pdev; -+ void __iomem *base_wp; /* HDMI wrapper */ -+ int code; -+ int mode; -+ u8 edid[HDMI_EDID_MAX_LENGTH]; -+ u8 edid_set; -+ bool custom_set; -+ struct hdmi_config cfg; -+} hdmi; -+ -+/* -+ * Logic for the below structure : -+ * user enters the CEA or VESA timings by specifying the HDMI/DVI code. -+ * There is a correspondence between CEA/VESA timing and code , Please -+ * refer to section 6.3 in HDMI 1.3 specification for timing code. -+ * In the below structure, cea_vesa_timings corresponds to all OMAP4 -+ * supported CEA and VESA timing values. -+ * code_cea corresponds to the CEA code , It is used to get the timing -+ * from cea_vesa_timing array. Similarly with code_vesa. -+ * code_index is used for back mapping, That is once EDID is read from -+ * the TV, EDID is parsed to find the timing values and then map it to -+ * corresponding CEA or VESA index. -+ */ -+ -+static const struct hdmi_timings cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = { -+ { {640, 480, 25200, 96, 16, 48, 2, 10, 33} , 0 , 0}, -+ { {1280, 720, 74250, 40, 440, 220, 5, 5, 20}, 1, 1}, -+ { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1}, -+ { {720, 480, 27027, 62, 16, 60, 6, 9, 30}, 0, 0}, -+ { {2880, 576, 108000, 256, 48, 272, 5, 5, 39}, 0, 0}, -+ { {1440, 240, 27027, 124, 38, 114, 3, 4, 15}, 0, 0}, -+ { {1440, 288, 27000, 126, 24, 138, 3, 2, 19}, 0, 0}, -+ { {1920, 540, 74250, 44, 528, 148, 5, 2, 15}, 1, 1}, -+ { {1920, 540, 74250, 44, 88, 148, 5, 2, 15}, 1, 1}, -+ { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36}, 1, 1}, -+ { {720, 576, 27000, 64, 12, 68, 5, 5, 39}, 0, 0}, -+ { {1440, 576, 54000, 128, 24, 136, 5, 5, 39}, 0, 0}, -+ { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36}, 1, 1}, -+ { {2880, 480, 108108, 248, 64, 240, 6, 9, 30}, 0, 0}, -+ { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36}, 1, 1}, -+ /* VESA From Here */ -+ { {640, 480, 25175, 96, 16, 48, 2 , 11, 31}, 0, 0}, -+ { {800, 600, 40000, 128, 40, 88, 4 , 1, 23}, 1, 1}, -+ { {848, 480, 33750, 112, 16, 112, 8 , 6, 23}, 1, 1}, -+ { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20}, 1, 0}, -+ { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, 1, 0}, -+ { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18}, 1, 1}, -+ { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36}, 1, 1}, -+ { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38}, 1, 1}, -+ { {1024, 768, 65000, 136, 24, 160, 6, 3, 29}, 0, 0}, -+ { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32}, 1, 0}, -+ { {1440, 900, 106500, 152, 80, 232, 6, 3, 25}, 1, 0}, -+ { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30}, 1, 0}, -+ { {1366, 768, 85500, 143, 70, 213, 3, 3, 24}, 1, 1}, -+ { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36}, 1, 1}, -+ { {1280, 768, 68250, 32, 48, 80, 7, 3, 12}, 0, 1}, -+ { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23}, 0, 1}, -+ { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21}, 0, 1}, -+ { {1280, 800, 79500, 32, 48, 80, 6, 3, 14}, 0, 1}, -+ { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1} -+}; -+ -+/* -+ * This is a static mapping array which maps the timing values -+ * with corresponding CEA / VESA code -+ */ -+static const int code_index[OMAP_HDMI_TIMINGS_NB] = { -+ 1, 19, 4, 2, 37, 6, 21, 20, 5, 16, 17, 29, 31, 35, 32, -+ /* <--15 CEA 17--> vesa*/ -+ 4, 9, 0xE, 0x17, 0x1C, 0x27, 0x20, 0x23, 0x10, 0x2A, -+ 0X2F, 0x3A, 0X51, 0X52, 0x16, 0x29, 0x39, 0x1B -+}; -+ -+/* -+ * This is reverse static mapping which maps the CEA / VESA code -+ * to the corresponding timing values -+ */ -+static const int code_cea[39] = { -+ -1, 0, 3, 3, 2, 8, 5, 5, -1, -1, -+ -1, -1, -1, -1, -1, -1, 9, 10, 10, 1, -+ 7, 6, 6, -1, -1, -1, -1, -1, -1, 11, -+ 11, 12, 14, -1, -1, 13, 13, 4, 4 -+}; -+ -+static const int code_vesa[85] = { -+ -1, -1, -1, -1, 15, -1, -1, -1, -1, 16, -+ -1, -1, -1, -1, 17, -1, 23, -1, -1, -1, -+ -1, -1, 29, 18, -1, -1, -1, 32, 19, -1, -+ -1, -1, 21, -1, -1, 22, -1, -1, -1, 20, -+ -1, 30, 24, -1, -1, -1, -1, 25, -1, -1, -+ -1, -1, -1, -1, -1, -1, -1, 31, 26, -1, -+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -+ -1, 27, 28, -1, 33}; -+ -+static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0}; -+ -+static inline void hdmi_write_reg(const struct hdmi_reg idx, u32 val) -+{ -+ __raw_writel(val, hdmi.base_wp + idx.idx); -+} -+ -+static inline u32 hdmi_read_reg(const struct hdmi_reg idx) -+{ -+ return __raw_readl(hdmi.base_wp + idx.idx); -+} -+ -+static inline int hdmi_wait_for_bit_change(const struct hdmi_reg idx, -+ int b2, int b1, u32 val) -+{ -+ u32 t = 0; -+ while (val != REG_GET(idx, b2, b1)) { -+ udelay(1); -+ if (t++ > 10000) -+ return !val; -+ } -+ return val; -+} -+ -+int hdmi_init_display(struct omap_dss_device *dssdev) -+{ -+ DSSDBG("init_display\n"); -+ -+ return 0; -+} -+ -+static int hdmi_pll_init(enum hdmi_clk_refsel refsel, int dcofreq, -+ struct hdmi_pll_info *fmt, u16 sd) -+{ -+ u32 r; -+ -+ /* PLL start always use manual mode */ -+ REG_FLD_MOD(PLLCTRL_PLL_CONTROL, 0x0, 0, 0); -+ -+ r = hdmi_read_reg(PLLCTRL_CFG1); -+ r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */ -+ r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */ -+ -+ hdmi_write_reg(PLLCTRL_CFG1, r); -+ -+ r = hdmi_read_reg(PLLCTRL_CFG2); -+ -+ r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */ -+ r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */ -+ r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */ -+ -+ if (dcofreq) { -+ /* divider programming for frequency beyond 1000Mhz */ -+ REG_FLD_MOD(PLLCTRL_CFG3, sd, 17, 10); -+ r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */ -+ } else { -+ r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */ -+ } -+ -+ hdmi_write_reg(PLLCTRL_CFG2, r); -+ -+ r = hdmi_read_reg(PLLCTRL_CFG4); -+ r = FLD_MOD(r, fmt->regm2, 24, 18); -+ r = FLD_MOD(r, fmt->regmf, 17, 0); -+ -+ hdmi_write_reg(PLLCTRL_CFG4, r); -+ -+ /* go now */ -+ REG_FLD_MOD(PLLCTRL_PLL_GO, 0x1, 0, 0); -+ -+ /* wait for bit change */ -+ if (hdmi_wait_for_bit_change(PLLCTRL_PLL_GO, 0, 0, 1) != 1) { -+ DSSERR("PLL GO bit not set\n"); -+ return -ETIMEDOUT; -+ } -+ -+ /* Wait till the lock bit is set in PLL status */ -+ if (hdmi_wait_for_bit_change(PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) { -+ DSSWARN("cannot lock PLL\n"); -+ DSSWARN("CFG1 0x%x\n", -+ hdmi_read_reg(PLLCTRL_CFG1)); -+ DSSWARN("CFG2 0x%x\n", -+ hdmi_read_reg(PLLCTRL_CFG2)); -+ DSSWARN("CFG4 0x%x\n", -+ hdmi_read_reg(PLLCTRL_CFG4)); -+ return -ETIMEDOUT; -+ } -+ -+ DSSDBG("PLL locked!\n"); -+ -+ return 0; -+} -+ -+/* PHY_PWR_CMD */ -+static int hdmi_set_phy_pwr(enum hdmi_phy_pwr val) -+{ -+ /* Command for power control of HDMI PHY */ -+ REG_FLD_MOD(HDMI_WP_PWR_CTRL, val, 7, 6); -+ -+ /* Status of the power control of HDMI PHY */ -+ if (hdmi_wait_for_bit_change(HDMI_WP_PWR_CTRL, 5, 4, val) != val) { -+ DSSERR("Failed to set PHY power mode to %d\n", val); -+ return -ETIMEDOUT; -+ } -+ -+ return 0; -+} -+ -+/* PLL_PWR_CMD */ -+static int hdmi_set_pll_pwr(enum hdmi_pll_pwr val) -+{ -+ /* Command for power control of HDMI PLL */ -+ REG_FLD_MOD(HDMI_WP_PWR_CTRL, val, 3, 2); -+ -+ /* wait till PHY_PWR_STATUS is set */ -+ if (hdmi_wait_for_bit_change(HDMI_WP_PWR_CTRL, 1, 0, val) != val) { -+ DSSERR("Failed to set PHY_PWR_STATUS\n"); -+ return -ETIMEDOUT; -+ } -+ -+ return 0; -+} -+ -+static int hdmi_pll_reset(void) -+{ -+ /* SYSRESET controlled by power FSM */ -+ REG_FLD_MOD(PLLCTRL_PLL_CONTROL, 0x0, 3, 3); -+ -+ /* READ 0x0 reset is in progress */ -+ if (hdmi_wait_for_bit_change(PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) { -+ DSSERR("Failed to sysreset PLL\n"); -+ return -ETIMEDOUT; -+ } -+ -+ return 0; -+} -+ -+static int hdmi_phy_init(void) -+{ -+ u16 r = 0; -+ -+ r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_LDOON); -+ if (r) -+ return r; -+ -+ r = hdmi_set_phy_pwr(HDMI_PHYPWRCMD_TXON); -+ if (r) -+ return r; -+ -+ /* -+ * Read address 0 in order to get the SCP reset done completed -+ * Dummy access performed to make sure reset is done -+ */ -+ hdmi_read_reg(HDMI_TXPHY_TX_CTRL); -+ -+ /* -+ * Write to phy address 0 to configure the clock -+ * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field -+ */ -+ REG_FLD_MOD(HDMI_TXPHY_TX_CTRL, 0x1, 31, 30); -+ -+ /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */ -+ hdmi_write_reg(HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); -+ -+ /* Setup max LDO voltage */ -+ REG_FLD_MOD(HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); -+ -+ /* Write to phy address 3 to change the polarity control */ -+ REG_FLD_MOD(HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27); -+ -+ return 0; -+} -+ -+static int hdmi_wait_softreset(void) -+{ -+ /* reset W1 */ -+ REG_FLD_MOD(HDMI_WP_SYSCONFIG, 0x1, 0, 0); -+ -+ /* wait till SOFTRESET == 0 */ -+ if (hdmi_wait_for_bit_change(HDMI_WP_SYSCONFIG, 0, 0, 0) != 0) { -+ DSSERR("sysconfig reset failed\n"); -+ return -ETIMEDOUT; -+ } -+ -+ return 0; -+} -+ -+static int hdmi_pll_program(struct hdmi_pll_info *fmt) -+{ -+ u16 r = 0; -+ enum hdmi_clk_refsel refsel; -+ -+ /* wait for wrapper reset */ -+ r = hdmi_wait_softreset(); -+ if (r) -+ return r; -+ -+ r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF); -+ if (r) -+ return r; -+ -+ r = hdmi_set_pll_pwr(HDMI_PLLPWRCMD_BOTHON_ALLCLKS); -+ if (r) -+ return r; -+ -+ r = hdmi_pll_reset(); -+ if (r) -+ return r; -+ -+ refsel = HDMI_REFSEL_SYSCLK; -+ -+ r = hdmi_pll_init(refsel, fmt->dcofreq, fmt, fmt->regsd); -+ if (r) -+ return r; -+ -+ return 0; -+} -+ -+static void hdmi_phy_off(void) -+{ -+ hdmi_set_phy_pwr(HDMI_PHYPWRCMD_OFF); -+} -+ -+static int hdmi_core_ddc_edid(u8 *pedid, int ext) -+{ -+ u32 i, j; -+ char checksum = 0; -+ u32 offset = 0; -+ -+ /* Turn on CLK for DDC */ -+ REG_FLD_MOD(HDMI_CORE_AV_DPD, 0x7, 2, 0); -+ -+ /* -+ * SW HACK : Without the Delay DDC(i2c bus) reads 0 values / -+ * right shifted values( The behavior is not consistent and seen only -+ * with some TV's) -+ */ -+ usleep_range(800, 1000); -+ -+ if (!ext) { -+ /* Clk SCL Devices */ -+ REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0xA, 3, 0); -+ -+ /* HDMI_CORE_DDC_STATUS_IN_PROG */ -+ if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS, -+ 4, 4, 0) != 0) { -+ DSSERR("Failed to program DDC\n"); -+ return -ETIMEDOUT; -+ } -+ -+ /* Clear FIFO */ -+ REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x9, 3, 0); -+ -+ /* HDMI_CORE_DDC_STATUS_IN_PROG */ -+ if (hdmi_wait_for_bit_change(HDMI_CORE_DDC_STATUS, -+ 4, 4, 0) != 0) { -+ DSSERR("Failed to program DDC\n"); -+ return -ETIMEDOUT; -+ } -+ -+ } else { -+ if (ext % 2 != 0) -+ offset = 0x80; -+ } -+ -+ /* Load Segment Address Register */ -+ REG_FLD_MOD(HDMI_CORE_DDC_SEGM, ext/2, 7, 0); -+ -+ /* Load Slave Address Register */ -+ REG_FLD_MOD(HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1); -+ -+ /* Load Offset Address Register */ -+ REG_FLD_MOD(HDMI_CORE_DDC_OFFSET, offset, 7, 0); -+ -+ /* Load Byte Count */ -+ REG_FLD_MOD(HDMI_CORE_DDC_COUNT1, 0x80, 7, 0); -+ REG_FLD_MOD(HDMI_CORE_DDC_COUNT2, 0x0, 1, 0); -+ -+ /* Set DDC_CMD */ -+ if (ext) -+ REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x4, 3, 0); -+ else -+ REG_FLD_MOD(HDMI_CORE_DDC_CMD, 0x2, 3, 0); -+ -+ /* HDMI_CORE_DDC_STATUS_BUS_LOW */ -+ if (REG_GET(HDMI_CORE_DDC_STATUS, 6, 6) == 1) { -+ DSSWARN("I2C Bus Low?\n"); -+ return -EIO; -+ } -+ /* HDMI_CORE_DDC_STATUS_NO_ACK */ -+ if (REG_GET(HDMI_CORE_DDC_STATUS, 5, 5) == 1) { -+ DSSWARN("I2C No Ack\n"); -+ return -EIO; -+ } -+ -+ i = ext * 128; -+ j = 0; -+ while (((REG_GET(HDMI_CORE_DDC_STATUS, 4, 4) == 1) || -+ (REG_GET(HDMI_CORE_DDC_STATUS, 2, 2) == 0)) && -+ j < 128) { -+ -+ if (REG_GET(HDMI_CORE_DDC_STATUS, 2, 2) == 0) { -+ /* FIFO not empty */ -+ pedid[i++] = REG_GET(HDMI_CORE_DDC_DATA, 7, 0); -+ j++; -+ } -+ } -+ -+ for (j = 0; j < 128; j++) -+ checksum += pedid[j]; -+ -+ if (checksum != 0) { -+ DSSERR("E-EDID checksum failed!!\n"); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+static int read_edid(u8 *pedid, u16 max_length) -+{ -+ int r = 0, n = 0, i = 0; -+ int max_ext_blocks = (max_length / 128) - 1; -+ -+ r = hdmi_core_ddc_edid(pedid, 0); -+ if (r) { -+ return r; -+ } else { -+ n = pedid[0x7e]; -+ -+ /* -+ * README: need to comply with max_length set by the caller. -+ * Better implementation should be to allocate necessary -+ * memory to store EDID according to nb_block field found -+ * in first block -+ */ -+ if (n > max_ext_blocks) -+ n = max_ext_blocks; -+ -+ for (i = 1; i <= n; i++) { -+ r = hdmi_core_ddc_edid(pedid, i); -+ if (r) -+ return r; -+ } -+ } -+ return 0; -+} -+ -+static int get_timings_index(void) -+{ -+ int code; -+ -+ if (hdmi.mode == 0) -+ code = code_vesa[hdmi.code]; -+ else -+ code = code_cea[hdmi.code]; -+ -+ if (code == -1) { -+ /* HDMI code 4 corresponds to 640 * 480 VGA */ -+ hdmi.code = 4; -+ /* DVI mode 1 corresponds to HDMI 0 to DVI */ -+ hdmi.mode = HDMI_DVI; -+ -+ code = code_vesa[hdmi.code]; -+ } -+ return code; -+} -+ -+static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) -+{ -+ int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0; -+ int timing_vsync = 0, timing_hsync = 0; -+ struct omap_video_timings temp; -+ struct hdmi_cm cm = {-1}; -+ DSSDBG("hdmi_get_code\n"); -+ -+ for (i = 0; i < OMAP_HDMI_TIMINGS_NB; i++) { -+ temp = cea_vesa_timings[i].timings; -+ if ((temp.pixel_clock == timing->pixel_clock) && -+ (temp.x_res == timing->x_res) && -+ (temp.y_res == timing->y_res)) { -+ -+ temp_hsync = temp.hfp + temp.hsw + temp.hbp; -+ timing_hsync = timing->hfp + timing->hsw + timing->hbp; -+ temp_vsync = temp.vfp + temp.vsw + temp.vbp; -+ timing_vsync = timing->vfp + timing->vsw + timing->vbp; -+ -+ DSSDBG("temp_hsync = %d , temp_vsync = %d" -+ "timing_hsync = %d, timing_vsync = %d\n", -+ temp_hsync, temp_hsync, -+ timing_hsync, timing_vsync); -+ -+ if ((temp_hsync == timing_hsync) && -+ (temp_vsync == timing_vsync)) { -+ code = i; -+ cm.code = code_index[i]; -+ if (code < 14) -+ cm.mode = HDMI_HDMI; -+ else -+ cm.mode = HDMI_DVI; -+ DSSDBG("Hdmi_code = %d mode = %d\n", -+ cm.code, cm.mode); -+ break; -+ } -+ } -+ } -+ -+ return cm; -+} -+ -+static void get_horz_vert_timing_info(int current_descriptor_addrs, u8 *edid , -+ struct omap_video_timings *timings) -+{ -+ /* X and Y resolution */ -+ timings->x_res = (((edid[current_descriptor_addrs + 4] & 0xF0) << 4) | -+ edid[current_descriptor_addrs + 2]); -+ timings->y_res = (((edid[current_descriptor_addrs + 7] & 0xF0) << 4) | -+ edid[current_descriptor_addrs + 5]); -+ -+ timings->pixel_clock = ((edid[current_descriptor_addrs + 1] << 8) | -+ edid[current_descriptor_addrs]); -+ -+ timings->pixel_clock = 10 * timings->pixel_clock; -+ -+ /* HORIZONTAL FRONT PORCH */ -+ timings->hfp = edid[current_descriptor_addrs + 8] | -+ ((edid[current_descriptor_addrs + 11] & 0xc0) << 2); -+ /* HORIZONTAL SYNC WIDTH */ -+ timings->hsw = edid[current_descriptor_addrs + 9] | -+ ((edid[current_descriptor_addrs + 11] & 0x30) << 4); -+ /* HORIZONTAL BACK PORCH */ -+ timings->hbp = (((edid[current_descriptor_addrs + 4] & 0x0F) << 8) | -+ edid[current_descriptor_addrs + 3]) - -+ (timings->hfp + timings->hsw); -+ /* VERTICAL FRONT PORCH */ -+ timings->vfp = ((edid[current_descriptor_addrs + 10] & 0xF0) >> 4) | -+ ((edid[current_descriptor_addrs + 11] & 0x0f) << 2); -+ /* VERTICAL SYNC WIDTH */ -+ timings->vsw = (edid[current_descriptor_addrs + 10] & 0x0F) | -+ ((edid[current_descriptor_addrs + 11] & 0x03) << 4); -+ /* VERTICAL BACK PORCH */ -+ timings->vbp = (((edid[current_descriptor_addrs + 7] & 0x0F) << 8) | -+ edid[current_descriptor_addrs + 6]) - -+ (timings->vfp + timings->vsw); -+ -+} -+ -+/* Description : This function gets the resolution information from EDID */ -+static void get_edid_timing_data(u8 *edid) -+{ -+ u8 count; -+ u16 current_descriptor_addrs; -+ struct hdmi_cm cm; -+ struct omap_video_timings edid_timings; -+ -+ /* seach block 0, there are 4 DTDs arranged in priority order */ -+ for (count = 0; count < EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR; count++) { -+ current_descriptor_addrs = -+ EDID_DESCRIPTOR_BLOCK0_ADDRESS + -+ count * EDID_TIMING_DESCRIPTOR_SIZE; -+ get_horz_vert_timing_info(current_descriptor_addrs, -+ edid, &edid_timings); -+ cm = hdmi_get_code(&edid_timings); -+ DSSDBG("Block0[%d] value matches code = %d , mode = %d\n", -+ count, cm.code, cm.mode); -+ if (cm.code == -1) { -+ continue; -+ } else { -+ hdmi.code = cm.code; -+ hdmi.mode = cm.mode; -+ DSSDBG("code = %d , mode = %d\n", -+ hdmi.code, hdmi.mode); -+ return; -+ } -+ } -+ if (edid[0x7e] != 0x00) { -+ for (count = 0; count < EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR; -+ count++) { -+ current_descriptor_addrs = -+ EDID_DESCRIPTOR_BLOCK1_ADDRESS + -+ count * EDID_TIMING_DESCRIPTOR_SIZE; -+ get_horz_vert_timing_info(current_descriptor_addrs, -+ edid, &edid_timings); -+ cm = hdmi_get_code(&edid_timings); -+ DSSDBG("Block1[%d] value matches code = %d, mode = %d", -+ count, cm.code, cm.mode); -+ if (cm.code == -1) { -+ continue; -+ } else { -+ hdmi.code = cm.code; -+ hdmi.mode = cm.mode; -+ DSSDBG("code = %d , mode = %d\n", -+ hdmi.code, hdmi.mode); -+ return; -+ } -+ } -+ } -+ -+ DSSINFO("no valid timing found , falling back to VGA\n"); -+ hdmi.code = 4; /* setting default value of 640 480 VGA */ -+ hdmi.mode = HDMI_DVI; -+} -+ -+static void hdmi_read_edid(struct omap_video_timings *dp) -+{ -+ int ret = 0, code; -+ -+ memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH); -+ -+ if (!hdmi.edid_set) -+ ret = read_edid(hdmi.edid, HDMI_EDID_MAX_LENGTH); -+ -+ if (!ret) { -+ if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) { -+ /* search for timings of default resolution */ -+ get_edid_timing_data(hdmi.edid); -+ hdmi.edid_set = true; -+ } -+ } else { -+ DSSWARN("failed to read E-EDID\n"); -+ } -+ -+ if (!hdmi.edid_set) { -+ DSSINFO("fallback to VGA\n"); -+ hdmi.code = 4; /* setting default value of 640 480 VGA */ -+ hdmi.mode = HDMI_DVI; -+ } -+ -+ code = get_timings_index(); -+ -+ *dp = cea_vesa_timings[code].timings; -+} -+ -+static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, -+ struct hdmi_core_infoframe_avi *avi_cfg, -+ struct hdmi_core_packet_enable_repeat *repeat_cfg) -+{ -+ DSSDBG("Enter hdmi_core_init\n"); -+ -+ /* video core */ -+ video_cfg->ip_bus_width = HDMI_INPUT_8BIT; -+ video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT; -+ video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE; -+ video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE; -+ video_cfg->hdmi_dvi = HDMI_DVI; -+ video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK; -+ -+ /* info frame */ -+ avi_cfg->db1_format = 0; -+ avi_cfg->db1_active_info = 0; -+ avi_cfg->db1_bar_info_dv = 0; -+ avi_cfg->db1_scan_info = 0; -+ avi_cfg->db2_colorimetry = 0; -+ avi_cfg->db2_aspect_ratio = 0; -+ avi_cfg->db2_active_fmt_ar = 0; -+ avi_cfg->db3_itc = 0; -+ avi_cfg->db3_ec = 0; -+ avi_cfg->db3_q_range = 0; -+ avi_cfg->db3_nup_scaling = 0; -+ avi_cfg->db4_videocode = 0; -+ avi_cfg->db5_pixel_repeat = 0; -+ avi_cfg->db6_7_line_eoftop = 0 ; -+ avi_cfg->db8_9_line_sofbottom = 0; -+ avi_cfg->db10_11_pixel_eofleft = 0; -+ avi_cfg->db12_13_pixel_sofright = 0; -+ -+ /* packet enable and repeat */ -+ repeat_cfg->audio_pkt = 0; -+ repeat_cfg->audio_pkt_repeat = 0; -+ repeat_cfg->avi_infoframe = 0; -+ repeat_cfg->avi_infoframe_repeat = 0; -+ repeat_cfg->gen_cntrl_pkt = 0; -+ repeat_cfg->gen_cntrl_pkt_repeat = 0; -+ repeat_cfg->generic_pkt = 0; -+ repeat_cfg->generic_pkt_repeat = 0; -+} -+ -+static void hdmi_core_powerdown_disable(void) -+{ -+ DSSDBG("Enter hdmi_core_powerdown_disable\n"); -+ REG_FLD_MOD(HDMI_CORE_CTRL1, 0x0, 0, 0); -+} -+ -+static void hdmi_core_swreset_release(void) -+{ -+ DSSDBG("Enter hdmi_core_swreset_release\n"); -+ REG_FLD_MOD(HDMI_CORE_SYS_SRST, 0x0, 0, 0); -+} -+ -+static void hdmi_core_swreset_assert(void) -+{ -+ DSSDBG("Enter hdmi_core_swreset_assert\n"); -+ REG_FLD_MOD(HDMI_CORE_SYS_SRST, 0x1, 0, 0); -+} -+ -+/* DSS_HDMI_CORE_VIDEO_CONFIG */ -+static void hdmi_core_video_config(struct hdmi_core_video_config *cfg) -+{ -+ u32 r = 0; -+ -+ /* sys_ctrl1 default configuration not tunable */ -+ r = hdmi_read_reg(HDMI_CORE_CTRL1); -+ r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5); -+ r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4); -+ r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2); -+ r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1); -+ hdmi_write_reg(HDMI_CORE_CTRL1, r); -+ -+ REG_FLD_MOD(HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6); -+ -+ /* Vid_Mode */ -+ r = hdmi_read_reg(HDMI_CORE_SYS_VID_MODE); -+ -+ /* dither truncation configuration */ -+ if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) { -+ r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6); -+ r = FLD_MOD(r, 1, 5, 5); -+ } else { -+ r = FLD_MOD(r, cfg->op_dither_truc, 7, 6); -+ r = FLD_MOD(r, 0, 5, 5); -+ } -+ hdmi_write_reg(HDMI_CORE_SYS_VID_MODE, r); -+ -+ /* HDMI_Ctrl */ -+ r = hdmi_read_reg(HDMI_CORE_AV_HDMI_CTRL); -+ r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6); -+ r = FLD_MOD(r, cfg->pkt_mode, 5, 3); -+ r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0); -+ hdmi_write_reg(HDMI_CORE_AV_HDMI_CTRL, r); -+ -+ /* TMDS_CTRL */ -+ REG_FLD_MOD(HDMI_CORE_SYS_TMDS_CTRL, -+ cfg->tclk_sel_clkmult, 6, 5); -+} -+ -+static void hdmi_core_aux_infoframe_avi_config( -+ struct hdmi_core_infoframe_avi info_avi) -+{ -+ u32 val; -+ char sum = 0, checksum = 0; -+ -+ sum += 0x82 + 0x002 + 0x00D; -+ hdmi_write_reg(HDMI_CORE_AV_AVI_TYPE, 0x082); -+ hdmi_write_reg(HDMI_CORE_AV_AVI_VERS, 0x002); -+ hdmi_write_reg(HDMI_CORE_AV_AVI_LEN, 0x00D); -+ -+ val = (info_avi.db1_format << 5) | -+ (info_avi.db1_active_info << 4) | -+ (info_avi.db1_bar_info_dv << 2) | -+ (info_avi.db1_scan_info); -+ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(0), val); -+ sum += val; -+ -+ val = (info_avi.db2_colorimetry << 6) | -+ (info_avi.db2_aspect_ratio << 4) | -+ (info_avi.db2_active_fmt_ar); -+ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(1), val); -+ sum += val; -+ -+ val = (info_avi.db3_itc << 7) | -+ (info_avi.db3_ec << 4) | -+ (info_avi.db3_q_range << 2) | -+ (info_avi.db3_nup_scaling); -+ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(2), val); -+ sum += val; -+ -+ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(3), info_avi.db4_videocode); -+ sum += info_avi.db4_videocode; -+ -+ val = info_avi.db5_pixel_repeat; -+ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(4), val); -+ sum += val; -+ -+ val = info_avi.db6_7_line_eoftop & 0x00FF; -+ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(5), val); -+ sum += val; -+ -+ val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF); -+ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(6), val); -+ sum += val; -+ -+ val = info_avi.db8_9_line_sofbottom & 0x00FF; -+ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(7), val); -+ sum += val; -+ -+ val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF); -+ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(8), val); -+ sum += val; -+ -+ val = info_avi.db10_11_pixel_eofleft & 0x00FF; -+ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(9), val); -+ sum += val; -+ -+ val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF); -+ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(10), val); -+ sum += val; -+ -+ val = info_avi.db12_13_pixel_sofright & 0x00FF; -+ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(11), val); -+ sum += val; -+ -+ val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF); -+ hdmi_write_reg(HDMI_CORE_AV_AVI_DBYTE(12), val); -+ sum += val; -+ -+ checksum = 0x100 - sum; -+ hdmi_write_reg(HDMI_CORE_AV_AVI_CHSUM, checksum); -+} -+ -+static void hdmi_core_av_packet_config( -+ struct hdmi_core_packet_enable_repeat repeat_cfg) -+{ -+ /* enable/repeat the infoframe */ -+ hdmi_write_reg(HDMI_CORE_AV_PB_CTRL1, -+ (repeat_cfg.audio_pkt << 5) | -+ (repeat_cfg.audio_pkt_repeat << 4) | -+ (repeat_cfg.avi_infoframe << 1) | -+ (repeat_cfg.avi_infoframe_repeat)); -+ -+ /* enable/repeat the packet */ -+ hdmi_write_reg(HDMI_CORE_AV_PB_CTRL2, -+ (repeat_cfg.gen_cntrl_pkt << 3) | -+ (repeat_cfg.gen_cntrl_pkt_repeat << 2) | -+ (repeat_cfg.generic_pkt << 1) | -+ (repeat_cfg.generic_pkt_repeat)); -+} -+ -+static void hdmi_wp_init(struct omap_video_timings *timings, -+ struct hdmi_video_format *video_fmt, -+ struct hdmi_video_interface *video_int) -+{ -+ DSSDBG("Enter hdmi_wp_init\n"); -+ -+ timings->hbp = 0; -+ timings->hfp = 0; -+ timings->hsw = 0; -+ timings->vbp = 0; -+ timings->vfp = 0; -+ timings->vsw = 0; -+ -+ video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444; -+ video_fmt->y_res = 0; -+ video_fmt->x_res = 0; -+ -+ video_int->vsp = 0; -+ video_int->hsp = 0; -+ -+ video_int->interlacing = 0; -+ video_int->tm = 0; /* HDMI_TIMING_SLAVE */ -+ -+} -+ -+static void hdmi_wp_video_start(bool start) -+{ -+ REG_FLD_MOD(HDMI_WP_VIDEO_CFG, start, 31, 31); -+} -+ -+static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt, -+ struct omap_video_timings *timings, struct hdmi_config *param) -+{ -+ DSSDBG("Enter hdmi_wp_video_init_format\n"); -+ -+ video_fmt->y_res = param->timings.timings.y_res; -+ video_fmt->x_res = param->timings.timings.x_res; -+ -+ timings->hbp = param->timings.timings.hbp; -+ timings->hfp = param->timings.timings.hfp; -+ timings->hsw = param->timings.timings.hsw; -+ timings->vbp = param->timings.timings.vbp; -+ timings->vfp = param->timings.timings.vfp; -+ timings->vsw = param->timings.timings.vsw; -+} -+ -+static void hdmi_wp_video_config_format( -+ struct hdmi_video_format *video_fmt) -+{ -+ u32 l = 0; -+ -+ REG_FLD_MOD(HDMI_WP_VIDEO_CFG, video_fmt->packing_mode, 10, 8); -+ -+ l |= FLD_VAL(video_fmt->y_res, 31, 16); -+ l |= FLD_VAL(video_fmt->x_res, 15, 0); -+ hdmi_write_reg(HDMI_WP_VIDEO_SIZE, l); -+} -+ -+static void hdmi_wp_video_config_interface( -+ struct hdmi_video_interface *video_int) -+{ -+ u32 r; -+ DSSDBG("Enter hdmi_wp_video_config_interface\n"); -+ -+ r = hdmi_read_reg(HDMI_WP_VIDEO_CFG); -+ r = FLD_MOD(r, video_int->vsp, 7, 7); -+ r = FLD_MOD(r, video_int->hsp, 6, 6); -+ r = FLD_MOD(r, video_int->interlacing, 3, 3); -+ r = FLD_MOD(r, video_int->tm, 1, 0); -+ hdmi_write_reg(HDMI_WP_VIDEO_CFG, r); -+} -+ -+static void hdmi_wp_video_config_timing( -+ struct omap_video_timings *timings) -+{ -+ u32 timing_h = 0; -+ u32 timing_v = 0; -+ -+ DSSDBG("Enter hdmi_wp_video_config_timing\n"); -+ -+ timing_h |= FLD_VAL(timings->hbp, 31, 20); -+ timing_h |= FLD_VAL(timings->hfp, 19, 8); -+ timing_h |= FLD_VAL(timings->hsw, 7, 0); -+ hdmi_write_reg(HDMI_WP_VIDEO_TIMING_H, timing_h); -+ -+ timing_v |= FLD_VAL(timings->vbp, 31, 20); -+ timing_v |= FLD_VAL(timings->vfp, 19, 8); -+ timing_v |= FLD_VAL(timings->vsw, 7, 0); -+ hdmi_write_reg(HDMI_WP_VIDEO_TIMING_V, timing_v); -+} -+ -+static void hdmi_basic_configure(struct hdmi_config *cfg) -+{ -+ /* HDMI */ -+ struct omap_video_timings video_timing; -+ struct hdmi_video_format video_format; -+ struct hdmi_video_interface video_interface; -+ /* HDMI core */ -+ struct hdmi_core_infoframe_avi avi_cfg; -+ struct hdmi_core_video_config v_core_cfg; -+ struct hdmi_core_packet_enable_repeat repeat_cfg; -+ -+ hdmi_wp_init(&video_timing, &video_format, -+ &video_interface); -+ -+ hdmi_core_init(&v_core_cfg, -+ &avi_cfg, -+ &repeat_cfg); -+ -+ hdmi_wp_video_init_format(&video_format, -+ &video_timing, cfg); -+ -+ hdmi_wp_video_config_timing(&video_timing); -+ -+ /* video config */ -+ video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422; -+ -+ hdmi_wp_video_config_format(&video_format); -+ -+ video_interface.vsp = cfg->timings.vsync_pol; -+ video_interface.hsp = cfg->timings.hsync_pol; -+ video_interface.interlacing = cfg->interlace; -+ video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */ -+ -+ hdmi_wp_video_config_interface(&video_interface); -+ -+ /* -+ * configure core video part -+ * set software reset in the core -+ */ -+ hdmi_core_swreset_assert(); -+ -+ /* power down off */ -+ hdmi_core_powerdown_disable(); -+ -+ v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL; -+ v_core_cfg.hdmi_dvi = cfg->cm.mode; -+ -+ hdmi_core_video_config(&v_core_cfg); -+ -+ /* release software reset in the core */ -+ hdmi_core_swreset_release(); -+ -+ /* -+ * configure packet -+ * info frame video see doc CEA861-D page 65 -+ */ -+ avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB; -+ avi_cfg.db1_active_info = -+ HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF; -+ avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO; -+ avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0; -+ avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO; -+ avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO; -+ avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME; -+ avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO; -+ avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601; -+ avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT; -+ avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO; -+ avi_cfg.db4_videocode = cfg->cm.code; -+ avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO; -+ avi_cfg.db6_7_line_eoftop = 0; -+ avi_cfg.db8_9_line_sofbottom = 0; -+ avi_cfg.db10_11_pixel_eofleft = 0; -+ avi_cfg.db12_13_pixel_sofright = 0; -+ -+ hdmi_core_aux_infoframe_avi_config(avi_cfg); -+ -+ /* enable/repeat the infoframe */ -+ repeat_cfg.avi_infoframe = HDMI_PACKETENABLE; -+ repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON; -+ /* wakeup */ -+ repeat_cfg.audio_pkt = HDMI_PACKETENABLE; -+ repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON; -+ hdmi_core_av_packet_config(repeat_cfg); -+} -+ -+static void update_hdmi_timings(struct hdmi_config *cfg, -+ struct omap_video_timings *timings, int code) -+{ -+ cfg->timings.timings.x_res = timings->x_res; -+ cfg->timings.timings.y_res = timings->y_res; -+ cfg->timings.timings.hbp = timings->hbp; -+ cfg->timings.timings.hfp = timings->hfp; -+ cfg->timings.timings.hsw = timings->hsw; -+ cfg->timings.timings.vbp = timings->vbp; -+ cfg->timings.timings.vfp = timings->vfp; -+ cfg->timings.timings.vsw = timings->vsw; -+ cfg->timings.timings.pixel_clock = timings->pixel_clock; -+ cfg->timings.vsync_pol = cea_vesa_timings[code].vsync_pol; -+ cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol; -+} -+ -+static void hdmi_compute_pll(unsigned long clkin, int phy, -+ int n, struct hdmi_pll_info *pi) -+{ -+ unsigned long refclk; -+ u32 mf; -+ -+ /* -+ * Input clock is predivided by N + 1 -+ * out put of which is reference clk -+ */ -+ refclk = clkin / (n + 1); -+ pi->regn = n; -+ -+ /* -+ * multiplier is pixel_clk/ref_clk -+ * Multiplying by 100 to avoid fractional part removal -+ */ -+ pi->regm = (phy * 100/(refclk))/100; -+ pi->regm2 = 1; -+ -+ /* -+ * fractional multiplier is remainder of the difference between -+ * multiplier and actual phy(required pixel clock thus should be -+ * multiplied by 218(262144) divided by the reference clock -+ */ -+ mf = (phy - pi->regm * refclk) * 262144; -+ pi->regmf = mf/(refclk); -+ -+ /* -+ * Dcofreq should be set to 1 if required pixel clock -+ * is greater than 1000MHz -+ */ -+ pi->dcofreq = phy > 1000 * 100; -+ pi->regsd = ((pi->regm * clkin / 10) / ((n + 1) * 250) + 5) / 10; -+ -+ DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); -+ DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); -+} -+ -+static void hdmi_enable_clocks(int enable) -+{ -+ if (enable) -+ dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK | -+ DSS_CLK_SYSCK | DSS_CLK_VIDFCK); -+ else -+ dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK | -+ DSS_CLK_SYSCK | DSS_CLK_VIDFCK); -+} -+ -+static int hdmi_power_on(struct omap_dss_device *dssdev) -+{ -+ int r, code = 0; -+ struct hdmi_pll_info pll_data; -+ struct omap_video_timings *p; -+ int clkin, n, phy; -+ -+ hdmi_enable_clocks(1); -+ -+ dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 0); -+ -+ p = &dssdev->panel.timings; -+ -+ DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", -+ dssdev->panel.timings.x_res, -+ dssdev->panel.timings.y_res); -+ -+ if (!hdmi.custom_set) { -+ DSSDBG("Read EDID as no EDID is not set on poweron\n"); -+ hdmi_read_edid(p); -+ } -+ code = get_timings_index(); -+ dssdev->panel.timings = cea_vesa_timings[code].timings; -+ update_hdmi_timings(&hdmi.cfg, p, code); -+ -+ clkin = 3840; /* 38.4 MHz */ -+ n = 15; /* this is a constant for our math */ -+ phy = p->pixel_clock; -+ -+ hdmi_compute_pll(clkin, phy, n, &pll_data); -+ -+ hdmi_wp_video_start(0); -+ -+ /* config the PLL and PHY first */ -+ r = hdmi_pll_program(&pll_data); -+ if (r) { -+ DSSDBG("Failed to lock PLL\n"); -+ goto err; -+ } -+ -+ r = hdmi_phy_init(); -+ if (r) { -+ DSSDBG("Failed to start PHY\n"); -+ goto err; -+ } -+ -+ hdmi.cfg.cm.mode = hdmi.mode; -+ hdmi.cfg.cm.code = hdmi.code; -+ hdmi_basic_configure(&hdmi.cfg); -+ -+ /* Make selection of HDMI in DSS */ -+ dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); -+ -+ /* Select the dispc clock source as PRCM clock, to ensure that it is not -+ * DSI PLL source as the clock selected by DSI PLL might not be -+ * sufficient for the resolution selected / that can be changed -+ * dynamically by user. This can be moved to single location , say -+ * Boardfile. -+ */ -+ dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); -+ -+ /* bypass TV gamma table */ -+ dispc_enable_gamma_table(0); -+ -+ /* tv size */ -+ dispc_set_digit_size(dssdev->panel.timings.x_res, -+ dssdev->panel.timings.y_res); -+ -+ dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 1); -+ -+ hdmi_wp_video_start(1); -+ -+ return 0; -+err: -+ hdmi_enable_clocks(0); -+ return -EIO; -+} -+ -+static void hdmi_power_off(struct omap_dss_device *dssdev) -+{ -+ dispc_enable_channel(OMAP_DSS_CHANNEL_DIGIT, 0); -+ -+ hdmi_wp_video_start(0); -+ hdmi_phy_off(); -+ hdmi_set_pll_pwr(HDMI_PLLPWRCMD_ALLOFF); -+ hdmi_enable_clocks(0); -+ -+ hdmi.edid_set = 0; -+} -+ -+int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, -+ struct omap_video_timings *timings) -+{ -+ struct hdmi_cm cm; -+ -+ cm = hdmi_get_code(timings); -+ if (cm.code == -1) { -+ DSSERR("Invalid timing entered\n"); -+ return -EINVAL; -+ } -+ -+ return 0; -+ -+} -+ -+void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev) -+{ -+ struct hdmi_cm cm; -+ -+ hdmi.custom_set = 1; -+ cm = hdmi_get_code(&dssdev->panel.timings); -+ hdmi.code = cm.code; -+ hdmi.mode = cm.mode; -+ omapdss_hdmi_display_enable(dssdev); -+ hdmi.custom_set = 0; -+} -+ -+int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev) -+{ -+ int r = 0; -+ -+ DSSDBG("ENTER hdmi_display_enable\n"); -+ -+ mutex_lock(&hdmi.lock); -+ -+ r = omap_dss_start_device(dssdev); -+ if (r) { -+ DSSERR("failed to start device\n"); -+ goto err0; -+ } -+ -+ if (dssdev->platform_enable) { -+ r = dssdev->platform_enable(dssdev); -+ if (r) { -+ DSSERR("failed to enable GPIO's\n"); -+ goto err1; -+ } -+ } -+ -+ r = hdmi_power_on(dssdev); -+ if (r) { -+ DSSERR("failed to power on device\n"); -+ goto err2; -+ } -+ -+ mutex_unlock(&hdmi.lock); -+ return 0; -+ -+err2: -+ if (dssdev->platform_disable) -+ dssdev->platform_disable(dssdev); -+err1: -+ omap_dss_stop_device(dssdev); -+err0: -+ mutex_unlock(&hdmi.lock); -+ return r; -+} -+ -+void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev) -+{ -+ DSSDBG("Enter hdmi_display_disable\n"); -+ -+ mutex_lock(&hdmi.lock); -+ -+ hdmi_power_off(dssdev); -+ -+ if (dssdev->platform_disable) -+ dssdev->platform_disable(dssdev); -+ -+ omap_dss_stop_device(dssdev); -+ -+ mutex_unlock(&hdmi.lock); -+} -+ -+/* HDMI HW IP initialisation */ -+static int omapdss_hdmihw_probe(struct platform_device *pdev) -+{ -+ struct resource *hdmi_mem; -+ -+ hdmi.pdata = pdev->dev.platform_data; -+ hdmi.pdev = pdev; -+ -+ mutex_init(&hdmi.lock); -+ -+ hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0); -+ if (!hdmi_mem) { -+ DSSERR("can't get IORESOURCE_MEM HDMI\n"); -+ return -EINVAL; -+ } -+ -+ /* Base address taken from platform */ -+ hdmi.base_wp = ioremap(hdmi_mem->start, resource_size(hdmi_mem)); -+ if (!hdmi.base_wp) { -+ DSSERR("can't ioremap WP\n"); -+ return -ENOMEM; -+ } -+ -+ hdmi_panel_init(); -+ -+ return 0; -+} -+ -+static int omapdss_hdmihw_remove(struct platform_device *pdev) -+{ -+ hdmi_panel_exit(); -+ -+ iounmap(hdmi.base_wp); -+ -+ return 0; -+} -+ -+static struct platform_driver omapdss_hdmihw_driver = { -+ .probe = omapdss_hdmihw_probe, -+ .remove = omapdss_hdmihw_remove, -+ .driver = { -+ .name = "omapdss_hdmi", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+int hdmi_init_platform_driver(void) -+{ -+ return platform_driver_register(&omapdss_hdmihw_driver); -+} -+ -+void hdmi_uninit_platform_driver(void) -+{ -+ return platform_driver_unregister(&omapdss_hdmihw_driver); -+} --- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-306-V5_HDMI_panel_driver_addition_in_the_DSS.patch b/packages/linux/patches/linux-2.6.38-rc8-306-V5_HDMI_panel_driver_addition_in_the_DSS.patch deleted file mode 100644 index 8d2cdcc739..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc8-306-V5_HDMI_panel_driver_addition_in_the_DSS.patch +++ /dev/null @@ -1,252 +0,0 @@ -The panel driver(hdmi_omap4_panel.c) in omap2/dss acts as a controller -to manage the enable and disable requests and synchronize audio and video. - -Signed-off-by: Mythri P K ---- - drivers/video/omap2/dss/dss.h | 2 + - drivers/video/omap2/dss/hdmi_omap4_panel.c | 222 ++++++++++++++++++++++++++++ - 2 files changed, 224 insertions(+), 0 deletions(-) - create mode 100644 drivers/video/omap2/dss/hdmi_omap4_panel.c - -diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h -index 6bf923c..05ccd00 100644 ---- a/drivers/video/omap2/dss/dss.h -+++ b/drivers/video/omap2/dss/dss.h -@@ -483,6 +483,8 @@ void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev); - void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev); - int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, - struct omap_video_timings *timings); -+int hdmi_panel_init(void); -+void hdmi_panel_exit(void); - - /* RFBI */ - #ifdef CONFIG_OMAP2_DSS_RFBI -diff --git a/drivers/video/omap2/dss/hdmi_omap4_panel.c b/drivers/video/omap2/dss/hdmi_omap4_panel.c -new file mode 100644 -index 0000000..ffb5de9 ---- /dev/null -+++ b/drivers/video/omap2/dss/hdmi_omap4_panel.c -@@ -0,0 +1,222 @@ -+/* -+ * hdmi_omap4_panel.c -+ * -+ * HDMI library support functions for TI OMAP4 processors. -+ * -+ * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ -+ * Authors: Mythri P k -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published by -+ * the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License along with -+ * this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "dss.h" -+ -+static struct { -+ struct mutex hdmi_lock; -+} hdmi; -+ -+ -+static int hdmi_panel_probe(struct omap_dss_device *dssdev) -+{ -+ DSSDBG("ENTER hdmi_panel_probe\n"); -+ -+ dssdev->panel.config = OMAP_DSS_LCD_TFT | -+ OMAP_DSS_LCD_IVS | OMAP_DSS_LCD_IHS; -+ -+ /* -+ * Initialize the timings to 640 * 480 -+ * This is only for framebuffer update not for TV timing setting -+ * Setting TV timing will be done only on enable -+ */ -+ dssdev->panel.timings.x_res = 640; -+ dssdev->panel.timings.y_res = 480; -+ -+ DSSDBG("hdmi_panel_probe x_res= %d y_res = %d\n", -+ dssdev->panel.timings.x_res, -+ dssdev->panel.timings.y_res); -+ return 0; -+} -+ -+static void hdmi_panel_remove(struct omap_dss_device *dssdev) -+{ -+ -+} -+ -+static int hdmi_panel_enable(struct omap_dss_device *dssdev) -+{ -+ int r = 0; -+ DSSDBG("ENTER hdmi_panel_enable\n"); -+ -+ mutex_lock(&hdmi.hdmi_lock); -+ -+ if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) { -+ r = -EINVAL; -+ goto err; -+ } -+ -+ r = omapdss_hdmi_display_enable(dssdev); -+ if (r) { -+ DSSERR("failed to power on\n"); -+ goto err; -+ } -+ -+ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; -+ -+err: -+ mutex_unlock(&hdmi.hdmi_lock); -+ -+ return r; -+} -+ -+static void hdmi_panel_disable(struct omap_dss_device *dssdev) -+{ -+ mutex_lock(&hdmi.hdmi_lock); -+ -+ if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) -+ omapdss_hdmi_display_disable(dssdev); -+ -+ dssdev->state = OMAP_DSS_DISPLAY_DISABLED; -+ -+ mutex_unlock(&hdmi.hdmi_lock); -+} -+ -+static int hdmi_panel_suspend(struct omap_dss_device *dssdev) -+{ -+ int r = 0; -+ -+ mutex_lock(&hdmi.hdmi_lock); -+ -+ if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE) { -+ r = -EINVAL; -+ goto err; -+ } -+ -+ dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED; -+ -+ omapdss_hdmi_display_disable(dssdev); -+ -+err: -+ mutex_unlock(&hdmi.hdmi_lock); -+ -+ return r; -+} -+ -+static int hdmi_panel_resume(struct omap_dss_device *dssdev) -+{ -+ int r = 0; -+ -+ mutex_lock(&hdmi.hdmi_lock); -+ -+ if (dssdev->state != OMAP_DSS_DISPLAY_SUSPENDED) { -+ r = -EINVAL; -+ goto err; -+ } -+ -+ r = omapdss_hdmi_display_enable(dssdev); -+ if (r) { -+ DSSERR("failed to power on\n"); -+ goto err; -+ } -+ -+ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE; -+ -+err: -+ mutex_unlock(&hdmi.hdmi_lock); -+ -+ return r; -+} -+ -+static void hdmi_get_timings(struct omap_dss_device *dssdev, -+ struct omap_video_timings *timings) -+{ -+ mutex_lock(&hdmi.hdmi_lock); -+ -+ *timings = dssdev->panel.timings; -+ -+ mutex_unlock(&hdmi.hdmi_lock); -+} -+ -+static void hdmi_set_timings(struct omap_dss_device *dssdev, -+ struct omap_video_timings *timings) -+{ -+ DSSDBG("hdmi_set_timings\n"); -+ -+ mutex_lock(&hdmi.hdmi_lock); -+ -+ dssdev->panel.timings = *timings; -+ -+ if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) { -+ /* turn the hdmi off and on to get new timings to use */ -+ omapdss_hdmi_display_disable(dssdev); -+ omapdss_hdmi_display_set_timing(dssdev); -+ } -+ -+ mutex_unlock(&hdmi.hdmi_lock); -+} -+ -+static int hdmi_check_timings(struct omap_dss_device *dssdev, -+ struct omap_video_timings *timings) -+{ -+ int r = 0; -+ -+ DSSDBG("hdmi_check_timings\n"); -+ -+ mutex_lock(&hdmi.hdmi_lock); -+ -+ r = omapdss_hdmi_display_check_timing(dssdev, timings); -+ if (r) { -+ DSSERR("Timing cannot be applied\n"); -+ goto err; -+ } -+err: -+ mutex_unlock(&hdmi.hdmi_lock); -+ return r; -+} -+ -+static struct omap_dss_driver hdmi_driver = { -+ .probe = hdmi_panel_probe, -+ .remove = hdmi_panel_remove, -+ .enable = hdmi_panel_enable, -+ .disable = hdmi_panel_disable, -+ .suspend = hdmi_panel_suspend, -+ .resume = hdmi_panel_resume, -+ .get_timings = hdmi_get_timings, -+ .set_timings = hdmi_set_timings, -+ .check_timings = hdmi_check_timings, -+ .driver = { -+ .name = "hdmi_panel", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+int hdmi_panel_init(void) -+{ -+ mutex_init(&hdmi.hdmi_lock); -+ -+ omap_dss_register_driver(&hdmi_driver); -+ -+ return 0; -+} -+ -+void hdmi_panel_exit(void) -+{ -+ omap_dss_unregister_driver(&hdmi_driver); -+ -+} --- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-307-V5_Add_makefile_and_kconfig_changes_to_enable_HDMI_in_OMAP4.patch b/packages/linux/patches/linux-2.6.38-rc8-307-V5_Add_makefile_and_kconfig_changes_to_enable_HDMI_in_OMAP4.patch deleted file mode 100644 index f95348bc66..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc8-307-V5_Add_makefile_and_kconfig_changes_to_enable_HDMI_in_OMAP4.patch +++ /dev/null @@ -1,36 +0,0 @@ -Signed-off-by: Mythri P K ---- - drivers/video/omap2/dss/Kconfig | 8 ++++++++ - drivers/video/omap2/dss/Makefile | 2 ++ - 2 files changed, 10 insertions(+), 0 deletions(-) - -diff --git a/drivers/video/omap2/dss/Kconfig b/drivers/video/omap2/dss/Kconfig -index db01473..bfc5da0 100644 ---- a/drivers/video/omap2/dss/Kconfig -+++ b/drivers/video/omap2/dss/Kconfig -@@ -60,6 +60,14 @@ config OMAP2_DSS_VENC - help - OMAP Video Encoder support for S-Video and composite TV-out. - -+config OMAP4_DSS_HDMI -+ bool "HDMI support" -+ depends on ARCH_OMAP4 -+ default y -+ help -+ HDMI Interface. This adds the High Definition Multimedia Interface. -+ See http://www.hdmi.org/ for HDMI specification. -+ - config OMAP2_DSS_SDI - bool "SDI support" - depends on ARCH_OMAP3 -diff --git a/drivers/video/omap2/dss/Makefile b/drivers/video/omap2/dss/Makefile -index 7db17b5..10d9d3b 100644 ---- a/drivers/video/omap2/dss/Makefile -+++ b/drivers/video/omap2/dss/Makefile -@@ -5,3 +5,5 @@ omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o - omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o - omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o - omapdss-$(CONFIG_OMAP2_DSS_DSI) += dsi.o -+omapdss-$(CONFIG_OMAP4_DSS_HDMI) += hdmi.o \ -+ hdmi_omap4_panel.o --- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-308-V5_Call_to_HDMI_module_init_to_register_driver.patch b/packages/linux/patches/linux-2.6.38-rc8-308-V5_Call_to_HDMI_module_init_to_register_driver.patch deleted file mode 100644 index 75ca4de0c8..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc8-308-V5_Call_to_HDMI_module_init_to_register_driver.patch +++ /dev/null @@ -1,43 +0,0 @@ -calling the platform registration of HDMI driver from core -during initialization. - -Signed-off-by: Mythri P K ---- - drivers/video/omap2/dss/core.c | 9 +++++++++ - 1 files changed, 9 insertions(+), 0 deletions(-) - -diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c -index c2f930b..1aa2ed1 100644 ---- a/drivers/video/omap2/dss/core.c -+++ b/drivers/video/omap2/dss/core.c -@@ -209,6 +209,12 @@ static int omap_dss_probe(struct platform_device *pdev) - goto err_dsi; - } - -+ r = hdmi_init_platform_driver(); -+ if (r) { -+ DSSERR("Failed to initialize hdmi\n"); -+ goto err_hdmi; -+ } -+ - r = dss_initialize_debugfs(); - if (r) - goto err_debugfs; -@@ -238,6 +244,8 @@ static int omap_dss_probe(struct platform_device *pdev) - err_register: - dss_uninitialize_debugfs(); - err_debugfs: -+ hdmi_uninit_platform_driver(); -+err_hdmi: - dsi_uninit_platform_driver(); - err_dsi: - venc_uninit_platform_driver(); -@@ -263,6 +271,7 @@ static int omap_dss_remove(struct platform_device *pdev) - dispc_uninit_platform_driver(); - rfbi_uninit_platform_driver(); - dsi_uninit_platform_driver(); -+ hdmi_uninit_platform_driver(); - dss_uninit_platform_driver(); - - dss_uninit_overlays(pdev); --- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-309-V5_Add_HDMI_structure_in_the_board_file_for_OMAP4_SDP.patch b/packages/linux/patches/linux-2.6.38-rc8-309-V5_Add_HDMI_structure_in_the_board_file_for_OMAP4_SDP.patch deleted file mode 100644 index 491cc89a66..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc8-309-V5_Add_HDMI_structure_in_the_board_file_for_OMAP4_SDP.patch +++ /dev/null @@ -1,118 +0,0 @@ -Adding board file structure for display which adds the display -structure with HDMI as the default driver when the display init -is called. -HDMI GPIO configurations are also done in this file. - -Signed-off-by: Mythri P K ---- - arch/arm/mach-omap2/board-4430sdp.c | 75 +++++++++++++++++++++++++++++++++++ - 1 files changed, 75 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c -index 85805d4..f5fcc5f 100644 ---- a/arch/arm/mach-omap2/board-4430sdp.c -+++ b/arch/arm/mach-omap2/board-4430sdp.c -@@ -36,6 +36,7 @@ - #include - #include - #include -+#include - - #include "mux.h" - #include "hsmmc.h" -@@ -47,6 +48,8 @@ - #define ETH_KS8851_QUART 138 - #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO 184 - #define OMAP4_SFH7741_ENABLE_GPIO 188 -+#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ -+#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ - - static const int sdp4430_keymap[] = { - KEY(0, 0, KEY_E), -@@ -620,6 +623,76 @@ static void __init omap_sfh7741prox_init(void) - } - } - -+static void sdp4430_hdmi_mux_init(void) -+{ -+ /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */ -+ omap_mux_init_signal("hdmi_hpd", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("hdmi_cec", -+ OMAP_PIN_INPUT_PULLUP); -+ /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */ -+ omap_mux_init_signal("hdmi_ddc_scl", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("hdmi_ddc_sda", -+ OMAP_PIN_INPUT_PULLUP); -+} -+ -+static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) -+{ -+ int status; -+ -+ status = gpio_request_one(HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, -+ "hdmi_gpio_hpd"); -+ if (status) { -+ pr_err("Cannot request GPIO %d\n", HDMI_GPIO_HPD); -+ return status; -+ } -+ status = gpio_request_one(HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, -+ "hdmi_gpio_ls_oe"); -+ if (status) { -+ pr_err("Cannot request GPIO %d\n", HDMI_GPIO_LS_OE); -+ goto error1; -+ } -+ -+ return 0; -+ -+error1: -+ gpio_free(HDMI_GPIO_HPD); -+ -+ return status; -+} -+ -+static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev) -+{ -+ gpio_free(HDMI_GPIO_LS_OE); -+ gpio_free(HDMI_GPIO_HPD); -+} -+ -+static struct omap_dss_device sdp4430_hdmi_device = { -+ .name = "hdmi", -+ .driver_name = "hdmi_panel", -+ .type = OMAP_DISPLAY_TYPE_HDMI, -+ .platform_enable = sdp4430_panel_enable_hdmi, -+ .platform_disable = sdp4430_panel_disable_hdmi, -+ .channel = OMAP_DSS_CHANNEL_DIGIT, -+}; -+ -+static struct omap_dss_device *sdp4430_dss_devices[] = { -+ &sdp4430_hdmi_device, -+}; -+ -+static struct omap_dss_board_info sdp4430_dss_data = { -+ .num_devices = ARRAY_SIZE(sdp4430_dss_devices), -+ .devices = sdp4430_dss_devices, -+ .default_device = &sdp4430_hdmi_device, -+}; -+ -+void omap_4430sdp_display_init(void) -+{ -+ sdp4430_hdmi_mux_init(); -+ omap_display_init(&sdp4430_dss_data); -+} -+ - #ifdef CONFIG_OMAP_MUX - static struct omap_board_mux board_mux[] __initdata = { - OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), -@@ -661,6 +734,8 @@ static void __init omap_4430sdp_init(void) - status = omap4_keyboard_init(&sdp4430_keypad_data); - if (status) - pr_err("Keypad initialization failed: %d\n", status); -+ -+ omap_4430sdp_display_init(); - } - - static void __init omap_4430sdp_map_io(void) --- 1.5.6.3 diff --git a/packages/linux/patches/linux-2.6.38-rc8-310-V5_Add_HDMI_structure_in_the_board_file_for_OMAP4__PANDA.patch b/packages/linux/patches/linux-2.6.38-rc8-310-V5_Add_HDMI_structure_in_the_board_file_for_OMAP4__PANDA.patch deleted file mode 100644 index 9c4b26ec9e..0000000000 --- a/packages/linux/patches/linux-2.6.38-rc8-310-V5_Add_HDMI_structure_in_the_board_file_for_OMAP4__PANDA.patch +++ /dev/null @@ -1,117 +0,0 @@ -Adding board file structure for display which adds the display -structure with HDMI as the default driver when the display init -is called. -HDMI GPIO configurations are also done in this file. - -Signed-off-by: Mythri P K ---- - arch/arm/mach-omap2/board-omap4panda.c | 74 ++++++++++++++++++++++++++++++++ - 1 files changed, 74 insertions(+), 0 deletions(-) - -diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c -index a94ce07..4869c0f 100644 ---- a/arch/arm/mach-omap2/board-omap4panda.c -+++ b/arch/arm/mach-omap2/board-omap4panda.c -@@ -34,6 +34,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -49,6 +50,8 @@ - #define GPIO_HUB_NRESET 62 - #define GPIO_WIFI_PMENA 43 - #define GPIO_WIFI_IRQ 53 -+#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */ -+#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ - - /* wl127x BT, FM, GPS connectivity chip */ - static int wl1271_gpios[] = {46, -1, -1}; -@@ -467,6 +470,76 @@ static struct omap_board_mux board_mux[] __initdata = { - #define board_mux NULL - #endif - -+static void sdp4430_hdmi_mux_init(void) -+{ -+ /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */ -+ omap_mux_init_signal("hdmi_hpd", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("hdmi_cec", -+ OMAP_PIN_INPUT_PULLUP); -+ /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */ -+ omap_mux_init_signal("hdmi_ddc_scl", -+ OMAP_PIN_INPUT_PULLUP); -+ omap_mux_init_signal("hdmi_ddc_sda", -+ OMAP_PIN_INPUT_PULLUP); -+} -+ -+static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev) -+{ -+ int status; -+ -+ status = gpio_request_one(HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, -+ "hdmi_gpio_hpd"); -+ if (status) { -+ pr_err("Cannot request GPIO %d\n", HDMI_GPIO_HPD); -+ return status; -+ } -+ status = gpio_request_one(HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, -+ "hdmi_gpio_ls_oe"); -+ if (status) { -+ pr_err("Cannot request GPIO %d\n", HDMI_GPIO_LS_OE); -+ goto error1; -+ } -+ -+ return 0; -+ -+error1: -+ gpio_free(HDMI_GPIO_HPD); -+ -+ return status; -+} -+ -+static void sdp4430_panel_disable_hdmi(struct omap_dss_device *dssdev) -+{ -+ gpio_free(HDMI_GPIO_LS_OE); -+ gpio_free(HDMI_GPIO_HPD); -+} -+ -+static struct omap_dss_device sdp4430_hdmi_device = { -+ .name = "hdmi", -+ .driver_name = "hdmi_panel", -+ .type = OMAP_DISPLAY_TYPE_HDMI, -+ .platform_enable = sdp4430_panel_enable_hdmi, -+ .platform_disable = sdp4430_panel_disable_hdmi, -+ .channel = OMAP_DSS_CHANNEL_DIGIT, -+}; -+ -+static struct omap_dss_device *sdp4430_dss_devices[] = { -+ &sdp4430_hdmi_device, -+}; -+ -+static struct omap_dss_board_info sdp4430_dss_data = { -+ .num_devices = ARRAY_SIZE(sdp4430_dss_devices), -+ .devices = sdp4430_dss_devices, -+ .default_device = &sdp4430_hdmi_device, -+}; -+ -+void omap_panda_display_init(void) -+{ -+ sdp4430_hdmi_mux_init(); -+ omap_display_init(&sdp4430_dss_data); -+} -+ - static void __init omap4_panda_init(void) - { - int package = OMAP_PACKAGE_CBS; -@@ -485,6 +558,7 @@ static void __init omap4_panda_init(void) - omap4_twl6030_hsmmc_init(mmc); - omap4_ehci_init(); - usb_musb_init(&musb_board_data); -+ omap_panda_display_init(); - } - - static void __init omap4_panda_map_io(void) --- 1.5.6.3