diff --git a/packages/linux/meta b/packages/linux/meta index 779f9bb5c3..18dfa1a0aa 100644 --- a/packages/linux/meta +++ b/packages/linux/meta @@ -20,9 +20,6 @@ PKG_NAME="linux" case "$LINUX" in - 3.11) - PKG_VERSION="3.11.6" - ;; *) PKG_VERSION="3.12" ;; diff --git a/packages/linux/patches/3.11.6/linux-003-no_dev_console.patch b/packages/linux/patches/3.11.6/linux-003-no_dev_console.patch deleted file mode 100644 index df35a7ab9a..0000000000 --- a/packages/linux/patches/3.11.6/linux-003-no_dev_console.patch +++ /dev/null @@ -1,21 +0,0 @@ -diff --git a/init/main.c b/init/main.c -index 9484f4b..db55edd 100644 ---- a/init/main.c -+++ b/init/main.c -@@ -880,8 +880,14 @@ static noinline void __init kernel_init_freeable(void) - do_basic_setup(); - - /* Open the /dev/console on the rootfs, this should never fail */ -- if (sys_open((const char __user *) "/dev/console", O_RDWR, 0) < 0) -- pr_err("Warning: unable to open an initial console.\n"); -+ char *console = "/dev_console"; -+ -+ if (sys_open((const char __user *) "/dev/console", O_RDWR, 0) < 0) { -+ sys_mknod(console, S_IFCHR|0600, (TTYAUX_MAJOR<<8)|1); -+ if (sys_open(console, O_RDWR, 0) < 0) -+ printk(KERN_WARNING "Warning: unable to open an initial console.\n"); -+ sys_unlink(console); -+ } - - (void) sys_dup(0); - (void) sys_dup(0); diff --git a/packages/linux/patches/3.11.6/linux-052-XBOX_remote_support.patch b/packages/linux/patches/3.11.6/linux-052-XBOX_remote_support.patch deleted file mode 100644 index 6b43f9b315..0000000000 --- a/packages/linux/patches/3.11.6/linux-052-XBOX_remote_support.patch +++ /dev/null @@ -1,1029 +0,0 @@ -diff -Naur linux-3.9.4/drivers/staging/media/lirc/Kconfig linux-3.9.4.patch/drivers/staging/media/lirc/Kconfig ---- linux-3.9.4/drivers/staging/media/lirc/Kconfig 2013-05-24 20:45:59.000000000 +0200 -+++ linux-3.9.4.patch/drivers/staging/media/lirc/Kconfig 2013-05-30 18:18:57.238957100 +0200 -@@ -63,10 +63,17 @@ - help - Driver for the SIR IrDA port - -+config LIRC_XBOX -+ tristate "XBOX USB IR Remote" -+ depends on LIRC && USB -+ help -+ Driver for the Microsoft XBOX USB IR Remote -+ - config LIRC_ZILOG - tristate "Zilog/Hauppauge IR Transmitter" - depends on LIRC && I2C - help - Driver for the Zilog/Hauppauge IR Transmitter, found on - PVR-150/500, HVR-1200/1250/1700/1800, HD-PVR and other cards -+ - endif -diff -Naur linux-3.9.4/drivers/staging/media/lirc/lirc_xbox.c linux-3.9.4.patch/drivers/staging/media/lirc/lirc_xbox.c ---- linux-3.9.4/drivers/staging/media/lirc/lirc_xbox.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.9.4.patch/drivers/staging/media/lirc/lirc_xbox.c 2013-05-30 18:40:22.523775446 +0200 -@@ -0,0 +1,995 @@ -+/* -+ * lirc_xbox - USB remote support for LIRC -+ * (supports Microsoft XBOX DVD Dongle) -+ * -+ * Copyright (C) 2003-2004 Paul Miller -+ * -+ * This driver was derived from: -+ * Vladimir Dergachev 's 2002 -+ * "USB ATI Remote support" (input device) -+ * Adrian Dewhurst 's 2002 -+ * "USB StreamZap remote driver" (LIRC) -+ * Artur Lipowski 's 2002 -+ * "lirc_dev" and "lirc_gpio" LIRC modules -+ * Michael Wojciechowski -+ * initial xbox support -+ * Vassilis Virvilis 2006 -+ * reworked the patch for lirc submission -+ * Paul Miller's 2004 -+ * lirc_atiusb - removed all ati remote support -+ * $Id: lirc_xbox.c,v 1.88 2011/06/03 11:11:11 jmartin Exp $ -+ */ -+ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include -+ -+//#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33) -+//#include -+//#endif -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+//#include "drivers/kcompat.h" -+//#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35) -+#include -+#include -+//#else -+//#include "drivers/lirc.h" -+//#include "drivers/lirc_dev/lirc_dev.h" -+//#endif -+ -+#define DRIVER_VERSION "$Revision: 0.01 $" -+#define DRIVER_AUTHOR "Jason Martin " -+#define DRIVER_DESC "XBOX DVD Dongle USB remote driver for LIRC" -+#define DRIVER_NAME "lirc_xbox" -+ -+#define CODE_LENGTH 6 -+#define CODE_MIN_LENGTH 6 -+#define DECODE_LENGTH 1 -+ -+#ifndef URB_ASYNC_UNLINK -+#define URB_ASYNC_UNLINK 0 -+#endif -+ -+/* module parameters */ -+#ifdef CONFIG_USB_DEBUG -+static int debug = 1; -+#else -+static int debug; -+#endif -+ -+#define dprintk(fmt, args...) \ -+ do { \ -+ if (debug) \ -+ printk(KERN_DEBUG fmt, ## args); \ -+ } while (0) -+ -+/* -+ * USB_BUFF_LEN must be the maximum value of the code_length array. -+ * It is used for static arrays. -+ */ -+#define USB_BUFF_LEN 6 -+ -+static int mask = 0xFFFF; /* channel acceptance bit mask */ -+static int unique; /* enable channel-specific codes */ -+static int repeat = 10; /* repeat time in 1/100 sec */ -+static unsigned long repeat_jiffies; /* repeat timeout */ -+ -+/* get hi and low bytes of a 16-bits int */ -+#define HI(a) ((unsigned char)((a) >> 8)) -+#define LO(a) ((unsigned char)((a) & 0xff)) -+ -+/* general constants */ -+#define SEND_FLAG_IN_PROGRESS 1 -+#define SEND_FLAG_COMPLETE 2 -+#define FREE_ALL 0xFF -+ -+/* endpoints */ -+#define EP_KEYS 0 -+#define EP_MOUSE 1 -+#define EP_MOUSE_ADDR 0x81 -+#define EP_KEYS_ADDR 0x82 -+ -+/* USB vendor ids for XBOX DVD Dongles */ -+#define VENDOR_MS1 0x040b -+#define VENDOR_MS2 0x045e -+#define VENDOR_MS3 0xFFFF -+ -+static struct usb_device_id usb_remote_table[] = { -+ /* Gamester Xbox DVD Movie Playback Kit IR */ -+ { USB_DEVICE(VENDOR_MS1, 0x6521) }, -+ -+ /* Microsoft Xbox DVD Movie Playback Kit IR */ -+ { USB_DEVICE(VENDOR_MS2, 0x0284) }, -+ -+ /* -+ * Some Chinese manufacturer -- conflicts with the joystick from the -+ * same manufacturer -+ */ -+ { USB_DEVICE(VENDOR_MS3, 0xFFFF) }, -+ -+ /* Terminating entry */ -+ { } -+}; -+ -+/* init strings */ -+#define USB_OUTLEN 7 -+ -+static char init1[] = {0x01, 0x00, 0x20, 0x14}; -+static char init2[] = {0x01, 0x00, 0x20, 0x14, 0x20, 0x20, 0x20}; -+ -+struct in_endpt { -+ /* inner link in list of endpoints for the remote specified by ir */ -+ struct list_head iep_list_link; -+ struct xbox_dev *ir; -+ struct urb *urb; -+ struct usb_endpoint_descriptor *ep; -+ -+ /* buffers and dma */ -+ unsigned char *buf; -+ unsigned int len; -+ dma_addr_t dma; -+ -+ /* handle repeats */ -+ unsigned char old[USB_BUFF_LEN]; -+ unsigned long old_jiffies; -+}; -+ -+struct out_endpt { -+ struct xbox_dev *ir; -+ struct urb *urb; -+ struct usb_endpoint_descriptor *ep; -+ -+ /* buffers and dma */ -+ unsigned char *buf; -+ dma_addr_t dma; -+ -+ /* handle sending (init strings) */ -+ int send_flags; -+ wait_queue_head_t wait; -+}; -+ -+ -+/* data structure for each usb remote */ -+struct xbox_dev { -+ /* inner link in list of all remotes managed by this module */ -+ struct list_head remote_list_link; -+ /* Number of usb interfaces associated with this device */ -+ int dev_refcount; -+ -+ /* usb */ -+ struct usb_device *usbdev; -+ /* Head link to list of all inbound endpoints in this remote */ -+ struct list_head iep_listhead; -+ struct out_endpt *out_init; -+ int devnum; -+ -+ /* lirc */ -+ struct lirc_driver *d; -+ int connected; -+ -+ /* locking */ -+ struct mutex lock; -+}; -+ -+/* list of all registered devices via the remote_list_link in xbox_dev */ -+static struct list_head remote_list; -+ -+/* -+ * Convenience macros to retrieve a pointer to the surrounding struct from -+ * the given list_head reference within, pointed at by link. -+ */ -+#define get_iep_from_link(link) \ -+ list_entry((link), struct in_endpt, iep_list_link); -+#define get_irctl_from_link(link) \ -+ list_entry((link), struct xbox_dev, remote_list_link); -+ -+/* send packet - used to initialize remote */ -+static void send_packet(struct out_endpt *oep, u16 cmd, unsigned char *data) -+{ -+ struct xbox_dev *ir = oep->ir; -+ DECLARE_WAITQUEUE(wait, current); -+ int timeout = HZ; /* 1 second */ -+ unsigned char buf[USB_OUTLEN]; -+ -+ dprintk(DRIVER_NAME "[%d]: send called (%#x)\n", ir->devnum, cmd); -+ -+ mutex_lock(&ir->lock); -+ oep->urb->transfer_buffer_length = LO(cmd) + 1; -+ oep->urb->dev = oep->ir->usbdev; -+ oep->send_flags = SEND_FLAG_IN_PROGRESS; -+ -+ memcpy(buf+1, data, LO(cmd)); -+ buf[0] = HI(cmd); -+ memcpy(oep->buf, buf, LO(cmd)+1); -+ -+ set_current_state(TASK_INTERRUPTIBLE); -+ add_wait_queue(&oep->wait, &wait); -+ -+ if (usb_submit_urb(oep->urb, GFP_ATOMIC)) { -+ set_current_state(TASK_RUNNING); -+ remove_wait_queue(&oep->wait, &wait); -+ mutex_unlock(&ir->lock); -+ return; -+ } -+ mutex_unlock(&ir->lock); -+ -+ while (timeout && (oep->urb->status == -EINPROGRESS) -+ && !(oep->send_flags & SEND_FLAG_COMPLETE)) { -+ timeout = schedule_timeout(timeout); -+ rmb(); -+ } -+ -+ dprintk(DRIVER_NAME "[%d]: send complete (%#x)\n", ir->devnum, cmd); -+ -+ set_current_state(TASK_RUNNING); -+ remove_wait_queue(&oep->wait, &wait); -+ oep->urb->transfer_flags |= URB_ASYNC_UNLINK; -+ usb_unlink_urb(oep->urb); -+} -+ -+static int unregister_from_lirc(struct xbox_dev *ir) -+{ -+ struct lirc_driver *d = ir->d; -+ int devnum; -+ -+ devnum = ir->devnum; -+ dprintk(DRIVER_NAME "[%d]: unregister from lirc called\n", devnum); -+ -+ lirc_unregister_driver(d->minor); -+ -+ printk(DRIVER_NAME "[%d]: usb remote disconnected\n", devnum); -+ return 0; -+} -+ -+static int set_use_inc(void *data) -+{ -+ struct xbox_dev *ir = data; -+ struct list_head *pos, *n; -+ struct in_endpt *iep; -+ int rtn; -+ -+ if (!ir) { -+ printk(DRIVER_NAME "[?]: set_use_inc called with no context\n"); -+ return -EIO; -+ } -+ dprintk(DRIVER_NAME "[%d]: set use inc\n", ir->devnum); -+ -+ mutex_lock(&ir->lock); -+ if (!ir->connected) { -+ if (!ir->usbdev) { -+ mutex_unlock(&ir->lock); -+ dprintk(DRIVER_NAME "[%d]: !ir->usbdev\n", ir->devnum); -+ return -ENOENT; -+ } -+ -+ /* Iterate through the inbound endpoints */ -+ list_for_each_safe(pos, n, &ir->iep_listhead) { -+ /* extract the current in_endpt */ -+ iep = get_iep_from_link(pos); -+ iep->urb->dev = ir->usbdev; -+ dprintk(DRIVER_NAME "[%d]: linking iep 0x%02x (%p)\n", -+ ir->devnum, iep->ep->bEndpointAddress, iep); -+ rtn = usb_submit_urb(iep->urb, GFP_ATOMIC); -+ if (rtn) { -+ printk(DRIVER_NAME "[%d]: open result = %d " -+ "error submitting urb\n", -+ ir->devnum, rtn); -+ mutex_unlock(&ir->lock); -+ return -EIO; -+ } -+ } -+ ir->connected = 1; -+ } -+ mutex_unlock(&ir->lock); -+ -+ return 0; -+} -+ -+static void set_use_dec(void *data) -+{ -+ struct xbox_dev *ir = data; -+ struct list_head *pos, *n; -+ struct in_endpt *iep; -+ -+ if (!ir) { -+ printk(DRIVER_NAME "[?]: set_use_dec called with no context\n"); -+ return; -+ } -+ dprintk(DRIVER_NAME "[%d]: set use dec\n", ir->devnum); -+ -+ mutex_lock(&ir->lock); -+ if (ir->connected) { -+ /* Free inbound usb urbs */ -+ list_for_each_safe(pos, n, &ir->iep_listhead) { -+ iep = get_iep_from_link(pos); -+ dprintk(DRIVER_NAME "[%d]: unlinking iep 0x%02x (%p)\n", -+ ir->devnum, iep->ep->bEndpointAddress, iep); -+ usb_kill_urb(iep->urb); -+ } -+ ir->connected = 0; -+ } -+ mutex_unlock(&ir->lock); -+} -+ -+static void print_data(struct in_endpt *iep, char *buf, int len) -+{ -+ const int clen = CODE_LENGTH; -+ char codes[clen * 3 + 1]; -+ int i; -+ -+ if (len <= 0) -+ return; -+ -+ for (i = 0; i < len && i < clen; i++) -+ snprintf(codes+i*3, 4, "%02x ", buf[i] & 0xFF); -+ printk(DRIVER_NAME "[%d]: data received %s (ep=0x%x length=%d)\n", -+ iep->ir->devnum, codes, iep->ep->bEndpointAddress, len); -+} -+ -+static int code_check_xbox(struct in_endpt *iep, int len) -+{ -+ // struct xbox_dev *ir = iep->ir; -+ const int clen = CODE_LENGTH; -+ -+ if (len != clen) { -+ dprintk(DRIVER_NAME ": We got %d instead of %d bytes from xbox " -+ "ir.. ?\n", len, clen); -+ return -1; -+ } -+ -+ /* check for repeats */ -+ if (memcmp(iep->old, iep->buf, len) == 0) { -+ if (iep->old_jiffies + repeat_jiffies > jiffies) -+ return -1; -+ } else { -+ /* -+ * the third byte of xbox ir packet seems to contain key info -+ * the last two bytes are.. some kind of clock? -+ */ -+ iep->buf[0] = iep->buf[2]; -+ memset(iep->buf + 1, 0, len - 1); -+ memcpy(iep->old, iep->buf, len); -+ } -+ iep->old_jiffies = jiffies; -+ -+ return 0; -+} -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19) -+static void usb_remote_recv(struct urb *urb, struct pt_regs *regs) -+#else -+static void usb_remote_recv(struct urb *urb) -+#endif -+{ -+ struct in_endpt *iep; -+ int len, result = -1; -+ -+ if (!urb) -+ return; -+ iep = urb->context; -+ if (!iep) { -+ urb->transfer_flags |= URB_ASYNC_UNLINK; -+ usb_unlink_urb(urb); -+ return; -+ } -+ if (!iep->ir->usbdev) -+ return; -+ -+ len = urb->actual_length; -+ if (debug) -+ print_data(iep, urb->transfer_buffer, len); -+ -+ switch (urb->status) { -+ -+ case 0: -+ result = code_check_xbox(iep, len); -+ -+ if (result < 0) -+ break; -+ -+ lirc_buffer_write(iep->ir->d->rbuf, iep->buf); -+ wake_up(&iep->ir->d->rbuf->wait_poll); -+ break; -+ -+ case -ECONNRESET: -+ case -ENOENT: -+ case -ESHUTDOWN: -+ urb->transfer_flags |= URB_ASYNC_UNLINK; -+ usb_unlink_urb(urb); -+ return; -+ -+ case -EPIPE: -+ default: -+ break; -+ } -+ -+ usb_submit_urb(urb, GFP_ATOMIC); -+} -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19) -+static void usb_remote_send(struct urb *urb, struct pt_regs *regs) -+#else -+static void usb_remote_send(struct urb *urb) -+#endif -+{ -+ struct out_endpt *oep; -+ -+ if (!urb) -+ return; -+ oep = urb->context; -+ if (!oep) { -+ urb->transfer_flags |= URB_ASYNC_UNLINK; -+ usb_unlink_urb(urb); -+ return; -+ } -+ if (!oep->ir->usbdev) -+ return; -+ -+ dprintk(DRIVER_NAME "[%d]: usb out called\n", oep->ir->devnum); -+ -+ if (urb->status) -+ return; -+ -+ oep->send_flags |= SEND_FLAG_COMPLETE; -+ wmb(); -+ if (waitqueue_active(&oep->wait)) -+ wake_up(&oep->wait); -+} -+ -+ -+/* -+ * Initialization and removal -+ */ -+ -+/* -+ * Free iep according to mem_failure which specifies a checkpoint into the -+ * initialization sequence for rollback recovery. -+ */ -+static void free_in_endpt(struct in_endpt *iep, int mem_failure) -+{ -+ struct xbox_dev *ir; -+ dprintk(DRIVER_NAME ": free_in_endpt(%p, %d)\n", iep, mem_failure); -+ if (!iep) -+ return; -+ -+ ir = iep->ir; -+ if (!ir) { -+ dprintk(DRIVER_NAME ": free_in_endpt: WARNING! null ir\n"); -+ return; -+ } -+ mutex_lock(&ir->lock); -+ switch (mem_failure) { -+ case FREE_ALL: -+ case 5: -+ list_del(&iep->iep_list_link); -+ dprintk(DRIVER_NAME "[%d]: free_in_endpt removing ep=0x%0x " -+ "from list\n", ir->devnum, iep->ep->bEndpointAddress); -+ case 4: -+ if (iep->urb) { -+ iep->urb->transfer_flags |= URB_ASYNC_UNLINK; -+ usb_unlink_urb(iep->urb); -+ usb_free_urb(iep->urb); -+ iep->urb = 0; -+ } else -+ dprintk(DRIVER_NAME "[%d]: free_in_endpt null urb!\n", -+ ir->devnum); -+ case 3: -+ usb_free_coherent(iep->ir->usbdev, iep->len, iep->buf, iep->dma); -+ iep->buf = 0; -+ case 2: -+ kfree(iep); -+ } -+ mutex_unlock(&ir->lock); -+} -+ -+/* -+ * Construct a new inbound endpoint for this remote, and add it to the list of -+ * in_epts in ir. -+ */ -+static struct in_endpt *new_in_endpt(struct xbox_dev *ir, -+ struct usb_endpoint_descriptor *ep) -+{ -+ struct usb_device *dev = ir->usbdev; -+ struct in_endpt *iep; -+ int pipe, maxp, len, addr; -+ int mem_failure; -+ -+ addr = ep->bEndpointAddress; -+ pipe = usb_rcvintpipe(dev, addr); -+ maxp = usb_maxpacket(dev, pipe, usb_pipeout(pipe)); -+ -+/* len = (maxp > USB_BUFLEN) ? USB_BUFLEN : maxp; -+ * len -= (len % CODE_LENGTH); */ -+ len = CODE_LENGTH; -+ -+ dprintk(DRIVER_NAME "[%d]: acceptable inbound endpoint (0x%x) found " -+ "(maxp=%d len=%d)\n", ir->devnum, addr, maxp, len); -+ -+ mem_failure = 0; -+ iep = kzalloc(sizeof(*iep), GFP_KERNEL); -+ if (!iep) { -+ mem_failure = 1; -+ goto new_in_endpt_failure_check; -+ } -+ iep->ir = ir; -+ iep->ep = ep; -+ iep->len = len; -+ -+ iep->buf = usb_alloc_coherent(dev, len, GFP_ATOMIC, &iep->dma); -+ if (!iep->buf) { -+ mem_failure = 2; -+ goto new_in_endpt_failure_check; -+ } -+ -+ iep->urb = usb_alloc_urb(0, GFP_KERNEL); -+ if (!iep->urb) -+ mem_failure = 3; -+ -+new_in_endpt_failure_check: -+ -+ if (mem_failure) { -+ free_in_endpt(iep, mem_failure); -+ printk(DRIVER_NAME "[%d]: ep=0x%x out of memory (code=%d)\n", -+ ir->devnum, addr, mem_failure); -+ return NULL; -+ } -+ list_add_tail(&iep->iep_list_link, &ir->iep_listhead); -+ dprintk(DRIVER_NAME "[%d]: adding ep=0x%0x to list\n", -+ ir->devnum, iep->ep->bEndpointAddress); -+ return iep; -+} -+ -+static void free_out_endpt(struct out_endpt *oep, int mem_failure) -+{ -+ struct xbox_dev *ir; -+ dprintk(DRIVER_NAME ": free_out_endpt(%p, %d)\n", oep, mem_failure); -+ if (!oep) -+ return; -+ -+ wake_up_all(&oep->wait); -+ -+ ir = oep->ir; -+ if (!ir) { -+ dprintk(DRIVER_NAME ": free_out_endpt: WARNING! null ir\n"); -+ return; -+ } -+ mutex_lock(&ir->lock); -+ switch (mem_failure) { -+ case FREE_ALL: -+ case 4: -+ if (oep->urb) { -+ oep->urb->transfer_flags |= URB_ASYNC_UNLINK; -+ usb_unlink_urb(oep->urb); -+ usb_free_urb(oep->urb); -+ oep->urb = 0; -+ } else { -+ dprintk(DRIVER_NAME "[%d]: free_out_endpt: null urb!\n", -+ ir->devnum); -+ } -+ case 3: -+ usb_free_coherent(oep->ir->usbdev, USB_OUTLEN, -+ oep->buf, oep->dma); -+ oep->buf = 0; -+ case 2: -+ kfree(oep); -+ } -+ mutex_unlock(&ir->lock); -+} -+ -+static struct out_endpt *new_out_endpt(struct xbox_dev *ir, -+ struct usb_endpoint_descriptor *ep) -+{ -+ struct usb_device *dev = ir->usbdev; -+ struct out_endpt *oep; -+ int mem_failure; -+ -+ dprintk(DRIVER_NAME "[%d]: acceptable outbound endpoint (0x%x) found\n", -+ ir->devnum, ep->bEndpointAddress); -+ -+ mem_failure = 0; -+ oep = kzalloc(sizeof(*oep), GFP_KERNEL); -+ if (!oep) -+ mem_failure = 1; -+ else { -+ oep->ir = ir; -+ oep->ep = ep; -+ init_waitqueue_head(&oep->wait); -+ -+ oep->buf = usb_alloc_coherent(dev, USB_OUTLEN, -+ GFP_ATOMIC, &oep->dma); -+ if (!oep->buf) -+ mem_failure = 2; -+ else { -+ oep->urb = usb_alloc_urb(0, GFP_KERNEL); -+ if (!oep->urb) -+ mem_failure = 3; -+ } -+ } -+ if (mem_failure) { -+ free_out_endpt(oep, mem_failure); -+ printk(DRIVER_NAME "[%d]: ep=0x%x out of memory (code=%d)\n", -+ ir->devnum, ep->bEndpointAddress, mem_failure); -+ return NULL; -+ } -+ return oep; -+} -+ -+static void free_irctl(struct xbox_dev *ir, int mem_failure) -+{ -+ struct list_head *pos, *n; -+ struct in_endpt *in; -+ dprintk(DRIVER_NAME ": free_irctl(%p, %d)\n", ir, mem_failure); -+ -+ if (!ir) -+ return; -+ -+ list_for_each_safe(pos, n, &ir->iep_listhead) { -+ in = get_iep_from_link(pos); -+ free_in_endpt(in, FREE_ALL); -+ } -+ if (ir->out_init) { -+ free_out_endpt(ir->out_init, FREE_ALL); -+ ir->out_init = NULL; -+ } -+ -+ mutex_lock(&ir->lock); -+ switch (mem_failure) { -+ case FREE_ALL: -+ case 6: -+ if (!--ir->dev_refcount) { -+ list_del(&ir->remote_list_link); -+ dprintk(DRIVER_NAME "[%d]: free_irctl: removing " -+ "remote from list\n", ir->devnum); -+ } else { -+ dprintk(DRIVER_NAME "[%d]: free_irctl: refcount at %d," -+ "aborting free_irctl\n", -+ ir->devnum, ir->dev_refcount); -+ mutex_unlock(&ir->lock); -+ return; -+ } -+ case 5: -+ case 4: -+ case 3: -+ if (ir->d) { -+ switch (mem_failure) { -+ case 5: -+ lirc_buffer_free(ir->d->rbuf); -+ case 4: -+ kfree(ir->d->rbuf); -+ case 3: -+ kfree(ir->d); -+ } -+ } else -+ printk(DRIVER_NAME "[%d]: ir->d is a null pointer!\n", -+ ir->devnum); -+ case 2: -+ mutex_unlock(&ir->lock); -+ kfree(ir); -+ return; -+ } -+ mutex_unlock(&ir->lock); -+} -+ -+static struct xbox_dev *new_irctl(struct usb_interface *intf) -+{ -+ struct usb_device *dev = interface_to_usbdev(intf); -+ struct xbox_dev *ir; -+ struct lirc_driver *driver; -+ int devnum, dclen; -+ int mem_failure; -+ -+ devnum = dev->devnum; -+ -+ dprintk(DRIVER_NAME "[%d]: remote type = XBOX DVD Dongle\n", devnum); -+ -+ mem_failure = 0; -+ ir = kzalloc(sizeof(*ir), GFP_KERNEL); -+ if (!ir) { -+ mem_failure = 1; -+ goto new_irctl_failure_check; -+ } -+ -+ dclen = DECODE_LENGTH; -+ -+ /* -+ * add this infrared remote struct to remote_list, keeping track -+ * of the number of drivers registered. -+ */ -+ dprintk(DRIVER_NAME "[%d]: adding remote to list\n", devnum); -+ list_add_tail(&ir->remote_list_link, &remote_list); -+ ir->dev_refcount = 1; -+ -+ driver = kzalloc(sizeof(*driver), GFP_KERNEL); -+ if (!driver) { -+ mem_failure = 2; -+ goto new_irctl_failure_check; -+ } -+ -+ ir->d = driver; -+ driver->rbuf = kmalloc(sizeof(*(driver->rbuf)), GFP_KERNEL); -+ if (!driver->rbuf) { -+ mem_failure = 3; -+ goto new_irctl_failure_check; -+ } -+ -+ if (lirc_buffer_init(driver->rbuf, dclen, 2)) { -+ mem_failure = 4; -+ goto new_irctl_failure_check; -+ } -+ -+ strcpy(driver->name, DRIVER_NAME " "); -+ driver->minor = -1; -+ driver->code_length = dclen * 8; -+ driver->features = LIRC_CAN_REC_LIRCCODE; -+ driver->data = ir; -+ driver->set_use_inc = &set_use_inc; -+ driver->set_use_dec = &set_use_dec; -+ driver->dev = &intf->dev; -+ driver->owner = THIS_MODULE; -+ ir->usbdev = dev; -+ ir->devnum = devnum; -+ -+ mutex_init(&ir->lock); -+ INIT_LIST_HEAD(&ir->iep_listhead); -+ -+new_irctl_failure_check: -+ -+ if (mem_failure) { -+ free_irctl(ir, mem_failure); -+ printk(DRIVER_NAME "[%d]: out of memory (code=%d)\n", -+ devnum, mem_failure); -+ return NULL; -+ } -+ return ir; -+} -+ -+/* -+ * Scan the global list of remotes to see if the device listed is one of them. -+ * If it is, the corresponding xbox_dev is returned, with its dev_refcount -+ * incremented. Otherwise, returns null. -+ */ -+static struct xbox_dev *get_prior_reg_ir(struct usb_device *dev) -+{ -+ struct list_head *pos; -+ struct xbox_dev *ir = NULL; -+ -+ dprintk(DRIVER_NAME "[%d]: scanning remote_list...\n", dev->devnum); -+ list_for_each(pos, &remote_list) { -+ ir = get_irctl_from_link(pos); -+ if (ir->usbdev != dev) { -+ dprintk(DRIVER_NAME "[%d]: device %d isn't it...", -+ dev->devnum, ir->devnum); -+ ir = NULL; -+ } else { -+ dprintk(DRIVER_NAME "[%d]: prior instance found.\n", -+ dev->devnum); -+ ir->dev_refcount++; -+ break; -+ } -+ } -+ return ir; -+} -+ -+/* -+ * If the USB interface has an out endpoint for control. -+ */ -+static void send_outbound_init(struct xbox_dev *ir) -+{ -+ if (ir->out_init) { -+ struct out_endpt *oep = ir->out_init; -+ dprintk(DRIVER_NAME "[%d]: usb_remote_probe: initializing " -+ "outbound ep\n", ir->devnum); -+ usb_fill_int_urb(oep->urb, ir->usbdev, -+ usb_sndintpipe(ir->usbdev, oep->ep->bEndpointAddress), -+ oep->buf, USB_OUTLEN, usb_remote_send, -+ oep, oep->ep->bInterval); -+ oep->urb->transfer_dma = oep->dma; -+ oep->urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; -+ -+ send_packet(oep, 0x8004, init1); -+ send_packet(oep, 0x8007, init2); -+ } -+} -+ -+/* Log driver and usb info */ -+static void log_usb_dev_info(struct usb_device *dev) -+{ -+ char buf[63], name[128] = ""; -+ -+ if (dev->descriptor.iManufacturer -+ && usb_string(dev, dev->descriptor.iManufacturer, -+ buf, sizeof(buf)) > 0) -+ strlcpy(name, buf, sizeof(name)); -+ if (dev->descriptor.iProduct -+ && usb_string(dev, dev->descriptor.iProduct, buf, sizeof(buf)) > 0) -+ snprintf(name + strlen(name), sizeof(name) - strlen(name), -+ " %s", buf); -+ printk(DRIVER_NAME "[%d]: %s on usb%d:%d\n", dev->devnum, name, -+ dev->bus->busnum, dev->devnum); -+} -+ -+ -+static int usb_remote_probe(struct usb_interface *intf, -+ const struct usb_device_id *id) -+{ -+ struct usb_device *dev = interface_to_usbdev(intf); -+ struct usb_host_interface *idesc; -+ struct usb_endpoint_descriptor *ep; -+ struct in_endpt *iep; -+ struct xbox_dev *ir; -+ int i; -+ -+ dprintk(DRIVER_NAME "[%d]: usb_remote_probe: dev:%p, intf:%p, id:%p)\n", -+ dev->devnum, dev, intf, id); -+ -+ idesc = intf->cur_altsetting; -+ -+ /* Check if a usb remote has already been registered for this device */ -+ ir = get_prior_reg_ir(dev); -+ -+ if (!ir) { -+ ir = new_irctl(intf); -+ if (!ir) -+ return -ENOMEM; -+ } -+ -+ /* -+ * step through the endpoints to find first in and first out endpoint -+ * of type interrupt transfer -+ */ -+ for (i = 0; i < idesc->desc.bNumEndpoints; ++i) { -+ ep = &idesc->endpoint[i].desc; -+ dprintk(DRIVER_NAME "[%d]: processing endpoint %d\n", -+ dev->devnum, i); -+ if (((ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == -+ USB_DIR_IN) && -+ ((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == -+ USB_ENDPOINT_XFER_INT)) { -+ -+ iep = new_in_endpt(ir, ep); -+ if (iep) -+ { -+ usb_fill_int_urb(iep->urb, dev, -+ usb_rcvintpipe(dev, -+ iep->ep->bEndpointAddress), -+ iep->buf, iep->len, usb_remote_recv, -+ iep, iep->ep->bInterval); -+ iep->urb->transfer_dma = iep->dma; -+ iep->urb->transfer_flags |= -+ URB_NO_TRANSFER_DMA_MAP; -+ } -+ } -+ -+ if (((ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == -+ USB_DIR_OUT) && -+ ((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == -+ USB_ENDPOINT_XFER_INT) && -+ (ir->out_init == NULL)) -+ ir->out_init = new_out_endpt(ir, ep); -+ } -+ if (list_empty(&ir->iep_listhead)) { -+ printk(DRIVER_NAME "[%d]: inbound endpoint not found\n", -+ ir->devnum); -+ free_irctl(ir, FREE_ALL); -+ return -ENODEV; -+ } -+ if (ir->dev_refcount == 1) { -+ ir->d->minor = lirc_register_driver(ir->d); -+ if (ir->d->minor < 0) { -+ free_irctl(ir, FREE_ALL); -+ return -ENODEV; -+ } -+ -+ /* Note new driver registration in kernel logs */ -+ log_usb_dev_info(dev); -+ -+ /* outbound data (initialization) */ -+ send_outbound_init(ir); -+ } -+ -+ usb_set_intfdata(intf, ir); -+ return 0; -+} -+ -+static void usb_remote_disconnect(struct usb_interface *intf) -+{ -+ /* struct usb_device *dev = interface_to_usbdev(intf); */ -+ struct xbox_dev *ir = usb_get_intfdata(intf); -+ usb_set_intfdata(intf, NULL); -+ -+ dprintk(DRIVER_NAME ": disconnecting remote %d:\n", -+ (ir ? ir->devnum : -1)); -+ if (!ir || !ir->d) -+ return; -+ -+ if (ir->usbdev) { -+ /* Only unregister once */ -+ ir->usbdev = NULL; -+ unregister_from_lirc(ir); -+ } -+ -+ /* This also removes the current remote from remote_list */ -+ free_irctl(ir, FREE_ALL); -+} -+ -+static struct usb_driver usb_remote_driver = { -+ .name = DRIVER_NAME, -+ .probe = usb_remote_probe, -+ .disconnect = usb_remote_disconnect, -+ .id_table = usb_remote_table -+}; -+ -+static int __init usb_remote_init(void) -+{ -+ int i; -+ -+ INIT_LIST_HEAD(&remote_list); -+ -+ printk(KERN_INFO "\n" DRIVER_NAME ": " DRIVER_DESC " " -+ DRIVER_VERSION "\n"); -+ printk(DRIVER_NAME ": " DRIVER_AUTHOR "\n"); -+ dprintk(DRIVER_NAME ": debug mode enabled: " -+ "$Id: lirc_xbox.c,v 1.88 2011/06/05 11:11:11 jmartin Exp $\n"); -+ -+ repeat_jiffies = repeat*HZ/100; -+ -+ i = usb_register(&usb_remote_driver); -+ if (i) { -+ printk(DRIVER_NAME ": usb register failed, result = %d\n", i); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ -+static void __exit usb_remote_exit(void) -+{ -+ usb_deregister(&usb_remote_driver); -+} -+ -+module_init(usb_remote_init); -+module_exit(usb_remote_exit); -+ -+MODULE_DESCRIPTION(DRIVER_DESC); -+MODULE_AUTHOR(DRIVER_AUTHOR); -+MODULE_LICENSE("GPL"); -+MODULE_DEVICE_TABLE(usb, usb_remote_table); -+ -+module_param(debug, bool, S_IRUGO | S_IWUSR); -+MODULE_PARM_DESC(debug, "Debug enabled or not (default: 0)"); -+ -+module_param(mask, int, S_IRUGO | S_IWUSR); -+MODULE_PARM_DESC(mask, "Set channel acceptance bit mask (default: 0xFFFF)"); -+ -+module_param(unique, bool, S_IRUGO | S_IWUSR); -+MODULE_PARM_DESC(unique, "Enable channel-specific codes (default: 0)"); -+ -+module_param(repeat, int, S_IRUGO | S_IWUSR); -+MODULE_PARM_DESC(repeat, "Repeat timeout (1/100 sec) (default: 10)"); -diff -Naur linux-3.9.4/drivers/staging/media/lirc/Makefile linux-3.9.4.patch/drivers/staging/media/lirc/Makefile ---- linux-3.9.4/drivers/staging/media/lirc/Makefile 2013-05-24 20:45:59.000000000 +0200 -+++ linux-3.9.4.patch/drivers/staging/media/lirc/Makefile 2013-05-30 18:17:39.163634834 +0200 -@@ -10,4 +10,5 @@ - obj-$(CONFIG_LIRC_SASEM) += lirc_sasem.o - obj-$(CONFIG_LIRC_SERIAL) += lirc_serial.o - obj-$(CONFIG_LIRC_SIR) += lirc_sir.o -+obj-$(CONFIG_LIRC_XBOX) += lirc_xbox.o - obj-$(CONFIG_LIRC_ZILOG) += lirc_zilog.o diff --git a/packages/linux/patches/3.11.6/linux-053-spinelplus-remote-0.2.patch b/packages/linux/patches/3.11.6/linux-053-spinelplus-remote-0.2.patch deleted file mode 100644 index f110183d85..0000000000 --- a/packages/linux/patches/3.11.6/linux-053-spinelplus-remote-0.2.patch +++ /dev/null @@ -1,161 +0,0 @@ -diff -Naur linux-3.9/drivers/hid/hid-core.c linux-3.9.patch/drivers/hid/hid-core.c ---- linux-3.9/drivers/hid/hid-core.c 2013-04-29 02:36:01.000000000 +0200 -+++ linux-3.9.patch/drivers/hid/hid-core.c 2013-04-29 17:08:40.528324010 +0200 -@@ -1681,6 +1681,9 @@ - { HID_USB_DEVICE(USB_VENDOR_ID_ORTEK, USB_DEVICE_ID_ORTEK_PKB1700) }, - { HID_USB_DEVICE(USB_VENDOR_ID_ORTEK, USB_DEVICE_ID_ORTEK_WKB2000) }, - { HID_USB_DEVICE(USB_VENDOR_ID_PETALYNX, USB_DEVICE_ID_PETALYNX_MAXTER_REMOTE) }, -+ { HID_USB_DEVICE(USB_VENDOR_ID_PHILIPS, USB_DEVICE_ID_PHILIPS_SPINEL_PLUS_1) }, -+ { HID_USB_DEVICE(USB_VENDOR_ID_PHILIPS, USB_DEVICE_ID_PHILIPS_SPINEL_PLUS_2) }, -+ { HID_USB_DEVICE(USB_VENDOR_ID_PHILIPS, USB_DEVICE_ID_PHILIPS_SPINEL_PLUS_3) }, - { HID_USB_DEVICE(USB_VENDOR_ID_PRIMAX, USB_DEVICE_ID_PRIMAX_KEYBOARD) }, - #if IS_ENABLED(CONFIG_HID_ROCCAT) - { HID_USB_DEVICE(USB_VENDOR_ID_ROCCAT, USB_DEVICE_ID_ROCCAT_KONE) }, -diff -Naur linux-3.9/drivers/hid/hid-ids.h linux-3.9.patch/drivers/hid/hid-ids.h ---- linux-3.9/drivers/hid/hid-ids.h 2013-04-29 02:36:01.000000000 +0200 -+++ linux-3.9.patch/drivers/hid/hid-ids.h 2013-04-29 17:08:40.537323981 +0200 -@@ -663,6 +663,9 @@ - - #define USB_VENDOR_ID_PHILIPS 0x0471 - #define USB_DEVICE_ID_PHILIPS_IEEE802154_DONGLE 0x0617 -+#define USB_DEVICE_ID_PHILIPS_SPINEL_PLUS_1 0x206c -+#define USB_DEVICE_ID_PHILIPS_SPINEL_PLUS_2 0x20cc -+#define USB_DEVICE_ID_PHILIPS_SPINEL_PLUS_3 0x0613 - - #define USB_VENDOR_ID_PI_ENGINEERING 0x05f3 - #define USB_DEVICE_ID_PI_ENGINEERING_VEC_USB_FOOTPEDAL 0xff -diff -Naur linux-3.9/drivers/hid/hid-spinelplus.c linux-3.9.patch/drivers/hid/hid-spinelplus.c ---- linux-3.9/drivers/hid/hid-spinelplus.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-3.9.patch/drivers/hid/hid-spinelplus.c 2013-04-29 17:08:40.537323981 +0200 -@@ -0,0 +1,104 @@ -+/* -+ * HID driver for "PHILIPS MCE USB IR Receiver- Spinel plus" remotes -+ * -+ * Copyright (c) 2010 Panagiotis Skintzos -+ * -+ * Renamed to Spinel, cleanup and modified to also support -+ * Spinel Plus 0471:20CC by Stephan Raue 2012. -+ */ -+ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the Free -+ * Software Foundation; either version 2 of the License, or (at your option) -+ * any later version. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "hid-ids.h" -+ -+#define spinelplus_map_key(c) set_bit(EV_REP, hi->input->evbit); \ -+ hid_map_usage_clear(hi, usage, bit, max, EV_KEY, (c)) -+ -+static int spinelplus_input_mapping(struct hid_device *hdev, -+ struct hid_input *hi, struct hid_field *field, struct hid_usage *usage, -+ unsigned long **bit, int *max) -+{ -+ switch (usage->hid) { -+ case 0xffbc000d: spinelplus_map_key(KEY_MEDIA); break; -+ case 0xffbc0024: spinelplus_map_key(KEY_MEDIA); break; -+ case 0xffbc0027: spinelplus_map_key(KEY_ZOOM); break; -+ case 0xffbc0033: spinelplus_map_key(KEY_HOME); break; -+ case 0xffbc0035: spinelplus_map_key(KEY_CAMERA); break; -+ case 0xffbc0036: spinelplus_map_key(KEY_EPG); break; -+ case 0xffbc0037: spinelplus_map_key(KEY_DVD); break; -+ case 0xffbc0038: spinelplus_map_key(KEY_HOME); break; -+ case 0xffbc0039: spinelplus_map_key(KEY_MP3); break; -+ case 0xffbc003a: spinelplus_map_key(KEY_VIDEO); break; -+ case 0xffbc005a: spinelplus_map_key(KEY_TEXT); break; -+ case 0xffbc005b: spinelplus_map_key(KEY_RED); break; -+ case 0xffbc005c: spinelplus_map_key(KEY_GREEN); break; -+ case 0xffbc005d: spinelplus_map_key(KEY_YELLOW); break; -+ case 0xffbc005e: spinelplus_map_key(KEY_BLUE); break; -+ default: -+ return 0; -+ } -+ return 1; -+} -+ -+static int spinelplus_probe(struct hid_device *hdev, -+ const struct hid_device_id *id) -+{ -+ int ret; -+ /* Connect only to hid input (not hiddev & hidraw)*/ -+ unsigned int cmask = HID_CONNECT_HIDINPUT; -+ -+ ret = hid_parse(hdev); -+ if (ret) { -+ dev_err(&hdev->dev, "parse failed\n"); -+ goto err_free; -+ } -+ -+ ret = hid_hw_start(hdev, cmask); -+ if (ret) { -+ dev_err(&hdev->dev, "hw start failed\n"); -+ goto err_free; -+ } -+ -+ return 0; -+err_free: -+ return ret; -+} -+ -+static const struct hid_device_id spinelplus_devices[] = { -+ { HID_USB_DEVICE(USB_VENDOR_ID_PHILIPS,USB_DEVICE_ID_PHILIPS_SPINEL_PLUS_1) }, -+ { HID_USB_DEVICE(USB_VENDOR_ID_PHILIPS,USB_DEVICE_ID_PHILIPS_SPINEL_PLUS_2) }, -+ { HID_USB_DEVICE(USB_VENDOR_ID_PHILIPS,USB_DEVICE_ID_PHILIPS_SPINEL_PLUS_3) }, -+ { } -+}; -+MODULE_DEVICE_TABLE(hid, spinelplus_devices); -+ -+static struct hid_driver spinelplus_driver = { -+ .name = "SpinelPlus", -+ .id_table = spinelplus_devices, -+ .input_mapping = spinelplus_input_mapping, -+ .probe = spinelplus_probe, -+}; -+ -+static int __init spinelplus_init(void) -+{ -+ return hid_register_driver(&spinelplus_driver); -+} -+ -+static void __exit spinelplus_exit(void) -+{ -+ hid_unregister_driver(&spinelplus_driver); -+} -+ -+module_init(spinelplus_init); -+module_exit(spinelplus_exit); -+MODULE_LICENSE("GPL"); -diff -Naur linux-3.9/drivers/hid/Kconfig linux-3.9.patch/drivers/hid/Kconfig ---- linux-3.9/drivers/hid/Kconfig 2013-04-29 02:36:01.000000000 +0200 -+++ linux-3.9.patch/drivers/hid/Kconfig 2013-04-29 17:08:40.538323977 +0200 -@@ -602,6 +602,12 @@ - ---help--- - Support for Steelseries SRW-S1 steering wheel - -+config HID_SPINELPLUS -+ tristate "Spinel Plus remote control" -+ depends on USB_HID -+ ---help--- -+ Say Y here if you have a Spinel Plus (0471:206c/20cc/0613) remote -+ - config HID_SUNPLUS - tristate "Sunplus wireless desktop" - depends on USB_HID -diff -Naur linux-3.9/drivers/hid/Makefile linux-3.9.patch/drivers/hid/Makefile ---- linux-3.9/drivers/hid/Makefile 2013-04-29 02:36:01.000000000 +0200 -+++ linux-3.9.patch/drivers/hid/Makefile 2013-04-29 17:09:26.744173841 +0200 -@@ -101,6 +101,7 @@ - obj-$(CONFIG_HID_SMARTJOYPLUS) += hid-sjoy.o - obj-$(CONFIG_HID_SONY) += hid-sony.o - obj-$(CONFIG_HID_SPEEDLINK) += hid-speedlink.o -+obj-$(CONFIG_HID_SPINELPLUS) += hid-spinelplus.o - obj-$(CONFIG_HID_STEELSERIES) += hid-steelseries.o - obj-$(CONFIG_HID_SUNPLUS) += hid-sunplus.o - obj-$(CONFIG_HID_GREENASIA) += hid-gaff.o diff --git a/packages/linux/patches/3.11.6/linux-054-nuvoton_revert_d7b290a1056c5564eec8a1b169c6e84ff3.6.114c13.patch b/packages/linux/patches/3.11.6/linux-054-nuvoton_revert_d7b290a1056c5564eec8a1b169c6e84ff3.6.114c13.patch deleted file mode 100644 index 08566d1f13..0000000000 --- a/packages/linux/patches/3.11.6/linux-054-nuvoton_revert_d7b290a1056c5564eec8a1b169c6e84ff3.6.114c13.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Naur linux-3.0/drivers/media/rc/nuvoton-cir.c linux-3.0.patch/drivers/media/rc/nuvoton-cir.c ---- linux-3.0/drivers/media/rc/nuvoton-cir.c 2011-07-22 04:17:23.000000000 +0200 -+++ linux-3.0.patch/drivers/media/rc/nuvoton-cir.c 2011-07-22 21:30:48.374591146 +0200 -@@ -1110,7 +1110,7 @@ - rdev->dev.parent = &pdev->dev; - rdev->driver_name = NVT_DRIVER_NAME; - rdev->map_name = RC_MAP_RC6_MCE; -- rdev->timeout = MS_TO_NS(100); -+ rdev->timeout = US_TO_NS(1000); - /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */ - rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD); - #if 0 diff --git a/packages/linux/patches/3.11.6/linux-055-add_Formosa_eHome_Infrared_Receiver.patch b/packages/linux/patches/3.11.6/linux-055-add_Formosa_eHome_Infrared_Receiver.patch deleted file mode 100644 index e2afb63e3d..0000000000 --- a/packages/linux/patches/3.11.6/linux-055-add_Formosa_eHome_Infrared_Receiver.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- linux-3.2.2.orig/drivers/media/rc/mceusb.c 2012-01-30 23:37:12.374473509 +0100 -+++ linux-3.2.2/drivers/media/rc/mceusb.c 2012-01-30 23:40:57.989652931 +0100 -@@ -350,6 +350,8 @@ - { USB_DEVICE(VENDOR_FORMOSA, 0xe015) }, - /* Formosa21 / eHome Infrared Receiver */ - { USB_DEVICE(VENDOR_FORMOSA, 0xe016) }, -+ /* Formosa21 / eHome Infrared Receiver */ -+ { USB_DEVICE(VENDOR_FORMOSA, 0xe042) }, - /* Formosa aim / Trust MCE Infrared Receiver */ - { USB_DEVICE(VENDOR_FORMOSA, 0xe017), - .driver_info = MCE_GEN2_NO_TX }, diff --git a/packages/linux/patches/3.11.6/linux-056-add_Adaptec_eHome_Infrared_Receiver.patch b/packages/linux/patches/3.11.6/linux-056-add_Adaptec_eHome_Infrared_Receiver.patch deleted file mode 100644 index 461a82e4d5..0000000000 --- a/packages/linux/patches/3.11.6/linux-056-add_Adaptec_eHome_Infrared_Receiver.patch +++ /dev/null @@ -1,20 +0,0 @@ -diff -Naur linux-3.6.7/drivers/media/rc/mceusb.c linux-3.6.7.patch/drivers/media/rc/mceusb.c ---- linux-3.6.7/drivers/media/rc/mceusb.c 2012-11-29 04:45:51.142129739 +0100 -+++ linux-3.6.7.patch/drivers/media/rc/mceusb.c 2012-11-29 04:51:30.982828558 +0100 -@@ -200,6 +200,7 @@ - #define VENDOR_TIVO 0x105a - #define VENDOR_CONEXANT 0x0572 - #define VENDOR_TWISTEDMELON 0x2596 -+#define VENDOR_ADAPTEC 0x03f3 - - enum mceusb_model_type { - MCE_GEN2 = 0, /* Most boards */ -@@ -400,6 +401,8 @@ - { USB_DEVICE(VENDOR_TWISTEDMELON, 0x8016) }, - /* Twisted Melon Inc. - Manta Transceiver */ - { USB_DEVICE(VENDOR_TWISTEDMELON, 0x8042) }, -+ /* Adaptec / HP eHome Receiver */ -+ { USB_DEVICE(VENDOR_ADAPTEC, 0x0094) }, - /* Terminating entry */ - { } - }; diff --git a/packages/linux/patches/3.11.6/linux-057-Removed-MCE-customer-code-restriction-in-rc6-decode.patch b/packages/linux/patches/3.11.6/linux-057-Removed-MCE-customer-code-restriction-in-rc6-decode.patch deleted file mode 100644 index 9f84e6659f..0000000000 --- a/packages/linux/patches/3.11.6/linux-057-Removed-MCE-customer-code-restriction-in-rc6-decode.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- linux/drivers/media/rc/ir-rc6-decoder.c 2012-11-25 22:08:13.148418669 -0800 -+++ linux.patch/drivers/media/rc/ir-rc6-decoder.c 2012-11-25 22:07:48.864417975 -0800 -@@ -39,7 +39,6 @@ - #define RC6_STARTBIT_MASK 0x08 /* for the header bits */ - #define RC6_6A_MCE_TOGGLE_MASK 0x8000 /* for the body bits */ - #define RC6_6A_LCC_MASK 0xffff0000 /* RC6-6A-32 long customer code mask */ --#define RC6_6A_MCE_CC 0x800f0000 /* MCE customer code */ - #ifndef CHAR_BIT - #define CHAR_BIT 8 /* Normally in */ - #endif -@@ -242,9 +241,8 @@ again: - } - - scancode = data->body; -- if (data->count == RC6_6A_32_NBITS && -- (scancode & RC6_6A_LCC_MASK) == RC6_6A_MCE_CC) { -- /* MCE RC */ -+ if (data->count == RC6_6A_32_NBITS) { -+ /* MCE compatible RC */ - toggle = (scancode & RC6_6A_MCE_TOGGLE_MASK) ? 1 : 0; - scancode &= ~RC6_6A_MCE_TOGGLE_MASK; - } else { diff --git a/packages/linux/patches/3.11.6/linux-057-add_SMK_Manufacturing_Inc_Infrared_Receiver.patch b/packages/linux/patches/3.11.6/linux-057-add_SMK_Manufacturing_Inc_Infrared_Receiver.patch deleted file mode 100644 index 67fc7a0de8..0000000000 --- a/packages/linux/patches/3.11.6/linux-057-add_SMK_Manufacturing_Inc_Infrared_Receiver.patch +++ /dev/null @@ -1,13 +0,0 @@ -diff -Naur linux-3.9.4/drivers/media/rc/mceusb.c linux-3.9.4.patch/drivers/media/rc/mceusb.c ---- linux-3.9.4/drivers/media/rc/mceusb.c 2013-05-24 20:45:59.000000000 +0200 -+++ linux-3.9.4.patch/drivers/media/rc/mceusb.c 2013-05-27 12:28:12.811230633 +0200 -@@ -309,6 +309,9 @@ - /* SMK/I-O Data GV-MC7/RCKIT Receiver */ - { USB_DEVICE(VENDOR_SMK, 0x0353), - .driver_info = MCE_GEN2_NO_TX }, -+ /* SMK Manufacturing, Inc. Receiver */ -+ { USB_DEVICE(VENDOR_SMK, 0x0357), -+ .driver_info = MCE_GEN2_NO_TX }, - /* Tatung eHome Infrared Transceiver */ - { USB_DEVICE(VENDOR_TATUNG, 0x9150) }, - /* Shuttle eHome Infrared Transceiver */ diff --git a/packages/linux/patches/3.11.6/linux-058.01-HID-Sony-upstream_patches.patch.todo-or-remove b/packages/linux/patches/3.11.6/linux-058.01-HID-Sony-upstream_patches.patch.todo-or-remove deleted file mode 100644 index 2995d9d8bb..0000000000 --- a/packages/linux/patches/3.11.6/linux-058.01-HID-Sony-upstream_patches.patch.todo-or-remove +++ /dev/null @@ -1,867 +0,0 @@ -diff --git a/drivers/hid/Kconfig b/drivers/hid/Kconfig -index 427b759..22d320e 100644 ---- a/drivers/hid/Kconfig -+++ b/drivers/hid/Kconfig -@@ -561,15 +561,6 @@ config HID_PRIMAX - Support for Primax devices that are not fully compliant with the - HID standard. - --config HID_PS3REMOTE -- tristate "Sony PS3 BD Remote Control" -- depends on HID -- ---help--- -- Support for the Sony PS3 Blue-ray Disk Remote Control and Logitech -- Harmony Adapter for PS3, which connect over Bluetooth. -- -- Support for the 6-axis controllers is provided by HID_SONY. -- - config HID_ROCCAT - tristate "Roccat device support" - depends on USB_HID -@@ -594,12 +585,17 @@ config HID_SAMSUNG - Support for Samsung InfraRed remote control or keyboards. - - config HID_SONY -- tristate "Sony PS3 controller" -+ tristate "Sony PS2/3 accessories" - depends on USB_HID -+ depends on NEW_LEDS -+ depends on LEDS_CLASS - ---help--- -- Support for Sony PS3 6-axis controllers. -- -- Support for the Sony PS3 BD Remote is provided by HID_PS3REMOTE. -+ Support for -+ -+ * Sony PS3 6-axis controllers -+ * Buzz controllers -+ * Sony PS3 Blue-ray Disk Remote Control (Bluetooth) -+ * Logitech Harmony adapter for Sony Playstation 3 (Bluetooth) - - config HID_SPEEDLINK - tristate "Speedlink VAD Cezanne mouse support" -diff --git a/drivers/hid/Makefile b/drivers/hid/Makefile -index b545124..419b7ca 100644 ---- a/drivers/hid/Makefile -+++ b/drivers/hid/Makefile -@@ -92,7 +92,6 @@ hid-picolcd-y += hid-picolcd_debugfs.o - endif - - obj-$(CONFIG_HID_PRIMAX) += hid-primax.o --obj-$(CONFIG_HID_PS3REMOTE) += hid-ps3remote.o - obj-$(CONFIG_HID_ROCCAT) += hid-roccat.o hid-roccat-common.o \ - hid-roccat-arvo.o hid-roccat-isku.o hid-roccat-kone.o \ - hid-roccat-koneplus.o hid-roccat-konepure.o hid-roccat-kovaplus.o \ -diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c -index b885a28..37e35c0 100644 ---- a/drivers/hid/hid-core.c -+++ b/drivers/hid/hid-core.c -@@ -1683,6 +1683,8 @@ static const struct hid_device_id hid_have_special_driver[] = { - { HID_USB_DEVICE(USB_VENDOR_ID_SAMSUNG, USB_DEVICE_ID_SAMSUNG_IR_REMOTE) }, - { HID_USB_DEVICE(USB_VENDOR_ID_SAMSUNG, USB_DEVICE_ID_SAMSUNG_WIRELESS_KBD_MOUSE) }, - { HID_USB_DEVICE(USB_VENDOR_ID_SKYCABLE, USB_DEVICE_ID_SKYCABLE_WIRELESS_PRESENTER) }, -+ { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_BUZZ_CONTROLLER) }, -+ { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_WIRELESS_BUZZ_CONTROLLER) }, - { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_PS3_BDREMOTE) }, - { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_PS3_CONTROLLER) }, - { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_NAVIGATION_CONTROLLER) }, -diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h -index 56b224e..c11cca1 100644 ---- a/drivers/hid/hid-ids.h -+++ b/drivers/hid/hid-ids.h -@@ -737,6 +737,8 @@ - #define USB_DEVICE_ID_SONY_PS3_BDREMOTE 0x0306 - #define USB_DEVICE_ID_SONY_PS3_CONTROLLER 0x0268 - #define USB_DEVICE_ID_SONY_NAVIGATION_CONTROLLER 0x042f -+#define USB_DEVICE_ID_SONY_BUZZ_CONTROLLER 0x0002 -+#define USB_DEVICE_ID_SONY_WIRELESS_BUZZ_CONTROLLER 0x1000 - - #define USB_VENDOR_ID_SOUNDGRAPH 0x15c2 - #define USB_DEVICE_ID_SOUNDGRAPH_IMON_FIRST 0x0034 -diff --git a/drivers/hid/hid-ps3remote.c b/drivers/hid/hid-ps3remote.c -deleted file mode 100644 -index f1239d3..0000000 ---- a/drivers/hid/hid-ps3remote.c -+++ /dev/null -@@ -1,204 +0,0 @@ --/* -- * HID driver for Sony PS3 BD Remote Control -- * -- * Copyright (c) 2012 David Dillow -- * Based on a blend of the bluez fakehid user-space code by Marcel Holtmann -- * and other kernel HID drivers. -- */ -- --/* -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License as published by the Free -- * Software Foundation; either version 2 of the License, or (at your option) -- * any later version. -- */ -- --/* NOTE: in order for the Sony PS3 BD Remote Control to be found by -- * a Bluetooth host, the key combination Start+Enter has to be kept pressed -- * for about 7 seconds with the Bluetooth Host Controller in discovering mode. -- * -- * There will be no PIN request from the device. -- */ -- --#include --#include --#include -- --#include "hid-ids.h" -- --static __u8 ps3remote_rdesc[] = { -- 0x05, 0x01, /* GUsagePage Generic Desktop */ -- 0x09, 0x05, /* LUsage 0x05 [Game Pad] */ -- 0xA1, 0x01, /* MCollection Application (mouse, keyboard) */ -- -- /* Use collection 1 for joypad buttons */ -- 0xA1, 0x02, /* MCollection Logical (interrelated data) */ -- -- /* Ignore the 1st byte, maybe it is used for a controller -- * number but it's not needed for correct operation */ -- 0x75, 0x08, /* GReportSize 0x08 [8] */ -- 0x95, 0x01, /* GReportCount 0x01 [1] */ -- 0x81, 0x01, /* MInput 0x01 (Const[0] Arr[1] Abs[2]) */ -- -- /* Bytes from 2nd to 4th are a bitmap for joypad buttons, for these -- * buttons multiple keypresses are allowed */ -- 0x05, 0x09, /* GUsagePage Button */ -- 0x19, 0x01, /* LUsageMinimum 0x01 [Button 1 (primary/trigger)] */ -- 0x29, 0x18, /* LUsageMaximum 0x18 [Button 24] */ -- 0x14, /* GLogicalMinimum [0] */ -- 0x25, 0x01, /* GLogicalMaximum 0x01 [1] */ -- 0x75, 0x01, /* GReportSize 0x01 [1] */ -- 0x95, 0x18, /* GReportCount 0x18 [24] */ -- 0x81, 0x02, /* MInput 0x02 (Data[0] Var[1] Abs[2]) */ -- -- 0xC0, /* MEndCollection */ -- -- /* Use collection 2 for remote control buttons */ -- 0xA1, 0x02, /* MCollection Logical (interrelated data) */ -- -- /* 5th byte is used for remote control buttons */ -- 0x05, 0x09, /* GUsagePage Button */ -- 0x18, /* LUsageMinimum [No button pressed] */ -- 0x29, 0xFE, /* LUsageMaximum 0xFE [Button 254] */ -- 0x14, /* GLogicalMinimum [0] */ -- 0x26, 0xFE, 0x00, /* GLogicalMaximum 0x00FE [254] */ -- 0x75, 0x08, /* GReportSize 0x08 [8] */ -- 0x95, 0x01, /* GReportCount 0x01 [1] */ -- 0x80, /* MInput */ -- -- /* Ignore bytes from 6th to 11th, 6th to 10th are always constant at -- * 0xff and 11th is for press indication */ -- 0x75, 0x08, /* GReportSize 0x08 [8] */ -- 0x95, 0x06, /* GReportCount 0x06 [6] */ -- 0x81, 0x01, /* MInput 0x01 (Const[0] Arr[1] Abs[2]) */ -- -- /* 12th byte is for battery strength */ -- 0x05, 0x06, /* GUsagePage Generic Device Controls */ -- 0x09, 0x20, /* LUsage 0x20 [Battery Strength] */ -- 0x14, /* GLogicalMinimum [0] */ -- 0x25, 0x05, /* GLogicalMaximum 0x05 [5] */ -- 0x75, 0x08, /* GReportSize 0x08 [8] */ -- 0x95, 0x01, /* GReportCount 0x01 [1] */ -- 0x81, 0x02, /* MInput 0x02 (Data[0] Var[1] Abs[2]) */ -- -- 0xC0, /* MEndCollection */ -- -- 0xC0 /* MEndCollection [Game Pad] */ --}; -- --static const unsigned int ps3remote_keymap_joypad_buttons[] = { -- [0x01] = KEY_SELECT, -- [0x02] = BTN_THUMBL, /* L3 */ -- [0x03] = BTN_THUMBR, /* R3 */ -- [0x04] = BTN_START, -- [0x05] = KEY_UP, -- [0x06] = KEY_RIGHT, -- [0x07] = KEY_DOWN, -- [0x08] = KEY_LEFT, -- [0x09] = BTN_TL2, /* L2 */ -- [0x0a] = BTN_TR2, /* R2 */ -- [0x0b] = BTN_TL, /* L1 */ -- [0x0c] = BTN_TR, /* R1 */ -- [0x0d] = KEY_OPTION, /* options/triangle */ -- [0x0e] = KEY_BACK, /* back/circle */ -- [0x0f] = BTN_0, /* cross */ -- [0x10] = KEY_SCREEN, /* view/square */ -- [0x11] = KEY_HOMEPAGE, /* PS button */ -- [0x14] = KEY_ENTER, --}; --static const unsigned int ps3remote_keymap_remote_buttons[] = { -- [0x00] = KEY_1, -- [0x01] = KEY_2, -- [0x02] = KEY_3, -- [0x03] = KEY_4, -- [0x04] = KEY_5, -- [0x05] = KEY_6, -- [0x06] = KEY_7, -- [0x07] = KEY_8, -- [0x08] = KEY_9, -- [0x09] = KEY_0, -- [0x0e] = KEY_ESC, /* return */ -- [0x0f] = KEY_CLEAR, -- [0x16] = KEY_EJECTCD, -- [0x1a] = KEY_MENU, /* top menu */ -- [0x28] = KEY_TIME, -- [0x30] = KEY_PREVIOUS, -- [0x31] = KEY_NEXT, -- [0x32] = KEY_PLAY, -- [0x33] = KEY_REWIND, /* scan back */ -- [0x34] = KEY_FORWARD, /* scan forward */ -- [0x38] = KEY_STOP, -- [0x39] = KEY_PAUSE, -- [0x40] = KEY_CONTEXT_MENU, /* pop up/menu */ -- [0x60] = KEY_FRAMEBACK, /* slow/step back */ -- [0x61] = KEY_FRAMEFORWARD, /* slow/step forward */ -- [0x63] = KEY_SUBTITLE, -- [0x64] = KEY_AUDIO, -- [0x65] = KEY_ANGLE, -- [0x70] = KEY_INFO, /* display */ -- [0x80] = KEY_BLUE, -- [0x81] = KEY_RED, -- [0x82] = KEY_GREEN, -- [0x83] = KEY_YELLOW, --}; -- --static __u8 *ps3remote_fixup(struct hid_device *hdev, __u8 *rdesc, -- unsigned int *rsize) --{ -- *rsize = sizeof(ps3remote_rdesc); -- return ps3remote_rdesc; --} -- --static int ps3remote_mapping(struct hid_device *hdev, struct hid_input *hi, -- struct hid_field *field, struct hid_usage *usage, -- unsigned long **bit, int *max) --{ -- unsigned int key = usage->hid & HID_USAGE; -- -- if ((usage->hid & HID_USAGE_PAGE) != HID_UP_BUTTON) -- return -1; -- -- switch (usage->collection_index) { -- case 1: -- if (key >= ARRAY_SIZE(ps3remote_keymap_joypad_buttons)) -- return -1; -- -- key = ps3remote_keymap_joypad_buttons[key]; -- if (!key) -- return -1; -- break; -- case 2: -- if (key >= ARRAY_SIZE(ps3remote_keymap_remote_buttons)) -- return -1; -- -- key = ps3remote_keymap_remote_buttons[key]; -- if (!key) -- return -1; -- break; -- default: -- return -1; -- } -- -- hid_map_usage_clear(hi, usage, bit, max, EV_KEY, key); -- return 1; --} -- --static const struct hid_device_id ps3remote_devices[] = { -- /* PS3 BD Remote Control */ -- { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_PS3_BDREMOTE) }, -- /* Logitech Harmony Adapter for PS3 */ -- { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_PS3) }, -- { } --}; --MODULE_DEVICE_TABLE(hid, ps3remote_devices); -- --static struct hid_driver ps3remote_driver = { -- .name = "ps3_remote", -- .id_table = ps3remote_devices, -- .report_fixup = ps3remote_fixup, -- .input_mapping = ps3remote_mapping, --}; --module_hid_driver(ps3remote_driver); -- --MODULE_LICENSE("GPL"); --MODULE_AUTHOR("David Dillow , Antonio Ospite "); -diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c -index 312098e..83f9629 100644 ---- a/drivers/hid/hid-sony.c -+++ b/drivers/hid/hid-sony.c -@@ -1,11 +1,13 @@ - /* -- * HID driver for some sony "special" devices -+ * HID driver for Sony / PS2 / PS3 BD devices. - * - * Copyright (c) 1999 Andreas Gal - * Copyright (c) 2000-2005 Vojtech Pavlik - * Copyright (c) 2005 Michael Haboustak for Concept2, Inc - * Copyright (c) 2008 Jiri Slaby -- * Copyright (c) 2006-2008 Jiri Kosina -+ * Copyright (c) 2012 David Dillow -+ * Copyright (c) 2006-2013 Jiri Kosina -+ * Copyright (c) 2013 Colin Leitner - */ - - /* -@@ -15,17 +17,28 @@ - * any later version. - */ - -+/* NOTE: in order for the Sony PS3 BD Remote Control to be found by -+ * a Bluetooth host, the key combination Start+Enter has to be kept pressed -+ * for about 7 seconds with the Bluetooth Host Controller in discovering mode. -+ * -+ * There will be no PIN request from the device. -+ */ -+ - #include - #include - #include - #include - #include -+#include "usbhid/usbhid.h" -+#include - - #include "hid-ids.h" - - #define VAIO_RDESC_CONSTANT (1 << 0) - #define SIXAXIS_CONTROLLER_USB (1 << 1) - #define SIXAXIS_CONTROLLER_BT (1 << 2) -+#define BUZZ_CONTROLLER (1 << 3) -+#define PS3REMOTE (1 << 4) - - static const u8 sixaxis_rdesc_fixup[] = { - 0x95, 0x13, 0x09, 0x01, 0x81, 0x02, 0x95, 0x0C, -@@ -55,10 +68,214 @@ static const u8 sixaxis_rdesc_fixup2[] = { - 0xb1, 0x02, 0xc0, 0xc0, - }; - -+static __u8 ps3remote_rdesc[] = { -+ 0x05, 0x01, /* GUsagePage Generic Desktop */ -+ 0x09, 0x05, /* LUsage 0x05 [Game Pad] */ -+ 0xA1, 0x01, /* MCollection Application (mouse, keyboard) */ -+ -+ /* Use collection 1 for joypad buttons */ -+ 0xA1, 0x02, /* MCollection Logical (interrelated data) */ -+ -+ /* Ignore the 1st byte, maybe it is used for a controller -+ * number but it's not needed for correct operation */ -+ 0x75, 0x08, /* GReportSize 0x08 [8] */ -+ 0x95, 0x01, /* GReportCount 0x01 [1] */ -+ 0x81, 0x01, /* MInput 0x01 (Const[0] Arr[1] Abs[2]) */ -+ -+ /* Bytes from 2nd to 4th are a bitmap for joypad buttons, for these -+ * buttons multiple keypresses are allowed */ -+ 0x05, 0x09, /* GUsagePage Button */ -+ 0x19, 0x01, /* LUsageMinimum 0x01 [Button 1 (primary/trigger)] */ -+ 0x29, 0x18, /* LUsageMaximum 0x18 [Button 24] */ -+ 0x14, /* GLogicalMinimum [0] */ -+ 0x25, 0x01, /* GLogicalMaximum 0x01 [1] */ -+ 0x75, 0x01, /* GReportSize 0x01 [1] */ -+ 0x95, 0x18, /* GReportCount 0x18 [24] */ -+ 0x81, 0x02, /* MInput 0x02 (Data[0] Var[1] Abs[2]) */ -+ -+ 0xC0, /* MEndCollection */ -+ -+ /* Use collection 2 for remote control buttons */ -+ 0xA1, 0x02, /* MCollection Logical (interrelated data) */ -+ -+ /* 5th byte is used for remote control buttons */ -+ 0x05, 0x09, /* GUsagePage Button */ -+ 0x18, /* LUsageMinimum [No button pressed] */ -+ 0x29, 0xFE, /* LUsageMaximum 0xFE [Button 254] */ -+ 0x14, /* GLogicalMinimum [0] */ -+ 0x26, 0xFE, 0x00, /* GLogicalMaximum 0x00FE [254] */ -+ 0x75, 0x08, /* GReportSize 0x08 [8] */ -+ 0x95, 0x01, /* GReportCount 0x01 [1] */ -+ 0x80, /* MInput */ -+ -+ /* Ignore bytes from 6th to 11th, 6th to 10th are always constant at -+ * 0xff and 11th is for press indication */ -+ 0x75, 0x08, /* GReportSize 0x08 [8] */ -+ 0x95, 0x06, /* GReportCount 0x06 [6] */ -+ 0x81, 0x01, /* MInput 0x01 (Const[0] Arr[1] Abs[2]) */ -+ -+ /* 12th byte is for battery strength */ -+ 0x05, 0x06, /* GUsagePage Generic Device Controls */ -+ 0x09, 0x20, /* LUsage 0x20 [Battery Strength] */ -+ 0x14, /* GLogicalMinimum [0] */ -+ 0x25, 0x05, /* GLogicalMaximum 0x05 [5] */ -+ 0x75, 0x08, /* GReportSize 0x08 [8] */ -+ 0x95, 0x01, /* GReportCount 0x01 [1] */ -+ 0x81, 0x02, /* MInput 0x02 (Data[0] Var[1] Abs[2]) */ -+ -+ 0xC0, /* MEndCollection */ -+ -+ 0xC0 /* MEndCollection [Game Pad] */ -+}; -+ -+static const unsigned int ps3remote_keymap_joypad_buttons[] = { -+ [0x01] = KEY_SELECT, -+ [0x02] = BTN_THUMBL, /* L3 */ -+ [0x03] = BTN_THUMBR, /* R3 */ -+ [0x04] = BTN_START, -+ [0x05] = KEY_UP, -+ [0x06] = KEY_RIGHT, -+ [0x07] = KEY_DOWN, -+ [0x08] = KEY_LEFT, -+ [0x09] = BTN_TL2, /* L2 */ -+ [0x0a] = BTN_TR2, /* R2 */ -+ [0x0b] = BTN_TL, /* L1 */ -+ [0x0c] = BTN_TR, /* R1 */ -+ [0x0d] = KEY_OPTION, /* options/triangle */ -+ [0x0e] = KEY_BACK, /* back/circle */ -+ [0x0f] = BTN_0, /* cross */ -+ [0x10] = KEY_SCREEN, /* view/square */ -+ [0x11] = KEY_HOMEPAGE, /* PS button */ -+ [0x14] = KEY_ENTER, -+}; -+static const unsigned int ps3remote_keymap_remote_buttons[] = { -+ [0x00] = KEY_1, -+ [0x01] = KEY_2, -+ [0x02] = KEY_3, -+ [0x03] = KEY_4, -+ [0x04] = KEY_5, -+ [0x05] = KEY_6, -+ [0x06] = KEY_7, -+ [0x07] = KEY_8, -+ [0x08] = KEY_9, -+ [0x09] = KEY_0, -+ [0x0e] = KEY_ESC, /* return */ -+ [0x0f] = KEY_CLEAR, -+ [0x16] = KEY_EJECTCD, -+ [0x1a] = KEY_MENU, /* top menu */ -+ [0x28] = KEY_TIME, -+ [0x30] = KEY_PREVIOUS, -+ [0x31] = KEY_NEXT, -+ [0x32] = KEY_PLAY, -+ [0x33] = KEY_REWIND, /* scan back */ -+ [0x34] = KEY_FORWARD, /* scan forward */ -+ [0x38] = KEY_STOP, -+ [0x39] = KEY_PAUSE, -+ [0x40] = KEY_CONTEXT_MENU, /* pop up/menu */ -+ [0x60] = KEY_FRAMEBACK, /* slow/step back */ -+ [0x61] = KEY_FRAMEFORWARD, /* slow/step forward */ -+ [0x63] = KEY_SUBTITLE, -+ [0x64] = KEY_AUDIO, -+ [0x65] = KEY_ANGLE, -+ [0x70] = KEY_INFO, /* display */ -+ [0x80] = KEY_BLUE, -+ [0x81] = KEY_RED, -+ [0x82] = KEY_GREEN, -+ [0x83] = KEY_YELLOW, -+}; -+ -+static const unsigned int buzz_keymap[] = { -+ /* The controller has 4 remote buzzers, each with one LED and 5 -+ * buttons. -+ * -+ * We use the mapping chosen by the controller, which is: -+ * -+ * Key Offset -+ * ------------------- -+ * Buzz 1 -+ * Blue 5 -+ * Orange 4 -+ * Green 3 -+ * Yellow 2 -+ * -+ * So, for example, the orange button on the third buzzer is mapped to -+ * BTN_TRIGGER_HAPPY14 -+ */ -+ [ 1] = BTN_TRIGGER_HAPPY1, -+ [ 2] = BTN_TRIGGER_HAPPY2, -+ [ 3] = BTN_TRIGGER_HAPPY3, -+ [ 4] = BTN_TRIGGER_HAPPY4, -+ [ 5] = BTN_TRIGGER_HAPPY5, -+ [ 6] = BTN_TRIGGER_HAPPY6, -+ [ 7] = BTN_TRIGGER_HAPPY7, -+ [ 8] = BTN_TRIGGER_HAPPY8, -+ [ 9] = BTN_TRIGGER_HAPPY9, -+ [10] = BTN_TRIGGER_HAPPY10, -+ [11] = BTN_TRIGGER_HAPPY11, -+ [12] = BTN_TRIGGER_HAPPY12, -+ [13] = BTN_TRIGGER_HAPPY13, -+ [14] = BTN_TRIGGER_HAPPY14, -+ [15] = BTN_TRIGGER_HAPPY15, -+ [16] = BTN_TRIGGER_HAPPY16, -+ [17] = BTN_TRIGGER_HAPPY17, -+ [18] = BTN_TRIGGER_HAPPY18, -+ [19] = BTN_TRIGGER_HAPPY19, -+ [20] = BTN_TRIGGER_HAPPY20, -+}; -+ - struct sony_sc { - unsigned long quirks; -+ -+ void *extra; - }; - -+struct buzz_extra { -+ int led_state; -+ struct led_classdev *leds[4]; -+}; -+ -+static __u8 *ps3remote_fixup(struct hid_device *hdev, __u8 *rdesc, -+ unsigned int *rsize) -+{ -+ *rsize = sizeof(ps3remote_rdesc); -+ return ps3remote_rdesc; -+} -+ -+static int ps3remote_mapping(struct hid_device *hdev, struct hid_input *hi, -+ struct hid_field *field, struct hid_usage *usage, -+ unsigned long **bit, int *max) -+{ -+ unsigned int key = usage->hid & HID_USAGE; -+ -+ if ((usage->hid & HID_USAGE_PAGE) != HID_UP_BUTTON) -+ return -1; -+ -+ switch (usage->collection_index) { -+ case 1: -+ if (key >= ARRAY_SIZE(ps3remote_keymap_joypad_buttons)) -+ return -1; -+ -+ key = ps3remote_keymap_joypad_buttons[key]; -+ if (!key) -+ return -1; -+ break; -+ case 2: -+ if (key >= ARRAY_SIZE(ps3remote_keymap_remote_buttons)) -+ return -1; -+ -+ key = ps3remote_keymap_remote_buttons[key]; -+ if (!key) -+ return -1; -+ break; -+ default: -+ return -1; -+ } -+ -+ hid_map_usage_clear(hi, usage, bit, max, EV_KEY, key); -+ return 1; -+} -+ -+ - /* Sony Vaio VGX has wrongly mouse pointer declared as constant */ - static __u8 *sony_report_fixup(struct hid_device *hdev, __u8 *rdesc, - unsigned int *rsize) -@@ -95,6 +312,10 @@ static __u8 *sony_report_fixup(struct hid_device *hdev, __u8 *rdesc, - *rsize = sizeof(sixaxis_rdesc_fixup2); - memcpy(rdesc, &sixaxis_rdesc_fixup2, *rsize); - } -+ -+ if (sc->quirks & PS3REMOTE) -+ return ps3remote_fixup(hdev, rdesc, rsize); -+ - return rdesc; - } - -@@ -117,6 +338,41 @@ static int sony_raw_event(struct hid_device *hdev, struct hid_report *report, - return 0; - } - -+static int sony_mapping(struct hid_device *hdev, struct hid_input *hi, -+ struct hid_field *field, struct hid_usage *usage, -+ unsigned long **bit, int *max) -+{ -+ struct sony_sc *sc = hid_get_drvdata(hdev); -+ -+ if (sc->quirks & BUZZ_CONTROLLER) { -+ unsigned int key = usage->hid & HID_USAGE; -+ -+ if ((usage->hid & HID_USAGE_PAGE) != HID_UP_BUTTON) -+ return -1; -+ -+ switch (usage->collection_index) { -+ case 1: -+ if (key >= ARRAY_SIZE(buzz_keymap)) -+ return -1; -+ -+ key = buzz_keymap[key]; -+ if (!key) -+ return -1; -+ break; -+ default: -+ return -1; -+ } -+ -+ hid_map_usage_clear(hi, usage, bit, max, EV_KEY, key); -+ return 1; -+ } -+ -+ if (sc->quirks & PS3REMOTE) -+ return ps3remote_mapping(hdev, hi, field, usage, bit, max); -+ -+ return -1; -+} -+ - /* - * The Sony Sixaxis does not handle HID Output Reports on the Interrupt EP - * like it should according to usbhid/hid-core.c::usbhid_output_raw_report() -@@ -192,11 +448,181 @@ static int sixaxis_set_operational_bt(struct hid_device *hdev) - return hdev->hid_output_raw_report(hdev, buf, sizeof(buf), HID_FEATURE_REPORT); - } - -+static void buzz_set_leds(struct hid_device *hdev, int leds) -+{ -+ struct list_head *report_list = -+ &hdev->report_enum[HID_OUTPUT_REPORT].report_list; -+ struct hid_report *report = list_entry(report_list->next, -+ struct hid_report, list); -+ __s32 *value = report->field[0]->value; -+ -+ value[0] = 0x00; -+ value[1] = (leds & 1) ? 0xff : 0x00; -+ value[2] = (leds & 2) ? 0xff : 0x00; -+ value[3] = (leds & 4) ? 0xff : 0x00; -+ value[4] = (leds & 8) ? 0xff : 0x00; -+ value[5] = 0x00; -+ value[6] = 0x00; -+ hid_hw_request(hdev, report, HID_REQ_SET_REPORT); -+} -+ -+static void buzz_led_set_brightness(struct led_classdev *led, -+ enum led_brightness value) -+{ -+ struct device *dev = led->dev->parent; -+ struct hid_device *hdev = container_of(dev, struct hid_device, dev); -+ struct sony_sc *drv_data; -+ struct buzz_extra *buzz; -+ -+ int n; -+ -+ drv_data = hid_get_drvdata(hdev); -+ if (!drv_data || !drv_data->extra) { -+ hid_err(hdev, "No device data\n"); -+ return; -+ } -+ buzz = drv_data->extra; -+ -+ for (n = 0; n < 4; n++) { -+ if (led == buzz->leds[n]) { -+ int on = !! (buzz->led_state & (1 << n)); -+ if (value == LED_OFF && on) { -+ buzz->led_state &= ~(1 << n); -+ buzz_set_leds(hdev, buzz->led_state); -+ } else if (value != LED_OFF && !on) { -+ buzz->led_state |= (1 << n); -+ buzz_set_leds(hdev, buzz->led_state); -+ } -+ break; -+ } -+ } -+} -+ -+static enum led_brightness buzz_led_get_brightness(struct led_classdev *led) -+{ -+ struct device *dev = led->dev->parent; -+ struct hid_device *hdev = container_of(dev, struct hid_device, dev); -+ struct sony_sc *drv_data; -+ struct buzz_extra *buzz; -+ -+ int n; -+ int on = 0; -+ -+ drv_data = hid_get_drvdata(hdev); -+ if (!drv_data || !drv_data->extra) { -+ hid_err(hdev, "No device data\n"); -+ return LED_OFF; -+ } -+ buzz = drv_data->extra; -+ -+ for (n = 0; n < 4; n++) { -+ if (led == buzz->leds[n]) { -+ on = !! (buzz->led_state & (1 << n)); -+ break; -+ } -+ } -+ -+ return on ? LED_FULL : LED_OFF; -+} -+ -+static int buzz_init(struct hid_device *hdev) -+{ -+ struct sony_sc *drv_data; -+ struct buzz_extra *buzz; -+ int n, ret = 0; -+ struct led_classdev *led; -+ size_t name_sz; -+ char *name; -+ -+ drv_data = hid_get_drvdata(hdev); -+ BUG_ON(!(drv_data->quirks & BUZZ_CONTROLLER)); -+ -+ buzz = kzalloc(sizeof(*buzz), GFP_KERNEL); -+ if (!buzz) { -+ hid_err(hdev, "Insufficient memory, cannot allocate driver data\n"); -+ return -ENOMEM; -+ } -+ drv_data->extra = buzz; -+ -+ /* Clear LEDs as we have no way of reading their initial state. This is -+ * only relevant if the driver is loaded after somebody actively set the -+ * LEDs to on */ -+ buzz_set_leds(hdev, 0x00); -+ -+ name_sz = strlen(dev_name(&hdev->dev)) + strlen("::buzz#") + 1; -+ -+ for (n = 0; n < 4; n++) { -+ led = kzalloc(sizeof(struct led_classdev) + name_sz, GFP_KERNEL); -+ if (!led) { -+ hid_err(hdev, "Couldn't allocate memory for LED %d\n", n); -+ goto error_leds; -+ } -+ -+ name = (void *)(&led[1]); -+ snprintf(name, name_sz, "%s::buzz%d", dev_name(&hdev->dev), n + 1); -+ led->name = name; -+ led->brightness = 0; -+ led->max_brightness = 1; -+ led->brightness_get = buzz_led_get_brightness; -+ led->brightness_set = buzz_led_set_brightness; -+ -+ if (led_classdev_register(&hdev->dev, led)) { -+ hid_err(hdev, "Failed to register LED %d\n", n); -+ kfree(led); -+ goto error_leds; -+ } -+ -+ buzz->leds[n] = led; -+ } -+ -+ return ret; -+ -+error_leds: -+ for (n = 0; n < 4; n++) { -+ led = buzz->leds[n]; -+ buzz->leds[n] = NULL; -+ if (!led) -+ continue; -+ led_classdev_unregister(led); -+ kfree(led); -+ } -+ -+ kfree(drv_data->extra); -+ drv_data->extra = NULL; -+ return ret; -+} -+ -+static void buzz_remove(struct hid_device *hdev) -+{ -+ struct sony_sc *drv_data; -+ struct buzz_extra *buzz; -+ struct led_classdev *led; -+ int n; -+ -+ drv_data = hid_get_drvdata(hdev); -+ BUG_ON(!(drv_data->quirks & BUZZ_CONTROLLER)); -+ -+ buzz = drv_data->extra; -+ -+ for (n = 0; n < 4; n++) { -+ led = buzz->leds[n]; -+ buzz->leds[n] = NULL; -+ if (!led) -+ continue; -+ led_classdev_unregister(led); -+ kfree(led); -+ } -+ -+ kfree(drv_data->extra); -+ drv_data->extra = NULL; -+} -+ - static int sony_probe(struct hid_device *hdev, const struct hid_device_id *id) - { - int ret; - unsigned long quirks = id->driver_data; - struct sony_sc *sc; -+ unsigned int connect_mask = HID_CONNECT_DEFAULT; - - sc = kzalloc(sizeof(*sc), GFP_KERNEL); - if (sc == NULL) { -@@ -213,8 +639,14 @@ static int sony_probe(struct hid_device *hdev, const struct hid_device_id *id) - goto err_free; - } - -- ret = hid_hw_start(hdev, HID_CONNECT_DEFAULT | -- HID_CONNECT_HIDDEV_FORCE); -+ if (sc->quirks & VAIO_RDESC_CONSTANT) -+ connect_mask |= HID_CONNECT_HIDDEV_FORCE; -+ else if (sc->quirks & SIXAXIS_CONTROLLER_USB) -+ connect_mask |= HID_CONNECT_HIDDEV_FORCE; -+ else if (sc->quirks & SIXAXIS_CONTROLLER_BT) -+ connect_mask |= HID_CONNECT_HIDDEV_FORCE; -+ -+ ret = hid_hw_start(hdev, connect_mask); - if (ret) { - hid_err(hdev, "hw start failed\n"); - goto err_free; -@@ -226,6 +658,8 @@ static int sony_probe(struct hid_device *hdev, const struct hid_device_id *id) - } - else if (sc->quirks & SIXAXIS_CONTROLLER_BT) - ret = sixaxis_set_operational_bt(hdev); -+ else if (sc->quirks & BUZZ_CONTROLLER) -+ ret = buzz_init(hdev); - else - ret = 0; - -@@ -242,8 +676,13 @@ err_free: - - static void sony_remove(struct hid_device *hdev) - { -+ struct sony_sc *sc = hid_get_drvdata(hdev); -+ -+ if (sc->quirks & BUZZ_CONTROLLER) -+ buzz_remove(hdev); -+ - hid_hw_stop(hdev); -- kfree(hid_get_drvdata(hdev)); -+ kfree(sc); - } - - static const struct hid_device_id sony_devices[] = { -@@ -257,17 +696,30 @@ static const struct hid_device_id sony_devices[] = { - .driver_data = VAIO_RDESC_CONSTANT }, - { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_VAIO_VGP_MOUSE), - .driver_data = VAIO_RDESC_CONSTANT }, -+ /* Wired Buzz Controller. Reported as Sony Hub from its USB ID and as -+ * Logitech joystick from the device descriptor. */ -+ { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_BUZZ_CONTROLLER), -+ .driver_data = BUZZ_CONTROLLER }, -+ { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_WIRELESS_BUZZ_CONTROLLER), -+ .driver_data = BUZZ_CONTROLLER }, -+ /* PS3 BD Remote Control */ -+ { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_PS3_BDREMOTE), -+ .driver_data = PS3REMOTE }, -+ /* Logitech Harmony Adapter for PS3 */ -+ { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_PS3), -+ .driver_data = PS3REMOTE }, - { } - }; - MODULE_DEVICE_TABLE(hid, sony_devices); - - static struct hid_driver sony_driver = { -- .name = "sony", -- .id_table = sony_devices, -- .probe = sony_probe, -- .remove = sony_remove, -- .report_fixup = sony_report_fixup, -- .raw_event = sony_raw_event -+ .name = "sony", -+ .id_table = sony_devices, -+ .input_mapping = sony_mapping, -+ .probe = sony_probe, -+ .remove = sony_remove, -+ .report_fixup = sony_report_fixup, -+ .raw_event = sony_raw_event - }; - module_hid_driver(sony_driver); - diff --git a/packages/linux/patches/3.11.6/linux-058.05-hid_sony-add_autorepeat_for_PS3_remotes.patch b/packages/linux/patches/3.11.6/linux-058.05-hid_sony-add_autorepeat_for_PS3_remotes.patch deleted file mode 100644 index abdc74f673..0000000000 --- a/packages/linux/patches/3.11.6/linux-058.05-hid_sony-add_autorepeat_for_PS3_remotes.patch +++ /dev/null @@ -1,61 +0,0 @@ -Betreff: [RFC] hid/sony: add autorepeat for PS3 remotes -Von: David Dillow -Datum: 28.06.2013 04:28 -An: linux-input@vger.kernel.org -Kopie (CC): Stephan Raue - -Some applications using the PS3 remote would like to have autorepeat -from the device. Use the input subsystem's software emulation to provide -this capability, and enable those that don't need it to turn it off. ---- -I'm not sure this is the correct approach, or if it is even appropriate -for a remote to do autorepeat. However, the media/rc subsystem does do -it by default, and it's been requested by users, so there is at least -some demand. - -This compiled against the hid-sony driver with the PS3 remote changes -merged, but I have done no testing of it. If the approach seems -reasonable, I'll try to test it when the MythTV is idle. - - drivers/hid/hid-sony.c | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) -diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c -index ecbc749..0bbcd07 100644 ---- a/drivers/hid/hid-sony.c -+++ b/drivers/hid/hid-sony.c -@@ -274,6 +274,24 @@ static int ps3remote_mapping(struct hid_device *hdev, struct hid_input *hi, - return 1; - } - -+static int ps3remote_setup_repeat(struct hid_device *hdev) -+{ -+ struct hid_input *hidinput = list_first_entry(&hdev->inputs, -+ struct hid_input, list); -+ struct input_dev *input = hidinput->input; -+ -+ /* -+ * Set up autorepeat defaults per the remote control subsystem; -+ * this must be done after hid_hw_start(), as having these non-zero -+ * at the time of input_register_device() tells the input system that -+ * the hardware does the autorepeat, and the PS3 remote does not. -+ */ -+ set_bit(EV_REP, input->evbit); -+ input->rep[REP_DELAY] = 500; -+ input->rep[REP_PERIOD] = 125; -+ -+ return 0; -+} - - /* Sony Vaio VGX has wrongly mouse pointer declared as constant */ - static __u8 *sony_report_fixup(struct hid_device *hdev, __u8 *rdesc, -@@ -659,6 +677,8 @@ static int sony_probe(struct hid_device *hdev, const struct hid_device_id *id) - ret = sixaxis_set_operational_bt(hdev); - else if (sc->quirks & BUZZ_CONTROLLER) - ret = buzz_init(hdev); -+ else if (sc->quirks & PS3REMOTE) -+ ret = ps3remote_setup_repeat(hdev); - else - ret = 0; - - - diff --git a/packages/linux/patches/3.11.6/linux-058.06-hid_sony-add_SMK_link.patch b/packages/linux/patches/3.11.6/linux-058.06-hid_sony-add_SMK_link.patch deleted file mode 100644 index bc92ecf487..0000000000 --- a/packages/linux/patches/3.11.6/linux-058.06-hid_sony-add_SMK_link.patch +++ /dev/null @@ -1,47 +0,0 @@ -commit 5a601d61d36236a667cc7d170b300d18dd6240c6 -Author: Juan J. Sierralta -Date: Sun Jul 28 09:26:04 2013 +0300 - - Add support for SMK-Link PS3 remote - -diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c -index 396d24d..9eb7129 100644 ---- a/drivers/hid/hid-core.c -+++ b/drivers/hid/hid-core.c -@@ -1686,6 +1686,7 @@ static const struct hid_device_id hid_have_special_driver[] = { - { HID_USB_DEVICE(USB_VENDOR_ID_SAMSUNG, USB_DEVICE_ID_SAMSUNG_IR_REMOTE) }, - { HID_USB_DEVICE(USB_VENDOR_ID_SAMSUNG, USB_DEVICE_ID_SAMSUNG_WIRELESS_KBD_MOUSE) }, - { HID_USB_DEVICE(USB_VENDOR_ID_SKYCABLE, USB_DEVICE_ID_SKYCABLE_WIRELESS_PRESENTER) }, -+ { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SMK, USB_DEVICE_ID_SONY_PS3_BDREMOTE) }, - { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_BUZZ_CONTROLLER) }, - { HID_USB_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_WIRELESS_BUZZ_CONTROLLER) }, - { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SONY, USB_DEVICE_ID_SONY_PS3_BDREMOTE) }, -diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h -index dd0511e..2801df1 100644 ---- a/drivers/hid/hid-ids.h -+++ b/drivers/hid/hid-ids.h -@@ -734,6 +734,7 @@ - #define USB_VENDOR_ID_SKYCABLE 0x1223 - #define USB_DEVICE_ID_SKYCABLE_WIRELESS_PRESENTER 0x3F07 - -+#define USB_VENDOR_ID_SMK 0x0609 - #define USB_VENDOR_ID_SONY 0x054c - #define USB_DEVICE_ID_SONY_VAIO_VGX_MOUSE 0x024b - #define USB_DEVICE_ID_SONY_VAIO_VGP_MOUSE 0x0374 -diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c -index 8f425e2..614f057 100644 ---- a/drivers/hid/hid-sony.c -+++ b/drivers/hid/hid-sony.c -@@ -728,8 +728,12 @@ static const struct hid_device_id sony_devices[] = { - /* Logitech Harmony Adapter for PS3 */ - { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_HARMONY_PS3), - .driver_data = PS3REMOTE }, -+ /* SMK-Link Universal Remote Control VP3700 */ -+ { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_SMK, USB_DEVICE_ID_SONY_PS3_BDREMOTE), -+ .driver_data = PS3REMOTE }, - { } - }; -+ - MODULE_DEVICE_TABLE(hid, sony_devices); - - static struct hid_driver sony_driver = { diff --git a/packages/linux/patches/3.11.6/linux-059-remove_some_xpad_pids-0.2.patch b/packages/linux/patches/3.11.6/linux-059-remove_some_xpad_pids-0.2.patch deleted file mode 100644 index 4a6d1c7a08..0000000000 --- a/packages/linux/patches/3.11.6/linux-059-remove_some_xpad_pids-0.2.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Naur linux-3.8.4/drivers/input/joystick/xpad.c linux-3.8.4.patch/drivers/input/joystick/xpad.c ---- linux-3.8.4/drivers/input/joystick/xpad.c 2013-03-20 21:11:19.000000000 +0100 -+++ linux-3.8.4.patch/drivers/input/joystick/xpad.c 2013-03-26 20:24:29.273978355 +0100 -@@ -174,7 +174,6 @@ - { 0x1bad, 0xf901, "Gamestop Xbox 360 Controller", 0, XTYPE_XBOX360 }, - { 0x1bad, 0xf903, "Tron Xbox 360 controller", 0, XTYPE_XBOX360 }, - { 0x24c6, 0x5300, "PowerA MINI PROEX Controller", 0, XTYPE_XBOX360 }, -- { 0xffff, 0xffff, "Chinese-made Xbox Controller", 0, XTYPE_XBOX }, - { 0x0000, 0x0000, "Generic X-Box pad", 0, XTYPE_UNKNOWN } - }; - diff --git a/packages/linux/patches/3.11.6/linux-060-add_AUGUST_DVB-T205.patch b/packages/linux/patches/3.11.6/linux-060-add_AUGUST_DVB-T205.patch deleted file mode 100644 index 26de5761f0..0000000000 --- a/packages/linux/patches/3.11.6/linux-060-add_AUGUST_DVB-T205.patch +++ /dev/null @@ -1,13 +0,0 @@ -diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c -index c0cd084..c4b279f 100644 ---- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c -+++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c -@@ -1388,6 +1388,8 @@ static const struct usb_device_id rtl28xxu_id_table[] = { - &rtl2832u_props, "Leadtek WinFast DTV Dongle mini", NULL) }, - { DVB_USB_DEVICE(USB_VID_GTEK, USB_PID_CPYTO_REDI_PC50A, - &rtl2832u_props, "Crypto ReDi PC 50 A", NULL) }, -+ { DVB_USB_DEVICE(USB_VID_GTEK, 0xa803, -+ &rtl2832u_props, "Realtek RTL2832U reference design", NULL) }, - { } - }; - MODULE_DEVICE_TABLE(usb, rtl28xxu_id_table); diff --git a/packages/linux/patches/3.11.6/linux-203-stb0899_enable_low_symbol_rate.patch b/packages/linux/patches/3.11.6/linux-203-stb0899_enable_low_symbol_rate.patch deleted file mode 100644 index f302b6ce1b..0000000000 --- a/packages/linux/patches/3.11.6/linux-203-stb0899_enable_low_symbol_rate.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -Naur linux-3.7.2/drivers/media/dvb-frontends/stb0899_drv.c linux-3.7.2.patch/drivers/media/dvb-frontends/stb0899_drv.c ---- linux-3.7.2/drivers/media/dvb-frontends/stb0899_drv.c 2013-01-11 18:19:28.000000000 +0100 -+++ linux-3.7.2.patch/drivers/media/dvb-frontends/stb0899_drv.c 2013-01-16 10:25:43.479645317 +0100 -@@ -1581,7 +1581,7 @@ - .frequency_max = 2150000, - .frequency_stepsize = 0, - .frequency_tolerance = 0, -- .symbol_rate_min = 5000000, -+ .symbol_rate_min = 1000000, - .symbol_rate_max = 45000000, - - .caps = FE_CAN_INVERSION_AUTO | diff --git a/packages/linux/patches/3.11.6/linux-210-dvbsky.patch b/packages/linux/patches/3.11.6/linux-210-dvbsky.patch deleted file mode 100644 index 97683e9275..0000000000 --- a/packages/linux/patches/3.11.6/linux-210-dvbsky.patch +++ /dev/null @@ -1,6161 +0,0 @@ -diff -urN a/drivers/media/dvb-frontends/Kconfig b/drivers/media/dvb-frontends/Kconfig ---- a/drivers/media/dvb-frontends/Kconfig 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/dvb-frontends/Kconfig 2013-05-03 17:03:57.000000000 +0800 -@@ -200,6 +200,20 @@ - help - A DVB-S/S2 tuner module. Say Y when you want to support this frontend. - -+config DVB_M88DS3103 -+ tristate "Montage M88DS3103 based" -+ depends on DVB_CORE && I2C -+ default m if !MEDIA_SUBDRV_AUTOSELECT -+ help -+ A DVB-S/S2 tuner module. Say Y when you want to support this frontend. -+ -+config DVB_M88DC2800 -+ tristate "Montage M88DC2800 based" -+ depends on DVB_CORE && I2C -+ default m if !MEDIA_SUBDRV_AUTOSELECT -+ help -+ A DVB-C tuner module. Say Y when you want to support this frontend. -+ - config DVB_SI21XX - tristate "Silicon Labs SI21XX based" - depends on DVB_CORE && I2C -diff -urN a/drivers/media/dvb-frontends/m88dc2800.c b/drivers/media/dvb-frontends/m88dc2800.c ---- a/drivers/media/dvb-frontends/m88dc2800.c 1970-01-01 08:00:00.000000000 +0800 -+++ b/drivers/media/dvb-frontends/m88dc2800.c 2013-01-26 16:03:21.000000000 +0800 -@@ -0,0 +1,2124 @@ -+/* -+ M88DC2800/M88TC2800 - DVB-C demodulator and tuner from Montage -+ -+ Copyright (C) 2012 Max nibble -+ Copyright (C) 2011 Montage Technology / www.montage-tech.com -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 2 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+*/ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "dvb_frontend.h" -+#include "m88dc2800.h" -+ -+struct m88dc2800_state { -+ struct i2c_adapter *i2c; -+ const struct m88dc2800_config *config; -+ struct dvb_frontend frontend; -+ u32 freq; -+ u32 ber; -+ u32 sym; -+ u16 qam; -+ u8 inverted; -+ u32 xtal; -+ /* tuner state */ -+ u8 tuner_init_OK; /* Tuner initialize status */ -+ u8 tuner_dev_addr; /* Tuner device address */ -+ u32 tuner_freq; /* RF frequency to be set, unit: KHz */ -+ u16 tuner_qam; /* Reserved */ -+ u16 tuner_mode; -+ u8 tuner_bandwidth; /* Bandwidth of the channel, unit: MHz, 6/7/8 */ -+ u8 tuner_loopthrough; /* Tuner loop through switch, 0/1 */ -+ u32 tuner_crystal; /* Tuner crystal frequency, unit: KHz */ -+ u32 tuner_dac; /* Tuner DAC frequency, unit: KHz */ -+ u16 tuner_mtt; /* Tuner chip version, D1: 0x0d, E0: 0x0e, E1: 0x8e */ -+ u16 tuner_custom_cfg; -+ u32 tuner_version; /* Tuner driver version number */ -+ u32 tuner_time; -+}; -+ -+static int debug; -+module_param(debug, int, 0644); -+MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); -+ -+#define dprintk(args...) \ -+ do { \ -+ if (debug) \ -+ printk(KERN_INFO "m88dc2800: " args); \ -+ } while (0) -+ -+ -+static int m88dc2800_i2c_write(struct m88dc2800_state *state, u8 addr, -+ u8 * p_data, u8 len) -+{ -+ struct i2c_msg msg = { .flags = 0 }; -+ -+ msg.addr = addr; -+ msg.buf = p_data; -+ msg.len = len; -+ -+ return i2c_transfer(state->i2c, &msg, 1); -+} -+ -+static int m88dc2800_i2c_read(struct m88dc2800_state *state, u8 addr, -+ u8 * p_data, u8 len) -+{ -+ struct i2c_msg msg = { .flags = I2C_M_RD }; -+ -+ msg.addr = addr; -+ msg.buf = p_data; -+ msg.len = len; -+ -+ return i2c_transfer(state->i2c, &msg, 1); -+} -+ -+/*demod register operations.*/ -+static int WriteReg(struct m88dc2800_state *state, u8 reg, u8 data) -+{ -+ u8 buf[] = { reg, data }; -+ u8 addr = state->config->demod_address; -+ int err; -+ -+ dprintk("%s: write reg 0x%02x, value 0x%02x\n", __func__, reg, data); -+ -+ err = m88dc2800_i2c_write(state, addr, buf, 2); -+ -+ if (err != 1) { -+ printk(KERN_ERR -+ "%s: writereg error(err == %i, reg == 0x%02x," -+ " value == 0x%02x)\n", __func__, err, reg, data); -+ return -EIO; -+ } -+ return 0; -+} -+ -+static int ReadReg(struct m88dc2800_state *state, u8 reg) -+{ -+ int ret; -+ u8 b0[] = { reg }; -+ u8 b1[] = { 0 }; -+ u8 addr = state->config->demod_address; -+ -+ ret = m88dc2800_i2c_write(state, addr, b0, 1); -+ -+ if (ret != 1) { -+ printk(KERN_ERR "%s: reg=0x%x (error=%d)\n", -+ __func__, reg, ret); -+ return -EIO; -+ } -+ -+ ret = m88dc2800_i2c_read(state, addr, b1, 1); -+ -+ dprintk("%s: read reg 0x%02x, value 0x%02x\n", __func__, reg, b1[0]); -+ return b1[0]; -+} -+ -+static int _mt_fe_tn_set_reg(struct m88dc2800_state *state, u8 reg, -+ u8 data) -+{ -+ int ret; -+ u8 buf[2]; -+ u8 addr = state->tuner_dev_addr; -+ -+ buf[1] = ReadReg(state, 0x86); -+ buf[1] |= 0x80; -+ ret = WriteReg(state, 0x86, buf[1]); -+ -+ buf[0] = reg; -+ buf[1] = data; -+ -+ ret = m88dc2800_i2c_write(state, addr, buf, 2); -+ if (ret != 1) -+ return -EIO; -+ return 0; -+} -+ -+static int _mt_fe_tn_get_reg(struct m88dc2800_state *state, u8 reg, -+ u8 * p_data) -+{ -+ int ret; -+ u8 buf[2]; -+ u8 addr = state->tuner_dev_addr; -+ -+ buf[1] = ReadReg(state, 0x86); -+ buf[1] |= 0x80; -+ ret = WriteReg(state, 0x86, buf[1]); -+ -+ buf[0] = reg; -+ ret = m88dc2800_i2c_write(state, addr, buf, 1); -+ -+ msleep(1); -+ -+ buf[1] = ReadReg(state, 0x86); -+ buf[1] |= 0x80; -+ ret = WriteReg(state, 0x86, buf[1]); -+ -+ return m88dc2800_i2c_read(state, addr, p_data, 1); -+} -+ -+/* Tuner operation functions.*/ -+static int _mt_fe_tn_set_RF_front_tc2800(struct m88dc2800_state *state) -+{ -+ u32 freq_KHz = state->tuner_freq; -+ u8 a, b, c; -+ if (state->tuner_mtt == 0xD1) { /* D1 */ -+ if (freq_KHz <= 123000) { -+ if (freq_KHz <= 56000) { -+ a = 0x00; b = 0x00; c = 0x00; -+ } else if (freq_KHz <= 64000) { -+ a = 0x10; b = 0x01; c = 0x08; -+ } else if (freq_KHz <= 72000) { -+ a = 0x20; b = 0x02; c = 0x10; -+ } else if (freq_KHz <= 80000) { -+ a = 0x30; b = 0x03; c = 0x18; -+ } else if (freq_KHz <= 88000) { -+ a = 0x40; b = 0x04; c = 0x20; -+ } else if (freq_KHz <= 96000) { -+ a = 0x50; b = 0x05; c = 0x28; -+ } else if (freq_KHz <= 104000) { -+ a = 0x60; b = 0x06; c = 0x30; -+ } else { -+ a = 0x70; b = 0x07; c = 0x38; -+ } -+ _mt_fe_tn_set_reg(state, 0x58, 0x9b); -+ _mt_fe_tn_set_reg(state, 0x59, a); -+ _mt_fe_tn_set_reg(state, 0x5d, b); -+ _mt_fe_tn_set_reg(state, 0x5e, c); -+ _mt_fe_tn_set_reg(state, 0x5a, 0x75); -+ _mt_fe_tn_set_reg(state, 0x73, 0x0c); -+ } else { /* if (freq_KHz > 112000) */ -+ _mt_fe_tn_set_reg(state, 0x58, 0x7b); -+ if (freq_KHz <= 304000) { -+ if (freq_KHz <= 136000) { -+ _mt_fe_tn_set_reg(state, 0x5e, 0x40); -+ } else if (freq_KHz <= 160000) { -+ _mt_fe_tn_set_reg(state, 0x5e, 0x48); -+ } else if (freq_KHz <= 184000) { -+ _mt_fe_tn_set_reg(state, 0x5e, 0x50); -+ } else if (freq_KHz <= 208000) { -+ _mt_fe_tn_set_reg(state, 0x5e, 0x58); -+ } else if (freq_KHz <= 232000) { -+ _mt_fe_tn_set_reg(state, 0x5e, 0x60); -+ } else if (freq_KHz <= 256000) { -+ _mt_fe_tn_set_reg(state, 0x5e, 0x68); -+ } else if (freq_KHz <= 280000) { -+ _mt_fe_tn_set_reg(state, 0x5e, 0x70); -+ } else { /* if (freq_KHz <= 304000) */ -+ _mt_fe_tn_set_reg(state, 0x5e, 0x78); -+ } -+ if (freq_KHz <= 171000) { -+ _mt_fe_tn_set_reg(state, 0x73, 0x08); -+ } else if (freq_KHz <= 211000) { -+ _mt_fe_tn_set_reg(state, 0x73, 0x0a); -+ } else { -+ _mt_fe_tn_set_reg(state, 0x73, 0x0e); -+ } -+ } else { /* if (freq_KHz > 304000) */ -+ _mt_fe_tn_set_reg(state, 0x5e, 0x88); -+ if (freq_KHz <= 400000) { -+ _mt_fe_tn_set_reg(state, 0x73, 0x0c); -+ } else if (freq_KHz <= 450000) { -+ _mt_fe_tn_set_reg(state, 0x73, 0x09); -+ } else if (freq_KHz <= 550000) { -+ _mt_fe_tn_set_reg(state, 0x73, 0x0e); -+ } else if (freq_KHz <= 650000) { -+ _mt_fe_tn_set_reg(state, 0x73, 0x0d); -+ } else { /*if (freq_KHz > 650000) */ -+ _mt_fe_tn_set_reg(state, 0x73, 0x0e); -+ } -+ } -+ } -+ if (freq_KHz > 800000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x24); -+ else if (freq_KHz > 700000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x34); -+ else if (freq_KHz > 500000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x44); -+ else if (freq_KHz > 300000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x43); -+ else if (freq_KHz > 220000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x54); -+ else if (freq_KHz > 110000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x14); -+ else -+ _mt_fe_tn_set_reg(state, 0x87, 0x54); -+ if (freq_KHz > 600000) -+ _mt_fe_tn_set_reg(state, 0x6a, 0x53); -+ else if (freq_KHz > 500000) -+ _mt_fe_tn_set_reg(state, 0x6a, 0x57); -+ else -+ _mt_fe_tn_set_reg(state, 0x6a, 0x59); -+ if (freq_KHz < 200000) { -+ _mt_fe_tn_set_reg(state, 0x20, 0x5d); -+ } else if (freq_KHz < 500000) { -+ _mt_fe_tn_set_reg(state, 0x20, 0x7d); -+ } else { -+ _mt_fe_tn_set_reg(state, 0x20, 0xfd); -+ } /* end of 0xD1 */ -+ } else if (state->tuner_mtt == 0xE1) { /* E1 */ -+ if (freq_KHz <= 112000) { /* 123MHz */ -+ if (freq_KHz <= 56000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x01); -+ } else if (freq_KHz <= 64000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x09); -+ } else if (freq_KHz <= 72000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x11); -+ } else if (freq_KHz <= 80000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x19); -+ } else if (freq_KHz <= 88000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x21); -+ } else if (freq_KHz <= 96000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x29); -+ } else if (freq_KHz <= 104000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x31); -+ } else { /* if (freq_KHz <= 112000) */ -+ _mt_fe_tn_set_reg(state, 0x5c, 0x39); -+ } -+ _mt_fe_tn_set_reg(state, 0x5b, 0x30); -+ } else { /* if (freq_KHz > 112000) */ -+ if (freq_KHz <= 304000) { -+ if (freq_KHz <= 136000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x41); -+ } else if (freq_KHz <= 160000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x49); -+ } else if (freq_KHz <= 184000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x51); -+ } else if (freq_KHz <= 208000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x59); -+ } else if (freq_KHz <= 232000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x61); -+ } else if (freq_KHz <= 256000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x69); -+ } else if (freq_KHz <= 280000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x71); -+ } else { /* if (freq_KHz <= 304000) */ -+ _mt_fe_tn_set_reg(state, 0x5c, 0x79); -+ } -+ if (freq_KHz <= 150000) { -+ _mt_fe_tn_set_reg(state, 0x5b, 0x28); -+ } else if (freq_KHz <= 256000) { -+ _mt_fe_tn_set_reg(state, 0x5b, 0x29); -+ } else { -+ _mt_fe_tn_set_reg(state, 0x5b, 0x2a); -+ } -+ } else { /* if (freq_KHz > 304000) */ -+ if (freq_KHz <= 400000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x89); -+ } else if (freq_KHz <= 450000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x91); -+ } else if (freq_KHz <= 650000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0x98); -+ } else if (freq_KHz <= 850000) { -+ _mt_fe_tn_set_reg(state, 0x5c, 0xa0); -+ } else { -+ _mt_fe_tn_set_reg(state, 0x5c, 0xa8); -+ } -+ _mt_fe_tn_set_reg(state, 0x5b, 0x08); -+ } -+ } -+ } /* end of 0xE1 */ -+ return 0; -+} -+ -+static int _mt_fe_tn_cali_PLL_tc2800(struct m88dc2800_state *state, -+ u32 freq_KHz, -+ u32 cali_freq_thres_div2, -+ u32 cali_freq_thres_div3r, -+ u32 cali_freq_thres_div3) -+{ -+ s32 N, F, MUL; -+ u8 buf, tmp, tmp2; -+ s32 M; -+ const s32 crystal_KHz = state->tuner_crystal; -+ if (state->tuner_mtt == 0xD1) { -+ M = state->tuner_crystal / 4000; -+ if (freq_KHz > cali_freq_thres_div2) { -+ MUL = 4; -+ tmp = 2; -+ } else if (freq_KHz > 300000) { -+ MUL = 8; -+ tmp = 3; -+ } else if (freq_KHz > (cali_freq_thres_div2 / 2)) { -+ MUL = 8; -+ tmp = 4; -+ } else if (freq_KHz > (cali_freq_thres_div2 / 4)) { -+ MUL = 16; -+ tmp = 5; -+ } else if (freq_KHz > (cali_freq_thres_div2 / 8)) { -+ MUL = 32; -+ tmp = 6; -+ } else if (freq_KHz > (cali_freq_thres_div2 / 16)) { -+ MUL = 64; -+ tmp = 7; -+ } else { /* invalid */ -+ MUL = 0; -+ tmp = 0; -+ return 1; -+ } -+ } else if (state->tuner_mtt == 0xE1) { -+ M = state->tuner_crystal / 1000; -+ _mt_fe_tn_set_reg(state, 0x30, 0xff); -+ _mt_fe_tn_set_reg(state, 0x32, 0xe0); -+ _mt_fe_tn_set_reg(state, 0x33, 0x86); -+ _mt_fe_tn_set_reg(state, 0x37, 0x70); -+ _mt_fe_tn_set_reg(state, 0x38, 0x20); -+ _mt_fe_tn_set_reg(state, 0x39, 0x18); -+ _mt_fe_tn_set_reg(state, 0x89, 0x83); -+ if (freq_KHz > cali_freq_thres_div2) { -+ M = M / 4; -+ MUL = 4; -+ tmp = 2; -+ tmp2 = M + 16; /* 48 */ -+ } else if (freq_KHz > cali_freq_thres_div3r) { -+ M = M / 3; -+ MUL = 6; -+ tmp = 2; -+ tmp2 = M + 32; /* 32 */ -+ } else if (freq_KHz > cali_freq_thres_div3) { -+ M = M / 3; -+ MUL = 6; -+ tmp = 2; -+ tmp2 = M; /* 16 */ -+ } else if (freq_KHz > 304000) { -+ M = M / 4; -+ MUL = 8; -+ tmp = 3; -+ tmp2 = M + 16; /* 48 */ -+ } else if (freq_KHz > (cali_freq_thres_div2 / 2)) { -+ M = M / 4; -+ MUL = 8; -+ tmp = 4; -+ tmp2 = M + 16; /* 48 */ -+ } else if (freq_KHz > (cali_freq_thres_div3r / 2)) { -+ M = M / 3; -+ MUL = 12; -+ tmp = 4; -+ tmp2 = M + 32; /* 32 */ -+ } else if (freq_KHz > (cali_freq_thres_div3 / 2)) { -+ M = M / 3; -+ MUL = 12; -+ tmp = 4; -+ tmp2 = M; /* 16 */ -+ } else if (freq_KHz > (cali_freq_thres_div2 / 4)) { -+ M = M / 4; -+ MUL = 16; -+ tmp = 5; -+ tmp2 = M + 16; /* 48 */ -+ } else if (freq_KHz > (cali_freq_thres_div3r / 4)) { -+ M = M / 3; -+ MUL = 24; -+ tmp = 5; -+ tmp2 = M + 32; /* 32 */ -+ } else if (freq_KHz > (cali_freq_thres_div3 / 4)) { -+ M = M / 3; -+ MUL = 24; -+ tmp = 5; -+ tmp2 = M; /* 16 */ -+ } else if (freq_KHz > (cali_freq_thres_div2 / 8)) { -+ M = M / 4; -+ MUL = 32; -+ tmp = 6; -+ tmp2 = M + 16; /* 48 */ -+ } else if (freq_KHz > (cali_freq_thres_div3r / 8)) { -+ M = M / 3; -+ MUL = 48; -+ tmp = 6; -+ tmp2 = M + 32; /* 32 */ -+ } else if (freq_KHz > (cali_freq_thres_div3 / 8)) { -+ M = M / 3; -+ MUL = 48; -+ tmp = 6; -+ tmp2 = M; /* 16 */ -+ } else if (freq_KHz > (cali_freq_thres_div2 / 16)) { -+ M = M / 4; -+ MUL = 64; -+ tmp = 7; -+ tmp2 = M + 16; /* 48 */ -+ } else if (freq_KHz > (cali_freq_thres_div3r / 16)) { -+ M = M / 3; -+ MUL = 96; -+ tmp = 7; -+ tmp2 = M + 32; /* 32 */ -+ } else if (freq_KHz > (cali_freq_thres_div3 / 16)) { -+ M = M / 3; -+ MUL = 96; -+ tmp = 7; -+ tmp2 = M; /* 16 */ -+ } else { /* invalid */ -+ M = M / 4; -+ MUL = 0; -+ tmp = 0; -+ tmp2 = 48; -+ return 1; -+ } -+ if (freq_KHz == 291000) { -+ M = state->tuner_crystal / 1000 / 3; -+ MUL = 12; -+ tmp = 4; -+ tmp2 = M + 32; /* 32 */ -+ } -+ /* -+ if (freq_KHz == 578000) { -+ M = state->tuner_crystal / 1000 / 4; -+ MUL = 4; -+ tmp = 2; -+ tmp2 = M + 16; // 48 -+ } -+ */ -+ if (freq_KHz == 690000) { -+ M = state->tuner_crystal / 1000 / 3; -+ MUL = 4; -+ tmp = 2; -+ tmp2 = M + 16; /* 48 */ -+ } -+ _mt_fe_tn_get_reg(state, 0x33, &buf); -+ buf &= 0xc0; -+ buf += tmp2; -+ _mt_fe_tn_set_reg(state, 0x33, buf); -+ } else { -+ return 1; -+ } -+ _mt_fe_tn_get_reg(state, 0x39, &buf); -+ buf &= 0xf8; -+ buf += tmp; -+ _mt_fe_tn_set_reg(state, 0x39, buf); -+ N = (freq_KHz * MUL * M / crystal_KHz) / 2 * 2 - 256; -+ buf = (N >> 8) & 0xcf; -+ if (state->tuner_mtt == 0xE1) { -+ buf |= 0x30; -+ } -+ _mt_fe_tn_set_reg(state, 0x34, buf); -+ buf = N & 0xff; -+ _mt_fe_tn_set_reg(state, 0x35, buf); -+ F = ((freq_KHz * MUL * M / (crystal_KHz / 1000) / 2) - -+ (freq_KHz * MUL * M / crystal_KHz / 2 * 1000)) * 64 / 1000; -+ buf = F & 0xff; -+ _mt_fe_tn_set_reg(state, 0x36, buf); -+ if (F == 0) { -+ if (state->tuner_mtt == 0xD1) { -+ _mt_fe_tn_set_reg(state, 0x3d, 0xca); -+ } else if (state->tuner_mtt == 0xE1) { -+ _mt_fe_tn_set_reg(state, 0x3d, 0xfe); -+ } else { -+ return 1; -+ } -+ _mt_fe_tn_set_reg(state, 0x3e, 0x9c); -+ _mt_fe_tn_set_reg(state, 0x3f, 0x34); -+ } -+ if (F > 0) { -+ if (state->tuner_mtt == 0xD1) { -+ if ((F == 32) || (F == 16) || (F == 48)) { -+ _mt_fe_tn_set_reg(state, 0x3e, 0xa4); -+ _mt_fe_tn_set_reg(state, 0x3d, 0x4a); -+ _mt_fe_tn_set_reg(state, 0x3f, 0x36); -+ } else { -+ _mt_fe_tn_set_reg(state, 0x3e, 0xa4); -+ _mt_fe_tn_set_reg(state, 0x3d, 0x4a); -+ _mt_fe_tn_set_reg(state, 0x3f, 0x36); -+ } -+ } else if (state->tuner_mtt == 0xE1) { -+ _mt_fe_tn_set_reg(state, 0x3e, 0xa4); -+ _mt_fe_tn_set_reg(state, 0x3d, 0x7e); -+ _mt_fe_tn_set_reg(state, 0x3f, 0x36); -+ _mt_fe_tn_set_reg(state, 0x89, 0x84); -+ _mt_fe_tn_get_reg(state, 0x39, &buf); -+ buf = buf & 0x1f; -+ _mt_fe_tn_set_reg(state, 0x39, buf); -+ _mt_fe_tn_get_reg(state, 0x32, &buf); -+ buf = buf | 0x02; -+ _mt_fe_tn_set_reg(state, 0x32, buf); -+ } else { -+ return 1; -+ } -+ } -+ _mt_fe_tn_set_reg(state, 0x41, 0x00); -+ if (state->tuner_mtt == 0xD1) { -+ msleep(5); -+ } else if (state->tuner_mtt == 0xE1) { -+ msleep(2); -+ } else { -+ return 1; -+ } -+ _mt_fe_tn_set_reg(state, 0x41, 0x02); -+ _mt_fe_tn_set_reg(state, 0x30, 0x7f); -+ _mt_fe_tn_set_reg(state, 0x30, 0xff); -+ _mt_fe_tn_set_reg(state, 0x31, 0x80); -+ _mt_fe_tn_set_reg(state, 0x31, 0x00); -+ -+ return 0; -+} -+ -+static int _mt_fe_tn_set_PLL_freq_tc2800(struct m88dc2800_state *state) -+{ -+ u8 buf, buf1; -+ u32 freq_thres_div2_KHz, freq_thres_div3r_KHz, -+ freq_thres_div3_KHz; -+ const u32 freq_KHz = state->tuner_freq; -+ if (state->tuner_mtt == 0xD1) { -+ _mt_fe_tn_set_reg(state, 0x32, 0xe1); -+ _mt_fe_tn_set_reg(state, 0x33, 0xa6); -+ _mt_fe_tn_set_reg(state, 0x37, 0x7f); -+ _mt_fe_tn_set_reg(state, 0x38, 0x20); -+ _mt_fe_tn_set_reg(state, 0x39, 0x18); -+ _mt_fe_tn_set_reg(state, 0x40, 0x40); -+ freq_thres_div2_KHz = 520000; -+ _mt_fe_tn_cali_PLL_tc2800(state, freq_KHz, -+ freq_thres_div2_KHz, 0, 0); -+ msleep(5); -+ _mt_fe_tn_get_reg(state, 0x3a, &buf); -+ buf1 = buf; -+ buf = buf & 0x03; -+ buf1 = buf1 & 0x01; -+ if ((buf1 == 0) || (buf == 3)) { -+ freq_thres_div2_KHz = 420000; -+ _mt_fe_tn_cali_PLL_tc2800(state, freq_KHz, -+ freq_thres_div2_KHz, 0, -+ 0); -+ msleep(5); -+ _mt_fe_tn_get_reg(state, 0x3a, &buf); -+ buf = buf & 0x07; -+ if (buf == 5) { -+ freq_thres_div2_KHz = 520000; -+ _mt_fe_tn_cali_PLL_tc2800(state, freq_KHz, -+ freq_thres_div2_KHz, -+ 0, 0); -+ msleep(5); -+ } -+ } -+ _mt_fe_tn_get_reg(state, 0x38, &buf); -+ _mt_fe_tn_set_reg(state, 0x38, buf); -+ _mt_fe_tn_get_reg(state, 0x32, &buf); -+ buf = buf | 0x10; -+ _mt_fe_tn_set_reg(state, 0x32, buf); -+ _mt_fe_tn_set_reg(state, 0x30, 0x7f); -+ _mt_fe_tn_set_reg(state, 0x30, 0xff); -+ _mt_fe_tn_get_reg(state, 0x32, &buf); -+ buf = buf & 0xdf; -+ _mt_fe_tn_set_reg(state, 0x32, buf); -+ _mt_fe_tn_set_reg(state, 0x40, 0x0); -+ _mt_fe_tn_set_reg(state, 0x30, 0x7f); -+ _mt_fe_tn_set_reg(state, 0x30, 0xff); -+ _mt_fe_tn_set_reg(state, 0x31, 0x80); -+ _mt_fe_tn_set_reg(state, 0x31, 0x00); -+ msleep(5); -+ _mt_fe_tn_get_reg(state, 0x39, &buf); -+ buf = buf >> 5; -+ if (buf < 5) { -+ _mt_fe_tn_get_reg(state, 0x39, &buf); -+ buf = buf | 0xa0; -+ buf = buf & 0xbf; -+ _mt_fe_tn_set_reg(state, 0x39, buf); -+ _mt_fe_tn_get_reg(state, 0x32, &buf); -+ buf = buf | 0x02; -+ _mt_fe_tn_set_reg(state, 0x32, buf); -+ } -+ _mt_fe_tn_get_reg(state, 0x37, &buf); -+ if (buf > 0x70) { -+ buf = 0x7f; -+ _mt_fe_tn_set_reg(state, 0x40, 0x40); -+ } -+ _mt_fe_tn_set_reg(state, 0x37, buf); -+ _mt_fe_tn_get_reg(state, 0x38, &buf); -+ if (buf < 0x0f) { -+ buf = (buf & 0x0f) << 2; -+ buf = buf + 0x0f; -+ _mt_fe_tn_set_reg(state, 0x37, buf); -+ } else if (buf < 0x1f) { -+ buf = buf + 0x0f; -+ _mt_fe_tn_set_reg(state, 0x37, buf); -+ } -+ _mt_fe_tn_get_reg(state, 0x32, &buf); -+ buf = (buf | 0x20) & 0xef; -+ _mt_fe_tn_set_reg(state, 0x32, buf); -+ _mt_fe_tn_set_reg(state, 0x41, 0x00); -+ msleep(5); -+ _mt_fe_tn_set_reg(state, 0x41, 0x02); -+ } else if (state->tuner_mtt == 0xE1) { -+ freq_thres_div2_KHz = 580000; -+ freq_thres_div3r_KHz = 500000; -+ freq_thres_div3_KHz = 440000; -+ _mt_fe_tn_cali_PLL_tc2800(state, freq_KHz, -+ freq_thres_div2_KHz, -+ freq_thres_div3r_KHz, -+ freq_thres_div3_KHz); -+ msleep(3); -+ _mt_fe_tn_get_reg(state, 0x38, &buf); -+ _mt_fe_tn_set_reg(state, 0x38, buf); -+ _mt_fe_tn_set_reg(state, 0x30, 0x7f); -+ _mt_fe_tn_set_reg(state, 0x30, 0xff); -+ _mt_fe_tn_set_reg(state, 0x31, 0x80); -+ _mt_fe_tn_set_reg(state, 0x31, 0x00); -+ msleep(3); -+ _mt_fe_tn_get_reg(state, 0x38, &buf); -+ _mt_fe_tn_set_reg(state, 0x38, buf); -+ _mt_fe_tn_get_reg(state, 0x32, &buf); -+ buf = buf | 0x10; -+ _mt_fe_tn_set_reg(state, 0x32, buf); -+ _mt_fe_tn_set_reg(state, 0x30, 0x7f); -+ _mt_fe_tn_set_reg(state, 0x30, 0xff); -+ _mt_fe_tn_get_reg(state, 0x32, &buf); -+ buf = buf & 0xdf; -+ _mt_fe_tn_set_reg(state, 0x32, buf); -+ _mt_fe_tn_set_reg(state, 0x31, 0x80); -+ _mt_fe_tn_set_reg(state, 0x31, 0x00); -+ msleep(3); -+ _mt_fe_tn_get_reg(state, 0x37, &buf); -+ _mt_fe_tn_set_reg(state, 0x37, buf); -+ /* -+ if ((freq_KHz == 802000) || (freq_KHz == 826000)) { -+ _mt_fe_tn_set_reg(state, 0x37, 0x5e); -+ } -+ */ -+ _mt_fe_tn_get_reg(state, 0x32, &buf); -+ buf = (buf & 0xef) | 0x30; -+ _mt_fe_tn_set_reg(state, 0x32, buf); -+ _mt_fe_tn_set_reg(state, 0x41, 0x00); -+ msleep(2); -+ _mt_fe_tn_set_reg(state, 0x41, 0x02); -+ } else { -+ return 1; -+ } -+ return 0; -+} -+ -+static int _mt_fe_tn_set_BB_tc2800(struct m88dc2800_state *state) -+{ -+ return 0; -+} -+ -+ static int _mt_fe_tn_set_appendix_tc2800(struct m88dc2800_state *state) -+ -+{ -+ u8 buf; -+ const u32 freq_KHz = state->tuner_freq; -+ if (state->tuner_mtt == 0xD1) { -+ if ((freq_KHz == 123000) || (freq_KHz == 147000) || -+ (freq_KHz == 171000) || (freq_KHz == 195000)) { -+ _mt_fe_tn_set_reg(state, 0x20, 0x1b); -+ } -+ if ((freq_KHz == 371000) || (freq_KHz == 419000) || -+ (freq_KHz == 610000) || (freq_KHz == 730000) || -+ (freq_KHz == 754000) || (freq_KHz == 826000)) { -+ _mt_fe_tn_get_reg(state, 0x0d, &buf); -+ _mt_fe_tn_set_reg(state, 0x0d, (u8) (buf + 1)); -+ } -+ if ((freq_KHz == 522000) || (freq_KHz == 578000) || -+ (freq_KHz == 634000) || (freq_KHz == 690000) || -+ (freq_KHz == 834000)) { -+ _mt_fe_tn_get_reg(state, 0x0d, &buf); -+ _mt_fe_tn_set_reg(state, 0x0d, (u8) (buf - 1)); -+ } -+ } else if (state->tuner_mtt == 0xE1) { -+ _mt_fe_tn_set_reg(state, 0x20, 0xfc); -+ if (freq_KHz == 123000 || freq_KHz == 147000 || -+ freq_KHz == 171000 || freq_KHz == 195000 || -+ freq_KHz == 219000 || freq_KHz == 267000 || -+ freq_KHz == 291000 || freq_KHz == 339000 || -+ freq_KHz == 387000 || freq_KHz == 435000 || -+ freq_KHz == 482000 || freq_KHz == 530000 || -+ freq_KHz == 722000 || -+ (state->tuner_custom_cfg == 1 && freq_KHz == 315000)) { -+ _mt_fe_tn_set_reg(state, 0x20, 0x5c); -+ } -+ } -+ return 0; -+} -+ -+ static int _mt_fe_tn_set_DAC_tc2800(struct m88dc2800_state *state) -+{ -+ u8 buf, tempnumber; -+ s32 N; -+ s32 f1f2number, f1, f2, delta1, Totalnum1; -+ s32 cntT, cntin, NCOI, z0, z1, z2, tmp; -+ u32 fc, fadc, fsd, f2d; -+ u32 FreqTrue108_Hz; -+ s32 M = state->tuner_crystal / 4000; -+ /* const u8 bandwidth = state->tuner_bandwidth; */ -+ const u16 DAC_fre = 108; -+ const u32 crystal_KHz = state->tuner_crystal; -+ const u32 DACFreq_KHz = state->tuner_dac; -+ const u32 freq_KHz = state->tuner_freq; -+ -+ if (state->tuner_mtt == 0xE1) { -+ _mt_fe_tn_get_reg(state, 0x33, &buf); -+ M = buf & 0x0f; -+ if (M == 0) -+ M = 6; -+ } -+ _mt_fe_tn_get_reg(state, 0x34, &buf); -+ N = buf & 0x07; -+ _mt_fe_tn_get_reg(state, 0x35, &buf); -+ N = (N << 8) + buf; -+ buf = ((N + 256) * crystal_KHz / M / DAC_fre + 500) / 1000; -+ if (state->tuner_mtt == 0xE1) { -+ _mt_fe_tn_set_appendix_tc2800(state); -+ if (freq_KHz == 187000 || freq_KHz == 195000 || -+ freq_KHz == 131000 || freq_KHz == 211000 || -+ freq_KHz == 219000 || freq_KHz == 227000 || -+ freq_KHz == 267000 || freq_KHz == 299000 || -+ freq_KHz == 347000 || freq_KHz == 363000 || -+ freq_KHz == 395000 || freq_KHz == 403000 || -+ freq_KHz == 435000 || freq_KHz == 482000 || -+ freq_KHz == 474000 || freq_KHz == 490000 || -+ freq_KHz == 610000 || freq_KHz == 642000 || -+ freq_KHz == 666000 || freq_KHz == 722000 || -+ freq_KHz == 754000 || -+ ((freq_KHz == 379000 || freq_KHz == 467000 || -+ freq_KHz == 762000) && state->tuner_custom_cfg != 1)) { -+ buf = buf + 1; -+ } -+ if (freq_KHz == 123000 || freq_KHz == 139000 || -+ freq_KHz == 147000 || freq_KHz == 171000 || -+ freq_KHz == 179000 || freq_KHz == 203000 || -+ freq_KHz == 235000 || freq_KHz == 251000 || -+ freq_KHz == 259000 || freq_KHz == 283000 || -+ freq_KHz == 331000 || freq_KHz == 363000 || -+ freq_KHz == 371000 || freq_KHz == 387000 || -+ freq_KHz == 411000 || freq_KHz == 427000 || -+ freq_KHz == 443000 || freq_KHz == 451000 || -+ freq_KHz == 459000 || freq_KHz == 506000 || -+ freq_KHz == 514000 || freq_KHz == 538000 || -+ freq_KHz == 546000 || freq_KHz == 554000 || -+ freq_KHz == 562000 || freq_KHz == 570000 || -+ freq_KHz == 578000 || freq_KHz == 602000 || -+ freq_KHz == 626000 || freq_KHz == 658000 || -+ freq_KHz == 690000 || freq_KHz == 714000 || -+ freq_KHz == 746000 || freq_KHz == 522000 || -+ freq_KHz == 826000 || freq_KHz == 155000 || -+ freq_KHz == 530000 || -+ ((freq_KHz == 275000 || freq_KHz == 355000) && -+ state->tuner_custom_cfg != 1) || -+ ((freq_KHz == 467000 || freq_KHz == 762000 || -+ freq_KHz == 778000 || freq_KHz == 818000) && -+ state->tuner_custom_cfg == 1)) { -+ buf = buf - 1; -+ } -+ } -+ _mt_fe_tn_set_reg(state, 0x0e, buf); -+ _mt_fe_tn_set_reg(state, 0x0d, buf); -+ f1f2number = -+ (((DACFreq_KHz * M * buf) / crystal_KHz) << 16) / (N + 256) + -+ (((DACFreq_KHz * M * buf) % crystal_KHz) << 16) / ((N + 256) * -+ crystal_KHz); -+ _mt_fe_tn_set_reg(state, 0xf1, (f1f2number & 0xff00) >> 8); -+ _mt_fe_tn_set_reg(state, 0xf2, f1f2number & 0x00ff); -+ FreqTrue108_Hz = -+ (N + 256) * crystal_KHz / (M * buf) * 1000 + -+ (((N + 256) * crystal_KHz) % (M * buf)) * 1000 / (M * buf); -+ f1 = 4096; -+ fc = FreqTrue108_Hz; -+ fadc = fc / 4; -+ fsd = 27000000; -+ f2d = state->tuner_bandwidth * 1000 / 2 - 150; -+ f2 = (fsd / 250) * f2d / ((fc + 500) / 1000); -+ delta1 = ((f1 - f2) << 15) / f2; -+ Totalnum1 = ((f1 - f2) << 15) - delta1 * f2; -+ cntT = f2; -+ cntin = Totalnum1; -+ NCOI = delta1; -+ z0 = cntin; -+ z1 = cntT; -+ z2 = NCOI; -+ tempnumber = (z0 & 0xff00) >> 8; -+ _mt_fe_tn_set_reg(state, 0xc9, (u8) (tempnumber & 0x0f)); -+ tempnumber = (z0 & 0xff); -+ _mt_fe_tn_set_reg(state, 0xca, tempnumber); -+ tempnumber = (z1 & 0xff00) >> 8; -+ _mt_fe_tn_set_reg(state, 0xcb, tempnumber); -+ tempnumber = (z1 & 0xff); -+ _mt_fe_tn_set_reg(state, 0xcc, tempnumber); -+ tempnumber = (z2 & 0xff00) >> 8; -+ _mt_fe_tn_set_reg(state, 0xcd, tempnumber); -+ tempnumber = (z2 & 0xff); -+ _mt_fe_tn_set_reg(state, 0xce, tempnumber); -+ tmp = f1; -+ f1 = f2; -+ f2 = tmp / 2; -+ delta1 = ((f1 - f2) << 15) / f2; -+ Totalnum1 = ((f1 - f2) << 15) - delta1 * f2; -+ NCOI = (f1 << 15) / f2 - (1 << 15); -+ cntT = f2; -+ cntin = Totalnum1; -+ z0 = cntin; -+ z1 = cntT; -+ z2 = NCOI; -+ tempnumber = (z0 & 0xff00) >> 8; -+ _mt_fe_tn_set_reg(state, 0xd9, (u8) (tempnumber & 0x0f)); -+ tempnumber = (z0 & 0xff); -+ _mt_fe_tn_set_reg(state, 0xda, tempnumber); -+ tempnumber = (z1 & 0xff00) >> 8; -+ _mt_fe_tn_set_reg(state, 0xdb, tempnumber); -+ tempnumber = (z1 & 0xff); -+ _mt_fe_tn_set_reg(state, 0xdc, tempnumber); -+ tempnumber = (z2 & 0xff00) >> 8; -+ _mt_fe_tn_set_reg(state, 0xdd, tempnumber); -+ tempnumber = (z2 & 0xff); -+ _mt_fe_tn_set_reg(state, 0xde, tempnumber); -+ -+ return 0; -+} -+ -+static int _mt_fe_tn_preset_tc2800(struct m88dc2800_state *state) -+{ -+ if (state->tuner_mtt == 0xD1) { -+ _mt_fe_tn_set_reg(state, 0x19, 0x4a); -+ _mt_fe_tn_set_reg(state, 0x1b, 0x4b); -+ _mt_fe_tn_set_reg(state, 0x04, 0x04); -+ _mt_fe_tn_set_reg(state, 0x17, 0x0d); -+ _mt_fe_tn_set_reg(state, 0x62, 0x6c); -+ _mt_fe_tn_set_reg(state, 0x63, 0xf4); -+ _mt_fe_tn_set_reg(state, 0x1f, 0x0e); -+ _mt_fe_tn_set_reg(state, 0x6b, 0xf4); -+ _mt_fe_tn_set_reg(state, 0x14, 0x01); -+ _mt_fe_tn_set_reg(state, 0x5a, 0x75); -+ _mt_fe_tn_set_reg(state, 0x66, 0x74); -+ _mt_fe_tn_set_reg(state, 0x72, 0xe0); -+ _mt_fe_tn_set_reg(state, 0x70, 0x07); -+ _mt_fe_tn_set_reg(state, 0x15, 0x7b); -+ _mt_fe_tn_set_reg(state, 0x55, 0x71); -+ _mt_fe_tn_set_reg(state, 0x75, 0x55); -+ _mt_fe_tn_set_reg(state, 0x76, 0xac); -+ _mt_fe_tn_set_reg(state, 0x77, 0x6c); -+ _mt_fe_tn_set_reg(state, 0x78, 0x8b); -+ _mt_fe_tn_set_reg(state, 0x79, 0x42); -+ _mt_fe_tn_set_reg(state, 0x7a, 0xd2); -+ _mt_fe_tn_set_reg(state, 0x81, 0x01); -+ _mt_fe_tn_set_reg(state, 0x82, 0x00); -+ _mt_fe_tn_set_reg(state, 0x82, 0x02); -+ _mt_fe_tn_set_reg(state, 0x82, 0x04); -+ _mt_fe_tn_set_reg(state, 0x82, 0x06); -+ _mt_fe_tn_set_reg(state, 0x82, 0x08); -+ _mt_fe_tn_set_reg(state, 0x82, 0x09); -+ _mt_fe_tn_set_reg(state, 0x82, 0x29); -+ _mt_fe_tn_set_reg(state, 0x82, 0x49); -+ _mt_fe_tn_set_reg(state, 0x82, 0x58); -+ _mt_fe_tn_set_reg(state, 0x82, 0x59); -+ _mt_fe_tn_set_reg(state, 0x82, 0x98); -+ _mt_fe_tn_set_reg(state, 0x82, 0x99); -+ _mt_fe_tn_set_reg(state, 0x10, 0x05); -+ _mt_fe_tn_set_reg(state, 0x10, 0x0d); -+ _mt_fe_tn_set_reg(state, 0x11, 0x95); -+ _mt_fe_tn_set_reg(state, 0x11, 0x9d); -+ if (state->tuner_loopthrough != 0) { -+ _mt_fe_tn_set_reg(state, 0x67, 0x25); -+ } else { -+ _mt_fe_tn_set_reg(state, 0x67, 0x05); -+ } -+ } else if (state->tuner_mtt == 0xE1) { -+ _mt_fe_tn_set_reg(state, 0x1b, 0x47); -+ if (state->tuner_mode == 0) { /* DVB-C */ -+ _mt_fe_tn_set_reg(state, 0x66, 0x74); -+ _mt_fe_tn_set_reg(state, 0x62, 0x2c); -+ _mt_fe_tn_set_reg(state, 0x63, 0x54); -+ _mt_fe_tn_set_reg(state, 0x68, 0x0b); -+ _mt_fe_tn_set_reg(state, 0x14, 0x00); -+ } else { /* CTTB */ -+ _mt_fe_tn_set_reg(state, 0x66, 0x74); -+ _mt_fe_tn_set_reg(state, 0x62, 0x0c); -+ _mt_fe_tn_set_reg(state, 0x63, 0x54); -+ _mt_fe_tn_set_reg(state, 0x68, 0x0b); -+ _mt_fe_tn_set_reg(state, 0x14, 0x05); -+ } -+ _mt_fe_tn_set_reg(state, 0x6f, 0x00); -+ _mt_fe_tn_set_reg(state, 0x84, 0x04); -+ _mt_fe_tn_set_reg(state, 0x5e, 0xbe); -+ _mt_fe_tn_set_reg(state, 0x87, 0x07); -+ _mt_fe_tn_set_reg(state, 0x8a, 0x1f); -+ _mt_fe_tn_set_reg(state, 0x8b, 0x1f); -+ _mt_fe_tn_set_reg(state, 0x88, 0x30); -+ _mt_fe_tn_set_reg(state, 0x58, 0x34); -+ _mt_fe_tn_set_reg(state, 0x61, 0x8c); -+ _mt_fe_tn_set_reg(state, 0x6a, 0x42); -+ } -+ return 0; -+} -+ -+static int mt_fe_tn_wakeup_tc2800(struct m88dc2800_state *state) -+{ -+ _mt_fe_tn_set_reg(state, 0x16, 0xb1); -+ _mt_fe_tn_set_reg(state, 0x09, 0x7d); -+ return 0; -+} -+ -+ static int mt_fe_tn_sleep_tc2800(struct m88dc2800_state *state) -+{ -+ _mt_fe_tn_set_reg(state, 0x16, 0xb0); -+ _mt_fe_tn_set_reg(state, 0x09, 0x6d); -+ return 0; -+} -+ -+ static int mt_fe_tn_init_tc2800(struct m88dc2800_state *state) -+{ -+ if (state->tuner_init_OK != 1) { -+ state->tuner_dev_addr = 0x61; /* TUNER_I2C_ADDR_TC2800 */ -+ state->tuner_freq = 650000; -+ state->tuner_qam = 0; -+ state->tuner_mode = 0; // 0: DVB-C, 1: CTTB -+ state->tuner_bandwidth = 8; -+ state->tuner_loopthrough = 0; -+ state->tuner_crystal = 24000; -+ state->tuner_dac = 7200; -+ state->tuner_mtt = 0x00; -+ state->tuner_custom_cfg = 0; -+ state->tuner_version = 30022; /* Driver version number */ -+ state->tuner_time = 12092611; -+ state->tuner_init_OK = 1; -+ } -+ _mt_fe_tn_set_reg(state, 0x2b, 0x46); -+ _mt_fe_tn_set_reg(state, 0x2c, 0x75); -+ if (state->tuner_mtt == 0x00) { -+ u8 tmp = 0; -+ _mt_fe_tn_get_reg(state, 0x01, &tmp); -+ printk(KERN_INFO "m88dc2800: tuner id = 0x%02x ", tmp); -+ switch (tmp) { -+ case 0x0d: -+ state->tuner_mtt = 0xD1; -+ break; -+ case 0x8e: -+ default: -+ state->tuner_mtt = 0xE1; -+ break; -+ } -+ } -+ return 0; -+} -+ -+ static int mt_fe_tn_set_freq_tc2800(struct m88dc2800_state *state, -+ u32 freq_KHz) -+{ -+ u8 buf; -+ u8 buf1; -+ -+ mt_fe_tn_init_tc2800(state); -+ state->tuner_freq = freq_KHz; -+ _mt_fe_tn_set_reg(state, 0x21, freq_KHz > 500000 ? 0xb9 : 0x99); -+ mt_fe_tn_wakeup_tc2800(state); -+ _mt_fe_tn_set_reg(state, 0x05, 0x7f); -+ _mt_fe_tn_set_reg(state, 0x06, 0xf8); -+ _mt_fe_tn_set_RF_front_tc2800(state); -+ _mt_fe_tn_set_PLL_freq_tc2800(state); -+ _mt_fe_tn_set_DAC_tc2800(state); -+ _mt_fe_tn_set_BB_tc2800(state); -+ _mt_fe_tn_preset_tc2800(state); -+ _mt_fe_tn_set_reg(state, 0x05, 0x00); -+ _mt_fe_tn_set_reg(state, 0x06, 0x00); -+ if (state->tuner_mtt == 0xD1) { -+ _mt_fe_tn_set_reg(state, 0x00, 0x01); -+ _mt_fe_tn_set_reg(state, 0x00, 0x00); -+ msleep(5); -+ _mt_fe_tn_set_reg(state, 0x41, 0x00); -+ msleep(5); -+ _mt_fe_tn_set_reg(state, 0x41, 0x02); -+ -+ _mt_fe_tn_get_reg(state, 0x69, &buf1); -+ buf1 = buf1 & 0x0f; -+ _mt_fe_tn_get_reg(state, 0x61, &buf); -+ buf = buf & 0x0f; -+ if (buf == 0x0c) -+ _mt_fe_tn_set_reg(state, 0x6a, 0x59); -+ if (buf1 > 0x02) { -+ if (freq_KHz > 600000) -+ _mt_fe_tn_set_reg(state, 0x66, 0x44); -+ else if (freq_KHz > 500000) -+ _mt_fe_tn_set_reg(state, 0x66, 0x64); -+ else -+ _mt_fe_tn_set_reg(state, 0x66, 0x74); -+ } -+ if (buf1 < 0x03) { -+ if (freq_KHz > 800000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x64); -+ else if (freq_KHz > 600000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x54); -+ else if (freq_KHz > 500000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x54); -+ else if (freq_KHz > 300000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x43); -+ else if (freq_KHz > 220000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x54); -+ else if (freq_KHz > 110000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x14); -+ else -+ _mt_fe_tn_set_reg(state, 0x87, 0x54); -+ msleep(5); -+ } else if (buf < 0x0c) { -+ if (freq_KHz > 800000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x14); -+ else if (freq_KHz > 600000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x14); -+ else if (freq_KHz > 500000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x34); -+ else if (freq_KHz > 300000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x43); -+ else if (freq_KHz > 220000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x54); -+ else if (freq_KHz > 110000) -+ _mt_fe_tn_set_reg(state, 0x87, 0x14); -+ else -+ _mt_fe_tn_set_reg(state, 0x87, 0x54); -+ msleep(5); -+ } -+ } else if ((state->tuner_mtt == 0xE1)) { -+ _mt_fe_tn_set_reg(state, 0x00, 0x01); -+ _mt_fe_tn_set_reg(state, 0x00, 0x00); -+ msleep(20); -+ _mt_fe_tn_get_reg(state, 0x32, &buf); -+ buf = (buf & 0xef) | 0x28; -+ _mt_fe_tn_set_reg(state, 0x32, buf); -+ msleep(50); -+ _mt_fe_tn_get_reg(state, 0x38, &buf); -+ _mt_fe_tn_set_reg(state, 0x38, buf); -+ _mt_fe_tn_get_reg(state, 0x32, &buf); -+ buf = (buf & 0xf7) | 0x10; -+ _mt_fe_tn_set_reg(state, 0x32, buf); -+ msleep(10); -+ _mt_fe_tn_get_reg(state, 0x69, &buf); -+ buf = buf & 0x03; -+ _mt_fe_tn_set_reg(state, 0x2a, buf); -+ if (buf > 0) { -+ msleep(20); -+ _mt_fe_tn_get_reg(state, 0x84, &buf); -+ buf = buf & 0x1f; -+ _mt_fe_tn_set_reg(state, 0x68, 0x0a); -+ _mt_fe_tn_get_reg(state, 0x88, &buf1); -+ buf1 = buf1 & 0x1f; -+ if (buf <= buf1) -+ _mt_fe_tn_set_reg(state, 0x66, 0x44); -+ else -+ _mt_fe_tn_set_reg(state, 0x66, 0x74); -+ } else { -+ if (freq_KHz <= 600000) -+ _mt_fe_tn_set_reg(state, 0x68, 0x0c); -+ else -+ _mt_fe_tn_set_reg(state, 0x68, 0x0e); -+ _mt_fe_tn_set_reg(state, 0x30, 0xfb); -+ _mt_fe_tn_set_reg(state, 0x30, 0xff); -+ _mt_fe_tn_set_reg(state, 0x31, 0x04); -+ _mt_fe_tn_set_reg(state, 0x31, 0x00); -+ } -+ if (state->tuner_loopthrough != 0) { -+ _mt_fe_tn_get_reg(state, 0x28, &buf); -+ if (buf == 0) { -+ _mt_fe_tn_set_reg(state, 0x28, 0xff); -+ _mt_fe_tn_get_reg(state, 0x61, &buf); -+ buf = buf & 0x0f; -+ if (buf > 9) -+ _mt_fe_tn_set_reg(state, 0x67, 0x74); -+ else if (buf > 6) -+ _mt_fe_tn_set_reg(state, 0x67, 0x64); -+ else if (buf > 3) -+ _mt_fe_tn_set_reg(state, 0x67, 0x54); -+ else -+ _mt_fe_tn_set_reg(state, 0x67, 0x44); -+ } -+ } else { -+ _mt_fe_tn_set_reg(state, 0x67, 0x34); -+ } -+ } else { -+ return 1; -+ } -+ return 0; -+} -+ -+ -+/* -+static int mt_fe_tn_set_BB_filter_band_tc2800(struct m88dc2800_state *state, -+ u8 bandwidth) -+{ -+ u8 buf, tmp; -+ -+ _mt_fe_tn_get_reg(state, 0x53, &tmp); -+ -+ if (bandwidth == 6) -+ buf = 0x01 << 1; -+ else if (bandwidth == 7) -+ buf = 0x02 << 1; -+ else if (bandwidth == 8) -+ buf = 0x04 << 1; -+ else -+ buf = 0x04 << 1; -+ -+ tmp &= 0xf1; -+ tmp |= buf; -+ _mt_fe_tn_set_reg(state, 0x53, tmp); -+ state->tuner_bandwidth = bandwidth; -+ return 0; -+} -+*/ -+ -+static s32 mt_fe_tn_get_signal_strength_tc2800(struct m88dc2800_state -+ *state) -+{ -+ s32 level = -107; -+ s32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6; -+ s32 val1, val2, val; -+ s32 result2, result3, result4, result5, result6; -+ s32 append; -+ u8 tmp; -+ s32 freq_KHz = (s32) state->tuner_freq; -+ if (state->tuner_mtt == 0xD1) { -+ _mt_fe_tn_get_reg(state, 0x61, &tmp); -+ tmp1 = tmp & 0x0f; -+ _mt_fe_tn_get_reg(state, 0x69, &tmp); -+ tmp2 = tmp & 0x0f; -+ _mt_fe_tn_get_reg(state, 0x73, &tmp); -+ tmp3 = tmp & 0x07; -+ _mt_fe_tn_get_reg(state, 0x7c, &tmp); -+ tmp4 = (tmp >> 4) & 0x0f; -+ _mt_fe_tn_get_reg(state, 0x7b, &tmp); -+ tmp5 = tmp & 0x0f; -+ _mt_fe_tn_get_reg(state, 0x7f, &tmp); -+ tmp6 = (tmp >> 5) & 0x01; -+ if (tmp1 > 6) { -+ val1 = 0; -+ if (freq_KHz <= 200000) { -+ val2 = (tmp1 - 6) * 267; -+ } else if (freq_KHz <= 600000) { -+ val2 = (tmp1 - 6) * 280; -+ } else { -+ val2 = (tmp1 - 6) * 290; -+ } -+ val = val1 + val2; -+ } else { -+ if (tmp1 == 0) { -+ val1 = -550; -+ } else { -+ val1 = 0; -+ } -+ if ((tmp1 < 4) && (freq_KHz >= 506000)) { -+ val1 = -850; -+ } -+ val2 = 0; -+ val = val1 + val2; -+ } -+ if (freq_KHz <= 95000) { -+ result2 = tmp2 * 289; -+ } else if (freq_KHz <= 155000) { -+ result2 = tmp2 * 278; -+ } else if (freq_KHz <= 245000) { -+ result2 = tmp2 * 267; -+ } else if (freq_KHz <= 305000) { -+ result2 = tmp2 * 256; -+ } else if (freq_KHz <= 335000) { -+ result2 = tmp2 * 244; -+ } else if (freq_KHz <= 425000) { -+ result2 = tmp2 * 233; -+ } else if (freq_KHz <= 575000) { -+ result2 = tmp2 * 222; -+ } else if (freq_KHz <= 665000) { -+ result2 = tmp2 * 211; -+ } else { -+ result2 = tmp2 * 200; -+ } -+ result3 = (6 - tmp3) * 100; -+ result4 = 300 * tmp4; -+ result5 = 50 * tmp5; -+ result6 = 300 * tmp6; -+ if (freq_KHz < 105000) { -+ append = -450; -+ } else if (freq_KHz <= 227000) { -+ append = -4 * (freq_KHz / 1000 - 100) + 150; -+ } else if (freq_KHz <= 305000) { -+ append = -4 * (freq_KHz / 1000 - 100); -+ } else if (freq_KHz <= 419000) { -+ append = 500 - 40 * (freq_KHz / 1000 - 300) / 17 + 130; -+ } else if (freq_KHz <= 640000) { -+ append = 500 - 40 * (freq_KHz / 1000 - 300) / 17; -+ } else { -+ append = -500; -+ } -+ level = append - (val + result2 + result3 + result4 + -+ result5 + result6); -+ level /= 100; -+ } else if (state->tuner_mtt == 0xE1) { -+ _mt_fe_tn_get_reg(state, 0x61, &tmp); -+ tmp1 = tmp & 0x0f; -+ _mt_fe_tn_get_reg(state, 0x84, &tmp); -+ tmp2 = tmp & 0x1f; -+ _mt_fe_tn_get_reg(state, 0x69, &tmp); -+ tmp3 = tmp & 0x03; -+ _mt_fe_tn_get_reg(state, 0x73, &tmp); -+ tmp4 = tmp & 0x0f; -+ _mt_fe_tn_get_reg(state, 0x7c, &tmp); -+ tmp5 = (tmp >> 4) & 0x0f; -+ _mt_fe_tn_get_reg(state, 0x7b, &tmp); -+ tmp6 = tmp & 0x0f; -+ if (freq_KHz < 151000) { -+ result2 = (1150 - freq_KHz / 100) * 163 / 33 + 4230; -+ result3 = (1150 - freq_KHz / 100) * 115 / 33 + 1850; -+ result4 = -3676 * (freq_KHz / 1000) / 100 + 6115; -+ } else if (freq_KHz < 257000) { -+ result2 = (1540 - freq_KHz / 100) * 11 / 4 + 3870; -+ result3 = (1540 - freq_KHz / 100) * 205 / 96 + 2100; -+ result4 = -21 * freq_KHz / 1000 + 5084; -+ } else if (freq_KHz < 305000) { -+ result2 = (2620 - freq_KHz / 100) * 5 / 3 + 2770; -+ result3 = (2620 - freq_KHz / 100) * 10 / 7 + 1700; -+ result4 = 650; -+ } else if (freq_KHz < 449000) { -+ result2 = (307 - freq_KHz / 1000) * 82 / 27 + 11270; -+ result3 = (3100 - freq_KHz / 100) * 5 / 3 + 10000; -+ result4 = 134 * freq_KHz / 10000 + 11875; -+ } else { -+ result2 = (307 - freq_KHz / 1000) * 82 / 27 + 11270; -+ result3 = 8400; -+ result4 = 5300; -+ } -+ if (tmp1 > 6) { -+ val1 = result2; -+ val2 = 2900; -+ val = 500; -+ } else if (tmp1 > 0) { -+ val1 = result3; -+ val2 = 2700; -+ val = 500; -+ } else { -+ val1 = result4; -+ val2 = 2700; -+ val = 400; -+ } -+ level = val1 - (val2 * tmp1 + 500 * tmp2 + 3000 * tmp3 - -+ 500 * tmp4 + 3000 * tmp5 + val * tmp6) - 1000; -+ level /= 1000; -+ } -+ return level; -+} -+ -+ -+/* m88dc2800 operation functions */ -+u8 M88DC2000GetLock(struct m88dc2800_state * state) -+{ -+ u8 u8ret = 0; -+ if (ReadReg(state, 0x80) < 0x06) { -+ if ((ReadReg(state, 0xdf) & 0x80) == 0x80 -+ &&(ReadReg(state, 0x91) & 0x23) == 0x03 -+ &&(ReadReg(state, 0x43) & 0x08) == 0x08) -+ u8ret = 1; -+ else -+ u8ret = 0; -+ } else { -+ if ((ReadReg(state, 0x85) & 0x08) == 0x08) -+ u8ret = 1; -+ else -+ u8ret = 0; -+ } -+ dprintk("%s, lock=%d\n", __func__, u8ret); -+ return u8ret; -+} -+ -+static int M88DC2000SetTsType(struct m88dc2800_state *state, u8 type) -+{ -+ u8 regC2H; -+ -+ if (type == 3) { -+ WriteReg(state, 0x84, 0x6A); -+ WriteReg(state, 0xC0, 0x43); -+ WriteReg(state, 0xE2, 0x06); -+ regC2H = ReadReg(state, 0xC2); -+ regC2H &= 0xC0; -+ regC2H |= 0x1B; -+ WriteReg(state, 0xC2, regC2H); -+ WriteReg(state, 0xC1, 0x60); /* common interface */ -+ } else if (type == 1) { -+ WriteReg(state, 0x84, 0x6A); -+ WriteReg(state, 0xC0, 0x47); /* serial format */ -+ WriteReg(state, 0xE2, 0x02); -+ regC2H = ReadReg(state, 0xC2); -+ regC2H &= 0xC7; -+ WriteReg(state, 0xC2, regC2H); -+ WriteReg(state, 0xC1, 0x00); -+ } else { -+ WriteReg(state, 0x84, 0x6C); -+ WriteReg(state, 0xC0, 0x43); /* parallel format */ -+ WriteReg(state, 0xE2, 0x06); -+ regC2H = ReadReg(state, 0xC2); -+ regC2H &= 0xC7; -+ WriteReg(state, 0xC2, regC2H); -+ WriteReg(state, 0xC1, 0x00); -+ } -+ return 0; -+} -+ -+static int M88DC2000RegInitial_TC2800(struct m88dc2800_state *state) -+{ -+ u8 RegE3H, RegE4H; -+ -+ WriteReg(state, 0x00, 0x48); -+ WriteReg(state, 0x01, 0x09); -+ WriteReg(state, 0xFB, 0x0A); -+ WriteReg(state, 0xFC, 0x0B); -+ WriteReg(state, 0x02, 0x0B); -+ WriteReg(state, 0x03, 0x18); -+ WriteReg(state, 0x05, 0x0D); -+ WriteReg(state, 0x36, 0x80); -+ WriteReg(state, 0x43, 0x40); -+ WriteReg(state, 0x55, 0x7A); -+ WriteReg(state, 0x56, 0xD9); -+ WriteReg(state, 0x57, 0xDF); -+ WriteReg(state, 0x58, 0x39); -+ WriteReg(state, 0x5A, 0x00); -+ WriteReg(state, 0x5C, 0x71); -+ WriteReg(state, 0x5D, 0x23); -+ WriteReg(state, 0x86, 0x40); -+ WriteReg(state, 0xF9, 0x08); -+ WriteReg(state, 0x61, 0x40); -+ WriteReg(state, 0x62, 0x0A); -+ WriteReg(state, 0x90, 0x06); -+ WriteReg(state, 0xDE, 0x00); -+ WriteReg(state, 0xA0, 0x03); -+ WriteReg(state, 0xDF, 0x81); -+ WriteReg(state, 0xFA, 0x40); -+ WriteReg(state, 0x37, 0x10); -+ WriteReg(state, 0xF0, 0x40); -+ WriteReg(state, 0xF2, 0x9C); -+ WriteReg(state, 0xF3, 0x40); -+ RegE3H = ReadReg(state, 0xE3); -+ RegE4H = ReadReg(state, 0xE4); -+ if (((RegE3H & 0xC0) == 0x00) && ((RegE4H & 0xC0) == 0x00)) { -+ WriteReg(state, 0x30, 0xFF); -+ WriteReg(state, 0x31, 0x00); -+ WriteReg(state, 0x32, 0x00); -+ WriteReg(state, 0x33, 0x00); -+ WriteReg(state, 0x35, 0x32); -+ WriteReg(state, 0x40, 0x00); -+ WriteReg(state, 0x41, 0x10); -+ WriteReg(state, 0xF1, 0x02); -+ WriteReg(state, 0xF4, 0x04); -+ WriteReg(state, 0xF5, 0x00); -+ WriteReg(state, 0x42, 0x14); -+ WriteReg(state, 0xE1, 0x25); -+ } else if (((RegE3H & 0xC0) == 0x80) && ((RegE4H & 0xC0) == 0x40)) { -+ WriteReg(state, 0x30, 0xFF); -+ WriteReg(state, 0x31, 0x00); -+ WriteReg(state, 0x32, 0x00); -+ WriteReg(state, 0x33, 0x00); -+ WriteReg(state, 0x35, 0x32); -+ WriteReg(state, 0x39, 0x00); -+ WriteReg(state, 0x3A, 0x00); -+ WriteReg(state, 0x40, 0x00); -+ WriteReg(state, 0x41, 0x10); -+ WriteReg(state, 0xF1, 0x00); -+ WriteReg(state, 0xF4, 0x00); -+ WriteReg(state, 0xF5, 0x40); -+ WriteReg(state, 0x42, 0x14); -+ WriteReg(state, 0xE1, 0x25); -+ } else if ((RegE3H == 0x80 || RegE3H == 0x81) -+ && (RegE4H == 0x80 || RegE4H == 0x81)) { -+ WriteReg(state, 0x30, 0xFF); -+ WriteReg(state, 0x31, 0x00); -+ WriteReg(state, 0x32, 0x00); -+ WriteReg(state, 0x33, 0x00); -+ WriteReg(state, 0x35, 0x32); -+ WriteReg(state, 0x39, 0x00); -+ WriteReg(state, 0x3A, 0x00); -+ WriteReg(state, 0xF1, 0x00); -+ WriteReg(state, 0xF4, 0x00); -+ WriteReg(state, 0xF5, 0x40); -+ WriteReg(state, 0x42, 0x24); -+ WriteReg(state, 0xE1, 0x25); -+ WriteReg(state, 0x92, 0x7F); -+ WriteReg(state, 0x93, 0x91); -+ WriteReg(state, 0x95, 0x00); -+ WriteReg(state, 0x2B, 0x33); -+ WriteReg(state, 0x2A, 0x2A); -+ WriteReg(state, 0x2E, 0x80); -+ WriteReg(state, 0x25, 0x25); -+ WriteReg(state, 0x2D, 0xFF); -+ WriteReg(state, 0x26, 0xFF); -+ WriteReg(state, 0x27, 0x00); -+ WriteReg(state, 0x24, 0x25); -+ WriteReg(state, 0xA4, 0xFF); -+ WriteReg(state, 0xA3, 0x0D); -+ } else { -+ WriteReg(state, 0x30, 0xFF); -+ WriteReg(state, 0x31, 0x00); -+ WriteReg(state, 0x32, 0x00); -+ WriteReg(state, 0x33, 0x00); -+ WriteReg(state, 0x35, 0x32); -+ WriteReg(state, 0x39, 0x00); -+ WriteReg(state, 0x3A, 0x00); -+ WriteReg(state, 0xF1, 0x00); -+ WriteReg(state, 0xF4, 0x00); -+ WriteReg(state, 0xF5, 0x40); -+ WriteReg(state, 0x42, 0x24); -+ WriteReg(state, 0xE1, 0x27); -+ WriteReg(state, 0x92, 0x7F); -+ WriteReg(state, 0x93, 0x91); -+ WriteReg(state, 0x95, 0x00); -+ WriteReg(state, 0x2B, 0x33); -+ WriteReg(state, 0x2A, 0x2A); -+ WriteReg(state, 0x2E, 0x80); -+ WriteReg(state, 0x25, 0x25); -+ WriteReg(state, 0x2D, 0xFF); -+ WriteReg(state, 0x26, 0xFF); -+ WriteReg(state, 0x27, 0x00); -+ WriteReg(state, 0x24, 0x25); -+ WriteReg(state, 0xA4, 0xFF); -+ WriteReg(state, 0xA3, 0x10); -+ } -+ WriteReg(state, 0xF6, 0x4E); -+ WriteReg(state, 0xF7, 0x20); -+ WriteReg(state, 0x89, 0x02); -+ WriteReg(state, 0x14, 0x08); -+ WriteReg(state, 0x6F, 0x0D); -+ WriteReg(state, 0x10, 0xFF); -+ WriteReg(state, 0x11, 0x00); -+ WriteReg(state, 0x12, 0x30); -+ WriteReg(state, 0x13, 0x23); -+ WriteReg(state, 0x60, 0x00); -+ WriteReg(state, 0x69, 0x00); -+ WriteReg(state, 0x6A, 0x03); -+ WriteReg(state, 0xE0, 0x75); -+ WriteReg(state, 0x8D, 0x29); -+ WriteReg(state, 0x4E, 0xD8); -+ WriteReg(state, 0x88, 0x80); -+ WriteReg(state, 0x52, 0x79); -+ WriteReg(state, 0x53, 0x03); -+ WriteReg(state, 0x59, 0x30); -+ WriteReg(state, 0x5E, 0x02); -+ WriteReg(state, 0x5F, 0x0F); -+ WriteReg(state, 0x71, 0x03); -+ WriteReg(state, 0x72, 0x12); -+ WriteReg(state, 0x73, 0x12); -+ -+ return 0; -+} -+ -+static int M88DC2000AutoTSClock_P(struct m88dc2800_state *state, u32 sym, -+ u16 qam) -+{ -+ u32 dataRate; -+ u8 clk_div, value; -+ printk(KERN_INFO -+ "m88dc2800: M88DC2000AutoTSClock_P, symrate=%d qam=%d\n", -+ sym, qam); -+ switch (qam) { -+ case 16: -+ dataRate = 4; -+ break; -+ case 32: -+ dataRate = 5; -+ break; -+ case 128: -+ dataRate = 7; -+ break; -+ case 256: -+ dataRate = 8; -+ break; -+ case 64: -+ default: -+ dataRate = 6; -+ break; -+ } -+ dataRate *= sym * 105; -+ dataRate /= 800; -+ if (dataRate <= 4115) -+ clk_div = 0x05; -+ else if (dataRate <= 4800) -+ clk_div = 0x04; -+ else if (dataRate <= 5760) -+ clk_div = 0x03; -+ else if (dataRate <= 7200) -+ clk_div = 0x02; -+ else if (dataRate <= 9600) -+ clk_div = 0x01; -+ else -+ clk_div = 0x00; -+ value = ReadReg(state, 0xC2); -+ value &= 0xc0; -+ value |= clk_div; -+ WriteReg(state, 0xC2, value); -+ return 0; -+} -+ -+static int M88DC2000AutoTSClock_C(struct m88dc2800_state *state, u32 sym, -+ u16 qam) -+{ -+ u32 dataRate; -+ u8 clk_div, value; -+ printk(KERN_INFO -+ "m88dc2800: M88DC2000AutoTSClock_C, symrate=%d qam=%d\n", -+ sym, qam); -+ switch (qam) { -+ case 16: -+ dataRate = 4; -+ break; -+ case 32: -+ dataRate = 5; -+ break; -+ case 128: -+ dataRate = 7; -+ break; -+ case 256: -+ dataRate = 8; -+ break; -+ case 64: -+ default: -+ dataRate = 6; -+ break; -+ } -+ dataRate *= sym * 105; -+ dataRate /= 800; -+ if (dataRate <= 4115) -+ clk_div = 0x3F; -+ else if (dataRate <= 4800) -+ clk_div = 0x36; -+ else if (dataRate <= 5760) -+ clk_div = 0x2D; -+ else if (dataRate <= 7200) -+ clk_div = 0x24; -+ else if (dataRate <= 9600) -+ clk_div = 0x1B; -+ else -+ clk_div = 0x12; -+ value = ReadReg(state, 0xC2); -+ value &= 0xc0; -+ value |= clk_div; -+ WriteReg(state, 0xC2, value); -+ return 0; -+} -+ -+static int M88DC2000SetTxMode(struct m88dc2800_state *state, u8 inverted, -+ u8 j83) -+{ -+ u8 value = 0; -+ if (inverted) -+ value |= 0x08; /* spectrum inverted */ -+ if (j83) -+ value |= 0x01; /* J83C */ -+ WriteReg(state, 0x83, value); -+ return 0; -+} -+ -+static int M88DC2000SoftReset(struct m88dc2800_state *state) -+{ -+ WriteReg(state, 0x80, 0x01); -+ WriteReg(state, 0x82, 0x00); -+ msleep(1); -+ WriteReg(state, 0x80, 0x00); -+ return 0; -+} -+ -+static int M88DC2000SetSym(struct m88dc2800_state *state, u32 sym, u32 xtal) -+{ -+ u8 value; -+ u8 reg6FH, reg12H; -+ u64 fValue; -+ u32 dwValue; -+ -+ printk(KERN_INFO "%s, sym=%d, xtal=%d\n", __func__, sym, xtal); -+ fValue = 4294967296 * (sym + 10); -+ do_div(fValue, xtal); -+ -+ /* fValue = 4294967296 * (sym + 10) / xtal; */ -+ dwValue = (u32) fValue; -+ printk(KERN_INFO "%s, fvalue1=%x\n", __func__, dwValue); -+ WriteReg(state, 0x58, (u8) ((dwValue >> 24) & 0xff)); -+ WriteReg(state, 0x57, (u8) ((dwValue >> 16) & 0xff)); -+ WriteReg(state, 0x56, (u8) ((dwValue >> 8) & 0xff)); -+ WriteReg(state, 0x55, (u8) ((dwValue >> 0) & 0xff)); -+ -+ /* fValue = 2048 * xtal / sym; */ -+ fValue = 2048 * xtal; -+ do_div(fValue, sym); -+ dwValue = (u32) fValue; -+ printk(KERN_INFO "%s, fvalue2=%x\n", __func__, dwValue); -+ WriteReg(state, 0x5D, (u8) ((dwValue >> 8) & 0xff)); -+ WriteReg(state, 0x5C, (u8) ((dwValue >> 0) & 0xff)); -+ value = ReadReg(state, 0x5A); -+ if (((dwValue >> 16) & 0x0001) == 0) -+ value &= 0x7F; -+ else -+ value |= 0x80; -+ WriteReg(state, 0x5A, value); -+ value = ReadReg(state, 0x89); -+ if (sym <= 1800) -+ value |= 0x01; -+ else -+ value &= 0xFE; -+ WriteReg(state, 0x89, value); -+ if (sym >= 6700) { -+ reg6FH = 0x0D; -+ reg12H = 0x30; -+ } else if (sym >= 4000) { -+ fValue = 22 * 4096 / sym; -+ reg6FH = (u8) fValue; -+ reg12H = 0x30; -+ } else if (sym >= 2000) { -+ fValue = 14 * 4096 / sym; -+ reg6FH = (u8) fValue; -+ reg12H = 0x20; -+ } else { -+ fValue = 7 * 4096 / sym; -+ reg6FH = (u8) fValue; -+ reg12H = 0x10; -+ } -+ WriteReg(state, 0x6F, reg6FH); -+ WriteReg(state, 0x12, reg12H); -+ if (((ReadReg(state, 0xE3) & 0x80) == 0x80) -+ && ((ReadReg(state, 0xE4) & 0x80) == 0x80)) { -+ if (sym < 3000) { -+ WriteReg(state, 0x6C, 0x16); -+ WriteReg(state, 0x6D, 0x10); -+ WriteReg(state, 0x6E, 0x18); -+ } else { -+ WriteReg(state, 0x6C, 0x14); -+ WriteReg(state, 0x6D, 0x0E); -+ WriteReg(state, 0x6E, 0x36); -+ } -+ } else { -+ WriteReg(state, 0x6C, 0x16); -+ WriteReg(state, 0x6D, 0x10); -+ WriteReg(state, 0x6E, 0x18); -+ } -+ return 0; -+} -+ -+static int M88DC2000SetQAM(struct m88dc2800_state *state, u16 qam) -+{ -+ u8 reg00H, reg4AH, regC2H, reg44H, reg4CH, reg4DH, reg74H, value; -+ u8 reg8BH, reg8EH; -+ printk(KERN_INFO "%s, qam=%d\n", __func__, qam); -+ regC2H = ReadReg(state, 0xC2); -+ regC2H &= 0xF8; -+ switch (qam) { -+ case 16: /* 16 QAM */ -+ reg00H = 0x08; -+ reg4AH = 0x0F; -+ regC2H |= 0x02; -+ reg44H = 0xAA; -+ reg4CH = 0x0C; -+ reg4DH = 0xF7; -+ reg74H = 0x0E; -+ if (((ReadReg(state, 0xE3) & 0x80) == 0x80) -+ && ((ReadReg(state, 0xE4) & 0x80) == 0x80)) { -+ reg8BH = 0x5A; -+ reg8EH = 0xBD; -+ } else { -+ reg8BH = 0x5B; -+ reg8EH = 0x9D; -+ } -+ WriteReg(state, 0x6E, 0x18); -+ break; -+ case 32: /* 32 QAM */ -+ reg00H = 0x18; -+ reg4AH = 0xFB; -+ regC2H |= 0x02; -+ reg44H = 0xAA; -+ reg4CH = 0x0C; -+ reg4DH = 0xF7; -+ reg74H = 0x0E; -+ if (((ReadReg(state, 0xE3) & 0x80) == 0x80) -+ && ((ReadReg(state, 0xE4) & 0x80) == 0x80)) { -+ reg8BH = 0x5A; -+ reg8EH = 0xBD; -+ } else { -+ reg8BH = 0x5B; -+ reg8EH = 0x9D; -+ } -+ WriteReg(state, 0x6E, 0x18); -+ break; -+ case 64: /* 64 QAM */ -+ reg00H = 0x48; -+ reg4AH = 0xCD; -+ regC2H |= 0x02; -+ reg44H = 0xAA; -+ reg4CH = 0x0C; -+ reg4DH = 0xF7; -+ reg74H = 0x0E; -+ if (((ReadReg(state, 0xE3) & 0x80) == 0x80) -+ && ((ReadReg(state, 0xE4) & 0x80) == 0x80)) { -+ reg8BH = 0x5A; -+ reg8EH = 0xBD; -+ } else { -+ reg8BH = 0x5B; -+ reg8EH = 0x9D; -+ } -+ break; -+ case 128: /* 128 QAM */ -+ reg00H = 0x28; -+ reg4AH = 0xFF; -+ regC2H |= 0x02; -+ reg44H = 0xA9; -+ reg4CH = 0x08; -+ reg4DH = 0xF5; -+ reg74H = 0x0E; -+ reg8BH = 0x5B; -+ reg8EH = 0x9D; -+ break; -+ case 256: /* 256 QAM */ -+ reg00H = 0x38; -+ reg4AH = 0xCD; -+ if (((ReadReg(state, 0xE3) & 0x80) == 0x80) -+ && ((ReadReg(state, 0xE4) & 0x80) == 0x80)) { -+ regC2H |= 0x02; -+ } else { -+ regC2H |= 0x01; -+ } -+ reg44H = 0xA9; -+ reg4CH = 0x08; -+ reg4DH = 0xF5; -+ reg74H = 0x0E; -+ reg8BH = 0x5B; -+ reg8EH = 0x9D; -+ break; -+ default: /* 64 QAM */ -+ reg00H = 0x48; -+ reg4AH = 0xCD; -+ regC2H |= 0x02; -+ reg44H = 0xAA; -+ reg4CH = 0x0C; -+ reg4DH = 0xF7; -+ reg74H = 0x0E; -+ if (((ReadReg(state, 0xE3) & 0x80) == 0x80) -+ && ((ReadReg(state, 0xE4) & 0x80) == 0x80)) { -+ reg8BH = 0x5A; -+ reg8EH = 0xBD; -+ } else { -+ reg8BH = 0x5B; -+ reg8EH = 0x9D; -+ } -+ break; -+ } -+ WriteReg(state, 0x00, reg00H); -+ value = ReadReg(state, 0x88); -+ value |= 0x08; -+ WriteReg(state, 0x88, value); -+ WriteReg(state, 0x4B, 0xFF); -+ WriteReg(state, 0x4A, reg4AH); -+ value &= 0xF7; -+ WriteReg(state, 0x88, value); -+ WriteReg(state, 0xC2, regC2H); -+ WriteReg(state, 0x44, reg44H); -+ WriteReg(state, 0x4C, reg4CH); -+ WriteReg(state, 0x4D, reg4DH); -+ WriteReg(state, 0x74, reg74H); -+ WriteReg(state, 0x8B, reg8BH); -+ WriteReg(state, 0x8E, reg8EH); -+ return 0; -+} -+ -+static int M88DC2000WriteTuner_TC2800(struct m88dc2800_state *state, -+ u32 freq_KHz) -+{ -+ printk(KERN_INFO "%s, freq=%d KHz\n", __func__, freq_KHz); -+ return mt_fe_tn_set_freq_tc2800(state, freq_KHz); -+} -+ -+static int m88dc2800_init(struct dvb_frontend *fe) -+{ -+ dprintk("%s()\n", __func__); -+ return 0; -+} -+ -+static int m88dc2800_set_parameters(struct dvb_frontend *fe) -+{ -+ struct dtv_frontend_properties *c = &fe->dtv_property_cache; -+ u8 is_annex_c, is_update; -+ u16 temp_qam; -+ s32 waiting_time; -+ struct m88dc2800_state *state = fe->demodulator_priv; -+ -+ is_annex_c = c->delivery_system == SYS_DVBC_ANNEX_C ? 1 : 0; -+ -+ switch (c->modulation) { -+ case QAM_16: -+ temp_qam = 16; -+ break; -+ case QAM_32: -+ temp_qam = 32; -+ break; -+ case QAM_128: -+ temp_qam = 128; -+ break; -+ case QAM_256: -+ temp_qam = 256; -+ break; -+ default: /* QAM_64 */ -+ temp_qam = 64; -+ break; -+ } -+ -+ state->inverted = c->inversion == INVERSION_ON ? 1 : 0; -+ -+ printk(KERN_INFO -+ "m88dc2800: state, freq=%d qam=%d sym=%d inverted=%d xtal=%d\n", -+ state->freq, state->qam, state->sym, state->inverted, -+ state->xtal); -+ printk(KERN_INFO -+ "m88dc2800: set frequency to %d qam=%d symrate=%d annex-c=%d\n", -+ c->frequency, temp_qam, c->symbol_rate, is_annex_c); -+ -+ is_update = 0; -+ WriteReg(state, 0x80, 0x01); -+ if (c->frequency != state->freq) { -+ M88DC2000WriteTuner_TC2800(state, c->frequency / 1000); -+ state->freq = c->frequency; -+ } -+ if (c->symbol_rate != state->sym) { -+ M88DC2000SetSym(state, c->symbol_rate / 1000, state->xtal); -+ state->sym = c->symbol_rate; -+ is_update = 1; -+ } -+ if (temp_qam != state->qam) { -+ M88DC2000SetQAM(state, temp_qam); -+ state->qam = temp_qam; -+ is_update = 1; -+ } -+ -+ if (is_update != 0) { -+ if (state->config->ts_mode == 3) -+ M88DC2000AutoTSClock_C(state, state->sym / 1000, -+ temp_qam); -+ else -+ M88DC2000AutoTSClock_P(state, state->sym / 1000, -+ temp_qam); -+ } -+ -+ M88DC2000SetTxMode(state, state->inverted, is_annex_c); -+ M88DC2000SoftReset(state); -+ if (((ReadReg(state, 0xE3) & 0x80) == 0x80) -+ && ((ReadReg(state, 0xE4) & 0x80) == 0x80)) -+ waiting_time = 800; -+ else -+ waiting_time = 500; -+ while (waiting_time > 0) { -+ msleep(50); -+ waiting_time -= 50; -+ if (M88DC2000GetLock(state)) -+ return 0; -+ } -+ -+ state->inverted = (state->inverted != 0) ? 0 : 1; -+ M88DC2000SetTxMode(state, state->inverted, is_annex_c); -+ M88DC2000SoftReset(state); -+ if (((ReadReg(state, 0xE3) & 0x80) == 0x80) && -+ ((ReadReg(state, 0xE4) & 0x80) == 0x80)) -+ waiting_time = 800; -+ else -+ waiting_time = 500; -+ while (waiting_time > 0) { -+ msleep(50); -+ waiting_time -= 50; -+ if (M88DC2000GetLock(state)) -+ return 0; -+ } -+ return 0; -+} -+ -+static int m88dc2800_read_status(struct dvb_frontend *fe, -+ fe_status_t * status) -+{ -+ struct m88dc2800_state *state = fe->demodulator_priv; -+ *status = 0; -+ -+ if (M88DC2000GetLock(state)) { -+ *status = FE_HAS_SIGNAL | FE_HAS_CARRIER -+ |FE_HAS_SYNC | FE_HAS_VITERBI | FE_HAS_LOCK; -+ } -+ return 0; -+} -+ -+static int m88dc2800_read_ber(struct dvb_frontend *fe, u32 * ber) -+{ -+ struct m88dc2800_state *state = fe->demodulator_priv; -+ u16 tmp; -+ -+ if (M88DC2000GetLock(state) == 0) { -+ state->ber = 0; -+ } else if ((ReadReg(state, 0xA0) & 0x80) != 0x80) { -+ tmp = ReadReg(state, 0xA2) << 8; -+ tmp += ReadReg(state, 0xA1); -+ state->ber = tmp; -+ WriteReg(state, 0xA0, 0x05); -+ WriteReg(state, 0xA0, 0x85); -+ } -+ *ber = state->ber; -+ return 0; -+} -+ -+static int m88dc2800_read_signal_strength(struct dvb_frontend *fe, -+ u16 * strength) -+{ -+ struct m88dc2800_state *state = fe->demodulator_priv; -+ s16 tuner_strength; -+ -+ tuner_strength = mt_fe_tn_get_signal_strength_tc2800(state); -+ *strength = tuner_strength < -107 ? 0 : tuner_strength + 107; -+ -+ return 0; -+} -+ -+static int m88dc2800_read_snr(struct dvb_frontend *fe, u16 * snr) -+{ -+ static const u32 mes_log[] = { -+ 0, 3010, 4771, 6021, 6990, 7781, 8451, 9031, 9542, 10000, -+ 10414, 10792, 11139, 11461, 11761, 12041, 12304, 12553, 12788, -+ 13010, 13222, 13424, 13617, 13802, 13979, 14150, 14314, 14472, -+ 14624, 14771, 14914, 15052, 15185, 15315, 15441, 15563, 15682, -+ 15798, 15911, 16021, 16128, 16232, 16335, 16435, 16532, 16628, -+ 16721, 16812, 16902, 16990, 17076, 17160, 17243, 17324, 17404, -+ 17482, 17559, 17634, 17709, 17782, 17853, 17924, 17993, 18062, -+ 18129, 18195, 18261, 18325, 18388, 18451, 18513, 18573, 18633, -+ 18692, 18751, 18808, 18865, 18921, 18976, 19031 -+ }; -+ struct m88dc2800_state *state = fe->demodulator_priv; -+ u8 i; -+ u32 _snr, mse; -+ -+ if ((ReadReg(state, 0x91) & 0x23) != 0x03) { -+ *snr = 0; -+ return 0; -+ } -+ mse = 0; -+ for (i = 0; i < 30; i++) { -+ mse += (ReadReg(state, 0x08) << 8) + ReadReg(state, 0x07); -+ } -+ mse /= 30; -+ if (mse > 80) -+ mse = 80; -+ switch (state->qam) { -+ case 16: -+ _snr = 34080; -+ break; /* 16QAM */ -+ case 32: -+ _snr = 37600; -+ break; /* 32QAM */ -+ case 64: -+ _snr = 40310; -+ break; /* 64QAM */ -+ case 128: -+ _snr = 43720; -+ break; /* 128QAM */ -+ case 256: -+ _snr = 46390; -+ break; /* 256QAM */ -+ default: -+ _snr = 40310; -+ break; -+ } -+ _snr -= mes_log[mse - 1]; /* C - 10*log10(MSE) */ -+ _snr /= 1000; -+ if (_snr > 0xff) -+ _snr = 0xff; -+ *snr = _snr; -+ return 0; -+} -+ -+static int m88dc2800_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks) -+{ -+ struct m88dc2800_state *state = fe->demodulator_priv; -+ u8 u8Value; -+ -+ u8Value = ReadReg(state, 0xdf); -+ u8Value |= 0x02; /* Hold */ -+ WriteReg(state, 0xdf, u8Value); -+ -+ *ucblocks = ReadReg(state, 0xd5); -+ *ucblocks = (*ucblocks << 8) | ReadReg(state, 0xd4); -+ -+ u8Value &= 0xfe; /* Clear */ -+ WriteReg(state, 0xdf, u8Value); -+ u8Value &= 0xfc; /* Update */ -+ u8Value |= 0x01; -+ WriteReg(state, 0xdf, u8Value); -+ -+ return 0; -+} -+ -+static int m88dc2800_sleep(struct dvb_frontend *fe) -+{ -+ struct m88dc2800_state *state = fe->demodulator_priv; -+ -+ mt_fe_tn_sleep_tc2800(state); -+ state->freq = 0; -+ -+ return 0; -+} -+ -+static void m88dc2800_release(struct dvb_frontend *fe) -+{ -+ struct m88dc2800_state *state = fe->demodulator_priv; -+ kfree(state); -+} -+ -+static struct dvb_frontend_ops m88dc2800_ops; -+ -+struct dvb_frontend *m88dc2800_attach(const struct m88dc2800_config -+ *config, struct i2c_adapter *i2c) -+{ -+ struct m88dc2800_state *state = NULL; -+ -+ /* allocate memory for the internal state */ -+ state = kzalloc(sizeof(struct m88dc2800_state), GFP_KERNEL); -+ if (state == NULL) -+ goto error; -+ -+ /* setup the state */ -+ state->config = config; -+ state->i2c = i2c; -+ state->xtal = 28800; -+ -+ WriteReg(state, 0x80, 0x01); -+ M88DC2000RegInitial_TC2800(state); -+ M88DC2000SetTsType(state, state->config->ts_mode); -+ mt_fe_tn_init_tc2800(state); -+ -+ /* create dvb_frontend */ -+ memcpy(&state->frontend.ops, &m88dc2800_ops, -+ sizeof(struct dvb_frontend_ops)); -+ state->frontend.demodulator_priv = state; -+ return &state->frontend; -+ -+ error: -+ kfree(state); -+ return NULL; -+} -+ -+EXPORT_SYMBOL(m88dc2800_attach); -+ -+static struct dvb_frontend_ops m88dc2800_ops = { -+ .delsys = {SYS_DVBC_ANNEX_A, SYS_DVBC_ANNEX_C}, -+ .info = { -+ .name = "Montage M88DC2800 DVB-C", -+ .frequency_stepsize = 62500, -+ .frequency_min = 48000000, -+ .frequency_max = 870000000, -+ .symbol_rate_min = 870000, -+ .symbol_rate_max = 9000000, -+ .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | -+ FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO -+ }, -+ .release = m88dc2800_release, -+ .init = m88dc2800_init, -+ .sleep = m88dc2800_sleep, -+ .set_frontend = m88dc2800_set_parameters, -+ .read_status = m88dc2800_read_status, -+ .read_ber = m88dc2800_read_ber, -+ .read_signal_strength = m88dc2800_read_signal_strength, -+ .read_snr = m88dc2800_read_snr, -+ .read_ucblocks = m88dc2800_read_ucblocks, -+}; -+ -+MODULE_DESCRIPTION("Montage DVB-C demodulator driver"); -+MODULE_AUTHOR("Max Nibble "); -+MODULE_LICENSE("GPL"); -+MODULE_VERSION("1.00"); -diff -urN a/drivers/media/dvb-frontends/m88dc2800.h b/drivers/media/dvb-frontends/m88dc2800.h ---- a/drivers/media/dvb-frontends/m88dc2800.h 1970-01-01 08:00:00.000000000 +0800 -+++ b/drivers/media/dvb-frontends/m88dc2800.h 2013-01-26 14:57:32.000000000 +0800 -@@ -0,0 +1,43 @@ -+/* -+ M88DC2800/M88TC2800 - DVB-C demodulator and tuner from Montage -+ -+ Copyright (C) 2012 Max Nibble -+ Copyright (C) 2011 Montage Technology - www.montage-tech.com -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 2 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+*/ -+ -+#ifndef M88DC2800_H -+#define M88DC2800_H -+ -+#include -+ -+struct m88dc2800_config { -+ u8 demod_address; -+ u8 ts_mode; -+}; -+ -+#if defined(CONFIG_DVB_M88DC2800) || (defined(CONFIG_DVB_M88DC2800_MODULE) && defined(MODULE)) -+extern struct dvb_frontend* m88dc2800_attach(const struct m88dc2800_config* config, -+ struct i2c_adapter* i2c); -+#else -+static inline struct dvb_frontend* m88dc2800_attach(const struct m88dc2800_config* config, -+ struct i2c_adapter* i2c) -+{ -+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); -+ return NULL; -+} -+#endif /* CONFIG_DVB_M88DC2800 */ -+#endif /* M88DC2800_H */ -diff -urN a/drivers/media/dvb-frontends/m88ds3103.c b/drivers/media/dvb-frontends/m88ds3103.c ---- a/drivers/media/dvb-frontends/m88ds3103.c 1970-01-01 08:00:00.000000000 +0800 -+++ b/drivers/media/dvb-frontends/m88ds3103.c 2013-01-30 12:33:47.000000000 +0800 -@@ -0,0 +1,1710 @@ -+/* -+ Montage Technology M88DS3103/M88TS2022 - DVBS/S2 Satellite demod/tuner driver -+ -+ Copyright (C) 2011 Max nibble -+ Copyright (C) 2010 Montage Technology -+ Copyright (C) 2009 Konstantin Dimitrov. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 2 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "dvb_frontend.h" -+#include "m88ds3103.h" -+#include "m88ds3103_priv.h" -+ -+static int debug; -+module_param(debug, int, 0644); -+MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); -+ -+#define dprintk(args...) \ -+ do { \ -+ if (debug) \ -+ printk(KERN_INFO "m88ds3103: " args); \ -+ } while (0) -+ -+/*demod register operations.*/ -+static int m88ds3103_writereg(struct m88ds3103_state *state, int reg, int data) -+{ -+ u8 buf[] = { reg, data }; -+ struct i2c_msg msg = { .addr = state->config->demod_address, -+ .flags = 0, .buf = buf, .len = 2 }; -+ int err; -+ -+ if (debug > 1) -+ printk("m88ds3103: %s: write reg 0x%02x, value 0x%02x\n", -+ __func__, reg, data); -+ -+ err = i2c_transfer(state->i2c, &msg, 1); -+ if (err != 1) { -+ printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x," -+ " value == 0x%02x)\n", __func__, err, reg, data); -+ return -EREMOTEIO; -+ } -+ return 0; -+} -+ -+static int m88ds3103_readreg(struct m88ds3103_state *state, u8 reg) -+{ -+ int ret; -+ u8 b0[] = { reg }; -+ u8 b1[] = { 0 }; -+ struct i2c_msg msg[] = { -+ { .addr = state->config->demod_address, .flags = 0, -+ .buf = b0, .len = 1 }, -+ { .addr = state->config->demod_address, .flags = I2C_M_RD, -+ .buf = b1, .len = 1 } -+ }; -+ ret = i2c_transfer(state->i2c, msg, 2); -+ -+ if (ret != 2) { -+ printk(KERN_ERR "%s: reg=0x%x (error=%d)\n", -+ __func__, reg, ret); -+ return ret; -+ } -+ -+ if (debug > 1) -+ printk(KERN_INFO "m88ds3103: read reg 0x%02x, value 0x%02x\n", -+ reg, b1[0]); -+ -+ return b1[0]; -+} -+ -+/*tuner register operations.*/ -+static int m88ds3103_tuner_writereg(struct m88ds3103_state *state, int reg, int data) -+{ -+ u8 buf[] = { reg, data }; -+ struct i2c_msg msg = { .addr = 0x60, -+ .flags = 0, .buf = buf, .len = 2 }; -+ int err; -+ -+ m88ds3103_writereg(state, 0x03, 0x11); -+ err = i2c_transfer(state->i2c, &msg, 1); -+ -+ if (err != 1) { -+ printk("%s: writereg error(err == %i, reg == 0x%02x," -+ " value == 0x%02x)\n", __func__, err, reg, data); -+ return -EREMOTEIO; -+ } -+ -+ return 0; -+} -+ -+static int m88ds3103_tuner_readreg(struct m88ds3103_state *state, u8 reg) -+{ -+ int ret; -+ u8 b0[] = { reg }; -+ u8 b1[] = { 0 }; -+ struct i2c_msg msg[] = { -+ { .addr = 0x60, .flags = 0, -+ .buf = b0, .len = 1 }, -+ { .addr = 0x60, .flags = I2C_M_RD, -+ .buf = b1, .len = 1 } -+ }; -+ -+ m88ds3103_writereg(state, 0x03, 0x11); -+ ret = i2c_transfer(state->i2c, msg, 2); -+ -+ if (ret != 2) { -+ printk(KERN_ERR "%s: reg=0x%x(error=%d)\n", __func__, reg, ret); -+ return ret; -+ } -+ -+ return b1[0]; -+} -+ -+/* Bulk demod I2C write, for firmware download. */ -+static int m88ds3103_writeregN(struct m88ds3103_state *state, int reg, -+ const u8 *data, u16 len) -+{ -+ int ret = -EREMOTEIO; -+ struct i2c_msg msg; -+ u8 *buf; -+ -+ buf = kmalloc(len + 1, GFP_KERNEL); -+ if (buf == NULL) { -+ printk("Unable to kmalloc\n"); -+ ret = -ENOMEM; -+ goto error; -+ } -+ -+ *(buf) = reg; -+ memcpy(buf + 1, data, len); -+ -+ msg.addr = state->config->demod_address; -+ msg.flags = 0; -+ msg.buf = buf; -+ msg.len = len + 1; -+ -+ if (debug > 1) -+ printk(KERN_INFO "m88ds3103: %s: write regN 0x%02x, len = %d\n", -+ __func__, reg, len); -+ -+ ret = i2c_transfer(state->i2c, &msg, 1); -+ if (ret != 1) { -+ printk(KERN_ERR "%s: writereg error(err == %i, reg == 0x%02x\n", -+ __func__, ret, reg); -+ ret = -EREMOTEIO; -+ } -+ -+error: -+ kfree(buf); -+ -+ return ret; -+} -+ -+static int m88ds3103_load_firmware(struct dvb_frontend *fe) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ const struct firmware *fw; -+ int i, ret = 0; -+ -+ dprintk("%s()\n", __func__); -+ -+ if (state->skip_fw_load) -+ return 0; -+ /* Load firmware */ -+ /* request the firmware, this will block until someone uploads it */ -+ if(state->demod_id == DS3000_ID){ -+ printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__, -+ DS3000_DEFAULT_FIRMWARE); -+ ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE, -+ state->i2c->dev.parent); -+ }else if(state->demod_id == DS3103_ID){ -+ printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n", __func__, -+ DS3103_DEFAULT_FIRMWARE); -+ ret = request_firmware(&fw, DS3103_DEFAULT_FIRMWARE, -+ state->i2c->dev.parent); -+ } -+ -+ printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n", __func__); -+ if (ret) { -+ printk(KERN_ERR "%s: No firmware uploaded (timeout or file not " -+ "found?)\n", __func__); -+ return ret; -+ } -+ -+ /* Make sure we don't recurse back through here during loading */ -+ state->skip_fw_load = 1; -+ -+ dprintk("Firmware is %zu bytes (%02x %02x .. %02x %02x)\n", -+ fw->size, -+ fw->data[0], -+ fw->data[1], -+ fw->data[fw->size - 2], -+ fw->data[fw->size - 1]); -+ -+ /* stop internal mcu. */ -+ m88ds3103_writereg(state, 0xb2, 0x01); -+ /* split firmware to download.*/ -+ for(i = 0; i < FW_DOWN_LOOP; i++){ -+ ret = m88ds3103_writeregN(state, 0xb0, &(fw->data[FW_DOWN_SIZE*i]), FW_DOWN_SIZE); -+ if(ret != 1) break; -+ } -+ /* start internal mcu. */ -+ if(ret == 1) -+ m88ds3103_writereg(state, 0xb2, 0x00); -+ -+ release_firmware(fw); -+ -+ dprintk("%s: Firmware upload %s\n", __func__, -+ ret == 1 ? "complete" : "failed"); -+ -+ if(ret == 1) ret = 0; -+ -+ /* Ensure firmware is always loaded if required */ -+ state->skip_fw_load = 0; -+ -+ return ret; -+} -+ -+ -+static int m88ds3103_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ u8 data; -+ -+ dprintk("%s(%d)\n", __func__, voltage); -+ -+ dprintk("m88ds3103:pin_ctrl = (%02x)\n", state->config->pin_ctrl); -+ -+ if(state->config->set_voltage) -+ state->config->set_voltage(fe, voltage); -+ -+ data = m88ds3103_readreg(state, 0xa2); -+ -+ if(state->config->pin_ctrl & 0x80){ /*If control pin is assigned.*/ -+ data &= ~0x03; /* bit0 V/H, bit1 off/on */ -+ if(state->config->pin_ctrl & 0x02) -+ data |= 0x02; -+ -+ switch (voltage) { -+ case SEC_VOLTAGE_18: -+ if((state->config->pin_ctrl & 0x01) == 0) -+ data |= 0x01; -+ break; -+ case SEC_VOLTAGE_13: -+ if(state->config->pin_ctrl & 0x01) -+ data |= 0x01; -+ break; -+ case SEC_VOLTAGE_OFF: -+ if(state->config->pin_ctrl & 0x02) -+ data &= ~0x02; -+ else -+ data |= 0x02; -+ break; -+ } -+ } -+ -+ m88ds3103_writereg(state, 0xa2, data); -+ -+ return 0; -+} -+ -+static int m88ds3103_read_status(struct dvb_frontend *fe, fe_status_t* status) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ int lock = 0; -+ -+ *status = 0; -+ -+ switch (state->delivery_system){ -+ case SYS_DVBS: -+ lock = m88ds3103_readreg(state, 0xd1); -+ dprintk("%s: SYS_DVBS status=%x.\n", __func__, lock); -+ -+ if ((lock & 0x07) == 0x07){ -+ /*if((m88ds3103_readreg(state, 0x0d) & 0x07) == 0x07)*/ -+ *status = FE_HAS_SIGNAL | FE_HAS_CARRIER -+ | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; -+ -+ } -+ break; -+ case SYS_DVBS2: -+ lock = m88ds3103_readreg(state, 0x0d); -+ dprintk("%s: SYS_DVBS2 status=%x.\n", __func__, lock); -+ -+ if ((lock & 0x8f) == 0x8f) -+ *status = FE_HAS_SIGNAL | FE_HAS_CARRIER -+ | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK; -+ -+ break; -+ default: -+ break; -+ } -+ -+ return 0; -+} -+ -+static int m88ds3103_read_ber(struct dvb_frontend *fe, u32* ber) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ u8 tmp1, tmp2, tmp3; -+ u32 ldpc_frame_cnt, pre_err_packags, code_rate_fac = 0; -+ -+ dprintk("%s()\n", __func__); -+ -+ switch (state->delivery_system) { -+ case SYS_DVBS: -+ m88ds3103_writereg(state, 0xf9, 0x04); -+ tmp3 = m88ds3103_readreg(state, 0xf8); -+ if ((tmp3&0x10) == 0){ -+ tmp1 = m88ds3103_readreg(state, 0xf7); -+ tmp2 = m88ds3103_readreg(state, 0xf6); -+ tmp3 |= 0x10; -+ m88ds3103_writereg(state, 0xf8, tmp3); -+ state->preBer = (tmp1<<8) | tmp2; -+ } -+ break; -+ case SYS_DVBS2: -+ tmp1 = m88ds3103_readreg(state, 0x7e) & 0x0f; -+ switch(tmp1){ -+ case 0: code_rate_fac = 16008 - 80; break; -+ case 1: code_rate_fac = 21408 - 80; break; -+ case 2: code_rate_fac = 25728 - 80; break; -+ case 3: code_rate_fac = 32208 - 80; break; -+ case 4: code_rate_fac = 38688 - 80; break; -+ case 5: code_rate_fac = 43040 - 80; break; -+ case 6: code_rate_fac = 48408 - 80; break; -+ case 7: code_rate_fac = 51648 - 80; break; -+ case 8: code_rate_fac = 53840 - 80; break; -+ case 9: code_rate_fac = 57472 - 80; break; -+ case 10: code_rate_fac = 58192 - 80; break; -+ } -+ -+ tmp1 = m88ds3103_readreg(state, 0xd7) & 0xff; -+ tmp2 = m88ds3103_readreg(state, 0xd6) & 0xff; -+ tmp3 = m88ds3103_readreg(state, 0xd5) & 0xff; -+ ldpc_frame_cnt = (tmp1 << 16) | (tmp2 << 8) | tmp3; -+ -+ tmp1 = m88ds3103_readreg(state, 0xf8) & 0xff; -+ tmp2 = m88ds3103_readreg(state, 0xf7) & 0xff; -+ pre_err_packags = tmp1<<8 | tmp2; -+ -+ if (ldpc_frame_cnt > 1000){ -+ m88ds3103_writereg(state, 0xd1, 0x01); -+ m88ds3103_writereg(state, 0xf9, 0x01); -+ m88ds3103_writereg(state, 0xf9, 0x00); -+ m88ds3103_writereg(state, 0xd1, 0x00); -+ state->preBer = pre_err_packags; -+ } -+ break; -+ default: -+ break; -+ } -+ *ber = state->preBer; -+ -+ return 0; -+} -+ -+static int m88ds3103_read_signal_strength(struct dvb_frontend *fe, -+ u16 *signal_strength) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ u16 gain; -+ u8 gain1, gain2, gain3 = 0; -+ -+ dprintk("%s()\n", __func__); -+ -+ gain1 = m88ds3103_tuner_readreg(state, 0x3d) & 0x1f; -+ dprintk("%s: gain1 = 0x%02x \n", __func__, gain1); -+ -+ if (gain1 > 15) gain1 = 15; -+ gain2 = m88ds3103_tuner_readreg(state, 0x21) & 0x1f; -+ dprintk("%s: gain2 = 0x%02x \n", __func__, gain2); -+ -+ if(state->tuner_id == TS2022_ID){ -+ gain3 = (m88ds3103_tuner_readreg(state, 0x66)>>3) & 0x07; -+ dprintk("%s: gain3 = 0x%02x \n", __func__, gain3); -+ -+ if (gain2 > 16) gain2 = 16; -+ if (gain2 < 2) gain2 = 2; -+ if (gain3 > 6) gain3 = 6; -+ }else{ -+ if (gain2 > 13) gain2 = 13; -+ gain3 = 0; -+ } -+ -+ gain = gain1*23 + gain2*35 + gain3*29; -+ *signal_strength = 60000 - gain*55; -+ -+ return 0; -+} -+ -+ -+static int m88ds3103_read_snr(struct dvb_frontend *fe, u16 *p_snr) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ u8 val, npow1, npow2, spow1, cnt; -+ u16 tmp, snr; -+ u32 npow, spow, snr_total; -+ static const u16 mes_log10[] ={ -+ 0, 3010, 4771, 6021, 6990, 7781, 8451, 9031, 9542, 10000, -+ 10414, 10792, 11139, 11461, 11761, 12041, 12304, 12553, 12788, 13010, -+ 13222, 13424, 13617, 13802, 13979, 14150, 14314, 14472, 14624, 14771, -+ 14914, 15052, 15185, 15315, 15441, 15563, 15682, 15798, 15911, 16021, -+ 16128, 16232, 16335, 16435, 16532, 16628, 16721, 16812, 16902, 16990, -+ 17076, 17160, 17243, 17324, 17404, 17482, 17559, 17634, 17709, 17782, -+ 17853, 17924, 17993, 18062, 18129, 18195, 18261, 18325, 18388, 18451, -+ 18513, 18573, 18633, 18692, 18751, 18808, 18865, 18921, 18976, 19031 -+ }; -+ static const u16 mes_loge[] ={ -+ 0, 6931, 10986, 13863, 16094, 17918, 19459, 20794, 21972, 23026, -+ 23979, 24849, 25649, 26391, 27081, 27726, 28332, 28904, 29444, 29957, -+ 30445, 30910, 31355, 31781, 32189, 32581, 32958, 33322, 33673, 34012, -+ 34340, 34657, -+ }; -+ -+ dprintk("%s()\n", __func__); -+ -+ snr = 0; -+ -+ switch (state->delivery_system){ -+ case SYS_DVBS: -+ cnt = 10; snr_total = 0; -+ while(cnt > 0){ -+ val = m88ds3103_readreg(state, 0xff); -+ snr_total += val; -+ cnt--; -+ } -+ tmp = (u16)(snr_total/80); -+ if(tmp > 0){ -+ if (tmp > 32) tmp = 32; -+ snr = (mes_loge[tmp - 1] * 100) / 45; -+ }else{ -+ snr = 0; -+ } -+ break; -+ case SYS_DVBS2: -+ cnt = 10; npow = 0; spow = 0; -+ while(cnt >0){ -+ npow1 = m88ds3103_readreg(state, 0x8c) & 0xff; -+ npow2 = m88ds3103_readreg(state, 0x8d) & 0xff; -+ npow += (((npow1 & 0x3f) + (u16)(npow2 << 6)) >> 2); -+ -+ spow1 = m88ds3103_readreg(state, 0x8e) & 0xff; -+ spow += ((spow1 * spow1) >> 1); -+ cnt--; -+ } -+ npow /= 10; spow /= 10; -+ if(spow == 0){ -+ snr = 0; -+ }else if(npow == 0){ -+ snr = 19; -+ }else{ -+ if(spow > npow){ -+ tmp = (u16)(spow / npow); -+ if (tmp > 80) tmp = 80; -+ snr = mes_log10[tmp - 1]*3; -+ }else{ -+ tmp = (u16)(npow / spow); -+ if (tmp > 80) tmp = 80; -+ snr = -(mes_log10[tmp - 1] / 1000); -+ } -+ } -+ break; -+ default: -+ break; -+ } -+ *p_snr = snr; -+ -+ return 0; -+} -+ -+ -+static int m88ds3103_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ u8 tmp1, tmp2, tmp3, data; -+ -+ dprintk("%s()\n", __func__); -+ -+ switch (state->delivery_system) { -+ case SYS_DVBS: -+ data = m88ds3103_readreg(state, 0xf8); -+ data |= 0x40; -+ m88ds3103_writereg(state, 0xf8, data); -+ tmp1 = m88ds3103_readreg(state, 0xf5); -+ tmp2 = m88ds3103_readreg(state, 0xf4); -+ *ucblocks = (tmp1 <<8) | tmp2; -+ data &= ~0x20; -+ m88ds3103_writereg(state, 0xf8, data); -+ data |= 0x20; -+ m88ds3103_writereg(state, 0xf8, data); -+ data &= ~0x40; -+ m88ds3103_writereg(state, 0xf8, data); -+ break; -+ case SYS_DVBS2: -+ tmp1 = m88ds3103_readreg(state, 0xda); -+ tmp2 = m88ds3103_readreg(state, 0xd9); -+ tmp3 = m88ds3103_readreg(state, 0xd8); -+ *ucblocks = (tmp1 <<16)|(tmp2 <<8)|tmp3; -+ data = m88ds3103_readreg(state, 0xd1); -+ data |= 0x01; -+ m88ds3103_writereg(state, 0xd1, data); -+ data &= ~0x01; -+ m88ds3103_writereg(state, 0xd1, data); -+ break; -+ default: -+ break; -+ } -+ return 0; -+} -+ -+static int m88ds3103_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ u8 data_a1, data_a2; -+ -+ dprintk("%s(%d)\n", __func__, tone); -+ if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) { -+ printk(KERN_ERR "%s: Invalid, tone=%d\n", __func__, tone); -+ return -EINVAL; -+ } -+ -+ data_a1 = m88ds3103_readreg(state, 0xa1); -+ data_a2 = m88ds3103_readreg(state, 0xa2); -+ if(state->demod_id == DS3103_ID) -+ data_a2 &= 0xdf; /* Normal mode */ -+ switch (tone) { -+ case SEC_TONE_ON: -+ dprintk("%s: SEC_TONE_ON\n", __func__); -+ data_a1 |= 0x04; -+ data_a1 &= ~0x03; -+ data_a1 &= ~0x40; -+ data_a2 &= ~0xc0; -+ break; -+ case SEC_TONE_OFF: -+ dprintk("%s: SEC_TONE_OFF\n", __func__); -+ data_a2 &= ~0xc0; -+ data_a2 |= 0x80; -+ break; -+ } -+ m88ds3103_writereg(state, 0xa2, data_a2); -+ m88ds3103_writereg(state, 0xa1, data_a1); -+ return 0; -+} -+ -+static int m88ds3103_send_diseqc_msg(struct dvb_frontend *fe, -+ struct dvb_diseqc_master_cmd *d) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ int i, ret = 0; -+ u8 tmp, time_out; -+ -+ /* Dump DiSEqC message */ -+ if (debug) { -+ printk(KERN_INFO "m88ds3103: %s(", __func__); -+ for (i = 0 ; i < d->msg_len ;) { -+ printk(KERN_INFO "0x%02x", d->msg[i]); -+ if (++i < d->msg_len) -+ printk(KERN_INFO ", "); -+ } -+ } -+ -+ tmp = m88ds3103_readreg(state, 0xa2); -+ tmp &= ~0xc0; -+ if(state->demod_id == DS3103_ID) -+ tmp &= ~0x20; -+ m88ds3103_writereg(state, 0xa2, tmp); -+ -+ for (i = 0; i < d->msg_len; i ++) -+ m88ds3103_writereg(state, (0xa3+i), d->msg[i]); -+ -+ tmp = m88ds3103_readreg(state, 0xa1); -+ tmp &= ~0x38; -+ tmp &= ~0x40; -+ tmp |= ((d->msg_len-1) << 3) | 0x07; -+ tmp &= ~0x80; -+ m88ds3103_writereg(state, 0xa1, tmp); -+ /* 1.5 * 9 * 8 = 108ms */ -+ time_out = 150; -+ while (time_out > 0){ -+ msleep(10); -+ time_out -= 10; -+ tmp = m88ds3103_readreg(state, 0xa1); -+ if ((tmp & 0x40) == 0) -+ break; -+ } -+ if (time_out == 0){ -+ tmp = m88ds3103_readreg(state, 0xa1); -+ tmp &= ~0x80; -+ tmp |= 0x40; -+ m88ds3103_writereg(state, 0xa1, tmp); -+ ret = 1; -+ } -+ tmp = m88ds3103_readreg(state, 0xa2); -+ tmp &= ~0xc0; -+ tmp |= 0x80; -+ m88ds3103_writereg(state, 0xa2, tmp); -+ return ret; -+} -+ -+ -+static int m88ds3103_diseqc_send_burst(struct dvb_frontend *fe, -+ fe_sec_mini_cmd_t burst) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ u8 val, time_out; -+ -+ dprintk("%s()\n", __func__); -+ -+ val = m88ds3103_readreg(state, 0xa2); -+ val &= ~0xc0; -+ if(state->demod_id == DS3103_ID) -+ val &= 0xdf; /* Normal mode */ -+ m88ds3103_writereg(state, 0xa2, val); -+ /* DiSEqC burst */ -+ if (burst == SEC_MINI_B) -+ m88ds3103_writereg(state, 0xa1, 0x01); -+ else -+ m88ds3103_writereg(state, 0xa1, 0x02); -+ -+ msleep(13); -+ -+ time_out = 5; -+ do{ -+ val = m88ds3103_readreg(state, 0xa1); -+ if ((val & 0x40) == 0) -+ break; -+ msleep(1); -+ time_out --; -+ } while (time_out > 0); -+ -+ val = m88ds3103_readreg(state, 0xa2); -+ val &= ~0xc0; -+ val |= 0x80; -+ m88ds3103_writereg(state, 0xa2, val); -+ -+ return 0; -+} -+ -+static void m88ds3103_release(struct dvb_frontend *fe) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ -+ dprintk("%s\n", __func__); -+ kfree(state); -+} -+ -+static int m88ds3103_check_id(struct m88ds3103_state *state) -+{ -+ int val_00, val_01; -+ -+ /*check demod id*/ -+ val_01 = m88ds3103_readreg(state, 0x01); -+ printk(KERN_INFO "DS3000 chip version: %x attached.\n", val_01); -+ -+ if(val_01 == 0xD0) -+ state->demod_id = DS3103_ID; -+ else if(val_01 == 0xC0) -+ state->demod_id = DS3000_ID; -+ else -+ state->demod_id = UNKNOW_ID; -+ -+ /*check tuner id*/ -+ val_00 = m88ds3103_tuner_readreg(state, 0x00); -+ printk(KERN_INFO "TS202x chip version[1]: %x attached.\n", val_00); -+ val_00 &= 0x03; -+ if(val_00 == 0) -+ { -+ m88ds3103_tuner_writereg(state, 0x00, 0x01); -+ msleep(3); -+ } -+ m88ds3103_tuner_writereg(state, 0x00, 0x03); -+ msleep(5); -+ -+ val_00 = m88ds3103_tuner_readreg(state, 0x00); -+ printk(KERN_INFO "TS202x chip version[2]: %x attached.\n", val_00); -+ val_00 &= 0xff; -+ if((val_00 == 0x01) || (val_00 == 0x41) || (val_00 == 0x81)) -+ state->tuner_id = TS2020_ID; -+ else if(((val_00 & 0xc0)== 0xc0) || (val_00 == 0x83)) -+ state->tuner_id = TS2022_ID; -+ else -+ state->tuner_id = UNKNOW_ID; -+ -+ return state->demod_id; -+} -+ -+static struct dvb_frontend_ops m88ds3103_ops; -+static int m88ds3103_initilaze(struct dvb_frontend *fe); -+ -+struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *config, -+ struct i2c_adapter *i2c) -+{ -+ struct m88ds3103_state *state = NULL; -+ -+ dprintk("%s\n", __func__); -+ -+ /* allocate memory for the internal state */ -+ state = kzalloc(sizeof(struct m88ds3103_state), GFP_KERNEL); -+ if (state == NULL) { -+ printk(KERN_ERR "Unable to kmalloc\n"); -+ goto error2; -+ } -+ -+ state->config = config; -+ state->i2c = i2c; -+ state->preBer = 0xffff; -+ state->delivery_system = SYS_DVBS; /*Default to DVB-S.*/ -+ -+ /* check demod id */ -+ if(m88ds3103_check_id(state) == UNKNOW_ID){ -+ printk(KERN_ERR "Unable to find Montage chip\n"); -+ goto error3; -+ } -+ -+ memcpy(&state->frontend.ops, &m88ds3103_ops, -+ sizeof(struct dvb_frontend_ops)); -+ state->frontend.demodulator_priv = state; -+ -+ m88ds3103_initilaze(&state->frontend); -+ -+ return &state->frontend; -+ -+error3: -+ kfree(state); -+error2: -+ return NULL; -+} -+EXPORT_SYMBOL(m88ds3103_attach); -+ -+static int m88ds3103_set_carrier_offset(struct dvb_frontend *fe, -+ s32 carrier_offset_khz) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ s32 tmp; -+ -+ tmp = carrier_offset_khz; -+ tmp *= 65536; -+ -+ tmp = (2*tmp + MT_FE_MCLK_KHZ) / (2*MT_FE_MCLK_KHZ); -+ -+ if (tmp < 0) -+ tmp += 65536; -+ -+ m88ds3103_writereg(state, 0x5f, tmp >> 8); -+ m88ds3103_writereg(state, 0x5e, tmp & 0xff); -+ -+ return 0; -+} -+ -+static int m88ds3103_set_symrate(struct dvb_frontend *fe) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ struct dtv_frontend_properties *c = &fe->dtv_property_cache; -+ u16 value; -+ -+ value = (((c->symbol_rate / 1000) << 15) + (MT_FE_MCLK_KHZ / 4)) / (MT_FE_MCLK_KHZ / 2); -+ m88ds3103_writereg(state, 0x61, value & 0x00ff); -+ m88ds3103_writereg(state, 0x62, (value & 0xff00) >> 8); -+ -+ return 0; -+} -+ -+static int m88ds3103_set_CCI(struct dvb_frontend *fe) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ u8 tmp; -+ -+ tmp = m88ds3103_readreg(state, 0x56); -+ tmp &= ~0x01; -+ m88ds3103_writereg(state, 0x56, tmp); -+ -+ tmp = m88ds3103_readreg(state, 0x76); -+ tmp &= ~0x80; -+ m88ds3103_writereg(state, 0x76, tmp); -+ -+ return 0; -+} -+ -+static int m88ds3103_init_reg(struct m88ds3103_state *state, const u8 *p_reg_tab, u32 size) -+{ -+ u32 i; -+ -+ for(i = 0; i < size; i+=2) -+ m88ds3103_writereg(state, p_reg_tab[i], p_reg_tab[i+1]); -+ -+ return 0; -+} -+ -+static int m88ds3103_get_locked_sym_rate(struct m88ds3103_state *state, u32 *sym_rate_KSs) -+{ -+ u16 tmp; -+ u32 sym_rate_tmp; -+ u8 val_0x6d, val_0x6e; -+ -+ val_0x6d = m88ds3103_readreg(state, 0x6d); -+ val_0x6e = m88ds3103_readreg(state, 0x6e); -+ -+ tmp = (u16)((val_0x6e<<8) | val_0x6d); -+ -+ sym_rate_tmp = (u32)(tmp * MT_FE_MCLK_KHZ); -+ sym_rate_tmp = (u32)(sym_rate_tmp / (1<<16)); -+ *sym_rate_KSs = sym_rate_tmp; -+ -+ return 0; -+} -+ -+static int m88ds3103_get_channel_info(struct m88ds3103_state *state, u8 *p_mode, u8 *p_coderate) -+{ -+ u8 tmp, val_0x7E; -+ -+ if(state->delivery_system == SYS_DVBS2){ -+ val_0x7E = m88ds3103_readreg(state, 0x7e); -+ tmp = (u8)((val_0x7E&0xC0) >> 6); -+ *p_mode = tmp; -+ tmp = (u8)(val_0x7E & 0x0f); -+ *p_coderate = tmp; -+ } else { -+ *p_mode = 0; -+ tmp = m88ds3103_readreg(state, 0xe6); -+ tmp = (u8)(tmp >> 5); -+ *p_coderate = tmp; -+ } -+ -+ return 0; -+} -+ -+static int m88ds3103_set_clock_ratio(struct m88ds3103_state *state) -+{ -+ u8 val, mod_fac, tmp1, tmp2; -+ u32 input_datarate, locked_sym_rate_KSs; -+ u32 MClk_KHz = 96000; -+ u8 mod_mode, code_rate, divid_ratio = 0; -+ -+ locked_sym_rate_KSs = 0; -+ m88ds3103_get_locked_sym_rate(state, &locked_sym_rate_KSs); -+ if(locked_sym_rate_KSs == 0) -+ return 0; -+ -+ m88ds3103_get_channel_info(state, &mod_mode, &code_rate); -+ -+ if (state->delivery_system == SYS_DVBS2) -+ { -+ switch(mod_mode) { -+ case 1: mod_fac = 3; break; -+ case 2: mod_fac = 4; break; -+ case 3: mod_fac = 5; break; -+ default: mod_fac = 2; break; -+ } -+ -+ switch(code_rate) { -+ case 0: input_datarate = locked_sym_rate_KSs*mod_fac/8/4; break; -+ case 1: input_datarate = locked_sym_rate_KSs*mod_fac/8/3; break; -+ case 2: input_datarate = locked_sym_rate_KSs*mod_fac*2/8/5; break; -+ case 3: input_datarate = locked_sym_rate_KSs*mod_fac/8/2; break; -+ case 4: input_datarate = locked_sym_rate_KSs*mod_fac*3/8/5; break; -+ case 5: input_datarate = locked_sym_rate_KSs*mod_fac*2/8/3; break; -+ case 6: input_datarate = locked_sym_rate_KSs*mod_fac*3/8/4; break; -+ case 7: input_datarate = locked_sym_rate_KSs*mod_fac*4/8/5; break; -+ case 8: input_datarate = locked_sym_rate_KSs*mod_fac*5/8/6; break; -+ case 9: input_datarate = locked_sym_rate_KSs*mod_fac*8/8/9; break; -+ case 10: input_datarate = locked_sym_rate_KSs*mod_fac*9/8/10; break; -+ default: input_datarate = locked_sym_rate_KSs*mod_fac*2/8/3; break; -+ } -+ -+ if(state->demod_id == DS3000_ID) -+ input_datarate = input_datarate * 115 / 100; -+ -+ if(input_datarate < 4800) {tmp1 = 15;tmp2 = 15;} //4.8MHz TS clock -+ else if(input_datarate < 4966) {tmp1 = 14;tmp2 = 15;} //4.966MHz TS clock -+ else if(input_datarate < 5143) {tmp1 = 14;tmp2 = 14;} //5.143MHz TS clock -+ else if(input_datarate < 5333) {tmp1 = 13;tmp2 = 14;} //5.333MHz TS clock -+ else if(input_datarate < 5538) {tmp1 = 13;tmp2 = 13;} //5.538MHz TS clock -+ else if(input_datarate < 5760) {tmp1 = 12;tmp2 = 13;} //5.76MHz TS clock allan 0809 -+ else if(input_datarate < 6000) {tmp1 = 12;tmp2 = 12;} //6MHz TS clock -+ else if(input_datarate < 6260) {tmp1 = 11;tmp2 = 12;} //6.26MHz TS clock -+ else if(input_datarate < 6545) {tmp1 = 11;tmp2 = 11;} //6.545MHz TS clock -+ else if(input_datarate < 6857) {tmp1 = 10;tmp2 = 11;} //6.857MHz TS clock -+ else if(input_datarate < 7200) {tmp1 = 10;tmp2 = 10;} //7.2MHz TS clock -+ else if(input_datarate < 7578) {tmp1 = 9;tmp2 = 10;} //7.578MHz TS clock -+ else if(input_datarate < 8000) {tmp1 = 9;tmp2 = 9;} //8MHz TS clock -+ else if(input_datarate < 8470) {tmp1 = 8;tmp2 = 9;} //8.47MHz TS clock -+ else if(input_datarate < 9000) {tmp1 = 8;tmp2 = 8;} //9MHz TS clock -+ else if(input_datarate < 9600) {tmp1 = 7;tmp2 = 8;} //9.6MHz TS clock -+ else if(input_datarate < 10285) {tmp1 = 7;tmp2 = 7;} //10.285MHz TS clock -+ else if(input_datarate < 12000) {tmp1 = 6;tmp2 = 6;} //12MHz TS clock -+ else if(input_datarate < 14400) {tmp1 = 5;tmp2 = 5;} //14.4MHz TS clock -+ else if(input_datarate < 18000) {tmp1 = 4;tmp2 = 4;} //18MHz TS clock -+ else {tmp1 = 3;tmp2 = 3;} //24MHz TS clock -+ -+ if(state->demod_id == DS3000_ID) { -+ val = (u8)((tmp1<<4) + tmp2); -+ m88ds3103_writereg(state, 0xfe, val); -+ } else { -+ tmp1 = m88ds3103_readreg(state, 0x22); -+ tmp2 = m88ds3103_readreg(state, 0x24); -+ -+ tmp1 >>= 6; -+ tmp1 &= 0x03; -+ tmp2 >>= 6; -+ tmp2 &= 0x03; -+ -+ if((tmp1 == 0x00) && (tmp2 == 0x01)) -+ MClk_KHz = 144000; -+ else if((tmp1 == 0x00) && (tmp2 == 0x03)) -+ MClk_KHz = 72000; -+ else if((tmp1 == 0x01) && (tmp2 == 0x01)) -+ MClk_KHz = 115200; -+ else if((tmp1 == 0x02) && (tmp2 == 0x01)) -+ MClk_KHz = 96000; -+ else if((tmp1 == 0x03) && (tmp2 == 0x00)) -+ MClk_KHz = 192000; -+ else -+ return 0; -+ -+ if(input_datarate < 5200) /*Max. 2011-12-23 11:55*/ -+ input_datarate = 5200; -+ -+ if(input_datarate != 0) -+ divid_ratio = (u8)(MClk_KHz / input_datarate); -+ else -+ divid_ratio = 0xFF; -+ -+ if(divid_ratio > 128) -+ divid_ratio = 128; -+ -+ if(divid_ratio < 2) -+ divid_ratio = 2; -+ -+ tmp1 = (u8)(divid_ratio / 2); -+ tmp2 = (u8)(divid_ratio / 2); -+ -+ if((divid_ratio % 2) != 0) -+ tmp2 += 1; -+ -+ tmp1 -= 1; -+ tmp2 -= 1; -+ -+ tmp1 &= 0x3f; -+ tmp2 &= 0x3f; -+ -+ val = m88ds3103_readreg(state, 0xfe); -+ val &= 0xF0; -+ val |= (tmp2 >> 2) & 0x0f; -+ m88ds3103_writereg(state, 0xfe, val); -+ -+ val = (u8)((tmp2 & 0x03) << 6); -+ val |= tmp1; -+ m88ds3103_writereg(state, 0xea, val); -+ } -+ } else { -+ mod_fac = 2; -+ -+ switch(code_rate) { -+ case 4: input_datarate = locked_sym_rate_KSs*mod_fac/2/8; break; -+ case 3: input_datarate = locked_sym_rate_KSs*mod_fac*2/3/8; break; -+ case 2: input_datarate = locked_sym_rate_KSs*mod_fac*3/4/8; break; -+ case 1: input_datarate = locked_sym_rate_KSs*mod_fac*5/6/8; break; -+ case 0: input_datarate = locked_sym_rate_KSs*mod_fac*7/8/8; break; -+ default: input_datarate = locked_sym_rate_KSs*mod_fac*3/4/8; break; -+ } -+ -+ if(state->demod_id == DS3000_ID) -+ input_datarate = input_datarate * 115 / 100; -+ -+ if(input_datarate < 6857) {tmp1 = 7;tmp2 = 7;} //6.857MHz TS clock -+ else if(input_datarate < 7384) {tmp1 = 6;tmp2 = 7;} //7.384MHz TS clock -+ else if(input_datarate < 8000) {tmp1 = 6;tmp2 = 6;} //8MHz TS clock -+ else if(input_datarate < 8727) {tmp1 = 5;tmp2 = 6;} //8.727MHz TS clock -+ else if(input_datarate < 9600) {tmp1 = 5;tmp2 = 5;} //9.6MHz TS clock -+ else if(input_datarate < 10666) {tmp1 = 4;tmp2 = 5;} //10.666MHz TS clock -+ else if(input_datarate < 12000) {tmp1 = 4;tmp2 = 4;} //12MHz TS clock -+ else if(input_datarate < 13714) {tmp1 = 3;tmp2 = 4;} //13.714MHz TS clock -+ else if(input_datarate < 16000) {tmp1 = 3;tmp2 = 3;} //16MHz TS clock -+ else if(input_datarate < 19200) {tmp1 = 2;tmp2 = 3;} //19.2MHz TS clock -+ else {tmp1 = 2;tmp2 = 2;} //24MHz TS clock -+ -+ if(state->demod_id == DS3000_ID) { -+ val = m88ds3103_readreg(state, 0xfe); -+ val &= 0xc0; -+ val |= ((u8)((tmp1<<3) + tmp2)); -+ m88ds3103_writereg(state, 0xfe, val); -+ } else { -+ if(input_datarate < 5200) /*Max. 2011-12-23 11:55*/ -+ input_datarate = 5200; -+ -+ if(input_datarate != 0) -+ divid_ratio = (u8)(MClk_KHz / input_datarate); -+ else -+ divid_ratio = 0xFF; -+ -+ if(divid_ratio > 128) -+ divid_ratio = 128; -+ -+ if(divid_ratio < 2) -+ divid_ratio = 2; -+ -+ tmp1 = (u8)(divid_ratio / 2); -+ tmp2 = (u8)(divid_ratio / 2); -+ -+ if((divid_ratio % 2) != 0) -+ tmp2 += 1; -+ -+ tmp1 -= 1; -+ tmp2 -= 1; -+ -+ tmp1 &= 0x3f; -+ tmp2 &= 0x3f; -+ -+ val = m88ds3103_readreg(state, 0xfe); -+ val &= 0xF0; -+ val |= (tmp2 >> 2) & 0x0f; -+ m88ds3103_writereg(state, 0xfe, val); -+ -+ val = (u8)((tmp2 & 0x03) << 6); -+ val |= tmp1; -+ m88ds3103_writereg(state, 0xea, val); -+ } -+ } -+ return 0; -+} -+ -+static int m88ds3103_demod_connect(struct dvb_frontend *fe, s32 carrier_offset_khz) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ struct dtv_frontend_properties *c = &fe->dtv_property_cache; -+ u16 value; -+ u8 val1,val2,data; -+ -+ dprintk("connect delivery system = %d\n", state->delivery_system); -+ -+ /* ds3000 global reset */ -+ m88ds3103_writereg(state, 0x07, 0x80); -+ m88ds3103_writereg(state, 0x07, 0x00); -+ /* ds3000 build-in uC reset */ -+ m88ds3103_writereg(state, 0xb2, 0x01); -+ /* ds3000 software reset */ -+ m88ds3103_writereg(state, 0x00, 0x01); -+ -+ switch (state->delivery_system) { -+ case SYS_DVBS: -+ /* initialise the demod in DVB-S mode */ -+ if(state->demod_id == DS3000_ID){ -+ m88ds3103_init_reg(state, ds3000_dvbs_init_tab, sizeof(ds3000_dvbs_init_tab)); -+ -+ value = m88ds3103_readreg(state, 0xfe); -+ value &= 0xc0; -+ value |= 0x1b; -+ m88ds3103_writereg(state, 0xfe, value); -+ -+ if(state->config->ci_mode) -+ val1 = 0x80; -+ else if(state->config->ts_mode) -+ val1 = 0x60; -+ else -+ val1 = 0x20; -+ m88ds3103_writereg(state, 0xfd, val1); -+ -+ }else if(state->demod_id == DS3103_ID){ -+ m88ds3103_init_reg(state, ds3103_dvbs_init_tab, sizeof(ds3103_dvbs_init_tab)); -+ -+ /* set ts clock */ -+ if(state->config->ci_mode == 2){ -+ val1 = 6; val2 = 6; -+ }else if(state->config->ts_mode == 0) { -+ val1 = 3; val2 = 3; -+ }else{ -+ val1 = 0; val2 = 0; -+ } -+ val1 -= 1; val2 -= 1; -+ val1 &= 0x3f; val2 &= 0x3f; -+ data = m88ds3103_readreg(state, 0xfe); -+ data &= 0xf0; -+ data |= (val2 >> 2) & 0x0f; -+ m88ds3103_writereg(state, 0xfe, data); -+ data = (val2 & 0x03) << 6; -+ data |= val1; -+ m88ds3103_writereg(state, 0xea, data); -+ -+ m88ds3103_writereg(state, 0x4d, 0xfd & m88ds3103_readreg(state, 0x4d)); -+ m88ds3103_writereg(state, 0x30, 0xef & m88ds3103_readreg(state, 0x30)); -+ -+ /* set master clock */ -+ val1 = m88ds3103_readreg(state, 0x22); -+ val2 = m88ds3103_readreg(state, 0x24); -+ -+ val1 &= 0x3f; -+ val2 &= 0x3f; -+ val1 |= 0x80; -+ val2 |= 0x40; -+ -+ m88ds3103_writereg(state, 0x22, val1); -+ m88ds3103_writereg(state, 0x24, val2); -+ -+ if(state->config->ci_mode) -+ val1 = 0x03; -+ else if(state->config->ts_mode) -+ val1 = 0x06; -+ else -+ val1 = 0x42; -+ m88ds3103_writereg(state, 0xfd, val1); -+ } -+ break; -+ case SYS_DVBS2: -+ /* initialise the demod in DVB-S2 mode */ -+ if(state->demod_id == DS3000_ID){ -+ m88ds3103_init_reg(state, ds3000_dvbs2_init_tab, sizeof(ds3000_dvbs2_init_tab)); -+ -+ if (c->symbol_rate >= 30000000) -+ m88ds3103_writereg(state, 0xfe, 0x54); -+ else -+ m88ds3103_writereg(state, 0xfe, 0x98); -+ -+ }else if(state->demod_id == DS3103_ID){ -+ m88ds3103_init_reg(state, ds3103_dvbs2_init_tab, sizeof(ds3103_dvbs2_init_tab)); -+ -+ /* set ts clock */ -+ if(state->config->ci_mode == 2){ -+ val1 = 6; val2 = 6; -+ }else if(state->config->ts_mode == 0){ -+ val1 = 5; val2 = 4; -+ }else{ -+ val1 = 0; val2 = 0; -+ } -+ val1 -= 1; val2 -= 1; -+ val1 &= 0x3f; val2 &= 0x3f; -+ data = m88ds3103_readreg(state, 0xfe); -+ data &= 0xf0; -+ data |= (val2 >> 2) & 0x0f; -+ m88ds3103_writereg(state, 0xfe, data); -+ data = (val2 & 0x03) << 6; -+ data |= val1; -+ m88ds3103_writereg(state, 0xea, data); -+ -+ m88ds3103_writereg(state, 0x4d, 0xfd & m88ds3103_readreg(state, 0x4d)); -+ m88ds3103_writereg(state, 0x30, 0xef & m88ds3103_readreg(state, 0x30)); -+ -+ /* set master clock */ -+ val1 = m88ds3103_readreg(state, 0x22); -+ val2 = m88ds3103_readreg(state, 0x24); -+ -+ val1 &= 0x3f; -+ val2 &= 0x3f; -+ if((state->config->ci_mode == 2) || (state->config->ts_mode == 1)){ -+ val1 |= 0x80; -+ val2 |= 0x40; -+ }else{ -+ if (c->symbol_rate >= 28000000){ -+ val1 |= 0xc0; -+ }else if (c->symbol_rate >= 18000000){ -+ val2 |= 0x40; -+ }else{ -+ val1 |= 0x80; -+ val2 |= 0x40; -+ } -+ } -+ m88ds3103_writereg(state, 0x22, val1); -+ m88ds3103_writereg(state, 0x24, val2); -+ } -+ -+ if(state->config->ci_mode) -+ val1 = 0x03; -+ else if(state->config->ts_mode) -+ val1 = 0x06; -+ else -+ val1 = 0x42; -+ m88ds3103_writereg(state, 0xfd, val1); -+ -+ break; -+ default: -+ return 1; -+ } -+ /* disable 27MHz clock output */ -+ m88ds3103_writereg(state, 0x29, 0x80); -+ /* enable ac coupling */ -+ m88ds3103_writereg(state, 0x25, 0x8a); -+ -+ if ((c->symbol_rate / 1000) <= 3000){ -+ m88ds3103_writereg(state, 0xc3, 0x08); /* 8 * 32 * 100 / 64 = 400*/ -+ m88ds3103_writereg(state, 0xc8, 0x20); -+ m88ds3103_writereg(state, 0xc4, 0x08); /* 8 * 0 * 100 / 128 = 0*/ -+ m88ds3103_writereg(state, 0xc7, 0x00); -+ }else if((c->symbol_rate / 1000) <= 10000){ -+ m88ds3103_writereg(state, 0xc3, 0x08); /* 8 * 16 * 100 / 64 = 200*/ -+ m88ds3103_writereg(state, 0xc8, 0x10); -+ m88ds3103_writereg(state, 0xc4, 0x08); /* 8 * 0 * 100 / 128 = 0*/ -+ m88ds3103_writereg(state, 0xc7, 0x00); -+ }else{ -+ m88ds3103_writereg(state, 0xc3, 0x08); /* 8 * 6 * 100 / 64 = 75*/ -+ m88ds3103_writereg(state, 0xc8, 0x06); -+ m88ds3103_writereg(state, 0xc4, 0x08); /* 8 * 0 * 100 / 128 = 0*/ -+ m88ds3103_writereg(state, 0xc7, 0x00); -+ } -+ -+ m88ds3103_set_symrate(fe); -+ -+ m88ds3103_set_CCI(fe); -+ -+ m88ds3103_set_carrier_offset(fe, carrier_offset_khz); -+ -+ /* ds3000 out of software reset */ -+ m88ds3103_writereg(state, 0x00, 0x00); -+ /* start ds3000 build-in uC */ -+ m88ds3103_writereg(state, 0xb2, 0x00); -+ -+ return 0; -+} -+ -+static int m88ds3103_set_frontend(struct dvb_frontend *fe) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ struct dtv_frontend_properties *c = &fe->dtv_property_cache; -+ -+ int i; -+ fe_status_t status; -+ u8 lpf_mxdiv, mlpf_max, mlpf_min, nlpf, div4, capCode, changePLL; -+ s32 offset_khz, lpf_offset_KHz; -+ u16 value, ndiv, lpf_coeff; -+ u32 f3db, gdiv28, realFreq; -+ u8 RFgain; -+ -+ dprintk("%s() ", __func__); -+ dprintk("c frequency = %d\n", c->frequency); -+ dprintk("symbol rate = %d\n", c->symbol_rate); -+ dprintk("delivery system = %d\n", c->delivery_system); -+ -+ realFreq = c->frequency; -+ lpf_offset_KHz = 0; -+ if(c->symbol_rate < 5000000){ -+ lpf_offset_KHz = FREQ_OFFSET_AT_SMALL_SYM_RATE_KHz; -+ realFreq += FREQ_OFFSET_AT_SMALL_SYM_RATE_KHz; -+ } -+ -+ if (state->config->set_ts_params) -+ state->config->set_ts_params(fe, 0); -+ -+ div4 = 0; -+ RFgain = 0; -+ if(state->tuner_id == TS2022_ID){ -+ m88ds3103_tuner_writereg(state, 0x10, 0x0a); -+ m88ds3103_tuner_writereg(state, 0x11, 0x40); -+ if (realFreq < 1103000) { -+ m88ds3103_tuner_writereg(state, 0x10, 0x1b); -+ div4 = 1; -+ ndiv = (realFreq * (6 + 8) * 4)/MT_FE_CRYSTAL_KHZ; -+ }else { -+ ndiv = (realFreq * (6 + 8) * 2)/MT_FE_CRYSTAL_KHZ; -+ } -+ ndiv = ndiv + ndiv%2; -+ if(ndiv < 4095) -+ ndiv = ndiv - 1024; -+ else if (ndiv < 6143) -+ ndiv = ndiv + 1024; -+ else -+ ndiv = ndiv + 3072; -+ -+ m88ds3103_tuner_writereg(state, 0x01, (ndiv & 0x3f00) >> 8); -+ }else{ -+ m88ds3103_tuner_writereg(state, 0x10, 0x00); -+ if (realFreq < 1146000){ -+ m88ds3103_tuner_writereg(state, 0x10, 0x11); -+ div4 = 1; -+ ndiv = (realFreq * (6 + 8) * 4) / MT_FE_CRYSTAL_KHZ; -+ }else{ -+ m88ds3103_tuner_writereg(state, 0x10, 0x01); -+ ndiv = (realFreq * (6 + 8) * 2) / MT_FE_CRYSTAL_KHZ; -+ } -+ ndiv = ndiv + ndiv%2; -+ ndiv = ndiv - 1024; -+ m88ds3103_tuner_writereg(state, 0x01, (ndiv>>8)&0x0f); -+ } -+ /* set pll */ -+ m88ds3103_tuner_writereg(state, 0x02, ndiv & 0x00ff); -+ m88ds3103_tuner_writereg(state, 0x03, 0x06); -+ m88ds3103_tuner_writereg(state, 0x51, 0x0f); -+ m88ds3103_tuner_writereg(state, 0x51, 0x1f); -+ m88ds3103_tuner_writereg(state, 0x50, 0x10); -+ m88ds3103_tuner_writereg(state, 0x50, 0x00); -+ -+ if(state->tuner_id == TS2022_ID){ -+ if(( realFreq >= 1650000 ) && (realFreq <= 1850000)){ -+ msleep(5); -+ value = m88ds3103_tuner_readreg(state, 0x14); -+ value &= 0x7f; -+ if(value < 64){ -+ m88ds3103_tuner_writereg(state, 0x10, 0x82); -+ m88ds3103_tuner_writereg(state, 0x11, 0x6f); -+ -+ m88ds3103_tuner_writereg(state, 0x51, 0x0f); -+ m88ds3103_tuner_writereg(state, 0x51, 0x1f); -+ m88ds3103_tuner_writereg(state, 0x50, 0x10); -+ m88ds3103_tuner_writereg(state, 0x50, 0x00); -+ } -+ } -+ msleep(5); -+ value = m88ds3103_tuner_readreg(state, 0x14); -+ value &= 0x1f; -+ -+ if(value > 19){ -+ value = m88ds3103_tuner_readreg(state, 0x10); -+ value &= 0x1d; -+ m88ds3103_tuner_writereg(state, 0x10, value); -+ } -+ }else{ -+ msleep(5); -+ value = m88ds3103_tuner_readreg(state, 0x66); -+ changePLL = (((value & 0x80) >> 7) != div4); -+ -+ if(changePLL){ -+ m88ds3103_tuner_writereg(state, 0x10, 0x11); -+ div4 = 1; -+ ndiv = (realFreq * (6 + 8) * 4)/MT_FE_CRYSTAL_KHZ; -+ ndiv = ndiv + ndiv%2; -+ ndiv = ndiv - 1024; -+ -+ m88ds3103_tuner_writereg(state, 0x01, (ndiv>>8) & 0x0f); -+ m88ds3103_tuner_writereg(state, 0x02, ndiv & 0xff); -+ -+ m88ds3103_tuner_writereg(state, 0x51, 0x0f); -+ m88ds3103_tuner_writereg(state, 0x51, 0x1f); -+ m88ds3103_tuner_writereg(state, 0x50, 0x10); -+ m88ds3103_tuner_writereg(state, 0x50, 0x00); -+ } -+ } -+ /*set the RF gain*/ -+ if(state->tuner_id == TS2020_ID) -+ m88ds3103_tuner_writereg(state, 0x60, 0x79); -+ -+ m88ds3103_tuner_writereg(state, 0x51, 0x17); -+ m88ds3103_tuner_writereg(state, 0x51, 0x1f); -+ m88ds3103_tuner_writereg(state, 0x50, 0x08); -+ m88ds3103_tuner_writereg(state, 0x50, 0x00); -+ msleep(5); -+ -+ if(state->tuner_id == TS2020_ID){ -+ RFgain = m88ds3103_tuner_readreg(state, 0x3d); -+ RFgain &= 0x0f; -+ if(RFgain < 15){ -+ if(RFgain < 4) -+ RFgain = 0; -+ else -+ RFgain = RFgain -3; -+ value = ((RFgain << 3) | 0x01) & 0x79; -+ m88ds3103_tuner_writereg(state, 0x60, value); -+ m88ds3103_tuner_writereg(state, 0x51, 0x17); -+ m88ds3103_tuner_writereg(state, 0x51, 0x1f); -+ m88ds3103_tuner_writereg(state, 0x50, 0x08); -+ m88ds3103_tuner_writereg(state, 0x50, 0x00); -+ } -+ } -+ -+ /* set the LPF */ -+ if(state->tuner_id == TS2022_ID){ -+ m88ds3103_tuner_writereg(state, 0x25, 0x00); -+ m88ds3103_tuner_writereg(state, 0x27, 0x70); -+ m88ds3103_tuner_writereg(state, 0x41, 0x09); -+ m88ds3103_tuner_writereg(state, 0x08, 0x0b); -+ } -+ -+ f3db = ((c->symbol_rate / 1000) *135) / 200 + 2000; -+ f3db += lpf_offset_KHz; -+ if (f3db < 7000) -+ f3db = 7000; -+ if (f3db > 40000) -+ f3db = 40000; -+ -+ gdiv28 = (MT_FE_CRYSTAL_KHZ / 1000 * 1694 + 500) / 1000; -+ m88ds3103_tuner_writereg(state, 0x04, gdiv28 & 0xff); -+ m88ds3103_tuner_writereg(state, 0x51, 0x1b); -+ m88ds3103_tuner_writereg(state, 0x51, 0x1f); -+ m88ds3103_tuner_writereg(state, 0x50, 0x04); -+ m88ds3103_tuner_writereg(state, 0x50, 0x00); -+ msleep(5); -+ -+ value = m88ds3103_tuner_readreg(state, 0x26); -+ capCode = value & 0x3f; -+ if(state->tuner_id == TS2022_ID){ -+ m88ds3103_tuner_writereg(state, 0x41, 0x0d); -+ -+ m88ds3103_tuner_writereg(state, 0x51, 0x1b); -+ m88ds3103_tuner_writereg(state, 0x51, 0x1f); -+ m88ds3103_tuner_writereg(state, 0x50, 0x04); -+ m88ds3103_tuner_writereg(state, 0x50, 0x00); -+ -+ msleep(2); -+ -+ value = m88ds3103_tuner_readreg(state, 0x26); -+ value &= 0x3f; -+ value = (capCode + value) / 2; -+ } -+ else -+ value = capCode; -+ -+ gdiv28 = gdiv28 * 207 / (value * 2 + 151); -+ mlpf_max = gdiv28 * 135 / 100; -+ mlpf_min = gdiv28 * 78 / 100; -+ if (mlpf_max > 63) -+ mlpf_max = 63; -+ -+ if(state->tuner_id == TS2022_ID) -+ lpf_coeff = 3200; -+ else -+ lpf_coeff = 2766; -+ -+ nlpf = (f3db * gdiv28 * 2 / lpf_coeff / (MT_FE_CRYSTAL_KHZ / 1000) + 1) / 2 ; -+ if (nlpf > 23) nlpf = 23; -+ if (nlpf < 1) nlpf = 1; -+ -+ lpf_mxdiv = (nlpf * (MT_FE_CRYSTAL_KHZ / 1000) * lpf_coeff * 2 / f3db + 1) / 2; -+ -+ if (lpf_mxdiv < mlpf_min){ -+ nlpf++; -+ lpf_mxdiv = (nlpf * (MT_FE_CRYSTAL_KHZ / 1000) * lpf_coeff * 2 / f3db + 1) / 2; -+ } -+ -+ if (lpf_mxdiv > mlpf_max) -+ lpf_mxdiv = mlpf_max; -+ -+ m88ds3103_tuner_writereg(state, 0x04, lpf_mxdiv); -+ m88ds3103_tuner_writereg(state, 0x06, nlpf); -+ m88ds3103_tuner_writereg(state, 0x51, 0x1b); -+ m88ds3103_tuner_writereg(state, 0x51, 0x1f); -+ m88ds3103_tuner_writereg(state, 0x50, 0x04); -+ m88ds3103_tuner_writereg(state, 0x50, 0x00); -+ msleep(5); -+ -+ if(state->tuner_id == TS2022_ID){ -+ msleep(2); -+ value = m88ds3103_tuner_readreg(state, 0x26); -+ capCode = value & 0x3f; -+ -+ m88ds3103_tuner_writereg(state, 0x41, 0x09); -+ -+ m88ds3103_tuner_writereg(state, 0x51, 0x1b); -+ m88ds3103_tuner_writereg(state, 0x51, 0x1f); -+ m88ds3103_tuner_writereg(state, 0x50, 0x04); -+ m88ds3103_tuner_writereg(state, 0x50, 0x00); -+ -+ msleep(2); -+ value = m88ds3103_tuner_readreg(state, 0x26); -+ value &= 0x3f; -+ value = (capCode + value) / 2; -+ -+ value = value | 0x80; -+ m88ds3103_tuner_writereg(state, 0x25, value); -+ m88ds3103_tuner_writereg(state, 0x27, 0x30); -+ -+ m88ds3103_tuner_writereg(state, 0x08, 0x09); -+ } -+ -+ /* Set the BB gain */ -+ m88ds3103_tuner_writereg(state, 0x51, 0x1e); -+ m88ds3103_tuner_writereg(state, 0x51, 0x1f); -+ m88ds3103_tuner_writereg(state, 0x50, 0x01); -+ m88ds3103_tuner_writereg(state, 0x50, 0x00); -+ if(state->tuner_id == TS2020_ID){ -+ if(RFgain == 15){ -+ msleep(40); -+ value = m88ds3103_tuner_readreg(state, 0x21); -+ value &= 0x0f; -+ if(value < 3){ -+ m88ds3103_tuner_writereg(state, 0x60, 0x61); -+ m88ds3103_tuner_writereg(state, 0x51, 0x17); -+ m88ds3103_tuner_writereg(state, 0x51, 0x1f); -+ m88ds3103_tuner_writereg(state, 0x50, 0x08); -+ m88ds3103_tuner_writereg(state, 0x50, 0x00); -+ } -+ } -+ } -+ msleep(60); -+ -+ offset_khz = (ndiv - ndiv % 2 + 1024) * MT_FE_CRYSTAL_KHZ -+ / (6 + 8) / (div4 + 1) / 2 - realFreq; -+ -+ m88ds3103_demod_connect(fe, offset_khz+lpf_offset_KHz); -+ -+ for (i = 0; i < 30 ; i++) { -+ m88ds3103_read_status(fe, &status); -+ if (status & FE_HAS_LOCK){ -+ break; -+ } -+ msleep(20); -+ } -+ -+ if((status & FE_HAS_LOCK) == 0){ -+ state->delivery_system = (state->delivery_system == SYS_DVBS) ? SYS_DVBS2 : SYS_DVBS; -+ m88ds3103_demod_connect(fe, offset_khz); -+ -+ for (i = 0; i < 30 ; i++) { -+ m88ds3103_read_status(fe, &status); -+ if (status & FE_HAS_LOCK){ -+ break; -+ } -+ msleep(20); -+ } -+ } -+ -+ if (status & FE_HAS_LOCK){ -+ if(state->config->ci_mode == 2) -+ m88ds3103_set_clock_ratio(state); -+ if(state->config->start_ctrl){ -+ if(state->first_lock == 0){ -+ state->config->start_ctrl(fe); -+ state->first_lock = 1; -+ } -+ } -+ } -+ -+ return 0; -+} -+ -+static int m88ds3103_tune(struct dvb_frontend *fe, -+ bool re_tune, -+ unsigned int mode_flags, -+ unsigned int *delay, -+ fe_status_t *status) -+{ -+ *delay = HZ / 5; -+ -+ dprintk("%s() ", __func__); -+ dprintk("re_tune = %d\n", re_tune); -+ -+ if (re_tune) { -+ int ret = m88ds3103_set_frontend(fe); -+ if (ret) -+ return ret; -+ } -+ -+ return m88ds3103_read_status(fe, status); -+} -+ -+static enum dvbfe_algo m88ds3103_get_algo(struct dvb_frontend *fe) -+{ -+ return DVBFE_ALGO_HW; -+} -+ -+ /* -+ * Power config will reset and load initial firmware if required -+ */ -+static int m88ds3103_initilaze(struct dvb_frontend *fe) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ int ret; -+ -+ dprintk("%s()\n", __func__); -+ /* hard reset */ -+ m88ds3103_writereg(state, 0x07, 0x80); -+ m88ds3103_writereg(state, 0x07, 0x00); -+ msleep(1); -+ -+ m88ds3103_writereg(state, 0x08, 0x01 | m88ds3103_readreg(state, 0x08)); -+ msleep(1); -+ -+ if(state->tuner_id == TS2020_ID){ -+ /* TS2020 init */ -+ m88ds3103_tuner_writereg(state, 0x42, 0x73); -+ msleep(2); -+ m88ds3103_tuner_writereg(state, 0x05, 0x01); -+ m88ds3103_tuner_writereg(state, 0x62, 0xb5); -+ m88ds3103_tuner_writereg(state, 0x07, 0x02); -+ m88ds3103_tuner_writereg(state, 0x08, 0x01); -+ } -+ else if(state->tuner_id == TS2022_ID){ -+ /* TS2022 init */ -+ m88ds3103_tuner_writereg(state, 0x62, 0x6c); -+ msleep(2); -+ m88ds3103_tuner_writereg(state, 0x42, 0x6c); -+ msleep(2); -+ m88ds3103_tuner_writereg(state, 0x7d, 0x9d); -+ m88ds3103_tuner_writereg(state, 0x7c, 0x9a); -+ m88ds3103_tuner_writereg(state, 0x7a, 0x76); -+ -+ m88ds3103_tuner_writereg(state, 0x3b, 0x01); -+ m88ds3103_tuner_writereg(state, 0x63, 0x88); -+ -+ m88ds3103_tuner_writereg(state, 0x61, 0x85); -+ m88ds3103_tuner_writereg(state, 0x22, 0x30); -+ m88ds3103_tuner_writereg(state, 0x30, 0x40); -+ m88ds3103_tuner_writereg(state, 0x20, 0x23); -+ m88ds3103_tuner_writereg(state, 0x24, 0x02); -+ m88ds3103_tuner_writereg(state, 0x12, 0xa0); -+ } -+ -+ if(state->demod_id == DS3103_ID){ -+ m88ds3103_writereg(state, 0x07, 0xe0); -+ m88ds3103_writereg(state, 0x07, 0x00); -+ msleep(1); -+ } -+ m88ds3103_writereg(state, 0xb2, 0x01); -+ -+ /* Load the firmware if required */ -+ ret = m88ds3103_load_firmware(fe); -+ if (ret != 0){ -+ printk(KERN_ERR "%s: Unable initialize firmware\n", __func__); -+ return ret; -+ } -+ if(state->demod_id == DS3103_ID){ -+ m88ds3103_writereg(state, 0x4d, 0xfd & m88ds3103_readreg(state, 0x4d)); -+ m88ds3103_writereg(state, 0x30, 0xef & m88ds3103_readreg(state, 0x30)); -+ } -+ -+ return 0; -+} -+ -+/* -+ * Initialise or wake up device -+ */ -+static int m88ds3103_initfe(struct dvb_frontend *fe) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ u8 val; -+ -+ dprintk("%s()\n", __func__); -+ -+ /* 1st step to wake up demod */ -+ m88ds3103_writereg(state, 0x08, 0x01 | m88ds3103_readreg(state, 0x08)); -+ m88ds3103_writereg(state, 0x04, 0xfe & m88ds3103_readreg(state, 0x04)); -+ m88ds3103_writereg(state, 0x23, 0xef & m88ds3103_readreg(state, 0x23)); -+ -+ /* 2nd step to wake up tuner */ -+ val = m88ds3103_tuner_readreg(state, 0x00) & 0xff; -+ if((val & 0x01) == 0){ -+ m88ds3103_tuner_writereg(state, 0x00, 0x01); -+ msleep(50); -+ } -+ m88ds3103_tuner_writereg(state, 0x00, 0x03); -+ msleep(50); -+ -+ return 0; -+} -+ -+/* Put device to sleep */ -+static int m88ds3103_sleep(struct dvb_frontend *fe) -+{ -+ struct m88ds3103_state *state = fe->demodulator_priv; -+ -+ dprintk("%s()\n", __func__); -+ -+ /* 1st step to sleep tuner */ -+ m88ds3103_tuner_writereg(state, 0x00, 0x00); -+ -+ /* 2nd step to sleep demod */ -+ m88ds3103_writereg(state, 0x08, 0xfe & m88ds3103_readreg(state, 0x08)); -+ m88ds3103_writereg(state, 0x04, 0x01 | m88ds3103_readreg(state, 0x04)); -+ m88ds3103_writereg(state, 0x23, 0x10 | m88ds3103_readreg(state, 0x23)); -+ -+ -+ return 0; -+} -+ -+static struct dvb_frontend_ops m88ds3103_ops = { -+ .delsys = { SYS_DVBS, SYS_DVBS2}, -+ .info = { -+ .name = "Montage DS3103/TS2022", -+ .type = FE_QPSK, -+ .frequency_min = 950000, -+ .frequency_max = 2150000, -+ .frequency_stepsize = 1011, /* kHz for QPSK frontends */ -+ .frequency_tolerance = 5000, -+ .symbol_rate_min = 1000000, -+ .symbol_rate_max = 45000000, -+ .caps = FE_CAN_INVERSION_AUTO | -+ FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | -+ FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | -+ FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | -+ FE_CAN_2G_MODULATION | -+ FE_CAN_QPSK | FE_CAN_RECOVER -+ }, -+ -+ .release = m88ds3103_release, -+ -+ .init = m88ds3103_initfe, -+ .sleep = m88ds3103_sleep, -+ .read_status = m88ds3103_read_status, -+ .read_ber = m88ds3103_read_ber, -+ .read_signal_strength = m88ds3103_read_signal_strength, -+ .read_snr = m88ds3103_read_snr, -+ .read_ucblocks = m88ds3103_read_ucblocks, -+ .set_tone = m88ds3103_set_tone, -+ .set_voltage = m88ds3103_set_voltage, -+ .diseqc_send_master_cmd = m88ds3103_send_diseqc_msg, -+ .diseqc_send_burst = m88ds3103_diseqc_send_burst, -+ .get_frontend_algo = m88ds3103_get_algo, -+ .tune = m88ds3103_tune, -+ .set_frontend = m88ds3103_set_frontend, -+}; -+ -+MODULE_DESCRIPTION("DVB Frontend module for Montage DS3103/TS2022 hardware"); -+MODULE_AUTHOR("Max nibble"); -+MODULE_LICENSE("GPL"); -diff -urN a/drivers/media/dvb-frontends/m88ds3103.h b/drivers/media/dvb-frontends/m88ds3103.h ---- a/drivers/media/dvb-frontends/m88ds3103.h 1970-01-01 08:00:00.000000000 +0800 -+++ b/drivers/media/dvb-frontends/m88ds3103.h 2013-01-30 12:33:51.000000000 +0800 -@@ -0,0 +1,53 @@ -+/* -+ Montage Technology M88DS3103/M88TS2022 - DVBS/S2 Satellite demod/tuner driver -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 2 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#ifndef M88DS3103_H -+#define M88DS3103_H -+ -+#include -+ -+struct m88ds3103_config { -+ /* the demodulator's i2c address */ -+ u8 demod_address; -+ u8 ci_mode; -+ u8 pin_ctrl; -+ u8 ts_mode; /* 0: Parallel, 1: Serial */ -+ -+ /* Set device param to start dma */ -+ int (*set_ts_params)(struct dvb_frontend *fe, int is_punctured); -+ /* Start to transfer data */ -+ int (*start_ctrl)(struct dvb_frontend *fe); -+ /* Set LNB voltage */ -+ int (*set_voltage)(struct dvb_frontend* fe, fe_sec_voltage_t voltage); -+}; -+ -+#if defined(CONFIG_DVB_M88DS3103) || \ -+ (defined(CONFIG_DVB_M88DS3103_MODULE) && defined(MODULE)) -+extern struct dvb_frontend *m88ds3103_attach( -+ const struct m88ds3103_config *config, -+ struct i2c_adapter *i2c); -+#else -+static inline struct dvb_frontend *m88ds3103_attach( -+ const struct m88ds3103_config *config, -+ struct i2c_adapter *i2c) -+{ -+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); -+ return NULL; -+} -+#endif /* CONFIG_DVB_M88DS3103 */ -+#endif /* M88DS3103_H */ -diff -urN a/drivers/media/dvb-frontends/m88ds3103_priv.h b/drivers/media/dvb-frontends/m88ds3103_priv.h ---- a/drivers/media/dvb-frontends/m88ds3103_priv.h 1970-01-01 08:00:00.000000000 +0800 -+++ b/drivers/media/dvb-frontends/m88ds3103_priv.h 2013-01-30 12:33:56.000000000 +0800 -@@ -0,0 +1,403 @@ -+/* -+ Montage Technology M88DS3103/M88TS2022 - DVBS/S2 Satellite demod/tuner driver -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 2 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#ifndef M88DS3103_PRIV_H -+#define M88DS3103_PRIV_H -+ -+#define FW_DOWN_SIZE 32 -+#define FW_DOWN_LOOP (8192/FW_DOWN_SIZE) -+#define DS3103_DEFAULT_FIRMWARE "dvb-fe-ds3103.fw" -+#define DS3000_DEFAULT_FIRMWARE "dvb-fe-ds300x.fw" -+#define MT_FE_MCLK_KHZ 96000 /* in kHz */ -+#define MT_FE_CRYSTAL_KHZ 27000 /* in kHz */ -+#define FREQ_OFFSET_AT_SMALL_SYM_RATE_KHz 3000 -+#define DS3000_ID 0x3000 -+#define DS3103_ID 0x3103 -+#define TS2020_ID 0x2020 -+#define TS2022_ID 0x2022 -+#define UNKNOW_ID 0x0000 -+ -+struct m88ds3103_state { -+ struct i2c_adapter *i2c; -+ const struct m88ds3103_config *config; -+ -+ struct dvb_frontend frontend; -+ -+ u32 preBer; -+ u8 skip_fw_load; -+ u8 first_lock; /* The first time of signal lock */ -+ u16 demod_id; /* demod chip type */ -+ u16 tuner_id; /* tuner chip type */ -+ fe_delivery_system_t delivery_system; -+}; -+ -+/* For M88DS3103 demod dvbs mode.*/ -+static u8 ds3103_dvbs_init_tab[] = { -+ 0x23, 0x07, -+ 0x08, 0x03, -+ 0x0c, 0x02, -+ 0x21, 0x54, -+ 0x25, 0x82, -+ 0x27, 0x31, -+ 0x30, 0x08, -+ 0x31, 0x40, -+ 0x32, 0x32, -+ 0x33, 0x35, -+ 0x35, 0xff, -+ 0x3a, 0x00, -+ 0x37, 0x10, -+ 0x38, 0x10, -+ 0x39, 0x02, -+ 0x42, 0x60, -+ 0x4a, 0x80, -+ 0x4b, 0x04, -+ 0x4d, 0x91, -+ 0x5d, 0xc8, -+ 0x50, 0x36, -+ 0x51, 0x36, -+ 0x52, 0x36, -+ 0x53, 0x36, -+ 0x63, 0x0f, -+ 0x64, 0x30, -+ 0x65, 0x40, -+ 0x68, 0x26, -+ 0x69, 0x4c, -+ 0x70, 0x20, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0x40, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0x60, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0x80, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0xa0, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0x1f, -+ 0x76, 0x38, -+ 0x77, 0xa6, -+ 0x78, 0x0c, -+ 0x79, 0x80, -+ 0x7f, 0x14, -+ 0x7c, 0x00, -+ 0xae, 0x82, -+ 0x80, 0x64, -+ 0x81, 0x66, -+ 0x82, 0x44, -+ 0x85, 0x04, -+ 0xcd, 0xf4, -+ 0x90, 0x33, -+ 0xa0, 0x44, -+ 0xc0, 0x08, -+ 0xc3, 0x10, -+ 0xc4, 0x08, -+ 0xc5, 0xf0, -+ 0xc6, 0xff, -+ 0xc7, 0x00, -+ 0xc8, 0x1a, -+ 0xc9, 0x80, -+ 0xe0, 0xf8, -+ 0xe6, 0x8b, -+ 0xd0, 0x40, -+ 0xf8, 0x20, -+ 0xfa, 0x0f, -+ 0x00, 0x00, -+ 0xbd, 0x01, -+ 0xb8, 0x00, -+}; -+/* For M88DS3103 demod dvbs2 mode.*/ -+static u8 ds3103_dvbs2_init_tab[] = { -+ 0x23, 0x07, -+ 0x08, 0x07, -+ 0x0c, 0x02, -+ 0x21, 0x54, -+ 0x25, 0x82, -+ 0x27, 0x31, -+ 0x30, 0x08, -+ 0x32, 0x32, -+ 0x33, 0x35, -+ 0x35, 0xff, -+ 0x3a, 0x00, -+ 0x37, 0x10, -+ 0x38, 0x10, -+ 0x39, 0x02, -+ 0x42, 0x60, -+ 0x4a, 0x80, -+ 0x4b, 0x04, -+ 0x4d, 0x91, -+ 0x5d, 0xc8, -+ 0x50, 0x36, -+ 0x51, 0x36, -+ 0x52, 0x36, -+ 0x53, 0x36, -+ 0x63, 0x0f, -+ 0x64, 0x10, -+ 0x65, 0x20, -+ 0x68, 0x46, -+ 0x69, 0xcd, -+ 0x70, 0x20, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0x40, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0x60, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0x80, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0xa0, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0x1f, -+ 0x76, 0x38, -+ 0x77, 0xa6, -+ 0x78, 0x0c, -+ 0x79, 0x80, -+ 0x7f, 0x14, -+ 0x85, 0x08, -+ 0xcd, 0xf4, -+ 0x90, 0x33, -+ 0x86, 0x00, -+ 0x87, 0x0f, -+ 0x89, 0x00, -+ 0x8b, 0x44, -+ 0x8c, 0x66, -+ 0x9d, 0xc1, -+ 0x8a, 0x10, -+ 0xad, 0x40, -+ 0xa0, 0x44, -+ 0xc0, 0x08, -+ 0xc1, 0x10, -+ 0xc2, 0x08, -+ 0xc3, 0x10, -+ 0xc4, 0x08, -+ 0xc5, 0xf0, -+ 0xc6, 0xff, -+ 0xc7, 0x00, -+ 0xc8, 0x1a, -+ 0xc9, 0x80, -+ 0xca, 0x23, -+ 0xcb, 0x24, -+ 0xcc, 0xf4, -+ 0xce, 0x74, -+ 0x00, 0x00, -+ 0xbd, 0x01, -+ 0xb8, 0x00, -+}; -+ -+/* For M88DS3000 demod dvbs mode.*/ -+static u8 ds3000_dvbs_init_tab[] = { -+ 0x23, 0x05, -+ 0x08, 0x03, -+ 0x0c, 0x02, -+ 0x21, 0x54, -+ 0x25, 0x82, -+ 0x27, 0x31, -+ 0x30, 0x08, -+ 0x31, 0x40, -+ 0x32, 0x32, -+ 0x33, 0x35, -+ 0x35, 0xff, -+ 0x3a, 0x00, -+ 0x37, 0x10, -+ 0x38, 0x10, -+ 0x39, 0x02, -+ 0x42, 0x60, -+ 0x4a, 0x40, -+ 0x4b, 0x04, -+ 0x4d, 0x91, -+ 0x5d, 0xc8, -+ 0x50, 0x77, -+ 0x51, 0x77, -+ 0x52, 0x36, -+ 0x53, 0x36, -+ 0x56, 0x01, -+ 0x63, 0x47, -+ 0x64, 0x30, -+ 0x65, 0x40, -+ 0x68, 0x26, -+ 0x69, 0x4c, -+ 0x70, 0x20, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0x40, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0x60, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0x80, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0xa0, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0x1f, -+ 0x76, 0x00, -+ 0x77, 0xd1, -+ 0x78, 0x0c, -+ 0x79, 0x80, -+ 0x7f, 0x04, -+ 0x7c, 0x00, -+ 0x80, 0x86, -+ 0x81, 0xa6, -+ 0x85, 0x04, -+ 0xcd, 0xf4, -+ 0x90, 0x33, -+ 0xa0, 0x44, -+ 0xc0, 0x18, -+ 0xc3, 0x10, -+ 0xc4, 0x08, -+ 0xc5, 0x80, -+ 0xc6, 0x80, -+ 0xc7, 0x0a, -+ 0xc8, 0x1a, -+ 0xc9, 0x80, -+ 0xfe, 0xb6, -+ 0xe0, 0xf8, -+ 0xe6, 0x8b, -+ 0xd0, 0x40, -+ 0xf8, 0x20, -+ 0xfa, 0x0f, -+ 0xad, 0x20, -+ 0xae, 0x07, -+ 0xb8, 0x00, -+}; -+ -+/* For M88DS3000 demod dvbs2 mode.*/ -+static u8 ds3000_dvbs2_init_tab[] = { -+ 0x23, 0x0f, -+ 0x08, 0x07, -+ 0x0c, 0x02, -+ 0x21, 0x54, -+ 0x25, 0x82, -+ 0x27, 0x31, -+ 0x30, 0x08, -+ 0x31, 0x32, -+ 0x32, 0x32, -+ 0x33, 0x35, -+ 0x35, 0xff, -+ 0x3a, 0x00, -+ 0x37, 0x10, -+ 0x38, 0x10, -+ 0x39, 0x02, -+ 0x42, 0x60, -+ 0x4a, 0x80, -+ 0x4b, 0x04, -+ 0x4d, 0x91, -+ 0x5d, 0x88, -+ 0x50, 0x36, -+ 0x51, 0x36, -+ 0x52, 0x36, -+ 0x53, 0x36, -+ 0x63, 0x60, -+ 0x64, 0x10, -+ 0x65, 0x10, -+ 0x68, 0x04, -+ 0x69, 0x29, -+ 0x70, 0x20, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0x40, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0x60, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0x80, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0xa0, -+ 0x71, 0x70, -+ 0x72, 0x04, -+ 0x73, 0x00, -+ 0x70, 0x1f, -+ 0xa0, 0x44, -+ 0xc0, 0x08, -+ 0xc1, 0x10, -+ 0xc2, 0x08, -+ 0xc3, 0x10, -+ 0xc4, 0x08, -+ 0xc5, 0xf0, -+ 0xc6, 0xf0, -+ 0xc7, 0x0a, -+ 0xc8, 0x1a, -+ 0xc9, 0x80, -+ 0xca, 0x23, -+ 0xcb, 0x24, -+ 0xce, 0x74, -+ 0x56, 0x01, -+ 0x90, 0x03, -+ 0x76, 0x80, -+ 0x77, 0x42, -+ 0x78, 0x0a, -+ 0x79, 0x80, -+ 0xad, 0x40, -+ 0xae, 0x07, -+ 0x7f, 0xd4, -+ 0x7c, 0x00, -+ 0x80, 0xa8, -+ 0x81, 0xda, -+ 0x7c, 0x01, -+ 0x80, 0xda, -+ 0x81, 0xec, -+ 0x7c, 0x02, -+ 0x80, 0xca, -+ 0x81, 0xeb, -+ 0x7c, 0x03, -+ 0x80, 0xba, -+ 0x81, 0xdb, -+ 0x85, 0x08, -+ 0x86, 0x00, -+ 0x87, 0x02, -+ 0x89, 0x80, -+ 0x8b, 0x44, -+ 0x8c, 0xaa, -+ 0x8a, 0x10, -+ 0xba, 0x00, -+ 0xf5, 0x04, -+ 0xd2, 0x32, -+ 0xb8, 0x00, -+}; -+ -+#endif /* M88DS3103_PRIV_H */ -diff -urN a/drivers/media/dvb-frontends/Makefile b/drivers/media/dvb-frontends/Makefile ---- a/drivers/media/dvb-frontends/Makefile 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/dvb-frontends/Makefile 2013-05-03 17:04:31.000000000 +0800 -@@ -103,4 +103,5 @@ - obj-$(CONFIG_DVB_RTL2832) += rtl2832.o - obj-$(CONFIG_DVB_M88RS2000) += m88rs2000.o - obj-$(CONFIG_DVB_AF9033) += af9033.o -- -+obj-$(CONFIG_DVB_M88DS3103) += m88ds3103.o -+obj-$(CONFIG_DVB_M88DC2800) += m88dc2800.o -diff -urN a/drivers/media/pci/cx23885/cimax2.c b/drivers/media/pci/cx23885/cimax2.c ---- a/drivers/media/pci/cx23885/cimax2.c 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/pci/cx23885/cimax2.c 2013-03-31 22:03:29.000000000 +0800 -@@ -415,7 +415,7 @@ - return state->status; - } - --int netup_ci_init(struct cx23885_tsport *port) -+int netup_ci_init(struct cx23885_tsport *port, bool isDVBSky) - { - struct netup_ci_state *state; - u8 cimax_init[34] = { -@@ -464,6 +464,11 @@ - goto err; - } - -+ if(isDVBSky) { -+ cimax_init[32] = 0x22; -+ cimax_init[33] = 0x00; -+ } -+ - port->port_priv = state; - - switch (port->nr) { -@@ -537,3 +542,19 @@ - dvb_ca_en50221_release(&state->ca); - kfree(state); - } -+ -+/* CI irq handler for DVBSky board*/ -+int dvbsky_ci_slot_status(struct cx23885_dev *dev) -+{ -+ struct cx23885_tsport *port = NULL; -+ struct netup_ci_state *state = NULL; -+ -+ ci_dbg_print("%s:\n", __func__); -+ -+ port = &dev->ts1; -+ state = port->port_priv; -+ schedule_work(&state->work); -+ ci_dbg_print("%s: Wakeup CI0\n", __func__); -+ -+ return 1; -+} -diff -urN a/drivers/media/pci/cx23885/cimax2.h b/drivers/media/pci/cx23885/cimax2.h ---- a/drivers/media/pci/cx23885/cimax2.h 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/pci/cx23885/cimax2.h 2013-01-30 12:34:37.000000000 +0800 -@@ -41,7 +41,9 @@ - extern int netup_ci_slot_status(struct cx23885_dev *dev, u32 pci_status); - extern int netup_poll_ci_slot_status(struct dvb_ca_en50221 *en50221, - int slot, int open); --extern int netup_ci_init(struct cx23885_tsport *port); -+extern int netup_ci_init(struct cx23885_tsport *port, bool isDVBSky); - extern void netup_ci_exit(struct cx23885_tsport *port); - -+extern int dvbsky_ci_slot_status(struct cx23885_dev *dev); -+ - #endif -diff -urN a/drivers/media/pci/cx23885/cx23885-cards.c b/drivers/media/pci/cx23885/cx23885-cards.c ---- a/drivers/media/pci/cx23885/cx23885-cards.c 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/pci/cx23885/cx23885-cards.c 2013-05-03 17:34:46.000000000 +0800 -@@ -569,6 +569,34 @@ - .name = "TeVii S471", - .portb = CX23885_MPEG_DVB, - }, -+ [CX23885_BOARD_BST_PS8512] = { -+ .name = "Bestunar PS8512", -+ .portb = CX23885_MPEG_DVB, -+ }, -+ [CX23885_BOARD_DVBSKY_S950] = { -+ .name = "DVBSKY S950", -+ .portb = CX23885_MPEG_DVB, -+ }, -+ [CX23885_BOARD_DVBSKY_S952] = { -+ .name = "DVBSKY S952", -+ .portb = CX23885_MPEG_DVB, -+ .portc = CX23885_MPEG_DVB, -+ }, -+ [CX23885_BOARD_DVBSKY_S950_CI] = { -+ .ci_type = 3, -+ .name = "DVBSKY S950CI DVB-S2 CI", -+ .portb = CX23885_MPEG_DVB, -+ }, -+ [CX23885_BOARD_DVBSKY_C2800E_CI] = { -+ .ci_type = 3, -+ .name = "DVBSKY C2800E DVB-C CI", -+ .portb = CX23885_MPEG_DVB, -+ }, -+ [CX23885_BOARD_DVBSKY_T9580] = { -+ .name = "DVBSKY T9580", -+ .portb = CX23885_MPEG_DVB, -+ .portc = CX23885_MPEG_DVB, -+ }, - [CX23885_BOARD_PROF_8000] = { - .name = "Prof Revolution DVB-S2 8000", - .portb = CX23885_MPEG_DVB, -@@ -605,7 +633,7 @@ - CX25840_NONE1_CH3, - .amux = CX25840_AUDIO6, - } }, -- } -+ } - }; - const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards); - -@@ -818,6 +846,30 @@ - .subdevice = 0x9022, - .card = CX23885_BOARD_TEVII_S471, - }, { -+ .subvendor = 0x14f1, -+ .subdevice = 0x8512, -+ .card = CX23885_BOARD_BST_PS8512, -+ }, { -+ .subvendor = 0x4254, -+ .subdevice = 0x0950, -+ .card = CX23885_BOARD_DVBSKY_S950, -+ }, { -+ .subvendor = 0x4254, -+ .subdevice = 0x0952, -+ .card = CX23885_BOARD_DVBSKY_S952, -+ }, { -+ .subvendor = 0x4254, -+ .subdevice = 0x950C, -+ .card = CX23885_BOARD_DVBSKY_S950_CI, -+ }, { -+ .subvendor = 0x4254, -+ .subdevice = 0x2800, -+ .card = CX23885_BOARD_DVBSKY_C2800E_CI, -+ }, { -+ .subvendor = 0x4254, -+ .subdevice = 0x9580, -+ .card = CX23885_BOARD_DVBSKY_T9580, -+ }, { - .subvendor = 0x8000, - .subdevice = 0x3034, - .card = CX23885_BOARD_PROF_8000, -@@ -1224,7 +1276,7 @@ - cx_set(GP0_IO, 0x00040004); - break; - case CX23885_BOARD_TBS_6920: -- case CX23885_BOARD_PROF_8000: -+ case CX23885_BOARD_PROF_8000: - cx_write(MC417_CTL, 0x00000036); - cx_write(MC417_OEN, 0x00001000); - cx_set(MC417_RWD, 0x00000002); -@@ -1394,9 +1446,84 @@ - cx_set(GP0_IO, 0x00040004); - mdelay(60); - break; -+ case CX23885_BOARD_DVBSKY_S950: -+ case CX23885_BOARD_BST_PS8512: -+ cx23885_gpio_enable(dev, GPIO_2, 1); -+ cx23885_gpio_clear(dev, GPIO_2); -+ msleep(100); -+ cx23885_gpio_set(dev, GPIO_2); -+ break; -+ case CX23885_BOARD_DVBSKY_S952: -+ case CX23885_BOARD_DVBSKY_T9580: -+ cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */ -+ -+ cx23885_gpio_enable(dev, GPIO_2, 1); -+ cx23885_gpio_enable(dev, GPIO_11, 1); -+ -+ cx23885_gpio_clear(dev, GPIO_2); -+ cx23885_gpio_clear(dev, GPIO_11); -+ msleep(100); -+ cx23885_gpio_set(dev, GPIO_2); -+ cx23885_gpio_set(dev, GPIO_11); -+ break; -+ case CX23885_BOARD_DVBSKY_S950_CI: -+ case CX23885_BOARD_DVBSKY_C2800E_CI: -+ /* GPIO-0 INTA from CiMax, input -+ GPIO-1 reset CiMax, output, high active -+ GPIO-2 reset demod, output, low active -+ GPIO-3 to GPIO-10 data/addr for CAM -+ GPIO-11 ~CS0 to CiMax1 -+ GPIO-12 ~CS1 to CiMax2 -+ GPIO-13 ADL0 load LSB addr -+ GPIO-14 ADL1 load MSB addr -+ GPIO-15 ~RDY from CiMax -+ GPIO-17 ~RD to CiMax -+ GPIO-18 ~WR to CiMax -+ */ -+ cx_set(GP0_IO, 0x00060002); /* GPIO 1/2 as output */ -+ cx_clear(GP0_IO, 0x00010004); /*GPIO 0 as input*/ -+ mdelay(100);/* reset delay */ -+ cx_set(GP0_IO, 0x00060004); /* GPIO as out, reset high */ -+ cx_clear(GP0_IO, 0x00010002); -+ cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */ -+ /* GPIO-15 IN as ~ACK, rest as OUT */ -+ cx_write(MC417_OEN, 0x00001000); -+ /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */ -+ cx_write(MC417_RWD, 0x0000c300); -+ /* enable irq */ -+ cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/ -+ break; - } - } - -+static int cx23885_ir_patch(struct i2c_adapter *i2c, u8 reg, u8 mask) -+{ -+ struct i2c_msg msgs[2]; -+ u8 tx_buf[2], rx_buf[1]; -+ /* Write register address */ -+ tx_buf[0] = reg; -+ msgs[0].addr = 0x4c; -+ msgs[0].flags = 0; -+ msgs[0].len = 1; -+ msgs[0].buf = (char *) tx_buf; -+ /* Read data from register */ -+ msgs[1].addr = 0x4c; -+ msgs[1].flags = I2C_M_RD; -+ msgs[1].len = 1; -+ msgs[1].buf = (char *) rx_buf; -+ -+ i2c_transfer(i2c, msgs, 2); -+ -+ tx_buf[0] = reg; -+ tx_buf[1] = rx_buf[0] | mask; -+ msgs[0].addr = 0x4c; -+ msgs[0].flags = 0; -+ msgs[0].len = 2; -+ msgs[0].buf = (char *) tx_buf; -+ -+ return i2c_transfer(i2c, msgs, 1); -+} -+ - int cx23885_ir_init(struct cx23885_dev *dev) - { - static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = { -@@ -1482,6 +1609,23 @@ - v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, - ir_rx_pin_cfg_count, ir_rx_pin_cfg); - break; -+ case CX23885_BOARD_BST_PS8512: -+ case CX23885_BOARD_DVBSKY_S950: -+ case CX23885_BOARD_DVBSKY_S952: -+ case CX23885_BOARD_DVBSKY_S950_CI: -+ case CX23885_BOARD_DVBSKY_C2800E_CI: -+ case CX23885_BOARD_DVBSKY_T9580: -+ dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE); -+ if (dev->sd_ir == NULL) { -+ ret = -ENODEV; -+ break; -+ } -+ v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, -+ ir_rx_pin_cfg_count, ir_rx_pin_cfg); -+ -+ cx23885_ir_patch(&(dev->i2c_bus[2].i2c_adap),0x1f,0x80); -+ cx23885_ir_patch(&(dev->i2c_bus[2].i2c_adap),0x23,0x80); -+ break; - case CX23885_BOARD_HAUPPAUGE_HVR1250: - if (!enable_885_ir) - break; -@@ -1511,9 +1655,15 @@ - cx23888_ir_remove(dev); - dev->sd_ir = NULL; - break; -+ case CX23885_BOARD_BST_PS8512: -+ case CX23885_BOARD_DVBSKY_S950: -+ case CX23885_BOARD_DVBSKY_S952: -+ case CX23885_BOARD_DVBSKY_S950_CI: -+ case CX23885_BOARD_DVBSKY_C2800E_CI: -+ case CX23885_BOARD_DVBSKY_T9580: - case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: - case CX23885_BOARD_TEVII_S470: -- case CX23885_BOARD_HAUPPAUGE_HVR1250: -+ case CX23885_BOARD_HAUPPAUGE_HVR1250: - case CX23885_BOARD_MYGICA_X8507: - cx23885_irq_remove(dev, PCI_MSK_AV_CORE); - /* sd_ir is a duplicate pointer to the AV Core, just clear it */ -@@ -1556,6 +1706,12 @@ - if (dev->sd_ir) - cx23885_irq_add_enable(dev, PCI_MSK_IR); - break; -+ case CX23885_BOARD_BST_PS8512: -+ case CX23885_BOARD_DVBSKY_S950: -+ case CX23885_BOARD_DVBSKY_S952: -+ case CX23885_BOARD_DVBSKY_S950_CI: -+ case CX23885_BOARD_DVBSKY_C2800E_CI: -+ case CX23885_BOARD_DVBSKY_T9580: - case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: - case CX23885_BOARD_TEVII_S470: - case CX23885_BOARD_HAUPPAUGE_HVR1250: -@@ -1657,6 +1813,10 @@ - ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ - ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; - break; -+ case CX23885_BOARD_BST_PS8512: -+ case CX23885_BOARD_DVBSKY_S950: -+ case CX23885_BOARD_DVBSKY_S950_CI: -+ case CX23885_BOARD_DVBSKY_C2800E_CI: - case CX23885_BOARD_TEVII_S470: - case CX23885_BOARD_TEVII_S471: - case CX23885_BOARD_DVBWORLD_2005: -@@ -1694,6 +1854,22 @@ - ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ - ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; - break; -+ case CX23885_BOARD_DVBSKY_S952: -+ ts1->gen_ctrl_val = 0x5; /* Parallel */ -+ ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ -+ ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; -+ ts2->gen_ctrl_val = 0xe; /* Serial bus + punctured clock */ -+ ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ -+ ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; -+ break; -+ case CX23885_BOARD_DVBSKY_T9580: -+ ts1->gen_ctrl_val = 0x5; /* Parallel */ -+ ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ -+ ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; -+ ts2->gen_ctrl_val = 0x8; /* Serial bus */ -+ ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ -+ ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; -+ break; - case CX23885_BOARD_HAUPPAUGE_HVR1250: - case CX23885_BOARD_HAUPPAUGE_HVR1500: - case CX23885_BOARD_HAUPPAUGE_HVR1500Q: -@@ -1749,6 +1925,12 @@ - case CX23885_BOARD_MPX885: - case CX23885_BOARD_MYGICA_X8507: - case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: -+ case CX23885_BOARD_BST_PS8512: -+ case CX23885_BOARD_DVBSKY_S950: -+ case CX23885_BOARD_DVBSKY_S952: -+ case CX23885_BOARD_DVBSKY_S950_CI: -+ case CX23885_BOARD_DVBSKY_C2800E_CI: -+ case CX23885_BOARD_DVBSKY_T9580: - case CX23885_BOARD_AVERMEDIA_HC81R: - dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev, - &dev->i2c_bus[2].i2c_adap, -diff -urN a/drivers/media/pci/cx23885/cx23885-core.c b/drivers/media/pci/cx23885/cx23885-core.c ---- a/drivers/media/pci/cx23885/cx23885-core.c 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/pci/cx23885/cx23885-core.c 2013-05-03 17:36:31.000000000 +0800 -@@ -1909,6 +1909,10 @@ - (pci_status & PCI_MSK_GPIO0)) - handled += altera_ci_irq(dev); - -+ if (cx23885_boards[dev->board].ci_type == 3 && -+ (pci_status & PCI_MSK_GPIO0)) -+ handled += dvbsky_ci_slot_status(dev); -+ - if (ts1_status) { - if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) - handled += cx23885_irq_ts(ts1, ts1_status); -@@ -2144,6 +2148,8 @@ - cx23885_irq_add_enable(dev, PCI_MSK_GPIO1 | PCI_MSK_GPIO0); - break; - case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: -+ case CX23885_BOARD_DVBSKY_S950_CI: -+ case CX23885_BOARD_DVBSKY_C2800E_CI: - cx23885_irq_add_enable(dev, PCI_MSK_GPIO0); - break; - } -diff -urN a/drivers/media/pci/cx23885/cx23885-dvb.c b/drivers/media/pci/cx23885/cx23885-dvb.c ---- a/drivers/media/pci/cx23885/cx23885-dvb.c 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/pci/cx23885/cx23885-dvb.c 2013-05-03 17:38:34.000000000 +0800 -@@ -51,6 +51,8 @@ - #include "stv6110.h" - #include "lnbh24.h" - #include "cx24116.h" -+#include "m88ds3103.h" -+#include "m88dc2800.h" - #include "cimax2.h" - #include "lgs8gxx.h" - #include "netup-eeprom.h" -@@ -64,8 +66,8 @@ - #include "stv0367.h" - #include "drxk.h" - #include "mt2063.h" --#include "stv090x.h" --#include "stb6100.h" -+#include "stv090x.h" -+#include "stb6100.h" - #include "stb6100_cfg.h" - #include "tda10071.h" - #include "a8293.h" -@@ -500,42 +502,130 @@ - .if_khz = 5380, - }; - --static struct stv090x_config prof_8000_stv090x_config = { -- .device = STV0903, -- .demod_mode = STV090x_SINGLE, -- .clk_mode = STV090x_CLK_EXT, -- .xtal = 27000000, -- .address = 0x6A, -- .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED, -- .repeater_level = STV090x_RPTLEVEL_64, -- .adc1_range = STV090x_ADC_2Vpp, -- .diseqc_envelope_mode = false, -- -- .tuner_get_frequency = stb6100_get_frequency, -- .tuner_set_frequency = stb6100_set_frequency, -- .tuner_set_bandwidth = stb6100_set_bandwidth, -- .tuner_get_bandwidth = stb6100_get_bandwidth, --}; - --static struct stb6100_config prof_8000_stb6100_config = { -- .tuner_address = 0x60, -- .refclock = 27000000, --}; -- --static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) -+/* bst control */ -+int bst_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) - { - struct cx23885_tsport *port = fe->dvb->priv; - struct cx23885_dev *dev = port->dev; -+ -+ cx23885_gpio_enable(dev, GPIO_1, 1); -+ cx23885_gpio_enable(dev, GPIO_0, 1); -+ -+ switch (voltage) { -+ case SEC_VOLTAGE_13: -+ cx23885_gpio_set(dev, GPIO_1); -+ cx23885_gpio_clear(dev, GPIO_0); -+ break; -+ case SEC_VOLTAGE_18: -+ cx23885_gpio_set(dev, GPIO_1); -+ cx23885_gpio_set(dev, GPIO_0); -+ break; -+ case SEC_VOLTAGE_OFF: -+ cx23885_gpio_clear(dev, GPIO_1); -+ cx23885_gpio_clear(dev, GPIO_0); -+ break; -+ } -+ return 0; -+} - -- if (voltage == SEC_VOLTAGE_18) -- cx_write(MC417_RWD, 0x00001e00); -- else if (voltage == SEC_VOLTAGE_13) -- cx_write(MC417_RWD, 0x00001a00); -- else -- cx_write(MC417_RWD, 0x00001800); -+int dvbsky_set_voltage_sec(struct dvb_frontend *fe, fe_sec_voltage_t voltage) -+{ -+ struct cx23885_tsport *port = fe->dvb->priv; -+ struct cx23885_dev *dev = port->dev; -+ -+ cx23885_gpio_enable(dev, GPIO_12, 1); -+ cx23885_gpio_enable(dev, GPIO_13, 1); -+ -+ switch (voltage) { -+ case SEC_VOLTAGE_13: -+ cx23885_gpio_set(dev, GPIO_13); -+ cx23885_gpio_clear(dev, GPIO_12); -+ break; -+ case SEC_VOLTAGE_18: -+ cx23885_gpio_set(dev, GPIO_13); -+ cx23885_gpio_set(dev, GPIO_12); -+ break; -+ case SEC_VOLTAGE_OFF: -+ cx23885_gpio_clear(dev, GPIO_13); -+ cx23885_gpio_clear(dev, GPIO_12); -+ break; -+ } - return 0; - } - -+/* bestunar single dvb-s2 */ -+static struct m88ds3103_config bst_ds3103_config = { -+ .demod_address = 0x68, -+ .ci_mode = 0, -+ .pin_ctrl = 0x82, -+ .ts_mode = 0, -+ .set_voltage = bst_set_voltage, -+}; -+/* DVBSKY dual dvb-s2 */ -+static struct m88ds3103_config dvbsky_ds3103_config_pri = { -+ .demod_address = 0x68, -+ .ci_mode = 0, -+ .pin_ctrl = 0x82, -+ .ts_mode = 0, -+ .set_voltage = bst_set_voltage, -+}; -+static struct m88ds3103_config dvbsky_ds3103_config_sec = { -+ .demod_address = 0x68, -+ .ci_mode = 0, -+ .pin_ctrl = 0x82, -+ .ts_mode = 1, -+ .set_voltage = dvbsky_set_voltage_sec, -+}; -+ -+static struct m88ds3103_config dvbsky_ds3103_ci_config = { -+ .demod_address = 0x68, -+ .ci_mode = 2, -+ .pin_ctrl = 0x82, -+ .ts_mode = 0, -+}; -+ -+static struct m88dc2800_config dvbsky_dc2800_config = { -+ .demod_address = 0x1c, -+ .ts_mode = 3, -+}; -+ -+static struct stv090x_config prof_8000_stv090x_config = { -+ .device = STV0903, -+ .demod_mode = STV090x_SINGLE, -+ .clk_mode = STV090x_CLK_EXT, -+ .xtal = 27000000, -+ .address = 0x6A, -+ .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED, -+ .repeater_level = STV090x_RPTLEVEL_64, -+ .adc1_range = STV090x_ADC_2Vpp, -+ .diseqc_envelope_mode = false, -+ -+ .tuner_get_frequency = stb6100_get_frequency, -+ .tuner_set_frequency = stb6100_set_frequency, -+ .tuner_set_bandwidth = stb6100_set_bandwidth, -+ .tuner_get_bandwidth = stb6100_get_bandwidth, -+}; -+ -+static struct stb6100_config prof_8000_stb6100_config = { -+ .tuner_address = 0x60, -+ .refclock = 27000000, -+}; -+ -+static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) -+{ -+ struct cx23885_tsport *port = fe->dvb->priv; -+ struct cx23885_dev *dev = port->dev; -+ -+ if (voltage == SEC_VOLTAGE_18) -+ cx_write(MC417_RWD, 0x00001e00); -+ else if (voltage == SEC_VOLTAGE_13) -+ cx_write(MC417_RWD, 0x00001a00); -+ else -+ cx_write(MC417_RWD, 0x00001800); -+ return 0; -+} -+ - static int cx23885_dvb_set_frontend(struct dvb_frontend *fe) - { - struct dtv_frontend_properties *p = &fe->dtv_property_cache; -@@ -1250,23 +1340,79 @@ - &tevii_ds3000_config, - &i2c_bus->i2c_adap); - break; -- case CX23885_BOARD_PROF_8000: -- i2c_bus = &dev->i2c_bus[0]; -+ case CX23885_BOARD_BST_PS8512: -+ case CX23885_BOARD_DVBSKY_S950: -+ i2c_bus = &dev->i2c_bus[1]; -+ fe0->dvb.frontend = dvb_attach(m88ds3103_attach, -+ &bst_ds3103_config, -+ &i2c_bus->i2c_adap); -+ break; -+ -+ case CX23885_BOARD_DVBSKY_S952: -+ switch (port->nr) { -+ /* port B */ -+ case 1: -+ i2c_bus = &dev->i2c_bus[1]; -+ fe0->dvb.frontend = dvb_attach(m88ds3103_attach, -+ &dvbsky_ds3103_config_pri, -+ &i2c_bus->i2c_adap); -+ break; -+ /* port C */ -+ case 2: -+ i2c_bus = &dev->i2c_bus[0]; -+ fe0->dvb.frontend = dvb_attach(m88ds3103_attach, -+ &dvbsky_ds3103_config_sec, -+ &i2c_bus->i2c_adap); -+ break; -+ } -+ break; - -- fe0->dvb.frontend = dvb_attach(stv090x_attach, -- &prof_8000_stv090x_config, -- &i2c_bus->i2c_adap, -- STV090x_DEMODULATOR_0); -- if (fe0->dvb.frontend != NULL) { -- if (!dvb_attach(stb6100_attach, -- fe0->dvb.frontend, -- &prof_8000_stb6100_config, -- &i2c_bus->i2c_adap)) -- goto frontend_detach; -+ case CX23885_BOARD_DVBSKY_S950_CI: -+ i2c_bus = &dev->i2c_bus[1]; -+ fe0->dvb.frontend = dvb_attach(m88ds3103_attach, -+ &dvbsky_ds3103_ci_config, -+ &i2c_bus->i2c_adap); -+ break; -+ -+ case CX23885_BOARD_DVBSKY_C2800E_CI: -+ i2c_bus = &dev->i2c_bus[1]; -+ fe0->dvb.frontend = dvb_attach(m88dc2800_attach, -+ &dvbsky_dc2800_config, -+ &i2c_bus->i2c_adap); -+ break; - -- fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage; -+ case CX23885_BOARD_DVBSKY_T9580: -+ switch (port->nr) { -+ /* port B */ -+ case 1: -+ i2c_bus = &dev->i2c_bus[1]; -+ fe0->dvb.frontend = dvb_attach(m88ds3103_attach, -+ &dvbsky_ds3103_config_pri, -+ &i2c_bus->i2c_adap); -+ break; -+ /* port C */ -+ case 2: -+ break; - } - break; -+ -+ case CX23885_BOARD_PROF_8000: -+ i2c_bus = &dev->i2c_bus[0]; -+ -+ fe0->dvb.frontend = dvb_attach(stv090x_attach, -+ &prof_8000_stv090x_config, -+ &i2c_bus->i2c_adap, -+ STV090x_DEMODULATOR_0); -+ if (fe0->dvb.frontend != NULL) { -+ if (!dvb_attach(stb6100_attach, -+ fe0->dvb.frontend, -+ &prof_8000_stb6100_config, -+ &i2c_bus->i2c_adap)) -+ goto frontend_detach; -+ -+ fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage; -+ } -+ break; - case CX23885_BOARD_HAUPPAUGE_HVR4400: - i2c_bus = &dev->i2c_bus[0]; - fe0->dvb.frontend = dvb_attach(tda10071_attach, -@@ -1325,7 +1471,7 @@ - printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n", - port->nr, port->frontends.adapter.proposed_mac); - -- netup_ci_init(port); -+ netup_ci_init(port, false); - break; - } - case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: { -@@ -1352,6 +1498,41 @@ - memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6); - break; - } -+ case CX23885_BOARD_BST_PS8512: -+ case CX23885_BOARD_DVBSKY_S950: -+ case CX23885_BOARD_DVBSKY_S952: -+ case CX23885_BOARD_DVBSKY_T9580:{ -+ u8 eeprom[256]; /* 24C02 i2c eeprom */ -+ -+ if(port->nr > 2) -+ break; -+ -+ dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; -+ tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom)); -+ printk(KERN_INFO "DVBSKY PCIe MAC= %pM\n", eeprom + 0xc0+(port->nr-1)*8); -+ memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xc0 + -+ (port->nr-1)*8, 6); -+ break; -+ } -+ case CX23885_BOARD_DVBSKY_S950_CI: { -+ u8 eeprom[256]; /* 24C02 i2c eeprom */ -+ -+ if(port->nr > 2) -+ break; -+ -+ dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; -+ tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom)); -+ printk(KERN_INFO "DVBSKY PCIe MAC= %pM\n", eeprom + 0xc0+(port->nr-1)*8); -+ memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xc0 + -+ (port->nr-1)*8, 6); -+ -+ netup_ci_init(port, true); -+ break; -+ } -+ case CX23885_BOARD_DVBSKY_C2800E_CI: { -+ netup_ci_init(port, true); -+ break; -+ } - } - - return ret; -@@ -1434,6 +1615,8 @@ - - switch (port->dev->board) { - case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: -+ case CX23885_BOARD_DVBSKY_S950_CI: -+ case CX23885_BOARD_DVBSKY_C2800E_CI: - netup_ci_exit(port); - break; - case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: -diff -urN a/drivers/media/pci/cx23885/cx23885.h b/drivers/media/pci/cx23885/cx23885.h ---- a/drivers/media/pci/cx23885/cx23885.h 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/pci/cx23885/cx23885.h 2013-05-03 17:14:20.000000000 +0800 -@@ -94,6 +94,14 @@ - #define CX23885_BOARD_HAUPPAUGE_HVR4400 38 - #define CX23885_BOARD_AVERMEDIA_HC81R 39 - -+#define CX23885_BOARD_BASE_INDEX 40 -+#define CX23885_BOARD_BST_PS8512 (CX23885_BOARD_BASE_INDEX) -+#define CX23885_BOARD_DVBSKY_S952 (CX23885_BOARD_BASE_INDEX+1) -+#define CX23885_BOARD_DVBSKY_S950 (CX23885_BOARD_BASE_INDEX+2) -+#define CX23885_BOARD_DVBSKY_S950_CI (CX23885_BOARD_BASE_INDEX+3) -+#define CX23885_BOARD_DVBSKY_C2800E_CI (CX23885_BOARD_BASE_INDEX+4) -+#define CX23885_BOARD_DVBSKY_T9580 (CX23885_BOARD_BASE_INDEX+5) -+ - #define GPIO_0 0x00000001 - #define GPIO_1 0x00000002 - #define GPIO_2 0x00000004 -@@ -231,7 +239,7 @@ - */ - u32 clk_freq; - struct cx23885_input input[MAX_CX23885_INPUT]; -- int ci_type; /* for NetUP */ -+ int ci_type; /* 1 and 2 for NetUP, 3 for DVBSky. */ - /* Force bottom field first during DMA (888 workaround) */ - u32 force_bff; - }; -diff -urN a/drivers/media/pci/cx23885/cx23885-input.c b/drivers/media/pci/cx23885/cx23885-input.c ---- a/drivers/media/pci/cx23885/cx23885-input.c 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/pci/cx23885/cx23885-input.c 2013-05-03 17:42:09.000000000 +0800 -@@ -89,6 +89,12 @@ - case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: - case CX23885_BOARD_TEVII_S470: - case CX23885_BOARD_HAUPPAUGE_HVR1250: -+ case CX23885_BOARD_BST_PS8512: -+ case CX23885_BOARD_DVBSKY_S950: -+ case CX23885_BOARD_DVBSKY_S952: -+ case CX23885_BOARD_DVBSKY_S950_CI: -+ case CX23885_BOARD_DVBSKY_C2800E_CI: -+ case CX23885_BOARD_DVBSKY_T9580: - case CX23885_BOARD_MYGICA_X8507: - /* - * The only boards we handle right now. However other boards -@@ -141,6 +147,12 @@ - case CX23885_BOARD_HAUPPAUGE_HVR1850: - case CX23885_BOARD_HAUPPAUGE_HVR1290: - case CX23885_BOARD_HAUPPAUGE_HVR1250: -+ case CX23885_BOARD_BST_PS8512: -+ case CX23885_BOARD_DVBSKY_S950: -+ case CX23885_BOARD_DVBSKY_S952: -+ case CX23885_BOARD_DVBSKY_S950_CI: -+ case CX23885_BOARD_DVBSKY_C2800E_CI: -+ case CX23885_BOARD_DVBSKY_T9580: - case CX23885_BOARD_MYGICA_X8507: - /* - * The IR controller on this board only returns pulse widths. -@@ -291,6 +303,18 @@ - /* A guess at the remote */ - rc_map = RC_MAP_TEVII_NEC; - break; -+ case CX23885_BOARD_BST_PS8512: -+ case CX23885_BOARD_DVBSKY_S950: -+ case CX23885_BOARD_DVBSKY_S952: -+ case CX23885_BOARD_DVBSKY_S950_CI: -+ case CX23885_BOARD_DVBSKY_C2800E_CI: -+ case CX23885_BOARD_DVBSKY_T9580: -+ /* Integrated CX2388[58] IR controller */ -+ driver_type = RC_DRIVER_IR_RAW; -+ allowed_protos = RC_BIT_ALL; -+ /* A guess at the remote */ -+ rc_map = RC_MAP_DVBSKY; -+ break; - case CX23885_BOARD_MYGICA_X8507: - /* Integrated CX23885 IR controller */ - driver_type = RC_DRIVER_IR_RAW; -diff -urN a/drivers/media/pci/cx23885/Kconfig b/drivers/media/pci/cx23885/Kconfig ---- a/drivers/media/pci/cx23885/Kconfig 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/pci/cx23885/Kconfig 2013-05-03 17:43:05.000000000 +0800 -@@ -23,6 +23,8 @@ - select DVB_STB6100 if MEDIA_SUBDRV_AUTOSELECT - select DVB_STV6110 if MEDIA_SUBDRV_AUTOSELECT - select DVB_CX24116 if MEDIA_SUBDRV_AUTOSELECT -+ select DVB_M88DS3103 if MEDIA_SUBDRV_AUTOSELECT -+ select DVB_M88DC2800 if MEDIA_SUBDRV_AUTOSELECT - select DVB_STV0900 if MEDIA_SUBDRV_AUTOSELECT - select DVB_DS3000 if MEDIA_SUBDRV_AUTOSELECT - select DVB_TS2020 if MEDIA_SUBDRV_AUTOSELECT -diff -urN a/drivers/media/pci/cx88/cx88-cards.c b/drivers/media/pci/cx88/cx88-cards.c ---- a/drivers/media/pci/cx88/cx88-cards.c 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/pci/cx88/cx88-cards.c 2013-05-03 17:06:55.000000000 +0800 -@@ -2309,6 +2309,18 @@ - } }, - .mpeg = CX88_MPEG_DVB, - }, -+ [CX88_BOARD_BST_PS8312] = { -+ .name = "Bestunar PS8312 DVB-S/S2", -+ .tuner_type = UNSET, -+ .radio_type = UNSET, -+ .tuner_addr = ADDR_UNSET, -+ .radio_addr = ADDR_UNSET, -+ .input = { { -+ .type = CX88_VMUX_DVB, -+ .vmux = 0, -+ } }, -+ .mpeg = CX88_MPEG_DVB, -+ }, - }; - - /* ------------------------------------------------------------------ */ -@@ -2813,6 +2825,10 @@ - .subvendor = 0x1822, - .subdevice = 0x0023, - .card = CX88_BOARD_TWINHAN_VP1027_DVBS, -+ }, { -+ .subvendor = 0x14f1, -+ .subdevice = 0x8312, -+ .card = CX88_BOARD_BST_PS8312, - }, - }; - -@@ -3547,6 +3563,12 @@ - cx_write(MO_SRST_IO, 1); - msleep(100); - break; -+ case CX88_BOARD_BST_PS8312: -+ cx_write(MO_GP1_IO, 0x808000); -+ msleep(100); -+ cx_write(MO_GP1_IO, 0x808080); -+ msleep(100); -+ break; - } /*end switch() */ - - -diff -urN a/drivers/media/pci/cx88/cx88-dvb.c b/drivers/media/pci/cx88/cx88-dvb.c ---- a/drivers/media/pci/cx88/cx88-dvb.c 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/pci/cx88/cx88-dvb.c 2013-05-03 17:09:09.000000000 +0800 -@@ -54,6 +54,7 @@ - #include "stv0288.h" - #include "stb6000.h" - #include "cx24116.h" -+#include "m88ds3103.h" - #include "stv0900.h" - #include "stb6100.h" - #include "stb6100_proc.h" -@@ -459,6 +460,56 @@ - return core->prev_set_voltage(fe, voltage); - return 0; - } -+/*CX88_BOARD_BST_PS8312*/ -+static int bst_dvbs_set_voltage(struct dvb_frontend *fe, -+ fe_sec_voltage_t voltage) -+{ -+ struct cx8802_dev *dev= fe->dvb->priv; -+ struct cx88_core *core = dev->core; -+ -+ cx_write(MO_GP1_IO, 0x111111); -+ switch (voltage) { -+ case SEC_VOLTAGE_13: -+ cx_write(MO_GP1_IO, 0x020200); -+ break; -+ case SEC_VOLTAGE_18: -+ cx_write(MO_GP1_IO, 0x020202); -+ break; -+ case SEC_VOLTAGE_OFF: -+ cx_write(MO_GP1_IO, 0x111100); -+ break; -+ } -+ -+ if (core->prev_set_voltage) -+ return core->prev_set_voltage(fe, voltage); -+ return 0; -+} -+ -+static int bst_dvbs_set_voltage_v2(struct dvb_frontend *fe, -+ fe_sec_voltage_t voltage) -+{ -+ struct cx8802_dev *dev= fe->dvb->priv; -+ struct cx88_core *core = dev->core; -+ -+ cx_write(MO_GP1_IO, 0x111101); -+ switch (voltage) { -+ case SEC_VOLTAGE_13: -+ cx_write(MO_GP1_IO, 0x020200); -+ break; -+ case SEC_VOLTAGE_18: -+ -+ cx_write(MO_GP1_IO, 0x020202); -+ break; -+ case SEC_VOLTAGE_OFF: -+ -+ cx_write(MO_GP1_IO, 0x111110); -+ break; -+ } -+ -+ if (core->prev_set_voltage) -+ return core->prev_set_voltage(fe, voltage); -+ return 0; -+} - - static int vp1027_set_voltage(struct dvb_frontend *fe, - fe_sec_voltage_t voltage) -@@ -706,6 +757,11 @@ - .clk_out_div = 1, - }; - -+static struct m88ds3103_config dvbsky_ds3103_config = { -+ .demod_address = 0x68, -+ .set_ts_params = ds3000_set_ts_param, -+}; -+ - static const struct stv0900_config prof_7301_stv0900_config = { - .demod_address = 0x6a, - /* demod_mode = 0,*/ -@@ -1477,6 +1533,35 @@ - &tevii_ts2020_config, &core->i2c_adap); - fe0->dvb.frontend->ops.set_voltage = - tevii_dvbs_set_voltage; -+ } -+ break; -+ case CX88_BOARD_BST_PS8312: -+ fe0->dvb.frontend = dvb_attach(m88ds3103_attach, -+ &dvbsky_ds3103_config, -+ &core->i2c_adap); -+ if (fe0->dvb.frontend != NULL){ -+ int ret; -+ u8 b0[] = { 0x60 }; -+ u8 b1[2] = { 0 }; -+ struct i2c_msg msg[] = { -+ { -+ .addr = 0x50, -+ .flags = 0, -+ .buf = b0, -+ .len = 1 -+ }, { -+ .addr = 0x50, -+ .flags = I2C_M_RD, -+ .buf = b1, -+ .len = 2 -+ } -+ }; -+ ret = i2c_transfer(&core->i2c_adap, msg, 2); -+ printk("PS8312: config = %02x, %02x", b1[0],b1[1]); -+ if(b1[0] == 0xaa) -+ fe0->dvb.frontend->ops.set_voltage = bst_dvbs_set_voltage_v2; -+ else -+ fe0->dvb.frontend->ops.set_voltage = bst_dvbs_set_voltage; - } - break; - case CX88_BOARD_OMICOM_SS4_PCI: -diff -urN a/drivers/media/pci/cx88/cx88.h b/drivers/media/pci/cx88/cx88.h ---- a/drivers/media/pci/cx88/cx88.h 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/pci/cx88/cx88.h 2013-05-03 17:05:57.000000000 +0800 -@@ -238,6 +238,7 @@ - #define CX88_BOARD_WINFAST_DTV1800H_XC4000 88 - #define CX88_BOARD_WINFAST_TV2000_XP_GLOBAL_6F36 89 - #define CX88_BOARD_WINFAST_TV2000_XP_GLOBAL_6F43 90 -+#define CX88_BOARD_BST_PS8312 91 - - enum cx88_itype { - CX88_VMUX_COMPOSITE1 = 1, -diff -urN a/drivers/media/pci/cx88/cx88-input.c b/drivers/media/pci/cx88/cx88-input.c ---- a/drivers/media/pci/cx88/cx88-input.c 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/pci/cx88/cx88-input.c 2013-01-26 14:52:03.000000000 +0800 -@@ -419,6 +419,10 @@ - rc_type = RC_BIT_NEC; - ir->sampling = 0xff00; /* address */ - break; -+ case CX88_BOARD_BST_PS8312: -+ ir_codes = RC_MAP_DVBSKY; -+ ir->sampling = 0xff00; /* address */ -+ break; - } - - if (!ir_codes) { -diff -urN a/drivers/media/pci/cx88/Kconfig b/drivers/media/pci/cx88/Kconfig ---- a/drivers/media/pci/cx88/Kconfig 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/pci/cx88/Kconfig 2013-05-03 17:10:41.000000000 +0800 -@@ -57,6 +57,7 @@ - select DVB_ISL6421 if MEDIA_SUBDRV_AUTOSELECT - select DVB_S5H1411 if MEDIA_SUBDRV_AUTOSELECT - select DVB_CX24116 if MEDIA_SUBDRV_AUTOSELECT -+ select DVB_M88DS3103 if MEDIA_SUBDRV_AUTOSELECT - select DVB_STV0299 if MEDIA_SUBDRV_AUTOSELECT - select DVB_STV0288 if MEDIA_SUBDRV_AUTOSELECT - select DVB_STB6000 if MEDIA_SUBDRV_AUTOSELECT -diff -urN a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile ---- a/drivers/media/rc/keymaps/Makefile 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/rc/keymaps/Makefile 2013-05-03 17:43:41.000000000 +0800 -@@ -27,6 +27,7 @@ - rc-dm1105-nec.o \ - rc-dntv-live-dvb-t.o \ - rc-dntv-live-dvbt-pro.o \ -+ rc-dvbsky.o \ - rc-em-terratec.o \ - rc-encore-enltv2.o \ - rc-encore-enltv.o \ -diff -urN a/drivers/media/rc/keymaps/rc-dvbsky.c b/drivers/media/rc/keymaps/rc-dvbsky.c ---- a/drivers/media/rc/keymaps/rc-dvbsky.c 1970-01-01 08:00:00.000000000 +0800 -+++ b/drivers/media/rc/keymaps/rc-dvbsky.c 2013-01-26 14:52:49.000000000 +0800 -@@ -0,0 +1,78 @@ -+/* rc-dvbsky.c - Keytable for Dvbsky Remote Controllers -+ * -+ * keymap imported from ir-keymaps.c -+ * -+ * -+ * Copyright (c) 2010-2012 by Nibble Max -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ */ -+ -+#include -+#include -+/* -+ * This table contains the complete RC5 code, instead of just the data part -+ */ -+ -+static struct rc_map_table rc5_dvbsky[] = { -+ { 0x0000, KEY_0 }, -+ { 0x0001, KEY_1 }, -+ { 0x0002, KEY_2 }, -+ { 0x0003, KEY_3 }, -+ { 0x0004, KEY_4 }, -+ { 0x0005, KEY_5 }, -+ { 0x0006, KEY_6 }, -+ { 0x0007, KEY_7 }, -+ { 0x0008, KEY_8 }, -+ { 0x0009, KEY_9 }, -+ { 0x000a, KEY_MUTE }, -+ { 0x000d, KEY_OK }, -+ { 0x000b, KEY_STOP }, -+ { 0x000c, KEY_EXIT }, -+ { 0x000e, KEY_CAMERA }, /*Snap shot*/ -+ { 0x000f, KEY_SUBTITLE }, /*PIP*/ -+ { 0x0010, KEY_VOLUMEUP }, -+ { 0x0011, KEY_VOLUMEDOWN }, -+ { 0x0012, KEY_FAVORITES }, -+ { 0x0013, KEY_LIST }, /*Info*/ -+ { 0x0016, KEY_PAUSE }, -+ { 0x0017, KEY_PLAY }, -+ { 0x001f, KEY_RECORD }, -+ { 0x0020, KEY_CHANNELDOWN }, -+ { 0x0021, KEY_CHANNELUP }, -+ { 0x0025, KEY_POWER2 }, -+ { 0x0026, KEY_REWIND }, -+ { 0x0027, KEY_FASTFORWARD }, -+ { 0x0029, KEY_LAST }, -+ { 0x002b, KEY_MENU }, -+ { 0x002c, KEY_EPG }, -+ { 0x002d, KEY_ZOOM }, -+}; -+ -+static struct rc_map_list rc5_dvbsky_map = { -+ .map = { -+ .scan = rc5_dvbsky, -+ .size = ARRAY_SIZE(rc5_dvbsky), -+ .rc_type = RC_TYPE_RC5, -+ .name = RC_MAP_DVBSKY, -+ } -+}; -+ -+static int __init init_rc_map_rc5_dvbsky(void) -+{ -+ return rc_map_register(&rc5_dvbsky_map); -+} -+ -+static void __exit exit_rc_map_rc5_dvbsky(void) -+{ -+ rc_map_unregister(&rc5_dvbsky_map); -+} -+ -+module_init(init_rc_map_rc5_dvbsky) -+module_exit(exit_rc_map_rc5_dvbsky) -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Nibble Max "); -diff -urN a/drivers/media/usb/dvb-usb-v2/dvbsky.c b/drivers/media/usb/dvb-usb-v2/dvbsky.c ---- a/drivers/media/usb/dvb-usb-v2/dvbsky.c 1970-01-01 08:00:00.000000000 +0800 -+++ b/drivers/media/usb/dvb-usb-v2/dvbsky.c 2013-05-03 17:47:38.000000000 +0800 -@@ -0,0 +1,665 @@ -+/* -+ * Driver for DVBSky USB2.0 receiver -+ * -+ * Copyright (C) 2013 Max nibble -+ * -+ * CIMax code is copied and modified from: -+ * CIMax2(R) SP2 driver in conjunction with NetUp Dual DVB-S2 CI card -+ * Copyright (C) 2009 NetUP Inc. -+ * Copyright (C) 2009 Igor M. Liplianin -+ * Copyright (C) 2009 Abylay Ospan -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#include "dvb_ca_en50221.h" -+#include "dvb_usb.h" -+#include "m88ds3103.h" -+ -+static int dvbsky_debug; -+module_param(dvbsky_debug, int, 0644); -+MODULE_PARM_DESC(dvbsky_debug, "Activates dvbsky usb debugging (default:0)"); -+ -+#define DVBSKY_CI_CTL 0x04 -+#define DVBSKY_CI_RD 1 -+ -+#define dprintk(args...) \ -+ do { \ -+ if (dvbsky_debug) \ -+ printk(KERN_INFO "dvbsky_usb: " args); \ -+ } while (0) -+ -+DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); -+ -+struct dvbsky_state { -+ struct mutex stream_mutex; -+ u8 has_ci; -+ u8 ci_attached; -+ struct dvb_ca_en50221 ci; -+ unsigned long next_status_checked_time; -+ u8 ci_i2c_addr; -+ u8 current_ci_flag; -+ int ci_status; -+}; -+ -+static int dvbsky_stream_ctrl(struct dvb_usb_device *d, u8 onoff) -+{ -+ struct dvbsky_state *state = d_to_priv(d); -+ int ret; -+ u8 obuf_pre[3] = { 0x37, 0, 0 }; -+ u8 obuf_post[3] = { 0x36, 3, 0 }; -+ dprintk("%s() -off \n", __func__); -+ mutex_lock(&state->stream_mutex); -+ ret = dvb_usbv2_generic_write(d, obuf_pre, 3); -+ if (!ret && onoff) { -+ msleep(10); -+ ret = dvb_usbv2_generic_write(d, obuf_post, 3); -+ dprintk("%s() -on \n", __func__); -+ } -+ mutex_unlock(&state->stream_mutex); -+ return ret; -+} -+ -+/* CI opertaions */ -+static int dvbsky_ci_read_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg, -+ u8 *buf, int len) -+{ -+ int ret; -+ struct i2c_msg msg[] = { -+ { -+ .addr = addr, -+ .flags = 0, -+ .buf = ®, -+ .len = 1 -+ }, { -+ .addr = addr, -+ .flags = I2C_M_RD, -+ .buf = buf, -+ .len = len -+ } -+ }; -+ -+ ret = i2c_transfer(i2c_adap, msg, 2); -+ -+ if (ret != 2) { -+ dprintk("%s: error, Reg = 0x%02x, Status = %d\n", __func__, reg, ret); -+ return -1; -+ } -+ return 0; -+} -+ -+static int dvbsky_ci_write_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg, -+ u8 *buf, int len) -+{ -+ int ret; -+ u8 buffer[len + 1]; -+ -+ struct i2c_msg msg = { -+ .addr = addr, -+ .flags = 0, -+ .buf = &buffer[0], -+ .len = len + 1 -+ }; -+ -+ buffer[0] = reg; -+ memcpy(&buffer[1], buf, len); -+ -+ ret = i2c_transfer(i2c_adap, &msg, 1); -+ -+ if (ret != 1) { -+ dprintk("%s: error, Reg=[0x%02x], Status=%d\n", __func__, reg, ret); -+ return -1; -+ } -+ return 0; -+} -+ -+static int dvbsky_ci_op_cam(struct dvb_ca_en50221 *ci, int slot, -+ u8 flag, u8 read, int addr, u8 data) -+{ -+ struct dvb_usb_device *d = ci->data; -+ struct dvbsky_state *state = d_to_priv(d); -+ u8 store; -+ int ret; -+ u8 command[4], respond[2], command_size, respond_size; -+ -+ /*dprintk("%s()\n", __func__);*/ -+ if (0 != slot) -+ return -EINVAL; -+ -+ if (state->current_ci_flag != flag) { -+ ret = dvbsky_ci_read_i2c(&d->i2c_adap, state->ci_i2c_addr, -+ 0, &store, 1); -+ if (ret != 0) -+ return ret; -+ -+ store &= ~0x0c; -+ store |= flag; -+ -+ ret = dvbsky_ci_write_i2c(&d->i2c_adap, state->ci_i2c_addr, -+ 0, &store, 1); -+ if (ret != 0) -+ return ret; -+ } -+ state->current_ci_flag = flag; -+ -+ command[1] = (u8)((addr >> 8) & 0xff); /*high part of address*/ -+ command[2] = (u8)(addr & 0xff); /*low part of address*/ -+ if (read) { -+ command[0] = 0x71; -+ command_size = 3; -+ respond_size = 2; -+ } else { -+ command[0] = 0x70; -+ command[3] = data; -+ command_size = 4; -+ respond_size = 1; -+ } -+ ret = dvb_usbv2_generic_rw(d, command, command_size, respond, respond_size); -+ -+ return (read) ? respond[1] : 0; -+} -+ -+static int dvbsky_ci_read_attribute_mem(struct dvb_ca_en50221 *ci, -+ int slot, int addr) -+{ -+ return dvbsky_ci_op_cam(ci, slot, 0, DVBSKY_CI_RD, addr, 0); -+} -+ -+static int dvbsky_ci_write_attribute_mem(struct dvb_ca_en50221 *ci, -+ int slot, int addr, u8 data) -+{ -+ return dvbsky_ci_op_cam(ci, slot, 0, 0, addr, data); -+} -+ -+static int dvbsky_ci_read_cam_ctl(struct dvb_ca_en50221 *ci, int slot, u8 addr) -+{ -+ return dvbsky_ci_op_cam(ci, slot, DVBSKY_CI_CTL, DVBSKY_CI_RD, addr, 0); -+} -+ -+static int dvbsky_ci_write_cam_ctl(struct dvb_ca_en50221 *ci, int slot, -+ u8 addr, u8 data) -+{ -+ return dvbsky_ci_op_cam(ci, slot, DVBSKY_CI_CTL, 0, addr, data); -+} -+ -+static int dvbsky_ci_slot_reset(struct dvb_ca_en50221 *ci, int slot) -+{ -+ struct dvb_usb_device *d = ci->data; -+ struct dvbsky_state *state = d_to_priv(d); -+ u8 buf = 0x80; -+ int ret; -+ dprintk("%s() slot=%d\n", __func__, slot); -+ -+ if (0 != slot) -+ return -EINVAL; -+ -+ udelay(500); -+ ret = dvbsky_ci_write_i2c(&d->i2c_adap, state->ci_i2c_addr, -+ 0, &buf, 1); -+ -+ if (ret != 0) -+ return ret; -+ -+ udelay(500); -+ -+ buf = 0x00; -+ ret = dvbsky_ci_write_i2c(&d->i2c_adap, state->ci_i2c_addr, -+ 0, &buf, 1); -+ msleep(1000); -+ dprintk("%s() slot=%d complete\n", __func__, slot); -+ return 0; -+ -+} -+ -+static int dvbsky_ci_slot_shutdown(struct dvb_ca_en50221 *ci, int slot) -+{ -+ /* not implemented */ -+ dprintk("%s()\n", __func__); -+ return 0; -+} -+ -+static int dvbsky_ci_slot_ts_enable(struct dvb_ca_en50221 *ci, int slot) -+{ -+ struct dvb_usb_device *d = ci->data; -+ struct dvbsky_state *state = d_to_priv(d); -+ u8 buf; -+ int ret; -+ -+ dprintk("%s()\n", __func__); -+ if (0 != slot) -+ return -EINVAL; -+ -+ dvbsky_ci_read_i2c(&d->i2c_adap, state->ci_i2c_addr, -+ 0, &buf, 1); -+ buf |= 0x60; -+ -+ ret = dvbsky_ci_write_i2c(&d->i2c_adap, state->ci_i2c_addr, -+ 0, &buf, 1); -+ return ret; -+} -+ -+static int dvbsky_ci_poll_slot_status(struct dvb_ca_en50221 *ci, int slot, -+ int open) -+{ -+ struct dvb_usb_device *d = ci->data; -+ struct dvbsky_state *state = d_to_priv(d); -+ int ret = 0; -+ u8 buf = 0; -+ /*dprintk("%s()\n", __func__);*/ -+ -+ /* CAM module INSERT/REMOVE processing. slow operation because of i2c -+ * transfers */ -+ if (time_after(jiffies, state->next_status_checked_time)) { -+ ret = dvbsky_ci_read_i2c(&d->i2c_adap, state->ci_i2c_addr, -+ 0, &buf, 1); -+ -+ /*dprintk("%s() status=%x\n", __func__, buf);*/ -+ -+ state->next_status_checked_time = jiffies -+ + msecs_to_jiffies(1000); -+ -+ if (ret != 0) -+ return 0; -+ -+ if (buf & 1) { -+ state->ci_status = DVB_CA_EN50221_POLL_CAM_PRESENT | -+ DVB_CA_EN50221_POLL_CAM_READY; -+ } -+ else -+ state->ci_status = 0; -+ } -+ /*dprintk("%s() ret=%x\n", __func__, state->ci_status);*/ -+ return state->ci_status; -+} -+ -+static int dvbsky_ci_init(struct dvb_usb_device *d) -+{ -+ struct dvbsky_state *state = d_to_priv(d); -+ int ret; -+ u8 cimax_init[34] = { -+ 0x00, /* module A control*/ -+ 0x00, /* auto select mask high A */ -+ 0x00, /* auto select mask low A */ -+ 0x00, /* auto select pattern high A */ -+ 0x00, /* auto select pattern low A */ -+ 0x44, /* memory access time A */ -+ 0x00, /* invert input A */ -+ 0x00, /* RFU */ -+ 0x00, /* RFU */ -+ 0x00, /* module B control*/ -+ 0x00, /* auto select mask high B */ -+ 0x00, /* auto select mask low B */ -+ 0x00, /* auto select pattern high B */ -+ 0x00, /* auto select pattern low B */ -+ 0x44, /* memory access time B */ -+ 0x00, /* invert input B */ -+ 0x00, /* RFU */ -+ 0x00, /* RFU */ -+ 0x00, /* auto select mask high Ext */ -+ 0x00, /* auto select mask low Ext */ -+ 0x00, /* auto select pattern high Ext */ -+ 0x00, /* auto select pattern low Ext */ -+ 0x00, /* RFU */ -+ 0x02, /* destination - module A */ -+ 0x01, /* power on (use it like store place) */ -+ 0x00, /* RFU */ -+ 0x00, /* int status read only */ -+ 0x00, /* Max: Disable the interrupt in USB solution.*/ -+ 0x05, /* EXTINT=active-high, INT=push-pull */ -+ 0x00, /* USCG1 */ -+ 0x04, /* ack active low */ -+ 0x00, /* LOCK = 0 */ -+ 0x22, /* serial mode, rising in, rising out, MSB first*/ -+ 0x00 /* synchronization */ -+ }; -+ dprintk("%s()\n", __func__); -+ state->current_ci_flag = 0xff; -+ state->ci_status = 0; -+ state->next_status_checked_time = jiffies + msecs_to_jiffies(1000); -+ state->ci_i2c_addr = 0x40; -+ -+ state->ci.owner = THIS_MODULE; -+ state->ci.read_attribute_mem = dvbsky_ci_read_attribute_mem; -+ state->ci.write_attribute_mem = dvbsky_ci_write_attribute_mem; -+ state->ci.read_cam_control = dvbsky_ci_read_cam_ctl; -+ state->ci.write_cam_control = dvbsky_ci_write_cam_ctl; -+ state->ci.slot_reset = dvbsky_ci_slot_reset; -+ state->ci.slot_shutdown = dvbsky_ci_slot_shutdown; -+ state->ci.slot_ts_enable = dvbsky_ci_slot_ts_enable; -+ state->ci.poll_slot_status = dvbsky_ci_poll_slot_status; -+ state->ci.data = d; -+ -+ ret = dvbsky_ci_write_i2c(&d->i2c_adap, state->ci_i2c_addr, -+ 0, &cimax_init[0], 34); -+ /* lock registers */ -+ ret |= dvbsky_ci_write_i2c(&d->i2c_adap, state->ci_i2c_addr, -+ 0x1f, &cimax_init[0x18], 1); -+ /* power on slots */ -+ ret |= dvbsky_ci_write_i2c(&d->i2c_adap, state->ci_i2c_addr, -+ 0x18, &cimax_init[0x18], 1); -+ if (0 != ret) -+ return ret; -+ -+ ret = dvb_ca_en50221_init(&d->adapter[0].dvb_adap, &state->ci, 0, 1); -+ if (ret) -+ return ret; -+ state->ci_attached = 1; -+ dprintk("%s() complete.\n", __func__); -+ return 0; -+} -+ -+static void dvbsky_ci_release(struct dvb_usb_device *d) -+{ -+ struct dvbsky_state *state = d_to_priv(d); -+ -+ /* detach CI */ -+ if (state->ci_attached) -+ dvb_ca_en50221_release(&state->ci); -+ -+ return; -+} -+ -+static int dvbsky_streaming_ctrl(struct dvb_frontend *fe, int onoff) -+{ -+ struct dvb_usb_device *d = fe_to_d(fe); -+ /*dprintk("%s() %d\n", __func__, onoff);*/ -+ return dvbsky_stream_ctrl(d, (onoff == 0) ? 0 : 1); -+} -+ -+/* GPIO */ -+static int dvbsky_gpio_ctrl(struct dvb_usb_device *d, u8 gport, u8 value) -+{ -+ u8 obuf[64], ibuf[64]; -+ obuf[0] = 0x0e; -+ obuf[1] = gport; -+ obuf[2] = value; -+ return dvb_usbv2_generic_rw(d, obuf, 3, ibuf, 1); -+} -+ -+/* I2C */ -+static int dvbsky_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], -+ int num) -+{ -+ struct dvb_usb_device *d = i2c_get_adapdata(adap); -+ int ret = 0; -+ u8 ibuf[64], obuf[64]; -+ -+ if (mutex_lock_interruptible(&d->i2c_mutex) < 0) -+ return -EAGAIN; -+ -+ if (num > 2) { -+ printk(KERN_ERR "dvbsky_usb: too many i2c messages[%d] than 2.", num); -+ ret = -EOPNOTSUPP; -+ goto i2c_error; -+ } -+ -+ if(num == 1) { -+ if (msg[0].len > 60) { -+ printk(KERN_ERR "dvbsky_usb: too many i2c bytes[%d] than 60.", msg[0].len); -+ ret = -EOPNOTSUPP; -+ goto i2c_error; -+ } -+ if (msg[0].flags & I2C_M_RD) { -+ /* single read */ -+ obuf[0] = 0x09; -+ obuf[1] = 0; -+ obuf[2] = msg[0].len; -+ obuf[3] = msg[0].addr; -+ ret = dvb_usbv2_generic_rw(d, obuf, 4, ibuf, msg[0].len + 1); -+ /*dprintk("%s(): read status = %d\n", __func__, ibuf[0]);*/ -+ if (!ret) -+ memcpy(msg[0].buf, &ibuf[1], msg[0].len); -+ } else { -+ /* write */ -+ obuf[0] = 0x08; -+ obuf[1] = msg[0].addr; -+ obuf[2] = msg[0].len; -+ memcpy(&obuf[3], msg[0].buf, msg[0].len); -+ ret = dvb_usbv2_generic_rw(d, obuf, msg[0].len + 3, ibuf, 1); -+ /*dprintk("%s(): write status = %d\n", __func__, ibuf[0]);*/ -+ } -+ } else { -+ if ((msg[0].len > 60) || (msg[1].len > 60)) { -+ printk(KERN_ERR "dvbsky_usb: too many i2c bytes[w-%d][r-%d] than 60.", msg[0].len, msg[1].len); -+ ret = -EOPNOTSUPP; -+ goto i2c_error; -+ } -+ /* write then read */ -+ obuf[0] = 0x09; -+ obuf[1] = msg[0].len; -+ obuf[2] = msg[1].len; -+ obuf[3] = msg[0].addr; -+ memcpy(&obuf[4], msg[0].buf, msg[0].len); -+ ret = dvb_usbv2_generic_rw(d, obuf, msg[0].len + 4, ibuf, msg[1].len + 1); -+ /*dprintk("%s(): write then read status = %d\n", __func__, ibuf[0]);*/ -+ if (!ret) -+ memcpy(msg[1].buf, &ibuf[1], msg[1].len); -+ } -+i2c_error: -+ mutex_unlock(&d->i2c_mutex); -+ return (ret) ? ret : num; -+} -+ -+static u32 dvbsky_i2c_func(struct i2c_adapter *adapter) -+{ -+ return I2C_FUNC_I2C; -+} -+ -+static struct i2c_algorithm dvbsky_i2c_algo = { -+ .master_xfer = dvbsky_i2c_xfer, -+ .functionality = dvbsky_i2c_func, -+}; -+ -+#if IS_ENABLED(CONFIG_RC_CORE) -+static int dvbsky_rc_query(struct dvb_usb_device *d) -+{ -+ u32 code = 0xffff; -+ u8 obuf[2], ibuf[2], toggle; -+ int ret; -+ obuf[0] = 0x10; -+ ret = dvb_usbv2_generic_rw(d, obuf, 1, ibuf, 2); -+ if(ret == 0) -+ code = (ibuf[0] << 8) | ibuf[1]; -+ -+ if (code != 0xffff) { -+ dprintk("rc code: %x", code); -+ toggle = (code & 0x800) ? 1 : 0; -+ code &= 0x3f; -+ rc_keydown(d->rc_dev, code, toggle); -+ } -+ return 0; -+} -+ -+static int dvbsky_get_rc_config(struct dvb_usb_device *d, struct dvb_usb_rc *rc) -+{ -+ rc->allowed_protos = RC_BIT_RC5; -+ rc->query = dvbsky_rc_query; -+ rc->interval = 300; -+ return 0; -+} -+#else -+ #define dvbsky_get_rc_config NULL -+#endif -+ -+static int dvbsky_sync_ctrl(struct dvb_frontend *fe) -+{ -+ struct dvb_usb_device *d = fe_to_d(fe); -+ return dvbsky_stream_ctrl(d, 1); -+} -+ -+static int dvbsky_usb_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) -+{ -+ struct dvb_usb_device *d = fe_to_d(fe); -+ u8 value; -+ -+ if (voltage == SEC_VOLTAGE_OFF) -+ value = 0; -+ else -+ value = 1; -+ return dvbsky_gpio_ctrl(d, 0x80, value); -+} -+ -+static int dvbsky_read_mac_addr(struct dvb_usb_adapter *adap, u8 mac[6]) -+{ -+ struct dvb_usb_device *d = adap_to_d(adap); -+ u8 obuf[] = { 0x1e, 0x00 }; -+ u8 ibuf[6] = { 0 }; -+ struct i2c_msg msg[] = { -+ { -+ .addr = 0x51, -+ .flags = 0, -+ .buf = obuf, -+ .len = 2, -+ }, { -+ .addr = 0x51, -+ .flags = I2C_M_RD, -+ .buf = ibuf, -+ .len = 6, -+ -+ } -+ }; -+ -+ if (i2c_transfer(&d->i2c_adap, msg, 2) == 2) -+ memcpy(mac, ibuf, 6); -+ -+ printk(KERN_INFO "dvbsky_usb MAC address=%pM\n", mac); -+ -+ return 0; -+} -+ -+static struct m88ds3103_config dvbsky_usb_ds3103_config = { -+ .demod_address = 0x68, -+ .ci_mode = 1, -+ .pin_ctrl = 0x83, -+ .ts_mode = 0, -+ .start_ctrl = dvbsky_sync_ctrl, -+ .set_voltage = dvbsky_usb_set_voltage, -+}; -+ -+static int dvbsky_s960_attach(struct dvb_usb_adapter *adap) -+{ -+ struct dvbsky_state *state = adap_to_priv(adap); -+ struct dvb_usb_device *d = adap_to_d(adap); -+ int ret = 0; -+ -+ dprintk("%s()\n", __func__); -+ -+ dvbsky_gpio_ctrl(d, 0x04, 1); -+ -+ dvbsky_gpio_ctrl(d, 0x83, 0); -+ msleep(50); -+ dvbsky_gpio_ctrl(d, 0x83, 1); -+ msleep(20); -+ -+ adap->fe[0] = dvb_attach(m88ds3103_attach, -+ &dvbsky_usb_ds3103_config, -+ &d->i2c_adap); -+ if (!adap->fe[0]) { -+ printk(KERN_ERR "dvbsky_s960_attach fail."); -+ ret = -ENODEV; -+ } -+ -+ state->has_ci = 0; -+ -+ return ret; -+} -+ -+static int dvbsky_identify_state(struct dvb_usb_device *d, const char **name) -+{ -+ return WARM; -+} -+ -+static int dvbsky_init(struct dvb_usb_device *d) -+{ -+ struct dvbsky_state *state = d_to_priv(d); -+ int ret; -+ -+ /* use default interface */ -+ ret = usb_set_interface(d->udev, 0, 0); -+ if (ret) -+ return ret; -+ -+ mutex_init(&state->stream_mutex); -+ -+ /* attach CI */ -+ if (state->has_ci) { -+ dvbsky_gpio_ctrl(d, 0xc0, 1); -+ msleep(100); -+ dvbsky_gpio_ctrl(d, 0xc0, 0); -+ msleep(50); -+ state->ci_attached = 0; -+ ret = dvbsky_ci_init(d); -+ if (ret) -+ return ret; -+ } -+ return 0; -+} -+ -+static void dvbsky_exit(struct dvb_usb_device *d) -+{ -+ return dvbsky_ci_release(d); -+} -+ -+/* DVB USB Driver stuff */ -+static struct dvb_usb_device_properties dvbsky_s960_props = { -+ .driver_name = KBUILD_MODNAME, -+ .owner = THIS_MODULE, -+ .adapter_nr = adapter_nr, -+ .size_of_priv = sizeof(struct dvbsky_state), -+ -+ .generic_bulk_ctrl_endpoint = 0x01, -+ .generic_bulk_ctrl_endpoint_response = 0x81, -+ -+ .i2c_algo = &dvbsky_i2c_algo, -+ .frontend_attach = dvbsky_s960_attach, -+ .init = dvbsky_init, -+ .get_rc_config = dvbsky_get_rc_config, -+ .streaming_ctrl = dvbsky_streaming_ctrl, -+ .identify_state = dvbsky_identify_state, -+ .exit = dvbsky_exit, -+ .read_mac_address = dvbsky_read_mac_addr, -+ -+ .num_adapters = 1, -+ .adapter = { -+ { -+ .stream = DVB_USB_STREAM_BULK(0x82, 8, 4096), -+ } -+ } -+}; -+ -+static const struct usb_device_id dvbsky_id_table[] = { -+ { DVB_USB_DEVICE(0x0572, 0x6831, -+ &dvbsky_s960_props, "DVBSky S960/S860", RC_MAP_DVBSKY) }, -+ { } -+}; -+MODULE_DEVICE_TABLE(usb, dvbsky_id_table); -+ -+static struct usb_driver dvbsky_usb_driver = { -+ .name = KBUILD_MODNAME, -+ .id_table = dvbsky_id_table, -+ .probe = dvb_usbv2_probe, -+ .disconnect = dvb_usbv2_disconnect, -+ .suspend = dvb_usbv2_suspend, -+ .resume = dvb_usbv2_resume, -+ .reset_resume = dvb_usbv2_reset_resume, -+ .no_dynamic_id = 1, -+ .soft_unbind = 1, -+}; -+ -+module_usb_driver(dvbsky_usb_driver); -+ -+MODULE_AUTHOR("Max nibble "); -+MODULE_DESCRIPTION("Driver for DVBSky USB2.0"); -+MODULE_LICENSE("GPL"); -diff -urN a/drivers/media/usb/dvb-usb-v2/Kconfig b/drivers/media/usb/dvb-usb-v2/Kconfig ---- a/drivers/media/usb/dvb-usb-v2/Kconfig 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/usb/dvb-usb-v2/Kconfig 2013-05-03 17:45:35.000000000 +0800 -@@ -149,3 +149,10 @@ - help - Say Y here to support the Realtek RTL28xxU DVB USB receiver. - -+config DVB_USB_DVBSKY -+ tristate "DVBSky USB2.0 support" -+ depends on DVB_USB_V2 -+ select DVB_M88DS3103 if MEDIA_SUBDRV_AUTOSELECT -+ help -+ Say Y here to support the USB receivers from DVBSky. -+ -diff -urN a/drivers/media/usb/dvb-usb-v2/Makefile b/drivers/media/usb/dvb-usb-v2/Makefile ---- a/drivers/media/usb/dvb-usb-v2/Makefile 2013-04-29 08:36:01.000000000 +0800 -+++ b/drivers/media/usb/dvb-usb-v2/Makefile 2013-02-17 12:03:00.000000000 +0800 -@@ -43,6 +43,9 @@ - dvb-usb-rtl28xxu-objs := rtl28xxu.o - obj-$(CONFIG_DVB_USB_RTL28XXU) += dvb-usb-rtl28xxu.o - -+dvb-usb-dvbsky-objs := dvbsky.o -+obj-$(CONFIG_DVB_USB_DVBSKY) += dvb-usb-dvbsky.o -+ - ccflags-y += -I$(srctree)/drivers/media/dvb-core - ccflags-y += -I$(srctree)/drivers/media/dvb-frontends - ccflags-y += -I$(srctree)/drivers/media/tuners -diff -urN a/include/media/rc-map.h b/include/media/rc-map.h ---- a/include/media/rc-map.h 2013-04-29 08:36:01.000000000 +0800 -+++ b/include/media/rc-map.h 2013-05-03 17:02:46.000000000 +0800 -@@ -118,6 +118,7 @@ - #define RC_MAP_DM1105_NEC "rc-dm1105-nec" - #define RC_MAP_DNTV_LIVE_DVBT_PRO "rc-dntv-live-dvbt-pro" - #define RC_MAP_DNTV_LIVE_DVB_T "rc-dntv-live-dvb-t" -+#define RC_MAP_DVBSKY "rc-dvbsky" - #define RC_MAP_EMPTY "rc-empty" - #define RC_MAP_EM_TERRATEC "rc-em-terratec" - #define RC_MAP_ENCORE_ENLTV2 "rc-encore-enltv2" diff --git a/packages/linux/patches/3.11.6/linux-210.01-dvbsky-auto-off.patch b/packages/linux/patches/3.11.6/linux-210.01-dvbsky-auto-off.patch deleted file mode 100644 index 381e8b9bc9..0000000000 --- a/packages/linux/patches/3.11.6/linux-210.01-dvbsky-auto-off.patch +++ /dev/null @@ -1,31 +0,0 @@ -diff --git a/drivers/media/dvb-frontends/m88ds3103.c b/drivers/media/dvb-frontends/m88ds3103.c -index 315809d..54dff7c 100644 ---- a/drivers/media/dvb-frontends/m88ds3103.c -+++ b/drivers/media/dvb-frontends/m88ds3103.c -@@ -1244,6 +1244,8 @@ static int m88ds3103_set_frontend(struct dvb_frontend *fe) - dprintk("symbol rate = %d\n", c->symbol_rate); - dprintk("delivery system = %d\n", c->delivery_system); - -+ state->delivery_system = c->delivery_system; -+ - realFreq = c->frequency; - lpf_offset_KHz = 0; - if(c->symbol_rate < 5000000){ -@@ -1501,7 +1503,7 @@ static int m88ds3103_set_frontend(struct dvb_frontend *fe) - } - msleep(20); - } -- -+/* - if((status & FE_HAS_LOCK) == 0){ - state->delivery_system = (state->delivery_system == SYS_DVBS) ? SYS_DVBS2 : SYS_DVBS; - m88ds3103_demod_connect(fe, offset_khz); -@@ -1514,7 +1516,7 @@ static int m88ds3103_set_frontend(struct dvb_frontend *fe) - msleep(20); - } - } -- -+*/ - if (status & FE_HAS_LOCK){ - if(state->config->ci_mode == 2) - m88ds3103_set_clock_ratio(state); diff --git a/packages/linux/patches/3.11.6/linux-212-mantis_stb0899_faster_lock.patch b/packages/linux/patches/3.11.6/linux-212-mantis_stb0899_faster_lock.patch deleted file mode 100644 index eef4e1effc..0000000000 --- a/packages/linux/patches/3.11.6/linux-212-mantis_stb0899_faster_lock.patch +++ /dev/null @@ -1,138 +0,0 @@ -diff -Naur linux-3.7.2/drivers/media/dvb-frontends/stb0899_algo.c linux-3.7.2.patch/drivers/media/dvb-frontends/stb0899_algo.c ---- linux-3.7.2/drivers/media/dvb-frontends/stb0899_algo.c 2013-01-11 18:19:28.000000000 +0100 -+++ linux-3.7.2.patch/drivers/media/dvb-frontends/stb0899_algo.c 2013-01-16 10:28:33.633409961 +0100 -@@ -206,7 +206,6 @@ - static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state) - { - struct stb0899_internal *internal = &state->internal; -- struct stb0899_params *params = &state->params; - - short int derot_step, derot_freq = 0, derot_limit, next_loop = 3; - int index = 0; -@@ -216,10 +215,9 @@ - - /* timing loop computation & symbol rate optimisation */ - derot_limit = (internal->sub_range / 2L) / internal->mclk; -- derot_step = (params->srate / 2L) / internal->mclk; -+ derot_step = internal->derot_step * 4; /* dertot_step = decreasing delta */ - - while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) { -- index++; - derot_freq += index * internal->direction * derot_step; /* next derot zig zag position */ - - if (abs(derot_freq) > derot_limit) -@@ -230,6 +228,7 @@ - STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq)); - stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */ - } -+ index++; - internal->direction = -internal->direction; /* Change zigzag direction */ - } - -@@ -278,14 +277,18 @@ - { - struct stb0899_internal *internal = &state->internal; - -- short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3; -+ short int derot_freq = 0, last_derot_freq = 0, derot_limit, derot_step, next_loop = 3; - int index = 0; -+ int base_freq; - u8 cfr[2]; - u8 reg; - - internal->status = NOCARRIER; - derot_limit = (internal->sub_range / 2L) / internal->mclk; - derot_freq = internal->derot_freq; -+ derot_step = internal->derot_step * 2; -+ last_derot_freq = internal->derot_freq; -+ base_freq = internal->derot_freq; - - reg = stb0899_read_reg(state, STB0899_CFD); - STB0899_SETFIELD_VAL(CFD_ON, reg, 1); -@@ -294,11 +297,10 @@ - do { - dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk); - if (stb0899_check_carrier(state) == NOCARRIER) { -- index++; - last_derot_freq = derot_freq; -- derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */ -+ derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */ - -- if(abs(derot_freq) > derot_limit) -+ if (derot_freq > base_freq + derot_limit || derot_freq < base_freq - derot_limit) - next_loop--; - - if (next_loop) { -@@ -310,9 +312,10 @@ - STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq)); - stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */ - } -+ index++; -+ internal->direction = -internal->direction; /* Change zigzag direction */ - } - -- internal->direction = -internal->direction; /* Change zigzag direction */ - } while ((internal->status != CARRIEROK) && next_loop); - - if (internal->status == CARRIEROK) { -@@ -338,6 +341,7 @@ - int lock = 0, index = 0, dataTime = 500, loop; - u8 reg; - -+ msleep(1); - internal->status = NODATA; - - /* RESET FEC */ -@@ -348,6 +352,7 @@ - reg = stb0899_read_reg(state, STB0899_TSTRES); - STB0899_SETFIELD_VAL(FRESACS, reg, 0); - stb0899_write_reg(state, STB0899_TSTRES, reg); -+ msleep(1); - - if (params->srate <= 2000000) - dataTime = 2000; -@@ -363,6 +368,7 @@ - - stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop */ - while (1) { -+ msleep(1); // Alex: added 1 mSec - /* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP */ - reg = stb0899_read_reg(state, STB0899_VSTATUS); - lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg); -@@ -390,20 +396,21 @@ - short int derot_freq, derot_step, derot_limit, next_loop = 3; - u8 cfr[2]; - u8 reg; -- int index = 1; -+ int index = 0; -+ int base_freq; - - struct stb0899_internal *internal = &state->internal; -- struct stb0899_params *params = &state->params; - -- derot_step = (params->srate / 4L) / internal->mclk; -+ derot_step = internal->derot_step; - derot_limit = (internal->sub_range / 2L) / internal->mclk; - derot_freq = internal->derot_freq; -+ base_freq = internal->derot_freq; - - do { - if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) { - - derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */ -- if (abs(derot_freq) > derot_limit) -+ if (derot_freq > base_freq + derot_limit || derot_freq < base_freq - derot_limit) - next_loop--; - - if (next_loop) { -@@ -417,9 +424,9 @@ - stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */ - - stb0899_check_carrier(state); -- index++; - } - } -+ index++; - internal->direction = -internal->direction; /* change zig zag direction */ - } while ((internal->status != DATAOK) && next_loop); - diff --git a/packages/linux/patches/3.11.6/linux-221-ngene-octopus.patch b/packages/linux/patches/3.11.6/linux-221-ngene-octopus.patch deleted file mode 100644 index ea092a58f9..0000000000 --- a/packages/linux/patches/3.11.6/linux-221-ngene-octopus.patch +++ /dev/null @@ -1,12735 +0,0 @@ -From c5891c83d5777a2e691c2a452a7f57a6b6a13344 Mon Sep 17 00:00:00 2001 -From: Stefan Saraev -Date: Sun, 12 May 2013 23:47:07 +0300 -Subject: [PATCH] dvb: ngene/octopus - ---- - drivers/media/dvb-frontends/Kconfig | 26 + - drivers/media/dvb-frontends/Makefile | 2 + - drivers/media/dvb-frontends/stv0367dd.c | 2269 +++++++++++++++++ - drivers/media/dvb-frontends/stv0367dd.h | 17 + - drivers/media/dvb-frontends/stv0367dd_regs.h | 3431 ++++++++++++++++++++++++++ - drivers/media/dvb-frontends/tda18212dd.c | 906 +++++++ - drivers/media/dvb-frontends/tda18212dd.h | 5 + - drivers/media/pci/ddbridge/Kconfig | 14 +- - drivers/media/pci/ddbridge/ddbridge-core.c | 1947 ++++++++++++---- - drivers/media/pci/ddbridge/ddbridge-regs.h | 56 +- - drivers/media/pci/ddbridge/ddbridge.h | 97 +- - drivers/media/pci/ngene/Kconfig | 17 +- - drivers/media/pci/ngene/Makefile | 3 +- - drivers/media/pci/ngene/ngene-av.c | 348 +++ - drivers/media/pci/ngene/ngene-cards.c | 778 +++++-- - drivers/media/pci/ngene/ngene-core.c | 378 +++- - drivers/media/pci/ngene/ngene-dvb.c | 372 +++ - drivers/media/pci/ngene/ngene-eeprom.c | 284 +++ - drivers/media/pci/ngene/ngene-i2c.c | 113 + - drivers/media/pci/ngene/ngene.h | 40 + - drivers/staging/media/cxd2099/TODO | 12 - - drivers/staging/media/cxd2099/cxd2099.c | 47 +- - drivers/staging/media/cxd2099/cxd2099.h | 2 +- - 23 files changed, 10416 insertions(+), 748 deletions(-) - create mode 100644 drivers/media/dvb-frontends/stv0367dd.c - create mode 100644 drivers/media/dvb-frontends/stv0367dd.h - create mode 100644 drivers/media/dvb-frontends/stv0367dd_regs.h - create mode 100644 drivers/media/dvb-frontends/tda18212dd.c - create mode 100644 drivers/media/dvb-frontends/tda18212dd.h - create mode 100644 drivers/media/pci/ngene/ngene-av.c - create mode 100644 drivers/media/pci/ngene/ngene-eeprom.c - delete mode 100644 drivers/staging/media/cxd2099/TODO - -diff --git a/drivers/media/dvb-frontends/Kconfig b/drivers/media/dvb-frontends/Kconfig -index 05cf66f..1e0275f 100644 ---- a/drivers/media/dvb-frontends/Kconfig -+++ b/drivers/media/dvb-frontends/Kconfig -@@ -19,6 +19,14 @@ config DVB_STB0899 - A DVB-S/S2/DSS Multistandard demodulator. Say Y when you want - to support this demodulator based frontends - -+config DVB_CXD2099 -+ tristate "CXD2099AR Common Interface driver" -+ depends on DVB_CORE && PCI && I2C -+ ---help--- -+ Support for the CI module found on cards based on -+ - Micronas ngene PCIe bridge: cineS2 etc. -+ - Digital Devices PCIe bridge: Octopus series -+ - config DVB_STB6100 - tristate "STB6100 based tuners" - depends on DVB_CORE && I2C -@@ -63,6 +71,24 @@ config DVB_TDA18271C2DD - - Say Y when you want to support this tuner. - -+config DVB_STV0367DD -+ tristate "STV 0367 (DD)" -+ depends on DVB_CORE && I2C -+ default m if DVB_FE_CUSTOMISE -+ help -+ STV 0367 DVB-C/T demodulator (Digital Devices driver). -+ -+ Say Y when you want to support this frontend. -+ -+config DVB_TDA18212DD -+ tristate "NXP TDA18212 silicon tuner (DD)" -+ depends on DVB_CORE && I2C -+ default m if DVB_FE_CUSTOMISE -+ help -+ NXP TDA18212 silicon tuner (Digital Devices driver). -+ -+ Say Y when you want to support this tuner. -+ - comment "DVB-S (satellite) frontends" - depends on DVB_CORE - -diff --git a/drivers/media/dvb-frontends/Makefile b/drivers/media/dvb-frontends/Makefile -index 75440de..25ab5f8 100644 ---- a/drivers/media/dvb-frontends/Makefile -+++ b/drivers/media/dvb-frontends/Makefile -@@ -100,6 +100,8 @@ obj-$(CONFIG_DVB_STV0367) += stv0367.o - obj-$(CONFIG_DVB_CXD2820R) += cxd2820r.o - obj-$(CONFIG_DVB_DRXK) += drxk.o - obj-$(CONFIG_DVB_TDA18271C2DD) += tda18271c2dd.o -+obj-$(CONFIG_DVB_STV0367DD) += stv0367dd.o -+obj-$(CONFIG_DVB_TDA18212DD) += tda18212dd.o - obj-$(CONFIG_DVB_IT913X_FE) += it913x-fe.o - obj-$(CONFIG_DVB_A8293) += a8293.o - obj-$(CONFIG_DVB_TDA10071) += tda10071.o -diff --git a/drivers/media/dvb-frontends/stv0367dd.c b/drivers/media/dvb-frontends/stv0367dd.c -new file mode 100644 -index 0000000..34a38cf ---- /dev/null -+++ b/drivers/media/dvb-frontends/stv0367dd.c -@@ -0,0 +1,2269 @@ -+/* -+ * stv0367dd: STV0367 DVB-C/T demodulator driver -+ * -+ * Copyright (C) 2011 Digital Devices GmbH -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 only, as published by the Free Software Foundation. -+ * -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ * 02110-1301, USA -+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "dvb_frontend.h" -+#include "stv0367dd.h" -+#include "stv0367dd_regs.h" -+ -+enum omode { OM_NONE, OM_DVBT, OM_DVBC, OM_QAM_ITU_C }; -+enum { QAM_MOD_QAM4 = 0, -+ QAM_MOD_QAM16, -+ QAM_MOD_QAM32, -+ QAM_MOD_QAM64, -+ QAM_MOD_QAM128, -+ QAM_MOD_QAM256, -+ QAM_MOD_QAM512, -+ QAM_MOD_QAM1024 -+}; -+ -+enum {QAM_SPECT_NORMAL, QAM_SPECT_INVERTED }; -+ -+enum { -+ QAM_FEC_A = 1, /* J83 Annex A */ -+ QAM_FEC_B = (1<<1), /* J83 Annex B */ -+ QAM_FEC_C = (1<<2) /* J83 Annex C */ -+}; -+ -+enum EDemodState { Off, QAMSet, OFDMSet, QAMStarted, OFDMStarted }; -+ -+struct stv_state { -+#ifdef USE_API3 -+ struct dvb_frontend c_frontend; -+ struct dvb_frontend t_frontend; -+#else -+ struct dvb_frontend frontend; -+#endif -+ fe_modulation_t modulation; -+ u32 symbol_rate; -+ u32 bandwidth; -+ struct device *dev; -+ -+ struct i2c_adapter *i2c; -+ u8 adr; -+ void *priv; -+ -+ struct mutex mutex; -+ struct mutex ctlock; -+ -+ u32 master_clock; -+ u32 adc_clock; -+ u8 ID; -+ u8 I2CRPT; -+ u32 omode; -+ u8 qam_inversion; -+ -+ s32 IF; -+ -+ s32 m_FECTimeOut; -+ s32 m_DemodTimeOut; -+ s32 m_SignalTimeOut; -+ s32 m_DemodLockTime; -+ s32 m_FFTTimeOut; -+ s32 m_TSTimeOut; -+ -+ bool m_bFirstTimeLock; -+ -+ u8 m_Save_QAM_AGC_CTL; -+ -+ enum EDemodState demod_state; -+ -+ u8 m_OFDM_FFTMode; // 0 = 2k, 1 = 8k, 2 = 4k -+ u8 m_OFDM_Modulation; // -+ u8 m_OFDM_FEC; // -+ u8 m_OFDM_Guard; -+ -+ u32 ucblocks; -+}; -+ -+struct init_table { -+ u16 adr; -+ u8 data; -+}; -+ -+struct init_table base_init[] = { -+ { R367_IOCFG0, 0x80 }, -+ { R367_DAC0R, 0x00 }, -+ { R367_IOCFG1, 0x00 }, -+ { R367_DAC1R, 0x00 }, -+ { R367_IOCFG2, 0x00 }, -+ { R367_SDFR, 0x00 }, -+ { R367_AUX_CLK, 0x00 }, -+ { R367_FREESYS1, 0x00 }, -+ { R367_FREESYS2, 0x00 }, -+ { R367_FREESYS3, 0x00 }, -+ { R367_GPIO_CFG, 0x55 }, -+ { R367_GPIO_CMD, 0x01 }, -+ { R367_TSTRES, 0x00 }, -+ { R367_ANACTRL, 0x00 }, -+ { R367_TSTBUS, 0x00 }, -+ { R367_RF_AGC2, 0x20 }, -+ { R367_ANADIGCTRL, 0x0b }, -+ { R367_PLLMDIV, 0x01 }, -+ { R367_PLLNDIV, 0x08 }, -+ { R367_PLLSETUP, 0x18 }, -+ { R367_DUAL_AD12, 0x04 }, -+ { R367_TSTBIST, 0x00 }, -+ { 0x0000, 0x00 } -+}; -+ -+struct init_table qam_init[] = { -+ { R367_QAM_CTRL_1, 0x06 },// Orginal 0x04 -+ { R367_QAM_CTRL_2, 0x03 }, -+ { R367_QAM_IT_STATUS1, 0x2b }, -+ { R367_QAM_IT_STATUS2, 0x08 }, -+ { R367_QAM_IT_EN1, 0x00 }, -+ { R367_QAM_IT_EN2, 0x00 }, -+ { R367_QAM_CTRL_STATUS, 0x04 }, -+ { R367_QAM_TEST_CTL, 0x00 }, -+ { R367_QAM_AGC_CTL, 0x73 }, -+ { R367_QAM_AGC_IF_CFG, 0x50 }, -+ { R367_QAM_AGC_RF_CFG, 0x02 },// RF Freeze -+ { R367_QAM_AGC_PWM_CFG, 0x03 }, -+ { R367_QAM_AGC_PWR_REF_L, 0x5a }, -+ { R367_QAM_AGC_PWR_REF_H, 0x00 }, -+ { R367_QAM_AGC_RF_TH_L, 0xff }, -+ { R367_QAM_AGC_RF_TH_H, 0x07 }, -+ { R367_QAM_AGC_IF_LTH_L, 0x00 }, -+ { R367_QAM_AGC_IF_LTH_H, 0x08 }, -+ { R367_QAM_AGC_IF_HTH_L, 0xff }, -+ { R367_QAM_AGC_IF_HTH_H, 0x07 }, -+ { R367_QAM_AGC_PWR_RD_L, 0xa0 }, -+ { R367_QAM_AGC_PWR_RD_M, 0xe9 }, -+ { R367_QAM_AGC_PWR_RD_H, 0x03 }, -+ { R367_QAM_AGC_PWM_IFCMD_L, 0xe4 }, -+ { R367_QAM_AGC_PWM_IFCMD_H, 0x00 }, -+ { R367_QAM_AGC_PWM_RFCMD_L, 0xff }, -+ { R367_QAM_AGC_PWM_RFCMD_H, 0x07 }, -+ { R367_QAM_IQDEM_CFG, 0x01 }, -+ { R367_QAM_MIX_NCO_LL, 0x22 }, -+ { R367_QAM_MIX_NCO_HL, 0x96 }, -+ { R367_QAM_MIX_NCO_HH, 0x55 }, -+ { R367_QAM_SRC_NCO_LL, 0xff }, -+ { R367_QAM_SRC_NCO_LH, 0x0c }, -+ { R367_QAM_SRC_NCO_HL, 0xf5 }, -+ { R367_QAM_SRC_NCO_HH, 0x20 }, -+ { R367_QAM_IQDEM_GAIN_SRC_L, 0x06 }, -+ { R367_QAM_IQDEM_GAIN_SRC_H, 0x01 }, -+ { R367_QAM_IQDEM_DCRM_CFG_LL, 0xfe }, -+ { R367_QAM_IQDEM_DCRM_CFG_LH, 0xff }, -+ { R367_QAM_IQDEM_DCRM_CFG_HL, 0x0f }, -+ { R367_QAM_IQDEM_DCRM_CFG_HH, 0x00 }, -+ { R367_QAM_IQDEM_ADJ_COEFF0, 0x34 }, -+ { R367_QAM_IQDEM_ADJ_COEFF1, 0xae }, -+ { R367_QAM_IQDEM_ADJ_COEFF2, 0x46 }, -+ { R367_QAM_IQDEM_ADJ_COEFF3, 0x77 }, -+ { R367_QAM_IQDEM_ADJ_COEFF4, 0x96 }, -+ { R367_QAM_IQDEM_ADJ_COEFF5, 0x69 }, -+ { R367_QAM_IQDEM_ADJ_COEFF6, 0xc7 }, -+ { R367_QAM_IQDEM_ADJ_COEFF7, 0x01 }, -+ { R367_QAM_IQDEM_ADJ_EN, 0x04 }, -+ { R367_QAM_IQDEM_ADJ_AGC_REF, 0x94 }, -+ { R367_QAM_ALLPASSFILT1, 0xc9 }, -+ { R367_QAM_ALLPASSFILT2, 0x2d }, -+ { R367_QAM_ALLPASSFILT3, 0xa3 }, -+ { R367_QAM_ALLPASSFILT4, 0xfb }, -+ { R367_QAM_ALLPASSFILT5, 0xf6 }, -+ { R367_QAM_ALLPASSFILT6, 0x45 }, -+ { R367_QAM_ALLPASSFILT7, 0x6f }, -+ { R367_QAM_ALLPASSFILT8, 0x7e }, -+ { R367_QAM_ALLPASSFILT9, 0x05 }, -+ { R367_QAM_ALLPASSFILT10, 0x0a }, -+ { R367_QAM_ALLPASSFILT11, 0x51 }, -+ { R367_QAM_TRL_AGC_CFG, 0x20 }, -+ { R367_QAM_TRL_LPF_CFG, 0x28 }, -+ { R367_QAM_TRL_LPF_ACQ_GAIN, 0x44 }, -+ { R367_QAM_TRL_LPF_TRK_GAIN, 0x22 }, -+ { R367_QAM_TRL_LPF_OUT_GAIN, 0x03 }, -+ { R367_QAM_TRL_LOCKDET_LTH, 0x04 }, -+ { R367_QAM_TRL_LOCKDET_HTH, 0x11 }, -+ { R367_QAM_TRL_LOCKDET_TRGVAL, 0x20 }, -+ { R367_QAM_IQ_QAM, 0x01 }, -+ { R367_QAM_FSM_STATE, 0xa0 }, -+ { R367_QAM_FSM_CTL, 0x08 }, -+ { R367_QAM_FSM_STS, 0x0c }, -+ { R367_QAM_FSM_SNR0_HTH, 0x00 }, -+ { R367_QAM_FSM_SNR1_HTH, 0x00 }, -+ { R367_QAM_FSM_SNR2_HTH, 0x00 }, -+ { R367_QAM_FSM_SNR0_LTH, 0x00 }, -+ { R367_QAM_FSM_SNR1_LTH, 0x00 }, -+ { R367_QAM_FSM_EQA1_HTH, 0x00 }, -+ { R367_QAM_FSM_TEMPO, 0x32 }, -+ { R367_QAM_FSM_CONFIG, 0x03 }, -+ { R367_QAM_EQU_I_TESTTAP_L, 0x11 }, -+ { R367_QAM_EQU_I_TESTTAP_M, 0x00 }, -+ { R367_QAM_EQU_I_TESTTAP_H, 0x00 }, -+ { R367_QAM_EQU_TESTAP_CFG, 0x00 }, -+ { R367_QAM_EQU_Q_TESTTAP_L, 0xff }, -+ { R367_QAM_EQU_Q_TESTTAP_M, 0x00 }, -+ { R367_QAM_EQU_Q_TESTTAP_H, 0x00 }, -+ { R367_QAM_EQU_TAP_CTRL, 0x00 }, -+ { R367_QAM_EQU_CTR_CRL_CONTROL_L, 0x11 }, -+ { R367_QAM_EQU_CTR_CRL_CONTROL_H, 0x05 }, -+ { R367_QAM_EQU_CTR_HIPOW_L, 0x00 }, -+ { R367_QAM_EQU_CTR_HIPOW_H, 0x00 }, -+ { R367_QAM_EQU_I_EQU_LO, 0xef }, -+ { R367_QAM_EQU_I_EQU_HI, 0x00 }, -+ { R367_QAM_EQU_Q_EQU_LO, 0xee }, -+ { R367_QAM_EQU_Q_EQU_HI, 0x00 }, -+ { R367_QAM_EQU_MAPPER, 0xc5 }, -+ { R367_QAM_EQU_SWEEP_RATE, 0x80 }, -+ { R367_QAM_EQU_SNR_LO, 0x64 }, -+ { R367_QAM_EQU_SNR_HI, 0x03 }, -+ { R367_QAM_EQU_GAMMA_LO, 0x00 }, -+ { R367_QAM_EQU_GAMMA_HI, 0x00 }, -+ { R367_QAM_EQU_ERR_GAIN, 0x36 }, -+ { R367_QAM_EQU_RADIUS, 0xaa }, -+ { R367_QAM_EQU_FFE_MAINTAP, 0x00 }, -+ { R367_QAM_EQU_FFE_LEAKAGE, 0x63 }, -+ { R367_QAM_EQU_FFE_MAINTAP_POS, 0xdf }, -+ { R367_QAM_EQU_GAIN_WIDE, 0x88 }, -+ { R367_QAM_EQU_GAIN_NARROW, 0x41 }, -+ { R367_QAM_EQU_CTR_LPF_GAIN, 0xd1 }, -+ { R367_QAM_EQU_CRL_LPF_GAIN, 0xa7 }, -+ { R367_QAM_EQU_GLOBAL_GAIN, 0x06 }, -+ { R367_QAM_EQU_CRL_LD_SEN, 0x85 }, -+ { R367_QAM_EQU_CRL_LD_VAL, 0xe2 }, -+ { R367_QAM_EQU_CRL_TFR, 0x20 }, -+ { R367_QAM_EQU_CRL_BISTH_LO, 0x00 }, -+ { R367_QAM_EQU_CRL_BISTH_HI, 0x00 }, -+ { R367_QAM_EQU_SWEEP_RANGE_LO, 0x00 }, -+ { R367_QAM_EQU_SWEEP_RANGE_HI, 0x00 }, -+ { R367_QAM_EQU_CRL_LIMITER, 0x40 }, -+ { R367_QAM_EQU_MODULUS_MAP, 0x90 }, -+ { R367_QAM_EQU_PNT_GAIN, 0xa7 }, -+ { R367_QAM_FEC_AC_CTR_0, 0x16 }, -+ { R367_QAM_FEC_AC_CTR_1, 0x0b }, -+ { R367_QAM_FEC_AC_CTR_2, 0x88 }, -+ { R367_QAM_FEC_AC_CTR_3, 0x02 }, -+ { R367_QAM_FEC_STATUS, 0x12 }, -+ { R367_QAM_RS_COUNTER_0, 0x7d }, -+ { R367_QAM_RS_COUNTER_1, 0xd0 }, -+ { R367_QAM_RS_COUNTER_2, 0x19 }, -+ { R367_QAM_RS_COUNTER_3, 0x0b }, -+ { R367_QAM_RS_COUNTER_4, 0xa3 }, -+ { R367_QAM_RS_COUNTER_5, 0x00 }, -+ { R367_QAM_BERT_0, 0x01 }, -+ { R367_QAM_BERT_1, 0x25 }, -+ { R367_QAM_BERT_2, 0x41 }, -+ { R367_QAM_BERT_3, 0x39 }, -+ { R367_QAM_OUTFORMAT_0, 0xc2 }, -+ { R367_QAM_OUTFORMAT_1, 0x22 }, -+ { R367_QAM_SMOOTHER_2, 0x28 }, -+ { R367_QAM_TSMF_CTRL_0, 0x01 }, -+ { R367_QAM_TSMF_CTRL_1, 0xc6 }, -+ { R367_QAM_TSMF_CTRL_3, 0x43 }, -+ { R367_QAM_TS_ON_ID_0, 0x00 }, -+ { R367_QAM_TS_ON_ID_1, 0x00 }, -+ { R367_QAM_TS_ON_ID_2, 0x00 }, -+ { R367_QAM_TS_ON_ID_3, 0x00 }, -+ { R367_QAM_RE_STATUS_0, 0x00 }, -+ { R367_QAM_RE_STATUS_1, 0x00 }, -+ { R367_QAM_RE_STATUS_2, 0x00 }, -+ { R367_QAM_RE_STATUS_3, 0x00 }, -+ { R367_QAM_TS_STATUS_0, 0x00 }, -+ { R367_QAM_TS_STATUS_1, 0x00 }, -+ { R367_QAM_TS_STATUS_2, 0xa0 }, -+ { R367_QAM_TS_STATUS_3, 0x00 }, -+ { R367_QAM_T_O_ID_0, 0x00 }, -+ { R367_QAM_T_O_ID_1, 0x00 }, -+ { R367_QAM_T_O_ID_2, 0x00 }, -+ { R367_QAM_T_O_ID_3, 0x00 }, -+ { 0x0000, 0x00 } // EOT -+}; -+ -+struct init_table ofdm_init[] = { -+ //{R367_OFDM_ID ,0x60}, -+ //{R367_OFDM_I2CRPT ,0x22}, -+ //{R367_OFDM_TOPCTRL ,0x02}, -+ //{R367_OFDM_IOCFG0 ,0x40}, -+ //{R367_OFDM_DAC0R ,0x00}, -+ //{R367_OFDM_IOCFG1 ,0x00}, -+ //{R367_OFDM_DAC1R ,0x00}, -+ //{R367_OFDM_IOCFG2 ,0x62}, -+ //{R367_OFDM_SDFR ,0x00}, -+ //{R367_OFDM_STATUS ,0xf8}, -+ //{R367_OFDM_AUX_CLK ,0x0a}, -+ //{R367_OFDM_FREESYS1 ,0x00}, -+ //{R367_OFDM_FREESYS2 ,0x00}, -+ //{R367_OFDM_FREESYS3 ,0x00}, -+ //{R367_OFDM_GPIO_CFG ,0x55}, -+ //{R367_OFDM_GPIO_CMD ,0x00}, -+ {R367_OFDM_AGC2MAX ,0xff}, -+ {R367_OFDM_AGC2MIN ,0x00}, -+ {R367_OFDM_AGC1MAX ,0xff}, -+ {R367_OFDM_AGC1MIN ,0x00}, -+ {R367_OFDM_AGCR ,0xbc}, -+ {R367_OFDM_AGC2TH ,0x00}, -+ //{R367_OFDM_AGC12C ,0x01}, //Note: This defines AGC pins, also needed for QAM -+ {R367_OFDM_AGCCTRL1 ,0x85}, -+ {R367_OFDM_AGCCTRL2 ,0x1f}, -+ {R367_OFDM_AGC1VAL1 ,0x00}, -+ {R367_OFDM_AGC1VAL2 ,0x00}, -+ {R367_OFDM_AGC2VAL1 ,0x6f}, -+ {R367_OFDM_AGC2VAL2 ,0x05}, -+ {R367_OFDM_AGC2PGA ,0x00}, -+ {R367_OFDM_OVF_RATE1 ,0x00}, -+ {R367_OFDM_OVF_RATE2 ,0x00}, -+ {R367_OFDM_GAIN_SRC1 ,0x2b}, -+ {R367_OFDM_GAIN_SRC2 ,0x04}, -+ {R367_OFDM_INC_DEROT1 ,0x55}, -+ {R367_OFDM_INC_DEROT2 ,0x55}, -+ {R367_OFDM_PPM_CPAMP_DIR ,0x2c}, -+ {R367_OFDM_PPM_CPAMP_INV ,0x00}, -+ {R367_OFDM_FREESTFE_1 ,0x00}, -+ {R367_OFDM_FREESTFE_2 ,0x1c}, -+ {R367_OFDM_DCOFFSET ,0x00}, -+ {R367_OFDM_EN_PROCESS ,0x05}, -+ {R367_OFDM_SDI_SMOOTHER ,0x80}, -+ {R367_OFDM_FE_LOOP_OPEN ,0x1c}, -+ {R367_OFDM_FREQOFF1 ,0x00}, -+ {R367_OFDM_FREQOFF2 ,0x00}, -+ {R367_OFDM_FREQOFF3 ,0x00}, -+ {R367_OFDM_TIMOFF1 ,0x00}, -+ {R367_OFDM_TIMOFF2 ,0x00}, -+ {R367_OFDM_EPQ ,0x02}, -+ {R367_OFDM_EPQAUTO ,0x01}, -+ {R367_OFDM_SYR_UPDATE ,0xf5}, -+ {R367_OFDM_CHPFREE ,0x00}, -+ {R367_OFDM_PPM_STATE_MAC ,0x23}, -+ {R367_OFDM_INR_THRESHOLD ,0xff}, -+ {R367_OFDM_EPQ_TPS_ID_CELL ,0xf9}, -+ {R367_OFDM_EPQ_CFG ,0x00}, -+ {R367_OFDM_EPQ_STATUS ,0x01}, -+ {R367_OFDM_AUTORELOCK ,0x81}, -+ {R367_OFDM_BER_THR_VMSB ,0x00}, -+ {R367_OFDM_BER_THR_MSB ,0x00}, -+ {R367_OFDM_BER_THR_LSB ,0x00}, -+ {R367_OFDM_CCD ,0x83}, -+ {R367_OFDM_SPECTR_CFG ,0x00}, -+ {R367_OFDM_CHC_DUMMY ,0x18}, -+ {R367_OFDM_INC_CTL ,0x88}, -+ {R367_OFDM_INCTHRES_COR1 ,0xb4}, -+ {R367_OFDM_INCTHRES_COR2 ,0x96}, -+ {R367_OFDM_INCTHRES_DET1 ,0x0e}, -+ {R367_OFDM_INCTHRES_DET2 ,0x11}, -+ {R367_OFDM_IIR_CELLNB ,0x8d}, -+ {R367_OFDM_IIRCX_COEFF1_MSB ,0x00}, -+ {R367_OFDM_IIRCX_COEFF1_LSB ,0x00}, -+ {R367_OFDM_IIRCX_COEFF2_MSB ,0x09}, -+ {R367_OFDM_IIRCX_COEFF2_LSB ,0x18}, -+ {R367_OFDM_IIRCX_COEFF3_MSB ,0x14}, -+ {R367_OFDM_IIRCX_COEFF3_LSB ,0x9c}, -+ {R367_OFDM_IIRCX_COEFF4_MSB ,0x00}, -+ {R367_OFDM_IIRCX_COEFF4_LSB ,0x00}, -+ {R367_OFDM_IIRCX_COEFF5_MSB ,0x36}, -+ {R367_OFDM_IIRCX_COEFF5_LSB ,0x42}, -+ {R367_OFDM_FEPATH_CFG ,0x00}, -+ {R367_OFDM_PMC1_FUNC ,0x65}, -+ {R367_OFDM_PMC1_FOR ,0x00}, -+ {R367_OFDM_PMC2_FUNC ,0x00}, -+ {R367_OFDM_STATUS_ERR_DA ,0xe0}, -+ {R367_OFDM_DIG_AGC_R ,0xfe}, -+ {R367_OFDM_COMAGC_TARMSB ,0x0b}, -+ {R367_OFDM_COM_AGC_TAR_ENMODE ,0x41}, -+ {R367_OFDM_COM_AGC_CFG ,0x3e}, -+ {R367_OFDM_COM_AGC_GAIN1 ,0x39}, -+ {R367_OFDM_AUT_AGC_TARGETMSB ,0x0b}, -+ {R367_OFDM_LOCK_DET_MSB ,0x01}, -+ {R367_OFDM_AGCTAR_LOCK_LSBS ,0x40}, -+ {R367_OFDM_AUT_GAIN_EN ,0xf4}, -+ {R367_OFDM_AUT_CFG ,0xf0}, -+ {R367_OFDM_LOCKN ,0x23}, -+ {R367_OFDM_INT_X_3 ,0x00}, -+ {R367_OFDM_INT_X_2 ,0x03}, -+ {R367_OFDM_INT_X_1 ,0x8d}, -+ {R367_OFDM_INT_X_0 ,0xa0}, -+ {R367_OFDM_MIN_ERRX_MSB ,0x00}, -+ {R367_OFDM_COR_CTL ,0x00}, -+ {R367_OFDM_COR_STAT ,0xf6}, -+ {R367_OFDM_COR_INTEN ,0x00}, -+ {R367_OFDM_COR_INTSTAT ,0x3f}, -+ {R367_OFDM_COR_MODEGUARD ,0x03}, -+ {R367_OFDM_AGC_CTL ,0x08}, -+ {R367_OFDM_AGC_MANUAL1 ,0x00}, -+ {R367_OFDM_AGC_MANUAL2 ,0x00}, -+ {R367_OFDM_AGC_TARG ,0x16}, -+ {R367_OFDM_AGC_GAIN1 ,0x53}, -+ {R367_OFDM_AGC_GAIN2 ,0x1d}, -+ {R367_OFDM_RESERVED_1 ,0x00}, -+ {R367_OFDM_RESERVED_2 ,0x00}, -+ {R367_OFDM_RESERVED_3 ,0x00}, -+ {R367_OFDM_CAS_CTL ,0x44}, -+ {R367_OFDM_CAS_FREQ ,0xb3}, -+ {R367_OFDM_CAS_DAGCGAIN ,0x12}, -+ {R367_OFDM_SYR_CTL ,0x04}, -+ {R367_OFDM_SYR_STAT ,0x10}, -+ {R367_OFDM_SYR_NCO1 ,0x00}, -+ {R367_OFDM_SYR_NCO2 ,0x00}, -+ {R367_OFDM_SYR_OFFSET1 ,0x00}, -+ {R367_OFDM_SYR_OFFSET2 ,0x00}, -+ {R367_OFDM_FFT_CTL ,0x00}, -+ {R367_OFDM_SCR_CTL ,0x70}, -+ {R367_OFDM_PPM_CTL1 ,0xf8}, -+ {R367_OFDM_TRL_CTL ,0xac}, -+ {R367_OFDM_TRL_NOMRATE1 ,0x1e}, -+ {R367_OFDM_TRL_NOMRATE2 ,0x58}, -+ {R367_OFDM_TRL_TIME1 ,0x1d}, -+ {R367_OFDM_TRL_TIME2 ,0xfc}, -+ {R367_OFDM_CRL_CTL ,0x24}, -+ {R367_OFDM_CRL_FREQ1 ,0xad}, -+ {R367_OFDM_CRL_FREQ2 ,0x9d}, -+ {R367_OFDM_CRL_FREQ3 ,0xff}, -+ {R367_OFDM_CHC_CTL ,0x01}, -+ {R367_OFDM_CHC_SNR ,0xf0}, -+ {R367_OFDM_BDI_CTL ,0x00}, -+ {R367_OFDM_DMP_CTL ,0x00}, -+ {R367_OFDM_TPS_RCVD1 ,0x30}, -+ {R367_OFDM_TPS_RCVD2 ,0x02}, -+ {R367_OFDM_TPS_RCVD3 ,0x01}, -+ {R367_OFDM_TPS_RCVD4 ,0x00}, -+ {R367_OFDM_TPS_ID_CELL1 ,0x00}, -+ {R367_OFDM_TPS_ID_CELL2 ,0x00}, -+ {R367_OFDM_TPS_RCVD5_SET1 ,0x02}, -+ {R367_OFDM_TPS_SET2 ,0x02}, -+ {R367_OFDM_TPS_SET3 ,0x01}, -+ {R367_OFDM_TPS_CTL ,0x00}, -+ {R367_OFDM_CTL_FFTOSNUM ,0x34}, -+ {R367_OFDM_TESTSELECT ,0x09}, -+ {R367_OFDM_MSC_REV ,0x0a}, -+ {R367_OFDM_PIR_CTL ,0x00}, -+ {R367_OFDM_SNR_CARRIER1 ,0xa1}, -+ {R367_OFDM_SNR_CARRIER2 ,0x9a}, -+ {R367_OFDM_PPM_CPAMP ,0x2c}, -+ {R367_OFDM_TSM_AP0 ,0x00}, -+ {R367_OFDM_TSM_AP1 ,0x00}, -+ {R367_OFDM_TSM_AP2 ,0x00}, -+ {R367_OFDM_TSM_AP3 ,0x00}, -+ {R367_OFDM_TSM_AP4 ,0x00}, -+ {R367_OFDM_TSM_AP5 ,0x00}, -+ {R367_OFDM_TSM_AP6 ,0x00}, -+ {R367_OFDM_TSM_AP7 ,0x00}, -+ //{R367_OFDM_TSTRES ,0x00}, -+ //{R367_OFDM_ANACTRL ,0x0D},/*caution PLL stopped, to be restarted at init!!!*/ -+ //{R367_OFDM_TSTBUS ,0x00}, -+ //{R367_OFDM_TSTRATE ,0x00}, -+ {R367_OFDM_CONSTMODE ,0x01}, -+ {R367_OFDM_CONSTCARR1 ,0x00}, -+ {R367_OFDM_CONSTCARR2 ,0x00}, -+ {R367_OFDM_ICONSTEL ,0x0a}, -+ {R367_OFDM_QCONSTEL ,0x15}, -+ {R367_OFDM_TSTBISTRES0 ,0x00}, -+ {R367_OFDM_TSTBISTRES1 ,0x00}, -+ {R367_OFDM_TSTBISTRES2 ,0x28}, -+ {R367_OFDM_TSTBISTRES3 ,0x00}, -+ //{R367_OFDM_RF_AGC1 ,0xff}, -+ //{R367_OFDM_RF_AGC2 ,0x83}, -+ //{R367_OFDM_ANADIGCTRL ,0x19}, -+ //{R367_OFDM_PLLMDIV ,0x0c}, -+ //{R367_OFDM_PLLNDIV ,0x55}, -+ //{R367_OFDM_PLLSETUP ,0x18}, -+ //{R367_OFDM_DUAL_AD12 ,0x00}, -+ //{R367_OFDM_TSTBIST ,0x00}, -+ //{R367_OFDM_PAD_COMP_CTRL ,0x00}, -+ //{R367_OFDM_PAD_COMP_WR ,0x00}, -+ //{R367_OFDM_PAD_COMP_RD ,0xe0}, -+ {R367_OFDM_SYR_TARGET_FFTADJT_MSB ,0x00}, -+ {R367_OFDM_SYR_TARGET_FFTADJT_LSB ,0x00}, -+ {R367_OFDM_SYR_TARGET_CHCADJT_MSB ,0x00}, -+ {R367_OFDM_SYR_TARGET_CHCADJT_LSB ,0x00}, -+ {R367_OFDM_SYR_FLAG ,0x00}, -+ {R367_OFDM_CRL_TARGET1 ,0x00}, -+ {R367_OFDM_CRL_TARGET2 ,0x00}, -+ {R367_OFDM_CRL_TARGET3 ,0x00}, -+ {R367_OFDM_CRL_TARGET4 ,0x00}, -+ {R367_OFDM_CRL_FLAG ,0x00}, -+ {R367_OFDM_TRL_TARGET1 ,0x00}, -+ {R367_OFDM_TRL_TARGET2 ,0x00}, -+ {R367_OFDM_TRL_CHC ,0x00}, -+ {R367_OFDM_CHC_SNR_TARG ,0x00}, -+ {R367_OFDM_TOP_TRACK ,0x00}, -+ {R367_OFDM_TRACKER_FREE1 ,0x00}, -+ {R367_OFDM_ERROR_CRL1 ,0x00}, -+ {R367_OFDM_ERROR_CRL2 ,0x00}, -+ {R367_OFDM_ERROR_CRL3 ,0x00}, -+ {R367_OFDM_ERROR_CRL4 ,0x00}, -+ {R367_OFDM_DEC_NCO1 ,0x2c}, -+ {R367_OFDM_DEC_NCO2 ,0x0f}, -+ {R367_OFDM_DEC_NCO3 ,0x20}, -+ {R367_OFDM_SNR ,0xf1}, -+ {R367_OFDM_SYR_FFTADJ1 ,0x00}, -+ {R367_OFDM_SYR_FFTADJ2 ,0x00}, -+ {R367_OFDM_SYR_CHCADJ1 ,0x00}, -+ {R367_OFDM_SYR_CHCADJ2 ,0x00}, -+ {R367_OFDM_SYR_OFF ,0x00}, -+ {R367_OFDM_PPM_OFFSET1 ,0x00}, -+ {R367_OFDM_PPM_OFFSET2 ,0x03}, -+ {R367_OFDM_TRACKER_FREE2 ,0x00}, -+ {R367_OFDM_DEBG_LT10 ,0x00}, -+ {R367_OFDM_DEBG_LT11 ,0x00}, -+ {R367_OFDM_DEBG_LT12 ,0x00}, -+ {R367_OFDM_DEBG_LT13 ,0x00}, -+ {R367_OFDM_DEBG_LT14 ,0x00}, -+ {R367_OFDM_DEBG_LT15 ,0x00}, -+ {R367_OFDM_DEBG_LT16 ,0x00}, -+ {R367_OFDM_DEBG_LT17 ,0x00}, -+ {R367_OFDM_DEBG_LT18 ,0x00}, -+ {R367_OFDM_DEBG_LT19 ,0x00}, -+ {R367_OFDM_DEBG_LT1A ,0x00}, -+ {R367_OFDM_DEBG_LT1B ,0x00}, -+ {R367_OFDM_DEBG_LT1C ,0x00}, -+ {R367_OFDM_DEBG_LT1D ,0x00}, -+ {R367_OFDM_DEBG_LT1E ,0x00}, -+ {R367_OFDM_DEBG_LT1F ,0x00}, -+ {R367_OFDM_RCCFGH ,0x00}, -+ {R367_OFDM_RCCFGM ,0x00}, -+ {R367_OFDM_RCCFGL ,0x00}, -+ {R367_OFDM_RCINSDELH ,0x00}, -+ {R367_OFDM_RCINSDELM ,0x00}, -+ {R367_OFDM_RCINSDELL ,0x00}, -+ {R367_OFDM_RCSTATUS ,0x00}, -+ {R367_OFDM_RCSPEED ,0x6f}, -+ {R367_OFDM_RCDEBUGM ,0xe7}, -+ {R367_OFDM_RCDEBUGL ,0x9b}, -+ {R367_OFDM_RCOBSCFG ,0x00}, -+ {R367_OFDM_RCOBSM ,0x00}, -+ {R367_OFDM_RCOBSL ,0x00}, -+ {R367_OFDM_RCFECSPY ,0x00}, -+ {R367_OFDM_RCFSPYCFG ,0x00}, -+ {R367_OFDM_RCFSPYDATA ,0x00}, -+ {R367_OFDM_RCFSPYOUT ,0x00}, -+ {R367_OFDM_RCFSTATUS ,0x00}, -+ {R367_OFDM_RCFGOODPACK ,0x00}, -+ {R367_OFDM_RCFPACKCNT ,0x00}, -+ {R367_OFDM_RCFSPYMISC ,0x00}, -+ {R367_OFDM_RCFBERCPT4 ,0x00}, -+ {R367_OFDM_RCFBERCPT3 ,0x00}, -+ {R367_OFDM_RCFBERCPT2 ,0x00}, -+ {R367_OFDM_RCFBERCPT1 ,0x00}, -+ {R367_OFDM_RCFBERCPT0 ,0x00}, -+ {R367_OFDM_RCFBERERR2 ,0x00}, -+ {R367_OFDM_RCFBERERR1 ,0x00}, -+ {R367_OFDM_RCFBERERR0 ,0x00}, -+ {R367_OFDM_RCFSTATESM ,0x00}, -+ {R367_OFDM_RCFSTATESL ,0x00}, -+ {R367_OFDM_RCFSPYBER ,0x00}, -+ {R367_OFDM_RCFSPYDISTM ,0x00}, -+ {R367_OFDM_RCFSPYDISTL ,0x00}, -+ {R367_OFDM_RCFSPYOBS7 ,0x00}, -+ {R367_OFDM_RCFSPYOBS6 ,0x00}, -+ {R367_OFDM_RCFSPYOBS5 ,0x00}, -+ {R367_OFDM_RCFSPYOBS4 ,0x00}, -+ {R367_OFDM_RCFSPYOBS3 ,0x00}, -+ {R367_OFDM_RCFSPYOBS2 ,0x00}, -+ {R367_OFDM_RCFSPYOBS1 ,0x00}, -+ {R367_OFDM_RCFSPYOBS0 ,0x00}, -+ //{R367_OFDM_TSGENERAL ,0x00}, -+ //{R367_OFDM_RC1SPEED ,0x6f}, -+ //{R367_OFDM_TSGSTATUS ,0x18}, -+ {R367_OFDM_FECM ,0x01}, -+ {R367_OFDM_VTH12 ,0xff}, -+ {R367_OFDM_VTH23 ,0xa1}, -+ {R367_OFDM_VTH34 ,0x64}, -+ {R367_OFDM_VTH56 ,0x40}, -+ {R367_OFDM_VTH67 ,0x00}, -+ {R367_OFDM_VTH78 ,0x2c}, -+ {R367_OFDM_VITCURPUN ,0x12}, -+ {R367_OFDM_VERROR ,0x01}, -+ {R367_OFDM_PRVIT ,0x3f}, -+ {R367_OFDM_VAVSRVIT ,0x00}, -+ {R367_OFDM_VSTATUSVIT ,0xbd}, -+ {R367_OFDM_VTHINUSE ,0xa1}, -+ {R367_OFDM_KDIV12 ,0x20}, -+ {R367_OFDM_KDIV23 ,0x40}, -+ {R367_OFDM_KDIV34 ,0x20}, -+ {R367_OFDM_KDIV56 ,0x30}, -+ {R367_OFDM_KDIV67 ,0x00}, -+ {R367_OFDM_KDIV78 ,0x30}, -+ {R367_OFDM_SIGPOWER ,0x54}, -+ {R367_OFDM_DEMAPVIT ,0x40}, -+ {R367_OFDM_VITSCALE ,0x00}, -+ {R367_OFDM_FFEC1PRG ,0x00}, -+ {R367_OFDM_FVITCURPUN ,0x12}, -+ {R367_OFDM_FVERROR ,0x01}, -+ {R367_OFDM_FVSTATUSVIT ,0xbd}, -+ {R367_OFDM_DEBUG_LT1 ,0x00}, -+ {R367_OFDM_DEBUG_LT2 ,0x00}, -+ {R367_OFDM_DEBUG_LT3 ,0x00}, -+ {R367_OFDM_TSTSFMET ,0x00}, -+ {R367_OFDM_SELOUT ,0x00}, -+ {R367_OFDM_TSYNC ,0x00}, -+ {R367_OFDM_TSTERR ,0x00}, -+ {R367_OFDM_TSFSYNC ,0x00}, -+ {R367_OFDM_TSTSFERR ,0x00}, -+ {R367_OFDM_TSTTSSF1 ,0x01}, -+ {R367_OFDM_TSTTSSF2 ,0x1f}, -+ {R367_OFDM_TSTTSSF3 ,0x00}, -+ {R367_OFDM_TSTTS1 ,0x00}, -+ {R367_OFDM_TSTTS2 ,0x1f}, -+ {R367_OFDM_TSTTS3 ,0x01}, -+ {R367_OFDM_TSTTS4 ,0x00}, -+ {R367_OFDM_TSTTSRC ,0x00}, -+ {R367_OFDM_TSTTSRS ,0x00}, -+ {R367_OFDM_TSSTATEM ,0xb0}, -+ {R367_OFDM_TSSTATEL ,0x40}, -+ {R367_OFDM_TSCFGH ,0x80}, -+ {R367_OFDM_TSCFGM ,0x00}, -+ {R367_OFDM_TSCFGL ,0x20}, -+ {R367_OFDM_TSSYNC ,0x00}, -+ {R367_OFDM_TSINSDELH ,0x00}, -+ {R367_OFDM_TSINSDELM ,0x00}, -+ {R367_OFDM_TSINSDELL ,0x00}, -+ {R367_OFDM_TSDIVN ,0x03}, -+ {R367_OFDM_TSDIVPM ,0x00}, -+ {R367_OFDM_TSDIVPL ,0x00}, -+ {R367_OFDM_TSDIVQM ,0x00}, -+ {R367_OFDM_TSDIVQL ,0x00}, -+ {R367_OFDM_TSDILSTKM ,0x00}, -+ {R367_OFDM_TSDILSTKL ,0x00}, -+ {R367_OFDM_TSSPEED ,0x6f}, -+ {R367_OFDM_TSSTATUS ,0x81}, -+ {R367_OFDM_TSSTATUS2 ,0x6a}, -+ {R367_OFDM_TSBITRATEM ,0x0f}, -+ {R367_OFDM_TSBITRATEL ,0xc6}, -+ {R367_OFDM_TSPACKLENM ,0x00}, -+ {R367_OFDM_TSPACKLENL ,0xfc}, -+ {R367_OFDM_TSBLOCLENM ,0x0a}, -+ {R367_OFDM_TSBLOCLENL ,0x80}, -+ {R367_OFDM_TSDLYH ,0x90}, -+ {R367_OFDM_TSDLYM ,0x68}, -+ {R367_OFDM_TSDLYL ,0x01}, -+ {R367_OFDM_TSNPDAV ,0x00}, -+ {R367_OFDM_TSBUFSTATH ,0x00}, -+ {R367_OFDM_TSBUFSTATM ,0x00}, -+ {R367_OFDM_TSBUFSTATL ,0x00}, -+ {R367_OFDM_TSDEBUGM ,0xcf}, -+ {R367_OFDM_TSDEBUGL ,0x1e}, -+ {R367_OFDM_TSDLYSETH ,0x00}, -+ {R367_OFDM_TSDLYSETM ,0x68}, -+ {R367_OFDM_TSDLYSETL ,0x00}, -+ {R367_OFDM_TSOBSCFG ,0x00}, -+ {R367_OFDM_TSOBSM ,0x47}, -+ {R367_OFDM_TSOBSL ,0x1f}, -+ {R367_OFDM_ERRCTRL1 ,0x95}, -+ {R367_OFDM_ERRCNT1H ,0x80}, -+ {R367_OFDM_ERRCNT1M ,0x00}, -+ {R367_OFDM_ERRCNT1L ,0x00}, -+ {R367_OFDM_ERRCTRL2 ,0x95}, -+ {R367_OFDM_ERRCNT2H ,0x00}, -+ {R367_OFDM_ERRCNT2M ,0x00}, -+ {R367_OFDM_ERRCNT2L ,0x00}, -+ {R367_OFDM_FECSPY ,0x88}, -+ {R367_OFDM_FSPYCFG ,0x2c}, -+ {R367_OFDM_FSPYDATA ,0x3a}, -+ {R367_OFDM_FSPYOUT ,0x06}, -+ {R367_OFDM_FSTATUS ,0x61}, -+ {R367_OFDM_FGOODPACK ,0xff}, -+ {R367_OFDM_FPACKCNT ,0xff}, -+ {R367_OFDM_FSPYMISC ,0x66}, -+ {R367_OFDM_FBERCPT4 ,0x00}, -+ {R367_OFDM_FBERCPT3 ,0x00}, -+ {R367_OFDM_FBERCPT2 ,0x36}, -+ {R367_OFDM_FBERCPT1 ,0x36}, -+ {R367_OFDM_FBERCPT0 ,0x14}, -+ {R367_OFDM_FBERERR2 ,0x00}, -+ {R367_OFDM_FBERERR1 ,0x03}, -+ {R367_OFDM_FBERERR0 ,0x28}, -+ {R367_OFDM_FSTATESM ,0x00}, -+ {R367_OFDM_FSTATESL ,0x02}, -+ {R367_OFDM_FSPYBER ,0x00}, -+ {R367_OFDM_FSPYDISTM ,0x01}, -+ {R367_OFDM_FSPYDISTL ,0x9f}, -+ {R367_OFDM_FSPYOBS7 ,0xc9}, -+ {R367_OFDM_FSPYOBS6 ,0x99}, -+ {R367_OFDM_FSPYOBS5 ,0x08}, -+ {R367_OFDM_FSPYOBS4 ,0xec}, -+ {R367_OFDM_FSPYOBS3 ,0x01}, -+ {R367_OFDM_FSPYOBS2 ,0x0f}, -+ {R367_OFDM_FSPYOBS1 ,0xf5}, -+ {R367_OFDM_FSPYOBS0 ,0x08}, -+ {R367_OFDM_SFDEMAP ,0x40}, -+ {R367_OFDM_SFERROR ,0x00}, -+ {R367_OFDM_SFAVSR ,0x30}, -+ {R367_OFDM_SFECSTATUS ,0xcc}, -+ {R367_OFDM_SFKDIV12 ,0x20}, -+ {R367_OFDM_SFKDIV23 ,0x40}, -+ {R367_OFDM_SFKDIV34 ,0x20}, -+ {R367_OFDM_SFKDIV56 ,0x20}, -+ {R367_OFDM_SFKDIV67 ,0x00}, -+ {R367_OFDM_SFKDIV78 ,0x20}, -+ {R367_OFDM_SFDILSTKM ,0x00}, -+ {R367_OFDM_SFDILSTKL ,0x00}, -+ {R367_OFDM_SFSTATUS ,0xb5}, -+ {R367_OFDM_SFDLYH ,0x90}, -+ {R367_OFDM_SFDLYM ,0x60}, -+ {R367_OFDM_SFDLYL ,0x01}, -+ {R367_OFDM_SFDLYSETH ,0xc0}, -+ {R367_OFDM_SFDLYSETM ,0x60}, -+ {R367_OFDM_SFDLYSETL ,0x00}, -+ {R367_OFDM_SFOBSCFG ,0x00}, -+ {R367_OFDM_SFOBSM ,0x47}, -+ {R367_OFDM_SFOBSL ,0x05}, -+ {R367_OFDM_SFECINFO ,0x40}, -+ {R367_OFDM_SFERRCTRL ,0x74}, -+ {R367_OFDM_SFERRCNTH ,0x80}, -+ {R367_OFDM_SFERRCNTM ,0x00}, -+ {R367_OFDM_SFERRCNTL ,0x00}, -+ {R367_OFDM_SYMBRATEM ,0x2f}, -+ {R367_OFDM_SYMBRATEL ,0x50}, -+ {R367_OFDM_SYMBSTATUS ,0x7f}, -+ {R367_OFDM_SYMBCFG ,0x00}, -+ {R367_OFDM_SYMBFIFOM ,0xf4}, -+ {R367_OFDM_SYMBFIFOL ,0x0d}, -+ {R367_OFDM_SYMBOFFSM ,0xf0}, -+ {R367_OFDM_SYMBOFFSL ,0x2d}, -+ //{R367_OFDM_DEBUG_LT4 ,0x00}, -+ //{R367_OFDM_DEBUG_LT5 ,0x00}, -+ //{R367_OFDM_DEBUG_LT6 ,0x00}, -+ //{R367_OFDM_DEBUG_LT7 ,0x00}, -+ //{R367_OFDM_DEBUG_LT8 ,0x00}, -+ //{R367_OFDM_DEBUG_LT9 ,0x00}, -+ { 0x0000, 0x00 } // EOT -+}; -+ -+inline u32 MulDiv32(u32 a, u32 b, u32 c) -+{ -+ u64 tmp64; -+ -+ tmp64 = (u64)a * (u64)b; -+ do_div(tmp64, c); -+ -+ return (u32) tmp64; -+} -+ -+static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -+{ -+ struct i2c_msg msg = -+ {.addr = adr, .flags = 0, .buf = data, .len = len}; -+ -+ if (i2c_transfer(adap, &msg, 1) != 1) { -+ printk("stv0367: i2c_write error\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+#if 0 -+static int i2c_read(struct i2c_adapter *adap, -+ u8 adr, u8 *msg, int len, u8 *answ, int alen) -+{ -+ struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, -+ .buf = msg, .len = len}, -+ { .addr = adr, .flags = I2C_M_RD, -+ .buf = answ, .len = alen } }; -+ if (i2c_transfer(adap, msgs, 2) != 2) { -+ printk("stv0367: i2c_read error\n"); -+ return -1; -+ } -+ return 0; -+} -+#endif -+ -+static int writereg(struct stv_state *state, u16 reg, u8 dat) -+{ -+ u8 mm[3] = { (reg >> 8), reg & 0xff, dat }; -+ -+ return i2c_write(state->i2c, state->adr, mm, 3); -+} -+ -+static int readreg(struct stv_state *state, u16 reg, u8 *val) -+{ -+ u8 msg[2] = {reg >> 8, reg & 0xff}; -+ struct i2c_msg msgs[2] = {{.addr = state->adr, .flags = 0, -+ .buf = msg, .len = 2}, -+ {.addr = state->adr, .flags = I2C_M_RD, -+ .buf = val, .len = 1}}; -+ return (i2c_transfer(state->i2c, msgs, 2) == 2) ? 0 : -1; -+} -+ -+static int readregs(struct stv_state *state, u16 reg, u8 *val, int count) -+{ -+ u8 msg[2] = {reg >> 8, reg & 0xff}; -+ struct i2c_msg msgs[2] = {{.addr = state->adr, .flags = 0, -+ .buf = msg, .len = 2}, -+ {.addr = state->adr, .flags = I2C_M_RD, -+ .buf = val, .len = count}}; -+ return (i2c_transfer(state->i2c, msgs, 2) == 2) ? 0 : -1; -+} -+ -+static int write_init_table(struct stv_state *state, struct init_table *tab) -+{ -+ while (1) { -+ if (!tab->adr) -+ break; -+ if (writereg(state, tab->adr, tab->data) < 0) -+ return -1; -+ tab++; -+ } -+ return 0; -+} -+ -+static int qam_set_modulation(struct stv_state *state) -+{ -+ int stat = 0; -+ -+ switch(state->modulation) { -+ case QAM_16: -+ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM16 ); -+ writereg(state, R367_QAM_AGC_PWR_REF_L,0x64); /* Set analog AGC reference */ -+ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ -+ writereg(state, R367_QAM_FSM_STATE,0x90); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); -+ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x95); -+ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,0x8a); -+ break; -+ case QAM_32: -+ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM32 ); -+ writereg(state, R367_QAM_AGC_PWR_REF_L,0x6e); /* Set analog AGC reference */ -+ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ -+ writereg(state, R367_QAM_FSM_STATE,0xb0); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xb7); -+ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x9d); -+ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x7f); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); -+ break; -+ case QAM_64: -+ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM64 ); -+ writereg(state, R367_QAM_AGC_PWR_REF_L,0x5a); /* Set analog AGC reference */ -+ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x82); /* Set digital AGC reference */ -+ if(state->symbol_rate>4500000) -+ { -+ writereg(state, R367_QAM_FSM_STATE,0xb0); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa5); -+ } -+ else if(state->symbol_rate>2500000) // 25000000 -+ { -+ writereg(state, R367_QAM_FSM_STATE,0xa0); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa6); -+ } -+ else -+ { -+ writereg(state, R367_QAM_FSM_STATE,0xa0); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xd1); -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); -+ } -+ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x95); -+ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,0x99); -+ break; -+ case QAM_128: -+ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM128 ); -+ writereg(state, R367_QAM_AGC_PWR_REF_L,0x76); /* Set analog AGC reference */ -+ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ -+ writereg(state, R367_QAM_FSM_STATE,0x90); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xb1); -+ if(state->symbol_rate>4500000) // 45000000 -+ { -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); -+ } -+ else if(state->symbol_rate>2500000) // 25000000 -+ { -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa6); -+ } -+ else -+ { -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0x97); -+ } -+ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x8e); -+ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x7f); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); -+ break; -+ case QAM_256: -+ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM256 ); -+ writereg(state, R367_QAM_AGC_PWR_REF_L,0x5a); /* Set analog AGC reference */ -+ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x94); /* Set digital AGC reference */ -+ writereg(state, R367_QAM_FSM_STATE,0xa0); -+ if(state->symbol_rate>4500000) // 45000000 -+ { -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ } -+ else if(state->symbol_rate>2500000) // 25000000 -+ { -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ } -+ else -+ { -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xd1); -+ } -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); -+ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x85); -+ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); -+ break; -+ default: -+ stat = -EINVAL; -+ break; -+ } -+ return stat; -+} -+ -+ -+static int QAM_SetSymbolRate(struct stv_state *state) -+{ -+ int status = 0; -+ u32 sr = state->symbol_rate; -+ u32 Corr = 0; -+ u32 Temp, Temp1, AdpClk; -+ -+ switch(state->modulation) { -+ default: -+ case QAM_16: Corr = 1032; break; -+ case QAM_32: Corr = 954; break; -+ case QAM_64: Corr = 983; break; -+ case QAM_128: Corr = 957; break; -+ case QAM_256: Corr = 948; break; -+ } -+ -+ // Transfer ration -+ Temp = (256*sr) / state->adc_clock; -+ writereg(state, R367_QAM_EQU_CRL_TFR,(Temp)); -+ -+ /* Symbol rate and SRC gain calculation */ -+ AdpClk = (state->master_clock)/2000; /* TRL works at half the system clock */ -+ -+ Temp = state->symbol_rate; -+ Temp1 = sr; -+ -+ if(sr < 2097152) /* 2097152 = 2^21 */ -+ { -+ Temp = ((((sr * 2048) / AdpClk) * 16384 ) / 125 ) * 8; -+ Temp1 = (((((sr * 2048) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 10000000; -+ } -+ else if(sr < 4194304) /* 4194304 = 2**22 */ -+ { -+ Temp = ((((sr * 1024) / AdpClk) * 16384 ) / 125 ) * 16; -+ Temp1 = (((((sr * 1024) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 5000000; -+ } -+ else if(sr < 8388608) /* 8388608 = 2**23 */ -+ { -+ Temp = ((((sr * 512) / AdpClk) * 16384 ) / 125 ) * 32; -+ Temp1 = (((((sr * 512) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 2500000; -+ } -+ else -+ { -+ Temp = ((((sr * 256) / AdpClk) * 16384 ) / 125 ) * 64; -+ Temp1 = (((((sr * 256) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 1250000; -+ } -+ -+ ///* Filters' coefficients are calculated and written into registers only if the filters are enabled */ -+ //if (ChipGetField(hChip,F367qam_ADJ_EN)) // Is disabled from init! -+ //{ -+ // FE_367qam_SetIirAdjacentcoefficient(hChip, MasterClk_Hz, SymbolRate); -+ //} -+ ///* AllPass filter is never used on this IC */ -+ //ChipSetField(hChip,F367qam_ALLPASSFILT_EN,0); // should be disabled from init! -+ -+ writereg(state, R367_QAM_SRC_NCO_LL,(Temp)); -+ writereg(state, R367_QAM_SRC_NCO_LH,(Temp>>8)); -+ writereg(state, R367_QAM_SRC_NCO_HL,(Temp>>16)); -+ writereg(state, R367_QAM_SRC_NCO_HH,(Temp>>24)); -+ -+ writereg(state, R367_QAM_IQDEM_GAIN_SRC_L,(Temp1)); -+ writereg(state, R367_QAM_IQDEM_GAIN_SRC_H,(Temp1>>8)); -+ return status; -+} -+ -+ -+static int QAM_SetDerotFrequency(struct stv_state *state, u32 DerotFrequency) -+{ -+ int status = 0; -+ u32 Sampled_IF; -+ -+ do { -+ //if (DerotFrequency < 1000000) -+ // DerotFrequency = state->adc_clock/4; /* ZIF operation */ -+ if (DerotFrequency > state->adc_clock) -+ DerotFrequency = DerotFrequency - state->adc_clock; // User Alias -+ -+ Sampled_IF = ((32768 * (DerotFrequency/1000)) / (state->adc_clock/1000)) * 256; -+ if(Sampled_IF > 8388607) -+ Sampled_IF = 8388607; -+ -+ writereg(state, R367_QAM_MIX_NCO_LL, (Sampled_IF)); -+ writereg(state, R367_QAM_MIX_NCO_HL, (Sampled_IF>>8)); -+ writereg(state, R367_QAM_MIX_NCO_HH, (Sampled_IF>>16)); -+ } while(0); -+ -+ return status; -+} -+ -+ -+ -+static int QAM_Start(struct stv_state *state, s32 offsetFreq,s32 IntermediateFrequency) -+{ -+ int status = 0; -+ u32 AGCTimeOut = 25; -+ u32 TRLTimeOut = 100000000 / state->symbol_rate; -+ u32 CRLSymbols = 0; -+ u32 EQLTimeOut = 100; -+ u32 SearchRange = state->symbol_rate / 25; -+ u32 CRLTimeOut; -+ u8 Temp; -+ -+ if( state->demod_state != QAMSet ) { -+ writereg(state, R367_DEBUG_LT4,0x00); -+ writereg(state, R367_DEBUG_LT5,0x01); -+ writereg(state, R367_DEBUG_LT6,0x06);// R367_QAM_CTRL_1 -+ writereg(state, R367_DEBUG_LT7,0x03);// R367_QAM_CTRL_2 -+ writereg(state, R367_DEBUG_LT8,0x00); -+ writereg(state, R367_DEBUG_LT9,0x00); -+ -+ // Tuner Setup -+ writereg(state, R367_ANADIGCTRL,0x8B); /* Buffer Q disabled, I Enabled, signed ADC */ -+ writereg(state, R367_DUAL_AD12,0x04); /* ADCQ disabled */ -+ -+ // Clock setup -+ writereg(state, R367_ANACTRL,0x0D); /* PLL bypassed and disabled */ -+ writereg(state, R367_TOPCTRL,0x10); // Set QAM -+ -+ writereg(state, R367_PLLMDIV,27); /* IC runs at 58 MHz with a 27 MHz crystal */ -+ writereg(state, R367_PLLNDIV,232); -+ writereg(state, R367_PLLSETUP,0x18); /* ADC clock is equal to system clock */ -+ -+ msleep(50); -+ writereg(state, R367_ANACTRL,0x00); /* PLL enabled and used */ -+ -+ state->master_clock = 58000000; -+ state->adc_clock = 58000000; -+ -+ state->demod_state = QAMSet; -+ } -+ -+ state->m_bFirstTimeLock = true; -+ state->m_DemodLockTime = -1; -+ -+ qam_set_modulation(state); -+ QAM_SetSymbolRate(state); -+ -+ // Will make problems on low symbol rates ( < 2500000 ) -+ -+ switch(state->modulation) { -+ default: -+ case QAM_16: CRLSymbols = 150000; break; -+ case QAM_32: CRLSymbols = 250000; break; -+ case QAM_64: CRLSymbols = 200000; break; -+ case QAM_128: CRLSymbols = 250000; break; -+ case QAM_256: CRLSymbols = 250000; break; -+ } -+ -+ CRLTimeOut = (25 * CRLSymbols * (SearchRange/1000)) / (state->symbol_rate/1000); -+ CRLTimeOut = (1000 * CRLTimeOut) / state->symbol_rate; -+ if( CRLTimeOut < 50 ) CRLTimeOut = 50; -+ -+ state->m_FECTimeOut = 20; -+ state->m_DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut; -+ state->m_SignalTimeOut = AGCTimeOut + TRLTimeOut; -+ -+ // QAM_AGC_ACCUMRSTSEL = 0; -+ readreg(state, R367_QAM_AGC_CTL,&state->m_Save_QAM_AGC_CTL); -+ writereg(state, R367_QAM_AGC_CTL,state->m_Save_QAM_AGC_CTL & ~0x0F); -+ -+ // QAM_MODULUSMAP_EN = 0 -+ readreg(state, R367_QAM_EQU_PNT_GAIN,&Temp); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,Temp & ~0x40); -+ -+ // QAM_SWEEP_EN = 0 -+ readreg(state, R367_QAM_EQU_CTR_LPF_GAIN,&Temp); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,Temp & ~0x08); -+ -+ QAM_SetDerotFrequency(state, IntermediateFrequency); -+ -+ // Release TRL -+ writereg(state, R367_QAM_CTRL_1,0x00); -+ -+ state->IF = IntermediateFrequency; -+ state->demod_state = QAMStarted; -+ -+ return status; -+} -+ -+static int OFDM_Start(struct stv_state *state, s32 offsetFreq,s32 IntermediateFrequency) -+{ -+ int status = 0; -+ u8 GAIN_SRC1; -+ u32 Derot; -+ u8 SYR_CTL; -+ u8 tmp1; -+ u8 tmp2; -+ -+ if ( state->demod_state != OFDMSet ) { -+ // QAM Disable -+ writereg(state, R367_DEBUG_LT4, 0x00); -+ writereg(state, R367_DEBUG_LT5, 0x00); -+ writereg(state, R367_DEBUG_LT6, 0x00);// R367_QAM_CTRL_1 -+ writereg(state, R367_DEBUG_LT7, 0x00);// R367_QAM_CTRL_2 -+ writereg(state, R367_DEBUG_LT8, 0x00); -+ writereg(state, R367_DEBUG_LT9, 0x00); -+ -+ // Tuner Setup -+ writereg(state, R367_ANADIGCTRL, 0x89); /* Buffer Q disabled, I Enabled, unsigned ADC */ -+ writereg(state, R367_DUAL_AD12, 0x04); /* ADCQ disabled */ -+ -+ // Clock setup -+ writereg(state, R367_ANACTRL, 0x0D); /* PLL bypassed and disabled */ -+ writereg(state, R367_TOPCTRL, 0x00); // Set OFDM -+ -+ writereg(state, R367_PLLMDIV, 1); /* IC runs at 54 MHz with a 27 MHz crystal */ -+ writereg(state, R367_PLLNDIV, 8); -+ writereg(state, R367_PLLSETUP, 0x18); /* ADC clock is equal to system clock */ -+ -+ msleep(50); -+ writereg(state, R367_ANACTRL, 0x00); /* PLL enabled and used */ -+ -+ state->master_clock = 54000000; -+ state->adc_clock = 54000000; -+ -+ state->demod_state = OFDMSet; -+ } -+ -+ state->m_bFirstTimeLock = true; -+ state->m_DemodLockTime = -1; -+ -+ // Set inversion in GAIN_SRC1 (fixed from init) -+ // is in GAIN_SRC1, see below -+ -+ GAIN_SRC1 = 0xA0; -+ // Bandwidth -+ -+ // Fixed values for 54 MHz -+ switch(state->bandwidth) { -+ case 0: -+ case 8000000: -+ // Normrate = 44384; -+ writereg(state, R367_OFDM_TRL_CTL,0x14); -+ writereg(state, R367_OFDM_TRL_NOMRATE1,0xB0); -+ writereg(state, R367_OFDM_TRL_NOMRATE2,0x56); -+ // Gain SRC = 2774 -+ writereg(state, R367_OFDM_GAIN_SRC1,0x0A | GAIN_SRC1); -+ writereg(state, R367_OFDM_GAIN_SRC2,0xD6); -+ break; -+ case 7000000: -+ // Normrate = 38836; -+ writereg(state, R367_OFDM_TRL_CTL,0x14); -+ writereg(state, R367_OFDM_TRL_NOMRATE1,0xDA); -+ writereg(state, R367_OFDM_TRL_NOMRATE2,0x4B); -+ // Gain SRC = 2427 -+ writereg(state, R367_OFDM_GAIN_SRC1,0x09 | GAIN_SRC1); -+ writereg(state, R367_OFDM_GAIN_SRC2,0x7B); -+ break; -+ case 6000000: -+ // Normrate = 33288; -+ writereg(state, R367_OFDM_TRL_CTL,0x14); -+ writereg(state, R367_OFDM_TRL_NOMRATE1,0x04); -+ writereg(state, R367_OFDM_TRL_NOMRATE2,0x41); -+ // Gain SRC = 2080 -+ writereg(state, R367_OFDM_GAIN_SRC1,0x08 | GAIN_SRC1); -+ writereg(state, R367_OFDM_GAIN_SRC2,0x20); -+ break; -+ default: -+ return -EINVAL; -+ break; -+ } -+ -+ Derot = ((IntermediateFrequency/1000) * 65536) / (state->master_clock / 1000); -+ -+ writereg(state, R367_OFDM_INC_DEROT1,(Derot>>8)); -+ writereg(state, R367_OFDM_INC_DEROT2,(Derot)); -+ -+ readreg(state, R367_OFDM_SYR_CTL,&SYR_CTL); -+ SYR_CTL &= ~0x78; -+ writereg(state, R367_OFDM_SYR_CTL,SYR_CTL); // EchoPos = 0 -+ -+ -+ writereg(state, R367_OFDM_COR_MODEGUARD,0x03); // Force = 0, Mode = 0, Guard = 3 -+ SYR_CTL &= 0x01; -+ writereg(state, R367_OFDM_SYR_CTL,SYR_CTL); // SYR_TR_DIS = 0 -+ -+ msleep(5); -+ -+ writereg(state, R367_OFDM_COR_CTL,0x20); // Start core -+ -+ // -- Begin M.V. -+ // Reset FEC and Read Solomon -+ readreg(state, R367_OFDM_SFDLYSETH,&tmp1); -+ readreg(state, R367_TSGENERAL,&tmp2); -+ writereg(state, R367_OFDM_SFDLYSETH,tmp1 | 0x08); -+ writereg(state, R367_TSGENERAL,tmp2 | 0x01); -+ // -- End M.V. -+ -+ state->m_SignalTimeOut = 200; -+ state->IF = IntermediateFrequency; -+ state->demod_state = OFDMStarted; -+ state->m_DemodTimeOut = 0; -+ state->m_FECTimeOut = 0; -+ state->m_TSTimeOut = 0; -+ -+ return status; -+} -+ -+#if 0 -+static int Stop(struct stv_state *state) -+{ -+ int status = 0; -+ -+ switch(state->demod_state) -+ { -+ case QAMStarted: -+ status = writereg(state, R367_QAM_CTRL_1,0x06); -+ state->demod_state = QAMSet; -+ break; -+ case OFDMStarted: -+ status = writereg(state, R367_OFDM_COR_CTL,0x00); -+ state->demod_state = OFDMSet; -+ break; -+ default: -+ break; -+ } -+ return status; -+} -+#endif -+ -+static s32 Log10x100(u32 x) -+{ -+ static u32 LookupTable[100] = { -+ 101157945, 103514217, 105925373, 108392691, 110917482, -+ 113501082, 116144861, 118850223, 121618600, 124451461, // 800.5 - 809.5 -+ 127350308, 130316678, 133352143, 136458314, 139636836, -+ 142889396, 146217717, 149623566, 153108746, 156675107, // 810.5 - 819.5 -+ 160324539, 164058977, 167880402, 171790839, 175792361, -+ 179887092, 184077200, 188364909, 192752491, 197242274, // 820.5 - 829.5 -+ 201836636, 206538016, 211348904, 216271852, 221309471, -+ 226464431, 231739465, 237137371, 242661010, 248313311, // 830.5 - 839.5 -+ 254097271, 260015956, 266072506, 272270131, 278612117, -+ 285101827, 291742701, 298538262, 305492111, 312607937, // 840.5 - 849.5 -+ 319889511, 327340695, 334965439, 342767787, 350751874, -+ 358921935, 367282300, 375837404, 384591782, 393550075, // 850.5 - 859.5 -+ 402717034, 412097519, 421696503, 431519077, 441570447, -+ 451855944, 462381021, 473151259, 484172368, 495450191, // 860.5 - 869.5 -+ 506990708, 518800039, 530884444, 543250331, 555904257, -+ 568852931, 582103218, 595662144, 609536897, 623734835, // 870.5 - 879.5 -+ 638263486, 653130553, 668343918, 683911647, 699841996, -+ 716143410, 732824533, 749894209, 767361489, 785235635, // 880.5 - 889.5 -+ 803526122, 822242650, 841395142, 860993752, 881048873, -+ 901571138, 922571427, 944060876, 966050879, 988553095, // 890.5 - 899.5 -+ }; -+ s32 y; -+ int i; -+ -+ if (x == 0) -+ return 0; -+ y = 800; -+ if (x >= 1000000000) { -+ x /= 10; -+ y += 100; -+ } -+ -+ while (x < 100000000) { -+ x *= 10; -+ y -= 100; -+ } -+ i = 0; -+ while (i < 100 && x > LookupTable[i]) -+ i += 1; -+ y += i; -+ return y; -+} -+ -+static int QAM_GetSignalToNoise(struct stv_state *state, s32 *pSignalToNoise) -+{ -+ u32 RegValAvg = 0; -+ u8 RegVal[2]; -+ int status = 0, i; -+ -+ *pSignalToNoise = 0; -+ for (i = 0; i < 10; i += 1 ) { -+ readregs(state, R367_QAM_EQU_SNR_LO, RegVal, 2); -+ RegValAvg += RegVal[0] + 256 * RegVal[1]; -+ } -+ if (RegValAvg != 0) { -+ s32 Power = 1; -+ switch(state->modulation) { -+ case QAM_16: -+ Power = 20480; -+ break; -+ case QAM_32: -+ Power = 23040; -+ break; -+ case QAM_64: -+ Power = 21504; -+ break; -+ case QAM_128: -+ Power = 23616; break; -+ case QAM_256: -+ Power = 21760; break; -+ default: -+ break; -+ } -+ *pSignalToNoise = Log10x100((Power * 320) / RegValAvg); -+ } else { -+ *pSignalToNoise = 380; -+ } -+ return status; -+} -+ -+static int OFDM_GetSignalToNoise(struct stv_state *state, s32 *pSignalToNoise) -+{ -+ u8 CHC_SNR = 0; -+ -+ int status = readreg(state, R367_OFDM_CHC_SNR, &CHC_SNR); -+ if (status >= 0) { -+ // Note: very unclear documentation on this. -+ // Datasheet states snr = CHC_SNR/4 dB -> way to high values! -+ // Software snr = ( 1000 * CHC_SNR ) / 8 / 32 / 10; -> to low values -+ // Comment in SW states this should be ( 1000 * CHC_SNR ) / 4 / 32 / 10; for the 367 -+ // 361/362 Datasheet: snr = CHC_SNR/8 dB -> this looks best -+ *pSignalToNoise = ( (s32)CHC_SNR * 10) / 8; -+ } -+ //printk("SNR %d\n", *pSignalToNoise); -+ return status; -+} -+ -+#if 0 -+static int DVBC_GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) -+{ -+ *pQuality = 100; -+ return 0; -+}; -+ -+static int DVBT_GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) -+{ -+ static s32 QE_SN[] = { -+ 51, // QPSK 1/2 -+ 69, // QPSK 2/3 -+ 79, // QPSK 3/4 -+ 89, // QPSK 5/6 -+ 97, // QPSK 7/8 -+ 108, // 16-QAM 1/2 -+ 131, // 16-QAM 2/3 -+ 146, // 16-QAM 3/4 -+ 156, // 16-QAM 5/6 -+ 160, // 16-QAM 7/8 -+ 165, // 64-QAM 1/2 -+ 187, // 64-QAM 2/3 -+ 202, // 64-QAM 3/4 -+ 216, // 64-QAM 5/6 -+ 225, // 64-QAM 7/8 -+ }; -+ u8 TPS_Received[2]; -+ int Constellation; -+ int CodeRate; -+ s32 SignalToNoiseRel, BERQuality; -+ -+ *pQuality = 0; -+ readregs(state, R367_OFDM_TPS_RCVD2, TPS_Received, sizeof(TPS_Received)); -+ Constellation = TPS_Received[0] & 0x03; -+ CodeRate = TPS_Received[1] & 0x07; -+ -+ if( Constellation > 2 || CodeRate > 5 ) -+ return -1; -+ SignalToNoiseRel = SignalToNoise - QE_SN[Constellation * 5 + CodeRate]; -+ BERQuality = 100; -+ -+ if( SignalToNoiseRel < -70 ) -+ *pQuality = 0; -+ else if( SignalToNoiseRel < 30 ) { -+ *pQuality = ((SignalToNoiseRel + 70) * BERQuality)/100; -+ } else -+ *pQuality = BERQuality; -+ return 0; -+}; -+ -+static s32 DVBCQuality(struct stv_state *state, s32 SignalToNoise) -+{ -+ s32 SignalToNoiseRel = 0; -+ s32 Quality = 0; -+ s32 BERQuality = 100; -+ -+ switch(state->modulation) { -+ case QAM_16: SignalToNoiseRel = SignalToNoise - 200 ; break; -+ case QAM_32: SignalToNoiseRel = SignalToNoise - 230 ; break; // Not in NorDig -+ case QAM_64: SignalToNoiseRel = SignalToNoise - 260 ; break; -+ case QAM_128: SignalToNoiseRel = SignalToNoise - 290 ; break; -+ case QAM_256: SignalToNoiseRel = SignalToNoise - 320 ; break; -+ } -+ -+ if( SignalToNoiseRel < -70 ) Quality = 0; -+ else if( SignalToNoiseRel < 30 ) -+ { -+ Quality = ((SignalToNoiseRel + 70) * BERQuality)/100; -+ } -+ else -+ Quality = BERQuality; -+ -+ return Quality; -+} -+ -+static int GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) -+{ -+ *pQuality = 0; -+ switch(state->demod_state) -+ { -+ case QAMStarted: -+ *pQuality = DVBCQuality(state, SignalToNoise); -+ break; -+ case OFDMStarted: -+ return DVBT_GetQuality(state, SignalToNoise, pQuality); -+ } -+ return 0; -+}; -+#endif -+ -+static int attach_init(struct stv_state *state) -+{ -+ int stat = 0; -+ -+ stat = readreg(state, R367_ID, &state->ID); -+ if ( stat < 0 || state->ID != 0x60 ) -+ return -ENODEV; -+ printk("stv0367 found\n"); -+ -+ writereg(state, R367_TOPCTRL, 0x10); -+ write_init_table(state, base_init); -+ write_init_table(state, qam_init); -+ -+ writereg(state, R367_TOPCTRL, 0x00); -+ write_init_table(state, ofdm_init); -+ -+ writereg(state, R367_OFDM_GAIN_SRC1, 0x2A); -+ writereg(state, R367_OFDM_GAIN_SRC2, 0xD6); -+ writereg(state, R367_OFDM_INC_DEROT1, 0x55); -+ writereg(state, R367_OFDM_INC_DEROT2, 0x55); -+ writereg(state, R367_OFDM_TRL_CTL, 0x14); -+ writereg(state, R367_OFDM_TRL_NOMRATE1, 0xAE); -+ writereg(state, R367_OFDM_TRL_NOMRATE2, 0x56); -+ writereg(state, R367_OFDM_FEPATH_CFG, 0x0); -+ -+ // OFDM TS Setup -+ -+ writereg(state, R367_OFDM_TSCFGH, 0x70); -+ writereg(state, R367_OFDM_TSCFGM, 0xC0); -+ writereg(state, R367_OFDM_TSCFGL, 0x20); -+ writereg(state, R367_OFDM_TSSPEED, 0x40); // Fixed at 54 MHz -+ //writereg(state, R367_TSTBUS, 0x80); // Invert CLK -+ -+ writereg(state, R367_OFDM_TSCFGH, 0x71); -+ writereg(state, R367_OFDM_TSCFGH, 0x70); -+ -+ writereg(state, R367_TOPCTRL, 0x10); -+ -+ // Also needed for QAM -+ writereg(state, R367_OFDM_AGC12C, 0x01); // AGC Pin setup -+ -+ writereg(state, R367_OFDM_AGCCTRL1, 0x8A); // -+ -+ // QAM TS setup, note exact format also depends on descrambler settings -+ writereg(state, R367_QAM_OUTFORMAT_0, 0x85); // Inverted Clock, Swap, serial -+ // writereg(state, R367_QAM_OUTFORMAT_1, 0x00); // -+ -+ // Clock setup -+ writereg(state, R367_ANACTRL, 0x0D); /* PLL bypassed and disabled */ -+ -+ if( state->master_clock == 58000000 ) { -+ writereg(state, R367_PLLMDIV,27); /* IC runs at 58 MHz with a 27 MHz crystal */ -+ writereg(state, R367_PLLNDIV,232); -+ } else { -+ writereg(state, R367_PLLMDIV,1); /* IC runs at 54 MHz with a 27 MHz crystal */ -+ writereg(state, R367_PLLNDIV,8); -+ } -+ writereg(state, R367_PLLSETUP, 0x18); /* ADC clock is equal to system clock */ -+ -+ // Tuner setup -+ writereg(state, R367_ANADIGCTRL, 0x8b); /* Buffer Q disabled, I Enabled, signed ADC */ -+ writereg(state, R367_DUAL_AD12, 0x04); /* ADCQ disabled */ -+ -+ writereg(state, R367_QAM_FSM_SNR2_HTH, 0x23); /* Improves the C/N lock limit */ -+ writereg(state, R367_QAM_IQ_QAM, 0x01); /* ZIF/IF Automatic mode */ -+ writereg(state, R367_QAM_EQU_FFE_LEAKAGE, 0x83); /* Improving burst noise performances */ -+ writereg(state, R367_QAM_IQDEM_ADJ_EN, 0x05); /* Improving ACI performances */ -+ -+ writereg(state, R367_ANACTRL, 0x00); /* PLL enabled and used */ -+ -+ writereg(state, R367_I2CRPT, state->I2CRPT); -+ state->demod_state = QAMSet; -+ return stat; -+} -+ -+#ifdef USE_API3 -+static void c_release(struct dvb_frontend* fe) -+#else -+static void release(struct dvb_frontend* fe) -+#endif -+{ -+ struct stv_state *state=fe->demodulator_priv; -+ printk("%s\n", __FUNCTION__); -+ kfree(state); -+} -+ -+#ifdef USE_API3 -+static int c_init (struct dvb_frontend *fe) -+{ -+ struct stv_state *state=fe->demodulator_priv; -+ -+ if (mutex_trylock(&state->ctlock)==0) -+ return -EBUSY; -+ state->omode = OM_DVBC; -+ return 0; -+} -+ -+static int c_sleep(struct dvb_frontend* fe) -+{ -+ struct stv_state *state=fe->demodulator_priv; -+ -+ mutex_unlock(&state->ctlock); -+ return 0; -+} -+#endif -+ -+static int gate_ctrl(struct dvb_frontend* fe, int enable) -+{ -+ struct stv_state *state = fe->demodulator_priv; -+ u8 i2crpt = state->I2CRPT & ~0x80; -+ -+ if (enable) -+ i2crpt |= 0x80; -+ if (writereg(state, R367_I2CRPT, i2crpt) < 0) -+ return -1; -+ state->I2CRPT = i2crpt; -+ return 0; -+} -+ -+#if 0 -+static int c_track(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -+{ -+ return DVBFE_ALGO_SEARCH_AGAIN; -+} -+#endif -+ -+#if 0 -+int (*set_property)(struct dvb_frontend* fe, struct dtv_property* tvp); -+int (*get_property)(struct dvb_frontend* fe, struct dtv_property* tvp); -+#endif -+ -+static int ofdm_lock(struct stv_state *state) -+{ -+ int status = 0; -+ u8 OFDM_Status; -+ s32 DemodTimeOut = 10; -+ s32 FECTimeOut = 0; -+ s32 TSTimeOut = 0; -+ u8 CPAMPMin = 255; -+ u8 CPAMPValue; -+ u8 SYR_STAT; -+ u8 FFTMode; -+ u8 TSStatus; -+ -+ msleep(state->m_SignalTimeOut); -+ readreg(state, R367_OFDM_STATUS,&OFDM_Status); -+ -+ if (!(OFDM_Status & 0x40)) -+ return -1; -+ //printk("lock 1\n"); -+ -+ readreg(state, R367_OFDM_SYR_STAT,&SYR_STAT); -+ FFTMode = (SYR_STAT & 0x0C) >> 2; -+ -+ switch(FFTMode) -+ { -+ case 0: // 2K -+ DemodTimeOut = 10; -+ FECTimeOut = 150; -+ TSTimeOut = 125; -+ CPAMPMin = 20; -+ break; -+ case 1: // 8K -+ DemodTimeOut = 55; -+ FECTimeOut = 600; -+ TSTimeOut = 500; -+ CPAMPMin = 80; -+ break; -+ case 2: // 4K -+ DemodTimeOut = 40; -+ FECTimeOut = 300; -+ TSTimeOut = 250; -+ CPAMPMin = 30; -+ break; -+ } -+ state->m_OFDM_FFTMode = FFTMode; -+ readreg(state, R367_OFDM_PPM_CPAMP_DIR,&CPAMPValue); -+ msleep(DemodTimeOut); -+ { -+ // Release FEC and Read Solomon Reset -+ u8 tmp1; -+ u8 tmp2; -+ readreg(state, R367_OFDM_SFDLYSETH,&tmp1); -+ readreg(state, R367_TSGENERAL,&tmp2); -+ writereg(state, R367_OFDM_SFDLYSETH,tmp1 & ~0x08); -+ writereg(state, R367_TSGENERAL,tmp2 & ~0x01); -+ } -+ msleep(FECTimeOut); -+ if( (OFDM_Status & 0x98) != 0x98 ) -+ ;//return -1; -+ //printk("lock 2\n"); -+ -+ { -+ u8 Guard = (SYR_STAT & 0x03); -+ if(Guard < 2) -+ { -+ u8 tmp; -+ readreg(state, R367_OFDM_SYR_CTL,&tmp); -+ writereg(state, R367_OFDM_SYR_CTL,tmp & ~0x04); // Clear AUTO_LE_EN -+ readreg(state, R367_OFDM_SYR_UPDATE,&tmp); -+ writereg(state, R367_OFDM_SYR_UPDATE,tmp & ~0x10); // Clear SYR_FILTER -+ } else { -+ u8 tmp; -+ readreg(state, R367_OFDM_SYR_CTL,&tmp); -+ writereg(state, R367_OFDM_SYR_CTL,tmp | 0x04); // Set AUTO_LE_EN -+ readreg(state, R367_OFDM_SYR_UPDATE,&tmp); -+ writereg(state, R367_OFDM_SYR_UPDATE,tmp | 0x10); // Set SYR_FILTER -+ } -+ -+ // apply Sfec workaround if 8K 64QAM CR!=1/2 -+ if( FFTMode == 1) -+ { -+ u8 tmp[2]; -+ readregs(state, R367_OFDM_TPS_RCVD2, tmp, 2); -+ if( ((tmp[0] & 0x03) == 0x02) && (( tmp[1] & 0x07 ) != 0) ) -+ { -+ writereg(state, R367_OFDM_SFDLYSETH,0xc0); -+ writereg(state, R367_OFDM_SFDLYSETM,0x60); -+ writereg(state, R367_OFDM_SFDLYSETL,0x00); -+ } -+ else -+ { -+ writereg(state, R367_OFDM_SFDLYSETH,0x00); -+ } -+ } -+ } -+ msleep(TSTimeOut); -+ readreg(state, R367_OFDM_TSSTATUS,&TSStatus); -+ if( (TSStatus & 0x80) != 0x80 ) -+ return -1; -+ //printk("lock 3\n"); -+ return status; -+} -+ -+ -+ -+#ifdef USE_API3 -+static int set_parameters(struct dvb_frontend *fe, -+ struct dvb_frontend_parameters *p) -+{ -+ int stat; -+ struct stv_state *state = fe->demodulator_priv; -+ u32 OF = 0; -+ u32 IF; -+ -+ if (fe->ops.tuner_ops.set_params) -+ fe->ops.tuner_ops.set_params(fe, p); -+ -+ switch (state->omode) { -+ case OM_DVBC: -+ case OM_QAM_ITU_C: -+ state->modulation = p->u.qam.modulation; -+ state->symbol_rate = p->u.qam.symbol_rate; -+ break; -+ case OM_DVBT: -+ switch (p->u.ofdm.bandwidth) { -+ case BANDWIDTH_AUTO: -+ case BANDWIDTH_8_MHZ: -+ state->bandwidth = 8000000; -+ break; -+ case BANDWIDTH_7_MHZ: -+ state->bandwidth = 7000000; -+ break; -+ case BANDWIDTH_6_MHZ: -+ state->bandwidth = 6000000; -+ break; -+ default: -+ return -EINVAL; -+ } -+ break; -+ default: -+ return -EINVAL; -+ } -+#else -+static int set_parameters(struct dvb_frontend *fe) -+{ -+ int stat; -+ struct stv_state *state = fe->demodulator_priv; -+ u32 OF = 0; -+ u32 IF; -+ -+ switch (fe->dtv_property_cache.delivery_system) { -+ case SYS_DVBC_ANNEX_A: -+ state->omode = OM_DVBC; -+ /* symbol rate 0 might cause an oops */ -+ if (fe->dtv_property_cache.symbol_rate == 0) { -+ printk(KERN_ERR "stv0367dd: Invalid symbol rate\n"); -+ return -EINVAL; -+ } -+ break; -+ case SYS_DVBT: -+ state->omode = OM_DVBT; -+ break; -+ default: -+ return -EINVAL; -+ } -+ if (fe->ops.tuner_ops.set_params) -+ fe->ops.tuner_ops.set_params(fe); -+ state->modulation = fe->dtv_property_cache.modulation; -+ state->symbol_rate = fe->dtv_property_cache.symbol_rate; -+ state->bandwidth = fe->dtv_property_cache.bandwidth_hz; -+#endif -+ fe->ops.tuner_ops.get_if_frequency(fe, &IF); -+ //fe->ops.tuner_ops.get_frequency(fe, &IF); -+ -+ switch(state->omode) { -+ case OM_DVBT: -+ stat = OFDM_Start(state, OF, IF); -+ ofdm_lock(state); -+ break; -+ case OM_DVBC: -+ case OM_QAM_ITU_C: -+ stat = QAM_Start(state, OF, IF); -+ break; -+ default: -+ stat = -EINVAL; -+ } -+ //printk("%s IF=%d OF=%d done\n", __FUNCTION__, IF, OF); -+ return stat; -+} -+ -+#if 0 -+static int c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -+{ -+ //struct stv_state *state = fe->demodulator_priv; -+ //printk("%s\n", __FUNCTION__); -+ return 0; -+} -+ -+static int OFDM_GetLockStatus(struct stv_state *state, LOCK_STATUS* pLockStatus, s32 Time) -+{ -+ int status = STATUS_SUCCESS; -+ u8 OFDM_Status; -+ s32 DemodTimeOut = 0; -+ s32 FECTimeOut = 0; -+ s32 TSTimeOut = 0; -+ u8 CPAMPMin = 255; -+ u8 CPAMPValue; -+ bool SYRLock; -+ u8 SYR_STAT; -+ u8 FFTMode; -+ u8 TSStatus; -+ -+ readreg(state, R367_OFDM_STATUS,&OFDM_Status); -+ -+ SYRLock = (OFDM_Status & 0x40) != 0; -+ -+ if( Time > m_SignalTimeOut && !SYRLock ) -+ { -+ *pLockStatus = NEVER_LOCK; -+ break; -+ } -+ -+ if( !SYRLock ) break; -+ -+ *pLockStatus = SIGNAL_PRESENT; -+ -+ // Check Mode -+ -+ readreg(state, R367_OFDM_SYR_STAT,&SYR_STAT); -+ FFTMode = (SYR_STAT & 0x0C) >> 2; -+ -+ switch(FFTMode) -+ { -+ case 0: // 2K -+ DemodTimeOut = 10; -+ FECTimeOut = 150; -+ TSTimeOut = 125; -+ CPAMPMin = 20; -+ break; -+ case 1: // 8K -+ DemodTimeOut = 55; -+ FECTimeOut = 600; -+ TSTimeOut = 500; -+ CPAMPMin = 80; -+ break; -+ case 2: // 4K -+ DemodTimeOut = 40; -+ FECTimeOut = 300; -+ TSTimeOut = 250; -+ CPAMPMin = 30; -+ break; -+ } -+ -+ m_OFDM_FFTMode = FFTMode; -+ -+ if( m_DemodTimeOut == 0 && m_bFirstTimeLock ) -+ { -+ m_DemodTimeOut = Time + DemodTimeOut; -+ //break; -+ } -+ -+ readreg(state, R367_OFDM_PPM_CPAMP_DIR,&CPAMPValue); -+ -+ if( Time <= m_DemodTimeOut && CPAMPValue < CPAMPMin ) -+ { -+ break; -+ } -+ -+ if( CPAMPValue < CPAMPMin && m_bFirstTimeLock ) -+ { -+ // initiate retry -+ *pLockStatus = NEVER_LOCK; -+ break; -+ } -+ -+ if( CPAMPValue < CPAMPMin ) break; -+ -+ *pLockStatus = DEMOD_LOCK; -+ -+ if( m_FECTimeOut == 0 && m_bFirstTimeLock ) -+ { -+ // Release FEC and Read Solomon Reset -+ u8 tmp1; -+ u8 tmp2; -+ readreg(state, R367_OFDM_SFDLYSETH,&tmp1); -+ readreg(state, R367_TSGENERAL,&tmp2); -+ writereg(state, R367_OFDM_SFDLYSETH,tmp1 & ~0x08); -+ writereg(state, R367_TSGENERAL,tmp2 & ~0x01); -+ -+ m_FECTimeOut = Time + FECTimeOut; -+ } -+ -+ // Wait for TSP_LOCK, LK, PRF -+ if( (OFDM_Status & 0x98) != 0x98 ) -+ { -+ if( Time > m_FECTimeOut ) *pLockStatus = NEVER_LOCK; -+ break; -+ } -+ -+ if( m_bFirstTimeLock && m_TSTimeOut == 0) -+ { -+ u8 Guard = (SYR_STAT & 0x03); -+ if(Guard < 2) -+ { -+ u8 tmp; -+ readreg(state, R367_OFDM_SYR_CTL,&tmp); -+ writereg(state, R367_OFDM_SYR_CTL,tmp & ~0x04); // Clear AUTO_LE_EN -+ readreg(state, R367_OFDM_SYR_UPDATE,&tmp); -+ writereg(state, R367_OFDM_SYR_UPDATE,tmp & ~0x10); // Clear SYR_FILTER -+ } else { -+ u8 tmp; -+ readreg(state, R367_OFDM_SYR_CTL,&tmp); -+ writereg(state, R367_OFDM_SYR_CTL,tmp | 0x04); // Set AUTO_LE_EN -+ readreg(state, R367_OFDM_SYR_UPDATE,&tmp); -+ writereg(state, R367_OFDM_SYR_UPDATE,tmp | 0x10); // Set SYR_FILTER -+ } -+ -+ // apply Sfec workaround if 8K 64QAM CR!=1/2 -+ if( FFTMode == 1) -+ { -+ u8 tmp[2]; -+ readreg(state, R367_OFDM_TPS_RCVD2,tmp,2); -+ if( ((tmp[0] & 0x03) == 0x02) && (( tmp[1] & 0x07 ) != 0) ) -+ { -+ writereg(state, R367_OFDM_SFDLYSETH,0xc0); -+ writereg(state, R367_OFDM_SFDLYSETM,0x60); -+ writereg(state, R367_OFDM_SFDLYSETL,0x00); -+ } -+ else -+ { -+ writereg(state, R367_OFDM_SFDLYSETH,0x00); -+ } -+ } -+ -+ m_TSTimeOut = Time + TSTimeOut; -+ } -+ readreg(state, R367_OFDM_TSSTATUS,&TSStatus); -+ if( (TSStatus & 0x80) != 0x80 ) -+ { -+ if( Time > m_TSTimeOut ) *pLockStatus = NEVER_LOCK; -+ break; -+ } -+ *pLockStatus = MPEG_LOCK; -+ m_bFirstTimeLock = false; -+ return status; -+} -+ -+#endif -+ -+static int read_status(struct dvb_frontend *fe, fe_status_t *status) -+{ -+ struct stv_state *state = fe->demodulator_priv; -+ *status=0; -+ -+ switch(state->demod_state) { -+ case QAMStarted: -+ { -+ u8 FEC_Lock; -+ u8 QAM_Lock; -+ -+ readreg(state, R367_QAM_FSM_STS, &QAM_Lock); -+ QAM_Lock &= 0x0F; -+ if (QAM_Lock >10) -+ *status|=0x07; -+ readreg(state, R367_QAM_FEC_STATUS,&FEC_Lock); -+ if (FEC_Lock&2) -+ *status|=0x1f; -+ if (state->m_bFirstTimeLock) { -+ state->m_bFirstTimeLock = false; -+ // QAM_AGC_ACCUMRSTSEL to Tracking; -+ writereg(state, R367_QAM_AGC_CTL, state->m_Save_QAM_AGC_CTL); -+ } -+ break; -+ } -+ case OFDMStarted: -+ { -+ u8 OFDM_Status; -+ u8 TSStatus; -+ -+ readreg(state, R367_OFDM_TSSTATUS, &TSStatus); -+ -+ readreg(state, R367_OFDM_STATUS, &OFDM_Status); -+ if (OFDM_Status & 0x40) -+ *status |= FE_HAS_SIGNAL; -+ -+ if ((OFDM_Status & 0x98) == 0x98) -+ *status|=0x0f; -+ -+ if (TSStatus & 0x80) -+ *status |= 0x1f; -+ break; -+ } -+ default: -+ break; -+ } -+ return 0; -+} -+ -+static int read_ber(struct dvb_frontend *fe, u32 *ber) -+{ -+ //struct stv_state *state = fe->demodulator_priv; -+ *ber=0; -+ return 0; -+} -+ -+static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) -+{ -+ if (fe->ops.tuner_ops.get_rf_strength) -+ fe->ops.tuner_ops.get_rf_strength(fe, strength); -+ else -+ *strength = 0; -+ return 0; -+} -+ -+static int read_snr(struct dvb_frontend *fe, u16 *snr) -+{ -+ struct stv_state *state = fe->demodulator_priv; -+ s32 snr2 = 0; -+ -+ switch(state->demod_state) { -+ case QAMStarted: -+ QAM_GetSignalToNoise(state, &snr2); -+ break; -+ case OFDMStarted: -+ OFDM_GetSignalToNoise(state, &snr2); -+ break; -+ default: -+ break; -+ } -+ *snr = snr2&0xffff; -+ return 0; -+} -+ -+static int read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -+{ -+ struct stv_state *state = fe->demodulator_priv; -+ u8 errl, errm, errh; -+ u8 val; -+ -+ switch(state->demod_state) { -+ case QAMStarted: -+ readreg(state, R367_QAM_RS_COUNTER_4, &errl); -+ readreg(state, R367_QAM_RS_COUNTER_5, &errm); -+ *ucblocks = (errm << 8) | errl; -+ break; -+ case OFDMStarted: -+ readreg(state, R367_OFDM_SFERRCNTH, &val); -+ if ((val & 0x80) == 0) { -+ readreg(state, R367_OFDM_ERRCNT1H, &errh); -+ readreg(state, R367_OFDM_ERRCNT1M, &errl); -+ readreg(state, R367_OFDM_ERRCNT1L, &errm); -+ state->ucblocks = (errh <<16) | (errm << 8) | errl; -+ } -+ *ucblocks = state->ucblocks; -+ break; -+ default: -+ *ucblocks = 0; -+ break; -+ } -+ return 0; -+} -+ -+static int c_get_tune_settings(struct dvb_frontend *fe, -+ struct dvb_frontend_tune_settings *sets) -+{ -+ sets->min_delay_ms=3000; -+ sets->max_drift=0; -+ sets->step_size=0; -+ return 0; -+} -+ -+#ifndef USE_API3 -+static int get_tune_settings(struct dvb_frontend *fe, -+ struct dvb_frontend_tune_settings *sets) -+{ -+ switch (fe->dtv_property_cache.delivery_system) { -+ case SYS_DVBC_ANNEX_A: -+ case SYS_DVBC_ANNEX_C: -+ return c_get_tune_settings(fe, sets); -+ default: -+ /* DVB-T: Use info.frequency_stepsize. */ -+ return -EINVAL; -+ } -+} -+#endif -+ -+#ifdef USE_API3 -+static void t_release(struct dvb_frontend* fe) -+{ -+ //struct stv_state *state=fe->demodulator_priv; -+ //printk("%s\n", __FUNCTION__); -+ //kfree(state); -+} -+ -+static int t_init (struct dvb_frontend *fe) -+{ -+ struct stv_state *state=fe->demodulator_priv; -+ if (mutex_trylock(&state->ctlock)==0) -+ return -EBUSY; -+ state->omode = OM_DVBT; -+ return 0; -+} -+ -+static int t_sleep(struct dvb_frontend* fe) -+{ -+ struct stv_state *state=fe->demodulator_priv; -+ mutex_unlock(&state->ctlock); -+ return 0; -+} -+#endif -+ -+#if 0 -+static int t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -+{ -+ //struct stv_state *state = fe->demodulator_priv; -+ //printk("%s\n", __FUNCTION__); -+ return 0; -+} -+ -+static enum dvbfe_algo algo(struct dvb_frontend *fe) -+{ -+ return DVBFE_ALGO_CUSTOM; -+} -+#endif -+ -+#ifdef USE_API3 -+static struct dvb_frontend_ops c_ops = { -+ .info = { -+ .name = "STV0367 DVB-C", -+ .type = FE_QAM, -+ .frequency_stepsize = 62500, -+ .frequency_min = 47000000, -+ .frequency_max = 862000000, -+ .symbol_rate_min = 870000, -+ .symbol_rate_max = 11700000, -+ .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | -+ FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO -+ }, -+ .release = c_release, -+ .init = c_init, -+ .sleep = c_sleep, -+ .i2c_gate_ctrl = gate_ctrl, -+ -+ .get_tune_settings = c_get_tune_settings, -+ -+ .read_status = read_status, -+ .read_ber = read_ber, -+ .read_signal_strength = read_signal_strength, -+ .read_snr = read_snr, -+ .read_ucblocks = read_ucblocks, -+ -+#if 1 -+ .set_frontend = set_parameters, -+#else -+ .get_frontend_algo = algo, -+ .search = search, -+#endif -+}; -+ -+static struct dvb_frontend_ops t_ops = { -+ .info = { -+ .name = "STV0367 DVB-T", -+ .type = FE_OFDM, -+ .frequency_min = 47125000, -+ .frequency_max = 865000000, -+ .frequency_stepsize = 166667, -+ .frequency_tolerance = 0, -+ .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | -+ FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | -+ FE_CAN_FEC_AUTO | -+ FE_CAN_QAM_16 | FE_CAN_QAM_64 | -+ FE_CAN_QAM_AUTO | -+ FE_CAN_TRANSMISSION_MODE_AUTO | -+ FE_CAN_GUARD_INTERVAL_AUTO | -+ FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | -+ FE_CAN_MUTE_TS -+ }, -+ .release = t_release, -+ .init = t_init, -+ .sleep = t_sleep, -+ .i2c_gate_ctrl = gate_ctrl, -+ -+ .set_frontend = set_parameters, -+ -+ .read_status = read_status, -+ .read_ber = read_ber, -+ .read_signal_strength = read_signal_strength, -+ .read_snr = read_snr, -+ .read_ucblocks = read_ucblocks, -+}; -+ -+#else -+ -+static struct dvb_frontend_ops common_ops = { -+ .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT }, -+ .info = { -+ .name = "STV0367 DVB-C DVB-T", -+ .frequency_stepsize = 166667, /* DVB-T only */ -+ .frequency_min = 47000000, /* DVB-T: 47125000 */ -+ .frequency_max = 865000000, /* DVB-C: 862000000 */ -+ .symbol_rate_min = 870000, -+ .symbol_rate_max = 11700000, -+ .caps = /* DVB-C */ -+ FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | -+ FE_CAN_QAM_128 | FE_CAN_QAM_256 | -+ FE_CAN_FEC_AUTO | -+ /* DVB-T */ -+ FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | -+ FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | -+ FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | -+ FE_CAN_TRANSMISSION_MODE_AUTO | -+ FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | -+ FE_CAN_RECOVER | FE_CAN_MUTE_TS -+ }, -+ .release = release, -+ .i2c_gate_ctrl = gate_ctrl, -+ -+ .get_tune_settings = get_tune_settings, -+ -+ .set_frontend = set_parameters, -+ -+ .read_status = read_status, -+ .read_ber = read_ber, -+ .read_signal_strength = read_signal_strength, -+ .read_snr = read_snr, -+ .read_ucblocks = read_ucblocks, -+}; -+#endif -+ -+ -+static void init_state(struct stv_state *state, struct stv0367_cfg *cfg) -+{ -+ u32 ulENARPTLEVEL = 5; -+ u32 ulQAMInversion = 2; -+ state->omode = OM_NONE; -+ state->adr = cfg->adr; -+ -+ mutex_init(&state->mutex); -+ mutex_init(&state->ctlock); -+ -+#ifdef USE_API3 -+ memcpy(&state->c_frontend.ops, &c_ops, sizeof(struct dvb_frontend_ops)); -+ memcpy(&state->t_frontend.ops, &t_ops, sizeof(struct dvb_frontend_ops)); -+ state->c_frontend.demodulator_priv = state; -+ state->t_frontend.demodulator_priv = state; -+#else -+ memcpy(&state->frontend.ops, &common_ops, sizeof(struct dvb_frontend_ops)); -+ state->frontend.demodulator_priv = state; -+#endif -+ -+ state->master_clock = 58000000; -+ state->adc_clock = 58000000; -+ state->I2CRPT = 0x08 | ((ulENARPTLEVEL & 0x07) << 4); -+ state->qam_inversion = ((ulQAMInversion & 3) << 6 ); -+ state->demod_state = Off; -+} -+ -+ -+struct dvb_frontend *stv0367_attach(struct i2c_adapter *i2c, struct stv0367_cfg *cfg, -+ struct dvb_frontend **fe_t) -+{ -+ struct stv_state *state = NULL; -+ -+ state = kzalloc(sizeof(struct stv_state), GFP_KERNEL); -+ if (!state) -+ return NULL; -+ -+ state->i2c = i2c; -+ init_state(state, cfg); -+ -+ if (attach_init(state)<0) -+ goto error; -+#ifdef USE_API3 -+ *fe_t = &state->t_frontend; -+ return &state->c_frontend; -+#else -+ return &state->frontend; -+#endif -+ -+error: -+ printk("stv0367: not found\n"); -+ kfree(state); -+ return NULL; -+} -+ -+ -+MODULE_DESCRIPTION("STV0367DD driver"); -+MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); -+MODULE_LICENSE("GPL"); -+ -+EXPORT_SYMBOL(stv0367_attach); -+ -+ -+ -diff --git a/drivers/media/dvb-frontends/stv0367dd.h b/drivers/media/dvb-frontends/stv0367dd.h -new file mode 100644 -index 0000000..665d4c8 ---- /dev/null -+++ b/drivers/media/dvb-frontends/stv0367dd.h -@@ -0,0 +1,17 @@ -+#ifndef _STV0367DD_H_ -+#define _STV0367DD_H_ -+ -+#include -+#include -+ -+struct stv0367_cfg { -+ u8 adr; -+ u32 xtal; -+ u32 ts_mode; -+}; -+ -+ -+extern struct dvb_frontend *stv0367_attach(struct i2c_adapter *i2c, -+ struct stv0367_cfg *cfg, -+ struct dvb_frontend **fe_t); -+#endif -diff --git a/drivers/media/dvb-frontends/stv0367dd_regs.h b/drivers/media/dvb-frontends/stv0367dd_regs.h -new file mode 100644 -index 0000000..f33e787 ---- /dev/null -+++ b/drivers/media/dvb-frontends/stv0367dd_regs.h -@@ -0,0 +1,3431 @@ -+// @DVB-C/DVB-T STMicroelectronics STV0367 register defintions -+// Author Manfred Völkel, Februar 2011 -+// (c) 2010 DigitalDevices GmbH Germany. All rights reserved -+ -+// $Id: DD_STV0367Register.h 357 2011-04-27 02:39:13Z manfred $ -+ -+/* ======================================================================= -+ -- Registers Declaration -+ -- ------------------------- -+ -- Each register (R367_XXXXX) is defined by its address (2 bytes). -+ -- -+ -- Each field (F367_XXXXX)is defined as follow: -+ -- [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] -+ ======================================================================= */ -+ -+/* ID */ -+#define R367_ID 0xF000 -+#define F367_IDENTIFICATIONREG 0xF00000FF -+ -+/* I2CRPT */ -+#define R367_I2CRPT 0xF001 -+#define F367_I2CT_ON 0xF0010080 -+#define F367_ENARPT_LEVEL 0xF0010070 -+#define F367_SCLT_DELAY 0xF0010008 -+#define F367_SCLT_NOD 0xF0010004 -+#define F367_STOP_ENABLE 0xF0010002 -+#define F367_SDAT_NOD 0xF0010001 -+ -+/* TOPCTRL */ -+#define R367_TOPCTRL 0xF002 -+#define F367_STDBY 0xF0020080 -+#define F367_STDBY_FEC 0xF0020040 -+#define F367_STDBY_CORE 0xF0020020 -+#define F367_QAM_COFDM 0xF0020010 -+#define F367_TS_DIS 0xF0020008 -+#define F367_DIR_CLK_216 0xF0020004 -+#define F367_TUNER_BB 0xF0020002 -+#define F367_DVBT_H 0xF0020001 -+ -+/* IOCFG0 */ -+#define R367_IOCFG0 0xF003 -+#define F367_OP0_SD 0xF0030080 -+#define F367_OP0_VAL 0xF0030040 -+#define F367_OP0_OD 0xF0030020 -+#define F367_OP0_INV 0xF0030010 -+#define F367_OP0_DACVALUE_HI 0xF003000F -+ -+/* DAC0R */ -+#define R367_DAC0R 0xF004 -+#define F367_OP0_DACVALUE_LO 0xF00400FF -+ -+/* IOCFG1 */ -+#define R367_IOCFG1 0xF005 -+#define F367_IP0 0xF0050040 -+#define F367_OP1_OD 0xF0050020 -+#define F367_OP1_INV 0xF0050010 -+#define F367_OP1_DACVALUE_HI 0xF005000F -+ -+/* DAC1R */ -+#define R367_DAC1R 0xF006 -+#define F367_OP1_DACVALUE_LO 0xF00600FF -+ -+/* IOCFG2 */ -+#define R367_IOCFG2 0xF007 -+#define F367_OP2_LOCK_CONF 0xF00700E0 -+#define F367_OP2_OD 0xF0070010 -+#define F367_OP2_VAL 0xF0070008 -+#define F367_OP1_LOCK_CONF 0xF0070007 -+ -+/* SDFR */ -+#define R367_SDFR 0xF008 -+#define F367_OP0_FREQ 0xF00800F0 -+#define F367_OP1_FREQ 0xF008000F -+ -+/* STATUS */ -+#define R367_OFDM_STATUS 0xF009 -+#define F367_TPS_LOCK 0xF0090080 -+#define F367_SYR_LOCK 0xF0090040 -+#define F367_AGC_LOCK 0xF0090020 -+#define F367_PRF 0xF0090010 -+#define F367_LK 0xF0090008 -+#define F367_PR 0xF0090007 -+ -+/* AUX_CLK */ -+#define R367_AUX_CLK 0xF00A -+#define F367_AUXFEC_CTL 0xF00A00C0 -+#define F367_DIS_CKX4 0xF00A0020 -+#define F367_CKSEL 0xF00A0018 -+#define F367_CKDIV_PROG 0xF00A0006 -+#define F367_AUXCLK_ENA 0xF00A0001 -+ -+/* FREESYS1 */ -+#define R367_FREESYS1 0xF00B -+#define F367_FREE_SYS1 0xF00B00FF -+ -+/* FREESYS2 */ -+#define R367_FREESYS2 0xF00C -+#define F367_FREE_SYS2 0xF00C00FF -+ -+/* FREESYS3 */ -+#define R367_FREESYS3 0xF00D -+#define F367_FREE_SYS3 0xF00D00FF -+ -+/* GPIO_CFG */ -+#define R367_GPIO_CFG 0xF00E -+#define F367_GPIO7_NOD 0xF00E0080 -+#define F367_GPIO7_CFG 0xF00E0040 -+#define F367_GPIO6_NOD 0xF00E0020 -+#define F367_GPIO6_CFG 0xF00E0010 -+#define F367_GPIO5_NOD 0xF00E0008 -+#define F367_GPIO5_CFG 0xF00E0004 -+#define F367_GPIO4_NOD 0xF00E0002 -+#define F367_GPIO4_CFG 0xF00E0001 -+ -+/* GPIO_CMD */ -+#define R367_GPIO_CMD 0xF00F -+#define F367_GPIO7_VAL 0xF00F0008 -+#define F367_GPIO6_VAL 0xF00F0004 -+#define F367_GPIO5_VAL 0xF00F0002 -+#define F367_GPIO4_VAL 0xF00F0001 -+ -+/* AGC2MAX */ -+#define R367_OFDM_AGC2MAX 0xF010 -+#define F367_OFDM_AGC2_MAX 0xF01000FF -+ -+/* AGC2MIN */ -+#define R367_OFDM_AGC2MIN 0xF011 -+#define F367_OFDM_AGC2_MIN 0xF01100FF -+ -+/* AGC1MAX */ -+#define R367_OFDM_AGC1MAX 0xF012 -+#define F367_OFDM_AGC1_MAX 0xF01200FF -+ -+/* AGC1MIN */ -+#define R367_OFDM_AGC1MIN 0xF013 -+#define F367_OFDM_AGC1_MIN 0xF01300FF -+ -+/* AGCR */ -+#define R367_OFDM_AGCR 0xF014 -+#define F367_OFDM_RATIO_A 0xF01400E0 -+#define F367_OFDM_RATIO_B 0xF0140018 -+#define F367_OFDM_RATIO_C 0xF0140007 -+ -+/* AGC2TH */ -+#define R367_OFDM_AGC2TH 0xF015 -+#define F367_OFDM_AGC2_THRES 0xF01500FF -+ -+/* AGC12C */ -+#define R367_OFDM_AGC12C 0xF016 -+#define F367_OFDM_AGC1_IV 0xF0160080 -+#define F367_OFDM_AGC1_OD 0xF0160040 -+#define F367_OFDM_AGC1_LOAD 0xF0160020 -+#define F367_OFDM_AGC2_IV 0xF0160010 -+#define F367_OFDM_AGC2_OD 0xF0160008 -+#define F367_OFDM_AGC2_LOAD 0xF0160004 -+#define F367_OFDM_AGC12_MODE 0xF0160003 -+ -+/* AGCCTRL1 */ -+#define R367_OFDM_AGCCTRL1 0xF017 -+#define F367_OFDM_DAGC_ON 0xF0170080 -+#define F367_OFDM_INVERT_AGC12 0xF0170040 -+#define F367_OFDM_AGC1_MODE 0xF0170008 -+#define F367_OFDM_AGC2_MODE 0xF0170007 -+ -+/* AGCCTRL2 */ -+#define R367_OFDM_AGCCTRL2 0xF018 -+#define F367_OFDM_FRZ2_CTRL 0xF0180060 -+#define F367_OFDM_FRZ1_CTRL 0xF0180018 -+#define F367_OFDM_TIME_CST 0xF0180007 -+ -+/* AGC1VAL1 */ -+#define R367_OFDM_AGC1VAL1 0xF019 -+#define F367_OFDM_AGC1_VAL_LO 0xF01900FF -+ -+/* AGC1VAL2 */ -+#define R367_OFDM_AGC1VAL2 0xF01A -+#define F367_OFDM_AGC1_VAL_HI 0xF01A000F -+ -+/* AGC2VAL1 */ -+#define R367_OFDM_AGC2VAL1 0xF01B -+#define F367_OFDM_AGC2_VAL_LO 0xF01B00FF -+ -+/* AGC2VAL2 */ -+#define R367_OFDM_AGC2VAL2 0xF01C -+#define F367_OFDM_AGC2_VAL_HI 0xF01C000F -+ -+/* AGC2PGA */ -+#define R367_OFDM_AGC2PGA 0xF01D -+#define F367_OFDM_AGC2_PGA 0xF01D00FF -+ -+/* OVF_RATE1 */ -+#define R367_OFDM_OVF_RATE1 0xF01E -+#define F367_OFDM_OVF_RATE_HI 0xF01E000F -+ -+/* OVF_RATE2 */ -+#define R367_OFDM_OVF_RATE2 0xF01F -+#define F367_OFDM_OVF_RATE_LO 0xF01F00FF -+ -+/* GAIN_SRC1 */ -+#define R367_OFDM_GAIN_SRC1 0xF020 -+#define F367_OFDM_INV_SPECTR 0xF0200080 -+#define F367_OFDM_IQ_INVERT 0xF0200040 -+#define F367_OFDM_INR_BYPASS 0xF0200020 -+#define F367_OFDM_STATUS_INV_SPECRUM 0xF0200010 -+#define F367_OFDM_GAIN_SRC_HI 0xF020000F -+ -+/* GAIN_SRC2 */ -+#define R367_OFDM_GAIN_SRC2 0xF021 -+#define F367_OFDM_GAIN_SRC_LO 0xF02100FF -+ -+/* INC_DEROT1 */ -+#define R367_OFDM_INC_DEROT1 0xF022 -+#define F367_OFDM_INC_DEROT_HI 0xF02200FF -+ -+/* INC_DEROT2 */ -+#define R367_OFDM_INC_DEROT2 0xF023 -+#define F367_OFDM_INC_DEROT_LO 0xF02300FF -+ -+/* PPM_CPAMP_DIR */ -+#define R367_OFDM_PPM_CPAMP_DIR 0xF024 -+#define F367_OFDM_PPM_CPAMP_DIRECT 0xF02400FF -+ -+/* PPM_CPAMP_INV */ -+#define R367_OFDM_PPM_CPAMP_INV 0xF025 -+#define F367_OFDM_PPM_CPAMP_INVER 0xF02500FF -+ -+/* FREESTFE_1 */ -+#define R367_OFDM_FREESTFE_1 0xF026 -+#define F367_OFDM_SYMBOL_NUMBER_INC 0xF02600C0 -+#define F367_OFDM_SEL_LSB 0xF0260004 -+#define F367_OFDM_AVERAGE_ON 0xF0260002 -+#define F367_OFDM_DC_ADJ 0xF0260001 -+ -+/* FREESTFE_2 */ -+#define R367_OFDM_FREESTFE_2 0xF027 -+#define F367_OFDM_SEL_SRCOUT 0xF02700C0 -+#define F367_OFDM_SEL_SYRTHR 0xF027001F -+ -+/* DCOFFSET */ -+#define R367_OFDM_DCOFFSET 0xF028 -+#define F367_OFDM_SELECT_I_Q 0xF0280080 -+#define F367_OFDM_DC_OFFSET 0xF028007F -+ -+/* EN_PROCESS */ -+#define R367_OFDM_EN_PROCESS 0xF029 -+#define F367_OFDM_FREE 0xF02900F0 -+#define F367_OFDM_ENAB_MANUAL 0xF0290001 -+ -+/* SDI_SMOOTHER */ -+#define R367_OFDM_SDI_SMOOTHER 0xF02A -+#define F367_OFDM_DIS_SMOOTH 0xF02A0080 -+#define F367_OFDM_SDI_INC_SMOOTHER 0xF02A007F -+ -+/* FE_LOOP_OPEN */ -+#define R367_OFDM_FE_LOOP_OPEN 0xF02B -+#define F367_OFDM_TRL_LOOP_OP 0xF02B0002 -+#define F367_OFDM_CRL_LOOP_OP 0xF02B0001 -+ -+/* FREQOFF1 */ -+#define R367_OFDM_FREQOFF1 0xF02C -+#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_VHI 0xF02C00FF -+ -+/* FREQOFF2 */ -+#define R367_OFDM_FREQOFF2 0xF02D -+#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_HI 0xF02D00FF -+ -+/* FREQOFF3 */ -+#define R367_OFDM_FREQOFF3 0xF02E -+#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_LO 0xF02E00FF -+ -+/* TIMOFF1 */ -+#define R367_OFDM_TIMOFF1 0xF02F -+#define F367_OFDM_TIM_OFFSET_LOOP_OPEN_HI 0xF02F00FF -+ -+/* TIMOFF2 */ -+#define R367_OFDM_TIMOFF2 0xF030 -+#define F367_OFDM_TIM_OFFSET_LOOP_OPEN_LO 0xF03000FF -+ -+/* EPQ */ -+#define R367_OFDM_EPQ 0xF031 -+#define F367_OFDM_EPQ1 0xF03100FF -+ -+/* EPQAUTO */ -+#define R367_OFDM_EPQAUTO 0xF032 -+#define F367_OFDM_EPQ2 0xF03200FF -+ -+/* SYR_UPDATE */ -+#define R367_OFDM_SYR_UPDATE 0xF033 -+#define F367_OFDM_SYR_PROTV 0xF0330080 -+#define F367_OFDM_SYR_PROTV_GAIN 0xF0330060 -+#define F367_OFDM_SYR_FILTER 0xF0330010 -+#define F367_OFDM_SYR_TRACK_THRES 0xF033000C -+ -+/* CHPFREE */ -+#define R367_OFDM_CHPFREE 0xF034 -+#define F367_OFDM_CHP_FREE 0xF03400FF -+ -+/* PPM_STATE_MAC */ -+#define R367_OFDM_PPM_STATE_MAC 0xF035 -+#define F367_OFDM_PPM_STATE_MACHINE_DECODER 0xF035003F -+ -+/* INR_THRESHOLD */ -+#define R367_OFDM_INR_THRESHOLD 0xF036 -+#define F367_OFDM_INR_THRESH 0xF03600FF -+ -+/* EPQ_TPS_ID_CELL */ -+#define R367_OFDM_EPQ_TPS_ID_CELL 0xF037 -+#define F367_OFDM_ENABLE_LGTH_TO_CF 0xF0370080 -+#define F367_OFDM_DIS_TPS_RSVD 0xF0370040 -+#define F367_OFDM_DIS_BCH 0xF0370020 -+#define F367_OFDM_DIS_ID_CEL 0xF0370010 -+#define F367_OFDM_TPS_ADJUST_SYM 0xF037000F -+ -+/* EPQ_CFG */ -+#define R367_OFDM_EPQ_CFG 0xF038 -+#define F367_OFDM_EPQ_RANGE 0xF0380002 -+#define F367_OFDM_EPQ_SOFT 0xF0380001 -+ -+/* EPQ_STATUS */ -+#define R367_OFDM_EPQ_STATUS 0xF039 -+#define F367_OFDM_SLOPE_INC 0xF03900FC -+#define F367_OFDM_TPS_FIELD 0xF0390003 -+ -+/* AUTORELOCK */ -+#define R367_OFDM_AUTORELOCK 0xF03A -+#define F367_OFDM_BYPASS_BER_TEMPO 0xF03A0080 -+#define F367_OFDM_BER_TEMPO 0xF03A0070 -+#define F367_OFDM_BYPASS_COFDM_TEMPO 0xF03A0008 -+#define F367_OFDM_COFDM_TEMPO 0xF03A0007 -+ -+/* BER_THR_VMSB */ -+#define R367_OFDM_BER_THR_VMSB 0xF03B -+#define F367_OFDM_BER_THRESHOLD_HI 0xF03B00FF -+ -+/* BER_THR_MSB */ -+#define R367_OFDM_BER_THR_MSB 0xF03C -+#define F367_OFDM_BER_THRESHOLD_MID 0xF03C00FF -+ -+/* BER_THR_LSB */ -+#define R367_OFDM_BER_THR_LSB 0xF03D -+#define F367_OFDM_BER_THRESHOLD_LO 0xF03D00FF -+ -+/* CCD */ -+#define R367_OFDM_CCD 0xF03E -+#define F367_OFDM_CCD_DETECTED 0xF03E0080 -+#define F367_OFDM_CCD_RESET 0xF03E0040 -+#define F367_OFDM_CCD_THRESHOLD 0xF03E000F -+ -+/* SPECTR_CFG */ -+#define R367_OFDM_SPECTR_CFG 0xF03F -+#define F367_OFDM_SPECT_CFG 0xF03F0003 -+ -+/* CONSTMU_MSB */ -+#define R367_OFDM_CONSTMU_MSB 0xF040 -+#define F367_OFDM_CONSTMU_FREEZE 0xF0400080 -+#define F367_OFDM_CONSTNU_FORCE_EN 0xF0400040 -+#define F367_OFDM_CONST_MU_MSB 0xF040003F -+ -+/* CONSTMU_LSB */ -+#define R367_OFDM_CONSTMU_LSB 0xF041 -+#define F367_OFDM_CONST_MU_LSB 0xF04100FF -+ -+/* CONSTMU_MAX_MSB */ -+#define R367_OFDM_CONSTMU_MAX_MSB 0xF042 -+#define F367_OFDM_CONST_MU_MAX_MSB 0xF042003F -+ -+/* CONSTMU_MAX_LSB */ -+#define R367_OFDM_CONSTMU_MAX_LSB 0xF043 -+#define F367_OFDM_CONST_MU_MAX_LSB 0xF04300FF -+ -+/* ALPHANOISE */ -+#define R367_OFDM_ALPHANOISE 0xF044 -+#define F367_OFDM_USE_ALLFILTER 0xF0440080 -+#define F367_OFDM_INTER_ON 0xF0440040 -+#define F367_OFDM_ALPHA_NOISE 0xF044001F -+ -+/* MAXGP_MSB */ -+#define R367_OFDM_MAXGP_MSB 0xF045 -+#define F367_OFDM_MUFILTER_LENGTH 0xF04500F0 -+#define F367_OFDM_MAX_GP_MSB 0xF045000F -+ -+/* MAXGP_LSB */ -+#define R367_OFDM_MAXGP_LSB 0xF046 -+#define F367_OFDM_MAX_GP_LSB 0xF04600FF -+ -+/* ALPHAMSB */ -+#define R367_OFDM_ALPHAMSB 0xF047 -+#define F367_OFDM_CHC_DATARATE 0xF04700C0 -+#define F367_OFDM_ALPHA_MSB 0xF047003F -+ -+/* ALPHALSB */ -+#define R367_OFDM_ALPHALSB 0xF048 -+#define F367_OFDM_ALPHA_LSB 0xF04800FF -+ -+/* PILOT_ACCU */ -+#define R367_OFDM_PILOT_ACCU 0xF049 -+#define F367_OFDM_USE_SCAT4ADDAPT 0xF0490080 -+#define F367_OFDM_PILOT_ACC 0xF049001F -+ -+/* PILOTMU_ACCU */ -+#define R367_OFDM_PILOTMU_ACCU 0xF04A -+#define F367_OFDM_DISCARD_BAD_SP 0xF04A0080 -+#define F367_OFDM_DISCARD_BAD_CP 0xF04A0040 -+#define F367_OFDM_PILOT_MU_ACCU 0xF04A001F -+ -+/* FILT_CHANNEL_EST */ -+#define R367_OFDM_FILT_CHANNEL_EST 0xF04B -+#define F367_OFDM_USE_FILT_PILOT 0xF04B0080 -+#define F367_OFDM_FILT_CHANNEL 0xF04B007F -+ -+/* ALPHA_NOPISE_FREQ */ -+#define R367_OFDM_ALPHA_NOPISE_FREQ 0xF04C -+#define F367_OFDM_NOISE_FREQ_FILT 0xF04C0040 -+#define F367_OFDM_ALPHA_NOISE_FREQ 0xF04C003F -+ -+/* RATIO_PILOT */ -+#define R367_OFDM_RATIO_PILOT 0xF04D -+#define F367_OFDM_RATIO_MEAN_SP 0xF04D00F0 -+#define F367_OFDM_RATIO_MEAN_CP 0xF04D000F -+ -+/* CHC_CTL */ -+#define R367_OFDM_CHC_CTL 0xF04E -+#define F367_OFDM_TRACK_EN 0xF04E0080 -+#define F367_OFDM_NOISE_NORM_EN 0xF04E0040 -+#define F367_OFDM_FORCE_CHC_RESET 0xF04E0020 -+#define F367_OFDM_SHORT_TIME 0xF04E0010 -+#define F367_OFDM_FORCE_STATE_EN 0xF04E0008 -+#define F367_OFDM_FORCE_STATE 0xF04E0007 -+ -+/* EPQ_ADJUST */ -+#define R367_OFDM_EPQ_ADJUST 0xF04F -+#define F367_OFDM_ADJUST_SCAT_IND 0xF04F00C0 -+#define F367_OFDM_ONE_SYMBOL 0xF04F0010 -+#define F367_OFDM_EPQ_DECAY 0xF04F000E -+#define F367_OFDM_HOLD_SLOPE 0xF04F0001 -+ -+/* EPQ_THRES */ -+#define R367_OFDM_EPQ_THRES 0xF050 -+#define F367_OFDM_EPQ_THR 0xF05000FF -+ -+/* OMEGA_CTL */ -+#define R367_OFDM_OMEGA_CTL 0xF051 -+#define F367_OFDM_OMEGA_RST 0xF0510080 -+#define F367_OFDM_FREEZE_OMEGA 0xF0510040 -+#define F367_OFDM_OMEGA_SEL 0xF051003F -+ -+/* GP_CTL */ -+#define R367_OFDM_GP_CTL 0xF052 -+#define F367_OFDM_CHC_STATE 0xF05200E0 -+#define F367_OFDM_FREEZE_GP 0xF0520010 -+#define F367_OFDM_GP_SEL 0xF052000F -+ -+/* MUMSB */ -+#define R367_OFDM_MUMSB 0xF053 -+#define F367_OFDM_MU_MSB 0xF053007F -+ -+/* MULSB */ -+#define R367_OFDM_MULSB 0xF054 -+#define F367_OFDM_MU_LSB 0xF05400FF -+ -+/* GPMSB */ -+#define R367_OFDM_GPMSB 0xF055 -+#define F367_OFDM_CSI_THRESHOLD 0xF05500E0 -+#define F367_OFDM_GP_MSB 0xF055000F -+ -+/* GPLSB */ -+#define R367_OFDM_GPLSB 0xF056 -+#define F367_OFDM_GP_LSB 0xF05600FF -+ -+/* OMEGAMSB */ -+#define R367_OFDM_OMEGAMSB 0xF057 -+#define F367_OFDM_OMEGA_MSB 0xF057007F -+ -+/* OMEGALSB */ -+#define R367_OFDM_OMEGALSB 0xF058 -+#define F367_OFDM_OMEGA_LSB 0xF05800FF -+ -+/* SCAT_NB */ -+#define R367_OFDM_SCAT_NB 0xF059 -+#define F367_OFDM_CHC_TEST 0xF05900F8 -+#define F367_OFDM_SCAT_NUMB 0xF0590003 -+ -+/* CHC_DUMMY */ -+#define R367_OFDM_CHC_DUMMY 0xF05A -+#define F367_OFDM_CHC_DUM 0xF05A00FF -+ -+/* INC_CTL */ -+#define R367_OFDM_INC_CTL 0xF05B -+#define F367_OFDM_INC_BYPASS 0xF05B0080 -+#define F367_OFDM_INC_NDEPTH 0xF05B000C -+#define F367_OFDM_INC_MADEPTH 0xF05B0003 -+ -+/* INCTHRES_COR1 */ -+#define R367_OFDM_INCTHRES_COR1 0xF05C -+#define F367_OFDM_INC_THRES_COR1 0xF05C00FF -+ -+/* INCTHRES_COR2 */ -+#define R367_OFDM_INCTHRES_COR2 0xF05D -+#define F367_OFDM_INC_THRES_COR2 0xF05D00FF -+ -+/* INCTHRES_DET1 */ -+#define R367_OFDM_INCTHRES_DET1 0xF05E -+#define F367_OFDM_INC_THRES_DET1 0xF05E003F -+ -+/* INCTHRES_DET2 */ -+#define R367_OFDM_INCTHRES_DET2 0xF05F -+#define F367_OFDM_INC_THRES_DET2 0xF05F003F -+ -+/* IIR_CELLNB */ -+#define R367_OFDM_IIR_CELLNB 0xF060 -+#define F367_OFDM_NRST_IIR 0xF0600080 -+#define F367_OFDM_IIR_CELL_NB 0xF0600007 -+ -+/* IIRCX_COEFF1_MSB */ -+#define R367_OFDM_IIRCX_COEFF1_MSB 0xF061 -+#define F367_OFDM_IIR_CX_COEFF1_MSB 0xF06100FF -+ -+/* IIRCX_COEFF1_LSB */ -+#define R367_OFDM_IIRCX_COEFF1_LSB 0xF062 -+#define F367_OFDM_IIR_CX_COEFF1_LSB 0xF06200FF -+ -+/* IIRCX_COEFF2_MSB */ -+#define R367_OFDM_IIRCX_COEFF2_MSB 0xF063 -+#define F367_OFDM_IIR_CX_COEFF2_MSB 0xF06300FF -+ -+/* IIRCX_COEFF2_LSB */ -+#define R367_OFDM_IIRCX_COEFF2_LSB 0xF064 -+#define F367_OFDM_IIR_CX_COEFF2_LSB 0xF06400FF -+ -+/* IIRCX_COEFF3_MSB */ -+#define R367_OFDM_IIRCX_COEFF3_MSB 0xF065 -+#define F367_OFDM_IIR_CX_COEFF3_MSB 0xF06500FF -+ -+/* IIRCX_COEFF3_LSB */ -+#define R367_OFDM_IIRCX_COEFF3_LSB 0xF066 -+#define F367_OFDM_IIR_CX_COEFF3_LSB 0xF06600FF -+ -+/* IIRCX_COEFF4_MSB */ -+#define R367_OFDM_IIRCX_COEFF4_MSB 0xF067 -+#define F367_OFDM_IIR_CX_COEFF4_MSB 0xF06700FF -+ -+/* IIRCX_COEFF4_LSB */ -+#define R367_OFDM_IIRCX_COEFF4_LSB 0xF068 -+#define F367_OFDM_IIR_CX_COEFF4_LSB 0xF06800FF -+ -+/* IIRCX_COEFF5_MSB */ -+#define R367_OFDM_IIRCX_COEFF5_MSB 0xF069 -+#define F367_OFDM_IIR_CX_COEFF5_MSB 0xF06900FF -+ -+/* IIRCX_COEFF5_LSB */ -+#define R367_OFDM_IIRCX_COEFF5_LSB 0xF06A -+#define F367_OFDM_IIR_CX_COEFF5_LSB 0xF06A00FF -+ -+/* FEPATH_CFG */ -+#define R367_OFDM_FEPATH_CFG 0xF06B -+#define F367_OFDM_DEMUX_SWAP 0xF06B0004 -+#define F367_OFDM_DIGAGC_SWAP 0xF06B0002 -+#define F367_OFDM_LONGPATH_IF 0xF06B0001 -+ -+/* PMC1_FUNC */ -+#define R367_OFDM_PMC1_FUNC 0xF06C -+#define F367_OFDM_SOFT_RSTN 0xF06C0080 -+#define F367_OFDM_PMC1_AVERAGE_TIME 0xF06C0078 -+#define F367_OFDM_PMC1_WAIT_TIME 0xF06C0006 -+#define F367_OFDM_PMC1_2N_SEL 0xF06C0001 -+ -+/* PMC1_FOR */ -+#define R367_OFDM_PMC1_FOR 0xF06D -+#define F367_OFDM_PMC1_FORCE 0xF06D0080 -+#define F367_OFDM_PMC1_FORCE_VALUE 0xF06D007C -+ -+/* PMC2_FUNC */ -+#define R367_OFDM_PMC2_FUNC 0xF06E -+#define F367_OFDM_PMC2_SOFT_STN 0xF06E0080 -+#define F367_OFDM_PMC2_ACCU_TIME 0xF06E0070 -+#define F367_OFDM_PMC2_CMDP_MN 0xF06E0008 -+#define F367_OFDM_PMC2_SWAP 0xF06E0004 -+ -+/* STATUS_ERR_DA */ -+#define R367_OFDM_STATUS_ERR_DA 0xF06F -+#define F367_OFDM_COM_USEGAINTRK 0xF06F0080 -+#define F367_OFDM_COM_AGCLOCK 0xF06F0040 -+#define F367_OFDM_AUT_AGCLOCK 0xF06F0020 -+#define F367_OFDM_MIN_ERR_X_LSB 0xF06F000F -+ -+/* DIG_AGC_R */ -+#define R367_OFDM_DIG_AGC_R 0xF070 -+#define F367_OFDM_COM_SOFT_RSTN 0xF0700080 -+#define F367_OFDM_COM_AGC_ON 0xF0700040 -+#define F367_OFDM_COM_EARLY 0xF0700020 -+#define F367_OFDM_AUT_SOFT_RESETN 0xF0700010 -+#define F367_OFDM_AUT_AGC_ON 0xF0700008 -+#define F367_OFDM_AUT_EARLY 0xF0700004 -+#define F367_OFDM_AUT_ROT_EN 0xF0700002 -+#define F367_OFDM_LOCK_SOFT_RESETN 0xF0700001 -+ -+/* COMAGC_TARMSB */ -+#define R367_OFDM_COMAGC_TARMSB 0xF071 -+#define F367_OFDM_COM_AGC_TARGET_MSB 0xF07100FF -+ -+/* COM_AGC_TAR_ENMODE */ -+#define R367_OFDM_COM_AGC_TAR_ENMODE 0xF072 -+#define F367_OFDM_COM_AGC_TARGET_LSB 0xF07200F0 -+#define F367_OFDM_COM_ENMODE 0xF072000F -+ -+/* COM_AGC_CFG */ -+#define R367_OFDM_COM_AGC_CFG 0xF073 -+#define F367_OFDM_COM_N 0xF07300F8 -+#define F367_OFDM_COM_STABMODE 0xF0730006 -+#define F367_OFDM_ERR_SEL 0xF0730001 -+ -+/* COM_AGC_GAIN1 */ -+#define R367_OFDM_COM_AGC_GAIN1 0xF074 -+#define F367_OFDM_COM_GAIN1ACK 0xF07400F0 -+#define F367_OFDM_COM_GAIN1TRK 0xF074000F -+ -+/* AUT_AGC_TARGETMSB */ -+#define R367_OFDM_AUT_AGC_TARGETMSB 0xF075 -+#define F367_OFDM_AUT_AGC_TARGET_MSB 0xF07500FF -+ -+/* LOCK_DET_MSB */ -+#define R367_OFDM_LOCK_DET_MSB 0xF076 -+#define F367_OFDM_LOCK_DETECT_MSB 0xF07600FF -+ -+/* AGCTAR_LOCK_LSBS */ -+#define R367_OFDM_AGCTAR_LOCK_LSBS 0xF077 -+#define F367_OFDM_AUT_AGC_TARGET_LSB 0xF07700F0 -+#define F367_OFDM_LOCK_DETECT_LSB 0xF077000F -+ -+/* AUT_GAIN_EN */ -+#define R367_OFDM_AUT_GAIN_EN 0xF078 -+#define F367_OFDM_AUT_ENMODE 0xF07800F0 -+#define F367_OFDM_AUT_GAIN2 0xF078000F -+ -+/* AUT_CFG */ -+#define R367_OFDM_AUT_CFG 0xF079 -+#define F367_OFDM_AUT_N 0xF07900F8 -+#define F367_OFDM_INT_CHOICE 0xF0790006 -+#define F367_OFDM_INT_LOAD 0xF0790001 -+ -+/* LOCKN */ -+#define R367_OFDM_LOCKN 0xF07A -+#define F367_OFDM_LOCK_N 0xF07A00F8 -+#define F367_OFDM_SEL_IQNTAR 0xF07A0004 -+#define F367_OFDM_LOCK_DETECT_CHOICE 0xF07A0003 -+ -+/* INT_X_3 */ -+#define R367_OFDM_INT_X_3 0xF07B -+#define F367_OFDM_INT_X3 0xF07B00FF -+ -+/* INT_X_2 */ -+#define R367_OFDM_INT_X_2 0xF07C -+#define F367_OFDM_INT_X2 0xF07C00FF -+ -+/* INT_X_1 */ -+#define R367_OFDM_INT_X_1 0xF07D -+#define F367_OFDM_INT_X1 0xF07D00FF -+ -+/* INT_X_0 */ -+#define R367_OFDM_INT_X_0 0xF07E -+#define F367_OFDM_INT_X0 0xF07E00FF -+ -+/* MIN_ERRX_MSB */ -+#define R367_OFDM_MIN_ERRX_MSB 0xF07F -+#define F367_OFDM_MIN_ERR_X_MSB 0xF07F00FF -+ -+/* COR_CTL */ -+#define R367_OFDM_COR_CTL 0xF080 -+#define F367_OFDM_CORE_ACTIVE 0xF0800020 -+#define F367_OFDM_HOLD 0xF0800010 -+#define F367_OFDM_CORE_STATE_CTL 0xF080000F -+ -+/* COR_STAT */ -+#define R367_OFDM_COR_STAT 0xF081 -+#define F367_OFDM_SCATT_LOCKED 0xF0810080 -+#define F367_OFDM_TPS_LOCKED 0xF0810040 -+#define F367_OFDM_SYR_LOCKED_COR 0xF0810020 -+#define F367_OFDM_AGC_LOCKED_STAT 0xF0810010 -+#define F367_OFDM_CORE_STATE_STAT 0xF081000F -+ -+/* COR_INTEN */ -+#define R367_OFDM_COR_INTEN 0xF082 -+#define F367_OFDM_INTEN 0xF0820080 -+#define F367_OFDM_INTEN_SYR 0xF0820020 -+#define F367_OFDM_INTEN_FFT 0xF0820010 -+#define F367_OFDM_INTEN_AGC 0xF0820008 -+#define F367_OFDM_INTEN_TPS1 0xF0820004 -+#define F367_OFDM_INTEN_TPS2 0xF0820002 -+#define F367_OFDM_INTEN_TPS3 0xF0820001 -+ -+/* COR_INTSTAT */ -+#define R367_OFDM_COR_INTSTAT 0xF083 -+#define F367_OFDM_INTSTAT_SYR 0xF0830020 -+#define F367_OFDM_INTSTAT_FFT 0xF0830010 -+#define F367_OFDM_INTSAT_AGC 0xF0830008 -+#define F367_OFDM_INTSTAT_TPS1 0xF0830004 -+#define F367_OFDM_INTSTAT_TPS2 0xF0830002 -+#define F367_OFDM_INTSTAT_TPS3 0xF0830001 -+ -+/* COR_MODEGUARD */ -+#define R367_OFDM_COR_MODEGUARD 0xF084 -+#define F367_OFDM_FORCE 0xF0840010 -+#define F367_OFDM_MODE 0xF084000C -+#define F367_OFDM_GUARD 0xF0840003 -+ -+/* AGC_CTL */ -+#define R367_OFDM_AGC_CTL 0xF085 -+#define F367_OFDM_AGC_TIMING_FACTOR 0xF08500E0 -+#define F367_OFDM_AGC_LAST 0xF0850010 -+#define F367_OFDM_AGC_GAIN 0xF085000C -+#define F367_OFDM_AGC_NEG 0xF0850002 -+#define F367_OFDM_AGC_SET 0xF0850001 -+ -+/* AGC_MANUAL1 */ -+#define R367_OFDM_AGC_MANUAL1 0xF086 -+#define F367_OFDM_AGC_VAL_LO 0xF08600FF -+ -+/* AGC_MANUAL2 */ -+#define R367_OFDM_AGC_MANUAL2 0xF087 -+#define F367_OFDM_AGC_VAL_HI 0xF087000F -+ -+/* AGC_TARG */ -+#define R367_OFDM_AGC_TARG 0xF088 -+#define F367_OFDM_AGC_TARGET 0xF08800FF -+ -+/* AGC_GAIN1 */ -+#define R367_OFDM_AGC_GAIN1 0xF089 -+#define F367_OFDM_AGC_GAIN_LO 0xF08900FF -+ -+/* AGC_GAIN2 */ -+#define R367_OFDM_AGC_GAIN2 0xF08A -+#define F367_OFDM_AGC_LOCKED_GAIN2 0xF08A0010 -+#define F367_OFDM_AGC_GAIN_HI 0xF08A000F -+ -+/* RESERVED_1 */ -+#define R367_OFDM_RESERVED_1 0xF08B -+#define F367_OFDM_RESERVED1 0xF08B00FF -+ -+/* RESERVED_2 */ -+#define R367_OFDM_RESERVED_2 0xF08C -+#define F367_OFDM_RESERVED2 0xF08C00FF -+ -+/* RESERVED_3 */ -+#define R367_OFDM_RESERVED_3 0xF08D -+#define F367_OFDM_RESERVED3 0xF08D00FF -+ -+/* CAS_CTL */ -+#define R367_OFDM_CAS_CTL 0xF08E -+#define F367_OFDM_CCS_ENABLE 0xF08E0080 -+#define F367_OFDM_ACS_DISABLE 0xF08E0040 -+#define F367_OFDM_DAGC_DIS 0xF08E0020 -+#define F367_OFDM_DAGC_GAIN 0xF08E0018 -+#define F367_OFDM_CCSMU 0xF08E0007 -+ -+/* CAS_FREQ */ -+#define R367_OFDM_CAS_FREQ 0xF08F -+#define F367_OFDM_CCS_FREQ 0xF08F00FF -+ -+/* CAS_DAGCGAIN */ -+#define R367_OFDM_CAS_DAGCGAIN 0xF090 -+#define F367_OFDM_CAS_DAGC_GAIN 0xF09000FF -+ -+/* SYR_CTL */ -+#define R367_OFDM_SYR_CTL 0xF091 -+#define F367_OFDM_SICTH_ENABLE 0xF0910080 -+#define F367_OFDM_LONG_ECHO 0xF0910078 -+#define F367_OFDM_AUTO_LE_EN 0xF0910004 -+#define F367_OFDM_SYR_BYPASS 0xF0910002 -+#define F367_OFDM_SYR_TR_DIS 0xF0910001 -+ -+/* SYR_STAT */ -+#define R367_OFDM_SYR_STAT 0xF092 -+#define F367_OFDM_SYR_LOCKED_STAT 0xF0920010 -+#define F367_OFDM_SYR_MODE 0xF092000C -+#define F367_OFDM_SYR_GUARD 0xF0920003 -+ -+/* SYR_NCO1 */ -+#define R367_OFDM_SYR_NCO1 0xF093 -+#define F367_OFDM_SYR_NCO_LO 0xF09300FF -+ -+/* SYR_NCO2 */ -+#define R367_OFDM_SYR_NCO2 0xF094 -+#define F367_OFDM_SYR_NCO_HI 0xF094003F -+ -+/* SYR_OFFSET1 */ -+#define R367_OFDM_SYR_OFFSET1 0xF095 -+#define F367_OFDM_SYR_OFFSET_LO 0xF09500FF -+ -+/* SYR_OFFSET2 */ -+#define R367_OFDM_SYR_OFFSET2 0xF096 -+#define F367_OFDM_SYR_OFFSET_HI 0xF096003F -+ -+/* FFT_CTL */ -+#define R367_OFDM_FFT_CTL 0xF097 -+#define F367_OFDM_SHIFT_FFT_TRIG 0xF0970018 -+#define F367_OFDM_FFT_TRIGGER 0xF0970004 -+#define F367_OFDM_FFT_MANUAL 0xF0970002 -+#define F367_OFDM_IFFT_MODE 0xF0970001 -+ -+/* SCR_CTL */ -+#define R367_OFDM_SCR_CTL 0xF098 -+#define F367_OFDM_SYRADJDECAY 0xF0980070 -+#define F367_OFDM_SCR_CPEDIS 0xF0980002 -+#define F367_OFDM_SCR_DIS 0xF0980001 -+ -+/* PPM_CTL1 */ -+#define R367_OFDM_PPM_CTL1 0xF099 -+#define F367_OFDM_PPM_MAXFREQ 0xF0990030 -+#define F367_OFDM_PPM_MAXTIM 0xF0990008 -+#define F367_OFDM_PPM_INVSEL 0xF0990004 -+#define F367_OFDM_PPM_SCATDIS 0xF0990002 -+#define F367_OFDM_PPM_BYP 0xF0990001 -+ -+/* TRL_CTL */ -+#define R367_OFDM_TRL_CTL 0xF09A -+#define F367_OFDM_TRL_NOMRATE_LSB 0xF09A0080 -+#define F367_OFDM_TRL_GAIN_FACTOR 0xF09A0078 -+#define F367_OFDM_TRL_LOOPGAIN 0xF09A0007 -+ -+/* TRL_NOMRATE1 */ -+#define R367_OFDM_TRL_NOMRATE1 0xF09B -+#define F367_OFDM_TRL_NOMRATE_LO 0xF09B00FF -+ -+/* TRL_NOMRATE2 */ -+#define R367_OFDM_TRL_NOMRATE2 0xF09C -+#define F367_OFDM_TRL_NOMRATE_HI 0xF09C00FF -+ -+/* TRL_TIME1 */ -+#define R367_OFDM_TRL_TIME1 0xF09D -+#define F367_OFDM_TRL_TOFFSET_LO 0xF09D00FF -+ -+/* TRL_TIME2 */ -+#define R367_OFDM_TRL_TIME2 0xF09E -+#define F367_OFDM_TRL_TOFFSET_HI 0xF09E00FF -+ -+/* CRL_CTL */ -+#define R367_OFDM_CRL_CTL 0xF09F -+#define F367_OFDM_CRL_DIS 0xF09F0080 -+#define F367_OFDM_CRL_GAIN_FACTOR 0xF09F0078 -+#define F367_OFDM_CRL_LOOPGAIN 0xF09F0007 -+ -+/* CRL_FREQ1 */ -+#define R367_OFDM_CRL_FREQ1 0xF0A0 -+#define F367_OFDM_CRL_FOFFSET_LO 0xF0A000FF -+ -+/* CRL_FREQ2 */ -+#define R367_OFDM_CRL_FREQ2 0xF0A1 -+#define F367_OFDM_CRL_FOFFSET_HI 0xF0A100FF -+ -+/* CRL_FREQ3 */ -+#define R367_OFDM_CRL_FREQ3 0xF0A2 -+#define F367_OFDM_CRL_FOFFSET_VHI 0xF0A200FF -+ -+/* TPS_SFRAME_CTL */ -+#define R367_OFDM_TPS_SFRAME_CTL 0xF0A3 -+#define F367_OFDM_TPS_SFRAME_SYNC 0xF0A30001 -+ -+/* CHC_SNR */ -+#define R367_OFDM_CHC_SNR 0xF0A4 -+#define F367_OFDM_CHCSNR 0xF0A400FF -+ -+/* BDI_CTL */ -+#define R367_OFDM_BDI_CTL 0xF0A5 -+#define F367_OFDM_BDI_LPSEL 0xF0A50002 -+#define F367_OFDM_BDI_SERIAL 0xF0A50001 -+ -+/* DMP_CTL */ -+#define R367_OFDM_DMP_CTL 0xF0A6 -+#define F367_OFDM_DMP_SCALING_FACTOR 0xF0A6001E -+#define F367_OFDM_DMP_SDDIS 0xF0A60001 -+ -+/* TPS_RCVD1 */ -+#define R367_OFDM_TPS_RCVD1 0xF0A7 -+#define F367_OFDM_TPS_CHANGE 0xF0A70040 -+#define F367_OFDM_BCH_OK 0xF0A70020 -+#define F367_OFDM_TPS_SYNC 0xF0A70010 -+#define F367_OFDM_TPS_FRAME 0xF0A70003 -+ -+/* TPS_RCVD2 */ -+#define R367_OFDM_TPS_RCVD2 0xF0A8 -+#define F367_OFDM_TPS_HIERMODE 0xF0A80070 -+#define F367_OFDM_TPS_CONST 0xF0A80003 -+ -+/* TPS_RCVD3 */ -+#define R367_OFDM_TPS_RCVD3 0xF0A9 -+#define F367_OFDM_TPS_LPCODE 0xF0A90070 -+#define F367_OFDM_TPS_HPCODE 0xF0A90007 -+ -+/* TPS_RCVD4 */ -+#define R367_OFDM_TPS_RCVD4 0xF0AA -+#define F367_OFDM_TPS_GUARD 0xF0AA0030 -+#define F367_OFDM_TPS_MODE 0xF0AA0003 -+ -+/* TPS_ID_CELL1 */ -+#define R367_OFDM_TPS_ID_CELL1 0xF0AB -+#define F367_OFDM_TPS_ID_CELL_LO 0xF0AB00FF -+ -+/* TPS_ID_CELL2 */ -+#define R367_OFDM_TPS_ID_CELL2 0xF0AC -+#define F367_OFDM_TPS_ID_CELL_HI 0xF0AC00FF -+ -+/* TPS_RCVD5_SET1 */ -+#define R367_OFDM_TPS_RCVD5_SET1 0xF0AD -+#define F367_OFDM_TPS_NA 0xF0AD00FC -+#define F367_OFDM_TPS_SETFRAME 0xF0AD0003 -+ -+/* TPS_SET2 */ -+#define R367_OFDM_TPS_SET2 0xF0AE -+#define F367_OFDM_TPS_SETHIERMODE 0xF0AE0070 -+#define F367_OFDM_TPS_SETCONST 0xF0AE0003 -+ -+/* TPS_SET3 */ -+#define R367_OFDM_TPS_SET3 0xF0AF -+#define F367_OFDM_TPS_SETLPCODE 0xF0AF0070 -+#define F367_OFDM_TPS_SETHPCODE 0xF0AF0007 -+ -+/* TPS_CTL */ -+#define R367_OFDM_TPS_CTL 0xF0B0 -+#define F367_OFDM_TPS_IMM 0xF0B00004 -+#define F367_OFDM_TPS_BCHDIS 0xF0B00002 -+#define F367_OFDM_TPS_UPDDIS 0xF0B00001 -+ -+/* CTL_FFTOSNUM */ -+#define R367_OFDM_CTL_FFTOSNUM 0xF0B1 -+#define F367_OFDM_SYMBOL_NUMBER 0xF0B1007F -+ -+/* TESTSELECT */ -+#define R367_OFDM_TESTSELECT 0xF0B2 -+#define F367_OFDM_TEST_SELECT 0xF0B2001F -+ -+/* MSC_REV */ -+#define R367_OFDM_MSC_REV 0xF0B3 -+#define F367_OFDM_REV_NUMBER 0xF0B300FF -+ -+/* PIR_CTL */ -+#define R367_OFDM_PIR_CTL 0xF0B4 -+#define F367_OFDM_FREEZE 0xF0B40001 -+ -+/* SNR_CARRIER1 */ -+#define R367_OFDM_SNR_CARRIER1 0xF0B5 -+#define F367_OFDM_SNR_CARRIER_LO 0xF0B500FF -+ -+/* SNR_CARRIER2 */ -+#define R367_OFDM_SNR_CARRIER2 0xF0B6 -+#define F367_OFDM_MEAN 0xF0B600C0 -+#define F367_OFDM_SNR_CARRIER_HI 0xF0B6001F -+ -+/* PPM_CPAMP */ -+#define R367_OFDM_PPM_CPAMP 0xF0B7 -+#define F367_OFDM_PPM_CPC 0xF0B700FF -+ -+/* TSM_AP0 */ -+#define R367_OFDM_TSM_AP0 0xF0B8 -+#define F367_OFDM_ADDRESS_BYTE_0 0xF0B800FF -+ -+/* TSM_AP1 */ -+#define R367_OFDM_TSM_AP1 0xF0B9 -+#define F367_OFDM_ADDRESS_BYTE_1 0xF0B900FF -+ -+/* TSM_AP2 */ -+#define R367_OFDM_TSM_AP2 0xF0BA -+#define F367_OFDM_DATA_BYTE_0 0xF0BA00FF -+ -+/* TSM_AP3 */ -+#define R367_OFDM_TSM_AP3 0xF0BB -+#define F367_OFDM_DATA_BYTE_1 0xF0BB00FF -+ -+/* TSM_AP4 */ -+#define R367_OFDM_TSM_AP4 0xF0BC -+#define F367_OFDM_DATA_BYTE_2 0xF0BC00FF -+ -+/* TSM_AP5 */ -+#define R367_OFDM_TSM_AP5 0xF0BD -+#define F367_OFDM_DATA_BYTE_3 0xF0BD00FF -+ -+/* TSM_AP6 */ -+#define R367_OFDM_TSM_AP6 0xF0BE -+#define F367_OFDM_TSM_AP_6 0xF0BE00FF -+ -+/* TSM_AP7 */ -+#define R367_OFDM_TSM_AP7 0xF0BF -+#define F367_OFDM_MEM_SELECT_BYTE 0xF0BF00FF -+ -+/* TSTRES */ -+#define R367_TSTRES 0xF0C0 -+#define F367_FRES_DISPLAY 0xF0C00080 -+#define F367_FRES_FIFO_AD 0xF0C00020 -+#define F367_FRESRS 0xF0C00010 -+#define F367_FRESACS 0xF0C00008 -+#define F367_FRESFEC 0xF0C00004 -+#define F367_FRES_PRIF 0xF0C00002 -+#define F367_FRESCORE 0xF0C00001 -+ -+/* ANACTRL */ -+#define R367_ANACTRL 0xF0C1 -+#define F367_BYPASS_XTAL 0xF0C10040 -+#define F367_BYPASS_PLLXN 0xF0C1000C -+#define F367_DIS_PAD_OSC 0xF0C10002 -+#define F367_STDBY_PLLXN 0xF0C10001 -+ -+/* TSTBUS */ -+#define R367_TSTBUS 0xF0C2 -+#define F367_TS_BYTE_CLK_INV 0xF0C20080 -+#define F367_CFG_IP 0xF0C20070 -+#define F367_CFG_TST 0xF0C2000F -+ -+/* TSTRATE */ -+#define R367_TSTRATE 0xF0C6 -+#define F367_FORCEPHA 0xF0C60080 -+#define F367_FNEWPHA 0xF0C60010 -+#define F367_FROT90 0xF0C60008 -+#define F367_FR 0xF0C60007 -+ -+/* CONSTMODE */ -+#define R367_OFDM_CONSTMODE 0xF0CB -+#define F367_OFDM_TST_PRIF 0xF0CB00E0 -+#define F367_OFDM_CAR_TYPE 0xF0CB0018 -+#define F367_OFDM_CONST_MODE 0xF0CB0003 -+ -+/* CONSTCARR1 */ -+#define R367_OFDM_CONSTCARR1 0xF0CC -+#define F367_OFDM_CONST_CARR_LO 0xF0CC00FF -+ -+/* CONSTCARR2 */ -+#define R367_OFDM_CONSTCARR2 0xF0CD -+#define F367_OFDM_CONST_CARR_HI 0xF0CD001F -+ -+/* ICONSTEL */ -+#define R367_OFDM_ICONSTEL 0xF0CE -+#define F367_OFDM_PICONSTEL 0xF0CE00FF -+ -+/* QCONSTEL */ -+#define R367_OFDM_QCONSTEL 0xF0CF -+#define F367_OFDM_PQCONSTEL 0xF0CF00FF -+ -+/* TSTBISTRES0 */ -+#define R367_OFDM_TSTBISTRES0 0xF0D0 -+#define F367_OFDM_BEND_PPM 0xF0D00080 -+#define F367_OFDM_BBAD_PPM 0xF0D00040 -+#define F367_OFDM_BEND_FFTW 0xF0D00020 -+#define F367_OFDM_BBAD_FFTW 0xF0D00010 -+#define F367_OFDM_BEND_FFT_BUF 0xF0D00008 -+#define F367_OFDM_BBAD_FFT_BUF 0xF0D00004 -+#define F367_OFDM_BEND_SYR 0xF0D00002 -+#define F367_OFDM_BBAD_SYR 0xF0D00001 -+ -+/* TSTBISTRES1 */ -+#define R367_OFDM_TSTBISTRES1 0xF0D1 -+#define F367_OFDM_BEND_CHC_CP 0xF0D10080 -+#define F367_OFDM_BBAD_CHC_CP 0xF0D10040 -+#define F367_OFDM_BEND_CHCI 0xF0D10020 -+#define F367_OFDM_BBAD_CHCI 0xF0D10010 -+#define F367_OFDM_BEND_BDI 0xF0D10008 -+#define F367_OFDM_BBAD_BDI 0xF0D10004 -+#define F367_OFDM_BEND_SDI 0xF0D10002 -+#define F367_OFDM_BBAD_SDI 0xF0D10001 -+ -+/* TSTBISTRES2 */ -+#define R367_OFDM_TSTBISTRES2 0xF0D2 -+#define F367_OFDM_BEND_CHC_INC 0xF0D20080 -+#define F367_OFDM_BBAD_CHC_INC 0xF0D20040 -+#define F367_OFDM_BEND_CHC_SPP 0xF0D20020 -+#define F367_OFDM_BBAD_CHC_SPP 0xF0D20010 -+#define F367_OFDM_BEND_CHC_CPP 0xF0D20008 -+#define F367_OFDM_BBAD_CHC_CPP 0xF0D20004 -+#define F367_OFDM_BEND_CHC_SP 0xF0D20002 -+#define F367_OFDM_BBAD_CHC_SP 0xF0D20001 -+ -+/* TSTBISTRES3 */ -+#define R367_OFDM_TSTBISTRES3 0xF0D3 -+#define F367_OFDM_BEND_QAM 0xF0D30080 -+#define F367_OFDM_BBAD_QAM 0xF0D30040 -+#define F367_OFDM_BEND_SFEC_VIT 0xF0D30020 -+#define F367_OFDM_BBAD_SFEC_VIT 0xF0D30010 -+#define F367_OFDM_BEND_SFEC_DLINE 0xF0D30008 -+#define F367_OFDM_BBAD_SFEC_DLINE 0xF0D30004 -+#define F367_OFDM_BEND_SFEC_HW 0xF0D30002 -+#define F367_OFDM_BBAD_SFEC_HW 0xF0D30001 -+ -+/* RF_AGC1 */ -+#define R367_RF_AGC1 0xF0D4 -+#define F367_RF_AGC1_LEVEL_HI 0xF0D400FF -+ -+/* RF_AGC2 */ -+#define R367_RF_AGC2 0xF0D5 -+#define F367_REF_ADGP 0xF0D50080 -+#define F367_STDBY_ADCGP 0xF0D50020 -+#define F367_CHANNEL_SEL 0xF0D5001C -+#define F367_RF_AGC1_LEVEL_LO 0xF0D50003 -+ -+/* ANADIGCTRL */ -+#define R367_ANADIGCTRL 0xF0D7 -+#define F367_SEL_CLKDEM 0xF0D70020 -+#define F367_EN_BUFFER_Q 0xF0D70010 -+#define F367_EN_BUFFER_I 0xF0D70008 -+#define F367_ADC_RIS_EGDE 0xF0D70004 -+#define F367_SGN_ADC 0xF0D70002 -+#define F367_SEL_AD12_SYNC 0xF0D70001 -+ -+/* PLLMDIV */ -+#define R367_PLLMDIV 0xF0D8 -+#define F367_PLL_MDIV 0xF0D800FF -+ -+/* PLLNDIV */ -+#define R367_PLLNDIV 0xF0D9 -+#define F367_PLL_NDIV 0xF0D900FF -+ -+/* PLLSETUP */ -+#define R367_PLLSETUP 0xF0DA -+#define F367_PLL_PDIV 0xF0DA0070 -+#define F367_PLL_KDIV 0xF0DA000F -+ -+/* DUAL_AD12 */ -+#define R367_DUAL_AD12 0xF0DB -+#define F367_FS20M 0xF0DB0020 -+#define F367_FS50M 0xF0DB0010 -+#define F367_INMODE0 0xF0DB0008 -+#define F367_POFFQ 0xF0DB0004 -+#define F367_POFFI 0xF0DB0002 -+#define F367_INMODE1 0xF0DB0001 -+ -+/* TSTBIST */ -+#define R367_TSTBIST 0xF0DC -+#define F367_TST_BYP_CLK 0xF0DC0080 -+#define F367_TST_GCLKENA_STD 0xF0DC0040 -+#define F367_TST_GCLKENA 0xF0DC0020 -+#define F367_TST_MEMBIST 0xF0DC001F -+ -+/* PAD_COMP_CTRL */ -+#define R367_PAD_COMP_CTRL 0xF0DD -+#define F367_COMPTQ 0xF0DD0010 -+#define F367_COMPEN 0xF0DD0008 -+#define F367_FREEZE2 0xF0DD0004 -+#define F367_SLEEP_INHBT 0xF0DD0002 -+#define F367_CHIP_SLEEP 0xF0DD0001 -+ -+/* PAD_COMP_WR */ -+#define R367_PAD_COMP_WR 0xF0DE -+#define F367_WR_ASRC 0xF0DE007F -+ -+/* PAD_COMP_RD */ -+#define R367_PAD_COMP_RD 0xF0DF -+#define F367_COMPOK 0xF0DF0080 -+#define F367_RD_ASRC 0xF0DF007F -+ -+/* SYR_TARGET_FFTADJT_MSB */ -+#define R367_OFDM_SYR_TARGET_FFTADJT_MSB 0xF100 -+#define F367_OFDM_SYR_START 0xF1000080 -+#define F367_OFDM_SYR_TARGET_FFTADJ_HI 0xF100000F -+ -+/* SYR_TARGET_FFTADJT_LSB */ -+#define R367_OFDM_SYR_TARGET_FFTADJT_LSB 0xF101 -+#define F367_OFDM_SYR_TARGET_FFTADJ_LO 0xF10100FF -+ -+/* SYR_TARGET_CHCADJT_MSB */ -+#define R367_OFDM_SYR_TARGET_CHCADJT_MSB 0xF102 -+#define F367_OFDM_SYR_TARGET_CHCADJ_HI 0xF102000F -+ -+/* SYR_TARGET_CHCADJT_LSB */ -+#define R367_OFDM_SYR_TARGET_CHCADJT_LSB 0xF103 -+#define F367_OFDM_SYR_TARGET_CHCADJ_LO 0xF10300FF -+ -+/* SYR_FLAG */ -+#define R367_OFDM_SYR_FLAG 0xF104 -+#define F367_OFDM_TRIG_FLG1 0xF1040080 -+#define F367_OFDM_TRIG_FLG0 0xF1040040 -+#define F367_OFDM_FFT_FLG1 0xF1040008 -+#define F367_OFDM_FFT_FLG0 0xF1040004 -+#define F367_OFDM_CHC_FLG1 0xF1040002 -+#define F367_OFDM_CHC_FLG0 0xF1040001 -+ -+/* CRL_TARGET1 */ -+#define R367_OFDM_CRL_TARGET1 0xF105 -+#define F367_OFDM_CRL_START 0xF1050080 -+#define F367_OFDM_CRL_TARGET_VHI 0xF105000F -+ -+/* CRL_TARGET2 */ -+#define R367_OFDM_CRL_TARGET2 0xF106 -+#define F367_OFDM_CRL_TARGET_HI 0xF10600FF -+ -+/* CRL_TARGET3 */ -+#define R367_OFDM_CRL_TARGET3 0xF107 -+#define F367_OFDM_CRL_TARGET_LO 0xF10700FF -+ -+/* CRL_TARGET4 */ -+#define R367_OFDM_CRL_TARGET4 0xF108 -+#define F367_OFDM_CRL_TARGET_VLO 0xF10800FF -+ -+/* CRL_FLAG */ -+#define R367_OFDM_CRL_FLAG 0xF109 -+#define F367_OFDM_CRL_FLAG1 0xF1090002 -+#define F367_OFDM_CRL_FLAG0 0xF1090001 -+ -+/* TRL_TARGET1 */ -+#define R367_OFDM_TRL_TARGET1 0xF10A -+#define F367_OFDM_TRL_TARGET_HI 0xF10A00FF -+ -+/* TRL_TARGET2 */ -+#define R367_OFDM_TRL_TARGET2 0xF10B -+#define F367_OFDM_TRL_TARGET_LO 0xF10B00FF -+ -+/* TRL_CHC */ -+#define R367_OFDM_TRL_CHC 0xF10C -+#define F367_OFDM_TRL_START 0xF10C0080 -+#define F367_OFDM_CHC_START 0xF10C0040 -+#define F367_OFDM_TRL_FLAG1 0xF10C0002 -+#define F367_OFDM_TRL_FLAG0 0xF10C0001 -+ -+/* CHC_SNR_TARG */ -+#define R367_OFDM_CHC_SNR_TARG 0xF10D -+#define F367_OFDM_CHC_SNR_TARGET 0xF10D00FF -+ -+/* TOP_TRACK */ -+#define R367_OFDM_TOP_TRACK 0xF10E -+#define F367_OFDM_TOP_START 0xF10E0080 -+#define F367_OFDM_FIRST_FLAG 0xF10E0070 -+#define F367_OFDM_TOP_FLAG1 0xF10E0008 -+#define F367_OFDM_TOP_FLAG0 0xF10E0004 -+#define F367_OFDM_CHC_FLAG1 0xF10E0002 -+#define F367_OFDM_CHC_FLAG0 0xF10E0001 -+ -+/* TRACKER_FREE1 */ -+#define R367_OFDM_TRACKER_FREE1 0xF10F -+#define F367_OFDM_TRACKER_FREE_1 0xF10F00FF -+ -+/* ERROR_CRL1 */ -+#define R367_OFDM_ERROR_CRL1 0xF110 -+#define F367_OFDM_ERROR_CRL_VHI 0xF11000FF -+ -+/* ERROR_CRL2 */ -+#define R367_OFDM_ERROR_CRL2 0xF111 -+#define F367_OFDM_ERROR_CRL_HI 0xF11100FF -+ -+/* ERROR_CRL3 */ -+#define R367_OFDM_ERROR_CRL3 0xF112 -+#define F367_OFDM_ERROR_CRL_LOI 0xF11200FF -+ -+/* ERROR_CRL4 */ -+#define R367_OFDM_ERROR_CRL4 0xF113 -+#define F367_OFDM_ERROR_CRL_VLO 0xF11300FF -+ -+/* DEC_NCO1 */ -+#define R367_OFDM_DEC_NCO1 0xF114 -+#define F367_OFDM_DEC_NCO_VHI 0xF11400FF -+ -+/* DEC_NCO2 */ -+#define R367_OFDM_DEC_NCO2 0xF115 -+#define F367_OFDM_DEC_NCO_HI 0xF11500FF -+ -+/* DEC_NCO3 */ -+#define R367_OFDM_DEC_NCO3 0xF116 -+#define F367_OFDM_DEC_NCO_LO 0xF11600FF -+ -+/* SNR */ -+#define R367_OFDM_SNR 0xF117 -+#define F367_OFDM_SNRATIO 0xF11700FF -+ -+/* SYR_FFTADJ1 */ -+#define R367_OFDM_SYR_FFTADJ1 0xF118 -+#define F367_OFDM_SYR_FFTADJ_HI 0xF11800FF -+ -+/* SYR_FFTADJ2 */ -+#define R367_OFDM_SYR_FFTADJ2 0xF119 -+#define F367_OFDM_SYR_FFTADJ_LO 0xF11900FF -+ -+/* SYR_CHCADJ1 */ -+#define R367_OFDM_SYR_CHCADJ1 0xF11A -+#define F367_OFDM_SYR_CHCADJ_HI 0xF11A00FF -+ -+/* SYR_CHCADJ2 */ -+#define R367_OFDM_SYR_CHCADJ2 0xF11B -+#define F367_OFDM_SYR_CHCADJ_LO 0xF11B00FF -+ -+/* SYR_OFF */ -+#define R367_OFDM_SYR_OFF 0xF11C -+#define F367_OFDM_SYR_OFFSET 0xF11C00FF -+ -+/* PPM_OFFSET1 */ -+#define R367_OFDM_PPM_OFFSET1 0xF11D -+#define F367_OFDM_PPM_OFFSET_HI 0xF11D00FF -+ -+/* PPM_OFFSET2 */ -+#define R367_OFDM_PPM_OFFSET2 0xF11E -+#define F367_OFDM_PPM_OFFSET_LO 0xF11E00FF -+ -+/* TRACKER_FREE2 */ -+#define R367_OFDM_TRACKER_FREE2 0xF11F -+#define F367_OFDM_TRACKER_FREE_2 0xF11F00FF -+ -+/* DEBG_LT10 */ -+#define R367_OFDM_DEBG_LT10 0xF120 -+#define F367_OFDM_DEBUG_LT10 0xF12000FF -+ -+/* DEBG_LT11 */ -+#define R367_OFDM_DEBG_LT11 0xF121 -+#define F367_OFDM_DEBUG_LT11 0xF12100FF -+ -+/* DEBG_LT12 */ -+#define R367_OFDM_DEBG_LT12 0xF122 -+#define F367_OFDM_DEBUG_LT12 0xF12200FF -+ -+/* DEBG_LT13 */ -+#define R367_OFDM_DEBG_LT13 0xF123 -+#define F367_OFDM_DEBUG_LT13 0xF12300FF -+ -+/* DEBG_LT14 */ -+#define R367_OFDM_DEBG_LT14 0xF124 -+#define F367_OFDM_DEBUG_LT14 0xF12400FF -+ -+/* DEBG_LT15 */ -+#define R367_OFDM_DEBG_LT15 0xF125 -+#define F367_OFDM_DEBUG_LT15 0xF12500FF -+ -+/* DEBG_LT16 */ -+#define R367_OFDM_DEBG_LT16 0xF126 -+#define F367_OFDM_DEBUG_LT16 0xF12600FF -+ -+/* DEBG_LT17 */ -+#define R367_OFDM_DEBG_LT17 0xF127 -+#define F367_OFDM_DEBUG_LT17 0xF12700FF -+ -+/* DEBG_LT18 */ -+#define R367_OFDM_DEBG_LT18 0xF128 -+#define F367_OFDM_DEBUG_LT18 0xF12800FF -+ -+/* DEBG_LT19 */ -+#define R367_OFDM_DEBG_LT19 0xF129 -+#define F367_OFDM_DEBUG_LT19 0xF12900FF -+ -+/* DEBG_LT1A */ -+#define R367_OFDM_DEBG_LT1A 0xF12A -+#define F367_OFDM_DEBUG_LT1A 0xF12A00FF -+ -+/* DEBG_LT1B */ -+#define R367_OFDM_DEBG_LT1B 0xF12B -+#define F367_OFDM_DEBUG_LT1B 0xF12B00FF -+ -+/* DEBG_LT1C */ -+#define R367_OFDM_DEBG_LT1C 0xF12C -+#define F367_OFDM_DEBUG_LT1C 0xF12C00FF -+ -+/* DEBG_LT1D */ -+#define R367_OFDM_DEBG_LT1D 0xF12D -+#define F367_OFDM_DEBUG_LT1D 0xF12D00FF -+ -+/* DEBG_LT1E */ -+#define R367_OFDM_DEBG_LT1E 0xF12E -+#define F367_OFDM_DEBUG_LT1E 0xF12E00FF -+ -+/* DEBG_LT1F */ -+#define R367_OFDM_DEBG_LT1F 0xF12F -+#define F367_OFDM_DEBUG_LT1F 0xF12F00FF -+ -+/* RCCFGH */ -+#define R367_OFDM_RCCFGH 0xF200 -+#define F367_OFDM_TSRCFIFO_DVBCI 0xF2000080 -+#define F367_OFDM_TSRCFIFO_SERIAL 0xF2000040 -+#define F367_OFDM_TSRCFIFO_DISABLE 0xF2000020 -+#define F367_OFDM_TSFIFO_2TORC 0xF2000010 -+#define F367_OFDM_TSRCFIFO_HSGNLOUT 0xF2000008 -+#define F367_OFDM_TSRCFIFO_ERRMODE 0xF2000006 -+#define F367_OFDM_RCCFGH_0 0xF2000001 -+ -+/* RCCFGM */ -+#define R367_OFDM_RCCFGM 0xF201 -+#define F367_OFDM_TSRCFIFO_MANSPEED 0xF20100C0 -+#define F367_OFDM_TSRCFIFO_PERMDATA 0xF2010020 -+#define F367_OFDM_TSRCFIFO_NONEWSGNL 0xF2010010 -+#define F367_OFDM_RCBYTE_OVERSAMPLING 0xF201000E -+#define F367_OFDM_TSRCFIFO_INVDATA 0xF2010001 -+ -+/* RCCFGL */ -+#define R367_OFDM_RCCFGL 0xF202 -+#define F367_OFDM_TSRCFIFO_BCLKDEL1CK 0xF20200C0 -+#define F367_OFDM_RCCFGL_5 0xF2020020 -+#define F367_OFDM_TSRCFIFO_DUTY50 0xF2020010 -+#define F367_OFDM_TSRCFIFO_NSGNL2DATA 0xF2020008 -+#define F367_OFDM_TSRCFIFO_DISSERMUX 0xF2020004 -+#define F367_OFDM_RCCFGL_1 0xF2020002 -+#define F367_OFDM_TSRCFIFO_STOPCKDIS 0xF2020001 -+ -+/* RCINSDELH */ -+#define R367_OFDM_RCINSDELH 0xF203 -+#define F367_OFDM_TSRCDEL_SYNCBYTE 0xF2030080 -+#define F367_OFDM_TSRCDEL_XXHEADER 0xF2030040 -+#define F367_OFDM_TSRCDEL_BBHEADER 0xF2030020 -+#define F367_OFDM_TSRCDEL_DATAFIELD 0xF2030010 -+#define F367_OFDM_TSRCINSDEL_ISCR 0xF2030008 -+#define F367_OFDM_TSRCINSDEL_NPD 0xF2030004 -+#define F367_OFDM_TSRCINSDEL_RSPARITY 0xF2030002 -+#define F367_OFDM_TSRCINSDEL_CRC8 0xF2030001 -+ -+/* RCINSDELM */ -+#define R367_OFDM_RCINSDELM 0xF204 -+#define F367_OFDM_TSRCINS_BBPADDING 0xF2040080 -+#define F367_OFDM_TSRCINS_BCHFEC 0xF2040040 -+#define F367_OFDM_TSRCINS_LDPCFEC 0xF2040020 -+#define F367_OFDM_TSRCINS_EMODCOD 0xF2040010 -+#define F367_OFDM_TSRCINS_TOKEN 0xF2040008 -+#define F367_OFDM_TSRCINS_XXXERR 0xF2040004 -+#define F367_OFDM_TSRCINS_MATYPE 0xF2040002 -+#define F367_OFDM_TSRCINS_UPL 0xF2040001 -+ -+/* RCINSDELL */ -+#define R367_OFDM_RCINSDELL 0xF205 -+#define F367_OFDM_TSRCINS_DFL 0xF2050080 -+#define F367_OFDM_TSRCINS_SYNCD 0xF2050040 -+#define F367_OFDM_TSRCINS_BLOCLEN 0xF2050020 -+#define F367_OFDM_TSRCINS_SIGPCOUNT 0xF2050010 -+#define F367_OFDM_TSRCINS_FIFO 0xF2050008 -+#define F367_OFDM_TSRCINS_REALPACK 0xF2050004 -+#define F367_OFDM_TSRCINS_TSCONFIG 0xF2050002 -+#define F367_OFDM_TSRCINS_LATENCY 0xF2050001 -+ -+/* RCSTATUS */ -+#define R367_OFDM_RCSTATUS 0xF206 -+#define F367_OFDM_TSRCFIFO_LINEOK 0xF2060080 -+#define F367_OFDM_TSRCFIFO_ERROR 0xF2060040 -+#define F367_OFDM_TSRCFIFO_DATA7 0xF2060020 -+#define F367_OFDM_RCSTATUS_4 0xF2060010 -+#define F367_OFDM_TSRCFIFO_DEMODSEL 0xF2060008 -+#define F367_OFDM_TSRC1FIFOSPEED_STORE 0xF2060004 -+#define F367_OFDM_RCSTATUS_1 0xF2060002 -+#define F367_OFDM_TSRCSERIAL_IMPOSSIBLE 0xF2060001 -+ -+/* RCSPEED */ -+#define R367_OFDM_RCSPEED 0xF207 -+#define F367_OFDM_TSRCFIFO_OUTSPEED 0xF20700FF -+ -+/* RCDEBUGM */ -+#define R367_OFDM_RCDEBUGM 0xF208 -+#define F367_OFDM_SD_UNSYNC 0xF2080080 -+#define F367_OFDM_ULFLOCK_DETECTM 0xF2080040 -+#define F367_OFDM_SUL_SELECTOS 0xF2080020 -+#define F367_OFDM_DILUL_NOSCRBLE 0xF2080010 -+#define F367_OFDM_NUL_SCRB 0xF2080008 -+#define F367_OFDM_UL_SCRB 0xF2080004 -+#define F367_OFDM_SCRAULBAD 0xF2080002 -+#define F367_OFDM_SCRAUL_UNSYNC 0xF2080001 -+ -+/* RCDEBUGL */ -+#define R367_OFDM_RCDEBUGL 0xF209 -+#define F367_OFDM_RS_ERR 0xF2090080 -+#define F367_OFDM_LLFLOCK_DETECTM 0xF2090040 -+#define F367_OFDM_NOT_SUL_SELECTOS 0xF2090020 -+#define F367_OFDM_DILLL_NOSCRBLE 0xF2090010 -+#define F367_OFDM_NLL_SCRB 0xF2090008 -+#define F367_OFDM_LL_SCRB 0xF2090004 -+#define F367_OFDM_SCRALLBAD 0xF2090002 -+#define F367_OFDM_SCRALL_UNSYNC 0xF2090001 -+ -+/* RCOBSCFG */ -+#define R367_OFDM_RCOBSCFG 0xF20A -+#define F367_OFDM_TSRCFIFO_OBSCFG 0xF20A00FF -+ -+/* RCOBSM */ -+#define R367_OFDM_RCOBSM 0xF20B -+#define F367_OFDM_TSRCFIFO_OBSDATA_HI 0xF20B00FF -+ -+/* RCOBSL */ -+#define R367_OFDM_RCOBSL 0xF20C -+#define F367_OFDM_TSRCFIFO_OBSDATA_LO 0xF20C00FF -+ -+/* RCFECSPY */ -+#define R367_OFDM_RCFECSPY 0xF210 -+#define F367_OFDM_SPYRC_ENABLE 0xF2100080 -+#define F367_OFDM_RCNO_SYNCBYTE 0xF2100040 -+#define F367_OFDM_RCSERIAL_MODE 0xF2100020 -+#define F367_OFDM_RCUNUSUAL_PACKET 0xF2100010 -+#define F367_OFDM_BERRCMETER_DATAMODE 0xF210000C -+#define F367_OFDM_BERRCMETER_LMODE 0xF2100002 -+#define F367_OFDM_BERRCMETER_RESET 0xF2100001 -+ -+/* RCFSPYCFG */ -+#define R367_OFDM_RCFSPYCFG 0xF211 -+#define F367_OFDM_FECSPYRC_INPUT 0xF21100C0 -+#define F367_OFDM_RCRST_ON_ERROR 0xF2110020 -+#define F367_OFDM_RCONE_SHOT 0xF2110010 -+#define F367_OFDM_RCI2C_MODE 0xF211000C -+#define F367_OFDM_SPYRC_HSTERESIS 0xF2110003 -+ -+/* RCFSPYDATA */ -+#define R367_OFDM_RCFSPYDATA 0xF212 -+#define F367_OFDM_SPYRC_STUFFING 0xF2120080 -+#define F367_OFDM_RCNOERR_PKTJITTER 0xF2120040 -+#define F367_OFDM_SPYRC_CNULLPKT 0xF2120020 -+#define F367_OFDM_SPYRC_OUTDATA_MODE 0xF212001F -+ -+/* RCFSPYOUT */ -+#define R367_OFDM_RCFSPYOUT 0xF213 -+#define F367_OFDM_FSPYRC_DIRECT 0xF2130080 -+#define F367_OFDM_RCFSPYOUT_6 0xF2130040 -+#define F367_OFDM_SPYRC_OUTDATA_BUS 0xF2130038 -+#define F367_OFDM_RCSTUFF_MODE 0xF2130007 -+ -+/* RCFSTATUS */ -+#define R367_OFDM_RCFSTATUS 0xF214 -+#define F367_OFDM_SPYRC_ENDSIM 0xF2140080 -+#define F367_OFDM_RCVALID_SIM 0xF2140040 -+#define F367_OFDM_RCFOUND_SIGNAL 0xF2140020 -+#define F367_OFDM_RCDSS_SYNCBYTE 0xF2140010 -+#define F367_OFDM_RCRESULT_STATE 0xF214000F -+ -+/* RCFGOODPACK */ -+#define R367_OFDM_RCFGOODPACK 0xF215 -+#define F367_OFDM_RCGOOD_PACKET 0xF21500FF -+ -+/* RCFPACKCNT */ -+#define R367_OFDM_RCFPACKCNT 0xF216 -+#define F367_OFDM_RCPACKET_COUNTER 0xF21600FF -+ -+/* RCFSPYMISC */ -+#define R367_OFDM_RCFSPYMISC 0xF217 -+#define F367_OFDM_RCLABEL_COUNTER 0xF21700FF -+ -+/* RCFBERCPT4 */ -+#define R367_OFDM_RCFBERCPT4 0xF218 -+#define F367_OFDM_FBERRCMETER_CPT_MMMMSB 0xF21800FF -+ -+/* RCFBERCPT3 */ -+#define R367_OFDM_RCFBERCPT3 0xF219 -+#define F367_OFDM_FBERRCMETER_CPT_MMMSB 0xF21900FF -+ -+/* RCFBERCPT2 */ -+#define R367_OFDM_RCFBERCPT2 0xF21A -+#define F367_OFDM_FBERRCMETER_CPT_MMSB 0xF21A00FF -+ -+/* RCFBERCPT1 */ -+#define R367_OFDM_RCFBERCPT1 0xF21B -+#define F367_OFDM_FBERRCMETER_CPT_MSB 0xF21B00FF -+ -+/* RCFBERCPT0 */ -+#define R367_OFDM_RCFBERCPT0 0xF21C -+#define F367_OFDM_FBERRCMETER_CPT_LSB 0xF21C00FF -+ -+/* RCFBERERR2 */ -+#define R367_OFDM_RCFBERERR2 0xF21D -+#define F367_OFDM_FBERRCMETER_ERR_HI 0xF21D00FF -+ -+/* RCFBERERR1 */ -+#define R367_OFDM_RCFBERERR1 0xF21E -+#define F367_OFDM_FBERRCMETER_ERR 0xF21E00FF -+ -+/* RCFBERERR0 */ -+#define R367_OFDM_RCFBERERR0 0xF21F -+#define F367_OFDM_FBERRCMETER_ERR_LO 0xF21F00FF -+ -+/* RCFSTATESM */ -+#define R367_OFDM_RCFSTATESM 0xF220 -+#define F367_OFDM_RCRSTATE_F 0xF2200080 -+#define F367_OFDM_RCRSTATE_E 0xF2200040 -+#define F367_OFDM_RCRSTATE_D 0xF2200020 -+#define F367_OFDM_RCRSTATE_C 0xF2200010 -+#define F367_OFDM_RCRSTATE_B 0xF2200008 -+#define F367_OFDM_RCRSTATE_A 0xF2200004 -+#define F367_OFDM_RCRSTATE_9 0xF2200002 -+#define F367_OFDM_RCRSTATE_8 0xF2200001 -+ -+/* RCFSTATESL */ -+#define R367_OFDM_RCFSTATESL 0xF221 -+#define F367_OFDM_RCRSTATE_7 0xF2210080 -+#define F367_OFDM_RCRSTATE_6 0xF2210040 -+#define F367_OFDM_RCRSTATE_5 0xF2210020 -+#define F367_OFDM_RCRSTATE_4 0xF2210010 -+#define F367_OFDM_RCRSTATE_3 0xF2210008 -+#define F367_OFDM_RCRSTATE_2 0xF2210004 -+#define F367_OFDM_RCRSTATE_1 0xF2210002 -+#define F367_OFDM_RCRSTATE_0 0xF2210001 -+ -+/* RCFSPYBER */ -+#define R367_OFDM_RCFSPYBER 0xF222 -+#define F367_OFDM_RCFSPYBER_7 0xF2220080 -+#define F367_OFDM_SPYRCOBS_XORREAD 0xF2220040 -+#define F367_OFDM_FSPYRCBER_OBSMODE 0xF2220020 -+#define F367_OFDM_FSPYRCBER_SYNCBYT 0xF2220010 -+#define F367_OFDM_FSPYRCBER_UNSYNC 0xF2220008 -+#define F367_OFDM_FSPYRCBER_CTIME 0xF2220007 -+ -+/* RCFSPYDISTM */ -+#define R367_OFDM_RCFSPYDISTM 0xF223 -+#define F367_OFDM_RCPKTTIME_DISTANCE_HI 0xF22300FF -+ -+/* RCFSPYDISTL */ -+#define R367_OFDM_RCFSPYDISTL 0xF224 -+#define F367_OFDM_RCPKTTIME_DISTANCE_LO 0xF22400FF -+ -+/* RCFSPYOBS7 */ -+#define R367_OFDM_RCFSPYOBS7 0xF228 -+#define F367_OFDM_RCSPYOBS_SPYFAIL 0xF2280080 -+#define F367_OFDM_RCSPYOBS_SPYFAIL1 0xF2280040 -+#define F367_OFDM_RCSPYOBS_ERROR 0xF2280020 -+#define F367_OFDM_RCSPYOBS_STROUT 0xF2280010 -+#define F367_OFDM_RCSPYOBS_RESULTSTATE1 0xF228000F -+ -+/* RCFSPYOBS6 */ -+#define R367_OFDM_RCFSPYOBS6 0xF229 -+#define F367_OFDM_RCSPYOBS_RESULTSTATE0 0xF22900F0 -+#define F367_OFDM_RCSPYOBS_RESULTSTATEM1 0xF229000F -+ -+/* RCFSPYOBS5 */ -+#define R367_OFDM_RCFSPYOBS5 0xF22A -+#define F367_OFDM_RCSPYOBS_BYTEOFPACKET1 0xF22A00FF -+ -+/* RCFSPYOBS4 */ -+#define R367_OFDM_RCFSPYOBS4 0xF22B -+#define F367_OFDM_RCSPYOBS_BYTEVALUE1 0xF22B00FF -+ -+/* RCFSPYOBS3 */ -+#define R367_OFDM_RCFSPYOBS3 0xF22C -+#define F367_OFDM_RCSPYOBS_DATA1 0xF22C00FF -+ -+/* RCFSPYOBS2 */ -+#define R367_OFDM_RCFSPYOBS2 0xF22D -+#define F367_OFDM_RCSPYOBS_DATA0 0xF22D00FF -+ -+/* RCFSPYOBS1 */ -+#define R367_OFDM_RCFSPYOBS1 0xF22E -+#define F367_OFDM_RCSPYOBS_DATAM1 0xF22E00FF -+ -+/* RCFSPYOBS0 */ -+#define R367_OFDM_RCFSPYOBS0 0xF22F -+#define F367_OFDM_RCSPYOBS_DATAM2 0xF22F00FF -+ -+/* TSGENERAL */ -+#define R367_TSGENERAL 0xF230 -+#define F367_TSGENERAL_7 0xF2300080 -+#define F367_TSGENERAL_6 0xF2300040 -+#define F367_TSFIFO_BCLK1ALL 0xF2300020 -+#define F367_TSGENERAL_4 0xF2300010 -+#define F367_MUXSTREAM_OUTMODE 0xF2300008 -+#define F367_TSFIFO_PERMPARAL 0xF2300006 -+#define F367_RST_REEDSOLO 0xF2300001 -+ -+/* RC1SPEED */ -+#define R367_RC1SPEED 0xF231 -+#define F367_TSRCFIFO1_OUTSPEED 0xF23100FF -+ -+/* TSGSTATUS */ -+#define R367_TSGSTATUS 0xF232 -+#define F367_TSGSTATUS_7 0xF2320080 -+#define F367_TSGSTATUS_6 0xF2320040 -+#define F367_RSMEM_FULL 0xF2320020 -+#define F367_RS_MULTCALC 0xF2320010 -+#define F367_RSIN_OVERTIME 0xF2320008 -+#define F367_TSFIFO3_DEMODSEL 0xF2320004 -+#define F367_TSFIFO2_DEMODSEL 0xF2320002 -+#define F367_TSFIFO1_DEMODSEL 0xF2320001 -+ -+ -+/* FECM */ -+#define R367_OFDM_FECM 0xF233 -+#define F367_OFDM_DSS_DVB 0xF2330080 -+#define F367_OFDM_DEMOD_BYPASS 0xF2330040 -+#define F367_OFDM_CMP_SLOWMODE 0xF2330020 -+#define F367_OFDM_DSS_SRCH 0xF2330010 -+#define F367_OFDM_FECM_3 0xF2330008 -+#define F367_OFDM_DIFF_MODEVIT 0xF2330004 -+#define F367_OFDM_SYNCVIT 0xF2330002 -+#define F367_OFDM_I2CSYM 0xF2330001 -+ -+/* VTH12 */ -+#define R367_OFDM_VTH12 0xF234 -+#define F367_OFDM_VTH_12 0xF23400FF -+ -+/* VTH23 */ -+#define R367_OFDM_VTH23 0xF235 -+#define F367_OFDM_VTH_23 0xF23500FF -+ -+/* VTH34 */ -+#define R367_OFDM_VTH34 0xF236 -+#define F367_OFDM_VTH_34 0xF23600FF -+ -+/* VTH56 */ -+#define R367_OFDM_VTH56 0xF237 -+#define F367_OFDM_VTH_56 0xF23700FF -+ -+/* VTH67 */ -+#define R367_OFDM_VTH67 0xF238 -+#define F367_OFDM_VTH_67 0xF23800FF -+ -+/* VTH78 */ -+#define R367_OFDM_VTH78 0xF239 -+#define F367_OFDM_VTH_78 0xF23900FF -+ -+/* VITCURPUN */ -+#define R367_OFDM_VITCURPUN 0xF23A -+#define F367_OFDM_VIT_MAPPING 0xF23A00E0 -+#define F367_OFDM_VIT_CURPUN 0xF23A001F -+ -+/* VERROR */ -+#define R367_OFDM_VERROR 0xF23B -+#define F367_OFDM_REGERR_VIT 0xF23B00FF -+ -+/* PRVIT */ -+#define R367_OFDM_PRVIT 0xF23C -+#define F367_OFDM_PRVIT_7 0xF23C0080 -+#define F367_OFDM_DIS_VTHLOCK 0xF23C0040 -+#define F367_OFDM_E7_8VIT 0xF23C0020 -+#define F367_OFDM_E6_7VIT 0xF23C0010 -+#define F367_OFDM_E5_6VIT 0xF23C0008 -+#define F367_OFDM_E3_4VIT 0xF23C0004 -+#define F367_OFDM_E2_3VIT 0xF23C0002 -+#define F367_OFDM_E1_2VIT 0xF23C0001 -+ -+/* VAVSRVIT */ -+#define R367_OFDM_VAVSRVIT 0xF23D -+#define F367_OFDM_AMVIT 0xF23D0080 -+#define F367_OFDM_FROZENVIT 0xF23D0040 -+#define F367_OFDM_SNVIT 0xF23D0030 -+#define F367_OFDM_TOVVIT 0xF23D000C -+#define F367_OFDM_HYPVIT 0xF23D0003 -+ -+/* VSTATUSVIT */ -+#define R367_OFDM_VSTATUSVIT 0xF23E -+#define F367_OFDM_VITERBI_ON 0xF23E0080 -+#define F367_OFDM_END_LOOPVIT 0xF23E0040 -+#define F367_OFDM_VITERBI_DEPRF 0xF23E0020 -+#define F367_OFDM_PRFVIT 0xF23E0010 -+#define F367_OFDM_LOCKEDVIT 0xF23E0008 -+#define F367_OFDM_VITERBI_DELOCK 0xF23E0004 -+#define F367_OFDM_VIT_DEMODSEL 0xF23E0002 -+#define F367_OFDM_VITERBI_COMPOUT 0xF23E0001 -+ -+/* VTHINUSE */ -+#define R367_OFDM_VTHINUSE 0xF23F -+#define F367_OFDM_VIT_INUSE 0xF23F00FF -+ -+/* KDIV12 */ -+#define R367_OFDM_KDIV12 0xF240 -+#define F367_OFDM_KDIV12_MANUAL 0xF2400080 -+#define F367_OFDM_K_DIVIDER_12 0xF240007F -+ -+/* KDIV23 */ -+#define R367_OFDM_KDIV23 0xF241 -+#define F367_OFDM_KDIV23_MANUAL 0xF2410080 -+#define F367_OFDM_K_DIVIDER_23 0xF241007F -+ -+/* KDIV34 */ -+#define R367_OFDM_KDIV34 0xF242 -+#define F367_OFDM_KDIV34_MANUAL 0xF2420080 -+#define F367_OFDM_K_DIVIDER_34 0xF242007F -+ -+/* KDIV56 */ -+#define R367_OFDM_KDIV56 0xF243 -+#define F367_OFDM_KDIV56_MANUAL 0xF2430080 -+#define F367_OFDM_K_DIVIDER_56 0xF243007F -+ -+/* KDIV67 */ -+#define R367_OFDM_KDIV67 0xF244 -+#define F367_OFDM_KDIV67_MANUAL 0xF2440080 -+#define F367_OFDM_K_DIVIDER_67 0xF244007F -+ -+/* KDIV78 */ -+#define R367_OFDM_KDIV78 0xF245 -+#define F367_OFDM_KDIV78_MANUAL 0xF2450080 -+#define F367_OFDM_K_DIVIDER_78 0xF245007F -+ -+/* SIGPOWER */ -+#define R367_OFDM_SIGPOWER 0xF246 -+#define F367_OFDM_SIGPOWER_MANUAL 0xF2460080 -+#define F367_OFDM_SIG_POWER 0xF246007F -+ -+/* DEMAPVIT */ -+#define R367_OFDM_DEMAPVIT 0xF247 -+#define F367_OFDM_DEMAPVIT_7 0xF2470080 -+#define F367_OFDM_K_DIVIDER_VIT 0xF247007F -+ -+/* VITSCALE */ -+#define R367_OFDM_VITSCALE 0xF248 -+#define F367_OFDM_NVTH_NOSRANGE 0xF2480080 -+#define F367_OFDM_VERROR_MAXMODE 0xF2480040 -+#define F367_OFDM_KDIV_MODE 0xF2480030 -+#define F367_OFDM_NSLOWSN_LOCKED 0xF2480008 -+#define F367_OFDM_DELOCK_PRFLOSS 0xF2480004 -+#define F367_OFDM_DIS_RSFLOCK 0xF2480002 -+#define F367_OFDM_VITSCALE_0 0xF2480001 -+ -+/* FFEC1PRG */ -+#define R367_OFDM_FFEC1PRG 0xF249 -+#define F367_OFDM_FDSS_DVB 0xF2490080 -+#define F367_OFDM_FDSS_SRCH 0xF2490040 -+#define F367_OFDM_FFECPROG_5 0xF2490020 -+#define F367_OFDM_FFECPROG_4 0xF2490010 -+#define F367_OFDM_FFECPROG_3 0xF2490008 -+#define F367_OFDM_FFECPROG_2 0xF2490004 -+#define F367_OFDM_FTS1_DISABLE 0xF2490002 -+#define F367_OFDM_FTS2_DISABLE 0xF2490001 -+ -+/* FVITCURPUN */ -+#define R367_OFDM_FVITCURPUN 0xF24A -+#define F367_OFDM_FVIT_MAPPING 0xF24A00E0 -+#define F367_OFDM_FVIT_CURPUN 0xF24A001F -+ -+/* FVERROR */ -+#define R367_OFDM_FVERROR 0xF24B -+#define F367_OFDM_FREGERR_VIT 0xF24B00FF -+ -+/* FVSTATUSVIT */ -+#define R367_OFDM_FVSTATUSVIT 0xF24C -+#define F367_OFDM_FVITERBI_ON 0xF24C0080 -+#define F367_OFDM_F1END_LOOPVIT 0xF24C0040 -+#define F367_OFDM_FVITERBI_DEPRF 0xF24C0020 -+#define F367_OFDM_FPRFVIT 0xF24C0010 -+#define F367_OFDM_FLOCKEDVIT 0xF24C0008 -+#define F367_OFDM_FVITERBI_DELOCK 0xF24C0004 -+#define F367_OFDM_FVIT_DEMODSEL 0xF24C0002 -+#define F367_OFDM_FVITERBI_COMPOUT 0xF24C0001 -+ -+/* DEBUG_LT1 */ -+#define R367_OFDM_DEBUG_LT1 0xF24D -+#define F367_OFDM_DBG_LT1 0xF24D00FF -+ -+/* DEBUG_LT2 */ -+#define R367_OFDM_DEBUG_LT2 0xF24E -+#define F367_OFDM_DBG_LT2 0xF24E00FF -+ -+/* DEBUG_LT3 */ -+#define R367_OFDM_DEBUG_LT3 0xF24F -+#define F367_OFDM_DBG_LT3 0xF24F00FF -+ -+ /* TSTSFMET */ -+#define R367_OFDM_TSTSFMET 0xF250 -+#define F367_OFDM_TSTSFEC_METRIQUES 0xF25000FF -+ -+ /* SELOUT */ -+#define R367_OFDM_SELOUT 0xF252 -+#define F367_OFDM_EN_SYNC 0xF2520080 -+#define F367_OFDM_EN_TBUSDEMAP 0xF2520040 -+#define F367_OFDM_SELOUT_5 0xF2520020 -+#define F367_OFDM_SELOUT_4 0xF2520010 -+#define F367_OFDM_TSTSYNCHRO_MODE 0xF2520002 -+ -+ /* TSYNC */ -+#define R367_OFDM_TSYNC 0xF253 -+#define F367_OFDM_CURPUN_INCMODE 0xF2530080 -+#define F367_OFDM_CERR_TSTMODE 0xF2530040 -+#define F367_OFDM_SHIFTSOF_MODE 0xF2530030 -+#define F367_OFDM_SLOWPHA_MODE 0xF2530008 -+#define F367_OFDM_PXX_BYPALL 0xF2530004 -+#define F367_OFDM_FROTA45_FIRST 0xF2530002 -+#define F367_OFDM_TST_BCHERROR 0xF2530001 -+ -+ /* TSTERR */ -+#define R367_OFDM_TSTERR 0xF254 -+#define F367_OFDM_TST_LONGPKT 0xF2540080 -+#define F367_OFDM_TST_ISSYION 0xF2540040 -+#define F367_OFDM_TST_NPDON 0xF2540020 -+#define F367_OFDM_TSTERR_4 0xF2540010 -+#define F367_OFDM_TRACEBACK_MODE 0xF2540008 -+#define F367_OFDM_TST_RSPARITY 0xF2540004 -+#define F367_OFDM_METRIQUE_MODE 0xF2540003 -+ -+ /* TSFSYNC */ -+#define R367_OFDM_TSFSYNC 0xF255 -+#define F367_OFDM_EN_SFECSYNC 0xF2550080 -+#define F367_OFDM_EN_SFECDEMAP 0xF2550040 -+#define F367_OFDM_SFCERR_TSTMODE 0xF2550020 -+#define F367_OFDM_SFECPXX_BYPALL 0xF2550010 -+#define F367_OFDM_SFECTSTSYNCHRO_MODE 0xF255000F -+ -+ /* TSTSFERR */ -+#define R367_OFDM_TSTSFERR 0xF256 -+#define F367_OFDM_TSTSTERR_7 0xF2560080 -+#define F367_OFDM_TSTSTERR_6 0xF2560040 -+#define F367_OFDM_TSTSTERR_5 0xF2560020 -+#define F367_OFDM_TSTSTERR_4 0xF2560010 -+#define F367_OFDM_SFECTRACEBACK_MODE 0xF2560008 -+#define F367_OFDM_SFEC_NCONVPROG 0xF2560004 -+#define F367_OFDM_SFECMETRIQUE_MODE 0xF2560003 -+ -+ /* TSTTSSF1 */ -+#define R367_OFDM_TSTTSSF1 0xF258 -+#define F367_OFDM_TSTERSSF 0xF2580080 -+#define F367_OFDM_TSTTSSFEN 0xF2580040 -+#define F367_OFDM_SFEC_OUTMODE 0xF2580030 -+#define F367_OFDM_XLSF_NOFTHRESHOLD 0xF2580008 -+#define F367_OFDM_TSTTSSF_STACKSEL 0xF2580007 -+ -+ /* TSTTSSF2 */ -+#define R367_OFDM_TSTTSSF2 0xF259 -+#define F367_OFDM_DILSF_DBBHEADER 0xF2590080 -+#define F367_OFDM_TSTTSSF_DISBUG 0xF2590040 -+#define F367_OFDM_TSTTSSF_NOBADSTART 0xF2590020 -+#define F367_OFDM_TSTTSSF_SELECT 0xF259001F -+ -+ /* TSTTSSF3 */ -+#define R367_OFDM_TSTTSSF3 0xF25A -+#define F367_OFDM_TSTTSSF3_7 0xF25A0080 -+#define F367_OFDM_TSTTSSF3_6 0xF25A0040 -+#define F367_OFDM_TSTTSSF3_5 0xF25A0020 -+#define F367_OFDM_TSTTSSF3_4 0xF25A0010 -+#define F367_OFDM_TSTTSSF3_3 0xF25A0008 -+#define F367_OFDM_TSTTSSF3_2 0xF25A0004 -+#define F367_OFDM_TSTTSSF3_1 0xF25A0002 -+#define F367_OFDM_DISSF_CLKENABLE 0xF25A0001 -+ -+ /* TSTTS1 */ -+#define R367_OFDM_TSTTS1 0xF25C -+#define F367_OFDM_TSTERS 0xF25C0080 -+#define F367_OFDM_TSFIFO_DSSSYNCB 0xF25C0040 -+#define F367_OFDM_TSTTS_FSPYBEFRS 0xF25C0020 -+#define F367_OFDM_NFORCE_SYNCBYTE 0xF25C0010 -+#define F367_OFDM_XL_NOFTHRESHOLD 0xF25C0008 -+#define F367_OFDM_TSTTS_FRFORCEPKT 0xF25C0004 -+#define F367_OFDM_DESCR_NOTAUTO 0xF25C0002 -+#define F367_OFDM_TSTTSEN 0xF25C0001 -+ -+ /* TSTTS2 */ -+#define R367_OFDM_TSTTS2 0xF25D -+#define F367_OFDM_DIL_DBBHEADER 0xF25D0080 -+#define F367_OFDM_TSTTS_NOBADXXX 0xF25D0040 -+#define F367_OFDM_TSFIFO_DELSPEEDUP 0xF25D0020 -+#define F367_OFDM_TSTTS_SELECT 0xF25D001F -+ -+ /* TSTTS3 */ -+#define R367_OFDM_TSTTS3 0xF25E -+#define F367_OFDM_TSTTS_NOPKTGAIN 0xF25E0080 -+#define F367_OFDM_TSTTS_NOPKTENE 0xF25E0040 -+#define F367_OFDM_TSTTS_ISOLATION 0xF25E0020 -+#define F367_OFDM_TSTTS_DISBUG 0xF25E0010 -+#define F367_OFDM_TSTTS_NOBADSTART 0xF25E0008 -+#define F367_OFDM_TSTTS_STACKSEL 0xF25E0007 -+ -+ /* TSTTS4 */ -+#define R367_OFDM_TSTTS4 0xF25F -+#define F367_OFDM_TSTTS4_7 0xF25F0080 -+#define F367_OFDM_TSTTS4_6 0xF25F0040 -+#define F367_OFDM_TSTTS4_5 0xF25F0020 -+#define F367_OFDM_TSTTS_DISDSTATE 0xF25F0010 -+#define F367_OFDM_TSTTS_FASTNOSYNC 0xF25F0008 -+#define F367_OFDM_EXT_FECSPYIN 0xF25F0004 -+#define F367_OFDM_TSTTS_NODPZERO 0xF25F0002 -+#define F367_OFDM_TSTTS_NODIV3 0xF25F0001 -+ -+ /* TSTTSRC */ -+#define R367_OFDM_TSTTSRC 0xF26C -+#define F367_OFDM_TSTTSRC_7 0xF26C0080 -+#define F367_OFDM_TSRCFIFO_DSSSYNCB 0xF26C0040 -+#define F367_OFDM_TSRCFIFO_DPUNACTIVE 0xF26C0020 -+#define F367_OFDM_TSRCFIFO_DELSPEEDUP 0xF26C0010 -+#define F367_OFDM_TSTTSRC_NODIV3 0xF26C0008 -+#define F367_OFDM_TSTTSRC_FRFORCEPKT 0xF26C0004 -+#define F367_OFDM_SAT25_SDDORIGINE 0xF26C0002 -+#define F367_OFDM_TSTTSRC_INACTIVE 0xF26C0001 -+ -+ /* TSTTSRS */ -+#define R367_OFDM_TSTTSRS 0xF26D -+#define F367_OFDM_TSTTSRS_7 0xF26D0080 -+#define F367_OFDM_TSTTSRS_6 0xF26D0040 -+#define F367_OFDM_TSTTSRS_5 0xF26D0020 -+#define F367_OFDM_TSTTSRS_4 0xF26D0010 -+#define F367_OFDM_TSTTSRS_3 0xF26D0008 -+#define F367_OFDM_TSTTSRS_2 0xF26D0004 -+#define F367_OFDM_TSTRS_DISRS2 0xF26D0002 -+#define F367_OFDM_TSTRS_DISRS1 0xF26D0001 -+ -+/* TSSTATEM */ -+#define R367_OFDM_TSSTATEM 0xF270 -+#define F367_OFDM_TSDIL_ON 0xF2700080 -+#define F367_OFDM_TSSKIPRS_ON 0xF2700040 -+#define F367_OFDM_TSRS_ON 0xF2700020 -+#define F367_OFDM_TSDESCRAMB_ON 0xF2700010 -+#define F367_OFDM_TSFRAME_MODE 0xF2700008 -+#define F367_OFDM_TS_DISABLE 0xF2700004 -+#define F367_OFDM_TSACM_MODE 0xF2700002 -+#define F367_OFDM_TSOUT_NOSYNC 0xF2700001 -+ -+/* TSSTATEL */ -+#define R367_OFDM_TSSTATEL 0xF271 -+#define F367_OFDM_TSNOSYNCBYTE 0xF2710080 -+#define F367_OFDM_TSPARITY_ON 0xF2710040 -+#define F367_OFDM_TSSYNCOUTRS_ON 0xF2710020 -+#define F367_OFDM_TSDVBS2_MODE 0xF2710010 -+#define F367_OFDM_TSISSYI_ON 0xF2710008 -+#define F367_OFDM_TSNPD_ON 0xF2710004 -+#define F367_OFDM_TSCRC8_ON 0xF2710002 -+#define F367_OFDM_TSDSS_PACKET 0xF2710001 -+ -+/* TSCFGH */ -+#define R367_OFDM_TSCFGH 0xF272 -+#define F367_OFDM_TSFIFO_DVBCI 0xF2720080 -+#define F367_OFDM_TSFIFO_SERIAL 0xF2720040 -+#define F367_OFDM_TSFIFO_TEIUPDATE 0xF2720020 -+#define F367_OFDM_TSFIFO_DUTY50 0xF2720010 -+#define F367_OFDM_TSFIFO_HSGNLOUT 0xF2720008 -+#define F367_OFDM_TSFIFO_ERRMODE 0xF2720006 -+#define F367_OFDM_RST_HWARE 0xF2720001 -+ -+/* TSCFGM */ -+#define R367_OFDM_TSCFGM 0xF273 -+#define F367_OFDM_TSFIFO_MANSPEED 0xF27300C0 -+#define F367_OFDM_TSFIFO_PERMDATA 0xF2730020 -+#define F367_OFDM_TSFIFO_NONEWSGNL 0xF2730010 -+#define F367_OFDM_TSFIFO_BITSPEED 0xF2730008 -+#define F367_OFDM_NPD_SPECDVBS2 0xF2730004 -+#define F367_OFDM_TSFIFO_STOPCKDIS 0xF2730002 -+#define F367_OFDM_TSFIFO_INVDATA 0xF2730001 -+ -+/* TSCFGL */ -+#define R367_OFDM_TSCFGL 0xF274 -+#define F367_OFDM_TSFIFO_BCLKDEL1CK 0xF27400C0 -+#define F367_OFDM_BCHERROR_MODE 0xF2740030 -+#define F367_OFDM_TSFIFO_NSGNL2DATA 0xF2740008 -+#define F367_OFDM_TSFIFO_EMBINDVB 0xF2740004 -+#define F367_OFDM_TSFIFO_DPUNACT 0xF2740002 -+#define F367_OFDM_TSFIFO_NPDOFF 0xF2740001 -+ -+/* TSSYNC */ -+#define R367_OFDM_TSSYNC 0xF275 -+#define F367_OFDM_TSFIFO_PERMUTE 0xF2750080 -+#define F367_OFDM_TSFIFO_FISCR3B 0xF2750060 -+#define F367_OFDM_TSFIFO_SYNCMODE 0xF2750018 -+#define F367_OFDM_TSFIFO_SYNCSEL 0xF2750007 -+ -+/* TSINSDELH */ -+#define R367_OFDM_TSINSDELH 0xF276 -+#define F367_OFDM_TSDEL_SYNCBYTE 0xF2760080 -+#define F367_OFDM_TSDEL_XXHEADER 0xF2760040 -+#define F367_OFDM_TSDEL_BBHEADER 0xF2760020 -+#define F367_OFDM_TSDEL_DATAFIELD 0xF2760010 -+#define F367_OFDM_TSINSDEL_ISCR 0xF2760008 -+#define F367_OFDM_TSINSDEL_NPD 0xF2760004 -+#define F367_OFDM_TSINSDEL_RSPARITY 0xF2760002 -+#define F367_OFDM_TSINSDEL_CRC8 0xF2760001 -+ -+/* TSINSDELM */ -+#define R367_OFDM_TSINSDELM 0xF277 -+#define F367_OFDM_TSINS_BBPADDING 0xF2770080 -+#define F367_OFDM_TSINS_BCHFEC 0xF2770040 -+#define F367_OFDM_TSINS_LDPCFEC 0xF2770020 -+#define F367_OFDM_TSINS_EMODCOD 0xF2770010 -+#define F367_OFDM_TSINS_TOKEN 0xF2770008 -+#define F367_OFDM_TSINS_XXXERR 0xF2770004 -+#define F367_OFDM_TSINS_MATYPE 0xF2770002 -+#define F367_OFDM_TSINS_UPL 0xF2770001 -+ -+/* TSINSDELL */ -+#define R367_OFDM_TSINSDELL 0xF278 -+#define F367_OFDM_TSINS_DFL 0xF2780080 -+#define F367_OFDM_TSINS_SYNCD 0xF2780040 -+#define F367_OFDM_TSINS_BLOCLEN 0xF2780020 -+#define F367_OFDM_TSINS_SIGPCOUNT 0xF2780010 -+#define F367_OFDM_TSINS_FIFO 0xF2780008 -+#define F367_OFDM_TSINS_REALPACK 0xF2780004 -+#define F367_OFDM_TSINS_TSCONFIG 0xF2780002 -+#define F367_OFDM_TSINS_LATENCY 0xF2780001 -+ -+/* TSDIVN */ -+#define R367_OFDM_TSDIVN 0xF279 -+#define F367_OFDM_TSFIFO_LOWSPEED 0xF2790080 -+#define F367_OFDM_BYTE_OVERSAMPLING 0xF2790070 -+#define F367_OFDM_TSMANUAL_PACKETNBR 0xF279000F -+ -+/* TSDIVPM */ -+#define R367_OFDM_TSDIVPM 0xF27A -+#define F367_OFDM_TSMANUAL_P_HI 0xF27A00FF -+ -+/* TSDIVPL */ -+#define R367_OFDM_TSDIVPL 0xF27B -+#define F367_OFDM_TSMANUAL_P_LO 0xF27B00FF -+ -+/* TSDIVQM */ -+#define R367_OFDM_TSDIVQM 0xF27C -+#define F367_OFDM_TSMANUAL_Q_HI 0xF27C00FF -+ -+/* TSDIVQL */ -+#define R367_OFDM_TSDIVQL 0xF27D -+#define F367_OFDM_TSMANUAL_Q_LO 0xF27D00FF -+ -+/* TSDILSTKM */ -+#define R367_OFDM_TSDILSTKM 0xF27E -+#define F367_OFDM_TSFIFO_DILSTK_HI 0xF27E00FF -+ -+/* TSDILSTKL */ -+#define R367_OFDM_TSDILSTKL 0xF27F -+#define F367_OFDM_TSFIFO_DILSTK_LO 0xF27F00FF -+ -+/* TSSPEED */ -+#define R367_OFDM_TSSPEED 0xF280 -+#define F367_OFDM_TSFIFO_OUTSPEED 0xF28000FF -+ -+/* TSSTATUS */ -+#define R367_OFDM_TSSTATUS 0xF281 -+#define F367_OFDM_TSFIFO_LINEOK 0xF2810080 -+#define F367_OFDM_TSFIFO_ERROR 0xF2810040 -+#define F367_OFDM_TSFIFO_DATA7 0xF2810020 -+#define F367_OFDM_TSFIFO_NOSYNC 0xF2810010 -+#define F367_OFDM_ISCR_INITIALIZED 0xF2810008 -+#define F367_OFDM_ISCR_UPDATED 0xF2810004 -+#define F367_OFDM_SOFFIFO_UNREGUL 0xF2810002 -+#define F367_OFDM_DIL_READY 0xF2810001 -+ -+/* TSSTATUS2 */ -+#define R367_OFDM_TSSTATUS2 0xF282 -+#define F367_OFDM_TSFIFO_DEMODSEL 0xF2820080 -+#define F367_OFDM_TSFIFOSPEED_STORE 0xF2820040 -+#define F367_OFDM_DILXX_RESET 0xF2820020 -+#define F367_OFDM_TSSERIAL_IMPOSSIBLE 0xF2820010 -+#define F367_OFDM_TSFIFO_UNDERSPEED 0xF2820008 -+#define F367_OFDM_BITSPEED_EVENT 0xF2820004 -+#define F367_OFDM_UL_SCRAMBDETECT 0xF2820002 -+#define F367_OFDM_ULDTV67_FALSELOCK 0xF2820001 -+ -+/* TSBITRATEM */ -+#define R367_OFDM_TSBITRATEM 0xF283 -+#define F367_OFDM_TSFIFO_BITRATE_HI 0xF28300FF -+ -+/* TSBITRATEL */ -+#define R367_OFDM_TSBITRATEL 0xF284 -+#define F367_OFDM_TSFIFO_BITRATE_LO 0xF28400FF -+ -+/* TSPACKLENM */ -+#define R367_OFDM_TSPACKLENM 0xF285 -+#define F367_OFDM_TSFIFO_PACKCPT 0xF28500E0 -+#define F367_OFDM_DIL_RPLEN_HI 0xF285001F -+ -+/* TSPACKLENL */ -+#define R367_OFDM_TSPACKLENL 0xF286 -+#define F367_OFDM_DIL_RPLEN_LO 0xF28600FF -+ -+/* TSBLOCLENM */ -+#define R367_OFDM_TSBLOCLENM 0xF287 -+#define F367_OFDM_TSFIFO_PFLEN_HI 0xF28700FF -+ -+/* TSBLOCLENL */ -+#define R367_OFDM_TSBLOCLENL 0xF288 -+#define F367_OFDM_TSFIFO_PFLEN_LO 0xF28800FF -+ -+/* TSDLYH */ -+#define R367_OFDM_TSDLYH 0xF289 -+#define F367_OFDM_SOFFIFO_TSTIMEVALID 0xF2890080 -+#define F367_OFDM_SOFFIFO_SPEEDUP 0xF2890040 -+#define F367_OFDM_SOFFIFO_STOP 0xF2890020 -+#define F367_OFDM_SOFFIFO_REGULATED 0xF2890010 -+#define F367_OFDM_SOFFIFO_REALSBOFF_HI 0xF289000F -+ -+/* TSDLYM */ -+#define R367_OFDM_TSDLYM 0xF28A -+#define F367_OFDM_SOFFIFO_REALSBOFF_MED 0xF28A00FF -+ -+/* TSDLYL */ -+#define R367_OFDM_TSDLYL 0xF28B -+#define F367_OFDM_SOFFIFO_REALSBOFF_LO 0xF28B00FF -+ -+/* TSNPDAV */ -+#define R367_OFDM_TSNPDAV 0xF28C -+#define F367_OFDM_TSNPD_AVERAGE 0xF28C00FF -+ -+/* TSBUFSTATH */ -+#define R367_OFDM_TSBUFSTATH 0xF28D -+#define F367_OFDM_TSISCR_3BYTES 0xF28D0080 -+#define F367_OFDM_TSISCR_NEWDATA 0xF28D0040 -+#define F367_OFDM_TSISCR_BUFSTAT_HI 0xF28D003F -+ -+/* TSBUFSTATM */ -+#define R367_OFDM_TSBUFSTATM 0xF28E -+#define F367_OFDM_TSISCR_BUFSTAT_MED 0xF28E00FF -+ -+/* TSBUFSTATL */ -+#define R367_OFDM_TSBUFSTATL 0xF28F -+#define F367_OFDM_TSISCR_BUFSTAT_LO 0xF28F00FF -+ -+/* TSDEBUGM */ -+#define R367_OFDM_TSDEBUGM 0xF290 -+#define F367_OFDM_TSFIFO_ILLPACKET 0xF2900080 -+#define F367_OFDM_DIL_NOSYNC 0xF2900040 -+#define F367_OFDM_DIL_ISCR 0xF2900020 -+#define F367_OFDM_DILOUT_BSYNCB 0xF2900010 -+#define F367_OFDM_TSFIFO_EMPTYPKT 0xF2900008 -+#define F367_OFDM_TSFIFO_EMPTYRD 0xF2900004 -+#define F367_OFDM_SOFFIFO_STOPM 0xF2900002 -+#define F367_OFDM_SOFFIFO_SPEEDUPM 0xF2900001 -+ -+/* TSDEBUGL */ -+#define R367_OFDM_TSDEBUGL 0xF291 -+#define F367_OFDM_TSFIFO_PACKLENFAIL 0xF2910080 -+#define F367_OFDM_TSFIFO_SYNCBFAIL 0xF2910040 -+#define F367_OFDM_TSFIFO_VITLIBRE 0xF2910020 -+#define F367_OFDM_TSFIFO_BOOSTSPEEDM 0xF2910010 -+#define F367_OFDM_TSFIFO_UNDERSPEEDM 0xF2910008 -+#define F367_OFDM_TSFIFO_ERROR_EVNT 0xF2910004 -+#define F367_OFDM_TSFIFO_FULL 0xF2910002 -+#define F367_OFDM_TSFIFO_OVERFLOWM 0xF2910001 -+ -+/* TSDLYSETH */ -+#define R367_OFDM_TSDLYSETH 0xF292 -+#define F367_OFDM_SOFFIFO_OFFSET 0xF29200E0 -+#define F367_OFDM_SOFFIFO_SYMBOFFSET_HI 0xF292001F -+ -+/* TSDLYSETM */ -+#define R367_OFDM_TSDLYSETM 0xF293 -+#define F367_OFDM_SOFFIFO_SYMBOFFSET_MED 0xF29300FF -+ -+/* TSDLYSETL */ -+#define R367_OFDM_TSDLYSETL 0xF294 -+#define F367_OFDM_SOFFIFO_SYMBOFFSET_LO 0xF29400FF -+ -+/* TSOBSCFG */ -+#define R367_OFDM_TSOBSCFG 0xF295 -+#define F367_OFDM_TSFIFO_OBSCFG 0xF29500FF -+ -+/* TSOBSM */ -+#define R367_OFDM_TSOBSM 0xF296 -+#define F367_OFDM_TSFIFO_OBSDATA_HI 0xF29600FF -+ -+/* TSOBSL */ -+#define R367_OFDM_TSOBSL 0xF297 -+#define F367_OFDM_TSFIFO_OBSDATA_LO 0xF29700FF -+ -+/* ERRCTRL1 */ -+#define R367_OFDM_ERRCTRL1 0xF298 -+#define F367_OFDM_ERR_SRC1 0xF29800F0 -+#define F367_OFDM_ERRCTRL1_3 0xF2980008 -+#define F367_OFDM_NUM_EVT1 0xF2980007 -+ -+/* ERRCNT1H */ -+#define R367_OFDM_ERRCNT1H 0xF299 -+#define F367_OFDM_ERRCNT1_OLDVALUE 0xF2990080 -+#define F367_OFDM_ERR_CNT1 0xF299007F -+ -+/* ERRCNT1M */ -+#define R367_OFDM_ERRCNT1M 0xF29A -+#define F367_OFDM_ERR_CNT1_HI 0xF29A00FF -+ -+/* ERRCNT1L */ -+#define R367_OFDM_ERRCNT1L 0xF29B -+#define F367_OFDM_ERR_CNT1_LO 0xF29B00FF -+ -+/* ERRCTRL2 */ -+#define R367_OFDM_ERRCTRL2 0xF29C -+#define F367_OFDM_ERR_SRC2 0xF29C00F0 -+#define F367_OFDM_ERRCTRL2_3 0xF29C0008 -+#define F367_OFDM_NUM_EVT2 0xF29C0007 -+ -+/* ERRCNT2H */ -+#define R367_OFDM_ERRCNT2H 0xF29D -+#define F367_OFDM_ERRCNT2_OLDVALUE 0xF29D0080 -+#define F367_OFDM_ERR_CNT2_HI 0xF29D007F -+ -+/* ERRCNT2M */ -+#define R367_OFDM_ERRCNT2M 0xF29E -+#define F367_OFDM_ERR_CNT2_MED 0xF29E00FF -+ -+/* ERRCNT2L */ -+#define R367_OFDM_ERRCNT2L 0xF29F -+#define F367_OFDM_ERR_CNT2_LO 0xF29F00FF -+ -+/* FECSPY */ -+#define R367_OFDM_FECSPY 0xF2A0 -+#define F367_OFDM_SPY_ENABLE 0xF2A00080 -+#define F367_OFDM_NO_SYNCBYTE 0xF2A00040 -+#define F367_OFDM_SERIAL_MODE 0xF2A00020 -+#define F367_OFDM_UNUSUAL_PACKET 0xF2A00010 -+#define F367_OFDM_BERMETER_DATAMODE 0xF2A0000C -+#define F367_OFDM_BERMETER_LMODE 0xF2A00002 -+#define F367_OFDM_BERMETER_RESET 0xF2A00001 -+ -+/* FSPYCFG */ -+#define R367_OFDM_FSPYCFG 0xF2A1 -+#define F367_OFDM_FECSPY_INPUT 0xF2A100C0 -+#define F367_OFDM_RST_ON_ERROR 0xF2A10020 -+#define F367_OFDM_ONE_SHOT 0xF2A10010 -+#define F367_OFDM_I2C_MOD 0xF2A1000C -+#define F367_OFDM_SPY_HYSTERESIS 0xF2A10003 -+ -+/* FSPYDATA */ -+#define R367_OFDM_FSPYDATA 0xF2A2 -+#define F367_OFDM_SPY_STUFFING 0xF2A20080 -+#define F367_OFDM_NOERROR_PKTJITTER 0xF2A20040 -+#define F367_OFDM_SPY_CNULLPKT 0xF2A20020 -+#define F367_OFDM_SPY_OUTDATA_MODE 0xF2A2001F -+ -+/* FSPYOUT */ -+#define R367_OFDM_FSPYOUT 0xF2A3 -+#define F367_OFDM_FSPY_DIRECT 0xF2A30080 -+#define F367_OFDM_FSPYOUT_6 0xF2A30040 -+#define F367_OFDM_SPY_OUTDATA_BUS 0xF2A30038 -+#define F367_OFDM_STUFF_MODE 0xF2A30007 -+ -+/* FSTATUS */ -+#define R367_OFDM_FSTATUS 0xF2A4 -+#define F367_OFDM_SPY_ENDSIM 0xF2A40080 -+#define F367_OFDM_VALID_SIM 0xF2A40040 -+#define F367_OFDM_FOUND_SIGNAL 0xF2A40020 -+#define F367_OFDM_DSS_SYNCBYTE 0xF2A40010 -+#define F367_OFDM_RESULT_STATE 0xF2A4000F -+ -+/* FGOODPACK */ -+#define R367_OFDM_FGOODPACK 0xF2A5 -+#define F367_OFDM_FGOOD_PACKET 0xF2A500FF -+ -+/* FPACKCNT */ -+#define R367_OFDM_FPACKCNT 0xF2A6 -+#define F367_OFDM_FPACKET_COUNTER 0xF2A600FF -+ -+/* FSPYMISC */ -+#define R367_OFDM_FSPYMISC 0xF2A7 -+#define F367_OFDM_FLABEL_COUNTER 0xF2A700FF -+ -+/* FBERCPT4 */ -+#define R367_OFDM_FBERCPT4 0xF2A8 -+#define F367_OFDM_FBERMETER_CPT5 0xF2A800FF -+ -+/* FBERCPT3 */ -+#define R367_OFDM_FBERCPT3 0xF2A9 -+#define F367_OFDM_FBERMETER_CPT4 0xF2A900FF -+ -+/* FBERCPT2 */ -+#define R367_OFDM_FBERCPT2 0xF2AA -+#define F367_OFDM_FBERMETER_CPT3 0xF2AA00FF -+ -+/* FBERCPT1 */ -+#define R367_OFDM_FBERCPT1 0xF2AB -+#define F367_OFDM_FBERMETER_CPT2 0xF2AB00FF -+ -+/* FBERCPT0 */ -+#define R367_OFDM_FBERCPT0 0xF2AC -+#define F367_OFDM_FBERMETER_CPT1 0xF2AC00FF -+ -+/* FBERERR2 */ -+#define R367_OFDM_FBERERR2 0xF2AD -+#define F367_OFDM_FBERMETER_ERR_HI 0xF2AD00FF -+ -+/* FBERERR1 */ -+#define R367_OFDM_FBERERR1 0xF2AE -+#define F367_OFDM_FBERMETER_ERR_MED 0xF2AE00FF -+ -+/* FBERERR0 */ -+#define R367_OFDM_FBERERR0 0xF2AF -+#define F367_OFDM_FBERMETER_ERR_LO 0xF2AF00FF -+ -+/* FSTATESM */ -+#define R367_OFDM_FSTATESM 0xF2B0 -+#define F367_OFDM_RSTATE_F 0xF2B00080 -+#define F367_OFDM_RSTATE_E 0xF2B00040 -+#define F367_OFDM_RSTATE_D 0xF2B00020 -+#define F367_OFDM_RSTATE_C 0xF2B00010 -+#define F367_OFDM_RSTATE_B 0xF2B00008 -+#define F367_OFDM_RSTATE_A 0xF2B00004 -+#define F367_OFDM_RSTATE_9 0xF2B00002 -+#define F367_OFDM_RSTATE_8 0xF2B00001 -+ -+/* FSTATESL */ -+#define R367_OFDM_FSTATESL 0xF2B1 -+#define F367_OFDM_RSTATE_7 0xF2B10080 -+#define F367_OFDM_RSTATE_6 0xF2B10040 -+#define F367_OFDM_RSTATE_5 0xF2B10020 -+#define F367_OFDM_RSTATE_4 0xF2B10010 -+#define F367_OFDM_RSTATE_3 0xF2B10008 -+#define F367_OFDM_RSTATE_2 0xF2B10004 -+#define F367_OFDM_RSTATE_1 0xF2B10002 -+#define F367_OFDM_RSTATE_0 0xF2B10001 -+ -+/* FSPYBER */ -+#define R367_OFDM_FSPYBER 0xF2B2 -+#define F367_OFDM_FSPYBER_7 0xF2B20080 -+#define F367_OFDM_FSPYOBS_XORREAD 0xF2B20040 -+#define F367_OFDM_FSPYBER_OBSMODE 0xF2B20020 -+#define F367_OFDM_FSPYBER_SYNCBYTE 0xF2B20010 -+#define F367_OFDM_FSPYBER_UNSYNC 0xF2B20008 -+#define F367_OFDM_FSPYBER_CTIME 0xF2B20007 -+ -+/* FSPYDISTM */ -+#define R367_OFDM_FSPYDISTM 0xF2B3 -+#define F367_OFDM_PKTTIME_DISTANCE_HI 0xF2B300FF -+ -+/* FSPYDISTL */ -+#define R367_OFDM_FSPYDISTL 0xF2B4 -+#define F367_OFDM_PKTTIME_DISTANCE_LO 0xF2B400FF -+ -+/* FSPYOBS7 */ -+#define R367_OFDM_FSPYOBS7 0xF2B8 -+#define F367_OFDM_FSPYOBS_SPYFAIL 0xF2B80080 -+#define F367_OFDM_FSPYOBS_SPYFAIL1 0xF2B80040 -+#define F367_OFDM_FSPYOBS_ERROR 0xF2B80020 -+#define F367_OFDM_FSPYOBS_STROUT 0xF2B80010 -+#define F367_OFDM_FSPYOBS_RESULTSTATE1 0xF2B8000F -+ -+/* FSPYOBS6 */ -+#define R367_OFDM_FSPYOBS6 0xF2B9 -+#define F367_OFDM_FSPYOBS_RESULTSTATE0 0xF2B900F0 -+#define F367_OFDM_FSPYOBS_RESULTSTATEM1 0xF2B9000F -+ -+/* FSPYOBS5 */ -+#define R367_OFDM_FSPYOBS5 0xF2BA -+#define F367_OFDM_FSPYOBS_BYTEOFPACKET1 0xF2BA00FF -+ -+/* FSPYOBS4 */ -+#define R367_OFDM_FSPYOBS4 0xF2BB -+#define F367_OFDM_FSPYOBS_BYTEVALUE1 0xF2BB00FF -+ -+/* FSPYOBS3 */ -+#define R367_OFDM_FSPYOBS3 0xF2BC -+#define F367_OFDM_FSPYOBS_DATA1 0xF2BC00FF -+ -+/* FSPYOBS2 */ -+#define R367_OFDM_FSPYOBS2 0xF2BD -+#define F367_OFDM_FSPYOBS_DATA0 0xF2BD00FF -+ -+/* FSPYOBS1 */ -+#define R367_OFDM_FSPYOBS1 0xF2BE -+#define F367_OFDM_FSPYOBS_DATAM1 0xF2BE00FF -+ -+/* FSPYOBS0 */ -+#define R367_OFDM_FSPYOBS0 0xF2BF -+#define F367_OFDM_FSPYOBS_DATAM2 0xF2BF00FF -+ -+/* SFDEMAP */ -+#define R367_OFDM_SFDEMAP 0xF2C0 -+#define F367_OFDM_SFDEMAP_7 0xF2C00080 -+#define F367_OFDM_SFEC_K_DIVIDER_VIT 0xF2C0007F -+ -+/* SFERROR */ -+#define R367_OFDM_SFERROR 0xF2C1 -+#define F367_OFDM_SFEC_REGERR_VIT 0xF2C100FF -+ -+/* SFAVSR */ -+#define R367_OFDM_SFAVSR 0xF2C2 -+#define F367_OFDM_SFEC_SUMERRORS 0xF2C20080 -+#define F367_OFDM_SERROR_MAXMODE 0xF2C20040 -+#define F367_OFDM_SN_SFEC 0xF2C20030 -+#define F367_OFDM_KDIV_MODE_SFEC 0xF2C2000C -+#define F367_OFDM_SFAVSR_1 0xF2C20002 -+#define F367_OFDM_SFAVSR_0 0xF2C20001 -+ -+/* SFECSTATUS */ -+#define R367_OFDM_SFECSTATUS 0xF2C3 -+#define F367_OFDM_SFEC_ON 0xF2C30080 -+#define F367_OFDM_SFSTATUS_6 0xF2C30040 -+#define F367_OFDM_SFSTATUS_5 0xF2C30020 -+#define F367_OFDM_SFSTATUS_4 0xF2C30010 -+#define F367_OFDM_LOCKEDSFEC 0xF2C30008 -+#define F367_OFDM_SFEC_DELOCK 0xF2C30004 -+#define F367_OFDM_SFEC_DEMODSEL1 0xF2C30002 -+#define F367_OFDM_SFEC_OVFON 0xF2C30001 -+ -+/* SFKDIV12 */ -+#define R367_OFDM_SFKDIV12 0xF2C4 -+#define F367_OFDM_SFECKDIV12_MAN 0xF2C40080 -+#define F367_OFDM_SFEC_K_DIVIDER_12 0xF2C4007F -+ -+/* SFKDIV23 */ -+#define R367_OFDM_SFKDIV23 0xF2C5 -+#define F367_OFDM_SFECKDIV23_MAN 0xF2C50080 -+#define F367_OFDM_SFEC_K_DIVIDER_23 0xF2C5007F -+ -+/* SFKDIV34 */ -+#define R367_OFDM_SFKDIV34 0xF2C6 -+#define F367_OFDM_SFECKDIV34_MAN 0xF2C60080 -+#define F367_OFDM_SFEC_K_DIVIDER_34 0xF2C6007F -+ -+/* SFKDIV56 */ -+#define R367_OFDM_SFKDIV56 0xF2C7 -+#define F367_OFDM_SFECKDIV56_MAN 0xF2C70080 -+#define F367_OFDM_SFEC_K_DIVIDER_56 0xF2C7007F -+ -+/* SFKDIV67 */ -+#define R367_OFDM_SFKDIV67 0xF2C8 -+#define F367_OFDM_SFECKDIV67_MAN 0xF2C80080 -+#define F367_OFDM_SFEC_K_DIVIDER_67 0xF2C8007F -+ -+/* SFKDIV78 */ -+#define R367_OFDM_SFKDIV78 0xF2C9 -+#define F367_OFDM_SFECKDIV78_MAN 0xF2C90080 -+#define F367_OFDM_SFEC_K_DIVIDER_78 0xF2C9007F -+ -+/* SFDILSTKM */ -+#define R367_OFDM_SFDILSTKM 0xF2CA -+#define F367_OFDM_SFEC_PACKCPT 0xF2CA00E0 -+#define F367_OFDM_SFEC_DILSTK_HI 0xF2CA001F -+ -+/* SFDILSTKL */ -+#define R367_OFDM_SFDILSTKL 0xF2CB -+#define F367_OFDM_SFEC_DILSTK_LO 0xF2CB00FF -+ -+/* SFSTATUS */ -+#define R367_OFDM_SFSTATUS 0xF2CC -+#define F367_OFDM_SFEC_LINEOK 0xF2CC0080 -+#define F367_OFDM_SFEC_ERROR 0xF2CC0040 -+#define F367_OFDM_SFEC_DATA7 0xF2CC0020 -+#define F367_OFDM_SFEC_OVERFLOW 0xF2CC0010 -+#define F367_OFDM_SFEC_DEMODSEL2 0xF2CC0008 -+#define F367_OFDM_SFEC_NOSYNC 0xF2CC0004 -+#define F367_OFDM_SFEC_UNREGULA 0xF2CC0002 -+#define F367_OFDM_SFEC_READY 0xF2CC0001 -+ -+/* SFDLYH */ -+#define R367_OFDM_SFDLYH 0xF2CD -+#define F367_OFDM_SFEC_TSTIMEVALID 0xF2CD0080 -+#define F367_OFDM_SFEC_SPEEDUP 0xF2CD0040 -+#define F367_OFDM_SFEC_STOP 0xF2CD0020 -+#define F367_OFDM_SFEC_REGULATED 0xF2CD0010 -+#define F367_OFDM_SFEC_REALSYMBOFFSET 0xF2CD000F -+ -+/* SFDLYM */ -+#define R367_OFDM_SFDLYM 0xF2CE -+#define F367_OFDM_SFEC_REALSYMBOFFSET_HI 0xF2CE00FF -+ -+/* SFDLYL */ -+#define R367_OFDM_SFDLYL 0xF2CF -+#define F367_OFDM_SFEC_REALSYMBOFFSET_LO 0xF2CF00FF -+ -+/* SFDLYSETH */ -+#define R367_OFDM_SFDLYSETH 0xF2D0 -+#define F367_OFDM_SFEC_OFFSET 0xF2D000E0 -+#define F367_OFDM_SFECDLYSETH_4 0xF2D00010 -+#define F367_OFDM_RST_SFEC 0xF2D00008 -+#define F367_OFDM_SFECDLYSETH_2 0xF2D00004 -+#define F367_OFDM_SFEC_DISABLE 0xF2D00002 -+#define F367_OFDM_SFEC_UNREGUL 0xF2D00001 -+ -+/* SFDLYSETM */ -+#define R367_OFDM_SFDLYSETM 0xF2D1 -+#define F367_OFDM_SFECDLYSETM_7 0xF2D10080 -+#define F367_OFDM_SFEC_SYMBOFFSET_HI 0xF2D1007F -+ -+/* SFDLYSETL */ -+#define R367_OFDM_SFDLYSETL 0xF2D2 -+#define F367_OFDM_SFEC_SYMBOFFSET_LO 0xF2D200FF -+ -+/* SFOBSCFG */ -+#define R367_OFDM_SFOBSCFG 0xF2D3 -+#define F367_OFDM_SFEC_OBSCFG 0xF2D300FF -+ -+/* SFOBSM */ -+#define R367_OFDM_SFOBSM 0xF2D4 -+#define F367_OFDM_SFEC_OBSDATA_HI 0xF2D400FF -+ -+/* SFOBSL */ -+#define R367_OFDM_SFOBSL 0xF2D5 -+#define F367_OFDM_SFEC_OBSDATA_LO 0xF2D500FF -+ -+/* SFECINFO */ -+#define R367_OFDM_SFECINFO 0xF2D6 -+#define F367_OFDM_SFECINFO_7 0xF2D60080 -+#define F367_OFDM_SFEC_SYNCDLSB 0xF2D60070 -+#define F367_OFDM_SFCE_S1CPHASE 0xF2D6000F -+ -+/* SFERRCTRL */ -+#define R367_OFDM_SFERRCTRL 0xF2D8 -+#define F367_OFDM_SFEC_ERR_SOURCE 0xF2D800F0 -+#define F367_OFDM_SFERRCTRL_3 0xF2D80008 -+#define F367_OFDM_SFEC_NUM_EVENT 0xF2D80007 -+ -+/* SFERRCNTH */ -+#define R367_OFDM_SFERRCNTH 0xF2D9 -+#define F367_OFDM_SFERRC_OLDVALUE 0xF2D90080 -+#define F367_OFDM_SFEC_ERR_CNT 0xF2D9007F -+ -+/* SFERRCNTM */ -+#define R367_OFDM_SFERRCNTM 0xF2DA -+#define F367_OFDM_SFEC_ERR_CNT_HI 0xF2DA00FF -+ -+/* SFERRCNTL */ -+#define R367_OFDM_SFERRCNTL 0xF2DB -+#define F367_OFDM_SFEC_ERR_CNT_LO 0xF2DB00FF -+ -+/* SYMBRATEM */ -+#define R367_OFDM_SYMBRATEM 0xF2E0 -+#define F367_OFDM_DEFGEN_SYMBRATE_HI 0xF2E000FF -+ -+/* SYMBRATEL */ -+#define R367_OFDM_SYMBRATEL 0xF2E1 -+#define F367_OFDM_DEFGEN_SYMBRATE_LO 0xF2E100FF -+ -+/* SYMBSTATUS */ -+#define R367_OFDM_SYMBSTATUS 0xF2E2 -+#define F367_OFDM_SYMBDLINE2_OFF 0xF2E20080 -+#define F367_OFDM_SDDL_REINIT1 0xF2E20040 -+#define F367_OFDM_SDD_REINIT1 0xF2E20020 -+#define F367_OFDM_TOKENID_ERROR 0xF2E20010 -+#define F367_OFDM_SYMBRATE_OVERFLOW 0xF2E20008 -+#define F367_OFDM_SYMBRATE_UNDERFLOW 0xF2E20004 -+#define F367_OFDM_TOKENID_RSTEVENT 0xF2E20002 -+#define F367_OFDM_TOKENID_RESET1 0xF2E20001 -+ -+/* SYMBCFG */ -+#define R367_OFDM_SYMBCFG 0xF2E3 -+#define F367_OFDM_SYMBCFG_7 0xF2E30080 -+#define F367_OFDM_SYMBCFG_6 0xF2E30040 -+#define F367_OFDM_SYMBCFG_5 0xF2E30020 -+#define F367_OFDM_SYMBCFG_4 0xF2E30010 -+#define F367_OFDM_SYMRATE_FSPEED 0xF2E3000C -+#define F367_OFDM_SYMRATE_SSPEED 0xF2E30003 -+ -+/* SYMBFIFOM */ -+#define R367_OFDM_SYMBFIFOM 0xF2E4 -+#define F367_OFDM_SYMBFIFOM_7 0xF2E40080 -+#define F367_OFDM_SYMBFIFOM_6 0xF2E40040 -+#define F367_OFDM_DEFGEN_SYMFIFO_HI 0xF2E4003F -+ -+/* SYMBFIFOL */ -+#define R367_OFDM_SYMBFIFOL 0xF2E5 -+#define F367_OFDM_DEFGEN_SYMFIFO_LO 0xF2E500FF -+ -+/* SYMBOFFSM */ -+#define R367_OFDM_SYMBOFFSM 0xF2E6 -+#define F367_OFDM_TOKENID_RESET2 0xF2E60080 -+#define F367_OFDM_SDDL_REINIT2 0xF2E60040 -+#define F367_OFDM_SDD_REINIT2 0xF2E60020 -+#define F367_OFDM_SYMBOFFSM_4 0xF2E60010 -+#define F367_OFDM_SYMBOFFSM_3 0xF2E60008 -+#define F367_OFDM_DEFGEN_SYMBOFFSET_HI 0xF2E60007 -+ -+/* SYMBOFFSL */ -+#define R367_OFDM_SYMBOFFSL 0xF2E7 -+#define F367_OFDM_DEFGEN_SYMBOFFSET_LO 0xF2E700FF -+ -+/* DEBUG_LT4 */ -+#define R367_DEBUG_LT4 0xF400 -+#define F367_F_DEBUG_LT4 0xF40000FF -+ -+/* DEBUG_LT5 */ -+#define R367_DEBUG_LT5 0xF401 -+#define F367_F_DEBUG_LT5 0xF40100FF -+ -+/* DEBUG_LT6 */ -+#define R367_DEBUG_LT6 0xF402 -+#define F367_F_DEBUG_LT6 0xF40200FF -+ -+/* DEBUG_LT7 */ -+#define R367_DEBUG_LT7 0xF403 -+#define F367_F_DEBUG_LT7 0xF40300FF -+ -+/* DEBUG_LT8 */ -+#define R367_DEBUG_LT8 0xF404 -+#define F367_F_DEBUG_LT8 0xF40400FF -+ -+/* DEBUG_LT9 */ -+#define R367_DEBUG_LT9 0xF405 -+#define F367_F_DEBUG_LT9 0xF40500FF -+ -+/* CTRL_1 */ -+#define R367_QAM_CTRL_1 0xF402 -+#define F367_QAM_SOFT_RST 0xF4020080 -+#define F367_QAM_EQU_RST 0xF4020008 -+#define F367_QAM_CRL_RST 0xF4020004 -+#define F367_QAM_TRL_RST 0xF4020002 -+#define F367_QAM_AGC_RST 0xF4020001 -+ -+/* CTRL_2 */ -+#define R367_QAM_CTRL_2 0xF403 -+#define F367_QAM_DEINT_RST 0xF4030008 -+#define F367_QAM_RS_RST 0xF4030004 -+ -+/* IT_STATUS1 */ -+#define R367_QAM_IT_STATUS1 0xF408 -+#define F367_QAM_SWEEP_OUT 0xF4080080 -+#define F367_QAM_FSM_CRL 0xF4080040 -+#define F367_QAM_CRL_LOCK 0xF4080020 -+#define F367_QAM_MFSM 0xF4080010 -+#define F367_QAM_TRL_LOCK 0xF4080008 -+#define F367_QAM_TRL_AGC_LIMIT 0xF4080004 -+#define F367_QAM_ADJ_AGC_LOCK 0xF4080002 -+#define F367_QAM_AGC_QAM_LOCK 0xF4080001 -+ -+/* IT_STATUS2 */ -+#define R367_QAM_IT_STATUS2 0xF409 -+#define F367_QAM_TSMF_CNT 0xF4090080 -+#define F367_QAM_TSMF_EOF 0xF4090040 -+#define F367_QAM_TSMF_RDY 0xF4090020 -+#define F367_QAM_FEC_NOCORR 0xF4090010 -+#define F367_QAM_SYNCSTATE 0xF4090008 -+#define F367_QAM_DEINT_LOCK 0xF4090004 -+#define F367_QAM_FADDING_FRZ 0xF4090002 -+#define F367_QAM_TAPMON_ALARM 0xF4090001 -+ -+/* IT_EN1 */ -+#define R367_QAM_IT_EN1 0xF40A -+#define F367_QAM_SWEEP_OUTE 0xF40A0080 -+#define F367_QAM_FSM_CRLE 0xF40A0040 -+#define F367_QAM_CRL_LOCKE 0xF40A0020 -+#define F367_QAM_MFSME 0xF40A0010 -+#define F367_QAM_TRL_LOCKE 0xF40A0008 -+#define F367_QAM_TRL_AGC_LIMITE 0xF40A0004 -+#define F367_QAM_ADJ_AGC_LOCKE 0xF40A0002 -+#define F367_QAM_AGC_LOCKE 0xF40A0001 -+ -+/* IT_EN2 */ -+#define R367_QAM_IT_EN2 0xF40B -+#define F367_QAM_TSMF_CNTE 0xF40B0080 -+#define F367_QAM_TSMF_EOFE 0xF40B0040 -+#define F367_QAM_TSMF_RDYE 0xF40B0020 -+#define F367_QAM_FEC_NOCORRE 0xF40B0010 -+#define F367_QAM_SYNCSTATEE 0xF40B0008 -+#define F367_QAM_DEINT_LOCKE 0xF40B0004 -+#define F367_QAM_FADDING_FRZE 0xF40B0002 -+#define F367_QAM_TAPMON_ALARME 0xF40B0001 -+ -+/* CTRL_STATUS */ -+#define R367_QAM_CTRL_STATUS 0xF40C -+#define F367_QAM_QAMFEC_LOCK 0xF40C0004 -+#define F367_QAM_TSMF_LOCK 0xF40C0002 -+#define F367_QAM_TSMF_ERROR 0xF40C0001 -+ -+/* TEST_CTL */ -+#define R367_QAM_TEST_CTL 0xF40F -+#define F367_QAM_TST_BLK_SEL 0xF40F0060 -+#define F367_QAM_TST_BUS_SEL 0xF40F001F -+ -+/* AGC_CTL */ -+#define R367_QAM_AGC_CTL 0xF410 -+#define F367_QAM_AGC_LCK_TH 0xF41000F0 -+#define F367_QAM_AGC_ACCUMRSTSEL 0xF4100007 -+ -+/* AGC_IF_CFG */ -+#define R367_QAM_AGC_IF_CFG 0xF411 -+#define F367_QAM_AGC_IF_BWSEL 0xF41100F0 -+#define F367_QAM_AGC_IF_FREEZE 0xF4110002 -+ -+/* AGC_RF_CFG */ -+#define R367_QAM_AGC_RF_CFG 0xF412 -+#define F367_QAM_AGC_RF_BWSEL 0xF4120070 -+#define F367_QAM_AGC_RF_FREEZE 0xF4120002 -+ -+/* AGC_PWM_CFG */ -+#define R367_QAM_AGC_PWM_CFG 0xF413 -+#define F367_QAM_AGC_RF_PWM_TST 0xF4130080 -+#define F367_QAM_AGC_RF_PWM_INV 0xF4130040 -+#define F367_QAM_AGC_IF_PWM_TST 0xF4130008 -+#define F367_QAM_AGC_IF_PWM_INV 0xF4130004 -+#define F367_QAM_AGC_PWM_CLKDIV 0xF4130003 -+ -+/* AGC_PWR_REF_L */ -+#define R367_QAM_AGC_PWR_REF_L 0xF414 -+#define F367_QAM_AGC_PWRREF_LO 0xF41400FF -+ -+/* AGC_PWR_REF_H */ -+#define R367_QAM_AGC_PWR_REF_H 0xF415 -+#define F367_QAM_AGC_PWRREF_HI 0xF4150003 -+ -+/* AGC_RF_TH_L */ -+#define R367_QAM_AGC_RF_TH_L 0xF416 -+#define F367_QAM_AGC_RF_TH_LO 0xF41600FF -+ -+/* AGC_RF_TH_H */ -+#define R367_QAM_AGC_RF_TH_H 0xF417 -+#define F367_QAM_AGC_RF_TH_HI 0xF417000F -+ -+/* AGC_IF_LTH_L */ -+#define R367_QAM_AGC_IF_LTH_L 0xF418 -+#define F367_QAM_AGC_IF_THLO_LO 0xF41800FF -+ -+/* AGC_IF_LTH_H */ -+#define R367_QAM_AGC_IF_LTH_H 0xF419 -+#define F367_QAM_AGC_IF_THLO_HI 0xF419000F -+ -+/* AGC_IF_HTH_L */ -+#define R367_QAM_AGC_IF_HTH_L 0xF41A -+#define F367_QAM_AGC_IF_THHI_LO 0xF41A00FF -+ -+/* AGC_IF_HTH_H */ -+#define R367_QAM_AGC_IF_HTH_H 0xF41B -+#define F367_QAM_AGC_IF_THHI_HI 0xF41B000F -+ -+/* AGC_PWR_RD_L */ -+#define R367_QAM_AGC_PWR_RD_L 0xF41C -+#define F367_QAM_AGC_PWR_WORD_LO 0xF41C00FF -+ -+/* AGC_PWR_RD_M */ -+#define R367_QAM_AGC_PWR_RD_M 0xF41D -+#define F367_QAM_AGC_PWR_WORD_ME 0xF41D00FF -+ -+/* AGC_PWR_RD_H */ -+#define R367_QAM_AGC_PWR_RD_H 0xF41E -+#define F367_QAM_AGC_PWR_WORD_HI 0xF41E0003 -+ -+/* AGC_PWM_IFCMD_L */ -+#define R367_QAM_AGC_PWM_IFCMD_L 0xF420 -+#define F367_QAM_AGC_IF_PWMCMD_LO 0xF42000FF -+ -+/* AGC_PWM_IFCMD_H */ -+#define R367_QAM_AGC_PWM_IFCMD_H 0xF421 -+#define F367_QAM_AGC_IF_PWMCMD_HI 0xF421000F -+ -+/* AGC_PWM_RFCMD_L */ -+#define R367_QAM_AGC_PWM_RFCMD_L 0xF422 -+#define F367_QAM_AGC_RF_PWMCMD_LO 0xF42200FF -+ -+/* AGC_PWM_RFCMD_H */ -+#define R367_QAM_AGC_PWM_RFCMD_H 0xF423 -+#define F367_QAM_AGC_RF_PWMCMD_HI 0xF423000F -+ -+/* IQDEM_CFG */ -+#define R367_QAM_IQDEM_CFG 0xF424 -+#define F367_QAM_IQDEM_CLK_SEL 0xF4240004 -+#define F367_QAM_IQDEM_INVIQ 0xF4240002 -+#define F367_QAM_IQDEM_A2DTYPE 0xF4240001 -+ -+/* MIX_NCO_LL */ -+#define R367_QAM_MIX_NCO_LL 0xF425 -+#define F367_QAM_MIX_NCO_INC_LL 0xF42500FF -+ -+/* MIX_NCO_HL */ -+#define R367_QAM_MIX_NCO_HL 0xF426 -+#define F367_QAM_MIX_NCO_INC_HL 0xF42600FF -+ -+/* MIX_NCO_HH */ -+#define R367_QAM_MIX_NCO_HH 0xF427 -+#define F367_QAM_MIX_NCO_INVCNST 0xF4270080 -+#define F367_QAM_MIX_NCO_INC_HH 0xF427007F -+ -+/* SRC_NCO_LL */ -+#define R367_QAM_SRC_NCO_LL 0xF428 -+#define F367_QAM_SRC_NCO_INC_LL 0xF42800FF -+ -+/* SRC_NCO_LH */ -+#define R367_QAM_SRC_NCO_LH 0xF429 -+#define F367_QAM_SRC_NCO_INC_LH 0xF42900FF -+ -+/* SRC_NCO_HL */ -+#define R367_QAM_SRC_NCO_HL 0xF42A -+#define F367_QAM_SRC_NCO_INC_HL 0xF42A00FF -+ -+/* SRC_NCO_HH */ -+#define R367_QAM_SRC_NCO_HH 0xF42B -+#define F367_QAM_SRC_NCO_INC_HH 0xF42B007F -+ -+/* IQDEM_GAIN_SRC_L */ -+#define R367_QAM_IQDEM_GAIN_SRC_L 0xF42C -+#define F367_QAM_GAIN_SRC_LO 0xF42C00FF -+ -+/* IQDEM_GAIN_SRC_H */ -+#define R367_QAM_IQDEM_GAIN_SRC_H 0xF42D -+#define F367_QAM_GAIN_SRC_HI 0xF42D0003 -+ -+/* IQDEM_DCRM_CFG_LL */ -+#define R367_QAM_IQDEM_DCRM_CFG_LL 0xF430 -+#define F367_QAM_DCRM0_DCIN_L 0xF43000FF -+ -+/* IQDEM_DCRM_CFG_LH */ -+#define R367_QAM_IQDEM_DCRM_CFG_LH 0xF431 -+#define F367_QAM_DCRM1_I_DCIN_L 0xF43100FC -+#define F367_QAM_DCRM0_DCIN_H 0xF4310003 -+ -+/* IQDEM_DCRM_CFG_HL */ -+#define R367_QAM_IQDEM_DCRM_CFG_HL 0xF432 -+#define F367_QAM_DCRM1_Q_DCIN_L 0xF43200F0 -+#define F367_QAM_DCRM1_I_DCIN_H 0xF432000F -+ -+/* IQDEM_DCRM_CFG_HH */ -+#define R367_QAM_IQDEM_DCRM_CFG_HH 0xF433 -+#define F367_QAM_DCRM1_FRZ 0xF4330080 -+#define F367_QAM_DCRM0_FRZ 0xF4330040 -+#define F367_QAM_DCRM1_Q_DCIN_H 0xF433003F -+ -+/* IQDEM_ADJ_COEFF0 */ -+#define R367_QAM_IQDEM_ADJ_COEFF0 0xF434 -+#define F367_QAM_ADJIIR_COEFF10_L 0xF43400FF -+ -+/* IQDEM_ADJ_COEFF1 */ -+#define R367_QAM_IQDEM_ADJ_COEFF1 0xF435 -+#define F367_QAM_ADJIIR_COEFF11_L 0xF43500FC -+#define F367_QAM_ADJIIR_COEFF10_H 0xF4350003 -+ -+/* IQDEM_ADJ_COEFF2 */ -+#define R367_QAM_IQDEM_ADJ_COEFF2 0xF436 -+#define F367_QAM_ADJIIR_COEFF12_L 0xF43600F0 -+#define F367_QAM_ADJIIR_COEFF11_H 0xF436000F -+ -+/* IQDEM_ADJ_COEFF3 */ -+#define R367_QAM_IQDEM_ADJ_COEFF3 0xF437 -+#define F367_QAM_ADJIIR_COEFF20_L 0xF43700C0 -+#define F367_QAM_ADJIIR_COEFF12_H 0xF437003F -+ -+/* IQDEM_ADJ_COEFF4 */ -+#define R367_QAM_IQDEM_ADJ_COEFF4 0xF438 -+#define F367_QAM_ADJIIR_COEFF20_H 0xF43800FF -+ -+/* IQDEM_ADJ_COEFF5 */ -+#define R367_QAM_IQDEM_ADJ_COEFF5 0xF439 -+#define F367_QAM_ADJIIR_COEFF21_L 0xF43900FF -+ -+/* IQDEM_ADJ_COEFF6 */ -+#define R367_QAM_IQDEM_ADJ_COEFF6 0xF43A -+#define F367_QAM_ADJIIR_COEFF22_L 0xF43A00FC -+#define F367_QAM_ADJIIR_COEFF21_H 0xF43A0003 -+ -+/* IQDEM_ADJ_COEFF7 */ -+#define R367_QAM_IQDEM_ADJ_COEFF7 0xF43B -+#define F367_QAM_ADJIIR_COEFF22_H 0xF43B000F -+ -+/* IQDEM_ADJ_EN */ -+#define R367_QAM_IQDEM_ADJ_EN 0xF43C -+#define F367_QAM_ALLPASSFILT_EN 0xF43C0008 -+#define F367_QAM_ADJ_AGC_EN 0xF43C0004 -+#define F367_QAM_ADJ_COEFF_FRZ 0xF43C0002 -+#define F367_QAM_ADJ_EN 0xF43C0001 -+ -+/* IQDEM_ADJ_AGC_REF */ -+#define R367_QAM_IQDEM_ADJ_AGC_REF 0xF43D -+#define F367_QAM_ADJ_AGC_REF 0xF43D00FF -+ -+/* ALLPASSFILT1 */ -+#define R367_QAM_ALLPASSFILT1 0xF440 -+#define F367_QAM_ALLPASSFILT_COEFF1_LO 0xF44000FF -+ -+/* ALLPASSFILT2 */ -+#define R367_QAM_ALLPASSFILT2 0xF441 -+#define F367_QAM_ALLPASSFILT_COEFF1_ME 0xF44100FF -+ -+/* ALLPASSFILT3 */ -+#define R367_QAM_ALLPASSFILT3 0xF442 -+#define F367_QAM_ALLPASSFILT_COEFF2_LO 0xF44200C0 -+#define F367_QAM_ALLPASSFILT_COEFF1_HI 0xF442003F -+ -+/* ALLPASSFILT4 */ -+#define R367_QAM_ALLPASSFILT4 0xF443 -+#define F367_QAM_ALLPASSFILT_COEFF2_MEL 0xF44300FF -+ -+/* ALLPASSFILT5 */ -+#define R367_QAM_ALLPASSFILT5 0xF444 -+#define F367_QAM_ALLPASSFILT_COEFF2_MEH 0xF44400FF -+ -+/* ALLPASSFILT6 */ -+#define R367_QAM_ALLPASSFILT6 0xF445 -+#define F367_QAM_ALLPASSFILT_COEFF3_LO 0xF44500F0 -+#define F367_QAM_ALLPASSFILT_COEFF2_HI 0xF445000F -+ -+/* ALLPASSFILT7 */ -+#define R367_QAM_ALLPASSFILT7 0xF446 -+#define F367_QAM_ALLPASSFILT_COEFF3_MEL 0xF44600FF -+ -+/* ALLPASSFILT8 */ -+#define R367_QAM_ALLPASSFILT8 0xF447 -+#define F367_QAM_ALLPASSFILT_COEFF3_MEH 0xF44700FF -+ -+/* ALLPASSFILT9 */ -+#define R367_QAM_ALLPASSFILT9 0xF448 -+#define F367_QAM_ALLPASSFILT_COEFF4_LO 0xF44800FC -+#define F367_QAM_ALLPASSFILT_COEFF3_HI 0xF4480003 -+ -+/* ALLPASSFILT10 */ -+#define R367_QAM_ALLPASSFILT10 0xF449 -+#define F367_QAM_ALLPASSFILT_COEFF4_ME 0xF44900FF -+ -+/* ALLPASSFILT11 */ -+#define R367_QAM_ALLPASSFILT11 0xF44A -+#define F367_QAM_ALLPASSFILT_COEFF4_HI 0xF44A00FF -+ -+/* TRL_AGC_CFG */ -+#define R367_QAM_TRL_AGC_CFG 0xF450 -+#define F367_QAM_TRL_AGC_FREEZE 0xF4500080 -+#define F367_QAM_TRL_AGC_REF 0xF450007F -+ -+/* TRL_LPF_CFG */ -+#define R367_QAM_TRL_LPF_CFG 0xF454 -+#define F367_QAM_NYQPOINT_INV 0xF4540040 -+#define F367_QAM_TRL_SHIFT 0xF4540030 -+#define F367_QAM_NYQ_COEFF_SEL 0xF454000C -+#define F367_QAM_TRL_LPF_FREEZE 0xF4540002 -+#define F367_QAM_TRL_LPF_CRT 0xF4540001 -+ -+/* TRL_LPF_ACQ_GAIN */ -+#define R367_QAM_TRL_LPF_ACQ_GAIN 0xF455 -+#define F367_QAM_TRL_GDIR_ACQ 0xF4550070 -+#define F367_QAM_TRL_GINT_ACQ 0xF4550007 -+ -+/* TRL_LPF_TRK_GAIN */ -+#define R367_QAM_TRL_LPF_TRK_GAIN 0xF456 -+#define F367_QAM_TRL_GDIR_TRK 0xF4560070 -+#define F367_QAM_TRL_GINT_TRK 0xF4560007 -+ -+/* TRL_LPF_OUT_GAIN */ -+#define R367_QAM_TRL_LPF_OUT_GAIN 0xF457 -+#define F367_QAM_TRL_GAIN_OUT 0xF4570007 -+ -+/* TRL_LOCKDET_LTH */ -+#define R367_QAM_TRL_LOCKDET_LTH 0xF458 -+#define F367_QAM_TRL_LCK_THLO 0xF4580007 -+ -+/* TRL_LOCKDET_HTH */ -+#define R367_QAM_TRL_LOCKDET_HTH 0xF459 -+#define F367_QAM_TRL_LCK_THHI 0xF45900FF -+ -+/* TRL_LOCKDET_TRGVAL */ -+#define R367_QAM_TRL_LOCKDET_TRGVAL 0xF45A -+#define F367_QAM_TRL_LCK_TRG 0xF45A00FF -+ -+/* IQ_QAM */ -+#define R367_QAM_IQ_QAM 0xF45C -+#define F367_QAM_IQ_INPUT 0xF45C0008 -+#define F367_QAM_DETECT_MODE 0xF45C0007 -+ -+/* FSM_STATE */ -+#define R367_QAM_FSM_STATE 0xF460 -+#define F367_QAM_CRL_DFE 0xF4600080 -+#define F367_QAM_DFE_START 0xF4600040 -+#define F367_QAM_CTRLG_START 0xF4600030 -+#define F367_QAM_FSM_FORCESTATE 0xF460000F -+ -+/* FSM_CTL */ -+#define R367_QAM_FSM_CTL 0xF461 -+#define F367_QAM_FEC2_EN 0xF4610040 -+#define F367_QAM_SIT_EN 0xF4610020 -+#define F367_QAM_TRL_AHEAD 0xF4610010 -+#define F367_QAM_TRL2_EN 0xF4610008 -+#define F367_QAM_FSM_EQA1_EN 0xF4610004 -+#define F367_QAM_FSM_BKP_DIS 0xF4610002 -+#define F367_QAM_FSM_FORCE_EN 0xF4610001 -+ -+/* FSM_STS */ -+#define R367_QAM_FSM_STS 0xF462 -+#define F367_QAM_FSM_STATUS 0xF462000F -+ -+/* FSM_SNR0_HTH */ -+#define R367_QAM_FSM_SNR0_HTH 0xF463 -+#define F367_QAM_SNR0_HTH 0xF46300FF -+ -+/* FSM_SNR1_HTH */ -+#define R367_QAM_FSM_SNR1_HTH 0xF464 -+#define F367_QAM_SNR1_HTH 0xF46400FF -+ -+/* FSM_SNR2_HTH */ -+#define R367_QAM_FSM_SNR2_HTH 0xF465 -+#define F367_QAM_SNR2_HTH 0xF46500FF -+ -+/* FSM_SNR0_LTH */ -+#define R367_QAM_FSM_SNR0_LTH 0xF466 -+#define F367_QAM_SNR0_LTH 0xF46600FF -+ -+/* FSM_SNR1_LTH */ -+#define R367_QAM_FSM_SNR1_LTH 0xF467 -+#define F367_QAM_SNR1_LTH 0xF46700FF -+ -+/* FSM_EQA1_HTH */ -+#define R367_QAM_FSM_EQA1_HTH 0xF468 -+#define F367_QAM_SNR3_HTH_LO 0xF46800F0 -+#define F367_QAM_EQA1_HTH 0xF468000F -+ -+/* FSM_TEMPO */ -+#define R367_QAM_FSM_TEMPO 0xF469 -+#define F367_QAM_SIT 0xF46900C0 -+#define F367_QAM_WST 0xF4690038 -+#define F367_QAM_ELT 0xF4690006 -+#define F367_QAM_SNR3_HTH_HI 0xF4690001 -+ -+/* FSM_CONFIG */ -+#define R367_QAM_FSM_CONFIG 0xF46A -+#define F367_QAM_FEC2_DFEOFF 0xF46A0004 -+#define F367_QAM_PRIT_STATE 0xF46A0002 -+#define F367_QAM_MODMAP_STATE 0xF46A0001 -+ -+/* EQU_I_TESTTAP_L */ -+#define R367_QAM_EQU_I_TESTTAP_L 0xF474 -+#define F367_QAM_I_TEST_TAP_L 0xF47400FF -+ -+/* EQU_I_TESTTAP_M */ -+#define R367_QAM_EQU_I_TESTTAP_M 0xF475 -+#define F367_QAM_I_TEST_TAP_M 0xF47500FF -+ -+/* EQU_I_TESTTAP_H */ -+#define R367_QAM_EQU_I_TESTTAP_H 0xF476 -+#define F367_QAM_I_TEST_TAP_H 0xF476001F -+ -+/* EQU_TESTAP_CFG */ -+#define R367_QAM_EQU_TESTAP_CFG 0xF477 -+#define F367_QAM_TEST_FFE_DFE_SEL 0xF4770040 -+#define F367_QAM_TEST_TAP_SELECT 0xF477003F -+ -+/* EQU_Q_TESTTAP_L */ -+#define R367_QAM_EQU_Q_TESTTAP_L 0xF478 -+#define F367_QAM_Q_TEST_TAP_L 0xF47800FF -+ -+/* EQU_Q_TESTTAP_M */ -+#define R367_QAM_EQU_Q_TESTTAP_M 0xF479 -+#define F367_QAM_Q_TEST_TAP_M 0xF47900FF -+ -+/* EQU_Q_TESTTAP_H */ -+#define R367_QAM_EQU_Q_TESTTAP_H 0xF47A -+#define F367_QAM_Q_TEST_TAP_H 0xF47A001F -+ -+/* EQU_TAP_CTRL */ -+#define R367_QAM_EQU_TAP_CTRL 0xF47B -+#define F367_QAM_MTAP_FRZ 0xF47B0010 -+#define F367_QAM_PRE_FREEZE 0xF47B0008 -+#define F367_QAM_DFE_TAPMON_EN 0xF47B0004 -+#define F367_QAM_FFE_TAPMON_EN 0xF47B0002 -+#define F367_QAM_MTAP_ONLY 0xF47B0001 -+ -+/* EQU_CTR_CRL_CONTROL_L */ -+#define R367_QAM_EQU_CTR_CRL_CONTROL_L 0xF47C -+#define F367_QAM_EQU_CTR_CRL_CONTROL_LO 0xF47C00FF -+ -+/* EQU_CTR_CRL_CONTROL_H */ -+#define R367_QAM_EQU_CTR_CRL_CONTROL_H 0xF47D -+#define F367_QAM_EQU_CTR_CRL_CONTROL_HI 0xF47D00FF -+ -+/* EQU_CTR_HIPOW_L */ -+#define R367_QAM_EQU_CTR_HIPOW_L 0xF47E -+#define F367_QAM_CTR_HIPOW_L 0xF47E00FF -+ -+/* EQU_CTR_HIPOW_H */ -+#define R367_QAM_EQU_CTR_HIPOW_H 0xF47F -+#define F367_QAM_CTR_HIPOW_H 0xF47F00FF -+ -+/* EQU_I_EQU_LO */ -+#define R367_QAM_EQU_I_EQU_LO 0xF480 -+#define F367_QAM_EQU_I_EQU_L 0xF48000FF -+ -+/* EQU_I_EQU_HI */ -+#define R367_QAM_EQU_I_EQU_HI 0xF481 -+#define F367_QAM_EQU_I_EQU_H 0xF4810003 -+ -+/* EQU_Q_EQU_LO */ -+#define R367_QAM_EQU_Q_EQU_LO 0xF482 -+#define F367_QAM_EQU_Q_EQU_L 0xF48200FF -+ -+/* EQU_Q_EQU_HI */ -+#define R367_QAM_EQU_Q_EQU_HI 0xF483 -+#define F367_QAM_EQU_Q_EQU_H 0xF4830003 -+ -+/* EQU_MAPPER */ -+#define R367_QAM_EQU_MAPPER 0xF484 -+#define F367_QAM_QUAD_AUTO 0xF4840080 -+#define F367_QAM_QUAD_INV 0xF4840040 -+#define F367_QAM_QAM_MODE 0xF4840007 -+ -+/* EQU_SWEEP_RATE */ -+#define R367_QAM_EQU_SWEEP_RATE 0xF485 -+#define F367_QAM_SNR_PER 0xF48500C0 -+#define F367_QAM_SWEEP_RATE 0xF485003F -+ -+/* EQU_SNR_LO */ -+#define R367_QAM_EQU_SNR_LO 0xF486 -+#define F367_QAM_SNR_LO 0xF48600FF -+ -+/* EQU_SNR_HI */ -+#define R367_QAM_EQU_SNR_HI 0xF487 -+#define F367_QAM_SNR_HI 0xF48700FF -+ -+/* EQU_GAMMA_LO */ -+#define R367_QAM_EQU_GAMMA_LO 0xF488 -+#define F367_QAM_GAMMA_LO 0xF48800FF -+ -+/* EQU_GAMMA_HI */ -+#define R367_QAM_EQU_GAMMA_HI 0xF489 -+#define F367_QAM_GAMMA_ME 0xF48900FF -+ -+/* EQU_ERR_GAIN */ -+#define R367_QAM_EQU_ERR_GAIN 0xF48A -+#define F367_QAM_EQA1MU 0xF48A0070 -+#define F367_QAM_CRL2MU 0xF48A000E -+#define F367_QAM_GAMMA_HI 0xF48A0001 -+ -+/* EQU_RADIUS */ -+#define R367_QAM_EQU_RADIUS 0xF48B -+#define F367_QAM_RADIUS 0xF48B00FF -+ -+/* EQU_FFE_MAINTAP */ -+#define R367_QAM_EQU_FFE_MAINTAP 0xF48C -+#define F367_QAM_FFE_MAINTAP_INIT 0xF48C00FF -+ -+/* EQU_FFE_LEAKAGE */ -+#define R367_QAM_EQU_FFE_LEAKAGE 0xF48E -+#define F367_QAM_LEAK_PER 0xF48E00F0 -+#define F367_QAM_EQU_OUTSEL 0xF48E0002 -+#define F367_QAM_PNT2DFE 0xF48E0001 -+ -+/* EQU_FFE_MAINTAP_POS */ -+#define R367_QAM_EQU_FFE_MAINTAP_POS 0xF48F -+#define F367_QAM_FFE_LEAK_EN 0xF48F0080 -+#define F367_QAM_DFE_LEAK_EN 0xF48F0040 -+#define F367_QAM_FFE_MAINTAP_POS 0xF48F003F -+ -+/* EQU_GAIN_WIDE */ -+#define R367_QAM_EQU_GAIN_WIDE 0xF490 -+#define F367_QAM_DFE_GAIN_WIDE 0xF49000F0 -+#define F367_QAM_FFE_GAIN_WIDE 0xF490000F -+ -+/* EQU_GAIN_NARROW */ -+#define R367_QAM_EQU_GAIN_NARROW 0xF491 -+#define F367_QAM_DFE_GAIN_NARROW 0xF49100F0 -+#define F367_QAM_FFE_GAIN_NARROW 0xF491000F -+ -+/* EQU_CTR_LPF_GAIN */ -+#define R367_QAM_EQU_CTR_LPF_GAIN 0xF492 -+#define F367_QAM_CTR_GTO 0xF4920080 -+#define F367_QAM_CTR_GDIR 0xF4920070 -+#define F367_QAM_SWEEP_EN 0xF4920008 -+#define F367_QAM_CTR_GINT 0xF4920007 -+ -+/* EQU_CRL_LPF_GAIN */ -+#define R367_QAM_EQU_CRL_LPF_GAIN 0xF493 -+#define F367_QAM_CRL_GTO 0xF4930080 -+#define F367_QAM_CRL_GDIR 0xF4930070 -+#define F367_QAM_SWEEP_DIR 0xF4930008 -+#define F367_QAM_CRL_GINT 0xF4930007 -+ -+/* EQU_GLOBAL_GAIN */ -+#define R367_QAM_EQU_GLOBAL_GAIN 0xF494 -+#define F367_QAM_CRL_GAIN 0xF49400F8 -+#define F367_QAM_CTR_INC_GAIN 0xF4940004 -+#define F367_QAM_CTR_FRAC 0xF4940003 -+ -+/* EQU_CRL_LD_SEN */ -+#define R367_QAM_EQU_CRL_LD_SEN 0xF495 -+#define F367_QAM_CTR_BADPOINT_EN 0xF4950080 -+#define F367_QAM_CTR_GAIN 0xF4950070 -+#define F367_QAM_LIMANEN 0xF4950008 -+#define F367_QAM_CRL_LD_SEN 0xF4950007 -+ -+/* EQU_CRL_LD_VAL */ -+#define R367_QAM_EQU_CRL_LD_VAL 0xF496 -+#define F367_QAM_CRL_BISTH_LIMIT 0xF4960080 -+#define F367_QAM_CARE_EN 0xF4960040 -+#define F367_QAM_CRL_LD_PER 0xF4960030 -+#define F367_QAM_CRL_LD_WST 0xF496000C -+#define F367_QAM_CRL_LD_TFS 0xF4960003 -+ -+/* EQU_CRL_TFR */ -+#define R367_QAM_EQU_CRL_TFR 0xF497 -+#define F367_QAM_CRL_LD_TFR 0xF49700FF -+ -+/* EQU_CRL_BISTH_LO */ -+#define R367_QAM_EQU_CRL_BISTH_LO 0xF498 -+#define F367_QAM_CRL_BISTH_LO 0xF49800FF -+ -+/* EQU_CRL_BISTH_HI */ -+#define R367_QAM_EQU_CRL_BISTH_HI 0xF499 -+#define F367_QAM_CRL_BISTH_HI 0xF49900FF -+ -+/* EQU_SWEEP_RANGE_LO */ -+#define R367_QAM_EQU_SWEEP_RANGE_LO 0xF49A -+#define F367_QAM_SWEEP_RANGE_LO 0xF49A00FF -+ -+/* EQU_SWEEP_RANGE_HI */ -+#define R367_QAM_EQU_SWEEP_RANGE_HI 0xF49B -+#define F367_QAM_SWEEP_RANGE_HI 0xF49B00FF -+ -+/* EQU_CRL_LIMITER */ -+#define R367_QAM_EQU_CRL_LIMITER 0xF49C -+#define F367_QAM_BISECTOR_EN 0xF49C0080 -+#define F367_QAM_PHEST128_EN 0xF49C0040 -+#define F367_QAM_CRL_LIM 0xF49C003F -+ -+/* EQU_MODULUS_MAP */ -+#define R367_QAM_EQU_MODULUS_MAP 0xF49D -+#define F367_QAM_PNT_DEPTH 0xF49D00E0 -+#define F367_QAM_MODULUS_CMP 0xF49D001F -+ -+/* EQU_PNT_GAIN */ -+#define R367_QAM_EQU_PNT_GAIN 0xF49E -+#define F367_QAM_PNT_EN 0xF49E0080 -+#define F367_QAM_MODULUSMAP_EN 0xF49E0040 -+#define F367_QAM_PNT_GAIN 0xF49E003F -+ -+/* FEC_AC_CTR_0 */ -+#define R367_QAM_FEC_AC_CTR_0 0xF4A8 -+#define F367_QAM_BE_BYPASS 0xF4A80020 -+#define F367_QAM_REFRESH47 0xF4A80010 -+#define F367_QAM_CT_NBST 0xF4A80008 -+#define F367_QAM_TEI_ENA 0xF4A80004 -+#define F367_QAM_DS_ENA 0xF4A80002 -+#define F367_QAM_TSMF_EN 0xF4A80001 -+ -+/* FEC_AC_CTR_1 */ -+#define R367_QAM_FEC_AC_CTR_1 0xF4A9 -+#define F367_QAM_DEINT_DEPTH 0xF4A900FF -+ -+/* FEC_AC_CTR_2 */ -+#define R367_QAM_FEC_AC_CTR_2 0xF4AA -+#define F367_QAM_DEINT_M 0xF4AA00F8 -+#define F367_QAM_DIS_UNLOCK 0xF4AA0004 -+#define F367_QAM_DESCR_MODE 0xF4AA0003 -+ -+/* FEC_AC_CTR_3 */ -+#define R367_QAM_FEC_AC_CTR_3 0xF4AB -+#define F367_QAM_DI_UNLOCK 0xF4AB0080 -+#define F367_QAM_DI_FREEZE 0xF4AB0040 -+#define F367_QAM_MISMATCH 0xF4AB0030 -+#define F367_QAM_ACQ_MODE 0xF4AB000C -+#define F367_QAM_TRK_MODE 0xF4AB0003 -+ -+/* FEC_STATUS */ -+#define R367_QAM_FEC_STATUS 0xF4AC -+#define F367_QAM_DEINT_SMCNTR 0xF4AC00E0 -+#define F367_QAM_DEINT_SYNCSTATE 0xF4AC0018 -+#define F367_QAM_DEINT_SYNLOST 0xF4AC0004 -+#define F367_QAM_DESCR_SYNCSTATE 0xF4AC0002 -+ -+/* RS_COUNTER_0 */ -+#define R367_QAM_RS_COUNTER_0 0xF4AE -+#define F367_QAM_BK_CT_L 0xF4AE00FF -+ -+/* RS_COUNTER_1 */ -+#define R367_QAM_RS_COUNTER_1 0xF4AF -+#define F367_QAM_BK_CT_H 0xF4AF00FF -+ -+/* RS_COUNTER_2 */ -+#define R367_QAM_RS_COUNTER_2 0xF4B0 -+#define F367_QAM_CORR_CT_L 0xF4B000FF -+ -+/* RS_COUNTER_3 */ -+#define R367_QAM_RS_COUNTER_3 0xF4B1 -+#define F367_QAM_CORR_CT_H 0xF4B100FF -+ -+/* RS_COUNTER_4 */ -+#define R367_QAM_RS_COUNTER_4 0xF4B2 -+#define F367_QAM_UNCORR_CT_L 0xF4B200FF -+ -+/* RS_COUNTER_5 */ -+#define R367_QAM_RS_COUNTER_5 0xF4B3 -+#define F367_QAM_UNCORR_CT_H 0xF4B300FF -+ -+/* BERT_0 */ -+#define R367_QAM_BERT_0 0xF4B4 -+#define F367_QAM_RS_NOCORR 0xF4B40004 -+#define F367_QAM_CT_HOLD 0xF4B40002 -+#define F367_QAM_CT_CLEAR 0xF4B40001 -+ -+/* BERT_1 */ -+#define R367_QAM_BERT_1 0xF4B5 -+#define F367_QAM_BERT_ON 0xF4B50020 -+#define F367_QAM_BERT_ERR_SRC 0xF4B50010 -+#define F367_QAM_BERT_ERR_MODE 0xF4B50008 -+#define F367_QAM_BERT_NBYTE 0xF4B50007 -+ -+/* BERT_2 */ -+#define R367_QAM_BERT_2 0xF4B6 -+#define F367_QAM_BERT_ERRCOUNT_L 0xF4B600FF -+ -+/* BERT_3 */ -+#define R367_QAM_BERT_3 0xF4B7 -+#define F367_QAM_BERT_ERRCOUNT_H 0xF4B700FF -+ -+/* OUTFORMAT_0 */ -+#define R367_QAM_OUTFORMAT_0 0xF4B8 -+#define F367_QAM_CLK_POLARITY 0xF4B80080 -+#define F367_QAM_FEC_TYPE 0xF4B80040 -+#define F367_QAM_SYNC_STRIP 0xF4B80008 -+#define F367_QAM_TS_SWAP 0xF4B80004 -+#define F367_QAM_OUTFORMAT 0xF4B80003 -+ -+/* OUTFORMAT_1 */ -+#define R367_QAM_OUTFORMAT_1 0xF4B9 -+#define F367_QAM_CI_DIVRANGE 0xF4B900FF -+ -+/* SMOOTHER_2 */ -+#define R367_QAM_SMOOTHER_2 0xF4BE -+#define F367_QAM_FIFO_BYPASS 0xF4BE0020 -+ -+/* TSMF_CTRL_0 */ -+#define R367_QAM_TSMF_CTRL_0 0xF4C0 -+#define F367_QAM_TS_NUMBER 0xF4C0001E -+#define F367_QAM_SEL_MODE 0xF4C00001 -+ -+/* TSMF_CTRL_1 */ -+#define R367_QAM_TSMF_CTRL_1 0xF4C1 -+#define F367_QAM_CHECK_ERROR_BIT 0xF4C10080 -+#define F367_QAM_CHCK_F_SYNC 0xF4C10040 -+#define F367_QAM_H_MODE 0xF4C10008 -+#define F367_QAM_D_V_MODE 0xF4C10004 -+#define F367_QAM_MODE 0xF4C10003 -+ -+/* TSMF_CTRL_3 */ -+#define R367_QAM_TSMF_CTRL_3 0xF4C3 -+#define F367_QAM_SYNC_IN_COUNT 0xF4C300F0 -+#define F367_QAM_SYNC_OUT_COUNT 0xF4C3000F -+ -+/* TS_ON_ID_0 */ -+#define R367_QAM_TS_ON_ID_0 0xF4C4 -+#define F367_QAM_TS_ID_L 0xF4C400FF -+ -+/* TS_ON_ID_1 */ -+#define R367_QAM_TS_ON_ID_1 0xF4C5 -+#define F367_QAM_TS_ID_H 0xF4C500FF -+ -+/* TS_ON_ID_2 */ -+#define R367_QAM_TS_ON_ID_2 0xF4C6 -+#define F367_QAM_ON_ID_L 0xF4C600FF -+ -+/* TS_ON_ID_3 */ -+#define R367_QAM_TS_ON_ID_3 0xF4C7 -+#define F367_QAM_ON_ID_H 0xF4C700FF -+ -+/* RE_STATUS_0 */ -+#define R367_QAM_RE_STATUS_0 0xF4C8 -+#define F367_QAM_RECEIVE_STATUS_L 0xF4C800FF -+ -+/* RE_STATUS_1 */ -+#define R367_QAM_RE_STATUS_1 0xF4C9 -+#define F367_QAM_RECEIVE_STATUS_LH 0xF4C900FF -+ -+/* RE_STATUS_2 */ -+#define R367_QAM_RE_STATUS_2 0xF4CA -+#define F367_QAM_RECEIVE_STATUS_HL 0xF4CA00FF -+ -+/* RE_STATUS_3 */ -+#define R367_QAM_RE_STATUS_3 0xF4CB -+#define F367_QAM_RECEIVE_STATUS_HH 0xF4CB003F -+ -+/* TS_STATUS_0 */ -+#define R367_QAM_TS_STATUS_0 0xF4CC -+#define F367_QAM_TS_STATUS_L 0xF4CC00FF -+ -+/* TS_STATUS_1 */ -+#define R367_QAM_TS_STATUS_1 0xF4CD -+#define F367_QAM_TS_STATUS_H 0xF4CD007F -+ -+/* TS_STATUS_2 */ -+#define R367_QAM_TS_STATUS_2 0xF4CE -+#define F367_QAM_ERROR 0xF4CE0080 -+#define F367_QAM_EMERGENCY 0xF4CE0040 -+#define F367_QAM_CRE_TS 0xF4CE0030 -+#define F367_QAM_VER 0xF4CE000E -+#define F367_QAM_M_LOCK 0xF4CE0001 -+ -+/* TS_STATUS_3 */ -+#define R367_QAM_TS_STATUS_3 0xF4CF -+#define F367_QAM_UPDATE_READY 0xF4CF0080 -+#define F367_QAM_END_FRAME_HEADER 0xF4CF0040 -+#define F367_QAM_CONTCNT 0xF4CF0020 -+#define F367_QAM_TS_IDENTIFIER_SEL 0xF4CF000F -+ -+/* T_O_ID_0 */ -+#define R367_QAM_T_O_ID_0 0xF4D0 -+#define F367_QAM_ON_ID_I_L 0xF4D000FF -+ -+/* T_O_ID_1 */ -+#define R367_QAM_T_O_ID_1 0xF4D1 -+#define F367_QAM_ON_ID_I_H 0xF4D100FF -+ -+/* T_O_ID_2 */ -+#define R367_QAM_T_O_ID_2 0xF4D2 -+#define F367_QAM_TS_ID_I_L 0xF4D200FF -+ -+/* T_O_ID_3 */ -+#define R367_QAM_T_O_ID_3 0xF4D3 -+#define F367_QAM_TS_ID_I_H 0xF4D300FF -+ -diff --git a/drivers/media/dvb-frontends/tda18212dd.c b/drivers/media/dvb-frontends/tda18212dd.c -new file mode 100644 -index 0000000..de2350b ---- /dev/null -+++ b/drivers/media/dvb-frontends/tda18212dd.c -@@ -0,0 +1,906 @@ -+/* -+ * tda18212: Driver for the TDA18212 tuner -+ * -+ * Copyright (C) 2011 Digital Devices GmbH -+ * -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 only, as published by the Free Software Foundation. -+ * -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ * 02110-1301, USA -+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "dvb_frontend.h" -+ -+#ifndef CHK_ERROR -+ #define CHK_ERROR(s) if ((status = s) < 0) break -+#endif -+ -+#define MASTER_PSM_AGC1 0 -+#define MASTER_AGC1_6_15dB 1 -+ -+#define SLAVE_PSM_AGC1 1 -+#define SLAVE_AGC1_6_15dB 0 -+ -+// 0 = 2 Vpp ... 2 = 1 Vpp, 7 = 0.5 Vpp -+#define IF_LEVEL_DVBC 2 -+#define IF_LEVEL_DVBT 2 -+ -+enum { -+ ID_1 = 0x00, -+ ID_2 = 0x01, -+ ID_3 = 0x02, -+ THERMO_1, -+ THERMO_2, -+ POWER_STATE_1, -+ POWER_STATE_2, -+ INPUT_POWER_LEVEL, -+ IRQ_STATUS, -+ IRQ_ENABLE, -+ IRQ_CLEAR, -+ IRQ_SET, -+ AGC1_1, -+ AGC2_1, -+ AGCK_1, -+ RF_AGC_1, -+ IR_MIXER_1 = 0x10, -+ AGC5_1, -+ IF_AGC, -+ IF_1, -+ REFERENCE, -+ IF_FREQUENCY_1, -+ RF_FREQUENCY_1, -+ RF_FREQUENCY_2, -+ RF_FREQUENCY_3, -+ MSM_1, -+ MSM_2, -+ PSM_1, -+ DCC_1, -+ FLO_MAX, -+ IR_CAL_1, -+ IR_CAL_2, -+ IR_CAL_3 = 0x20, -+ IR_CAL_4, -+ VSYNC_MGT, -+ IR_MIXER_2, -+ AGC1_2, -+ AGC5_2, -+ RF_CAL_1, -+ RF_CAL_2, -+ RF_CAL_3, -+ RF_CAL_4, -+ RF_CAL_5, -+ RF_CAL_6, -+ RF_FILTER_1, -+ RF_FILTER_2, -+ RF_FILTER_3, -+ RF_BAND_PASS_FILTER, -+ CP_CURRENT = 0x30, -+ AGC_DET_OUT = 0x31, -+ RF_AGC_GAIN_1 = 0x32, -+ RF_AGC_GAIN_2 = 0x33, -+ IF_AGC_GAIN = 0x34, -+ POWER_1 = 0x35, -+ POWER_2 = 0x36, -+ MISC_1, -+ RFCAL_LOG_1, -+ RFCAL_LOG_2, -+ RFCAL_LOG_3, -+ RFCAL_LOG_4, -+ RFCAL_LOG_5, -+ RFCAL_LOG_6, -+ RFCAL_LOG_7, -+ RFCAL_LOG_8, -+ RFCAL_LOG_9 = 0x40, -+ RFCAL_LOG_10 = 0x41, -+ RFCAL_LOG_11 = 0x42, -+ RFCAL_LOG_12 = 0x43, -+ REG_MAX, -+}; -+ -+enum HF_Standard { -+ HF_None=0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio, -+ HF_AnalogMax, HF_DVBT_6MHZ, HF_DVBT_7MHZ, HF_DVBT_8MHZ, -+ HF_DVBT, HF_ATSC, HF_DVBC_6MHZ, HF_DVBC_7MHZ, -+ HF_DVBC_8MHZ, HF_DVBC -+}; -+ -+struct SStandardParams { -+ s32 m_IFFrequency; -+ u32 m_BandWidth; -+ u8 m_IF_1; // FF IF_HP_fc:2 IF_Notch:1 LP_FC_Offset:2 LP_FC:3 -+ u8 m_IR_MIXER_2; // 03 :6 HI_Pass:1 DC_Notch:1 -+ u8 m_AGC1_1; // 0F :4 AGC1_Top:4 -+ u8 m_AGC2_1; // 0F :4 AGC2_Top:4 -+ u8 m_RF_AGC_1_Low; // EF RF_AGC_Adapt:1 RF_AGC_Adapt_Top:2 :1 RF_Atten_3dB:1 RF_AGC_Top:3 -+ u8 m_RF_AGC_1_High;// EF RF_AGC_Adapt:1 RF_AGC_Adapt_Top:2 :1 RF_Atten_3dB:1 RF_AGC_Top:3 -+ u8 m_IR_MIXER_1; // 0F :4 IR_mixer_Top:4 -+ u8 m_AGC5_1; // 1F :3 AGC5_Ana AGC5_Top:4 -+ u8 m_AGCK_1; // 0F :4 AGCK_Step:2 AGCK_Mode:2 -+ u8 m_PSM_1; // 20 :2 PSM_StoB:1 :5 -+ bool m_AGC1_Freeze; -+ bool m_LTO_STO_immune; -+}; -+ -+struct SStandardParams m_StandardTable[HF_DVBC_8MHZ - HF_DVBT_6MHZ + 1] = -+{ -+ { 3250000, 6000000, 0x20, 0x03, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_6MHZ -+ { 3500000, 7000000, 0x31, 0x01, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_7MHZ -+ { 4000000, 8000000, 0x22, 0x01, 0x00, 0x07, 0x2B, 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, // HF_DVBT_8MHZ -+ { 0, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, false, false }, // HF_DVBT (Unused) -+ { 3250000, 6000000, 0x20, 0x03, 0x0A, 0x07, 0x6D, 0x6D, 0x0E, 0x0E, 0x02, 0x20, false, false }, // HF_ATSC -+ { 3600000, 6000000, 0x10, 0x01, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_6MHZ -+// { 5000000, 7000000, 0x53, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) -+// { 5000000, 8000000, 0x53, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_8MHZ -+ { 5000000, 7000000, 0x93, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) -+ { 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x83, 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, // HF_DVBC_8MHZ -+}; -+ -+struct tda_state { -+ struct i2c_adapter *i2c; -+ u8 adr; -+ -+ enum HF_Standard m_Standard; -+ u32 m_Frequency; -+ u32 IF; -+ -+ bool m_isMaster; -+ bool m_bPowerMeasurement; -+ bool m_bLTEnable; -+ bool m_bEnableFreeze; -+ -+ u16 m_ID; -+ -+ s32 m_SettlingTime; -+ -+ u8 m_IFLevelDVBC; -+ u8 m_IFLevelDVBT; -+ u8 m_Regs[REG_MAX]; -+ u8 m_LastPowerLevel; -+}; -+ -+static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len) -+{ -+ struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, -+ .buf = data, .len = len}}; -+ return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; -+} -+ -+static int i2c_read(struct i2c_adapter *adap, -+ u8 adr, u8 *msg, int len, u8 *answ, int alen) -+{ -+ struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, -+ .buf = msg, .len = len}, -+ { .addr = adr, .flags = I2C_M_RD, -+ .buf = answ, .len = alen } }; -+ if (i2c_transfer(adap, msgs, 2) != 2) { -+ printk("tda18212dd: i2c_read error\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -+{ -+ struct i2c_msg msg = {.addr = adr, .flags = 0, -+ .buf = data, .len = len}; -+ -+ if (i2c_transfer(adap, &msg, 1) != 1) { -+ printk("tda18212: i2c_write error\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+static int write_regs(struct tda_state *state, -+ u8 SubAddr, u8 *Regs, u16 nRegs) -+{ -+ u8 data[nRegs+1]; -+ -+ data[0] = SubAddr; -+ memcpy(data + 1, Regs, nRegs); -+ return i2c_write(state->i2c, state->adr, data, nRegs+1); -+} -+ -+static int write_reg(struct tda_state *state, u8 SubAddr,u8 Reg) -+{ -+ u8 msg[2] = {SubAddr, Reg}; -+ -+ return i2c_write(state->i2c, state->adr, msg, 2); -+} -+ -+static int Read(struct tda_state *state, u8 * Regs) -+{ -+ return i2c_readn(state->i2c, state->adr, Regs, REG_MAX); -+} -+ -+static int update_regs(struct tda_state *state, u8 RegFrom,u8 RegTo) -+{ -+ return write_regs(state, RegFrom, -+ &state->m_Regs[RegFrom], RegTo-RegFrom+1); -+} -+ -+static int update_reg(struct tda_state *state, u8 Reg) -+{ -+ return write_reg(state, Reg,state->m_Regs[Reg]); -+} -+ -+ -+static int read_regs(struct tda_state *state, -+ u8 SubAddr, u8 *Regs, u16 nRegs) -+{ -+ return i2c_read(state->i2c, state->adr, -+ &SubAddr, 1, Regs, nRegs); -+} -+ -+static int read_reg(struct tda_state *state, -+ u8 SubAddr, u8 *Reg) -+{ -+ return i2c_read(state->i2c, state->adr, -+ &SubAddr, 1, Reg, 1); -+} -+ -+static int read_reg1(struct tda_state *state, u8 Reg) -+{ -+ return read_reg(state, Reg, &state->m_Regs[Reg]); -+} -+ -+static void init_state(struct tda_state *state) -+{ -+ u32 ulIFLevelDVBC = IF_LEVEL_DVBC; -+ u32 ulIFLevelDVBT = IF_LEVEL_DVBT; -+ u32 ulPowerMeasurement = 1; -+ u32 ulLTEnable = 1; -+ u32 ulEnableFreeze = 0; -+ -+ state->m_Frequency = 0; -+ state->m_isMaster = true; -+ state->m_ID = 0; -+ state->m_LastPowerLevel = 0xFF; -+ state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07); -+ state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07); -+ state->m_bPowerMeasurement = (ulPowerMeasurement != 0); -+ state->m_bLTEnable = (ulLTEnable != 0); -+ state->m_bEnableFreeze = (ulEnableFreeze != 0); -+} -+ -+static int StartCalibration(struct tda_state *state) -+{ -+ int status = 0; -+ do { -+ state->m_Regs[POWER_2] &= ~0x02; // RSSI CK = 31.25 kHz -+ CHK_ERROR(update_reg(state, POWER_2)); -+ -+ state->m_Regs[AGC1_2] = (state->m_Regs[AGC1_2] & ~0x60) | 0x40; // AGC1 Do Step = 2 -+ CHK_ERROR(update_reg(state, AGC1_2)); // AGC -+ -+ state->m_Regs[RF_FILTER_3] = (state->m_Regs[RF_FILTER_3] & ~0xC0) | 0x40; // AGC2 Do Step = 1 -+ CHK_ERROR(update_reg(state, RF_FILTER_3)); -+ -+ state->m_Regs[AGCK_1] |= 0xC0; // AGCs Assym Up Step = 3 // Datasheet sets all bits to 1! -+ CHK_ERROR(update_reg(state, AGCK_1)); -+ -+ state->m_Regs[AGC5_1] = (state->m_Regs[AGC5_1] & ~0x60) | 0x40; // AGCs Assym Do Step = 2 -+ CHK_ERROR(update_reg(state, AGC5_1)); -+ -+ state->m_Regs[IRQ_CLEAR] |= 0x80; // Reset IRQ -+ CHK_ERROR(update_reg(state, IRQ_CLEAR)); -+ -+ state->m_Regs[MSM_1] = 0x3B; // Set Calibration -+ state->m_Regs[MSM_2] = 0x01; // Start MSM -+ CHK_ERROR(update_regs(state, MSM_1,MSM_2)); -+ state->m_Regs[MSM_2] = 0x00; -+ -+ } while(0); -+ return status; -+} -+ -+static int FinishCalibration(struct tda_state *state) -+{ -+ int status = 0; -+ u8 RFCal_Log[12]; -+ -+ do { -+ u8 IRQ = 0; -+ int Timeout = 150; // 1.5 s -+ while(true) { -+ CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); -+ if ((IRQ & 0x80) != 0 ) -+ break; -+ Timeout -= 1; -+ if (Timeout == 0) { -+ status = -1; -+ break; -+ } -+ msleep(10); -+ } -+ CHK_ERROR(status); -+ -+ state->m_Regs[FLO_MAX] = 0x0A; -+ CHK_ERROR(update_reg(state, FLO_MAX)); -+ -+ state->m_Regs[AGC1_1] &= ~0xC0; -+ if( state->m_bLTEnable ) state->m_Regs[AGC1_1] |= 0x80; // LTEnable -+ -+ state->m_Regs[AGC1_1] |= (state->m_isMaster ? MASTER_AGC1_6_15dB : SLAVE_AGC1_6_15dB ) << 6; -+ CHK_ERROR(update_reg(state, AGC1_1)); -+ -+ state->m_Regs[PSM_1] &= ~0xC0; -+ state->m_Regs[PSM_1] |= (state->m_isMaster ? MASTER_PSM_AGC1 : SLAVE_PSM_AGC1 ) << 6; -+ CHK_ERROR(update_reg(state, PSM_1)); -+ -+ state->m_Regs[REFERENCE] |= 0x03; // XTOUT = 3 -+ CHK_ERROR(update_reg(state, REFERENCE)); -+ -+ CHK_ERROR(read_regs(state, RFCAL_LOG_1,RFCal_Log,sizeof(RFCal_Log))); -+ } while(0); -+ return status; -+} -+ -+static int PowerOn(struct tda_state *state) -+{ -+ state->m_Regs[POWER_STATE_2] &= ~0x0F; -+ update_reg(state, POWER_STATE_2); -+ state->m_Regs[REFERENCE] |= 0x40; // Digital clock source = Sigma Delta -+ update_reg(state, REFERENCE); -+ return 0; -+} -+ -+static int Standby(struct tda_state *state) -+{ -+ int status = 0; -+ -+ do { -+ state->m_Regs[REFERENCE] &= ~0x40; // Digital clock source = Quarz -+ CHK_ERROR(update_reg(state, REFERENCE)); -+ -+ state->m_Regs[POWER_STATE_2] &= ~0x0F; -+ state->m_Regs[POWER_STATE_2] |= state->m_isMaster ? 0x08 : 0x0E; -+ CHK_ERROR(update_reg(state, POWER_STATE_2)); -+ } while(0); -+ return status; -+} -+ -+static int attach_init(struct tda_state *state) -+{ -+ int stat = 0; -+ u8 Id[2]; -+ u8 PowerState = 0x00; -+ -+ state->m_Standard = HF_None; -+ -+ /* first read after cold reset sometimes fails on some cards, -+ try twice */ -+ stat = read_regs(state, ID_1, Id, sizeof(Id)); -+ stat = read_regs(state, ID_1, Id, sizeof(Id)); -+ if (stat < 0) -+ return -1; -+ -+ state->m_ID = ((Id[0] & 0x7F) << 8) | Id[1]; -+ state->m_isMaster = ((Id[0] & 0x80) != 0); -+ if( !state->m_isMaster ) -+ state->m_bLTEnable = false; -+ -+ printk("tda18212dd: ChipID %04x\n", state->m_ID); -+ -+ if( state->m_ID != 18212 ) -+ return -1; -+ -+ stat = read_reg(state, POWER_STATE_1 ,&PowerState); -+ if (stat < 0) -+ return stat; -+ -+ printk("tda18212dd: PowerState %02x\n", PowerState); -+ -+ if (state->m_isMaster) { -+ if( PowerState & 0x02 ) { -+ // msleep for XTAL Calibration (on a PC this should be long done) -+ u8 IRQStatus = 0; -+ int Timeout = 10; -+ -+ while(Timeout > 0) { -+ read_reg(state, IRQ_STATUS, &IRQStatus); -+ if (IRQStatus & 0x20) -+ break; -+ Timeout -= 1; -+ msleep(10); -+ } -+ if( (IRQStatus & 0x20) == 0 ) { -+ stat = -ETIMEDOUT; -+ } -+ } -+ } else { -+ write_reg(state, FLO_MAX, 0x00); -+ write_reg(state, CP_CURRENT,0x68); -+ } -+ Read(state, state->m_Regs); -+ -+ PowerOn(state); -+ StartCalibration(state); -+ FinishCalibration(state); -+ Standby(state); -+ return stat; -+} -+ -+static int PowerMeasurement(struct tda_state *state, u8 *pPowerLevel) -+{ -+ int status = 0; -+ -+ do { -+ u8 IRQ = 0; -+ int Timeout = 70; // 700 ms -+ -+ state->m_Regs[IRQ_CLEAR] |= 0x80; // Reset IRQ -+ CHK_ERROR(update_reg(state, IRQ_CLEAR)); -+ -+ state->m_Regs[MSM_1] = 0x80; // power measurement -+ state->m_Regs[MSM_2] = 0x01; // Start MSM -+ CHK_ERROR(update_regs(state, MSM_1,MSM_2)); -+ state->m_Regs[MSM_2] = 0x00; -+ -+ while(true) { -+ CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); -+ if( (IRQ & 0x80) != 0 ) -+ break; -+ Timeout -= 1; -+ if( Timeout == 0 ) -+ { -+ status = -1; -+ break; -+ } -+ msleep(10); -+ } -+ CHK_ERROR(status); -+ -+ CHK_ERROR(read_reg1(state, INPUT_POWER_LEVEL)); -+ *pPowerLevel = state->m_Regs[INPUT_POWER_LEVEL] & 0x7F; -+ -+ -+ if( *pPowerLevel > 110 ) *pPowerLevel = 110; -+ } while(0); -+ /* printk("PL %d\n", *pPowerLevel); */ -+ return status; -+} -+ -+static int SetFrequency(struct tda_state *state, u32 Frequency, enum HF_Standard Standard) -+{ -+ int status = 0; -+ struct SStandardParams *StandardParams; -+ u32 f = Frequency / 1000; -+ u8 IRQ = 0; -+ int Timeout = 25; // 250 ms -+ u32 fRatio = Frequency / 16000000; -+ u32 fDelta = Frequency - fRatio * 16000000; -+ -+ if( Standard < HF_DVBT_6MHZ || Standard > HF_DVBC_8MHZ ) -+ return -EINVAL; -+ StandardParams = &m_StandardTable[Standard - HF_DVBT_6MHZ]; -+ -+ if( StandardParams->m_IFFrequency == 0 ) -+ return -EINVAL; -+ state->m_Standard = HF_None; -+ state->m_Frequency = 0; -+ -+ do { -+ // IF Level -+ state->m_Regs[IF_AGC] = (Standard >= HF_DVBC_6MHZ) ? state->m_IFLevelDVBC : state->m_IFLevelDVBT; -+ CHK_ERROR(update_reg(state, IF_AGC)); -+ -+ // --------------------------------------------------------------------------------- -+ // Standard setup -+ -+ state->m_Regs[IF_1] = StandardParams->m_IF_1; -+ CHK_ERROR(update_reg(state, IF_1)); -+ -+ state->m_Regs[IR_MIXER_2] = (state->m_Regs[IR_MIXER_2] & ~0x03) | StandardParams->m_IR_MIXER_2; -+ CHK_ERROR(update_reg(state, IR_MIXER_2)); -+ -+ state->m_Regs[AGC1_1] = (state->m_Regs[AGC1_1] & ~0x0F) | StandardParams->m_AGC1_1; -+ CHK_ERROR(update_reg(state, AGC1_1)); -+ -+ state->m_Regs[AGC2_1] = (state->m_Regs[AGC2_1] & ~0x0F) | StandardParams->m_AGC2_1; -+ CHK_ERROR(update_reg(state, AGC2_1)); -+ -+ state->m_Regs[RF_AGC_1] &= ~0xEF; -+ if( Frequency < 291000000 ) -+ state->m_Regs[RF_AGC_1] |= StandardParams->m_RF_AGC_1_Low; -+ else -+ state->m_Regs[RF_AGC_1] |= StandardParams->m_RF_AGC_1_High; -+ CHK_ERROR(update_reg(state, RF_AGC_1)); -+ -+ state->m_Regs[IR_MIXER_1] = (state->m_Regs[IR_MIXER_1] & ~0x0F) | StandardParams->m_IR_MIXER_1; -+ CHK_ERROR(update_reg(state, IR_MIXER_1)); -+ -+ state->m_Regs[AGC5_1] = (state->m_Regs[AGC5_1] & ~0x1F) | StandardParams->m_AGC5_1; -+ CHK_ERROR(update_reg(state, AGC5_1)); -+ -+ state->m_Regs[AGCK_1] = (state->m_Regs[AGCK_1] & ~0x0F) | StandardParams->m_AGCK_1; -+ CHK_ERROR(update_reg(state, AGCK_1)); -+ -+ state->m_Regs[PSM_1] = (state->m_Regs[PSM_1] & ~0x20) | StandardParams->m_PSM_1; -+ CHK_ERROR(update_reg(state, PSM_1)); -+ -+ state->m_Regs[IF_FREQUENCY_1] = ( StandardParams->m_IFFrequency / 50000 ); -+ CHK_ERROR(update_reg(state, IF_FREQUENCY_1)); -+ -+ if( state->m_isMaster && StandardParams->m_LTO_STO_immune ) -+ { -+ u8 tmp; -+ u8 RF_Filter_Gain; -+ -+ CHK_ERROR(read_reg(state, RF_AGC_GAIN_1,&tmp)); -+ RF_Filter_Gain = (tmp & 0x30) >> 4; -+ -+ state->m_Regs[RF_FILTER_1] = (state->m_Regs[RF_FILTER_1] & ~0x0C) | (RF_Filter_Gain << 2); -+ CHK_ERROR(update_reg(state, RF_FILTER_1)); -+ -+ state->m_Regs[RF_FILTER_1] |= 0x10; // Force -+ CHK_ERROR(update_reg(state, RF_FILTER_1)); -+ -+ while( RF_Filter_Gain != 0 ) -+ { -+ RF_Filter_Gain -= 1; -+ state->m_Regs[RF_FILTER_1] = (state->m_Regs[RF_FILTER_1] & ~0x0C) | (RF_Filter_Gain << 2); -+ CHK_ERROR(update_reg(state, RF_FILTER_1)); -+ msleep(10); -+ } -+ CHK_ERROR(status); -+ -+ state->m_Regs[RF_AGC_1] |= 0x08; -+ CHK_ERROR(update_reg(state, RF_AGC_1)); -+ } -+ -+ // --------------------------------------------------------------------------------- -+ -+ state->m_Regs[IRQ_CLEAR] |= 0x80; // Reset IRQ -+ CHK_ERROR(update_reg(state, IRQ_CLEAR)); -+ -+ CHK_ERROR(PowerOn(state)); -+ -+ state->m_Regs[RF_FREQUENCY_1] = ((f >> 16) & 0xFF); -+ state->m_Regs[RF_FREQUENCY_2] = ((f >> 8) & 0xFF); -+ state->m_Regs[RF_FREQUENCY_3] = ((f ) & 0xFF); -+ CHK_ERROR(update_regs(state, RF_FREQUENCY_1,RF_FREQUENCY_3)); -+ -+ state->m_Regs[MSM_1] = 0x41; // Tune -+ state->m_Regs[MSM_2] = 0x01; // Start MSM -+ CHK_ERROR(update_regs(state, MSM_1, MSM_2)); -+ state->m_Regs[MSM_2] = 0x00; -+ -+ while(true) -+ { -+ CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); -+ if( (IRQ & 0x80) != 0 ) break; -+ Timeout -= 1; -+ if (Timeout == 0) { -+ status = -1; -+ break; -+ } -+ msleep(10); -+ } -+ CHK_ERROR(status); -+ -+ // --------------------------------------------------------------------------------- -+ -+ if( state->m_isMaster && StandardParams->m_LTO_STO_immune ) -+ { -+ state->m_Regs[RF_AGC_1] &= ~0x08; -+ CHK_ERROR(update_reg(state, RF_AGC_1)); -+ -+ msleep(50); -+ -+ state->m_Regs[RF_FILTER_1] &= ~0x10; // remove force -+ CHK_ERROR(update_reg(state, RF_FILTER_1)); -+ } -+ -+ // --------------------------------------------------------------------------------- -+ // Spur reduction -+ -+ if( Frequency < 72000000 ) -+ { -+ state->m_Regs[REFERENCE] |= 0x40; // Set digital clock -+ } -+ else if( Frequency < 104000000 ) -+ { -+ state->m_Regs[REFERENCE] &= ~0x40; // Clear digital clock -+ } -+ else if( Frequency < 120000000 ) -+ { -+ state->m_Regs[REFERENCE] |= 0x40; // Set digital clock -+ } -+ else -+ { -+ if( fDelta <= 8000000 ) -+ { -+ if( fRatio & 1 ) state->m_Regs[REFERENCE] &= ~0x40; // Clear digital clock -+ else state->m_Regs[REFERENCE] |= 0x40; // Set digital clock -+ } -+ else -+ { -+ if( fRatio & 1 ) state->m_Regs[REFERENCE] |= 0x40; // Set digital clock -+ else state->m_Regs[REFERENCE] &= ~0x40; // Clear digital clock -+ } -+ -+ } -+ CHK_ERROR(update_reg(state, REFERENCE)); -+ -+ if( StandardParams->m_AGC1_Freeze && state->m_bEnableFreeze ) -+ { -+ u8 tmp; -+ int AGC1GainMin = 0; -+ int nSteps = 10; -+ int Step = 0; -+ -+ CHK_ERROR(read_reg(state, AGC1_2,&tmp)); -+ -+ if( (tmp & 0x80) == 0 ) -+ { -+ state->m_Regs[AGC1_2] |= 0x80; // Loop off -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ state->m_Regs[AGC1_2] |= 0x10 ; // Force gain -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ } -+ // Adapt -+ if( state->m_Regs[AGC1_1] & 0x40 ) // AGC1_6_15dB set -+ { -+ AGC1GainMin = 6; -+ nSteps = 4; -+ } -+ while( Step < nSteps ) -+ { -+ int Down = 0; -+ int Up = 0, i; -+ u8 AGC1_Gain; -+ -+ Step = Step + 1; -+ -+ for (i = 0; i < 40; i += 1) { -+ CHK_ERROR(read_reg(state, AGC_DET_OUT, &tmp)); -+ Up += (tmp & 0x02) ? 1 : -4; -+ Down += (tmp & 0x01) ? 14 : -1; -+ msleep(1); -+ } -+ CHK_ERROR(status); -+ AGC1_Gain = (state->m_Regs[AGC1_2] & 0x0F); -+ if( Up >= 15 && AGC1_Gain != 9 ) -+ { -+ state->m_Regs[AGC1_2] = ( state->m_Regs[AGC1_2] & ~0x0F ) | (AGC1_Gain + 1); -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ } -+ else if ( Down >= 10 && AGC1_Gain != AGC1GainMin ) -+ { -+ state->m_Regs[AGC1_2] = ( state->m_Regs[AGC1_2] & ~0x0F ) | (AGC1_Gain - 1); -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ } -+ else -+ { -+ Step = nSteps; -+ } -+ } -+ } -+ else -+ { -+ state->m_Regs[AGC1_2] &= ~0x10 ; // unforce gain -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ state->m_Regs[AGC1_2] &= ~0x80; // Loop on -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ } -+ -+ state->m_Standard = Standard; -+ state->m_Frequency = Frequency; -+ -+ if( state->m_bPowerMeasurement ) -+ PowerMeasurement(state, &state->m_LastPowerLevel); -+ } while(0); -+ -+ return status; -+} -+ -+static int sleep(struct dvb_frontend* fe) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ -+ Standby(state); -+ return 0; -+} -+ -+static int init(struct dvb_frontend* fe) -+{ -+ //struct tda_state *state = fe->tuner_priv; -+ return 0; -+} -+ -+static int release(struct dvb_frontend* fe) -+{ -+ kfree(fe->tuner_priv); -+ fe->tuner_priv = NULL; -+ return 0; -+} -+ -+#ifdef USE_API3 -+static int set_params(struct dvb_frontend *fe, -+ struct dvb_frontend_parameters *params) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ int status = 0; -+ int Standard; -+ -+ state->m_Frequency = params->frequency; -+ -+ if (fe->ops.info.type == FE_OFDM) -+ switch (params->u.ofdm.bandwidth) { -+ case BANDWIDTH_6_MHZ: -+ Standard = HF_DVBT_6MHZ; -+ break; -+ case BANDWIDTH_7_MHZ: -+ Standard = HF_DVBT_7MHZ; -+ break; -+ default: -+ case BANDWIDTH_8_MHZ: -+ Standard = HF_DVBT_8MHZ; -+ break; -+ } -+ else if (fe->ops.info.type == FE_QAM) { -+ Standard = HF_DVBC_8MHZ; -+ } else -+ return -EINVAL; -+ -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 1); -+ SetFrequency(state, state->m_Frequency, Standard); -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 0); -+ -+ return status; -+} -+#else -+static int set_params(struct dvb_frontend *fe) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ struct dtv_frontend_properties *p = &fe->dtv_property_cache; -+ int status = 0; -+ int Standard; -+ -+ state->m_Frequency = p->frequency; -+ -+ if (p->delivery_system == SYS_DVBT) -+ switch (p->bandwidth_hz) { -+ case 6000000: -+ Standard = HF_DVBT_6MHZ; -+ break; -+ case 7000000: -+ Standard = HF_DVBT_7MHZ; -+ break; -+ default: -+ case 8000000: -+ Standard = HF_DVBT_8MHZ; -+ break; -+ } -+ else if (p->delivery_system == SYS_DVBC_ANNEX_A) { -+ Standard = HF_DVBC_8MHZ; -+ } else -+ return -EINVAL; -+ -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 1); -+ SetFrequency(state, state->m_Frequency, Standard); -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 0); -+ -+ return status; -+} -+#endif -+ -+static int get_frequency(struct dvb_frontend *fe, u32 *frequency) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ -+ *frequency = state->IF; -+ return 0; -+} -+ -+static int get_rf_strength(struct dvb_frontend *fe, u16 *st) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ -+ *st = state->m_LastPowerLevel; -+ return 0; -+} -+ -+static int get_if(struct dvb_frontend *fe, u32 *frequency) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ -+ state->IF = 0; -+ if (state->m_Standard < HF_DVBT_6MHZ || -+ state->m_Standard > HF_DVBC_8MHZ) -+ return 0; -+ state->IF = m_StandardTable[state->m_Standard - HF_DVBT_6MHZ].m_IFFrequency; -+ *frequency = state->IF; -+ return 0; -+} -+ -+static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) -+{ -+ //struct tda_state *state = fe->tuner_priv; -+ //*bandwidth = priv->bandwidth; -+ return 0; -+} -+ -+ -+static struct dvb_tuner_ops tuner_ops = { -+ .info = { -+ .name = "NXP TDA18212", -+ .frequency_min = 47125000, -+ .frequency_max = 865000000, -+ .frequency_step = 62500 -+ }, -+ .init = init, -+ .sleep = sleep, -+ .set_params = set_params, -+ .release = release, -+ .get_frequency = get_frequency, -+ .get_if_frequency = get_if, -+ .get_bandwidth = get_bandwidth, -+ .get_rf_strength = get_rf_strength, -+}; -+ -+struct dvb_frontend *tda18212dd_attach(struct dvb_frontend *fe, -+ struct i2c_adapter *i2c, u8 adr) -+{ -+ struct tda_state *state; -+ int stat; -+ -+ state = kzalloc(sizeof(struct tda_state), GFP_KERNEL); -+ if (!state) -+ return NULL; -+ state->adr = adr; -+ state->i2c = i2c; -+ memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops)); -+ init_state(state); -+ -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 1); -+ stat = attach_init(state); -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 0); -+ if (stat < 0) { -+ kfree(state); -+ return 0; -+ } -+ fe->tuner_priv = state; -+ return fe; -+} -+ -+EXPORT_SYMBOL_GPL(tda18212dd_attach); -+MODULE_DESCRIPTION("TDA18212 driver"); -+MODULE_AUTHOR("DD"); -+MODULE_LICENSE("GPL"); -+ -+/* -+ * Local variables: -+ * c-basic-offset: 8 -+ * End: -+ */ -diff --git a/drivers/media/dvb-frontends/tda18212dd.h b/drivers/media/dvb-frontends/tda18212dd.h -new file mode 100644 -index 0000000..687fab4 ---- /dev/null -+++ b/drivers/media/dvb-frontends/tda18212dd.h -@@ -0,0 +1,5 @@ -+#ifndef _TDA18212DD_H_ -+#define _TDA18212DD_H_ -+struct dvb_frontend *tda18212dd_attach(struct dvb_frontend *fe, -+ struct i2c_adapter *i2c, u8 adr); -+#endif -diff --git a/drivers/media/pci/ddbridge/Kconfig b/drivers/media/pci/ddbridge/Kconfig -index 44e5dc1..0a4ae75 100644 ---- a/drivers/media/pci/ddbridge/Kconfig -+++ b/drivers/media/pci/ddbridge/Kconfig -@@ -1,11 +1,14 @@ - config DVB_DDBRIDGE - tristate "Digital Devices bridge support" - depends on DVB_CORE && PCI && I2C -- select DVB_LNBP21 if MEDIA_SUBDRV_AUTOSELECT -- select DVB_STV6110x if MEDIA_SUBDRV_AUTOSELECT -- select DVB_STV090x if MEDIA_SUBDRV_AUTOSELECT -- select DVB_DRXK if MEDIA_SUBDRV_AUTOSELECT -- select DVB_TDA18271C2DD if MEDIA_SUBDRV_AUTOSELECT -+ select DVB_CXD2099 -+ select DVB_LNBP21 if !DVB_FE_CUSTOMISE -+ select DVB_STV6110x if !DVB_FE_CUSTOMISE -+ select DVB_STV090x if !DVB_FE_CUSTOMISE -+ select DVB_DRXK if !DVB_FE_CUSTOMISE -+ select DVB_TDA18271C2DD if !DVB_FE_CUSTOMISE -+ select DVB_STV0367DD if !DVB_FE_CUSTOMISE -+ select DVB_TDA18212DD if !DVB_FE_CUSTOMISE - ---help--- - Support for cards with the Digital Devices PCI express bridge: - - Octopus PCIe Bridge -@@ -14,5 +17,6 @@ config DVB_DDBRIDGE - - DuoFlex S2 Octopus - - DuoFlex CT Octopus - - cineS2(v6) -+ - cineCT(v6) - - Say Y if you own such a card and want to use it. -diff --git a/drivers/media/pci/ddbridge/ddbridge-core.c b/drivers/media/pci/ddbridge/ddbridge-core.c -index 36e3452..adff8cd 100644 ---- a/drivers/media/pci/ddbridge/ddbridge-core.c -+++ b/drivers/media/pci/ddbridge/ddbridge-core.c -@@ -31,11 +31,11 @@ - #include - #include - #include -+#include - #include - #include - #include - #include "ddbridge.h" -- - #include "ddbridge-regs.h" - - #include "tda18271c2dd.h" -@@ -43,14 +43,60 @@ - #include "stv090x.h" - #include "lnbh24.h" - #include "drxk.h" -+#if 0 -+#include "stv0367.h" -+#else -+#include "stv0367dd.h" -+#endif -+#if 0 -+#include "tda18212.h" -+#else -+#include "tda18212dd.h" -+#endif -+ -+static int adapter_alloc; -+module_param(adapter_alloc, int, 0444); -+MODULE_PARM_DESC(adapter_alloc, "0-one adapter per io, 1-one per tab with io, 2-one per tab, 3-one for all"); -+ -+static int ts_loop = -1; -+module_param(ts_loop, int, 0444); -+MODULE_PARM_DESC(ts_loop, "TS in/out on port ts_loop"); - - DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); - -+static struct ddb *ddbs[32]; -+ - /* MSI had problems with lost interrupts, fixed but needs testing */ --#undef CONFIG_PCI_MSI -+/* #undef CONFIG_PCI_MSI */ -+ -+/******************************************************************************/ -+ -+static inline void ddbwritel(struct ddb *dev, u32 val, u32 adr) -+{ -+ writel(val, (char *) (dev->regs+(adr))); -+} -+ -+static inline u32 ddbreadl(struct ddb *dev, u32 adr) -+{ -+ return readl((char *) (dev->regs+(adr))); -+} -+ -+#define ddbcpyto(_dev, _adr, _src, _count) memcpy_toio((char *) \ -+ (_dev->regs + (_adr)), (_src), (_count)) -+ -+#define ddbcpyfrom(_dev, _dst, _adr, _count) memcpy_fromio((_dst), (char *) \ -+ (_dev->regs + (_adr)), (_count)) -+ - - /******************************************************************************/ - -+static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -+{ -+ struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len}; -+ -+ return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; -+} -+ - static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) - { - struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, -@@ -58,10 +104,31 @@ static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) - return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; - } - -+static int i2c_read_regs(struct i2c_adapter *adapter, -+ u8 adr, u8 reg, u8 *val, u8 len) -+{ -+ struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, -+ .buf = ®, .len = 1}, -+ {.addr = adr, .flags = I2C_M_RD, -+ .buf = val, .len = len } }; -+ return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; -+} -+ -+static int i2c_read_regs16(struct i2c_adapter *adapter, -+ u8 adr, u16 reg, u8 *val, u8 len) -+{ -+ u8 reg16[2] = { reg >> 8, reg }; -+ struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, -+ .buf = (u8 *)®16, .len = 2}, -+ {.addr = adr, .flags = I2C_M_RD, -+ .buf = val, .len = len } }; -+ return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; -+} -+ - static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val) - { - struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, -- .buf = ®, .len = 1 }, -+ .buf = ®, .len = 1}, - {.addr = adr, .flags = I2C_M_RD, - .buf = val, .len = 1 } }; - return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; -@@ -70,14 +137,22 @@ static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, u8 reg, u8 *val) - static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr, - u16 reg, u8 *val) - { -- u8 msg[2] = {reg>>8, reg&0xff}; -+ u8 msg[2] = {reg >> 8, reg & 0xff}; - struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, - .buf = msg, .len = 2}, - {.addr = adr, .flags = I2C_M_RD, -- .buf = val, .len = 1} }; -+ .buf = val, .len = 1 } }; - return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; - } - -+static int i2c_write_reg16(struct i2c_adapter *adap, u8 adr, -+ u16 reg, u8 val) -+{ -+ u8 msg[3] = {reg >> 8, reg & 0xff, val}; -+ -+ return i2c_write(adap, adr, msg, 3); -+} -+ - static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) - { - struct ddb *dev = i2c->dev; -@@ -85,18 +160,18 @@ static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) - u32 val; - - i2c->done = 0; -- ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND); -+ ddbwritel(dev, (adr << 9) | cmd, i2c->regs + I2C_COMMAND); - stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ); - if (stat <= 0) { - printk(KERN_ERR "I2C timeout\n"); - { /* MSI debugging*/ -- u32 istat = ddbreadl(INTERRUPT_STATUS); -+ u32 istat = ddbreadl(dev, INTERRUPT_STATUS); - printk(KERN_ERR "IRS %08x\n", istat); -- ddbwritel(istat, INTERRUPT_ACK); -+ ddbwritel(dev, istat, INTERRUPT_ACK); - } - return -EIO; - } -- val = ddbreadl(i2c->regs+I2C_COMMAND); -+ val = ddbreadl(dev, i2c->regs+I2C_COMMAND); - if (val & 0x70000) - return -EIO; - return 0; -@@ -105,7 +180,7 @@ static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) - static int ddb_i2c_master_xfer(struct i2c_adapter *adapter, - struct i2c_msg msg[], int num) - { -- struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter); -+ struct ddb_i2c *i2c = (struct ddb_i2c *) i2c_get_adapdata(adapter); - struct ddb *dev = i2c->dev; - u8 addr = 0; - -@@ -116,8 +191,8 @@ static int ddb_i2c_master_xfer(struct i2c_adapter *adapter, - !(msg[0].flags & I2C_M_RD)) { - memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf, - msg[0].buf, msg[0].len); -- ddbwritel(msg[0].len|(msg[1].len << 16), -- i2c->regs+I2C_TASKLENGTH); -+ ddbwritel(dev, msg[0].len|(msg[1].len << 16), -+ i2c->regs + I2C_TASKLENGTH); - if (!ddb_i2c_cmd(i2c, addr, 1)) { - memcpy_fromio(msg[1].buf, - dev->regs + I2C_TASKMEM_BASE + i2c->rbuf, -@@ -125,17 +200,16 @@ static int ddb_i2c_master_xfer(struct i2c_adapter *adapter, - return num; - } - } -- - if (num == 1 && !(msg[0].flags & I2C_M_RD)) { -- ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf, msg[0].buf, msg[0].len); -- ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH); -+ ddbcpyto(dev, I2C_TASKMEM_BASE + i2c->wbuf, msg[0].buf, msg[0].len); -+ ddbwritel(dev, msg[0].len, i2c->regs + I2C_TASKLENGTH); - if (!ddb_i2c_cmd(i2c, addr, 2)) - return num; - } - if (num == 1 && (msg[0].flags & I2C_M_RD)) { -- ddbwritel(msg[0].len << 16, i2c->regs + I2C_TASKLENGTH); -+ ddbwritel(dev, msg[0].len << 16, i2c->regs + I2C_TASKLENGTH); - if (!ddb_i2c_cmd(i2c, addr, 3)) { -- ddbcpyfrom(msg[0].buf, -+ ddbcpyfrom(dev, msg[0].buf, - I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len); - return num; - } -@@ -160,7 +234,7 @@ static void ddb_i2c_release(struct ddb *dev) - struct ddb_i2c *i2c; - struct i2c_adapter *adap; - -- for (i = 0; i < dev->info->port_num; i++) { -+ for (i = 0; i < dev->info->i2c_num; i++) { - i2c = &dev->i2c[i]; - adap = &i2c->adap; - i2c_del_adapter(adap); -@@ -173,15 +247,15 @@ static int ddb_i2c_init(struct ddb *dev) - struct ddb_i2c *i2c; - struct i2c_adapter *adap; - -- for (i = 0; i < dev->info->port_num; i++) { -+ for (i = 0; i < dev->info->i2c_num; i++) { - i2c = &dev->i2c[i]; - i2c->dev = dev; - i2c->nr = i; - i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4); - i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8); - i2c->regs = 0x80 + i * 0x20; -- ddbwritel(I2C_SPEED_100, i2c->regs + I2C_TIMING); -- ddbwritel((i2c->rbuf << 16) | i2c->wbuf, -+ ddbwritel(dev, I2C_SPEED_100, i2c->regs + I2C_TIMING); -+ ddbwritel(dev, (i2c->rbuf << 16) | i2c->wbuf, - i2c->regs + I2C_TASKADDRESS); - init_waitqueue_head(&i2c->wq); - -@@ -216,69 +290,94 @@ static int ddb_i2c_init(struct ddb *dev) - /******************************************************************************/ - /******************************************************************************/ - --#if 0 --static void set_table(struct ddb *dev, u32 off, -- dma_addr_t *pbuf, u32 num) -+static void ddb_set_dma_table(struct ddb *dev, struct ddb_dma *dma) - { - u32 i, base; - u64 mem; - -- base = DMA_BASE_ADDRESS_TABLE + off; -- for (i = 0; i < num; i++) { -- mem = pbuf[i]; -- ddbwritel(mem & 0xffffffff, base + i * 8); -- ddbwritel(mem >> 32, base + i * 8 + 4); -+ if (!dma) -+ return; -+ base = DMA_BASE_ADDRESS_TABLE + dma->nr * 0x100; -+ for (i = 0; i < dma->num; i++) { -+ mem = dma->pbuf[i]; -+ ddbwritel(dev, mem & 0xffffffff, base + i * 8); -+ ddbwritel(dev, mem >> 32, base + i * 8 + 4); - } -+ dma->bufreg = (dma->div << 16) | -+ ((dma->num & 0x1f) << 11) | -+ ((dma->size >> 7) & 0x7ff); - } --#endif - --static void ddb_address_table(struct ddb *dev) -+static void ddb_set_dma_tables(struct ddb *dev) - { -- u32 i, j, base; -- u64 mem; -- dma_addr_t *pbuf; -+ u32 i; - -- for (i = 0; i < dev->info->port_num * 2; i++) { -- base = DMA_BASE_ADDRESS_TABLE + i * 0x100; -- pbuf = dev->input[i].pbuf; -- for (j = 0; j < dev->input[i].dma_buf_num; j++) { -- mem = pbuf[j]; -- ddbwritel(mem & 0xffffffff, base + j * 8); -- ddbwritel(mem >> 32, base + j * 8 + 4); -- } -- } -- for (i = 0; i < dev->info->port_num; i++) { -- base = DMA_BASE_ADDRESS_TABLE + 0x800 + i * 0x100; -- pbuf = dev->output[i].pbuf; -- for (j = 0; j < dev->output[i].dma_buf_num; j++) { -- mem = pbuf[j]; -- ddbwritel(mem & 0xffffffff, base + j * 8); -- ddbwritel(mem >> 32, base + j * 8 + 4); -- } -- } -+ for (i = 0; i < dev->info->port_num * 2; i++) -+ ddb_set_dma_table(dev, dev->input[i].dma); -+ for (i = 0; i < dev->info->port_num; i++) -+ ddb_set_dma_table(dev, dev->output[i].dma); - } - --static void io_free(struct pci_dev *pdev, u8 **vbuf, -- dma_addr_t *pbuf, u32 size, int num) -+static void dma_free(struct pci_dev *pdev, struct ddb_dma *dma) - { - int i; - -- for (i = 0; i < num; i++) { -- if (vbuf[i]) { -- pci_free_consistent(pdev, size, vbuf[i], pbuf[i]); -- vbuf[i] = 0; -+ if (!dma) -+ return; -+ for (i = 0; i < dma->num; i++) { -+ if (dma->vbuf[i]) { -+ pci_free_consistent(pdev, dma->size, -+ dma->vbuf[i], dma->pbuf[i]); -+ dma->vbuf[i] = 0; - } - } - } - --static int io_alloc(struct pci_dev *pdev, u8 **vbuf, -- dma_addr_t *pbuf, u32 size, int num) -+static void ddb_redirect_dma(struct ddb *dev, -+ struct ddb_dma *sdma, -+ struct ddb_dma *ddma) -+{ -+ u32 i, base; -+ u64 mem; -+ -+ sdma->bufreg = ddma->bufreg; -+ base = DMA_BASE_ADDRESS_TABLE + sdma->nr * 0x100; -+ for (i = 0; i < ddma->num; i++) { -+ mem = ddma->pbuf[i]; -+ ddbwritel(dev, mem & 0xffffffff, base + i * 8); -+ ddbwritel(dev, mem >> 32, base + i * 8 + 4); -+ } -+} -+ -+static void ddb_unredirect(struct ddb_port *port) -+{ -+ struct ddb_input *ored, *ired; -+ -+ ored = port->output->redirect; -+ ired = port->input[0]->redirect; -+ -+ if (!ored || !ired) -+ return; -+ if (ired->port->output->redirect == port->input[0]) { -+ ired->port->output->redirect = ored; -+ ddb_set_dma_table(port->dev, port->input[0]->dma); -+ ddb_redirect_dma(ored->port->dev, ored->dma, ired->port->output->dma); -+ } else -+ ddb_set_dma_table(ored->port->dev, ored->dma); -+ ored->redirect = ired; -+ port->input[0]->redirect = 0; -+ port->output->redirect = 0; -+} -+ -+static int dma_alloc(struct pci_dev *pdev, struct ddb_dma *dma) - { - int i; - -- for (i = 0; i < num; i++) { -- vbuf[i] = pci_alloc_consistent(pdev, size, &pbuf[i]); -- if (!vbuf[i]) -+ if (!dma) -+ return 0; -+ for (i = 0; i < dma->num; i++) { -+ dma->vbuf[i] = pci_alloc_consistent(pdev, dma->size, &dma->pbuf[i]); -+ if (!dma->vbuf[i]) - return -ENOMEM; - } - return 0; -@@ -293,34 +392,23 @@ static int ddb_buffers_alloc(struct ddb *dev) - port = &dev->port[i]; - switch (port->class) { - case DDB_PORT_TUNER: -- if (io_alloc(dev->pdev, port->input[0]->vbuf, -- port->input[0]->pbuf, -- port->input[0]->dma_buf_size, -- port->input[0]->dma_buf_num) < 0) -+ if (dma_alloc(dev->pdev, port->input[0]->dma) < 0) - return -1; -- if (io_alloc(dev->pdev, port->input[1]->vbuf, -- port->input[1]->pbuf, -- port->input[1]->dma_buf_size, -- port->input[1]->dma_buf_num) < 0) -+ if (dma_alloc(dev->pdev, port->input[1]->dma) < 0) - return -1; - break; - case DDB_PORT_CI: -- if (io_alloc(dev->pdev, port->input[0]->vbuf, -- port->input[0]->pbuf, -- port->input[0]->dma_buf_size, -- port->input[0]->dma_buf_num) < 0) -+ case DDB_PORT_LOOP: -+ if (dma_alloc(dev->pdev, port->input[0]->dma) < 0) - return -1; -- if (io_alloc(dev->pdev, port->output->vbuf, -- port->output->pbuf, -- port->output->dma_buf_size, -- port->output->dma_buf_num) < 0) -+ if (dma_alloc(dev->pdev, port->output->dma) < 0) - return -1; - break; - default: - break; - } - } -- ddb_address_table(dev); -+ ddb_set_dma_tables(dev); - return 0; - } - -@@ -331,18 +419,11 @@ static void ddb_buffers_free(struct ddb *dev) - - for (i = 0; i < dev->info->port_num; i++) { - port = &dev->port[i]; -- io_free(dev->pdev, port->input[0]->vbuf, -- port->input[0]->pbuf, -- port->input[0]->dma_buf_size, -- port->input[0]->dma_buf_num); -- io_free(dev->pdev, port->input[1]->vbuf, -- port->input[1]->pbuf, -- port->input[1]->dma_buf_size, -- port->input[1]->dma_buf_num); -- io_free(dev->pdev, port->output->vbuf, -- port->output->pbuf, -- port->output->dma_buf_size, -- port->output->dma_buf_num); -+ -+ ddb_unredirect(port); -+ dma_free(dev->pdev, port->input[0]->dma); -+ dma_free(dev->pdev, port->input[1]->dma); -+ dma_free(dev->pdev, port->output->dma); - } - } - -@@ -350,90 +431,116 @@ static void ddb_input_start(struct ddb_input *input) - { - struct ddb *dev = input->port->dev; - -- spin_lock_irq(&input->lock); -- input->cbuf = 0; -- input->coff = 0; -+ spin_lock_irq(&input->dma->lock); -+ input->dma->cbuf = 0; -+ input->dma->coff = 0; - - /* reset */ -- ddbwritel(0, TS_INPUT_CONTROL(input->nr)); -- ddbwritel(2, TS_INPUT_CONTROL(input->nr)); -- ddbwritel(0, TS_INPUT_CONTROL(input->nr)); -+ ddbwritel(dev, 0, TS_INPUT_CONTROL(input->nr)); -+ ddbwritel(dev, 2, TS_INPUT_CONTROL(input->nr)); -+ ddbwritel(dev, 0, TS_INPUT_CONTROL(input->nr)); - -- ddbwritel((1 << 16) | -- (input->dma_buf_num << 11) | -- (input->dma_buf_size >> 7), -- DMA_BUFFER_SIZE(input->nr)); -- ddbwritel(0, DMA_BUFFER_ACK(input->nr)); -+ ddbwritel(dev, input->dma->bufreg, DMA_BUFFER_SIZE(input->dma->nr)); -+ ddbwritel(dev, 0, DMA_BUFFER_ACK(input->dma->nr)); - -- ddbwritel(1, DMA_BASE_WRITE); -- ddbwritel(3, DMA_BUFFER_CONTROL(input->nr)); -- ddbwritel(9, TS_INPUT_CONTROL(input->nr)); -- input->running = 1; -- spin_unlock_irq(&input->lock); -+ ddbwritel(dev, 1, DMA_BASE_WRITE); -+ ddbwritel(dev, 3, DMA_BUFFER_CONTROL(input->dma->nr)); -+ ddbwritel(dev, 9, TS_INPUT_CONTROL(input->nr)); -+ input->dma->running = 1; -+ spin_unlock_irq(&input->dma->lock); -+ /* printk(KERN_INFO "input_start %d\n", input->nr); */ - } - - static void ddb_input_stop(struct ddb_input *input) - { - struct ddb *dev = input->port->dev; - -- spin_lock_irq(&input->lock); -- ddbwritel(0, TS_INPUT_CONTROL(input->nr)); -- ddbwritel(0, DMA_BUFFER_CONTROL(input->nr)); -- input->running = 0; -- spin_unlock_irq(&input->lock); -+ spin_lock_irq(&input->dma->lock); -+ ddbwritel(dev, 0, TS_INPUT_CONTROL(input->nr)); -+ ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma->nr)); -+ input->dma->running = 0; -+ spin_unlock_irq(&input->dma->lock); - } - - static void ddb_output_start(struct ddb_output *output) - { - struct ddb *dev = output->port->dev; - -- spin_lock_irq(&output->lock); -- output->cbuf = 0; -- output->coff = 0; -- ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); -- ddbwritel(2, TS_OUTPUT_CONTROL(output->nr)); -- ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); -- ddbwritel(0x3c, TS_OUTPUT_CONTROL(output->nr)); -- ddbwritel((1 << 16) | -- (output->dma_buf_num << 11) | -- (output->dma_buf_size >> 7), -- DMA_BUFFER_SIZE(output->nr + 8)); -- ddbwritel(0, DMA_BUFFER_ACK(output->nr + 8)); -- -- ddbwritel(1, DMA_BASE_READ); -- ddbwritel(3, DMA_BUFFER_CONTROL(output->nr + 8)); -- /* ddbwritel(0xbd, TS_OUTPUT_CONTROL(output->nr)); */ -- ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr)); -- output->running = 1; -- spin_unlock_irq(&output->lock); -+ spin_lock_irq(&output->dma->lock); -+ output->dma->cbuf = 0; -+ output->dma->coff = 0; -+ ddbwritel(dev, 0, TS_OUTPUT_CONTROL(output->nr)); -+ ddbwritel(dev, 2, TS_OUTPUT_CONTROL(output->nr)); -+ ddbwritel(dev, 0, TS_OUTPUT_CONTROL(output->nr)); -+ ddbwritel(dev, 0x3c, TS_OUTPUT_CONTROL(output->nr)); -+ ddbwritel(dev, output->dma->bufreg, DMA_BUFFER_SIZE(output->dma->nr)); -+ ddbwritel(dev, 0, DMA_BUFFER_ACK(output->dma->nr)); -+ -+ ddbwritel(dev, 1, DMA_BASE_READ); -+ ddbwritel(dev, 3, DMA_BUFFER_CONTROL(output->dma->nr)); -+ if (output->port->input[0]->port->class == DDB_PORT_LOOP) -+ ddbwritel(dev, 0x05, TS_OUTPUT_CONTROL(output->nr)); -+ else -+ ddbwritel(dev, 0x1d, TS_OUTPUT_CONTROL(output->nr)); -+ output->dma->running = 1; -+ spin_unlock_irq(&output->dma->lock); -+ /* printk(KERN_INFO "output_start %d\n", output->nr); */ -+} -+ -+#if 0 -+static void ddb_input_start_all(struct ddb_input *input) -+{ -+ struct ddb_input *next; -+ -+ ddb_input_start(input); -+ while ((next = input->redirect) && -+ next != input) { -+ ddb_input_start(next); -+ ddb_output_start(next->port->output); -+ } - } -+#endif - - static void ddb_output_stop(struct ddb_output *output) - { - struct ddb *dev = output->port->dev; - -- spin_lock_irq(&output->lock); -- ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); -- ddbwritel(0, DMA_BUFFER_CONTROL(output->nr + 8)); -- output->running = 0; -- spin_unlock_irq(&output->lock); -+ spin_lock_irq(&output->dma->lock); -+ ddbwritel(dev, 0, TS_OUTPUT_CONTROL(output->nr)); -+ ddbwritel(dev, 0, DMA_BUFFER_CONTROL(output->dma->nr)); -+ output->dma->running = 0; -+ spin_unlock_irq(&output->dma->lock); -+} -+ -+#if 0 -+static void ddb_input_stop_all(struct ddb_input *input) -+{ -+ struct ddb_input *next; -+ -+ ddb_input_stop(input); -+ while ((next = input->redirect) && -+ next != input) { -+ ddb_input_stop(next); -+ ddb_output_stop(next->port->output); -+ } - } -+#endif - - static u32 ddb_output_free(struct ddb_output *output) - { -- u32 idx, off, stat = output->stat; -+ u32 idx, off, stat = output->dma->stat; - s32 diff; - - idx = (stat >> 11) & 0x1f; - off = (stat & 0x7ff) << 7; - -- if (output->cbuf != idx) { -- if ((((output->cbuf + 1) % output->dma_buf_num) == idx) && -- (output->dma_buf_size - output->coff <= 188)) -+ if (output->dma->cbuf != idx) { -+ if ((((output->dma->cbuf + 1) % output->dma->num) == idx) && -+ (output->dma->size - output->dma->coff <= 188)) - return 0; - return 188; - } -- diff = off - output->coff; -+ diff = off - output->dma->coff; - if (diff <= 0 || diff > 188) - return 188; - return 0; -@@ -443,24 +550,24 @@ static ssize_t ddb_output_write(struct ddb_output *output, - const u8 *buf, size_t count) - { - struct ddb *dev = output->port->dev; -- u32 idx, off, stat = output->stat; -+ u32 idx, off, stat = output->dma->stat; - u32 left = count, len; - - idx = (stat >> 11) & 0x1f; - off = (stat & 0x7ff) << 7; - - while (left) { -- len = output->dma_buf_size - output->coff; -- if ((((output->cbuf + 1) % output->dma_buf_num) == idx) && -+ len = output->dma->size - output->dma->coff; -+ if ((((output->dma->cbuf + 1) % output->dma->num) == idx) && - (off == 0)) { - if (len <= 188) - break; - len -= 188; - } -- if (output->cbuf == idx) { -- if (off > output->coff) { -+ if (output->dma->cbuf == idx) { -+ if (off > output->dma->coff) { - #if 1 -- len = off - output->coff; -+ len = off - output->dma->coff; - len -= (len % 188); - if (len <= 188) - -@@ -471,68 +578,146 @@ static ssize_t ddb_output_write(struct ddb_output *output, - } - if (len > left) - len = left; -- if (copy_from_user(output->vbuf[output->cbuf] + output->coff, -+ if (copy_from_user(output->dma->vbuf[output->dma->cbuf] + -+ output->dma->coff, - buf, len)) - return -EIO; -+ /* printk("cfu %d %d %d\n", len, output->cbuf, output->coff); */ - left -= len; - buf += len; -- output->coff += len; -- if (output->coff == output->dma_buf_size) { -- output->coff = 0; -- output->cbuf = ((output->cbuf + 1) % output->dma_buf_num); -+ output->dma->coff += len; -+ if (output->dma->coff == output->dma->size) { -+ output->dma->coff = 0; -+ output->dma->cbuf = ((output->dma->cbuf + 1) % -+ output->dma->num); - } -- ddbwritel((output->cbuf << 11) | (output->coff >> 7), -- DMA_BUFFER_ACK(output->nr + 8)); -+ ddbwritel(dev, (output->dma->cbuf << 11) | (output->dma->coff >> 7), -+ DMA_BUFFER_ACK(output->dma->nr)); - } - return count - left; - } - -+#if 0 -+static u32 ddb_input_free_bytes(struct ddb_input *input) -+{ -+ struct ddb *dev = input->port->dev; -+ u32 idx, off, stat = input->dma->stat; -+ u32 ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(input->dma->nr)); -+ -+ idx = (stat >> 11) & 0x1f; -+ off = (stat & 0x7ff) << 7; -+ -+ if (ctrl & 4) -+ return 0; -+ if (input->dma->cbuf != idx) -+ return 1; -+ return 0; -+} -+ -+static s32 ddb_output_used_bufs(struct ddb_output *output) -+{ -+ u32 idx, off, stat, ctrl; -+ s32 diff; -+ -+ spin_lock_irq(&output->dma->lock); -+ stat = output->dma->stat; -+ ctrl = output->dma->ctrl; -+ spin_unlock_irq(&output->dma->lock); -+ -+ idx = (stat >> 11) & 0x1f; -+ off = (stat & 0x7ff) << 7; -+ -+ if (ctrl & 4) -+ return 0; -+ diff = output->dma->cbuf - idx; -+ if (diff == 0 && off < output->dma->coff) -+ return 0; -+ if (diff <= 0) -+ diff += output->dma->num; -+ return diff; -+} -+ -+static s32 ddb_input_free_bufs(struct ddb_input *input) -+{ -+ u32 idx, off, stat, ctrl; -+ s32 free; -+ -+ spin_lock_irq(&input->dma->lock); -+ ctrl = input->dma->ctrl; -+ stat = input->dma->stat; -+ spin_unlock_irq(&input->dma->lock); -+ if (ctrl & 4) -+ return 0; -+ idx = (stat >> 11) & 0x1f; -+ off = (stat & 0x7ff) << 7; -+ free = input->dma->cbuf - idx; -+ if (free == 0 && off < input->dma->coff) -+ return 0; -+ if (free <= 0) -+ free += input->dma->num; -+ return free - 1; -+} -+ -+static u32 ddb_output_ok(struct ddb_output *output) -+{ -+ struct ddb_input *input = output->port->input[0]; -+ s32 diff; -+ -+ diff = ddb_input_free_bufs(input) - ddb_output_used_bufs(output); -+ if (diff > 0) -+ return 1; -+ return 0; -+} -+#endif -+ - static u32 ddb_input_avail(struct ddb_input *input) - { - struct ddb *dev = input->port->dev; -- u32 idx, off, stat = input->stat; -- u32 ctrl = ddbreadl(DMA_BUFFER_CONTROL(input->nr)); -+ u32 idx, off, stat = input->dma->stat; -+ u32 ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(input->dma->nr)); - - idx = (stat >> 11) & 0x1f; - off = (stat & 0x7ff) << 7; - - if (ctrl & 4) { - printk(KERN_ERR "IA %d %d %08x\n", idx, off, ctrl); -- ddbwritel(input->stat, DMA_BUFFER_ACK(input->nr)); -+ ddbwritel(dev, stat, DMA_BUFFER_ACK(input->dma->nr)); - return 0; - } -- if (input->cbuf != idx) -+ if (input->dma->cbuf != idx || off < input->dma->coff) - return 188; - return 0; - } - --static ssize_t ddb_input_read(struct ddb_input *input, u8 *buf, size_t count) -+static size_t ddb_input_read(struct ddb_input *input, u8 *buf, size_t count) - { - struct ddb *dev = input->port->dev; - u32 left = count; -- u32 idx, free, stat = input->stat; -+ u32 idx, off, free, stat = input->dma->stat; - int ret; - - idx = (stat >> 11) & 0x1f; -+ off = (stat & 0x7ff) << 7; - - while (left) { -- if (input->cbuf == idx) -+ if (input->dma->cbuf == idx) - return count - left; -- free = input->dma_buf_size - input->coff; -+ free = input->dma->size - input->dma->coff; - if (free > left) - free = left; -- ret = copy_to_user(buf, input->vbuf[input->cbuf] + -- input->coff, free); -+ ret = copy_to_user(buf, input->dma->vbuf[input->dma->cbuf] + -+ input->dma->coff, free); - if (ret) - return -EFAULT; -- input->coff += free; -- if (input->coff == input->dma_buf_size) { -- input->coff = 0; -- input->cbuf = (input->cbuf+1) % input->dma_buf_num; -+ input->dma->coff += free; -+ if (input->dma->coff == input->dma->size) { -+ input->dma->coff = 0; -+ input->dma->cbuf = (input->dma->cbuf+1) % -+ input->dma->num; - } - left -= free; -- ddbwritel((input->cbuf << 11) | (input->coff >> 7), -- DMA_BUFFER_ACK(input->nr)); -+ ddbwritel(dev, (input->dma->cbuf << 11) | (input->dma->coff >> 7), -+ DMA_BUFFER_ACK(input->dma->nr)); - } - return count; - } -@@ -554,7 +739,7 @@ static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe) - } - #endif - --static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) -+static int locked_gate_ctrl(struct dvb_frontend *fe, int enable) - { - struct ddb_input *input = fe->sec_priv; - struct ddb_port *port = input->port; -@@ -562,9 +747,9 @@ static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) - - if (enable) { - mutex_lock(&port->i2c_gate_lock); -- status = input->gate_ctrl(fe, 1); -+ status = input->dvb.gate_ctrl(fe, 1); - } else { -- status = input->gate_ctrl(fe, 0); -+ status = input->dvb.gate_ctrl(fe, 0); - mutex_unlock(&port->i2c_gate_lock); - } - return status; -@@ -577,18 +762,88 @@ static int demod_attach_drxk(struct ddb_input *input) - struct drxk_config config; - - memset(&config, 0, sizeof(config)); -- config.microcode_name = "drxk_a3.mc"; -- config.qam_demod_parameter_count = 4; - config.adr = 0x29 + (input->nr & 1); -+ config.microcode_name = "drxk_a3.mc"; - -- fe = input->fe = dvb_attach(drxk_attach, &config, i2c); -- if (!input->fe) { -+#ifdef USE_API3 -+ fe = input->dvb.fe = dvb_attach(drxk_attach, &config, i2c, &input->dvb.fe2); -+#else -+ fe = input->dvb.fe = dvb_attach(drxk_attach, &config, i2c); -+#endif -+ if (!input->dvb.fe) { - printk(KERN_ERR "No DRXK found!\n"); - return -ENODEV; - } - fe->sec_priv = input; -- input->gate_ctrl = fe->ops.i2c_gate_ctrl; -- fe->ops.i2c_gate_ctrl = drxk_gate_ctrl; -+ input->dvb.gate_ctrl = fe->ops.i2c_gate_ctrl; -+ fe->ops.i2c_gate_ctrl = locked_gate_ctrl; -+ return 0; -+} -+ -+#if 0 -+struct stv0367_config stv0367_0 = { -+ .demod_address = 0x1f, -+ .xtal = 27000000, -+ .if_khz = 5000, -+ .if_iq_mode = FE_TER_NORMAL_IF_TUNER, -+ .ts_mode = STV0367_SERIAL_PUNCT_CLOCK, -+ .clk_pol = STV0367_RISINGEDGE_CLOCK, -+}; -+ -+struct stv0367_config stv0367_1 = { -+ .demod_address = 0x1e, -+ .xtal = 27000000, -+ .if_khz = 5000, -+ .if_iq_mode = FE_TER_NORMAL_IF_TUNER, -+ .ts_mode = STV0367_SERIAL_PUNCT_CLOCK, -+ .clk_pol = STV0367_RISINGEDGE_CLOCK, -+}; -+ -+ -+static int demod_attach_stv0367(struct ddb_input *input) -+{ -+ struct i2c_adapter *i2c = &input->port->i2c->adap; -+ struct dvb_frontend *fe; -+ -+ fe = input->dvb.fe = dvb_attach(stv0367ter_attach, -+ (input->nr & 1) ? &stv0367_1 : &stv0367_0, -+ i2c); -+ if (!input->dvb.fe) { -+ printk(KERN_ERR "No stv0367 found!\n"); -+ return -ENODEV; -+ } -+ fe->sec_priv = input; -+ input->dvb.gate_ctrl = fe->ops.i2c_gate_ctrl; -+ fe->ops.i2c_gate_ctrl = locked_gate_ctrl; -+ return 0; -+} -+#endif -+ -+struct stv0367_cfg stv0367dd_0 = { -+ .adr = 0x1f, -+ .xtal = 27000000, -+}; -+ -+struct stv0367_cfg stv0367dd_1 = { -+ .adr = 0x1e, -+ .xtal = 27000000, -+}; -+ -+static int demod_attach_stv0367dd(struct ddb_input *input) -+{ -+ struct i2c_adapter *i2c = &input->port->i2c->adap; -+ struct dvb_frontend *fe; -+ -+ fe = input->dvb.fe = dvb_attach(stv0367_attach, i2c, -+ (input->nr & 1) ? &stv0367dd_1 : &stv0367dd_0, -+ &input->dvb.fe2); -+ if (!input->dvb.fe) { -+ printk(KERN_ERR "No stv0367 found!\n"); -+ return -ENODEV; -+ } -+ fe->sec_priv = input; -+ input->dvb.gate_ctrl = fe->ops.i2c_gate_ctrl; -+ fe->ops.i2c_gate_ctrl = locked_gate_ctrl; - return 0; - } - -@@ -597,18 +852,57 @@ static int tuner_attach_tda18271(struct ddb_input *input) - struct i2c_adapter *i2c = &input->port->i2c->adap; - struct dvb_frontend *fe; - -- if (input->fe->ops.i2c_gate_ctrl) -- input->fe->ops.i2c_gate_ctrl(input->fe, 1); -- fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60); -+ if (input->dvb.fe->ops.i2c_gate_ctrl) -+ input->dvb.fe->ops.i2c_gate_ctrl(input->dvb.fe, 1); -+ fe = dvb_attach(tda18271c2dd_attach, input->dvb.fe, i2c, 0x60); -+ if (input->dvb.fe->ops.i2c_gate_ctrl) -+ input->dvb.fe->ops.i2c_gate_ctrl(input->dvb.fe, 0); - if (!fe) { - printk(KERN_ERR "No TDA18271 found!\n"); - return -ENODEV; - } -- if (input->fe->ops.i2c_gate_ctrl) -- input->fe->ops.i2c_gate_ctrl(input->fe, 0); - return 0; - } - -+static int tuner_attach_tda18212dd(struct ddb_input *input) -+{ -+ struct i2c_adapter *i2c = &input->port->i2c->adap; -+ struct dvb_frontend *fe; -+ -+ fe = dvb_attach(tda18212dd_attach, input->dvb.fe, i2c, -+ (input->nr & 1) ? 0x63 : 0x60); -+ if (!fe) { -+ printk(KERN_ERR "No TDA18212 found!\n"); -+ return -ENODEV; -+ } -+ return 0; -+} -+ -+#if 0 -+struct tda18212_config tda18212_0 = { -+ .i2c_address = 0x60, -+}; -+ -+struct tda18212_config tda18212_1 = { -+ .i2c_address = 0x63, -+}; -+ -+static int tuner_attach_tda18212(struct ddb_input *input) -+{ -+ struct i2c_adapter *i2c = &input->port->i2c->adap; -+ struct dvb_frontend *fe; -+ struct tda18212_config *cfg; -+ -+ cfg = (input->nr & 1) ? &tda18212_1 : &tda18212_0; -+ fe = dvb_attach(tda18212_attach, input->dvb.fe, i2c, cfg); -+ if (!fe) { -+ printk(KERN_ERR "No TDA18212 found!\n"); -+ return -ENODEV; -+ } -+ return 0; -+} -+#endif -+ - /******************************************************************************/ - /******************************************************************************/ - /******************************************************************************/ -@@ -668,14 +962,14 @@ static int demod_attach_stv0900(struct ddb_input *input, int type) - struct i2c_adapter *i2c = &input->port->i2c->adap; - struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; - -- input->fe = dvb_attach(stv090x_attach, feconf, i2c, -+ input->dvb.fe = dvb_attach(stv090x_attach, feconf, i2c, - (input->nr & 1) ? STV090x_DEMODULATOR_1 - : STV090x_DEMODULATOR_0); -- if (!input->fe) { -+ if (!input->dvb.fe) { - printk(KERN_ERR "No STV0900 found!\n"); - return -ENODEV; - } -- if (!dvb_attach(lnbh24_attach, input->fe, i2c, 0, -+ if (!dvb_attach(lnbh24_attach, input->dvb.fe, i2c, 0, - 0, (input->nr & 1) ? - (0x09 - type) : (0x0b - type))) { - printk(KERN_ERR "No LNBH24 found!\n"); -@@ -692,7 +986,7 @@ static int tuner_attach_stv6110(struct ddb_input *input, int type) - &stv6110b : &stv6110a; - struct stv6110x_devctl *ctl; - -- ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c); -+ ctl = dvb_attach(stv6110x_attach, input->dvb.fe, tunerconf, i2c); - if (!ctl) { - printk(KERN_ERR "No STV6110X found!\n"); - return -ENODEV; -@@ -760,10 +1054,10 @@ static int start_feed(struct dvb_demux_feed *dvbdmxfeed) - struct dvb_demux *dvbdmx = dvbdmxfeed->demux; - struct ddb_input *input = dvbdmx->priv; - -- if (!input->users) -+ if (!input->dvb.users) - ddb_input_start(input); - -- return ++input->users; -+ return ++input->dvb.users; - } - - static int stop_feed(struct dvb_demux_feed *dvbdmxfeed) -@@ -771,8 +1065,8 @@ static int stop_feed(struct dvb_demux_feed *dvbdmxfeed) - struct dvb_demux *dvbdmx = dvbdmxfeed->demux; - struct ddb_input *input = dvbdmx->priv; - -- if (--input->users) -- return input->users; -+ if (--input->dvb.users) -+ return input->dvb.users; - - ddb_input_stop(input); - return 0; -@@ -781,116 +1075,200 @@ static int stop_feed(struct dvb_demux_feed *dvbdmxfeed) - - static void dvb_input_detach(struct ddb_input *input) - { -- struct dvb_adapter *adap = &input->adap; -- struct dvb_demux *dvbdemux = &input->demux; -+ struct dvb_demux *dvbdemux = &input->dvb.demux; - -- switch (input->attached) { -+ switch (input->dvb.attached) { -+ case 6: -+ if (input->dvb.fe2) -+ dvb_unregister_frontend(input->dvb.fe2); -+ if (input->dvb.fe) -+ dvb_unregister_frontend(input->dvb.fe); - case 5: -- if (input->fe2) -- dvb_unregister_frontend(input->fe2); -- if (input->fe) { -- dvb_unregister_frontend(input->fe); -- dvb_frontend_detach(input->fe); -- input->fe = NULL; -- } -+ dvb_frontend_detach(input->dvb.fe); -+ input->dvb.fe = NULL; - case 4: -- dvb_net_release(&input->dvbnet); -- -+ dvb_net_release(&input->dvb.dvbnet); - case 3: - dvbdemux->dmx.close(&dvbdemux->dmx); - dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, -- &input->hw_frontend); -+ &input->dvb.hw_frontend); - dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, -- &input->mem_frontend); -- dvb_dmxdev_release(&input->dmxdev); -- -+ &input->dvb.mem_frontend); -+ dvb_dmxdev_release(&input->dvb.dmxdev); - case 2: -- dvb_dmx_release(&input->demux); -- -+ dvb_dmx_release(&input->dvb.demux); - case 1: -- dvb_unregister_adapter(adap); -+ break; - } -- input->attached = 0; -+ input->dvb.attached = 0; - } - -+static int dvb_register_adapters(struct ddb *dev) -+{ -+ int i, ret = 0; -+ struct ddb_port *port; -+ struct dvb_adapter *adap; -+ -+ if (adapter_alloc == 3) { -+ port = &dev->port[0]; -+ adap = port->input[0]->dvb.adap; -+ ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE, -+ &port->dev->pdev->dev, -+ adapter_nr); -+ if (ret < 0) -+ return ret; -+ port->input[0]->dvb.adap_registered = 1; -+ for (i = 0; i < dev->info->port_num; i++) { -+ port = &dev->port[i]; -+ port->input[0]->dvb.adap = adap; -+ port->input[1]->dvb.adap = adap; -+ } -+ return 0; -+ } -+ -+ for (i = 0; i < dev->info->port_num; i++) { -+ port = &dev->port[i]; -+ switch (port->class) { -+ case DDB_PORT_TUNER: -+ adap = port->input[0]->dvb.adap; -+ ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE, -+ &port->dev->pdev->dev, -+ adapter_nr); -+ if (ret < 0) -+ return ret; -+ port->input[0]->dvb.adap_registered = 1; -+ -+ if (adapter_alloc > 0) { -+ port->input[1]->dvb.adap = port->input[0]->dvb.adap; -+ break; -+ } -+ adap = port->input[1]->dvb.adap; -+ ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE, -+ &port->dev->pdev->dev, -+ adapter_nr); -+ if (ret < 0) -+ return ret; -+ port->input[1]->dvb.adap_registered = 1; -+ break; -+ -+ case DDB_PORT_CI: -+ case DDB_PORT_LOOP: -+ adap = port->input[0]->dvb.adap; -+ ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE, -+ &port->dev->pdev->dev, -+ adapter_nr); -+ if (ret < 0) -+ return ret; -+ port->input[0]->dvb.adap_registered = 1; -+ break; -+ default: -+ if (adapter_alloc < 2) -+ break; -+ adap = port->input[0]->dvb.adap; -+ ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE, -+ &port->dev->pdev->dev, -+ adapter_nr); -+ if (ret < 0) -+ return ret; -+ port->input[0]->dvb.adap_registered = 1; -+ break; -+ } -+ } -+ return ret; -+} -+ -+static void dvb_unregister_adapters(struct ddb *dev) -+{ -+ int i; -+ struct ddb_port *port; -+ struct ddb_input *input; -+ -+ for (i = 0; i < dev->info->port_num; i++) { -+ port = &dev->port[i]; -+ -+ input = port->input[0]; -+ if (input->dvb.adap_registered) -+ dvb_unregister_adapter(input->dvb.adap); -+ input->dvb.adap_registered = 0; -+ -+ input = port->input[1]; -+ if (input->dvb.adap_registered) -+ dvb_unregister_adapter(input->dvb.adap); -+ input->dvb.adap_registered = 0; -+ } -+} -+ -+ - static int dvb_input_attach(struct ddb_input *input) - { -- int ret; -+ int ret = 0; - struct ddb_port *port = input->port; -- struct dvb_adapter *adap = &input->adap; -- struct dvb_demux *dvbdemux = &input->demux; -- -- ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE, -- &input->port->dev->pdev->dev, -- adapter_nr); -- if (ret < 0) { -- printk(KERN_ERR "ddbridge: Could not register adapter." -- "Check if you enabled enough adapters in dvb-core!\n"); -- return ret; -- } -- input->attached = 1; -+ struct dvb_adapter *adap = input->dvb.adap; -+ struct dvb_demux *dvbdemux = &input->dvb.demux; -+ -+ input->dvb.attached = 1; - - ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux", - start_feed, - stop_feed, input); - if (ret < 0) - return ret; -- input->attached = 2; -+ input->dvb.attached = 2; - -- ret = my_dvb_dmxdev_ts_card_init(&input->dmxdev, &input->demux, -- &input->hw_frontend, -- &input->mem_frontend, adap); -+ ret = my_dvb_dmxdev_ts_card_init(&input->dvb.dmxdev, -+ &input->dvb.demux, -+ &input->dvb.hw_frontend, -+ &input->dvb.mem_frontend, adap); - if (ret < 0) - return ret; -- input->attached = 3; -+ input->dvb.attached = 3; - -- ret = dvb_net_init(adap, &input->dvbnet, input->dmxdev.demux); -+ ret = dvb_net_init(adap, &input->dvb.dvbnet, input->dvb.dmxdev.demux); - if (ret < 0) - return ret; -- input->attached = 4; -+ input->dvb.attached = 4; - -- input->fe = 0; -+ input->dvb.fe = 0; - switch (port->type) { - case DDB_TUNER_DVBS_ST: - if (demod_attach_stv0900(input, 0) < 0) - return -ENODEV; - if (tuner_attach_stv6110(input, 0) < 0) - return -ENODEV; -- if (input->fe) { -- if (dvb_register_frontend(adap, input->fe) < 0) -- return -ENODEV; -- } - break; - case DDB_TUNER_DVBS_ST_AA: - if (demod_attach_stv0900(input, 1) < 0) - return -ENODEV; - if (tuner_attach_stv6110(input, 1) < 0) - return -ENODEV; -- if (input->fe) { -- if (dvb_register_frontend(adap, input->fe) < 0) -- return -ENODEV; -- } - break; - case DDB_TUNER_DVBCT_TR: - if (demod_attach_drxk(input) < 0) - return -ENODEV; - if (tuner_attach_tda18271(input) < 0) - return -ENODEV; -- if (input->fe) { -- if (dvb_register_frontend(adap, input->fe) < 0) -- return -ENODEV; -- } -- if (input->fe2) { -- if (dvb_register_frontend(adap, input->fe2) < 0) -- return -ENODEV; -- input->fe2->tuner_priv = input->fe->tuner_priv; -- memcpy(&input->fe2->ops.tuner_ops, -- &input->fe->ops.tuner_ops, -- sizeof(struct dvb_tuner_ops)); -- } - break; -+ case DDB_TUNER_DVBCT_ST: -+ if (demod_attach_stv0367dd(input) < 0) -+ return -ENODEV; -+ if (tuner_attach_tda18212dd(input) < 0) -+ return -ENODEV; -+ break; -+ } -+ input->dvb.attached = 5; -+ if (input->dvb.fe) { -+ if (dvb_register_frontend(adap, input->dvb.fe) < 0) -+ return -ENODEV; - } -- input->attached = 5; -+ if (input->dvb.fe2) { -+ if (dvb_register_frontend(adap, input->dvb.fe2) < 0) -+ return -ENODEV; -+ input->dvb.fe2->tuner_priv = input->dvb.fe->tuner_priv; -+ memcpy(&input->dvb.fe2->ops.tuner_ops, -+ &input->dvb.fe->ops.tuner_ops, -+ sizeof(struct dvb_tuner_ops)); -+ } -+ input->dvb.attached = 6; - return 0; - } - -@@ -910,7 +1288,8 @@ static ssize_t ts_write(struct file *file, const char *buf, - if (file->f_flags & O_NONBLOCK) - break; - if (wait_event_interruptible( -- output->wq, ddb_output_free(output) >= 188) < 0) -+ output->dma->wq, -+ ddb_output_free(output) >= 188) < 0) - break; - } - stat = ddb_output_write(output, buf, left); -@@ -937,7 +1316,7 @@ static ssize_t ts_read(struct file *file, char *buf, - if (file->f_flags & O_NONBLOCK) - break; - if (wait_event_interruptible( -- input->wq, ddb_input_avail(input) >= 188) < 0) -+ input->dma->wq, ddb_input_avail(input) >= 188) < 0) - break; - } - read = ddb_input_read(input, buf, left); -@@ -970,21 +1349,53 @@ static unsigned int ts_poll(struct file *file, poll_table *wait) - return mask; - } - --static const struct file_operations ci_fops = { -- .owner = THIS_MODULE, -- .read = ts_read, -- .write = ts_write, -- .open = dvb_generic_open, -- .release = dvb_generic_release, -- .poll = ts_poll, -- .mmap = 0, --}; -- -+#if 0 -+static int ts_release(struct inode *inode, struct file *file) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ddb_output *output = dvbdev->priv; -+ struct ddb_input *input = output->port->input[0]; -+ -+ -+ return dvb_generic_release(inode, file); -+} -+ -+static unsigned int ts_open(struct inode *inode, struct file *file) -+{ -+ int err; -+ struct dvb_device *dvbdev = file->private_data; -+ struct ddb_output *output = dvbdev->priv; -+ struct ddb_input *input = output->port->input[0]; -+ -+ err = dvb_generic_open(inode, file); -+ if (err < 0) -+ return err; -+ -+#if 0 -+ if ((file->f_flags & O_ACCMODE) == O_RDONLY) -+ ddb_input_start(input); -+ else -+ ddb_output_start(output); -+#endif -+ return err; -+} -+#endif -+ -+static const struct file_operations ci_fops = { -+ .owner = THIS_MODULE, -+ .read = ts_read, -+ .write = ts_write, -+ .open = dvb_generic_open, -+ .release = dvb_generic_release, -+ .poll = ts_poll, -+ .mmap = 0, -+}; -+ - static struct dvb_device dvbdev_ci = { - .priv = 0, -- .readers = -1, -- .writers = -1, -- .users = -1, -+ .readers = 1, -+ .writers = 1, -+ .users = 2, - .fops = &ci_fops, - }; - -@@ -992,53 +1403,297 @@ static struct dvb_device dvbdev_ci = { - /****************************************************************************/ - /****************************************************************************/ - -+static int set_redirect(u32 i, u32 p) -+{ -+ struct ddb *idev = ddbs[(i >> 4) & 0x1f]; -+ struct ddb_input *input; -+ struct ddb *pdev = ddbs[(p >> 4) & 0x1f]; -+ struct ddb_port *port; -+ -+ if (!idev || !pdev) -+ return -EINVAL; -+ -+ port = &pdev->port[p & 3]; -+ if (port->class != DDB_PORT_CI && port->class != DDB_PORT_LOOP) -+ return -EINVAL; -+ -+ ddb_unredirect(port); -+ if (i == 8) -+ return 0; -+ input = &idev->input[i & 7]; -+ if (input->port->class != DDB_PORT_TUNER) -+ port->input[0]->redirect = input->redirect; -+ else -+ port->input[0]->redirect = input; -+ input->redirect = port->input[0]; -+ port->output->redirect = input; -+ -+ ddb_redirect_dma(input->port->dev, input->dma, port->output->dma); -+ return 0; -+} -+ -+static void input_write_output(struct ddb_input *input, -+ struct ddb_output *output) -+{ -+ ddbwritel(output->port->dev, -+ input->dma->stat, DMA_BUFFER_ACK(output->dma->nr)); -+} -+ -+static void output_ack_input(struct ddb_output *output, -+ struct ddb_input *input) -+{ -+ ddbwritel(input->port->dev, -+ output->dma->stat, DMA_BUFFER_ACK(input->dma->nr)); -+} -+ -+static void input_write_dvb(struct ddb_input *input, struct ddb_dvb *dvb) -+{ -+ struct ddb_dma *dma = input->dma; -+ struct ddb *dev = input->port->dev; -+ -+ if (4 & ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr))) -+ printk(KERN_ERR "Overflow dma %d\n", dma->nr); -+ while (dma->cbuf != ((dma->stat >> 11) & 0x1f) -+ || (4 & ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr)))) { -+ dvb_dmx_swfilter_packets(&dvb->demux, -+ dma->vbuf[dma->cbuf], -+ dma->size / 188); -+ dma->cbuf = (dma->cbuf + 1) % dma->num; -+ ddbwritel(dev, (dma->cbuf << 11), DMA_BUFFER_ACK(dma->nr)); -+ dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); -+ } -+} -+ - static void input_tasklet(unsigned long data) - { - struct ddb_input *input = (struct ddb_input *) data; -+ struct ddb_dma *dma = input->dma; - struct ddb *dev = input->port->dev; - -- spin_lock(&input->lock); -- if (!input->running) { -- spin_unlock(&input->lock); -+ spin_lock(&dma->lock); -+ if (!dma->running) { -+ spin_unlock(&dma->lock); - return; - } -- input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); -+ dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); - - if (input->port->class == DDB_PORT_TUNER) { -- if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr))) -- printk(KERN_ERR "Overflow input %d\n", input->nr); -- while (input->cbuf != ((input->stat >> 11) & 0x1f) -- || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) { -- dvb_dmx_swfilter_packets(&input->demux, -- input->vbuf[input->cbuf], -- input->dma_buf_size / 188); -- -- input->cbuf = (input->cbuf + 1) % input->dma_buf_num; -- ddbwritel((input->cbuf << 11), -- DMA_BUFFER_ACK(input->nr)); -- input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); -- } -+ if (input->redirect) -+ input_write_output(input, -+ input->redirect->port->output); -+ else -+ input_write_dvb(input, &input->dvb); -+ } -+ if (input->port->class == DDB_PORT_CI || -+ input->port->class == DDB_PORT_LOOP) { -+ if (input->redirect) { -+ if (input->redirect->port->class == DDB_PORT_TUNER) -+ input_write_dvb(input, &input->redirect->dvb); -+ else -+ input_write_output(input, -+ input->redirect->port->output); -+ } else -+ wake_up(&dma->wq); - } -- if (input->port->class == DDB_PORT_CI) -- wake_up(&input->wq); -- spin_unlock(&input->lock); -+ spin_unlock(&dma->lock); - } - - static void output_tasklet(unsigned long data) - { - struct ddb_output *output = (struct ddb_output *) data; -+ struct ddb_dma *dma = output->dma; - struct ddb *dev = output->port->dev; - -- spin_lock(&output->lock); -- if (!output->running) { -- spin_unlock(&output->lock); -+ spin_lock(&dma->lock); -+ if (!dma->running) { -+ spin_unlock(&dma->lock); - return; - } -- output->stat = ddbreadl(DMA_BUFFER_CURRENT(output->nr + 8)); -- wake_up(&output->wq); -- spin_unlock(&output->lock); -+ dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); -+ dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr)); -+ if (output->redirect) -+ output_ack_input(output, output->redirect); -+ wake_up(&dma->wq); -+ spin_unlock(&dma->lock); -+} -+ -+#if 0 -+static void io_tasklet(unsigned long data) -+{ -+ struct ddb_dma *dma = (struct ddb_dma *) data; -+ -+ spin_lock(&dma->lock); -+ if (!dma->running) { -+ spin_unlock(&dma->lock); -+ return; -+ } -+ dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); -+ dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr)); -+ if (dma->nr & 8) -+ handle_output((struct ddb_output *) dma->io); -+ else -+ handle_input((struct ddb_input *) dma->io); -+ wake_up(&dma->wq); -+ spin_unlock(&dma->lock); -+} -+#endif -+ -+/****************************************************************************/ -+/****************************************************************************/ -+/****************************************************************************/ -+ -+static int wait_ci_ready(struct ddb_ci *ci) -+{ -+ u32 count = 100; -+ -+ do { -+ if (ddbreadl(ci->port->dev, -+ CI_CONTROL(ci->nr)) & CI_READY) -+ break; -+ msleep(1); -+ if ((--count) == 0) -+ return -1; -+ } while (1); -+ return 0; -+} -+ -+static int read_attribute_mem(struct dvb_ca_en50221 *ca, -+ int slot, int address) -+{ -+ struct ddb_ci *ci = ca->data; -+ u32 val, off = (address >> 1) & (CI_BUFFER_SIZE-1); -+ -+ if (address > CI_BUFFER_SIZE) -+ return -1; -+ ddbwritel(ci->port->dev, CI_READ_CMD | (1 << 16) | address, -+ CI_DO_READ_ATTRIBUTES(ci->nr)); -+ wait_ci_ready(ci); -+ val = 0xff & ddbreadl(ci->port->dev, CI_BUFFER(ci->nr) + off); -+ /* printk("%04x: %02x\n", address, val); */ -+ return val; -+} -+ -+static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, -+ int address, u8 value) -+{ -+ struct ddb_ci *ci = ca->data; -+ -+ ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address, -+ CI_DO_ATTRIBUTE_RW(ci->nr)); -+ wait_ci_ready(ci); -+ return 0; -+} -+ -+static int read_cam_control(struct dvb_ca_en50221 *ca, -+ int slot, u8 address) -+{ -+ u32 count = 100; -+ struct ddb_ci *ci = ca->data; -+ u32 res; -+ -+ ddbwritel(ci->port->dev, CI_READ_CMD | address, -+ CI_DO_IO_RW(ci->nr)); -+ do { -+ res = ddbreadl(ci->port->dev, CI_READDATA(ci->nr)); -+ if (res & CI_READY) -+ break; -+ msleep(1); -+ if ((--count) == 0) -+ return -1; -+ } while (1); -+ return 0xff & res; -+} -+ -+static int write_cam_control(struct dvb_ca_en50221 *ca, int slot, -+ u8 address, u8 value) -+{ -+ struct ddb_ci *ci = ca->data; -+ -+ ddbwritel(ci->port->dev, CI_WRITE_CMD | (value << 16) | address, -+ CI_DO_IO_RW(ci->nr)); -+ wait_ci_ready(ci); -+ return 0; -+} -+ -+static int slot_reset(struct dvb_ca_en50221 *ca, int slot) -+{ -+ struct ddb_ci *ci = ca->data; -+ -+ printk(KERN_INFO "slot reset %d\n", ci->nr); -+ ddbwritel(ci->port->dev, CI_POWER_ON, -+ CI_CONTROL(ci->nr)); -+ msleep(300); -+ ddbwritel(ci->port->dev, CI_POWER_ON | CI_RESET_CAM, -+ CI_CONTROL(ci->nr)); -+ ddbwritel(ci->port->dev, CI_ENABLE | CI_POWER_ON | CI_RESET_CAM, -+ CI_CONTROL(ci->nr)); -+ udelay(20); -+ ddbwritel(ci->port->dev, CI_ENABLE | CI_POWER_ON, -+ CI_CONTROL(ci->nr)); -+ return 0; -+} -+ -+static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot) -+{ -+ struct ddb_ci *ci = ca->data; -+ -+ printk(KERN_INFO "slot shutdown\n"); -+ ddbwritel(ci->port->dev, 0, CI_CONTROL(ci->nr)); -+ return 0; -+} -+ -+static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot) -+{ -+ struct ddb_ci *ci = ca->data; -+ u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr)); -+ -+ ddbwritel(ci->port->dev, val | CI_BYPASS_DISABLE, -+ CI_CONTROL(ci->nr)); -+ return 0; -+} -+ -+static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open) -+{ -+ struct ddb_ci *ci = ca->data; -+ u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr)); -+ int stat = 0; -+ -+ if (val & CI_CAM_DETECT) -+ stat |= DVB_CA_EN50221_POLL_CAM_PRESENT; -+ if (val & CI_CAM_READY) -+ stat |= DVB_CA_EN50221_POLL_CAM_READY; -+ return stat; - } - -+static struct dvb_ca_en50221 en_templ = { -+ .read_attribute_mem = read_attribute_mem, -+ .write_attribute_mem = write_attribute_mem, -+ .read_cam_control = read_cam_control, -+ .write_cam_control = write_cam_control, -+ .slot_reset = slot_reset, -+ .slot_shutdown = slot_shutdown, -+ .slot_ts_enable = slot_ts_enable, -+ .poll_slot_status = poll_slot_status, -+}; -+ -+static void ci_attach(struct ddb_port *port) -+{ -+ struct ddb_ci *ci = 0; -+ -+ ci = kzalloc(sizeof(*ci), GFP_KERNEL); -+ if (!ci) -+ return; -+ memcpy(&ci->en, &en_templ, sizeof(en_templ)); -+ ci->en.data = ci; -+ port->en = &ci->en; -+ ci->port = port; -+ ci->nr = port->nr - 2; -+} -+ -+/****************************************************************************/ -+/****************************************************************************/ -+/****************************************************************************/ -+ - - struct cxd2099_cfg cxd_cfg = { - .bitrate = 62000, -@@ -1049,28 +1704,22 @@ struct cxd2099_cfg cxd_cfg = { - - static int ddb_ci_attach(struct ddb_port *port) - { -- int ret; -- -- ret = dvb_register_adapter(&port->output->adap, -- "DDBridge", -- THIS_MODULE, -- &port->dev->pdev->dev, -- adapter_nr); -- if (ret < 0) -- return ret; -- port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap); -- if (!port->en) { -- dvb_unregister_adapter(&port->output->adap); -- return -ENODEV; -+ if (port->type == DDB_CI_EXTERNAL_SONY) { -+ port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap); -+ if (!port->en) -+ return -ENODEV; -+ dvb_ca_en50221_init(port->input[0]->dvb.adap, -+ port->en, 0, 1); - } -- ddb_input_start(port->input[0]); -- ddb_output_start(port->output); -- dvb_ca_en50221_init(&port->output->adap, -- port->en, 0, 1); -- ret = dvb_register_device(&port->output->adap, &port->output->dev, -- &dvbdev_ci, (void *) port->output, -- DVB_DEVICE_SEC); -- return ret; -+#if 1 -+ if (port->type == DDB_CI_INTERNAL) { -+ ci_attach(port); -+ if (!port->en) -+ return -ENODEV; -+ dvb_ca_en50221_init(port->input[0]->dvb.adap, port->en, 0, 1); -+ } -+#endif -+ return 0; - } - - static int ddb_port_attach(struct ddb_port *port) -@@ -1086,6 +1735,15 @@ static int ddb_port_attach(struct ddb_port *port) - break; - case DDB_PORT_CI: - ret = ddb_ci_attach(port); -+ if (ret < 0) -+ break; -+ case DDB_PORT_LOOP: -+ ddb_input_start(port->input[0]); -+ ddb_output_start(port->output); -+ ret = dvb_register_device(port->input[0]->dvb.adap, -+ &port->input[0]->dvb.dev, -+ &dvbdev_ci, (void *) port->output, -+ DVB_DEVICE_SEC); - break; - default: - break; -@@ -1100,6 +1758,10 @@ static int ddb_ports_attach(struct ddb *dev) - int i, ret = 0; - struct ddb_port *port; - -+ ret = dvb_register_adapters(dev); -+ if (ret < 0) -+ return ret; -+ - for (i = 0; i < dev->info->port_num; i++) { - port = &dev->port[i]; - ret = ddb_port_attach(port); -@@ -1122,25 +1784,26 @@ static void ddb_ports_detach(struct ddb *dev) - dvb_input_detach(port->input[1]); - break; - case DDB_PORT_CI: -- if (port->output->dev) -- dvb_unregister_device(port->output->dev); -+ case DDB_PORT_LOOP: -+ if (port->input[0]->dvb.dev) -+ dvb_unregister_device(port->input[0]->dvb.dev); -+ ddb_input_stop(port->input[0]); -+ ddb_output_stop(port->output); - if (port->en) { -- ddb_input_stop(port->input[0]); -- ddb_output_stop(port->output); - dvb_ca_en50221_release(port->en); - kfree(port->en); - port->en = 0; -- dvb_unregister_adapter(&port->output->adap); - } - break; - } - } -+ dvb_unregister_adapters(dev); - } - - /****************************************************************************/ - /****************************************************************************/ - --static int port_has_ci(struct ddb_port *port) -+static int port_has_cxd(struct ddb_port *port) - { - u8 val; - return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1; -@@ -1172,6 +1835,21 @@ static int port_has_drxks(struct ddb_port *port) - return 1; - } - -+static int port_has_stv0367(struct ddb_port *port) -+{ -+ u8 val; -+ -+ if (i2c_read_reg16(&port->i2c->adap, 0x1e, 0xf000, &val) < 0) -+ return 0; -+ if (val != 0x60) -+ return 0; -+ if (i2c_read_reg16(&port->i2c->adap, 0x1f, 0xf000, &val) < 0) -+ return 0; -+ if (val != 0x60) -+ return 0; -+ return 1; -+} -+ - static void ddb_port_probe(struct ddb_port *port) - { - struct ddb *dev = port->dev; -@@ -1179,62 +1857,92 @@ static void ddb_port_probe(struct ddb_port *port) - - port->class = DDB_PORT_NONE; - -- if (port_has_ci(port)) { -+ if (port->nr > 1 && dev->info->type == DDB_OCTOPUS_CI) { -+ modname = "CI internal"; -+ port->class = DDB_PORT_CI; -+ port->type = DDB_CI_INTERNAL; -+ } else if (port_has_cxd(port)) { - modname = "CI"; - port->class = DDB_PORT_CI; -- ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); -+ port->type = DDB_CI_EXTERNAL_SONY; -+ ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING); - } else if (port_has_stv0900(port)) { - modname = "DUAL DVB-S2"; - port->class = DDB_PORT_TUNER; - port->type = DDB_TUNER_DVBS_ST; -- ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); -+ ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING); - } else if (port_has_stv0900_aa(port)) { - modname = "DUAL DVB-S2"; - port->class = DDB_PORT_TUNER; - port->type = DDB_TUNER_DVBS_ST_AA; -- ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); -+ ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING); - } else if (port_has_drxks(port)) { - modname = "DUAL DVB-C/T"; - port->class = DDB_PORT_TUNER; - port->type = DDB_TUNER_DVBCT_TR; -- ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); -+ ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING); -+ } else if (port_has_stv0367(port)) { -+ modname = "DUAL DVB-C/T"; -+ port->class = DDB_PORT_TUNER; -+ port->type = DDB_TUNER_DVBCT_ST; -+ ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING); -+ } else if (port->nr == ts_loop) { -+ modname = "TS LOOP"; -+ port->class = DDB_PORT_LOOP; - } -- printk(KERN_INFO "Port %d (TAB %d): %s\n", -- port->nr, port->nr+1, modname); -+ printk(KERN_INFO "Port %d (TAB %d): %s\n", port->nr, port->nr+1, modname); - } - --static void ddb_input_init(struct ddb_port *port, int nr) -+static void ddb_dma_init(struct ddb_dma *dma, int nr, void *io) -+{ -+ unsigned long priv = (unsigned long) io; -+ -+ dma->io = io; -+ dma->nr = nr; -+ spin_lock_init(&dma->lock); -+ init_waitqueue_head(&dma->wq); -+ if (nr & 8) { -+ tasklet_init(&dma->tasklet, output_tasklet, priv); -+ dma->num = OUTPUT_DMA_BUFS; -+ dma->size = OUTPUT_DMA_SIZE; -+ dma->div = OUTPUT_DMA_IRQ_DIV; -+ } else { -+ tasklet_init(&dma->tasklet, input_tasklet, priv); -+ dma->num = INPUT_DMA_BUFS; -+ dma->size = INPUT_DMA_SIZE; -+ dma->div = INPUT_DMA_IRQ_DIV; -+ } -+} -+ -+static void ddb_input_init(struct ddb_port *port, int nr, int pnr) - { - struct ddb *dev = port->dev; - struct ddb_input *input = &dev->input[nr]; - -+ port->input[pnr] = input; - input->nr = nr; - input->port = port; -- input->dma_buf_num = INPUT_DMA_BUFS; -- input->dma_buf_size = INPUT_DMA_SIZE; -- ddbwritel(0, TS_INPUT_CONTROL(nr)); -- ddbwritel(2, TS_INPUT_CONTROL(nr)); -- ddbwritel(0, TS_INPUT_CONTROL(nr)); -- ddbwritel(0, DMA_BUFFER_ACK(nr)); -- tasklet_init(&input->tasklet, input_tasklet, (unsigned long) input); -- spin_lock_init(&input->lock); -- init_waitqueue_head(&input->wq); -+ input->dma = &dev->dma[nr]; -+ ddb_dma_init(input->dma, nr, (void *) input); -+ ddbwritel(dev, 0, TS_INPUT_CONTROL(nr)); -+ ddbwritel(dev, 2, TS_INPUT_CONTROL(nr)); -+ ddbwritel(dev, 0, TS_INPUT_CONTROL(nr)); -+ ddbwritel(dev, 0, DMA_BUFFER_ACK(input->dma->nr)); -+ input->dvb.adap = &dev->adap[input->nr]; - } - - static void ddb_output_init(struct ddb_port *port, int nr) - { - struct ddb *dev = port->dev; - struct ddb_output *output = &dev->output[nr]; -+ port->output = output; - output->nr = nr; - output->port = port; -- output->dma_buf_num = OUTPUT_DMA_BUFS; -- output->dma_buf_size = OUTPUT_DMA_SIZE; -- -- ddbwritel(0, TS_OUTPUT_CONTROL(nr)); -- ddbwritel(2, TS_OUTPUT_CONTROL(nr)); -- ddbwritel(0, TS_OUTPUT_CONTROL(nr)); -- tasklet_init(&output->tasklet, output_tasklet, (unsigned long) output); -- init_waitqueue_head(&output->wq); -+ output->dma = &dev->dma[nr + 8]; -+ ddb_dma_init(output->dma, nr + 8, (void *) output); -+ ddbwritel(dev, 0, TS_OUTPUT_CONTROL(nr)); -+ ddbwritel(dev, 2, TS_OUTPUT_CONTROL(nr)); -+ ddbwritel(dev, 0, TS_OUTPUT_CONTROL(nr)); - } - - static void ddb_ports_init(struct ddb *dev) -@@ -1247,14 +1955,16 @@ static void ddb_ports_init(struct ddb *dev) - port->dev = dev; - port->nr = i; - port->i2c = &dev->i2c[i]; -- port->input[0] = &dev->input[2 * i]; -- port->input[1] = &dev->input[2 * i + 1]; -- port->output = &dev->output[i]; - - mutex_init(&port->i2c_gate_lock); - ddb_port_probe(port); -- ddb_input_init(port, 2 * i); -- ddb_input_init(port, 2 * i + 1); -+ if (i >= 2 && dev->info->type == DDB_OCTOPUS_CI) { -+ ddb_input_init(port, 2 + i, 0); -+ ddb_input_init(port, 4 + i, 1); -+ } else { -+ ddb_input_init(port, 2 * i, 0); -+ ddb_input_init(port, 2 * i + 1, 1); -+ } - ddb_output_init(port, i); - } - } -@@ -1267,9 +1977,12 @@ static void ddb_ports_release(struct ddb *dev) - for (i = 0; i < dev->info->port_num; i++) { - port = &dev->port[i]; - port->dev = dev; -- tasklet_kill(&port->input[0]->tasklet); -- tasklet_kill(&port->input[1]->tasklet); -- tasklet_kill(&port->output->tasklet); -+ if (port->input[0]) -+ tasklet_kill(&port->input[0]->dma->tasklet); -+ if (port->input[1]) -+ tasklet_kill(&port->input[1]->dma->tasklet); -+ if (port->output) -+ tasklet_kill(&port->output->dma->tasklet); - } - } - -@@ -1288,13 +2001,18 @@ static void irq_handle_i2c(struct ddb *dev, int n) - static irqreturn_t irq_handler(int irq, void *dev_id) - { - struct ddb *dev = (struct ddb *) dev_id; -- u32 s = ddbreadl(INTERRUPT_STATUS); -+ u32 s = ddbreadl(dev, INTERRUPT_STATUS); - - if (!s) - return IRQ_NONE; - - do { -- ddbwritel(s, INTERRUPT_ACK); -+ ddbwritel(dev, s, INTERRUPT_ACK); -+ -+ if (s & 0x0000000f) -+ dev->i2c_irq++; -+ if (s & 0x000fff00) -+ dev->ts_irq++; - - if (s & 0x00000001) - irq_handle_i2c(dev, 0); -@@ -1306,33 +2024,32 @@ static irqreturn_t irq_handler(int irq, void *dev_id) - irq_handle_i2c(dev, 3); - - if (s & 0x00000100) -- tasklet_schedule(&dev->input[0].tasklet); -+ tasklet_schedule(&dev->dma[0].tasklet); - if (s & 0x00000200) -- tasklet_schedule(&dev->input[1].tasklet); -+ tasklet_schedule(&dev->dma[1].tasklet); - if (s & 0x00000400) -- tasklet_schedule(&dev->input[2].tasklet); -+ tasklet_schedule(&dev->dma[2].tasklet); - if (s & 0x00000800) -- tasklet_schedule(&dev->input[3].tasklet); -+ tasklet_schedule(&dev->dma[3].tasklet); - if (s & 0x00001000) -- tasklet_schedule(&dev->input[4].tasklet); -+ tasklet_schedule(&dev->dma[4].tasklet); - if (s & 0x00002000) -- tasklet_schedule(&dev->input[5].tasklet); -+ tasklet_schedule(&dev->dma[5].tasklet); - if (s & 0x00004000) -- tasklet_schedule(&dev->input[6].tasklet); -+ tasklet_schedule(&dev->dma[6].tasklet); - if (s & 0x00008000) -- tasklet_schedule(&dev->input[7].tasklet); -- -+ tasklet_schedule(&dev->dma[7].tasklet); - if (s & 0x00010000) -- tasklet_schedule(&dev->output[0].tasklet); -+ tasklet_schedule(&dev->dma[8].tasklet); - if (s & 0x00020000) -- tasklet_schedule(&dev->output[1].tasklet); -+ tasklet_schedule(&dev->dma[9].tasklet); - if (s & 0x00040000) -- tasklet_schedule(&dev->output[2].tasklet); -+ tasklet_schedule(&dev->dma[10].tasklet); - if (s & 0x00080000) -- tasklet_schedule(&dev->output[3].tasklet); -+ tasklet_schedule(&dev->dma[11].tasklet); - -- /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */ -- } while ((s = ddbreadl(INTERRUPT_STATUS))); -+ /* if (s & 0x000f0000) printk("%08x\n", istat); */ -+ } while ((s = ddbreadl(dev, INTERRUPT_STATUS))); - - return IRQ_HANDLED; - } -@@ -1346,21 +2063,21 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) - u32 data, shift; - - if (wlen > 4) -- ddbwritel(1, SPI_CONTROL); -+ ddbwritel(dev, 1, SPI_CONTROL); - while (wlen > 4) { - /* FIXME: check for big-endian */ - data = swab32(*(u32 *)wbuf); - wbuf += 4; - wlen -= 4; -- ddbwritel(data, SPI_DATA); -- while (ddbreadl(SPI_CONTROL) & 0x0004) -+ ddbwritel(dev, data, SPI_DATA); -+ while (ddbreadl(dev, SPI_CONTROL) & 0x0004) - ; - } - - if (rlen) -- ddbwritel(0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); -+ ddbwritel(dev, 0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); - else -- ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); -+ ddbwritel(dev, 0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); - - data = 0; - shift = ((4 - wlen) * 8); -@@ -1372,33 +2089,33 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) - } - if (shift) - data <<= shift; -- ddbwritel(data, SPI_DATA); -- while (ddbreadl(SPI_CONTROL) & 0x0004) -+ ddbwritel(dev, data, SPI_DATA); -+ while (ddbreadl(dev, SPI_CONTROL) & 0x0004) - ; - - if (!rlen) { -- ddbwritel(0, SPI_CONTROL); -+ ddbwritel(dev, 0, SPI_CONTROL); - return 0; - } - if (rlen > 4) -- ddbwritel(1, SPI_CONTROL); -+ ddbwritel(dev, 1, SPI_CONTROL); - - while (rlen > 4) { -- ddbwritel(0xffffffff, SPI_DATA); -- while (ddbreadl(SPI_CONTROL) & 0x0004) -+ ddbwritel(dev, 0xffffffff, SPI_DATA); -+ while (ddbreadl(dev, SPI_CONTROL) & 0x0004) - ; -- data = ddbreadl(SPI_DATA); -+ data = ddbreadl(dev, SPI_DATA); - *(u32 *) rbuf = swab32(data); - rbuf += 4; - rlen -= 4; - } -- ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL); -- ddbwritel(0xffffffff, SPI_DATA); -- while (ddbreadl(SPI_CONTROL) & 0x0004) -+ ddbwritel(dev, 0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL); -+ ddbwritel(dev, 0xffffffff, SPI_DATA); -+ while (ddbreadl(dev, SPI_CONTROL) & 0x0004) - ; - -- data = ddbreadl(SPI_DATA); -- ddbwritel(0, SPI_CONTROL); -+ data = ddbreadl(dev, SPI_DATA); -+ ddbwritel(dev, 0, SPI_CONTROL); - - if (rlen < 4) - data <<= ((4 - rlen) * 8); -@@ -1421,14 +2138,21 @@ struct ddb_flashio { - __u32 read_len; - }; - -+struct ddb_gpio { -+ __u32 mask; -+ __u32 data; -+}; -+ -+ - #define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio) -+#define IOCTL_DDB_GPIO_IN _IOWR(DDB_MAGIC, 0x01, struct ddb_gpio) -+#define IOCTL_DDB_GPIO_OUT _IOWR(DDB_MAGIC, 0x02, struct ddb_gpio) - - #define DDB_NAME "ddbridge" - - static u32 ddb_num; --static struct ddb *ddbs[32]; --static struct class *ddb_class; - static int ddb_major; -+static DEFINE_MUTEX(ddb_mutex); - - static int ddb_open(struct inode *inode, struct file *file) - { -@@ -1470,6 +2194,16 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) - return -EFAULT; - break; - } -+ case IOCTL_DDB_GPIO_OUT: -+ { -+ struct ddb_gpio gpio; -+ if (copy_from_user(&gpio, parg, sizeof(gpio))) -+ break; -+ ddbwritel(dev, gpio.mask, GPIO_DIRECTION); -+ ddbwritel(dev, gpio.data, GPIO_OUTPUT); -+ res = 0; -+ break; -+ } - default: - return -ENOTTY; - } -@@ -1481,52 +2215,336 @@ static const struct file_operations ddb_fops = { - .open = ddb_open, - }; - --static char *ddb_devnode(struct device *device, umode_t *mode) -+static char *ddb_devnode(struct device *device, mode_t *mode) - { - struct ddb *dev = dev_get_drvdata(device); - - return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr); - } - -+static ssize_t ports_show(struct device *device, struct device_attribute *attr, char *buf) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ -+ return sprintf(buf, "%d\n", dev->info->port_num); -+} -+ -+static ssize_t ts_irq_show(struct device *device, struct device_attribute *attr, char *buf) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ -+ return sprintf(buf, "%d\n", dev->ts_irq); -+} -+ -+static ssize_t i2c_irq_show(struct device *device, struct device_attribute *attr, char *buf) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ -+ return sprintf(buf, "%d\n", dev->i2c_irq); -+} -+ -+static char *class_name[] = { -+ "NONE", "CI", "TUNER", "LOOP" -+}; -+ -+static char *type_name[] = { -+ "NONE", "DVBS_ST", "DVBS_ST_AA", "DVBCT_TR", "DVBCT_ST", "INTERNAL", "CXD2099", -+}; -+ -+static ssize_t fan_show(struct device *device, struct device_attribute *attr, char *buf) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ u32 val; -+ -+ val = ddbreadl(dev, GPIO_OUTPUT) & 1; -+ return sprintf(buf, "%d\n", val); -+} -+ -+static ssize_t fan_store(struct device *device, struct device_attribute *d, -+ const char *buf, size_t count) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ unsigned val; -+ -+ if (sscanf(buf, "%u\n", &val) != 1) -+ return -EINVAL; -+ ddbwritel(dev, 1, GPIO_DIRECTION); -+ ddbwritel(dev, val & 1, GPIO_OUTPUT); -+ return count; -+} -+ -+static ssize_t temp_show(struct device *device, struct device_attribute *attr, char *buf) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ int temp; -+ u8 tmp[2]; -+ -+ if (!dev->info->temp_num) -+ return sprintf(buf, "no sensor\n"); -+ if (i2c_read_regs(&dev->i2c[0].adap, 0x48, 0, tmp, 2) < 0) -+ return sprintf(buf, "read_error\n"); -+ temp = (tmp[0] << 3) | (tmp[1] >> 5); -+ temp *= 125; -+ return sprintf(buf, "%d\n", temp); -+} -+ -+static ssize_t mod_show(struct device *device, struct device_attribute *attr, char *buf) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ int num = attr->attr.name[3] - 0x30; -+ -+ return sprintf(buf, "%s:%s\n", -+ class_name[dev->port[num].class], -+ type_name[dev->port[num].type]); -+} -+ -+static ssize_t led_show(struct device *device, struct device_attribute *attr, char *buf) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ int num = attr->attr.name[3] - 0x30; -+ -+ return sprintf(buf, "%d\n", dev->leds & (1 << num) ? 1 : 0); -+} -+ -+ -+static void ddb_set_led(struct ddb *dev, int num, int val) -+{ -+ if (!dev->info->led_num) -+ return; -+ switch (dev->port[num].class) { -+ case DDB_PORT_TUNER: -+ switch (dev->port[num].type) { -+ case DDB_TUNER_DVBS_ST: -+ printk(KERN_INFO "LED %d %d\n", num, val); -+ i2c_write_reg16(&dev->i2c[num].adap, -+ 0x69, 0xf14c, val ? 2 : 0); -+ break; -+ case DDB_TUNER_DVBCT_ST: -+ printk(KERN_INFO "LED %d %d\n", num, val); -+ i2c_write_reg16(&dev->i2c[num].adap, -+ 0x1f, 0xf00e, 0); -+ i2c_write_reg16(&dev->i2c[num].adap, -+ 0x1f, 0xf00f, val ? 1 : 0); -+ break; -+ } -+ break; -+ default: -+ break; -+ } -+} -+ -+static ssize_t led_store(struct device *device, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ int num = attr->attr.name[3] - 0x30; -+ unsigned val; -+ -+ if (sscanf(buf, "%u\n", &val) != 1) -+ return -EINVAL; -+ if (val) -+ dev->leds |= (1 << num); -+ else -+ dev->leds &= ~(1 << num); -+ ddb_set_led(dev, num, val); -+ return count; -+} -+ -+static ssize_t snr_show(struct device *device, struct device_attribute *attr, char *buf) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ char snr[32]; -+ int num = attr->attr.name[3] - 0x30; -+ -+ /* serial number at 0x100-0x11f */ -+ if (i2c_read_regs16(&dev->i2c[num].adap, 0x57, 0x100, snr, 32) < 0) -+ return sprintf(buf, "NO SNR\n"); -+ snr[31] = 0; /* in case it is not terminated on EEPROM */ -+ return sprintf(buf, "%s\n", snr); -+} -+ -+ -+static ssize_t snr_store(struct device *device, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ int num = attr->attr.name[3] - 0x30; -+ u8 snr[34] = { 0x01, 0x00 }; -+ -+ if (count > 31) -+ return -EINVAL; -+ memcpy(snr + 2, buf, count); -+ i2c_write(&dev->i2c[num].adap, 0x57, snr, 34); -+ return count; -+} -+ -+static ssize_t redirect_show(struct device *device, struct device_attribute *attr, char *buf) -+{ -+ return 0; -+} -+ -+static ssize_t redirect_store(struct device *device, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ unsigned int i, p; -+ int res; -+ -+ if (sscanf(buf, "%x %x\n", &i, &p) != 2) -+ return -EINVAL; -+ printk(KERN_INFO "redirect: %02x, %02x\n", i, p); -+ res = set_redirect(i, p); -+ if (res < 0) -+ return res; -+ return count; -+} -+ -+#define __ATTR_MRO(_name, _show) { \ -+ .attr = { .name = __stringify(_name), .mode = 0444 }, \ -+ .show = _show, \ -+} -+ -+struct device_attribute ddb_attrs[] = { -+ __ATTR_RO(ports), -+ __ATTR_RO(ts_irq), -+ __ATTR_RO(i2c_irq), -+ __ATTR(redirect, 0666, redirect_show, redirect_store), -+ __ATTR_NULL -+}; -+ -+static struct device_attribute ddb_mod[] = { -+ __ATTR_MRO(mod0, mod_show), -+ __ATTR_MRO(mod1, mod_show), -+ __ATTR_MRO(mod2, mod_show), -+ __ATTR_MRO(mod3, mod_show), -+}; -+ -+static struct device_attribute ddb_temp = -+ __ATTR_RO(temp); -+ -+static struct device_attribute ddb_fan = -+ __ATTR(fan, 0666, fan_show, fan_store); -+ -+static struct device_attribute ddb_led[] = { -+ __ATTR(led0, 0666, led_show, led_store), -+ __ATTR(led1, 0666, led_show, led_store), -+ __ATTR(led2, 0666, led_show, led_store), -+ __ATTR(led3, 0666, led_show, led_store), -+}; -+ -+static struct device_attribute ddb_snr[] = { -+ __ATTR(snr0, 0666, snr_show, snr_store), -+ __ATTR(snr1, 0666, snr_show, snr_store), -+ __ATTR(snr2, 0666, snr_show, snr_store), -+ __ATTR(snr3, 0666, snr_show, snr_store), -+}; -+ -+static struct class ddb_class = { -+ .name = "ddbridge", -+ .owner = THIS_MODULE, -+ .dev_attrs = ddb_attrs, -+ .devnode = ddb_devnode, -+}; -+ - static int ddb_class_create(void) - { - ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops); - if (ddb_major < 0) - return ddb_major; -- -- ddb_class = class_create(THIS_MODULE, DDB_NAME); -- if (IS_ERR(ddb_class)) { -- unregister_chrdev(ddb_major, DDB_NAME); -- return PTR_ERR(ddb_class); -- } -- ddb_class->devnode = ddb_devnode; -+ if (class_register(&ddb_class) < 0) -+ return -1; - return 0; - } - - static void ddb_class_destroy(void) - { -- class_destroy(ddb_class); -+ class_unregister(&ddb_class); - unregister_chrdev(ddb_major, DDB_NAME); - } - -+static int ddb_device_files_create(struct ddb *dev) -+{ -+ int i, error = 0; -+ -+ if (dev->info->temp_num > 0) -+ error = device_create_file(dev->ddb_dev, &ddb_temp); -+ -+ if (!error && dev->info->fan_num > 0) -+ error = device_create_file(dev->ddb_dev, &ddb_fan); -+ -+ for (i = 0; !error && (i < dev->info->led_num); i++) -+ error = device_create_file(dev->ddb_dev, &ddb_led[i]); -+ -+ for (i = 0; !error && (i < dev->info->port_num); i++) -+ error = device_create_file(dev->ddb_dev, &ddb_mod[i]); -+ -+ for (i = 0; !error && (i < dev->info->i2c_num); i++) -+ error = device_create_file(dev->ddb_dev, &ddb_snr[i]); -+ -+ return error; -+} -+ -+static void ddb_device_files_delete(struct ddb *dev) -+{ -+ int i; -+ -+ if (dev->info->temp_num > 0) -+ device_remove_file(dev->ddb_dev, &ddb_temp); -+ -+ if (dev->info->fan_num > 0) -+ device_remove_file(dev->ddb_dev, &ddb_fan); -+ -+ for (i = 0; i < dev->info->led_num; i++) -+ device_remove_file(dev->ddb_dev, &ddb_led[i]); -+ -+ for (i = 0; i < dev->info->port_num; i++) -+ device_remove_file(dev->ddb_dev, &ddb_mod[i]); -+ -+ for (i = 0; i < dev->info->i2c_num; i++) -+ device_remove_file(dev->ddb_dev, &ddb_snr[i]); -+} -+ - static int ddb_device_create(struct ddb *dev) - { -+ int error = -1; -+ -+ mutex_lock(&ddb_mutex); - dev->nr = ddb_num++; -- dev->ddb_dev = device_create(ddb_class, NULL, -+ ddbs[dev->nr] = dev; -+ mutex_unlock(&ddb_mutex); -+ dev->ddb_dev = device_create(&ddb_class, &dev->pdev->dev, - MKDEV(ddb_major, dev->nr), - dev, "ddbridge%d", dev->nr); -- ddbs[dev->nr] = dev; -- if (IS_ERR(dev->ddb_dev)) -- return -1; -+ if (IS_ERR(dev->ddb_dev)) { -+ printk(KERN_ERR ": Could not create ddbridge device\n"); -+ goto fail1; -+ } -+ error = ddb_device_files_create(dev); -+ if (error) { -+ printk(KERN_ERR ": Could not create ddbridge sysfs files\n"); -+ goto fail2; -+ } -+ - return 0; -+ -+fail2: -+ ddb_device_files_delete(dev); -+ device_destroy(&ddb_class, MKDEV(ddb_major, dev->nr)); -+ -+fail1: -+ mutex_lock(&ddb_mutex); -+ ddb_num--; -+ ddbs[dev->nr] = NULL; -+ mutex_unlock(&ddb_mutex); -+ -+ return error; - } - - static void ddb_device_destroy(struct ddb *dev) - { -- ddb_num--; - if (IS_ERR(dev->ddb_dev)) - return; -- device_destroy(ddb_class, MKDEV(ddb_major, 0)); -+ ddb_device_files_delete(dev); -+ device_destroy(&ddb_class, MKDEV(ddb_major, dev->nr)); - } - - -@@ -1549,7 +2567,7 @@ static void ddb_remove(struct pci_dev *pdev) - ddb_ports_detach(dev); - ddb_i2c_release(dev); - -- ddbwritel(0, INTERRUPT_ENABLE); -+ ddbwritel(dev, 0, INTERRUPT_ENABLE); - free_irq(dev->pdev->irq, dev); - #ifdef CONFIG_PCI_MSI - if (dev->msi) -@@ -1564,7 +2582,6 @@ static void ddb_remove(struct pci_dev *pdev) - pci_disable_device(pdev); - } - -- - static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id) - { - struct ddb *dev; -@@ -1574,10 +2591,9 @@ static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id) - if (pci_enable_device(pdev) < 0) - return -ENODEV; - -- dev = vmalloc(sizeof(struct ddb)); -+ dev = vzalloc(sizeof(struct ddb)); - if (dev == NULL) - return -ENOMEM; -- memset(dev, 0, sizeof(struct ddb)); - - dev->pdev = pdev; - pci_set_drvdata(pdev, dev); -@@ -1590,7 +2606,8 @@ static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id) - stat = -ENOMEM; - goto fail; - } -- printk(KERN_INFO "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4)); -+ printk(KERN_INFO "HW %08x REG %08x\n", -+ ddbreadl(dev, 0), ddbreadl(dev, 4)); - - #ifdef CONFIG_PCI_MSI - if (pci_msi_enabled()) -@@ -1606,11 +2623,11 @@ static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id) - irq_flag, "DDBridge", (void *) dev); - if (stat < 0) - goto fail1; -- ddbwritel(0, DMA_BASE_WRITE); -- ddbwritel(0, DMA_BASE_READ); -- ddbwritel(0xffffffff, INTERRUPT_ACK); -- ddbwritel(0xfff0f, INTERRUPT_ENABLE); -- ddbwritel(0, MSI1_ENABLE); -+ ddbwritel(dev, 0, DMA_BASE_WRITE); -+ ddbwritel(dev, 0, DMA_BASE_READ); -+ ddbwritel(dev, 0xffffffff, INTERRUPT_ACK); -+ ddbwritel(dev, 0x000fff0f, INTERRUPT_ENABLE); -+ ddbwritel(dev, 0, MSI1_ENABLE); - - if (ddb_i2c_init(dev) < 0) - goto fail1; -@@ -1621,7 +2638,14 @@ static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id) - } - if (ddb_ports_attach(dev) < 0) - goto fail3; -- ddb_device_create(dev); -+ -+ if (ddb_device_create(dev) < 0) -+ goto fail3; -+ -+ if (dev->info->fan_num) { -+ ddbwritel(dev, 1, GPIO_DIRECTION); -+ ddbwritel(dev, 1, GPIO_OUTPUT); -+ } - return 0; - - fail3: -@@ -1631,11 +2655,14 @@ fail3: - fail2: - printk(KERN_ERR "fail2\n"); - ddb_buffers_free(dev); -+ ddb_i2c_release(dev); - fail1: - printk(KERN_ERR "fail1\n"); -+ free_irq(dev->pdev->irq, dev); -+#ifdef CONFIG_PCI_MSI - if (dev->msi) - pci_disable_msi(dev->pdev); -- free_irq(dev->pdev->irq, dev); -+#endif - fail: - printk(KERN_ERR "fail\n"); - ddb_unmap(dev); -@@ -1657,23 +2684,78 @@ static struct ddb_info ddb_octopus = { - .type = DDB_OCTOPUS, - .name = "Digital Devices Octopus DVB adapter", - .port_num = 4, -+ .i2c_num = 4, - }; - - static struct ddb_info ddb_octopus_le = { - .type = DDB_OCTOPUS, - .name = "Digital Devices Octopus LE DVB adapter", - .port_num = 2, -+ .i2c_num = 2, -+}; -+ -+static struct ddb_info ddb_octopus_oem = { -+ .type = DDB_OCTOPUS, -+ .name = "Digital Devices Octopus OEM", -+ .port_num = 4, -+ .i2c_num = 4, -+ .led_num = 1, -+ .fan_num = 1, -+ .temp_num = 1, -+}; -+ -+static struct ddb_info ddb_octopus_mini = { -+ .type = DDB_OCTOPUS, -+ .name = "Digital Devices Octopus Mini", -+ .port_num = 4, -+ .i2c_num = 4, - }; - - static struct ddb_info ddb_v6 = { - .type = DDB_OCTOPUS, - .name = "Digital Devices Cine S2 V6 DVB adapter", - .port_num = 3, -+ .i2c_num = 3, -+}; -+ -+static struct ddb_info ddb_v6_5 = { -+ .type = DDB_OCTOPUS, -+ .name = "Digital Devices Cine S2 V6.5 DVB adapter", -+ .port_num = 4, -+ .i2c_num = 4, -+}; -+ -+static struct ddb_info ddb_dvbct = { -+ .type = DDB_OCTOPUS, -+ .name = "Digital Devices DVBCT V6.1 DVB adapter", -+ .port_num = 3, -+ .i2c_num = 3, -+}; -+ -+static struct ddb_info ddb_satixS2v3 = { -+ .type = DDB_OCTOPUS, -+ .name = "Mystique SaTiX-S2 V3 DVB adapter", -+ .port_num = 3, -+ .i2c_num = 3, -+}; -+ -+static struct ddb_info ddb_ci = { -+ .type = DDB_OCTOPUS_CI, -+ .name = "Digital Devices Octopus CI", -+ .port_num = 4, -+ .i2c_num = 2, -+}; -+ -+static struct ddb_info ddb_cis = { -+ .type = DDB_OCTOPUS_CI, -+ .name = "Digital Devices Octopus CI single", -+ .port_num = 3, -+ .i2c_num = 2, - }; - - #define DDVID 0xdd01 /* Digital Devices Vendor ID */ - --#define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \ -+#define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \ - .vendor = _vend, .device = _dev, \ - .subvendor = _subvend, .subdevice = _subdev, \ - .driver_data = (unsigned long)&_driverdata } -@@ -1682,8 +2764,15 @@ static const struct pci_device_id ddb_id_tbl[] = { - DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus), - DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus), - DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le), -- DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus), -+ DDB_ID(DDVID, 0x0003, DDVID, 0x0003, ddb_octopus_oem), -+ DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus_mini), - DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6), -+ DDB_ID(DDVID, 0x0003, DDVID, 0x0021, ddb_v6_5), -+ DDB_ID(DDVID, 0x0003, DDVID, 0x0030, ddb_dvbct), -+ DDB_ID(DDVID, 0x0003, DDVID, 0xdb03, ddb_satixS2v3), -+ DDB_ID(DDVID, 0x0005, DDVID, 0x0004, ddb_octopus), -+ DDB_ID(DDVID, 0x0011, DDVID, 0x0040, ddb_ci), -+ DDB_ID(DDVID, 0x0011, DDVID, 0x0041, ddb_cis), - /* in case sub-ids got deleted in flash */ - DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none), - {0} -@@ -1700,18 +2789,16 @@ static struct pci_driver ddb_pci_driver = { - - static __init int module_init_ddbridge(void) - { -- int ret; -+ int stat; - - printk(KERN_INFO "Digital Devices PCIE bridge driver, " - "Copyright (C) 2010-11 Digital Devices GmbH\n"); -- -- ret = ddb_class_create(); -- if (ret < 0) -- return ret; -- ret = pci_register_driver(&ddb_pci_driver); -- if (ret < 0) -+ if (ddb_class_create()) -+ return -1; -+ stat = pci_register_driver(&ddb_pci_driver); -+ if (stat < 0) - ddb_class_destroy(); -- return ret; -+ return stat; - } - - static __exit void module_exit_ddbridge(void) -@@ -1726,4 +2813,4 @@ module_exit(module_exit_ddbridge); - MODULE_DESCRIPTION("Digital Devices PCIe Bridge"); - MODULE_AUTHOR("Ralph Metzler"); - MODULE_LICENSE("GPL"); --MODULE_VERSION("0.5"); -+MODULE_VERSION("0.8"); -diff --git a/drivers/media/pci/ddbridge/ddbridge-regs.h b/drivers/media/pci/ddbridge/ddbridge-regs.h -index a3ccb31..46e8a21 100644 ---- a/drivers/media/pci/ddbridge/ddbridge-regs.h -+++ b/drivers/media/pci/ddbridge/ddbridge-regs.h -@@ -21,11 +21,12 @@ - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - --/* DD-DVBBridgeV1.h 273 2010-09-17 05:03:16Z manfred */ -+/* DD-DVBBridgeV1.h 388 2011-07-13 20:47:08Z manfred */ - - /* Register Definitions */ - --#define CUR_REGISTERMAP_VERSION 0x10000 -+#define CUR_REGISTERMAP_VERSION 0x10003 -+#define CUR_REGISTERMAP_VERSION_CI 0x10000 - - #define HARDWARE_VERSION 0x00 - #define REGISTERMAP_VERSION 0x04 -@@ -36,8 +37,14 @@ - #define SPI_CONTROL 0x10 - #define SPI_DATA 0x14 - --/* ------------------------------------------------------------------------- */ -+/* -------------------------------------------------------------------------- */ -+/* GPIO */ -+ -+#define GPIO_OUTPUT 0x20 -+#define GPIO_INPUT 0x24 -+#define GPIO_DIRECTION 0x28 - -+/* -------------------------------------------------------------------------- */ - /* Interrupt controller */ - /* How many MSI's are available depends on HW (Min 2 max 8) */ - /* How many are usable also depends on Host platform */ -@@ -149,3 +156,46 @@ - #define DMA_BASE_ADDRESS_TABLE (0x2000) - #define DMA_BASE_ADDRESS_TABLE_ENTRIES (512) - -+/* -------------------------------------------------------------------------- */ -+/* CI Interface (only CI-Bridge) */ -+ -+#define CI_BASE (0x400) -+#define CI_CONTROL(i) (CI_BASE + (i) * 32 + 0x00) -+ -+#define CI_DO_ATTRIBUTE_RW(i) (CI_BASE + (i) * 32 + 0x04) -+#define CI_DO_IO_RW(i) (CI_BASE + (i) * 32 + 0x08) -+#define CI_READDATA(i) (CI_BASE + (i) * 32 + 0x0c) -+#define CI_DO_READ_ATTRIBUTES(i) (CI_BASE + (i) * 32 + 0x10) -+ -+#define CI_RESET_CAM (0x00000001) -+#define CI_POWER_ON (0x00000002) -+#define CI_ENABLE (0x00000004) -+#define CI_BLOCKIO_ENABLE (0x00000008) -+#define CI_BYPASS_DISABLE (0x00000010) -+#define CI_DISABLE_AUTO_OFF (0x00000020) -+ -+#define CI_CAM_READY (0x00010000) -+#define CI_CAM_DETECT (0x00020000) -+#define CI_READY (0x80000000) -+#define CI_BLOCKIO_ACTIVE (0x40000000) -+#define CI_BLOCKIO_RCVDATA (0x20000000) -+#define CI_BLOCKIO_SEND_PENDING (0x10000000) -+#define CI_BLOCKIO_SEND_COMPLETE (0x08000000) -+ -+#define CI_READ_CMD (0x40000000) -+#define CI_WRITE_CMD (0x80000000) -+ -+#define CI_BLOCKIO_SEND(i) (CI_BASE + (i) * 32 + 0x14) -+#define CI_BLOCKIO_RECEIVE(i) (CI_BASE + (i) * 32 + 0x18) -+ -+#define CI_BLOCKIO_SEND_COMMAND (0x80000000) -+#define CI_BLOCKIO_SEND_COMPLETE_ACK (0x40000000) -+#define CI_BLOCKIO_RCVDATA_ACK (0x40000000) -+ -+#define CI_BUFFER_BASE (0x3000) -+#define CI_BUFFER_SIZE (0x0800) -+#define CI_BLOCKIO_BUFFER_SIZE (CI_BUFFER_SIZE/2) -+ -+#define CI_BUFFER(i) (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE) -+#define CI_BLOCKIO_RECEIVE_BUFFER(i) (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE) -+#define CI_BLOCKIO_SEND_BUFFER(i) (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE + CI_BLOCKIO_BUFFER_SIZE) -diff --git a/drivers/media/pci/ddbridge/ddbridge.h b/drivers/media/pci/ddbridge/ddbridge.h -index 8b1b41d..ce2df00 100644 ---- a/drivers/media/pci/ddbridge/ddbridge.h -+++ b/drivers/media/pci/ddbridge/ddbridge.h -@@ -32,7 +32,10 @@ - #include - #include - #include -+#include -+#include - #include -+#include - - #include "dmxdev.h" - #include "dvbdev.h" -@@ -52,43 +55,53 @@ struct ddb_info { - int type; - #define DDB_NONE 0 - #define DDB_OCTOPUS 1 -+#define DDB_OCTOPUS_CI 2 - char *name; - int port_num; -- u32 port_type[DDB_MAX_PORT]; -+ int i2c_num; -+ int led_num; -+ int fan_num; -+ int temp_num; - }; - - /* DMA_SIZE MUST be divisible by 188 and 128 !!! */ - --#define INPUT_DMA_MAX_BUFS 32 /* hardware table limit */ -+#define DMA_MAX_BUFS 32 /* hardware table limit */ -+ - #define INPUT_DMA_BUFS 8 - #define INPUT_DMA_SIZE (128*47*21) -+#define INPUT_DMA_IRQ_DIV 1 - --#define OUTPUT_DMA_MAX_BUFS 32 - #define OUTPUT_DMA_BUFS 8 - #define OUTPUT_DMA_SIZE (128*47*21) -+#define OUTPUT_DMA_IRQ_DIV 1 - - struct ddb; - struct ddb_port; - --struct ddb_input { -- struct ddb_port *port; -+struct ddb_dma { -+ void *io; - u32 nr; -- int attached; -- -- dma_addr_t pbuf[INPUT_DMA_MAX_BUFS]; -- u8 *vbuf[INPUT_DMA_MAX_BUFS]; -- u32 dma_buf_num; -- u32 dma_buf_size; -+ dma_addr_t pbuf[DMA_MAX_BUFS]; -+ u8 *vbuf[DMA_MAX_BUFS]; -+ u32 num; -+ u32 size; -+ u32 div; -+ u32 bufreg; - - struct tasklet_struct tasklet; - spinlock_t lock; - wait_queue_head_t wq; - int running; - u32 stat; -+ u32 ctrl; - u32 cbuf; - u32 coff; -+}; - -- struct dvb_adapter adap; -+struct ddb_dvb { -+ struct dvb_adapter *adap; -+ int adap_registered; - struct dvb_device *dev; - struct dvb_frontend *fe; - struct dvb_frontend *fe2; -@@ -99,32 +112,36 @@ struct ddb_input { - struct dmx_frontend mem_frontend; - int users; - int (*gate_ctrl)(struct dvb_frontend *, int); -+ int attached; - }; - --struct ddb_output { -+struct ddb_ci { -+ struct dvb_ca_en50221 en; - struct ddb_port *port; - u32 nr; -- dma_addr_t pbuf[OUTPUT_DMA_MAX_BUFS]; -- u8 *vbuf[OUTPUT_DMA_MAX_BUFS]; -- u32 dma_buf_num; -- u32 dma_buf_size; -- struct tasklet_struct tasklet; -- spinlock_t lock; -- wait_queue_head_t wq; -- int running; -- u32 stat; -- u32 cbuf; -- u32 coff; -+}; - -- struct dvb_adapter adap; -- struct dvb_device *dev; -+ -+struct ddb_input { -+ struct ddb_port *port; -+ u32 nr; -+ struct ddb_dma *dma; -+ struct ddb_input *redirect; -+ -+ struct ddb_dvb dvb; -+}; -+ -+struct ddb_output { -+ struct ddb_port *port; -+ u32 nr; -+ struct ddb_dma *dma; -+ struct ddb_input *redirect; - }; - - struct ddb_i2c { - struct ddb *dev; - u32 nr; - struct i2c_adapter adap; -- struct i2c_adapter adap2; - u32 regs; - u32 rbuf; - u32 wbuf; -@@ -141,12 +158,15 @@ struct ddb_port { - #define DDB_PORT_NONE 0 - #define DDB_PORT_CI 1 - #define DDB_PORT_TUNER 2 -+#define DDB_PORT_LOOP 3 - u32 type; - #define DDB_TUNER_NONE 0 - #define DDB_TUNER_DVBS_ST 1 - #define DDB_TUNER_DVBS_ST_AA 2 --#define DDB_TUNER_DVBCT_TR 16 --#define DDB_TUNER_DVBCT_ST 17 -+#define DDB_TUNER_DVBCT_TR 3 -+#define DDB_TUNER_DVBCT_ST 4 -+#define DDB_CI_INTERNAL 5 -+#define DDB_CI_EXTERNAL_SONY 6 - u32 adr; - - struct ddb_input *input[2]; -@@ -161,25 +181,20 @@ struct ddb { - struct ddb_i2c i2c[DDB_MAX_I2C]; - struct ddb_input input[DDB_MAX_INPUT]; - struct ddb_output output[DDB_MAX_OUTPUT]; -+ struct dvb_adapter adap[DDB_MAX_INPUT]; -+ struct ddb_dma dma[DDB_MAX_INPUT + DDB_MAX_OUTPUT]; - - struct device *ddb_dev; -- int nr; -+ u32 nr; - u8 iobuf[1028]; - - struct ddb_info *info; - int msi; --}; -- --/****************************************************************************/ - --#define ddbwritel(_val, _adr) writel((_val), \ -- (char *) (dev->regs+(_adr))) --#define ddbreadl(_adr) readl((char *) (dev->regs+(_adr))) --#define ddbcpyto(_adr, _src, _count) memcpy_toio((char *) \ -- (dev->regs+(_adr)), (_src), (_count)) --#define ddbcpyfrom(_dst, _adr, _count) memcpy_fromio((_dst), (char *) \ -- (dev->regs+(_adr)), (_count)) -+ u8 leds; - --/****************************************************************************/ -+ u32 ts_irq; -+ u32 i2c_irq; -+}; - - #endif -diff --git a/drivers/media/pci/ngene/Kconfig b/drivers/media/pci/ngene/Kconfig -index 637d506..14975c7 100644 ---- a/drivers/media/pci/ngene/Kconfig -+++ b/drivers/media/pci/ngene/Kconfig -@@ -1,13 +1,16 @@ - config DVB_NGENE - tristate "Micronas nGene support" - depends on DVB_CORE && PCI && I2C -- select DVB_LNBP21 if MEDIA_SUBDRV_AUTOSELECT -- select DVB_STV6110x if MEDIA_SUBDRV_AUTOSELECT -- select DVB_STV090x if MEDIA_SUBDRV_AUTOSELECT -- select DVB_LGDT330X if MEDIA_SUBDRV_AUTOSELECT -- select DVB_DRXK if MEDIA_SUBDRV_AUTOSELECT -- select DVB_TDA18271C2DD if MEDIA_SUBDRV_AUTOSELECT -- select MEDIA_TUNER_MT2131 if MEDIA_SUBDRV_AUTOSELECT -+ select DVB_CXD2099 -+ select DVB_LNBP21 if !DVB_FE_CUSTOMISE -+ select DVB_STV6110x if !DVB_FE_CUSTOMISE -+ select DVB_STV090x if !DVB_FE_CUSTOMISE -+ select DVB_LGDT330X if !DVB_FE_CUSTOMISE -+ select DVB_DRXK if !DVB_FE_CUSTOMISE -+ select DVB_TDA18271C2DD if !DVB_FE_CUSTOMISE -+ select DVB_STV0367DD if !DVB_FE_CUSTOMISE -+ select DVB_TDA18212DD if !DVB_FE_CUSTOMISE -+ select MEDIA_TUNER_MT2131 if !MEDIA_TUNER_CUSTOMISE - ---help--- - Support for Micronas PCI express cards with nGene bridge. - -diff --git a/drivers/media/pci/ngene/Makefile b/drivers/media/pci/ngene/Makefile -index 5c0b5d6..42c036a 100644 ---- a/drivers/media/pci/ngene/Makefile -+++ b/drivers/media/pci/ngene/Makefile -@@ -2,7 +2,8 @@ - # Makefile for the nGene device driver - # - --ngene-objs := ngene-core.o ngene-i2c.o ngene-cards.o ngene-dvb.o -+ngene-objs := ngene-core.o ngene-i2c.o ngene-cards.o ngene-av.o \ -+ ngene-eeprom.o ngene-dvb.o - - obj-$(CONFIG_DVB_NGENE) += ngene.o - -diff --git a/drivers/media/pci/ngene/ngene-av.c b/drivers/media/pci/ngene/ngene-av.c -new file mode 100644 -index 0000000..a86459e ---- /dev/null -+++ b/drivers/media/pci/ngene/ngene-av.c -@@ -0,0 +1,348 @@ -+/* -+ * ngene-av.c: nGene PCIe bridge driver - DVB video/audio support -+ * -+ * Copyright (C) 2005-2007 Micronas -+ * -+ * Copyright (C) 2008-2009 Ralph Metzler -+ * Modifications for new nGene firmware, -+ * support for EEPROM-copying, -+ * support for new dual DVB-S2 card prototype -+ * -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 only, as published by the Free Software Foundation. -+ * -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ * 02110-1301, USA -+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/* This file provides the support functions for DVB audio/video devices -+ (/dev/dvb/adapter0/[video|audio]), not to be confused with V4L2 support */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "ngene.h" -+ -+#if 0 -+ -+static void *ain_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags) -+{ -+ struct ngene_channel *chan = priv; -+ struct ngene *dev = chan->dev; -+ -+ if (dvb_ringbuffer_free(&dev->ain_rbuf) >= len) { -+ dvb_ringbuffer_write(&dev->ain_rbuf, buf, len); -+ wake_up_interruptible(&dev->ain_rbuf.queue); -+ } else -+ printk(KERN_INFO DEVICE_NAME ": Dropped ain packet.\n"); -+ -+ return 0; -+} -+ -+static void *vcap_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags) -+{ -+ -+ struct ngene_channel *chan = priv; -+ struct ngene *dev = chan->dev; -+ -+ if (len >= 1920 * 1080) -+ len = 1920 * 1080; -+ if (dvb_ringbuffer_free(&dev->vin_rbuf) >= len) { -+ dvb_ringbuffer_write(&dev->vin_rbuf, buf, len); -+ wake_up_interruptible(&dev->vin_rbuf.queue); -+ } else { -+ ;/*printk(KERN_INFO DEVICE_NAME ": Dropped vcap packet.\n"); */ -+ } -+ return 0; -+} -+ -+static ssize_t audio_write(struct file *file, -+ const char *buf, size_t count, loff_t *ppos) -+{ -+ return -EINVAL; -+} -+ -+ssize_t audio_read(struct file *file, char *buf, size_t count, loff_t *ppos) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ int left; -+ int avail; -+ -+ left = count; -+ while (left) { -+ if (wait_event_interruptible( -+ dev->ain_rbuf.queue, -+ dvb_ringbuffer_avail(&dev->ain_rbuf) > 0) < 0) -+ return -EAGAIN; -+ avail = dvb_ringbuffer_avail(&dev->ain_rbuf); -+ if (avail > left) -+ avail = left; -+ dvb_ringbuffer_read_user(&dev->ain_rbuf, buf, avail); -+ left -= avail; -+ buf += avail; -+ } -+ return count; -+} -+ -+static int audio_open(struct inode *inode, struct file *file) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ struct ngene_channel *chan2 = &chan->dev->channel[2]; -+ int ret; -+ -+ ret = dvb_generic_open(inode, file); -+ if (ret < 0) -+ return ret; -+ dvb_ringbuffer_flush(&dev->ain_rbuf); -+ -+ chan2->Capture1Length = MAX_AUDIO_BUFFER_SIZE; -+ chan2->pBufferExchange = ain_exchange; -+ ngene_command_stream_control(chan2->dev, chan2->number, 0x80, -+ SMODE_AUDIO_CAPTURE, 0); -+ return ret; -+} -+ -+static int audio_release(struct inode *inode, struct file *file) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ struct ngene_channel *chan2 = &chan->dev->channel[2]; -+ -+ ngene_command_stream_control(dev, 2, 0, 0, 0); -+ chan2->pBufferExchange = 0; -+ -+ return dvb_generic_release(inode, file); -+} -+ -+static const struct file_operations audio_fops = { -+ .owner = THIS_MODULE, -+ .read = audio_read, -+ .write = audio_write, -+ .open = audio_open, -+ .release = audio_release, -+}; -+ -+static struct dvb_device dvbdev_audio = { -+ .priv = 0, -+ .readers = -1, -+ .writers = 1, -+ .users = 1, -+ .fops = &audio_fops, -+}; -+ -+static int video_open(struct inode *inode, struct file *file) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ struct ngene_channel *chan0 = &chan->dev->channel[0]; -+ int ret; -+ -+ ret = dvb_generic_open(inode, file); -+ if (ret < 0) -+ return ret; -+ if ((file->f_flags & O_ACCMODE) != O_RDONLY) -+ return ret; -+ dvb_ringbuffer_flush(&dev->vin_rbuf); -+ -+ chan0->nBytesPerLine = 1920 * 2; -+ chan0->nLines = 540; -+ chan0->Capture1Length = 1920 * 2 * 540; -+ chan0->pBufferExchange = vcap_exchange; -+ chan0->itumode = 2; -+ ngene_command_stream_control(chan0->dev, chan0->number, -+ 0x80, SMODE_VIDEO_CAPTURE, 0); -+ return ret; -+} -+ -+static int video_release(struct inode *inode, struct file *file) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ struct ngene_channel *chan0 = &chan->dev->channel[0]; -+ -+ ngene_command_stream_control(dev, 0, 0, 0, 0); -+ chan0->pBufferExchange = 0; -+ -+ return dvb_generic_release(inode, file); -+} -+ -+static ssize_t video_write(struct file *file, -+ const char *buf, size_t count, loff_t *ppos) -+{ -+ return -EINVAL; -+} -+ -+ssize_t video_read(struct file *file, char *buf, size_t count, loff_t *ppos) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ int left, avail; -+ -+ left = count; -+ while (left) { -+ if (wait_event_interruptible( -+ dev->vin_rbuf.queue, -+ dvb_ringbuffer_avail(&dev->vin_rbuf) > 0) < 0) -+ return -EAGAIN; -+ avail = dvb_ringbuffer_avail(&dev->vin_rbuf); -+ if (avail > left) -+ avail = left; -+ dvb_ringbuffer_read_user(&dev->vin_rbuf, buf, avail); -+ left -= avail; -+ buf += avail; -+ } -+ return count; -+} -+ -+/* Why is this not exported from dvb_core ?!?! */ -+ -+static int dvb_usercopy2(struct inode *inode, struct file *file, -+ unsigned int cmd, unsigned long arg, -+ int (*func)(struct inode *inode, struct file *file, -+ unsigned int cmd, void *arg)) -+{ -+ char sbuf[128]; -+ void *mbuf = NULL; -+ void *parg = NULL; -+ int err = -EINVAL; -+ -+ /* Copy arguments into temp kernel buffer */ -+ switch (_IOC_DIR(cmd)) { -+ case _IOC_NONE: -+ /* -+ * For this command, the pointer is actually an integer -+ * argument. -+ */ -+ parg = (void *)arg; -+ break; -+ case _IOC_READ: /* some v4l ioctls are marked wrong ... */ -+ case _IOC_WRITE: -+ case (_IOC_WRITE | _IOC_READ): -+ if (_IOC_SIZE(cmd) <= sizeof(sbuf)) { -+ parg = sbuf; -+ } else { -+ /* too big to allocate from stack */ -+ mbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL); -+ if (NULL == mbuf) -+ return -ENOMEM; -+ parg = mbuf; -+ } -+ -+ err = -EFAULT; -+ if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd))) -+ goto out; -+ break; -+ } -+ -+ /* call driver */ -+ err = func(inode, file, cmd, parg); -+ if (err == -ENOIOCTLCMD) -+ err = -EINVAL; -+ -+ if (err < 0) -+ goto out; -+ -+ /* Copy results into user buffer */ -+ switch (_IOC_DIR(cmd)) { -+ case _IOC_READ: -+ case (_IOC_WRITE | _IOC_READ): -+ if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd))) -+ err = -EFAULT; -+ break; -+ } -+ -+out: -+ kfree(mbuf); -+ return err; -+} -+ -+static int video_do_ioctl(struct inode *inode, struct file *file, -+ unsigned int cmd, void *parg) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ int ret = 0; -+ unsigned long arg = (unsigned long)parg; -+ -+ switch (cmd) { -+ case VIDEO_SET_STREAMTYPE: -+ switch (arg) { -+ case VIDEO_CAP_MPEG2: -+ /* printk(KERN_INFO DEVICE_NAME ": setting MPEG2\n"); */ -+ send_cli(dev, "vdec mpeg2\n"); -+ break; -+ case VIDEO_CAP_AVC: -+ /* printk(KERN_INFO DEVICE_NAME ": setting H264\n"); */ -+ send_cli(dev, "vdec h264\n"); -+ break; -+ case VIDEO_CAP_VC1: -+ /* printk(KERN_INFO DEVICE_NAME ": setting VC1\n"); */ -+ send_cli(dev, "vdec vc1\n"); -+ break; -+ default: -+ ret = -EINVAL; -+ break; -+ } -+ break; -+ default: -+ ret = -ENOIOCTLCMD; -+ return -EINVAL; -+ } -+ return ret; -+} -+ -+static int video_ioctl(struct inode *inode, struct file *file, -+ unsigned int cmd, unsigned long arg) -+{ -+ return dvb_usercopy2(inode, file, cmd, arg, video_do_ioctl); -+} -+ -+static const struct file_operations video_fops = { -+ .owner = THIS_MODULE, -+ .read = video_read, -+ .write = video_write, -+ .open = video_open, -+ .release = video_release, -+ .ioctl = video_ioctl, -+}; -+ -+static struct dvb_device dvbdev_video = { -+ .priv = 0, -+ .readers = -1, -+ .writers = 1, -+ .users = -1, -+ .fops = &video_fops, -+}; -+#endif -diff --git a/drivers/media/pci/ngene/ngene-cards.c b/drivers/media/pci/ngene/ngene-cards.c -index 9e82d21..c9b1bd4 100644 ---- a/drivers/media/pci/ngene/ngene-cards.c -+++ b/drivers/media/pci/ngene/ngene-cards.c -@@ -42,8 +42,8 @@ - #include "mt2131.h" - #include "tda18271c2dd.h" - #include "drxk.h" --#include "drxd.h" --#include "dvb-pll.h" -+#include "tda18212dd.h" -+#include "stv0367dd.h" - - - /****************************************************************************/ -@@ -86,8 +86,98 @@ static int tuner_attach_stv6110(struct ngene_channel *chan) - return 0; - } - -+#if 0 -+static int tuner_attach_mt2060(struct ngene_channel *chan) -+{ -+ struct ngene *dev = chan->dev; -+ void *tconf = dev->card_info->tuner_config[chan->number]; -+ u8 drxa = dev->card_info->demoda[chan->number]; -+ struct dvb_frontend *fe = chan->fe, *fe2; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19) -+ fe->misc_priv = chan; -+#else -+ fe->sec_priv = chan; -+#endif -+ fe->ops.i2c_gate_ctrl = dev->card_info->gate_ctrl; -+ -+ dev->card_info->gate_ctrl(fe, 1); -+ fe2 = mt2060_attach(fe, &chan->i2c_adapter, tconf, 1220); -+ dev->card_info->gate_ctrl(fe, 0); -+ -+ i2c_write_register(&chan->i2c_adapter, drxa, 3, 4); -+ write_demod(&chan->i2c_adapter, drxa, 0x1012, 15); -+ write_demod(&chan->i2c_adapter, drxa, 0x1007, 0xc27); -+ write_demod(&chan->i2c_adapter, drxa, 0x0020, 0x003); -+ -+ return fe2 ? 0 : -ENODEV; -+} -+ -+static int tuner_attach_xc3028(struct ngene_channel *chan) -+{ -+ struct ngene *dev = chan->dev; -+ void *tconf = dev->card_info->tuner_config[chan->number]; -+ struct dvb_frontend *fe = chan->fe, *fe2; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19) -+ fe->misc_priv = chan; -+#else -+ fe->sec_priv = chan; -+#endif -+ fe->ops.i2c_gate_ctrl = dev->card_info->gate_ctrl; -+ -+ dev->card_info->gate_ctrl(fe, 1); -+ fe2 = xc3028_attach(fe, &chan->i2c_adapter, tconf); -+ dev->card_info->gate_ctrl(fe, 0); -+ -+ /*chan->fe->ops.tuner_ops.set_frequency(chan->fe,231250000);*/ -+ -+ return fe2 ? 0 : -ENODEV; -+} -+ -+static int demod_attach_drxd(struct ngene_channel *chan) -+{ -+ void *feconf = chan->dev->card_info->fe_config[chan->number]; -+ -+ chan->fe = drxd_attach(feconf, -+ chan, &chan->i2c_adapter, -+ &chan->dev->pci_dev->dev); -+ return (chan->fe) ? 0 : -ENODEV; -+} -+ -+static int demod_attach_drxh(struct ngene_channel *chan) -+{ -+ void *feconf = chan->dev->card_info->fe_config[chan->number]; -+ -+ chan->fe = drxh_attach(feconf, chan, -+ &chan->i2c_adapter, &chan->dev->pci_dev->dev); -+ return (chan->fe) ? 0 : -ENODEV; -+} -+ -+static int demod_attach_stb0899(struct ngene_channel *chan) -+{ -+ void *feconf = chan->dev->card_info->fe_config[chan->number]; -+ -+ chan->fe = stb0899_attach(feconf, -+ chan, &chan->i2c_adapter, -+ &chan->dev->pci_dev->dev); -+ if (chan->fe) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18) -+ chan->set_tone = chan->fe->ops->set_tone; -+ chan->fe->ops->set_tone = lnbh21_set_tone; -+ chan->fe->ops->set_voltage = lnbh21_set_voltage; -+#else -+ chan->set_tone = chan->fe->ops.set_tone; -+ chan->fe->ops.set_tone = lnbh21_set_tone; -+ chan->fe->ops.set_voltage = lnbh21_set_voltage; -+#endif -+ } -+ -+ return (chan->fe) ? 0 : -ENODEV; -+} -+#endif - --static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) -+static int locked_gate_ctrl(struct dvb_frontend *fe, int enable) - { - struct ngene_channel *chan = fe->sec_priv; - int status; -@@ -121,12 +211,29 @@ static int tuner_attach_tda18271(struct ngene_channel *chan) - return 0; - } - -+static int tuner_attach_tda18212dd(struct ngene_channel *chan) -+{ -+ struct i2c_adapter *i2c; -+ struct dvb_frontend *fe; -+ -+ i2c = &chan->dev->channel[0].i2c_adapter; -+ fe = dvb_attach(tda18212dd_attach, chan->fe, i2c, -+ (chan->number & 1) ? 0x63 : 0x60); -+ if (!fe) { -+ printk(KERN_ERR "No TDA18212 found!\n"); -+ return -ENODEV; -+ } -+ return 0; -+} -+ - static int tuner_attach_probe(struct ngene_channel *chan) - { - if (chan->demod_type == 0) - return tuner_attach_stv6110(chan); - if (chan->demod_type == 1) - return tuner_attach_tda18271(chan); -+ if (chan->demod_type == 2) -+ return tuner_attach_tda18212dd(chan); - return -EINVAL; - } - -@@ -218,18 +325,51 @@ static int demod_attach_drxk(struct ngene_channel *chan, - struct drxk_config config; - - memset(&config, 0, sizeof(config)); -- config.microcode_name = "drxk_a3.mc"; -- config.qam_demod_parameter_count = 4; - config.adr = 0x29 + (chan->number ^ 2); -+ config.microcode_name = "drxk_a3.mc"; - -+#ifdef USE_API3 -+ chan->fe = dvb_attach(drxk_attach, &config, i2c, &chan->fe2); -+#else - chan->fe = dvb_attach(drxk_attach, &config, i2c); -+#endif - if (!chan->fe) { - printk(KERN_ERR "No DRXK found!\n"); - return -ENODEV; - } - chan->fe->sec_priv = chan; - chan->gate_ctrl = chan->fe->ops.i2c_gate_ctrl; -- chan->fe->ops.i2c_gate_ctrl = drxk_gate_ctrl; -+ chan->fe->ops.i2c_gate_ctrl = locked_gate_ctrl; -+ return 0; -+} -+ -+static int port_has_stv0367(struct i2c_adapter *i2c, int port) -+{ -+ u8 val; -+ -+ if (i2c_read_reg16(i2c, 0x1c + (port ^ 1), 0xf000, &val) < 0) -+ return 0; -+ if (val != 0x60) -+ return 0; -+ return 1; -+} -+ -+static int demod_attach_stv0367dd(struct ngene_channel *chan, -+ struct i2c_adapter *i2c) -+{ -+ struct stv0367_cfg cfg; -+ -+ memset(&cfg, 0, sizeof cfg); -+ cfg.adr = 0x1c + (chan->number ^ 1); -+ -+ chan->fe = dvb_attach(stv0367_attach, i2c, &cfg, &chan->fe2); -+ if (!chan->fe) { -+ printk(KERN_ERR "No stv0367 found!\n"); -+ return -ENODEV; -+ } -+ chan->fe->sec_priv = chan; -+ chan->gate_ctrl = chan->fe->ops.i2c_gate_ctrl; -+ chan->fe->ops.i2c_gate_ctrl = locked_gate_ctrl; - return 0; - } - -@@ -279,6 +419,9 @@ static int cineS2_probe(struct ngene_channel *chan) - } else if (port_has_drxk(i2c, chan->number^2)) { - chan->demod_type = 1; - demod_attach_drxk(chan, i2c); -+ } else if (port_has_stv0367(i2c, chan->number)) { -+ chan->demod_type = 2; -+ demod_attach_stv0367dd(chan, i2c); - } else { - printk(KERN_ERR "No demod found on chan %d\n", chan->number); - return -ENODEV; -@@ -315,249 +458,140 @@ static int demod_attach_lg330x(struct ngene_channel *chan) - return (chan->fe) ? 0 : -ENODEV; - } - --static int demod_attach_drxd(struct ngene_channel *chan) --{ -- struct drxd_config *feconf; -- -- feconf = chan->dev->card_info->fe_config[chan->number]; -- -- chan->fe = dvb_attach(drxd_attach, feconf, chan, -- &chan->i2c_adapter, &chan->dev->pci_dev->dev); -- if (!chan->fe) { -- pr_err("No DRXD found!\n"); -- return -ENODEV; -- } -- return 0; --} -+/****************************************************************************/ -+/* Switch control (I2C gates, etc.) *****************************************/ -+/****************************************************************************/ - --static int tuner_attach_dtt7520x(struct ngene_channel *chan) -+#if 0 -+static int avf_output(struct ngene_channel *chan, int state) - { -- struct drxd_config *feconf; -- -- feconf = chan->dev->card_info->fe_config[chan->number]; -- -- if (!dvb_attach(dvb_pll_attach, chan->fe, feconf->pll_address, -- &chan->i2c_adapter, -- feconf->pll_type)) { -- pr_err("No pll(%d) found!\n", feconf->pll_type); -- return -ENODEV; -- } -+ if (chan->dev->card_info->avf[chan->number]) -+ i2c_write_register(&chan->i2c_adapter, -+ chan->dev->card_info->avf[chan->number], -+ 0xf2, state ? 0x89 : 0x80); - return 0; - } - --/****************************************************************************/ --/* EEPROM TAGS **************************************************************/ --/****************************************************************************/ -- --#define MICNG_EE_START 0x0100 --#define MICNG_EE_END 0x0FF0 -+/* Viper expander: sw11,sw12,sw21,sw22,i2csw1,i2csw2,tsen1,tsen2 */ - --#define MICNG_EETAG_END0 0x0000 --#define MICNG_EETAG_END1 0xFFFF -- --/* 0x0001 - 0x000F reserved for housekeeping */ --/* 0xFFFF - 0xFFFE reserved for housekeeping */ -- --/* Micronas assigned tags -- EEProm tags for hardware support */ -- --#define MICNG_EETAG_DRXD1_OSCDEVIATION 0x1000 /* 2 Bytes data */ --#define MICNG_EETAG_DRXD2_OSCDEVIATION 0x1001 /* 2 Bytes data */ -- --#define MICNG_EETAG_MT2060_1_1STIF 0x1100 /* 2 Bytes data */ --#define MICNG_EETAG_MT2060_2_1STIF 0x1101 /* 2 Bytes data */ -- --/* Tag range for OEMs */ -+static int exp_set(struct ngene *dev) -+{ -+ return i2c_write(&dev->channel[0].i2c_adapter, -+ dev->card_info->exp, dev->exp_val); -+} - --#define MICNG_EETAG_OEM_FIRST 0xC000 --#define MICNG_EETAG_OEM_LAST 0xFFEF -+static int exp_init(struct ngene *dev) -+{ -+ if (!dev->card_info->exp) -+ return 0; -+ dev->exp_val = dev->card_info->exp_init; -+ return exp_set(dev); -+} - --static int i2c_write_eeprom(struct i2c_adapter *adapter, -- u8 adr, u16 reg, u8 data) -+static int exp_set_bit(struct ngene *dev, int bit, int val) - { -- u8 m[3] = {(reg >> 8), (reg & 0xff), data}; -- struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, -- .len = sizeof(m)}; -+ if (val) -+ set_bit(bit, &dev->exp_val); -+ else -+ clear_bit(bit, &dev->exp_val); -+ return exp_set(dev); -+} - -- if (i2c_transfer(adapter, &msg, 1) != 1) { -- pr_err(DEVICE_NAME ": Error writing EEPROM!\n"); -- return -EIO; -+static int viper_switch_ctrl(struct ngene_channel *chan, int type, int val) -+{ -+ switch (type) { -+ case 0: /* I2C tuner gate on/off */ -+ return exp_set_bit(chan->dev, 4 + chan->number, val); -+ case 1: /* Stream: 0=TS 1=ITU */ -+ avf_output(chan, val); -+ return exp_set_bit(chan->dev, 6 + chan->number, val); -+ case 2: /* Input: 0=digital 1=analog antenna input */ -+ exp_set_bit(chan->dev, 0 + chan->number * 2, val ? 0 : 1); -+ exp_set_bit(chan->dev, 1 + chan->number * 2, val ? 1 : 0); -+ break; - } - return 0; - } - --static int i2c_read_eeprom(struct i2c_adapter *adapter, -- u8 adr, u16 reg, u8 *data, int len) -+static int viper_switch_ctrl2(struct ngene_channel *chan, int type, int val) - { -- u8 msg[2] = {(reg >> 8), (reg & 0xff)}; -- struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, -- .buf = msg, .len = 2 }, -- {.addr = adr, .flags = I2C_M_RD, -- .buf = data, .len = len} }; -- -- if (i2c_transfer(adapter, msgs, 2) != 2) { -- pr_err(DEVICE_NAME ": Error reading EEPROM\n"); -- return -EIO; -+ switch (type) { -+ case 0: /* I2C tuner gate on/off */ -+ return exp_set_bit(chan->dev, 4 + chan->number, val); -+ case 1: /* Stream: 0=TS 1=ITU */ -+ avf_output(chan, val); -+ return exp_set_bit(chan->dev, 6 + chan->number, val); -+ case 2: /* Input: 0=digital 1=analog antenna input */ -+ exp_set_bit(chan->dev, 0 + chan->number * 2, val ? 0 : 1); -+ exp_set_bit(chan->dev, 1 + chan->number * 2, 0); -+ break; - } - return 0; - } - --static int ReadEEProm(struct i2c_adapter *adapter, -- u16 Tag, u32 MaxLen, u8 *data, u32 *pLength) -+static int viper_gate_ctrl(struct dvb_frontend *fe, int enable) - { -- int status = 0; -- u16 Addr = MICNG_EE_START, Length, tag = 0; -- u8 EETag[3]; -- -- while (Addr + sizeof(u16) + 1 < MICNG_EE_END) { -- if (i2c_read_eeprom(adapter, 0x50, Addr, EETag, sizeof(EETag))) -- return -1; -- tag = (EETag[0] << 8) | EETag[1]; -- if (tag == MICNG_EETAG_END0 || tag == MICNG_EETAG_END1) -- return -1; -- if (tag == Tag) -- break; -- Addr += sizeof(u16) + 1 + EETag[2]; -- } -- if (Addr + sizeof(u16) + 1 + EETag[2] > MICNG_EE_END) { -- pr_err(DEVICE_NAME -- ": Reached EOEE @ Tag = %04x Length = %3d\n", -- tag, EETag[2]); -- return -1; -- } -- Length = EETag[2]; -- if (Length > MaxLen) -- Length = (u16) MaxLen; -- if (Length > 0) { -- Addr += sizeof(u16) + 1; -- status = i2c_read_eeprom(adapter, 0x50, Addr, data, Length); -- if (!status) { -- *pLength = EETag[2]; --#if 0 -- if (Length < EETag[2]) -- status = STATUS_BUFFER_OVERFLOW; -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19) -+ struct ngene_channel *chan = fe->misc_priv; -+#else /* Why is there no misc_priv available anymore !?!?! */ -+ /* Well, just abuse sec :-) */ -+ struct ngene_channel *chan = fe->sec_priv; - #endif -- } -- } -- return status; -+ struct ngene *dev = chan->dev; -+ -+ return dev->card_info->switch_ctrl(chan, 0, enable); - } - --static int WriteEEProm(struct i2c_adapter *adapter, -- u16 Tag, u32 Length, u8 *data) -+static int python_switch_ctrl(struct ngene_channel *chan, int type, int val) - { -- int status = 0; -- u16 Addr = MICNG_EE_START; -- u8 EETag[3]; -- u16 tag = 0; -- int retry, i; -- -- while (Addr + sizeof(u16) + 1 < MICNG_EE_END) { -- if (i2c_read_eeprom(adapter, 0x50, Addr, EETag, sizeof(EETag))) -- return -1; -- tag = (EETag[0] << 8) | EETag[1]; -- if (tag == MICNG_EETAG_END0 || tag == MICNG_EETAG_END1) -- return -1; -- if (tag == Tag) -- break; -- Addr += sizeof(u16) + 1 + EETag[2]; -- } -- if (Addr + sizeof(u16) + 1 + EETag[2] > MICNG_EE_END) { -- pr_err(DEVICE_NAME -- ": Reached EOEE @ Tag = %04x Length = %3d\n", -- tag, EETag[2]); -- return -1; -- } -- -- if (Length > EETag[2]) -- return -EINVAL; -- /* Note: We write the data one byte at a time to avoid -- issues with page sizes. (which are different for -- each manufacture and eeprom size) -- */ -- Addr += sizeof(u16) + 1; -- for (i = 0; i < Length; i++, Addr++) { -- status = i2c_write_eeprom(adapter, 0x50, Addr, data[i]); -- -- if (status) -- break; -- -- /* Poll for finishing write cycle */ -- retry = 10; -- while (retry) { -- u8 Tmp; -- -- msleep(50); -- status = i2c_read_eeprom(adapter, 0x50, Addr, &Tmp, 1); -- if (status) -- break; -- if (Tmp != data[i]) -- pr_err(DEVICE_NAME -- "eeprom write error\n"); -- retry -= 1; -- } -- if (status) { -- pr_err(DEVICE_NAME -- ": Timeout polling eeprom\n"); -- break; -- } -+ switch (type) { -+ case 0: /* I2C tuner gate on/off */ -+ if (chan->number > 1) -+ return -EINVAL; -+ return ngene_command_gpio_set(chan->dev, 3 + chan->number, val); -+ case 1: /* Stream: 0=TS 1=ITU */ -+ avf_output(chan, val); -+ return 0; - } -- return status; -+ return 0; - } - --static int eeprom_read_ushort(struct i2c_adapter *adapter, u16 tag, u16 *data) -+static int viper_reset_xc(struct dvb_frontend *fe) - { -- int stat; -- u8 buf[2]; -- u32 len = 0; -- -- stat = ReadEEProm(adapter, tag, 2, buf, &len); -- if (stat) -- return stat; -- if (len != 2) -- return -EINVAL; -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19) -+ struct ngene_channel *chan = fe->misc_priv; -+#else -+ struct ngene_channel *chan = fe->sec_priv; -+#endif -+ struct ngene *dev = chan->dev; - -- *data = (buf[0] << 8) | buf[1]; -- return 0; --} -+ printk(KERN_INFO DEVICE_NAME ": Reset XC3028\n"); - --static int eeprom_write_ushort(struct i2c_adapter *adapter, u16 tag, u16 data) --{ -- int stat; -- u8 buf[2]; -+ if (chan->number > 1) -+ return -EINVAL; - -- buf[0] = data >> 8; -- buf[1] = data & 0xff; -- stat = WriteEEProm(adapter, tag, 2, buf); -- if (stat) -- return stat; -+ ngene_command_gpio_set(dev, 3 + chan->number, 0); -+ msleep(150); -+ ngene_command_gpio_set(dev, 3 + chan->number, 1); - return 0; - } - --static s16 osc_deviation(void *priv, s16 deviation, int flag) -+static int python_gate_ctrl(struct dvb_frontend *fe, int enable) - { -- struct ngene_channel *chan = priv; -- struct i2c_adapter *adap = &chan->i2c_adapter; -- u16 data = 0; -- -- if (flag) { -- data = (u16) deviation; -- pr_info(DEVICE_NAME ": write deviation %d\n", -- deviation); -- eeprom_write_ushort(adap, 0x1000 + chan->number, data); -- } else { -- if (eeprom_read_ushort(adap, 0x1000 + chan->number, &data)) -- data = 0; -- pr_info(DEVICE_NAME ": read deviation %d\n", -- (s16) data); -- } -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19) -+ struct ngene_channel *chan = fe->misc_priv; -+#else /* Why is there no misc_priv available anymore !?!?! */ -+ struct ngene_channel *chan = fe->sec_priv; -+#endif -+ struct ngene *dev = chan->dev; - -- return (s16) data; -+ if (chan->number == 0) -+ return ngene_command_gpio_set(dev, 3, enable); -+ if (chan->number == 1) -+ return ngene_command_gpio_set(dev, 4, enable); -+ return -EINVAL; - } -- --/****************************************************************************/ --/* Switch control (I2C gates, etc.) *****************************************/ --/****************************************************************************/ -- -+#endif - - static struct stv090x_config fe_cineS2 = { - .device = STV0900, -@@ -705,14 +739,18 @@ static struct ngene_info ngene_info_m780 = { - .fw_version = 15, - }; - -+/****************************************************************************/ -+ -+#if 0 - static struct drxd_config fe_terratec_dvbt_0 = { - .index = 0, - .demod_address = 0x70, - .demod_revision = 0xa2, - .demoda_address = 0x00, - .pll_address = 0x60, -- .pll_type = DVB_PLL_THOMSON_DTT7520X, -+ .pll_type = DRXD_PLL_DTT7520X, - .clock = 20000, -+ .pll_set = ngene_pll_set_th_dtt7520x, - .osc_deviation = osc_deviation, - }; - -@@ -722,8 +760,9 @@ static struct drxd_config fe_terratec_dvbt_1 = { - .demod_revision = 0xa2, - .demoda_address = 0x00, - .pll_address = 0x60, -- .pll_type = DVB_PLL_THOMSON_DTT7520X, -+ .pll_type = DRXD_PLL_DTT7520X, - .clock = 20000, -+ .pll_set = ngene_pll_set_th_dtt7520x, - .osc_deviation = osc_deviation, - }; - -@@ -732,13 +771,293 @@ static struct ngene_info ngene_info_terratec = { - .name = "Terratec Integra/Cinergy2400i Dual DVB-T", - .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, - .demod_attach = {demod_attach_drxd, demod_attach_drxd}, -- .tuner_attach = {tuner_attach_dtt7520x, tuner_attach_dtt7520x}, - .fe_config = {&fe_terratec_dvbt_0, &fe_terratec_dvbt_1}, - .i2c_access = 1, - }; - - /****************************************************************************/ - -+static struct mt2060_config tuner_python_0 = { -+ .i2c_address = 0x60, -+ .clock_out = 3, -+ .input = 0 -+}; -+ -+static struct mt2060_config tuner_python_1 = { -+ .i2c_address = 0x61, -+ .clock_out = 3, -+ .input = 1 -+}; -+ -+static struct drxd_config fe_python_0 = { -+ .index = 0, -+ .demod_address = 0x71, -+ .demod_revision = 0xb1, -+ .demoda_address = 0x41, -+ .clock = 16000, -+ .osc_deviation = osc_deviation, -+}; -+ -+static struct drxd_config fe_python_1 = { -+ .index = 1, -+ .demod_address = 0x70, -+ .demod_revision = 0xb1, -+ .demoda_address = 0x45, -+ .clock = 16000, -+ .osc_deviation = osc_deviation, -+}; -+ -+static struct ngene_info ngene_info_python = { -+ .type = NGENE_PYTHON, -+ .name = "Micronas MicPython/Hedgehog Dual DVB-T", -+ .io_type = {NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_AIN, NGENE_IO_AIN}, -+ .demod_attach = {demod_attach_drxd, demod_attach_drxd}, -+ .tuner_attach = {tuner_attach_mt2060, tuner_attach_mt2060}, -+ .fe_config = {&fe_python_0, &fe_python_1}, -+ .tuner_config = {&tuner_python_0, &tuner_python_1}, -+ .avf = {0x43, 0x47}, -+ .msp = {0x40, 0x42}, -+ .demoda = {0x41, 0x45}, -+ .gate_ctrl = python_gate_ctrl, -+ .switch_ctrl = python_switch_ctrl, -+}; -+ -+/****************************************************************************/ -+ -+static struct drxd_config fe_appb_dvbt_0 = { -+ .index = 0, -+ .demod_address = 0x71, -+ .demod_revision = 0xa2, -+ .demoda_address = 0x41, -+ .pll_address = 0x63, -+ .pll_type = DRXD_PLL_MT3X0823, -+ .clock = 20000, -+ .pll_set = ngene_pll_set_mt_3x0823, -+ .osc_deviation = osc_deviation, -+}; -+ -+static struct drxd_config fe_appb_dvbt_1 = { -+ .index = 1, -+ .demod_address = 0x70, -+ .demod_revision = 0xa2, -+ .demoda_address = 0x45, -+ .pll_address = 0x60, -+ .pll_type = DRXD_PLL_MT3X0823, -+ .clock = 20000, -+ .pll_set = ngene_pll_set_mt_3x0823, -+ .osc_deviation = osc_deviation, -+}; -+ -+static struct ngene_info ngene_info_appboard = { -+ .type = NGENE_APP, -+ .name = "Micronas Application Board Dual DVB-T", -+ .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, -+ .demod_attach = {demod_attach_drxd, demod_attach_drxd}, -+ .fe_config = {&fe_appb_dvbt_0, &fe_appb_dvbt_1}, -+ .avf = {0x43, 0x47}, -+}; -+ -+static struct ngene_info ngene_info_appboard_ntsc = { -+ .type = NGENE_APP, -+ .name = "Micronas Application Board Dual DVB-T", -+ .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, -+ .demod_attach = {demod_attach_drxd, demod_attach_drxd}, -+ .fe_config = {&fe_appb_dvbt_0, &fe_appb_dvbt_1}, -+ .avf = {0x43, 0x47}, -+ .ntsc = 1, -+}; -+ -+/****************************************************************************/ -+ -+static struct stb0899_config fe_sidewinder_0 = { -+ .demod_address = 0x68, -+ .pll_address = 0x63, -+}; -+ -+static struct stb0899_config fe_sidewinder_1 = { -+ .demod_address = 0x6b, -+ .pll_address = 0x60, -+}; -+ -+static struct ngene_info ngene_info_sidewinder = { -+ .type = NGENE_SIDEWINDER, -+ .name = "Micronas MicSquirrel/Sidewinder Dual DVB-S2", -+ .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, -+ .demod_attach = {demod_attach_stb0899, demod_attach_stb0899}, -+ .fe_config = {&fe_sidewinder_0, &fe_sidewinder_1}, -+ .lnb = {0x0b, 0x08}, -+}; -+ -+/****************************************************************************/ -+/* Yet unnamed S2 card with dual DVB-S2 demod */ -+/****************************************************************************/ -+ -+static struct stv0900_config fe_s2_0 = { -+ .addr = 0x68, -+ .pll = 0x63, -+ .pll_type = 0, -+ .nr = 0, -+}; -+ -+static struct stv0900_config fe_s2_1 = { -+ .addr = 0x68, -+ .pll = 0x60, -+ .pll_type = 0, -+ .nr = 1, -+}; -+ -+static struct ngene_info ngene_info_s2 = { -+ .type = NGENE_SIDEWINDER, -+ .name = "S2", -+ .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN, -+ NGENE_IO_TSIN, NGENE_IO_TSIN}, -+ .demod_attach = {demod_attach_stv0900, demod_attach_stv0900}, -+ .fe_config = {&fe_s2_0, &fe_s2_1}, -+ .lnb = {0x0b, 0x08}, -+ .tsf = {3, 3}, -+ .fw_version = 15, -+}; -+ -+static struct stv0900_config fe_s2b_0 = { -+ .addr = 0x68, -+ .pll = 0x60, -+ .pll_type = 0x10, -+ .nr = 0, -+}; -+ -+static struct stv0900_config fe_s2b_1 = { -+ .addr = 0x68, -+ .pll = 0x63, -+ .pll_type = 0x10, -+ .nr = 1, -+}; -+ -+static struct ngene_info ngene_info_s2_b = { -+ .type = NGENE_SIDEWINDER, -+ .name = "S2 V2", -+ .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN, -+ NGENE_IO_TSIN, NGENE_IO_TSIN}, -+ .demod_attach = {demod_attach_stv0900, demod_attach_stv0900}, -+ .fe_config = {&fe_s2b_0, &fe_s2b_1}, -+ .lnb = {0x0b, 0x08}, -+ .tsf = {3, 3}, -+ .fw_version = 17, -+}; -+ -+/****************************************************************************/ -+ -+static struct xc3028_config tuner_viper_0 = { -+ .adr = 0x61, -+ .reset = viper_reset_xc -+}; -+ -+static struct xc3028_config tuner_viper_1 = { -+ .adr = 0x64, -+ .reset = viper_reset_xc -+}; -+ -+static struct drxh_config fe_viper_h_0 = {.adr = 0x2b}; -+ -+static struct drxh_config fe_viper_h_1 = {.adr = 0x29}; -+ -+static struct drxh_config fe_viper_l_0 = {.adr = 0x2b, .type = 3931}; -+ -+static struct drxh_config fe_viper_l_1 = {.adr = 0x29, .type = 3931}; -+ -+static struct ngene_info ngene_info_viper_v1 = { -+ .type = NGENE_VIPER, -+ .name = "Micronas MicViper Dual ATSC DRXH", -+ .io_type = {NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_AIN, NGENE_IO_AIN}, -+ .demod_attach = {demod_attach_drxh, demod_attach_drxh}, -+ .fe_config = {&fe_viper_h_0, &fe_viper_h_1}, -+ .tuner_config = {&tuner_viper_0, &tuner_viper_1}, -+ .tuner_attach = {tuner_attach_xc3028, tuner_attach_xc3028}, -+ .avf = {0x43, 0x47}, -+ .msp = {0x40, 0x42}, -+ .exp = 0x20, -+ .exp_init = 0xf5, -+ .gate_ctrl = viper_gate_ctrl, -+ .switch_ctrl = viper_switch_ctrl, -+ .tsf = {2, 2}, -+}; -+ -+static struct ngene_info ngene_info_viper_v2 = { -+ .type = NGENE_VIPER, -+ .name = "Micronas MicViper Dual ATSC DRXL", -+ .io_type = {NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_AIN, NGENE_IO_AIN}, -+ .demod_attach = {demod_attach_drxh, demod_attach_drxh}, -+ .fe_config = {&fe_viper_l_0, &fe_viper_l_1}, -+ .tuner_config = {&tuner_viper_0, &tuner_viper_1}, -+ .tuner_attach = {tuner_attach_xc3028, tuner_attach_xc3028}, -+ .avf = {0x43, 0x47}, -+ .msp = {0x40, 0x42}, -+ .exp = 0x38, -+ .exp_init = 0xf5, -+ .gate_ctrl = viper_gate_ctrl, -+ .switch_ctrl = viper_switch_ctrl, -+ .tsf = {2, 2}, -+}; -+ -+/****************************************************************************/ -+ -+static struct ngene_info ngene_info_vbox_v1 = { -+ .type = NGENE_VBOX_V1, -+ .name = "VBox Cat's Eye 164E", -+ .io_type = {NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_AIN, NGENE_IO_AIN}, -+ .demod_attach = {demod_attach_drxh, demod_attach_drxh}, -+ .fe_config = {&fe_viper_h_0, &fe_viper_h_1}, -+ .tuner_config = {&tuner_viper_0, &tuner_viper_1}, -+ .tuner_attach = {tuner_attach_xc3028, tuner_attach_xc3028}, -+ .avf = {0x43, 0x47}, -+ .msp = {0x40, 0x42}, -+ .exp = 0x20, -+ .exp_init = 0xf5, -+ .gate_ctrl = viper_gate_ctrl, -+ .switch_ctrl = viper_switch_ctrl, -+ .tsf = {2, 2}, -+}; -+ -+/****************************************************************************/ -+ -+static struct ngene_info ngene_info_vbox_v2 = { -+ .type = NGENE_VBOX_V2, -+ .name = "VBox Cat's Eye 164E", -+ .io_type = {NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_AIN, NGENE_IO_AIN}, -+ .demod_attach = {demod_attach_drxh, demod_attach_drxh}, -+ .fe_config = {&fe_viper_h_0, &fe_viper_h_1}, -+ .tuner_config = {&tuner_viper_0, &tuner_viper_1}, -+ .tuner_attach = {tuner_attach_xc3028, tuner_attach_xc3028}, -+ .avf = {0x43, 0x47}, -+ .msp = {0x40, 0x42}, -+ .exp = 0x20, -+ .exp_init = 0xf5, -+ .gate_ctrl = viper_gate_ctrl, -+ .switch_ctrl = viper_switch_ctrl2, -+ .tsf = {2, 2}, -+}; -+ -+/****************************************************************************/ -+ -+static struct ngene_info ngene_info_racer = { -+ .type = NGENE_RACER, -+ .name = "Micronas MicRacer HDTV Decoder Card", -+ .io_type = {NGENE_IO_HDTV, NGENE_IO_NONE, -+ NGENE_IO_AIN, NGENE_IO_NONE, -+ NGENE_IO_TSOUT}, -+ .i2s = {0, 0, 1, 0}, -+ .fw_version = 17, -+}; -+#endif - - - /****************************************************************************/ -@@ -753,6 +1072,8 @@ static struct ngene_info ngene_info_terratec = { - /****************************************************************************/ - - static const struct pci_device_id ngene_id_tbl[] = { -+ NGENE_ID(0x18c3, 0xab04, ngene_info_cineS2), -+ NGENE_ID(0x18c3, 0xab05, ngene_info_cineS2v5), - NGENE_ID(0x18c3, 0xabc3, ngene_info_cineS2), - NGENE_ID(0x18c3, 0xabc4, ngene_info_cineS2), - NGENE_ID(0x18c3, 0xdb01, ngene_info_satixS2), -@@ -761,7 +1082,32 @@ static const struct pci_device_id ngene_id_tbl[] = { - NGENE_ID(0x18c3, 0xdd10, ngene_info_duoFlex), - NGENE_ID(0x18c3, 0xdd20, ngene_info_duoFlex), - NGENE_ID(0x1461, 0x062e, ngene_info_m780), -+#if 0 /* not (yet?) supported */ -+ NGENE_ID(0x18c3, 0x0000, ngene_info_appboard), -+ NGENE_ID(0x18c3, 0x0004, ngene_info_appboard), -+ NGENE_ID(0x18c3, 0x8011, ngene_info_appboard), -+ NGENE_ID(0x18c3, 0x8015, ngene_info_appboard_ntsc), - NGENE_ID(0x153b, 0x1167, ngene_info_terratec), -+ NGENE_ID(0x18c3, 0x0030, ngene_info_python), -+ NGENE_ID(0x18c3, 0x0052, ngene_info_sidewinder), -+ NGENE_ID(0x18c3, 0x8f00, ngene_info_racer), -+ NGENE_ID(0x18c3, 0x0041, ngene_info_viper_v1), -+ NGENE_ID(0x18c3, 0x0042, ngene_info_viper_v2), -+ NGENE_ID(0x14f3, 0x0041, ngene_info_vbox_v1), -+ NGENE_ID(0x14f3, 0x0043, ngene_info_vbox_v2), -+ NGENE_ID(0x18c3, 0xabcd, ngene_info_s2), -+ NGENE_ID(0x18c3, 0xabc2, ngene_info_s2_b), -+ NGENE_ID(0x18c3, 0xabc3, ngene_info_s2_b), -+ NGENE_ID(0x18c3, 0x0001, ngene_info_appboard), -+ NGENE_ID(0x18c3, 0x0005, ngene_info_appboard), -+ NGENE_ID(0x18c3, 0x0009, ngene_info_appboard_atsc), -+ NGENE_ID(0x18c3, 0x000b, ngene_info_appboard_atsc), -+ NGENE_ID(0x18c3, 0x0010, ngene_info_shrek_50_fp), -+ NGENE_ID(0x18c3, 0x0011, ngene_info_shrek_60_fp), -+ NGENE_ID(0x18c3, 0x0012, ngene_info_shrek_50), -+ NGENE_ID(0x18c3, 0x0013, ngene_info_shrek_60), -+ NGENE_ID(0x18c3, 0x0000, ngene_info_hognose), -+#endif - {0} - }; - MODULE_DEVICE_TABLE(pci, ngene_id_tbl); -@@ -798,7 +1144,7 @@ static void ngene_resume(struct pci_dev *dev) - printk(KERN_INFO DEVICE_NAME ": resume\n"); - } - --static const struct pci_error_handlers ngene_errors = { -+static struct pci_error_handlers ngene_errors = { - .error_detected = ngene_error_detected, - .link_reset = ngene_link_reset, - .slot_reset = ngene_slot_reset, -diff --git a/drivers/media/pci/ngene/ngene-core.c b/drivers/media/pci/ngene/ngene-core.c -index 37ebc42..84510db 100644 ---- a/drivers/media/pci/ngene/ngene-core.c -+++ b/drivers/media/pci/ngene/ngene-core.c -@@ -86,6 +86,14 @@ static void event_tasklet(unsigned long data) - if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify)) - dev->RxEventNotify(dev, Event.TimeStamp, - Event.RXCharacter); -+#if 0 -+ if ((Event.GPIOStatus & 0x80) && (dev->Gpio2EventNotify)) -+ dev->Gpio2EventNotify(dev, Event.TimeStamp, -+ Event.GPIOStatus & 0x1f); -+ if ((Event.GPIOStatus & 0x40) && (dev->Gpio3EventNotify)) -+ dev->Gpio3EventNotify(dev, Event.TimeStamp, -+ Event.GPIOStatus & 0x1f); -+#endif - } - } - -@@ -214,6 +222,13 @@ static irqreturn_t irq_handler(int irq, void *dev_id) - u8 nextWriteIndex = - (dev->EventQueueWriteIndex + 1) & - (EVENT_QUEUE_SIZE - 1); -+#if 0 -+ printk(KERN_ERR DEVICE_NAME -+ ": Event interrupt %02x Uart = %02x Gpio = %02x\n", -+ dev->EventBuffer->EventStatus, -+ dev->EventBuffer->UARTStatus, -+ dev->EventBuffer->GPIOStatus); -+#endif - if (nextWriteIndex != dev->EventQueueReadIndex) { - dev->EventQueue[dev->EventQueueWriteIndex] = - *(dev->EventBuffer); -@@ -258,16 +273,22 @@ static void dump_command_io(struct ngene *dev) - u8 buf[8], *b; - - ngcpyfrom(buf, HOST_TO_NGENE, 8); -- printk(KERN_ERR "host_to_ngene (%04x): %*ph\n", HOST_TO_NGENE, 8, buf); -+ printk(KERN_ERR "host_to_ngene (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n", -+ HOST_TO_NGENE, buf[0], buf[1], buf[2], buf[3], -+ buf[4], buf[5], buf[6], buf[7]); - - ngcpyfrom(buf, NGENE_TO_HOST, 8); -- printk(KERN_ERR "ngene_to_host (%04x): %*ph\n", NGENE_TO_HOST, 8, buf); -+ printk(KERN_ERR "ngene_to_host (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n", -+ NGENE_TO_HOST, buf[0], buf[1], buf[2], buf[3], -+ buf[4], buf[5], buf[6], buf[7]); - - b = dev->hosttongene; -- printk(KERN_ERR "dev->hosttongene (%p): %*ph\n", b, 8, b); -+ printk(KERN_ERR "dev->hosttongene (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n", -+ b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]); - - b = dev->ngenetohost; -- printk(KERN_ERR "dev->ngenetohost (%p): %*ph\n", b, 8, b); -+ printk(KERN_ERR "dev->ngenetohost (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n", -+ b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]); - } - - static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com) -@@ -316,12 +337,24 @@ static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com) - ngwritel(1, FORCE_INT); - - ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ); -+#if 0 -+ if (ret < 0) -+ return ret; -+ if (!dev->cmd_done) -+ ; -+#endif - if (!ret) { - /*ngwritel(0, FORCE_NMI);*/ - - printk(KERN_ERR DEVICE_NAME - ": Command timeout cmd=%02x prev=%02x\n", - com->cmd.hdr.Opcode, dev->prev_cmd); -+#if 0 -+ printk(KERN_ERR DEVICE_NAME ": Icounts=%08x\n", -+ ngreadl(NGENE_INT_COUNTS)); -+ if (ngreadl(NGENE_INT_COUNTS) == 0xffffffff) -+ ngwritel(0, NGENE_INT_ENABLE); -+#endif - dump_command_io(dev); - return -1; - } -@@ -348,6 +381,19 @@ int ngene_command(struct ngene *dev, struct ngene_command *com) - return result; - } - -+#if 0 -+int ngene_command_nop(struct ngene *dev) -+{ -+ struct ngene_command com; -+ -+ com.cmd.hdr.Opcode = CMD_NOP; -+ com.cmd.hdr.Length = 0; -+ com.in_len = 0; -+ com.out_len = 0; -+ -+ return ngene_command(dev, &com); -+} -+#endif - - static int ngene_command_load_firmware(struct ngene *dev, - u8 *ngene_fw, u32 size) -@@ -382,6 +428,83 @@ static int ngene_command_load_firmware(struct ngene *dev, - return ngene_command(dev, &com); - } - -+#if 0 -+int ngene_command_imem_read(struct ngene *dev, u8 adr, u8 *data, int type) -+{ -+ struct ngene_command com; -+ -+ com.cmd.hdr.Opcode = type ? CMD_SFR_READ : CMD_IRAM_READ; -+ com.cmd.hdr.Length = 1; -+ com.cmd.SfrIramRead.address = adr; -+ com.in_len = 1; -+ com.out_len = 2; -+ -+ if (ngene_command(dev, &com) < 0) -+ return -EIO; -+ -+ *data = com.cmd.raw8[1]; -+ return 0; -+} -+ -+int ngene_command_imem_write(struct ngene *dev, u8 adr, u8 data, int type) -+{ -+ struct ngene_command com; -+ -+ com.cmd.hdr.Opcode = type ? CMD_SFR_WRITE : CMD_IRAM_WRITE; -+ com.cmd.hdr.Length = 2; -+ com.cmd.SfrIramWrite.address = adr; -+ com.cmd.SfrIramWrite.data = data; -+ com.in_len = 2; -+ com.out_len = 1; -+ -+ if (ngene_command(dev, &com) < 0) -+ return -EIO; -+ -+ return 0; -+} -+ -+static int ngene_command_config_uart(struct ngene *dev, u8 config, -+ tx_cb_t *tx_cb, rx_cb_t *rx_cb) -+{ -+ struct ngene_command com; -+ -+ com.cmd.hdr.Opcode = CMD_CONFIGURE_UART; -+ com.cmd.hdr.Length = sizeof(struct FW_CONFIGURE_UART) - 2; -+ com.cmd.ConfigureUart.UartControl = config; -+ com.in_len = sizeof(struct FW_CONFIGURE_UART); -+ com.out_len = 0; -+ -+ if (ngene_command(dev, &com) < 0) -+ return -EIO; -+ -+ dev->TxEventNotify = tx_cb; -+ dev->RxEventNotify = rx_cb; -+ -+ dprintk(KERN_DEBUG DEVICE_NAME ": Set UART config %02x.\n", config); -+ -+ return 0; -+} -+ -+static void tx_cb(struct ngene *dev, u32 ts) -+{ -+ dev->tx_busy = 0; -+ wake_up_interruptible(&dev->tx_wq); -+} -+ -+static void rx_cb(struct ngene *dev, u32 ts, u8 c) -+{ -+ int rp = dev->uart_rp; -+ int nwp, wp = dev->uart_wp; -+ -+ /* dprintk(KERN_DEBUG DEVICE_NAME ": %c\n", c); */ -+ nwp = (wp + 1) % (UART_RBUF_LEN); -+ if (nwp == rp) -+ return; -+ dev->uart_rbuf[wp] = c; -+ dev->uart_wp = nwp; -+ wake_up_interruptible(&dev->rx_wq); -+} -+#endif - - static int ngene_command_config_buf(struct ngene *dev, u8 config) - { -@@ -427,6 +550,18 @@ int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level) - return ngene_command(dev, &com); - } - -+#if 0 -+/* The reset is only wired to GPIO4 on MicRacer Revision 1.10 ! -+ Also better set bootdelay to 1 in nvram or less. */ -+static void ngene_reset_decypher(struct ngene *dev) -+{ -+ printk(KERN_INFO DEVICE_NAME ": Resetting Decypher.\n"); -+ ngene_command_gpio_set(dev, 4, 0); -+ msleep(1); -+ ngene_command_gpio_set(dev, 4, 1); -+ msleep(2000); -+} -+#endif - - /* - 02000640 is sample on rising edge. -@@ -512,6 +647,17 @@ void FillTSBuffer(void *Buffer, int Length, u32 Flags) - } - } - -+#if 0 -+static void clear_tsin(struct ngene_channel *chan) -+{ -+ struct SBufferHeader *Cur = chan->nextBuffer; -+ -+ do { -+ memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR)); -+ Cur = Cur->Next; -+ } while (Cur != chan->nextBuffer); -+} -+#endif - - static void flush_buffers(struct ngene_channel *chan) - { -@@ -732,6 +878,14 @@ void set_transfer(struct ngene_channel *chan, int state) - if (dev->card_info->switch_ctrl) - dev->card_info->switch_ctrl(chan, 1, state ^ 1); - -+#if 0 -+ /* Disable AVF output if present. */ -+ if (dev->card_info->avf[chan->number]) -+ i2c_write_register(&chan->i2c_adapter, -+ chan->dev->card_info->avf[chan->number], -+ 0xf2, state ? 0x80 : 0x89); -+ -+#endif - if (state) { - spin_lock_irq(&chan->state_lock); - -@@ -752,8 +906,8 @@ void set_transfer(struct ngene_channel *chan, int state) - if (chan->mode & NGENE_IO_TSIN) - chan->pBufferExchange = tsin_exchange; - spin_unlock_irq(&chan->state_lock); -- } -- /* else printk(KERN_INFO DEVICE_NAME ": lock=%08x\n", -+ } else -+ ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n", - ngreadl(0x9310)); */ - - ret = ngene_command_stream_control(dev, chan->number, -@@ -771,6 +925,89 @@ void set_transfer(struct ngene_channel *chan, int state) - } - } - -+#if 0 -+/****************************************************************************/ -+/* Decypher firmware loading ************************************************/ -+/****************************************************************************/ -+ -+#define DECYPHER_FW "decypher.fw" -+ -+static int dec_ts_send(struct ngene *dev, u8 *buf, u32 len) -+{ -+#if 0 -+ if (wait_event_interruptible(dev->tsout_rbuf.queue, -+ dvb_ringbuffer_free -+ (&dev->tsout_rbuf) >= len) < 0) -+ return 0; -+#else -+ while (dvb_ringbuffer_free(&dev->tsout_rbuf) < len) -+ msleep(1); -+ -+#endif -+ -+ dvb_ringbuffer_write(&dev->tsout_rbuf, buf, len); -+ -+ return len; -+} -+ -+u8 dec_fw_fill_ts[188] = { 0x47, 0x09, 0x0e, 0x10, 0xff, 0xff, 0x00, 0x00 }; -+ -+int dec_fw_send(struct ngene *dev, u8 *fw, u32 size) -+{ -+ struct ngene_channel *chan = &dev->channel[4]; -+ u32 len = 180, cc = 0; -+ u8 buf[8] = { 0x47, 0x09, 0x0e, 0x10, 0x00, 0x00, 0x00, 0x00 }; -+ -+ set_transfer(chan, 1); -+ msleep(100); -+ while (size) { -+ len = 180; -+ if (len > size) -+ len = size; -+ buf[3] = 0x10 | (cc & 0x0f); -+ buf[4] = (cc >> 8); -+ buf[5] = cc & 0xff; -+ buf[6] = len; -+ -+ dec_ts_send(dev, buf, 8); -+ dec_ts_send(dev, fw, len); -+ if (len < 180) -+ dec_ts_send(dev, dec_fw_fill_ts + len + 8, 180 - len); -+ cc++; -+ size -= len; -+ fw += len; -+ } -+ for (len = 0; len < 512; len++) -+ dec_ts_send(dev, dec_fw_fill_ts, 188); -+ while (dvb_ringbuffer_avail(&dev->tsout_rbuf)) -+ msleep(10); -+ msleep(100); -+ set_transfer(chan, 0); -+ return 0; -+} -+ -+int dec_fw_boot(struct ngene *dev) -+{ -+ u32 size; -+ const struct firmware *fw = NULL; -+ u8 *dec_fw; -+ -+ if (request_firmware(&fw, DECYPHER_FW, &dev->pci_dev->dev) < 0) { -+ printk(KERN_ERR DEVICE_NAME -+ ": %s not found. Check hotplug directory.\n", -+ DECYPHER_FW); -+ return -1; -+ } -+ printk(KERN_INFO DEVICE_NAME ": Booting decypher firmware file %s\n", -+ DECYPHER_FW); -+ -+ size = fw->size; -+ dec_fw = (u8 *)fw->data; -+ dec_fw_send(dev, dec_fw, size); -+ release_firmware(fw); -+ return 0; -+} -+#endif - - /****************************************************************************/ - /* nGene hardware init and release functions ********************************/ -@@ -1065,6 +1302,85 @@ static u32 Buffer2Sizes[MAX_STREAM] = { - 0 - }; - -+#if 0 -+static int allocate_buffer(struct pci_dev *pci_dev, dma_addr_t of, -+ struct SRingBufferDescriptor *rbuf, -+ u32 entries, u32 size1, u32 size2) -+{ -+ if (create_ring_buffer(pci_dev, rbuf, entries) < 0) -+ return -ENOMEM; -+ -+ if (AllocateRingBuffers(pci_dev, of, rbuf, size1, size2) < 0) -+ return -ENOMEM; -+ -+ return 0; -+} -+ -+static int channel_allocate_buffers(struct ngene_channel *chan) -+{ -+ struct ngene *dev = chan->dev; -+ int type = dev->card_info->io_type[chan->number]; -+ int status; -+ -+ chan->State = KSSTATE_STOP; -+ -+ if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) { -+ status = create_ring_buffer(dev->pci_dev, -+ &chan->RingBuffer, -+ RingBufferSizes[chan->number]); -+ if (status < 0) -+ return -ENOMEM; -+ -+ if (type & (NGENE_IO_TV | NGENE_IO_AIN)) { -+ status = AllocateRingBuffers(dev->pci_dev, -+ dev->PAOverflowBuffer, -+ &chan->RingBuffer, -+ Buffer1Sizes[chan->number], -+ Buffer2Sizes[chan-> -+ number]); -+ if (status < 0) -+ return -ENOMEM; -+ } else if (type & NGENE_IO_HDTV) { -+ status = AllocateRingBuffers(dev->pci_dev, -+ dev->PAOverflowBuffer, -+ &chan->RingBuffer, -+ MAX_HDTV_BUFFER_SIZE, 0); -+ if (status < 0) -+ return -ENOMEM; -+ } -+ } -+ -+ if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { -+ -+ status = create_ring_buffer(dev->pci_dev, -+ &chan->TSRingBuffer, RING_SIZE_TS); -+ if (status < 0) -+ return -ENOMEM; -+ -+ status = AllocateRingBuffers(dev->pci_dev, -+ dev->PAOverflowBuffer, -+ &chan->TSRingBuffer, -+ MAX_TS_BUFFER_SIZE, 0); -+ if (status) -+ return -ENOMEM; -+ } -+ -+ if (type & NGENE_IO_TSOUT) { -+ status = create_ring_buffer(dev->pci_dev, -+ &chan->TSIdleBuffer, 1); -+ if (status < 0) -+ return -ENOMEM; -+ status = AllocateRingBuffers(dev->pci_dev, -+ dev->PAOverflowBuffer, -+ &chan->TSIdleBuffer, -+ MAX_TS_BUFFER_SIZE, 0); -+ if (status) -+ return -ENOMEM; -+ FillTSIdleBuffer(&chan->TSIdleBuffer, &chan->TSRingBuffer); -+ } -+ return 0; -+} -+#endif - - static int AllocCommonBuffers(struct ngene *dev) - { -@@ -1318,6 +1634,10 @@ static int ngene_buffer_config(struct ngene *dev) - u8 tsin12_config[6] = { 0x60, 0x60, 0x00, 0x00, 0x00, 0x00 }; - u8 tsin1234_config[6] = { 0x30, 0x30, 0x00, 0x30, 0x30, 0x00 }; - u8 tsio1235_config[6] = { 0x30, 0x30, 0x00, 0x28, 0x00, 0x38 }; -+#if 0 -+ u8 tsin34_config[6] = { 0x00, 0x00, 0x00, 0x60, 0x60, 0x00 }; -+ u8 tsio35_config[6] = { 0x00, 0x00, 0x00, 0x60, 0x00, 0x60 }; -+#endif - u8 *bconf = tsin12_config; - - if (dev->card_info->io_type[2]&NGENE_IO_TSIN && -@@ -1327,10 +1647,22 @@ static int ngene_buffer_config(struct ngene *dev) - dev->ci.en) - bconf = tsio1235_config; - } -+#if 0 -+ if (dev->card_info->io_type[0] == NGENE_IO_HDTV) { -+ bconf = hdtv_config; -+ ngene_reset_decypher(dev); -+ } -+#endif - stat = ngene_command_config_free_buf(dev, bconf); - } else { - int bconf = BUFFER_CONFIG_4422; - -+#if 0 -+ if (dev->card_info->io_type[0] == NGENE_IO_HDTV) { -+ bconf = BUFFER_CONFIG_8022; -+ ngene_reset_decypher(dev); -+ } -+#endif - if (dev->card_info->io_type[3] == NGENE_IO_TSIN) - bconf = BUFFER_CONFIG_3333; - stat = ngene_command_config_buf(dev, bconf); -@@ -1403,8 +1735,10 @@ static int ngene_start(struct ngene *dev) - if (stat < 0) - goto fail; - -- return 0; -+ if (!stat) -+ return stat; - -+ /* otherwise error: fall through */ - fail: - ngwritel(0, NGENE_INT_ENABLE); - free_irq(dev->pci_dev->irq, dev); -@@ -1688,10 +2022,36 @@ int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) - - - dev->i2c_current_bus = -1; -+#if 0 -+ exp_init(dev); -+ -+ /* Disable analog TV decoder chips if present */ -+ if (dev->card_info->msp[0]) -+ i2c_write_msp_register(&dev->channel[0].i2c_adapter, -+ dev->card_info->msp[0], 0x00, 0x0000); -+ if (dev->card_info->msp[1]) -+ i2c_write_msp_register(&dev->channel[1].i2c_adapter, -+ dev->card_info->msp[1], 0x00, 0x0000); -+ { -+ u16 data; -+ read_msp(&dev->channel[0].i2c_adapter, -+ dev->card_info->msp[0], 0x00, &data); -+ } -+ if (dev->card_info->avf[0]) -+ i2c_write_register(&dev->channel[0].i2c_adapter, -+ dev->card_info->avf[0], 0xf2, 0x80); -+ if (dev->card_info->avf[1]) -+ i2c_write_register(&dev->channel[1].i2c_adapter, -+ dev->card_info->avf[1], 0xf2, 0x80); -+ if (copy_eeprom) { -+ i2c_copy_eeprom(&dev->channel[0].i2c_adapter, 0x50, 0x52); -+ i2c_dump_eeprom(&dev->channel[0].i2c_adapter, 0x52); -+ } -+ /*i2c_check_eeprom(&dev->i2c_adapter);*/ -+#endif - - /* Register DVB adapters and devices for both channels */ -- stat = init_channels(dev); -- if (stat < 0) -+ if (init_channels(dev) < 0) - goto fail2; - - return 0; -diff --git a/drivers/media/pci/ngene/ngene-dvb.c b/drivers/media/pci/ngene/ngene-dvb.c -index fcb16a6..8049e2b 100644 ---- a/drivers/media/pci/ngene/ngene-dvb.c -+++ b/drivers/media/pci/ngene/ngene-dvb.c -@@ -42,10 +42,319 @@ - - #include "ngene.h" - -+#if 0 -+int ngene_stream_control(struct ngene *dev, u8 stream, u8 control, u8 mode, -+ u16 lines, u16 bpl, u16 vblines, u16 vbibpl) -+{ -+ if (!(mode & SMODE_TRANSPORT_STREAM)) -+ return -EINVAL; -+ -+ if (lines * bpl > MAX_VIDEO_BUFFER_SIZE) -+ return -EINVAL; -+ -+ if ((mode & SMODE_TRANSPORT_STREAM) && (((bpl * lines) & 0xff) != 0)) -+ return -EINVAL; -+ -+ if ((mode & SMODE_VIDEO_CAPTURE) && (bpl & 7) != 0) -+ return -EINVAL; -+ -+ return ngene_command_stream_control(dev, stream, control, mode, 0); -+} -+#endif - - /****************************************************************************/ - /* COMMAND API interface ****************************************************/ - /****************************************************************************/ -+#if 0 -+ -+static int command_do_ioctl(struct inode *inode, struct file *file, -+ unsigned int cmd, void *parg) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ int err = 0; -+ -+ switch (cmd) { -+ case IOCTL_MIC_NO_OP: -+ err = ngene_command_nop(dev); -+ break; -+ -+ case IOCTL_MIC_DOWNLOAD_FIRMWARE: -+ break; -+ -+ case IOCTL_MIC_I2C_READ: -+ { -+ MIC_I2C_READ *msg = parg; -+ -+ err = ngene_command_i2c_read(dev, msg->I2CAddress >> 1, -+ msg->OutData, msg->OutLength, -+ msg->OutData, msg->InLength, 1); -+ break; -+ } -+ -+ case IOCTL_MIC_I2C_WRITE: -+ { -+ MIC_I2C_WRITE *msg = parg; -+ -+ err = ngene_command_i2c_write(dev, msg->I2CAddress >> 1, -+ msg->Data, msg->Length); -+ break; -+ } -+ -+ case IOCTL_MIC_TEST_GETMEM: -+ { -+ MIC_MEM *m = parg; -+ -+ if (m->Length > 64 * 1024 || m->Start + m->Length > 64 * 1024) -+ return -EINVAL; -+ -+ /* WARNING, only use this on x86, -+ other archs may not swallow this */ -+ err = copy_to_user(m->Data, dev->iomem + m->Start, m->Length); -+ break; -+ } -+ -+ case IOCTL_MIC_TEST_SETMEM: -+ { -+ MIC_MEM *m = parg; -+ -+ if (m->Length > 64 * 1024 || m->Start + m->Length > 64 * 1024) -+ return -EINVAL; -+ -+ err = copy_from_user(dev->iomem + m->Start, m->Data, m->Length); -+ break; -+ } -+ -+ case IOCTL_MIC_SFR_READ: -+ { -+ MIC_IMEM *m = parg; -+ -+ err = ngene_command_imem_read(dev, m->Address, &m->Data, 1); -+ break; -+ } -+ -+ case IOCTL_MIC_SFR_WRITE: -+ { -+ MIC_IMEM *m = parg; -+ -+ err = ngene_command_imem_write(dev, m->Address, m->Data, 1); -+ break; -+ } -+ -+ case IOCTL_MIC_IRAM_READ: -+ { -+ MIC_IMEM *m = parg; -+ -+ err = ngene_command_imem_read(dev, m->Address, &m->Data, 0); -+ break; -+ } -+ -+ case IOCTL_MIC_IRAM_WRITE: -+ { -+ MIC_IMEM *m = parg; -+ -+ err = ngene_command_imem_write(dev, m->Address, m->Data, 0); -+ break; -+ } -+ -+ case IOCTL_MIC_STREAM_CONTROL: -+ { -+ MIC_STREAM_CONTROL *m = parg; -+ -+ err = ngene_stream_control(dev, m->Stream, m->Control, m->Mode, -+ m->nLines, m->nBytesPerLine, -+ m->nVBILines, m->nBytesPerVBILine); -+ break; -+ } -+ -+ default: -+ err = -EINVAL; -+ break; -+ } -+ return err; -+} -+ -+static int command_ioctl(struct inode *inode, struct file *file, -+ unsigned int cmd, unsigned long arg) -+{ -+ void *parg = (void *)arg, *pbuf = NULL; -+ char buf[64]; -+ int res = -EFAULT; -+ -+ if (_IOC_DIR(cmd) & _IOC_WRITE) { -+ parg = buf; -+ if (_IOC_SIZE(cmd) > sizeof(buf)) { -+ pbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL); -+ if (!pbuf) -+ return -ENOMEM; -+ parg = pbuf; -+ } -+ if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd))) -+ goto error; -+ } -+ res = command_do_ioctl(inode, file, cmd, parg); -+ if (res < 0) -+ goto error; -+ if (_IOC_DIR(cmd) & _IOC_READ) -+ if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd))) -+ res = -EFAULT; -+error: -+ kfree(pbuf); -+ return res; -+} -+ -+struct page *ngene_nopage(struct vm_area_struct *vma, -+ unsigned long address, int *type) -+{ -+ return 0; -+} -+ -+static int ngene_mmap(struct file *file, struct vm_area_struct *vma) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ -+ unsigned long size = vma->vm_end - vma->vm_start; -+ unsigned long off = vma->vm_pgoff << PAGE_SHIFT; -+ unsigned long padr = pci_resource_start(dev->pci_dev, 0) + off; -+ unsigned long psize = pci_resource_len(dev->pci_dev, 0) - off; -+ -+ if (size > psize) -+ return -EINVAL; -+ -+ if (io_remap_pfn_range(vma, vma->vm_start, padr >> PAGE_SHIFT, size, -+ vma->vm_page_prot)) -+ return -EAGAIN; -+ return 0; -+} -+ -+ -+static int write_uart(struct ngene *dev, u8 *data, int len) -+{ -+ struct ngene_command com; -+ -+ com.cmd.hdr.Opcode = CMD_WRITE_UART; -+ com.cmd.hdr.Length = len; -+ memcpy(com.cmd.WriteUart.Data, data, len); -+ com.cmd.WriteUart.Data[len] = 0; -+ com.cmd.WriteUart.Data[len + 1] = 0; -+ com.in_len = len; -+ com.out_len = 0; -+ -+ if (ngene_command(dev, &com) < 0) -+ return -EIO; -+ -+ return 0; -+} -+ -+static int send_cli(struct ngene *dev, char *cmd) -+{ -+ /* printk(KERN_INFO DEVICE_NAME ": %s", cmd); */ -+ return write_uart(dev, cmd, strlen(cmd)); -+} -+ -+static int send_cli_val(struct ngene *dev, char *cmd, u32 val) -+{ -+ char s[32]; -+ -+ snprintf(s, 32, "%s %d\n", cmd, val); -+ /* printk(KERN_INFO DEVICE_NAME ": %s", s); */ -+ return write_uart(dev, s, strlen(s)); -+} -+ -+static int ngene_command_write_uart_user(struct ngene *dev, -+ const u8 *data, int len) -+{ -+ struct ngene_command com; -+ -+ dev->tx_busy = 1; -+ com.cmd.hdr.Opcode = CMD_WRITE_UART; -+ com.cmd.hdr.Length = len; -+ -+ if (copy_from_user(com.cmd.WriteUart.Data, data, len)) -+ return -EFAULT; -+ com.in_len = len; -+ com.out_len = 0; -+ -+ if (ngene_command(dev, &com) < 0) -+ return -EIO; -+ -+ return 0; -+} -+ -+static ssize_t uart_write(struct file *file, const char *buf, -+ size_t count, loff_t *ppos) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ int len, ret = 0; -+ size_t left = count; -+ -+ while (left) { -+ len = left; -+ if (len > 250) -+ len = 250; -+ ret = wait_event_interruptible(dev->tx_wq, dev->tx_busy == 0); -+ if (ret < 0) -+ return ret; -+ ngene_command_write_uart_user(dev, buf, len); -+ left -= len; -+ buf += len; -+ } -+ return count; -+} -+ -+static ssize_t uart_read(struct file *file, char *buf, -+ size_t count, loff_t *ppos) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ int left; -+ int wp, rp, avail, len; -+ -+ if (!dev->uart_rbuf) -+ return -EINVAL; -+ if (count > 128) -+ count = 128; -+ left = count; -+ while (left) { -+ if (wait_event_interruptible(dev->rx_wq, -+ dev->uart_wp != dev->uart_rp) < 0) -+ return -EAGAIN; -+ wp = dev->uart_wp; -+ rp = dev->uart_rp; -+ avail = (wp - rp); -+ -+ if (avail < 0) -+ avail += UART_RBUF_LEN; -+ if (avail > left) -+ avail = left; -+ if (wp < rp) { -+ len = UART_RBUF_LEN - rp; -+ if (len > avail) -+ len = avail; -+ if (copy_to_user(buf, dev->uart_rbuf + rp, len)) -+ return -EFAULT; -+ if (len < avail) -+ if (copy_to_user(buf + len, dev->uart_rbuf, -+ avail - len)) -+ return -EFAULT; -+ } else { -+ if (copy_to_user(buf, dev->uart_rbuf + rp, avail)) -+ return -EFAULT; -+ } -+ dev->uart_rp = (rp + avail) % UART_RBUF_LEN; -+ left -= avail; -+ buf += avail; -+ } -+ return count; -+} -+ -+#endif - - static ssize_t ts_write(struct file *file, const char *buf, - size_t count, loff_t *ppos) -@@ -133,6 +442,11 @@ void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags) - struct ngene_channel *chan = priv; - struct ngene *dev = chan->dev; - -+#if 0 -+ printk(KERN_INFO DEVICE_NAME ": tsin %08x %02x %02x %02x %02x\n", -+ len, ((u8 *) buf)[512 * 188], ((u8 *) buf)[0], -+ ((u8 *) buf)[1], ((u8 *) buf)[2]); -+#endif - - if (flags & DF_SWAP32) - swap_buffer(buf, len); -@@ -191,12 +505,49 @@ void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags) - return buf; - } - -+#if 0 -+static void set_dto(struct ngene_channel *chan, u32 rate) -+{ -+ u64 val = rate * 0x89705f41ULL; /* times val for 2^26 Hz */ -+ -+ val = ((val >> 25) + 1) >> 1; -+ chan->AudioDTOValue = (u32) val; -+ /* chan->AudioDTOUpdated=1; */ -+ /* printk(KERN_INFO DEVICE_NAME ": Setting DTO to %08x\n", val); */ -+} -+#endif - - - int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed) - { - struct dvb_demux *dvbdmx = dvbdmxfeed->demux; - struct ngene_channel *chan = dvbdmx->priv; -+#if 0 -+ struct ngene *dev = chan->dev; -+ -+ if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) { -+ switch (dvbdmxfeed->pes_type) { -+ case DMX_TS_PES_VIDEO: -+ send_cli_val(dev, "vpid", dvbdmxfeed->pid); -+ send_cli(dev, "res 1080i50\n"); -+ /* send_cli(dev, "vdec mpeg2\n"); */ -+ break; -+ -+ case DMX_TS_PES_AUDIO: -+ send_cli_val(dev, "apid", dvbdmxfeed->pid); -+ send_cli(dev, "start\n"); -+ break; -+ -+ case DMX_TS_PES_PCR: -+ send_cli_val(dev, "pcrpid", dvbdmxfeed->pid); -+ break; -+ -+ default: -+ break; -+ } -+ -+ } -+#endif - - if (chan->users == 0) { - if (!chan->dev->cmd_timeout_workaround || !chan->running) -@@ -210,6 +561,27 @@ int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed) - { - struct dvb_demux *dvbdmx = dvbdmxfeed->demux; - struct ngene_channel *chan = dvbdmx->priv; -+#if 0 -+ struct ngene *dev = chan->dev; -+ -+ if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) { -+ switch (dvbdmxfeed->pes_type) { -+ case DMX_TS_PES_VIDEO: -+ send_cli(dev, "stop\n"); -+ break; -+ -+ case DMX_TS_PES_AUDIO: -+ break; -+ -+ case DMX_TS_PES_PCR: -+ break; -+ -+ default: -+ break; -+ } -+ -+ } -+#endif - - if (--chan->users) - return chan->users; -diff --git a/drivers/media/pci/ngene/ngene-eeprom.c b/drivers/media/pci/ngene/ngene-eeprom.c -new file mode 100644 -index 0000000..281d9f9 ---- /dev/null -+++ b/drivers/media/pci/ngene/ngene-eeprom.c -@@ -0,0 +1,284 @@ -+/* -+ * ngene-eeprom.c: nGene PCIe bridge driver - eeprom support -+ * -+ * Copyright (C) 2005-2007 Micronas -+ * -+ * Copyright (C) 2008-2009 Ralph Metzler -+ * Modifications for new nGene firmware, -+ * support for EEPROM-copying, -+ * support for new dual DVB-S2 card prototype -+ * -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 only, as published by the Free Software Foundation. -+ * -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ * 02110-1301, USA -+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+#if 0 -+static int copy_eeprom; -+module_param(copy_eeprom, int, 0444); -+MODULE_PARM_DESC(copy_eeprom, "Copy eeprom."); -+ -+#define MICNG_EE_START 0x0100 -+#define MICNG_EE_END 0x0FF0 -+ -+#define MICNG_EETAG_END0 0x0000 -+#define MICNG_EETAG_END1 0xFFFF -+ -+/* 0x0001 - 0x000F reserved for housekeeping */ -+/* 0xFFFF - 0xFFFE reserved for housekeeping */ -+ -+/* Micronas assigned tags -+ EEProm tags for hardware support */ -+ -+#define MICNG_EETAG_DRXD1_OSCDEVIATION 0x1000 /* 2 Bytes data */ -+#define MICNG_EETAG_DRXD2_OSCDEVIATION 0x1001 /* 2 Bytes data */ -+ -+#define MICNG_EETAG_MT2060_1_1STIF 0x1100 /* 2 Bytes data */ -+#define MICNG_EETAG_MT2060_2_1STIF 0x1101 /* 2 Bytes data */ -+ -+/* Tag range for OEMs */ -+ -+#define MICNG_EETAG_OEM_FIRST 0xC000 -+#define MICNG_EETAG_OEM_LAST 0xFFEF -+ -+static int i2c_write_eeprom(struct i2c_adapter *adapter, -+ u8 adr, u16 reg, u8 data) -+{ -+ u8 m[3] = {(reg >> 8), (reg & 0xff), data}; -+ struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, -+ .len = sizeof(m)}; -+ -+ if (i2c_transfer(adapter, &msg, 1) != 1) { -+ dprintk(KERN_ERR DEVICE_NAME ": Error writing EEPROM!\n"); -+ return -EIO; -+ } -+ return 0; -+} -+ -+static int i2c_read_eeprom(struct i2c_adapter *adapter, -+ u8 adr, u16 reg, u8 *data, int len) -+{ -+ u8 msg[2] = {(reg >> 8), (reg & 0xff)}; -+ struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, -+ .buf = msg, .len = 2 }, -+ {.addr = adr, .flags = I2C_M_RD, -+ .buf = data, .len = len} }; -+ -+ if (i2c_transfer(adapter, msgs, 2) != 2) { -+ dprintk(KERN_ERR DEVICE_NAME ": Error reading EEPROM\n"); -+ return -EIO; -+ } -+ return 0; -+} -+ -+static int ReadEEProm(struct i2c_adapter *adapter, -+ u16 Tag, u32 MaxLen, u8 *data, u32 *pLength) -+{ -+ int status = 0; -+ u16 Addr = MICNG_EE_START, Length, tag = 0; -+ u8 EETag[3]; -+ -+ while (Addr + sizeof(u16) + 1 < MICNG_EE_END) { -+ if (i2c_read_eeprom(adapter, 0x50, Addr, EETag, sizeof(EETag))) -+ return -1; -+ tag = (EETag[0] << 8) | EETag[1]; -+ if (tag == MICNG_EETAG_END0 || tag == MICNG_EETAG_END1) -+ return -1; -+ if (tag == Tag) -+ break; -+ Addr += sizeof(u16) + 1 + EETag[2]; -+ } -+ if (Addr + sizeof(u16) + 1 + EETag[2] > MICNG_EE_END) { -+ printk(KERN_ERR DEVICE_NAME -+ ": Reached EOEE @ Tag = %04x Length = %3d\n", -+ tag, EETag[2]); -+ return -1; -+ } -+ Length = EETag[2]; -+ if (Length > MaxLen) -+ Length = (u16) MaxLen; -+ if (Length > 0) { -+ Addr += sizeof(u16) + 1; -+ status = i2c_read_eeprom(adapter, 0x50, Addr, data, Length); -+ if (!status) { -+ *pLength = EETag[2]; -+ if (Length < EETag[2]) -+ ; /*status=STATUS_BUFFER_OVERFLOW; */ -+ } -+ } -+ return status; -+} -+ -+static int WriteEEProm(struct i2c_adapter *adapter, -+ u16 Tag, u32 Length, u8 *data) -+{ -+ int status = 0; -+ u16 Addr = MICNG_EE_START; -+ u8 EETag[3]; -+ u16 tag = 0; -+ int retry, i; -+ -+ while (Addr + sizeof(u16) + 1 < MICNG_EE_END) { -+ if (i2c_read_eeprom(adapter, 0x50, Addr, EETag, sizeof(EETag))) -+ return -1; -+ tag = (EETag[0] << 8) | EETag[1]; -+ if (tag == MICNG_EETAG_END0 || tag == MICNG_EETAG_END1) -+ return -1; -+ if (tag == Tag) -+ break; -+ Addr += sizeof(u16) + 1 + EETag[2]; -+ } -+ if (Addr + sizeof(u16) + 1 + EETag[2] > MICNG_EE_END) { -+ printk(KERN_ERR DEVICE_NAME -+ ": Reached EOEE @ Tag = %04x Length = %3d\n", -+ tag, EETag[2]); -+ return -1; -+ } -+ -+ if (Length > EETag[2]) -+ return -EINVAL; -+ /* Note: We write the data one byte at a time to avoid -+ issues with page sizes. (which are different for -+ each manufacture and eeprom size) -+ */ -+ Addr += sizeof(u16) + 1; -+ for (i = 0; i < Length; i++, Addr++) { -+ status = i2c_write_eeprom(adapter, 0x50, Addr, data[i]); -+ -+ if (status) -+ break; -+ -+ /* Poll for finishing write cycle */ -+ retry = 10; -+ while (retry) { -+ u8 Tmp; -+ -+ msleep(50); -+ status = i2c_read_eeprom(adapter, 0x50, Addr, &Tmp, 1); -+ if (status) -+ break; -+ if (Tmp != data[i]) -+ printk(KERN_ERR DEVICE_NAME -+ "eeprom write error\n"); -+ retry -= 1; -+ } -+ if (status) { -+ printk(KERN_ERR DEVICE_NAME -+ ": Timeout polling eeprom\n"); -+ break; -+ } -+ } -+ return status; -+} -+ -+static void i2c_init_eeprom(struct i2c_adapter *adapter) -+{ -+ u8 tags[] = {0x10, 0x00, 0x02, 0x00, 0x00, -+ 0x10, 0x01, 0x02, 0x00, 0x00, -+ 0x00, 0x00, 0x00}; -+ -+ int i; -+ -+ for (i = 0; i < sizeof(tags); i++) -+ i2c_write_eeprom(adapter, 0x50, 0x0100 + i, tags[i]); -+} -+ -+int eeprom_read_ushort(struct i2c_adapter *adapter, u16 tag, u16 *data) -+{ -+ int stat; -+ u8 buf[2]; -+ u32 len = 0; -+ -+ stat = ReadEEProm(adapter, tag, 2, buf, &len); -+ if (stat) -+ return stat; -+ if (len != 2) -+ return -EINVAL; -+ -+ *data = (buf[0] << 8) | buf[1]; -+ return 0; -+} -+ -+static int eeprom_write_ushort(struct i2c_adapter *adapter, u16 tag, u16 data) -+{ -+ int stat; -+ u8 buf[2]; -+ -+ buf[0] = data >> 8; -+ buf[1] = data & 0xff; -+ stat = WriteEEProm(adapter, tag, 2, buf); -+ if (stat) -+ return stat; -+ return 0; -+} -+ -+int i2c_dump_eeprom(struct i2c_adapter *adapter, u8 adr) -+{ -+ u8 buf[64]; -+ int i; -+ -+ if (i2c_read_eeprom(adapter, adr, 0x0000, buf, sizeof(buf))) { -+ printk(KERN_ERR DEVICE_NAME ": No EEPROM?\n"); -+ return -1; -+ } -+ for (i = 0; i < sizeof(buf); i++) { -+ if (!(i & 15)) -+ printk(KERN_DEBUG "\n"); -+ printk(KERN_DEBUG "%02x ", buf[i]); -+ } -+ printk("\n"); -+ -+ return 0; -+} -+ -+int i2c_copy_eeprom(struct i2c_adapter *adapter, u8 adr, u8 adr2) -+{ -+ u8 buf[64]; -+ int i; -+ -+ if (i2c_read_eeprom(adapter, adr, 0x0000, buf, sizeof(buf))) { -+ printk(KERN_ERR DEVICE_NAME ": No EEPROM?\n"); -+ return -1; -+ } -+ buf[36] = 0xc3; -+ buf[39] = 0xab; -+ for (i = 0; i < sizeof(buf); i++) { -+ i2c_write_eeprom(adapter, adr2, i, buf[i]); -+ msleep(10); -+ } -+ return 0; -+} -+ -+int i2c_check_eeprom(struct i2c_adapter *adapter) -+{ -+ u8 buf[13]; -+ -+ i2c_dump_eeprom(adapter); -+ -+ if (i2c_read_eeprom(adapter, 0x50, 0x0100, buf, sizeof(buf))) { -+ printk(KERN_ERR DEVICE_NAME ": No EEPROM?\n"); -+ return -1; -+ } -+ if (buf[0] != 0x10 || buf[1] != 0x00) { -+ printk(KERN_INFO DEVICE_NAME -+ ": Initializing EEPROM TAG area\n"); -+ i2c_init_eeprom(adapter); -+ } -+ return 0; -+} -+ -+#endif -diff --git a/drivers/media/pci/ngene/ngene-i2c.c b/drivers/media/pci/ngene/ngene-i2c.c -index d28554f..601bea4 100644 ---- a/drivers/media/pci/ngene/ngene-i2c.c -+++ b/drivers/media/pci/ngene/ngene-i2c.c -@@ -77,6 +77,11 @@ static int ngene_command_i2c_write(struct ngene *dev, u8 adr, - { - struct ngene_command com; - -+#if 0 -+ /* Probing by writing 0 bytes does not work */ -+ if (!outlen) -+ outlen++; -+#endif - - com.cmd.hdr.Opcode = CMD_I2C_WRITE; - com.cmd.hdr.Length = outlen + 1; -@@ -148,6 +153,39 @@ done: - return num; - } - -+#if 0 -+static int ngene_i2c_algo_control(struct i2c_adapter *adap, -+ unsigned int cmd, unsigned long arg) -+{ -+ struct ngene_channel *chan = -+ (struct ngene_channel *)i2c_get_adapdata(adap); -+ -+ switch (cmd) { -+ case IOCTL_MIC_TUN_RDY: -+ chan->tun_rdy = 1; -+ if (chan->dec_rdy == 1) -+ chan->tun_dec_rdy = 1; -+ break; -+ -+ case IOCTL_MIC_DEC_RDY: -+ chan->dec_rdy = 1; -+ if (chan->tun_rdy == 1) -+ chan->tun_dec_rdy = 1; -+ break; -+ -+ case IOCTL_MIC_TUN_DETECT: -+ { -+ int *palorbtsc = (int *)arg; -+ *palorbtsc = chan->dev->card_info->ntsc; -+ break; -+ } -+ -+ default: -+ break; -+ } -+ return 0; -+} -+#endif - - static u32 ngene_i2c_functionality(struct i2c_adapter *adap) - { -@@ -174,3 +212,78 @@ int ngene_i2c_init(struct ngene *dev, int dev_nr) - return i2c_add_adapter(adap); - } - -+#if 0 -+int i2c_write(struct i2c_adapter *adapter, u8 adr, u8 data) -+{ -+ u8 m[1] = {data}; -+ struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 1}; -+ -+ if (i2c_transfer(adapter, &msg, 1) != 1) { -+ printk(KERN_ERR DEVICE_NAME -+ ": Failed to write to I2C adr %02x!\n", adr); -+ return -1; -+ } -+ return 0; -+} -+ -+static int i2c_write_register(struct i2c_adapter *adapter, -+ u8 adr, u8 reg, u8 data) -+{ -+ u8 m[2] = {reg, data}; -+ struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2}; -+ -+ if (i2c_transfer(adapter, &msg, 1) != 1) { -+ printk(KERN_ERR DEVICE_NAME -+ ": Failed to write to I2C register %02x@%02x!\n", -+ reg, adr); -+ return -1; -+ } -+ return 0; -+} -+ -+static int i2c_write_read(struct i2c_adapter *adapter, -+ u8 adr, u8 *w, u8 wlen, u8 *r, u8 rlen) -+{ -+ struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, -+ .buf = w, .len = wlen}, -+ {.addr = adr, .flags = I2C_M_RD, -+ .buf = r, .len = rlen} }; -+ -+ if (i2c_transfer(adapter, msgs, 2) != 2) { -+ printk(KERN_ERR DEVICE_NAME ": error in i2c_write_read\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+static int test_dec_i2c(struct i2c_adapter *adapter, int reg) -+{ -+ u8 data[256] = { reg, 0x00, 0x93, 0x78, 0x43, 0x45 }; -+ u8 data2[256]; -+ int i; -+ -+ memset(data2, 0, 256); -+ i2c_write_read(adapter, 0x66, data, 2, data2, 4); -+ for (i = 0; i < 4; i++) -+ printk(KERN_DEBUG "%02x ", data2[i]); -+ printk(KERN_DEBUG "\n"); -+ -+ return 0; -+} -+ -+static int i2c_write_msp_register(struct i2c_adapter *adapter, -+ u8 adr, u8 reg, u16 data) -+{ -+ u8 m[3] = {reg, (data >> 8) & 0xff, data & 0xff}; -+ struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 3 }; -+ -+ if (i2c_transfer(adapter, &msg, 1) != 1) { -+ printk(KERN_ERR DEVICE_NAME -+ ": Failed to write to I2C register %02x@%02x!\n", -+ reg, adr); -+ return -1; -+ } -+ return 0; -+} -+ -+#endif -diff --git a/drivers/media/pci/ngene/ngene.h b/drivers/media/pci/ngene/ngene.h -index 22c39ff..e3ae00c 100644 ---- a/drivers/media/pci/ngene/ngene.h -+++ b/drivers/media/pci/ngene/ngene.h -@@ -653,6 +653,11 @@ struct ngene_channel { - struct dmx_frontend mem_frontend; - int users; - struct video_device *v4l_dev; -+#if 0 -+ struct dvb_device *command_dev; -+ struct dvb_device *audio_dev; -+ struct dvb_device *video_dev; -+#endif - struct dvb_device *ci_dev; - struct tasklet_struct demux_tasklet; - -@@ -691,6 +696,9 @@ struct ngene_channel { - struct mychip *mychip; - struct snd_card *soundcard; - u8 *evenbuffer; -+#if 0 -+ u8 *soundbuffer; -+#endif - u8 dma_on; - int soundstreamon; - int audiomute; -@@ -849,6 +857,10 @@ struct ngene_info { - u8 lnb[4]; - int i2c_access; - u8 ntsc; -+#if 0 -+ u8 exp; -+ u8 exp_init; -+#endif - u8 tsf[4]; - u8 i2s[4]; - -@@ -885,6 +897,25 @@ struct ngene_buffer { - }; - #endif - -+#if 0 -+int ngene_command_stream_control(struct ngene *dev, -+ u8 stream, u8 control, u8 mode, u8 flags); -+int ngene_command_nop(struct ngene *dev); -+int ngene_command_i2c_read(struct ngene *dev, u8 adr, -+ u8 *out, u8 outlen, u8 *in, u8 inlen, int flag); -+int ngene_command_i2c_write(struct ngene *dev, u8 adr, u8 *out, u8 outlen); -+int ngene_command_imem_read(struct ngene *dev, u8 adr, u8 *data, int type); -+int ngene_command_imem_write(struct ngene *dev, u8 adr, u8 data, int type); -+int ngene_stream_control(struct ngene *dev, u8 stream, u8 control, u8 mode, -+ u16 lines, u16 bpl, u16 vblines, u16 vbibpl); -+ -+int ngene_v4l2_init(struct ngene_channel *chan); -+void ngene_v4l2_remove(struct ngene_channel *chan); -+int ngene_snd_exit(struct ngene_channel *chan); -+int ngene_snd_init(struct ngene_channel *chan); -+ -+struct i2c_client *avf4910a_attach(struct i2c_adapter *adap, int addr); -+#endif - - /* Provided by ngene-core.c */ - int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id); -@@ -914,6 +945,15 @@ int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, - struct dmx_frontend *mem_frontend, - struct dvb_adapter *dvb_adapter); - -+/* Provided by ngene-eeprom.c */ -+#if 0 -+int i2c_copy_eeprom(struct i2c_adapter *adapter, u8 adr, u8 adr2); -+int i2c_dump_eeprom(struct i2c_adapter *adapter, u8 adr); -+int i2c_check_eeprom(struct i2c_adapter *adapter); -+int eeprom_write_ushort(struct i2c_adapter *adapter, u16 tag, u16 data); -+int eeprom_read_ushort(struct i2c_adapter *adapter, u16 tag, u16 *data); -+#endif -+ - #endif - - /* LocalWords: Endif -diff --git a/drivers/staging/media/cxd2099/TODO b/drivers/staging/media/cxd2099/TODO -deleted file mode 100644 -index 375bb6f..0000000 ---- a/drivers/staging/media/cxd2099/TODO -+++ /dev/null -@@ -1,12 +0,0 @@ --For now, data is passed through '/dev/dvb/adapterX/sec0': -- - Encrypted data must be written to 'sec0'. -- - Decrypted data can be read from 'sec0'. -- - Setup the CAM using device 'ca0'. -- --But this is wrong. There are some discussions about the proper way for --doing it, as seen at: -- http://www.mail-archive.com/linux-media@vger.kernel.org/msg22196.html -- --While there's no proper fix for it, the driver should be kept in staging. -- --Patches should be submitted to: linux-media@vger.kernel.org. -diff --git a/drivers/staging/media/cxd2099/cxd2099.c b/drivers/staging/media/cxd2099/cxd2099.c -index 822c487..6d54b01 100644 ---- a/drivers/staging/media/cxd2099/cxd2099.c -+++ b/drivers/staging/media/cxd2099/cxd2099.c -@@ -66,9 +66,8 @@ static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr, - struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2}; - - if (i2c_transfer(adapter, &msg, 1) != 1) { -- dev_err(&adapter->dev, -- "Failed to write to I2C register %02x@%02x!\n", -- reg, adr); -+ printk(KERN_ERR "Failed to write to I2C register %02x@%02x!\n", -+ reg, adr); - return -1; - } - return 0; -@@ -80,7 +79,7 @@ static int i2c_write(struct i2c_adapter *adapter, u8 adr, - struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len}; - - if (i2c_transfer(adapter, &msg, 1) != 1) { -- dev_err(&adapter->dev, "Failed to write to I2C!\n"); -+ printk(KERN_ERR "Failed to write to I2C!\n"); - return -1; - } - return 0; -@@ -95,7 +94,7 @@ static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, - .buf = val, .len = 1} }; - - if (i2c_transfer(adapter, msgs, 2) != 2) { -- dev_err(&adapter->dev, "error in i2c_read_reg\n"); -+ printk(KERN_ERR "error in i2c_read_reg\n"); - return -1; - } - return 0; -@@ -110,7 +109,7 @@ static int i2c_read(struct i2c_adapter *adapter, u8 adr, - .buf = data, .len = n} }; - - if (i2c_transfer(adapter, msgs, 2) != 2) { -- dev_err(&adapter->dev, "error in i2c_read\n"); -+ printk(KERN_ERR "error in i2c_read\n"); - return -1; - } - return 0; -@@ -118,9 +117,10 @@ static int i2c_read(struct i2c_adapter *adapter, u8 adr, - - static int read_block(struct cxd *ci, u8 adr, u8 *data, u8 n) - { -- int status; -+ int status = 0; - -- status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr); -+ if (ci->lastaddress != adr) -+ status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr); - if (!status) { - ci->lastaddress = adr; - status = i2c_read(ci->i2c, ci->cfg.adr, 1, data, n); -@@ -278,7 +278,7 @@ static void cam_mode(struct cxd *ci, int mode) - #ifdef BUFFER_MODE - if (!ci->en.read_data) - return; -- dev_info(&ci->i2c->dev, "enable cam buffer mode\n"); -+ printk(KERN_INFO "enable cam buffer mode\n"); - /* write_reg(ci, 0x0d, 0x00); */ - /* write_reg(ci, 0x0e, 0x01); */ - write_regm(ci, 0x08, 0x40, 0x40); -@@ -525,7 +525,7 @@ static int slot_reset(struct dvb_ca_en50221 *ca, int slot) - msleep(10); - #if 0 - read_reg(ci, 0x06, &val); -- dev_info(&ci->i2c->dev, "%d:%02x\n", i, val); -+ printk(KERN_INFO "%d:%02x\n", i, val); - if (!(val&0x10)) - break; - #else -@@ -543,7 +543,7 @@ static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot) - { - struct cxd *ci = ca->data; - -- dev_info(&ci->i2c->dev, "slot_shutdown\n"); -+ printk(KERN_INFO "slot_shutdown\n"); - mutex_lock(&ci->lock); - write_regm(ci, 0x09, 0x08, 0x08); - write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */ -@@ -579,10 +579,10 @@ static int campoll(struct cxd *ci) - - if (istat&0x40) { - ci->dr = 1; -- dev_info(&ci->i2c->dev, "DR\n"); -+ printk(KERN_INFO "DR\n"); - } - if (istat&0x20) -- dev_info(&ci->i2c->dev, "WC\n"); -+ printk(KERN_INFO "WC\n"); - - if (istat&2) { - u8 slotstat; -@@ -598,7 +598,7 @@ static int campoll(struct cxd *ci) - if (ci->slot_stat) { - ci->slot_stat = 0; - write_regm(ci, 0x03, 0x00, 0x08); -- dev_info(&ci->i2c->dev, "NO CAM\n"); -+ printk(KERN_INFO "NO CAM\n"); - ci->ready = 0; - } - } -@@ -635,7 +635,7 @@ static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount) - campoll(ci); - mutex_unlock(&ci->lock); - -- dev_info(&ci->i2c->dev, "read_data\n"); -+ printk(KERN_INFO "read_data\n"); - if (!ci->dr) - return 0; - -@@ -684,29 +684,30 @@ struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg, - void *priv, - struct i2c_adapter *i2c) - { -- struct cxd *ci; -+ struct cxd *ci = 0; - u8 val; - - if (i2c_read_reg(i2c, cfg->adr, 0, &val) < 0) { -- dev_info(&i2c->dev, "No CXD2099 detected at %02x\n", cfg->adr); -- return NULL; -+ printk(KERN_INFO "No CXD2099 detected at %02x\n", cfg->adr); -+ return 0; - } - -- ci = kzalloc(sizeof(struct cxd), GFP_KERNEL); -+ ci = kmalloc(sizeof(struct cxd), GFP_KERNEL); - if (!ci) -- return NULL; -+ return 0; -+ memset(ci, 0, sizeof(*ci)); - - mutex_init(&ci->lock); -- ci->cfg = *cfg; -+ memcpy(&ci->cfg, cfg, sizeof(struct cxd2099_cfg)); - ci->i2c = i2c; - ci->lastaddress = 0xff; - ci->clk_reg_b = 0x4a; - ci->clk_reg_f = 0x1b; - -- ci->en = en_templ; -+ memcpy(&ci->en, &en_templ, sizeof(en_templ)); - ci->en.data = ci; - init(ci); -- dev_info(&i2c->dev, "Attached CXD2099AR at %02x\n", ci->cfg.adr); -+ printk(KERN_INFO "Attached CXD2099AR at %02x\n", ci->cfg.adr); - return &ci->en; - } - EXPORT_SYMBOL(cxd2099_attach); -diff --git a/drivers/staging/media/cxd2099/cxd2099.h b/drivers/staging/media/cxd2099/cxd2099.h -index 0eb607c..19c588a 100644 ---- a/drivers/staging/media/cxd2099/cxd2099.h -+++ b/drivers/staging/media/cxd2099/cxd2099.h -@@ -43,7 +43,7 @@ struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg, - static inline struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg, - void *priv, struct i2c_adapter *i2c) - { -- dev_warn(&i2c->dev, "%s: driver disabled by Kconfig\n", __func__); -+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); - return NULL; - } - #endif --- -1.7.2.5 - diff --git a/packages/linux/patches/3.11.6/linux-222-stb0899_signal_quality.patch b/packages/linux/patches/3.11.6/linux-222-stb0899_signal_quality.patch deleted file mode 100644 index fd6539d2bf..0000000000 --- a/packages/linux/patches/3.11.6/linux-222-stb0899_signal_quality.patch +++ /dev/null @@ -1,62 +0,0 @@ -diff -Naur linux-3.7.2/drivers/media/dvb-frontends/stb0899_drv.c linux-3.7.2.patch/drivers/media/dvb-frontends/stb0899_drv.c ---- linux-3.7.2/drivers/media/dvb-frontends/stb0899_drv.c 2013-01-11 18:19:28.000000000 +0100 -+++ linux-3.7.2.patch/drivers/media/dvb-frontends/stb0899_drv.c 2013-01-16 10:33:10.323380937 +0100 -@@ -971,6 +971,16 @@ - - *strength = stb0899_table_lookup(stb0899_dvbsrf_tab, ARRAY_SIZE(stb0899_dvbsrf_tab) - 1, val); - *strength += 750; -+ -+ const int MIN_STRENGTH_DVBS = 0; -+ const int MAX_STRENGTH_DVBS = 680; -+ if (*strength < MIN_STRENGTH_DVBS) -+ *strength = 0; -+ else if(*strength > MAX_STRENGTH_DVBS) -+ *strength = 0xFFFF; -+ else -+ *strength = (*strength - MIN_STRENGTH_DVBS) * 0xFFFF / (MAX_STRENGTH_DVBS - MIN_STRENGTH_DVBS); -+ - dprintk(state->verbose, FE_DEBUG, 1, "AGCIQVALUE = 0x%02x, C = %d * 0.1 dBm", - val & 0xff, *strength); - } -@@ -983,6 +993,7 @@ - - *strength = stb0899_table_lookup(stb0899_dvbs2rf_tab, ARRAY_SIZE(stb0899_dvbs2rf_tab) - 1, val); - *strength += 950; -+ *strength = *strength << 4; - dprintk(state->verbose, FE_DEBUG, 1, "IF_AGC_GAIN = 0x%04x, C = %d * 0.1 dBm", - val & 0x3fff, *strength); - } -@@ -1016,6 +1027,16 @@ - val = MAKEWORD16(buf[0], buf[1]); - - *snr = stb0899_table_lookup(stb0899_cn_tab, ARRAY_SIZE(stb0899_cn_tab) - 1, val); -+ -+ const int MIN_SNR_DVBS = 0; -+ const int MAX_SNR_DVBS = 200; -+ if (*snr < MIN_SNR_DVBS) -+ *snr = 0; -+ else if(*snr > MAX_SNR_DVBS) -+ *snr = 0xFFFF; -+ else -+ *snr = (*snr - MIN_SNR_DVBS) * 0xFFFF / (MAX_SNR_DVBS - MIN_SNR_DVBS); -+ - dprintk(state->verbose, FE_DEBUG, 1, "NIR = 0x%02x%02x = %u, C/N = %d * 0.1 dBm\n", - buf[0], buf[1], val, *snr); - } -@@ -1040,6 +1061,16 @@ - val = (quantn - estn) / 10; - } - *snr = val; -+ -+ const int MIN_SNR_DVBS2 = 10; -+ const int MAX_SNR_DVBS2 = 70; -+ if (*snr < MIN_SNR_DVBS2) -+ *snr = 0; -+ else if(*snr > MAX_SNR_DVBS2) -+ *snr = 0xFFFF; -+ else -+ *snr = (*snr - MIN_SNR_DVBS2) * 0xFFFF / (MAX_SNR_DVBS2 - MIN_SNR_DVBS2); -+ - dprintk(state->verbose, FE_DEBUG, 1, "Es/N0 quant = %d (%d) estimate = %u (%d), C/N = %d * 0.1 dBm", - quant, quantn, est, estn, val); - } diff --git a/packages/linux/patches/3.11.6/linux-223-Fix-video-artifacts-with-tt-3600-s2-usb.patch b/packages/linux/patches/3.11.6/linux-223-Fix-video-artifacts-with-tt-3600-s2-usb.patch deleted file mode 100644 index 7aaabc48c0..0000000000 --- a/packages/linux/patches/3.11.6/linux-223-Fix-video-artifacts-with-tt-3600-s2-usb.patch +++ /dev/null @@ -1,17 +0,0 @@ -diff -Naur linux-3.7.9/drivers/media/usb/dvb-usb/pctv452e.c linux-3.7.9.patch/drivers/media/usb/dvb-usb/pctv452e.c ---- linux-3.7.9/drivers/media/usb/dvb-usb/pctv452e.c 2013-01-11 18:19:28.000000000 +0100 -+++ linux-3.7.9.patch/drivers/media/usb/dvb-usb/pctv452e.c 2013-01-16 10:35:01.131342123 +0100 -@@ -995,11 +995,11 @@ - /* parameter for the MPEG2-data transfer */ - .stream = { - .type = USB_ISOC, -- .count = 7, -+ .count = 4, - .endpoint = 0x02, - .u = { - .isoc = { -- .framesperurb = 4, -+ .framesperurb = 64, - .framesize = 940, - .interval = 1 - } diff --git a/packages/linux/patches/3.11.6/linux-700-jmicron_1_0_8_5.patch.todo-or-remove b/packages/linux/patches/3.11.6/linux-700-jmicron_1_0_8_5.patch.todo-or-remove deleted file mode 100644 index 80a2c8195f..0000000000 --- a/packages/linux/patches/3.11.6/linux-700-jmicron_1_0_8_5.patch.todo-or-remove +++ /dev/null @@ -1,1603 +0,0 @@ -diff -Naur linux-3.7.2/drivers/net/ethernet/jme.c linux-3.7.2.patch/drivers/net/ethernet/jme.c ---- linux-3.7.2/drivers/net/ethernet/jme.c 2013-01-11 18:19:28.000000000 +0100 -+++ linux-3.7.2.patch/drivers/net/ethernet/jme.c 2013-01-16 10:16:40.087516337 +0100 -@@ -22,7 +22,10 @@ - * - */ - -+#include -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28) - #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -+#endif - - #include - #include -@@ -48,6 +51,7 @@ - static int force_pseudohp = -1; - static int no_pseudohp = -1; - static int no_extplug = -1; -+static int delay_time = 11; - module_param(force_pseudohp, int, 0); - MODULE_PARM_DESC(force_pseudohp, - "Enable pseudo hot-plug feature manually by driver instead of BIOS."); -@@ -56,6 +60,24 @@ - module_param(no_extplug, int, 0); - MODULE_PARM_DESC(no_extplug, - "Do not use external plug signal for pseudo hot-plug."); -+module_param(delay_time, uint, 0); -+MODULE_PARM_DESC(delay_time, -+ "Seconds to delay before switching lower speed; default = 11 seconds(3 trials)"); -+ -+#ifndef JME_NEW_PM_API -+static void -+jme_pci_wakeup_enable(struct jme_adapter *jme, int enable) -+{ -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27) -+ pci_enable_wake(jme->pdev, PCI_D1, enable); -+ pci_enable_wake(jme->pdev, PCI_D2, enable); -+ pci_enable_wake(jme->pdev, PCI_D3hot, enable); -+ pci_enable_wake(jme->pdev, PCI_D3cold, enable); -+#else -+ pci_pme_active(jme->pdev, enable); -+#endif -+} -+#endif - - static int - jme_mdio_read(struct net_device *netdev, int phy, int reg) -@@ -758,6 +780,9 @@ - jme->dev->mtu + RX_EXTRA_LEN); - if (unlikely(!skb)) - return -ENOMEM; -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19) -+ skb->dev = jme->dev; -+#endif - - mapping = pci_map_page(jme->pdev, virt_to_page(skb->data), - offset_in_page(skb->data), skb_tailroom(skb), -@@ -967,11 +992,29 @@ - jme_udpsum(struct sk_buff *skb) - { - u16 csum = 0xFFFFu; -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) -+ struct iphdr *iph; -+ int iphlen; -+ struct udphdr *udph; -+#endif - - if (skb->len < (ETH_HLEN + sizeof(struct iphdr))) - return csum; - if (skb->protocol != htons(ETH_P_IP)) - return csum; -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) -+ iph = (struct iphdr *)skb_pull(skb, ETH_HLEN); -+ iphlen = (iph->ihl << 2); -+ if ((iph->protocol != IPPROTO_UDP) || -+ (skb->len < (iphlen + sizeof(struct udphdr)))) { -+ skb_push(skb, ETH_HLEN); -+ return csum; -+ } -+ udph = (struct udphdr *)skb_pull(skb, iphlen); -+ csum = udph->check; -+ skb_push(skb, iphlen); -+ skb_push(skb, ETH_HLEN); -+#else - skb_set_network_header(skb, ETH_HLEN); - if ((ip_hdr(skb)->protocol != IPPROTO_UDP) || - (skb->len < (ETH_HLEN + -@@ -985,6 +1028,7 @@ - csum = udp_hdr(skb)->check; - skb_reset_transport_header(skb); - skb_reset_network_header(skb); -+#endif - - return csum; - } -@@ -1054,8 +1098,24 @@ - if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb)) - skb->ip_summed = CHECKSUM_UNNECESSARY; - else -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36) -+ skb->ip_summed = CHECKSUM_NONE; -+#else - skb_checksum_none_assert(skb); -- -+#endif -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) -+ if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) { -+ if (jme->vlgrp) { -+ jme->jme_vlan_rx(skb, jme->vlgrp, -+ le16_to_cpu(rxdesc->descwb.vlan)); -+ NET_STAT(jme).rx_bytes += 4; -+ } else { -+ dev_kfree_skb(skb); -+ } -+ } else { -+ jme->jme_rx(skb); -+ } -+#else - if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) { - u16 vid = le16_to_cpu(rxdesc->descwb.vlan); - -@@ -1064,6 +1124,7 @@ - } - jme->jme_rx(skb); - -+#endif - if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) == - cpu_to_le16(RXWBFLAG_DEST_MUL)) - ++(NET_STAT(jme).multicast); -@@ -1292,6 +1353,223 @@ - } - - static void -+jme_set_physpeed_capability(struct jme_adapter *jme, u16 speed) -+{ -+ u32 advert, advert2; -+ -+// spin_lock_bh(&jme->phy_lock); -+ advert = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE); -+ advert2 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000); -+ switch (speed) { -+ case SPEED_1000: -+ advert = (advert|ADVERTISE_100HALF|ADVERTISE_100FULL); -+ advert2 = (advert2|ADVERTISE_1000HALF|ADVERTISE_1000FULL); -+ break; -+ case SPEED_100: -+ advert = (advert|ADVERTISE_100HALF|ADVERTISE_100FULL); -+ advert2 = advert2 & ~(ADVERTISE_1000HALF|ADVERTISE_1000FULL); -+ break; -+ default: -+ advert = advert & ~(ADVERTISE_100HALF|ADVERTISE_100FULL); -+ advert2 = advert2 & ~(ADVERTISE_1000HALF|ADVERTISE_1000FULL); -+ } -+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE, advert); -+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, advert2); -+// spin_unlock_bh(&jme->phy_lock); -+ return; -+} -+ -+/* -+ PHY reg: MII_FCSCOUNTER is read and clear, we have to -+ continuing read until RJ45 is attached, then cache -+ this result. -+*/ -+static int -+jme_check_ANcomplete(struct jme_adapter *jme) -+{ -+ u32 val; -+ -+ val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_FCSCOUNTER); -+ return ((val&(PHY_SPEC_STATUS_AN_FAIL|PHY_SPEC_STATUS_AN_COMPLETE)) -+ == PHY_SPEC_STATUS_AN_COMPLETE) ? true : false; -+} -+ -+static int -+jme_media_connected(struct jme_adapter *jme) -+{ -+ if (jme->media_cnct == true) -+ return true; -+ -+ jme->media_cnct = jme_check_ANcomplete(jme); -+ return jme->media_cnct; -+} -+ -+static inline void -+jme_slowspeed_tune(struct jme_adapter *jme, u16 speed) -+{ -+ if (jme_check_ANcomplete(jme)) -+ jme_set_physpeed_capability(jme, speed); -+ else { -+ jme->media_cnct = false; -+ jme->media_cnct_sec = 0; -+ } -+} -+ -+static void -+asd_polling_func(unsigned long data) -+{ -+ struct jme_adapter *jme = (struct jme_adapter *)data; -+ unsigned long flags; -+ /* -+ check condition term by term. -+ 1. link is up() -+ ==> reset all thing, exit the process. -+ 2. there is no RJ45 cable attached -+ ==> do nothing but polling -+ 3. RJ45 cable attached. but link is down -+ ==> downspeed if the timeing is over 3.5 second. -+ */ -+ spin_lock_irqsave(&jme->asd_lock, flags); -+ if (jme->flag_run_asd == true) { -+ if (jme_media_connected(jme)) { -+ jme->media_cnct_sec++; -+ if (jme->media_cnct_sec == (delay_time*3-5)) { -+ /* Unable to link anyway, it can NOT be resolved -+ by slower speed, restore the capability */ -+ jme_set_physpeed_capability(jme, SPEED_1000); -+ jme->media_cnct = false; -+ jme->media_cnct_sec = 0; -+ } else if (jme->media_cnct_sec == (delay_time*2-5)) -+ jme_slowspeed_tune(jme, SPEED_10); -+ else if (jme->media_cnct_sec == delay_time-5) -+ jme_slowspeed_tune(jme, SPEED_100); -+ } -+ mod_timer(&jme->asd_timer, jiffies+HZ); -+ spin_unlock_irqrestore(&jme->asd_lock, flags); -+ return ; -+ } -+ jme->media_cnct = false; -+ jme->media_cnct_sec = 0; -+ spin_unlock_irqrestore(&jme->asd_lock, flags); -+ return; -+} -+ -+static int jme_check_linkup(struct jme_adapter *jme) -+{ -+ u32 phylink; -+ -+ if (jme->fpgaver) -+ phylink = jme_linkstat_from_phy(jme); -+ else -+ phylink = jread32(jme, JME_PHY_LINK); -+ -+ return (phylink & PHY_LINK_UP) ? true : false; -+} -+ -+static void jme_LC_task(struct work_struct *work) -+{ -+ struct jme_adapter *jme; -+ struct net_device *netdev; -+ int rc; -+ unsigned long flags; -+ -+ jme = container_of(work, struct jme_adapter, LC_task); -+ netdev = jme->dev; -+ -+ -+ msleep(500); -+ while (!atomic_dec_and_test(&jme->link_changing)) { -+ atomic_inc(&jme->link_changing); -+ netif_info(jme, intr, jme->dev, "Get link change lock failed\n"); -+ while (atomic_read(&jme->link_changing) != 1) -+ netif_info(jme, intr, jme->dev, "Waiting link change lock\n"); -+ } -+ spin_lock_irqsave(&jme->asd_lock, flags); -+ if (jme_check_linkup(jme)) { -+ if (jme->flag_run_asd) { -+ jme->flag_run_asd = false; -+ del_timer_sync(&jme->asd_timer); -+ } -+ } else { -+ if (!jme->flag_run_asd) { -+ jme_set_physpeed_capability(jme, SPEED_1000); -+ jme_check_ANcomplete(jme); -+ jme->media_cnct = false; -+ jme->flag_run_asd = true; -+ jme->media_cnct_sec = 0; -+ jme->asd_timer.expires = jiffies + 4*HZ; -+ jme->asd_timer.function = &asd_polling_func; -+ jme->asd_timer.data = (unsigned long)jme; -+ add_timer(&jme->asd_timer); -+ } -+ } -+ spin_unlock_irqrestore(&jme->asd_lock, flags); -+ if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu) -+ goto out; -+ -+ jme->old_mtu = netdev->mtu; -+ netif_stop_queue(netdev); -+ if (jme_pseudo_hotplug_enabled(jme)) -+ jme_stop_shutdown_timer(jme); -+ -+ jme_stop_pcc_timer(jme); -+ tasklet_disable(&jme->txclean_task); -+ tasklet_disable(&jme->rxclean_task); -+ tasklet_disable(&jme->rxempty_task); -+ -+ if (netif_carrier_ok(netdev)) { -+ jme_disable_rx_engine(jme); -+ jme_disable_tx_engine(jme); -+ jme_reset_mac_processor(jme); -+ jme_free_rx_resources(jme); -+ jme_free_tx_resources(jme); -+ -+ if (test_bit(JME_FLAG_POLL, &jme->flags)) -+ jme_polling_mode(jme); -+ -+ netif_carrier_off(netdev); -+ } -+ -+ jme_check_link(netdev, 0); -+ if (netif_carrier_ok(netdev)) { -+ rc = jme_setup_rx_resources(jme); -+ if (rc) { -+ pr_err("Allocating resources for RX error, Device STOPPED!\n"); -+ goto out_enable_tasklet; -+ } -+ -+ rc = jme_setup_tx_resources(jme); -+ if (rc) { -+ pr_err("Allocating resources for TX error, Device STOPPED!\n"); -+ goto err_out_free_rx_resources; -+ } -+ -+ jme_enable_rx_engine(jme); -+ jme_enable_tx_engine(jme); -+ -+ netif_start_queue(netdev); -+ -+ if (test_bit(JME_FLAG_POLL, &jme->flags)) -+ jme_interrupt_mode(jme); -+ -+ jme_start_pcc_timer(jme); -+ } else if (jme_pseudo_hotplug_enabled(jme)) { -+ jme_start_shutdown_timer(jme); -+ } -+ -+ goto out_enable_tasklet; -+ -+err_out_free_rx_resources: -+ jme_free_rx_resources(jme); -+out_enable_tasklet: -+ tasklet_enable(&jme->txclean_task); -+ tasklet_hi_enable(&jme->rxclean_task); -+ tasklet_hi_enable(&jme->rxempty_task); -+out: -+ atomic_inc(&jme->link_changing); -+} -+ -+static void - jme_link_change_tasklet(unsigned long arg) - { - struct jme_adapter *jme = (struct jme_adapter *)arg; -@@ -1385,6 +1663,7 @@ - jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget)) - { - struct jme_adapter *jme = jme_napi_priv(holder); -+ DECLARE_NETDEV - int rest; - - rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget)); -@@ -1538,7 +1817,7 @@ - * all other events are ignored - */ - jwrite32(jme, JME_IEVE, intrstat); -- tasklet_schedule(&jme->linkch_task); -+ schedule_work(&jme->LC_task); - goto out_reenable; - } - -@@ -1585,8 +1864,13 @@ - jwrite32f(jme, JME_IENS, INTR_ENABLE); - } - -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18) -+static irqreturn_t -+jme_intr(int irq, void *dev_id, struct pt_regs *regs) -+#else - static irqreturn_t - jme_intr(int irq, void *dev_id) -+#endif - { - struct net_device *netdev = dev_id; - struct jme_adapter *jme = netdev_priv(netdev); -@@ -1611,8 +1895,13 @@ - return IRQ_HANDLED; - } - -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18) -+static irqreturn_t -+jme_msi(int irq, void *dev_id, struct pt_regs *regs) -+#else - static irqreturn_t - jme_msi(int irq, void *dev_id) -+#endif - { - struct net_device *netdev = dev_id; - struct jme_adapter *jme = netdev_priv(netdev); -@@ -1648,8 +1937,13 @@ - { - int rc; - struct net_device *netdev = jme->dev; -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18) -+ irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr; -+ int irq_flags = SA_SHIRQ; -+#else - irq_handler_t handler = jme_intr; - int irq_flags = IRQF_SHARED; -+#endif - - if (!pci_enable_msi(jme->pdev)) { - set_bit(JME_FLAG_MSI, &jme->flags); -@@ -1746,55 +2040,60 @@ - } - - static int --jme_phy_specreg_read(struct jme_adapter *jme, u32 specreg) --{ -- u32 phy_addr; -- -- phy_addr = JM_PHY_SPEC_REG_READ | specreg; -- jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG, -- phy_addr); -- return jme_mdio_read(jme->dev, jme->mii_if.phy_id, -- JM_PHY_SPEC_DATA_REG); --} -- --static void --jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data) --{ -- u32 phy_addr; -- -- phy_addr = JM_PHY_SPEC_REG_WRITE | ext_reg; -- jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG, -- phy_data); -- jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG, -- phy_addr); --} -- --static int - jme_phy_calibration(struct jme_adapter *jme) - { -- u32 ctrl1000, phy_data; -+ u32 ctrl1000, bmcr, phy_addr, phy_data; - -- jme_phy_off(jme); -- jme_phy_on(jme); -- /* Enabel PHY test mode 1 */ -+ // Turn PHY off -+ bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR); -+ bmcr |= BMCR_PDOWN; -+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr); -+ // Turn PHY on -+ bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR); -+ bmcr &= ~BMCR_PDOWN; -+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr); -+ // Enabel PHY test mode 1 - ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000); - ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK; - ctrl1000 |= PHY_GAD_TEST_MODE_1; -- jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000); -- -- phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG); -+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000); -+ -+ -+ phy_addr = JM_PHY_SPEC_REG_READ | JM_PHY_EXT_COMM_2_REG; -+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG, -+ phy_addr); -+ phy_data = jme_mdio_read(jme->dev, jme->mii_if.phy_id, -+ JM_PHY_SPEC_DATA_REG); -+ - phy_data &= ~JM_PHY_EXT_COMM_2_CALI_MODE_0; - phy_data |= JM_PHY_EXT_COMM_2_CALI_LATCH | - JM_PHY_EXT_COMM_2_CALI_ENABLE; -- jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data); -+ -+ phy_addr = JM_PHY_SPEC_REG_WRITE | JM_PHY_EXT_COMM_2_REG; -+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG, -+ phy_data); -+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG, -+ phy_addr); -+ - msleep(20); -- phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG); -+ -+ phy_addr = JM_PHY_SPEC_REG_READ | JM_PHY_EXT_COMM_2_REG; -+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG, -+ phy_addr); -+ phy_data = jme_mdio_read(jme->dev, jme->mii_if.phy_id, -+ JM_PHY_SPEC_DATA_REG); -+ - phy_data &= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE | - JM_PHY_EXT_COMM_2_CALI_MODE_0 | - JM_PHY_EXT_COMM_2_CALI_LATCH); -- jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data); - -- /* Disable PHY test mode */ -+ phy_addr = JM_PHY_SPEC_REG_WRITE | JM_PHY_EXT_COMM_2_REG; -+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG, -+ phy_data); -+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG, -+ phy_addr); -+ -+ // Disable PHY test mode - ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000); - ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK; - jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000); -@@ -1804,11 +2103,11 @@ - static int - jme_phy_setEA(struct jme_adapter *jme) - { -- u32 phy_comm0 = 0, phy_comm1 = 0; -+ u32 phy_addr, phy_comm0 = 0, phy_comm1 = 0; - u8 nic_ctrl; - - pci_read_config_byte(jme->pdev, PCI_PRIV_SHARE_NICCTRL, &nic_ctrl); -- if ((nic_ctrl & 0x3) == JME_FLAG_PHYEA_ENABLE) -+ if ((nic_ctrl & 0x3) == JME_FLAG_PHYEA_ENABLE) - return 0; - - switch (jme->pdev->device) { -@@ -1840,14 +2139,23 @@ - if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 2)) - phy_comm0 = 0x408A; - break; -- default: -+ default: - return -ENODEV; - } -- if (phy_comm0) -- jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_0_REG, phy_comm0); -- if (phy_comm1) -- jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_1_REG, phy_comm1); -- -+ if (phy_comm0){ -+ phy_addr = JM_PHY_SPEC_REG_WRITE | JM_PHY_EXT_COMM_0_REG; -+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, -+ JM_PHY_SPEC_DATA_REG, phy_comm0); -+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, -+ JM_PHY_SPEC_ADDR_REG, phy_addr); -+ } -+ if (phy_comm1){ -+ phy_addr = JM_PHY_SPEC_REG_WRITE | JM_PHY_EXT_COMM_1_REG; -+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, -+ JM_PHY_SPEC_DATA_REG, phy_comm1); -+ jme_mdio_write(jme->dev, jme->mii_if.phy_id, -+ JM_PHY_SPEC_ADDR_REG, phy_addr); -+ } - return 0; - } - -@@ -1995,7 +2303,7 @@ - struct page *page, - u32 page_offset, - u32 len, -- bool hidma) -+ u8 hidma) - { - dma_addr_t dmaaddr; - -@@ -2029,20 +2337,24 @@ - struct jme_ring *txring = &(jme->txring[0]); - struct txdesc *txdesc = txring->desc, *ctxdesc; - struct jme_buffer_info *txbi = txring->bufinf, *ctxbi; -- bool hidma = jme->dev->features & NETIF_F_HIGHDMA; -+ u8 hidma = jme->dev->features & NETIF_F_HIGHDMA; - int i, nr_frags = skb_shinfo(skb)->nr_frags; - int mask = jme->tx_ring_mask; -- const struct skb_frag_struct *frag; -+ struct skb_frag_struct *frag; - u32 len; - - for (i = 0 ; i < nr_frags ; ++i) { - frag = &skb_shinfo(skb)->frags[i]; - ctxdesc = txdesc + ((idx + i + 2) & (mask)); - ctxbi = txbi + ((idx + i + 2) & (mask)); -- -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) -+ jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page, -+ frag->page_offset, frag->size, hidma); -+#else - jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, - skb_frag_page(frag), - frag->page_offset, skb_frag_size(frag), hidma); -+#endif - } - - len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len; -@@ -2056,8 +2368,13 @@ - static int - jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb) - { -- if (unlikely(skb_shinfo(skb)->gso_size && -- skb_header_cloned(skb) && -+ if (unlikely( -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17) -+ skb_shinfo(skb)->tso_size -+#else -+ skb_shinfo(skb)->gso_size -+#endif -+ && skb_header_cloned(skb) && - pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) { - dev_kfree_skb(skb); - return -1; -@@ -2069,7 +2386,11 @@ - static int - jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags) - { -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17) -+ *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT); -+#else - *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT); -+#endif - if (*mss) { - *flags |= TXFLAG_LSEN; - -@@ -2099,9 +2420,22 @@ - static void - jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags) - { -- if (skb->ip_summed == CHECKSUM_PARTIAL) { -+#ifdef CHECKSUM_PARTIAL -+ if (skb->ip_summed == CHECKSUM_PARTIAL) -+#else -+ if (skb->ip_summed == CHECKSUM_HW) -+#endif -+ { - u8 ip_proto; - -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) -+ if (skb->protocol == htons(ETH_P_IP)) -+ ip_proto = ip_hdr(skb)->protocol; -+ else if (skb->protocol == htons(ETH_P_IPV6)) -+ ip_proto = ipv6_hdr(skb)->nexthdr; -+ else -+ ip_proto = 0; -+#else - switch (skb->protocol) { - case htons(ETH_P_IP): - ip_proto = ip_hdr(skb)->protocol; -@@ -2113,6 +2447,7 @@ - ip_proto = 0; - break; - } -+#endif - - switch (ip_proto) { - case IPPROTO_TCP: -@@ -2219,7 +2554,11 @@ - * This function is already protected by netif_tx_lock() - */ - -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31) -+static int -+#else - static netdev_tx_t -+#endif - jme_start_xmit(struct sk_buff *skb, struct net_device *netdev) - { - struct jme_adapter *jme = netdev_priv(netdev); -@@ -2246,6 +2585,9 @@ - TXCS_SELECT_QUEUE0 | - TXCS_QUEUE0S | - TXCS_ENABLE); -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29) -+ netdev->trans_start = jiffies; -+#endif - - tx_dbg(jme, "xmit: %d+%d@%lu\n", - idx, skb_shinfo(skb)->nr_frags + 2, jiffies); -@@ -2292,6 +2634,9 @@ - { - struct jme_adapter *jme = netdev_priv(netdev); - u32 mc_hash[2] = {}; -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33) -+ int i; -+#endif - - spin_lock_bh(&jme->rxmcs_lock); - -@@ -2302,12 +2647,28 @@ - } else if (netdev->flags & IFF_ALLMULTI) { - jme->reg_rxmcs |= RXMCS_ALLMULFRAME; - } else if (netdev->flags & IFF_MULTICAST) { -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34) -+ struct dev_mc_list *mclist; -+#else - struct netdev_hw_addr *ha; -+#endif - int bit_nr; - - jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED; -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33) -+ for (i = 0, mclist = netdev->mc_list; -+ mclist && i < netdev->mc_count; -+ ++i, mclist = mclist->next) { -+#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34) -+ netdev_for_each_mc_addr(mclist, netdev) { -+#else - netdev_for_each_mc_addr(ha, netdev) { -+#endif -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34) -+ bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F; -+#else - bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F; -+#endif - mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F); - } - -@@ -2333,11 +2694,27 @@ - ((new_mtu) < IPV6_MIN_MTU)) - return -EINVAL; - -+ if (new_mtu > 4000) { -+ jme->reg_rxcs &= ~RXCS_FIFOTHNP; -+ jme->reg_rxcs |= RXCS_FIFOTHNP_64QW; -+ jme_restart_rx_engine(jme); -+ } else { -+ jme->reg_rxcs &= ~RXCS_FIFOTHNP; -+ jme->reg_rxcs |= RXCS_FIFOTHNP_128QW; -+ jme_restart_rx_engine(jme); -+ } -+ -+ if (new_mtu > 1900) { -+ netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | -+ NETIF_F_TSO | NETIF_F_TSO6); -+ } else { -+ if (test_bit(JME_FLAG_TXCSUM, &jme->flags)) -+ netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; -+ if (test_bit(JME_FLAG_TSO, &jme->flags)) -+ netdev->features |= NETIF_F_TSO | NETIF_F_TSO6; -+ } - - netdev->mtu = new_mtu; -- netdev_update_features(netdev); -- -- jme_restart_rx_engine(jme); - jme_reset_link(jme); - - return 0; -@@ -2390,15 +2767,45 @@ - atomic_inc(&jme->link_changing); - } - -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) -+static void -+jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp) -+{ -+ struct jme_adapter *jme = netdev_priv(netdev); -+ -+ jme_pause_rx(jme); -+ jme->vlgrp = grp; -+ jme_resume_rx(jme); -+} -+#endif -+ -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) -+static void -+jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid) -+{ -+ struct jme_adapter *jme = netdev_priv(netdev); -+ -+ if(jme->vlgrp) { -+ jme_pause_rx(jme); -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20) -+ jme->vlgrp->vlan_devices[vid] = NULL; -+#else -+ vlan_group_set_device(jme->vlgrp, vid, NULL); -+#endif -+ jme_resume_rx(jme); -+ } -+} -+#endif -+ - static void - jme_get_drvinfo(struct net_device *netdev, - struct ethtool_drvinfo *info) - { - struct jme_adapter *jme = netdev_priv(netdev); - -- strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); -- strlcpy(info->version, DRV_VERSION, sizeof(info->version)); -- strlcpy(info->bus_info, pci_name(jme->pdev), sizeof(info->bus_info)); -+ strcpy(info->driver, DRV_NAME); -+ strcpy(info->version, DRV_VERSION); -+ strcpy(info->bus_info, pci_name(jme->pdev)); - } - - static int -@@ -2500,6 +2907,9 @@ - test_bit(JME_FLAG_POLL, &jme->flags)) { - clear_bit(JME_FLAG_POLL, &jme->flags); - jme->jme_rx = netif_rx; -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) -+ jme->jme_vlan_rx = vlan_hwaccel_rx; -+#endif - dpi->cur = PCC_P1; - dpi->attempt = PCC_P1; - dpi->cnt = 0; -@@ -2509,6 +2919,9 @@ - !(test_bit(JME_FLAG_POLL, &jme->flags))) { - set_bit(JME_FLAG_POLL, &jme->flags); - jme->jme_rx = netif_receive_skb; -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) -+ jme->jme_vlan_rx = vlan_hwaccel_receive_skb; -+#endif - jme_interrupt_mode(jme); - } - -@@ -2622,7 +3035,12 @@ - jme->reg_pmcs |= PMCS_MFEN; - - jwrite32(jme, JME_PMCS, jme->reg_pmcs); -+#ifndef JME_NEW_PM_API -+ jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs)); -+#endif -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) - device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs)); -+#endif - - return 0; - } -@@ -2724,21 +3142,21 @@ - jme->msg_enable = value; - } - --static netdev_features_t --jme_fix_features(struct net_device *netdev, netdev_features_t features) -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) -+static u32 -+jme_get_rx_csum(struct net_device *netdev) - { -- if (netdev->mtu > 1900) -- features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM); -- return features; -+ struct jme_adapter *jme = netdev_priv(netdev); -+ return jme->reg_rxmcs & RXMCS_CHECKSUM; - } - - static int --jme_set_features(struct net_device *netdev, netdev_features_t features) -+jme_set_rx_csum(struct net_device *netdev, u32 on) - { - struct jme_adapter *jme = netdev_priv(netdev); - - spin_lock_bh(&jme->rxmcs_lock); -- if (features & NETIF_F_RXCSUM) -+ if (on) - jme->reg_rxmcs |= RXMCS_CHECKSUM; - else - jme->reg_rxmcs &= ~RXMCS_CHECKSUM; -@@ -2748,14 +3166,40 @@ - return 0; - } - --#ifdef CONFIG_NET_POLL_CONTROLLER --static void jme_netpoll(struct net_device *dev) -+static int -+jme_set_tx_csum(struct net_device *netdev, u32 on) - { -- unsigned long flags; -+ struct jme_adapter *jme = netdev_priv(netdev); -+ -+ if (on) { -+ set_bit(JME_FLAG_TXCSUM, &jme->flags); -+ if (netdev->mtu <= 1900) -+ netdev->features |= -+ NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; -+ } else { -+ clear_bit(JME_FLAG_TXCSUM, &jme->flags); -+ netdev->features &= -+ ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM); -+ } -+ -+ return 0; -+} -+ -+static int -+jme_set_tso(struct net_device *netdev, u32 on) -+{ -+ struct jme_adapter *jme = netdev_priv(netdev); -+ -+ if (on) { -+ set_bit(JME_FLAG_TSO, &jme->flags); -+ if (netdev->mtu <= 1900) -+ netdev->features |= NETIF_F_TSO | NETIF_F_TSO6; -+ } else { -+ clear_bit(JME_FLAG_TSO, &jme->flags); -+ netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6); -+ } - -- local_irq_save(flags); -- jme_intr(dev->irq, dev); -- local_irq_restore(flags); -+ return 0; - } - #endif - -@@ -2885,7 +3329,11 @@ - return 0; - } - -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18) -+static struct ethtool_ops jme_ethtool_ops = { -+#else - static const struct ethtool_ops jme_ethtool_ops = { -+#endif - .get_drvinfo = jme_get_drvinfo, - .get_regs_len = jme_get_regs_len, - .get_regs = jme_get_regs, -@@ -2900,6 +3348,13 @@ - .get_link = jme_get_link, - .get_msglevel = jme_get_msglevel, - .set_msglevel = jme_set_msglevel, -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0) -+ .get_rx_csum = jme_get_rx_csum, -+ .set_rx_csum = jme_set_rx_csum, -+ .set_tx_csum = jme_set_tx_csum, -+ .set_tso = jme_set_tso, -+ .set_sg = ethtool_op_set_sg, -+#endif - .nway_reset = jme_nway_reset, - .get_eeprom_len = jme_get_eeprom_len, - .get_eeprom = jme_get_eeprom, -@@ -2910,17 +3365,40 @@ - jme_pci_dma64(struct pci_dev *pdev) - { - if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 && -- !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) -+ !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) -+#else -+ !pci_set_dma_mask(pdev, DMA_64BIT_MASK) -+#endif -+ ) -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) - if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) -+#else -+ if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) -+#endif - return 1; - - if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 && -- !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))) -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) -+ !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)) -+#else -+ !pci_set_dma_mask(pdev, DMA_40BIT_MASK) -+#endif -+ ) -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) - if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40))) -+#else -+ if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK)) -+#endif - return 1; - -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) - if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) - if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) -+#else -+ if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) -+ if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) -+#endif - return 0; - - return -1; -@@ -2948,6 +3426,7 @@ - jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF; - } - -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) - static const struct net_device_ops jme_netdev_ops = { - .ndo_open = jme_open, - .ndo_stop = jme_close, -@@ -2955,15 +3434,16 @@ - .ndo_do_ioctl = jme_ioctl, - .ndo_start_xmit = jme_start_xmit, - .ndo_set_mac_address = jme_set_macaddr, -- .ndo_set_rx_mode = jme_set_multi, -+ .ndo_set_rx_mode = jme_set_multi, -+ -+ - .ndo_change_mtu = jme_change_mtu, - .ndo_tx_timeout = jme_tx_timeout, -- .ndo_fix_features = jme_fix_features, -- .ndo_set_features = jme_set_features, --#ifdef CONFIG_NET_POLL_CONTROLLER -- .ndo_poll_controller = jme_netpoll, -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) -+ .ndo_vlan_rx_register = jme_vlan_rx_register, - #endif - }; -+#endif - - static int __devinit - jme_init_one(struct pci_dev *pdev, -@@ -3013,18 +3493,29 @@ - */ - netdev = alloc_etherdev(sizeof(*jme)); - if (!netdev) { -+ pr_err("Cannot allocate netdev structure\n"); - rc = -ENOMEM; - goto err_out_release_regions; - } -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29) - netdev->netdev_ops = &jme_netdev_ops; -+#else -+ netdev->open = jme_open; -+ netdev->stop = jme_close; -+ netdev->do_ioctl = jme_ioctl; -+ netdev->hard_start_xmit = jme_start_xmit; -+ netdev->set_mac_address = jme_set_macaddr; -+ netdev->set_multicast_list = jme_set_multi; -+ netdev->change_mtu = jme_change_mtu; -+ netdev->tx_timeout = jme_tx_timeout; -+ netdev->vlan_rx_register = jme_vlan_rx_register; -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) -+ netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid; -+#endif -+ NETDEV_GET_STATS(netdev, &jme_get_stats); -+#endif - netdev->ethtool_ops = &jme_ethtool_ops; - netdev->watchdog_timeo = TX_TIMEOUT; -- netdev->hw_features = NETIF_F_IP_CSUM | -- NETIF_F_IPV6_CSUM | -- NETIF_F_SG | -- NETIF_F_TSO | -- NETIF_F_TSO6 | -- NETIF_F_RXCSUM; - netdev->features = NETIF_F_IP_CSUM | - NETIF_F_IPV6_CSUM | - NETIF_F_SG | -@@ -3045,6 +3536,9 @@ - jme->pdev = pdev; - jme->dev = netdev; - jme->jme_rx = netif_rx; -+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0) -+ jme->jme_vlan_rx = vlan_hwaccel_rx; -+#endif - jme->old_mtu = netdev->mtu = 1500; - jme->phylink = 0; - jme->tx_ring_size = 1 << 10; -@@ -3083,6 +3577,9 @@ - tasklet_init(&jme->pcc_task, - jme_pcc_tasklet, - (unsigned long) jme); -+ -+ INIT_WORK(&jme->LC_task, jme_LC_task); -+ - jme->dpi.cur = PCC_P1; - - jme->reg_ghc = 0; -@@ -3091,9 +3588,8 @@ - jme->reg_txpfc = 0; - jme->reg_pmcs = PMCS_MFEN; - jme->reg_gpreg1 = GPREG1_DEFAULT; -- -- if (jme->reg_rxmcs & RXMCS_CHECKSUM) -- netdev->features |= NETIF_F_RXCSUM; -+ set_bit(JME_FLAG_TXCSUM, &jme->flags); -+ set_bit(JME_FLAG_TSO, &jme->flags); - - /* - * Get Max Read Req Size from PCI Config Space -@@ -3149,10 +3645,19 @@ - - jme_clear_pm(jme); - pci_set_power_state(jme->pdev, PCI_D0); -+#ifndef JME_NEW_PM_API -+ jme_pci_wakeup_enable(jme, true); -+#endif -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) - device_set_wakeup_enable(&pdev->dev, true); -+#endif - - jme_set_phyfifo_5level(jme); -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,22) -+ pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev); -+#else - jme->pcirev = pdev->revision; -+#endif - if (!jme->fpgaver) - jme_phy_init(jme); - jme_phy_off(jme); -@@ -3179,14 +3684,26 @@ - goto err_out_unmap; - } - -- netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n", -+ init_timer(&(jme->asd_timer)); -+ jme->media_cnct_sec = 0; -+ jme->flag_run_asd = false; -+ jme->media_cnct = false; -+ -+ netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x " -+ "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n", - (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ? - "JMC250 Gigabit Ethernet" : - (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ? - "JMC260 Fast Ethernet" : "Unknown", - (jme->fpgaver != 0) ? " (FPGA)" : "", - (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev, -- jme->pcirev, netdev->dev_addr); -+ jme->pcirev, -+ netdev->dev_addr[0], -+ netdev->dev_addr[1], -+ netdev->dev_addr[2], -+ netdev->dev_addr[3], -+ netdev->dev_addr[4], -+ netdev->dev_addr[5]); - - return 0; - -@@ -3209,6 +3726,8 @@ - struct net_device *netdev = pci_get_drvdata(pdev); - struct jme_adapter *jme = netdev_priv(netdev); - -+ del_timer_sync(&jme->asd_timer); -+ cancel_work_sync(&jme->LC_task); - unregister_netdev(netdev); - iounmap(jme->regs); - pci_set_drvdata(pdev, NULL); -@@ -3225,26 +3744,48 @@ - struct jme_adapter *jme = netdev_priv(netdev); - - jme_powersave_phy(jme); -- pci_pme_active(pdev, true); -+#ifndef JME_NEW_PM_API -+ jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs)); -+#endif -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26) -+ device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs)); -+#endif - } - --#ifdef CONFIG_PM_SLEEP -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25) -+ #ifdef CONFIG_PM -+ #define JME_HAVE_PM -+ #endif -+#else -+ #ifdef CONFIG_PM_SLEEP -+ #define JME_HAVE_PM -+ #endif -+#endif -+ -+#ifdef JME_HAVE_PM - static int -+#ifdef JME_NEW_PM_API - jme_suspend(struct device *dev) -+#else -+jme_suspend(struct pci_dev *pdev, pm_message_t state) -+#endif - { -+#ifdef JME_NEW_PM_API - struct pci_dev *pdev = to_pci_dev(dev); -+#endif - struct net_device *netdev = pci_get_drvdata(pdev); - struct jme_adapter *jme = netdev_priv(netdev); -- -- if (!netif_running(netdev)) -- return 0; -- -+ unsigned long flags; -+ - atomic_dec(&jme->link_changing); - - netif_device_detach(netdev); - netif_stop_queue(netdev); - jme_stop_irq(jme); -- -+ spin_lock_irqsave(&jme->asd_lock, flags); -+ if (jme->flag_run_asd) -+ del_timer_sync(&jme->asd_timer); -+ spin_unlock_irqrestore(&jme->asd_lock, flags); - tasklet_disable(&jme->txclean_task); - tasklet_disable(&jme->rxclean_task); - tasklet_disable(&jme->rxempty_task); -@@ -3268,21 +3809,37 @@ - tasklet_hi_enable(&jme->rxempty_task); - - jme_powersave_phy(jme); -+ jme->media_cnct_sec = 0; -+ jme->media_cnct = false; -+#ifndef JME_NEW_PM_API -+ pci_save_state(pdev); -+ jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs)); -+ pci_set_power_state(pdev, PCI_D3hot); -+#endif - - return 0; - } - - static int -+#ifdef JME_NEW_PM_API - jme_resume(struct device *dev) -+#else -+jme_resume(struct pci_dev *pdev) -+#endif - { -+#ifdef JME_NEW_PM_API - struct pci_dev *pdev = to_pci_dev(dev); -+#endif - struct net_device *netdev = pci_get_drvdata(pdev); - struct jme_adapter *jme = netdev_priv(netdev); -- -- if (!netif_running(netdev)) -- return 0; -+ unsigned long flags; - - jme_clear_pm(jme); -+#ifndef JME_NEW_PM_API -+ pci_set_power_state(pdev, PCI_D0); -+ pci_restore_state(pdev); -+#endif -+ - jme_phy_on(jme); - if (test_bit(JME_FLAG_SSET, &jme->flags)) - jme_set_settings(netdev, &jme->old_ecmd); -@@ -3296,19 +3853,35 @@ - atomic_inc(&jme->link_changing); - - jme_reset_link(jme); -- -+ spin_lock_irqsave(&jme->asd_lock, flags); -+ if (jme->flag_run_asd) { -+ jme_check_ANcomplete(jme); -+ jme->asd_timer.expires = jiffies + 4*HZ; -+ jme->asd_timer.function = &asd_polling_func; -+ jme->asd_timer.data = (unsigned long)jme; -+ add_timer(&jme->asd_timer); -+ } -+ spin_unlock_irqrestore(&jme->asd_lock, flags); - return 0; - } - -+#ifdef JME_NEW_PM_API - static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume); - #define JME_PM_OPS (&jme_pm_ops) -+#endif - - #else - -+#ifdef JME_NEW_PM_API - #define JME_PM_OPS NULL - #endif -+#endif - -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24) -+static struct pci_device_id jme_pci_tbl[] = { -+#else - static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = { -+#endif - { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) }, - { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) }, - { } -@@ -3320,7 +3893,12 @@ - .probe = jme_init_one, - .remove = __devexit_p(jme_remove_one), - .shutdown = jme_shutdown, -+#ifndef JME_NEW_PM_API -+ .suspend = jme_suspend, -+ .resume = jme_resume -+#else - .driver.pm = JME_PM_OPS, -+#endif - }; - - static int __init -@@ -3344,3 +3922,4 @@ - MODULE_LICENSE("GPL"); - MODULE_VERSION(DRV_VERSION); - MODULE_DEVICE_TABLE(pci, jme_pci_tbl); -+ -diff -Naur linux-3.7.2/drivers/net/ethernet/jme.h linux-3.7.2.patch/drivers/net/ethernet/jme.h ---- linux-3.7.2/drivers/net/ethernet/jme.h 2013-01-11 18:19:28.000000000 +0100 -+++ linux-3.7.2.patch/drivers/net/ethernet/jme.h 2013-01-16 10:11:32.534765166 +0100 -@@ -27,7 +27,7 @@ - #include - - #define DRV_NAME "jme" --#define DRV_VERSION "1.0.8" -+#define DRV_VERSION "1.0.8.5-jmmod" - #define PFX DRV_NAME ": " - - #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250 -@@ -43,6 +43,15 @@ - NETIF_MSG_TX_ERR | \ - NETIF_MSG_HW) - -+#ifndef pr_err -+#define pr_err(fmt, arg...) \ -+ printk(KERN_ERR fmt, ##arg) -+#endif -+#ifndef netdev_err -+#define netdev_err(netdev, fmt, arg...) \ -+ pr_err(fmt, ##arg) -+#endif -+ - #ifdef TX_DEBUG - #define tx_dbg(priv, fmt, args...) \ - printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args) -@@ -54,6 +63,55 @@ - } while (0) - #endif - -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33) -+#define jme_msg(msglvl, type, priv, fmt, args...) \ -+ if (netif_msg_##type(priv)) \ -+ printk(msglvl "%s: " fmt, (priv)->dev->name, ## args) -+ -+#define msg_probe(priv, fmt, args...) \ -+ jme_msg(KERN_INFO, probe, priv, fmt, ## args) -+ -+#define msg_link(priv, fmt, args...) \ -+ jme_msg(KERN_INFO, link, priv, fmt, ## args) -+ -+#define msg_intr(priv, fmt, args...) \ -+ jme_msg(KERN_INFO, intr, priv, fmt, ## args) -+ -+#define msg_rx_err(priv, fmt, args...) \ -+ jme_msg(KERN_ERR, rx_err, priv, fmt, ## args) -+ -+#define msg_rx_status(priv, fmt, args...) \ -+ jme_msg(KERN_INFO, rx_status, priv, fmt, ## args) -+ -+#define msg_tx_err(priv, fmt, args...) \ -+ jme_msg(KERN_ERR, tx_err, priv, fmt, ## args) -+ -+#define msg_tx_done(priv, fmt, args...) \ -+ jme_msg(KERN_INFO, tx_done, priv, fmt, ## args) -+ -+#define msg_tx_queued(priv, fmt, args...) \ -+ jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args) -+ -+#define msg_hw(priv, fmt, args...) \ -+ jme_msg(KERN_ERR, hw, priv, fmt, ## args) -+ -+#ifndef netif_info -+#define netif_info(priv, type, dev, fmt, args...) \ -+ msg_ ## type(priv, fmt, ## args) -+#endif -+#ifndef netif_err -+#define netif_err(priv, type, dev, fmt, args...) \ -+ msg_ ## type(priv, fmt, ## args) -+#endif -+#endif -+ -+#ifndef NETIF_F_TSO6 -+#define NETIF_F_TSO6 0 -+#endif -+#ifndef NETIF_F_IPV6_CSUM -+#define NETIF_F_IPV6_CSUM 0 -+#endif -+ - /* - * Extra PCI Configuration space interface - */ -@@ -102,6 +160,7 @@ - }; - - #define HALF_US 500 /* 500 ns */ -+#define JMESPIIOCTL SIOCDEVPRIVATE - - #define PCI_PRIV_PE1 0xE4 - -@@ -388,10 +447,75 @@ - atomic_t nr_free; - }; - -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18) -+#define false 0 -+#define true 0 -+#define netdev_alloc_skb(dev, len) dev_alloc_skb(len) -+#define PCI_VENDOR_ID_JMICRON 0x197B -+#endif -+ -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19) -+#define PCI_VDEVICE(vendor, device) \ -+ PCI_VENDOR_ID_##vendor, (device), \ -+ PCI_ANY_ID, PCI_ANY_ID, 0, 0 -+#endif -+ -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) -+#define NET_STAT(priv) priv->stats -+#define NETDEV_GET_STATS(netdev, fun_ptr) \ -+ netdev->get_stats = fun_ptr -+#define DECLARE_NET_DEVICE_STATS struct net_device_stats stats; -+/* -+ * CentOS 5.2 have *_hdr helpers back-ported -+ */ -+#ifdef RHEL_RELEASE_CODE -+#if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,2) -+#define __DEFINE_IPHDR_HELPERS__ -+#endif -+#else -+#define __DEFINE_IPHDR_HELPERS__ -+#endif -+#else - #define NET_STAT(priv) (priv->dev->stats) - #define NETDEV_GET_STATS(netdev, fun_ptr) - #define DECLARE_NET_DEVICE_STATS -+#endif -+ -+#ifdef __DEFINE_IPHDR_HELPERS__ -+static inline struct iphdr *ip_hdr(const struct sk_buff *skb) -+{ -+ return skb->nh.iph; -+} -+ -+static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb) -+{ -+ return skb->nh.ipv6h; -+} - -+static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb) -+{ -+ return skb->h.th; -+} -+#endif -+ -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) -+#define DECLARE_NAPI_STRUCT -+#define NETIF_NAPI_SET(dev, napis, pollfn, q) \ -+ dev->poll = pollfn; \ -+ dev->weight = q; -+#define JME_NAPI_HOLDER(holder) struct net_device *holder -+#define JME_NAPI_WEIGHT(w) int *w -+#define JME_NAPI_WEIGHT_VAL(w) *w -+#define JME_NAPI_WEIGHT_SET(w, r) *w = r -+#define DECLARE_NETDEV struct net_device *netdev = jme->dev; -+#define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev) -+#define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev); -+#define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev); -+#define JME_RX_SCHEDULE_PREP(priv) \ -+ netif_rx_schedule_prep(priv->dev) -+#define JME_RX_SCHEDULE(priv) \ -+ __netif_rx_schedule(priv->dev); -+#else - #define DECLARE_NAPI_STRUCT struct napi_struct napi; - #define NETIF_NAPI_SET(dev, napis, pollfn, q) \ - netif_napi_add(dev, napis, pollfn, q); -@@ -399,6 +523,7 @@ - #define JME_NAPI_WEIGHT(w) int w - #define JME_NAPI_WEIGHT_VAL(w) w - #define JME_NAPI_WEIGHT_SET(w, r) -+#define DECLARE_NETDEV - #define JME_RX_COMPLETE(dev, napis) napi_complete(napis) - #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi); - #define JME_NAPI_DISABLE(priv) \ -@@ -408,6 +533,18 @@ - napi_schedule_prep(&priv->napi) - #define JME_RX_SCHEDULE(priv) \ - __napi_schedule(&priv->napi); -+#endif -+ -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,38) -+#define JME_NEW_PM_API -+#endif -+ -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26) -+static inline __u32 ethtool_cmd_speed(struct ethtool_cmd *ep) -+{ -+ return ep->speed; -+} -+#endif - - /* - * Jmac Adapter Private data -@@ -427,6 +564,7 @@ - struct tasklet_struct txclean_task; - struct tasklet_struct linkch_task; - struct tasklet_struct pcc_task; -+ struct work_struct LC_task; - unsigned long flags; - u32 reg_txcs; - u32 reg_txpfc; -@@ -450,6 +588,7 @@ - u32 msg_enable; - struct ethtool_cmd old_ecmd; - unsigned int old_mtu; -+ struct vlan_group *vlgrp; - struct dynpcc_info dpi; - atomic_t intr_sem; - atomic_t link_changing; -@@ -457,13 +596,32 @@ - atomic_t rx_cleaning; - atomic_t rx_empty; - int (*jme_rx)(struct sk_buff *skb); -+ spinlock_t asd_lock; -+ u8 flag_run_asd; -+ u32 media_cnct_sec; -+ u8 media_cnct; -+ struct timer_list asd_timer; -+ int (*jme_vlan_rx)(struct sk_buff *skb, -+ struct vlan_group *grp, -+ unsigned short vlan_tag); - DECLARE_NAPI_STRUCT - DECLARE_NET_DEVICE_STATS - }; - -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) -+static struct net_device_stats * -+jme_get_stats(struct net_device *netdev) -+{ -+ struct jme_adapter *jme = netdev_priv(netdev); -+ return &jme->stats; -+} -+#endif -+ - enum jme_flags_bits { - JME_FLAG_MSI = 1, - JME_FLAG_SSET = 2, -+ JME_FLAG_TXCSUM = 3, -+ JME_FLAG_TSO = 4, - JME_FLAG_POLL = 5, - JME_FLAG_SHUTDOWN = 6, - }; -@@ -472,6 +630,15 @@ - #define JME_REG_LEN 0x500 - #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216 - -+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) -+static inline struct jme_adapter* -+jme_napi_priv(struct net_device *holder) -+{ -+ struct jme_adapter *jme; -+ jme = netdev_priv(holder); -+ return jme; -+} -+#else - static inline struct jme_adapter* - jme_napi_priv(struct napi_struct *napi) - { -@@ -479,6 +646,7 @@ - jme = container_of(napi, struct jme_adapter, napi); - return jme; - } -+#endif - - /* - * MMaped I/O Resters -@@ -730,7 +898,7 @@ - RXCS_RETRYCNT_60 = 0x00000F00, - - RXCS_DEFAULT = RXCS_FIFOTHTP_128T | -- RXCS_FIFOTHNP_16QW | -+ RXCS_FIFOTHNP_128QW | - RXCS_DMAREQSZ_128B | - RXCS_RETRYGAP_256ns | - RXCS_RETRYCNT_32, -@@ -762,20 +930,20 @@ - - /* Extern PHY common register 2 */ - --#define PHY_GAD_TEST_MODE_1 0x00002000 --#define PHY_GAD_TEST_MODE_MSK 0x0000E000 --#define JM_PHY_SPEC_REG_READ 0x00004000 --#define JM_PHY_SPEC_REG_WRITE 0x00008000 --#define PHY_CALIBRATION_DELAY 20 -+#define PHY_GAD_TEST_MODE_1 0x00002000 //BIT_13 GIGA Test mode 1 -+#define PHY_GAD_TEST_MODE_MSK 0x0000E000 //BIT_13_15 GIGA Test mode mask -+#define JM_PHY_SPEC_REG_READ 0x00004000 //BIT_14 -+#define JM_PHY_SPEC_REG_WRITE 0x00008000 //BIT_15 -+#define PHY_CALIBRATION_DELAY 20 // 20 milliseconds - #define JM_PHY_SPEC_ADDR_REG 0x1E - #define JM_PHY_SPEC_DATA_REG 0x1F - - #define JM_PHY_EXT_COMM_0_REG 0x30 --#define JM_PHY_EXT_COMM_1_REG 0x31 -+#define JM_PHY_EXT_COMM_1_REG 0x31 - #define JM_PHY_EXT_COMM_2_REG 0x32 --#define JM_PHY_EXT_COMM_2_CALI_ENABLE 0x01 --#define JM_PHY_EXT_COMM_2_CALI_MODE_0 0x02 --#define JM_PHY_EXT_COMM_2_CALI_LATCH 0x10 -+#define JM_PHY_EXT_COMM_2_CALI_ENABLE 0x01 //BIT_0 -+#define JM_PHY_EXT_COMM_2_CALI_MODE_0 0x02 //BIT_1 -+#define JM_PHY_EXT_COMM_2_CALI_LATCH 0x10 //BIT_4 - #define PCI_PRIV_SHARE_NICCTRL 0xF5 - #define JME_FLAG_PHYEA_ENABLE 0x2 - -@@ -908,6 +1076,14 @@ - }; - - /* -+ * False carrier Counter -+ */ -+enum jme_phy_an_status { -+ PHY_SPEC_STATUS_AN_COMPLETE = 0x00000800, -+ PHY_SPEC_STATUS_AN_FAIL = 0x00008000, -+}; -+ -+/* - * Giga PHY Status Registers - */ - enum jme_phy_link_bit_mask { -@@ -1277,3 +1453,4 @@ - static void jme_set_multi(struct net_device *netdev); - - #endif -+ diff --git a/packages/linux/patches/3.11.6/linux-701-linksys_aes2500_brcmfmac.patch b/packages/linux/patches/3.11.6/linux-701-linksys_aes2500_brcmfmac.patch deleted file mode 100644 index 639a6ab30b..0000000000 --- a/packages/linux/patches/3.11.6/linux-701-linksys_aes2500_brcmfmac.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/drivers/net/wireless/brcm80211/brcmfmac/usb.c 2013-07-21 16:06:37.443909481 +0200 -+++ b/drivers/net/wireless/brcm80211/brcmfmac/usb.c 2013-07-21 16:11:10.696335476 +0200 -@@ -1470,15 +1470,18 @@ - } - - #define BRCMF_USB_VENDOR_ID_BROADCOM 0x0a5c -+#define BRCMF_USB_VENDOR_ID_LINKSYS 0x13b1 - #define BRCMF_USB_DEVICE_ID_43143 0xbd1e - #define BRCMF_USB_DEVICE_ID_43236 0xbd17 - #define BRCMF_USB_DEVICE_ID_43242 0xbd1f -+#define BRCMF_USB_DEVICE_ID_AE2500 0x003a - #define BRCMF_USB_DEVICE_ID_BCMFW 0x0bdc - - static struct usb_device_id brcmf_usb_devid_table[] = { - { USB_DEVICE(BRCMF_USB_VENDOR_ID_BROADCOM, BRCMF_USB_DEVICE_ID_43143) }, - { USB_DEVICE(BRCMF_USB_VENDOR_ID_BROADCOM, BRCMF_USB_DEVICE_ID_43236) }, - { USB_DEVICE(BRCMF_USB_VENDOR_ID_BROADCOM, BRCMF_USB_DEVICE_ID_43242) }, -+ { USB_DEVICE(BRCMF_USB_VENDOR_ID_LINKSYS, BRCMF_USB_DEVICE_ID_AE2500) }, - /* special entry for device with firmware loaded and running */ - { USB_DEVICE(BRCMF_USB_VENDOR_ID_BROADCOM, BRCMF_USB_DEVICE_ID_BCMFW) }, - { } diff --git a/packages/linux/patches/3.11.6/linux-702-Support-for-cheap-Ralink-3070-WiFi-plug.patch b/packages/linux/patches/3.11.6/linux-702-Support-for-cheap-Ralink-3070-WiFi-plug.patch deleted file mode 100644 index dba087cd57..0000000000 --- a/packages/linux/patches/3.11.6/linux-702-Support-for-cheap-Ralink-3070-WiFi-plug.patch +++ /dev/null @@ -1,72 +0,0 @@ -commit 073af93346306a0e079c161e3ed8dd263fef0b20 -Author: Stefan Saraev -Date: Sat Jul 13 19:31:03 2013 +0300 - - Support for cheap Ralink 3070 WiFi plug - - source: http://www.geekamole.com/2013/rt2800usb-fix-for-ralinkmediatek-3070-gentoo-linux/ - -diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h -index a7630d5..9504d45 100644 ---- a/drivers/net/wireless/rt2x00/rt2800.h -+++ b/drivers/net/wireless/rt2x00/rt2800.h -@@ -69,6 +69,7 @@ - #define RF3320 0x000b - #define RF3322 0x000c - #define RF3053 0x000d -+#define RF3070 0x3070 - #define RF5592 0x000f - #define RF3290 0x3290 - #define RF5360 0x5360 -diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c -index 72f32e5..3e18df4 100644 ---- a/drivers/net/wireless/rt2x00/rt2800lib.c -+++ b/drivers/net/wireless/rt2x00/rt2800lib.c -@@ -2599,6 +2599,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, - break; - case RF5360: - case RF5370: -+ case RF3070: - case RF5372: - case RF5390: - case RF5392: -@@ -2615,6 +2616,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, - rt2x00_rf(rt2x00dev, RF3322) || - rt2x00_rf(rt2x00dev, RF5360) || - rt2x00_rf(rt2x00dev, RF5370) || -+ rt2x00_rf(rt2x00dev, RF3070) || - rt2x00_rf(rt2x00dev, RF5372) || - rt2x00_rf(rt2x00dev, RF5390) || - rt2x00_rf(rt2x00dev, RF5392)) { -@@ -3199,6 +3201,7 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) - case RF3290: - case RF5360: - case RF5370: -+ case RF3070: - case RF5372: - case RF5390: - case RF5392: -@@ -5515,6 +5518,7 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) - case RF3322: - case RF5360: - case RF5370: -+ case RF3070: - case RF5372: - case RF5390: - case RF5392: -@@ -5969,6 +5973,7 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) - rt2x00_rf(rt2x00dev, RF3322) || - rt2x00_rf(rt2x00dev, RF5360) || - rt2x00_rf(rt2x00dev, RF5370) || -+ rt2x00_rf(rt2x00dev, RF3070) || - rt2x00_rf(rt2x00dev, RF5372) || - rt2x00_rf(rt2x00dev, RF5390) || - rt2x00_rf(rt2x00dev, RF5392)) { -@@ -6071,6 +6076,7 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) - case RF3290: - case RF5360: - case RF5370: -+ case RF3070: - case RF5372: - case RF5390: - case RF5392: diff --git a/packages/linux/patches/3.11.6/linux-703-macmini2012-ethernet.patch b/packages/linux/patches/3.11.6/linux-703-macmini2012-ethernet.patch deleted file mode 100644 index 298260ea69..0000000000 --- a/packages/linux/patches/3.11.6/linux-703-macmini2012-ethernet.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- linux-3.9.2/drivers/net/ethernet/broadcom/tg3.c 2013-05-11 18:19:28.000000000 +0400 -+++ linux-3.9.2/drivers/net/ethernet/broadcom/tg3.c 2013-05-25 20:55:00.282972605 +0400 -@@ -333,6 +333,8 @@ - {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)}, - {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)}, - {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)}, -+ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)}, -+ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)}, - {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)}, - {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)}, - {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)}, diff --git a/packages/linux/patches/3.11.6/linux-704-Support-for-Ubiquiti-WifiStation.patch b/packages/linux/patches/3.11.6/linux-704-Support-for-Ubiquiti-WifiStation.patch deleted file mode 100644 index 7932c0723b..0000000000 --- a/packages/linux/patches/3.11.6/linux-704-Support-for-Ubiquiti-WifiStation.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 62330f8f9b6105bfe201f52b7ed86ea6ce3d5901 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Sun, 8 Sep 2013 10:33:51 +0100 -Subject: [PATCH] Add Ubiquiti WifiStation USB id to ath9k wifi driver - ---- - drivers/net/wireless/ath/ath9k/hif_usb.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c -index 75a6376..8cb8d8d 100644 ---- a/drivers/net/wireless/ath/ath9k/hif_usb.c -+++ b/drivers/net/wireless/ath/ath9k/hif_usb.c -@@ -37,9 +37,11 @@ - { USB_DEVICE(0x13D3, 0x3350) }, /* Azurewave */ - { USB_DEVICE(0x04CA, 0x4605) }, /* Liteon */ - { USB_DEVICE(0x040D, 0x3801) }, /* VIA */ -+ { USB_DEVICE(0x0cf3, 0xb002) }, /* Ubiquiti WifiStation */ - { USB_DEVICE(0x0cf3, 0xb003) }, /* Ubiquiti WifiStation Ext */ - { USB_DEVICE(0x0cf3, 0xb002) }, /* Ubiquiti WifiStation */ - { USB_DEVICE(0x057c, 0x8403) }, /* AVM FRITZ!WLAN 11N v2 USB */ -+ { USB_DEVICE(0x057c, 0x8403) }, /* AVM FRITZ!WLAN 11N v2 USB */ - - { USB_DEVICE(0x0cf3, 0x7015), - .driver_info = AR9287_USB }, /* Atheros */ --- -1.8.4 - diff --git a/packages/linux/patches/3.11.6/linux-705-Support-for-Buffalo-WLI-UC-G300HP-V1.patch b/packages/linux/patches/3.11.6/linux-705-Support-for-Buffalo-WLI-UC-G300HP-V1.patch deleted file mode 100644 index 816af3b9d2..0000000000 --- a/packages/linux/patches/3.11.6/linux-705-Support-for-Buffalo-WLI-UC-G300HP-V1.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/drivers/net/wireless/rt2x00/rt2800usb.c 2013-10-08 15:14:44.844047190 +0200 -+++ b/drivers/net/wireless/rt2x00/rt2800usb.c 2013-10-08 15:15:00.279904575 +0200 -@@ -976,6 +976,7 @@ - { USB_DEVICE(0x0411, 0x015d) }, - { USB_DEVICE(0x0411, 0x016f) }, - { USB_DEVICE(0x0411, 0x01a2) }, -+ { USB_DEVICE(0x0411, 0x01a8) }, - { USB_DEVICE(0x0411, 0x01ee) }, - /* Corega */ - { USB_DEVICE(0x07aa, 0x002f) }, diff --git a/packages/linux/patches/3.11.6/linux-706-Sitecom-N300.patch b/packages/linux/patches/3.11.6/linux-706-Sitecom-N300.patch deleted file mode 100644 index 9f52eeb2d5..0000000000 --- a/packages/linux/patches/3.11.6/linux-706-Sitecom-N300.patch +++ /dev/null @@ -1,11 +0,0 @@ -diff -Naur linux-3.10.16/drivers/staging/rtl8712/usb_intf.c linux-3.10.16.patch/drivers/staging/rtl8712/usb_intf.c ---- linux-3.10.16/drivers/staging/rtl8712/usb_intf.c 2013-10-14 01:08:56.000000000 +0200 -+++ linux-3.10.16.patch/drivers/staging/rtl8712/usb_intf.c 2013-10-16 13:27:44.032951265 +0200 -@@ -92,6 +92,7 @@ - {USB_DEVICE(0x0DF6, 0x005B)}, - {USB_DEVICE(0x0DF6, 0x005D)}, - {USB_DEVICE(0x0DF6, 0x0063)}, -+ {USB_DEVICE(0x0DF6, 0x006C)}, - /* Sweex */ - {USB_DEVICE(0x177F, 0x0154)}, - /* Thinkware */ diff --git a/packages/linux/patches/3.11.6/linux-900-hide_tsc_error.patch b/packages/linux/patches/3.11.6/linux-900-hide_tsc_error.patch deleted file mode 100644 index 61b73b69b0..0000000000 --- a/packages/linux/patches/3.11.6/linux-900-hide_tsc_error.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -uNr linux-3.6.4-orig/arch/x86/kernel/tsc.c linux-3.6.4-new/arch/x86/kernel/tsc.c ---- linux-3.6.4-orig/arch/x86/kernel/tsc.c 2012-11-03 14:19:55.000000000 +0100 -+++ linux-3.6.4-new/arch/x86/kernel/tsc.c 2012-11-03 14:23:05.000000000 +0100 -@@ -374,7 +374,7 @@ - goto success; - } - } -- pr_err("Fast TSC calibration failed\n"); -+ pr_info("Fast TSC calibration failed\n"); - return 0; - - success: diff --git a/packages/linux/patches/3.11.6/linux-950-saa716x_PCIe_interface_chipset.patch b/packages/linux/patches/3.11.6/linux-950-saa716x_PCIe_interface_chipset.patch deleted file mode 100644 index 7428c7ce68..0000000000 --- a/packages/linux/patches/3.11.6/linux-950-saa716x_PCIe_interface_chipset.patch +++ /dev/null @@ -1,13031 +0,0 @@ -diff --git a/drivers/media/common/Kconfig b/drivers/media/common/Kconfig -index b85f88c..238b2ed 100644 ---- a/drivers/media/common/Kconfig -+++ b/drivers/media/common/Kconfig -@@ -22,4 +22,5 @@ config CYPRESS_FIRMWARE - - source "drivers/media/common/b2c2/Kconfig" - source "drivers/media/common/saa7146/Kconfig" -+source "drivers/media/common/saa716x/Kconfig" - source "drivers/media/common/siano/Kconfig" -diff --git a/drivers/media/common/Makefile b/drivers/media/common/Makefile -index d208de3..b3c373d 100644 ---- a/drivers/media/common/Makefile -+++ b/drivers/media/common/Makefile -@@ -1,4 +1,4 @@ --obj-y += b2c2/ saa7146/ siano/ -+obj-y += b2c2/ saa7146/ saa716x/ siano/ - obj-$(CONFIG_VIDEO_CX2341X) += cx2341x.o - obj-$(CONFIG_VIDEO_BTCX) += btcx-risc.o - obj-$(CONFIG_VIDEO_TVEEPROM) += tveeprom.o -diff --git a/drivers/media/common/saa716x/Kconfig b/drivers/media/common/saa716x/Kconfig -new file mode 100644 -index 0000000..e667a58 ---- /dev/null -+++ b/drivers/media/common/saa716x/Kconfig -@@ -0,0 +1,67 @@ -+menuconfig SAA716X_SUPPORT -+ bool "Support for SAA716x family from NXP/Philips" -+ depends on PCI && I2C -+ help -+ support for saa716x -+ -+if SAA716X_SUPPORT -+config SAA716X_CORE -+ tristate "SAA7160/1/2 PCI Express bridge based devices" -+ depends on PCI && I2C -+ -+ help -+ Support for PCI cards based on the SAA7160/1/2 PCI Express bridge. -+ -+ Say Y if you own such a device and want to use it. -+ -+config DVB_SAA716X_BUDGET -+ tristate "SAA7160/1/2 based Budget PCIe cards (DVB only)" -+ depends on SAA716X_CORE && DVB_CORE -+ select DVB_DS3000 if !DVB_FE_CUSTOMISE -+ select DVB_DS3103 if !DVB_FE_CUSTOMISE -+ select DVB_TS2022 if !DVB_FE_CUSTOMISE -+ -+ help -+ Support for the SAA7160/1/2 based Budget PCIe DVB cards -+ Currently supported devices are: -+ -+ * KNC1 Dual S2 (DVB-S, DVB-S/S2) -+ * Twinhan/Azurewave VP-1028 (DVB-S) -+ * Twinhan/Azurewave VP-3071 (DVB-T x2) -+ * Twinhan/Azurewave VP-6002 (DVB-S) -+ -+ Say Y if you own such a device and want to use it. -+ -+config DVB_SAA716X_HYBRID -+ tristate "SAA7160/1/2 based Hybrid PCIe cards (DVB + Analog)" -+ depends on SAA716X_CORE && DVB_CORE -+ -+ help -+ Support for the SAA7160/1/2 based Hybrid PCIe DVB cards -+ Currently supported devices are: -+ -+ * Avermedia H-788 (DVB-T) -+ * Avermedia HC-82 (DVB-T) -+ * NXP Reference (Atlantis) (DVB-T x2) -+ * NXP Reference (Nemo) (DVB-T) -+ * Twinhan/Azurewave VP-6090 (DVB-S x2, DVB-T x2) -+ -+ Say Y if you own such a device and want to use it. -+ -+#config DVB_SAA716X_FF -+# tristate "SAA7160/1/2 based Full Fledged PCIe cards" -+# depends on SAA716X_CORE && DVB_CORE -+# depends on INPUT # IR -+# default n -+ -+# help -+# Support for the SAA7160/1/2 based Full fledged PCIe DVB cards -+# These cards do feature a hardware MPEG decoder and other -+# peripherals. Also known as Premium cards. -+# Currently supported devices are: -+ -+# * Technotrend S2 6400 Dual S2 HD (DVB-S/S2 x2) -+ -+# Say Y if you own such a device and want to use it. -+ -+endif # SAA716X_SUPPORT -diff --git a/drivers/media/common/saa716x/Makefile b/drivers/media/common/saa716x/Makefile -new file mode 100644 -index 0000000..c86f224 ---- /dev/null -+++ b/drivers/media/common/saa716x/Makefile -@@ -0,0 +1,26 @@ -+saa716x_core-objs := saa716x_pci.o \ -+ saa716x_i2c.o \ -+ saa716x_cgu.o \ -+ saa716x_msi.o \ -+ saa716x_dma.o \ -+ saa716x_vip.o \ -+ saa716x_aip.o \ -+ saa716x_phi.o \ -+ saa716x_boot.o \ -+ saa716x_fgpi.o \ -+ saa716x_adap.o \ -+ saa716x_gpio.o \ -+ saa716x_greg.o \ -+ saa716x_rom.o \ -+ saa716x_spi.o -+ -+#saa716x_ff-objs := saa716x_ff_main.o \ -+# saa716x_ff_cmd.o \ -+# saa716x_ff_ir.o -+ -+obj-$(CONFIG_SAA716X_CORE) += saa716x_core.o -+obj-$(CONFIG_DVB_SAA716X_BUDGET) += saa716x_budget.o -+obj-$(CONFIG_DVB_SAA716X_HYBRID) += saa716x_hybrid.o -+#obj-$(CONFIG_DVB_SAA716X_FF) += saa716x_ff.o -+ -+EXTRA_CFLAGS = -Idrivers/media/dvb-core/ -Idrivers/media/dvb-frontends/ -Idrivers/media/tuners/ -diff --git a/drivers/media/common/saa716x/saa716x_adap.c b/drivers/media/common/saa716x/saa716x_adap.c -new file mode 100644 -index 0000000..6d7346c ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_adap.c -@@ -0,0 +1,274 @@ -+#include -+ -+#include "dmxdev.h" -+#include "dvbdev.h" -+#include "dvb_demux.h" -+#include "dvb_frontend.h" -+ -+#include "saa716x_mod.h" -+#include "saa716x_spi.h" -+#include "saa716x_adap.h" -+#include "saa716x_i2c.h" -+#include "saa716x_gpio.h" -+#include "saa716x_priv.h" -+#include "saa716x_budget.h" -+ -+ -+DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); -+ -+ -+void saa716x_dma_start(struct saa716x_dev *saa716x, u8 adapter) -+{ -+ struct fgpi_stream_params params; -+ -+ dprintk(SAA716x_DEBUG, 1, "SAA716x Start DMA engine for Adapter:%d", adapter); -+ -+ params.bits = 8; -+ params.samples = 188; -+ params.lines = 348; -+ params.pitch = 188; -+ params.offset = 0; -+ params.page_tables = 0; -+ params.stream_type = FGPI_TRANSPORT_STREAM; -+ params.stream_flags = 0; -+ -+ saa716x_fgpi_start(saa716x, saa716x->config->adap_config[adapter].ts_port, ¶ms); -+} -+ -+void saa716x_dma_stop(struct saa716x_dev *saa716x, u8 adapter) -+{ -+ dprintk(SAA716x_DEBUG, 1, "SAA716x Stop DMA engine for Adapter:%d", adapter); -+ -+ saa716x_fgpi_stop(saa716x, saa716x->config->adap_config[adapter].ts_port); -+} -+ -+static int saa716x_dvb_start_feed(struct dvb_demux_feed *dvbdmxfeed) -+{ -+ struct dvb_demux *dvbdmx = dvbdmxfeed->demux; -+ struct saa716x_adapter *saa716x_adap = dvbdmx->priv; -+ struct saa716x_dev *saa716x = saa716x_adap->saa716x; -+ -+ dprintk(SAA716x_DEBUG, 1, "SAA716x DVB Start feed"); -+ if (!dvbdmx->dmx.frontend) { -+ dprintk(SAA716x_DEBUG, 1, "no frontend ?"); -+ return -EINVAL; -+ } -+ saa716x_adap->feeds++; -+ dprintk(SAA716x_DEBUG, 1, "SAA716x start feed, feeds=%d", -+ saa716x_adap->feeds); -+ -+ if (saa716x_adap->feeds == 1) { -+ dprintk(SAA716x_DEBUG, 1, "SAA716x start feed & dma"); -+ saa716x_dma_start(saa716x, saa716x_adap->count); -+ } -+ -+ return saa716x_adap->feeds; -+} -+ -+static int saa716x_dvb_stop_feed(struct dvb_demux_feed *dvbdmxfeed) -+{ -+ struct dvb_demux *dvbdmx = dvbdmxfeed->demux; -+ struct saa716x_adapter *saa716x_adap = dvbdmx->priv; -+ struct saa716x_dev *saa716x = saa716x_adap->saa716x; -+ -+ dprintk(SAA716x_DEBUG, 1, "SAA716x DVB Stop feed"); -+ if (!dvbdmx->dmx.frontend) { -+ dprintk(SAA716x_DEBUG, 1, "no frontend ?"); -+ return -EINVAL; -+ } -+ saa716x_adap->feeds--; -+ if (saa716x_adap->feeds == 0) { -+ dprintk(SAA716x_DEBUG, 1, "saa716x stop feed and dma"); -+ saa716x_dma_stop(saa716x, saa716x_adap->count); -+ } -+ -+ return 0; -+} -+ -+int saa716x_dvb_init(struct saa716x_dev *saa716x) -+{ -+ struct saa716x_adapter *saa716x_adap = saa716x->saa716x_adap; -+ struct saa716x_config *config = saa716x->config; -+ int result, i; -+ -+ mutex_init(&saa716x->adap_lock); -+ -+ for (i = 0; i < config->adapters; i++) { -+ -+ dprintk(SAA716x_DEBUG, 1, "dvb_register_adapter"); -+ if (dvb_register_adapter(&saa716x_adap->dvb_adapter, -+ "SAA716x dvb adapter", -+ THIS_MODULE, -+ &saa716x->pdev->dev, -+ adapter_nr) < 0) { -+ -+ dprintk(SAA716x_ERROR, 1, "Error registering adapter"); -+ return -ENODEV; -+ } -+ -+ saa716x_adap->count = i; -+ -+ saa716x_adap->dvb_adapter.priv = saa716x_adap; -+ saa716x_adap->demux.dmx.capabilities = DMX_TS_FILTERING | -+ DMX_SECTION_FILTERING | -+ DMX_MEMORY_BASED_FILTERING; -+ -+ saa716x_adap->demux.priv = saa716x_adap; -+ saa716x_adap->demux.filternum = 256; -+ saa716x_adap->demux.feednum = 256; -+ saa716x_adap->demux.start_feed = saa716x_dvb_start_feed; -+ saa716x_adap->demux.stop_feed = saa716x_dvb_stop_feed; -+ saa716x_adap->demux.write_to_decoder = NULL; -+ switch (saa716x->pdev->subsystem_device) { -+ case TEVII_S472: { -+ struct saa716x_i2c *i2c = saa716x->i2c; -+ struct i2c_adapter *adapter = &i2c[SAA716x_I2C_BUS_B].i2c_adapter; -+ u8 mac[6]; -+ u8 b0[] = { 0, 9 }; -+ struct i2c_msg msg[] = { -+ { -+ .addr = 0x50, -+ .flags = 0, -+ .buf = b0, -+ .len = 2 -+ }, { -+ .addr = 0x50, -+ .flags = I2C_M_RD, -+ .buf = mac, -+ .len = 6 -+ } -+ }; -+ -+ i2c_transfer(adapter, msg, 2); -+ dprintk(SAA716x_INFO, 1, "TeVii S472 MAC= %pM\n", mac); -+ memcpy(saa716x_adap->dvb_adapter.proposed_mac, mac, 6); -+ } -+ } -+ -+ dprintk(SAA716x_DEBUG, 1, "dvb_dmx_init"); -+ if ((result = dvb_dmx_init(&saa716x_adap->demux)) < 0) { -+ dprintk(SAA716x_ERROR, 1, "dvb_dmx_init failed, ERROR=%d", result); -+ goto err0; -+ } -+ -+ saa716x_adap->dmxdev.filternum = 256; -+ saa716x_adap->dmxdev.demux = &saa716x_adap->demux.dmx; -+ saa716x_adap->dmxdev.capabilities = 0; -+ -+ dprintk(SAA716x_DEBUG, 1, "dvb_dmxdev_init"); -+ if ((result = dvb_dmxdev_init(&saa716x_adap->dmxdev, -+ &saa716x_adap->dvb_adapter)) < 0) { -+ -+ dprintk(SAA716x_ERROR, 1, "dvb_dmxdev_init failed, ERROR=%d", result); -+ goto err1; -+ } -+ -+ saa716x_adap->fe_hw.source = DMX_FRONTEND_0; -+ -+ if ((result = saa716x_adap->demux.dmx.add_frontend(&saa716x_adap->demux.dmx, -+ &saa716x_adap->fe_hw)) < 0) { -+ -+ dprintk(SAA716x_ERROR, 1, "dvb_dmx_init failed, ERROR=%d", result); -+ goto err2; -+ } -+ -+ saa716x_adap->fe_mem.source = DMX_MEMORY_FE; -+ -+ if ((result = saa716x_adap->demux.dmx.add_frontend(&saa716x_adap->demux.dmx, -+ &saa716x_adap->fe_mem)) < 0) { -+ dprintk(SAA716x_ERROR, 1, "dvb_dmx_init failed, ERROR=%d", result); -+ goto err3; -+ } -+ -+ if ((result = saa716x_adap->demux.dmx.connect_frontend(&saa716x_adap->demux.dmx, -+ &saa716x_adap->fe_hw)) < 0) { -+ -+ dprintk(SAA716x_ERROR, 1, "dvb_dmx_init failed, ERROR=%d", result); -+ goto err4; -+ } -+ -+ dvb_net_init(&saa716x_adap->dvb_adapter, &saa716x_adap->dvb_net, &saa716x_adap->demux.dmx); -+// tasklet_init(&saa716x_adap->tasklet, saa716x_dma_xfer, (unsigned long) saa716x); -+ dprintk(SAA716x_DEBUG, 1, "Frontend Init"); -+ saa716x_adap->saa716x = saa716x; -+ -+ if (config->frontend_attach) { -+ result = config->frontend_attach(saa716x_adap, i); -+ if (result < 0) -+ dprintk(SAA716x_ERROR, 1, "SAA716x frontend attach failed"); -+ -+ if (saa716x_adap->fe == NULL) { -+ dprintk(SAA716x_ERROR, 1, "A frontend driver was not found for [%04x:%04x] subsystem [%04x:%04x]\n", -+ saa716x->pdev->vendor, -+ saa716x->pdev->device, -+ saa716x->pdev->subsystem_vendor, -+ saa716x->pdev->subsystem_device); -+ } else { -+ result = dvb_register_frontend(&saa716x_adap->dvb_adapter, saa716x_adap->fe); -+ if (result < 0) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x register frontend failed"); -+ goto err6; -+ } -+ } -+ -+ } else { -+ dprintk(SAA716x_ERROR, 1, "Frontend attach = NULL"); -+ } -+ -+ saa716x_fgpi_init(saa716x, config->adap_config[i].ts_port, -+ config->adap_config[i].worker); -+ -+ saa716x_adap++; -+ } -+ -+ -+ return 0; -+ -+ /* Error conditions */ -+err6: -+ dvb_frontend_detach(saa716x_adap->fe); -+err4: -+ saa716x_adap->demux.dmx.remove_frontend(&saa716x_adap->demux.dmx, &saa716x_adap->fe_mem); -+err3: -+ saa716x_adap->demux.dmx.remove_frontend(&saa716x_adap->demux.dmx, &saa716x_adap->fe_hw); -+err2: -+ dvb_dmxdev_release(&saa716x_adap->dmxdev); -+err1: -+ dvb_dmx_release(&saa716x_adap->demux); -+err0: -+ dvb_unregister_adapter(&saa716x_adap->dvb_adapter); -+ -+ return result; -+} -+EXPORT_SYMBOL(saa716x_dvb_init); -+ -+void saa716x_dvb_exit(struct saa716x_dev *saa716x) -+{ -+ struct saa716x_adapter *saa716x_adap = saa716x->saa716x_adap; -+ int i; -+ -+ for (i = 0; i < saa716x->config->adapters; i++) { -+ -+ saa716x_fgpi_exit(saa716x, saa716x->config->adap_config[i].ts_port); -+ -+ if (saa716x_adap->fe) { -+ dvb_unregister_frontend(saa716x_adap->fe); -+ dvb_frontend_detach(saa716x_adap->fe); -+ } -+ -+// tasklet_kill(&saa716x->tasklet); -+ dvb_net_release(&saa716x_adap->dvb_net); -+ saa716x_adap->demux.dmx.remove_frontend(&saa716x_adap->demux.dmx, &saa716x_adap->fe_mem); -+ saa716x_adap->demux.dmx.remove_frontend(&saa716x_adap->demux.dmx, &saa716x_adap->fe_hw); -+ dvb_dmxdev_release(&saa716x_adap->dmxdev); -+ dvb_dmx_release(&saa716x_adap->demux); -+ -+ dprintk(SAA716x_DEBUG, 1, "dvb_unregister_adapter"); -+ dvb_unregister_adapter(&saa716x_adap->dvb_adapter); -+ -+ saa716x_adap++; -+ } -+ -+ return; -+} -+EXPORT_SYMBOL(saa716x_dvb_exit); -diff --git a/drivers/media/common/saa716x/saa716x_adap.h b/drivers/media/common/saa716x/saa716x_adap.h -new file mode 100644 -index 0000000..7822e36 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_adap.h -@@ -0,0 +1,9 @@ -+#ifndef __SAA716x_ADAP_H -+#define __SAA716x_ADAP_H -+ -+struct saa716x_dev; -+ -+extern int saa716x_dvb_init(struct saa716x_dev *saa716x); -+extern void saa716x_dvb_exit(struct saa716x_dev *saa716x); -+ -+#endif /* __SAA716x_ADAP_H */ -diff --git a/drivers/media/common/saa716x/saa716x_aip.c b/drivers/media/common/saa716x/saa716x_aip.c -new file mode 100644 -index 0000000..3bdb265 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_aip.c -@@ -0,0 +1,20 @@ -+#include -+ -+#include "saa716x_mod.h" -+#include "saa716x_aip_reg.h" -+#include "saa716x_spi.h" -+#include "saa716x_aip.h" -+#include "saa716x_priv.h" -+ -+int saa716x_aip_status(struct saa716x_dev *saa716x, u32 dev) -+{ -+ return SAA716x_EPRD(dev, AI_CTL) == 0 ? 0 : -1; -+} -+EXPORT_SYMBOL_GPL(saa716x_aip_status); -+ -+void saa716x_aip_disable(struct saa716x_dev *saa716x) -+{ -+ SAA716x_EPWR(AI0, AI_CTL, 0x00); -+ SAA716x_EPWR(AI1, AI_CTL, 0x00); -+} -+EXPORT_SYMBOL_GPL(saa716x_aip_disable); -diff --git a/drivers/media/common/saa716x/saa716x_aip.h b/drivers/media/common/saa716x/saa716x_aip.h -new file mode 100644 -index 0000000..36277b7 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_aip.h -@@ -0,0 +1,9 @@ -+#ifndef __SAA716x_AIP_H -+#define __SAA716x_AIP_H -+ -+struct saa716x_dev; -+ -+extern int saa716x_aip_status(struct saa716x_dev *saa716x, u32 dev); -+extern void saa716x_aip_disable(struct saa716x_dev *saa716x); -+ -+#endif /* __SAA716x_AIP_H */ -diff --git a/drivers/media/common/saa716x/saa716x_aip_reg.h b/drivers/media/common/saa716x/saa716x_aip_reg.h -new file mode 100644 -index 0000000..3e0893a ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_aip_reg.h -@@ -0,0 +1,62 @@ -+#ifndef __SAA716x_AIP_REG_H -+#define __SAA716x_AIP_REG_H -+ -+/* -------------- AI Registers ---------------- */ -+ -+#define AI_STATUS 0x000 -+#define AI_BUF1_ACTIVE (0x00000001 << 4) -+#define AI_OVERRUN (0x00000001 << 3) -+#define AI_HBE (0x00000001 << 2) -+#define AI_BUF2_FULL (0x00000001 << 1) -+#define AI_BUF1_FULL (0x00000001 << 0) -+ -+#define AI_CTL 0x004 -+#define AI_RESET (0x00000001 << 31) -+#define AI_CAP_ENABLE (0x00000001 << 30) -+#define AI_CAP_MODE (0x00000003 << 28) -+#define AI_SIGN_CONVERT (0x00000001 << 27) -+#define AI_EARLYMODE (0x00000001 << 26) -+#define AI_DIAGMODE (0x00000001 << 25) -+#define AI_RAWMODE (0x00000001 << 24) -+#define AI_OVR_INTEN (0x00000001 << 7) -+#define AI_HBE_INTEN (0x00000001 << 6) -+#define AI_BUF2_INTEN (0x00000001 << 5) -+#define AI_BUF1_INTEN (0x00000001 << 4) -+#define AI_ACK_OVR (0x00000001 << 3) -+#define AI_ACK_HBE (0x00000001 << 2) -+#define AI_ACK2 (0x00000001 << 1) -+#define AI_ACK1 (0x00000001 << 0) -+ -+#define AI_SERIAL 0x008 -+#define AI_SER_MASTER (0x00000001 << 31) -+#define AI_DATAMODE (0x00000001 << 30) -+#define AI_FRAMEMODE (0x00000003 << 28) -+#define AI_CLOCK_EDGE (0x00000001 << 27) -+#define AI_SSPOS4 (0x00000001 << 19) -+#define AI_NR_CHAN (0x00000003 << 17) -+#define AI_WSDIV (0x000001ff << 8) -+#define AI_SCKDIV (0x000000ff << 0) -+ -+#define AI_FRAMING 0x00c -+#define AI_VALIDPOS (0x000001ff << 22) -+#define AI_LEFTPOS (0x000001ff << 13) -+#define AI_RIGHTPOS (0x000001ff << 4) -+#define AI_SSPOS_3_0 (0x0000000f << 0) -+ -+#define AI_BASE1 0x014 -+#define AI_BASE2 0x018 -+#define AI_BASE (0x03ffffff << 6) -+ -+#define AI_SIZE 0x01c -+#define AI_SAMPLE_SIZE (0x03ffffff << 6) -+ -+#define AI_INT_ACK 0x020 -+#define AI_ACK_OVR (0x00000001 << 3) -+#define AI_ACK_HBE (0x00000001 << 2) -+#define AI_ACK2 (0x00000001 << 1) -+#define AI_ACK1 (0x00000001 << 0) -+ -+#define AI_PWR_DOWN 0xff4 -+#define AI_PWR_DWN (0x00000001 << 0) -+ -+#endif /* __SAA716x_AIP_REG_H */ -diff --git a/drivers/media/common/saa716x/saa716x_boot.c b/drivers/media/common/saa716x/saa716x_boot.c -new file mode 100644 -index 0000000..21e59d0 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_boot.c -@@ -0,0 +1,319 @@ -+#include -+ -+#include "saa716x_mod.h" -+ -+#include "saa716x_greg_reg.h" -+#include "saa716x_cgu_reg.h" -+#include "saa716x_vip_reg.h" -+#include "saa716x_aip_reg.h" -+#include "saa716x_msi_reg.h" -+#include "saa716x_dma_reg.h" -+#include "saa716x_gpio_reg.h" -+#include "saa716x_fgpi_reg.h" -+#include "saa716x_dcs_reg.h" -+ -+#include "saa716x_boot.h" -+#include "saa716x_spi.h" -+#include "saa716x_priv.h" -+ -+static int saa716x_ext_boot(struct saa716x_dev *saa716x) -+{ -+ /* Write GREG boot_ready to 0 -+ * DW_0 = 0x0001_2018 -+ * DW_1 = 0x0000_0000 -+ */ -+ SAA716x_EPWR(GREG, GREG_RSTU_CTRL, 0x00000000); -+ -+ /* Clear VI0 interrupt -+ * DW_2 = 0x0000_0fe8 -+ * DW_3 = 0x0000_03ff -+ */ -+ SAA716x_EPWR(VI0, INT_CLR_STATUS, 0x000003ff); -+ -+ /* Clear VI1 interrupt -+ * DW_4 = 0x0000_1fe8 -+ * DW_5 = 0x0000_03ff -+ */ -+ SAA716x_EPWR(VI1, INT_CLR_STATUS, 0x000003ff); -+ -+ /* CLear FGPI0 interrupt -+ * DW_6 = 0x0000_2fe8 -+ * DW_7 = 0x0000_007f -+ */ -+ SAA716x_EPWR(FGPI0, INT_CLR_STATUS, 0x0000007f); -+ -+ /* Clear FGPI1 interrupt -+ * DW_8 = 0x0000_3fe8 -+ * DW_9 = 0x0000_007f -+ */ -+ SAA716x_EPWR(FGPI1, INT_CLR_STATUS, 0x0000007f); -+ -+ /* Clear FGPI2 interrupt -+ * DW_10 = 0x0000_4fe8 -+ * DW_11 = 0x0000_007f -+ */ -+ SAA716x_EPWR(FGPI2, INT_CLR_STATUS, 0x0000007f); -+ -+ /* Clear FGPI3 interrupt -+ * DW_12 = 0x0000_5fe8 -+ * DW_13 = 0x0000_007f -+ */ -+ SAA716x_EPWR(FGPI3, INT_CLR_STATUS, 0x0000007f); -+ -+ /* Clear AI0 interrupt -+ * DW_14 = 0x0000_6020 -+ * DW_15 = 0x0000_000f -+ */ -+ SAA716x_EPWR(AI0, AI_INT_ACK, 0x0000000f); -+ -+ /* Clear AI1 interrupt -+ * DW_16 = 0x0000_7020 -+ * DW_17 = 0x0000_200f -+ */ -+ SAA716x_EPWR(AI1, AI_INT_ACK, 0x0000000f); -+ -+ /* Set GREG boot_ready bit to 1 -+ * DW_18 = 0x0001_2018 -+ * DW_19 = 0x0000_2000 -+ */ -+ SAA716x_EPWR(GREG, GREG_RSTU_CTRL, 0x00002000); -+#if 0 -+ /* End of Boot script command -+ * DW_20 = 0x0000_0006 -+ * Where to write this value ?? -+ * This seems very odd an address to trigger the -+ * Boot Control State Machine ! -+ */ -+ SAA716x_EPWR(VI0, 0x00000006, 0xffffffff); -+#endif -+ return 0; -+} -+ -+/* Internal Bootscript configuration */ -+static void saa716x_int_boot(struct saa716x_dev *saa716x) -+{ -+ /* #1 Configure PCI COnfig space -+ * GREG_JETSTR_CONFIG_0 -+ */ -+ SAA716x_EPWR(GREG, GREG_SUBSYS_CONFIG, saa716x->pdev->subsystem_vendor); -+ -+ /* GREG_JETSTR_CONFIG_1 -+ * pmcsr_scale:7 = 0x00 -+ * pmcsr_scale:6 = 0x00 -+ * pmcsr_scale:5 = 0x00 -+ * pmcsr_scale:4 = 0x00 -+ * pmcsr_scale:3 = 0x00 -+ * pmcsr_scale:2 = 0x00 -+ * pmcsr_scale:1 = 0x00 -+ * pmcsr_scale:0 = 0x00 -+ * BAR mask = 20 bit -+ * BAR prefetch = no -+ * MSI capable = 32 messages -+ */ -+ SAA716x_EPWR(GREG, GREG_MSI_BAR_PMCSR, 0x00001005); -+ -+ /* GREG_JETSTR_CONFIG_2 -+ * pmcsr_data:3 = 0x0 -+ * pmcsr_data:2 = 0x0 -+ * pmcsr_data:1 = 0x0 -+ * pmcsr_data:0 = 0x0 -+ */ -+ SAA716x_EPWR(GREG, GREG_PMCSR_DATA_1, 0x00000000); -+ -+ /* GREG_JETSTR_CONFIG_3 -+ * pmcsr_data:7 = 0x0 -+ * pmcsr_data:6 = 0x0 -+ * pmcsr_data:5 = 0x0 -+ * pmcsr_data:4 = 0x0 -+ */ -+ SAA716x_EPWR(GREG, GREG_PMCSR_DATA_2, 0x00000000); -+ -+ /* #2 Release GREG resets -+ * ip_rst_an -+ * dpa1_rst_an -+ * jetsream_reset_an -+ */ -+ SAA716x_EPWR(GREG, GREG_RSTU_CTRL, 0x00000e00); -+ -+ /* #3 GPIO Setup -+ * GPIO 25:24 = Output -+ * GPIO Output "0" after Reset -+ */ -+ SAA716x_EPWR(GPIO, GPIO_OEN, 0xfcffffff); -+ -+ /* #4 Custom stuff goes in here */ -+ -+ /* #5 Disable CGU Clocks -+ * except for PHY, Jetstream, DPA1, DCS, Boot, GREG -+ * CGU_PCR_0_3: pss_mmu_clk:0 = 0x0 -+ */ -+ SAA716x_EPWR(CGU, CGU_PCR_0_3, 0x00000006); -+ -+ /* CGU_PCR_0_4: pss_dtl2mtl_mmu_clk:0 = 0x0 */ -+ SAA716x_EPWR(CGU, CGU_PCR_0_4, 0x00000006); -+ -+ /* CGU_PCR_0_5: pss_msi_ck:0 = 0x0 */ -+ SAA716x_EPWR(CGU, CGU_PCR_0_5, 0x00000006); -+ -+ /* CGU_PCR_0_7: pss_gpio_clk:0 = 0x0 */ -+ SAA716x_EPWR(CGU, CGU_PCR_0_7, 0x00000006); -+ -+ /* CGU_PCR_2_1: spi_clk:0 = 0x0 */ -+ SAA716x_EPWR(CGU, CGU_PCR_2_1, 0x00000006); -+ -+ /* CGU_PCR_3_2: i2c_clk:0 = 0x0 */ -+ SAA716x_EPWR(CGU, CGU_PCR_3_2, 0x00000006); -+ -+ /* CGU_PCR_4_1: phi_clk:0 = 0x0 */ -+ SAA716x_EPWR(CGU, CGU_PCR_4_1, 0x00000006); -+ -+ /* CGU_PCR_5: vip0_clk:0 = 0x0 */ -+ SAA716x_EPWR(CGU, CGU_PCR_5, 0x00000006); -+ -+ /* CGU_PCR_6: vip1_clk:0 = 0x0 */ -+ SAA716x_EPWR(CGU, CGU_PCR_6, 0x00000006); -+ -+ /* CGU_PCR_7: fgpi0_clk:0 = 0x0 */ -+ SAA716x_EPWR(CGU, CGU_PCR_7, 0x00000006); -+ -+ /* CGU_PCR_8: fgpi1_clk:0 = 0x0 */ -+ SAA716x_EPWR(CGU, CGU_PCR_8, 0x00000006); -+ -+ /* CGU_PCR_9: fgpi2_clk:0 = 0x0 */ -+ SAA716x_EPWR(CGU, CGU_PCR_9, 0x00000006); -+ -+ /* CGU_PCR_10: fgpi3_clk:0 = 0x0 */ -+ SAA716x_EPWR(CGU, CGU_PCR_10, 0x00000006); -+ -+ /* CGU_PCR_11: ai0_clk:0 = 0x0 */ -+ SAA716x_EPWR(CGU, CGU_PCR_11, 0x00000006); -+ -+ /* CGU_PCR_12: ai1_clk:0 = 0x0 */ -+ SAA716x_EPWR(CGU, CGU_PCR_12, 0x00000006); -+ -+ /* #6 Set GREG boot_ready = 0x1 */ -+ SAA716x_EPWR(GREG, GREG_RSTU_CTRL, 0x00002000); -+ -+ /* #7 Disable GREG CGU Clock */ -+ SAA716x_EPWR(CGU, CGU_PCR_0_6, 0x00000006); -+ -+ /* End of Bootscript command ?? */ -+} -+ -+int saa716x_core_boot(struct saa716x_dev *saa716x) -+{ -+ struct saa716x_config *config = saa716x->config; -+ -+ switch (config->boot_mode) { -+ case SAA716x_EXT_BOOT: -+ dprintk(SAA716x_DEBUG, 1, "Using External Boot from config"); -+ saa716x_ext_boot(saa716x); -+ break; -+ case SAA716x_INT_BOOT: -+ dprintk(SAA716x_DEBUG, 1, "Using Internal Boot from config"); -+ saa716x_int_boot(saa716x); -+ break; -+ default: -+ dprintk(SAA716x_ERROR, 1, "Unknown configuration %d", config->boot_mode); -+ break; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(saa716x_core_boot); -+ -+static void saa716x_bus_report(struct pci_dev *pdev, int enable) -+{ -+ u32 reg; -+ -+ pci_read_config_dword(pdev, 0x04, ®); -+ if (enable) -+ reg |= 0x00000100; /* enable SERR */ -+ else -+ reg &= 0xfffffeff; /* disable SERR */ -+ pci_write_config_dword(pdev, 0x04, reg); -+ -+ pci_read_config_dword(pdev, 0x58, ®); -+ reg &= 0xfffffffd; -+ pci_write_config_dword(pdev, 0x58, reg); -+} -+ -+int saa716x_jetpack_init(struct saa716x_dev *saa716x) -+{ -+ /* -+ * configure PHY through config space not to report -+ * non-fatal error messages to avoid problems with -+ * quirky BIOS'es -+ */ -+ saa716x_bus_report(saa716x->pdev, 0); -+ -+ /* -+ * create time out for blocks that have no clock -+ * helps with lower bitrates on FGPI -+ */ -+ SAA716x_EPWR(DCS, DCSC_CTRL, ENABLE_TIMEOUT); -+ -+ /* Reset all blocks */ -+ SAA716x_EPWR(MSI, MSI_SW_RST, MSI_SW_RESET); -+ SAA716x_EPWR(MMU, MMU_SW_RST, MMU_SW_RESET); -+ SAA716x_EPWR(BAM, BAM_SW_RST, BAM_SW_RESET); -+ -+ switch (saa716x->pdev->device) { -+ case SAA7162: -+ dprintk(SAA716x_DEBUG, 1, "SAA%02x Decoder disable", saa716x->pdev->device); -+ SAA716x_EPWR(GPIO, GPIO_OEN, 0xfcffffff); -+ SAA716x_EPWR(GPIO, GPIO_WR, 0x00000000); /* Disable decoders */ -+ msleep(10); -+ SAA716x_EPWR(GPIO, GPIO_WR, 0x03000000); /* Enable decoders */ -+ break; -+ case SAA7161: -+ dprintk(SAA716x_DEBUG, 1, "SAA%02x Decoder disable", saa716x->pdev->device); -+ SAA716x_EPWR(GPIO, GPIO_OEN, 0xfeffffff); -+ SAA716x_EPWR(GPIO, GPIO_WR, 0x00000000); /* Disable decoders */ -+ msleep(10); -+ SAA716x_EPWR(GPIO, GPIO_WR, 0x01000000); /* Enable decoder */ -+ break; -+ case SAA7160: -+ saa716x->i2c_rate = SAA716x_I2C_RATE_100; -+ break; -+ default: -+ dprintk(SAA716x_ERROR, 1, "Unknown device (0x%02x)", saa716x->pdev->device); -+ return -ENODEV; -+ } -+ -+ /* General setup for MMU */ -+ SAA716x_EPWR(MMU, MMU_MODE, 0x14); -+ dprintk(SAA716x_DEBUG, 1, "SAA%02x Jetpack Successfully initialized", saa716x->pdev->device); -+ -+ return 0; -+} -+EXPORT_SYMBOL(saa716x_jetpack_init); -+ -+void saa716x_core_reset(struct saa716x_dev *saa716x) -+{ -+ dprintk(SAA716x_DEBUG, 1, "RESET Modules"); -+ -+ /* VIP */ -+ SAA716x_EPWR(VI0, VI_MODE, SOFT_RESET); -+ SAA716x_EPWR(VI1, VI_MODE, SOFT_RESET); -+ -+ /* FGPI */ -+ SAA716x_EPWR(FGPI0, FGPI_SOFT_RESET, FGPI_SOFTWARE_RESET); -+ SAA716x_EPWR(FGPI1, FGPI_SOFT_RESET, FGPI_SOFTWARE_RESET); -+ SAA716x_EPWR(FGPI2, FGPI_SOFT_RESET, FGPI_SOFTWARE_RESET); -+ SAA716x_EPWR(FGPI3, FGPI_SOFT_RESET, FGPI_SOFTWARE_RESET); -+ -+ /* AIP */ -+ SAA716x_EPWR(AI0, AI_CTL, AI_RESET); -+ SAA716x_EPWR(AI1, AI_CTL, AI_RESET); -+ -+ /* BAM */ -+ SAA716x_EPWR(BAM, BAM_SW_RST, BAM_SW_RESET); -+ -+ /* MMU */ -+ SAA716x_EPWR(MMU, MMU_SW_RST, MMU_SW_RESET); -+ -+ /* MSI */ -+ SAA716x_EPWR(MSI, MSI_SW_RST, MSI_SW_RESET); -+} -+EXPORT_SYMBOL_GPL(saa716x_core_reset); -diff --git a/drivers/media/common/saa716x/saa716x_boot.h b/drivers/media/common/saa716x/saa716x_boot.h -new file mode 100644 -index 0000000..8102853 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_boot.h -@@ -0,0 +1,18 @@ -+#ifndef __SAA716x_BOOT_H -+#define __SAA716x_BOOT_H -+ -+#define DISABLE_TIMEOUT 0x17 -+#define ENABLE_TIMEOUT 0x16 -+ -+enum saa716x_boot_mode { -+ SAA716x_EXT_BOOT = 1, -+ SAA716x_INT_BOOT, /* GPIO[31:30] = 0x01 */ -+}; -+ -+struct saa716x_dev; -+ -+extern int saa716x_core_boot(struct saa716x_dev *saa716x); -+extern int saa716x_jetpack_init(struct saa716x_dev *saa716x); -+extern void saa716x_core_reset(struct saa716x_dev *saa716x); -+ -+#endif /* __SAA716x_BOOT_H */ -diff --git a/drivers/media/common/saa716x/saa716x_budget.c b/drivers/media/common/saa716x/saa716x_budget.c -new file mode 100644 -index 0000000..6b52fc1 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_budget.c -@@ -0,0 +1,717 @@ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#include "saa716x_mod.h" -+ -+#include "saa716x_gpio_reg.h" -+#include "saa716x_greg_reg.h" -+#include "saa716x_msi_reg.h" -+ -+#include "saa716x_adap.h" -+#include "saa716x_i2c.h" -+#include "saa716x_msi.h" -+#include "saa716x_budget.h" -+#include "saa716x_gpio.h" -+#include "saa716x_rom.h" -+#include "saa716x_spi.h" -+#include "saa716x_priv.h" -+ -+#include "mb86a16.h" -+#include "stv6110x.h" -+#include "stv090x.h" -+#include "ds3103.h" -+#include "ts2022.h" -+ -+unsigned int verbose; -+module_param(verbose, int, 0644); -+MODULE_PARM_DESC(verbose, "verbose startup messages, default is 1 (yes)"); -+ -+unsigned int int_type; -+module_param(int_type, int, 0644); -+MODULE_PARM_DESC(int_type, "force Interrupt Handler type: 0=INT-A, 1=MSI, 2=MSI-X. default INT-A mode"); -+ -+#define DRIVER_NAME "SAA716x Budget" -+ -+static int saa716x_budget_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pci_id) -+{ -+ struct saa716x_dev *saa716x; -+ int err = 0; -+ -+ saa716x = kzalloc(sizeof (struct saa716x_dev), GFP_KERNEL); -+ if (saa716x == NULL) { -+ printk(KERN_ERR "saa716x_budget_pci_probe ERROR: out of memory\n"); -+ err = -ENOMEM; -+ goto fail0; -+ } -+ -+ saa716x->verbose = verbose; -+ saa716x->int_type = int_type; -+ saa716x->pdev = pdev; -+ saa716x->config = (struct saa716x_config *) pci_id->driver_data; -+ -+ err = saa716x_pci_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x PCI Initialization failed"); -+ goto fail1; -+ } -+ -+ err = saa716x_cgu_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x CGU Init failed"); -+ goto fail1; -+ } -+ -+ err = saa716x_core_boot(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x Core Boot failed"); -+ goto fail2; -+ } -+ dprintk(SAA716x_DEBUG, 1, "SAA716x Core Boot Success"); -+ -+ err = saa716x_msi_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x MSI Init failed"); -+ goto fail2; -+ } -+ -+ err = saa716x_jetpack_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x Jetpack core initialization failed"); -+ goto fail1; -+ } -+ -+ err = saa716x_i2c_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x I2C Initialization failed"); -+ goto fail3; -+ } -+ -+ saa716x_gpio_init(saa716x); -+ -+ err = saa716x_dump_eeprom(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x EEPROM dump failed"); -+ } -+ -+ err = saa716x_eeprom_data(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x EEPROM read failed"); -+ } -+ -+ /* set default port mapping */ -+ SAA716x_EPWR(GREG, GREG_VI_CTRL, 0x04080FA9); -+ /* enable FGPI3 and FGPI1 for TS input from Port 2 and 6 */ -+ SAA716x_EPWR(GREG, GREG_FGPI_CTRL, 0x321); -+ -+ err = saa716x_dvb_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x DVB initialization failed"); -+ goto fail4; -+ } -+ -+ return 0; -+ -+fail4: -+ saa716x_dvb_exit(saa716x); -+fail3: -+ saa716x_i2c_exit(saa716x); -+fail2: -+ saa716x_pci_exit(saa716x); -+fail1: -+ kfree(saa716x); -+fail0: -+ return err; -+} -+ -+static void saa716x_budget_pci_remove(struct pci_dev *pdev) -+{ -+ struct saa716x_dev *saa716x = pci_get_drvdata(pdev); -+ -+ saa716x_dvb_exit(saa716x); -+ saa716x_i2c_exit(saa716x); -+ saa716x_pci_exit(saa716x); -+ kfree(saa716x); -+} -+ -+static irqreturn_t saa716x_budget_pci_irq(int irq, void *dev_id) -+{ -+ struct saa716x_dev *saa716x = (struct saa716x_dev *) dev_id; -+ -+ u32 stat_h, stat_l, mask_h, mask_l; -+ -+ if (unlikely(saa716x == NULL)) { -+ printk("%s: saa716x=NULL", __func__); -+ return IRQ_NONE; -+ } -+ -+ stat_l = SAA716x_EPRD(MSI, MSI_INT_STATUS_L); -+ stat_h = SAA716x_EPRD(MSI, MSI_INT_STATUS_H); -+ mask_l = SAA716x_EPRD(MSI, MSI_INT_ENA_L); -+ mask_h = SAA716x_EPRD(MSI, MSI_INT_ENA_H); -+ -+ dprintk(SAA716x_DEBUG, 1, "MSI STAT L=<%02x> H=<%02x>, CTL L=<%02x> H=<%02x>", -+ stat_l, stat_h, mask_l, mask_h); -+ -+ if (!((stat_l & mask_l) || (stat_h & mask_h))) -+ return IRQ_NONE; -+ -+ if (stat_l) -+ SAA716x_EPWR(MSI, MSI_INT_STATUS_CLR_L, stat_l); -+ -+ if (stat_h) -+ SAA716x_EPWR(MSI, MSI_INT_STATUS_CLR_H, stat_h); -+ -+ saa716x_msi_event(saa716x, stat_l, stat_h); -+#if 0 -+ dprintk(SAA716x_DEBUG, 1, "VI STAT 0=<%02x> 1=<%02x>, CTL 1=<%02x> 2=<%02x>", -+ SAA716x_EPRD(VI0, INT_STATUS), -+ SAA716x_EPRD(VI1, INT_STATUS), -+ SAA716x_EPRD(VI0, INT_ENABLE), -+ SAA716x_EPRD(VI1, INT_ENABLE)); -+ -+ dprintk(SAA716x_DEBUG, 1, "FGPI STAT 0=<%02x> 1=<%02x>, CTL 1=<%02x> 2=<%02x>", -+ SAA716x_EPRD(FGPI0, INT_STATUS), -+ SAA716x_EPRD(FGPI1, INT_STATUS), -+ SAA716x_EPRD(FGPI0, INT_ENABLE), -+ SAA716x_EPRD(FGPI0, INT_ENABLE)); -+ -+ dprintk(SAA716x_DEBUG, 1, "FGPI STAT 2=<%02x> 3=<%02x>, CTL 2=<%02x> 3=<%02x>", -+ SAA716x_EPRD(FGPI2, INT_STATUS), -+ SAA716x_EPRD(FGPI3, INT_STATUS), -+ SAA716x_EPRD(FGPI2, INT_ENABLE), -+ SAA716x_EPRD(FGPI3, INT_ENABLE)); -+ -+ dprintk(SAA716x_DEBUG, 1, "AI STAT 0=<%02x> 1=<%02x>, CTL 0=<%02x> 1=<%02x>", -+ SAA716x_EPRD(AI0, AI_STATUS), -+ SAA716x_EPRD(AI1, AI_STATUS), -+ SAA716x_EPRD(AI0, AI_CTL), -+ SAA716x_EPRD(AI1, AI_CTL)); -+ -+ dprintk(SAA716x_DEBUG, 1, "I2C STAT 0=<%02x> 1=<%02x>, CTL 0=<%02x> 1=<%02x>", -+ SAA716x_EPRD(I2C_A, INT_STATUS), -+ SAA716x_EPRD(I2C_B, INT_STATUS), -+ SAA716x_EPRD(I2C_A, INT_ENABLE), -+ SAA716x_EPRD(I2C_B, INT_ENABLE)); -+ -+ dprintk(SAA716x_DEBUG, 1, "DCS STAT=<%02x>, CTL=<%02x>", -+ SAA716x_EPRD(DCS, DCSC_INT_STATUS), -+ SAA716x_EPRD(DCS, DCSC_INT_ENABLE)); -+#endif -+ -+ if (stat_l) { -+ if (stat_l & MSI_INT_TAGACK_FGPI_0) { -+ tasklet_schedule(&saa716x->fgpi[0].tasklet); -+ } -+ if (stat_l & MSI_INT_TAGACK_FGPI_1) { -+ tasklet_schedule(&saa716x->fgpi[1].tasklet); -+ } -+ if (stat_l & MSI_INT_TAGACK_FGPI_2) { -+ tasklet_schedule(&saa716x->fgpi[2].tasklet); -+ } -+ if (stat_l & MSI_INT_TAGACK_FGPI_3) { -+ tasklet_schedule(&saa716x->fgpi[3].tasklet); -+ } -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static void demux_worker(unsigned long data) -+{ -+ struct saa716x_fgpi_stream_port *fgpi_entry = (struct saa716x_fgpi_stream_port *)data; -+ struct saa716x_dev *saa716x = fgpi_entry->saa716x; -+ struct dvb_demux *demux; -+ u32 fgpi_index; -+ u32 i; -+ u32 write_index; -+ -+ fgpi_index = fgpi_entry->dma_channel - 6; -+ demux = NULL; -+ for (i = 0; i < saa716x->config->adapters; i++) { -+ if (saa716x->config->adap_config[i].ts_port == fgpi_index) { -+ demux = &saa716x->saa716x_adap[i].demux; -+ break; -+ } -+ } -+ if (demux == NULL) { -+ printk(KERN_ERR "%s: unexpected channel %u\n", -+ __func__, fgpi_entry->dma_channel); -+ return; -+ } -+ -+ write_index = saa716x_fgpi_get_write_index(saa716x, fgpi_index); -+ if (write_index < 0) -+ return; -+ -+ dprintk(SAA716x_DEBUG, 1, "dma buffer = %d", write_index); -+ -+ if (write_index == fgpi_entry->read_index) { -+ printk(KERN_DEBUG "%s: called but nothing to do\n", __func__); -+ return; -+ } -+ -+ do { -+ u8 *data = (u8 *)fgpi_entry->dma_buf[fgpi_entry->read_index].mem_virt; -+ -+ pci_dma_sync_sg_for_cpu(saa716x->pdev, -+ fgpi_entry->dma_buf[fgpi_entry->read_index].sg_list, -+ fgpi_entry->dma_buf[fgpi_entry->read_index].list_len, -+ PCI_DMA_FROMDEVICE); -+ -+ dvb_dmx_swfilter(demux, data, 348 * 188); -+ -+ fgpi_entry->read_index = (fgpi_entry->read_index + 1) & 7; -+ } while (write_index != fgpi_entry->read_index); -+} -+ -+ -+#define SAA716x_MODEL_TWINHAN_VP3071 "Twinhan/Azurewave VP-3071" -+#define SAA716x_DEV_TWINHAN_VP3071 "2x DVB-T" -+ -+static int saa716x_vp3071_frontend_attach(struct saa716x_adapter *adapter, int count) -+{ -+ struct saa716x_dev *saa716x = adapter->saa716x; -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) SAA716x frontend Init", count); -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) Device ID=%02x", count, saa716x->pdev->subsystem_device); -+ -+ return -ENODEV; -+} -+ -+static struct saa716x_config saa716x_vp3071_config = { -+ .model_name = SAA716x_MODEL_TWINHAN_VP3071, -+ .dev_type = SAA716x_DEV_TWINHAN_VP3071, -+ .boot_mode = SAA716x_EXT_BOOT, -+ .adapters = 2, -+ .frontend_attach = saa716x_vp3071_frontend_attach, -+ .irq_handler = saa716x_budget_pci_irq, -+ .i2c_rate = SAA716x_I2C_RATE_100, -+}; -+ -+ -+#define SAA716x_MODEL_TWINHAN_VP1028 "Twinhan/Azurewave VP-1028" -+#define SAA716x_DEV_TWINHAN_VP1028 "DVB-S" -+ -+static int vp1028_dvbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) -+{ -+ struct saa716x_dev *saa716x = fe->dvb->priv; -+ -+ switch (voltage) { -+ case SEC_VOLTAGE_13: -+ dprintk(SAA716x_ERROR, 1, "Polarization=[13V]"); -+ break; -+ case SEC_VOLTAGE_18: -+ dprintk(SAA716x_ERROR, 1, "Polarization=[18V]"); -+ break; -+ case SEC_VOLTAGE_OFF: -+ dprintk(SAA716x_ERROR, 1, "Frontend (dummy) POWERDOWN"); -+ break; -+ default: -+ dprintk(SAA716x_ERROR, 1, "Invalid = (%d)", (u32 ) voltage); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+struct mb86a16_config vp1028_mb86a16_config = { -+ .demod_address = 0x08, -+ .set_voltage = vp1028_dvbs_set_voltage, -+}; -+ -+static int saa716x_vp1028_frontend_attach(struct saa716x_adapter *adapter, int count) -+{ -+ struct saa716x_dev *saa716x = adapter->saa716x; -+ struct saa716x_i2c *i2c = &saa716x->i2c[1]; -+ -+ if (count == 0) { -+ -+ mutex_lock(&saa716x->adap_lock); -+ -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) Power ON", count); -+ saa716x_gpio_set_output(saa716x, 10); -+ msleep(1); -+ -+ /* VP-1028 has inverted power supply control */ -+ saa716x_gpio_write(saa716x, 10, 1); /* set to standby */ -+ saa716x_gpio_write(saa716x, 10, 0); /* switch it on */ -+ msleep(100); -+ -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) Reset", count); -+ saa716x_gpio_set_output(saa716x, 12); -+ msleep(1); -+ -+ /* reset demodulator (Active LOW) */ -+ saa716x_gpio_write(saa716x, 12, 1); -+ msleep(100); -+ saa716x_gpio_write(saa716x, 12, 0); -+ msleep(100); -+ saa716x_gpio_write(saa716x, 12, 1); -+ msleep(100); -+ -+ mutex_unlock(&saa716x->adap_lock); -+ -+ dprintk(SAA716x_ERROR, 1, "Probing for MB86A16 (DVB-S/DSS)"); -+ adapter->fe = mb86a16_attach(&vp1028_mb86a16_config, &i2c->i2c_adapter); -+ if (adapter->fe) { -+ dprintk(SAA716x_ERROR, 1, "found MB86A16 DVB-S/DSS frontend @0x%02x", -+ vp1028_mb86a16_config.demod_address); -+ -+ } else { -+ goto exit; -+ } -+ dprintk(SAA716x_ERROR, 1, "Done!"); -+ } -+ -+ return 0; -+exit: -+ dprintk(SAA716x_ERROR, 1, "Frontend attach failed"); -+ return -ENODEV; -+} -+ -+static struct saa716x_config saa716x_vp1028_config = { -+ .model_name = SAA716x_MODEL_TWINHAN_VP1028, -+ .dev_type = SAA716x_DEV_TWINHAN_VP1028, -+ .boot_mode = SAA716x_EXT_BOOT, -+ .adapters = 1, -+ .frontend_attach = saa716x_vp1028_frontend_attach, -+ .irq_handler = saa716x_budget_pci_irq, -+ .i2c_rate = SAA716x_I2C_RATE_100, -+}; -+ -+ -+#define SAA716x_MODEL_TWINHAN_VP6002 "Twinhan/Azurewave VP-6002" -+#define SAA716x_DEV_TWINHAN_VP6002 "DVB-S" -+ -+static int saa716x_vp6002_frontend_attach(struct saa716x_adapter *adapter, int count) -+{ -+ struct saa716x_dev *saa716x = adapter->saa716x; -+ -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) SAA716x frontend Init", count); -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) Device ID=%02x", count, saa716x->pdev->subsystem_device); -+ -+ return -ENODEV; -+} -+ -+static struct saa716x_config saa716x_vp6002_config = { -+ .model_name = SAA716x_MODEL_TWINHAN_VP6002, -+ .dev_type = SAA716x_DEV_TWINHAN_VP6002, -+ .boot_mode = SAA716x_EXT_BOOT, -+ .adapters = 1, -+ .frontend_attach = saa716x_vp6002_frontend_attach, -+ .irq_handler = saa716x_budget_pci_irq, -+ .i2c_rate = SAA716x_I2C_RATE_100, -+}; -+ -+ -+#define SAA716x_MODEL_KNC1_DUALS2 "KNC One Dual S2" -+#define SAA716x_DEV_KNC1_DUALS2 "1xDVB-S + 1xDVB-S/S2" -+ -+static int saa716x_knc1_duals2_frontend_attach(struct saa716x_adapter *adapter, int count) -+{ -+ struct saa716x_dev *saa716x = adapter->saa716x; -+ -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) SAA716x frontend Init", count); -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) Device ID=%02x", count, saa716x->pdev->subsystem_device); -+ -+ return -ENODEV; -+} -+ -+static struct saa716x_config saa716x_knc1_duals2_config = { -+ .model_name = SAA716x_MODEL_KNC1_DUALS2, -+ .dev_type = SAA716x_DEV_KNC1_DUALS2, -+ .boot_mode = SAA716x_EXT_BOOT, -+ .adapters = 2, -+ .frontend_attach = saa716x_knc1_duals2_frontend_attach, -+ .irq_handler = saa716x_budget_pci_irq, -+ .i2c_rate = SAA716x_I2C_RATE_100, -+}; -+ -+ -+#define SAA716x_MODEL_SKYSTAR2_EXPRESS_HD "SkyStar 2 eXpress HD" -+#define SAA716x_DEV_SKYSTAR2_EXPRESS_HD "DVB-S/S2" -+ -+static struct stv090x_config skystar2_stv090x_config = { -+ .device = STV0903, -+ .demod_mode = STV090x_SINGLE, -+ .clk_mode = STV090x_CLK_EXT, -+ -+ .xtal = 8000000, -+ .address = 0x68, -+ -+ .ts1_mode = STV090x_TSMODE_DVBCI, -+ .ts2_mode = STV090x_TSMODE_SERIAL_CONTINUOUS, -+ -+ .repeater_level = STV090x_RPTLEVEL_16, -+ -+ .tuner_init = NULL, -+ .tuner_sleep = NULL, -+ .tuner_set_mode = NULL, -+ .tuner_set_frequency = NULL, -+ .tuner_get_frequency = NULL, -+ .tuner_set_bandwidth = NULL, -+ .tuner_get_bandwidth = NULL, -+ .tuner_set_bbgain = NULL, -+ .tuner_get_bbgain = NULL, -+ .tuner_set_refclk = NULL, -+ .tuner_get_status = NULL, -+}; -+ -+static int skystar2_set_voltage(struct dvb_frontend *fe, -+ enum fe_sec_voltage voltage) -+{ -+ int err; -+ u8 en = 0; -+ u8 sel = 0; -+ -+ switch (voltage) { -+ case SEC_VOLTAGE_OFF: -+ en = 0; -+ break; -+ -+ case SEC_VOLTAGE_13: -+ en = 1; -+ sel = 0; -+ break; -+ -+ case SEC_VOLTAGE_18: -+ en = 1; -+ sel = 1; -+ break; -+ -+ default: -+ break; -+ } -+ -+ err = stv090x_set_gpio(fe, 2, 0, en, 0); -+ if (err < 0) -+ goto exit; -+ err = stv090x_set_gpio(fe, 3, 0, sel, 0); -+ if (err < 0) -+ goto exit; -+ -+ return 0; -+exit: -+ return err; -+} -+ -+static int skystar2_voltage_boost(struct dvb_frontend *fe, long arg) -+{ -+ int err; -+ u8 value; -+ -+ if (arg) -+ value = 1; -+ else -+ value = 0; -+ -+ err = stv090x_set_gpio(fe, 4, 0, value, 0); -+ if (err < 0) -+ goto exit; -+ -+ return 0; -+exit: -+ return err; -+} -+ -+static struct stv6110x_config skystar2_stv6110x_config = { -+ .addr = 0x60, -+ .refclk = 16000000, -+ .clk_div = 2, -+}; -+ -+static int skystar2_express_hd_frontend_attach(struct saa716x_adapter *adapter, -+ int count) -+{ -+ struct saa716x_dev *saa716x = adapter->saa716x; -+ struct saa716x_i2c *i2c = &saa716x->i2c[SAA716x_I2C_BUS_B]; -+ struct stv6110x_devctl *ctl; -+ -+ if (count < saa716x->config->adapters) { -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) SAA716x frontend Init", -+ count); -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) Device ID=%02x", count, -+ saa716x->pdev->subsystem_device); -+ -+ saa716x_gpio_set_output(saa716x, 26); -+ -+ /* Reset the demodulator */ -+ saa716x_gpio_write(saa716x, 26, 1); -+ msleep(10); -+ saa716x_gpio_write(saa716x, 26, 0); -+ msleep(10); -+ saa716x_gpio_write(saa716x, 26, 1); -+ msleep(10); -+ -+ adapter->fe = dvb_attach(stv090x_attach, -+ &skystar2_stv090x_config, -+ &i2c->i2c_adapter, -+ STV090x_DEMODULATOR_0); -+ -+ if (adapter->fe) { -+ dprintk(SAA716x_NOTICE, 1, "found STV0903 @0x%02x", -+ skystar2_stv090x_config.address); -+ } else { -+ goto exit; -+ } -+ -+ adapter->fe->ops.set_voltage = skystar2_set_voltage; -+ adapter->fe->ops.enable_high_lnb_voltage = skystar2_voltage_boost; -+ -+ ctl = dvb_attach(stv6110x_attach, -+ adapter->fe, -+ &skystar2_stv6110x_config, -+ &i2c->i2c_adapter); -+ -+ if (ctl) { -+ dprintk(SAA716x_NOTICE, 1, "found STV6110(A) @0x%02x", -+ skystar2_stv6110x_config.addr); -+ -+ skystar2_stv090x_config.tuner_init = ctl->tuner_init; -+ skystar2_stv090x_config.tuner_sleep = ctl->tuner_sleep; -+ skystar2_stv090x_config.tuner_set_mode = ctl->tuner_set_mode; -+ skystar2_stv090x_config.tuner_set_frequency = ctl->tuner_set_frequency; -+ skystar2_stv090x_config.tuner_get_frequency = ctl->tuner_get_frequency; -+ skystar2_stv090x_config.tuner_set_bandwidth = ctl->tuner_set_bandwidth; -+ skystar2_stv090x_config.tuner_get_bandwidth = ctl->tuner_get_bandwidth; -+ skystar2_stv090x_config.tuner_set_bbgain = ctl->tuner_set_bbgain; -+ skystar2_stv090x_config.tuner_get_bbgain = ctl->tuner_get_bbgain; -+ skystar2_stv090x_config.tuner_set_refclk = ctl->tuner_set_refclk; -+ skystar2_stv090x_config.tuner_get_status = ctl->tuner_get_status; -+ -+ /* call the init function once to initialize -+ tuner's clock output divider and demod's -+ master clock */ -+ if (adapter->fe->ops.init) -+ adapter->fe->ops.init(adapter->fe); -+ } else { -+ goto exit; -+ } -+ -+ dprintk(SAA716x_ERROR, 1, "Done!"); -+ return 0; -+ } -+exit: -+ dprintk(SAA716x_ERROR, 1, "Frontend attach failed"); -+ return -ENODEV; -+} -+ -+static struct saa716x_config skystar2_express_hd_config = { -+ .model_name = SAA716x_MODEL_SKYSTAR2_EXPRESS_HD, -+ .dev_type = SAA716x_DEV_SKYSTAR2_EXPRESS_HD, -+ .boot_mode = SAA716x_EXT_BOOT, -+ .adapters = 1, -+ .frontend_attach = skystar2_express_hd_frontend_attach, -+ .irq_handler = saa716x_budget_pci_irq, -+ .i2c_rate = SAA716x_I2C_RATE_100, -+ .adap_config = { -+ { -+ /* Adapter 0 */ -+ .ts_port = 1, /* using FGPI 1 */ -+ .worker = demux_worker -+ } -+ } -+}; -+ -+static struct ds3103_config s472_ds3103_config = { -+ .demod_address = 0x68, -+ .ci_mode = 1, -+}; -+ -+static int saa716x_s472_frontend_attach(struct saa716x_adapter *adapter, int count) -+{ -+ struct saa716x_dev *saa716x = adapter->saa716x; -+ struct saa716x_i2c *i2c = &saa716x->i2c[1]; -+ -+ if (count != 0) -+ return 0; -+ -+ dprintk(SAA716x_ERROR, 1, "Probing for DS3103 (DVB-S/S2)"); -+ adapter->fe = dvb_attach(ds3103_attach, &s472_ds3103_config, -+ &i2c->i2c_adapter); -+ -+ if (adapter->fe == NULL) { -+ dprintk(SAA716x_ERROR, 1, "Frontend attach failed"); -+ return -ENODEV; -+ } -+ -+ dprintk(SAA716x_ERROR, 1, "found DS3103 DVB-S/S2 frontend @0x%02x", -+ s472_ds3103_config.demod_address); -+ if (NULL == dvb_attach(ts2022_attach, adapter->fe, 0x60, &i2c->i2c_adapter)) -+ dprintk(SAA716x_ERROR, 1, "ts2022 attach failed"); -+ else -+ dprintk(SAA716x_ERROR, 1, "ts2022 attached!"); -+ -+ dprintk(SAA716x_ERROR, 1, "Done!"); -+ return 0; -+ -+} -+ -+static struct saa716x_config tevii_s472_config = { -+ .model_name = "TeVii S472 DVB-S2", -+ .dev_type = "DVB-S/S2", -+ .boot_mode = SAA716x_EXT_BOOT, -+ .adapters = 1, -+ .frontend_attach = saa716x_s472_frontend_attach, -+ .irq_handler = saa716x_budget_pci_irq, -+ .i2c_rate = SAA716x_I2C_RATE_100, -+ .adap_config = { -+ { -+ /* Adapter 0 */ -+ .ts_port = 1, /* using FGPI 1 */ -+ .worker = demux_worker -+ } -+ } -+}; -+ -+static struct pci_device_id saa716x_budget_pci_table[] = { -+ -+ MAKE_ENTRY(TWINHAN_TECHNOLOGIES, TWINHAN_VP_1028, SAA7160, &saa716x_vp1028_config), /* VP-1028 */ -+ MAKE_ENTRY(TWINHAN_TECHNOLOGIES, TWINHAN_VP_3071, SAA7160, &saa716x_vp3071_config), /* VP-3071 */ -+ MAKE_ENTRY(TWINHAN_TECHNOLOGIES, TWINHAN_VP_6002, SAA7160, &saa716x_vp6002_config), /* VP-6002 */ -+ MAKE_ENTRY(KNC_One, KNC_Dual_S2, SAA7160, &saa716x_knc1_duals2_config), -+ MAKE_ENTRY(TECHNISAT, SKYSTAR2_EXPRESS_HD, SAA7160, &skystar2_express_hd_config), -+ MAKE_ENTRY(TEVII, TEVII_S472, SAA7160, &tevii_s472_config), -+ { } -+}; -+MODULE_DEVICE_TABLE(pci, saa716x_budget_pci_table); -+ -+static struct pci_driver saa716x_budget_pci_driver = { -+ .name = DRIVER_NAME, -+ .id_table = saa716x_budget_pci_table, -+ .probe = saa716x_budget_pci_probe, -+ .remove = saa716x_budget_pci_remove, -+}; -+ -+static int saa716x_budget_init(void) -+{ -+ return pci_register_driver(&saa716x_budget_pci_driver); -+} -+ -+static void saa716x_budget_exit(void) -+{ -+ return pci_unregister_driver(&saa716x_budget_pci_driver); -+} -+ -+module_init(saa716x_budget_init); -+module_exit(saa716x_budget_exit); -+ -+MODULE_DESCRIPTION("SAA716x Budget driver"); -+MODULE_AUTHOR("Manu Abraham"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/media/common/saa716x/saa716x_budget.h b/drivers/media/common/saa716x/saa716x_budget.h -new file mode 100644 -index 0000000..d6b8c46 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_budget.h -@@ -0,0 +1,17 @@ -+#ifndef __SAA716x_BUDGET_H -+#define __SAA716x_BUDGET_H -+ -+#define TWINHAN_TECHNOLOGIES 0x1822 -+#define TWINHAN_VP_3071 0x0039 -+#define TWINHAN_VP_1028 0x0044 -+#define TWINHAN_VP_6002 0x0047 -+ -+#define KNC_One 0x1894 -+#define KNC_Dual_S2 0x0110 -+ -+#define TECHNISAT 0x1AE4 -+#define SKYSTAR2_EXPRESS_HD 0x0700 -+#define TEVII 0x9022 -+#define TEVII_S472 0xd472 -+ -+#endif /* __SAA716x_BUDGET_H */ -diff --git a/drivers/media/common/saa716x/saa716x_cgu.c b/drivers/media/common/saa716x/saa716x_cgu.c -new file mode 100644 -index 0000000..a0ffb04 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_cgu.c -@@ -0,0 +1,539 @@ -+#include -+ -+#include "saa716x_mod.h" -+ -+#include "saa716x_cgu_reg.h" -+#include "saa716x_spi.h" -+#include "saa716x_priv.h" -+ -+u32 cgu_clk[14] = { -+ CGU_FDC_0, -+ CGU_FDC_1, -+ CGU_FDC_2, -+ CGU_FDC_3, -+ CGU_FDC_4, -+ CGU_FDC_5, -+ CGU_FDC_6, -+ CGU_FDC_7, -+ CGU_FDC_8, -+ CGU_FDC_9, -+ CGU_FDC_10, -+ CGU_FDC_11, -+ CGU_FDC_12, -+ CGU_FDC_13 -+}; -+ -+char *clk_desc[14] = { -+ "Clk PSS", -+ "Clk DCS", -+ "Clk SPI", -+ "Clk I2C/Boot", -+ "Clk PHI", -+ "Clk VI0", -+ "Clk VI1", -+ "Clk FGPI0", -+ "Clk FGPI1", -+ "Clk FGPI2", -+ "Clk FGPI3", -+ "Clk AI0", -+ "Clk AI1", -+ "Clk Phy" -+}; -+ -+int saa716x_getbootscript_setup(struct saa716x_dev *saa716x) -+{ -+ struct saa716x_cgu *cgu = &saa716x->cgu; -+ -+ u8 i; -+ s8 N = 0; -+ s16 M = 0; -+ -+ SAA716x_EPWR(CGU, CGU_PCR_0_6, CGU_PCR_RUN); /* GREG */ -+ SAA716x_EPWR(CGU, CGU_PCR_0_3, CGU_PCR_RUN); /* PSS_MMU */ -+ SAA716x_EPWR(CGU, CGU_PCR_0_4, CGU_PCR_RUN); /* PSS_DTL2MTL */ -+ SAA716x_EPWR(CGU, CGU_PCR_0_5, CGU_PCR_RUN); /* MSI */ -+ SAA716x_EPWR(CGU, CGU_PCR_3_2, CGU_PCR_RUN); /* I2C */ -+ SAA716x_EPWR(CGU, CGU_PCR_4_1, CGU_PCR_RUN); /* PHI */ -+ SAA716x_EPWR(CGU, CGU_PCR_0_7, CGU_PCR_RUN); /* GPIO */ -+ SAA716x_EPWR(CGU, CGU_PCR_2_1, CGU_PCR_RUN); /* SPI */ -+ SAA716x_EPWR(CGU, CGU_PCR_1_1, CGU_PCR_RUN); /* DCS */ -+ SAA716x_EPWR(CGU, CGU_PCR_3_1, CGU_PCR_RUN); /* BOOT */ -+ -+ /* get all dividers */ -+ for (i = 0; i < CGU_CLKS; i++) { -+ cgu->clk_boot_div[i] = SAA716x_EPRD(CGU, cgu_clk[i]); -+ cgu->clk_curr_div[i] = cgu->clk_boot_div[i]; -+ -+ N = (cgu->clk_boot_div[i] >> 11) & 0xff; -+ N *= -1; -+ M = ((cgu->clk_boot_div[i] >> 3) & 0xff) + N; -+ -+ if (M) -+ cgu->clk_freq[i] = (u32 ) N * PLL_FREQ / (u32 ) M; -+ else -+ cgu->clk_freq[i] = 0; -+ -+ dprintk(SAA716x_DEBUG, 1, "Domain %d: %s <0x%02x> Divider: 0x%x --> N=%d, M=%d, freq=%d", -+ i, clk_desc[i], cgu_clk[i], cgu->clk_boot_div[i], N, M, cgu->clk_freq[i]); -+ } -+ /* store clock settings */ -+ cgu->clk_vi_0[0] = cgu->clk_freq[CLK_DOMAIN_VI0]; -+ cgu->clk_vi_0[1] = cgu->clk_freq[CLK_DOMAIN_VI0]; -+ cgu->clk_vi_0[2] = cgu->clk_freq[CLK_DOMAIN_VI0]; -+ cgu->clk_vi_1[0] = cgu->clk_freq[CLK_DOMAIN_VI1]; -+ cgu->clk_vi_1[1] = cgu->clk_freq[CLK_DOMAIN_VI1]; -+ cgu->clk_vi_1[2] = cgu->clk_freq[CLK_DOMAIN_VI1]; -+ -+ return 0; -+} -+ -+int saa716x_set_clk_internal(struct saa716x_dev *saa716x, u32 port) -+{ -+ struct saa716x_cgu *cgu = &saa716x->cgu; -+ -+ u8 delay = 1; -+ -+ switch (port) { -+ case PORT_VI0_VIDEO: -+ cgu->clk_int_port[PORT_VI0_VIDEO] = 1; -+ -+ if (!cgu->clk_int_port[PORT_VI0_VBI]) { -+ delay = 0; -+ break; -+ } -+ -+ SAA716x_CGU_CLKRUN(5); -+ break; -+ -+ case PORT_VI0_VBI: -+ cgu->clk_int_port[PORT_VI0_VBI] = 1; -+ -+ if (!cgu->clk_int_port[PORT_VI0_VIDEO]) { -+ delay = 0; -+ break; -+ } -+ -+ SAA716x_CGU_CLKRUN(5); -+ break; -+ -+ case PORT_VI1_VIDEO: -+ cgu->clk_int_port[PORT_VI1_VIDEO] = 1; -+ -+ if (!cgu->clk_int_port[PORT_VI1_VBI]) { -+ delay = 0; -+ break; -+ } -+ -+ SAA716x_CGU_CLKRUN(6); -+ break; -+ -+ case PORT_VI1_VBI: -+ cgu->clk_int_port[PORT_VI1_VBI] = 1; -+ -+ if (!cgu->clk_int_port[PORT_VI1_VIDEO]) { -+ delay = 0; -+ break; -+ } -+ -+ SAA716x_CGU_CLKRUN(6); -+ break; -+ -+ case PORT_FGPI0: -+ cgu->clk_int_port[PORT_FGPI0] = 1; -+ SAA716x_CGU_CLKRUN(7); -+ break; -+ -+ case PORT_FGPI1: -+ cgu->clk_int_port[PORT_FGPI1] = 1; -+ SAA716x_CGU_CLKRUN(8); -+ break; -+ -+ case PORT_FGPI2: -+ cgu->clk_int_port[PORT_FGPI2] = 1; -+ SAA716x_CGU_CLKRUN(9); -+ break; -+ -+ case PORT_FGPI3: -+ cgu->clk_int_port[PORT_FGPI3] = 1; -+ SAA716x_CGU_CLKRUN(10); -+ break; -+ -+ case PORT_AI0: -+ cgu->clk_int_port[PORT_AI0] = 1; -+ SAA716x_CGU_CLKRUN(11); -+ break; -+ -+ case PORT_AI1: -+ cgu->clk_int_port[PORT_AI1] = 1; -+ SAA716x_CGU_CLKRUN(12); -+ break; -+ -+ case PORT_ALL: -+ SAA716x_CGU_CLKRUN(5); -+ SAA716x_CGU_CLKRUN(6); -+ SAA716x_CGU_CLKRUN(7); -+ SAA716x_CGU_CLKRUN(8); -+ SAA716x_CGU_CLKRUN(9); -+ SAA716x_CGU_CLKRUN(10); -+ SAA716x_CGU_CLKRUN(11); -+ SAA716x_CGU_CLKRUN(12); -+ -+ cgu->clk_int_port[PORT_VI0_VIDEO] = 1; -+ cgu->clk_int_port[PORT_VI0_VBI] = 1; -+ cgu->clk_int_port[PORT_VI1_VIDEO] = 1; -+ cgu->clk_int_port[PORT_VI1_VBI] = 1; -+ cgu->clk_int_port[PORT_FGPI0] = 1; -+ cgu->clk_int_port[PORT_FGPI1] = 1; -+ cgu->clk_int_port[PORT_FGPI2] = 1; -+ cgu->clk_int_port[PORT_FGPI3] = 1; -+ cgu->clk_int_port[PORT_AI0] = 1; -+ cgu->clk_int_port[PORT_AI1] = 1; -+ break; -+ -+ default: -+ dprintk(SAA716x_ERROR, 1, "Unknown port <%02x>", port); -+ delay = 0; -+ break; -+ } -+ -+ /* wait for PLL */ -+ if (delay) -+ msleep(1); -+ -+ return 0; -+} -+ -+int saa716x_set_clk_external(struct saa716x_dev *saa716x, u32 port) -+{ -+ struct saa716x_cgu *cgu = &saa716x->cgu; -+ -+ u8 delay = 1; -+ -+ switch (port) { -+ case PORT_VI0_VIDEO: -+ cgu->clk_int_port[PORT_VI0_VIDEO] = 0; -+ -+ if (!cgu->clk_int_port[PORT_VI0_VBI]) { -+ delay = 0; -+ break; -+ } -+ -+ SAA716x_EPWR(CGU, CGU_FS1_5, 0x2); /* VI 0 clk */ -+ SAA716x_EPWR(CGU, CGU_ESR_5, 0x0); /* disable divider */ -+ break; -+ -+ case PORT_VI0_VBI: -+ cgu->clk_int_port[PORT_VI0_VBI] = 0; -+ -+ if (!cgu->clk_int_port[PORT_VI0_VIDEO]) { -+ delay = 0; -+ break; -+ } -+ -+ SAA716x_EPWR(CGU, CGU_FS1_5, 0x2); /* VI 0 clk */ -+ SAA716x_EPWR(CGU, CGU_ESR_5, 0x0); /* disable divider */ -+ break; -+ -+ case PORT_VI1_VIDEO: -+ cgu->clk_int_port[PORT_VI1_VIDEO] = 0; -+ -+ if (!cgu->clk_int_port[PORT_VI1_VBI]) { -+ delay = 0; -+ break; -+ } -+ -+ SAA716x_EPWR(CGU, CGU_FS1_6, 0x3); /* VI 1 clk */ -+ SAA716x_EPWR(CGU, CGU_ESR_6, 0x0); /* disable divider */ -+ break; -+ -+ case PORT_VI1_VBI: -+ cgu->clk_int_port[PORT_VI1_VBI] = 0; -+ -+ if (!cgu->clk_int_port[PORT_VI1_VIDEO]) { -+ delay = 0; -+ break; -+ } -+ -+ SAA716x_EPWR(CGU, CGU_FS1_6, 0x3); /* VI 1 clk */ -+ SAA716x_EPWR(CGU, CGU_ESR_6, 0x0); /* disable divider */ -+ break; -+ -+ case PORT_FGPI0: -+ cgu->clk_int_port[PORT_FGPI0] = 0; -+ -+ SAA716x_EPWR(CGU, CGU_FS1_7, 0x4); /* FGPI 0 clk */ -+ SAA716x_EPWR(CGU, CGU_ESR_7, 0x0); /* disable divider */ -+ break; -+ -+ case PORT_FGPI1: -+ cgu->clk_int_port[PORT_FGPI1] = 0; -+ -+ SAA716x_EPWR(CGU, CGU_FS1_8, 0x5); /* FGPI 1 clk */ -+ SAA716x_EPWR(CGU, CGU_ESR_8, 0x0); /* disable divider */ -+ break; -+ -+ case PORT_FGPI2: -+ cgu->clk_int_port[PORT_FGPI2] = 0; -+ -+ SAA716x_EPWR(CGU, CGU_FS1_9, 0x6); /* FGPI 2 clk */ -+ SAA716x_EPWR(CGU, CGU_ESR_9, 0x0); /* disable divider */ -+ break; -+ -+ case PORT_FGPI3: -+ cgu->clk_int_port[PORT_FGPI3] = 0; -+ -+ SAA716x_EPWR(CGU, CGU_FS1_10, 0x7); /* FGPI 3 clk */ -+ SAA716x_EPWR(CGU, CGU_ESR_10, 0x0); /* disable divider */ -+ break; -+ -+ case PORT_AI0: -+ cgu->clk_int_port[PORT_AI0] = 1; -+ -+ SAA716x_EPWR(CGU, CGU_FS1_11, 0x8); /* AI 0 clk */ -+ SAA716x_EPWR(CGU, CGU_ESR_11, 0x0); /* disable divider */ -+ break; -+ -+ case PORT_AI1: -+ cgu->clk_int_port[PORT_AI1] = 1; -+ -+ SAA716x_EPWR(CGU, CGU_FS1_12, 0x9); /* AI 1 clk */ -+ SAA716x_EPWR(CGU, CGU_ESR_12, 0x0); /* disable divider */ -+ break; -+ -+ default: -+ dprintk(SAA716x_ERROR, 1, "Unknown port <%02x>", port); -+ delay = 0; -+ break; -+ -+ } -+ -+ if (delay) -+ msleep(1); -+ -+ return 0; -+} -+ -+int saa716x_get_clk(struct saa716x_dev *saa716x, -+ enum saa716x_clk_domain domain, -+ u32 *frequency) -+{ -+ struct saa716x_cgu *cgu = &saa716x->cgu; -+ -+ switch (domain) { -+ case CLK_DOMAIN_PSS: -+ case CLK_DOMAIN_DCS: -+ case CLK_DOMAIN_SPI: -+ case CLK_DOMAIN_I2C: -+ case CLK_DOMAIN_PHI: -+ case CLK_DOMAIN_VI0: -+ case CLK_DOMAIN_VI1: -+ case CLK_DOMAIN_FGPI0: -+ case CLK_DOMAIN_FGPI1: -+ case CLK_DOMAIN_FGPI2: -+ case CLK_DOMAIN_FGPI3: -+ case CLK_DOMAIN_AI0: -+ case CLK_DOMAIN_AI1: -+ case CLK_DOMAIN_PHY: -+ *frequency = cgu->clk_freq[domain]; -+ break; -+ -+ case CLK_DOMAIN_VI0VBI: -+ *frequency = cgu->clk_freq[CLK_DOMAIN_VI0]; -+ break; -+ -+ case CLK_DOMAIN_VI1VBI: -+ *frequency =cgu->clk_freq[CLK_DOMAIN_VI1]; -+ break; -+ default: -+ dprintk(SAA716x_ERROR, 1, "Error Clock domain <%02x>", domain); -+ break; -+ } -+ -+ return 0; -+} -+ -+int saa716x_set_clk(struct saa716x_dev *saa716x, -+ enum saa716x_clk_domain domain, -+ u32 frequency) -+{ -+ struct saa716x_cgu *cgu = &saa716x->cgu; -+ -+ u32 M = 1, N = 1, reset, i; -+ s8 N_tmp, M_tmp, sub, add, lsb; -+ -+ -+ if (cgu->clk_freq_min > frequency) -+ frequency = cgu->clk_freq_min; -+ -+ if (cgu->clk_freq_max < frequency) -+ frequency = cgu->clk_freq_max; -+ -+ switch (domain) { -+ case CLK_DOMAIN_PSS: -+ case CLK_DOMAIN_DCS: -+ case CLK_DOMAIN_SPI: -+ case CLK_DOMAIN_I2C: -+ case CLK_DOMAIN_PHI: -+ case CLK_DOMAIN_FGPI0: -+ case CLK_DOMAIN_FGPI1: -+ case CLK_DOMAIN_FGPI2: -+ case CLK_DOMAIN_FGPI3: -+ case CLK_DOMAIN_AI0: -+ case CLK_DOMAIN_AI1: -+ case CLK_DOMAIN_PHY: -+ -+ if (frequency == cgu->clk_freq[domain]) -+ return 0; /* same frequency */ -+ break; -+ -+ case CLK_DOMAIN_VI0: -+ -+ if (frequency == cgu->clk_vi_0[1]) { -+ return 0; -+ -+ } else if (frequency == cgu->clk_vi_0[0]) { -+ cgu->clk_vi_0[1] = frequency; /* store */ -+ -+ if (frequency == cgu->clk_vi_0[2]) -+ return 0; -+ -+ } else { -+ cgu->clk_vi_0[1] = frequency; -+ -+ if (frequency != cgu->clk_vi_0[2]) -+ return 0; -+ -+ } -+ break; -+ -+ case CLK_DOMAIN_VI1: -+ if (frequency == cgu->clk_vi_1[1]) { -+ return 0; -+ -+ } else if (frequency == cgu->clk_vi_1[0]) { -+ cgu->clk_vi_1[1] = frequency; /* store */ -+ -+ if (frequency == cgu->clk_vi_1[2]) -+ return 0; -+ -+ } else { -+ cgu->clk_vi_1[1] = frequency; -+ -+ if (frequency != cgu->clk_vi_1[2]) -+ return 0; -+ -+ } -+ break; -+ -+ case CLK_DOMAIN_VI0VBI: -+ if (frequency == cgu->clk_vi_0[2]) { -+ return 0; -+ -+ } else if (frequency == cgu->clk_vi_0[0]) { -+ cgu->clk_vi_0[2] = frequency; /* store */ -+ -+ if (frequency == cgu->clk_vi_0[1]) -+ return 0; -+ -+ } else { -+ cgu->clk_vi_0[2] = frequency; /* store */ -+ -+ if (frequency != cgu->clk_vi_0[1]) -+ return 0; -+ -+ } -+ domain = CLK_DOMAIN_VI0; /* change domain */ -+ break; -+ -+ case CLK_DOMAIN_VI1VBI: -+ if (frequency == cgu->clk_vi_1[2]) { -+ return 0; -+ -+ } else if (frequency == cgu->clk_vi_1[0]) { -+ cgu->clk_vi_1[2] = frequency; /* store */ -+ -+ if (frequency == cgu->clk_vi_1[1]) -+ return 0; -+ -+ } else { -+ cgu->clk_vi_1[2] = frequency; /* store */ -+ -+ if (frequency != cgu->clk_vi_1[1]) -+ return 0; -+ -+ } -+ domain = CLK_DOMAIN_VI1; /* change domain */ -+ break; -+ } -+ -+ /* calculate divider */ -+ do { -+ M = (N * PLL_FREQ) / frequency; -+ if (M == 0) -+ N++; -+ -+ } while (M == 0); -+ -+ /* calculate frequency */ -+ cgu->clk_freq[domain] = (N * PLL_FREQ) / M; -+ -+ N_tmp = N & 0xff; -+ M_tmp = M & 0xff; -+ sub = -N_tmp; -+ add = M_tmp - N_tmp; -+ lsb = 4; /* run */ -+ -+ if (((10 * N) / M) < 5) -+ lsb |= 1; /* stretch */ -+ -+ /* store new divider */ -+ cgu->clk_curr_div[domain] = sub & 0xff; -+ cgu->clk_curr_div[domain] <<= 8; -+ cgu->clk_curr_div[domain] = add & 0xff; -+ cgu->clk_curr_div[domain] <<= 3; -+ cgu->clk_curr_div[domain] |= lsb; -+ -+ dprintk(SAA716x_DEBUG, 1, "Domain <0x%02x> Frequency <%d> Set Freq <%d> N=%d M=%d Divider <0x%02x>", -+ domain, -+ frequency, -+ cgu->clk_freq[domain], -+ N, -+ M, -+ cgu->clk_curr_div[domain]); -+ -+ reset = 0; -+ -+ /* Reset */ -+ SAA716x_EPWR(CGU, cgu_clk[domain], cgu->clk_curr_div[domain] | 0x2); -+ -+ /* Reset disable */ -+ for (i = 0; i < 1000; i++) { -+ msleep(10); -+ reset = SAA716x_EPRD(CGU, cgu_clk[domain]); -+ -+ if (cgu->clk_curr_div[domain == reset]) -+ break; -+ } -+ -+ if (cgu->clk_curr_div[domain] != reset) -+ SAA716x_EPWR(CGU, cgu_clk[domain], cgu->clk_curr_div[domain]); -+ -+ return 0; -+} -+ -+int saa716x_cgu_init(struct saa716x_dev *saa716x) -+{ -+ struct saa716x_cgu *cgu = &saa716x->cgu; -+ -+ cgu->clk_freq_min = PLL_FREQ / 255; -+ if (PLL_FREQ > (cgu->clk_freq_min * 255)) -+ cgu->clk_freq_min++; -+ -+ cgu->clk_freq_max = PLL_FREQ; -+ -+ saa716x_getbootscript_setup(saa716x); -+ saa716x_set_clk_internal(saa716x, PORT_ALL); -+ -+ return 0; -+} -+EXPORT_SYMBOL(saa716x_cgu_init); -diff --git a/drivers/media/common/saa716x/saa716x_cgu.h b/drivers/media/common/saa716x/saa716x_cgu.h -new file mode 100644 -index 0000000..5353cf2 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_cgu.h -@@ -0,0 +1,61 @@ -+#ifndef __SAA716x_CGU_H -+#define __SAA716x_CGU_H -+ -+#define PLL_FREQ 2500 -+ -+#define SAA716x_CGU_CLKRUN(__reg) do { \ -+ SAA716x_EPWR(CGU, CGU_PCR_##__reg, CGU_PCR_RUN); /* Run */ \ -+ SAA716x_EPWR(CGU, CGU_SCR_##__reg, CGU_SCR_ENF1); /* Switch */ \ -+ SAA716x_EPWR(CGU, CGU_FS1_##__reg, 0x00000000); /* PLL Clk */ \ -+ SAA716x_EPWR(CGU, CGU_ESR_##__reg, CGU_ESR_FD_EN); /* Frac div */ \ -+} while (0) -+ -+enum saa716x_clk_domain { -+ CLK_DOMAIN_PSS = 0, -+ CLK_DOMAIN_DCS = 1, -+ CLK_DOMAIN_SPI = 2, -+ CLK_DOMAIN_I2C = 3, -+ CLK_DOMAIN_PHI = 4, -+ CLK_DOMAIN_VI0 = 5, -+ CLK_DOMAIN_VI1 = 6, -+ CLK_DOMAIN_FGPI0 = 7, -+ CLK_DOMAIN_FGPI1 = 8, -+ CLK_DOMAIN_FGPI2 = 9, -+ CLK_DOMAIN_FGPI3 = 10, -+ CLK_DOMAIN_AI0 = 11, -+ CLK_DOMAIN_AI1 = 12, -+ CLK_DOMAIN_PHY = 13, -+ CLK_DOMAIN_VI0VBI = 14, -+ CLK_DOMAIN_VI1VBI = 15 -+}; -+ -+#define PORT_VI0_VIDEO 0 -+#define PORT_VI0_VBI 2 -+#define PORT_VI1_VIDEO 3 -+#define PORT_VI1_VBI 5 -+#define PORT_FGPI0 6 -+#define PORT_FGPI1 7 -+#define PORT_FGPI2 8 -+#define PORT_FGPI3 9 -+#define PORT_AI0 10 -+#define PORT_AI1 11 -+#define PORT_ALL 12 -+ -+#define CGU_CLKS 14 -+ -+struct saa716x_cgu { -+ u8 clk_int_port[12]; -+ u32 clk_vi_0[3]; -+ u32 clk_vi_1[3]; -+ u32 clk_boot_div[CGU_CLKS]; -+ u32 clk_curr_div[CGU_CLKS]; -+ u32 clk_freq[CGU_CLKS]; -+ u32 clk_freq_min; -+ u32 clk_freq_max; -+}; -+ -+extern int saa716x_cgu_init(struct saa716x_dev *saa716x); -+extern int saa716x_set_clk_internal(struct saa716x_dev *saa716x, u32 port); -+extern int saa716x_set_clk_external(struct saa716x_dev *saa716x, u32 port); -+ -+#endif /* __SAA716x_CGU_H */ -diff --git a/drivers/media/common/saa716x/saa716x_cgu_reg.h b/drivers/media/common/saa716x/saa716x_cgu_reg.h -new file mode 100644 -index 0000000..f7d82ae ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_cgu_reg.h -@@ -0,0 +1,178 @@ -+#ifndef __SAA716x_CGU_REG_H -+#define __SAA716x_CGU_REG_H -+ -+/* -------------- CGU Registers -------------- */ -+ -+#define CGU_SCR_0 0x000 -+#define CGU_SCR_1 0x004 -+#define CGU_SCR_2 0x008 -+#define CGU_SCR_3 0x00c -+#define CGU_SCR_4 0x010 -+#define CGU_SCR_5 0x014 -+#define CGU_SCR_6 0x018 -+#define CGU_SCR_7 0x01c -+#define CGU_SCR_8 0x020 -+#define CGU_SCR_9 0x024 -+#define CGU_SCR_10 0x028 -+#define CGU_SCR_11 0x02c -+#define CGU_SCR_12 0x030 -+#define CGU_SCR_13 0x034 -+#define CGU_SCR_STOP (0x00000001 << 3) -+#define CGU_SCR_RESET (0x00000001 << 2) -+#define CGU_SCR_ENF2 (0x00000001 << 1) -+#define CGU_SCR_ENF1 (0x00000001 << 0) -+ -+#define CGU_FS1_0 0x038 -+#define CGU_FS1_1 0x03c -+#define CGU_FS1_2 0x040 -+#define CGU_FS1_3 0x044 -+#define CGU_FS1_4 0x048 -+#define CGU_FS1_5 0x04c -+#define CGU_FS1_6 0x050 -+#define CGU_FS1_7 0x054 -+#define CGU_FS1_8 0x058 -+#define CGU_FS1_9 0x05c -+#define CGU_FS1_10 0x060 -+#define CGU_FS1_11 0x064 -+#define CGU_FS1_12 0x068 -+#define CGU_FS1_13 0x06c -+#define CGU_FS1_PLL (0x00000000 << 0) -+ -+ -+#define CGU_FS2_0 0x070 -+#define CGU_FS2_1 0x074 -+#define CGU_FS2_2 0x078 -+#define CGU_FS2_3 0x07c -+#define CGU_FS2_4 0x080 -+#define CGU_FS2_5 0x084 -+#define CGU_FS2_6 0x088 -+#define CGU_FS2_7 0x08c -+#define CGU_FS2_8 0x090 -+#define CGU_FS2_9 0x094 -+#define CGU_FS2_10 0x098 -+#define CGU_FS2_11 0x09c -+#define CGU_FS2_12 0x0a0 -+#define CGU_FS2_13 0x0a4 -+ -+#define CGU_SSR_0 0x0a8 -+#define CGU_SSR_1 0x0ac -+#define CGU_SSR_2 0x0b0 -+#define CGU_SSR_3 0x0b4 -+#define CGU_SSR_4 0x0b8 -+#define CGU_SSR_5 0x0bc -+#define CGU_SSR_6 0x0c0 -+#define CGU_SSR_7 0x0c4 -+#define CGU_SSR_8 0x0c8 -+#define CGU_SSR_9 0x0cc -+#define CGU_SSR_10 0x0d0 -+#define CGU_SSR_11 0x0d4 -+#define CGU_SSR_12 0x0d8 -+#define CGU_SSR_13 0x0dc -+ -+#define CGU_PCR_0_0 0x0e0 -+#define CGU_PCR_0_1 0x0e4 -+#define CGU_PCR_0_2 0x0e8 -+#define CGU_PCR_0_3 0x0ec -+#define CGU_PCR_0_4 0x0f0 -+#define CGU_PCR_0_5 0x0f4 -+#define CGU_PCR_0_6 0x0f8 -+#define CGU_PCR_0_7 0x0fc -+#define CGU_PCR_1_0 0x100 -+#define CGU_PCR_1_1 0x104 -+#define CGU_PCR_2_0 0x108 -+#define CGU_PCR_2_1 0x10c -+#define CGU_PCR_3_0 0x110 -+#define CGU_PCR_3_1 0x114 -+#define CGU_PCR_3_2 0x118 -+#define CGU_PCR_4_0 0x11c -+#define CGU_PCR_4_1 0x120 -+#define CGU_PCR_5 0x124 -+#define CGU_PCR_6 0x128 -+#define CGU_PCR_7 0x12c -+#define CGU_PCR_8 0x130 -+#define CGU_PCR_9 0x134 -+#define CGU_PCR_10 0x138 -+#define CGU_PCR_11 0x13c -+#define CGU_PCR_12 0x140 -+#define CGU_PCR_13 0x144 -+#define CGU_PCR_WAKE_EN (0x00000001 << 2) -+#define CGU_PCR_AUTO (0x00000001 << 1) -+#define CGU_PCR_RUN (0x00000001 << 0) -+ -+ -+#define CGU_PSR_0_0 0x148 -+#define CGU_PSR_0_1 0x14c -+#define CGU_PSR_0_2 0x150 -+#define CGU_PSR_0_3 0x154 -+#define CGU_PSR_0_4 0x158 -+#define CGU_PSR_0_5 0x15c -+#define CGU_PSR_0_6 0x160 -+#define CGU_PSR_0_7 0x164 -+#define CGU_PSR_1_0 0x168 -+#define CGU_PSR_1_1 0x16c -+#define CGU_PSR_2_0 0x170 -+#define CGU_PSR_2_1 0x174 -+#define CGU_PSR_3_0 0x178 -+#define CGU_PSR_3_1 0x17c -+#define CGU_PSR_3_2 0x180 -+#define CGU_PSR_4_0 0x184 -+#define CGU_PSR_4_1 0x188 -+#define CGU_PSR_5 0x18c -+#define CGU_PSR_6 0x190 -+#define CGU_PSR_7 0x194 -+#define CGU_PSR_8 0x198 -+#define CGU_PSR_9 0x19c -+#define CGU_PSR_10 0x1a0 -+#define CGU_PSR_11 0x1a4 -+#define CGU_PSR_12 0x1a8 -+#define CGU_PSR_13 0x1ac -+ -+#define CGU_ESR_0_0 0x1b0 -+#define CGU_ESR_0_1 0x1b4 -+#define CGU_ESR_0_2 0x1b8 -+#define CGU_ESR_0_3 0x1bc -+#define CGU_ESR_0_4 0x1c0 -+#define CGU_ESR_0_5 0x1c4 -+#define CGU_ESR_0_6 0x1c8 -+#define CGU_ESR_0_7 0x1cc -+#define CGU_ESR_1_0 0x1d0 -+#define CGU_ESR_1_1 0x1d4 -+#define CGU_ESR_2_0 0x1d8 -+#define CGU_ESR_2_1 0x1dc -+#define CGU_ESR_3_0 0x1e0 -+#define CGU_ESR_3_1 0x1e4 -+#define CGU_ESR_3_2 0x1e8 -+#define CGU_ESR_4_0 0x1ec -+#define CGU_ESR_4_1 0x1f0 -+#define CGU_ESR_5 0x1f4 -+#define CGU_ESR_6 0x1f8 -+#define CGU_ESR_7 0x1fc -+#define CGU_ESR_8 0x200 -+#define CGU_ESR_9 0x204 -+#define CGU_ESR_10 0x208 -+#define CGU_ESR_11 0x20c -+#define CGU_ESR_12 0x210 -+#define CGU_ESR_13 0x214 -+#define CGU_ESR_FD_EN (0x00000001 << 0) -+ -+#define CGU_FDC_0 0x218 -+#define CGU_FDC_1 0x21c -+#define CGU_FDC_2 0x220 -+#define CGU_FDC_3 0x224 -+#define CGU_FDC_4 0x228 -+#define CGU_FDC_5 0x22c -+#define CGU_FDC_6 0x230 -+#define CGU_FDC_7 0x234 -+#define CGU_FDC_8 0x238 -+#define CGU_FDC_9 0x23c -+#define CGU_FDC_10 0x240 -+#define CGU_FDC_11 0x244 -+#define CGU_FDC_12 0x248 -+#define CGU_FDC_13 0x24c -+#define CGU_FDC_STRETCH (0x00000001 << 0) -+#define CGU_FDC_RESET (0x00000001 << 1) -+#define CGU_FDC_RUN1 (0x00000001 << 2) -+#define CGU_FDC_MADD (0x000000ff << 3) -+#define CGU_FDC_MSUB (0x000000ff << 11) -+ -+#endif /* __SAA716x_CGU_REG_H */ -diff --git a/drivers/media/common/saa716x/saa716x_dcs_reg.h b/drivers/media/common/saa716x/saa716x_dcs_reg.h -new file mode 100644 -index 0000000..26dba68 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_dcs_reg.h -@@ -0,0 +1,56 @@ -+#ifndef __SAA716x_DCS_REG_H -+#define __SAA716x_DCS_REG_H -+ -+/* -------------- DCS Registers -------------- */ -+ -+#define DCSC_CTRL 0x000 -+#define DCSC_SEL_PLLDI (0x03ffffff << 5) -+#define DCSC_TOUT_SEL (0x0000000f << 1) -+#define DCSC_TOUT_OFF (0x00000001 << 0) -+ -+#define DCSC_ADDR 0x00c -+#define DCSC_ERR_TOUT_ADDR (0x3fffffff << 2) -+ -+#define DCSC_STAT 0x010 -+#define DCSC_ERR_TOUT_GNT (0x0000001f << 24) -+#define DCSC_ERR_TOUT_SEL (0x0000007f << 10) -+#define DCSC_ERR_TOUT_READ (0x00000001 << 8) -+#define DCSC_ERR_TOUT_MASK (0x0000000f << 4) -+#define DCSC_ERR_ACK (0x00000001 << 1) -+ -+#define DCSC_FEATURES 0x040 -+#define DCSC_UNIQUE_ID (0x00000007 << 16) -+#define DCSC_SECURITY (0x00000001 << 14) -+#define DCSC_NUM_BASE_REGS (0x00000003 << 11) -+#define DCSC_NUM_TARGETS (0x0000001f << 5) -+#define DCSC_NUM_INITIATORS (0x0000001f << 0) -+ -+#define DCSC_BASE_REG0 0x100 -+#define DCSC_BASE_N_REG (0x00000fff << 20) -+ -+#define DCSC_INT_CLR_ENABLE 0xfd8 -+#define DCSC_INT_CLR_ENABLE_TOUT (0x00000001 << 1) -+#define DCSC_INT_CLR_ENABLE_ERROR (0x00000001 << 0) -+ -+#define DCSC_INT_SET_ENABLE 0xfdc -+#define DCSC_INT_SET_ENABLE_TOUT (0x00000001 << 1) -+#define DCSC_INT_SET_ENABLE_ERROR (0x00000001 << 0) -+ -+#define DCSC_INT_STATUS 0xfe0 -+#define DCSC_INT_STATUS_TOUT (0x00000001 << 1) -+#define DCSC_INT_STATUS_ERROR (0x00000001 << 0) -+ -+#define DCSC_INT_ENABLE 0xfe4 -+#define DCSC_INT_ENABLE_TOUT (0x00000001 << 1) -+#define DCSC_INT_ENABLE_ERROR (0x00000001 << 0) -+ -+#define DCSC_INT_CLR_STATUS 0xfe8 -+#define DCSC_INT_CLEAR_TOUT (0x00000001 << 1) -+#define DCSC_INT_CLEAR_ERROR (0x00000001 << 0) -+ -+#define DCSC_INT_SET_STATUS 0xfec -+#define DCSC_INT_SET_TOUT (0x00000001 << 1) -+#define DCSC_INT_SET_ERROR (0x00000001 << 0) -+ -+ -+#endif /* __SAA716x_DCS_REG_H */ -diff --git a/drivers/media/common/saa716x/saa716x_dma.c b/drivers/media/common/saa716x/saa716x_dma.c -new file mode 100644 -index 0000000..21d1dd8 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_dma.c -@@ -0,0 +1,306 @@ -+#include -+#include -+#include -+#include -+#include -+ -+#include "saa716x_dma.h" -+#include "saa716x_spi.h" -+#include "saa716x_priv.h" -+ -+/* Allocates one page of memory, which is stores the data of one -+ * 716x page table. The result gets stored in the passed DMA buffer -+ * structure. -+ */ -+static int saa716x_allocate_ptable(struct saa716x_dmabuf *dmabuf) -+{ -+ struct saa716x_dev *saa716x = dmabuf->saa716x; -+ struct pci_dev *pdev = saa716x->pdev; -+ -+ dprintk(SAA716x_DEBUG, 1, "SG Page table allocate"); -+ dmabuf->mem_ptab_virt = (void *) __get_free_page(GFP_KERNEL); -+ -+ if (dmabuf->mem_ptab_virt == NULL) { -+ dprintk(SAA716x_ERROR, 1, "ERROR: Out of pages !"); -+ return -ENOMEM; -+ } -+ -+ dmabuf->mem_ptab_phys = dma_map_single(&pdev->dev, -+ dmabuf->mem_ptab_virt, -+ SAA716x_PAGE_SIZE, -+ DMA_TO_DEVICE); -+ -+ if (dmabuf->mem_ptab_phys == 0) { -+ dprintk(SAA716x_ERROR, 1, "ERROR: map memory failed !"); -+ return -ENOMEM; -+ } -+ -+ BUG_ON(!(((unsigned long) dmabuf->mem_ptab_phys % SAA716x_PAGE_SIZE) == 0)); -+ -+ return 0; -+} -+ -+static void saa716x_free_ptable(struct saa716x_dmabuf *dmabuf) -+{ -+ struct saa716x_dev *saa716x = dmabuf->saa716x; -+ struct pci_dev *pdev = saa716x->pdev; -+ -+ BUG_ON(dmabuf == NULL); -+ dprintk(SAA716x_DEBUG, 1, "SG Page table free"); -+ -+ /* free physical PCI memory */ -+ if (dmabuf->mem_ptab_phys != 0) { -+ dma_unmap_single(&pdev->dev, -+ dmabuf->mem_ptab_phys, -+ SAA716x_PAGE_SIZE, -+ DMA_TO_DEVICE); -+ -+ dmabuf->mem_ptab_phys = 0; -+ } -+ -+ /* free kernel memory */ -+ if (dmabuf->mem_ptab_virt != NULL) { -+ free_page((unsigned long) dmabuf->mem_ptab_virt); -+ dmabuf->mem_ptab_virt = NULL; -+ } -+} -+ -+static void saa716x_dmabuf_sgfree(struct saa716x_dmabuf *dmabuf) -+{ -+ struct saa716x_dev *saa716x = dmabuf->saa716x; -+ -+ BUG_ON(dmabuf == NULL); -+ dprintk(SAA716x_DEBUG, 1, "SG free"); -+ -+ dmabuf->mem_virt = NULL; -+ if (dmabuf->mem_virt_noalign != NULL) { -+ if (dmabuf->dma_type == SAA716x_DMABUF_INT) -+ vfree(dmabuf->mem_virt_noalign); -+ -+ dmabuf->mem_virt_noalign = NULL; -+ } -+ -+ if (dmabuf->sg_list != NULL) { -+ kfree(dmabuf->sg_list); -+ dmabuf->sg_list = NULL; -+ } -+} -+ -+/* -+ * Create a SG, when an allocated buffer is passed to it, -+ * otherwise the needed memory gets allocated by itself -+ */ -+static int saa716x_dmabuf_sgalloc(struct saa716x_dmabuf *dmabuf, void *buf, int size) -+{ -+ struct saa716x_dev *saa716x = dmabuf->saa716x; -+ struct scatterlist *list; -+ struct page *pg; -+ -+ int i, pages; -+ -+ BUG_ON(!(size > 0)); -+ BUG_ON(dmabuf == NULL); -+ dprintk(SAA716x_DEBUG, 1, "SG allocate"); -+ -+ if ((size % SAA716x_PAGE_SIZE) != 0) /* calculate required pages */ -+ pages = size / SAA716x_PAGE_SIZE + 1; -+ else -+ pages = size / SAA716x_PAGE_SIZE; -+ -+ /* Allocate memory for SG list */ -+ dmabuf->sg_list = kzalloc(sizeof (struct scatterlist) * pages, GFP_KERNEL); -+ if (dmabuf->sg_list == NULL) { -+ dprintk(SAA716x_ERROR, 1, "Failed to allocate memory for scatterlist."); -+ return -ENOMEM; -+ } -+ -+ dprintk(SAA716x_DEBUG, 1, "Initializing SG table"); -+ sg_init_table(dmabuf->sg_list, pages); -+ -+ if (buf == NULL) { -+ -+ /* allocate memory, unaligned */ -+ dmabuf->mem_virt_noalign = vmalloc((pages + 1) * SAA716x_PAGE_SIZE); -+ if (dmabuf->mem_virt_noalign == NULL) { -+ dprintk(SAA716x_ERROR, 1, "Failed to allocate memory for buffer"); -+ return -ENOMEM; -+ } -+ -+ /* align memory to page */ -+ dmabuf->mem_virt = (void *) PAGE_ALIGN (((unsigned long) dmabuf->mem_virt_noalign)); -+ -+ BUG_ON(!((((unsigned long) dmabuf->mem_virt) % SAA716x_PAGE_SIZE) == 0)); -+ } else { -+ dmabuf->mem_virt = buf; -+ } -+ -+ dmabuf->list_len = pages; /* scatterlist length */ -+ list = dmabuf->sg_list; -+ -+ dprintk(SAA716x_DEBUG, 1, "Allocating SG pages"); -+ for (i = 0; i < pages; i++) { -+ if (buf == NULL) -+ pg = vmalloc_to_page(dmabuf->mem_virt + i * SAA716x_PAGE_SIZE); -+ else -+ pg = virt_to_page(dmabuf->mem_virt + i * SAA716x_PAGE_SIZE); -+ -+ BUG_ON(pg == NULL); -+ sg_set_page(&list[i], pg, SAA716x_PAGE_SIZE, 0); -+ } -+ -+ dprintk(SAA716x_DEBUG, 1, "Done!"); -+ return 0; -+} -+ -+/* Fill the "page table" page with the pointers to the specified SG buffer */ -+static void saa716x_dmabuf_sgpagefill(struct saa716x_dmabuf *dmabuf, struct scatterlist *sg_list, int pages, int offset) -+{ -+ struct saa716x_dev *saa716x = dmabuf->saa716x; -+ struct pci_dev *pdev = saa716x->pdev; -+ struct scatterlist *sg_cur; -+ -+ u32 *page; -+ int i, j, k = 0; -+ dma_addr_t addr = 0; -+ -+ BUG_ON(dmabuf == NULL); -+ BUG_ON(sg_list == NULL); -+ BUG_ON(pages == 0); -+ dprintk(SAA716x_DEBUG, 1, "SG page fill"); -+ -+ /* make page writable for the PC */ -+ dma_sync_single_for_cpu(&pdev->dev, dmabuf->mem_ptab_phys, SAA716x_PAGE_SIZE, DMA_TO_DEVICE); -+ page = dmabuf->mem_ptab_virt; -+ -+ /* create page table */ -+ for (i = 0; i < pages; i++) { -+ sg_cur = &sg_list[i]; -+ BUG_ON(!(((sg_cur->length + sg_cur->offset) % SAA716x_PAGE_SIZE) == 0)); -+ -+ if (i == 0) -+ dmabuf->offset = (sg_cur->length + sg_cur->offset) % SAA716x_PAGE_SIZE; -+ else -+ BUG_ON(sg_cur->offset != 0); -+ -+ for (j = 0; (j * SAA716x_PAGE_SIZE) < sg_dma_len(sg_cur); j++) { -+ -+ if ((offset + sg_cur->offset) >= SAA716x_PAGE_SIZE) { -+ offset -= SAA716x_PAGE_SIZE; -+ continue; -+ } -+ -+ addr = ((u64)sg_dma_address(sg_cur)) + (j * SAA716x_PAGE_SIZE) - sg_cur->offset; -+ -+ BUG_ON(addr == 0); -+ page[k * 2] = (u32 )addr; /* Low */ -+ page[k * 2 + 1] = (u32 )(((u64) addr) >> 32); /* High */ -+ BUG_ON(page[k * 2] % SAA716x_PAGE_SIZE); -+ k++; -+ } -+ } -+ -+ for (; k < (SAA716x_PAGE_SIZE / 8); k++) { -+ page[k * 2] = (u32 ) addr; -+ page[k * 2 + 1] = (u32 ) (((u64 ) addr) >> 32); -+ } -+ -+ /* make "page table" page writable for the PC */ -+ dma_sync_single_for_device(&pdev->dev, -+ dmabuf->mem_ptab_phys, -+ SAA716x_PAGE_SIZE, -+ DMA_TO_DEVICE); -+ -+} -+ -+void saa716x_dmabufsync_dev(struct saa716x_dmabuf *dmabuf) -+{ -+ struct saa716x_dev *saa716x = dmabuf->saa716x; -+ struct pci_dev *pdev = saa716x->pdev; -+ -+ dprintk(SAA716x_DEBUG, 1, "DMABUF sync DEVICE"); -+ BUG_ON(dmabuf->sg_list == NULL); -+ -+ dma_sync_sg_for_device(&pdev->dev, -+ dmabuf->sg_list, -+ dmabuf->list_len, -+ DMA_FROM_DEVICE); -+ -+} -+ -+void saa716x_dmabufsync_cpu(struct saa716x_dmabuf *dmabuf) -+{ -+ struct saa716x_dev *saa716x = dmabuf->saa716x; -+ struct pci_dev *pdev = saa716x->pdev; -+ -+ dprintk(SAA716x_DEBUG, 1, "DMABUF sync CPU"); -+ BUG_ON(dmabuf->sg_list == NULL); -+ -+ dma_sync_sg_for_cpu(&pdev->dev, -+ dmabuf->sg_list, -+ dmabuf->list_len, -+ DMA_FROM_DEVICE); -+} -+ -+/* Allocates a DMA buffer for the specified external linear buffer. */ -+int saa716x_dmabuf_alloc(struct saa716x_dev *saa716x, struct saa716x_dmabuf *dmabuf, int size) -+{ -+ struct pci_dev *pdev = saa716x->pdev; -+ -+ int ret; -+ -+ BUG_ON(saa716x == NULL); -+ BUG_ON(dmabuf == NULL); -+ BUG_ON(! (size > 0)); -+ -+ dmabuf->dma_type = SAA716x_DMABUF_INT; -+ -+ dmabuf->mem_virt_noalign = NULL; -+ dmabuf->mem_virt = NULL; -+ dmabuf->mem_ptab_phys = 0; -+ dmabuf->mem_ptab_virt = NULL; -+ -+ dmabuf->list_len = 0; -+ dmabuf->saa716x = saa716x; -+ -+ /* Allocate page table */ -+ ret = saa716x_allocate_ptable(dmabuf); -+ if (ret < 0) { -+ dprintk(SAA716x_ERROR, 1, "PT alloc failed, Out of memory"); -+ goto err1; -+ } -+ -+ /* Allocate buffer as SG */ -+ ret = saa716x_dmabuf_sgalloc(dmabuf, NULL, size); -+ if (ret < 0) { -+ dprintk(SAA716x_ERROR, 1, "SG alloc failed"); -+ goto err2; -+ } -+ -+ ret = dma_map_sg(&pdev->dev, dmabuf->sg_list, dmabuf->list_len, DMA_FROM_DEVICE); -+ if (ret < 0) { -+ dprintk(SAA716x_ERROR, 1, "SG map failed"); -+ goto err3; -+ } -+ -+ saa716x_dmabuf_sgpagefill(dmabuf, dmabuf->sg_list, ret, 0); -+ -+ return 0; -+err3: -+ saa716x_dmabuf_sgfree(dmabuf); -+err2: -+ saa716x_free_ptable(dmabuf); -+err1: -+ return ret; -+} -+ -+void saa716x_dmabuf_free(struct saa716x_dev *saa716x, struct saa716x_dmabuf *dmabuf) -+{ -+ struct pci_dev *pdev = saa716x->pdev; -+ -+ BUG_ON(saa716x == NULL); -+ BUG_ON(dmabuf == NULL); -+ -+ dma_unmap_sg(&pdev->dev, dmabuf->sg_list, dmabuf->list_len, DMA_FROM_DEVICE); -+ saa716x_dmabuf_sgfree(dmabuf); -+ saa716x_free_ptable(dmabuf); -+} -diff --git a/drivers/media/common/saa716x/saa716x_dma.h b/drivers/media/common/saa716x/saa716x_dma.h -new file mode 100644 -index 0000000..f92d667 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_dma.h -@@ -0,0 +1,38 @@ -+#ifndef __SAA716x_DMA_H -+#define __SAA716x_DMA_H -+ -+#define SAA716x_PAGE_SIZE 4096 -+ -+enum saa716x_dma_type { -+ SAA716x_DMABUF_EXT_LIN, /* Linear external */ -+ SAA716x_DMABUF_EXT_SG, /* SG external */ -+ SAA716x_DMABUF_INT /* Linear internal */ -+}; -+ -+struct saa716x_dev; -+ -+struct saa716x_dmabuf { -+ enum saa716x_dma_type dma_type; -+ -+ void *mem_virt_noalign; -+ void *mem_virt; /* page aligned */ -+ dma_addr_t mem_ptab_phys; -+ void *mem_ptab_virt; -+ void *sg_list; /* SG list */ -+ -+ struct saa716x_dev *saa716x; -+ -+ int list_len; /* buffer len */ -+ int offset; /* page offset */ -+}; -+ -+extern int saa716x_dmabuf_alloc(struct saa716x_dev *saa716x, -+ struct saa716x_dmabuf *dmabuf, -+ int size); -+extern void saa716x_dmabuf_free(struct saa716x_dev *saa716x, -+ struct saa716x_dmabuf *dmabuf); -+ -+extern void saa716x_dmabufsync_dev(struct saa716x_dmabuf *dmabuf); -+extern void saa716x_dmabufsync_cpu(struct saa716x_dmabuf *dmabuf); -+ -+#endif /* __SAA716x_DMA_H */ -diff --git a/drivers/media/common/saa716x/saa716x_dma_reg.h b/drivers/media/common/saa716x/saa716x_dma_reg.h -new file mode 100644 -index 0000000..6037ca9 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_dma_reg.h -@@ -0,0 +1,200 @@ -+#ifndef __SAA716x_DMA_REG_H -+#define __SAA716x_DMA_REG_H -+ -+/* -------------- BAM Registers -------------- */ -+ -+#define BAM_VI0_0_DMA_BUF_MODE 0x000 -+ -+#define BAM_VI0_0_ADDR_OFFST_0 0x004 -+#define BAM_VI0_0_ADDR_OFFST_1 0x008 -+#define BAM_VI0_0_ADDR_OFFST_2 0x00c -+#define BAM_VI0_0_ADDR_OFFST_3 0x010 -+#define BAM_VI0_0_ADDR_OFFST_4 0x014 -+#define BAM_VI0_0_ADDR_OFFST_5 0x018 -+#define BAM_VI0_0_ADDR_OFFST_6 0x01c -+#define BAM_VI0_0_ADDR_OFFST_7 0x020 -+ -+#define BAM_VI0_1_DMA_BUF_MODE 0x024 -+#define BAM_VI0_1_ADDR_OFFST_0 0x028 -+#define BAM_VI0_1_ADDR_OFFST_1 0x02c -+#define BAM_VI0_1_ADDR_OFFST_2 0x030 -+#define BAM_VI0_1_ADDR_OFFST_3 0x034 -+#define BAM_VI0_1_ADDR_OFFST_4 0x038 -+#define BAM_VI0_1_ADDR_OFFST_5 0x03c -+#define BAM_VI0_1_ADDR_OFFST_6 0x040 -+#define BAM_VI0_1_ADDR_OFFST_7 0x044 -+ -+#define BAM_VI0_2_DMA_BUF_MODE 0x048 -+#define BAM_VI0_2_ADDR_OFFST_0 0x04c -+#define BAM_VI0_2_ADDR_OFFST_1 0x050 -+#define BAM_VI0_2_ADDR_OFFST_2 0x054 -+#define BAM_VI0_2_ADDR_OFFST_3 0x058 -+#define BAM_VI0_2_ADDR_OFFST_4 0x05c -+#define BAM_VI0_2_ADDR_OFFST_5 0x060 -+#define BAM_VI0_2_ADDR_OFFST_6 0x064 -+#define BAM_VI0_2_ADDR_OFFST_7 0x068 -+ -+ -+#define BAM_VI1_0_DMA_BUF_MODE 0x06c -+#define BAM_VI1_0_ADDR_OFFST_0 0x070 -+#define BAM_VI1_0_ADDR_OFFST_1 0x074 -+#define BAM_VI1_0_ADDR_OFFST_2 0x078 -+#define BAM_VI1_0_ADDR_OFFST_3 0x07c -+#define BAM_VI1_0_ADDR_OFFST_4 0x080 -+#define BAM_VI1_0_ADDR_OFFST_5 0x084 -+#define BAM_VI1_0_ADDR_OFFST_6 0x088 -+#define BAM_VI1_0_ADDR_OFFST_7 0x08c -+ -+#define BAM_VI1_1_DMA_BUF_MODE 0x090 -+#define BAM_VI1_1_ADDR_OFFST_0 0x094 -+#define BAM_VI1_1_ADDR_OFFST_1 0x098 -+#define BAM_VI1_1_ADDR_OFFST_2 0x09c -+#define BAM_VI1_1_ADDR_OFFST_3 0x0a0 -+#define BAM_VI1_1_ADDR_OFFST_4 0x0a4 -+#define BAM_VI1_1_ADDR_OFFST_5 0x0a8 -+#define BAM_VI1_1_ADDR_OFFST_6 0x0ac -+#define BAM_VI1_1_ADDR_OFFST_7 0x0b0 -+ -+#define BAM_VI1_2_DMA_BUF_MODE 0x0b4 -+#define BAM_VI1_2_ADDR_OFFST_0 0x0b8 -+#define BAM_VI1_2_ADDR_OFFST_1 0x0bc -+#define BAM_VI1_2_ADDR_OFFST_2 0x0c0 -+#define BAM_VI1_2_ADDR_OFFST_3 0x0c4 -+#define BAM_VI1_2_ADDR_OFFST_4 0x0c8 -+#define BAM_VI1_2_ADDR_OFFST_5 0x0cc -+#define BAM_VI1_2_ADDR_OFFST_6 0x0d0 -+#define BAM_VI1_2_ADDR_OFFST_7 0x0d4 -+ -+ -+#define BAM_FGPI0_DMA_BUF_MODE 0x0d8 -+#define BAM_FGPI0_ADDR_OFFST_0 0x0dc -+#define BAM_FGPI0_ADDR_OFFST_1 0x0e0 -+#define BAM_FGPI0_ADDR_OFFST_2 0x0e4 -+#define BAM_FGPI0_ADDR_OFFST_3 0x0e8 -+#define BAM_FGPI0_ADDR_OFFST_4 0x0ec -+#define BAM_FGPI0_ADDR_OFFST_5 0x0f0 -+#define BAM_FGPI0_ADDR_OFFST_6 0x0f4 -+#define BAM_FGPI0_ADDR_OFFST_7 0x0f8 -+ -+#define BAM_FGPI1_DMA_BUF_MODE 0x0fc -+#define BAM_FGPI1_ADDR_OFFST_0 0x100 -+#define BAM_FGPI1_ADDR_OFFST_1 0x104 -+#define BAM_FGPI1_ADDR_OFFST_2 0x108 -+#define BAM_FGPI1_ADDR_OFFST_3 0x10c -+#define BAM_FGPI1_ADDR_OFFST_4 0x110 -+#define BAM_FGPI1_ADDR_OFFST_5 0x114 -+#define BAM_FGPI1_ADDR_OFFST_6 0x118 -+#define BAM_FGPI1_ADDR_OFFST_7 0x11c -+ -+#define BAM_FGPI2_DMA_BUF_MODE 0x120 -+#define BAM_FGPI2_ADDR_OFFST_0 0x124 -+#define BAM_FGPI2_ADDR_OFFST_1 0x128 -+#define BAM_FGPI2_ADDR_OFFST_2 0x12c -+#define BAM_FGPI2_ADDR_OFFST_3 0x130 -+#define BAM_FGPI2_ADDR_OFFST_4 0x134 -+#define BAM_FGPI2_ADDR_OFFST_5 0x138 -+#define BAM_FGPI2_ADDR_OFFST_6 0x13c -+#define BAM_FGPI2_ADDR_OFFST_7 0x140 -+ -+#define BAM_FGPI3_DMA_BUF_MODE 0x144 -+#define BAM_FGPI3_ADDR_OFFST_0 0x148 -+#define BAM_FGPI3_ADDR_OFFST_1 0x14c -+#define BAM_FGPI3_ADDR_OFFST_2 0x150 -+#define BAM_FGPI3_ADDR_OFFST_3 0x154 -+#define BAM_FGPI3_ADDR_OFFST_4 0x158 -+#define BAM_FGPI3_ADDR_OFFST_5 0x15c -+#define BAM_FGPI3_ADDR_OFFST_6 0x160 -+#define BAM_FGPI3_ADDR_OFFST_7 0x164 -+ -+ -+#define BAM_AI0_DMA_BUF_MODE 0x168 -+#define BAM_AI0_ADDR_OFFST_0 0x16c -+#define BAM_AI0_ADDR_OFFST_1 0x170 -+#define BAM_AI0_ADDR_OFFST_2 0x174 -+#define BAM_AI0_ADDR_OFFST_3 0x178 -+#define BAM_AI0_ADDR_OFFST_4 0x17c -+#define BAM_AIO_ADDR_OFFST_5 0x180 -+#define BAM_AI0_ADDR_OFFST_6 0x184 -+#define BAM_AIO_ADDR_OFFST_7 0x188 -+ -+#define BAM_AI1_DMA_BUF_MODE 0x18c -+#define BAM_AI1_ADDR_OFFST_0 0x190 -+#define BAM_AI1_ADDR_OFFST_1 0x194 -+#define BAM_AI1_ADDR_OFFST_2 0x198 -+#define BAM_AI1_ADDR_OFFST_3 0x19c -+#define BAM_AI1_ADDR_OFFST_4 0x1a0 -+#define BAM_AI1_ADDR_OFFST_5 0x1a4 -+#define BAM_AI1_ADDR_OFFST_6 0x1a8 -+#define BAM_AI1_ADDR_OFFST_7 0x1ac -+ -+#define BAM_SW_RST 0xff0 -+#define BAM_SW_RESET (0x00000001 << 0) -+ -+ -+ -+ -+ -+/* -------------- MMU Registers -------------- */ -+ -+#define MMU_MODE 0x000 -+ -+#define MMU_DMA_CONFIG0 0x004 -+#define MMU_DMA_CONFIG1 0x008 -+#define MMU_DMA_CONFIG2 0x00c -+#define MMU_DMA_CONFIG3 0x010 -+#define MMU_DMA_CONFIG4 0x014 -+#define MMU_DMA_CONFIG5 0x018 -+#define MMU_DMA_CONFIG6 0x01c -+#define MMU_DMA_CONFIG7 0x020 -+#define MMU_DMA_CONFIG8 0x024 -+#define MMU_DMA_CONFIG9 0x028 -+#define MMU_DMA_CONFIG10 0x02c -+#define MMU_DMA_CONFIG11 0x030 -+#define MMU_DMA_CONFIG12 0x034 -+#define MMU_DMA_CONFIG13 0x038 -+#define MMU_DMA_CONFIG14 0x03c -+#define MMU_DMA_CONFIG15 0x040 -+ -+#define MMU_SW_RST 0xff0 -+#define MMU_SW_RESET (0x0001 << 0) -+ -+#define MMU_PTA_BASE0 0x044 /* DMA 0 */ -+#define MMU_PTA_BASE1 0x084 /* DMA 1 */ -+#define MMU_PTA_BASE2 0x0c4 /* DMA 2 */ -+#define MMU_PTA_BASE3 0x104 /* DMA 3 */ -+#define MMU_PTA_BASE4 0x144 /* DMA 4 */ -+#define MMU_PTA_BASE5 0x184 /* DMA 5 */ -+#define MMU_PTA_BASE6 0x1c4 /* DMA 6 */ -+#define MMU_PTA_BASE7 0x204 /* DMA 7 */ -+#define MMU_PTA_BASE8 0x244 /* DMA 8 */ -+#define MMU_PTA_BASE9 0x284 /* DMA 9 */ -+#define MMU_PTA_BASE10 0x2c4 /* DMA 10 */ -+#define MMU_PTA_BASE11 0x304 /* DMA 11 */ -+#define MMU_PTA_BASE12 0x344 /* DMA 12 */ -+#define MMU_PTA_BASE13 0x384 /* DMA 13 */ -+#define MMU_PTA_BASE14 0x3c4 /* DMA 14 */ -+#define MMU_PTA_BASE15 0x404 /* DMA 15 */ -+ -+#define MMU_PTA_BASE 0x044 /* DMA 0 */ -+#define MMU_PTA_OFFSET 0x40 -+ -+#define PTA_BASE(__ch) (MMU_PTA_BASE + (MMU_PTA_OFFSET * __ch)) -+ -+#define MMU_PTA0_LSB(__ch) PTA_BASE(__ch) + 0x00 -+#define MMU_PTA0_MSB(__ch) PTA_BASE(__ch) + 0x04 -+#define MMU_PTA1_LSB(__ch) PTA_BASE(__ch) + 0x08 -+#define MMU_PTA1_MSB(__ch) PTA_BASE(__ch) + 0x0c -+#define MMU_PTA2_LSB(__ch) PTA_BASE(__ch) + 0x10 -+#define MMU_PTA2_MSB(__ch) PTA_BASE(__ch) + 0x14 -+#define MMU_PTA3_LSB(__ch) PTA_BASE(__ch) + 0x18 -+#define MMU_PTA3_MSB(__ch) PTA_BASE(__ch) + 0x1c -+#define MMU_PTA4_LSB(__ch) PTA_BASE(__ch) + 0x20 -+#define MMU_PTA4_MSB(__ch) PTA_BASE(__ch) + 0x24 -+#define MMU_PTA5_LSB(__ch) PTA_BASE(__ch) + 0x28 -+#define MMU_PTA5_MSB(__ch) PTA_BASE(__ch) + 0x2c -+#define MMU_PTA6_LSB(__ch) PTA_BASE(__ch) + 0x30 -+#define MMU_PTA6_MSB(__ch) PTA_BASE(__ch) + 0x34 -+#define MMU_PTA7_LSB(__ch) PTA_BASE(__ch) + 0x38 -+#define MMU_PTA7_MSB(__ch) PTA_BASE(__ch) + 0x3c -+ -+#endif /* __SAA716x_DMA_REG_H */ -diff --git a/drivers/media/common/saa716x/saa716x_ff.h b/drivers/media/common/saa716x/saa716x_ff.h -new file mode 100644 -index 0000000..cb65929 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_ff.h -@@ -0,0 +1,158 @@ -+#ifndef __SAA716x_FF_H -+#define __SAA716x_FF_H -+ -+#include "dvb_filter.h" -+#include "dvb_ringbuffer.h" -+ -+#define TECHNOTREND 0x13c2 -+#define S2_6400_DUAL_S2_PREMIUM_DEVEL 0x3009 -+#define S2_6400_DUAL_S2_PREMIUM_PROD 0x300A -+ -+#define TT_PREMIUM_GPIO_POWER_ENABLE 27 -+#define TT_PREMIUM_GPIO_RESET_BACKEND 26 -+#define TT_PREMIUM_GPIO_FPGA_CS1 17 -+#define TT_PREMIUM_GPIO_FPGA_CS0 16 -+#define TT_PREMIUM_GPIO_FPGA_PROGRAMN 15 -+#define TT_PREMIUM_GPIO_FPGA_DONE 14 -+#define TT_PREMIUM_GPIO_FPGA_INITN 13 -+ -+/* fpga interrupt register addresses */ -+#define FPGA_ADDR_PHI_ICTRL 0x8000 /* PHI General control of the PC => STB interrupt controller */ -+#define FPGA_ADDR_PHI_ISR 0x8010 /* PHI Interrupt Status Register */ -+#define FPGA_ADDR_PHI_ISET 0x8020 /* PHI Interrupt Set Register */ -+#define FPGA_ADDR_PHI_ICLR 0x8030 /* PHI Interrupt Clear Register */ -+#define FPGA_ADDR_EMI_ICTRL 0x8100 /* EMI General control of the STB => PC interrupt controller */ -+#define FPGA_ADDR_EMI_ISR 0x8110 /* EMI Interrupt Status Register */ -+#define FPGA_ADDR_EMI_ISET 0x8120 /* EMI Interrupt Set Register */ -+#define FPGA_ADDR_EMI_ICLR 0x8130 /* EMI Interrupt Clear Register */ -+ -+/* fpga TS router register addresses */ -+#define FPGA_ADDR_TSR_CTRL 0x8200 /* TS router control register */ -+#define FPGA_ADDR_TSR_MUX1 0x8210 /* TS multiplexer 1 selection register */ -+#define FPGA_ADDR_TSR_MUX2 0x8220 /* TS multiplexer 2 selection register */ -+#define FPGA_ADDR_TSR_MUX3 0x8230 /* TS multiplexer 3 selection register */ -+#define FPGA_ADDR_TSR_MUXCI1 0x8240 /* TS multiplexer CI 1 selection register */ -+#define FPGA_ADDR_TSR_MUXCI2 0x8250 /* TS multiplexer CI 2 selection register */ -+ -+#define FPGA_ADDR_TSR_BRFE1 0x8280 /* bit rate for TS coming from frontend 1 */ -+#define FPGA_ADDR_TSR_BRFE2 0x8284 /* bit rate for TS coming from frontend 2 */ -+#define FPGA_ADDR_TSR_BRFF1 0x828C /* bit rate for TS coming from FIFO 1 */ -+#define FPGA_ADDR_TSR_BRO1 0x8294 /* bit rate for TS going to output 1 */ -+#define FPGA_ADDR_TSR_BRO2 0x8298 /* bit rate for TS going to output 2 */ -+#define FPGA_ADDR_TSR_BRO3 0x829C /* bit rate for TS going to output 3 */ -+ -+/* fpga TS FIFO register addresses */ -+#define FPGA_ADDR_FIFO_CTRL 0x8300 /* FIFO control register */ -+#define FPGA_ADDR_FIFO_STAT 0x8310 /* FIFO status register */ -+ -+#define FPGA_ADDR_VERSION 0x80F0 /* FPGA bitstream version register */ -+ -+#define FPGA_ADDR_PIO_CTRL 0x8500 /* FPGA GPIO control register */ -+ -+#define ISR_CMD_MASK 0x0001 /* interrupt source for normal cmds (osd, fre, av, ...) */ -+#define ISR_READY_MASK 0x0002 /* interrupt source for command acknowledge */ -+#define ISR_BLOCK_MASK 0x0004 /* interrupt source for single block transfers and acknowledge */ -+#define ISR_DATA_MASK 0x0008 /* interrupt source for data transfer acknowledge */ -+#define ISR_BOOT_FINISH_MASK 0x0010 /* interrupt source for boot finish indication */ -+#define ISR_AUDIO_PTS_MASK 0x0020 /* interrupt source for audio PTS */ -+#define ISR_VIDEO_PTS_MASK 0x0040 /* interrupt source for video PTS */ -+#define ISR_CURRENT_STC_MASK 0x0080 /* interrupt source for current system clock */ -+#define ISR_REMOTE_EVENT_MASK 0x0100 /* interrupt source for remote events */ -+#define ISR_DVO_FORMAT_MASK 0x0200 /* interrupt source for DVO format change */ -+#define ISR_OSD_CMD_MASK 0x0400 /* interrupt source for OSD cmds */ -+#define ISR_OSD_READY_MASK 0x0800 /* interrupt source for OSD command acknowledge */ -+#define ISR_FE_CMD_MASK 0x1000 /* interrupt source for frontend cmds */ -+#define ISR_FE_READY_MASK 0x2000 /* interrupt source for frontend command acknowledge */ -+#define ISR_LOG_MESSAGE_MASK 0x4000 /* interrupt source for log messages */ -+#define ISR_FIFO1_EMPTY_MASK 0x8000 /* interrupt source for FIFO1 empty */ -+ -+#define ADDR_CMD_DATA 0x0000 /* address for cmd data in fpga dpram */ -+#define ADDR_OSD_CMD_DATA 0x01A0 /* address for OSD cmd data */ -+#define ADDR_FE_CMD_DATA 0x05C0 /* address for frontend cmd data */ -+#define ADDR_BLOCK_DATA 0x0600 /* address for block data */ -+#define ADDR_AUDIO_PTS 0x3E00 /* address for audio PTS (64 Bits) */ -+#define ADDR_VIDEO_PTS 0x3E08 /* address for video PTS (64 Bits) */ -+#define ADDR_CURRENT_STC 0x3E10 /* address for system clock (64 Bits) */ -+#define ADDR_DVO_FORMAT 0x3E18 /* address for DVO format 32 Bits) */ -+#define ADDR_REMOTE_EVENT 0x3F00 /* address for remote events (32 Bits) */ -+#define ADDR_LOG_MESSAGE 0x3F80 /* address for log messages */ -+ -+#define SIZE_CMD_DATA 0x01A0 /* maximum size for command data (416 Bytes) */ -+#define SIZE_OSD_CMD_DATA 0x0420 /* maximum size for OSD command data (1056 Bytes) */ -+#define SIZE_FE_CMD_DATA 0x0040 /* maximum size for frontend command data (64 Bytes) */ -+#define SIZE_BLOCK_DATA 0x3800 /* maximum size for block data (14 kB) */ -+#define SIZE_LOG_MESSAGE_DATA 0x0080 /* maximum size for log message data (128 Bytes) */ -+ -+#define SIZE_BLOCK_HEADER 8 /* block header size */ -+ -+#define MAX_RESULT_LEN 256 -+#define MAX_DATA_LEN (1024 * 1024) -+ -+#define TSOUT_LEN (1024 * TS_SIZE) -+#define TSBUF_LEN (8 * 1024) -+ -+/* place to store all the necessary device information */ -+struct sti7109_dev { -+ struct saa716x_dev *dev; -+ struct dvb_device *osd_dev; -+ struct dvb_device *video_dev; -+ struct dvb_device *audio_dev; -+ -+ void *iobuf; /* memory for all buffers */ -+ struct dvb_ringbuffer tsout; /* buffer for TS output */ -+ u8 *tsbuf; /* temp ts buffer */ -+ -+ struct tasklet_struct fifo_tasklet; -+ -+ wait_queue_head_t boot_finish_wq; -+ int boot_finished; -+ -+ wait_queue_head_t cmd_ready_wq; -+ int cmd_ready; -+ u8 cmd_data[SIZE_CMD_DATA]; -+ u32 cmd_len; -+ -+ wait_queue_head_t result_avail_wq; -+ int result_avail; -+ u8 result_data[MAX_RESULT_LEN]; -+ u32 result_len; -+ u32 result_max_len; -+ -+ wait_queue_head_t osd_cmd_ready_wq; -+ int osd_cmd_ready; -+ u8 osd_cmd_data[SIZE_OSD_CMD_DATA]; -+ u32 osd_cmd_len; -+ -+ wait_queue_head_t osd_result_avail_wq; -+ int osd_result_avail; -+ u8 osd_result_data[MAX_RESULT_LEN]; -+ u32 osd_result_len; -+ u32 osd_result_max_len; -+ -+ u16 data_handle; -+ u8 *data_buffer; /* raw data transfer buffer */ -+ wait_queue_head_t data_ready_wq; -+ int data_ready; -+ wait_queue_head_t block_done_wq; -+ int block_done; -+ -+ struct mutex cmd_lock; -+ struct mutex osd_cmd_lock; -+ struct mutex data_lock; -+ -+ u64 audio_pts; -+ u64 video_pts; -+ u64 current_stc; -+ -+ u32 int_count_enable; -+ u32 total_int_count; -+ u32 fgpi_int_count[2]; -+ u32 i2c_int_count[2]; -+ u32 ext_int_total_count; -+ u32 ext_int_source_count[16]; -+ u32 last_int_ticks; -+ -+ u16 fpga_version; -+}; -+ -+#endif /* __SAA716x_FF_H */ -diff --git a/drivers/media/common/saa716x/saa716x_ff_cmd.c b/drivers/media/common/saa716x/saa716x_ff_cmd.c -new file mode 100644 -index 0000000..81c1078 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_ff_cmd.c -@@ -0,0 +1,412 @@ -+#include -+ -+#include -+#include -+ -+#include "saa716x_phi_reg.h" -+ -+#include "saa716x_phi.h" -+#include "saa716x_spi.h" -+#include "saa716x_priv.h" -+#include "saa716x_ff.h" -+#include "saa716x_ff_cmd.h" -+ -+ -+int sti7109_cmd_init(struct sti7109_dev *sti7109) -+{ -+ mutex_init(&sti7109->cmd_lock); -+ mutex_init(&sti7109->osd_cmd_lock); -+ mutex_init(&sti7109->data_lock); -+ -+ init_waitqueue_head(&sti7109->boot_finish_wq); -+ sti7109->boot_finished = 0; -+ -+ init_waitqueue_head(&sti7109->cmd_ready_wq); -+ sti7109->cmd_ready = 0; -+ -+ init_waitqueue_head(&sti7109->result_avail_wq); -+ sti7109->result_avail = 0; -+ -+ init_waitqueue_head(&sti7109->osd_cmd_ready_wq); -+ sti7109->osd_cmd_ready = 0; -+ init_waitqueue_head(&sti7109->osd_result_avail_wq); -+ sti7109->osd_result_avail = 0; -+ -+ sti7109->data_handle = 0; -+ sti7109->data_buffer = (u8 *) (sti7109->iobuf + TSOUT_LEN + TSBUF_LEN); -+ init_waitqueue_head(&sti7109->data_ready_wq); -+ sti7109->data_ready = 0; -+ init_waitqueue_head(&sti7109->block_done_wq); -+ sti7109->block_done = 0; -+ return 0; -+} -+ -+static int sti7109_do_raw_cmd(struct sti7109_dev * sti7109) -+{ -+ struct saa716x_dev * saa716x = sti7109->dev; -+ unsigned long timeout; -+ -+ timeout = 1 * HZ; -+ timeout = wait_event_interruptible_timeout(sti7109->cmd_ready_wq, -+ sti7109->cmd_ready == 1, -+ timeout); -+ -+ if (timeout == -ERESTARTSYS || sti7109->cmd_ready == 0) { -+ if (timeout == -ERESTARTSYS) { -+ /* a signal arrived */ -+ dprintk(SAA716x_ERROR, 1, "cmd ERESTARTSYS"); -+ return -ERESTARTSYS; -+ } -+ dprintk(SAA716x_ERROR, 1, -+ "timed out waiting for command ready"); -+ return -EIO; -+ } -+ -+ sti7109->cmd_ready = 0; -+ sti7109->result_avail = 0; -+ saa716x_phi_write(saa716x, ADDR_CMD_DATA, sti7109->cmd_data, -+ sti7109->cmd_len); -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_PHI_ISET, ISR_CMD_MASK); -+ -+ if (sti7109->result_max_len > 0) { -+ timeout = 1 * HZ; -+ timeout = wait_event_interruptible_timeout( -+ sti7109->result_avail_wq, -+ sti7109->result_avail == 1, -+ timeout); -+ -+ if (timeout == -ERESTARTSYS || sti7109->result_avail == 0) { -+ sti7109->result_len = 0; -+ if (timeout == -ERESTARTSYS) { -+ /* a signal arrived */ -+ dprintk(SAA716x_ERROR, 1, "result ERESTARTSYS"); -+ return -ERESTARTSYS; -+ } -+ dprintk(SAA716x_ERROR, 1, -+ "timed out waiting for command result"); -+ return -EIO; -+ } -+ -+ if (sti7109->result_len > sti7109->result_max_len) { -+ sti7109->result_len = sti7109->result_max_len; -+ dprintk(SAA716x_NOTICE, 1, -+ "not enough space in result buffer"); -+ } -+ } -+ -+ return 0; -+} -+ -+int sti7109_raw_cmd(struct sti7109_dev * sti7109, osd_raw_cmd_t * cmd) -+{ -+ struct saa716x_dev * saa716x = sti7109->dev; -+ int err; -+ -+ if (cmd->cmd_len > SIZE_CMD_DATA) { -+ dprintk(SAA716x_ERROR, 1, "command too long"); -+ return -EFAULT; -+ } -+ -+ mutex_lock(&sti7109->cmd_lock); -+ -+ err = -EFAULT; -+ if (copy_from_user(sti7109->cmd_data, (void __user *)cmd->cmd_data, -+ cmd->cmd_len)) -+ goto out; -+ -+ sti7109->cmd_len = cmd->cmd_len; -+ sti7109->result_max_len = cmd->result_len; -+ -+ err = sti7109_do_raw_cmd(sti7109); -+ if (err) -+ goto out; -+ -+ cmd->result_len = sti7109->result_len; -+ if (sti7109->result_len > 0) { -+ if (copy_to_user((void __user *)cmd->result_data, -+ sti7109->result_data, -+ sti7109->result_len)) -+ err = -EFAULT; -+ } -+ -+out: -+ mutex_unlock(&sti7109->cmd_lock); -+ return err; -+} -+ -+static int sti7109_do_raw_osd_cmd(struct sti7109_dev * sti7109) -+{ -+ struct saa716x_dev * saa716x = sti7109->dev; -+ unsigned long timeout; -+ -+ timeout = 1 * HZ; -+ timeout = wait_event_interruptible_timeout(sti7109->osd_cmd_ready_wq, -+ sti7109->osd_cmd_ready == 1, -+ timeout); -+ -+ if (timeout == -ERESTARTSYS || sti7109->osd_cmd_ready == 0) { -+ if (timeout == -ERESTARTSYS) { -+ /* a signal arrived */ -+ dprintk(SAA716x_ERROR, 1, "osd cmd ERESTARTSYS"); -+ return -ERESTARTSYS; -+ } -+ dprintk(SAA716x_ERROR, 1, -+ "timed out waiting for osd command ready"); -+ return -EIO; -+ } -+ -+ sti7109->osd_cmd_ready = 0; -+ sti7109->osd_result_avail = 0; -+ saa716x_phi_write(saa716x, ADDR_OSD_CMD_DATA, sti7109->osd_cmd_data, -+ sti7109->osd_cmd_len); -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_PHI_ISET, ISR_OSD_CMD_MASK); -+ -+ if (sti7109->osd_result_max_len > 0) { -+ timeout = 1 * HZ; -+ timeout = wait_event_interruptible_timeout( -+ sti7109->osd_result_avail_wq, -+ sti7109->osd_result_avail == 1, -+ timeout); -+ -+ if (timeout == -ERESTARTSYS || sti7109->osd_result_avail == 0) { -+ sti7109->osd_result_len = 0; -+ if (timeout == -ERESTARTSYS) { -+ /* a signal arrived */ -+ dprintk(SAA716x_ERROR, 1, -+ "osd result ERESTARTSYS"); -+ return -ERESTARTSYS; -+ } -+ dprintk(SAA716x_ERROR, 1, -+ "timed out waiting for osd command result"); -+ return -EIO; -+ } -+ -+ if (sti7109->osd_result_len > sti7109->osd_result_max_len) { -+ sti7109->osd_result_len = sti7109->osd_result_max_len; -+ dprintk(SAA716x_NOTICE, 1, -+ "not enough space in result buffer"); -+ } -+ } -+ -+ return 0; -+} -+ -+int sti7109_raw_osd_cmd(struct sti7109_dev * sti7109, osd_raw_cmd_t * cmd) -+{ -+ struct saa716x_dev * saa716x = sti7109->dev; -+ int err; -+ -+ if (cmd->cmd_len > SIZE_OSD_CMD_DATA) { -+ dprintk(SAA716x_ERROR, 1, "command too long"); -+ return -EFAULT; -+ } -+ -+ mutex_lock(&sti7109->osd_cmd_lock); -+ -+ err = -EFAULT; -+ if (copy_from_user(sti7109->osd_cmd_data, (void __user *)cmd->cmd_data, -+ cmd->cmd_len)) -+ goto out; -+ -+ sti7109->osd_cmd_len = cmd->cmd_len; -+ sti7109->osd_result_max_len = cmd->result_len; -+ -+ err = sti7109_do_raw_osd_cmd(sti7109); -+ if (err) -+ goto out; -+ -+ cmd->result_len = sti7109->osd_result_len; -+ if (sti7109->osd_result_len > 0) { -+ if (copy_to_user((void __user *)cmd->result_data, -+ sti7109->osd_result_data, -+ sti7109->osd_result_len)) -+ err = -EFAULT; -+ } -+ -+out: -+ mutex_unlock(&sti7109->osd_cmd_lock); -+ return err; -+} -+ -+static int sti7109_do_raw_data(struct sti7109_dev * sti7109, osd_raw_data_t * data) -+{ -+ struct saa716x_dev * saa716x = sti7109->dev; -+ unsigned long timeout; -+ u16 blockSize; -+ u16 lastBlockSize; -+ u16 numBlocks; -+ u16 blockIndex; -+ u8 blockHeader[SIZE_BLOCK_HEADER]; -+ u8 * blockPtr; -+ int activeBlock; -+ -+ timeout = 1 * HZ; -+ timeout = wait_event_interruptible_timeout(sti7109->data_ready_wq, -+ sti7109->data_ready == 1, -+ timeout); -+ -+ if (timeout == -ERESTARTSYS || sti7109->data_ready == 0) { -+ if (timeout == -ERESTARTSYS) { -+ /* a signal arrived */ -+ dprintk(SAA716x_ERROR, 1, "data ERESTARTSYS"); -+ return -ERESTARTSYS; -+ } -+ dprintk(SAA716x_ERROR, 1, "timed out waiting for data ready"); -+ return -EIO; -+ } -+ -+ sti7109->data_ready = 0; -+ -+ /* -+ * 8 bytes is the size of the block header. Block header structure is: -+ * 16 bit - block index -+ * 16 bit - number of blocks -+ * 16 bit - current block data size -+ * 16 bit - block handle. This is used to reference the data in the -+ * command that uses it. -+ */ -+ blockSize = (SIZE_BLOCK_DATA / 2) - SIZE_BLOCK_HEADER; -+ numBlocks = data->data_length / blockSize; -+ lastBlockSize = data->data_length % blockSize; -+ if (lastBlockSize > 0) -+ numBlocks++; -+ -+ blockHeader[2] = (u8) (numBlocks >> 8); -+ blockHeader[3] = (u8) numBlocks; -+ blockHeader[6] = (u8) (sti7109->data_handle >> 8); -+ blockHeader[7] = (u8) sti7109->data_handle; -+ blockPtr = sti7109->data_buffer; -+ activeBlock = 0; -+ for (blockIndex = 0; blockIndex < numBlocks; blockIndex++) { -+ u32 addr; -+ -+ if (lastBlockSize && (blockIndex == (numBlocks - 1))) -+ blockSize = lastBlockSize; -+ -+ blockHeader[0] = (uint8_t) (blockIndex >> 8); -+ blockHeader[1] = (uint8_t) blockIndex; -+ blockHeader[4] = (uint8_t) (blockSize >> 8); -+ blockHeader[5] = (uint8_t) blockSize; -+ -+ addr = ADDR_BLOCK_DATA + activeBlock * (SIZE_BLOCK_DATA / 2); -+ saa716x_phi_write(saa716x, addr, blockHeader, -+ SIZE_BLOCK_HEADER); -+ saa716x_phi_write(saa716x, addr + SIZE_BLOCK_HEADER, blockPtr, -+ blockSize); -+ activeBlock = (activeBlock + 1) & 1; -+ if (blockIndex > 0) { -+ timeout = 1 * HZ; -+ timeout = wait_event_timeout(sti7109->block_done_wq, -+ sti7109->block_done == 1, -+ timeout); -+ -+ if (sti7109->block_done == 0) { -+ dprintk(SAA716x_ERROR, 1, -+ "timed out waiting for block done"); -+ return -EIO; -+ } -+ } -+ sti7109->block_done = 0; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_PHI_ISET, ISR_BLOCK_MASK); -+ blockPtr += blockSize; -+ } -+ timeout = 1 * HZ; -+ timeout = wait_event_timeout(sti7109->block_done_wq, -+ sti7109->block_done == 1, -+ timeout); -+ -+ if (sti7109->block_done == 0) { -+ dprintk(SAA716x_ERROR, 1, "timed out waiting for block done"); -+ return -EIO; -+ } -+ sti7109->block_done = 0; -+ -+ data->data_handle = sti7109->data_handle; -+ sti7109->data_handle++; -+ return 0; -+} -+ -+int sti7109_raw_data(struct sti7109_dev * sti7109, osd_raw_data_t * data) -+{ -+ struct saa716x_dev * saa716x = sti7109->dev; -+ int err; -+ -+ if (data->data_length > MAX_DATA_LEN) { -+ dprintk(SAA716x_ERROR, 1, "data too big"); -+ return -EFAULT; -+ } -+ -+ mutex_lock(&sti7109->data_lock); -+ -+ err = -EFAULT; -+ if (copy_from_user(sti7109->data_buffer, -+ (void __user *)data->data_buffer, -+ data->data_length)) -+ goto out; -+ -+ err = sti7109_do_raw_data(sti7109, data); -+ if (err) -+ goto out; -+ -+out: -+ mutex_unlock(&sti7109->data_lock); -+ return err; -+} -+ -+int sti7109_cmd_get_fw_version(struct sti7109_dev *sti7109, u32 *fw_version) -+{ -+ int ret_val = -EINVAL; -+ -+ mutex_lock(&sti7109->cmd_lock); -+ -+ sti7109->cmd_data[0] = 0x00; -+ sti7109->cmd_data[1] = 0x04; -+ sti7109->cmd_data[2] = 0x00; -+ sti7109->cmd_data[3] = 0x00; -+ sti7109->cmd_data[4] = 0x00; -+ sti7109->cmd_data[5] = 0x00; -+ sti7109->cmd_len = 6; -+ sti7109->result_max_len = MAX_RESULT_LEN; -+ -+ ret_val = sti7109_do_raw_cmd(sti7109); -+ if (ret_val == 0) { -+ *fw_version = (sti7109->result_data[6] << 16) -+ | (sti7109->result_data[7] << 8) -+ | sti7109->result_data[8]; -+ } -+ -+ mutex_unlock(&sti7109->cmd_lock); -+ -+ return ret_val; -+} -+ -+int sti7109_cmd_get_video_format(struct sti7109_dev *sti7109, video_size_t *vs) -+{ -+ int ret_val = -EINVAL; -+ -+ mutex_lock(&sti7109->cmd_lock); -+ -+ sti7109->cmd_data[0] = 0x00; -+ sti7109->cmd_data[1] = 0x05; /* command length */ -+ sti7109->cmd_data[2] = 0x00; -+ sti7109->cmd_data[3] = 0x01; /* A/V decoder command group */ -+ sti7109->cmd_data[4] = 0x00; -+ sti7109->cmd_data[5] = 0x10; /* get video format info command */ -+ sti7109->cmd_data[6] = 0x00; /* decoder index 0 */ -+ sti7109->cmd_len = 7; -+ sti7109->result_max_len = MAX_RESULT_LEN; -+ -+ ret_val = sti7109_do_raw_cmd(sti7109); -+ if (ret_val == 0) { -+ vs->w = (sti7109->result_data[7] << 8) -+ | sti7109->result_data[8]; -+ vs->h = (sti7109->result_data[9] << 8) -+ | sti7109->result_data[10]; -+ vs->aspect_ratio = sti7109->result_data[11] >> 4; -+ } -+ -+ mutex_unlock(&sti7109->cmd_lock); -+ -+ return ret_val; -+} -+ -diff --git a/drivers/media/common/saa716x/saa716x_ff_cmd.h b/drivers/media/common/saa716x/saa716x_ff_cmd.h -new file mode 100644 -index 0000000..fc79f08 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_ff_cmd.h -@@ -0,0 +1,16 @@ -+#ifndef __SAA716x_FF_CMD_H -+#define __SAA716x_FF_CMD_H -+ -+extern int sti7109_cmd_init(struct sti7109_dev *sti7109); -+extern int sti7109_raw_cmd(struct sti7109_dev * sti7109, -+ osd_raw_cmd_t * cmd); -+extern int sti7109_raw_osd_cmd(struct sti7109_dev * sti7109, -+ osd_raw_cmd_t * cmd); -+extern int sti7109_raw_data(struct sti7109_dev * sti7109, -+ osd_raw_data_t * data); -+extern int sti7109_cmd_get_fw_version(struct sti7109_dev *sti7109, -+ u32 *fw_version); -+extern int sti7109_cmd_get_video_format(struct sti7109_dev *sti7109, -+ video_size_t *vs); -+ -+#endif /* __SAA716x_FF_CMD_H */ -diff --git a/drivers/media/common/saa716x/saa716x_ff_ir.c b/drivers/media/common/saa716x/saa716x_ff_ir.c -new file mode 100644 -index 0000000..3562478 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_ff_ir.c -@@ -0,0 +1,265 @@ -+/* -+ * Driver for the remote control of the TT6400 DVB-S2 card -+ * -+ * Copyright (C) 2010 Oliver Endriss -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version 2 -+ * of the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html -+ * -+ */ -+ -+#include -+#include -+ -+#include "saa716x_spi.h" -+#include "saa716x_priv.h" -+#include "saa716x_ff.h" -+ -+ -+/* infrared remote control */ -+struct infrared { -+ u16 key_map[128]; -+ struct input_dev *input_dev; -+ char input_phys[32]; -+ struct timer_list keyup_timer; -+ struct tasklet_struct tasklet; -+ u32 command; -+ u32 device_mask; -+ u8 protocol; -+ u16 last_key; -+ u16 last_toggle; -+ bool delay_timer_finished; -+}; -+ -+#define IR_RC5 0 -+#define UP_TIMEOUT (HZ*7/25) -+ -+ -+/* key-up timer */ -+static void ir_emit_keyup(unsigned long parm) -+{ -+ struct infrared *ir = (struct infrared *) parm; -+ -+ if (!ir || !test_bit(ir->last_key, ir->input_dev->key)) -+ return; -+ -+ input_report_key(ir->input_dev, ir->last_key, 0); -+ input_sync(ir->input_dev); -+} -+ -+ -+/* tasklet */ -+static void ir_emit_key(unsigned long parm) -+{ -+ struct saa716x_dev *saa716x = (struct saa716x_dev *) parm; -+ struct infrared *ir = saa716x->ir_priv; -+ u32 ircom = ir->command; -+ u8 data; -+ u8 addr; -+ u16 toggle; -+ u16 keycode; -+ -+ /* extract device address and data */ -+ if (ircom & 0x80000000) { /* CEC remote command */ -+ addr = 0; -+ data = ircom & 0x7F; -+ toggle = 0; -+ } else { -+ switch (ir->protocol) { -+ case IR_RC5: /* extended RC5: 5 bits device address, 7 bits data */ -+ addr = (ircom >> 6) & 0x1f; -+ /* data bits 1..6 */ -+ data = ircom & 0x3f; -+ /* data bit 7 (inverted) */ -+ if (!(ircom & 0x1000)) -+ data |= 0x40; -+ toggle = ircom & 0x0800; -+ break; -+ -+ default: -+ printk(KERN_ERR "%s: invalid protocol %x\n", -+ __func__, ir->protocol); -+ return; -+ } -+ } -+ -+ input_event(ir->input_dev, EV_MSC, MSC_RAW, (addr << 16) | data); -+ input_event(ir->input_dev, EV_MSC, MSC_SCAN, data); -+ -+ keycode = ir->key_map[data]; -+ -+ dprintk(SAA716x_DEBUG, 0, -+ "%s: code %08x -> addr %i data 0x%02x -> keycode %i\n", -+ __func__, ircom, addr, data, keycode); -+ -+ /* check device address */ -+ if (!(ir->device_mask & (1 << addr))) -+ return; -+ -+ if (!keycode) { -+ printk(KERN_WARNING "%s: code %08x -> addr %i data 0x%02x -> unknown key!\n", -+ __func__, ircom, addr, data); -+ return; -+ } -+ -+ if (timer_pending(&ir->keyup_timer)) { -+ del_timer(&ir->keyup_timer); -+ if (ir->last_key != keycode || toggle != ir->last_toggle) { -+ ir->delay_timer_finished = false; -+ input_event(ir->input_dev, EV_KEY, ir->last_key, 0); -+ input_event(ir->input_dev, EV_KEY, keycode, 1); -+ input_sync(ir->input_dev); -+ } else if (ir->delay_timer_finished) { -+ input_event(ir->input_dev, EV_KEY, keycode, 2); -+ input_sync(ir->input_dev); -+ } -+ } else { -+ ir->delay_timer_finished = false; -+ input_event(ir->input_dev, EV_KEY, keycode, 1); -+ input_sync(ir->input_dev); -+ } -+ -+ ir->last_key = keycode; -+ ir->last_toggle = toggle; -+ -+ ir->keyup_timer.expires = jiffies + UP_TIMEOUT; -+ add_timer(&ir->keyup_timer); -+ -+} -+ -+ -+/* register with input layer */ -+static void ir_register_keys(struct infrared *ir) -+{ -+ int i; -+ -+ set_bit(EV_KEY, ir->input_dev->evbit); -+ set_bit(EV_REP, ir->input_dev->evbit); -+ set_bit(EV_MSC, ir->input_dev->evbit); -+ -+ set_bit(MSC_RAW, ir->input_dev->mscbit); -+ set_bit(MSC_SCAN, ir->input_dev->mscbit); -+ -+ memset(ir->input_dev->keybit, 0, sizeof(ir->input_dev->keybit)); -+ -+ for (i = 0; i < ARRAY_SIZE(ir->key_map); i++) { -+ if (ir->key_map[i] > KEY_MAX) -+ ir->key_map[i] = 0; -+ else if (ir->key_map[i] > KEY_RESERVED) -+ set_bit(ir->key_map[i], ir->input_dev->keybit); -+ } -+ -+ ir->input_dev->keycode = ir->key_map; -+ ir->input_dev->keycodesize = sizeof(ir->key_map[0]); -+ ir->input_dev->keycodemax = ARRAY_SIZE(ir->key_map); -+} -+ -+ -+/* called by the input driver after rep[REP_DELAY] ms */ -+static void ir_repeat_key(unsigned long parm) -+{ -+ struct infrared *ir = (struct infrared *) parm; -+ -+ ir->delay_timer_finished = true; -+} -+ -+ -+/* interrupt handler */ -+void saa716x_ir_handler(struct saa716x_dev *saa716x, u32 ir_cmd) -+{ -+ struct infrared *ir = saa716x->ir_priv; -+ -+ if (!ir) -+ return; -+ -+ ir->command = ir_cmd; -+ tasklet_schedule(&ir->tasklet); -+} -+ -+ -+int saa716x_ir_init(struct saa716x_dev *saa716x) -+{ -+ struct input_dev *input_dev; -+ struct infrared *ir; -+ int rc; -+ int i; -+ -+ if (!saa716x) -+ return -ENOMEM; -+ -+ ir = kzalloc(sizeof(struct infrared), GFP_KERNEL); -+ if (!ir) -+ return -ENOMEM; -+ -+ init_timer(&ir->keyup_timer); -+ ir->keyup_timer.function = ir_emit_keyup; -+ ir->keyup_timer.data = (unsigned long) ir; -+ -+ input_dev = input_allocate_device(); -+ if (!input_dev) -+ goto err; -+ -+ ir->input_dev = input_dev; -+ input_dev->name = "TT6400 DVB IR receiver"; -+ snprintf(ir->input_phys, sizeof(ir->input_phys), -+ "pci-%s/ir0", pci_name(saa716x->pdev)); -+ input_dev->phys = ir->input_phys; -+ input_dev->id.bustype = BUS_PCI; -+ input_dev->id.version = 1; -+ input_dev->id.vendor = saa716x->pdev->subsystem_vendor; -+ input_dev->id.product = saa716x->pdev->subsystem_device; -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22) -+ input_dev->dev.parent = &saa716x->pdev->dev; -+#else -+ input_dev->cdev.dev = &saa716x->pdev->dev; -+#endif -+ rc = input_register_device(input_dev); -+ if (rc) -+ goto err; -+ -+ /* TODO: fix setup/keymap */ -+ ir->protocol = IR_RC5; -+ ir->device_mask = 0xffffffff; -+ for (i = 0; i < ARRAY_SIZE(ir->key_map); i++) -+ ir->key_map[i] = i+1; -+ ir_register_keys(ir); -+ -+ /* override repeat timer */ -+ input_dev->timer.function = ir_repeat_key; -+ input_dev->timer.data = (unsigned long) ir; -+ -+ tasklet_init(&ir->tasklet, ir_emit_key, (unsigned long) saa716x); -+ saa716x->ir_priv = ir; -+ -+ return 0; -+ -+err: -+ if (ir->input_dev) -+ input_free_device(ir->input_dev); -+ kfree(ir); -+ return -ENOMEM; -+} -+ -+ -+void saa716x_ir_exit(struct saa716x_dev *saa716x) -+{ -+ struct infrared *ir = saa716x->ir_priv; -+ -+ saa716x->ir_priv = NULL; -+ tasklet_kill(&ir->tasklet); -+ del_timer_sync(&ir->keyup_timer); -+ input_unregister_device(ir->input_dev); -+ kfree(ir); -+} -diff --git a/drivers/media/common/saa716x/saa716x_ff_main.c b/drivers/media/common/saa716x/saa716x_ff_main.c -new file mode 100644 -index 0000000..34093c2 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_ff_main.c -@@ -0,0 +1,1535 @@ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#include -+#include -+#include -+ -+#include "saa716x_mod.h" -+ -+#include "saa716x_dma_reg.h" -+#include "saa716x_fgpi_reg.h" -+#include "saa716x_greg_reg.h" -+#include "saa716x_phi_reg.h" -+#include "saa716x_spi_reg.h" -+#include "saa716x_msi_reg.h" -+ -+#include "saa716x_vip.h" -+#include "saa716x_aip.h" -+#include "saa716x_msi.h" -+#include "saa716x_adap.h" -+#include "saa716x_gpio.h" -+#include "saa716x_phi.h" -+#include "saa716x_rom.h" -+#include "saa716x_spi.h" -+#include "saa716x_priv.h" -+ -+#include "saa716x_ff.h" -+#include "saa716x_ff_cmd.h" -+ -+#include "stv6110x.h" -+#include "stv090x.h" -+#include "isl6423.h" -+ -+unsigned int verbose; -+module_param(verbose, int, 0644); -+MODULE_PARM_DESC(verbose, "verbose startup messages, default is 1 (yes)"); -+ -+unsigned int int_type; -+module_param(int_type, int, 0644); -+MODULE_PARM_DESC(int_type, "force Interrupt Handler type: 0=INT-A, 1=MSI, 2=MSI-X. default INT-A mode"); -+ -+unsigned int int_count_enable; -+module_param(int_count_enable, int, 0644); -+MODULE_PARM_DESC(int_count_enable, "enable counting of interrupts"); -+ -+#define DRIVER_NAME "SAA716x FF" -+ -+static int saa716x_ff_fpga_init(struct saa716x_dev *saa716x) -+{ -+ struct sti7109_dev *sti7109 = saa716x->priv; -+ int fpgaInit; -+ int fpgaDone; -+ int rounds; -+ int ret; -+ const struct firmware *fw; -+ -+ /* request the FPGA firmware, this will block until someone uploads it */ -+ ret = request_firmware(&fw, "dvb-ttpremium-fpga-01.fw", &saa716x->pdev->dev); -+ if (ret) { -+ if (ret == -ENOENT) { -+ printk(KERN_ERR "dvb-ttpremium: could not load FPGA firmware," -+ " file not found: dvb-ttpremium-fpga-01.fw\n"); -+ printk(KERN_ERR "dvb-ttpremium: usually this should be in " -+ "/usr/lib/hotplug/firmware or /lib/firmware\n"); -+ } else -+ printk(KERN_ERR "dvb-ttpremium: cannot request firmware" -+ " (error %i)\n", ret); -+ return -EINVAL; -+ } -+ -+ /* set FPGA PROGRAMN high */ -+ saa716x_gpio_write(saa716x, TT_PREMIUM_GPIO_FPGA_PROGRAMN, 1); -+ msleep(10); -+ -+ /* set FPGA PROGRAMN low to set it into configuration mode */ -+ saa716x_gpio_write(saa716x, TT_PREMIUM_GPIO_FPGA_PROGRAMN, 0); -+ msleep(10); -+ -+ /* set FPGA PROGRAMN high to start configuration process */ -+ saa716x_gpio_write(saa716x, TT_PREMIUM_GPIO_FPGA_PROGRAMN, 1); -+ -+ rounds = 0; -+ fpgaInit = saa716x_gpio_read(saa716x, TT_PREMIUM_GPIO_FPGA_INITN); -+ while (fpgaInit == 0 && rounds < 5000) { -+ //msleep(1); -+ fpgaInit = saa716x_gpio_read(saa716x, TT_PREMIUM_GPIO_FPGA_INITN); -+ rounds++; -+ } -+ dprintk(SAA716x_INFO, 1, "SAA716x FF FPGA INITN=%d, rounds=%d", -+ fpgaInit, rounds); -+ -+ SAA716x_EPWR(SPI, SPI_CLOCK_COUNTER, 0x08); -+ SAA716x_EPWR(SPI, SPI_CONTROL_REG, SPI_MODE_SELECT); -+ -+ msleep(10); -+ -+ fpgaDone = saa716x_gpio_read(saa716x, TT_PREMIUM_GPIO_FPGA_DONE); -+ dprintk(SAA716x_INFO, 1, "SAA716x FF FPGA DONE=%d", fpgaDone); -+ dprintk(SAA716x_INFO, 1, "SAA716x FF FPGA write bitstream"); -+ saa716x_spi_write(saa716x, fw->data, fw->size); -+ dprintk(SAA716x_INFO, 1, "SAA716x FF FPGA write bitstream done"); -+ fpgaDone = saa716x_gpio_read(saa716x, TT_PREMIUM_GPIO_FPGA_DONE); -+ dprintk(SAA716x_INFO, 1, "SAA716x FF FPGA DONE=%d", fpgaDone); -+ -+ msleep(10); -+ -+ release_firmware(fw); -+ -+ if (!fpgaDone) { -+ printk(KERN_ERR "SAA716x FF FPGA is not responding, did you " -+ "connect the power supply?\n"); -+ return -EINVAL; -+ } -+ -+ sti7109->fpga_version = SAA716x_EPRD(PHI_1, FPGA_ADDR_VERSION); -+ printk(KERN_INFO "SAA716x FF FPGA version %X.%02X\n", -+ sti7109->fpga_version >> 8, sti7109->fpga_version & 0xFF); -+ -+ return 0; -+} -+ -+static int saa716x_ff_st7109_init(struct saa716x_dev *saa716x) -+{ -+ int i; -+ int length; -+ u32 requestedBlock; -+ u32 writtenBlock; -+ u32 numBlocks; -+ u32 blockSize; -+ u32 lastBlockSize; -+ u64 startTime; -+ u64 currentTime; -+ u64 waitTime; -+ int ret; -+ const struct firmware *fw; -+ u32 loaderVersion; -+ -+ /* request the st7109 loader, this will block until someone uploads it */ -+ ret = request_firmware(&fw, "dvb-ttpremium-loader-01.fw", &saa716x->pdev->dev); -+ if (ret) { -+ if (ret == -ENOENT) { -+ printk(KERN_ERR "dvb-ttpremium: could not load ST7109 loader," -+ " file not found: dvb-ttpremium-loader-01.fw\n"); -+ printk(KERN_ERR "dvb-ttpremium: usually this should be in " -+ "/usr/lib/hotplug/firmware or /lib/firmware\n"); -+ } else -+ printk(KERN_ERR "dvb-ttpremium: cannot request firmware" -+ " (error %i)\n", ret); -+ return -EINVAL; -+ } -+ loaderVersion = (fw->data[0x1385] << 8) | fw->data[0x1384]; -+ printk(KERN_INFO "SAA716x FF loader version %X.%02X\n", -+ loaderVersion >> 8, loaderVersion & 0xFF); -+ -+ saa716x_phi_write(saa716x, 0, fw->data, fw->size); -+ msleep(10); -+ -+ release_firmware(fw); -+ -+ /* take ST out of reset */ -+ saa716x_gpio_write(saa716x, TT_PREMIUM_GPIO_RESET_BACKEND, 1); -+ -+ startTime = jiffies; -+ waitTime = 0; -+ do { -+ requestedBlock = SAA716x_EPRD(PHI_1, 0x3ffc); -+ if (requestedBlock == 1) -+ break; -+ -+ currentTime = jiffies; -+ waitTime = currentTime - startTime; -+ } while (waitTime < (1 * HZ)); -+ -+ if (waitTime >= 1 * HZ) { -+ dprintk(SAA716x_ERROR, 1, "STi7109 seems to be DEAD!"); -+ return -1; -+ } -+ dprintk(SAA716x_INFO, 1, "STi7109 ready after %llu ticks", waitTime); -+ -+ /* request the st7109 firmware, this will block until someone uploads it */ -+ ret = request_firmware(&fw, "dvb-ttpremium-st7109-01.fw", &saa716x->pdev->dev); -+ if (ret) { -+ if (ret == -ENOENT) { -+ printk(KERN_ERR "dvb-ttpremium: could not load ST7109 firmware," -+ " file not found: dvb-ttpremium-st7109-01.fw\n"); -+ printk(KERN_ERR "dvb-ttpremium: usually this should be in " -+ "/usr/lib/hotplug/firmware or /lib/firmware\n"); -+ } else -+ printk(KERN_ERR "dvb-ttpremium: cannot request firmware" -+ " (error %i)\n", ret); -+ return -EINVAL; -+ } -+ -+ dprintk(SAA716x_INFO, 1, "SAA716x FF download ST7109 firmware"); -+ writtenBlock = 0; -+ blockSize = 0x3c00; -+ length = fw->size; -+ numBlocks = length / blockSize; -+ lastBlockSize = length % blockSize; -+ for (i = 0; i < length; i += blockSize) { -+ writtenBlock++; -+ /* write one block (last may differ from blockSize) */ -+ if (lastBlockSize && writtenBlock == (numBlocks + 1)) -+ saa716x_phi_write(saa716x, 0, &fw->data[i], lastBlockSize); -+ else -+ saa716x_phi_write(saa716x, 0, &fw->data[i], blockSize); -+ -+ SAA716x_EPWR(PHI_1, 0x3ff8, writtenBlock); -+ startTime = jiffies; -+ waitTime = 0; -+ do { -+ requestedBlock = SAA716x_EPRD(PHI_1, 0x3ffc); -+ if (requestedBlock == (writtenBlock + 1)) -+ break; -+ -+ currentTime = jiffies; -+ waitTime = currentTime - startTime; -+ } while (waitTime < (1 * HZ)); -+ -+ if (waitTime >= 1 * HZ) { -+ dprintk(SAA716x_ERROR, 1, "STi7109 seems to be DEAD!"); -+ release_firmware(fw); -+ return -1; -+ } -+ } -+ -+ /* disable frontend support through ST firmware */ -+ SAA716x_EPWR(PHI_1, 0x3ff4, 1); -+ -+ /* indicate end of transfer */ -+ writtenBlock++; -+ writtenBlock |= 0x80000000; -+ SAA716x_EPWR(PHI_1, 0x3ff8, writtenBlock); -+ -+ dprintk(SAA716x_INFO, 1, "SAA716x FF download ST7109 firmware done"); -+ -+ release_firmware(fw); -+ -+ return 0; -+} -+ -+static int saa716x_usercopy(struct dvb_device *dvbdev, -+ unsigned int cmd, unsigned long arg, -+ int (*func)(struct dvb_device *dvbdev, -+ unsigned int cmd, void *arg)) -+{ -+ char sbuf[128]; -+ void *mbuf = NULL; -+ void *parg = NULL; -+ int err = -EINVAL; -+ -+ /* Copy arguments into temp kernel buffer */ -+ switch (_IOC_DIR(cmd)) { -+ case _IOC_NONE: -+ /* -+ * For this command, the pointer is actually an integer -+ * argument. -+ */ -+ parg = (void *) arg; -+ break; -+ case _IOC_READ: /* some v4l ioctls are marked wrong ... */ -+ case _IOC_WRITE: -+ case (_IOC_WRITE | _IOC_READ): -+ if (_IOC_SIZE(cmd) <= sizeof(sbuf)) { -+ parg = sbuf; -+ } else { -+ /* too big to allocate from stack */ -+ mbuf = kmalloc(_IOC_SIZE(cmd),GFP_KERNEL); -+ if (NULL == mbuf) -+ return -ENOMEM; -+ parg = mbuf; -+ } -+ -+ err = -EFAULT; -+ if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd))) -+ goto out; -+ break; -+ } -+ -+ /* call driver */ -+ if ((err = func(dvbdev, cmd, parg)) == -ENOIOCTLCMD) -+ err = -EINVAL; -+ -+ if (err < 0) -+ goto out; -+ -+ /* Copy results into user buffer */ -+ switch (_IOC_DIR(cmd)) -+ { -+ case _IOC_READ: -+ case (_IOC_WRITE | _IOC_READ): -+ if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd))) -+ err = -EFAULT; -+ break; -+ } -+ -+out: -+ kfree(mbuf); -+ return err; -+} -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36) && !defined(EXPERIMENTAL_TREE) -+static int dvb_osd_ioctl(struct inode *inode, struct file *file, -+#else -+static long dvb_osd_ioctl(struct file *file, -+#endif -+ unsigned int cmd, unsigned long arg) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct sti7109_dev *sti7109 = dvbdev->priv; -+ int err = -EINVAL; -+ -+ if (!dvbdev) -+ return -ENODEV; -+ -+ if (cmd == OSD_RAW_CMD) { -+ osd_raw_cmd_t raw_cmd; -+ u8 hdr[4]; -+ -+ err = -EFAULT; -+ if (copy_from_user(&raw_cmd, (void __user *)arg, -+ _IOC_SIZE(cmd))) -+ goto out; -+ -+ if (copy_from_user(hdr, (void __user *)raw_cmd.cmd_data, 4)) -+ goto out; -+ -+ if (hdr[3] == 4) -+ err = sti7109_raw_osd_cmd(sti7109, &raw_cmd); -+ else -+ err = sti7109_raw_cmd(sti7109, &raw_cmd); -+ -+ if (err) -+ goto out; -+ -+ if (copy_to_user((void __user *)arg, &raw_cmd, _IOC_SIZE(cmd))) -+ err = -EFAULT; -+ } -+ else if (cmd == OSD_RAW_DATA) { -+ osd_raw_data_t raw_data; -+ -+ err = -EFAULT; -+ if (copy_from_user(&raw_data, (void __user *)arg, -+ _IOC_SIZE(cmd))) -+ goto out; -+ -+ err = sti7109_raw_data(sti7109, &raw_data); -+ if (err) -+ goto out; -+ -+ if (copy_to_user((void __user *)arg, &raw_data, _IOC_SIZE(cmd))) -+ err = -EFAULT; -+ } -+ -+out: -+ return err; -+} -+ -+static struct file_operations dvb_osd_fops = { -+ .owner = THIS_MODULE, -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36) && !defined(EXPERIMENTAL_TREE) -+ .ioctl = dvb_osd_ioctl, -+#else -+ .unlocked_ioctl = dvb_osd_ioctl, -+#endif -+ .open = dvb_generic_open, -+ .release = dvb_generic_release, -+}; -+ -+static struct dvb_device dvbdev_osd = { -+ .priv = NULL, -+ .users = 2, -+ .writers = 2, -+ .fops = &dvb_osd_fops, -+ .kernel_ioctl = NULL, -+}; -+ -+static int saa716x_ff_osd_exit(struct saa716x_dev *saa716x) -+{ -+ struct sti7109_dev *sti7109 = saa716x->priv; -+ -+ dvb_unregister_device(sti7109->osd_dev); -+ return 0; -+} -+ -+static int saa716x_ff_osd_init(struct saa716x_dev *saa716x) -+{ -+ struct saa716x_adapter *saa716x_adap = saa716x->saa716x_adap; -+ struct sti7109_dev *sti7109 = saa716x->priv; -+ -+ dvb_register_device(&saa716x_adap->dvb_adapter, -+ &sti7109->osd_dev, -+ &dvbdev_osd, -+ sti7109, -+ DVB_DEVICE_OSD); -+ -+ return 0; -+} -+ -+static int do_dvb_audio_ioctl(struct dvb_device *dvbdev, -+ unsigned int cmd, void *parg) -+{ -+ struct sti7109_dev *sti7109 = dvbdev->priv; -+ //struct saa716x_dev *saa716x = sti7109->dev; -+ int ret = 0; -+ -+ switch (cmd) { -+ case AUDIO_GET_PTS: -+ { -+ *(u64 *)parg = sti7109->audio_pts; -+ break; -+ } -+ default: -+ ret = -ENOIOCTLCMD; -+ break; -+ } -+ return ret; -+} -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36) && !defined(EXPERIMENTAL_TREE) -+static int dvb_audio_ioctl(struct inode *inode, struct file *file, -+#else -+static long dvb_audio_ioctl(struct file *file, -+#endif -+ unsigned int cmd, unsigned long arg) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ -+ if (!dvbdev) -+ return -ENODEV; -+ -+ return saa716x_usercopy (dvbdev, cmd, arg, do_dvb_audio_ioctl); -+} -+ -+static struct file_operations dvb_audio_fops = { -+ .owner = THIS_MODULE, -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36) && !defined(EXPERIMENTAL_TREE) -+ .ioctl = dvb_audio_ioctl, -+#else -+ .unlocked_ioctl = dvb_audio_ioctl, -+#endif -+ .open = dvb_generic_open, -+ .release = dvb_generic_release, -+}; -+ -+static struct dvb_device dvbdev_audio = { -+ .priv = NULL, -+ .users = 1, -+ .writers = 1, -+ .fops = &dvb_audio_fops, -+ .kernel_ioctl = NULL, -+}; -+ -+static int saa716x_ff_audio_exit(struct saa716x_dev *saa716x) -+{ -+ struct sti7109_dev *sti7109 = saa716x->priv; -+ -+ dvb_unregister_device(sti7109->audio_dev); -+ return 0; -+} -+ -+static int saa716x_ff_audio_init(struct saa716x_dev *saa716x) -+{ -+ struct saa716x_adapter *saa716x_adap = saa716x->saa716x_adap; -+ struct sti7109_dev *sti7109 = saa716x->priv; -+ -+ dvb_register_device(&saa716x_adap->dvb_adapter, -+ &sti7109->audio_dev, -+ &dvbdev_audio, -+ sti7109, -+ DVB_DEVICE_AUDIO); -+ -+ return 0; -+} -+ -+static void fifo_worker(unsigned long data) -+{ -+ struct saa716x_dev *saa716x = (struct saa716x_dev *) data; -+ struct sti7109_dev *sti7109 = saa716x->priv; -+ u32 fifoCtrl; -+ u32 fifoStat; -+ u16 fifoSize; -+ u16 fifoUsage; -+ u16 fifoFree; -+ int len; -+ -+ fifoCtrl = SAA716x_EPRD(PHI_1, FPGA_ADDR_FIFO_CTRL); -+ fifoStat = SAA716x_EPRD(PHI_1, FPGA_ADDR_FIFO_STAT); -+ fifoSize = (u16) (fifoStat >> 16); -+ fifoUsage = (u16) fifoStat; -+ fifoFree = fifoSize - fifoUsage; -+ spin_lock(&sti7109->tsout.lock); -+ len = dvb_ringbuffer_avail(&sti7109->tsout); -+ if (len > fifoFree) -+ len = fifoFree; -+ if (len >= TS_SIZE) -+ { -+ while (len >= TS_SIZE) -+ { -+ dvb_ringbuffer_read(&sti7109->tsout, sti7109->tsbuf, (size_t) TS_SIZE); -+ saa716x_phi_write_fifo(saa716x, sti7109->tsbuf, TS_SIZE); -+ len -= TS_SIZE; -+ } -+ wake_up(&sti7109->tsout.queue); -+ fifoCtrl |= 0x4; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_FIFO_CTRL, fifoCtrl); -+ } -+ spin_unlock(&sti7109->tsout.lock); -+} -+ -+#define FREE_COND_TS (dvb_ringbuffer_free(&sti7109->tsout) >= TS_SIZE) -+ -+static ssize_t dvb_video_write(struct file *file, const char __user *buf, -+ size_t count, loff_t *ppos) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct sti7109_dev *sti7109 = dvbdev->priv; -+ struct saa716x_dev *saa716x = sti7109->dev; -+ unsigned long todo = count; -+ -+ if ((file->f_flags & O_ACCMODE) == O_RDONLY) -+ return -EPERM; -+/* -+ if (av7110->videostate.stream_source != VIDEO_SOURCE_MEMORY) -+ return -EPERM; -+*/ -+ if ((file->f_flags & O_NONBLOCK) && !FREE_COND_TS) -+ return -EWOULDBLOCK; -+ -+ while (todo >= TS_SIZE) { -+ if (!FREE_COND_TS) { -+ if (file->f_flags & O_NONBLOCK) -+ break; -+ if (wait_event_interruptible(sti7109->tsout.queue, FREE_COND_TS)) -+ break; -+ } -+ dvb_ringbuffer_write(&sti7109->tsout, buf, TS_SIZE); -+ todo -= TS_SIZE; -+ buf += TS_SIZE; -+ } -+ -+ if (count > todo) { -+ u32 fifoCtrl; -+ -+ fifoCtrl = SAA716x_EPRD(PHI_1, FPGA_ADDR_FIFO_CTRL); -+ fifoCtrl |= 0x4; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_FIFO_CTRL, fifoCtrl); -+ } -+ -+ return count - todo; -+} -+ -+static unsigned int dvb_video_poll(struct file *file, poll_table *wait) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct sti7109_dev *sti7109 = dvbdev->priv; -+ unsigned int mask = 0; -+ -+ if ((file->f_flags & O_ACCMODE) != O_RDONLY) -+ poll_wait(file, &sti7109->tsout.queue, wait); -+ -+ if ((file->f_flags & O_ACCMODE) != O_RDONLY) { -+ if (1/*sti7109->playing*/) { -+ if (FREE_COND_TS) -+ mask |= (POLLOUT | POLLWRNORM); -+ } else /* if not playing: may play if asked for */ -+ mask |= (POLLOUT | POLLWRNORM); -+ } -+ -+ return mask; -+} -+ -+static int do_dvb_video_ioctl(struct dvb_device *dvbdev, -+ unsigned int cmd, void *parg) -+{ -+ struct sti7109_dev *sti7109 = dvbdev->priv; -+ struct saa716x_dev *saa716x = sti7109->dev; -+ int ret = 0; -+ -+ switch (cmd) { -+ case VIDEO_SELECT_SOURCE: -+ { -+ video_stream_source_t stream_source; -+ -+ stream_source = (video_stream_source_t) parg; -+ if (stream_source == VIDEO_SOURCE_DEMUX) { -+ /* stop and reset FIFO 1 */ -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_FIFO_CTRL, 1); -+ } -+ else { -+ dvb_ringbuffer_flush_spinlock_wakeup(&sti7109->tsout); -+ /* reset FIFO 1 */ -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_FIFO_CTRL, 1); -+ /* start FIFO 1 */ -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_FIFO_CTRL, 2); -+ } -+ break; -+ } -+ case VIDEO_CLEAR_BUFFER: -+ { -+ dvb_ringbuffer_flush_spinlock_wakeup(&sti7109->tsout); -+ break; -+ } -+ case VIDEO_GET_PTS: -+ { -+ *(u64 *)parg = sti7109->video_pts; -+ break; -+ } -+ case VIDEO_GET_SIZE: -+ { -+ ret = sti7109_cmd_get_video_format(sti7109, (video_size_t *) parg); -+ break; -+ } -+ default: -+ ret = -ENOIOCTLCMD; -+ break; -+ } -+ return ret; -+} -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36) && !defined(EXPERIMENTAL_TREE) -+static int dvb_video_ioctl(struct inode *inode, struct file *file, -+#else -+static long dvb_video_ioctl(struct file *file, -+#endif -+ unsigned int cmd, unsigned long arg) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ -+ if (!dvbdev) -+ return -ENODEV; -+ -+ return saa716x_usercopy (dvbdev, cmd, arg, do_dvb_video_ioctl); -+} -+ -+static struct file_operations dvb_video_fops = { -+ .owner = THIS_MODULE, -+ .write = dvb_video_write, -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 36) && !defined(EXPERIMENTAL_TREE) -+ .ioctl = dvb_video_ioctl, -+#else -+ .unlocked_ioctl = dvb_video_ioctl, -+#endif -+ .open = dvb_generic_open, -+ .release = dvb_generic_release, -+ .poll = dvb_video_poll, -+}; -+ -+static struct dvb_device dvbdev_video = { -+ .priv = NULL, -+ .users = 1, -+ .writers = 1, -+ .fops = &dvb_video_fops, -+ .kernel_ioctl = NULL, -+}; -+ -+static int saa716x_ff_video_exit(struct saa716x_dev *saa716x) -+{ -+ struct sti7109_dev *sti7109 = saa716x->priv; -+ -+ tasklet_kill(&sti7109->fifo_tasklet); -+ dvb_unregister_device(sti7109->video_dev); -+ return 0; -+} -+ -+static int saa716x_ff_video_init(struct saa716x_dev *saa716x) -+{ -+ struct saa716x_adapter *saa716x_adap = saa716x->saa716x_adap; -+ struct sti7109_dev *sti7109 = saa716x->priv; -+ -+ dvb_ringbuffer_init(&sti7109->tsout, sti7109->iobuf, TSOUT_LEN); -+ sti7109->tsbuf = (u8 *) (sti7109->iobuf + TSOUT_LEN); -+ -+ dvb_register_device(&saa716x_adap->dvb_adapter, -+ &sti7109->video_dev, -+ &dvbdev_video, -+ sti7109, -+ DVB_DEVICE_VIDEO); -+ -+ tasklet_init(&sti7109->fifo_tasklet, fifo_worker, -+ (unsigned long)saa716x); -+ -+ return 0; -+} -+ -+static int saa716x_ff_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pci_id) -+{ -+ struct saa716x_dev *saa716x; -+ struct sti7109_dev *sti7109; -+ int err = 0; -+ u32 value; -+ unsigned long timeout; -+ u32 fw_version; -+ -+ saa716x = kzalloc(sizeof (struct saa716x_dev), GFP_KERNEL); -+ if (saa716x == NULL) { -+ printk(KERN_ERR "saa716x_budget_pci_probe ERROR: out of memory\n"); -+ err = -ENOMEM; -+ goto fail0; -+ } -+ -+ saa716x->verbose = verbose; -+ saa716x->int_type = int_type; -+ saa716x->pdev = pdev; -+ saa716x->config = (struct saa716x_config *) pci_id->driver_data; -+ -+ err = saa716x_pci_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x PCI Initialization failed"); -+ goto fail1; -+ } -+ -+ err = saa716x_cgu_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x CGU Init failed"); -+ goto fail1; -+ } -+ -+ err = saa716x_core_boot(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x Core Boot failed"); -+ goto fail2; -+ } -+ dprintk(SAA716x_DEBUG, 1, "SAA716x Core Boot Success"); -+ -+ err = saa716x_msi_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x MSI Init failed"); -+ goto fail2; -+ } -+ -+ err = saa716x_jetpack_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x Jetpack core initialization failed"); -+ goto fail1; -+ } -+ -+ err = saa716x_i2c_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x I2C Initialization failed"); -+ goto fail3; -+ } -+ -+ err = saa716x_phi_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x PHI Initialization failed"); -+ goto fail3; -+ } -+ -+ saa716x_gpio_init(saa716x); -+ -+ /* prepare the sti7109 device struct */ -+ sti7109 = kzalloc(sizeof(struct sti7109_dev), GFP_KERNEL); -+ if (!sti7109) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x: out of memory"); -+ goto fail3; -+ } -+ -+ sti7109->dev = saa716x; -+ -+ sti7109->iobuf = vmalloc(TSOUT_LEN + TSBUF_LEN + MAX_DATA_LEN); -+ if (!sti7109->iobuf) -+ goto fail4; -+ -+ sti7109_cmd_init(sti7109); -+ -+ sti7109->int_count_enable = int_count_enable; -+ sti7109->total_int_count = 0; -+ memset(sti7109->fgpi_int_count, 0, sizeof(sti7109->fgpi_int_count)); -+ memset(sti7109->i2c_int_count, 0, sizeof(sti7109->i2c_int_count)); -+ sti7109->ext_int_total_count = 0; -+ memset(sti7109->ext_int_source_count, 0, sizeof(sti7109->ext_int_source_count)); -+ sti7109->last_int_ticks = jiffies; -+ -+ saa716x->priv = sti7109; -+ -+ saa716x_gpio_set_output(saa716x, TT_PREMIUM_GPIO_POWER_ENABLE); -+ saa716x_gpio_set_output(saa716x, TT_PREMIUM_GPIO_RESET_BACKEND); -+ saa716x_gpio_set_output(saa716x, TT_PREMIUM_GPIO_FPGA_CS0); -+ saa716x_gpio_set_mode(saa716x, TT_PREMIUM_GPIO_FPGA_CS0, 1); -+ saa716x_gpio_set_output(saa716x, TT_PREMIUM_GPIO_FPGA_CS1); -+ saa716x_gpio_set_mode(saa716x, TT_PREMIUM_GPIO_FPGA_CS1, 1); -+ saa716x_gpio_set_output(saa716x, TT_PREMIUM_GPIO_FPGA_PROGRAMN); -+ saa716x_gpio_set_input(saa716x, TT_PREMIUM_GPIO_FPGA_DONE); -+ saa716x_gpio_set_input(saa716x, TT_PREMIUM_GPIO_FPGA_INITN); -+ -+ /* hold ST in reset */ -+ saa716x_gpio_write(saa716x, TT_PREMIUM_GPIO_RESET_BACKEND, 0); -+ -+ /* enable board power */ -+ saa716x_gpio_write(saa716x, TT_PREMIUM_GPIO_POWER_ENABLE, 1); -+ msleep(100); -+ -+ err = saa716x_ff_fpga_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x FF FPGA Initialization failed"); -+ goto fail5; -+ } -+ -+ /* configure TS muxer */ -+ if (sti7109->fpga_version < 0x110) { -+ /* select FIFO 1 for TS mux 3 */ -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_TSR_MUX3, 4); -+ } else { -+ /* select FIFO 1 for TS mux 3 */ -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_TSR_MUX3, 1); -+ } -+ -+ /* enable interrupts from ST7109 -> PC */ -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_EMI_ICTRL, 0x3); -+ -+ value = SAA716x_EPRD(MSI, MSI_CONFIG33); -+ value &= 0xFCFFFFFF; -+ value |= MSI_INT_POL_EDGE_FALL; -+ SAA716x_EPWR(MSI, MSI_CONFIG33, value); -+ SAA716x_EPWR(MSI, MSI_INT_ENA_SET_H, MSI_INT_EXTINT_0); -+ -+ /* enable tuner reset */ -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_PIO_CTRL, 0); -+ msleep(50); -+ /* disable tuner reset */ -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_PIO_CTRL, 1); -+ -+ err = saa716x_ff_st7109_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x FF STi7109 initialization failed"); -+ goto fail5; -+ } -+ -+ err = saa716x_dump_eeprom(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x EEPROM dump failed"); -+ } -+ -+ err = saa716x_eeprom_data(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x EEPROM dump failed"); -+ } -+ -+ /* enable FGPI2 and FGPI3 for TS inputs */ -+ SAA716x_EPWR(GREG, GREG_VI_CTRL, 0x0689F04); -+ SAA716x_EPWR(GREG, GREG_FGPI_CTRL, 0x280); -+ -+ err = saa716x_dvb_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x DVB initialization failed"); -+ goto fail6; -+ } -+ -+ /* wait a maximum of 10 seconds for the STi7109 to boot */ -+ timeout = 10 * HZ; -+ timeout = wait_event_interruptible_timeout(sti7109->boot_finish_wq, -+ sti7109->boot_finished == 1, -+ timeout); -+ -+ if (timeout == -ERESTARTSYS || sti7109->boot_finished == 0) { -+ if (timeout == -ERESTARTSYS) { -+ /* a signal arrived */ -+ goto fail6; -+ } -+ dprintk(SAA716x_ERROR, 1, "timed out waiting for boot finish"); -+ err = -1; -+ goto fail6; -+ } -+ dprintk(SAA716x_INFO, 1, "STi7109 finished booting"); -+ -+ err = saa716x_ff_video_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x FF VIDEO initialization failed"); -+ goto fail7; -+ } -+ -+ err = saa716x_ff_audio_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x FF AUDIO initialization failed"); -+ goto fail8; -+ } -+ -+ err = saa716x_ff_osd_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x FF OSD initialization failed"); -+ goto fail9; -+ } -+ -+ err = sti7109_cmd_get_fw_version(sti7109, &fw_version); -+ if (!err) { -+ printk(KERN_INFO "SAA716x FF firmware version %X.%X.%X\n", -+ (fw_version >> 16) & 0xFF, (fw_version >> 8) & 0xFF, -+ fw_version & 0xFF); -+ } -+ -+ err = saa716x_ir_init(saa716x); -+ if (err) -+ goto fail9; -+ -+ return 0; -+ -+fail9: -+ saa716x_ff_osd_exit(saa716x); -+fail8: -+ saa716x_ff_audio_exit(saa716x); -+fail7: -+ saa716x_ff_video_exit(saa716x); -+fail6: -+ saa716x_dvb_exit(saa716x); -+fail5: -+ SAA716x_EPWR(MSI, MSI_INT_ENA_CLR_H, MSI_INT_EXTINT_0); -+ -+ /* disable board power */ -+ saa716x_gpio_write(saa716x, TT_PREMIUM_GPIO_POWER_ENABLE, 0); -+ -+ vfree(sti7109->iobuf); -+fail4: -+ kfree(sti7109); -+fail3: -+ saa716x_i2c_exit(saa716x); -+fail2: -+ saa716x_pci_exit(saa716x); -+fail1: -+ kfree(saa716x); -+fail0: -+ return err; -+} -+ -+static void saa716x_ff_pci_remove(struct pci_dev *pdev) -+{ -+ struct saa716x_dev *saa716x = pci_get_drvdata(pdev); -+ struct sti7109_dev *sti7109 = saa716x->priv; -+ -+ saa716x_ir_exit(saa716x); -+ -+ saa716x_ff_osd_exit(saa716x); -+ -+ saa716x_ff_audio_exit(saa716x); -+ -+ saa716x_ff_video_exit(saa716x); -+ -+ saa716x_dvb_exit(saa716x); -+ -+ SAA716x_EPWR(MSI, MSI_INT_ENA_CLR_H, MSI_INT_EXTINT_0); -+ -+ /* disable board power */ -+ saa716x_gpio_write(saa716x, TT_PREMIUM_GPIO_POWER_ENABLE, 0); -+ -+ vfree(sti7109->iobuf); -+ -+ saa716x->priv = NULL; -+ kfree(sti7109); -+ -+ saa716x_i2c_exit(saa716x); -+ saa716x_pci_exit(saa716x); -+ kfree(saa716x); -+} -+ -+static void demux_worker(unsigned long data) -+{ -+ struct saa716x_fgpi_stream_port *fgpi_entry = (struct saa716x_fgpi_stream_port *)data; -+ struct saa716x_dev *saa716x = fgpi_entry->saa716x; -+ struct dvb_demux *demux; -+ u32 fgpi_index; -+ u32 i; -+ u32 write_index; -+ -+ fgpi_index = fgpi_entry->dma_channel - 6; -+ demux = NULL; -+ for (i = 0; i < saa716x->config->adapters; i++) { -+ if (saa716x->config->adap_config[i].ts_port == fgpi_index) { -+ demux = &saa716x->saa716x_adap[i].demux; -+ break; -+ } -+ } -+ if (demux == NULL) { -+ printk(KERN_ERR "%s: unexpected channel %u\n", -+ __func__, fgpi_entry->dma_channel); -+ return; -+ } -+ -+ write_index = saa716x_fgpi_get_write_index(saa716x, fgpi_index); -+ if (write_index < 0) -+ return; -+ -+ dprintk(SAA716x_DEBUG, 1, "dma buffer = %d", write_index); -+ -+ if (write_index == fgpi_entry->read_index) { -+ printk(KERN_DEBUG "%s: called but nothing to do\n", __func__); -+ return; -+ } -+ -+ do { -+ u8 *data = (u8 *)fgpi_entry->dma_buf[fgpi_entry->read_index].mem_virt; -+ -+ pci_dma_sync_sg_for_cpu(saa716x->pdev, -+ fgpi_entry->dma_buf[fgpi_entry->read_index].sg_list, -+ fgpi_entry->dma_buf[fgpi_entry->read_index].list_len, -+ PCI_DMA_FROMDEVICE); -+ -+ dvb_dmx_swfilter(demux, data, 348 * 188); -+ -+ fgpi_entry->read_index = (fgpi_entry->read_index + 1) & 7; -+ } while (write_index != fgpi_entry->read_index); -+} -+ -+static irqreturn_t saa716x_ff_pci_irq(int irq, void *dev_id) -+{ -+ struct saa716x_dev *saa716x = (struct saa716x_dev *) dev_id; -+ struct sti7109_dev *sti7109; -+ u32 msiStatusL; -+ u32 msiStatusH; -+ u32 phiISR; -+ -+ if (unlikely(saa716x == NULL)) { -+ printk("%s: saa716x=NULL", __func__); -+ return IRQ_NONE; -+ } -+ sti7109 = saa716x->priv; -+ if (unlikely(sti7109 == NULL)) { -+ printk("%s: sti7109=NULL", __func__); -+ return IRQ_NONE; -+ } -+ if (sti7109->int_count_enable) -+ sti7109->total_int_count++; -+#if 0 -+ dprintk(SAA716x_DEBUG, 1, "VI STAT 0=<%02x> 1=<%02x>, CTL 1=<%02x> 2=<%02x>", -+ SAA716x_EPRD(VI0, INT_STATUS), -+ SAA716x_EPRD(VI1, INT_STATUS), -+ SAA716x_EPRD(VI0, INT_ENABLE), -+ SAA716x_EPRD(VI1, INT_ENABLE)); -+ -+ dprintk(SAA716x_DEBUG, 1, "FGPI STAT 0=<%02x> 1=<%02x>, CTL 1=<%02x> 2=<%02x>", -+ SAA716x_EPRD(FGPI0, INT_STATUS), -+ SAA716x_EPRD(FGPI1, INT_STATUS), -+ SAA716x_EPRD(FGPI0, INT_ENABLE), -+ SAA716x_EPRD(FGPI0, INT_ENABLE)); -+ -+ dprintk(SAA716x_DEBUG, 1, "FGPI STAT 2=<%02x> 3=<%02x>, CTL 2=<%02x> 3=<%02x>", -+ SAA716x_EPRD(FGPI2, INT_STATUS), -+ SAA716x_EPRD(FGPI3, INT_STATUS), -+ SAA716x_EPRD(FGPI2, INT_ENABLE), -+ SAA716x_EPRD(FGPI3, INT_ENABLE)); -+ -+ dprintk(SAA716x_DEBUG, 1, "AI STAT 0=<%02x> 1=<%02x>, CTL 0=<%02x> 1=<%02x>", -+ SAA716x_EPRD(AI0, AI_STATUS), -+ SAA716x_EPRD(AI1, AI_STATUS), -+ SAA716x_EPRD(AI0, AI_CTL), -+ SAA716x_EPRD(AI1, AI_CTL)); -+ -+ dprintk(SAA716x_DEBUG, 1, "MSI STAT L=<%02x> H=<%02x>, CTL L=<%02x> H=<%02x>", -+ SAA716x_EPRD(MSI, MSI_INT_STATUS_L), -+ SAA716x_EPRD(MSI, MSI_INT_STATUS_H), -+ SAA716x_EPRD(MSI, MSI_INT_ENA_L), -+ SAA716x_EPRD(MSI, MSI_INT_ENA_H)); -+ -+ dprintk(SAA716x_DEBUG, 1, "I2C STAT 0=<%02x> 1=<%02x>, CTL 0=<%02x> 1=<%02x>", -+ SAA716x_EPRD(I2C_A, INT_STATUS), -+ SAA716x_EPRD(I2C_B, INT_STATUS), -+ SAA716x_EPRD(I2C_A, INT_ENABLE), -+ SAA716x_EPRD(I2C_B, INT_ENABLE)); -+ -+ dprintk(SAA716x_DEBUG, 1, "DCS STAT=<%02x>, CTL=<%02x>", -+ SAA716x_EPRD(DCS, DCSC_INT_STATUS), -+ SAA716x_EPRD(DCS, DCSC_INT_ENABLE)); -+#endif -+ msiStatusL = SAA716x_EPRD(MSI, MSI_INT_STATUS_L); -+ SAA716x_EPWR(MSI, MSI_INT_STATUS_CLR_L, msiStatusL); -+ msiStatusH = SAA716x_EPRD(MSI, MSI_INT_STATUS_H); -+ SAA716x_EPWR(MSI, MSI_INT_STATUS_CLR_H, msiStatusH); -+ -+ if (msiStatusL) { -+ if (msiStatusL & MSI_INT_TAGACK_FGPI_2) { -+ if (sti7109->int_count_enable) -+ sti7109->fgpi_int_count[0]++; -+ tasklet_schedule(&saa716x->fgpi[2].tasklet); -+ } -+ if (msiStatusL & MSI_INT_TAGACK_FGPI_3) { -+ if (sti7109->int_count_enable) -+ sti7109->fgpi_int_count[1]++; -+ tasklet_schedule(&saa716x->fgpi[3].tasklet); -+ } -+ } -+ if (msiStatusH) { -+ //dprintk(SAA716x_INFO, 1, "msiStatusH: %08X", msiStatusH); -+ } -+ -+ if (msiStatusH & MSI_INT_I2CINT_0) { -+ if (sti7109->int_count_enable) -+ sti7109->i2c_int_count[0]++; -+ saa716x->i2c[0].i2c_op = 0; -+ wake_up(&saa716x->i2c[0].i2c_wq); -+ } -+ if (msiStatusH & MSI_INT_I2CINT_1) { -+ if (sti7109->int_count_enable) -+ sti7109->i2c_int_count[1]++; -+ saa716x->i2c[1].i2c_op = 0; -+ wake_up(&saa716x->i2c[1].i2c_wq); -+ } -+ -+ if (msiStatusH & MSI_INT_EXTINT_0) { -+ -+ phiISR = SAA716x_EPRD(PHI_1, FPGA_ADDR_EMI_ISR); -+ //dprintk(SAA716x_INFO, 1, "interrupt status register: %08X", phiISR); -+ -+ if (sti7109->int_count_enable) { -+ int i; -+ sti7109->ext_int_total_count++; -+ for (i = 0; i < 16; i++) -+ if (phiISR & (1 << i)) -+ sti7109->ext_int_source_count[i]++; -+ } -+ -+ if (phiISR & ISR_CMD_MASK) { -+ -+ u32 value; -+ u32 length; -+ /*dprintk(SAA716x_INFO, 1, "CMD interrupt source");*/ -+ -+ value = SAA716x_EPRD(PHI_1, ADDR_CMD_DATA); -+ value = __cpu_to_be32(value); -+ length = (value >> 16) + 2; -+ -+ /*dprintk(SAA716x_INFO, 1, "CMD length: %d", length);*/ -+ -+ if (length > MAX_RESULT_LEN) { -+ dprintk(SAA716x_ERROR, 1, "CMD length %d > %d", length, MAX_RESULT_LEN); -+ length = MAX_RESULT_LEN; -+ } -+ -+ saa716x_phi_read(saa716x, ADDR_CMD_DATA, sti7109->result_data, length); -+ sti7109->result_len = length; -+ sti7109->result_avail = 1; -+ wake_up(&sti7109->result_avail_wq); -+ -+ phiISR &= ~ISR_CMD_MASK; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_EMI_ICLR, ISR_CMD_MASK); -+ } -+ -+ if (phiISR & ISR_READY_MASK) { -+ /*dprintk(SAA716x_INFO, 1, "READY interrupt source");*/ -+ sti7109->cmd_ready = 1; -+ wake_up(&sti7109->cmd_ready_wq); -+ phiISR &= ~ISR_READY_MASK; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_EMI_ICLR, ISR_READY_MASK); -+ } -+ -+ if (phiISR & ISR_OSD_CMD_MASK) { -+ -+ u32 value; -+ u32 length; -+ /*dprintk(SAA716x_INFO, 1, "OSD CMD interrupt source");*/ -+ -+ value = SAA716x_EPRD(PHI_1, ADDR_OSD_CMD_DATA); -+ value = __cpu_to_be32(value); -+ length = (value >> 16) + 2; -+ -+ /*dprintk(SAA716x_INFO, 1, "OSD CMD length: %d", length);*/ -+ -+ if (length > MAX_RESULT_LEN) { -+ dprintk(SAA716x_ERROR, 1, "OSD CMD length %d > %d", length, MAX_RESULT_LEN); -+ length = MAX_RESULT_LEN; -+ } -+ -+ saa716x_phi_read(saa716x, ADDR_OSD_CMD_DATA, sti7109->osd_result_data, length); -+ sti7109->osd_result_len = length; -+ sti7109->osd_result_avail = 1; -+ wake_up(&sti7109->osd_result_avail_wq); -+ -+ phiISR &= ~ISR_OSD_CMD_MASK; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_EMI_ICLR, ISR_OSD_CMD_MASK); -+ } -+ -+ if (phiISR & ISR_OSD_READY_MASK) { -+ /*dprintk(SAA716x_INFO, 1, "OSD_READY interrupt source");*/ -+ sti7109->osd_cmd_ready = 1; -+ wake_up(&sti7109->osd_cmd_ready_wq); -+ phiISR &= ~ISR_OSD_READY_MASK; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_EMI_ICLR, ISR_OSD_READY_MASK); -+ } -+ -+ if (phiISR & ISR_BLOCK_MASK) { -+ /*dprintk(SAA716x_INFO, 1, "BLOCK interrupt source");*/ -+ sti7109->block_done = 1; -+ wake_up(&sti7109->block_done_wq); -+ phiISR &= ~ISR_BLOCK_MASK; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_EMI_ICLR, ISR_BLOCK_MASK); -+ } -+ -+ if (phiISR & ISR_DATA_MASK) { -+ /*dprintk(SAA716x_INFO, 1, "DATA interrupt source");*/ -+ sti7109->data_ready = 1; -+ wake_up(&sti7109->data_ready_wq); -+ phiISR &= ~ISR_DATA_MASK; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_EMI_ICLR, ISR_DATA_MASK); -+ } -+ -+ if (phiISR & ISR_BOOT_FINISH_MASK) { -+ /*dprintk(SAA716x_INFO, 1, "BOOT FINISH interrupt source");*/ -+ sti7109->boot_finished = 1; -+ wake_up(&sti7109->boot_finish_wq); -+ phiISR &= ~ISR_BOOT_FINISH_MASK; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_EMI_ICLR, ISR_BOOT_FINISH_MASK); -+ } -+ -+ if (phiISR & ISR_AUDIO_PTS_MASK) { -+ u8 data[8]; -+ -+ saa716x_phi_read(saa716x, ADDR_AUDIO_PTS, data, 8); -+ sti7109->audio_pts = (((u64) data[3] & 0x01) << 32) -+ | ((u64) data[4] << 24) -+ | ((u64) data[5] << 16) -+ | ((u64) data[6] << 8) -+ | ((u64) data[7]); -+ -+ phiISR &= ~ISR_AUDIO_PTS_MASK; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_EMI_ICLR, ISR_AUDIO_PTS_MASK); -+ -+ /*dprintk(SAA716x_INFO, 1, "AUDIO PTS: %llX", sti7109->audio_pts);*/ -+ } -+ -+ if (phiISR & ISR_VIDEO_PTS_MASK) { -+ u8 data[8]; -+ -+ saa716x_phi_read(saa716x, ADDR_VIDEO_PTS, data, 8); -+ sti7109->video_pts = (((u64) data[3] & 0x01) << 32) -+ | ((u64) data[4] << 24) -+ | ((u64) data[5] << 16) -+ | ((u64) data[6] << 8) -+ | ((u64) data[7]); -+ -+ phiISR &= ~ISR_VIDEO_PTS_MASK; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_EMI_ICLR, ISR_VIDEO_PTS_MASK); -+ -+ /*dprintk(SAA716x_INFO, 1, "VIDEO PTS: %llX", sti7109->video_pts);*/ -+ } -+ -+ if (phiISR & ISR_CURRENT_STC_MASK) { -+ u8 data[8]; -+ -+ saa716x_phi_read(saa716x, ADDR_CURRENT_STC, data, 8); -+ sti7109->current_stc = (((u64) data[3] & 0x01) << 32) -+ | ((u64) data[4] << 24) -+ | ((u64) data[5] << 16) -+ | ((u64) data[6] << 8) -+ | ((u64) data[7]); -+ -+ phiISR &= ~ISR_CURRENT_STC_MASK; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_EMI_ICLR, ISR_CURRENT_STC_MASK); -+ -+ /*dprintk(SAA716x_INFO, 1, "CURRENT STC: %llu", sti7109->current_stc);*/ -+ } -+ -+ if (phiISR & ISR_REMOTE_EVENT_MASK) { -+ u8 data[4]; -+ u32 remote_event; -+ -+ saa716x_phi_read(saa716x, ADDR_REMOTE_EVENT, data, 4); -+ remote_event = (data[3] << 24) -+ | (data[2] << 16) -+ | (data[1] << 8) -+ | (data[0]); -+ memset(data, 0, sizeof(data)); -+ saa716x_phi_write(saa716x, ADDR_REMOTE_EVENT, data, 4); -+ -+ phiISR &= ~ISR_REMOTE_EVENT_MASK; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_EMI_ICLR, ISR_REMOTE_EVENT_MASK); -+ -+ if (remote_event == 0) { -+ dprintk(SAA716x_ERROR, 1, "REMOTE EVENT: %X ignored", remote_event); -+ } else { -+ dprintk(SAA716x_INFO, 1, "REMOTE EVENT: %X", remote_event); -+ saa716x_ir_handler(saa716x, remote_event); -+ } -+ } -+ -+ if (phiISR & ISR_DVO_FORMAT_MASK) { -+ u8 data[4]; -+ u32 format; -+ -+ saa716x_phi_read(saa716x, ADDR_DVO_FORMAT, data, 4); -+ format = (data[0] << 24) -+ | (data[1] << 16) -+ | (data[2] << 8) -+ | (data[3]); -+ -+ phiISR &= ~ISR_DVO_FORMAT_MASK; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_EMI_ICLR, ISR_DVO_FORMAT_MASK); -+ -+ dprintk(SAA716x_INFO, 1, "DVO FORMAT CHANGE: %u", format); -+ } -+ -+ if (phiISR & ISR_LOG_MESSAGE_MASK) { -+ char message[SIZE_LOG_MESSAGE_DATA]; -+ -+ saa716x_phi_read(saa716x, ADDR_LOG_MESSAGE, message, -+ SIZE_LOG_MESSAGE_DATA); -+ -+ phiISR &= ~ISR_LOG_MESSAGE_MASK; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_EMI_ICLR, ISR_LOG_MESSAGE_MASK); -+ -+ dprintk(SAA716x_INFO, 1, "LOG MESSAGE: %.*s", -+ SIZE_LOG_MESSAGE_DATA, message); -+ } -+ -+ if (phiISR & ISR_FIFO1_EMPTY_MASK) { -+ u32 fifoCtrl; -+ -+ /*dprintk(SAA716x_INFO, 1, "FIFO EMPTY interrupt source");*/ -+ fifoCtrl = SAA716x_EPRD(PHI_1, FPGA_ADDR_FIFO_CTRL); -+ fifoCtrl &= ~0x4; -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_FIFO_CTRL, fifoCtrl); -+ tasklet_schedule(&sti7109->fifo_tasklet); -+ phiISR &= ~ISR_FIFO1_EMPTY_MASK; -+ } -+ -+ if (phiISR) { -+ dprintk(SAA716x_INFO, 1, "unknown interrupt source"); -+ SAA716x_EPWR(PHI_1, FPGA_ADDR_EMI_ICLR, phiISR); -+ } -+ } -+ -+ if (sti7109->int_count_enable) { -+ if (jiffies - sti7109->last_int_ticks >= HZ) { -+ dprintk(SAA716x_INFO, 1, "int count: t: %d, f:%d %d, i:%d %d," -+ "e: %d (%d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d)", -+ sti7109->total_int_count, -+ sti7109->fgpi_int_count[0], -+ sti7109->fgpi_int_count[1], -+ sti7109->i2c_int_count[0], -+ sti7109->i2c_int_count[1], -+ sti7109->ext_int_total_count, -+ sti7109->ext_int_source_count[0], -+ sti7109->ext_int_source_count[1], -+ sti7109->ext_int_source_count[2], -+ sti7109->ext_int_source_count[3], -+ sti7109->ext_int_source_count[4], -+ sti7109->ext_int_source_count[5], -+ sti7109->ext_int_source_count[6], -+ sti7109->ext_int_source_count[7], -+ sti7109->ext_int_source_count[8], -+ sti7109->ext_int_source_count[9], -+ sti7109->ext_int_source_count[10], -+ sti7109->ext_int_source_count[11], -+ sti7109->ext_int_source_count[12], -+ sti7109->ext_int_source_count[13], -+ sti7109->ext_int_source_count[14], -+ sti7109->ext_int_source_count[15]); -+ sti7109->total_int_count = 0; -+ memset(sti7109->fgpi_int_count, 0, sizeof(sti7109->fgpi_int_count)); -+ memset(sti7109->i2c_int_count, 0, sizeof(sti7109->i2c_int_count)); -+ sti7109->ext_int_total_count = 0; -+ memset(sti7109->ext_int_source_count, 0, sizeof(sti7109->ext_int_source_count)); -+ sti7109->last_int_ticks = jiffies; -+ } -+ } -+ return IRQ_HANDLED; -+} -+ -+#define SAA716x_MODEL_S2_6400_DUAL "Technotrend S2 6400 Dual S2 Premium" -+#define SAA716x_DEV_S2_6400_DUAL "2x DVB-S/S2 + Hardware decode" -+ -+static struct stv090x_config tt6400_stv090x_config = { -+ .device = STV0900, -+ .demod_mode = STV090x_DUAL, -+ .clk_mode = STV090x_CLK_EXT, -+ -+ .xtal = 13500000, -+ .address = 0x68, -+ -+ .ts1_mode = STV090x_TSMODE_SERIAL_CONTINUOUS, -+ .ts2_mode = STV090x_TSMODE_SERIAL_CONTINUOUS, -+ .ts1_clk = 135000000, -+ .ts2_clk = 135000000, -+ -+ .repeater_level = STV090x_RPTLEVEL_16, -+ -+ .tuner_init = NULL, -+ .tuner_set_mode = NULL, -+ .tuner_set_frequency = NULL, -+ .tuner_get_frequency = NULL, -+ .tuner_set_bandwidth = NULL, -+ .tuner_get_bandwidth = NULL, -+ .tuner_set_bbgain = NULL, -+ .tuner_get_bbgain = NULL, -+ .tuner_set_refclk = NULL, -+ .tuner_get_status = NULL, -+}; -+ -+static struct stv6110x_config tt6400_stv6110x_config = { -+ .addr = 0x60, -+ .refclk = 27000000, -+ .clk_div = 2, -+}; -+ -+static struct isl6423_config tt6400_isl6423_config[2] = { -+ { -+ .current_max = SEC_CURRENT_515m, -+ .curlim = SEC_CURRENT_LIM_ON, -+ .mod_extern = 1, -+ .addr = 0x09, -+ }, -+ { -+ .current_max = SEC_CURRENT_515m, -+ .curlim = SEC_CURRENT_LIM_ON, -+ .mod_extern = 1, -+ .addr = 0x08, -+ } -+}; -+ -+ -+static int saa716x_s26400_frontend_attach(struct saa716x_adapter *adapter, int count) -+{ -+ struct saa716x_dev *saa716x = adapter->saa716x; -+ struct saa716x_i2c *i2c = saa716x->i2c; -+ struct i2c_adapter *i2c_adapter = &i2c[SAA716x_I2C_BUS_A].i2c_adapter; -+ -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) SAA716x frontend Init", count); -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) Device ID=%02x", count, saa716x->pdev->subsystem_device); -+ -+ if (count == 0 || count == 1) { -+ adapter->fe = dvb_attach(stv090x_attach, -+ &tt6400_stv090x_config, -+ i2c_adapter, -+ STV090x_DEMODULATOR_0 + count); -+ -+ if (adapter->fe) { -+ struct stv6110x_devctl *ctl; -+ ctl = dvb_attach(stv6110x_attach, -+ adapter->fe, -+ &tt6400_stv6110x_config, -+ i2c_adapter); -+ -+ tt6400_stv090x_config.tuner_init = ctl->tuner_init; -+ tt6400_stv090x_config.tuner_sleep = ctl->tuner_sleep; -+ tt6400_stv090x_config.tuner_set_mode = ctl->tuner_set_mode; -+ tt6400_stv090x_config.tuner_set_frequency = ctl->tuner_set_frequency; -+ tt6400_stv090x_config.tuner_get_frequency = ctl->tuner_get_frequency; -+ tt6400_stv090x_config.tuner_set_bandwidth = ctl->tuner_set_bandwidth; -+ tt6400_stv090x_config.tuner_get_bandwidth = ctl->tuner_get_bandwidth; -+ tt6400_stv090x_config.tuner_set_bbgain = ctl->tuner_set_bbgain; -+ tt6400_stv090x_config.tuner_get_bbgain = ctl->tuner_get_bbgain; -+ tt6400_stv090x_config.tuner_set_refclk = ctl->tuner_set_refclk; -+ tt6400_stv090x_config.tuner_get_status = ctl->tuner_get_status; -+ -+ if (count == 1) { -+ /* call the init function once to initialize -+ tuner's clock output divider and demod's -+ master clock */ -+ /* The second tuner drives the STV0900 so -+ call it only for adapter 1 */ -+ if (adapter->fe->ops.init) -+ adapter->fe->ops.init(adapter->fe); -+ } -+ -+ dvb_attach(isl6423_attach, -+ adapter->fe, -+ i2c_adapter, -+ &tt6400_isl6423_config[count]); -+ -+ } -+ } -+ return 0; -+} -+ -+static struct saa716x_config saa716x_s26400_config = { -+ .model_name = SAA716x_MODEL_S2_6400_DUAL, -+ .dev_type = SAA716x_DEV_S2_6400_DUAL, -+ .boot_mode = SAA716x_EXT_BOOT, -+ .adapters = 2, -+ .frontend_attach = saa716x_s26400_frontend_attach, -+ .irq_handler = saa716x_ff_pci_irq, -+ .i2c_rate = SAA716x_I2C_RATE_100, -+ .i2c_mode = SAA716x_I2C_MODE_IRQ_BUFFERED, -+ -+ .adap_config = { -+ { -+ /* Adapter 0 */ -+ .ts_port = 2, -+ .worker = demux_worker -+ },{ -+ /* Adapter 1 */ -+ .ts_port = 3, -+ .worker = demux_worker -+ } -+ } -+}; -+ -+ -+static struct pci_device_id saa716x_ff_pci_table[] = { -+ -+ MAKE_ENTRY(TECHNOTREND, S2_6400_DUAL_S2_PREMIUM_DEVEL, SAA7160, &saa716x_s26400_config), /* S2 6400 Dual development version */ -+ MAKE_ENTRY(TECHNOTREND, S2_6400_DUAL_S2_PREMIUM_PROD, SAA7160, &saa716x_s26400_config), /* S2 6400 Dual production version */ -+ { } -+}; -+MODULE_DEVICE_TABLE(pci, saa716x_ff_pci_table); -+ -+static struct pci_driver saa716x_ff_pci_driver = { -+ .name = DRIVER_NAME, -+ .id_table = saa716x_ff_pci_table, -+ .probe = saa716x_ff_pci_probe, -+ .remove = saa716x_ff_pci_remove, -+}; -+ -+static int saa716x_ff_init(void) -+{ -+ return pci_register_driver(&saa716x_ff_pci_driver); -+} -+ -+static void saa716x_ff_exit(void) -+{ -+ return pci_unregister_driver(&saa716x_ff_pci_driver); -+} -+ -+module_init(saa716x_ff_init); -+module_exit(saa716x_ff_exit); -+ -+MODULE_DESCRIPTION("SAA716x FF driver"); -+MODULE_AUTHOR("Manu Abraham"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/media/common/saa716x/saa716x_fgpi.c b/drivers/media/common/saa716x/saa716x_fgpi.c -new file mode 100644 -index 0000000..8bdb13d ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_fgpi.c -@@ -0,0 +1,389 @@ -+#include -+ -+#include "saa716x_mod.h" -+ -+#include "saa716x_fgpi_reg.h" -+#include "saa716x_dma_reg.h" -+#include "saa716x_msi_reg.h" -+ -+#include "saa716x_dma.h" -+#include "saa716x_fgpi.h" -+#include "saa716x_spi.h" -+#include "saa716x_priv.h" -+ -+static const u32 mmu_pta_base[] = { -+ MMU_PTA_BASE0, -+ MMU_PTA_BASE1, -+ MMU_PTA_BASE2, -+ MMU_PTA_BASE3, -+ MMU_PTA_BASE4, -+ MMU_PTA_BASE5, -+ MMU_PTA_BASE6, -+ MMU_PTA_BASE7, -+ MMU_PTA_BASE8, -+ MMU_PTA_BASE9, -+ MMU_PTA_BASE10, -+ MMU_PTA_BASE11, -+ MMU_PTA_BASE12, -+ MMU_PTA_BASE13, -+ MMU_PTA_BASE14, -+ MMU_PTA_BASE15, -+}; -+ -+static const u32 mmu_dma_cfg[] = { -+ MMU_DMA_CONFIG0, -+ MMU_DMA_CONFIG1, -+ MMU_DMA_CONFIG2, -+ MMU_DMA_CONFIG3, -+ MMU_DMA_CONFIG4, -+ MMU_DMA_CONFIG5, -+ MMU_DMA_CONFIG6, -+ MMU_DMA_CONFIG7, -+ MMU_DMA_CONFIG8, -+ MMU_DMA_CONFIG9, -+ MMU_DMA_CONFIG10, -+ MMU_DMA_CONFIG11, -+ MMU_DMA_CONFIG12, -+ MMU_DMA_CONFIG13, -+ MMU_DMA_CONFIG14, -+ MMU_DMA_CONFIG15, -+}; -+ -+static const u32 fgpi_ch[] = { -+ FGPI0, -+ FGPI1, -+ FGPI2, -+ FGPI3 -+}; -+ -+static const u32 bamdma_bufmode[] = { -+ BAM_FGPI0_DMA_BUF_MODE, -+ BAM_FGPI1_DMA_BUF_MODE, -+ BAM_FGPI2_DMA_BUF_MODE, -+ BAM_FGPI3_DMA_BUF_MODE -+}; -+ -+static const u32 msi_int_tagack[] = { -+ MSI_INT_TAGACK_FGPI_0, -+ MSI_INT_TAGACK_FGPI_1, -+ MSI_INT_TAGACK_FGPI_2, -+ MSI_INT_TAGACK_FGPI_3 -+}; -+ -+static const u32 msi_int_ovrflw[] = { -+ MSI_INT_OVRFLW_FGPI_0, -+ MSI_INT_OVRFLW_FGPI_1, -+ MSI_INT_OVRFLW_FGPI_2, -+ MSI_INT_OVRFLW_FGPI_3 -+}; -+ -+static const u32 msi_int_avint[] = { -+ MSI_INT_AVINT_FGPI_0, -+ MSI_INT_AVINT_FGPI_1, -+ MSI_INT_AVINT_FGPI_2, -+ MSI_INT_AVINT_FGPI_3 -+}; -+ -+void saa716x_fgpiint_disable(struct saa716x_dmabuf *dmabuf, int channel) -+{ -+ struct saa716x_dev *saa716x = dmabuf->saa716x; -+ -+ u32 fgpi_port; -+ -+ fgpi_port = fgpi_ch[channel]; -+ -+ SAA716x_EPWR(fgpi_port, INT_ENABLE, 0); /* disable FGPI IRQ */ -+ SAA716x_EPWR(fgpi_port, INT_CLR_STATUS, 0x7f); /* clear status */ -+} -+EXPORT_SYMBOL_GPL(saa716x_fgpiint_disable); -+ -+int saa716x_fgpi_get_write_index(struct saa716x_dev *saa716x, u32 fgpi_index) -+{ -+ u32 fgpi_base; -+ u32 buf_mode_reg; -+ u32 buf_mode; -+ -+ switch (fgpi_index) { -+ case 0: /* FGPI_0 */ -+ fgpi_base = FGPI0; -+ buf_mode_reg = BAM_FGPI0_DMA_BUF_MODE; -+ break; -+ -+ case 1: /* FGPI_1 */ -+ fgpi_base = FGPI1; -+ buf_mode_reg = BAM_FGPI1_DMA_BUF_MODE; -+ break; -+ -+ case 2: /* FGPI_2 */ -+ fgpi_base = FGPI2; -+ buf_mode_reg = BAM_FGPI2_DMA_BUF_MODE; -+ break; -+ -+ case 3: /* FGPI_3 */ -+ fgpi_base = FGPI3; -+ buf_mode_reg = BAM_FGPI3_DMA_BUF_MODE; -+ break; -+ -+ default: -+ printk(KERN_ERR "%s: unexpected fgpi %u\n", -+ __func__, fgpi_index); -+ return -1; -+ } -+ -+ buf_mode = SAA716x_EPRD(BAM, buf_mode_reg); -+ if (saa716x->revision < 2) { -+ /* workaround for revision 1: restore buffer numbers on BAM */ -+ SAA716x_EPWR(fgpi_base, INT_CLR_STATUS, 0x7F); -+ SAA716x_EPWR(BAM, buf_mode_reg, buf_mode | 7); -+ } -+ return (buf_mode >> 3) & 0x7; -+} -+EXPORT_SYMBOL_GPL(saa716x_fgpi_get_write_index); -+ -+static u32 saa716x_init_ptables(struct saa716x_dmabuf *dmabuf, int channel) -+{ -+ struct saa716x_dev *saa716x = dmabuf->saa716x; -+ -+ u32 config, i; -+ -+ for (i = 0; i < FGPI_BUFFERS; i++) -+ BUG_ON((dmabuf[i].mem_ptab_phys == 0)); -+ -+ config = mmu_dma_cfg[channel]; /* DMACONFIGx */ -+ -+ SAA716x_EPWR(MMU, config, (FGPI_BUFFERS - 1)); -+ SAA716x_EPWR(MMU, MMU_PTA0_LSB(channel), PTA_LSB(dmabuf[0].mem_ptab_phys)); /* Low */ -+ SAA716x_EPWR(MMU, MMU_PTA0_MSB(channel), PTA_MSB(dmabuf[0].mem_ptab_phys)); /* High */ -+ SAA716x_EPWR(MMU, MMU_PTA1_LSB(channel), PTA_LSB(dmabuf[1].mem_ptab_phys)); /* Low */ -+ SAA716x_EPWR(MMU, MMU_PTA1_MSB(channel), PTA_MSB(dmabuf[1].mem_ptab_phys)); /* High */ -+ SAA716x_EPWR(MMU, MMU_PTA2_LSB(channel), PTA_LSB(dmabuf[2].mem_ptab_phys)); /* Low */ -+ SAA716x_EPWR(MMU, MMU_PTA2_MSB(channel), PTA_MSB(dmabuf[2].mem_ptab_phys)); /* High */ -+ SAA716x_EPWR(MMU, MMU_PTA3_LSB(channel), PTA_LSB(dmabuf[3].mem_ptab_phys)); /* Low */ -+ SAA716x_EPWR(MMU, MMU_PTA3_MSB(channel), PTA_MSB(dmabuf[3].mem_ptab_phys)); /* High */ -+ SAA716x_EPWR(MMU, MMU_PTA4_LSB(channel), PTA_LSB(dmabuf[4].mem_ptab_phys)); /* Low */ -+ SAA716x_EPWR(MMU, MMU_PTA4_MSB(channel), PTA_MSB(dmabuf[4].mem_ptab_phys)); /* High */ -+ SAA716x_EPWR(MMU, MMU_PTA5_LSB(channel), PTA_LSB(dmabuf[5].mem_ptab_phys)); /* Low */ -+ SAA716x_EPWR(MMU, MMU_PTA5_MSB(channel), PTA_MSB(dmabuf[5].mem_ptab_phys)); /* High */ -+ SAA716x_EPWR(MMU, MMU_PTA6_LSB(channel), PTA_LSB(dmabuf[6].mem_ptab_phys)); /* Low */ -+ SAA716x_EPWR(MMU, MMU_PTA6_MSB(channel), PTA_MSB(dmabuf[6].mem_ptab_phys)); /* High */ -+ SAA716x_EPWR(MMU, MMU_PTA7_LSB(channel), PTA_LSB(dmabuf[7].mem_ptab_phys)); /* Low */ -+ SAA716x_EPWR(MMU, MMU_PTA7_MSB(channel), PTA_MSB(dmabuf[7].mem_ptab_phys)); /* High */ -+ -+ return 0; -+} -+ -+int saa716x_fgpi_setparams(struct saa716x_dmabuf *dmabuf, -+ struct fgpi_stream_params *stream_params, -+ int port) -+{ -+ struct saa716x_dev *saa716x = dmabuf->saa716x; -+ -+ u32 fgpi_port, buf_mode, val, mid; -+ u32 D1_XY_END, offst_1, offst_2; -+ int i = 0; -+ -+ fgpi_port = fgpi_ch[port]; -+ buf_mode = bamdma_bufmode[port]; -+ -+ /* Reset FGPI block */ -+ SAA716x_EPWR(fgpi_port, FGPI_SOFT_RESET, FGPI_SOFTWARE_RESET); -+ -+ /* Reset DMA channel */ -+ SAA716x_EPWR(BAM, buf_mode, 0x00000040); -+ saa716x_init_ptables(dmabuf, saa716x->fgpi[port].dma_channel); -+ -+ -+ /* monitor BAM reset */ -+ val = SAA716x_EPRD(BAM, buf_mode); -+ while (val && (i < 100)) { -+ msleep(30); -+ val = SAA716x_EPRD(BAM, buf_mode); -+ i++; -+ } -+ -+ if (val) { -+ dprintk(SAA716x_ERROR, 1, "Error: BAM FGPI Reset failed!"); -+ return -EIO; -+ } -+ -+ /* set buffer count */ -+ SAA716x_EPWR(BAM, buf_mode, FGPI_BUFFERS - 1); -+ -+ /* initialize all available address offsets */ -+ SAA716x_EPWR(BAM, BAM_FGPI_ADDR_OFFST_0(port), 0x0); -+ SAA716x_EPWR(BAM, BAM_FGPI_ADDR_OFFST_1(port), 0x0); -+ SAA716x_EPWR(BAM, BAM_FGPI_ADDR_OFFST_2(port), 0x0); -+ SAA716x_EPWR(BAM, BAM_FGPI_ADDR_OFFST_3(port), 0x0); -+ SAA716x_EPWR(BAM, BAM_FGPI_ADDR_OFFST_4(port), 0x0); -+ SAA716x_EPWR(BAM, BAM_FGPI_ADDR_OFFST_5(port), 0x0); -+ SAA716x_EPWR(BAM, BAM_FGPI_ADDR_OFFST_6(port), 0x0); -+ SAA716x_EPWR(BAM, BAM_FGPI_ADDR_OFFST_7(port), 0x0); -+ -+ /* get module ID */ -+ mid = SAA716x_EPRD(fgpi_port, FGPI_MODULE_ID); -+ if (mid != 0x14b0100) -+ dprintk(SAA716x_ERROR, 1, "FGPI Id<%04x> is not supported", mid); -+ -+ /* Initialize FGPI block */ -+ SAA716x_EPWR(fgpi_port, FGPI_REC_SIZE, stream_params->samples * (stream_params->bits / 8)); -+ SAA716x_EPWR(fgpi_port, FGPI_STRIDE, stream_params->pitch); -+ -+ offst_1 = 0; -+ offst_2 = 0; -+ switch (stream_params->stream_type) { -+ case FGPI_TRANSPORT_STREAM: -+ SAA716x_EPWR(fgpi_port, FGPI_CONTROL, 0x00000080); -+ SAA716x_EPWR(fgpi_port, FGPI_SIZE, stream_params->lines); -+ break; -+ -+ case FGPI_PROGRAM_STREAM: -+ SAA716x_EPWR(fgpi_port, FGPI_CONTROL, 0x00000088); -+ SAA716x_EPWR(fgpi_port, FGPI_SIZE, stream_params->lines); -+ break; -+ -+ case FGPI_VIDEO_STREAM: -+ SAA716x_EPWR(fgpi_port, FGPI_CONTROL, 0x00000088); -+ SAA716x_EPWR(fgpi_port, FGPI_D1_XY_START, 0x00000002); -+ -+ if ((stream_params->stream_flags & FGPI_INTERLACED) && -+ (stream_params->stream_flags & FGPI_ODD_FIELD) && -+ (stream_params->stream_flags & FGPI_EVEN_FIELD)) { -+ -+ SAA716x_EPWR(fgpi_port, FGPI_SIZE, stream_params->lines / 2); -+ SAA716x_EPWR(fgpi_port, FGPI_STRIDE, 768 * 4); /* interlaced stride of 2 lines */ -+ -+ D1_XY_END = (stream_params->samples << 16); -+ D1_XY_END |= (stream_params->lines / 2) + 2; -+ -+ if (stream_params->stream_flags & FGPI_PAL) -+ offst_1 = 768 * 2; -+ else -+ offst_2 = 768 * 2; -+ -+ } else { -+ SAA716x_EPWR(fgpi_port, FGPI_SIZE, stream_params->lines); -+ SAA716x_EPWR(fgpi_port, FGPI_STRIDE, 768 * 2); /* stride of 1 line */ -+ -+ D1_XY_END = stream_params->samples << 16; -+ D1_XY_END |= stream_params->lines + 2; -+ } -+ -+ SAA716x_EPWR(fgpi_port, FGPI_D1_XY_END, D1_XY_END); -+ break; -+ -+ default: -+ SAA716x_EPWR(fgpi_port, FGPI_CONTROL, 0x00000080); -+ break; -+ } -+ -+ SAA716x_EPWR(fgpi_port, FGPI_BASE_1, ((saa716x->fgpi[port].dma_channel) << 21) + offst_1); -+ SAA716x_EPWR(fgpi_port, FGPI_BASE_2, ((saa716x->fgpi[port].dma_channel) << 21) + offst_2); -+ -+ return 0; -+} -+ -+int saa716x_fgpi_start(struct saa716x_dev *saa716x, int port, -+ struct fgpi_stream_params *stream_params) -+{ -+ u32 fgpi_port; -+ u32 config; -+ u32 val; -+ u32 i; -+ -+ fgpi_port = fgpi_ch[port]; -+ -+ SAA716x_EPWR(fgpi_port, FGPI_INTERFACE, 0); -+ msleep(10); -+ -+ if (saa716x_fgpi_setparams(saa716x->fgpi[port].dma_buf, stream_params, port) != 0) { -+ return -EIO; -+ } -+ -+ config = mmu_dma_cfg[saa716x->fgpi[port].dma_channel]; /* DMACONFIGx */ -+ -+ val = SAA716x_EPRD(MMU, config); -+ SAA716x_EPWR(MMU, config, val & ~0x40); -+ SAA716x_EPWR(MMU, config, val | 0x40); -+ -+ SAA716x_EPWR(fgpi_port, INT_ENABLE, 0x7F); -+ -+ val = SAA716x_EPRD(MMU, config); -+ i = 0; -+ while (i < 500) { -+ if (val & 0x80) -+ break; -+ msleep(10); -+ val = SAA716x_EPRD(MMU, config); -+ i++; -+ } -+ -+ if (!(val & 0x80)) { -+ dprintk(SAA716x_ERROR, 1, "Error: PTE pre-fetch failed!"); -+ return -EIO; -+ } -+ -+ val = SAA716x_EPRD(fgpi_port, FGPI_CONTROL); -+ val |= 0x3000; -+ -+ saa716x_set_clk_external(saa716x, saa716x->fgpi[port].dma_channel); -+ -+ SAA716x_EPWR(fgpi_port, FGPI_CONTROL, val); -+ -+ SAA716x_EPWR(MSI, MSI_INT_ENA_SET_L, msi_int_tagack[port]); -+ -+ return 0; -+} -+ -+int saa716x_fgpi_stop(struct saa716x_dev *saa716x, int port) -+{ -+ u32 fgpi_port; -+ u32 val; -+ -+ fgpi_port = fgpi_ch[port]; -+ -+ SAA716x_EPWR(MSI, MSI_INT_ENA_CLR_L, msi_int_tagack[port]); -+ -+ val = SAA716x_EPRD(fgpi_port, FGPI_CONTROL); -+ val &= ~0x3000; -+ SAA716x_EPWR(fgpi_port, FGPI_CONTROL, val); -+ -+ saa716x_set_clk_internal(saa716x, saa716x->fgpi[port].dma_channel); -+ -+ return 0; -+} -+ -+int saa716x_fgpi_init(struct saa716x_dev *saa716x, int port, -+ void (*worker)(unsigned long)) -+{ -+ int i; -+ int ret; -+ -+ saa716x->fgpi[port].dma_channel = port + 6; -+ for (i = 0; i < FGPI_BUFFERS; i++) -+ { -+ /* TODO: what is a good size for TS DMA buffer? */ -+ ret = saa716x_dmabuf_alloc(saa716x, &saa716x->fgpi[port].dma_buf[i], 16 * SAA716x_PAGE_SIZE); -+ if (ret < 0) { -+ return ret; -+ } -+ } -+ saa716x->fgpi[port].saa716x = saa716x; -+ tasklet_init(&saa716x->fgpi[port].tasklet, worker, -+ (unsigned long)&saa716x->fgpi[port]); -+ saa716x->fgpi[port].read_index = 0; -+ -+ return 0; -+} -+ -+int saa716x_fgpi_exit(struct saa716x_dev *saa716x, int port) -+{ -+ int i; -+ -+ tasklet_kill(&saa716x->fgpi[port].tasklet); -+ for (i = 0; i < FGPI_BUFFERS; i++) -+ { -+ saa716x_dmabuf_free(saa716x, &saa716x->fgpi[port].dma_buf[i]); -+ } -+ -+ return 0; -+} -diff --git a/drivers/media/common/saa716x/saa716x_fgpi.h b/drivers/media/common/saa716x/saa716x_fgpi.h -new file mode 100644 -index 0000000..225aff0 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_fgpi.h -@@ -0,0 +1,112 @@ -+#ifndef __SAA716x_FGPI_H -+#define __SAA716x_FGPI_H -+ -+#include -+ -+#define FGPI_BUFFERS 8 -+#define PTA_LSB(__mem) ((u32 ) (__mem)) -+#define PTA_MSB(__mem) ((u32 ) ((u64)(__mem) >> 32)) -+ -+#define BAM_DMA_BUF_MODE_BASE 0x0d8 -+#define BAM_DMA_BUF_MODE_OFFSET 0x24 -+ -+#define BAM_DMA_BUF_MODE(__ch) (BAM_DMA_BUF_MODE_BASE + (BAM_DMA_BUF_MODE_OFFSET * __ch)) -+ -+#define BAM_FGPI_ADDR_OFFST_BASE 0x0dc -+#define BAM_FGPI_ADDR_OFFST_OFFSET 0x24 -+ -+#define BAM_FGPI_ADDR_OFFSET(__ch) (BAM_FGPI_ADDR_OFFST_BASE + (BAM_FGPI_ADDR_OFFST_OFFSET * __ch)) -+ -+#define BAM_FGPI_ADDR_OFFST_0(__ch) BAM_FGPI_ADDR_OFFSET(__ch) + 0x00 -+#define BAM_FGPI_ADDR_OFFST_1(__ch) BAM_FGPI_ADDR_OFFSET(__ch) + 0x04 -+#define BAM_FGPI_ADDR_OFFST_2(__ch) BAM_FGPI_ADDR_OFFSET(__ch) + 0x08 -+#define BAM_FGPI_ADDR_OFFST_3(__ch) BAM_FGPI_ADDR_OFFSET(__ch) + 0x0c -+#define BAM_FGPI_ADDR_OFFST_4(__ch) BAM_FGPI_ADDR_OFFSET(__ch) + 0x10 -+#define BAM_FGPI_ADDR_OFFST_5(__ch) BAM_FGPI_ADDR_OFFSET(__ch) + 0x14 -+#define BAM_FGPI_ADDR_OFFST_6(__ch) BAM_FGPI_ADDR_OFFSET(__ch) + 0x18 -+#define BAM_FGPI_ADDR_OFFST_7(__ch) BAM_FGPI_ADDR_OFFSET(__ch) + 0x1c -+ -+struct saa716x_dmabuf; -+ -+/* -+ * Port supported streams -+ * -+ * FGPI_AUDIO_STREAM -+ * FGPI_VIDEO_STREAM -+ * FGPI_VBI_STREAM -+ * FGPI_TRANSPORT_STREAM -+ * FGPI_PROGRAM_STREAM -+ */ -+enum fgpi_stream_type { -+ FGPI_AUDIO_STREAM = 0x01, -+ FGPI_VIDEO_STREAM = 0x02, -+ FGPI_VBI_STREAM = 0x04, -+ FGPI_TRANSPORT_STREAM = 0x08, -+ FGPI_PROGRAM_STREAM = 0x10 -+}; -+ -+/* -+ * Stream port flags -+ * -+ * FGPI_ODD_FIELD -+ * FGPI_EVEN_FIELD -+ * FGPI_HD_0 -+ * FGPI_HD_1 -+ * FGPI_PAL -+ * FGPI_NTSC -+ */ -+enum fgpi_stream_flags { -+ FGPI_ODD_FIELD = 0x0001, -+ FGPI_EVEN_FIELD = 0x0002, -+ FGPI_INTERLACED = 0x0004, -+ FGPI_HD0 = 0x0010, -+ FGPI_HD1 = 0x0020, -+ FGPI_PAL = 0x0040, -+ FGPI_NTSC = 0x0080, -+ FGPI_NO_SCALER = 0x0100, -+}; -+ -+/* -+ * Stream port parameters -+ * bits: Bits per sample -+ * samples: samples perline -+ * lines: number of lines -+ * pitch: stream pitch in bytes -+ * offset: offset to first valid line -+ */ -+struct fgpi_stream_params { -+ u32 bits; -+ u32 samples; -+ u32 lines; -+ -+ s32 pitch; -+ -+ u32 offset; -+ u32 page_tables; -+ -+ enum fgpi_stream_flags stream_flags; -+ enum fgpi_stream_type stream_type; -+}; -+ -+struct saa716x_dmabuf; -+ -+struct saa716x_fgpi_stream_port { -+ u8 dma_channel; -+ struct saa716x_dmabuf dma_buf[FGPI_BUFFERS]; -+ struct saa716x_dev *saa716x; -+ struct tasklet_struct tasklet; -+ u8 read_index; -+}; -+ -+extern void saa716x_fgpiint_disable(struct saa716x_dmabuf *dmabuf, int channel); -+extern int saa716x_fgpi_get_write_index(struct saa716x_dev *saa716x, -+ u32 fgpi_index); -+extern int saa716x_fgpi_start(struct saa716x_dev *saa716x, int port, -+ struct fgpi_stream_params *stream_params); -+extern int saa716x_fgpi_stop(struct saa716x_dev *saa716x, int port); -+ -+extern int saa716x_fgpi_init(struct saa716x_dev *saa716x, int port, -+ void (*worker)(unsigned long)); -+extern int saa716x_fgpi_exit(struct saa716x_dev *saa716x, int port); -+ -+#endif /* __SAA716x_FGPI_H */ -diff --git a/drivers/media/common/saa716x/saa716x_fgpi_reg.h b/drivers/media/common/saa716x/saa716x_fgpi_reg.h -new file mode 100644 -index 0000000..1193016 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_fgpi_reg.h -@@ -0,0 +1,74 @@ -+#ifndef __SAA716x_FGPI_REG_H -+#define __SAA716x_FGPI_REG_H -+ -+/* -------------- FGPI Registers -------------- */ -+ -+#define FGPI_CONTROL 0x000 -+#define FGPI_CAPTURE_ENABLE_2 (0x00000001 << 13) -+#define FGPI_CAPTURE_ENABLE_1 (0x00000001 << 12) -+#define FGPI_MODE (0x00000001 << 11) -+#define FGPI_SAMPLE_SIZE (0x00000003 << 8) -+#define FGPI_BUF_SYNC_MSG_STOP (0x00000003 << 5) -+#define FGPI_REC_START_MSG_START (0x00000003 << 2) -+#define FGPI_TSTAMP_SELECT (0x00000001 << 1) -+#define FGPI_VAR_LENGTH (0x00000001 << 0) -+ -+#define FGPI_BASE_1 0x004 -+#define FGPI_BASE_2 0x008 -+#define FGPI_SIZE 0x00c -+#define FGPI_REC_SIZE 0x010 -+#define FGPI_STRIDE 0x014 -+#define FGPI_NUM_RECORD_1 0x018 -+#define FGPI_NUM_RECORD_2 0x01c -+#define FGPI_THRESHOLD_1 0x020 -+#define FGPI_THRESHOLD_2 0x024 -+#define FGPI_D1_XY_START 0x028 -+#define FGPI_D1_XY_END 0x02c -+ -+#define INT_STATUS 0xfe0 -+#define FGPI_BUF1_ACTIVE (0x00000001 << 7) -+#define FGPI_OVERFLOW (0x00000001 << 6) -+#define FGPI_MBE (0x00000001 << 5) -+#define FGPI_UNDERRUN (0x00000001 << 4) -+#define FGPI_THRESH2_REACHED (0x00000001 << 3) -+#define FGPI_THRESH1_REACHED (0x00000001 << 2) -+#define FGPI_BUF2_FULL (0x00000001 << 1) -+#define FGPI_BUF1_FULL (0x00000001 << 0) -+ -+#define INT_ENABLE 0xfe4 -+#define FGPI_OVERFLOW_ENA (0x00000001 << 6) -+#define FGPI_MBE_ENA (0x00000001 << 5) -+#define FGPI_UNDERRUN_ENA (0x00000001 << 4) -+#define FGPI_THRESH2_REACHED_ENA (0x00000001 << 3) -+#define FGPI_THRESH1_REACHED_ENA (0x00000001 << 2) -+#define FGPI_BUF2_FULL_ENA (0x00000001 << 1) -+#define FGPI_BUF1_FULL_ENA (0x00000001 << 0) -+ -+#define INT_CLR_STATUS 0xfe8 -+#define FGPI_OVERFLOW_ACK (0x00000001 << 6) -+#define FGPI_MBE_ACK (0x00000001 << 5) -+#define FGPI_UNDERRUN_ACK (0x00000001 << 4) -+#define FGPI_THRESH2_REACHED_ACK (0x00000001 << 3) -+#define FGPI_THRESH1_REACHED_ACK (0x00000001 << 2) -+#define FGPI_BUF2_DONE_ACK (0x00000001 << 1) -+#define FGPI_BUF1_DONE_ACK (0x00000001 << 0) -+ -+#define INT_SET_STATUS 0xfec -+#define FGPI_OVERFLOW_SET (0x00000001 << 6) -+#define FGPI_MBE_SET (0x00000001 << 5) -+#define FGPI_UNDERRUN_SET (0x00000001 << 4) -+#define FGPI_THRESH2_REACHED_SET (0x00000001 << 3) -+#define FGPI_THRESH1_REACHED_SET (0x00000001 << 2) -+#define FGPI_BUF2_DONE_SET (0x00000001 << 1) -+#define FGPI_BUF1_DONE_SET (0x00000001 << 0) -+ -+#define FGPI_SOFT_RESET 0xff0 -+#define FGPI_SOFTWARE_RESET (0x00000001 << 0) -+ -+#define FGPI_INTERFACE 0xff4 -+#define FGPI_DISABLE_BUS_IF (0x00000001 << 0) -+ -+#define FGPI_MOD_ID_EXT 0xff8 -+#define FGPI_MODULE_ID 0xffc -+ -+#endif /* __SAA716x_FGPI_REG_H */ -diff --git a/drivers/media/common/saa716x/saa716x_gpio.c b/drivers/media/common/saa716x/saa716x_gpio.c -new file mode 100644 -index 0000000..62b6112 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_gpio.c -@@ -0,0 +1,140 @@ -+#include -+#include -+ -+#include "saa716x_mod.h" -+ -+#include "saa716x_gpio_reg.h" -+ -+#include "saa716x_gpio.h" -+#include "saa716x_spi.h" -+#include "saa716x_priv.h" -+ -+void saa716x_gpio_init(struct saa716x_dev *saa716x) -+{ -+ spin_lock_init(&saa716x->gpio_lock); -+} -+EXPORT_SYMBOL_GPL(saa716x_gpio_init); -+ -+int saa716x_get_gpio_mode(struct saa716x_dev *saa716x, u32 *config) -+{ -+ *config = SAA716x_EPRD(GPIO, GPIO_WR_MODE); -+ -+ return 0; -+} -+ -+int saa716x_set_gpio_mode(struct saa716x_dev *saa716x, u32 mask, u32 config) -+{ -+ unsigned long flags; -+ u32 reg; -+ -+ spin_lock_irqsave(&saa716x->gpio_lock, flags); -+ reg = SAA716x_EPRD(GPIO, GPIO_WR_MODE); -+ reg &= ~mask; -+ reg |= (config & mask); -+ SAA716x_EPWR(GPIO, GPIO_WR_MODE, reg); -+ spin_unlock_irqrestore(&saa716x->gpio_lock, flags); -+ -+ return 0; -+} -+ -+u32 saa716x_gpio_rd(struct saa716x_dev *saa716x) -+{ -+ return SAA716x_EPRD(GPIO, GPIO_RD); -+} -+ -+void saa716x_gpio_wr(struct saa716x_dev *saa716x, u32 data) -+{ -+ SAA716x_EPWR(GPIO, GPIO_WR, data); -+} -+ -+void saa716x_gpio_ctl(struct saa716x_dev *saa716x, u32 mask, u32 bits) -+{ -+ unsigned long flags; -+ u32 reg; -+ -+ spin_lock_irqsave(&saa716x->gpio_lock, flags); -+ -+ reg = SAA716x_EPRD(GPIO, GPIO_OEN); -+ reg &= mask; -+ reg |= bits; -+ SAA716x_EPWR(GPIO, GPIO_OEN, reg); -+ -+ spin_unlock_irqrestore(&saa716x->gpio_lock, flags); -+} -+ -+void saa716x_gpio_bits(struct saa716x_dev *saa716x, u32 bits) -+{ -+ unsigned long flags; -+ u32 reg; -+ -+ spin_lock_irqsave(&saa716x->gpio_lock, flags); -+ -+ reg = SAA716x_EPRD(GPIO, GPIO_WR); -+ reg &= ~bits; -+ /* TODO ! add maskable config bits in here */ -+ /* reg |= (config->mask & bits) */ -+ reg |= bits; -+ SAA716x_EPWR(GPIO, GPIO_WR, reg); -+ -+ spin_unlock_irqrestore(&saa716x->gpio_lock, flags); -+} -+ -+void saa716x_gpio_set_output(struct saa716x_dev *saa716x, int gpio) -+{ -+ uint32_t value; -+ -+ value = SAA716x_EPRD(GPIO, GPIO_OEN); -+ value &= ~(1 << gpio); -+ SAA716x_EPWR(GPIO, GPIO_OEN, value); -+} -+EXPORT_SYMBOL_GPL(saa716x_gpio_set_output); -+ -+void saa716x_gpio_set_input(struct saa716x_dev *saa716x, int gpio) -+{ -+ uint32_t value; -+ -+ value = SAA716x_EPRD(GPIO, GPIO_OEN); -+ value |= 1 << gpio; -+ SAA716x_EPWR(GPIO, GPIO_OEN, value); -+} -+EXPORT_SYMBOL_GPL(saa716x_gpio_set_input); -+ -+void saa716x_gpio_set_mode(struct saa716x_dev *saa716x, int gpio, int mode) -+{ -+ uint32_t value; -+ -+ value = SAA716x_EPRD(GPIO, GPIO_WR_MODE); -+ if (mode) -+ value |= 1 << gpio; -+ else -+ value &= ~(1 << gpio); -+ SAA716x_EPWR(GPIO, GPIO_WR_MODE, value); -+} -+EXPORT_SYMBOL_GPL(saa716x_gpio_set_mode); -+ -+void saa716x_gpio_write(struct saa716x_dev *saa716x, int gpio, int set) -+{ -+ uint32_t value; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&saa716x->gpio_lock, flags); -+ value = SAA716x_EPRD(GPIO, GPIO_WR); -+ if (set) -+ value |= 1 << gpio; -+ else -+ value &= ~(1 << gpio); -+ SAA716x_EPWR(GPIO, GPIO_WR, value); -+ spin_unlock_irqrestore(&saa716x->gpio_lock, flags); -+} -+EXPORT_SYMBOL_GPL(saa716x_gpio_write); -+ -+int saa716x_gpio_read(struct saa716x_dev *saa716x, int gpio) -+{ -+ uint32_t value; -+ -+ value = SAA716x_EPRD(GPIO, GPIO_RD); -+ if (value & (1 << gpio)) -+ return 1; -+ return 0; -+} -+EXPORT_SYMBOL_GPL(saa716x_gpio_read); -diff --git a/drivers/media/common/saa716x/saa716x_gpio.h b/drivers/media/common/saa716x/saa716x_gpio.h -new file mode 100644 -index 0000000..a82580b ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_gpio.h -@@ -0,0 +1,26 @@ -+#ifndef __SAA716x_GPIO_H -+#define __SAA716x_GPIO_H -+ -+#define BOOT_MODE GPIO_31 | GPIO_30 -+#define AV_UNIT_B GPIO_25 -+#define AV_UNIT_A GPIO_24 -+#define AV_INTR_B GPIO_01 -+#define AV_INTR_A GPIO_00 -+ -+struct saa716x_dev; -+ -+extern void saa716x_gpio_init(struct saa716x_dev *saa716x); -+ -+extern u32 saa716x_gpio_rd(struct saa716x_dev *saa716x); -+extern void saa716x_gpio_wr(struct saa716x_dev *saa716x, u32 data); -+extern void saa716x_gpio_ctl(struct saa716x_dev *saa716x, u32 mask, u32 bits); -+ -+extern void saa716x_gpio_bits(struct saa716x_dev *saa716x, u32 bits); -+ -+extern void saa716x_gpio_set_output(struct saa716x_dev *saa716x, int gpio); -+extern void saa716x_gpio_set_input(struct saa716x_dev *saa716x, int gpio); -+extern void saa716x_gpio_set_mode(struct saa716x_dev *saa716x, int gpio, int mode); -+extern void saa716x_gpio_write(struct saa716x_dev *saa716x, int gpio, int set); -+extern int saa716x_gpio_read(struct saa716x_dev *saa716x, int gpio); -+ -+#endif /* __SAA716x_GPIO_H */ -diff --git a/drivers/media/common/saa716x/saa716x_gpio_reg.h b/drivers/media/common/saa716x/saa716x_gpio_reg.h -new file mode 100644 -index 0000000..f36184a ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_gpio_reg.h -@@ -0,0 +1,47 @@ -+#ifndef __SAA716x_GPIO_REG_H -+#define __SAA716x_GPIO_REG_H -+ -+/* -------------- GPIO Registers -------------- */ -+ -+#define GPIO_RD 0x000 -+#define GPIO_WR 0x004 -+#define GPIO_WR_MODE 0x008 -+#define GPIO_OEN 0x00c -+ -+#define GPIO_SW_RST 0xff0 -+#define GPIO_SW_RESET (0x00000001 << 0) -+ -+#define GPIO_31 (1 << 31) -+#define GPIO_30 (1 << 30) -+#define GPIO_29 (1 << 29) -+#define GPIO_28 (1 << 28) -+#define GPIO_27 (1 << 27) -+#define GPIO_26 (1 << 26) -+#define GPIO_25 (1 << 25) -+#define GPIO_24 (1 << 24) -+#define GPIO_23 (1 << 23) -+#define GPIO_22 (1 << 22) -+#define GPIO_21 (1 << 21) -+#define GPIO_20 (1 << 20) -+#define GPIO_19 (1 << 19) -+#define GPIO_18 (1 << 18) -+#define GPIO_17 (1 << 17) -+#define GPIO_16 (1 << 16) -+#define GPIO_15 (1 << 15) -+#define GPIO_14 (1 << 14) -+#define GPIO_13 (1 << 13) -+#define GPIO_12 (1 << 12) -+#define GPIO_11 (1 << 11) -+#define GPIO_10 (1 << 10) -+#define GPIO_09 (1 << 9) -+#define GPIO_08 (1 << 8) -+#define GPIO_07 (1 << 7) -+#define GPIO_06 (1 << 6) -+#define GPIO_05 (1 << 5) -+#define GPIO_04 (1 << 4) -+#define GPIO_03 (1 << 3) -+#define GPIO_02 (1 << 2) -+#define GPIO_01 (1 << 1) -+#define GPIO_00 (1 << 0) -+ -+#endif /* __SAA716x_GPIO_REG_H */ -diff --git a/drivers/media/common/saa716x/saa716x_greg.c b/drivers/media/common/saa716x/saa716x_greg.c -new file mode 100644 -index 0000000..d93a3b8 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_greg.c -@@ -0,0 +1,42 @@ -+#include -+ -+#include "saa716x_mod.h" -+ -+#include "saa716x_greg_reg.h" -+#include "saa716x_greg.h" -+#include "saa716x_spi.h" -+#include "saa716x_priv.h" -+ -+static u32 g_save[12]; -+ -+void saa716x_greg_save(struct saa716x_dev *saa716x) -+{ -+ g_save[0] = SAA716x_EPRD(GREG, GREG_SUBSYS_CONFIG); -+ g_save[1] = SAA716x_EPRD(GREG, GREG_MSI_BAR_PMCSR); -+ g_save[2] = SAA716x_EPRD(GREG, GREG_PMCSR_DATA_1); -+ g_save[3] = SAA716x_EPRD(GREG, GREG_PMCSR_DATA_2); -+ g_save[4] = SAA716x_EPRD(GREG, GREG_VI_CTRL); -+ g_save[5] = SAA716x_EPRD(GREG, GREG_FGPI_CTRL); -+ g_save[6] = SAA716x_EPRD(GREG, GREG_RSTU_CTRL); -+ g_save[7] = SAA716x_EPRD(GREG, GREG_I2C_CTRL); -+ g_save[8] = SAA716x_EPRD(GREG, GREG_OVFLW_CTRL); -+ g_save[9] = SAA716x_EPRD(GREG, GREG_TAG_ACK_FLEN); -+ -+ g_save[10] = SAA716x_EPRD(GREG, GREG_VIDEO_IN_CTRL); -+} -+ -+void saa716x_greg_restore(struct saa716x_dev *saa716x) -+{ -+ SAA716x_EPWR(GREG, GREG_SUBSYS_CONFIG, g_save[0]); -+ SAA716x_EPWR(GREG, GREG_MSI_BAR_PMCSR, g_save[1]); -+ SAA716x_EPWR(GREG, GREG_PMCSR_DATA_1, g_save[2]); -+ SAA716x_EPWR(GREG, GREG_PMCSR_DATA_2, g_save[3]); -+ SAA716x_EPWR(GREG, GREG_VI_CTRL, g_save[4]); -+ SAA716x_EPWR(GREG, GREG_FGPI_CTRL, g_save[5]); -+ SAA716x_EPWR(GREG, GREG_RSTU_CTRL, g_save[6]); -+ SAA716x_EPWR(GREG, GREG_I2C_CTRL, g_save[7]); -+ SAA716x_EPWR(GREG, GREG_OVFLW_CTRL, g_save[8]); -+ SAA716x_EPWR(GREG, GREG_TAG_ACK_FLEN, g_save[9]); -+ -+ SAA716x_EPWR(GREG, GREG_VIDEO_IN_CTRL, g_save[10]); -+} -diff --git a/drivers/media/common/saa716x/saa716x_greg.h b/drivers/media/common/saa716x/saa716x_greg.h -new file mode 100644 -index 0000000..487595e ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_greg.h -@@ -0,0 +1,9 @@ -+#ifndef __SAA716x_GREG_H -+#define __SAA716x_GREG_H -+ -+struct saa716x_dev; -+ -+extern void saa716x_greg_save(struct saa716x_dev *saa716x); -+extern void saa716x_greg_restore(struct saa716x_dev *saa716x); -+ -+#endif /* __SAA716x_GREG_H */ -diff --git a/drivers/media/common/saa716x/saa716x_greg_reg.h b/drivers/media/common/saa716x/saa716x_greg_reg.h -new file mode 100644 -index 0000000..052e8cd ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_greg_reg.h -@@ -0,0 +1,91 @@ -+#ifndef __SAA716x_GREG_REG_H -+#define __SAA716x_GREG_REG_H -+ -+/* -------------- GREG Registers -------------- */ -+ -+#define GREG_SUBSYS_CONFIG 0x000 -+#define GREG_SUBSYS_ID (0x0000ffff << 16) -+#define GREG_SUBSYS_VID (0x0000ffff << 0) -+ -+#define GREG_MSI_BAR_PMCSR 0x004 -+#define GREG_PMCSR_SCALE_7 (0x00000003 << 30) -+#define GREG_PMCSR_SCALE_6 (0x00000003 << 28) -+#define GREG_PMCSR_SCALE_5 (0x00000003 << 26) -+#define GREG_PMCSR_SCALE_4 (0x00000003 << 24) -+#define GREG_PMCSR_SCALE_3 (0x00000003 << 22) -+#define GREG_PMCSR_SCALE_2 (0x00000003 << 20) -+#define GREG_PMCSR_SCALE_1 (0x00000003 << 18) -+#define GREG_PMCSR_SCALE_0 (0x00000003 << 16) -+ -+#define GREG_BAR_WIDTH_17 (0x0000001e << 8) -+#define GREG_BAR_WIDTH_18 (0x0000001c << 8) -+#define GREG_BAR_WIDTH_19 (0x00000018 << 8) -+#define GREG_BAR_WIDTH_20 (0x00000010 << 8) -+ -+#define GREG_BAR_PREFETCH (0x00000001 << 3) -+#define GREG_MSI_MM_CAP1 (0x00000000 << 0) // FIXME ! -+#define GREG_MSI_MM_CAP2 (0x00000001 << 0) -+#define GREG_MSI_MM_CAP4 (0x00000002 << 0) -+#define GREG_MSI_MM_CAP8 (0x00000003 << 0) -+#define GREG_MSI_MM_CAP16 (0x00000004 << 0) -+#define GREG_MSI_MM_CAP32 (0x00000005 << 0) -+ -+#define GREG_PMCSR_DATA_1 0x008 -+#define GREG_PMCSR_DATA_2 0x00c -+#define GREG_VI_CTRL 0x010 -+#define GREG_FGPI_CTRL 0x014 -+ -+#define GREG_RSTU_CTRL 0x018 -+#define GREG_BOOT_READY (0x00000001 << 13) -+#define GREG_RESET_REQ (0x00000001 << 12) -+#define GREG_IP_RST_RELEASE (0x00000001 << 11) -+#define GREG_ADAPTER_RST_RELEASE (0x00000001 << 10) -+#define GREG_PCIE_CORE_RST_RELEASE (0x00000001 << 9) -+#define GREG_BOOT_IP_RST_RELEASE (0x00000001 << 8) -+#define GREG_BOOT_RST_RELEASE (0x00000001 << 7) -+#define GREG_CGU_RST_RELEASE (0x00000001 << 6) -+#define GREG_IP_RST_ASSERT (0x00000001 << 5) -+#define GREG_ADAPTER_RST_ASSERT (0x00000001 << 4) -+#define GREG_RST_ASSERT (0x00000001 << 3) -+#define GREG_BOOT_IP_RST_ASSERT (0x00000001 << 2) -+#define GREG_BOOT_RST_ASSERT (0x00000001 << 1) -+#define GREG_CGU_RST_ASSERT (0x00000001 << 0) -+ -+#define GREG_I2C_CTRL 0x01c -+#define GREG_I2C_SLAVE_ADDR (0x0000007f << 0) -+ -+#define GREG_OVFLW_CTRL 0x020 -+#define GREG_OVERFLOW_ENABLE (0x00001fff << 0) -+ -+#define GREG_TAG_ACK_FLEN 0x024 -+#define GREG_TAG_ACK_FLEN_1B (0x00000000 << 0) -+#define GREG_TAG_ACK_FLEN_2B (0x00000001 << 0) -+#define GREG_TAG_ACK_FLEN_4B (0x00000002 << 0) -+#define GREG_TAG_ACK_FLEN_8B (0x00000003 << 0) -+ -+#define GREG_VIDEO_IN_CTRL 0x028 -+ -+#define GREG_SPARE_1 0x02c -+#define GREG_SPARE_2 0x030 -+#define GREG_SPARE_3 0x034 -+#define GREG_SPARE_4 0x038 -+#define GREG_SPARE_5 0x03c -+#define GREG_SPARE_6 0x040 -+#define GREG_SPARE_7 0x044 -+#define GREG_SPARE_8 0x048 -+#define GREG_SPARE_9 0x04c -+#define GREG_SPARE_10 0x050 -+#define GREG_SPARE_11 0x054 -+#define GREG_SPARE_12 0x058 -+#define GREG_SPARE_13 0x05c -+#define GREG_SPARE_14 0x060 -+#define GREG_SPARE_15 0x064 -+ -+#define GREG_FAIL_DISABLE 0x068 -+#define GREG_BOOT_FAIL_DISABLE (0x00000001 << 0) -+ -+#define GREG_SW_RST 0xff0 -+#define GREG_SW_RESET (0x00000001 << 0) -+ -+ -+#endif /* __SAA716x_GREG_REG_H */ -diff --git a/drivers/media/common/saa716x/saa716x_hybrid.c b/drivers/media/common/saa716x/saa716x_hybrid.c -new file mode 100644 -index 0000000..27e5e71 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_hybrid.c -@@ -0,0 +1,726 @@ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#include "saa716x_mod.h" -+ -+#include "saa716x_gpio_reg.h" -+#include "saa716x_greg_reg.h" -+#include "saa716x_msi_reg.h" -+ -+#include "saa716x_adap.h" -+#include "saa716x_i2c.h" -+#include "saa716x_msi.h" -+#include "saa716x_hybrid.h" -+#include "saa716x_gpio.h" -+#include "saa716x_rom.h" -+#include "saa716x_spi.h" -+#include "saa716x_priv.h" -+ -+#include "zl10353.h" -+#include "mb86a16.h" -+#include "tda1004x.h" -+#include "tda827x.h" -+ -+unsigned int verbose; -+module_param(verbose, int, 0644); -+MODULE_PARM_DESC(verbose, "verbose startup messages, default is 1 (yes)"); -+ -+unsigned int int_type; -+module_param(int_type, int, 0644); -+MODULE_PARM_DESC(int_type, "force Interrupt Handler type: 0=INT-A, 1=MSI, 2=MSI-X. default INT-A mode"); -+ -+#define DRIVER_NAME "SAA716x Hybrid" -+ -+static int saa716x_hybrid_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pci_id) -+{ -+ struct saa716x_dev *saa716x; -+ int err = 0; -+ -+ saa716x = kzalloc(sizeof (struct saa716x_dev), GFP_KERNEL); -+ if (saa716x == NULL) { -+ printk(KERN_ERR "saa716x_hybrid_pci_probe ERROR: out of memory\n"); -+ err = -ENOMEM; -+ goto fail0; -+ } -+ -+ saa716x->verbose = verbose; -+ saa716x->int_type = int_type; -+ saa716x->pdev = pdev; -+ saa716x->config = (struct saa716x_config *) pci_id->driver_data; -+ -+ err = saa716x_pci_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x PCI Initialization failed"); -+ goto fail1; -+ } -+ -+ err = saa716x_cgu_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x CGU Init failed"); -+ goto fail1; -+ } -+ -+ err = saa716x_core_boot(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x Core Boot failed"); -+ goto fail2; -+ } -+ dprintk(SAA716x_DEBUG, 1, "SAA716x Core Boot Success"); -+ -+ err = saa716x_msi_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x MSI Init failed"); -+ goto fail2; -+ } -+ -+ err = saa716x_jetpack_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x Jetpack core Initialization failed"); -+ goto fail1; -+ } -+ -+ err = saa716x_i2c_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x I2C Initialization failed"); -+ goto fail3; -+ } -+ -+ saa716x_gpio_init(saa716x); -+ -+ err = saa716x_dump_eeprom(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x EEPROM dump failed"); -+ } -+ -+ err = saa716x_eeprom_data(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x EEPROM dump failed"); -+ } -+ -+ /* enable decoders on 7162 */ -+ if (pdev->device == SAA7162) { -+ saa716x_gpio_set_output(saa716x, 24); -+ saa716x_gpio_set_output(saa716x, 25); -+ -+ saa716x_gpio_write(saa716x, 24, 0); -+ saa716x_gpio_write(saa716x, 25, 0); -+ -+ msleep(10); -+ -+ saa716x_gpio_write(saa716x, 24, 1); -+ saa716x_gpio_write(saa716x, 25, 1); -+ } -+ -+ /* set default port mapping */ -+ SAA716x_EPWR(GREG, GREG_VI_CTRL, 0x2C688F44); -+ /* enable FGPI3 and FGPI0 for TS input from Port 3 and 6 */ -+ SAA716x_EPWR(GREG, GREG_FGPI_CTRL, 0x894); -+ -+ err = saa716x_dvb_init(saa716x); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x DVB initialization failed"); -+ goto fail4; -+ } -+ -+ return 0; -+ -+fail4: -+ saa716x_dvb_exit(saa716x); -+fail3: -+ saa716x_i2c_exit(saa716x); -+fail2: -+ saa716x_pci_exit(saa716x); -+fail1: -+ kfree(saa716x); -+fail0: -+ return err; -+} -+ -+static void saa716x_hybrid_pci_remove(struct pci_dev *pdev) -+{ -+ struct saa716x_dev *saa716x = pci_get_drvdata(pdev); -+ -+ saa716x_dvb_exit(saa716x); -+ saa716x_i2c_exit(saa716x); -+ saa716x_pci_exit(saa716x); -+ kfree(saa716x); -+} -+ -+static irqreturn_t saa716x_hybrid_pci_irq(int irq, void *dev_id) -+{ -+ struct saa716x_dev *saa716x = (struct saa716x_dev *) dev_id; -+ -+ u32 stat_h, stat_l, mask_h, mask_l; -+ -+ if (unlikely(saa716x == NULL)) { -+ printk("%s: saa716x=NULL", __func__); -+ return IRQ_NONE; -+ } -+ -+ stat_l = SAA716x_EPRD(MSI, MSI_INT_STATUS_L); -+ stat_h = SAA716x_EPRD(MSI, MSI_INT_STATUS_H); -+ mask_l = SAA716x_EPRD(MSI, MSI_INT_ENA_L); -+ mask_h = SAA716x_EPRD(MSI, MSI_INT_ENA_H); -+ -+ dprintk(SAA716x_DEBUG, 1, "MSI STAT L=<%02x> H=<%02x>, CTL L=<%02x> H=<%02x>", -+ stat_l, stat_h, mask_l, mask_h); -+ -+ if (!((stat_l & mask_l) || (stat_h & mask_h))) -+ return IRQ_NONE; -+ -+ if (stat_l) -+ SAA716x_EPWR(MSI, MSI_INT_STATUS_CLR_L, stat_l); -+ -+ if (stat_h) -+ SAA716x_EPWR(MSI, MSI_INT_STATUS_CLR_H, stat_h); -+ -+ saa716x_msi_event(saa716x, stat_l, stat_h); -+#if 0 -+ dprintk(SAA716x_DEBUG, 1, "VI STAT 0=<%02x> 1=<%02x>, CTL 1=<%02x> 2=<%02x>", -+ SAA716x_EPRD(VI0, INT_STATUS), -+ SAA716x_EPRD(VI1, INT_STATUS), -+ SAA716x_EPRD(VI0, INT_ENABLE), -+ SAA716x_EPRD(VI1, INT_ENABLE)); -+ -+ dprintk(SAA716x_DEBUG, 1, "FGPI STAT 0=<%02x> 1=<%02x>, CTL 1=<%02x> 2=<%02x>", -+ SAA716x_EPRD(FGPI0, INT_STATUS), -+ SAA716x_EPRD(FGPI1, INT_STATUS), -+ SAA716x_EPRD(FGPI0, INT_ENABLE), -+ SAA716x_EPRD(FGPI0, INT_ENABLE)); -+ -+ dprintk(SAA716x_DEBUG, 1, "FGPI STAT 2=<%02x> 3=<%02x>, CTL 2=<%02x> 3=<%02x>", -+ SAA716x_EPRD(FGPI2, INT_STATUS), -+ SAA716x_EPRD(FGPI3, INT_STATUS), -+ SAA716x_EPRD(FGPI2, INT_ENABLE), -+ SAA716x_EPRD(FGPI3, INT_ENABLE)); -+ -+ dprintk(SAA716x_DEBUG, 1, "AI STAT 0=<%02x> 1=<%02x>, CTL 0=<%02x> 1=<%02x>", -+ SAA716x_EPRD(AI0, AI_STATUS), -+ SAA716x_EPRD(AI1, AI_STATUS), -+ SAA716x_EPRD(AI0, AI_CTL), -+ SAA716x_EPRD(AI1, AI_CTL)); -+ -+ dprintk(SAA716x_DEBUG, 1, "I2C STAT 0=<%02x> 1=<%02x>, CTL 0=<%02x> 1=<%02x>", -+ SAA716x_EPRD(I2C_A, INT_STATUS), -+ SAA716x_EPRD(I2C_B, INT_STATUS), -+ SAA716x_EPRD(I2C_A, INT_ENABLE), -+ SAA716x_EPRD(I2C_B, INT_ENABLE)); -+ -+ dprintk(SAA716x_DEBUG, 1, "DCS STAT=<%02x>, CTL=<%02x>", -+ SAA716x_EPRD(DCS, DCSC_INT_STATUS), -+ SAA716x_EPRD(DCS, DCSC_INT_ENABLE)); -+#endif -+ -+ if (stat_l) { -+ if (stat_l & MSI_INT_TAGACK_FGPI_0) { -+ tasklet_schedule(&saa716x->fgpi[0].tasklet); -+ } -+ if (stat_l & MSI_INT_TAGACK_FGPI_1) { -+ tasklet_schedule(&saa716x->fgpi[1].tasklet); -+ } -+ if (stat_l & MSI_INT_TAGACK_FGPI_2) { -+ tasklet_schedule(&saa716x->fgpi[2].tasklet); -+ } -+ if (stat_l & MSI_INT_TAGACK_FGPI_3) { -+ tasklet_schedule(&saa716x->fgpi[3].tasklet); -+ } -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static void demux_worker(unsigned long data) -+{ -+ struct saa716x_fgpi_stream_port *fgpi_entry = (struct saa716x_fgpi_stream_port *)data; -+ struct saa716x_dev *saa716x = fgpi_entry->saa716x; -+ struct dvb_demux *demux; -+ u32 fgpi_index; -+ u32 i; -+ u32 write_index; -+ -+ fgpi_index = fgpi_entry->dma_channel - 6; -+ demux = NULL; -+ for (i = 0; i < saa716x->config->adapters; i++) { -+ if (saa716x->config->adap_config[i].ts_port == fgpi_index) { -+ demux = &saa716x->saa716x_adap[i].demux; -+ break; -+ } -+ } -+ if (demux == NULL) { -+ printk(KERN_ERR "%s: unexpected channel %u\n", -+ __func__, fgpi_entry->dma_channel); -+ return; -+ } -+ -+ write_index = saa716x_fgpi_get_write_index(saa716x, fgpi_index); -+ if (write_index < 0) -+ return; -+ -+ dprintk(SAA716x_DEBUG, 1, "dma buffer = %d", write_index); -+ -+ if (write_index == fgpi_entry->read_index) { -+ printk(KERN_DEBUG "%s: called but nothing to do\n", __func__); -+ return; -+ } -+ -+ do { -+ u8 *data = (u8 *)fgpi_entry->dma_buf[fgpi_entry->read_index].mem_virt; -+ -+ pci_dma_sync_sg_for_cpu(saa716x->pdev, -+ fgpi_entry->dma_buf[fgpi_entry->read_index].sg_list, -+ fgpi_entry->dma_buf[fgpi_entry->read_index].list_len, -+ PCI_DMA_FROMDEVICE); -+ -+ dvb_dmx_swfilter(demux, data, 348 * 188); -+ -+ fgpi_entry->read_index = (fgpi_entry->read_index + 1) & 7; -+ } while (write_index != fgpi_entry->read_index); -+} -+ -+/* -+ * Twinhan/Azurewave VP-6090 -+ * DVB-S Frontend: 2x MB86A16 -+ * DVB-T Frontend: 2x TDA10046 + TDA8275 -+ */ -+#define SAA716x_MODEL_TWINHAN_VP6090 "Twinhan/Azurewave VP-6090" -+#define SAA716x_DEV_TWINHAN_VP6090 "2xDVB-S + 2xDVB-T + 2xAnalog" -+ -+static int tda1004x_vp6090_request_firmware(struct dvb_frontend *fe, -+ const struct firmware **fw, -+ char *name) -+{ -+ struct saa716x_adapter *adapter = fe->dvb->priv; -+ -+ return request_firmware(fw, name, &adapter->saa716x->pdev->dev); -+} -+ -+static struct tda1004x_config tda1004x_vp6090_config = { -+ .demod_address = 0x8, -+ .invert = 0, -+ .invert_oclk = 0, -+ .xtal_freq = TDA10046_XTAL_4M, -+ .agc_config = TDA10046_AGC_DEFAULT, -+ .if_freq = TDA10046_FREQ_3617, -+ .request_firmware = tda1004x_vp6090_request_firmware, -+}; -+ -+static int vp6090_dvbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) -+{ -+ struct saa716x_dev *saa716x = fe->dvb->priv; -+ -+ switch (voltage) { -+ case SEC_VOLTAGE_13: -+ dprintk(SAA716x_ERROR, 1, "Polarization=[13V]"); -+ break; -+ case SEC_VOLTAGE_18: -+ dprintk(SAA716x_ERROR, 1, "Polarization=[18V]"); -+ break; -+ case SEC_VOLTAGE_OFF: -+ dprintk(SAA716x_ERROR, 1, "Frontend (dummy) POWERDOWN"); -+ break; -+ default: -+ dprintk(SAA716x_ERROR, 1, "Invalid = (%d)", (u32 ) voltage); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+struct mb86a16_config vp6090_mb86a16_config = { -+ .demod_address = 0x08, -+ .set_voltage = vp6090_dvbs_set_voltage, -+}; -+ -+static int saa716x_vp6090_frontend_attach(struct saa716x_adapter *adapter, int count) -+{ -+ struct saa716x_dev *saa716x = adapter->saa716x; -+ struct saa716x_i2c *i2c = &saa716x->i2c[count]; -+ -+ dprintk(SAA716x_ERROR, 1, "Adapter (%d) SAA716x frontend Init", count); -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) Device ID=%02x", count, saa716x->pdev->subsystem_device); -+ -+ dprintk(SAA716x_ERROR, 1, "Adapter (%d) Power ON", count); -+ -+ saa716x_gpio_set_output(saa716x, 11); -+ saa716x_gpio_set_output(saa716x, 10); -+ saa716x_gpio_write(saa716x, 11, 1); -+ saa716x_gpio_write(saa716x, 10, 1); -+ msleep(100); -+#if 0 -+ dprintk(SAA716x_ERROR, 1, "Probing for MB86A16 (DVB-S/DSS)"); -+ adapter->fe = mb86a16_attach(&vp6090_mb86a16_config, &i2c->i2c_adapter); -+ if (adapter->fe) { -+ dprintk(SAA716x_ERROR, 1, "found MB86A16 DVB-S/DSS frontend @0x%02x", -+ vp6090_mb86a16_config.demod_address); -+ -+ } else { -+ goto exit; -+ } -+#endif -+ adapter->fe = tda10046_attach(&tda1004x_vp6090_config, &i2c->i2c_adapter); -+ if (adapter->fe == NULL) { -+ dprintk(SAA716x_ERROR, 1, "Frontend attach failed"); -+ return -ENODEV; -+ } else { -+ dprintk(SAA716x_ERROR, 1, "Done!"); -+ return 0; -+ } -+ -+ return 0; -+} -+ -+static struct saa716x_config saa716x_vp6090_config = { -+ .model_name = SAA716x_MODEL_TWINHAN_VP6090, -+ .dev_type = SAA716x_DEV_TWINHAN_VP6090, -+ .boot_mode = SAA716x_EXT_BOOT, -+ .adapters = 1, -+ .frontend_attach = saa716x_vp6090_frontend_attach, -+ .irq_handler = saa716x_hybrid_pci_irq, -+ .i2c_rate = SAA716x_I2C_RATE_100, -+}; -+ -+/* -+ * NXP Reference design (Atlantis) -+ * 2x DVB-T Frontend: 2x TDA10046 -+ * Analog Decoder: 2x Internal -+ */ -+#define SAA716x_MODEL_NXP_ATLANTIS "Atlantis reference board" -+#define SAA716x_DEV_NXP_ATLANTIS "2x DVB-T + 2x Analog" -+ -+static int tda1004x_atlantis_request_firmware(struct dvb_frontend *fe, -+ const struct firmware **fw, -+ char *name) -+{ -+ struct saa716x_adapter *adapter = fe->dvb->priv; -+ -+ return request_firmware(fw, name, &adapter->saa716x->pdev->dev); -+} -+ -+static struct tda1004x_config tda1004x_atlantis_config = { -+ .demod_address = 0x8, -+ .invert = 0, -+ .invert_oclk = 0, -+ .xtal_freq = TDA10046_XTAL_16M, -+ .agc_config = TDA10046_AGC_TDA827X, -+ .if_freq = TDA10046_FREQ_045, -+ .request_firmware = tda1004x_atlantis_request_firmware, -+ .tuner_address = 0x60, -+}; -+ -+static struct tda827x_config tda827x_atlantis_config = { -+ .init = NULL, -+ .sleep = NULL, -+ .config = 0, -+ .switch_addr = 0, -+ .agcf = NULL, -+}; -+ -+static int saa716x_atlantis_frontend_attach(struct saa716x_adapter *adapter, -+ int count) -+{ -+ struct saa716x_dev *saa716x = adapter->saa716x; -+ struct saa716x_i2c *i2c; -+ u8 i2c_buf[3] = { 0x05, 0x23, 0x01 }; /* activate the silent I2C bus */ -+ struct i2c_msg msg = { -+ .addr = 0x42 >> 1, -+ .flags = 0, -+ .buf = i2c_buf, -+ .len = sizeof(i2c_buf) -+ }; -+ -+ if (count < saa716x->config->adapters) { -+ u32 reset_gpio; -+ -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) SAA716x frontend Init", -+ count); -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) Device ID=%02x", count, -+ saa716x->pdev->subsystem_device); -+ -+ if (count == 0) { -+ reset_gpio = 14; -+ i2c = &saa716x->i2c[SAA716x_I2C_BUS_A]; -+ } else { -+ reset_gpio = 15; -+ i2c = &saa716x->i2c[SAA716x_I2C_BUS_B]; -+ } -+ -+ /* activate the silent I2C bus */ -+ i2c_transfer(&i2c->i2c_adapter, &msg, 1); -+ -+ saa716x_gpio_set_output(saa716x, reset_gpio); -+ -+ /* Reset the demodulator */ -+ saa716x_gpio_write(saa716x, reset_gpio, 1); -+ msleep(10); -+ saa716x_gpio_write(saa716x, reset_gpio, 0); -+ msleep(10); -+ saa716x_gpio_write(saa716x, reset_gpio, 1); -+ msleep(10); -+ -+ adapter->fe = tda10046_attach(&tda1004x_atlantis_config, -+ &i2c->i2c_adapter); -+ if (adapter->fe == NULL) -+ goto exit; -+ -+ dprintk(SAA716x_ERROR, 1, -+ "found TDA10046 DVB-T frontend @0x%02x", -+ tda1004x_atlantis_config.demod_address); -+ -+ if (dvb_attach(tda827x_attach, adapter->fe, -+ tda1004x_atlantis_config.tuner_address, -+ &i2c->i2c_adapter, &tda827x_atlantis_config)) { -+ dprintk(SAA716x_ERROR, 1, "found TDA8275 tuner @0x%02x", -+ tda1004x_atlantis_config.tuner_address); -+ } else { -+ goto exit; -+ } -+ -+ dprintk(SAA716x_ERROR, 1, "Done!"); -+ return 0; -+ } -+ -+exit: -+ dprintk(SAA716x_ERROR, 1, "Frontend attach failed"); -+ return -ENODEV; -+} -+ -+static struct saa716x_config saa716x_atlantis_config = { -+ .model_name = SAA716x_MODEL_NXP_ATLANTIS, -+ .dev_type = SAA716x_DEV_NXP_ATLANTIS, -+ .boot_mode = SAA716x_EXT_BOOT, -+ .adapters = 2, -+ .frontend_attach = saa716x_atlantis_frontend_attach, -+ .irq_handler = saa716x_hybrid_pci_irq, -+ .i2c_rate = SAA716x_I2C_RATE_100, -+ .adap_config = { -+ { -+ /* Adapter 0 */ -+ .ts_port = 3, /* using FGPI 3 */ -+ .worker = demux_worker -+ }, -+ { -+ /* Adapter 1 */ -+ .ts_port = 0, /* using FGPI 0 */ -+ .worker = demux_worker -+ } -+ } -+}; -+ -+/* -+ * NXP Reference design (NEMO) -+ * DVB-T Frontend: 1x TDA10046 + TDA8275 -+ * Analog Decoder: External SAA7136 -+ */ -+#define SAA716x_MODEL_NXP_NEMO "NEMO reference board" -+#define SAA716x_DEV_NXP_NEMO "DVB-T + Analog" -+ -+static int tda1004x_nemo_request_firmware(struct dvb_frontend *fe, -+ const struct firmware **fw, -+ char *name) -+{ -+ struct saa716x_adapter *adapter = fe->dvb->priv; -+ -+ return request_firmware(fw, name, &adapter->saa716x->pdev->dev); -+} -+ -+static struct tda1004x_config tda1004x_nemo_config = { -+ .demod_address = 0x8, -+ .invert = 0, -+ .invert_oclk = 0, -+ .xtal_freq = TDA10046_XTAL_16M, -+ .agc_config = TDA10046_AGC_TDA827X, -+ .if_freq = TDA10046_FREQ_045, -+ .request_firmware = tda1004x_nemo_request_firmware, -+ .tuner_address = 0x60, -+}; -+ -+static struct tda827x_config tda827x_nemo_config = { -+ .init = NULL, -+ .sleep = NULL, -+ .config = 0, -+ .switch_addr = 0, -+ .agcf = NULL, -+}; -+ -+static int saa716x_nemo_frontend_attach(struct saa716x_adapter *adapter, int count) -+{ -+ struct saa716x_dev *saa716x = adapter->saa716x; -+ struct saa716x_i2c *demod_i2c = &saa716x->i2c[SAA716x_I2C_BUS_B]; -+ struct saa716x_i2c *tuner_i2c = &saa716x->i2c[SAA716x_I2C_BUS_A]; -+ -+ -+ if (count == 0) { -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) SAA716x frontend Init", count); -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) Device ID=%02x", count, saa716x->pdev->subsystem_device); -+ dprintk(SAA716x_ERROR, 1, "Adapter (%d) Power ON", count); -+ -+ /* GPIO 26 controls a +15dB gain */ -+ saa716x_gpio_set_output(saa716x, 26); -+ saa716x_gpio_write(saa716x, 26, 0); -+ -+ saa716x_gpio_set_output(saa716x, 14); -+ -+ /* Reset the demodulator */ -+ saa716x_gpio_write(saa716x, 14, 1); -+ msleep(10); -+ saa716x_gpio_write(saa716x, 14, 0); -+ msleep(10); -+ saa716x_gpio_write(saa716x, 14, 1); -+ msleep(10); -+ -+ adapter->fe = tda10046_attach(&tda1004x_nemo_config, -+ &demod_i2c->i2c_adapter); -+ if (adapter->fe) { -+ dprintk(SAA716x_ERROR, 1, "found TDA10046 DVB-T frontend @0x%02x", -+ tda1004x_nemo_config.demod_address); -+ -+ } else { -+ goto exit; -+ } -+ if (dvb_attach(tda827x_attach, adapter->fe, -+ tda1004x_nemo_config.tuner_address, -+ &tuner_i2c->i2c_adapter, &tda827x_nemo_config)) { -+ dprintk(SAA716x_ERROR, 1, "found TDA8275 tuner @0x%02x", -+ tda1004x_nemo_config.tuner_address); -+ } else { -+ goto exit; -+ } -+ dprintk(SAA716x_ERROR, 1, "Done!"); -+ } -+ -+ return 0; -+exit: -+ dprintk(SAA716x_ERROR, 1, "Frontend attach failed"); -+ return -ENODEV; -+} -+ -+static struct saa716x_config saa716x_nemo_config = { -+ .model_name = SAA716x_MODEL_NXP_NEMO, -+ .dev_type = SAA716x_DEV_NXP_NEMO, -+ .boot_mode = SAA716x_EXT_BOOT, -+ .adapters = 1, -+ .frontend_attach = saa716x_nemo_frontend_attach, -+ .irq_handler = saa716x_hybrid_pci_irq, -+ .i2c_rate = SAA716x_I2C_RATE_100, -+ -+ .adap_config = { -+ { -+ /* Adapter 0 */ -+ .ts_port = 3, /* using FGPI 3 */ -+ .worker = demux_worker -+ } -+ } -+}; -+ -+ -+#define SAA716x_MODEL_AVERMEDIA_HC82 "Avermedia HC82 Express-54" -+#define SAA716x_DEV_AVERMEDIA_HC82 "DVB-T + Analog" -+ -+#if 0 -+static struct zl10353_config saa716x_averhc82_zl10353_config = { -+ .demod_address = 0x1f, -+ .adc_clock = 450560, -+ .if2 = 361667, -+ .no_tuner = 1, -+ .parallel_ts = 1, -+}; -+#endif -+ -+static int saa716x_averhc82_frontend_attach(struct saa716x_adapter *adapter, int count) -+{ -+ struct saa716x_dev *saa716x = adapter->saa716x; -+ -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) SAA716x frontend Init", count); -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) Device ID=%02x", count, saa716x->pdev->subsystem_device); -+ -+// adapter->fe = zl10353_attach(&saa716x_averhc82_zl10353_config, &i2c->i2c_adapter); -+ -+ -+ return 0; -+} -+ -+static struct saa716x_config saa716x_averhc82_config = { -+ .model_name = SAA716x_MODEL_AVERMEDIA_HC82, -+ .dev_type = SAA716x_DEV_AVERMEDIA_HC82, -+ .boot_mode = SAA716x_EXT_BOOT, -+ .adapters = 1, -+ .frontend_attach = saa716x_averhc82_frontend_attach, -+ .irq_handler = saa716x_hybrid_pci_irq, -+ .i2c_rate = SAA716x_I2C_RATE_100, -+}; -+ -+#define SAA716x_MODEL_AVERMEDIA_H788 "Avermedia H788" -+#define SAA716x_DEV_AVERMEDIA_H788 "DVB-T + Analaog" -+ -+static int saa716x_averh88_frontend_attach(struct saa716x_adapter *adapter, int count) -+{ -+ struct saa716x_dev *saa716x = adapter->saa716x; -+ -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) SAA716x frontend Init", count); -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%d) Device ID=%02x", count, saa716x->pdev->subsystem_device); -+ -+ return -ENODEV; -+} -+ -+static struct saa716x_config saa716x_averh788_config = { -+ .model_name = SAA716x_MODEL_AVERMEDIA_H788, -+ .dev_type = SAA716x_DEV_AVERMEDIA_H788, -+ .boot_mode = SAA716x_EXT_BOOT, -+ .adapters = 1, -+ .frontend_attach = saa716x_averh88_frontend_attach, -+ .irq_handler = saa716x_hybrid_pci_irq, -+ .i2c_rate = SAA716x_I2C_RATE_100, -+}; -+ -+static struct pci_device_id saa716x_hybrid_pci_table[] = { -+ -+ MAKE_ENTRY(TWINHAN_TECHNOLOGIES, TWINHAN_VP_6090, SAA7162, &saa716x_vp6090_config), -+ MAKE_ENTRY(AVERMEDIA, AVERMEDIA_HC82, SAA7160, &saa716x_averhc82_config), -+ MAKE_ENTRY(AVERMEDIA, AVERMEDIA_H788, SAA7160, &saa716x_averh788_config), -+ MAKE_ENTRY(KWORLD, KWORLD_DVB_T_PE310, SAA7162, &saa716x_atlantis_config), -+ MAKE_ENTRY(NXP_REFERENCE_BOARD, PCI_ANY_ID, SAA7162, &saa716x_atlantis_config), -+ MAKE_ENTRY(NXP_REFERENCE_BOARD, PCI_ANY_ID, SAA7160, &saa716x_nemo_config), -+ { } -+}; -+MODULE_DEVICE_TABLE(pci, saa716x_hybrid_pci_table); -+ -+static struct pci_driver saa716x_hybrid_pci_driver = { -+ .name = DRIVER_NAME, -+ .id_table = saa716x_hybrid_pci_table, -+ .probe = saa716x_hybrid_pci_probe, -+ .remove = saa716x_hybrid_pci_remove, -+}; -+ -+static int saa716x_hybrid_init(void) -+{ -+ return pci_register_driver(&saa716x_hybrid_pci_driver); -+} -+ -+static void saa716x_hybrid_exit(void) -+{ -+ return pci_unregister_driver(&saa716x_hybrid_pci_driver); -+} -+ -+module_init(saa716x_hybrid_init); -+module_exit(saa716x_hybrid_exit); -+ -+MODULE_DESCRIPTION("SAA716x Hybrid driver"); -+MODULE_AUTHOR("Manu Abraham"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/media/common/saa716x/saa716x_hybrid.h b/drivers/media/common/saa716x/saa716x_hybrid.h -new file mode 100644 -index 0000000..df34a59 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_hybrid.h -@@ -0,0 +1,13 @@ -+#ifndef __SAA716x_HYBRID_H -+#define __SAA716x_HYBRID_H -+ -+#define TWINHAN_TECHNOLOGIES 0x1822 -+#define AVERMEDIA 0x1461 -+#define KWORLD 0x17DE -+ -+#define TWINHAN_VP_6090 0x0027 -+#define AVERMEDIA_HC82 0x2355 -+#define AVERMEDIA_H788 0x1455 -+#define KWORLD_DVB_T_PE310 0x7521 -+ -+#endif /* __SAA716x_HYBRID_H */ -diff --git a/drivers/media/common/saa716x/saa716x_i2c.c b/drivers/media/common/saa716x/saa716x_i2c.c -new file mode 100644 -index 0000000..91a091d ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_i2c.c -@@ -0,0 +1,734 @@ -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#include "saa716x_mod.h" -+ -+#include "saa716x_i2c_reg.h" -+#include "saa716x_msi_reg.h" -+#include "saa716x_cgu_reg.h" -+ -+#include "saa716x_i2c.h" -+#include "saa716x_msi.h" -+#include "saa716x_spi.h" -+#include "saa716x_priv.h" -+ -+#define SAA716x_I2C_TXFAIL (I2C_ERROR_IBE | \ -+ I2C_ACK_INTER_MTNA | \ -+ I2C_FAILURE_INTER_MAF) -+ -+#define SAA716x_I2C_TXBUSY (I2C_TRANSMIT | \ -+ I2C_TRANSMIT_PROG) -+ -+#define SAA716x_I2C_RXBUSY (I2C_RECEIVE | \ -+ I2C_RECEIVE_CLEAR) -+ -+static const char* state[] = { -+ "Idle", -+ "DoneStop", -+ "Busy", -+ "TOscl", -+ "TOarb", -+ "DoneWrite", -+ "DoneRead", -+ "DoneWriteTO", -+ "DoneReadTO", -+ "NoDevice", -+ "NoACK", -+ "BUSErr", -+ "ArbLost", -+ "SEQErr", -+ "STErr" -+}; -+ -+int saa716x_i2c_irqevent(struct saa716x_dev *saa716x, u8 bus) -+{ -+ u32 stat, mask; -+ u32 *I2C_DEV; -+ -+ BUG_ON(saa716x == NULL); -+ I2C_DEV = saa716x->I2C_DEV; -+ -+ stat = SAA716x_EPRD(I2C_DEV[bus], INT_STATUS); -+ mask = SAA716x_EPRD(I2C_DEV[bus], INT_ENABLE); -+ saa716x->i2c[bus].i2c_stat = stat; -+ dprintk(SAA716x_DEBUG, 0, "Bus(%d) I2C event: Status=<%s> --> Stat=<%02x> Mask=<%02x>", -+ bus, state[stat], stat, mask); -+ -+ if (!(stat & mask)) -+ return -1; -+ -+ SAA716x_EPWR(I2C_DEV[bus], INT_CLR_STATUS, stat); -+ -+ if (stat & I2C_INTERRUPT_STFNF) -+ dprintk(SAA716x_DEBUG, 0, " "); -+ -+ if (stat & I2C_INTERRUPT_MTFNF) { -+ dprintk(SAA716x_DEBUG, 0, " "); -+ } -+ -+ if (stat & I2C_INTERRUPT_RFDA) -+ dprintk(SAA716x_DEBUG, 0, " "); -+ -+ if (stat & I2C_INTERRUPTE_RFF) -+ dprintk(SAA716x_DEBUG, 0, " "); -+ -+ if (stat & I2C_SLAVE_INTERRUPT_STDR) -+ dprintk(SAA716x_DEBUG, 0, " "); -+ -+ if (stat & I2C_MASTER_INTERRUPT_MTDR) { -+ dprintk(SAA716x_DEBUG, 0, " "); -+ } -+ -+ if (stat & I2C_ERROR_IBE) -+ dprintk(SAA716x_DEBUG, 0, " "); -+ -+ if (stat & I2C_MODE_CHANGE_INTER_MSMC) -+ dprintk(SAA716x_DEBUG, 0, " "); -+ -+ if (stat & I2C_SLAVE_RECEIVE_INTER_SRSD) -+ dprintk(SAA716x_DEBUG, 0, " "); -+ -+ if (stat & I2C_SLAVE_TRANSMIT_INTER_STSD) -+ dprintk(SAA716x_DEBUG, 0, " "); -+ -+ if (stat & I2C_ACK_INTER_MTNA) -+ dprintk(SAA716x_DEBUG, 0, " "); -+ -+ if (stat & I2C_FAILURE_INTER_MAF) -+ dprintk(SAA716x_DEBUG, 0, " "); -+ -+ if (stat & I2C_INTERRUPT_MTD) -+ dprintk(SAA716x_DEBUG, 0, " "); -+ -+ return 0; -+} -+ -+static irqreturn_t saa716x_i2c_irq(int irq, void *dev_id) -+{ -+ struct saa716x_dev *saa716x = (struct saa716x_dev *) dev_id; -+ -+ if (unlikely(saa716x == NULL)) { -+ printk("%s: saa716x=NULL", __func__); -+ return IRQ_NONE; -+ } -+ dprintk(SAA716x_DEBUG, 1, "MSI STAT L=<%02x> H=<%02x>, CTL L=<%02x> H=<%02x>", -+ SAA716x_EPRD(MSI, MSI_INT_STATUS_L), -+ SAA716x_EPRD(MSI, MSI_INT_STATUS_H), -+ SAA716x_EPRD(MSI, MSI_INT_ENA_L), -+ SAA716x_EPRD(MSI, MSI_INT_ENA_H)); -+ -+ dprintk(SAA716x_DEBUG, 1, "I2C STAT 0=<%02x> 1=<%02x>, CTL 0=<%02x> 1=<%02x>", -+ SAA716x_EPRD(I2C_A, INT_STATUS), -+ SAA716x_EPRD(I2C_B, INT_STATUS), -+ SAA716x_EPRD(I2C_A, INT_CLR_STATUS), -+ SAA716x_EPRD(I2C_B, INT_CLR_STATUS)); -+ -+ return IRQ_HANDLED; -+} -+ -+static void saa716x_term_xfer(struct saa716x_i2c *i2c, u32 I2C_DEV) -+{ -+ struct saa716x_dev *saa716x = i2c->saa716x; -+ -+ SAA716x_EPWR(I2C_DEV, I2C_CONTROL, 0xc0); /* Start: SCL/SDA High */ -+ msleep(10); -+ SAA716x_EPWR(I2C_DEV, I2C_CONTROL, 0x80); -+ msleep(10); -+ SAA716x_EPWR(I2C_DEV, I2C_CONTROL, 0x00); -+ msleep(10); -+ SAA716x_EPWR(I2C_DEV, I2C_CONTROL, 0x80); -+ msleep(10); -+ SAA716x_EPWR(I2C_DEV, I2C_CONTROL, 0xc0); -+ -+ return; -+} -+ -+static void saa716x_i2c_hwdeinit(struct saa716x_i2c *i2c, u32 I2C_DEV) -+{ -+ struct saa716x_dev *saa716x = i2c->saa716x; -+ -+ /* Disable all interrupts and clear status */ -+ SAA716x_EPWR(I2C_DEV, INT_CLR_ENABLE, 0x1fff); -+ SAA716x_EPWR(I2C_DEV, INT_CLR_STATUS, 0x1fff); -+} -+ -+static int saa716x_i2c_hwinit(struct saa716x_i2c *i2c, u32 I2C_DEV) -+{ -+ struct saa716x_dev *saa716x = i2c->saa716x; -+ struct i2c_adapter *adapter = &i2c->i2c_adapter; -+ -+ int i, err = 0; -+ u32 reg; -+ -+ reg = SAA716x_EPRD(I2C_DEV, I2C_STATUS); -+ if (!(reg & 0xd)) { -+ dprintk(SAA716x_ERROR, 1, "Adapter (%02x) %s RESET failed, Exiting !", -+ I2C_DEV, adapter->name); -+ err = -EIO; -+ goto exit; -+ } -+ -+ /* Flush queue */ -+ SAA716x_EPWR(I2C_DEV, I2C_CONTROL, 0xcc); -+ -+ /* Disable all interrupts and clear status */ -+ SAA716x_EPWR(I2C_DEV, INT_CLR_ENABLE, 0x1fff); -+ SAA716x_EPWR(I2C_DEV, INT_CLR_STATUS, 0x1fff); -+ -+ /* Reset I2C Core and generate a delay */ -+ SAA716x_EPWR(I2C_DEV, I2C_CONTROL, 0xc1); -+ -+ for (i = 0; i < 100; i++) { -+ reg = SAA716x_EPRD(I2C_DEV, I2C_CONTROL); -+ if (reg == 0xc0) { -+ dprintk(SAA716x_ERROR, 1, "Adapter (%02x) %s RESET", -+ I2C_DEV, adapter->name); -+ break; -+ } -+ msleep(1); -+ -+ if (i == 99) -+ err = -EIO; -+ } -+ -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "Adapter (%02x) %s RESET failed", -+ I2C_DEV, adapter->name); -+ -+ saa716x_term_xfer(i2c, I2C_DEV); -+ err = -EIO; -+ goto exit; -+ } -+ -+ /* I2C Rate Setup */ -+ switch (i2c->i2c_rate) { -+ case SAA716x_I2C_RATE_400: -+ -+ dprintk(SAA716x_DEBUG, 1, "Initializing Adapter %s @ 400k", adapter->name); -+ SAA716x_EPWR(I2C_DEV, I2C_CLOCK_DIVISOR_HIGH, 0x1a); /* 0.5 * 27MHz/400kHz */ -+ SAA716x_EPWR(I2C_DEV, I2C_CLOCK_DIVISOR_LOW, 0x21); /* 0.5 * 27MHz/400kHz */ -+ SAA716x_EPWR(I2C_DEV, I2C_SDA_HOLD, 0x19); -+ break; -+ -+ case SAA716x_I2C_RATE_100: -+ -+ dprintk(SAA716x_DEBUG, 1, "Initializing Adapter %s @ 100k", adapter->name); -+ SAA716x_EPWR(I2C_DEV, I2C_CLOCK_DIVISOR_HIGH, 0x68); /* 0.5 * 27MHz/100kHz */ -+ SAA716x_EPWR(I2C_DEV, I2C_CLOCK_DIVISOR_LOW, 0x87); /* 0.5 * 27MHz/100kHz */ -+ SAA716x_EPWR(I2C_DEV, I2C_SDA_HOLD, 0x60); -+ break; -+ -+ default: -+ -+ dprintk(SAA716x_ERROR, 1, "Adapter %s Unknown Rate (Rate=0x%02x)", -+ adapter->name, -+ i2c->i2c_rate); -+ -+ break; -+ } -+ -+ /* Disable all interrupts and clear status */ -+ SAA716x_EPWR(I2C_DEV, INT_CLR_ENABLE, 0x1fff); -+ SAA716x_EPWR(I2C_DEV, INT_CLR_STATUS, 0x1fff); -+ -+ if (i2c->i2c_mode >= SAA716x_I2C_MODE_IRQ) { -+ /* Enabled interrupts: -+ * Master Transaction Done, -+ * Master Transaction Data Request -+ * (0x81) -+ */ -+ msleep(5); -+ -+ SAA716x_EPWR(I2C_DEV, INT_SET_ENABLE, -+ I2C_SET_ENABLE_MTDR | I2C_SET_ENABLE_MTD); -+ -+ /* Check interrupt enable status */ -+ reg = SAA716x_EPRD(I2C_DEV, INT_ENABLE); -+ if (reg != 0x81) { -+ -+ dprintk(SAA716x_ERROR, 1, -+ "Adapter (%d) %s Interrupt enable failed, Exiting !", -+ i, -+ adapter->name); -+ -+ err = -EIO; -+ goto exit; -+ } -+ } -+ -+ /* Check status */ -+ reg = SAA716x_EPRD(I2C_DEV, I2C_STATUS); -+ if (!(reg & 0xd)) { -+ -+ dprintk(SAA716x_ERROR, 1, -+ "Adapter (%02x) %s has bad state, Exiting !", -+ I2C_DEV, -+ adapter->name); -+ -+ err = -EIO; -+ goto exit; -+ } -+#if 0 -+ saa716x_add_irqvector(saa716x, -+ i2c_vec[i].vector, -+ i2c_vec[i].edge, -+ i2c_vec[i].handler, -+ SAA716x_I2C_ADAPTER(i)); -+#endif -+ reg = SAA716x_EPRD(CGU, CGU_SCR_3); -+ dprintk(SAA716x_DEBUG, 1, "Adapter (%02x) Autowake <%d> Active <%d>", -+ I2C_DEV, -+ (reg >> 1) & 0x01, -+ reg & 0x01); -+ -+ return 0; -+exit: -+ return err; -+} -+ -+static int saa716x_i2c_send(struct saa716x_i2c *i2c, u32 I2C_DEV, u32 data) -+{ -+ struct saa716x_dev *saa716x = i2c->saa716x; -+ int i, err = 0; -+ u32 reg; -+ -+ if (i2c->i2c_mode >= SAA716x_I2C_MODE_IRQ) { -+ /* Write to FIFO */ -+ SAA716x_EPWR(I2C_DEV, TX_FIFO, data); -+ return 0; -+ } -+ -+ /* Check FIFO status before TX */ -+ reg = SAA716x_EPRD(I2C_DEV, I2C_STATUS); -+ i2c->stat_tx_prior = reg; -+ if (reg & SAA716x_I2C_TXBUSY) { -+ for (i = 0; i < 100; i++) { -+ /* TODO! check for hotplug devices */ -+ msleep(10); -+ reg = SAA716x_EPRD(I2C_DEV, I2C_STATUS); -+ -+ if (reg & SAA716x_I2C_TXBUSY) { -+ dprintk(SAA716x_ERROR, 1, "FIFO full or Blocked"); -+ -+ err = saa716x_i2c_hwinit(i2c, I2C_DEV); -+ if (err < 0) { -+ dprintk(SAA716x_ERROR, 1, "Error Reinit"); -+ err = -EIO; -+ goto exit; -+ } -+ } else { -+ break; -+ } -+ } -+ } -+ -+ /* Write to FIFO */ -+ SAA716x_EPWR(I2C_DEV, TX_FIFO, data); -+ -+ /* Check for data write */ -+ for (i = 0; i < 1000; i++) { -+ /* TODO! check for hotplug devices */ -+ reg = SAA716x_EPRD(I2C_DEV, I2C_STATUS); -+ if (reg & I2C_TRANSMIT_CLEAR) { -+ break; -+ } -+ } -+ i2c->stat_tx_done = reg; -+ -+ if (!(reg & I2C_TRANSMIT_CLEAR)) { -+ dprintk(SAA716x_ERROR, 1, "TXFIFO not empty after Timeout, tried %d loops!", i); -+ err = -EIO; -+ goto exit; -+ } -+ -+ return err; -+ -+exit: -+ dprintk(SAA716x_ERROR, 1, "I2C Send failed (Err=%d)", err); -+ return err; -+} -+ -+static int saa716x_i2c_recv(struct saa716x_i2c *i2c, u32 I2C_DEV, u32 *data) -+{ -+ struct saa716x_dev *saa716x = i2c->saa716x; -+ int i, err = 0; -+ u32 reg; -+ -+ /* Check FIFO status before RX */ -+ for (i = 0; i < 1000; i++) { -+ reg = SAA716x_EPRD(I2C_DEV, I2C_STATUS); -+ if (!(reg & SAA716x_I2C_RXBUSY)) { -+ break; -+ } -+ } -+ if (reg & SAA716x_I2C_RXBUSY) { -+ dprintk(SAA716x_INFO, 1, "FIFO empty"); -+ err = -EIO; -+ goto exit; -+ } -+ -+ /* Read from FIFO */ -+ *data = SAA716x_EPRD(I2C_DEV, RX_FIFO); -+ -+ return 0; -+exit: -+ dprintk(SAA716x_ERROR, 1, "Error Reading data, err=%d", err); -+ return err; -+} -+ -+static void saa716x_i2c_irq_start(struct saa716x_i2c *i2c, u32 I2C_DEV) -+{ -+ struct saa716x_dev *saa716x = i2c->saa716x; -+ -+ if (i2c->i2c_mode == SAA716x_I2C_MODE_POLLING) -+ return; -+ -+ i2c->i2c_op = 1; -+ SAA716x_EPWR(I2C_DEV, INT_CLR_STATUS, 0x1fff); -+} -+ -+static int saa716x_i2c_irq_wait(struct saa716x_i2c *i2c, u32 I2C_DEV) -+{ -+ struct saa716x_dev *saa716x = i2c->saa716x; -+ unsigned long timeout; -+ int err = 0; -+ -+ if (i2c->i2c_mode == SAA716x_I2C_MODE_POLLING) -+ return 0; -+ -+ timeout = HZ/100 + 1; /* 10ms */ -+ timeout = wait_event_interruptible_timeout(i2c->i2c_wq, i2c->i2c_op == 0, timeout); -+ if (timeout == -ERESTARTSYS || i2c->i2c_op) { -+ SAA716x_EPWR(I2C_DEV, INT_CLR_STATUS, 0x1fff); -+ if (timeout == -ERESTARTSYS) { -+ /* a signal arrived */ -+ err = -ERESTARTSYS; -+ } else { -+ dprintk(SAA716x_ERROR, 1, "timed out waiting for end of xfer!"); -+ err = -EIO; -+ } -+ } -+ return err; -+} -+ -+static int saa716x_i2c_write_msg(struct saa716x_i2c *i2c, u32 I2C_DEV, -+ u16 addr, u8 *buf, u16 len, u8 add_stop) -+{ -+ struct saa716x_dev *saa716x = i2c->saa716x; -+ u32 data; -+ int err; -+ int i; -+ int bytes; -+ -+ saa716x_i2c_irq_start(i2c, I2C_DEV); -+ -+ /* first write START with I2C address */ -+ data = I2C_START_BIT | (addr << 1); -+ dprintk(SAA716x_DEBUG, 1, "length=%d Addr:0x%02x", len, data); -+ err = saa716x_i2c_send(i2c, I2C_DEV, data); -+ if (err < 0) { -+ dprintk(SAA716x_ERROR, 1, "Address write failed"); -+ goto exit; -+ } -+ -+ bytes = i2c->block_size - 1; -+ -+ /* now write the data */ -+ while (len > 0) { -+ if (bytes == i2c->block_size) { -+ /* this is not the first round, so restart irq */ -+ saa716x_i2c_irq_start(i2c, I2C_DEV); -+ } -+ -+ if (bytes > len) -+ bytes = len; -+ -+ for (i = 0; i < bytes; i++) { -+ data = buf[i]; -+ dprintk(SAA716x_DEBUG, 0, " 0x%02x\n", i, data); -+ if (add_stop && i == (len - 1)) -+ data |= I2C_STOP_BIT; -+ err = saa716x_i2c_send(i2c, I2C_DEV, data); -+ if (err < 0) { -+ dprintk(SAA716x_ERROR, 1, "Data send failed"); -+ goto exit; -+ } -+ } -+ -+ err = saa716x_i2c_irq_wait(i2c, I2C_DEV); -+ if (err < 0) { -+ goto exit; -+ } -+ -+ len -= bytes; -+ buf += bytes; -+ bytes = i2c->block_size; -+ } -+ -+ return 0; -+ -+exit: -+ dprintk(SAA716x_ERROR, 1, "Error writing data, err=%d", err); -+ return err; -+} -+ -+static int saa716x_i2c_read_msg(struct saa716x_i2c *i2c, u32 I2C_DEV, -+ u16 addr, u8 *buf, u16 len, u8 add_stop) -+{ -+ struct saa716x_dev *saa716x = i2c->saa716x; -+ u32 data; -+ int err; -+ int i; -+ int bytes; -+ -+ saa716x_i2c_irq_start(i2c, I2C_DEV); -+ -+ /* first write START with I2C address */ -+ data = I2C_START_BIT | (addr << 1) | 1; -+ dprintk(SAA716x_DEBUG, 1, "length=%d Addr:0x%02x", len, data); -+ err = saa716x_i2c_send(i2c, I2C_DEV, data); -+ if (err < 0) { -+ dprintk(SAA716x_ERROR, 1, "Address write failed"); -+ goto exit; -+ } -+ -+ bytes = i2c->block_size - 1; -+ -+ /* now read the data */ -+ while (len > 0) { -+ if (bytes == i2c->block_size) { -+ /* this is not the first round, so restart irq */ -+ saa716x_i2c_irq_start(i2c, I2C_DEV); -+ } -+ -+ if (bytes > len) -+ bytes = len; -+ -+ for (i = 0; i < bytes; i++) { -+ data = 0x00; /* dummy write for reading */ -+ if (add_stop && i == (len - 1)) -+ data |= I2C_STOP_BIT; -+ err = saa716x_i2c_send(i2c, I2C_DEV, data); -+ if (err < 0) { -+ dprintk(SAA716x_ERROR, 1, "Data send failed"); -+ goto exit; -+ } -+ } -+ -+ err = saa716x_i2c_irq_wait(i2c, I2C_DEV); -+ if (err < 0) { -+ goto exit; -+ } -+ -+ for (i = 0; i < bytes; i++) { -+ err = saa716x_i2c_recv(i2c, I2C_DEV, &data); -+ if (err < 0) { -+ dprintk(SAA716x_ERROR, 1, "Data receive failed"); -+ goto exit; -+ } -+ dprintk(SAA716x_DEBUG, 0, " 0x%02x\n\n", i, data); -+ buf[i] = data; -+ } -+ -+ len -= bytes; -+ buf += bytes; -+ bytes = i2c->block_size; -+ } -+ -+ return 0; -+ -+exit: -+ dprintk(SAA716x_ERROR, 1, "Error reading data, err=%d", err); -+ return err; -+} -+ -+static int saa716x_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) -+{ -+ struct saa716x_i2c *i2c = i2c_get_adapdata(adapter); -+ struct saa716x_dev *saa716x = i2c->saa716x; -+ -+ u32 DEV = SAA716x_I2C_BUS(i2c->i2c_dev); -+ int i, j, err = 0; -+ int t; -+ -+ dprintk(SAA716x_DEBUG, 0, "\n"); -+ dprintk(SAA716x_DEBUG, 1, "Bus(%02x) I2C transfer", DEV); -+ mutex_lock(&i2c->i2c_lock); -+ -+ for (t = 0; t < 3; t++) { -+ for (i = 0; i < num; i++) { -+ if (msgs[i].flags & I2C_M_RD) -+ err = saa716x_i2c_read_msg(i2c, DEV, -+ msgs[i].addr, msgs[i].buf, msgs[i].len, -+ i == (num - 1)); -+ else -+ err = saa716x_i2c_write_msg(i2c, DEV, -+ msgs[i].addr, msgs[i].buf, msgs[i].len, -+ i == (num - 1)); -+ if (err < 0) { -+ err = -EIO; -+ goto retry; -+ } -+ } -+ break; -+retry: -+ dprintk(SAA716x_INFO, 1, "Error in Transfer, try %d", t); -+ for (i = 0; i < num; i++) { -+ dprintk(SAA716x_INFO, 1, "msg %d, addr = 0x%02x, len=%d, flags=0x%x", -+ i, msgs[i].addr, msgs[i].len, msgs[i].flags); -+ if (!(msgs[i].flags & I2C_M_RD)) { -+ for (j = 0; j < msgs[i].len; j++) { -+ dprintk(SAA716x_INFO, 1, " 0x%02x", -+ j, msgs[i].buf[j]); -+ } -+ } -+ } -+ err = saa716x_i2c_hwinit(i2c, DEV); -+ if (err < 0) { -+ dprintk(SAA716x_ERROR, 1, "Error Reinit"); -+ err = -EIO; -+ goto bail_out; -+ } -+ } -+ -+ mutex_unlock(&i2c->i2c_lock); -+ return num; -+ -+bail_out: -+ dprintk(SAA716x_ERROR, 1, "ERROR: Bailing out <%d>", err); -+ mutex_unlock(&i2c->i2c_lock); -+ return err; -+} -+ -+static u32 saa716x_i2c_func(struct i2c_adapter *adapter) -+{ -+ return I2C_FUNC_SMBUS_EMUL; -+} -+ -+static const struct i2c_algorithm saa716x_algo = { -+ .master_xfer = saa716x_i2c_xfer, -+ .functionality = saa716x_i2c_func, -+}; -+ -+struct saa716x_i2cvec { -+ u32 vector; -+ enum saa716x_edge edge; -+ irqreturn_t (*handler)(int irq, void *dev_id); -+}; -+ -+static const struct saa716x_i2cvec i2c_vec[] = { -+ { -+ .vector = I2CINT_0, -+ .edge = SAA716x_EDGE_RISING, -+ .handler = saa716x_i2c_irq -+ }, { -+ .vector = I2CINT_1, -+ .edge = SAA716x_EDGE_RISING, -+ .handler = saa716x_i2c_irq -+ } -+}; -+ -+int saa716x_i2c_init(struct saa716x_dev *saa716x) -+{ -+ struct pci_dev *pdev = saa716x->pdev; -+ struct saa716x_i2c *i2c = saa716x->i2c; -+ struct i2c_adapter *adapter = NULL; -+ -+ int i, err = 0; -+ -+ dprintk(SAA716x_DEBUG, 1, "Initializing SAA%02x I2C Core", -+ saa716x->pdev->device); -+ -+ for (i = 0; i < SAA716x_I2C_ADAPTERS; i++) { -+ -+ mutex_init(&i2c->i2c_lock); -+ -+ init_waitqueue_head(&i2c->i2c_wq); -+ i2c->i2c_op = 0; -+ -+ i2c->i2c_dev = i; -+ i2c->i2c_rate = saa716x->config->i2c_rate; -+ i2c->i2c_mode = saa716x->config->i2c_mode; -+ adapter = &i2c->i2c_adapter; -+ -+ if (i2c->i2c_mode == SAA716x_I2C_MODE_IRQ_BUFFERED) -+ i2c->block_size = 8; -+ else -+ i2c->block_size = 1; -+ -+ if (adapter != NULL) { -+ -+ i2c_set_adapdata(adapter, i2c); -+ -+ strcpy(adapter->name, SAA716x_I2C_ADAPTER(i)); -+ -+ adapter->owner = THIS_MODULE; -+ adapter->algo = &saa716x_algo; -+ adapter->algo_data = NULL; -+ adapter->timeout = 500; /* FIXME ! */ -+ adapter->retries = 3; /* FIXME ! */ -+ adapter->dev.parent = &pdev->dev; -+ -+ dprintk(SAA716x_DEBUG, 1, "Initializing adapter (%d) %s", -+ i, -+ adapter->name); -+ -+ err = i2c_add_adapter(adapter); -+ if (err < 0) { -+ dprintk(SAA716x_ERROR, 1, "Adapter (%d) %s init failed", i, adapter->name); -+ goto exit; -+ } -+ -+ i2c->saa716x = saa716x; -+ saa716x_i2c_hwinit(i2c, SAA716x_I2C_BUS(i)); -+ } -+ i2c++; -+ } -+ -+ if (saa716x->config->i2c_mode >= SAA716x_I2C_MODE_IRQ) { -+ SAA716x_EPWR(MSI, MSI_INT_ENA_SET_H, MSI_INT_I2CINT_0); -+ SAA716x_EPWR(MSI, MSI_INT_ENA_SET_H, MSI_INT_I2CINT_1); -+ } -+ -+ dprintk(SAA716x_DEBUG, 1, "SAA%02x I2C Core succesfully initialized", -+ saa716x->pdev->device); -+ -+ return 0; -+exit: -+ return err; -+} -+EXPORT_SYMBOL_GPL(saa716x_i2c_init); -+ -+int saa716x_i2c_exit(struct saa716x_dev *saa716x) -+{ -+ struct saa716x_i2c *i2c = saa716x->i2c; -+ struct i2c_adapter *adapter = NULL; -+ int i, err = 0; -+ -+ dprintk(SAA716x_DEBUG, 1, "Removing SAA%02x I2C Core", saa716x->pdev->device); -+ -+ for (i = 0; i < SAA716x_I2C_ADAPTERS; i++) { -+ -+ adapter = &i2c->i2c_adapter; -+#if 0 -+ saa716x_remove_irqvector(saa716x, i2c_vec[i].vector); -+#endif -+ saa716x_i2c_hwdeinit(i2c, SAA716x_I2C_BUS(i)); -+ dprintk(SAA716x_DEBUG, 1, "Removing adapter (%d) %s", i, adapter->name); -+ -+ i2c_del_adapter(adapter); -+ i2c++; -+ } -+ dprintk(SAA716x_DEBUG, 1, "SAA%02x I2C Core succesfully removed", saa716x->pdev->device); -+ -+ return 0; -+ -+exit: -+ return err; -+} -+EXPORT_SYMBOL_GPL(saa716x_i2c_exit); -diff --git a/drivers/media/common/saa716x/saa716x_i2c.h b/drivers/media/common/saa716x/saa716x_i2c.h -new file mode 100644 -index 0000000..da767ac ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_i2c.h -@@ -0,0 +1,52 @@ -+#ifndef __SAA716x_I2C_H -+#define __SAA716x_I2C_H -+ -+#define SAA716x_I2C_ADAPTERS 2 -+ -+#define SAA716x_I2C_ADAPTER(__dev) (( \ -+ (__dev == 1) ? \ -+ "SAA716x I2C Core 1" : \ -+ "SAA716x I2C Core 0")) -+ -+#define SAA716x_I2C_BUS(__x) ((__x == 1) ? 0x0000c000 : 0x0000b000) -+ -+#define SAA716x_I2C_BUS_A 0x01 -+#define SAA716x_I2C_BUS_B 0x00 -+ -+struct saa716x_dev; -+ -+enum saa716x_i2c_rate { -+ SAA716x_I2C_RATE_400 = 1, -+ SAA716x_I2C_RATE_100, -+}; -+ -+enum saa716x_i2c_mode { -+ SAA716x_I2C_MODE_POLLING = 0, -+ SAA716x_I2C_MODE_IRQ, -+ SAA716x_I2C_MODE_IRQ_BUFFERED -+}; -+ -+struct saa716x_i2c { -+ struct i2c_adapter i2c_adapter; -+ struct mutex i2c_lock; -+ struct saa716x_dev *saa716x; -+ u8 i2c_dev; -+ -+ enum saa716x_i2c_rate i2c_rate; /* run time */ -+ enum saa716x_i2c_mode i2c_mode; -+ u32 block_size; /* block size for buffered -+ mode, 1 otherwise */ -+ u32 i2c_stat; -+ -+ u32 stat_tx_prior; -+ u32 stat_tx_done; -+ wait_queue_head_t i2c_wq; -+ int i2c_op; -+}; -+ -+extern int saa716x_i2c_init(struct saa716x_dev *saa716x); -+extern int saa716x_i2c_exit(struct saa716x_dev *saa716x); -+extern void saa716x_i2cint_disable(struct saa716x_dev *saa716x); -+extern int saa716x_i2c_irqevent(struct saa716x_dev *saa716x, u8 bus); -+ -+#endif /* __SAA716x_I2C_H */ -diff --git a/drivers/media/common/saa716x/saa716x_i2c_reg.h b/drivers/media/common/saa716x/saa716x_i2c_reg.h -new file mode 100644 -index 0000000..8fa992c ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_i2c_reg.h -@@ -0,0 +1,145 @@ -+#ifndef __SAA716x_I2C_REG_H -+#define __SAA716x_I2C_REG_H -+ -+/* -------------- I2C Registers -------------- */ -+ -+#define RX_FIFO 0x000 -+#define I2C_RX_BYTE (0x000000ff << 0) -+ -+#define TX_FIFO 0x000 -+#define I2C_STOP_BIT (0x00000001 << 9) -+#define I2C_START_BIT (0x00000001 << 8) -+#define I2C_TX_BYTE (0x000000ff << 0) -+ -+#define I2C_STATUS 0x008 -+#define I2C_TRANSMIT (0x00000001 << 11) -+#define I2C_RECEIVE (0x00000001 << 10) -+#define I2C_TRANSMIT_S_PROG (0x00000001 << 9) -+#define I2C_TRANSMIT_S_CLEAR (0x00000001 << 8) -+#define I2C_TRANSMIT_PROG (0x00000001 << 7) -+#define I2C_TRANSMIT_CLEAR (0x00000001 << 6) -+#define I2C_RECEIVE_PROG (0x00000001 << 5) -+#define I2C_RECEIVE_CLEAR (0x00000001 << 4) -+#define I2C_SDA_LINE (0x00000001 << 3) -+#define I2C_SCL_LINE (0x00000001 << 2) -+#define I2C_START_STOP_FLAG (0x00000001 << 1) -+#define I2C_MODE_STATUS (0x00000001 << 0) -+ -+#define I2C_CONTROL 0x00c -+#define I2C_SCL_CONTROL (0x00000001 << 7) -+#define I2C_SDA_CONTROL (0x00000001 << 6) -+#define I2C_RECEIVE_PROTECT (0x00000001 << 5) -+#define I2C_RECEIVE_PRO_READ (0x00000001 << 4) -+#define I2C_TRANS_SELF_CLEAR (0x00000001 << 3) -+#define I2C_TRANS_S_SELF_CLEAR (0x00000001 << 2) -+#define I2C_SLAVE_ADDR_10BIT (0x00000001 << 1) -+#define I2C_RESET (0x00000001 << 0) -+ -+#define I2C_CLOCK_DIVISOR_HIGH 0x010 -+#define I2C_CLOCK_HIGH (0x0000ffff << 0) -+ -+#define I2C_CLOCK_DIVISOR_LOW 0x014 -+#define I2C_CLOCK_LOW (0x0000ffff << 0) -+ -+#define I2C_RX_LEVEL 0x01c -+#define I2C_RECEIVE_RANGE (0x0000007f << 0) -+ -+#define I2C_TX_LEVEL 0x020 -+#define I2C_TRANSMIT_RANGE (0x0000007f << 0) -+ -+#define I2C_SDA_HOLD 0x028 -+#define I2C_HOLD_TIME (0x0000007f << 0) -+ -+#define MODULE_CONF 0xfd4 -+#define INT_CLR_ENABLE 0xfd8 -+#define I2C_CLR_ENABLE_STFNF (0x00000001 << 12) -+#define I2C_CLR_ENABLE_MTFNF (0x00000001 << 11) -+#define I2C_CLR_ENABLE_RFDA (0x00000001 << 10) -+#define I2C_CLR_ENABLE_RFF (0x00000001 << 9) -+#define I2C_CLR_ENABLE_STDR (0x00000001 << 8) -+#define I2C_CLR_ENABLE_MTDR (0x00000001 << 7) -+#define I2C_CLR_ENABLE_IBE (0x00000001 << 6) -+#define I2C_CLR_ENABLE_MSMC (0x00000001 << 5) -+#define I2C_CLR_ENABLE_SRSD (0x00000001 << 4) -+#define I2C_CLR_ENABLE_STSD (0x00000001 << 3) -+#define I2C_CLR_ENABLE_MTNA (0x00000001 << 2) -+#define I2C_CLR_ENABLE_MAF (0x00000001 << 1) -+#define I2C_CLR_ENABLE_MTD (0x00000001 << 0) -+ -+#define INT_SET_ENABLE 0xfdc -+#define I2C_SET_ENABLE_STFNF (0x00000001 << 12) -+#define I2C_SET_ENABLE_MTFNF (0x00000001 << 11) -+#define I2C_SET_ENABLE_RFDA (0x00000001 << 10) -+#define I2C_SET_ENABLE_RFF (0x00000001 << 9) -+#define I2C_SET_ENABLE_STDR (0x00000001 << 8) -+#define I2C_SET_ENABLE_MTDR (0x00000001 << 7) -+#define I2C_SET_ENABLE_IBE (0x00000001 << 6) -+#define I2C_SET_ENABLE_MSMC (0x00000001 << 5) -+#define I2C_SET_ENABLE_SRSD (0x00000001 << 4) -+#define I2C_SET_ENABLE_STSD (0x00000001 << 3) -+#define I2C_SET_ENABLE_MTNA (0x00000001 << 2) -+#define I2C_SET_ENABLE_MAF (0x00000001 << 1) -+#define I2C_SET_ENABLE_MTD (0x00000001 << 0) -+ -+#define INT_STATUS 0xfe0 -+#define I2C_INTERRUPT_STFNF (0x00000001 << 12) -+#define I2C_INTERRUPT_MTFNF (0x00000001 << 11) -+#define I2C_INTERRUPT_RFDA (0x00000001 << 10) -+#define I2C_INTERRUPTE_RFF (0x00000001 << 9) -+#define I2C_SLAVE_INTERRUPT_STDR (0x00000001 << 8) -+#define I2C_MASTER_INTERRUPT_MTDR (0x00000001 << 7) -+#define I2C_ERROR_IBE (0x00000001 << 6) -+#define I2C_MODE_CHANGE_INTER_MSMC (0x00000001 << 5) -+#define I2C_SLAVE_RECEIVE_INTER_SRSD (0x00000001 << 4) -+#define I2C_SLAVE_TRANSMIT_INTER_STSD (0x00000001 << 3) -+#define I2C_ACK_INTER_MTNA (0x00000001 << 2) -+#define I2C_FAILURE_INTER_MAF (0x00000001 << 1) -+#define I2C_INTERRUPT_MTD (0x00000001 << 0) -+ -+#define INT_ENABLE 0xfe4 -+#define I2C_ENABLE_STFNF (0x00000001 << 12) -+#define I2C_ENABLE_MTFNF (0x00000001 << 11) -+#define I2C_ENABLE_RFDA (0x00000001 << 10) -+#define I2C_ENABLE_RFF (0x00000001 << 9) -+#define I2C_ENABLE_STDR (0x00000001 << 8) -+#define I2C_ENABLE_MTDR (0x00000001 << 7) -+#define I2C_ENABLE_IBE (0x00000001 << 6) -+#define I2C_ENABLE_MSMC (0x00000001 << 5) -+#define I2C_ENABLE_SRSD (0x00000001 << 4) -+#define I2C_ENABLE_STSD (0x00000001 << 3) -+#define I2C_ENABLE_MTNA (0x00000001 << 2) -+#define I2C_ENABLE_MAF (0x00000001 << 1) -+#define I2C_ENABLE_MTD (0x00000001 << 0) -+ -+#define INT_CLR_STATUS 0xfe8 -+#define I2C_CLR_STATUS_STFNF (0x00000001 << 12) -+#define I2C_CLR_STATUS_MTFNF (0x00000001 << 11) -+#define I2C_CLR_STATUS_RFDA (0x00000001 << 10) -+#define I2C_CLR_STATUS_RFF (0x00000001 << 9) -+#define I2C_CLR_STATUS_STDR (0x00000001 << 8) -+#define I2C_CLR_STATUS_MTDR (0x00000001 << 7) -+#define I2C_CLR_STATUS_IBE (0x00000001 << 6) -+#define I2C_CLR_STATUS_MSMC (0x00000001 << 5) -+#define I2C_CLR_STATUS_SRSD (0x00000001 << 4) -+#define I2C_CLR_STATUS_STSD (0x00000001 << 3) -+#define I2C_CLR_STATUS_MTNA (0x00000001 << 2) -+#define I2C_CLR_STATUS_MAF (0x00000001 << 1) -+#define I2C_CLR_STATIS_MTD (0x00000001 << 0) -+ -+#define INT_SET_STATUS 0xfec -+#define I2C_SET_STATUS_STFNF (0x00000001 << 12) -+#define I2C_SET_STATUS_MTFNF (0x00000001 << 11) -+#define I2C_SET_STATUS_RFDA (0x00000001 << 10) -+#define I2C_SET_STATUS_RFF (0x00000001 << 9) -+#define I2C_SET_STATUS_STDR (0x00000001 << 8) -+#define I2C_SET_STATUS_MTDR (0x00000001 << 7) -+#define I2C_SET_STATUS_IBE (0x00000001 << 6) -+#define I2C_SET_STATUS_MSMC (0x00000001 << 5) -+#define I2C_SET_STATUS_SRSD (0x00000001 << 4) -+#define I2C_SET_STATUS_STSD (0x00000001 << 3) -+#define I2C_SET_STATUS_MTNA (0x00000001 << 2) -+#define I2C_SET_STATUS_MAF (0x00000001 << 1) -+#define I2C_SET_STATIS_MTD (0x00000001 << 0) -+ -+ -+#endif /* __SAA716x_I2C_REG_H */ -diff --git a/drivers/media/common/saa716x/saa716x_mod.h b/drivers/media/common/saa716x/saa716x_mod.h -new file mode 100644 -index 0000000..273efdd ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_mod.h -@@ -0,0 +1,50 @@ -+#ifndef __SAA716x_MOD_H -+#define __SAA716x_MOD_H -+ -+/* BAR = 17 bits */ -+/* -+ VI0 0x00000000 -+ VI1 0x00001000 -+ FGPI0 0x00002000 -+ FGPI1 0x00003000 -+ FGPI2 0x00004000 -+ FGPI3 0x00005000 -+ AI0 0x00006000 -+ AI1 0x00007000 -+ BAM 0x00008000 -+ MMU 0x00009000 -+ MSI 0x0000a000 -+ I2C_B 0x0000b000 -+ I2C_A 0x0000c000 -+ SPI 0x0000d000 -+ GPIO 0x0000e000 -+ PHI_0 0x0000f000 -+ CGU 0x00013000 -+ DCS 0x00014000 -+ GREG 0x00012000 -+ -+ PHI_1 0x00020000 -+*/ -+ -+#define VI0 0x00000000 -+#define VI1 0x00001000 -+#define FGPI0 0x00002000 -+#define FGPI1 0x00003000 -+#define FGPI2 0x00004000 -+#define FGPI3 0x00005000 -+#define AI0 0x00006000 -+#define AI1 0x00007000 -+#define BAM 0x00008000 -+#define MMU 0x00009000 -+#define MSI 0x0000a000 -+#define I2C_B 0x0000b000 -+#define I2C_A 0x0000c000 -+#define SPI 0x0000d000 -+#define GPIO 0x0000e000 -+#define PHI_0 0x0000f000 -+#define GREG 0x00012000 -+#define CGU 0x00013000 -+#define DCS 0x00014000 -+#define PHI_1 0x00020000 -+ -+#endif /* __SAA716x_MOD_H */ -diff --git a/drivers/media/common/saa716x/saa716x_msi.c b/drivers/media/common/saa716x/saa716x_msi.c -new file mode 100644 -index 0000000..b0f05a2 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_msi.c -@@ -0,0 +1,479 @@ -+#include -+ -+#include -+#include -+#include -+ -+#include "saa716x_mod.h" -+ -+#include "saa716x_msi_reg.h" -+#include "saa716x_msi.h" -+#include "saa716x_spi.h" -+ -+#include "saa716x_priv.h" -+ -+#define SAA716x_MSI_VECTORS 50 -+ -+static const char *vector_name[] = { -+ "TAGACK_VI0_0", -+ "TAGACK_VI0_1", -+ "TAGACK_VI0_2", -+ "TAGACK_VI1_0", -+ "TAGACK_VI1_1", -+ "TAGACK_VI1_2", -+ "TAGACK_FGPI_0", -+ "TAGACK_FGPI_1", -+ "TAGACK_FGPI_2", -+ "TAGACK_FGPI_3", -+ "TAGACK_AI_0", -+ "TAGACK_AI_1", -+ "OVRFLW_VI0_0", -+ "OVRFLW_VI0_1", -+ "OVRFLW_VI0_2", -+ "OVRFLW_VI1_0", -+ "OVRFLW_VI1_1", -+ "OVRFLW_VI1_2", -+ "OVRFLW_FGPI_O", -+ "OVRFLW_FGPI_1", -+ "OVRFLW_FGPI_2", -+ "OVRFLW_FGPI_3", -+ "OVRFLW_AI_0", -+ "OVRFLW_AI_1", -+ "AVINT_VI0", -+ "AVINT_VI1", -+ "AVINT_FGPI_0", -+ "AVINT_FGPI_1", -+ "AVINT_FGPI_2", -+ "AVINT_FGPI_3", -+ "AVINT_AI_0", -+ "AVINT_AI_1", -+ "UNMAPD_TC_INT", -+ "EXTINT_0", -+ "EXTINT_1", -+ "EXTINT_2", -+ "EXTINT_3", -+ "EXTINT_4", -+ "EXTINT_5", -+ "EXTINT_6", -+ "EXTINT_7", -+ "EXTINT_8", -+ "EXTINT_9", -+ "EXTINT_10", -+ "EXTINT_11", -+ "EXTINT_12", -+ "EXTINT_13", -+ "EXTINT_14", -+ "EXTINT_15", -+ "I2CINT_0", -+ "I2CINT_1" -+}; -+ -+static u32 MSI_CONFIG_REG[51] = { -+ MSI_CONFIG0, -+ MSI_CONFIG1, -+ MSI_CONFIG2, -+ MSI_CONFIG3, -+ MSI_CONFIG4, -+ MSI_CONFIG5, -+ MSI_CONFIG6, -+ MSI_CONFIG7, -+ MSI_CONFIG8, -+ MSI_CONFIG9, -+ MSI_CONFIG10, -+ MSI_CONFIG11, -+ MSI_CONFIG12, -+ MSI_CONFIG13, -+ MSI_CONFIG14, -+ MSI_CONFIG15, -+ MSI_CONFIG16, -+ MSI_CONFIG17, -+ MSI_CONFIG18, -+ MSI_CONFIG19, -+ MSI_CONFIG20, -+ MSI_CONFIG21, -+ MSI_CONFIG22, -+ MSI_CONFIG23, -+ MSI_CONFIG24, -+ MSI_CONFIG25, -+ MSI_CONFIG26, -+ MSI_CONFIG27, -+ MSI_CONFIG28, -+ MSI_CONFIG29, -+ MSI_CONFIG30, -+ MSI_CONFIG31, -+ MSI_CONFIG32, -+ MSI_CONFIG33, -+ MSI_CONFIG34, -+ MSI_CONFIG35, -+ MSI_CONFIG36, -+ MSI_CONFIG37, -+ MSI_CONFIG38, -+ MSI_CONFIG39, -+ MSI_CONFIG40, -+ MSI_CONFIG41, -+ MSI_CONFIG42, -+ MSI_CONFIG43, -+ MSI_CONFIG44, -+ MSI_CONFIG45, -+ MSI_CONFIG46, -+ MSI_CONFIG47, -+ MSI_CONFIG48, -+ MSI_CONFIG49, -+ MSI_CONFIG50 -+}; -+ -+int saa716x_msi_event(struct saa716x_dev *saa716x, u32 stat_l, u32 stat_h) -+{ -+ dprintk(SAA716x_DEBUG, 0, "%s: MSI event ", __func__); -+ -+ if (stat_l & MSI_INT_TAGACK_VI0_0) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[0]); -+ -+ if (stat_l & MSI_INT_TAGACK_VI0_1) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[1]); -+ -+ if (stat_l & MSI_INT_TAGACK_VI0_2) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[2]); -+ -+ if (stat_l & MSI_INT_TAGACK_VI1_0) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[3]); -+ -+ if (stat_l & MSI_INT_TAGACK_VI1_1) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[4]); -+ -+ if (stat_l & MSI_INT_TAGACK_VI1_2) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[5]); -+ -+ if (stat_l & MSI_INT_TAGACK_FGPI_0) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[6]); -+ -+ if (stat_l & MSI_INT_TAGACK_FGPI_1) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[7]); -+ -+ if (stat_l & MSI_INT_TAGACK_FGPI_2) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[8]); -+ -+ if (stat_l & MSI_INT_TAGACK_FGPI_3) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[9]); -+ -+ if (stat_l & MSI_INT_TAGACK_AI_0) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[10]); -+ -+ if (stat_l & MSI_INT_TAGACK_AI_1) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[11]); -+ -+ if (stat_l & MSI_INT_OVRFLW_VI0_0) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[12]); -+ -+ if (stat_l & MSI_INT_OVRFLW_VI0_1) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[13]); -+ -+ if (stat_l & MSI_INT_OVRFLW_VI0_2) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[14]); -+ -+ if (stat_l & MSI_INT_OVRFLW_VI1_0) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[15]); -+ -+ if (stat_l & MSI_INT_OVRFLW_VI1_1) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[16]); -+ -+ if (stat_l & MSI_INT_OVRFLW_VI1_2) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[17]); -+ -+ if (stat_l & MSI_INT_OVRFLW_FGPI_0) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[18]); -+ -+ if (stat_l & MSI_INT_OVRFLW_FGPI_1) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[19]); -+ -+ if (stat_l & MSI_INT_OVRFLW_FGPI_2) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[20]); -+ -+ if (stat_l & MSI_INT_OVRFLW_FGPI_3) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[21]); -+ -+ if (stat_l & MSI_INT_OVRFLW_AI_0) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[22]); -+ -+ if (stat_l & MSI_INT_OVRFLW_AI_1) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[23]); -+ -+ if (stat_l & MSI_INT_AVINT_VI0) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[24]); -+ -+ if (stat_l & MSI_INT_AVINT_VI1) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[25]); -+ -+ if (stat_l & MSI_INT_AVINT_FGPI_0) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[26]); -+ -+ if (stat_l & MSI_INT_AVINT_FGPI_1) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[27]); -+ -+ if (stat_l & MSI_INT_AVINT_FGPI_2) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[28]); -+ -+ if (stat_l & MSI_INT_AVINT_FGPI_3) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[29]); -+ -+ if (stat_l & MSI_INT_AVINT_AI_0) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[30]); -+ -+ if (stat_l & MSI_INT_AVINT_AI_1) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[31]); -+ -+ if (stat_h & MSI_INT_UNMAPD_TC_INT) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[32]); -+ -+ if (stat_h & MSI_INT_EXTINT_0) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[33]); -+ -+ if (stat_h & MSI_INT_EXTINT_1) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[34]); -+ -+ if (stat_h & MSI_INT_EXTINT_2) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[35]); -+ -+ if (stat_h & MSI_INT_EXTINT_3) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[36]); -+ -+ if (stat_h & MSI_INT_EXTINT_4) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[37]); -+ -+ if (stat_h & MSI_INT_EXTINT_5) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[38]); -+ -+ if (stat_h & MSI_INT_EXTINT_6) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[39]); -+ -+ if (stat_h & MSI_INT_EXTINT_7) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[40]); -+ -+ if (stat_h & MSI_INT_EXTINT_8) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[41]); -+ -+ if (stat_h & MSI_INT_EXTINT_9) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[42]); -+ -+ if (stat_h & MSI_INT_EXTINT_10) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[43]); -+ -+ if (stat_h & MSI_INT_EXTINT_11) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[44]); -+ -+ if (stat_h & MSI_INT_EXTINT_12) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[45]); -+ -+ if (stat_h & MSI_INT_EXTINT_13) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[46]); -+ -+ if (stat_h & MSI_INT_EXTINT_14) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[47]); -+ -+ if (stat_h & MSI_INT_EXTINT_15) -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[48]); -+ -+ if (stat_h & MSI_INT_I2CINT_0) { -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[49]); -+ saa716x_i2c_irqevent(saa716x, 0); -+ } -+ -+ if (stat_h & MSI_INT_I2CINT_1) { -+ dprintk(SAA716x_DEBUG, 0, "<%s> ", vector_name[50]); -+ saa716x_i2c_irqevent(saa716x, 1); -+ } -+ -+ dprintk(SAA716x_DEBUG, 0, "\n"); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(saa716x_msi_event); -+ -+int saa716x_msi_init(struct saa716x_dev *saa716x) -+{ -+ u32 ena_l, ena_h, sta_l, sta_h, mid; -+ int i; -+ -+ dprintk(SAA716x_DEBUG, 1, "Initializing MSI .."); -+ saa716x->handlers = 0; -+ -+ /* get module id & version */ -+ mid = SAA716x_EPRD(MSI, MSI_MODULE_ID); -+ if (mid != 0x30100) -+ dprintk(SAA716x_ERROR, 1, "MSI Id<%04x> is not supported", mid); -+ -+ /* let HW take care of MSI race */ -+ SAA716x_EPWR(MSI, MSI_DELAY_TIMER, 0x0); -+ -+ /* INTA Polarity: Active High */ -+ SAA716x_EPWR(MSI, MSI_INTA_POLARITY, MSI_INTA_POLARITY_HIGH); -+ -+ /* -+ * IRQ Edge Rising: 25:24 = 0x01 -+ * Traffic Class: 18:16 = 0x00 -+ * MSI ID: 4:0 = 0x00 -+ */ -+ for (i = 0; i < SAA716x_MSI_VECTORS; i++) -+ SAA716x_EPWR(MSI, MSI_CONFIG_REG[i], MSI_INT_POL_EDGE_RISE); -+ -+ /* get Status */ -+ ena_l = SAA716x_EPRD(MSI, MSI_INT_ENA_L); -+ ena_h = SAA716x_EPRD(MSI, MSI_INT_ENA_H); -+ sta_l = SAA716x_EPRD(MSI, MSI_INT_STATUS_L); -+ sta_h = SAA716x_EPRD(MSI, MSI_INT_STATUS_H); -+ -+ /* disable and clear enabled and asserted IRQ's */ -+ if (sta_l) -+ SAA716x_EPWR(MSI, MSI_INT_STATUS_CLR_L, sta_l); -+ -+ if (sta_h) -+ SAA716x_EPWR(MSI, MSI_INT_STATUS_CLR_H, sta_h); -+ -+ if (ena_l) -+ SAA716x_EPWR(MSI, MSI_INT_ENA_CLR_L, ena_l); -+ -+ if (ena_h) -+ SAA716x_EPWR(MSI, MSI_INT_ENA_CLR_H, ena_h); -+ -+ msleep(5); -+ -+ /* Check IRQ's really disabled */ -+ ena_l = SAA716x_EPRD(MSI, MSI_INT_ENA_L); -+ ena_h = SAA716x_EPRD(MSI, MSI_INT_ENA_H); -+ sta_l = SAA716x_EPRD(MSI, MSI_INT_STATUS_L); -+ sta_h = SAA716x_EPRD(MSI, MSI_INT_STATUS_H); -+ -+ if ((ena_l == 0) && (ena_h == 0) && (sta_l == 0) && (sta_h == 0)) { -+ dprintk(SAA716x_DEBUG, 1, "Interrupts ena_l <%02x> ena_h <%02x> sta_l <%02x> sta_h <%02x>", -+ ena_l, ena_h, sta_l, sta_h); -+ -+ return 0; -+ } else { -+ dprintk(SAA716x_DEBUG, 1, "I/O error"); -+ return -EIO; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(saa716x_msi_init); -+ -+void saa716x_msiint_disable(struct saa716x_dev *saa716x) -+{ -+ dprintk(SAA716x_DEBUG, 1, "Disabling Interrupts ..."); -+ -+ SAA716x_EPWR(MSI, MSI_INT_ENA_L, 0x0); -+ SAA716x_EPWR(MSI, MSI_INT_ENA_H, 0x0); -+ SAA716x_EPWR(MSI, MSI_INT_STATUS_CLR_L, 0xffffffff); -+ SAA716x_EPWR(MSI, MSI_INT_STATUS_CLR_L, 0x0000ffff); -+} -+EXPORT_SYMBOL_GPL(saa716x_msiint_disable); -+ -+ -+/* Map the given vector Id to the hardware bitmask. */ -+static void saa716x_map_vector(struct saa716x_dev *saa716x, int vector, u32 *mask_l, u32 *mask_h) -+{ -+ u32 tmp = 1; -+ -+ if (vector < 32) { -+ /* Bits 0 - 31 */ -+ tmp <<= vector; -+ *mask_l = tmp; -+ *mask_h = 0; -+ } else { -+ /* Bits 32 - 48 */ -+ tmp <<= vector - 32; -+ *mask_l = 0; -+ *mask_h = tmp; -+ } -+} -+ -+int saa716x_add_irqvector(struct saa716x_dev *saa716x, -+ int vector, -+ enum saa716x_edge edge, -+ irqreturn_t (*handler)(int irq, void *dev_id), -+ char *desc) -+{ -+ struct saa716x_msix_entry *msix_handler = NULL; -+ -+ u32 config, mask_l, mask_h, ena_l, ena_h; -+ -+ BUG_ON(saa716x == NULL); -+ BUG_ON(vector > SAA716x_MSI_VECTORS); -+ dprintk(SAA716x_DEBUG, 1, "Adding Vector %d <%s>", vector, vector_name[vector]); -+ -+ if ((vector > 32) && (vector < 49)) { -+ config = SAA716x_EPRD(MSI, MSI_CONFIG_REG[vector]); -+ config &= 0xfcffffff; /* clear polarity */ -+ -+ switch (edge) { -+ default: -+ case SAA716x_EDGE_RISING: -+ SAA716x_EPWR(MSI, MSI_CONFIG_REG[vector], config | 0x01000000); -+ break; -+ -+ case SAA716x_EDGE_FALLING: -+ SAA716x_EPWR(MSI, MSI_CONFIG_REG[vector], config | 0x02000000); -+ break; -+ -+ case SAA716x_EDGE_ANY: -+ SAA716x_EPWR(MSI, MSI_CONFIG_REG[vector], config | 0x03000000); -+ break; -+ } -+ } -+ -+ saa716x_map_vector(saa716x, vector, &mask_l, &mask_h); -+ -+ /* add callback */ -+ msix_handler = &saa716x->saa716x_msix_handler[saa716x->handlers]; -+ strcpy(msix_handler->desc, desc); -+ msix_handler->vector = vector; -+ msix_handler->handler = handler; -+ saa716x->handlers++; -+ -+ SAA716x_EPWR(MSI, MSI_INT_ENA_SET_L, mask_l); -+ SAA716x_EPWR(MSI, MSI_INT_ENA_SET_H, mask_h); -+ -+ ena_l = SAA716x_EPRD(MSI, MSI_INT_ENA_L); -+ ena_h = SAA716x_EPRD(MSI, MSI_INT_ENA_H); -+ dprintk(SAA716x_DEBUG, 1, "Interrupts ena_l <%02x> ena_h <%02x>", ena_l, ena_h); -+ -+ return 0; -+} -+ -+int saa716x_remove_irqvector(struct saa716x_dev *saa716x, int vector) -+{ -+ struct saa716x_msix_entry *msix_handler; -+ int i; -+ u32 mask_l, mask_h; -+ -+ msix_handler = &saa716x->saa716x_msix_handler[saa716x->handlers]; -+ BUG_ON(msix_handler == NULL); -+ dprintk(SAA716x_DEBUG, 1, "Removing Vector %d <%s>", vector, vector_name[vector]); -+ -+ /* loop through the registered handlers */ -+ for (i = 0; i < saa716x->handlers; i++) { -+ -+ /* we found our vector */ -+ if (msix_handler->vector == vector) { -+ BUG_ON(msix_handler->handler == NULL); /* no handler yet */ -+ dprintk(SAA716x_DEBUG, 1, "Vector %d <%s> removed", -+ msix_handler->vector, -+ msix_handler->desc); -+ -+ /* check whether it is already released */ -+ if (msix_handler->handler) { -+ msix_handler->vector = 0; -+ msix_handler->handler = NULL; -+ saa716x->handlers--; -+ } -+ } -+ } -+ -+ saa716x_map_vector(saa716x, vector, &mask_l, &mask_h); -+ -+ /* disable vector */ -+ SAA716x_EPWR(MSI, MSI_INT_ENA_CLR_L, mask_l); -+ SAA716x_EPWR(MSI, MSI_INT_ENA_CLR_H, mask_h); -+ -+ return 0; -+} -diff --git a/drivers/media/common/saa716x/saa716x_msi.h b/drivers/media/common/saa716x/saa716x_msi.h -new file mode 100644 -index 0000000..8eb72d7 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_msi.h -@@ -0,0 +1,87 @@ -+#ifndef __SAA716x_MSI_H -+#define __SAA716x_MSI_H -+ -+#define TAGACK_VI0_0 0x000 -+#define TAGACK_VI0_1 0x001 -+#define TAGACK_VI0_2 0x002 -+#define TAGACK_VI1_0 0x003 -+#define TAGACK_VI1_1 0x004 -+#define TAGACK_VI1_2 0x005 -+#define TAGACK_FGPI_0 0x006 -+#define TAGACK_FGPI_1 0x007 -+#define TAGACK_FGPI_2 0x008 -+#define TAGACK_FGPI_3 0x009 -+#define TAGACK_AI_0 0x00a -+#define TAGACK_AI_1 0x00b -+#define OVRFLW_VI0_0 0x00c -+#define OVRFLW_VI0_1 0x00d -+#define OVRFLW_VI0_2 0x00e -+#define OVRFLW_VI1_0 0x00f -+#define OVRFLW_VI1_1 0x010 -+#define OVRFLW_VI1_2 0x011 -+#define OVRFLW_FGPI_O 0x012 -+#define OVRFLW_FGPI_1 0x013 -+#define OVRFLW_FGPI_2 0x014 -+#define OVRFLW_FGPI_3 0x015 -+#define OVRFLW_AI_0 0x016 -+#define OVRFLW_AI_1 0x017 -+#define AVINT_VI0 0x018 -+#define AVINT_VI1 0x019 -+#define AVINT_FGPI_0 0x01a -+#define AVINT_FGPI_1 0x01b -+#define AVINT_FGPI_2 0x01c -+#define AVINT_FGPI_3 0x01d -+#define AVINT_AI_0 0x01e -+#define AVINT_AI_1 0x01f -+#define UNMAPD_TC_INT 0x020 -+#define EXTINT_0 0x021 -+#define EXTINT_1 0x022 -+#define EXTINT_2 0x023 -+#define EXTINT_3 0x024 -+#define EXTINT_4 0x025 -+#define EXTINT_5 0x026 -+#define EXTINT_6 0x027 -+#define EXTINT_7 0x028 -+#define EXTINT_8 0x029 -+#define EXTINT_9 0x02a -+#define EXTINT_10 0x02b -+#define EXTINT_11 0x02c -+#define EXTINT_12 0x02d -+#define EXTINT_13 0x02e -+#define EXTINT_14 0x02f -+#define EXTINT_15 0x030 -+#define I2CINT_0 0x031 -+#define I2CINT_1 0x032 -+ -+#define SAA716x_TC0 0x000 -+#define SAA716x_TC1 0x001 -+#define SAA716x_TC2 0x002 -+#define SAA716x_TC3 0x003 -+#define SAA716x_TC4 0x004 -+#define SAA716x_TC5 0x005 -+#define SAA716x_TC6 0x006 -+#define SAA716x_TC7 0x007 -+ -+ -+enum saa716x_edge { -+ SAA716x_EDGE_RISING = 1, -+ SAA716x_EDGE_FALLING = 2, -+ SAA716x_EDGE_ANY = 3 -+}; -+ -+struct saa716x_dev; -+ -+extern int saa716x_msi_event(struct saa716x_dev *saa716x, u32 stat_l, u32 stat_h); -+ -+extern int saa716x_msi_init(struct saa716x_dev *saa716x); -+extern void saa716x_msiint_disable(struct saa716x_dev *saa716x); -+ -+extern int saa716x_add_irqvector(struct saa716x_dev *saa716x, -+ int vector, -+ enum saa716x_edge edge, -+ irqreturn_t (*handler)(int irq, void *dev_id), -+ char *desc); -+ -+extern int saa716x_remove_irqvector(struct saa716x_dev *saa716x, int vector); -+ -+#endif /* __SAA716x_MSI_H */ -diff --git a/drivers/media/common/saa716x/saa716x_msi_reg.h b/drivers/media/common/saa716x/saa716x_msi_reg.h -new file mode 100644 -index 0000000..d9a12c7 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_msi_reg.h -@@ -0,0 +1,143 @@ -+#ifndef __SAA716x_MSI_REG_H -+#define __SAA716x_MSI_REG_H -+ -+/* -------------- MSI Registers -------------- */ -+ -+#define MSI_DELAY_TIMER 0x000 -+#define MSI_DELAY_1CLK (0x00000001 << 0) -+#define MSI_DELAY_2CLK (0x00000002 << 0) -+ -+#define MSI_INTA_POLARITY 0x004 -+#define MSI_INTA_POLARITY_HIGH (0x00000001 << 0) -+ -+#define MSI_CONFIG0 0x008 -+#define MSI_CONFIG1 0x00c -+#define MSI_CONFIG2 0x010 -+#define MSI_CONFIG3 0x014 -+#define MSI_CONFIG4 0x018 -+#define MSI_CONFIG5 0x01c -+#define MSI_CONFIG6 0x020 -+#define MSI_CONFIG7 0x024 -+#define MSI_CONFIG8 0x028 -+#define MSI_CONFIG9 0x02c -+#define MSI_CONFIG10 0x030 -+#define MSI_CONFIG11 0x034 -+#define MSI_CONFIG12 0x038 -+#define MSI_CONFIG13 0x03c -+#define MSI_CONFIG14 0x040 -+#define MSI_CONFIG15 0x044 -+#define MSI_CONFIG16 0x048 -+#define MSI_CONFIG17 0x04c -+#define MSI_CONFIG18 0x050 -+#define MSI_CONFIG19 0x054 -+#define MSI_CONFIG20 0x058 -+#define MSI_CONFIG21 0x05c -+#define MSI_CONFIG22 0x060 -+#define MSI_CONFIG23 0x064 -+#define MSI_CONFIG24 0x068 -+#define MSI_CONFIG25 0x06c -+#define MSI_CONFIG26 0x070 -+#define MSI_CONFIG27 0x074 -+#define MSI_CONFIG28 0x078 -+#define MSI_CONFIG29 0x07c -+#define MSI_CONFIG30 0x080 -+#define MSI_CONFIG31 0x084 -+#define MSI_CONFIG32 0x088 -+#define MSI_CONFIG33 0x08c -+#define MSI_CONFIG34 0x090 -+#define MSI_CONFIG35 0x094 -+#define MSI_CONFIG36 0x098 -+#define MSI_CONFIG37 0x09c -+#define MSI_CONFIG38 0x0a0 -+#define MSI_CONFIG39 0x0a4 -+#define MSI_CONFIG40 0x0a8 -+#define MSI_CONFIG41 0x0ac -+#define MSI_CONFIG42 0x0b0 -+#define MSI_CONFIG43 0x0b4 -+#define MSI_CONFIG44 0x0b8 -+#define MSI_CONFIG45 0x0bc -+#define MSI_CONFIG46 0x0c0 -+#define MSI_CONFIG47 0x0c4 -+#define MSI_CONFIG48 0x0c8 -+#define MSI_CONFIG49 0x0cc -+#define MSI_CONFIG50 0x0d0 -+ -+#define MSI_INT_POL_EDGE_RISE (0x00000001 << 24) -+#define MSI_INT_POL_EDGE_FALL (0x00000002 << 24) -+#define MSI_INT_POL_EDGE_ANY (0x00000003 << 24) -+#define MSI_TC (0x00000007 << 16) -+#define MSI_ID (0x0000000f << 0) -+ -+#define MSI_INT_STATUS_L 0xfc0 -+#define MSI_INT_TAGACK_VI0_0 (0x00000001 << 0) -+#define MSI_INT_TAGACK_VI0_1 (0x00000001 << 1) -+#define MSI_INT_TAGACK_VI0_2 (0x00000001 << 2) -+#define MSI_INT_TAGACK_VI1_0 (0x00000001 << 3) -+#define MSI_INT_TAGACK_VI1_1 (0x00000001 << 4) -+#define MSI_INT_TAGACK_VI1_2 (0x00000001 << 5) -+#define MSI_INT_TAGACK_FGPI_0 (0x00000001 << 6) -+#define MSI_INT_TAGACK_FGPI_1 (0x00000001 << 7) -+#define MSI_INT_TAGACK_FGPI_2 (0x00000001 << 8) -+#define MSI_INT_TAGACK_FGPI_3 (0x00000001 << 9) -+#define MSI_INT_TAGACK_AI_0 (0x00000001 << 10) -+#define MSI_INT_TAGACK_AI_1 (0x00000001 << 11) -+#define MSI_INT_OVRFLW_VI0_0 (0x00000001 << 12) -+#define MSI_INT_OVRFLW_VI0_1 (0x00000001 << 13) -+#define MSI_INT_OVRFLW_VI0_2 (0x00000001 << 14) -+#define MSI_INT_OVRFLW_VI1_0 (0x00000001 << 15) -+#define MSI_INT_OVRFLW_VI1_1 (0x00000001 << 16) -+#define MSI_INT_OVRFLW_VI1_2 (0x00000001 << 17) -+#define MSI_INT_OVRFLW_FGPI_0 (0x00000001 << 18) -+#define MSI_INT_OVRFLW_FGPI_1 (0x00000001 << 19) -+#define MSI_INT_OVRFLW_FGPI_2 (0x00000001 << 20) -+#define MSI_INT_OVRFLW_FGPI_3 (0x00000001 << 21) -+#define MSI_INT_OVRFLW_AI_0 (0x00000001 << 22) -+#define MSI_INT_OVRFLW_AI_1 (0x00000001 << 23) -+#define MSI_INT_AVINT_VI0 (0x00000001 << 24) -+#define MSI_INT_AVINT_VI1 (0x00000001 << 25) -+#define MSI_INT_AVINT_FGPI_0 (0x00000001 << 26) -+#define MSI_INT_AVINT_FGPI_1 (0x00000001 << 27) -+#define MSI_INT_AVINT_FGPI_2 (0x00000001 << 28) -+#define MSI_INT_AVINT_FGPI_3 (0x00000001 << 29) -+#define MSI_INT_AVINT_AI_0 (0x00000001 << 30) -+#define MSI_INT_AVINT_AI_1 (0x00000001 << 31) -+ -+#define MSI_INT_STATUS_H 0xfc4 -+#define MSI_INT_UNMAPD_TC_INT (0x00000001 << 0) -+#define MSI_INT_EXTINT_0 (0x00000001 << 1) -+#define MSI_INT_EXTINT_1 (0x00000001 << 2) -+#define MSI_INT_EXTINT_2 (0x00000001 << 3) -+#define MSI_INT_EXTINT_3 (0x00000001 << 4) -+#define MSI_INT_EXTINT_4 (0x00000001 << 5) -+#define MSI_INT_EXTINT_5 (0x00000001 << 6) -+#define MSI_INT_EXTINT_6 (0x00000001 << 7) -+#define MSI_INT_EXTINT_7 (0x00000001 << 8) -+#define MSI_INT_EXTINT_8 (0x00000001 << 9) -+#define MSI_INT_EXTINT_9 (0x00000001 << 10) -+#define MSI_INT_EXTINT_10 (0x00000001 << 11) -+#define MSI_INT_EXTINT_11 (0x00000001 << 12) -+#define MSI_INT_EXTINT_12 (0x00000001 << 13) -+#define MSI_INT_EXTINT_13 (0x00000001 << 14) -+#define MSI_INT_EXTINT_14 (0x00000001 << 15) -+#define MSI_INT_EXTINT_15 (0x00000001 << 16) -+#define MSI_INT_I2CINT_0 (0x00000001 << 17) -+#define MSI_INT_I2CINT_1 (0x00000001 << 18) -+ -+#define MSI_INT_STATUS_CLR_L 0xfc8 -+#define MSI_INT_STATUS_CLR_H 0xfcc -+#define MSI_INT_STATUS_SET_L 0xfd0 -+#define MSI_INT_STATUS_SET_H 0xfd4 -+#define MSI_INT_ENA_L 0xfd8 -+#define MSI_INT_ENA_H 0xfdc -+#define MSI_INT_ENA_CLR_L 0xfe0 -+#define MSI_INT_ENA_CLR_H 0xfe4 -+#define MSI_INT_ENA_SET_L 0xfe8 -+#define MSI_INT_ENA_SET_H 0xfec -+ -+#define MSI_SW_RST 0xff0 -+#define MSI_SW_RESET (0x0001 << 0) -+ -+#define MSI_MODULE_ID 0xffc -+ -+ -+#endif /* __SAA716x_MSI_REG_H */ -diff --git a/drivers/media/common/saa716x/saa716x_pci.c b/drivers/media/common/saa716x/saa716x_pci.c -new file mode 100644 -index 0000000..7fa6bad ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_pci.c -@@ -0,0 +1,275 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "saa716x_spi.h" -+#include "saa716x_msi.h" -+#include "saa716x_priv.h" -+ -+#define DRIVER_NAME "SAA716x Core" -+ -+static irqreturn_t saa716x_msi_handler(int irq, void *dev_id) -+{ -+ return IRQ_HANDLED; -+} -+ -+static int saa716x_enable_msi(struct saa716x_dev *saa716x) -+{ -+ struct pci_dev *pdev = saa716x->pdev; -+ int err; -+ -+ err = pci_enable_msi(pdev); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "MSI enable failed <%d>", err); -+ return err; -+ } -+ -+ return err; -+} -+ -+static int saa716x_enable_msix(struct saa716x_dev *saa716x) -+{ -+ struct pci_dev *pdev = saa716x->pdev; -+ int i, ret = 0; -+ -+ for (i = 0; i < SAA716x_MSI_MAX_VECTORS; i++) -+ saa716x->msix_entries[i].entry = i; -+ -+ ret = pci_enable_msix(pdev, saa716x->msix_entries, SAA716x_MSI_MAX_VECTORS); -+ if (ret < 0) -+ dprintk(SAA716x_ERROR, 1, "MSI-X request failed <%d>", ret); -+ if (ret > 0) -+ dprintk(SAA716x_ERROR, 1, "Request exceeds available IRQ's <%d>", ret); -+ -+ return ret; -+} -+ -+static int saa716x_request_irq(struct saa716x_dev *saa716x) -+{ -+ struct pci_dev *pdev = saa716x->pdev; -+ struct saa716x_config *config = saa716x->config; -+ int i, ret = 0; -+ -+ if (saa716x->int_type == MODE_MSI) { -+ dprintk(SAA716x_DEBUG, 1, "Using MSI mode"); -+ ret = saa716x_enable_msi(saa716x); -+ } else if (saa716x->int_type == MODE_MSI_X) { -+ dprintk(SAA716x_DEBUG, 1, "Using MSI-X mode"); -+ ret = saa716x_enable_msix(saa716x); -+ } -+ -+ if (ret) { -+ dprintk(SAA716x_ERROR, 1, "INT-A Mode"); -+ saa716x->int_type = MODE_INTA; -+ } -+ -+ if (saa716x->int_type == MODE_MSI) { -+ ret = request_irq(pdev->irq, -+ config->irq_handler, -+ 0, -+ DRIVER_NAME, -+ saa716x); -+ -+ if (ret) { -+ pci_disable_msi(pdev); -+ dprintk(SAA716x_ERROR, 1, "MSI registration failed"); -+ ret = -EIO; -+ } -+ } -+ -+ if (saa716x->int_type == MODE_MSI_X) { -+ for (i = 0; SAA716x_MSI_MAX_VECTORS; i++) { -+ ret = request_irq(saa716x->msix_entries[i].vector, -+ saa716x->saa716x_msix_handler[i].handler, -+ IRQF_SHARED, -+ saa716x->saa716x_msix_handler[i].desc, -+ saa716x); -+ -+ dprintk(SAA716x_ERROR, 1, "%s @ 0x%p", saa716x->saa716x_msix_handler[i].desc, saa716x->saa716x_msix_handler[i].handler); -+ if (ret) { -+ dprintk(SAA716x_ERROR, 1, "%s MSI-X-%d registration failed <%d>", saa716x->saa716x_msix_handler[i].desc, i, ret); -+ return -1; -+ } -+ } -+ } -+ -+ if (saa716x->int_type == MODE_INTA) { -+ ret = request_irq(pdev->irq, -+ config->irq_handler, -+ IRQF_SHARED, -+ DRIVER_NAME, -+ saa716x); -+ if (ret < 0) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x IRQ registration failed <%d>", ret); -+ ret = -ENODEV; -+ } -+ } -+ -+ return ret; -+} -+ -+static void saa716x_free_irq(struct saa716x_dev *saa716x) -+{ -+ struct pci_dev *pdev = saa716x->pdev; -+ int i, vector; -+ -+ if (saa716x->int_type == MODE_MSI_X) { -+ -+ for (i = 0; i < SAA716x_MSI_MAX_VECTORS; i++) { -+ vector = saa716x->msix_entries[i].vector; -+ free_irq(vector, saa716x); -+ } -+ -+ pci_disable_msix(pdev); -+ -+ } else { -+ free_irq(pdev->irq, saa716x); -+ if (saa716x->int_type == MODE_MSI) -+ pci_disable_msi(pdev); -+ } -+} -+ -+int saa716x_pci_init(struct saa716x_dev *saa716x) -+{ -+ struct pci_dev *pdev = saa716x->pdev; -+ int err = 0, ret = -ENODEV, i, use_dac, pm_cap; -+ u32 msi_cap; -+ u8 revision; -+ -+ dprintk(SAA716x_ERROR, 1, "found a %s PCIe card", saa716x->config->model_name); -+ -+ err = pci_enable_device(pdev); -+ if (err != 0) { -+ ret = -ENODEV; -+ dprintk(SAA716x_ERROR, 1, "ERROR: PCI enable failed (%i)", err); -+ goto fail0; -+ } -+ -+ if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { -+ use_dac = 1; -+ err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); -+ if (err) { -+ dprintk(SAA716x_ERROR, 1, "Unable to obtain 64bit DMA"); -+ goto fail1; -+ } -+ } else if ((err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) { -+ dprintk(SAA716x_ERROR, 1, "Unable to obtain 32bit DMA"); -+ goto fail1; -+ } -+ -+ pci_set_master(pdev); -+ -+ pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); -+ if (pm_cap == 0) { -+ dprintk(SAA716x_ERROR, 1, "Cannot find Power Management Capability"); -+ err = -EIO; -+ goto fail1; -+ } -+ -+ if (!request_mem_region(pci_resource_start(pdev, 0), -+ pci_resource_len(pdev, 0), -+ DRIVER_NAME)) { -+ -+ dprintk(SAA716x_ERROR, 1, "BAR0 Request failed"); -+ ret = -ENODEV; -+ goto fail1; -+ } -+ saa716x->mmio = ioremap(pci_resource_start(pdev, 0), -+ pci_resource_len(pdev, 0)); -+ -+ if (!saa716x->mmio) { -+ dprintk(SAA716x_ERROR, 1, "Mem 0 remap failed"); -+ ret = -ENODEV; -+ goto fail2; -+ } -+ -+ for (i = 0; i < SAA716x_MSI_MAX_VECTORS; i++) -+ saa716x->msix_entries[i].entry = i; -+ -+ err = saa716x_request_irq(saa716x); -+ if (err < 0) { -+ dprintk(SAA716x_ERROR, 1, "SAA716x IRQ registration failed, err=%d", err); -+ ret = -ENODEV; -+ goto fail3; -+ } -+ -+ pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision); -+ pci_read_config_dword(pdev, 0x40, &msi_cap); -+ -+ saa716x->revision = revision; -+ -+ dprintk(SAA716x_ERROR, 0, " SAA%02x Rev %d [%04x:%04x], ", -+ saa716x->pdev->device, -+ revision, -+ saa716x->pdev->subsystem_vendor, -+ saa716x->pdev->subsystem_device); -+ -+ dprintk(SAA716x_ERROR, 0, -+ "irq: %d,\n mmio: 0x%p\n", -+ saa716x->pdev->irq, -+ saa716x->mmio); -+ -+ dprintk(SAA716x_ERROR, 0, " SAA%02x %sBit, MSI %s, MSI-X=%d msgs", -+ saa716x->pdev->device, -+ (((msi_cap >> 23) & 0x01) == 1 ? "64":"32"), -+ (((msi_cap >> 16) & 0x01) == 1 ? "Enabled" : "Disabled"), -+ (1 << ((msi_cap >> 17) & 0x07))); -+ -+ dprintk(SAA716x_ERROR, 0, "\n"); -+ -+ pci_set_drvdata(pdev, saa716x); -+ -+ return 0; -+ -+fail3: -+ dprintk(SAA716x_ERROR, 1, "Err: IO Unmap"); -+ if (saa716x->mmio) -+ iounmap(saa716x->mmio); -+fail2: -+ dprintk(SAA716x_ERROR, 1, "Err: Release regions"); -+ release_mem_region(pci_resource_start(pdev, 0), -+ pci_resource_len(pdev, 0)); -+ -+fail1: -+ dprintk(SAA716x_ERROR, 1, "Err: Disabling device"); -+ pci_disable_device(pdev); -+ -+fail0: -+ pci_set_drvdata(pdev, NULL); -+ return ret; -+} -+EXPORT_SYMBOL_GPL(saa716x_pci_init); -+ -+void saa716x_pci_exit(struct saa716x_dev *saa716x) -+{ -+ struct pci_dev *pdev = saa716x->pdev; -+ -+ saa716x_free_irq(saa716x); -+ -+ dprintk(SAA716x_NOTICE, 1, "SAA%02x mem0: 0x%p", -+ saa716x->pdev->device, -+ saa716x->mmio); -+ -+ if (saa716x->mmio) { -+ iounmap(saa716x->mmio); -+ release_mem_region(pci_resource_start(pdev, 0), -+ pci_resource_len(pdev, 0)); -+ } -+ -+ pci_disable_device(pdev); -+ pci_set_drvdata(pdev, NULL); -+} -+EXPORT_SYMBOL_GPL(saa716x_pci_exit); -+ -+MODULE_DESCRIPTION("SAA716x bridge driver"); -+MODULE_AUTHOR("Manu Abraham"); -+MODULE_LICENSE("GPL"); -diff --git a/drivers/media/common/saa716x/saa716x_phi.c b/drivers/media/common/saa716x/saa716x_phi.c -new file mode 100644 -index 0000000..7df9a98 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_phi.c -@@ -0,0 +1,152 @@ -+#include -+ -+#include "saa716x_mod.h" -+ -+#include "saa716x_phi_reg.h" -+ -+#include "saa716x_spi.h" -+#include "saa716x_phi.h" -+#include "saa716x_priv.h" -+ -+u32 PHI_0_REGS[] = { -+ PHI_0_MODE, -+ PHI_0_0_CONFIG, -+ PHI_0_1_CONFIG, -+ PHI_0_2_CONFIG, -+ PHI_0_3_CONFIG -+}; -+ -+u32 PHI_1_REGS[] = { -+ PHI_1_MODE, -+ PHI_1_0_CONFIG, -+ PHI_1_1_CONFIG, -+ PHI_1_2_CONFIG, -+ PHI_1_3_CONFIG, -+ PHI_1_4_CONFIG, -+ PHI_1_5_CONFIG, -+ PHI_1_6_CONFIG, -+ PHI_1_7_CONFIG -+}; -+ -+#define PHI_BASE(__port) (( \ -+ (__port == PHI_1) ? \ -+ PHI_1_BASE : \ -+ PHI_0_BASE \ -+)) -+ -+#define PHI_APERTURE(_port) (( \ -+ (__port == PHI_1) ? \ -+ PHI_1_APERTURE: \ -+ PHI_0_APERTURE \ -+)) -+ -+#define PHI_REG(__port, __reg) (( \ -+ (__port == PHI_1) ? \ -+ PHI_1_REGS[__reg] : \ -+ PHI_0_REGS[__reg] \ -+)) -+ -+#define PHI_SLAVE(__port, __slave) (( \ -+ PHI_BASE(__port) + (__slave * (PHI_APERTURE(__port))) \ -+)) -+ -+/* // Read SAA716x registers -+ * SAA716x_EPRD(PHI_0, PHI_REG(__port, __reg)) -+ * SAA716x_EPWR(PHI_1, PHI_REG(__port, __reg), __data) -+ * -+ * // Read slave registers -+ * SAA716x_EPRD(PHI_0, PHI_SLAVE(__port, __slave, __offset)) -+ * SAA716x_EPWR(PHI_1, PHI_SLAVE(__port, __slave, _offset), __data) -+ */ -+ -+int saa716x_init_phi(struct saa716x_dev *saa716x, u32 port, u8 slave) -+{ -+ int i; -+ -+ /* Reset */ -+ SAA716x_EPWR(PHI_0, PHI_SW_RST, 0x1); -+ -+ for (i = 0; i < 20; i++) { -+ msleep(1); -+ if (!(SAA716x_EPRD(PHI_0, PHI_SW_RST))) -+ break; -+ } -+ -+ return 0; -+} -+ -+int saa716x_phi_init(struct saa716x_dev *saa716x) -+{ -+ uint32_t value; -+ -+ /* init PHI 0 to FIFO mode */ -+ value = 0; -+ value |= PHI_FIFO_MODE; -+ SAA716x_EPWR(PHI_0, PHI_0_MODE, value); -+ -+ value = 0; -+ value |= 0x02; /* chip select 1 */ -+ value |= 0x00 << 8; /* ready mask */ -+ value |= 0x03 << 12; /* strobe time */ -+ value |= 0x06 << 20; /* cycle time */ -+ SAA716x_EPWR(PHI_0, PHI_0_0_CONFIG, value); -+ -+ /* init PHI 1 to SRAM mode, auto increment on */ -+ value = 0; -+ value |= PHI_AUTO_INCREMENT; -+ SAA716x_EPWR(PHI_0, PHI_1_MODE, value); -+ -+ value = 0; -+ value |= 0x01; /* chip select 0 */ -+ value |= 0x00 << 8; /* ready mask */ -+ value |= 0x03 << 12; /* strobe time */ -+ value |= 0x05 << 20; /* cycle time */ -+ SAA716x_EPWR(PHI_0, PHI_1_0_CONFIG, value); -+ -+ value = 0; -+ value |= PHI_ALE_POL; /* ALE is active high */ -+ SAA716x_EPWR(PHI_0, PHI_POLARITY, value); -+ -+ SAA716x_EPWR(PHI_0, PHI_TIMEOUT, 0x2a); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(saa716x_phi_init); -+ -+int saa716x_phi_write(struct saa716x_dev *saa716x, u32 address, const u8 * data, int length) -+{ -+ int i; -+ -+ for (i = 0; i < length; i += 4) { -+ SAA716x_EPWR(PHI_1, address, *((u32 *) &data[i])); -+ address += 4; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(saa716x_phi_write); -+ -+int saa716x_phi_read(struct saa716x_dev *saa716x, u32 address, u8 * data, int length) -+{ -+ int i; -+ -+ for (i = 0; i < length; i += 4) { -+ *((u32 *) &data[i]) = SAA716x_EPRD(PHI_1, address); -+ address += 4; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(saa716x_phi_read); -+ -+int saa716x_phi_write_fifo(struct saa716x_dev *saa716x, const u8 * data, int length) -+{ -+ int i; -+ -+ for (i = 0; i < length; i += 4) { -+ SAA716x_EPWR(PHI_0, PHI_0_0_RW_0, *((u32 *) &data[i])); -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(saa716x_phi_write_fifo); -diff --git a/drivers/media/common/saa716x/saa716x_phi.h b/drivers/media/common/saa716x/saa716x_phi.h -new file mode 100644 -index 0000000..ff5cda2 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_phi.h -@@ -0,0 +1,39 @@ -+#ifndef __SAA716x_PHI_H -+#define __SAA716x_PHI_H -+ -+/* PHI SLAVE */ -+#define PHI_SLAVE_0 0 -+#define PHI_SLAVE_1 1 -+#define PHI_SLAVE_2 2 -+#define PHI_SLAVE_3 3 -+#define PHI_SLAVE_4 4 -+#define PHI_SLAVE_5 5 -+#define PHI_SLAVE_6 6 -+#define PHI_SLAVE_7 7 -+ -+/* PHI_REG */ -+#define PHI_MODE 0 -+#define PHI_CONFIG_0 1 -+#define PHI_CONFIG_1 2 -+#define PHI_CONFIG_2 3 -+#define PHI_CONFIG_3 4 -+#define PHI_CONFIG_4 5 -+#define PHI_CONFIG_5 6 -+#define PHI_CONFIG_6 7 -+#define PHI_CONFIG_7 8 -+ -+#define PHI_0_BASE 0x1000 -+#define PHI_0_APERTURE 0x0800 -+ -+#define PHI_1_BASE 0x0000 -+#define PHI_1_APERTURE 0xfffc -+ -+struct saa716x_dev; -+ -+extern int saa716x_init_phi(struct saa716x_dev *saa716x, u32 port, u8 slave); -+extern int saa716x_phi_init(struct saa716x_dev *saa716x); -+extern int saa716x_phi_write(struct saa716x_dev *saa716x, u32 address, const u8 *data, int length); -+extern int saa716x_phi_read(struct saa716x_dev *saa716x, u32 address, u8 *data, int length); -+extern int saa716x_phi_write_fifo(struct saa716x_dev *saa716x, const u8 * data, int length); -+ -+#endif /* __SAA716x_PHI_H */ -diff --git a/drivers/media/common/saa716x/saa716x_phi_reg.h b/drivers/media/common/saa716x/saa716x_phi_reg.h -new file mode 100644 -index 0000000..08f0aa7 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_phi_reg.h -@@ -0,0 +1,100 @@ -+#ifndef __SAA716x_PHI_REG_H -+#define __SAA716x_PHI_REG_H -+ -+/* -------------- PHI_0 Registers -------------- */ -+ -+#define PHI_0_MODE 0x0000 -+#define PHI_0_0_CONFIG 0x0008 -+#define PHI_0_1_CONFIG 0x000c -+#define PHI_0_2_CONFIG 0x0010 -+#define PHI_0_3_CONFIG 0x0014 -+ -+#define PHI_POLARITY 0x0038 -+#define PHI_TIMEOUT 0x003c -+#define PHI_SW_RST 0x0ff0 -+ -+#define PHI_0_0_RW_0 0x1000 -+#define PHI_0_0_RW_511 0x17fc -+ -+#define PHI_0_1_RW_0 0x1800 -+#define PHI_0_1_RW_511 0x1ffc -+ -+#define PHI_0_2_RW_0 0x2000 -+#define PHI_0_2_RW_511 0x27fc -+ -+#define PHI_0_3_RW_0 0x2800 -+#define PHI_0_3_RW_511 0x2ffc -+ -+#define PHI_CSN_DEASSERT (0x00000001 << 2) -+#define PHI_AUTO_INCREMENT (0x00000001 << 1) -+#define PHI_FIFO_MODE (0x00000001 << 0) -+ -+#define PHI_DELAY_RD_WR (0x0000001f << 27) -+#define PHI_EXTEND_RDY3 (0x00000003 << 25) -+#define PHI_EXTEND_RDY2 (0x00000003 << 23) -+#define PHI_EXTEND_RDY1 (0x00000003 << 21) -+#define PHI_EXTEND_RDY0 (0x00000003 << 19) -+#define PHI_RDY3_OD (0x00000001 << 18) -+#define PHI_RDY2_OD (0x00000001 << 17) -+#define PHI_RDY1_OD (0x00000001 << 16) -+#define PHI_RDY0_OD (0x00000001 << 15) -+#define PHI_ALE_POL (0x00000001 << 14) -+#define PHI_WRN_POL (0x00000001 << 13) -+#define PHI_RDN_POL (0x00000001 << 12) -+#define PHI_RDY3_POL (0x00000001 << 11) -+#define PHI_RDY2_POL (0x00000001 << 10) -+#define PHI_RDY1_POL (0x00000001 << 9) -+#define PHI_RDY0_POL (0x00000001 << 8) -+#define PHI_CSN7_POL (0x00000001 << 7) -+#define PHI_CSN6_POL (0x00000001 << 6) -+#define PHI_CSN5_POL (0x00000001 << 5) -+#define PHI_CSN4_POL (0x00000001 << 4) -+#define PHI_CSN3_POL (0x00000001 << 3) -+#define PHI_CSN2_POL (0x00000001 << 2) -+#define PHI_CSN1_POL (0x00000001 << 1) -+#define PHI_CSN0_POL (0x00000001 << 0) -+ -+/* -------------- PHI_1 Registers -------------- */ -+ -+#define PHI_1 0x00020000 -+ -+#define PHI_1_MODE 0x00004 -+#define PHI_1_0_CONFIG 0x00018 -+#define PHI_1_1_CONFIG 0x0001c -+#define PHI_1_2_CONFIG 0x00020 -+#define PHI_1_3_CONFIG 0x00024 -+#define PHI_1_4_CONFIG 0x00028 -+#define PHI_1_5_CONFIG 0x0002c -+#define PHI_1_6_CONFIG 0x00030 -+#define PHI_1_7_CONFIG 0x00034 -+ -+#define PHI_1_0_RW_0 0x00000 -+#define PHI_1_0_RW_16383 0x0fffc -+ -+#define PHI_1_1_RW_0 0x1000 -+#define PHI_1_1_RW_16383 0x1ffc -+ -+#define PHI_1_2_RW_0 0x2000 -+#define PHI_1_2_RW_16383 0x2ffc -+ -+#define PHI_1_3_RW_0 0x3000 -+#define PHI_1_3_RW_16383 0x3ffc -+ -+#define PHI_1_4_RW_0 0x4000 -+#define PHI_1_4_RW_16383 0x4ffc -+ -+#define PHI_1_5_RW_0 0x5000 -+#define PHI_1_5_RW_16383 0x5ffc -+ -+#define PHI_1_6_RW_0 0x6000 -+#define PHI_1_6_RW_16383 0x6ffc -+ -+#define PHI_1_7_RW_0 0x7000 -+#define PHI_1_7_RW_16383 0x7ffc -+ -+ -+/* BAR = 20 bits */ -+/* -------------- PHI1 Registers -------------- */ -+ -+ -+#endif /* __SAA716x_PHI_REG_H */ -diff --git a/drivers/media/common/saa716x/saa716x_priv.h b/drivers/media/common/saa716x/saa716x_priv.h -new file mode 100644 -index 0000000..1ad1d9c ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_priv.h -@@ -0,0 +1,194 @@ -+#ifndef __SAA716x_PRIV_H -+#define __SAA716x_PRIV_H -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include "saa716x_i2c.h" -+#include "saa716x_boot.h" -+#include "saa716x_cgu.h" -+#include "saa716x_dma.h" -+#include "saa716x_fgpi.h" -+ -+#include "dvbdev.h" -+#include "dvb_demux.h" -+#include "dmxdev.h" -+#include "dvb_frontend.h" -+#include "dvb_net.h" -+ -+#define SAA716x_ERROR 0 -+#define SAA716x_NOTICE 1 -+#define SAA716x_INFO 2 -+#define SAA716x_DEBUG 3 -+ -+#define SAA716x_DEV (saa716x)->num -+#define SAA716x_VERBOSE (saa716x)->verbose -+#define SAA716x_MAX_ADAPTERS 4 -+ -+#define dprintk(__x, __y, __fmt, __arg...) do { \ -+ if (__y) { \ -+ if ((SAA716x_VERBOSE > SAA716x_ERROR) && (SAA716x_VERBOSE > __x)) \ -+ printk(KERN_ERR "%s (%d): " __fmt "\n" , __func__ , SAA716x_DEV , ##__arg); \ -+ else if ((SAA716x_VERBOSE > SAA716x_NOTICE) && (SAA716x_VERBOSE > __x)) \ -+ printk(KERN_NOTICE "%s (%d): " __fmt "\n" , __func__ , SAA716x_DEV , ##__arg); \ -+ else if ((SAA716x_VERBOSE > SAA716x_INFO) && (SAA716x_VERBOSE > __x)) \ -+ printk(KERN_INFO "%s (%d): " __fmt "\n" , __func__ , SAA716x_DEV , ##__arg); \ -+ else if ((SAA716x_VERBOSE > SAA716x_DEBUG) && (SAA716x_VERBOSE > __x)) \ -+ printk(KERN_DEBUG "%s (%d): " __fmt "\n" , __func__ , SAA716x_DEV , ##__arg); \ -+ } else { \ -+ if (SAA716x_VERBOSE > __x) \ -+ printk(__fmt , ##__arg); \ -+ } \ -+} while(0) -+ -+ -+#define NXP_SEMICONDUCTOR 0x1131 -+#define SAA7160 0x7160 -+#define SAA7161 0x7161 -+#define SAA7162 0x7162 -+ -+#define NXP_REFERENCE_BOARD 0x1131 -+ -+#define MAKE_ENTRY(__subven, __subdev, __chip, __configptr) { \ -+ .vendor = NXP_SEMICONDUCTOR, \ -+ .device = (__chip), \ -+ .subvendor = (__subven), \ -+ .subdevice = (__subdev), \ -+ .driver_data = (unsigned long) (__configptr) \ -+} -+ -+#define SAA716x_EPWR(__offst, __addr, __data) writel((__data), (saa716x->mmio + (__offst + __addr))) -+#define SAA716x_EPRD(__offst, __addr) readl((saa716x->mmio + (__offst + __addr))) -+ -+#define SAA716x_RCWR(__offst, __addr, __data) writel((__data), (saa716x->mmio + (__offst + __addr))) -+#define SAA716x_RCRD(__offst, __addr) readl((saa716x->mmio + (__offst + __addr))) -+ -+ -+#define SAA716x_MSI_MAX_VECTORS 16 -+ -+struct saa716x_msix_entry { -+ int vector; -+ u8 desc[32]; -+ irqreturn_t (*handler)(int irq, void *dev_id); -+}; -+ -+struct saa716x_dev; -+struct saa716x_adapter; -+struct saa716x_spi_config; -+ -+struct saa716x_adap_config { -+ u32 ts_port; -+ void (*worker)(unsigned long); -+}; -+ -+struct saa716x_config { -+ char *model_name; -+ char *dev_type; -+ -+ enum saa716x_boot_mode boot_mode; -+ -+ int adapters; -+ int frontends; -+ -+ int (*frontend_attach)(struct saa716x_adapter *adapter, int count); -+ irqreturn_t (*irq_handler)(int irq, void *dev_id); -+ -+ struct saa716x_adap_config adap_config[SAA716x_MAX_ADAPTERS]; -+ enum saa716x_i2c_rate i2c_rate; -+ enum saa716x_i2c_mode i2c_mode; -+}; -+ -+struct saa716x_adapter { -+ struct dvb_adapter dvb_adapter; -+ struct dvb_frontend *fe; -+ struct dvb_demux demux; -+ struct dmxdev dmxdev; -+ struct dmx_frontend fe_hw; -+ struct dmx_frontend fe_mem; -+ struct dvb_net dvb_net; -+ -+ struct saa716x_dev *saa716x; -+ -+ u8 feeds; -+ u8 count; -+}; -+ -+struct saa716x_dev { -+ struct saa716x_config *config; -+ struct pci_dev *pdev; -+ -+ int num; /* device count */ -+ int verbose; -+ -+ u8 revision; -+ -+ /* PCI */ -+ void __iomem *mmio; -+ -+#define MODE_INTA 0 -+#define MODE_MSI 1 -+#define MODE_MSI_X 2 -+ u8 int_type; -+ -+ struct msix_entry msix_entries[SAA716x_MSI_MAX_VECTORS]; -+ struct saa716x_msix_entry saa716x_msix_handler[56]; -+ u8 handlers; /* no. of active handlers */ -+ -+ /* I2C */ -+ struct saa716x_i2c i2c[2]; -+ u32 i2c_rate; /* init time */ -+ u32 I2C_DEV[2]; -+ -+ struct saa716x_spi_state *saa716x_spi; -+ struct saa716x_spi_config spi_config; -+ -+ struct saa716x_adapter saa716x_adap[SAA716x_MAX_ADAPTERS]; -+ struct mutex adap_lock; -+ struct saa716x_cgu cgu; -+ -+ spinlock_t gpio_lock; -+ /* DMA */ -+ -+ struct saa716x_fgpi_stream_port fgpi[4]; -+ -+ u32 id_offst; -+ u32 id_len; -+ void *priv; -+ -+ /* remote control */ -+ void *ir_priv; -+}; -+ -+/* PCI */ -+extern int saa716x_pci_init(struct saa716x_dev *saa716x); -+extern void saa716x_pci_exit(struct saa716x_dev *saa716x); -+ -+/* MSI */ -+extern int saa716x_msi_init(struct saa716x_dev *saa716x); -+extern void saa716x_msi_exit(struct saa716x_dev *saa716x); -+extern void saa716x_msiint_disable(struct saa716x_dev *saa716x); -+ -+/* DMA */ -+extern int saa716x_dma_init(struct saa716x_dev *saa716x); -+extern void saa716x_dma_exit(struct saa716x_dev *saa716x); -+ -+/* AUDIO */ -+extern int saa716x_audio_init(struct saa716x_dev *saa716x); -+extern void saa716x_audio_exit(struct saa716x_dev *saa716x); -+ -+/* Boot */ -+extern int saa716x_core_boot(struct saa716x_dev *saa716x); -+extern int saa716x_jetpack_init(struct saa716x_dev *saa716x); -+ -+/* Remote control */ -+extern int saa716x_ir_init(struct saa716x_dev *saa716x); -+extern void saa716x_ir_exit(struct saa716x_dev *saa716x); -+extern void saa716x_ir_handler(struct saa716x_dev *saa716x, u32 ir_cmd); -+ -+#endif /* __SAA716x_PRIV_H */ -diff --git a/drivers/media/common/saa716x/saa716x_reg.h b/drivers/media/common/saa716x/saa716x_reg.h -new file mode 100644 -index 0000000..effd966 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_reg.h -@@ -0,0 +1,1279 @@ -+#ifndef __SAA716x_REG_H -+#define __SAA716x_REG_H -+ -+/* BAR = 17 bits */ -+/* -+ VI0 0x00000000 -+ VI1 0x00001000 -+ FGPI0 0x00002000 -+ FGPI1 0x00003000 -+ FGPI2 0x00004000 -+ FGPI3 0x00005000 -+ AI0 0x00006000 -+ AI1 0x00007000 -+ BAM 0x00008000 -+ MMU 0x00009000 -+ MSI 0x0000a000 -+ I2C_B 0x0000b000 -+ I2C_A 0x0000c000 -+ SPI 0x0000d000 -+ GPIO 0x0000e000 -+ PHI_0 0x0000f000 -+ CGU 0x00013000 -+ DCS 0x00014000 -+ GREG 0x00012000 -+ -+ PHI_1 0x00020000 -+*/ -+ -+/* -------------- VIP Registers -------------- */ -+ -+#define VI0 0x00000000 -+#define VI1 0x00001000 -+ -+#define VI_MODE 0x000 -+#define VID_CFEN (0x00000003 << 30) -+#define VID_OSM (0x00000001 << 29) -+#define VID_FSEQ (0x00000001 << 28) -+#define AUX_CFEN (0x00000003 << 26) -+#define AUX_OSM (0x00000001 << 25) -+#define AUX_FSEQ (0x00000001 << 24) -+#define AUX_ANC_DATA (0x00000003 << 22) -+#define AUX_ANC_RAW (0x00000001 << 21) -+#define RST_ON_ERR (0x00000001 << 17) -+#define SOFT_RESET (0x00000001 << 16) -+#define IFF_CLAMP (0x00000001 << 14) -+#define IFF_MODE (0x00000003 << 12) -+#define DFF_CLAMP (0x00000001 << 10) -+#define DFF_MODE (0x00000003 << 8) -+#define HSP_CLAMP (0x00000001 << 3) -+#define HSP_RGB (0x00000001 << 2) -+#define HSP_MODE (0x00000003 << 0) -+ -+#define RCRB_CTRL 0x004 -+#define RCRB_CFG_ADDR 0x008 -+#define RCRB_CFG_EXT_ADDR 0x00c -+#define RCRB_IO_ADDR 0x010 -+#define RCRB_MEM_LADDR 0x014 -+#define RCRB_MEM_UADDR 0x018 -+#define RCRB_DATA 0x01c -+#define RCRB_MASK 0x020 -+#define RCRB_MSG_HDR 0x040 -+#define RCRB_MSG_PL0 0x044 -+#define RCRB_MSG_PL1 0x048 -+ -+#define ID_MASK0 0x020 -+#define VI_ID_MASK_0 (0x000000ff << 8) -+#define VI_DATA_ID_0 (0x000000ff << 0) -+ -+#define ID_MASK1 0x024 -+#define VI_ID_MASK_1 (0x000000ff << 8) -+#define VI_DATA_ID_1 (0x000000ff << 0) -+ -+#define VIP_LINE_THRESH 0x040 -+#define VI_LCTHR (0x000007ff << 0) -+ -+#define VIN_FORMAT 0x100 -+#define VI_VSRA (0x00000003 << 30) -+#define VI_SYNCHD (0x00000001 << 25) -+#define VI_DUAL_STREAM (0x00000001 << 24) -+#define VI_NHDAUX (0x00000001 << 20) -+#define VI_NPAR (0x00000001 << 19) -+#define VI_VSEL (0x00000003 << 14) -+#define VI_TWOS (0x00000001 << 13) -+#define VI_TPG (0x00000001 << 12) -+#define VI_FREF (0x00000001 << 10) -+#define VI_FTGL (0x00000001 << 9) -+#define VI_SF (0x00000001 << 3) -+#define VI_FZERO (0x00000001 << 2) -+#define VI_REVS (0x00000001 << 1) -+#define VI_REHS (0x00000001 << 0) -+ -+#define TC76543210 0x800 -+#define TCFEDCBA98 0x804 -+#define PHYCFG 0x900 -+#define CONFIG 0xfd4 -+#define INT_ENABLE_CLR 0xfd8 -+#define INT_ENABLE_SET 0xfdc -+ -+ -+#define INT_STATUS 0xfe0 -+#define VI_STAT_FID_AUX (0x00000001 << 31) -+#define VI_STAT_FID_VID (0x00000001 << 30) -+#define VI_STAT_FID_VPI (0x00000001 << 29) -+#define VI_STAT_LINE_COUNT (0x00000fff << 16) -+#define VI_STAT_AUX_OVRFLW (0x00000001 << 9) -+#define VI_STAT_VID_OVRFLW (0x00000001 << 8) -+#define VI_STAT_WIN_SEQBRK (0x00000001 << 7) -+#define VI_STAT_FID_SEQBRK (0x00000001 << 6) -+#define VI_STAT_LINE_THRESH (0x00000001 << 5) -+#define VI_STAT_AUX_WRAP (0x00000001 << 4) -+#define VI_STAT_AUX_START_IN (0x00000001 << 3) -+#define VI_STAT_AUX_END_OUT (0x00000001 << 2) -+#define VI_STAT_VID_START_IN (0x00000001 << 1) -+#define VI_STAT_VID_END_OUT (0x00000001 << 0) -+ -+#define INT_ENABLE 0xfe4 -+#define VI_ENABLE_AUX_OVRFLW (0x00000001 << 9) -+#define VI_ENABLE_VID_OVRFLW (0x00000001 << 8) -+#define VI_ENABLE_WIN_SEQBRK (0x00000001 << 7) -+#define VI_ENABLE_FID_SEQBRK (0x00000001 << 6) -+#define VI_ENABLE_LINE_THRESH (0x00000001 << 5) -+#define VI_ENABLE_AUX_WRAP (0x00000001 << 4) -+#define VI_ENABLE_AUX_START_IN (0x00000001 << 3) -+#define VI_ENABLE_AUX_END_OUT (0x00000001 << 2) -+#define VI_ENABLE_VID_START_IN (0x00000001 << 1) -+#define VI_ENABLE_VID_END_OUT (0x00000001 << 0) -+ -+#define INT_CLR_STATUS 0xfe8 -+#define VI_CLR_STATUS_AUX_OVRFLW (0x00000001 << 9) -+#define VI_CLR_STATUS_VID_OVRFLW (0x00000001 << 8) -+#define VI_CLR_STATUS_WIN_SEQBRK (0x00000001 << 7) -+#define VI_CLR_STATUS_FID_SEQBRK (0x00000001 << 6) -+#define VI_CLR_STATUS_LINE_THRESH (0x00000001 << 5) -+#define VI_CLR_STATUS_AUX_WRAP (0x00000001 << 4) -+#define VI_CLR_STATUS_AUX_START_IN (0x00000001 << 3) -+#define VI_CLR_STATUS_AUX_END_OUT (0x00000001 << 2) -+#define VI_CLR_STATUS_VID_START_IN (0x00000001 << 1) -+#define VI_CLR_STATUS_VID_END_OUT (0x00000001 << 0) -+ -+#define INT_SET_STATUS 0xfec -+#define VI_SET_STATUS_AUX_OVRFLW (0x00000001 << 9) -+#define VI_SET_STATUS_VID_OVRFLW (0x00000001 << 8) -+#define VI_SET_STATUS_WIN_SEQBRK (0x00000001 << 7) -+#define VI_SET_STATUS_FID_SEQBRK (0x00000001 << 6) -+#define VI_SET_STATUS_LINE_THRESH (0x00000001 << 5) -+#define VI_SET_STATUS_AUX_WRAP (0x00000001 << 4) -+#define VI_SET_STATUS_AUX_START_IN (0x00000001 << 3) -+#define VI_SET_STATUS_AUX_END_OUT (0x00000001 << 2) -+#define VI_SET_STATUS_VID_START_IN (0x00000001 << 1) -+#define VI_SET_STATUS_VID_END_OUT (0x00000001 << 0) -+ -+#define VIP_POWER_DOWN 0xff4 -+#define VI_PWR_DWN (0x00000001 << 31) -+ -+ -+ -+ -+/* -------------- FGPI Registers -------------- */ -+ -+#define FGPI0 0x00002000 -+#define FGPI1 0x00003000 -+#define FGPI2 0x00004000 -+#define FGPI3 0x00005000 -+ -+#define FGPI_CONTROL 0x000 -+#define FGPI_CAPTURE_ENABLE_2 (0x00000001 << 13) -+#define FGPI_CAPTURE_ENABLE_1 (0x00000001 << 12) -+#define FGPI_MODE (0x00000001 << 11) -+#define FGPI_SAMPLE_SIZE (0x00000003 << 8) -+#define FGPI_BUF_SYNC_MSG_STOP (0x00000003 << 5) -+#define FGPI_REC_START_MSG_START (0x00000003 << 2) -+#define FGPI_TSTAMP_SELECT (0x00000001 << 1) -+#define FGPI_VAR_LENGTH (0x00000001 << 0) -+ -+#define FGPI_BASE_1 0x004 -+#define FGPI_BASE_2 0x008 -+#define FGPI_SIZE 0x00c -+#define FGPI_REC_SIZE 0x010 -+#define FGPI_STRIDE 0x014 -+#define FGPI_NUM_RECORD_1 0x018 -+#define FGPI_NUM_RECORD_2 0x01c -+#define FGPI_THRESHOLD_1 0x020 -+#define FGPI_THRESHOLD_2 0x024 -+#define FGPI_D1_XY_START 0x028 -+#define FGPI_D1_XY_END 0x02c -+ -+#define INT_STATUS 0xfe0 -+#define FGPI_BUF1_ACTIVE (0x00000001 << 7) -+#define FGPI_OVERFLOW (0x00000001 << 6) -+#define FGPI_MBE (0x00000001 << 5) -+#define FGPI_UNDERRUN (0x00000001 << 4) -+#define FGPI_THRESH2_REACHED (0x00000001 << 3) -+#define FGPI_THRESH1_REACHED (0x00000001 << 2) -+#define FGPI_BUF2_FULL (0x00000001 << 1) -+#define FGPI_BUF1_FULL (0x00000001 << 0) -+ -+#define INT_ENABLE 0xfe4 -+#define FGPI_OVERFLOW_ENA (0x00000001 << 6) -+#define FGPI_MBE_ENA (0x00000001 << 5) -+#define FGPI_UNDERRUN_ENA (0x00000001 << 4) -+#define FGPI_THRESH2_REACHED_ENA (0x00000001 << 3) -+#define FGPI_THRESH1_REACHED_ENA (0x00000001 << 2) -+#define FGPI_BUF2_FULL_ENA (0x00000001 << 1) -+#define FGPI_BUF1_FULL_ENA (0x00000001 << 0) -+ -+#define INT_CLR_STATUS 0xfe8 -+#define FGPI_OVERFLOW_ACK (0x00000001 << 6) -+#define FGPI_MBE_ACK (0x00000001 << 5) -+#define FGPI_UNDERRUN_ACK (0x00000001 << 4) -+#define FGPI_THRESH2_REACHED_ACK (0x00000001 << 3) -+#define FGPI_THRESH1_REACHED_ACK (0x00000001 << 2) -+#define FGPI_BUF2_DONE_ACK (0x00000001 << 1) -+#define FGPI_BUF1_DONE_ACK (0x00000001 << 0) -+ -+#define INT_SET_STATUS 0xfec -+#define FGPI_OVERFLOW_SET (0x00000001 << 6) -+#define FGPI_MBE_SET (0x00000001 << 5) -+#define FGPI_UNDERRUN_SET (0x00000001 << 4) -+#define FGPI_THRESH2_REACHED_SET (0x00000001 << 3) -+#define FGPI_THRESH1_REACHED_SET (0x00000001 << 2) -+#define FGPI_BUF2_DONE_SET (0x00000001 << 1) -+#define FGPI_BUF1_DONE_SET (0x00000001 << 0) -+ -+#define FGPI_SOFT_RESET 0xff0 -+#define FGPI_SOFTWARE_RESET (0x00000001 << 0) -+ -+#define FGPI_INTERFACE 0xff4 -+#define FGPI_DISABLE_BUS_IF (0x00000001 << 0) -+ -+#define FGPI_MOD_ID_EXT 0xff8 -+#define FGPI_MODULE_ID 0xffc -+ -+ -+/* -------------- AI Registers ---------------- */ -+ -+#define AI0 0x00006000 -+#define AI1 0x00007000 -+ -+#define AI_STATUS 0x000 -+#define AI_BUF1_ACTIVE (0x00000001 << 4) -+#define AI_OVERRUN (0x00000001 << 3) -+#define AI_HBE (0x00000001 << 2) -+#define AI_BUF2_FULL (0x00000001 << 1) -+#define AI_BUF1_FULL (0x00000001 << 0) -+ -+#define AI_CTL 0x004 -+#define AI_RESET (0x00000001 << 31) -+#define AI_CAP_ENABLE (0x00000001 << 30) -+#define AI_CAP_MODE (0x00000003 << 28) -+#define AI_SIGN_CONVERT (0x00000001 << 27) -+#define AI_EARLYMODE (0x00000001 << 26) -+#define AI_DIAGMODE (0x00000001 << 25) -+#define AI_RAWMODE (0x00000001 << 24) -+#define AI_OVR_INTEN (0x00000001 << 7) -+#define AI_HBE_INTEN (0x00000001 << 6) -+#define AI_BUF2_INTEN (0x00000001 << 5) -+#define AI_BUF1_INTEN (0x00000001 << 4) -+#define AI_ACK_OVR (0x00000001 << 3) -+#define AI_ACK_HBE (0x00000001 << 2) -+#define AI_ACK2 (0x00000001 << 1) -+#define AI_ACK1 (0x00000001 << 0) -+ -+#define AI_SERIAL 0x008 -+#define AI_SER_MASTER (0x00000001 << 31) -+#define AI_DATAMODE (0x00000001 << 30) -+#define AI_FRAMEMODE (0x00000003 << 28) -+#define AI_CLOCK_EDGE (0x00000001 << 27) -+#define AI_SSPOS4 (0x00000001 << 19) -+#define AI_NR_CHAN (0x00000003 << 17) -+#define AI_WSDIV (0x000001ff << 8) -+#define AI_SCKDIV (0x000000ff << 0) -+ -+#define AI_FRAMING 0x00c -+#define AI_VALIDPOS (0x000001ff << 22) -+#define AI_LEFTPOS (0x000001ff << 13) -+#define AI_RIGHTPOS (0x000001ff << 4) -+#define AI_SSPOS_3_0 (0x0000000f << 0) -+ -+#define AI_BASE1 0x014 -+#define AI_BASE2 0x018 -+#define AI_BASE (0x03ffffff << 6) -+ -+#define AI_SIZE 0x01c -+#define AI_SAMPLE_SIZE (0x03ffffff << 6) -+ -+#define AI_INT_ACK 0x020 -+#define AI_ACK_OVR (0x00000001 << 3) -+#define AI_ACK_HBE (0x00000001 << 2) -+#define AI_ACK2 (0x00000001 << 1) -+#define AI_ACK1 (0x00000001 << 0) -+ -+#define AI_PWR_DOWN 0xff4 -+#define AI_PWR_DWN (0x00000001 << 0) -+ -+/* -------------- BAM Registers -------------- */ -+ -+#define BAM 0x00008000 -+ -+#define BAM_VI0_0_DMA_BUF_MODE 0x000 -+ -+#define BAM_VI0_0_ADDR_OFFST_0 0x004 -+#define BAM_VI0_0_ADDR_OFFST_1 0x008 -+#define BAM_VI0_0_ADDR_OFFST_2 0x00c -+#define BAM_VI0_0_ADDR_OFFST_3 0x010 -+#define BAM_VI0_0_ADDR_OFFST_4 0x014 -+#define BAM_VI0_0_ADDR_OFFST_5 0x018 -+#define BAM_VI0_0_ADDR_OFFST_6 0x01c -+#define BAM_VI0_0_ADDR_OFFST_7 0x020 -+ -+#define BAM_VI0_1_DMA_BUF_MODE 0x024 -+#define BAM_VI0_1_ADDR_OFFST_0 0x028 -+#define BAM_VI0_1_ADDR_OFFST_1 0x02c -+#define BAM_VI0_1_ADDR_OFFST_2 0x030 -+#define BAM_VI0_1_ADDR_OFFST_3 0x034 -+#define BAM_VI0_1_ADDR_OFFST_4 0x038 -+#define BAM_VI0_1_ADDR_OFFST_5 0x03c -+#define BAM_VI0_1_ADDR_OFFST_6 0x040 -+#define BAM_VI0_1_ADDR_OFFST_7 0x044 -+ -+#define BAM_VI0_2_DMA_BUF_MODE 0x048 -+#define BAM_VI0_2_ADDR_OFFST_0 0x04c -+#define BAM_VI0_2_ADDR_OFFST_1 0x050 -+#define BAM_VI0_2_ADDR_OFFST_2 0x054 -+#define BAM_VI0_2_ADDR_OFFST_3 0x058 -+#define BAM_VI0_2_ADDR_OFFST_4 0x05c -+#define BAM_VI0_2_ADDR_OFFST_5 0x060 -+#define BAM_VI0_2_ADDR_OFFST_6 0x064 -+#define BAM_VI0_2_ADDR_OFFST_7 0x068 -+ -+ -+#define BAM_VI1_0_DMA_BUF_MODE 0x06c -+#define BAM_VI1_0_ADDR_OFFST_0 0x070 -+#define BAM_VI1_0_ADDR_OFFST_1 0x074 -+#define BAM_VI1_0_ADDR_OFFST_2 0x078 -+#define BAM_VI1_0_ADDR_OFFST_3 0x07c -+#define BAM_VI1_0_ADDR_OFFST_4 0x080 -+#define BAM_VI1_0_ADDR_OFFST_5 0x084 -+#define BAM_VI1_0_ADDR_OFFST_6 0x088 -+#define BAM_VI1_0_ADDR_OFFST_7 0x08c -+ -+#define BAM_VI1_1_DMA_BUF_MODE 0x090 -+#define BAM_VI1_1_ADDR_OFFST_0 0x094 -+#define BAM_VI1_1_ADDR_OFFST_1 0x098 -+#define BAM_VI1_1_ADDR_OFFST_2 0x09c -+#define BAM_VI1_1_ADDR_OFFST_3 0x0a0 -+#define BAM_VI1_1_ADDR_OFFST_4 0x0a4 -+#define BAM_VI1_1_ADDR_OFFST_5 0x0a8 -+#define BAM_VI1_1_ADDR_OFFST_6 0x0ac -+#define BAM_VI1_1_ADDR_OFFST_7 0x0b0 -+ -+#define BAM_VI1_2_DMA_BUF_MODE 0x0b4 -+#define BAM_VI1_2_ADDR_OFFST_0 0x0b8 -+#define BAM_VI1_2_ADDR_OFFST_1 0x0bc -+#define BAM_VI1_2_ADDR_OFFST_2 0x0c0 -+#define BAM_VI1_2_ADDR_OFFST_3 0x0c4 -+#define BAM_VI1_2_ADDR_OFFST_4 0x0c8 -+#define BAM_VI1_2_ADDR_OFFST_5 0x0cc -+#define BAM_VI1_2_ADDR_OFFST_6 0x0d0 -+#define BAM_VI1_2_ADDR_OFFST_7 0x0d4 -+ -+ -+#define BAM_FGPI0_DMA_BUF_MODE 0x0d8 -+#define BAM_FGPI0_ADDR_OFFST_0 0x0dc -+#define BAM_FGPI0_ADDR_OFFST_1 0x0e0 -+#define BAM_FGPI0_ADDR_OFFST_2 0x0e4 -+#define BAM_FGPI0_ADDR_OFFST_3 0x0e8 -+#define BAM_FGPI0_ADDR_OFFST_4 0x0ec -+#define BAM_FGPI0_ADDR_OFFST_5 0x0f0 -+#define BAM_FGPI0_ADDR_OFFST_6 0x0f4 -+#define BAM_FGPI0_ADDR_OFFST_7 0x0f8 -+ -+#define BAM_FGPI1_DMA_BUF_MODE 0x0fc -+#define BAM_FGPI1_ADDR_OFFST_0 0x100 -+#define BAM_FGPI1_ADDR_OFFST_1 0x104 -+#define BAM_FGPI1_ADDR_OFFST_2 0x108 -+#define BAM_FGPI1_ADDR_OFFST_3 0x10c -+#define BAM_FGPI1_ADDR_OFFST_4 0x110 -+#define BAM_FGPI1_ADDR_OFFST_5 0x114 -+#define BAM_FGPI1_ADDR_OFFST_6 0x118 -+#define BAM_FGPI1_ADDR_OFFST_7 0x11c -+ -+#define BAM_FGPI2_DMA_BUF_MODE 0x120 -+#define BAM_FGPI2_ADDR_OFFST_0 0x124 -+#define BAM_FGPI2_ADDR_OFFST_1 0x128 -+#define BAM_FGPI2_ADDR_OFFST_2 0x12c -+#define BAM_FGPI2_ADDR_OFFST_3 0x130 -+#define BAM_FGPI2_ADDR_OFFST_4 0x134 -+#define BAM_FGPI2_ADDR_OFFST_5 0x138 -+#define BAM_FGPI2_ADDR_OFFST_6 0x13c -+#define BAM_FGPI2_ADDR_OFFST_7 0x140 -+ -+#define BAM_FGPI3_DMA_BUF_MODE 0x144 -+#define BAM_FGPI3_ADDR_OFFST_0 0x148 -+#define BAM_FGPI3_ADDR_OFFST_1 0x14c -+#define BAM_FGPI3_ADDR_OFFST_2 0x150 -+#define BAM_FGPI3_ADDR_OFFST_3 0x154 -+#define BAM_FGPI3_ADDR_OFFST_4 0x158 -+#define BAM_FGPI3_ADDR_OFFST_5 0x15c -+#define BAM_FGPI3_ADDR_OFFST_6 0x160 -+#define BAM_FGPI3_ADDR_OFFST_7 0x164 -+ -+ -+#define BAM_AI0_DMA_BUF_MODE 0x168 -+#define BAM_AI0_ADDR_OFFST_0 0x16c -+#define BAM_AI0_ADDR_OFFST_1 0x170 -+#define BAM_AI0_ADDR_OFFST_2 0x174 -+#define BAM_AI0_ADDR_OFFST_3 0x178 -+#define BAM_AI0_ADDR_OFFST_4 0x17c -+#define BAM_AIO_ADDR_OFFST_5 0x180 -+#define BAM_AI0_ADDR_OFFST_6 0x184 -+#define BAM_AIO_ADDR_OFFST_7 0x188 -+ -+#define BAM_AI1_DMA_BUF_MODE 0x18c -+#define BAM_AI1_ADDR_OFFST_0 0x190 -+#define BAM_AI1_ADDR_OFFST_1 0x194 -+#define BAM_AI1_ADDR_OFFST_2 0x198 -+#define BAM_AI1_ADDR_OFFST_3 0x19c -+#define BAM_AI1_ADDR_OFFST_4 0x1a0 -+#define BAM_AI1_ADDR_OFFST_5 0x1a4 -+#define BAM_AI1_ADDR_OFFST_6 0x1a8 -+#define BAM_AI1_ADDR_OFFST_7 0x1ac -+ -+#define BAM_SW_RST 0xff0 -+#define BAM_SW_RESET (0x00000001 << 0) -+ -+ -+ -+ -+ -+/* -------------- MMU Registers -------------- */ -+ -+#define MMU 0x00009000 -+ -+#define MMU_MODE 0x000 -+ -+#define MMU_DMA_CONFIG0 0x004 -+#define MMU_DMA_CONFIG1 0x008 -+#define MMU_DMA_CONFIG2 0x00c -+#define MMU_DMA_CONFIG3 0x010 -+#define MMU_DMA_CONFIG4 0x014 -+#define MMU_DMA_CONFIG5 0x018 -+#define MMU_DMA_CONFIG6 0x01c -+#define MMU_DMA_CONFIG7 0x020 -+#define MMU_DMA_CONFIG8 0x024 -+#define MMU_DMA_CONFIG9 0x028 -+#define MMU_DMA_CONFIG10 0x02c -+#define MMU_DMA_CONFIG11 0x030 -+#define MMU_DMA_CONFIG12 0x034 -+#define MMU_DMA_CONFIG13 0x038 -+#define MMU_DMA_CONFIG14 0x03c -+#define MMU_DMA_CONFIG15 0x040 -+ -+#define MMU_SW_RST 0xff0 -+#define MMU_SW_RESET (0x0001 << 0) -+ -+#define MMU_PTA_BASE0 0x044 /* DMA 0 */ -+#define MMU_PTA_BASE1 0x084 /* DMA 1 */ -+#define MMU_PTA_BASE2 0x0c4 /* DMA 2 */ -+#define MMU_PTA_BASE3 0x104 /* DMA 3 */ -+#define MMU_PTA_BASE4 0x144 /* DMA 4 */ -+#define MMU_PTA_BASE5 0x184 /* DMA 5 */ -+#define MMU_PTA_BASE6 0x1c4 /* DMA 6 */ -+#define MMU_PTA_BASE7 0x204 /* DMA 7 */ -+#define MMU_PTA_BASE8 0x244 /* DMA 8 */ -+#define MMU_PTA_BASE9 0x284 /* DMA 9 */ -+#define MMU_PTA_BASE10 0x2c4 /* DMA 10 */ -+#define MMU_PTA_BASE11 0x304 /* DMA 11 */ -+#define MMU_PTA_BASE12 0x344 /* DMA 12 */ -+#define MMU_PTA_BASE13 0x384 /* DMA 13 */ -+#define MMU_PTA_BASE14 0x3c4 /* DMA 14 */ -+#define MMU_PTA_BASE15 0x404 /* DMA 15 */ -+ -+#define MMU_PTA_BASE 0x044 /* DMA 0 */ -+#define MMU_PTA_OFFSET 0x40 -+ -+#define PTA_BASE(__ch) (MMU_PTA_BASE + (MMU_PTA_OFFSET * __ch)) -+ -+#define MMU_PTA0_LSB(__ch) PTA_BASE(__ch) + 0x00 -+#define MMU_PTA0_MSB(__ch) PTA_BASE(__ch) + 0x04 -+#define MMU_PTA1_LSB(__ch) PTA_BASE(__ch) + 0x08 -+#define MMU_PTA1_MSB(__ch) PTA_BASE(__ch) + 0x0c -+#define MMU_PTA2_LSB(__ch) PTA_BASE(__ch) + 0x10 -+#define MMU_PTA2_MSB(__ch) PTA_BASE(__ch) + 0x14 -+#define MMU_PTA3_LSB(__ch) PTA_BASE(__ch) + 0x18 -+#define MMU_PTA3_MSB(__ch) PTA_BASE(__ch) + 0x1c -+#define MMU_PTA4_LSB(__ch) PTA_BASE(__ch) + 0x20 -+#define MMU_PTA4_MSB(__ch) PTA_BASE(__ch) + 0x24 -+#define MMU_PTA5_LSB(__ch) PTA_BASE(__ch) + 0x28 -+#define MMU_PTA5_MSB(__ch) PTA_BASE(__ch) + 0x2c -+#define MMU_PTA6_LSB(__ch) PTA_BASE(__ch) + 0x30 -+#define MMU_PTA6_MSB(__ch) PTA_BASE(__ch) + 0x34 -+#define MMU_PTA7_LSB(__ch) PTA_BASE(__ch) + 0x38 -+#define MMU_PTA7_MSB(__ch) PTA_BASE(__ch) + 0x3c -+ -+ -+/* -------------- MSI Registers -------------- */ -+ -+#define MSI 0x0000a000 -+ -+#define MSI_DELAY_TIMER 0x000 -+#define MSI_DELAY_1CLK (0x00000001 << 0) -+#define MSI_DELAY_2CLK (0x00000002 << 0) -+ -+#define MSI_INTA_POLARITY 0x004 -+#define MSI_INTA_POLARITY_HIGH (0x00000001 << 0) -+ -+#define MSI_CONFIG0 0x008 -+#define MSI_CONFIG1 0x00c -+#define MSI_CONFIG2 0x010 -+#define MSI_CONFIG3 0x014 -+#define MSI_CONFIG4 0x018 -+#define MSI_CONFIG5 0x01c -+#define MSI_CONFIG6 0x020 -+#define MSI_CONFIG7 0x024 -+#define MSI_CONFIG8 0x028 -+#define MSI_CONFIG9 0x02c -+#define MSI_CONFIG10 0x030 -+#define MSI_CONFIG11 0x034 -+#define MSI_CONFIG12 0x038 -+#define MSI_CONFIG13 0x03c -+#define MSI_CONFIG14 0x040 -+#define MSI_CONFIG15 0x044 -+#define MSI_CONFIG16 0x048 -+#define MSI_CONFIG17 0x04c -+#define MSI_CONFIG18 0x050 -+#define MSI_CONFIG19 0x054 -+#define MSI_CONFIG20 0x058 -+#define MSI_CONFIG21 0x05c -+#define MSI_CONFIG22 0x060 -+#define MSI_CONFIG23 0x064 -+#define MSI_CONFIG24 0x068 -+#define MSI_CONFIG25 0x06c -+#define MSI_CONFIG26 0x070 -+#define MSI_CONFIG27 0x074 -+#define MSI_CONFIG28 0x078 -+#define MSI_CONFIG29 0x07c -+#define MSI_CONFIG30 0x080 -+#define MSI_CONFIG31 0x084 -+#define MSI_CONFIG32 0x088 -+#define MSI_CONFIG33 0x08c -+#define MSI_CONFIG34 0x090 -+#define MSI_CONFIG35 0x094 -+#define MSI_CONFIG36 0x098 -+#define MSI_CONFIG37 0x09c -+#define MSI_CONFIG38 0x0a0 -+#define MSI_CONFIG39 0x0a4 -+#define MSI_CONFIG40 0x0a8 -+#define MSI_CONFIG41 0x0ac -+#define MSI_CONFIG42 0x0b0 -+#define MSI_CONFIG43 0x0b4 -+#define MSI_CONFIG44 0x0b8 -+#define MSI_CONFIG45 0x0bc -+#define MSI_CONFIG46 0x0c0 -+#define MSI_CONFIG47 0x0c4 -+#define MSI_CONFIG48 0x0c8 -+#define MSI_CONFIG49 0x0cc -+#define MSI_CONFIG50 0x0d0 -+ -+#define MSI_INT_POL_EDGE_RISE (0x00000001 << 24) -+#define MSI_INT_POL_EDGE_FALL (0x00000002 << 24) -+#define MSI_INT_POL_EDGE_ANY (0x00000003 << 24) -+#define MSI_TC (0x00000007 << 16) -+#define MSI_ID (0x0000000f << 0) -+ -+#define MSI_INT_STATUS_L 0xfc0 -+#define MSI_INT_TAGACK_VI0_0 (0x00000001 << 0) -+#define MSI_INT_TAGACK_VI0_1 (0x00000001 << 1) -+#define MSI_INT_TAGACK_VI0_2 (0x00000001 << 2) -+#define MSI_INT_TAGACK_VI1_0 (0x00000001 << 3) -+#define MSI_INT_TAGACK_VI1_1 (0x00000001 << 4) -+#define MSI_INT_TAGACK_VI1_2 (0x00000001 << 5) -+#define MSI_INT_TAGACK_FGPI_0 (0x00000001 << 6) -+#define MSI_INT_TAGACK_FGPI_1 (0x00000001 << 7) -+#define MSI_INT_TAGACK_FGPI_2 (0x00000001 << 8) -+#define MSI_INT_TAGACK_FGPI_3 (0x00000001 << 9) -+#define MSI_INT_TAGACK_AI_0 (0x00000001 << 10) -+#define MSI_INT_TAGACK_AI_1 (0x00000001 << 11) -+#define MSI_INT_OVRFLW_VI0_0 (0x00000001 << 12) -+#define MSI_INT_OVRFLW_VI0_1 (0x00000001 << 13) -+#define MSI_INT_OVRFLW_VI0_2 (0x00000001 << 14) -+#define MSI_INT_OVRFLW_VI1_0 (0x00000001 << 15) -+#define MSI_INT_OVRFLW_VI1_1 (0x00000001 << 16) -+#define MSI_INT_OVRFLW_VI1_2 (0x00000001 << 17) -+#define MSI_INT_OVRFLW_FGPI_O (0x00000001 << 18) -+#define MSI_INT_OVRFLW_FGPI_1 (0x00000001 << 19) -+#define MSI_INT_OVRFLW_FGPI_2 (0x00000001 << 20) -+#define MSI_INT_OVRFLW_FGPI_3 (0x00000001 << 21) -+#define MSI_INT_OVRFLW_AI_0 (0x00000001 << 22) -+#define MSI_INT_OVRFLW_AI_1 (0x00000001 << 23) -+#define MSI_INT_AVINT_VI0 (0x00000001 << 24) -+#define MSI_INT_AVINT_VI1 (0x00000001 << 25) -+#define MSI_INT_AVINT_FGPI_0 (0x00000001 << 26) -+#define MSI_INT_AVINT_FGPI_1 (0x00000001 << 27) -+#define MSI_INT_AVINT_FGPI_2 (0x00000001 << 28) -+#define MSI_INT_AVINT_FGPI_3 (0x00000001 << 29) -+#define MSI_INT_AVINT_AI_0 (0x00000001 << 30) -+#define MSI_INT_AVINT_AI_1 (0x00000001 << 31) -+ -+#define MSI_INT_STATUS_H 0xfc4 -+#define MSI_INT_UNMAPD_TC_INT (0x00000001 << 0) -+#define MSI_INT_EXTINT_0 (0x00000001 << 1) -+#define MSI_INT_EXTINT_1 (0x00000001 << 2) -+#define MSI_INT_EXTINT_2 (0x00000001 << 3) -+#define MSI_INT_EXTINT_3 (0x00000001 << 4) -+#define MSI_INT_EXTINT_4 (0x00000001 << 5) -+#define MSI_INT_EXTINT_5 (0x00000001 << 6) -+#define MSI_INT_EXTINT_6 (0x00000001 << 7) -+#define MSI_INT_EXTINT_7 (0x00000001 << 8) -+#define MSI_INT_EXTINT_8 (0x00000001 << 9) -+#define MSI_INT_EXTINT_9 (0x00000001 << 10) -+#define MSI_INT_EXTINT_10 (0x00000001 << 11) -+#define MSI_INT_EXTINT_11 (0x00000001 << 12) -+#define MSI_INT_EXTINT_12 (0x00000001 << 13) -+#define MSI_INT_EXTINT_13 (0x00000001 << 14) -+#define MSI_INT_EXTINT_14 (0x00000001 << 15) -+#define MSI_INT_EXTINT_15 (0x00000001 << 16) -+#define MSI_INT_I2CINT_0 (0x00000001 << 17) -+#define MSI_INT_I2CINT_1 (0x00000001 << 18) -+ -+#define MSI_INT_STATUS_CLR_L 0xfc8 -+#define MSI_INT_STATUS_CLR_H 0xfcc -+#define MSI_INT_STATUS_SET_L 0xfd0 -+#define MSI_INT_STATUS_SET_H 0xfd4 -+#define MSI_INT_ENA_L 0xfd8 -+#define MSI_INT_ENA_H 0xfdc -+#define MSI_INT_ENA_CLR_L 0xfe0 -+#define MSI_INT_ENA_CLR_H 0xfe4 -+#define MSI_INT_ENA_SET_L 0xfe8 -+#define MSI_INT_ENA_SET_H 0xfec -+ -+#define MSI_SW_RST 0xff0 -+#define MSI_SW_RESET (0x0001 << 0) -+ -+#define MSI_MODULE_ID 0xffc -+ -+ -+/* -------------- I2C Registers -------------- */ -+ -+#define I2C_B 0x0000b000 -+#define I2C_A 0x0000c000 -+ -+#define RX_FIFO 0x000 -+#define I2C_RX_BYTE (0x000000ff << 0) -+ -+#define TX_FIFO 0x000 -+#define I2C_STOP_BIT (0x00000001 << 9) -+#define I2C_START_BIT (0x00000001 << 8) -+#define I2C_TX_BYTE (0x000000ff << 0) -+ -+#define I2C_STATUS 0x008 -+#define I2C_TRANSMIT (0x00000001 << 11) -+#define I2C_RECEIVE (0x00000001 << 10) -+#define I2C_TRANSMIT_S_PROG (0x00000001 << 9) -+#define I2C_TRANSMIT_S_CLEAR (0x00000001 << 8) -+#define I2C_TRANSMIT_PROG (0x00000001 << 7) -+#define I2C_TRANSMIT_CLEAR (0x00000001 << 6) -+#define I2C_RECEIVE_PROG (0x00000001 << 5) -+#define I2C_RECEIVE_CLEAR (0x00000001 << 4) -+#define I2C_SDA_LINE (0x00000001 << 3) -+#define I2C_SCL_LINE (0x00000001 << 2) -+#define I2C_START_STOP_FLAG (0x00000001 << 1) -+#define I2C_MODE_STATUS (0x00000001 << 0) -+ -+#define I2C_CONTROL 0x00c -+#define I2C_SCL_CONTROL (0x00000001 << 7) -+#define I2C_SDA_CONTROL (0x00000001 << 6) -+#define I2C_RECEIVE_PROTECT (0x00000001 << 5) -+#define I2C_RECEIVE_PRO_READ (0x00000001 << 4) -+#define I2C_TRANS_SELF_CLEAR (0x00000001 << 3) -+#define I2C_TRANS_S_SELF_CLEAR (0x00000001 << 2) -+#define I2C_SLAVE_ADDR_10BIT (0x00000001 << 1) -+#define I2C_RESET (0x00000001 << 0) -+ -+#define I2C_CLOCK_DIVISOR_HIGH 0x010 -+#define I2C_CLOCK_HIGH (0x0000ffff << 0) -+ -+#define I2C_CLOCK_DIVISOR_LOW 0x014 -+#define I2C_CLOCK_LOW (0x0000ffff << 0) -+ -+#define I2C_RX_LEVEL 0x01c -+#define I2C_RECEIVE_RANGE (0x0000007f << 0) -+ -+#define I2C_TX_LEVEL 0x020 -+#define I2C_TRANSMIT_RANGE (0x0000007f << 0) -+ -+#define I2C_SDA_HOLD 0x028 -+#define I2C_HOLD_TIME (0x0000007f << 0) -+ -+#define MODULE_CONF 0xfd4 -+#define INT_CLR_ENABLE 0xfd8 -+#define I2C_CLR_ENABLE_STFNF (0x00000001 << 12) -+#define I2C_CLR_ENABLE_MTFNF (0x00000001 << 11) -+#define I2C_CLR_ENABLE_RFDA (0x00000001 << 10) -+#define I2C_CLR_ENABLE_RFF (0x00000001 << 9) -+#define I2C_CLR_ENABLE_STDR (0x00000001 << 8) -+#define I2C_CLR_ENABLE_MTDR (0x00000001 << 7) -+#define I2C_CLR_ENABLE_IBE (0x00000001 << 6) -+#define I2C_CLR_ENABLE_MSMC (0x00000001 << 5) -+#define I2C_CLR_ENABLE_SRSD (0x00000001 << 4) -+#define I2C_CLR_ENABLE_STSD (0x00000001 << 3) -+#define I2C_CLR_ENABLE_MTNA (0x00000001 << 2) -+#define I2C_CLR_ENABLE_MAF (0x00000001 << 1) -+#define I2C_CLR_ENABLE_MTD (0x00000001 << 0) -+ -+#define INT_SET_ENABLE 0xfdc -+#define I2C_SET_ENABLE_STFNF (0x00000001 << 12) -+#define I2C_SET_ENABLE_MTFNF (0x00000001 << 11) -+#define I2C_SET_ENABLE_RFDA (0x00000001 << 10) -+#define I2C_SET_ENABLE_RFF (0x00000001 << 9) -+#define I2C_SET_ENABLE_STDR (0x00000001 << 8) -+#define I2C_SET_ENABLE_MTDR (0x00000001 << 7) -+#define I2C_SET_ENABLE_IBE (0x00000001 << 6) -+#define I2C_SET_ENABLE_MSMC (0x00000001 << 5) -+#define I2C_SET_ENABLE_SRSD (0x00000001 << 4) -+#define I2C_SET_ENABLE_STSD (0x00000001 << 3) -+#define I2C_SET_ENABLE_MTNA (0x00000001 << 2) -+#define I2C_SET_ENABLE_MAF (0x00000001 << 1) -+#define I2C_SET_ENABLE_MTD (0x00000001 << 0) -+ -+#define INT_STATUS 0xfe0 -+#define I2C_INTERRUPT_STFNF (0x00000001 << 12) -+#define I2C_INTERRUPT_MTFNF (0x00000001 << 11) -+#define I2C_INTERRUPT_RFDA (0x00000001 << 10) -+#define I2C_INTERRUPTE_RFF (0x00000001 << 9) -+#define I2C_SLAVE_INTERRUPT_STDR (0x00000001 << 8) -+#define I2C_MASTER_INTERRUPT_MTDR (0x00000001 << 7) -+#define I2C_ERROR_IBE (0x00000001 << 6) -+#define I2C_MODE_CHANGE_INTER_MSMC (0x00000001 << 5) -+#define I2C_SLAVE_RECEIVE_INTER_SRSD (0x00000001 << 4) -+#define I2C_SLAVE_TRANSMIT_INTER_STSD (0x00000001 << 3) -+#define I2C_ACK_INTER_MTNA (0x00000001 << 2) -+#define I2C_FAILURE_INTER_MAF (0x00000001 << 1) -+#define I2C_INTERRUPT_MTD (0x00000001 << 0) -+ -+#define INT_ENABLE 0xfe4 -+#define I2C_ENABLE_STFNF (0x00000001 << 12) -+#define I2C_ENABLE_MTFNF (0x00000001 << 11) -+#define I2C_ENABLE_RFDA (0x00000001 << 10) -+#define I2C_ENABLE_RFF (0x00000001 << 9) -+#define I2C_ENABLE_STDR (0x00000001 << 8) -+#define I2C_ENABLE_MTDR (0x00000001 << 7) -+#define I2C_ENABLE_IBE (0x00000001 << 6) -+#define I2C_ENABLE_MSMC (0x00000001 << 5) -+#define I2C_ENABLE_SRSD (0x00000001 << 4) -+#define I2C_ENABLE_STSD (0x00000001 << 3) -+#define I2C_ENABLE_MTNA (0x00000001 << 2) -+#define I2C_ENABLE_MAF (0x00000001 << 1) -+#define I2C_ENABLE_MTD (0x00000001 << 0) -+ -+#define INT_CLR_STATUS 0xfe8 -+#define I2C_CLR_STATUS_STFNF (0x00000001 << 12) -+#define I2C_CLR_STATUS_MTFNF (0x00000001 << 11) -+#define I2C_CLR_STATUS_RFDA (0x00000001 << 10) -+#define I2C_CLR_STATUS_RFF (0x00000001 << 9) -+#define I2C_CLR_STATUS_STDR (0x00000001 << 8) -+#define I2C_CLR_STATUS_MTDR (0x00000001 << 7) -+#define I2C_CLR_STATUS_IBE (0x00000001 << 6) -+#define I2C_CLR_STATUS_MSMC (0x00000001 << 5) -+#define I2C_CLR_STATUS_SRSD (0x00000001 << 4) -+#define I2C_CLR_STATUS_STSD (0x00000001 << 3) -+#define I2C_CLR_STATUS_MTNA (0x00000001 << 2) -+#define I2C_CLR_STATUS_MAF (0x00000001 << 1) -+#define I2C_CLR_STATIS_MTD (0x00000001 << 0) -+ -+#define INT_SET_STATUS 0xfec -+#define I2C_SET_STATUS_STFNF (0x00000001 << 12) -+#define I2C_SET_STATUS_MTFNF (0x00000001 << 11) -+#define I2C_SET_STATUS_RFDA (0x00000001 << 10) -+#define I2C_SET_STATUS_RFF (0x00000001 << 9) -+#define I2C_SET_STATUS_STDR (0x00000001 << 8) -+#define I2C_SET_STATUS_MTDR (0x00000001 << 7) -+#define I2C_SET_STATUS_IBE (0x00000001 << 6) -+#define I2C_SET_STATUS_MSMC (0x00000001 << 5) -+#define I2C_SET_STATUS_SRSD (0x00000001 << 4) -+#define I2C_SET_STATUS_STSD (0x00000001 << 3) -+#define I2C_SET_STATUS_MTNA (0x00000001 << 2) -+#define I2C_SET_STATUS_MAF (0x00000001 << 1) -+#define I2C_SET_STATIS_MTD (0x00000001 << 0) -+ -+ -+ -+ -+/* -------------- SPI Registers -------------- */ -+ -+#define SPI 0x0000d000 -+ -+#define SPI_CONTROL_REG 0x000 -+#define SPI_SERIAL_INTER_ENABLE (0x00000001 << 7) -+#define SPI_LSB_FIRST_ENABLE (0x00000001 << 6) -+#define SPI_MODE_SELECT (0x00000001 << 5) -+#define SPI_CLOCK_POLARITY (0x00000001 << 4) -+#define SPI_CLOCK_PHASE (0x00000001 << 3) -+ -+#define SPI_STATUS 0x004 -+#define SPI_TRANSFER_FLAG (0x00000001 << 7) -+#define SPI_WRITE_COLLISSION (0x00000001 << 6) -+#define SPI_READ_OVERRUN (0x00000001 << 5) -+#define SPI_MODE_FAULT (0x00000001 << 4) -+#define SPI_SLAVE_ABORT (0x00000001 << 3) -+ -+#define SPI_DATA 0x008 -+#define SPI_BIDI_DATA (0x000000ff << 0) -+ -+#define SPI_CLOCK_COUNTER 0x00c -+#define SPI_CLOCK (0x00000001 << 0) -+ -+ -+ -+ -+/* -------------- GPIO Registers -------------- */ -+ -+#define GPIO 0x0000e000 -+ -+#define GPIO_RD 0x000 -+#define GPIO_WR 0x004 -+#define GPIO_WR_MODE 0x008 -+#define GPIO_OEN 0x00c -+ -+#define GPIO_SW_RST 0xff0 -+#define GPIO_SW_RESET (0x00000001 << 0) -+ -+#define GPIO_31 (1 << 31) -+#define GPIO_30 (1 << 30) -+#define GPIO_29 (1 << 29) -+#define GPIO_28 (1 << 28) -+#define GPIO_27 (1 << 27) -+#define GPIO_26 (1 << 26) -+#define GPIO_25 (1 << 25) -+#define GPIO_24 (1 << 24) -+#define GPIO_23 (1 << 23) -+#define GPIO_22 (1 << 22) -+#define GPIO_21 (1 << 21) -+#define GPIO_20 (1 << 20) -+#define GPIO_19 (1 << 19) -+#define GPIO_18 (1 << 18) -+#define GPIO_17 (1 << 17) -+#define GPIO_16 (1 << 16) -+#define GPIO_15 (1 << 15) -+#define GPIO_14 (1 << 14) -+#define GPIO_13 (1 << 13) -+#define GPIO_12 (1 << 12) -+#define GPIO_11 (1 << 11) -+#define GPIO_10 (1 << 10) -+#define GPIO_09 (1 << 9) -+#define GPIO_08 (1 << 8) -+#define GPIO_07 (1 << 7) -+#define GPIO_06 (1 << 6) -+#define GPIO_05 (1 << 5) -+#define GPIO_04 (1 << 4) -+#define GPIO_03 (1 << 3) -+#define GPIO_02 (1 << 2) -+#define GPIO_01 (1 << 1) -+#define GPIO_00 (1 << 0) -+ -+/* -------------- PHI_0 Registers -------------- */ -+ -+#define PHI_0 0x0000f000 -+ -+#define PHI_0_MODE 0x0000 -+#define PHI_0_0_CONFIG 0x0008 -+#define PHI_0_1_CONFIG 0x000c -+#define PHI_0_2_CONFIG 0x0010 -+#define PHI_0_3_CONFIG 0x0014 -+ -+#define PHI_POLARITY 0x0038 -+#define PHI_TIMEOUT 0x003c -+#define PHI_SW_RST 0x0ff0 -+ -+#define PHI_0_0_RW_0 0x1000 -+#define PHI_0_0_RW_511 0x17fc -+ -+#define PHI_0_1_RW_0 0x1800 -+#define PHI_0_1_RW_511 0x1ffc -+ -+#define PHI_0_2_RW_0 0x2000 -+#define PHI_0_2_RW_511 0x27fc -+ -+#define PHI_0_3_RW_0 0x2800 -+#define PHI_0_3_RW_511 0x2ffc -+ -+#define PHI_CSN_DEASSERT (0x00000001 << 2) -+#define PHI_AUTO_INCREMENT (0x00000001 << 1) -+#define PHI_FIFO_MODE (0x00000001 << 0) -+ -+#define PHI_DELAY_RD_WR (0x0000001f << 27) -+#define PHI_EXTEND_RDY3 (0x00000003 << 25) -+#define PHI_EXTEND_RDY2 (0x00000003 << 23) -+#define PHI_EXTEND_RDY1 (0x00000003 << 21) -+#define PHI_EXTEND_RDY0 (0x00000003 << 19) -+#define PHI_RDY3_OD (0x00000001 << 18) -+#define PHI_RDY2_OD (0x00000001 << 17) -+#define PHI_RDY1_OD (0x00000001 << 16) -+#define PHI_RDY0_OD (0x00000001 << 15) -+#define PHI_ALE_POL (0x00000001 << 14) -+#define PHI_WRN_POL (0x00000001 << 13) -+#define PHI_RDN_POL (0x00000001 << 12) -+#define PHI_RDY3_POL (0x00000001 << 11) -+#define PHI_RDY2_POL (0x00000001 << 10) -+#define PHI_RDY1_POL (0x00000001 << 9) -+#define PHI_RDY0_POL (0x00000001 << 8) -+#define PHI_CSN7_POL (0x00000001 << 7) -+#define PHI_CSN6_POL (0x00000001 << 6) -+#define PHI_CSN5_POL (0x00000001 << 5) -+#define PHI_CSN4_POL (0x00000001 << 4) -+#define PHI_CSN3_POL (0x00000001 << 3) -+#define PHI_CSN2_POL (0x00000001 << 2) -+#define PHI_CSN1_POL (0x00000001 << 1) -+#define PHI_CSN0_POL (0x00000001 << 0) -+ -+/* -------------- PHI_1 Registers -------------- */ -+ -+#define PHI_1 0x00020000 -+ -+#define PHI_1_MODE 0x00004 -+#define PHI_1_0_CONFIG 0x00018 -+#define PHI_1_1_CONFIG 0x0001c -+#define PHI_1_2_CONFIG 0x00020 -+#define PHI_1_3_CONFIG 0x00024 -+#define PHI_1_4_CONFIG 0x00028 -+#define PHI_1_5_CONFIG 0x0002c -+#define PHI_1_6_CONFIG 0x00030 -+#define PHI_1_7_CONFIG 0x00034 -+ -+#define PHI_1_0_RW_0 0x00000 -+#define PHI_1_0_RW_16383 0x0fffc -+ -+#define PHI_1_1_RW_0 0x1000 -+#define PHI_1_1_RW_16383 0x1ffc -+ -+#define PHI_1_2_RW_0 0x2000 -+#define PHI_1_2_RW_16383 0x2ffc -+ -+#define PHI_1_3_RW_0 0x3000 -+#define PHI_1_3_RW_16383 0x3ffc -+ -+#define PHI_1_4_RW_0 0x4000 -+#define PHI_1_4_RW_16383 0x4ffc -+ -+#define PHI_1_5_RW_0 0x5000 -+#define PHI_1_5_RW_16383 0x5ffc -+ -+#define PHI_1_6_RW_0 0x6000 -+#define PHI_1_6_RW_16383 0x6ffc -+ -+#define PHI_1_7_RW_0 0x7000 -+#define PHI_1_7_RW_16383 0x7ffc -+ -+/* -------------- CGU Registers -------------- */ -+ -+#define CGU 0x00013000 -+ -+#define CGU_SCR_0 0x000 -+#define CGU_SCR_1 0x004 -+#define CGU_SCR_2 0x008 -+#define CGU_SCR_3 0x00c -+#define CGU_SCR_4 0x010 -+#define CGU_SCR_5 0x014 -+#define CGU_SCR_6 0x018 -+#define CGU_SCR_7 0x01c -+#define CGU_SCR_8 0x020 -+#define CGU_SCR_9 0x024 -+#define CGU_SCR_10 0x028 -+#define CGU_SCR_11 0x02c -+#define CGU_SCR_12 0x030 -+#define CGU_SCR_13 0x034 -+#define CGU_SCR_STOP (0x00000001 << 3) -+#define CGU_SCR_RESET (0x00000001 << 2) -+#define CGU_SCR_ENF2 (0x00000001 << 1) -+#define CGU_SCR_ENF1 (0x00000001 << 0) -+ -+#define CGU_FS1_0 0x038 -+#define CGU_FS1_1 0x03c -+#define CGU_FS1_2 0x040 -+#define CGU_FS1_3 0x044 -+#define CGU_FS1_4 0x048 -+#define CGU_FS1_5 0x04c -+#define CGU_FS1_6 0x050 -+#define CGU_FS1_7 0x054 -+#define CGU_FS1_8 0x058 -+#define CGU_FS1_9 0x05c -+#define CGU_FS1_10 0x060 -+#define CGU_FS1_11 0x064 -+#define CGU_FS1_12 0x068 -+#define CGU_FS1_13 0x06c -+#define CGU_FS1_PLL (0x00000000 << 0) -+ -+ -+#define CGU_FS2_0 0x070 -+#define CGU_FS2_1 0x074 -+#define CGU_FS2_2 0x078 -+#define CGU_FS2_3 0x07c -+#define CGU_FS2_4 0x080 -+#define CGU_FS2_5 0x084 -+#define CGU_FS2_6 0x088 -+#define CGU_FS2_7 0x08c -+#define CGU_FS2_8 0x090 -+#define CGU_FS2_9 0x094 -+#define CGU_FS2_10 0x098 -+#define CGU_FS2_11 0x09c -+#define CGU_FS2_12 0x0a0 -+#define CGU_FS2_13 0x0a4 -+ -+#define CGU_SSR_0 0x0a8 -+#define CGU_SSR_1 0x0ac -+#define CGU_SSR_2 0x0b0 -+#define CGU_SSR_3 0x0b4 -+#define CGU_SSR_4 0x0b8 -+#define CGU_SSR_5 0x0bc -+#define CGU_SSR_6 0x0c0 -+#define CGU_SSR_7 0x0c4 -+#define CGU_SSR_8 0x0c8 -+#define CGU_SSR_9 0x0cc -+#define CGU_SSR_10 0x0d0 -+#define CGU_SSR_11 0x0d4 -+#define CGU_SSR_12 0x0d8 -+#define CGU_SSR_13 0x0dc -+ -+#define CGU_PCR_0_0 0x0e0 -+#define CGU_PCR_0_1 0x0e4 -+#define CGU_PCR_0_2 0x0e8 -+#define CGU_PCR_0_3 0x0ec -+#define CGU_PCR_0_4 0x0f0 -+#define CGU_PCR_0_5 0x0f4 -+#define CGU_PCR_0_6 0x0f8 -+#define CGU_PCR_0_7 0x0fc -+#define CGU_PCR_1_0 0x100 -+#define CGU_PCR_1_1 0x104 -+#define CGU_PCR_2_0 0x108 -+#define CGU_PCR_2_1 0x10c -+#define CGU_PCR_3_0 0x110 -+#define CGU_PCR_3_1 0x114 -+#define CGU_PCR_3_2 0x118 -+#define CGU_PCR_4_0 0x11c -+#define CGU_PCR_4_1 0x120 -+#define CGU_PCR_5 0x124 -+#define CGU_PCR_6 0x128 -+#define CGU_PCR_7 0x12c -+#define CGU_PCR_8 0x130 -+#define CGU_PCR_9 0x134 -+#define CGU_PCR_10 0x138 -+#define CGU_PCR_11 0x13c -+#define CGU_PCR_12 0x140 -+#define CGU_PCR_13 0x144 -+#define CGU_PCR_WAKE_EN (0x00000001 << 2) -+#define CGU_PCR_AUTO (0x00000001 << 1) -+#define CGU_PCR_RUN (0x00000001 << 0) -+ -+ -+#define CGU_PSR_0_0 0x148 -+#define CGU_PSR_0_1 0x14c -+#define CGU_PSR_0_2 0x150 -+#define CGU_PSR_0_3 0x154 -+#define CGU_PSR_0_4 0x158 -+#define CGU_PSR_0_5 0x15c -+#define CGU_PSR_0_6 0x160 -+#define CGU_PSR_0_7 0x164 -+#define CGU_PSR_1_0 0x168 -+#define CGU_PSR_1_1 0x16c -+#define CGU_PSR_2_0 0x170 -+#define CGU_PSR_2_1 0x174 -+#define CGU_PSR_3_0 0x178 -+#define CGU_PSR_3_1 0x17c -+#define CGU_PSR_3_2 0x180 -+#define CGU_PSR_4_0 0x184 -+#define CGU_PSR_4_1 0x188 -+#define CGU_PSR_5 0x18c -+#define CGU_PSR_6 0x190 -+#define CGU_PSR_7 0x194 -+#define CGU_PSR_8 0x198 -+#define CGU_PSR_9 0x19c -+#define CGU_PSR_10 0x1a0 -+#define CGU_PSR_11 0x1a4 -+#define CGU_PSR_12 0x1a8 -+#define CGU_PSR_13 0x1ac -+ -+#define CGU_ESR_0_0 0x1b0 -+#define CGU_ESR_0_1 0x1b4 -+#define CGU_ESR_0_2 0x1b8 -+#define CGU_ESR_0_3 0x1bc -+#define CGU_ESR_0_4 0x1c0 -+#define CGU_ESR_0_5 0x1c4 -+#define CGU_ESR_0_6 0x1c8 -+#define CGU_ESR_0_7 0x1cc -+#define CGU_ESR_1_0 0x1d0 -+#define CGU_ESR_1_1 0x1d4 -+#define CGU_ESR_2_0 0x1d8 -+#define CGU_ESR_2_1 0x1dc -+#define CGU_ESR_3_0 0x1e0 -+#define CGU_ESR_3_1 0x1e4 -+#define CGU_ESR_3_2 0x1e8 -+#define CGU_ESR_4_0 0x1ec -+#define CGU_ESR_4_1 0x1f0 -+#define CGU_ESR_5 0x1f4 -+#define CGU_ESR_6 0x1f8 -+#define CGU_ESR_7 0x1fc -+#define CGU_ESR_8 0x200 -+#define CGU_ESR_9 0x204 -+#define CGU_ESR_10 0x208 -+#define CGU_ESR_11 0x20c -+#define CGU_ESR_12 0x210 -+#define CGU_ESR_13 0x214 -+#define CGU_ESR_FD_EN (0x00000001 << 0) -+ -+#define CGU_FDC_0 0x218 -+#define CGU_FDC_1 0x21c -+#define CGU_FDC_2 0x220 -+#define CGU_FDC_3 0x224 -+#define CGU_FDC_4 0x228 -+#define CGU_FDC_5 0x22c -+#define CGU_FDC_6 0x230 -+#define CGU_FDC_7 0x234 -+#define CGU_FDC_8 0x238 -+#define CGU_FDC_9 0x23c -+#define CGU_FDC_10 0x240 -+#define CGU_FDC_11 0x244 -+#define CGU_FDC_12 0x248 -+#define CGU_FDC_13 0x24c -+#define CGU_FDC_STRETCH (0x00000001 << 0) -+#define CGU_FDC_RESET (0x00000001 << 1) -+#define CGU_FDC_RUN1 (0x00000001 << 2) -+#define CGU_FDC_MADD (0x000000ff << 3) -+#define CGU_FDC_MSUB (0x000000ff << 11) -+ -+/* -------------- DCS Registers -------------- */ -+ -+#define DCS 0x00014000 -+ -+#define DCSC_CTRL 0x000 -+#define DCSC_SEL_PLLDI (0x03ffffff << 5) -+#define DCSC_TOUT_SEL (0x0000000f << 1) -+#define DCSC_TOUT_OFF (0x00000001 << 0) -+ -+#define DCSC_ADDR 0x00c -+#define DCSC_ERR_TOUT_ADDR (0x3fffffff << 2) -+ -+#define DCSC_STAT 0x010 -+#define DCSC_ERR_TOUT_GNT (0x0000001f << 24) -+#define DCSC_ERR_TOUT_SEL (0x0000007f << 10) -+#define DCSC_ERR_TOUT_READ (0x00000001 << 8) -+#define DCSC_ERR_TOUT_MASK (0x0000000f << 4) -+#define DCSC_ERR_ACK (0x00000001 << 1) -+ -+#define DCSC_FEATURES 0x040 -+#define DCSC_UNIQUE_ID (0x00000007 << 16) -+#define DCSC_SECURITY (0x00000001 << 14) -+#define DCSC_NUM_BASE_REGS (0x00000003 << 11) -+#define DCSC_NUM_TARGETS (0x0000001f << 5) -+#define DCSC_NUM_INITIATORS (0x0000001f << 0) -+ -+#define DCSC_BASE_REG0 0x100 -+#define DCSC_BASE_N_REG (0x00000fff << 20) -+ -+#define DCSC_INT_CLR_ENABLE 0xfd8 -+#define DCSC_INT_CLR_ENABLE_TOUT (0x00000001 << 1) -+#define DCSC_INT_CLR_ENABLE_ERROR (0x00000001 << 0) -+ -+#define DCSC_INT_SET_ENABLE 0xfdc -+#define DCSC_INT_SET_ENABLE_TOUT (0x00000001 << 1) -+#define DCSC_INT_SET_ENABLE_ERROR (0x00000001 << 0) -+ -+#define DCSC_INT_STATUS 0xfe0 -+#define DCSC_INT_STATUS_TOUT (0x00000001 << 1) -+#define DCSC_INT_STATUS_ERROR (0x00000001 << 0) -+ -+#define DCSC_INT_ENABLE 0xfe4 -+#define DCSC_INT_ENABLE_TOUT (0x00000001 << 1) -+#define DCSC_INT_ENABLE_ERROR (0x00000001 << 0) -+ -+#define DCSC_INT_CLR_STATUS 0xfe8 -+#define DCSC_INT_CLEAR_TOUT (0x00000001 << 1) -+#define DCSC_INT_CLEAR_ERROR (0x00000001 << 0) -+ -+#define DCSC_INT_SET_STATUS 0xfec -+#define DCSC_INT_SET_TOUT (0x00000001 << 1) -+#define DCSC_INT_SET_ERROR (0x00000001 << 0) -+ -+ -+ -+ -+/* -------------- GREG Registers -------------- */ -+ -+#define GREG 0x00012000 -+ -+#define GREG_SUBSYS_CONFIG 0x000 -+#define GREG_SUBSYS_ID (0x0000ffff << 16) -+#define GREG_SUBSYS_VID (0x0000ffff << 0) -+ -+#define GREG_MSI_BAR_PMCSR 0x004 -+#define GREG_PMCSR_SCALE_7 (0x00000003 << 30) -+#define GREG_PMCSR_SCALE_6 (0x00000003 << 28) -+#define GREG_PMCSR_SCALE_5 (0x00000003 << 26) -+#define GREG_PMCSR_SCALE_4 (0x00000003 << 24) -+#define GREG_PMCSR_SCALE_3 (0x00000003 << 22) -+#define GREG_PMCSR_SCALE_2 (0x00000003 << 20) -+#define GREG_PMCSR_SCALE_1 (0x00000003 << 18) -+#define GREG_PMCSR_SCALE_0 (0x00000003 << 16) -+ -+#define GREG_BAR_WIDTH_17 (0x0000001e << 8) -+#define GREG_BAR_WIDTH_18 (0x0000001c << 8) -+#define GREG_BAR_WIDTH_19 (0x00000018 << 8) -+#define GREG_BAR_WIDTH_20 (0x00000010 << 8) -+ -+#define GREG_BAR_PREFETCH (0x00000001 << 3) -+#define GREG_MSI_MM_CAP1 (0x00000000 << 0) // FIXME ! -+#define GREG_MSI_MM_CAP2 (0x00000001 << 0) -+#define GREG_MSI_MM_CAP4 (0x00000002 << 0) -+#define GREG_MSI_MM_CAP8 (0x00000003 << 0) -+#define GREG_MSI_MM_CAP16 (0x00000004 << 0) -+#define GREG_MSI_MM_CAP32 (0x00000005 << 0) -+ -+#define GREG_PMCSR_DATA_1 0x008 -+#define GREG_PMCSR_DATA_2 0x00c -+#define GREG_VI_CTRL 0x010 -+#define GREG_FGPI_CTRL 0x014 -+ -+#define GREG_RSTU_CTRL 0x018 -+#define GREG_BOOT_READY (0x00000001 << 13) -+#define GREG_RESET_REQ (0x00000001 << 12) -+#define GREG_IP_RST_RELEASE (0x00000001 << 11) -+#define GREG_ADAPTER_RST_RELEASE (0x00000001 << 10) -+#define GREG_PCIE_CORE_RST_RELEASE (0x00000001 << 9) -+#define GREG_BOOT_IP_RST_RELEASE (0x00000001 << 8) -+#define GREG_BOOT_RST_RELEASE (0x00000001 << 7) -+#define GREG_CGU_RST_RELEASE (0x00000001 << 6) -+#define GREG_IP_RST_ASSERT (0x00000001 << 5) -+#define GREG_ADAPTER_RST_ASSERT (0x00000001 << 4) -+#define GREG_RST_ASSERT (0x00000001 << 3) -+#define GREG_BOOT_IP_RST_ASSERT (0x00000001 << 2) -+#define GREG_BOOT_RST_ASSERT (0x00000001 << 1) -+#define GREG_CGU_RST_ASSERT (0x00000001 << 0) -+ -+#define GREG_I2C_CTRL 0x01c -+#define GREG_I2C_SLAVE_ADDR (0x0000007f << 0) -+ -+#define GREG_OVFLW_CTRL 0x020 -+#define GREG_OVERFLOW_ENABLE (0x00001fff << 0) -+ -+#define GREG_TAG_ACK_FLEN 0x024 -+#define GREG_TAG_ACK_FLEN_1B (0x00000000 << 0) -+#define GREG_TAG_ACK_FLEN_2B (0x00000001 << 0) -+#define GREG_TAG_ACK_FLEN_4B (0x00000002 << 0) -+#define GREG_TAG_ACK_FLEN_8B (0x00000003 << 0) -+ -+#define GREG_VIDEO_IN_CTRL 0x028 -+ -+#define GREG_SPARE_1 0x02c -+#define GREG_SPARE_2 0x030 -+#define GREG_SPARE_3 0x034 -+#define GREG_SPARE_4 0x038 -+#define GREG_SPARE_5 0x03c -+#define GREG_SPARE_6 0x040 -+#define GREG_SPARE_7 0x044 -+#define GREG_SPARE_8 0x048 -+#define GREG_SPARE_9 0x04c -+#define GREG_SPARE_10 0x050 -+#define GREG_SPARE_11 0x054 -+#define GREG_SPARE_12 0x058 -+#define GREG_SPARE_13 0x05c -+#define GREG_SPARE_14 0x060 -+#define GREG_SPARE_15 0x064 -+ -+#define GREG_FAIL_DISABLE 0x068 -+#define GREG_BOOT_FAIL_DISABLE (0x00000001 << 0) -+ -+#define GREG_SW_RST 0xff0 -+#define GREG_SW_RESET (0x00000001 << 0) -+ -+ -+ -+ -+/* BAR = 20 bits */ -+ -+/* -------------- PHI1 Registers -------------- */ -+ -+#define PHI_1 0x00020000 -+ -+ -+ -+#endif /* __SAA716x_REG_H */ -diff --git a/drivers/media/common/saa716x/saa716x_rom.c b/drivers/media/common/saa716x/saa716x_rom.c -new file mode 100644 -index 0000000..7f8dbe1 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_rom.c -@@ -0,0 +1,1071 @@ -+#include -+#include -+ -+#include "saa716x_rom.h" -+#include "saa716x_adap.h" -+#include "saa716x_spi.h" -+#include "saa716x_priv.h" -+ -+int i; -+ -+static int eeprom_read_bytes(struct saa716x_dev *saa716x, u16 reg, u16 len, u8 *val) -+{ -+ struct saa716x_i2c *i2c = saa716x->i2c; -+ struct i2c_adapter *adapter = &i2c[SAA716x_I2C_BUS_B].i2c_adapter; -+ -+ u8 b0[] = { MSB(reg), LSB(reg) }; -+ int ret; -+ -+ struct i2c_msg msg[] = { -+ { .addr = 0x50, .flags = 0, .buf = b0, .len = sizeof (b0) }, -+ { .addr = 0x50, .flags = I2C_M_RD, .buf = val, .len = len } -+ }; -+ -+ ret = i2c_transfer(adapter, msg, 2); -+ if (ret != 2) { -+ dprintk(SAA716x_ERROR, 1, "read error ", reg, ret); -+ return -EREMOTEIO; -+ } -+ -+ return ret; -+} -+ -+static int saa716x_read_rombytes(struct saa716x_dev *saa716x, u16 reg, u16 len, u8 *val) -+{ -+ struct saa716x_i2c *i2c = saa716x->i2c; -+ struct i2c_adapter *adapter = &i2c[SAA716x_I2C_BUS_B].i2c_adapter; -+ struct i2c_msg msg[2]; -+ -+ u8 b0[2]; -+ int ret, count; -+ -+ count = len / DUMP_BYTES; -+ if (len % DUMP_BYTES) -+ count++; -+ -+ count *= 2; -+ -+ for (i = 0; i < count; i += 2) { -+ dprintk(SAA716x_DEBUG, 1, "Length=%d, Count=%d, Reg=0x%02x", -+ len, -+ count, -+ reg); -+ -+ b0[0] = MSB(reg); -+ b0[1] = LSB(reg); -+ -+ /* Write */ -+ msg[0].addr = 0x50; -+ msg[0].flags = 0; -+ msg[0].buf = b0; -+ msg[0].len = 2; -+ -+ /* Read */ -+ msg[1].addr = 0x50; -+ msg[1].flags = I2C_M_RD; -+ msg[1].buf = val; -+ -+ if (i == (count - 2)) { -+ /* last message */ -+ if (len % DUMP_BYTES) { -+ msg[1].len = len % DUMP_BYTES; -+ dprintk(SAA716x_DEBUG, 1, "Last Message length=%d", len % DUMP_BYTES); -+ } else { -+ msg[1].len = DUMP_BYTES; -+ } -+ } else { -+ msg[1].len = DUMP_BYTES; -+ } -+ -+ ret = i2c_transfer(adapter, msg, 2); -+ if (ret != 2) { -+ dprintk(SAA716x_ERROR, 1, "read error ", reg, ret); -+ return -EREMOTEIO; -+ } -+ -+ reg += DUMP_BYTES; -+ val += DUMP_BYTES; -+ } -+ -+ return 0; -+} -+ -+static int saa716x_get_offset(struct saa716x_dev *saa716x, u8 *buf, u32 *offset) -+{ -+ int i; -+ -+ *offset = 0; -+ for (i = 0; i < 256; i++) { -+ if (!(strncmp("START", buf + i, 5))) -+ break; -+ } -+ dprintk(SAA716x_INFO, 1, "Offset @ %d", i); -+ *offset = i; -+ -+ return 0; -+} -+ -+static int saa716x_eeprom_header(struct saa716x_dev *saa716x, -+ struct saa716x_romhdr *rom_header, -+ u8 *buf, -+ u32 *offset) -+{ -+ memcpy(rom_header, &buf[*offset], sizeof (struct saa716x_romhdr)); -+ if (rom_header->header_size != sizeof (struct saa716x_romhdr)) { -+ dprintk(SAA716x_ERROR, 1, -+ "ERROR: Header size mismatch! Read size=%d bytes, Expected=%d", -+ (int)sizeof (struct saa716x_romhdr), -+ rom_header->header_size); -+ -+ return -1; -+ } -+ *offset += sizeof (struct saa716x_romhdr); -+ -+ dprintk(SAA716x_NOTICE, 0, "SAA%02x ROM: Data=%d bytes\n", -+ saa716x->pdev->device, -+ rom_header->data_size); -+ -+ dprintk(SAA716x_NOTICE, 0, "SAA%02x ROM: Version=%d\n", -+ saa716x->pdev->device, -+ rom_header->version); -+ -+ dprintk(SAA716x_NOTICE, 0, "SAA%02x ROM: Devices=%d\n", -+ saa716x->pdev->device, -+ rom_header->devices); -+ -+ dprintk(SAA716x_NOTICE, 0, "SAA%02x ROM: Compressed=%d\n\n", -+ saa716x->pdev->device, -+ rom_header->compression); -+ -+ return 0; -+} -+ -+int saa716x_dump_eeprom(struct saa716x_dev *saa716x) -+{ -+ struct saa716x_romhdr rom_header; -+ u8 buf[DUMP_BYTES]; -+ int i, err = 0; -+ u32 offset = 0; -+ -+ err = eeprom_read_bytes(saa716x, DUMP_OFFST, DUMP_BYTES, buf); -+ if (err < 0) { -+ dprintk(SAA716x_ERROR, 1, "EEPROM Read error"); -+ return err; -+ } -+ -+ dprintk(SAA716x_NOTICE, 0, " Card: %s\n", -+ saa716x->config->model_name); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " ---------------- SAA%02x ROM @ Offset 0x%02x ----------------", -+ saa716x->pdev->device, -+ DUMP_OFFST); -+ -+ for (i = 0; i < DUMP_BYTES; i++) { -+ if ((i % 16) == 0) { -+ dprintk(SAA716x_NOTICE, 0, "\n "); -+ dprintk(SAA716x_NOTICE, 0, "%04x: ", i); -+ } -+ -+ if ((i % 8) == 0) -+ dprintk(SAA716x_NOTICE, 0, " "); -+ if ((i % 4) == 0) -+ dprintk(SAA716x_NOTICE, 0, " "); -+ dprintk(SAA716x_NOTICE, 0, "%02x ", buf[i]); -+ } -+ dprintk(SAA716x_NOTICE, 0, "\n"); -+ dprintk(SAA716x_NOTICE, 0, -+ " ---------------- SAA%02x ROM Dump end ---------------------\n\n", -+ saa716x->pdev->device); -+ -+ err = saa716x_get_offset(saa716x, buf, &offset); -+ if (err != 0) { -+ dprintk(SAA716x_ERROR, 1, "ERROR: Descriptor not found <%d>", err); -+ return err; -+ } -+ offset += 5; -+ saa716x->id_offst = offset; -+ /* Get header */ -+ err = saa716x_eeprom_header(saa716x, &rom_header, buf, &offset); -+ if (err != 0) { -+ dprintk(SAA716x_ERROR, 1, "ERROR: Header Read failed <%d>", err); -+ return -1; -+ } -+ saa716x->id_len = rom_header.data_size; -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(saa716x_dump_eeprom); -+ -+static void saa716x_descriptor_dbg(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset, -+ u8 size, -+ u8 ext_size) -+{ -+ int i; -+ -+ dprintk(SAA716x_INFO, 0, " "); -+ for (i = 0; i < 49; i++) -+ dprintk(SAA716x_INFO, 0, "-"); -+ -+ for (i = 0; i < size + ext_size; i++) { -+ if ((i % 16) == 0) -+ dprintk(SAA716x_INFO, 0, "\n "); -+ if ((i % 8) == 0) -+ dprintk(SAA716x_INFO, 0, " "); -+ if ((i % 4) == 0) -+ dprintk(SAA716x_INFO, 0, " "); -+ -+ dprintk(SAA716x_INFO, 0, "%02x ", buf[*offset + i]); -+ } -+ -+ dprintk(SAA716x_INFO, 0, "\n "); -+ for (i = 0; i < 49; i++) -+ dprintk(SAA716x_INFO, 0, "-"); -+ dprintk(SAA716x_INFO, 0, "\n"); -+ -+} -+ -+static int saa716x_decoder_info(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset) -+{ -+ struct saa716x_decoder_hdr header; -+ -+ memcpy(&header, &buf[*offset], sizeof (struct saa716x_decoder_hdr)); -+ saa716x_descriptor_dbg(saa716x, buf, offset, header.size, header.ext_data); -+ if (header.size != sizeof (struct saa716x_decoder_hdr)) { -+ dprintk(SAA716x_ERROR, 1, -+ "ERROR: Header size mismatch! Read size=%d bytes, Expected=%d", -+ header.size, -+ (int)sizeof (struct saa716x_decoder_hdr)); -+ -+ return -1; -+ } -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Size=%d bytes\n", -+ saa716x->pdev->device, -+ header.size); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Ext Data=%d bytes\n\n", -+ saa716x->pdev->device, -+ header.ext_data); -+ -+ *offset += header.size + header.ext_data; -+ return 0; -+} -+ -+static int saa716x_gpio_info(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset) -+{ -+ struct saa716x_gpio_hdr header; -+ -+ memcpy(&header, &buf[*offset], sizeof (struct saa716x_gpio_hdr)); -+ saa716x_descriptor_dbg(saa716x, buf, offset, header.size, header.ext_data); -+ if (header.size != sizeof (struct saa716x_gpio_hdr)) { -+ dprintk(SAA716x_ERROR, 1, -+ "ERROR: Header size mismatch! Read size=%d bytes, Expected=%d", -+ header.size, -+ (int)sizeof (struct saa716x_gpio_hdr)); -+ -+ return -1; -+ } -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Size=%d bytes\n", -+ saa716x->pdev->device, -+ header.size); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Pins=%d\n", -+ saa716x->pdev->device, -+ header.pins); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Ext data=%d\n\n", -+ saa716x->pdev->device, -+ header.ext_data); -+ -+ *offset += header.size + header.ext_data; -+ -+ return 0; -+} -+ -+static int saa716x_video_decoder_info(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset) -+{ -+ struct saa716x_video_decoder_hdr header; -+ -+ memcpy(&header, &buf[*offset], sizeof (struct saa716x_video_decoder_hdr)); -+ saa716x_descriptor_dbg(saa716x, buf, offset, header.size, header.ext_data); -+ if (header.size != sizeof (struct saa716x_video_decoder_hdr)) { -+ dprintk(SAA716x_ERROR, 1, -+ "ERROR: Header size mismatch! Read size=%d bytes, Expected=%d", -+ header.size, -+ (int)sizeof (struct saa716x_video_decoder_hdr)); -+ -+ return -1; -+ } -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Size=%d bytes\n", -+ saa716x->pdev->device, -+ header.size); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: PORT 0=0x%02x\n", -+ saa716x->pdev->device, -+ header.video_port0); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: PORT 1=0x%02x\n", -+ saa716x->pdev->device, -+ header.video_port1); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: PORT 2=0x%02x\n", -+ saa716x->pdev->device, -+ header.video_port2); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: VBI PORT ID=0x%02x\n", -+ saa716x->pdev->device, -+ header.vbi_port_id); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Video PORT Type=0x%02x\n", -+ saa716x->pdev->device, -+ header.video_port_type); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: VBI PORT Type=0x%02x\n", -+ saa716x->pdev->device, -+ header.vbi_port_type); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Encoder PORT Type=0x%02x\n", -+ saa716x->pdev->device, -+ header.encoder_port_type); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Video Output=0x%02x\n", -+ saa716x->pdev->device, -+ header.video_output); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: VBI Output=0x%02x\n", -+ saa716x->pdev->device, -+ header.vbi_output); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Encoder Output=0x%02x\n", -+ saa716x->pdev->device, -+ header.encoder_output); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Ext data=%d bytes\n\n", -+ saa716x->pdev->device, -+ header.ext_data); -+ -+ *offset += header.size + header.ext_data; -+ return 0; -+} -+ -+static int saa716x_audio_decoder_info(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset) -+{ -+ struct saa716x_audio_decoder_hdr header; -+ -+ memcpy(&header, &buf[*offset], sizeof (struct saa716x_audio_decoder_hdr)); -+ saa716x_descriptor_dbg(saa716x, buf, offset, header.size, header.ext_data); -+ if (header.size != sizeof (struct saa716x_audio_decoder_hdr)) { -+ dprintk(SAA716x_ERROR, 1, -+ "ERROR: Header size mismatch! Read size=%d bytes, Expected=%d", -+ header.size, -+ (int)sizeof (struct saa716x_audio_decoder_hdr)); -+ -+ return -1; -+ } -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Size=%d bytes\n", -+ saa716x->pdev->device, -+ header.size); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Ext data=%d bytes\n\n", -+ saa716x->pdev->device, -+ header.ext_data); -+ -+ *offset += header.size + header.ext_data; -+ return 0; -+} -+ -+static int saa716x_event_source_info(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset) -+{ -+ struct saa716x_evsrc_hdr header; -+ -+ memcpy(&header, &buf[*offset], sizeof (struct saa716x_evsrc_hdr)); -+ saa716x_descriptor_dbg(saa716x, buf, offset, header.size, header.ext_data); -+ if (header.size != sizeof (struct saa716x_evsrc_hdr)) { -+ dprintk(SAA716x_ERROR, 1, -+ "ERROR: Header size mismatch! Read size=%d bytes, Expected=%d", -+ header.size, -+ (int)sizeof (struct saa716x_evsrc_hdr)); -+ -+ return -1; -+ } -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Size=%d bytes\n", -+ saa716x->pdev->device, -+ header.size); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Ext data=%d bytes\n\n", -+ saa716x->pdev->device, -+ header.ext_data); -+ -+ *offset += header.size + header.ext_data; -+ return 0; -+} -+ -+static int saa716x_crossbar_info(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset) -+{ -+ struct saa716x_xbar_hdr header; -+ struct saa716x_xbar_pair_info pair_info; -+ -+ memcpy(&header, &buf[*offset], sizeof (struct saa716x_xbar_hdr)); -+ saa716x_descriptor_dbg(saa716x, buf, offset, header.size, header.ext_data); -+ if (header.size != sizeof (struct saa716x_xbar_hdr)) { -+ dprintk(SAA716x_ERROR, 1, -+ "ERROR: Header size mismatch! Read size=%d bytes, Expected=%d", -+ header.size, -+ (int)sizeof (struct saa716x_xbar_hdr)); -+ -+ return -1; -+ } -+ -+ memcpy(&pair_info, &buf[*offset], sizeof (struct saa716x_xbar_pair_info)); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Size=%d bytes\n", -+ saa716x->pdev->device, -+ header.size); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Pairs=%d\n", -+ saa716x->pdev->device, -+ header.pair_inputs); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Ext data=%d bytes\n\n", -+ saa716x->pdev->device, -+ header.ext_data); -+ -+ *offset += header.size + header.ext_data + (sizeof (struct saa716x_xbar_pair_info) * header.pair_inputs); -+ return 0; -+} -+ -+static int saa716x_tuner_info(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset) -+{ -+ struct saa716x_tuner_hdr header; -+ -+ memcpy(&header, &buf[*offset], sizeof (struct saa716x_tuner_hdr)); -+ saa716x_descriptor_dbg(saa716x, buf, offset, header.size, header.ext_data); -+ if (header.size != sizeof (struct saa716x_tuner_hdr)) { -+ dprintk(SAA716x_ERROR, 1, -+ "ERROR: Header size mismatch! Read size=%d bytes, Expected=%d", -+ header.size, -+ (int)sizeof (struct saa716x_tuner_hdr)); -+ -+ return -1; -+ } -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Size=%d bytes\n", -+ saa716x->pdev->device, -+ header.size); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Ext data=%d bytes\n\n", -+ saa716x->pdev->device, -+ header.ext_data); -+ -+ *offset += header.size + header.ext_data; -+ return 0; -+} -+ -+static int saa716x_pll_info(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset) -+{ -+ struct saa716x_pll_hdr header; -+ -+ memcpy(&header, &buf[*offset], sizeof (struct saa716x_pll_hdr)); -+ saa716x_descriptor_dbg(saa716x, buf, offset, header.size, header.ext_data); -+ if (header.size != sizeof (struct saa716x_pll_hdr)) { -+ dprintk(SAA716x_ERROR, 1, -+ "ERROR: Header size mismatch! Read size=%d bytes, Expected=%d", -+ header.size, -+ (int)sizeof (struct saa716x_pll_hdr)); -+ -+ return -1; -+ } -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Size=%d bytes\n", -+ saa716x->pdev->device, -+ header.size); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Ext data=%d bytes\n\n", -+ saa716x->pdev->device, -+ header.ext_data); -+ -+ *offset += header.size + header.ext_data; -+ return 0; -+} -+ -+static int saa716x_channel_decoder_info(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset) -+{ -+ struct saa716x_channel_decoder_hdr header; -+ -+ memcpy(&header, &buf[*offset], sizeof (struct saa716x_channel_decoder_hdr)); -+ saa716x_descriptor_dbg(saa716x, buf, offset, header.size, header.ext_data); -+ if (header.size != sizeof (struct saa716x_channel_decoder_hdr)) { -+ dprintk(SAA716x_ERROR, 1, -+ "ERROR: Header size mismatch! Read size=%d bytes, Expected=%d", -+ header.size, -+ (int)sizeof (struct saa716x_channel_decoder_hdr)); -+ -+ return -1; -+ } -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Size=%d bytes\n", -+ saa716x->pdev->device, -+ header.size); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Ext data=%d bytes\n\n", -+ saa716x->pdev->device, -+ header.ext_data); -+ -+ *offset += header.size + header.ext_data; -+ return 0; -+} -+ -+static int saa716x_encoder_info(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset) -+{ -+ struct saa716x_encoder_hdr header; -+ -+ memcpy(&header, &buf[*offset], sizeof (struct saa716x_encoder_hdr)); -+ saa716x_descriptor_dbg(saa716x, buf, offset, header.size, header.ext_data); -+ if (header.size != sizeof (struct saa716x_encoder_hdr)) { -+ dprintk(SAA716x_ERROR, 1, -+ "ERROR: Header size mismatch! Read size=%d bytes, Expected=%d", -+ header.size, -+ (int)sizeof (struct saa716x_encoder_hdr)); -+ -+ return -1; -+ } -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Size=%d bytes\n", -+ saa716x->pdev->device, -+ header.size); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Ext data=%d bytes\n\n", -+ saa716x->pdev->device, -+ header.ext_data); -+ -+ *offset += header.size + header.ext_data; -+ return 0; -+} -+ -+static int saa716x_ir_info(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset) -+{ -+ struct saa716x_ir_hdr header; -+ -+ memcpy(&header, &buf[*offset], sizeof (struct saa716x_ir_hdr)); -+ saa716x_descriptor_dbg(saa716x, buf, offset, header.size, header.ext_data); -+ if (header.size != sizeof (struct saa716x_ir_hdr)) { -+ dprintk(SAA716x_ERROR, 1, -+ "ERROR: Header size mismatch! Read size=%d bytes, Expected=%d", -+ header.size, -+ (int)sizeof (struct saa716x_ir_hdr)); -+ -+ return -1; -+ } -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Size=%d bytes\n", -+ saa716x->pdev->device, -+ header.size); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Ext data=%d bytes\n\n", -+ saa716x->pdev->device, -+ header.ext_data); -+ -+ *offset += header.size + header.ext_data; -+ return 0; -+} -+ -+static int saa716x_eeprom_info(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset) -+{ -+ struct saa716x_eeprom_hdr header; -+ -+ memcpy(&header, &buf[*offset], sizeof (struct saa716x_eeprom_hdr)); -+ saa716x_descriptor_dbg(saa716x, buf, offset, header.size, header.ext_data); -+ if (header.size != sizeof (struct saa716x_eeprom_hdr)) { -+ dprintk(SAA716x_ERROR, 1, -+ "ERROR: Header size mismatch! Read size=%d bytes, Expected=%d", -+ header.size, -+ (int)sizeof (struct saa716x_eeprom_hdr)); -+ -+ return -1; -+ } -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Size=%d bytes\n", -+ saa716x->pdev->device, -+ header.size); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Ext data=%d bytes\n\n", -+ saa716x->pdev->device, -+ header.ext_data); -+ -+ *offset += header.size + header.ext_data; -+ return 0; -+} -+ -+static int saa716x_filter_info(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset) -+{ -+ struct saa716x_filter_hdr header; -+ -+ memcpy(&header, &buf[*offset], sizeof (struct saa716x_filter_hdr)); -+ saa716x_descriptor_dbg(saa716x, buf, offset, header.size, header.ext_data); -+ if (header.size != sizeof (struct saa716x_filter_hdr)) { -+ dprintk(SAA716x_ERROR, 1, -+ "ERROR: Header size mismatch! Read size=%d bytes, Expected=%d", -+ header.size, -+ (int)sizeof(struct saa716x_filter_hdr)); -+ -+ return -1; -+ } -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Size=%d bytes\n", -+ saa716x->pdev->device, -+ header.size); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Ext data=%d bytes\n", -+ saa716x->pdev->device, -+ header.ext_data); -+ -+ *offset += header.size + header.ext_data; -+ return 0; -+} -+ -+static int saa716x_streamdev_info(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset) -+{ -+ struct saa716x_streamdev_hdr header; -+ -+ memcpy(&header, &buf[*offset], sizeof (struct saa716x_streamdev_hdr)); -+ saa716x_descriptor_dbg(saa716x, buf, offset, header.size, header.ext_data); -+ if (header.size != sizeof (struct saa716x_streamdev_hdr)) { -+ dprintk(SAA716x_ERROR, 1, -+ "ERROR: Header size mismatch! Read size=%d bytes, Expected=%d", -+ header.size, -+ (int)sizeof(struct saa716x_streamdev_hdr)); -+ -+ return -1; -+ } -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Size=%d bytes\n", -+ saa716x->pdev->device, -+ header.size); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Ext data=%d bytes\n", -+ saa716x->pdev->device, -+ header.ext_data); -+ -+ *offset += header.size + header.ext_data; -+ return 0; -+} -+ -+static int saa716x_unknown_device_info(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset) -+{ -+ u8 size; -+ u8 ext_size = 0; -+ -+ size = buf[*offset]; -+ if (size > 1) -+ ext_size = buf[*offset + size -1]; -+ -+ saa716x_descriptor_dbg(saa716x, buf, offset, size, ext_size); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Size=%d bytes\n", -+ saa716x->pdev->device, -+ size); -+ -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Ext data=%d bytes\n\n", -+ saa716x->pdev->device, -+ ext_size); -+ -+ *offset += size + ext_size; -+ return 0; -+} -+ -+ -+static void saa716x_device_dbg(struct saa716x_dev *saa716x, -+ u8 *buf, -+ u32 *offset, -+ u8 size, -+ u8 ext_size, -+ u8 addr_size) -+{ -+ int i; -+ -+ dprintk(SAA716x_INFO, 0, " "); -+ for (i = 0; i < 53; i++) -+ dprintk(SAA716x_INFO, 0, "-"); -+ -+ for (i = 0; i < size + ext_size + addr_size; i++) { -+ if ((i % 16) == 0) -+ dprintk(SAA716x_INFO, 0, "\n "); -+ if ((i % 8) == 0) -+ dprintk(SAA716x_INFO, 0, " "); -+ if ((i % 4) == 0) -+ dprintk(SAA716x_INFO, 0, " "); -+ -+ dprintk(SAA716x_INFO, 0, "%02x ", buf[*offset + i]); -+ } -+ -+ dprintk(SAA716x_INFO, 0, "\n "); -+ for (i = 0; i < 53; i++) -+ dprintk(SAA716x_INFO, 0, "-"); -+ dprintk(SAA716x_INFO, 0, "\n"); -+ -+} -+ -+ -+static int saa716x_device_info(struct saa716x_dev *saa716x, -+ struct saa716x_devinfo *device, -+ u8 *buf, -+ u32 *offset) -+{ -+ u8 address = 0; -+ -+ memcpy(device, &buf[*offset], sizeof(struct saa716x_devinfo)); -+ if (device->struct_size != sizeof(struct saa716x_devinfo)) { -+ dprintk(SAA716x_ERROR, 1, "ERROR: Device size mismatch! Read=%d bytes, expected=%d bytes", -+ device->struct_size, -+ (int)sizeof(struct saa716x_devinfo)); -+ -+ return -1; -+ } -+ -+ saa716x_device_dbg(saa716x, -+ buf, -+ offset, -+ device->struct_size, -+ device->extd_data_size, -+ device->addr_size); -+ -+ *offset += device->struct_size; -+ -+ if (device->addr_size) { -+ address = buf[*offset]; -+ address >>= 1; -+ *offset += device->addr_size; -+ } -+ -+ dprintk(SAA716x_NOTICE, 0, " SAA%02x ROM: Device @ 0x%02x\n", -+ saa716x->pdev->device, -+ address); -+ -+ dprintk(SAA716x_NOTICE, 0, " SAA%02x ROM: Size=%d bytes\n", -+ saa716x->pdev->device, -+ device->struct_size); -+ -+ dprintk(SAA716x_NOTICE, 0, " SAA%02x ROM: Device ID=0x%02x\n", -+ saa716x->pdev->device, -+ device->device_id); -+ -+ dprintk(SAA716x_NOTICE, 0, " SAA%02x ROM: Master ID=0x%02x\n", -+ saa716x->pdev->device, -+ device->master_devid); -+ -+ dprintk(SAA716x_NOTICE, 0, " SAA%02x ROM: Bus ID=0x%02x\n", -+ saa716x->pdev->device, -+ device->master_busid); -+ -+ dprintk(SAA716x_NOTICE, 0, " SAA%02x ROM: Device type=0x%02x\n", -+ saa716x->pdev->device, -+ device->device_type); -+ -+ dprintk(SAA716x_NOTICE, 0, " SAA%02x ROM: Implementation ID=0x%02x\n", -+ saa716x->pdev->device, -+ device->implem_id); -+ -+ dprintk(SAA716x_NOTICE, 0, " SAA%02x ROM: Path ID=0x%02x\n", -+ saa716x->pdev->device, -+ device->path_id); -+ -+ dprintk(SAA716x_NOTICE, 0, " SAA%02x ROM: GPIO ID=0x%02x\n", -+ saa716x->pdev->device, -+ device->gpio_id); -+ -+ dprintk(SAA716x_NOTICE, 0, " SAA%02x ROM: Address=%d bytes\n", -+ saa716x->pdev->device, -+ device->addr_size); -+ -+ dprintk(SAA716x_NOTICE, 0, " SAA%02x ROM: Extended data=%d bytes\n\n", -+ saa716x->pdev->device, -+ device->extd_data_size); -+ -+ if (device->extd_data_size) { -+ u32 mask; -+ -+ mask = 0x00000001; -+ while (mask) { -+ if (device->device_type & mask) { -+ switch (mask) { -+ case DECODER_DEVICE: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found decoder device\n", -+ saa716x->pdev->device); -+ -+ saa716x_decoder_info(saa716x, buf, offset); -+ break; -+ -+ case GPIO_SOURCE: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found GPIO device\n", -+ saa716x->pdev->device); -+ -+ saa716x_gpio_info(saa716x, buf, offset); -+ break; -+ -+ case VIDEO_DECODER: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found Video Decoder device\n", -+ saa716x->pdev->device); -+ -+ saa716x_video_decoder_info(saa716x, buf, offset); -+ break; -+ -+ case AUDIO_DECODER: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found Audio Decoder device\n", -+ saa716x->pdev->device); -+ -+ saa716x_audio_decoder_info(saa716x, buf, offset); -+ break; -+ -+ case EVENT_SOURCE: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found Event source\n", -+ saa716x->pdev->device); -+ -+ saa716x_event_source_info(saa716x, buf, offset); -+ break; -+ -+ case CROSSBAR: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found Crossbar device\n", -+ saa716x->pdev->device); -+ -+ saa716x_crossbar_info(saa716x, buf, offset); -+ break; -+ -+ case TUNER_DEVICE: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found Tuner device\n", -+ saa716x->pdev->device); -+ -+ saa716x_tuner_info(saa716x, buf, offset); -+ break; -+ -+ case PLL_DEVICE: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found PLL device\n", -+ saa716x->pdev->device); -+ -+ saa716x_pll_info(saa716x, buf, offset); -+ break; -+ -+ case CHANNEL_DECODER: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found Channel Demodulator device\n", -+ saa716x->pdev->device); -+ -+ saa716x_channel_decoder_info(saa716x, buf, offset); -+ break; -+ -+ case RDS_DECODER: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found RDS Decoder device\n", -+ saa716x->pdev->device); -+ -+ saa716x_unknown_device_info(saa716x, buf, offset); -+ break; -+ -+ case ENCODER_DEVICE: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found Encoder device\n", -+ saa716x->pdev->device); -+ -+ saa716x_encoder_info(saa716x, buf, offset); -+ break; -+ -+ case IR_DEVICE: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found IR device\n", -+ saa716x->pdev->device); -+ -+ saa716x_ir_info(saa716x, buf, offset); -+ break; -+ -+ case EEPROM_DEVICE: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found EEPROM device\n", -+ saa716x->pdev->device); -+ -+ saa716x_eeprom_info(saa716x, buf, offset); -+ break; -+ -+ case NOISE_FILTER: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found Noise filter device\n", -+ saa716x->pdev->device); -+ -+ saa716x_filter_info(saa716x, buf, offset); -+ break; -+ -+ case LNx_DEVICE: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found LNx device\n", -+ saa716x->pdev->device); -+ -+ saa716x_unknown_device_info(saa716x, buf, offset); -+ break; -+ -+ case STREAM_DEVICE: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found streaming device\n", -+ saa716x->pdev->device); -+ -+ saa716x_streamdev_info(saa716x, buf, offset); -+ break; -+ -+ case CONFIGSPACE_DEVICE: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found Configspace device\n", -+ saa716x->pdev->device); -+ -+ saa716x_unknown_device_info(saa716x, buf, offset); -+ break; -+ -+ default: -+ dprintk(SAA716x_NOTICE, 0, -+ " SAA%02x ROM: Found unknown device\n", -+ saa716x->pdev->device); -+ -+ saa716x_unknown_device_info(saa716x, buf, offset); -+ break; -+ } -+ } -+ mask <<= 1; -+ } -+ } -+ -+ dprintk(SAA716x_NOTICE, 0, "\n"); -+ -+ return 0; -+} -+ -+int saa716x_eeprom_data(struct saa716x_dev *saa716x) -+{ -+ struct saa716x_romhdr rom_header; -+ struct saa716x_devinfo *device; -+ -+ u8 buf[1024]; -+ int i, ret = 0; -+ u32 offset = 0; -+ -+ /* dump */ -+ ret = saa716x_read_rombytes(saa716x, saa716x->id_offst, saa716x->id_len + 8, buf); -+ if (ret < 0) { -+ dprintk(SAA716x_ERROR, 1, "EEPROM Read error <%d>", ret); -+ goto err0; -+ } -+ -+ /* Get header */ -+ ret = saa716x_eeprom_header(saa716x, &rom_header, buf, &offset); -+ if (ret != 0) { -+ dprintk(SAA716x_ERROR, 1, "ERROR: Header Read failed <%d>", ret); -+ goto err0; -+ } -+ -+ /* allocate for device info */ -+ device = kzalloc(sizeof (struct saa716x_devinfo) * rom_header.devices, GFP_KERNEL); -+ if (device == NULL) { -+ dprintk(SAA716x_ERROR, 1, "ERROR: out of memory"); -+ goto err0; -+ } -+ -+ for (i = 0; i < rom_header.devices; i++) { -+ dprintk(SAA716x_NOTICE, 0, " SAA%02x ROM: ===== Device %d =====\n", -+ saa716x->pdev->device, -+ i); -+ -+ ret = saa716x_device_info(saa716x, &device[i], buf, &offset); -+ if (ret != 0) { -+ dprintk(SAA716x_ERROR, 1, "ERROR: Device info read failed <%d>", ret); -+ goto err1; -+ } -+ } -+ -+ kfree(device); -+ -+ return 0; -+ -+err1: -+ kfree(device); -+ -+err0: -+ return ret; -+} -+EXPORT_SYMBOL_GPL(saa716x_eeprom_data); -diff --git a/drivers/media/common/saa716x/saa716x_rom.h b/drivers/media/common/saa716x/saa716x_rom.h -new file mode 100644 -index 0000000..6bb317f ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_rom.h -@@ -0,0 +1,253 @@ -+#ifndef __SAA716x_ROM_H -+#define __SAA716x_ROM_H -+ -+ -+#define MSB(__x) ((__x >> 8) & 0xff) -+#define LSB(__x) (__x & 0xff) -+ -+#define DUMP_BYTES 0xf0 -+#define DUMP_OFFST 0x000 -+ -+struct saa716x_dev; -+ -+struct saa716x_romhdr { -+ u16 header_size; -+ u8 compression; -+ u8 version; -+ u16 data_size; -+ u8 devices; -+ u8 checksum; -+} __attribute__((packed)); -+ -+struct saa716x_devinfo { -+ u8 struct_size; -+ u8 device_id; -+ u8 master_devid; -+ u8 master_busid; -+ u32 device_type; -+ u16 implem_id; -+ u8 path_id; -+ u8 gpio_id; -+ u16 addr_size; -+ u16 extd_data_size; -+} __attribute__((packed)); -+ -+enum saa716x_device_types { -+ DECODER_DEVICE = 0x00000001, -+ GPIO_SOURCE = 0x00000002, -+ VIDEO_DECODER = 0x00000004, -+ AUDIO_DECODER = 0x00000008, -+ EVENT_SOURCE = 0x00000010, -+ CROSSBAR = 0x00000020, -+ TUNER_DEVICE = 0x00000040, -+ PLL_DEVICE = 0x00000080, -+ CHANNEL_DECODER = 0x00000100, -+ RDS_DECODER = 0x00000200, -+ ENCODER_DEVICE = 0x00000400, -+ IR_DEVICE = 0x00000800, -+ EEPROM_DEVICE = 0x00001000, -+ NOISE_FILTER = 0x00002000, -+ LNx_DEVICE = 0x00004000, -+ STREAM_DEVICE = 0x00010000, -+ CONFIGSPACE_DEVICE = 0x80000000 -+}; -+ -+struct saa716x_decoder_hdr { -+ u8 size; -+ u8 ext_data; -+}; -+ -+struct saa716x_decoder_info { -+ struct saa716x_decoder_hdr decoder_hdr; -+ u8 *ext_data; -+}; -+ -+struct saa716x_gpio_hdr { -+ u8 size; -+ u8 pins; -+ u8 rsvd; -+ u8 ext_data; -+}; -+ -+struct saa716x_gpio_info { -+ struct saa716x_gpio_hdr gpio_hdr; -+ u8 *ext_data; -+}; -+ -+struct saa716x_video_decoder_hdr { -+ u8 size; -+ u8 video_port0; -+ u8 video_port1; -+ u8 video_port2; -+ u8 vbi_port_id; -+ u8 video_port_type; -+ u8 vbi_port_type; -+ u8 encoder_port_type; -+ u8 video_output; -+ u8 vbi_output; -+ u8 encoder_output; -+ u8 ext_data; -+}; -+ -+struct saa716x_video_decoder_info { -+ struct saa716x_video_decoder_hdr decoder_hdr; -+ u8 *ext_data; -+}; -+ -+struct saa716x_audio_decoder_hdr { -+ u8 size; -+ u8 port; -+ u8 output; -+ u8 ext_data; -+}; -+ -+struct saa716x_audio_decoder_info { -+ struct saa716x_audio_decoder_hdr decoder_hdr; -+ u8 *ext_data; -+}; -+ -+struct saa716x_evsrc_hdr { -+ u8 size; -+ u8 master_devid; -+ u16 condition_id; -+ u8 rsvd; -+ u8 ext_data; -+}; -+ -+struct saa716x_evsrc_info { -+ struct saa716x_evsrc_hdr evsrc_hdr; -+ u8 *ext_data; -+}; -+ -+enum saa716x_input_pair_type { -+ TUNER_SIF = 0x00, -+ TUNER_LINE = 0x01, -+ TUNER_SPDIF = 0x02, -+ TUNER_NONE = 0x03, -+ CVBS_LINE = 0x04, -+ CVBS_SPDIF = 0x05, -+ CVBS_NONE = 0x06, -+ YC_LINE = 0x07, -+ YC_SPDIF = 0x08, -+ YC_NONE = 0x09, -+ YPbPr_LINE = 0x0a, -+ YPbPr_SPDIF = 0x0b, -+ YPbPr_NONE = 0x0c, -+ NO_LINE = 0x0d, -+ NO_SPDIF = 0x0e, -+ RGB_LINE = 0x0f, -+ RGB_SPDIF = 0x10, -+ RGB_NONE = 0x11 -+}; -+ -+struct saa716x_xbar_pair_info { -+ u8 pair_input_type; -+ u8 video_input_id; -+ u8 audio_input_id; -+}; -+ -+struct saa716x_xbar_hdr { -+ u8 size; -+ u8 pair_inputs; -+ u8 pair_route_default; -+ u8 ext_data; -+}; -+ -+struct saa716x_xbar_info { -+ struct saa716x_xbar_hdr xbar_hdr; -+ struct saa716x_xbar_pair_info *pair_info; -+ u8 *ext_data; -+}; -+ -+struct saa716x_tuner_hdr { -+ u8 size; -+ u8 ext_data; -+}; -+ -+struct saa716x_tuner_info { -+ struct saa716x_tuner_hdr tuner_hdr; -+ u8 *ext_data; -+}; -+ -+struct saa716x_pll_hdr { -+ u8 size; -+ u8 ext_data; -+}; -+ -+struct saa716x_pll_info { -+ struct saa716x_pll_hdr pll_hdr; -+ u8 *ext_data; -+}; -+ -+struct saa716x_channel_decoder_hdr { -+ u8 size; -+ u8 port; -+ u8 ext_data; -+}; -+ -+struct saa716x_channel_decoder_info { -+ struct saa716x_channel_decoder_hdr channel_dec_hdr; -+ u8 *ext_data; -+}; -+ -+struct saa716x_encoder_hdr { -+ u8 size; -+ u8 stream_port0; -+ u8 stream_port1; -+ u8 ext_data; -+}; -+ -+struct saa716x_encoder_info { -+ struct saa716x_encoder_hdr encoder_hdr; -+ u8 *ext_data; -+}; -+ -+struct saa716x_ir_hdr { -+ u8 size; -+ u8 ir_caps; -+ u8 ext_data; -+}; -+ -+struct saa716x_ir_info { -+ struct saa716x_ir_hdr ir_hdr; -+ u8 *ext_data; -+}; -+ -+struct saa716x_eeprom_hdr { -+ u8 size; -+ u8 rel_device; -+ u8 ext_data; -+}; -+ -+struct saa716x_eeprom_info { -+ struct saa716x_eeprom_hdr eeprom_hdr; -+ u8 *ext_data; -+}; -+ -+struct saa716x_filter_hdr { -+ u8 size; -+ u8 video_decoder; -+ u8 audio_decoder; -+ u8 event_source; -+ u8 ext_data; -+}; -+ -+struct saa716x_filter_info { -+ struct saa716x_filter_hdr filter_hdr; -+ u8 *ext_data; -+}; -+ -+struct saa716x_streamdev_hdr { -+ u8 size; -+ u8 ext_data; -+}; -+ -+struct saa716x_streamdev_info { -+ struct saa716x_streamdev_hdr streamdev_hdr; -+ u8 *ext_data; -+}; -+ -+extern int saa716x_dump_eeprom(struct saa716x_dev *saa716x); -+extern int saa716x_eeprom_data(struct saa716x_dev *saa716x); -+ -+#endif /* __SAA716x_ROM_H */ -diff --git a/drivers/media/common/saa716x/saa716x_spi.c b/drivers/media/common/saa716x/saa716x_spi.c -new file mode 100644 -index 0000000..8859454 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_spi.c -@@ -0,0 +1,313 @@ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "saa716x_mod.h" -+ -+#include "saa716x_spi_reg.h" -+#include "saa716x_spi.h" -+#include "saa716x_priv.h" -+ -+#if 0 // not needed atm -+int saa716x_spi_irqevent(struct saa716x_dev *saa716x) -+{ -+ u32 stat, mask; -+ -+ BUG_ON(saa716x == NULL); -+ -+ stat = SAA716x_EPRD(SPI, SPI_STATUS); -+ mask = SAA716x_EPRD(SPI, SPI_CONTROL_REG) & SPI_SERIAL_INTER_ENABLE; -+ if ((!stat && !mask)) -+ return -1; -+ -+ dprintk(SAA716x_DEBUG, 0, "SPI event: Stat=<%02x>", stat); -+ -+ if (stat & SPI_TRANSFER_FLAG) -+ dprintk(SAA716x_DEBUG, 0, " "); -+ if (stat & SPI_WRITE_COLLISSION) -+ dprintk(SAA716x_DEBUG, 0, " "); -+ if (stat & SPI_READ_OVERRUN) -+ dprintk(SAA716x_DEBUG, 0, " "); -+ if (stat & SPI_MODE_FAULT) -+ dprintk(SAA716x_DEBUG, 0, " "); -+ if (stat & SPI_SLAVE_ABORT) -+ dprintk(SAA716x_DEBUG, 0, " "); -+ -+ return 0; -+} -+#endif -+ -+void saa716x_spi_write(struct saa716x_dev *saa716x, const u8 *data, int length) -+{ -+ int i; -+ u32 value; -+ int rounds; -+ -+ for (i = 0; i < length; i++) { -+ SAA716x_EPWR(SPI, SPI_DATA, data[i]); -+ rounds = 0; -+ value = SAA716x_EPRD(SPI, SPI_STATUS); -+ -+ while ((value & SPI_TRANSFER_FLAG) == 0 && rounds < 5000) { -+ value = SAA716x_EPRD(SPI, SPI_STATUS); -+ rounds++; -+ } -+ } -+} -+EXPORT_SYMBOL_GPL(saa716x_spi_write); -+ -+#if 0 // not needed atm -+static int saa716x_spi_status(struct saa716x_dev *saa716x, u32 *status) -+{ -+ u32 stat; -+ -+ stat = SAA716x_EPRD(SPI, SPI_STATUS); -+ -+ if (stat & SPI_TRANSFER_FLAG) -+ dprintk(SAA716x_DEBUG, 1, "Transfer complete <%02x>", stat); -+ -+ if (stat & SPI_WRITE_COLLISSION) -+ dprintk(SAA716x_DEBUG, 1, "Write collission <%02x>", stat); -+ -+ if (stat & SPI_READ_OVERRUN) -+ dprintk(SAA716x_DEBUG, 1, "Read Overrun <%02x>", stat); -+ -+ if (stat & SPI_MODE_FAULT) -+ dprintk(SAA716x_DEBUG, 1, "MODE fault <%02x>", stat); -+ -+ if (stat & SPI_SLAVE_ABORT) -+ dprintk(SAA716x_DEBUG, 1, "SLAVE abort <%02x>", stat); -+ -+ *status = stat; -+ -+ return 0; -+} -+ -+#define SPI_CYCLE_TIMEOUT 100 -+ -+static int saa716x_spi_xfer(struct saa716x_dev *saa716x, u32 *data) -+{ -+ u32 i, status = 0; -+ -+ /* write data and wait for completion */ -+ SAA716x_EPWR(SPI, SPI_DATA, data[i]); -+ for (i = 0; i < SPI_CYCLE_TIMEOUT; i++) { -+ msleep(10); -+ saa716x_spi_status(saa716x, &status); -+#if 0 -+ if (status & SPI_TRANSFER_FLAG) { -+ data = SAA716x_EPRD(SPI, SPI_DATA); -+ return 0; -+ } -+#endif -+ if (status & (SPI_WRITE_COLLISSION | -+ SPI_READ_OVERRUN | -+ SPI_MODE_FAULT | -+ SPI_SLAVE_ABORT)) -+ -+ return -EIO; -+ } -+ -+ return -EIO; -+} -+ -+#if 0 -+static int saa716x_spi_wr(struct saa716x_dev *saa716x, const u8 *data, int length) -+{ -+ struct saa716x_spi_config *config = saa716x->spi_config; -+ u32 gpio_mask; -+ int ret = 0; -+ -+ // protect against multiple access -+ spin_lock(&saa716x->gpio_lock); -+ -+ // configure the module -+ saa716x_spi_config(saa716x); -+ -+ // check input -+ -+ // change polarity of GPIO if active high -+ if (config->active_hi) { -+ select = 1; -+ release = 0; -+ } -+ -+ // configure GPIO, first set output register to low selected level -+ saa716x_gpio_write(saa716x, gpio, select); -+ -+ // set mode register to register controlled (0) -+ gpio_mask = (1 << gpio); -+ saa716x_set_gpio_mode(saa716x, gpio_mask, 0); -+ -+ // configure bit as output (0) -+ saa716x_gpio_ctl(saa716x, gpio_mask, 0); -+ -+ // wait at least 500ns before sending a byte -+ msleep(1); -+ -+ // send command -+ for (i = 0; i < dwCommandSize; i++) { -+ ucData = 0; -+// dwStatus = TransferData(pucCommand[i], &ucData); -+ ret = saa716x_spi_xfer(saa716x); -+ //tmDBGPRINTEx(4,("Info: Command 0x%x ", pucCommand[i] )); -+ -+ /* If command length > 1, disable CS at the end of each command. -+ * But after the last command byte CS must be left active! -+ */ -+ if ((dwCommandSize > 1) && (i < dwCommandSize - 1)) { -+ -+ saa716x_gpio_write(saa716x, gpio, release); -+ msleep(1); /* 500 nS minimum */ -+ saa716x_gpio_write(saa716x, gpio, select); -+ } -+ -+ if (ret != 0) { -+ dprintk(SAA716x_ERROR, 1, "ERROR: Command transfer failed"); -+ msleep(1); /* 500 nS minimum */ -+ saa716x_gpio_write(saa716x, gpio, release); /* release GPIO */ -+ spin_unlock(&saa716x->spi_lock); -+ return ret; -+ } -+ -+ if (config->LSB_first) -+ dwTransferByte++; -+ else -+ dwTransferByte--; -+ } -+ -+// assume that the byte order is the same as the bit order -+ -+// send read address -+ -+// send data -+ -+// wait at least 500ns before releasing slave -+ -+// release GPIO pin -+ -+ // release spinlock -+ spin_unlock(&saa716x->gpio_lock); -+} -+#endif -+ -+#define MODEBITS (SPI_CPOL | SPI_CPHA) -+ -+static int saa716x_spi_setup(struct spi_device *spi) -+{ -+ struct spi_master *master = spi->master; -+ struct saa716x_spi_state *saa716x_spi = spi_master_get_devdata(master); -+ struct saa716x_dev *saa716x = saa716x_spi->saa716x; -+ struct saa716x_spi_config *config = &saa716x->spi_config; -+ -+ u8 control = 0; -+ -+ if (spi->mode & ~MODEBITS) { -+ dprintk(SAA716x_ERROR, 1, "ERROR: Unsupported MODE bits <%x>", -+ spi->mode & ~MODEBITS); -+ -+ return -EINVAL; -+ } -+ -+ SAA716x_EPWR(SPI, SPI_CLOCK_COUNTER, config->clk_count); -+ -+ control |= SPI_MODE_SELECT; /* SPI Master */ -+ -+ if (config->LSB_first) -+ control |= SPI_LSB_FIRST_ENABLE; -+ -+ if (config->clk_pol) -+ control |= SPI_CLOCK_POLARITY; -+ -+ if (config->clk_pha) -+ control |= SPI_CLOCK_PHASE; -+ -+ SAA716x_EPWR(SPI, SPI_CONTROL_REG, control); -+ -+ return 0; -+} -+ -+static void saa716x_spi_cleanup(struct spi_device *spi) -+{ -+ -+} -+ -+static int saa716x_spi_transfer(struct spi_device *spi, struct spi_message *msg) -+{ -+ struct spi_master *master = spi->master; -+ struct saa716x_spi_state *saa716x_spi = spi_master_get_devdata(master); -+ struct saa716x_dev *saa716x = saa716x_spi->saa716x; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&saa716x->gpio_lock, flags); -+#if 0 -+ if (saa716x_spi->run == QUEUE_STOPPED) { -+ spin_unlock_irqrestore(&saa716x_spi->lock, flags); -+ return -ESHUTDOWN; -+ } -+ -+ msg->actual_length = 0; -+ msg->status = -EINPROGRESS; -+ msg->state = START_STATE; -+ -+ list_add_tail(&msg->queue, &saa716x_spi->queue); -+ -+ if (saa716x_spi->run == QUEUE_RUNNING && !saa716x_spi->busy) -+ queue_work(saa716x_spi->workqueue, &saa716x_spi->pump_messages); -+#endif -+ spin_unlock_irqrestore(&saa716x->gpio_lock, flags); -+ -+ return 0; -+} -+ -+int saa716x_spi_init(struct saa716x_dev *saa716x) -+{ -+ struct pci_dev *pdev = saa716x->pdev; -+ struct spi_master *master; -+ struct saa716x_spi_state *saa716x_spi; -+ int ret; -+ -+ dprintk(SAA716x_DEBUG, 1, "Initializing SAA%02x I2C Core", -+ saa716x->pdev->device); -+ -+ master = spi_alloc_master(&pdev->dev, sizeof (struct saa716x_spi_state)); -+ if (master == NULL) { -+ dprintk(SAA716x_ERROR, 1, "ERROR: Cannot allocate SPI Master!"); -+ return -ENOMEM; -+ } -+ -+ saa716x_spi = spi_master_get_devdata(master); -+ saa716x_spi->master = master; -+ saa716x_spi->saa716x = saa716x; -+ saa716x->saa716x_spi = saa716x_spi; -+ -+ master->bus_num = pdev->bus->number; -+ master->num_chipselect = 1; /* TODO! use config */ -+ master->cleanup = saa716x_spi_cleanup; -+ master->setup = saa716x_spi_setup; -+ master->transfer = saa716x_spi_transfer; -+ -+ ret = spi_register_master(master); -+ if (ret != 0) { -+ dprintk(SAA716x_ERROR, 1, "ERROR: registering SPI Master!"); -+ goto err; -+ } -+err: -+ spi_master_put(master); -+ return ret; -+} -+EXPORT_SYMBOL(saa716x_spi_init); -+ -+void saa716x_spi_exit(struct saa716x_dev *saa716x) -+{ -+ struct saa716x_spi_state *saa716x_spi = saa716x->saa716x_spi; -+ -+ spi_unregister_master(saa716x_spi->master); -+ dprintk(SAA716x_DEBUG, 1, "SAA%02x SPI succesfully removed", saa716x->pdev->device); -+} -+EXPORT_SYMBOL(saa716x_spi_exit); -+#endif -+ -diff --git a/drivers/media/common/saa716x/saa716x_spi.h b/drivers/media/common/saa716x/saa716x_spi.h -new file mode 100644 -index 0000000..0060c22 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_spi.h -@@ -0,0 +1,23 @@ -+#ifndef __SAA716x_SPI_H -+#define __SAA716x_SPI_H -+ -+struct saa716x_dev; -+ -+struct saa716x_spi_config { -+ u8 clk_count; -+ u8 clk_pol:1; -+ u8 clk_pha:1; -+ u8 LSB_first:1; -+}; -+ -+struct saa716x_spi_state { -+ struct spi_master *master; -+ struct saa716x_dev *saa716x; -+}; -+ -+extern void saa716x_spi_write(struct saa716x_dev *saa716x, const u8 *data, int length); -+ -+extern int saa716x_spi_init(struct saa716x_dev *saa716x); -+extern void saa716x_spi_exit(struct saa716x_dev *saa716x); -+ -+#endif /* __SAA716x_SPI_H */ -diff --git a/drivers/media/common/saa716x/saa716x_spi_reg.h b/drivers/media/common/saa716x/saa716x_spi_reg.h -new file mode 100644 -index 0000000..c51abce ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_spi_reg.h -@@ -0,0 +1,27 @@ -+#ifndef __SAA716x_SPI_REG_H -+#define __SAA716x_SPI_REG_H -+ -+/* -------------- SPI Registers -------------- */ -+ -+#define SPI_CONTROL_REG 0x000 -+#define SPI_SERIAL_INTER_ENABLE (0x00000001 << 7) -+#define SPI_LSB_FIRST_ENABLE (0x00000001 << 6) -+#define SPI_MODE_SELECT (0x00000001 << 5) -+#define SPI_CLOCK_POLARITY (0x00000001 << 4) -+#define SPI_CLOCK_PHASE (0x00000001 << 3) -+ -+#define SPI_STATUS 0x004 -+#define SPI_TRANSFER_FLAG (0x00000001 << 7) -+#define SPI_WRITE_COLLISSION (0x00000001 << 6) -+#define SPI_READ_OVERRUN (0x00000001 << 5) -+#define SPI_MODE_FAULT (0x00000001 << 4) -+#define SPI_SLAVE_ABORT (0x00000001 << 3) -+ -+#define SPI_DATA 0x008 -+#define SPI_BIDI_DATA (0x000000ff << 0) -+ -+#define SPI_CLOCK_COUNTER 0x00c -+#define SPI_CLOCK (0x00000001 << 0) -+ -+ -+#endif /* __SAA716x_SPI_REG_H */ -diff --git a/drivers/media/common/saa716x/saa716x_vip.c b/drivers/media/common/saa716x/saa716x_vip.c -new file mode 100644 -index 0000000..4cd4c81 ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_vip.c -@@ -0,0 +1,23 @@ -+#include -+ -+#include "saa716x_mod.h" -+ -+#include "saa716x_vip_reg.h" -+#include "saa716x_spi.h" -+#include "saa716x_priv.h" -+ -+void saa716x_vipint_disable(struct saa716x_dev *saa716x) -+{ -+ SAA716x_EPWR(VI0, INT_ENABLE, 0); /* disable VI 0 IRQ */ -+ SAA716x_EPWR(VI1, INT_ENABLE, 0); /* disable VI 1 IRQ */ -+ SAA716x_EPWR(VI0, INT_CLR_STATUS, 0x3ff); /* clear IRQ */ -+ SAA716x_EPWR(VI1, INT_CLR_STATUS, 0x3ff); /* clear IRQ */ -+} -+EXPORT_SYMBOL_GPL(saa716x_vipint_disable); -+ -+void saa716x_vip_disable(struct saa716x_dev *saa716x) -+{ -+ SAA716x_EPWR(VI0, VIP_POWER_DOWN, VI_PWR_DWN); -+ SAA716x_EPWR(VI1, VIP_POWER_DOWN, VI_PWR_DWN); -+} -+EXPORT_SYMBOL_GPL(saa716x_vip_disable); -diff --git a/drivers/media/common/saa716x/saa716x_vip.h b/drivers/media/common/saa716x/saa716x_vip.h -new file mode 100644 -index 0000000..55c6a1a ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_vip.h -@@ -0,0 +1,9 @@ -+#ifndef __SAA716x_VIP_H -+#define __SAA716x_VIP_H -+ -+struct saa716x_dev; -+ -+extern void saa716x_vipint_disable(struct saa716x_dev *saa716x); -+extern void saa716x_vip_disable(struct saa716x_dev *saa716x); -+ -+#endif /* __SAA716x_VIP_H */ -diff --git a/drivers/media/common/saa716x/saa716x_vip_reg.h b/drivers/media/common/saa716x/saa716x_vip_reg.h -new file mode 100644 -index 0000000..2d773bd ---- /dev/null -+++ b/drivers/media/common/saa716x/saa716x_vip_reg.h -@@ -0,0 +1,127 @@ -+#ifndef __SAA716x_VIP_REG_H -+#define __SAA716x_VIP_REG_H -+ -+/* -------------- VIP Registers -------------- */ -+ -+#define VI_MODE 0x000 -+#define VID_CFEN (0x00000003 << 30) -+#define VID_OSM (0x00000001 << 29) -+#define VID_FSEQ (0x00000001 << 28) -+#define AUX_CFEN (0x00000003 << 26) -+#define AUX_OSM (0x00000001 << 25) -+#define AUX_FSEQ (0x00000001 << 24) -+#define AUX_ANC_DATA (0x00000003 << 22) -+#define AUX_ANC_RAW (0x00000001 << 21) -+#define RST_ON_ERR (0x00000001 << 17) -+#define SOFT_RESET (0x00000001 << 16) -+#define IFF_CLAMP (0x00000001 << 14) -+#define IFF_MODE (0x00000003 << 12) -+#define DFF_CLAMP (0x00000001 << 10) -+#define DFF_MODE (0x00000003 << 8) -+#define HSP_CLAMP (0x00000001 << 3) -+#define HSP_RGB (0x00000001 << 2) -+#define HSP_MODE (0x00000003 << 0) -+ -+#define RCRB_CTRL 0x004 -+#define RCRB_CFG_ADDR 0x008 -+#define RCRB_CFG_EXT_ADDR 0x00c -+#define RCRB_IO_ADDR 0x010 -+#define RCRB_MEM_LADDR 0x014 -+#define RCRB_MEM_UADDR 0x018 -+#define RCRB_DATA 0x01c -+#define RCRB_MASK 0x020 -+#define RCRB_MSG_HDR 0x040 -+#define RCRB_MSG_PL0 0x044 -+#define RCRB_MSG_PL1 0x048 -+ -+#define ID_MASK0 0x020 -+#define VI_ID_MASK_0 (0x000000ff << 8) -+#define VI_DATA_ID_0 (0x000000ff << 0) -+ -+#define ID_MASK1 0x024 -+#define VI_ID_MASK_1 (0x000000ff << 8) -+#define VI_DATA_ID_1 (0x000000ff << 0) -+ -+#define VIP_LINE_THRESH 0x040 -+#define VI_LCTHR (0x000007ff << 0) -+ -+#define VIN_FORMAT 0x100 -+#define VI_VSRA (0x00000003 << 30) -+#define VI_SYNCHD (0x00000001 << 25) -+#define VI_DUAL_STREAM (0x00000001 << 24) -+#define VI_NHDAUX (0x00000001 << 20) -+#define VI_NPAR (0x00000001 << 19) -+#define VI_VSEL (0x00000003 << 14) -+#define VI_TWOS (0x00000001 << 13) -+#define VI_TPG (0x00000001 << 12) -+#define VI_FREF (0x00000001 << 10) -+#define VI_FTGL (0x00000001 << 9) -+#define VI_SF (0x00000001 << 3) -+#define VI_FZERO (0x00000001 << 2) -+#define VI_REVS (0x00000001 << 1) -+#define VI_REHS (0x00000001 << 0) -+ -+#define TC76543210 0x800 -+#define TCFEDCBA98 0x804 -+#define PHYCFG 0x900 -+#define CONFIG 0xfd4 -+#define INT_ENABLE_CLR 0xfd8 -+#define INT_ENABLE_SET 0xfdc -+ -+ -+#define INT_STATUS 0xfe0 -+#define VI_STAT_FID_AUX (0x00000001 << 31) -+#define VI_STAT_FID_VID (0x00000001 << 30) -+#define VI_STAT_FID_VPI (0x00000001 << 29) -+#define VI_STAT_LINE_COUNT (0x00000fff << 16) -+#define VI_STAT_AUX_OVRFLW (0x00000001 << 9) -+#define VI_STAT_VID_OVRFLW (0x00000001 << 8) -+#define VI_STAT_WIN_SEQBRK (0x00000001 << 7) -+#define VI_STAT_FID_SEQBRK (0x00000001 << 6) -+#define VI_STAT_LINE_THRESH (0x00000001 << 5) -+#define VI_STAT_AUX_WRAP (0x00000001 << 4) -+#define VI_STAT_AUX_START_IN (0x00000001 << 3) -+#define VI_STAT_AUX_END_OUT (0x00000001 << 2) -+#define VI_STAT_VID_START_IN (0x00000001 << 1) -+#define VI_STAT_VID_END_OUT (0x00000001 << 0) -+ -+#define INT_ENABLE 0xfe4 -+#define VI_ENABLE_AUX_OVRFLW (0x00000001 << 9) -+#define VI_ENABLE_VID_OVRFLW (0x00000001 << 8) -+#define VI_ENABLE_WIN_SEQBRK (0x00000001 << 7) -+#define VI_ENABLE_FID_SEQBRK (0x00000001 << 6) -+#define VI_ENABLE_LINE_THRESH (0x00000001 << 5) -+#define VI_ENABLE_AUX_WRAP (0x00000001 << 4) -+#define VI_ENABLE_AUX_START_IN (0x00000001 << 3) -+#define VI_ENABLE_AUX_END_OUT (0x00000001 << 2) -+#define VI_ENABLE_VID_START_IN (0x00000001 << 1) -+#define VI_ENABLE_VID_END_OUT (0x00000001 << 0) -+ -+#define INT_CLR_STATUS 0xfe8 -+#define VI_CLR_STATUS_AUX_OVRFLW (0x00000001 << 9) -+#define VI_CLR_STATUS_VID_OVRFLW (0x00000001 << 8) -+#define VI_CLR_STATUS_WIN_SEQBRK (0x00000001 << 7) -+#define VI_CLR_STATUS_FID_SEQBRK (0x00000001 << 6) -+#define VI_CLR_STATUS_LINE_THRESH (0x00000001 << 5) -+#define VI_CLR_STATUS_AUX_WRAP (0x00000001 << 4) -+#define VI_CLR_STATUS_AUX_START_IN (0x00000001 << 3) -+#define VI_CLR_STATUS_AUX_END_OUT (0x00000001 << 2) -+#define VI_CLR_STATUS_VID_START_IN (0x00000001 << 1) -+#define VI_CLR_STATUS_VID_END_OUT (0x00000001 << 0) -+ -+#define INT_SET_STATUS 0xfec -+#define VI_SET_STATUS_AUX_OVRFLW (0x00000001 << 9) -+#define VI_SET_STATUS_VID_OVRFLW (0x00000001 << 8) -+#define VI_SET_STATUS_WIN_SEQBRK (0x00000001 << 7) -+#define VI_SET_STATUS_FID_SEQBRK (0x00000001 << 6) -+#define VI_SET_STATUS_LINE_THRESH (0x00000001 << 5) -+#define VI_SET_STATUS_AUX_WRAP (0x00000001 << 4) -+#define VI_SET_STATUS_AUX_START_IN (0x00000001 << 3) -+#define VI_SET_STATUS_AUX_END_OUT (0x00000001 << 2) -+#define VI_SET_STATUS_VID_START_IN (0x00000001 << 1) -+#define VI_SET_STATUS_VID_END_OUT (0x00000001 << 0) -+ -+#define VIP_POWER_DOWN 0xff4 -+#define VI_PWR_DWN (0x00000001 << 31) -+ -+#endif /* __SAA716x_VIP_REG_H */ -diff --git a/drivers/media/dvb-frontends/ds3103.h b/drivers/media/dvb-frontends/ds3103.h -new file mode 100644 -index 0000000..e52740c ---- /dev/null -+++ b/drivers/media/dvb-frontends/ds3103.h -@@ -0,0 +1,47 @@ -+/* -+ Montage Technology DS3103 - DVBS/S2 Demodulator driver -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 2 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+*/ -+ -+#ifndef DS3103_H -+#define DS3103_H -+ -+#include -+ -+struct ds3103_config { -+ /* the demodulator's i2c address */ -+ u8 demod_address; -+ u8 ci_mode; -+ /* Set device param to start dma */ -+ int (*set_ts_params)(struct dvb_frontend *fe, int is_punctured); -+ /* Hook for Lock LED */ -+ void (*set_lock_led)(struct dvb_frontend *fe, int offon); -+}; -+ -+#if defined(CONFIG_DVB_DS3103) || \ -+ (defined(CONFIG_DVB_DS3103_MODULE) && defined(MODULE)) -+extern struct dvb_frontend *ds3103_attach(const struct ds3103_config *config, -+ struct i2c_adapter *i2c); -+#else -+static inline -+struct dvb_frontend *ds3103_attach(const struct ds3103_config *config, -+ struct i2c_adapter *i2c) -+{ -+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); -+ return NULL; -+} -+#endif /* CONFIG_DVB_DS3103 */ -+#endif /* DS3103_H */ -diff --git a/drivers/media/dvb-frontends/ts2022.h b/drivers/media/dvb-frontends/ts2022.h -new file mode 100644 -index 0000000..c894edb ---- /dev/null -+++ b/drivers/media/dvb-frontends/ts2022.h -@@ -0,0 +1,51 @@ -+ /* -+ Driver for Montage TS2022 DVBS/S2 Silicon tuner -+ -+ Copyright (C) 2012 Tomazzo Muzumici -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 2 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ -+ */ -+ -+#ifndef __DVB_TS2022_H__ -+#define __DVB_TS2022_H__ -+ -+#include -+#include "dvb_frontend.h" -+ -+/** -+ * Attach a ts2022 tuner to the supplied frontend structure. -+ * -+ * @param fe Frontend to attach to. -+ * @param addr i2c address of the tuner. -+ * @param i2c i2c adapter to use. -+ * @return FE pointer on success, NULL on failure. -+ */ -+#if defined(CONFIG_DVB_TS2022) || (defined(CONFIG_DVB_TS2022_MODULE) \ -+ && defined(MODULE)) -+extern struct dvb_frontend *ts2022_attach(struct dvb_frontend *fe, int addr, -+ struct i2c_adapter *i2c); -+#else -+static inline struct dvb_frontend *ts2022_attach(struct dvb_frontend *fe, -+ int addr, -+ struct i2c_adapter *i2c) -+{ -+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); -+ return NULL; -+} -+#endif /* CONFIG_DVB_TS2022 */ -+ -+#endif /* __DVB_TS2022_H__ */ -diff --git a/include/uapi/linux/dvb/osd.h b/include/uapi/linux/dvb/osd.h -index 880e684..edd728c 100644 ---- a/include/uapi/linux/dvb/osd.h -+++ b/include/uapi/linux/dvb/osd.h -@@ -141,4 +141,20 @@ typedef struct osd_cap_s { - #define OSD_SEND_CMD _IOW('o', 160, osd_cmd_t) - #define OSD_GET_CAPABILITY _IOR('o', 161, osd_cap_t) - -+typedef struct osd_raw_cmd_s { -+ const void __user *cmd_data; -+ int cmd_len; -+ void __user *result_data; -+ int result_len; -+} osd_raw_cmd_t; -+ -+typedef struct osd_raw_data_s { -+ const void __user *data_buffer; -+ int data_length; -+ int data_handle; -+} osd_raw_data_t; -+ -+#define OSD_RAW_CMD _IOWR('o', 162, osd_raw_cmd_t) -+#define OSD_RAW_DATA _IOWR('o', 163, osd_raw_data_t) -+ - #endif diff --git a/packages/linux/patches/3.11.6/linux-990.06-hda-Avoid-outputting-HDMI-audio-before-prepare-.patch b/packages/linux/patches/3.11.6/linux-990.06-hda-Avoid-outputting-HDMI-audio-before-prepare-.patch deleted file mode 100644 index 93bf4fbef1..0000000000 --- a/packages/linux/patches/3.11.6/linux-990.06-hda-Avoid-outputting-HDMI-audio-before-prepare-.patch +++ /dev/null @@ -1,78 +0,0 @@ -commit aad0b407edfef6e2527a9bb877ce754e1efb7b10 -Author: Stefan Saraev -Date: Mon Jul 1 13:06:10 2013 +0300 - - ALSA: hda - Avoid outputting HDMI audio before prepare() and after close() - - adapted to 3.10 - - From a6024295fd3290a8c9c5519a03316081ee82378a Mon Sep 17 00:00:00 2001 - From: Anssi Hannula - Date: Sat, 16 Feb 2013 17:42:46 +0200 - Subject: [PATCH] ALSA: hda - Avoid outputting HDMI audio before prepare() and - after close() - - Some HDMI codecs (at least NVIDIA 0x10de000b:0x10de0101:0x100100) start - transmitting an empty audio stream as soon as PIN_OUT and AC_DIG1_ENABLE - are enabled. - - Since commit 6169b673618bf0b2518ce413b54925782a603f06 ("ALSA: hda - - Always turn on pins for HDMI/DP") this happens at first open() time, and - will continue even after close(). - - Additionally, some codecs (at least Intel PantherPoint HDMI) currently - continue transmitting HDMI audio even after close() in case some actual - audio was output after open() (this happens regardless of PIN_OUT). - - Empty HDMI audio transmission when not intended has the effect that a - possible HDMI audio sink/receiver may prefer the empty HDMI audio stream - over an actual audio stream on its S/PDIF inputs. - - To avoid the issue before first prepare(), set stream format to 0 on - codec initialization. 0 is not a valid format value for HDMI and will - prevent the audio stream from being output. - - Additionally, at close() time, make sure that the stream is cleaned up. - This will ensure that the format is reset to 0 at that time, preventing - audio from being output in that case. - - Thanks to OpenELEC developers and users for their help in investigating - this issue on the affected NVIDIA "ION2" hardware. Testing of the final - version on NVIDIA ION2 was done by OpenELEC user "MrXIII". Testing on - Intel PantherPoint was done by myself. - - Signed-off-by: Anssi Hannula - Cc: stable@vger.kernel.org - -diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c -index e12f7a0..9bfdd51 100644 ---- a/sound/pci/hda/patch_hdmi.c -+++ b/sound/pci/hda/patch_hdmi.c -@@ -1360,6 +1360,14 @@ static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) - if (err < 0) - return err; - -+ /* -+ * Some HDMI codecs (at least NVIDIA 0x10de000b:0x10de0101:0x100100) -+ * start transmitting an empty audio stream as soon as PIN_OUT and -+ * AC_DIG1_ENABLE are enabled, which happens at open() time. -+ * To avoid that, set format to 0, which is not valid for HDMI. -+ */ -+ snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_STREAM_FORMAT, 0); -+ - if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) - spec->cvt_nids[spec->num_cvts] = cvt_nid; - spec->num_cvts++; -@@ -1474,6 +1482,12 @@ static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, - struct hdmi_spec_per_pin *per_pin; - - if (hinfo->nid) { -+ /* -+ * Make sure no empty audio is output after this point by -+ * setting stream format to 0, which is not valid for HDMI. -+ */ -+ __snd_hda_codec_cleanup_stream(codec, hinfo->nid, 1); -+ - cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid); - if (snd_BUG_ON(cvt_idx < 0)) - return -EINVAL; diff --git a/packages/linux/patches/3.11.6/linux-990.11-ALSA-AMD-HD-Audio.patch b/packages/linux/patches/3.11.6/linux-990.11-ALSA-AMD-HD-Audio.patch deleted file mode 100644 index 1408681da3..0000000000 --- a/packages/linux/patches/3.11.6/linux-990.11-ALSA-AMD-HD-Audio.patch +++ /dev/null @@ -1,805 +0,0 @@ -Combined patch for ATI/AMD HDMI. - -Actual patchset has been posted to ALSA-devel. - --- -Anssi Hannula - -diff --git a/sound/pci/hda/hda_eld.c b/sound/pci/hda/hda_eld.c -index d0d7ac1e..750841e 100644 ---- a/sound/pci/hda/hda_eld.c -+++ b/sound/pci/hda/hda_eld.c -@@ -2,6 +2,7 @@ - * Generic routines and proc interface for ELD(EDID Like Data) information - * - * Copyright(c) 2008 Intel Corporation. -+ * Copyright (c) 2013 Anssi Hannula - * - * Authors: - * Wu Fengguang -@@ -316,6 +317,9 @@ int snd_hdmi_get_eld_size(struct hda_codec *codec, hda_nid_t nid) - AC_DIPSIZE_ELD_BUF); - } - -+static int atihdmi_get_eld(struct hda_codec *codec, hda_nid_t nid, -+ unsigned char *buf, int *eld_size); -+ - int snd_hdmi_get_eld(struct hda_codec *codec, hda_nid_t nid, - unsigned char *buf, int *eld_size) - { -@@ -323,6 +327,9 @@ int snd_hdmi_get_eld(struct hda_codec *codec, hda_nid_t nid, - int ret = 0; - int size; - -+ if (is_atihdmi(codec)) -+ return atihdmi_get_eld(codec, nid, buf, eld_size); -+ - /* - * ELD size is initialized to zero in caller function. If no errors and - * ELD is valid, actual eld_size is assigned. -@@ -671,3 +678,153 @@ void snd_hdmi_eld_update_pcm_info(struct parsed_hdmi_eld *e, - hinfo->maxbps = min(hinfo->maxbps, maxbps); - hinfo->channels_max = min(hinfo->channels_max, channels_max); - } -+ -+ -+/* ATI/AMD specific stuff (ELD emulation) */ -+ -+#define ATI_VERB_SET_AUDIO_DESCRIPTOR 0x776 -+#define ATI_VERB_SET_SINK_INFO_INDEX 0x780 -+#define ATI_VERB_GET_SPEAKER_ALLOCATION 0xf70 -+#define ATI_VERB_GET_AUDIO_DESCRIPTOR 0xf76 -+#define ATI_VERB_GET_AUDIO_VIDEO_DELAY 0xf7b -+#define ATI_VERB_GET_SINK_INFO_INDEX 0xf80 -+#define ATI_VERB_GET_SINK_INFO_DATA 0xf81 -+ -+#define ATI_SPKALLOC_SPKALLOC 0x007f -+#define ATI_SPKALLOC_TYPE_HDMI 0x0100 -+#define ATI_SPKALLOC_TYPE_DISPLAYPORT 0x0200 -+ -+/* first three bytes are just standard SAD */ -+#define ATI_AUDIODESC_CHANNELS 0x00000007 -+#define ATI_AUDIODESC_RATES 0x0000ff00 -+#define ATI_AUDIODESC_LPCM_STEREO_RATES 0xff000000 -+ -+/* in standard HDMI VSDB format */ -+#define ATI_DELAY_VIDEO_LATENCY 0x000000ff -+#define ATI_DELAY_AUDIO_LATENCY 0x0000ff00 -+ -+enum ati_sink_info_idx { -+ ATI_INFO_IDX_MANUFACTURER_ID = 0, -+ ATI_INFO_IDX_PRODUCT_ID = 1, -+ ATI_INFO_IDX_SINK_DESC_LEN = 2, -+ ATI_INFO_IDX_PORT_ID_LOW = 3, -+ ATI_INFO_IDX_PORT_ID_HIGH = 4, -+ ATI_INFO_IDX_SINK_DESC_FIRST = 5, -+ ATI_INFO_IDX_SINK_DESC_LAST = 22, /* max len 18 bytes */ -+}; -+ -+static int atihdmi_get_eld(struct hda_codec *codec, hda_nid_t nid, -+ unsigned char *buf, int *eld_size) -+{ -+ int spkalloc, ati_sad, aud_synch; -+ int sink_desc_len = 0; -+ int pos, i; -+ -+ /* ATI/AMD does not have ELD, emulate it */ -+ -+ spkalloc = snd_hda_codec_read(codec, nid, 0, ATI_VERB_GET_SPEAKER_ALLOCATION, 0); -+ -+ if (!spkalloc) { -+ snd_printd(KERN_INFO "HDMI ATI/AMD: no speaker allocation for ELD\n"); -+ return -EINVAL; -+ } -+ -+ memset(buf, 0, ELD_FIXED_BYTES + ELD_MAX_MNL + ELD_MAX_SAD * 3); -+ -+ /* version */ -+ buf[0] = ELD_VER_CEA_861D << 3; -+ -+ /* speaker allocation from EDID */ -+ buf[7] = spkalloc & ATI_SPKALLOC_SPKALLOC; -+ -+ /* is DisplayPort? */ -+ if (spkalloc & ATI_SPKALLOC_TYPE_DISPLAYPORT) -+ buf[5] |= 0x04; -+ -+ pos = ELD_FIXED_BYTES; -+ -+ if (is_amdhdmi_rev3(codec)) { -+ int sink_info; -+ -+ snd_hda_codec_write(codec, nid, 0, ATI_VERB_SET_SINK_INFO_INDEX, ATI_INFO_IDX_PORT_ID_LOW); -+ sink_info = snd_hda_codec_read(codec, nid, 0, ATI_VERB_GET_SINK_INFO_DATA, 0); -+ put_unaligned_le32(sink_info, buf + 8); -+ -+ snd_hda_codec_write(codec, nid, 0, ATI_VERB_SET_SINK_INFO_INDEX, ATI_INFO_IDX_PORT_ID_HIGH); -+ sink_info = snd_hda_codec_read(codec, nid, 0, ATI_VERB_GET_SINK_INFO_DATA, 0); -+ put_unaligned_le32(sink_info, buf + 12); -+ -+ snd_hda_codec_write(codec, nid, 0, ATI_VERB_SET_SINK_INFO_INDEX, ATI_INFO_IDX_MANUFACTURER_ID); -+ sink_info = snd_hda_codec_read(codec, nid, 0, ATI_VERB_GET_SINK_INFO_DATA, 0); -+ put_unaligned_le16(sink_info, buf + 16); -+ -+ snd_hda_codec_write(codec, nid, 0, ATI_VERB_SET_SINK_INFO_INDEX, ATI_INFO_IDX_PRODUCT_ID); -+ sink_info = snd_hda_codec_read(codec, nid, 0, ATI_VERB_GET_SINK_INFO_DATA, 0); -+ put_unaligned_le16(sink_info, buf + 18); -+ -+ snd_hda_codec_write(codec, nid, 0, ATI_VERB_SET_SINK_INFO_INDEX, ATI_INFO_IDX_SINK_DESC_LEN); -+ sink_desc_len = snd_hda_codec_read(codec, nid, 0, ATI_VERB_GET_SINK_INFO_DATA, 0); -+ -+ if (sink_desc_len > ELD_MAX_MNL) { -+ snd_printd(KERN_INFO "HDMI ATI/AMD: Truncating HDMI sink description with length %d\n", -+ sink_desc_len); -+ sink_desc_len = ELD_MAX_MNL; -+ } -+ -+ buf[4] |= sink_desc_len; -+ -+ for (i = 0; i < sink_desc_len; i++) { -+ snd_hda_codec_write(codec, nid, 0, ATI_VERB_SET_SINK_INFO_INDEX, ATI_INFO_IDX_SINK_DESC_FIRST + i); -+ buf[pos++] = snd_hda_codec_read(codec, nid, 0, ATI_VERB_GET_SINK_INFO_DATA, 0); -+ } -+ } -+ -+ for (i = AUDIO_CODING_TYPE_LPCM; i <= AUDIO_CODING_TYPE_WMAPRO; i++) { -+ if (i == AUDIO_CODING_TYPE_SACD || i == AUDIO_CODING_TYPE_DST) -+ continue; /* not handled by ATI/AMD */ -+ -+ snd_hda_codec_write(codec, nid, 0, ATI_VERB_SET_AUDIO_DESCRIPTOR, i << 3); -+ ati_sad = snd_hda_codec_read(codec, nid, 0, ATI_VERB_GET_AUDIO_DESCRIPTOR, 0); -+ -+ if (ati_sad & ATI_AUDIODESC_RATES) { -+ /* format is supported, copy SAD as-is */ -+ buf[pos++] = (ati_sad & 0x0000ff) >> 0; -+ buf[pos++] = (ati_sad & 0x00ff00) >> 8; -+ buf[pos++] = (ati_sad & 0xff0000) >> 16; -+ } -+ -+ if (i == AUDIO_CODING_TYPE_LPCM -+ && (ati_sad & ATI_AUDIODESC_LPCM_STEREO_RATES) -+ && (ati_sad & ATI_AUDIODESC_LPCM_STEREO_RATES) >> 16 != (ati_sad & ATI_AUDIODESC_RATES)) { -+ /* for PCM there is a separate stereo rate mask */ -+ buf[pos++] = ((ati_sad & 0x000000ff) & ~ATI_AUDIODESC_CHANNELS) | 0x1; -+ /* rates from the extra byte */ -+ buf[pos++] = (ati_sad & 0xff000000) >> 24; -+ buf[pos++] = (ati_sad & 0x00ff0000) >> 16; -+ } -+ } -+ -+ if (pos == ELD_FIXED_BYTES + sink_desc_len) { -+ snd_printd(KERN_INFO "HDMI ATI/AMD: no audio descriptors for ELD\n"); -+ return -EINVAL; -+ } -+ -+ aud_synch = snd_hda_codec_read(codec, nid, 0, ATI_VERB_GET_AUDIO_VIDEO_DELAY, 0); -+ if ((aud_synch & ATI_DELAY_VIDEO_LATENCY) && (aud_synch & ATI_DELAY_AUDIO_LATENCY)) { -+ int video_latency = (aud_synch & ATI_DELAY_VIDEO_LATENCY) - 1; -+ int audio_latency = ((aud_synch & ATI_DELAY_AUDIO_LATENCY) >> 8) - 1; -+ -+ if (video_latency > audio_latency) -+ buf[6] = min(video_latency - audio_latency, 0xfa); -+ } -+ -+ /* Baseline length */ -+ buf[2] = pos - 4; -+ -+ /* SAD count */ -+ buf[5] |= ((pos - ELD_FIXED_BYTES - sink_desc_len) / 3) << 4; -+ -+ *eld_size = pos; -+ -+ return 0; -+} -diff --git a/sound/pci/hda/hda_local.h b/sound/pci/hda/hda_local.h -index 2e7493e..7c0b89e 100644 ---- a/sound/pci/hda/hda_local.h -+++ b/sound/pci/hda/hda_local.h -@@ -786,4 +786,9 @@ static inline void snd_hda_eld_proc_free(struct hda_codec *codec, - #define SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE 80 - void snd_print_channel_allocation(int spk_alloc, char *buf, int buflen); - -+/* shared with patch_hdmi.c and hda_eld.c */ -+#define is_atihdmi(codec) (((codec)->vendor_id & 0xffff0000) == 0x10020000) -+#define is_amdhdmi_rev3(codec) \ -+ ((codec)->vendor_id == 0x1002aa01 && ((codec)->revision_id & 0xff00) >= 0x0300) -+ - #endif /* __SOUND_HDA_LOCAL_H */ -diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c -index 3d8cd044..22f30fe 100644 ---- a/sound/pci/hda/patch_hdmi.c -+++ b/sound/pci/hda/patch_hdmi.c -@@ -6,6 +6,7 @@ - * Copyright (c) 2006 ATI Technologies Inc. - * Copyright (c) 2008 NVIDIA Corp. All rights reserved. - * Copyright (c) 2008 Wei Ni -+ * Copyright (c) 2013 Anssi Hannula - * - * Authors: - * Wu Fengguang -@@ -46,6 +47,9 @@ MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); - - #define is_haswell(codec) ((codec)->vendor_id == 0x80862807) - -+/* is_atihdmi() and is_amdhdmi_rev3() are in hda_local.h */ -+#define has_amd_full_remap_support(codec) is_amdhdmi_rev3(codec) -+ - struct hdmi_spec_per_cvt { - hda_nid_t cvt_nid; - int assigned; -@@ -89,7 +93,7 @@ struct hdmi_spec { - - struct hdmi_eld temp_eld; - /* -- * Non-generic ATI/NVIDIA specific -+ * Non-generic VIA/NVIDIA specific - */ - struct hda_multi_out multiout; - struct hda_pcm_stream pcm_playback; -@@ -573,6 +577,20 @@ static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels) - return ca; - } - -+#ifdef CONFIG_SND_DEBUG_VERBOSE -+static int atihdmi_get_chan_slot(struct hda_codec *codec, hda_nid_t pin_nid, int asp_slot); -+ -+static int hdmi_get_chan_slot(struct hda_codec *codec, hda_nid_t pin_nid, int asp_slot) -+{ -+ if (is_atihdmi(codec)) -+ return atihdmi_get_chan_slot(codec, pin_nid, asp_slot); -+ -+ return snd_hda_codec_read(codec, pin_nid, 0, -+ AC_VERB_GET_HDMI_CHAN_SLOT, -+ asp_slot); -+} -+#endif -+ - static void hdmi_debug_channel_mapping(struct hda_codec *codec, - hda_nid_t pin_nid) - { -@@ -581,14 +599,26 @@ static void hdmi_debug_channel_mapping(struct hda_codec *codec, - int slot; - - for (i = 0; i < 8; i++) { -- slot = snd_hda_codec_read(codec, pin_nid, 0, -- AC_VERB_GET_HDMI_CHAN_SLOT, i); -+ slot = hdmi_get_chan_slot(codec, pin_nid, i); - printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n", - slot >> 4, slot & 0xf); - } - #endif - } - -+static int atihdmi_set_chan_slot(struct hda_codec *codec, hda_nid_t pin_nid, -+ int chanslot_setup); -+ -+static int hdmi_set_chan_slot(struct hda_codec *codec, hda_nid_t pin_nid, -+ int chanslot_setup) -+{ -+ if (is_atihdmi(codec)) -+ return atihdmi_set_chan_slot(codec, pin_nid, chanslot_setup); -+ -+ return snd_hda_codec_write(codec, pin_nid, 0, -+ AC_VERB_SET_HDMI_CHAN_SLOT, -+ chanslot_setup); -+} - - static void hdmi_std_setup_channel_mapping(struct hda_codec *codec, - hda_nid_t pin_nid, -@@ -617,9 +647,8 @@ static void hdmi_std_setup_channel_mapping(struct hda_codec *codec, - } - - for (i = 0; i < 8; i++) { -- err = snd_hda_codec_write(codec, pin_nid, 0, -- AC_VERB_SET_HDMI_CHAN_SLOT, -- non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]); -+ err = hdmi_set_chan_slot(codec, pin_nid, -+ non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i]); - if (err) { - snd_printdd(KERN_NOTICE - "HDMI: channel mapping failed\n"); -@@ -728,8 +757,7 @@ static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec, - else - val = 0xf; - val |= (i << 4); -- err = snd_hda_codec_write(codec, pin_nid, 0, -- AC_VERB_SET_HDMI_CHAN_SLOT, val); -+ err = hdmi_set_chan_slot(codec, pin_nid, val); - if (err) - return -EINVAL; - } -@@ -883,6 +911,8 @@ static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, - return true; - } - -+static void atihdmi_set_ca(struct hda_codec *codec, hda_nid_t pin_nid, int ca); -+ - static void hdmi_setup_audio_infoframe(struct hda_codec *codec, - struct hdmi_spec_per_pin *per_pin, - bool non_pcm) -@@ -912,6 +942,16 @@ static void hdmi_setup_audio_infoframe(struct hda_codec *codec, - if (ca < 0) - ca = 0; - -+ if (is_atihdmi(codec)) { -+ /* for ATI/AMD we just want to map channels and set ca */ -+ hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca, -+ channels, per_pin->chmap, -+ per_pin->chmap_set); -+ atihdmi_set_ca(codec, pin_nid, ca); -+ per_pin->non_pcm = non_pcm; -+ return; -+ } -+ - memset(&ai, 0, sizeof(ai)); - if (eld->info.conn_type == 0) { /* HDMI */ - struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; -@@ -1100,7 +1140,7 @@ static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, - new_pinctl); - - } -- if (is_hbr_format(format) && !new_pinctl) { -+ if (is_hbr_format(format) && !new_pinctl && !is_atihdmi(codec)) { - snd_printdd("hdmi_setup_stream: HBR is not supported\n"); - return -EINVAL; - } -@@ -1603,6 +1643,8 @@ static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol, - return 0; - } - -+static int atihdmi_swap_fc_lfe(int pos); -+ - static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag, - unsigned int size, unsigned int __user *tlv) - { -@@ -1613,6 +1655,10 @@ static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag, - FL | FR | RL | RR | LFE | FC | RLC | RRC; - unsigned int __user *dst; - int chs, count = 0; -+ int tlv_type = SNDRV_CTL_TLVT_CHMAP_VAR; -+ -+ if (is_atihdmi(codec) && !has_amd_full_remap_support(codec)) -+ tlv_type = SNDRV_CTL_TLVT_CHMAP_PAIRED; - - if (size < 8) - return -ENOMEM; -@@ -1620,19 +1666,35 @@ static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag, - return -EFAULT; - size -= 8; - dst = tlv + 2; -- for (chs = 2; chs <= spec->channels_max; chs++) { -+ for (chs = 2; chs <= spec->channels_max; -+ chs += (tlv_type == SNDRV_CTL_TLVT_CHMAP_PAIRED) ? 2 : 1) { - int i, c; - struct cea_channel_speaker_allocation *cap; - cap = channel_allocations; - for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) { - int chs_bytes = chs * 4; -- if (cap->channels != chs) -+ -+ if (tlv_type == SNDRV_CTL_TLVT_CHMAP_PAIRED) { -+ int chanpairs = 0; -+ /* in paired mode we need to take into account -+ * the occupied channel pairs instead of just the -+ * channel count */ -+ for (c = 0; c < 7; c += 2) { -+ if (cap->speakers[c] || cap->speakers[c+1]) -+ chanpairs++; -+ } -+ if (chanpairs * 2 != chs) -+ continue; -+ -+ } else if (cap->channels != chs) - continue; -+ - if (cap->spk_mask & ~valid_mask) - continue; - if (size < 8) - return -ENOMEM; -- if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) || -+ -+ if (put_user(tlv_type, dst) || - put_user(chs_bytes, dst + 1)) - return -EFAULT; - dst += 2; -@@ -1643,10 +1705,27 @@ static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag, - size -= chs_bytes; - count += chs_bytes; - for (c = 7; c >= 0; c--) { -- int spk = cap->speakers[c]; -- if (!spk) -- continue; -- if (put_user(spk_to_chmap(spk), dst)) -+ int spk; -+ int chan = c; -+ int chpos; -+ -+ if (tlv_type == SNDRV_CTL_TLVT_CHMAP_PAIRED) -+ chan = 7 - atihdmi_swap_fc_lfe(7 - chan); -+ -+ spk = cap->speakers[chan]; -+ if (spk) -+ chpos = spk_to_chmap(spk); -+ else { -+ /* We need to reserve an N/A channel in paired mode -+ * if the companion channel is occupied. */ -+ if (tlv_type == SNDRV_CTL_TLVT_CHMAP_PAIRED -+ && cap->speakers[chan + (chan % 2 ? -1 : 1)]) -+ chpos = SNDRV_CHMAP_NA; -+ else -+ continue; -+ } -+ -+ if (put_user(chpos, dst)) - return -EFAULT; - dst++; - } -@@ -1672,6 +1751,18 @@ static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol, - return 0; - } - -+static int atihdmi_pairwise_chmap_check_order(struct hda_codec *codec, int ca, -+ int chs, unsigned char *map); -+ -+static int hdmi_chmap_check_order(struct hda_codec *codec, int ca, -+ int chs, unsigned char *map) -+{ -+ if (is_atihdmi(codec) && !has_amd_full_remap_support(codec)) -+ return atihdmi_pairwise_chmap_check_order(codec, ca, chs, map); -+ -+ return 0; /* anything can be remapped as needed */ -+} -+ - static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) - { -@@ -1683,7 +1774,7 @@ static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol, - unsigned int ctl_idx; - struct snd_pcm_substream *substream; - unsigned char chmap[8]; -- int i, ca, prepared = 0; -+ int i, err, ca, prepared = 0; - - ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); - substream = snd_pcm_chmap_substream(info, ctl_idx); -@@ -1707,6 +1798,9 @@ static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol, - ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap); - if (ca < 0) - return -EINVAL; -+ err = hdmi_chmap_check_order(codec, ca, ARRAY_SIZE(chmap), chmap); -+ if (err < 0) -+ return -EINVAL; - per_pin->chmap_set = true; - memcpy(per_pin->chmap, chmap, sizeof(chmap)); - if (prepared) -@@ -2551,13 +2645,182 @@ static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) - - /* - * ATI-specific implementations -- * -- * FIXME: we may omit the whole this and use the generic code once after -- * it's confirmed to work. - */ - --#define ATIHDMI_CVT_NID 0x02 /* audio converter */ --#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */ -+/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ -+#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 -+#define ATI_VERB_SET_DOWNMIX_INFO 0x772 -+#define ATI_VERB_SET_MULTICHANNEL_01 0x777 -+#define ATI_VERB_SET_MULTICHANNEL_23 0x778 -+#define ATI_VERB_SET_MULTICHANNEL_45 0x779 -+#define ATI_VERB_SET_MULTICHANNEL_67 0x77a -+#define ATI_VERB_SET_HBR_CONTROL 0x77c -+#define ATI_VERB_SET_MULTICHANNEL_1 0x785 -+#define ATI_VERB_SET_MULTICHANNEL_3 0x786 -+#define ATI_VERB_SET_MULTICHANNEL_5 0x787 -+#define ATI_VERB_SET_MULTICHANNEL_7 0x788 -+#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 -+#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 -+#define ATI_VERB_GET_DOWNMIX_INFO 0xf72 -+#define ATI_VERB_GET_MULTICHANNEL_01 0xf77 -+#define ATI_VERB_GET_MULTICHANNEL_23 0xf78 -+#define ATI_VERB_GET_MULTICHANNEL_45 0xf79 -+#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a -+#define ATI_VERB_GET_HBR_CONTROL 0xf7c -+#define ATI_VERB_GET_MULTICHANNEL_1 0xf85 -+#define ATI_VERB_GET_MULTICHANNEL_3 0xf86 -+#define ATI_VERB_GET_MULTICHANNEL_5 0xf87 -+#define ATI_VERB_GET_MULTICHANNEL_7 0xf88 -+#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 -+ -+/* AMD specific HDA cvt verbs */ -+#define ATI_VERB_SET_RAMP_RATE 0x770 -+#define ATI_VERB_GET_RAMP_RATE 0xf70 -+ -+#define ATI_OUT_ENABLE 0x1 -+ -+#define ATI_HBR_CAPABLE 0x01 -+#define ATI_HBR_ENABLE 0x10 -+ -+static void atihdmi_set_ca(struct hda_codec *codec, hda_nid_t pin_nid, int ca) -+{ -+ printk("ATI: setting ca %d\n", ca); -+ snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); -+} -+ -+static int atihdmi_swap_fc_lfe(int pos) -+{ -+ /* -+ * Older ATI/AMD without channel-wise mapping -+ * have automatic FC/LFE swap built-in. -+ */ -+ -+ switch (pos) { -+ /* see channel_allocations[].speakers[] */ -+ case 2: return 3; -+ case 3: return 2; -+ default: break; -+ } -+ -+ return pos; -+} -+ -+static int atihdmi_pairwise_chmap_check_order(struct hda_codec *codec, int ca, -+ int chs, unsigned char *map) -+{ -+ struct cea_channel_speaker_allocation *cap; -+ int i, j; -+ -+ /* check that only channel pairs need to be remapped on old ATI/AMD */ -+ -+ cap = &channel_allocations[get_channel_allocation_order(ca)]; -+ for (i = 0; i < chs; ++i) { -+ int mask = to_spk_mask(map[i]); -+ bool ok = false; -+ bool companion_ok = false; -+ -+ if (!mask) -+ continue; -+ -+ for (j = 0 + i % 2; j < 8; j += 2) { -+ int chan_idx = 7 - atihdmi_swap_fc_lfe(j); -+ if (cap->speakers[chan_idx] == mask) { -+ /* channel is in a supported position */ -+ ok = true; -+ -+ if (i % 2 == 0 && i + 1 < chs) { -+ /* even channel, check the odd companion */ -+ int comp_chan_idx = 7 - atihdmi_swap_fc_lfe(j + 1); -+ int comp_mask_req = to_spk_mask(map[i+1]); -+ int comp_mask_act = cap->speakers[comp_chan_idx]; -+ -+ if (comp_mask_req == comp_mask_act) -+ companion_ok = true; -+ else -+ return -EINVAL; -+ } -+ break; -+ } -+ } -+ -+ if (!ok) -+ return -EINVAL; -+ -+ if (companion_ok) -+ i++; /* companion channel already checked */ -+ } -+ -+ return 0; -+} -+ -+static int atihdmi_set_chan_slot(struct hda_codec *codec, hda_nid_t pin_nid, -+ int chanslot_setup) -+{ -+ int hdmi_slot = chanslot_setup & 0xf; -+ int stream_channel = chanslot_setup >> 4; -+ int verb; -+ int ati_channel_setup = 0; -+ -+ if (hdmi_slot > 7) -+ return -EINVAL; -+ -+ if (!has_amd_full_remap_support(codec)) { -+ hdmi_slot = atihdmi_swap_fc_lfe(hdmi_slot); -+ -+ /* In case this is an odd slot but without stream channel, do not -+ * disable the slot since the corresponding even slot could have a -+ * channel. In case neither have a channel, the slot pair will be -+ * disabled when this function is called for the even slot. */ -+ if (hdmi_slot % 2 != 0 && stream_channel == 0xf) -+ return 0; -+ -+ hdmi_slot -= hdmi_slot % 2; -+ -+ if (stream_channel != 0xf) -+ stream_channel -= stream_channel % 2; -+ } -+ -+ verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; -+ -+ /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ -+ -+ if (stream_channel != 0xf) -+ ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; -+ -+ return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); -+} -+ -+#ifdef CONFIG_SND_DEBUG_VERBOSE -+static int atihdmi_get_chan_slot(struct hda_codec *codec, hda_nid_t pin_nid, int asp_slot) -+{ -+ bool was_odd = false; -+ int ati_asp_slot = asp_slot; -+ int verb; -+ int ati_channel_setup; -+ -+ /* emulate AC_VERB_GET_HDMI_CHAN_SLOT */ -+ -+ if (asp_slot > 7) -+ return -EINVAL; -+ -+ if (!has_amd_full_remap_support(codec)) { -+ ati_asp_slot = atihdmi_swap_fc_lfe(asp_slot); -+ if (ati_asp_slot % 2 != 0) { -+ ati_asp_slot -= 1; -+ was_odd = true; -+ } -+ } -+ -+ verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; -+ -+ ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); -+ -+ if (!(ati_channel_setup & ATI_OUT_ENABLE)) -+ return (0xf << 4) | asp_slot; -+ -+ return ((ati_channel_setup & 0xf0) + ((!!was_odd) << 4)) | asp_slot; -+} -+#endif - - static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, - struct hda_codec *codec, -@@ -2565,34 +2828,117 @@ static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, - unsigned int format, - struct snd_pcm_substream *substream) - { -+ hda_nid_t cvt_nid = hinfo->nid; - struct hdmi_spec *spec = codec->spec; -- struct hdmi_spec_per_cvt *per_cvt = get_cvt(spec, 0); -- int chans = substream->runtime->channels; -- int i, err; -+ int pin_idx = hinfo_to_pin_index(spec, hinfo); -+ struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); -+ hda_nid_t pin_nid = per_pin->pin_nid; -+ int hbr_ctl, hbr_ctl_new; - -- err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format, -- substream); -- if (err < 0) -+ hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); -+ if (hbr_ctl & ATI_HBR_CAPABLE) { -+ if (is_hbr_format(format)) -+ hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; -+ else -+ hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; -+ -+ snd_printdd("atihdmi_playback_pcm_prepare: " -+ "NID=0x%x, %shbr-ctl=0x%x\n", -+ pin_nid, -+ hbr_ctl == hbr_ctl_new ? "" : "new-", -+ hbr_ctl_new); -+ -+ if (hbr_ctl != hbr_ctl_new) -+ snd_hda_codec_write(codec, pin_nid, 0, -+ ATI_VERB_SET_HBR_CONTROL, -+ hbr_ctl_new); -+ -+ } else if (is_hbr_format(format)) { -+ snd_printdd("atihdmi_playback_pcm_prepare: HBR is not supported\n"); -+ return -EINVAL; -+ } -+ -+ if (is_amdhdmi_rev3(codec)) { -+ int ramp_rate = 180; /* default as per spec */ -+ /* disable ramp-up/down for non-pcm as per spec */ -+ if (format & AC_FMT_TYPE_NON_PCM) -+ ramp_rate = 0; -+ -+ snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); -+ } -+ -+ return generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, format, substream); -+} -+ -+static int atihdmi_build_pcms(struct hda_codec *codec) -+{ -+ struct hdmi_spec *spec = codec->spec; -+ int err, pin_idx; -+ -+ err = generic_hdmi_build_pcms(codec); -+ -+ if (err) - return err; -- snd_hda_codec_write(codec, per_cvt->cvt_nid, 0, -- AC_VERB_SET_CVT_CHAN_COUNT, chans - 1); -- /* FIXME: XXX */ -- for (i = 0; i < chans; i++) { -- snd_hda_codec_write(codec, per_cvt->cvt_nid, 0, -- AC_VERB_SET_HDMI_CHAN_SLOT, -- (i << 4) | i); -+ -+ for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { -+ struct hda_pcm *info = get_pcm_rec(spec, pin_idx); -+ -+ info->stream[SNDRV_PCM_STREAM_PLAYBACK].ops.prepare = atihdmi_playback_pcm_prepare; - } -+ -+ return 0; -+} -+ -+static int atihdmi_init(struct hda_codec *codec) -+{ -+ struct hdmi_spec *spec = codec->spec; -+ int pin_idx, err; -+ -+ err = generic_hdmi_init(codec); -+ -+ if (err) -+ return err; -+ -+ for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { -+ struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); -+ -+ /* make sure downmix information in infoframe is zero */ -+ snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); -+ -+ /* enable channel-wise remap mode if supported */ -+ if (has_amd_full_remap_support(codec)) -+ snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_MULTICHANNEL_MODE, 1); -+ } -+ - return 0; - } - - static int patch_atihdmi(struct hda_codec *codec) - { - struct hdmi_spec *spec; -- int err = patch_simple_hdmi(codec, ATIHDMI_CVT_NID, ATIHDMI_PIN_NID); -- if (err < 0) -+ struct hdmi_spec_per_cvt *per_cvt; -+ int err, cvt_idx; -+ -+ err = patch_generic_hdmi(codec); -+ -+ if (err) - return err; -+ -+ codec->patch_ops.init = atihdmi_init; -+ codec->patch_ops.build_pcms = atihdmi_build_pcms; -+ -+ /* ATI/AMD converters do not advertise all of their capabilities */ - spec = codec->spec; -- spec->pcm_playback.ops.prepare = atihdmi_playback_pcm_prepare; -+ for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { -+ per_cvt = get_cvt(spec, cvt_idx); -+ per_cvt->channels_max = max(per_cvt->channels_max, 8u); -+ per_cvt->rates |= SUPPORTED_RATES; -+ per_cvt->formats |= SUPPORTED_FORMATS; -+ per_cvt->maxbps = max(per_cvt->maxbps, 24u); -+ } -+ -+ spec->channels_max = max(spec->channels_max, 8u); -+ - return 0; - } - -@@ -2612,7 +2958,7 @@ static const struct hda_codec_preset snd_hda_preset_hdmi[] = { - { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi }, - { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi }, - { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi }, --{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi }, -+{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_atihdmi }, - { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi }, - { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi }, - { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi }, diff --git a/packages/linux/patches/3.11.6/linux-990.12-RADEON-upstream-fix-01.patch b/packages/linux/patches/3.11.6/linux-990.12-RADEON-upstream-fix-01.patch deleted file mode 100644 index 80454716cd..0000000000 --- a/packages/linux/patches/3.11.6/linux-990.12-RADEON-upstream-fix-01.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 6a4a51f43cc6635c7b731d9fb2e1e32333d594fe Mon Sep 17 00:00:00 2001 -From: Alex Deucher -Date: Fri, 27 Sep 2013 18:09:54 -0400 -Subject: [PATCH 1/3] drm/radeon: use 64-bit math to calculate CTS values for - audio (v2) - -Avoid losing precision. See bug: -https://bugs.freedesktop.org/show_bug.cgi?id=69675 - -v2: fix math as per Anssi's comments. - -Signed-off-by: Alex Deucher ---- - drivers/gpu/drm/radeon/r600_hdmi.c | 11 +++++++++-- - 1 file changed, 9 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c -index b0fa600..49043a5 100644 ---- a/drivers/gpu/drm/radeon/r600_hdmi.c -+++ b/drivers/gpu/drm/radeon/r600_hdmi.c -@@ -75,8 +75,15 @@ static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { - */ - static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int N, int freq) - { -- if (*CTS == 0) -- *CTS = clock * N / (128 * freq) * 1000; -+ u64 n; -+ u32 d; -+ -+ if (*CTS == 0) { -+ n = (u64)clock * (u64)N * 1000ULL; -+ d = 128 * freq; -+ do_div(n, d); -+ *CTS = n; -+ } - DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", - N, *CTS, freq); - } --- -1.8.3.1 - diff --git a/packages/linux/patches/3.11.6/linux-990.12-RADEON-upstream-fix-02.patch b/packages/linux/patches/3.11.6/linux-990.12-RADEON-upstream-fix-02.patch deleted file mode 100644 index c8613eba95..0000000000 --- a/packages/linux/patches/3.11.6/linux-990.12-RADEON-upstream-fix-02.patch +++ /dev/null @@ -1,43 +0,0 @@ -From c8908f579ae9aac33122cfdfffaef30bba0a7697 Mon Sep 17 00:00:00 2001 -From: Alex Deucher -Date: Fri, 27 Sep 2013 18:19:42 -0400 -Subject: [PATCH 2/3] drm/radeon: fix N/CTS clock matching for audio - -The drm code that calculates the 1001 clocks rounds up -rather than truncating. This allows the table to match -properly on those modes. - -See bug: -https://bugs.freedesktop.org/show_bug.cgi?id=69675 - -Signed-off-by: Alex Deucher ---- - drivers/gpu/drm/radeon/r600_hdmi.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c -index 2ce2793..a378081 100644 ---- a/drivers/gpu/drm/radeon/r600_hdmi.c -+++ b/drivers/gpu/drm/radeon/r600_hdmi.c -@@ -58,15 +58,15 @@ enum r600_hdmi_iec_status_bits { - static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = { - /* 32kHz 44.1kHz 48kHz */ - /* Clock N CTS N CTS N CTS */ -- { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ -+ { 25175, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ - { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ - { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ - { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ - { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ - { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ -- { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ -+ { 74176, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ - { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ -- { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ -+ { 148352, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ - { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ - { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ - }; --- -1.8.3.1 - diff --git a/packages/linux/patches/3.11.6/linux-990.12-RADEON-upstream-fix-03.patch b/packages/linux/patches/3.11.6/linux-990.12-RADEON-upstream-fix-03.patch deleted file mode 100644 index bd5e75d61f..0000000000 --- a/packages/linux/patches/3.11.6/linux-990.12-RADEON-upstream-fix-03.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 37396f32fc8c8a4f68e0fd069e4e63ce19786ef4 Mon Sep 17 00:00:00 2001 -From: Alex Deucher -Date: Fri, 27 Sep 2013 18:22:15 -0400 -Subject: [PATCH 3/3] drm/radeon: use hw generated CTS/N values for audio - -Use the hw generated values rather than calculating -them in the driver. There may be some older r6xx -asics where this doesn't work correctly. This remains -to be seen. - -See bug: -https://bugs.freedesktop.org/show_bug.cgi?id=69675 - -Signed-off-by: Alex Deucher ---- - drivers/gpu/drm/radeon/evergreen_hdmi.c | 3 +-- - drivers/gpu/drm/radeon/r600_hdmi.c | 3 +-- - 2 files changed, 2 insertions(+), 4 deletions(-) - -diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c -index f71ce39..f815c20 100644 ---- a/drivers/gpu/drm/radeon/evergreen_hdmi.c -+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c -@@ -288,8 +288,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode - /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ - - WREG32(HDMI_ACR_PACKET_CONTROL + offset, -- HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ -- HDMI_ACR_SOURCE); /* select SW CTS value */ -+ HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ - - evergreen_hdmi_update_ACR(encoder, mode->clock); - -diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c -index a378081..2b5f9a7 100644 ---- a/drivers/gpu/drm/radeon/r600_hdmi.c -+++ b/drivers/gpu/drm/radeon/r600_hdmi.c -@@ -451,8 +451,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod - } - - WREG32(HDMI0_ACR_PACKET_CONTROL + offset, -- HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ -- HDMI0_ACR_SOURCE); /* select SW CTS value */ -+ HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */ - - WREG32(HDMI0_VBI_PACKET_CONTROL + offset, - HDMI0_NULL_SEND | /* send null packets when required */ --- -1.8.3.1 - diff --git a/packages/linux/patches/3.11.6/linux-991.01-ptrace_fix.patch b/packages/linux/patches/3.11.6/linux-991.01-ptrace_fix.patch deleted file mode 100644 index 656284df17..0000000000 --- a/packages/linux/patches/3.11.6/linux-991.01-ptrace_fix.patch +++ /dev/null @@ -1,17 +0,0 @@ -diff -Naur linux-3.10.10/include/uapi/linux/ptrace.h linux-3.10.10.patch/include/uapi/linux/ptrace.h ---- linux-3.10.10/include/uapi/linux/ptrace.h 2013-08-29 18:47:51.000000000 +0200 -+++ linux-3.10.10.patch/include/uapi/linux/ptrace.h 2013-09-04 16:38:10.182685149 +0200 -@@ -55,11 +55,13 @@ - - #define PTRACE_PEEKSIGINFO 0x4209 - -+#ifdef __KERNEL__ - struct ptrace_peeksiginfo_args { - __u64 off; /* from which siginfo to start */ - __u32 flags; - __s32 nr; /* how may siginfos to take */ - }; -+#endif /* __KERNEL__ */ - - /* Read signals from a shared (process wide) queue */ - #define PTRACE_PEEKSIGINFO_SHARED (1 << 0) diff --git a/packages/linux/patches/3.11.6/linux-992.01.i915_pass_mode_to_write_eld.patch b/packages/linux/patches/3.11.6/linux-992.01.i915_pass_mode_to_write_eld.patch deleted file mode 100644 index 841e84b079..0000000000 --- a/packages/linux/patches/3.11.6/linux-992.01.i915_pass_mode_to_write_eld.patch +++ /dev/null @@ -1,66 +0,0 @@ -Signed-off-by: Jani Nikula ---- - drivers/gpu/drm/i915/i915_drv.h | 3 ++- - drivers/gpu/drm/i915/intel_display.c | 11 +++++++---- - 2 files changed, 9 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h -index 6106d3d..caee590 100644 ---- a/drivers/gpu/drm/i915/i915_drv.h -+++ b/drivers/gpu/drm/i915/i915_drv.h -@@ -379,7 +379,8 @@ struct drm_i915_display_funcs { - void (*crtc_disable)(struct drm_crtc *crtc); - void (*off)(struct drm_crtc *crtc); - void (*write_eld)(struct drm_connector *connector, -- struct drm_crtc *crtc); -+ struct drm_crtc *crtc, -+ struct drm_display_mode *mode); - void (*fdi_link_train)(struct drm_crtc *crtc); - void (*init_clock_gating)(struct drm_device *dev); - int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, -diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c -index 4f1b636..55740f2 100644 ---- a/drivers/gpu/drm/i915/intel_display.c -+++ b/drivers/gpu/drm/i915/intel_display.c -@@ -6752,7 +6752,8 @@ static bool intel_eld_uptodate(struct drm_connector *connector, - } - - static void g4x_write_eld(struct drm_connector *connector, -- struct drm_crtc *crtc) -+ struct drm_crtc *crtc, -+ struct drm_display_mode *mode) - { - struct drm_i915_private *dev_priv = connector->dev->dev_private; - uint8_t *eld = connector->eld; -@@ -6792,7 +6793,8 @@ static void g4x_write_eld(struct drm_connector *connector, - } - - static void haswell_write_eld(struct drm_connector *connector, -- struct drm_crtc *crtc) -+ struct drm_crtc *crtc, -+ struct drm_display_mode *mode) - { - struct drm_i915_private *dev_priv = connector->dev->dev_private; - uint8_t *eld = connector->eld; -@@ -6879,7 +6881,8 @@ static void haswell_write_eld(struct drm_connector *connector, - } - - static void ironlake_write_eld(struct drm_connector *connector, -- struct drm_crtc *crtc) -+ struct drm_crtc *crtc, -+ struct drm_display_mode *mode) - { - struct drm_i915_private *dev_priv = connector->dev->dev_private; - uint8_t *eld = connector->eld; -@@ -6974,7 +6977,7 @@ void intel_write_eld(struct drm_encoder *encoder, - connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; - - if (dev_priv->display.write_eld) -- dev_priv->display.write_eld(connector, crtc); -+ dev_priv->display.write_eld(connector, crtc, mode); - } - - static void i845_update_cursor(struct drm_crtc *crtc, u32 base) --- -1.7.9.5 - diff --git a/packages/linux/patches/3.11.6/linux-992.02-i915_set_hdmi_audio_clock.patch b/packages/linux/patches/3.11.6/linux-992.02-i915_set_hdmi_audio_clock.patch deleted file mode 100644 index ec33a09002..0000000000 --- a/packages/linux/patches/3.11.6/linux-992.02-i915_set_hdmi_audio_clock.patch +++ /dev/null @@ -1,110 +0,0 @@ -Reference: http://mid.gmane.org/CAGpEb3Ep1LRZETPxHGRfBDqr5Ts2tAc8gCukWwugUf1U5NYv1g@mail.gmail.com -Reference: http://mid.gmane.org/20130206213533.GA16367@hardeman.nu -Reported-by: David Härdeman -Reported-by: Jasper Smet -Tested-by: Jasper Smet -Signed-off-by: Jani Nikula ---- - drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++- - drivers/gpu/drm/i915/intel_display.c | 48 +++++++++++++++++++++++++++++++--- - 2 files changed, 55 insertions(+), 5 deletions(-) - -diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h -index 13153c3..3266819 100644 ---- a/drivers/gpu/drm/i915/i915_reg.h -+++ b/drivers/gpu/drm/i915/i915_reg.h -@@ -4875,7 +4875,17 @@ - #define AUD_CONFIG_LOWER_N_SHIFT 4 - #define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4) - #define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16 --#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16) -+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16) -+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16) -+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16) -+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16) -+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16) -+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16) -+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16) -+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16) -+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16) -+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16) -+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16) - #define AUD_CONFIG_DISABLE_NCTS (1 << 3) - - /* HSW Audio */ -diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c -index 55740f2..a097f84 100644 ---- a/drivers/gpu/drm/i915/intel_display.c -+++ b/drivers/gpu/drm/i915/intel_display.c -@@ -6722,6 +6722,44 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, - return 0; - } - -+static struct { -+ int clock; -+ u32 config; -+} hdmi_audio_clock[] = { -+ { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, -+ { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ -+ { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, -+ { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, -+ { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, -+ { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, -+ { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, -+ { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, -+ { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, -+ { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, -+}; -+ -+/* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ -+static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { -+ if (mode->clock == hdmi_audio_clock[i].clock) -+ break; -+ } -+ -+ if (i == ARRAY_SIZE(hdmi_audio_clock)) { -+ DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); -+ i = 1; -+ } -+ -+ DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", -+ hdmi_audio_clock[i].clock, -+ hdmi_audio_clock[i].config); -+ -+ return hdmi_audio_clock[i].config; -+} -+ - static bool intel_eld_uptodate(struct drm_connector *connector, - int reg_eldv, uint32_t bits_eldv, - int reg_elda, uint32_t bits_elda, -@@ -6847,8 +6885,9 @@ static void haswell_write_eld(struct drm_connector *connector, - DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); - eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ - I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ -- } else -- I915_WRITE(aud_config, 0); -+ } else { -+ I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); -+ } - - if (intel_eld_uptodate(connector, - aud_cntrl_st2, eldv, -@@ -6926,8 +6965,9 @@ static void ironlake_write_eld(struct drm_connector *connector, - DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); - eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ - I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ -- } else -- I915_WRITE(aud_config, 0); -+ } else { -+ I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); -+ } - - if (intel_eld_uptodate(connector, - aud_cntrl_st2, eldv, --- -1.7.9.5 - diff --git a/packages/linux/patches/3.11.6/linux-995-CX24120-13Z_frontend.patch b/packages/linux/patches/3.11.6/linux-995-CX24120-13Z_frontend.patch deleted file mode 100755 index 41d0f1d9d2..0000000000 --- a/packages/linux/patches/3.11.6/linux-995-CX24120-13Z_frontend.patch +++ /dev/null @@ -1,1577 +0,0 @@ -http://patchwork.linuxtv.org/patch/10575/ -modified for 3.7.10 - -diff -NurEbBw --strip-trailing-cr linux-3.4-r1/drivers/media/common/b2c2/flexcop-common.h linux-3.4-r1-S2/drivers/media/common/b2c2/flexcop-common.h ---- linux-3.4-r1/drivers/media/common/b2c2/flexcop-common.h 2012-04-03 15:23:44.824143495 +0400 -+++ linux-3.4-r1-S2/drivers/media/common/b2c2/flexcop-common.h 2012-04-03 15:26:40.756140116 +0400 -@@ -91,6 +91,8 @@ - int feedcount; - int pid_filtering; - int fullts_streaming_state; -+ /* the stream will be activated by an externally (by the fe for example) */ -+ int need_external_stream_control; - - /* bus specific callbacks */ - flexcop_ibi_value(*read_ibi_reg) (struct flexcop_device *, -@@ -177,6 +179,8 @@ - struct dvb_demux_feed *dvbdmxfeed, int onoff); - void flexcop_hw_filter_init(struct flexcop_device *fc); - -+extern void flexcop_external_stream_control(struct dvb_frontend *fe, u8 onoff); -+ - void flexcop_smc_ctrl(struct flexcop_device *fc, int onoff); - - void flexcop_set_mac_filter(struct flexcop_device *fc, u8 mac[6]); -diff -NurEbBw --strip-trailing-cr linux-3.4-r1/drivers/media/common/b2c2/flexcop-fe-tuner.c linux-3.4-r1-S2/drivers/media/common/b2c2/flexcop-fe-tuner.c ---- linux-3.4-r1/drivers/media/common/b2c2/flexcop-fe-tuner.c 2012-04-03 15:23:44.828143388 +0400 -+++ linux-3.4-r1-S2/drivers/media/common/b2c2/flexcop-fe-tuner.c 2012-04-03 15:26:40.760141513 +0400 -@@ -12,6 +12,7 @@ - #include "cx24113.h" - #include "cx24123.h" - #include "isl6421.h" -+#include "cx24120.h" - #include "mt352.h" - #include "bcm3510.h" - #include "nxt200x.h" -@@ -26,6 +27,15 @@ - #define FE_SUPPORTED(fe) (defined(CONFIG_DVB_##fe) || \ - (defined(CONFIG_DVB_##fe##_MODULE) && defined(MODULE))) - -+#if FE_SUPPORTED(BCM3510) || FE_SUPPORTED(CX24120) -+static int flexcop_fe_request_firmware(struct dvb_frontend *fe, -+ const struct firmware **fw, char* name) -+{ -+ struct flexcop_device *fc = fe->dvb->priv; -+ return request_firmware(fw, name, fc->dev); -+} -+#endif -+ - /* lnb control */ - #if FE_SUPPORTED(MT312) || FE_SUPPORTED(STV0299) - static int flexcop_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) -@@ -445,13 +455,6 @@ - - /* AirStar ATSC 1st generation */ - #if FE_SUPPORTED(BCM3510) --static int flexcop_fe_request_firmware(struct dvb_frontend *fe, -- const struct firmware **fw, char* name) --{ -- struct flexcop_device *fc = fe->dvb->priv; -- return request_firmware(fw, name, fc->dev); --} -- - static struct bcm3510_config air2pc_atsc_first_gen_config = { - .demod_address = 0x0f, - .request_firmware = flexcop_fe_request_firmware, -@@ -619,10 +622,40 @@ - #define cablestar2_attach NULL - #endif - -+/* SkyStar S2 PCI DVB-S/S2 card based on Conexant cx24120/cx24118 */ -+#if FE_SUPPORTED(CX24120) && FE_SUPPORTED(ISL6421) -+static const struct cx24120_config skystar2_rev3_3_cx24120_config = { -+ .i2c_addr = 0x55, -+ .request_firmware = flexcop_fe_request_firmware, -+}; -+ -+static int skystarS2_rev33_attach(struct flexcop_device *fc, struct i2c_adapter *i2c) -+{ -+// struct dvb_frontend_ops *ops; -+ -+ fc->fe = dvb_attach(cx24120_attach, -+ &skystar2_rev3_3_cx24120_config, i2c); -+ if (fc->fe == NULL) return 0; -+ fc->dev_type = FC_SKYS2_REV33; -+ fc->fc_i2c_adap[2].no_base_addr = 1; -+ if ( (dvb_attach(isl6421_attach, fc->fe, -+ &fc->fc_i2c_adap[2].i2c_adap, 0x08, 0, 0, false) == NULL) ) { -+ err("ISL6421 could NOT be attached!"); -+ return 0; -+ } -+ info("ISL6421 successfully attached."); -+// ops = &fc->fe->ops; -+ return 1; -+} -+#else -+#define skystarS2_rev33_attach NULL -+#endif -+ - static struct { - flexcop_device_type_t type; - int (*attach)(struct flexcop_device *, struct i2c_adapter *); - } flexcop_frontends[] = { -+ { FC_SKYS2_REV33, skystarS2_rev33_attach }, - { FC_SKY_REV27, skystar2_rev27_attach }, - { FC_SKY_REV28, skystar2_rev28_attach }, - { FC_SKY_REV26, skystar2_rev26_attach }, -diff -NurEbBw --strip-trailing-cr linux-3.4-r1/drivers/media/common/b2c2/flexcop-hw-filter.c linux-3.4-r1-S2/drivers/media/common/b2c2/flexcop-hw-filter.c ---- linux-3.4-r1/drivers/media/common/b2c2/flexcop-hw-filter.c 2012-04-03 15:23:44.828143388 +0400 -+++ linux-3.4-r1-S2/drivers/media/common/b2c2/flexcop-hw-filter.c 2012-04-03 15:26:40.760141513 +0400 -@@ -11,6 +11,12 @@ - deb_ts("rcv_data is now: '%s'\n", onoff ? "on" : "off"); - } - -+void flexcop_external_stream_control(struct dvb_frontend *fe, u8 onoff) -+{ -+ struct flexcop_device *fc = fe->dvb->priv; -+ flexcop_rcv_data_ctrl(fc, onoff); -+} -+ - void flexcop_smc_ctrl(struct flexcop_device *fc, int onoff) - { - flexcop_set_ibi_value(ctrl_208, SMC_Enable_sig, onoff); -@@ -199,6 +205,7 @@ - - /* if it was the first or last feed request change the stream-status */ - if (fc->feedcount == onoff) { -+ if (!fc->need_external_stream_control) - flexcop_rcv_data_ctrl(fc, onoff); - if (fc->stream_control) /* device specific stream control */ - fc->stream_control(fc, onoff); -diff -NurEbBw --strip-trailing-cr linux-3.4-r1/drivers/media/common/b2c2/flexcop-misc.c linux-3.4-r1-S2/drivers/media/common/b2c2/flexcop-misc.c ---- linux-3.4-r1/drivers/media/common/b2c2/flexcop-misc.c 2012-04-03 15:23:44.832143280 +0400 -+++ linux-3.4-r1-S2/drivers/media/common/b2c2/flexcop-misc.c 2012-04-03 15:26:40.760141513 +0400 -@@ -56,6 +56,7 @@ - [FC_SKY_REV26] = "Sky2PC/SkyStar 2 DVB-S rev 2.6", - [FC_SKY_REV27] = "Sky2PC/SkyStar 2 DVB-S rev 2.7a/u", - [FC_SKY_REV28] = "Sky2PC/SkyStar 2 DVB-S rev 2.8", -+ [FC_SKYS2_REV33]= "Sky2PC/SkyStar S2 DVB-S/S2 rev 3.3", - }; - - static const char *flexcop_bus_names[] = { -diff -NurEbBw --strip-trailing-cr linux-3.4-r1/drivers/media/common/b2c2/flexcop-reg.h linux-3.4-r1-S2/drivers/media/common/b2c2/flexcop-reg.h ---- linux-3.4-r1/drivers/media/common/b2c2/flexcop-reg.h 2012-04-03 15:23:44.832143280 +0400 -+++ linux-3.4-r1-S2/drivers/media/common/b2c2/flexcop-reg.h 2012-04-03 15:26:40.760141513 +0400 -@@ -24,6 +24,7 @@ - FC_SKY_REV26, - FC_SKY_REV27, - FC_SKY_REV28, -+ FC_SKYS2_REV33, - } flexcop_device_type_t; - - typedef enum { -diff -NurEbBw --strip-trailing-cr linux-3.4-r1/drivers/media/common/b2c2/Kconfig linux-3.4-r1-S2/drivers/media/common/b2c2/Kconfig ---- linux-3.4-r1/drivers/media/common/b2c2/Kconfig 2012-04-03 15:23:44.824143495 +0400 -+++ linux-3.4-r1-S2/drivers/media/common/b2c2/Kconfig 2012-04-03 15:26:40.760141513 +0400 -@@ -3,6 +3,7 @@ - depends on DVB_CORE && I2C - depends on DVB_B2C2_FLEXCOP_PCI || DVB_B2C2_FLEXCOP_USB - default y -+ select DVB_CX24120 if !DVB_FE_CUSTOMISE - select DVB_PLL if MEDIA_SUBDRV_AUTOSELECT - select DVB_STV0299 if MEDIA_SUBDRV_AUTOSELECT - select DVB_MT352 if MEDIA_SUBDRV_AUTOSELECT -diff -NurEbBw --strip-trailing-cr linux-3.4-r1/drivers/media/dvb-frontends/cx24120.c linux-3.4-r1-S2/drivers/media/dvb-frontends/cx24120.c ---- linux-3.4-r1/drivers/media/dvb-frontends/cx24120.c 1970-01-01 03:00:00.000000000 +0300 -+++ linux-3.4-r1-S2/drivers/media/dvb-frontends/cx24120.c 2012-04-03 16:10:59.000000000 +0400 -@@ -0,0 +1,1053 @@ -+/* -+ Conexant cx24120/cx24118 - DVBS/S2 Satellite demod/tuner driver -+ Version 0.0.4a 03.04.2012 -+ -+ Copyright (C) 2009 Sergey Tyurin -+ Updated 2012 by Jannis Achstetter -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 2 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+*/ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "dvb_frontend.h" -+#include "cx24120.h" -+#include "cx24120_const.h" -+ -+//========================== -+#define dbginfo(args...) do { if(cx24120_debug) { printk(KERN_DEBUG "CX24120: %s: >>> ", __func__); \ -+ printk(args); } } while (0) -+#define info(args...) do { printk(KERN_INFO "CX24120: %s: -> ", __func__); \ -+ printk(args); } while (0) -+#define err(args...) do { printk(KERN_ERR "CX24120: %s: ### ERROR: ", __func__); \ -+ printk(args); } while (0) -+//========================== -+ -+static int cx24120_debug=0; -+static int reg_debug=0; -+MODULE_DESCRIPTION("DVB Frontend module for Conexant CX24120/CX24118 hardware"); -+module_param(cx24120_debug, int, 0644); -+MODULE_PARM_DESC(cx24120_debug, "Activates frontend debugging (default:0)"); -+ -+// ############################## -+struct cx24120_state { -+ struct i2c_adapter *i2c; -+ const struct cx24120_config *config; -+ struct dvb_frontend frontend; -+ u8 need_set_mpeg_out; -+ u8 attached; -+ u8 dvb_s2_mode; -+ u8 cold_init; -+}; -+// ##################################### -+// #### Command message to firmware #### -+struct cx24120_cmd { // total size = 36 -+ u8 id; // [00] - message id -+ u8 arg[30]; // [04] - message first byte -+ u8 len; // [34] - message lengh or first registers to read -+ u8 reg; // [35] - number of registers to read -+}; -+ -+//=================================================================== -+static int cx24120_readreg(struct cx24120_state *state, u8 reg) -+{ -+ int ret; -+ u8 buf = 0; -+ struct i2c_msg msg[] = { -+ { .addr = state->config->i2c_addr, -+ .flags = 0, -+ .len = 1, -+ .buf = ® }, -+ -+ { .addr = state->config->i2c_addr, -+ .flags = I2C_M_RD, -+ .len = 1, -+ .buf = &buf } -+ }; -+ ret = i2c_transfer(state->i2c, msg, 2); -+ if (ret != 2) { -+ err("Read error: reg=0x%02x, ret=0x%02x)\n", reg, ret); -+ return ret; -+ } -+ if (reg_debug) dbginfo("reg=0x%02x; data=0x%02x\n", reg, buf); -+ return buf; -+} // end cx24120_readreg -+//=================================================================== -+static int cx24120_writereg(struct cx24120_state *state, u8 reg, u8 data) -+{ -+ u8 buf[] = { reg, data }; -+ struct i2c_msg msg = { -+ .addr = state->config->i2c_addr, -+ .flags = 0, -+ .buf = buf, -+ .len = 2 }; -+ int ret; -+ ret = i2c_transfer(state->i2c, &msg, 1); -+ if (ret != 1) { -+ err("Write error: i2c_write error(err == %i, 0x%02x: 0x%02x)\n", ret, reg, data); -+ return ret; -+ } -+ if (reg_debug) dbginfo("reg=0x%02x; data=0x%02x\n", reg, data); -+ return 0; -+} // end cx24120_writereg -+//=================================================================== -+static int cx24120_writeregN(struct cx24120_state *state, u8 reg, const u8 *values, u16 len, u8 incr) -+{ -+ u8 buf[5]; /* maximum 4 data bytes at once - flexcop limitation (very limited i2c-interface this one) */ -+ struct i2c_msg msg = { -+ .addr = state->config->i2c_addr, -+ .flags = 0, -+ .buf = buf, -+ .len = len }; -+ int ret; -+ -+ do { -+ buf[0] = reg; -+ msg.len = len > 4 ? 4 : len; -+ memcpy(&buf[1], values, msg.len); -+ len -= msg.len; // data length revers counter -+ values += msg.len; // incr data pointer -+ if (incr) reg += msg.len; -+ msg.len++; /* don't forget the addr byte */ -+ ret = i2c_transfer(state->i2c, &msg, 1); -+ if (ret != 1) { -+ err("i2c_write error(err == %i, 0x%02x)\n", ret, reg); -+ return ret; -+ } -+ if (reg_debug) { -+ if( !(reg == 0xFA) && !(reg == 0x20) && !(reg == 0x21)) { // Exclude firmware upload & diseqc messages -+ dbginfo("reg=0x%02x; data=0x%02x,0x%02x,0x%02x,0x%02x\n", // from debug -+ reg, buf[1], buf[2], buf[3], buf[4]); -+ } -+ } -+ } while (len); -+ return 0; -+} // end cx24120_writeregN -+//=================================================================== -+static struct dvb_frontend_ops cx24120_ops; -+//=================================================================== -+struct dvb_frontend *cx24120_attach(const struct cx24120_config *config, struct i2c_adapter *i2c) -+{ -+ struct cx24120_state *state = NULL; -+ int demod_rev; -+ -+ info("Conexant cx24120/cx24118 - DVBS/S2 Satellite demod/tuner\n"); -+ info("Driver version: 'SVT - 0.0.4a 03.04.2012'\n"); -+ state = kzalloc(sizeof(struct cx24120_state), -+ GFP_KERNEL); -+ if (state == NULL) { -+ err("### Unable to allocate memory for cx24120_state structure. :(\n"); -+ goto error; -+ } -+ /* setup the state */ -+ state->config = config; -+ state->i2c = i2c; -+ /* check if the demod is present and has proper type */ -+ demod_rev = cx24120_readreg(state, CX24120_REG_REVISION); -+ switch (demod_rev) { -+ case 0x07: -+ info("Demod CX24120 rev. 0x07 detected.\n"); -+ break; -+ case 0x05: -+ info("Demod CX24120 rev. 0x05 detected.\n"); -+ break; -+ default: -+ err("### Unsupported demod revision: 0x%x detected. Exit.\n", demod_rev); -+ goto error; -+ } -+ /* create dvb_frontend */ -+ state->attached = 0x10; // set attached flag -+ state->cold_init=0; -+ memcpy(&state->frontend.ops, &cx24120_ops, sizeof(struct dvb_frontend_ops)); -+ state->frontend.demodulator_priv = state; -+ info("Conexant cx24120/cx24118 - DVBS/S2 Satellite demod/tuner ATTACHED.\n"); -+ return &state->frontend; -+ -+error: -+ kfree(state); -+ return NULL; -+} -+EXPORT_SYMBOL(cx24120_attach); // end cx24120_attach -+//=================================================================== -+static int cx24120_test_rom(struct cx24120_state *state) -+{ -+ int err, ret; -+ err = cx24120_readreg(state, 0xFD); -+ if (err & 4 ) -+ { -+ ret = cx24120_readreg(state, 0xDF) & 0xFE; -+ err = cx24120_writereg(state, 0xDF, ret); -+ } -+ return err; -+} // end cx24120_test_rom -+//=================================================================== -+static int cx24120_read_snr(struct dvb_frontend *fe, u16 *snr) -+{ -+ struct cx24120_state *state = fe->demodulator_priv; -+ -+ *snr = (cx24120_readreg(state, CX24120_REG_QUALITY_H)<<8) | -+ (cx24120_readreg(state, CX24120_REG_QUALITY_L)); -+ dbginfo("read SNR index = %d\n", *snr); -+ -+ return 0; -+} -+EXPORT_SYMBOL(cx24120_read_snr); // end cx24120_read_snr -+//=================================================================== -+static int cx24120_read_ber(struct dvb_frontend *fe, u32 *ber) -+{ -+ struct cx24120_state *state = fe->demodulator_priv; -+ -+ *ber = (cx24120_readreg(state, CX24120_REG_BER_HH) << 24) | // BER high byte of high word -+ (cx24120_readreg(state, CX24120_REG_BER_HL) << 16) | // BER low byte of high word -+ (cx24120_readreg(state, CX24120_REG_BER_LH) << 8) | // BER high byte of low word -+ cx24120_readreg(state, CX24120_REG_BER_LL); // BER low byte of low word -+ dbginfo("read BER index = %d\n", *ber); -+ -+ return 0; -+} -+EXPORT_SYMBOL(cx24120_read_ber); // end cx24120_read_ber -+//=================================================================== -+static int cx24120_message_send(struct cx24120_state *state, struct cx24120_cmd *cmd); -+//=================================================================== -+static int cx24120_msg_mpeg_output_global_config(struct cx24120_state *state, u8 flag) -+{ -+ u8 tristate; -+ struct cx24120_cmd cmd; -+ -+ memset(&cmd, 0, sizeof(struct cx24120_cmd)); -+ -+ cmd.id = 0x13; // (19) message Enable/Disable mpeg output ??? -+ cmd.arg[0] = 1; -+ cmd.arg[1] = 0; -+ tristate = flag ? 0 : (u8)(-1); -+ cmd.arg[2] = tristate; -+ cmd.arg[3] = 1; -+ cmd.len = 4; -+ -+ if(flag) dbginfo("MPEG output DISABLED\n"); -+ else dbginfo("MPEG output ENABLED\n"); -+ -+ return cx24120_message_send(state, &cmd); -+} // end cx24120_msg_mpeg_output_global_config -+//=================================================================== -+static int cx24120_message_send(struct cx24120_state *state, struct cx24120_cmd *cmd) -+{ -+ u8 xxzz; -+ u32 msg_cmd_mask; -+ int ret, ficus; -+ -+ if(state->dvb_s2_mode & 0x02) { // is MPEG enabled? -+ // if yes: -+ xxzz = cmd->id - 0x11; // look for specific message id -+ if ( xxzz <= 0x13 ) { -+ msg_cmd_mask = 1 << xxzz; -+ //0x0F8021 // if cmd_id 17 or 22 or 33-36, 42, 47, 57-61 etc. disable mpeg output -+ if ( msg_cmd_mask & 0x0F8021 ) { // 000011111000000000100001b -+ cx24120_msg_mpeg_output_global_config(state, 0); -+ msleep(100); -+ state->dvb_s2_mode &= 0xFD; // reset mpeg out enable flag -+ } -+ } -+ } -+ ret = cx24120_writereg(state, 0x00 /* reg id*/, cmd->id /* value */); // message start & target -+ ret = cx24120_writeregN(state, 0x01 /* reg msg*/, &cmd->arg[0], cmd->len /* len*/, 1 /* incr */); // message data -+ ret = cx24120_writereg(state, 0x1F /* reg msg_end */, 0x01 /* value */); // message end -+ -+ ficus = 1000; -+ while ( cx24120_readreg(state, 0x1F)) { // is command done??? -+ msleep(1); -+ if( !(--ficus)) { -+ err("Too long waiting 'done' state from reg(0x1F). :(\n"); -+ return -EREMOTEIO; -+ } -+ } -+ dbginfo("Successfully send message 0x%02x\n", cmd->id); -+ -+ if ( cmd->reg > 30 ) { -+ err("Too much registers to read. cmd->reg = %d", cmd->reg); -+ return -EREMOTEIO; -+ } -+ ficus = 0; -+ if ( cmd->reg ) { // cmd->reg - qty consecutive regs to read -+ while ( ficus < cmd->reg ){ // starts from reg No cmd->len -+ // number of registers to read is cmd->reg -+ // and write results starts from cmd->arg[0]. -+ cmd->arg[ficus] = cx24120_readreg(state, (cmd->len+ficus+1)); -+ ++ficus; -+ } -+ } -+ return 0; -+} // end cx24120_message_send -+//=================================================================== -+static int cx24120_set_frontend(struct dvb_frontend *fe) -+{ -+ struct dtv_frontend_properties *p = &fe->dtv_property_cache; -+ struct cx24120_state *state = fe->demodulator_priv; -+ struct cx24120_cmd cmd; -+ u32 srate, freq; -+ fe_code_rate_t fec; -+ fe_spectral_inversion_t inversion; -+ u8 smbr1, smbr2; -+ int ret; -+ -+ memset(&cmd, 0, sizeof(struct cx24120_cmd)); -+ -+ cmd.id = CMD_TUNEREQUEST; // 0x11 set tuner parametrs -+ cmd.len = 15; -+ -+ freq = p->frequency; -+ srate = p->symbol_rate; -+ fec = p->fec_inner; -+ inversion = p->inversion; -+ -+ // check symbol rate -+ if ( srate > 31000000 ) { // if symbol rate > 31 000 -+ smbr1 = (-(srate < 31000001) & 3) + 2; // ebp -+ smbr2 = (-(srate < 31000001) & 6) + 4; // edi -+ } else { -+ smbr1 = 3; -+ smbr2 = 6; -+ } -+ -+ ret = cx24120_writereg(state, 0xE6, smbr1); -+ ret = cx24120_readreg(state, 0xF0); -+ ret &= 0xFFFFFFF0; -+ ret |= smbr2; -+ ret = cx24120_writereg(state, 0xF0, ret); -+ -+ cmd.arg[0] = 0; // CMD_TUNER_REQUEST -+ -+ // Frequency -+ cmd.arg[1] = (freq & 0xFF0000) >> 16; /* intermediate frequency in kHz */ -+ cmd.arg[2] = (freq & 0x00FF00) >> 8; -+ cmd.arg[3] = (freq & 0x0000FF); -+ -+ // Symbol Rate -+ cmd.arg[4] = ((srate/1000) & 0xFF00) >> 8; -+ cmd.arg[5] = ((srate/1000) & 0x00FF); -+ -+ // Inversion -+ if ( inversion ) { -+ if ( inversion == 1 ) cmd.arg[6] = 4; -+ else cmd.arg[6] = 0x0C; -+ } else { -+ cmd.arg[6] = 0; -+ } -+ -+ // FEC -+ switch ( fec ) // fec = p->u.qpsk.fec_inner -+ { -+ case 1: // FEC_1_2 -+ cmd.arg[7] = 0x2E; break; // [11] = 0 by memset -+ case 2: // FEC_2_3 -+ cmd.arg[7] = 0x2F; break; -+ case 3: // FEC_3_4 -+ cmd.arg[7] = 0x30; break; -+ case 5: // FEC_5_6 -+ cmd.arg[7] = 0x31; break; -+ case 7: // FEC_7_8 -+ cmd.arg[7] = 0x32; break; -+ default: // FEC_NONE, FEC_4_5, FEC_6_7, FEC_8_9, -+ // FEC_AUTO, FEC_3_5, FEC_9_10 -+ if ( state->dvb_s2_mode & 1 ) { // if DVB-S2 mode -+ cmd.arg[7] = 0; -+ cmd.arg[11] = 0; -+ } else { -+ cmd.arg[7] = 0x2E; -+ cmd.arg[11] = 0xAC; -+ } -+ break; -+ } -+ cmd.arg[8] = 0x13; -+ cmd.arg[9] = 0x88; -+ cmd.arg[10] = 0; -+ cmd.arg[12] = smbr2; -+ cmd.arg[13] = smbr1; -+ cmd.arg[14] = 0; -+ -+ state->need_set_mpeg_out |= 0x01; // after tune we need restart mpeg out ????? -+ -+ return cx24120_message_send(state, &cmd); -+ -+} -+EXPORT_SYMBOL(cx24120_set_frontend); // end cx24120_set_frontend -+//=================================================================== -+void cx24120_message_fill(struct cx24120_cmd *cmd, -+ u8 msg_id, -+ u8 *msg_addr, -+ u8 msg_len, -+ u8 num_regs) -+{ -+ cmd->id = msg_id; -+ memcpy(&cmd->arg[0], msg_addr, msg_len); -+ cmd->len = msg_len; -+ cmd->reg = num_regs; -+} // end cx24120_message_fill -+//=================================================================== -+static int cx24120_read_signal_strength(struct dvb_frontend *fe, u16 *signal_strength) -+{ -+ struct cx24120_state *state = fe->demodulator_priv; -+ struct cx24120_cmd cmd; -+ int result, sigstr_h, sigstr_l; -+ -+ cx24120_message_fill(&cmd, 0x1A/*msg_id*/, &cx24120_msg_read_sigstr[0], 1/*msg_len*/, 0/*num_regs*/); -+ -+ if( !(cx24120_message_send(state, &cmd)) ) { -+ sigstr_h = (cx24120_readreg(state, CX24120_REG_SIGSTR_H) >> 6) << 8; -+ sigstr_l = cx24120_readreg(state, CX24120_REG_SIGSTR_L ); -+ dbginfo("Signal strength from firmware= 0x%x\n", (sigstr_h | sigstr_l)); -+ *signal_strength = ((sigstr_h | sigstr_l) << 5) & 0x0000FFFF; -+ dbginfo("Signal strength= 0x%x\n", *signal_strength); -+ result = 0; -+ } else { -+ err("error reading signal strength\n"); -+ result = -EREMOTEIO; -+ } -+ return result; -+} -+EXPORT_SYMBOL(cx24120_read_signal_strength); // end cx24120_read_signal_strength -+//=================================================================== -+static int cx24120_msg_mpeg_output_config(struct cx24120_state *state, u8 num, -+ struct cx24120_skystar2_mpeg_config *config_msg) -+{ -+ struct cx24120_cmd cmd; -+ -+ memset(&cmd, 0, sizeof(struct cx24120_cmd)); -+ -+ cmd.id = CMD_MPEG_INIT; // cmd->id=20 - message id -+ cmd.len = 7; -+ cmd.arg[0] = num; // sequental number - can be 0,1,2 -+ cmd.arg[1] = ((config_msg->x1 & 0x01) << 1) | -+ ((config_msg->x1 >> 1) & 0x01); -+ cmd.arg[2] = 0x05; -+ cmd.arg[3] = 0x02; -+ cmd.arg[4] = ((config_msg->x2 >> 1) & 0x01); -+ cmd.arg[5] = (config_msg->x2 & 0xF0) | (config_msg->x3 & 0x0F); -+ cmd.arg[6] = state->attached; /* 0x10 if succesfully attached */ -+ -+ return cx24120_message_send(state, &cmd); -+} // end cx24120_msg_mpeg_output_config -+//=================================================================== -+static int cx24120_diseqc_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst) -+{ -+ struct cx24120_state *state = fe->demodulator_priv; -+ struct cx24120_cmd cmd; -+ -+ memset(&cmd, 0, sizeof(struct cx24120_cmd)); -+ -+ cmd.id = CMD_DISEQC_BURST; -+ cmd.arg[0] = 0x00; -+ if (burst) -+ cmd.arg[1] = 0x01; -+ dbginfo("burst sent.\n"); -+ -+ return cx24120_message_send(state, &cmd); -+} -+EXPORT_SYMBOL(cx24120_diseqc_send_burst); // end cx24120_diseqc_send_burst -+//=================================================================== -+static int cx24120_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) -+{ -+ struct cx24120_state *state = fe->demodulator_priv; -+ struct cx24120_cmd cmd; -+ -+ dbginfo("cmd(0x23,4) - tone = %d\n", tone); -+ if ((tone != SEC_TONE_ON) && (tone != SEC_TONE_OFF)) { -+ err("Invalid tone=%d\n", tone); -+ return -EINVAL; -+ } -+ memset(&cmd, 0, sizeof(struct cx24120_cmd)); -+ cmd.id = CMD_SETTONE; // 0x23 -+ cmd.len = 4; -+ if (!tone) -+ cmd.arg[3] = 0x01; -+ return cx24120_message_send(state, &cmd); -+} -+EXPORT_SYMBOL(cx24120_set_tone); // end cx24120_set_tone -+//=================================================================== -+static int cx24120_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) -+{ -+ struct cx24120_state *state = fe->demodulator_priv; -+ struct cx24120_cmd cmd; -+ -+ memset(&cmd, 0, sizeof(struct cx24120_cmd)); -+ cmd.id = CMD_SETVOLTAGE; // -+ cmd.len = 2; -+ if (!(voltage - 1)) -+ cmd.arg[1] = 0x01; -+ return cx24120_message_send(state, &cmd); -+} -+EXPORT_SYMBOL(cx24120_set_voltage); // end cx24120_set_voltage -+//=================================================================== -+static int cx24120_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *d) -+{ -+ struct cx24120_state *state = fe->demodulator_priv; -+ struct cx24120_cmd cmd; -+ int back_count; -+ -+ dbginfo("Start sending diseqc sequence===============\n"); -+ -+ memset(&cmd, 0, sizeof(struct cx24120_cmd)); -+ -+ cmd.id = CMD_DISEQC_MSG1; // 0x20 -+ cmd.len = 11; -+ cmd.arg[0] = 0x00; -+ cmd.arg[1] = 0x00; -+ cmd.arg[2] = 0x03; -+ cmd.arg[3] = 0x16; -+ cmd.arg[4] = 0x28; -+ cmd.arg[5] = 0x01; -+ cmd.arg[6] = 0x01; -+ cmd.arg[7] = 0x14; -+ cmd.arg[8] = 0x19; -+ cmd.arg[9] = 0x14; -+ cmd.arg[10] = 0x1E; -+ if ( cx24120_message_send(state, &cmd) ) { -+ err("send 1st message(0x%x) filed==========\n", cmd.id); -+ return -EREMOTEIO; -+ } -+ cmd.id = CMD_DISEQC_MSG2; // 0x21 -+ cmd.len = d->msg_len + 6; -+ cmd.arg[0] = 0x00; -+ cmd.arg[1] = 0x01; -+ cmd.arg[2] = 0x02; -+ cmd.arg[3] = 0x00; -+ cmd.arg[4] = 0x00; -+ cmd.arg[5] = d->msg_len; -+ -+ memcpy(&cmd.arg[6], &d->msg, d->msg_len); -+ -+ if ( cx24120_message_send(state, &cmd) ) { -+ err("send 2d message(0x%x) filed========\n", cmd.id); -+ return -EREMOTEIO; -+ } -+ back_count = 100; -+ do { -+ if ( !(cx24120_readreg(state, 0x93) & 0x01) ) { -+ dbginfo("diseqc sequence sent success==========.\n"); -+ return 0; -+ } -+ msleep(5); -+ --back_count; -+ } while ( back_count ); -+ err("Too long waiting for diseqc.=============\n"); -+ return -ETIMEDOUT; -+} -+EXPORT_SYMBOL(cx24120_send_diseqc_msg); // end cx24120_send_diseqc_msg -+//=================================================================== -+static int cx24120_read_status(struct dvb_frontend *fe, fe_status_t *status) -+{ -+ struct cx24120_state *state = fe->demodulator_priv; -+ struct cx24120_cmd cmd; -+ int ret, clock_seq_num, GettedFEC; -+ u8 mode_code, mode_8PSK_flag, attached_flag, clock_id; -+ -+ ret = cx24120_readreg(state, CX24120_REG_STATUS); //0x3A -+ dbginfo("status = 0x%x\n", ret); -+ *status = 0; -+ if ( ret & CX24120_HAS_SIGNAL ) *status = FE_HAS_SIGNAL; -+ if ( ret & CX24120_HAS_CARRIER) *status |= FE_HAS_CARRIER; -+ if ( ret & CX24120_HAS_VITERBI) *status |= (FE_HAS_VITERBI + FE_HAS_SYNC); -+ -+ if ( ret & CX24120_HAS_LOCK ) { // 0x08 -+ *status |= FE_HAS_LOCK; -+ if ( state->need_set_mpeg_out & 1 ) { // just tuned??? -+ memset(&cmd, 0, sizeof(struct cx24120_cmd)); -+ cmd.id = CMD_CLOCK_READ; -+ cmd.arg[0] = 0x00; -+ cmd.len = 1; // cmd.reg != 0, so it is first register to read -+ cmd.reg = 6; // number of registers to read (0x01-0x06) -+ if ( !cx24120_message_send(state, &cmd) ) { // in cmd[0]-[5] - result -+ // 0x02-0x07 -+ ret = cx24120_readreg(state, CX24120_REG_FECMODE) & 0x3F; // ntv - 0x8E(142) & 3F = 14 -+ GettedFEC = ret; // 0x0d= 13 -+ dbginfo("Get FEC: %d\n", ret); -+ if ( state->dvb_s2_mode & 0x01 ) { // is DVB-S2? -+ switch (ret-4) { -+ case 0: -+ mode_code = 0x01; goto mode_QPSK; // FEC_1_2 - qpsk only -+ case 1: -+ case 8: -+ mode_code = 0x64; goto mode_8PSK; // FEC_3_5 (10)- 8PSK only -+ case 2: -+ case 9: -+ mode_code = 0x02; goto mode_8PSK; // FEC_2_3 -+ case 3: -+ case 10: -+ mode_code = 0x03; goto mode_8PSK; // FEC_3_4 // 14-4=10 - ntv+ -+ case 4: -+ mode_code = 0x04; goto mode_QPSK; // FEC_4_5 - qpsk only -+ case 5: -+ case 11: -+ mode_code = 0x05; goto mode_8PSK; // FEC_5_6 -+ case 6: -+ case 12: -+ mode_code = 0x08; goto mode_8PSK; // FEC_8_9 -+ case 7: -+ case 13: -+ mode_code = 0x65; goto mode_8PSK; // FEC_9_10 (11)- 8PSK only -+ default: -+ info("Unknown DVB-S2 modefec (not QPSK or 8PSK): %d\n", ret-4); -+ mode_code = 0x01; // set like for mode 0 -+ mode_8PSK: -+ if ( ret > 11 ) { // 14 -+ mode_8PSK_flag = 0x63; // DVB-S2-8PSK flag -+ dbginfo("DVB-S2: 8PSK mode: %d, mode_code= 0x%x\n", ret-4, mode_code); -+ } else { -+ mode_QPSK: -+ mode_8PSK_flag = 0x00; -+ dbginfo("DVB-S2: QPSK mode: %d\n", ret-4); -+ } -+ break; -+ } // end switch -+ } // end if dvb_s2_mode // dvb-s2 -+ else { // state->dvb_s2_mode & 1 = 0 -> #### DVB-S -+ switch ( ret - 2 ) { -+ case 0: -+ mode_code = 2; break; // FEC_2_3 -+ case 1: -+ mode_code = 3; break; // FEC_3_4 -+ case 2: -+ mode_code = 4; break; // FEC_4_5 -+ case 3: -+ mode_code = 5; break; // FEC_5_6 -+ case 4: -+ mode_code = 6; break; // FEC_6_7 -+ case 5: -+ mode_code = 7; break; // FEC_7_8 -+ default: -+ mode_code = 1;break; // FEC_1_2 -+ } -+ mode_8PSK_flag = 0; -+ } // end of switch for dvb-s -+ -+ attached_flag = 0x10; -+ if (state->attached == 0x10) // must be 0x10 if successfully attached in flexcop_fe_tuner -+ attached_flag = 0; -+ ret = 0; -+ if ( state->dvb_s2_mode & 0x01 ) // if dvb-s2 -+ ret = (cx24120_readreg(state, CX24120_REG_FECMODE) >> 7) & 0x01; // QPSK or 8PSK ??? -+ // bit 4 bit 5 bit 0 bit 3 -+ clock_id = (ret << 3) | attached_flag | (state->dvb_s2_mode & 1) | 4; // possible id: 4, 5, 13. 12-impossible, -+ // ntv S2 = 0x8E -> 8 | 1 | 4 = 13 // because 7th bit of ret - is S2 flag -+ // 1/2 S2 = 0x0d -> 0 | 1 | 4 = 5 -+ dbginfo("Check clock table for: clock_id=0x%x, 8PSK_mask=0x%x, mode_code=0x%x\n", -+ clock_id, mode_8PSK_flag, mode_code); -+ -+ clock_seq_num = 0; -+ while ( (clock_ratios_table[clock_seq_num].ratio_id != clock_id) || -+ (clock_ratios_table[clock_seq_num].mode_xPSK != mode_8PSK_flag) || -+ (clock_ratios_table[clock_seq_num].fec_mode != mode_code) ) -+ { -+ /* dbginfo("Check table string(%d): clock_id=%d, 8PSK_flag=%d, mode_code=%d\n", clock_seq_num, -+ * clock_ratios_table[clock_seq_num].ratio_id, -+ * clock_ratios_table[clock_seq_num].mode_xPSK, -+ * clock_ratios_table[clock_seq_num].fec_mode); -+ */ -+ ++clock_seq_num; -+ if ( clock_seq_num == ARRAY_SIZE(clock_ratios_table) ) { -+ info("Check in clock table filed: unsupported modulation tuned - data reception in danger. :(\n"); -+ goto settings_end; -+ } -+ } -+ //############################### -+ dbginfo("Check succesful: GetFEC: %d; post lock: m=%d, n=%d; clock_seq_idx: %d m=%d, n=%d, rate=%d\n", -+ GettedFEC, -+ cmd.arg[2] | (cmd.arg[1] << 8) | (cmd.arg[0] << 16), // registers was readed early -+ cmd.arg[5] | (cmd.arg[4] << 8) | (cmd.arg[3] << 16), // in message with id = 0x16 -+ clock_seq_num, -+ clock_ratios_table[clock_seq_num].m_rat, -+ clock_ratios_table[clock_seq_num].n_rat, -+ clock_ratios_table[clock_seq_num].rate); -+ //############################### -+ cmd.id = CMD_CLOCK_SET; -+ cmd.len = 10; -+ cmd.reg = 0; -+ cmd.arg[0] = 0; -+ cmd.arg[1] = state->attached; // must be 0x10 if successfully attached in flexcop_fe_tuner -+ -+ cmd.arg[2] = (clock_ratios_table[clock_seq_num].m_rat >> 16) & 0xFF; -+ cmd.arg[3] = (clock_ratios_table[clock_seq_num].m_rat >> 8) & 0xFF; -+ cmd.arg[4] = (clock_ratios_table[clock_seq_num].m_rat >> 0) & 0xFF; -+ -+ cmd.arg[5] = (clock_ratios_table[clock_seq_num].n_rat >> 16) & 0xFF; -+ cmd.arg[6] = (clock_ratios_table[clock_seq_num].n_rat >> 8) & 0xFF; -+ cmd.arg[7] = (clock_ratios_table[clock_seq_num].n_rat >> 0) & 0xFF; -+ -+ cmd.arg[8] = (clock_ratios_table[clock_seq_num].rate >> 8) & 0xFF; -+ cmd.arg[9] = (clock_ratios_table[clock_seq_num].rate >> 0) & 0xFF; -+ -+ cx24120_message_send(state, &cmd); -+ -+ settings_end: -+ msleep(200); -+ cx24120_msg_mpeg_output_global_config(state, 1); -+ state->dvb_s2_mode |= 0x02; // set mpeg flag -+ state->need_set_mpeg_out &= 0xFE; // clocks set done -> clear flag -+ } -+ } -+ } -+ return 0; -+} -+EXPORT_SYMBOL(cx24120_read_status); // end cx24120_read_status -+//=================================================================== -+int cx24120_init(struct dvb_frontend *fe) -+{ -+ const struct firmware *fw; -+ struct cx24120_state *state = fe->demodulator_priv; -+ struct cx24120_cmd cmd; -+ u8 ret, ret_EA, reg1, fL, fH; -+ u32 vco, xtal_khz; -+ u64 inv_vco, res, xxyyzz; -+ int reset_result; -+ -+ if( state->cold_init ) return 0; -+ -+ ret = cx24120_writereg(state, 0xEA, 0x00); -+ ret = cx24120_test_rom(state); -+ ret = cx24120_readreg(state, 0xFB) & 0xFE; -+ ret = cx24120_writereg(state, 0xFB, ret); -+ ret = cx24120_readreg(state, 0xFC) & 0xFE; -+ ret = cx24120_writereg(state, 0xFC, ret); -+ ret = cx24120_writereg(state, 0xC3, 0x04); -+ ret = cx24120_writereg(state, 0xC4, 0x04); -+ ret = cx24120_writereg(state, 0xCE, 0x00); -+ ret = cx24120_writereg(state, 0xCF, 0x00); -+ ret_EA = cx24120_readreg(state, 0xEA) & 0xFE; -+ ret = cx24120_writereg(state, 0xEA, ret_EA); -+ ret = cx24120_writereg(state, 0xEB, 0x0C); -+ ret = cx24120_writereg(state, 0xEC, 0x06); -+ ret = cx24120_writereg(state, 0xED, 0x05); -+ ret = cx24120_writereg(state, 0xEE, 0x03); -+ ret = cx24120_writereg(state, 0xEF, 0x05); -+ ret = cx24120_writereg(state, 0xF3, 0x03); -+ ret = cx24120_writereg(state, 0xF4, 0x44); -+ -+ reg1 = 0xF0; -+ do { -+ cx24120_writereg(state, reg1, 0x04); -+ cx24120_writereg(state, reg1 - 10, 0x02); -+ ++reg1; -+ } while ( reg1 != 0xF3 ); -+ -+ ret = cx24120_writereg(state, 0xEA, (ret_EA | 0x01)); -+ reg1 = 0xC5; -+ do { -+ ret = cx24120_writereg(state, reg1, 0x00); -+ ret = cx24120_writereg(state, reg1 + 1, 0x00); -+ reg1 += 2; -+ } while ( reg1 != 0xCB ); -+ -+ ret = cx24120_writereg(state, 0xE4, 0x03); -+ ret = cx24120_writereg(state, 0xEB, 0x0A); -+ -+ dbginfo("Requesting firmware (%s) to download...\n", CX24120_FIRMWARE); -+ ret = state->config->request_firmware(fe, &fw, CX24120_FIRMWARE); -+ if (ret) { -+ err("Could not load firmware (%s): %d\n", CX24120_FIRMWARE, ret); -+ return ret; -+ } -+ dbginfo("Firmware found and it size is %d bytes (%02x %02x .. %02x %02x)\n", -+ (int)fw->size, // firmware_size in bytes u32* -+ fw->data[0], // fw 1st byte -+ fw->data[1], // fw 2d byte -+ fw->data[fw->size - 2], // fw before last byte -+ fw->data[fw->size - 1]); // fw last byte -+ -+ ret = cx24120_test_rom(state); -+ ret = cx24120_readreg(state, 0xFB) & 0xFE; -+ ret = cx24120_writereg(state, 0xFB, ret); -+ ret = cx24120_writereg(state, 0xE0, 0x76); -+ ret = cx24120_writereg(state, 0xF7, 0x81); -+ ret = cx24120_writereg(state, 0xF8, 0x00); -+ ret = cx24120_writereg(state, 0xF9, 0x00); -+ ret = cx24120_writeregN(state, 0xFA, fw->data, (fw->size - 1), 0x00); -+ ret = cx24120_writereg(state, 0xF7, 0xC0); -+ ret = cx24120_writereg(state, 0xE0, 0x00); -+ ret = (fw->size - 2) & 0x00FF; -+ ret = cx24120_writereg(state, 0xF8, ret); // ret now is 0x7a -+ ret = ((fw->size - 2) >> 8) & 0x00FF; -+ ret = cx24120_writereg(state, 0xF9, ret); // ret now is 0xaf -+ ret = cx24120_writereg(state, 0xF7, 0x00); -+ ret = cx24120_writereg(state, 0xDC, 0x00); -+ ret = cx24120_writereg(state, 0xDC, 0x07); -+ msleep(500); -+ -+ ret = cx24120_readreg(state, 0xE1); // now is 0xd5 - last byte of the firmware -+ if ( ret == fw->data[fw->size - 1] ) { -+ dbginfo("Firmware uploaded successfully\n"); -+ reset_result = 0; -+ } else { -+ err("Firmware upload failed. Last byte returned=0x%x\n", ret ); -+ reset_result = -EREMOTEIO; -+ } -+ ret = cx24120_writereg(state, 0xDC, 0x00); -+ release_firmware(fw); -+ if (reset_result) -+ return reset_result; -+ -+ //================== Start tuner -+ cx24120_message_fill(&cmd, CMD_START_TUNER, &cx24120_msg_tuner_init[0], 3, 0); // 0x1B -+ if(cx24120_message_send(state, &cmd)) { -+ err("Error tuner start! :(\n"); -+ return -EREMOTEIO; -+ } -+ memset(&cmd, 0, sizeof(struct cx24120_cmd)); -+ -+ cmd.id = CMD_VCO_SET; // 0x10 -+ cmd.len = 12; -+ -+ // ###################### -+ // Calc VCO -+ xtal_khz = 10111; -+ xxyyzz = 0x400000000ULL; // 17179869184 -+ vco = xtal_khz * 10 * 4; // 404440 -+ inv_vco = xxyyzz / vco; // 42478 = 0x00A5EE -+ res = xxyyzz % vco; // 66864 = 0x010530 -+ -+ if( inv_vco > xtal_khz * 10 * 2) ++inv_vco; -+ -+ fH = (inv_vco >> 8) & 0xFF; -+ fL = (inv_vco) & 0xFF; -+ dbginfo("vco= %d, inv_vco= %lld, res= %lld, fL= 0x%x, fH= 0x%x\n", vco, inv_vco, res, fL, fH); -+ // ###################### -+ -+ cmd.arg[0] = 0x06; -+ cmd.arg[1] = 0x2B; -+ cmd.arg[2] = 0xD8; -+ cmd.arg[3] = fH; // 0xA5 -+ cmd.arg[4] = fL; // 0xEE -+ cmd.arg[5] = 0x03; -+ cmd.arg[6] = 0x9D; -+ cmd.arg[7] = 0xFC; -+ cmd.arg[8] = 0x06; -+ cmd.arg[9] = 0x03; -+ cmd.arg[10] = 0x27; -+ cmd.arg[11] = 0x7F; -+ -+ if(cx24120_message_send(state, &cmd)) { -+ err("Error set VCO! :(\n"); -+ return -EREMOTEIO; -+ } -+ memset(&cmd, 0, sizeof(struct cx24120_cmd)); -+ // set bandwidth -+ cmd.id = CMD_BANDWIDTH; // 0x15 -+ cmd.len = 12; -+ cmd.arg[0] = 0x00; -+ cmd.arg[1] = 0x00; -+ cmd.arg[2] = 0x00; -+ cmd.arg[3] = 0x00; -+ cmd.arg[4] = 0x05; -+ cmd.arg[5] = 0x02; -+ cmd.arg[6] = 0x02; -+ cmd.arg[7] = 0x00; -+ cmd.arg[8] = 0x05; -+ cmd.arg[9] = 0x02; -+ cmd.arg[10] = 0x02; -+ cmd.arg[11] = 0x00; -+ -+ if ( cx24120_message_send(state, &cmd) ) { -+ err("Error set bandwidth! :(\n"); -+ return -EREMOTEIO; -+ } -+ ret = cx24120_readreg(state, 0xBA); -+ if ( ret > 3) { -+ dbginfo("Reset-readreg 0xBA: %x\n", ret); -+ err("Error intitilizing tuner! :(\n"); -+ return -EREMOTEIO; -+ } -+ dbginfo("Tuner initialized correctly.\n"); -+ -+ ret = cx24120_writereg(state, 0xEB, 0x0A); -+ if (cx24120_msg_mpeg_output_global_config(state, 0) || -+ cx24120_msg_mpeg_output_config(state, 0, &initial_mpeg_config) || -+ cx24120_msg_mpeg_output_config(state, 1, &initial_mpeg_config) || -+ cx24120_msg_mpeg_output_config(state, 2, &initial_mpeg_config) ) -+ { -+ err("Error initilizing mpeg output. :(\n"); -+ return -EREMOTEIO; -+ } else { -+ cmd.id = 0x3C; // 60 -+ cmd.len = 0x03; -+ cmd.arg[0] = 0x00; -+ cmd.arg[1] = 0x10; -+ cmd.arg[2] = 0x10; -+ if(cx24120_message_send(state, &cmd)) { -+ err("Error sending final init message. :(\n"); -+ return -EREMOTEIO; -+ } -+ } -+ state->cold_init=1; -+ return 0; -+} -+EXPORT_SYMBOL(cx24120_init); // end cx24120_reset -+//=================================================================== -+static int cx24120_tune(struct dvb_frontend *fe, bool re_tune, -+ unsigned int mode_flags, unsigned int *delay, fe_status_t *p_status) -+{ -+ struct dtv_frontend_properties *p = &fe->dtv_property_cache; -+ struct cx24120_state *state = fe->demodulator_priv; -+ int delay_cnt, sd_idx = 0; -+ fe_status_t status; -+ -+ if (re_tune) { -+ -+// dbginfo("Compare symrate with table: symrate= %d, in table= %d\n", -+// p->u.qpsk.symbol_rate, symrates_pairs[sd_idx].symrate); -+ -+ while ( p->symbol_rate > symrates_pairs[sd_idx].symrate ) { -+ ++sd_idx; -+ } -+ dbginfo("Found symrate delay = %d\n", symrates_pairs[sd_idx].delay); -+ state->dvb_s2_mode &= 0xFE; // clear bit -> try not DVB-S2 -+ dbginfo("trying DVB-S =================\n"); -+ cx24120_set_frontend(fe); -+ -+ delay_cnt = symrates_pairs[sd_idx].delay; -+ dbginfo("Wait for LOCK for DVB-S =================\n"); -+ while (delay_cnt >= 0) { -+ cx24120_read_status(fe, &status); -+ if (status & FE_HAS_LOCK) { -+ dbginfo("DVB-S LOCKED================\n"); -+ break; -+ } -+ msleep(100); -+ delay_cnt -=100; -+ } -+ dbginfo("Waiting finished - NO lock for DVB-S =================\n"); -+ -+ cx24120_read_status(fe, &status); -+ if ( !(status & FE_HAS_LOCK) ) { // if no lock on S -+ dbginfo("trying DVB-S2 ++++++++++++++++++++++++++\n"); -+ state->dvb_s2_mode |= 0x01; // may be it locked on S2 ? -+ p->fec_inner = FEC_AUTO; -+ cx24120_set_frontend(fe); -+ delay_cnt = symrates_pairs[sd_idx].delay; -+ dbginfo("Wait for LOCK for DVB-S2 ++++++++++++++++\n"); -+ while (delay_cnt >= 0) { -+ cx24120_read_status(fe, &status); -+ if (status & FE_HAS_LOCK) { -+ dbginfo("DVB-S2 LOCKED++++++++++++++++\n"); -+ break; -+ } -+ msleep(100); -+ delay_cnt -=100; -+ } -+ dbginfo("Waiting finished - NO lock for DVB-S2 ++++++++++++++++\n"); -+ } -+ } -+ return 0; -+} -+EXPORT_SYMBOL(cx24120_tune); // end of cx24120_tune -+//=================================================================== -+static int cx24120_get_algo(struct dvb_frontend *fe) -+{ -+ return DVBFE_ALGO_HW; -+} -+EXPORT_SYMBOL(cx24120_get_algo); -+//=================================================================== -+static int cx24120_sleep(struct dvb_frontend *fe) -+{ -+ return 0; -+} -+EXPORT_SYMBOL(cx24120_sleep); -+//=================================================================== -+/*static int cx24120_wakeup(struct dvb_frontend *fe) -+ * { -+ * return 0; -+ * } -+ * EXPORT_SYMBOL(cx24120_wakeup); -+ */ -+//=================================================================== -+static int cx24120_get_frontend(struct dvb_frontend *fe) -+{ -+ return 0; -+} -+EXPORT_SYMBOL(cx24120_get_frontend); -+//=================================================================== -+static void cx24120_release(struct dvb_frontend *fe) -+{ -+ struct cx24120_state *state = fe->demodulator_priv; -+ dbginfo("Clear state structure\n"); -+ kfree(state); -+} -+EXPORT_SYMBOL(cx24120_release); -+//=================================================================== -+static int cx24120_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) // UNCORRECTED_BLOCKS -+{ -+ struct cx24120_state *state = fe->demodulator_priv; -+ -+ *ucblocks = (cx24120_readreg(state, CX24120_REG_UCB_H) << 8) | -+ cx24120_readreg(state, CX24120_REG_UCB_L); -+ dbginfo("Blocks = %d\n", *ucblocks); -+ return 0; -+} -+EXPORT_SYMBOL(cx24120_read_ucblocks); -+// ######################################################################################## -+static struct dvb_frontend_ops cx24120_ops = { -+ -+ .delsys = { SYS_DVBS2 }, -+ .info = { -+ .name = "Conexant CX24120/CX24118", -+ .frequency_min = 950000, -+ .frequency_max = 2150000, -+ .frequency_stepsize = 1011, /* kHz for QPSK frontends */ -+ .frequency_tolerance = 5000, -+ .symbol_rate_min = 1000000, -+ .symbol_rate_max = 45000000, -+ .caps = // 0x500006ff -+ FE_CAN_INVERSION_AUTO | //0x00 000 001 -+ FE_CAN_FEC_1_2 | //0x00 000 002 -+ FE_CAN_FEC_2_3 | //0x00 000 004 -+ FE_CAN_FEC_3_4 | //0x00 000 008 -+ FE_CAN_FEC_4_5 | //0x00 000 010 -+ FE_CAN_FEC_5_6 | //0x00 000 020 -+ FE_CAN_FEC_6_7 | //0x00 000 040 -+ FE_CAN_FEC_7_8 | //0x00 000 080 -+ FE_CAN_FEC_AUTO | //0x00 000 200 -+ FE_CAN_QPSK | //0x00 000 400 -+//??? FE_HAS_EXTENDED_CAPS | //0x00 800 000 /* We need more bitspace for newer APIs, indicate this. */ -+ FE_CAN_2G_MODULATION | //0x10 000 000 /* frontend supports "2nd generation modulation" (DVB-S2) */ -+ FE_CAN_RECOVER //0x40 000 000 /* frontend can recover from a cable unplug automatically */ -+ }, //sum=50 000 6FF -+ .release = cx24120_release, -+ -+ .init = cx24120_init, -+ .sleep = cx24120_sleep, -+ -+ .tune = cx24120_tune, -+ .get_frontend_algo = cx24120_get_algo, -+ .set_frontend = cx24120_set_frontend, -+ -+ .get_frontend = cx24120_get_frontend, -+ .read_status = cx24120_read_status, -+ .read_ber = cx24120_read_ber, -+ .read_signal_strength = cx24120_read_signal_strength, -+ .read_snr = cx24120_read_snr, -+ .read_ucblocks = cx24120_read_ucblocks, -+ -+ .diseqc_send_master_cmd = cx24120_send_diseqc_msg, -+ -+ .diseqc_send_burst = cx24120_diseqc_send_burst, -+ .set_tone = cx24120_set_tone, -+ .set_voltage = cx24120_set_voltage, -+}; -+//=================================================================== -+MODULE_PARM_DESC(cx24120_debug, "prints some verbose debugging information (default:0)"); -+MODULE_AUTHOR("Sergey Tyurin"); -+MODULE_LICENSE("GPL"); -diff -NurEbBw --strip-trailing-cr linux-3.4-r1/drivers/media/dvb-frontends/cx24120_const.h linux-3.4-r1-S2/drivers/media/dvb-frontends/cx24120_const.h ---- linux-3.4-r1/drivers/media/dvb-frontends/cx24120_const.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-3.4-r1-S2/drivers/media/dvb-frontends/cx24120_const.h 2012-04-03 16:37:20.684139905 +0400 -@@ -0,0 +1,259 @@ -+/* -+ * Conexant CX24120/CX24118 - DVB-S/S2 demod/tuner driver -+ * DVBS/S2 Satellite demod/tuner driver static definitins -+ * -+ * Copyright (C) 2009 Sergey Tyurin -+ * Updated 2012 by Jannis Achstetter -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#define CX24120_FIRMWARE "dvb-fe-cx24120-1.20.58.2.fw" -+ -+// ############################## -+// ### cx24120 i2c registers ### -+#define CX24120_REG_CMD_START (0x00) // write cmd_id, and then start write args to next register: -+#define CX24120_REG_CMD_ARGS (0x01) // write command arguments, max 4 at once, then next 4, etc. -+#define CX24120_REG_CMD_END (0x1F) // write 0x01 for end, and read it for command result -+ -+#define CX24120_REG_FECMODE (0x39) // FEC status -+#define CX24120_REG_STATUS (0x3A) // Tuner status - signal, carrier, sync, lock ... -+#define CX24120_REG_QUALITY_H (0x40) // SNR high byte -+#define CX24120_REG_QUALITY_L (0x41) // SNR low byte -+ -+#define CX24120_REG_BER_HH (0x47) // BER high byte of high word -+#define CX24120_REG_BER_HL (0x48) // BER low byte of high word -+#define CX24120_REG_BER_LH (0x49) // BER high byte of low word -+#define CX24120_REG_BER_LL (0x4A) // BER low byte of low word -+ -+#define CX24120_REG_SIGSTR_H (0x3A) // Signal strength high byte & ??? status register ??? -+#define CX24120_REG_SIGSTR_L (0x3B) // Signal strength low byte -+ -+#define CX24120_REG_UCB_H (0x50) // UCB high byte -+#define CX24120_REG_UCB_L (0x51) // UCB low byte -+ -+#define CX24120_REG_REVISION (0xFF) // Chip revision (ro). Must be 0x7 or 0x5 -+ -+// ############################## -+/* Command messages */ -+enum command_message_id { -+ CMD_VCO_SET = 0x10, // cmdlen = 12; -+ CMD_TUNEREQUEST = 0x11, // cmd.len = 15; -+ -+ CMD_MPEG_ONOFF = 0x13, // cmd.len = 4; -+ CMD_MPEG_INIT = 0x14, // cmd.len = 7; -+ CMD_BANDWIDTH = 0x15, // cmd.len = 12; -+ CMD_CLOCK_READ = 0x16, // read clock from registers 0x01-0x06 -+ CMD_CLOCK_SET = 0x17, // cmd.len = 10; -+ -+ CMD_DISEQC_MSG1 = 0x20, // cmd.len = 11; -+ CMD_DISEQC_MSG2 = 0x21, // cmd.len = d->msg_len + 6; -+ CMD_SETVOLTAGE = 0x22, // cmd.len = 2; -+ CMD_SETTONE = 0x23, // cmd.len = 4; -+ CMD_DISEQC_BURST = 0x24, // cmd.len not used !!! -+ -+ CMD_READ_SNR = 0x1A, // Read signal strength -+ CMD_START_TUNER = 0x1B, // ??? -+ -+ CMD_TUNER_INIT = 0x3C, // cmd.len = 0x03; -+}; -+// ############################## -+/* signal status */ -+#define CX24120_HAS_SIGNAL (0x01) -+#define CX24120_HAS_CARRIER (0x02) -+#define CX24120_HAS_VITERBI (0x04) -+#define CX24120_HAS_LOCK (0x08) -+#define CX24120_HAS_UNK1 (0x10) -+#define CX24120_HAS_UNK2 (0x20) -+#define CX24120_STATUS_MASK (0x0f) -+#define CX24120_SIGNAL_MASK (0xc0) -+ -+static u8 cx24120_msg_tuner_init[] = { 0,0,0,0,0,0 }; -+static u8 cx24120_msg_read_sigstr[] = {0,0}; -+ -+static struct cx24120_skystar2_mpeg_config { -+ u8 x1; -+ u8 x2; -+ u8 x3; -+} initial_mpeg_config = { -+ 0xA1, // 10100001 -+ 0x76, // 01110110 -+ 0x07, // 00000111 -+}; -+ -+static struct cx24120_symrate_delay { -+ u32 symrate; -+ u32 delay; -+} symrates_pairs[] = { -+ { 3000000, 15000 }, -+ { 6000000, 10000 }, -+ { 8000000, 5000 }, -+ { 10000000, 2000 }, -+ {0x0FFFFFFFF, 400 }, -+}; -+ -+static struct cx24120_clock_ratios_table { -+ u32 ratio_id; -+ u32 mode_xPSK; -+ u32 fec_mode; -+ u32 m_rat; -+ u32 n_rat; -+ u32 rate; -+} clock_ratios_table[] = { -+{ 21 , 0 , 1 , 770068 , 763515 , 258 }, -+{ 21 , 0 , 100 , 97409 , 80370 , 310 }, -+{ 21 , 0 , 2 , 137293 , 101802 , 345 }, -+{ 21 , 0 , 3 , 4633447 , 3054060 , 388 }, -+{ 21 , 0 , 4 , 2472041 , 1527030 , 414 }, -+{ 21 , 0 , 5 , 85904 , 50901 , 432 }, -+{ 21 , 0 , 8 , 2751229 , 1527030 , 461 }, -+{ 21 , 0 , 101 , 1392872 , 763515 , 467 }, -+{ 21 , 99 , 100 , 1850771 , 1019430 , 464 }, -+{ 21 , 99 , 2 , 137293 , 67962 , 517 }, -+{ 21 , 99 , 3 , 4633447 , 2038860 , 581 }, // was 4 - ERRORR! FEC_4_5 not in DVB-S2 -+{ 21 , 99 , 5 , 85904 , 33981 , 647 }, -+{ 21 , 99 , 8 , 2751229 , 1019430 , 690 }, -+{ 21 , 99 , 101 , 1392872 , 509715 , 699 }, -+{ 29 , 0 , 1 , 770068 , 782127 , 252 }, -+{ 29 , 0 , 100 , 1850771 , 1564254 , 302 }, -+{ 29 , 0 , 2 , 686465 , 521418 , 337 }, -+{ 29 , 0 , 3 , 4633447 , 3128508 , 379 }, -+{ 29 , 0 , 4 , 2472041 , 1564254 , 404 }, -+{ 29 , 0 , 5 , 429520 , 260709 , 421 }, -+{ 29 , 0 , 8 , 2751229 , 1564254 , 450 }, -+{ 29 , 0 , 101 , 1392872 , 782127 , 455 }, -+{ 29 , 99 , 100 , 1850771 , 1043118 , 454 }, -+{ 29 , 99 , 2 , 686465 , 347706 , 505 }, -+{ 29 , 99 , 3 , 4633447 , 2086236 , 568 }, // was 4 - ERRORR! FEC_4_5 not in DVB-S2 -+{ 29 , 99 , 5 , 429520 , 173853 , 632 }, -+{ 29 , 99 , 8 , 2751229 , 1043118 , 675 }, -+{ 29 , 99 , 101 , 1392872 , 521559 , 683 }, -+{ 17 , 0 , 1 , 766052 , 763515 , 256 }, -+{ 17 , 0 , 100 , 96901 , 80370 , 308 }, -+{ 17 , 0 , 2 , 136577 , 101802 , 343 }, -+{ 17 , 0 , 3 , 4609283 , 3054060 , 386 }, -+{ 17 , 0 , 4 , 2459149 , 1527030 , 412 }, -+{ 17 , 0 , 5 , 85456 , 50901 , 429 }, -+{ 17 , 0 , 8 , 2736881 , 1527030 , 458 }, -+{ 17 , 0 , 101 , 1385608 , 763515 , 464 }, -+{ 17 , 99 , 100 , 1841119 , 1019430 , 462 }, -+{ 17 , 99 , 2 , 136577 , 67962 , 514 }, -+{ 17 , 99 , 3 , 4609283 , 2038860 , 578 }, // was 4 - ERRORR! FEC_4_5 not in DVB-S2 -+{ 17 , 99 , 5 , 85456 , 33981 , 643 }, -+{ 17 , 99 , 8 , 2736881 , 1019430 , 687 }, -+{ 17 , 99 , 101 , 1385608 , 509715 , 695 }, -+{ 25 , 0 , 1 , 766052 , 782127 , 250 }, -+{ 25 , 0 , 100 , 1841119 , 1564254 , 301 }, -+{ 25 , 0 , 2 , 682885 , 521418 , 335 }, -+{ 25 , 0 , 3 , 4609283 , 3128508 , 377 }, -+{ 25 , 0 , 4 , 2459149 , 1564254 , 402 }, -+{ 25 , 0 , 5 , 427280 , 260709 , 419 }, -+{ 25 , 0 , 8 , 2736881 , 1564254 , 447 }, -+{ 25 , 0 , 101 , 1385608 , 782127 , 453 }, -+{ 25 , 99 , 100 , 1841119 , 1043118 , 451 }, -+{ 25 , 99 , 2 , 682885 , 347706 , 502 }, -+{ 25 , 99 , 3 , 4609283 , 2086236 , 565 }, // was 4 - ERRORR! FEC_4_5 not in DVB-S2 -+{ 25 , 99 , 5 , 427280 , 173853 , 629 }, -+{ 25 , 99 , 8 , 2736881 , 1043118 , 671 }, -+{ 25 , 99 , 101 , 1385608 , 521559 , 680 }, -+{ 5 , 0 , 1 , 273088 , 254505 , 274 }, -+{ 5 , 0 , 100 , 17272 , 13395 , 330 }, -+{ 5 , 0 , 2 , 24344 , 16967 , 367 }, -+{ 5 , 0 , 3 , 410788 , 254505 , 413 }, -+{ 5 , 0 , 4 , 438328 , 254505 , 440 }, -+{ 5 , 0 , 5 , 30464 , 16967 , 459 }, -+{ 5 , 0 , 8 , 487832 , 254505 , 490 }, -+{ 5 , 0 , 101 , 493952 , 254505 , 496 }, -+{ 5 , 99 , 100 , 328168 , 169905 , 494 }, -+{ 5 , 99 , 2 , 24344 , 11327 , 550 }, // work for 0x0d - 11278V - DVB-S2 - 8PSK MPEG-4/HD -+{ 5 , 99 , 3 , 410788 , 169905 , 618 }, // 0x0e S2 8psk // was 4 - ERRORR! FEC_4_5 not in DVB-S2 -+{ 5 , 99 , 5 , 30464 , 11327 , 688 }, -+{ 5 , 99 , 8 , 487832 , 169905 , 735 }, -+{ 5 , 99 , 101 , 493952 , 169905 , 744 }, -+{ 13 , 0 , 1 , 273088 , 260709 , 268 }, -+{ 13 , 0 , 100 , 328168 , 260709 , 322 }, -+{ 13 , 0 , 2 , 121720 , 86903 , 358 }, -+{ 13 , 0 , 3 , 410788 , 260709 , 403 }, -+{ 13 , 0 , 4 , 438328 , 260709 , 430 }, -+{ 13 , 0 , 5 , 152320 , 86903 , 448 }, -+{ 13 , 0 , 8 , 487832 , 260709 , 479 }, -+{ 13 , 0 , 101 , 493952 , 260709 , 485 }, -+{ 13 , 99 , 100 , 328168 , 173853 , 483 }, -+{ 13 , 99 , 2 , 121720 , 57951 , 537 }, // work for 0x8d - dvb-s2 8psk -+{ 13 , 99 , 3 , 410788 , 173853 , 604 }, // was 4 - ERRORR! FEC_4_5 not in DVB-S2 -+{ 13 , 99 , 5 , 152320 , 57951 , 672 }, -+{ 13 , 99 , 8 , 487832 , 173853 , 718 }, -+{ 13 , 99 , 101 , 493952 , 173853 , 727 }, -+{ 1 , 0 , 1 , 815248 , 763515 , 273 }, -+{ 1 , 0 , 100 , 51562 , 40185 , 328 }, -+{ 1 , 0 , 2 , 72674 , 50901 , 365 }, -+{ 1 , 0 , 3 , 1226323 , 763515 , 411 }, -+{ 1 , 0 , 4 , 1308538 , 763515 , 438 }, -+{ 1 , 0 , 5 , 90944 , 50901 , 457 }, -+{ 1 , 0 , 8 , 1456322 , 763515 , 488 }, -+{ 1 , 0 , 101 , 1474592 , 763515 , 494 }, -+{ 1 , 99 , 100 , 979678 , 509715 , 492 }, -+{ 1 , 99 , 2 , 72674 , 33981 , 547 }, -+{ 1 , 99 , 3 , 1226323 , 509715 , 615 }, // was 4 - ERRORR!? FEC_4_5 not in DVB-S2 -+{ 1 , 99 , 5 , 90944 , 33981 , 685 }, -+{ 1 , 99 , 8 , 1456322 , 509715 , 731 }, -+{ 1 , 99 , 101 , 1474592 , 509715 , 740 }, -+{ 9 , 0 , 1 , 815248 , 782127 , 266 }, -+{ 9 , 0 , 100 , 979678 , 782127 , 320 }, -+{ 9 , 0 , 2 , 363370 , 260709 , 356 }, -+{ 9 , 0 , 3 , 1226323 , 782127 , 401 }, -+{ 9 , 0 , 4 , 1308538 , 782127 , 428 }, -+{ 9 , 0 , 5 , 454720 , 260709 , 446 }, -+{ 9 , 0 , 8 , 1456322 , 782127 , 476 }, -+{ 9 , 0 , 101 , 1474592 , 782127 , 482 }, -+{ 9 , 99 , 100 , 979678 , 521559 , 480 }, -+{ 9 , 99 , 2 , 363370 , 173853 , 535 }, -+{ 9 , 99 , 3 , 1226323 , 521559 , 601 }, // was 4 - ERRORR! FEC_4_5 not in DVB-S2 -+{ 9 , 99 , 5 , 454720 , 173853 , 669 }, -+{ 9 , 99 , 8 , 1456322 , 521559 , 714 }, -+{ 9 , 99 , 101 , 1474592 , 521559 , 723 }, -+{ 18 , 0 , 1 , 535 , 588 , 233 }, -+{ 18 , 0 , 2 , 1070 , 882 , 311 }, -+{ 18 , 0 , 6 , 3210 , 2058 , 399 }, -+{ 16 , 0 , 1 , 763 , 816 , 239 }, -+{ 16 , 0 , 2 , 1526 , 1224 , 319 }, -+{ 16 , 0 , 3 , 2289 , 1632 , 359 }, -+{ 16 , 0 , 5 , 3815 , 2448 , 399 }, -+{ 16 , 0 , 7 , 5341 , 3264 , 419 }, -+{ 22 , 0 , 1 , 535 , 588 , 233 }, -+{ 22 , 0 , 2 , 1070 , 882 , 311 }, -+{ 22 , 0 , 6 , 3210 , 2058 , 399 }, -+{ 20 , 0 , 1 , 143429 , 152592 , 241 }, -+{ 20 , 0 , 2 , 286858 , 228888 , 321 }, -+{ 20 , 0 , 3 , 430287 , 305184 , 361 }, -+{ 20 , 0 , 5 , 717145 , 457776 , 401 }, -+{ 20 , 0 , 7 , 1004003 , 610368 , 421 }, -+{ 2 , 0 , 1 , 584 , 588 , 254 }, -+{ 2 , 0 , 2 , 1169 , 882 , 339 }, -+{ 2 , 0 , 6 , 3507 , 2058 , 436 }, -+{ 0 , 0 , 1 , 812 , 816 , 255 }, -+{ 0 , 0 , 2 , 1624 , 1224 , 340 }, -+{ 0 , 0 , 3 , 2436 , 1632 , 382 }, -+{ 0 , 0 , 5 , 4060 , 2448 , 425 }, -+{ 0 , 0 , 7 , 5684 , 3264 , 446 }, -+{ 6 , 0 , 1 , 584 , 588 , 254 }, -+{ 6 , 0 , 2 , 1168 , 882 , 339 }, -+{ 6 , 0 , 6 , 3504 , 2058 , 436 }, -+{ 4 , 0 , 1 , 152592 , 152592 , 256 }, -+{ 4 , 0 , 2 , 305184 , 228888 , 341 }, -+{ 4 , 0 , 3 , 457776 , 305184 , 384 }, -+{ 4 , 0 , 5 , 762960 , 457776 , 427 }, -+{ 4 , 0 , 7 , 1068144 , 610368 , 448 }, -+}; -diff -NurEbBw --strip-trailing-cr linux-3.4-r1/drivers/media/dvb-frontends/cx24120.h linux-3.4-r1-S2/drivers/media/dvb-frontends/cx24120.h ---- linux-3.4-r1/drivers/media/dvb-frontends/cx24120.h 1970-01-01 03:00:00.000000000 +0300 -+++ linux-3.4-r1-S2/drivers/media/dvb-frontends/cx24120.h 2012-04-03 10:27:59.000000000 +0400 -@@ -0,0 +1,59 @@ -+/* -+ * Conexant CX24120/CX24118 - DVB-S/S2 demod/tuner driver -+ * -+ * Copyright (C) 2008 Patrick Boettcher -+ * Copyright (C) 2009 Sergey Tyurin -+ * Updated 2012 by Jannis Achstetter -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#ifndef CX24120_H -+#define CX24120_H -+ -+#include -+ -+struct firmware; -+struct dvb_frontend; -+struct i2c_adapter; -+ -+struct cx24120_config -+{ -+ u8 i2c_addr; -+ int (*request_firmware)(struct dvb_frontend *fe, const struct firmware **fw, char *name); -+ void (*stream_control)(struct dvb_frontend *fe, u8 onoff); -+}; -+ -+#if defined(CONFIG_DVB_CX24120) || \ -+ (defined(CONFIG_DVB_CX24120_MODULE) && defined(MODULE)) -+extern struct dvb_frontend *cx24120_attach(const struct cx24120_config *config, -+ struct i2c_adapter *i2c); -+extern int cx24120_reset(struct dvb_frontend *fe); -+#else -+static inline -+struct dvb_frontend *cx24120_attach(const struct cx24120_config *config, -+ struct i2c_adapter *i2c) -+{ -+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); -+ return NULL; -+} -+static inline int cx24120_reset(struct dvb_frontend *fe) -+{ -+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); -+ return -ENODEV; -+} -+#endif -+ -+#endif -diff -NurEbBw --strip-trailing-cr linux-3.4-r1/drivers/media/dvb-frontends/Kconfig linux-3.4-r1-S2/drivers/media/dvb-frontends/Kconfig ---- linux-3.4-r1/drivers/media/dvb-frontends/Kconfig 2012-04-03 15:23:44.976143444 +0400 -+++ linux-3.4-r1-S2/drivers/media/dvb-frontends/Kconfig 2012-04-03 15:26:40.760141513 +0400 -@@ -4,6 +4,13 @@ - comment "Multistandard (satellite) frontends" - depends on DVB_CORE - -+config DVB_CX24120 -+ tristate "Conexant CX24120 based" -+ depends on DVB_CORE && I2C -+ default m if DVB_FE_CUSTOMISE -+ help -+ A DVB-S/DVB-S2 tuner module. Say Y when you want to support this frontend. -+ - config DVB_STB0899 - tristate "STB0899 based" - depends on DVB_CORE && I2C -diff -NurEbBw --strip-trailing-cr linux-3.4-r1/drivers/media/dvb-frontends/Makefile linux-3.4-r1-S2/drivers/media/dvb-frontends/Makefile ---- linux-3.4-r1/drivers/media/dvb-frontends/Makefile 2012-04-03 15:23:44.976143444 +0400 -+++ linux-3.4-r1-S2/drivers/media/dvb-frontends/Makefile 2012-04-03 15:26:40.760141513 +0400 -@@ -19,6 +19,10 @@ - obj-$(CONFIG_DVB_CX22700) += cx22700.o - obj-$(CONFIG_DVB_S5H1432) += s5h1432.o - obj-$(CONFIG_DVB_CX24110) += cx24110.o -+ -+# inserted by Custler -+obj-$(CONFIG_DVB_CX24120) += cx24120.o -+ - obj-$(CONFIG_DVB_TDA8083) += tda8083.o - obj-$(CONFIG_DVB_L64781) += l64781.o - obj-$(CONFIG_DVB_DIB3000MB) += dib3000mb.o diff --git a/packages/linux/patches/3.11.6/linux-998.01-cpufreq-revert-9d3ce4af3be0235d4cf41ea9fd774205a32e58a2.patch b/packages/linux/patches/3.11.6/linux-998.01-cpufreq-revert-9d3ce4af3be0235d4cf41ea9fd774205a32e58a2.patch deleted file mode 100644 index 7ba44dc839..0000000000 --- a/packages/linux/patches/3.11.6/linux-998.01-cpufreq-revert-9d3ce4af3be0235d4cf41ea9fd774205a32e58a2.patch +++ /dev/null @@ -1,84 +0,0 @@ -This reverts -https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/patch/?id=9d3ce4af3be0235d4cf41ea9fd774205a32e58a2 - -From 9d3ce4af3be0235d4cf41ea9fd774205a32e58a2 Mon Sep 17 00:00:00 2001 -From: Srivatsa S. Bhat -Date: Thu, 11 Jul 2013 22:15:37 +0000 -Subject: cpufreq: Revert commit a66b2e to fix suspend/resume regression - -commit aae760ed21cd690fe8a6db9f3a177ad55d7e12ab upstream. - -commit a66b2e (cpufreq: Preserve sysfs files across suspend/resume) -has unfortunately caused several things in the cpufreq subsystem to -break subtly after a suspend/resume cycle. - -The intention of that patch was to retain the file permissions of the -cpufreq related sysfs files across suspend/resume. To achieve that, -the commit completely removed the calls to cpufreq_add_dev() and -__cpufreq_remove_dev() during suspend/resume transitions. But the -problem is that those functions do 2 kinds of things: - 1. Low-level initialization/tear-down that are critical to the - correct functioning of cpufreq-core. - 2. Kobject and sysfs related initialization/teardown. - -Ideally we should have reorganized the code to cleanly separate these -two responsibilities, and skipped only the sysfs related parts during -suspend/resume. Since we skipped the entire callbacks instead (which -also included some CPU and cpufreq-specific critical components), -cpufreq subsystem started behaving erratically after suspend/resume. - -So revert the commit to fix the regression. We'll revisit and address -the original goal of that commit separately, since it involves quite a -bit of careful code reorganization and appears to be non-trivial. - -(While reverting the commit, note that another commit f51e1eb - (cpufreq: Fix cpufreq regression after suspend/resume) already - reverted part of the original set of changes. So revert only the - remaining ones). - -Signed-off-by: Srivatsa S. Bhat -Acked-by: Viresh Kumar -Tested-by: Paul Bolle -Signed-off-by: Rafael J. Wysocki -Signed-off-by: Greg Kroah-Hartman - ---- -diff -Naur linux-3.10.4/drivers/cpufreq/cpufreq.c linux-3.10.4.patch/drivers/cpufreq/cpufreq.c ---- linux-3.10.4/drivers/cpufreq/cpufreq.c 2013-07-29 01:30:49.000000000 +0200 -+++ linux-3.10.4.patch/drivers/cpufreq/cpufreq.c 2013-07-30 08:08:08.016815021 +0200 -@@ -1837,15 +1837,13 @@ - if (dev) { - switch (action) { - case CPU_ONLINE: -- case CPU_ONLINE_FROZEN: - cpufreq_add_dev(dev, NULL); - break; - case CPU_DOWN_PREPARE: -- case CPU_DOWN_PREPARE_FROZEN: -+ case CPU_UP_CANCELED_FROZEN: - __cpufreq_remove_dev(dev, NULL); - break; - case CPU_DOWN_FAILED: -- case CPU_DOWN_FAILED_FROZEN: - cpufreq_add_dev(dev, NULL); - break; - } -diff -Naur linux-3.10.4/drivers/cpufreq/cpufreq_stats.c linux-3.10.4.patch/drivers/cpufreq/cpufreq_stats.c ---- linux-3.10.4/drivers/cpufreq/cpufreq_stats.c 2013-07-29 01:30:49.000000000 +0200 -+++ linux-3.10.4.patch/drivers/cpufreq/cpufreq_stats.c 2013-07-30 08:08:08.016815021 +0200 -@@ -353,11 +353,13 @@ - cpufreq_update_policy(cpu); - break; - case CPU_DOWN_PREPARE: -- case CPU_DOWN_PREPARE_FROZEN: - cpufreq_stats_free_sysfs(cpu); - break; - case CPU_DEAD: -- case CPU_DEAD_FROZEN: -+ cpufreq_stats_free_table(cpu); -+ break; -+ case CPU_UP_CANCELED_FROZEN: -+ cpufreq_stats_free_sysfs(cpu); - cpufreq_stats_free_table(cpu); - break; - } diff --git a/packages/linux/patches/3.11.6/linux-999.02-A-split-for-ds3000-ts2020-code-forgot-to-change-the-.patch b/packages/linux/patches/3.11.6/linux-999.02-A-split-for-ds3000-ts2020-code-forgot-to-change-the-.patch deleted file mode 100644 index 3e88b490ed..0000000000 --- a/packages/linux/patches/3.11.6/linux-999.02-A-split-for-ds3000-ts2020-code-forgot-to-change-the-.patch +++ /dev/null @@ -1,30 +0,0 @@ -From edab54fcfb1eb4b56868d2e364cf49dc3c6bad25 Mon Sep 17 00:00:00 2001 -From: Stefan Saraev -Date: Wed, 18 Sep 2013 14:52:05 +0300 -Subject: [PATCH] A split for ds3000/ts2020 code forgot to change the TEVII_S471 code. - Change the TEVII_S471 according the changes to TEVII_S470. - -BP: https://linuxtv.org/patch/19731/ ---- - drivers/media/pci/cx23885/cx23885-dvb.c | 5 +++++ - 1 files changed, 5 insertions(+), 0 deletions(-) - -diff --git a/drivers/media/pci/cx23885/cx23885-dvb.c b/drivers/media/pci/cx23885/cx23885-dvb.c -index 5db14f8..4cbf20a 100644 ---- a/drivers/media/pci/cx23885/cx23885-dvb.c -+++ b/drivers/media/pci/cx23885/cx23885-dvb.c -@@ -1339,6 +1339,11 @@ static int dvb_register(struct cx23885_tsport *port) - fe0->dvb.frontend = dvb_attach(ds3000_attach, - &tevii_ds3000_config, - &i2c_bus->i2c_adap); -+ if (fe0->dvb.frontend != NULL) { -+ dvb_attach(ts2020_attach, fe0->dvb.frontend, -+ &tevii_ts2020_config, &i2c_bus->i2c_adap); -+ fe0->dvb.frontend->ops.set_voltage = f300_set_voltage; -+ } - break; - case CX23885_BOARD_BST_PS8512: - case CX23885_BOARD_DVBSKY_S950: --- -1.7.2.5 - diff --git a/projects/RPi/linux/linux.arm.conf b/projects/RPi/linux/linux.arm.conf index 1be55b142e..d49662b10c 100644 --- a/projects/RPi/linux/linux.arm.conf +++ b/projects/RPi/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 3.11.0 Kernel Configuration +# Linux/arm 3.12.0 Kernel Configuration # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -51,15 +51,14 @@ CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_FHANDLE=y # CONFIG_AUDIT is not set -CONFIG_HAVE_GENERIC_HARDIRQS=y # # IRQ subsystem # -CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_IRQ_SHOW=y CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_FORCED_THREADING=y CONFIG_KTIME_SCALAR=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -114,6 +113,7 @@ CONFIG_CGROUPS=y # CONFIG_BLK_CGROUP is not set # CONFIG_CHECKPOINT_RESTORE is not set # CONFIG_NAMESPACES is not set +# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set # CONFIG_SCHED_AUTOGROUP is not set # CONFIG_SYSFS_DEPRECATED is not set # CONFIG_RELAY is not set @@ -162,7 +162,6 @@ CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set -CONFIG_SLUB_CPU_PARTIAL=y # CONFIG_PROFILING is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set @@ -208,6 +207,7 @@ CONFIG_LBDAF=y CONFIG_BLK_DEV_BSG=y CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set # # Partition Types @@ -232,6 +232,7 @@ CONFIG_LDM_PARTITION=y # CONFIG_KARMA_PARTITION is not set CONFIG_EFI_PARTITION=y # CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set # # IO Schedulers @@ -291,18 +292,6 @@ CONFIG_ARCH_BCM2708=y # CONFIG_GPIO_PCA953X is not set # CONFIG_PLAT_SPEAR is not set -# -# ST-Ericsson AB U300/U335 Platform -# - -# -# ST-Ericsson Mobile Platform Products -# - -# -# ST-Ericsson U300/U335 Feature Selections -# - # # Broadcom BCM2708 Implementations # @@ -310,8 +299,8 @@ CONFIG_MACH_BCM2708=y CONFIG_BCM2708_GPIO=y CONFIG_BCM2708_VCMEM=y # CONFIG_BCM2708_NOL2CACHE is not set -CONFIG_BCM2708_DMAER=y CONFIG_BCM2708_SPIDEV=y +CONFIG_BCM2708_DMAER=y # # Processor Type @@ -365,7 +354,14 @@ CONFIG_ARCH_NR_GPIO=0 # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y CONFIG_PREEMPT_COUNT=y -CONFIG_HZ=100 +CONFIG_HZ_FIXED=0 +# CONFIG_HZ_100 is not set +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +CONFIG_HZ_300=y +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=300 CONFIG_SCHED_HRTICK=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set @@ -373,6 +369,7 @@ CONFIG_AEABI=y # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set CONFIG_HAVE_ARCH_PFN_VALID=y # CONFIG_HIGHMEM is not set +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_HAVE_MEMBLOCK=y @@ -389,6 +386,7 @@ CONFIG_CROSS_MEMORY_ATTACH=y CONFIG_NEED_PER_CPU_KM=y CONFIG_CLEANCACHE=y CONFIG_FRONTSWAP=y +# CONFIG_CMA is not set # CONFIG_ZBUD is not set # CONFIG_ZSWAP is not set CONFIG_FORCE_MAX_ZONEORDER=11 @@ -439,15 +437,20 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y # # ARM CPU frequency scaling drivers # -# CONFIG_ARM_EXYNOS4210_CPUFREQ is not set -# CONFIG_ARM_EXYNOS4X12_CPUFREQ is not set -# CONFIG_ARM_EXYNOS5250_CPUFREQ is not set # CONFIG_ARM_KIRKWOOD_CPUFREQ is not set CONFIG_ARM_BCM2835_CPUFREQ=y + +# +# CPU Idle +# CONFIG_CPU_IDLE=y # CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y + +# +# ARM CPU Idle Drivers +# # CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set # @@ -501,7 +504,6 @@ CONFIG_NET_IP_TUNNEL=m CONFIG_IP_MROUTE=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y -# CONFIG_ARPD is not set # CONFIG_SYN_COOKIES is not set # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set @@ -737,7 +739,6 @@ CONFIG_FW_LOADER_USER_HELPER=y # CONFIG_SYS_HYPERVISOR is not set # CONFIG_GENERIC_CPU_DEVICES is not set CONFIG_DMA_SHARED_BUFFER=y -# CONFIG_CMA is not set # # Bus devices @@ -941,6 +942,7 @@ CONFIG_USB_NET_CDCETHER=m # CONFIG_USB_NET_CDC_NCM is not set # CONFIG_USB_NET_CDC_MBIM is not set CONFIG_USB_NET_DM9601=m +# CONFIG_USB_NET_SR9700 is not set CONFIG_USB_NET_SMSC75XX=m CONFIG_USB_NET_SMSC95XX=y # CONFIG_USB_NET_GL620A is not set @@ -1015,6 +1017,7 @@ CONFIG_RT73USB=m CONFIG_RT2800USB=m CONFIG_RT2800USB_RT33XX=y CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT3573=y CONFIG_RT2800USB_RT53XX=y CONFIG_RT2800USB_RT55XX=y CONFIG_RT2800USB_UNKNOWN=y @@ -1156,6 +1159,7 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_IFX6X60 is not set # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_ST_ASC is not set # CONFIG_TTY_PRINTK is not set # CONFIG_HVC_DCC is not set # CONFIG_IPMI_HANDLER is not set @@ -1221,6 +1225,7 @@ CONFIG_SPI_MASTER=y CONFIG_SPI_BCM2708=y # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_DSPI is not set # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_PL022 is not set # CONFIG_SPI_PXA2XX_PCI is not set @@ -1294,6 +1299,10 @@ CONFIG_GPIO_SYSFS=y # AC97 GPIO expanders: # +# +# LPC GPIO expanders: +# + # # MODULbus GPIO expanders: # @@ -1317,8 +1326,8 @@ CONFIG_POWER_SUPPLY=y # CONFIG_CHARGER_LP8727 is not set # CONFIG_CHARGER_GPIO is not set # CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_SMB347 is not set -# CONFIG_BATTERY_GOLDFISH is not set # CONFIG_POWER_RESET is not set CONFIG_POWER_RESET_RESTART=y # CONFIG_POWER_AVS is not set @@ -1358,6 +1367,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_GPIO_FAN is not set # CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HTU21 is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_JC42 is not set # CONFIG_SENSORS_LINEAGE is not set @@ -1476,6 +1486,7 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_DA9052_SPI is not set # CONFIG_MFD_DA9052_I2C is not set # CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9063 is not set # CONFIG_MFD_MC13XXX_SPI is not set # CONFIG_MFD_MC13XXX_I2C is not set # CONFIG_HTC_EGPIO is not set @@ -1599,7 +1610,7 @@ CONFIG_VIDEO_PVRUSB2_DVB=y # CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set # CONFIG_VIDEO_HDPVR is not set # CONFIG_VIDEO_USBVISION is not set -# CONFIG_VIDEO_STK1160 is not set +# CONFIG_VIDEO_STK1160_COMMON is not set # # Analog/digital TV USB devices @@ -1681,7 +1692,6 @@ CONFIG_CYPRESS_FIRMWARE=m CONFIG_DVB_B2C2_FLEXCOP=m CONFIG_SMS_SIANO_MDTV=m CONFIG_SMS_SIANO_RC=y -# CONFIG_SMS_SIANO_DEBUGFS is not set # # Media ancillary drivers (tuners, sensors, i2c, frontends) @@ -1914,6 +1924,7 @@ CONFIG_FB_BCM2708=y # CONFIG_FB_METRONOME is not set # CONFIG_FB_BROADSHEET is not set # CONFIG_FB_AUO_K190X is not set +# CONFIG_FB_SIMPLE is not set # CONFIG_EXYNOS_VIDEO is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set @@ -1997,6 +2008,7 @@ CONFIG_HID_TOPSEED=y # CONFIG_HID_THRUSTMASTER is not set # CONFIG_HID_WACOM is not set CONFIG_HID_WIIMOTE=m +# CONFIG_HID_XINMO is not set # CONFIG_HID_ZEROPLUS is not set CONFIG_HID_ZYDACRON=y # CONFIG_HID_SENSOR_HUB is not set @@ -2012,6 +2024,7 @@ CONFIG_USB_HIDDEV=y # I2C HID support # # CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=y CONFIG_USB_ARCH_HAS_HCD=y @@ -2040,11 +2053,13 @@ CONFIG_USB_MON=m # CONFIG_USB_ISP1760_HCD is not set # CONFIG_USB_ISP1362_HCD is not set # CONFIG_USB_FUSBH200_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set # CONFIG_USB_OHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set CONFIG_USB_DWCOTG=y # CONFIG_USB_HCD_SSB is not set +# CONFIG_USB_HCD_TEST_MODE is not set # # USB Device Class drivers @@ -2083,13 +2098,13 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USB_DWC3 is not set -# CONFIG_USB_CHIPIDEA is not set # # USB port drivers # CONFIG_USB_SERIAL=m CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_SIMPLE is not set # CONFIG_USB_SERIAL_AIRCABLE is not set # CONFIG_USB_SERIAL_ARK3116 is not set # CONFIG_USB_SERIAL_BELKIN is not set @@ -2100,7 +2115,6 @@ CONFIG_USB_SERIAL_CP210X=m # CONFIG_USB_SERIAL_CYPRESS_M8 is not set # CONFIG_USB_SERIAL_EMPEG is not set CONFIG_USB_SERIAL_FTDI_SIO=m -# CONFIG_USB_SERIAL_FUNSOFT is not set # CONFIG_USB_SERIAL_VISOR is not set # CONFIG_USB_SERIAL_IPAQ is not set # CONFIG_USB_SERIAL_IR is not set @@ -2118,16 +2132,13 @@ CONFIG_USB_SERIAL_IUU=m # CONFIG_USB_SERIAL_METRO is not set # CONFIG_USB_SERIAL_MOS7720 is not set # CONFIG_USB_SERIAL_MOS7840 is not set -# CONFIG_USB_SERIAL_MOTOROLA is not set # CONFIG_USB_SERIAL_NAVMAN is not set CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_SERIAL_OTI6858 is not set # CONFIG_USB_SERIAL_QCAUX is not set # CONFIG_USB_SERIAL_QUALCOMM is not set # CONFIG_USB_SERIAL_SPCP8X5 is not set -# CONFIG_USB_SERIAL_HP4X is not set # CONFIG_USB_SERIAL_SAFE is not set -# CONFIG_USB_SERIAL_SIEMENS_MPI is not set # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set # CONFIG_USB_SERIAL_SYMBOL is not set # CONFIG_USB_SERIAL_TI is not set @@ -2136,15 +2147,11 @@ CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_SERIAL_OPTION is not set # CONFIG_USB_SERIAL_OMNINET is not set # CONFIG_USB_SERIAL_OPTICON is not set -# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set # CONFIG_USB_SERIAL_XSENS_MT is not set -# CONFIG_USB_SERIAL_ZIO is not set # CONFIG_USB_SERIAL_WISHBONE is not set # CONFIG_USB_SERIAL_ZTE is not set # CONFIG_USB_SERIAL_SSU100 is not set # CONFIG_USB_SERIAL_QT2 is not set -# CONFIG_USB_SERIAL_FLASHLOADER is not set -# CONFIG_USB_SERIAL_SUUNTO is not set # CONFIG_USB_SERIAL_DEBUG is not set # @@ -2167,11 +2174,24 @@ CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_YUREX is not set # CONFIG_USB_EZUSB_FX2 is not set # CONFIG_USB_HSIC_USB3503 is not set + +# +# USB Physical Layer drivers +# # CONFIG_USB_PHY is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_AM335X_PHY_USB is not set +# CONFIG_SAMSUNG_USB2PHY is not set +# CONFIG_SAMSUNG_USB3PHY is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_RCAR_PHY is not set +# CONFIG_USB_ULPI is not set # CONFIG_USB_GADGET is not set CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set @@ -2217,12 +2237,12 @@ CONFIG_LEDS_GPIO=y # CONFIG_LEDS_LP5521 is not set # CONFIG_LEDS_LP5523 is not set # CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_LP8501 is not set # CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_PCA9633 is not set +# CONFIG_LEDS_PCA963X is not set # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_BD2802 is not set # CONFIG_LEDS_LT3593 is not set -# CONFIG_LEDS_RENESAS_TPU is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_LM355x is not set # CONFIG_LEDS_OT200 is not set @@ -2325,6 +2345,7 @@ CONFIG_RTC_DRV_DS1307=y # # CONFIG_RTC_DRV_PL030 is not set # CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_MOXART is not set # # HID Sensor RTC drivers @@ -2349,9 +2370,9 @@ CONFIG_STAGING=y # CONFIG_PRISM2_USB is not set # CONFIG_ECHO is not set # CONFIG_COMEDI is not set -# CONFIG_ASUS_OLED is not set # CONFIG_RTLLIB is not set CONFIG_R8712U=m +# CONFIG_R8188EU is not set CONFIG_RTS5139=m # CONFIG_RTS5139_DEBUG is not set # CONFIG_TRANZPORT is not set @@ -2372,6 +2393,7 @@ CONFIG_ZRAM=y # CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set CONFIG_STAGING_MEDIA=y CONFIG_DVB_AS102=m +# CONFIG_USB_MSI3101 is not set CONFIG_LIRC_STAGING=y CONFIG_LIRC_IGORPLUGUSB=m # CONFIG_LIRC_IMON is not set @@ -2388,11 +2410,13 @@ CONFIG_LIRC_XBOX=m # CONFIG_ANDROID is not set # CONFIG_USB_WPAN_HCD is not set # CONFIG_WIMAX_GDM72XX is not set +# CONFIG_LTE_GDM724X is not set # CONFIG_CED1401 is not set # CONFIG_DGRP is not set -CONFIG_ZCACHE=y -# CONFIG_ZCACHE_DEBUG is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_LUSTRE_FS is not set # CONFIG_USB_BTMTK is not set +# CONFIG_DGAP is not set CONFIG_CLKDEV_LOOKUP=y # @@ -2453,6 +2477,7 @@ CONFIG_BTRFS_FS=y # CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set # CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set # CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_ASSERT is not set # CONFIG_NILFS2_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_EXPORTFS=y @@ -2510,6 +2535,7 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_ECRYPT_FS is not set CONFIG_HFS_FS=y CONFIG_HFSPLUS_FS=y +# CONFIG_HFSPLUS_FS_POSIX_ACL is not set # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set @@ -2746,6 +2772,8 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_DEBUG_USER is not set # CONFIG_DEBUG_LL is not set CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_PL01X is not set +# CONFIG_DEBUG_UART_8250 is not set CONFIG_UNCOMPRESS_INCLUDE="mach/uncompress.h" # CONFIG_OC_ETM is not set # CONFIG_PID_IN_CONTEXTIDR is not set @@ -2818,6 +2846,7 @@ CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set # CONFIG_CRYPTO_GHASH is not set CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y diff --git a/projects/RPi/options b/projects/RPi/options index 8618d98795..36229bfd0e 100755 --- a/projects/RPi/options +++ b/projects/RPi/options @@ -111,7 +111,7 @@ # Kernel to use. values can be: # default: default mainline kernel - LINUX="3.11" + LINUX="default" # use linux-next (latest rc) instead latest released version LINUX_NEXT="no" diff --git a/projects/RPi/patches/linux/linux-01-RPi_support-d747469.patch b/projects/RPi/patches/linux/linux-01-RPi_support-a2a4960.patch similarity index 96% rename from projects/RPi/patches/linux/linux-01-RPi_support-d747469.patch rename to projects/RPi/patches/linux/linux-01-RPi_support-a2a4960.patch index 256b03e9e3..e9addac07f 100644 --- a/projects/RPi/patches/linux/linux-01-RPi_support-d747469.patch +++ b/projects/RPi/patches/linux/linux-01-RPi_support-a2a4960.patch @@ -1,7 +1,7 @@ -From 9fca890f6bf59e17b10e3bc69725184503faf07b Mon Sep 17 00:00:00 2001 +From 06783b43efa0a0e80f87cfb87f809b04e490bf8b Mon Sep 17 00:00:00 2001 From: popcornmix Date: Sun, 12 May 2013 12:24:19 +0100 -Subject: [PATCH 01/98] Main bcm2708 linux port +Subject: [PATCH 01/82] Main bcm2708 linux port Signed-off-by: popcornmix --- @@ -11,12 +11,13 @@ Signed-off-by: popcornmix arch/arm/configs/bcmrpi_cutdown_defconfig | 474 +++++++ arch/arm/configs/bcmrpi_defconfig | 510 ++++++++ arch/arm/configs/bcmrpi_emergency_defconfig | 532 ++++++++ + arch/arm/kernel/process.c | 10 + arch/arm/mach-bcm2708/Kconfig | 34 + arch/arm/mach-bcm2708/Makefile | 7 + arch/arm/mach-bcm2708/Makefile.boot | 3 + arch/arm/mach-bcm2708/armctrl.c | 208 ++++ arch/arm/mach-bcm2708/armctrl.h | 27 + - arch/arm/mach-bcm2708/bcm2708.c | 638 ++++++++++ + arch/arm/mach-bcm2708/bcm2708.c | 711 +++++++++++ arch/arm/mach-bcm2708/bcm2708.h | 51 + arch/arm/mach-bcm2708/bcm2708_gpio.c | 339 +++++ arch/arm/mach-bcm2708/clock.c | 61 + @@ -36,7 +37,7 @@ Signed-off-by: popcornmix arch/arm/mach-bcm2708/include/mach/memory.h | 57 + arch/arm/mach-bcm2708/include/mach/platform.h | 220 ++++ arch/arm/mach-bcm2708/include/mach/power.h | 26 + - arch/arm/mach-bcm2708/include/mach/system.h | 53 + + arch/arm/mach-bcm2708/include/mach/system.h | 38 + arch/arm/mach-bcm2708/include/mach/timex.h | 23 + arch/arm/mach-bcm2708/include/mach/uncompress.h | 84 ++ arch/arm/mach-bcm2708/include/mach/vc_mem.h | 35 + @@ -51,11 +52,11 @@ Signed-off-by: popcornmix drivers/mmc/host/Kconfig | 21 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-bcm2708.c | 1424 ++++++++++++++++++++++ - drivers/mmc/host/sdhci.c | 209 +++- + drivers/mmc/host/sdhci.c | 203 ++- drivers/mmc/host/sdhci.h | 37 + drivers/tty/serial/amba-pl011.c | 2 +- include/linux/mmc/sdhci.h | 2 + - 50 files changed, 7732 insertions(+), 72 deletions(-) + 51 files changed, 7794 insertions(+), 72 deletions(-) create mode 100644 arch/arm/configs/bcmrpi_cutdown_defconfig create mode 100644 arch/arm/configs/bcmrpi_defconfig create mode 100644 arch/arm/configs/bcmrpi_emergency_defconfig @@ -96,10 +97,10 @@ Signed-off-by: popcornmix create mode 100644 drivers/mmc/host/sdhci-bcm2708.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index 43594d5..9935688 100644 +index 1ad6fb6..54da673 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -366,6 +366,21 @@ config ARCH_AT91 +@@ -368,6 +368,21 @@ config ARCH_AT91 This enables support for systems based on Atmel AT91RM9200 and AT91SAM9* processors. @@ -121,7 +122,7 @@ index 43594d5..9935688 100644 config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" select ARCH_REQUIRE_GPIOLIB -@@ -1041,6 +1056,7 @@ source "arch/arm/mach-virt/Kconfig" +@@ -1043,6 +1058,7 @@ source "arch/arm/mach-virt/Kconfig" source "arch/arm/mach-vt8500/Kconfig" source "arch/arm/mach-w90x900/Kconfig" @@ -130,12 +131,12 @@ index 43594d5..9935688 100644 source "arch/arm/mach-zynq/Kconfig" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug -index 583f4a0..b3b654d 100644 +index 9762c84..d89dd0b 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug -@@ -610,6 +610,14 @@ choice - For more details about semihosting, please see - chapter 8 of DUI0203I_rvct_developer_guide.pdf from ARM Ltd. +@@ -847,6 +847,14 @@ choice + options; the platform specific options are deprecated + and will be soon removed. + config DEBUG_BCM2708_UART0 + bool "Broadcom BCM2708 UART0 (PL011)" @@ -149,7 +150,7 @@ index 583f4a0..b3b654d 100644 config DEBUG_EXYNOS_UART diff --git a/arch/arm/Makefile b/arch/arm/Makefile -index 6fd2cea..917f6ff 100644 +index db50b62..4470657 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -146,6 +146,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 @@ -1694,6 +1695,27 @@ index 0000000..3b40c49 +# CONFIG_CRYPTO_HW is not set +CONFIG_CRC_ITU_T=y +CONFIG_LIBCRC32C=y +diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c +index 94f6b05..dd67686 100644 +--- a/arch/arm/kernel/process.c ++++ b/arch/arm/kernel/process.c +@@ -176,6 +176,16 @@ void arch_cpu_idle(void) + default_idle(); + } + ++char bcm2708_reboot_mode = 'h'; ++ ++int __init reboot_setup(char *str) ++{ ++ bcm2708_reboot_mode = str[0]; ++ return 1; ++} ++ ++__setup("reboot=", reboot_setup); ++ + /* + * Called by kexec, immediately prior to machine_kexec(). + * diff --git a/arch/arm/mach-bcm2708/Kconfig b/arch/arm/mach-bcm2708/Kconfig new file mode 100644 index 0000000..9355841 @@ -2005,10 +2027,10 @@ index 0000000..0aa916e +#endif diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c new file mode 100644 -index 0000000..e6459b3 +index 0000000..f3d14b0 --- /dev/null +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -0,0 +1,638 @@ +@@ -0,0 +1,711 @@ +/* + * linux/arch/arm/mach-bcm2708/bcm2708.c + * @@ -2069,6 +2091,11 @@ index 0000000..e6459b3 +#include "armctrl.h" +#include "clock.h" + ++#ifdef CONFIG_BCM_VC_CMA ++#include ++#endif ++ ++ +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to + * give us IO access only to 64Mbytes of physical memory (26 bits). We could + * represent this window by setting our dmamasks to 26 bits but, in fact @@ -2084,6 +2111,7 @@ index 0000000..e6459b3 +/* command line parameters */ +static unsigned boardrev, serial; +static unsigned uart_clock; ++static unsigned reboot_part = 0; + +static void __init bcm2708_init_led(void); + @@ -2446,21 +2474,78 @@ index 0000000..e6459b3 + return ret; +} + ++int calc_rsts(int partition) ++{ ++ return PM_PASSWORD | ++ ((partition & (1 << 0)) << 0) | ++ ((partition & (1 << 1)) << 1) | ++ ((partition & (1 << 2)) << 2) | ++ ((partition & (1 << 3)) << 3) | ++ ((partition & (1 << 4)) << 4) | ++ ((partition & (1 << 5)) << 5); ++} ++ ++static void bcm2708_restart(enum reboot_mode mode, const char *cmd) ++{ ++ extern char bcm2708_reboot_mode; ++ uint32_t pm_rstc, pm_wdog; ++ uint32_t timeout = 10; ++ uint32_t pm_rsts = 0; ++ ++ if(bcm2708_reboot_mode == 'q') ++ { ++ // NOOBS < 1.3 booting with reboot=q ++ pm_rsts = readl(__io_address(PM_RSTS)); ++ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET; ++ } ++ else if(bcm2708_reboot_mode == 'p') ++ { ++ // NOOBS < 1.3 halting ++ pm_rsts = readl(__io_address(PM_RSTS)); ++ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET; ++ } ++ else ++ { ++ pm_rsts = calc_rsts(reboot_part); ++ } ++ ++ writel(pm_rsts, __io_address(PM_RSTS)); ++ ++ /* Setup watchdog for reset */ ++ pm_rstc = readl(__io_address(PM_RSTC)); ++ ++ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0) ++ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET; ++ ++ writel(pm_wdog, __io_address(PM_WDOG)); ++ writel(pm_rstc, __io_address(PM_RSTC)); ++} ++ +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */ +static void bcm2708_power_off(void) +{ -+ /* we set the watchdog hard reset bit here to distinguish this reset from the normal (full) reset. bootcode.bin will not reboot after a hard reset */ -+ uint32_t pm_rsts = readl(__io_address(PM_RSTS)); -+ pm_rsts = PM_PASSWORD | (pm_rsts & PM_RSTC_WRCFG_CLR) | PM_RSTS_HADWRH_SET; -+ writel(pm_rsts, __io_address(PM_RSTS)); -+ /* continue with normal reset mechanism */ -+ arch_reset(0, ""); ++ extern char bcm2708_reboot_mode; ++ if(bcm2708_reboot_mode == 'q') ++ { ++ // NOOBS < v1.3 ++ bcm2708_restart('p', ""); ++ } ++ else ++ { ++ /* partition 63 is special code for HALT the bootloader knows not to boot*/ ++ reboot_part = 63; ++ /* continue with normal reset mechanism */ ++ bcm2708_restart(0, ""); ++ } +} + +void __init bcm2708_init(void) +{ + int i; + ++#if defined(CONFIG_BCM_VC_CMA) ++ vc_cma_early_init(); ++#endif + printk("bcm2708.uart_clock = %d\n", uart_clock); + pm_power_off = bcm2708_power_off; + @@ -2632,7 +2717,14 @@ index 0000000..e6459b3 + * context. Increase size of atomic coherent pool to make sure such + * the allocations won't fail. + */ -+ init_dma_coherent_pool_size(SZ_2M); ++ init_dma_coherent_pool_size(SZ_4M); ++} ++ ++static void __init board_reserve(void) ++{ ++#if defined(CONFIG_BCM_VC_CMA) ++ vc_cma_reserve(); ++#endif +} + +MACHINE_START(BCM2708, "BCM2708") @@ -2642,11 +2734,14 @@ index 0000000..e6459b3 + .init_time = bcm2708_timer_init, + .init_machine = bcm2708_init, + .init_early = bcm2708_init_early, ++ .reserve = board_reserve, ++ .restart = bcm2708_restart, +MACHINE_END + +module_param(boardrev, uint, 0644); +module_param(serial, uint, 0644); +module_param(uart_clock, uint, 0644); ++module_param(reboot_part, uint, 0644); diff --git a/arch/arm/mach-bcm2708/bcm2708.h b/arch/arm/mach-bcm2708/bcm2708.h new file mode 100644 index 0000000..dfe8700 @@ -4909,10 +5004,10 @@ index 0000000..52b3b02 +#endif diff --git a/arch/arm/mach-bcm2708/include/mach/system.h b/arch/arm/mach-bcm2708/include/mach/system.h new file mode 100644 -index 0000000..bc9d458 +index 0000000..2d0b821 --- /dev/null +++ b/arch/arm/mach-bcm2708/include/mach/system.h -@@ -0,0 +1,53 @@ +@@ -0,0 +1,38 @@ +/* + * arch/arm/mach-bcm2708/include/mach/system.h + * @@ -4950,21 +5045,6 @@ index 0000000..bc9d458 + cpu_do_idle(); +} + -+static inline void arch_reset(char mode, const char *cmd) -+{ -+ uint32_t pm_rstc, pm_wdog; -+ uint32_t timeout = 10; -+ -+ /* Setup watchdog for reset */ -+ pm_rstc = readl(IO_ADDRESS(PM_RSTC)); -+ -+ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0) -+ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET; -+ -+ writel(pm_wdog, IO_ADDRESS(PM_WDOG)); -+ writel(pm_rstc, IO_ADDRESS(PM_RSTC)); -+} -+ +#endif diff --git a/arch/arm/mach-bcm2708/include/mach/timex.h b/arch/arm/mach-bcm2708/include/mach/timex.h new file mode 100644 @@ -6500,7 +6580,7 @@ index a10297d..c9ddd87 100644 ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206 wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig -index 8a4c066..6794c7d 100644 +index 7fc5099..97cb760 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -260,6 +260,27 @@ config MMC_SDHCI_BCM_KONA @@ -6532,7 +6612,7 @@ index 8a4c066..6794c7d 100644 tristate "SDHCI platform support for the BCM2835 SD/MMC Controller" depends on ARCH_BCM2835 diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile -index d422e21..3589f43 100644 +index c41d0c3..656dfa1 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o @@ -7974,7 +8054,7 @@ index 0000000..d8ef77c +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:"DRIVER_NAME); diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c -index a78bd4f..763dbf9 100644 +index 7a7fb4f..4b250ea 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -28,6 +28,7 @@ @@ -8413,20 +8493,7 @@ index a78bd4f..763dbf9 100644 } } } -@@ -3119,6 +3187,12 @@ int sdhci_add_host(struct sdhci_host *host) - SDHCI_MAX_CURRENT_MULTIPLIER; - } - -+ if(host->ops->voltage_broken) { -+ ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; -+ // Cannot support UHS modes if we are stuck at 3.3V; -+ mmc->caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50); -+ } -+ - mmc->ocr_avail = ocr_avail; - mmc->ocr_avail_sdio = ocr_avail; - if (host->ocr_avail_sdio) -@@ -3249,6 +3323,7 @@ int sdhci_add_host(struct sdhci_host *host) +@@ -3252,6 +3320,7 @@ int sdhci_add_host(struct sdhci_host *host) pr_info("%s: SDHCI controller on %s [%s] using %s\n", mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), @@ -8490,7 +8557,7 @@ index b037f18..8a02ec8 100644 extern int sdhci_runtime_suspend_host(struct sdhci_host *host); extern int sdhci_runtime_resume_host(struct sdhci_host *host); diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c -index 28b35ad..600c755 100644 +index aaa2286..783bfb3 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -84,7 +84,7 @@ struct vendor_data { @@ -8503,7 +8570,7 @@ index 28b35ad..600c755 100644 static struct vendor_data vendor_arm = { diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h -index e3c6a74..458794c 100644 +index 3e781b8..aad2393 100644 --- a/include/linux/mmc/sdhci.h +++ b/include/linux/mmc/sdhci.h @@ -131,6 +131,7 @@ struct sdhci_host { @@ -8526,10 +8593,10 @@ index e3c6a74..458794c 100644 1.8.4 -From 03372514cc8e531599f131c04b94976899f8a420 Mon Sep 17 00:00:00 2001 +From 0c2cc902b9a01445585e9715ca2bf36a902467cf Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 7 May 2013 22:20:24 +0100 -Subject: [PATCH 02/98] Add quick config. +Subject: [PATCH 02/82] Add quick config. This is designed for quick compiling when developing. No modules are needed and it includes all Pi specific drivers @@ -8745,10 +8812,10 @@ index 0000000..e5efe75 1.8.4 -From 2572d0c01f72204a5ff7c1b92c84bb4cd5f4f415 Mon Sep 17 00:00:00 2001 +From f5449b637e752281bb486374b1b13d540375a807 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 1 May 2013 19:46:17 +0100 -Subject: [PATCH 03/98] Add dwc_otg driver +Subject: [PATCH 03/82] Add dwc_otg driver Signed-off-by: popcornmix --- @@ -8877,7 +8944,7 @@ Signed-off-by: popcornmix create mode 100644 drivers/usb/host/dwc_otg/test/test_sysfs.pl diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile -index 238c5d4..dbc71e9 100644 +index 70d7c5b..df8834b 100644 --- a/drivers/usb/Makefile +++ b/drivers/usb/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_USB_U132_HCD) += host/ @@ -8901,10 +8968,10 @@ index acbfeb0..7d675c8 100644 return i; } diff --git a/drivers/usb/core/message.c b/drivers/usb/core/message.c -index e7ee1e4..8723c20 100644 +index 82927e1..b1ffeff 100644 --- a/drivers/usb/core/message.c +++ b/drivers/usb/core/message.c -@@ -1875,6 +1875,85 @@ int usb_set_configuration(struct usb_device *dev, int configuration) +@@ -1885,6 +1885,85 @@ int usb_set_configuration(struct usb_device *dev, int configuration) if (cp->string == NULL && !(dev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS)) cp->string = usb_cache_string(dev, cp->desc.iConfiguration); @@ -12887,10 +12954,10 @@ index 0000000..a896d73 +} +module_exit(fsg_cleanup); diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig -index 4263d01..da71b93 100644 +index b3f20d7..92f4cc3 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig -@@ -671,6 +671,19 @@ config USB_HWA_HCD +@@ -650,6 +650,19 @@ config USB_HWA_HCD To compile this driver a module, choose M here: the module will be called "hwa-hc". @@ -12911,10 +12978,10 @@ index 4263d01..da71b93 100644 tristate "i.MX21 HCD support" depends on ARM && ARCH_MXC diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile -index bea7112..268b9c1 100644 +index 50b0041..64dd651 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile -@@ -52,6 +52,8 @@ obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o +@@ -56,6 +56,8 @@ obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o @@ -65820,10 +65887,10 @@ index 0000000..cdc9963 1.8.4 -From 29686c26c808ed4c2c0fe71088a6ff7d01c2d7f1 Mon Sep 17 00:00:00 2001 +From 0de58221dbee59bcb4b3ed3b2ddf3ef74bb10b7b Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 1 May 2013 19:54:32 +0100 -Subject: [PATCH 04/98] bcm2708 watchdog driver +Subject: [PATCH 04/82] bcm2708 watchdog driver Signed-off-by: popcornmix --- @@ -65834,10 +65901,10 @@ Signed-off-by: popcornmix create mode 100644 drivers/watchdog/bcm2708_wdog.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig -index 362085d..8928aed 100644 +index d1d53f3..a1eb410 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig -@@ -382,6 +382,12 @@ config RETU_WATCHDOG +@@ -392,6 +392,12 @@ config RETU_WATCHDOG To compile this driver as a module, choose M here: the module will be called retu_wdt. @@ -65851,10 +65918,10 @@ index 362085d..8928aed 100644 config AT32AP700X_WDT diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile -index 2f26a0b..fdf37ac 100644 +index 6c5bb27..7b1ca3f 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile -@@ -53,6 +53,7 @@ obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_wdt.o +@@ -54,6 +54,7 @@ obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_wdt.o obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o obj-$(CONFIG_UX500_WATCHDOG) += ux500_wdt.o obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o @@ -66256,22 +66323,22 @@ index 0000000..2f19203 1.8.4 -From 9a9e3acf4ea976ce01b1d2128ecf21611794aecb Mon Sep 17 00:00:00 2001 +From 6108fa91cd84340c79bf7bca8f5505449c017b55 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 1 May 2013 19:55:09 +0100 -Subject: [PATCH 05/98] bcm2708 framebuffer driver +Subject: [PATCH 05/82] bcm2708 framebuffer driver Signed-off-by: popcornmix --- drivers/video/Kconfig | 14 + drivers/video/Makefile | 1 + - drivers/video/bcm2708_fb.c | 491 ++++++++ - drivers/video/logo/logo_linux_clut224.ppm | 1762 ++++++++++++++--------------- - 4 files changed, 1387 insertions(+), 881 deletions(-) + drivers/video/bcm2708_fb.c | 491 ++++++ + drivers/video/logo/logo_linux_clut224.ppm | 2483 ++++++++++------------------- + 4 files changed, 1387 insertions(+), 1602 deletions(-) create mode 100644 drivers/video/bcm2708_fb.c diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig -index 4cf1e1d..9c332f1 100644 +index 84b685f..4c82aab 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -310,6 +310,20 @@ config FB_PM2_FIFO_DISCONNECT @@ -66805,894 +66872,1615 @@ index 0000000..08d9238 +MODULE_PARM_DESC(fbheight, "Height of ARM Framebuffer"); +MODULE_PARM_DESC(fbdepth, "Bit depth of ARM Framebuffer"); diff --git a/drivers/video/logo/logo_linux_clut224.ppm b/drivers/video/logo/logo_linux_clut224.ppm -index 285d552..7626beb 100644 +index 3c14e43..7626beb 100644 --- a/drivers/video/logo/logo_linux_clut224.ppm +++ b/drivers/video/logo/logo_linux_clut224.ppm -@@ -1,883 +1,883 @@ +@@ -1,1604 +1,883 @@ P3 +-# Standard 224-color Linux logo -80 80 +63 80 255 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 11 15 17 33 49 54 59 85 92 73 97 106 --83 116 129 105 131 142 115 114 122 74 88 93 20 29 31 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 6 6 6 6 6 6 10 10 10 10 10 10 --10 10 10 6 6 6 6 6 6 6 6 6 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 2 3 3 17 23 26 50 67 72 73 97 106 59 85 92 73 97 106 --105 131 142 124 127 131 105 131 142 105 131 142 53 75 83 6 8 8 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 6 6 6 10 10 10 14 14 14 22 22 22 26 26 26 30 30 30 34 34 34 --30 30 30 30 30 30 26 26 26 18 18 18 14 14 14 10 10 10 6 6 6 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 --0 0 0 1 1 1 26 35 39 59 85 92 59 85 92 59 85 92 29 43 47 53 75 83 --108 122 132 132 98 104 108 122 132 105 131 142 101 101 101 43 45 48 6 8 8 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --6 6 6 14 14 14 26 26 26 42 42 42 54 54 54 66 66 66 78 78 78 78 78 78 --78 78 78 74 74 74 66 66 66 54 54 54 42 42 42 26 26 26 18 18 18 10 10 10 --6 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- --0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 --11 15 17 27 40 45 59 85 92 59 85 92 27 40 45 31 45 49 73 97 106 93 121 133 --108 122 132 108 122 132 105 131 142 108 122 132 105 131 142 73 97 106 26 35 39 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 10 10 --22 22 22 42 42 42 66 66 66 86 86 86 66 66 66 38 38 38 38 38 38 22 22 22 --26 26 26 34 34 34 54 54 54 66 66 66 86 86 86 70 70 70 46 46 46 26 26 26 --14 14 14 6 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- --0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 7 12 13 21 31 35 42 59 64 --53 75 83 53 75 83 50 67 72 42 59 64 32 40 45 42 59 64 73 97 106 116 116 116 --132 98 104 116 116 116 108 122 132 117 104 110 105 131 142 83 116 129 50 67 72 7 12 13 --1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 10 10 26 26 26 --50 50 50 82 82 82 58 58 58 6 6 6 2 2 6 2 2 6 2 2 6 2 2 6 --2 2 6 2 2 6 2 2 6 2 2 6 6 6 6 54 54 54 86 86 86 66 66 66 --38 38 38 18 18 18 6 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- --0 0 0 1 1 1 6 8 8 15 22 25 26 35 39 36 54 60 53 75 83 59 85 92 --59 85 92 48 63 69 15 22 25 12 17 20 52 67 79 94 94 94 132 98 104 132 98 104 --117 104 110 108 122 132 108 122 132 115 114 122 105 131 142 77 105 114 59 85 92 36 54 60 --7 12 13 0 0 0 0 0 0 0 0 0 0 0 0 6 6 6 22 22 22 50 50 50 --78 78 78 34 34 34 2 2 6 2 2 6 2 2 6 2 2 6 2 2 6 2 2 6 --2 2 6 2 2 6 2 2 6 2 2 6 2 2 6 2 2 6 6 6 6 70 70 70 --78 78 78 46 46 46 22 22 22 6 6 6 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- --0 0 0 15 22 25 29 43 47 36 54 60 42 59 64 42 59 64 48 63 69 21 31 35 --6 8 8 29 43 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253 253 253 253 253 253 253 253 253 253 253 253 253 253 --253 253 253 253 253 253 253 253 253 250 250 250 238 238 238 198 198 198 6 6 6 38 38 38 --58 58 58 26 26 26 38 38 38 2 2 6 2 2 6 2 2 6 2 2 6 46 46 46 --78 78 78 30 30 30 10 10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 30 33 --36 54 60 0 0 0 0 0 0 30 30 30 74 74 74 58 58 58 2 2 6 42 42 42 --2 2 6 22 22 22 231 231 231 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 --253 253 253 253 253 253 253 253 253 250 250 250 253 253 253 253 253 253 253 253 253 253 253 253 --253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 --253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 246 246 246 46 46 46 38 38 38 --42 42 42 14 14 14 38 38 38 14 14 14 2 2 6 2 2 6 2 2 6 6 6 6 --86 86 86 46 46 46 14 14 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 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253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 --253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 231 231 231 6 6 6 --2 2 6 2 2 6 10 10 10 30 30 30 2 2 6 2 2 6 2 2 6 2 2 6 --2 2 6 66 66 66 58 58 58 22 22 22 6 6 6 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 10 10 --38 38 38 78 78 78 6 6 6 2 2 6 2 2 6 46 46 46 14 14 14 42 42 42 --246 246 246 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 --253 253 253 253 253 253 231 231 231 242 242 242 253 253 253 253 253 253 253 253 253 253 253 253 --253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 --253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 253 234 234 234 10 10 10 --2 2 6 2 2 6 22 22 22 14 14 14 2 2 6 2 2 6 2 2 6 2 2 6 --2 2 6 66 66 66 62 62 62 22 22 22 6 6 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22 22 22 22 22 22 +- 18 18 18 14 14 14 10 10 10 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 @@ -68577,10 +69365,10 @@ index 285d552..7626beb 100644 1.8.4 -From 64c1c9e9b7ec62217c51d9e79d80feb1b413269f Mon Sep 17 00:00:00 2001 +From 4d1525a5865dfc9a110d202b416c5c46de21f01b Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 2 Jul 2013 23:42:01 +0100 -Subject: [PATCH 06/98] bcm2708 vchiq driver +Subject: [PATCH 06/82] bcm2708 vchiq driver Signed-off-by: popcornmix --- @@ -68598,26 +69386,26 @@ Signed-off-by: popcornmix .../misc/vc04_services/interface/vchiq_arm/vchiq.h | 40 + .../vc04_services/interface/vchiq_arm/vchiq_2835.h | 42 + .../interface/vchiq_arm/vchiq_2835_arm.c | 538 +++ - .../vc04_services/interface/vchiq_arm/vchiq_arm.c | 2808 ++++++++++++++ + .../vc04_services/interface/vchiq_arm/vchiq_arm.c | 2813 ++++++++++++++ .../vc04_services/interface/vchiq_arm/vchiq_arm.h | 212 ++ .../interface/vchiq_arm/vchiq_build_info.h | 37 + .../vc04_services/interface/vchiq_arm/vchiq_cfg.h | 60 + .../interface/vchiq_arm/vchiq_connected.c | 119 + .../interface/vchiq_arm/vchiq_connected.h | 50 + - .../vc04_services/interface/vchiq_arm/vchiq_core.c | 3818 ++++++++++++++++++++ - .../vc04_services/interface/vchiq_arm/vchiq_core.h | 703 ++++ + .../vc04_services/interface/vchiq_arm/vchiq_core.c | 3824 ++++++++++++++++++++ + .../vc04_services/interface/vchiq_arm/vchiq_core.h | 706 ++++ .../interface/vchiq_arm/vchiq_genversion | 87 + .../vc04_services/interface/vchiq_arm/vchiq_if.h | 188 + .../interface/vchiq_arm/vchiq_ioctl.h | 129 + - .../interface/vchiq_arm/vchiq_kern_lib.c | 454 +++ + .../interface/vchiq_arm/vchiq_kern_lib.c | 456 +++ .../interface/vchiq_arm/vchiq_memdrv.h | 71 + .../interface/vchiq_arm/vchiq_pagelist.h | 58 + .../vc04_services/interface/vchiq_arm/vchiq_proc.c | 253 ++ .../vc04_services/interface/vchiq_arm/vchiq_shim.c | 815 +++++ - .../vc04_services/interface/vchiq_arm/vchiq_util.c | 120 + + .../vc04_services/interface/vchiq_arm/vchiq_util.c | 151 + .../vc04_services/interface/vchiq_arm/vchiq_util.h | 81 + .../interface/vchiq_arm/vchiq_version.c | 59 + - 33 files changed, 12175 insertions(+) + 33 files changed, 12222 insertions(+) create mode 100644 drivers/misc/vc04_services/Kconfig create mode 100644 drivers/misc/vc04_services/Makefile create mode 100644 drivers/misc/vc04_services/interface/vchi/connections/connection.h @@ -70794,10 +71582,10 @@ index 0000000..2b5fa56 +} diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c new file mode 100644 -index 0000000..f87bbdd +index 0000000..f44d4b4 --- /dev/null +++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c -@@ -0,0 +1,2808 @@ +@@ -0,0 +1,2813 @@ +/** + * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * @@ -71159,6 +71947,17 @@ index 0000000..f87bbdd + +/**************************************************************************** +* ++* user_service_free ++* ++***************************************************************************/ ++static void ++user_service_free(void *userdata) ++{ ++ kfree(userdata); ++} ++ ++/**************************************************************************** ++* +* vchiq_ioctl +* +***************************************************************************/ @@ -71267,7 +72066,7 @@ index 0000000..f87bbdd + service = vchiq_add_service_internal( + instance->state, + &args.params, srvstate, -+ instance); ++ instance, user_service_free); + + if (service != NULL) { + user_service->service = service; @@ -71290,8 +72089,6 @@ index 0000000..f87bbdd + service = NULL; + ret = (status == VCHIQ_RETRY) ? + -EINTR : -EIO; -+ user_service->service = NULL; -+ user_service->instance = NULL; + break; + } + } @@ -71303,7 +72100,6 @@ index 0000000..f87bbdd + sizeof(service->handle)) != 0) { + ret = -EFAULT; + vchiq_remove_service(service->handle); -+ kfree(user_service); + } + + service = NULL; @@ -71596,10 +72392,8 @@ index 0000000..f87bbdd + } + + if (completion->reason == -+ VCHIQ_SERVICE_CLOSED) { ++ VCHIQ_SERVICE_CLOSED) + unlock_service(service); -+ kfree(user_service); -+ } + + if (copy_to_user((void __user *)( + (size_t)args.buf + @@ -71951,7 +72745,6 @@ index 0000000..f87bbdd + spin_unlock(&msg_queue_spinlock); + + unlock_service(service); -+ kfree(user_service); + } + + /* Release any closed services */ @@ -74116,10 +74909,10 @@ index 0000000..863b3e3 +#endif /* VCHIQ_CONNECTED_H */ diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c new file mode 100644 -index 0000000..2efb124 +index 0000000..f35ed4f --- /dev/null +++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c -@@ -0,0 +1,3818 @@ +@@ -0,0 +1,3824 @@ +/** + * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * @@ -74395,6 +75188,9 @@ index 0000000..2efb124 + } + spin_unlock(&service_spinlock); + ++ if (service && service->userdata_term) ++ service->userdata_term(service->base.userdata); ++ + kfree(service); +} + @@ -75611,6 +76407,7 @@ index 0000000..2efb124 + version, version_min); + vchiq_loud_error_footer(); + unlock_service(service); ++ service = NULL; + goto fail_open; + } + service->peer_version = version; @@ -75676,7 +76473,8 @@ index 0000000..2efb124 + return 1; + +bail_not_ready: -+ unlock_service(service); ++ if (service) ++ unlock_service(service); + + return 0; +} @@ -76598,7 +77396,7 @@ index 0000000..2efb124 +VCHIQ_SERVICE_T * +vchiq_add_service_internal(VCHIQ_STATE_T *state, + const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, -+ VCHIQ_INSTANCE_T instance) ++ VCHIQ_INSTANCE_T instance, VCHIQ_USERDATA_TERM_T userdata_term) +{ + VCHIQ_SERVICE_T *service; + @@ -76610,6 +77408,7 @@ index 0000000..2efb124 + service->handle = VCHIQ_SERVICE_HANDLE_INVALID; + service->ref_count = 1; + service->srvstate = VCHIQ_SRVSTATE_FREE; ++ service->userdata_term = userdata_term; + service->localport = VCHIQ_PORT_FREE; + service->remoteport = VCHIQ_PORT_FREE; + @@ -77940,10 +78739,10 @@ index 0000000..2efb124 +} diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h new file mode 100644 -index 0000000..bddfc6a +index 0000000..47cdf27 --- /dev/null +++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h -@@ -0,0 +1,703 @@ +@@ -0,0 +1,706 @@ +/** + * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * @@ -78183,6 +78982,8 @@ index 0000000..bddfc6a + VCHIQ_BULK_RECEIVE +} VCHIQ_BULK_DIR_T; + ++typedef void (*VCHIQ_USERDATA_TERM_T)(void *userdata); ++ +typedef struct vchiq_bulk_struct { + short mode; + short dir; @@ -78230,6 +79031,7 @@ index 0000000..bddfc6a + VCHIQ_SERVICE_HANDLE_T handle; + unsigned int ref_count; + int srvstate; ++ VCHIQ_USERDATA_TERM_T userdata_term; + unsigned int localport; + unsigned int remoteport; + int public_fourcc; @@ -78480,7 +79282,7 @@ index 0000000..bddfc6a +extern VCHIQ_SERVICE_T * +vchiq_add_service_internal(VCHIQ_STATE_T *state, + const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, -+ VCHIQ_INSTANCE_T instance); ++ VCHIQ_INSTANCE_T instance, VCHIQ_USERDATA_TERM_T userdata_term); + +extern VCHIQ_STATUS_T +vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id); @@ -79071,10 +79873,10 @@ index 0000000..e248037 +#endif diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c new file mode 100644 -index 0000000..62965c6 +index 0000000..be9735f --- /dev/null +++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c -@@ -0,0 +1,454 @@ +@@ -0,0 +1,456 @@ +/** + * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * @@ -79318,7 +80120,8 @@ index 0000000..62965c6 + state, + params, + srvstate, -+ instance); ++ instance, ++ NULL); + + if (service) { + *phandle = service->handle; @@ -79359,7 +80162,8 @@ index 0000000..62965c6 + service = vchiq_add_service_internal(state, + params, + VCHIQ_SRVSTATE_OPENING, -+ instance); ++ instance, ++ NULL); + + if (service) { + status = vchiq_open_service_internal(service, current->pid); @@ -80752,10 +81556,10 @@ index 0000000..f752f8d +EXPORT_SYMBOL(vchi_service_release); diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c new file mode 100644 -index 0000000..03cece571b +index 0000000..c2eefef --- /dev/null +++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c -@@ -0,0 +1,120 @@ +@@ -0,0 +1,151 @@ +/** + * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * @@ -80839,8 +81643,20 @@ index 0000000..03cece571b + } + } + ++ /* ++ * Write to queue->storage must be visible after read from ++ * queue->read ++ */ ++ smp_mb(); ++ + queue->storage[queue->write & (queue->size - 1)] = header; + ++ /* ++ * Write to queue->storage must be visible before write to ++ * queue->write ++ */ ++ smp_wmb(); ++ + queue->write++; + + up(&queue->push); @@ -80855,6 +81671,13 @@ index 0000000..03cece571b + } + + up(&queue->push); // We haven't removed anything from the queue. ++ ++ /* ++ * Read from queue->storage must be visible after read from ++ * queue->write ++ */ ++ smp_rmb(); ++ + return queue->storage[queue->read & (queue->size - 1)]; +} + @@ -80868,8 +81691,20 @@ index 0000000..03cece571b + } + } + ++ /* ++ * Read from queue->storage must be visible after read from ++ * queue->write ++ */ ++ smp_rmb(); ++ + header = queue->storage[queue->read & (queue->size - 1)]; + ++ /* ++ * Read from queue->storage must be visible before write to ++ * queue->read ++ */ ++ smp_mb(); ++ + queue->read++; + + up(&queue->pop); @@ -81032,10 +81867,10 @@ index 0000000..b6bfa21 1.8.4 -From 4e3eba9df31db6cbdf4f1b73522e049f4e49b8dc Mon Sep 17 00:00:00 2001 +From 03dde57ea271342aa5012a643263b43ea95c89eb Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:31:47 +0100 -Subject: [PATCH 07/98] cma: Add vc_cma driver to enable use of CMA +Subject: [PATCH 07/82] cma: Add vc_cma driver to enable use of CMA Signed-off-by: popcornmix --- @@ -81079,7 +81914,7 @@ index 7ff1d0d..fc85f0c 100644 +obj-$(CONFIG_BRCM_CHAR_DRIVERS) += broadcom/ diff --git a/drivers/char/broadcom/Kconfig b/drivers/char/broadcom/Kconfig new file mode 100644 -index 0000000..ae3e8b2 +index 0000000..e23b440 --- /dev/null +++ b/drivers/char/broadcom/Kconfig @@ -0,0 +1,16 @@ @@ -81088,17 +81923,17 @@ index 0000000..ae3e8b2 +# + +menuconfig BRCM_CHAR_DRIVERS -+ tristate "Broadcom Char Drivers" -+ depends on PROC_FS ++ bool "Broadcom Char Drivers" + help + Broadcom's char drivers + +config BCM_VC_CMA + bool "Videocore CMA" -+ depends on CMA ++ depends on CMA && BRCM_CHAR_DRIVERS + default n + help + Helper for videocore CMA access. ++ diff --git a/drivers/char/broadcom/Makefile b/drivers/char/broadcom/Makefile new file mode 100644 index 0000000..13c5bca @@ -81128,7 +81963,7 @@ index 0000000..c6fcc37 +vc-cma-objs := vc_cma.o diff --git a/drivers/char/broadcom/vc_cma/vc_cma.c b/drivers/char/broadcom/vc_cma/vc_cma.c new file mode 100644 -index 0000000..0f12701 +index 0000000..a635f9f --- /dev/null +++ b/drivers/char/broadcom/vc_cma/vc_cma.c @@ -0,0 +1,1143 @@ @@ -81683,7 +82518,7 @@ index 0000000..0f12701 + __func__, (unsigned int)page_to_phys(chunk), + vc_cma_base, vc_cma_base + vc_cma_size - 1); + LOG_ERR("%s: dev->cma_area = %p\n", __func__, -+ vc_cma_device.dev.cma_area); ++ (void*)0/*vc_cma_device.dev.cma_area*/); + LOG_ERR("%s: ===============================", + __func__); + break; @@ -82324,10 +83159,10 @@ index 0000000..5325832 1.8.4 -From 7e01591dc9904bd0e34e50a4ba6d0dc573029f46 Mon Sep 17 00:00:00 2001 +From bf751558ab1a40b021d5900966659bfa16ecb335 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 26 Mar 2012 22:15:50 +0100 -Subject: [PATCH 08/98] bcm2708: alsa sound driver +Subject: [PATCH 08/82] bcm2708: alsa sound driver Signed-off-by: popcornmix --- @@ -82413,10 +83248,10 @@ index 339aabf..df947e5 100644 CONFIG_USB_HIDDEV=y CONFIG_HID_A4TECH=m diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index e6459b3..a724746 100644 +index f3d14b0..e6add5f 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -423,6 +423,16 @@ struct platform_device bcm2708_powerman_device = { +@@ -429,6 +429,16 @@ struct platform_device bcm2708_powerman_device = { .coherent_dma_mask = 0xffffffffUL}, }; @@ -82433,7 +83268,7 @@ index e6459b3..a724746 100644 int __init bcm_register_device(struct platform_device *pdev) { int ret; -@@ -474,6 +484,8 @@ void __init bcm2708_init(void) +@@ -537,6 +547,8 @@ void __init bcm2708_init(void) bcm_register_device(&bcm2708_emmc_device); #endif bcm2708_init_led(); @@ -84649,10 +85484,10 @@ index 0000000..af3e6eb 1.8.4 -From 204ed24fe32df5f09c9e167a7505d36ad2d1f5b5 Mon Sep 17 00:00:00 2001 +From 52911e377567e105431b80ea1167df8f58de065d Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 26 Mar 2013 17:26:38 +0000 -Subject: [PATCH 09/98] Allow mac address to be set in smsc95xx +Subject: [PATCH 09/82] Allow mac address to be set in smsc95xx Signed-off-by: popcornmix --- @@ -84746,10 +85581,10 @@ index 3f38ba8..60076fe 100644 1.8.4 -From 66f3f3a3efb6eaf5163d0eebacc64ee9455b9957 Mon Sep 17 00:00:00 2001 +From afd4b59ba5e3bf9118bf9ea07282707d89d80ba5 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 8 May 2012 23:12:13 +0100 -Subject: [PATCH 10/98] possible fix for sdcard missing status. Thank naren +Subject: [PATCH 10/82] possible fix for sdcard missing status. Thank naren --- drivers/mmc/host/sdhci-bcm2708.c | 9 +++++++++ @@ -84786,10 +85621,10 @@ index d8ef77c..0514bc1 100644 1.8.4 -From 11eb3c7d0ba87243d8ca88091b31826f0f56cf0c Mon Sep 17 00:00:00 2001 +From addaed5ebe3d27dedfd0cb666e7098eaf58f5612 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Thu, 17 May 2012 14:44:19 +0100 -Subject: [PATCH 11/98] sdcard patch improvements from naren +Subject: [PATCH 11/82] sdcard patch improvements from naren --- drivers/mmc/host/sdhci-bcm2708.c | 23 +++++++---------------- @@ -84848,10 +85683,10 @@ index 0514bc1..7ba715b 100644 1.8.4 -From 6052e4aaa113d5d1286fe38a4db003ea5aea8c25 Mon Sep 17 00:00:00 2001 +From 0f1bf0d00853b2f4ea69ee0881fc469040b822df Mon Sep 17 00:00:00 2001 From: Grigori Goronzy Date: Mon, 4 Jun 2012 04:27:48 +0200 -Subject: [PATCH 12/98] sdhci-bcm2708: speed up DMA sync +Subject: [PATCH 12/82] sdhci-bcm2708: speed up DMA sync Experiments show that it doesn't really take that long to sync, so we can reduce the poll interval slightly. Might improve performance a bit. @@ -84876,10 +85711,10 @@ index 7ba715b..fe656c0 100644 1.8.4 -From 0581204b7cf5a2a75903b8fd31236ebb0ac88e1f Mon Sep 17 00:00:00 2001 +From e8e2859ee337d238629739097a4a97ddb218bac6 Mon Sep 17 00:00:00 2001 From: Grigori Goronzy Date: Mon, 11 Jun 2012 18:52:04 +0200 -Subject: [PATCH 13/98] sdhci-bcm2708: remove custom clock handling +Subject: [PATCH 13/82] sdhci-bcm2708: remove custom clock handling The custom clock handling code is redundant and buggy. The MMC/SDHCI subsystem does a better job than it, so remove it for good. @@ -84977,10 +85812,10 @@ index fe656c0..18be90c 100644 1.8.4 -From e81244421acc9539f75e57fa6e62fe63453f6412 Mon Sep 17 00:00:00 2001 +From abca27f964c3c0dcb8480f46ba6c380de4fd1a96 Mon Sep 17 00:00:00 2001 From: Grigori Goronzy Date: Mon, 11 Jun 2012 18:53:59 +0200 -Subject: [PATCH 14/98] sdhci-bcm2708: add additional quirks +Subject: [PATCH 14/82] sdhci-bcm2708: add additional quirks Some additional quirks are needed for correct operation. There's no SDHCI capabilities register documented, and it always reads @@ -85010,10 +85845,10 @@ index 18be90c..1be1785 100644 1.8.4 -From 08764b41dfc0c1262d1e05fd74ad98c88c3eccce Mon Sep 17 00:00:00 2001 +From e0615f329b8b249540b36c12e41eadf9fd53b666 Mon Sep 17 00:00:00 2001 From: Grigori Goronzy Date: Mon, 11 Jun 2012 18:57:13 +0200 -Subject: [PATCH 15/98] sdhci-bcm2708: add allow_highspeed parameter +Subject: [PATCH 15/82] sdhci-bcm2708: add allow_highspeed parameter Add a parameter to disable high-speed mode for the few cards that still might have problems. High-speed mode is enabled by default. @@ -85060,10 +85895,10 @@ index 1be1785..9a6d195 100644 1.8.4 -From be20d05fa501b6032876d642a4706c7226770274 Mon Sep 17 00:00:00 2001 +From 26f6920b48fd609c051ed4aa89a74530a1295d56 Mon Sep 17 00:00:00 2001 From: Grigori Goronzy Date: Mon, 11 Jun 2012 18:58:40 +0200 -Subject: [PATCH 16/98] sdhci-bcm2708: assume 50 MHz eMMC clock +Subject: [PATCH 16/82] sdhci-bcm2708: assume 50 MHz eMMC clock 80 MHz clock isnt't suited well to be dividable to get SD clocks of 25 MHz (default mode) or 50 MHz (high speed mode). 50 MHz are perfect to @@ -85089,10 +85924,10 @@ index 9a6d195..8747f5f 100644 1.8.4 -From 60b82402606de8c2aac9ae2ed5bdc12285f9bb88 Mon Sep 17 00:00:00 2001 +From 28aaf7acfa3191852fd6d20629597187bf647e8d Mon Sep 17 00:00:00 2001 From: popcornmix Date: Sat, 16 Jun 2012 22:31:55 +0100 -Subject: [PATCH 17/98] Allow emmc clock to be specified as command line +Subject: [PATCH 17/82] Allow emmc clock to be specified as command line parameter --- @@ -85138,10 +85973,10 @@ index 8747f5f..fe889d3 100644 1.8.4 -From 3c063db0757e7355e4da3b7ba8202d74b28a6fef Mon Sep 17 00:00:00 2001 +From c22f6a2e0ae13c1b37b084784e7383ac650b9b23 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Sat, 16 Jun 2012 22:35:38 +0100 -Subject: [PATCH 18/98] sdhci-bcm2708: raise DMA sync timeout +Subject: [PATCH 18/82] sdhci-bcm2708: raise DMA sync timeout Commit d64b84c by accident reduced the maximum overall DMA sync timeout. The maximum overall timeout was reduced from 100ms to 30ms, @@ -85171,10 +86006,10 @@ index fe889d3..16c8df1 100644 1.8.4 -From dbd0fbe268d2fc99bcabbe98056c34eecae3383a Mon Sep 17 00:00:00 2001 +From b410c7b3c6cb2a52b59432ec7167c6b48ef81e9f Mon Sep 17 00:00:00 2001 From: popcornmix Date: Fri, 22 Jun 2012 12:57:42 +0100 -Subject: [PATCH 19/98] Use ndelay rather than udelay. Thanks lb +Subject: [PATCH 19/82] Use ndelay rather than udelay. Thanks lb --- drivers/mmc/host/sdhci-bcm2708.c | 8 ++++---- @@ -85221,23 +86056,24 @@ index 16c8df1..0eb48c9 100644 1.8.4 -From 528074d07c49c257952d736c2d40c64466ad8fe1 Mon Sep 17 00:00:00 2001 +From 518b44c7249830efcb5e2248dc243bff2fc42b09 Mon Sep 17 00:00:00 2001 From: popcornmix -Date: Wed, 3 Jul 2013 00:41:10 +0100 -Subject: [PATCH 20/98] Backport of Chris Boot's i2c and spi drivers. +Date: Mon, 4 Nov 2013 18:56:10 +0000 +Subject: [PATCH 20/82] Add Chris Boot's i2c and spi drivers. --- arch/arm/configs/bcmrpi_cutdown_defconfig | 9 + - arch/arm/configs/bcmrpi_defconfig | 5 + - arch/arm/mach-bcm2708/bcm2708.c | 100 ++++- + arch/arm/configs/bcmrpi_defconfig | 6 + + arch/arm/mach-bcm2708/Kconfig | 7 + + arch/arm/mach-bcm2708/bcm2708.c | 104 ++++- arch/arm/mach-bcm2708/include/mach/platform.h | 3 + - drivers/i2c/busses/Kconfig | 8 + + drivers/i2c/busses/Kconfig | 19 + drivers/i2c/busses/Makefile | 1 + - drivers/i2c/busses/i2c-bcm2708.c | 396 +++++++++++++++++ + drivers/i2c/busses/i2c-bcm2708.c | 408 +++++++++++++++++ drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + - drivers/spi/spi-bcm2708.c | 594 ++++++++++++++++++++++++++ - 10 files changed, 1123 insertions(+), 2 deletions(-) + drivers/spi/spi-bcm2708.c | 626 ++++++++++++++++++++++++++ + 11 files changed, 1190 insertions(+), 2 deletions(-) create mode 100644 drivers/i2c/busses/i2c-bcm2708.c create mode 100644 drivers/spi/spi-bcm2708.c @@ -85259,10 +86095,10 @@ index e519412..2c2e29e 100644 +CONFIG_SPI_MASTER=y +CONFIG_SPI_BCM2708=m diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index df947e5..6219df3 100644 +index df947e5..31f5afaa 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -214,6 +214,11 @@ CONFIG_SERIAL_AMBA_PL011=y +@@ -214,6 +214,12 @@ CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_RAW_DRIVER=y @@ -85271,11 +86107,28 @@ index df947e5..6219df3 100644 +CONFIG_I2C_BCM2708=m +CONFIG_SPI=y +CONFIG_SPI_BCM2708=m ++CONFIG_SPI_SPIDEV=m CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y +diff --git a/arch/arm/mach-bcm2708/Kconfig b/arch/arm/mach-bcm2708/Kconfig +index 9355841..e151ed4 100644 +--- a/arch/arm/mach-bcm2708/Kconfig ++++ b/arch/arm/mach-bcm2708/Kconfig +@@ -31,4 +31,11 @@ config BCM2708_NOL2CACHE + help + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt. + ++config BCM2708_SPIDEV ++ bool "Bind spidev to SPI0 master" ++ depends on MACH_BCM2708 ++ depends on SPI ++ default y ++ help ++ Binds spidev driver to the SPI0 master + endmenu diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index a724746..141ed61 100644 +index e6add5f..dfcc605 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c @@ -31,6 +31,7 @@ @@ -85286,7 +86139,7 @@ index a724746..141ed61 100644 #include #include -@@ -197,7 +198,6 @@ static void __init bcm2708_clocksource_init(void) +@@ -203,7 +204,6 @@ static void __init bcm2708_clocksource_init(void) /* warning - the USB needs a clock > 34MHz */ @@ -85294,7 +86147,7 @@ index a724746..141ed61 100644 static struct clk sdhost_clk = { #ifdef CONFIG_ARCH_BCM2708_CHIPIT .rate = 4000000, /* 4MHz */ -@@ -205,7 +205,6 @@ static void __init bcm2708_clocksource_init(void) +@@ -211,7 +211,6 @@ static void __init bcm2708_clocksource_init(void) .rate = 250000000, /* 250MHz */ #endif }; @@ -85302,7 +86155,7 @@ index a724746..141ed61 100644 static struct clk_lookup lookups[] = { { /* UART0 */ -@@ -215,6 +214,15 @@ static void __init bcm2708_clocksource_init(void) +@@ -221,6 +220,15 @@ static void __init bcm2708_clocksource_init(void) { /* USB */ .dev_id = "bcm2708_usb", .clk = &osc_clk, @@ -85318,7 +86171,7 @@ index a724746..141ed61 100644 } }; -@@ -433,6 +441,85 @@ struct platform_device bcm2708_powerman_device = { +@@ -439,6 +447,89 @@ struct platform_device bcm2708_powerman_device = { }, }; @@ -85335,14 +86188,18 @@ index a724746..141ed61 100644 +}; + + ++static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); +static struct platform_device bcm2708_spi_device = { + .name = "bcm2708_spi", + .id = 0, + .num_resources = ARRAY_SIZE(bcm2708_spi_resources), + .resource = bcm2708_spi_resources, ++ .dev = { ++ .dma_mask = &bcm2708_spi_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)}, +}; + -+#ifdef CONFIG_SPI ++#ifdef CONFIG_BCM2708_SPIDEV +static struct spi_board_info bcm2708_spi_devices[] = { +#ifdef CONFIG_SPI_SPIDEV + { @@ -85404,7 +86261,7 @@ index a724746..141ed61 100644 int __init bcm_register_device(struct platform_device *pdev) { int ret; -@@ -487,12 +574,21 @@ void __init bcm2708_init(void) +@@ -550,12 +641,21 @@ void __init bcm2708_init(void) for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) bcm_register_device(&bcm2708_alsa_devices[i]); @@ -85419,7 +86276,7 @@ index a724746..141ed61 100644 system_rev = boardrev; system_serial_low = serial; + -+#ifdef CONFIG_SPI ++#ifdef CONFIG_BCM2708_SPIDEV + spi_register_board_info(bcm2708_spi_devices, + ARRAY_SIZE(bcm2708_spi_devices)); +#endif @@ -85444,10 +86301,10 @@ index 110ce07..4d3c15d 100644 #define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/ diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig -index dc6dea6..74b03eb 100644 +index cdcbd83..5a4144c 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig -@@ -345,6 +345,14 @@ config I2C_BCM2835 +@@ -345,6 +345,25 @@ config I2C_BCM2835 This support is also available as a module. If so, the module will be called i2c-bcm2835. @@ -85458,6 +86315,17 @@ index dc6dea6..74b03eb 100644 + Enabling this option will add BSC (Broadcom Serial Controller) + support for the BCM2708. BSC is a Broadcom proprietary bus compatible + with I2C/TWI/SMBus. ++ ++config I2C_BCM2708_BAUDRATE ++ prompt "BCM2708 I2C baudrate" ++ depends on I2C_BCM2708 ++ int ++ default 100000 ++ help ++ Set the I2C baudrate. This will alter the default value. A ++ different baudrate can be set by using a module parameter as well. If ++ no parameter is provided when loading, this is the value that will be ++ used. + config I2C_BLACKFIN_TWI tristate "Blackfin TWI I2C support" @@ -85476,10 +86344,10 @@ index d00997f..15622cd 100644 obj-$(CONFIG_I2C_CPM) += i2c-cpm.o diff --git a/drivers/i2c/busses/i2c-bcm2708.c b/drivers/i2c/busses/i2c-bcm2708.c new file mode 100644 -index 0000000..4d451a4 +index 0000000..72750c7 --- /dev/null +++ b/drivers/i2c/busses/i2c-bcm2708.c -@@ -0,0 +1,396 @@ +@@ -0,0 +1,408 @@ +/* + * Driver for Broadcom BCM2708 BSC Controllers + * @@ -85548,11 +86416,15 @@ index 0000000..4d451a4 +#define BSC_S_DONE 0x00000002 +#define BSC_S_TA 0x00000001 + -+#define I2C_CLOCK_HZ 100000 /* FIXME: get from DT */ +#define I2C_TIMEOUT_MS 150 + +#define DRV_NAME "bcm2708_i2c" + ++static unsigned int baudrate = CONFIG_I2C_BCM2708_BAUDRATE; ++module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP); ++MODULE_PARM_DESC(baudrate, "The I2C baudrate"); ++ ++ +struct bcm2708_i2c { + struct i2c_adapter adapter; + @@ -85575,7 +86447,7 @@ index 0000000..4d451a4 + * + * FIXME: This is a hack. Use pinmux / pinctrl. + */ -+static void bcm2708_i2c_init_pinmode(void) ++static void bcm2708_i2c_init_pinmode(int id) +{ +#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3)) +#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) @@ -85583,8 +86455,10 @@ index 0000000..4d451a4 + int pin; + u32 *gpio = ioremap(0x20200000, SZ_16K); + ++ BUG_ON(id != 0 && id != 1); + /* BSC0 is on GPIO 0 & 1, BSC1 is on GPIO 2 & 3 */ -+ for (pin = 0; pin <= 3; pin++) { ++ for (pin = id*2+0; pin <= id*2+1; pin++) { ++printk("bcm2708_i2c_init_pinmode(%d,%d)\n", id, pin); + INP_GPIO(pin); /* set mode to GPIO input first */ + SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */ + } @@ -85630,7 +86504,7 @@ index 0000000..4d451a4 + u32 c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_ST | BSC_C_CLEAR_1; + + bus_hz = clk_get_rate(bi->clk); -+ cdiv = bus_hz / I2C_CLOCK_HZ; ++ cdiv = bus_hz / baudrate; + + if (bi->msg->flags & I2C_M_RD) + c |= BSC_C_INTR | BSC_C_READ; @@ -85651,6 +86525,11 @@ index 0000000..4d451a4 + + spin_lock(&bi->lock); + ++ /* we may see camera interrupts on the "other" I2C channel ++ Just return if we've not sent anything */ ++ if (!bi->nmsgs || !bi->msg ) ++ goto early_exit; ++ + s = bcm2708_rd(bi, BSC_S); + + if (s & (BSC_S_CLKT | BSC_S_ERR)) { @@ -85684,6 +86563,7 @@ index 0000000..4d451a4 + handled = false; + } + ++early_exit: + spin_unlock(&bi->lock); + + return handled ? IRQ_HANDLED : IRQ_NONE; @@ -85757,7 +86637,7 @@ index 0000000..4d451a4 + return PTR_ERR(clk); + } + -+ bcm2708_i2c_init_pinmode(); ++ bcm2708_i2c_init_pinmode(pdev->id); + + bi = kzalloc(sizeof(*bi), GFP_KERNEL); + if (!bi) @@ -85813,8 +86693,8 @@ index 0000000..4d451a4 + goto out_free_irq; + } + -+ dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d)\n", -+ pdev->id, (unsigned long)regs->start, irq); ++ dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d) (baudrate %dk)\n", ++ pdev->id, (unsigned long)regs->start, irq, baudrate/1000); + + return 0; + @@ -85877,10 +86757,10 @@ index 0000000..4d451a4 +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig -index 89cbbab..193df09 100644 +index b9c53cc..41ad35a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig -@@ -86,6 +86,14 @@ config SPI_BCM2835 +@@ -85,6 +85,14 @@ config SPI_BCM2835 is for the regular SPI controller. Slave mode operation is not also not supported. @@ -85894,25 +86774,25 @@ index 89cbbab..193df09 100644 + config SPI_BFIN5XX tristate "SPI controller driver for ADI Blackfin5xx" - depends on BLACKFIN + depends on BLACKFIN && !BF60x diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile -index 33f9c09..17b4737 100644 +index ab8d864..a011073 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_SPI_AU1550) += spi-au1550.o - obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o +@@ -18,6 +18,7 @@ obj-$(CONFIG_SPI_BCM2835) += spi-bcm2835.o obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o + obj-$(CONFIG_SPI_BFIN_V3) += spi-bfin-v3.o +obj-$(CONFIG_SPI_BCM2708) += spi-bcm2708.o obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o diff --git a/drivers/spi/spi-bcm2708.c b/drivers/spi/spi-bcm2708.c new file mode 100644 -index 0000000..9f1580e +index 0000000..abaa5a6 --- /dev/null +++ b/drivers/spi/spi-bcm2708.c -@@ -0,0 +1,594 @@ +@@ -0,0 +1,626 @@ +/* + * Driver for Broadcom BCM2708 SPI Controllers + * @@ -86061,10 +86941,31 @@ index 0000000..9f1580e +static inline void bcm2708_wr_fifo(struct bcm2708_spi *bs, int len) +{ + u8 byte; ++ u16 val; + + if (len > bs->len) + len = bs->len; + ++ if (unlikely(bcm2708_rd(bs, SPI_CS) & SPI_CS_LEN)) { ++ /* LoSSI mode */ ++ if (unlikely(len % 2)) { ++ printk(KERN_ERR"bcm2708_wr_fifo: length must be even, skipping.\n"); ++ bs->len = 0; ++ return; ++ } ++ while (len) { ++ if (bs->tx_buf) { ++ val = *(const u16 *)bs->tx_buf; ++ bs->tx_buf += 2; ++ } else ++ val = 0; ++ bcm2708_wr(bs, SPI_FIFO, val); ++ bs->len -= 2; ++ len -= 2; ++ } ++ return; ++ } ++ + while (len--) { + byte = bs->tx_buf ? *bs->tx_buf++ : 0; + bcm2708_wr(bs, SPI_FIFO, byte); @@ -86149,8 +87050,12 @@ index 0000000..9f1580e + switch (bpw) { + case 8: + break; ++ case 9: ++ /* Reading in LoSSI mode is a special case. See 'BCM2835 ARM Peripherals' datasheet */ ++ cs |= SPI_CS_LEN; ++ break; + default: -+ dev_dbg(dev, "setup: invalid bits_per_word %u (must be 8)\n", ++ dev_dbg(dev, "setup: invalid bits_per_word %u (must be 8 or 9)\n", + bpw); + return -EINVAL; + } @@ -86174,6 +87079,10 @@ index 0000000..9f1580e + if (state) { + state->cs = cs; + state->cdiv = cdiv; ++ dev_dbg(dev, "setup: want %d Hz; " ++ "bus_hz=%lu / cdiv=%u == %lu Hz; " ++ "mode %u: cs 0x%08X\n", ++ hz, bus_hz, cdiv, bus_hz/cdiv, mode, cs); + } + + return 0; @@ -86192,8 +87101,10 @@ index 0000000..9f1580e + + if (xfer->bits_per_word || xfer->speed_hz) { + ret = bcm2708_setup_state(spi->master, &spi->dev, &state, -+ spi->max_speed_hz, spi->chip_select, spi->mode, -+ spi->bits_per_word); ++ xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz, ++ spi->chip_select, spi->mode, ++ xfer->bits_per_word ? xfer->bits_per_word : ++ spi->bits_per_word); + if (ret) + return ret; + @@ -86293,6 +87204,7 @@ index 0000000..9f1580e + if (ret < 0) { + kfree(state); + spi->controller_state = NULL; ++ return ret; + } + + dev_dbg(&spi->dev, @@ -86511,35 +87423,10 @@ index 0000000..9f1580e 1.8.4 -From b2c6380fa9041f817b8dd797c7c0ff330d6616ed Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Thu, 19 Jul 2012 16:00:28 +0100 -Subject: [PATCH 21/98] Add SPI_SPI_DEV module - ---- - arch/arm/configs/bcmrpi_defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 6219df3..31f5afaa 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -219,6 +219,7 @@ CONFIG_I2C_CHARDEV=m - CONFIG_I2C_BCM2708=m - CONFIG_SPI=y - CONFIG_SPI_BCM2708=m -+CONFIG_SPI_SPIDEV=m - CONFIG_GPIO_SYSFS=y - # CONFIG_HWMON is not set - CONFIG_WATCHDOG=y --- -1.8.4 - - -From 67252012c6724325feab17f97de836d47260d9a7 Mon Sep 17 00:00:00 2001 +From cfa0f75fac23a1595b4bcee2ebda393687d3cb64 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 17 Jul 2012 00:48:27 +0100 -Subject: [PATCH 22/98] Add sync_after_dma module parameter +Subject: [PATCH 21/82] Add sync_after_dma module parameter --- drivers/mmc/host/sdhci-bcm2708.c | 61 ++++++++++++++++++++++------------------ @@ -86656,10 +87543,10 @@ index 0eb48c9..984f2cf 100644 1.8.4 -From 6ad5654dd590e8525952a7a12cb8a0aa9430ee0e Mon Sep 17 00:00:00 2001 +From 8dbbed73f54c90394b7d1459cc067b8428f629be Mon Sep 17 00:00:00 2001 From: popcornmix Date: Sun, 12 May 2013 12:25:52 +0100 -Subject: [PATCH 23/98] sdhci-bcm2708: use extension FIFO to buffer DMA +Subject: [PATCH 22/82] sdhci-bcm2708: use extension FIFO to buffer DMA transfers The additional FIFO might speed up transfers in some cases. @@ -86711,10 +87598,10 @@ index 984f2cf..9c3f304 100644 1.8.4 -From 3cc0111ad1079692aedc8422c1f19d4109ea3b49 Mon Sep 17 00:00:00 2001 +From dc1889a5c6b2eda3a4b2425b3e7d0896a91e5b2f Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:42:49 +0100 -Subject: [PATCH 24/98] sdhci-bcm2708: use multiblock-type transfers for single +Subject: [PATCH 23/82] sdhci-bcm2708: use multiblock-type transfers for single blocks There are issues with both single block reads (missed completion) @@ -86728,10 +87615,10 @@ adds a quirk for this and uses it. 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c -index cd0b7f4..ed79223 100644 +index 1a3163f..b39f38b 100644 --- a/drivers/mmc/card/block.c +++ b/drivers/mmc/card/block.c -@@ -1322,7 +1322,7 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq, +@@ -1361,7 +1361,7 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq, brq->data.blocks = 1; } @@ -86770,10 +87657,10 @@ index 3b0c33a..e9ae33c 100644 1.8.4 -From d2a1f75842dfaa7ec20a8e5888c16f33fb62f814 Mon Sep 17 00:00:00 2001 +From 018fa7cb0987a0a51edac7697d4340b44b55c41e Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 1 Aug 2012 19:02:14 +0100 -Subject: [PATCH 25/98] Add module parameter for missing_status quirk. +Subject: [PATCH 24/82] Add module parameter for missing_status quirk. sdhci-bcm2708.missing_status=0 may improve interrupt latency --- @@ -86829,10 +87716,10 @@ index 7600c58..4dfa669 100644 1.8.4 -From 21c52ee182f4201b219cec12644fdba60e6dc1f1 Mon Sep 17 00:00:00 2001 +From 123e90f8ef43a524a8c411d03b5ce53e927842ad Mon Sep 17 00:00:00 2001 From: ddv2005 Date: Sun, 5 Aug 2012 10:42:12 -0400 -Subject: [PATCH 26/98] Fix spinlock recursion in sdhci-bcm2708.c +Subject: [PATCH 25/82] Fix spinlock recursion in sdhci-bcm2708.c --- drivers/mmc/host/sdhci-bcm2708.c | 14 +++++++------- @@ -86901,10 +87788,10 @@ index 4dfa669..dc94b55 100644 1.8.4 -From 67e5ecd17ad6eb1f57c3bad4ffcbb8ff0895edf2 Mon Sep 17 00:00:00 2001 +From ff26575b25f1e4a32036ba70a458c3efcc6ab5ab Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 8 May 2013 11:46:50 +0100 -Subject: [PATCH 27/98] enabling the realtime clock 1-wire chip DS1307 and +Subject: [PATCH 26/82] enabling the realtime clock 1-wire chip DS1307 and 1-wire on GPIO4 (as a module) --- @@ -86912,7 +87799,7 @@ Subject: [PATCH 27/98] enabling the realtime clock 1-wire chip DS1307 and 1 file changed, 20 insertions(+) diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 141ed61..402bfe7 100644 +index dfcc605..5f869e8 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c @@ -32,6 +32,7 @@ @@ -86923,7 +87810,7 @@ index 141ed61..402bfe7 100644 #include #include -@@ -71,6 +72,9 @@ +@@ -76,6 +77,9 @@ */ #define DMA_MASK_BITS_COMMON 32 @@ -86933,7 +87820,7 @@ index 141ed61..402bfe7 100644 /* command line parameters */ static unsigned boardrev, serial; static unsigned uart_clock; -@@ -250,6 +254,19 @@ static void __init bcm2708_clocksource_init(void) +@@ -256,6 +260,19 @@ static void __init bcm2708_clocksource_init(void) .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources), }; @@ -86953,7 +87840,7 @@ index 141ed61..402bfe7 100644 static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); static struct platform_device bcm2708_fb_device = { -@@ -561,6 +578,9 @@ void __init bcm2708_init(void) +@@ -628,6 +645,9 @@ void __init bcm2708_init(void) #ifdef CONFIG_BCM2708_GPIO bcm_register_device(&bcm2708_gpio_device); #endif @@ -86967,21 +87854,21 @@ index 141ed61..402bfe7 100644 1.8.4 -From c8cf7e1fb4669532bfad1daa3c25dce85ca7ff12 Mon Sep 17 00:00:00 2001 +From 8b21a09d9e687d42173731835ea36e7a1411649e Mon Sep 17 00:00:00 2001 From: popcornmix Date: Sun, 12 May 2013 12:27:48 +0100 -Subject: [PATCH 28/98] Add low-latency mode to sdcard driver. Disable with +Subject: [PATCH 27/82] Add low-latency mode to sdcard driver. Disable with sdhci-bcm2708.enable_llm=0. Thanks ddv2005. --- - drivers/mmc/host/sdhci-bcm2708.c | 17 ++-- - drivers/mmc/host/sdhci.c | 165 ++++++++++++++++++++++++++++++--------- + drivers/mmc/host/sdhci-bcm2708.c | 15 ++-- + drivers/mmc/host/sdhci.c | 169 ++++++++++++++++++++++++++++++--------- drivers/mmc/host/sdhci.h | 6 ++ include/linux/mmc/sdhci.h | 1 + - 4 files changed, 145 insertions(+), 44 deletions(-) + 4 files changed, 146 insertions(+), 45 deletions(-) diff --git a/drivers/mmc/host/sdhci-bcm2708.c b/drivers/mmc/host/sdhci-bcm2708.c -index dc94b55..6263977 100644 +index dc94b55..6dacdb3 100644 --- a/drivers/mmc/host/sdhci-bcm2708.c +++ b/drivers/mmc/host/sdhci-bcm2708.c @@ -135,6 +135,7 @@ static inline unsigned long int since_ns(hptime_t t) @@ -87029,14 +87916,12 @@ index dc94b55..6263977 100644 host->quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | -@@ -1256,12 +1258,13 @@ static int sdhci_bcm2708_probe(struct platform_device *pdev) - } +@@ -1257,11 +1259,12 @@ static int sdhci_bcm2708_probe(struct platform_device *pdev) host_priv->dma_chan = ret; -- ret = request_irq(host_priv->dma_irq, sdhci_bcm2708_dma_irq, + ret = request_irq(host_priv->dma_irq, sdhci_bcm2708_dma_irq, - IRQF_SHARED, DRIVER_NAME " (dma)", host); -+ ret = request_irq(host_priv->dma_irq, sdhci_bcm2708_dma_irq,0,//IRQF_SHARED, -+ DRIVER_NAME " (dma)", host); ++ 0 /*IRQF_SHARED*/, DRIVER_NAME " (dma)", host); if (ret) { dev_err(&pdev->dev, "cannot set DMA IRQ\n"); goto err_add_dma_irq; @@ -87061,7 +87946,7 @@ index dc94b55..6263977 100644 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c -index 763dbf9..2c47d16 100644 +index 4b250ea..48b12ac 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -132,6 +132,91 @@ static void sdhci_dumpregs(struct sdhci_host *host) @@ -87386,6 +88271,15 @@ index 763dbf9..2c47d16 100644 if (unexpected) { pr_err("%s: Unexpected interrupt 0x%08x.\n", +@@ -2660,7 +2749,7 @@ int sdhci_resume_host(struct sdhci_host *host) + } + + if (!device_may_wakeup(mmc_dev(host->mmc))) { +- ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, ++ ret = request_irq(host->irq, sdhci_irq, 0 /*IRQF_SHARED*/, + mmc_hostname(host->mmc), host); + if (ret) + return ret; @@ -2737,15 +2826,15 @@ int sdhci_runtime_suspend_host(struct sdhci_host *host) host->flags &= ~SDHCI_NEEDS_RETUNING; } @@ -87435,16 +88329,18 @@ index 763dbf9..2c47d16 100644 return ret; } -@@ -3287,7 +3376,7 @@ int sdhci_add_host(struct sdhci_host *host) - host->tuning_timer.function = sdhci_tuning_timer; - } +@@ -3286,8 +3375,8 @@ int sdhci_add_host(struct sdhci_host *host) + + sdhci_init(host, 0); - ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, -+ ret = request_irq(host->irq, sdhci_irq, 0,//IRQF_SHARED, - mmc_hostname(mmc), host); +- mmc_hostname(mmc), host); ++ ret = request_irq(host->irq, sdhci_irq, 0 /*IRQF_SHARED*/, ++ mmc_hostname(mmc), host); if (ret) { pr_err("%s: Failed to request IRQ %d: %d\n", -@@ -3351,7 +3440,7 @@ void sdhci_remove_host(struct sdhci_host *host, int dead) + mmc_hostname(mmc), host->irq, ret); +@@ -3348,7 +3437,7 @@ void sdhci_remove_host(struct sdhci_host *host, int dead) unsigned long flags; if (dead) { @@ -87453,7 +88349,7 @@ index 763dbf9..2c47d16 100644 host->flags |= SDHCI_DEVICE_DEAD; -@@ -3363,7 +3452,7 @@ void sdhci_remove_host(struct sdhci_host *host, int dead) +@@ -3360,7 +3449,7 @@ void sdhci_remove_host(struct sdhci_host *host, int dead) tasklet_schedule(&host->finish_tasklet); } @@ -87478,7 +88374,7 @@ index 8a02ec8..4218039 100644 + #endif /* __SDHCI_HW_H */ diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h -index 458794c..f085d4d 100644 +index aad2393..0aeeef8 100644 --- a/include/linux/mmc/sdhci.h +++ b/include/linux/mmc/sdhci.h @@ -100,6 +100,7 @@ struct sdhci_host { @@ -87493,10 +88389,10 @@ index 458794c..f085d4d 100644 1.8.4 -From 8bfe5c9ae72152c622541ddf8a1c93f0b59fc9b7 Mon Sep 17 00:00:00 2001 +From 10573426156ce4a50557fcd3b3e97406f13434d7 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:46:42 +0100 -Subject: [PATCH 29/98] Add FIQ patch to dwc_otg driver. Enable with +Subject: [PATCH 28/82] Add FIQ patch to dwc_otg driver. Enable with dwc_otg.fiq_fix_enable=1. Should give about 10% more ARM performance. Thanks to Gordon and Costas @@ -87527,10 +88423,10 @@ Subject: [PATCH 29/98] Add FIQ patch to dwc_otg driver. Enable with create mode 100755 drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index 9935688..b06d944 100644 +index 54da673..d605c86 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -378,6 +378,7 @@ config ARCH_BCM2708 +@@ -380,6 +380,7 @@ config ARCH_BCM2708 select ARM_ERRATA_411920 select MACH_BCM2708 select VC4 @@ -87628,10 +88524,10 @@ index da18725..274aa30 100644 return 0; } diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 402bfe7..6bf738a 100644 +index 5f869e8..dd73b81 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -308,12 +308,32 @@ static void __init bcm2708_clocksource_init(void) +@@ -314,12 +314,32 @@ static void __init bcm2708_clocksource_init(void) .flags = IORESOURCE_MEM, }, [1] = { @@ -87666,7 +88562,7 @@ index 402bfe7..6bf738a 100644 static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); static struct platform_device bcm2708_usb_device = { -@@ -583,6 +603,11 @@ void __init bcm2708_init(void) +@@ -650,6 +670,11 @@ void __init bcm2708_init(void) #endif bcm_register_device(&bcm2708_systemtimer_device); bcm_register_device(&bcm2708_fb_device); @@ -88656,423 +89552,10 @@ index e46d9bb..6b2c7d0 100644 1.8.4 -From 80627048540879277d55c32bfd1c6baa86553a0d Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Fri, 12 Apr 2013 23:58:47 +0100 -Subject: [PATCH 32/98] Add verious user config requests. - CONFIG_DEVTMPFS_MOUNT, CONFIG_NFS_V4_1=y CONFIG_NFSD_V3_ACL=y - CONFIG_NFSD_V4=y, drbd and IPSEC modules - ---- - arch/arm/configs/bcmrpi_defconfig | 334 ++++++++++++++++++++++++++++++++++++-- - 1 file changed, 324 insertions(+), 10 deletions(-) - -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 31f5afaa..ef43466 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -1,3 +1,4 @@ -+# CONFIG_ARM_PATCH_PHYS_VIRT is not set - CONFIG_EXPERIMENTAL=y - # CONFIG_LOCALVERSION_AUTO is not set - CONFIG_SYSVIPC=y -@@ -52,12 +53,212 @@ CONFIG_IP_PNP=y - CONFIG_IP_PNP_DHCP=y - CONFIG_IP_PNP_RARP=y - CONFIG_SYN_COOKIES=y --# CONFIG_INET_XFRM_MODE_TRANSPORT is not set --# CONFIG_INET_XFRM_MODE_TUNNEL is not set --# CONFIG_INET_XFRM_MODE_BEET is not set --# CONFIG_INET_LRO is not set --# CONFIG_INET_DIAG is not set --# CONFIG_IPV6 is not set -+CONFIG_INET_AH=m -+CONFIG_INET_ESP=m -+CONFIG_INET_IPCOMP=m -+CONFIG_INET_XFRM_MODE_TRANSPORT=m -+CONFIG_INET_XFRM_MODE_TUNNEL=m -+CONFIG_INET_XFRM_MODE_BEET=m -+CONFIG_INET_LRO=m -+CONFIG_INET_DIAG=m -+CONFIG_IPV6_PRIVACY=y -+CONFIG_INET6_AH=m -+CONFIG_INET6_ESP=m -+CONFIG_INET6_IPCOMP=m -+CONFIG_IPV6_MULTIPLE_TABLES=y -+CONFIG_NETFILTER=y -+CONFIG_NF_CONNTRACK=m -+CONFIG_NF_CONNTRACK_ZONES=y -+CONFIG_NF_CONNTRACK_EVENTS=y -+CONFIG_NF_CONNTRACK_TIMESTAMP=y -+CONFIG_NF_CT_PROTO_DCCP=m -+CONFIG_NF_CT_PROTO_SCTP=m -+CONFIG_NF_CT_PROTO_UDPLITE=m -+CONFIG_NF_CONNTRACK_AMANDA=m -+CONFIG_NF_CONNTRACK_FTP=m -+CONFIG_NF_CONNTRACK_H323=m -+CONFIG_NF_CONNTRACK_IRC=m -+CONFIG_NF_CONNTRACK_NETBIOS_NS=m -+CONFIG_NF_CONNTRACK_SNMP=m -+CONFIG_NF_CONNTRACK_PPTP=m -+CONFIG_NF_CONNTRACK_SANE=m -+CONFIG_NF_CONNTRACK_SIP=m -+CONFIG_NF_CONNTRACK_TFTP=m -+CONFIG_NF_CT_NETLINK=m -+CONFIG_NETFILTER_TPROXY=m -+CONFIG_NETFILTER_XT_SET=m -+CONFIG_NETFILTER_XT_TARGET_AUDIT=m -+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -+CONFIG_NETFILTER_XT_TARGET_CT=m -+CONFIG_NETFILTER_XT_TARGET_DSCP=m -+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m -+CONFIG_NETFILTER_XT_TARGET_LED=m -+CONFIG_NETFILTER_XT_TARGET_MARK=m -+CONFIG_NETFILTER_XT_TARGET_NFLOG=m -+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m -+CONFIG_NETFILTER_XT_TARGET_TEE=m -+CONFIG_NETFILTER_XT_TARGET_TPROXY=m -+CONFIG_NETFILTER_XT_TARGET_TRACE=m -+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m -+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -+CONFIG_NETFILTER_XT_MATCH_COMMENT=m -+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -+CONFIG_NETFILTER_XT_MATCH_CPU=m -+CONFIG_NETFILTER_XT_MATCH_DCCP=m -+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m -+CONFIG_NETFILTER_XT_MATCH_DSCP=m -+CONFIG_NETFILTER_XT_MATCH_ESP=m -+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_HELPER=m -+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -+CONFIG_NETFILTER_XT_MATCH_LENGTH=m -+CONFIG_NETFILTER_XT_MATCH_LIMIT=m -+CONFIG_NETFILTER_XT_MATCH_MAC=m -+CONFIG_NETFILTER_XT_MATCH_MARK=m -+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -+CONFIG_NETFILTER_XT_MATCH_OSF=m -+CONFIG_NETFILTER_XT_MATCH_OWNER=m -+CONFIG_NETFILTER_XT_MATCH_POLICY=m -+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -+CONFIG_NETFILTER_XT_MATCH_QUOTA=m -+CONFIG_NETFILTER_XT_MATCH_RATEEST=m -+CONFIG_NETFILTER_XT_MATCH_REALM=m -+CONFIG_NETFILTER_XT_MATCH_RECENT=m -+CONFIG_NETFILTER_XT_MATCH_SCTP=m -+CONFIG_NETFILTER_XT_MATCH_SOCKET=m -+CONFIG_NETFILTER_XT_MATCH_STATE=m -+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -+CONFIG_NETFILTER_XT_MATCH_STRING=m -+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -+CONFIG_NETFILTER_XT_MATCH_TIME=m -+CONFIG_NETFILTER_XT_MATCH_U32=m -+CONFIG_IP_SET=m -+CONFIG_IP_SET_BITMAP_IP=m -+CONFIG_IP_SET_BITMAP_IPMAC=m -+CONFIG_IP_SET_BITMAP_PORT=m -+CONFIG_IP_SET_HASH_IP=m -+CONFIG_IP_SET_HASH_IPPORT=m -+CONFIG_IP_SET_HASH_IPPORTIP=m -+CONFIG_IP_SET_HASH_IPPORTNET=m -+CONFIG_IP_SET_HASH_NET=m -+CONFIG_IP_SET_HASH_NETPORT=m -+CONFIG_IP_SET_HASH_NETIFACE=m -+CONFIG_IP_SET_LIST_SET=m -+CONFIG_NF_CONNTRACK_IPV4=m -+CONFIG_IP_NF_IPTABLES=m -+CONFIG_IP_NF_MATCH_AH=m -+CONFIG_IP_NF_MATCH_ECN=m -+CONFIG_IP_NF_MATCH_TTL=m -+CONFIG_IP_NF_FILTER=m -+CONFIG_IP_NF_TARGET_REJECT=m -+CONFIG_IP_NF_TARGET_LOG=m -+CONFIG_IP_NF_TARGET_ULOG=m -+CONFIG_NF_NAT=m -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+CONFIG_IP_NF_TARGET_NETMAP=m -+CONFIG_IP_NF_TARGET_REDIRECT=m -+CONFIG_IP_NF_MANGLE=m -+CONFIG_IP_NF_TARGET_ECN=m -+CONFIG_IP_NF_TARGET_TTL=m -+CONFIG_IP_NF_RAW=m -+CONFIG_IP_NF_ARPTABLES=m -+CONFIG_IP_NF_ARPFILTER=m -+CONFIG_IP_NF_ARP_MANGLE=m -+CONFIG_NF_CONNTRACK_IPV6=m -+CONFIG_IP6_NF_IPTABLES=m -+CONFIG_IP6_NF_MATCH_AH=m -+CONFIG_IP6_NF_MATCH_EUI64=m -+CONFIG_IP6_NF_MATCH_FRAG=m -+CONFIG_IP6_NF_MATCH_OPTS=m -+CONFIG_IP6_NF_MATCH_HL=m -+CONFIG_IP6_NF_MATCH_IPV6HEADER=m -+CONFIG_IP6_NF_MATCH_MH=m -+CONFIG_IP6_NF_MATCH_RT=m -+CONFIG_IP6_NF_TARGET_HL=m -+CONFIG_IP6_NF_TARGET_LOG=m -+CONFIG_IP6_NF_FILTER=m -+CONFIG_IP6_NF_TARGET_REJECT=m -+CONFIG_IP6_NF_MANGLE=m -+CONFIG_IP6_NF_RAW=m -+CONFIG_BRIDGE_NF_EBTABLES=m -+CONFIG_BRIDGE_EBT_BROUTE=m -+CONFIG_BRIDGE_EBT_T_FILTER=m -+CONFIG_BRIDGE_EBT_T_NAT=m -+CONFIG_BRIDGE_EBT_802_3=m -+CONFIG_BRIDGE_EBT_AMONG=m -+CONFIG_BRIDGE_EBT_ARP=m -+CONFIG_BRIDGE_EBT_IP=m -+CONFIG_BRIDGE_EBT_IP6=m -+CONFIG_BRIDGE_EBT_LIMIT=m -+CONFIG_BRIDGE_EBT_MARK=m -+CONFIG_BRIDGE_EBT_PKTTYPE=m -+CONFIG_BRIDGE_EBT_STP=m -+CONFIG_BRIDGE_EBT_VLAN=m -+CONFIG_BRIDGE_EBT_ARPREPLY=m -+CONFIG_BRIDGE_EBT_DNAT=m -+CONFIG_BRIDGE_EBT_MARK_T=m -+CONFIG_BRIDGE_EBT_REDIRECT=m -+CONFIG_BRIDGE_EBT_SNAT=m -+CONFIG_BRIDGE_EBT_LOG=m -+CONFIG_BRIDGE_EBT_ULOG=m -+CONFIG_BRIDGE_EBT_NFLOG=m -+CONFIG_BRIDGE=m -+CONFIG_VLAN_8021Q=m -+CONFIG_VLAN_8021Q_GVRP=y -+CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_CBQ=m -+CONFIG_NET_SCH_HTB=m -+CONFIG_NET_SCH_HFSC=m -+CONFIG_NET_SCH_PRIO=m -+CONFIG_NET_SCH_MULTIQ=m -+CONFIG_NET_SCH_RED=m -+CONFIG_NET_SCH_SFB=m -+CONFIG_NET_SCH_SFQ=m -+CONFIG_NET_SCH_TEQL=m -+CONFIG_NET_SCH_TBF=m -+CONFIG_NET_SCH_GRED=m -+CONFIG_NET_SCH_DSMARK=m -+CONFIG_NET_SCH_NETEM=m -+CONFIG_NET_SCH_DRR=m -+CONFIG_NET_SCH_MQPRIO=m -+CONFIG_NET_SCH_CHOKE=m -+CONFIG_NET_SCH_QFQ=m -+CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_TCINDEX=m -+CONFIG_NET_CLS_ROUTE4=m -+CONFIG_NET_CLS_FW=m -+CONFIG_NET_CLS_U32=m -+CONFIG_CLS_U32_MARK=y -+CONFIG_NET_CLS_RSVP=m -+CONFIG_NET_CLS_RSVP6=m -+CONFIG_NET_CLS_FLOW=m -+CONFIG_NET_CLS_CGROUP=m -+CONFIG_NET_EMATCH=y -+CONFIG_NET_EMATCH_CMP=m -+CONFIG_NET_EMATCH_NBYTE=m -+CONFIG_NET_EMATCH_U32=m -+CONFIG_NET_EMATCH_META=m -+CONFIG_NET_EMATCH_TEXT=m -+CONFIG_NET_CLS_ACT=y -+CONFIG_NET_ACT_POLICE=m -+CONFIG_NET_ACT_GACT=m -+CONFIG_GACT_PROB=y -+CONFIG_NET_ACT_MIRRED=m -+CONFIG_NET_ACT_IPT=m -+CONFIG_NET_ACT_NAT=m -+CONFIG_NET_ACT_PEDIT=m -+CONFIG_NET_ACT_SIMP=m -+CONFIG_NET_ACT_SKBEDIT=m -+CONFIG_NET_ACT_CSUM=m - CONFIG_NET_PKTGEN=m - CONFIG_IRDA=m - CONFIG_IRLAN=m -@@ -98,8 +299,11 @@ CONFIG_NET_9P=m - CONFIG_NFC=m - CONFIG_NFC_PN533=m - CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y - CONFIG_BLK_DEV_LOOP=y - CONFIG_BLK_DEV_CRYPTOLOOP=m -+CONFIG_BLK_DEV_DRBD=m - CONFIG_BLK_DEV_NBD=m - CONFIG_BLK_DEV_RAM=y - CONFIG_CDROM_PKTCDVD=m -@@ -143,12 +347,12 @@ CONFIG_RT2500USB=m - CONFIG_RT73USB=m - CONFIG_RT2800USB=m - CONFIG_RT2800USB_RT53XX=y --CONFIG_RTL8192CU=m - CONFIG_WL1251=m - CONFIG_WL12XX_MENU=m - CONFIG_ZD1211RW=m - CONFIG_MWIFIEX=m - CONFIG_MWIFIEX_SDIO=m -+CONFIG_RTL8192CU=m - CONFIG_WIMAX_I2400M_USB=m - CONFIG_USB_CATC=m - CONFIG_USB_KAWETH=m -@@ -224,7 +428,116 @@ CONFIG_GPIO_SYSFS=y - # CONFIG_HWMON is not set - CONFIG_WATCHDOG=y - CONFIG_BCM2708_WDT=m --# CONFIG_MFD_SUPPORT is not set -+CONFIG_MEDIA_SUPPORT=m -+CONFIG_VIDEO_DEV=m -+CONFIG_DVB_CORE=m -+CONFIG_RC_ATI_REMOTE=m -+CONFIG_IR_IMON=m -+CONFIG_IR_MCEUSB=m -+CONFIG_IR_REDRAT3=m -+CONFIG_IR_STREAMZAP=m -+CONFIG_RC_LOOPBACK=m -+CONFIG_MEDIA_ATTACH=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_USB_M5602=m -+CONFIG_USB_STV06XX=m -+CONFIG_USB_GL860=m -+CONFIG_USB_GSPCA_BENQ=m -+CONFIG_USB_GSPCA_CONEX=m -+CONFIG_USB_GSPCA_CPIA1=m -+CONFIG_USB_GSPCA_ETOMS=m -+CONFIG_USB_GSPCA_FINEPIX=m -+CONFIG_USB_GSPCA_JEILINJ=m -+CONFIG_USB_GSPCA_KINECT=m -+CONFIG_USB_GSPCA_KONICA=m -+CONFIG_USB_GSPCA_MARS=m -+CONFIG_USB_GSPCA_MR97310A=m -+CONFIG_USB_GSPCA_NW80X=m -+CONFIG_USB_GSPCA_OV519=m -+CONFIG_USB_GSPCA_OV534=m -+CONFIG_USB_GSPCA_OV534_9=m -+CONFIG_USB_GSPCA_PAC207=m -+CONFIG_USB_GSPCA_PAC7302=m -+CONFIG_USB_GSPCA_PAC7311=m -+CONFIG_USB_GSPCA_SE401=m -+CONFIG_USB_GSPCA_SN9C2028=m -+CONFIG_USB_GSPCA_SN9C20X=m -+CONFIG_USB_GSPCA_SONIXB=m -+CONFIG_USB_GSPCA_SONIXJ=m -+CONFIG_USB_GSPCA_SPCA500=m -+CONFIG_USB_GSPCA_SPCA501=m -+CONFIG_USB_GSPCA_SPCA505=m -+CONFIG_USB_GSPCA_SPCA506=m -+CONFIG_USB_GSPCA_SPCA508=m -+CONFIG_USB_GSPCA_SPCA561=m -+CONFIG_USB_GSPCA_SPCA1528=m -+CONFIG_USB_GSPCA_SQ905=m -+CONFIG_USB_GSPCA_SQ905C=m -+CONFIG_USB_GSPCA_SQ930X=m -+CONFIG_USB_GSPCA_STK014=m -+CONFIG_USB_GSPCA_STV0680=m -+CONFIG_USB_GSPCA_SUNPLUS=m -+CONFIG_USB_GSPCA_T613=m -+CONFIG_USB_GSPCA_TV8532=m -+CONFIG_USB_GSPCA_VC032X=m -+CONFIG_USB_GSPCA_VICAM=m -+CONFIG_USB_GSPCA_XIRLINK_CIT=m -+CONFIG_USB_GSPCA_ZC3XX=m -+CONFIG_VIDEO_PVRUSB2=m -+CONFIG_VIDEO_HDPVR=m -+CONFIG_VIDEO_EM28XX=m -+CONFIG_VIDEO_EM28XX_ALSA=m -+CONFIG_VIDEO_EM28XX_DVB=m -+CONFIG_VIDEO_TLG2300=m -+CONFIG_VIDEO_CX231XX=m -+CONFIG_VIDEO_CX231XX_ALSA=m -+CONFIG_VIDEO_CX231XX_DVB=m -+CONFIG_VIDEO_USBVISION=m -+CONFIG_USB_ET61X251=m -+CONFIG_USB_SN9C102=m -+CONFIG_USB_PWC=m -+CONFIG_USB_ZR364XX=m -+CONFIG_USB_STKWEBCAM=m -+CONFIG_USB_S2255=m -+CONFIG_USB_DSBR=m -+CONFIG_RADIO_SI470X=y -+CONFIG_USB_SI470X=m -+CONFIG_USB_MR800=m -+CONFIG_DVB_USB=m -+CONFIG_DVB_USB_A800=m -+CONFIG_DVB_USB_DIBUSB_MB=m -+CONFIG_DVB_USB_DIBUSB_MC=m -+CONFIG_DVB_USB_DIB0700=m -+CONFIG_DVB_USB_UMT_010=m -+CONFIG_DVB_USB_CXUSB=m -+CONFIG_DVB_USB_M920X=m -+CONFIG_DVB_USB_GL861=m -+CONFIG_DVB_USB_AU6610=m -+CONFIG_DVB_USB_DIGITV=m -+CONFIG_DVB_USB_VP7045=m -+CONFIG_DVB_USB_VP702X=m -+CONFIG_DVB_USB_GP8PSK=m -+CONFIG_DVB_USB_NOVA_T_USB2=m -+CONFIG_DVB_USB_TTUSB2=m -+CONFIG_DVB_USB_DTT200U=m -+CONFIG_DVB_USB_OPERA1=m -+CONFIG_DVB_USB_AF9005=m -+CONFIG_DVB_USB_AF9005_REMOTE=m -+CONFIG_DVB_USB_DW2102=m -+CONFIG_DVB_USB_CINERGY_T2=m -+CONFIG_DVB_USB_ANYSEE=m -+CONFIG_DVB_USB_DTV5100=m -+CONFIG_DVB_USB_AF9015=m -+CONFIG_DVB_USB_CE6230=m -+CONFIG_DVB_USB_FRIIO=m -+CONFIG_DVB_USB_EC168=m -+CONFIG_DVB_USB_AZ6027=m -+CONFIG_DVB_USB_LME2510=m -+CONFIG_DVB_USB_TECHNISAT_USB2=m -+CONFIG_SMS_SIANO_MDTV=m -+CONFIG_SMS_USB_DRV=m -+CONFIG_DVB_B2C2_FLEXCOP=m -+CONFIG_DVB_B2C2_FLEXCOP_USB=m - CONFIG_FB=y - CONFIG_FB_BCM2708=y - CONFIG_FRAMEBUFFER_CONSOLE=y -@@ -450,6 +763,9 @@ CONFIG_NFS_V3_ACL=y - CONFIG_NFS_V4=y - CONFIG_ROOT_NFS=y - CONFIG_NFS_FSCACHE=y -+CONFIG_NFSD=m -+CONFIG_NFSD_V3_ACL=y -+CONFIG_NFSD_V4=y - CONFIG_CIFS=m - CONFIG_CIFS_WEAK_PW_HASH=y - CONFIG_CIFS_XATTR=y -@@ -516,7 +832,6 @@ CONFIG_KGDB=y - CONFIG_KGDB_KDB=y - CONFIG_KDB_KEYBOARD=y - CONFIG_STRICT_DEVMEM=y --CONFIG_CRYPTO_AUTHENC=m - CONFIG_CRYPTO_SEQIV=m - CONFIG_CRYPTO_CBC=y - CONFIG_CRYPTO_HMAC=y -@@ -529,7 +844,6 @@ CONFIG_CRYPTO_TGR192=m - CONFIG_CRYPTO_WP512=m - CONFIG_CRYPTO_CAST5=m - CONFIG_CRYPTO_DES=y --CONFIG_CRYPTO_DEFLATE=m - # CONFIG_CRYPTO_ANSI_CPRNG is not set - # CONFIG_CRYPTO_HW is not set - CONFIG_CRC_ITU_T=y --- -1.8.4 - - -From 50ebfebc8fa2e1744afbeb86d6e3bb7c07d26464 Mon Sep 17 00:00:00 2001 +From 07635c35a799cd4b81b18ebf23b38b006a2b0316 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Sat, 8 Sep 2012 15:17:53 +0100 -Subject: [PATCH 33/98] Avoid dynamic memory allocation for channel lock in USB +Subject: [PATCH 31/82] Avoid dynamic memory allocation for channel lock in USB driver. Thanks ddv2005. --- @@ -89179,25 +89662,24 @@ index b7b6b0c..76b5085 100644 1.8.4 -From d6c1ae4ab108231b5dbe45ed16683c656fee1992 Mon Sep 17 00:00:00 2001 +From 513857d2806c9cdc7405e858f2c0d4404b79e508 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:49:20 +0100 -Subject: [PATCH 34/98] Add cpufreq driver +Subject: [PATCH 32/82] Add cpufreq driver --- arch/arm/Kconfig | 1 + - arch/arm/configs/bcmrpi_defconfig | 6 + drivers/cpufreq/Kconfig.arm | 8 ++ drivers/cpufreq/Makefile | 1 + - drivers/cpufreq/bcm2835-cpufreq.c | 238 ++++++++++++++++++++++++++++++++++++++ - 5 files changed, 254 insertions(+) + drivers/cpufreq/bcm2835-cpufreq.c | 239 ++++++++++++++++++++++++++++++++++++++ + 4 files changed, 249 insertions(+) create mode 100755 drivers/cpufreq/bcm2835-cpufreq.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index b06d944..fe64557 100644 +index d605c86..43c34dc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -374,6 +374,7 @@ config ARCH_BCM2708 +@@ -376,6 +376,7 @@ config ARCH_BCM2708 select HAVE_SCHED_CLOCK select NEED_MACH_MEMORY_H select CLKDEV_LOOKUP @@ -89205,28 +89687,11 @@ index b06d944..fe64557 100644 select GENERIC_CLOCKEVENTS select ARM_ERRATA_411920 select MACH_BCM2708 -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index ef43466..5b0a171 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -39,6 +39,12 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 - CONFIG_ZBOOT_ROM_BSS=0x0 - CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" - CONFIG_KEXEC=y -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_STAT=m -+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y - CONFIG_CPU_IDLE=y - CONFIG_VFP=y - CONFIG_BINFMT_MISC=m diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm -index de4d5d9..86b9a0a 100644 +index 0fa204b..b30b345 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm -@@ -216,6 +216,14 @@ config ARM_SPEAR_CPUFREQ +@@ -228,6 +228,14 @@ config ARM_SPEAR_CPUFREQ help This adds the CPUFreq driver support for SPEAr SOCs. @@ -89242,7 +89707,7 @@ index de4d5d9..86b9a0a 100644 bool "TEGRA CPUFreq support" depends on ARCH_TEGRA diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile -index d345b5a..06dd265 100644 +index ad5866c..a47a44c 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o @@ -89255,10 +89720,10 @@ index d345b5a..06dd265 100644 ################################################################################## diff --git a/drivers/cpufreq/bcm2835-cpufreq.c b/drivers/cpufreq/bcm2835-cpufreq.c new file mode 100755 -index 0000000..f9b976c +index 0000000..7bc55bd --- /dev/null +++ b/drivers/cpufreq/bcm2835-cpufreq.c -@@ -0,0 +1,238 @@ +@@ -0,0 +1,239 @@ +/***************************************************************************** +* Copyright 2011 Broadcom Corporation. All rights reserved. +* @@ -89352,7 +89817,7 @@ index 0000000..f9b976c + if (s == 0 && (msg.request_code & 0x80000000)) + actual_rate = msg.tag.val/1000; + -+ print_debug("Setting new frequency = %d -> %d (actual %d)", cur_rate, arm_rate, actual_rate); ++ print_debug("Setting new frequency = %d -> %d (actual %d)\n", cur_rate, arm_rate, actual_rate); + return actual_rate; +} + @@ -89378,7 +89843,7 @@ index 0000000..f9b976c + if (s == 0 && (msg.request_code & 0x80000000)) + arm_rate = msg.tag.val/1000; + -+ print_debug("%s frequency = %d", ++ print_debug("%s frequency = %d\n", + tag == VCMSG_GET_CLOCK_RATE ? "Current": + tag == VCMSG_GET_MIN_CLOCK ? "Min": + tag == VCMSG_GET_MAX_CLOCK ? "Max": @@ -89394,7 +89859,7 @@ index 0000000..f9b976c +*/ +static int __init bcm2835_cpufreq_module_init(void) +{ -+ print_debug("IN"); ++ print_debug("IN\n"); + return cpufreq_register_driver(&bcm2835_cpufreq_driver); +} + @@ -89405,7 +89870,7 @@ index 0000000..f9b976c +*/ +static void __exit bcm2835_cpufreq_module_exit(void) +{ -+ print_debug("IN"); ++ print_debug("IN\n"); + cpufreq_unregister_driver(&bcm2835_cpufreq_driver); + return; +} @@ -89425,7 +89890,7 @@ index 0000000..f9b976c + policy->max = policy->cpuinfo.max_freq = bcm2835_cpufreq_get_clock(VCMSG_GET_MAX_CLOCK); + policy->cur = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE); + -+ print_info("min=%d max=%d cur=%d", policy->min, policy->max, policy->cur); ++ print_info("min=%d max=%d cur=%d\n", policy->min, policy->max, policy->cur); + return 0; +} + @@ -89438,8 +89903,10 @@ index 0000000..f9b976c +static int bcm2835_cpufreq_driver_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation) +{ + unsigned int target = target_freq; ++#ifdef CPUFREQ_DEBUG_ENABLE + unsigned int cur = policy->cur; -+ print_debug("%s: min=%d max=%d cur=%d target=%d",policy->governor->name,policy->min,policy->max,policy->cur,target_freq); ++#endif ++ print_debug("%s: min=%d max=%d cur=%d target=%d\n",policy->governor->name,policy->min,policy->max,policy->cur,target_freq); + + /* if we are above min and using ondemand, then just use max */ + if (strcmp("ondemand", policy->governor->name)==0 && target > policy->min) @@ -89453,18 +89920,18 @@ index 0000000..f9b976c + + if (!policy->cur) + { -+ print_err("Error occurred setting a new frequency (%d)!", target); ++ print_err("Error occurred setting a new frequency (%d)!\n", target); + policy->cur = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE); + return -EINVAL; + } -+ print_debug("Freq %d->%d (min=%d max=%d target=%d request=%d)", cur, policy->cur, policy->min, policy->max, target_freq, target); ++ print_debug("Freq %d->%d (min=%d max=%d target=%d request=%d)\n", cur, policy->cur, policy->min, policy->max, target_freq, target); + return 0; +} + +static unsigned int bcm2835_cpufreq_driver_get(unsigned int cpu) +{ + unsigned int actual_rate = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE); -+ print_debug("%d", actual_rate); ++ print_debug("cpu=%d\n", actual_rate); + return actual_rate; +} + @@ -89476,7 +89943,7 @@ index 0000000..f9b976c + +static int bcm2835_cpufreq_driver_verify(struct cpufreq_policy *policy) +{ -+ print_info("switching to governor %s", policy->governor->name); ++ print_info("switching to governor %s\n", policy->governor->name); + return 0; +} + @@ -89484,7 +89951,6 @@ index 0000000..f9b976c +/* the CPUFreq driver */ +static struct cpufreq_driver bcm2835_cpufreq_driver = { + .name = "BCM2835 CPUFreq", -+ .owner = THIS_MODULE, + .init = bcm2835_cpufreq_driver_init, + .verify = bcm2835_cpufreq_driver_verify, + .target = bcm2835_cpufreq_driver_target, @@ -89501,10 +89967,939 @@ index 0000000..f9b976c 1.8.4 -From 4dc2e0f78d48cc663d2bc6ace7cfffad1f757c93 Mon Sep 17 00:00:00 2001 +From 48f4a94476f55b5c51c2c51268cf8d7e28247f19 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Fri, 12 Apr 2013 23:58:47 +0100 +Subject: [PATCH 33/82] config: add missing options from 3.6.y kernel + +--- + arch/arm/configs/bcmrpi_defconfig | 637 +++++++++++++++++++++++++++++++++----- + 1 file changed, 551 insertions(+), 86 deletions(-) + +diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig +index 31f5afaa..1db7746 100644 +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -1,11 +1,17 @@ +-CONFIG_EXPERIMENTAL=y ++# CONFIG_ARM_PATCH_PHYS_VIRT is not set + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SYSVIPC=y + CONFIG_POSIX_MQUEUE=y +-CONFIG_BSD_PROCESS_ACCT=y +-CONFIG_BSD_PROCESS_ACCT_V3=y + CONFIG_FHANDLE=y + CONFIG_AUDIT=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_BSD_PROCESS_ACCT=y ++CONFIG_BSD_PROCESS_ACCT_V3=y ++CONFIG_TASKSTATS=y ++CONFIG_TASK_DELAY_ACCT=y ++CONFIG_TASK_XACCT=y ++CONFIG_TASK_IO_ACCOUNTING=y + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y + CONFIG_CGROUP_FREEZER=y +@@ -15,22 +21,23 @@ CONFIG_RESOURCE_COUNTERS=y + CONFIG_BLK_CGROUP=y + CONFIG_NAMESPACES=y + CONFIG_SCHED_AUTOGROUP=y ++CONFIG_BLK_DEV_INITRD=y + CONFIG_EMBEDDED=y + # CONFIG_COMPAT_BRK is not set +-CONFIG_SLAB=y + CONFIG_PROFILING=y + CONFIG_OPROFILE=m + CONFIG_KPROBES=y ++CONFIG_JUMP_LABEL=y + CONFIG_MODULES=y + CONFIG_MODULE_UNLOAD=y + CONFIG_MODVERSIONS=y + CONFIG_MODULE_SRCVERSION_ALL=y + # CONFIG_BLK_DEV_BSG is not set + CONFIG_BLK_DEV_THROTTLING=y ++CONFIG_PARTITION_ADVANCED=y ++CONFIG_MAC_PARTITION=y + CONFIG_CFQ_GROUP_IOSCHED=y + CONFIG_ARCH_BCM2708=y +-CONFIG_NO_HZ=y +-CONFIG_HIGH_RES_TIMERS=y + CONFIG_AEABI=y + CONFIG_SECCOMP=y + CONFIG_CC_STACKPROTECTOR=y +@@ -38,6 +45,14 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 + CONFIG_ZBOOT_ROM_BSS=0x0 + CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" + CONFIG_KEXEC=y ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_STAT=m ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y + CONFIG_CPU_IDLE=y + CONFIG_VFP=y + CONFIG_BINFMT_MISC=m +@@ -52,15 +67,257 @@ CONFIG_IP_PNP=y + CONFIG_IP_PNP_DHCP=y + CONFIG_IP_PNP_RARP=y + CONFIG_SYN_COOKIES=y +-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +-# CONFIG_INET_XFRM_MODE_TUNNEL is not set +-# CONFIG_INET_XFRM_MODE_BEET is not set +-# CONFIG_INET_LRO is not set +-# CONFIG_INET_DIAG is not set +-# CONFIG_IPV6 is not set ++CONFIG_INET_AH=m ++CONFIG_INET_ESP=m ++CONFIG_INET_IPCOMP=m ++CONFIG_INET_XFRM_MODE_TRANSPORT=m ++CONFIG_INET_XFRM_MODE_TUNNEL=m ++CONFIG_INET_XFRM_MODE_BEET=m ++CONFIG_INET_LRO=m ++CONFIG_INET_DIAG=m ++CONFIG_IPV6_PRIVACY=y ++CONFIG_INET6_AH=m ++CONFIG_INET6_ESP=m ++CONFIG_INET6_IPCOMP=m ++CONFIG_IPV6_MULTIPLE_TABLES=y ++CONFIG_NETFILTER=y ++CONFIG_NF_CONNTRACK=m ++CONFIG_NF_CONNTRACK_ZONES=y ++CONFIG_NF_CONNTRACK_EVENTS=y ++CONFIG_NF_CONNTRACK_TIMESTAMP=y ++CONFIG_NF_CT_PROTO_DCCP=m ++CONFIG_NF_CT_PROTO_UDPLITE=m ++CONFIG_NF_CONNTRACK_AMANDA=m ++CONFIG_NF_CONNTRACK_FTP=m ++CONFIG_NF_CONNTRACK_H323=m ++CONFIG_NF_CONNTRACK_IRC=m ++CONFIG_NF_CONNTRACK_NETBIOS_NS=m ++CONFIG_NF_CONNTRACK_SNMP=m ++CONFIG_NF_CONNTRACK_PPTP=m ++CONFIG_NF_CONNTRACK_SANE=m ++CONFIG_NF_CONNTRACK_SIP=m ++CONFIG_NF_CONNTRACK_TFTP=m ++CONFIG_NF_CT_NETLINK=m ++CONFIG_NETFILTER_TPROXY=m ++CONFIG_NETFILTER_XT_SET=m ++CONFIG_NETFILTER_XT_TARGET_AUDIT=m ++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m ++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m ++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m ++CONFIG_NETFILTER_XT_TARGET_DSCP=m ++CONFIG_NETFILTER_XT_TARGET_HMARK=m ++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m ++CONFIG_NETFILTER_XT_TARGET_LED=m ++CONFIG_NETFILTER_XT_TARGET_LOG=m ++CONFIG_NETFILTER_XT_TARGET_MARK=m ++CONFIG_NETFILTER_XT_TARGET_NFLOG=m ++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m ++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m ++CONFIG_NETFILTER_XT_TARGET_TEE=m ++CONFIG_NETFILTER_XT_TARGET_TPROXY=m ++CONFIG_NETFILTER_XT_TARGET_TRACE=m ++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m ++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m ++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m ++CONFIG_NETFILTER_XT_MATCH_BPF=m ++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m ++CONFIG_NETFILTER_XT_MATCH_COMMENT=m ++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m ++CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m ++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m ++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m ++CONFIG_NETFILTER_XT_MATCH_CPU=m ++CONFIG_NETFILTER_XT_MATCH_DCCP=m ++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m ++CONFIG_NETFILTER_XT_MATCH_DSCP=m ++CONFIG_NETFILTER_XT_MATCH_ESP=m ++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_HELPER=m ++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m ++CONFIG_NETFILTER_XT_MATCH_LENGTH=m ++CONFIG_NETFILTER_XT_MATCH_LIMIT=m ++CONFIG_NETFILTER_XT_MATCH_MAC=m ++CONFIG_NETFILTER_XT_MATCH_MARK=m ++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m ++CONFIG_NETFILTER_XT_MATCH_NFACCT=m ++CONFIG_NETFILTER_XT_MATCH_OSF=m ++CONFIG_NETFILTER_XT_MATCH_OWNER=m ++CONFIG_NETFILTER_XT_MATCH_POLICY=m ++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m ++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m ++CONFIG_NETFILTER_XT_MATCH_QUOTA=m ++CONFIG_NETFILTER_XT_MATCH_RATEEST=m ++CONFIG_NETFILTER_XT_MATCH_REALM=m ++CONFIG_NETFILTER_XT_MATCH_RECENT=m ++CONFIG_NETFILTER_XT_MATCH_SOCKET=m ++CONFIG_NETFILTER_XT_MATCH_STATE=m ++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m ++CONFIG_NETFILTER_XT_MATCH_STRING=m ++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m ++CONFIG_NETFILTER_XT_MATCH_TIME=m ++CONFIG_NETFILTER_XT_MATCH_U32=m ++CONFIG_IP_SET=m ++CONFIG_IP_SET_BITMAP_IP=m ++CONFIG_IP_SET_BITMAP_IPMAC=m ++CONFIG_IP_SET_BITMAP_PORT=m ++CONFIG_IP_SET_HASH_IP=m ++CONFIG_IP_SET_HASH_IPPORT=m ++CONFIG_IP_SET_HASH_IPPORTIP=m ++CONFIG_IP_SET_HASH_IPPORTNET=m ++CONFIG_IP_SET_HASH_NET=m ++CONFIG_IP_SET_HASH_NETPORT=m ++CONFIG_IP_SET_HASH_NETIFACE=m ++CONFIG_IP_SET_LIST_SET=m ++CONFIG_IP_VS=m ++CONFIG_IP_VS_PROTO_TCP=y ++CONFIG_IP_VS_PROTO_UDP=y ++CONFIG_IP_VS_PROTO_ESP=y ++CONFIG_IP_VS_PROTO_AH=y ++CONFIG_IP_VS_PROTO_SCTP=y ++CONFIG_IP_VS_RR=m ++CONFIG_IP_VS_WRR=m ++CONFIG_IP_VS_LC=m ++CONFIG_IP_VS_WLC=m ++CONFIG_IP_VS_LBLC=m ++CONFIG_IP_VS_LBLCR=m ++CONFIG_IP_VS_DH=m ++CONFIG_IP_VS_SH=m ++CONFIG_IP_VS_SED=m ++CONFIG_IP_VS_NQ=m ++CONFIG_IP_VS_FTP=m ++CONFIG_IP_VS_PE_SIP=m ++CONFIG_NF_CONNTRACK_IPV4=m ++CONFIG_IP_NF_IPTABLES=m ++CONFIG_IP_NF_MATCH_AH=m ++CONFIG_IP_NF_MATCH_ECN=m ++CONFIG_IP_NF_MATCH_TTL=m ++CONFIG_IP_NF_FILTER=m ++CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_TARGET_ULOG=m ++CONFIG_NF_NAT_IPV4=m ++CONFIG_IP_NF_TARGET_MASQUERADE=m ++CONFIG_IP_NF_TARGET_NETMAP=m ++CONFIG_IP_NF_TARGET_REDIRECT=m ++CONFIG_IP_NF_MANGLE=m ++CONFIG_IP_NF_TARGET_ECN=m ++CONFIG_IP_NF_TARGET_TTL=m ++CONFIG_IP_NF_RAW=m ++CONFIG_IP_NF_ARPTABLES=m ++CONFIG_IP_NF_ARPFILTER=m ++CONFIG_IP_NF_ARP_MANGLE=m ++CONFIG_NF_CONNTRACK_IPV6=m ++CONFIG_IP6_NF_IPTABLES=m ++CONFIG_IP6_NF_MATCH_AH=m ++CONFIG_IP6_NF_MATCH_EUI64=m ++CONFIG_IP6_NF_MATCH_FRAG=m ++CONFIG_IP6_NF_MATCH_OPTS=m ++CONFIG_IP6_NF_MATCH_HL=m ++CONFIG_IP6_NF_MATCH_IPV6HEADER=m ++CONFIG_IP6_NF_MATCH_MH=m ++CONFIG_IP6_NF_MATCH_RT=m ++CONFIG_IP6_NF_TARGET_HL=m ++CONFIG_IP6_NF_FILTER=m ++CONFIG_IP6_NF_TARGET_REJECT=m ++CONFIG_IP6_NF_MANGLE=m ++CONFIG_IP6_NF_RAW=m ++CONFIG_NF_NAT_IPV6=m ++CONFIG_IP6_NF_TARGET_MASQUERADE=m ++CONFIG_IP6_NF_TARGET_NPT=m ++CONFIG_BRIDGE_NF_EBTABLES=m ++CONFIG_BRIDGE_EBT_BROUTE=m ++CONFIG_BRIDGE_EBT_T_FILTER=m ++CONFIG_BRIDGE_EBT_T_NAT=m ++CONFIG_BRIDGE_EBT_802_3=m ++CONFIG_BRIDGE_EBT_AMONG=m ++CONFIG_BRIDGE_EBT_ARP=m ++CONFIG_BRIDGE_EBT_IP=m ++CONFIG_BRIDGE_EBT_IP6=m ++CONFIG_BRIDGE_EBT_LIMIT=m ++CONFIG_BRIDGE_EBT_MARK=m ++CONFIG_BRIDGE_EBT_PKTTYPE=m ++CONFIG_BRIDGE_EBT_STP=m ++CONFIG_BRIDGE_EBT_VLAN=m ++CONFIG_BRIDGE_EBT_ARPREPLY=m ++CONFIG_BRIDGE_EBT_DNAT=m ++CONFIG_BRIDGE_EBT_MARK_T=m ++CONFIG_BRIDGE_EBT_REDIRECT=m ++CONFIG_BRIDGE_EBT_SNAT=m ++CONFIG_BRIDGE_EBT_LOG=m ++CONFIG_BRIDGE_EBT_ULOG=m ++CONFIG_BRIDGE_EBT_NFLOG=m ++CONFIG_SCTP_COOKIE_HMAC_SHA1=y ++CONFIG_L2TP=m ++CONFIG_BRIDGE=m ++CONFIG_VLAN_8021Q=m ++CONFIG_VLAN_8021Q_GVRP=y ++CONFIG_ATALK=m ++CONFIG_NET_SCHED=y ++CONFIG_NET_SCH_CBQ=m ++CONFIG_NET_SCH_HTB=m ++CONFIG_NET_SCH_HFSC=m ++CONFIG_NET_SCH_PRIO=m ++CONFIG_NET_SCH_MULTIQ=m ++CONFIG_NET_SCH_RED=m ++CONFIG_NET_SCH_SFB=m ++CONFIG_NET_SCH_SFQ=m ++CONFIG_NET_SCH_TEQL=m ++CONFIG_NET_SCH_TBF=m ++CONFIG_NET_SCH_GRED=m ++CONFIG_NET_SCH_DSMARK=m ++CONFIG_NET_SCH_NETEM=m ++CONFIG_NET_SCH_DRR=m ++CONFIG_NET_SCH_MQPRIO=m ++CONFIG_NET_SCH_CHOKE=m ++CONFIG_NET_SCH_QFQ=m ++CONFIG_NET_SCH_CODEL=m ++CONFIG_NET_SCH_FQ_CODEL=m ++CONFIG_NET_SCH_INGRESS=m ++CONFIG_NET_SCH_PLUG=m ++CONFIG_NET_CLS_BASIC=m ++CONFIG_NET_CLS_TCINDEX=m ++CONFIG_NET_CLS_ROUTE4=m ++CONFIG_NET_CLS_FW=m ++CONFIG_NET_CLS_U32=m ++CONFIG_CLS_U32_MARK=y ++CONFIG_NET_CLS_RSVP=m ++CONFIG_NET_CLS_RSVP6=m ++CONFIG_NET_CLS_FLOW=m ++CONFIG_NET_CLS_CGROUP=m ++CONFIG_NET_EMATCH=y ++CONFIG_NET_EMATCH_CMP=m ++CONFIG_NET_EMATCH_NBYTE=m ++CONFIG_NET_EMATCH_U32=m ++CONFIG_NET_EMATCH_META=m ++CONFIG_NET_EMATCH_TEXT=m ++CONFIG_NET_EMATCH_IPSET=m ++CONFIG_NET_CLS_ACT=y ++CONFIG_NET_ACT_POLICE=m ++CONFIG_NET_ACT_GACT=m ++CONFIG_GACT_PROB=y ++CONFIG_NET_ACT_MIRRED=m ++CONFIG_NET_ACT_IPT=m ++CONFIG_NET_ACT_NAT=m ++CONFIG_NET_ACT_PEDIT=m ++CONFIG_NET_ACT_SIMP=m ++CONFIG_NET_ACT_SKBEDIT=m ++CONFIG_NET_ACT_CSUM=m ++CONFIG_BATMAN_ADV=m ++CONFIG_OPENVSWITCH=m + CONFIG_NET_PKTGEN=m ++CONFIG_HAMRADIO=y ++CONFIG_AX25=m ++CONFIG_NETROM=m ++CONFIG_ROSE=m ++CONFIG_MKISS=m ++CONFIG_6PACK=m ++CONFIG_BPQETHER=m ++CONFIG_BAYCOM_SER_FDX=m ++CONFIG_BAYCOM_SER_HDX=m ++CONFIG_YAM=m + CONFIG_IRDA=m + CONFIG_IRLAN=m ++CONFIG_IRNET=m + CONFIG_IRCOMM=m + CONFIG_IRDA_ULTRA=y + CONFIG_IRDA_CACHE_LAST_LSAP=y +@@ -73,8 +330,6 @@ CONFIG_USB_IRDA=m + CONFIG_SIGMATEL_FIR=m + CONFIG_MCS_FIR=m + CONFIG_BT=m +-CONFIG_BT_L2CAP=y +-CONFIG_BT_SCO=y + CONFIG_BT_RFCOMM=m + CONFIG_BT_RFCOMM_TTY=y + CONFIG_BT_BNEP=m +@@ -89,21 +344,28 @@ CONFIG_BT_HCIVHCI=m + CONFIG_BT_MRVL=m + CONFIG_BT_MRVL_SDIO=m + CONFIG_BT_ATH3K=m ++CONFIG_BT_WILINK=m + CONFIG_CFG80211=m ++CONFIG_CFG80211_WEXT=y + CONFIG_MAC80211=m + CONFIG_MAC80211_RC_PID=y + CONFIG_MAC80211_MESH=y + CONFIG_WIMAX=m ++CONFIG_RFKILL=m ++CONFIG_RFKILL_INPUT=y + CONFIG_NET_9P=m + CONFIG_NFC=m + CONFIG_NFC_PN533=m + CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_CMA=y + CONFIG_BLK_DEV_LOOP=y + CONFIG_BLK_DEV_CRYPTOLOOP=m ++CONFIG_BLK_DEV_DRBD=m + CONFIG_BLK_DEV_NBD=m + CONFIG_BLK_DEV_RAM=y + CONFIG_CDROM_PKTCDVD=m +-CONFIG_MISC_DEVICES=y + CONFIG_SCSI=y + # CONFIG_SCSI_PROC_FS is not set + CONFIG_BLK_DEV_SD=m +@@ -111,13 +373,50 @@ CONFIG_BLK_DEV_SR=m + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_LOWLEVEL is not set + CONFIG_MD=y ++CONFIG_BLK_DEV_DM=m ++CONFIG_DM_CRYPT=m + CONFIG_NETDEVICES=y ++CONFIG_DUMMY=m ++CONFIG_NETCONSOLE=m + CONFIG_TUN=m +-CONFIG_PHYLIB=m + CONFIG_MDIO_BITBANG=m +-CONFIG_NET_ETHERNET=y +-# CONFIG_NETDEV_1000 is not set +-# CONFIG_NETDEV_10000 is not set ++CONFIG_PPP=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_RTL8152=m ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_CDC_MBIM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SMSC75XX=m ++CONFIG_USB_NET_SMSC95XX=y ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_EPSON2888=y ++CONFIG_USB_KC2190=y ++CONFIG_USB_NET_ZAURUS=m ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_QMI_WWAN=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m + CONFIG_LIBERTAS_THINFIRM=m + CONFIG_LIBERTAS_THINFIRM_USB=m + CONFIG_AT76C50X_USB=m +@@ -125,14 +424,18 @@ CONFIG_USB_ZD1201=m + CONFIG_USB_NET_RNDIS_WLAN=m + CONFIG_RTL8187=m + CONFIG_MAC80211_HWSIM=m +-CONFIG_ATH_COMMON=m ++CONFIG_ATH_CARDS=m + CONFIG_ATH9K=m + CONFIG_ATH9K_HTC=m + CONFIG_CARL9170=m ++CONFIG_ATH6KL=m ++CONFIG_ATH6KL_USB=m ++CONFIG_AR5523=m ++CONFIG_ATH10K=m + CONFIG_B43=m ++# CONFIG_B43_PHY_N is not set + CONFIG_B43LEGACY=m + CONFIG_HOSTAP=m +-CONFIG_IWM=m + CONFIG_LIBERTAS=m + CONFIG_LIBERTAS_USB=m + CONFIG_LIBERTAS_SDIO=m +@@ -143,56 +446,25 @@ CONFIG_RT2500USB=m + CONFIG_RT73USB=m + CONFIG_RT2800USB=m + CONFIG_RT2800USB_RT53XX=y ++CONFIG_RT2800USB_UNKNOWN=y + CONFIG_RTL8192CU=m +-CONFIG_WL1251=m +-CONFIG_WL12XX_MENU=m + CONFIG_ZD1211RW=m + CONFIG_MWIFIEX=m + CONFIG_MWIFIEX_SDIO=m + CONFIG_WIMAX_I2400M_USB=m +-CONFIG_USB_CATC=m +-CONFIG_USB_KAWETH=m +-CONFIG_USB_PEGASUS=m +-CONFIG_USB_RTL8150=m +-CONFIG_USB_USBNET=y +-CONFIG_USB_NET_AX8817X=m +-CONFIG_USB_NET_CDCETHER=m +-CONFIG_USB_NET_CDC_EEM=m +-CONFIG_USB_NET_DM9601=m +-CONFIG_USB_NET_SMSC75XX=m +-CONFIG_USB_NET_SMSC95XX=y +-CONFIG_USB_NET_GL620A=m +-CONFIG_USB_NET_NET1080=m +-CONFIG_USB_NET_PLUSB=m +-CONFIG_USB_NET_MCS7830=m +-CONFIG_USB_NET_CDC_SUBSET=m +-CONFIG_USB_ALI_M5632=y +-CONFIG_USB_AN2720=y +-CONFIG_USB_KC2190=y +-# CONFIG_USB_NET_ZAURUS is not set +-CONFIG_USB_NET_CX82310_ETH=m +-CONFIG_USB_NET_KALMIA=m +-CONFIG_USB_NET_INT51X1=m +-CONFIG_USB_IPHETH=m +-CONFIG_USB_SIERRA_NET=m +-CONFIG_USB_VL600=m +-CONFIG_PPP=m +-CONFIG_PPP_ASYNC=m +-CONFIG_PPP_SYNC_TTY=m +-CONFIG_PPP_DEFLATE=m +-CONFIG_PPP_BSDCOMP=m +-CONFIG_SLIP=m +-CONFIG_SLIP_COMPRESSED=y +-CONFIG_NETCONSOLE=m + CONFIG_INPUT_POLLDEV=m + # CONFIG_INPUT_MOUSEDEV_PSAUX is not set + CONFIG_INPUT_JOYDEV=m + CONFIG_INPUT_EVDEV=m + # CONFIG_INPUT_KEYBOARD is not set + # CONFIG_INPUT_MOUSE is not set ++CONFIG_INPUT_JOYSTICK=y ++CONFIG_JOYSTICK_IFORCE=m ++CONFIG_JOYSTICK_IFORCE_USB=y ++CONFIG_JOYSTICK_XPAD=m ++CONFIG_JOYSTICK_XPAD_FF=y + CONFIG_INPUT_MISC=y + CONFIG_INPUT_AD714X=m +-CONFIG_INPUT_ATI_REMOTE=m + CONFIG_INPUT_ATI_REMOTE2=m + CONFIG_INPUT_KEYSPAN_REMOTE=m + CONFIG_INPUT_POWERMATE=m +@@ -202,18 +474,17 @@ CONFIG_INPUT_UINPUT=m + CONFIG_INPUT_GPIO_ROTARY_ENCODER=m + CONFIG_INPUT_ADXL34X=m + CONFIG_INPUT_CMA3000=m +-CONFIG_SERIO=m +-CONFIG_SERIO_RAW=m +-CONFIG_GAMEPORT=m +-CONFIG_GAMEPORT_NS558=m +-CONFIG_GAMEPORT_L4=m ++# CONFIG_SERIO is not set + CONFIG_VT_HW_CONSOLE_BINDING=y + # CONFIG_LEGACY_PTYS is not set + # CONFIG_DEVKMEM is not set + CONFIG_SERIAL_AMBA_PL011=y + CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +-# CONFIG_HW_RANDOM is not set ++CONFIG_HW_RANDOM=y ++CONFIG_HW_RANDOM_BCM2708=y + CONFIG_RAW_DRIVER=y ++CONFIG_BRCM_CHAR_DRIVERS=y ++CONFIG_BCM_VC_CMA=y + CONFIG_I2C=y + CONFIG_I2C_CHARDEV=m + CONFIG_I2C_BCM2708=m +@@ -222,9 +493,152 @@ CONFIG_SPI_BCM2708=m + CONFIG_SPI_SPIDEV=m + CONFIG_GPIO_SYSFS=y + # CONFIG_HWMON is not set ++CONFIG_THERMAL=y ++CONFIG_THERMAL_BCM2835=y + CONFIG_WATCHDOG=y + CONFIG_BCM2708_WDT=m +-# CONFIG_MFD_SUPPORT is not set ++CONFIG_MEDIA_SUPPORT=m ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++CONFIG_MEDIA_ANALOG_TV_SUPPORT=y ++CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y ++CONFIG_MEDIA_RADIO_SUPPORT=y ++CONFIG_MEDIA_RC_SUPPORT=y ++CONFIG_MEDIA_CONTROLLER=y ++CONFIG_LIRC=m ++CONFIG_RC_DEVICES=y ++CONFIG_RC_ATI_REMOTE=m ++CONFIG_IR_IMON=m ++CONFIG_IR_MCEUSB=m ++CONFIG_IR_REDRAT3=m ++CONFIG_IR_STREAMZAP=m ++CONFIG_IR_IGUANA=m ++CONFIG_IR_TTUSBIR=m ++CONFIG_RC_LOOPBACK=m ++CONFIG_IR_GPIO_CIR=m ++CONFIG_MEDIA_USB_SUPPORT=y ++CONFIG_USB_VIDEO_CLASS=m ++CONFIG_USB_M5602=m ++CONFIG_USB_STV06XX=m ++CONFIG_USB_GL860=m ++CONFIG_USB_GSPCA_BENQ=m ++CONFIG_USB_GSPCA_CONEX=m ++CONFIG_USB_GSPCA_CPIA1=m ++CONFIG_USB_GSPCA_ETOMS=m ++CONFIG_USB_GSPCA_FINEPIX=m ++CONFIG_USB_GSPCA_JEILINJ=m ++CONFIG_USB_GSPCA_JL2005BCD=m ++CONFIG_USB_GSPCA_KINECT=m ++CONFIG_USB_GSPCA_KONICA=m ++CONFIG_USB_GSPCA_MARS=m ++CONFIG_USB_GSPCA_MR97310A=m ++CONFIG_USB_GSPCA_NW80X=m ++CONFIG_USB_GSPCA_OV519=m ++CONFIG_USB_GSPCA_OV534=m ++CONFIG_USB_GSPCA_OV534_9=m ++CONFIG_USB_GSPCA_PAC207=m ++CONFIG_USB_GSPCA_PAC7302=m ++CONFIG_USB_GSPCA_PAC7311=m ++CONFIG_USB_GSPCA_SE401=m ++CONFIG_USB_GSPCA_SN9C2028=m ++CONFIG_USB_GSPCA_SN9C20X=m ++CONFIG_USB_GSPCA_SONIXB=m ++CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA500=m ++CONFIG_USB_GSPCA_SPCA501=m ++CONFIG_USB_GSPCA_SPCA505=m ++CONFIG_USB_GSPCA_SPCA506=m ++CONFIG_USB_GSPCA_SPCA508=m ++CONFIG_USB_GSPCA_SPCA561=m ++CONFIG_USB_GSPCA_SPCA1528=m ++CONFIG_USB_GSPCA_SQ905=m ++CONFIG_USB_GSPCA_SQ905C=m ++CONFIG_USB_GSPCA_SQ930X=m ++CONFIG_USB_GSPCA_STK014=m ++CONFIG_USB_GSPCA_STV0680=m ++CONFIG_USB_GSPCA_SUNPLUS=m ++CONFIG_USB_GSPCA_T613=m ++CONFIG_USB_GSPCA_TOPRO=m ++CONFIG_USB_GSPCA_TV8532=m ++CONFIG_USB_GSPCA_VC032X=m ++CONFIG_USB_GSPCA_VICAM=m ++CONFIG_USB_GSPCA_XIRLINK_CIT=m ++CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_USB_PWC=m ++CONFIG_VIDEO_CPIA2=m ++CONFIG_USB_ZR364XX=m ++CONFIG_USB_STKWEBCAM=m ++CONFIG_USB_S2255=m ++CONFIG_USB_SN9C102=m ++CONFIG_VIDEO_USBTV=m ++CONFIG_VIDEO_PVRUSB2=m ++CONFIG_VIDEO_HDPVR=m ++CONFIG_VIDEO_TLG2300=m ++CONFIG_VIDEO_USBVISION=m ++CONFIG_VIDEO_STK1160=m ++CONFIG_VIDEO_STK1160_AC97=y ++CONFIG_VIDEO_AU0828=m ++CONFIG_VIDEO_CX231XX=m ++CONFIG_VIDEO_CX231XX_ALSA=m ++CONFIG_VIDEO_CX231XX_DVB=m ++CONFIG_VIDEO_TM6000=m ++CONFIG_VIDEO_TM6000_ALSA=m ++CONFIG_VIDEO_TM6000_DVB=m ++CONFIG_DVB_USB=m ++CONFIG_DVB_USB_A800=m ++CONFIG_DVB_USB_DIBUSB_MB=m ++CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y ++CONFIG_DVB_USB_DIBUSB_MC=m ++CONFIG_DVB_USB_DIB0700=m ++CONFIG_DVB_USB_UMT_010=m ++CONFIG_DVB_USB_CXUSB=m ++CONFIG_DVB_USB_M920X=m ++CONFIG_DVB_USB_DIGITV=m ++CONFIG_DVB_USB_VP7045=m ++CONFIG_DVB_USB_VP702X=m ++CONFIG_DVB_USB_GP8PSK=m ++CONFIG_DVB_USB_NOVA_T_USB2=m ++CONFIG_DVB_USB_TTUSB2=m ++CONFIG_DVB_USB_DTT200U=m ++CONFIG_DVB_USB_OPERA1=m ++CONFIG_DVB_USB_AF9005=m ++CONFIG_DVB_USB_AF9005_REMOTE=m ++CONFIG_DVB_USB_PCTV452E=m ++CONFIG_DVB_USB_DW2102=m ++CONFIG_DVB_USB_CINERGY_T2=m ++CONFIG_DVB_USB_DTV5100=m ++CONFIG_DVB_USB_FRIIO=m ++CONFIG_DVB_USB_AZ6027=m ++CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_USB_V2=m ++CONFIG_DVB_USB_AF9015=m ++CONFIG_DVB_USB_AF9035=m ++CONFIG_DVB_USB_ANYSEE=m ++CONFIG_DVB_USB_AU6610=m ++CONFIG_DVB_USB_AZ6007=m ++CONFIG_DVB_USB_CE6230=m ++CONFIG_DVB_USB_EC168=m ++CONFIG_DVB_USB_GL861=m ++CONFIG_DVB_USB_IT913X=m ++CONFIG_DVB_USB_LME2510=m ++CONFIG_DVB_USB_MXL111SF=m ++CONFIG_DVB_USB_RTL28XXU=m ++CONFIG_SMS_USB_DRV=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m ++CONFIG_VIDEO_EM28XX=m ++CONFIG_VIDEO_EM28XX_ALSA=m ++CONFIG_VIDEO_EM28XX_DVB=m ++CONFIG_RADIO_SI470X=y ++CONFIG_USB_SI470X=m ++CONFIG_USB_MR800=m ++CONFIG_USB_DSBR=m ++CONFIG_RADIO_SHARK=m ++CONFIG_RADIO_SHARK2=m ++CONFIG_RADIO_SI4713=m ++CONFIG_USB_KEENE=m ++CONFIG_USB_MA901=m ++CONFIG_RADIO_SAA7706H=m ++CONFIG_RADIO_TEF6862=m ++CONFIG_RADIO_WL128X=m + CONFIG_FB=y + CONFIG_FB_BCM2708=y + CONFIG_FRAMEBUFFER_CONSOLE=y +@@ -250,9 +664,9 @@ CONFIG_SND_USB_AUDIO=m + CONFIG_SND_USB_UA101=m + CONFIG_SND_USB_CAIAQ=m + CONFIG_SND_USB_6FIRE=m ++CONFIG_SND_USB_HIFACE=m + CONFIG_SOUND_PRIME=m +-CONFIG_HID_PID=y +-CONFIG_USB_HIDDEV=y ++CONFIG_HIDRAW=y + CONFIG_HID_A4TECH=m + CONFIG_HID_ACRUX=m + CONFIG_HID_APPLE=m +@@ -263,6 +677,7 @@ CONFIG_HID_CYPRESS=m + CONFIG_HID_DRAGONRISE=m + CONFIG_HID_EMS_FF=m + CONFIG_HID_ELECOM=m ++CONFIG_HID_ELO=m + CONFIG_HID_EZKEY=m + CONFIG_HID_HOLTEK=m + CONFIG_HID_KEYTOUCH=m +@@ -283,7 +698,6 @@ CONFIG_HID_ORTEK=m + CONFIG_HID_PANTHERLORD=m + CONFIG_HID_PETALYNX=m + CONFIG_HID_PICOLCD=m +-CONFIG_HID_QUANTA=m + CONFIG_HID_ROCCAT=m + CONFIG_HID_SAMSUNG=m + CONFIG_HID_SONY=m +@@ -292,15 +706,19 @@ CONFIG_HID_SUNPLUS=m + CONFIG_HID_GREENASIA=m + CONFIG_HID_SMARTJOYPLUS=m + CONFIG_HID_TOPSEED=m ++CONFIG_HID_THINGM=m + CONFIG_HID_THRUSTMASTER=m + CONFIG_HID_WACOM=m + CONFIG_HID_WIIMOTE=m + CONFIG_HID_ZEROPLUS=m + CONFIG_HID_ZYDACRON=m ++CONFIG_HID_PID=y ++CONFIG_USB_HIDDEV=y + CONFIG_USB=y + CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + CONFIG_USB_MON=m + CONFIG_USB_DWCOTG=y ++CONFIG_USB_PRINTER=m + CONFIG_USB_STORAGE=y + CONFIG_USB_STORAGE_REALTEK=m + CONFIG_USB_STORAGE_DATAFAB=m +@@ -315,8 +733,6 @@ CONFIG_USB_STORAGE_ONETOUCH=m + CONFIG_USB_STORAGE_KARMA=m + CONFIG_USB_STORAGE_CYPRESS_ATACB=m + CONFIG_USB_STORAGE_ENE_UB6250=m +-CONFIG_USB_UAS=m +-CONFIG_USB_LIBUSUAL=y + CONFIG_USB_MDC800=m + CONFIG_USB_MICROTEK=m + CONFIG_USB_SERIAL=m +@@ -337,6 +753,7 @@ CONFIG_USB_SERIAL_IPAQ=m + CONFIG_USB_SERIAL_IR=m + CONFIG_USB_SERIAL_EDGEPORT=m + CONFIG_USB_SERIAL_EDGEPORT_TI=m ++CONFIG_USB_SERIAL_F81232=m + CONFIG_USB_SERIAL_GARMIN=m + CONFIG_USB_SERIAL_IPW=m + CONFIG_USB_SERIAL_IUU=m +@@ -345,6 +762,7 @@ CONFIG_USB_SERIAL_KEYSPAN=m + CONFIG_USB_SERIAL_KLSI=m + CONFIG_USB_SERIAL_KOBIL_SCT=m + CONFIG_USB_SERIAL_MCT_U232=m ++CONFIG_USB_SERIAL_METRO=m + CONFIG_USB_SERIAL_MOS7720=m + CONFIG_USB_SERIAL_MOS7840=m + CONFIG_USB_SERIAL_MOTOROLA=m +@@ -366,8 +784,12 @@ CONFIG_USB_SERIAL_OPTION=m + CONFIG_USB_SERIAL_OMNINET=m + CONFIG_USB_SERIAL_OPTICON=m + CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m ++CONFIG_USB_SERIAL_XSENS_MT=m + CONFIG_USB_SERIAL_ZIO=m ++CONFIG_USB_SERIAL_WISHBONE=m ++CONFIG_USB_SERIAL_ZTE=m + CONFIG_USB_SERIAL_SSU100=m ++CONFIG_USB_SERIAL_QT2=m + CONFIG_USB_SERIAL_DEBUG=m + CONFIG_USB_EMI62=m + CONFIG_USB_EMI26=m +@@ -389,17 +811,60 @@ CONFIG_USB_TEST=m + CONFIG_USB_ISIGHTFW=m + CONFIG_USB_YUREX=m + CONFIG_MMC=y ++CONFIG_MMC_BLOCK_MINORS=32 + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_PLTFM=y + CONFIG_MMC_SDHCI_BCM2708=y + CONFIG_MMC_SDHCI_BCM2708_DMA=y +-CONFIG_LEDS_GPIO=y +-CONFIG_LEDS_TRIGGER_TIMER=m +-CONFIG_LEDS_TRIGGER_HEARTBEAT=m +-CONFIG_LEDS_TRIGGER_DEFAULT_ON=m ++CONFIG_LEDS_GPIO=m ++CONFIG_LEDS_TRIGGER_TIMER=y ++CONFIG_LEDS_TRIGGER_ONESHOT=y ++CONFIG_LEDS_TRIGGER_HEARTBEAT=y ++CONFIG_LEDS_TRIGGER_BACKLIGHT=y ++CONFIG_LEDS_TRIGGER_CPU=y ++CONFIG_LEDS_TRIGGER_GPIO=y ++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y ++CONFIG_LEDS_TRIGGER_TRANSIENT=m ++CONFIG_LEDS_TRIGGER_CAMERA=m ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_DRV_DS1307=m ++CONFIG_RTC_DRV_DS1374=m ++CONFIG_RTC_DRV_DS1672=m ++CONFIG_RTC_DRV_DS3232=m ++CONFIG_RTC_DRV_MAX6900=m ++CONFIG_RTC_DRV_RS5C372=m ++CONFIG_RTC_DRV_ISL1208=m ++CONFIG_RTC_DRV_ISL12022=m ++CONFIG_RTC_DRV_X1205=m ++CONFIG_RTC_DRV_PCF2127=m ++CONFIG_RTC_DRV_PCF8523=m ++CONFIG_RTC_DRV_PCF8563=m ++CONFIG_RTC_DRV_PCF8583=m ++CONFIG_RTC_DRV_M41T80=m ++CONFIG_RTC_DRV_BQ32K=m ++CONFIG_RTC_DRV_S35390A=m ++CONFIG_RTC_DRV_FM3130=m ++CONFIG_RTC_DRV_RX8581=m ++CONFIG_RTC_DRV_RX8025=m ++CONFIG_RTC_DRV_EM3027=m ++CONFIG_RTC_DRV_RV3029C2=m ++CONFIG_RTC_DRV_M41T93=m ++CONFIG_RTC_DRV_M41T94=m ++CONFIG_RTC_DRV_DS1305=m ++CONFIG_RTC_DRV_DS1390=m ++CONFIG_RTC_DRV_MAX6902=m ++CONFIG_RTC_DRV_R9701=m ++CONFIG_RTC_DRV_RS5C348=m ++CONFIG_RTC_DRV_DS3234=m ++CONFIG_RTC_DRV_PCF2123=m ++CONFIG_RTC_DRV_RX4581=m + CONFIG_UIO=m + CONFIG_UIO_PDRV=m + CONFIG_UIO_PDRV_GENIRQ=m ++CONFIG_STAGING=y ++CONFIG_STAGING_MEDIA=y ++CONFIG_LIRC_STAGING=y ++CONFIG_LIRC_RPI=m + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_EXT4_FS=y + CONFIG_EXT4_FS_POSIX_ACL=y +@@ -422,6 +887,8 @@ CONFIG_BTRFS_FS=m + CONFIG_BTRFS_FS_POSIX_ACL=y + CONFIG_NILFS2_FS=m + CONFIG_FANOTIFY=y ++CONFIG_QFMT_V1=m ++CONFIG_QFMT_V2=m + CONFIG_AUTOFS4_FS=y + CONFIG_FUSE_FS=m + CONFIG_CUSE=m +@@ -444,21 +911,22 @@ CONFIG_SQUASHFS=m + CONFIG_SQUASHFS_XATTR=y + CONFIG_SQUASHFS_LZO=y + CONFIG_SQUASHFS_XZ=y ++CONFIG_F2FS_FS=y + CONFIG_NFS_FS=y +-CONFIG_NFS_V3=y + CONFIG_NFS_V3_ACL=y + CONFIG_NFS_V4=y + CONFIG_ROOT_NFS=y + CONFIG_NFS_FSCACHE=y ++CONFIG_NFSD=m ++CONFIG_NFSD_V3_ACL=y ++CONFIG_NFSD_V4=y + CONFIG_CIFS=m + CONFIG_CIFS_WEAK_PW_HASH=y + CONFIG_CIFS_XATTR=y + CONFIG_CIFS_POSIX=y + CONFIG_9P_FS=m + CONFIG_9P_FS_POSIX_ACL=y +-CONFIG_PARTITION_ADVANCED=y +-CONFIG_MAC_PARTITION=y +-CONFIG_EFI_PARTITION=y ++CONFIG_9P_FS_SECURITY=y + CONFIG_NLS_DEFAULT="utf8" + CONFIG_NLS_CODEPAGE_437=y + CONFIG_NLS_CODEPAGE_737=m +@@ -498,15 +966,15 @@ CONFIG_NLS_ISO8859_15=m + CONFIG_NLS_KOI8_R=m + CONFIG_NLS_KOI8_U=m + CONFIG_NLS_UTF8=m ++CONFIG_DLM=m + CONFIG_PRINTK_TIME=y +-CONFIG_DETECT_HUNG_TASK=y +-CONFIG_TIMER_STATS=y +-CONFIG_DEBUG_STACK_USAGE=y ++CONFIG_BOOT_PRINTK_DELAY=y + CONFIG_DEBUG_INFO=y ++CONFIG_DEBUG_STACK_USAGE=y + CONFIG_DEBUG_MEMORY_INIT=y +-CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_TIMER_STATS=y + CONFIG_LATENCYTOP=y +-CONFIG_SYSCTL_SYSCALL_CHECK=y + CONFIG_IRQSOFF_TRACER=y + CONFIG_SCHED_TRACER=y + CONFIG_STACK_TRACER=y +@@ -516,20 +984,17 @@ CONFIG_KGDB=y + CONFIG_KGDB_KDB=y + CONFIG_KDB_KEYBOARD=y + CONFIG_STRICT_DEVMEM=y +-CONFIG_CRYPTO_AUTHENC=m + CONFIG_CRYPTO_SEQIV=m + CONFIG_CRYPTO_CBC=y + CONFIG_CRYPTO_HMAC=y + CONFIG_CRYPTO_XCBC=m + CONFIG_CRYPTO_MD5=y + CONFIG_CRYPTO_SHA1=y +-CONFIG_CRYPTO_SHA256=m + CONFIG_CRYPTO_SHA512=m + CONFIG_CRYPTO_TGR192=m + CONFIG_CRYPTO_WP512=m + CONFIG_CRYPTO_CAST5=m + CONFIG_CRYPTO_DES=y +-CONFIG_CRYPTO_DEFLATE=m + # CONFIG_CRYPTO_ANSI_CPRNG is not set + # CONFIG_CRYPTO_HW is not set + CONFIG_CRC_ITU_T=y +-- +1.8.4 + + +From 4995fa0e671e5e20d298e46b38cccd0ddff72b8d Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 8 Apr 2013 21:12:48 +0100 -Subject: [PATCH 35/98] Add NAK holdoff scheme. Enabled by default, disable +Subject: [PATCH 34/82] Add NAK holdoff scheme. Enabled by default, disable with dwc_otg.nak_holdoff_enable=0. Thanks gsh --- @@ -89714,10 +91109,10 @@ index a9dea55..ebee73a 100644 1.8.4 -From f2f2f5c42537dc8af901f3b7dede5fa51c0b01ef Mon Sep 17 00:00:00 2001 +From 207d67ce894d7e8040f568ebf557856e19475bee Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 26 Mar 2013 19:24:24 +0000 -Subject: [PATCH 36/98] Added hwmon/thermal driver for reporting core +Subject: [PATCH 35/82] Added hwmon/thermal driver for reporting core temperature. Thanks Dorian --- @@ -89733,10 +91128,10 @@ Subject: [PATCH 36/98] Added hwmon/thermal driver for reporting core create mode 100644 drivers/thermal/bcm2835-thermal.c diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 6bf738a..a3a5333 100644 +index dd73b81..a82d5bd 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -557,6 +557,14 @@ struct platform_device bcm2708_powerman_device = { +@@ -567,6 +567,14 @@ struct platform_device bcm2708_powerman_device = { .resource = bcm2708_bsc1_resources, }; @@ -89751,7 +91146,7 @@ index 6bf738a..a3a5333 100644 int __init bcm_register_device(struct platform_device *pdev) { int ret; -@@ -623,6 +631,9 @@ void __init bcm2708_init(void) +@@ -690,6 +698,9 @@ void __init bcm2708_init(void) bcm_register_device(&bcm2708_bsc0_device); bcm_register_device(&bcm2708_bsc1_device); @@ -89762,10 +91157,10 @@ index 6bf738a..a3a5333 100644 struct amba_device *d = amba_devs[i]; amba_device_register(d, &iomem_resource); diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig -index e989f7f..9447135 100644 +index b3ab9d4..d60bc7f 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig -@@ -1543,6 +1543,16 @@ config SENSORS_MC13783_ADC +@@ -1553,6 +1553,16 @@ config SENSORS_MC13783_ADC help Support for the A/D converter on MC13783 and MC13892 PMIC. @@ -89783,10 +91178,10 @@ index e989f7f..9447135 100644 comment "ACPI drivers" diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile -index 4f0fb52..4c22d31 100644 +index ec7cde0..a06e078 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile -@@ -141,6 +141,7 @@ obj-$(CONFIG_SENSORS_W83L785TS) += w83l785ts.o +@@ -142,6 +142,7 @@ obj-$(CONFIG_SENSORS_W83L785TS) += w83l785ts.o obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o @@ -90020,10 +91415,10 @@ index 0000000..5bbed45 + +module_platform_driver(bcm2835_hwmon_driver); diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig -index e988c81..724f06c 100644 +index dbfc390..8d3c280 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig -@@ -169,6 +169,12 @@ config INTEL_POWERCLAMP +@@ -181,6 +181,12 @@ config INTEL_POWERCLAMP enforce idle time which results in more package C-state residency. The user interface is exposed via generic thermal framework. @@ -90037,11 +91432,11 @@ index e988c81..724f06c 100644 tristate "X86 package temperature thermal driver" depends on X86_THERMAL_VECTOR diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile -index 67184a2..ea5ef4d 100644 +index 584b363..97e5a03 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile -@@ -23,5 +23,6 @@ obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o - obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o +@@ -27,5 +27,6 @@ obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o + obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o +obj-$(CONFIG_THERMAL_BCM2835) += bcm2835-thermal.o @@ -90265,499 +91660,20 @@ index 0000000..3f9a733 1.8.4 -From 78eb99419ecbc288ab57ac8b1c777e5189d4c228 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Wed, 4 Sep 2013 21:49:26 +0100 -Subject: [PATCH 37/98] Add config options - -Increase to CONFIG_MMC_BLOCK_MINORS=32 -and enable CONFIG_JUMP_LABEL -See: https://github.com/raspberrypi/linux/pull/348 - -Move to SLUB memory allocator. -See: https://github.com/raspberrypi/linux/pull/349 ---- - arch/arm/configs/bcmrpi_defconfig | 273 ++++++++++++-------------------------- - 1 file changed, 83 insertions(+), 190 deletions(-) - -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 5b0a171..fdda50b 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -1,12 +1,17 @@ - # CONFIG_ARM_PATCH_PHYS_VIRT is not set --CONFIG_EXPERIMENTAL=y - # CONFIG_LOCALVERSION_AUTO is not set - CONFIG_SYSVIPC=y - CONFIG_POSIX_MQUEUE=y --CONFIG_BSD_PROCESS_ACCT=y --CONFIG_BSD_PROCESS_ACCT_V3=y - CONFIG_FHANDLE=y - CONFIG_AUDIT=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_BSD_PROCESS_ACCT=y -+CONFIG_BSD_PROCESS_ACCT_V3=y -+CONFIG_TASKSTATS=y -+CONFIG_TASK_DELAY_ACCT=y -+CONFIG_TASK_XACCT=y -+CONFIG_TASK_IO_ACCOUNTING=y - CONFIG_IKCONFIG=y - CONFIG_IKCONFIG_PROC=y - CONFIG_CGROUP_FREEZER=y -@@ -18,20 +23,20 @@ CONFIG_NAMESPACES=y - CONFIG_SCHED_AUTOGROUP=y - CONFIG_EMBEDDED=y - # CONFIG_COMPAT_BRK is not set --CONFIG_SLAB=y - CONFIG_PROFILING=y - CONFIG_OPROFILE=m - CONFIG_KPROBES=y -+CONFIG_JUMP_LABEL=y - CONFIG_MODULES=y - CONFIG_MODULE_UNLOAD=y - CONFIG_MODVERSIONS=y - CONFIG_MODULE_SRCVERSION_ALL=y - # CONFIG_BLK_DEV_BSG is not set - CONFIG_BLK_DEV_THROTTLING=y -+CONFIG_PARTITION_ADVANCED=y -+CONFIG_MAC_PARTITION=y - CONFIG_CFQ_GROUP_IOSCHED=y - CONFIG_ARCH_BCM2708=y --CONFIG_NO_HZ=y --CONFIG_HIGH_RES_TIMERS=y - CONFIG_AEABI=y - CONFIG_SECCOMP=y - CONFIG_CC_STACKPROTECTOR=y -@@ -41,9 +46,10 @@ CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,11520 - CONFIG_KEXEC=y - CONFIG_CPU_FREQ=y - CONFIG_CPU_FREQ_STAT=m --CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y --CONFIG_CPU_FREQ_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y - CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_ONDEMAND=y - CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y - CONFIG_CPU_IDLE=y - CONFIG_VFP=y -@@ -97,10 +103,8 @@ CONFIG_NETFILTER_XT_TARGET_AUDIT=m - CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m - CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m - CONFIG_NETFILTER_XT_TARGET_CONNMARK=m --CONFIG_NETFILTER_XT_TARGET_CT=m - CONFIG_NETFILTER_XT_TARGET_DSCP=m - CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m --CONFIG_NETFILTER_XT_TARGET_LED=m - CONFIG_NETFILTER_XT_TARGET_MARK=m - CONFIG_NETFILTER_XT_TARGET_NFLOG=m - CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -@@ -166,12 +170,7 @@ CONFIG_IP_NF_MATCH_ECN=m - CONFIG_IP_NF_MATCH_TTL=m - CONFIG_IP_NF_FILTER=m - CONFIG_IP_NF_TARGET_REJECT=m --CONFIG_IP_NF_TARGET_LOG=m - CONFIG_IP_NF_TARGET_ULOG=m --CONFIG_NF_NAT=m --CONFIG_IP_NF_TARGET_MASQUERADE=m --CONFIG_IP_NF_TARGET_NETMAP=m --CONFIG_IP_NF_TARGET_REDIRECT=m - CONFIG_IP_NF_MANGLE=m - CONFIG_IP_NF_TARGET_ECN=m - CONFIG_IP_NF_TARGET_TTL=m -@@ -190,7 +189,6 @@ CONFIG_IP6_NF_MATCH_IPV6HEADER=m - CONFIG_IP6_NF_MATCH_MH=m - CONFIG_IP6_NF_MATCH_RT=m - CONFIG_IP6_NF_TARGET_HL=m --CONFIG_IP6_NF_TARGET_LOG=m - CONFIG_IP6_NF_FILTER=m - CONFIG_IP6_NF_TARGET_REJECT=m - CONFIG_IP6_NF_MANGLE=m -@@ -217,6 +215,7 @@ CONFIG_BRIDGE_EBT_SNAT=m - CONFIG_BRIDGE_EBT_LOG=m - CONFIG_BRIDGE_EBT_ULOG=m - CONFIG_BRIDGE_EBT_NFLOG=m -+CONFIG_L2TP=m - CONFIG_BRIDGE=m - CONFIG_VLAN_8021Q=m - CONFIG_VLAN_8021Q_GVRP=y -@@ -280,8 +279,6 @@ CONFIG_USB_IRDA=m - CONFIG_SIGMATEL_FIR=m - CONFIG_MCS_FIR=m - CONFIG_BT=m --CONFIG_BT_L2CAP=y --CONFIG_BT_SCO=y - CONFIG_BT_RFCOMM=m - CONFIG_BT_RFCOMM_TTY=y - CONFIG_BT_BNEP=m -@@ -313,7 +310,6 @@ CONFIG_BLK_DEV_DRBD=m - CONFIG_BLK_DEV_NBD=m - CONFIG_BLK_DEV_RAM=y - CONFIG_CDROM_PKTCDVD=m --CONFIG_MISC_DEVICES=y - CONFIG_SCSI=y - # CONFIG_SCSI_PROC_FS is not set - CONFIG_BLK_DEV_SD=m -@@ -322,44 +318,16 @@ CONFIG_SCSI_MULTI_LUN=y - # CONFIG_SCSI_LOWLEVEL is not set - CONFIG_MD=y - CONFIG_NETDEVICES=y -+CONFIG_NETCONSOLE=m - CONFIG_TUN=m --CONFIG_PHYLIB=m - CONFIG_MDIO_BITBANG=m --CONFIG_NET_ETHERNET=y --# CONFIG_NETDEV_1000 is not set --# CONFIG_NETDEV_10000 is not set --CONFIG_LIBERTAS_THINFIRM=m --CONFIG_LIBERTAS_THINFIRM_USB=m --CONFIG_AT76C50X_USB=m --CONFIG_USB_ZD1201=m --CONFIG_USB_NET_RNDIS_WLAN=m --CONFIG_RTL8187=m --CONFIG_MAC80211_HWSIM=m --CONFIG_ATH_COMMON=m --CONFIG_ATH9K=m --CONFIG_ATH9K_HTC=m --CONFIG_CARL9170=m --CONFIG_B43=m --CONFIG_B43LEGACY=m --CONFIG_HOSTAP=m --CONFIG_IWM=m --CONFIG_LIBERTAS=m --CONFIG_LIBERTAS_USB=m --CONFIG_LIBERTAS_SDIO=m --CONFIG_P54_COMMON=m --CONFIG_P54_USB=m --CONFIG_RT2X00=m --CONFIG_RT2500USB=m --CONFIG_RT73USB=m --CONFIG_RT2800USB=m --CONFIG_RT2800USB_RT53XX=y --CONFIG_WL1251=m --CONFIG_WL12XX_MENU=m --CONFIG_ZD1211RW=m --CONFIG_MWIFIEX=m --CONFIG_MWIFIEX_SDIO=m --CONFIG_RTL8192CU=m --CONFIG_WIMAX_I2400M_USB=m -+CONFIG_PPP=m -+CONFIG_PPP_BSDCOMP=m -+CONFIG_PPP_DEFLATE=m -+CONFIG_PPP_ASYNC=m -+CONFIG_PPP_SYNC_TTY=m -+CONFIG_SLIP=m -+CONFIG_SLIP_COMPRESSED=y - CONFIG_USB_CATC=m - CONFIG_USB_KAWETH=m - CONFIG_USB_PEGASUS=m -@@ -386,14 +354,32 @@ CONFIG_USB_NET_INT51X1=m - CONFIG_USB_IPHETH=m - CONFIG_USB_SIERRA_NET=m - CONFIG_USB_VL600=m --CONFIG_PPP=m --CONFIG_PPP_ASYNC=m --CONFIG_PPP_SYNC_TTY=m --CONFIG_PPP_DEFLATE=m --CONFIG_PPP_BSDCOMP=m --CONFIG_SLIP=m --CONFIG_SLIP_COMPRESSED=y --CONFIG_NETCONSOLE=m -+CONFIG_LIBERTAS_THINFIRM=m -+CONFIG_LIBERTAS_THINFIRM_USB=m -+CONFIG_AT76C50X_USB=m -+CONFIG_USB_ZD1201=m -+CONFIG_USB_NET_RNDIS_WLAN=m -+CONFIG_RTL8187=m -+CONFIG_MAC80211_HWSIM=m -+CONFIG_B43=m -+CONFIG_B43LEGACY=m -+CONFIG_HOSTAP=m -+CONFIG_LIBERTAS=m -+CONFIG_LIBERTAS_USB=m -+CONFIG_LIBERTAS_SDIO=m -+CONFIG_P54_COMMON=m -+CONFIG_P54_USB=m -+CONFIG_RT2X00=m -+CONFIG_RT2500USB=m -+CONFIG_RT73USB=m -+CONFIG_RT2800USB=m -+CONFIG_RT2800USB_RT53XX=y -+CONFIG_RT2800USB_UNKNOWN=y -+CONFIG_ZD1211RW=m -+CONFIG_MWIFIEX=m -+CONFIG_MWIFIEX_SDIO=m -+CONFIG_RTL8192CU=m -+CONFIG_WIMAX_I2400M_USB=m - CONFIG_INPUT_POLLDEV=m - # CONFIG_INPUT_MOUSEDEV_PSAUX is not set - CONFIG_INPUT_JOYDEV=m -@@ -402,7 +388,6 @@ CONFIG_INPUT_EVDEV=m - # CONFIG_INPUT_MOUSE is not set - CONFIG_INPUT_MISC=y - CONFIG_INPUT_AD714X=m --CONFIG_INPUT_ATI_REMOTE=m - CONFIG_INPUT_ATI_REMOTE2=m - CONFIG_INPUT_KEYSPAN_REMOTE=m - CONFIG_INPUT_POWERMATE=m -@@ -432,118 +417,11 @@ CONFIG_SPI_BCM2708=m - CONFIG_SPI_SPIDEV=m - CONFIG_GPIO_SYSFS=y - # CONFIG_HWMON is not set -+CONFIG_THERMAL=y -+CONFIG_THERMAL_BCM2835=y - CONFIG_WATCHDOG=y - CONFIG_BCM2708_WDT=m - CONFIG_MEDIA_SUPPORT=m --CONFIG_VIDEO_DEV=m --CONFIG_DVB_CORE=m --CONFIG_RC_ATI_REMOTE=m --CONFIG_IR_IMON=m --CONFIG_IR_MCEUSB=m --CONFIG_IR_REDRAT3=m --CONFIG_IR_STREAMZAP=m --CONFIG_RC_LOOPBACK=m --CONFIG_MEDIA_ATTACH=y --CONFIG_USB_VIDEO_CLASS=m --CONFIG_USB_M5602=m --CONFIG_USB_STV06XX=m --CONFIG_USB_GL860=m --CONFIG_USB_GSPCA_BENQ=m --CONFIG_USB_GSPCA_CONEX=m --CONFIG_USB_GSPCA_CPIA1=m --CONFIG_USB_GSPCA_ETOMS=m --CONFIG_USB_GSPCA_FINEPIX=m --CONFIG_USB_GSPCA_JEILINJ=m --CONFIG_USB_GSPCA_KINECT=m --CONFIG_USB_GSPCA_KONICA=m --CONFIG_USB_GSPCA_MARS=m --CONFIG_USB_GSPCA_MR97310A=m --CONFIG_USB_GSPCA_NW80X=m --CONFIG_USB_GSPCA_OV519=m --CONFIG_USB_GSPCA_OV534=m --CONFIG_USB_GSPCA_OV534_9=m --CONFIG_USB_GSPCA_PAC207=m --CONFIG_USB_GSPCA_PAC7302=m --CONFIG_USB_GSPCA_PAC7311=m --CONFIG_USB_GSPCA_SE401=m --CONFIG_USB_GSPCA_SN9C2028=m --CONFIG_USB_GSPCA_SN9C20X=m --CONFIG_USB_GSPCA_SONIXB=m --CONFIG_USB_GSPCA_SONIXJ=m --CONFIG_USB_GSPCA_SPCA500=m --CONFIG_USB_GSPCA_SPCA501=m --CONFIG_USB_GSPCA_SPCA505=m --CONFIG_USB_GSPCA_SPCA506=m --CONFIG_USB_GSPCA_SPCA508=m --CONFIG_USB_GSPCA_SPCA561=m --CONFIG_USB_GSPCA_SPCA1528=m --CONFIG_USB_GSPCA_SQ905=m --CONFIG_USB_GSPCA_SQ905C=m --CONFIG_USB_GSPCA_SQ930X=m --CONFIG_USB_GSPCA_STK014=m --CONFIG_USB_GSPCA_STV0680=m --CONFIG_USB_GSPCA_SUNPLUS=m --CONFIG_USB_GSPCA_T613=m --CONFIG_USB_GSPCA_TV8532=m --CONFIG_USB_GSPCA_VC032X=m --CONFIG_USB_GSPCA_VICAM=m --CONFIG_USB_GSPCA_XIRLINK_CIT=m --CONFIG_USB_GSPCA_ZC3XX=m --CONFIG_VIDEO_PVRUSB2=m --CONFIG_VIDEO_HDPVR=m --CONFIG_VIDEO_EM28XX=m --CONFIG_VIDEO_EM28XX_ALSA=m --CONFIG_VIDEO_EM28XX_DVB=m --CONFIG_VIDEO_TLG2300=m --CONFIG_VIDEO_CX231XX=m --CONFIG_VIDEO_CX231XX_ALSA=m --CONFIG_VIDEO_CX231XX_DVB=m --CONFIG_VIDEO_USBVISION=m --CONFIG_USB_ET61X251=m --CONFIG_USB_SN9C102=m --CONFIG_USB_PWC=m --CONFIG_USB_ZR364XX=m --CONFIG_USB_STKWEBCAM=m --CONFIG_USB_S2255=m --CONFIG_USB_DSBR=m --CONFIG_RADIO_SI470X=y --CONFIG_USB_SI470X=m --CONFIG_USB_MR800=m --CONFIG_DVB_USB=m --CONFIG_DVB_USB_A800=m --CONFIG_DVB_USB_DIBUSB_MB=m --CONFIG_DVB_USB_DIBUSB_MC=m --CONFIG_DVB_USB_DIB0700=m --CONFIG_DVB_USB_UMT_010=m --CONFIG_DVB_USB_CXUSB=m --CONFIG_DVB_USB_M920X=m --CONFIG_DVB_USB_GL861=m --CONFIG_DVB_USB_AU6610=m --CONFIG_DVB_USB_DIGITV=m --CONFIG_DVB_USB_VP7045=m --CONFIG_DVB_USB_VP702X=m --CONFIG_DVB_USB_GP8PSK=m --CONFIG_DVB_USB_NOVA_T_USB2=m --CONFIG_DVB_USB_TTUSB2=m --CONFIG_DVB_USB_DTT200U=m --CONFIG_DVB_USB_OPERA1=m --CONFIG_DVB_USB_AF9005=m --CONFIG_DVB_USB_AF9005_REMOTE=m --CONFIG_DVB_USB_DW2102=m --CONFIG_DVB_USB_CINERGY_T2=m --CONFIG_DVB_USB_ANYSEE=m --CONFIG_DVB_USB_DTV5100=m --CONFIG_DVB_USB_AF9015=m --CONFIG_DVB_USB_CE6230=m --CONFIG_DVB_USB_FRIIO=m --CONFIG_DVB_USB_EC168=m --CONFIG_DVB_USB_AZ6027=m --CONFIG_DVB_USB_LME2510=m --CONFIG_DVB_USB_TECHNISAT_USB2=m --CONFIG_SMS_SIANO_MDTV=m --CONFIG_SMS_USB_DRV=m --CONFIG_DVB_B2C2_FLEXCOP=m --CONFIG_DVB_B2C2_FLEXCOP_USB=m - CONFIG_FB=y - CONFIG_FB_BCM2708=y - CONFIG_FRAMEBUFFER_CONSOLE=y -@@ -570,8 +448,6 @@ CONFIG_SND_USB_UA101=m - CONFIG_SND_USB_CAIAQ=m - CONFIG_SND_USB_6FIRE=m - CONFIG_SOUND_PRIME=m --CONFIG_HID_PID=y --CONFIG_USB_HIDDEV=y - CONFIG_HID_A4TECH=m - CONFIG_HID_ACRUX=m - CONFIG_HID_APPLE=m -@@ -602,7 +478,6 @@ CONFIG_HID_ORTEK=m - CONFIG_HID_PANTHERLORD=m - CONFIG_HID_PETALYNX=m - CONFIG_HID_PICOLCD=m --CONFIG_HID_QUANTA=m - CONFIG_HID_ROCCAT=m - CONFIG_HID_SAMSUNG=m - CONFIG_HID_SONY=m -@@ -612,10 +487,10 @@ CONFIG_HID_GREENASIA=m - CONFIG_HID_SMARTJOYPLUS=m - CONFIG_HID_TOPSEED=m - CONFIG_HID_THRUSTMASTER=m --CONFIG_HID_WACOM=m --CONFIG_HID_WIIMOTE=m - CONFIG_HID_ZEROPLUS=m - CONFIG_HID_ZYDACRON=m -+CONFIG_HID_PID=y -+CONFIG_USB_HIDDEV=y - CONFIG_USB=y - CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - CONFIG_USB_MON=m -@@ -634,8 +509,6 @@ CONFIG_USB_STORAGE_ONETOUCH=m - CONFIG_USB_STORAGE_KARMA=m - CONFIG_USB_STORAGE_CYPRESS_ATACB=m - CONFIG_USB_STORAGE_ENE_UB6250=m --CONFIG_USB_UAS=m --CONFIG_USB_LIBUSUAL=y - CONFIG_USB_MDC800=m - CONFIG_USB_MICROTEK=m - CONFIG_USB_SERIAL=m -@@ -708,14 +581,40 @@ CONFIG_USB_TEST=m - CONFIG_USB_ISIGHTFW=m - CONFIG_USB_YUREX=m - CONFIG_MMC=y -+CONFIG_MMC_BLOCK_MINORS=32 - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_PLTFM=y - CONFIG_MMC_SDHCI_BCM2708=y - CONFIG_MMC_SDHCI_BCM2708_DMA=y --CONFIG_LEDS_GPIO=y --CONFIG_LEDS_TRIGGER_TIMER=m --CONFIG_LEDS_TRIGGER_HEARTBEAT=m --CONFIG_LEDS_TRIGGER_DEFAULT_ON=m -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_DRV_DS1307=m -+CONFIG_RTC_DRV_DS1374=m -+CONFIG_RTC_DRV_DS1672=m -+CONFIG_RTC_DRV_DS3232=m -+CONFIG_RTC_DRV_MAX6900=m -+CONFIG_RTC_DRV_RS5C372=m -+CONFIG_RTC_DRV_ISL1208=m -+CONFIG_RTC_DRV_ISL12022=m -+CONFIG_RTC_DRV_X1205=m -+CONFIG_RTC_DRV_PCF8563=m -+CONFIG_RTC_DRV_PCF8583=m -+CONFIG_RTC_DRV_M41T80=m -+CONFIG_RTC_DRV_BQ32K=m -+CONFIG_RTC_DRV_S35390A=m -+CONFIG_RTC_DRV_FM3130=m -+CONFIG_RTC_DRV_RX8581=m -+CONFIG_RTC_DRV_RX8025=m -+CONFIG_RTC_DRV_EM3027=m -+CONFIG_RTC_DRV_RV3029C2=m -+CONFIG_RTC_DRV_M41T93=m -+CONFIG_RTC_DRV_M41T94=m -+CONFIG_RTC_DRV_DS1305=m -+CONFIG_RTC_DRV_DS1390=m -+CONFIG_RTC_DRV_MAX6902=m -+CONFIG_RTC_DRV_R9701=m -+CONFIG_RTC_DRV_RS5C348=m -+CONFIG_RTC_DRV_DS3234=m -+CONFIG_RTC_DRV_PCF2123=m - CONFIG_UIO=m - CONFIG_UIO_PDRV=m - CONFIG_UIO_PDRV_GENIRQ=m -@@ -764,7 +663,6 @@ CONFIG_SQUASHFS_XATTR=y - CONFIG_SQUASHFS_LZO=y - CONFIG_SQUASHFS_XZ=y - CONFIG_NFS_FS=y --CONFIG_NFS_V3=y - CONFIG_NFS_V3_ACL=y - CONFIG_NFS_V4=y - CONFIG_ROOT_NFS=y -@@ -778,9 +676,6 @@ CONFIG_CIFS_XATTR=y - CONFIG_CIFS_POSIX=y - CONFIG_9P_FS=m - CONFIG_9P_FS_POSIX_ACL=y --CONFIG_PARTITION_ADVANCED=y --CONFIG_MAC_PARTITION=y --CONFIG_EFI_PARTITION=y - CONFIG_NLS_DEFAULT="utf8" - CONFIG_NLS_CODEPAGE_437=y - CONFIG_NLS_CODEPAGE_737=m -@@ -828,7 +723,6 @@ CONFIG_DEBUG_INFO=y - CONFIG_DEBUG_MEMORY_INIT=y - CONFIG_BOOT_PRINTK_DELAY=y - CONFIG_LATENCYTOP=y --CONFIG_SYSCTL_SYSCALL_CHECK=y - CONFIG_IRQSOFF_TRACER=y - CONFIG_SCHED_TRACER=y - CONFIG_STACK_TRACER=y -@@ -844,7 +738,6 @@ CONFIG_CRYPTO_HMAC=y - CONFIG_CRYPTO_XCBC=m - CONFIG_CRYPTO_MD5=y - CONFIG_CRYPTO_SHA1=y --CONFIG_CRYPTO_SHA256=m - CONFIG_CRYPTO_SHA512=m - CONFIG_CRYPTO_TGR192=m - CONFIG_CRYPTO_WP512=m --- -1.8.4 - - -From 91b3d218bc17bce57c7e99c88c9f82c805e69fdf Mon Sep 17 00:00:00 2001 +From fe149eba8c774155801f10e8295f1ce4117a3329 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 17 Apr 2013 12:16:36 +0100 -Subject: [PATCH 38/98] Enable multiple ALSA channels +Subject: [PATCH 36/82] Enable multiple ALSA channels --- arch/arm/mach-bcm2708/bcm2708.c | 54 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 48 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index a3a5333..e010515 100644 +index a82d5bd..a388dd8 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -470,12 +470,54 @@ struct platform_device bcm2708_powerman_device = { +@@ -476,12 +476,54 @@ struct platform_device bcm2708_powerman_device = { static struct platform_device bcm2708_alsa_devices[] = { @@ -90822,88 +91738,10 @@ index a3a5333..e010515 100644 1.8.4 -From d6237e975e005f8c38aa9efe914c82ec3d9251a1 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Wed, 3 Oct 2012 20:08:19 +0100 -Subject: [PATCH 39/98] set i2c speed via module-parameter or menuconfig. - Thanks FrankBoesing - ---- - drivers/i2c/busses/Kconfig | 11 +++++++++++ - drivers/i2c/busses/i2c-bcm2708.c | 12 ++++++++---- - 2 files changed, 19 insertions(+), 4 deletions(-) - -diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig -index 74b03eb..6d40a22 100644 ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -353,6 +353,17 @@ config I2C_BCM2708 - support for the BCM2708. BSC is a Broadcom proprietary bus compatible - with I2C/TWI/SMBus. - -+config I2C_BCM2708_BAUDRATE -+ prompt "BCM2708 I2C baudrate" -+ depends on I2C_BCM2708 -+ int -+ default 100000 -+ help -+ Set the I2C baudrate. This will alter the default value. A -+ different baudrate can be set by using a module parameter as well. If -+ no parameter is provided when loading, this is the value that will be -+ used. -+ - config I2C_BLACKFIN_TWI - tristate "Blackfin TWI I2C support" - depends on BLACKFIN -diff --git a/drivers/i2c/busses/i2c-bcm2708.c b/drivers/i2c/busses/i2c-bcm2708.c -index 4d451a4..ac9df18 100644 ---- a/drivers/i2c/busses/i2c-bcm2708.c -+++ b/drivers/i2c/busses/i2c-bcm2708.c -@@ -66,11 +66,15 @@ - #define BSC_S_DONE 0x00000002 - #define BSC_S_TA 0x00000001 - --#define I2C_CLOCK_HZ 100000 /* FIXME: get from DT */ - #define I2C_TIMEOUT_MS 150 - - #define DRV_NAME "bcm2708_i2c" - -+static unsigned int baudrate = CONFIG_I2C_BCM2708_BAUDRATE; -+module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP); -+MODULE_PARM_DESC(baudrate, "The I2C baudrate"); -+ -+ - struct bcm2708_i2c { - struct i2c_adapter adapter; - -@@ -148,7 +152,7 @@ static inline void bcm2708_bsc_setup(struct bcm2708_i2c *bi) - u32 c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_ST | BSC_C_CLEAR_1; - - bus_hz = clk_get_rate(bi->clk); -- cdiv = bus_hz / I2C_CLOCK_HZ; -+ cdiv = bus_hz / baudrate; - - if (bi->msg->flags & I2C_M_RD) - c |= BSC_C_INTR | BSC_C_READ; -@@ -331,8 +335,8 @@ static int bcm2708_i2c_probe(struct platform_device *pdev) - goto out_free_irq; - } - -- dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d)\n", -- pdev->id, (unsigned long)regs->start, irq); -+ dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d) (baudrate %dk)\n", -+ pdev->id, (unsigned long)regs->start, irq, baudrate/1000); - - return 0; - --- -1.8.4 - - -From f34f6a03f8deb2ffa48ce71b0a863c70c62e0f16 Mon Sep 17 00:00:00 2001 +From a1720b532066d483873e72fa2c597cd9e8e1bfe3 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Oct 2012 21:31:48 +0100 -Subject: [PATCH 40/98] Allow the number of cycles delay between sdcard +Subject: [PATCH 37/82] Allow the number of cycles delay between sdcard peripheral writes to be specified on command line with sdhci-bcm2708.cycle_delay @@ -90912,7 +91750,7 @@ Subject: [PATCH 40/98] Allow the number of cycles delay between sdcard 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-bcm2708.c b/drivers/mmc/host/sdhci-bcm2708.c -index 6263977..499d1a8 100644 +index 6dacdb3..dcaefcd 100644 --- a/drivers/mmc/host/sdhci-bcm2708.c +++ b/drivers/mmc/host/sdhci-bcm2708.c @@ -77,6 +77,8 @@ @@ -90945,20 +91783,20 @@ index 6263977..499d1a8 100644 1.8.4 -From 36d5a52753988822d3c86dcb8a197625ef5281bb Mon Sep 17 00:00:00 2001 +From 686663ae52d94a9e15ea2cde8171d2b819a5f319 Mon Sep 17 00:00:00 2001 From: dero Date: Mon, 19 Nov 2012 12:46:06 +0100 -Subject: [PATCH 41/98] Lazy CRC quirk: Implemented retrying mechanisms for SD +Subject: [PATCH 38/82] Lazy CRC quirk: Implemented retrying mechanisms for SD SSR and SCR, disabled missing_status and spurious CRC ACMD51 quirks by default (should be fixed by the retrying-mechanishm) --- - drivers/mmc/core/sd.c | 111 ++++++++++++++++++++++++++++++++++----- + drivers/mmc/core/sd.c | 110 ++++++++++++++++++++++++++++++++++----- drivers/mmc/host/sdhci-bcm2708.c | 11 +++- - 2 files changed, 106 insertions(+), 16 deletions(-) + 2 files changed, 106 insertions(+), 15 deletions(-) diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c -index 176d125..84288a9 100644 +index 5e8823d..e0e9afb 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c @@ -13,6 +13,8 @@ @@ -90986,7 +91824,7 @@ index 176d125..84288a9 100644 /* * Given the decoded CSD structure, decode the raw CID to our CID structure. */ -@@ -210,12 +221,62 @@ static int mmc_decode_scr(struct mmc_card *card) +@@ -210,12 +221,63 @@ static int mmc_decode_scr(struct mmc_card *card) } /* @@ -91046,12 +91884,12 @@ index 176d125..84288a9 100644 { + unsigned long timeout_at; unsigned int au, es, et, eo; -- int err, i; -+ int err, i, tries; + int err, i, max_au; ++ int tries; u32 *ssr; if (!(card->csd.cmdclass & CCC_APP_SPEC)) { -@@ -228,14 +289,40 @@ static int mmc_read_ssr(struct mmc_card *card) +@@ -228,14 +290,40 @@ static int mmc_read_ssr(struct mmc_card *card) if (!ssr) return -ENOMEM; @@ -91097,7 +91935,7 @@ index 176d125..84288a9 100644 for (i = 0; i < 16; i++) ssr[i] = be32_to_cpu(ssr[i]); -@@ -813,14 +900,10 @@ int mmc_sd_setup_card(struct mmc_host *host, struct mmc_card *card, +@@ -816,14 +904,10 @@ int mmc_sd_setup_card(struct mmc_host *host, struct mmc_card *card, if (!reinit) { /* @@ -91116,7 +91954,7 @@ index 176d125..84288a9 100644 /* diff --git a/drivers/mmc/host/sdhci-bcm2708.c b/drivers/mmc/host/sdhci-bcm2708.c -index 499d1a8..5dabf7a 100644 +index dcaefcd..a3ecdf2 100644 --- a/drivers/mmc/host/sdhci-bcm2708.c +++ b/drivers/mmc/host/sdhci-bcm2708.c @@ -137,6 +137,7 @@ static inline unsigned long int since_ns(hptime_t t) @@ -91176,155 +92014,10 @@ index 499d1a8..5dabf7a 100644 1.8.4 -From 9039ad73f20b3c912f08ee9928ef73d2f4a33ba0 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Thu, 28 Mar 2013 00:10:32 +0000 -Subject: [PATCH 42/98] bcm2708: Add vc_cma driver to enable use of CMA - ---- - arch/arm/mach-bcm2708/bcm2708.c | 18 ++++++++++++++++++ - 1 file changed, 18 insertions(+) - -diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index e010515..9d38d40 100644 ---- a/arch/arm/mach-bcm2708/bcm2708.c -+++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -60,6 +60,11 @@ - #include "armctrl.h" - #include "clock.h" - -+#ifdef CONFIG_BCM_VC_CMA -+#include -+#endif -+ -+ - /* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to - * give us IO access only to 64Mbytes of physical memory (26 bits). We could - * represent this window by setting our dmamasks to 26 bits but, in fact -@@ -634,6 +639,9 @@ void __init bcm2708_init(void) - { - int i; - -+#if defined(CONFIG_BCM_VC_CMA) -+ vc_cma_early_init(); -+#endif - printk("bcm2708.uart_clock = %d\n", uart_clock); - pm_power_off = bcm2708_power_off; - -@@ -827,7 +835,16 @@ void __init bcm2708_init_early(void) - * context. Increase size of atomic coherent pool to make sure such - * the allocations won't fail. - */ -+#if !defined(CONFIG_BCM_VC_CMA) - init_dma_coherent_pool_size(SZ_2M); -+#endif -+} -+ -+static void __init board_reserve(void) -+{ -+#if defined(CONFIG_BCM_VC_CMA) -+ vc_cma_reserve(); -+#endif - } - - MACHINE_START(BCM2708, "BCM2708") -@@ -837,6 +854,7 @@ void __init bcm2708_init_early(void) - .init_time = bcm2708_timer_init, - .init_machine = bcm2708_init, - .init_early = bcm2708_init_early, -+ .reserve = board_reserve, - MACHINE_END - - module_param(boardrev, uint, 0644); --- -1.8.4 - - -From 927798c6f84694cdf3f1d4049dc8d0bc310f74a6 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Wed, 24 Oct 2012 22:00:43 +0100 -Subject: [PATCH 43/98] Fix reboot with new restart method of machine driver - ---- - arch/arm/mach-bcm2708/bcm2708.c | 18 +++++++++++++++++- - arch/arm/mach-bcm2708/include/mach/system.h | 15 --------------- - 2 files changed, 17 insertions(+), 16 deletions(-) - -diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 9d38d40..9f456e9 100644 ---- a/arch/arm/mach-bcm2708/bcm2708.c -+++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -624,6 +624,21 @@ int __init bcm_register_device(struct platform_device *pdev) - return ret; - } - -+static void bcm2708_restart(char mode, const char *cmd) -+{ -+ uint32_t pm_rstc, pm_wdog; -+ uint32_t timeout = 10; -+ -+ /* Setup watchdog for reset */ -+ pm_rstc = readl(__io_address(PM_RSTC)); -+ -+ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0) -+ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET; -+ -+ writel(pm_wdog, __io_address(PM_WDOG)); -+ writel(pm_rstc, __io_address(PM_RSTC)); -+} -+ - /* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */ - static void bcm2708_power_off(void) - { -@@ -632,7 +647,7 @@ static void bcm2708_power_off(void) - pm_rsts = PM_PASSWORD | (pm_rsts & PM_RSTC_WRCFG_CLR) | PM_RSTS_HADWRH_SET; - writel(pm_rsts, __io_address(PM_RSTS)); - /* continue with normal reset mechanism */ -- arch_reset(0, ""); -+ bcm2708_restart(0, ""); - } - - void __init bcm2708_init(void) -@@ -855,6 +870,7 @@ static void __init board_reserve(void) - .init_machine = bcm2708_init, - .init_early = bcm2708_init_early, - .reserve = board_reserve, -+ .restart = bcm2708_restart, - MACHINE_END - - module_param(boardrev, uint, 0644); -diff --git a/arch/arm/mach-bcm2708/include/mach/system.h b/arch/arm/mach-bcm2708/include/mach/system.h -index bc9d458..2d0b821 100644 ---- a/arch/arm/mach-bcm2708/include/mach/system.h -+++ b/arch/arm/mach-bcm2708/include/mach/system.h -@@ -35,19 +35,4 @@ static inline void arch_idle(void) - cpu_do_idle(); - } - --static inline void arch_reset(char mode, const char *cmd) --{ -- uint32_t pm_rstc, pm_wdog; -- uint32_t timeout = 10; -- -- /* Setup watchdog for reset */ -- pm_rstc = readl(IO_ADDRESS(PM_RSTC)); -- -- pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0) -- pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET; -- -- writel(pm_wdog, IO_ADDRESS(PM_WDOG)); -- writel(pm_rstc, IO_ADDRESS(PM_RSTC)); --} -- - #endif --- -1.8.4 - - -From 0fa0203afc42678c9cb4719c5710d5a5f043abd0 Mon Sep 17 00:00:00 2001 +From 90e0bc3b54e69a9c746168e978810930dcfc5c7b Mon Sep 17 00:00:00 2001 From: Gordon Hollingworth Date: Sun, 4 Nov 2012 15:55:01 +0000 -Subject: [PATCH 44/98] Make sure we wait for the reset to finish +Subject: [PATCH 39/82] Make sure we wait for the reset to finish --- drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 2 ++ @@ -91347,31 +92040,32 @@ index aff59df..1a23d4b 100644 1.8.4 -From 397afe17888dafc5c5125c95fdca52d85f0add42 Mon Sep 17 00:00:00 2001 +From 61d55ded63bf8fd4e946748aa28fe01fbc641f33 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 19 Nov 2012 18:27:05 +0000 -Subject: [PATCH 45/98] Add Simon Hall's dma helper module, useful in future +Subject: [PATCH 40/82] Add Simon Hall's dma helper module, useful in future for X acceleration --- - arch/arm/mach-bcm2708/Kconfig | 7 + + arch/arm/mach-bcm2708/Kconfig | 8 + arch/arm/mach-bcm2708/Makefile | 3 + arch/arm/mach-bcm2708/dmaer.c | 886 ++++++++++++++++++++++++ arch/arm/mach-bcm2708/include/mach/vc_support.h | 69 ++ arch/arm/mach-bcm2708/vc_support.c | 318 +++++++++ - 5 files changed, 1283 insertions(+) + 5 files changed, 1284 insertions(+) create mode 100755 arch/arm/mach-bcm2708/dmaer.c create mode 100755 arch/arm/mach-bcm2708/include/mach/vc_support.h create mode 100755 arch/arm/mach-bcm2708/vc_support.c diff --git a/arch/arm/mach-bcm2708/Kconfig b/arch/arm/mach-bcm2708/Kconfig -index 9355841..cfa8779 100644 +index e151ed4..2dcd6fa 100644 --- a/arch/arm/mach-bcm2708/Kconfig +++ b/arch/arm/mach-bcm2708/Kconfig -@@ -31,4 +31,11 @@ config BCM2708_NOL2CACHE - help - Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt. - +@@ -38,4 +38,12 @@ config BCM2708_SPIDEV + default y + help + Binds spidev driver to the SPI0 master ++ +config BCM2708_DMAER + tristate "BCM2708 DMA helper" + depends on MACH_BCM2708 @@ -92686,10 +93380,10 @@ index 0000000..0bc41c4 1.8.4 -From 20def2275a9ab4dcc3566769ea88a386c02dc849 Mon Sep 17 00:00:00 2001 +From e3c17da3dffbfb12ff81cb840e1895fbc395906f Mon Sep 17 00:00:00 2001 From: Aron Szabo Date: Sat, 16 Jun 2012 12:15:55 +0200 -Subject: [PATCH 46/98] lirc: added support for RaspberryPi GPIO +Subject: [PATCH 41/82] lirc: added support for RaspberryPi GPIO --- drivers/staging/media/lirc/Kconfig | 6 + @@ -93424,10 +94118,10 @@ index 0000000..96acab0 1.8.4 -From f3c764b1a2ac492c762721e88e3ef8e1a4ab7b64 Mon Sep 17 00:00:00 2001 +From 97f6f722559421387f1a1a1396522ab0c1563ea0 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 11 Dec 2012 18:23:03 +0000 -Subject: [PATCH 47/98] Default to dwc_otp.lpm_enable=0 +Subject: [PATCH 42/82] Default to dwc_otp.lpm_enable=0 --- drivers/usb/host/dwc_otg/dwc_otg_driver.c | 2 +- @@ -93450,38 +94144,10 @@ index d58ebd7..c2bb596 100644 1.8.4 -From 510c702cee5c8d99638af2967cdffeb15ee15291 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Tue, 11 Dec 2012 19:04:27 +0000 -Subject: [PATCH 48/98] Increase default coherent pool so vchiq starts up - ---- - arch/arm/mach-bcm2708/bcm2708.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - -diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 9f456e9..87fd348 100644 ---- a/arch/arm/mach-bcm2708/bcm2708.c -+++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -850,9 +850,7 @@ void __init bcm2708_init_early(void) - * context. Increase size of atomic coherent pool to make sure such - * the allocations won't fail. - */ --#if !defined(CONFIG_BCM_VC_CMA) -- init_dma_coherent_pool_size(SZ_2M); --#endif -+ init_dma_coherent_pool_size(SZ_4M); - } - - static void __init board_reserve(void) --- -1.8.4 - - -From d778ff805f77c7c41b961ae5cee9cd726fc7e311 Mon Sep 17 00:00:00 2001 +From 983a0999608be29ebe004fbc0eb11c8243f7573a Mon Sep 17 00:00:00 2001 From: P33M Date: Wed, 9 Jan 2013 16:12:04 +0000 -Subject: [PATCH 49/98] dwc_otg: fix bug in dwc_otg_hcd.c resulting in silent +Subject: [PATCH 43/82] dwc_otg: fix bug in dwc_otg_hcd.c resulting in silent kernel memory corruption, escalating to OOPS under high USB load. --- @@ -93518,84 +94184,10 @@ index ebee73a..b3efaf4 100644 1.8.4 -From 043148c2a8cad1331d569f9fefd4c9b640e4e2cb Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Mon, 21 Jan 2013 23:03:53 +0000 -Subject: [PATCH 50/98] Return error value from bcm2708_setup_state. Thanks - notro - ---- - drivers/spi/spi-bcm2708.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/spi/spi-bcm2708.c b/drivers/spi/spi-bcm2708.c -index 9f1580e..8513704 100644 ---- a/drivers/spi/spi-bcm2708.c -+++ b/drivers/spi/spi-bcm2708.c -@@ -378,6 +378,7 @@ static int bcm2708_spi_setup(struct spi_device *spi) - if (ret < 0) { - kfree(state); - spi->controller_state = NULL; -+ return ret; - } - - dev_dbg(&spi->dev, --- -1.8.4 - - -From ed10330b78520fb29709da4cc11c548ad152bcb4 Mon Sep 17 00:00:00 2001 -From: Kamal Mostafa -Date: Mon, 22 Oct 2012 15:52:44 -0700 -Subject: [PATCH 51/98] spi/spi-bcm2708: respect per-transfer SPI clock - speed_hz value - -The bcm2708 SPI driver's bcm2708_process_transfer() was ignoring the -per-transfer speed_hz value even when it was provided (it always just -used the spi device's max_speed_hz value). Now, per-transfer speed_hz -values are respected. - -Also added debug print to bcm2708_setup_state() to help keep an eye on -the configured SPI parameters. - -Signed-off-by: Kamal Mostafa ---- - drivers/spi/spi-bcm2708.c | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - -diff --git a/drivers/spi/spi-bcm2708.c b/drivers/spi/spi-bcm2708.c -index 8513704..b74aa32 100644 ---- a/drivers/spi/spi-bcm2708.c -+++ b/drivers/spi/spi-bcm2708.c -@@ -259,6 +259,10 @@ static int bcm2708_setup_state(struct spi_master *master, - if (state) { - state->cs = cs; - state->cdiv = cdiv; -+ dev_dbg(dev, "setup: want %d Hz; " -+ "bus_hz=%lu / cdiv=%u == %lu Hz; " -+ "mode %u: cs 0x%08X\n", -+ hz, bus_hz, cdiv, bus_hz/cdiv, mode, cs); - } - - return 0; -@@ -277,7 +281,8 @@ static int bcm2708_process_transfer(struct bcm2708_spi *bs, - - if (xfer->bits_per_word || xfer->speed_hz) { - ret = bcm2708_setup_state(spi->master, &spi->dev, &state, -- spi->max_speed_hz, spi->chip_select, spi->mode, -+ xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz, -+ spi->chip_select, spi->mode, - spi->bits_per_word); - if (ret) - return ret; --- -1.8.4 - - -From 3db63bd3b35cb20f6ff7c64b82e6095ca128e334 Mon Sep 17 00:00:00 2001 +From b035bd5b8416ada559cea222b1bfc49a328357f9 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:51:55 +0100 -Subject: [PATCH 52/98] Add hwrng (hardware random number generator) driver +Subject: [PATCH 44/82] Add hwrng (hardware random number generator) driver --- arch/arm/mach-bcm2708/include/mach/platform.h | 1 + @@ -93618,7 +94210,7 @@ index 89e72d1..992a630 100644 #define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */ #define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */ diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig -index 40a8654..2e485d71 100644 +index 0aa9d91..1d575d0 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -314,3 +314,14 @@ config HW_RANDOM_TPM @@ -93772,112 +94364,10 @@ index 0000000..1ffa7d7 1.8.4 -From 6cc39a2058056ffb7e3d3eaf8b9b6625ed320879 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Thu, 7 Feb 2013 17:04:13 +0000 -Subject: [PATCH 53/98] Add missing newlines to log messages - ---- - drivers/cpufreq/bcm2835-cpufreq.c | 20 ++++++++++---------- - 1 file changed, 10 insertions(+), 10 deletions(-) - -diff --git a/drivers/cpufreq/bcm2835-cpufreq.c b/drivers/cpufreq/bcm2835-cpufreq.c -index f9b976c..397fed0 100755 ---- a/drivers/cpufreq/bcm2835-cpufreq.c -+++ b/drivers/cpufreq/bcm2835-cpufreq.c -@@ -91,7 +91,7 @@ static uint32_t bcm2835_cpufreq_set_clock(int cur_rate, int arm_rate) - if (s == 0 && (msg.request_code & 0x80000000)) - actual_rate = msg.tag.val/1000; - -- print_debug("Setting new frequency = %d -> %d (actual %d)", cur_rate, arm_rate, actual_rate); -+ print_debug("Setting new frequency = %d -> %d (actual %d)\n", cur_rate, arm_rate, actual_rate); - return actual_rate; - } - -@@ -117,7 +117,7 @@ static uint32_t bcm2835_cpufreq_get_clock(int tag) - if (s == 0 && (msg.request_code & 0x80000000)) - arm_rate = msg.tag.val/1000; - -- print_debug("%s frequency = %d", -+ print_debug("%s frequency = %d\n", - tag == VCMSG_GET_CLOCK_RATE ? "Current": - tag == VCMSG_GET_MIN_CLOCK ? "Min": - tag == VCMSG_GET_MAX_CLOCK ? "Max": -@@ -133,7 +133,7 @@ static uint32_t bcm2835_cpufreq_get_clock(int tag) - */ - static int __init bcm2835_cpufreq_module_init(void) - { -- print_debug("IN"); -+ print_debug("IN\n"); - return cpufreq_register_driver(&bcm2835_cpufreq_driver); - } - -@@ -144,7 +144,7 @@ static int __init bcm2835_cpufreq_module_init(void) - */ - static void __exit bcm2835_cpufreq_module_exit(void) - { -- print_debug("IN"); -+ print_debug("IN\n"); - cpufreq_unregister_driver(&bcm2835_cpufreq_driver); - return; - } -@@ -164,7 +164,7 @@ static int bcm2835_cpufreq_driver_init(struct cpufreq_policy *policy) - policy->max = policy->cpuinfo.max_freq = bcm2835_cpufreq_get_clock(VCMSG_GET_MAX_CLOCK); - policy->cur = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE); - -- print_info("min=%d max=%d cur=%d", policy->min, policy->max, policy->cur); -+ print_info("min=%d max=%d cur=%d\n", policy->min, policy->max, policy->cur); - return 0; - } - -@@ -178,7 +178,7 @@ static int bcm2835_cpufreq_driver_target(struct cpufreq_policy *policy, unsigned - { - unsigned int target = target_freq; - unsigned int cur = policy->cur; -- print_debug("%s: min=%d max=%d cur=%d target=%d",policy->governor->name,policy->min,policy->max,policy->cur,target_freq); -+ print_debug("%s: min=%d max=%d cur=%d target=%d\n",policy->governor->name,policy->min,policy->max,policy->cur,target_freq); - - /* if we are above min and using ondemand, then just use max */ - if (strcmp("ondemand", policy->governor->name)==0 && target > policy->min) -@@ -192,18 +192,18 @@ static int bcm2835_cpufreq_driver_target(struct cpufreq_policy *policy, unsigned - - if (!policy->cur) - { -- print_err("Error occurred setting a new frequency (%d)!", target); -+ print_err("Error occurred setting a new frequency (%d)!\n", target); - policy->cur = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE); - return -EINVAL; - } -- print_debug("Freq %d->%d (min=%d max=%d target=%d request=%d)", cur, policy->cur, policy->min, policy->max, target_freq, target); -+ print_debug("Freq %d->%d (min=%d max=%d target=%d request=%d)\n", cur, policy->cur, policy->min, policy->max, target_freq, target); - return 0; - } - - static unsigned int bcm2835_cpufreq_driver_get(unsigned int cpu) - { - unsigned int actual_rate = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE); -- print_debug("%d", actual_rate); -+ print_debug("cpu=%d\n", actual_rate); - return actual_rate; - } - -@@ -215,7 +215,7 @@ static unsigned int bcm2835_cpufreq_driver_get(unsigned int cpu) - - static int bcm2835_cpufreq_driver_verify(struct cpufreq_policy *policy) - { -- print_info("switching to governor %s", policy->governor->name); -+ print_info("switching to governor %s\n", policy->governor->name); - return 0; - } - --- -1.8.4 - - -From 0171249253522fa6cf702cdd2f1f2cc3502e94b9 Mon Sep 17 00:00:00 2001 +From e7e4126390137ea359cfb76cffc2b69c725e0dc6 Mon Sep 17 00:00:00 2001 From: Technion Date: Mon, 11 Feb 2013 22:08:53 +1100 -Subject: [PATCH 54/98] Changed wording on logging. Previously, we received +Subject: [PATCH 45/82] Changed wording on logging. Previously, we received errors like this: mmc0: could read SD Status register (SSR) at the 3th attempt A more sensible response is now returned. A typo also fixed in comments. @@ -93887,7 +94377,7 @@ Subject: [PATCH 54/98] Changed wording on logging. Previously, we received 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c -index 84288a9..d144d66 100644 +index e0e9afb..25b98a9 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c @@ -238,7 +238,7 @@ static int mmc_read_scr(struct mmc_card *card) @@ -93899,7 +94389,7 @@ index 84288a9..d144d66 100644 touch_nmi_watchdog(); // we are still alive! -@@ -320,7 +320,7 @@ static int mmc_read_ssr(struct mmc_card *card) +@@ -321,7 +321,7 @@ static int mmc_read_ssr(struct mmc_card *card) if( tries > 1 ) { @@ -93912,10 +94402,10 @@ index 84288a9..d144d66 100644 1.8.4 -From b320a9e0cd696edaba7613662f7454998cc22bfc Mon Sep 17 00:00:00 2001 +From 6c1706493529f0f0dd5c9f944cc01981cd030b47 Mon Sep 17 00:00:00 2001 From: P33M Date: Fri, 15 Feb 2013 22:36:47 +0000 -Subject: [PATCH 55/98] dwc_otg: Fix unsafe access of QTD during URB enqueue +Subject: [PATCH 46/82] dwc_otg: Fix unsafe access of QTD during URB enqueue In dwc_otg_hcd_urb_enqueue during qtd creation, it was possible that the transaction could complete almost immediately after the qtd was assigned @@ -94002,10 +94492,10 @@ index b3efaf4..1554be5 100644 1.8.4 -From 408a58e3132f49bc38d2f1e3dc488aa21d8da1af Mon Sep 17 00:00:00 2001 +From 9351b307e68fa5389a561537ba695fe6f068c2e8 Mon Sep 17 00:00:00 2001 From: P33M Date: Fri, 15 Feb 2013 22:38:40 +0000 -Subject: [PATCH 56/98] dwc_otg: Fix incorrect URB allocation error handling +Subject: [PATCH 47/82] dwc_otg: Fix incorrect URB allocation error handling If the memory allocation for a dwc_otg_urb failed, the kernel would OOPS because for some reason a member of the *unallocated* struct was set to @@ -94046,10 +94536,10 @@ index 35d03d1..6fe30e3 100644 1.8.4 -From 52953b25d6d738c7681395b6f1df9228fc026241 Mon Sep 17 00:00:00 2001 +From 73ceb51a9b51d70305ed1c7677daa3ee807f92b2 Mon Sep 17 00:00:00 2001 From: pjennings Date: Wed, 20 Feb 2013 17:51:43 -0600 -Subject: [PATCH 57/98] Added inverted transmitter support +Subject: [PATCH 48/82] Added inverted transmitter support --- drivers/staging/media/lirc/lirc_rpi.c | 17 +++++++++++------ @@ -94130,10 +94620,10 @@ index 96acab0..5bb0dfe 100644 1.8.4 -From e469227a5d9315971fd94bf646166305c647cca4 Mon Sep 17 00:00:00 2001 +From d9a6d84bd83bcdf8edb9b6add4d59e148dde11d6 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Sun, 24 Feb 2013 16:30:57 +0000 -Subject: [PATCH 58/98] Add retry on error and tidy of temperature driver +Subject: [PATCH 49/82] Add retry on error and tidy of temperature driver --- drivers/thermal/bcm2835-thermal.c | 78 ++++++++++++++------------------------- @@ -94260,10 +94750,10 @@ index 3f9a733..85fceb5 100644 1.8.4 -From 098816e91e648d607ae2b41ee7d7141e65d687ce Mon Sep 17 00:00:00 2001 +From 589b438b9d484e464f6894ab1daab3dce8833bf1 Mon Sep 17 00:00:00 2001 From: P33M Date: Thu, 28 Feb 2013 16:52:51 +0000 -Subject: [PATCH 59/98] dwc_otg: fix potential use-after-free case in interrupt +Subject: [PATCH 50/82] dwc_otg: fix potential use-after-free case in interrupt handler If a transaction had previously aborted, certain interrupts are @@ -94295,10 +94785,10 @@ index 1a23d4b..7af455d 100644 1.8.4 -From 7183dceb7d585cf4f7afc430b04fefd244dd943e Mon Sep 17 00:00:00 2001 +From ca577be817a50946fe082bbbdb5cde78fdb47a3e Mon Sep 17 00:00:00 2001 From: P33M Date: Sun, 3 Mar 2013 14:45:53 +0000 -Subject: [PATCH 60/98] dwc_otg: add handling of SPLIT transaction data toggle +Subject: [PATCH 51/82] dwc_otg: add handling of SPLIT transaction data toggle errors Previously a data toggle error on packets from a USB1.1 device behind @@ -94353,10 +94843,10 @@ index 7af455d..a27dacd 100644 1.8.4 -From ff6407232b5a82b64b5bc523264aff3e31d3d04e Mon Sep 17 00:00:00 2001 +From 016d8e6a44821e3547e00be48ed83efdc02cc467 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 1 May 2013 21:14:28 +0100 -Subject: [PATCH 61/98] Add bitbanging pullups, use them for w1-gpio +Subject: [PATCH 52/82] Add bitbanging pullups, use them for w1-gpio Allows parasite power to work, uses module option pullup=1 --- @@ -94495,83 +94985,10 @@ index e10acc2..667fdd5 100644 1.8.4 -From 7263e590695cecb72c1c16eeab2fdebf86fe9831 Mon Sep 17 00:00:00 2001 -From: notro -Date: Sat, 26 Jan 2013 20:38:03 +0100 -Subject: [PATCH 62/98] spi-bcm2708: add 9-bit support using LoSSI mode - ---- - drivers/spi/spi-bcm2708.c | 30 ++++++++++++++++++++++++++++-- - 1 file changed, 28 insertions(+), 2 deletions(-) - -diff --git a/drivers/spi/spi-bcm2708.c b/drivers/spi/spi-bcm2708.c -index b74aa32..abaa5a6 100644 ---- a/drivers/spi/spi-bcm2708.c -+++ b/drivers/spi/spi-bcm2708.c -@@ -146,10 +146,31 @@ static inline void bcm2708_rd_fifo(struct bcm2708_spi *bs, int len) - static inline void bcm2708_wr_fifo(struct bcm2708_spi *bs, int len) - { - u8 byte; -+ u16 val; - - if (len > bs->len) - len = bs->len; - -+ if (unlikely(bcm2708_rd(bs, SPI_CS) & SPI_CS_LEN)) { -+ /* LoSSI mode */ -+ if (unlikely(len % 2)) { -+ printk(KERN_ERR"bcm2708_wr_fifo: length must be even, skipping.\n"); -+ bs->len = 0; -+ return; -+ } -+ while (len) { -+ if (bs->tx_buf) { -+ val = *(const u16 *)bs->tx_buf; -+ bs->tx_buf += 2; -+ } else -+ val = 0; -+ bcm2708_wr(bs, SPI_FIFO, val); -+ bs->len -= 2; -+ len -= 2; -+ } -+ return; -+ } -+ - while (len--) { - byte = bs->tx_buf ? *bs->tx_buf++ : 0; - bcm2708_wr(bs, SPI_FIFO, byte); -@@ -234,8 +255,12 @@ static int bcm2708_setup_state(struct spi_master *master, - switch (bpw) { - case 8: - break; -+ case 9: -+ /* Reading in LoSSI mode is a special case. See 'BCM2835 ARM Peripherals' datasheet */ -+ cs |= SPI_CS_LEN; -+ break; - default: -- dev_dbg(dev, "setup: invalid bits_per_word %u (must be 8)\n", -+ dev_dbg(dev, "setup: invalid bits_per_word %u (must be 8 or 9)\n", - bpw); - return -EINVAL; - } -@@ -283,7 +308,8 @@ static int bcm2708_process_transfer(struct bcm2708_spi *bs, - ret = bcm2708_setup_state(spi->master, &spi->dev, &state, - xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz, - spi->chip_select, spi->mode, -- spi->bits_per_word); -+ xfer->bits_per_word ? xfer->bits_per_word : -+ spi->bits_per_word); - if (ret) - return ret; - --- -1.8.4 - - -From fc5ba144c17d0de46e37f82db0e55884c9d2912d Mon Sep 17 00:00:00 2001 +From ccf2dee549dfe3a9a365255ef742bed2794f1f87 Mon Sep 17 00:00:00 2001 From: P33M Date: Thu, 21 Mar 2013 19:36:17 +0000 -Subject: [PATCH 63/98] dwc_otg: implement tasklet for returning URBs to +Subject: [PATCH 53/82] dwc_otg: implement tasklet for returning URBs to usbcore hcd layer The dwc_otg driver interrupt handler for transfer completion will spend @@ -94813,10 +95230,10 @@ index 2b4a14e..39787e3 100644 1.8.4 -From 98434c9fee536931b9286c5dd52c271b58130d72 Mon Sep 17 00:00:00 2001 +From 17181a1c89f20b4e11d6f7d7e461e4d9666b21ce Mon Sep 17 00:00:00 2001 From: P33M Date: Mon, 22 Apr 2013 00:08:36 +0100 -Subject: [PATCH 65/98] dwc_otg: fix NAK holdoff and allow on split +Subject: [PATCH 55/82] dwc_otg: fix NAK holdoff and allow on split transactions only This corrects a bug where if a single active non-periodic endpoint @@ -94886,10 +95303,10 @@ index 533b17d..73f7643 100644 1.8.4 -From 528ac5e9e0e149d5d64648c6b03aa14726b0d8aa Mon Sep 17 00:00:00 2001 +From c3e96740bbfb0cde7b181e2871a20412641f8e88 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Fri, 26 Apr 2013 10:08:31 -0700 -Subject: [PATCH 66/98] Merge pull request #286 from +Subject: [PATCH 56/82] Merge pull request #286 from martinezjavier/rpi-3.6.y-dev add mmap support and some cleanups to bcm2835 ALSA driver @@ -95370,10 +95787,10 @@ index 080bd5c..36afee3 100755 1.8.4 -From 02ea18b94aa294b60e8add5713a25d8044d516b7 Mon Sep 17 00:00:00 2001 +From a7e509238c4f108746e4f6567e5e7f2461dd11ef Mon Sep 17 00:00:00 2001 From: popcornmix Date: Fri, 10 May 2013 19:42:38 +0100 -Subject: [PATCH 67/98] mmc: suppress sdcard warnings we are happy about by +Subject: [PATCH 57/82] mmc: suppress sdcard warnings we are happy about by default --- @@ -95381,7 +95798,7 @@ Subject: [PATCH 67/98] mmc: suppress sdcard warnings we are happy about by 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-bcm2708.c b/drivers/mmc/host/sdhci-bcm2708.c -index 5dabf7a..455ad78 100644 +index a3ecdf2..71f33ce 100644 --- a/drivers/mmc/host/sdhci-bcm2708.c +++ b/drivers/mmc/host/sdhci-bcm2708.c @@ -139,6 +139,7 @@ static inline unsigned long int since_ns(hptime_t t) @@ -95439,181 +95856,10 @@ index 5dabf7a..455ad78 100644 1.8.4 -From eea9b9c8b9ed28a50e01572330670ff7678e2d63 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Tue, 14 May 2013 11:42:25 +0100 -Subject: [PATCH 68/98] Allow reboot=q on command line to set a flag that - bootcode.bin can use to boot from alternate partition - ---- - arch/arm/mach-bcm2708/bcm2708.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 87fd348..1ed4d73 100644 ---- a/arch/arm/mach-bcm2708/bcm2708.c -+++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -629,6 +629,15 @@ static void bcm2708_restart(char mode, const char *cmd) - uint32_t pm_rstc, pm_wdog; - uint32_t timeout = 10; - -+ /* For quick reset notification add reboot=q to cmdline -+ */ -+ if(mode == 'q') -+ { -+ uint32_t pm_rsts = readl(__io_address(PM_RSTS)); -+ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET; -+ writel(pm_rsts, __io_address(PM_RSTS)); -+ } -+ - /* Setup watchdog for reset */ - pm_rstc = readl(__io_address(PM_RSTC)); - --- -1.8.4 - - -From 6d987a9dadeb0a557f7a842770f1c3ef42edf8d5 Mon Sep 17 00:00:00 2001 -From: hutorny -Date: Mon, 13 May 2013 10:26:14 +0300 -Subject: [PATCH 70/98] Update bcm2708.c to use CONFIG_BCM2708_SPIDEV rather - than CONFIG_SPI - ---- - arch/arm/mach-bcm2708/Kconfig | 7 +++++++ - arch/arm/mach-bcm2708/bcm2708.c | 4 ++-- - 2 files changed, 9 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/mach-bcm2708/Kconfig b/arch/arm/mach-bcm2708/Kconfig -index cfa8779..314ee38 100644 ---- a/arch/arm/mach-bcm2708/Kconfig -+++ b/arch/arm/mach-bcm2708/Kconfig -@@ -38,4 +38,11 @@ config BCM2708_DMAER - help - Enable DMA helper for accelerating X composition - -+config BCM2708_SPIDEV -+ bool "Bind spidev to SPI0 master" -+ depends on MACH_BCM2708 -+ depends on SPI -+ default y -+ help -+ Binds spidev driver to the SPI0 master - endmenu -diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 1ed4d73..68c577a 100644 ---- a/arch/arm/mach-bcm2708/bcm2708.c -+++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -545,7 +545,7 @@ struct platform_device bcm2708_powerman_device = { - .resource = bcm2708_spi_resources, - }; - --#ifdef CONFIG_SPI -+#ifdef CONFIG_BCM2708_SPIDEV - static struct spi_board_info bcm2708_spi_devices[] = { - #ifdef CONFIG_SPI_SPIDEV - { -@@ -715,7 +715,7 @@ void __init bcm2708_init(void) - system_rev = boardrev; - system_serial_low = serial; - --#ifdef CONFIG_SPI -+#ifdef CONFIG_BCM2708_SPIDEV - spi_register_board_info(bcm2708_spi_devices, - ARRAY_SIZE(bcm2708_spi_devices)); - #endif --- -1.8.4 - - -From 4c355ddaebff658e385a2232958cd22ccb8ef20e Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Sat, 8 Jun 2013 22:14:13 +0100 -Subject: [PATCH 72/98] Only init gpio pins of selected i2c bus - ---- - drivers/i2c/busses/i2c-bcm2708.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - -diff --git a/drivers/i2c/busses/i2c-bcm2708.c b/drivers/i2c/busses/i2c-bcm2708.c -index ac9df18..13a4cd7 100644 ---- a/drivers/i2c/busses/i2c-bcm2708.c -+++ b/drivers/i2c/busses/i2c-bcm2708.c -@@ -97,7 +97,7 @@ struct bcm2708_i2c { - * - * FIXME: This is a hack. Use pinmux / pinctrl. - */ --static void bcm2708_i2c_init_pinmode(void) -+static void bcm2708_i2c_init_pinmode(int id) - { - #define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3)) - #define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) -@@ -105,8 +105,10 @@ static void bcm2708_i2c_init_pinmode(void) - int pin; - u32 *gpio = ioremap(0x20200000, SZ_16K); - -+ BUG_ON(id != 0 && id != 1); - /* BSC0 is on GPIO 0 & 1, BSC1 is on GPIO 2 & 3 */ -- for (pin = 0; pin <= 3; pin++) { -+ for (pin = id*2+0; pin <= id*2+1; pin++) { -+printk("bcm2708_i2c_init_pinmode(%d,%d)\n", id, pin); - INP_GPIO(pin); /* set mode to GPIO input first */ - SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */ - } -@@ -279,7 +281,7 @@ static int bcm2708_i2c_probe(struct platform_device *pdev) - return PTR_ERR(clk); - } - -- bcm2708_i2c_init_pinmode(); -+ bcm2708_i2c_init_pinmode(pdev->id); - - bi = kzalloc(sizeof(*bi), GFP_KERNEL); - if (!bi) --- -1.8.4 - - -From e7aeccf765f45674a1c45f90f0fc219dc1f8df37 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Thu, 13 Jun 2013 16:46:54 +0100 -Subject: [PATCH 73/98] Avoid responding to unexpected I2C interrupts - ---- - drivers/i2c/busses/i2c-bcm2708.c | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/drivers/i2c/busses/i2c-bcm2708.c b/drivers/i2c/busses/i2c-bcm2708.c -index 13a4cd7..72750c7 100644 ---- a/drivers/i2c/busses/i2c-bcm2708.c -+++ b/drivers/i2c/busses/i2c-bcm2708.c -@@ -175,6 +175,11 @@ static irqreturn_t bcm2708_i2c_interrupt(int irq, void *dev_id) - - spin_lock(&bi->lock); - -+ /* we may see camera interrupts on the "other" I2C channel -+ Just return if we've not sent anything */ -+ if (!bi->nmsgs || !bi->msg ) -+ goto early_exit; -+ - s = bcm2708_rd(bi, BSC_S); - - if (s & (BSC_S_CLKT | BSC_S_ERR)) { -@@ -208,6 +213,7 @@ static irqreturn_t bcm2708_i2c_interrupt(int irq, void *dev_id) - handled = false; - } - -+early_exit: - spin_unlock(&bi->lock); - - return handled ? IRQ_HANDLED : IRQ_NONE; --- -1.8.4 - - -From bd5ac92d8c102fe8c3283f8e8f00cd3c91bd1300 Mon Sep 17 00:00:00 2001 +From 9be1838ab3c08af3421d4ceb89ade82009c527e6 Mon Sep 17 00:00:00 2001 From: Harm Hanemaaijer Date: Thu, 20 Jun 2013 20:21:39 +0200 -Subject: [PATCH 74/98] Speed up console framebuffer imageblit function +Subject: [PATCH 58/82] Speed up console framebuffer imageblit function Especially on platforms with a slower CPU but a relatively high framebuffer fill bandwidth, like current ARM devices, the existing @@ -95825,10 +96071,10 @@ index baed57d..ce91bf2 100644 1.8.4 -From afee0c44e9701678f2063bcfc845771ee6424f0d Mon Sep 17 00:00:00 2001 +From de56c40c1f5fb19dadd8c5fa488915b95fb6f7ac Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Mon, 17 Jun 2013 13:32:11 +0300 -Subject: [PATCH 75/98] fbdev: add FBIOCOPYAREA ioctl +Subject: [PATCH 59/82] fbdev: add FBIOCOPYAREA ioctl Based on the patch authored by Ali Gholami Rudi at https://lkml.org/lkml/2009/7/13/153 @@ -95843,12 +96089,12 @@ Signed-off-by: Siarhei Siamashka 2 files changed, 35 insertions(+) diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c -index 36e1fe2..1aa4d46 100644 +index dacaf74..5985bfa 100644 --- a/drivers/video/fbmem.c +++ b/drivers/video/fbmem.c -@@ -1074,6 +1074,25 @@ static int fb_check_caps(struct fb_info *info, struct fb_var_screeninfo *var, - return ret; +@@ -1083,6 +1083,25 @@ static int fb_check_caps(struct fb_info *info, struct fb_var_screeninfo *var, } + EXPORT_SYMBOL(fb_blank); +static int fb_copyarea_user(struct fb_info *info, + struct fb_copyarea *copy) @@ -95872,7 +96118,7 @@ index 36e1fe2..1aa4d46 100644 static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) { -@@ -1084,6 +1103,7 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, +@@ -1093,6 +1112,7 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, struct fb_cmap cmap_from; struct fb_cmap_user cmap; struct fb_event event; @@ -95880,7 +96126,7 @@ index 36e1fe2..1aa4d46 100644 void __user *argp = (void __user *)arg; long ret = 0; -@@ -1193,6 +1213,15 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, +@@ -1202,6 +1222,15 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, console_unlock(); unlock_fb_info(info); break; @@ -95896,7 +96142,7 @@ index 36e1fe2..1aa4d46 100644 default: if (!lock_fb_info(info)) return -ENODEV; -@@ -1347,6 +1376,7 @@ static long fb_compat_ioctl(struct file *file, unsigned int cmd, +@@ -1356,6 +1385,7 @@ static long fb_compat_ioctl(struct file *file, unsigned int cmd, case FBIOPAN_DISPLAY: case FBIOGET_CON2FBMAP: case FBIOPUT_CON2FBMAP: @@ -95924,10 +96170,10 @@ index fb795c3..fa72af0 100644 1.8.4 -From b43c057eceb68103bc55fdd2b0eaac0541b0b602 Mon Sep 17 00:00:00 2001 +From 4ff866a7add9f47565263bd1004bdcec71894533 Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Mon, 17 Jun 2013 16:00:25 +0300 -Subject: [PATCH 76/98] bcm2708_fb: DMA acceleration for fb_copyarea +Subject: [PATCH 60/82] bcm2708_fb: DMA acceleration for fb_copyarea Based on http://www.raspberrypi.org/phpBB3/viewtopic.php?p=62425#p62425 Also used Simon's dmaer_master module as a reference for tweaking DMA @@ -96171,10 +96417,10 @@ index 08d9238..c10c5ee 100644 1.8.4 -From 0683cbcae13b09f3baf002f6905cdee9548505fd Mon Sep 17 00:00:00 2001 +From a649566c8170b418a8bf67eaeeba1fe695e6d663 Mon Sep 17 00:00:00 2001 From: Mike Bradley Date: Mon, 17 Jun 2013 11:31:42 -0700 -Subject: [PATCH 77/98] dwc_otg: Call usb_hcd_unlink_urb_from_ep with lock held +Subject: [PATCH 61/82] dwc_otg: Call usb_hcd_unlink_urb_from_ep with lock held in completion handler usb_hcd_unlink_urb_from_ep must be called with the HCD lock held. Calling it @@ -96261,10 +96507,10 @@ index 39787e3..5e6a26a 100644 1.8.4 -From 10b42226b71ff181ced123e9f93f60f9b186b827 Mon Sep 17 00:00:00 2001 +From 80007e07fed0871cbcdd0b49122a4d9d5059c5a1 Mon Sep 17 00:00:00 2001 From: Gordon Hollingworth Date: Thu, 4 Apr 2013 11:05:21 +0100 -Subject: [PATCH 78/98] USB fix using a FIQ to implement split transactions +Subject: [PATCH 62/82] USB fix using a FIQ to implement split transactions This commit adds a FIQ implementaion that schedules the split transactions using a FIQ so we don't get @@ -97667,10 +97913,10 @@ index 1b1f83c..c8590b5 100644 1.8.4 -From 7384de894b44619cf98a55d040dcded0653f7f1b Mon Sep 17 00:00:00 2001 +From 7a5d1f564dc3f0a05fb6e31bbb01040ebc19b983 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 11:39:46 +0100 -Subject: [PATCH 79/98] dwc_otg: fix device attributes and avoid kernel +Subject: [PATCH 63/82] dwc_otg: fix device attributes and avoid kernel warnings on boot --- @@ -97739,10 +97985,10 @@ index fab2961..af1cd4d 100644 1.8.4 -From b5994a121f2e14ac22599dcd52fbf88014b442d2 Mon Sep 17 00:00:00 2001 +From 6f6b15799bb09733814a03eb0d48e6f2b55e6d4e Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 10 Jul 2013 23:53:31 +0100 -Subject: [PATCH 81/98] sdhci-bcm2807: Increase sync_after_dma timeout +Subject: [PATCH 64/82] sdhci-bcm2807: Increase sync_after_dma timeout The current timeout is being hit with some cards that complete successfully with a longer timeout. The timeout is not handled well, and is believed to be a code path that causes corruption. @@ -97752,7 +97998,7 @@ The timeout is not handled well, and is believed to be a code path that causes c 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-bcm2708.c b/drivers/mmc/host/sdhci-bcm2708.c -index 455ad78..7f79f54 100644 +index 71f33ce..45499d8 100644 --- a/drivers/mmc/host/sdhci-bcm2708.c +++ b/drivers/mmc/host/sdhci-bcm2708.c @@ -842,7 +842,7 @@ static void sdhci_bcm2708_dma_complete_irq(struct sdhci_host *host, @@ -97768,10 +98014,10 @@ index 455ad78..7f79f54 100644 1.8.4 -From 98a35f04b5bec52b249476f33248c169a803082d Mon Sep 17 00:00:00 2001 +From 567e8f771ba1c2a89b7d1f9936af7009e2d7b3f9 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 15 Jul 2013 23:55:52 +0100 -Subject: [PATCH 82/98] dcw_otg: avoid logging function that can cause panics +Subject: [PATCH 65/82] dcw_otg: avoid logging function that can cause panics See: https://github.com/raspberrypi/firmware/issues/21 Thanks to cleverca22 for fix @@ -97796,10 +98042,10 @@ index af1cd4d..9da0c92 100644 1.8.4 -From cfa89df22ac4dce5b4347f0aaedc52e36d8ca9cd Mon Sep 17 00:00:00 2001 +From 89b663525d62c59581ff7f6d251191d25cf317c4 Mon Sep 17 00:00:00 2001 From: P33M Date: Sat, 13 Jul 2013 20:41:26 +0100 -Subject: [PATCH 83/98] dwc_otg: mask correct interrupts after transaction +Subject: [PATCH 66/82] dwc_otg: mask correct interrupts after transaction error recovery The dwc_otg driver will unmask certain interrupts on a transaction @@ -97866,10 +98112,10 @@ index 8e5789f..fd73e41 100644 1.8.4 -From 1c6c2da01833eaf24e572bb5d98e872bd7ec15b9 Mon Sep 17 00:00:00 2001 +From 63e61dfa9152ceac4c7b7a8c316fee0cf10cfad0 Mon Sep 17 00:00:00 2001 From: P33M Date: Sat, 13 Jul 2013 21:48:41 +0100 -Subject: [PATCH 84/98] dwc_otg: fiq: prevent FIQ thrash and incorrect state +Subject: [PATCH 67/82] dwc_otg: fiq: prevent FIQ thrash and incorrect state passing to IRQ In the case of a transaction to a device that had previously aborted @@ -97926,10 +98172,10 @@ index fd73e41..2ec0565 100644 1.8.4 -From 209604d729b57d3bd3b23502b63db04ce60e85f2 Mon Sep 17 00:00:00 2001 +From 16417807fd34069f47d28b4c68f3f55d33204dcc Mon Sep 17 00:00:00 2001 From: Gordon Hollingworth Date: Mon, 8 Jul 2013 04:12:19 +0100 -Subject: [PATCH 85/98] Fix function tracing +Subject: [PATCH 68/82] Fix function tracing --- drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 12 ++++++------ @@ -97994,10 +98240,10 @@ index 2ec0565..083b1c3 100644 1.8.4 -From f4b655bb91e1acd6edb035c376c2d521d76f1950 Mon Sep 17 00:00:00 2001 +From 760ef0f0be87a6c12ba2d8a84c507c18ad20d833 Mon Sep 17 00:00:00 2001 From: P33M Date: Thu, 18 Jul 2013 16:32:41 +0100 -Subject: [PATCH 86/98] dwc_otg: whitespace cleanup in dwc_otg_urb_enqueue +Subject: [PATCH 69/82] dwc_otg: whitespace cleanup in dwc_otg_urb_enqueue --- drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 53 ++++++++++++++-------------- @@ -98084,10 +98330,10 @@ index d1c5c2b..315c803 100644 1.8.4 -From b222727cdf29a3fe84504c960401ce365cf4c924 Mon Sep 17 00:00:00 2001 +From 3798869b67bd8d0562ad2ce92cb95a68e3c16cc0 Mon Sep 17 00:00:00 2001 From: P33M Date: Thu, 18 Jul 2013 17:07:26 +0100 -Subject: [PATCH 87/98] dwc_otg: prevent OOPSes during device disconnects +Subject: [PATCH 70/82] dwc_otg: prevent OOPSes during device disconnects The dwc_otg_urb_enqueue function is thread-unsafe. In particular the access of urb->hcpriv, usb_hcd_link_urb_to_ep, dwc_otg_urb->qtd and @@ -98228,10 +98474,10 @@ index 7b92025..db95851 100644 1.8.4 -From aed74e90a046ffda736b3c4f730a83600b9cd670 Mon Sep 17 00:00:00 2001 +From d9713eaaf34a55fffcf3e2f4c53ba8af74601045 Mon Sep 17 00:00:00 2001 From: P33M Date: Mon, 22 Jul 2013 14:08:26 +0100 -Subject: [PATCH 88/98] dwc_otg: prevent BUG() in TT allocation if hub address +Subject: [PATCH 71/82] dwc_otg: prevent BUG() in TT allocation if hub address is > 16 A fixed-size array is used to track TT allocation. This was @@ -98321,10 +98567,10 @@ index 083b1c3..c76910d 100644 1.8.4 -From e866cf025cd42df58ab2068cba237a803d28531b Mon Sep 17 00:00:00 2001 +From 6e443da697427a4de231fdd651f9f430e76043bc Mon Sep 17 00:00:00 2001 From: P33M Date: Tue, 23 Jul 2013 14:15:32 +0100 -Subject: [PATCH 89/98] dwc_otg: make channel halts with unknown state less +Subject: [PATCH 72/82] dwc_otg: make channel halts with unknown state less damaging If the IRQ received a channel halt interrupt through the FIQ @@ -98369,10 +98615,10 @@ index c76910d..5fd8613 100644 1.8.4 -From 3394d2d3d4ff0a694a76fe67ab822eee30531aa7 Mon Sep 17 00:00:00 2001 +From 29bca904c787fbaad871d5cadfd71ce6f9bef590 Mon Sep 17 00:00:00 2001 From: P33M Date: Tue, 30 Jul 2013 09:58:48 +0100 -Subject: [PATCH 90/98] dwc_otg: fiq_split: use TTs with more granularity +Subject: [PATCH 73/82] dwc_otg: fiq_split: use TTs with more granularity This fixes certain issues with split transaction scheduling. @@ -98492,264 +98738,10 @@ index 5fd8613..a959a49 100644 1.8.4 -From b1bfbb1915325d7eca03e33659ff90eb07062d66 Mon Sep 17 00:00:00 2001 -From: Matthew Hails -Date: Mon, 13 May 2013 14:22:48 +0100 -Subject: [PATCH 91/98] VCHIQ: Fix mem leak of USER_SERVICE_T objects. - -The userdata for VCHIQ services created through the ioctl API is -a kmalloced structure. These objects were getting leaked, most -notably in vchiq_release(), where the service could be closed, -freed and removed from the service list before the wait-to-die -loop was entered. - -This change adds a userdata termination callback, and implements -it in the case where USER_SERVICE_T is used for the service -userdata. ---- - .../vc04_services/interface/vchiq_arm/vchiq_arm.c | 21 +++++++++++++-------- - .../vc04_services/interface/vchiq_arm/vchiq_core.c | 6 +++++- - .../vc04_services/interface/vchiq_arm/vchiq_core.h | 5 ++++- - .../interface/vchiq_arm/vchiq_kern_lib.c | 6 ++++-- - 4 files changed, 26 insertions(+), 12 deletions(-) - -diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c -index f87bbdd..f44d4b4 100644 ---- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c -+++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c -@@ -359,6 +359,17 @@ struct vchiq_instance_struct { - - /**************************************************************************** - * -+* user_service_free -+* -+***************************************************************************/ -+static void -+user_service_free(void *userdata) -+{ -+ kfree(userdata); -+} -+ -+/**************************************************************************** -+* - * vchiq_ioctl - * - ***************************************************************************/ -@@ -467,7 +478,7 @@ struct vchiq_instance_struct { - service = vchiq_add_service_internal( - instance->state, - &args.params, srvstate, -- instance); -+ instance, user_service_free); - - if (service != NULL) { - user_service->service = service; -@@ -490,8 +501,6 @@ struct vchiq_instance_struct { - service = NULL; - ret = (status == VCHIQ_RETRY) ? - -EINTR : -EIO; -- user_service->service = NULL; -- user_service->instance = NULL; - break; - } - } -@@ -503,7 +512,6 @@ struct vchiq_instance_struct { - sizeof(service->handle)) != 0) { - ret = -EFAULT; - vchiq_remove_service(service->handle); -- kfree(user_service); - } - - service = NULL; -@@ -796,10 +804,8 @@ struct vchiq_instance_struct { - } - - if (completion->reason == -- VCHIQ_SERVICE_CLOSED) { -+ VCHIQ_SERVICE_CLOSED) - unlock_service(service); -- kfree(user_service); -- } - - if (copy_to_user((void __user *)( - (size_t)args.buf + -@@ -1151,7 +1157,6 @@ struct vchiq_instance_struct { - spin_unlock(&msg_queue_spinlock); - - unlock_service(service); -- kfree(user_service); - } - - /* Release any closed services */ -diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c -index 2efb124..9f66704 100644 ---- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c -+++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c -@@ -273,6 +273,9 @@ static const char *msg_type_str(unsigned int msg_type) - } - spin_unlock(&service_spinlock); - -+ if (service && service->userdata_term) -+ service->userdata_term(service->base.userdata); -+ - kfree(service); - } - -@@ -2476,7 +2479,7 @@ static const char *msg_type_str(unsigned int msg_type) - VCHIQ_SERVICE_T * - vchiq_add_service_internal(VCHIQ_STATE_T *state, - const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, -- VCHIQ_INSTANCE_T instance) -+ VCHIQ_INSTANCE_T instance, VCHIQ_USERDATA_TERM_T userdata_term) - { - VCHIQ_SERVICE_T *service; - -@@ -2488,6 +2491,7 @@ static const char *msg_type_str(unsigned int msg_type) - service->handle = VCHIQ_SERVICE_HANDLE_INVALID; - service->ref_count = 1; - service->srvstate = VCHIQ_SRVSTATE_FREE; -+ service->userdata_term = userdata_term; - service->localport = VCHIQ_PORT_FREE; - service->remoteport = VCHIQ_PORT_FREE; - -diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h -index bddfc6a..47cdf27 100644 ---- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h -+++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h -@@ -237,6 +237,8 @@ enum { - VCHIQ_BULK_RECEIVE - } VCHIQ_BULK_DIR_T; - -+typedef void (*VCHIQ_USERDATA_TERM_T)(void *userdata); -+ - typedef struct vchiq_bulk_struct { - short mode; - short dir; -@@ -284,6 +286,7 @@ enum { - VCHIQ_SERVICE_HANDLE_T handle; - unsigned int ref_count; - int srvstate; -+ VCHIQ_USERDATA_TERM_T userdata_term; - unsigned int localport; - unsigned int remoteport; - int public_fourcc; -@@ -534,7 +537,7 @@ struct bulk_waiter { - extern VCHIQ_SERVICE_T * - vchiq_add_service_internal(VCHIQ_STATE_T *state, - const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, -- VCHIQ_INSTANCE_T instance); -+ VCHIQ_INSTANCE_T instance, VCHIQ_USERDATA_TERM_T userdata_term); - - extern VCHIQ_STATUS_T - vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id); -diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c -index 62965c6..be9735f 100644 ---- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c -+++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c -@@ -241,7 +241,8 @@ VCHIQ_STATUS_T vchiq_add_service( - state, - params, - srvstate, -- instance); -+ instance, -+ NULL); - - if (service) { - *phandle = service->handle; -@@ -282,7 +283,8 @@ VCHIQ_STATUS_T vchiq_open_service( - service = vchiq_add_service_internal(state, - params, - VCHIQ_SRVSTATE_OPENING, -- instance); -+ instance, -+ NULL); - - if (service) { - status = vchiq_open_service_internal(service, current->pid); --- -1.8.4 - - -From abaa5025cfedb517ae41bf312522c475a18119bc Mon Sep 17 00:00:00 2001 -From: Philip Taylor -Date: Tue, 28 May 2013 17:20:49 +0100 -Subject: [PATCH 92/98] vchiq_util: Fix race condition in push/pop - -The lack of memory barriers could (very rarely) result in -vchiu_queue_pop reading the next value before it had been written -(getting either NULL, or a value that had been popped once already). ---- - .../vc04_services/interface/vchiq_arm/vchiq_util.c | 31 ++++++++++++++++++++++ - 1 file changed, 31 insertions(+) - -diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c -index 03cece571b..c2eefef 100644 ---- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c -+++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c -@@ -81,8 +81,20 @@ void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header) - } - } - -+ /* -+ * Write to queue->storage must be visible after read from -+ * queue->read -+ */ -+ smp_mb(); -+ - queue->storage[queue->write & (queue->size - 1)] = header; - -+ /* -+ * Write to queue->storage must be visible before write to -+ * queue->write -+ */ -+ smp_wmb(); -+ - queue->write++; - - up(&queue->push); -@@ -97,6 +109,13 @@ VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue) - } - - up(&queue->push); // We haven't removed anything from the queue. -+ -+ /* -+ * Read from queue->storage must be visible after read from -+ * queue->write -+ */ -+ smp_rmb(); -+ - return queue->storage[queue->read & (queue->size - 1)]; - } - -@@ -110,8 +129,20 @@ VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue) - } - } - -+ /* -+ * Read from queue->storage must be visible after read from -+ * queue->write -+ */ -+ smp_rmb(); -+ - header = queue->storage[queue->read & (queue->size - 1)]; - -+ /* -+ * Read from queue->storage must be visible before write to -+ * queue->read -+ */ -+ smp_mb(); -+ - queue->read++; - - up(&queue->pop); --- -1.8.4 - - -From 8a46856b89047002657183e23e10f95c62b183f7 Mon Sep 17 00:00:00 2001 +From 1471953a4bfae9a23f6a08844f41ff580c21f68a Mon Sep 17 00:00:00 2001 From: P33M Date: Fri, 2 Aug 2013 10:04:18 +0100 -Subject: [PATCH 93/98] dwc_otg: fix potential sleep while atomic during urb +Subject: [PATCH 74/82] dwc_otg: fix potential sleep while atomic during urb enqueue Fixes a regression introduced with eb1b482a. Kmalloc called from @@ -98778,10 +98770,10 @@ index 87e517d..88c0544 100644 1.8.4 -From e645415e6b6bb20411efa607fcd6255074cd256a Mon Sep 17 00:00:00 2001 +From 4fbcf5bf785808166d063f6fd7e889c72e41d7be Mon Sep 17 00:00:00 2001 From: P33M Date: Mon, 5 Aug 2013 11:42:12 +0100 -Subject: [PATCH 94/98] dwc_otg: make fiq_split_enable imply fiq_fix_enable +Subject: [PATCH 75/82] dwc_otg: make fiq_split_enable imply fiq_fix_enable Failing to set up the FIQ correctly would result in "IRQ 32: nobody cared" errors in dmesg. @@ -98810,10 +98802,10 @@ index 176dc14..f06c3d2 100644 1.8.4 -From 69f33fc4b90b0a5daa5f23186726e1deea5c4945 Mon Sep 17 00:00:00 2001 +From 39b26759190e28cbc3ec49c88232990fbedf4162 Mon Sep 17 00:00:00 2001 From: P33M Date: Mon, 5 Aug 2013 11:47:12 +0100 -Subject: [PATCH 95/98] dwc_otg: prevent crashes on host port disconnects +Subject: [PATCH 76/82] dwc_otg: prevent crashes on host port disconnects Fix several issues resulting in crashes or inconsistent state if a Model A root port was disconnected. @@ -98971,10 +98963,10 @@ index 88c0544..ae4271a 100644 1.8.4 -From 1b35f8f34cfe123a2acd0fbb6ebced1f41c74b1f Mon Sep 17 00:00:00 2001 +From 5e060de08fcc5defa2863c66473541b992c28759 Mon Sep 17 00:00:00 2001 From: P33M Date: Mon, 5 Aug 2013 13:17:58 +0100 -Subject: [PATCH 96/98] dwc_otg: prevent leaking URBs during enqueue +Subject: [PATCH 77/82] dwc_otg: prevent leaking URBs during enqueue A dwc_otg_urb would get leaked if the HCD enqueue function failed for any reason. Free the URB at the appropriate points. @@ -99010,168 +99002,138 @@ index ae4271a..ee8eec9 100644 1.8.4 -From 9f8c1e55a0726ab617725053a499d257bc013ffa Mon Sep 17 00:00:00 2001 +From f87c55a6420947fb19f480623712ba5a8c14d272 Mon Sep 17 00:00:00 2001 +From: P33M +Date: Fri, 20 Sep 2013 16:08:27 +0100 +Subject: [PATCH 79/82] dwc_otg: Enable NAK holdoff for control split + transactions + +Certain low-speed devices take a very long time to complete a +data or status stage of a control transaction, producing NAK +responses until they complete internal processing - the USB2.0 +spec limit is up to 500mS. This causes the same type of interrupt +storm as seen with USB-serial dongles prior to c8edb238. + +In certain circumstances, usually while booting, this interrupt +storm could cause SD card timeouts. +--- + drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +index 3a549a1..f8dc4be 100644 +--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +@@ -1857,8 +1857,7 @@ static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd, + */ + switch(dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { + case UE_BULK: +- //case UE_INTERRUPT: +- //case UE_CONTROL: ++ case UE_CONTROL: + if (nak_holdoff_enable) + hc->qh->nak_frame = dwc_otg_hcd_get_frame_number(hcd); + } +-- +1.8.4 + + +From af6315d795eb6221491046befc8cc593e28b000e Mon Sep 17 00:00:00 2001 From: popcornmix -Date: Mon, 19 Aug 2013 15:21:22 +0100 -Subject: [PATCH 97/98] Changes for new NOOBS multi partition booting from gsh +Date: Fri, 20 Sep 2013 19:07:56 +0100 +Subject: [PATCH 80/82] dwc_otg: Fix for occasional lockup on boot when doing a + USB reset --- - arch/arm/kernel/process.c | 10 ++++++++ - arch/arm/mach-bcm2708/bcm2708.c | 56 ++++++++++++++++++++++++++++++++--------- - 2 files changed, 54 insertions(+), 12 deletions(-) + drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c -index 94f6b05..dd67686 100644 ---- a/arch/arm/kernel/process.c -+++ b/arch/arm/kernel/process.c -@@ -176,6 +176,16 @@ void arch_cpu_idle(void) - default_idle(); - } - -+char bcm2708_reboot_mode = 'h'; -+ -+int __init reboot_setup(char *str) -+{ -+ bcm2708_reboot_mode = str[0]; -+ return 1; -+} -+ -+__setup("reboot=", reboot_setup); -+ - /* - * Called by kexec, immediately prior to machine_kexec(). - * -diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 68c577a..3fe7626 100644 ---- a/arch/arm/mach-bcm2708/bcm2708.c -+++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -83,6 +83,7 @@ - /* command line parameters */ - static unsigned boardrev, serial; - static unsigned uart_clock; -+static unsigned reboot_part = 0; - - static void __init bcm2708_init_led(void); - -@@ -624,20 +625,43 @@ int __init bcm_register_device(struct platform_device *pdev) - return ret; - } - --static void bcm2708_restart(char mode, const char *cmd) -+int calc_rsts(int partition) - { -+ return PM_PASSWORD | -+ ((partition & (1 << 0)) << 0) | -+ ((partition & (1 << 1)) << 1) | -+ ((partition & (1 << 2)) << 2) | -+ ((partition & (1 << 3)) << 3) | -+ ((partition & (1 << 4)) << 4) | -+ ((partition & (1 << 5)) << 5); -+} -+ -+static void bcm2708_restart(enum reboot_mode mode, const char *cmd) -+{ -+ extern char bcm2708_reboot_mode; - uint32_t pm_rstc, pm_wdog; - uint32_t timeout = 10; -+ uint32_t pm_rsts = 0; - -- /* For quick reset notification add reboot=q to cmdline -- */ -- if(mode == 'q') -+ if(bcm2708_reboot_mode == 'q') - { -- uint32_t pm_rsts = readl(__io_address(PM_RSTS)); -+ // NOOBS < 1.3 booting with reboot=q -+ pm_rsts = readl(__io_address(PM_RSTS)); - pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET; -- writel(pm_rsts, __io_address(PM_RSTS)); -+ } -+ else if(bcm2708_reboot_mode == 'p') -+ { -+ // NOOBS < 1.3 halting -+ pm_rsts = readl(__io_address(PM_RSTS)); -+ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET; -+ } -+ else -+ { -+ pm_rsts = calc_rsts(reboot_part); +diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +index f8dc4be..64d33a5 100644 +--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +@@ -742,8 +742,8 @@ int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd) } -+ writel(pm_rsts, __io_address(PM_RSTS)); -+ - /* Setup watchdog for reset */ - pm_rstc = readl(__io_address(PM_RSTC)); + /* Clear interrupt */ +- //gintsts.b.sofintr = 1; +- //DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32); ++ gintsts.b.sofintr = 1; ++ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32); -@@ -651,12 +675,19 @@ static void bcm2708_restart(char mode, const char *cmd) - /* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */ - static void bcm2708_power_off(void) - { -- /* we set the watchdog hard reset bit here to distinguish this reset from the normal (full) reset. bootcode.bin will not reboot after a hard reset */ -- uint32_t pm_rsts = readl(__io_address(PM_RSTS)); -- pm_rsts = PM_PASSWORD | (pm_rsts & PM_RSTC_WRCFG_CLR) | PM_RSTS_HADWRH_SET; -- writel(pm_rsts, __io_address(PM_RSTS)); -- /* continue with normal reset mechanism */ -- bcm2708_restart(0, ""); -+ extern char bcm2708_reboot_mode; -+ if(bcm2708_reboot_mode == 'q') -+ { -+ // NOOBS < v1.3 -+ bcm2708_restart('p', ""); -+ } -+ else -+ { -+ /* partition 63 is special code for HALT the bootloader knows not to boot*/ -+ reboot_part = 63; -+ /* continue with normal reset mechanism */ -+ bcm2708_restart(0, ""); -+ } - } - - void __init bcm2708_init(void) -@@ -883,3 +914,4 @@ static void __init board_reserve(void) - module_param(boardrev, uint, 0644); - module_param(serial, uint, 0644); - module_param(uart_clock, uint, 0644); -+module_param(reboot_part, uint, 0644); --- -1.8.4 - - -From d7474694bdc9836af17f4b4d839509f9aad7ffa7 Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Wed, 20 Mar 2013 09:58:21 +0000 -Subject: [PATCH 98/98] SW-11786: Fix USE_AFTER_FREE defect (61220) - -In the error paths of parse_open, only unlock the service if it is not -NULL. In the fail path, NULL the service after it is unlocked to -prevent a double unlock. ---- - drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c -index 9f66704..f35ed4f 100644 ---- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c -+++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c -@@ -1492,6 +1492,7 @@ static const char *msg_type_str(unsigned int msg_type) - version, version_min); - vchiq_loud_error_footer(); - unlock_service(service); -+ service = NULL; - goto fail_open; - } - service->peer_version = version; -@@ -1557,7 +1558,8 @@ static const char *msg_type_str(unsigned int msg_type) return 1; - - bail_not_ready: -- unlock_service(service); -+ if (service) -+ unlock_service(service); - - return 0; } -- 1.8.4 + +From dc8b6fedf169cc022e3729dab011e0b2b770d93b Mon Sep 17 00:00:00 2001 +From: P33M +Date: Fri, 27 Sep 2013 14:42:24 +0100 +Subject: [PATCH 81/82] dwc_otg: Don't issue traffic to LS devices in FS mode + +Issuing low-speed packets when the root port is in full-speed mode +causes the root port to stop responding. Explicitly fail when +enqueuing URBs to a LS endpoint on a FS bus. +--- + drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +index 1904f6a..22300f0 100644 +--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c ++++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +@@ -501,6 +501,7 @@ int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd, + dwc_otg_transaction_type_e tr_type; + dwc_otg_qtd_t *qtd; + gintmsk_data_t intr_mask = {.d32 = 0 }; ++ hprt0_data_t hprt0 = { .d32 = 0 }; + + #ifdef DEBUG /* integrity checks (Broadcom) */ + if (NULL == hcd->core_if) { +@@ -515,6 +516,16 @@ int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd, + return -DWC_E_NO_DEVICE; + } + ++ /* Some core configurations cannot support LS traffic on a FS root port */ ++ if ((hcd->fops->speed(hcd, dwc_otg_urb->priv) == USB_SPEED_LOW) && ++ (hcd->core_if->hwcfg2.b.fs_phy_type == 1) && ++ (hcd->core_if->hwcfg2.b.hs_phy_type == 1)) { ++ hprt0.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0); ++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) { ++ return -DWC_E_NO_DEVICE; ++ } ++ } ++ + qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc); + if (qtd == NULL) { + DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n"); +-- +1.8.4 + + +From c7768e2beacacbef7d6d05f40f45f0aa96cf7082 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Sat, 9 Nov 2013 17:42:58 +0000 +Subject: [PATCH 82/82] mmc: Report 3.3V support in caps + +--- + drivers/mmc/host/sdhci-bcm2708.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-bcm2708.c b/drivers/mmc/host/sdhci-bcm2708.c +index 45499d8..6ef7899 100644 +--- a/drivers/mmc/host/sdhci-bcm2708.c ++++ b/drivers/mmc/host/sdhci-bcm2708.c +@@ -1282,6 +1282,8 @@ static int sdhci_bcm2708_probe(struct platform_device *pdev) + host_priv->dma_chan, host_priv->dma_chan_base, + host_priv->dma_irq); + ++ // we support 3.3V ++ host->caps |= SDHCI_CAN_VDD_330; + if (allow_highspeed) + host->mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; + +-- +1.8.4 +