Mesa: Fix performance regression when sw decoding on AMD APUs

packages/graphics/Mesa/patches/Mesa-1002-Revert-r600g-radeonsi-Always-use-GTT-again-for-PIPE_.patch

@@ -0,0 +1,33 @@
+From 2402ec06e7d968bfa2dd06d73d5d9a5096fcfbb5 Mon Sep 17 00:00:00 2001
+From: fritsch <Peter.Fruehberger@gmail.com>
+Date: Tue, 3 Feb 2015 10:10:48 +0100
+Subject: [PATCH 2/3] Revert "r600g,radeonsi: Always use GTT again for
+ PIPE_USAGE_STREAM buffers"
+
+This reverts commit 64c2bdc334ba472603b1e7cd2c3046cfbce285b6.
+---
+ src/gallium/drivers/radeon/r600_buffer_common.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
+index acdabc0..ee05776 100644
+--- a/src/gallium/drivers/radeon/r600_buffer_common.c
++++ b/src/gallium/drivers/radeon/r600_buffer_common.c
+@@ -110,13 +110,11 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
+ 	enum radeon_bo_flag flags = 0;
+ 
+ 	switch (res->b.b.usage) {
+-	case PIPE_USAGE_STREAM:
+-		flags = RADEON_FLAG_GTT_WC;
+-		/* fall through */
+ 	case PIPE_USAGE_STAGING:
+ 		/* Transfers are likely to occur more often with these resources. */
+ 		res->domains = RADEON_DOMAIN_GTT;
+ 		break;
++	case PIPE_USAGE_STREAM:
+ 	case PIPE_USAGE_DYNAMIC:
+ 		/* Older kernels didn't always flush the HDP cache before
+ 		 * CS execution
+-- 
+1.9.1
+