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Merge pull request #7333 from jernejsk/opi3-lts
Allwinner: Add OrangePi 3 LTS support
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@ -1968,7 +1968,7 @@ CONFIG_MICREL_PHY=y
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CONFIG_MICROCHIP_PHY=m
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CONFIG_MICROCHIP_PHY=m
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# CONFIG_MICROCHIP_T1_PHY is not set
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# CONFIG_MICROCHIP_T1_PHY is not set
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# CONFIG_MICROSEMI_PHY is not set
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# CONFIG_MICROSEMI_PHY is not set
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# CONFIG_MOTORCOMM_PHY is not set
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CONFIG_MOTORCOMM_PHY=y
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# CONFIG_NATIONAL_PHY is not set
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# CONFIG_NATIONAL_PHY is not set
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# CONFIG_NXP_C45_TJA11XX_PHY is not set
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# CONFIG_NXP_C45_TJA11XX_PHY is not set
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# CONFIG_NXP_TJA11XX_PHY is not set
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# CONFIG_NXP_TJA11XX_PHY is not set
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@ -0,0 +1,150 @@
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From git@z Thu Jan 1 00:00:00 1970
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Subject: [PATCH] net: phy: add support for Motorcomm yt8531C phy
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Sun, 09 Oct 2022 22:24:05 +0300
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Message-Id: <20221009192405.97118-1-f.kardame@manjaro.org>
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MIME-Version: 1.0
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Content-Type: text/plain; charset="utf-8"
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Content-Transfer-Encoding: 7bit
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This patch adds support for Motorcomm YT8531C which is
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used in OrangePi 3 LTS, OrangePi 4 LTS and OrangePi 800
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Currently being used by Manjaro Arm kernel
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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Signed-off-by: Furkan Kardame <f.kardame@manjaro.org>
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---
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drivers/net/phy/motorcomm.c | 90 +++++++++++++++++++++++++++++++++++++
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1 file changed, 90 insertions(+)
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diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
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index 7e6ac2c5e..cbc8ef15d 100644
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--- a/drivers/net/phy/motorcomm.c
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+++ b/drivers/net/phy/motorcomm.c
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@@ -10,6 +10,7 @@
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#include <linux/phy.h>
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#define PHY_ID_YT8511 0x0000010a
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+#define PHY_ID_YT8531 0x4f51e91b
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#define YT8511_PAGE_SELECT 0x1e
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#define YT8511_PAGE 0x1f
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@@ -38,6 +39,38 @@
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#define YT8511_DELAY_FE_TX_EN (0xf << 12)
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#define YT8511_DELAY_FE_TX_DIS (0x2 << 12)
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+#define YT8531_RGMII_CONFIG1 0xa003
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+
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+/* TX Gig-E Delay is bits 3:0, default 0x1
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+ * TX Fast-E Delay is bits 7:4, default 0xf
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+ * RX Delay is bits 13:10, default 0x0
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+ * Delay = 150ps * N
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+ * On = 2000ps, off = 50ps
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+ */
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+#define YT8531_DELAY_GE_TX_EN (0xd << 0)
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+#define YT8531_DELAY_GE_TX_DIS (0x0 << 0)
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+#define YT8531_DELAY_FE_TX_EN (0xd << 4)
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+#define YT8531_DELAY_FE_TX_DIS (0x0 << 4)
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+#define YT8531_DELAY_RX_EN (0xd << 10)
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+#define YT8531_DELAY_RX_DIS (0x0 << 10)
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+#define YT8531_DELAY_MASK (GENMASK(13, 10) | GENMASK(7, 0))
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+
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+#define YT8531_SYNCE_CFG 0xa012
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+
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+/* Clk src config is bits 3:1
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+ * 3b000 src from pll
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+ * 3b001 src from rx_clk
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+ * 3b010 src from serdes
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+ * 3b011 src from ptp_in
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+ * 3b100 src from 25mhz refclk *default*
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+ * 3b101 src from 25mhz ssc
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+ * Clk rate select is bit 4
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+ * 1b0 25mhz clk output *default*
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+ * 1b1 125mhz clk output
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+ * Clkout enable is bit 6
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+ */
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+#define YT8531_CLKCFG_125M (BIT(6) | BIT(4) | (0x0 < 1))
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+
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static int yt8511_read_page(struct phy_device *phydev)
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{
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return __phy_read(phydev, YT8511_PAGE_SELECT);
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@@ -111,6 +145,51 @@ static int yt8511_config_init(struct phy_device *phydev)
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return phy_restore_page(phydev, oldpage, ret);
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}
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+static int yt8531_config_init(struct phy_device *phydev)
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+{
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+ int oldpage, ret = 0;
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+ unsigned int val;
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+
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+ oldpage = phy_select_page(phydev, YT8531_RGMII_CONFIG1);
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+ if (oldpage < 0)
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+ goto err_restore_page;
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+
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+ /* set rgmii delay mode */
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+ switch (phydev->interface) {
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+ case PHY_INTERFACE_MODE_RGMII:
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+ val = YT8531_DELAY_RX_DIS | YT8531_DELAY_GE_TX_DIS | YT8531_DELAY_FE_TX_DIS;
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+ break;
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+ case PHY_INTERFACE_MODE_RGMII_RXID:
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+ val = YT8531_DELAY_RX_EN | YT8531_DELAY_GE_TX_DIS | YT8531_DELAY_FE_TX_DIS;
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+ break;
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+ case PHY_INTERFACE_MODE_RGMII_TXID:
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+ val = YT8531_DELAY_RX_DIS | YT8531_DELAY_GE_TX_EN | YT8531_DELAY_FE_TX_EN;
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+ break;
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+ case PHY_INTERFACE_MODE_RGMII_ID:
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+ val = YT8531_DELAY_RX_EN | YT8531_DELAY_GE_TX_EN | YT8531_DELAY_FE_TX_EN;
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+ break;
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+ default: /* do not support other modes */
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+ ret = -EOPNOTSUPP;
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+ goto err_restore_page;
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+ }
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+
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+ ret = __phy_modify(phydev, YT8511_PAGE, YT8531_DELAY_MASK, val);
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+ if (ret < 0)
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+ goto err_restore_page;
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+
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+ /* set clock mode to 125mhz */
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+ ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8531_SYNCE_CFG);
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+ if (ret < 0)
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+ goto err_restore_page;
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+
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+ ret = __phy_write(phydev, YT8511_PAGE, YT8531_CLKCFG_125M);
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+ if (ret < 0)
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+ goto err_restore_page;
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+
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+err_restore_page:
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+ return phy_restore_page(phydev, oldpage, ret);
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+}
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+
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static struct phy_driver motorcomm_phy_drvs[] = {
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{
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PHY_ID_MATCH_EXACT(PHY_ID_YT8511),
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@@ -120,7 +200,16 @@ static struct phy_driver motorcomm_phy_drvs[] = {
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.resume = genphy_resume,
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.read_page = yt8511_read_page,
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.write_page = yt8511_write_page,
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+ }, {
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+ PHY_ID_MATCH_EXACT(PHY_ID_YT8531),
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+ .name = "YT8531 Gigabit Ethernet",
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+ .config_init = yt8531_config_init,
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+ .suspend = genphy_suspend,
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+ .resume = genphy_resume,
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+ .read_page = yt8511_read_page,
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+ .write_page = yt8511_write_page,
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},
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+
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};
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module_phy_driver(motorcomm_phy_drvs);
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@@ -131,6 +220,7 @@ MODULE_LICENSE("GPL");
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static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = {
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{ PHY_ID_MATCH_EXACT(PHY_ID_YT8511) },
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+ { PHY_ID_MATCH_EXACT(PHY_ID_YT8531) },
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{ /* sentinal */ }
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};
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--
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2.37.3
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@ -0,0 +1,59 @@
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From 6f4abbea26de4ef963e9edd8eb051f5e7f2e0c6c Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@gmail.com>
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Date: Mon, 2 Jan 2023 15:49:59 +0100
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Subject: [PATCH] OrangePi 3 LTS support
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Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
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---
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arch/arm64/boot/dts/allwinner/Makefile | 1 +
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.../allwinner/sun50i-h6-orangepi-3-lts.dts | 26 +++++++++++++++++++
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2 files changed, 27 insertions(+)
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create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
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diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
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index 6a96494a2e0a..ace8159a6324 100644
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--- a/arch/arm64/boot/dts/allwinner/Makefile
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+++ b/arch/arm64/boot/dts/allwinner/Makefile
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@@ -32,6 +32,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-beelink-gs1.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb
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+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3-lts.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
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new file mode 100644
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index 000000000000..0e490936b50c
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--- /dev/null
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
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@@ -0,0 +1,26 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+// Copyright (C) 2023 Jernej Skrabec <jernej.skrabec@gmail.com>
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+
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+#include "sun50i-h6-orangepi-3.dts"
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+
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+/ {
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+ model = "OrangePi 3 LTS";
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+ compatible = "xunlong,orangepi-3-lts", "allwinner,sun50i-h6";
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+};
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+
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+&emac {
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+ allwinner,rx-delay-ps = <200>;
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+ allwinner,tx-delay-ps = <300>;
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+};
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+
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+&mmc1 {
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+ status = "disabled";
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+};
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+
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+&r_rsb {
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+ clock-frequency = <100000>;
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+};
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+
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+&uart1 {
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+ status = "disabled";
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+};
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--
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2.39.0
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@ -120,6 +120,11 @@ devices = \
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'config': 'orangepi_3_defconfig',
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'config': 'orangepi_3_defconfig',
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'crust_config': 'orangepi_3_defconfig'
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'crust_config': 'orangepi_3_defconfig'
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},
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},
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'orangepi-3-lts': {
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'dtb': 'sun50i-h6-orangepi-3-lts.dtb',
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'config': 'orangepi_3_defconfig',
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'crust_config': 'orangepi_3_defconfig'
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},
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'orangepi-lite2': {
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'orangepi-lite2': {
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'dtb': 'sun50i-h6-orangepi-lite2.dtb',
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'dtb': 'sun50i-h6-orangepi-lite2.dtb',
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'config': 'orangepi_lite2_defconfig',
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'config': 'orangepi_lite2_defconfig',
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