Merge branch 'master' of github.com:OpenELEC/OpenELEC.tv

2025-07-29 13:46:49 +00:00 · 2013-11-25 02:01:41 +01:00 · 2013-11-25 02:01:41 +01:00 · 2e3d49a50f
commit 2e3d49a50f
parent 2756b8ee3c 28bbaa14c1
17 changed files with 1760 additions and 22 deletions
--- a/packages/multimedia/libva-driver-intel/patches.upstream/0001-render-add-support-for-brightness-contrast-hue-satur.patch
+++ b/packages/multimedia/libva-driver-intel/patches.upstream/0001-render-add-support-for-brightness-contrast-hue-satur.patch
@ -0,0 +1,659 @@
 From f81d7beb3f0a849851f232ad5fc1404b4a0c5802 Mon Sep 17 00:00:00 2001
 From: "Xiang, Haihao" <haihao.xiang@intel.com>
 Date: Thu, 26 Sep 2013 11:02:09 +0800
 Subject: [PATCH 1/5] render: add support for
 brightness/contrast/hue/saturation
 Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
 ---
 src/i965_drv_video.c                               | 35 +++++++++-
 src/i965_drv_video.h                               |  9 +++
 src/i965_render.c                                  | 33 +++++++++-
 src/shaders/render/Makefile.am                     | 17 ++++-
 src/shaders/render/exa_wm.g4i                      | 19 ++++++
 src/shaders/render/exa_wm_yuv_color_balance.g4a    | 38 +++++++++++
 src/shaders/render/exa_wm_yuv_color_balance.g4b    | 15 +++++
 .../render/exa_wm_yuv_color_balance.g4b.gen5       | 15 +++++
 src/shaders/render/exa_wm_yuv_color_balance.g6a    | 38 +++++++++++
 src/shaders/render/exa_wm_yuv_color_balance.g6b    | 15 +++++
 src/shaders/render/exa_wm_yuv_color_balance.g7a    | 38 +++++++++++
 src/shaders/render/exa_wm_yuv_color_balance.g7b    | 15 +++++
 .../render/exa_wm_yuv_color_balance.g7b.haswell    | 15 +++++
 src/shaders/render/exa_wm_yuv_color_balance.gxa    | 75 ++++++++++++++++++++++
 14 files changed, 371 insertions(+), 6 deletions(-)
 create mode 100644 src/shaders/render/exa_wm_yuv_color_balance.g4a
 create mode 100644 src/shaders/render/exa_wm_yuv_color_balance.g4b
 create mode 100644 src/shaders/render/exa_wm_yuv_color_balance.g4b.gen5
 create mode 100644 src/shaders/render/exa_wm_yuv_color_balance.g6a
 create mode 100644 src/shaders/render/exa_wm_yuv_color_balance.g6b
 create mode 100644 src/shaders/render/exa_wm_yuv_color_balance.g7a
 create mode 100644 src/shaders/render/exa_wm_yuv_color_balance.g7b
 create mode 100644 src/shaders/render/exa_wm_yuv_color_balance.g7b.haswell
 create mode 100644 src/shaders/render/exa_wm_yuv_color_balance.gxa
 diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
 index 31dafa2..6ed07f1 100755
 --- a/src/i965_drv_video.c
 +++ b/src/i965_drv_video.c
@@ -97,6 +97,30 @@ enum {
 /* List of supported display attributes */
 static const VADisplayAttribute i965_display_attributes[] = {
     {
 +        VADisplayAttribBrightness,
 +        -100, 100, DEFAULT_BRIGHTNESS,
 +        VA_DISPLAY_ATTRIB_GETTABLE | VA_DISPLAY_ATTRIB_SETTABLE
 +    },
 +
 +    {
 +        VADisplayAttribContrast,
 +        0, 100, DEFAULT_CONTRAST,
 +        VA_DISPLAY_ATTRIB_GETTABLE | VA_DISPLAY_ATTRIB_SETTABLE
 +    },
 +
 +    {
 +        VADisplayAttribHue,
 +        -180, 180, DEFAULT_HUE,
 +        VA_DISPLAY_ATTRIB_GETTABLE | VA_DISPLAY_ATTRIB_SETTABLE
 +    },
 +
 +    {
 +        VADisplayAttribSaturation,
 +        0, 100, DEFAULT_SATURATION,
 +        VA_DISPLAY_ATTRIB_GETTABLE | VA_DISPLAY_ATTRIB_SETTABLE
 +    },
 +
 +    {
         VADisplayAttribRotation,
         0, 3, VA_ROTATION_NONE,
         VA_DISPLAY_ATTRIB_GETTABLE|VA_DISPLAY_ATTRIB_SETTABLE
@@ -2410,7 +2434,16 @@ i965_display_attributes_init(VADriverContextP ctx)
     );
     i965->rotation_attrib = get_display_attribute(ctx, VADisplayAttribRotation);
 -    if (!i965->rotation_attrib) {
 +    i965->brightness_attrib = get_display_attribute(ctx, VADisplayAttribBrightness);
 +    i965->contrast_attrib = get_display_attribute(ctx, VADisplayAttribContrast);
 +    i965->hue_attrib = get_display_attribute(ctx, VADisplayAttribHue);
 +    i965->saturation_attrib = get_display_attribute(ctx, VADisplayAttribSaturation);
 +
 +    if (!i965->rotation_attrib ||
 +        !i965->brightness_attrib ||
 +        !i965->contrast_attrib ||
 +        !i965->hue_attrib ||
 +        !i965->saturation_attrib) {
         goto error;
     }
     return true;
 diff --git a/src/i965_drv_video.h b/src/i965_drv_video.h
 index a0e7790..3b06ac0 100644
 --- a/src/i965_drv_video.h
 +++ b/src/i965_drv_video.h
@@ -59,6 +59,11 @@
 #define I965_SURFACE_FLAG_TOP_FIELD_FIRST       0x00000001
 #define I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST   0x00000002
 +#define DEFAULT_BRIGHTNESS      0
 +#define DEFAULT_CONTRAST        10
 +#define DEFAULT_HUE             0
 +#define DEFAULT_SATURATION      10
 +
 struct i965_surface
 {
     struct object_base *base;
@@ -321,6 +326,10 @@ struct i965_driver_data
     VADisplayAttribute *display_attributes;
     unsigned int num_display_attributes;
     VADisplayAttribute *rotation_attrib;
 +    VADisplayAttribute *brightness_attrib;
 +    VADisplayAttribute *contrast_attrib;
 +    VADisplayAttribute *hue_attrib;
 +    VADisplayAttribute *saturation_attrib;
     VAContextID current_context_id;
     /* VA/DRI (X11) specific data */
 diff --git a/src/i965_render.c b/src/i965_render.c
 index 26a7baf..b4fd29b 100644
 --- a/src/i965_render.c
 +++ b/src/i965_render.c
@@ -35,6 +35,7 @@
 #include <stdlib.h>
 #include <string.h>
 #include <assert.h>
 +#include <math.h>
 #include <va/va_drmcommon.h>
@@ -64,6 +65,7 @@ static const uint32_t ps_kernel_static[][4] =
 #include "shaders/render/exa_wm_xy.g4b"
 #include "shaders/render/exa_wm_src_affine.g4b"
 #include "shaders/render/exa_wm_src_sample_planar.g4b"
 +#include "shaders/render/exa_wm_yuv_color_balance.g4b"
 #include "shaders/render/exa_wm_yuv_rgb.g4b"
 #include "shaders/render/exa_wm_write.g4b"
 };
@@ -86,6 +88,7 @@ static const uint32_t ps_kernel_static_gen5[][4] =
 #include "shaders/render/exa_wm_xy.g4b.gen5"
 #include "shaders/render/exa_wm_src_affine.g4b.gen5"
 #include "shaders/render/exa_wm_src_sample_planar.g4b.gen5"
 +#include "shaders/render/exa_wm_yuv_color_balance.g4b.gen5"
 #include "shaders/render/exa_wm_yuv_rgb.g4b.gen5"
 #include "shaders/render/exa_wm_write.g4b.gen5"
 };
@@ -105,6 +108,7 @@ static const uint32_t sf_kernel_static_gen6[][4] =
 static const uint32_t ps_kernel_static_gen6[][4] = {
 #include "shaders/render/exa_wm_src_affine.g6b"
 #include "shaders/render/exa_wm_src_sample_planar.g6b"
 +#include "shaders/render/exa_wm_yuv_color_balance.g6b"
 #include "shaders/render/exa_wm_yuv_rgb.g6b"
 #include "shaders/render/exa_wm_write.g6b"
 };
@@ -123,6 +127,7 @@ static const uint32_t sf_kernel_static_gen7[][4] =
 static const uint32_t ps_kernel_static_gen7[][4] = {
 #include "shaders/render/exa_wm_src_affine.g7b"
 #include "shaders/render/exa_wm_src_sample_planar.g7b"
 +#include "shaders/render/exa_wm_yuv_color_balance.g7b"
 #include "shaders/render/exa_wm_yuv_rgb.g7b"
 #include "shaders/render/exa_wm_write.g7b"
 };
@@ -137,6 +142,7 @@ static const uint32_t ps_subpic_kernel_static_gen7[][4] = {
 static const uint32_t ps_kernel_static_gen7_haswell[][4] = {
 #include "shaders/render/exa_wm_src_affine.g7b"
 #include "shaders/render/exa_wm_src_sample_planar.g7b.haswell"
 +#include "shaders/render/exa_wm_yuv_color_balance.g7b.haswell"
 #include "shaders/render/exa_wm_yuv_rgb.g7b"
 #include "shaders/render/exa_wm_write.g7b"
 };
@@ -1050,6 +1056,8 @@ i965_render_upload_vertex(
     i965_fill_vertex_buffer(ctx, tex_coords, vid_coords);
 }
 +#define PI  3.1415926
 +
 static void
 i965_render_upload_constants(VADriverContextP ctx,
                              struct object_surface *obj_surface)
@@ -1057,6 +1065,11 @@ i965_render_upload_constants(VADriverContextP ctx,
     struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct i965_render_state *render_state = &i965->render_state;
     unsigned short *constant_buffer;
 +    float *color_balance_base;
 +    float contrast = (float)i965->contrast_attrib->value / DEFAULT_CONTRAST;
 +    float brightness = (float)i965->brightness_attrib->value / 255; /* YUV is float in the shader */
 +    float hue = (float)i965->hue_attrib->value / 180 * PI;
 +    float saturation = (float)i965->saturation_attrib->value / DEFAULT_SATURATION;
     dri_bo_map(render_state->curbe.bo, 1);
     assert(render_state->curbe.bo->virtual);
@@ -1065,14 +1078,28 @@ i965_render_upload_constants(VADriverContextP ctx,
     if (obj_surface->subsampling == SUBSAMPLE_YUV400) {
         assert(obj_surface->fourcc == VA_FOURCC('Y', '8', '0', '0'));
 -        *constant_buffer = 2;
 +        constant_buffer[0] = 2;
     } else {
         if (obj_surface->fourcc == VA_FOURCC('N', 'V', '1', '2'))
 -            *constant_buffer = 1;
 +            constant_buffer[0] = 1;
         else
 -            *constant_buffer = 0;
 +            constant_buffer[0] = 0;
     }
 +    if (i965->contrast_attrib->value == DEFAULT_CONTRAST &&
 +        i965->brightness_attrib->value == DEFAULT_BRIGHTNESS &&
 +        i965->hue_attrib->value == DEFAULT_HUE &&
 +        i965->saturation_attrib->value == DEFAULT_SATURATION)
 +        constant_buffer[1] = 1; /* skip color balance transformation */
 +    else
 +        constant_buffer[1] = 0;
 +
 +    color_balance_base = (float *)constant_buffer + 4;
 +    *color_balance_base++ = contrast;
 +    *color_balance_base++ = brightness;
 +    *color_balance_base++ = cos(hue) * contrast * saturation;
 +    *color_balance_base++ = sin(hue) * contrast * saturation;
 +
     dri_bo_unmap(render_state->curbe.bo);
 }
 diff --git a/src/shaders/render/Makefile.am b/src/shaders/render/Makefile.am
 index dac58c7..1653b4a 100644
 --- a/src/shaders/render/Makefile.am
 +++ b/src/shaders/render/Makefile.am
@@ -1,7 +1,8 @@
 INTEL_G4I =			\
 	exa_wm.g4i		\
 -	exa_wm_affine.g4i
 +	exa_wm_affine.g4i	\
 +	exa_wm_yuv_color_balance.gxa
 INTEL_G4A =				\
 	exa_sf.g4a			\
@@ -9,6 +10,7 @@ INTEL_G4A =				\
 	exa_wm_src_affine.g4a		\
 	exa_wm_src_sample_argb.g4a	\
 	exa_wm_src_sample_planar.g4a	\
 +	exa_wm_yuv_color_balance.g4a	\
 	exa_wm_yuv_rgb.g4a		\
 	exa_wm_write.g4a
@@ -20,6 +22,7 @@ INTEL_G4B =				\
 	exa_wm_src_affine.g4b		\
 	exa_wm_src_sample_argb.g4b	\
 	exa_wm_src_sample_planar.g4b	\
 +	exa_wm_yuv_color_balance.g4b	\
 	exa_wm_yuv_rgb.g4b		\
 	exa_wm_write.g4b
@@ -29,14 +32,18 @@ INTEL_G4B_GEN5 =				\
 	exa_wm_src_affine.g4b.gen5		\
 	exa_wm_src_sample_argb.g4b.gen5	\
 	exa_wm_src_sample_planar.g4b.gen5	\
 +	exa_wm_yuv_color_balance.g4b.gen5	\
 	exa_wm_yuv_rgb.g4b.gen5			\
 	exa_wm_write.g4b.gen5
 +INTEL_G6I = $(INTEL_G4I)
 +
 INTEL_G6A =				\
 	exa_wm_src_affine.g6a 		\
 	exa_wm_src_sample_argb.g6a 	\
 	exa_wm_src_sample_planar.g6a 	\
 	exa_wm_write.g6a 		\
 +	exa_wm_yuv_color_balance.g6a	\
 	exa_wm_yuv_rgb.g6a
 INTEL_G6S = $(INTEL_G6A:%.g6a=%.g6s)
@@ -46,13 +53,17 @@ INTEL_G6B =				\
 	exa_wm_src_sample_argb.g6b 	\
 	exa_wm_src_sample_planar.g6b 	\
 	exa_wm_write.g6b 		\
 +	exa_wm_yuv_color_balance.g6b	\
 	exa_wm_yuv_rgb.g6b
 +INTEL_G7I = $(INTEL_G4I)
 +
 INTEL_G7A =				\
 	exa_wm_src_affine.g7a 		\
 	exa_wm_src_sample_argb.g7a 	\
 	exa_wm_src_sample_planar.g7a 	\
 	exa_wm_write.g7a 		\
 +	exa_wm_yuv_color_balance.g7a	\
 	exa_wm_yuv_rgb.g7a
 INTEL_G7S = $(INTEL_G7A:%.g7a=%.g7s)
@@ -62,11 +73,13 @@ INTEL_G7B =				\
 	exa_wm_src_sample_argb.g7b 	\
 	exa_wm_src_sample_planar.g7b 	\
 	exa_wm_write.g7b 		\
 +	exa_wm_yuv_color_balance.g7b	\
 	exa_wm_yuv_rgb.g7b
 # XXX: only regenerate binary for EU code containing JMPI instructions
 INTEL_G7B_HASWELL = \
 	exa_wm_src_sample_planar.g7b.haswell	\
 +	exa_wm_yuv_color_balance.g7b.haswell	\
 	$(NULL)
 TARGETS  =
@@ -80,7 +93,7 @@ endif
 all-local: $(TARGETS)
 -SUFFIXES = .g4a .g4s .g4b .g6a .g6s .g6b .g7a .g7s .g7b .g7b.haswell
 +SUFFIXES = .g4a .g4s .g4b .g4b.gen5 .g6a .g6s .g6b .g7a .g7s .g7b .g7b.haswell
 if HAVE_GEN4ASM
 $(INTEL_G4S): $(INTEL_G4A) $(INTEL_G4I)
 diff --git a/src/shaders/render/exa_wm.g4i b/src/shaders/render/exa_wm.g4i
 index 8163de5..dd47d51 100644
 --- a/src/shaders/render/exa_wm.g4i
 +++ b/src/shaders/render/exa_wm.g4i
@@ -142,6 +142,25 @@ define(`mask_sample_a',		`g28')
 define(`mask_sample_a_01',	`g28')
 define(`mask_sample_a_23',	`g29')
 +/* Color Balance to these registers */
 +define(`color_balance_base',    `g32')
 +
 +define(`color_balance_r',       `g32')
 +define(`color_balance_r_01',    `g32')
 +define(`color_balance_r_23',    `g33')
 +
 +define(`color_balance_g',       `g34')
 +define(`color_balance_g_01',    `g34')
 +define(`color_balance_g_23',    `g35')
 +
 +define(`color_balance_b',       `g36')
 +define(`color_balance_b_01',    `g37')
 +define(`color_balance_b_23',    `g37')
 +
 +define(`color_balance_a',       `g38')
 +define(`color_balance_a_01',    `g39')
 +define(`color_balance_a_23',    `g39')
 +
 /* data port SIMD16 send registers */
 define(`data_port_msg_0',	`m0')
 diff --git a/src/shaders/render/exa_wm_yuv_color_balance.g4a b/src/shaders/render/exa_wm_yuv_color_balance.g4a
 new file mode 100644
 index 0000000..33ba67a
 --- /dev/null
 +++ b/src/shaders/render/exa_wm_yuv_color_balance.g4a
@@ -0,0 +1,38 @@
 +/*
 + * Copyright © 2013 Intel Corporation
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a
 + * copy of this software and associated documentation files (the "Software"),
 + * to deal in the Software without restriction, including without limitation
 + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 + * and/or sell copies of the Software, and to permit persons to whom the
 + * Software is furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice (including the next
 + * paragraph) shall be included in all copies or substantial portions of the
 + * Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 + * IN THE SOFTWARE.
 + *
 + * Authors:
 + *    Haihao Xiang <haihao.xiang@intel.com>
 + *
 + */
 +
 +include(`exa_wm.g4i')
 +
 +/* Color Balance parameters */
 +define(`skip_color_balance',    `g2.2<0,1,0>uw')
 +define(`contrast',              `g2.16<0,1,0>f')
 +define(`brightness',            `g2.20<0,1,0>f')
 +define(`cos_c_s',               `g2.24<0,1,0>f')
 +define(`sin_c_s',               `g2.28<0,1,0>f')
 +define(`sin_c_s_t',             `g2.28')
 +
 +include(`exa_wm_yuv_color_balance.gxa')
 diff --git a/src/shaders/render/exa_wm_yuv_color_balance.g4b b/src/shaders/render/exa_wm_yuv_color_balance.g4b
 new file mode 100644
 index 0000000..cba9aca
 --- /dev/null
 +++ b/src/shaders/render/exa_wm_yuv_color_balance.g4b
@@ -0,0 +1,15 @@
 +   { 0x01000010, 0x20002d3c, 0x00000042, 0x00010001 },
 +   { 0x00010020, 0x34001c00, 0x00001400, 0x0000000d },
 +   { 0x00802040, 0x24007fbd, 0x008d01c0, 0xbd808081 },
 +   { 0x00802041, 0x240077bd, 0x008d0400, 0x00000050 },
 +   { 0x00802040, 0x240077bd, 0x008d0400, 0x00000054 },
 +   { 0x00802040, 0x21c07fbd, 0x008d0400, 0x3d808081 },
 +   { 0x00802040, 0x24807fbd, 0x008d0200, 0xbf008084 },
 +   { 0x00802040, 0x24407fbd, 0x008d0240, 0xbf008084 },
 +   { 0x00802001, 0x240003fc, 0x00000000, 0x3f008084 },
 +   { 0x00802048, 0x240077bc, 0x008d0440, 0x0000005c },
 +   { 0x00802048, 0x220077bd, 0x008d0480, 0x00000058 },
 +   { 0x00000041, 0x205c7fbd, 0x0000005c, 0xbf800000 },
 +   { 0x00802001, 0x240003fc, 0x00000000, 0x3f008084 },
 +   { 0x00802048, 0x240077bc, 0x008d0480, 0x0000005c },
 +   { 0x00802048, 0x224077bd, 0x008d0440, 0x00000058 },
 diff --git a/src/shaders/render/exa_wm_yuv_color_balance.g4b.gen5 b/src/shaders/render/exa_wm_yuv_color_balance.g4b.gen5
 new file mode 100644
 index 0000000..5a24a0e
 --- /dev/null
 +++ b/src/shaders/render/exa_wm_yuv_color_balance.g4b.gen5
@@ -0,0 +1,15 @@
 +   { 0x01000010, 0x20002d3c, 0x00000042, 0x00010001 },
 +   { 0x00010020, 0x34001c00, 0x00001400, 0x0000001a },
 +   { 0x00802040, 0x24007fbd, 0x008d01c0, 0xbd808081 },
 +   { 0x00802041, 0x240077bd, 0x008d0400, 0x00000050 },
 +   { 0x00802040, 0x240077bd, 0x008d0400, 0x00000054 },
 +   { 0x00802040, 0x21c07fbd, 0x008d0400, 0x3d808081 },
 +   { 0x00802040, 0x24807fbd, 0x008d0200, 0xbf008084 },
 +   { 0x00802040, 0x24407fbd, 0x008d0240, 0xbf008084 },
 +   { 0x00802001, 0x240003fc, 0x00000000, 0x3f008084 },
 +   { 0x00802048, 0x240077bc, 0x008d0440, 0x0000005c },
 +   { 0x00802048, 0x220077bd, 0x008d0480, 0x00000058 },
 +   { 0x00000041, 0x205c7fbd, 0x0000005c, 0xbf800000 },
 +   { 0x00802001, 0x240003fc, 0x00000000, 0x3f008084 },
 +   { 0x00802048, 0x240077bc, 0x008d0480, 0x0000005c },
 +   { 0x00802048, 0x224077bd, 0x008d0440, 0x00000058 },
 diff --git a/src/shaders/render/exa_wm_yuv_color_balance.g6a b/src/shaders/render/exa_wm_yuv_color_balance.g6a
 new file mode 100644
 index 0000000..6906357
 --- /dev/null
 +++ b/src/shaders/render/exa_wm_yuv_color_balance.g6a
@@ -0,0 +1,38 @@
 +/*
 + * Copyright © 2013 Intel Corporation
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a
 + * copy of this software and associated documentation files (the "Software"),
 + * to deal in the Software without restriction, including without limitation
 + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 + * and/or sell copies of the Software, and to permit persons to whom the
 + * Software is furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice (including the next
 + * paragraph) shall be included in all copies or substantial portions of the
 + * Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 + * IN THE SOFTWARE.
 + *
 + * Authors:
 + *    Haihao Xiang <haihao.xiang@intel.com>
 + *
 + */
 +
 +include(`exa_wm.g4i')
 +
 +/* Color Balance parameters */
 +define(`skip_color_balance',    `g6.2<0,1,0>uw')
 +define(`contrast',              `g6.16<0,1,0>f')
 +define(`brightness',            `g6.20<0,1,0>f')
 +define(`cos_c_s',               `g6.24<0,1,0>f')
 +define(`sin_c_s',               `g6.28<0,1,0>f')
 +define(`sin_c_s_t',             `g6.28')
 +
 +include(`exa_wm_yuv_color_balance.gxa')
 diff --git a/src/shaders/render/exa_wm_yuv_color_balance.g6b b/src/shaders/render/exa_wm_yuv_color_balance.g6b
 new file mode 100644
 index 0000000..0a9e6b9
 --- /dev/null
 +++ b/src/shaders/render/exa_wm_yuv_color_balance.g6b
@@ -0,0 +1,15 @@
 +   { 0x01000010, 0x20002d3c, 0x000000c2, 0x00010001 },
 +   { 0x00010020, 0x34001c00, 0x00001400, 0x0000001a },
 +   { 0x00800040, 0x24007fbd, 0x008d01c0, 0xbd808081 },
 +   { 0x00800041, 0x240077bd, 0x008d0400, 0x000000d0 },
 +   { 0x00800040, 0x240077bd, 0x008d0400, 0x000000d4 },
 +   { 0x00800040, 0x21c07fbd, 0x008d0400, 0x3d808081 },
 +   { 0x00800040, 0x24807fbd, 0x008d0200, 0xbf008084 },
 +   { 0x00800040, 0x24407fbd, 0x008d0240, 0xbf008084 },
 +   { 0x00800001, 0x240003fc, 0x00000000, 0x3f008084 },
 +   { 0x00800048, 0x240077bc, 0x008d0440, 0x000000dc },
 +   { 0x00800048, 0x220077bd, 0x008d0480, 0x000000d8 },
 +   { 0x00000041, 0x20dc7fbd, 0x000000dc, 0xbf800000 },
 +   { 0x00800001, 0x240003fc, 0x00000000, 0x3f008084 },
 +   { 0x00800048, 0x240077bc, 0x008d0480, 0x000000dc },
 +   { 0x00800048, 0x224077bd, 0x008d0440, 0x000000d8 },
 diff --git a/src/shaders/render/exa_wm_yuv_color_balance.g7a b/src/shaders/render/exa_wm_yuv_color_balance.g7a
 new file mode 100644
 index 0000000..6906357
 --- /dev/null
 +++ b/src/shaders/render/exa_wm_yuv_color_balance.g7a
@@ -0,0 +1,38 @@
 +/*
 + * Copyright © 2013 Intel Corporation
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a
 + * copy of this software and associated documentation files (the "Software"),
 + * to deal in the Software without restriction, including without limitation
 + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 + * and/or sell copies of the Software, and to permit persons to whom the
 + * Software is furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice (including the next
 + * paragraph) shall be included in all copies or substantial portions of the
 + * Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 + * IN THE SOFTWARE.
 + *
 + * Authors:
 + *    Haihao Xiang <haihao.xiang@intel.com>
 + *
 + */
 +
 +include(`exa_wm.g4i')
 +
 +/* Color Balance parameters */
 +define(`skip_color_balance',    `g6.2<0,1,0>uw')
 +define(`contrast',              `g6.16<0,1,0>f')
 +define(`brightness',            `g6.20<0,1,0>f')
 +define(`cos_c_s',               `g6.24<0,1,0>f')
 +define(`sin_c_s',               `g6.28<0,1,0>f')
 +define(`sin_c_s_t',             `g6.28')
 +
 +include(`exa_wm_yuv_color_balance.gxa')
 diff --git a/src/shaders/render/exa_wm_yuv_color_balance.g7b b/src/shaders/render/exa_wm_yuv_color_balance.g7b
 new file mode 100644
 index 0000000..0a9e6b9
 --- /dev/null
 +++ b/src/shaders/render/exa_wm_yuv_color_balance.g7b
@@ -0,0 +1,15 @@
 +   { 0x01000010, 0x20002d3c, 0x000000c2, 0x00010001 },
 +   { 0x00010020, 0x34001c00, 0x00001400, 0x0000001a },
 +   { 0x00800040, 0x24007fbd, 0x008d01c0, 0xbd808081 },
 +   { 0x00800041, 0x240077bd, 0x008d0400, 0x000000d0 },
 +   { 0x00800040, 0x240077bd, 0x008d0400, 0x000000d4 },
 +   { 0x00800040, 0x21c07fbd, 0x008d0400, 0x3d808081 },
 +   { 0x00800040, 0x24807fbd, 0x008d0200, 0xbf008084 },
 +   { 0x00800040, 0x24407fbd, 0x008d0240, 0xbf008084 },
 +   { 0x00800001, 0x240003fc, 0x00000000, 0x3f008084 },
 +   { 0x00800048, 0x240077bc, 0x008d0440, 0x000000dc },
 +   { 0x00800048, 0x220077bd, 0x008d0480, 0x000000d8 },
 +   { 0x00000041, 0x20dc7fbd, 0x000000dc, 0xbf800000 },
 +   { 0x00800001, 0x240003fc, 0x00000000, 0x3f008084 },
 +   { 0x00800048, 0x240077bc, 0x008d0480, 0x000000dc },
 +   { 0x00800048, 0x224077bd, 0x008d0440, 0x000000d8 },
 diff --git a/src/shaders/render/exa_wm_yuv_color_balance.g7b.haswell b/src/shaders/render/exa_wm_yuv_color_balance.g7b.haswell
 new file mode 100644
 index 0000000..2780c08
 --- /dev/null
 +++ b/src/shaders/render/exa_wm_yuv_color_balance.g7b.haswell
@@ -0,0 +1,15 @@
 +   { 0x01000010, 0x20002d3c, 0x000000c2, 0x00010001 },
 +   { 0x00010020, 0x34001c00, 0x00001400, 0x000000d0 },
 +   { 0x00800040, 0x24007fbd, 0x008d01c0, 0xbd808081 },
 +   { 0x00800041, 0x240077bd, 0x008d0400, 0x000000d0 },
 +   { 0x00800040, 0x240077bd, 0x008d0400, 0x000000d4 },
 +   { 0x00800040, 0x21c07fbd, 0x008d0400, 0x3d808081 },
 +   { 0x00800040, 0x24807fbd, 0x008d0200, 0xbf008084 },
 +   { 0x00800040, 0x24407fbd, 0x008d0240, 0xbf008084 },
 +   { 0x00800001, 0x240003fc, 0x00000000, 0x3f008084 },
 +   { 0x00800048, 0x240077bc, 0x008d0440, 0x000000dc },
 +   { 0x00800048, 0x220077bd, 0x008d0480, 0x000000d8 },
 +   { 0x00000041, 0x20dc7fbd, 0x000000dc, 0xbf800000 },
 +   { 0x00800001, 0x240003fc, 0x00000000, 0x3f008084 },
 +   { 0x00800048, 0x240077bc, 0x008d0480, 0x000000dc },
 +   { 0x00800048, 0x224077bd, 0x008d0440, 0x000000d8 },
 diff --git a/src/shaders/render/exa_wm_yuv_color_balance.gxa b/src/shaders/render/exa_wm_yuv_color_balance.gxa
 new file mode 100644
 index 0000000..948067c
 --- /dev/null
 +++ b/src/shaders/render/exa_wm_yuv_color_balance.gxa
@@ -0,0 +1,75 @@
 +/*
 + * Copyright © 2013 Intel Corporation
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a
 + * copy of this software and associated documentation files (the "Software"),
 + * to deal in the Software without restriction, including without limitation
 + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 + * and/or sell copies of the Software, and to permit persons to whom the
 + * Software is furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice (including the next
 + * paragraph) shall be included in all copies or substantial portions of the
 + * Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 + * IN THE SOFTWARE.
 + *
 + * Authors:
 + *    Haihao Xiang <haihao.xiang@intel.com>
 + *
 + */
 +
 +define(`Cr',                    `src_sample_b')
 +define(`Cr_01',                 `src_sample_b_01')
 +define(`Cr_23',                 `src_sample_b_23')
 +
 +define(`Y',                     `src_sample_r')
 +define(`Y_01',                  `src_sample_r_01')
 +define(`Y_23',                  `src_sample_r_23')
 +
 +define(`Cb',                    `src_sample_g')
 +define(`Cb_01',                 `src_sample_g_01')
 +define(`Cb_23',                 `src_sample_g_23')
 +
 +define(`Crn',                   `color_balance_g')
 +define(`Crn_01',                `color_balance_g_01')
 +define(`Crn_23',                `color_balance_g_23')
 +
 +define(`Yn',                    `color_balance_r')
 +define(`Yn_01',                 `color_balance_r_01')
 +define(`Yn_23',                 `color_balance_r_23')
 +
 +define(`Cbn',                   `color_balance_b')
 +define(`Cbn_01',                `color_balance_b_01')
 +define(`Cbn_23',                `color_balance_b_23')
 +
 +cmp.e.f0.0 (1) null skip_color_balance 0x1uw {align1};
 +(f0.0) jmpi _DONE_COLOR_BALANCE;
 +
 +/* Yout = (Yin - 16 / 255) * contrast + brightness + 16 / 255 */
 +add (16)    Yn<1>F      Y<8,8,1>F       -0.0627451F     { compr align1 };
 +mul (16)    Yn<1>F      Yn<8,8,1>F      contrast        { compr align1 };
 +add (16)    Yn<1>F      Yn<8,8,1>F      brightness      { compr align1 };
 +add (16)    Y<1>F       Yn<8,8,1>F      0.0627451F      { compr align1 };
 +
 +/* Uout = (Uin - 128 / 255) * cos_c_s + (Vin - 128 / 255) * sin_c_s + 128 / 255 */
 +/* Vout = (Vin - 128 / 255) * cos_c_s - (Uin - 128 / 255) * sin_c_s + 128 / 255 */
 +add (16)    Cbn<1>F     Cb<8,8,1>F      -0.501961F      { compr align1 };
 +add (16)    Crn<1>F     Cr<8,8,1>F      -0.501961F      { compr align1 };
 +
 +mov (16)    acc0<1>F    0.501961F                       { compr align1 };
 +mac (16)    acc0<1>F    Crn<8,8,1>F     sin_c_s         { compr align1 };
 +mac (16)    Cb<1>F      Cbn<8,8,1>F     cos_c_s         { compr align1 };
 +
 +mul (1)     sin_c_s_t<1>F       sin_c_s         -1.0F   { align1};
 +mov (16)    acc0<1>F            0.501961F               { compr align1 };
 +mac (16)    acc0<1>F            Cbn<8,8,1>F     sin_c_s { compr align1 };
 +mac (16)    Cr<1>F              Crn<8,8,1>F     cos_c_s { compr align1 };
 +
 +_DONE_COLOR_BALANCE:
 -- 
 1.8.3.2
--- a/packages/multimedia/libva-driver-intel/patches.upstream/0002-Increase-the-size-of-constant-buffer-for-PS-thread-t.patch
+++ b/packages/multimedia/libva-driver-intel/patches.upstream/0002-Increase-the-size-of-constant-buffer-for-PS-thread-t.patch
@ -0,0 +1,276 @@
 From bf2bb5e0ccc8375800a9ed1bad956fd766641f1a Mon Sep 17 00:00:00 2001
 From: Zhao Yakui <yakui.zhao@intel.com>
 Date: Fri, 22 Nov 2013 13:39:34 +0800
 Subject: [PATCH 2/5] Increase the size of constant buffer for PS thread to
 pass more info
 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
 ---
 src/i965_render.c                             | 16 ++++-----
 src/shaders/render/exa_wm.g4i                 | 52 ++++++++++++++-------------
 src/shaders/render/exa_wm_src_affine.g4b      | 12 +++----
 src/shaders/render/exa_wm_src_affine.g4b.gen5 | 12 +++----
 src/shaders/render/exa_wm_src_affine.g6a      |  3 --
 src/shaders/render/exa_wm_src_affine.g6b      |  8 ++---
 src/shaders/render/exa_wm_src_affine.g7a      |  2 --
 src/shaders/render/exa_wm_src_affine.g7b      |  8 ++---
 src/shaders/render/exa_wm_xy.g4b              |  4 +--
 src/shaders/render/exa_wm_xy.g4b.gen5         |  4 +--
 10 files changed, 60 insertions(+), 61 deletions(-)
 diff --git a/src/i965_render.c b/src/i965_render.c
 index b4fd29b..0777ce0 100644
 --- a/src/i965_render.c
 +++ b/src/i965_render.c
@@ -55,7 +55,7 @@ static const uint32_t sf_kernel_static[][4] =
 #include "shaders/render/exa_sf.g4b"
 };
 -#define PS_KERNEL_NUM_GRF       32
 +#define PS_KERNEL_NUM_GRF       48
 #define PS_MAX_THREADS          32
 #define I965_GRF_BLOCKS(nreg)	((nreg + 15) / 16 - 1)
@@ -308,8 +308,8 @@ static struct i965_kernel render_kernels_gen7_haswell[] = {
 #define URB_SF_ENTRIES	      1
 #define URB_SF_ENTRY_SIZE     2
 -#define URB_CS_ENTRIES	      1
 -#define URB_CS_ENTRY_SIZE     1
 +#define URB_CS_ENTRIES	      4
 +#define URB_CS_ENTRY_SIZE     4
 static void
 i965_render_vs_unit(VADriverContextP ctx)
@@ -445,8 +445,8 @@ i965_subpic_render_wm_unit(VADriverContextP ctx)
     wm_state->thread2.scratch_space_base_pointer = 0;
     wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
 -    wm_state->thread3.dispatch_grf_start_reg = 3; /* XXX */
 -    wm_state->thread3.const_urb_entry_read_length = 0;
 +    wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
 +    wm_state->thread3.const_urb_entry_read_length = 4;
     wm_state->thread3.const_urb_entry_read_offset = 0;
     wm_state->thread3.urb_entry_read_length = 1; /* XXX */
     wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
@@ -510,7 +510,7 @@ i965_render_wm_unit(VADriverContextP ctx)
     wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
     wm_state->thread3.dispatch_grf_start_reg = 2; /* XXX */
 -    wm_state->thread3.const_urb_entry_read_length = 1;
 +    wm_state->thread3.const_urb_entry_read_length = 4;
     wm_state->thread3.const_urb_entry_read_offset = 0;
     wm_state->thread3.urb_entry_read_length = 1; /* XXX */
     wm_state->thread3.urb_entry_read_offset = 0; /* XXX */
@@ -2071,7 +2071,7 @@ gen6_emit_wm_state(VADriverContextP ctx, int kernel)
     OUT_RELOC(batch, 
               render_state->curbe.bo,
               I915_GEM_DOMAIN_INSTRUCTION, 0,
 -              0);
 +              (URB_CS_ENTRY_SIZE-1));
     OUT_BATCH(batch, 0);
     OUT_BATCH(batch, 0);
     OUT_BATCH(batch, 0);
@@ -2837,7 +2837,7 @@ gen7_emit_wm_state(VADriverContextP ctx, int kernel)
     BEGIN_BATCH(batch, 7);
     OUT_BATCH(batch, GEN6_3DSTATE_CONSTANT_PS | (7 - 2));
 -    OUT_BATCH(batch, 1);
 +    OUT_BATCH(batch, URB_CS_ENTRY_SIZE);
     OUT_BATCH(batch, 0);
     OUT_RELOC(batch, 
               render_state->curbe.bo,
 diff --git a/src/shaders/render/exa_wm.g4i b/src/shaders/render/exa_wm.g4i
 index dd47d51..e186d3a 100644
 --- a/src/shaders/render/exa_wm.g4i
 +++ b/src/shaders/render/exa_wm.g4i
@@ -1,5 +1,5 @@
 /*
 - * Copyright © 2006 Intel Corporation
 + * Copyright © 2006-2013 Intel Corporation
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -39,39 +39,43 @@ define(`screen_y0', `g1.4<0,1,0>F')
 define(`interleaved_uv', `g2.0<0,1,0>UW')
 /* Source transformation parameters */
 -define(`src_du_dx', `g3.0<0,1,0>F')
 -define(`src_du_dy', `g3.4<0,1,0>F')
 -define(`src_uo',    `g3.12<0,1,0>F')
 -define(`src_dv_dx', `g3.16<0,1,0>F')
 -define(`src_dv_dy', `g3.20<0,1,0>F')
 -define(`src_vo',    `g3.28<0,1,0>F')
 -define(`src_dw_dx', `g4.0<0,1,0>F')
 -define(`src_dw_dy', `g4.4<0,1,0>F')
 -define(`src_wo',    `g4.12<0,1,0>F')
 -
 -define(`mask_du_dx', `g5.0<0,1,0>F')
 -define(`mask_du_dy', `g5.4<0,1,0>F')
 -define(`mask_uo',    `g5.12<0,1,0>F')
 -define(`mask_dv_dx', `g5.16<0,1,0>F')
 -define(`mask_dv_dy', `g5.20<0,1,0>F')
 -define(`mask_vo',    `g5.28<0,1,0>F')
 -define(`mask_dw_dx', `g6.0<0,1,0>F')
 -define(`mask_dw_dy', `g6.4<0,1,0>F')
 -define(`mask_wo',    `g6.12<0,1,0>F')
 +define(`src_du_dx', `g6.0<0,1,0>F')
 +define(`src_du_dy', `g6.4<0,1,0>F')
 +define(`src_uo',    `g6.12<0,1,0>F')
 +define(`src_dv_dx', `g6.16<0,1,0>F')
 +define(`src_dv_dy', `g6.20<0,1,0>F')
 +define(`src_vo',    `g6.28<0,1,0>F')
 +define(`src_dw_dx', `g7.0<0,1,0>F')
 +define(`src_dw_dy', `g7.4<0,1,0>F')
 +define(`src_wo',    `g7.12<0,1,0>F')
 +
 +define(`mask_du_dx', `g8.0<0,1,0>F')
 +define(`mask_du_dy', `g8.4<0,1,0>F')
 +define(`mask_uo',    `g8.12<0,1,0>F')
 +define(`mask_dv_dx', `g8.16<0,1,0>F')
 +define(`mask_dv_dy', `g8.20<0,1,0>F')
 +define(`mask_vo',    `g8.28<0,1,0>F')
 +define(`mask_dw_dx', `g9.0<0,1,0>F')
 +define(`mask_dw_dy', `g9.4<0,1,0>F')
 +define(`mask_wo',    `g9.12<0,1,0>F')
 +
 +/* Attribute for snb+ */
 +define(`a0_a_x',`g10.0<0,1,0>F')
 +define(`a0_a_y',`g10.16<0,1,0>F')
 /*
  * Local variables. Pairs must be aligned on even reg boundry
  */
 /* this holds the X dest coordinates */
 -define(`dst_x',	    `g8')
 +define(`dst_x',	    `g42')
 define(`dst_x_0',   `dst_x')
 -define(`dst_x_1',   `g9')
 +define(`dst_x_1',   `g43')
 /* this holds the Y dest coordinates */
 -define(`dst_y',	    `g10')
 +define(`dst_y',	    `g44')
 define(`dst_y_0',   `dst_y')
 -define(`dst_y_1',   `g11')
 +define(`dst_y_1',   `g45')
 /* When computing x * dn/dx, use this */
 define(`temp_x',    `g30')
 diff --git a/src/shaders/render/exa_wm_src_affine.g4b b/src/shaders/render/exa_wm_src_affine.g4b
 index d30da87..7507b72 100644
 --- a/src/shaders/render/exa_wm_src_affine.g4b
 +++ b/src/shaders/render/exa_wm_src_affine.g4b
@@ -1,8 +1,8 @@
 -   { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000060 },
 -   { 0x00802041, 0x238077bd, 0x008d0140, 0x00000064 },
 +   { 0x00802041, 0x23c077bd, 0x008d0540, 0x000000c0 },
 +   { 0x00802041, 0x238077bd, 0x008d0580, 0x000000c4 },
    { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
 -   { 0x00802040, 0x204077be, 0x008d03c0, 0x0000006c },
 -   { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000070 },
 -   { 0x00802041, 0x238077bd, 0x008d0140, 0x00000074 },
 +   { 0x00802040, 0x204077be, 0x008d03c0, 0x000000cc },
 +   { 0x00802041, 0x23c077bd, 0x008d0540, 0x000000d0 },
 +   { 0x00802041, 0x238077bd, 0x008d0580, 0x000000d4 },
    { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
 -   { 0x00802040, 0x208077be, 0x008d03c0, 0x0000007c },
 +   { 0x00802040, 0x208077be, 0x008d03c0, 0x000000dc },
 diff --git a/src/shaders/render/exa_wm_src_affine.g4b.gen5 b/src/shaders/render/exa_wm_src_affine.g4b.gen5
 index d30da87..7507b72 100644
 --- a/src/shaders/render/exa_wm_src_affine.g4b.gen5
 +++ b/src/shaders/render/exa_wm_src_affine.g4b.gen5
@@ -1,8 +1,8 @@
 -   { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000060 },
 -   { 0x00802041, 0x238077bd, 0x008d0140, 0x00000064 },
 +   { 0x00802041, 0x23c077bd, 0x008d0540, 0x000000c0 },
 +   { 0x00802041, 0x238077bd, 0x008d0580, 0x000000c4 },
    { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
 -   { 0x00802040, 0x204077be, 0x008d03c0, 0x0000006c },
 -   { 0x00802041, 0x23c077bd, 0x008d0100, 0x00000070 },
 -   { 0x00802041, 0x238077bd, 0x008d0140, 0x00000074 },
 +   { 0x00802040, 0x204077be, 0x008d03c0, 0x000000cc },
 +   { 0x00802041, 0x23c077bd, 0x008d0540, 0x000000d0 },
 +   { 0x00802041, 0x238077bd, 0x008d0580, 0x000000d4 },
    { 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 },
 -   { 0x00802040, 0x208077be, 0x008d03c0, 0x0000007c },
 +   { 0x00802040, 0x208077be, 0x008d03c0, 0x000000dc },
 diff --git a/src/shaders/render/exa_wm_src_affine.g6a b/src/shaders/render/exa_wm_src_affine.g6a
 index 568aef3..04358cb 100644
 --- a/src/shaders/render/exa_wm_src_affine.g6a
 +++ b/src/shaders/render/exa_wm_src_affine.g6a
@@ -35,9 +35,6 @@ define(`vh',    `m5')
 define(`bl',    `g2.0<8,8,1>F')
 define(`bh',    `g4.0<8,8,1>F')
 -define(`a0_a_x',`g7.0<0,1,0>F')
 -define(`a0_a_y',`g7.16<0,1,0>F')
 -
 /* U */
 pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */
 pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */
 diff --git a/src/shaders/render/exa_wm_src_affine.g6b b/src/shaders/render/exa_wm_src_affine.g6b
 index 5d0ffcc..22c1d22 100644
 --- a/src/shaders/render/exa_wm_src_affine.g6b
 +++ b/src/shaders/render/exa_wm_src_affine.g6b
@@ -1,4 +1,4 @@
 -   { 0x0060005a, 0x204077be, 0x000000e0, 0x008d0040 },
 -   { 0x0060005a, 0x206077be, 0x000000e0, 0x008d0080 },
 -   { 0x0060005a, 0x208077be, 0x000000f0, 0x008d0040 },
 -   { 0x0060005a, 0x20a077be, 0x000000f0, 0x008d0080 },
 +   { 0x0060005a, 0x204077be, 0x00000140, 0x008d0040 },
 +   { 0x0060005a, 0x206077be, 0x00000140, 0x008d0080 },
 +   { 0x0060005a, 0x208077be, 0x00000150, 0x008d0040 },
 +   { 0x0060005a, 0x20a077be, 0x00000150, 0x008d0080 },
 diff --git a/src/shaders/render/exa_wm_src_affine.g7a b/src/shaders/render/exa_wm_src_affine.g7a
 index a786bc0..88e5ed5 100644
 --- a/src/shaders/render/exa_wm_src_affine.g7a
 +++ b/src/shaders/render/exa_wm_src_affine.g7a
@@ -35,8 +35,6 @@ define(`vh',    `g69')
 define(`bl',    `g2.0<8,8,1>F')
 define(`bh',    `g4.0<8,8,1>F')
 -define(`a0_a_x',`g7.0<0,1,0>F')
 -define(`a0_a_y',`g7.16<0,1,0>F')
 /* U */
 pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */
 diff --git a/src/shaders/render/exa_wm_src_affine.g7b b/src/shaders/render/exa_wm_src_affine.g7b
 index 5dbbf1b..a15b7b6 100644
 --- a/src/shaders/render/exa_wm_src_affine.g7b
 +++ b/src/shaders/render/exa_wm_src_affine.g7b
@@ -1,4 +1,4 @@
 -   { 0x0060005a, 0x284077bd, 0x000000e0, 0x008d0040 },
 -   { 0x0060005a, 0x286077bd, 0x000000e0, 0x008d0080 },
 -   { 0x0060005a, 0x288077bd, 0x000000f0, 0x008d0040 },
 -   { 0x0060005a, 0x28a077bd, 0x000000f0, 0x008d0080 },
 +   { 0x0060005a, 0x284077bd, 0x00000140, 0x008d0040 },
 +   { 0x0060005a, 0x286077bd, 0x00000140, 0x008d0080 },
 +   { 0x0060005a, 0x288077bd, 0x00000150, 0x008d0040 },
 +   { 0x0060005a, 0x28a077bd, 0x00000150, 0x008d0080 },
 diff --git a/src/shaders/render/exa_wm_xy.g4b b/src/shaders/render/exa_wm_xy.g4b
 index 327fc29..2b3b235 100644
 --- a/src/shaders/render/exa_wm_xy.g4b
 +++ b/src/shaders/render/exa_wm_xy.g4b
@@ -1,4 +1,4 @@
    { 0x00800040, 0x23c06d29, 0x00480028, 0x10101010 },
    { 0x00800040, 0x23806d29, 0x0048002a, 0x11001100 },
 -   { 0x00802040, 0x2100753d, 0x008d03c0, 0x00004020 },
 -   { 0x00802040, 0x2140753d, 0x008d0380, 0x00004024 },
 +   { 0x00802040, 0x2540753d, 0x008d03c0, 0x00004020 },
 +   { 0x00802040, 0x2580753d, 0x008d0380, 0x00004024 },
 diff --git a/src/shaders/render/exa_wm_xy.g4b.gen5 b/src/shaders/render/exa_wm_xy.g4b.gen5
 index 327fc29..2b3b235 100644
 --- a/src/shaders/render/exa_wm_xy.g4b.gen5
 +++ b/src/shaders/render/exa_wm_xy.g4b.gen5
@@ -1,4 +1,4 @@
    { 0x00800040, 0x23c06d29, 0x00480028, 0x10101010 },
    { 0x00800040, 0x23806d29, 0x0048002a, 0x11001100 },
 -   { 0x00802040, 0x2100753d, 0x008d03c0, 0x00004020 },
 -   { 0x00802040, 0x2140753d, 0x008d0380, 0x00004024 },
 +   { 0x00802040, 0x2540753d, 0x008d03c0, 0x00004020 },
 +   { 0x00802040, 0x2580753d, 0x008d0380, 0x00004024 },
 -- 
 1.8.3.2
--- a/packages/multimedia/libva-driver-intel/patches.upstream/0003-Constant-buffer-passes-YUV2RGB-CSC-matrix-instead-of.patch
+++ b/packages/multimedia/libva-driver-intel/patches.upstream/0003-Constant-buffer-passes-YUV2RGB-CSC-matrix-instead-of.patch
@ -0,0 +1,629 @@
 From 7be8aa161fd9d885c1d4cb27ad21af21f617256b Mon Sep 17 00:00:00 2001
 From: Zhao Yakui <yakui.zhao@intel.com>
 Date: Fri, 22 Nov 2013 13:39:34 +0800
 Subject: [PATCH 3/5] Constant buffer passes YUV2RGB CSC matrix instead of
 hardcoded matrix
 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
 ---
 src/i965_render.c                          | 10 ++++
 src/shaders/render/Makefile.am             |  5 +-
 src/shaders/render/exa_wm_yuv_rgb.g4a      | 72 ++---------------------------
 src/shaders/render/exa_wm_yuv_rgb.g4b      | 23 +++++-----
 src/shaders/render/exa_wm_yuv_rgb.g4b.gen5 | 23 +++++-----
 src/shaders/render/exa_wm_yuv_rgb.g6a      | 73 ++---------------------------
 src/shaders/render/exa_wm_yuv_rgb.g6b      | 23 +++++-----
 src/shaders/render/exa_wm_yuv_rgb.g7a      | 73 ++---------------------------
 src/shaders/render/exa_wm_yuv_rgb.g7b      | 23 +++++-----
 src/shaders/render/exa_yuv_gen4.g4i        | 42 +++++++++++++++++
 src/shaders/render/exa_yuv_gen6.g4i        | 42 +++++++++++++++++
 src/shaders/render/exa_yuv_rgb.gxa         | 74 ++++++++++++++++++++++++++++++
 12 files changed, 229 insertions(+), 254 deletions(-)
 create mode 100644 src/shaders/render/exa_yuv_gen4.g4i
 create mode 100644 src/shaders/render/exa_yuv_gen6.g4i
 create mode 100644 src/shaders/render/exa_yuv_rgb.gxa
 diff --git a/src/i965_render.c b/src/i965_render.c
 index 0777ce0..5b1a1a5 100644
 --- a/src/i965_render.c
 +++ b/src/i965_render.c
@@ -311,6 +311,12 @@ static struct i965_kernel render_kernels_gen7_haswell[] = {
 #define URB_CS_ENTRIES	      4
 #define URB_CS_ENTRY_SIZE     4
 +static float yuv_to_rgb_bt601[3][4] = {
 +{1.164,		0,	1.596,		-0.06275,},
 +{1.164,		-0.392,	-0.813,		-0.50196,},
 +{1.164,		2.017,	0,		-0.50196,},
 +};
 +
 static void
 i965_render_vs_unit(VADriverContextP ctx)
 {
@@ -1070,6 +1076,7 @@ i965_render_upload_constants(VADriverContextP ctx,
     float brightness = (float)i965->brightness_attrib->value / 255; /* YUV is float in the shader */
     float hue = (float)i965->hue_attrib->value / 180 * PI;
     float saturation = (float)i965->saturation_attrib->value / DEFAULT_SATURATION;
 +    float *yuv_to_rgb;
     dri_bo_map(render_state->curbe.bo, 1);
     assert(render_state->curbe.bo->virtual);
@@ -1100,6 +1107,9 @@ i965_render_upload_constants(VADriverContextP ctx,
     *color_balance_base++ = cos(hue) * contrast * saturation;
     *color_balance_base++ = sin(hue) * contrast * saturation;
 +    yuv_to_rgb = (float *)constant_buffer + 8;
 +    memcpy(yuv_to_rgb, yuv_to_rgb_bt601, sizeof(yuv_to_rgb_bt601));
 +
     dri_bo_unmap(render_state->curbe.bo);
 }
 diff --git a/src/shaders/render/Makefile.am b/src/shaders/render/Makefile.am
 index 1653b4a..bed683b 100644
 --- a/src/shaders/render/Makefile.am
 +++ b/src/shaders/render/Makefile.am
@@ -2,7 +2,10 @@
 INTEL_G4I =			\
 	exa_wm.g4i		\
 	exa_wm_affine.g4i	\
 -	exa_wm_yuv_color_balance.gxa
 +	exa_wm_yuv_color_balance.gxa \
 +	exa_yuv_rgb.gxa		\
 +	exa_yuv_gen4.g4i	\
 +	exa_yuv_gen6.g4i
 INTEL_G4A =				\
 	exa_sf.g4a			\
 diff --git a/src/shaders/render/exa_wm_yuv_rgb.g4a b/src/shaders/render/exa_wm_yuv_rgb.g4a
 index b3abe4b..e3d2464 100644
 --- a/src/shaders/render/exa_wm_yuv_rgb.g4a
 +++ b/src/shaders/render/exa_wm_yuv_rgb.g4a
@@ -1,5 +1,5 @@
 /*
 - * Copyright © 2006 Intel Corporation
 + * Copyright © 2006-2013 Intel Corporation
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,72 +27,6 @@
  */
 include(`exa_wm.g4i')
 +include(`exa_yuv_gen4.g4i')
 +include(`exa_yuv_rgb.gxa')
 -define(`YCbCr_base',	`src_sample_base')
 -
 -define(`Cr',		`src_sample_b')
 -define(`Cr_01',		`src_sample_b_01')
 -define(`Cr_23',		`src_sample_b_23')
 -
 -define(`Y',		`src_sample_r')
 -define(`Y_01',		`src_sample_r_01')
 -define(`Y_23',		`src_sample_r_23')
 -
 -define(`Cb',		`src_sample_g')
 -define(`Cb_01',		`src_sample_g_01')
 -define(`Cb_23',		`src_sample_g_23')
 -
 -define(`Crn',		`mask_sample_g')
 -define(`Crn_01',	`mask_sample_g_01')
 -define(`Crn_23',	`mask_sample_g_23')
 -
 -define(`Yn',		`mask_sample_r')
 -define(`Yn_01',		`mask_sample_r_01')
 -define(`Yn_23',		`mask_sample_r_23')
 -
 -define(`Cbn',		`mask_sample_b')
 -define(`Cbn_01',	`mask_sample_b_01')
 -define(`Cbn_23',	`mask_sample_b_23')
 -
 -    /* color space conversion function:
 -     * R = Clamp ( 1.164(Y-16/255) + 1.596(Cr-128/255), 0, 1)
 -     * G = Clamp ( 1.164(Y-16/255) - 0.813(Cr-128/255) - 0.392(Cb-128/255), 0, 1)
 -     * B = Clamp ( 1.164(Y-16/255) + 2.017(Cb-128/255), 0, 1)
 -     */
 -
 -    /* Normalize Y, Cb and Cr:
 -     *
 -     * Yn = (Y - 16/255) * 1.164
 -     * Crn = Cr - 128 / 255
 -     * Cbn = Cb - 128 / 255
 -     */
 -add (16)    Yn<1>F		Y<8,8,1>F	-0.0627451F { compr align1 };
 -mul (16)    Yn<1>F		Yn<8,8,1>F	1.164F	    { compr align1 };
 -
 -add (16)    Crn<1>F		Cr<8,8,1>F	-0.501961F  { compr align1 };
 -
 -add (16)    Cbn<1>F		Cb<8,8,1>F	-0.501961F  { compr align1 };
 -
 -    /* 
 -     * R = Y + Cr * 1.596
 -     */
 -mov (16)    acc0<1>F		Yn<8,8,1>F		    { compr align1 };
 -mac.sat(16) src_sample_r<1>F	Crn<8,8,1>F	1.596F	    { compr align1 };
 -     
 -    /*
 -     * G = Crn * -0.813 + Cbn * -0.392 + Y
 -     */
 -mov (16)    acc0<1>F		Yn<8,8,1>F		    { compr align1 };
 -mac (16)    acc0<1>F		Crn<8,8,1>F    	-0.813F	    { compr align1 };
 -mac.sat(16) src_sample_g<1>F	Cbn<8,8,1>F    	-0.392F	    { compr align1 };
 -
 -    /*
 -     * B = Cbn * 2.017 + Y
 -     */
 -mov (16)    acc0<1>F	        Yn<8,8,1>F		    { compr align1 };
 -mac.sat(16) src_sample_b<1>F	Cbn<8,8,1>F     2.017F	    { compr align1 };
 -
 -    /*
 -     * A = 1.0
 -     */
 -mov (16)    src_sample_a<1>F	1.0F			    { compr align1 };
 diff --git a/src/shaders/render/exa_wm_yuv_rgb.g4b b/src/shaders/render/exa_wm_yuv_rgb.g4b
 index 6b99838..b116ece 100644
 --- a/src/shaders/render/exa_wm_yuv_rgb.g4b
 +++ b/src/shaders/render/exa_wm_yuv_rgb.g4b
@@ -1,12 +1,13 @@
 -   { 0x00802040, 0x22c07fbd, 0x008d01c0, 0xbd808081 },
 -   { 0x00802041, 0x22c07fbd, 0x008d02c0, 0x3f94fdf4 },
 -   { 0x00802040, 0x23007fbd, 0x008d0240, 0xbf008084 },
 -   { 0x00802040, 0x23407fbd, 0x008d0200, 0xbf008084 },
 -   { 0x00802001, 0x240003bc, 0x008d02c0, 0x00000000 },
 -   { 0x80802048, 0x21c07fbd, 0x008d0300, 0x3fcc49ba },
 -   { 0x00802001, 0x240003bc, 0x008d02c0, 0x00000000 },
 -   { 0x00802048, 0x24007fbc, 0x008d0300, 0xbf5020c5 },
 -   { 0x80802048, 0x22007fbd, 0x008d0340, 0xbec8b439 },
 -   { 0x00802001, 0x240003bc, 0x008d02c0, 0x00000000 },
 -   { 0x80802048, 0x22407fbd, 0x008d0340, 0x40011687 },
 +   { 0x00802040, 0x22c077bd, 0x008d01c0, 0x0000006c },
 +   { 0x00802040, 0x230077bd, 0x008d0200, 0x0000007c },
 +   { 0x00802040, 0x234077bd, 0x008d0240, 0x0000008c },
 +   { 0x00802041, 0x240077bc, 0x008d02c0, 0x00000060 },
 +   { 0x00802048, 0x240077bc, 0x008d0300, 0x00000064 },
 +   { 0x80802048, 0x21c077bd, 0x008d0340, 0x00000068 },
 +   { 0x00802041, 0x240077bc, 0x008d02c0, 0x00000070 },
 +   { 0x00802048, 0x240077bc, 0x008d0300, 0x00000074 },
 +   { 0x80802048, 0x220077bd, 0x008d0340, 0x00000078 },
 +   { 0x00802041, 0x240077bc, 0x008d02c0, 0x00000080 },
 +   { 0x00802048, 0x240077bc, 0x008d0300, 0x00000084 },
 +   { 0x80802048, 0x224077bd, 0x008d0340, 0x00000088 },
    { 0x00802001, 0x228003fd, 0x00000000, 0x3f800000 },
 diff --git a/src/shaders/render/exa_wm_yuv_rgb.g4b.gen5 b/src/shaders/render/exa_wm_yuv_rgb.g4b.gen5
 index 6b99838..b116ece 100644
 --- a/src/shaders/render/exa_wm_yuv_rgb.g4b.gen5
 +++ b/src/shaders/render/exa_wm_yuv_rgb.g4b.gen5
@@ -1,12 +1,13 @@
 -   { 0x00802040, 0x22c07fbd, 0x008d01c0, 0xbd808081 },
 -   { 0x00802041, 0x22c07fbd, 0x008d02c0, 0x3f94fdf4 },
 -   { 0x00802040, 0x23007fbd, 0x008d0240, 0xbf008084 },
 -   { 0x00802040, 0x23407fbd, 0x008d0200, 0xbf008084 },
 -   { 0x00802001, 0x240003bc, 0x008d02c0, 0x00000000 },
 -   { 0x80802048, 0x21c07fbd, 0x008d0300, 0x3fcc49ba },
 -   { 0x00802001, 0x240003bc, 0x008d02c0, 0x00000000 },
 -   { 0x00802048, 0x24007fbc, 0x008d0300, 0xbf5020c5 },
 -   { 0x80802048, 0x22007fbd, 0x008d0340, 0xbec8b439 },
 -   { 0x00802001, 0x240003bc, 0x008d02c0, 0x00000000 },
 -   { 0x80802048, 0x22407fbd, 0x008d0340, 0x40011687 },
 +   { 0x00802040, 0x22c077bd, 0x008d01c0, 0x0000006c },
 +   { 0x00802040, 0x230077bd, 0x008d0200, 0x0000007c },
 +   { 0x00802040, 0x234077bd, 0x008d0240, 0x0000008c },
 +   { 0x00802041, 0x240077bc, 0x008d02c0, 0x00000060 },
 +   { 0x00802048, 0x240077bc, 0x008d0300, 0x00000064 },
 +   { 0x80802048, 0x21c077bd, 0x008d0340, 0x00000068 },
 +   { 0x00802041, 0x240077bc, 0x008d02c0, 0x00000070 },
 +   { 0x00802048, 0x240077bc, 0x008d0300, 0x00000074 },
 +   { 0x80802048, 0x220077bd, 0x008d0340, 0x00000078 },
 +   { 0x00802041, 0x240077bc, 0x008d02c0, 0x00000080 },
 +   { 0x00802048, 0x240077bc, 0x008d0300, 0x00000084 },
 +   { 0x80802048, 0x224077bd, 0x008d0340, 0x00000088 },
    { 0x00802001, 0x228003fd, 0x00000000, 0x3f800000 },
 diff --git a/src/shaders/render/exa_wm_yuv_rgb.g6a b/src/shaders/render/exa_wm_yuv_rgb.g6a
 index b3abe4b..ede0298 100644
 --- a/src/shaders/render/exa_wm_yuv_rgb.g6a
 +++ b/src/shaders/render/exa_wm_yuv_rgb.g6a
@@ -1,5 +1,5 @@
 /*
 - * Copyright © 2006 Intel Corporation
 + * Copyright © 2006-2013 Intel Corporation
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,72 +27,5 @@
  */
 include(`exa_wm.g4i')
 -
 -define(`YCbCr_base',	`src_sample_base')
 -
 -define(`Cr',		`src_sample_b')
 -define(`Cr_01',		`src_sample_b_01')
 -define(`Cr_23',		`src_sample_b_23')
 -
 -define(`Y',		`src_sample_r')
 -define(`Y_01',		`src_sample_r_01')
 -define(`Y_23',		`src_sample_r_23')
 -
 -define(`Cb',		`src_sample_g')
 -define(`Cb_01',		`src_sample_g_01')
 -define(`Cb_23',		`src_sample_g_23')
 -
 -define(`Crn',		`mask_sample_g')
 -define(`Crn_01',	`mask_sample_g_01')
 -define(`Crn_23',	`mask_sample_g_23')
 -
 -define(`Yn',		`mask_sample_r')
 -define(`Yn_01',		`mask_sample_r_01')
 -define(`Yn_23',		`mask_sample_r_23')
 -
 -define(`Cbn',		`mask_sample_b')
 -define(`Cbn_01',	`mask_sample_b_01')
 -define(`Cbn_23',	`mask_sample_b_23')
 -
 -    /* color space conversion function:
 -     * R = Clamp ( 1.164(Y-16/255) + 1.596(Cr-128/255), 0, 1)
 -     * G = Clamp ( 1.164(Y-16/255) - 0.813(Cr-128/255) - 0.392(Cb-128/255), 0, 1)
 -     * B = Clamp ( 1.164(Y-16/255) + 2.017(Cb-128/255), 0, 1)
 -     */
 -
 -    /* Normalize Y, Cb and Cr:
 -     *
 -     * Yn = (Y - 16/255) * 1.164
 -     * Crn = Cr - 128 / 255
 -     * Cbn = Cb - 128 / 255
 -     */
 -add (16)    Yn<1>F		Y<8,8,1>F	-0.0627451F { compr align1 };
 -mul (16)    Yn<1>F		Yn<8,8,1>F	1.164F	    { compr align1 };
 -
 -add (16)    Crn<1>F		Cr<8,8,1>F	-0.501961F  { compr align1 };
 -
 -add (16)    Cbn<1>F		Cb<8,8,1>F	-0.501961F  { compr align1 };
 -
 -    /* 
 -     * R = Y + Cr * 1.596
 -     */
 -mov (16)    acc0<1>F		Yn<8,8,1>F		    { compr align1 };
 -mac.sat(16) src_sample_r<1>F	Crn<8,8,1>F	1.596F	    { compr align1 };
 -     
 -    /*
 -     * G = Crn * -0.813 + Cbn * -0.392 + Y
 -     */
 -mov (16)    acc0<1>F		Yn<8,8,1>F		    { compr align1 };
 -mac (16)    acc0<1>F		Crn<8,8,1>F    	-0.813F	    { compr align1 };
 -mac.sat(16) src_sample_g<1>F	Cbn<8,8,1>F    	-0.392F	    { compr align1 };
 -
 -    /*
 -     * B = Cbn * 2.017 + Y
 -     */
 -mov (16)    acc0<1>F	        Yn<8,8,1>F		    { compr align1 };
 -mac.sat(16) src_sample_b<1>F	Cbn<8,8,1>F     2.017F	    { compr align1 };
 -
 -    /*
 -     * A = 1.0
 -     */
 -mov (16)    src_sample_a<1>F	1.0F			    { compr align1 };
 +include(`exa_yuv_gen6.g4i')
 +include(`exa_yuv_rgb.gxa')
 diff --git a/src/shaders/render/exa_wm_yuv_rgb.g6b b/src/shaders/render/exa_wm_yuv_rgb.g6b
 index 6c8c724..d09ae00 100644
 --- a/src/shaders/render/exa_wm_yuv_rgb.g6b
 +++ b/src/shaders/render/exa_wm_yuv_rgb.g6b
@@ -1,12 +1,13 @@
 -   { 0x00800040, 0x22c07fbd, 0x008d01c0, 0xbd808081 },
 -   { 0x00800041, 0x22c07fbd, 0x008d02c0, 0x3f94fdf4 },
 -   { 0x00800040, 0x23007fbd, 0x008d0240, 0xbf008084 },
 -   { 0x00800040, 0x23407fbd, 0x008d0200, 0xbf008084 },
 -   { 0x00800001, 0x240003bc, 0x008d02c0, 0x00000000 },
 -   { 0x80800048, 0x21c07fbd, 0x008d0300, 0x3fcc49ba },
 -   { 0x00800001, 0x240003bc, 0x008d02c0, 0x00000000 },
 -   { 0x00800048, 0x24007fbc, 0x008d0300, 0xbf5020c5 },
 -   { 0x80800048, 0x22007fbd, 0x008d0340, 0xbec8b439 },
 -   { 0x00800001, 0x240003bc, 0x008d02c0, 0x00000000 },
 -   { 0x80800048, 0x22407fbd, 0x008d0340, 0x40011687 },
 +   { 0x00800040, 0x22c077bd, 0x008d01c0, 0x000000ec },
 +   { 0x00800040, 0x230077bd, 0x008d0200, 0x000000fc },
 +   { 0x00800040, 0x234077bd, 0x008d0240, 0x0000010c },
 +   { 0x00800041, 0x240077bc, 0x008d02c0, 0x000000e0 },
 +   { 0x00800048, 0x240077bc, 0x008d0300, 0x000000e4 },
 +   { 0x80800048, 0x21c077bd, 0x008d0340, 0x000000e8 },
 +   { 0x00800041, 0x240077bc, 0x008d02c0, 0x000000f0 },
 +   { 0x00800048, 0x240077bc, 0x008d0300, 0x000000f4 },
 +   { 0x80800048, 0x220077bd, 0x008d0340, 0x000000f8 },
 +   { 0x00800041, 0x240077bc, 0x008d02c0, 0x00000100 },
 +   { 0x00800048, 0x240077bc, 0x008d0300, 0x00000104 },
 +   { 0x80800048, 0x224077bd, 0x008d0340, 0x00000108 },
    { 0x00800001, 0x228003fd, 0x00000000, 0x3f800000 },
 diff --git a/src/shaders/render/exa_wm_yuv_rgb.g7a b/src/shaders/render/exa_wm_yuv_rgb.g7a
 index 5cd33e2..ede0298 100644
 --- a/src/shaders/render/exa_wm_yuv_rgb.g7a
 +++ b/src/shaders/render/exa_wm_yuv_rgb.g7a
@@ -1,5 +1,5 @@
 /*
 - * Copyright © 2006 Intel Corporation
 + * Copyright © 2006-2013 Intel Corporation
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -27,72 +27,5 @@
  */
 include(`exa_wm.g4i')
 -
 -define(`YCbCr_base',	`src_sample_base')
 -
 -define(`Cr',		`src_sample_b')
 -define(`Cr_01',		`src_sample_b_01')
 -define(`Cr_23',		`src_sample_b_23')
 -
 -define(`Y',		`src_sample_r')
 -define(`Y_01',		`src_sample_r_01')
 -define(`Y_23',		`src_sample_r_23')
 -
 -define(`Cb',		`src_sample_g')
 -define(`Cb_01',		`src_sample_g_01')
 -define(`Cb_23',		`src_sample_g_23')
 -
 -define(`Crn',		`mask_sample_g')
 -define(`Crn_01',	`mask_sample_g_01')
 -define(`Crn_23',	`mask_sample_g_23')
 -
 -define(`Yn',		`mask_sample_r')
 -define(`Yn_01',		`mask_sample_r_01')
 -define(`Yn_23',		`mask_sample_r_23')
 -
 -define(`Cbn',		`mask_sample_b')
 -define(`Cbn_01',	`mask_sample_b_01')
 -define(`Cbn_23',	`mask_sample_b_23')
 -
 -    /* color space conversion function:
 -     * R = Clamp ( 1.164(Y-16/255) + 1.596(Cr-128/255), 0, 1)
 -     * G = Clamp ( 1.164(Y-16/255) - 0.813(Cr-128/255) - 0.392(Cb-128/255), 0, 1)
 -     * B = Clamp ( 1.164(Y-16/255) + 2.017(Cb-128/255), 0, 1)
 -     */
 -
 -    /* Normalize Y, Cb and Cr:
 -     *
 -     * Yn = (Y - 16/255) * 1.164
 -     * Crn = Cr - 128 / 255
 -     * Cbn = Cb - 128 / 255
 -     */
 -add (16)    Yn<1>F		Y<8,8,1>F	-0.0627451F { compr align1 };
 -mul (16)    Yn<1>F		Yn<8,8,1>F	1.164F	    { compr align1 };
 -
 -add (16)    Crn<1>F		Cr<8,8,1>F	-0.501961F  { compr align1 };
 -
 -add (16)    Cbn<1>F		Cb<8,8,1>F	-0.501961F  { compr align1 };
 -
 -    /* 
 -     * R = Y + Cr * 1.596
 -     */
 -mov (16)    acc0<1>F		Yn<8,8,1>F		    { compr align1 };
 -mac.sat(16) src_sample_r<1>F	Crn<8,8,1>F	1.596F	    { compr align1 };
 -     
 -    /*
 -     * G = Crn * -0.813 + Cbn * -0.392 + Y
 -     */
 -mov (16)    acc0<1>F		Yn<8,8,1>F		    { compr align1 };
 -mac (16)    acc0<1>F		Crn<8,8,1>F    	-0.813F	    { compr align1 };
 -mac.sat(16) src_sample_g<1>F	Cbn<8,8,1>F    	-0.392F	    { compr align1 };
 -
 -    /*
 -     * B = Cbn * 2.017 + Y
 -     */
 -mov (16)    acc0<1>F	        Yn<8,8,1>F		    { compr align1 };
 -mac.sat(16) src_sample_b<1>F	Cbn<8,8,1>F     2.017F	    { compr align1 };
 -
 -    /*
 -     * A = 1.0
 -     */
 -mov (16)    src_sample_a<1>F	1.0F        { compr align1 };
 +include(`exa_yuv_gen6.g4i')
 +include(`exa_yuv_rgb.gxa')
 diff --git a/src/shaders/render/exa_wm_yuv_rgb.g7b b/src/shaders/render/exa_wm_yuv_rgb.g7b
 index 6c8c724..d09ae00 100644
 --- a/src/shaders/render/exa_wm_yuv_rgb.g7b
 +++ b/src/shaders/render/exa_wm_yuv_rgb.g7b
@@ -1,12 +1,13 @@
 -   { 0x00800040, 0x22c07fbd, 0x008d01c0, 0xbd808081 },
 -   { 0x00800041, 0x22c07fbd, 0x008d02c0, 0x3f94fdf4 },
 -   { 0x00800040, 0x23007fbd, 0x008d0240, 0xbf008084 },
 -   { 0x00800040, 0x23407fbd, 0x008d0200, 0xbf008084 },
 -   { 0x00800001, 0x240003bc, 0x008d02c0, 0x00000000 },
 -   { 0x80800048, 0x21c07fbd, 0x008d0300, 0x3fcc49ba },
 -   { 0x00800001, 0x240003bc, 0x008d02c0, 0x00000000 },
 -   { 0x00800048, 0x24007fbc, 0x008d0300, 0xbf5020c5 },
 -   { 0x80800048, 0x22007fbd, 0x008d0340, 0xbec8b439 },
 -   { 0x00800001, 0x240003bc, 0x008d02c0, 0x00000000 },
 -   { 0x80800048, 0x22407fbd, 0x008d0340, 0x40011687 },
 +   { 0x00800040, 0x22c077bd, 0x008d01c0, 0x000000ec },
 +   { 0x00800040, 0x230077bd, 0x008d0200, 0x000000fc },
 +   { 0x00800040, 0x234077bd, 0x008d0240, 0x0000010c },
 +   { 0x00800041, 0x240077bc, 0x008d02c0, 0x000000e0 },
 +   { 0x00800048, 0x240077bc, 0x008d0300, 0x000000e4 },
 +   { 0x80800048, 0x21c077bd, 0x008d0340, 0x000000e8 },
 +   { 0x00800041, 0x240077bc, 0x008d02c0, 0x000000f0 },
 +   { 0x00800048, 0x240077bc, 0x008d0300, 0x000000f4 },
 +   { 0x80800048, 0x220077bd, 0x008d0340, 0x000000f8 },
 +   { 0x00800041, 0x240077bc, 0x008d02c0, 0x00000100 },
 +   { 0x00800048, 0x240077bc, 0x008d0300, 0x00000104 },
 +   { 0x80800048, 0x224077bd, 0x008d0340, 0x00000108 },
    { 0x00800001, 0x228003fd, 0x00000000, 0x3f800000 },
 diff --git a/src/shaders/render/exa_yuv_gen4.g4i b/src/shaders/render/exa_yuv_gen4.g4i
 new file mode 100644
 index 0000000..5a66616
 --- /dev/null
 +++ b/src/shaders/render/exa_yuv_gen4.g4i
@@ -0,0 +1,42 @@
 +/*
 + * Copyright © 2013 Intel Corporation
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a
 + * copy of this software and associated documentation files (the "Software"),
 + * to deal in the Software without restriction, including without limitation
 + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 + * and/or sell copies of the Software, and to permit persons to whom the
 + * Software is furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice (including the next
 + * paragraph) shall be included in all copies or substantial portions of the
 + * Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 + * IN THE SOFTWARE.
 + *
 + * Authors:
 + *    Zhao Yakui <yakui.zhao@intel.com>
 + */
 +
 +/* YUV to RGB matrix coeff */
 +
 +define(`coef_ry',	`g3.0<0,1,0>F')
 +define(`coef_ru',	`g3.4<0,1,0>F')
 +define(`coef_rv',	`g3.8<0,1,0>F')
 +define(`coef_yd',	`g3.12<0,1,0>F')
 +
 +define(`coef_gy',	`g3.16<0,1,0>F')
 +define(`coef_gu',	`g3.20<0,1,0>F')
 +define(`coef_gv',	`g3.24<0,1,0>F')
 +define(`coef_ud',	`g3.28<0,1,0>F')
 +
 +define(`coef_by',	`g4.0<0,1,0>F')
 +define(`coef_bu',	`g4.4<0,1,0>F')
 +define(`coef_bv',	`g4.8<0,1,0>F')
 +define(`coef_vd',	`g4.12<0,1,0>F')
 diff --git a/src/shaders/render/exa_yuv_gen6.g4i b/src/shaders/render/exa_yuv_gen6.g4i
 new file mode 100644
 index 0000000..a8d69ee
 --- /dev/null
 +++ b/src/shaders/render/exa_yuv_gen6.g4i
@@ -0,0 +1,42 @@
 +/*
 + * Copyright © 2013 Intel Corporation
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a
 + * copy of this software and associated documentation files (the "Software"),
 + * to deal in the Software without restriction, including without limitation
 + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 + * and/or sell copies of the Software, and to permit persons to whom the
 + * Software is furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice (including the next
 + * paragraph) shall be included in all copies or substantial portions of the
 + * Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 + * IN THE SOFTWARE.
 + *
 + * Authors:
 + *    Zhao Yakui <yakui.zhao@intel.com>
 + */
 +/* YUV to RGB matrix coeff */
 +
 +
 +define(`coef_ry',	`g7.0<0,1,0>F')
 +define(`coef_ru',	`g7.4<0,1,0>F')
 +define(`coef_rv',	`g7.8<0,1,0>F')
 +define(`coef_yd',	`g7.12<0,1,0>F')
 +
 +define(`coef_gy',	`g7.16<0,1,0>F')
 +define(`coef_gu',	`g7.20<0,1,0>F')
 +define(`coef_gv',	`g7.24<0,1,0>F')
 +define(`coef_ud',	`g7.28<0,1,0>F')
 +
 +define(`coef_by',	`g8.0<0,1,0>F')
 +define(`coef_bu',	`g8.4<0,1,0>F')
 +define(`coef_bv',	`g8.8<0,1,0>F')
 +define(`coef_vd',	`g8.12<0,1,0>F')
 diff --git a/src/shaders/render/exa_yuv_rgb.gxa b/src/shaders/render/exa_yuv_rgb.gxa
 new file mode 100644
 index 0000000..656ae73
 --- /dev/null
 +++ b/src/shaders/render/exa_yuv_rgb.gxa
@@ -0,0 +1,74 @@
 +/*
 + * Copyright © 2013 Intel Corporation
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a
 + * copy of this software and associated documentation files (the "Software"),
 + * to deal in the Software without restriction, including without limitation
 + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 + * and/or sell copies of the Software, and to permit persons to whom the
 + * Software is furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice (including the next
 + * paragraph) shall be included in all copies or substantial portions of the
 + * Software.
 + *
 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 + * IN THE SOFTWARE.
 + *
 + * Authors:
 + *    Zhao Yakui <yakui.zhao@intel.com>
 + */
 +
 +define(`YCbCr_base',	`src_sample_base')
 +
 +define(`Cr',		`src_sample_b')
 +define(`Cr_01',		`src_sample_b_01')
 +define(`Cr_23',		`src_sample_b_23')
 +
 +define(`Y',		`src_sample_r')
 +define(`Y_01',		`src_sample_r_01')
 +define(`Y_23',		`src_sample_r_23')
 +
 +define(`Cb',		`src_sample_g')
 +define(`Cb_01',		`src_sample_g_01')
 +define(`Cb_23',		`src_sample_g_23')
 +
 +define(`Crn',		`mask_sample_b')
 +define(`Crn_01',	`mask_sample_b_01')
 +define(`Crn_23',	`mask_sample_b_23')
 +
 +define(`Yn',		`mask_sample_r')
 +define(`Yn_01',		`mask_sample_r_01')
 +define(`Yn_23',		`mask_sample_r_23')
 +
 +define(`Cbn',		`mask_sample_g')
 +define(`Cbn_01',	`mask_sample_g_01')
 +define(`Cbn_23',	`mask_sample_g_23')
 +
 +add (16)    Yn<1>F		Y<8,8,1>F	coef_yd	    { compr align1 };
 +
 +add (16)    Cbn<1>F		Cb<8,8,1>F	coef_ud	    { compr align1 };
 +
 +add (16)    Crn<1>F		Cr<8,8,1>F	coef_vd     { compr align1 };
 +
 +mul (16)    acc0<1>F		Yn<8,8,1>F	coef_ry	    { compr align1 };
 +mac (16)    acc0<1>F		Cbn<8,8,1>F	coef_ru	    { compr align1 };
 +mac.sat (16) src_sample_r<1>F	Crn<8,8,1>F	coef_rv	    { compr align1 };
 +     
 +mul (16)    acc0<1>F		Yn<8,8,1>F	coef_gy	    { compr align1 };
 +mac (16)    acc0<1>F		Cbn<8,8,1>F	coef_gu	    { compr align1 };
 +mac.sat(16) src_sample_g<1>F	Crn<8,8,1>F    	coef_gv	    { compr align1 };
 +
 +mul (16)    acc0<1>F		Yn<8,8,1>F	coef_by	    { compr align1 };
 +mac (16)    acc0<1>F		Cbn<8,8,1>F	coef_bu	    { compr align1 };
 +mac.sat(16) src_sample_b<1>F	Crn<8,8,1>F    	coef_bv	    { compr align1 };
 +
 +    /*
 +     * A = 1.0
 +     */
 +mov (16)    src_sample_a<1>F	1.0F			    { compr align1 };
 -- 
 1.8.3.2
--- a/packages/multimedia/libva-driver-intel/patches.upstream/0004-Support-the-BT709-color-standard-for-conversion-from.patch
+++ b/packages/multimedia/libva-driver-intel/patches.upstream/0004-Support-the-BT709-color-standard-for-conversion-from.patch
@ -0,0 +1,130 @@
 From 9c5a739430029aece3b9e29bd3e3ae612e46c6f0 Mon Sep 17 00:00:00 2001
 From: Zhao Yakui <yakui.zhao@intel.com>
 Date: Fri, 22 Nov 2013 13:39:34 +0800
 Subject: [PATCH 4/5] Support the BT709 color standard for conversion from YUV
 to RGB
 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
 ---
 src/i965_output_dri.c |  7 +++++++
 src/i965_render.c     | 22 +++++++++++++++++-----
 src/i965_render.h     |  2 ++
 3 files changed, 26 insertions(+), 5 deletions(-)
 diff --git a/src/i965_output_dri.c b/src/i965_output_dri.c
 index de7be92..1467367 100644
 --- a/src/i965_output_dri.c
 +++ b/src/i965_output_dri.c
@@ -127,6 +127,7 @@ i965_put_surface_dri(
     bool new_region = false;
     uint32_t name;
     int i, ret;
 +    unsigned int color_flag = 0;
     /* Currently don't support DRI1 */
     if (!VA_CHECK_DRM_AUTH_TYPE(ctx, VA_DRM_AUTH_DRI2))
@@ -179,6 +180,12 @@ i965_put_surface_dri(
         assert(ret == 0);
     }
 +    color_flag = flags & VA_SRC_COLOR_MASK;
 +    if (color_flag == 0)
 +        color_flag = VA_SRC_BT601;
 +
 +    pp_flag = color_flag;
 +
     if ((flags & VA_FILTER_SCALING_MASK) == VA_FILTER_SCALING_NL_ANAMORPHIC)
         pp_flag |= I965_PP_FLAG_AVS;
 diff --git a/src/i965_render.c b/src/i965_render.c
 index 5b1a1a5..5be8a96 100644
 --- a/src/i965_render.c
 +++ b/src/i965_render.c
@@ -317,6 +317,12 @@ static float yuv_to_rgb_bt601[3][4] = {
 {1.164,		2.017,	0,		-0.50196,},
 };
 +static float yuv_to_rgb_bt709[3][4] = {
 +{1.164,		0,	1.793,		-0.06275,},
 +{1.164,		-0.213,	-0.533,		-0.50196,},
 +{1.164,		2.112,	0,		-0.50196,},
 +};
 +
 static void
 i965_render_vs_unit(VADriverContextP ctx)
 {
@@ -1066,7 +1072,8 @@ i965_render_upload_vertex(
 static void
 i965_render_upload_constants(VADriverContextP ctx,
 -                             struct object_surface *obj_surface)
 +                             struct object_surface *obj_surface,
 +                             unsigned int flags)
 {
     struct i965_driver_data *i965 = i965_driver_data(ctx);
     struct i965_render_state *render_state = &i965->render_state;
@@ -1077,6 +1084,7 @@ i965_render_upload_constants(VADriverContextP ctx,
     float hue = (float)i965->hue_attrib->value / 180 * PI;
     float saturation = (float)i965->saturation_attrib->value / DEFAULT_SATURATION;
     float *yuv_to_rgb;
 +    unsigned int color_flag;
     dri_bo_map(render_state->curbe.bo, 1);
     assert(render_state->curbe.bo->virtual);
@@ -1107,8 +1115,12 @@ i965_render_upload_constants(VADriverContextP ctx,
     *color_balance_base++ = cos(hue) * contrast * saturation;
     *color_balance_base++ = sin(hue) * contrast * saturation;
 +    color_flag = flags & VA_SRC_COLOR_MASK;
     yuv_to_rgb = (float *)constant_buffer + 8;
 -    memcpy(yuv_to_rgb, yuv_to_rgb_bt601, sizeof(yuv_to_rgb_bt601));
 +    if (color_flag == VA_SRC_BT709)
 +        memcpy(yuv_to_rgb, yuv_to_rgb_bt709, sizeof(yuv_to_rgb_bt709));
 +    else
 +        memcpy(yuv_to_rgb, yuv_to_rgb_bt601, sizeof(yuv_to_rgb_bt601));
     dri_bo_unmap(render_state->curbe.bo);
 }
@@ -1155,7 +1167,7 @@ i965_surface_render_state_setup(
     i965_render_cc_viewport(ctx);
     i965_render_cc_unit(ctx);
     i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
 -    i965_render_upload_constants(ctx, obj_surface);
 +    i965_render_upload_constants(ctx, obj_surface, flags);
 }
 static void
@@ -1842,7 +1854,7 @@ gen6_render_setup_states(
     gen6_render_color_calc_state(ctx);
     gen6_render_blend_state(ctx);
     gen6_render_depth_stencil_state(ctx);
 -    i965_render_upload_constants(ctx, obj_surface);
 +    i965_render_upload_constants(ctx, obj_surface, flags);
     i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
 }
@@ -2436,7 +2448,7 @@ gen7_render_setup_states(
     gen7_render_color_calc_state(ctx);
     gen7_render_blend_state(ctx);
     gen7_render_depth_stencil_state(ctx);
 -    i965_render_upload_constants(ctx, obj_surface);
 +    i965_render_upload_constants(ctx, obj_surface, flags);
     i965_render_upload_vertex(ctx, obj_surface, src_rect, dst_rect);
 }
 diff --git a/src/i965_render.h b/src/i965_render.h
 index f09b535..1960ace 100644
 --- a/src/i965_render.h
 +++ b/src/i965_render.h
@@ -33,6 +33,8 @@
 #define NUM_RENDER_KERNEL       3
 +#define VA_SRC_COLOR_MASK       0x000000f0
 +
 #include "i965_post_processing.h"
 struct i965_kernel;
 -- 
 1.8.3.2
--- a/packages/multimedia/libva-driver-intel/patches.upstream/0005-Support-the-smpte240m-color-standard-for-conversion-.patch
+++ b/packages/multimedia/libva-driver-intel/patches.upstream/0005-Support-the-smpte240m-color-standard-for-conversion-.patch
@ -0,0 +1,40 @@
 From a653c376d7650bf967a753cd4bda68bfeab5f4eb Mon Sep 17 00:00:00 2001
 From: Zhao Yakui <yakui.zhao@intel.com>
 Date: Fri, 22 Nov 2013 13:39:34 +0800
 Subject: [PATCH 5/5] Support the smpte240m color standard for conversion from
 YUV to RGB
 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
 ---
 src/i965_render.c | 8 ++++++++
 1 file changed, 8 insertions(+)
 diff --git a/src/i965_render.c b/src/i965_render.c
 index 5be8a96..92270cb 100644
 --- a/src/i965_render.c
 +++ b/src/i965_render.c
@@ -323,6 +323,12 @@ static float yuv_to_rgb_bt709[3][4] = {
 {1.164,		2.112,	0,		-0.50196,},
 };
 +static float yuv_to_rgb_smpte_240[3][4] = {
 +{1.164,		0,	1.794,		-0.06275,},
 +{1.164,		-0.258,	-0.5425,	-0.50196,},
 +{1.164,		2.078,	0,		-0.50196,},
 +};
 +
 static void
 i965_render_vs_unit(VADriverContextP ctx)
 {
@@ -1119,6 +1125,8 @@ i965_render_upload_constants(VADriverContextP ctx,
     yuv_to_rgb = (float *)constant_buffer + 8;
     if (color_flag == VA_SRC_BT709)
         memcpy(yuv_to_rgb, yuv_to_rgb_bt709, sizeof(yuv_to_rgb_bt709));
 +    else if (color_flag == VA_SRC_SMPTE_240)
 +        memcpy(yuv_to_rgb, yuv_to_rgb_smpte_240, sizeof(yuv_to_rgb_smpte_240));
     else
         memcpy(yuv_to_rgb, yuv_to_rgb_bt601, sizeof(yuv_to_rgb_bt601));
 -- 
 1.8.3.2
--- a/packages/multimedia/libva-driver-intel/patches.upstream/0006-libva-driver-intel-fix-surface_empty.patch
+++ b/packages/multimedia/libva-driver-intel/patches.upstream/0006-libva-driver-intel-fix-surface_empty.patch
--- a/packages/sysutils/systemd/package.mk
+++ b/packages/sysutils/systemd/package.mk
@ -152,6 +152,22 @@ post_makeinstall_target() {
  # remove debug-shell.service, we install our own
    rm -rf $INSTALL/lib/systemd/system/debug-shell.service
  # remove systemd-update-utmp. pointless
    rm -rf $INSTALL/lib/systemd/systemd-update-utmp
    rm -rf $INSTALL/lib/systemd/system/systemd-update-utmp-runlevel.service
    rm -rf $INSTALL/lib/systemd/system/systemd-update-utmp.service
    rm -rf $INSTALL/lib/systemd/system/sysinit.target.wants/systemd-update-utmp.service
  # remove systemd-ask-password. pointless
    rm -rf $INSTALL/lib/systemd/system/systemd-ask-password-wall.service
    rm -rf $INSTALL/lib/systemd/system/systemd-ask-password-wall.path
    rm -rf $INSTALL/lib/systemd/system/systemd-ask-password-console.path
    rm -rf $INSTALL/lib/systemd/system/systemd-ask-password-console.service
    rm -rf $INSTALL/bin/systemd-ask-password
    rm -rf $INSTALL/bin/systemd-tty-ask-password-agent
    rm -rf $INSTALL/lib/systemd/system/sysinit.target.wants/systemd-ask-password-console.path
    rm -rf $INSTALL/lib/systemd/system/multi-user.target.wants/systemd-ask-password-wall.path
  # remove some generators we never use
    rm -rf $INSTALL/lib/systemd/system-generators/systemd-fstab-generator
--- a/packages/sysutils/timezone-data/system.d/tz-data-monitor.path
+++ b/packages/sysutils/timezone-data/system.d/tz-data-monitor.path
@ -3,7 +3,7 @@ Description=Timezone data monitor
 After=local-fs.target
 [Path]
-PathModified=/storage/.xbmc/userdata/guisettings.xml
+PathChanged=/storage/.xbmc/userdata/guisettings.xml
 [Install]
 WantedBy=multi-user.target
--- a/packages/sysutils/timezone-data/system.d/tz-data-monitor.service
+++ b/packages/sysutils/timezone-data/system.d/tz-data-monitor.service
@ -4,6 +4,7 @@ Description=Timezone data monitor
 [Service]
 Type=oneshot
 ExecStart=/bin/systemctl restart tz-data.service
 StartLimitInterval=0
 [Install]
 WantedBy=multi-user.target
--- a/packages/sysutils/timezone-data/system.d/tz-data.service
+++ b/packages/sysutils/timezone-data/system.d/tz-data.service
@ -8,6 +8,7 @@ ConditionPathExists=/storage/.xbmc/userdata/guisettings.xml
 Type=oneshot
 ExecStart=/usr/lib/openelec/tzdata-setup
 RemainAfterExit=yes
 StartLimitInterval=0
 [Install]
 WantedBy=xbmc.service
--- a/projects/ARCTIC_MC/linux/linux.x86_64.conf
+++ b/projects/ARCTIC_MC/linux/linux.x86_64.conf
@ -3333,9 +3333,7 @@ CONFIG_RTS5139=m
 # CONFIG_VT6655 is not set
 CONFIG_VT6656=m
 # CONFIG_DX_SEP is not set
-CONFIG_ZSMALLOC=y
+# CONFIG_ZSMALLOC is not set
 CONFIG_ZRAM=y
 # CONFIG_ZRAM_DEBUG is not set
 # CONFIG_FB_SM7XX is not set
 # CONFIG_CRYSTALHD is not set
 # CONFIG_FB_XGI is not set
--- a/projects/ATV/linux/linux.i386.conf
+++ b/projects/ATV/linux/linux.i386.conf
@ -2852,9 +2852,7 @@ CONFIG_RTS5139=m
 # CONFIG_VT6655 is not set
 # CONFIG_VT6656 is not set
 # CONFIG_DX_SEP is not set
-CONFIG_ZSMALLOC=y
+# CONFIG_ZSMALLOC is not set
 CONFIG_ZRAM=y
 # CONFIG_ZRAM_DEBUG is not set
 # CONFIG_FB_SM7XX is not set
 # CONFIG_CRYSTALHD is not set
 # CONFIG_FB_XGI is not set
--- a/projects/Generic/linux/linux.i386.conf
+++ b/projects/Generic/linux/linux.i386.conf
@ -3363,9 +3363,7 @@ CONFIG_RTS5139=m
 # CONFIG_VT6655 is not set
 CONFIG_VT6656=m
 # CONFIG_DX_SEP is not set
-CONFIG_ZSMALLOC=y
+# CONFIG_ZSMALLOC is not set
 CONFIG_ZRAM=y
 # CONFIG_ZRAM_DEBUG is not set
 # CONFIG_FB_SM7XX is not set
 # CONFIG_CRYSTALHD is not set
 # CONFIG_FB_XGI is not set
--- a/projects/Generic/linux/linux.x86_64.conf
+++ b/projects/Generic/linux/linux.x86_64.conf
@ -3332,9 +3332,7 @@ CONFIG_RTS5139=m
 # CONFIG_VT6655 is not set
 CONFIG_VT6656=m
 # CONFIG_DX_SEP is not set
-CONFIG_ZSMALLOC=y
+# CONFIG_ZSMALLOC is not set
 CONFIG_ZRAM=y
 # CONFIG_ZRAM_DEBUG is not set
 # CONFIG_FB_SM7XX is not set
 # CONFIG_CRYSTALHD is not set
 # CONFIG_FB_XGI is not set
--- a/projects/RPi/linux/linux.arm.conf
+++ b/projects/RPi/linux/linux.arm.conf
@ -2378,9 +2378,7 @@ CONFIG_RTS5139=m
 # CONFIG_TRANZPORT is not set
 # CONFIG_USB_SERIAL_QUATECH2 is not set
 CONFIG_VT6656=m
-CONFIG_ZSMALLOC=y
+# CONFIG_ZSMALLOC is not set
 CONFIG_ZRAM=y
 # CONFIG_ZRAM_DEBUG is not set
 # CONFIG_USB_ENESTORAGE is not set
 # CONFIG_BCM_WIMAX is not set
 # CONFIG_FT1000 is not set
--- a/projects/Virtual/linux/linux.i386.conf
+++ b/projects/Virtual/linux/linux.i386.conf
@ -3363,9 +3363,7 @@ CONFIG_RTS5139=m
 # CONFIG_VT6655 is not set
 CONFIG_VT6656=m
 # CONFIG_DX_SEP is not set
-CONFIG_ZSMALLOC=y
+# CONFIG_ZSMALLOC is not set
 CONFIG_ZRAM=y
 # CONFIG_ZRAM_DEBUG is not set
 # CONFIG_FB_SM7XX is not set
 # CONFIG_CRYSTALHD is not set
 # CONFIG_FB_XGI is not set
--- a/projects/Virtual/linux/linux.x86_64.conf
+++ b/projects/Virtual/linux/linux.x86_64.conf
@ -3332,9 +3332,7 @@ CONFIG_RTS5139=m
 # CONFIG_VT6655 is not set
 CONFIG_VT6656=m
 # CONFIG_DX_SEP is not set
-CONFIG_ZSMALLOC=y
+# CONFIG_ZSMALLOC is not set
 CONFIG_ZRAM=y
 # CONFIG_ZRAM_DEBUG is not set
 # CONFIG_FB_SM7XX is not set
 # CONFIG_CRYSTALHD is not set
 # CONFIG_FB_XGI is not set