linux: update to linux-3.15-rc5

packages/linux/patches/3.15-rc4/linux-999.03-drm-radeon-PLL-fixes.patch

@@ -1,379 +0,0 @@
-From 514738e09ec3ec0d1fb15cc3eabe4698b0d51358 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Fri, 4 Apr 2014 13:45:42 +0200
-Subject: [PATCH 2/6] drm/radeon: apply more strict limits for PLL params v2
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Letting post and refernce divider get to big is bad for signal stability.
-
-v2: increase the limit to 210
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/radeon/radeon_display.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
-index 4e83ffd..35129ad 100644
---- a/drivers/gpu/drm/radeon/radeon_display.c
-+++ b/drivers/gpu/drm/radeon/radeon_display.c
-@@ -936,6 +936,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
- 	}
- 	post_div = post_div_best;
- 
-+	/* limit reference * post divider to a maximum */
-+	ref_div_max = min(210 / post_div, ref_div_max);
-+
- 	/* get matching reference and feedback divider */
- 	ref_div = max(den / post_div, 1u);
- 	fb_div = nom;
--- 
-1.9.1
-
-From 6e26c28955078c20a78a41e03911d67b5f85bd55 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
-Date: Wed, 23 Apr 2014 20:46:06 +0200
-Subject: [PATCH 6/6] drm/radeon: use pflip irq on R600+
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Christian König <christian.koenig@amd.com>
----
- drivers/gpu/drm/radeon/cik.c            | 76 +++++++++++++++++++++++++++++++++
- drivers/gpu/drm/radeon/cikd.h           |  9 ++++
- drivers/gpu/drm/radeon/evergreen.c      | 28 +++++++++---
- drivers/gpu/drm/radeon/r600.c           | 10 +++--
- drivers/gpu/drm/radeon/radeon.h         |  6 +++
- drivers/gpu/drm/radeon/radeon_display.c |  4 ++
- drivers/gpu/drm/radeon/si.c             | 28 +++++++++---
- 7 files changed, 144 insertions(+), 17 deletions(-)
-
-diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
-index bbb1784..e29c9b2 100644
---- a/drivers/gpu/drm/radeon/cik.c
-+++ b/drivers/gpu/drm/radeon/cik.c
-@@ -6662,6 +6662,19 @@ static void cik_disable_interrupt_state(struct radeon_device *rdev)
- 		WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
- 		WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
- 	}
-+	/* pflip */
-+	if (rdev->num_crtc >= 2) {
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
-+	}
-+	if (rdev->num_crtc >= 4) {
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
-+	}
-+	if (rdev->num_crtc >= 6) {
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
-+	}
- 
- 	/* dac hotplug */
- 	WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
-@@ -7018,6 +7031,25 @@ int cik_irq_set(struct radeon_device *rdev)
- 		WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
- 	}
- 
-+	if (rdev->num_crtc >= 2) {
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_MASK);
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_MASK);
-+	}
-+	if (rdev->num_crtc >= 4) {
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_MASK);
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_MASK);
-+	}
-+	if (rdev->num_crtc >= 6) {
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_MASK);
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_MASK);
-+	}
-+
- 	WREG32(DC_HPD1_INT_CONTROL, hpd1);
- 	WREG32(DC_HPD2_INT_CONTROL, hpd2);
- 	WREG32(DC_HPD3_INT_CONTROL, hpd3);
-@@ -7054,6 +7086,29 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
- 	rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
- 	rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);
- 
-+	rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +
-+		EVERGREEN_CRTC0_REGISTER_OFFSET);
-+	rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +
-+		EVERGREEN_CRTC1_REGISTER_OFFSET);
-+	if (rdev->num_crtc >= 4) {
-+		rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +
-+			EVERGREEN_CRTC2_REGISTER_OFFSET);
-+		rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +
-+			EVERGREEN_CRTC3_REGISTER_OFFSET);
-+	}
-+	if (rdev->num_crtc >= 6) {
-+		rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +
-+			EVERGREEN_CRTC4_REGISTER_OFFSET);
-+		rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +
-+			EVERGREEN_CRTC5_REGISTER_OFFSET);
-+	}
-+
-+	if (rdev->irq.stat_regs.cik.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
-+		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_CLEAR);
-+	if (rdev->irq.stat_regs.cik.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
-+		WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_CLEAR);
- 	if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)
- 		WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
- 	if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)
-@@ -7064,6 +7119,12 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
- 		WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
- 
- 	if (rdev->num_crtc >= 4) {
-+		if (rdev->irq.stat_regs.cik.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
-+			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
-+			       GRPH_PFLIP_INT_CLEAR);
-+		if (rdev->irq.stat_regs.cik.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
-+			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
-+			       GRPH_PFLIP_INT_CLEAR);
- 		if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
- 			WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
- 		if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
-@@ -7075,6 +7136,12 @@ static inline void cik_irq_ack(struct radeon_device *rdev)
- 	}
- 
- 	if (rdev->num_crtc >= 6) {
-+		if (rdev->irq.stat_regs.cik.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
-+			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
-+			       GRPH_PFLIP_INT_CLEAR);
-+		if (rdev->irq.stat_regs.cik.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
-+			WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,
-+			       GRPH_PFLIP_INT_CLEAR);
- 		if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
- 			WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
- 		if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
-@@ -7426,6 +7493,15 @@ restart_ih:
- 				break;
- 			}
- 			break;
-+		case 8: /* D1 page flip */
-+		case 9: /* D2 page flip */
-+		case 10: /* D3 page flip */
-+		case 11: /* D4 page flip */
-+		case 12: /* D5 page flip */
-+		case 13: /* D6 page flip */
-+			DRM_DEBUG("IH: D%d flip\n", src_id - 7);
-+			radeon_crtc_handle_flip(rdev, src_id - 8);
-+			break;
- 		case 42: /* HPD hotplug */
- 			switch (src_data) {
- 			case 0:
-diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
-index 98bae9d7..d1b2c71 100644
---- a/drivers/gpu/drm/radeon/cikd.h
-+++ b/drivers/gpu/drm/radeon/cikd.h
-@@ -882,6 +882,15 @@
- #       define DC_HPD6_RX_INTERRUPT                     (1 << 18)
- #define DISP_INTERRUPT_STATUS_CONTINUE6                 0x6780
- 
-+/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
-+#define GRPH_INT_STATUS                                 0x6858
-+#       define GRPH_PFLIP_INT_OCCURRED                  (1 << 0)
-+#       define GRPH_PFLIP_INT_CLEAR                     (1 << 8)
-+/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
-+#define GRPH_INT_CONTROL                                0x685c
-+#       define GRPH_PFLIP_INT_MASK                      (1 << 0)
-+#       define GRPH_PFLIP_INT_TYPE                      (1 << 8)
-+
- #define	DAC_AUTODETECT_INT_CONTROL			0x67c8
- 
- #define DC_HPD1_INT_STATUS                              0x601c
-diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
-index 27b0ff1..8ffee2b 100644
---- a/drivers/gpu/drm/radeon/evergreen.c
-+++ b/drivers/gpu/drm/radeon/evergreen.c
-@@ -4375,7 +4375,6 @@ int evergreen_irq_set(struct radeon_device *rdev)
- 	u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
- 	u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
- 	u32 grbm_int_cntl = 0;
--	u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
- 	u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
- 	u32 dma_cntl, dma_cntl1 = 0;
- 	u32 thermal_int = 0;
-@@ -4558,15 +4557,21 @@ int evergreen_irq_set(struct radeon_device *rdev)
- 		WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
- 	}
- 
--	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
--	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
-+	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
-+	       GRPH_PFLIP_INT_MASK);
-+	WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
-+	       GRPH_PFLIP_INT_MASK);
- 	if (rdev->num_crtc >= 4) {
--		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
--		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_MASK);
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_MASK);
- 	}
- 	if (rdev->num_crtc >= 6) {
--		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
--		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_MASK);
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_MASK);
- 	}
- 
- 	WREG32(DC_HPD1_INT_CONTROL, hpd1);
-@@ -4955,6 +4960,15 @@ restart_ih:
- 				break;
- 			}
- 			break;
-+		case 8: /* D1 page flip */
-+		case 9: /* D2 page flip */
-+		case 10: /* D3 page flip */
-+		case 11: /* D4 page flip */
-+		case 12: /* D5 page flip */
-+		case 13: /* D6 page flip */
-+			DRM_DEBUG("IH: D%d flip\n", src_id - 7);
-+			radeon_crtc_handle_flip(rdev, src_id - 8);
-+			break;
- 		case 42: /* HPD hotplug */
- 			switch (src_data) {
- 			case 0:
-diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
-index 647ef40..114a3ef 100644
---- a/drivers/gpu/drm/radeon/r600.c
-+++ b/drivers/gpu/drm/radeon/r600.c
-@@ -3509,7 +3509,6 @@ int r600_irq_set(struct radeon_device *rdev)
- 	u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
- 	u32 grbm_int_cntl = 0;
- 	u32 hdmi0, hdmi1;
--	u32 d1grph = 0, d2grph = 0;
- 	u32 dma_cntl;
- 	u32 thermal_int = 0;
- 
-@@ -3618,8 +3617,8 @@ int r600_irq_set(struct radeon_device *rdev)
- 	WREG32(CP_INT_CNTL, cp_int_cntl);
- 	WREG32(DMA_CNTL, dma_cntl);
- 	WREG32(DxMODE_INT_MASK, mode_int);
--	WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
--	WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
-+	WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
-+	WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
- 	WREG32(GRBM_INT_CNTL, grbm_int_cntl);
- 	if (ASIC_IS_DCE3(rdev)) {
- 		WREG32(DC_HPD1_INT_CONTROL, hpd1);
-@@ -3922,6 +3921,11 @@ restart_ih:
- 				break;
- 			}
- 			break;
-+		case 9: /* D1 pflip */
-+		case 10: /* D2 pflip */
-+			DRM_DEBUG("IH: D%d flip\n", src_id - 8);
-+			radeon_crtc_handle_flip(rdev, src_id - 9);
-+			break;
- 		case 19: /* HPD/DAC hotplug */
- 			switch (src_data) {
- 			case 0:
-diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
-index e887d02..5587de9 100644
---- a/drivers/gpu/drm/radeon/radeon.h
-+++ b/drivers/gpu/drm/radeon/radeon.h
-@@ -733,6 +733,12 @@ struct cik_irq_stat_regs {
- 	u32 disp_int_cont4;
- 	u32 disp_int_cont5;
- 	u32 disp_int_cont6;
-+	u32 d1grph_int;
-+	u32 d2grph_int;
-+	u32 d3grph_int;
-+	u32 d4grph_int;
-+	u32 d5grph_int;
-+	u32 d6grph_int;
- };
- 
- union radeon_irq_stat_regs {
-diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
-index 12a01e9..5e4326f 100644
---- a/drivers/gpu/drm/radeon/radeon_display.c
-+++ b/drivers/gpu/drm/radeon/radeon_display.c
-@@ -284,6 +284,10 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
- 	u32 update_pending;
- 	int vpos, hpos;
- 
-+	/* can happen during initialization */
-+	if (radeon_crtc == NULL)
-+		return;
-+
- 	spin_lock_irqsave(&rdev->ddev->event_lock, flags);
- 	work = radeon_crtc->unpin_work;
- 	if (work == NULL ||
-diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
-index 9a124d0..2b47e53 100644
---- a/drivers/gpu/drm/radeon/si.c
-+++ b/drivers/gpu/drm/radeon/si.c
-@@ -5777,7 +5777,6 @@ int si_irq_set(struct radeon_device *rdev)
- 	u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
- 	u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0;
- 	u32 grbm_int_cntl = 0;
--	u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
- 	u32 dma_cntl, dma_cntl1;
- 	u32 thermal_int = 0;
- 
-@@ -5916,16 +5915,22 @@ int si_irq_set(struct radeon_device *rdev)
- 	}
- 
- 	if (rdev->num_crtc >= 2) {
--		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
--		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_MASK);
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_MASK);
- 	}
- 	if (rdev->num_crtc >= 4) {
--		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
--		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_MASK);
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_MASK);
- 	}
- 	if (rdev->num_crtc >= 6) {
--		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
--		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_MASK);
-+		WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,
-+		       GRPH_PFLIP_INT_MASK);
- 	}
- 
- 	if (!ASIC_IS_NODCE(rdev)) {
-@@ -6289,6 +6294,15 @@ restart_ih:
- 				break;
- 			}
- 			break;
-+		case 8: /* D1 page flip */
-+		case 9: /* D2 page flip */
-+		case 10: /* D3 page flip */
-+		case 11: /* D4 page flip */
-+		case 12: /* D5 page flip */
-+		case 13: /* D6 page flip */
-+			DRM_DEBUG("IH: D%d flip\n", src_id - 7);
-+			radeon_crtc_handle_flip(rdev, src_id - 8);
-+			break;
- 		case 42: /* HPD hotplug */
- 			switch (src_data) {
- 			case 0:
--- 
-1.9.1
-
-