From 3342d0a6c795a6a2702525038452e9ee73beabbf Mon Sep 17 00:00:00 2001 From: mglae Date: Tue, 6 Sep 2016 19:07:03 +0200 Subject: [PATCH] update ddbridge drivers in kernel 4.7.2 --- ...todo => linux-221-ddbridge-features.patch} | 26094 ++++++---------- projects/Generic/linux/linux.x86_64.conf | 1 + projects/Virtual/linux/linux.x86_64.conf | 1 + 3 files changed, 10247 insertions(+), 15849 deletions(-) rename packages/linux/patches/4.7.2/{linux-221-ngene-octopus.todo => linux-221-ddbridge-features.patch} (57%) diff --git a/packages/linux/patches/4.7.2/linux-221-ngene-octopus.todo b/packages/linux/patches/4.7.2/linux-221-ddbridge-features.patch similarity index 57% rename from packages/linux/patches/4.7.2/linux-221-ngene-octopus.todo rename to packages/linux/patches/4.7.2/linux-221-ddbridge-features.patch index 91fdbc9d67..958d680c78 100644 --- a/packages/linux/patches/4.7.2/linux-221-ngene-octopus.todo +++ b/packages/linux/patches/4.7.2/linux-221-ddbridge-features.patch @@ -1,89 +1,50 @@ -From 4e0cb03f8d73ecda1283c6690f30b2944f169455 Mon Sep 17 00:00:00 2001 -From: Stefan Saraev -Date: Thu, 11 Jun 2015 10:45:56 +0300 -Subject: [PATCH] dvb: ngene/octopus - -source: http://linuxtv.org/hg/~endriss/media_build_experimental/ - -note: SYS_DVBC2 not added. ci extensions (en50221) not added. ---- - drivers/media/dvb-core/Makefile | 2 +- - drivers/media/dvb-core/dvb_netstream.c | 259 ++ - drivers/media/dvb-core/dvb_netstream.h | 94 + - drivers/media/dvb-core/dvbdev.c | 11 +- - drivers/media/dvb-core/dvbdev.h | 4 + - drivers/media/dvb-frontends/Kconfig | 27 + - drivers/media/dvb-frontends/Makefile | 3 + - drivers/media/dvb-frontends/cxd2843.c | 2022 ++++++++++++ - drivers/media/dvb-frontends/cxd2843.h | 30 + - drivers/media/dvb-frontends/drxk_hard.c | 3614 +++++++++----------- - drivers/media/dvb-frontends/drxk_hard.h | 298 +- - drivers/media/dvb-frontends/drxk_map.h | 3 - - drivers/media/dvb-frontends/lnbh25.c | 153 + - drivers/media/dvb-frontends/lnbh25.h | 28 + - drivers/media/dvb-frontends/stv0367dd.c | 2331 +++++++++++++ - drivers/media/dvb-frontends/stv0367dd.h | 17 + - drivers/media/dvb-frontends/stv0367dd_regs.h | 3431 +++++++++++++++++++ - drivers/media/dvb-frontends/stv090x.c | 45 +- - drivers/media/dvb-frontends/stv0910.c | 1371 ++++++++ - drivers/media/dvb-frontends/stv0910.h | 31 + - drivers/media/dvb-frontends/stv0910_regs.h | 3998 +++++++++++++++++++++++ - drivers/media/dvb-frontends/stv6111.c | 450 +++ - drivers/media/dvb-frontends/stv6111.h | 5 + - drivers/media/dvb-frontends/tda18212dd.c | 974 ++++++ - drivers/media/dvb-frontends/tda18212dd.h | 5 + - drivers/media/dvb-frontends/tda18271c2dd.c | 17 +- - drivers/media/dvb-frontends/tda18271c2dd.h | 6 +- - drivers/media/dvb-frontends/tda18271c2dd_maps.h | 8 +- - drivers/media/pci/ddbridge/Kconfig | 11 +- - drivers/media/pci/ddbridge/Makefile | 2 - - drivers/media/pci/ddbridge/ddbridge-core.c | 3941 ++++++++++++++++------ - drivers/media/pci/ddbridge/ddbridge-i2c.c | 257 ++ - drivers/media/pci/ddbridge/ddbridge-i2c.h | 105 + - drivers/media/pci/ddbridge/ddbridge-mod.c | 1148 +++++++ - drivers/media/pci/ddbridge/ddbridge-ns.c | 489 +++ - drivers/media/pci/ddbridge/ddbridge-regs.h | 347 +- - drivers/media/pci/ddbridge/ddbridge.c | 470 +++ - drivers/media/pci/ddbridge/ddbridge.h | 419 ++- - drivers/media/pci/ddbridge/octonet.c | 199 ++ - drivers/media/pci/ngene/Kconfig | 4 + - drivers/media/pci/ngene/Makefile | 3 +- - drivers/media/pci/ngene/ngene-av.c | 348 ++ - drivers/media/pci/ngene/ngene-cards.c | 975 ++++-- - drivers/media/pci/ngene/ngene-core.c | 410 ++- - drivers/media/pci/ngene/ngene-dvb.c | 379 ++- - drivers/media/pci/ngene/ngene-eeprom.c | 284 ++ - drivers/media/pci/ngene/ngene-i2c.c | 113 + - drivers/media/pci/ngene/ngene.h | 42 +- - include/uapi/linux/dvb/mod.h | 22 + - include/uapi/linux/dvb/ns.h | 68 + - 50 files changed, 25733 insertions(+), 3540 deletions(-) - create mode 100644 drivers/media/dvb-core/dvb_netstream.c - create mode 100644 drivers/media/dvb-core/dvb_netstream.h - create mode 100644 drivers/media/dvb-frontends/cxd2843.c - create mode 100644 drivers/media/dvb-frontends/cxd2843.h - create mode 100644 drivers/media/dvb-frontends/lnbh25.c - create mode 100644 drivers/media/dvb-frontends/lnbh25.h - create mode 100644 drivers/media/dvb-frontends/stv0367dd.c - create mode 100644 drivers/media/dvb-frontends/stv0367dd.h - create mode 100644 drivers/media/dvb-frontends/stv0367dd_regs.h - create mode 100644 drivers/media/dvb-frontends/stv0910.c - create mode 100644 drivers/media/dvb-frontends/stv0910.h - create mode 100644 drivers/media/dvb-frontends/stv0910_regs.h - create mode 100644 drivers/media/dvb-frontends/stv6111.c - create mode 100644 drivers/media/dvb-frontends/stv6111.h - create mode 100644 drivers/media/dvb-frontends/tda18212dd.c - create mode 100644 drivers/media/dvb-frontends/tda18212dd.h - create mode 100644 drivers/media/pci/ddbridge/ddbridge-i2c.c - create mode 100644 drivers/media/pci/ddbridge/ddbridge-i2c.h - create mode 100644 drivers/media/pci/ddbridge/ddbridge-mod.c - create mode 100644 drivers/media/pci/ddbridge/ddbridge-ns.c - create mode 100644 drivers/media/pci/ddbridge/ddbridge.c - create mode 100644 drivers/media/pci/ddbridge/octonet.c - create mode 100644 drivers/media/pci/ngene/ngene-av.c - create mode 100644 drivers/media/pci/ngene/ngene-eeprom.c - create mode 100644 include/uapi/linux/dvb/mod.h - create mode 100644 include/uapi/linux/dvb/ns.h + drivers/media/dvb-core/Makefile | 2 +- + drivers/media/dvb-core/dvb_ca_en50221.c | 128 +- + drivers/media/dvb-core/dvb_ca_en50221.h | 7 + + drivers/media/dvb-core/dvb_frontend.c | 15 + + drivers/media/dvb-core/dvb_frontend.h | 4 + + drivers/media/dvb-core/dvb_netstream.c | 259 + + drivers/media/dvb-core/dvb_netstream.h | 93 + + drivers/media/dvb-core/dvbdev.c | 3 +- + drivers/media/dvb-core/dvbdev.h | 4 + + drivers/media/dvb-frontends/Kconfig | 41 + + drivers/media/dvb-frontends/Makefile | 5 + + drivers/media/dvb-frontends/cxd2843.c | 2063 ++++++++ + drivers/media/dvb-frontends/cxd2843.h | 30 + + drivers/media/dvb-frontends/mxl5xx.c | 1738 +++++++ + drivers/media/dvb-frontends/mxl5xx.h | 39 + + drivers/media/dvb-frontends/mxl5xx_defs.h | 818 ++++ + drivers/media/dvb-frontends/mxl5xx_regs.h | 941 ++++ + drivers/media/dvb-frontends/stv0367dd.c | 1874 +++++++ + drivers/media/dvb-frontends/stv0367dd.h | 31 + + drivers/media/dvb-frontends/stv0367dd_regs.h | 3429 +++++++++++++ + drivers/media/dvb-frontends/stv0910.c | 1526 ++++++ + drivers/media/dvb-frontends/stv0910.h | 31 + + drivers/media/dvb-frontends/stv0910_regs.h | 3997 +++++++++++++++ + drivers/media/dvb-frontends/stv6111.c | 684 +++ + drivers/media/dvb-frontends/stv6111.h | 20 + + drivers/media/pci/ddbridge/Kconfig | 29 +- + drivers/media/pci/ddbridge/Makefile | 4 +- + drivers/media/pci/ddbridge/ddbridge-core.c | 5105 +++++++++++++++----- + drivers/media/pci/ddbridge/ddbridge-i2c.c | 290 ++ + drivers/media/pci/ddbridge/ddbridge-i2c.h | 116 + + drivers/media/pci/ddbridge/ddbridge-mod.c | 1118 +++++ + drivers/media/pci/ddbridge/ddbridge-ns.c | 491 ++ + drivers/media/pci/ddbridge/ddbridge-regs.h | 355 +- + drivers/media/pci/ddbridge/ddbridge.c | 541 +++ + drivers/media/pci/ddbridge/ddbridge.h | 579 ++- + drivers/media/pci/ddbridge/octonet.c | 262 + + .../media/platform/sti/c8sectpfe/c8sectpfe-dvb.c | 1 + + drivers/media/tuners/tda18212.c | 5 + + drivers/media/tuners/tda18212.h | 7 + + drivers/media/usb/dvb-usb-v2/anysee.c | 2 + + drivers/media/usb/em28xx/em28xx-dvb.c | 1 + + drivers/staging/media/cxd2099/cxd2099.c | 234 +- + drivers/staging/media/cxd2099/cxd2099.h | 6 +- + include/uapi/linux/dvb/frontend.h | 7 +- + include/uapi/linux/dvb/mod.h | 22 + + include/uapi/linux/dvb/ns.h | 69 + + 46 files changed, 25615 insertions(+), 1411 deletions(-) diff --git a/drivers/media/dvb-core/Makefile b/drivers/media/dvb-core/Makefile index 8f22bcd..5ff851a 100644 @@ -97,17 +58,295 @@ index 8f22bcd..5ff851a 100644 + $(dvb-net-y) dvb_ringbuffer.o dvb_math.o dvb_netstream.o obj-$(CONFIG_DVB_CORE) += dvb-core.o +diff --git a/drivers/media/dvb-core/dvb_ca_en50221.c b/drivers/media/dvb-core/dvb_ca_en50221.c +index f82cd1f..4849156 100644 +--- a/drivers/media/dvb-core/dvb_ca_en50221.c ++++ b/drivers/media/dvb-core/dvb_ca_en50221.c +@@ -315,7 +315,7 @@ static int dvb_ca_en50221_link_init(struct dvb_ca_private *ca, int slot) + /* read the buffer size from the CAM */ + if ((ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN | CMDREG_SR)) != 0) + return ret; +- if ((ret = dvb_ca_en50221_wait_if_status(ca, slot, STATUSREG_DA, HZ / 10)) != 0) ++ if ((ret = dvb_ca_en50221_wait_if_status(ca, slot, STATUSREG_DA, HZ)) != 0) + return ret; + if ((ret = dvb_ca_en50221_read_data(ca, slot, buf, 2)) != 2) + return -EIO; +@@ -612,65 +612,78 @@ static int dvb_ca_en50221_read_data(struct dvb_ca_private *ca, int slot, u8 * eb + } + } + +- /* check if there is data available */ +- if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0) +- goto exit; +- if (!(status & STATUSREG_DA)) { +- /* no data */ +- status = 0; +- goto exit; +- } +- +- /* read the amount of data */ +- if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_SIZE_HIGH)) < 0) +- goto exit; +- bytes_read = status << 8; +- if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_SIZE_LOW)) < 0) +- goto exit; +- bytes_read |= status; ++ if (ca->pub->read_data && (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_LINKINIT)) { ++ if (ebuf == NULL) ++ status = ca->pub->read_data(ca->pub, slot, buf, sizeof(buf)); ++ else ++ status = ca->pub->read_data(ca->pub, slot, buf, ecount); ++ if (status < 0) ++ return status; ++ bytes_read = status; ++ if (status == 0) ++ goto exit; ++ } else { + +- /* check it will fit */ +- if (ebuf == NULL) { +- if (bytes_read > ca->slot_info[slot].link_buf_size) { +- printk("dvb_ca adapter %d: CAM tried to send a buffer larger than the link buffer size (%i > %i)!\n", +- ca->dvbdev->adapter->num, bytes_read, ca->slot_info[slot].link_buf_size); +- ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; +- status = -EIO; ++ /* check if there is data available */ ++ if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0) + goto exit; +- } +- if (bytes_read < 2) { +- printk("dvb_ca adapter %d: CAM sent a buffer that was less than 2 bytes!\n", +- ca->dvbdev->adapter->num); +- ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; +- status = -EIO; ++ if (!(status & STATUSREG_DA)) { ++ /* no data */ ++ status = 0; + goto exit; + } +- } else { +- if (bytes_read > ecount) { +- printk("dvb_ca adapter %d: CAM tried to send a buffer larger than the ecount size!\n", +- ca->dvbdev->adapter->num); +- status = -EIO; ++ ++ /* read the amount of data */ ++ if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_SIZE_HIGH)) < 0) ++ goto exit; ++ bytes_read = status << 8; ++ if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_SIZE_LOW)) < 0) + goto exit; ++ bytes_read |= status; ++ ++ /* check it will fit */ ++ if (ebuf == NULL) { ++ if (bytes_read > ca->slot_info[slot].link_buf_size) { ++ printk("dvb_ca adapter %d: CAM tried to send a buffer larger than the link buffer size (%i > %i)!\n", ++ ca->dvbdev->adapter->num, bytes_read, ca->slot_info[slot].link_buf_size); ++ ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; ++ status = -EIO; ++ goto exit; ++ } ++ if (bytes_read < 2) { ++ printk("dvb_ca adapter %d: CAM sent a buffer that was less than 2 bytes!\n", ++ ca->dvbdev->adapter->num); ++ ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; ++ status = -EIO; ++ goto exit; ++ } ++ } else { ++ if (bytes_read > ecount) { ++ printk("dvb_ca adapter %d: CAM tried to send a buffer larger than the ecount size!\n", ++ ca->dvbdev->adapter->num); ++ status = -EIO; ++ goto exit; ++ } + } +- } + +- /* fill the buffer */ +- for (i = 0; i < bytes_read; i++) { +- /* read byte and check */ +- if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_DATA)) < 0) +- goto exit; ++ /* fill the buffer */ ++ for (i = 0; i < bytes_read; i++) { ++ /* read byte and check */ ++ if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_DATA)) < 0) ++ goto exit; + +- /* OK, store it in the buffer */ +- buf[i] = status; +- } ++ /* OK, store it in the buffer */ ++ buf[i] = status; ++ } + +- /* check for read error (RE should now be 0) */ +- if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0) +- goto exit; +- if (status & STATUSREG_RE) { +- ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; +- status = -EIO; +- goto exit; ++ /* check for read error (RE should now be 0) */ ++ if ((status = ca->pub->read_cam_control(ca->pub, slot, CTRLIF_STATUS)) < 0) ++ goto exit; ++ if (status & STATUSREG_RE) { ++ ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; ++ status = -EIO; ++ goto exit; ++ } + } + + /* OK, add it to the receive buffer, or copy into external buffer if supplied */ +@@ -722,6 +735,9 @@ static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, u8 * b + if (bytes_write > ca->slot_info[slot].link_buf_size) + return -EINVAL; + ++ if (ca->pub->write_data && (ca->slot_info[slot].slot_state != DVB_CA_SLOTSTATE_LINKINIT)) ++ return ca->pub->write_data(ca->pub, slot, buf, bytes_write); ++ + /* it is possible we are dealing with a single buffer implementation, + thus if there is data available for read or if there is even a read + already in progress, we do nothing but awake the kernel thread to +@@ -1057,7 +1073,8 @@ static int dvb_ca_en50221_thread(void *data) + + printk("dvb_ca adapter %d: Invalid PC card inserted :(\n", + ca->dvbdev->adapter->num); +- ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; ++ printk("dvb_ca adapter %d: Trying to read attribute memory again (some CAMs are slow)\n", ++ ca->dvbdev->adapter->num); + dvb_ca_en50221_thread_update_delay(ca); + break; + } +@@ -1087,7 +1104,10 @@ static int dvb_ca_en50221_thread(void *data) + if (time_after(jiffies, ca->slot_info[slot].timeout)) { + printk("dvb_ca adapter %d: DVB CAM did not respond :(\n", + ca->dvbdev->adapter->num); +- ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; ++ printk("dvb_ca adapter %d: Ignoring missing FR (some CAMs are broken)\n", ++ ca->dvbdev->adapter->num); ++ ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_LINKINIT; ++ ca->wakeup = 1; + dvb_ca_en50221_thread_update_delay(ca); + break; + } +@@ -1113,7 +1133,7 @@ static int dvb_ca_en50221_thread(void *data) + } + + printk("dvb_ca adapter %d: DVB CAM link initialisation failed :(\n", ca->dvbdev->adapter->num); +- ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_INVALID; ++ ca->slot_info[slot].slot_state = DVB_CA_SLOTSTATE_UNINITIALISED; + dvb_ca_en50221_thread_update_delay(ca); + break; + } +diff --git a/drivers/media/dvb-core/dvb_ca_en50221.h b/drivers/media/dvb-core/dvb_ca_en50221.h +index 1e4bbbd..056d10c 100644 +--- a/drivers/media/dvb-core/dvb_ca_en50221.h ++++ b/drivers/media/dvb-core/dvb_ca_en50221.h +@@ -41,6 +41,8 @@ + * @write_attribute_mem: function for writing attribute memory on the CAM + * @read_cam_control: function for reading the control interface on the CAM + * @write_cam_control: function for reading the control interface on the CAM ++ * @read_data: function for reading data ++ * @write_data: function for writing data + * @slot_reset: function to reset the CAM slot + * @slot_shutdown: function to shutdown a CAM slot + * @slot_ts_enable: function to enable the Transport Stream on a CAM slot +@@ -66,6 +68,11 @@ struct dvb_ca_en50221 { + int (*write_cam_control)(struct dvb_ca_en50221 *ca, + int slot, u8 address, u8 value); + ++ int (*read_data)(struct dvb_ca_en50221* ca, ++ int slot, u8 *ebuf, int ecount); ++ int (*write_data)(struct dvb_ca_en50221* ca, ++ int slot, u8 *ebuf, int ecount); ++ + int (*slot_reset)(struct dvb_ca_en50221 *ca, int slot); + int (*slot_shutdown)(struct dvb_ca_en50221 *ca, int slot); + int (*slot_ts_enable)(struct dvb_ca_en50221 *ca, int slot); +diff --git a/drivers/media/dvb-core/dvb_frontend.c b/drivers/media/dvb-core/dvb_frontend.c +index c014261..6047f4f 100644 +--- a/drivers/media/dvb-core/dvb_frontend.c ++++ b/drivers/media/dvb-core/dvb_frontend.c +@@ -1019,6 +1019,7 @@ static struct dtv_cmds_h dtv_cmds[DTV_MAX_COMMAND + 1] = { + _DTV_CMD(DTV_STREAM_ID, 1, 0), + _DTV_CMD(DTV_DVBT2_PLP_ID_LEGACY, 1, 0), + _DTV_CMD(DTV_LNA, 1, 0), ++ _DTV_CMD(DTV_INPUT, 1, 0), + + /* Get */ + _DTV_CMD(DTV_DISEQC_SLAVE_REPLY, 0, 1), +@@ -1449,6 +1450,14 @@ static int dtv_property_process_get(struct dvb_frontend *fe, + tvp->u.data = c->lna; + break; + ++ case DTV_INPUT: ++ tvp->u.buffer.data[0] = c->input; ++ tvp->u.buffer.data[1] = fe->ops.xbar[0]; ++ tvp->u.buffer.data[2] = fe->ops.xbar[1]; ++ tvp->u.buffer.data[3] = fe->ops.xbar[2]; ++ tvp->u.buffer.len = 4; ++ break; ++ + /* Fill quality measures */ + case DTV_STAT_SIGNAL_STRENGTH: + tvp->u.st = c->strength; +@@ -1884,6 +1893,12 @@ static int dtv_property_process_set(struct dvb_frontend *fe, + c->lna = LNA_AUTO; + break; + ++ case DTV_INPUT: ++ c->input = tvp->u.data; ++ if (fe->ops.set_input) ++ r = fe->ops.set_input(fe, c->input); ++ break; ++ + default: + return -EINVAL; + } +diff --git a/drivers/media/dvb-core/dvb_frontend.h b/drivers/media/dvb-core/dvb_frontend.h +index 9592573..c93aff5 100644 +--- a/drivers/media/dvb-core/dvb_frontend.h ++++ b/drivers/media/dvb-core/dvb_frontend.h +@@ -471,6 +471,7 @@ struct dvb_frontend_ops { + int (*i2c_gate_ctrl)(struct dvb_frontend* fe, int enable); + int (*ts_bus_ctrl)(struct dvb_frontend* fe, int acquire); + int (*set_lna)(struct dvb_frontend *); ++ int (*set_input)(struct dvb_frontend *, int); + + /* + * These callbacks are for devices that implement their own +@@ -483,6 +484,8 @@ struct dvb_frontend_ops { + + int (*set_property)(struct dvb_frontend* fe, struct dtv_property* tvp); + int (*get_property)(struct dvb_frontend* fe, struct dtv_property* tvp); ++ ++ u8 xbar[3]; + }; + + #ifdef __DVB_CORE__ +@@ -632,6 +635,7 @@ struct dtv_frontend_properties { + u8 atscmh_sccc_code_mode_d; + + u32 lna; ++ s32 input; + + /* statistics data */ + struct dtv_fe_stats strength; diff --git a/drivers/media/dvb-core/dvb_netstream.c b/drivers/media/dvb-core/dvb_netstream.c new file mode 100644 -index 0000000..43322c7 +index 0000000..0d80780 --- /dev/null +++ b/drivers/media/dvb-core/dvb_netstream.c @@ -0,0 +1,259 @@ +/* + * dvb_netstream.c: support for DVB to network streaming hardware + * -+ * Copyright (C) 2012-2013 Digital Devices GmbH -+ * Ralph Metzler ++ * Copyright (C) 2012-2013 Marcus and Ralph Metzler ++ * for Digital Devices GmbH ++ * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License @@ -133,20 +372,20 @@ index 0000000..43322c7 +static ssize_t ns_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) +{ -+ printk("%s\n", __func__); ++ pr_info("%s\n", __func__); + return 0; +} + +static ssize_t ns_read(struct file *file, char *buf, + size_t count, loff_t *ppos) +{ -+ printk("%s\n", __func__); ++ pr_info("%s\n", __func__); + return 0; +} + +static unsigned int ns_poll(struct file *file, poll_table *wait) +{ -+ printk("%s\n", __func__); ++ pr_info("%s\n", __func__); + return 0; +} + @@ -185,7 +424,7 @@ index 0000000..43322c7 + struct dvbnss *nss; + + nss = vmalloc(sizeof(*nss)); -+ if (!nss) ++ if (!nss) + return -ENOMEM; + nss->ns = ns; + if (ns->alloc && ns->alloc(nss) < 0) { @@ -209,7 +448,7 @@ index 0000000..43322c7 +{ + struct dvbnss *nss = file->private_data; + struct dvb_netstream *ns = nss->ns; -+ //unsigned long arg = (unsigned long) parg; ++ /*unsigned long arg = (unsigned long) parg;*/ + int ret = 0; + + switch (cmd) { @@ -217,18 +456,16 @@ index 0000000..43322c7 + { + struct dvb_ns_rtcp *rtcpm = parg; + -+ if (ns->set_rtcp_msg) { -+ //printk("%s calling NS_SET_RTCP_MSG\n", __func__); ++ if (ns->set_rtcp_msg) + ret = ns->set_rtcp_msg(nss, rtcpm->msg, rtcpm->len); -+ } + break; + } + + case NS_SET_NET: + memcpy(&nss->params, parg, sizeof(nss->params)); -+ if (ns->set_net) { ++ if (ns->set_net) + ret = ns->set_net(nss); -+ } else ++ else + ret = set_net(nss, (struct dvb_ns_params *) parg); + break; + @@ -250,15 +487,17 @@ index 0000000..43322c7 + case NS_SET_PACKETS: + { + struct dvb_ns_packet *packet = parg; -+ if (ns->set_ts_packets) { -+ ret = ns->set_ts_packets(nss, packet->buf, packet->count * 188); -+ } ++ ++ if (ns->set_ts_packets) ++ ret = ns->set_ts_packets(nss, packet->buf, ++ packet->count * 188); + break; + } + + case NS_INSERT_PACKETS: + { + u8 count = *(u8 *) parg; ++ + if (ns->insert_ts_packets) + ret = ns->insert_ts_packets(nss, count); + break; @@ -269,14 +508,14 @@ index 0000000..43322c7 + u16 pid = *(u16 *) parg; + u16 byte = (pid & 0x1fff) >> 3; + u8 bit = 1 << (pid & 7); -+ ++ + if (pid & 0x2000) { -+ if (pid & 0x8000) ++ if (pid & 0x8000) + memset(nss->pids, 0xff, 0x400); + else + memset(nss->pids, 0x00, 0x400); + } else { -+ if (pid & 0x8000) ++ if (pid & 0x8000) + nss->pids[byte] |= bit; + else + nss->pids[byte] &= ~bit; @@ -298,7 +537,7 @@ index 0000000..43322c7 + { + u8 ci = *(u8 *) parg; + -+ if (nss->running) ++ if (nss->running) + ret = -EBUSY; + else if (ns->set_ci) + ret = ns->set_ci(nss, ci); @@ -338,41 +577,40 @@ index 0000000..43322c7 +}; + + -+int dvb_netstream_init(struct dvb_adapter *dvb_adapter, struct dvb_netstream *ns) ++int dvb_netstream_init(struct dvb_adapter *dvb_adapter, ++ struct dvb_netstream *ns) +{ + mutex_init(&ns->mutex); + spin_lock_init(&ns->lock); + ns->exit = 0; + dvb_register_device(dvb_adapter, &ns->dvbdev, &ns_dev, ns, -+ DVB_DEVICE_NS); ++ DVB_DEVICE_NS, 0); + INIT_LIST_HEAD(&ns->nssl); + return 0; +} -+ +EXPORT_SYMBOL(dvb_netstream_init); + +void dvb_netstream_release(struct dvb_netstream *ns) +{ -+ ns->exit=1; ++ ns->exit = 1; + if (ns->dvbdev->users > 1) { + wait_event(ns->dvbdev->wait_queue, + ns->dvbdev->users == 1); + } + dvb_unregister_device(ns->dvbdev); +} -+ +EXPORT_SYMBOL(dvb_netstream_release); diff --git a/drivers/media/dvb-core/dvb_netstream.h b/drivers/media/dvb-core/dvb_netstream.h new file mode 100644 -index 0000000..df73ed5 +index 0000000..a40f1f1 --- /dev/null +++ b/drivers/media/dvb-core/dvb_netstream.h -@@ -0,0 +1,94 @@ +@@ -0,0 +1,93 @@ +/* + * dvb_netstream.c: support for DVB to network streaming hardware + * -+ * Copyright (C) 2012-2013 Digital Devices GmbH -+ * Ralph Metzler ++ * Copyright (C) 2012-2013 Marcus and Ralph Metzler ++ * for Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License @@ -413,17 +651,17 @@ index 0000000..df73ed5 +#define DVBNS_MAXPIDS 32 + +struct dvbnss { -+ struct dvb_netstream *ns; ++ struct dvb_netstream *ns; + void *priv; + + u8 pids[1024]; + u8 packet[1328]; + u32 pp; -+ ++ + struct socket *sock; + struct sockaddr_in sadr; + u32 sn; -+ ++ + struct dvb_ns_params params; + + struct list_head nssl; @@ -434,7 +672,7 @@ index 0000000..df73ed5 + +struct dvb_netstream { + void *priv; -+ ++ + struct mutex mutex; + spinlock_t lock; + struct dvb_device *dvbdev; @@ -442,18 +680,17 @@ index 0000000..df73ed5 + + struct list_head nssl; + -+ int (*set_net) (struct dvbnss *); -+ int (*set_pid) (struct dvbnss *, u16); -+ int (*set_pids) (struct dvbnss *); -+ int (*set_ci) (struct dvbnss *, u8); -+ int (*set_rtcp_msg) (struct dvbnss *, u8 *, u32); -+ int (*set_ts_packets) (struct dvbnss *, u8 *, u32); -+ int (*insert_ts_packets) (struct dvbnss *, u8); -+ int (*start) (struct dvbnss *); -+ int (*stop) (struct dvbnss *); -+ int (*alloc) (struct dvbnss *); -+ void (*free) (struct dvbnss *); -+ ++ int (*set_net)(struct dvbnss *); ++ int (*set_pid)(struct dvbnss *, u16); ++ int (*set_pids)(struct dvbnss *); ++ int (*set_ci)(struct dvbnss *, u8); ++ int (*set_rtcp_msg)(struct dvbnss *, u8 *, u32); ++ int (*set_ts_packets)(struct dvbnss *, u8 *, u32); ++ int (*insert_ts_packets)(struct dvbnss *, u8); ++ int (*start)(struct dvbnss *); ++ int (*stop)(struct dvbnss *); ++ int (*alloc)(struct dvbnss *); ++ void (*free)(struct dvbnss *); +}; + + @@ -463,10 +700,10 @@ index 0000000..df73ed5 + +#endif diff --git a/drivers/media/dvb-core/dvbdev.c b/drivers/media/dvb-core/dvbdev.c -index 13bb57f..ef320af 100644 +index 75a3f4b..3f309b4 100644 --- a/drivers/media/dvb-core/dvbdev.c +++ b/drivers/media/dvb-core/dvbdev.c -@@ -47,7 +47,7 @@ static DEFINE_MUTEX(dvbdev_register_lock); +@@ -50,7 +50,7 @@ static DEFINE_MUTEX(dvbdev_register_lock); static const char * const dnames[] = { "video", "audio", "sec", "frontend", "demux", "dvr", "ca", @@ -475,42 +712,7 @@ index 13bb57f..ef320af 100644 }; #ifdef CONFIG_DVB_DYNAMIC_MINORS -@@ -68,7 +68,7 @@ static int dvb_device_open(struct inode *inode, struct file *file) - { - struct dvb_device *dvbdev; - -- mutex_lock(&dvbdev_mutex); -+ //mutex_lock(&dvbdev_mutex); - down_read(&minor_rwsem); - dvbdev = dvb_minors[iminor(inode)]; - -@@ -84,12 +84,12 @@ static int dvb_device_open(struct inode *inode, struct file *file) - if (file->f_op->open) - err = file->f_op->open(inode,file); - up_read(&minor_rwsem); -- mutex_unlock(&dvbdev_mutex); -+ //mutex_unlock(&dvbdev_mutex); - return err; - } - fail: - up_read(&minor_rwsem); -- mutex_unlock(&dvbdev_mutex); -+ //mutex_unlock(&dvbdev_mutex); - return -ENODEV; - } - -@@ -553,8 +553,10 @@ int dvb_usercopy(struct file *file, - } - - /* call driver */ -+ //mutex_lock(&dvbdev_mutex); - if ((err = func(file, cmd, parg)) == -ENOIOCTLCMD) - err = -ENOTTY; -+ //mutex_unlock(&dvbdev_mutex); - - if (err < 0) - goto out; -@@ -573,6 +575,7 @@ out: +@@ -900,6 +900,7 @@ out: kfree(mbuf); return err; } @@ -519,7 +721,7 @@ index 13bb57f..ef320af 100644 static int dvb_uevent(struct device *dev, struct kobj_uevent_env *env) { diff --git a/drivers/media/dvb-core/dvbdev.h b/drivers/media/dvb-core/dvbdev.h -index 12629b8..e918a09 100644 +index 4aff7bd..ae4f4d1 100644 --- a/drivers/media/dvb-core/dvbdev.h +++ b/drivers/media/dvb-core/dvbdev.h @@ -48,6 +48,10 @@ @@ -534,11 +736,48 @@ index 12629b8..e918a09 100644 #define DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr) \ static short adapter_nr[] = \ diff --git a/drivers/media/dvb-frontends/Kconfig b/drivers/media/dvb-frontends/Kconfig -index 97c151d..2bf9390 100644 +index a82f77c..3692927 100644 --- a/drivers/media/dvb-frontends/Kconfig +++ b/drivers/media/dvb-frontends/Kconfig -@@ -72,6 +72,33 @@ config DVB_SI2165 +@@ -28,6 +28,14 @@ config DVB_STV090x + DVB-S/S2/DSS Multistandard Professional/Broadcast demodulators. + Say Y when you want to support these frontends. ++config DVB_STV0910 ++ tristate "STV0910 based" ++ depends on DVB_CORE && I2C ++ default m if !MEDIA_SUBDRV_AUTOSELECT ++ help ++ ST STV0910 DVB-S/S2 demodulator. ++ Say Y when you want to support these frontends. ++ + config DVB_STV6110x + tristate "STV6110/(A) based tuners" + depends on DVB_CORE && I2C +@@ -35,6 +43,21 @@ config DVB_STV6110x + help + A Silicon tuner that supports DVB-S and DVB-S2 modes + ++config DVB_STV6111 ++ tristate "STV6111 based tuners" ++ depends on DVB_CORE && I2C ++ default m if !MEDIA_SUBDRV_AUTOSELECT ++ help ++ A Silicon tuner that supports DVB-S and DVB-S2 modes ++ ++config DVB_MXL5XX ++ tristate "Maxlinear MX58x based" ++ depends on DVB_CORE && I2C ++ default m if !MEDIA_SUBDRV_AUTOSELECT ++ help ++ Maxlinear MX58x family of tuners/demods. ++ Say Y when you want to support these frontends. ++ + config DVB_M88DS3103 + tristate "Montage Technology M88DS3103" + depends on DVB_CORE && I2C && I2C_MUX +@@ -81,6 +104,24 @@ config DVB_MN88473 + help Say Y when you want to support this frontend. +config DVB_STV0367DD @@ -550,15 +789,6 @@ index 97c151d..2bf9390 100644 + + Say Y when you want to support this frontend. + -+config DVB_TDA18212DD -+ tristate "NXP TDA18212 silicon tuner (DD)" -+ depends on DVB_CORE && I2C -+ default m if !MEDIA_SUBDRV_AUTOSELECT -+ help -+ NXP TDA18212 silicon tuner (Digital Devices driver). -+ -+ Say Y when you want to support this tuner. -+ +config DVB_CXD2843 + tristate "Sony CXD2843 DVB-C/T demodulator family" + depends on DVB_CORE && I2C @@ -572,31 +802,33 @@ index 97c151d..2bf9390 100644 depends on DVB_CORE diff --git a/drivers/media/dvb-frontends/Makefile b/drivers/media/dvb-frontends/Makefile -index 23d399b..db9b87a 100644 +index eb7191f..1749be8 100644 --- a/drivers/media/dvb-frontends/Makefile +++ b/drivers/media/dvb-frontends/Makefile -@@ -106,6 +106,9 @@ obj-$(CONFIG_DVB_STV0367) += stv0367.o - obj-$(CONFIG_DVB_CXD2820R) += cxd2820r.o +@@ -110,6 +110,11 @@ obj-$(CONFIG_DVB_CXD2820R) += cxd2820r.o + obj-$(CONFIG_DVB_CXD2841ER) += cxd2841er.o obj-$(CONFIG_DVB_DRXK) += drxk.o obj-$(CONFIG_DVB_TDA18271C2DD) += tda18271c2dd.o +obj-$(CONFIG_DVB_STV0367DD) += stv0367dd.o -+obj-$(CONFIG_DVB_TDA18212DD) += tda18212dd.o +obj-$(CONFIG_DVB_CXD2843) += cxd2843.o ++obj-$(CONFIG_DVB_STV0910) += stv0910.o ++obj-$(CONFIG_DVB_STV6111) += stv6111.o ++obj-$(CONFIG_DVB_MXL5XX) += mxl5xx.o obj-$(CONFIG_DVB_SI2165) += si2165.o obj-$(CONFIG_DVB_A8293) += a8293.o obj-$(CONFIG_DVB_SP2) += sp2.o diff --git a/drivers/media/dvb-frontends/cxd2843.c b/drivers/media/dvb-frontends/cxd2843.c new file mode 100644 -index 0000000..27e5eac +index 0000000..959e4ab --- /dev/null +++ b/drivers/media/dvb-frontends/cxd2843.c -@@ -0,0 +1,2022 @@ +@@ -0,0 +1,2063 @@ +/* + * Driver for the Sony CXD2843ER DVB-T/T2/C/C2 demodulator. + * Also supports the CXD2837ER DVB-T/T2/C and the + * CXD2838ER ISDB-T demodulator. + * -+ * Copyright (C) 2013-2014 Digital Devices GmbH ++ * Copyright (C) 2013-2015 Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License @@ -616,6 +848,9 @@ index 0000000..27e5eac + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + ++#undef pr_fmt ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ +#include +#include +#include @@ -623,21 +858,27 @@ index 0000000..27e5eac +#include +#include +#include -+#include +#include +#include + +#include "dvb_frontend.h" ++#include "dvb_math.h" +#include "cxd2843.h" + ++#define FE_STATUS_FULL_LOCK (FE_HAS_SIGNAL \ ++ | FE_HAS_CARRIER \ ++ | FE_HAS_VITERBI \ ++ | FE_HAS_SYNC \ ++ | FE_HAS_LOCK) ++ ++#define INTLOG10X100(x) ((u32) (((u64) intlog10(x) * 100) >> 24)) ++ +#define USE_ALGO 1 + -+enum EDemodType { CXD2843, CXD2837, CXD2838 }; -+enum EDemodState { Unknown, Shutdown, Sleep, ActiveT, ++enum demod_type { CXD2843, CXD2837, CXD2838 }; ++enum demod_state { Unknown, Shutdown, Sleep, ActiveT, + ActiveT2, ActiveC, ActiveC2, ActiveIT }; -+enum ET2Profile { T2P_Base, T2P_Lite }; -+enum omode { OM_NONE, OM_DVBT, OM_DVBT2, OM_DVBC, -+ OM_QAM_ITU_C, OM_DVBC2, OM_ISDBT }; ++enum t2_profile { T2P_Base, T2P_Lite }; + +struct cxd_state { + struct dvb_frontend frontend; @@ -650,10 +891,10 @@ index 0000000..27e5eac + u8 adrx; + u8 curbankx; + -+ enum EDemodType type; -+ enum EDemodState state; -+ enum ET2Profile T2Profile; -+ enum omode omode; ++ enum demod_type type; ++ enum demod_state state; ++ enum t2_profile T2Profile; ++ enum fe_delivery_system delsys; + + u8 IF_FS; + int ContinuousClock; @@ -684,8 +925,8 @@ index 0000000..27e5eac + .addr = adr, .flags = 0, .buf = data, .len = len}; + + if (i2c_transfer(adap, &msg, 1) != 1) { -+ pr_err("cxd2843: i2c_write error\n"); -+ return -1; ++ pr_err("i2c_write error\n"); ++ return -EREMOTEIO; + } + return 0; +} @@ -715,8 +956,8 @@ index 0000000..27e5eac + { .addr = adr, .flags = I2C_M_RD, + .buf = answ, .len = alen } }; + if (i2c_transfer(adap, msgs, 2) != 2) { -+ pr_err("cxd2843: i2c_read error\n"); -+ return -1; ++ pr_err("i2c_read error\n"); ++ return -EREMOTEIO; + } + return 0; +} @@ -921,7 +1162,7 @@ index 0000000..27e5eac + +static int read_tps(struct cxd_state *state, u8 *tps) +{ -+ if (state->last_status != 0x1f) ++ if (state->last_status != FE_STATUS_FULL_LOCK) + return 0; + + freeze_regst(state); @@ -983,11 +1224,13 @@ index 0000000..27e5eac + writebitst(state, 0x25, 0x6A, 0x02, 0x03); + { + static u8 data[3] = { 0x07, 0x61, 0x36 }; ++ + writeregst(state, 0x25, 0x89, data, sizeof(data)); + } + writebitst(state, 0x25, 0xCB, 0x05, 0x07); + { + static u8 data[4] = { 0x2E, 0xE0, 0x2E, 0xE0 }; ++ + writeregst(state, 0x25, 0xDC, data, sizeof(data)); + } + writeregt(state, 0x25, 0xE2, 0x2F); @@ -1001,6 +1244,7 @@ index 0000000..27e5eac + writebitst(state, 0x2B, 0x2B, 0x00, 0x1F); + { + u8 data[2] = { 0x75, 0x75 }; ++ + writeregst(state, 0x2D, 0x24, data, sizeof(data)); + } + @@ -1014,7 +1258,7 @@ index 0000000..27e5eac +} + +static int ConfigureTS(struct cxd_state *state, -+ enum EDemodState newDemodState) ++ enum demod_state newDemodState) +{ + int status = 0; + u8 OSERCKMODE = state->SerialMode ? 1 : 0; @@ -1118,6 +1362,7 @@ index 0000000..27e5eac + { + u8 data[2] = { 0x09, 0x54 }; /* 20.5 MHz */ + /*u8 data[2] = { 0x0A, 0xD4 }; */ /* 41 MHz */ ++ + writeregst(state, 0x00, 0x43, data, 2); /* Enable ADC 2+3 */ + } + writeregx(state, 0x00, 0x18, 0x00); /* Enable ADC 4 */ @@ -1152,6 +1397,7 @@ index 0000000..27e5eac + case 8: + { + u8 TR_data[] = { 0x11, 0xF0, 0x00, 0x00, 0x00 }; ++ + /* Timing recovery */ + writeregst(state, 0x20, 0x9F, TR_data, sizeof(TR_data)); + /* Add EQ Optimisation for tuner here */ @@ -1163,6 +1409,7 @@ index 0000000..27e5eac + case 7: + { + u8 TR_data[] = { 0x14, 0x80, 0x00, 0x00, 0x00 }; ++ + writeregst(state, 0x20, 0x9F, TR_data, sizeof(TR_data)); + writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data)); + writebitst(state, 0x10, 0xD7, 0x02, 0x07); @@ -1171,6 +1418,7 @@ index 0000000..27e5eac + case 6: + { + u8 TR_data[] = { 0x17, 0xEA, 0xAA, 0xAA, 0xAA }; ++ + writeregst(state, 0x20, 0x9F, TR_data, sizeof(TR_data)); + writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data)); + writebitst(state, 0x10, 0xD7, 0x04, 0x07); @@ -1179,6 +1427,7 @@ index 0000000..27e5eac + case 5: + { + u8 TR_data[] = { 0x1C, 0xB3, 0x33, 0x33, 0x33 }; ++ + writeregst(state, 0x20, 0x9F, TR_data, sizeof(TR_data)); + writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data)); + writebitst(state, 0x10, 0xD7, 0x06, 0x07); @@ -1187,6 +1436,7 @@ index 0000000..27e5eac + case 2: /* 1.7 MHz */ + { + u8 TR_data[] = { 0x58, 0xE2, 0xAF, 0xE0, 0xBC }; ++ + writeregst(state, 0x20, 0x9F, TR_data, sizeof(TR_data)); + writeregst(state, 0x10, 0xB6, IF_data, sizeof(IF_data)); + writebitst(state, 0x10, 0xD7, 0x03, 0x07); @@ -1209,6 +1459,7 @@ index 0000000..27e5eac + { + u8 data[2] = { 0x09, 0x54 }; /* 20.5 MHz */ + /*u8 data[2] = { 0x0A, 0xD4 }; */ /* 41 MHz */ ++ + writeregst(state, 0x00, 0x43, data, 2); /* Enable ADC 2+3 */ + } + writeregx(state, 0x00, 0x18, 0x00); /* Enable ADC 4 */ @@ -1260,6 +1511,7 @@ index 0000000..27e5eac + { + u8 data[2] = { 0x09, 0x54 }; /* 20.5 MHz */ + /*u8 data[2] = { 0x0A, 0xD4 }; */ /* 41 MHz */ ++ + writeregst(state, 0x00, 0x43, data, 2); /* Enable ADC 2+3 */ + } + writeregx(state, 0x00, 0x18, 0x00); /* Enable ADC 4 */ @@ -1330,6 +1582,7 @@ index 0000000..27e5eac + { + u8 data[2] = { 0x09, 0x54 }; /* 20.5 MHz */ + /*u8 data[2] = { 0x0A, 0xD4 }; */ /* 41 MHz */ ++ + writeregst(state, 0x00, 0x43, data, sizeof(data)); + /* Enable ADC 2+3 */ + } @@ -1346,11 +1599,13 @@ index 0000000..27e5eac + writebitst(state, 0x25, 0x6A, 0x00, 0x03); + { + u8 data[3] = { 0x0C, 0xD1, 0x40 }; ++ + writeregst(state, 0x25, 0x89, data, sizeof(data)); + } + writebitst(state, 0x25, 0xCB, 0x01, 0x07); + { + u8 data[4] = { 0x7B, 0x00, 0x7B, 0x00 }; ++ + writeregst(state, 0x25, 0xDC, data, sizeof(data)); + } + writeregt(state, 0x25, 0xE2, 0x30); @@ -1364,6 +1619,7 @@ index 0000000..27e5eac + writebitst(state, 0x2B, 0x2B, 0x10, 0x1F); + { + u8 data[2] = { 0x01, 0x01 }; ++ + writeregst(state, 0x2D, 0x24, data, sizeof(data)); + } + @@ -1433,7 +1689,6 @@ index 0000000..27e5eac + u8 TSIF_data[2] = { 0x61, 0x60 } ; /* 20.5/41 MHz */ + /*u8 TSIF_data[2] = { 0x60,0x00 } ; */ /* 24 MHz */ + -+ pr_info("%s\n", __func__); + + ConfigureTS(state, ActiveIT); + @@ -1446,6 +1701,7 @@ index 0000000..27e5eac + { + u8 data[2] = { 0x09, 0x54 }; /* 20.5 MHz, 24 MHz */ + /*u8 data[2] = { 0x0A, 0xD4 }; */ /* 41 MHz */ ++ + writeregst(state, 0x00, 0x43, data, 2); /* Enable ADC 2+3 */ + } + writeregx(state, 0x00, 0x18, 0x00); /* Enable ADC 4 */ @@ -1491,6 +1747,7 @@ index 0000000..27e5eac +{ + { + static u8 data[2] = { 0x02, 0x80}; ++ + writeregst(state, 0x27, 0xF4, data, sizeof(data)); + } + writebitst(state, 0x27, 0x51, 0x40, 0xF0); @@ -1500,9 +1757,11 @@ index 0000000..27e5eac + writebitst(state, 0x27, 0x76, 0x19, 0x3F); + if (state->bw == 6) { + static u8 data[5] = { 0x17, 0xEA, 0xAA, 0xAA, 0xAA}; ++ + writeregst(state, 0x20, 0x9F, data, sizeof(data)); + } else { + static u8 data[5] = { 0x11, 0xF0, 0x00, 0x00, 0x00}; ++ + writeregst(state, 0x20, 0x9F, data, sizeof(data)); + } + writebitst(state, 0x27, 0xC9, 0x07, 0x07); @@ -1510,10 +1769,12 @@ index 0000000..27e5eac + { + static u8 data[10] = { 0x16, 0xF0, 0x2B, 0xD8, + 0x16, 0x16, 0xF0, 0x2C, 0xD8, 0x16 }; ++ + writeregst(state, 0x2A, 0x20, data, sizeof(data)); + } + { + static u8 data[4] = { 0x00, 0x00, 0x00, 0x00 }; ++ + writeregst(state, 0x50, 0x6B, data, sizeof(data)); + } + writebitst(state, 0x50, 0x6F, 0x00, 0x40); /* Disable Preset */ @@ -1581,9 +1842,18 @@ index 0000000..27e5eac + kfree(state); +} + ++static int sleep(struct dvb_frontend *fe) ++{ ++ struct cxd_state *state = fe->demodulator_priv; ++ ++ Stop(state); ++ ShutDown(state); ++ return 0; ++} ++ +static int Start(struct cxd_state *state, u32 IntermediateFrequency) +{ -+ enum EDemodState newDemodState = Unknown; ++ enum demod_state newDemodState = Unknown; + u32 iffreq; + + if (state->state < Sleep) @@ -1591,33 +1861,32 @@ index 0000000..27e5eac + + iffreq = MulDiv32(IntermediateFrequency, 16777216, 41000000); + -+ switch (state->omode) { -+ case OM_DVBT: ++ switch (state->delsys) { ++ case SYS_DVBT: + if (state->type == CXD2838) + return -EINVAL; + newDemodState = ActiveT; + break; -+ case OM_DVBT2: ++ case SYS_DVBT2: + if (state->type == CXD2838) + return -EINVAL; + newDemodState = ActiveT2; + break; -+ case OM_DVBC: -+ case OM_QAM_ITU_C: ++ case SYS_DVBC_ANNEX_A: + if (state->type == CXD2838) + return -EINVAL; + newDemodState = ActiveC; + break; -+ case OM_DVBC2: -+ if (state->type != CXD2843) -+ return -EINVAL; -+ newDemodState = ActiveC2; -+ break; -+ case OM_ISDBT: ++ case SYS_ISDBT: + if (state->type != CXD2838) + return -EINVAL; + newDemodState = ActiveIT; + break; ++ case SYS_DVBC2: ++ if (state->type != CXD2843) ++ return -EINVAL; ++ newDemodState = ActiveC2; ++ break; + default: + return -EINVAL; + } @@ -1717,16 +1986,11 @@ index 0000000..27e5eac + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBC_ANNEX_A: -+ state->omode = OM_DVBC; -+ break; ++ case SYS_DVBC2: + case SYS_DVBT: -+ state->omode = OM_DVBT; -+ break; + case SYS_DVBT2: -+ state->omode = OM_DVBT2; -+ break; + case SYS_ISDBT: -+ state->omode = OM_ISDBT; ++ state->delsys = fe->dtv_property_cache.delivery_system; + break; + default: + return -EINVAL; @@ -1744,7 +2008,8 @@ index 0000000..27e5eac + state->plp = fe->dtv_property_cache.stream_id & 0xff; + } + /* printk("PLP = %08x, bw = %u\n", state->plp, state->bw); */ -+ fe->ops.tuner_ops.get_if_frequency(fe, &IF); ++ if (fe->ops.tuner_ops.get_if_frequency) ++ fe->ops.tuner_ops.get_if_frequency(fe, &IF); + stat = Start(state, IF); + return stat; +} @@ -1754,8 +2019,8 @@ index 0000000..27e5eac +{ + u8 data[2] = {0x00, 0x00}; /* 20.5 MHz */ + -+ state->omode = OM_NONE; -+ state->state = Unknown; ++ state->delsys = SYS_UNDEFINED; ++ state->state = Unknown; + + writeregx(state, 0xFF, 0x02, 0x00); + usleep_range(4000, 5000); @@ -1812,25 +2077,11 @@ index 0000000..27e5eac + state->SerialClockFrequency = + (cfg->ts_clock >= 1 && cfg->ts_clock <= 5) ? + cfg->ts_clock : 1; /* 1 = fastest (82 MBit/s), 5 = slowest */ -+ state->SerialClockFrequency = 1; + /* IF Fullscale 0x50 = 1.4V, 0x39 = 1V, 0x28 = 0.7V */ + state->IF_FS = 0x50; +} + -+static int get_tune_settings(struct dvb_frontend *fe, -+ struct dvb_frontend_tune_settings *sets) -+{ -+ switch (fe->dtv_property_cache.delivery_system) { -+ case SYS_DVBC_ANNEX_A: -+ case SYS_DVBC_ANNEX_C: -+ /*return c_get_tune_settings(fe, sets);*/ -+ default: -+ /* DVB-T: Use info.frequency_stepsize. */ -+ return -EINVAL; -+ } -+} -+ -+static int read_status(struct dvb_frontend *fe, fe_status_t *status) ++static int read_status(struct dvb_frontend *fe, enum fe_status *status) +{ + struct cxd_state *state = fe->demodulator_priv; + u8 rdata; @@ -1842,10 +2093,16 @@ index 0000000..27e5eac + if (rdata & 0x02) + break; + if (rdata & 0x01) { -+ *status |= 0x07; ++ *status |= (FE_HAS_SIGNAL ++ | FE_HAS_CARRIER ++ | FE_HAS_VITERBI); + readregst(state, 0x40, 0x10, &rdata, 1); + if (rdata & 0x20) -+ *status |= 0x1f; ++ *status |= (FE_HAS_SIGNAL ++ | FE_HAS_CARRIER ++ | FE_HAS_VITERBI ++ | FE_HAS_SYNC ++ | FE_HAS_LOCK); + } + break; + case ActiveT: @@ -1853,9 +2110,15 @@ index 0000000..27e5eac + if (rdata & 0x10) + break; + if ((rdata & 0x07) == 0x06) { -+ *status |= 0x07; ++ *status |= (FE_HAS_SIGNAL ++ | FE_HAS_CARRIER ++ | FE_HAS_VITERBI); + if (rdata & 0x20) -+ *status |= 0x1f; ++ *status |= (FE_HAS_SIGNAL ++ | FE_HAS_CARRIER ++ | FE_HAS_VITERBI ++ | FE_HAS_SYNC ++ | FE_HAS_LOCK); + } + break; + case ActiveT2: @@ -1863,14 +2126,16 @@ index 0000000..27e5eac + if (rdata & 0x10) + break; + if ((rdata & 0x07) == 0x06) { -+ *status |= 0x07; ++ *status |= (FE_HAS_SIGNAL ++ | FE_HAS_CARRIER ++ | FE_HAS_VITERBI); + if (rdata & 0x20) -+ *status |= 0x08; ++ *status |= FE_HAS_SYNC; + } + if (*status & 0x08) { + readregst(state, 0x22, 0x12, &rdata, 1); + if (rdata & 0x01) -+ *status |= 0x10; ++ *status |= FE_HAS_LOCK; + } + break; + case ActiveC2: @@ -1878,11 +2143,13 @@ index 0000000..27e5eac + if (rdata & 0x10) + break; + if ((rdata & 0x07) == 0x06) { -+ *status |= 0x07; ++ *status |= (FE_HAS_SIGNAL ++ | FE_HAS_CARRIER ++ | FE_HAS_VITERBI); + if (rdata & 0x20) -+ *status |= 0x18; ++ *status |= (FE_HAS_SYNC | FE_HAS_LOCK); + } -+ if ((*status & 0x10) && state->FirstTimeLock) { ++ if ((*status & FE_HAS_LOCK) && state->FirstTimeLock) { + u8 data; + + /* Change1stTrial */ @@ -1899,9 +2166,11 @@ index 0000000..27e5eac + if (rdata & 0x10) + break; + if (rdata & 0x02) { -+ *status |= 0x07; ++ *status |= (FE_HAS_SIGNAL ++ | FE_HAS_CARRIER ++ | FE_HAS_VITERBI); + if (rdata & 0x01) -+ *status |= 0x18; ++ *status |= (FE_HAS_SYNC | FE_HAS_LOCK); + } + break; + default: @@ -1988,126 +2257,65 @@ index 0000000..27e5eac + return 0; +} + -+static int read_ber(struct dvb_frontend *fe, u32 *ber) ++static int read_ber(struct dvb_frontend *fe, u32 *ber, u32 *n, u32 *d) +{ + struct cxd_state *state = fe->demodulator_priv; -+ u32 n, d; + int s = 0; + + *ber = 0; ++ *n = 0; ++ *d = 1; ++ + switch (state->state) { + case ActiveT: -+ s = get_ber_t(state, &n, &d); ++ s = get_ber_t(state, n, d); + break; + case ActiveT2: -+ s = get_ber_t2(state, &n, &d); ++ s = get_ber_t2(state, n, d); + break; + case ActiveC: -+ s = get_ber_c(state, &n, &d); ++ s = get_ber_c(state, n, d); + break; + case ActiveC2: -+ s = get_ber_c2(state, &n, &d); ++ s = get_ber_c2(state, n, d); + break; + case ActiveIT: -+ s = get_ber_it(state, &n, &d); ++ s = get_ber_it(state, n, d); + break; + default: + break; + } ++ + if (s) + return s; + ++ if (d) ++ *ber = (*n * 1000) / *d; ++ + return 0; +} + -+static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) ++static u32 snrreg_to_db_t_c2_it(u32 reg, u32 max, u32 offset) +{ -+ if (fe->ops.tuner_ops.get_rf_strength) -+ fe->ops.tuner_ops.get_rf_strength(fe, strength); -+ else -+ *strength = 0; -+ return 0; -+} ++ s32 snr; + -+static s32 Log10x100(u32 x) -+{ -+ static u32 LookupTable[100] = { -+ 101157945, 103514217, 105925373, 108392691, 110917482, -+ 113501082, 116144861, 118850223, 121618600, 124451461, -+ 127350308, 130316678, 133352143, 136458314, 139636836, -+ 142889396, 146217717, 149623566, 153108746, 156675107, -+ 160324539, 164058977, 167880402, 171790839, 175792361, -+ 179887092, 184077200, 188364909, 192752491, 197242274, -+ 201836636, 206538016, 211348904, 216271852, 221309471, -+ 226464431, 231739465, 237137371, 242661010, 248313311, -+ 254097271, 260015956, 266072506, 272270131, 278612117, -+ 285101827, 291742701, 298538262, 305492111, 312607937, -+ 319889511, 327340695, 334965439, 342767787, 350751874, -+ 358921935, 367282300, 375837404, 384591782, 393550075, -+ 402717034, 412097519, 421696503, 431519077, 441570447, -+ 451855944, 462381021, 473151259, 484172368, 495450191, -+ 506990708, 518800039, 530884444, 543250331, 555904257, -+ 568852931, 582103218, 595662144, 609536897, 623734835, -+ 638263486, 653130553, 668343918, 683911647, 699841996, -+ 716143410, 732824533, 749894209, 767361489, 785235635, -+ 803526122, 822242650, 841395142, 860993752, 881048873, -+ 901571138, 922571427, 944060876, 966050879, 988553095, -+ }; -+ s32 y; -+ int i; -+ -+ if (x == 0) ++ if (reg == 0) + return 0; -+ y = 800; -+ if (x >= 1000000000) { -+ x /= 10; -+ y += 100; -+ } + -+ while (x < 100000000) { -+ x *= 10; -+ y -= 100; -+ } -+ i = 0; -+ while (i < 100 && x > LookupTable[i]) -+ i += 1; -+ y += i; -+ return y; ++ snr = 100 * ((INTLOG10X100(reg) - INTLOG10X100(max - reg)) + offset); ++ ++ if (snr < 0) ++ return 0; ++ ++ return snr; +} + -+#if 0 -+static void GetPLPIds(struct cxd_state *state, u32 nValues, -+ u8 *Values, u32 *Returned) ++static u32 snrreg_to_db_c(u32 reg, u32 max, u32 mult) +{ -+ u8 nPids = 0; -+ -+ *Returned = 0; -+ if (state->state != ActiveT2) -+ return; -+ if (state->last_status != 0x1f) -+ return; -+ -+ freeze_regst(state); -+ readregst_unlocked(state, 0x22, 0x7F, &nPids, 1); -+ -+ Values[0] = nPids; -+ if (nPids >= nValues) -+ nPids = nValues - 1; -+ -+ readregst_unlocked(state, 0x22, 0x80, &Values[1], -+ nPids > 128 ? 128 : nPids); -+ -+ if (nPids > 128) -+ readregst_unlocked(state, 0x23, 0x10, &Values[129], -+ nPids - 128); -+ -+ *Returned = nPids + 1; -+ -+ unfreeze_regst(state); ++ return (reg != 0 ? ((max - INTLOG10X100(reg)) * mult + 500) / 10 : 0); +} -+#endif + -+static void GetSignalToNoiseIT(struct cxd_state *state, u32 *SignalToNoise) ++static int GetSignalToNoiseIT(struct cxd_state *state, u32 *snr) +{ + u8 Data[2]; + u32 reg; @@ -2117,19 +2325,25 @@ index 0000000..27e5eac + unfreeze_regst(state); + + reg = (Data[0] << 8) | Data[1]; -+ if (reg > 51441) -+ reg = 51441; + -+ if (state->bw == 8) { ++ switch (state->bw) { ++ case 8: + if (reg > 1143) + reg = 1143; -+ *SignalToNoise = (Log10x100(reg) - -+ Log10x100(1200 - reg)) + 220; -+ } else -+ *SignalToNoise = Log10x100(reg) - 90; ++ *snr = snrreg_to_db_t_c2_it(reg, 1200, 220); ++ break; ++ default: ++ if (reg > 51441) ++ reg = 51441; ++ ++ *snr = (reg > 0 ? (INTLOG10X100(reg) - 90) : 0); ++ break; ++ } ++ ++ return 0; +} + -+static void GetSignalToNoiseC2(struct cxd_state *state, u32 *SignalToNoise) ++static int GetSignalToNoiseC2(struct cxd_state *state, u32 *snr) +{ + u8 Data[2]; + u32 reg; @@ -2142,11 +2356,13 @@ index 0000000..27e5eac + if (reg > 51441) + reg = 51441; + -+ *SignalToNoise = (Log10x100(reg) - Log10x100(55000 - reg)) + 384; ++ *snr = snrreg_to_db_t_c2_it(reg, 55000, 384); ++ ++ return 0; +} + + -+static void GetSignalToNoiseT2(struct cxd_state *state, u32 *SignalToNoise) ++static int GetSignalToNoiseT2(struct cxd_state *state, u32 *snr) +{ + u8 Data[2]; + u32 reg; @@ -2159,10 +2375,12 @@ index 0000000..27e5eac + if (reg > 10876) + reg = 10876; + -+ *SignalToNoise = (Log10x100(reg) - Log10x100(12600 - reg)) + 320; ++ *snr = snrreg_to_db_t_c2_it(reg, 12600, 320); ++ ++ return 0; +} + -+static void GetSignalToNoiseT(struct cxd_state *state, u32 *SignalToNoise) ++static int GetSignalToNoiseT(struct cxd_state *state, u32 *snr) +{ + u8 Data[2]; + u32 reg; @@ -2175,16 +2393,18 @@ index 0000000..27e5eac + if (reg > 4996) + reg = 4996; + -+ *SignalToNoise = (Log10x100(reg) - Log10x100(5350 - reg)) + 285; ++ *snr = snrreg_to_db_t_c2_it(reg, 5350, 285); ++ ++ return 0; +} + -+static void GetSignalToNoiseC(struct cxd_state *state, u32 *SignalToNoise) ++static int GetSignalToNoiseC(struct cxd_state *state, u32 *snr) +{ + u8 Data[2]; + u8 Constellation = 0; + u32 reg; + -+ *SignalToNoise = 0; ++ *snr = 0; + + freeze_regst(state); + readregst_unlocked(state, 0x40, 0x19, &Constellation, 1); @@ -2193,7 +2413,7 @@ index 0000000..27e5eac + + reg = ((u32)(Data[0] & 0x1F) << 8) | (Data[1]); + if (reg == 0) -+ return; ++ return 0; + + switch (Constellation & 0x07) { + case 0: /* QAM 16 */ @@ -2201,58 +2421,84 @@ index 0000000..27e5eac + case 4: /* QAM 256 */ + if (reg < 126) + reg = 126; -+ *SignalToNoise = ((439 - Log10x100(reg)) * 2134 + 500) / 1000; ++ *snr = snrreg_to_db_c(reg, 439, 2134); + break; + case 1: /* QAM 32 */ + case 3: /* QAM 128 */ + if (reg < 69) + reg = 69; -+ *SignalToNoise = ((432 - Log10x100(reg)) * 2015 + 500) / 1000; ++ *snr = snrreg_to_db_c(reg, 432, 2015); + break; + } ++ ++ return 0; +} + -+static int read_snr(struct dvb_frontend *fe, u16 *snr) ++static u32 read_snr(struct dvb_frontend *fe, u16 *snr) +{ ++ u32 ret = 0; + struct cxd_state *state = fe->demodulator_priv; -+ u32 SNR = 0; + -+ *snr = 0; -+ if (state->last_status != 0x1f) ++ if (state->last_status != FE_STATUS_FULL_LOCK) + return 0; + + switch (state->state) { + case ActiveC: -+ GetSignalToNoiseC(state, &SNR); ++ GetSignalToNoiseC(state, &ret); + break; + case ActiveC2: -+ GetSignalToNoiseC2(state, &SNR); ++ GetSignalToNoiseC2(state, &ret); + break; + case ActiveT: -+ GetSignalToNoiseT(state, &SNR); ++ GetSignalToNoiseT(state, &ret); + break; + case ActiveT2: -+ GetSignalToNoiseT2(state, &SNR); ++ GetSignalToNoiseT2(state, &ret); + break; + case ActiveIT: -+ GetSignalToNoiseIT(state, &SNR); ++ GetSignalToNoiseIT(state, &ret); + break; + default: -+ break; ++ return -EINVAL; + } -+ *snr = SNR; ++ ++ *snr = ret & 0xffff; + return 0; +} + -+static int read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) ++static int read_agc_gain_c_t_t2(struct dvb_frontend *fe, u16 *strength) +{ -+ *ucblocks = 0; ++ struct cxd_state *state = fe->demodulator_priv; ++ u8 data[2]; ++ u8 regbank; ++ ++ switch (state->state) { ++ case ActiveC: ++ case ActiveT: ++ regbank = 0x10; ++ break; ++ case ActiveT2: ++ regbank = 0x20; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ freeze_regst(state); ++ readregst_unlocked(state, regbank, 0x26, data, sizeof(data)); ++ unfreeze_regst(state); ++ ++ *strength = 65535 - ++ (((((u16)data[0] & 0x0F) << 8) ++ | (u16)(data[1] & 0xFF)) ++ << 4); ++ + return 0; +} + +static int tune(struct dvb_frontend *fe, bool re_tune, + unsigned int mode_flags, -+ unsigned int *delay, fe_status_t *status) ++ unsigned int *delay, enum fe_status *status) +{ + struct cxd_state *state = fe->demodulator_priv; + int r; @@ -2277,7 +2523,7 @@ index 0000000..27e5eac +{ + int r; + u32 loops = 20, i; -+ fe_status_t status; ++ enum fe_status status; + + r = set_parameters(fe); + @@ -2310,9 +2556,9 @@ index 0000000..27e5eac + read_tps(state, tps); + +/* TPSData[0] [7:6] CNST[1:0] -+ TPSData[0] [5:3] HIER[2:0] -+ TPSData[0] [2:0] HRATE[2:0] -+*/ ++ * TPSData[0] [5:3] HIER[2:0] ++ * TPSData[0] [2:0] HRATE[2:0] ++ */ + switch ((tps[0] >> 6) & 0x03) { + case 0: + p->modulation = QPSK; @@ -2357,9 +2603,9 @@ index 0000000..27e5eac + } + +/* TPSData[1] [7:5] LRATE[2:0] -+ TPSData[1] [4:3] GI[1:0] -+ TPSData[1] [2:1] MODE[1:0] -+*/ ++ * TPSData[1] [4:3] GI[1:0] ++ * TPSData[1] [2:1] MODE[1:0] ++ */ + switch ((tps[1] >> 5) & 0x07) { + case 0: + p->code_rate_LP = FEC_1_2; @@ -2412,38 +2658,74 @@ index 0000000..27e5eac + freeze_regst(state); + readregst_unlocked(state, 0x40, 0x19, &qam, 1); + unfreeze_regst(state); -+ p->modulation = qam & 0x07; ++ p->modulation = 1 + (qam & 0x07); + return 0; +} + -+static int get_frontend(struct dvb_frontend *fe) ++static int get_frontend(struct dvb_frontend *fe, ++ struct dtv_frontend_properties *p) +{ + struct cxd_state *state = fe->demodulator_priv; ++ enum fe_status status = 0; ++ int tmp; ++ u16 snr = 0, strength = 0; ++ u32 ber = 0, bernom = 0, berdenom = 1; ++ ++ tmp = read_status(fe, &status); ++ ++ p->strength.len = 1; ++ p->cnr.len = 1; ++ p->pre_bit_error.len = 1; ++ p->pre_bit_count.len = 1; ++ p->post_bit_error.len = 1; ++ ++ if (state->last_status != FE_STATUS_FULL_LOCK) { ++ p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; + -+ if (state->last_status != 0x1f) + return 0; -+ -+ switch (state->state) { -+ case ActiveT: -+ get_fe_t(state); -+ break; -+ case ActiveT2: -+ break; -+ case ActiveC: -+ get_fe_c(state); -+ break; -+ case ActiveC2: -+ break; -+ case ActiveIT: -+ break; -+ default: -+ break; + } ++ ++ if (state->state == ActiveT) ++ get_fe_t(state); ++ else if (state->state == ActiveC) ++ get_fe_c(state); ++ ++ if (read_agc_gain_c_t_t2(fe, &strength)) ++ p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ else { ++ p->strength.stat[0].scale = FE_SCALE_RELATIVE; ++ p->strength.stat[0].uvalue = strength; ++ } ++ ++ if (read_snr(fe, &snr)) ++ p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ else { ++ p->cnr.stat[0].scale = FE_SCALE_DECIBEL; ++ p->cnr.stat[0].svalue = snr; ++ } ++ ++ if (read_ber(fe, &ber, &bernom, &berdenom)) { ++ p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ } else { ++ p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; ++ p->pre_bit_error.stat[0].uvalue = bernom; ++ p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; ++ p->pre_bit_count.stat[0].uvalue = berdenom; ++ p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; ++ p->post_bit_error.stat[0].uvalue = ber; ++ } ++ + return 0; +} + +static struct dvb_frontend_ops common_ops_2843 = { -+ .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT, SYS_DVBT2 }, ++ .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT, SYS_DVBT2, SYS_DVBC2 }, + .info = { + .name = "CXD2843 DVB-C/C2 DVB-T/T2", + .frequency_stepsize = 166667, /* DVB-T only */ @@ -2451,28 +2733,22 @@ index 0000000..27e5eac + .frequency_max = 865000000, /* DVB-C: 862000000 */ + .symbol_rate_min = 870000, + .symbol_rate_max = 11700000, -+ .caps = /* DVB-C */ -+ FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | -+ FE_CAN_QAM_128 | FE_CAN_QAM_256 | -+ FE_CAN_FEC_AUTO | -+ /* DVB-T */ -+ FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | ++ .caps = FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_32 | ++ FE_CAN_QAM_64 | FE_CAN_QAM_128 | FE_CAN_QAM_256 | ++ FE_CAN_QAM_AUTO | + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | ++ FE_CAN_FEC_4_5 | + FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | -+ FE_CAN_RECOVER | FE_CAN_MUTE_TS ++ FE_CAN_RECOVER | FE_CAN_MUTE_TS | FE_CAN_2G_MODULATION + }, + .release = release, ++ .sleep = sleep, + .i2c_gate_ctrl = gate_ctrl, + .set_frontend = set_parameters, + -+ .get_tune_settings = get_tune_settings, + .read_status = read_status, -+ .read_ber = read_ber, -+ .read_signal_strength = read_signal_strength, -+ .read_snr = read_snr, -+ .read_ucblocks = read_ucblocks, + .get_frontend = get_frontend, +#ifdef USE_ALGO + .get_frontend_algo = get_algo, @@ -2490,28 +2766,22 @@ index 0000000..27e5eac + .frequency_max = 865000000, /* DVB-C: 862000000 */ + .symbol_rate_min = 870000, + .symbol_rate_max = 11700000, -+ .caps = /* DVB-C */ -+ FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | -+ FE_CAN_QAM_128 | FE_CAN_QAM_256 | -+ FE_CAN_FEC_AUTO | -+ /* DVB-T */ -+ FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | ++ .caps = FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_32 | ++ FE_CAN_QAM_64 | FE_CAN_QAM_128 | FE_CAN_QAM_256 | ++ FE_CAN_QAM_AUTO | + FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | ++ FE_CAN_FEC_4_5 | + FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | -+ FE_CAN_RECOVER | FE_CAN_MUTE_TS ++ FE_CAN_RECOVER | FE_CAN_MUTE_TS | FE_CAN_2G_MODULATION + }, + .release = release, ++ .sleep = sleep, + .i2c_gate_ctrl = gate_ctrl, + .set_frontend = set_parameters, + -+ .get_tune_settings = get_tune_settings, + .read_status = read_status, -+ .read_ber = read_ber, -+ .read_signal_strength = read_signal_strength, -+ .read_snr = read_snr, -+ .read_ucblocks = read_ucblocks, + .get_frontend = get_frontend, +#ifdef USE_ALGO + .get_frontend_algo = get_algo, @@ -2529,23 +2799,20 @@ index 0000000..27e5eac + .frequency_max = 865000000, + .symbol_rate_min = 870000, + .symbol_rate_max = 11700000, -+ .caps = FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | -+ FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | ++ .caps = FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | ++ FE_CAN_QAM_AUTO | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | ++ FE_CAN_FEC_3_4 | FE_CAN_FEC_4_5 | + FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | + FE_CAN_TRANSMISSION_MODE_AUTO | + FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | -+ FE_CAN_RECOVER | FE_CAN_MUTE_TS ++ FE_CAN_RECOVER | FE_CAN_MUTE_TS | FE_CAN_2G_MODULATION + }, + .release = release, ++ .sleep = sleep, + .i2c_gate_ctrl = gate_ctrl, + .set_frontend = set_parameters, + -+ .get_tune_settings = get_tune_settings, + .read_status = read_status, -+ .read_ber = read_ber, -+ .read_signal_strength = read_signal_strength, -+ .read_snr = read_snr, -+ .read_ucblocks = read_ucblocks, +#ifdef USE_ALGO + .get_frontend_algo = get_algo, + .search = search, @@ -2583,8 +2850,13 @@ index 0000000..27e5eac + sizeof(struct dvb_frontend_ops)); + break; + default: -+ return -1; ++ return -ENODEV; + } ++ ++ pr_info("%s with ChipID %02X found at adr %02X on %s\n", ++ state->frontend.ops.info.name, ChipID, state->adrt, ++ dev_name(&state->i2c->dev)); ++ + state->frontend.demodulator_priv = state; + return 0; +} @@ -2604,7 +2876,8 @@ index 0000000..27e5eac + init(state); + return &state->frontend; + } -+ pr_err("cxd2843: not found\n"); ++ pr_err("No supported demodulator found at adr %02X on %s\n", ++ cfg->adr, dev_name(&i2c->dev)); + kfree(state); + return NULL; +} @@ -2615,7 +2888,7 @@ index 0000000..27e5eac +MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb-frontends/cxd2843.h b/drivers/media/dvb-frontends/cxd2843.h new file mode 100644 -index 0000000..f3e355b +index 0000000..2467a6b --- /dev/null +++ b/drivers/media/dvb-frontends/cxd2843.h @@ -0,0 +1,30 @@ @@ -2631,12 +2904,12 @@ index 0000000..f3e355b + u8 parallel; +}; + -+#if defined(CONFIG_DVB_CXD2843) || \ -+ (defined(CONFIG_DVB_CXD2843_MODULE) && defined(MODULE)) ++#if IS_REACHABLE(CONFIG_DVB_CXD2843) + +extern struct dvb_frontend *cxd2843_attach(struct i2c_adapter *i2c, + struct cxd2843_cfg *cfg); + ++ +#else + +static inline struct dvb_frontend *cxd2843_attach(struct i2c_adapter *i2c, @@ -2646,6929 +2919,29 @@ index 0000000..f3e355b + return NULL; +} + -+#endif ++#endif /* CONFIG_DVB_CXD2843 */ + -+#endif -diff --git a/drivers/media/dvb-frontends/drxk_hard.c b/drivers/media/dvb-frontends/drxk_hard.c -index d46cf5f..91a7f9f 100644 ---- a/drivers/media/dvb-frontends/drxk_hard.c -+++ b/drivers/media/dvb-frontends/drxk_hard.c -@@ -21,8 +21,6 @@ - * Or, point your browser to http://www.gnu.org/copyleft/gpl.html - */ - --#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -- - #include - #include - #include -@@ -30,42 +28,50 @@ - #include - #include - #include --#include - #include - - #include "dvb_frontend.h" - #include "drxk.h" - #include "drxk_hard.h" --#include "dvb_math.h" -- --static int power_down_dvbt(struct drxk_state *state, bool set_power_mode); --static int power_down_qam(struct drxk_state *state); --static int set_dvbt_standard(struct drxk_state *state, -- enum operation_mode o_mode); --static int set_qam_standard(struct drxk_state *state, -- enum operation_mode o_mode); --static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, -- s32 tuner_freq_offset); --static int set_dvbt_standard(struct drxk_state *state, -- enum operation_mode o_mode); --static int dvbt_start(struct drxk_state *state); --static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, -- s32 tuner_freq_offset); --static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status); --static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status); --static int switch_antenna_to_qam(struct drxk_state *state); --static int switch_antenna_to_dvbt(struct drxk_state *state); -- --static bool is_dvbt(struct drxk_state *state) -+ -+static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode); -+static int PowerDownQAM(struct drxk_state *state); -+static int SetDVBTStandard(struct drxk_state *state, -+ enum OperationMode oMode); -+static int SetQAMStandard(struct drxk_state *state, -+ enum OperationMode oMode); -+static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, -+ s32 tunerFreqOffset); -+static int SetDVBTStandard(struct drxk_state *state, -+ enum OperationMode oMode); -+static int DVBTStart(struct drxk_state *state); -+static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, -+ s32 tunerFreqOffset); -+static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus); -+static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus); -+static int SwitchAntennaToQAM(struct drxk_state *state); -+static int SwitchAntennaToDVBT(struct drxk_state *state); -+ -+static bool IsDVBT(struct drxk_state *state) -+{ -+ return state->m_OperationMode == OM_DVBT; -+} -+ -+static bool IsQAM(struct drxk_state *state) -+{ -+ return state->m_OperationMode == OM_QAM_ITU_A || -+ state->m_OperationMode == OM_QAM_ITU_B || -+ state->m_OperationMode == OM_QAM_ITU_C; -+} -+ -+bool IsA1WithPatchCode(struct drxk_state *state) - { -- return state->m_operation_mode == OM_DVBT; -+ return state->m_DRXK_A1_PATCH_CODE; - } - --static bool is_qam(struct drxk_state *state) -+bool IsA1WithRomCode(struct drxk_state *state) - { -- return state->m_operation_mode == OM_QAM_ITU_A || -- state->m_operation_mode == OM_QAM_ITU_B || -- state->m_operation_mode == OM_QAM_ITU_C; -+ return state->m_DRXK_A1_ROM_CODE; - } - - #define NOA1ROM 0 -@@ -166,9 +172,9 @@ static unsigned int debug; - module_param(debug, int, 0644); - MODULE_PARM_DESC(debug, "enable debug messages"); - --#define dprintk(level, fmt, arg...) do { \ --if (debug >= level) \ -- printk(KERN_DEBUG KBUILD_MODNAME ": %s " fmt, __func__, ##arg); \ -+#define dprintk(level, fmt, arg...) do { \ -+if (debug >= level) \ -+ printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \ - } while (0) - - -@@ -182,17 +188,15 @@ static inline u32 MulDiv32(u32 a, u32 b, u32 c) - return (u32) tmp64; - } - --static inline u32 Frac28a(u32 a, u32 c) -+inline u32 Frac28a(u32 a, u32 c) - { - int i = 0; - u32 Q1 = 0; - u32 R0 = 0; - - R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ -- Q1 = a / c; /* -- * integer part, only the 4 least significant -- * bits will be visible in the result -- */ -+ Q1 = a / c; /* integer part, only the 4 least significant bits -+ will be visible in the result */ - - /* division using radix 16, 7 nibbles in the result */ - for (i = 0; i < 7; i++) { -@@ -206,51 +210,114 @@ static inline u32 Frac28a(u32 a, u32 c) - return Q1; - } - --static inline u32 log10times100(u32 value) -+static u32 Log10Times100(u32 x) - { -- return (100L * intlog10(value)) >> 24; --} -- --/****************************************************************************/ --/* I2C **********************************************************************/ --/****************************************************************************/ -+ static const u8 scale = 15; -+ static const u8 indexWidth = 5; -+ u8 i = 0; -+ u32 y = 0; -+ u32 d = 0; -+ u32 k = 0; -+ u32 r = 0; -+ /* -+ log2lut[n] = (1<i2c); -- state->drxk_i2c_exclusive_lock = true; -+ static const u32 log2lut[] = { -+ 0, /* 0.000000 */ -+ 290941, /* 290941.300628 */ -+ 573196, /* 573196.476418 */ -+ 847269, /* 847269.179851 */ -+ 1113620, /* 1113620.489452 */ -+ 1372674, /* 1372673.576986 */ -+ 1624818, /* 1624817.752104 */ -+ 1870412, /* 1870411.981536 */ -+ 2109788, /* 2109787.962654 */ -+ 2343253, /* 2343252.817465 */ -+ 2571091, /* 2571091.461923 */ -+ 2793569, /* 2793568.696416 */ -+ 3010931, /* 3010931.055901 */ -+ 3223408, /* 3223408.452106 */ -+ 3431216, /* 3431215.635215 */ -+ 3634553, /* 3634553.498355 */ -+ 3833610, /* 3833610.244726 */ -+ 4028562, /* 4028562.434393 */ -+ 4219576, /* 4219575.925308 */ -+ 4406807, /* 4406806.721144 */ -+ 4590402, /* 4590401.736809 */ -+ 4770499, /* 4770499.491025 */ -+ 4947231, /* 4947230.734179 */ -+ 5120719, /* 5120719.018555 */ -+ 5291081, /* 5291081.217197 */ -+ 5458428, /* 5458427.996830 */ -+ 5622864, /* 5622864.249668 */ -+ 5784489, /* 5784489.488298 */ -+ 5943398, /* 5943398.207380 */ -+ 6099680, /* 6099680.215452 */ -+ 6253421, /* 6253420.939751 */ -+ 6404702, /* 6404701.706649 */ -+ 6553600, /* 6553600.000000 */ -+ }; - -- return 0; --} - --static void drxk_i2c_unlock(struct drxk_state *state) --{ -- if (!state->drxk_i2c_exclusive_lock) -- return; -+ if (x == 0) -+ return 0; - -- i2c_unlock_adapter(state->i2c); -- state->drxk_i2c_exclusive_lock = false; -+ /* Scale x (normalize) */ -+ /* computing y in log(x/y) = log(x) - log(y) */ -+ if ((x & ((0xffffffff) << (scale + 1))) == 0) { -+ for (k = scale; k > 0; k--) { -+ if (x & (((u32) 1) << scale)) -+ break; -+ x <<= 1; -+ } -+ } else { -+ for (k = scale; k < 31; k++) { -+ if ((x & (((u32) (-1)) << (scale + 1))) == 0) -+ break; -+ x >>= 1; -+ } -+ } -+ /* -+ Now x has binary point between bit[scale] and bit[scale-1] -+ and 1.0 <= x < 2.0 */ -+ -+ /* correction for divison: log(x) = log(x/y)+log(y) */ -+ y = k * ((((u32) 1) << scale) * 200); -+ -+ /* remove integer part */ -+ x &= ((((u32) 1) << scale) - 1); -+ /* get index */ -+ i = (u8) (x >> (scale - indexWidth)); -+ /* compute delta (x - a) */ -+ d = x & ((((u32) 1) << (scale - indexWidth)) - 1); -+ /* compute log, multiplication (d* (..)) must be within range ! */ -+ y += log2lut[i] + -+ ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth)); -+ /* Conver to log10() */ -+ y /= 108853; /* (log2(10) << scale) */ -+ r = (y >> 1); -+ /* rounding */ -+ if (y & ((u32) 1)) -+ r++; -+ return r; - } - --static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs, -- unsigned len) --{ -- if (state->drxk_i2c_exclusive_lock) -- return __i2c_transfer(state->i2c, msgs, len); -- else -- return i2c_transfer(state->i2c, msgs, len); --} -+/****************************************************************************/ -+/* I2C **********************************************************************/ -+/****************************************************************************/ - --static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val) -+static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val) - { - struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD, - .buf = val, .len = 1} - }; - -- return drxk_i2c_transfer(state, msgs, 1); -+ return i2c_transfer(adapter, msgs, 1); - } - --static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len) -+static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) - { - int status; - struct i2c_msg msg = { -@@ -260,20 +327,20 @@ static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len) - if (debug > 2) { - int i; - for (i = 0; i < len; i++) -- pr_cont(" %02x", data[i]); -- pr_cont("\n"); -+ printk(KERN_CONT " %02x", data[i]); -+ printk(KERN_CONT "\n"); - } -- status = drxk_i2c_transfer(state, &msg, 1); -+ status = i2c_transfer(adap, &msg, 1); - if (status >= 0 && status != 1) - status = -EIO; - - if (status < 0) -- pr_err("i2c write error at addr 0x%02x\n", adr); -+ printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr); - - return status; - } - --static int i2c_read(struct drxk_state *state, -+static int i2c_read(struct i2c_adapter *adap, - u8 adr, u8 *msg, int len, u8 *answ, int alen) - { - int status; -@@ -284,25 +351,25 @@ static int i2c_read(struct drxk_state *state, - .buf = answ, .len = alen} - }; - -- status = drxk_i2c_transfer(state, msgs, 2); -+ status = i2c_transfer(adap, msgs, 2); - if (status != 2) { - if (debug > 2) -- pr_cont(": ERROR!\n"); -+ printk(KERN_CONT ": ERROR!\n"); - if (status >= 0) - status = -EIO; - -- pr_err("i2c read error at addr 0x%02x\n", adr); -+ printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr); - return status; - } - if (debug > 2) { - int i; - dprintk(2, ": read from"); - for (i = 0; i < len; i++) -- pr_cont(" %02x", msg[i]); -- pr_cont(", value = "); -+ printk(KERN_CONT " %02x", msg[i]); -+ printk(KERN_CONT ", value = "); - for (i = 0; i < alen; i++) -- pr_cont(" %02x", answ[i]); -- pr_cont("\n"); -+ printk(KERN_CONT " %02x", answ[i]); -+ printk(KERN_CONT "\n"); - } - return 0; - } -@@ -327,7 +394,7 @@ static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags) - len = 2; - } - dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); -- status = i2c_read(state, adr, mm1, len, mm2, 2); -+ status = i2c_read(state->i2c, adr, mm1, len, mm2, 2); - if (status < 0) - return status; - if (data) -@@ -361,7 +428,7 @@ static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags) - len = 2; - } - dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags); -- status = i2c_read(state, adr, mm1, len, mm2, 4); -+ status = i2c_read(state->i2c, adr, mm1, len, mm2, 4); - if (status < 0) - return status; - if (data) -@@ -397,7 +464,7 @@ static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags) - mm[len + 1] = (data >> 8) & 0xff; - - dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags); -- return i2c_write(state, adr, mm, len + 2); -+ return i2c_write(state->i2c, adr, mm, len + 2); - } - - static int write16(struct drxk_state *state, u32 reg, u16 data) -@@ -428,7 +495,7 @@ static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags) - mm[len + 3] = (data >> 24) & 0xff; - dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags); - -- return i2c_write(state, adr, mm, len + 4); -+ return i2c_write(state->i2c, adr, mm, len + 4); - } - - static int write32(struct drxk_state *state, u32 reg, u32 data) -@@ -436,55 +503,55 @@ static int write32(struct drxk_state *state, u32 reg, u32 data) - return write32_flags(state, reg, data, 0); - } - --static int write_block(struct drxk_state *state, u32 address, -- const int block_size, const u8 p_block[]) -+static int write_block(struct drxk_state *state, u32 Address, -+ const int BlockSize, const u8 pBlock[]) - { -- int status = 0, blk_size = block_size; -- u8 flags = 0; -+ int status = 0, BlkSize = BlockSize; -+ u8 Flags = 0; - - if (state->single_master) -- flags |= 0xC0; -- -- while (blk_size > 0) { -- int chunk = blk_size > state->m_chunk_size ? -- state->m_chunk_size : blk_size; -- u8 *adr_buf = &state->chunk[0]; -- u32 adr_length = 0; -- -- if (DRXDAP_FASI_LONG_FORMAT(address) || (flags != 0)) { -- adr_buf[0] = (((address << 1) & 0xFF) | 0x01); -- adr_buf[1] = ((address >> 16) & 0xFF); -- adr_buf[2] = ((address >> 24) & 0xFF); -- adr_buf[3] = ((address >> 7) & 0xFF); -- adr_buf[2] |= flags; -- adr_length = 4; -- if (chunk == state->m_chunk_size) -- chunk -= 2; -+ Flags |= 0xC0; -+ -+ while (BlkSize > 0) { -+ int Chunk = BlkSize > state->m_ChunkSize ? -+ state->m_ChunkSize : BlkSize; -+ u8 *AdrBuf = &state->Chunk[0]; -+ u32 AdrLength = 0; -+ -+ if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) { -+ AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01); -+ AdrBuf[1] = ((Address >> 16) & 0xFF); -+ AdrBuf[2] = ((Address >> 24) & 0xFF); -+ AdrBuf[3] = ((Address >> 7) & 0xFF); -+ AdrBuf[2] |= Flags; -+ AdrLength = 4; -+ if (Chunk == state->m_ChunkSize) -+ Chunk -= 2; - } else { -- adr_buf[0] = ((address << 1) & 0xFF); -- adr_buf[1] = (((address >> 16) & 0x0F) | -- ((address >> 18) & 0xF0)); -- adr_length = 2; -+ AdrBuf[0] = ((Address << 1) & 0xFF); -+ AdrBuf[1] = (((Address >> 16) & 0x0F) | -+ ((Address >> 18) & 0xF0)); -+ AdrLength = 2; - } -- memcpy(&state->chunk[adr_length], p_block, chunk); -- dprintk(2, "(0x%08x, 0x%02x)\n", address, flags); -+ memcpy(&state->Chunk[AdrLength], pBlock, Chunk); -+ dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags); - if (debug > 1) { - int i; -- if (p_block) -- for (i = 0; i < chunk; i++) -- pr_cont(" %02x", p_block[i]); -- pr_cont("\n"); -+ if (pBlock) -+ for (i = 0; i < Chunk; i++) -+ printk(KERN_CONT " %02x", pBlock[i]); -+ printk(KERN_CONT "\n"); - } -- status = i2c_write(state, state->demod_address, -- &state->chunk[0], chunk + adr_length); -+ status = i2c_write(state->i2c, state->demod_address, -+ &state->Chunk[0], Chunk + AdrLength); - if (status < 0) { -- pr_err("%s: i2c write error at addr 0x%02x\n", -- __func__, address); -+ printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n", -+ __func__, Address); - break; - } -- p_block += chunk; -- address += (chunk >> 1); -- blk_size -= chunk; -+ pBlock += Chunk; -+ Address += (Chunk >> 1); -+ BlkSize -= Chunk; - } - return status; - } -@@ -493,29 +560,29 @@ static int write_block(struct drxk_state *state, u32 address, - #define DRXK_MAX_RETRIES_POWERUP 20 - #endif - --static int power_up_device(struct drxk_state *state) -+int PowerUpDevice(struct drxk_state *state) - { - int status; - u8 data = 0; -- u16 retry_count = 0; -+ u16 retryCount = 0; - - dprintk(1, "\n"); - -- status = i2c_read1(state, state->demod_address, &data); -+ status = i2c_read1(state->i2c, state->demod_address, &data); - if (status < 0) { - do { - data = 0; -- status = i2c_write(state, state->demod_address, -+ status = i2c_write(state->i2c, state->demod_address, - &data, 1); -- usleep_range(10000, 11000); -- retry_count++; -+ msleep(10); -+ retryCount++; - if (status < 0) - continue; -- status = i2c_read1(state, state->demod_address, -+ status = i2c_read1(state->i2c, state->demod_address, - &data); - } while (status < 0 && -- (retry_count < DRXK_MAX_RETRIES_POWERUP)); -- if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP) -+ (retryCount < DRXK_MAX_RETRIES_POWERUP)); -+ if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP) - goto error; - } - -@@ -531,11 +598,11 @@ static int power_up_device(struct drxk_state *state) - if (status < 0) - goto error; - -- state->m_current_power_mode = DRX_POWER_UP; -+ state->m_currentPowerMode = DRX_POWER_UP; - - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - - return status; - } -@@ -547,106 +614,111 @@ static int init_state(struct drxk_state *state) - * FIXME: most (all?) of the values bellow should be moved into - * struct drxk_config, as they are probably board-specific - */ -- u32 ul_vsb_if_agc_mode = DRXK_AGC_CTRL_AUTO; -- u32 ul_vsb_if_agc_output_level = 0; -- u32 ul_vsb_if_agc_min_level = 0; -- u32 ul_vsb_if_agc_max_level = 0x7FFF; -- u32 ul_vsb_if_agc_speed = 3; -- -- u32 ul_vsb_rf_agc_mode = DRXK_AGC_CTRL_AUTO; -- u32 ul_vsb_rf_agc_output_level = 0; -- u32 ul_vsb_rf_agc_min_level = 0; -- u32 ul_vsb_rf_agc_max_level = 0x7FFF; -- u32 ul_vsb_rf_agc_speed = 3; -- u32 ul_vsb_rf_agc_top = 9500; -- u32 ul_vsb_rf_agc_cut_off_current = 4000; -- -- u32 ul_atv_if_agc_mode = DRXK_AGC_CTRL_AUTO; -- u32 ul_atv_if_agc_output_level = 0; -- u32 ul_atv_if_agc_min_level = 0; -- u32 ul_atv_if_agc_max_level = 0; -- u32 ul_atv_if_agc_speed = 3; -- -- u32 ul_atv_rf_agc_mode = DRXK_AGC_CTRL_OFF; -- u32 ul_atv_rf_agc_output_level = 0; -- u32 ul_atv_rf_agc_min_level = 0; -- u32 ul_atv_rf_agc_max_level = 0; -- u32 ul_atv_rf_agc_top = 9500; -- u32 ul_atv_rf_agc_cut_off_current = 4000; -- u32 ul_atv_rf_agc_speed = 3; -+ u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO; -+ u32 ulVSBIfAgcOutputLevel = 0; -+ u32 ulVSBIfAgcMinLevel = 0; -+ u32 ulVSBIfAgcMaxLevel = 0x7FFF; -+ u32 ulVSBIfAgcSpeed = 3; -+ -+ u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO; -+ u32 ulVSBRfAgcOutputLevel = 0; -+ u32 ulVSBRfAgcMinLevel = 0; -+ u32 ulVSBRfAgcMaxLevel = 0x7FFF; -+ u32 ulVSBRfAgcSpeed = 3; -+ u32 ulVSBRfAgcTop = 9500; -+ u32 ulVSBRfAgcCutOffCurrent = 4000; -+ -+ u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO; -+ u32 ulATVIfAgcOutputLevel = 0; -+ u32 ulATVIfAgcMinLevel = 0; -+ u32 ulATVIfAgcMaxLevel = 0; -+ u32 ulATVIfAgcSpeed = 3; -+ -+ u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF; -+ u32 ulATVRfAgcOutputLevel = 0; -+ u32 ulATVRfAgcMinLevel = 0; -+ u32 ulATVRfAgcMaxLevel = 0; -+ u32 ulATVRfAgcTop = 9500; -+ u32 ulATVRfAgcCutOffCurrent = 4000; -+ u32 ulATVRfAgcSpeed = 3; - - u32 ulQual83 = DEFAULT_MER_83; - u32 ulQual93 = DEFAULT_MER_93; - -- u32 ul_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; -- u32 ul_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; -+ u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; -+ u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; - - /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */ - /* io_pad_cfg_mode output mode is drive always */ - /* io_pad_cfg_drive is set to power 2 (23 mA) */ -- u32 ul_gpio_cfg = 0x0113; -- u32 ul_invert_ts_clock = 0; -- u32 ul_ts_data_strength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; -- u32 ul_dvbt_bitrate = 50000000; -- u32 ul_dvbc_bitrate = DRXK_QAM_SYMBOLRATE_MAX * 8; -+ u32 ulGPIOCfg = 0x0113; -+ u32 ulInvertTSClock = 0; -+ u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; -+ u32 ulDVBTBitrate = 50000000; -+ u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8; - -- u32 ul_insert_rs_byte = 0; -+ u32 ulInsertRSByte = 0; - -- u32 ul_rf_mirror = 1; -- u32 ul_power_down = 0; -+ u32 ulRfMirror = 1; -+ u32 ulPowerDown = 0; - - dprintk(1, "\n"); - -- state->m_has_lna = false; -- state->m_has_dvbt = false; -- state->m_has_dvbc = false; -- state->m_has_atv = false; -- state->m_has_oob = false; -- state->m_has_audio = false; -+ state->m_hasLNA = false; -+ state->m_hasDVBT = false; -+ state->m_hasDVBC = false; -+ state->m_hasATV = false; -+ state->m_hasOOB = false; -+ state->m_hasAudio = false; - -- if (!state->m_chunk_size) -- state->m_chunk_size = 124; -+ if (!state->m_ChunkSize) -+ state->m_ChunkSize = 124; - -- state->m_osc_clock_freq = 0; -- state->m_smart_ant_inverted = false; -- state->m_b_p_down_open_bridge = false; -+ state->m_oscClockFreq = 0; -+ state->m_smartAntInverted = false; -+ state->m_bPDownOpenBridge = false; - - /* real system clock frequency in kHz */ -- state->m_sys_clock_freq = 151875; -+ state->m_sysClockFreq = 151875; - /* Timing div, 250ns/Psys */ - /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */ -- state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) * -+ state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) * - HI_I2C_DELAY) / 1000; - /* Clipping */ -- if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) -- state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; -- state->m_hi_cfg_wake_up_key = (state->demod_address << 1); -+ if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) -+ state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; -+ state->m_HICfgWakeUpKey = (state->demod_address << 1); - /* port/bridge/power down ctrl */ -- state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; -+ state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; - -- state->m_b_power_down = (ul_power_down != 0); -+ state->m_bPowerDown = (ulPowerDown != 0); - -- state->m_drxk_a3_patch_code = false; -+ state->m_DRXK_A1_PATCH_CODE = false; -+ state->m_DRXK_A1_ROM_CODE = false; -+ state->m_DRXK_A2_ROM_CODE = false; -+ state->m_DRXK_A3_ROM_CODE = false; -+ state->m_DRXK_A2_PATCH_CODE = false; -+ state->m_DRXK_A3_PATCH_CODE = false; - - /* Init AGC and PGA parameters */ - /* VSB IF */ -- state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode; -- state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level; -- state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level; -- state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level; -- state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed; -- state->m_vsb_pga_cfg = 140; -+ state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode); -+ state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel); -+ state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel); -+ state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel); -+ state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed); -+ state->m_vsbPgaCfg = 140; - - /* VSB RF */ -- state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode; -- state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level; -- state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level; -- state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level; -- state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed; -- state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top; -- state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current; -- state->m_vsb_pre_saw_cfg.reference = 0x07; -- state->m_vsb_pre_saw_cfg.use_pre_saw = true; -+ state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode); -+ state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel); -+ state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel); -+ state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel); -+ state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed); -+ state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop); -+ state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent); -+ state->m_vsbPreSawCfg.reference = 0x07; -+ state->m_vsbPreSawCfg.usePreSaw = true; - - state->m_Quality83percent = DEFAULT_MER_83; - state->m_Quality93percent = DEFAULT_MER_93; -@@ -656,127 +728,127 @@ static int init_state(struct drxk_state *state) - } - - /* ATV IF */ -- state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode; -- state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level; -- state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level; -- state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level; -- state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed; -+ state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode); -+ state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel); -+ state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel); -+ state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel); -+ state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed); - - /* ATV RF */ -- state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode; -- state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level; -- state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level; -- state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level; -- state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed; -- state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top; -- state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current; -- state->m_atv_pre_saw_cfg.reference = 0x04; -- state->m_atv_pre_saw_cfg.use_pre_saw = true; -+ state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode); -+ state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel); -+ state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel); -+ state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel); -+ state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed); -+ state->m_atvRfAgcCfg.top = (ulATVRfAgcTop); -+ state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent); -+ state->m_atvPreSawCfg.reference = 0x04; -+ state->m_atvPreSawCfg.usePreSaw = true; - - - /* DVBT RF */ -- state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; -- state->m_dvbt_rf_agc_cfg.output_level = 0; -- state->m_dvbt_rf_agc_cfg.min_output_level = 0; -- state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF; -- state->m_dvbt_rf_agc_cfg.top = 0x2100; -- state->m_dvbt_rf_agc_cfg.cut_off_current = 4000; -- state->m_dvbt_rf_agc_cfg.speed = 1; -+ state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; -+ state->m_dvbtRfAgcCfg.outputLevel = 0; -+ state->m_dvbtRfAgcCfg.minOutputLevel = 0; -+ state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF; -+ state->m_dvbtRfAgcCfg.top = 0x2100; -+ state->m_dvbtRfAgcCfg.cutOffCurrent = 4000; -+ state->m_dvbtRfAgcCfg.speed = 1; - - - /* DVBT IF */ -- state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; -- state->m_dvbt_if_agc_cfg.output_level = 0; -- state->m_dvbt_if_agc_cfg.min_output_level = 0; -- state->m_dvbt_if_agc_cfg.max_output_level = 9000; -- state->m_dvbt_if_agc_cfg.top = 13424; -- state->m_dvbt_if_agc_cfg.cut_off_current = 0; -- state->m_dvbt_if_agc_cfg.speed = 3; -- state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30; -- state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000; -+ state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; -+ state->m_dvbtIfAgcCfg.outputLevel = 0; -+ state->m_dvbtIfAgcCfg.minOutputLevel = 0; -+ state->m_dvbtIfAgcCfg.maxOutputLevel = 9000; -+ state->m_dvbtIfAgcCfg.top = 13424; -+ state->m_dvbtIfAgcCfg.cutOffCurrent = 0; -+ state->m_dvbtIfAgcCfg.speed = 3; -+ state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30; -+ state->m_dvbtIfAgcCfg.IngainTgtMax = 30000; - /* state->m_dvbtPgaCfg = 140; */ - -- state->m_dvbt_pre_saw_cfg.reference = 4; -- state->m_dvbt_pre_saw_cfg.use_pre_saw = false; -+ state->m_dvbtPreSawCfg.reference = 4; -+ state->m_dvbtPreSawCfg.usePreSaw = false; - - /* QAM RF */ -- state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; -- state->m_qam_rf_agc_cfg.output_level = 0; -- state->m_qam_rf_agc_cfg.min_output_level = 6023; -- state->m_qam_rf_agc_cfg.max_output_level = 27000; -- state->m_qam_rf_agc_cfg.top = 0x2380; -- state->m_qam_rf_agc_cfg.cut_off_current = 4000; -- state->m_qam_rf_agc_cfg.speed = 3; -+ state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF; -+ state->m_qamRfAgcCfg.outputLevel = 0; -+ state->m_qamRfAgcCfg.minOutputLevel = 6023; -+ state->m_qamRfAgcCfg.maxOutputLevel = 27000; -+ state->m_qamRfAgcCfg.top = 0x2380; -+ state->m_qamRfAgcCfg.cutOffCurrent = 4000; -+ state->m_qamRfAgcCfg.speed = 3; - - /* QAM IF */ -- state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; -- state->m_qam_if_agc_cfg.output_level = 0; -- state->m_qam_if_agc_cfg.min_output_level = 0; -- state->m_qam_if_agc_cfg.max_output_level = 9000; -- state->m_qam_if_agc_cfg.top = 0x0511; -- state->m_qam_if_agc_cfg.cut_off_current = 0; -- state->m_qam_if_agc_cfg.speed = 3; -- state->m_qam_if_agc_cfg.ingain_tgt_max = 5119; -- state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50; -- -- state->m_qam_pga_cfg = 140; -- state->m_qam_pre_saw_cfg.reference = 4; -- state->m_qam_pre_saw_cfg.use_pre_saw = false; -- -- state->m_operation_mode = OM_NONE; -- state->m_drxk_state = DRXK_UNINITIALIZED; -+ state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO; -+ state->m_qamIfAgcCfg.outputLevel = 0; -+ state->m_qamIfAgcCfg.minOutputLevel = 0; -+ state->m_qamIfAgcCfg.maxOutputLevel = 9000; -+ state->m_qamIfAgcCfg.top = 0x0511; -+ state->m_qamIfAgcCfg.cutOffCurrent = 0; -+ state->m_qamIfAgcCfg.speed = 3; -+ state->m_qamIfAgcCfg.IngainTgtMax = 5119; -+ state->m_qamIfAgcCfg.FastClipCtrlDelay = 50; -+ -+ state->m_qamPgaCfg = 140; -+ state->m_qamPreSawCfg.reference = 4; -+ state->m_qamPreSawCfg.usePreSaw = false; -+ -+ state->m_OperationMode = OM_NONE; -+ state->m_DrxkState = DRXK_UNINITIALIZED; - - /* MPEG output configuration */ -- state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG ouput */ -- state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */ -- state->m_invert_data = false; /* If TRUE; invert DATA signals */ -- state->m_invert_err = false; /* If TRUE; invert ERR signal */ -- state->m_invert_str = false; /* If TRUE; invert STR signals */ -- state->m_invert_val = false; /* If TRUE; invert VAL signals */ -- state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */ -+ state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */ -+ state->m_insertRSByte = false; /* If TRUE; insert RS byte */ -+ state->m_invertDATA = false; /* If TRUE; invert DATA signals */ -+ state->m_invertERR = false; /* If TRUE; invert ERR signal */ -+ state->m_invertSTR = false; /* If TRUE; invert STR signals */ -+ state->m_invertVAL = false; /* If TRUE; invert VAL signals */ -+ state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */ - - /* If TRUE; static MPEG clockrate will be used; - otherwise clockrate will adapt to the bitrate of the TS */ - -- state->m_dvbt_bitrate = ul_dvbt_bitrate; -- state->m_dvbc_bitrate = ul_dvbc_bitrate; -+ state->m_DVBTBitrate = ulDVBTBitrate; -+ state->m_DVBCBitrate = ulDVBCBitrate; - -- state->m_ts_data_strength = (ul_ts_data_strength & 0x07); -+ state->m_TSDataStrength = (ulTSDataStrength & 0x07); - - /* Maximum bitrate in b/s in case static clockrate is selected */ -- state->m_mpeg_ts_static_bitrate = 19392658; -- state->m_disable_te_ihandling = false; -+ state->m_mpegTsStaticBitrate = 19392658; -+ state->m_disableTEIhandling = false; - -- if (ul_insert_rs_byte) -- state->m_insert_rs_byte = true; -+ if (ulInsertRSByte) -+ state->m_insertRSByte = true; - -- state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; -- if (ul_mpeg_lock_time_out < 10000) -- state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out; -- state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; -- if (ul_demod_lock_time_out < 10000) -- state->m_demod_lock_time_out = ul_demod_lock_time_out; -+ state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; -+ if (ulMpegLockTimeOut < 10000) -+ state->m_MpegLockTimeOut = ulMpegLockTimeOut; -+ state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; -+ if (ulDemodLockTimeOut < 10000) -+ state->m_DemodLockTimeOut = ulDemodLockTimeOut; - - /* QAM defaults */ -- state->m_constellation = DRX_CONSTELLATION_AUTO; -- state->m_qam_interleave_mode = DRXK_QAM_I12_J17; -- state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */ -- state->m_fec_rs_prescale = 1; -+ state->m_Constellation = DRX_CONSTELLATION_AUTO; -+ state->m_qamInterleaveMode = DRXK_QAM_I12_J17; -+ state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */ -+ state->m_fecRsPrescale = 1; - -- state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM; -- state->m_agcfast_clip_ctrl_delay = 0; -+ state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM; -+ state->m_agcFastClipCtrlDelay = 0; - -- state->m_gpio_cfg = ul_gpio_cfg; -+ state->m_GPIOCfg = (ulGPIOCfg); - -- state->m_b_power_down = false; -- state->m_current_power_mode = DRX_POWER_DOWN; -+ state->m_bPowerDown = false; -+ state->m_currentPowerMode = DRX_POWER_DOWN; - -- state->m_rfmirror = (ul_rf_mirror == 0); -- state->m_if_agc_pol = false; -+ state->m_rfmirror = (ulRfMirror == 0); -+ state->m_IfAgcPol = false; - return 0; - } - --static int drxx_open(struct drxk_state *state) -+static int DRXX_Open(struct drxk_state *state) - { - int status = 0; - u32 jtag = 0; -@@ -785,8 +857,7 @@ static int drxx_open(struct drxk_state *state) - - dprintk(1, "\n"); - /* stop lock indicator process */ -- status = write16(state, SCU_RAM_GPIO__A, -- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); -+ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); - if (status < 0) - goto error; - /* Check device id */ -@@ -805,14 +876,14 @@ static int drxx_open(struct drxk_state *state) - status = write16(state, SIO_TOP_COMM_KEY__A, key); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int get_device_capabilities(struct drxk_state *state) -+static int GetDeviceCapabilities(struct drxk_state *state) - { -- u16 sio_pdr_ohw_cfg = 0; -- u32 sio_top_jtagid_lo = 0; -+ u16 sioPdrOhwCfg = 0; -+ u32 sioTopJtagidLo = 0; - int status; - const char *spin = ""; - -@@ -820,196 +891,197 @@ static int get_device_capabilities(struct drxk_state *state) - - /* driver 0.9.0 */ - /* stop lock indicator process */ -- status = write16(state, SCU_RAM_GPIO__A, -- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); -+ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); - if (status < 0) - goto error; -- status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); -+ status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA); - if (status < 0) - goto error; -- status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg); -+ status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg); - if (status < 0) - goto error; - status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); - if (status < 0) - goto error; - -- switch ((sio_pdr_ohw_cfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { -+ switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) { - case 0: - /* ignore (bypass ?) */ - break; - case 1: - /* 27 MHz */ -- state->m_osc_clock_freq = 27000; -+ state->m_oscClockFreq = 27000; - break; - case 2: - /* 20.25 MHz */ -- state->m_osc_clock_freq = 20250; -+ state->m_oscClockFreq = 20250; - break; - case 3: - /* 4 MHz */ -- state->m_osc_clock_freq = 20250; -+ state->m_oscClockFreq = 20250; - break; - default: -- pr_err("Clock Frequency is unknown\n"); -+ printk(KERN_ERR "drxk: Clock Frequency is unkonwn\n"); - return -EINVAL; - } - /* - Determine device capabilities - Based on pinning v14 - */ -- status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo); -+ status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo); - if (status < 0) - goto error; - -- pr_info("status = 0x%08x\n", sio_top_jtagid_lo); -+printk(KERN_ERR "drxk: status = 0x%08x\n", sioTopJtagidLo); - - /* driver 0.9.0 */ -- switch ((sio_top_jtagid_lo >> 29) & 0xF) { -+ switch ((sioTopJtagidLo >> 29) & 0xF) { - case 0: -- state->m_device_spin = DRXK_SPIN_A1; -+ state->m_deviceSpin = DRXK_SPIN_A1; - spin = "A1"; - break; - case 2: -- state->m_device_spin = DRXK_SPIN_A2; -+ state->m_deviceSpin = DRXK_SPIN_A2; - spin = "A2"; - break; - case 3: -- state->m_device_spin = DRXK_SPIN_A3; -+ state->m_deviceSpin = DRXK_SPIN_A3; - spin = "A3"; - break; - default: -- state->m_device_spin = DRXK_SPIN_UNKNOWN; -+ state->m_deviceSpin = DRXK_SPIN_UNKNOWN; - status = -EINVAL; -- pr_err("Spin %d unknown\n", (sio_top_jtagid_lo >> 29) & 0xF); -+ printk(KERN_ERR "drxk: Spin %d unknown\n", -+ (sioTopJtagidLo >> 29) & 0xF); - goto error2; - } -- switch ((sio_top_jtagid_lo >> 12) & 0xFF) { -+ switch ((sioTopJtagidLo >> 12) & 0xFF) { - case 0x13: - /* typeId = DRX3913K_TYPE_ID */ -- state->m_has_lna = false; -- state->m_has_oob = false; -- state->m_has_atv = false; -- state->m_has_audio = false; -- state->m_has_dvbt = true; -- state->m_has_dvbc = true; -- state->m_has_sawsw = true; -- state->m_has_gpio2 = false; -- state->m_has_gpio1 = false; -- state->m_has_irqn = false; -+ state->m_hasLNA = false; -+ state->m_hasOOB = false; -+ state->m_hasATV = false; -+ state->m_hasAudio = false; -+ state->m_hasDVBT = true; -+ state->m_hasDVBC = true; -+ state->m_hasSAWSW = true; -+ state->m_hasGPIO2 = false; -+ state->m_hasGPIO1 = false; -+ state->m_hasIRQN = false; - break; - case 0x15: - /* typeId = DRX3915K_TYPE_ID */ -- state->m_has_lna = false; -- state->m_has_oob = false; -- state->m_has_atv = true; -- state->m_has_audio = false; -- state->m_has_dvbt = true; -- state->m_has_dvbc = false; -- state->m_has_sawsw = true; -- state->m_has_gpio2 = true; -- state->m_has_gpio1 = true; -- state->m_has_irqn = false; -+ state->m_hasLNA = false; -+ state->m_hasOOB = false; -+ state->m_hasATV = true; -+ state->m_hasAudio = false; -+ state->m_hasDVBT = true; -+ state->m_hasDVBC = false; -+ state->m_hasSAWSW = true; -+ state->m_hasGPIO2 = true; -+ state->m_hasGPIO1 = true; -+ state->m_hasIRQN = false; - break; - case 0x16: - /* typeId = DRX3916K_TYPE_ID */ -- state->m_has_lna = false; -- state->m_has_oob = false; -- state->m_has_atv = true; -- state->m_has_audio = false; -- state->m_has_dvbt = true; -- state->m_has_dvbc = false; -- state->m_has_sawsw = true; -- state->m_has_gpio2 = true; -- state->m_has_gpio1 = true; -- state->m_has_irqn = false; -+ state->m_hasLNA = false; -+ state->m_hasOOB = false; -+ state->m_hasATV = true; -+ state->m_hasAudio = false; -+ state->m_hasDVBT = true; -+ state->m_hasDVBC = false; -+ state->m_hasSAWSW = true; -+ state->m_hasGPIO2 = true; -+ state->m_hasGPIO1 = true; -+ state->m_hasIRQN = false; - break; - case 0x18: - /* typeId = DRX3918K_TYPE_ID */ -- state->m_has_lna = false; -- state->m_has_oob = false; -- state->m_has_atv = true; -- state->m_has_audio = true; -- state->m_has_dvbt = true; -- state->m_has_dvbc = false; -- state->m_has_sawsw = true; -- state->m_has_gpio2 = true; -- state->m_has_gpio1 = true; -- state->m_has_irqn = false; -+ state->m_hasLNA = false; -+ state->m_hasOOB = false; -+ state->m_hasATV = true; -+ state->m_hasAudio = true; -+ state->m_hasDVBT = true; -+ state->m_hasDVBC = false; -+ state->m_hasSAWSW = true; -+ state->m_hasGPIO2 = true; -+ state->m_hasGPIO1 = true; -+ state->m_hasIRQN = false; - break; - case 0x21: - /* typeId = DRX3921K_TYPE_ID */ -- state->m_has_lna = false; -- state->m_has_oob = false; -- state->m_has_atv = true; -- state->m_has_audio = true; -- state->m_has_dvbt = true; -- state->m_has_dvbc = true; -- state->m_has_sawsw = true; -- state->m_has_gpio2 = true; -- state->m_has_gpio1 = true; -- state->m_has_irqn = false; -+ state->m_hasLNA = false; -+ state->m_hasOOB = false; -+ state->m_hasATV = true; -+ state->m_hasAudio = true; -+ state->m_hasDVBT = true; -+ state->m_hasDVBC = true; -+ state->m_hasSAWSW = true; -+ state->m_hasGPIO2 = true; -+ state->m_hasGPIO1 = true; -+ state->m_hasIRQN = false; - break; - case 0x23: - /* typeId = DRX3923K_TYPE_ID */ -- state->m_has_lna = false; -- state->m_has_oob = false; -- state->m_has_atv = true; -- state->m_has_audio = true; -- state->m_has_dvbt = true; -- state->m_has_dvbc = true; -- state->m_has_sawsw = true; -- state->m_has_gpio2 = true; -- state->m_has_gpio1 = true; -- state->m_has_irqn = false; -+ state->m_hasLNA = false; -+ state->m_hasOOB = false; -+ state->m_hasATV = true; -+ state->m_hasAudio = true; -+ state->m_hasDVBT = true; -+ state->m_hasDVBC = true; -+ state->m_hasSAWSW = true; -+ state->m_hasGPIO2 = true; -+ state->m_hasGPIO1 = true; -+ state->m_hasIRQN = false; - break; - case 0x25: - /* typeId = DRX3925K_TYPE_ID */ -- state->m_has_lna = false; -- state->m_has_oob = false; -- state->m_has_atv = true; -- state->m_has_audio = true; -- state->m_has_dvbt = true; -- state->m_has_dvbc = true; -- state->m_has_sawsw = true; -- state->m_has_gpio2 = true; -- state->m_has_gpio1 = true; -- state->m_has_irqn = false; -+ state->m_hasLNA = false; -+ state->m_hasOOB = false; -+ state->m_hasATV = true; -+ state->m_hasAudio = true; -+ state->m_hasDVBT = true; -+ state->m_hasDVBC = true; -+ state->m_hasSAWSW = true; -+ state->m_hasGPIO2 = true; -+ state->m_hasGPIO1 = true; -+ state->m_hasIRQN = false; - break; - case 0x26: - /* typeId = DRX3926K_TYPE_ID */ -- state->m_has_lna = false; -- state->m_has_oob = false; -- state->m_has_atv = true; -- state->m_has_audio = false; -- state->m_has_dvbt = true; -- state->m_has_dvbc = true; -- state->m_has_sawsw = true; -- state->m_has_gpio2 = true; -- state->m_has_gpio1 = true; -- state->m_has_irqn = false; -+ state->m_hasLNA = false; -+ state->m_hasOOB = false; -+ state->m_hasATV = true; -+ state->m_hasAudio = false; -+ state->m_hasDVBT = true; -+ state->m_hasDVBC = true; -+ state->m_hasSAWSW = true; -+ state->m_hasGPIO2 = true; -+ state->m_hasGPIO1 = true; -+ state->m_hasIRQN = false; - break; - default: -- pr_err("DeviceID 0x%02x not supported\n", -- ((sio_top_jtagid_lo >> 12) & 0xFF)); -+ printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n", -+ ((sioTopJtagidLo >> 12) & 0xFF)); - status = -EINVAL; - goto error2; - } - -- pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n", -- ((sio_top_jtagid_lo >> 12) & 0xFF), spin, -- state->m_osc_clock_freq / 1000, -- state->m_osc_clock_freq % 1000); -+ printk(KERN_INFO -+ "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n", -+ ((sioTopJtagidLo >> 12) & 0xFF), spin, -+ state->m_oscClockFreq / 1000, -+ state->m_oscClockFreq % 1000); - - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - - error2: - return status; - } - --static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result) -+static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult) - { - int status; - bool powerdown_cmd; -@@ -1021,37 +1093,37 @@ static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result) - if (status < 0) - goto error; - if (cmd == SIO_HI_RA_RAM_CMD_RESET) -- usleep_range(1000, 2000); -+ msleep(1); - - powerdown_cmd = - (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) && -- ((state->m_hi_cfg_ctrl) & -+ ((state->m_HICfgCtrl) & - SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) == - SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ); -- if (!powerdown_cmd) { -+ if (powerdown_cmd == false) { - /* Wait until command rdy */ -- u32 retry_count = 0; -- u16 wait_cmd; -+ u32 retryCount = 0; -+ u16 waitCmd; - - do { -- usleep_range(1000, 2000); -- retry_count += 1; -+ msleep(1); -+ retryCount += 1; - status = read16(state, SIO_HI_RA_RAM_CMD__A, -- &wait_cmd); -- } while ((status < 0) && (retry_count < DRXK_MAX_RETRIES) -- && (wait_cmd != 0)); -+ &waitCmd); -+ } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES) -+ && (waitCmd != 0)); - if (status < 0) - goto error; -- status = read16(state, SIO_HI_RA_RAM_RES__A, p_result); -+ status = read16(state, SIO_HI_RA_RAM_RES__A, pResult); - } - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - - return status; - } - --static int hi_cfg_command(struct drxk_state *state) -+static int HI_CfgCommand(struct drxk_state *state) - { - int status; - -@@ -1059,77 +1131,70 @@ static int hi_cfg_command(struct drxk_state *state) - - mutex_lock(&state->mutex); - -- status = write16(state, SIO_HI_RA_RAM_PAR_6__A, -- state->m_hi_cfg_timeout); -+ status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout); - if (status < 0) - goto error; -- status = write16(state, SIO_HI_RA_RAM_PAR_5__A, -- state->m_hi_cfg_ctrl); -+ status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl); - if (status < 0) - goto error; -- status = write16(state, SIO_HI_RA_RAM_PAR_4__A, -- state->m_hi_cfg_wake_up_key); -+ status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey); - if (status < 0) - goto error; -- status = write16(state, SIO_HI_RA_RAM_PAR_3__A, -- state->m_hi_cfg_bridge_delay); -+ status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay); - if (status < 0) - goto error; -- status = write16(state, SIO_HI_RA_RAM_PAR_2__A, -- state->m_hi_cfg_timing_div); -+ status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv); - if (status < 0) - goto error; -- status = write16(state, SIO_HI_RA_RAM_PAR_1__A, -- SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); -+ status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); - if (status < 0) - goto error; -- status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL); -+ status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0); - if (status < 0) - goto error; - -- state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; -+ state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; - error: - mutex_unlock(&state->mutex); - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int init_hi(struct drxk_state *state) -+static int InitHI(struct drxk_state *state) - { - dprintk(1, "\n"); - -- state->m_hi_cfg_wake_up_key = (state->demod_address << 1); -- state->m_hi_cfg_timeout = 0x96FF; -+ state->m_HICfgWakeUpKey = (state->demod_address << 1); -+ state->m_HICfgTimeout = 0x96FF; - /* port/bridge/power down ctrl */ -- state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; -+ state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; - -- return hi_cfg_command(state); -+ return HI_CfgCommand(state); - } - --static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable) -+static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable) - { - int status = -1; -- u16 sio_pdr_mclk_cfg = 0; -- u16 sio_pdr_mdx_cfg = 0; -+ u16 sioPdrMclkCfg = 0; -+ u16 sioPdrMdxCfg = 0; - u16 err_cfg = 0; - - dprintk(1, ": mpeg %s, %s mode\n", -- mpeg_enable ? "enable" : "disable", -- state->m_enable_parallel ? "parallel" : "serial"); -+ mpegEnable ? "enable" : "disable", -+ state->m_enableParallel ? "parallel" : "serial"); - - /* stop lock indicator process */ -- status = write16(state, SCU_RAM_GPIO__A, -- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); -+ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); - if (status < 0) - goto error; - - /* MPEG TS pad configuration */ -- status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY); -+ status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA); - if (status < 0) - goto error; - -- if (!mpeg_enable) { -+ if (mpegEnable == false) { - /* Set MPEG TS pads to inputmode */ - status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000); - if (status < 0) -@@ -1169,19 +1234,19 @@ static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable) - goto error; - } else { - /* Enable MPEG output */ -- sio_pdr_mdx_cfg = -- ((state->m_ts_data_strength << -+ sioPdrMdxCfg = -+ ((state->m_TSDataStrength << - SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003); -- sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength << -+ sioPdrMclkCfg = ((state->m_TSClockkStrength << - SIO_PDR_MCLK_CFG_DRIVE__B) | - 0x0003); - -- status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg); -+ status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg); - if (status < 0) - goto error; - - if (state->enable_merr_cfg) -- err_cfg = sio_pdr_mdx_cfg; -+ err_cfg = sioPdrMdxCfg; - - status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg); - if (status < 0) -@@ -1190,38 +1255,31 @@ static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable) - if (status < 0) - goto error; - -- if (state->m_enable_parallel) { -- /* parallel -> enable MD1 to MD7 */ -- status = write16(state, SIO_PDR_MD1_CFG__A, -- sio_pdr_mdx_cfg); -+ if (state->m_enableParallel == true) { -+ /* paralel -> enable MD1 to MD7 */ -+ status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg); - if (status < 0) - goto error; -- status = write16(state, SIO_PDR_MD2_CFG__A, -- sio_pdr_mdx_cfg); -+ status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg); - if (status < 0) - goto error; -- status = write16(state, SIO_PDR_MD3_CFG__A, -- sio_pdr_mdx_cfg); -+ status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg); - if (status < 0) - goto error; -- status = write16(state, SIO_PDR_MD4_CFG__A, -- sio_pdr_mdx_cfg); -+ status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg); - if (status < 0) - goto error; -- status = write16(state, SIO_PDR_MD5_CFG__A, -- sio_pdr_mdx_cfg); -+ status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg); - if (status < 0) - goto error; -- status = write16(state, SIO_PDR_MD6_CFG__A, -- sio_pdr_mdx_cfg); -+ status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg); - if (status < 0) - goto error; -- status = write16(state, SIO_PDR_MD7_CFG__A, -- sio_pdr_mdx_cfg); -+ status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg); - if (status < 0) - goto error; - } else { -- sio_pdr_mdx_cfg = ((state->m_ts_data_strength << -+ sioPdrMdxCfg = ((state->m_TSDataStrength << - SIO_PDR_MD0_CFG_DRIVE__B) - | 0x0003); - /* serial -> disable MD1 to MD7 */ -@@ -1247,10 +1305,10 @@ static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable) - if (status < 0) - goto error; - } -- status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg); -+ status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg); - if (status < 0) - goto error; -- status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg); -+ status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg); - if (status < 0) - goto error; - } -@@ -1262,21 +1320,21 @@ static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable) - status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int mpegts_disable(struct drxk_state *state) -+static int MPEGTSDisable(struct drxk_state *state) - { - dprintk(1, "\n"); - -- return mpegts_configure_pins(state, false); -+ return MPEGTSConfigurePins(state, false); - } - --static int bl_chain_cmd(struct drxk_state *state, -- u16 rom_offset, u16 nr_of_elements, u32 time_out) -+static int BLChainCmd(struct drxk_state *state, -+ u16 romOffset, u16 nrOfElements, u32 timeOut) - { -- u16 bl_status = 0; -+ u16 blStatus = 0; - int status; - unsigned long end; - -@@ -1285,46 +1343,46 @@ static int bl_chain_cmd(struct drxk_state *state, - status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN); - if (status < 0) - goto error; -- status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset); -+ status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset); - if (status < 0) - goto error; -- status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements); -+ status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements); - if (status < 0) - goto error; - status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); - if (status < 0) - goto error; - -- end = jiffies + msecs_to_jiffies(time_out); -+ end = jiffies + msecs_to_jiffies(timeOut); - do { -- usleep_range(1000, 2000); -- status = read16(state, SIO_BL_STATUS__A, &bl_status); -+ msleep(1); -+ status = read16(state, SIO_BL_STATUS__A, &blStatus); - if (status < 0) - goto error; -- } while ((bl_status == 0x1) && -+ } while ((blStatus == 0x1) && - ((time_is_after_jiffies(end)))); - -- if (bl_status == 0x1) { -- pr_err("SIO not ready\n"); -+ if (blStatus == 0x1) { -+ printk(KERN_ERR "drxk: SIO not ready\n"); - status = -EINVAL; - goto error2; - } - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - error2: - mutex_unlock(&state->mutex); - return status; - } - - --static int download_microcode(struct drxk_state *state, -- const u8 p_mc_image[], u32 length) -+static int DownloadMicrocode(struct drxk_state *state, -+ const u8 pMCImage[], u32 Length) - { -- const u8 *p_src = p_mc_image; -- u32 address; -- u16 n_blocks; -- u16 block_size; -+ const u8 *pSrc = pMCImage; -+ u32 Address; -+ u16 nBlocks; -+ u16 BlockSize; - u32 offset = 0; - u32 i; - int status = 0; -@@ -1334,131 +1392,130 @@ static int download_microcode(struct drxk_state *state, - /* down the drain (we don't care about MAGIC_WORD) */ - #if 0 - /* For future reference */ -- drain = (p_src[0] << 8) | p_src[1]; -+ Drain = (pSrc[0] << 8) | pSrc[1]; - #endif -- p_src += sizeof(u16); -+ pSrc += sizeof(u16); - offset += sizeof(u16); -- n_blocks = (p_src[0] << 8) | p_src[1]; -- p_src += sizeof(u16); -+ nBlocks = (pSrc[0] << 8) | pSrc[1]; -+ pSrc += sizeof(u16); - offset += sizeof(u16); - -- for (i = 0; i < n_blocks; i += 1) { -- address = (p_src[0] << 24) | (p_src[1] << 16) | -- (p_src[2] << 8) | p_src[3]; -- p_src += sizeof(u32); -+ for (i = 0; i < nBlocks; i += 1) { -+ Address = (pSrc[0] << 24) | (pSrc[1] << 16) | -+ (pSrc[2] << 8) | pSrc[3]; -+ pSrc += sizeof(u32); - offset += sizeof(u32); - -- block_size = ((p_src[0] << 8) | p_src[1]) * sizeof(u16); -- p_src += sizeof(u16); -+ BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16); -+ pSrc += sizeof(u16); - offset += sizeof(u16); - - #if 0 - /* For future reference */ -- flags = (p_src[0] << 8) | p_src[1]; -+ Flags = (pSrc[0] << 8) | pSrc[1]; - #endif -- p_src += sizeof(u16); -+ pSrc += sizeof(u16); - offset += sizeof(u16); - - #if 0 - /* For future reference */ -- block_crc = (p_src[0] << 8) | p_src[1]; -+ BlockCRC = (pSrc[0] << 8) | pSrc[1]; - #endif -- p_src += sizeof(u16); -+ pSrc += sizeof(u16); - offset += sizeof(u16); - -- if (offset + block_size > length) { -- pr_err("Firmware is corrupted.\n"); -+ if (offset + BlockSize > Length) { -+ printk(KERN_ERR "drxk: Firmware is corrupted.\n"); - return -EINVAL; - } - -- status = write_block(state, address, block_size, p_src); -+ status = write_block(state, Address, BlockSize, pSrc); - if (status < 0) { -- pr_err("Error %d while loading firmware\n", status); -+ printk(KERN_ERR "drxk: Error %d while loading firmware\n", status); - break; - } -- p_src += block_size; -- offset += block_size; -+ pSrc += BlockSize; -+ offset += BlockSize; - } - return status; - } - --static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable) -+static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable) - { - int status; - u16 data = 0; -- u16 desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON; -- u16 desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED; -+ u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON; -+ u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED; - unsigned long end; - - dprintk(1, "\n"); - -- if (!enable) { -- desired_ctrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF; -- desired_status = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; -+ if (enable == false) { -+ desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF; -+ desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN; - } - - status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); -- if (status >= 0 && data == desired_status) { -+ if (status >= 0 && data == desiredStatus) { - /* tokenring already has correct status */ - return status; - } - /* Disable/enable dvbt tokenring bridge */ -- status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl); -+ status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl); - - end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT); - do { - status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data); -- if ((status >= 0 && data == desired_status) -- || time_is_after_jiffies(end)) -+ if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end)) - break; -- usleep_range(1000, 2000); -+ msleep(1); - } while (1); -- if (data != desired_status) { -- pr_err("SIO not ready\n"); -+ if (data != desiredStatus) { -+ printk(KERN_ERR "drxk: SIO not ready\n"); - return -EINVAL; - } - return status; - } - --static int mpegts_stop(struct drxk_state *state) -+static int MPEGTSStop(struct drxk_state *state) - { - int status = 0; -- u16 fec_oc_snc_mode = 0; -- u16 fec_oc_ipr_mode = 0; -+ u16 fecOcSncMode = 0; -+ u16 fecOcIprMode = 0; - - dprintk(1, "\n"); - -- /* Graceful shutdown (byte boundaries) */ -- status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); -+ /* Gracefull shutdown (byte boundaries) */ -+ status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode); - if (status < 0) - goto error; -- fec_oc_snc_mode |= FEC_OC_SNC_MODE_SHUTDOWN__M; -- status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); -+ fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M; -+ status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode); - if (status < 0) - goto error; - - /* Suppress MCLK during absence of data */ -- status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode); -+ status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode); - if (status < 0) - goto error; -- fec_oc_ipr_mode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; -- status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode); -+ fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M; -+ status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode); - - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - - return status; - } - - static int scu_command(struct drxk_state *state, -- u16 cmd, u8 parameter_len, -- u16 *parameter, u8 result_len, u16 *result) -+ u16 cmd, u8 parameterLen, -+ u16 *parameter, u8 resultLen, u16 *result) - { - #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 - #error DRXK register mapping no longer compatible with this routine! - #endif -- u16 cur_cmd = 0; -+ u16 curCmd = 0; - int status = -EINVAL; - unsigned long end; - u8 buffer[34]; -@@ -1468,9 +1525,9 @@ static int scu_command(struct drxk_state *state, - - dprintk(1, "\n"); - -- if ((cmd == 0) || ((parameter_len > 0) && (parameter == NULL)) || -- ((result_len > 0) && (result == NULL))) { -- pr_err("Error %d on %s\n", status, __func__); -+ if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) || -+ ((resultLen > 0) && (result == NULL))) { -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - -@@ -1478,7 +1535,7 @@ static int scu_command(struct drxk_state *state, - - /* assume that the command register is ready - since it is checked afterwards */ -- for (ii = parameter_len - 1; ii >= 0; ii -= 1) { -+ for (ii = parameterLen - 1; ii >= 0; ii -= 1) { - buffer[cnt++] = (parameter[ii] & 0xFF); - buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF); - } -@@ -1486,28 +1543,27 @@ static int scu_command(struct drxk_state *state, - buffer[cnt++] = ((cmd >> 8) & 0xFF); - - write_block(state, SCU_RAM_PARAM_0__A - -- (parameter_len - 1), cnt, buffer); -+ (parameterLen - 1), cnt, buffer); - /* Wait until SCU has processed command */ - end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME); - do { -- usleep_range(1000, 2000); -- status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd); -+ msleep(1); -+ status = read16(state, SCU_RAM_COMMAND__A, &curCmd); - if (status < 0) - goto error; -- } while (!(cur_cmd == DRX_SCU_READY) && (time_is_after_jiffies(end))); -- if (cur_cmd != DRX_SCU_READY) { -- pr_err("SCU not ready\n"); -+ } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end))); -+ if (curCmd != DRX_SCU_READY) { -+ printk(KERN_ERR "drxk: SCU not ready\n"); - status = -EIO; - goto error2; - } - /* read results */ -- if ((result_len > 0) && (result != NULL)) { -+ if ((resultLen > 0) && (result != NULL)) { - s16 err; - int ii; - -- for (ii = result_len - 1; ii >= 0; ii -= 1) { -- status = read16(state, SCU_RAM_PARAM_0__A - ii, -- &result[ii]); -+ for (ii = resultLen - 1; ii >= 0; ii -= 1) { -+ status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]); - if (status < 0) - goto error; - } -@@ -1535,7 +1591,7 @@ static int scu_command(struct drxk_state *state, - sprintf(errname, "ERROR: %d\n", err); - p = errname; - } -- pr_err("%s while sending cmd 0x%04x with params:", p, cmd); -+ printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd); - print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt); - status = -EINVAL; - goto error2; -@@ -1543,13 +1599,13 @@ static int scu_command(struct drxk_state *state, - - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - error2: - mutex_unlock(&state->mutex); - return status; - } - --static int set_iqm_af(struct drxk_state *state, bool active) -+static int SetIqmAf(struct drxk_state *state, bool active) - { - u16 data = 0; - int status; -@@ -1579,14 +1635,14 @@ static int set_iqm_af(struct drxk_state *state, bool active) - - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode) -+static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode) - { - int status = 0; -- u16 sio_cc_pwd_mode = 0; -+ u16 sioCcPwdMode = 0; - - dprintk(1, "\n"); - -@@ -1596,19 +1652,19 @@ static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode) - - switch (*mode) { - case DRX_POWER_UP: -- sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_NONE; -+ sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE; - break; - case DRXK_POWER_DOWN_OFDM: -- sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OFDM; -+ sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM; - break; - case DRXK_POWER_DOWN_CORE: -- sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_CLOCK; -+ sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK; - break; - case DRXK_POWER_DOWN_PLL: -- sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_PLL; -+ sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL; - break; - case DRX_POWER_DOWN: -- sio_cc_pwd_mode = SIO_CC_PWD_MODE_LEVEL_OSC; -+ sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC; - break; - default: - /* Unknow sleep mode */ -@@ -1616,15 +1672,15 @@ static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode) - } - - /* If already in requested power mode, do nothing */ -- if (state->m_current_power_mode == *mode) -+ if (state->m_currentPowerMode == *mode) - return 0; - - /* For next steps make sure to start from DRX_POWER_UP mode */ -- if (state->m_current_power_mode != DRX_POWER_UP) { -- status = power_up_device(state); -+ if (state->m_currentPowerMode != DRX_POWER_UP) { -+ status = PowerUpDevice(state); - if (status < 0) - goto error; -- status = dvbt_enable_ofdm_token_ring(state, true); -+ status = DVBTEnableOFDMTokenRing(state, true); - if (status < 0) - goto error; - } -@@ -1641,31 +1697,31 @@ static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode) - /* Power down device */ - /* stop all comm_exec */ - /* Stop and power down previous standard */ -- switch (state->m_operation_mode) { -+ switch (state->m_OperationMode) { - case OM_DVBT: -- status = mpegts_stop(state); -+ status = MPEGTSStop(state); - if (status < 0) - goto error; -- status = power_down_dvbt(state, false); -+ status = PowerDownDVBT(state, false); - if (status < 0) - goto error; - break; - case OM_QAM_ITU_A: - case OM_QAM_ITU_C: -- status = mpegts_stop(state); -+ status = MPEGTSStop(state); - if (status < 0) - goto error; -- status = power_down_qam(state); -+ status = PowerDownQAM(state); - if (status < 0) - goto error; - break; - default: - break; - } -- status = dvbt_enable_ofdm_token_ring(state, false); -+ status = DVBTEnableOFDMTokenRing(state, false); - if (status < 0) - goto error; -- status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode); -+ status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode); - if (status < 0) - goto error; - status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); -@@ -1673,26 +1729,26 @@ static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode) - goto error; - - if (*mode != DRXK_POWER_DOWN_OFDM) { -- state->m_hi_cfg_ctrl |= -+ state->m_HICfgCtrl |= - SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; -- status = hi_cfg_command(state); -+ status = HI_CfgCommand(state); - if (status < 0) - goto error; - } - } -- state->m_current_power_mode = *mode; -+ state->m_currentPowerMode = *mode; - - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - - return status; - } - --static int power_down_dvbt(struct drxk_state *state, bool set_power_mode) -+static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode) - { -- enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM; -- u16 cmd_result = 0; -+ enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM; -+ u16 cmdResult = 0; - u16 data = 0; - int status; - -@@ -1703,17 +1759,11 @@ static int power_down_dvbt(struct drxk_state *state, bool set_power_mode) - goto error; - if (data == SCU_COMM_EXEC_ACTIVE) { - /* Send OFDM stop command */ -- status = scu_command(state, -- SCU_RAM_COMMAND_STANDARD_OFDM -- | SCU_RAM_COMMAND_CMD_DEMOD_STOP, -- 0, NULL, 1, &cmd_result); -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult); - if (status < 0) - goto error; - /* Send OFDM reset command */ -- status = scu_command(state, -- SCU_RAM_COMMAND_STANDARD_OFDM -- | SCU_RAM_COMMAND_CMD_DEMOD_RESET, -- 0, NULL, 1, &cmd_result); -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult); - if (status < 0) - goto error; - } -@@ -1730,24 +1780,24 @@ static int power_down_dvbt(struct drxk_state *state, bool set_power_mode) - goto error; - - /* powerdown AFE */ -- status = set_iqm_af(state, false); -+ status = SetIqmAf(state, false); - if (status < 0) - goto error; - - /* powerdown to OFDM mode */ -- if (set_power_mode) { -- status = ctrl_power_mode(state, &power_mode); -+ if (setPowerMode) { -+ status = CtrlPowerMode(state, &powerMode); - if (status < 0) - goto error; - } - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int setoperation_mode(struct drxk_state *state, -- enum operation_mode o_mode) -+static int SetOperationMode(struct drxk_state *state, -+ enum OperationMode oMode) - { - int status = 0; - -@@ -1759,37 +1809,36 @@ static int setoperation_mode(struct drxk_state *state, - */ - - /* disable HW lock indicator */ -- status = write16(state, SCU_RAM_GPIO__A, -- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); -+ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); - if (status < 0) - goto error; - - /* Device is already at the required mode */ -- if (state->m_operation_mode == o_mode) -+ if (state->m_OperationMode == oMode) - return 0; - -- switch (state->m_operation_mode) { -+ switch (state->m_OperationMode) { - /* OM_NONE was added for start up */ - case OM_NONE: - break; - case OM_DVBT: -- status = mpegts_stop(state); -+ status = MPEGTSStop(state); - if (status < 0) - goto error; -- status = power_down_dvbt(state, true); -+ status = PowerDownDVBT(state, true); - if (status < 0) - goto error; -- state->m_operation_mode = OM_NONE; -+ state->m_OperationMode = OM_NONE; - break; - case OM_QAM_ITU_A: /* fallthrough */ - case OM_QAM_ITU_C: -- status = mpegts_stop(state); -+ status = MPEGTSStop(state); - if (status < 0) - goto error; -- status = power_down_qam(state); -+ status = PowerDownQAM(state); - if (status < 0) - goto error; -- state->m_operation_mode = OM_NONE; -+ state->m_OperationMode = OM_NONE; - break; - case OM_QAM_ITU_B: - default: -@@ -1800,20 +1849,20 @@ static int setoperation_mode(struct drxk_state *state, - /* - Power up new standard - */ -- switch (o_mode) { -+ switch (oMode) { - case OM_DVBT: - dprintk(1, ": DVB-T\n"); -- state->m_operation_mode = o_mode; -- status = set_dvbt_standard(state, o_mode); -+ state->m_OperationMode = oMode; -+ status = SetDVBTStandard(state, oMode); - if (status < 0) - goto error; - break; - case OM_QAM_ITU_A: /* fallthrough */ - case OM_QAM_ITU_C: - dprintk(1, ": DVB-C Annex %c\n", -- (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C'); -- state->m_operation_mode = o_mode; -- status = set_qam_standard(state, o_mode); -+ (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C'); -+ state->m_OperationMode = oMode; -+ status = SetQAMStandard(state, oMode); - if (status < 0) - goto error; - break; -@@ -1823,121 +1872,123 @@ static int setoperation_mode(struct drxk_state *state, - } - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int start(struct drxk_state *state, s32 offset_freq, -- s32 intermediate_frequency) -+static int Start(struct drxk_state *state, s32 offsetFreq, -+ s32 IntermediateFrequency) - { - int status = -EINVAL; - -- u16 i_freqk_hz; -- s32 offsetk_hz = offset_freq / 1000; -+ u16 IFreqkHz; -+ s32 OffsetkHz = offsetFreq / 1000; - - dprintk(1, "\n"); -- if (state->m_drxk_state != DRXK_STOPPED && -- state->m_drxk_state != DRXK_DTV_STARTED) -+ if (state->m_DrxkState != DRXK_STOPPED && -+ state->m_DrxkState != DRXK_DTV_STARTED) - goto error; - -- state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON); -+ state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON); - -- if (intermediate_frequency < 0) { -- state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect; -- intermediate_frequency = -intermediate_frequency; -+ if (IntermediateFrequency < 0) { -+ state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; -+ IntermediateFrequency = -IntermediateFrequency; - } - -- switch (state->m_operation_mode) { -+ switch (state->m_OperationMode) { - case OM_QAM_ITU_A: - case OM_QAM_ITU_C: -- i_freqk_hz = (intermediate_frequency / 1000); -- status = set_qam(state, i_freqk_hz, offsetk_hz); -+ IFreqkHz = (IntermediateFrequency / 1000); -+ status = SetQAM(state, IFreqkHz, OffsetkHz); - if (status < 0) - goto error; -- state->m_drxk_state = DRXK_DTV_STARTED; -+ state->m_DrxkState = DRXK_DTV_STARTED; - break; - case OM_DVBT: -- i_freqk_hz = (intermediate_frequency / 1000); -- status = mpegts_stop(state); -+ IFreqkHz = (IntermediateFrequency / 1000); -+ status = MPEGTSStop(state); - if (status < 0) - goto error; -- status = set_dvbt(state, i_freqk_hz, offsetk_hz); -+ status = SetDVBT(state, IFreqkHz, OffsetkHz); - if (status < 0) - goto error; -- status = dvbt_start(state); -+ status = DVBTStart(state); - if (status < 0) - goto error; -- state->m_drxk_state = DRXK_DTV_STARTED; -+ state->m_DrxkState = DRXK_DTV_STARTED; - break; - default: - break; - } - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int shut_down(struct drxk_state *state) -+static int ShutDown(struct drxk_state *state) - { - dprintk(1, "\n"); - -- mpegts_stop(state); -+ MPEGTSStop(state); - return 0; - } - --static int get_lock_status(struct drxk_state *state, u32 *p_lock_status) -+static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus, -+ u32 Time) - { - int status = -EINVAL; - - dprintk(1, "\n"); - -- if (p_lock_status == NULL) -+ if (pLockStatus == NULL) - goto error; - -- *p_lock_status = NOT_LOCKED; -+ *pLockStatus = NOT_LOCKED; - - /* define the SCU command code */ -- switch (state->m_operation_mode) { -+ switch (state->m_OperationMode) { - case OM_QAM_ITU_A: - case OM_QAM_ITU_B: - case OM_QAM_ITU_C: -- status = get_qam_lock_status(state, p_lock_status); -+ status = GetQAMLockStatus(state, pLockStatus); - break; - case OM_DVBT: -- status = get_dvbt_lock_status(state, p_lock_status); -+ status = GetDVBTLockStatus(state, pLockStatus); - break; - default: -+ status = 0; - break; - } - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int mpegts_start(struct drxk_state *state) -+static int MPEGTSStart(struct drxk_state *state) - { - int status; - -- u16 fec_oc_snc_mode = 0; -+ u16 fecOcSncMode = 0; - - /* Allow OC to sync again */ -- status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode); -+ status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode); - if (status < 0) - goto error; -- fec_oc_snc_mode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; -- status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode); -+ fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M; -+ status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode); - if (status < 0) - goto error; - status = write16(state, FEC_OC_SNC_UNLOCK__A, 1); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int mpegts_dto_init(struct drxk_state *state) -+static int MPEGTSDtoInit(struct drxk_state *state) - { - int status; - -@@ -1979,68 +2030,68 @@ static int mpegts_dto_init(struct drxk_state *state) - status = write16(state, FEC_OC_SNC_HWM__A, 12); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - - return status; - } - --static int mpegts_dto_setup(struct drxk_state *state, -- enum operation_mode o_mode) -+static int MPEGTSDtoSetup(struct drxk_state *state, -+ enum OperationMode oMode) - { - int status; - -- u16 fec_oc_reg_mode = 0; /* FEC_OC_MODE register value */ -- u16 fec_oc_reg_ipr_mode = 0; /* FEC_OC_IPR_MODE register value */ -- u16 fec_oc_dto_mode = 0; /* FEC_OC_IPR_INVERT register value */ -- u16 fec_oc_fct_mode = 0; /* FEC_OC_IPR_INVERT register value */ -- u16 fec_oc_dto_period = 2; /* FEC_OC_IPR_INVERT register value */ -- u16 fec_oc_dto_burst_len = 188; /* FEC_OC_IPR_INVERT register value */ -- u32 fec_oc_rcn_ctl_rate = 0; /* FEC_OC_IPR_INVERT register value */ -- u16 fec_oc_tmd_mode = 0; -- u16 fec_oc_tmd_int_upd_rate = 0; -- u32 max_bit_rate = 0; -- bool static_clk = false; -+ u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */ -+ u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */ -+ u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */ -+ u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */ -+ u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */ -+ u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */ -+ u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */ -+ u16 fecOcTmdMode = 0; -+ u16 fecOcTmdIntUpdRate = 0; -+ u32 maxBitRate = 0; -+ bool staticCLK = false; - - dprintk(1, "\n"); - - /* Check insertion of the Reed-Solomon parity bytes */ -- status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode); -+ status = read16(state, FEC_OC_MODE__A, &fecOcRegMode); - if (status < 0) - goto error; -- status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode); -+ status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode); - if (status < 0) - goto error; -- fec_oc_reg_mode &= (~FEC_OC_MODE_PARITY__M); -- fec_oc_reg_ipr_mode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); -- if (state->m_insert_rs_byte) { -+ fecOcRegMode &= (~FEC_OC_MODE_PARITY__M); -+ fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M); -+ if (state->m_insertRSByte == true) { - /* enable parity symbol forward */ -- fec_oc_reg_mode |= FEC_OC_MODE_PARITY__M; -+ fecOcRegMode |= FEC_OC_MODE_PARITY__M; - /* MVAL disable during parity bytes */ -- fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; -+ fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M; - /* TS burst length to 204 */ -- fec_oc_dto_burst_len = 204; -+ fecOcDtoBurstLen = 204; - } - -- /* Check serial or parallel output */ -- fec_oc_reg_ipr_mode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); -- if (!state->m_enable_parallel) { -+ /* Check serial or parrallel output */ -+ fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M)); -+ if (state->m_enableParallel == false) { - /* MPEG data output is serial -> set ipr_mode[0] */ -- fec_oc_reg_ipr_mode |= FEC_OC_IPR_MODE_SERIAL__M; -+ fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M; - } - -- switch (o_mode) { -+ switch (oMode) { - case OM_DVBT: -- max_bit_rate = state->m_dvbt_bitrate; -- fec_oc_tmd_mode = 3; -- fec_oc_rcn_ctl_rate = 0xC00000; -- static_clk = state->m_dvbt_static_clk; -+ maxBitRate = state->m_DVBTBitrate; -+ fecOcTmdMode = 3; -+ fecOcRcnCtlRate = 0xC00000; -+ staticCLK = state->m_DVBTStaticCLK; - break; - case OM_QAM_ITU_A: /* fallthrough */ - case OM_QAM_ITU_C: -- fec_oc_tmd_mode = 0x0004; -- fec_oc_rcn_ctl_rate = 0xD2B4EE; /* good for >63 Mb/s */ -- max_bit_rate = state->m_dvbc_bitrate; -- static_clk = state->m_dvbc_static_clk; -+ fecOcTmdMode = 0x0004; -+ fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */ -+ maxBitRate = state->m_DVBCBitrate; -+ staticCLK = state->m_DVBCStaticCLK; - break; - default: - status = -EINVAL; -@@ -2049,84 +2100,83 @@ static int mpegts_dto_setup(struct drxk_state *state, - goto error; - - /* Configure DTO's */ -- if (static_clk) { -- u32 bit_rate = 0; -+ if (staticCLK) { -+ u32 bitRate = 0; - - /* Rational DTO for MCLK source (static MCLK rate), - Dynamic DTO for optimal grouping - (avoid intra-packet gaps), - DTO offset enable to sync TS burst with MSTRT */ -- fec_oc_dto_mode = (FEC_OC_DTO_MODE_DYNAMIC__M | -+ fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M | - FEC_OC_DTO_MODE_OFFSET_ENABLE__M); -- fec_oc_fct_mode = (FEC_OC_FCT_MODE_RAT_ENA__M | -+ fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M | - FEC_OC_FCT_MODE_VIRT_ENA__M); - - /* Check user defined bitrate */ -- bit_rate = max_bit_rate; -- if (bit_rate > 75900000UL) { /* max is 75.9 Mb/s */ -- bit_rate = 75900000UL; -+ bitRate = maxBitRate; -+ if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */ -+ bitRate = 75900000UL; - } - /* Rational DTO period: - dto_period = (Fsys / bitrate) - 2 - -- result should be floored, -+ Result should be floored, - to make sure >= requested bitrate - */ -- fec_oc_dto_period = (u16) (((state->m_sys_clock_freq) -- * 1000) / bit_rate); -- if (fec_oc_dto_period <= 2) -- fec_oc_dto_period = 0; -+ fecOcDtoPeriod = (u16) (((state->m_sysClockFreq) -+ * 1000) / bitRate); -+ if (fecOcDtoPeriod <= 2) -+ fecOcDtoPeriod = 0; - else -- fec_oc_dto_period -= 2; -- fec_oc_tmd_int_upd_rate = 8; -+ fecOcDtoPeriod -= 2; -+ fecOcTmdIntUpdRate = 8; - } else { -- /* (commonAttr->static_clk == false) => dynamic mode */ -- fec_oc_dto_mode = FEC_OC_DTO_MODE_DYNAMIC__M; -- fec_oc_fct_mode = FEC_OC_FCT_MODE__PRE; -- fec_oc_tmd_int_upd_rate = 5; -+ /* (commonAttr->staticCLK == false) => dynamic mode */ -+ fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M; -+ fecOcFctMode = FEC_OC_FCT_MODE__PRE; -+ fecOcTmdIntUpdRate = 5; - } - - /* Write appropriate registers with requested configuration */ -- status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len); -+ status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen); - if (status < 0) - goto error; -- status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period); -+ status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod); - if (status < 0) - goto error; -- status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode); -+ status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode); - if (status < 0) - goto error; -- status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode); -+ status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode); - if (status < 0) - goto error; -- status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode); -+ status = write16(state, FEC_OC_MODE__A, fecOcRegMode); - if (status < 0) - goto error; -- status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode); -+ status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode); - if (status < 0) - goto error; - - /* Rate integration settings */ -- status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate); -+ status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate); - if (status < 0) - goto error; -- status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, -- fec_oc_tmd_int_upd_rate); -+ status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate); - if (status < 0) - goto error; -- status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode); -+ status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int mpegts_configure_polarity(struct drxk_state *state) -+static int MPEGTSConfigurePolarity(struct drxk_state *state) - { -- u16 fec_oc_reg_ipr_invert = 0; -+ u16 fecOcRegIprInvert = 0; - - /* Data mask for the output data byte */ -- u16 invert_data_mask = -+ u16 InvertDataMask = - FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M | - FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M | - FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M | -@@ -2135,40 +2185,40 @@ static int mpegts_configure_polarity(struct drxk_state *state) - dprintk(1, "\n"); - - /* Control selective inversion of output bits */ -- fec_oc_reg_ipr_invert &= (~(invert_data_mask)); -- if (state->m_invert_data) -- fec_oc_reg_ipr_invert |= invert_data_mask; -- fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MERR__M)); -- if (state->m_invert_err) -- fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MERR__M; -- fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); -- if (state->m_invert_str) -- fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MSTRT__M; -- fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); -- if (state->m_invert_val) -- fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MVAL__M; -- fec_oc_reg_ipr_invert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); -- if (state->m_invert_clk) -- fec_oc_reg_ipr_invert |= FEC_OC_IPR_INVERT_MCLK__M; -- -- return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert); -+ fecOcRegIprInvert &= (~(InvertDataMask)); -+ if (state->m_invertDATA == true) -+ fecOcRegIprInvert |= InvertDataMask; -+ fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M)); -+ if (state->m_invertERR == true) -+ fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M; -+ fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M)); -+ if (state->m_invertSTR == true) -+ fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M; -+ fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M)); -+ if (state->m_invertVAL == true) -+ fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M; -+ fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M)); -+ if (state->m_invertCLK == true) -+ fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M; -+ -+ return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert); - } - - #define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000 - --static int set_agc_rf(struct drxk_state *state, -- struct s_cfg_agc *p_agc_cfg, bool is_dtv) -+static int SetAgcRf(struct drxk_state *state, -+ struct SCfgAgc *pAgcCfg, bool isDTV) - { - int status = -EINVAL; - u16 data = 0; -- struct s_cfg_agc *p_if_agc_settings; -+ struct SCfgAgc *pIfAgcSettings; - - dprintk(1, "\n"); - -- if (p_agc_cfg == NULL) -+ if (pAgcCfg == NULL) - goto error; - -- switch (p_agc_cfg->ctrl_mode) { -+ switch (pAgcCfg->ctrlMode) { - case DRXK_AGC_CTRL_AUTO: - /* Enable RF AGC DAC */ - status = read16(state, IQM_AF_STDBY__A, &data); -@@ -2186,7 +2236,7 @@ static int set_agc_rf(struct drxk_state *state, - data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; - - /* Polarity */ -- if (state->m_rf_agc_pol) -+ if (state->m_RfAgcPol) - data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; - else - data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; -@@ -2200,7 +2250,7 @@ static int set_agc_rf(struct drxk_state *state, - goto error; - - data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M; -- data |= (~(p_agc_cfg->speed << -+ data |= (~(pAgcCfg->speed << - SCU_RAM_AGC_KI_RED_RAGC_RED__B) - & SCU_RAM_AGC_KI_RED_RAGC_RED__M); - -@@ -2208,35 +2258,30 @@ static int set_agc_rf(struct drxk_state *state, - if (status < 0) - goto error; - -- if (is_dvbt(state)) -- p_if_agc_settings = &state->m_dvbt_if_agc_cfg; -- else if (is_qam(state)) -- p_if_agc_settings = &state->m_qam_if_agc_cfg; -+ if (IsDVBT(state)) -+ pIfAgcSettings = &state->m_dvbtIfAgcCfg; -+ else if (IsQAM(state)) -+ pIfAgcSettings = &state->m_qamIfAgcCfg; - else -- p_if_agc_settings = &state->m_atv_if_agc_cfg; -- if (p_if_agc_settings == NULL) { -+ pIfAgcSettings = &state->m_atvIfAgcCfg; -+ if (pIfAgcSettings == NULL) { - status = -EINVAL; - goto error; - } - - /* Set TOP, only if IF-AGC is in AUTO mode */ -- if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) { -- status = write16(state, -- SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, -- p_agc_cfg->top); -+ if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO) -+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top); - if (status < 0) - goto error; -- } - - /* Cut-Off current */ -- status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, -- p_agc_cfg->cut_off_current); -+ status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent); - if (status < 0) - goto error; - - /* Max. output level */ -- status = write16(state, SCU_RAM_AGC_RF_MAX__A, -- p_agc_cfg->max_output_level); -+ status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel); - if (status < 0) - goto error; - -@@ -2257,7 +2302,7 @@ static int set_agc_rf(struct drxk_state *state, - if (status < 0) - goto error; - data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M; -- if (state->m_rf_agc_pol) -+ if (state->m_RfAgcPol) - data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M; - else - data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M; -@@ -2271,8 +2316,7 @@ static int set_agc_rf(struct drxk_state *state, - goto error; - - /* Write value to output pin */ -- status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, -- p_agc_cfg->output_level); -+ status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel); - if (status < 0) - goto error; - break; -@@ -2303,22 +2347,22 @@ static int set_agc_rf(struct drxk_state *state, - } - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - - #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000 - --static int set_agc_if(struct drxk_state *state, -- struct s_cfg_agc *p_agc_cfg, bool is_dtv) -+static int SetAgcIf(struct drxk_state *state, -+ struct SCfgAgc *pAgcCfg, bool isDTV) - { - u16 data = 0; - int status = 0; -- struct s_cfg_agc *p_rf_agc_settings; -+ struct SCfgAgc *pRfAgcSettings; - - dprintk(1, "\n"); - -- switch (p_agc_cfg->ctrl_mode) { -+ switch (pAgcCfg->ctrlMode) { - case DRXK_AGC_CTRL_AUTO: - - /* Enable IF AGC DAC */ -@@ -2338,7 +2382,7 @@ static int set_agc_if(struct drxk_state *state, - data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; - - /* Polarity */ -- if (state->m_if_agc_pol) -+ if (state->m_IfAgcPol) - data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; - else - data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; -@@ -2351,7 +2395,7 @@ static int set_agc_if(struct drxk_state *state, - if (status < 0) - goto error; - data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M; -- data |= (~(p_agc_cfg->speed << -+ data |= (~(pAgcCfg->speed << - SCU_RAM_AGC_KI_RED_IAGC_RED__B) - & SCU_RAM_AGC_KI_RED_IAGC_RED__M); - -@@ -2359,15 +2403,14 @@ static int set_agc_if(struct drxk_state *state, - if (status < 0) - goto error; - -- if (is_qam(state)) -- p_rf_agc_settings = &state->m_qam_rf_agc_cfg; -+ if (IsQAM(state)) -+ pRfAgcSettings = &state->m_qamRfAgcCfg; - else -- p_rf_agc_settings = &state->m_atv_rf_agc_cfg; -- if (p_rf_agc_settings == NULL) -+ pRfAgcSettings = &state->m_atvRfAgcCfg; -+ if (pRfAgcSettings == NULL) - return -1; - /* Restore TOP */ -- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, -- p_rf_agc_settings->top); -+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top); - if (status < 0) - goto error; - break; -@@ -2391,7 +2434,7 @@ static int set_agc_if(struct drxk_state *state, - data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M; - - /* Polarity */ -- if (state->m_if_agc_pol) -+ if (state->m_IfAgcPol) - data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M; - else - data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M; -@@ -2400,8 +2443,7 @@ static int set_agc_if(struct drxk_state *state, - goto error; - - /* Write value to output pin */ -- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, -- p_agc_cfg->output_level); -+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel); - if (status < 0) - goto error; - break; -@@ -2426,181 +2468,207 @@ static int set_agc_if(struct drxk_state *state, - if (status < 0) - goto error; - break; -- } /* switch (agcSettingsIf->ctrl_mode) */ -+ } /* switch (agcSettingsIf->ctrlMode) */ - - /* always set the top to support - configurations without if-loop */ -- status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top); -+ status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int get_qam_signal_to_noise(struct drxk_state *state, -- s32 *p_signal_to_noise) -+static int ReadIFAgc(struct drxk_state *state, u32 *pValue) -+{ -+ u16 agcDacLvl; -+ int status; -+ u16 Level = 0; -+ -+ dprintk(1, "\n"); -+ -+ status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl); -+ if (status < 0) { -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); -+ return status; -+ } -+ -+ *pValue = 0; -+ -+ if (agcDacLvl > DRXK_AGC_DAC_OFFSET) -+ Level = agcDacLvl - DRXK_AGC_DAC_OFFSET; -+ if (Level < 14000) -+ *pValue = (14000 - Level) / 4; -+ else -+ *pValue = 0; -+ -+ return status; -+} -+ -+static int GetQAMSignalToNoise(struct drxk_state *state, -+ s32 *pSignalToNoise) - { - int status = 0; -- u16 qam_sl_err_power = 0; /* accum. error between -+ u16 qamSlErrPower = 0; /* accum. error between - raw and sliced symbols */ -- u32 qam_sl_sig_power = 0; /* used for MER, depends of -+ u32 qamSlSigPower = 0; /* used for MER, depends of - QAM modulation */ -- u32 qam_sl_mer = 0; /* QAM MER */ -+ u32 qamSlMer = 0; /* QAM MER */ - - dprintk(1, "\n"); - - /* MER calculation */ - - /* get the register value needed for MER */ -- status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power); -+ status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower); - if (status < 0) { -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return -EINVAL; - } - - switch (state->props.modulation) { - case QAM_16: -- qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; -+ qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; - break; - case QAM_32: -- qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; -+ qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2; - break; - case QAM_64: -- qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; -+ qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2; - break; - case QAM_128: -- qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; -+ qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2; - break; - default: - case QAM_256: -- qam_sl_sig_power = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; -+ qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2; - break; - } - -- if (qam_sl_err_power > 0) { -- qam_sl_mer = log10times100(qam_sl_sig_power) - -- log10times100((u32) qam_sl_err_power); -+ if (qamSlErrPower > 0) { -+ qamSlMer = Log10Times100(qamSlSigPower) - -+ Log10Times100((u32) qamSlErrPower); - } -- *p_signal_to_noise = qam_sl_mer; -+ *pSignalToNoise = qamSlMer; - - return status; - } - --static int get_dvbt_signal_to_noise(struct drxk_state *state, -- s32 *p_signal_to_noise) -+static int GetDVBTSignalToNoise(struct drxk_state *state, -+ s32 *pSignalToNoise) - { - int status; -- u16 reg_data = 0; -- u32 eq_reg_td_sqr_err_i = 0; -- u32 eq_reg_td_sqr_err_q = 0; -- u16 eq_reg_td_sqr_err_exp = 0; -- u16 eq_reg_td_tps_pwr_ofs = 0; -- u16 eq_reg_td_req_smb_cnt = 0; -- u32 tps_cnt = 0; -- u32 sqr_err_iq = 0; -+ u16 regData = 0; -+ u32 EqRegTdSqrErrI = 0; -+ u32 EqRegTdSqrErrQ = 0; -+ u16 EqRegTdSqrErrExp = 0; -+ u16 EqRegTdTpsPwrOfs = 0; -+ u16 EqRegTdReqSmbCnt = 0; -+ u32 tpsCnt = 0; -+ u32 SqrErrIQ = 0; - u32 a = 0; - u32 b = 0; - u32 c = 0; -- u32 i_mer = 0; -- u16 transmission_params = 0; -+ u32 iMER = 0; -+ u16 transmissionParams = 0; - - dprintk(1, "\n"); - -- status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, -- &eq_reg_td_tps_pwr_ofs); -+ status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs); - if (status < 0) - goto error; -- status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, -- &eq_reg_td_req_smb_cnt); -+ status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt); - if (status < 0) - goto error; -- status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, -- &eq_reg_td_sqr_err_exp); -+ status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp); - if (status < 0) - goto error; -- status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, -- ®_data); -+ status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, ®Data); - if (status < 0) - goto error; - /* Extend SQR_ERR_I operational range */ -- eq_reg_td_sqr_err_i = (u32) reg_data; -- if ((eq_reg_td_sqr_err_exp > 11) && -- (eq_reg_td_sqr_err_i < 0x00000FFFUL)) { -- eq_reg_td_sqr_err_i += 0x00010000UL; -+ EqRegTdSqrErrI = (u32) regData; -+ if ((EqRegTdSqrErrExp > 11) && -+ (EqRegTdSqrErrI < 0x00000FFFUL)) { -+ EqRegTdSqrErrI += 0x00010000UL; - } -- status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data); -+ status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®Data); - if (status < 0) - goto error; - /* Extend SQR_ERR_Q operational range */ -- eq_reg_td_sqr_err_q = (u32) reg_data; -- if ((eq_reg_td_sqr_err_exp > 11) && -- (eq_reg_td_sqr_err_q < 0x00000FFFUL)) -- eq_reg_td_sqr_err_q += 0x00010000UL; -+ EqRegTdSqrErrQ = (u32) regData; -+ if ((EqRegTdSqrErrExp > 11) && -+ (EqRegTdSqrErrQ < 0x00000FFFUL)) -+ EqRegTdSqrErrQ += 0x00010000UL; - -- status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, -- &transmission_params); -+ status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams); - if (status < 0) - goto error; - - /* Check input data for MER */ - - /* MER calculation (in 0.1 dB) without math.h */ -- if ((eq_reg_td_tps_pwr_ofs == 0) || (eq_reg_td_req_smb_cnt == 0)) -- i_mer = 0; -- else if ((eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) == 0) { -+ if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0)) -+ iMER = 0; -+ else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) { - /* No error at all, this must be the HW reset value - * Apparently no first measurement yet - * Set MER to 0.0 */ -- i_mer = 0; -+ iMER = 0; - } else { -- sqr_err_iq = (eq_reg_td_sqr_err_i + eq_reg_td_sqr_err_q) << -- eq_reg_td_sqr_err_exp; -- if ((transmission_params & -+ SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) << -+ EqRegTdSqrErrExp; -+ if ((transmissionParams & - OFDM_SC_RA_RAM_OP_PARAM_MODE__M) - == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K) -- tps_cnt = 17; -+ tpsCnt = 17; - else -- tps_cnt = 68; -+ tpsCnt = 68; - - /* IMER = 100 * log10 (x) -- where x = (eq_reg_td_tps_pwr_ofs^2 * -- eq_reg_td_req_smb_cnt * tps_cnt)/sqr_err_iq -+ where x = (EqRegTdTpsPwrOfs^2 * -+ EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ - - => IMER = a + b -c -- where a = 100 * log10 (eq_reg_td_tps_pwr_ofs^2) -- b = 100 * log10 (eq_reg_td_req_smb_cnt * tps_cnt) -- c = 100 * log10 (sqr_err_iq) -+ where a = 100 * log10 (EqRegTdTpsPwrOfs^2) -+ b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt) -+ c = 100 * log10 (SqrErrIQ) - */ - - /* log(x) x = 9bits * 9bits->18 bits */ -- a = log10times100(eq_reg_td_tps_pwr_ofs * -- eq_reg_td_tps_pwr_ofs); -+ a = Log10Times100(EqRegTdTpsPwrOfs * -+ EqRegTdTpsPwrOfs); - /* log(x) x = 16bits * 7bits->23 bits */ -- b = log10times100(eq_reg_td_req_smb_cnt * tps_cnt); -+ b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt); - /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ -- c = log10times100(sqr_err_iq); -+ c = Log10Times100(SqrErrIQ); - -- i_mer = a + b - c; -+ iMER = a + b; -+ /* No negative MER, clip to zero */ -+ if (iMER > c) -+ iMER -= c; -+ else -+ iMER = 0; - } -- *p_signal_to_noise = i_mer; -+ *pSignalToNoise = iMER; - - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise) -+static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise) - { - dprintk(1, "\n"); - -- *p_signal_to_noise = 0; -- switch (state->m_operation_mode) { -+ *pSignalToNoise = 0; -+ switch (state->m_OperationMode) { - case OM_DVBT: -- return get_dvbt_signal_to_noise(state, p_signal_to_noise); -+ return GetDVBTSignalToNoise(state, pSignalToNoise); - case OM_QAM_ITU_A: - case OM_QAM_ITU_C: -- return get_qam_signal_to_noise(state, p_signal_to_noise); -+ return GetQAMSignalToNoise(state, pSignalToNoise); - default: - break; - } -@@ -2608,7 +2676,7 @@ static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise) - } - - #if 0 --static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality) -+static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality) - { - /* SNR Values for quasi errorfree reception rom Nordig 2.2 */ - int status = 0; -@@ -2633,104 +2701,102 @@ static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality) - 225, /* 64-QAM 7/8 */ - }; - -- *p_quality = 0; -+ *pQuality = 0; - - do { -- s32 signal_to_noise = 0; -- u16 constellation = 0; -- u16 code_rate = 0; -- u32 signal_to_noise_rel; -- u32 ber_quality; -+ s32 SignalToNoise = 0; -+ u16 Constellation = 0; -+ u16 CodeRate = 0; -+ u32 SignalToNoiseRel; -+ u32 BERQuality; - -- status = get_dvbt_signal_to_noise(state, &signal_to_noise); -+ status = GetDVBTSignalToNoise(state, &SignalToNoise); - if (status < 0) - break; -- status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, -- &constellation); -+ status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation); - if (status < 0) - break; -- constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; -+ Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M; - -- status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, -- &code_rate); -+ status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate); - if (status < 0) - break; -- code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; -+ CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M; - -- if (constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || -- code_rate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8) -+ if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM || -+ CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8) - break; -- signal_to_noise_rel = signal_to_noise - -- QE_SN[constellation * 5 + code_rate]; -- ber_quality = 100; -- -- if (signal_to_noise_rel < -70) -- *p_quality = 0; -- else if (signal_to_noise_rel < 30) -- *p_quality = ((signal_to_noise_rel + 70) * -- ber_quality) / 100; -+ SignalToNoiseRel = SignalToNoise - -+ QE_SN[Constellation * 5 + CodeRate]; -+ BERQuality = 100; -+ -+ if (SignalToNoiseRel < -70) -+ *pQuality = 0; -+ else if (SignalToNoiseRel < 30) -+ *pQuality = ((SignalToNoiseRel + 70) * -+ BERQuality) / 100; - else -- *p_quality = ber_quality; -+ *pQuality = BERQuality; - } while (0); - return 0; - }; - --static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality) -+static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality) - { - int status = 0; -- *p_quality = 0; -+ *pQuality = 0; - - dprintk(1, "\n"); - - do { -- u32 signal_to_noise = 0; -- u32 ber_quality = 100; -- u32 signal_to_noise_rel = 0; -+ u32 SignalToNoise = 0; -+ u32 BERQuality = 100; -+ u32 SignalToNoiseRel = 0; - -- status = get_qam_signal_to_noise(state, &signal_to_noise); -+ status = GetQAMSignalToNoise(state, &SignalToNoise); - if (status < 0) - break; - - switch (state->props.modulation) { - case QAM_16: -- signal_to_noise_rel = signal_to_noise - 200; -+ SignalToNoiseRel = SignalToNoise - 200; - break; - case QAM_32: -- signal_to_noise_rel = signal_to_noise - 230; -+ SignalToNoiseRel = SignalToNoise - 230; - break; /* Not in NorDig */ - case QAM_64: -- signal_to_noise_rel = signal_to_noise - 260; -+ SignalToNoiseRel = SignalToNoise - 260; - break; - case QAM_128: -- signal_to_noise_rel = signal_to_noise - 290; -+ SignalToNoiseRel = SignalToNoise - 290; - break; - default: - case QAM_256: -- signal_to_noise_rel = signal_to_noise - 320; -+ SignalToNoiseRel = SignalToNoise - 320; - break; - } - -- if (signal_to_noise_rel < -70) -- *p_quality = 0; -- else if (signal_to_noise_rel < 30) -- *p_quality = ((signal_to_noise_rel + 70) * -- ber_quality) / 100; -+ if (SignalToNoiseRel < -70) -+ *pQuality = 0; -+ else if (SignalToNoiseRel < 30) -+ *pQuality = ((SignalToNoiseRel + 70) * -+ BERQuality) / 100; - else -- *p_quality = ber_quality; -+ *pQuality = BERQuality; - } while (0); - - return status; - } - --static int get_quality(struct drxk_state *state, s32 *p_quality) -+static int GetQuality(struct drxk_state *state, s32 *pQuality) - { - dprintk(1, "\n"); - -- switch (state->m_operation_mode) { -+ switch (state->m_OperationMode) { - case OM_DVBT: -- return get_dvbt_quality(state, p_quality); -+ return GetDVBTQuality(state, pQuality); - case OM_QAM_ITU_A: -- return get_dvbc_quality(state, p_quality); -+ return GetDVBCQuality(state, pQuality); - default: - break; - } -@@ -2752,68 +2818,65 @@ static int get_quality(struct drxk_state *state, s32 *p_quality) - #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F) - #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF) - --static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge) -+static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge) - { - int status = -EINVAL; - - dprintk(1, "\n"); - -- if (state->m_drxk_state == DRXK_UNINITIALIZED) -- return 0; -- if (state->m_drxk_state == DRXK_POWERED_DOWN) -+ if (state->m_DrxkState == DRXK_UNINITIALIZED) -+ goto error; -+ if (state->m_DrxkState == DRXK_POWERED_DOWN) - goto error; - - if (state->no_i2c_bridge) - return 0; - -- status = write16(state, SIO_HI_RA_RAM_PAR_1__A, -- SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); -+ status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY); - if (status < 0) - goto error; -- if (b_enable_bridge) { -- status = write16(state, SIO_HI_RA_RAM_PAR_2__A, -- SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED); -+ if (bEnableBridge) { -+ status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED); - if (status < 0) - goto error; - } else { -- status = write16(state, SIO_HI_RA_RAM_PAR_2__A, -- SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN); -+ status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN); - if (status < 0) - goto error; - } - -- status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL); -+ status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0); - - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int set_pre_saw(struct drxk_state *state, -- struct s_cfg_pre_saw *p_pre_saw_cfg) -+static int SetPreSaw(struct drxk_state *state, -+ struct SCfgPreSaw *pPreSawCfg) - { - int status = -EINVAL; - - dprintk(1, "\n"); - -- if ((p_pre_saw_cfg == NULL) -- || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M)) -+ if ((pPreSawCfg == NULL) -+ || (pPreSawCfg->reference > IQM_AF_PDREF__M)) - goto error; - -- status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference); -+ status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int bl_direct_cmd(struct drxk_state *state, u32 target_addr, -- u16 rom_offset, u16 nr_of_elements, u32 time_out) -+static int BLDirectCmd(struct drxk_state *state, u32 targetAddr, -+ u16 romOffset, u16 nrOfElements, u32 timeOut) - { -- u16 bl_status = 0; -- u16 offset = (u16) ((target_addr >> 0) & 0x00FFFF); -- u16 blockbank = (u16) ((target_addr >> 16) & 0x000FFF); -+ u16 blStatus = 0; -+ u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF); -+ u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF); - int status; - unsigned long end; - -@@ -2829,44 +2892,44 @@ static int bl_direct_cmd(struct drxk_state *state, u32 target_addr, - status = write16(state, SIO_BL_TGT_ADDR__A, offset); - if (status < 0) - goto error; -- status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset); -+ status = write16(state, SIO_BL_SRC_ADDR__A, romOffset); - if (status < 0) - goto error; -- status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements); -+ status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements); - if (status < 0) - goto error; - status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON); - if (status < 0) - goto error; - -- end = jiffies + msecs_to_jiffies(time_out); -+ end = jiffies + msecs_to_jiffies(timeOut); - do { -- status = read16(state, SIO_BL_STATUS__A, &bl_status); -+ status = read16(state, SIO_BL_STATUS__A, &blStatus); - if (status < 0) - goto error; -- } while ((bl_status == 0x1) && time_is_after_jiffies(end)); -- if (bl_status == 0x1) { -- pr_err("SIO not ready\n"); -+ } while ((blStatus == 0x1) && time_is_after_jiffies(end)); -+ if (blStatus == 0x1) { -+ printk(KERN_ERR "drxk: SIO not ready\n"); - status = -EINVAL; - goto error2; - } - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - error2: - mutex_unlock(&state->mutex); - return status; - - } - --static int adc_sync_measurement(struct drxk_state *state, u16 *count) -+static int ADCSyncMeasurement(struct drxk_state *state, u16 *count) - { - u16 data = 0; - int status; - - dprintk(1, "\n"); - -- /* start measurement */ -+ /* Start measurement */ - status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE); - if (status < 0) - goto error; -@@ -2893,42 +2956,42 @@ static int adc_sync_measurement(struct drxk_state *state, u16 *count) - - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int adc_synchronization(struct drxk_state *state) -+static int ADCSynchronization(struct drxk_state *state) - { - u16 count = 0; - int status; - - dprintk(1, "\n"); - -- status = adc_sync_measurement(state, &count); -+ status = ADCSyncMeasurement(state, &count); - if (status < 0) - goto error; - - if (count == 1) { -- /* Try sampling on a different edge */ -- u16 clk_neg = 0; -+ /* Try sampling on a diffrent edge */ -+ u16 clkNeg = 0; - -- status = read16(state, IQM_AF_CLKNEG__A, &clk_neg); -+ status = read16(state, IQM_AF_CLKNEG__A, &clkNeg); - if (status < 0) - goto error; -- if ((clk_neg & IQM_AF_CLKNEG_CLKNEGDATA__M) == -+ if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) == - IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) { -- clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); -- clk_neg |= -+ clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); -+ clkNeg |= - IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG; - } else { -- clk_neg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); -- clk_neg |= -+ clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M)); -+ clkNeg |= - IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS; - } -- status = write16(state, IQM_AF_CLKNEG__A, clk_neg); -+ status = write16(state, IQM_AF_CLKNEG__A, clkNeg); - if (status < 0) - goto error; -- status = adc_sync_measurement(state, &count); -+ status = ADCSyncMeasurement(state, &count); - if (status < 0) - goto error; - } -@@ -2937,25 +3000,25 @@ static int adc_synchronization(struct drxk_state *state) - status = -EINVAL; - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int set_frequency_shifter(struct drxk_state *state, -- u16 intermediate_freqk_hz, -- s32 tuner_freq_offset, bool is_dtv) -+static int SetFrequencyShifter(struct drxk_state *state, -+ u16 intermediateFreqkHz, -+ s32 tunerFreqOffset, bool isDTV) - { -- bool select_pos_image = false; -- u32 rf_freq_residual = tuner_freq_offset; -- u32 fm_frequency_shift = 0; -- bool tuner_mirror = !state->m_b_mirror_freq_spect; -- u32 adc_freq; -- bool adc_flip; -+ bool selectPosImage = false; -+ u32 rfFreqResidual = tunerFreqOffset; -+ u32 fmFrequencyShift = 0; -+ bool tunerMirror = !state->m_bMirrorFreqSpect; -+ u32 adcFreq; -+ bool adcFlip; - int status; -- u32 if_freq_actual; -- u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3); -- u32 frequency_shift; -- bool image_to_select; -+ u32 ifFreqActual; -+ u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3); -+ u32 frequencyShift; -+ bool imageToSelect; - - dprintk(1, "\n"); - -@@ -2963,125 +3026,121 @@ static int set_frequency_shifter(struct drxk_state *state, - Program frequency shifter - No need to account for mirroring on RF - */ -- if (is_dtv) { -- if ((state->m_operation_mode == OM_QAM_ITU_A) || -- (state->m_operation_mode == OM_QAM_ITU_C) || -- (state->m_operation_mode == OM_DVBT)) -- select_pos_image = true; -+ if (isDTV) { -+ if ((state->m_OperationMode == OM_QAM_ITU_A) || -+ (state->m_OperationMode == OM_QAM_ITU_C) || -+ (state->m_OperationMode == OM_DVBT)) -+ selectPosImage = true; - else -- select_pos_image = false; -+ selectPosImage = false; - } -- if (tuner_mirror) -+ if (tunerMirror) - /* tuner doesn't mirror */ -- if_freq_actual = intermediate_freqk_hz + -- rf_freq_residual + fm_frequency_shift; -+ ifFreqActual = intermediateFreqkHz + -+ rfFreqResidual + fmFrequencyShift; - else - /* tuner mirrors */ -- if_freq_actual = intermediate_freqk_hz - -- rf_freq_residual - fm_frequency_shift; -- if (if_freq_actual > sampling_frequency / 2) { -+ ifFreqActual = intermediateFreqkHz - -+ rfFreqResidual - fmFrequencyShift; -+ if (ifFreqActual > samplingFrequency / 2) { - /* adc mirrors */ -- adc_freq = sampling_frequency - if_freq_actual; -- adc_flip = true; -+ adcFreq = samplingFrequency - ifFreqActual; -+ adcFlip = true; - } else { - /* adc doesn't mirror */ -- adc_freq = if_freq_actual; -- adc_flip = false; -+ adcFreq = ifFreqActual; -+ adcFlip = false; - } - -- frequency_shift = adc_freq; -- image_to_select = state->m_rfmirror ^ tuner_mirror ^ -- adc_flip ^ select_pos_image; -- state->m_iqm_fs_rate_ofs = -- Frac28a((frequency_shift), sampling_frequency); -+ frequencyShift = adcFreq; -+ imageToSelect = state->m_rfmirror ^ tunerMirror ^ -+ adcFlip ^ selectPosImage; -+ state->m_IqmFsRateOfs = -+ Frac28a((frequencyShift), samplingFrequency); - -- if (image_to_select) -- state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1; -+ if (imageToSelect) -+ state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1; - - /* Program frequency shifter with tuner offset compensation */ -- /* frequency_shift += tuner_freq_offset; TODO */ -+ /* frequencyShift += tunerFreqOffset; TODO */ - status = write32(state, IQM_FS_RATE_OFS_LO__A, -- state->m_iqm_fs_rate_ofs); -+ state->m_IqmFsRateOfs); - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int init_agc(struct drxk_state *state, bool is_dtv) -+static int InitAGC(struct drxk_state *state, bool isDTV) - { -- u16 ingain_tgt = 0; -- u16 ingain_tgt_min = 0; -- u16 ingain_tgt_max = 0; -- u16 clp_cyclen = 0; -- u16 clp_sum_min = 0; -- u16 clp_dir_to = 0; -- u16 sns_sum_min = 0; -- u16 sns_sum_max = 0; -- u16 clp_sum_max = 0; -- u16 sns_dir_to = 0; -- u16 ki_innergain_min = 0; -- u16 if_iaccu_hi_tgt = 0; -- u16 if_iaccu_hi_tgt_min = 0; -- u16 if_iaccu_hi_tgt_max = 0; -+ u16 ingainTgt = 0; -+ u16 ingainTgtMin = 0; -+ u16 ingainTgtMax = 0; -+ u16 clpCyclen = 0; -+ u16 clpSumMin = 0; -+ u16 clpDirTo = 0; -+ u16 snsSumMin = 0; -+ u16 snsSumMax = 0; -+ u16 clpSumMax = 0; -+ u16 snsDirTo = 0; -+ u16 kiInnergainMin = 0; -+ u16 ifIaccuHiTgt = 0; -+ u16 ifIaccuHiTgtMin = 0; -+ u16 ifIaccuHiTgtMax = 0; - u16 data = 0; -- u16 fast_clp_ctrl_delay = 0; -- u16 clp_ctrl_mode = 0; -+ u16 fastClpCtrlDelay = 0; -+ u16 clpCtrlMode = 0; - int status = 0; - - dprintk(1, "\n"); - - /* Common settings */ -- sns_sum_max = 1023; -- if_iaccu_hi_tgt_min = 2047; -- clp_cyclen = 500; -- clp_sum_max = 1023; -+ snsSumMax = 1023; -+ ifIaccuHiTgtMin = 2047; -+ clpCyclen = 500; -+ clpSumMax = 1023; - - /* AGCInit() not available for DVBT; init done in microcode */ -- if (!is_qam(state)) { -- pr_err("%s: mode %d is not DVB-C\n", -- __func__, state->m_operation_mode); -+ if (!IsQAM(state)) { -+ printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode); - return -EINVAL; - } - - /* FIXME: Analog TV AGC require different settings */ - - /* Standard specific settings */ -- clp_sum_min = 8; -- clp_dir_to = (u16) -9; -- clp_ctrl_mode = 0; -- sns_sum_min = 8; -- sns_dir_to = (u16) -9; -- ki_innergain_min = (u16) -1030; -- if_iaccu_hi_tgt_max = 0x2380; -- if_iaccu_hi_tgt = 0x2380; -- ingain_tgt_min = 0x0511; -- ingain_tgt = 0x0511; -- ingain_tgt_max = 5119; -- fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay; -+ clpSumMin = 8; -+ clpDirTo = (u16) -9; -+ clpCtrlMode = 0; -+ snsSumMin = 8; -+ snsDirTo = (u16) -9; -+ kiInnergainMin = (u16) -1030; -+ ifIaccuHiTgtMax = 0x2380; -+ ifIaccuHiTgt = 0x2380; -+ ingainTgtMin = 0x0511; -+ ingainTgt = 0x0511; -+ ingainTgtMax = 5119; -+ fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay; - -- status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, -- fast_clp_ctrl_delay); -+ status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay); - if (status < 0) - goto error; - -- status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode); -+ status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode); - if (status < 0) - goto error; -- status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt); -+ status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt); - if (status < 0) - goto error; -- status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min); -+ status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin); - if (status < 0) - goto error; -- status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max); -+ status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax); - if (status < 0) - goto error; -- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, -- if_iaccu_hi_tgt_min); -+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin); - if (status < 0) - goto error; -- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, -- if_iaccu_hi_tgt_max); -+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax); - if (status < 0) - goto error; - status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0); -@@ -3096,22 +3155,20 @@ static int init_agc(struct drxk_state *state, bool is_dtv) - status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0); - if (status < 0) - goto error; -- status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max); -+ status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax); - if (status < 0) - goto error; -- status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max); -+ status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax); - if (status < 0) - goto error; - -- status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, -- ki_innergain_min); -+ status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin); - if (status < 0) - goto error; -- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, -- if_iaccu_hi_tgt); -+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt); - if (status < 0) - goto error; -- status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen); -+ status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen); - if (status < 0) - goto error; - -@@ -3128,16 +3185,16 @@ static int init_agc(struct drxk_state *state, bool is_dtv) - status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20); - if (status < 0) - goto error; -- status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min); -+ status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin); - if (status < 0) - goto error; -- status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min); -+ status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin); - if (status < 0) - goto error; -- status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to); -+ status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo); - if (status < 0) - goto error; -- status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to); -+ status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo); - if (status < 0) - goto error; - status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff); -@@ -3197,39 +3254,38 @@ static int init_agc(struct drxk_state *state, bool is_dtv) - status = write16(state, SCU_RAM_AGC_KI__A, data); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err) -+static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr) - { - int status; - - dprintk(1, "\n"); -- if (packet_err == NULL) -+ if (packetErr == NULL) - status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); - else -- status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, -- packet_err); -+ status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr); - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int dvbt_sc_command(struct drxk_state *state, -+static int DVBTScCommand(struct drxk_state *state, - u16 cmd, u16 subcmd, - u16 param0, u16 param1, u16 param2, - u16 param3, u16 param4) - { -- u16 cur_cmd = 0; -- u16 err_code = 0; -- u16 retry_cnt = 0; -- u16 sc_exec = 0; -+ u16 curCmd = 0; -+ u16 errCode = 0; -+ u16 retryCnt = 0; -+ u16 scExec = 0; - int status; - - dprintk(1, "\n"); -- status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec); -- if (sc_exec != 1) { -+ status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec); -+ if (scExec != 1) { - /* SC is not running */ - status = -EINVAL; - } -@@ -3237,13 +3293,13 @@ static int dvbt_sc_command(struct drxk_state *state, - goto error; - - /* Wait until sc is ready to receive command */ -- retry_cnt = 0; -+ retryCnt = 0; - do { -- usleep_range(1000, 2000); -- status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd); -- retry_cnt++; -- } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES)); -- if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0)) -+ msleep(1); -+ status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); -+ retryCnt++; -+ } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); -+ if (retryCnt >= DRXK_MAX_RETRIES && (status < 0)) - goto error; - - /* Write sub-command */ -@@ -3289,25 +3345,25 @@ static int dvbt_sc_command(struct drxk_state *state, - goto error; - - /* Wait until sc is ready processing command */ -- retry_cnt = 0; -+ retryCnt = 0; - do { -- usleep_range(1000, 2000); -- status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd); -- retry_cnt++; -- } while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES)); -- if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0)) -+ msleep(1); -+ status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd); -+ retryCnt++; -+ } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES)); -+ if (retryCnt >= DRXK_MAX_RETRIES && (status < 0)) - goto error; - - /* Check for illegal cmd */ -- status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code); -- if (err_code == 0xFFFF) { -+ status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode); -+ if (errCode == 0xFFFF) { - /* illegal command */ - status = -EINVAL; - } - if (status < 0) - goto error; - -- /* Retrieve results parameters from SC */ -+ /* Retreive results parameters from SC */ - switch (cmd) { - /* All commands yielding 5 results */ - /* All commands yielding 4 results */ -@@ -3332,44 +3388,44 @@ static int dvbt_sc_command(struct drxk_state *state, - } /* switch (cmd->cmd) */ - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int power_up_dvbt(struct drxk_state *state) -+static int PowerUpDVBT(struct drxk_state *state) - { -- enum drx_power_mode power_mode = DRX_POWER_UP; -+ enum DRXPowerMode powerMode = DRX_POWER_UP; - int status; - - dprintk(1, "\n"); -- status = ctrl_power_mode(state, &power_mode); -+ status = CtrlPowerMode(state, &powerMode); - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled) -+static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled) - { - int status; - - dprintk(1, "\n"); -- if (*enabled) -+ if (*enabled == true) - status = write16(state, IQM_CF_BYPASSDET__A, 0); - else - status = write16(state, IQM_CF_BYPASSDET__A, 1); - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - - #define DEFAULT_FR_THRES_8K 4000 --static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled) -+static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled) - { - - int status; - - dprintk(1, "\n"); -- if (*enabled) { -+ if (*enabled == true) { - /* write mask to 1 */ - status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, - DEFAULT_FR_THRES_8K); -@@ -3378,13 +3434,13 @@ static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled) - status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0); - } - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - - return status; - } - --static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state, -- struct drxk_cfg_dvbt_echo_thres_t *echo_thres) -+static int DVBTCtrlSetEchoThreshold(struct drxk_state *state, -+ struct DRXKCfgDvbtEchoThres_t *echoThres) - { - u16 data = 0; - int status; -@@ -3394,16 +3450,16 @@ static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state, - if (status < 0) - goto error; - -- switch (echo_thres->fft_mode) { -+ switch (echoThres->fftMode) { - case DRX_FFTMODE_2K: - data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M; -- data |= ((echo_thres->threshold << -+ data |= ((echoThres->threshold << - OFDM_SC_RA_RAM_ECHO_THRES_2K__B) - & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M)); - break; - case DRX_FFTMODE_8K: - data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M; -- data |= ((echo_thres->threshold << -+ data |= ((echoThres->threshold << - OFDM_SC_RA_RAM_ECHO_THRES_8K__B) - & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M)); - break; -@@ -3414,12 +3470,12 @@ static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state, - status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state, -- enum drxk_cfg_dvbt_sqi_speed *speed) -+static int DVBTCtrlSetSqiSpeed(struct drxk_state *state, -+ enum DRXKCfgDvbtSqiSpeed *speed) - { - int status = -EINVAL; - -@@ -3437,7 +3493,7 @@ static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state, - (u16) *speed); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - -@@ -3451,33 +3507,32 @@ error: - * Called in DVBTSetStandard - * - */ --static int dvbt_activate_presets(struct drxk_state *state) -+static int DVBTActivatePresets(struct drxk_state *state) - { - int status; - bool setincenable = false; - bool setfrenable = true; - -- struct drxk_cfg_dvbt_echo_thres_t echo_thres2k = { 0, DRX_FFTMODE_2K }; -- struct drxk_cfg_dvbt_echo_thres_t echo_thres8k = { 0, DRX_FFTMODE_8K }; -+ struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K }; -+ struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K }; - - dprintk(1, "\n"); -- status = dvbt_ctrl_set_inc_enable(state, &setincenable); -+ status = DVBTCtrlSetIncEnable(state, &setincenable); - if (status < 0) - goto error; -- status = dvbt_ctrl_set_fr_enable(state, &setfrenable); -+ status = DVBTCtrlSetFrEnable(state, &setfrenable); - if (status < 0) - goto error; -- status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k); -+ status = DVBTCtrlSetEchoThreshold(state, &echoThres2k); - if (status < 0) - goto error; -- status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k); -+ status = DVBTCtrlSetEchoThreshold(state, &echoThres8k); - if (status < 0) - goto error; -- status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, -- state->m_dvbt_if_agc_cfg.ingain_tgt_max); -+ status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - -@@ -3491,30 +3546,25 @@ error: - * For ROM code channel filter taps are loaded from the bootloader. For microcode - * the DVB-T taps from the drxk_filters.h are used. - */ --static int set_dvbt_standard(struct drxk_state *state, -- enum operation_mode o_mode) -+static int SetDVBTStandard(struct drxk_state *state, -+ enum OperationMode oMode) - { -- u16 cmd_result = 0; -+ u16 cmdResult = 0; - u16 data = 0; - int status; - - dprintk(1, "\n"); - -- power_up_dvbt(state); -+ PowerUpDVBT(state); - /* added antenna switch */ -- switch_antenna_to_dvbt(state); -+ SwitchAntennaToDVBT(state); - /* send OFDM reset command */ -- status = scu_command(state, -- SCU_RAM_COMMAND_STANDARD_OFDM -- | SCU_RAM_COMMAND_CMD_DEMOD_RESET, -- 0, NULL, 1, &cmd_result); -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult); - if (status < 0) - goto error; - - /* send OFDM setenv command */ -- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM -- | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, -- 0, NULL, 1, &cmd_result); -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult); - if (status < 0) - goto error; - -@@ -3546,7 +3596,7 @@ static int set_dvbt_standard(struct drxk_state *state, - status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC); - if (status < 0) - goto error; -- status = set_iqm_af(state, true); -+ status = SetIqmAf(state, true); - if (status < 0) - goto error; - -@@ -3568,7 +3618,7 @@ static int set_dvbt_standard(struct drxk_state *state, - status = write16(state, IQM_RC_STRETCH__A, 16); - if (status < 0) - goto error; -- status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */ -+ status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */ - if (status < 0) - goto error; - status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */ -@@ -3589,8 +3639,7 @@ static int set_dvbt_standard(struct drxk_state *state, - if (status < 0) - goto error; - -- status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, -- DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); -+ status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); - if (status < 0) - goto error; - -@@ -3609,10 +3658,10 @@ static int set_dvbt_standard(struct drxk_state *state, - goto error; - - /* IQM will not be reset from here, sync ADC and update/init AGC */ -- status = adc_synchronization(state); -+ status = ADCSynchronization(state); - if (status < 0) - goto error; -- status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg); -+ status = SetPreSaw(state, &state->m_dvbtPreSawCfg); - if (status < 0) - goto error; - -@@ -3621,10 +3670,10 @@ static int set_dvbt_standard(struct drxk_state *state, - if (status < 0) - goto error; - -- status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true); -+ status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true); - if (status < 0) - goto error; -- status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true); -+ status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true); - if (status < 0) - goto error; - -@@ -3642,10 +3691,9 @@ static int set_dvbt_standard(struct drxk_state *state, - if (status < 0) - goto error; - -- if (!state->m_drxk_a3_rom_code) { -- /* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay */ -- status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, -- state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay); -+ if (!state->m_DRXK_A3_ROM_CODE) { -+ /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */ -+ status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay); - if (status < 0) - goto error; - } -@@ -3680,43 +3728,41 @@ static int set_dvbt_standard(struct drxk_state *state, - goto error; - - /* Setup MPEG bus */ -- status = mpegts_dto_setup(state, OM_DVBT); -+ status = MPEGTSDtoSetup(state, OM_DVBT); - if (status < 0) - goto error; - /* Set DVBT Presets */ -- status = dvbt_activate_presets(state); -+ status = DVBTActivatePresets(state); - if (status < 0) - goto error; - - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - - /*============================================================================*/ - /** --* \brief start dvbt demodulating for channel. -+* \brief Start dvbt demodulating for channel. - * \param demod instance of demodulator. - * \return DRXStatus_t. - */ --static int dvbt_start(struct drxk_state *state) -+static int DVBTStart(struct drxk_state *state) - { - u16 param1; - int status; -- /* drxk_ofdm_sc_cmd_t scCmd; */ -+ /* DRXKOfdmScCmd_t scCmd; */ - - dprintk(1, "\n"); -- /* start correct processes to get in lock */ -+ /* Start correct processes to get in lock */ - /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */ - param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN; -- status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, -- OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, -- 0, 0, 0); -+ status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0); - if (status < 0) - goto error; -- /* start FEC OC */ -- status = mpegts_start(state); -+ /* Start FEC OC */ -+ status = MPEGTSStart(state); - if (status < 0) - goto error; - status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); -@@ -3724,7 +3770,7 @@ static int dvbt_start(struct drxk_state *state) - goto error; - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - -@@ -3737,23 +3783,20 @@ error: - * \return DRXStatus_t. - * // original DVBTSetChannel() - */ --static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, -- s32 tuner_freq_offset) -+static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, -+ s32 tunerFreqOffset) - { -- u16 cmd_result = 0; -- u16 transmission_params = 0; -- u16 operation_mode = 0; -- u32 iqm_rc_rate_ofs = 0; -+ u16 cmdResult = 0; -+ u16 transmissionParams = 0; -+ u16 operationMode = 0; -+ u32 iqmRcRateOfs = 0; - u32 bandwidth = 0; - u16 param1; - int status; - -- dprintk(1, "IF =%d, TFO = %d\n", -- intermediate_freqk_hz, tuner_freq_offset); -+ dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset); - -- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM -- | SCU_RAM_COMMAND_CMD_DEMOD_STOP, -- 0, NULL, 1, &cmd_result); -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult); - if (status < 0) - goto error; - -@@ -3776,19 +3819,19 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, - if (status < 0) - goto error; - -- /*== Write channel settings to device ================================*/ -+ /*== Write channel settings to device =====================================*/ - - /* mode */ - switch (state->props.transmission_mode) { - case TRANSMISSION_MODE_AUTO: - default: -- operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; -+ operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; - /* fall through , try first guess DRX_FFTMODE_8K */ - case TRANSMISSION_MODE_8K: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K; - break; - case TRANSMISSION_MODE_2K: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K; - break; - } - -@@ -3796,19 +3839,19 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, - switch (state->props.guard_interval) { - default: - case GUARD_INTERVAL_AUTO: -- operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; -+ operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; - /* fall through , try first guess DRX_GUARD_1DIV4 */ - case GUARD_INTERVAL_1_4: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4; - break; - case GUARD_INTERVAL_1_32: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32; - break; - case GUARD_INTERVAL_1_16: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16; - break; - case GUARD_INTERVAL_1_8: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8; - break; - } - -@@ -3817,18 +3860,18 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, - case HIERARCHY_AUTO: - case HIERARCHY_NONE: - default: -- operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; -+ operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M; - /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */ -- /* transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */ -+ /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */ - /* break; */ - case HIERARCHY_1: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1; - break; - case HIERARCHY_2: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2; - break; - case HIERARCHY_4: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4; - break; - } - -@@ -3837,30 +3880,30 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, - switch (state->props.modulation) { - case QAM_AUTO: - default: -- operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; -+ operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; - /* fall through , try first guess DRX_CONSTELLATION_QAM64 */ - case QAM_64: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64; - break; - case QPSK: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK; - break; - case QAM_16: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16; - break; - } - #if 0 -- /* No hierarchical channels support in BDA */ -+ /* No hierachical channels support in BDA */ - /* Priority (only for hierarchical channels) */ - switch (channel->priority) { - case DRX_PRIORITY_LOW: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; -- WR16(dev_addr, OFDM_EC_SB_PRIOR__A, -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO; -+ WR16(devAddr, OFDM_EC_SB_PRIOR__A, - OFDM_EC_SB_PRIOR_LO); - break; - case DRX_PRIORITY_HIGH: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; -- WR16(dev_addr, OFDM_EC_SB_PRIOR__A, -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; -+ WR16(devAddr, OFDM_EC_SB_PRIOR__A, - OFDM_EC_SB_PRIOR_HI)); - break; - case DRX_PRIORITY_UNKNOWN: /* fall through */ -@@ -3870,7 +3913,7 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, - } - #else - /* Set Priorty high */ -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI; - status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI); - if (status < 0) - goto error; -@@ -3880,111 +3923,90 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, - switch (state->props.code_rate_HP) { - case FEC_AUTO: - default: -- operation_mode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; -+ operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; - /* fall through , try first guess DRX_CODERATE_2DIV3 */ - case FEC_2_3: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3; - break; - case FEC_1_2: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2; - break; - case FEC_3_4: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4; - break; - case FEC_5_6: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6; - break; - case FEC_7_8: -- transmission_params |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8; -+ transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8; - break; - } - -- /* -- * SAW filter selection: normaly not necesarry, but if wanted -- * the application can select a SAW filter via the driver by -- * using UIOs -- */ -- -+ /* SAW filter selection: normaly not necesarry, but if wanted -+ the application can select a SAW filter via the driver by using UIOs */ - /* First determine real bandwidth (Hz) */ - /* Also set delay for impulse noise cruncher */ -- /* -- * Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is -- * changed by SC for fix for some 8K,1/8 guard but is restored by -- * InitEC and ResetEC functions -- */ -+ /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed -+ by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC -+ functions */ - switch (state->props.bandwidth_hz) { - case 0: - state->props.bandwidth_hz = 8000000; - /* fall though */ - case 8000000: - bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; -- status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, -- 3052); -+ status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052); - if (status < 0) - goto error; - /* cochannel protection for PAL 8 MHz */ -- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, -- 7); -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7); - if (status < 0) - goto error; -- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, -- 7); -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7); - if (status < 0) - goto error; -- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, -- 7); -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7); - if (status < 0) - goto error; -- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, -- 1); -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); - if (status < 0) - goto error; - break; - case 7000000: - bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; -- status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, -- 3491); -+ status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491); - if (status < 0) - goto error; - /* cochannel protection for PAL 7 MHz */ -- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, -- 8); -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8); - if (status < 0) - goto error; -- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, -- 8); -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8); - if (status < 0) - goto error; -- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, -- 4); -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4); - if (status < 0) - goto error; -- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, -- 1); -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); - if (status < 0) - goto error; - break; - case 6000000: - bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; -- status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, -- 4073); -+ status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073); - if (status < 0) - goto error; - /* cochannel protection for NTSC 6 MHz */ -- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, -- 19); -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19); - if (status < 0) - goto error; -- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, -- 19); -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19); - if (status < 0) - goto error; -- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, -- 14); -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14); - if (status < 0) - goto error; -- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, -- 1); -+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1); - if (status < 0) - goto error; - break; -@@ -3993,50 +4015,46 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, - goto error; - } - -- if (iqm_rc_rate_ofs == 0) { -+ if (iqmRcRateOfs == 0) { - /* Now compute IQM_RC_RATE_OFS - (((SysFreq/BandWidth)/2)/2) -1) * 2^23) - => - ((SysFreq / BandWidth) * (2^21)) - (2^23) - */ - /* (SysFreq / BandWidth) * (2^28) */ -- /* -- * assert (MAX(sysClk)/MIN(bandwidth) < 16) -- * => assert(MAX(sysClk) < 16*MIN(bandwidth)) -- * => assert(109714272 > 48000000) = true -- * so Frac 28 can be used -- */ -- iqm_rc_rate_ofs = Frac28a((u32) -- ((state->m_sys_clock_freq * -+ /* assert (MAX(sysClk)/MIN(bandwidth) < 16) -+ => assert(MAX(sysClk) < 16*MIN(bandwidth)) -+ => assert(109714272 > 48000000) = true so Frac 28 can be used */ -+ iqmRcRateOfs = Frac28a((u32) -+ ((state->m_sysClockFreq * - 1000) / 3), bandwidth); -- /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ -- if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40) -- iqm_rc_rate_ofs += 0x80L; -- iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7; -+ /* (SysFreq / BandWidth) * (2^21), rounding before truncating */ -+ if ((iqmRcRateOfs & 0x7fL) >= 0x40) -+ iqmRcRateOfs += 0x80L; -+ iqmRcRateOfs = iqmRcRateOfs >> 7; - /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ -- iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23); -+ iqmRcRateOfs = iqmRcRateOfs - (1 << 23); - } - -- iqm_rc_rate_ofs &= -+ iqmRcRateOfs &= - ((((u32) IQM_RC_RATE_OFS_HI__M) << - IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M); -- status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs); -+ status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs); - if (status < 0) - goto error; - - /* Bandwidth setting done */ - - #if 0 -- status = dvbt_set_frequency_shift(demod, channel, tuner_offset); -+ status = DVBTSetFrequencyShift(demod, channel, tunerOffset); - if (status < 0) - goto error; - #endif -- status = set_frequency_shifter(state, intermediate_freqk_hz, -- tuner_freq_offset, true); -+ status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true); - if (status < 0) - goto error; - -- /*== start SC, write channel settings to SC ==========================*/ -+ /*== Start SC, write channel settings to SC ===============================*/ - - /* Activate SCU to enable SCU commands */ - status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); -@@ -4052,9 +4070,7 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, - goto error; - - -- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM -- | SCU_RAM_COMMAND_CMD_DEMOD_START, -- 0, NULL, 1, &cmd_result); -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult); - if (status < 0) - goto error; - -@@ -4064,16 +4080,16 @@ static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz, - OFDM_SC_RA_RAM_OP_AUTO_CONST__M | - OFDM_SC_RA_RAM_OP_AUTO_HIER__M | - OFDM_SC_RA_RAM_OP_AUTO_RATE__M); -- status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM, -- 0, transmission_params, param1, 0, 0, 0); -+ status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM, -+ 0, transmissionParams, param1, 0, 0, 0); - if (status < 0) - goto error; - -- if (!state->m_drxk_a3_rom_code) -- status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed); -+ if (!state->m_DRXK_A3_ROM_CODE) -+ status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - - return status; - } -@@ -4082,13 +4098,13 @@ error: - /*============================================================================*/ - - /** --* \brief Retrieve lock status . -+* \brief Retreive lock status . - * \param demod Pointer to demodulator instance. - * \param lockStat Pointer to lock status structure. - * \return DRXStatus_t. - * - */ --static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status) -+static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus) - { - int status; - const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M | -@@ -4096,58 +4112,58 @@ static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status) - const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M); - const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M; - -- u16 sc_ra_ram_lock = 0; -- u16 sc_comm_exec = 0; -+ u16 ScRaRamLock = 0; -+ u16 ScCommExec = 0; - - dprintk(1, "\n"); - -- *p_lock_status = NOT_LOCKED; -+ *pLockStatus = NOT_LOCKED; - /* driver 0.9.0 */ - /* Check if SC is running */ -- status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec); -+ status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec); - if (status < 0) - goto end; -- if (sc_comm_exec == OFDM_SC_COMM_EXEC_STOP) -+ if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) - goto end; - -- status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock); -+ status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock); - if (status < 0) - goto end; - -- if ((sc_ra_ram_lock & mpeg_lock_mask) == mpeg_lock_mask) -- *p_lock_status = MPEG_LOCK; -- else if ((sc_ra_ram_lock & fec_lock_mask) == fec_lock_mask) -- *p_lock_status = FEC_LOCK; -- else if ((sc_ra_ram_lock & demod_lock_mask) == demod_lock_mask) -- *p_lock_status = DEMOD_LOCK; -- else if (sc_ra_ram_lock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) -- *p_lock_status = NEVER_LOCK; -+ if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) -+ *pLockStatus = MPEG_LOCK; -+ else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask) -+ *pLockStatus = FEC_LOCK; -+ else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask) -+ *pLockStatus = DEMOD_LOCK; -+ else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M) -+ *pLockStatus = NEVER_LOCK; - end: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - - return status; - } - --static int power_up_qam(struct drxk_state *state) -+static int PowerUpQAM(struct drxk_state *state) - { -- enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM; -+ enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM; - int status; - - dprintk(1, "\n"); -- status = ctrl_power_mode(state, &power_mode); -+ status = CtrlPowerMode(state, &powerMode); - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - - return status; - } - - - /** Power Down QAM */ --static int power_down_qam(struct drxk_state *state) -+static int PowerDownQAM(struct drxk_state *state) - { - u16 data = 0; -- u16 cmd_result; -+ u16 cmdResult; - int status = 0; - - dprintk(1, "\n"); -@@ -4163,18 +4179,16 @@ static int power_down_qam(struct drxk_state *state) - status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP); - if (status < 0) - goto error; -- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM -- | SCU_RAM_COMMAND_CMD_DEMOD_STOP, -- 0, NULL, 1, &cmd_result); -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult); - if (status < 0) - goto error; - } - /* powerdown AFE */ -- status = set_iqm_af(state, false); -+ status = SetIqmAf(state, false); - - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - - return status; - } -@@ -4192,20 +4206,20 @@ error: - * The implementation does not check this. - * - */ --static int set_qam_measurement(struct drxk_state *state, -- enum e_drxk_constellation modulation, -- u32 symbol_rate) -+static int SetQAMMeasurement(struct drxk_state *state, -+ enum EDrxkConstellation modulation, -+ u32 symbolRate) - { -- u32 fec_bits_desired = 0; /* BER accounting period */ -- u32 fec_rs_period_total = 0; /* Total period */ -- u16 fec_rs_prescale = 0; /* ReedSolomon Measurement Prescale */ -- u16 fec_rs_period = 0; /* Value for corresponding I2C register */ -+ u32 fecBitsDesired = 0; /* BER accounting period */ -+ u32 fecRsPeriodTotal = 0; /* Total period */ -+ u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */ -+ u16 fecRsPeriod = 0; /* Value for corresponding I2C register */ - int status = 0; - - dprintk(1, "\n"); - -- fec_rs_prescale = 1; -- /* fec_bits_desired = symbol_rate [kHz] * -+ fecRsPrescale = 1; -+ /* fecBitsDesired = symbolRate [kHz] * - FrameLenght [ms] * - (modulation + 1) * - SyncLoss (== 1) * -@@ -4213,19 +4227,19 @@ static int set_qam_measurement(struct drxk_state *state, - */ - switch (modulation) { - case DRX_CONSTELLATION_QAM16: -- fec_bits_desired = 4 * symbol_rate; -+ fecBitsDesired = 4 * symbolRate; - break; - case DRX_CONSTELLATION_QAM32: -- fec_bits_desired = 5 * symbol_rate; -+ fecBitsDesired = 5 * symbolRate; - break; - case DRX_CONSTELLATION_QAM64: -- fec_bits_desired = 6 * symbol_rate; -+ fecBitsDesired = 6 * symbolRate; - break; - case DRX_CONSTELLATION_QAM128: -- fec_bits_desired = 7 * symbol_rate; -+ fecBitsDesired = 7 * symbolRate; - break; - case DRX_CONSTELLATION_QAM256: -- fec_bits_desired = 8 * symbol_rate; -+ fecBitsDesired = 8 * symbolRate; - break; - default: - status = -EINVAL; -@@ -4233,41 +4247,40 @@ static int set_qam_measurement(struct drxk_state *state, - if (status < 0) - goto error; - -- fec_bits_desired /= 1000; /* symbol_rate [Hz] -> symbol_rate [kHz] */ -- fec_bits_desired *= 500; /* meas. period [ms] */ -+ fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */ -+ fecBitsDesired *= 500; /* meas. period [ms] */ - - /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */ -- /* fec_rs_period_total = fec_bits_desired / 1632 */ -- fec_rs_period_total = (fec_bits_desired / 1632UL) + 1; /* roughly ceil */ -+ /* fecRsPeriodTotal = fecBitsDesired / 1632 */ -+ fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */ - -- /* fec_rs_period_total = fec_rs_prescale * fec_rs_period */ -- fec_rs_prescale = 1 + (u16) (fec_rs_period_total >> 16); -- if (fec_rs_prescale == 0) { -+ /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */ -+ fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16); -+ if (fecRsPrescale == 0) { - /* Divide by zero (though impossible) */ - status = -EINVAL; - if (status < 0) - goto error; - } -- fec_rs_period = -- ((u16) fec_rs_period_total + -- (fec_rs_prescale >> 1)) / fec_rs_prescale; -+ fecRsPeriod = -+ ((u16) fecRsPeriodTotal + -+ (fecRsPrescale >> 1)) / fecRsPrescale; - - /* write corresponding registers */ -- status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period); -+ status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod); - if (status < 0) - goto error; -- status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, -- fec_rs_prescale); -+ status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale); - if (status < 0) - goto error; -- status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period); -+ status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int set_qam16(struct drxk_state *state) -+static int SetQAM16(struct drxk_state *state) - { - int status = 0; - -@@ -4323,8 +4336,7 @@ static int set_qam16(struct drxk_state *state) - goto error; - - /* QAM Slicer Settings */ -- status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, -- DRXK_QAM_SL_SIG_POWER_QAM16); -+ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16); - if (status < 0) - goto error; - -@@ -4450,7 +4462,7 @@ static int set_qam16(struct drxk_state *state) - - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - -@@ -4461,7 +4473,7 @@ error: - * \param demod instance of demod. - * \return DRXStatus_t. - */ --static int set_qam32(struct drxk_state *state) -+static int SetQAM32(struct drxk_state *state) - { - int status = 0; - -@@ -4520,8 +4532,7 @@ static int set_qam32(struct drxk_state *state) - - /* QAM Slicer Settings */ - -- status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, -- DRXK_QAM_SL_SIG_POWER_QAM32); -+ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32); - if (status < 0) - goto error; - -@@ -4646,7 +4657,7 @@ static int set_qam32(struct drxk_state *state) - status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - -@@ -4657,7 +4668,7 @@ error: - * \param demod instance of demod. - * \return DRXStatus_t. - */ --static int set_qam64(struct drxk_state *state) -+static int SetQAM64(struct drxk_state *state) - { - int status = 0; - -@@ -4714,8 +4725,7 @@ static int set_qam64(struct drxk_state *state) - goto error; - - /* QAM Slicer Settings */ -- status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, -- DRXK_QAM_SL_SIG_POWER_QAM64); -+ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64); - if (status < 0) - goto error; - -@@ -4840,7 +4850,7 @@ static int set_qam64(struct drxk_state *state) - status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - - return status; - } -@@ -4852,7 +4862,7 @@ error: - * \param demod: instance of demod. - * \return DRXStatus_t. - */ --static int set_qam128(struct drxk_state *state) -+static int SetQAM128(struct drxk_state *state) - { - int status = 0; - -@@ -4911,8 +4921,7 @@ static int set_qam128(struct drxk_state *state) - - /* QAM Slicer Settings */ - -- status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, -- DRXK_QAM_SL_SIG_POWER_QAM128); -+ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128); - if (status < 0) - goto error; - -@@ -5037,7 +5046,7 @@ static int set_qam128(struct drxk_state *state) - status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - - return status; - } -@@ -5049,7 +5058,7 @@ error: - * \param demod: instance of demod. - * \return DRXStatus_t. - */ --static int set_qam256(struct drxk_state *state) -+static int SetQAM256(struct drxk_state *state) - { - int status = 0; - -@@ -5107,8 +5116,7 @@ static int set_qam256(struct drxk_state *state) - - /* QAM Slicer Settings */ - -- status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, -- DRXK_QAM_SL_SIG_POWER_QAM256); -+ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256); - if (status < 0) - goto error; - -@@ -5233,7 +5241,7 @@ static int set_qam256(struct drxk_state *state) - status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - -@@ -5245,10 +5253,10 @@ error: - * \param channel: pointer to channel data. - * \return DRXStatus_t. - */ --static int qam_reset_qam(struct drxk_state *state) -+static int QAMResetQAM(struct drxk_state *state) - { - int status; -- u16 cmd_result; -+ u16 cmdResult; - - dprintk(1, "\n"); - /* Stop QAM comstate->m_exec */ -@@ -5256,12 +5264,10 @@ static int qam_reset_qam(struct drxk_state *state) - if (status < 0) - goto error; - -- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM -- | SCU_RAM_COMMAND_CMD_DEMOD_RESET, -- 0, NULL, 1, &cmd_result); -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - -@@ -5273,18 +5279,18 @@ error: - * \param channel: pointer to channel data. - * \return DRXStatus_t. - */ --static int qam_set_symbolrate(struct drxk_state *state) -+static int QAMSetSymbolrate(struct drxk_state *state) - { -- u32 adc_frequency = 0; -- u32 symb_freq = 0; -- u32 iqm_rc_rate = 0; -+ u32 adcFrequency = 0; -+ u32 symbFreq = 0; -+ u32 iqmRcRate = 0; - u16 ratesel = 0; -- u32 lc_symb_rate = 0; -+ u32 lcSymbRate = 0; - int status; - - dprintk(1, "\n"); - /* Select & calculate correct IQM rate */ -- adc_frequency = (state->m_sys_clock_freq * 1000) / 3; -+ adcFrequency = (state->m_sysClockFreq * 1000) / 3; - ratesel = 0; - /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */ - if (state->props.symbol_rate <= 1188750) -@@ -5300,38 +5306,38 @@ static int qam_set_symbolrate(struct drxk_state *state) - /* - IqmRcRate = ((Fadc / (symbolrate * (4<props.symbol_rate * (1 << ratesel); -- if (symb_freq == 0) { -+ symbFreq = state->props.symbol_rate * (1 << ratesel); -+ if (symbFreq == 0) { - /* Divide by zero */ - status = -EINVAL; - goto error; - } -- iqm_rc_rate = (adc_frequency / symb_freq) * (1 << 21) + -- (Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) - -+ iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) + -+ (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) - - (1 << 23); -- status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate); -+ status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate); - if (status < 0) - goto error; -- state->m_iqm_rc_rate = iqm_rc_rate; -+ state->m_iqmRcRate = iqmRcRate; - /* -- LcSymbFreq = round (.125 * symbolrate / adc_freq * (1<<15)) -+ LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15)) - */ -- symb_freq = state->props.symbol_rate; -- if (adc_frequency == 0) { -+ symbFreq = state->props.symbol_rate; -+ if (adcFrequency == 0) { - /* Divide by zero */ - status = -EINVAL; - goto error; - } -- lc_symb_rate = (symb_freq / adc_frequency) * (1 << 12) + -- (Frac28a((symb_freq % adc_frequency), adc_frequency) >> -+ lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) + -+ (Frac28a((symbFreq % adcFrequency), adcFrequency) >> - 16); -- if (lc_symb_rate > 511) -- lc_symb_rate = 511; -- status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate); -+ if (lcSymbRate > 511) -+ lcSymbRate = 511; -+ status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate); - - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - -@@ -5344,36 +5350,34 @@ error: - * \return DRXStatus_t. - */ - --static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status) -+static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus) - { - int status; -- u16 result[2] = { 0, 0 }; -+ u16 Result[2] = { 0, 0 }; - - dprintk(1, "\n"); -- *p_lock_status = NOT_LOCKED; -+ *pLockStatus = NOT_LOCKED; - status = scu_command(state, - SCU_RAM_COMMAND_STANDARD_QAM | - SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2, -- result); -+ Result); - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: %s status = %08x\n", __func__, status); - -- if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) { -+ if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) { - /* 0x0000 NOT LOCKED */ -- } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) { -+ } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) { - /* 0x4000 DEMOD LOCKED */ -- *p_lock_status = DEMOD_LOCK; -- } else if (result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) { -+ *pLockStatus = DEMOD_LOCK; -+ } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) { - /* 0x8000 DEMOD + FEC LOCKED (system lock) */ -- *p_lock_status = MPEG_LOCK; -+ *pLockStatus = MPEG_LOCK; - } else { - /* 0xC000 NEVER LOCKED */ - /* (system will never be able to lock to the signal) */ -- /* -- * TODO: check this, intermediate & standard specific lock -- * states are not taken into account here -- */ -- *p_lock_status = NEVER_LOCK; -+ /* TODO: check this, intermediate & standard specific lock states are not -+ taken into account here */ -+ *pLockStatus = NEVER_LOCK; - } - return status; - } -@@ -5385,70 +5389,12 @@ static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status) - #define QAM_LOCKRANGE__M 0x10 - #define QAM_LOCKRANGE_NORMAL 0x10 - --static int qam_demodulator_command(struct drxk_state *state, -- int number_of_parameters) -+static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, -+ s32 tunerFreqOffset) - { - int status; -- u16 cmd_result; -- u16 set_param_parameters[4] = { 0, 0, 0, 0 }; -- -- set_param_parameters[0] = state->m_constellation; /* modulation */ -- set_param_parameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ -- -- if (number_of_parameters == 2) { -- u16 set_env_parameters[1] = { 0 }; -- -- if (state->m_operation_mode == OM_QAM_ITU_C) -- set_env_parameters[0] = QAM_TOP_ANNEX_C; -- else -- set_env_parameters[0] = QAM_TOP_ANNEX_A; -- -- status = scu_command(state, -- SCU_RAM_COMMAND_STANDARD_QAM -- | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, -- 1, set_env_parameters, 1, &cmd_result); -- if (status < 0) -- goto error; -- -- status = scu_command(state, -- SCU_RAM_COMMAND_STANDARD_QAM -- | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, -- number_of_parameters, set_param_parameters, -- 1, &cmd_result); -- } else if (number_of_parameters == 4) { -- if (state->m_operation_mode == OM_QAM_ITU_C) -- set_param_parameters[2] = QAM_TOP_ANNEX_C; -- else -- set_param_parameters[2] = QAM_TOP_ANNEX_A; -- -- set_param_parameters[3] |= (QAM_MIRROR_AUTO_ON); -- /* Env parameters */ -- /* check for LOCKRANGE Extented */ -- /* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */ -- -- status = scu_command(state, -- SCU_RAM_COMMAND_STANDARD_QAM -- | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, -- number_of_parameters, set_param_parameters, -- 1, &cmd_result); -- } else { -- pr_warn("Unknown QAM demodulator parameter count %d\n", -- number_of_parameters); -- status = -EINVAL; -- } -- --error: -- if (status < 0) -- pr_warn("Warning %d on %s\n", status, __func__); -- return status; --} -- --static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, -- s32 tuner_freq_offset) --{ -- int status; -- u16 cmd_result; -- int qam_demod_param_count = state->qam_demod_parameter_count; -+ u16 setParamParameters[4] = { 0, 0, 0, 0 }; -+ u16 cmdResult; - - dprintk(1, "\n"); - /* -@@ -5463,7 +5409,7 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, - status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP); - if (status < 0) - goto error; -- status = qam_reset_qam(state); -+ status = QAMResetQAM(state); - if (status < 0) - goto error; - -@@ -5472,27 +5418,27 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, - * -set params; resets IQM,QAM,FEC HW; initializes some - * SCU variables - */ -- status = qam_set_symbolrate(state); -+ status = QAMSetSymbolrate(state); - if (status < 0) - goto error; - - /* Set params */ - switch (state->props.modulation) { - case QAM_256: -- state->m_constellation = DRX_CONSTELLATION_QAM256; -+ state->m_Constellation = DRX_CONSTELLATION_QAM256; - break; - case QAM_AUTO: - case QAM_64: -- state->m_constellation = DRX_CONSTELLATION_QAM64; -+ state->m_Constellation = DRX_CONSTELLATION_QAM64; - break; - case QAM_16: -- state->m_constellation = DRX_CONSTELLATION_QAM16; -+ state->m_Constellation = DRX_CONSTELLATION_QAM16; - break; - case QAM_32: -- state->m_constellation = DRX_CONSTELLATION_QAM32; -+ state->m_Constellation = DRX_CONSTELLATION_QAM32; - break; - case QAM_128: -- state->m_constellation = DRX_CONSTELLATION_QAM128; -+ state->m_Constellation = DRX_CONSTELLATION_QAM128; - break; - default: - status = -EINVAL; -@@ -5500,60 +5446,50 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, - } - if (status < 0) - goto error; -+ setParamParameters[0] = state->m_Constellation; /* modulation */ -+ setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ -+ if (state->m_OperationMode == OM_QAM_ITU_C) -+ setParamParameters[2] = QAM_TOP_ANNEX_C; -+ else -+ setParamParameters[2] = QAM_TOP_ANNEX_A; -+ setParamParameters[3] |= (QAM_MIRROR_AUTO_ON); -+ /* Env parameters */ -+ /* check for LOCKRANGE Extented */ -+ /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */ - -- /* Use the 4-parameter if it's requested or we're probing for -- * the correct command. */ -- if (state->qam_demod_parameter_count == 4 -- || !state->qam_demod_parameter_count) { -- qam_demod_param_count = 4; -- status = qam_demodulator_command(state, qam_demod_param_count); -- } -- -- /* Use the 2-parameter command if it was requested or if we're -- * probing for the correct command and the 4-parameter command -- * failed. */ -- if (state->qam_demod_parameter_count == 2 -- || (!state->qam_demod_parameter_count && status < 0)) { -- qam_demod_param_count = 2; -- status = qam_demodulator_command(state, qam_demod_param_count); -- } -- -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4, setParamParameters, 1, &cmdResult); - if (status < 0) { -- dprintk(1, "Could not set demodulator parameters.\n"); -- dprintk(1, -- "Make sure qam_demod_parameter_count (%d) is correct for your firmware (%s).\n", -- state->qam_demod_parameter_count, -- state->microcode_name); -- goto error; -- } else if (!state->qam_demod_parameter_count) { -- dprintk(1, -- "Auto-probing the QAM command parameters was successful - using %d parameters.\n", -- qam_demod_param_count); -+ /* Fall-back to the simpler call */ -+ if (state->m_OperationMode == OM_QAM_ITU_C) -+ setParamParameters[0] = QAM_TOP_ANNEX_C; -+ else -+ setParamParameters[0] = QAM_TOP_ANNEX_A; -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 1, setParamParameters, 1, &cmdResult); -+ if (status < 0) -+ goto error; - -- /* -- * One of our commands was successful. We don't need to -- * auto-probe anymore, now that we got the correct command. -- */ -- state->qam_demod_parameter_count = qam_demod_param_count; -+ setParamParameters[0] = state->m_Constellation; /* modulation */ -+ setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 2, setParamParameters, 1, &cmdResult); - } -+ if (status < 0) -+ goto error; - - /* - * STEP 3: enable the system in a mode where the ADC provides valid - * signal setup modulation independent registers - */ - #if 0 -- status = set_frequency(channel, tuner_freq_offset)); -+ status = SetFrequency(channel, tunerFreqOffset)); - if (status < 0) - goto error; - #endif -- status = set_frequency_shifter(state, intermediate_freqk_hz, -- tuner_freq_offset, true); -+ status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true); - if (status < 0) - goto error; - - /* Setup BER measurement */ -- status = set_qam_measurement(state, state->m_constellation, -- state->props.symbol_rate); -+ status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate); - if (status < 0) - goto error; - -@@ -5626,8 +5562,7 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, - goto error; - - /* Mirroring, QAM-block starting point not inverted */ -- status = write16(state, QAM_SY_SP_INV__A, -- QAM_SY_SP_INV_SPECTRUM_INV_DIS); -+ status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS); - if (status < 0) - goto error; - -@@ -5639,20 +5574,20 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, - /* STEP 4: modulation specific setup */ - switch (state->props.modulation) { - case QAM_16: -- status = set_qam16(state); -+ status = SetQAM16(state); - break; - case QAM_32: -- status = set_qam32(state); -+ status = SetQAM32(state); - break; - case QAM_AUTO: - case QAM_64: -- status = set_qam64(state); -+ status = SetQAM64(state); - break; - case QAM_128: -- status = set_qam128(state); -+ status = SetQAM128(state); - break; - case QAM_256: -- status = set_qam256(state); -+ status = SetQAM256(state); - break; - default: - status = -EINVAL; -@@ -5669,12 +5604,12 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, - /* Re-configure MPEG output, requires knowledge of channel bitrate */ - /* extAttr->currentChannel.modulation = channel->modulation; */ - /* extAttr->currentChannel.symbolrate = channel->symbolrate; */ -- status = mpegts_dto_setup(state, state->m_operation_mode); -+ status = MPEGTSDtoSetup(state, state->m_OperationMode); - if (status < 0) - goto error; - -- /* start processes */ -- status = mpegts_start(state); -+ /* Start processes */ -+ status = MPEGTSStart(state); - if (status < 0) - goto error; - status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE); -@@ -5688,9 +5623,7 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, - goto error; - - /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */ -- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM -- | SCU_RAM_COMMAND_CMD_DEMOD_START, -- 0, NULL, 1, &cmd_result); -+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult); - if (status < 0) - goto error; - -@@ -5699,12 +5632,12 @@ static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz, - - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int set_qam_standard(struct drxk_state *state, -- enum operation_mode o_mode) -+static int SetQAMStandard(struct drxk_state *state, -+ enum OperationMode oMode) - { - int status; - #ifdef DRXK_QAM_TAPS -@@ -5716,14 +5649,14 @@ static int set_qam_standard(struct drxk_state *state, - dprintk(1, "\n"); - - /* added antenna switch */ -- switch_antenna_to_qam(state); -+ SwitchAntennaToQAM(state); - - /* Ensure correct power-up mode */ -- status = power_up_qam(state); -+ status = PowerUpQAM(state); - if (status < 0) - goto error; - /* Reset QAM block */ -- status = qam_reset_qam(state); -+ status = QAMResetQAM(state); - if (status < 0) - goto error; - -@@ -5738,24 +5671,15 @@ static int set_qam_standard(struct drxk_state *state, - - /* Upload IQM Channel Filter settings by - boot loader from ROM table */ -- switch (o_mode) { -+ switch (oMode) { - case OM_QAM_ITU_A: -- status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, -- DRXK_BLCC_NR_ELEMENTS_TAPS, -- DRXK_BLC_TIMEOUT); -+ status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); - break; - case OM_QAM_ITU_C: -- status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A, -- DRXK_BL_ROM_OFFSET_TAPS_ITU_C, -- DRXK_BLDC_NR_ELEMENTS_TAPS, -- DRXK_BLC_TIMEOUT); -+ status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); - if (status < 0) - goto error; -- status = bl_direct_cmd(state, -- IQM_CF_TAP_IM0__A, -- DRXK_BL_ROM_OFFSET_TAPS_ITU_C, -- DRXK_BLDC_NR_ELEMENTS_TAPS, -- DRXK_BLC_TIMEOUT); -+ status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT); - break; - default: - status = -EINVAL; -@@ -5763,14 +5687,13 @@ static int set_qam_standard(struct drxk_state *state, - if (status < 0) - goto error; - -- status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B); -+ status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B)); - if (status < 0) - goto error; - status = write16(state, IQM_CF_SYMMETRIC__A, 0); - if (status < 0) - goto error; -- status = write16(state, IQM_CF_MIDTAP__A, -- ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B))); -+ status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B))); - if (status < 0) - goto error; - -@@ -5827,7 +5750,7 @@ static int set_qam_standard(struct drxk_state *state, - goto error; - - /* turn on IQMAF. Must be done before setAgc**() */ -- status = set_iqm_af(state, true); -+ status = SetIqmAf(state, true); - if (status < 0) - goto error; - status = write16(state, IQM_AF_START_LOCK__A, 0x01); -@@ -5835,7 +5758,7 @@ static int set_qam_standard(struct drxk_state *state, - goto error; - - /* IQM will not be reset from here, sync ADC and update/init AGC */ -- status = adc_synchronization(state); -+ status = ADCSynchronization(state); - if (status < 0) - goto error; - -@@ -5852,18 +5775,18 @@ static int set_qam_standard(struct drxk_state *state, - /* No more resets of the IQM, current standard correctly set => - now AGCs can be configured. */ - -- status = init_agc(state, true); -+ status = InitAGC(state, true); - if (status < 0) - goto error; -- status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg)); -+ status = SetPreSaw(state, &(state->m_qamPreSawCfg)); - if (status < 0) - goto error; - - /* Configure AGC's */ -- status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true); -+ status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true); - if (status < 0) - goto error; -- status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true); -+ status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true); - if (status < 0) - goto error; - -@@ -5871,19 +5794,18 @@ static int set_qam_standard(struct drxk_state *state, - status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int write_gpio(struct drxk_state *state) -+static int WriteGPIO(struct drxk_state *state) - { - int status; - u16 value = 0; - - dprintk(1, "\n"); - /* stop lock indicator process */ -- status = write16(state, SCU_RAM_GPIO__A, -- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); -+ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); - if (status < 0) - goto error; - -@@ -5892,11 +5814,10 @@ static int write_gpio(struct drxk_state *state) - if (status < 0) - goto error; - -- if (state->m_has_sawsw) { -- if (state->uio_mask & 0x0001) { /* UIO-1 */ -+ if (state->m_hasSAWSW) { -+ if (state->UIO_mask & 0x0001) { /* UIO-1 */ - /* write to io pad configuration register - output mode */ -- status = write16(state, SIO_PDR_SMA_TX_CFG__A, -- state->m_gpio_cfg); -+ status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg); - if (status < 0) - goto error; - -@@ -5904,7 +5825,7 @@ static int write_gpio(struct drxk_state *state) - status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); - if (status < 0) - goto error; -- if ((state->m_gpio & 0x0001) == 0) -+ if ((state->m_GPIO & 0x0001) == 0) - value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ - else - value |= 0x8000; /* write one to 15th bit - 1st UIO */ -@@ -5913,10 +5834,9 @@ static int write_gpio(struct drxk_state *state) - if (status < 0) - goto error; - } -- if (state->uio_mask & 0x0002) { /* UIO-2 */ -+ if (state->UIO_mask & 0x0002) { /* UIO-2 */ - /* write to io pad configuration register - output mode */ -- status = write16(state, SIO_PDR_SMA_RX_CFG__A, -- state->m_gpio_cfg); -+ status = write16(state, SIO_PDR_SMA_RX_CFG__A, state->m_GPIOCfg); - if (status < 0) - goto error; - -@@ -5924,7 +5844,7 @@ static int write_gpio(struct drxk_state *state) - status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); - if (status < 0) - goto error; -- if ((state->m_gpio & 0x0002) == 0) -+ if ((state->m_GPIO & 0x0002) == 0) - value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */ - else - value |= 0x4000; /* write one to 14th bit - 2st UIO */ -@@ -5933,10 +5853,9 @@ static int write_gpio(struct drxk_state *state) - if (status < 0) - goto error; - } -- if (state->uio_mask & 0x0004) { /* UIO-3 */ -+ if (state->UIO_mask & 0x0004) { /* UIO-3 */ - /* write to io pad configuration register - output mode */ -- status = write16(state, SIO_PDR_GPIO_CFG__A, -- state->m_gpio_cfg); -+ status = write16(state, SIO_PDR_GPIO_CFG__A, state->m_GPIOCfg); - if (status < 0) - goto error; - -@@ -5944,7 +5863,7 @@ static int write_gpio(struct drxk_state *state) - status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value); - if (status < 0) - goto error; -- if ((state->m_gpio & 0x0004) == 0) -+ if ((state->m_GPIO & 0x0004) == 0) - value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ - else - value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ -@@ -5958,11 +5877,11 @@ static int write_gpio(struct drxk_state *state) - status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int switch_antenna_to_qam(struct drxk_state *state) -+static int SwitchAntennaToQAM(struct drxk_state *state) - { - int status = 0; - bool gpio_state; -@@ -5972,22 +5891,22 @@ static int switch_antenna_to_qam(struct drxk_state *state) - if (!state->antenna_gpio) - return 0; - -- gpio_state = state->m_gpio & state->antenna_gpio; -+ gpio_state = state->m_GPIO & state->antenna_gpio; - - if (state->antenna_dvbt ^ gpio_state) { - /* Antenna is on DVB-T mode. Switch */ - if (state->antenna_dvbt) -- state->m_gpio &= ~state->antenna_gpio; -+ state->m_GPIO &= ~state->antenna_gpio; - else -- state->m_gpio |= state->antenna_gpio; -- status = write_gpio(state); -+ state->m_GPIO |= state->antenna_gpio; -+ status = WriteGPIO(state); - } - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - --static int switch_antenna_to_dvbt(struct drxk_state *state) -+static int SwitchAntennaToDVBT(struct drxk_state *state) - { - int status = 0; - bool gpio_state; -@@ -5997,23 +5916,23 @@ static int switch_antenna_to_dvbt(struct drxk_state *state) - if (!state->antenna_gpio) - return 0; - -- gpio_state = state->m_gpio & state->antenna_gpio; -+ gpio_state = state->m_GPIO & state->antenna_gpio; - - if (!(state->antenna_dvbt ^ gpio_state)) { - /* Antenna is on DVB-C mode. Switch */ - if (state->antenna_dvbt) -- state->m_gpio |= state->antenna_gpio; -+ state->m_GPIO |= state->antenna_gpio; - else -- state->m_gpio &= ~state->antenna_gpio; -- status = write_gpio(state); -+ state->m_GPIO &= ~state->antenna_gpio; -+ status = WriteGPIO(state); - } - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - return status; - } - - --static int power_down_device(struct drxk_state *state) -+static int PowerDownDevice(struct drxk_state *state) - { - /* Power down to requested mode */ - /* Backup some register settings */ -@@ -6024,86 +5943,98 @@ static int power_down_device(struct drxk_state *state) - int status; - - dprintk(1, "\n"); -- if (state->m_b_p_down_open_bridge) { -+ if (state->m_bPDownOpenBridge) { - /* Open I2C bridge before power down of DRXK */ - status = ConfigureI2CBridge(state, true); - if (status < 0) - goto error; - } - /* driver 0.9.0 */ -- status = dvbt_enable_ofdm_token_ring(state, false); -+ status = DVBTEnableOFDMTokenRing(state, false); - if (status < 0) - goto error; - -- status = write16(state, SIO_CC_PWD_MODE__A, -- SIO_CC_PWD_MODE_LEVEL_CLOCK); -+ status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK); - if (status < 0) - goto error; - status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); - if (status < 0) - goto error; -- state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; -- status = hi_cfg_command(state); -+ state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; -+ status = HI_CfgCommand(state); - error: - if (status < 0) -- pr_err("Error %d on %s\n", status, __func__); -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - - return status; - } - -+static int load_microcode(struct drxk_state *state, const char *mc_name) -+{ -+ const struct firmware *fw = NULL; -+ int err = 0; -+ -+ dprintk(1, "\n"); -+ -+ err = request_firmware(&fw, mc_name, state->i2c->dev.parent); -+ if (err < 0) { -+ printk(KERN_ERR -+ "drxk: Could not load firmware file %s.\n", mc_name); -+ printk(KERN_INFO -+ "drxk: Copy %s to your hotplug directory!\n", mc_name); -+ return err; -+ } -+ err = DownloadMicrocode(state, fw->data, fw->size); -+ release_firmware(fw); -+ return err; -+} -+ - static int init_drxk(struct drxk_state *state) - { -- int status = 0, n = 0; -- enum drx_power_mode power_mode = DRXK_POWER_DOWN_OFDM; -- u16 driver_version; -+ int status = 0; -+ enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM; -+ u16 driverVersion; - - dprintk(1, "\n"); -- if ((state->m_drxk_state == DRXK_UNINITIALIZED)) { -- drxk_i2c_lock(state); -- status = power_up_device(state); -+ if ((state->m_DrxkState == DRXK_UNINITIALIZED)) { -+ status = PowerUpDevice(state); - if (status < 0) - goto error; -- status = drxx_open(state); -+ status = DRXX_Open(state); - if (status < 0) - goto error; - /* Soft reset of OFDM-, sys- and osc-clockdomain */ -- status = write16(state, SIO_CC_SOFT_RST__A, -- SIO_CC_SOFT_RST_OFDM__M -- | SIO_CC_SOFT_RST_SYS__M -- | SIO_CC_SOFT_RST_OSC__M); -+ status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M); - if (status < 0) - goto error; - status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY); - if (status < 0) - goto error; -- /* -- * TODO is this needed? If yes, how much delay in -- * worst case scenario -- */ -- usleep_range(1000, 2000); -- state->m_drxk_a3_patch_code = true; -- status = get_device_capabilities(state); -+ /* TODO is this needed, if yes how much delay in worst case scenario */ -+ msleep(1); -+ state->m_DRXK_A3_PATCH_CODE = true; -+ status = GetDeviceCapabilities(state); - if (status < 0) - goto error; - - /* Bridge delay, uses oscilator clock */ - /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */ - /* SDA brdige delay */ -- state->m_hi_cfg_bridge_delay = -- (u16) ((state->m_osc_clock_freq / 1000) * -+ state->m_HICfgBridgeDelay = -+ (u16) ((state->m_oscClockFreq / 1000) * - HI_I2C_BRIDGE_DELAY) / 1000; - /* Clipping */ -- if (state->m_hi_cfg_bridge_delay > -+ if (state->m_HICfgBridgeDelay > - SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) { -- state->m_hi_cfg_bridge_delay = -+ state->m_HICfgBridgeDelay = - SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M; - } - /* SCL bridge delay, same as SDA for now */ -- state->m_hi_cfg_bridge_delay += -- state->m_hi_cfg_bridge_delay << -+ state->m_HICfgBridgeDelay += -+ state->m_HICfgBridgeDelay << - SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B; - -- status = init_hi(state); -+ status = InitHI(state); - if (status < 0) - goto error; - /* disable various processes */ -@@ -6112,14 +6043,13 @@ static int init_drxk(struct drxk_state *state) - && !(state->m_DRXK_A2_ROM_CODE)) - #endif - { -- status = write16(state, SCU_RAM_GPIO__A, -- SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); -+ status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); - if (status < 0) - goto error; - } - - /* disable MPEG port */ -- status = mpegts_disable(state); -+ status = MPEGTSDisable(state); - if (status < 0) - goto error; - -@@ -6132,30 +6062,23 @@ static int init_drxk(struct drxk_state *state) - goto error; - - /* enable token-ring bus through OFDM block for possible ucode upload */ -- status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, -- SIO_OFDM_SH_OFDM_RING_ENABLE_ON); -+ status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON); - if (status < 0) - goto error; - - /* include boot loader section */ -- status = write16(state, SIO_BL_COMM_EXEC__A, -- SIO_BL_COMM_EXEC_ACTIVE); -+ status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE); - if (status < 0) - goto error; -- status = bl_chain_cmd(state, 0, 6, 100); -+ status = BLChainCmd(state, 0, 6, 100); - if (status < 0) - goto error; - -- if (state->fw) { -- status = download_microcode(state, state->fw->data, -- state->fw->size); -- if (status < 0) -- goto error; -- } -+ if (state->microcode_name) -+ load_microcode(state, state->microcode_name); - - /* disable token-ring bus through OFDM block for possible ucode upload */ -- status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, -- SIO_OFDM_SH_OFDM_RING_ENABLE_OFF); -+ status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF); - if (status < 0) - goto error; - -@@ -6163,55 +6086,50 @@ static int init_drxk(struct drxk_state *state) - status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE); - if (status < 0) - goto error; -- status = drxx_open(state); -+ status = DRXX_Open(state); - if (status < 0) - goto error; - /* added for test */ - msleep(30); - -- power_mode = DRXK_POWER_DOWN_OFDM; -- status = ctrl_power_mode(state, &power_mode); -+ powerMode = DRXK_POWER_DOWN_OFDM; -+ status = CtrlPowerMode(state, &powerMode); - if (status < 0) - goto error; - - /* Stamp driver version number in SCU data RAM in BCD code -- Done to enable field application engineers to retrieve drxdriver version -+ Done to enable field application engineers to retreive drxdriver version - via I2C from SCU RAM. - Not using SCU command interface for SCU register access since no - microcode may be present. - */ -- driver_version = -+ driverVersion = - (((DRXK_VERSION_MAJOR / 100) % 10) << 12) + - (((DRXK_VERSION_MAJOR / 10) % 10) << 8) + - ((DRXK_VERSION_MAJOR % 10) << 4) + - (DRXK_VERSION_MINOR % 10); -- status = write16(state, SCU_RAM_DRIVER_VER_HI__A, -- driver_version); -+ status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion); - if (status < 0) - goto error; -- driver_version = -+ driverVersion = - (((DRXK_VERSION_PATCH / 1000) % 10) << 12) + - (((DRXK_VERSION_PATCH / 100) % 10) << 8) + - (((DRXK_VERSION_PATCH / 10) % 10) << 4) + - (DRXK_VERSION_PATCH % 10); -- status = write16(state, SCU_RAM_DRIVER_VER_LO__A, -- driver_version); -+ status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion); - if (status < 0) - goto error; - -- pr_info("DRXK driver version %d.%d.%d\n", -+ printk(KERN_INFO "DRXK driver version %d.%d.%d\n", - DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR, - DRXK_VERSION_PATCH); - -- /* -- * Dirty fix of default values for ROM/PATCH microcode -- * Dirty because this fix makes it impossible to setup -- * suitable values before calling DRX_Open. This solution -- * requires changes to RF AGC speed to be done via the CTRL -- * function after calling DRX_Open -- */ -+ /* Dirty fix of default values for ROM/PATCH microcode -+ Dirty because this fix makes it impossible to setup suitable values -+ before calling DRX_Open. This solution requires changes to RF AGC speed -+ to be done via the CTRL function after calling DRX_Open */ - -- /* m_dvbt_rf_agc_cfg.speed = 3; */ -+ /* m_dvbtRfAgcCfg.speed = 3; */ - - /* Reset driver debug flags to 0 */ - status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0); -@@ -6224,94 +6142,45 @@ static int init_drxk(struct drxk_state *state) - if (status < 0) - goto error; - /* MPEGTS functions are still the same */ -- status = mpegts_dto_init(state); -+ status = MPEGTSDtoInit(state); - if (status < 0) - goto error; -- status = mpegts_stop(state); -+ status = MPEGTSStop(state); - if (status < 0) - goto error; -- status = mpegts_configure_polarity(state); -+ status = MPEGTSConfigurePolarity(state); - if (status < 0) - goto error; -- status = mpegts_configure_pins(state, state->m_enable_mpeg_output); -+ status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput); - if (status < 0) - goto error; - /* added: configure GPIO */ -- status = write_gpio(state); -+ status = WriteGPIO(state); - if (status < 0) - goto error; - -- state->m_drxk_state = DRXK_STOPPED; -+ state->m_DrxkState = DRXK_STOPPED; - -- if (state->m_b_power_down) { -- status = power_down_device(state); -+ if (state->m_bPowerDown) { -+ status = PowerDownDevice(state); - if (status < 0) - goto error; -- state->m_drxk_state = DRXK_POWERED_DOWN; -+ state->m_DrxkState = DRXK_POWERED_DOWN; - } else -- state->m_drxk_state = DRXK_STOPPED; -- -- /* Initialize the supported delivery systems */ -- n = 0; -- if (state->m_has_dvbc) { -- state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; -- state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; -- strlcat(state->frontend.ops.info.name, " DVB-C", -- sizeof(state->frontend.ops.info.name)); -- } -- if (state->m_has_dvbt) { -- state->frontend.ops.delsys[n++] = SYS_DVBT; -- strlcat(state->frontend.ops.info.name, " DVB-T", -- sizeof(state->frontend.ops.info.name)); -- } -- drxk_i2c_unlock(state); -+ state->m_DrxkState = DRXK_STOPPED; - } - error: -- if (status < 0) { -- state->m_drxk_state = DRXK_NO_DEV; -- drxk_i2c_unlock(state); -- pr_err("Error %d on %s\n", status, __func__); -- } -+ if (status < 0) -+ printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__); - - return status; - } - --static void load_firmware_cb(const struct firmware *fw, -- void *context) --{ -- struct drxk_state *state = context; -- -- dprintk(1, ": %s\n", fw ? "firmware loaded" : "firmware not loaded"); -- if (!fw) { -- pr_err("Could not load firmware file %s.\n", -- state->microcode_name); -- pr_info("Copy %s to your hotplug directory!\n", -- state->microcode_name); -- state->microcode_name = NULL; -- -- /* -- * As firmware is now load asynchronous, it is not possible -- * anymore to fail at frontend attach. We might silently -- * return here, and hope that the driver won't crash. -- * We might also change all DVB callbacks to return -ENODEV -- * if the device is not initialized. -- * As the DRX-K devices have their own internal firmware, -- * let's just hope that it will match a firmware revision -- * compatible with this driver and proceed. -- */ -- } -- state->fw = fw; -- -- init_drxk(state); --} -- - static void drxk_release(struct dvb_frontend *fe) - { - struct drxk_state *state = fe->demodulator_priv; - - dprintk(1, "\n"); -- release_firmware(state->fw); -- - kfree(state); - } - -@@ -6320,13 +6189,7 @@ static int drxk_sleep(struct dvb_frontend *fe) - struct drxk_state *state = fe->demodulator_priv; - - dprintk(1, "\n"); -- -- if (state->m_drxk_state == DRXK_NO_DEV) -- return -ENODEV; -- if (state->m_drxk_state == DRXK_UNINITIALIZED) -- return 0; -- -- shut_down(state); -+ ShutDown(state); - return 0; - } - -@@ -6334,11 +6197,7 @@ static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) - { - struct drxk_state *state = fe->demodulator_priv; - -- dprintk(1, ": %s\n", enable ? "enable" : "disable"); -- -- if (state->m_drxk_state == DRXK_NO_DEV) -- return -ENODEV; -- -+ dprintk(1, "%s\n", enable ? "enable" : "disable"); - return ConfigureI2CBridge(state, enable ? true : false); - } - -@@ -6351,14 +6210,9 @@ static int drxk_set_parameters(struct dvb_frontend *fe) - - dprintk(1, "\n"); - -- if (state->m_drxk_state == DRXK_NO_DEV) -- return -ENODEV; -- -- if (state->m_drxk_state == DRXK_UNINITIALIZED) -- return -EAGAIN; -- - if (!fe->ops.tuner_ops.get_if_frequency) { -- pr_err("Error: get_if_frequency() not defined at tuner. Can't work without it!\n"); -+ printk(KERN_ERR -+ "drxk: Error: get_if_frequency() not defined at tuner. Can't work without it!\n"); - return -EINVAL; - } - -@@ -6373,23 +6227,22 @@ static int drxk_set_parameters(struct dvb_frontend *fe) - state->props = *p; - - if (old_delsys != delsys) { -- shut_down(state); -+ ShutDown(state); - switch (delsys) { - case SYS_DVBC_ANNEX_A: - case SYS_DVBC_ANNEX_C: -- if (!state->m_has_dvbc) -+ if (!state->m_hasDVBC) - return -EINVAL; -- state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? -- true : false; -+ state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false; - if (state->m_itut_annex_c) -- setoperation_mode(state, OM_QAM_ITU_C); -+ SetOperationMode(state, OM_QAM_ITU_C); - else -- setoperation_mode(state, OM_QAM_ITU_A); -+ SetOperationMode(state, OM_QAM_ITU_A); - break; - case SYS_DVBT: -- if (!state->m_has_dvbt) -+ if (!state->m_hasDVBT) - return -EINVAL; -- setoperation_mode(state, OM_DVBT); -+ SetOperationMode(state, OM_DVBT); - break; - default: - return -EINVAL; -@@ -6397,261 +6250,35 @@ static int drxk_set_parameters(struct dvb_frontend *fe) - } - - fe->ops.tuner_ops.get_if_frequency(fe, &IF); -- start(state, 0, IF); -- -- /* After set_frontend, stats aren't available */ -- p->strength.stat[0].scale = FE_SCALE_RELATIVE; -- p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -+ Start(state, 0, IF); - - /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */ - - return 0; - } - --static int get_strength(struct drxk_state *state, u64 *strength) --{ -- int status; -- struct s_cfg_agc rf_agc, if_agc; -- u32 total_gain = 0; -- u32 atten = 0; -- u32 agc_range = 0; -- u16 scu_lvl = 0; -- u16 scu_coc = 0; -- /* FIXME: those are part of the tuner presets */ -- u16 tuner_rf_gain = 50; /* Default value on az6007 driver */ -- u16 tuner_if_gain = 40; /* Default value on az6007 driver */ -- -- *strength = 0; -- -- if (is_dvbt(state)) { -- rf_agc = state->m_dvbt_rf_agc_cfg; -- if_agc = state->m_dvbt_if_agc_cfg; -- } else if (is_qam(state)) { -- rf_agc = state->m_qam_rf_agc_cfg; -- if_agc = state->m_qam_if_agc_cfg; -- } else { -- rf_agc = state->m_atv_rf_agc_cfg; -- if_agc = state->m_atv_if_agc_cfg; -- } -- -- if (rf_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) { -- /* SCU output_level */ -- status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl); -- if (status < 0) -- return status; -- -- /* SCU c.o.c. */ -- read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc); -- if (status < 0) -- return status; -- -- if (((u32) scu_lvl + (u32) scu_coc) < 0xffff) -- rf_agc.output_level = scu_lvl + scu_coc; -- else -- rf_agc.output_level = 0xffff; -- -- /* Take RF gain into account */ -- total_gain += tuner_rf_gain; -- -- /* clip output value */ -- if (rf_agc.output_level < rf_agc.min_output_level) -- rf_agc.output_level = rf_agc.min_output_level; -- if (rf_agc.output_level > rf_agc.max_output_level) -- rf_agc.output_level = rf_agc.max_output_level; -- -- agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level); -- if (agc_range > 0) { -- atten += 100UL * -- ((u32)(tuner_rf_gain)) * -- ((u32)(rf_agc.output_level - rf_agc.min_output_level)) -- / agc_range; -- } -- } -- -- if (if_agc.ctrl_mode == DRXK_AGC_CTRL_AUTO) { -- status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A, -- &if_agc.output_level); -- if (status < 0) -- return status; -- -- status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, -- &if_agc.top); -- if (status < 0) -- return status; -- -- /* Take IF gain into account */ -- total_gain += (u32) tuner_if_gain; -- -- /* clip output value */ -- if (if_agc.output_level < if_agc.min_output_level) -- if_agc.output_level = if_agc.min_output_level; -- if (if_agc.output_level > if_agc.max_output_level) -- if_agc.output_level = if_agc.max_output_level; -- -- agc_range = (u32)(if_agc.max_output_level - if_agc.min_output_level); -- if (agc_range > 0) { -- atten += 100UL * -- ((u32)(tuner_if_gain)) * -- ((u32)(if_agc.output_level - if_agc.min_output_level)) -- / agc_range; -- } -- } -- -- /* -- * Convert to 0..65535 scale. -- * If it can't be measured (AGC is disabled), just show 100%. -- */ -- if (total_gain > 0) -- *strength = (65535UL * atten / total_gain / 100); -- else -- *strength = 65535; -- -- return 0; --} -- --static int drxk_get_stats(struct dvb_frontend *fe) -+static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status) - { -- struct dtv_frontend_properties *c = &fe->dtv_property_cache; - struct drxk_state *state = fe->demodulator_priv; -- int status; - u32 stat; -- u16 reg16; -- u32 post_bit_count; -- u32 post_bit_err_count; -- u32 post_bit_error_scale; -- u32 pre_bit_err_count; -- u32 pre_bit_count; -- u32 pkt_count; -- u32 pkt_error_count; -- s32 cnr; -- -- if (state->m_drxk_state == DRXK_NO_DEV) -- return -ENODEV; -- if (state->m_drxk_state == DRXK_UNINITIALIZED) -- return -EAGAIN; -- -- /* get status */ -- state->fe_status = 0; -- get_lock_status(state, &stat); -+ -+ dprintk(1, "\n"); -+ *status = 0; -+ GetLockStatus(state, &stat, 0); - if (stat == MPEG_LOCK) -- state->fe_status |= 0x1f; -+ *status |= 0x1f; - if (stat == FEC_LOCK) -- state->fe_status |= 0x0f; -+ *status |= 0x0f; - if (stat == DEMOD_LOCK) -- state->fe_status |= 0x07; -- -- /* -- * Estimate signal strength from AGC -- */ -- get_strength(state, &c->strength.stat[0].uvalue); -- c->strength.stat[0].scale = FE_SCALE_RELATIVE; -- -- -- if (stat >= DEMOD_LOCK) { -- get_signal_to_noise(state, &cnr); -- c->cnr.stat[0].svalue = cnr * 100; -- c->cnr.stat[0].scale = FE_SCALE_DECIBEL; -- } else { -- c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- } -- -- if (stat < FEC_LOCK) { -- c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- return 0; -- } -- -- /* Get post BER */ -- -- /* BER measurement is valid if at least FEC lock is achieved */ -- -- /* -- * OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be -- * written to set nr of symbols or bits over which to measure -- * EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg(). -- */ -- -- /* Read registers for post/preViterbi BER calculation */ -- status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16); -- if (status < 0) -- goto error; -- pre_bit_err_count = reg16; -- -- status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16); -- if (status < 0) -- goto error; -- pre_bit_count = reg16; -- -- /* Number of bit-errors */ -- status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16); -- if (status < 0) -- goto error; -- post_bit_err_count = reg16; -- -- status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16); -- if (status < 0) -- goto error; -- post_bit_error_scale = reg16; -- -- status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16); -- if (status < 0) -- goto error; -- pkt_count = reg16; -- -- status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16); -- if (status < 0) -- goto error; -- pkt_error_count = reg16; -- write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0); -- -- post_bit_err_count *= post_bit_error_scale; -- -- post_bit_count = pkt_count * 204 * 8; -- -- /* Store the results */ -- c->block_error.stat[0].scale = FE_SCALE_COUNTER; -- c->block_error.stat[0].uvalue += pkt_error_count; -- c->block_count.stat[0].scale = FE_SCALE_COUNTER; -- c->block_count.stat[0].uvalue += pkt_count; -- -- c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; -- c->pre_bit_error.stat[0].uvalue += pre_bit_err_count; -- c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; -- c->pre_bit_count.stat[0].uvalue += pre_bit_count; -- -- c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; -- c->post_bit_error.stat[0].uvalue += post_bit_err_count; -- c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; -- c->post_bit_count.stat[0].uvalue += post_bit_count; -- --error: -- return status; -+ *status |= 0x07; -+ return 0; - } - -- --static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status) -+static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber) - { -- struct drxk_state *state = fe->demodulator_priv; -- int rc; -- - dprintk(1, "\n"); - -- rc = drxk_get_stats(fe); -- if (rc < 0) -- return rc; -- -- *status = state->fe_status; -- -+ *ber = 0; - return 0; - } - -@@ -6659,16 +6286,11 @@ static int drxk_read_signal_strength(struct dvb_frontend *fe, - u16 *strength) - { - struct drxk_state *state = fe->demodulator_priv; -- struct dtv_frontend_properties *c = &fe->dtv_property_cache; -+ u32 val = 0; - - dprintk(1, "\n"); -- -- if (state->m_drxk_state == DRXK_NO_DEV) -- return -ENODEV; -- if (state->m_drxk_state == DRXK_UNINITIALIZED) -- return -EAGAIN; -- -- *strength = c->strength.stat[0].uvalue; -+ ReadIFAgc(state, &val); -+ *strength = val & 0xffff; - return 0; - } - -@@ -6678,17 +6300,7 @@ static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr) - s32 snr2; - - dprintk(1, "\n"); -- -- if (state->m_drxk_state == DRXK_NO_DEV) -- return -ENODEV; -- if (state->m_drxk_state == DRXK_UNINITIALIZED) -- return -EAGAIN; -- -- get_signal_to_noise(state, &snr2); -- -- /* No negative SNR, clip to zero */ -- if (snr2 < 0) -- snr2 = 0; -+ GetSignalToNoise(state, &snr2); - *snr = snr2 & 0xffff; - return 0; - } -@@ -6699,30 +6311,17 @@ static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) - u16 err; - - dprintk(1, "\n"); -- -- if (state->m_drxk_state == DRXK_NO_DEV) -- return -ENODEV; -- if (state->m_drxk_state == DRXK_UNINITIALIZED) -- return -EAGAIN; -- -- dvbtqam_get_acc_pkt_err(state, &err); -+ DVBTQAMGetAccPktErr(state, &err); - *ucblocks = (u32) err; - return 0; - } - --static int drxk_get_tune_settings(struct dvb_frontend *fe, -- struct dvb_frontend_tune_settings *sets) -+static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings -+ *sets) - { -- struct drxk_state *state = fe->demodulator_priv; - struct dtv_frontend_properties *p = &fe->dtv_property_cache; - - dprintk(1, "\n"); -- -- if (state->m_drxk_state == DRXK_NO_DEV) -- return -ENODEV; -- if (state->m_drxk_state == DRXK_UNINITIALIZED) -- return -EAGAIN; -- - switch (p->delivery_system) { - case SYS_DVBC_ANNEX_A: - case SYS_DVBC_ANNEX_C: -@@ -6764,6 +6363,7 @@ static struct dvb_frontend_ops drxk_ops = { - .get_tune_settings = drxk_get_tune_settings, - - .read_status = drxk_read_status, -+ .read_ber = drxk_read_ber, - .read_signal_strength = drxk_read_signal_strength, - .read_snr = drxk_read_snr, - .read_ucblocks = drxk_read_ucblocks, -@@ -6772,10 +6372,10 @@ static struct dvb_frontend_ops drxk_ops = { - struct dvb_frontend *drxk_attach(const struct drxk_config *config, - struct i2c_adapter *i2c) - { -- struct dtv_frontend_properties *p; -+ int n; -+ - struct drxk_state *state = NULL; - u8 adr = config->adr; -- int status; - - dprintk(1, "\n"); - state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL); -@@ -6786,40 +6386,39 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config, - state->demod_address = adr; - state->single_master = config->single_master; - state->microcode_name = config->microcode_name; -- state->qam_demod_parameter_count = config->qam_demod_parameter_count; - state->no_i2c_bridge = config->no_i2c_bridge; - state->antenna_gpio = config->antenna_gpio; - state->antenna_dvbt = config->antenna_dvbt; -- state->m_chunk_size = config->chunk_size; -+ state->m_ChunkSize = config->chunk_size; - state->enable_merr_cfg = config->enable_merr_cfg; - - if (config->dynamic_clk) { -- state->m_dvbt_static_clk = false; -- state->m_dvbc_static_clk = false; -+ state->m_DVBTStaticCLK = 0; -+ state->m_DVBCStaticCLK = 0; - } else { -- state->m_dvbt_static_clk = true; -- state->m_dvbc_static_clk = true; -+ state->m_DVBTStaticCLK = 1; -+ state->m_DVBCStaticCLK = 1; - } - - - if (config->mpeg_out_clk_strength) -- state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07; -+ state->m_TSClockkStrength = config->mpeg_out_clk_strength & 0x07; - else -- state->m_ts_clockk_strength = 0x06; -+ state->m_TSClockkStrength = 0x06; - - if (config->parallel_ts) -- state->m_enable_parallel = true; -+ state->m_enableParallel = true; - else -- state->m_enable_parallel = false; -+ state->m_enableParallel = false; - - /* NOTE: as more UIO bits will be used, add them to the mask */ -- state->uio_mask = config->antenna_gpio; -+ state->UIO_mask = config->antenna_gpio; - - /* Default gpio to DVB-C */ - if (!state->antenna_dvbt && state->antenna_gpio) -- state->m_gpio |= state->antenna_gpio; -+ state->m_GPIO |= state->antenna_gpio; - else -- state->m_gpio &= ~state->antenna_gpio; -+ state->m_GPIO &= ~state->antenna_gpio; - - mutex_init(&state->mutex); - -@@ -6827,45 +6426,28 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config, - state->frontend.demodulator_priv = state; - - init_state(state); -- -- /* Load firmware and initialize DRX-K */ -- if (state->microcode_name) { -- const struct firmware *fw = NULL; -- -- status = request_firmware(&fw, state->microcode_name, -- state->i2c->dev.parent); -- if (status < 0) -- fw = NULL; -- load_firmware_cb(fw, state); -- } else if (init_drxk(state) < 0) -+ if (init_drxk(state) < 0) - goto error; - -+ /* Initialize the supported delivery systems */ -+ n = 0; -+ if (state->m_hasDVBC) { -+ state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; -+ state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; -+ strlcat(state->frontend.ops.info.name, " DVB-C", -+ sizeof(state->frontend.ops.info.name)); -+ } -+ if (state->m_hasDVBT) { -+ state->frontend.ops.delsys[n++] = SYS_DVBT; -+ strlcat(state->frontend.ops.info.name, " DVB-T", -+ sizeof(state->frontend.ops.info.name)); -+ } - -- /* Initialize stats */ -- p = &state->frontend.dtv_property_cache; -- p->strength.len = 1; -- p->cnr.len = 1; -- p->block_error.len = 1; -- p->block_count.len = 1; -- p->pre_bit_error.len = 1; -- p->pre_bit_count.len = 1; -- p->post_bit_error.len = 1; -- p->post_bit_count.len = 1; -- -- p->strength.stat[0].scale = FE_SCALE_RELATIVE; -- p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; -- -- pr_info("frontend initialized.\n"); -+ printk(KERN_INFO "drxk: frontend initialized.\n"); - return &state->frontend; - - error: -- pr_err("not found\n"); -+ printk(KERN_ERR "drxk: not found\n"); - kfree(state); - return NULL; - } -diff --git a/drivers/media/dvb-frontends/drxk_hard.h b/drivers/media/dvb-frontends/drxk_hard.h -index bae9c71..4bbf841 100644 ---- a/drivers/media/dvb-frontends/drxk_hard.h -+++ b/drivers/media/dvb-frontends/drxk_hard.h -@@ -46,7 +46,7 @@ - #define IQM_RC_ADJ_SEL_B_QAM 0x1 - #define IQM_RC_ADJ_SEL_B_VSB 0x2 - --enum operation_mode { -+enum OperationMode { - OM_NONE, - OM_QAM_ITU_A, - OM_QAM_ITU_B, -@@ -54,7 +54,7 @@ enum operation_mode { - OM_DVBT - }; - --enum drx_power_mode { -+enum DRXPowerMode { - DRX_POWER_UP = 0, - DRX_POWER_MODE_1, - DRX_POWER_MODE_2, -@@ -77,38 +77,25 @@ enum drx_power_mode { - }; - - --/* Intermediate power mode for DRXK, power down OFDM clock domain */ -+/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */ - #ifndef DRXK_POWER_DOWN_OFDM - #define DRXK_POWER_DOWN_OFDM DRX_POWER_MODE_1 - #endif - --/* Intermediate power mode for DRXK, power down core (sysclk) */ -+/** /brief Intermediate power mode for DRXK, power down core (sysclk) */ - #ifndef DRXK_POWER_DOWN_CORE - #define DRXK_POWER_DOWN_CORE DRX_POWER_MODE_9 - #endif - --/* Intermediate power mode for DRXK, power down pll (only osc runs) */ -+/** /brief Intermediate power mode for DRXK, power down pll (only osc runs) */ - #ifndef DRXK_POWER_DOWN_PLL - #define DRXK_POWER_DOWN_PLL DRX_POWER_MODE_10 - #endif - - --enum agc_ctrl_mode { -- DRXK_AGC_CTRL_AUTO = 0, -- DRXK_AGC_CTRL_USER, -- DRXK_AGC_CTRL_OFF --}; -- --enum e_drxk_state { -- DRXK_UNINITIALIZED = 0, -- DRXK_STOPPED, -- DRXK_DTV_STARTED, -- DRXK_ATV_STARTED, -- DRXK_POWERED_DOWN, -- DRXK_NO_DEV /* If drxk init failed */ --}; -- --enum e_drxk_coef_array_index { -+enum AGC_CTRL_MODE { DRXK_AGC_CTRL_AUTO = 0, DRXK_AGC_CTRL_USER, DRXK_AGC_CTRL_OFF }; -+enum EDrxkState { DRXK_UNINITIALIZED = 0, DRXK_STOPPED, DRXK_DTV_STARTED, DRXK_ATV_STARTED, DRXK_POWERED_DOWN }; -+enum EDrxkCoefArrayIndex { - DRXK_COEF_IDX_MN = 0, - DRXK_COEF_IDX_FM , - DRXK_COEF_IDX_L , -@@ -118,13 +105,13 @@ enum e_drxk_coef_array_index { - DRXK_COEF_IDX_I , - DRXK_COEF_IDX_MAX - }; --enum e_drxk_sif_attenuation { -+enum EDrxkSifAttenuation { - DRXK_SIF_ATTENUATION_0DB, - DRXK_SIF_ATTENUATION_3DB, - DRXK_SIF_ATTENUATION_6DB, - DRXK_SIF_ATTENUATION_9DB - }; --enum e_drxk_constellation { -+enum EDrxkConstellation { - DRX_CONSTELLATION_BPSK = 0, - DRX_CONSTELLATION_QPSK, - DRX_CONSTELLATION_PSK8, -@@ -138,7 +125,7 @@ enum e_drxk_constellation { - DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, - DRX_CONSTELLATION_AUTO = DRX_AUTO - }; --enum e_drxk_interleave_mode { -+enum EDrxkInterleaveMode { - DRXK_QAM_I12_J17 = 16, - DRXK_QAM_I_UNKNOWN = DRX_UNKNOWN - }; -@@ -149,14 +136,14 @@ enum { - DRXK_SPIN_UNKNOWN - }; - --enum drxk_cfg_dvbt_sqi_speed { -+enum DRXKCfgDvbtSqiSpeed { - DRXK_DVBT_SQI_SPEED_FAST = 0, - DRXK_DVBT_SQI_SPEED_MEDIUM, - DRXK_DVBT_SQI_SPEED_SLOW, - DRXK_DVBT_SQI_SPEED_UNKNOWN = DRX_UNKNOWN - } ; - --enum drx_fftmode_t { -+enum DRXFftmode_t { - DRX_FFTMODE_2K = 0, - DRX_FFTMODE_4K, - DRX_FFTMODE_8K, -@@ -164,47 +151,47 @@ enum drx_fftmode_t { - DRX_FFTMODE_AUTO = DRX_AUTO - }; - --enum drxmpeg_str_width_t { -+enum DRXMPEGStrWidth_t { - DRX_MPEG_STR_WIDTH_1, - DRX_MPEG_STR_WIDTH_8 - }; - --enum drx_qam_lock_range_t { -+enum DRXQamLockRange_t { - DRX_QAM_LOCKRANGE_NORMAL, - DRX_QAM_LOCKRANGE_EXTENDED - }; - --struct drxk_cfg_dvbt_echo_thres_t { -+struct DRXKCfgDvbtEchoThres_t { - u16 threshold; -- enum drx_fftmode_t fft_mode; -+ enum DRXFftmode_t fftMode; - } ; - --struct s_cfg_agc { -- enum agc_ctrl_mode ctrl_mode; /* off, user, auto */ -- u16 output_level; /* range dependent on AGC */ -- u16 min_output_level; /* range dependent on AGC */ -- u16 max_output_level; /* range dependent on AGC */ -+struct SCfgAgc { -+ enum AGC_CTRL_MODE ctrlMode; /* off, user, auto */ -+ u16 outputLevel; /* range dependent on AGC */ -+ u16 minOutputLevel; /* range dependent on AGC */ -+ u16 maxOutputLevel; /* range dependent on AGC */ - u16 speed; /* range dependent on AGC */ - u16 top; /* rf-agc take over point */ -- u16 cut_off_current; /* rf-agc is accelerated if output current -+ u16 cutOffCurrent; /* rf-agc is accelerated if output current - is below cut-off current */ -- u16 ingain_tgt_max; -- u16 fast_clip_ctrl_delay; -+ u16 IngainTgtMax; -+ u16 FastClipCtrlDelay; - }; - --struct s_cfg_pre_saw { -+struct SCfgPreSaw { - u16 reference; /* pre SAW reference value, range 0 .. 31 */ -- bool use_pre_saw; /* TRUE algorithms must use pre SAW sense */ -+ bool usePreSaw; /* TRUE algorithms must use pre SAW sense */ - }; - --struct drxk_ofdm_sc_cmd_t { -- u16 cmd; /* Command number */ -- u16 subcmd; /* Sub-command parameter*/ -- u16 param0; /* General purpous param */ -- u16 param1; /* General purpous param */ -- u16 param2; /* General purpous param */ -- u16 param3; /* General purpous param */ -- u16 param4; /* General purpous param */ -+struct DRXKOfdmScCmd_t { -+ u16 cmd; /**< Command number */ -+ u16 subcmd; /**< Sub-command parameter*/ -+ u16 param0; /**< General purpous param */ -+ u16 param1; /**< General purpous param */ -+ u16 param2; /**< General purpous param */ -+ u16 param3; /**< General purpous param */ -+ u16 param4; /**< General purpous param */ - }; - - struct drxk_state { -@@ -218,131 +205,132 @@ struct drxk_state { - - struct mutex mutex; - -- u32 m_instance; /* Channel 1,2,3 or 4 */ -- -- int m_chunk_size; -- u8 chunk[256]; -- -- bool m_has_lna; -- bool m_has_dvbt; -- bool m_has_dvbc; -- bool m_has_audio; -- bool m_has_atv; -- bool m_has_oob; -- bool m_has_sawsw; /* TRUE if mat_tx is available */ -- bool m_has_gpio1; /* TRUE if mat_rx is available */ -- bool m_has_gpio2; /* TRUE if GPIO is available */ -- bool m_has_irqn; /* TRUE if IRQN is available */ -- u16 m_osc_clock_freq; -- u16 m_hi_cfg_timing_div; -- u16 m_hi_cfg_bridge_delay; -- u16 m_hi_cfg_wake_up_key; -- u16 m_hi_cfg_timeout; -- u16 m_hi_cfg_ctrl; -- s32 m_sys_clock_freq; /* system clock frequency in kHz */ -- -- enum e_drxk_state m_drxk_state; /* State of Drxk (init,stopped,started) */ -- enum operation_mode m_operation_mode; /* digital standards */ -- struct s_cfg_agc m_vsb_rf_agc_cfg; /* settings for VSB RF-AGC */ -- struct s_cfg_agc m_vsb_if_agc_cfg; /* settings for VSB IF-AGC */ -- u16 m_vsb_pga_cfg; /* settings for VSB PGA */ -- struct s_cfg_pre_saw m_vsb_pre_saw_cfg; /* settings for pre SAW sense */ -- s32 m_Quality83percent; /* MER level (*0.1 dB) for 83% quality indication */ -- s32 m_Quality93percent; /* MER level (*0.1 dB) for 93% quality indication */ -- bool m_smart_ant_inverted; -- bool m_b_debug_enable_bridge; -- bool m_b_p_down_open_bridge; /* only open DRXK bridge before power-down once it has been accessed */ -- bool m_b_power_down; /* Power down when not used */ -- -- u32 m_iqm_fs_rate_ofs; /* frequency shift as written to DRXK register (28bit fixpoint) */ -- -- bool m_enable_mpeg_output; /* If TRUE, enable MPEG output */ -- bool m_insert_rs_byte; /* If TRUE, insert RS byte */ -- bool m_enable_parallel; /* If TRUE, parallel out otherwise serial */ -- bool m_invert_data; /* If TRUE, invert DATA signals */ -- bool m_invert_err; /* If TRUE, invert ERR signal */ -- bool m_invert_str; /* If TRUE, invert STR signals */ -- bool m_invert_val; /* If TRUE, invert VAL signals */ -- bool m_invert_clk; /* If TRUE, invert CLK signals */ -- bool m_dvbc_static_clk; -- bool m_dvbt_static_clk; /* If TRUE, static MPEG clockrate will -+ u32 m_Instance; /**< Channel 1,2,3 or 4 */ -+ -+ int m_ChunkSize; -+ u8 Chunk[256]; -+ -+ bool m_hasLNA; -+ bool m_hasDVBT; -+ bool m_hasDVBC; -+ bool m_hasAudio; -+ bool m_hasATV; -+ bool m_hasOOB; -+ bool m_hasSAWSW; /**< TRUE if mat_tx is available */ -+ bool m_hasGPIO1; /**< TRUE if mat_rx is available */ -+ bool m_hasGPIO2; /**< TRUE if GPIO is available */ -+ bool m_hasIRQN; /**< TRUE if IRQN is available */ -+ u16 m_oscClockFreq; -+ u16 m_HICfgTimingDiv; -+ u16 m_HICfgBridgeDelay; -+ u16 m_HICfgWakeUpKey; -+ u16 m_HICfgTimeout; -+ u16 m_HICfgCtrl; -+ s32 m_sysClockFreq; /**< system clock frequency in kHz */ -+ -+ enum EDrxkState m_DrxkState; /**< State of Drxk (init,stopped,started) */ -+ enum OperationMode m_OperationMode; /**< digital standards */ -+ struct SCfgAgc m_vsbRfAgcCfg; /**< settings for VSB RF-AGC */ -+ struct SCfgAgc m_vsbIfAgcCfg; /**< settings for VSB IF-AGC */ -+ u16 m_vsbPgaCfg; /**< settings for VSB PGA */ -+ struct SCfgPreSaw m_vsbPreSawCfg; /**< settings for pre SAW sense */ -+ s32 m_Quality83percent; /**< MER level (*0.1 dB) for 83% quality indication */ -+ s32 m_Quality93percent; /**< MER level (*0.1 dB) for 93% quality indication */ -+ bool m_smartAntInverted; -+ bool m_bDebugEnableBridge; -+ bool m_bPDownOpenBridge; /**< only open DRXK bridge before power-down once it has been accessed */ -+ bool m_bPowerDown; /**< Power down when not used */ -+ -+ u32 m_IqmFsRateOfs; /**< frequency shift as written to DRXK register (28bit fixpoint) */ -+ -+ bool m_enableMPEGOutput; /**< If TRUE, enable MPEG output */ -+ bool m_insertRSByte; /**< If TRUE, insert RS byte */ -+ bool m_enableParallel; /**< If TRUE, parallel out otherwise serial */ -+ bool m_invertDATA; /**< If TRUE, invert DATA signals */ -+ bool m_invertERR; /**< If TRUE, invert ERR signal */ -+ bool m_invertSTR; /**< If TRUE, invert STR signals */ -+ bool m_invertVAL; /**< If TRUE, invert VAL signals */ -+ bool m_invertCLK; /**< If TRUE, invert CLK signals */ -+ bool m_DVBCStaticCLK; -+ bool m_DVBTStaticCLK; /**< If TRUE, static MPEG clockrate will - be used, otherwise clockrate will - adapt to the bitrate of the TS */ -- u32 m_dvbt_bitrate; -- u32 m_dvbc_bitrate; -+ u32 m_DVBTBitrate; -+ u32 m_DVBCBitrate; - -- u8 m_ts_data_strength; -- u8 m_ts_clockk_strength; -+ u8 m_TSDataStrength; -+ u8 m_TSClockkStrength; - - bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */ - -- enum drxmpeg_str_width_t m_width_str; /* MPEG start width */ -- u32 m_mpeg_ts_static_bitrate; /* Maximum bitrate in b/s in case -+ enum DRXMPEGStrWidth_t m_widthSTR; /**< MPEG start width */ -+ u32 m_mpegTsStaticBitrate; /**< Maximum bitrate in b/s in case - static clockrate is selected */ - -- /* LARGE_INTEGER m_startTime; */ /* Contains the time of the last demod start */ -- s32 m_mpeg_lock_time_out; /* WaitForLockStatus Timeout (counts from start time) */ -- s32 m_demod_lock_time_out; /* WaitForLockStatus Timeout (counts from start time) */ -- -- bool m_disable_te_ihandling; -- -- bool m_rf_agc_pol; -- bool m_if_agc_pol; -- -- struct s_cfg_agc m_atv_rf_agc_cfg; /* settings for ATV RF-AGC */ -- struct s_cfg_agc m_atv_if_agc_cfg; /* settings for ATV IF-AGC */ -- struct s_cfg_pre_saw m_atv_pre_saw_cfg; /* settings for ATV pre SAW sense */ -- bool m_phase_correction_bypass; -- s16 m_atv_top_vid_peak; -- u16 m_atv_top_noise_th; -- enum e_drxk_sif_attenuation m_sif_attenuation; -- bool m_enable_cvbs_output; -- bool m_enable_sif_output; -- bool m_b_mirror_freq_spect; -- enum e_drxk_constellation m_constellation; /* constellation type of the channel */ -- u32 m_curr_symbol_rate; /* Current QAM symbol rate */ -- struct s_cfg_agc m_qam_rf_agc_cfg; /* settings for QAM RF-AGC */ -- struct s_cfg_agc m_qam_if_agc_cfg; /* settings for QAM IF-AGC */ -- u16 m_qam_pga_cfg; /* settings for QAM PGA */ -- struct s_cfg_pre_saw m_qam_pre_saw_cfg; /* settings for QAM pre SAW sense */ -- enum e_drxk_interleave_mode m_qam_interleave_mode; /* QAM Interleave mode */ -- u16 m_fec_rs_plen; -- u16 m_fec_rs_prescale; -- -- enum drxk_cfg_dvbt_sqi_speed m_sqi_speed; -- -- u16 m_gpio; -- u16 m_gpio_cfg; -- -- struct s_cfg_agc m_dvbt_rf_agc_cfg; /* settings for QAM RF-AGC */ -- struct s_cfg_agc m_dvbt_if_agc_cfg; /* settings for QAM IF-AGC */ -- struct s_cfg_pre_saw m_dvbt_pre_saw_cfg; /* settings for QAM pre SAW sense */ -- -- u16 m_agcfast_clip_ctrl_delay; -- bool m_adc_comp_passed; -+ /* LARGE_INTEGER m_StartTime; */ /**< Contains the time of the last demod start */ -+ s32 m_MpegLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */ -+ s32 m_DemodLockTimeOut; /**< WaitForLockStatus Timeout (counts from start time) */ -+ -+ bool m_disableTEIhandling; -+ -+ bool m_RfAgcPol; -+ bool m_IfAgcPol; -+ -+ struct SCfgAgc m_atvRfAgcCfg; /**< settings for ATV RF-AGC */ -+ struct SCfgAgc m_atvIfAgcCfg; /**< settings for ATV IF-AGC */ -+ struct SCfgPreSaw m_atvPreSawCfg; /**< settings for ATV pre SAW sense */ -+ bool m_phaseCorrectionBypass; -+ s16 m_atvTopVidPeak; -+ u16 m_atvTopNoiseTh; -+ enum EDrxkSifAttenuation m_sifAttenuation; -+ bool m_enableCVBSOutput; -+ bool m_enableSIFOutput; -+ bool m_bMirrorFreqSpect; -+ enum EDrxkConstellation m_Constellation; /**< Constellation type of the channel */ -+ u32 m_CurrSymbolRate; /**< Current QAM symbol rate */ -+ struct SCfgAgc m_qamRfAgcCfg; /**< settings for QAM RF-AGC */ -+ struct SCfgAgc m_qamIfAgcCfg; /**< settings for QAM IF-AGC */ -+ u16 m_qamPgaCfg; /**< settings for QAM PGA */ -+ struct SCfgPreSaw m_qamPreSawCfg; /**< settings for QAM pre SAW sense */ -+ enum EDrxkInterleaveMode m_qamInterleaveMode; /**< QAM Interleave mode */ -+ u16 m_fecRsPlen; -+ u16 m_fecRsPrescale; -+ -+ enum DRXKCfgDvbtSqiSpeed m_sqiSpeed; -+ -+ u16 m_GPIO; -+ u16 m_GPIOCfg; -+ -+ struct SCfgAgc m_dvbtRfAgcCfg; /**< settings for QAM RF-AGC */ -+ struct SCfgAgc m_dvbtIfAgcCfg; /**< settings for QAM IF-AGC */ -+ struct SCfgPreSaw m_dvbtPreSawCfg; /**< settings for QAM pre SAW sense */ -+ -+ u16 m_agcFastClipCtrlDelay; -+ bool m_adcCompPassed; - u16 m_adcCompCoef[64]; -- u16 m_adc_state; -+ u16 m_adcState; - - u8 *m_microcode; - int m_microcode_length; -- bool m_drxk_a3_rom_code; -- bool m_drxk_a3_patch_code; -+ bool m_DRXK_A1_PATCH_CODE; -+ bool m_DRXK_A1_ROM_CODE; -+ bool m_DRXK_A2_ROM_CODE; -+ bool m_DRXK_A3_ROM_CODE; -+ bool m_DRXK_A2_PATCH_CODE; -+ bool m_DRXK_A3_PATCH_CODE; - - bool m_rfmirror; -- u8 m_device_spin; -- u32 m_iqm_rc_rate; -- -- enum drx_power_mode m_current_power_mode; -+ u8 m_deviceSpin; -+ u32 m_iqmRcRate; - -- /* when true, avoids other devices to use the I2C bus */ -- bool drxk_i2c_exclusive_lock; -+ enum DRXPowerMode m_currentPowerMode; - - /* - * Configurable parameters at the driver. They stores the values found - * at struct drxk_config. - */ - -- u16 uio_mask; /* Bits used by UIO */ -+ u16 UIO_mask; /* Bits used by UIO */ - - bool enable_merr_cfg; - bool single_master; -@@ -350,13 +338,7 @@ struct drxk_state { - bool antenna_dvbt; - u16 antenna_gpio; - -- fe_status_t fe_status; -- -- /* Firmware */ - const char *microcode_name; -- struct completion fw_wait_load; -- const struct firmware *fw; -- int qam_demod_parameter_count; - }; - - #define NEVER_LOCK 0 -diff --git a/drivers/media/dvb-frontends/drxk_map.h b/drivers/media/dvb-frontends/drxk_map.h -index 761613f..23e16c1 100644 ---- a/drivers/media/dvb-frontends/drxk_map.h -+++ b/drivers/media/dvb-frontends/drxk_map.h -@@ -10,7 +10,6 @@ - #define FEC_RS_COMM_EXEC_STOP 0x0 - #define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012 - #define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013 --#define FEC_RS_NR_BIT_ERRORS__A 0x1C30014 - #define FEC_OC_MODE__A 0x1C40011 - #define FEC_OC_MODE_PARITY__M 0x1 - #define FEC_OC_DTO_MODE__A 0x1C40014 -@@ -130,8 +129,6 @@ - #define OFDM_EC_SB_PRIOR__A 0x3410013 - #define OFDM_EC_SB_PRIOR_HI 0x0 - #define OFDM_EC_SB_PRIOR_LO 0x1 --#define OFDM_EC_VD_ERR_BIT_CNT__A 0x3420017 --#define OFDM_EC_VD_IN_BIT_CNT__A 0x3420018 - #define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054 - #define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3 - #define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2 -diff --git a/drivers/media/dvb-frontends/lnbh25.c b/drivers/media/dvb-frontends/lnbh25.c ++#endif /* _CXD2843_H_ */ +diff --git a/drivers/media/dvb-frontends/mxl5xx.c b/drivers/media/dvb-frontends/mxl5xx.c new file mode 100644 -index 0000000..f167e67 +index 0000000..29bebed --- /dev/null -+++ b/drivers/media/dvb-frontends/lnbh25.c -@@ -0,0 +1,153 @@ ++++ b/drivers/media/dvb-frontends/mxl5xx.c +@@ -0,0 +1,1738 @@ +/* -+ * Driver for the ST LNBH25 ++ * Driver for the Maxlinear MX58x family of tuners/demods + * -+ * Copyright (C) 2014 Digital Devices GmbH ++ * Copyright (C) 2014-2015 Ralph Metzler ++ * Marcus Metzler ++ * developed for Digital Devices GmbH ++ * ++ * based on code: ++ * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved ++ * which was released under GPL V2 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License -+ * version 2 only, as published by the Free Software Foundation. ++ * version 2, as published by the Free Software Foundation. + * + * + * This program is distributed in the hope that it will be useful, @@ -9584,176 +2957,3537 @@ index 0000000..f167e67 + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + ++#undef pr_fmt ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + -+#include -+#include -+#include +#include +#include -+#include -+#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include + +#include "dvb_frontend.h" -+#include "lnbh25.h" ++#include "mxl5xx.h" ++#include "mxl5xx_regs.h" ++#include "mxl5xx_defs.h" + -+struct lnbh25 { -+ struct i2c_adapter *i2c; -+ u8 adr; -+ u8 reg[4]; -+ u8 boost; ++#define BYTE0(v) ((v >> 0) & 0xff) ++#define BYTE1(v) ((v >> 8) & 0xff) ++#define BYTE2(v) ((v >> 16) & 0xff) ++#define BYTE3(v) ((v >> 24) & 0xff) ++ ++ ++LIST_HEAD(mxllist); ++ ++struct mxl_base { ++ struct list_head mxllist; ++ struct list_head mxls; ++ ++ u8 adr; ++ struct i2c_adapter *i2c; ++ ++ u32 count; ++ u32 type; ++ u32 sku_type; ++ u32 chipversion; ++ u32 clock; ++ u32 fwversion; ++ ++ u8 *ts_map; ++ u8 can_clkout; ++ u8 chan_bond; ++ u8 demod_num; ++ u8 tuner_num; ++ ++ unsigned long next_tune; ++ ++ struct mutex i2c_lock; ++ struct mutex status_lock; ++ struct mutex tune_lock; ++ ++ u8 buf[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN]; ++ ++ u32 cmd_size; ++ u8 cmd_data[MAX_CMD_DATA]; +}; + -+static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) ++struct mxl { ++ struct list_head mxl; ++ ++ struct mxl_base *base; ++ struct dvb_frontend fe; ++ u32 demod; ++ u32 tuner; ++ u32 tuner_in_use; ++ ++ unsigned long tune_time; ++}; ++ ++static void convert_endian(u8 flag, u32 size, u8 *d) ++{ ++ u32 i; ++ ++ if (!flag) ++ return; ++ for (i = 0; i < (size & ~3); i += 4) { ++ d[i + 0] ^= d[i + 3]; ++ d[i + 3] ^= d[i + 0]; ++ d[i + 0] ^= d[i + 3]; ++ ++ d[i + 1] ^= d[i + 2]; ++ d[i + 2] ^= d[i + 1]; ++ d[i + 1] ^= d[i + 2]; ++ } ++ ++ switch (size & 3) { ++ case 0: ++ case 1: ++ /* do nothing */ ++ break; ++ case 2: ++ d[i + 0] ^= d[i + 1]; ++ d[i + 1] ^= d[i + 0]; ++ d[i + 0] ^= d[i + 1]; ++ break; ++ ++ case 3: ++ d[i + 0] ^= d[i + 2]; ++ d[i + 2] ^= d[i + 0]; ++ d[i + 0] ^= d[i + 2]; ++ break; ++ } ++ ++} ++ ++static int i2c_write(struct i2c_adapter *adap, u8 adr, ++ u8 *data, u32 len) +{ + struct i2c_msg msg = {.addr = adr, .flags = 0, + .buf = data, .len = len}; + -+ if (i2c_transfer(adap, &msg, 1) != 1) { -+ pr_err("lnbh25: i2c_write error\n"); ++ return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; ++} ++ ++static int i2c_read(struct i2c_adapter *adap, u8 adr, ++ u8 *data, u32 len) ++{ ++ struct i2c_msg msg = {.addr = adr, .flags = I2C_M_RD, ++ .buf = data, .len = len}; ++ ++ return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; ++} ++ ++static int i2cread(struct mxl *state, u8 *data, int len) ++{ ++ return i2c_read(state->base->i2c, state->base->adr, data, len); ++} ++ ++static int i2cwrite(struct mxl *state, u8 *data, int len) ++{ ++ return i2c_write(state->base->i2c, state->base->adr, data, len); ++} ++ ++static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val) ++{ ++ int stat; ++ u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = { ++ MXL_HYDRA_PLID_REG_READ, 0x04, ++ GET_BYTE(reg, 0), GET_BYTE(reg, 1), ++ GET_BYTE(reg, 2), GET_BYTE(reg, 3), ++ }; ++ ++ stat = i2cwrite(state, data, ++ MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE); ++ if (stat) ++ pr_err("i2c read error 1\n"); ++ if (!stat) ++ stat = i2cread(state, (u8 *) val, MXL_HYDRA_REG_SIZE_IN_BYTES); ++ le32_to_cpus(val); ++ if (stat) ++ pr_err("i2c read error 2\n"); ++ return stat; ++} ++ ++ ++#define DMA_I2C_INTERRUPT_ADDR 0x8000011C ++#define DMA_INTR_PROT_WR_CMP 0x08 ++ ++static int send_command(struct mxl *state, u32 size, u8 *buf) ++{ ++ int stat; ++ u32 val, count = 10; ++ ++ mutex_lock(&state->base->i2c_lock); ++ if (state->base->fwversion > 0x02010109) { ++ read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, &val); ++ if (DMA_INTR_PROT_WR_CMP & val) ++ pr_info("send_command busy\n"); ++ while ((DMA_INTR_PROT_WR_CMP & val) && --count) { ++ mutex_unlock(&state->base->i2c_lock); ++ usleep_range(1000, 2000); ++ mutex_lock(&state->base->i2c_lock); ++ read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, &val); ++ } ++ if (!count) { ++ pr_info("send_command busy\n"); ++ mutex_unlock(&state->base->i2c_lock); ++ return -EBUSY; ++ } ++ } ++ stat = i2cwrite(state, buf, size); ++ mutex_unlock(&state->base->i2c_lock); ++ return stat; ++} ++ ++static int write_register(struct mxl *state, u32 reg, u32 val) ++{ ++ int stat; ++ u8 data[MXL_HYDRA_REG_WRITE_LEN] = { ++ MXL_HYDRA_PLID_REG_WRITE, 0x08, ++ BYTE0(reg), BYTE1(reg), BYTE2(reg), BYTE3(reg), ++ BYTE0(val), BYTE1(val), BYTE2(val), BYTE3(val), ++ }; ++ mutex_lock(&state->base->i2c_lock); ++ stat = i2cwrite(state, data, sizeof(data)); ++ mutex_unlock(&state->base->i2c_lock); ++ if (stat) ++ pr_err("i2c write error\n"); ++ return stat; ++} ++ ++static int write_firmware_block(struct mxl *state, ++ u32 reg, u32 size, u8 *regDataPtr) ++{ ++ int stat; ++ u8 *buf = state->base->buf; ++ ++ mutex_lock(&state->base->i2c_lock); ++ buf[0] = MXL_HYDRA_PLID_REG_WRITE; ++ buf[1] = size + 4; ++ buf[2] = GET_BYTE(reg, 0); ++ buf[3] = GET_BYTE(reg, 1); ++ buf[4] = GET_BYTE(reg, 2); ++ buf[5] = GET_BYTE(reg, 3); ++ memcpy(&buf[6], regDataPtr, size); ++ stat = i2cwrite(state, buf, ++ MXL_HYDRA_I2C_HDR_SIZE + ++ MXL_HYDRA_REG_SIZE_IN_BYTES + size); ++ mutex_unlock(&state->base->i2c_lock); ++ if (stat) ++ pr_err("fw block write failed\n"); ++ return stat; ++} ++ ++static int read_register(struct mxl *state, u32 reg, u32 *val) ++{ ++ int stat; ++ u8 data[MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE] = { ++ MXL_HYDRA_PLID_REG_READ, 0x04, ++ GET_BYTE(reg, 0), GET_BYTE(reg, 1), ++ GET_BYTE(reg, 2), GET_BYTE(reg, 3), ++ }; ++ ++ mutex_lock(&state->base->i2c_lock); ++ stat = i2cwrite(state, data, ++ MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE); ++ if (stat) ++ pr_err("i2c read error 1\n"); ++ if (!stat) ++ stat = i2cread(state, (u8 *) val, MXL_HYDRA_REG_SIZE_IN_BYTES); ++ mutex_unlock(&state->base->i2c_lock); ++ le32_to_cpus(val); ++ if (stat) ++ pr_err("i2c read error 2\n"); ++ return stat; ++} ++ ++static int read_register_block(struct mxl *state, u32 reg, u32 size, u8 *data) ++{ ++ int stat; ++ u8 *buf = state->base->buf; ++ ++ mutex_lock(&state->base->i2c_lock); ++ ++ buf[0] = MXL_HYDRA_PLID_REG_READ; ++ buf[1] = size + 4; ++ buf[2] = GET_BYTE(reg, 0); ++ buf[3] = GET_BYTE(reg, 1); ++ buf[4] = GET_BYTE(reg, 2); ++ buf[5] = GET_BYTE(reg, 3); ++ stat = i2cwrite(state, buf, ++ MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES); ++ if (!stat) { ++ stat = i2cread(state, data, size); ++ convert_endian(MXL_ENABLE_BIG_ENDIAN, size, data); ++ } ++ mutex_unlock(&state->base->i2c_lock); ++ return stat; ++} ++ ++static int read_by_mnemonic(struct mxl *state, ++ u32 reg, u8 lsbloc, u8 numofbits, u32 *val) ++{ ++ u32 data = 0, mask = 0; ++ int stat; ++ ++ stat = read_register(state, reg, &data); ++ if (stat) ++ return stat; ++ mask = MXL_GET_REG_MASK_32(lsbloc, numofbits); ++ data &= mask; ++ data >>= lsbloc; ++ *val = data; ++ return 0; ++} ++ ++ ++static int update_by_mnemonic(struct mxl *state, ++ u32 reg, u8 lsbloc, u8 numofbits, u32 val) ++{ ++ u32 data, mask; ++ int stat; ++ ++ stat = read_register(state, reg, &data); ++ if (stat) ++ return stat; ++ mask = MXL_GET_REG_MASK_32(lsbloc, numofbits); ++ data = (data & ~mask) | ((val << lsbloc) & mask); ++ stat = write_register(state, reg, data); ++ return stat; ++} ++ ++static int firmware_is_alive(struct mxl *state) ++{ ++ u32 hb0, hb1; ++ ++ if (read_register(state, HYDRA_HEAR_BEAT, &hb0)) ++ return 0; ++ msleep(20); ++ if (read_register(state, HYDRA_HEAR_BEAT, &hb1)) ++ return 0; ++ if (hb1 == hb0) ++ return 0; ++ return 1; ++} ++ ++static int init(struct dvb_frontend *fe) ++{ ++ return 0; ++} ++ ++static void release(struct dvb_frontend *fe) ++{ ++ struct mxl *state = fe->demodulator_priv; ++ ++ list_del(&state->mxl); ++ /* Release one frontend, two more shall take its place! */ ++ state->base->count--; ++ if (state->base->count == 0) { ++ list_del(&state->base->mxllist); ++ kfree(state->base); ++ } ++ kfree(state); ++} ++ ++static int get_algo(struct dvb_frontend *fe) ++{ ++ return DVBFE_ALGO_HW; ++} ++ ++static int CfgDemodAbortTune(struct mxl *state) ++{ ++ MXL_HYDRA_DEMOD_ABORT_TUNE_T abortTuneCmd; ++ u8 cmdSize = sizeof(abortTuneCmd); ++ u8 cmdBuff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN]; ++ ++ abortTuneCmd.demodId = state->demod; ++ BUILD_HYDRA_CMD(MXL_HYDRA_ABORT_TUNE_CMD, MXL_CMD_WRITE, cmdSize, &abortTuneCmd, cmdBuff); ++ return send_command(state, cmdSize + MXL_HYDRA_CMD_HEADER_SIZE, &cmdBuff[0]); ++} ++ ++static int send_master_cmd(struct dvb_frontend *fe, ++ struct dvb_diseqc_master_cmd *cmd) ++{ ++ /*struct mxl *state = fe->demodulator_priv;*/ ++ ++ return 0; /*CfgDemodAbortTune(state);*/ ++} ++ ++static int set_parameters(struct dvb_frontend *fe) ++{ ++ struct mxl *state = fe->demodulator_priv; ++ struct dtv_frontend_properties *p = &fe->dtv_property_cache; ++ MXL_HYDRA_DEMOD_PARAM_T demodChanCfg; ++ u8 cmdSize = sizeof(demodChanCfg); ++ u8 cmdBuff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN]; ++ u32 srange = 10; ++ int stat; ++ ++ if (p->frequency < 950000 || p->frequency > 2150000) ++ return -EINVAL; ++ if (p->symbol_rate < 1000000 || p->symbol_rate > 45000000) ++ return -EINVAL; ++ ++ /* CfgDemodAbortTune(state); */ ++ ++ switch (p->delivery_system) { ++ case SYS_DSS: ++ demodChanCfg.standard = MXL_HYDRA_DSS; ++ demodChanCfg.rollOff = MXL_HYDRA_ROLLOFF_AUTO; ++ break; ++ case SYS_DVBS: ++ srange = p->symbol_rate / 1000000; ++ if (srange > 10) ++ srange = 10; ++ demodChanCfg.standard = MXL_HYDRA_DVBS; ++ demodChanCfg.rollOff = MXL_HYDRA_ROLLOFF_0_35; ++ demodChanCfg.modulationScheme = MXL_HYDRA_MOD_QPSK; ++ demodChanCfg.pilots = MXL_HYDRA_PILOTS_OFF; ++ break; ++ case SYS_DVBS2: ++ demodChanCfg.standard = MXL_HYDRA_DVBS2; ++ demodChanCfg.rollOff = MXL_HYDRA_ROLLOFF_AUTO; ++ demodChanCfg.modulationScheme = MXL_HYDRA_MOD_AUTO; ++ demodChanCfg.pilots = MXL_HYDRA_PILOTS_AUTO; ++ /* cfg_scrambler(state); */ ++ break; ++ default: ++ return -EINVAL; ++ } ++ demodChanCfg.tunerIndex = state->tuner; ++ demodChanCfg.demodIndex = state->demod; ++ demodChanCfg.frequencyInHz = p->frequency * 1000; ++ demodChanCfg.symbolRateInHz = p->symbol_rate; ++ demodChanCfg.maxCarrierOffsetInMHz = srange; ++ demodChanCfg.spectrumInversion = MXL_HYDRA_SPECTRUM_AUTO; ++ demodChanCfg.fecCodeRate = MXL_HYDRA_FEC_AUTO; ++ ++ mutex_lock(&state->base->tune_lock); ++ if (time_after(jiffies + msecs_to_jiffies(200), state->base->next_tune)) ++ while (time_before(jiffies, state->base->next_tune)) ++ usleep_range(10000, 11000); ++ state->base->next_tune = jiffies + msecs_to_jiffies(100); ++ state->tuner_in_use = state->tuner; ++ BUILD_HYDRA_CMD(MXL_HYDRA_DEMOD_SET_PARAM_CMD, MXL_CMD_WRITE, ++ cmdSize, &demodChanCfg, cmdBuff); ++ stat = send_command(state, cmdSize + MXL_HYDRA_CMD_HEADER_SIZE, &cmdBuff[0]); ++ mutex_unlock(&state->base->tune_lock); ++ return stat; ++} ++ ++static int get_stats(struct dvb_frontend *fe); ++ ++static int read_status(struct dvb_frontend *fe, enum fe_status *status) ++{ ++ struct mxl *state = fe->demodulator_priv; ++ ++ int stat; ++ u32 regData = 0; ++ ++ mutex_lock(&state->base->status_lock); ++ HYDRA_DEMOD_STATUS_LOCK(state, state->demod); ++ stat = read_register(state, (HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET + ++ HYDRA_DMD_STATUS_OFFSET(state->demod)), ++ ®Data); ++ HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); ++ mutex_unlock(&state->base->status_lock); ++ ++ *status = (regData == 1) ? 0x1f : 0; ++ get_stats(fe); ++ return stat; ++} ++ ++static int tune(struct dvb_frontend *fe, bool re_tune, ++ unsigned int mode_flags, ++ unsigned int *delay, enum fe_status *status) ++{ ++ struct mxl *state = fe->demodulator_priv; ++ int r = 0; ++ ++ *delay = HZ / 2; ++ if (re_tune) { ++ r = set_parameters(fe); ++ if (r) ++ return r; ++ state->tune_time = jiffies; ++ return 0; ++ } ++ if (*status & FE_HAS_LOCK) ++ return 0; ++ ++ r = read_status(fe, status); ++ if (r) ++ return r; ++ ++ return 0; ++} ++ ++static int enable_tuner(struct mxl *state, u32 tuner, u32 enable); ++ ++static int sleep(struct dvb_frontend *fe) ++{ ++ struct mxl *state = fe->demodulator_priv; ++ struct mxl *p; ++ ++ CfgDemodAbortTune(state); ++ if (state->tuner_in_use != 0xffffffff) { ++ mutex_lock(&state->base->tune_lock); ++ state->tuner_in_use = 0xffffffff; ++ list_for_each_entry(p, &state->base->mxls, mxl) { ++ if (p->tuner_in_use == state->tuner) ++ break; ++ } ++ if (&p->mxl == &state->base->mxls) ++ enable_tuner(state, state->tuner, 0); ++ mutex_unlock(&state->base->tune_lock); ++ } ++ return 0; ++} ++ ++static int read_snr(struct dvb_frontend *fe, u16 *snr) ++{ ++ struct mxl *state = fe->demodulator_priv; ++ int stat; ++ u32 regData = 0; ++ struct dtv_frontend_properties *p = &fe->dtv_property_cache; ++ ++ mutex_lock(&state->base->status_lock); ++ HYDRA_DEMOD_STATUS_LOCK(state, state->demod); ++ stat = read_register(state, (HYDRA_DMD_SNR_ADDR_OFFSET + ++ HYDRA_DMD_STATUS_OFFSET(state->demod)), ++ ®Data); ++ HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); ++ mutex_unlock(&state->base->status_lock); ++ *snr = (s16) (regData & 0xFFFF); /* 100x dB */ ++ p->cnr.len = 1; ++ p->cnr.stat[0].scale = FE_SCALE_DECIBEL; ++ p->cnr.stat[0].uvalue = 10 * (s64) *snr; ++ return stat; ++} ++ ++static int read_ber(struct dvb_frontend *fe, u32 *ber) ++{ ++ struct mxl *state = fe->demodulator_priv; ++ struct dtv_frontend_properties *p = &fe->dtv_property_cache; ++ u32 reg[8], reg2[4]; ++ int stat; ++ ++ *ber = 0; ++ mutex_lock(&state->base->status_lock); ++ HYDRA_DEMOD_STATUS_LOCK(state, state->demod); ++ stat = read_register_block(state, ++ (HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET + ++ HYDRA_DMD_STATUS_OFFSET(state->demod)), ++ (7 * sizeof(u32)), ++ (u8 *) ®[0]); ++ stat = read_register_block(state, ++ (HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET + ++ HYDRA_DMD_STATUS_OFFSET(state->demod)), ++ (4 * sizeof(u32)), ++ (u8 *) ®2[0]); ++ HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); ++ mutex_unlock(&state->base->status_lock); ++ ++ ++ switch (p->delivery_system) { ++ case SYS_DSS: ++ break; ++ case SYS_DVBS: ++ p->pre_bit_error.len = 1; ++ p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; ++ p->pre_bit_error.stat[0].uvalue = reg[5]; ++ p->pre_bit_count.len = 1; ++ p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; ++ p->pre_bit_count.stat[0].uvalue = reg[6] * 188 * 8; ++ break; ++ case SYS_DVBS2: ++ break; ++ default: ++ break; ++ } ++ pr_debug("ber %08x %08x %08x %08x %08x %08x %08x\n", ++ reg[0], reg[1], reg[2], reg[3], reg[4], reg[5], reg[6]); ++ pr_debug("ber2 %08x %08x %08x %08x\n", ++ reg[0], reg[1], reg[2], reg[3]); ++ /* ++ * pre_bit_error, pre_bit_count ++ * post_bit_error, post_bit_count; ++ * block_error block_count; ++ * reset_fec_counter(state); ++ */ ++ return 0; ++} ++ ++static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) ++{ ++ struct mxl *state = fe->demodulator_priv; ++ struct dtv_frontend_properties *p = &fe->dtv_property_cache; ++ int stat; ++ u32 regData = 0; ++ ++ mutex_lock(&state->base->status_lock); ++ HYDRA_DEMOD_STATUS_LOCK(state, state->demod); ++ stat = read_register(state, (HYDRA_DMD_STATUS_INPUT_POWER_ADDR + ++ HYDRA_DMD_STATUS_OFFSET(state->demod)), ++ ®Data); ++ HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); ++ mutex_unlock(&state->base->status_lock); ++ *strength = (u16) (regData & 0xFFFF); /* 10x dBm */ ++ p->strength.len = 1; ++ p->strength.stat[0].scale = FE_SCALE_DECIBEL; ++ p->strength.stat[0].uvalue = 10 * (s64) (s16) (regData & 0xFFFF); ++ return stat; ++} ++ ++static int read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) ++{ ++ return 0; ++} ++ ++static int get_stats(struct dvb_frontend *fe) ++{ ++ u16 val; ++ u32 val32; ++ ++ read_signal_strength(fe, &val); ++ read_snr(fe, &val); ++ read_ber(fe, &val32); ++ return 0; ++} ++ ++static enum fe_code_rate conv_fec(MXL_HYDRA_FEC_E fec) ++{ ++ enum fe_code_rate fec2fec[11] = { ++ FEC_NONE, FEC_1_2, FEC_3_5, FEC_2_3, ++ FEC_3_4, FEC_4_5, FEC_5_6, FEC_6_7, ++ FEC_7_8, FEC_8_9, FEC_9_10 ++ }; ++ ++ if (fec > MXL_HYDRA_FEC_9_10) ++ return FEC_NONE; ++ return fec2fec[fec]; ++} ++ ++static int get_frontend(struct dvb_frontend *fe, ++ struct dtv_frontend_properties *p) ++{ ++ struct mxl *state = fe->demodulator_priv; ++ u32 regData[MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE]; ++ u32 freq; ++ int stat; ++ ++ mutex_lock(&state->base->status_lock); ++ HYDRA_DEMOD_STATUS_LOCK(state, state->demod); ++ stat = read_register_block(state, ++ (HYDRA_DMD_STANDARD_ADDR_OFFSET + ++ HYDRA_DMD_STATUS_OFFSET(state->demod)), ++ (MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE * 4), /* 25 * 4 bytes */ ++ (u8 *) ®Data[0]); ++ /* read demod channel parameters */ ++ stat = read_register_block(state, ++ (HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR + ++ HYDRA_DMD_STATUS_OFFSET(state->demod)), ++ (4), /* 4 bytes */ ++ (u8 *) &freq); ++ HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod); ++ mutex_unlock(&state->base->status_lock); ++ ++ pr_debug("freq=%u delsys=%u srate=%u\n", ++ freq * 1000, regData[DMD_STANDARD_ADDR], ++ regData[DMD_SYMBOL_RATE_ADDR]); ++ p->symbol_rate = regData[DMD_SYMBOL_RATE_ADDR]; ++ p->frequency = freq; ++ /* ++ * p->delivery_system = (MXL_HYDRA_BCAST_STD_E )regData[DMD_STANDARD_ADDR]; ++ * p->inversion = (MXL_HYDRA_SPECTRUM_E )regData[DMD_SPECTRUM_INVERSION_ADDR]; ++ * freqSearchRangeKHz = (regData[DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR]); ++ */ ++ ++ p->fec_inner = conv_fec(regData[DMD_FEC_CODE_RATE_ADDR]); ++ switch (p->delivery_system) { ++ case SYS_DSS: ++ break; ++ case SYS_DVBS2: ++ switch ((MXL_HYDRA_PILOTS_E) regData[DMD_DVBS2_PILOT_ON_OFF_ADDR]) { ++ case MXL_HYDRA_PILOTS_OFF: ++ p->pilot = PILOT_OFF; ++ break; ++ case MXL_HYDRA_PILOTS_ON: ++ p->pilot = PILOT_ON; ++ break; ++ default: ++ break; ++ } ++ case SYS_DVBS: ++ switch ((MXL_HYDRA_MODULATION_E) regData[DMD_MODULATION_SCHEME_ADDR]) { ++ case MXL_HYDRA_MOD_QPSK: ++ p->modulation = QPSK; ++ break; ++ case MXL_HYDRA_MOD_8PSK: ++ p->modulation = PSK_8; ++ break; ++ default: ++ break; ++ } ++ switch ((MXL_HYDRA_ROLLOFF_E) regData[DMD_SPECTRUM_ROLL_OFF_ADDR]) { ++ case MXL_HYDRA_ROLLOFF_0_20: ++ p->rolloff = ROLLOFF_20; ++ break; ++ case MXL_HYDRA_ROLLOFF_0_35: ++ p->rolloff = ROLLOFF_35; ++ break; ++ case MXL_HYDRA_ROLLOFF_0_25: ++ p->rolloff = ROLLOFF_25; ++ break; ++ default: ++ break; ++ } ++ break; ++ default: ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++static int set_input(struct dvb_frontend *fe, int input) ++{ ++ struct mxl *state = fe->demodulator_priv; ++ struct dtv_frontend_properties *p = &fe->dtv_property_cache; ++ ++ state->tuner = p->input = input; ++ return 0; ++} ++ ++static struct dvb_frontend_ops mxl_ops = { ++ .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS }, ++ .xbar = { 4, 0, 8 }, /* tuner_max, demod id, demod_max */ ++ .info = { ++ .name = "MXL5XX", ++ .frequency_min = 950000, ++ .frequency_max = 2150000, ++ .frequency_stepsize = 0, ++ .frequency_tolerance = 0, ++ .symbol_rate_min = 1000000, ++ .symbol_rate_max = 45000000, ++ .caps = FE_CAN_INVERSION_AUTO | ++ FE_CAN_FEC_AUTO | ++ FE_CAN_QPSK | ++ FE_CAN_2G_MODULATION ++ }, ++ .init = init, ++ .release = release, ++ .get_frontend_algo = get_algo, ++ .tune = tune, ++ .read_status = read_status, ++ .sleep = sleep, ++ .read_snr = read_snr, ++ .read_ber = read_ber, ++ .read_signal_strength = read_signal_strength, ++ .read_ucblocks = read_ucblocks, ++ .get_frontend = get_frontend, ++ .set_input = set_input, ++ .diseqc_send_master_cmd = send_master_cmd, ++}; ++ ++static struct mxl_base *match_base(struct i2c_adapter *i2c, u8 adr) ++{ ++ struct mxl_base *p; ++ ++ list_for_each_entry(p, &mxllist, mxllist) ++ if (p->i2c == i2c && p->adr == adr) ++ return p; ++ return NULL; ++} ++ ++static void cfg_dev_xtal(struct mxl *state, u32 freq, u32 cap, u32 enable) ++{ ++ if (state->base->can_clkout || !enable) ++ SET_REG_FIELD_DATA(AFE_REG_D2A_XTAL_EN_CLKOUT_1P8, enable); ++ ++ if (freq == 24000000) ++ write_register(state, HYDRA_CRYSTAL_SETTING, 0); ++ else ++ write_register(state, HYDRA_CRYSTAL_SETTING, 1); ++ ++ write_register(state, HYDRA_CRYSTAL_CAP, cap); ++} ++ ++static u32 get_big_endian(u8 numOfBits, const u8 buf[]) ++{ ++ u32 retValue = 0; ++ ++ switch (numOfBits) { ++ case 24: ++ retValue = (((u32) buf[0]) << 16) | ++ (((u32) buf[1]) << 8) | buf[2]; ++ break; ++ case 32: ++ retValue = (((u32) buf[0]) << 24) | ++ (((u32) buf[1]) << 16) | ++ (((u32) buf[2]) << 8) | buf[3]; ++ break; ++ default: ++ break; ++ } ++ ++ return retValue; ++} ++ ++static int write_fw_segment(struct mxl *state, ++ u32 MemAddr, u32 totalSize, u8 *dataPtr) ++{ ++ int status; ++ u32 dataCount = 0; ++ u32 size = 0; ++ u32 origSize = 0; ++ u8 *wBufPtr = NULL; ++ u32 blockSize = ((MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH - ++ (MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES)) / 4) * 4; ++ u8 wMsgBuffer[MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH - ++ (MXL_HYDRA_I2C_HDR_SIZE + MXL_HYDRA_REG_SIZE_IN_BYTES)]; ++ ++ do { ++ size = origSize = (((u32)(dataCount + blockSize)) > totalSize) ? ++ (totalSize - dataCount) : blockSize; ++ ++ if (origSize & 3) ++ size = (origSize + 4) & ~3; ++ wBufPtr = &wMsgBuffer[0]; ++ memset((void *) wBufPtr, 0, size); ++ memcpy((void *) wBufPtr, (void *) dataPtr, origSize); ++ convert_endian(1, size, wBufPtr); ++ status = write_firmware_block(state, MemAddr, size, wBufPtr); ++ if (status) ++ return status; ++ dataCount += size; ++ MemAddr += size; ++ dataPtr += size; ++ } while (dataCount < totalSize); ++ ++ return status; ++} ++ ++static int do_firmware_download(struct mxl *state, u8 *mbinBufferPtr, u32 mbinBufferSize) ++ ++{ ++ int status; ++ u32 index = 0; ++ u32 segLength = 0; ++ u32 segAddress = 0; ++ MBIN_FILE_T *mbinPtr = (MBIN_FILE_T *)mbinBufferPtr; ++ MBIN_SEGMENT_T *segmentPtr; ++ MXL_BOOL_E xcpuFwFlag = MXL_FALSE; ++ ++ if (mbinPtr->header.id != MBIN_FILE_HEADER_ID) { ++ pr_err("%s: Invalid file header ID (%c)\n", ++ __func__, mbinPtr->header.id); ++ return -EINVAL; ++ } ++ status = write_register(state, FW_DL_SIGN_ADDR, 0); ++ if (status) ++ return status; ++ segmentPtr = (MBIN_SEGMENT_T *) (&mbinPtr->data[0]); ++ for (index = 0; index < mbinPtr->header.numSegments; index++) { ++ if (segmentPtr->header.id != MBIN_SEGMENT_HEADER_ID) { ++ pr_err("%s: Invalid segment header ID (%c)\n", ++ __func__, segmentPtr->header.id); ++ return -EINVAL; ++ } ++ segLength = get_big_endian(24, &(segmentPtr->header.len24[0])); ++ segAddress = get_big_endian(32, &(segmentPtr->header.address[0])); ++ ++ if (state->base->type == MXL_HYDRA_DEVICE_568) { ++ if ((((segAddress & 0x90760000) == 0x90760000) || ++ ((segAddress & 0x90740000) == 0x90740000)) && ++ (xcpuFwFlag == MXL_FALSE)) { ++ SET_REG_FIELD_DATA(PRCM_PRCM_CPU_SOFT_RST_N, 1); ++ msleep(200); ++ write_register(state, 0x90720000, 0); ++ usleep_range(10000, 11000); ++ xcpuFwFlag = MXL_TRUE; ++ } ++ status = write_fw_segment(state, segAddress, ++ segLength, (u8 *) segmentPtr->data); ++ } else { ++ if (((segAddress & 0x90760000) != 0x90760000) && ++ ((segAddress & 0x90740000) != 0x90740000)) ++ status = write_fw_segment(state, segAddress, ++ segLength, (u8 *) segmentPtr->data); ++ } ++ if (status) ++ return status; ++ segmentPtr = (MBIN_SEGMENT_T *) ++ &(segmentPtr->data[((segLength + 3) / 4) * 4]); ++ } ++ return status; ++} ++ ++static int check_fw(u8 *mbin, u32 mbin_len) ++{ ++ MBIN_FILE_HEADER_T *fh = (MBIN_FILE_HEADER_T *) mbin; ++ u32 flen = (fh->imageSize24[0] << 16) | ++ (fh->imageSize24[1] << 8) | fh->imageSize24[2]; ++ u8 *fw, cs = 0; ++ u32 i; ++ ++ if (fh->id != 'M' || fh->fmtVersion != '1' || flen > 0x3FFF0) { ++ pr_info("Invalid FW Header\n"); ++ return -1; ++ } ++ fw = mbin + sizeof(MBIN_FILE_HEADER_T); ++ for (i = 0; i < flen; i += 1) ++ cs += fw[i]; ++ if (cs != fh->imageChecksum) { ++ pr_info("Invalid FW Checksum\n"); + return -1; + } + return 0; +} + -+static int lnbh25_write_regs(struct lnbh25 *lnbh, int reg, int len) ++static int firmware_download(struct mxl *state, u8 *mbin, u32 mbin_len) +{ -+ u8 d[5]; ++ int status; ++ u32 regData = 0; ++ MXL_HYDRA_SKU_COMMAND_T devSkuCfg; ++ u8 cmdSize = sizeof(MXL_HYDRA_SKU_COMMAND_T); ++ u8 cmdBuff[sizeof(MXL_HYDRA_SKU_COMMAND_T) + 6]; + -+ memcpy(&d[1], &lnbh->reg[reg], len); -+ d[0] = reg + 2; -+ return i2c_write(lnbh->i2c, lnbh->adr, d, len + 1); ++ if (check_fw(mbin, mbin_len)) ++ return -1; ++ ++ /* put CPU into reset */ ++ status = SET_REG_FIELD_DATA(PRCM_PRCM_CPU_SOFT_RST_N, 0); ++ if (status) ++ return status; ++ usleep_range(1000, 2000); ++ ++ /* Reset TX FIFO's, BBAND, XBAR */ ++ status = write_register(state, HYDRA_RESET_TRANSPORT_FIFO_REG, ++ HYDRA_RESET_TRANSPORT_FIFO_DATA); ++ if (status) ++ return status; ++ status = write_register(state, HYDRA_RESET_BBAND_REG, ++ HYDRA_RESET_BBAND_DATA); ++ if (status) ++ return status; ++ status = write_register(state, HYDRA_RESET_XBAR_REG, ++ HYDRA_RESET_XBAR_DATA); ++ if (status) ++ return status; ++ ++ /* Disable clock to Baseband, Wideband, SerDes, Alias ext & Transport modules */ ++ status = write_register(state, HYDRA_MODULES_CLK_2_REG, HYDRA_DISABLE_CLK_2); ++ if (status) ++ return status; ++ /* Clear Software & Host interrupt status - (Clear on read) */ ++ status = read_register(state, HYDRA_PRCM_ROOT_CLK_REG, ®Data); ++ if (status) ++ return status; ++ status = do_firmware_download(state, mbin, mbin_len); ++ if (status) ++ return status; ++ ++ if (state->base->type == MXL_HYDRA_DEVICE_568) { ++ usleep_range(10000, 11000); ++ ++ /* bring XCPU out of reset */ ++ status = write_register(state, 0x90720000, 1); ++ if (status) ++ return status; ++ msleep(500); ++ ++ /* Enable XCPU UART message processing in MCPU */ ++ status = write_register(state, 0x9076B510, 1); ++ if (status) ++ return status; ++ } else { ++ /* Bring CPU out of reset */ ++ status = SET_REG_FIELD_DATA(PRCM_PRCM_CPU_SOFT_RST_N, 1); ++ if (status) ++ return status; ++ /* Wait until FW boots */ ++ msleep(150); ++ } ++ ++ /* Initilize XPT XBAR */ ++ status = write_register(state, XPT_DMD0_BASEADDR, 0x76543210); ++ if (status) ++ return status; ++ ++ if (!firmware_is_alive(state)) ++ return -1; ++ ++ pr_info("Hydra FW alive. Hail!\n"); ++ ++ /* sometimes register values are wrong shortly after first heart beats */ ++ msleep(50); ++ ++ devSkuCfg.skuType = state->base->sku_type; ++ BUILD_HYDRA_CMD(MXL_HYDRA_DEV_CFG_SKU_CMD, MXL_CMD_WRITE, ++ cmdSize, &devSkuCfg, cmdBuff); ++ status = send_command(state, cmdSize + MXL_HYDRA_CMD_HEADER_SIZE, &cmdBuff[0]); ++ ++ return status; +} + -+static int lnbh25_set_voltage(struct dvb_frontend *fe, -+ fe_sec_voltage_t voltage) ++static int cfg_ts_pad_mux(struct mxl *state, MXL_BOOL_E enableSerialTS) +{ -+ struct lnbh25 *lnbh = (struct lnbh25 *) fe->sec_priv; ++ int status = 0; ++ u32 padMuxValue = 0; + -+ switch (voltage) { -+ case SEC_VOLTAGE_OFF: -+ lnbh->reg[0] = 0x00; -+ lnbh->reg[1] &= ~0x01; /* Disable Tone */ -+ lnbh->reg[2] = 0x00; -+ return lnbh25_write_regs(lnbh, 0, 3); -+ case SEC_VOLTAGE_13: -+ lnbh->reg[0] = lnbh->boost + 1; ++ if (enableSerialTS == MXL_TRUE) { ++ padMuxValue = 0; ++ if ((state->base->type == MXL_HYDRA_DEVICE_541) || ++ (state->base->type == MXL_HYDRA_DEVICE_541S)) ++ padMuxValue = 2; ++ } else { ++ if ((state->base->type == MXL_HYDRA_DEVICE_581) || ++ (state->base->type == MXL_HYDRA_DEVICE_581S)) ++ padMuxValue = 2; ++ else ++ padMuxValue = 3; ++ } ++ ++ switch (state->base->type) { ++ case MXL_HYDRA_DEVICE_561: ++ case MXL_HYDRA_DEVICE_581: ++ case MXL_HYDRA_DEVICE_541: ++ case MXL_HYDRA_DEVICE_541S: ++ case MXL_HYDRA_DEVICE_561S: ++ case MXL_HYDRA_DEVICE_581S: ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_14_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_15_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_16_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_17_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_18_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_19_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_20_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_21_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_22_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_23_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_24_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_25_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_26_PINMUX_SEL, padMuxValue); + break; -+ case SEC_VOLTAGE_18: -+ lnbh->reg[0] = lnbh->boost + 8; ++ ++ case MXL_HYDRA_DEVICE_544: ++ case MXL_HYDRA_DEVICE_542: ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_01_PINMUX_SEL, 1); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_02_PINMUX_SEL, 0); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_03_PINMUX_SEL, 0); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_04_PINMUX_SEL, 0); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_08_PINMUX_SEL, 0); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_27_PINMUX_SEL, 1); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_28_PINMUX_SEL, 1); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_29_PINMUX_SEL, 1); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_30_PINMUX_SEL, 1); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_32_PINMUX_SEL, 1); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_33_PINMUX_SEL, 1); ++ if (enableSerialTS == MXL_ENABLE) { ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_09_PINMUX_SEL, 0); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_10_PINMUX_SEL, 0); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_11_PINMUX_SEL, 0); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_12_PINMUX_SEL, 0); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_13_PINMUX_SEL, 1); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_14_PINMUX_SEL, 1); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_15_PINMUX_SEL, 2); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_16_PINMUX_SEL, 2); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_17_PINMUX_SEL, 2); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_18_PINMUX_SEL, 2); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_19_PINMUX_SEL, 2); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_20_PINMUX_SEL, 2); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_21_PINMUX_SEL, 2); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_22_PINMUX_SEL, 2); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_23_PINMUX_SEL, 2); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_24_PINMUX_SEL, 2); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_25_PINMUX_SEL, 2); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_26_PINMUX_SEL, 2); ++ } else { ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_09_PINMUX_SEL, 3); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_10_PINMUX_SEL, 3); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_11_PINMUX_SEL, 3); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_12_PINMUX_SEL, 3); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_13_PINMUX_SEL, 3); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_14_PINMUX_SEL, 3); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_15_PINMUX_SEL, 3); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_16_PINMUX_SEL, 3); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_17_PINMUX_SEL, 3); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_18_PINMUX_SEL, 3); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_19_PINMUX_SEL, 3); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_20_PINMUX_SEL, 3); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_21_PINMUX_SEL, 1); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_22_PINMUX_SEL, 1); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_23_PINMUX_SEL, 1); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_24_PINMUX_SEL, 1); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_25_PINMUX_SEL, 1); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_26_PINMUX_SEL, 1); ++ } + break; ++ ++ case MXL_HYDRA_DEVICE_568: ++ if (enableSerialTS == MXL_FALSE) { ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_02_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_03_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_04_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_05_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_06_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_07_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_08_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_09_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_10_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_11_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_12_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_13_PINMUX_SEL, 5); ++ ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_14_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_16_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_17_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_18_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_19_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_20_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_21_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_22_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_23_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_24_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_25_PINMUX_SEL, padMuxValue); ++ ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_26_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_27_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_28_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_29_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_30_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_31_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_32_PINMUX_SEL, 5); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_33_PINMUX_SEL, 5); ++ } else { ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_09_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_10_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_11_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_12_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_13_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_14_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_15_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_16_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_17_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_18_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_19_PINMUX_SEL, padMuxValue); ++ } ++ break; ++ ++ ++ case MXL_HYDRA_DEVICE_584: + default: -+ return -EINVAL; -+ }; -+ -+ if (lnbh->reg[0] == 0x00) { -+ lnbh->reg[2] = 4; -+ lnbh25_write_regs(lnbh, 2, 2); -+ } else if (lnbh->reg[2] != 0x00) { -+ lnbh->reg[2] = 0; -+ lnbh25_write_regs(lnbh, 2, 2); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_09_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_10_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_11_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_12_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_13_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_14_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_15_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_16_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_17_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_18_PINMUX_SEL, padMuxValue); ++ status |= SET_REG_FIELD_DATA(PAD_MUX_DIGIO_19_PINMUX_SEL, padMuxValue); ++ break; + } -+ lnbh->reg[1] |= 0x01; -+ return lnbh25_write_regs(lnbh, 0, 3); ++ return status; +} + -+static int lnbh25_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg) -+{ -+ struct lnbh25 *lnbh = (struct lnbh25 *) fe->sec_priv; + -+ lnbh->boost = arg ? 3 : 0; ++static int set_drive_strength(struct mxl *state, ++ MXL_HYDRA_TS_DRIVE_STRENGTH_E tsDriveStrength) ++{ ++ int stat = 0; ++ u32 val; ++ ++ read_register(state, 0x90000194, &val); ++ pr_info("DIGIO = %08x\n", val); ++ pr_info("set drive_strength = %u\n", tsDriveStrength); ++ ++ ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_00, tsDriveStrength); ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_05, tsDriveStrength); ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_06, tsDriveStrength); ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_11, tsDriveStrength); ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_12, tsDriveStrength); ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_13, tsDriveStrength); ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_14, tsDriveStrength); ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_16, tsDriveStrength); ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_17, tsDriveStrength); ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_18, tsDriveStrength); ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_22, tsDriveStrength); ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_23, tsDriveStrength); ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_24, tsDriveStrength); ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_25, tsDriveStrength); ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_29, tsDriveStrength); ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_30, tsDriveStrength); ++ stat |= SET_REG_FIELD_DATA(PAD_MUX_PAD_DRV_DIGIO_31, tsDriveStrength); ++ ++ return stat; ++} ++ ++ ++static int enable_tuner(struct mxl *state, u32 tuner, u32 enable) ++{ ++ int stat = 0; ++ MxL_HYDRA_TUNER_CMD ctrlTunerCmd; ++ u8 cmdSize = sizeof(ctrlTunerCmd); ++ u8 cmdBuff[MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN]; ++ u32 val, count = 10; ++ ++ ctrlTunerCmd.tunerId = tuner; ++ ctrlTunerCmd.enable = enable; ++ BUILD_HYDRA_CMD(MXL_HYDRA_TUNER_ACTIVATE_CMD, MXL_CMD_WRITE, ++ cmdSize, &ctrlTunerCmd, cmdBuff); ++ stat = send_command(state, cmdSize + MXL_HYDRA_CMD_HEADER_SIZE, &cmdBuff[0]); ++ if (stat) ++ return stat; ++ read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); ++ while (--count && ((val >> tuner) & 1) != enable) { ++ msleep(20); ++ read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); ++ } ++ if (!count) ++ return -1; ++ read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val); ++ pr_info("tuner %u ready = %u\n", tuner, (val >> tuner) & 1); + + return 0; +} + -+static int lnbh25_set_tone(struct dvb_frontend *fe, -+ fe_sec_tone_mode_t tone) -+{ -+ /* struct lnbh25 *lnbh = (struct lnbh25 *) fe->sec_priv; */ + ++static int config_ts(struct mxl *state, MXL_HYDRA_DEMOD_ID_E demodId, ++ MXL_HYDRA_MPEGOUT_PARAM_T *mpegOutParamPtr) ++{ ++ int status = 0; ++ u32 ncoCountMin = 0; ++ u32 clkType = 0; ++ ++ MXL_REG_FIELD_T xpt_sync_polarity[MXL_HYDRA_DEMOD_MAX] = { ++ {XPT_SYNC_POLARITY0}, {XPT_SYNC_POLARITY1}, ++ {XPT_SYNC_POLARITY2}, {XPT_SYNC_POLARITY3}, ++ {XPT_SYNC_POLARITY4}, {XPT_SYNC_POLARITY5}, ++ {XPT_SYNC_POLARITY6}, {XPT_SYNC_POLARITY7} }; ++ MXL_REG_FIELD_T xpt_clock_polarity[MXL_HYDRA_DEMOD_MAX] = { ++ {XPT_CLOCK_POLARITY0}, {XPT_CLOCK_POLARITY1}, ++ {XPT_CLOCK_POLARITY2}, {XPT_CLOCK_POLARITY3}, ++ {XPT_CLOCK_POLARITY4}, {XPT_CLOCK_POLARITY5}, ++ {XPT_CLOCK_POLARITY6}, {XPT_CLOCK_POLARITY7} }; ++ MXL_REG_FIELD_T xpt_valid_polarity[MXL_HYDRA_DEMOD_MAX] = { ++ {XPT_VALID_POLARITY0}, {XPT_VALID_POLARITY1}, ++ {XPT_VALID_POLARITY2}, {XPT_VALID_POLARITY3}, ++ {XPT_VALID_POLARITY4}, {XPT_VALID_POLARITY5}, ++ {XPT_VALID_POLARITY6}, {XPT_VALID_POLARITY7} }; ++ MXL_REG_FIELD_T xpt_ts_clock_phase[MXL_HYDRA_DEMOD_MAX] = { ++ {XPT_TS_CLK_PHASE0}, {XPT_TS_CLK_PHASE1}, ++ {XPT_TS_CLK_PHASE2}, {XPT_TS_CLK_PHASE3}, ++ {XPT_TS_CLK_PHASE4}, {XPT_TS_CLK_PHASE5}, ++ {XPT_TS_CLK_PHASE6}, {XPT_TS_CLK_PHASE7} }; ++ MXL_REG_FIELD_T xpt_lsb_first[MXL_HYDRA_DEMOD_MAX] = { ++ {XPT_LSB_FIRST0}, {XPT_LSB_FIRST1}, {XPT_LSB_FIRST2}, {XPT_LSB_FIRST3}, ++ {XPT_LSB_FIRST4}, {XPT_LSB_FIRST5}, {XPT_LSB_FIRST6}, {XPT_LSB_FIRST7} }; ++ MXL_REG_FIELD_T xpt_sync_byte[MXL_HYDRA_DEMOD_MAX] = { ++ {XPT_SYNC_FULL_BYTE0}, {XPT_SYNC_FULL_BYTE1}, ++ {XPT_SYNC_FULL_BYTE2}, {XPT_SYNC_FULL_BYTE3}, ++ {XPT_SYNC_FULL_BYTE4}, {XPT_SYNC_FULL_BYTE5}, ++ {XPT_SYNC_FULL_BYTE6}, {XPT_SYNC_FULL_BYTE7} }; ++ MXL_REG_FIELD_T xpt_enable_output[MXL_HYDRA_DEMOD_MAX] = { ++ {XPT_ENABLE_OUTPUT0}, {XPT_ENABLE_OUTPUT1}, ++ {XPT_ENABLE_OUTPUT2}, {XPT_ENABLE_OUTPUT3}, ++ {XPT_ENABLE_OUTPUT4}, {XPT_ENABLE_OUTPUT5}, ++ {XPT_ENABLE_OUTPUT6}, {XPT_ENABLE_OUTPUT7} }; ++ MXL_REG_FIELD_T xpt_err_replace_sync[MXL_HYDRA_DEMOD_MAX] = { ++ {XPT_ERROR_REPLACE_SYNC0}, {XPT_ERROR_REPLACE_SYNC1}, ++ {XPT_ERROR_REPLACE_SYNC2}, {XPT_ERROR_REPLACE_SYNC3}, ++ {XPT_ERROR_REPLACE_SYNC4}, {XPT_ERROR_REPLACE_SYNC5}, ++ {XPT_ERROR_REPLACE_SYNC6}, {XPT_ERROR_REPLACE_SYNC7} }; ++ MXL_REG_FIELD_T xpt_err_replace_valid[MXL_HYDRA_DEMOD_MAX] = { ++ {XPT_ERROR_REPLACE_VALID0}, {XPT_ERROR_REPLACE_VALID1}, ++ {XPT_ERROR_REPLACE_VALID2}, {XPT_ERROR_REPLACE_VALID3}, ++ {XPT_ERROR_REPLACE_VALID4}, {XPT_ERROR_REPLACE_VALID5}, ++ {XPT_ERROR_REPLACE_VALID6}, {XPT_ERROR_REPLACE_VALID7} }; ++ MXL_REG_FIELD_T xpt_continuous_clock[MXL_HYDRA_DEMOD_MAX] = { ++ {XPT_TS_CLK_OUT_EN0}, {XPT_TS_CLK_OUT_EN1}, ++ {XPT_TS_CLK_OUT_EN2}, {XPT_TS_CLK_OUT_EN3}, ++ {XPT_TS_CLK_OUT_EN4}, {XPT_TS_CLK_OUT_EN5}, ++ {XPT_TS_CLK_OUT_EN6}, {XPT_TS_CLK_OUT_EN7} }; ++ MXL_REG_FIELD_T xpt_nco_clock_rate[MXL_HYDRA_DEMOD_MAX] = { ++ {XPT_NCO_COUNT_MIN0}, {XPT_NCO_COUNT_MIN1}, ++ {XPT_NCO_COUNT_MIN2}, {XPT_NCO_COUNT_MIN3}, ++ {XPT_NCO_COUNT_MIN4}, {XPT_NCO_COUNT_MIN5}, ++ {XPT_NCO_COUNT_MIN6}, {XPT_NCO_COUNT_MIN7} }; ++ ++ demodId = state->base->ts_map[demodId]; ++ ++ if (mpegOutParamPtr->enable == MXL_ENABLE) { ++ if (mpegOutParamPtr->mpegMode == MXL_HYDRA_MPEG_MODE_PARALLEL) { ++ } else { ++ cfg_ts_pad_mux(state, MXL_TRUE); ++ SET_REG_FIELD_DATA(XPT_ENABLE_PARALLEL_OUTPUT, MXL_FALSE); ++ } ++ } ++ ++ ncoCountMin = (u32)(MXL_HYDRA_NCO_CLK/mpegOutParamPtr->maxMpegClkRate); ++ ++ if (state->base->chipversion >= 2) { ++ status |= update_by_mnemonic(state, ++ xpt_nco_clock_rate[demodId].regAddr, /* Reg Addr */ ++ xpt_nco_clock_rate[demodId].lsbPos, /* LSB pos */ ++ xpt_nco_clock_rate[demodId].numOfBits, /* Num of bits */ ++ ncoCountMin); /* Data */ ++ } else ++ SET_REG_FIELD_DATA(XPT_NCO_COUNT_MIN, ncoCountMin); ++ ++ if (mpegOutParamPtr->mpegClkType == MXL_HYDRA_MPEG_CLK_CONTINUOUS) ++ clkType = 1; ++ ++ if (mpegOutParamPtr->mpegMode < MXL_HYDRA_MPEG_MODE_PARALLEL) { ++ status |= update_by_mnemonic(state, ++ xpt_continuous_clock[demodId].regAddr, ++ xpt_continuous_clock[demodId].lsbPos, ++ xpt_continuous_clock[demodId].numOfBits, ++ clkType); ++ } else ++ SET_REG_FIELD_DATA(XPT_TS_CLK_OUT_EN_PARALLEL, clkType); ++ ++ status |= update_by_mnemonic(state, ++ xpt_sync_polarity[demodId].regAddr, ++ xpt_sync_polarity[demodId].lsbPos, ++ xpt_sync_polarity[demodId].numOfBits, ++ mpegOutParamPtr->mpegSyncPol); ++ ++ status |= update_by_mnemonic(state, ++ xpt_valid_polarity[demodId].regAddr, ++ xpt_valid_polarity[demodId].lsbPos, ++ xpt_valid_polarity[demodId].numOfBits, ++ mpegOutParamPtr->mpegValidPol); ++ ++ status |= update_by_mnemonic(state, ++ xpt_clock_polarity[demodId].regAddr, ++ xpt_clock_polarity[demodId].lsbPos, ++ xpt_clock_polarity[demodId].numOfBits, ++ mpegOutParamPtr->mpegClkPol); ++ ++ status |= update_by_mnemonic(state, ++ xpt_sync_byte[demodId].regAddr, ++ xpt_sync_byte[demodId].lsbPos, ++ xpt_sync_byte[demodId].numOfBits, ++ mpegOutParamPtr->mpegSyncPulseWidth); ++ ++ status |= update_by_mnemonic(state, ++ xpt_ts_clock_phase[demodId].regAddr, ++ xpt_ts_clock_phase[demodId].lsbPos, ++ xpt_ts_clock_phase[demodId].numOfBits, ++ mpegOutParamPtr->mpegClkPhase); ++ ++ status |= update_by_mnemonic(state, ++ xpt_lsb_first[demodId].regAddr, ++ xpt_lsb_first[demodId].lsbPos, ++ xpt_lsb_first[demodId].numOfBits, ++ mpegOutParamPtr->lsbOrMsbFirst); ++ ++ switch (mpegOutParamPtr->mpegErrorIndication) { ++ case MXL_HYDRA_MPEG_ERR_REPLACE_SYNC: ++ status |= update_by_mnemonic(state, ++ xpt_err_replace_sync[demodId].regAddr, ++ xpt_err_replace_sync[demodId].lsbPos, ++ xpt_err_replace_sync[demodId].numOfBits, ++ MXL_TRUE); ++ status |= update_by_mnemonic(state, ++ xpt_err_replace_valid[demodId].regAddr, ++ xpt_err_replace_valid[demodId].lsbPos, ++ xpt_err_replace_valid[demodId].numOfBits, ++ MXL_FALSE); ++ break; ++ ++ case MXL_HYDRA_MPEG_ERR_REPLACE_VALID: ++ status |= update_by_mnemonic(state, ++ xpt_err_replace_sync[demodId].regAddr, ++ xpt_err_replace_sync[demodId].lsbPos, ++ xpt_err_replace_sync[demodId].numOfBits, ++ MXL_FALSE); ++ ++ status |= update_by_mnemonic(state, ++ xpt_err_replace_valid[demodId].regAddr, ++ xpt_err_replace_valid[demodId].lsbPos, ++ xpt_err_replace_valid[demodId].numOfBits, ++ MXL_TRUE); ++ break; ++ ++ case MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED: ++ default: ++ status |= update_by_mnemonic(state, ++ xpt_err_replace_sync[demodId].regAddr, ++ xpt_err_replace_sync[demodId].lsbPos, ++ xpt_err_replace_sync[demodId].numOfBits, ++ MXL_FALSE); ++ ++ status |= update_by_mnemonic(state, ++ xpt_err_replace_valid[demodId].regAddr, ++ xpt_err_replace_valid[demodId].lsbPos, ++ xpt_err_replace_valid[demodId].numOfBits, ++ MXL_FALSE); ++ ++ break; ++ ++ } ++ ++ if (mpegOutParamPtr->mpegMode != MXL_HYDRA_MPEG_MODE_PARALLEL) { ++ status |= update_by_mnemonic(state, ++ xpt_enable_output[demodId].regAddr, ++ xpt_enable_output[demodId].lsbPos, ++ xpt_enable_output[demodId].numOfBits, ++ mpegOutParamPtr->enable); ++ } ++ return status; ++} ++ ++static int config_mux(struct mxl *state) ++{ ++ SET_REG_FIELD_DATA(XPT_ENABLE_OUTPUT0, 0); ++ SET_REG_FIELD_DATA(XPT_ENABLE_OUTPUT1, 0); ++ SET_REG_FIELD_DATA(XPT_ENABLE_OUTPUT2, 0); ++ SET_REG_FIELD_DATA(XPT_ENABLE_OUTPUT3, 0); ++ SET_REG_FIELD_DATA(XPT_ENABLE_OUTPUT4, 0); ++ SET_REG_FIELD_DATA(XPT_ENABLE_OUTPUT5, 0); ++ SET_REG_FIELD_DATA(XPT_ENABLE_OUTPUT6, 0); ++ SET_REG_FIELD_DATA(XPT_ENABLE_OUTPUT7, 0); ++ SET_REG_FIELD_DATA(XPT_STREAM_MUXMODE0, 1); ++ SET_REG_FIELD_DATA(XPT_STREAM_MUXMODE1, 1); + return 0; +} + -+static int lnbh25_init(struct lnbh25 *lnbh) ++static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg) +{ -+ return lnbh25_write_regs(lnbh, 0, 2); ++ int stat = 0; ++ u8 *buf; ++ ++ if (cfg->fw) ++ return firmware_download(state, cfg->fw, cfg->fw_len); ++ ++ if (!cfg->fw_read) ++ return -1; ++ ++ buf = vmalloc(0x40000); ++ if (!buf) ++ return -ENOMEM; ++ ++ cfg->fw_read(cfg->fw_priv, buf, 0x40000); ++ stat = firmware_download(state, buf, 0x40000); ++ vfree(buf); ++ ++ return stat; +} + -+static void lnbh25_release(struct dvb_frontend *fe) ++static int validate_sku(struct mxl *state) +{ -+ kfree(fe->sec_priv); -+ fe->sec_priv = NULL; -+} ++ u32 padMuxBond, prcmChipId, prcmSoCId; ++ int status; ++ u32 type = state->base->type; + -+struct dvb_frontend *lnbh25_attach(struct dvb_frontend *fe, -+ struct i2c_adapter *i2c, -+ u8 adr) -+{ -+ struct lnbh25 *lnbh = kzalloc(sizeof(struct lnbh25), GFP_KERNEL); -+ if (!lnbh) -+ return NULL; ++ status = GET_REG_FIELD_DATA(PAD_MUX_BOND_OPTION, &padMuxBond); ++ status |= GET_REG_FIELD_DATA(PRCM_PRCM_CHIP_ID, &prcmChipId); ++ status |= GET_REG_FIELD_DATA(PRCM_AFE_SOC_ID, &prcmSoCId); ++ if (status) ++ return -1; + -+ lnbh->i2c = i2c; -+ lnbh->adr = adr; -+ lnbh->boost = 3; ++ pr_info("padMuxBond=%08x, prcmChipId=%08x, prcmSoCId=%08x\n", ++ padMuxBond, prcmChipId, prcmSoCId); ++ ++ if (prcmChipId != 0x560) { ++ switch (padMuxBond) { ++ case MXL_HYDRA_SKU_ID_581: ++ if (type == MXL_HYDRA_DEVICE_581) ++ return 0; ++ if (type == MXL_HYDRA_DEVICE_581S) { ++ state->base->type = MXL_HYDRA_DEVICE_581; ++ return 0; ++ } ++ break; ++ case MXL_HYDRA_SKU_ID_584: ++ if (type == MXL_HYDRA_DEVICE_584) ++ return 0; ++ break; ++ case MXL_HYDRA_SKU_ID_544: ++ if (type == MXL_HYDRA_DEVICE_544) ++ return 0; ++ if (type == MXL_HYDRA_DEVICE_542) ++ return 0; ++ break; ++ case MXL_HYDRA_SKU_ID_582: ++ if (type == MXL_HYDRA_DEVICE_582) ++ return 0; ++ break; ++ default: ++ return -1; ++ } ++ } else { + -+ if (lnbh25_init(lnbh)) { -+ kfree(lnbh); -+ return NULL; + } -+ fe->sec_priv = lnbh; -+ fe->ops.set_voltage = lnbh25_set_voltage; -+ fe->ops.enable_high_lnb_voltage = lnbh25_enable_high_lnb_voltage; -+ fe->ops.release_sec = lnbh25_release; -+ -+ pr_info("LNB25 on %02x\n", lnbh->adr); -+ -+ return fe; ++ return -1; +} -+EXPORT_SYMBOL(lnbh25_attach); + -+MODULE_DESCRIPTION("LNBH25"); -+MODULE_AUTHOR("Ralph Metzler"); ++static int get_fwinfo(struct mxl *state) ++{ ++ int status; ++ u32 val = 0; ++ ++ status = GET_REG_FIELD_DATA(PAD_MUX_BOND_OPTION, &val); ++ if (status) ++ return status; ++ pr_info("chipID=%08x\n", val); ++ ++ status = GET_REG_FIELD_DATA(PRCM_AFE_CHIP_MMSK_VER, &val); ++ if (status) ++ return status; ++ pr_info("chipVer=%08x\n", val); ++ ++ status = read_register(state, HYDRA_FIRMWARE_VERSION, &val); ++ if (status) ++ return status; ++ pr_info("FWVer=%08x\n", val); ++ ++ state->base->fwversion = val; ++ return status; ++} ++ ++ ++static u8 tsMap1_to_1[MXL_HYDRA_DEMOD_MAX] = { ++ MXL_HYDRA_DEMOD_ID_0, ++ MXL_HYDRA_DEMOD_ID_1, ++ MXL_HYDRA_DEMOD_ID_2, ++ MXL_HYDRA_DEMOD_ID_3, ++ MXL_HYDRA_DEMOD_ID_4, ++ MXL_HYDRA_DEMOD_ID_5, ++ MXL_HYDRA_DEMOD_ID_6, ++ MXL_HYDRA_DEMOD_ID_7, ++}; ++ ++static u8 tsMap54x[MXL_HYDRA_DEMOD_MAX] = { ++ MXL_HYDRA_DEMOD_ID_2, ++ MXL_HYDRA_DEMOD_ID_3, ++ MXL_HYDRA_DEMOD_ID_4, ++ MXL_HYDRA_DEMOD_ID_5, ++ MXL_HYDRA_DEMOD_MAX, ++ MXL_HYDRA_DEMOD_MAX, ++ MXL_HYDRA_DEMOD_MAX, ++ MXL_HYDRA_DEMOD_MAX, ++}; ++ ++static int probe(struct mxl *state, struct mxl5xx_cfg *cfg) ++{ ++ u32 chipver; ++ int fw, status, j; ++ MXL_HYDRA_MPEGOUT_PARAM_T mpegInterfaceCfg; ++ ++ state->base->ts_map = tsMap1_to_1; ++ ++ switch (state->base->type) { ++ case MXL_HYDRA_DEVICE_581: ++ case MXL_HYDRA_DEVICE_581S: ++ state->base->can_clkout = 1; ++ state->base->demod_num = 8; ++ state->base->tuner_num = 1; ++ state->base->sku_type = MXL_HYDRA_SKU_TYPE_581; ++ break; ++ case MXL_HYDRA_DEVICE_582: ++ state->base->can_clkout = 1; ++ state->base->demod_num = 8; ++ state->base->tuner_num = 3; ++ state->base->sku_type = MXL_HYDRA_SKU_TYPE_582; ++ break; ++ case MXL_HYDRA_DEVICE_585: ++ state->base->can_clkout = 0; ++ state->base->demod_num = 8; ++ state->base->tuner_num = 4; ++ state->base->sku_type = MXL_HYDRA_SKU_TYPE_585; ++ break; ++ case MXL_HYDRA_DEVICE_544: ++ state->base->can_clkout = 0; ++ state->base->demod_num = 4; ++ state->base->tuner_num = 4; ++ state->base->sku_type = MXL_HYDRA_SKU_TYPE_544; ++ state->base->ts_map = tsMap54x; ++ break; ++ case MXL_HYDRA_DEVICE_541: ++ case MXL_HYDRA_DEVICE_541S: ++ state->base->can_clkout = 0; ++ state->base->demod_num = 4; ++ state->base->tuner_num = 1; ++ state->base->sku_type = MXL_HYDRA_SKU_TYPE_541; ++ state->base->ts_map = tsMap54x; ++ break; ++ case MXL_HYDRA_DEVICE_561: ++ case MXL_HYDRA_DEVICE_561S: ++ state->base->can_clkout = 0; ++ state->base->demod_num = 6; ++ state->base->tuner_num = 1; ++ state->base->sku_type = MXL_HYDRA_SKU_TYPE_561; ++ break; ++ case MXL_HYDRA_DEVICE_568: ++ state->base->can_clkout = 0; ++ state->base->demod_num = 8; ++ state->base->tuner_num = 1; ++ state->base->chan_bond = 1; ++ state->base->sku_type = MXL_HYDRA_SKU_TYPE_568; ++ break; ++ case MXL_HYDRA_DEVICE_542: ++ state->base->can_clkout = 1; ++ state->base->demod_num = 4; ++ state->base->tuner_num = 3; ++ state->base->sku_type = MXL_HYDRA_SKU_TYPE_542; ++ state->base->ts_map = tsMap54x; ++ break; ++ case MXL_HYDRA_DEVICE_TEST: ++ case MXL_HYDRA_DEVICE_584: ++ default: ++ state->base->can_clkout = 0; ++ state->base->demod_num = 8; ++ state->base->tuner_num = 4; ++ state->base->sku_type = MXL_HYDRA_SKU_TYPE_584; ++ break; ++ } ++ ++ status = validate_sku(state); ++ if (status) ++ return status; ++ ++ SET_REG_FIELD_DATA(PRCM_AFE_REG_CLOCK_ENABLE, 1); ++ SET_REG_FIELD_DATA(PRCM_PRCM_AFE_REG_SOFT_RST_N, 1); ++ status = GET_REG_FIELD_DATA(PRCM_CHIP_VERSION, &chipver); ++ if (status) ++ state->base->chipversion = 0; ++ else ++ state->base->chipversion = (chipver == 2) ? 2 : 1; ++ pr_info("Hydra chip version %u\n", state->base->chipversion); ++ ++ cfg_dev_xtal(state, cfg->clk, cfg->cap, 0); ++ ++ fw = firmware_is_alive(state); ++ if (!fw) { ++ status = load_fw(state, cfg); ++ if (status) ++ return status; ++ } ++ get_fwinfo(state); ++ ++ config_mux(state); ++ mpegInterfaceCfg.enable = MXL_ENABLE; ++ mpegInterfaceCfg.lsbOrMsbFirst = MXL_HYDRA_MPEG_SERIAL_MSB_1ST; ++ /* supports only (0-104&139)MHz */ ++ if (cfg->ts_clk) ++ mpegInterfaceCfg.maxMpegClkRate = cfg->ts_clk; ++ else ++ mpegInterfaceCfg.maxMpegClkRate = 69; /* 139; */ ++ mpegInterfaceCfg.mpegClkPhase = MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_0_DEG; ++ mpegInterfaceCfg.mpegClkPol = MXL_HYDRA_MPEG_CLK_IN_PHASE; ++ /* MXL_HYDRA_MPEG_CLK_GAPPED; */ ++ mpegInterfaceCfg.mpegClkType = MXL_HYDRA_MPEG_CLK_CONTINUOUS; ++ mpegInterfaceCfg.mpegErrorIndication = ++ MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED; ++ mpegInterfaceCfg.mpegMode = MXL_HYDRA_MPEG_MODE_SERIAL_3_WIRE; ++ mpegInterfaceCfg.mpegSyncPol = MXL_HYDRA_MPEG_ACTIVE_HIGH; ++ mpegInterfaceCfg.mpegSyncPulseWidth = MXL_HYDRA_MPEG_SYNC_WIDTH_BIT; ++ mpegInterfaceCfg.mpegValidPol = MXL_HYDRA_MPEG_ACTIVE_HIGH; ++ ++ ++ for (j = 0; j < state->base->demod_num; j++) { ++ status = config_ts(state, (MXL_HYDRA_DEMOD_ID_E) j, ++ &mpegInterfaceCfg); ++ if (status) ++ return status; ++ } ++ set_drive_strength(state, 1); ++ return 0; ++} ++ ++struct dvb_frontend *mxl5xx_attach(struct i2c_adapter *i2c, ++ struct mxl5xx_cfg *cfg, ++ u32 demod, u32 tuner) ++{ ++ struct mxl *state; ++ struct mxl_base *base; ++ ++ state = kzalloc(sizeof(struct mxl), GFP_KERNEL); ++ if (!state) ++ return NULL; ++ ++ state->demod = demod; ++ state->tuner = tuner; ++ state->tuner_in_use = 0xffffffff; ++ ++ base = match_base(i2c, cfg->adr); ++ if (base) { ++ base->count++; ++ if (base->count > base->demod_num) ++ goto fail; ++ state->base = base; ++ } else { ++ base = kzalloc(sizeof(struct mxl_base), GFP_KERNEL); ++ if (!base) ++ goto fail; ++ base->i2c = i2c; ++ base->adr = cfg->adr; ++ base->type = cfg->type; ++ base->count = 1; ++ mutex_init(&base->i2c_lock); ++ mutex_init(&base->status_lock); ++ mutex_init(&base->tune_lock); ++ INIT_LIST_HEAD(&base->mxls); ++ ++ state->base = base; ++ if (probe(state, cfg) < 0) { ++ kfree(base); ++ goto fail; ++ } ++ list_add(&base->mxllist, &mxllist); ++ } ++ state->fe.ops = mxl_ops; ++ state->fe.ops.xbar[1] = demod; ++ state->fe.demodulator_priv = state; ++ state->fe.dtv_property_cache.input = tuner; ++ list_add(&state->mxl, &base->mxls); ++ return &state->fe; ++ ++fail: ++ kfree(state); ++ return NULL; ++} ++EXPORT_SYMBOL_GPL(mxl5xx_attach); ++ ++ ++MODULE_DESCRIPTION("MXL5XX driver"); ++MODULE_AUTHOR("Ralph and Marcus Metzler, Metzler Brothers Systementwicklung GbR"); +MODULE_LICENSE("GPL"); -diff --git a/drivers/media/dvb-frontends/lnbh25.h b/drivers/media/dvb-frontends/lnbh25.h +diff --git a/drivers/media/dvb-frontends/mxl5xx.h b/drivers/media/dvb-frontends/mxl5xx.h new file mode 100644 -index 0000000..4e8b3cc +index 0000000..e02ba1d --- /dev/null -+++ b/drivers/media/dvb-frontends/lnbh25.h -@@ -0,0 +1,28 @@ -+/* -+ * lnbh25.h -+ */ ++++ b/drivers/media/dvb-frontends/mxl5xx.h +@@ -0,0 +1,39 @@ ++#ifndef _MXL5XX_H_ ++#define _MXL5XX_H_ + -+#ifndef _LNBH25_H -+#define _LNBH25_H ++#include ++#include + -+#include ++struct mxl5xx_cfg { ++ u8 adr; ++ u8 type; ++ u32 cap; ++ u32 clk; ++ u32 ts_clk; + -+#if defined(CONFIG_DVB_LNBH25) || \ -+ (defined(CONFIG_DVB_LNBH25_MODULE) && defined(MODULE)) ++ u8 *fw; ++ u32 fw_len; ++ ++ int (*fw_read)(void *priv, u8 *buf, u32 len); ++ void *fw_priv; ++}; ++ ++#if IS_REACHABLE(CONFIG_DVB_MXL5XX) ++ ++extern struct dvb_frontend *mxl5xx_attach(struct i2c_adapter *i2c, ++ struct mxl5xx_cfg *cfg, ++ u32 demod, u32 tuner); + -+extern struct dvb_frontend *lnbh25_attach(struct dvb_frontend *fe, -+ struct i2c_adapter *i2c, -+ u8 i2c_addr); +#else + -+static inline struct dvb_frontend *lnbh25_attach(struct dvb_frontend *fe, -+ struct i2c_adapter *i2c, -+ u8 i2c_addr) ++static inline struct dvb_frontend *mxl5xx_attach(struct i2c_adapter *i2c, ++ struct mxl5xx_cfg *cfg, ++ u32 demod, u32 tuner) +{ + pr_warn("%s: driver disabled by Kconfig\n", __func__); + return NULL; +} + ++#endif /* CONFIG_DVB_MXL5XX */ ++ ++#endif /* _MXL5XX_H_ */ +diff --git a/drivers/media/dvb-frontends/mxl5xx_defs.h b/drivers/media/dvb-frontends/mxl5xx_defs.h +new file mode 100644 +index 0000000..35b5c0b +--- /dev/null ++++ b/drivers/media/dvb-frontends/mxl5xx_defs.h +@@ -0,0 +1,818 @@ ++/* ++ * Defines for the Maxlinear MX58x family of tuners/demods ++ * ++ * Copyright (C) 2014 Digital Devices GmbH ++ * ++ * based on code: ++ * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved ++ * which was released under GPL V2 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2, as published by the Free Software Foundation. ++ */ ++ ++typedef enum ++{ ++ MXL_DISABLE = 0, ++ MXL_ENABLE = 1, ++ ++ MXL_FALSE = 0, ++ MXL_TRUE = 1, ++ ++ MXL_INVALID = 0, ++ MXL_VALID = 1, ++ ++ MXL_NO = 0, ++ MXL_YES = 1, ++ ++ MXL_OFF = 0, ++ MXL_ON = 1 ++} MXL_BOOL_E; ++ ++// Firmware-Host Command IDs ++typedef enum ++{ ++ //--Device command IDs-- ++ MXL_HYDRA_DEV_NO_OP_CMD = 0, //No OP ++ ++ MXL_HYDRA_DEV_SET_POWER_MODE_CMD = 1, ++ MXL_HYDRA_DEV_SET_OVERWRITE_DEF_CMD = 2, ++ ++ // Host-used CMD, not used by firmware ++ MXL_HYDRA_DEV_FIRMWARE_DOWNLOAD_CMD = 3, ++ ++ // Additional CONTROL types from DTV ++ MXL_HYDRA_DEV_SET_BROADCAST_PID_STB_ID_CMD = 4, ++ MXL_HYDRA_DEV_GET_PMM_SLEEP_CMD = 5, ++ ++ //--Tuner command IDs-- ++ MXL_HYDRA_TUNER_TUNE_CMD = 6, ++ MXL_HYDRA_TUNER_GET_STATUS_CMD = 7, ++ ++ //--Demod command IDs-- ++ MXL_HYDRA_DEMOD_SET_PARAM_CMD = 8, ++ MXL_HYDRA_DEMOD_GET_STATUS_CMD = 9, ++ ++ MXL_HYDRA_DEMOD_RESET_FEC_COUNTER_CMD = 10, ++ ++ MXL_HYDRA_DEMOD_SET_PKT_NUM_CMD = 11, ++ ++ MXL_HYDRA_DEMOD_SET_IQ_SOURCE_CMD = 12, ++ MXL_HYDRA_DEMOD_GET_IQ_DATA_CMD = 13, ++ ++ MXL_HYDRA_DEMOD_GET_M68HC05_VER_CMD = 14, ++ ++ MXL_HYDRA_DEMOD_SET_ERROR_COUNTER_MODE_CMD = 15, ++ ++ //--- ABORT channel tune ++ MXL_HYDRA_ABORT_TUNE_CMD = 16, // Abort current tune command. ++ ++ //--SWM/FSK command IDs-- ++ MXL_HYDRA_FSK_RESET_CMD = 17, ++ MXL_HYDRA_FSK_MSG_CMD = 18, ++ MXL_HYDRA_FSK_SET_OP_MODE_CMD = 19, ++ ++ //--DiSeqC command IDs-- ++ MXL_HYDRA_DISEQC_MSG_CMD = 20, ++ MXL_HYDRA_DISEQC_COPY_MSG_TO_MAILBOX = 21, ++ MXL_HYDRA_DISEQC_CFG_MSG_CMD = 22, ++ ++ //--- FFT Debug Command IDs-- ++ MXL_HYDRA_REQ_FFT_SPECTRUM_CMD = 23, ++ ++ // -- Demod scramblle code ++ MXL_HYDRA_DEMOD_SCRAMBLE_CODE_CMD = 24, ++ ++ //---For host to know how many commands in total--- ++ MXL_HYDRA_LAST_HOST_CMD = 25, ++ ++ MXL_HYDRA_DEMOD_INTR_TYPE_CMD = 47, ++ MXL_HYDRA_DEV_INTR_CLEAR_CMD = 48, ++ MXL_HYDRA_TUNER_SPECTRUM_REQ_CMD = 53, ++ MXL_HYDRA_TUNER_ACTIVATE_CMD = 55, ++ MXL_HYDRA_DEV_CFG_POWER_MODE_CMD = 56, ++ MXL_HYDRA_DEV_XTAL_CAP_CMD = 57, ++ MXL_HYDRA_DEV_CFG_SKU_CMD = 58, ++ MXL_HYDRA_TUNER_SPECTRUM_MIN_GAIN_CMD = 59, ++ MXL_HYDRA_DISEQC_CONT_TONE_CFG = 60, ++ MXL_HYDRA_DEV_RF_WAKE_UP_CMD = 61, ++ MXL_HYDRA_DEMOD_CFG_EQ_CTRL_PARAM_CMD = 62, ++ MXL_HYDRA_DEMOD_FREQ_OFFSET_SEARCH_RANGE_CMD = 63, ++ MXL_HYDRA_DEV_REQ_PWR_FROM_ADCRSSI_CMD = 64, ++ ++ MXL_XCPU_PID_FLT_CFG_CMD = 65, ++ MXL_XCPU_SHMEM_TEST_CMD = 66, ++ MXL_XCPU_ABORT_TUNE_CMD = 67, ++ MXL_XCPU_CHAN_TUNE_CMD = 68, ++ MXL_XCPU_FLT_BOND_HDRS_CMD = 69, ++ ++ MXL_HYDRA_DEV_BROADCAST_WAKE_UP_CMD = 70, ++ MXL_HYDRA_FSK_CFG_FSK_FREQ_CMD = 71, ++ MXL_HYDRA_FSK_POWER_DOWN_CMD = 72, ++ MXL_XCPU_CLEAR_CB_STATS_CMD = 73, ++ MXL_XCPU_CHAN_BOND_RESTART_CMD = 74 ++} MXL_HYDRA_HOST_CMD_ID_E; ++ ++#define MXL_ENABLE_BIG_ENDIAN (0) ++ ++#define MXL_HYDRA_OEM_MAX_BLOCK_WRITE_LENGTH 248 ++ ++#define MXL_HYDRA_OEM_MAX_CMD_BUFF_LEN (248) ++ ++#define MXL_HYDRA_CAP_MIN 10 ++#define MXL_HYDRA_CAP_MAX 33 ++ ++#define MXL_HYDRA_PLID_REG_READ 0xFB // Read register PLID ++#define MXL_HYDRA_PLID_REG_WRITE 0xFC // Write register PLID ++ ++#define MXL_HYDRA_PLID_CMD_READ 0xFD // Command Read PLID ++#define MXL_HYDRA_PLID_CMD_WRITE 0xFE // Command Write PLID ++ ++#define MXL_HYDRA_REG_SIZE_IN_BYTES 4 // Hydra register size in bytes ++#define MXL_HYDRA_I2C_HDR_SIZE (2 * sizeof(u8)) // PLID + LEN(0xFF) ++#define MXL_HYDRA_CMD_HEADER_SIZE (MXL_HYDRA_REG_SIZE_IN_BYTES + MXL_HYDRA_I2C_HDR_SIZE) ++ ++#define MXL_HYDRA_SKU_ID_581 0 ++#define MXL_HYDRA_SKU_ID_584 1 ++#define MXL_HYDRA_SKU_ID_585 2 ++#define MXL_HYDRA_SKU_ID_544 3 ++#define MXL_HYDRA_SKU_ID_561 4 ++#define MXL_HYDRA_SKU_ID_582 5 ++#define MXL_HYDRA_SKU_ID_568 6 ++ ++// macro for register write data buffer size (PLID + LEN (0xFF) + RegAddr + RegData) ++#define MXL_HYDRA_REG_WRITE_LEN (MXL_HYDRA_I2C_HDR_SIZE + (2 * MXL_HYDRA_REG_SIZE_IN_BYTES)) ++ ++// maro to extract a single byte from 4-byte(32-bit) data ++#define GET_BYTE(x,n) (((x) >> (8*(n))) & 0xFF) ++ ++#define MAX_CMD_DATA 512 ++ ++#define MXL_GET_REG_MASK_32(lsbLoc,numOfBits) ((0xFFFFFFFF >> (32 - (numOfBits))) << (lsbLoc)) ++ ++#define GET_REG_FIELD_DATA(fieldName, dataPtr) read_by_mnemonic(state, fieldName, dataPtr); ++#define SET_REG_FIELD_DATA(fieldName, data) update_by_mnemonic(state, fieldName, data); ++ ++#define FW_DL_SIGN (0xDEADBEEF) ++ ++#define MBIN_FORMAT_VERSION '1' ++#define MBIN_FILE_HEADER_ID 'M' ++#define MBIN_SEGMENT_HEADER_ID 'S' ++#define MBIN_MAX_FILE_LENGTH (1<<23) ++ ++typedef struct ++{ ++ u8 id; ++ u8 fmtVersion; ++ u8 headerLen; ++ u8 numSegments; ++ u8 entryAddress[4]; ++ u8 imageSize24[3]; ++ u8 imageChecksum; ++ u8 reserved[4]; ++} MBIN_FILE_HEADER_T; ++ ++typedef struct ++{ ++ MBIN_FILE_HEADER_T header; ++ u8 data[1]; ++} MBIN_FILE_T; ++ ++typedef struct ++{ ++ u8 id; ++ u8 len24[3]; ++ u8 address[4]; ++} MBIN_SEGMENT_HEADER_T; ++ ++ ++typedef struct ++{ ++ MBIN_SEGMENT_HEADER_T header; ++ u8 data[1]; ++} MBIN_SEGMENT_T; ++ ++ ++typedef enum { MXL_CMD_WRITE = 0, MXL_CMD_READ} MXL_CMD_TYPE_E; ++ ++#define BUILD_HYDRA_CMD(cmdID, reqType, size, dataPtr, cmdBuff) \ ++ do { \ ++ cmdBuff[0] = ((reqType == MXL_CMD_WRITE) ? MXL_HYDRA_PLID_CMD_WRITE : MXL_HYDRA_PLID_CMD_READ); \ ++ cmdBuff[1] = (size > 251) ? 0xff : (u8) (size + 4); \ ++ cmdBuff[2] = size; \ ++ cmdBuff[3] = cmdID; \ ++ cmdBuff[4] = 0x00; \ ++ cmdBuff[5] = 0x00; \ ++ convert_endian(MXL_ENABLE_BIG_ENDIAN, size, (u8 *)dataPtr); \ ++ memcpy((void *)&cmdBuff[6], dataPtr, size); \ ++ } while(0) //; ++ ++typedef struct { ++ u32 regAddr; ++ u8 lsbPos; ++ u8 numOfBits; ++} MXL_REG_FIELD_T; ++ ++typedef struct { ++ u32 dataSize; ++ u8 data[MAX_CMD_DATA]; ++} MXL_DEV_CMD_DATA_T; ++ ++typedef enum ++{ ++ MXL_HYDRA_SKU_TYPE_MIN = 0x00, ++ MXL_HYDRA_SKU_TYPE_581 = 0x00, ++ MXL_HYDRA_SKU_TYPE_584 = 0x01, ++ MXL_HYDRA_SKU_TYPE_585 = 0x02, ++ MXL_HYDRA_SKU_TYPE_544 = 0x03, ++ MXL_HYDRA_SKU_TYPE_561 = 0x04, ++ MXL_HYDRA_SKU_TYPE_5xx = 0x05, ++ MXL_HYDRA_SKU_TYPE_5yy = 0x06, ++ MXL_HYDRA_SKU_TYPE_511 = 0x07, ++ MXL_HYDRA_SKU_TYPE_561_DE = 0x08, ++ MXL_HYDRA_SKU_TYPE_582 = 0x09, ++ MXL_HYDRA_SKU_TYPE_541 = 0x0A, ++ MXL_HYDRA_SKU_TYPE_568 = 0x0B, ++ MXL_HYDRA_SKU_TYPE_542 = 0x0C, ++ MXL_HYDRA_SKU_TYPE_MAX = 0x0D, ++} MXL_HYDRA_SKU_TYPE_E; ++ ++typedef struct ++{ ++ MXL_HYDRA_SKU_TYPE_E skuType; ++} MXL_HYDRA_SKU_COMMAND_T; ++ ++ ++typedef enum ++{ ++ MXL_HYDRA_DEMOD_ID_0 = 0, ++ MXL_HYDRA_DEMOD_ID_1, ++ MXL_HYDRA_DEMOD_ID_2, ++ MXL_HYDRA_DEMOD_ID_3, ++ MXL_HYDRA_DEMOD_ID_4, ++ MXL_HYDRA_DEMOD_ID_5, ++ MXL_HYDRA_DEMOD_ID_6, ++ MXL_HYDRA_DEMOD_ID_7, ++ MXL_HYDRA_DEMOD_MAX ++} MXL_HYDRA_DEMOD_ID_E; ++ ++#define MXL_DEMOD_SCRAMBLE_SEQ_LEN 12 ++ ++#define MAX_STEP_SIZE_24_XTAL_102_05_KHZ 195 ++#define MAX_STEP_SIZE_24_XTAL_204_10_KHZ 215 ++#define MAX_STEP_SIZE_24_XTAL_306_15_KHZ 203 ++#define MAX_STEP_SIZE_24_XTAL_408_20_KHZ 177 ++ ++#define MAX_STEP_SIZE_27_XTAL_102_05_KHZ 195 ++#define MAX_STEP_SIZE_27_XTAL_204_10_KHZ 215 ++#define MAX_STEP_SIZE_27_XTAL_306_15_KHZ 203 ++#define MAX_STEP_SIZE_27_XTAL_408_20_KHZ 177 ++ ++#define MXL_HYDRA_SPECTRUM_MIN_FREQ_KHZ 300000 ++#define MXL_HYDRA_SPECTRUM_MAX_FREQ_KHZ 2350000 ++ ++typedef enum ++{ ++ DMD_STANDARD_ADDR = 0, ++ DMD_SPECTRUM_INVERSION_ADDR, ++ DMD_SPECTRUM_ROLL_OFF_ADDR, ++ DMD_SYMBOL_RATE_ADDR, ++ DMD_MODULATION_SCHEME_ADDR, ++ DMD_FEC_CODE_RATE_ADDR, ++ DMD_SNR_ADDR, ++ DMD_FREQ_OFFSET_ADDR, ++ DMD_CTL_FREQ_OFFSET_ADDR, ++ DMD_STR_FREQ_OFFSET_ADDR, ++ DMD_FTL_FREQ_OFFSET_ADDR, ++ DMD_STR_NBC_SYNC_LOCK_ADDR, ++ DMD_CYCLE_SLIP_COUNT_ADDR, ++ DMD_DISPLAY_IQ_ADDR, ++ DMD_DVBS2_CRC_ERRORS_ADDR, ++ DMD_DVBS2_PER_COUNT_ADDR, ++ DMD_DVBS2_PER_WINDOW_ADDR, ++ DMD_DVBS_CORR_RS_ERRORS_ADDR, ++ DMD_DVBS_UNCORR_RS_ERRORS_ADDR, ++ DMD_DVBS_BER_COUNT_ADDR, ++ DMD_DVBS_BER_WINDOW_ADDR, ++ DMD_TUNER_ID_ADDR, ++ DMD_DVBS2_PILOT_ON_OFF_ADDR, ++ DMD_FREQ_SEARCH_RANGE_IN_KHZ_ADDR, ++ ++ MXL_DEMOD_CHAN_PARAMS_BUFF_SIZE, ++} MXL_DEMOD_CHAN_PARAMS_OFFSET_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_TUNER_ID_0 = 0, ++ MXL_HYDRA_TUNER_ID_1, ++ MXL_HYDRA_TUNER_ID_2, ++ MXL_HYDRA_TUNER_ID_3, ++ MXL_HYDRA_TUNER_MAX ++} MXL_HYDRA_TUNER_ID_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_DSS = 0, ++ MXL_HYDRA_DVBS, ++ MXL_HYDRA_DVBS2, ++} MXL_HYDRA_BCAST_STD_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_FEC_AUTO = 0, ++ MXL_HYDRA_FEC_1_2, ++ MXL_HYDRA_FEC_3_5, ++ MXL_HYDRA_FEC_2_3, ++ MXL_HYDRA_FEC_3_4, ++ MXL_HYDRA_FEC_4_5, ++ MXL_HYDRA_FEC_5_6, ++ MXL_HYDRA_FEC_6_7, ++ MXL_HYDRA_FEC_7_8, ++ MXL_HYDRA_FEC_8_9, ++ MXL_HYDRA_FEC_9_10, ++} MXL_HYDRA_FEC_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_MOD_AUTO = 0, ++ MXL_HYDRA_MOD_QPSK, ++ MXL_HYDRA_MOD_8PSK ++} MXL_HYDRA_MODULATION_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_SPECTRUM_AUTO = 0, ++ MXL_HYDRA_SPECTRUM_INVERTED, ++ MXL_HYDRA_SPECTRUM_NON_INVERTED, ++} MXL_HYDRA_SPECTRUM_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_ROLLOFF_AUTO = 0, ++ MXL_HYDRA_ROLLOFF_0_20, ++ MXL_HYDRA_ROLLOFF_0_25, ++ MXL_HYDRA_ROLLOFF_0_35 ++} MXL_HYDRA_ROLLOFF_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_PILOTS_OFF = 0, ++ MXL_HYDRA_PILOTS_ON, ++ MXL_HYDRA_PILOTS_AUTO ++} MXL_HYDRA_PILOTS_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_FORMATTER = 0, ++ MXL_HYDRA_LEGACY_FEC, ++ MXL_HYDRA_FREQ_RECOVERY, ++ MXL_HYDRA_NBC, ++ MXL_HYDRA_CTL, ++ MXL_HYDRA_EQ, ++} MXL_HYDRA_CONSTELLATION_SRC_E; ++ ++typedef struct ++{ ++ int agcLock; // AGC lock info ++ int fecLock; // Demod FEC block lock info ++} MXL_HYDRA_DEMOD_LOCK_T; ++ ++typedef struct ++{ ++ u32 rsErrors; // RS decoder err counter ++ u32 berWindow; // Ber Windows ++ u32 berCount; // BER count ++ u32 berWindow_Iter1; // Ber Windows - post viterbi ++ u32 berCount_Iter1; // BER count - post viterbi ++} MXL_HYDRA_DEMOD_STATUS_DVBS_T; ++ ++typedef struct ++{ ++ u32 rsErrors; // RS decoder err counter ++ u32 berWindow; // Ber Windows ++ u32 berCount; // BER count ++} MXL_HYDRA_DEMOD_STATUS_DSS_T; ++ ++typedef struct ++{ ++ u32 crcErrors; // CRC error counter ++ u32 packetErrorCount; // Number of packet errors ++ u32 totalPackets; // Total packets ++} MXL_HYDRA_DEMOD_STATUS_DVBS2_T; ++ ++typedef struct ++{ ++ MXL_HYDRA_BCAST_STD_E standardMask; // Standard DVB-S, DVB-S2 or DSS ++ ++ union ++ { ++ MXL_HYDRA_DEMOD_STATUS_DVBS_T demodStatus_DVBS; // DVB-S demod status ++ MXL_HYDRA_DEMOD_STATUS_DVBS2_T demodStatus_DVBS2; // DVB-S2 demod status ++ MXL_HYDRA_DEMOD_STATUS_DSS_T demodStatus_DSS; // DSS demod status ++ } u; ++ ++} MXL_HYDRA_DEMOD_STATUS_T; ++ ++typedef struct ++{ ++ s32 carrierOffsetInHz; // CRL offset info ++ s32 symbolOffsetInSymbol; // SRL offset info ++} MXL_HYDRA_DEMOD_SIG_OFFSET_INFO_T; ++ ++typedef struct ++{ ++ u8 scrambleSequence[MXL_DEMOD_SCRAMBLE_SEQ_LEN]; // scramble sequence ++ u32 scrambleCode; // scramble gold code ++} MXL_HYDRA_DEMOD_SCRAMBLE_INFO_T; ++ ++typedef enum ++{ ++ MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, // 102.05 KHz for 24 MHz XTAL ++ MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, // 204.10 KHz for 24 MHz XTAL ++ MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, // 306.15 KHz for 24 MHz XTAL ++ MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, // 408.20 KHz for 24 MHz XTAL ++ ++ MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, // 102.05 KHz for 27 MHz XTAL ++ MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, // 204.35 KHz for 27 MHz XTAL ++ MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, // 306.52 KHz for 27 MHz XTAL ++ MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, // 408.69 KHz for 27 MHz XTAL ++ ++} MXL_HYDRA_SPECTRUM_STEP_SIZE_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_SPECTRUM_RESOLUTION_00_1_DB, // 0.1 dB ++ MXL_HYDRA_SPECTRUM_RESOLUTION_01_0_DB, // 1.0 dB ++ MXL_HYDRA_SPECTRUM_RESOLUTION_05_0_DB, // 5.0 dB ++ MXL_HYDRA_SPECTRUM_RESOLUTION_10_0_DB, // 10 dB ++} MXL_HYDRA_SPECTRUM_RESOLUTION_E; ++ ++typedef enum ++{ ++ MXL_SPECTRUM_NO_ERROR, ++ MXL_SPECTRUM_INVALID_PARAMETER, ++ MXL_SPECTRUM_INVALID_STEP_SIZE, ++ MXL_SPECTRUM_BW_CANNOT_BE_COVERED, ++ MXL_SPECTRUM_DEMOD_BUSY, ++ MXL_SPECTRUM_TUNER_NOT_ENABLED, ++ ++} MXL_HYDRA_SPECTRUM_ERROR_CODE_E; ++ ++typedef struct ++{ ++ u32 tunerIndex; // TUNER Ctrl: one of MXL58x_TUNER_ID_E ++ u32 demodIndex; // DEMOD Ctrl: one of MXL58x_DEMOD_ID_E ++ MXL_HYDRA_SPECTRUM_STEP_SIZE_E stepSizeInKHz; ++ u32 startingFreqInkHz; ++ u32 totalSteps; ++ MXL_HYDRA_SPECTRUM_RESOLUTION_E spectrumDivision; ++} MXL_HYDRA_SPECTRUM_REQ_T; ++ ++typedef enum ++{ ++ MXL_HYDRA_SEARCH_MAX_OFFSET = 0, // DMD searches for max freq offset (i.e. 5MHz) ++ MXL_HYDRA_SEARCH_BW_PLUS_ROLLOFF, // DMD searches for BW + ROLLOFF/2 ++} MXL_HYDRA_SEARCH_FREQ_OFFSET_TYPE_E; ++ ++typedef struct ++{ ++ u32 demodIndex; ++ MXL_HYDRA_SEARCH_FREQ_OFFSET_TYPE_E searchType; ++} MXL58x_CFG_FREQ_OFF_SEARCH_RANGE_T; ++ ++ ++ ++ ++// there are two slices ++// slice0 - TS0, TS1, TS2 & TS3 ++// slice1 - TS4, TS5, TS6 & TS7 ++#define MXL_HYDRA_TS_SLICE_MAX 2 ++ ++#define MAX_FIXED_PID_NUM 32 ++ ++#define MXL_HYDRA_NCO_CLK 418 // 418 MHz ++ ++#define MXL_HYDRA_MAX_TS_CLOCK 139 // 139 MHz ++ ++#define MXL_HYDRA_TS_FIXED_PID_FILT_SIZE 32 ++ ++#define MXL_HYDRA_SHARED_PID_FILT_SIZE_DEFAULT 33 // Shared PID filter size in 1-1 mux mode ++#define MXL_HYDRA_SHARED_PID_FILT_SIZE_2_TO_1 66 // Shared PID filter size in 2-1 mux mode ++#define MXL_HYDRA_SHARED_PID_FILT_SIZE_4_TO_1 132 // Shared PID filter size in 4-1 mux mode ++ ++typedef enum ++{ ++ MXL_HYDRA_SOFTWARE_PID_BANK = 0, ++ MXL_HYDRA_HARDWARE_PID_BANK, ++} MXL_HYDRA_PID_BANK_TYPE_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_TS_MUX_PID_REMAP = 0, ++ MXL_HYDRA_TS_MUX_PREFIX_EXTRA_HEADER = 1, ++} MXL_HYDRA_TS_MUX_MODE_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_TS_MUX_DISABLE = 0, // No Mux ( 1 TSIF to 1 TSIF) ++ MXL_HYDRA_TS_MUX_2_TO_1, // Mux 2 TSIF to 1 TSIF ++ MXL_HYDRA_TS_MUX_4_TO_1, // Mux 4 TSIF to 1 TSIF ++} MXL_HYDRA_TS_MUX_TYPE_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_TS_GROUP_0_3 = 0, // TS group 0 to 3 (TS0, TS1, TS2 & TS3) ++ MXL_HYDRA_TS_GROUP_4_7, // TS group 0 to 3 (TS4, TS5, TS6 & TS7) ++} MXL_HYDRA_TS_GROUP_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_TS_PIDS_ALLOW_ALL = 0, // Allow all pids ++ MXL_HYDRA_TS_PIDS_DROP_ALL, // Drop all pids ++ MXL_HYDRA_TS_INVALIDATE_PID_FILTER, // Delete current PD filter in the device ++ ++} MXL_HYDRA_TS_PID_FLT_CTRL_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_TS_PID_FIXED = 0, ++ MXL_HYDRA_TS_PID_REGULAR, ++} MXL_HYDRA_TS_PID_TYPE_E; ++ ++typedef struct ++{ ++ u16 originalPid; // pid from TS ++ u16 remappedPid; // remapped pid ++ MXL_BOOL_E enable; // enable or disable pid ++ MXL_BOOL_E allowOrDrop; // allow or drop pid ++ MXL_BOOL_E enablePidRemap; // enable or disable pid remap ++ u8 bondId; // Bond ID in A0 always 0 - Only for 568 Sku ++ u8 destId; // Output port ID for the PID - Only for 568 Sku ++} MXL_HYDRA_TS_PID_T; ++ ++typedef struct ++{ ++ MXL_BOOL_E enable; ++ u8 numByte; ++ u8 header[12]; ++} MXL_HYDRA_TS_MUX_PREFIX_HEADER_T; ++ ++typedef enum ++{ ++ MXL_HYDRA_PID_BANK_A = 0, ++ MXL_HYDRA_PID_BANK_B, ++} MXL_HYDRA_PID_FILTER_BANK_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_MPEG_SERIAL_MSB_1ST = 0, ++ MXL_HYDRA_MPEG_SERIAL_LSB_1ST, ++ ++ MXL_HYDRA_MPEG_SYNC_WIDTH_BIT = 0, ++ MXL_HYDRA_MPEG_SYNC_WIDTH_BYTE ++} MXL_HYDRA_MPEG_DATA_FMT_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_MPEG_MODE_SERIAL_4_WIRE = 0, // MPEG 4 Wire serial mode ++ MXL_HYDRA_MPEG_MODE_SERIAL_3_WIRE, // MPEG 3 Wire serial mode ++ MXL_HYDRA_MPEG_MODE_SERIAL_2_WIRE, // MPEG 2 Wire serial mode ++ MXL_HYDRA_MPEG_MODE_PARALLEL // MPEG parallel mode - valid only for MxL581 ++} MXL_HYDRA_MPEG_MODE_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_MPEG_CLK_CONTINUOUS = 0, // Continuous MPEG clock ++ MXL_HYDRA_MPEG_CLK_GAPPED, // Gapped (gated) MPEG clock ++} MXL_HYDRA_MPEG_CLK_TYPE_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_MPEG_ACTIVE_LOW = 0, ++ MXL_HYDRA_MPEG_ACTIVE_HIGH, ++ ++ MXL_HYDRA_MPEG_CLK_NEGATIVE = 0, ++ MXL_HYDRA_MPEG_CLK_POSITIVE, ++ ++ MXL_HYDRA_MPEG_CLK_IN_PHASE = 0, ++ MXL_HYDRA_MPEG_CLK_INVERTED, ++} MXL_HYDRA_MPEG_CLK_FMT_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_0_DEG = 0, ++ MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_90_DEG, ++ MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_180_DEG, ++ MXL_HYDRA_MPEG_CLK_PHASE_SHIFT_270_DEG ++} MXL_HYDRA_MPEG_CLK_PHASE_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_MPEG_ERR_REPLACE_SYNC = 0, ++ MXL_HYDRA_MPEG_ERR_REPLACE_VALID, ++ MXL_HYDRA_MPEG_ERR_INDICATION_DISABLED ++} MXL_HYDRA_MPEG_ERR_INDICATION_E; ++ ++typedef struct ++{ ++ int enable; // Enable or Disable MPEG OUT ++ MXL_HYDRA_MPEG_CLK_TYPE_E mpegClkType; // Continuous or gapped ++ MXL_HYDRA_MPEG_CLK_FMT_E mpegClkPol; // MPEG Clk polarity ++ u8 maxMpegClkRate; // Max MPEG Clk rate (0 – 104 MHz, 139 MHz) ++ MXL_HYDRA_MPEG_CLK_PHASE_E mpegClkPhase; // MPEG Clk phase ++ MXL_HYDRA_MPEG_DATA_FMT_E lsbOrMsbFirst; // LSB first or MSB first in TS transmission ++ MXL_HYDRA_MPEG_DATA_FMT_E mpegSyncPulseWidth; // MPEG SYNC pulse width (1-bit or 1-byte) ++ MXL_HYDRA_MPEG_CLK_FMT_E mpegValidPol; // MPEG VALID polarity ++ MXL_HYDRA_MPEG_CLK_FMT_E mpegSyncPol; // MPEG SYNC polarity ++ MXL_HYDRA_MPEG_MODE_E mpegMode; // config 4/3/2-wire serial or parallel TS out ++ MXL_HYDRA_MPEG_ERR_INDICATION_E mpegErrorIndication; // Enable or Disable MPEG error indication ++} MXL_HYDRA_MPEGOUT_PARAM_T; ++ ++typedef enum ++{ ++ MXL_HYDRA_EXT_TS_IN_0 = 0, ++ MXL_HYDRA_EXT_TS_IN_1, ++ MXL_HYDRA_EXT_TS_IN_2, ++ MXL_HYDRA_EXT_TS_IN_3, ++ MXL_HYDRA_EXT_TS_IN_MAX ++ ++} MXL_HYDRA_EXT_TS_IN_ID_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_TS_OUT_0 = 0, ++ MXL_HYDRA_TS_OUT_1, ++ MXL_HYDRA_TS_OUT_2, ++ MXL_HYDRA_TS_OUT_3, ++ MXL_HYDRA_TS_OUT_4, ++ MXL_HYDRA_TS_OUT_5, ++ MXL_HYDRA_TS_OUT_6, ++ MXL_HYDRA_TS_OUT_7, ++ MXL_HYDRA_TS_OUT_MAX ++ ++} MXL_HYDRA_TS_OUT_ID_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_TS_DRIVE_STRENGTH_1x = 0, ++ MXL_HYDRA_TS_DRIVE_STRENGTH_2x, ++ MXL_HYDRA_TS_DRIVE_STRENGTH_3x, ++ MXL_HYDRA_TS_DRIVE_STRENGTH_4x, ++ MXL_HYDRA_TS_DRIVE_STRENGTH_5x, ++ MXL_HYDRA_TS_DRIVE_STRENGTH_6x, ++ MXL_HYDRA_TS_DRIVE_STRENGTH_7x, ++ MXL_HYDRA_TS_DRIVE_STRENGTH_8x ++ ++} MXL_HYDRA_TS_DRIVE_STRENGTH_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_DEVICE_581 = 0, ++ MXL_HYDRA_DEVICE_584, ++ MXL_HYDRA_DEVICE_585, ++ MXL_HYDRA_DEVICE_544, ++ MXL_HYDRA_DEVICE_561, ++ MXL_HYDRA_DEVICE_TEST, ++ MXL_HYDRA_DEVICE_582, ++ MXL_HYDRA_DEVICE_541, ++ MXL_HYDRA_DEVICE_568, ++ MXL_HYDRA_DEVICE_542, ++ MXL_HYDRA_DEVICE_541S, ++ MXL_HYDRA_DEVICE_561S, ++ MXL_HYDRA_DEVICE_581S, ++ MXL_HYDRA_DEVICE_MAX ++} MXL_HYDRA_DEVICE_E; ++ ++ ++// Demod IQ data ++typedef struct ++{ ++ u32 demodId; ++ u32 sourceOfIQ; // ==0, it means I/Q comes from Formatter ++ // ==1, Legacy FEC ++ // ==2, Frequency Recovery ++ // ==3, NBC ++ // ==4, CTL ++ // ==5, EQ ++ // ==6, FPGA ++} MXL_HYDRA_DEMOD_IQ_SRC_T; ++ ++typedef struct ++{ ++ u32 demodId; ++} MXL_HYDRA_DEMOD_ABORT_TUNE_T; ++ ++typedef struct ++{ ++ u8 tunerId; ++ u8 enable; ++} MxL_HYDRA_TUNER_CMD; ++ ++// Demod Para for Channel Tune ++typedef struct ++{ ++ u32 tunerIndex; ++ u32 demodIndex; ++ u32 frequencyInHz; // Frequency ++ u32 standard; // one of MXL_HYDRA_BCAST_STD_E ++ u32 spectrumInversion; // Input : Spectrum inversion. ++ u32 rollOff; /* rollOff (alpha) factor */ ++ u32 symbolRateInHz; /* Symbol rate */ ++ u32 pilots; /* TRUE = pilots enabled */ ++ u32 modulationScheme; // Input : Modulation Scheme is one of MXL_HYDRA_MODULATION_E ++ u32 fecCodeRate; // Input : Forward error correction rate. Is one of MXL_HYDRA_FEC_E ++ u32 maxCarrierOffsetInMHz; // Maximum carrier freq offset in MHz. Same as freqSearchRangeKHz, but in unit of MHz. ++} MXL_HYDRA_DEMOD_PARAM_T; ++ ++typedef struct ++{ ++ u32 demodIndex; ++ u8 scrambleSequence[12]; // scramble sequence ++ u32 scrambleCode; // scramble gold code ++} MXL_HYDRA_DEMOD_SCRAMBLE_CODE_T; ++ ++typedef struct ++{ ++ u32 intrType; ++ u32 intrDurationInNanoSecs; ++ u32 intrMask; ++} MXL_INTR_CFG_T; ++ ++typedef struct ++{ ++ u8 powerMode; // enumeration values are defined in MXL_HYDRA_PWR_MODE_E (device API.h) ++} MxL_HYDRA_POWER_MODE_CMD; ++ ++ ++typedef struct ++{ ++ u32 timeIntervalInSeconds; // in seconds ++ u32 tunerIndex; ++ s32 rssiThreshold; ++ ++} MXL_HYDRA_RF_WAKEUP_PARAM_T; ++ ++typedef struct ++{ ++ u32 tunerCount; ++ MXL_HYDRA_RF_WAKEUP_PARAM_T params; ++} MXL_HYDRA_RF_WAKEUP_CFG_T; ++ ++ ++typedef enum ++{ ++ MXL_HYDRA_AUX_CTRL_MODE_FSK = 0, // Select FSK controller ++ MXL_HYDRA_AUX_CTRL_MODE_DISEQC, // Select DiSEqC controller ++} MXL_HYDRA_AUX_CTRL_MODE_E; ++ ++ ++typedef enum ++{ ++ MXL_HYDRA_DISEQC_ENVELOPE_MODE = 0, ++ MXL_HYDRA_DISEQC_TONE_MODE, ++} MXL_HYDRA_DISEQC_OPMODE_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_DISEQC_1_X = 0, // Config DiSEqC 1.x mode ++ MXL_HYDRA_DISEQC_2_X, // Config DiSEqC 2.x mode ++ MXL_HYDRA_DISEQC_DISABLE // Disable DiSEqC ++} MXL_HYDRA_DISEQC_VER_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_DISEQC_CARRIER_FREQ_22KHZ= 0, // DiSEqC signal frequency of 22 KHz ++ MXL_HYDRA_DISEQC_CARRIER_FREQ_33KHZ, // DiSEqC signal frequency of 33 KHz ++ MXL_HYDRA_DISEQC_CARRIER_FREQ_44KHZ // DiSEqC signal frequency of 44 KHz ++} MXL_HYDRA_DISEQC_CARRIER_FREQ_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_DISEQC_ID_0 = 0, ++ MXL_HYDRA_DISEQC_ID_1, ++ MXL_HYDRA_DISEQC_ID_2, ++ MXL_HYDRA_DISEQC_ID_3 ++} MXL_HYDRA_DISEQC_ID_E; ++ ++typedef enum ++{ ++ MXL_HYDRA_FSK_CFG_TYPE_39KPBS = 0, // 39.0kbps ++ MXL_HYDRA_FSK_CFG_TYPE_39_017KPBS, // 39.017kbps ++ MXL_HYDRA_FSK_CFG_TYPE_115_2KPBS // 115.2kbps ++} MXL_HYDRA_FSK_OP_MODE_E; ++ ++ ++typedef struct ++{ ++ u32 diseqcId; // DSQ 0, 1, 2 or 3 ++ u32 opMode; // Envelope mode (0) or internal tone mode (1) ++ u32 version; // 0: 1.0 , 1: 1.1 , 2: Disable ++ u32 centerFreq; // 0: 22KHz, 1: 33KHz and 2: 44 KHz ++}MXL58x_DSQ_OP_MODE_T; ++ ++typedef struct ++{ ++ u32 diseqcId; ++ u32 contToneFlag; // 1: Enable , 0: Disable ++} MXL_HYDRA_DISEQC_CFG_CONT_TONE_T; +diff --git a/drivers/media/dvb-frontends/mxl5xx_regs.h b/drivers/media/dvb-frontends/mxl5xx_regs.h +new file mode 100644 +index 0000000..e983d0b +--- /dev/null ++++ b/drivers/media/dvb-frontends/mxl5xx_regs.h +@@ -0,0 +1,941 @@ ++/* ++* Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved ++* ++* License type: GPLv2 ++* ++* This program is free software; you can redistribute it and/or modify it under ++* the terms of the GNU General Public License as published by the Free Software ++* Foundation. ++* ++* This program is distributed in the hope that it will be useful, but WITHOUT ++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS ++* FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. ++* ++* You should have received a copy of the GNU General Public License along with ++* this program; if not, write to the Free Software Foundation, Inc., ++* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA ++* ++* This program may alternatively be licensed under a proprietary license from ++* MaxLinear, Inc. ++* ++* See terms and conditions defined in file 'LICENSE.txt', which is part of this ++* source code package. ++*/ ++ ++#ifndef __MXL58X_REGISTERS_H__ ++#define __MXL58X_REGISTERS_H__ ++ ++#ifdef __cplusplus ++extern "C" { +#endif + ++#define HYDRA_INTR_STATUS_REG 0x80030008 ++#define HYDRA_INTR_MASK_REG 0x8003000C ++ ++#define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 // 0 - 24 MHz & 1 - 27 MHz ++#define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 // 0 - 24 MHz & 1 - 27 MHz ++ ++#define HYDRA_CPU_RESET_REG 0x8003003C ++#define HYDRA_CPU_RESET_DATA 0x00000400 ++ ++#define HYDRA_RESET_TRANSPORT_FIFO_REG 0x80030028 ++#define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x00000000 ++ ++#define HYDRA_RESET_BBAND_REG 0x80030024 ++#define HYDRA_RESET_BBAND_DATA 0x00000000 ++ ++#define HYDRA_RESET_XBAR_REG 0x80030020 ++#define HYDRA_RESET_XBAR_DATA 0x00000000 ++ ++#define HYDRA_MODULES_CLK_1_REG 0x80030014 ++#define HYDRA_DISABLE_CLK_1 0x00000000 ++ ++#define HYDRA_MODULES_CLK_2_REG 0x8003001C ++#define HYDRA_DISABLE_CLK_2 0x0000000B ++ ++#define HYDRA_PRCM_ROOT_CLK_REG 0x80030018 ++#define HYDRA_PRCM_ROOT_CLK_DISABLE 0x00000000 ++ ++#define HYDRA_CPU_RESET_CHECK_REG 0x80030008 ++#define HYDRA_CPU_RESET_CHECK_OFFSET 0x40000000 // ++ ++#define HYDRA_SKU_ID_REG 0x90000190 ++ ++#define FW_DL_SIGN_ADDR 0x3FFFEAE0 ++ ++// Register to check if FW is running or not ++#define HYDRA_HEAR_BEAT 0x3FFFEDDC ++ ++// Firmware version ++#define HYDRA_FIRMWARE_VERSION 0x3FFFEDB8 ++#define HYDRA_FW_RC_VERSION 0x3FFFCFAC ++ ++// Firmware patch version ++#define HYDRA_FIRMWARE_PATCH_VERSION 0x3FFFEDC2 ++ ++// SOC operating temperature in C ++#define HYDRA_TEMPARATURE 0x3FFFEDB4 ++ ++// Demod & Tuner status registers ++// Demod 0 status base address ++#define HYDRA_DEMOD_0_BASE_ADDR 0x3FFFC64C ++ ++// Tuner 0 status base address ++#define HYDRA_TUNER_0_BASE_ADDR 0x3FFFCE4C ++ ++#define POWER_FROM_ADCRSSI_READBACK 0x3FFFEB6C ++ ++// Macros to determine base address of respective demod or tuner ++#define HYDRA_DMD_STATUS_OFFSET(demodID) ((demodID) * 0x100) ++#define HYDRA_TUNER_STATUS_OFFSET(tunerID) ((tunerID) * 0x40) ++ ++// Demod status address offset from respective demod's base address ++#define HYDRA_DMD_AGC_DIG_LEVEL_ADDR_OFFSET 0x3FFFC64C ++#define HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET 0x3FFFC650 ++#define HYDRA_DMD_ACQ_STATUS_ADDR_OFFSET 0x3FFFC654 ++ ++#define HYDRA_DMD_STANDARD_ADDR_OFFSET 0x3FFFC658 ++#define HYDRA_DMD_SPECTRUM_INVERSION_ADDR_OFFSET 0x3FFFC65C ++#define HYDRA_DMD_SPECTRUM_ROLL_OFF_ADDR_OFFSET 0x3FFFC660 ++#define HYDRA_DMD_SYMBOL_RATE_ADDR_OFFSET 0x3FFFC664 ++#define HYDRA_DMD_MODULATION_SCHEME_ADDR_OFFSET 0x3FFFC668 ++#define HYDRA_DMD_FEC_CODE_RATE_ADDR_OFFSET 0x3FFFC66C ++ ++#define HYDRA_DMD_SNR_ADDR_OFFSET 0x3FFFC670 ++#define HYDRA_DMD_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC674 ++#define HYDRA_DMD_CTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC678 ++#define HYDRA_DMD_STR_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC67C ++#define HYDRA_DMD_FTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC680 ++#define HYDRA_DMD_STR_NBC_SYNC_LOCK_ADDR_OFFSET 0x3FFFC684 ++#define HYDRA_DMD_CYCLE_SLIP_COUNT_ADDR_OFFSET 0x3FFFC688 ++ ++#define HYDRA_DMD_DISPLAY_I_ADDR_OFFSET 0x3FFFC68C ++#define HYDRA_DMD_DISPLAY_Q_ADDR_OFFSET 0x3FFFC68E ++ ++#define HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET 0x3FFFC690 ++#define HYDRA_DMD_DVBS2_PER_COUNT_ADDR_OFFSET 0x3FFFC694 ++#define HYDRA_DMD_DVBS2_PER_WINDOW_ADDR_OFFSET 0x3FFFC698 ++ ++#define HYDRA_DMD_DVBS_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC69C ++#define HYDRA_DMD_DVBS_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6A0 ++#define HYDRA_DMD_DVBS_BER_COUNT_ADDR_OFFSET 0x3FFFC6A4 ++#define HYDRA_DMD_DVBS_BER_WINDOW_ADDR_OFFSET 0x3FFFC6A8 ++ ++// Debug-purpose DVB-S DMD 0 ++#define HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6C8 // corrected RS Errors: 1st iteration ++#define HYDRA_DMD_DVBS_1ST_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6CC // uncorrected RS Errors: 1st iteration ++#define HYDRA_DMD_DVBS_BER_COUNT_1ST_ADDR_OFFSET 0x3FFFC6D0 ++#define HYDRA_DMD_DVBS_BER_WINDOW_1ST_ADDR_OFFSET 0x3FFFC6D4 ++ ++#define HYDRA_DMD_TUNER_ID_ADDR_OFFSET 0x3FFFC6AC ++#define HYDRA_DMD_DVBS2_PILOT_ON_OFF_ADDR_OFFSET 0x3FFFC6B0 ++#define HYDRA_DMD_FREQ_SEARCH_RANGE_KHZ_ADDR_OFFSET 0x3FFFC6B4 ++#define HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET 0x3FFFC6B8 ++#define HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR 0x3FFFC704 ++#define HYDRA_DMD_STATUS_INPUT_POWER_ADDR 0x3FFFC708 ++ ++// DVB-S new scaled_BER_count for a new BER API, see HYDRA-1343 "DVB-S post viterbi information" ++#define DMD0_STATUS_DVBS_1ST_SCALED_BER_COUNT_ADDR 0x3FFFC710 // DMD 0: 1st iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR ++#define DMD0_STATUS_DVBS_SCALED_BER_COUNT_ADDR 0x3FFFC714 // DMD 0: 2nd iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR ++ ++#define DMD0_SPECTRUM_MIN_GAIN_STATUS 0x3FFFC73C ++#define DMD0_SPECTRUM_MIN_GAIN_WB_SAGC_VALUE 0x3FFFC740 ++#define DMD0_SPECTRUM_ MIN_GAIN_NB_SAGC_VALUE 0x3FFFC744 ++ ++#define HYDRA_DMD_STATUS_END_ADDR_OFFSET 0x3FFFC748 ++ ++// Tuner status address offset from respective tuners's base address ++#define HYDRA_TUNER_DEMOD_ID_ADDR_OFFSET 0x3FFFCE4C ++#define HYDRA_TUNER_AGC_LOCK_OFFSET 0x3FFFCE50 ++#define HYDRA_TUNER_SPECTRUM_STATUS_OFFSET 0x3FFFCE54 ++#define HYDRA_TUNER_SPECTRUM_BIN_SIZE_OFFSET 0x3FFFCE58 ++#define HYDRA_TUNER_SPECTRUM_ADDRESS_OFFSET 0x3FFFCE5C ++#define HYDRA_TUNER_ENABLE_COMPLETE 0x3FFFEB78 ++ ++#define HYDRA_DEMOD_STATUS_LOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_YES) ++#define HYDRA_DEMOD_STATUS_UNLOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_NO) ++ ++#define HYDRA_TUNER_STATUS_LOCK(devId,tunerId) MxLWare_HYDRA_WriteRegister(devId,(HYDRA_TUNER_STATUS_LOCK_ADDR_OFFSET + HYDRA_TUNER_STATUS_OFFSET(tunerId)), MXL_YES) ++#define HYDRA_TUNER_STATUS_UNLOCK(devId,tunerId) MxLWare_HYDRA_WriteRegister(devId,(HYDRA_TUNER_STATUS_LOCK_ADDR_OFFSET + HYDRA_TUNER_STATUS_OFFSET(tunerId)), MXL_NO) ++ ++#define HYDRA_VERSION 0x3FFFEDB8 ++#define HYDRA_DEMOD0_VERSION 0x3FFFEDBC ++#define HYDRA_DEMOD1_VERSION 0x3FFFEDC0 ++#define HYDRA_DEMOD2_VERSION 0x3FFFEDC4 ++#define HYDRA_DEMOD3_VERSION 0x3FFFEDC8 ++#define HYDRA_DEMOD4_VERSION 0x3FFFEDCC ++#define HYDRA_DEMOD5_VERSION 0x3FFFEDD0 ++#define HYDRA_DEMOD6_VERSION 0x3FFFEDD4 ++#define HYDRA_DEMOD7_VERSION 0x3FFFEDD8 ++#define HYDRA_HEAR_BEAT 0x3FFFEDDC ++#define HYDRA_SKU_MGMT 0x3FFFEBC0 ++ ++#define MXL_HYDRA_FPGA_A_ADDRESS 0x91C00000 ++#define MXL_HYDRA_FPGA_B_ADDRESS 0x91D00000 ++ ++// TS control base address ++#define HYDRA_TS_CTRL_BASE_ADDR 0x90700000 ++ ++#define MPEG_MUX_MODE_SLICE0_REG HYDRA_TS_CTRL_BASE_ADDR + 0x08 ++#define MPEG_MUX_MODE_SLICE0_OFFSET (0),(2) ++ ++#define MPEG_MUX_MODE_SLICE1_REG HYDRA_TS_CTRL_BASE_ADDR + 0x08 ++#define MPEG_MUX_MODE_SLICE1_OFFSET (2),(2) ++ ++#define PID_BANK_SEL_SLICE0_REG HYDRA_TS_CTRL_BASE_ADDR + 0x190 ++#define PID_BANK_SEL_SLICE1_REG HYDRA_TS_CTRL_BASE_ADDR + 0x1B0 ++ ++#define SW_REGULAR_PID_SW_BANK_OFFSET 0,1 ++#define SW_FIXED_PID_SW_BANK_OFFSET 1,1 ++ ++#define HW_REGULAR_PID_BANK_OFFSET 8,4 ++#define HW_FIXED_PID_BANK_OFFSET 4,4 ++ ++#define MPEG_CLK_GATED_REG HYDRA_TS_CTRL_BASE_ADDR + 0x20 ++#define MPEG_CLK_GATED_OFFSET 0,1 ++ ++#define MPEG_CLK_ALWAYS_ON_REG HYDRA_TS_CTRL_BASE_ADDR + 0x1D4 ++#define MPEG_CLK_ALWAYS_ON_OFFSET 0,1 ++ ++#define HYDRA_REGULAR_PID_BANK_A_REG HYDRA_TS_CTRL_BASE_ADDR + 0x190 ++#define HYDRA_REGULAR_PID_BAN K_A_OFFSET 0,1 ++ ++#define HYDRA_FIXED_PID_BANK_A_REG HYDRA_TS_CTRL_BASE_ADDR + 0x190 ++#define HYDRA_FIXED_PID_BANK_A_OFFSET 1,1 ++ ++#define HYDRA_REGULAR_PID_BANK_B_REG HYDRA_TS_CTRL_BASE_ADDR + 0x1B0 ++#define HYDRA_REGULAR_PID_BANK_B_OFFSET 0,1 ++ ++#define HYDRA_FIXED_PID_BANK_B_REG HYDRA_TS_CTRL_BASE_ADDR + 0x1B0 ++#define HYDRA_FIXED_PID_BANK_B_OFFSET 1,1 ++ ++#define FIXED_PID_TBL_REG_ADDRESS_0 HYDRA_TS_CTRL_BASE_ADDR + 0x9000 ++#define FIXED_PID_TBL_REG_ADDRESS_1 HYDRA_TS_CTRL_BASE_ADDR + 0x9100 ++#define FIXED_PID_TBL_REG_ADDRESS_2 HYDRA_TS_CTRL_BASE_ADDR + 0x9200 ++#define FIXED_PID_TBL_REG_ADDRESS_3 HYDRA_TS_CTRL_BASE_ADDR + 0x9300 ++ ++#define FIXED_PID_TBL_REG_ADDRESS_4 HYDRA_TS_CTRL_BASE_ADDR + 0xB000 ++#define FIXED_PID_TBL_REG_ADDRESS_5 HYDRA_TS_CTRL_BASE_ADDR + 0xB100 ++#define FIXED_PID_TBL_REG_ADDRESS_6 HYDRA_TS_CTRL_BASE_ADDR + 0xB200 ++#define FIXED_PID_TBL_REG_ADDRESS_7 HYDRA_TS_CTRL_BASE_ADDR + 0xB300 ++ ++#define REGULAR_PID_TBL_REG_ADDRESS_0 HYDRA_TS_CTRL_BASE_ADDR + 0x8000 ++#define REGULAR_PID_TBL_REG_ADDRESS_1 HYDRA_TS_CTRL_BASE_ADDR + 0x8200 ++#define REGULAR_PID_TBL_REG_ADDRESS_2 HYDRA_TS_CTRL_BASE_ADDR + 0x8400 ++#define REGULAR_PID_TBL_REG_ADDRESS_3 HYDRA_TS_CTRL_BASE_ADDR + 0x8600 ++ ++#define REGULAR_PID_TBL_REG_ADDRESS_4 HYDRA_TS_CTRL_BASE_ADDR + 0xA000 ++#define REGULAR_PID_TBL_REG_ADDRESS_5 HYDRA_TS_CTRL_BASE_ADDR + 0xA200 ++#define REGULAR_PID_TBL_REG_ADDRESS_6 HYDRA_TS_CTRL_BASE_ADDR + 0xA400 ++#define REGULAR_PID_TBL_REG_ADDRESS_7 HYDRA_TS_CTRL_BASE_ADDR + 0xA600 ++ ++#define PID_VALID_OFFSET 0,1 ++#define PID_DROP_OFFSET 1,1 ++#define PID_REMAP_ENABLE_OFFSET 2,1 ++#define PID_VALUE_OFFSET 4,13 ++#define PID_MASK_OFFSET 19,13 ++ ++#define REGULAR_PID_REMAP_VALUE_OFFSET 0,13 ++#define FIXED_PID_REMAP_VALUE_OFFSET 0,16 ++#define PID_DEMODID_OFFSET 16,3 ++ ++ ++/////////////////////////////////////////////// ++ ++#if 0 ++#define AFE_REG_D2A_TA_ADC_CLK_OUT_FLIP 0x90200004,12,1 ++#define AFE_REG_D2A_TA_RFFE_LNACAPLOAD_1P8 0x90200028,24,4 ++#define AFE_REG_D2A_TA_RFFE_RF1_EN_1P8 0x90200028,5,1 ++#define AFE_REG_D2A_TA_RFFE_SPARE_1P8 0x90200028,8,8 ++#define AFE_REG_D2A_TB_ADC_CLK_OUT_FLIP 0x9020000C,23,1 ++#define AFE_REG_D2A_TB_RFFE_LNACAPLOAD_1P8 0x90200030,16,4 ++#define AFE_REG_D2A_TB_RFFE_RF1_EN_1P8 0x9020002C,21,1 ++#define AFE_REG_D2A_TB_RFFE_SPARE_1P8 0x90200030,0,8 ++#define AFE_REG_D2A_TC_ADC_CLK_OUT_FLIP 0x90200018,7,1 ++#define AFE_REG_D2A_TC_RFFE_LNACAPLOAD_1P8 0x90200038,2,4 ++#define AFE_REG_D2A_TC_RFFE_RF1_EN_1P8 0x90200034,14,1 ++#define AFE_REG_D2A_TC_RFFE_SPARE_1P8 0x90200034,17,8 ++#define AFE_REG_D2A_TD_ADC_CLK_OUT_FLIP 0x90200020,18,1 ++#define AFE_REG_D2A_TD_RFFE_LNACAPLOAD_1P8 0x9020003C,17,4 ++#define AFE_REG_D2A_TD_RFFE_RF1_EN_1P8 0x90200038,29,1 ++#define AFE_REG_D2A_TD_RFFE_SPARE_1P8 0x9020003C,1,8 +#endif ++#define AFE_REG_D2A_XTAL_EN_CLKOUT_1P8 0x90200054,23,1 ++ ++#define PAD_MUX_TS0_IN_CLK_PINMUX_SEL 0x90000018,0,3 ++#define PAD_MUX_TS0_IN_DATA_PINMUX_SEL 0x90000018,4,3 ++#define PAD_MUX_TS1_IN_CLK_PINMUX_SEL 0x90000018,8,3 ++#define PAD_MUX_TS1_IN_DATA_PINMUX_SEL 0x90000018,12,3 ++#define PAD_MUX_TS2_IN_CLK_PINMUX_SEL 0x90000018,16,3 ++#define PAD_MUX_TS2_IN_DATA_PINMUX_SEL 0x90000018,20,3 ++#define PAD_MUX_TS3_IN_CLK_PINMUX_SEL 0x90000018,24,3 ++#define PAD_MUX_TS3_IN_DATA_PINMUX_SEL 0x90000018,28,3 ++ ++#define PAD_MUX_GPIO_00_SYNC_BASEADDR 0x90000188 ++#define PAD_MUX_GPIO_01_SYNC_IN PAD_MUX_GPIO_00_SYNC_BASEADDR,1,1 ++ ++#define PRCM_AFE_SOC_ID 0x80030004,24,8 ++ ++#define PAD_MUX_UART_RX_C_PINMUX_BASEADDR 0x9000001C ++#define PAD_MUX_UART_RX_C_PINMUX_SEL PAD_MUX_UART_RX_C_PINMUX_BASEADDR,0,3 ++#define PAD_MUX_UART_RX_D_PINMUX_SEL PAD_MUX_UART_RX_C_PINMUX_BASEADDR,4,3 ++#define PAD_MUX_BOND_OPTION 0x90000190,0,3 ++#define PAD_MUX_DIGIO_01_PINMUX_SEL 0x9000016C,4,3 ++#define PAD_MUX_DIGIO_02_PINMUX_SEL 0x9000016C,8,3 ++#define PAD_MUX_DIGIO_03_PINMUX_SEL 0x9000016C,12,3 ++#define PAD_MUX_DIGIO_04_PINMUX_SEL 0x9000016C,16,3 ++#define PAD_MUX_DIGIO_05_PINMUX_SEL 0x9000016C,20,3 ++#define PAD_MUX_DIGIO_06_PINMUX_SEL 0x9000016C,24,3 ++#define PAD_MUX_DIGIO_07_PINMUX_SEL 0x9000016C,28,3 ++#define PAD_MUX_DIGIO_08_PINMUX_SEL 0x90000170,0,3 ++#define PAD_MUX_DIGIO_09_PINMUX_SEL 0x90000170,4,3 ++#define PAD_MUX_DIGIO_10_PINMUX_SEL 0x90000170,8,3 ++#define PAD_MUX_DIGIO_11_PINMUX_SEL 0x90000170,12,3 ++#define PAD_MUX_DIGIO_12_PINMUX_SEL 0x90000170,16,3 ++#define PAD_MUX_DIGIO_13_PINMUX_SEL 0x90000170,20,3 ++#define PAD_MUX_DIGIO_14_PINMUX_SEL 0x90000170,24,3 ++#define PAD_MUX_DIGIO_15_PINMUX_SEL 0x90000170,28,3 ++#define PAD_MUX_DIGIO_16_PINMUX_SEL 0x90000174,0,3 ++#define PAD_MUX_DIGIO_17_PINMUX_SEL 0x90000174,4,3 ++#define PAD_MUX_DIGIO_18_PINMUX_SEL 0x90000174,8,3 ++#define PAD_MUX_DIGIO_19_PINMUX_SEL 0x90000174,12,3 ++#define PAD_MUX_DIGIO_20_PINMUX_SEL 0x90000174,16,3 ++#define PAD_MUX_DIGIO_21_PINMUX_SEL 0x90000174,20,3 ++#define PAD_MUX_DIGIO_22_PINMUX_SEL 0x90000174,24,3 ++#define PAD_MUX_DIGIO_23_PINMUX_SEL 0x90000174,28,3 ++#define PAD_MUX_DIGIO_24_PINMUX_SEL 0x90000178,0,3 ++#define PAD_MUX_DIGIO_25_PINMUX_SEL 0x90000178,4,3 ++#define PAD_MUX_DIGIO_26_PINMUX_SEL 0x90000178,8,3 ++#define PAD_MUX_DIGIO_27_PINMUX_SEL 0x90000178,12,3 ++#define PAD_MUX_DIGIO_28_PINMUX_SEL 0x90000178,16,3 ++#define PAD_MUX_DIGIO_29_PINMUX_SEL 0x90000178,20,3 ++#define PAD_MUX_DIGIO_30_PINMUX_SEL 0x90000178,24,3 ++#define PAD_MUX_DIGIO_31_PINMUX_SEL 0x90000178,28,3 ++#define PAD_MUX_DIGIO_32_PINMUX_SEL 0x9000017C,0,3 ++#define PAD_MUX_DIGIO_33_PINMUX_SEL 0x9000017C,4,3 ++#define PAD_MUX_DIGIO_34_PINMUX_SEL 0x9000017C,8,3 ++#define PAD_MUX_EJTAG_TCK_PINMUX_SEL 0x90000020,0,3 ++#define PAD_MUX_EJTAG_TDI_PINMUX_SEL 0x90000020,8,3 ++#define PAD_MUX_EJTAG_TMS_PINMUX_SEL 0x90000020,4,3 ++#define PAD_MUX_EJTAG_TRSTN_PINMUX_SEL 0x90000020,12,3 ++#define PAD_MUX_PAD_DRV_DIGIO_00 0x90000194,0,3 ++#define PAD_MUX_PAD_DRV_DIGIO_05 0x90000194,20,3 ++#define PAD_MUX_PAD_DRV_DIGIO_06 0x90000194,24,3 ++#define PAD_MUX_PAD_DRV_DIGIO_11 0x90000198,12,3 ++#define PAD_MUX_PAD_DRV_DIGIO_12 0x90000198,16,3 ++#define PAD_MUX_PAD_DRV_DIGIO_13 0x90000198,20,3 ++#define PAD_MUX_PAD_DRV_DIGIO_14 0x90000198,24,3 ++#define PAD_MUX_PAD_DRV_DIGIO_16 0x9000019C,0,3 ++#define PAD_MUX_PAD_DRV_DIGIO_17 0x9000019C,4,3 ++#define PAD_MUX_PAD_DRV_DIGIO_18 0x9000019C,8,3 ++#define PAD_MUX_PAD_DRV_DIGIO_22 0x9000019C,24,3 ++#define PAD_MUX_PAD_DRV_DIGIO_23 0x9000019C,28,3 ++#define PAD_MUX_PAD_DRV_DIGIO_24 0x900001A0,0,3 ++#define PAD_MUX_PAD_DRV_DIGIO_25 0x900001A0,4,3 ++#define PAD_MUX_PAD_DRV_DIGIO_29 0x900001A0,20,3 ++#define PAD_MUX_PAD_DRV_DIGIO_30 0x900001A0,24,3 ++#define PAD_MUX_PAD_DRV_DIGIO_31 0x900001A0,28,3 ++#define PRCM_AFE_REG_CLOCK_ENABLE 0x80030014,9,1 ++#define PRCM_CHIP_VERSION 0x80030000,12,4 ++#define PRCM_AFE_CHIP_MMSK_VER 0x80030004,8,8 ++#define PRCM_PRCM_AFE_REG_SOFT_RST_N 0x8003003C,12,1 ++#define PRCM_PRCM_CPU_SOFT_RST_N 0x8003003C,0,1 ++#define PRCM_PRCM_DIGRF_APB_DATA_BB0 0x80030074,0,20 ++#define PRCM_PRCM_DIGRF_APB_DATA_BB1 0x80030078,0,20 ++#define PRCM_PRCM_DIGRF_APB_DATA_BB2 0x8003007C,0,20 ++#define PRCM_PRCM_DIGRF_APB_DATA_BB3 0x80030080,0,20 ++#define PRCM_PRCM_DIGRF_APB_DATA_BB4 0x80030084,0,20 ++#define PRCM_PRCM_DIGRF_APB_DATA_BB5 0x80030088,0,20 ++#define PRCM_PRCM_DIGRF_APB_DATA_BB6 0x8003008C,0,20 ++#define PRCM_PRCM_DIGRF_APB_DATA_BB7 0x80030090,0,20 ++#define PRCM_PRCM_DIGRF_CAPT_DONE 0x80030070,24,8 ++#define PRCM_PRCM_DIGRF_START_CAPT 0x80030064,2,1 ++#define PRCM_PRCM_PAD_MUX_SOFT_RST_N 0x8003003C,11,1 ++#define PRCM_PRCM_XPT_PARALLEL_FIFO_RST_N 0x80030028,20,1 ++#define XPT_APPEND_BYTES0 0x90700008,4,2 ++#define XPT_APPEND_BYTES1 0x90700008,6,2 ++#define XPT_CLOCK_POLARITY0 0x90700010,16,1 ++#define XPT_CLOCK_POLARITY1 0x90700010,17,1 ++#define XPT_CLOCK_POLARITY2 0x90700010,18,1 ++#define XPT_CLOCK_POLARITY3 0x90700010,19,1 ++#define XPT_CLOCK_POLARITY4 0x90700010,20,1 ++#define XPT_CLOCK_POLARITY5 0x90700010,21,1 ++#define XPT_CLOCK_POLARITY6 0x90700010,22,1 ++#define XPT_CLOCK_POLARITY7 0x90700010,23,1 ++#define XPT_DSS_DVB_ENCAP_EN0 0x90700000,16,1 ++#define XPT_DSS_DVB_ENCAP_EN1 0x90700000,17,1 ++#define XPT_DSS_DVB_ENCAP_EN2 0x90700000,18,1 ++#define XPT_DSS_DVB_ENCAP_EN3 0x90700000,19,1 ++#define XPT_DSS_DVB_ENCAP_EN4 0x90700000,20,1 ++#define XPT_DSS_DVB_ENCAP_EN5 0x90700000,21,1 ++#define XPT_DSS_DVB_ENCAP_EN6 0x90700000,22,1 ++#define XPT_DSS_DVB_ENCAP_EN7 0x90700000,23,1 ++#define XPT_DVB_MATCH_BYTE 0x9070017C,16,8 ++#define XPT_DVB_PACKET_SIZE0 0x90700180,0,8 ++#define XPT_DVB_PACKET_SIZE1 0x90700180,8,8 ++#define XPT_DVB_PACKET_SIZE2 0x90700180,16,8 ++#define XPT_DVB_PACKET_SIZE3 0x90700180,24,8 ++#define XPT_ENABLE_DVB_INPUT0 0x90700178,0,1 ++#define XPT_ENABLE_DVB_INPUT1 0x90700178,1,1 ++#define XPT_ENABLE_DVB_INPUT2 0x90700178,2,1 ++#define XPT_ENABLE_DVB_INPUT3 0x90700178,3,1 ++#define XPT_ENABLE_INPUT0 0x90700000,0,1 ++#define XPT_ENABLE_INPUT1 0x90700000,1,1 ++#define XPT_ENABLE_INPUT2 0x90700000,2,1 ++#define XPT_ENABLE_INPUT3 0x90700000,3,1 ++#define XPT_ENABLE_INPUT4 0x90700000,4,1 ++#define XPT_ENABLE_INPUT5 0x90700000,5,1 ++#define XPT_ENABLE_INPUT6 0x90700000,6,1 ++#define XPT_ENABLE_INPUT7 0x90700000,7,1 ++#define XPT_ENABLE_OUTPUT0 0x9070000C,0,1 ++#define XPT_ENABLE_OUTPUT1 0x9070000C,1,1 ++#define XPT_ENABLE_OUTPUT2 0x9070000C,2,1 ++#define XPT_ENABLE_OUTPUT3 0x9070000C,3,1 ++#define XPT_ENABLE_OUTPUT4 0x9070000C,4,1 ++#define XPT_ENABLE_OUTPUT5 0x9070000C,5,1 ++#define XPT_ENABLE_OUTPUT6 0x9070000C,6,1 ++#define XPT_ENABLE_OUTPUT7 0x9070000C,7,1 ++#define XPT_ENABLE_PARALLEL_OUTPUT 0x90700010,27,1 ++#define XPT_ENABLE_PCR_COUNT 0x90700184,1,1 ++#define XPT_ERROR_REPLACE_SYNC0 0x9070000C,24,1 ++#define XPT_ERROR_REPLACE_SYNC1 0x9070000C,25,1 ++#define XPT_ERROR_REPLACE_SYNC2 0x9070000C,26,1 ++#define XPT_ERROR_REPLACE_SYNC3 0x9070000C,27,1 ++#define XPT_ERROR_REPLACE_SYNC4 0x9070000C,28,1 ++#define XPT_ERROR_REPLACE_SYNC5 0x9070000C,29,1 ++#define XPT_ERROR_REPLACE_SYNC6 0x9070000C,30,1 ++#define XPT_ERROR_REPLACE_SYNC7 0x9070000C,31,1 ++#define XPT_ERROR_REPLACE_VALID0 0x90700014,8,1 ++#define XPT_ERROR_REPLACE_VALID1 0x90700014,9,1 ++#define XPT_ERROR_REPLACE_VALID2 0x90700014,10,1 ++#define XPT_ERROR_REPLACE_VALID3 0x90700014,11,1 ++#define XPT_ERROR_REPLACE_VALID4 0x90700014,12,1 ++#define XPT_ERROR_REPLACE_VALID5 0x90700014,13,1 ++#define XPT_ERROR_REPLACE_VALID6 0x90700014,14,1 ++#define XPT_ERROR_REPLACE_VALID7 0x90700014,15,1 ++#define XPT_INP0_MERGE_HDR0 0x90700058,0,32 ++#define XPT_INP0_MERGE_HDR1 0x9070005C,0,32 ++#define XPT_INP0_MERGE_HDR2 0x90700060,0,32 ++#define XPT_INP1_MERGE_HDR0 0x90700064,0,32 ++#define XPT_INP1_MERGE_HDR1 0x90700068,0,32 ++#define XPT_INP1_MERGE_HDR2 0x9070006C,0,32 ++#define XPT_INP2_MERGE_HDR0 0x90700070,0,32 ++#define XPT_INP2_MERGE_HDR1 0x90700074,0,32 ++#define XPT_INP2_MERGE_HDR2 0x90700078,0,32 ++#define XPT_INP3_MERGE_HDR0 0x9070007C,0,32 ++#define XPT_INP3_MERGE_HDR1 0x90700080,0,32 ++#define XPT_INP3_MERGE_HDR2 0x90700084,0,32 ++#define XPT_INP4_MERGE_HDR0 0x90700088,0,32 ++#define XPT_INP4_MERGE_HDR1 0x9070008C,0,32 ++#define XPT_INP4_MERGE_HDR2 0x90700090,0,32 ++#define XPT_INP5_MERGE_HDR0 0x90700094,0,32 ++#define XPT_INP5_MERGE_HDR1 0x90700098,0,32 ++#define XPT_INP5_MERGE_HDR2 0x9070009C,0,32 ++#define XPT_INP6_MERGE_HDR0 0x907000A0,0,32 ++#define XPT_INP6_MERGE_HDR1 0x907000A4,0,32 ++#define XPT_INP6_MERGE_HDR2 0x907000A8,0,32 ++#define XPT_INP7_MERGE_HDR0 0x907000AC,0,32 ++#define XPT_INP7_MERGE_HDR1 0x907000B0,0,32 ++#define XPT_INP7_MERGE_HDR2 0x907000B4,0,32 ++#define XPT_INP_MODE_DSS0 0x90700000,8,1 ++#define XPT_INP_MODE_DSS1 0x90700000,9,1 ++#define XPT_INP_MODE_DSS2 0x90700000,10,1 ++#define XPT_INP_MODE_DSS3 0x90700000,11,1 ++#define XPT_INP_MODE_DSS4 0x90700000,12,1 ++#define XPT_INP_MODE_DSS5 0x90700000,13,1 ++#define XPT_INP_MODE_DSS6 0x90700000,14,1 ++#define XPT_INP_MODE_DSS7 0x90700000,15,1 ++#define XPT_KNOWN_PID_MUX_SELECT0 0x90700190,8,4 ++#define XPT_KNOWN_PID_MUX_SELECT1 0x907001B0,8,4 ++#define XPT_LSB_FIRST0 0x9070000C,16,1 ++#define XPT_LSB_FIRST1 0x9070000C,17,1 ++#define XPT_LSB_FIRST2 0x9070000C,18,1 ++#define XPT_LSB_FIRST3 0x9070000C,19,1 ++#define XPT_LSB_FIRST4 0x9070000C,20,1 ++#define XPT_LSB_FIRST5 0x9070000C,21,1 ++#define XPT_LSB_FIRST6 0x9070000C,22,1 ++#define XPT_LSB_FIRST7 0x9070000C,23,1 ++#define XPT_MODE_27MHZ 0x90700184,0,1 ++#define XPT_NCO_COUNT_MIN 0x90700044,16,8 ++#define XPT_OUTPUT_MODE_DSS0 0x9070000C,8,1 ++#define XPT_OUTPUT_MODE_DSS1 0x9070000C,9,1 ++#define XPT_OUTPUT_MODE_DSS2 0x9070000C,10,1 ++#define XPT_OUTPUT_MODE_DSS3 0x9070000C,11,1 ++#define XPT_OUTPUT_MODE_DSS4 0x9070000C,12,1 ++#define XPT_OUTPUT_MODE_DSS5 0x9070000C,13,1 ++#define XPT_OUTPUT_MODE_DSS6 0x9070000C,14,1 ++#define XPT_OUTPUT_MODE_DSS7 0x9070000C,15,1 ++#define XPT_OUTPUT_MODE_MUXGATING0 0x90700020,0,1 ++#define XPT_OUTPUT_MODE_MUXGATING1 0x90700020,1,1 ++#define XPT_OUTPUT_MODE_MUXGATING2 0x90700020,2,1 ++#define XPT_OUTPUT_MODE_MUXGATING3 0x90700020,3,1 ++#define XPT_OUTPUT_MODE_MUXGATING4 0x90700020,4,1 ++#define XPT_OUTPUT_MODE_MUXGATING5 0x90700020,5,1 ++#define XPT_OUTPUT_MODE_MUXGATING6 0x90700020,6,1 ++#define XPT_OUTPUT_MODE_MUXGATING7 0x90700020,7,1 ++#define XPT_OUTPUT_MUXSELECT0 0x9070001C,0,3 ++#define XPT_OUTPUT_MUXSELECT1 0x9070001C,4,3 ++#define XPT_OUTPUT_MUXSELECT2 0x9070001C,8,3 ++#define XPT_OUTPUT_MUXSELECT3 0x9070001C,12,3 ++#define XPT_OUTPUT_MUXSELECT4 0x9070001C,16,3 ++#define XPT_OUTPUT_MUXSELECT5 0x9070001C,20,3 ++#define XPT_PCR_RTS_CORRECTION_ENABLE 0x90700008,14,1 ++#define XPT_PID_DEFAULT_DROP0 0x90700190,12,1 ++#define XPT_PID_DEFAULT_DROP1 0x90700190,13,1 ++#define XPT_PID_DEFAULT_DROP2 0x90700190,14,1 ++#define XPT_PID_DEFAULT_DROP3 0x90700190,15,1 ++#define XPT_PID_DEFAULT_DROP4 0x907001B0,12,1 ++#define XPT_PID_DEFAULT_DROP5 0x907001B0,13,1 ++#define XPT_PID_DEFAULT_DROP6 0x907001B0,14,1 ++#define XPT_PID_DEFAULT_DROP7 0x907001B0,15,1 ++#define XPT_PID_MUX_SELECT0 0x90700190,4,4 ++#define XPT_PID_MUX_SELECT1 0x907001B0,4,4 ++#define XPT_STREAM_MUXMODE0 0x90700008,0,2 ++#define XPT_STREAM_MUXMODE1 0x90700008,2,2 ++#define XPT_SYNC_FULL_BYTE0 0x90700010,0,1 ++#define XPT_SYNC_FULL_BYTE1 0x90700010,1,1 ++#define XPT_SYNC_FULL_BYTE2 0x90700010,2,1 ++#define XPT_SYNC_FULL_BYTE3 0x90700010,3,1 ++#define XPT_SYNC_FULL_BYTE4 0x90700010,4,1 ++#define XPT_SYNC_FULL_BYTE5 0x90700010,5,1 ++#define XPT_SYNC_FULL_BYTE6 0x90700010,6,1 ++#define XPT_SYNC_FULL_BYTE7 0x90700010,7,1 ++#define XPT_SYNC_LOCK_THRESHOLD 0x9070017C,0,8 ++#define XPT_SYNC_MISS_THRESHOLD 0x9070017C,8,8 ++#define XPT_SYNC_POLARITY0 0x90700010,8,1 ++#define XPT_SYNC_POLARITY1 0x90700010,9,1 ++#define XPT_SYNC_POLARITY2 0x90700010,10,1 ++#define XPT_SYNC_POLARITY3 0x90700010,11,1 ++#define XPT_SYNC_POLARITY4 0x90700010,12,1 ++#define XPT_SYNC_POLARITY5 0x90700010,13,1 ++#define XPT_SYNC_POLARITY6 0x90700010,14,1 ++#define XPT_SYNC_POLARITY7 0x90700010,15,1 ++#define XPT_TS_CLK_OUT_EN0 0x907001D4,0,1 ++#define XPT_TS_CLK_OUT_EN1 0x907001D4,1,1 ++#define XPT_TS_CLK_OUT_EN2 0x907001D4,2,1 ++#define XPT_TS_CLK_OUT_EN3 0x907001D4,3,1 ++#define XPT_TS_CLK_OUT_EN4 0x907001D4,4,1 ++#define XPT_TS_CLK_OUT_EN5 0x907001D4,5,1 ++#define XPT_TS_CLK_OUT_EN6 0x907001D4,6,1 ++#define XPT_TS_CLK_OUT_EN7 0x907001D4,7,1 ++#define XPT_TS_CLK_OUT_EN_PARALLEL 0x907001D4,8,1 ++#define XPT_TS_CLK_PHASE0 0x90700018,0,3 ++#define XPT_TS_CLK_PHASE1 0x90700018,4,3 ++#define XPT_TS_CLK_PHASE2 0x90700018,8,3 ++#define XPT_TS_CLK_PHASE3 0x90700018,12,3 ++#define XPT_TS_CLK_PHASE4 0x90700018,16,3 ++#define XPT_TS_CLK_PHASE5 0x90700018,20,3 ++#define XPT_TS_CLK_PHASE6 0x90700018,24,3 ++#define XPT_TS_CLK_PHASE7 0x90700018,28,3 ++#define XPT_VALID_POLARITY0 0x90700014,0,1 ++#define XPT_VALID_POLARITY1 0x90700014,1,1 ++#define XPT_VALID_POLARITY2 0x90700014,2,1 ++#define XPT_VALID_POLARITY3 0x90700014,3,1 ++#define XPT_VALID_POLARITY4 0x90700014,4,1 ++#define XPT_VALID_POLARITY5 0x90700014,5,1 ++#define XPT_VALID_POLARITY6 0x90700014,6,1 ++#define XPT_VALID_POLARITY7 0x90700014,7,1 ++#define XPT_ZERO_FILL_COUNT 0x90700008,8,6 ++ ++#define XPT_PACKET_GAP_MIN_BASEADDR 0x90700044 ++#define XPT_PACKET_GAP_MIN_TIMER XPT_PACKET_GAP_MIN_BASEADDR,0,16 ++#define XPT_NCO_COUNT_MIN0 XPT_PACKET_GAP_MIN_BASEADDR,16,8 ++#define XPT_NCO_COUNT_BASEADDR 0x90700238 ++#define XPT_NCO_COUNT_MIN1 XPT_NCO_COUNT_BASEADDR,0,8 ++#define XPT_NCO_COUNT_MIN2 XPT_NCO_COUNT_BASEADDR,8,8 ++#define XPT_NCO_COUNT_MIN3 XPT_NCO_COUNT_BASEADDR,16,8 ++#define XPT_NCO_COUNT_MIN4 XPT_NCO_COUNT_BASEADDR,24,8 ++ ++#define XPT_NCO_COUNT_BASEADDR1 0x9070023C ++#define XPT_NCO_COUNT_MIN5 XPT_NCO_COUNT_BASEADDR1,0,8 ++#define XPT_NCO_COUNT_MIN6 XPT_NCO_COUNT_BASEADDR1,8,8 ++#define XPT_NCO_COUNT_MIN7 XPT_NCO_COUNT_BASEADDR1,16,8 ++ ++// V2 DigRF status register ++#define BB0_DIGRF_CAPT_DONE 0x908000CC,0,1 ++#define PRCM_PRCM_CHIP_ID 0x80030000,0,12 ++ ++#define XPT_PID_BASEADDR 0x90708000 ++#define XPT_PID_VALID0 XPT_PID_BASEADDR,0,1 ++#define XPT_PID_DROP0 XPT_PID_BASEADDR,1,1 ++#define XPT_PID_REMAP0 XPT_PID_BASEADDR,2,1 ++#define XPT_PID_VALUE0 XPT_PID_BASEADDR,4,13 ++#define XPT_PID_MASK0 XPT_PID_BASEADDR,19,13 ++ ++#define XPT_PID_REMAP_BASEADDR 0x90708004 ++#define XPT_PID_REMAP_VALUE0 XPT_PID_REMAP_BASEADDR,0,13 ++#define XPT_PID_PORT_ID0 XPT_PID_REMAP_BASEADDR,16,3 ++ ++#define XPT_KNOWN_PID_BASEADDR 0x90709000 ++#define XPT_KNOWN_PID_VALID0 XPT_KNOWN_PID_BASEADDR,0,1 ++#define XPT_KNOWN_PID_DROP0 XPT_KNOWN_PID_BASEADDR,1,1 ++#define XPT_KNOWN_PID_REMAP0 XPT_KNOWN_PID_BASEADDR,2,1 ++#define XPT_KNOWN_PID_REMAP_VALUE0 XPT_KNOWN_PID_BASEADDR,16,13 ++ ++#define XPT_PID_BASEADDR1 0x9070A000 ++#define XPT_PID_VALID1 XPT_PID_BASEADDR1,0,1 ++#define XPT_PID_DROP1 XPT_PID_BASEADDR1,1,1 ++#define XPT_PID_REMAP1 XPT_PID_BASEADDR1,2,1 ++#define XPT_PID_VALUE1 XPT_PID_BASEADDR1,4,13 ++#define XPT_PID_MASK1 XPT_PID_BASEADDR1,19,13 ++ ++#define XPT_PID_REMAP_BASEADDR1 0x9070A004 ++#define XPT_PID_REMAP_VALUE1 XPT_PID_REMAP_BASEADDR1,0,13 ++ ++#define XPT_KNOWN_PID_BASEADDR1 0x9070B000 ++#define XPT_KNOWN_PID_VALID1 XPT_KNOWN_PID_BASEADDR1,0,1 ++#define XPT_KNOWN_PID_DROP1 XPT_KNOWN_PID_BASEADDR1,1,1 ++#define XPT_KNOWN_PID_REMAP1 XPT_KNOWN_PID_BASEADDR1,2,1 ++#define XPT_KNOWN_PID_REMAP_VALUE1 XPT_KNOWN_PID_BASEADDR1,16,13 ++ ++#define XPT_BERT_LOCK_BASEADDR 0x907000B8 ++#define XPT_BERT_LOCK_THRESHOLD XPT_BERT_LOCK_BASEADDR,0,8 ++#define XPT_BERT_LOCK_WINDOW XPT_BERT_LOCK_BASEADDR,8,8 ++ ++#define XPT_BERT_BASEADDR 0x907000BC ++#define XPT_BERT_ENABLE0 XPT_BERT_BASEADDR,0,1 ++#define XPT_BERT_ENABLE1 XPT_BERT_BASEADDR,1,1 ++#define XPT_BERT_ENABLE2 XPT_BERT_BASEADDR,2,1 ++#define XPT_BERT_ENABLE3 XPT_BERT_BASEADDR,3,1 ++#define XPT_BERT_ENABLE4 XPT_BERT_BASEADDR,4,1 ++#define XPT_BERT_ENABLE5 XPT_BERT_BASEADDR,5,1 ++#define XPT_BERT_ENABLE6 XPT_BERT_BASEADDR,6,1 ++#define XPT_BERT_ENABLE7 XPT_BERT_BASEADDR,7,1 ++#define XPT_BERT_SEQUENCE_PN23_0 XPT_BERT_BASEADDR,8,1 ++#define XPT_BERT_SEQUENCE_PN23_1 XPT_BERT_BASEADDR,9,1 ++#define XPT_BERT_SEQUENCE_PN23_2 XPT_BERT_BASEADDR,10,1 ++#define XPT_BERT_SEQUENCE_PN23_3 XPT_BERT_BASEADDR,11,1 ++#define XPT_BERT_SEQUENCE_PN23_4 XPT_BERT_BASEADDR,12,1 ++#define XPT_BERT_SEQUENCE_PN23_5 XPT_BERT_BASEADDR,13,1 ++#define XPT_BERT_SEQUENCE_PN23_6 XPT_BERT_BASEADDR,14,1 ++#define XPT_BERT_SEQUENCE_PN23_7 XPT_BERT_BASEADDR,15,1 ++#define XPT_LOCK_RESYNC0 XPT_BERT_BASEADDR,16,1 ++#define XPT_LOCK_RESYNC1 XPT_BERT_BASEADDR,17,1 ++#define XPT_LOCK_RESYNC2 XPT_BERT_BASEADDR,18,1 ++#define XPT_LOCK_RESYNC3 XPT_BERT_BASEADDR,19,1 ++#define XPT_LOCK_RESYNC4 XPT_BERT_BASEADDR,20,1 ++#define XPT_LOCK_RESYNC5 XPT_BERT_BASEADDR,21,1 ++#define XPT_LOCK_RESYNC6 XPT_BERT_BASEADDR,22,1 ++#define XPT_LOCK_RESYNC7 XPT_BERT_BASEADDR,23,1 ++#define XPT_BERT_DATA_POLARITY0 XPT_BERT_BASEADDR,24,1 ++#define XPT_BERT_DATA_POLARITY1 XPT_BERT_BASEADDR,25,1 ++#define XPT_BERT_DATA_POLARITY2 XPT_BERT_BASEADDR,26,1 ++#define XPT_BERT_DATA_POLARITY3 XPT_BERT_BASEADDR,27,1 ++#define XPT_BERT_DATA_POLARITY4 XPT_BERT_BASEADDR,28,1 ++#define XPT_BERT_DATA_POLARITY5 XPT_BERT_BASEADDR,29,1 ++#define XPT_BERT_DATA_POLARITY6 XPT_BERT_BASEADDR,30,1 ++#define XPT_BERT_DATA_POLARITY7 XPT_BERT_BASEADDR,31,1 ++ ++#define XPT_BERT_INVERT_BASEADDR 0x907000C0 ++#define XPT_BERT_INVERT_DATA0 XPT_BERT_INVERT_BASEADDR,0,1 ++#define XPT_BERT_INVERT_DATA1 XPT_BERT_INVERT_BASEADDR,1,1 ++#define XPT_BERT_INVERT_DATA2 XPT_BERT_INVERT_BASEADDR,2,1 ++#define XPT_BERT_INVERT_DATA3 XPT_BERT_INVERT_BASEADDR,3,1 ++#define XPT_BERT_INVERT_DATA4 XPT_BERT_INVERT_BASEADDR,4,1 ++#define XPT_BERT_INVERT_DATA5 XPT_BERT_INVERT_BASEADDR,5,1 ++#define XPT_BERT_INVERT_DATA6 XPT_BERT_INVERT_BASEADDR,6,1 ++#define XPT_BERT_INVERT_DATA7 XPT_BERT_INVERT_BASEADDR,7,1 ++#define XPT_BERT_INVERT_SEQUENCE0 XPT_BERT_INVERT_BASEADDR,8,1 ++#define XPT_BERT_INVERT_SEQUENCE1 XPT_BERT_INVERT_BASEADDR,9,1 ++#define XPT_BERT_INVERT_SEQUENCE2 XPT_BERT_INVERT_BASEADDR,10,1 ++#define XPT_BERT_INVERT_SEQUENCE3 XPT_BERT_INVERT_BASEADDR,11,1 ++#define XPT_BERT_INVERT_SEQUENCE4 XPT_BERT_INVERT_BASEADDR,12,1 ++#define XPT_BERT_INVERT_SEQUENCE5 XPT_BERT_INVERT_BASEADDR,13,1 ++#define XPT_BERT_INVERT_SEQUENCE6 XPT_BERT_INVERT_BASEADDR,14,1 ++#define XPT_BERT_INVERT_SEQUENCE7 XPT_BERT_INVERT_BASEADDR,15,1 ++#define XPT_BERT_OUTPUT_POLARITY0 XPT_BERT_INVERT_BASEADDR,16,1 ++#define XPT_BERT_OUTPUT_POLARITY1 XPT_BERT_INVERT_BASEADDR,17,1 ++#define XPT_BERT_OUTPUT_POLARITY2 XPT_BERT_INVERT_BASEADDR,18,1 ++#define XPT_BERT_OUTPUT_POLARITY3 XPT_BERT_INVERT_BASEADDR,19,1 ++#define XPT_BERT_OUTPUT_POLARITY4 XPT_BERT_INVERT_BASEADDR,20,1 ++#define XPT_BERT_OUTPUT_POLARITY5 XPT_BERT_INVERT_BASEADDR,21,1 ++#define XPT_BERT_OUTPUT_POLARITY6 XPT_BERT_INVERT_BASEADDR,22,1 ++#define XPT_BERT_OUTPUT_POLARITY7 XPT_BERT_INVERT_BASEADDR,23,1 ++ ++#define XPT_BERT_HEADER_BASEADDR 0x907000C4 ++#define XPT_BERT_HEADER_MODE0 XPT_BERT_HEADER_BASEADDR,0,2 ++#define XPT_BERT_HEADER_MODE1 XPT_BERT_HEADER_BASEADDR,2,2 ++#define XPT_BERT_HEADER_MODE2 XPT_BERT_HEADER_BASEADDR,4,2 ++#define XPT_BERT_HEADER_MODE3 XPT_BERT_HEADER_BASEADDR,6,2 ++#define XPT_BERT_HEADER_MODE4 XPT_BERT_HEADER_BASEADDR,8,2 ++#define XPT_BERT_HEADER_MODE5 XPT_BERT_HEADER_BASEADDR,10,2 ++#define XPT_BERT_HEADER_MODE6 XPT_BERT_HEADER_BASEADDR,12,2 ++#define XPT_BERT_HEADER_MODE7 XPT_BERT_HEADER_BASEADDR,14,2 ++ ++#define XPT_BERT_BASEADDR1 0x907000C8 ++#define XPT_BERT_LOCKED0 XPT_BERT_BASEADDR1,0,1 ++#define XPT_BERT_LOCKED1 XPT_BERT_BASEADDR1,1,1 ++#define XPT_BERT_LOCKED2 XPT_BERT_BASEADDR1,2,1 ++#define XPT_BERT_LOCKED3 XPT_BERT_BASEADDR1,3,1 ++#define XPT_BERT_LOCKED4 XPT_BERT_BASEADDR1,4,1 ++#define XPT_BERT_LOCKED5 XPT_BERT_BASEADDR1,5,1 ++#define XPT_BERT_LOCKED6 XPT_BERT_BASEADDR1,6,1 ++#define XPT_BERT_LOCKED7 XPT_BERT_BASEADDR1,7,1 ++#define XPT_BERT_BIT_COUNT_SAT0 XPT_BERT_BASEADDR1,8,1 ++#define XPT_BERT_BIT_COUNT_SAT1 XPT_BERT_BASEADDR1,9,1 ++#define XPT_BERT_BIT_COUNT_SAT2 XPT_BERT_BASEADDR1,10,1 ++#define XPT_BERT_BIT_COUNT_SAT3 XPT_BERT_BASEADDR1,11,1 ++#define XPT_BERT_BIT_COUNT_SAT4 XPT_BERT_BASEADDR1,12,1 ++#define XPT_BERT_BIT_COUNT_SAT5 XPT_BERT_BASEADDR1,13,1 ++#define XPT_BERT_BIT_COUNT_SAT6 XPT_BERT_BASEADDR1,14,1 ++#define XPT_BERT_BIT_COUNT_SAT7 XPT_BERT_BASEADDR1,15,1 ++ ++#define XPT_BERT_BIT_COUNT0_BASEADDR 0x907000CC ++#define XPT_BERT_BIT_COUNT0_LO XPT_BERT_BIT_COUNT0_BASEADDR,0,32 ++ ++#define XPT_BERT_BIT_COUNT0_BASEADDR1 0x907000D0 ++#define XPT_BERT_BIT_COUNT0_HI XPT_BERT_BIT_COUNT0_BASEADDR1,0,18 ++ ++#define XPT_BERT_BIT_COUNT1_BASEADDR 0x907000D4 ++#define XPT_BERT_BIT_COUNT1_LO XPT_BERT_BIT_COUNT1_BASEADDR,0,32 ++ ++#define XPT_BERT_BIT_COUNT1_BASEADDR1 0x907000D8 ++#define XPT_BERT_BIT_COUNT1_HI XPT_BERT_BIT_COUNT1_BASEADDR1,0,18 ++ ++#define XPT_BERT_BIT_COUNT2_BASEADDR 0x907000DC ++#define XPT_BERT_BIT_COUNT2_LO XPT_BERT_BIT_COUNT2_BASEADDR,0,32 ++ ++#define XPT_BERT_BIT_COUNT2_BASEADDR1 0x907000E0 ++#define XPT_BERT_BIT_COUNT2_HI XPT_BERT_BIT_COUNT2_BASEADDR1,0,18 ++ ++#define XPT_BERT_BIT_COUNT3_BASEADDR 0x907000E4 ++#define XPT_BERT_BIT_COUNT3_LO XPT_BERT_BIT_COUNT3_BASEADDR,0,32 ++ ++#define XPT_BERT_BIT_COUNT3_BASEADDR1 0x907000E8 ++#define XPT_BERT_BIT_COUNT3_HI XPT_BERT_BIT_COUNT3_BASEADDR1,0,18 ++ ++#define XPT_BERT_BIT_COUNT4_BASEADDR 0x907000EC ++#define XPT_BERT_BIT_COUNT4_LO XPT_BERT_BIT_COUNT4_BASEADDR,0,32 ++ ++#define XPT_BERT_BIT_COUNT4_BASEADDR1 0x907000F0 ++#define XPT_BERT_BIT_COUNT4_HI XPT_BERT_BIT_COUNT4_BASEADDR1,0,18 ++ ++#define XPT_BERT_BIT_COUNT5_BASEADDR 0x907000F4 ++#define XPT_BERT_BIT_COUNT5_LO XPT_BERT_BIT_COUNT5_BASEADDR,0,32 ++ ++#define XPT_BERT_BIT_COUNT5_BASEADDR1 0x907000F8 ++#define XPT_BERT_BIT_COUNT5_HI XPT_BERT_BIT_COUNT5_BASEADDR1,0,18 ++ ++#define XPT_BERT_BIT_COUNT6_BASEADDR 0x907000FC ++#define XPT_BERT_BIT_COUNT6_LO XPT_BERT_BIT_COUNT6_BASEADDR,0,32 ++ ++#define XPT_BERT_BIT_COUNT6_BASEADDR1 0x90700100 ++#define XPT_BERT_BIT_COUNT6_HI XPT_BERT_BIT_COUNT6_BASEADDR1,0,18 ++ ++#define XPT_BERT_BIT_COUNT7_BASEADDR 0x90700104 ++#define XPT_BERT_BIT_COUNT7_LO XPT_BERT_BIT_COUNT7_BASEADDR,0,32 ++ ++#define XPT_BERT_BIT_COUNT7_BASEADDR1 0x90700108 ++#define XPT_BERT_BIT_COUNT7_HI XPT_BERT_BIT_COUNT7_BASEADDR1,0,18 ++ ++#define XPT_BERT_ERR_COUNT0_BASEADDR 0x9070010C ++#define XPT_BERT_ERR_COUNT0_LO XPT_BERT_ERR_COUNT0_BASEADDR,0,32 ++ ++#define XPT_BERT_ERR_COUNT0_BASEADDR1 0x90700110 ++#define XPT_BERT_ERR_COUNT0_HI XPT_BERT_ERR_COUNT0_BASEADDR1,0,8 ++ ++#define XPT_BERT_ERR_COUNT1_BASEADDR 0x90700114 ++#define XPT_BERT_ERR_COUNT1_LO XPT_BERT_ERR_COUNT1_BASEADDR,0,32 ++ ++#define XPT_BERT_ERR_COUNT1_BASEADDR1 0x90700118 ++#define XPT_BERT_ERR_COUNT1_HI XPT_BERT_ERR_COUNT1_BASEADDR1,0,8 ++ ++#define XPT_BERT_ERR_COUNT2_BASEADDR 0x9070011C ++#define XPT_BERT_ERR_COUNT2_LO XPT_BERT_ERR_COUNT2_BASEADDR,0,32 ++ ++#define XPT_BERT_ERR_COUNT2_BASEADDR1 0x90700120 ++#define XPT_BERT_ERR_COUNT2_HI XPT_BERT_ERR_COUNT2_BASEADDR1,0,8 ++ ++#define XPT_BERT_ERR_COUNT3_BASEADDR 0x90700124 ++#define XPT_BERT_ERR_COUNT3_LO XPT_BERT_ERR_COUNT3_BASEADDR,0,32 ++ ++#define XPT_BERT_ERR_COUNT3_BASEADDR1 0x90700128 ++#define XPT_BERT_ERR_COUNT3_HI XPT_BERT_ERR_COUNT3_BASEADDR1,0,8 ++ ++#define XPT_BERT_ERR_COUNT4_BASEADDR 0x9070012C ++#define XPT_BERT_ERR_COUNT4_LO XPT_BERT_ERR_COUNT4_BASEADDR,0,32 ++ ++#define XPT_BERT_ERR_COUNT4_BASEADDR1 0x90700130 ++#define XPT_BERT_ERR_COUNT4_HI XPT_BERT_ERR_COUNT4_BASEADDR1,0,8 ++ ++#define XPT_BERT_ERR_COUNT5_BASEADDR 0x90700134 ++#define XPT_BERT_ERR_COUNT5_LO XPT_BERT_ERR_COUNT5_BASEADDR,0,32 ++ ++#define XPT_BERT_ERR_COUNT5_BASEADDR1 0x90700138 ++#define XPT_BERT_ERR_COUNT5_HI XPT_BERT_ERR_COUNT5_BASEADDR1,0,8 ++ ++#define XPT_BERT_ERR_COUNT6_BASEADDR 0x9070013C ++#define XPT_BERT_ERR_COUNT6_LO XPT_BERT_ERR_COUNT6_BASEADDR,0,32 ++ ++#define XPT_BERT_ERR_COUNT6_BASEADDR1 0x90700140 ++#define XPT_BERT_ERR_COUNT6_HI XPT_BERT_ERR_COUNT6_BASEADDR1,0,8 ++ ++#define XPT_BERT_ERR_COUNT7_BASEADDR 0x90700144 ++#define XPT_BERT_ERR_COUNT7_LO XPT_BERT_ERR_COUNT7_BASEADDR,0,32 ++ ++#define XPT_BERT_ERR_COUNT7_BASEADDR1 0x90700148 ++#define XPT_BERT_ERR_COUNT7_HI XPT_BERT_ERR_COUNT7_BASEADDR1,0,8 ++ ++#define XPT_BERT_ERROR_BASEADDR 0x9070014C ++#define XPT_BERT_ERROR_INSERT XPT_BERT_ERROR_BASEADDR,0,24 ++ ++#define XPT_BERT_ANALYZER_BASEADDR 0x90700150 ++#define XPT_BERT_ANALYZER_ENABLE XPT_BERT_ANALYZER_BASEADDR,0,1 ++#define XPT_BERT_ANALYZER_PORT XPT_BERT_ANALYZER_BASEADDR,4,3 ++#define XPT_BERT_ANALYZER_ERR_THRES XPT_BERT_ANALYZER_BASEADDR,15,17 ++ ++#define XPT_BERT_ANALYZER_BASEADDR1 0x90700154 ++#define XPT_BERT_ANALYZER_START XPT_BERT_ANALYZER_BASEADDR1,0,32 ++ ++#define XPT_BERT_ANALYZER_BASEADDR2 0x90700158 ++#define XPT_BERT_ANALYZER_TSTAMP0 XPT_BERT_ANALYZER_BASEADDR2,0,32 ++ ++#define XPT_BERT_ANALYZER_BASEADDR3 0x9070015C ++#define XPT_BERT_ANALYZER_TSTAMP1 XPT_BERT_ANALYZER_BASEADDR3,0,32 ++ ++#define XPT_BERT_ANALYZER_BASEADDR4 0x90700160 ++#define XPT_BERT_ANALYZER_TSTAMP2 XPT_BERT_ANALYZER_BASEADDR4,0,32 ++ ++#define XPT_BERT_ANALYZER_BASEADDR5 0x90700164 ++#define XPT_BERT_ANALYZER_TSTAMP3 XPT_BERT_ANALYZER_BASEADDR5,0,32 ++ ++#define XPT_BERT_ANALYZER_BASEADDR6 0x90700168 ++#define XPT_BERT_ANALYZER_TSTAMP4 XPT_BERT_ANALYZER_BASEADDR6,0,32 ++ ++#define XPT_BERT_ANALYZER_BASEADDR7 0x9070016C ++#define XPT_BERT_ANALYZER_TSTAMP5 XPT_BERT_ANALYZER_BASEADDR7,0,32 ++ ++#define XPT_BERT_ANALYZER_BASEADDR8 0x90700170 ++#define XPT_BERT_ANALYZER_TSTAMP6 XPT_BERT_ANALYZER_BASEADDR8,0,32 ++ ++#define XPT_BERT_ANALYZER_BASEADDR9 0x90700174 ++#define XPT_BERT_ANALYZER_TSTAMP7 XPT_BERT_ANALYZER_BASEADDR9,0,32 ++ ++#define XPT_DMD0_BASEADDR 0x9070024C ++#define XPT_DMD0_SEL XPT_DMD0_BASEADDR,0,3 ++#define XPT_DMD1_SEL XPT_DMD0_BASEADDR,4,3 ++#define XPT_DMD2_SEL XPT_DMD0_BASEADDR,8,3 ++#define XPT_DMD3_SEL XPT_DMD0_BASEADDR,12,3 ++#define XPT_DMD4_SEL XPT_DMD0_BASEADDR,16,3 ++#define XPT_DMD5_SEL XPT_DMD0_BASEADDR,20,3 ++#define XPT_DMD6_SEL XPT_DMD0_BASEADDR,24,3 ++#define XPT_DMD7_SEL XPT_DMD0_BASEADDR,28,3 ++ ++// V2 AGC Gain Freeze & step ++#define DBG_ENABLE_DISABLE_AGC (0x3FFFCF60) // 1: DISABLE, 0:ENABLE ++#define WB_DFE0_DFE_FB_RF1_BASEADDR 0x903004A4 ++#define WB_DFE0_DFE_FB_RF1_BO WB_DFE0_DFE_FB_RF1_BASEADDR,0,3 ++#define WB_DFE0_DFE_FB_RF2_BO WB_DFE0_DFE_FB_RF1_BASEADDR,4,4 ++#define WB_DFE0_DFE_FB_LNA_BO WB_DFE0_DFE_FB_RF1_BASEADDR,8,2 ++ ++#define WB_DFE1_DFE_FB_RF1_BASEADDR 0x904004A4 ++#define WB_DFE1_DFE_FB_RF1_BO WB_DFE1_DFE_FB_RF1_BASEADDR,0,3 ++#define WB_DFE1_DFE_FB_RF2_BO WB_DFE1_DFE_FB_RF1_BASEADDR,4,4 ++#define WB_DFE1_DFE_FB_LNA_BO WB_DFE1_DFE_FB_RF1_BASEADDR,8,2 ++ ++#define WB_DFE2_DFE_FB_RF1_BASEADDR 0x905004A4 ++#define WB_DFE2_DFE_FB_RF1_BO WB_DFE2_DFE_FB_RF1_BASEADDR,0,3 ++#define WB_DFE2_DFE_FB_RF2_BO WB_DFE2_DFE_FB_RF1_BASEADDR,4,4 ++#define WB_DFE2_DFE_FB_LNA_BO WB_DFE2_DFE_FB_RF1_BASEADDR,8,2 ++ ++#define WB_DFE3_DFE_FB_RF1_BASEADDR 0x906004A4 ++#define WB_DFE3_DFE_FB_RF1_BO WB_DFE3_DFE_FB_RF1_BASEADDR,0,3 ++#define WB_DFE3_DFE_FB_RF2_BO WB_DFE3_DFE_FB_RF1_BASEADDR,4,4 ++#define WB_DFE3_DFE_FB_LNA_BO WB_DFE3_DFE_FB_RF1_BASEADDR,8,2 ++ ++#define AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR 0x90200104 ++#define AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_2 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,0,1 ++#define AFE_REG_D2A_TA_RFFE_RF1_BO_1P8_3 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,1,1 ++#define AFE_REG_D2A_TB_RFFE_LNA_BO_1P8_2 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,2,1 ++#define AFE_REG_D2A_TB_RFFE_RF1_BO_1P8_3 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,3,1 ++#define AFE_REG_D2A_TC_RFFE_LNA_BO_1P8_2 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,4,1 ++#define AFE_REG_D2A_TC_RFFE_RF1_BO_1P8_3 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,5,1 ++#define AFE_REG_D2A_TD_RFFE_LNA_BO_1P8_2 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,6,1 ++#define AFE_REG_D2A_TD_RFFE_RF1_BO_1P8_3 AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR,7,1 ++ ++#define AFE_REG_AFE_REG_SPARE_BASEADDR 0x902000A0 ++#define AFE_REG_D2A_TA_RFFE_RF1_CAP_1P8 AFE_REG_AFE_REG_SPARE_BASEADDR,13,5 ++ ++#define AFE_REG_AFE_REG_SPARE_BASEADDR1 0x902000B4 ++#define AFE_REG_D2A_TB_RFFE_RF1_CAP_1P8 AFE_REG_AFE_REG_SPARE_BASEADDR1,13,5 ++ ++#define AFE_REG_AFE_REG_SPARE_BASEADDR2 0x902000C4 ++#define AFE_REG_D2A_TC_RFFE_RF1_CAP_1P8 AFE_REG_AFE_REG_SPARE_BASEADDR2,13,5 ++ ++#define AFE_REG_AFE_REG_SPARE_BASEADDR3 0x902000D4 ++#define AFE_REG_D2A_TD_RFFE_RF1_CAP_1P8 AFE_REG_AFE_REG_SPARE_BASEADDR3,13,5 ++ ++#define WB_DFE0_DFE_FB_AGC_BASEADDR 0x90300498 ++#define WB_DFE0_DFE_FB_AGC_APPLY WB_DFE0_DFE_FB_AGC_BASEADDR,0,1 ++ ++#define WB_DFE1_DFE_FB_AGC_BASEADDR 0x90400498 ++#define WB_DFE1_DFE_FB_AGC_APPLY WB_DFE1_DFE_FB_AGC_BASEADDR,0,1 ++ ++#define WB_DFE2_DFE_FB_AGC_BASEADDR 0x90500498 ++#define WB_DFE2_DFE_FB_AGC_APPLY WB_DFE2_DFE_FB_AGC_BASEADDR,0,1 ++ ++#define WB_DFE3_DFE_FB_AGC_BASEADDR 0x90600498 ++#define WB_DFE3_DFE_FB_AGC_APPLY WB_DFE3_DFE_FB_AGC_BASEADDR,0,1 ++ ++#define WDT_WD_INT_BASEADDR 0x8002000C ++#define WDT_WD_INT_STATUS WDT_WD_INT_BASEADDR,0,1 ++ ++#define FSK_TX_FTM_BASEADDR 0x80090000 ++#define FSK_TX_FTM_OE FSK_TX_FTM_BASEADDR,12,1 ++#define FSK_TX_FTM_TX_EN FSK_TX_FTM_BASEADDR,10,1 ++#define FSK_TX_FTM_FORCE_CARRIER_ON FSK_TX_FTM_BASEADDR,1,1 ++#define FSK_TX_FTM_FORCE_MARK_SPACE FSK_TX_FTM_BASEADDR,0,1 ++ ++#define FSK_TX_FTM_TX_CNT_BASEADDR 0x80090018 ++#define FSK_TX_FTM_TX_CNT_INT FSK_TX_FTM_TX_CNT_BASEADDR,8,4 ++#define FSK_TX_FTM_TX_INT_EN FSK_TX_FTM_TX_CNT_BASEADDR,4,1 ++#define FSK_TX_FTM_TX_INT_SRC_SEL FSK_TX_FTM_TX_CNT_BASEADDR,0,2 ++ ++#define AFE_REG_D2A_FSK_BIAS_BASEADDR 0x90200040 ++#define AFE_REG_D2A_FSK_BIAS_EN AFE_REG_D2A_FSK_BIAS_BASEADDR,0,1 ++#define AFE_REG_D2A_FSK_TEST_EN AFE_REG_D2A_FSK_BIAS_BASEADDR,10,1 ++#define AFE_REG_D2A_FSK_TEST_MODE AFE_REG_D2A_FSK_BIAS_BASEADDR,11,4 ++#define AFE_REG_D2A_FSK_TERM_INT_EN AFE_REG_D2A_FSK_BIAS_BASEADDR,15,1 ++#define AFE_REG_D2A_FSK_RESETB_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,16,1 ++#define AFE_REG_D2A_FSK_REG_EN_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,17,1 ++#define AFE_REG_D2A_FSK_REG_EN_LKG_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,18,1 ++#define AFE_REG_D2A_FSK_REG_AMP_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,19,3 ++#define AFE_REG_D2A_FSK_REG_TEST_CTRL_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,22,2 ++#define AFE_REG_D2A_DSQ_RX_MODE AFE_REG_D2A_FSK_BIAS_BASEADDR,24,1 ++#define AFE_REG_D2A_DSQ_RX_EN AFE_REG_D2A_FSK_BIAS_BASEADDR,25,1 ++#define AFE_REG_D2A_DSQ_HYST AFE_REG_D2A_FSK_BIAS_BASEADDR,26,2 ++#define AFE_REG_D2A_DSQ_RESETB_1P8 AFE_REG_D2A_FSK_BIAS_BASEADDR,28,1 ++#define AFE_REG_D2A_FSK_CLKRX_ENA AFE_REG_D2A_FSK_BIAS_BASEADDR,29,1 ++ ++#define DMD_TEI_BASEADDR 0x3FFFEBE0 ++#define DMD_TEI_ENA DMD_TEI_BASEADDR,0,1 ++ ++#define xpt_shm_input_control0 0x90700270,0,8 ++#define xpt_shm_input_control1 0x90700270,8,8 ++#define xpt_shm_input_control2 0x90700270,16,8 ++#define xpt_shm_input_control3 0x90700270,24,8 ++#define xpt_shm_input_control4 0x90700274,0,8 ++#define xpt_shm_input_control5 0x90700274,8,8 ++#define xpt_shm_input_control6 0x90700274,16,8 ++#define xpt_shm_input_control7 0x90700274,24,8 ++ ++ ++#define xpt_shm_output_control0 0x90700278,0,8 ++#define xpt_shm_output_control1 0x90700278,8,8 ++#define xpt_shm_output_control2 0x90700278,16,8 ++#define xpt_shm_output_control3 0x90700278,24,8 ++#define xpt_shm_output_control4 0x9070027C,0,8 ++#define xpt_shm_output_control5 0x9070027C,8,8 ++#define xpt_shm_output_control6 0x9070027C,16,8 ++#define xpt_shm_output_control7 0x9070027C,24,8 ++ ++#define xpt_mode_27mhz 0x90700184,0,1 ++#define xpt_enable_pcr_count 0x90700184,1,1 ++ ++#define xcpu_ctrl_003c_reg 0x9072003C,0,4 ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif //__MXL58X_REGISTERS_H__ diff --git a/drivers/media/dvb-frontends/stv0367dd.c b/drivers/media/dvb-frontends/stv0367dd.c new file mode 100644 -index 0000000..64f7970 +index 0000000..fcb7704 --- /dev/null +++ b/drivers/media/dvb-frontends/stv0367dd.c -@@ -0,0 +1,2331 @@ +@@ -0,0 +1,1874 @@ +/* + * stv0367dd: STV0367 DVB-C/T demodulator driver + * @@ -9777,6 +6511,9 @@ index 0000000..64f7970 + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + ++#undef pr_fmt ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ +#include +#include +#include @@ -9784,14 +6521,15 @@ index 0000000..64f7970 +#include +#include +#include -+#include +#include + +#include "dvb_frontend.h" ++#include "dvb_math.h" +#include "stv0367dd.h" +#include "stv0367dd_regs.h" + -+enum omode { OM_NONE, OM_DVBT, OM_DVBC, OM_QAM_ITU_C }; ++#define INTLOG10X100(x) ((u32) (((u64) intlog10(x) * 100) >> 24)) ++ +enum { QAM_MOD_QAM4 = 0, + QAM_MOD_QAM16, + QAM_MOD_QAM32, @@ -9813,19 +6551,15 @@ index 0000000..64f7970 +enum EDemodState { Off, QAMSet, OFDMSet, QAMStarted, OFDMStarted }; + +struct stv_state { -+#ifdef USE_API3 -+ struct dvb_frontend c_frontend; -+ struct dvb_frontend t_frontend; -+#else + struct dvb_frontend frontend; -+#endif -+ fe_modulation_t modulation; ++ enum fe_modulation modulation; + u32 symbol_rate; + u32 bandwidth; + struct device *dev; + + struct i2c_adapter *i2c; + u8 adr; ++ u8 cont_clock; + void *priv; + + struct mutex mutex; @@ -9835,7 +6569,7 @@ index 0000000..64f7970 + u32 adc_clock; + u8 ID; + u8 I2CRPT; -+ u32 omode; ++ enum fe_delivery_system delsys; + u8 qam_inversion; + + s32 IF; @@ -9853,9 +6587,9 @@ index 0000000..64f7970 + + enum EDemodState demod_state; + -+ u8 m_OFDM_FFTMode; // 0 = 2k, 1 = 8k, 2 = 4k -+ u8 m_OFDM_Modulation; // -+ u8 m_OFDM_FEC; // ++ u8 m_OFDM_FFTMode; /* 0 = 2k, 1 = 8k, 2 = 4k */ ++ u8 m_OFDM_Modulation; ++ u8 m_OFDM_FEC; + u8 m_OFDM_Guard; + + u32 ucblocks; @@ -9894,7 +6628,7 @@ index 0000000..64f7970 +}; + +struct init_table qam_init[] = { -+ { R367_QAM_CTRL_1, 0x06 },// Orginal 0x04 ++ { R367_QAM_CTRL_1, 0x06 }, /* Orginal 0x04 */ + { R367_QAM_CTRL_2, 0x03 }, + { R367_QAM_IT_STATUS1, 0x2b }, + { R367_QAM_IT_STATUS2, 0x08 }, @@ -9904,7 +6638,7 @@ index 0000000..64f7970 + { R367_QAM_TEST_CTL, 0x00 }, + { R367_QAM_AGC_CTL, 0x73 }, + { R367_QAM_AGC_IF_CFG, 0x50 }, -+ { R367_QAM_AGC_RF_CFG, 0x02 },// RF Freeze ++ { R367_QAM_AGC_RF_CFG, 0x02 }, /* RF Freeze */ + { R367_QAM_AGC_PWM_CFG, 0x03 }, + { R367_QAM_AGC_PWR_REF_L, 0x5a }, + { R367_QAM_AGC_PWR_REF_H, 0x00 }, @@ -9964,7 +6698,7 @@ index 0000000..64f7970 + { R367_QAM_TRL_LOCKDET_LTH, 0x04 }, + { R367_QAM_TRL_LOCKDET_HTH, 0x11 }, + { R367_QAM_TRL_LOCKDET_TRGVAL, 0x20 }, -+ { R367_QAM_IQ_QAM, 0x01 }, ++ { R367_QAM_IQ_QAM, 0x01 }, + { R367_QAM_FSM_STATE, 0xa0 }, + { R367_QAM_FSM_CTL, 0x08 }, + { R367_QAM_FSM_STS, 0x0c }, @@ -10055,456 +6789,415 @@ index 0000000..64f7970 + { R367_QAM_T_O_ID_1, 0x00 }, + { R367_QAM_T_O_ID_2, 0x00 }, + { R367_QAM_T_O_ID_3, 0x00 }, -+ { 0x0000, 0x00 } // EOT ++ { 0x0000, 0x00 } /* EOT */ +}; + +struct init_table ofdm_init[] = { -+ //{R367_OFDM_ID ,0x60}, -+ //{R367_OFDM_I2CRPT ,0x22}, -+ //{R367_OFDM_TOPCTRL ,0x02}, -+ //{R367_OFDM_IOCFG0 ,0x40}, -+ //{R367_OFDM_DAC0R ,0x00}, -+ //{R367_OFDM_IOCFG1 ,0x00}, -+ //{R367_OFDM_DAC1R ,0x00}, -+ //{R367_OFDM_IOCFG2 ,0x62}, -+ //{R367_OFDM_SDFR ,0x00}, -+ //{R367_OFDM_STATUS ,0xf8}, -+ //{R367_OFDM_AUX_CLK ,0x0a}, -+ //{R367_OFDM_FREESYS1 ,0x00}, -+ //{R367_OFDM_FREESYS2 ,0x00}, -+ //{R367_OFDM_FREESYS3 ,0x00}, -+ //{R367_OFDM_GPIO_CFG ,0x55}, -+ //{R367_OFDM_GPIO_CMD ,0x00}, -+ {R367_OFDM_AGC2MAX ,0xff}, -+ {R367_OFDM_AGC2MIN ,0x00}, -+ {R367_OFDM_AGC1MAX ,0xff}, -+ {R367_OFDM_AGC1MIN ,0x00}, -+ {R367_OFDM_AGCR ,0xbc}, -+ {R367_OFDM_AGC2TH ,0x00}, -+ //{R367_OFDM_AGC12C ,0x01}, //Note: This defines AGC pins, also needed for QAM -+ {R367_OFDM_AGCCTRL1 ,0x85}, -+ {R367_OFDM_AGCCTRL2 ,0x1f}, -+ {R367_OFDM_AGC1VAL1 ,0x00}, -+ {R367_OFDM_AGC1VAL2 ,0x00}, -+ {R367_OFDM_AGC2VAL1 ,0x6f}, -+ {R367_OFDM_AGC2VAL2 ,0x05}, -+ {R367_OFDM_AGC2PGA ,0x00}, -+ {R367_OFDM_OVF_RATE1 ,0x00}, -+ {R367_OFDM_OVF_RATE2 ,0x00}, -+ {R367_OFDM_GAIN_SRC1 ,0x2b}, -+ {R367_OFDM_GAIN_SRC2 ,0x04}, -+ {R367_OFDM_INC_DEROT1 ,0x55}, -+ {R367_OFDM_INC_DEROT2 ,0x55}, -+ {R367_OFDM_PPM_CPAMP_DIR ,0x2c}, -+ {R367_OFDM_PPM_CPAMP_INV ,0x00}, -+ {R367_OFDM_FREESTFE_1 ,0x00}, -+ {R367_OFDM_FREESTFE_2 ,0x1c}, -+ {R367_OFDM_DCOFFSET ,0x00}, -+ {R367_OFDM_EN_PROCESS ,0x05}, -+ {R367_OFDM_SDI_SMOOTHER ,0x80}, -+ {R367_OFDM_FE_LOOP_OPEN ,0x1c}, -+ {R367_OFDM_FREQOFF1 ,0x00}, -+ {R367_OFDM_FREQOFF2 ,0x00}, -+ {R367_OFDM_FREQOFF3 ,0x00}, -+ {R367_OFDM_TIMOFF1 ,0x00}, -+ {R367_OFDM_TIMOFF2 ,0x00}, -+ {R367_OFDM_EPQ ,0x02}, -+ {R367_OFDM_EPQAUTO ,0x01}, -+ {R367_OFDM_SYR_UPDATE ,0xf5}, -+ {R367_OFDM_CHPFREE ,0x00}, -+ {R367_OFDM_PPM_STATE_MAC ,0x23}, -+ {R367_OFDM_INR_THRESHOLD ,0xff}, -+ {R367_OFDM_EPQ_TPS_ID_CELL ,0xf9}, -+ {R367_OFDM_EPQ_CFG ,0x00}, -+ {R367_OFDM_EPQ_STATUS ,0x01}, -+ {R367_OFDM_AUTORELOCK ,0x81}, -+ {R367_OFDM_BER_THR_VMSB ,0x00}, -+ {R367_OFDM_BER_THR_MSB ,0x00}, -+ {R367_OFDM_BER_THR_LSB ,0x00}, -+ {R367_OFDM_CCD ,0x83}, -+ {R367_OFDM_SPECTR_CFG ,0x00}, -+ {R367_OFDM_CHC_DUMMY ,0x18}, -+ {R367_OFDM_INC_CTL ,0x88}, -+ {R367_OFDM_INCTHRES_COR1 ,0xb4}, -+ {R367_OFDM_INCTHRES_COR2 ,0x96}, -+ {R367_OFDM_INCTHRES_DET1 ,0x0e}, -+ {R367_OFDM_INCTHRES_DET2 ,0x11}, -+ {R367_OFDM_IIR_CELLNB ,0x8d}, -+ {R367_OFDM_IIRCX_COEFF1_MSB ,0x00}, -+ {R367_OFDM_IIRCX_COEFF1_LSB ,0x00}, -+ {R367_OFDM_IIRCX_COEFF2_MSB ,0x09}, -+ {R367_OFDM_IIRCX_COEFF2_LSB ,0x18}, -+ {R367_OFDM_IIRCX_COEFF3_MSB ,0x14}, -+ {R367_OFDM_IIRCX_COEFF3_LSB ,0x9c}, -+ {R367_OFDM_IIRCX_COEFF4_MSB ,0x00}, -+ {R367_OFDM_IIRCX_COEFF4_LSB ,0x00}, -+ {R367_OFDM_IIRCX_COEFF5_MSB ,0x36}, -+ {R367_OFDM_IIRCX_COEFF5_LSB ,0x42}, -+ {R367_OFDM_FEPATH_CFG ,0x00}, -+ {R367_OFDM_PMC1_FUNC ,0x65}, -+ {R367_OFDM_PMC1_FOR ,0x00}, -+ {R367_OFDM_PMC2_FUNC ,0x00}, -+ {R367_OFDM_STATUS_ERR_DA ,0xe0}, -+ {R367_OFDM_DIG_AGC_R ,0xfe}, -+ {R367_OFDM_COMAGC_TARMSB ,0x0b}, -+ {R367_OFDM_COM_AGC_TAR_ENMODE ,0x41}, -+ {R367_OFDM_COM_AGC_CFG ,0x3e}, -+ {R367_OFDM_COM_AGC_GAIN1 ,0x39}, -+ {R367_OFDM_AUT_AGC_TARGETMSB ,0x0b}, -+ {R367_OFDM_LOCK_DET_MSB ,0x01}, -+ {R367_OFDM_AGCTAR_LOCK_LSBS ,0x40}, -+ {R367_OFDM_AUT_GAIN_EN ,0xf4}, -+ {R367_OFDM_AUT_CFG ,0xf0}, -+ {R367_OFDM_LOCKN ,0x23}, -+ {R367_OFDM_INT_X_3 ,0x00}, -+ {R367_OFDM_INT_X_2 ,0x03}, -+ {R367_OFDM_INT_X_1 ,0x8d}, -+ {R367_OFDM_INT_X_0 ,0xa0}, -+ {R367_OFDM_MIN_ERRX_MSB ,0x00}, -+ {R367_OFDM_COR_CTL ,0x00}, -+ {R367_OFDM_COR_STAT ,0xf6}, -+ {R367_OFDM_COR_INTEN ,0x00}, -+ {R367_OFDM_COR_INTSTAT ,0x3f}, -+ {R367_OFDM_COR_MODEGUARD ,0x03}, -+ {R367_OFDM_AGC_CTL ,0x08}, -+ {R367_OFDM_AGC_MANUAL1 ,0x00}, -+ {R367_OFDM_AGC_MANUAL2 ,0x00}, -+ {R367_OFDM_AGC_TARG ,0x16}, -+ {R367_OFDM_AGC_GAIN1 ,0x53}, -+ {R367_OFDM_AGC_GAIN2 ,0x1d}, -+ {R367_OFDM_RESERVED_1 ,0x00}, -+ {R367_OFDM_RESERVED_2 ,0x00}, -+ {R367_OFDM_RESERVED_3 ,0x00}, -+ {R367_OFDM_CAS_CTL ,0x44}, -+ {R367_OFDM_CAS_FREQ ,0xb3}, -+ {R367_OFDM_CAS_DAGCGAIN ,0x12}, -+ {R367_OFDM_SYR_CTL ,0x04}, -+ {R367_OFDM_SYR_STAT ,0x10}, -+ {R367_OFDM_SYR_NCO1 ,0x00}, -+ {R367_OFDM_SYR_NCO2 ,0x00}, -+ {R367_OFDM_SYR_OFFSET1 ,0x00}, -+ {R367_OFDM_SYR_OFFSET2 ,0x00}, -+ {R367_OFDM_FFT_CTL ,0x00}, -+ {R367_OFDM_SCR_CTL ,0x70}, -+ {R367_OFDM_PPM_CTL1 ,0xf8}, -+ {R367_OFDM_TRL_CTL ,0xac}, -+ {R367_OFDM_TRL_NOMRATE1 ,0x1e}, -+ {R367_OFDM_TRL_NOMRATE2 ,0x58}, -+ {R367_OFDM_TRL_TIME1 ,0x1d}, -+ {R367_OFDM_TRL_TIME2 ,0xfc}, -+ {R367_OFDM_CRL_CTL ,0x24}, -+ {R367_OFDM_CRL_FREQ1 ,0xad}, -+ {R367_OFDM_CRL_FREQ2 ,0x9d}, -+ {R367_OFDM_CRL_FREQ3 ,0xff}, -+ {R367_OFDM_CHC_CTL ,0x01}, -+ {R367_OFDM_CHC_SNR ,0xf0}, -+ {R367_OFDM_BDI_CTL ,0x00}, -+ {R367_OFDM_DMP_CTL ,0x00}, -+ {R367_OFDM_TPS_RCVD1 ,0x30}, -+ {R367_OFDM_TPS_RCVD2 ,0x02}, -+ {R367_OFDM_TPS_RCVD3 ,0x01}, -+ {R367_OFDM_TPS_RCVD4 ,0x00}, -+ {R367_OFDM_TPS_ID_CELL1 ,0x00}, -+ {R367_OFDM_TPS_ID_CELL2 ,0x00}, -+ {R367_OFDM_TPS_RCVD5_SET1 ,0x02}, -+ {R367_OFDM_TPS_SET2 ,0x02}, -+ {R367_OFDM_TPS_SET3 ,0x01}, -+ {R367_OFDM_TPS_CTL ,0x00}, -+ {R367_OFDM_CTL_FFTOSNUM ,0x34}, -+ {R367_OFDM_TESTSELECT ,0x09}, -+ {R367_OFDM_MSC_REV ,0x0a}, -+ {R367_OFDM_PIR_CTL ,0x00}, -+ {R367_OFDM_SNR_CARRIER1 ,0xa1}, -+ {R367_OFDM_SNR_CARRIER2 ,0x9a}, -+ {R367_OFDM_PPM_CPAMP ,0x2c}, -+ {R367_OFDM_TSM_AP0 ,0x00}, -+ {R367_OFDM_TSM_AP1 ,0x00}, -+ {R367_OFDM_TSM_AP2 ,0x00}, -+ {R367_OFDM_TSM_AP3 ,0x00}, -+ {R367_OFDM_TSM_AP4 ,0x00}, -+ {R367_OFDM_TSM_AP5 ,0x00}, -+ {R367_OFDM_TSM_AP6 ,0x00}, -+ {R367_OFDM_TSM_AP7 ,0x00}, -+ //{R367_OFDM_TSTRES ,0x00}, -+ //{R367_OFDM_ANACTRL ,0x0D},/*caution PLL stopped, to be restarted at init!!!*/ -+ //{R367_OFDM_TSTBUS ,0x00}, -+ //{R367_OFDM_TSTRATE ,0x00}, -+ {R367_OFDM_CONSTMODE ,0x01}, -+ {R367_OFDM_CONSTCARR1 ,0x00}, -+ {R367_OFDM_CONSTCARR2 ,0x00}, -+ {R367_OFDM_ICONSTEL ,0x0a}, -+ {R367_OFDM_QCONSTEL ,0x15}, -+ {R367_OFDM_TSTBISTRES0 ,0x00}, -+ {R367_OFDM_TSTBISTRES1 ,0x00}, -+ {R367_OFDM_TSTBISTRES2 ,0x28}, -+ {R367_OFDM_TSTBISTRES3 ,0x00}, -+ //{R367_OFDM_RF_AGC1 ,0xff}, -+ //{R367_OFDM_RF_AGC2 ,0x83}, -+ //{R367_OFDM_ANADIGCTRL ,0x19}, -+ //{R367_OFDM_PLLMDIV ,0x0c}, -+ //{R367_OFDM_PLLNDIV ,0x55}, -+ //{R367_OFDM_PLLSETUP ,0x18}, -+ //{R367_OFDM_DUAL_AD12 ,0x00}, -+ //{R367_OFDM_TSTBIST ,0x00}, -+ //{R367_OFDM_PAD_COMP_CTRL ,0x00}, -+ //{R367_OFDM_PAD_COMP_WR ,0x00}, -+ //{R367_OFDM_PAD_COMP_RD ,0xe0}, -+ {R367_OFDM_SYR_TARGET_FFTADJT_MSB ,0x00}, -+ {R367_OFDM_SYR_TARGET_FFTADJT_LSB ,0x00}, -+ {R367_OFDM_SYR_TARGET_CHCADJT_MSB ,0x00}, -+ {R367_OFDM_SYR_TARGET_CHCADJT_LSB ,0x00}, -+ {R367_OFDM_SYR_FLAG ,0x00}, -+ {R367_OFDM_CRL_TARGET1 ,0x00}, -+ {R367_OFDM_CRL_TARGET2 ,0x00}, -+ {R367_OFDM_CRL_TARGET3 ,0x00}, -+ {R367_OFDM_CRL_TARGET4 ,0x00}, -+ {R367_OFDM_CRL_FLAG ,0x00}, -+ {R367_OFDM_TRL_TARGET1 ,0x00}, -+ {R367_OFDM_TRL_TARGET2 ,0x00}, -+ {R367_OFDM_TRL_CHC ,0x00}, -+ {R367_OFDM_CHC_SNR_TARG ,0x00}, -+ {R367_OFDM_TOP_TRACK ,0x00}, -+ {R367_OFDM_TRACKER_FREE1 ,0x00}, -+ {R367_OFDM_ERROR_CRL1 ,0x00}, -+ {R367_OFDM_ERROR_CRL2 ,0x00}, -+ {R367_OFDM_ERROR_CRL3 ,0x00}, -+ {R367_OFDM_ERROR_CRL4 ,0x00}, -+ {R367_OFDM_DEC_NCO1 ,0x2c}, -+ {R367_OFDM_DEC_NCO2 ,0x0f}, -+ {R367_OFDM_DEC_NCO3 ,0x20}, -+ {R367_OFDM_SNR ,0xf1}, -+ {R367_OFDM_SYR_FFTADJ1 ,0x00}, -+ {R367_OFDM_SYR_FFTADJ2 ,0x00}, -+ {R367_OFDM_SYR_CHCADJ1 ,0x00}, -+ {R367_OFDM_SYR_CHCADJ2 ,0x00}, -+ {R367_OFDM_SYR_OFF ,0x00}, -+ {R367_OFDM_PPM_OFFSET1 ,0x00}, -+ {R367_OFDM_PPM_OFFSET2 ,0x03}, -+ {R367_OFDM_TRACKER_FREE2 ,0x00}, -+ {R367_OFDM_DEBG_LT10 ,0x00}, -+ {R367_OFDM_DEBG_LT11 ,0x00}, -+ {R367_OFDM_DEBG_LT12 ,0x00}, -+ {R367_OFDM_DEBG_LT13 ,0x00}, -+ {R367_OFDM_DEBG_LT14 ,0x00}, -+ {R367_OFDM_DEBG_LT15 ,0x00}, -+ {R367_OFDM_DEBG_LT16 ,0x00}, -+ {R367_OFDM_DEBG_LT17 ,0x00}, -+ {R367_OFDM_DEBG_LT18 ,0x00}, -+ {R367_OFDM_DEBG_LT19 ,0x00}, -+ {R367_OFDM_DEBG_LT1A ,0x00}, -+ {R367_OFDM_DEBG_LT1B ,0x00}, -+ {R367_OFDM_DEBG_LT1C ,0x00}, -+ {R367_OFDM_DEBG_LT1D ,0x00}, -+ {R367_OFDM_DEBG_LT1E ,0x00}, -+ {R367_OFDM_DEBG_LT1F ,0x00}, -+ {R367_OFDM_RCCFGH ,0x00}, -+ {R367_OFDM_RCCFGM ,0x00}, -+ {R367_OFDM_RCCFGL ,0x00}, -+ {R367_OFDM_RCINSDELH ,0x00}, -+ {R367_OFDM_RCINSDELM ,0x00}, -+ {R367_OFDM_RCINSDELL ,0x00}, -+ {R367_OFDM_RCSTATUS ,0x00}, -+ {R367_OFDM_RCSPEED ,0x6f}, -+ {R367_OFDM_RCDEBUGM ,0xe7}, -+ {R367_OFDM_RCDEBUGL ,0x9b}, -+ {R367_OFDM_RCOBSCFG ,0x00}, -+ {R367_OFDM_RCOBSM ,0x00}, -+ {R367_OFDM_RCOBSL ,0x00}, -+ {R367_OFDM_RCFECSPY ,0x00}, -+ {R367_OFDM_RCFSPYCFG ,0x00}, -+ {R367_OFDM_RCFSPYDATA ,0x00}, -+ {R367_OFDM_RCFSPYOUT ,0x00}, -+ {R367_OFDM_RCFSTATUS ,0x00}, -+ {R367_OFDM_RCFGOODPACK ,0x00}, -+ {R367_OFDM_RCFPACKCNT ,0x00}, -+ {R367_OFDM_RCFSPYMISC ,0x00}, -+ {R367_OFDM_RCFBERCPT4 ,0x00}, -+ {R367_OFDM_RCFBERCPT3 ,0x00}, -+ {R367_OFDM_RCFBERCPT2 ,0x00}, -+ {R367_OFDM_RCFBERCPT1 ,0x00}, -+ {R367_OFDM_RCFBERCPT0 ,0x00}, -+ {R367_OFDM_RCFBERERR2 ,0x00}, -+ {R367_OFDM_RCFBERERR1 ,0x00}, -+ {R367_OFDM_RCFBERERR0 ,0x00}, -+ {R367_OFDM_RCFSTATESM ,0x00}, -+ {R367_OFDM_RCFSTATESL ,0x00}, -+ {R367_OFDM_RCFSPYBER ,0x00}, -+ {R367_OFDM_RCFSPYDISTM ,0x00}, -+ {R367_OFDM_RCFSPYDISTL ,0x00}, -+ {R367_OFDM_RCFSPYOBS7 ,0x00}, -+ {R367_OFDM_RCFSPYOBS6 ,0x00}, -+ {R367_OFDM_RCFSPYOBS5 ,0x00}, -+ {R367_OFDM_RCFSPYOBS4 ,0x00}, -+ {R367_OFDM_RCFSPYOBS3 ,0x00}, -+ {R367_OFDM_RCFSPYOBS2 ,0x00}, -+ {R367_OFDM_RCFSPYOBS1 ,0x00}, -+ {R367_OFDM_RCFSPYOBS0 ,0x00}, -+ //{R367_OFDM_TSGENERAL ,0x00}, -+ //{R367_OFDM_RC1SPEED ,0x6f}, -+ //{R367_OFDM_TSGSTATUS ,0x18}, -+ {R367_OFDM_FECM ,0x01}, -+ {R367_OFDM_VTH12 ,0xff}, -+ {R367_OFDM_VTH23 ,0xa1}, -+ {R367_OFDM_VTH34 ,0x64}, -+ {R367_OFDM_VTH56 ,0x40}, -+ {R367_OFDM_VTH67 ,0x00}, -+ {R367_OFDM_VTH78 ,0x2c}, -+ {R367_OFDM_VITCURPUN ,0x12}, -+ {R367_OFDM_VERROR ,0x01}, -+ {R367_OFDM_PRVIT ,0x3f}, -+ {R367_OFDM_VAVSRVIT ,0x00}, -+ {R367_OFDM_VSTATUSVIT ,0xbd}, -+ {R367_OFDM_VTHINUSE ,0xa1}, -+ {R367_OFDM_KDIV12 ,0x20}, -+ {R367_OFDM_KDIV23 ,0x40}, -+ {R367_OFDM_KDIV34 ,0x20}, -+ {R367_OFDM_KDIV56 ,0x30}, -+ {R367_OFDM_KDIV67 ,0x00}, -+ {R367_OFDM_KDIV78 ,0x30}, -+ {R367_OFDM_SIGPOWER ,0x54}, -+ {R367_OFDM_DEMAPVIT ,0x40}, -+ {R367_OFDM_VITSCALE ,0x00}, -+ {R367_OFDM_FFEC1PRG ,0x00}, -+ {R367_OFDM_FVITCURPUN ,0x12}, -+ {R367_OFDM_FVERROR ,0x01}, -+ {R367_OFDM_FVSTATUSVIT ,0xbd}, -+ {R367_OFDM_DEBUG_LT1 ,0x00}, -+ {R367_OFDM_DEBUG_LT2 ,0x00}, -+ {R367_OFDM_DEBUG_LT3 ,0x00}, -+ {R367_OFDM_TSTSFMET ,0x00}, -+ {R367_OFDM_SELOUT ,0x00}, -+ {R367_OFDM_TSYNC ,0x00}, -+ {R367_OFDM_TSTERR ,0x00}, -+ {R367_OFDM_TSFSYNC ,0x00}, -+ {R367_OFDM_TSTSFERR ,0x00}, -+ {R367_OFDM_TSTTSSF1 ,0x01}, -+ {R367_OFDM_TSTTSSF2 ,0x1f}, -+ {R367_OFDM_TSTTSSF3 ,0x00}, -+ {R367_OFDM_TSTTS1 ,0x00}, -+ {R367_OFDM_TSTTS2 ,0x1f}, -+ {R367_OFDM_TSTTS3 ,0x01}, -+ {R367_OFDM_TSTTS4 ,0x00}, -+ {R367_OFDM_TSTTSRC ,0x00}, -+ {R367_OFDM_TSTTSRS ,0x00}, -+ {R367_OFDM_TSSTATEM ,0xb0}, -+ {R367_OFDM_TSSTATEL ,0x40}, -+ {R367_OFDM_TSCFGH ,0x80}, -+ {R367_OFDM_TSCFGM ,0x00}, -+ {R367_OFDM_TSCFGL ,0x20}, -+ {R367_OFDM_TSSYNC ,0x00}, -+ {R367_OFDM_TSINSDELH ,0x00}, -+ {R367_OFDM_TSINSDELM ,0x00}, -+ {R367_OFDM_TSINSDELL ,0x00}, -+ {R367_OFDM_TSDIVN ,0x03}, -+ {R367_OFDM_TSDIVPM ,0x00}, -+ {R367_OFDM_TSDIVPL ,0x00}, -+ {R367_OFDM_TSDIVQM ,0x00}, -+ {R367_OFDM_TSDIVQL ,0x00}, -+ {R367_OFDM_TSDILSTKM ,0x00}, -+ {R367_OFDM_TSDILSTKL ,0x00}, -+ {R367_OFDM_TSSPEED ,0x6f}, -+ {R367_OFDM_TSSTATUS ,0x81}, -+ {R367_OFDM_TSSTATUS2 ,0x6a}, -+ {R367_OFDM_TSBITRATEM ,0x0f}, -+ {R367_OFDM_TSBITRATEL ,0xc6}, -+ {R367_OFDM_TSPACKLENM ,0x00}, -+ {R367_OFDM_TSPACKLENL ,0xfc}, -+ {R367_OFDM_TSBLOCLENM ,0x0a}, -+ {R367_OFDM_TSBLOCLENL ,0x80}, -+ {R367_OFDM_TSDLYH ,0x90}, -+ {R367_OFDM_TSDLYM ,0x68}, -+ {R367_OFDM_TSDLYL ,0x01}, -+ {R367_OFDM_TSNPDAV ,0x00}, -+ {R367_OFDM_TSBUFSTATH ,0x00}, -+ {R367_OFDM_TSBUFSTATM ,0x00}, -+ {R367_OFDM_TSBUFSTATL ,0x00}, -+ {R367_OFDM_TSDEBUGM ,0xcf}, -+ {R367_OFDM_TSDEBUGL ,0x1e}, -+ {R367_OFDM_TSDLYSETH ,0x00}, -+ {R367_OFDM_TSDLYSETM ,0x68}, -+ {R367_OFDM_TSDLYSETL ,0x00}, -+ {R367_OFDM_TSOBSCFG ,0x00}, -+ {R367_OFDM_TSOBSM ,0x47}, -+ {R367_OFDM_TSOBSL ,0x1f}, -+ {R367_OFDM_ERRCTRL1 ,0x95}, -+ {R367_OFDM_ERRCNT1H ,0x80}, -+ {R367_OFDM_ERRCNT1M ,0x00}, -+ {R367_OFDM_ERRCNT1L ,0x00}, -+ {R367_OFDM_ERRCTRL2 ,0x95}, -+ {R367_OFDM_ERRCNT2H ,0x00}, -+ {R367_OFDM_ERRCNT2M ,0x00}, -+ {R367_OFDM_ERRCNT2L ,0x00}, -+ {R367_OFDM_FECSPY ,0x88}, -+ {R367_OFDM_FSPYCFG ,0x2c}, -+ {R367_OFDM_FSPYDATA ,0x3a}, -+ {R367_OFDM_FSPYOUT ,0x06}, -+ {R367_OFDM_FSTATUS ,0x61}, -+ {R367_OFDM_FGOODPACK ,0xff}, -+ {R367_OFDM_FPACKCNT ,0xff}, -+ {R367_OFDM_FSPYMISC ,0x66}, -+ {R367_OFDM_FBERCPT4 ,0x00}, -+ {R367_OFDM_FBERCPT3 ,0x00}, -+ {R367_OFDM_FBERCPT2 ,0x36}, -+ {R367_OFDM_FBERCPT1 ,0x36}, -+ {R367_OFDM_FBERCPT0 ,0x14}, -+ {R367_OFDM_FBERERR2 ,0x00}, -+ {R367_OFDM_FBERERR1 ,0x03}, -+ {R367_OFDM_FBERERR0 ,0x28}, -+ {R367_OFDM_FSTATESM ,0x00}, -+ {R367_OFDM_FSTATESL ,0x02}, -+ {R367_OFDM_FSPYBER ,0x00}, -+ {R367_OFDM_FSPYDISTM ,0x01}, -+ {R367_OFDM_FSPYDISTL ,0x9f}, -+ {R367_OFDM_FSPYOBS7 ,0xc9}, -+ {R367_OFDM_FSPYOBS6 ,0x99}, -+ {R367_OFDM_FSPYOBS5 ,0x08}, -+ {R367_OFDM_FSPYOBS4 ,0xec}, -+ {R367_OFDM_FSPYOBS3 ,0x01}, -+ {R367_OFDM_FSPYOBS2 ,0x0f}, -+ {R367_OFDM_FSPYOBS1 ,0xf5}, -+ {R367_OFDM_FSPYOBS0 ,0x08}, -+ {R367_OFDM_SFDEMAP ,0x40}, -+ {R367_OFDM_SFERROR ,0x00}, -+ {R367_OFDM_SFAVSR ,0x30}, -+ {R367_OFDM_SFECSTATUS ,0xcc}, -+ {R367_OFDM_SFKDIV12 ,0x20}, -+ {R367_OFDM_SFKDIV23 ,0x40}, -+ {R367_OFDM_SFKDIV34 ,0x20}, -+ {R367_OFDM_SFKDIV56 ,0x20}, -+ {R367_OFDM_SFKDIV67 ,0x00}, -+ {R367_OFDM_SFKDIV78 ,0x20}, -+ {R367_OFDM_SFDILSTKM ,0x00}, -+ {R367_OFDM_SFDILSTKL ,0x00}, -+ {R367_OFDM_SFSTATUS ,0xb5}, -+ {R367_OFDM_SFDLYH ,0x90}, -+ {R367_OFDM_SFDLYM ,0x60}, -+ {R367_OFDM_SFDLYL ,0x01}, -+ {R367_OFDM_SFDLYSETH ,0xc0}, -+ {R367_OFDM_SFDLYSETM ,0x60}, -+ {R367_OFDM_SFDLYSETL ,0x00}, -+ {R367_OFDM_SFOBSCFG ,0x00}, -+ {R367_OFDM_SFOBSM ,0x47}, -+ {R367_OFDM_SFOBSL ,0x05}, -+ {R367_OFDM_SFECINFO ,0x40}, -+ {R367_OFDM_SFERRCTRL ,0x74}, -+ {R367_OFDM_SFERRCNTH ,0x80}, -+ {R367_OFDM_SFERRCNTM ,0x00}, -+ {R367_OFDM_SFERRCNTL ,0x00}, -+ {R367_OFDM_SYMBRATEM ,0x2f}, -+ {R367_OFDM_SYMBRATEL ,0x50}, -+ {R367_OFDM_SYMBSTATUS ,0x7f}, -+ {R367_OFDM_SYMBCFG ,0x00}, -+ {R367_OFDM_SYMBFIFOM ,0xf4}, -+ {R367_OFDM_SYMBFIFOL ,0x0d}, -+ {R367_OFDM_SYMBOFFSM ,0xf0}, -+ {R367_OFDM_SYMBOFFSL ,0x2d}, -+ //{R367_OFDM_DEBUG_LT4 ,0x00}, -+ //{R367_OFDM_DEBUG_LT5 ,0x00}, -+ //{R367_OFDM_DEBUG_LT6 ,0x00}, -+ //{R367_OFDM_DEBUG_LT7 ,0x00}, -+ //{R367_OFDM_DEBUG_LT8 ,0x00}, -+ //{R367_OFDM_DEBUG_LT9 ,0x00}, -+ { 0x0000, 0x00 } // EOT ++ { R367_OFDM_AGC2MAX, 0xff }, ++ { R367_OFDM_AGC2MIN, 0x00 }, ++ { R367_OFDM_AGC1MAX, 0xff }, ++ { R367_OFDM_AGC1MIN, 0x00 }, ++ { R367_OFDM_AGCR, 0xbc }, ++ { R367_OFDM_AGC2TH, 0x00 }, ++ { R367_OFDM_AGCCTRL1, 0x85 }, ++ { R367_OFDM_AGCCTRL2, 0x1f }, ++ { R367_OFDM_AGC1VAL1, 0x00 }, ++ { R367_OFDM_AGC1VAL2, 0x00 }, ++ { R367_OFDM_AGC2VAL1, 0x6f }, ++ { R367_OFDM_AGC2VAL2, 0x05 }, ++ { R367_OFDM_AGC2PGA, 0x00 }, ++ { R367_OFDM_OVF_RATE1, 0x00 }, ++ { R367_OFDM_OVF_RATE2, 0x00 }, ++ { R367_OFDM_GAIN_SRC1, 0x2b }, ++ { R367_OFDM_GAIN_SRC2, 0x04 }, ++ { R367_OFDM_INC_DEROT1, 0x55 }, ++ { R367_OFDM_INC_DEROT2, 0x55 }, ++ { R367_OFDM_PPM_CPAMP_DIR, 0x2c }, ++ { R367_OFDM_PPM_CPAMP_INV, 0x00 }, ++ { R367_OFDM_FREESTFE_1, 0x00 }, ++ { R367_OFDM_FREESTFE_2, 0x1c }, ++ { R367_OFDM_DCOFFSET, 0x00 }, ++ { R367_OFDM_EN_PROCESS, 0x05 }, ++ { R367_OFDM_SDI_SMOOTHER, 0x80 }, ++ { R367_OFDM_FE_LOOP_OPEN, 0x1c }, ++ { R367_OFDM_FREQOFF1, 0x00 }, ++ { R367_OFDM_FREQOFF2, 0x00 }, ++ { R367_OFDM_FREQOFF3, 0x00 }, ++ { R367_OFDM_TIMOFF1, 0x00 }, ++ { R367_OFDM_TIMOFF2, 0x00 }, ++ { R367_OFDM_EPQ, 0x02 }, ++ { R367_OFDM_EPQAUTO, 0x01 }, ++ { R367_OFDM_SYR_UPDATE, 0xf5 }, ++ { R367_OFDM_CHPFREE, 0x00 }, ++ { R367_OFDM_PPM_STATE_MAC, 0x23 }, ++ { R367_OFDM_INR_THRESHOLD, 0xff }, ++ { R367_OFDM_EPQ_TPS_ID_CELL, 0xf9 }, ++ { R367_OFDM_EPQ_CFG, 0x00 }, ++ { R367_OFDM_EPQ_STATUS, 0x01 }, ++ { R367_OFDM_AUTORELOCK, 0x81 }, ++ { R367_OFDM_BER_THR_VMSB, 0x00 }, ++ { R367_OFDM_BER_THR_MSB, 0x00 }, ++ { R367_OFDM_BER_THR_LSB, 0x00 }, ++ { R367_OFDM_CCD, 0x83 }, ++ { R367_OFDM_SPECTR_CFG, 0x00 }, ++ { R367_OFDM_CHC_DUMMY, 0x18 }, ++ { R367_OFDM_INC_CTL, 0x88 }, ++ { R367_OFDM_INCTHRES_COR1, 0xb4 }, ++ { R367_OFDM_INCTHRES_COR2, 0x96 }, ++ { R367_OFDM_INCTHRES_DET1, 0x0e }, ++ { R367_OFDM_INCTHRES_DET2, 0x11 }, ++ { R367_OFDM_IIR_CELLNB, 0x8d }, ++ { R367_OFDM_IIRCX_COEFF1_MSB, 0x00 }, ++ { R367_OFDM_IIRCX_COEFF1_LSB, 0x00 }, ++ { R367_OFDM_IIRCX_COEFF2_MSB, 0x09 }, ++ { R367_OFDM_IIRCX_COEFF2_LSB, 0x18 }, ++ { R367_OFDM_IIRCX_COEFF3_MSB, 0x14 }, ++ { R367_OFDM_IIRCX_COEFF3_LSB, 0x9c }, ++ { R367_OFDM_IIRCX_COEFF4_MSB, 0x00 }, ++ { R367_OFDM_IIRCX_COEFF4_LSB, 0x00 }, ++ { R367_OFDM_IIRCX_COEFF5_MSB, 0x36 }, ++ { R367_OFDM_IIRCX_COEFF5_LSB, 0x42 }, ++ { R367_OFDM_FEPATH_CFG, 0x00 }, ++ { R367_OFDM_PMC1_FUNC, 0x65 }, ++ { R367_OFDM_PMC1_FOR, 0x00 }, ++ { R367_OFDM_PMC2_FUNC, 0x00 }, ++ { R367_OFDM_STATUS_ERR_DA, 0xe0 }, ++ { R367_OFDM_DIG_AGC_R, 0xfe }, ++ { R367_OFDM_COMAGC_TARMSB, 0x0b }, ++ { R367_OFDM_COM_AGC_TAR_ENMODE, 0x41 }, ++ { R367_OFDM_COM_AGC_CFG, 0x3e }, ++ { R367_OFDM_COM_AGC_GAIN1, 0x39 }, ++ { R367_OFDM_AUT_AGC_TARGETMSB, 0x0b }, ++ { R367_OFDM_LOCK_DET_MSB, 0x01 }, ++ { R367_OFDM_AGCTAR_LOCK_LSBS, 0x40 }, ++ { R367_OFDM_AUT_GAIN_EN, 0xf4 }, ++ { R367_OFDM_AUT_CFG, 0xf0 }, ++ { R367_OFDM_LOCKN, 0x23 }, ++ { R367_OFDM_INT_X_3, 0x00 }, ++ { R367_OFDM_INT_X_2, 0x03 }, ++ { R367_OFDM_INT_X_1, 0x8d }, ++ { R367_OFDM_INT_X_0, 0xa0 }, ++ { R367_OFDM_MIN_ERRX_MSB, 0x00 }, ++ { R367_OFDM_COR_CTL, 0x00 }, ++ { R367_OFDM_COR_STAT, 0xf6 }, ++ { R367_OFDM_COR_INTEN, 0x00 }, ++ { R367_OFDM_COR_INTSTAT, 0x3f }, ++ { R367_OFDM_COR_MODEGUARD, 0x03 }, ++ { R367_OFDM_AGC_CTL, 0x08 }, ++ { R367_OFDM_AGC_MANUAL1, 0x00 }, ++ { R367_OFDM_AGC_MANUAL2, 0x00 }, ++ { R367_OFDM_AGC_TARG, 0x16 }, ++ { R367_OFDM_AGC_GAIN1, 0x53 }, ++ { R367_OFDM_AGC_GAIN2, 0x1d }, ++ { R367_OFDM_RESERVED_1, 0x00 }, ++ { R367_OFDM_RESERVED_2, 0x00 }, ++ { R367_OFDM_RESERVED_3, 0x00 }, ++ { R367_OFDM_CAS_CTL, 0x44 }, ++ { R367_OFDM_CAS_FREQ, 0xb3 }, ++ { R367_OFDM_CAS_DAGCGAIN, 0x12 }, ++ { R367_OFDM_SYR_CTL, 0x04 }, ++ { R367_OFDM_SYR_STAT, 0x10 }, ++ { R367_OFDM_SYR_NCO1, 0x00 }, ++ { R367_OFDM_SYR_NCO2, 0x00 }, ++ { R367_OFDM_SYR_OFFSET1, 0x00 }, ++ { R367_OFDM_SYR_OFFSET2, 0x00 }, ++ { R367_OFDM_FFT_CTL, 0x00 }, ++ { R367_OFDM_SCR_CTL, 0x70 }, ++ { R367_OFDM_PPM_CTL1, 0xf8 }, ++ { R367_OFDM_TRL_CTL, 0xac }, ++ { R367_OFDM_TRL_NOMRATE1, 0x1e }, ++ { R367_OFDM_TRL_NOMRATE2, 0x58 }, ++ { R367_OFDM_TRL_TIME1, 0x1d }, ++ { R367_OFDM_TRL_TIME2, 0xfc }, ++ { R367_OFDM_CRL_CTL, 0x24 }, ++ { R367_OFDM_CRL_FREQ1, 0xad }, ++ { R367_OFDM_CRL_FREQ2, 0x9d }, ++ { R367_OFDM_CRL_FREQ3, 0xff }, ++ { R367_OFDM_CHC_CTL, 0x01 }, ++ { R367_OFDM_CHC_SNR, 0xf0 }, ++ { R367_OFDM_BDI_CTL, 0x00 }, ++ { R367_OFDM_DMP_CTL, 0x00 }, ++ { R367_OFDM_TPS_RCVD1, 0x30 }, ++ { R367_OFDM_TPS_RCVD2, 0x02 }, ++ { R367_OFDM_TPS_RCVD3, 0x01 }, ++ { R367_OFDM_TPS_RCVD4, 0x00 }, ++ { R367_OFDM_TPS_ID_CELL1, 0x00 }, ++ { R367_OFDM_TPS_ID_CELL2, 0x00 }, ++ { R367_OFDM_TPS_RCVD5_SET1, 0x02 }, ++ { R367_OFDM_TPS_SET2, 0x02 }, ++ { R367_OFDM_TPS_SET3, 0x01 }, ++ { R367_OFDM_TPS_CTL, 0x00 }, ++ { R367_OFDM_CTL_FFTOSNUM, 0x34 }, ++ { R367_OFDM_TESTSELECT, 0x09 }, ++ { R367_OFDM_MSC_REV, 0x0a }, ++ { R367_OFDM_PIR_CTL, 0x00 }, ++ { R367_OFDM_SNR_CARRIER1, 0xa1 }, ++ { R367_OFDM_SNR_CARRIER2, 0x9a }, ++ { R367_OFDM_PPM_CPAMP, 0x2c }, ++ { R367_OFDM_TSM_AP0, 0x00 }, ++ { R367_OFDM_TSM_AP1, 0x00 }, ++ { R367_OFDM_TSM_AP2, 0x00 }, ++ { R367_OFDM_TSM_AP3, 0x00 }, ++ { R367_OFDM_TSM_AP4, 0x00 }, ++ { R367_OFDM_TSM_AP5, 0x00 }, ++ { R367_OFDM_TSM_AP6, 0x00 }, ++ { R367_OFDM_TSM_AP7, 0x00 }, ++ { R367_OFDM_CONSTMODE, 0x01 }, ++ { R367_OFDM_CONSTCARR1, 0x00 }, ++ { R367_OFDM_CONSTCARR2, 0x00 }, ++ { R367_OFDM_ICONSTEL, 0x0a }, ++ { R367_OFDM_QCONSTEL, 0x15 }, ++ { R367_OFDM_TSTBISTRES0, 0x00 }, ++ { R367_OFDM_TSTBISTRES1, 0x00 }, ++ { R367_OFDM_TSTBISTRES2, 0x28 }, ++ { R367_OFDM_TSTBISTRES3, 0x00 }, ++ { R367_OFDM_SYR_TARGET_FFTADJT_MSB, 0x00 }, ++ { R367_OFDM_SYR_TARGET_FFTADJT_LSB, 0x00 }, ++ { R367_OFDM_SYR_TARGET_CHCADJT_MSB, 0x00 }, ++ { R367_OFDM_SYR_TARGET_CHCADJT_LSB, 0x00 }, ++ { R367_OFDM_SYR_FLAG, 0x00 }, ++ { R367_OFDM_CRL_TARGET1, 0x00 }, ++ { R367_OFDM_CRL_TARGET2, 0x00 }, ++ { R367_OFDM_CRL_TARGET3, 0x00 }, ++ { R367_OFDM_CRL_TARGET4, 0x00 }, ++ { R367_OFDM_CRL_FLAG, 0x00 }, ++ { R367_OFDM_TRL_TARGET1, 0x00 }, ++ { R367_OFDM_TRL_TARGET2, 0x00 }, ++ { R367_OFDM_TRL_CHC, 0x00 }, ++ { R367_OFDM_CHC_SNR_TARG, 0x00 }, ++ { R367_OFDM_TOP_TRACK, 0x00 }, ++ { R367_OFDM_TRACKER_FREE1, 0x00 }, ++ { R367_OFDM_ERROR_CRL1, 0x00 }, ++ { R367_OFDM_ERROR_CRL2, 0x00 }, ++ { R367_OFDM_ERROR_CRL3, 0x00 }, ++ { R367_OFDM_ERROR_CRL4, 0x00 }, ++ { R367_OFDM_DEC_NCO1, 0x2c }, ++ { R367_OFDM_DEC_NCO2, 0x0f }, ++ { R367_OFDM_DEC_NCO3, 0x20 }, ++ { R367_OFDM_SNR, 0xf1 }, ++ { R367_OFDM_SYR_FFTADJ1, 0x00 }, ++ { R367_OFDM_SYR_FFTADJ2, 0x00 }, ++ { R367_OFDM_SYR_CHCADJ1, 0x00 }, ++ { R367_OFDM_SYR_CHCADJ2, 0x00 }, ++ { R367_OFDM_SYR_OFF, 0x00 }, ++ { R367_OFDM_PPM_OFFSET1, 0x00 }, ++ { R367_OFDM_PPM_OFFSET2, 0x03 }, ++ { R367_OFDM_TRACKER_FREE2, 0x00 }, ++ { R367_OFDM_DEBG_LT10, 0x00 }, ++ { R367_OFDM_DEBG_LT11, 0x00 }, ++ { R367_OFDM_DEBG_LT12, 0x00 }, ++ { R367_OFDM_DEBG_LT13, 0x00 }, ++ { R367_OFDM_DEBG_LT14, 0x00 }, ++ { R367_OFDM_DEBG_LT15, 0x00 }, ++ { R367_OFDM_DEBG_LT16, 0x00 }, ++ { R367_OFDM_DEBG_LT17, 0x00 }, ++ { R367_OFDM_DEBG_LT18, 0x00 }, ++ { R367_OFDM_DEBG_LT19, 0x00 }, ++ { R367_OFDM_DEBG_LT1A, 0x00 }, ++ { R367_OFDM_DEBG_LT1B, 0x00 }, ++ { R367_OFDM_DEBG_LT1C, 0x00 }, ++ { R367_OFDM_DEBG_LT1D, 0x00 }, ++ { R367_OFDM_DEBG_LT1E, 0x00 }, ++ { R367_OFDM_DEBG_LT1F, 0x00 }, ++ { R367_OFDM_RCCFGH, 0x00 }, ++ { R367_OFDM_RCCFGM, 0x00 }, ++ { R367_OFDM_RCCFGL, 0x00 }, ++ { R367_OFDM_RCINSDELH, 0x00 }, ++ { R367_OFDM_RCINSDELM, 0x00 }, ++ { R367_OFDM_RCINSDELL, 0x00 }, ++ { R367_OFDM_RCSTATUS, 0x00 }, ++ { R367_OFDM_RCSPEED, 0x6f }, ++ { R367_OFDM_RCDEBUGM, 0xe7 }, ++ { R367_OFDM_RCDEBUGL, 0x9b }, ++ { R367_OFDM_RCOBSCFG, 0x00 }, ++ { R367_OFDM_RCOBSM, 0x00 }, ++ { R367_OFDM_RCOBSL, 0x00 }, ++ { R367_OFDM_RCFECSPY, 0x00 }, ++ { R367_OFDM_RCFSPYCFG, 0x00 }, ++ { R367_OFDM_RCFSPYDATA, 0x00 }, ++ { R367_OFDM_RCFSPYOUT, 0x00 }, ++ { R367_OFDM_RCFSTATUS, 0x00 }, ++ { R367_OFDM_RCFGOODPACK, 0x00 }, ++ { R367_OFDM_RCFPACKCNT, 0x00 }, ++ { R367_OFDM_RCFSPYMISC, 0x00 }, ++ { R367_OFDM_RCFBERCPT4, 0x00 }, ++ { R367_OFDM_RCFBERCPT3, 0x00 }, ++ { R367_OFDM_RCFBERCPT2, 0x00 }, ++ { R367_OFDM_RCFBERCPT1, 0x00 }, ++ { R367_OFDM_RCFBERCPT0, 0x00 }, ++ { R367_OFDM_RCFBERERR2, 0x00 }, ++ { R367_OFDM_RCFBERERR1, 0x00 }, ++ { R367_OFDM_RCFBERERR0, 0x00 }, ++ { R367_OFDM_RCFSTATESM, 0x00 }, ++ { R367_OFDM_RCFSTATESL, 0x00 }, ++ { R367_OFDM_RCFSPYBER, 0x00 }, ++ { R367_OFDM_RCFSPYDISTM, 0x00 }, ++ { R367_OFDM_RCFSPYDISTL, 0x00 }, ++ { R367_OFDM_RCFSPYOBS7, 0x00 }, ++ { R367_OFDM_RCFSPYOBS6, 0x00 }, ++ { R367_OFDM_RCFSPYOBS5, 0x00 }, ++ { R367_OFDM_RCFSPYOBS4, 0x00 }, ++ { R367_OFDM_RCFSPYOBS3, 0x00 }, ++ { R367_OFDM_RCFSPYOBS2, 0x00 }, ++ { R367_OFDM_RCFSPYOBS1, 0x00 }, ++ { R367_OFDM_RCFSPYOBS0, 0x00 }, ++ { R367_OFDM_FECM, 0x01 }, ++ { R367_OFDM_VTH12, 0xff }, ++ { R367_OFDM_VTH23, 0xa1 }, ++ { R367_OFDM_VTH34, 0x64 }, ++ { R367_OFDM_VTH56, 0x40 }, ++ { R367_OFDM_VTH67, 0x00 }, ++ { R367_OFDM_VTH78, 0x2c }, ++ { R367_OFDM_VITCURPUN, 0x12 }, ++ { R367_OFDM_VERROR, 0x01 }, ++ { R367_OFDM_PRVIT, 0x3f }, ++ { R367_OFDM_VAVSRVIT, 0x00 }, ++ { R367_OFDM_VSTATUSVIT, 0xbd }, ++ { R367_OFDM_VTHINUSE, 0xa1 }, ++ { R367_OFDM_KDIV12, 0x20 }, ++ { R367_OFDM_KDIV23, 0x40 }, ++ { R367_OFDM_KDIV34, 0x20 }, ++ { R367_OFDM_KDIV56, 0x30 }, ++ { R367_OFDM_KDIV67, 0x00 }, ++ { R367_OFDM_KDIV78, 0x30 }, ++ { R367_OFDM_SIGPOWER, 0x54 }, ++ { R367_OFDM_DEMAPVIT, 0x40 }, ++ { R367_OFDM_VITSCALE, 0x00 }, ++ { R367_OFDM_FFEC1PRG, 0x00 }, ++ { R367_OFDM_FVITCURPUN, 0x12 }, ++ { R367_OFDM_FVERROR, 0x01 }, ++ { R367_OFDM_FVSTATUSVIT, 0xbd }, ++ { R367_OFDM_DEBUG_LT1, 0x00 }, ++ { R367_OFDM_DEBUG_LT2, 0x00 }, ++ { R367_OFDM_DEBUG_LT3, 0x00 }, ++ { R367_OFDM_TSTSFMET, 0x00 }, ++ { R367_OFDM_SELOUT, 0x00 }, ++ { R367_OFDM_TSYNC, 0x00 }, ++ { R367_OFDM_TSTERR, 0x00 }, ++ { R367_OFDM_TSFSYNC, 0x00 }, ++ { R367_OFDM_TSTSFERR, 0x00 }, ++ { R367_OFDM_TSTTSSF1, 0x01 }, ++ { R367_OFDM_TSTTSSF2, 0x1f }, ++ { R367_OFDM_TSTTSSF3, 0x00 }, ++ { R367_OFDM_TSTTS1, 0x00 }, ++ { R367_OFDM_TSTTS2, 0x1f }, ++ { R367_OFDM_TSTTS3, 0x01 }, ++ { R367_OFDM_TSTTS4, 0x00 }, ++ { R367_OFDM_TSTTSRC, 0x00 }, ++ { R367_OFDM_TSTTSRS, 0x00 }, ++ { R367_OFDM_TSSTATEM, 0xb0 }, ++ { R367_OFDM_TSSTATEL, 0x40 }, ++ { R367_OFDM_TSCFGH, 0x80 }, ++ { R367_OFDM_TSCFGM, 0x00 }, ++ { R367_OFDM_TSCFGL, 0x20 }, ++ { R367_OFDM_TSSYNC, 0x00 }, ++ { R367_OFDM_TSINSDELH, 0x00 }, ++ { R367_OFDM_TSINSDELM, 0x00 }, ++ { R367_OFDM_TSINSDELL, 0x00 }, ++ { R367_OFDM_TSDIVN, 0x03 }, ++ { R367_OFDM_TSDIVPM, 0x00 }, ++ { R367_OFDM_TSDIVPL, 0x00 }, ++ { R367_OFDM_TSDIVQM, 0x00 }, ++ { R367_OFDM_TSDIVQL, 0x00 }, ++ { R367_OFDM_TSDILSTKM, 0x00 }, ++ { R367_OFDM_TSDILSTKL, 0x00 }, ++ { R367_OFDM_TSSPEED, 0x6f }, ++ { R367_OFDM_TSSTATUS, 0x81 }, ++ { R367_OFDM_TSSTATUS2, 0x6a }, ++ { R367_OFDM_TSBITRATEM, 0x0f }, ++ { R367_OFDM_TSBITRATEL, 0xc6 }, ++ { R367_OFDM_TSPACKLENM, 0x00 }, ++ { R367_OFDM_TSPACKLENL, 0xfc }, ++ { R367_OFDM_TSBLOCLENM, 0x0a }, ++ { R367_OFDM_TSBLOCLENL, 0x80 }, ++ { R367_OFDM_TSDLYH, 0x90 }, ++ { R367_OFDM_TSDLYM, 0x68 }, ++ { R367_OFDM_TSDLYL, 0x01 }, ++ { R367_OFDM_TSNPDAV, 0x00 }, ++ { R367_OFDM_TSBUFSTATH, 0x00 }, ++ { R367_OFDM_TSBUFSTATM, 0x00 }, ++ { R367_OFDM_TSBUFSTATL, 0x00 }, ++ { R367_OFDM_TSDEBUGM, 0xcf }, ++ { R367_OFDM_TSDEBUGL, 0x1e }, ++ { R367_OFDM_TSDLYSETH, 0x00 }, ++ { R367_OFDM_TSDLYSETM, 0x68 }, ++ { R367_OFDM_TSDLYSETL, 0x00 }, ++ { R367_OFDM_TSOBSCFG, 0x00 }, ++ { R367_OFDM_TSOBSM, 0x47 }, ++ { R367_OFDM_TSOBSL, 0x1f }, ++ { R367_OFDM_ERRCTRL1, 0x95 }, ++ { R367_OFDM_ERRCNT1H, 0x80 }, ++ { R367_OFDM_ERRCNT1M, 0x00 }, ++ { R367_OFDM_ERRCNT1L, 0x00 }, ++ { R367_OFDM_ERRCTRL2, 0x95 }, ++ { R367_OFDM_ERRCNT2H, 0x00 }, ++ { R367_OFDM_ERRCNT2M, 0x00 }, ++ { R367_OFDM_ERRCNT2L, 0x00 }, ++ { R367_OFDM_FECSPY, 0x88 }, ++ { R367_OFDM_FSPYCFG, 0x2c }, ++ { R367_OFDM_FSPYDATA, 0x3a }, ++ { R367_OFDM_FSPYOUT, 0x06 }, ++ { R367_OFDM_FSTATUS, 0x61 }, ++ { R367_OFDM_FGOODPACK, 0xff }, ++ { R367_OFDM_FPACKCNT, 0xff }, ++ { R367_OFDM_FSPYMISC, 0x66 }, ++ { R367_OFDM_FBERCPT4, 0x00 }, ++ { R367_OFDM_FBERCPT3, 0x00 }, ++ { R367_OFDM_FBERCPT2, 0x36 }, ++ { R367_OFDM_FBERCPT1, 0x36 }, ++ { R367_OFDM_FBERCPT0, 0x14 }, ++ { R367_OFDM_FBERERR2, 0x00 }, ++ { R367_OFDM_FBERERR1, 0x03 }, ++ { R367_OFDM_FBERERR0, 0x28 }, ++ { R367_OFDM_FSTATESM, 0x00 }, ++ { R367_OFDM_FSTATESL, 0x02 }, ++ { R367_OFDM_FSPYBER, 0x00 }, ++ { R367_OFDM_FSPYDISTM, 0x01 }, ++ { R367_OFDM_FSPYDISTL, 0x9f }, ++ { R367_OFDM_FSPYOBS7, 0xc9 }, ++ { R367_OFDM_FSPYOBS6, 0x99 }, ++ { R367_OFDM_FSPYOBS5, 0x08 }, ++ { R367_OFDM_FSPYOBS4, 0xec }, ++ { R367_OFDM_FSPYOBS3, 0x01 }, ++ { R367_OFDM_FSPYOBS2, 0x0f }, ++ { R367_OFDM_FSPYOBS1, 0xf5 }, ++ { R367_OFDM_FSPYOBS0, 0x08 }, ++ { R367_OFDM_SFDEMAP, 0x40 }, ++ { R367_OFDM_SFERROR, 0x00 }, ++ { R367_OFDM_SFAVSR, 0x30 }, ++ { R367_OFDM_SFECSTATUS, 0xcc }, ++ { R367_OFDM_SFKDIV12, 0x20 }, ++ { R367_OFDM_SFKDIV23, 0x40 }, ++ { R367_OFDM_SFKDIV34, 0x20 }, ++ { R367_OFDM_SFKDIV56, 0x20 }, ++ { R367_OFDM_SFKDIV67, 0x00 }, ++ { R367_OFDM_SFKDIV78, 0x20 }, ++ { R367_OFDM_SFDILSTKM, 0x00 }, ++ { R367_OFDM_SFDILSTKL, 0x00 }, ++ { R367_OFDM_SFSTATUS, 0xb5 }, ++ { R367_OFDM_SFDLYH, 0x90 }, ++ { R367_OFDM_SFDLYM, 0x60 }, ++ { R367_OFDM_SFDLYL, 0x01 }, ++ { R367_OFDM_SFDLYSETH, 0xc0 }, ++ { R367_OFDM_SFDLYSETM, 0x60 }, ++ { R367_OFDM_SFDLYSETL, 0x00 }, ++ { R367_OFDM_SFOBSCFG, 0x00 }, ++ { R367_OFDM_SFOBSM, 0x47 }, ++ { R367_OFDM_SFOBSL, 0x05 }, ++ { R367_OFDM_SFECINFO, 0x40 }, ++ { R367_OFDM_SFERRCTRL, 0x74 }, ++ { R367_OFDM_SFERRCNTH, 0x80 }, ++ { R367_OFDM_SFERRCNTM, 0x00 }, ++ { R367_OFDM_SFERRCNTL, 0x00 }, ++ { R367_OFDM_SYMBRATEM, 0x2f }, ++ { R367_OFDM_SYMBRATEL, 0x50 }, ++ { R367_OFDM_SYMBSTATUS, 0x7f }, ++ { R367_OFDM_SYMBCFG, 0x00 }, ++ { R367_OFDM_SYMBFIFOM, 0xf4 }, ++ { R367_OFDM_SYMBFIFOL, 0x0d }, ++ { R367_OFDM_SYMBOFFSM, 0xf0 }, ++ { R367_OFDM_SYMBOFFSL, 0x2d }, ++ { 0x0000, 0x00 } /* EOT */ +}; + +static inline u32 MulDiv32(u32 a, u32 b, u32 c) @@ -10519,31 +7212,33 @@ index 0000000..64f7970 + +static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +{ -+ struct i2c_msg msg = -+ {.addr = adr, .flags = 0, .buf = data, .len = len}; ++ struct i2c_msg msg = { ++ .addr = adr, .flags = 0, .buf = data, .len = len }; + + if (i2c_transfer(adap, &msg, 1) != 1) { -+ printk("stv0367: i2c_write error\n"); -+ return -1; ++ pr_warn("i2c_write error ([%02x] %04x: %02x)\n", ++ adr, (data[0] << 8) | data[1], ++ (len > 2 ? data[2] : 0)); ++ return -EREMOTEIO; + } + return 0; +} + -+#if 0 -+static int i2c_read(struct i2c_adapter *adap, -+ u8 adr, u8 *msg, int len, u8 *answ, int alen) ++static int i2c_read(struct i2c_adapter *adap, u8 adr, u16 reg, u8 *val, int count) +{ -+ struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, -+ .buf = msg, .len = len}, -+ { .addr = adr, .flags = I2C_M_RD, -+ .buf = answ, .len = alen } }; ++ u8 msg[2] = {reg >> 8, reg & 0xff}; ++ struct i2c_msg msgs[2] = { ++ {.addr = adr, .flags = 0, .buf = msg, .len = 2 }, ++ {.addr = adr, .flags = I2C_M_RD, .buf = val, .len = count } }; ++ + if (i2c_transfer(adap, msgs, 2) != 2) { -+ printk("stv0367: i2c_read error\n"); -+ return -1; ++ pr_warn("i2c_read error ([%02x] %04x)\n", ++ adr, reg); ++ return -EREMOTEIO; + } ++ + return 0; +} -+#endif + +static int writereg(struct stv_state *state, u16 reg, u8 dat) +{ @@ -10554,22 +7249,12 @@ index 0000000..64f7970 + +static int readreg(struct stv_state *state, u16 reg, u8 *val) +{ -+ u8 msg[2] = {reg >> 8, reg & 0xff}; -+ struct i2c_msg msgs[2] = {{.addr = state->adr, .flags = 0, -+ .buf = msg, .len = 2}, -+ {.addr = state->adr, .flags = I2C_M_RD, -+ .buf = val, .len = 1}}; -+ return (i2c_transfer(state->i2c, msgs, 2) == 2) ? 0 : -1; ++ return i2c_read(state->i2c, state->adr, reg, val, 1); +} + +static int readregs(struct stv_state *state, u16 reg, u8 *val, int count) +{ -+ u8 msg[2] = {reg >> 8, reg & 0xff}; -+ struct i2c_msg msgs[2] = {{.addr = state->adr, .flags = 0, -+ .buf = msg, .len = 2}, -+ {.addr = state->adr, .flags = I2C_M_RD, -+ .buf = val, .len = count}}; -+ return (i2c_transfer(state->i2c, msgs, 2) == 2) ? 0 : -1; ++ return i2c_read(state->i2c, state->adr, reg, val, count); +} + +static int write_init_table(struct stv_state *state, struct init_table *tab) @@ -10578,9 +7263,10 @@ index 0000000..64f7970 + if (!tab->adr) + break; + if (writereg(state, tab->adr, tab->data) < 0) -+ return -1; ++ return -EREMOTEIO; + tab++; + } ++ + return 0; +} + @@ -10588,98 +7274,100 @@ index 0000000..64f7970 +{ + int stat = 0; + -+ switch(state->modulation) { ++ switch (state->modulation) { + case QAM_16: -+ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM16 ); -+ writereg(state, R367_QAM_AGC_PWR_REF_L,0x64); /* Set analog AGC reference */ -+ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ -+ writereg(state, R367_QAM_FSM_STATE,0x90); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); -+ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x95); -+ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,0x8a); ++ writereg(state, R367_QAM_EQU_MAPPER, ++ state->qam_inversion | QAM_MOD_QAM16); ++ /* Set analog AGC reference */ ++ writereg(state, R367_QAM_AGC_PWR_REF_L, 0x64); ++ /* Set digital AGC reference */ ++ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF, 0x00); ++ writereg(state, R367_QAM_FSM_STATE, 0x90); ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN, 0xc1); ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN, 0xa7); ++ writereg(state, R367_QAM_EQU_CRL_LD_SEN, 0x95); ++ writereg(state, R367_QAM_EQU_CRL_LIMITER, 0x40); ++ writereg(state, R367_QAM_EQU_PNT_GAIN, 0x8a); + break; + case QAM_32: -+ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM32 ); -+ writereg(state, R367_QAM_AGC_PWR_REF_L,0x6e); /* Set analog AGC reference */ -+ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ -+ writereg(state, R367_QAM_FSM_STATE,0xb0); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xb7); -+ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x9d); -+ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x7f); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); ++ writereg(state, R367_QAM_EQU_MAPPER, ++ state->qam_inversion | QAM_MOD_QAM32); ++ /* Set analog AGC reference */ ++ writereg(state, R367_QAM_AGC_PWR_REF_L, 0x6e); ++ /* Set digital AGC reference */ ++ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF, 0x00); ++ writereg(state, R367_QAM_FSM_STATE, 0xb0); ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN, 0xc1); ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN, 0xb7); ++ writereg(state, R367_QAM_EQU_CRL_LD_SEN, 0x9d); ++ writereg(state, R367_QAM_EQU_CRL_LIMITER, 0x7f); ++ writereg(state, R367_QAM_EQU_PNT_GAIN, 0xa7); + break; + case QAM_64: -+ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM64 ); -+ writereg(state, R367_QAM_AGC_PWR_REF_L,0x5a); /* Set analog AGC reference */ -+ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x82); /* Set digital AGC reference */ -+ if(state->symbol_rate>4500000) -+ { -+ writereg(state, R367_QAM_FSM_STATE,0xb0); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa5); ++ writereg(state, R367_QAM_EQU_MAPPER, ++ state->qam_inversion | QAM_MOD_QAM64); ++ /* Set analog AGC reference */ ++ writereg(state, R367_QAM_AGC_PWR_REF_L, 0x5a); ++ /* Set digital AGC reference */ ++ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF, 0x82); ++ ++ if (state->symbol_rate > 4500000) { ++ writereg(state, R367_QAM_FSM_STATE, 0xb0); ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN, 0xc1); ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN, 0xa5); ++ } else if (state->symbol_rate > 2500000) { /* 25000000 */ ++ writereg(state, R367_QAM_FSM_STATE, 0xa0); ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN, 0xc1); ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN, 0xa6); ++ } else { ++ writereg(state, R367_QAM_FSM_STATE, 0xa0); ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN, 0xd1); ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN, 0xa7); + } -+ else if(state->symbol_rate>2500000) // 25000000 -+ { -+ writereg(state, R367_QAM_FSM_STATE,0xa0); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa6); -+ } -+ else -+ { -+ writereg(state, R367_QAM_FSM_STATE,0xa0); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xd1); -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); -+ } -+ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x95); -+ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,0x99); ++ writereg(state, R367_QAM_EQU_CRL_LD_SEN, 0x95); ++ writereg(state, R367_QAM_EQU_CRL_LIMITER, 0x40); ++ writereg(state, R367_QAM_EQU_PNT_GAIN, 0x99); + break; + case QAM_128: -+ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM128 ); -+ writereg(state, R367_QAM_AGC_PWR_REF_L,0x76); /* Set analog AGC reference */ -+ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ -+ writereg(state, R367_QAM_FSM_STATE,0x90); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xb1); -+ if(state->symbol_rate>4500000) // 45000000 -+ { -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); ++ writereg(state, R367_QAM_EQU_MAPPER, ++ state->qam_inversion | QAM_MOD_QAM128); ++ /* Set analog AGC reference */ ++ writereg(state, R367_QAM_AGC_PWR_REF_L, 0x76); ++ /* Set digital AGC reference */ ++ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF, 0x00); ++ writereg(state, R367_QAM_FSM_STATE, 0x90); ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN, 0xb1); ++ if (state->symbol_rate > 4500000) { /* 45000000 */ ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN, 0xa7); ++ } else if (state->symbol_rate > 2500000) { /* 25000000 */ ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN, 0xa6); ++ } else { ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN, 0x97); + } -+ else if(state->symbol_rate>2500000) // 25000000 -+ { -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa6); -+ } -+ else -+ { -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0x97); -+ } -+ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x8e); -+ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x7f); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); ++ writereg(state, R367_QAM_EQU_CRL_LD_SEN, 0x8e); ++ writereg(state, R367_QAM_EQU_CRL_LIMITER, 0x7f); ++ writereg(state, R367_QAM_EQU_PNT_GAIN, 0xa7); + break; + case QAM_256: -+ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM256 ); -+ writereg(state, R367_QAM_AGC_PWR_REF_L,0x5a); /* Set analog AGC reference */ -+ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x94); /* Set digital AGC reference */ -+ writereg(state, R367_QAM_FSM_STATE,0xa0); -+ if(state->symbol_rate>4500000) // 45000000 -+ { -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); ++ writereg(state, R367_QAM_EQU_MAPPER, ++ state->qam_inversion | QAM_MOD_QAM256); ++ /* Set analog AGC reference */ ++ writereg(state, R367_QAM_AGC_PWR_REF_L, 0x5a); ++ /* Set digital AGC reference */ ++ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF, 0x94); ++ writereg(state, R367_QAM_FSM_STATE, 0xa0); ++ ++ if (state->symbol_rate > 4500000) { /* 45000000 */ ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN, 0xc1); ++ } else if (state->symbol_rate > 2500000) { /* 25000000 */ ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN, 0xc1); ++ } else { ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN, 0xd1); + } -+ else if(state->symbol_rate>2500000) // 25000000 -+ { -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ } -+ else -+ { -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xd1); -+ } -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); -+ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x85); -+ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN, 0xa7); ++ writereg(state, R367_QAM_EQU_CRL_LD_SEN, 0x85); ++ writereg(state, R367_QAM_EQU_CRL_LIMITER, 0x40); ++ writereg(state, R367_QAM_EQU_PNT_GAIN, 0xa7); + break; + default: + stat = -EINVAL; @@ -10688,7 +7376,6 @@ index 0000000..64f7970 + return stat; +} + -+ +static int QAM_SetSymbolRate(struct stv_state *state) +{ + int status = 0; @@ -10696,91 +7383,89 @@ index 0000000..64f7970 + u32 Corr = 0; + u32 Temp, Temp1, AdpClk; + -+ switch(state->modulation) { ++ switch (state->modulation) { + default: -+ case QAM_16: Corr = 1032; break; -+ case QAM_32: Corr = 954; break; -+ case QAM_64: Corr = 983; break; -+ case QAM_128: Corr = 957; break; -+ case QAM_256: Corr = 948; break; ++ case QAM_16: ++ Corr = 1032; ++ break; ++ case QAM_32: ++ Corr = 954; ++ break; ++ case QAM_64: ++ Corr = 983; ++ break; ++ case QAM_128: ++ Corr = 957; ++ break; ++ case QAM_256: ++ Corr = 948; ++ break; + } + -+ // Transfer ration ++ /* Transfer ration */ + Temp = (256*sr) / state->adc_clock; -+ writereg(state, R367_QAM_EQU_CRL_TFR,(Temp)); ++ writereg(state, R367_QAM_EQU_CRL_TFR, (Temp)); + + /* Symbol rate and SRC gain calculation */ -+ AdpClk = (state->master_clock) / 2000; /* TRL works at half the system clock */ ++ /* TRL works at half the system clock */ ++ AdpClk = (state->master_clock) / 2000; + + Temp = state->symbol_rate; + Temp1 = sr; + -+ if(sr < 2097152) /* 2097152 = 2^21 */ -+ { -+ Temp = ((((sr * 2048) / AdpClk) * 16384 ) / 125 ) * 8; -+ Temp1 = (((((sr * 2048) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 10000000; -+ } -+ else if(sr < 4194304) /* 4194304 = 2**22 */ -+ { -+ Temp = ((((sr * 1024) / AdpClk) * 16384 ) / 125 ) * 16; -+ Temp1 = (((((sr * 1024) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 5000000; -+ } -+ else if(sr < 8388608) /* 8388608 = 2**23 */ -+ { -+ Temp = ((((sr * 512) / AdpClk) * 16384 ) / 125 ) * 32; -+ Temp1 = (((((sr * 512) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 2500000; -+ } -+ else -+ { -+ Temp = ((((sr * 256) / AdpClk) * 16384 ) / 125 ) * 64; -+ Temp1 = (((((sr * 256) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 1250000; ++ if (sr < 2097152) { /* 2097152 = 2^21 */ ++ Temp = ((((sr * 2048) / AdpClk) * 16384) / 125) * 8; ++ Temp1 = (((((sr * 2048) / 439) * 256) / AdpClk) ++ * Corr * 9) / 10000000; ++ } else if (sr < 4194304) { /* 4194304 = 2**22 */ ++ Temp = ((((sr * 1024) / AdpClk) * 16384) / 125) * 16; ++ Temp1 = (((((sr * 1024) / 439) * 256) / AdpClk) ++ * Corr * 9) / 5000000; ++ } else if (sr < 8388608) { /* 8388608 = 2**23 */ ++ Temp = ((((sr * 512) / AdpClk) * 16384) / 125) * 32; ++ Temp1 = (((((sr * 512) / 439) * 256) / AdpClk) ++ * Corr * 9) / 2500000; ++ } else { ++ Temp = ((((sr * 256) / AdpClk) * 16384) / 125) * 64; ++ Temp1 = (((((sr * 256) / 439) * 256) / AdpClk) ++ * Corr * 9) / 1250000; + } + -+ ///* Filters' coefficients are calculated and written into registers only if the filters are enabled */ -+ //if (ChipGetField(hChip,F367qam_ADJ_EN)) // Is disabled from init! -+ //{ -+ // FE_367qam_SetIirAdjacentcoefficient(hChip, MasterClk_Hz, SymbolRate); -+ //} -+ ///* AllPass filter is never used on this IC */ -+ //ChipSetField(hChip,F367qam_ALLPASSFILT_EN,0); // should be disabled from init! ++ writereg(state, R367_QAM_SRC_NCO_LL, (Temp)); ++ writereg(state, R367_QAM_SRC_NCO_LH, (Temp>>8)); ++ writereg(state, R367_QAM_SRC_NCO_HL, (Temp>>16)); ++ writereg(state, R367_QAM_SRC_NCO_HH, (Temp>>24)); + -+ writereg(state, R367_QAM_SRC_NCO_LL,(Temp)); -+ writereg(state, R367_QAM_SRC_NCO_LH,(Temp>>8)); -+ writereg(state, R367_QAM_SRC_NCO_HL,(Temp>>16)); -+ writereg(state, R367_QAM_SRC_NCO_HH,(Temp>>24)); -+ -+ writereg(state, R367_QAM_IQDEM_GAIN_SRC_L,(Temp1)); -+ writereg(state, R367_QAM_IQDEM_GAIN_SRC_H,(Temp1>>8)); ++ writereg(state, R367_QAM_IQDEM_GAIN_SRC_L, (Temp1)); ++ writereg(state, R367_QAM_IQDEM_GAIN_SRC_H, (Temp1>>8)); + return status; +} + -+ +static int QAM_SetDerotFrequency(struct stv_state *state, u32 DerotFrequency) +{ + int status = 0; + u32 Sampled_IF; + + do { -+ //if (DerotFrequency < 1000000) -+ // DerotFrequency = state->adc_clock/4; /* ZIF operation */ + if (DerotFrequency > state->adc_clock) -+ DerotFrequency = DerotFrequency - state->adc_clock; // User Alias ++ /* User Alias */ ++ DerotFrequency = DerotFrequency - state->adc_clock; + -+ Sampled_IF = ((32768 * (DerotFrequency/1000)) / (state->adc_clock/1000)) * 256; -+ if(Sampled_IF > 8388607) ++ Sampled_IF = ((32768 * (DerotFrequency/1000)) ++ / (state->adc_clock/1000)) * 256; ++ if (Sampled_IF > 8388607) + Sampled_IF = 8388607; + + writereg(state, R367_QAM_MIX_NCO_LL, (Sampled_IF)); + writereg(state, R367_QAM_MIX_NCO_HL, (Sampled_IF>>8)); + writereg(state, R367_QAM_MIX_NCO_HH, (Sampled_IF>>16)); -+ } while(0); ++ } while (0); + + return status; +} + -+ -+ -+static int QAM_Start(struct stv_state *state, s32 offsetFreq,s32 IntermediateFrequency) ++static int QAM_Start(struct stv_state *state, s32 offsetFreq, ++ s32 IntermediateFrequency) +{ + int status = 0; + u32 AGCTimeOut = 25; @@ -10791,28 +7476,35 @@ index 0000000..64f7970 + u32 CRLTimeOut; + u8 Temp; + -+ if( state->demod_state != QAMSet ) { -+ writereg(state, R367_DEBUG_LT4,0x00); -+ writereg(state, R367_DEBUG_LT5,0x01); -+ writereg(state, R367_DEBUG_LT6,0x06);// R367_QAM_CTRL_1 -+ writereg(state, R367_DEBUG_LT7,0x03);// R367_QAM_CTRL_2 -+ writereg(state, R367_DEBUG_LT8,0x00); -+ writereg(state, R367_DEBUG_LT9,0x00); ++ if (state->demod_state != QAMSet) { ++ writereg(state, R367_DEBUG_LT4, 0x00); ++ writereg(state, R367_DEBUG_LT5, 0x01); ++ writereg(state, R367_DEBUG_LT6, 0x06); /* R367_QAM_CTRL_1 */ ++ writereg(state, R367_DEBUG_LT7, 0x03); /* R367_QAM_CTRL_2 */ ++ writereg(state, R367_DEBUG_LT8, 0x00); ++ writereg(state, R367_DEBUG_LT9, 0x00); + -+ // Tuner Setup -+ writereg(state, R367_ANADIGCTRL,0x8B); /* Buffer Q disabled, I Enabled, signed ADC */ -+ writereg(state, R367_DUAL_AD12,0x04); /* ADCQ disabled */ ++ /* Tuner Setup */ ++ /* Buffer Q disabled, I Enabled, signed ADC */ ++ writereg(state, R367_ANADIGCTRL, 0x8B); ++ /* ADCQ disabled */ ++ writereg(state, R367_DUAL_AD12, 0x04); + -+ // Clock setup -+ writereg(state, R367_ANACTRL,0x0D); /* PLL bypassed and disabled */ -+ writereg(state, R367_TOPCTRL,0x10); // Set QAM ++ /* Clock setup */ ++ /* PLL bypassed and disabled */ ++ writereg(state, R367_ANACTRL, 0x0D); ++ /* Set QAM */ ++ writereg(state, R367_TOPCTRL, 0x10); + -+ writereg(state, R367_PLLMDIV,27); /* IC runs at 58 MHz with a 27 MHz crystal */ -+ writereg(state, R367_PLLNDIV,232); -+ writereg(state, R367_PLLSETUP,0x18); /* ADC clock is equal to system clock */ ++ /* IC runs at 58 MHz with a 27 MHz crystal */ ++ writereg(state, R367_PLLMDIV, 27); ++ writereg(state, R367_PLLNDIV, 232); ++ /* ADC clock is equal to system clock */ ++ writereg(state, R367_PLLSETUP, 0x18); + + msleep(50); -+ writereg(state, R367_ANACTRL,0x00); /* PLL enabled and used */ ++ /* PLL enabled and used */ ++ writereg(state, R367_ANACTRL, 0x00); + + state->master_clock = 58000000; + state->adc_clock = 58000000; @@ -10826,41 +7518,54 @@ index 0000000..64f7970 + qam_set_modulation(state); + QAM_SetSymbolRate(state); + -+ // Will make problems on low symbol rates ( < 2500000 ) ++ /* Will make problems on low symbol rates ( < 2500000 ) */ + -+ switch(state->modulation) { ++ switch (state->modulation) { + default: -+ case QAM_16: CRLSymbols = 150000; break; -+ case QAM_32: CRLSymbols = 250000; break; -+ case QAM_64: CRLSymbols = 200000; break; -+ case QAM_128: CRLSymbols = 250000; break; -+ case QAM_256: CRLSymbols = 250000; break; ++ case QAM_16: ++ CRLSymbols = 150000; ++ break; ++ case QAM_32: ++ CRLSymbols = 250000; ++ break; ++ case QAM_64: ++ CRLSymbols = 200000; ++ break; ++ case QAM_128: ++ CRLSymbols = 250000; ++ break; ++ case QAM_256: ++ CRLSymbols = 250000; ++ break; + } + -+ CRLTimeOut = (25 * CRLSymbols * (SearchRange/1000)) / (state->symbol_rate/1000); ++ CRLTimeOut = (25 * CRLSymbols * (SearchRange/1000)) ++ / (state->symbol_rate/1000); + CRLTimeOut = (1000 * CRLTimeOut) / state->symbol_rate; -+ if( CRLTimeOut < 50 ) CRLTimeOut = 50; ++ if (CRLTimeOut < 50) ++ CRLTimeOut = 50; + + state->m_FECTimeOut = 20; -+ state->m_DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut; ++ state->m_DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut ++ + EQLTimeOut; + state->m_SignalTimeOut = AGCTimeOut + TRLTimeOut; + -+ // QAM_AGC_ACCUMRSTSEL = 0; -+ readreg(state, R367_QAM_AGC_CTL,&state->m_Save_QAM_AGC_CTL); -+ writereg(state, R367_QAM_AGC_CTL,state->m_Save_QAM_AGC_CTL & ~0x0F); ++ /* QAM_AGC_ACCUMRSTSEL = 0 */ ++ readreg(state, R367_QAM_AGC_CTL, &state->m_Save_QAM_AGC_CTL); ++ writereg(state, R367_QAM_AGC_CTL, state->m_Save_QAM_AGC_CTL & ~0x0F); + -+ // QAM_MODULUSMAP_EN = 0 -+ readreg(state, R367_QAM_EQU_PNT_GAIN,&Temp); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,Temp & ~0x40); ++ /* QAM_MODULUSMAP_EN = 0 */ ++ readreg(state, R367_QAM_EQU_PNT_GAIN, &Temp); ++ writereg(state, R367_QAM_EQU_PNT_GAIN, Temp & ~0x40); + -+ // QAM_SWEEP_EN = 0 -+ readreg(state, R367_QAM_EQU_CTR_LPF_GAIN,&Temp); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,Temp & ~0x08); ++ /* QAM_SWEEP_EN = 0 */ ++ readreg(state, R367_QAM_EQU_CTR_LPF_GAIN, &Temp); ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN, Temp & ~0x08); + + QAM_SetDerotFrequency(state, IntermediateFrequency); + -+ // Release TRL -+ writereg(state, R367_QAM_CTRL_1,0x00); ++ /* Release TRL */ ++ writereg(state, R367_QAM_CTRL_1, 0x00); + + state->IF = IntermediateFrequency; + state->demod_state = QAMStarted; @@ -10868,7 +7573,8 @@ index 0000000..64f7970 + return status; +} + -+static int OFDM_Start(struct stv_state *state, s32 offsetFreq,s32 IntermediateFrequency) ++static int OFDM_Start(struct stv_state *state, s32 offsetFreq, ++ s32 IntermediateFrequency) +{ + int status = 0; + u8 GAIN_SRC1; @@ -10877,29 +7583,34 @@ index 0000000..64f7970 + u8 tmp1; + u8 tmp2; + -+ if ( state->demod_state != OFDMSet ) { -+ // QAM Disable ++ if (state->demod_state != OFDMSet) { ++ /* QAM Disable */ + writereg(state, R367_DEBUG_LT4, 0x00); + writereg(state, R367_DEBUG_LT5, 0x00); -+ writereg(state, R367_DEBUG_LT6, 0x00);// R367_QAM_CTRL_1 -+ writereg(state, R367_DEBUG_LT7, 0x00);// R367_QAM_CTRL_2 ++ writereg(state, R367_DEBUG_LT6, 0x00); /* R367_QAM_CTRL_1 */ ++ writereg(state, R367_DEBUG_LT7, 0x00); /* R367_QAM_CTRL_2 */ + writereg(state, R367_DEBUG_LT8, 0x00); + writereg(state, R367_DEBUG_LT9, 0x00); + -+ // Tuner Setup -+ writereg(state, R367_ANADIGCTRL, 0x89); /* Buffer Q disabled, I Enabled, unsigned ADC */ ++ /* Tuner Setup */ ++ /* Buffer Q disabled, I Enabled, unsigned ADC */ ++ writereg(state, R367_ANADIGCTRL, 0x89); + writereg(state, R367_DUAL_AD12, 0x04); /* ADCQ disabled */ + -+ // Clock setup -+ writereg(state, R367_ANACTRL, 0x0D); /* PLL bypassed and disabled */ -+ writereg(state, R367_TOPCTRL, 0x00); // Set OFDM ++ /* Clock setup */ ++ /* PLL bypassed and disabled */ ++ writereg(state, R367_ANACTRL, 0x0D); ++ writereg(state, R367_TOPCTRL, 0x00); /* Set OFDM */ + -+ writereg(state, R367_PLLMDIV, 1); /* IC runs at 54 MHz with a 27 MHz crystal */ ++ /* IC runs at 54 MHz with a 27 MHz crystal */ ++ writereg(state, R367_PLLMDIV, 1); + writereg(state, R367_PLLNDIV, 8); -+ writereg(state, R367_PLLSETUP, 0x18); /* ADC clock is equal to system clock */ ++ /* ADC clock is equal to system clock */ ++ writereg(state, R367_PLLSETUP, 0x18); + + msleep(50); -+ writereg(state, R367_ANACTRL, 0x00); /* PLL enabled and used */ ++ /* PLL enabled and used */ ++ writereg(state, R367_ANACTRL, 0x00); + + state->master_clock = 54000000; + state->adc_clock = 54000000; @@ -10910,72 +7621,75 @@ index 0000000..64f7970 + state->m_bFirstTimeLock = true; + state->m_DemodLockTime = -1; + -+ // Set inversion in GAIN_SRC1 (fixed from init) -+ // is in GAIN_SRC1, see below ++ /* Set inversion in GAIN_SRC1 (fixed from init) ++ * is in GAIN_SRC1, see below ++ */ + + GAIN_SRC1 = 0xA0; -+ // Bandwidth ++ /* Bandwidth */ + -+ // Fixed values for 54 MHz -+ switch(state->bandwidth) { ++ /* Fixed values for 54 MHz */ ++ switch (state->bandwidth) { + case 0: + case 8000000: -+ // Normrate = 44384; -+ writereg(state, R367_OFDM_TRL_CTL,0x14); -+ writereg(state, R367_OFDM_TRL_NOMRATE1,0xB0); -+ writereg(state, R367_OFDM_TRL_NOMRATE2,0x56); -+ // Gain SRC = 2774 -+ writereg(state, R367_OFDM_GAIN_SRC1,0x0A | GAIN_SRC1); -+ writereg(state, R367_OFDM_GAIN_SRC2,0xD6); ++ /* Normrate = 44384 */ ++ writereg(state, R367_OFDM_TRL_CTL, 0x14); ++ writereg(state, R367_OFDM_TRL_NOMRATE1, 0xB0); ++ writereg(state, R367_OFDM_TRL_NOMRATE2, 0x56); ++ /* Gain SRC = 2774 */ ++ writereg(state, R367_OFDM_GAIN_SRC1, 0x0A | GAIN_SRC1); ++ writereg(state, R367_OFDM_GAIN_SRC2, 0xD6); + break; + case 7000000: -+ // Normrate = 38836; -+ writereg(state, R367_OFDM_TRL_CTL,0x14); -+ writereg(state, R367_OFDM_TRL_NOMRATE1,0xDA); -+ writereg(state, R367_OFDM_TRL_NOMRATE2,0x4B); -+ // Gain SRC = 2427 -+ writereg(state, R367_OFDM_GAIN_SRC1,0x09 | GAIN_SRC1); -+ writereg(state, R367_OFDM_GAIN_SRC2,0x7B); ++ /* Normrate = 38836 */ ++ writereg(state, R367_OFDM_TRL_CTL, 0x14); ++ writereg(state, R367_OFDM_TRL_NOMRATE1, 0xDA); ++ writereg(state, R367_OFDM_TRL_NOMRATE2, 0x4B); ++ /* Gain SRC = 2427 */ ++ writereg(state, R367_OFDM_GAIN_SRC1, 0x09 | GAIN_SRC1); ++ writereg(state, R367_OFDM_GAIN_SRC2, 0x7B); + break; + case 6000000: -+ // Normrate = 33288; -+ writereg(state, R367_OFDM_TRL_CTL,0x14); -+ writereg(state, R367_OFDM_TRL_NOMRATE1,0x04); -+ writereg(state, R367_OFDM_TRL_NOMRATE2,0x41); -+ // Gain SRC = 2080 -+ writereg(state, R367_OFDM_GAIN_SRC1,0x08 | GAIN_SRC1); -+ writereg(state, R367_OFDM_GAIN_SRC2,0x20); ++ /* Normrate = 33288 */ ++ writereg(state, R367_OFDM_TRL_CTL, 0x14); ++ writereg(state, R367_OFDM_TRL_NOMRATE1, 0x04); ++ writereg(state, R367_OFDM_TRL_NOMRATE2, 0x41); ++ /* Gain SRC = 2080 */ ++ writereg(state, R367_OFDM_GAIN_SRC1, 0x08 | GAIN_SRC1); ++ writereg(state, R367_OFDM_GAIN_SRC2, 0x20); + break; + default: + return -EINVAL; -+ break; + } + -+ Derot = ((IntermediateFrequency / 1000) * 65536) / (state->master_clock / 1000); ++ Derot = ((IntermediateFrequency / 1000) * 65536) ++ / (state->master_clock / 1000); + -+ writereg(state, R367_OFDM_INC_DEROT1,(Derot>>8)); -+ writereg(state, R367_OFDM_INC_DEROT2,(Derot)); ++ writereg(state, R367_OFDM_INC_DEROT1, (Derot>>8)); ++ writereg(state, R367_OFDM_INC_DEROT2, (Derot)); + -+ readreg(state, R367_OFDM_SYR_CTL,&SYR_CTL); -+ SYR_CTL &= ~0x78; -+ writereg(state, R367_OFDM_SYR_CTL,SYR_CTL); // EchoPos = 0 ++ readreg(state, R367_OFDM_SYR_CTL, &SYR_CTL); ++ SYR_CTL &= ~0x78; ++ writereg(state, R367_OFDM_SYR_CTL, SYR_CTL); /* EchoPos = 0 */ + + -+ writereg(state, R367_OFDM_COR_MODEGUARD,0x03); // Force = 0, Mode = 0, Guard = 3 ++ /* Force = 0, Mode = 0, Guard = 3 */ ++ writereg(state, R367_OFDM_COR_MODEGUARD, 0x03); + SYR_CTL &= 0x01; -+ writereg(state, R367_OFDM_SYR_CTL,SYR_CTL); // SYR_TR_DIS = 0 ++ writereg(state, R367_OFDM_SYR_CTL, SYR_CTL); /* SYR_TR_DIS = 0 */ + -+ msleep(5); ++ usleep_range(5000, 6000); + -+ writereg(state, R367_OFDM_COR_CTL,0x20); // Start core ++ writereg(state, R367_OFDM_COR_CTL, 0x20); /* Start core */ + -+ // -- Begin M.V. -+ // Reset FEC and Read Solomon -+ readreg(state, R367_OFDM_SFDLYSETH,&tmp1); -+ readreg(state, R367_TSGENERAL,&tmp2); -+ writereg(state, R367_OFDM_SFDLYSETH,tmp1 | 0x08); -+ writereg(state, R367_TSGENERAL,tmp2 | 0x01); -+ // -- End M.V. ++ /* -- Begin M.V. ++ * Reset FEC and Read Solomon ++ */ ++ readreg(state, R367_OFDM_SFDLYSETH, &tmp1); ++ readreg(state, R367_TSGENERAL, &tmp2); ++ writereg(state, R367_OFDM_SFDLYSETH, tmp1 | 0x08); ++ writereg(state, R367_TSGENERAL, tmp2 | 0x01); ++ /* -- End M.V. */ + + state->m_SignalTimeOut = 200; + state->IF = IntermediateFrequency; @@ -10987,88 +7701,22 @@ index 0000000..64f7970 + return status; +} + -+#if 0 -+static int Stop(struct stv_state *state) ++static int QAM_GetSignalToNoise(struct stv_state *state, u16 *snr) +{ -+ int status = 0; -+ -+ switch(state->demod_state) -+ { -+ case QAMStarted: -+ status = writereg(state, R367_QAM_CTRL_1,0x06); -+ state->demod_state = QAMSet; -+ break; -+ case OFDMStarted: -+ status = writereg(state, R367_OFDM_COR_CTL,0x00); -+ state->demod_state = OFDMSet; -+ break; -+ default: -+ break; -+ } -+ return status; -+} -+#endif -+ -+static s32 Log10x100(u32 x) -+{ -+ static u32 LookupTable[100] = { -+ 101157945, 103514217, 105925373, 108392691, 110917482, -+ 113501082, 116144861, 118850223, 121618600, 124451461, // 800.5 - 809.5 -+ 127350308, 130316678, 133352143, 136458314, 139636836, -+ 142889396, 146217717, 149623566, 153108746, 156675107, // 810.5 - 819.5 -+ 160324539, 164058977, 167880402, 171790839, 175792361, -+ 179887092, 184077200, 188364909, 192752491, 197242274, // 820.5 - 829.5 -+ 201836636, 206538016, 211348904, 216271852, 221309471, -+ 226464431, 231739465, 237137371, 242661010, 248313311, // 830.5 - 839.5 -+ 254097271, 260015956, 266072506, 272270131, 278612117, -+ 285101827, 291742701, 298538262, 305492111, 312607937, // 840.5 - 849.5 -+ 319889511, 327340695, 334965439, 342767787, 350751874, -+ 358921935, 367282300, 375837404, 384591782, 393550075, // 850.5 - 859.5 -+ 402717034, 412097519, 421696503, 431519077, 441570447, -+ 451855944, 462381021, 473151259, 484172368, 495450191, // 860.5 - 869.5 -+ 506990708, 518800039, 530884444, 543250331, 555904257, -+ 568852931, 582103218, 595662144, 609536897, 623734835, // 870.5 - 879.5 -+ 638263486, 653130553, 668343918, 683911647, 699841996, -+ 716143410, 732824533, 749894209, 767361489, 785235635, // 880.5 - 889.5 -+ 803526122, 822242650, 841395142, 860993752, 881048873, -+ 901571138, 922571427, 944060876, 966050879, 988553095, // 890.5 - 899.5 -+ }; -+ s32 y; ++ u32 RegValAvg = 0, tmpval; ++ s32 snrval; ++ u8 RegVal[2]; + int i; + -+ if (x == 0) -+ return 0; -+ y = 800; -+ if (x >= 1000000000) { -+ x /= 10; -+ y += 100; -+ } -+ -+ while (x < 100000000) { -+ x *= 10; -+ y -= 100; -+ } -+ i = 0; -+ while (i < 100 && x > LookupTable[i]) -+ i += 1; -+ y += i; -+ return y; -+} -+ -+static int QAM_GetSignalToNoise(struct stv_state *state, s32 *pSignalToNoise) -+{ -+ u32 RegValAvg = 0; -+ u8 RegVal[2]; -+ int status = 0, i; -+ -+ *pSignalToNoise = 0; -+ for (i = 0; i < 10; i += 1 ) { ++ *snr = 0; ++ for (i = 0; i < 10; i += 1) { + readregs(state, R367_QAM_EQU_SNR_LO, RegVal, 2); + RegValAvg += RegVal[0] + 256 * RegVal[1]; + } + if (RegValAvg != 0) { + s32 Power = 1; -+ switch(state->modulation) { ++ ++ switch (state->modulation) { + case QAM_16: + Power = 20480; + break; @@ -11079,136 +7727,56 @@ index 0000000..64f7970 + Power = 21504; + break; + case QAM_128: -+ Power = 23616; ++ Power = 23616; + break; + case QAM_256: -+ Power = 21760; ++ Power = 21760; + break; + default: + break; + } -+ *pSignalToNoise = Log10x100((Power * 320) / RegValAvg); ++ tmpval = (Power * 320) / RegValAvg; ++ snrval = ((tmpval != 0) ? INTLOG10X100(tmpval) : 0); + } else { -+ *pSignalToNoise = 380; ++ snrval = 380; + } -+ return status; ++ ++ *snr = 0xffff & (snrval * 100); ++ return 0; +} + -+static int OFDM_GetSignalToNoise(struct stv_state *state, s32 *pSignalToNoise) ++static int OFDM_GetSignalToNoise(struct stv_state *state, u16 *snr) +{ + u8 CHC_SNR = 0; + -+ int status = readreg(state, R367_OFDM_CHC_SNR, &CHC_SNR); -+ if (status >= 0) { -+ // Note: very unclear documentation on this. -+ // Datasheet states snr = CHC_SNR/4 dB -> way to high values! -+ // Software snr = ( 1000 * CHC_SNR ) / 8 / 32 / 10; -> to low values -+ // Comment in SW states this should be ( 1000 * CHC_SNR ) / 4 / 32 / 10; for the 367 -+ // 361/362 Datasheet: snr = CHC_SNR/8 dB -> this looks best -+ *pSignalToNoise = ( (s32)CHC_SNR * 10) / 8; ++ *snr = 0; ++ ++ if (readreg(state, R367_OFDM_CHC_SNR, &CHC_SNR) >= 0) { ++ /* Note: very unclear documentation on this. ++ * Datasheet states snr = CHC_SNR/4 dB -> way to high values! ++ * Software snr = ( 1000 * CHC_SNR ) / 8 / 32 / 10; ++ * -> to low values ++ * Comment in SW states this should be ++ * ( 1000 * CHC_SNR ) / 4 / 32 / 10; for the 367 ++ * 361/362 Datasheet: snr = CHC_SNR/8 dB -> this looks best ++ */ ++ *snr = ((u16)CHC_SNR * 1000) / 8; ++ return 0; + } -+ //printk("SNR %d\n", *pSignalToNoise); -+ return status; ++ return -EINVAL; +} + -+#if 0 -+static int DVBC_GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) -+{ -+ *pQuality = 100; -+ return 0; -+}; -+ -+static int DVBT_GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) -+{ -+ static s32 QE_SN[] = { -+ 51, // QPSK 1/2 -+ 69, // QPSK 2/3 -+ 79, // QPSK 3/4 -+ 89, // QPSK 5/6 -+ 97, // QPSK 7/8 -+ 108, // 16-QAM 1/2 -+ 131, // 16-QAM 2/3 -+ 146, // 16-QAM 3/4 -+ 156, // 16-QAM 5/6 -+ 160, // 16-QAM 7/8 -+ 165, // 64-QAM 1/2 -+ 187, // 64-QAM 2/3 -+ 202, // 64-QAM 3/4 -+ 216, // 64-QAM 5/6 -+ 225, // 64-QAM 7/8 -+ }; -+ u8 TPS_Received[2]; -+ int Constellation; -+ int CodeRate; -+ s32 SignalToNoiseRel, BERQuality; -+ -+ *pQuality = 0; -+ readregs(state, R367_OFDM_TPS_RCVD2, TPS_Received, sizeof(TPS_Received)); -+ Constellation = TPS_Received[0] & 0x03; -+ CodeRate = TPS_Received[1] & 0x07; -+ -+ if( Constellation > 2 || CodeRate > 5 ) -+ return -1; -+ SignalToNoiseRel = SignalToNoise - QE_SN[Constellation * 5 + CodeRate]; -+ BERQuality = 100; -+ -+ if( SignalToNoiseRel < -70 ) -+ *pQuality = 0; -+ else if( SignalToNoiseRel < 30 ) { -+ *pQuality = ((SignalToNoiseRel + 70) * BERQuality)/100; -+ } else -+ *pQuality = BERQuality; -+ return 0; -+}; -+ -+static s32 DVBCQuality(struct stv_state *state, s32 SignalToNoise) -+{ -+ s32 SignalToNoiseRel = 0; -+ s32 Quality = 0; -+ s32 BERQuality = 100; -+ -+ switch(state->modulation) { -+ case QAM_16: SignalToNoiseRel = SignalToNoise - 200 ; break; -+ case QAM_32: SignalToNoiseRel = SignalToNoise - 230 ; break; // Not in NorDig -+ case QAM_64: SignalToNoiseRel = SignalToNoise - 260 ; break; -+ case QAM_128: SignalToNoiseRel = SignalToNoise - 290 ; break; -+ case QAM_256: SignalToNoiseRel = SignalToNoise - 320 ; break; -+ } -+ -+ if( SignalToNoiseRel < -70 ) Quality = 0; -+ else if( SignalToNoiseRel < 30 ) -+ { -+ Quality = ((SignalToNoiseRel + 70) * BERQuality)/100; -+ } -+ else -+ Quality = BERQuality; -+ -+ return Quality; -+} -+ -+static int GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) -+{ -+ *pQuality = 0; -+ switch(state->demod_state) -+ { -+ case QAMStarted: -+ *pQuality = DVBCQuality(state, SignalToNoise); -+ break; -+ case OFDMStarted: -+ return DVBT_GetQuality(state, SignalToNoise, pQuality); -+ } -+ return 0; -+}; -+#endif -+ +static int attach_init(struct stv_state *state) +{ + int stat = 0; + + stat = readreg(state, R367_ID, &state->ID); -+ if ( stat < 0 || state->ID != 0x60 ) ++ if (stat < 0 || state->ID != 0x60) + return -ENODEV; -+ printk("stv0367 found\n"); ++ ++ pr_info("%s demod with ChipID %02X found at adr %02X on %s\n", ++ state->frontend.ops.info.name, state->ID, state->adr, ++ dev_name(&state->i2c->dev)); + + writereg(state, R367_TOPCTRL, 0x10); + write_init_table(state, base_init); @@ -11226,87 +7794,76 @@ index 0000000..64f7970 + writereg(state, R367_OFDM_TRL_NOMRATE2, 0x56); + writereg(state, R367_OFDM_FEPATH_CFG, 0x0); + -+ // OFDM TS Setup ++ /* OFDM TS Setup */ + + writereg(state, R367_OFDM_TSCFGH, 0x70); + writereg(state, R367_OFDM_TSCFGM, 0xC0); + writereg(state, R367_OFDM_TSCFGL, 0x20); -+ writereg(state, R367_OFDM_TSSPEED, 0x40); // Fixed at 54 MHz -+ //writereg(state, R367_TSTBUS, 0x80); // Invert CLK ++ writereg(state, R367_OFDM_TSSPEED, 0x40); /* Fixed at 54 MHz */ + + writereg(state, R367_OFDM_TSCFGH, 0x71); -+ writereg(state, R367_OFDM_TSCFGH, 0x70); ++ ++ if (state->cont_clock) ++ writereg(state, R367_OFDM_TSCFGH, 0xf0); ++ else ++ writereg(state, R367_OFDM_TSCFGH, 0x70); + + writereg(state, R367_TOPCTRL, 0x10); + -+ // Also needed for QAM -+ writereg(state, R367_OFDM_AGC12C, 0x01); // AGC Pin setup ++ /* Also needed for QAM */ ++ writereg(state, R367_OFDM_AGC12C, 0x01); /* AGC Pin setup */ + -+ writereg(state, R367_OFDM_AGCCTRL1, 0x8A); // ++ writereg(state, R367_OFDM_AGCCTRL1, 0x8A); + -+ // QAM TS setup, note exact format also depends on descrambler settings -+ writereg(state, R367_QAM_OUTFORMAT_0, 0x85); // Inverted Clock, Swap, serial -+ // writereg(state, R367_QAM_OUTFORMAT_1, 0x00); // ++ /* QAM TS setup, note exact format also depends on descrambler */ ++ /* settings */ ++ /* Inverted Clock, Swap, serial */ ++ writereg(state, R367_QAM_OUTFORMAT_0, 0x85); + -+ // Clock setup ++ /* Clock setup */ + writereg(state, R367_ANACTRL, 0x0D); /* PLL bypassed and disabled */ + -+ if( state->master_clock == 58000000 ) { -+ writereg(state, R367_PLLMDIV,27); /* IC runs at 58 MHz with a 27 MHz crystal */ -+ writereg(state, R367_PLLNDIV,232); ++ if (state->master_clock == 58000000) { ++ /* IC runs at 58 MHz with a 27 MHz crystal */ ++ writereg(state, R367_PLLMDIV, 27); ++ writereg(state, R367_PLLNDIV, 232); + } else { -+ writereg(state, R367_PLLMDIV,1); /* IC runs at 54 MHz with a 27 MHz crystal */ -+ writereg(state, R367_PLLNDIV,8); ++ /* IC runs at 54 MHz with a 27 MHz crystal */ ++ writereg(state, R367_PLLMDIV, 1); ++ writereg(state, R367_PLLNDIV, 8); + } -+ writereg(state, R367_PLLSETUP, 0x18); /* ADC clock is equal to system clock */ + -+ // Tuner setup -+ writereg(state, R367_ANADIGCTRL, 0x8b); /* Buffer Q disabled, I Enabled, signed ADC */ ++ /* ADC clock is equal to system clock */ ++ writereg(state, R367_PLLSETUP, 0x18); ++ ++ /* Tuner setup */ ++ /* Buffer Q disabled, I Enabled, signed ADC */ ++ writereg(state, R367_ANADIGCTRL, 0x8b); + writereg(state, R367_DUAL_AD12, 0x04); /* ADCQ disabled */ + -+ writereg(state, R367_QAM_FSM_SNR2_HTH, 0x23); /* Improves the C/N lock limit */ ++ /* Improves the C/N lock limit */ ++ writereg(state, R367_QAM_FSM_SNR2_HTH, 0x23); + writereg(state, R367_QAM_IQ_QAM, 0x01); /* ZIF/IF Automatic mode */ -+ writereg(state, R367_QAM_EQU_FFE_LEAKAGE, 0x83); /* Improving burst noise performances */ -+ writereg(state, R367_QAM_IQDEM_ADJ_EN, 0x05); /* Improving ACI performances */ ++ /* Improving burst noise performances */ ++ writereg(state, R367_QAM_EQU_FFE_LEAKAGE, 0x83); ++ /* Improving ACI performances */ ++ writereg(state, R367_QAM_IQDEM_ADJ_EN, 0x05); + + writereg(state, R367_ANACTRL, 0x00); /* PLL enabled and used */ + + writereg(state, R367_I2CRPT, state->I2CRPT); -+ state->demod_state = QAMSet; ++ state->demod_state = QAMSet; + return stat; +} + -+#ifdef USE_API3 -+static void c_release(struct dvb_frontend* fe) -+#else -+static void release(struct dvb_frontend* fe) -+#endif ++static void release(struct dvb_frontend *fe) +{ -+ struct stv_state *state=fe->demodulator_priv; -+ printk("%s\n", __FUNCTION__); ++ struct stv_state *state = fe->demodulator_priv; ++ ++ pr_info("%s()\n", __func__); + kfree(state); +} + -+#ifdef USE_API3 -+static int c_init (struct dvb_frontend *fe) -+{ -+ struct stv_state *state=fe->demodulator_priv; -+ -+ if (mutex_trylock(&state->ctlock)==0) -+ return -EBUSY; -+ state->omode = OM_DVBC; -+ return 0; -+} -+ -+static int c_sleep(struct dvb_frontend* fe) -+{ -+ struct stv_state *state=fe->demodulator_priv; -+ -+ mutex_unlock(&state->ctlock); -+ return 0; -+} -+#endif -+ +static int gate_ctrl(struct dvb_frontend *fe, int enable) +{ + struct stv_state *state = fe->demodulator_priv; @@ -11315,23 +7872,11 @@ index 0000000..64f7970 + if (enable) + i2crpt |= 0x80; + if (writereg(state, R367_I2CRPT, i2crpt) < 0) -+ return -1; ++ return -EIO; + state->I2CRPT = i2crpt; + return 0; +} + -+#if 0 -+static int c_track(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -+{ -+ return DVBFE_ALGO_SEARCH_AGAIN; -+} -+#endif -+ -+#if 0 -+int (*set_property)(struct dvb_frontend* fe, struct dtv_property* tvp); -+int (*get_property)(struct dvb_frontend* fe, struct dtv_property* tvp); -+#endif -+ +static int ofdm_lock(struct stv_state *state) +{ + int status = 0; @@ -11346,30 +7891,28 @@ index 0000000..64f7970 + u8 TSStatus; + + msleep(state->m_SignalTimeOut); -+ readreg(state, R367_OFDM_STATUS,&OFDM_Status); ++ readreg(state, R367_OFDM_STATUS, &OFDM_Status); + + if (!(OFDM_Status & 0x40)) -+ return -1; -+ //printk("lock 1\n"); ++ return -EIO; + -+ readreg(state, R367_OFDM_SYR_STAT,&SYR_STAT); ++ readreg(state, R367_OFDM_SYR_STAT, &SYR_STAT); + FFTMode = (SYR_STAT & 0x0C) >> 2; + -+ switch(FFTMode) -+ { -+ case 0: // 2K ++ switch (FFTMode) { ++ case 0: /* 2K */ + DemodTimeOut = 10; + FECTimeOut = 150; + TSTimeOut = 125; + CPAMPMin = 20; + break; -+ case 1: // 8K ++ case 1: /* 8K */ + DemodTimeOut = 55; + FECTimeOut = 600; + TSTimeOut = 500; + CPAMPMin = 80; + break; -+ case 2: // 4K ++ case 2: /* 4K */ + DemodTimeOut = 40; + FECTimeOut = 300; + TSTimeOut = 250; @@ -11377,103 +7920,68 @@ index 0000000..64f7970 + break; + } + state->m_OFDM_FFTMode = FFTMode; -+ readreg(state, R367_OFDM_PPM_CPAMP_DIR,&CPAMPValue); ++ readreg(state, R367_OFDM_PPM_CPAMP_DIR, &CPAMPValue); + msleep(DemodTimeOut); + { -+ // Release FEC and Read Solomon Reset ++ /* Release FEC and Read Solomon Reset */ + u8 tmp1; + u8 tmp2; -+ readreg(state, R367_OFDM_SFDLYSETH,&tmp1); -+ readreg(state, R367_TSGENERAL,&tmp2); -+ writereg(state, R367_OFDM_SFDLYSETH,tmp1 & ~0x08); -+ writereg(state, R367_TSGENERAL,tmp2 & ~0x01); ++ ++ readreg(state, R367_OFDM_SFDLYSETH, &tmp1); ++ readreg(state, R367_TSGENERAL, &tmp2); ++ writereg(state, R367_OFDM_SFDLYSETH, tmp1 & ~0x08); ++ writereg(state, R367_TSGENERAL, tmp2 & ~0x01); + } + msleep(FECTimeOut); -+ if( (OFDM_Status & 0x98) != 0x98 ) -+ ;//return -1; -+ //printk("lock 2\n"); ++ if ((OFDM_Status & 0x98) != 0x98) ++ ;/* return -1; */ ++ /* printk("lock 2\n"); */ + + { + u8 Guard = (SYR_STAT & 0x03); -+ if(Guard < 2) -+ { ++ ++ if (Guard < 2) { + u8 tmp; -+ readreg(state, R367_OFDM_SYR_CTL,&tmp); -+ writereg(state, R367_OFDM_SYR_CTL,tmp & ~0x04); // Clear AUTO_LE_EN -+ readreg(state, R367_OFDM_SYR_UPDATE,&tmp); -+ writereg(state, R367_OFDM_SYR_UPDATE,tmp & ~0x10); // Clear SYR_FILTER ++ ++ readreg(state, R367_OFDM_SYR_CTL, &tmp); ++ /* Clear AUTO_LE_EN */ ++ writereg(state, R367_OFDM_SYR_CTL, tmp & ~0x04); ++ readreg(state, R367_OFDM_SYR_UPDATE, &tmp); ++ /* Clear SYR_FILTER */ ++ writereg(state, R367_OFDM_SYR_UPDATE, tmp & ~0x10); + } else { + u8 tmp; -+ readreg(state, R367_OFDM_SYR_CTL,&tmp); -+ writereg(state, R367_OFDM_SYR_CTL,tmp | 0x04); // Set AUTO_LE_EN -+ readreg(state, R367_OFDM_SYR_UPDATE,&tmp); -+ writereg(state, R367_OFDM_SYR_UPDATE,tmp | 0x10); // Set SYR_FILTER ++ ++ readreg(state, R367_OFDM_SYR_CTL, &tmp); ++ /* Set AUTO_LE_EN */ ++ writereg(state, R367_OFDM_SYR_CTL, tmp | 0x04); ++ readreg(state, R367_OFDM_SYR_UPDATE, &tmp); ++ /* Set SYR_FILTER */ ++ writereg(state, R367_OFDM_SYR_UPDATE, tmp | 0x10); + } + -+ // apply Sfec workaround if 8K 64QAM CR!=1/2 -+ if( FFTMode == 1) -+ { ++ /* apply Sfec workaround if 8K 64QAM CR!=1/2 */ ++ if (FFTMode == 1) { + u8 tmp[2]; ++ + readregs(state, R367_OFDM_TPS_RCVD2, tmp, 2); -+ if( ((tmp[0] & 0x03) == 0x02) && (( tmp[1] & 0x07 ) != 0) ) -+ { -+ writereg(state, R367_OFDM_SFDLYSETH,0xc0); -+ writereg(state, R367_OFDM_SFDLYSETM,0x60); -+ writereg(state, R367_OFDM_SFDLYSETL,0x00); -+ } -+ else -+ { -+ writereg(state, R367_OFDM_SFDLYSETH,0x00); ++ if (((tmp[0] & 0x03) == 0x02) && ((tmp[1] & 0x07) != 0)) { ++ writereg(state, R367_OFDM_SFDLYSETH, 0xc0); ++ writereg(state, R367_OFDM_SFDLYSETM, 0x60); ++ writereg(state, R367_OFDM_SFDLYSETL, 0x00); ++ } else { ++ writereg(state, R367_OFDM_SFDLYSETH, 0x00); + } + } + } + msleep(TSTimeOut); -+ readreg(state, R367_OFDM_TSSTATUS,&TSStatus); -+ if( (TSStatus & 0x80) != 0x80 ) -+ return -1; -+ //printk("lock 3\n"); ++ readreg(state, R367_OFDM_TSSTATUS, &TSStatus); ++ if ((TSStatus & 0x80) != 0x80) ++ return -EIO; ++ + return status; +} + -+ -+#ifdef USE_API3 -+static int set_parameters(struct dvb_frontend *fe, -+ struct dvb_frontend_parameters *p) -+{ -+ int stat; -+ struct stv_state *state = fe->demodulator_priv; -+ u32 OF = 0; -+ u32 IF; -+ -+ if (fe->ops.tuner_ops.set_params) -+ fe->ops.tuner_ops.set_params(fe, p); -+ -+ switch (state->omode) { -+ case OM_DVBC: -+ case OM_QAM_ITU_C: -+ state->modulation = p->u.qam.modulation; -+ state->symbol_rate = p->u.qam.symbol_rate; -+ break; -+ case OM_DVBT: -+ switch (p->u.ofdm.bandwidth) { -+ case BANDWIDTH_AUTO: -+ case BANDWIDTH_8_MHZ: -+ state->bandwidth = 8000000; -+ break; -+ case BANDWIDTH_7_MHZ: -+ state->bandwidth = 7000000; -+ break; -+ case BANDWIDTH_6_MHZ: -+ state->bandwidth = 6000000; -+ break; -+ default: -+ return -EINVAL; -+ } -+ break; -+ default: -+ return -EINVAL; -+ } -+#else +static int set_parameters(struct dvb_frontend *fe) +{ + int stat; @@ -11483,209 +7991,48 @@ index 0000000..64f7970 + + switch (fe->dtv_property_cache.delivery_system) { + case SYS_DVBC_ANNEX_A: -+ state->omode = OM_DVBC; + /* symbol rate 0 might cause an oops */ + if (fe->dtv_property_cache.symbol_rate == 0) { -+ printk(KERN_ERR "stv0367dd: Invalid symbol rate\n"); ++ pr_err("Invalid symbol rate\n"); + return -EINVAL; + } + break; + case SYS_DVBT: -+ state->omode = OM_DVBT; + break; + default: + return -EINVAL; + } ++ ++ state->delsys = fe->dtv_property_cache.delivery_system; ++ + if (fe->ops.tuner_ops.set_params) + fe->ops.tuner_ops.set_params(fe); + state->modulation = fe->dtv_property_cache.modulation; + state->symbol_rate = fe->dtv_property_cache.symbol_rate; + state->bandwidth = fe->dtv_property_cache.bandwidth_hz; -+#endif + fe->ops.tuner_ops.get_if_frequency(fe, &IF); -+ //fe->ops.tuner_ops.get_frequency(fe, &IF); + -+ switch(state->omode) { -+ case OM_DVBT: ++ switch (state->delsys) { ++ case SYS_DVBT: + stat = OFDM_Start(state, OF, IF); + ofdm_lock(state); + break; -+ case OM_DVBC: -+ case OM_QAM_ITU_C: ++ case SYS_DVBC_ANNEX_A: + stat = QAM_Start(state, OF, IF); + break; + default: + stat = -EINVAL; + } -+ //printk("%s IF=%d OF=%d done\n", __FUNCTION__, IF, OF); ++ + return stat; +} + -+#if 0 -+static int c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -+{ -+ //struct stv_state *state = fe->demodulator_priv; -+ //printk("%s\n", __FUNCTION__); -+ return 0; -+} -+ -+static int OFDM_GetLockStatus(struct stv_state *state, LOCK_STATUS* pLockStatus, s32 Time) -+{ -+ int status = STATUS_SUCCESS; -+ u8 OFDM_Status; -+ s32 DemodTimeOut = 0; -+ s32 FECTimeOut = 0; -+ s32 TSTimeOut = 0; -+ u8 CPAMPMin = 255; -+ u8 CPAMPValue; -+ bool SYRLock; -+ u8 SYR_STAT; -+ u8 FFTMode; -+ u8 TSStatus; -+ -+ readreg(state, R367_OFDM_STATUS,&OFDM_Status); -+ -+ SYRLock = (OFDM_Status & 0x40) != 0; -+ -+ if( Time > m_SignalTimeOut && !SYRLock ) -+ { -+ *pLockStatus = NEVER_LOCK; -+ break; -+ } -+ -+ if( !SYRLock ) break; -+ -+ *pLockStatus = SIGNAL_PRESENT; -+ -+ // Check Mode -+ -+ readreg(state, R367_OFDM_SYR_STAT,&SYR_STAT); -+ FFTMode = (SYR_STAT & 0x0C) >> 2; -+ -+ switch(FFTMode) -+ { -+ case 0: // 2K -+ DemodTimeOut = 10; -+ FECTimeOut = 150; -+ TSTimeOut = 125; -+ CPAMPMin = 20; -+ break; -+ case 1: // 8K -+ DemodTimeOut = 55; -+ FECTimeOut = 600; -+ TSTimeOut = 500; -+ CPAMPMin = 80; -+ break; -+ case 2: // 4K -+ DemodTimeOut = 40; -+ FECTimeOut = 300; -+ TSTimeOut = 250; -+ CPAMPMin = 30; -+ break; -+ } -+ -+ m_OFDM_FFTMode = FFTMode; -+ -+ if( m_DemodTimeOut == 0 && m_bFirstTimeLock ) -+ { -+ m_DemodTimeOut = Time + DemodTimeOut; -+ //break; -+ } -+ -+ readreg(state, R367_OFDM_PPM_CPAMP_DIR,&CPAMPValue); -+ -+ if( Time <= m_DemodTimeOut && CPAMPValue < CPAMPMin ) -+ { -+ break; -+ } -+ -+ if( CPAMPValue < CPAMPMin && m_bFirstTimeLock ) -+ { -+ // initiate retry -+ *pLockStatus = NEVER_LOCK; -+ break; -+ } -+ -+ if( CPAMPValue < CPAMPMin ) break; -+ -+ *pLockStatus = DEMOD_LOCK; -+ -+ if( m_FECTimeOut == 0 && m_bFirstTimeLock ) -+ { -+ // Release FEC and Read Solomon Reset -+ u8 tmp1; -+ u8 tmp2; -+ readreg(state, R367_OFDM_SFDLYSETH,&tmp1); -+ readreg(state, R367_TSGENERAL,&tmp2); -+ writereg(state, R367_OFDM_SFDLYSETH,tmp1 & ~0x08); -+ writereg(state, R367_TSGENERAL,tmp2 & ~0x01); -+ -+ m_FECTimeOut = Time + FECTimeOut; -+ } -+ -+ // Wait for TSP_LOCK, LK, PRF -+ if( (OFDM_Status & 0x98) != 0x98 ) -+ { -+ if( Time > m_FECTimeOut ) *pLockStatus = NEVER_LOCK; -+ break; -+ } -+ -+ if( m_bFirstTimeLock && m_TSTimeOut == 0) -+ { -+ u8 Guard = (SYR_STAT & 0x03); -+ if(Guard < 2) -+ { -+ u8 tmp; -+ readreg(state, R367_OFDM_SYR_CTL,&tmp); -+ writereg(state, R367_OFDM_SYR_CTL,tmp & ~0x04); // Clear AUTO_LE_EN -+ readreg(state, R367_OFDM_SYR_UPDATE,&tmp); -+ writereg(state, R367_OFDM_SYR_UPDATE,tmp & ~0x10); // Clear SYR_FILTER -+ } else { -+ u8 tmp; -+ readreg(state, R367_OFDM_SYR_CTL,&tmp); -+ writereg(state, R367_OFDM_SYR_CTL,tmp | 0x04); // Set AUTO_LE_EN -+ readreg(state, R367_OFDM_SYR_UPDATE,&tmp); -+ writereg(state, R367_OFDM_SYR_UPDATE,tmp | 0x10); // Set SYR_FILTER -+ } -+ -+ // apply Sfec workaround if 8K 64QAM CR!=1/2 -+ if( FFTMode == 1) -+ { -+ u8 tmp[2]; -+ readreg(state, R367_OFDM_TPS_RCVD2,tmp,2); -+ if( ((tmp[0] & 0x03) == 0x02) && (( tmp[1] & 0x07 ) != 0) ) -+ { -+ writereg(state, R367_OFDM_SFDLYSETH,0xc0); -+ writereg(state, R367_OFDM_SFDLYSETM,0x60); -+ writereg(state, R367_OFDM_SFDLYSETL,0x00); -+ } -+ else -+ { -+ writereg(state, R367_OFDM_SFDLYSETH,0x00); -+ } -+ } -+ -+ m_TSTimeOut = Time + TSTimeOut; -+ } -+ readreg(state, R367_OFDM_TSSTATUS,&TSStatus); -+ if( (TSStatus & 0x80) != 0x80 ) -+ { -+ if( Time > m_TSTimeOut ) *pLockStatus = NEVER_LOCK; -+ break; -+ } -+ *pLockStatus = MPEG_LOCK; -+ m_bFirstTimeLock = false; -+ return status; -+} -+ -+#endif -+ -+static int read_status(struct dvb_frontend *fe, fe_status_t *status) ++static int read_status(struct dvb_frontend *fe, enum fe_status *status) +{ + struct stv_state *state = fe->demodulator_priv; -+ *status=0; ++ *status = 0; + -+ switch(state->demod_state) { ++ switch (state->demod_state) { + case QAMStarted: + { + u8 FEC_Lock; @@ -11693,15 +8040,22 @@ index 0000000..64f7970 + + readreg(state, R367_QAM_FSM_STS, &QAM_Lock); + QAM_Lock &= 0x0F; -+ if (QAM_Lock >10) -+ *status|=0x07; -+ readreg(state, R367_QAM_FEC_STATUS,&FEC_Lock); ++ if (QAM_Lock > 10) ++ *status |= (FE_HAS_SIGNAL ++ | FE_HAS_CARRIER ++ | FE_HAS_VITERBI); ++ readreg(state, R367_QAM_FEC_STATUS, &FEC_Lock); + if (FEC_Lock&2) -+ *status|=0x1f; ++ *status |= (FE_HAS_SIGNAL ++ | FE_HAS_CARRIER ++ | FE_HAS_VITERBI ++ | FE_HAS_SYNC ++ | FE_HAS_LOCK); + if (state->m_bFirstTimeLock) { + state->m_bFirstTimeLock = false; -+ // QAM_AGC_ACCUMRSTSEL to Tracking; -+ writereg(state, R367_QAM_AGC_CTL, state->m_Save_QAM_AGC_CTL); ++ /* QAM_AGC_ACCUMRSTSEL to Tracking */ ++ writereg(state, R367_QAM_AGC_CTL, ++ state->m_Save_QAM_AGC_CTL); + } + break; + } @@ -11717,15 +8071,23 @@ index 0000000..64f7970 + *status |= FE_HAS_SIGNAL; + + if ((OFDM_Status & 0x98) == 0x98) -+ *status|=0x0f; ++ *status |= (FE_HAS_SIGNAL ++ | FE_HAS_CARRIER ++ | FE_HAS_VITERBI ++ | FE_HAS_SYNC); + + if (TSStatus & 0x80) -+ *status |= 0x1f; ++ *status |= (FE_HAS_SIGNAL ++ | FE_HAS_CARRIER ++ | FE_HAS_VITERBI ++ | FE_HAS_SYNC ++ | FE_HAS_LOCK); + break; + } + default: + break; + } ++ + return 0; +} + @@ -11735,11 +8097,10 @@ index 0000000..64f7970 + u32 err; + u8 cnth, cntm, cntl; + -+#if 1 + readreg(state, R367_OFDM_SFERRCNTH, &cnth); + + if (cnth & 0x80) { -+ *ber = state->ber; ++ *ber = state->ber; + return 0; + } + @@ -11747,20 +8108,7 @@ index 0000000..64f7970 + readreg(state, R367_OFDM_SFERRCNTL, &cntl); + + err = ((cnth & 0x7f) << 16) | (cntm << 8) | cntl; -+ -+#if 0 -+ { -+ u64 err64; -+ err64 = (u64) err; -+ err64 *= 1000000000ULL; -+ err64 >>= 21; -+ err = err64; -+ } -+#endif -+#else -+ readreg(state, R367_OFDM_ERRCNT1HM, &cnth); + -+#endif + *ber = state->ber = err; + return 0; +} @@ -11776,7 +8124,6 @@ index 0000000..64f7970 + readreg(state, R367_QAM_BERT_2, &cntl); + readreg(state, R367_QAM_BERT_3, &cntm); + err = (cntm << 8) | cntl; -+ //printk("err %04x\n", err); + state->ber = err; + writereg(state, R367_QAM_BERT_1, 0x27); + } @@ -11807,21 +8154,20 @@ index 0000000..64f7970 + +static int read_snr(struct dvb_frontend *fe, u16 *snr) +{ -+ struct stv_state *state = fe->demodulator_priv; -+ s32 snr2 = 0; ++ struct stv_state *state = fe->demodulator_priv; + -+ switch(state->demod_state) { ++ *snr = 0; ++ ++ switch (state->demod_state) { + case QAMStarted: -+ QAM_GetSignalToNoise(state, &snr2); -+ break; ++ return QAM_GetSignalToNoise(state, snr); + case OFDMStarted: -+ OFDM_GetSignalToNoise(state, &snr2); -+ break; ++ return OFDM_GetSignalToNoise(state, snr); + default: + break; + } -+ *snr = snr2&0xffff; -+ return 0; ++ ++ return -EINVAL; +} + +static int read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) @@ -11830,7 +8176,7 @@ index 0000000..64f7970 + u8 errl, errm, errh; + u8 val; + -+ switch(state->demod_state) { ++ switch (state->demod_state) { + case QAMStarted: + readreg(state, R367_QAM_RS_COUNTER_4, &errl); + readreg(state, R367_QAM_RS_COUNTER_5, &errm); @@ -11842,7 +8188,7 @@ index 0000000..64f7970 + readreg(state, R367_OFDM_ERRCNT1H, &errh); + readreg(state, R367_OFDM_ERRCNT1M, &errl); + readreg(state, R367_OFDM_ERRCNT1L, &errm); -+ state->ucblocks = (errh <<16) | (errm << 8) | errl; ++ state->ucblocks = (errh << 16) | (errm << 8) | errl; + } + *ucblocks = state->ucblocks; + break; @@ -11856,13 +8202,12 @@ index 0000000..64f7970 +static int c_get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *sets) +{ -+ sets->min_delay_ms=3000; -+ sets->max_drift=0; -+ sets->step_size=0; ++ sets->min_delay_ms = 3000; ++ sets->max_drift = 0; ++ sets->step_size = 0; + return 0; +} + -+#ifndef USE_API3 +static int get_tune_settings(struct dvb_frontend *fe, + struct dvb_frontend_tune_settings *sets) +{ @@ -11875,114 +8220,62 @@ index 0000000..64f7970 + return -EINVAL; + } +} -+#endif + -+#ifdef USE_API3 -+static void t_release(struct dvb_frontend* fe) -+{ -+ //struct stv_state *state=fe->demodulator_priv; -+ //printk("%s\n", __FUNCTION__); -+ //kfree(state); -+} -+ -+static int t_init (struct dvb_frontend *fe) -+{ -+ struct stv_state *state=fe->demodulator_priv; -+ if (mutex_trylock(&state->ctlock)==0) -+ return -EBUSY; -+ state->omode = OM_DVBT; -+ return 0; -+} -+ -+static int t_sleep(struct dvb_frontend* fe) -+{ -+ struct stv_state *state=fe->demodulator_priv; -+ mutex_unlock(&state->ctlock); -+ return 0; -+} -+#endif -+ -+#if 0 -+static int t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) ++static int get_frontend(struct dvb_frontend *fe, ++ struct dtv_frontend_properties *p) +{ + //struct stv_state *state = fe->demodulator_priv; -+ //printk("%s\n", __FUNCTION__); ++ enum fe_status status = 0; ++ int tmp; ++ u16 snr = 0, strength = 0; ++ u32 ber = 0, ucblocks = 0; ++ ++ tmp = read_status(fe, &status); ++ ++ p->strength.len = 1; ++ p->cnr.len = 1; ++ p->post_bit_error.len = 1; ++ p->block_error.len = 1; ++ ++ if (!(status & FE_HAS_LOCK)) { ++ p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ return 0; ++ } ++ ++ if (read_snr(fe, &snr)) ++ p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ else { ++ p->cnr.stat[0].scale = FE_SCALE_DECIBEL; ++ p->cnr.stat[0].svalue = snr; ++ } ++ ++ if (read_signal_strength(fe, &strength)) ++ p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ else { ++ p->strength.stat[0].scale = FE_SCALE_RELATIVE; ++ p->strength.stat[0].svalue = strength; ++ } ++ ++ if (read_ber(fe, &ber)) ++ p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ else { ++ p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; ++ p->post_bit_error.stat[0].uvalue = ber; ++ } ++ ++ if (read_ucblocks(fe, &ucblocks)) ++ p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ else { ++ p->block_error.stat[0].scale = FE_SCALE_COUNTER; ++ p->block_error.stat[0].uvalue = ucblocks; ++ } ++ + return 0; +} + -+static enum dvbfe_algo algo(struct dvb_frontend *fe) -+{ -+ return DVBFE_ALGO_CUSTOM; -+} -+#endif -+ -+#ifdef USE_API3 -+static struct dvb_frontend_ops c_ops = { -+ .info = { -+ .name = "STV0367 DVB-C", -+ .type = FE_QAM, -+ .frequency_stepsize = 62500, -+ .frequency_min = 47000000, -+ .frequency_max = 862000000, -+ .symbol_rate_min = 870000, -+ .symbol_rate_max = 11700000, -+ .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | -+ FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO -+ }, -+ .release = c_release, -+ .init = c_init, -+ .sleep = c_sleep, -+ .i2c_gate_ctrl = gate_ctrl, -+ -+ .get_tune_settings = c_get_tune_settings, -+ -+ .read_status = read_status, -+ .read_ber = read_ber, -+ .read_signal_strength = read_signal_strength, -+ .read_snr = read_snr, -+ .read_ucblocks = read_ucblocks, -+ -+#if 1 -+ .set_frontend = set_parameters, -+#else -+ .get_frontend_algo = algo, -+ .search = search, -+#endif -+}; -+ -+static struct dvb_frontend_ops t_ops = { -+ .info = { -+ .name = "STV0367 DVB-T", -+ .type = FE_OFDM, -+ .frequency_min = 47125000, -+ .frequency_max = 865000000, -+ .frequency_stepsize = 166667, -+ .frequency_tolerance = 0, -+ .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | -+ FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | -+ FE_CAN_FEC_AUTO | -+ FE_CAN_QAM_16 | FE_CAN_QAM_64 | -+ FE_CAN_QAM_AUTO | -+ FE_CAN_TRANSMISSION_MODE_AUTO | -+ FE_CAN_GUARD_INTERVAL_AUTO | -+ FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | -+ FE_CAN_MUTE_TS -+ }, -+ .release = t_release, -+ .init = t_init, -+ .sleep = t_sleep, -+ .i2c_gate_ctrl = gate_ctrl, -+ -+ .set_frontend = set_parameters, -+ -+ .read_status = read_status, -+ .read_ber = read_ber, -+ .read_signal_strength = read_signal_strength, -+ .read_snr = read_snr, -+ .read_ucblocks = read_ucblocks, -+}; -+ -+#else + +static struct dvb_frontend_ops common_ops = { + .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT }, @@ -12011,46 +8304,38 @@ index 0000000..64f7970 + .get_tune_settings = get_tune_settings, + + .set_frontend = set_parameters, ++ .get_frontend = get_frontend, + + .read_status = read_status, -+ .read_ber = read_ber, -+ .read_signal_strength = read_signal_strength, -+ .read_snr = read_snr, -+ .read_ucblocks = read_ucblocks, +}; -+#endif + + -+static void init_state(struct stv_state *state, struct stv0367_cfg *cfg) ++static void init_state(struct stv_state *state, struct stv0367dd_cfg *cfg) +{ + u32 ulENARPTLEVEL = 5; + u32 ulQAMInversion = 2; -+ state->omode = OM_NONE; ++ ++ state->delsys = SYS_UNDEFINED; + state->adr = cfg->adr; ++ state->cont_clock = cfg->cont_clock; + + mutex_init(&state->mutex); + mutex_init(&state->ctlock); + -+#ifdef USE_API3 -+ memcpy(&state->c_frontend.ops, &c_ops, sizeof(struct dvb_frontend_ops)); -+ memcpy(&state->t_frontend.ops, &t_ops, sizeof(struct dvb_frontend_ops)); -+ state->c_frontend.demodulator_priv = state; -+ state->t_frontend.demodulator_priv = state; -+#else -+ memcpy(&state->frontend.ops, &common_ops, sizeof(struct dvb_frontend_ops)); ++ memcpy(&state->frontend.ops, &common_ops, ++ sizeof(struct dvb_frontend_ops)); ++ + state->frontend.demodulator_priv = state; -+#endif + + state->master_clock = 58000000; + state->adc_clock = 58000000; + state->I2CRPT = 0x08 | ((ulENARPTLEVEL & 0x07) << 4); -+ state->qam_inversion = ((ulQAMInversion & 3) << 6 ); ++ state->qam_inversion = ((ulQAMInversion & 3) << 6); + state->demod_state = Off; +} + -+ -+struct dvb_frontend *stv0367_attach(struct i2c_adapter *i2c, struct stv0367_cfg *cfg, -+ struct dvb_frontend **fe_t) ++struct dvb_frontend *stv0367dd_attach(struct i2c_adapter *i2c, ++ struct stv0367dd_cfg *cfg, struct dvb_frontend **fe_t) +{ + struct stv_state *state = NULL; + @@ -12061,73 +8346,78 @@ index 0000000..64f7970 + state->i2c = i2c; + init_state(state, cfg); + -+ if (attach_init(state)<0) ++ if (attach_init(state) < 0) + goto error; -+#ifdef USE_API3 -+ *fe_t = &state->t_frontend; -+ return &state->c_frontend; -+#else + return &state->frontend; -+#endif + +error: -+ printk("stv0367: not found\n"); ++ pr_err("No supported demodulator found at adr %02X on %s\n", ++ cfg->adr, dev_name(&i2c->dev)); ++ + kfree(state); + return NULL; +} -+ ++EXPORT_SYMBOL(stv0367dd_attach); + +MODULE_DESCRIPTION("STV0367DD driver"); +MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); +MODULE_LICENSE("GPL"); -+ -+EXPORT_SYMBOL(stv0367_attach); -+ -+ -+ diff --git a/drivers/media/dvb-frontends/stv0367dd.h b/drivers/media/dvb-frontends/stv0367dd.h new file mode 100644 -index 0000000..665d4c8 +index 0000000..2c0b426 --- /dev/null +++ b/drivers/media/dvb-frontends/stv0367dd.h -@@ -0,0 +1,17 @@ +@@ -0,0 +1,31 @@ +#ifndef _STV0367DD_H_ +#define _STV0367DD_H_ + +#include +#include + -+struct stv0367_cfg { ++struct stv0367dd_cfg { + u8 adr; + u32 xtal; -+ u32 ts_mode; ++ u8 parallel; ++ u8 cont_clock; +}; + ++#if IS_REACHABLE(CONFIG_DVB_STV0367DD) + -+extern struct dvb_frontend *stv0367_attach(struct i2c_adapter *i2c, -+ struct stv0367_cfg *cfg, -+ struct dvb_frontend **fe_t); -+#endif ++extern struct dvb_frontend *stv0367dd_attach(struct i2c_adapter *i2c, ++ struct stv0367dd_cfg *cfg, ++ struct dvb_frontend **fe_t); ++ ++#else ++ ++static inline struct dvb_frontend *stv0367dd_attach(struct i2c_adapter *i2c, ++ struct stv0367dd_cfg *cfg, struct dvb_frontend **fe_t) ++{ ++ pr_warn("%s: driver disabled by Kconfig\n", __func__); ++ return NULL; ++} ++ ++#endif /* CONFIG_DVB_STV0367DD */ ++ ++#endif /* _STV0367DD_H_ */ diff --git a/drivers/media/dvb-frontends/stv0367dd_regs.h b/drivers/media/dvb-frontends/stv0367dd_regs.h new file mode 100644 -index 0000000..eec0f57 +index 0000000..4f22ae6 --- /dev/null +++ b/drivers/media/dvb-frontends/stv0367dd_regs.h -@@ -0,0 +1,3431 @@ -+// @DVB-C/DVB-T STMicroelectronics STV0367 register defintions -+// Author Manfred Völkel, Februar 2011 -+// (c) 2010 DigitalDevices GmbH Germany. All rights reserved -+ -+// $Id: DD_STV0367Register.h 357 2011-04-27 02:39:13Z manfred $ -+ -+/* ======================================================================= -+ -- Registers Declaration -+ -- ------------------------- -+ -- Each register (R367_XXXXX) is defined by its address (2 bytes). -+ -- -+ -- Each field (F367_XXXXX)is defined as follow: -+ -- [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] -+ ======================================================================= */ +@@ -0,0 +1,3429 @@ ++/* @DVB-C/DVB-T STMicroelectronics STV0367 register defintions ++ * Author Manfred Voelkel, Februar 2011 ++ * (c) 2010 DigitalDevices GmbH Germany. All rights reserved ++ * ++ * ====================================================================== ++ * -- Registers Declaration ++ * -- ------------------------- ++ * -- Each register (R367_XXXXX) is defined by its address (2 bytes). ++ * -- ++ * -- Each field (F367_XXXXX)is defined as follow: ++ * -- [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] ++ * ====================================================================== ++ */ + +/* ID */ +#define R367_ID 0xF000 @@ -13941,7 +10231,7 @@ index 0000000..eec0f57 + /* SELOUT */ +#define R367_OFDM_SELOUT 0xF252 +#define F367_OFDM_EN_SYNC 0xF2520080 -+#define F367_OFDM_EN_TBUSDEMAP 0xF2520040 ++#define F367_OFDM_EN_TBUSDEMAP 0xF2520040 +#define F367_OFDM_SELOUT_5 0xF2520020 +#define F367_OFDM_SELOUT_4 0xF2520010 +#define F367_OFDM_TSTSYNCHRO_MODE 0xF2520002 @@ -13978,7 +10268,7 @@ index 0000000..eec0f57 +#define R367_OFDM_TSTSFERR 0xF256 +#define F367_OFDM_TSTSTERR_7 0xF2560080 +#define F367_OFDM_TSTSTERR_6 0xF2560040 -+#define F367_OFDM_TSTSTERR_5 0xF2560020 ++#define F367_OFDM_TSTSTERR_5 0xF2560020 +#define F367_OFDM_TSTSTERR_4 0xF2560010 +#define F367_OFDM_SFECTRACEBACK_MODE 0xF2560008 +#define F367_OFDM_SFEC_NCONVPROG 0xF2560004 @@ -13997,7 +10287,7 @@ index 0000000..eec0f57 +#define F367_OFDM_DILSF_DBBHEADER 0xF2590080 +#define F367_OFDM_TSTTSSF_DISBUG 0xF2590040 +#define F367_OFDM_TSTTSSF_NOBADSTART 0xF2590020 -+#define F367_OFDM_TSTTSSF_SELECT 0xF259001F ++#define F367_OFDM_TSTTSSF_SELECT 0xF259001F + + /* TSTTSSF3 */ +#define R367_OFDM_TSTTSSF3 0xF25A @@ -14020,14 +10310,14 @@ index 0000000..eec0f57 +#define F367_OFDM_TSTTS_FRFORCEPKT 0xF25C0004 +#define F367_OFDM_DESCR_NOTAUTO 0xF25C0002 +#define F367_OFDM_TSTTSEN 0xF25C0001 -+ ++ + /* TSTTS2 */ +#define R367_OFDM_TSTTS2 0xF25D +#define F367_OFDM_DIL_DBBHEADER 0xF25D0080 +#define F367_OFDM_TSTTS_NOBADXXX 0xF25D0040 +#define F367_OFDM_TSFIFO_DELSPEEDUP 0xF25D0020 +#define F367_OFDM_TSTTS_SELECT 0xF25D001F -+ ++ + /* TSTTS3 */ +#define R367_OFDM_TSTTS3 0xF25E +#define F367_OFDM_TSTTS_NOPKTGAIN 0xF25E0080 @@ -15544,96 +11834,18 @@ index 0000000..eec0f57 +/* T_O_ID_3 */ +#define R367_QAM_T_O_ID_3 0xF4D3 +#define F367_QAM_TS_ID_I_H 0xF4D300FF -+ -diff --git a/drivers/media/dvb-frontends/stv090x.c b/drivers/media/dvb-frontends/stv090x.c -index 0b2a934..ba93e7b 100644 ---- a/drivers/media/dvb-frontends/stv090x.c -+++ b/drivers/media/dvb-frontends/stv090x.c -@@ -3562,6 +3562,7 @@ static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status) - return 0; - } - -+#if 0 - static int stv090x_read_per(struct dvb_frontend *fe, u32 *per) - { - struct stv090x_state *state = fe->demodulator_priv; -@@ -3612,6 +3613,27 @@ err: - dprintk(FE_ERROR, 1, "I/O error"); - return -1; - } -+#endif -+ -+static int stv090x_read_ber(struct dvb_frontend *fe, u32 *ber) -+{ -+ struct stv090x_state *state = fe->demodulator_priv; -+ u32 reg, h, m, l; -+ -+ /* Counter 1: S1: 0x75 BER, S2: 0x67 PER */ -+ reg = STV090x_READ_DEMOD(state, ERRCNT12); -+ h = STV090x_GETFIELD_Px(reg, ERR_CNT12_FIELD); -+ -+ reg = STV090x_READ_DEMOD(state, ERRCNT11); -+ m = STV090x_GETFIELD_Px(reg, ERR_CNT11_FIELD); -+ -+ reg = STV090x_READ_DEMOD(state, ERRCNT10); -+ l = STV090x_GETFIELD_Px(reg, ERR_CNT10_FIELD); -+ -+ *ber = ((h << 16) | (m << 8) | l); -+ -+ return 0; -+} - - static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val) - { -@@ -3732,6 +3754,26 @@ static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr) - return 0; - } - -+static int stv090x_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -+{ -+ struct stv090x_state *state = fe->demodulator_priv; -+ u32 reg, h, m, l; -+ -+ /* Counter 2: 0xc1 TS error count */ -+ reg = STV090x_READ_DEMOD(state, ERRCNT22); -+ h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD); -+ -+ reg = STV090x_READ_DEMOD(state, ERRCNT21); -+ m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD); -+ -+ reg = STV090x_READ_DEMOD(state, ERRCNT20); -+ l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD); -+ -+ *ucblocks = ((h << 16) | (m << 8) | l); -+ -+ return 0; -+} -+ - static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) - { - struct stv090x_state *state = fe->demodulator_priv; -@@ -4914,9 +4956,10 @@ static struct dvb_frontend_ops stv090x_ops = { - - .search = stv090x_search, - .read_status = stv090x_read_status, -- .read_ber = stv090x_read_per, -+ .read_ber = stv090x_read_ber, - .read_signal_strength = stv090x_read_signal_strength, - .read_snr = stv090x_read_cnr, -+ .read_ucblocks = stv090x_read_ucblocks, - }; - - diff --git a/drivers/media/dvb-frontends/stv0910.c b/drivers/media/dvb-frontends/stv0910.c new file mode 100644 -index 0000000..d247932 +index 0000000..730ba5f --- /dev/null +++ b/drivers/media/dvb-frontends/stv0910.c -@@ -0,0 +1,1371 @@ +@@ -0,0 +1,1526 @@ +/* + * Driver for the ST STV0910 DVB-S/S2 demodulator. + * -+ * Copyright (C) 2014 Digital Devices GmbH ++ * Copyright (C) 2014-2015 Ralph Metzler ++ * Marcus Metzler ++ * developed for Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License @@ -15653,6 +11865,9 @@ index 0000000..d247932 + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + ++#undef pr_fmt ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ +#include +#include +#include @@ -15660,13 +11875,14 @@ index 0000000..d247932 +#include +#include +#include -+#include +#include + ++#include "dvb_math.h" +#include "dvb_frontend.h" +#include "stv0910.h" +#include "stv0910_regs.h" + ++#define INTLOG10X100(x) ((u32) (((u64) intlog10(x) * 100) >> 24)) + +#define TUNING_DELAY 200 +#define BER_SRC_S 0x20 @@ -15676,7 +11892,6 @@ index 0000000..d247932 + +enum ReceiveMode { Mode_None, Mode_DVBS, Mode_DVBS2, Mode_Auto }; + -+ +enum DVBS2_FECType { DVBS2_64K, DVBS2_16K }; + +enum DVBS2_ModCod { @@ -15733,6 +11948,7 @@ index 0000000..d247932 + u16 regoff; + u8 i2crpt; + u8 tscfgh; ++ u8 tsgeneral; + u8 tsspeed; + unsigned long tune_time; + @@ -15763,9 +11979,9 @@ index 0000000..d247932 + u8 Data; +}; + -+struct SLookupSNTable { -+ s16 SignalToNoise; -+ u16 RefValue; ++struct SLookup { ++ s16 Value; ++ u16 RegValue; +}; + +static inline int i2c_write(struct i2c_adapter *adap, u8 adr, @@ -15774,7 +11990,13 @@ index 0000000..d247932 + struct i2c_msg msg = {.addr = adr, .flags = 0, + .buf = data, .len = len}; + -+ return (i2c_transfer(adap, &msg, 1) == 1) ? 0 : -1; ++ if (i2c_transfer(adap, &msg, 1) != 1) { ++ pr_warn("i2c_write_error ([%02x] %04x: %02x)\n", ++ adr, (data[0] << 8) | data[1], ++ (len > 2 ? data[2] : 0)); ++ return -EREMOTEIO; ++ } ++ return 0; +} + +static int i2c_write_reg16(struct i2c_adapter *adap, u8 adr, u16 reg, u8 val) @@ -15789,32 +12011,27 @@ index 0000000..d247932 + return i2c_write_reg16(state->base->i2c, state->base->adr, reg, val); +} + -+static inline int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr, -+ u16 reg, u8 *val) ++static inline int i2c_read_regs16(struct i2c_adapter *adapter, u8 adr, ++ u16 reg, u8 *val, int count) +{ + u8 msg[2] = {reg >> 8, reg & 0xff}; + struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, + .buf = msg, .len = 2}, + {.addr = adr, .flags = I2C_M_RD, -+ .buf = val, .len = 1 } }; -+ return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; ++ .buf = val, .len = count } }; ++ ++ if (i2c_transfer(adapter, msgs, 2) != 2) { ++ pr_warn("i2c_read error ([%02x] %04x)\n", ++ adr, reg); ++ return -EREMOTEIO; ++ } ++ return 0; +} + +static int read_reg(struct stv *state, u16 reg, u8 *val) +{ -+ return i2c_read_reg16(state->base->i2c, state->base->adr, reg, val); -+} -+ -+ -+static inline int i2c_read_regs16(struct i2c_adapter *adapter, u8 adr, -+ u16 reg, u8 *val, int len) -+{ -+ u8 msg[2] = {reg >> 8, reg & 0xff}; -+ struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, -+ .buf = msg, .len = 2}, -+ {.addr = adr, .flags = I2C_M_RD, -+ .buf = val, .len = len } }; -+ return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; ++ return i2c_read_regs16(state->base->i2c, state->base->adr, ++ reg, val, 1); +} + +static int read_regs(struct stv *state, u16 reg, u8 *val, int len) @@ -15823,7 +12040,7 @@ index 0000000..d247932 + reg, val, len); +} + -+struct SLookupSNTable S1_SN_Lookup[] = { ++struct SLookup S1_SN_Lookup[] = { + { 0, 9242 }, /*C/N= 0dB*/ + { 05, 9105 }, /*C/N=0.5dB*/ + { 10, 8950 }, /*C/N=1.0dB*/ @@ -15880,7 +12097,7 @@ index 0000000..d247932 + { 510, 425 } /*C/N=51.0dB*/ +}; + -+struct SLookupSNTable S2_SN_Lookup[] = { ++struct SLookup S2_SN_Lookup[] = { + { -30, 13950 }, /*C/N=-2.5dB*/ + { -25, 13580 }, /*C/N=-2.5dB*/ + { -20, 13150 }, /*C/N=-2.0dB*/ @@ -15944,11 +12161,13 @@ index 0000000..d247932 +}; + +/********************************************************************* -+Tracking carrier loop carrier QPSK 1/4 to 8PSK 9/10 long Frame -+*********************************************************************/ ++ * Tracking carrier loop carrier QPSK 1/4 to 8PSK 9/10 long Frame ++ *********************************************************************/ +static u8 S2CarLoop[] = { + /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff -+ 20MPon 20MPoff 30MPon 30MPoff*/ ++ * 20MPon 20MPoff 30MPon 30MPoff ++ */ ++ + /* FE_QPSK_14 */ + 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x2A, 0x1C, 0x3A, 0x3B, + /* FE_QPSK_13 */ @@ -15985,10 +12204,13 @@ index 0000000..d247932 + 0x0C, 0x1C, 0x0C, 0x3B, 0x2B, 0x1B, 0x3A, 0x0B, 0x2A, 0x2A, + + /********************************************************************** -+ Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame -+ **********************************************************************/ -+ /*Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon -+ 20MPoff 30MPon 30MPoff*/ ++ * Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame ++ **********************************************************************/ ++ ++ /* Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon ++ * 20MPoff 30MPon 30MPoff ++ */ ++ + /* FE_16APSK_23 */ + 0x0A, 0x0A, 0x0A, 0x0A, 0x1A, 0x0A, 0x39, 0x0A, 0x29, 0x0A, + /* FE_16APSK_34 */ @@ -16017,6 +12239,7 @@ index 0000000..d247932 + enum FE_STV0910_ModCod ModCod, u32 Pilots) +{ + int i = 0; ++ + if (ModCod >= FE_32APSK_910) + i = ((int)FE_32APSK_910 - (int)FE_QPSK_14) * 10; + else if (ModCod >= FE_QPSK_14) @@ -16083,7 +12306,7 @@ index 0000000..d247932 +static int GetSignalParameters(struct stv *state) +{ + if (!state->Started) -+ return -1; ++ return -EINVAL; + + if (state->ReceiveMode == Mode_DVBS2) { + u8 tmp; @@ -16179,14 +12402,49 @@ index 0000000..d247932 + return 0; +} + ++static s32 TableLookup(struct SLookup *Table, ++ int TableSize, u16 RegValue) ++{ ++ s32 Value; ++ int imin = 0; ++ int imax = TableSize - 1; ++ int i; ++ s32 RegDiff; ++ ++ /* Assumes Table[0].RegValue > Table[imax].RegValue */ ++ if (RegValue >= Table[0].RegValue) ++ Value = Table[0].Value; ++ else if (RegValue <= Table[imax].RegValue) ++ Value = Table[imax].Value; ++ else { ++ while (imax-imin > 1) { ++ i = (imax + imin) / 2; ++ if ((Table[imin].RegValue >= RegValue) && ++ (RegValue >= Table[i].RegValue)) ++ imax = i; ++ else ++ imin = i; ++ } ++ ++ RegDiff = Table[imax].RegValue - Table[imin].RegValue; ++ Value = Table[imin].Value; ++ if (RegDiff != 0) ++ Value += ((s32)(RegValue - Table[imin].RegValue) * ++ (s32)(Table[imax].Value ++ - Table[imin].Value)) ++ / (RegDiff); ++ } ++ ++ return Value; ++} ++ +static int GetSignalToNoise(struct stv *state, s32 *SignalToNoise) +{ -+ int i; + u8 Data0; + u8 Data1; + u16 Data; + int nLookup; -+ struct SLookupSNTable *Lookup; ++ struct SLookup *Lookup; + + *SignalToNoise = 0; + @@ -16205,25 +12463,7 @@ index 0000000..d247932 + Lookup = S1_SN_Lookup; + } + Data = (((u16)Data1) << 8) | (u16) Data0; -+ if (Data > Lookup[0].RefValue) { -+ *SignalToNoise = Lookup[0].SignalToNoise; -+ } else if (Data <= Lookup[nLookup-1].RefValue) { -+ *SignalToNoise = Lookup[nLookup-1].SignalToNoise; -+ } else { -+ for (i = 0; i < nLookup - 1; i += 1) { -+ if (Data <= Lookup[i].RefValue && -+ Data > Lookup[i+1].RefValue) { -+ *SignalToNoise = -+ (s32)(Lookup[i].SignalToNoise) + -+ ((s32)(Data - Lookup[i].RefValue) * -+ (s32)(Lookup[i+1].SignalToNoise - -+ Lookup[i].SignalToNoise)) / -+ ((s32)(Lookup[i+1].RefValue) - -+ (s32)(Lookup[i].RefValue)); -+ break; -+ } -+ } -+ } ++ *SignalToNoise = TableLookup(Lookup, nLookup, Data); + return 0; +} + @@ -16236,7 +12476,7 @@ index 0000000..d247932 + Regs, 3); + + if (status) -+ return -1; ++ return -EINVAL; + + if ((Regs[0] & 0x80) == 0) { + state->LastBERDenominator = 1 << ((state->BERScale * 2) + @@ -16309,7 +12549,7 @@ index 0000000..d247932 + Regs, 3); + + if (status) -+ return -1; ++ return -EINVAL; + + if ((Regs[0] & 0x80) == 0) { + state->LastBERDenominator = @@ -16343,7 +12583,6 @@ index 0000000..d247932 + switch (state->ReceiveMode) { + case Mode_DVBS: + return GetBitErrorRateS(state, BERNumerator, BERDenominator); -+ break; + case Mode_DVBS2: + return GetBitErrorRateS2(state, BERNumerator, BERDenominator); + default: @@ -16352,11 +12591,6 @@ index 0000000..d247932 + return 0; +} + -+static int init(struct dvb_frontend *fe) -+{ -+ return 0; -+} -+ +static int set_mclock(struct stv *state, u32 MasterClock) +{ + u32 idf = 1; @@ -16417,7 +12651,6 @@ index 0000000..d247932 + fvco = (quartz * 2 * ndiv) / idf; + state->base->mclk = fvco / (2 * odf) * 1000000; + -+ pr_info("ndiv = %d, MasterClock = %d\n", ndiv, state->base->mclk); + return 0; +} + @@ -16484,8 +12717,6 @@ index 0000000..d247932 + ((symb >> 8) & 0x7F)); + write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF)); + -+ pr_info("symb = %u\n", symb); -+ + state->DEMOD |= 0x80; + write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->DEMOD); + @@ -16558,11 +12789,10 @@ index 0000000..d247932 + state->Started = 0; + + if (read_reg(state, RSTV0910_MID, &id) < 0) -+ return -1; ++ return -ENODEV; + + if (id != 0x51) + return -EINVAL; -+ pr_info("Found STV0910 id=0x%02x\n", id); + + /* Configure the I2C repeater to off */ + write_reg(state, RSTV0910_P1_I2CRPT, 0x24); @@ -16574,7 +12804,7 @@ index 0000000..d247932 + write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */ + write_reg(state, RSTV0910_PADCFG, 0x05); /* RF AGC Pads Dev = 05 */ + write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */ -+ write_reg(state, RSTV0910_TSGENERAL, 0x00); /* TSGENERAL */ ++ write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */ + write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */ + write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */ + @@ -16585,27 +12815,27 @@ index 0000000..d247932 + set_mclock(state, 135000000); + + /* TS output */ -+ write_reg(state, RSTV0910_P1_TSCFGH , state->tscfgh | 0x01); -+ write_reg(state, RSTV0910_P1_TSCFGH , state->tscfgh); -+ write_reg(state, RSTV0910_P1_TSCFGM , 0xC0); /* Manual speed */ -+ write_reg(state, RSTV0910_P1_TSCFGL , 0x20); ++ write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01); ++ write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh); ++ write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */ ++ write_reg(state, RSTV0910_P1_TSCFGL, 0x20); + + /* Speed = 67.5 MHz */ -+ write_reg(state, RSTV0910_P1_TSSPEED , state->tsspeed); ++ write_reg(state, RSTV0910_P1_TSSPEED, state->tsspeed); + -+ write_reg(state, RSTV0910_P2_TSCFGH , state->tscfgh | 0x01); -+ write_reg(state, RSTV0910_P2_TSCFGH , state->tscfgh); -+ write_reg(state, RSTV0910_P2_TSCFGM , 0xC0); /* Manual speed */ -+ write_reg(state, RSTV0910_P2_TSCFGL , 0x20); ++ write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01); ++ write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh); ++ write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */ ++ write_reg(state, RSTV0910_P2_TSCFGL, 0x20); + + /* Speed = 67.5 MHz */ -+ write_reg(state, RSTV0910_P2_TSSPEED , state->tsspeed); ++ write_reg(state, RSTV0910_P2_TSSPEED, state->tsspeed); + + /* Reset stream merger */ -+ write_reg(state, RSTV0910_P1_TSCFGH , state->tscfgh | 0x01); -+ write_reg(state, RSTV0910_P2_TSCFGH , state->tscfgh | 0x01); -+ write_reg(state, RSTV0910_P1_TSCFGH , state->tscfgh); -+ write_reg(state, RSTV0910_P2_TSCFGH , state->tscfgh); ++ write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01); ++ write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01); ++ write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh); ++ write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh); + + write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt); + write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt); @@ -16645,7 +12875,6 @@ index 0000000..d247932 + + state->base->count--; + if (state->base->count == 0) { -+ pr_info("remove STV base\n"); + list_del(&state->base->stvlist); + kfree(state->base); + } @@ -16669,8 +12898,75 @@ index 0000000..d247932 + return stat; +} + ++static int read_snr(struct dvb_frontend *fe, u16 *snr) ++{ ++ struct stv *state = fe->demodulator_priv; ++ s32 SNR; + -+static int read_status(struct dvb_frontend *fe, fe_status_t *status) ++ *snr = 0; ++ if (GetSignalToNoise(state, &SNR)) ++ return -EIO; ++ ++ *snr = 100 * SNR; ++ ++ return 0; ++} ++ ++static int read_ber(struct dvb_frontend *fe, u32 *ber, u32 *n, u32 *d) ++{ ++ struct stv *state = fe->demodulator_priv; ++ ++ *n = 0; ++ *d = 1; ++ ++ GetBitErrorRate(state, n, d); ++ if (d) ++ *ber = *n / *d; ++ else ++ *ber = 0; ++ ++ return 0; ++} ++ ++static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) ++{ ++ struct stv *state = fe->demodulator_priv; ++ u8 Reg[2]; ++ s32 bbgain; ++ s32 Power = 0; ++ int i; ++ ++ read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, Reg, 2); ++ ++ *strength = (((u32) Reg[0]) << 8) | Reg[1]; ++ ++ for (i = 0; i < 5; i += 1) { ++ read_regs(state, RSTV0910_P2_POWERI + state->regoff, Reg, 2); ++ Power += (u32) Reg[0] * (u32) Reg[0] ++ + (u32) Reg[1] * (u32) Reg[1]; ++ usleep_range(3000, 4000); ++ } ++ Power /= 5; ++ ++ bbgain = (465 - INTLOG10X100(Power)) * 10; ++ ++ if (fe->ops.tuner_ops.get_rf_strength) ++ fe->ops.tuner_ops.get_rf_strength(fe, strength); ++ else ++ *strength = 0; ++ ++ if (bbgain < (s32) *strength) ++ *strength -= bbgain; ++ else ++ *strength = 0; ++ ++ if (*strength > 0) ++ *strength = 10 * (s64) (s16) *strength - 108750; ++ ++ return 0; ++} ++ ++static int read_status(struct dvb_frontend *fe, enum fe_status *status) +{ + struct stv *state = fe->demodulator_priv; + u8 DmdState = 0; @@ -16691,11 +12987,15 @@ index 0000000..d247932 + return 0; + } + -+ *status |= 0x0f; ++ *status |= (FE_HAS_SIGNAL ++ | FE_HAS_CARRIER ++ | FE_HAS_VITERBI ++ | FE_HAS_SYNC); ++ + if (state->ReceiveMode == Mode_None) { + state->ReceiveMode = CurReceiveMode; + state->DemodLockTime = jiffies; -+ state->FirstTimeLock = 0; ++ state->FirstTimeLock = 1; + + write_reg(state, RSTV0910_P2_TSCFGH + state->regoff, + state->tscfgh); @@ -16708,12 +13008,14 @@ index 0000000..d247932 + if (DmdState & 0x40) { + if (state->ReceiveMode == Mode_DVBS2) { + u8 PDELStatus; ++ + read_reg(state, + RSTV0910_P2_PDELSTATUS1 + state->regoff, + &PDELStatus); + FECLock = (PDELStatus & 0x02) != 0; + } else { + u8 VStatus; ++ + read_reg(state, + RSTV0910_P2_VSTATUSVIT + state->regoff, + &VStatus); @@ -16724,7 +13026,7 @@ index 0000000..d247932 + if (!FECLock) + return 0; + -+ *status |= 0x10; ++ *status |= FE_HAS_LOCK; + + if (state->FirstTimeLock) { + u8 tmp; @@ -16734,7 +13036,8 @@ index 0000000..d247932 + + if (state->ReceiveMode == Mode_DVBS2) { + /* FSTV0910_P2_MANUALSX_ROLLOFF, -+ FSTV0910_P2_MANUALS2_ROLLOFF = 0 */ ++ * FSTV0910_P2_MANUALS2_ROLLOFF = 0 ++ */ + state->DEMOD &= ~0x84; + write_reg(state, RSTV0910_P2_DEMOD + state->regoff, + state->DEMOD); @@ -16765,8 +13068,9 @@ index 0000000..d247932 + } + /*Reset the Total packet counter */ + write_reg(state, RSTV0910_P2_FBERCPT4 + state->regoff, 0x00); -+ /*Reset the packet Error counter2 (and Set it to -+ infinit error count mode )*/ ++ /* Reset the packet Error counter2 (and Set it to ++ * infinit error count mode ) ++ */ + write_reg(state, RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1); + + TrackingOptimization(state); @@ -16774,9 +13078,117 @@ index 0000000..d247932 + return 0; +} + ++static int get_frontend(struct dvb_frontend *fe, ++ struct dtv_frontend_properties *p) ++{ ++ struct stv *state = fe->demodulator_priv; ++ enum fe_status status; ++ u16 snr = 0, strength = 0; ++ u32 ber = 0, bernom = 0, berdenom = 0; ++ u8 tmp; ++ ++ if (state->ReceiveMode == Mode_DVBS2) { ++ u32 mc; ++ enum fe_modulation modcod2mod[0x20] = { ++ QPSK, QPSK, QPSK, QPSK, ++ QPSK, QPSK, QPSK, QPSK, ++ QPSK, QPSK, QPSK, QPSK, ++ PSK_8, PSK_8, PSK_8, PSK_8, ++ PSK_8, PSK_8, APSK_16, APSK_16, ++ APSK_16, APSK_16, APSK_16, APSK_16, ++ APSK_32, APSK_32, APSK_32, APSK_32, ++ APSK_32, ++ }; ++ enum fe_code_rate modcod2fec[0x20] = { ++ FEC_NONE, FEC_1_4, FEC_1_3, FEC_2_5, ++ FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4, ++ FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10, ++ FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6, ++ FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4, ++ FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10, ++ FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9, ++ FEC_9_10 ++ }; ++ read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp); ++ mc = ((tmp & 0x7c) >> 2); ++ p->pilot = (tmp & 0x01) ? PILOT_ON : PILOT_OFF; ++ p->modulation = modcod2mod[mc]; ++ p->fec_inner = modcod2fec[mc]; ++ } else if (state->ReceiveMode == Mode_DVBS) { ++ read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp); ++ switch (tmp & 0x1F) { ++ case 0x0d: ++ p->fec_inner = FEC_1_2; ++ break; ++ case 0x12: ++ p->fec_inner = FEC_2_3; ++ break; ++ case 0x15: ++ p->fec_inner = FEC_3_4; ++ break; ++ case 0x18: ++ p->fec_inner = FEC_5_6; ++ break; ++ case 0x1a: ++ p->fec_inner = FEC_7_8; ++ break; ++ default: ++ p->fec_inner = FEC_NONE; ++ break; ++ } ++ p->rolloff = ROLLOFF_35; ++ } ++ ++ tmp = read_status(fe, &status); ++ ++ p->strength.len = 1; ++ p->cnr.len = 1; ++ p->pre_bit_error.len = 1; ++ p->pre_bit_count.len = 1; ++ p->post_bit_error.len = 1; ++ ++ if (!(status & FE_HAS_LOCK)) { ++ p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ return 0; ++ } ++ ++ if (read_snr(fe, &snr)) ++ p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ else { ++ p->cnr.stat[0].scale = FE_SCALE_DECIBEL; ++ p->cnr.stat[0].svalue = snr; ++ } ++ ++ if (read_signal_strength(fe, &strength)) ++ p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ else { ++ p->strength.stat[0].scale = FE_SCALE_DECIBEL; ++ p->strength.stat[0].svalue = strength; ++ } ++ ++ if (read_ber(fe, &ber, &bernom, &berdenom)) { ++ p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; ++ } else { ++ p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; ++ p->pre_bit_error.stat[0].uvalue = bernom; ++ p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; ++ p->pre_bit_count.stat[0].uvalue = berdenom; ++ p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; ++ p->post_bit_error.stat[0].uvalue = ber; ++ } ++ ++ return 0; ++} ++ +static int tune(struct dvb_frontend *fe, bool re_tune, + unsigned int mode_flags, -+ unsigned int *delay, fe_status_t *status) ++ unsigned int *delay, enum fe_status *status) +{ + struct stv *state = fe->demodulator_priv; + int r; @@ -16803,7 +13215,7 @@ index 0000000..d247932 + return DVBFE_ALGO_HW; +} + -+static int set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) ++static int set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone) +{ + struct stv *state = fe->demodulator_priv; + u16 offs = state->nr ? 0x40 : 0; @@ -16811,16 +13223,29 @@ index 0000000..d247932 + switch (tone) { + case SEC_TONE_ON: + return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38); -+ break; + case SEC_TONE_OFF: + return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a); -+ break; + default: + break; + } + return -EINVAL; +} + ++static int wait_dis(struct stv *state, u8 flag, u8 val) ++{ ++ int i; ++ u8 stat; ++ u16 offs = state->nr ? 0x40 : 0; ++ ++ for (i = 0; i < 10; i++) { ++ read_reg(state, RSTV0910_P1_DISTXSTATUS + offs, &stat); ++ if ((stat & flag) == val) ++ return 0; ++ usleep_range(10000, 11000); ++ } ++ return -ETIMEDOUT; ++} ++ +static int send_master_cmd(struct dvb_frontend *fe, + struct dvb_diseqc_master_cmd *cmd) +{ @@ -16829,20 +13254,12 @@ index 0000000..d247932 + int i; + + write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3E); -+ for (i = 0; i < cmd->msg_len; i++) ++ for (i = 0; i < cmd->msg_len; i++) { ++ wait_dis(state, 0x40, 0x00); + write_reg(state, RSTV0910_P1_DISTXFIFO + offs, cmd->msg[i]); ++ } + write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); -+ return 0; -+} -+ -+static int recv_slave_reply(struct dvb_frontend *fe, -+ struct dvb_diseqc_slave_reply *reply) -+{ -+ return 0; -+} -+ -+static int send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst) -+{ ++ wait_dis(state, 0x20, 0x20); + return 0; +} + @@ -16850,56 +13267,10 @@ index 0000000..d247932 +{ + struct stv *state = fe->demodulator_priv; + -+ pr_info("sleep %d\n", state->nr); + Stop(state); + return 0; +} + -+static int read_snr(struct dvb_frontend *fe, u16 *snr) -+{ -+ struct stv *state = fe->demodulator_priv; -+ s32 SNR; -+ -+ *snr = 0; -+ if (GetSignalToNoise(state, &SNR)) -+ return -EIO; -+ *snr = SNR; -+ return 0; -+} -+ -+static int read_ber(struct dvb_frontend *fe, u32 *ber) -+{ -+ struct stv *state = fe->demodulator_priv; -+ u32 n, d; -+ -+ GetBitErrorRate(state, &n, &d); -+ if (d) -+ *ber = n / d; -+ else -+ *ber = 0; -+ return 0; -+} -+ -+static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) -+{ -+ struct stv *state = fe->demodulator_priv; -+ u8 Agc1, Agc0; -+ -+ read_reg(state, RSTV0910_P2_AGCIQIN1 + state->regoff, &Agc1); -+ read_reg(state, RSTV0910_P2_AGCIQIN0 + state->regoff, &Agc0); -+ -+ *strength = ((255 - Agc1) * 3300) / 256; -+ return 0; -+} -+ -+static int read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -+{ -+ /* struct stv *state = fe->demodulator_priv; */ -+ -+ -+ return 0; -+} -+ +static struct dvb_frontend_ops stv0910_ops = { + .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS }, + .info = { @@ -16915,23 +13286,16 @@ index 0000000..d247932 + FE_CAN_QPSK | + FE_CAN_2G_MODULATION + }, -+ .init = init, + .sleep = sleep, + .release = release, + .i2c_gate_ctrl = gate_ctrl, + .get_frontend_algo = get_algo, ++ .get_frontend = get_frontend, + .tune = tune, + .read_status = read_status, + .set_tone = set_tone, + + .diseqc_send_master_cmd = send_master_cmd, -+ .diseqc_send_burst = send_burst, -+ .diseqc_recv_slave_reply = recv_slave_reply, -+ -+ .read_snr = read_snr, -+ .read_ber = read_ber, -+ .read_signal_strength = read_signal_strength, -+ .read_ucblocks = read_ucblocks, +}; + +static struct stv_base *match_base(struct i2c_adapter *i2c, u8 adr) @@ -16956,8 +13320,9 @@ index 0000000..d247932 + return NULL; + + state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40); ++ state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00; + state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4); -+ state->tsspeed = 0x40; ++ state->tsspeed = 0x28; + state->nr = nr; + state->regoff = state->nr ? 0 : 0x200; + state->SearchRange = 16000000; @@ -17003,7 +13368,7 @@ index 0000000..d247932 +MODULE_LICENSE("GPL"); diff --git a/drivers/media/dvb-frontends/stv0910.h b/drivers/media/dvb-frontends/stv0910.h new file mode 100644 -index 0000000..a6fad29 +index 0000000..de73fb9 --- /dev/null +++ b/drivers/media/dvb-frontends/stv0910.h @@ -0,0 +1,31 @@ @@ -17020,11 +13385,11 @@ index 0000000..a6fad29 + u8 rptlvl; +}; + -+#if defined(CONFIG_DVB_STV0910) || \ -+ (defined(CONFIG_DVB_STV0910_MODULE) && defined(MODULE)) ++#if IS_REACHABLE(CONFIG_DVB_STV0910) + +extern struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c, + struct stv0910_cfg *cfg, int nr); ++ +#else + +static inline struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c, @@ -17035,29 +13400,28 @@ index 0000000..a6fad29 + return NULL; +} + -+#endif ++#endif /* CONFIG_DVB_STV0910 */ + -+#endif ++#endif /* _STV0910_H_ */ diff --git a/drivers/media/dvb-frontends/stv0910_regs.h b/drivers/media/dvb-frontends/stv0910_regs.h new file mode 100644 -index 0000000..16e922f +index 0000000..33cb481 --- /dev/null +++ b/drivers/media/dvb-frontends/stv0910_regs.h -@@ -0,0 +1,3998 @@ -+// @DVB-S/DVB-S2 STMicroelectronics STV0900 register defintions -+// Author Manfred Völkel, August 2013 -+// (c) 2013 Digital Devices GmbH Germany. All rights reserved -+ -+// $Id: DD_STV0910Register.h 504 2013-09-02 23:02:14Z manfred $ -+ -+/* ======================================================================= -+-- Registers Declaration (Internal ST, All Applications ) -+-- ------------------------- -+-- Each register (RSTV0910__XXXXX) is defined by its address (2 bytes). -+-- -+-- Each field (FSTV0910__XXXXX)is defined as follow: -+-- [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] -+ ======================================================================= */ +@@ -0,0 +1,3997 @@ ++/* @DVB-S/DVB-S2 STMicroelectronics STV0900 register defintions ++ * Author Manfred Voelkel, August 2013 ++ * (c) 2013 Digital Devices GmbH Germany. All rights reserved ++ * ++ * ======================================================================= ++ * Registers Declaration (Internal ST, All Applications ) ++ * ------------------------- ++ * Each register (RSTV0910__XXXXX) is defined by its address (2 bytes). ++ * ++ * Each field (FSTV0910__XXXXX)is defined as follow: ++ * [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] ++ * ====================================================================== ++ */ + +/*MID*/ +#define RSTV0910_MID 0xf100 @@ -21044,10 +17408,10 @@ index 0000000..16e922f +#define STV0910_NBFIELDS 1776 diff --git a/drivers/media/dvb-frontends/stv6111.c b/drivers/media/dvb-frontends/stv6111.c new file mode 100644 -index 0000000..fbd6365 +index 0000000..827fe48 --- /dev/null +++ b/drivers/media/dvb-frontends/stv6111.c -@@ -0,0 +1,450 @@ +@@ -0,0 +1,684 @@ +/* + * Driver for the ST STV6111 tuner + * @@ -21071,6 +17435,9 @@ index 0000000..fbd6365 + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + ++#undef pr_fmt ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ +#include +#include +#include @@ -21078,11 +17445,274 @@ index 0000000..fbd6365 +#include +#include +#include -+#include +#include + +#include "dvb_frontend.h" + ++struct stv { ++ struct i2c_adapter *i2c; ++ u8 adr; ++ ++ u8 reg[11]; ++ u32 ref_freq; ++ u32 Frequency; ++}; ++ ++struct SLookup { ++ s16 Value; ++ u16 RegValue; ++}; ++ ++static struct SLookup LNAGain_NF_LookUp[] = { ++ /*Gain *100dB*/ /*Reg*/ ++ { 2572, 0 }, ++ { 2575, 1 }, ++ { 2580, 2 }, ++ { 2588, 3 }, ++ { 2596, 4 }, ++ { 2611, 5 }, ++ { 2633, 6 }, ++ { 2664, 7 }, ++ { 2701, 8 }, ++ { 2753, 9 }, ++ { 2816, 10 }, ++ { 2902, 11 }, ++ { 2995, 12 }, ++ { 3104, 13 }, ++ { 3215, 14 }, ++ { 3337, 15 }, ++ { 3492, 16 }, ++ { 3614, 17 }, ++ { 3731, 18 }, ++ { 3861, 19 }, ++ { 3988, 20 }, ++ { 4124, 21 }, ++ { 4253, 22 }, ++ { 4386, 23 }, ++ { 4505, 24 }, ++ { 4623, 25 }, ++ { 4726, 26 }, ++ { 4821, 27 }, ++ { 4903, 28 }, ++ { 4979, 29 }, ++ { 5045, 30 }, ++ { 5102, 31 } ++}; ++ ++static struct SLookup LNAGain_IIP3_LookUp[] = { ++ /*Gain *100dB*/ /*reg*/ ++ { 1548, 0 }, ++ { 1552, 1 }, ++ { 1569, 2 }, ++ { 1565, 3 }, ++ { 1577, 4 }, ++ { 1594, 5 }, ++ { 1627, 6 }, ++ { 1656, 7 }, ++ { 1700, 8 }, ++ { 1748, 9 }, ++ { 1805, 10 }, ++ { 1896, 11 }, ++ { 1995, 12 }, ++ { 2113, 13 }, ++ { 2233, 14 }, ++ { 2366, 15 }, ++ { 2543, 16 }, ++ { 2687, 17 }, ++ { 2842, 18 }, ++ { 2999, 19 }, ++ { 3167, 20 }, ++ { 3342, 21 }, ++ { 3507, 22 }, ++ { 3679, 23 }, ++ { 3827, 24 }, ++ { 3970, 25 }, ++ { 4094, 26 }, ++ { 4210, 27 }, ++ { 4308, 28 }, ++ { 4396, 29 }, ++ { 4468, 30 }, ++ { 4535, 31 } ++}; ++ ++static struct SLookup Gain_RFAGC_LookUp[] = { ++ /*Gain *100dB*/ /*reg*/ ++ { 4870, 0x3000 }, ++ { 4850, 0x3C00 }, ++ { 4800, 0x4500 }, ++ { 4750, 0x4800 }, ++ { 4700, 0x4B00 }, ++ { 4650, 0x4D00 }, ++ { 4600, 0x4F00 }, ++ { 4550, 0x5100 }, ++ { 4500, 0x5200 }, ++ { 4420, 0x5500 }, ++ { 4316, 0x5800 }, ++ { 4200, 0x5B00 }, ++ { 4119, 0x5D00 }, ++ { 3999, 0x6000 }, ++ { 3950, 0x6100 }, ++ { 3876, 0x6300 }, ++ { 3755, 0x6600 }, ++ { 3641, 0x6900 }, ++ { 3567, 0x6B00 }, ++ { 3425, 0x6F00 }, ++ { 3350, 0x7100 }, ++ { 3236, 0x7400 }, ++ { 3118, 0x7700 }, ++ { 3004, 0x7A00 }, ++ { 2917, 0x7C00 }, ++ { 2776, 0x7F00 }, ++ { 2635, 0x8200 }, ++ { 2516, 0x8500 }, ++ { 2406, 0x8800 }, ++ { 2290, 0x8B00 }, ++ { 2170, 0x8E00 }, ++ { 2073, 0x9100 }, ++ { 1949, 0x9400 }, ++ { 1836, 0x9700 }, ++ { 1712, 0x9A00 }, ++ { 1631, 0x9C00 }, ++ { 1515, 0x9F00 }, ++ { 1400, 0xA200 }, ++ { 1323, 0xA400 }, ++ { 1203, 0xA700 }, ++ { 1091, 0xAA00 }, ++ { 1011, 0xAC00 }, ++ { 904, 0xAF00 }, ++ { 787, 0xB200 }, ++ { 685, 0xB500 }, ++ { 571, 0xB800 }, ++ { 464, 0xBB00 }, ++ { 374, 0xBE00 }, ++ { 275, 0xC200 }, ++ { 181, 0xC600 }, ++ { 102, 0xCC00 }, ++ { 49, 0xD900 } ++}; ++ ++/* ++ * This table is 6 dB too low comapred to the others (probably created with ++ * a different BB_MAG setting) ++*/ ++static struct SLookup Gain_Channel_AGC_NF_LookUp[] = { ++ /*Gain *100dB*/ /*reg*/ ++ { 7082, 0x3000 }, ++ { 7052, 0x4000 }, ++ { 7007, 0x4600 }, ++ { 6954, 0x4A00 }, ++ { 6909, 0x4D00 }, ++ { 6833, 0x5100 }, ++ { 6753, 0x5400 }, ++ { 6659, 0x5700 }, ++ { 6561, 0x5A00 }, ++ { 6472, 0x5C00 }, ++ { 6366, 0x5F00 }, ++ { 6259, 0x6100 }, ++ { 6151, 0x6400 }, ++ { 6026, 0x6700 }, ++ { 5920, 0x6900 }, ++ { 5835, 0x6B00 }, ++ { 5770, 0x6C00 }, ++ { 5681, 0x6E00 }, ++ { 5596, 0x7000 }, ++ { 5503, 0x7200 }, ++ { 5429, 0x7300 }, ++ { 5319, 0x7500 }, ++ { 5220, 0x7700 }, ++ { 5111, 0x7900 }, ++ { 4983, 0x7B00 }, ++ { 4876, 0x7D00 }, ++ { 4755, 0x7F00 }, ++ { 4635, 0x8100 }, ++ { 4499, 0x8300 }, ++ { 4405, 0x8500 }, ++ { 4323, 0x8600 }, ++ { 4233, 0x8800 }, ++ { 4156, 0x8A00 }, ++ { 4038, 0x8C00 }, ++ { 3935, 0x8E00 }, ++ { 3823, 0x9000 }, ++ { 3712, 0x9200 }, ++ { 3601, 0x9500 }, ++ { 3511, 0x9700 }, ++ { 3413, 0x9900 }, ++ { 3309, 0x9B00 }, ++ { 3213, 0x9D00 }, ++ { 3088, 0x9F00 }, ++ { 2992, 0xA100 }, ++ { 2878, 0xA400 }, ++ { 2769, 0xA700 }, ++ { 2645, 0xAA00 }, ++ { 2538, 0xAD00 }, ++ { 2441, 0xB000 }, ++ { 2350, 0xB600 }, ++ { 2237, 0xBA00 }, ++ { 2137, 0xBF00 }, ++ { 2039, 0xC500 }, ++ { 1938, 0xDF00 }, ++ { 1927, 0xFF00 } ++}; ++ ++static struct SLookup Gain_Channel_AGC_IIP3_LookUp[] = { ++ /*Gain *100dB*/ /*reg*/ ++ { 7070, 0x3000 }, ++ { 7028, 0x4000 }, ++ { 7019, 0x4600 }, ++ { 6900, 0x4A00 }, ++ { 6811, 0x4D00 }, ++ { 6763, 0x5100 }, ++ { 6690, 0x5400 }, ++ { 6644, 0x5700 }, ++ { 6617, 0x5A00 }, ++ { 6598, 0x5C00 }, ++ { 6462, 0x5F00 }, ++ { 6348, 0x6100 }, ++ { 6197, 0x6400 }, ++ { 6154, 0x6700 }, ++ { 6098, 0x6900 }, ++ { 5893, 0x6B00 }, ++ { 5812, 0x6C00 }, ++ { 5773, 0x6E00 }, ++ { 5723, 0x7000 }, ++ { 5661, 0x7200 }, ++ { 5579, 0x7300 }, ++ { 5460, 0x7500 }, ++ { 5308, 0x7700 }, ++ { 5099, 0x7900 }, ++ { 4910, 0x7B00 }, ++ { 4800, 0x7D00 }, ++ { 4785, 0x7F00 }, ++ { 4635, 0x8100 }, ++ { 4466, 0x8300 }, ++ { 4314, 0x8500 }, ++ { 4295, 0x8600 }, ++ { 4144, 0x8800 }, ++ { 3920, 0x8A00 }, ++ { 3889, 0x8C00 }, ++ { 3771, 0x8E00 }, ++ { 3655, 0x9000 }, ++ { 3446, 0x9200 }, ++ { 3298, 0x9500 }, ++ { 3083, 0x9700 }, ++ { 3015, 0x9900 }, ++ { 2833, 0x9B00 }, ++ { 2746, 0x9D00 }, ++ { 2632, 0x9F00 }, ++ { 2598, 0xA100 }, ++ { 2480, 0xA400 }, ++ { 2236, 0xA700 }, ++ { 2171, 0xAA00 }, ++ { 2060, 0xAD00 }, ++ { 1999, 0xB000 }, ++ { 1974, 0xB600 }, ++ { 1820, 0xBA00 }, ++ { 1741, 0xBF00 }, ++ { 1655, 0xC500 }, ++ { 1444, 0xDF00 }, ++ { 1325, 0xFF00 }, ++}; ++ +static inline u32 MulDiv32(u32 a, u32 b, u32 c) +{ + u64 tmp64; @@ -21093,15 +17723,6 @@ index 0000000..fbd6365 + return (u32) tmp64; +} + -+ -+struct stv { -+ struct i2c_adapter *i2c; -+ u8 adr; -+ -+ u8 reg[11]; -+ u32 ref_freq; -+}; -+ +static int i2c_read(struct i2c_adapter *adap, + u8 adr, u8 *msg, int len, u8 *answ, int alen) +{ @@ -21110,8 +17731,8 @@ index 0000000..fbd6365 + { .addr = adr, .flags = I2C_M_RD, + .buf = answ, .len = alen } }; + if (i2c_transfer(adap, msgs, 2) != 2) { -+ pr_err("stv6111: i2c_read error\n"); -+ return -1; ++ pr_err("i2c_read error\n"); ++ return -EREMOTEIO; + } + return 0; +} @@ -21122,8 +17743,8 @@ index 0000000..fbd6365 + .buf = data, .len = len}; + + if (i2c_transfer(adap, &msg, 1) != 1) { -+ pr_err("stv6111: i2c_write error\n"); -+ return -1; ++ pr_err("i2c_write error\n"); ++ return -EREMOTEIO; + } + return 0; +} @@ -21137,38 +17758,18 @@ index 0000000..fbd6365 + return i2c_write(state->i2c, state->adr, d, len + 1); +} + -+#if 0 +static int write_reg(struct stv *state, u8 reg, u8 val) +{ + u8 d[2] = {reg, val}; + + return i2c_write(state->i2c, state->adr, d, 2); +} -+#endif + +static int read_reg(struct stv *state, u8 reg, u8 *val) +{ + return i2c_read(state->i2c, state->adr, ®, 1, val, 1); +} + -+static int read_regs(struct stv *state, u8 reg, u8 *val, int len) -+{ -+ return i2c_read(state->i2c, state->adr, ®, 1, val, len); -+} -+ -+static void dump_regs(struct stv *state) -+{ -+ u8 d[11], *c = &state->reg[0]; -+ -+ read_regs(state, 0, d, 11); -+ pr_info("stv6111_regs = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", -+ d[0], d[1], d[2], d[3], d[4], d[5], d[6], d[7], -+ d[8], d[9], d[10]); -+ pr_info("reg[] = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", -+ c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7], -+ c[8], c[9], c[10]); -+} -+ +static int wait_for_call_done(struct stv *state, u8 mask) +{ + int status = 0; @@ -21186,7 +17787,7 @@ index 0000000..fbd6365 + usleep_range(4000, 6000); + LockRetryCount -= 1; + -+ status = -1; ++ status = -EIO; + } + return status; +} @@ -21213,7 +17814,6 @@ index 0000000..fbd6365 + + state->ref_freq = 16000; + -+ + if (clkdiv <= 3) + state->reg[0x00] |= (clkdiv & 0x03); + if (agcmode <= 3) { @@ -21232,24 +17832,7 @@ index 0000000..fbd6365 +static int attach_init(struct stv *state) +{ + if (write_regs(state, 0, 11)) -+ return -1; -+ pr_info("attach_init OK\n"); -+ dump_regs(state); -+ return 0; -+} -+ -+static int sleep(struct dvb_frontend *fe) -+{ -+ /* struct tda_state *state = fe->tuner_priv; */ -+ -+ pr_info("tuner sleep\n"); -+ return 0; -+} -+ -+static int init(struct dvb_frontend *fe) -+{ -+ /* struct tda_state *state = fe->tuner_priv; */ -+ pr_info("init\n"); ++ return -ENODEV; + return 0; +} + @@ -21290,7 +17873,6 @@ index 0000000..fbd6365 + u32 p = 1, psel = 0, fvco, div, frac; + u8 Icp, tmp; + -+ pr_info("F = %u, COF = %u\n", Frequency, CutOffFrequency); + if (index < 6) + index = 6; + if (index > 50) @@ -21349,7 +17931,8 @@ index 0000000..fbd6365 + } + read_reg(state, 0x08, &tmp); + -+ dump_regs(state); ++ state->Frequency = Frequency; ++ + return 0; +} + @@ -21357,7 +17940,6 @@ index 0000000..fbd6365 +{ + struct stv *state = fe->tuner_priv; + struct dtv_frontend_properties *p = &fe->dtv_property_cache; -+ int status; + u32 freq, symb, cutoff; + + if (p->delivery_system != SYS_DVBS && p->delivery_system != SYS_DVBS2) @@ -21372,74 +17954,101 @@ index 0000000..fbd6365 + set_lof(state, freq, cutoff); + if (fe->ops.i2c_gate_ctrl) + fe->ops.i2c_gate_ctrl(fe, 0); -+ return status; -+} -+ -+static int get_frequency(struct dvb_frontend *fe, u32 *frequency) -+{ -+ *frequency = 0; + return 0; +} + -+static u32 AGC_Gain[] = { -+ 000, /* 0.0 */ -+ 000, /* 0.1 */ -+ 1000, /* 0.2 */ -+ 2000, /* 0.3 */ -+ 3000, /* 0.4 */ -+ 4000, /* 0.5 */ -+ 5000, /* 0.6 */ -+ 6000, /* 0.7 */ -+ 7000, /* 0.8 */ -+ 14000, /* 0.9 */ -+ 20000, /* 1.0 */ -+ 27000, /* 1.1 */ -+ 32000, /* 1.2 */ -+ 37000, /* 1.3 */ -+ 42000, /* 1.4 */ -+ 47000, /* 1.5 */ -+ 50000, /* 1.6 */ -+ 53000, /* 1.7 */ -+ 56000, /* 1.8 */ -+ 58000, /* 1.9 */ -+ 60000, /* 2.0 */ -+ 62000, /* 2.1 */ -+ 63000, /* 2.2 */ -+ 64000, /* 2.3 */ -+ 64500, /* 2.4 */ -+ 65000, /* 2.5 */ -+ 65500, /* 2.6 */ -+ 66000, /* 2.7 */ -+ 66500, /* 2.8 */ -+ 67000, /* 2.9 */ -+}; ++static s32 TableLookup(struct SLookup *Table, int TableSize, u16 RegValue) ++{ ++ s32 Gain; ++ s32 RegDiff; ++ int imin = 0; ++ int imax = TableSize - 1; ++ int i; ++ ++ /* Assumes Table[0].RegValue < Table[imax].RegValue */ ++ if (RegValue <= Table[0].RegValue) ++ Gain = Table[0].Value; ++ else if (RegValue >= Table[imax].RegValue) ++ Gain = Table[imax].Value; ++ else { ++ while (imax-imin > 1) { ++ i = (imax + imin) / 2; ++ if ((Table[imin].RegValue <= RegValue) && ++ (RegValue <= Table[i].RegValue)) ++ imax = i; ++ else ++ imin = i; ++ } ++ RegDiff = Table[imax].RegValue - Table[imin].RegValue; ++ Gain = Table[imin].Value; ++ if (RegDiff != 0) ++ Gain += ((s32) (RegValue - Table[imin].RegValue) * ++ (s32)(Table[imax].Value ++ - Table[imin].Value))/(RegDiff); ++ } ++ return Gain; ++} + +static int get_rf_strength(struct dvb_frontend *fe, u16 *st) +{ -+ *st = 0; -+#if 0 + struct stv *state = fe->tuner_priv; ++ u16 RFAgc = *st; + s32 Gain; -+ u32 Index = RFAgc / 100; -+ if (Index >= (sizeof(AGC_Gain) / sizeof(AGC_Gain[0]) - 1)) -+ Gain = AGC_Gain[sizeof(AGC_Gain) / sizeof(AGC_Gain[0]) - 1]; -+ else -+ Gain = AGC_Gain[Index] + -+ ((AGC_Gain[Index+1] - AGC_Gain[Index]) * -+ (RFAgc % 100)) / 100; -+ *st = Gain; -+#endif -+ return 0; -+} + -+static int get_if(struct dvb_frontend *fe, u32 *frequency) -+{ -+ *frequency = 0; -+ return 0; -+} ++ if ((state->reg[0x03] & 0x60) == 0) { ++ /* RF Mode, Read AGC ADC */ ++ u8 Reg = 0; ++ ++ if (fe->ops.i2c_gate_ctrl) ++ fe->ops.i2c_gate_ctrl(fe, 1); ++ write_reg(state, 0x02, state->reg[0x02] | 0x20); ++ read_reg(state, 2, &Reg); ++ if (Reg & 0x20) ++ read_reg(state, 2, &Reg); ++ if (fe->ops.i2c_gate_ctrl) ++ fe->ops.i2c_gate_ctrl(fe, 0); ++ ++ if ((state->reg[0x02] & 0x80) == 0) ++ /* NF */ ++ Gain = TableLookup(LNAGain_NF_LookUp, ++ ARRAY_SIZE(LNAGain_NF_LookUp), Reg & 0x1F); ++ else ++ /* IIP3 */ ++ Gain = TableLookup(LNAGain_IIP3_LookUp, ++ ARRAY_SIZE(LNAGain_IIP3_LookUp), Reg & 0x1F); ++ ++ Gain += TableLookup(Gain_RFAGC_LookUp, ++ ARRAY_SIZE(Gain_RFAGC_LookUp), RFAgc); ++ Gain -= 2400; ++ } else { ++ /* Channel Mode */ ++ if ((state->reg[0x02] & 0x80) == 0) { ++ /* NF */ ++ Gain = TableLookup(Gain_Channel_AGC_NF_LookUp, ++ ARRAY_SIZE(Gain_Channel_AGC_NF_LookUp), RFAgc); ++ Gain += 600; ++ } else { ++ /* IIP3 */ ++ Gain = TableLookup(Gain_Channel_AGC_IIP3_LookUp, ++ ARRAY_SIZE(Gain_Channel_AGC_IIP3_LookUp), ++ RFAgc); ++ } ++ } ++ ++ if (state->Frequency > 0) ++ /* Tilt correction ( 0.00016 dB/MHz ) */ ++ Gain -= ((((s32)(state->Frequency / 1000) - 1550) * 2) / 12); ++ ++ /* + (BBGain * 10); */ ++ Gain += (s32)((state->reg[0x01] & 0xC0) >> 6) * 600 - 1300; ++ ++ if (Gain < 0) ++ Gain = 0; ++ else if (Gain > 10000) ++ Gain = 10000; ++ ++ *st = 10000 - Gain; + -+static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) -+{ + return 0; +} + @@ -21450,13 +18059,8 @@ index 0000000..fbd6365 + .frequency_max = 2150000, + .frequency_step = 0 + }, -+ .init = init, -+ .sleep = sleep, + .set_params = set_params, + .release = release, -+ .get_frequency = get_frequency, -+ .get_if_frequency = get_if, -+ .get_bandwidth = get_bandwidth, + .get_rf_strength = get_rf_strength, + .set_bandwidth = set_bandwidth, +}; @@ -21492,1174 +18096,116 @@ index 0000000..fbd6365 +MODULE_DESCRIPTION("STV6111 driver"); +MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); +MODULE_LICENSE("GPL"); -+ -+/* -+ * Local variables: -+ * c-basic-offset: 8 -+ * End: -+ */ diff --git a/drivers/media/dvb-frontends/stv6111.h b/drivers/media/dvb-frontends/stv6111.h new file mode 100644 -index 0000000..31d200c +index 0000000..55b5ddc --- /dev/null +++ b/drivers/media/dvb-frontends/stv6111.h -@@ -0,0 +1,5 @@ +@@ -0,0 +1,20 @@ +#ifndef _STV6111_H_ +#define _STV6111_H_ -+struct dvb_frontend *stv6111_attach(struct dvb_frontend *fe, -+ struct i2c_adapter *i2c, u8 adr); -+#endif -diff --git a/drivers/media/dvb-frontends/tda18212dd.c b/drivers/media/dvb-frontends/tda18212dd.c -new file mode 100644 -index 0000000..7d99fd5 ---- /dev/null -+++ b/drivers/media/dvb-frontends/tda18212dd.c -@@ -0,0 +1,974 @@ -+/* -+ * tda18212: Driver for the TDA18212 tuner -+ * -+ * Copyright (C) 2011-2013 Digital Devices GmbH -+ * -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 only, as published by the Free Software Foundation. -+ * -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ * 02110-1301, USA -+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html -+ */ + -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include ++#if IS_REACHABLE(CONFIG_DVB_STV6111) + -+#include "dvb_frontend.h" ++extern struct dvb_frontend *stv6111_attach(struct dvb_frontend *fe, ++ struct i2c_adapter *i2c, u8 adr); + -+#ifndef CHK_ERROR -+#define CHK_ERROR(s) if ((status = s) < 0) break -+#endif -+ -+#define MASTER_PSM_AGC1 0 -+#define MASTER_AGC1_6_15dB 1 -+ -+#define SLAVE_PSM_AGC1 1 -+#define SLAVE_AGC1_6_15dB 0 -+ -+/* 0 = 2 Vpp ... 2 = 1 Vpp, 7 = 0.5 Vpp */ -+#define IF_LEVEL_DVBC 2 -+#define IF_LEVEL_DVBT 2 -+ -+enum { -+ ID_1 = 0x00, -+ ID_2 = 0x01, -+ ID_3 = 0x02, -+ THERMO_1, -+ THERMO_2, -+ POWER_STATE_1, -+ POWER_STATE_2, -+ INPUT_POWER_LEVEL, -+ IRQ_STATUS, -+ IRQ_ENABLE, -+ IRQ_CLEAR, -+ IRQ_SET, -+ AGC1_1, -+ AGC2_1, -+ AGCK_1, -+ RF_AGC_1, -+ IR_MIXER_1 = 0x10, -+ AGC5_1, -+ IF_AGC, -+ IF_1, -+ REFERENCE, -+ IF_FREQUENCY_1, -+ RF_FREQUENCY_1, -+ RF_FREQUENCY_2, -+ RF_FREQUENCY_3, -+ MSM_1, -+ MSM_2, -+ PSM_1, -+ DCC_1, -+ FLO_MAX, -+ IR_CAL_1, -+ IR_CAL_2, -+ IR_CAL_3 = 0x20, -+ IR_CAL_4, -+ VSYNC_MGT, -+ IR_MIXER_2, -+ AGC1_2, -+ AGC5_2, -+ RF_CAL_1, -+ RF_CAL_2, -+ RF_CAL_3, -+ RF_CAL_4, -+ RF_CAL_5, -+ RF_CAL_6, -+ RF_FILTER_1, -+ RF_FILTER_2, -+ RF_FILTER_3, -+ RF_BAND_PASS_FILTER, -+ CP_CURRENT = 0x30, -+ AGC_DET_OUT = 0x31, -+ RF_AGC_GAIN_1 = 0x32, -+ RF_AGC_GAIN_2 = 0x33, -+ IF_AGC_GAIN = 0x34, -+ POWER_1 = 0x35, -+ POWER_2 = 0x36, -+ MISC_1, -+ RFCAL_LOG_1, -+ RFCAL_LOG_2, -+ RFCAL_LOG_3, -+ RFCAL_LOG_4, -+ RFCAL_LOG_5, -+ RFCAL_LOG_6, -+ RFCAL_LOG_7, -+ RFCAL_LOG_8, -+ RFCAL_LOG_9 = 0x40, -+ RFCAL_LOG_10 = 0x41, -+ RFCAL_LOG_11 = 0x42, -+ RFCAL_LOG_12 = 0x43, -+ REG_MAX, -+}; -+ -+enum HF_Standard { -+ HF_None = 0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio, -+ HF_AnalogMax, HF_DVBT_6MHZ, HF_DVBT_7MHZ, HF_DVBT_8MHZ, -+ HF_DVBT, HF_ATSC, HF_DVBC_6MHZ, HF_DVBC_7MHZ, -+ HF_DVBC_8MHZ, HF_DVBC -+}; -+ -+struct SStandardParams { -+ s32 m_IFFrequency; -+ u32 m_BandWidth; -+ u8 m_IF_1; /* FF IF_HP_fc:2 IF_Notch:1 LP_FC_Offset:2 LP_FC:3 */ -+ u8 m_IR_MIXER_2; /* 03 :6 HI_Pass:1 DC_Notch:1 */ -+ u8 m_AGC1_1; /* 0F :4 AGC1_Top:4 */ -+ u8 m_AGC2_1; /* 0F :4 AGC2_Top:4 */ -+ /*EF RF_AGC_Adapt:1 RF_AGC_Adapt_Top:2 :1 RF_Atten_3dB:1 RF_AGC_Top:3 */ -+ u8 m_RF_AGC_1_Low; -+ /*EF RF_AGC_Adapt:1 RF_AGC_Adapt_Top:2 :1 RF_Atten_3dB:1 RF_AGC_Top:3 */ -+ u8 m_RF_AGC_1_High; -+ u8 m_IR_MIXER_1; /* 0F :4 IR_mixer_Top:4 */ -+ u8 m_AGC5_1; /* 1F :3 AGC5_Ana AGC5_Top:4 */ -+ u8 m_AGCK_1; /* 0F :4 AGCK_Step:2 AGCK_Mode:2 */ -+ u8 m_PSM_1; /* 20 :2 PSM_StoB:1 :5 */ -+ bool m_AGC1_Freeze; -+ bool m_LTO_STO_immune; -+}; -+ -+#if 0 -+static struct SStandardParams -+m_StandardTable[HF_DVBC_8MHZ - HF_DVBT_6MHZ + 1] = { -+ { 3250000, 6000000, 0x20, 0x03, 0x00, 0x07, 0x2B, -+ 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_6MHZ */ -+ { 3500000, 7000000, 0x31, 0x01, 0x00, 0x07, 0x2B, -+ 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_7MHZ */ -+ { 4000000, 8000000, 0x22, 0x01, 0x00, 0x07, 0x2B, -+ 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_8MHZ */ -+ { 0000000, 0, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, false, false }, /* HF_DVBT (Unused) */ -+ { 3250000, 6000000, 0x20, 0x03, 0x0A, 0x07, 0x6D, -+ 0x6D, 0x0E, 0x0E, 0x02, 0x20, false, false }, /* HF_ATSC */ -+ { 3600000, 6000000, 0x10, 0x01, 0x00, 0x07, 0x83, -+ 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, /* HF_DVBC_6MHZ */ -+ { 5000000, 7000000, 0x93, 0x03, 0x00, 0x07, 0x83, -+ 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, -+ /* HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) */ -+ { 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x83, -+ 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, /* HF_DVBC_8MHZ */ -+}; +#else -+static struct SStandardParams -+m_StandardTable[HF_DVBC_8MHZ - HF_DVBT_6MHZ + 1] = { -+ { 4000000, 6000000, 0x41, 0x03, 0x00, 0x07, 0x2B, -+ 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_6MHZ */ -+ { 4500000, 7000000, 0x42, 0x03, 0x00, 0x07, 0x2B, -+ 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_7MHZ */ -+ { 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x2B, -+ 0x2C, 0x0B, 0x0B, 0x02, 0x20, false, false }, /* HF_DVBT_8MHZ */ -+ /* ------------------------------ */ -+ { 0000000, 0, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, false, false }, /* HF_DVBT (Unused)*/ -+ { 3250000, 6000000, 0x20, 0x03, 0x0A, 0x07, 0x6D, -+ 0x6D, 0x0E, 0x0E, 0x02, 0x20, false, false }, /* HF_ATSC */ -+ { 3600000, 6000000, 0x10, 0x01, 0x00, 0x07, 0x83, -+ 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, /* HF_DVBC_6MHZ */ -+ { 5000000, 7000000, 0x93, 0x03, 0x00, 0x07, 0x83, -+ 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, -+ /* HF_DVBC_7MHZ (not documented by NXP, use same settings as 8 MHZ) */ -+ { 5000000, 8000000, 0x43, 0x03, 0x00, 0x07, 0x83, -+ 0x83, 0x0B, 0x0B, 0x02, 0x00, true , true }, /* HF_DVBC_8MHZ */ -+}; -+#endif + -+struct tda_state { -+ struct i2c_adapter *i2c; -+ u8 adr; -+ -+ enum HF_Standard m_Standard; -+ u32 m_Frequency; -+ u32 IF; -+ -+ bool m_isMaster; -+ bool m_bPowerMeasurement; -+ bool m_bLTEnable; -+ bool m_bEnableFreeze; -+ -+ u16 m_ID; -+ -+ s32 m_SettlingTime; -+ -+ u8 m_IFLevelDVBC; -+ u8 m_IFLevelDVBT; -+ u8 Regs[REG_MAX]; -+ u8 m_LastPowerLevel; -+}; -+ -+static int i2c_readn(struct i2c_adapter *adapter, u8 adr, u8 *data, int len) ++static inline struct dvb_frontend *stv6111_attach(struct dvb_frontend *fe, ++ struct i2c_adapter *i2c, u8 adr); +{ -+ struct i2c_msg msgs[1] = {{.addr = adr, .flags = I2C_M_RD, -+ .buf = data, .len = len} }; -+ return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; ++ pr_warn("%s: Driver disabled by Kconfig\n", __func__); ++ return NULL; +} + -+static int i2c_read(struct i2c_adapter *adap, -+ u8 adr, u8 *msg, int len, u8 *answ, int alen) -+{ -+ struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, -+ .buf = msg, .len = len}, -+ { .addr = adr, .flags = I2C_M_RD, -+ .buf = answ, .len = alen } }; -+ if (i2c_transfer(adap, msgs, 2) != 2) { -+ pr_err("tda18212dd: i2c_read error\n"); -+ return -1; -+ } -+ return 0; -+} ++#endif /* CONFIG_DVB_STV6111 */ + -+static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -+{ -+ struct i2c_msg msg = {.addr = adr, .flags = 0, -+ .buf = data, .len = len}; -+ -+ if (i2c_transfer(adap, &msg, 1) != 1) { -+ pr_err("tda18212: i2c_write error\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+static int write_regs(struct tda_state *state, -+ u8 SubAddr, u8 *Regs, u16 nRegs) -+{ -+ u8 data[REG_MAX + 1]; -+ -+ data[0] = SubAddr; -+ memcpy(data + 1, Regs, nRegs); -+ return i2c_write(state->i2c, state->adr, data, nRegs + 1); -+} -+ -+static int write_reg(struct tda_state *state, u8 SubAddr, u8 Reg) -+{ -+ u8 msg[2] = {SubAddr, Reg}; -+ -+ return i2c_write(state->i2c, state->adr, msg, 2); -+} -+ -+static int Read(struct tda_state *state, u8 *Regs) -+{ -+ return i2c_readn(state->i2c, state->adr, Regs, REG_MAX); -+} -+ -+static int update_regs(struct tda_state *state, u8 RegFrom, u8 RegTo) -+{ -+ return write_regs(state, RegFrom, -+ &state->Regs[RegFrom], RegTo-RegFrom + 1); -+} -+ -+static int update_reg(struct tda_state *state, u8 Reg) -+{ -+ return write_reg(state, Reg, state->Regs[Reg]); -+} -+ -+ -+static int read_regs(struct tda_state *state, -+ u8 SubAddr, u8 *Regs, u16 nRegs) -+{ -+ return i2c_read(state->i2c, state->adr, -+ &SubAddr, 1, Regs, nRegs); -+} -+ -+static int read_reg(struct tda_state *state, -+ u8 SubAddr, u8 *Reg) -+{ -+ return i2c_read(state->i2c, state->adr, -+ &SubAddr, 1, Reg, 1); -+} -+ -+static int read_reg1(struct tda_state *state, u8 Reg) -+{ -+ return read_reg(state, Reg, &state->Regs[Reg]); -+} -+ -+static void init_state(struct tda_state *state) -+{ -+ u32 ulIFLevelDVBC = IF_LEVEL_DVBC; -+ u32 ulIFLevelDVBT = IF_LEVEL_DVBT; -+ u32 ulPowerMeasurement = 1; -+ u32 ulLTEnable = 1; -+ u32 ulEnableFreeze = 0; -+ -+ state->m_Frequency = 0; -+ state->m_isMaster = true; -+ state->m_ID = 0; -+ state->m_LastPowerLevel = 0xFF; -+ state->m_IFLevelDVBC = (ulIFLevelDVBC & 0x07); -+ state->m_IFLevelDVBT = (ulIFLevelDVBT & 0x07); -+ state->m_bPowerMeasurement = (ulPowerMeasurement != 0); -+ state->m_bLTEnable = (ulLTEnable != 0); -+ state->m_bEnableFreeze = (ulEnableFreeze != 0); -+} -+ -+static int StartCalibration(struct tda_state *state) -+{ -+ int status = 0; -+ do { -+ state->Regs[POWER_2] &= ~0x02; /* RSSI CK = 31.25 kHz */ -+ CHK_ERROR(update_reg(state, POWER_2)); -+ -+ /* AGC1 Do Step = 2 */ -+ state->Regs[AGC1_2] = (state->Regs[AGC1_2] & ~0x60) | 0x40; -+ CHK_ERROR(update_reg(state, AGC1_2)); /* AGC */ -+ -+ /* AGC2 Do Step = 1 */ -+ state->Regs[RF_FILTER_3] = -+ (state->Regs[RF_FILTER_3] & ~0xC0) | 0x40; -+ CHK_ERROR(update_reg(state, RF_FILTER_3)); -+ -+ /* AGCs Assym Up Step = 3 // Datasheet sets all bits to 1! */ -+ state->Regs[AGCK_1] |= 0xC0; -+ CHK_ERROR(update_reg(state, AGCK_1)); -+ -+ /* AGCs Assym Do Step = 2 */ -+ state->Regs[AGC5_1] = (state->Regs[AGC5_1] & ~0x60) | 0x40; -+ CHK_ERROR(update_reg(state, AGC5_1)); -+ -+ state->Regs[IRQ_CLEAR] |= 0x80; /* Reset IRQ */ -+ CHK_ERROR(update_reg(state, IRQ_CLEAR)); -+ -+ state->Regs[MSM_1] = 0x3B; /* Set Calibration */ -+ state->Regs[MSM_2] = 0x01; /* Start MSM */ -+ CHK_ERROR(update_regs(state, MSM_1, MSM_2)); -+ state->Regs[MSM_2] = 0x00; -+ } while (0); -+ return status; -+} -+ -+static int FinishCalibration(struct tda_state *state) -+{ -+ int status = 0; -+ u8 RFCal_Log[12]; -+ -+ do { -+ u8 IRQ = 0; -+ int Timeout = 150; /* 1.5 s */ -+ while (true) { -+ CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); -+ if ((IRQ & 0x80) != 0) -+ break; -+ Timeout -= 1; -+ if (Timeout == 0) { -+ status = -1; -+ break; -+ } -+ usleep_range(10000, 12000); -+ } -+ CHK_ERROR(status); -+ -+ state->Regs[FLO_MAX] = 0x0A; -+ CHK_ERROR(update_reg(state, FLO_MAX)); -+ -+ state->Regs[AGC1_1] &= ~0xC0; -+ if (state->m_bLTEnable) -+ state->Regs[AGC1_1] |= 0x80; /* LTEnable */ -+ -+ state->Regs[AGC1_1] |= (state->m_isMaster ? -+ MASTER_AGC1_6_15dB : -+ SLAVE_AGC1_6_15dB) << 6; -+ CHK_ERROR(update_reg(state, AGC1_1)); -+ -+ state->Regs[PSM_1] &= ~0xC0; -+ state->Regs[PSM_1] |= (state->m_isMaster ? -+ MASTER_PSM_AGC1 : SLAVE_PSM_AGC1) << 6; -+ CHK_ERROR(update_reg(state, PSM_1)); -+ -+ state->Regs[REFERENCE] |= 0x03; /* XTOUT = 3 */ -+ CHK_ERROR(update_reg(state, REFERENCE)); -+ -+ CHK_ERROR(read_regs(state, RFCAL_LOG_1, -+ RFCal_Log, sizeof(RFCal_Log))); -+ } while (0); -+ return status; -+} -+ -+static int PowerOn(struct tda_state *state) -+{ -+ state->Regs[POWER_STATE_2] &= ~0x0F; -+ update_reg(state, POWER_STATE_2); -+ /* Digital clock source = Sigma Delta */ -+ state->Regs[REFERENCE] |= 0x40; -+ update_reg(state, REFERENCE); -+ return 0; -+} -+ -+static int Standby(struct tda_state *state) -+{ -+ int status = 0; -+ -+ do { -+ /* Digital clock source = Quarz */ -+ state->Regs[REFERENCE] &= ~0x40; -+ CHK_ERROR(update_reg(state, REFERENCE)); -+ -+ state->Regs[POWER_STATE_2] &= ~0x0F; -+ state->Regs[POWER_STATE_2] |= state->m_isMaster ? 0x08 : 0x0E; -+ CHK_ERROR(update_reg(state, POWER_STATE_2)); -+ } while (0); -+ return status; -+} -+ -+static int attach_init(struct tda_state *state) -+{ -+ int stat = 0; -+ u8 Id[2]; -+ u8 PowerState = 0x00; -+ -+ state->m_Standard = HF_None; -+ -+ /* first read after cold reset sometimes fails on some cards, -+ try twice */ -+ stat = read_regs(state, ID_1, Id, sizeof(Id)); -+ stat = read_regs(state, ID_1, Id, sizeof(Id)); -+ if (stat < 0) -+ return -1; -+ -+ state->m_ID = ((Id[0] & 0x7F) << 8) | Id[1]; -+ state->m_isMaster = ((Id[0] & 0x80) != 0); -+ if (!state->m_isMaster) -+ state->m_bLTEnable = false; -+ -+ pr_info("tda18212dd: ChipID %04x %s\n", state->m_ID, -+ state->m_isMaster ? "master" : "slave"); -+ -+ if (state->m_ID != 18212) -+ return -1; -+ -+ stat = read_reg(state, POWER_STATE_1 , &PowerState); -+ if (stat < 0) -+ return stat; -+ -+ pr_info("tda18212dd: PowerState %02x\n", PowerState); -+ -+ if (state->m_isMaster) { -+ if (PowerState & 0x02) { -+ /* msleep for XTAL Calibration -+ (on a PC this should be long done) */ -+ u8 IRQStatus = 0; -+ int Timeout = 10; -+ -+ while (Timeout > 0) { -+ read_reg(state, IRQ_STATUS, &IRQStatus); -+ if (IRQStatus & 0x20) -+ break; -+ Timeout -= 1; -+ usleep_range(10000, 12000); -+ } -+ if ((IRQStatus & 0x20) == 0) -+ stat = -ETIMEDOUT; -+ } -+ } else { -+ write_reg(state, FLO_MAX, 0x00); -+ write_reg(state, CP_CURRENT, 0x68); -+ } -+ Read(state, state->Regs); -+ -+ PowerOn(state); -+ StartCalibration(state); -+ FinishCalibration(state); -+ Standby(state); -+ -+ { -+ u8 RFCal_Log[12]; -+ -+ read_regs(state, RFCAL_LOG_1, RFCal_Log, sizeof(RFCal_Log)); -+ pr_info("RFCal Log: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", -+ RFCal_Log[0], RFCal_Log[1], -+ RFCal_Log[2], RFCal_Log[3], -+ RFCal_Log[4], RFCal_Log[5], -+ RFCal_Log[6], RFCal_Log[7], -+ RFCal_Log[8], RFCal_Log[9], -+ RFCal_Log[10], RFCal_Log[11]); -+ } -+ return stat; -+} -+ -+static int PowerMeasurement(struct tda_state *state, u8 *pPowerLevel) -+{ -+ int status = 0; -+ -+ do { -+ u8 IRQ = 0; -+ int Timeout = 70; /* 700 ms */ -+ -+ state->Regs[IRQ_CLEAR] |= 0x80; /* Reset IRQ */ -+ CHK_ERROR(update_reg(state, IRQ_CLEAR)); -+ -+ state->Regs[MSM_1] = 0x80; /* power measurement */ -+ state->Regs[MSM_2] = 0x01; /* Start MSM */ -+ CHK_ERROR(update_regs(state, MSM_1, MSM_2)); -+ state->Regs[MSM_2] = 0x00; -+ -+ while (true) { -+ CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); -+ if ((IRQ & 0x80) != 0) -+ break; -+ Timeout -= 1; -+ if (Timeout == 0) { -+ status = -1; -+ break; -+ } -+ usleep_range(10000, 12000); -+ } -+ CHK_ERROR(status); -+ -+ CHK_ERROR(read_reg1(state, INPUT_POWER_LEVEL)); -+ *pPowerLevel = state->Regs[INPUT_POWER_LEVEL] & 0x7F; -+ -+ if (*pPowerLevel > 110) -+ *pPowerLevel = 110; -+ } while (0); -+ /* pr_info("PL %d\n", *pPowerLevel); */ -+ return status; -+} -+ -+static int SetFrequency(struct tda_state *state, u32 Frequency, -+ enum HF_Standard Standard) -+{ -+ int status = 0; -+ struct SStandardParams *StandardParams; -+ u32 f = Frequency / 1000; -+ u8 IRQ = 0; -+ int Timeout = 25; /* 250 ms */ -+ u32 fRatio = Frequency / 16000000; -+ u32 fDelta = Frequency - fRatio * 16000000; -+ -+ if (Standard < HF_DVBT_6MHZ || Standard > HF_DVBC_8MHZ) -+ return -EINVAL; -+ StandardParams = &m_StandardTable[Standard - HF_DVBT_6MHZ]; -+ -+ if (StandardParams->m_IFFrequency == 0) -+ return -EINVAL; -+ state->m_Standard = HF_None; -+ state->m_Frequency = 0; -+ -+ do { -+ /* IF Level */ -+ state->Regs[IF_AGC] = (Standard >= HF_DVBC_6MHZ) ? -+ state->m_IFLevelDVBC : state->m_IFLevelDVBT; -+ CHK_ERROR(update_reg(state, IF_AGC)); -+ -+ /* Standard setup */ -+ state->Regs[IF_1] = StandardParams->m_IF_1; -+ CHK_ERROR(update_reg(state, IF_1)); -+ -+ state->Regs[IR_MIXER_2] = (state->Regs[IR_MIXER_2] & ~0x03) | -+ StandardParams->m_IR_MIXER_2; -+ CHK_ERROR(update_reg(state, IR_MIXER_2)); -+ -+ state->Regs[AGC1_1] = (state->Regs[AGC1_1] & ~0x0F) | -+ StandardParams->m_AGC1_1; -+ CHK_ERROR(update_reg(state, AGC1_1)); -+ -+ state->Regs[AGC2_1] = (state->Regs[AGC2_1] & ~0x0F) | -+ StandardParams->m_AGC2_1; -+ CHK_ERROR(update_reg(state, AGC2_1)); -+ -+ state->Regs[RF_AGC_1] &= ~0xEF; -+ if (Frequency < 291000000) -+ state->Regs[RF_AGC_1] |= StandardParams->m_RF_AGC_1_Low; -+ else -+ state->Regs[RF_AGC_1] |= -+ StandardParams->m_RF_AGC_1_High; -+ CHK_ERROR(update_reg(state, RF_AGC_1)); -+ -+ state->Regs[IR_MIXER_1] = -+ (state->Regs[IR_MIXER_1] & ~0x0F) | -+ StandardParams->m_IR_MIXER_1; -+ CHK_ERROR(update_reg(state, IR_MIXER_1)); -+ -+ state->Regs[AGC5_1] = (state->Regs[AGC5_1] & ~0x1F) | -+ StandardParams->m_AGC5_1; -+ CHK_ERROR(update_reg(state, AGC5_1)); -+ -+ state->Regs[AGCK_1] = (state->Regs[AGCK_1] & ~0x0F) | -+ StandardParams->m_AGCK_1; -+ CHK_ERROR(update_reg(state, AGCK_1)); -+ -+ state->Regs[PSM_1] = (state->Regs[PSM_1] & ~0x20) | -+ StandardParams->m_PSM_1; -+ CHK_ERROR(update_reg(state, PSM_1)); -+ -+ state->Regs[IF_FREQUENCY_1] = (StandardParams->m_IFFrequency / -+ 50000); -+ CHK_ERROR(update_reg(state, IF_FREQUENCY_1)); -+ -+ if (state->m_isMaster && StandardParams->m_LTO_STO_immune) { -+ u8 tmp; -+ u8 RF_Filter_Gain; -+ -+ CHK_ERROR(read_reg(state, RF_AGC_GAIN_1, &tmp)); -+ RF_Filter_Gain = (tmp & 0x30) >> 4; -+ -+ state->Regs[RF_FILTER_1] = -+ (state->Regs[RF_FILTER_1] & ~0x0C) | -+ (RF_Filter_Gain << 2); -+ CHK_ERROR(update_reg(state, RF_FILTER_1)); -+ -+ state->Regs[RF_FILTER_1] |= 0x10; /* Force */ -+ CHK_ERROR(update_reg(state, RF_FILTER_1)); -+ -+ while (RF_Filter_Gain != 0) { -+ RF_Filter_Gain -= 1; -+ state->Regs[RF_FILTER_1] = -+ (state->Regs[RF_FILTER_1] & ~0x0C) | -+ (RF_Filter_Gain << 2); -+ CHK_ERROR(update_reg(state, RF_FILTER_1)); -+ usleep_range(10000, 12000); -+ } -+ CHK_ERROR(status); -+ -+ state->Regs[RF_AGC_1] |= 0x08; -+ CHK_ERROR(update_reg(state, RF_AGC_1)); -+ } -+ -+ state->Regs[IRQ_CLEAR] |= 0x80; /* Reset IRQ */ -+ CHK_ERROR(update_reg(state, IRQ_CLEAR)); -+ -+ CHK_ERROR(PowerOn(state)); -+ -+ state->Regs[RF_FREQUENCY_1] = ((f >> 16) & 0xFF); -+ state->Regs[RF_FREQUENCY_2] = ((f >> 8) & 0xFF); -+ state->Regs[RF_FREQUENCY_3] = (f & 0xFF); -+ CHK_ERROR(update_regs(state, RF_FREQUENCY_1, RF_FREQUENCY_3)); -+ -+ state->Regs[MSM_1] = 0x41; /* Tune */ -+ state->Regs[MSM_2] = 0x01; /* Start MSM */ -+ CHK_ERROR(update_regs(state, MSM_1, MSM_2)); -+ state->Regs[MSM_2] = 0x00; -+ -+ while (true) { -+ CHK_ERROR(read_reg(state, IRQ_STATUS, &IRQ)); -+ if ((IRQ & 0x80) != 0) -+ break; -+ Timeout -= 1; -+ if (Timeout == 0) { -+ status = -1; -+ break; -+ } -+ usleep_range(10000, 12000); -+ } -+ CHK_ERROR(status); -+ -+ if (state->m_isMaster && StandardParams->m_LTO_STO_immune) { -+ state->Regs[RF_AGC_1] &= ~0x08; -+ CHK_ERROR(update_reg(state, RF_AGC_1)); -+ -+ msleep(50); -+ -+ state->Regs[RF_FILTER_1] &= ~0x10; /* remove force */ -+ CHK_ERROR(update_reg(state, RF_FILTER_1)); -+ } -+ -+ /* Spur reduction */ -+ -+ if (Frequency < 72000000) -+ state->Regs[REFERENCE] |= 0x40; /* Set digital clock */ -+ else if (Frequency < 104000000) -+ state->Regs[REFERENCE] &= ~0x40; /*Clear digital clock*/ -+ else if (Frequency < 120000000) -+ state->Regs[REFERENCE] |= 0x40; /* Set digital clock */ -+ else { -+ if (fDelta <= 8000000) { -+ /* Clear or set digital clock */ -+ if (fRatio & 1) -+ state->Regs[REFERENCE] &= ~0x40; -+ else -+ state->Regs[REFERENCE] |= 0x40; -+ } else { -+ /* Set or clear digital clock */ -+ if (fRatio & 1) -+ state->Regs[REFERENCE] |= 0x40; -+ else -+ state->Regs[REFERENCE] &= ~0x40; -+ } -+ -+ } -+ CHK_ERROR(update_reg(state, REFERENCE)); -+ -+ if (StandardParams->m_AGC1_Freeze && state->m_bEnableFreeze) { -+ u8 tmp; -+ int AGC1GainMin = 0; -+ int nSteps = 10; -+ int Step = 0; -+ -+ CHK_ERROR(read_reg(state, AGC1_2, &tmp)); -+ if ((tmp & 0x80) == 0) { -+ state->Regs[AGC1_2] |= 0x80; /* Loop off */ -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ state->Regs[AGC1_2] |= 0x10; /* Force gain */ -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ } -+ /* Adapt */ -+ if (state->Regs[AGC1_1] & 0x40) { /* AGC1_6_15dB set */ -+ AGC1GainMin = 6; -+ nSteps = 4; -+ } -+ while (Step < nSteps) { -+ int Down = 0; -+ int Up = 0, i; -+ u8 AGC1_Gain; -+ -+ Step = Step + 1; -+ -+ for (i = 0; i < 40; i += 1) { -+ CHK_ERROR(read_reg(state, AGC_DET_OUT, -+ &tmp)); -+ Up += (tmp & 0x02) ? 1 : -4; -+ Down += (tmp & 0x01) ? 14 : -1; -+ usleep_range(1000, 2000); -+ } -+ CHK_ERROR(status); -+ AGC1_Gain = (state->Regs[AGC1_2] & 0x0F); -+ if (Up >= 15 && AGC1_Gain != 9) { -+ state->Regs[AGC1_2] = -+ (state->Regs[AGC1_2] & ~0x0F) | -+ (AGC1_Gain + 1); -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ } else if (Down >= 10 && -+ AGC1_Gain != AGC1GainMin) { -+ state->Regs[AGC1_2] = -+ (state->Regs[AGC1_2] & ~0x0F) | -+ (AGC1_Gain - 1); -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ } else -+ Step = nSteps; -+ } -+ } else { -+ state->Regs[AGC1_2] &= ~0x10; /* unforce gain */ -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ state->Regs[AGC1_2] &= ~0x80; /* Loop on */ -+ CHK_ERROR(update_reg(state, AGC1_2)); -+ } -+ -+ state->m_Standard = Standard; -+ state->m_Frequency = Frequency; -+ -+ if (state->m_bPowerMeasurement) -+ PowerMeasurement(state, &state->m_LastPowerLevel); -+ } while (0); -+ -+ return status; -+} -+ -+static int sleep(struct dvb_frontend *fe) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ -+ Standby(state); -+ return 0; -+} -+ -+static int init(struct dvb_frontend *fe) -+{ -+ /* struct tda_state *state = fe->tuner_priv; */ -+ return 0; -+} -+ -+static int release(struct dvb_frontend *fe) -+{ -+ kfree(fe->tuner_priv); -+ fe->tuner_priv = NULL; -+ return 0; -+} -+ -+#ifndef USE_API3 -+static int set_params(struct dvb_frontend *fe) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ struct dtv_frontend_properties *p = &fe->dtv_property_cache; -+ int status = 0; -+ int Standard; -+ u32 bw; -+ -+ bw = (p->bandwidth_hz + 999999) / 1000000; -+ state->m_Frequency = p->frequency; -+ /*pr_info("tuner bw=%u freq=%u\n", bw, state->m_Frequency);*/ -+ if (p->delivery_system == SYS_DVBT || -+ p->delivery_system == SYS_DVBT2 || -+ p->delivery_system == SYS_ISDBT) { -+ switch (bw) { -+ case 6: -+ Standard = HF_DVBT_6MHZ; -+ break; -+ case 7: -+ Standard = HF_DVBT_7MHZ; -+ break; -+ default: -+ case 8: -+ Standard = HF_DVBT_8MHZ; -+ break; -+ } -+ } else if (p->delivery_system == SYS_DVBC_ANNEX_A) { -+ switch (bw) { -+ case 6: -+ Standard = HF_DVBC_6MHZ; -+ break; -+ case 7: -+ Standard = HF_DVBC_7MHZ; -+ break; -+ default: -+ case 8: -+ Standard = HF_DVBC_8MHZ; -+ break; -+ } -+ } else -+ return -EINVAL; -+ -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 1); -+ SetFrequency(state, state->m_Frequency, Standard); -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 0); -+ -+ return status; -+} -+#else -+static int set_params(struct dvb_frontend *fe, -+ struct dvb_frontend_parameters *params) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ int status = 0; -+ int Standard; -+ -+ state->m_Frequency = params->frequency; -+ -+ if (fe->ops.info.type == FE_OFDM) -+ switch (params->u.ofdm.bandwidth) { -+ case BANDWIDTH_6_MHZ: -+ Standard = HF_DVBT_6MHZ; -+ break; -+ case BANDWIDTH_7_MHZ: -+ Standard = HF_DVBT_7MHZ; -+ break; -+ default: -+ case BANDWIDTH_8_MHZ: -+ Standard = HF_DVBT_8MHZ; -+ break; -+ } -+ else if (fe->ops.info.type == FE_QAM) { -+ Standard = HF_DVBC_8MHZ; -+ } else -+ return -EINVAL; -+ -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 1); -+ SetFrequency(state, state->m_Frequency, Standard); -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 0); -+ -+ return status; -+} -+#endif -+ -+static int get_frequency(struct dvb_frontend *fe, u32 *frequency) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ -+ *frequency = state->IF; -+ return 0; -+} -+ -+static int get_rf_strength(struct dvb_frontend *fe, u16 *st) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ -+ *st = state->m_LastPowerLevel; -+ return 0; -+} -+ -+static int get_if(struct dvb_frontend *fe, u32 *frequency) -+{ -+ struct tda_state *state = fe->tuner_priv; -+ -+ state->IF = 0; -+ if (state->m_Standard < HF_DVBT_6MHZ || -+ state->m_Standard > HF_DVBC_8MHZ) -+ return 0; -+ state->IF = m_StandardTable[state->m_Standard - -+ HF_DVBT_6MHZ].m_IFFrequency; -+ *frequency = state->IF; -+ return 0; -+} -+ -+static int get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) -+{ -+ /* struct tda_state *state = fe->tuner_priv; */ -+ /* *bandwidth = priv->bandwidth; */ -+ return 0; -+} -+ -+ -+static struct dvb_tuner_ops tuner_ops = { -+ .info = { -+ .name = "NXP TDA18212", -+ .frequency_min = 47125000, -+ .frequency_max = 865000000, -+ .frequency_step = 62500 -+ }, -+ .init = init, -+ .sleep = sleep, -+ .set_params = set_params, -+ .release = release, -+ .get_frequency = get_frequency, -+ .get_if_frequency = get_if, -+ .get_bandwidth = get_bandwidth, -+ .get_rf_strength = get_rf_strength, -+}; -+ -+struct dvb_frontend *tda18212dd_attach(struct dvb_frontend *fe, -+ struct i2c_adapter *i2c, u8 adr) -+{ -+ struct tda_state *state; -+ int stat; -+ -+ state = kzalloc(sizeof(struct tda_state), GFP_KERNEL); -+ if (!state) -+ return NULL; -+ state->adr = adr; -+ state->i2c = i2c; -+ memcpy(&fe->ops.tuner_ops, &tuner_ops, sizeof(struct dvb_tuner_ops)); -+ init_state(state); -+ -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 1); -+ stat = attach_init(state); -+ if (fe->ops.i2c_gate_ctrl) -+ fe->ops.i2c_gate_ctrl(fe, 0); -+ if (stat < 0) { -+ kfree(state); -+ return 0; -+ } -+ fe->tuner_priv = state; -+ return fe; -+} -+EXPORT_SYMBOL_GPL(tda18212dd_attach); -+ -+MODULE_DESCRIPTION("TDA18212 driver"); -+MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); -+MODULE_LICENSE("GPL"); -+ -+/* -+ * Local variables: -+ * c-basic-offset: 8 -+ * End: -+ */ -diff --git a/drivers/media/dvb-frontends/tda18212dd.h b/drivers/media/dvb-frontends/tda18212dd.h -new file mode 100644 -index 0000000..687fab4a ---- /dev/null -+++ b/drivers/media/dvb-frontends/tda18212dd.h -@@ -0,0 +1,5 @@ -+#ifndef _TDA18212DD_H_ -+#define _TDA18212DD_H_ -+struct dvb_frontend *tda18212dd_attach(struct dvb_frontend *fe, -+ struct i2c_adapter *i2c, u8 adr); -+#endif -diff --git a/drivers/media/dvb-frontends/tda18271c2dd.c b/drivers/media/dvb-frontends/tda18271c2dd.c -index de0a1c1..ad7c72e 100644 ---- a/drivers/media/dvb-frontends/tda18271c2dd.c -+++ b/drivers/media/dvb-frontends/tda18271c2dd.c -@@ -32,10 +32,6 @@ - #include - - #include "dvb_frontend.h" --#include "tda18271c2dd.h" -- --/* Max transfer size done by I2C transfer functions */ --#define MAX_XFER_SIZE 64 - - struct SStandardParam { - s32 m_IFFrequency; -@@ -142,18 +138,11 @@ static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) - static int WriteRegs(struct tda_state *state, - u8 SubAddr, u8 *Regs, u16 nRegs) - { -- u8 data[MAX_XFER_SIZE]; -- -- if (1 + nRegs > sizeof(data)) { -- printk(KERN_WARNING -- "%s: i2c wr: len=%d is too big!\n", -- KBUILD_MODNAME, nRegs); -- return -EINVAL; -- } -+ u8 data[nRegs+1]; - - data[0] = SubAddr; - memcpy(data + 1, Regs, nRegs); -- return i2c_write(state->i2c, state->adr, data, nRegs + 1); -+ return i2c_write(state->i2c, state->adr, data, nRegs+1); - } - - static int WriteReg(struct tda_state *state, u8 SubAddr, u8 Reg) -@@ -1030,7 +1019,7 @@ static int ChannelConfiguration(struct tda_state *state, - state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; - - if ((Standard == HF_FM_Radio) && state->m_bFMInput) -- state->m_Regs[EP4] |= 0x80; -+ state->m_Regs[EP4] |= 80; - - state->m_Regs[MPD] &= ~0x80; - if (Standard > HF_AnalogMax) -diff --git a/drivers/media/dvb-frontends/tda18271c2dd.h b/drivers/media/dvb-frontends/tda18271c2dd.h -index 7ebd8ea..31f7926 100644 ---- a/drivers/media/dvb-frontends/tda18271c2dd.h -+++ b/drivers/media/dvb-frontends/tda18271c2dd.h -@@ -1,9 +1,7 @@ - #ifndef _TDA18271C2DD_H_ - #define _TDA18271C2DD_H_ -- --#include -- --#if IS_REACHABLE(CONFIG_DVB_TDA18271C2DD) -+#if defined(CONFIG_DVB_TDA18271C2DD) || (defined(CONFIG_DVB_TDA18271C2DD_MODULE) \ -+ && defined(MODULE)) - struct dvb_frontend *tda18271c2dd_attach(struct dvb_frontend *fe, - struct i2c_adapter *i2c, u8 adr); - #else -diff --git a/drivers/media/dvb-frontends/tda18271c2dd_maps.h b/drivers/media/dvb-frontends/tda18271c2dd_maps.h -index f3bca5c..b87661b 100644 ---- a/drivers/media/dvb-frontends/tda18271c2dd_maps.h -+++ b/drivers/media/dvb-frontends/tda18271c2dd_maps.h -@@ -5,7 +5,7 @@ enum HF_S { - HF_DVBC_8MHZ, HF_DVBC - }; - --static struct SStandardParam m_StandardTable[] = { -+struct SStandardParam m_StandardTable[] = { - { 0, 0, 0x00, 0x00 }, /* HF_None */ - { 6000000, 7000000, 0x1D, 0x2C }, /* HF_B, */ - { 6900000, 8000000, 0x1E, 0x2C }, /* HF_DK, */ -@@ -27,7 +27,7 @@ static struct SStandardParam m_StandardTable[] = { - { 0, 0, 0x00, 0x00 }, /* HF_DVBC (Unused) */ - }; - --static struct SMap m_BP_Filter_Map[] = { -+struct SMap m_BP_Filter_Map[] = { - { 62000000, 0x00 }, - { 84000000, 0x01 }, - { 100000000, 0x02 }, -@@ -799,14 +799,14 @@ static struct SRFBandMap m_RF_Band_Map[7] = { - { 865000000, 489500000, 697500000, 842000000}, - }; - --static u8 m_Thermometer_Map_1[16] = { -+u8 m_Thermometer_Map_1[16] = { - 60, 62, 66, 64, - 74, 72, 68, 70, - 90, 88, 84, 86, - 76, 78, 82, 80, - }; - --static u8 m_Thermometer_Map_2[16] = { -+u8 m_Thermometer_Map_2[16] = { - 92, 94, 98, 96, - 106, 104, 100, 102, - 122, 120, 116, 118, ++#endif /* _STV6111_H_ */ diff --git a/drivers/media/pci/ddbridge/Kconfig b/drivers/media/pci/ddbridge/Kconfig -index 44e5dc1..d283008 100644 +index 44e5dc1..eed08a4 100644 --- a/drivers/media/pci/ddbridge/Kconfig +++ b/drivers/media/pci/ddbridge/Kconfig -@@ -1,18 +1,23 @@ +@@ -1,11 +1,20 @@ config DVB_DDBRIDGE tristate "Digital Devices bridge support" depends on DVB_CORE && PCI && I2C ++ select STAGING_MEDIA + select DVB_CXD2099 select DVB_LNBP21 if MEDIA_SUBDRV_AUTOSELECT select DVB_STV6110x if MEDIA_SUBDRV_AUTOSELECT select DVB_STV090x if MEDIA_SUBDRV_AUTOSELECT ++ select DVB_LNBH25 if MEDIA_SUBDRV_AUTOSELECT ++ select DVB_STV6111 if MEDIA_SUBDRV_AUTOSELECT ++ select DVB_STV0910 if MEDIA_SUBDRV_AUTOSELECT select DVB_DRXK if MEDIA_SUBDRV_AUTOSELECT ++ select MEDIA_TUNER_TDA18212 if MEDIA_SUBDRV_AUTOSELECT select DVB_TDA18271C2DD if MEDIA_SUBDRV_AUTOSELECT + select DVB_STV0367DD if MEDIA_SUBDRV_AUTOSELECT -+ select DVB_TDA18212DD if MEDIA_SUBDRV_AUTOSELECT + select DVB_CXD2843 if MEDIA_SUBDRV_AUTOSELECT ++ select DVB_MXL5XX if MEDIA_SUBDRV_AUTOSELECT ---help--- Support for cards with the Digital Devices PCI express bridge: - Octopus PCIe Bridge - - Octopus mini PCIe Bridge +@@ -13,6 +22,24 @@ config DVB_DDBRIDGE - Octopus LE -- - DuoFlex S2 Octopus -- - DuoFlex CT Octopus + - DuoFlex S2 Octopus + - DuoFlex CT Octopus - - cineS2(v6) -+ - DuoFlex S2 -+ - DuoFlex CT + - cineS2(v6.x) + - cineCT(v6.x, v7) ++ - Max A8 C2/T2 ++ - Max S8 Say Y if you own such a card and want to use it. ++ ++config DVB_DDBRIDGE_MSIENABLE ++ bool "Enable Message Signaled Interrupts (MSI) per default (EXPERIMENTAL)" ++ depends on DVB_DDBRIDGE ++ depends on PCI_MSI ++ default n ++ ---help--- ++ Use PCI MSI (Message Signaled Interrupts) per default. Enabling this ++ might lead to I2C errors originating from the bridge in conjunction ++ with certain SATA controllers, requiring a reload of the ddbridge ++ module. MSI can still be disabled by passing msi=0 as option, as ++ this will just change the msi option default value. ++ ++ If you're unsure, concerned about stability and don't want to pass ++ module options in case of troubles, say N. diff --git a/drivers/media/pci/ddbridge/Makefile b/drivers/media/pci/ddbridge/Makefile -index 7446c8b..2610161 100644 +index 7446c8b..28e89f0 100644 --- a/drivers/media/pci/ddbridge/Makefile +++ b/drivers/media/pci/ddbridge/Makefile -@@ -2,8 +2,6 @@ +@@ -2,9 +2,7 @@ # Makefile for the ddbridge device driver # -ddbridge-objs := ddbridge-core.o - - obj-$(CONFIG_DVB_DDBRIDGE) += ddbridge.o +-obj-$(CONFIG_DVB_DDBRIDGE) += ddbridge.o ++obj-$(CONFIG_DVB_DDBRIDGE) += ddbridge.o octonet.o ccflags-y += -Idrivers/media/dvb-core/ + ccflags-y += -Idrivers/media/dvb-frontends/ diff --git a/drivers/media/pci/ddbridge/ddbridge-core.c b/drivers/media/pci/ddbridge/ddbridge-core.c -index 9e3492e..c2fc010 100644 +index 6e995ef..82c1938 100644 --- a/drivers/media/pci/ddbridge/ddbridge-core.c +++ b/drivers/media/pci/ddbridge/ddbridge-core.c -@@ -1,7 +1,8 @@ +@@ -1,7 +1,10 @@ /* - * ddbridge.c: Digital Devices PCIe bridge driver + * ddbridge-core.c: Digital Devices bridge core functions ++ * ++ * Copyright (C) 2010-2015 Digital Devices GmbH ++ * Marcus Metzler ++ * Ralph Metzler * - * Copyright (C) 2010-2011 Digital Devices GmbH -+ * Copyright (C) 2010-2013 Digital Devices GmbH -+ * Ralph Metzler * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License -@@ -21,268 +22,245 @@ +@@ -21,306 +24,289 @@ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html */ @@ -22703,7 +18249,15 @@ index 9e3492e..c2fc010 100644 +module_param(tt, int, 0444); +MODULE_PARM_DESC(tt, ""); + -+#define DDB_MAX_ADAPTER 32 ++static int fmode; ++module_param(fmode, int, 0444); ++MODULE_PARM_DESC(fmode, "frontend emulation mode"); ++ ++static int old_quattro; ++module_param(old_quattro, int, 0444); ++MODULE_PARM_DESC(old_quattro, "old quattro LNB input order "); ++ ++#define DDB_MAX_ADAPTER 64 +static struct ddb *ddbs[DDB_MAX_ADAPTER]; DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); @@ -22758,32 +18312,22 @@ index 9e3492e..c2fc010 100644 - return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; + u32 i; + -+ for (i = 0; i < dev->info->port_num * 2; i++) ++ for (i = 0; i < dev->link[0].info->port_num * 2; i++) + ddb_set_dma_table(dev, dev->input[i].dma); -+ for (i = 0; i < dev->info->port_num; i++) ++ for (i = 0; i < dev->link[0].info->port_num; i++) + ddb_set_dma_table(dev, dev->output[i].dma); } -static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) -+ -+/****************************************************************************/ -+/****************************************************************************/ -+/****************************************************************************/ -+ -+static void ddb_redirect_dma(struct ddb *dev, -+ struct ddb_dma *sdma, -+ struct ddb_dma *ddma) - { +-{ - struct ddb *dev = i2c->dev; -- int stat; +- long stat; - u32 val; -+ u32 i, base; -+ u64 mem; - i2c->done = 0; - ddbwritel((adr << 9) | cmd, i2c->regs + I2C_COMMAND); - stat = wait_event_timeout(i2c->wq, i2c->done == 1, HZ); -- if (stat <= 0) { +- if (stat == 0) { - printk(KERN_ERR "I2C timeout\n"); - { /* MSI debugging*/ - u32 istat = ddbreadl(INTERRUPT_STATUS); @@ -22791,22 +18335,21 @@ index 9e3492e..c2fc010 100644 - ddbwritel(istat, INTERRUPT_ACK); - } - return -EIO; -+ sdma->bufreg = ddma->bufreg; -+ base = DMA_BASE_ADDRESS_TABLE + sdma->nr * 0x100; -+ for (i = 0; i < ddma->num; i++) { -+ mem = ddma->pbuf[i]; -+ ddbwritel(dev, mem & 0xffffffff, base + i * 8); -+ ddbwritel(dev, mem >> 32, base + i * 8 + 4); - } +- } - val = ddbreadl(i2c->regs+I2C_COMMAND); - if (val & 0x70000) - return -EIO; - return 0; - } +-} ++/****************************************************************************/ ++/****************************************************************************/ ++/****************************************************************************/ -static int ddb_i2c_master_xfer(struct i2c_adapter *adapter, - struct i2c_msg msg[], int num) -+static int ddb_unredirect(struct ddb_port *port) ++static void ddb_redirect_dma(struct ddb *dev, ++ struct ddb_dma *sdma, ++ struct ddb_dma *ddma) { - struct ddb_i2c *i2c = (struct ddb_i2c *)i2c_get_adapdata(adapter); - struct ddb *dev = i2c->dev; @@ -22814,8 +18357,8 @@ index 9e3492e..c2fc010 100644 - - if (num) - addr = msg[0].addr; -+ struct ddb_input *oredi, *iredi = 0; -+ struct ddb_output *iredo = 0; ++ u32 i, base; ++ u64 mem; - if (num == 2 && msg[1].flags & I2C_M_RD && - !(msg[0].flags & I2C_M_RD)) { @@ -22829,13 +18372,25 @@ index 9e3492e..c2fc010 100644 - msg[1].len); - return num; - } -- } -- ++ sdma->bufreg = ddma->bufreg; ++ base = DMA_BASE_ADDRESS_TABLE + sdma->nr * 0x100; ++ for (i = 0; i < ddma->num; i++) { ++ mem = ddma->pbuf[i]; ++ ddbwritel(dev, mem & 0xffffffff, base + i * 8); ++ ddbwritel(dev, mem >> 32, base + i * 8 + 4); + } ++} + - if (num == 1 && !(msg[0].flags & I2C_M_RD)) { - ddbcpyto(I2C_TASKMEM_BASE + i2c->wbuf, msg[0].buf, msg[0].len); - ddbwritel(msg[0].len, i2c->regs + I2C_TASKLENGTH); - if (!ddb_i2c_cmd(i2c, addr, 2)) - return num; ++static int ddb_unredirect(struct ddb_port *port) ++{ ++ struct ddb_input *oredi, *iredi = 0; ++ struct ddb_output *iredo = 0; ++ + /*pr_info("unredirect %d.%d\n", port->dev->nr, port->nr);*/ + mutex_lock(&redirect_lock); + if (port->output->dma->running) { @@ -23015,7 +18570,7 @@ index 9e3492e..c2fc010 100644 + dir ? DMA_TO_DEVICE : + DMA_FROM_DEVICE); + kfree(dma->vbuf[i]); -+ dma->vbuf[i] = 0; ++ dma->vbuf[i] = NULL; + } } } @@ -23027,8 +18582,7 @@ index 9e3492e..c2fc010 100644 - u32 i, j, base; - u64 mem; - dma_addr_t *pbuf; -+ int i; - +- - for (i = 0; i < dev->info->port_num * 2; i++) { - base = DMA_BASE_ADDRESS_TABLE + i * 0x100; - pbuf = dev->input[i].pbuf; @@ -23045,6 +18599,8 @@ index 9e3492e..c2fc010 100644 - mem = pbuf[j]; - ddbwritel(mem & 0xffffffff, base + j * 8); - ddbwritel(mem >> 32, base + j * 8 + 4); ++ int i; ++ + if (!dma) + return 0; + for (i = 0; i < dma->num; i++) { @@ -23078,9 +18634,9 @@ index 9e3492e..c2fc010 100644 + return; + for (i = 0; i < dma->num; i++) { + if (dma->vbuf[i]) { -+ pci_free_consistent(pdev, dma->size, ++ dma_free_coherent(&pdev->dev, dma->size, + dma->vbuf[i], dma->pbuf[i]); -+ dma->vbuf[i] = 0; ++ dma->vbuf[i] = NULL; } } } @@ -23097,8 +18653,8 @@ index 9e3492e..c2fc010 100644 + if (!dma) + return 0; + for (i = 0; i < dma->num; i++) { -+ dma->vbuf[i] = pci_alloc_consistent(pdev, dma->size, -+ &dma->pbuf[i]); ++ dma->vbuf[i] = dma_alloc_coherent(&pdev->dev, dma->size, ++ &dma->pbuf[i], GFP_KERNEL); + if (!dma->vbuf[i]) return -ENOMEM; } @@ -23108,7 +18664,11 @@ index 9e3492e..c2fc010 100644 static int ddb_buffers_alloc(struct ddb *dev) { -@@ -293,34 +271,24 @@ static int ddb_buffers_alloc(struct ddb *dev) + int i; + struct ddb_port *port; + +- for (i = 0; i < dev->info->port_num; i++) { ++ for (i = 0; i < dev->link[0].info->port_num; i++) { port = &dev->port[i]; switch (port->class) { case DDB_PORT_TUNER: @@ -23116,30 +18676,42 @@ index 9e3492e..c2fc010 100644 - port->input[0]->pbuf, - port->input[0]->dma_buf_size, - port->input[0]->dma_buf_num) < 0) -+ if (dma_alloc(dev->pdev, port->input[0]->dma, 0) < 0) - return -1; +- return -1; - if (io_alloc(dev->pdev, port->input[1]->vbuf, - port->input[1]->pbuf, - port->input[1]->dma_buf_size, - port->input[1]->dma_buf_num) < 0) -+ if (dma_alloc(dev->pdev, port->input[1]->dma, 0) < 0) - return -1; +- return -1; ++ if (port->input[0]->dma) ++ if (dma_alloc(dev->pdev, port->input[0]->dma, 0) ++ < 0) ++ return -1; ++ if (port->input[1]->dma) ++ if (dma_alloc(dev->pdev, port->input[1]->dma, 0) ++ < 0) ++ return -1; break; case DDB_PORT_CI: - if (io_alloc(dev->pdev, port->input[0]->vbuf, - port->input[0]->pbuf, - port->input[0]->dma_buf_size, - port->input[0]->dma_buf_num) < 0) -+ case DDB_PORT_LOOP: -+ if (dma_alloc(dev->pdev, port->input[0]->dma, 0) < 0) - return -1; +- return -1; - if (io_alloc(dev->pdev, port->output->vbuf, - port->output->pbuf, - port->output->dma_buf_size, - port->output->dma_buf_num) < 0) +- return -1; ++ case DDB_PORT_LOOP: ++ if (port->input[0]->dma) ++ if (dma_alloc(dev->pdev, port->input[0]->dma, 0) ++ < 0) ++ return -1; + case DDB_PORT_MOD: -+ if (dma_alloc(dev->pdev, port->output->dma, 1) < 0) - return -1; ++ if (port->output->dma) ++ if (dma_alloc(dev->pdev, port->output->dma, 1) ++ < 0) ++ return -1; break; default: break; @@ -23150,9 +18722,12 @@ index 9e3492e..c2fc010 100644 return 0; } -@@ -331,287 +299,839 @@ static void ddb_buffers_free(struct ddb *dev) +@@ -329,111 +315,198 @@ static void ddb_buffers_free(struct ddb *dev) + int i; + struct ddb_port *port; - for (i = 0; i < dev->info->port_num; i++) { +- for (i = 0; i < dev->info->port_num; i++) { ++ for (i = 0; i < dev->link[0].info->port_num; i++) { port = &dev->port[i]; - io_free(dev->pdev, port->input[0]->vbuf, - port->input[0]->pbuf, @@ -23167,11 +18742,11 @@ index 9e3492e..c2fc010 100644 - port->output->dma_buf_size, - port->output->dma_buf_num); + -+ if (port->input[0]) ++ if (port->input[0] && port->input[0]->dma) + dma_free(dev->pdev, port->input[0]->dma, 0); -+ if (port->input[1]) ++ if (port->input[1] && port->input[1]->dma) + dma_free(dev->pdev, port->input[1]->dma, 0); -+ if (port->output) ++ if (port->output && port->output->dma) + dma_free(dev->pdev, port->output->dma, 1); } } @@ -23218,13 +18793,10 @@ index 9e3492e..c2fc010 100644 + } + if (output->port->class != DDB_PORT_MOD) { + if (output->port->input[0]->port->class == DDB_PORT_LOOP) -+ /*ddbwritel(dev, 0x15, TS_OUTPUT_CONTROL(output->nr)); -+ ddbwritel(dev, 0x45, -+ TS_OUTPUT_CONTROL(output->nr));*/ + ddbwritel(dev, (1 << 13) | 0x15, + TS_OUTPUT_CONTROL(output->nr)); + else -+ ddbwritel(dev, 0x1d, TS_OUTPUT_CONTROL(output->nr)); ++ ddbwritel(dev, 0x11d, TS_OUTPUT_CONTROL(output->nr)); + } + if (output->dma) { + output->dma->running = 1; @@ -23262,28 +18834,77 @@ index 9e3492e..c2fc010 100644 static void ddb_input_stop(struct ddb_input *input) { struct ddb *dev = input->port->dev; ++ u32 tag = DDB_LINK_TAG(input->port->lnr); ++ ++ if (input->dma) ++ spin_lock_irq(&input->dma->lock); ++ ddbwritel(dev, 0, tag | TS_INPUT_CONTROL(input->nr)); ++ if (input->dma) { ++ ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma->nr)); ++ input->dma->running = 0; ++ spin_unlock_irq(&input->dma->lock); ++ } ++} ++ ++static void ddb_input_start(struct ddb_input *input) ++{ ++ struct ddb *dev = input->port->dev; ++ /* u32 tsbase = TS_INPUT_BASE + input->nr * 0x10; */ ++ u32 tag = DDB_LINK_TAG(input->port->lnr); ++ ++ if (input->dma) { ++ spin_lock_irq(&input->dma->lock); ++ input->dma->cbuf = 0; ++ input->dma->coff = 0; ++ input->dma->stat = 0; ++ ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma->nr)); ++ } ++ ddbwritel(dev, 0, tag | TS_INPUT_CONTROL2(input->nr)); ++ ddbwritel(dev, 0, tag | TS_INPUT_CONTROL(input->nr)); ++ ddbwritel(dev, 2, tag | TS_INPUT_CONTROL(input->nr)); ++ ddbwritel(dev, 0, tag | TS_INPUT_CONTROL(input->nr)); ++ ++ if (input->dma) { ++ ddbwritel(dev, input->dma->bufreg, ++ DMA_BUFFER_SIZE(input->dma->nr)); ++ ddbwritel(dev, 0, DMA_BUFFER_ACK(input->dma->nr)); ++ ddbwritel(dev, 1, DMA_BASE_WRITE); ++ ddbwritel(dev, 3, DMA_BUFFER_CONTROL(input->dma->nr)); ++ } ++ if (dev->link[0].info->type == DDB_OCTONET) ++ ddbwritel(dev, 0x01, tag | TS_INPUT_CONTROL(input->nr)); ++ else ++ ddbwritel(dev, 0x09, tag | TS_INPUT_CONTROL(input->nr)); ++ if (input->dma) { ++ input->dma->running = 1; ++ spin_unlock_irq(&input->dma->lock); ++ } ++} - spin_lock_irq(&input->lock); - ddbwritel(0, TS_INPUT_CONTROL(input->nr)); - ddbwritel(0, DMA_BUFFER_CONTROL(input->nr)); - input->running = 0; - spin_unlock_irq(&input->lock); -+ if (input->dma) -+ spin_lock_irq(&input->dma->lock); -+ ddbwritel(dev, 0, TS_INPUT_CONTROL(input->nr)); -+ if (input->dma) { -+ ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma->nr)); -+ input->dma->running = 0; -+ spin_unlock_irq(&input->dma->lock); -+ } -+ /*pr_info("input_stop %d.%d\n", dev->nr, input->nr);*/ ++ ++static int ddb_dvb_ns_input_start(struct ddb_input *input) ++{ ++ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; ++ ++ if (!dvb->users) ++ ddb_input_start(input); ++ ++ return ++dvb->users; } -static void ddb_output_start(struct ddb_output *output) -+static void ddb_input_start(struct ddb_input *input) ++static int ddb_dvb_ns_input_stop(struct ddb_input *input) { - struct ddb *dev = output->port->dev; -+ struct ddb *dev = input->port->dev; ++ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; ++ ++ if (--dvb->users) ++ return dvb->users; - spin_lock_irq(&output->lock); - output->cbuf = 0; @@ -23304,67 +18925,14 @@ index 9e3492e..c2fc010 100644 - ddbwritel(0x1d, TS_OUTPUT_CONTROL(output->nr)); - output->running = 1; - spin_unlock_irq(&output->lock); -+ if (input->dma) { -+ spin_lock_irq(&input->dma->lock); -+ input->dma->cbuf = 0; -+ input->dma->coff = 0; -+ input->dma->stat = 0; -+ ddbwritel(dev, 0, DMA_BUFFER_CONTROL(input->dma->nr)); -+ } -+ ddbwritel(dev, 0, TS_INPUT_CONTROL2(input->nr)); -+ ddbwritel(dev, 0, TS_INPUT_CONTROL(input->nr)); -+ ddbwritel(dev, 2, TS_INPUT_CONTROL(input->nr)); -+ ddbwritel(dev, 0, TS_INPUT_CONTROL(input->nr)); -+ -+ if (input->dma) { -+ ddbwritel(dev, input->dma->bufreg, -+ DMA_BUFFER_SIZE(input->dma->nr)); -+ ddbwritel(dev, 0, DMA_BUFFER_ACK(input->dma->nr)); -+ ddbwritel(dev, 1, DMA_BASE_WRITE); -+ ddbwritel(dev, 3, DMA_BUFFER_CONTROL(input->dma->nr)); -+ } -+ if (dev->info->type == DDB_OCTONET) -+ ddbwritel(dev, 0x01, TS_INPUT_CONTROL(input->nr)); -+ else -+ ddbwritel(dev, 0x09, TS_INPUT_CONTROL(input->nr)); -+ if (input->dma) { -+ input->dma->running = 1; -+ spin_unlock_irq(&input->dma->lock); -+ } -+ /*pr_info("input_start %d.%d\n", dev->nr, input->nr);*/ ++ ddb_input_stop(input); ++ return 0; } -static void ddb_output_stop(struct ddb_output *output) -+ -+static int ddb_dvb_input_start(struct ddb_input *input) ++static void ddb_input_start_all(struct ddb_input *input) { - struct ddb *dev = output->port->dev; -+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; -+ -+ if (!dvb->users) -+ ddb_input_start(input); -+ -+ return ++dvb->users; -+} -+ -+static int ddb_dvb_input_stop(struct ddb_input *input) -+{ -+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - -- spin_lock_irq(&output->lock); -- ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); -- ddbwritel(0, DMA_BUFFER_CONTROL(output->nr + 8)); -- output->running = 0; -- spin_unlock_irq(&output->lock); -+ if (--dvb->users) -+ return dvb->users; -+ -+ ddb_input_stop(input); -+ return 0; -+} -+ -+static void ddb_input_start_all(struct ddb_input *input) -+{ + struct ddb_input *i = input; + struct ddb_output *o; + @@ -23383,7 +18951,12 @@ index 9e3492e..c2fc010 100644 +{ + struct ddb_input *i = input; + struct ddb_output *o; -+ + +- spin_lock_irq(&output->lock); +- ddbwritel(0, TS_OUTPUT_CONTROL(output->nr)); +- ddbwritel(0, DMA_BUFFER_CONTROL(output->nr + 8)); +- output->running = 0; +- spin_unlock_irq(&output->lock); + mutex_lock(&redirect_lock); + ddb_input_stop(input); + while (i && (o = i->redo)) { @@ -23418,30 +18991,8 @@ index 9e3492e..c2fc010 100644 if (diff <= 0 || diff > 188) return 188; return 0; - } - -+#if 0 -+static u32 ddb_dma_free(struct ddb_dma *dma) -+{ -+ u32 idx, off, stat = dma->stat; -+ s32 p1, p2, diff; -+ -+ idx = (stat >> 11) & 0x1f; -+ off = (stat & 0x7ff) << 7; -+ -+ p1 = idx * dma->size + off; -+ p2 = dma->cbuf * dma->size + dma->coff; -+ -+ diff = p1 - p2; -+ if (diff <= 0) -+ diff += dma->num * dma->size; -+ return diff; -+} -+#endif -+ - static ssize_t ddb_output_write(struct ddb_output *output, -- const __user u8 *buf, size_t count) -+ const u8 *buf, size_t count) +@@ -443,46 +516,53 @@ static ssize_t ddb_output_write(struct ddb_output *output, + const __user u8 *buf, size_t count) { struct ddb *dev = output->port->dev; - u32 idx, off, stat = output->stat; @@ -23510,82 +19061,7 @@ index 9e3492e..c2fc010 100644 } return count - left; } - -+#if 0 -+static u32 ddb_input_free_bytes(struct ddb_input *input) -+{ -+ struct ddb *dev = input->port->dev; -+ u32 idx, off, stat = input->dma->stat; -+ u32 ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(input->dma->nr)); -+ -+ idx = (stat >> 11) & 0x1f; -+ off = (stat & 0x7ff) << 7; -+ -+ if (ctrl & 4) -+ return 0; -+ if (input->dma->cbuf != idx) -+ return 1; -+ return 0; -+} -+ -+ -+ -+static s32 ddb_output_used_bufs(struct ddb_output *output) -+{ -+ u32 idx, off, stat, ctrl; -+ s32 diff; -+ -+ spin_lock_irq(&output->dma->lock); -+ stat = output->dma->stat; -+ ctrl = output->dma->ctrl; -+ spin_unlock_irq(&output->dma->lock); -+ -+ idx = (stat >> 11) & 0x1f; -+ off = (stat & 0x7ff) << 7; -+ -+ if (ctrl & 4) -+ return 0; -+ diff = output->dma->cbuf - idx; -+ if (diff == 0 && off < output->dma->coff) -+ return 0; -+ if (diff <= 0) -+ diff += output->dma->num; -+ return diff; -+} -+ -+static s32 ddb_input_free_bufs(struct ddb_input *input) -+{ -+ u32 idx, off, stat, ctrl; -+ s32 free; -+ -+ spin_lock_irq(&input->dma->lock); -+ ctrl = input->dma->ctrl; -+ stat = input->dma->stat; -+ spin_unlock_irq(&input->dma->lock); -+ if (ctrl & 4) -+ return 0; -+ idx = (stat >> 11) & 0x1f; -+ off = (stat & 0x7ff) << 7; -+ free = input->dma->cbuf - idx; -+ if (free == 0 && off < input->dma->coff) -+ return 0; -+ if (free <= 0) -+ free += input->dma->num; -+ return free - 1; -+} -+ -+static u32 ddb_output_ok(struct ddb_output *output) -+{ -+ struct ddb_input *input = output->port->input[0]; -+ s32 diff; -+ -+ diff = ddb_input_free_bufs(input) - ddb_output_used_bufs(output); -+ if (diff > 0) -+ return 1; -+ return 0; -+} -+#endif -+ +@@ -490,81 +570,276 @@ static ssize_t ddb_output_write(struct ddb_output *output, static u32 ddb_input_avail(struct ddb_input *input) { struct ddb *dev = input->port->dev; @@ -23611,7 +19087,8 @@ index 9e3492e..c2fc010 100644 } -static ssize_t ddb_input_read(struct ddb_input *input, __user u8 *buf, size_t count) -+static size_t ddb_input_read(struct ddb_input *input, u8 *buf, size_t count) ++static size_t ddb_input_read(struct ddb_input *input, ++ __user u8 *buf, size_t count) { struct ddb *dev = input->port->dev; u32 left = count; @@ -23666,22 +19143,16 @@ index 9e3492e..c2fc010 100644 -/******************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ - --#if 0 --static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe) -+static ssize_t ts_write(struct file *file, const char *buf, ++ ++static ssize_t ts_write(struct file *file, const __user char *buf, + size_t count, loff_t *ppos) - { -- int i; ++{ + struct dvb_device *dvbdev = file->private_data; + struct ddb_output *output = dvbdev->priv; + struct ddb *dev = output->port->dev; + size_t left = count; + int stat; - -- for (i = 0; i < dev->info->port_num * 2; i++) { -- if (dev->input[i].fe == fe) -- return &dev->input[i]; ++ + if (!dev->has_dma) + return -EINVAL; + while (left) { @@ -23698,32 +19169,20 @@ index 9e3492e..c2fc010 100644 + return stat; + buf += stat; + left -= stat; - } -- return NULL; ++ } + return (left == count) ? -EAGAIN : (count - left); - } --#endif - --static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) -+static ssize_t ts_read(struct file *file, char *buf, ++} ++ ++static ssize_t ts_read(struct file *file, __user char *buf, + size_t count, loff_t *ppos) - { -- struct ddb_input *input = fe->sec_priv; -- struct ddb_port *port = input->port; -- int status; ++{ + struct dvb_device *dvbdev = file->private_data; + struct ddb_output *output = dvbdev->priv; + struct ddb_input *input = output->port->input[0]; + struct ddb *dev = output->port->dev; + size_t left = count; + int stat; - -- if (enable) { -- mutex_lock(&port->i2c_gate_lock); -- status = input->gate_ctrl(fe, 1); -- } else { -- status = input->gate_ctrl(fe, 0); -- mutex_unlock(&port->i2c_gate_lock); ++ + if (!dev->has_dma) + return -EINVAL; + while (left) { @@ -23740,36 +19199,18 @@ index 9e3492e..c2fc010 100644 + return stat; + left -= stat; + buf += stat; - } -- return status; ++ } + return (count && (left == count)) ? -EAGAIN : (count - left); - } - --static int demod_attach_drxk(struct ddb_input *input) ++} ++ +static unsigned int ts_poll(struct file *file, poll_table *wait) - { -- struct i2c_adapter *i2c = &input->port->i2c->adap; -- struct dvb_frontend *fe; -- struct drxk_config config; ++{ + struct dvb_device *dvbdev = file->private_data; + struct ddb_output *output = dvbdev->priv; + struct ddb_input *input = output->port->input[0]; - -- memset(&config, 0, sizeof(config)); -- config.microcode_name = "drxk_a3.mc"; -- config.qam_demod_parameter_count = 4; -- config.adr = 0x29 + (input->nr & 1); ++ + unsigned int mask = 0; - -- fe = input->fe = dvb_attach(drxk_attach, &config, i2c); -- if (!input->fe) { -- printk(KERN_ERR "No DRXK found!\n"); -- return -ENODEV; -- } -- fe->sec_priv = input; -- input->gate_ctrl = fe->ops.i2c_gate_ctrl; -- fe->ops.i2c_gate_ctrl = drxk_gate_ctrl; -- return 0; ++ + poll_wait(file, &input->dma->wq, wait); + poll_wait(file, &output->dma->wq, wait); + if (ddb_input_avail(input) >= 188) @@ -23777,17 +19218,20 @@ index 9e3492e..c2fc010 100644 + if (ddb_output_free(output) >= 188) + mask |= POLLOUT | POLLWRNORM; + return mask; - } ++} --static int tuner_attach_tda18271(struct ddb_input *input) +-#if 0 +-static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe) +static int ts_release(struct inode *inode, struct file *file) { -- struct i2c_adapter *i2c = &input->port->i2c->adap; -- struct dvb_frontend *fe; +- int i; + struct dvb_device *dvbdev = file->private_data; + struct ddb_output *output = dvbdev->priv; + struct ddb_input *input = output->port->input[0]; -+ + +- for (i = 0; i < dev->info->port_num * 2; i++) { +- if (dev->input[i].fe == fe) +- return &dev->input[i]; + if ((file->f_flags & O_ACCMODE) == O_RDONLY) { + if (!input) + return -EINVAL; @@ -23796,10 +19240,13 @@ index 9e3492e..c2fc010 100644 + if (!output) + return -EINVAL; + ddb_output_stop(output); -+ } + } +- return NULL; + return dvb_generic_release(inode, file); -+} -+ + } +-#endif + +-static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) +static int ts_open(struct inode *inode, struct file *file) +{ + int err; @@ -23815,7 +19262,8 @@ index 9e3492e..c2fc010 100644 + } else if ((file->f_flags & O_ACCMODE) == O_WRONLY) { + if (!output) + return -EINVAL; -+ } ++ } else ++ return -EINVAL; + err = dvb_generic_open(inode, file); + if (err < 0) + return err; @@ -23904,116 +19352,75 @@ index 9e3492e..c2fc010 100644 +}; + + -+#if 0 -+static struct ddb_input *fe2input(struct ddb *dev, struct dvb_frontend *fe) -+{ -+ int i; -+ -+ for (i = 0; i < dev->info->port_num * 2; i++) { -+ if (dev->input[i].fe == fe) -+ return &dev->input[i]; -+ } -+ return NULL; -+} -+#endif -+ +static int locked_gate_ctrl(struct dvb_frontend *fe, int enable) -+{ -+ struct ddb_input *input = fe->sec_priv; -+ struct ddb_port *port = input->port; + { + struct ddb_input *input = fe->sec_priv; + struct ddb_port *port = input->port; + struct ddb_dvb *dvb = &port->dvb[input->nr & 1]; -+ int status; -+ -+ if (enable) { -+ mutex_lock(&port->i2c_gate_lock); + int status; + + if (enable) { + mutex_lock(&port->i2c_gate_lock); +- status = input->gate_ctrl(fe, 1); + status = dvb->i2c_gate_ctrl(fe, 1); -+ } else { + } else { +- status = input->gate_ctrl(fe, 0); + status = dvb->i2c_gate_ctrl(fe, 0); -+ mutex_unlock(&port->i2c_gate_lock); -+ } -+ return status; -+} -+ -+#if IS_ENABLED(CONFIG_DVB_DRXK) -+static int demod_attach_drxk(struct ddb_input *input) -+{ -+ struct i2c_adapter *i2c = &input->port->i2c->adap; + mutex_unlock(&port->i2c_gate_lock); + } + return status; +@@ -573,45 +848,158 @@ static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) + static int demod_attach_drxk(struct ddb_input *input) + { + struct i2c_adapter *i2c = &input->port->i2c->adap; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; -+ struct dvb_frontend *fe; -+ struct drxk_config config; -+ -+ memset(&config, 0, sizeof(config)); -+ config.adr = 0x29 + (input->nr & 1); + struct dvb_frontend *fe; + struct drxk_config config; + + memset(&config, 0, sizeof(config)); +- config.microcode_name = "drxk_a3.mc"; +- config.qam_demod_parameter_count = 4; + config.adr = 0x29 + (input->nr & 1); + config.microcode_name = "drxk_a3.mc"; -+ + +- fe = input->fe = dvb_attach(drxk_attach, &config, i2c); +- if (!input->fe) { +- printk(KERN_ERR "No DRXK found!\n"); + fe = dvb->fe = dvb_attach(drxk_attach, &config, i2c); + if (!fe) { + pr_err("No DRXK found!\n"); -+ return -ENODEV; -+ } -+ fe->sec_priv = input; + return -ENODEV; + } + fe->sec_priv = input; +- input->gate_ctrl = fe->ops.i2c_gate_ctrl; +- fe->ops.i2c_gate_ctrl = drxk_gate_ctrl; + dvb->i2c_gate_ctrl = fe->ops.i2c_gate_ctrl; + fe->ops.i2c_gate_ctrl = locked_gate_ctrl; -+ return 0; -+} -+#endif -+ -+#if 0 -+struct stv0367_config stv0367_0 = { -+ .demod_address = 0x1f, -+ .xtal = 27000000, -+ .if_khz = 5000, -+ .if_iq_mode = FE_TER_NORMAL_IF_TUNER, -+ .ts_mode = STV0367_SERIAL_PUNCT_CLOCK, -+ .clk_pol = STV0367_RISINGEDGE_CLOCK, -+}; -+ -+struct stv0367_config stv0367_1 = { -+ .demod_address = 0x1e, -+ .xtal = 27000000, -+ .if_khz = 5000, -+ .if_iq_mode = FE_TER_NORMAL_IF_TUNER, -+ .ts_mode = STV0367_SERIAL_PUNCT_CLOCK, -+ .clk_pol = STV0367_RISINGEDGE_CLOCK, -+}; -+ -+ -+static int demod_attach_stv0367(struct ddb_input *input) -+{ -+ struct i2c_adapter *i2c = &input->port->i2c->adap; -+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; -+ struct dvb_frontend *fe; -+ -+ fe = dvb->fe = dvb_attach(stv0367ter_attach, -+ (input->nr & 1) ? &stv0367_1 : &stv0367_0, -+ i2c); -+ if (!dvb->fe) { -+ pr_err("No stv0367 found!\n"); -+ return -ENODEV; -+ } -+ fe->sec_priv = input; -+ dvb->i2c_gate_ctrl = fe->ops.i2c_gate_ctrl; -+ fe->ops.i2c_gate_ctrl = locked_gate_ctrl; -+ return 0; -+} -+#endif -+ + return 0; + } + +-static int tuner_attach_tda18271(struct ddb_input *input) +-{ +- struct i2c_adapter *i2c = &input->port->i2c->adap; +- struct dvb_frontend *fe; +struct cxd2843_cfg cxd2843_0 = { + .adr = 0x6c, ++ .ts_clock = 1, +}; -+ + +- if (input->fe->ops.i2c_gate_ctrl) +- input->fe->ops.i2c_gate_ctrl(input->fe, 1); +- fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60); +struct cxd2843_cfg cxd2843_1 = { + .adr = 0x6d, ++ .ts_clock = 1, +}; + +struct cxd2843_cfg cxd2843p_0 = { + .adr = 0x6c, + .parallel = 1, +}; - -- if (input->fe->ops.i2c_gate_ctrl) -- input->fe->ops.i2c_gate_ctrl(input->fe, 1); -- fe = dvb_attach(tda18271c2dd_attach, input->fe, i2c, 0x60); ++ +struct cxd2843_cfg cxd2843p_1 = { + .adr = 0x6d, + .parallel = 1, @@ -24043,25 +19450,18 @@ index 9e3492e..c2fc010 100644 + return 0; +} + -+struct stv0367_cfg stv0367dd_0 = { -+ .adr = 0x1f, -+ .xtal = 27000000, -+}; -+ -+struct stv0367_cfg stv0367dd_1 = { -+ .adr = 0x1e, -+ .xtal = 27000000, -+}; -+ +static int demod_attach_stv0367dd(struct ddb_input *input) +{ + struct i2c_adapter *i2c = &input->port->i2c->adap; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + struct dvb_frontend *fe; ++ struct stv0367dd_cfg cfg = { .cont_clock = 0 }; + -+ fe = dvb->fe = dvb_attach(stv0367_attach, i2c, -+ (input->nr & 1) ? -+ &stv0367dd_1 : &stv0367dd_0, ++ cfg.adr = 0x1f - (input->nr & 1); ++ if (input->port->dev->link[input->port->lnr].info->con_clock) ++ cfg.cont_clock = 1; ++ fe = dvb->fe = dvb_attach(stv0367dd_attach, i2c, ++ &cfg, + &dvb->fe2); + if (!dvb->fe) { + pr_err("No stv0367 found!\n"); @@ -24097,46 +19497,50 @@ index 9e3492e..c2fc010 100644 -/******************************************************************************/ -/******************************************************************************/ -/******************************************************************************/ -+static int tuner_attach_tda18212dd(struct ddb_input *input) -+{ -+ struct i2c_adapter *i2c = &input->port->i2c->adap; -+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; -+ struct dvb_frontend *fe; -+ -+ fe = dvb_attach(tda18212dd_attach, dvb->fe, i2c, -+ (input->nr & 1) ? 0x63 : 0x60); -+ if (!fe) { -+ pr_err("No TDA18212 found!\n"); -+ return -ENODEV; -+ } -+ return 0; -+} -+ -+#ifdef CONFIG_DVB_TDA18212 -+struct tda18212_config tda18212_0 = { -+ .i2c_address = 0x60, -+}; -+ -+struct tda18212_config tda18212_1 = { -+ .i2c_address = 0x63, -+}; -+ +static int tuner_attach_tda18212(struct ddb_input *input) +{ -+ struct i2c_adapter *i2c = &input->port->i2c->adap; ++ struct i2c_adapter *adapter = &input->port->i2c->adap; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; -+ struct dvb_frontend *fe; -+ struct tda18212_config *cfg; ++ struct i2c_client *client; ++ struct tda18212_config config = { ++ .fe = dvb->fe, ++ .if_dvbt_6 = 3550, ++ .if_dvbt_7 = 3700, ++ .if_dvbt_8 = 4150, ++ .if_dvbt2_6 = 3250, ++ .if_dvbt2_7 = 4000, ++ .if_dvbt2_8 = 4000, ++ .if_dvbc = 5000, ++ .init_flags = TDA18212_INIT_RETRY, ++ }; ++ struct i2c_board_info board_info = { ++ .type = "tda18212", ++ .platform_data = &config, ++ }; + -+ cfg = (input->nr & 1) ? &tda18212_1 : &tda18212_0; -+ fe = dvb_attach(tda18212_attach, dvb->fe, i2c, cfg); -+ if (!fe) { -+ pr_err("No TDA18212 found!\n"); -+ return -ENODEV; ++ if (input->nr & 1) ++ board_info.addr = 0x63; ++ else ++ board_info.addr = 0x60; ++ ++ request_module(board_info.type); ++ ++ client = i2c_new_device(adapter, &board_info); ++ if (client == NULL || client->dev.driver == NULL) ++ goto err; ++ ++ if (!try_module_get(client->dev.driver->owner)) { ++ i2c_unregister_device(client); ++ goto err; + } ++ ++ dvb->i2c_client[0] = client; ++ + return 0; ++err: ++ dev_notice(input->port->dev->dev, "TDA18212 tuner not found. Device is not fully operational.\n"); ++ return -ENODEV; +} -+#endif + +/****************************************************************************/ +/****************************************************************************/ @@ -24144,7 +19548,7 @@ index 9e3492e..c2fc010 100644 static struct stv090x_config stv0900 = { .device = STV0900, -@@ -624,6 +1144,9 @@ static struct stv090x_config stv0900 = { +@@ -624,6 +1012,9 @@ static struct stv090x_config stv0900 = { .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, @@ -24154,7 +19558,7 @@ index 9e3492e..c2fc010 100644 .repeater_level = STV090x_RPTLEVEL_16, .adc1_range = STV090x_ADC_1Vpp, -@@ -643,6 +1166,9 @@ static struct stv090x_config stv0900_aa = { +@@ -643,6 +1034,9 @@ static struct stv090x_config stv0900_aa = { .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, @@ -24164,7 +19568,7 @@ index 9e3492e..c2fc010 100644 .repeater_level = STV090x_RPTLEVEL_16, .adc1_range = STV090x_ADC_1Vpp, -@@ -667,18 +1193,19 @@ static int demod_attach_stv0900(struct ddb_input *input, int type) +@@ -667,18 +1061,19 @@ static int demod_attach_stv0900(struct ddb_input *input, int type) { struct i2c_adapter *i2c = &input->port->i2c->adap; struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; @@ -24191,7 +19595,7 @@ index 9e3492e..c2fc010 100644 return -ENODEV; } return 0; -@@ -687,18 +1214,19 @@ static int demod_attach_stv0900(struct ddb_input *input, int type) +@@ -687,18 +1082,19 @@ static int demod_attach_stv0900(struct ddb_input *input, int type) static int tuner_attach_stv6110(struct ddb_input *input, int type) { struct i2c_adapter *i2c = &input->port->i2c->adap; @@ -24199,7 +19603,7 @@ index 9e3492e..c2fc010 100644 struct stv090x_config *feconf = type ? &stv0900_aa : &stv0900; struct stv6110x_config *tunerconf = (input->nr & 1) ? &stv6110b : &stv6110a; - struct stv6110x_devctl *ctl; + const struct stv6110x_devctl *ctl; - ctl = dvb_attach(stv6110x_attach, input->fe, tunerconf, i2c); + ctl = dvb_attach(stv6110x_attach, dvb->fe, tunerconf, i2c); @@ -24215,134 +19619,489 @@ index 9e3492e..c2fc010 100644 feconf->tuner_init = ctl->tuner_init; feconf->tuner_sleep = ctl->tuner_sleep; -@@ -715,329 +1243,919 @@ static int tuner_attach_stv6110(struct ddb_input *input, int type) +@@ -715,10 +1111,431 @@ static int tuner_attach_stv6110(struct ddb_input *input, int type) return 0; } --static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, -- int (*start_feed)(struct dvb_demux_feed *), -- int (*stop_feed)(struct dvb_demux_feed *), -- void *priv) -+static struct stv0910_cfg stv0910 = { ++static struct stv0910_cfg stv0910_p = { + .adr = 0x68, + .parallel = 1, + .rptlvl = 4, + .clk = 30000000, +}; + ++static struct lnbh25_config lnbh25_conf_0_0 = { ++ .i2c_address = 0x0c << 1, ++ .data2_config = LNBH25_TEN | LNBH25_EXTM ++}; ++ ++static struct lnbh25_config lnbh25_conf_0_1 = { ++ .i2c_address = 0x0d << 1, ++ .data2_config = LNBH25_TEN | LNBH25_EXTM ++}; ++ ++static struct lnbh25_config lnbh25_conf_1_0 = { ++ .i2c_address = 0x08 << 1, ++ .data2_config = LNBH25_TEN | LNBH25_EXTM ++}; ++ ++static struct lnbh25_config lnbh25_conf_1_1 = { ++ .i2c_address = 0x09 << 1, ++ .data2_config = LNBH25_TEN | LNBH25_EXTM ++}; ++ ++ +static int demod_attach_stv0910(struct ddb_input *input, int type) - { -- dvbdemux->priv = priv; ++{ + struct i2c_adapter *i2c = &input->port->i2c->adap; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; - -- dvbdemux->filternum = 256; -- dvbdemux->feednum = 256; -- dvbdemux->start_feed = start_feed; -- dvbdemux->stop_feed = stop_feed; -- dvbdemux->write_to_decoder = NULL; -- dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | -- DMX_SECTION_FILTERING | -- DMX_MEMORY_BASED_FILTERING); -- return dvb_dmx_init(dvbdemux); -+ dvb->fe = dvb_attach(stv0910_attach, i2c, &stv0910, (input->nr & 1)); ++ struct stv0910_cfg cfg = stv0910_p; ++ ++ if (type) ++ cfg.parallel = 2; ++ dvb->fe = dvb_attach(stv0910_attach, i2c, &cfg, (input->nr & 1)); ++ if (!dvb->fe) { ++ cfg.adr = 0x6c; ++ dvb->fe = dvb_attach(stv0910_attach, i2c, ++ &cfg, (input->nr & 1)); ++ } + if (!dvb->fe) { + pr_err("No STV0910 found!\n"); + return -ENODEV; + } -+ if (!dvb_attach(lnbh25_attach, dvb->fe, i2c, -+ (input->nr & 1) ? 0x09 : 0x08)) { -+ pr_err("No LNBH25 found!\n"); -+ return -ENODEV; ++ ++ if (!dvb_attach(lnbh25_attach, dvb->fe, ++ ((input->nr & 1) ? &lnbh25_conf_0_1 : &lnbh25_conf_0_0), ++ i2c)) { ++ if (!dvb_attach(lnbh25_attach, dvb->fe, ++ ((input->nr & 1) ? &lnbh25_conf_1_1 : &lnbh25_conf_1_0), ++ i2c)) { ++ pr_err("No LNBH25 found!\n"); ++ return -ENODEV; ++ } + } ++ + return 0; - } - --static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, -- struct dvb_demux *dvbdemux, -- struct dmx_frontend *hw_frontend, -- struct dmx_frontend *mem_frontend, -- struct dvb_adapter *dvb_adapter) -+static int tuner_attach_stv6111(struct ddb_input *input) - { -- int ret; -- -- dmxdev->filternum = 256; -- dmxdev->demux = &dvbdemux->dmx; -- dmxdev->capabilities = 0; -- ret = dvb_dmxdev_init(dmxdev, dvb_adapter); -- if (ret < 0) -- return ret; ++} ++ ++static int tuner_attach_stv6111(struct ddb_input *input, int type) ++{ + struct i2c_adapter *i2c = &input->port->i2c->adap; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + struct dvb_frontend *fe; - -- hw_frontend->source = DMX_FRONTEND_0; -- dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend); -- mem_frontend->source = DMX_MEMORY_FE; -- dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend); -- return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend); -+ fe = dvb_attach(stv6111_attach, dvb->fe, i2c, -+ (input->nr & 1) ? 0x63 : 0x60); ++ u8 adr = (type ? 0 : 4) + ((input->nr & 1) ? 0x63 : 0x60); ++ ++ fe = dvb_attach(stv6111_attach, dvb->fe, i2c, adr); + if (!fe) { -+ pr_err("No STV6111 found!\n"); -+ return -ENODEV; ++ fe = dvb_attach(stv6111_attach, dvb->fe, i2c, adr & ~4); ++ if (!fe) { ++ pr_err("No STV6111 found at 0x%02x!\n", adr); ++ return -ENODEV; ++ } + } + return 0; - } - --static int start_feed(struct dvb_demux_feed *dvbdmxfeed) -+static int lnb_command(struct ddb *dev, u32 lnb, u32 cmd) - { -- struct dvb_demux *dvbdmx = dvbdmxfeed->demux; -- struct ddb_input *input = dvbdmx->priv; -+ u32 c, v = 0; - -- if (!input->users) -- ddb_input_start(input); -- -- return ++input->users; -+ v = LNB_TONE & (dev->lnb_tone << (15 - lnb)); -+ pr_info("lnb_control[%u] = %08x\n", lnb, cmd | v); -+ ddbwritel(dev, cmd | v, LNB_CONTROL(lnb)); ++} ++ ++static int lnb_command(struct ddb *dev, u32 link, u32 lnb, u32 cmd) ++{ ++ u32 c, v = 0, tag = DDB_LINK_TAG(link); ++ ++ v = LNB_TONE & (dev->link[link].lnb.tone << (15 - lnb)); ++ ddbwritel(dev, cmd | v, tag | LNB_CONTROL(lnb)); + for (c = 0; c < 10; c++) { -+ v = ddbreadl(dev, LNB_CONTROL(lnb)); -+ pr_info("ctrl = %08x\n", v); ++ v = ddbreadl(dev, tag | LNB_CONTROL(lnb)); + if ((v & LNB_BUSY) == 0) + break; + msleep(20); + } ++ if (c == 10) ++ pr_info("lnb_command lnb = %08x cmd = %08x\n", lnb, cmd); + return 0; - } - --static int stop_feed(struct dvb_demux_feed *dvbdmxfeed) -+static int dd_send_master_cmd(struct dvb_frontend *fe, -+ struct dvb_diseqc_master_cmd *cmd) - { -- struct dvb_demux *dvbdmx = dvbdmxfeed->demux; -- struct ddb_input *input = dvbdmx->priv; -- -- if (--input->users) -- return input->users; ++} ++ ++static int max_send_master_cmd(struct dvb_frontend *fe, ++ struct dvb_diseqc_master_cmd *cmd) ++{ + struct ddb_input *input = fe->sec_priv; + struct ddb_port *port = input->port; + struct ddb *dev = port->dev; + struct ddb_dvb *dvb = &port->dvb[input->nr & 1]; ++ u32 tag = DDB_LINK_TAG(port->lnr); + int i; ++ u32 fmode = dev->link[port->lnr].lnb.fmode; ++ ++ if (fmode == 2 || fmode == 1) ++ return 0; ++ if (dvb->diseqc_send_master_cmd) ++ dvb->diseqc_send_master_cmd(fe, cmd); ++ ++ mutex_lock(&dev->link[port->lnr].lnb.lock); ++ ddbwritel(dev, 0, tag | LNB_BUF_LEVEL(dvb->input)); ++ for (i = 0; i < cmd->msg_len; i++) ++ ddbwritel(dev, cmd->msg[i], tag | LNB_BUF_WRITE(dvb->input)); ++ lnb_command(dev, port->lnr, dvb->input, LNB_CMD_DISEQC); ++ mutex_unlock(&dev->link[port->lnr].lnb.lock); ++ return 0; ++} ++ ++static int lnb_set_tone(struct ddb *dev, u32 link, u32 input, ++ enum fe_sec_tone_mode tone) ++{ ++ int s = 0; ++ u32 mask = (1ULL << input); ++ ++ switch (tone) { ++ case SEC_TONE_OFF: ++ if (!(dev->link[link].lnb.tone & mask)) ++ return 0; ++ dev->link[link].lnb.tone &= ~(1ULL << input); ++ break; ++ case SEC_TONE_ON: ++ if (dev->link[link].lnb.tone & mask) ++ return 0; ++ dev->link[link].lnb.tone |= (1ULL << input); ++ break; ++ default: ++ s = -EINVAL; ++ break; ++ }; ++ if (!s) ++ s = lnb_command(dev, link, input, LNB_CMD_NOP); ++ return s; ++} ++ ++static int lnb_set_voltage(struct ddb *dev, u32 link, u32 input, ++ enum fe_sec_voltage voltage) ++{ ++ int s = 0; ++ ++ if (dev->link[link].lnb.oldvoltage[input] == voltage) ++ return 0; ++ switch (voltage) { ++ case SEC_VOLTAGE_OFF: ++ if (dev->link[link].lnb.voltage[input]) ++ return 0; ++ lnb_command(dev, link, input, LNB_CMD_OFF); ++ break; ++ case SEC_VOLTAGE_13: ++ lnb_command(dev, link, input, LNB_CMD_LOW); ++ break; ++ case SEC_VOLTAGE_18: ++ lnb_command(dev, link, input, LNB_CMD_HIGH); ++ break; ++ default: ++ s = -EINVAL; ++ break; ++ }; ++ dev->link[link].lnb.oldvoltage[input] = voltage; ++ return s; ++} ++ ++static int max_set_input_unlocked(struct dvb_frontend *fe, int in) ++{ ++ struct ddb_input *input = fe->sec_priv; ++ struct ddb_port *port = input->port; ++ struct ddb *dev = port->dev; ++ struct ddb_dvb *dvb = &port->dvb[input->nr & 1]; ++ int res = 0; ++ ++ if (in > 3) ++ return -EINVAL; ++ if (dvb->input != in) { ++ u32 bit = (1ULL << input->nr); ++ u32 obit = dev->link[port->lnr].lnb.voltage[dvb->input] & bit; ++ ++ dev->link[port->lnr].lnb.voltage[dvb->input] &= ~bit; ++ dvb->input = in; ++ dev->link[port->lnr].lnb.voltage[dvb->input] |= obit; ++ } ++ res = dvb->set_input(fe, in); ++ return res; ++} ++ ++static int max_set_input(struct dvb_frontend *fe, int in) ++{ ++ struct ddb_input *input = fe->sec_priv; ++ struct ddb_port *port = input->port; ++ struct ddb *dev = input->port->dev; ++ int res; ++ ++ mutex_lock(&dev->link[port->lnr].lnb.lock); ++ res = max_set_input_unlocked(fe, in); ++ mutex_unlock(&dev->link[port->lnr].lnb.lock); ++ return res; ++} ++ ++static int max_set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone) ++{ ++ struct ddb_input *input = fe->sec_priv; ++ struct ddb_port *port = input->port; ++ struct ddb *dev = port->dev; ++ struct ddb_dvb *dvb = &port->dvb[input->nr & 1]; ++ int tuner = 0; ++ int res = 0; ++ u32 fmode = dev->link[port->lnr].lnb.fmode; ++ ++ mutex_lock(&dev->link[port->lnr].lnb.lock); ++ dvb->tone = tone; ++ switch (fmode) { ++ default: ++ case 0: ++ case 3: ++ res = lnb_set_tone(dev, port->lnr, dvb->input, tone); ++ break; ++ case 1: ++ case 2: ++ if (old_quattro) { ++ if (dvb->tone == SEC_TONE_ON) ++ tuner |= 2; ++ if (dvb->voltage == SEC_VOLTAGE_18) ++ tuner |= 1; ++ } else { ++ if (dvb->tone == SEC_TONE_ON) ++ tuner |= 1; ++ if (dvb->voltage == SEC_VOLTAGE_18) ++ tuner |= 2; ++ } ++ res = max_set_input_unlocked(fe, tuner); ++ break; ++ } ++ mutex_unlock(&dev->link[port->lnr].lnb.lock); ++ return res; ++} ++ ++static int max_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage voltage) ++{ ++ struct ddb_input *input = fe->sec_priv; ++ struct ddb_port *port = input->port; ++ struct ddb *dev = port->dev; ++ struct ddb_dvb *dvb = &port->dvb[input->nr & 1]; ++ int tuner = 0; ++ u32 nv, ov = dev->link[port->lnr].lnb.voltages; ++ int res = 0; ++ u32 fmode = dev->link[port->lnr].lnb.fmode; ++ ++ mutex_lock(&dev->link[port->lnr].lnb.lock); ++ dvb->voltage = voltage; ++ ++ switch (fmode) { ++ case 3: ++ default: ++ case 0: ++ if (fmode == 3) ++ max_set_input_unlocked(fe, 0); ++ if (voltage == SEC_VOLTAGE_OFF) ++ dev->link[port->lnr].lnb.voltage[dvb->input] &= ~(1ULL << input->nr); ++ else ++ dev->link[port->lnr].lnb.voltage[dvb->input] |= (1ULL << input->nr); ++ ++ res = lnb_set_voltage(dev, port->lnr, dvb->input, voltage); ++ break; ++ case 1: ++ case 2: ++ if (voltage == SEC_VOLTAGE_OFF) ++ dev->link[port->lnr].lnb.voltages &= ~(1ULL << input->nr); ++ else ++ dev->link[port->lnr].lnb.voltages |= (1ULL << input->nr); ++ nv = dev->link[port->lnr].lnb.voltages; ++ ++ if (old_quattro) { ++ if (dvb->tone == SEC_TONE_ON) ++ tuner |= 2; ++ if (dvb->voltage == SEC_VOLTAGE_18) ++ tuner |= 1; ++ } else { ++ if (dvb->tone == SEC_TONE_ON) ++ tuner |= 1; ++ if (dvb->voltage == SEC_VOLTAGE_18) ++ tuner |= 2; ++ } ++ res = max_set_input_unlocked(fe, tuner); ++ ++ if (nv != ov) { ++ if (nv) { ++ lnb_set_voltage(dev, port->lnr, 0, SEC_VOLTAGE_13); ++ if (fmode == 1) { ++ lnb_set_voltage(dev, port->lnr, 0, SEC_VOLTAGE_13); ++ if (old_quattro) { ++ lnb_set_voltage(dev, port->lnr, 1, SEC_VOLTAGE_18); ++ lnb_set_voltage(dev, port->lnr, 2, SEC_VOLTAGE_13); ++ } else { ++ lnb_set_voltage(dev, port->lnr, 1, SEC_VOLTAGE_13); ++ lnb_set_voltage(dev, port->lnr, 2, SEC_VOLTAGE_18); ++ } ++ lnb_set_voltage(dev, port->lnr, 3, SEC_VOLTAGE_18); ++ } ++ } else { ++ lnb_set_voltage(dev, port->lnr, 0, SEC_VOLTAGE_OFF); ++ if (fmode == 1) { ++ lnb_set_voltage(dev, port->lnr, 1, SEC_VOLTAGE_OFF); ++ lnb_set_voltage(dev, port->lnr, 2, SEC_VOLTAGE_OFF); ++ lnb_set_voltage(dev, port->lnr, 3, SEC_VOLTAGE_OFF); ++ } ++ } ++ } ++ break; ++ } ++ mutex_unlock(&dev->link[port->lnr].lnb.lock); ++ return res; ++} ++ ++static int max_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg) ++{ ++ ++ return 0; ++} ++ ++static int max_send_burst(struct dvb_frontend *fe, enum fe_sec_mini_cmd burst) ++{ ++ return 0; ++} ++ ++static int mxl_fw_read(void *priv, u8 *buf, u32 len) ++{ ++ struct ddb_link *link = priv; ++ struct ddb *dev = link->dev; ++ ++ pr_info("Read mxl_fw from link %u\n", link->nr); ++ ++ return ddbridge_flashread(dev, link->nr, buf, 0xc0000, len); ++} ++ ++static int lnb_init_fmode(struct ddb *dev, struct ddb_link *link, u32 fm) ++{ ++ u32 l = link->nr; ++ ++ if (link->lnb.fmode == fm) ++ return 0; ++ pr_info("Set fmode link %u = %u\n", l, fm); ++ mutex_lock(&link->lnb.lock); ++ if (fm == 2 || fm == 1) { ++ lnb_set_tone(dev, l, 0, SEC_TONE_OFF); ++ if (old_quattro) { ++ lnb_set_tone(dev, l, 1, SEC_TONE_OFF); ++ lnb_set_tone(dev, l, 2, SEC_TONE_ON); ++ } else { ++ lnb_set_tone(dev, l, 1, SEC_TONE_ON); ++ lnb_set_tone(dev, l, 2, SEC_TONE_OFF); ++ } ++ lnb_set_tone(dev, l, 3, SEC_TONE_ON); ++ } ++ link->lnb.fmode = fm; ++ mutex_unlock(&link->lnb.lock); ++ return 0; ++} ++ ++static struct mxl5xx_cfg mxl5xx = { ++ .adr = 0x60, ++ .type = 0x01, ++ .clk = 27000000, ++ .ts_clk = 139, ++ .cap = 12, ++ .fw_read = mxl_fw_read, ++}; ++ ++static int fe_attach_mxl5xx(struct ddb_input *input) ++{ ++ struct ddb *dev = input->port->dev; ++ struct i2c_adapter *i2c = &input->port->i2c->adap; ++ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; ++ struct ddb_port *port = input->port; ++ struct ddb_link *link = &dev->link[port->lnr]; ++ struct mxl5xx_cfg cfg; ++ int demod, tuner; ++ ++ cfg = mxl5xx; ++ cfg.fw_priv = link; ++ if (dev->link[0].info->type == DDB_OCTONET) ++ ; /* cfg.ts_clk = 69; */ ++ ++ demod = input->nr; ++ tuner = demod & 3; ++ if (fmode == 3) ++ tuner = 0; ++ dvb->fe = dvb_attach(mxl5xx_attach, i2c, &cfg, demod, tuner); ++ if (!dvb->fe) { ++ pr_err("No MXL5XX found!\n"); ++ return -ENODEV; ++ } ++ if (input->nr < 4) { ++ lnb_command(dev, port->lnr, input->nr, LNB_CMD_INIT); ++ lnb_set_voltage(dev, port->lnr, input->nr, SEC_VOLTAGE_OFF); ++ } ++ lnb_init_fmode(dev, link, fmode); ++ ++ dvb->fe->ops.set_voltage = max_set_voltage; ++ dvb->fe->ops.enable_high_lnb_voltage = max_enable_high_lnb_voltage; ++ dvb->fe->ops.set_tone = max_set_tone; ++ dvb->diseqc_send_master_cmd = dvb->fe->ops.diseqc_send_master_cmd; ++ dvb->fe->ops.diseqc_send_master_cmd = max_send_master_cmd; ++ dvb->fe->ops.diseqc_send_burst = max_send_burst; ++ dvb->fe->sec_priv = input; ++ dvb->set_input = dvb->fe->ops.set_input; ++ dvb->fe->ops.set_input = max_set_input; ++ dvb->input = tuner; ++ return 0; ++} ++ + static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, +- int (*start_feed)(struct dvb_demux_feed *), +- int (*stop_feed)(struct dvb_demux_feed *), +- void *priv) ++ int (*start_feed)(struct dvb_demux_feed *), ++ int (*stop_feed)(struct dvb_demux_feed *), ++ void *priv) + { + dvbdemux->priv = priv; + +@@ -734,10 +1551,10 @@ static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, + } + + static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, +- struct dvb_demux *dvbdemux, +- struct dmx_frontend *hw_frontend, +- struct dmx_frontend *mem_frontend, +- struct dvb_adapter *dvb_adapter) ++ struct dvb_demux *dvbdemux, ++ struct dmx_frontend *hw_frontend, ++ struct dmx_frontend *mem_frontend, ++ struct dvb_adapter *dvb_adapter) + { + int ret; + +@@ -759,1000 +1576,3010 @@ static int start_feed(struct dvb_demux_feed *dvbdmxfeed) + { + struct dvb_demux *dvbdmx = dvbdmxfeed->demux; + struct ddb_input *input = dvbdmx->priv; ++ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + +- if (!input->users) +- ddb_input_start(input); ++ if (!dvb->users) ++ ddb_input_start_all(input); + +- return ++input->users; ++ return ++dvb->users; + } + + static int stop_feed(struct dvb_demux_feed *dvbdmxfeed) + { + struct dvb_demux *dvbdmx = dvbdmxfeed->demux; + struct ddb_input *input = dvbdmx->priv; ++ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; + +- if (--input->users) +- return input->users; ++ if (--dvb->users) ++ return dvb->users; - ddb_input_stop(input); -+ mutex_lock(&dev->lnb_lock); -+ ddbwritel(dev, 0, LNB_BUF_LEVEL(dvb->input)); -+ for (i = 0; i < cmd->msg_len; i++) -+ ddbwritel(dev, cmd->msg[i], LNB_BUF_WRITE(dvb->input)); -+ lnb_command(dev, dvb->input, LNB_CMD_DISEQC); -+ mutex_unlock(&dev->lnb_lock); ++ ddb_input_stop_all(input); return 0; } - --static void dvb_input_detach(struct ddb_input *input) -+static int dd_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) + static void dvb_input_detach(struct ddb_input *input) { - struct dvb_adapter *adap = &input->adap; - struct dvb_demux *dvbdemux = &input->demux; @@ -24355,199 +20114,31 @@ index 9e3492e..c2fc010 100644 - dvb_unregister_frontend(input->fe); - dvb_frontend_detach(input->fe); - input->fe = NULL; -- } ++ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; ++ struct dvb_demux *dvbdemux = &dvb->demux; ++ struct i2c_client *client; ++ ++ switch (dvb->attached) { ++ case 0x31: ++ client = dvb->i2c_client[0]; ++ if (client) { ++ module_put(client->dev.driver->owner); ++ i2c_unregister_device(client); + } - case 4: - dvb_net_release(&input->dvbnet); - - case 3: -- dvbdemux->dmx.close(&dvbdemux->dmx); -- dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, -- &input->hw_frontend); -- dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, -- &input->mem_frontend); -- dvb_dmxdev_release(&input->dmxdev); -+ struct ddb_input *input = fe->sec_priv; -+ struct ddb_port *port = input->port; -+ struct ddb *dev = port->dev; -+ struct ddb_dvb *dvb = &port->dvb[input->nr & 1]; -+ int s = 0; - -- case 2: -- dvb_dmx_release(&input->demux); -+ mutex_lock(&dev->lnb_lock); -+ switch (tone) { -+ case SEC_TONE_OFF: -+ dev->lnb_tone &= ~(1ULL << dvb->input); -+ break; -+ case SEC_TONE_ON: -+ dev->lnb_tone |= (1ULL << dvb->input); -+ break; -+ default: -+ s = -EINVAL; -+ break; -+ }; -+ if (!s) -+ s = lnb_command(dev, dvb->input, LNB_CMD_NOP); -+ mutex_unlock(&dev->lnb_lock); -+ return 0; -+} - -- case 1: -- dvb_unregister_adapter(adap); -- } -- input->attached = 0; -+static int dd_enable_high_lnb_voltage(struct dvb_frontend *fe, long arg) -+{ -+ -+ return 0; - } - --static int dvb_input_attach(struct ddb_input *input) -+static int dd_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) - { -- int ret; -+ struct ddb_input *input = fe->sec_priv; - struct ddb_port *port = input->port; -- struct dvb_adapter *adap = &input->adap; -- struct dvb_demux *dvbdemux = &input->demux; -- -- ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE, -- &input->port->dev->pdev->dev, -- adapter_nr); -- if (ret < 0) { -- printk(KERN_ERR "ddbridge: Could not register adapter." -- "Check if you enabled enough adapters in dvb-core!\n"); -+ struct ddb *dev = port->dev; -+ struct ddb_dvb *dvb = &port->dvb[input->nr & 1]; -+ int s = 0; -+ -+ mutex_lock(&dev->lnb_lock); -+ switch (voltage) { -+ case SEC_VOLTAGE_OFF: -+ lnb_command(dev, dvb->input, LNB_CMD_OFF); -+ break; -+ case SEC_VOLTAGE_13: -+ lnb_command(dev, dvb->input, LNB_CMD_LOW); -+ break; -+ case SEC_VOLTAGE_18: -+ lnb_command(dev, dvb->input, LNB_CMD_HIGH); -+ break; -+ default: -+ s = -EINVAL; -+ break; -+ }; -+ mutex_unlock(&dev->lnb_lock); -+ return s; -+} -+ -+static int dd_set_input(struct dvb_frontend *fe) -+{ -+ -+ return 0; -+} -+ -+static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, -+ int (*start_feed)(struct dvb_demux_feed *), -+ int (*stop_feed)(struct dvb_demux_feed *), -+ void *priv) -+{ -+ dvbdemux->priv = priv; -+ -+ dvbdemux->filternum = 256; -+ dvbdemux->feednum = 256; -+ dvbdemux->start_feed = start_feed; -+ dvbdemux->stop_feed = stop_feed; -+ dvbdemux->write_to_decoder = NULL; -+ dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | -+ DMX_SECTION_FILTERING | -+ DMX_MEMORY_BASED_FILTERING); -+ return dvb_dmx_init(dvbdemux); -+} -+ -+static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, -+ struct dvb_demux *dvbdemux, -+ struct dmx_frontend *hw_frontend, -+ struct dmx_frontend *mem_frontend, -+ struct dvb_adapter *dvb_adapter) -+{ -+ int ret; -+ -+ dmxdev->filternum = 256; -+ dmxdev->demux = &dvbdemux->dmx; -+ dmxdev->capabilities = 0; -+ ret = dvb_dmxdev_init(dmxdev, dvb_adapter); -+ if (ret < 0) - return ret; -+ -+ hw_frontend->source = DMX_FRONTEND_0; -+ dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend); -+ mem_frontend->source = DMX_MEMORY_FE; -+ dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend); -+ return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend); -+} -+ -+#if 0 -+static int start_input(struct ddb_input *input) -+{ -+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; -+ -+ if (!dvb->users) -+ ddb_input_start_all(input); -+ -+ return ++dvb->users; -+} -+ -+static int stop_input(struct ddb_input *input) -+{ -+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; -+ -+ if (--dvb->users) -+ return dvb->users; -+ -+ ddb_input_stop_all(input); -+ return 0; -+} -+#endif -+ -+static int start_feed(struct dvb_demux_feed *dvbdmxfeed) -+{ -+ struct dvb_demux *dvbdmx = dvbdmxfeed->demux; -+ struct ddb_input *input = dvbdmx->priv; -+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; -+ -+ if (!dvb->users) -+ ddb_input_start_all(input); -+ -+ return ++dvb->users; -+} -+ -+static int stop_feed(struct dvb_demux_feed *dvbdmxfeed) -+{ -+ struct dvb_demux *dvbdmx = dvbdmxfeed->demux; -+ struct ddb_input *input = dvbdmx->priv; -+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; -+ -+ if (--dvb->users) -+ return dvb->users; -+ -+ ddb_input_stop_all(input); -+ return 0; -+} -+ -+static void dvb_input_detach(struct ddb_input *input) -+{ -+ struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; -+ struct dvb_demux *dvbdemux = &dvb->demux; -+ -+ switch (dvb->attached) { -+ case 0x31: + if (dvb->fe2) + dvb_unregister_frontend(dvb->fe2); + if (dvb->fe) + dvb_unregister_frontend(dvb->fe); + /* fallthrough */ + case 0x30: -+ dvb_frontend_detach(dvb->fe); ++ if (dvb->fe2) ++ dvb_frontend_detach(dvb->fe2); ++ if (dvb->fe) ++ dvb_frontend_detach(dvb->fe); + dvb->fe = dvb->fe2 = NULL; + /* fallthrough */ + case 0x21: @@ -24558,10 +20149,13 @@ index 9e3492e..c2fc010 100644 + dvb_net_release(&dvb->dvbnet); + /* fallthrough */ + case 0x11: -+ dvbdemux->dmx.close(&dvbdemux->dmx); -+ dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, + dvbdemux->dmx.close(&dvbdemux->dmx); + dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, +- &input->hw_frontend); + &dvb->hw_frontend); -+ dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, + dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, +- &input->mem_frontend); +- dvb_dmxdev_release(&input->dmxdev); + &dvb->mem_frontend); + dvb_dmxdev_release(&dvb->dmxdev); + /* fallthrough */ @@ -24573,14 +20167,17 @@ index 9e3492e..c2fc010 100644 + } + dvb->attached = 0x00; +} -+ + +- case 2: +- dvb_dmx_release(&input->demux); +static int dvb_register_adapters(struct ddb *dev) +{ + int i, ret = 0; + struct ddb_port *port; + struct dvb_adapter *adap; + -+ if (adapter_alloc == 3 || dev->info->type == DDB_MOD) { ++ if (adapter_alloc == 3 || dev->link[0].info->type == DDB_MOD || ++ dev->link[0].info->type == DDB_OCTONET) { + port = &dev->port[0]; + adap = port->dvb[0].adap; + ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE, @@ -24589,15 +20186,17 @@ index 9e3492e..c2fc010 100644 + if (ret < 0) + return ret; + port->dvb[0].adap_registered = 1; -+ for (i = 0; i < dev->info->port_num; i++) { ++ for (i = 0; i < dev->port_num; i++) { + port = &dev->port[i]; + port->dvb[0].adap = adap; + port->dvb[1].adap = adap; + } + return 0; + } -+ -+ for (i = 0; i < dev->info->port_num; i++) { + +- case 1: +- dvb_unregister_adapter(adap); ++ for (i = 0; i < dev->port_num; i++) { + port = &dev->port[i]; + switch (port->class) { + case DDB_PORT_TUNER: @@ -24658,7 +20257,7 @@ index 9e3492e..c2fc010 100644 + struct ddb_port *port; + struct ddb_dvb *dvb; + -+ for (i = 0; i < dev->info->port_num; i++) { ++ for (i = 0; i < dev->link[0].info->port_num; i++) { + port = &dev->port[i]; + + dvb = &port->dvb[0]; @@ -24671,16 +20270,30 @@ index 9e3492e..c2fc010 100644 + dvb_unregister_adapter(dvb->adap); + dvb->adap_registered = 0; } -- input->attached = 1; -+} -+ -+static int dvb_input_attach(struct ddb_input *input) -+{ +- input->attached = 0; + } + + static int dvb_input_attach(struct ddb_input *input) + { +- int ret; + int ret = 0; + struct ddb_dvb *dvb = &input->port->dvb[input->nr & 1]; -+ struct ddb_port *port = input->port; + struct ddb_port *port = input->port; +- struct dvb_adapter *adap = &input->adap; +- struct dvb_demux *dvbdemux = &input->demux; +- +- ret = dvb_register_adapter(adap, "DDBridge", THIS_MODULE, +- &input->port->dev->pdev->dev, +- adapter_nr); +- if (ret < 0) { +- printk(KERN_ERR "ddbridge: Could not register adapter." +- "Check if you enabled enough adapters in dvb-core!\n"); +- return ret; +- } +- input->attached = 1; + struct dvb_adapter *adap = dvb->adap; + struct dvb_demux *dvbdemux = &dvb->demux; ++ int par = 0; + + dvb->attached = 0x01; @@ -24718,8 +20331,12 @@ index 9e3492e..c2fc010 100644 + return ret; + dvb->attached = 0x21; + } -+ dvb->fe = dvb->fe2 = 0; ++ dvb->fe = dvb->fe2 = NULL; switch (port->type) { ++ case DDB_TUNER_MXL5XX: ++ if (fe_attach_mxl5xx(input) < 0) ++ return -ENODEV; ++ break; case DDB_TUNER_DVBS_ST: if (demod_attach_stv0900(input, 0) < 0) return -ENODEV; @@ -24729,13 +20346,6 @@ index 9e3492e..c2fc010 100644 - if (dvb_register_frontend(adap, input->fe) < 0) - return -ENODEV; - } -+ break; -+ case DDB_TUNER_DVBS_STV0910: -+ case DDB_TUNER_DVBS_STV0910_P: -+ if (demod_attach_stv0910(input, 0) < 0) -+ return -ENODEV; -+ if (tuner_attach_stv6111(input) < 0) -+ return -ENODEV; break; case DDB_TUNER_DVBS_ST_AA: if (demod_attach_stv0900(input, 1) < 0) @@ -24747,35 +20357,77 @@ index 9e3492e..c2fc010 100644 - return -ENODEV; - } break; -+#if IS_ENABLED(CONFIG_DVB_DRXK) - case DDB_TUNER_DVBCT_TR: - if (demod_attach_drxk(input) < 0) +- case DDB_TUNER_DVBCT_TR: +- if (demod_attach_drxk(input) < 0) ++ case DDB_TUNER_DVBS_STV0910: ++ if (demod_attach_stv0910(input, 0) < 0) ++ return -ENODEV; ++ if (tuner_attach_stv6111(input, 0) < 0) ++ return -ENODEV; ++ break; ++ case DDB_TUNER_DVBS_STV0910_PR: ++ if (demod_attach_stv0910(input, 1) < 0) ++ return -ENODEV; ++ if (tuner_attach_stv6111(input, 1) < 0) ++ return -ENODEV; ++ break; ++ case DDB_TUNER_DVBS_STV0910_P: ++ if (demod_attach_stv0910(input, 0) < 0) ++ return -ENODEV; ++ if (tuner_attach_stv6111(input, 1) < 0) ++ return -ENODEV; ++ break; ++ case DDB_TUNER_DVBCT_TR: ++ if (demod_attach_drxk(input) < 0) return -ENODEV; if (tuner_attach_tda18271(input) < 0) return -ENODEV; - if (dvb_register_frontend(adap, input->fe) < 0) + break; -+#endif + case DDB_TUNER_DVBCT_ST: + if (demod_attach_stv0367dd(input) < 0) + return -ENODEV; -+ if (tuner_attach_tda18212dd(input) < 0) -+ return -ENODEV; -+ break; -+ case DDB_TUNER_DVBCT2_SONY: -+ case DDB_TUNER_DVBC2T2_SONY: -+ case DDB_TUNER_ISDBT_SONY: -+ if (demod_attach_cxd2843(input, 0) < 0) -+ return -ENODEV; -+ if (tuner_attach_tda18212dd(input) < 0) ++ if (tuner_attach_tda18212(input) < 0) ++ { ++ if(dvb->fe2) ++ dvb_frontend_detach(dvb->fe2); ++ if(dvb->fe) ++ dvb_frontend_detach(dvb->fe); + return -ENODEV; ++ } + break; + case DDB_TUNER_DVBCT2_SONY_P: + case DDB_TUNER_DVBC2T2_SONY_P: + case DDB_TUNER_ISDBT_SONY_P: -+ if (demod_attach_cxd2843(input, 1) < 0) ++ if (input->port->dev->link[input->port->lnr].info->ts_quirks ++ & TS_QUIRK_SERIAL) ++ par = 0; ++ else ++ par = 1; ++ case DDB_TUNER_DVBCT2_SONY: ++ case DDB_TUNER_DVBC2T2_SONY: ++ case DDB_TUNER_ISDBT_SONY: ++ if (demod_attach_cxd2843(input, par) < 0) + return -ENODEV; -+ if (tuner_attach_tda18212dd(input) < 0) ++ if (tuner_attach_tda18212(input) < 0) ++ { ++ if(dvb->fe2) ++ dvb_frontend_detach(dvb->fe2); ++ if(dvb->fe) ++ dvb_frontend_detach(dvb->fe); ++ return -ENODEV; ++ } ++ break; ++ default: ++ return 0; ++ } ++ dvb->attached = 0x30; ++ if (dvb->fe) { ++ if (dvb_register_frontend(adap, dvb->fe) < 0) ++ return -ENODEV; ++ } ++ if (dvb->fe2) { ++ if (dvb_register_frontend(adap, dvb->fe2) < 0) return -ENODEV; - if (input->fe2) { - if (dvb_register_frontend(adap, input->fe2) < 0) @@ -24784,71 +20436,28 @@ index 9e3492e..c2fc010 100644 - memcpy(&input->fe2->ops.tuner_ops, - &input->fe->ops.tuner_ops, - sizeof(struct dvb_tuner_ops)); -- } - break; -+ default: -+ return 0; - } -- input->attached = 5; -+ dvb->attached = 0x30; -+ if (dvb->fe) { -+ if (dvb_register_frontend(adap, dvb->fe) < 0) -+ return -ENODEV; -+ } -+ if (dvb->fe2) { -+ if (dvb_register_frontend(adap, dvb->fe2) < 0) -+ return -ENODEV; + dvb->fe2->tuner_priv = dvb->fe->tuner_priv; + memcpy(&dvb->fe2->ops.tuner_ops, + &dvb->fe->ops.tuner_ops, + sizeof(struct dvb_tuner_ops)); + } + dvb->attached = 0x31; - return 0; - } - --/****************************************************************************/ --/****************************************************************************/ - --static ssize_t ts_write(struct file *file, const __user char *buf, -- size_t count, loff_t *ppos) ++ return 0; ++} ++ ++ +static int port_has_encti(struct ddb_port *port) - { -- struct dvb_device *dvbdev = file->private_data; -- struct ddb_output *output = dvbdev->priv; -- size_t left = count; -- int stat; ++{ + u8 val; + int ret = i2c_read_reg(&port->i2c->adap, 0x20, 0, &val); - -- while (left) { -- if (ddb_output_free(output) < 188) { -- if (file->f_flags & O_NONBLOCK) -- break; -- if (wait_event_interruptible( -- output->wq, ddb_output_free(output) >= 188) < 0) -- break; -- } -- stat = ddb_output_write(output, buf, left); -- if (stat < 0) -- break; -- buf += stat; -- left -= stat; -- } -- return (left == count) ? -EAGAIN : (count - left); ++ + if (!ret) + pr_info("[0x20]=0x%02x\n", val); + return ret ? 0 : 1; - } - --static ssize_t ts_read(struct file *file, __user char *buf, -- size_t count, loff_t *ppos) ++} ++ +static int port_has_cxd(struct ddb_port *port, u8 *type) - { -- struct dvb_device *dvbdev = file->private_data; -- struct ddb_output *output = dvbdev->priv; -- struct ddb_input *input = output->port->input[0]; -- int left, read; ++{ + u8 val; + u8 probe[4] = { 0xe0, 0x00, 0x00, 0x00 }, data[4]; + struct i2c_msg msgs[2] = {{ .addr = 0x40, .flags = 0, @@ -24858,60 +20467,37 @@ index 9e3492e..c2fc010 100644 + val = i2c_transfer(&port->i2c->adap, msgs, 2); + if (val != 2) + return 0; - -- count -= count % 188; -- left = count; -- while (left) { -- if (ddb_input_avail(input) < 188) { -- if (file->f_flags & O_NONBLOCK) -- break; -- if (wait_event_interruptible( -- input->wq, ddb_input_avail(input) >= 188) < 0) -- break; -- } -- read = ddb_input_read(input, buf, left); -- if (read < 0) -- return read; -- left -= read; -- buf += read; -- } -- return (left == count) ? -EAGAIN : (count - left); ++ + if (data[0] == 0x02 && data[1] == 0x2b && data[3] == 0x43) + *type = 2; + else + *type = 1; + return 1; - } - --static unsigned int ts_poll(struct file *file, poll_table *wait) -+static int port_has_xo2(struct ddb_port *port, u8 *id) - { -- /* -- struct dvb_device *dvbdev = file->private_data; -- struct ddb_output *output = dvbdev->priv; -- struct ddb_input *input = output->port->input[0]; -- */ -- unsigned int mask = 0; -+ u8 val; ++} ++ ++static int port_has_xo2(struct ddb_port *port, u8 *type, u8 *id) ++{ + u8 probe[1] = { 0x00 }, data[4]; -+ struct i2c_msg msgs[2] = {{ .addr = 0x10, .flags = 0, -+ .buf = probe, .len = 1 }, -+ { .addr = 0x10, .flags = I2C_M_RD, -+ .buf = data, .len = 4 } }; -+ val = i2c_transfer(&port->i2c->adap, msgs, 2); -+ if (val != 2) -+ return 0; + -+ if (data[0] != 'D' || data[1] != 'F') ++ if (i2c_io(&port->i2c->adap, 0x10, probe, 1, data, 4)) + return 0; -+ -+ *id = data[2]; -+ return 1; ++ if (data[0] == 'D' && data[1] == 'F') { ++ *id = data[2]; ++ *type = 1; ++ return 1; ++ } ++ if (data[0] == 'C' && data[1] == 'I') { ++ *id = data[2]; ++ *type = 2; ++ return 1; ++ } ++ return 0; +} + +static int port_has_stv0900(struct ddb_port *port) +{ + u8 val; ++ + if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0) + return 0; + return 1; @@ -24927,6 +20513,7 @@ index 9e3492e..c2fc010 100644 +static int port_has_drxks(struct ddb_port *port) +{ + u8 val; ++ + if (i2c_read(&port->i2c->adap, 0x29, &val) < 0) + return 0; + if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0) @@ -24948,52 +20535,11 @@ index 9e3492e..c2fc010 100644 + return 0; + return 1; +} - - #if 0 -- if (data_avail_to_read) -- mask |= POLLIN | POLLRDNORM; -- if (data_avail_to_write) -- mask |= POLLOUT | POLLWRNORM; -+static int init_xo2_old(struct ddb_port *port) -+{ -+ struct i2c_adapter *i2c = &port->i2c->adap; -+ u8 val; -+ int res; -+ -+ res = i2c_read_reg(i2c, 0x10, 0x04, &val); -+ if (res < 0) -+ return res; -+ -+ if (val != 0x02) { -+ pr_info("Port %d: invalid XO2\n", port->nr); -+ return -1; -+ } -+ i2c_write_reg(i2c, 0x10, 0xc0, 0x00); /* Disable XO2 I2C master */ -+ -+ i2c_read_reg(i2c, 0x10, 0x08, &val); -+ if (val != 0) { -+ i2c_write_reg(i2c, 0x10, 0x08, 0x00); -+ msleep(100); -+ } -+ /* Enable tuner power, disable pll, reset demods */ -+ i2c_write_reg(i2c, 0x10, 0x08, 0x04); -+ usleep_range(2000, 3000); -+ /* Release demod resets */ -+ i2c_write_reg(i2c, 0x10, 0x08, 0x07); -+ usleep_range(2000, 3000); -+ /* Start XO2 PLL */ -+ i2c_write_reg(i2c, 0x10, 0x08, 0x87); - -- poll_wait(file, &read_queue, wait); -- poll_wait(file, &write_queue, wait); -+ return 0; -+} - #endif -- return mask; + +static int init_xo2(struct ddb_port *port) +{ + struct i2c_adapter *i2c = &port->i2c->adap; ++ struct ddb *dev = port->dev; + u8 val, data[2]; + int res; + @@ -25016,20 +20562,71 @@ index 9e3492e..c2fc010 100644 + usleep_range(2000, 3000); + /* Release demod resets */ + i2c_write_reg(i2c, 0x10, 0x08, 0x07); ++ ++ /* speed: 0=55,1=75,2=90,3=104 MBit/s */ ++ i2c_write_reg(i2c, 0x10, 0x09, 2); ++ ++ if (dev->link[port->lnr].info->con_clock) { ++ pr_info("Setting continuous clock for XO2\n"); ++ i2c_write_reg(i2c, 0x10, 0x0a, 0x03); ++ i2c_write_reg(i2c, 0x10, 0x0b, 0x03); ++ } else { ++ i2c_write_reg(i2c, 0x10, 0x0a, 0x01); ++ i2c_write_reg(i2c, 0x10, 0x0b, 0x01); ++ } ++ + usleep_range(2000, 3000); + /* Start XO2 PLL */ + i2c_write_reg(i2c, 0x10, 0x08, 0x87); + + return 0; - } - --static const struct file_operations ci_fops = { -- .owner = THIS_MODULE, -- .read = ts_read, -- .write = ts_write, -- .open = dvb_generic_open, -- .release = dvb_generic_release, -- .poll = ts_poll, ++} ++ ++static int init_xo2_ci(struct ddb_port *port) ++{ ++ struct i2c_adapter *i2c = &port->i2c->adap; ++ struct ddb *dev = port->dev; ++ u8 val, data[2]; ++ int res; ++ ++ res = i2c_read_regs(i2c, 0x10, 0x04, data, 2); ++ if (res < 0) ++ return res; ++ ++ if (data[0] > 1) { ++ pr_info("Port %d: invalid XO2 CI %02x\n", ++ port->nr, data[0]); ++ return -1; ++ } ++ pr_info("Port %d: DuoFlex CI %u.%u\n", port->nr, data[0], data[1]); ++ ++ i2c_read_reg(i2c, 0x10, 0x08, &val); ++ if (val != 0) { ++ i2c_write_reg(i2c, 0x10, 0x08, 0x00); ++ msleep(100); ++ } ++ /* Enable both CI */ ++ i2c_write_reg(i2c, 0x10, 0x08, 3); ++ usleep_range(2000, 3000); ++ ++ ++ /* speed: 0=55,1=75,2=90,3=104 MBit/s */ ++ i2c_write_reg(i2c, 0x10, 0x09, 1); ++ ++ i2c_write_reg(i2c, 0x10, 0x08, 0x83); ++ usleep_range(2000, 3000); ++ ++ if (dev->link[port->lnr].info->con_clock) { ++ pr_info("Setting continuous clock for DuoFLex CI\n"); ++ i2c_write_reg(i2c, 0x10, 0x0a, 0x03); ++ i2c_write_reg(i2c, 0x10, 0x0b, 0x03); ++ } else { ++ i2c_write_reg(i2c, 0x10, 0x0a, 0x01); ++ i2c_write_reg(i2c, 0x10, 0x0b, 0x01); ++ } ++ return 0; ++} ++ +static int port_has_cxd28xx(struct ddb_port *port, u8 *id) +{ + struct i2c_adapter *i2c = &port->i2c->adap; @@ -25049,77 +20646,119 @@ index 9e3492e..c2fc010 100644 + "DUAL DVB-ISDBT", "DUAL DVB-C/C2/T/T2", + "DUAL ATSC", "DUAL DVB-C/C2/T/T2", + "", "" - }; - --static struct dvb_device dvbdev_ci = { -- .readers = -1, -- .writers = -1, -- .users = -1, -- .fops = &ci_fops, --}; ++}; ++ ++static char *xo2types[] = { ++ "DVBS_ST", "DVBCT2_SONY", ++ "ISDBT_SONY", "DVBC2T2_SONY", ++ "ATSC_ST", "DVBC2T2_ST" ++}; ++ +static void ddb_port_probe(struct ddb_port *port) +{ + struct ddb *dev = port->dev; -+ u8 id; ++ u32 l = port->lnr; ++ u8 id, type; + + port->name = "NO MODULE"; ++ port->type_name = "NONE"; + port->class = DDB_PORT_NONE; + -+ if (dev->info->type == DDB_MOD) { ++ /* Handle missing ports and ports without I2C */ ++ ++ if (port->nr == ts_loop) { ++ port->name = "TS LOOP"; ++ port->class = DDB_PORT_LOOP; ++ return; ++ } ++ ++ if (port->nr == 1 && dev->link[l].info->type == DDB_OCTOPUS_CI && ++ dev->link[l].info->i2c_mask == 1) { ++ port->name = "NO TAB"; ++ port->class = DDB_PORT_NONE; ++ return; ++ } ++ ++ if (dev->link[l].info->type == DDB_OCTOPUS_MAX) { ++ port->name = "DUAL DVB-S2 MAX"; ++ port->type_name = "MXL5XX"; ++ port->class = DDB_PORT_TUNER; ++ port->type = DDB_TUNER_MXL5XX; ++ if (port->i2c) ++ ddbwritel(dev, I2C_SPEED_400, ++ port->i2c->regs + I2C_TIMING); ++ return; ++ } ++ ++ if (dev->link[l].info->type == DDB_MOD) { + port->name = "MOD"; + port->class = DDB_PORT_MOD; + return; + } + -+ if (dev->info->type == DDB_OCTOPUS_MAX) { -+ port->name = "DUAL DVB-S2 MX"; -+ port->class = DDB_PORT_TUNER; -+ port->type = DDB_TUNER_MXL5XX; -+ if (port->i2c) -+ ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING); -+ return; -+ } -+ -+ if (port->nr > 1 && dev->info->type == DDB_OCTOPUS_CI) { ++ if (port->nr > 1 && dev->link[l].info->type == DDB_OCTOPUS_CI) { + port->name = "CI internal"; ++ port->type_name = "INTERNAL"; + port->class = DDB_PORT_CI; + port->type = DDB_CI_INTERNAL; -+ } else if (port_has_cxd(port, &id)) { ++ } ++ ++ if (!port->i2c) ++ return; ++ ++ /* Probe ports with I2C */ ++ ++ if (port_has_cxd(port, &id)) { + if (id == 1) { + port->name = "CI"; ++ port->type_name = "CXD2099"; + port->class = DDB_PORT_CI; + port->type = DDB_CI_EXTERNAL_SONY; + ddbwritel(dev, I2C_SPEED_400, + port->i2c->regs + I2C_TIMING); + } else { -+ pr_info(KERN_INFO "Port %d: Uninitialized DuoFlex\n", ++ pr_info("Port %d: Uninitialized DuoFlex\n", + port->nr); + return; + } -+ } else if (port_has_xo2(port, &id)) { ++ } else if (port_has_xo2(port, &type, &id)) { + ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING); ++ /*pr_info("XO2 ID %02x\n", id);*/ ++ if (type == 2) { ++ port->name = "DuoFlex CI"; ++ port->class = DDB_PORT_CI; ++ port->type = DDB_CI_EXTERNAL_XO2; ++ port->type_name = "CI_XO2"; ++ init_xo2_ci(port); ++ return; ++ } + id >>= 2; + if (id > 5) { + port->name = "unknown XO2 DuoFlex"; ++ port->type_name = "UNKNOWN"; + } else { ++ port->name = xo2names[id]; + port->class = DDB_PORT_TUNER; + port->type = DDB_TUNER_XO2 + id; -+ port->name = xo2names[id]; ++ port->type_name = xo2types[id]; + init_xo2(port); + } + } else if (port_has_cxd28xx(port, &id)) { + switch (id) { + case 0xa4: -+ port->name = "DUAL DVB-CT2 CXD2843"; ++ port->name = "DUAL DVB-C2T2 CXD2843"; + port->type = DDB_TUNER_DVBC2T2_SONY_P; ++ port->type_name = "DVBC2T2_SONY"; + break; + case 0xb1: + port->name = "DUAL DVB-CT2 CXD2837"; + port->type = DDB_TUNER_DVBCT2_SONY_P; ++ port->type_name = "DVBCT2_SONY"; + break; + case 0xb0: + port->name = "DUAL ISDB-T CXD2838"; + port->type = DDB_TUNER_ISDBT_SONY_P; ++ port->type_name = "ISDBT_SONY"; + break; + default: + return; @@ -25130,32 +20769,38 @@ index 9e3492e..c2fc010 100644 + port->name = "DUAL DVB-S2"; + port->class = DDB_PORT_TUNER; + port->type = DDB_TUNER_DVBS_ST; ++ port->type_name = "DVBS_ST"; + ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING); + } else if (port_has_stv0900_aa(port, &id)) { + port->name = "DUAL DVB-S2"; + port->class = DDB_PORT_TUNER; -+ port->type = DDB_TUNER_DVBS_ST_AA; -+ if (id == 0x51) -+ port->type = DDB_TUNER_DVBS_STV0910_P; -+ else ++ if (id == 0x51) { ++ if (port->nr == 0 && ++ dev->link[l].info->ts_quirks & TS_QUIRK_REVERSED) ++ port->type = DDB_TUNER_DVBS_STV0910_PR; ++ else ++ port->type = DDB_TUNER_DVBS_STV0910_P; ++ port->type_name = "DVBS_ST_0910"; ++ } else { + port->type = DDB_TUNER_DVBS_ST_AA; ++ port->type_name = "DVBS_ST_AA"; + } + ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING); + } else if (port_has_drxks(port)) { + port->name = "DUAL DVB-C/T"; + port->class = DDB_PORT_TUNER; + port->type = DDB_TUNER_DVBCT_TR; ++ port->type_name = "DVBCT_TR"; + ddbwritel(dev, I2C_SPEED_400, port->i2c->regs + I2C_TIMING); + } else if (port_has_stv0367(port)) { + port->name = "DUAL DVB-C/T"; + port->class = DDB_PORT_TUNER; + port->type = DDB_TUNER_DVBCT_ST; ++ port->type_name = "DVBCT_ST"; + ddbwritel(dev, I2C_SPEED_100, port->i2c->regs + I2C_TIMING); + } else if (port_has_encti(port)) { + port->name = "ENCTI"; + port->class = DDB_PORT_LOOP; -+ } else if (port->nr == ts_loop) { -+ port->name = "TS LOOP"; -+ port->class = DDB_PORT_LOOP; + } +} + @@ -25184,7 +20829,7 @@ index 9e3492e..c2fc010 100644 + int slot, int address) +{ + struct ddb_ci *ci = ca->data; -+ u32 val, off = (address >> 1) & (CI_BUFFER_SIZE-1); ++ u32 val, off = (address >> 1) & (CI_BUFFER_SIZE - 1); + + if (address > CI_BUFFER_SIZE) + return -1; @@ -25254,69 +20899,39 @@ index 9e3492e..c2fc010 100644 + CI_CONTROL(ci->nr)); + return 0; +} - --/****************************************************************************/ --/****************************************************************************/ --/****************************************************************************/ ++ +static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot) +{ + struct ddb_ci *ci = ca->data; - --static void input_tasklet(unsigned long data) ++ + ddbwritel(ci->port->dev, 0, CI_CONTROL(ci->nr)); + msleep(300); + return 0; +} + +static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot) - { -- struct ddb_input *input = (struct ddb_input *) data; -- struct ddb *dev = input->port->dev; ++{ + struct ddb_ci *ci = ca->data; + u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr)); - -- spin_lock(&input->lock); -- if (!input->running) { -- spin_unlock(&input->lock); -- return; -- } -- input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); ++ + ddbwritel(ci->port->dev, val | CI_BYPASS_DISABLE, + CI_CONTROL(ci->nr)); + return 0; +} - -- if (input->port->class == DDB_PORT_TUNER) { -- if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr))) -- printk(KERN_ERR "Overflow input %d\n", input->nr); -- while (input->cbuf != ((input->stat >> 11) & 0x1f) -- || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) { -- dvb_dmx_swfilter_packets(&input->demux, -- input->vbuf[input->cbuf], -- input->dma_buf_size / 188); ++ +static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open) +{ + struct ddb_ci *ci = ca->data; + u32 val = ddbreadl(ci->port->dev, CI_CONTROL(ci->nr)); + int stat = 0; - -- input->cbuf = (input->cbuf + 1) % input->dma_buf_num; -- ddbwritel((input->cbuf << 11), -- DMA_BUFFER_ACK(input->nr)); -- input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); -- } -- } -- if (input->port->class == DDB_PORT_CI) -- wake_up(&input->wq); -- spin_unlock(&input->lock); ++ + if (val & CI_CAM_DETECT) + stat |= DVB_CA_EN50221_POLL_CAM_PRESENT; + if (val & CI_CAM_READY) + stat |= DVB_CA_EN50221_POLL_CAM_READY; + return stat; - } - --static void output_tasklet(unsigned long data) ++} ++ +static struct dvb_ca_en50221 en_templ = { + .read_attribute_mem = read_attribute_mem, + .write_attribute_mem = write_attribute_mem, @@ -25329,228 +20944,336 @@ index 9e3492e..c2fc010 100644 +}; + +static void ci_attach(struct ddb_port *port) - { -- struct ddb_output *output = (struct ddb_output *) data; -- struct ddb *dev = output->port->dev; ++{ + struct ddb_ci *ci = 0; - -- spin_lock(&output->lock); -- if (!output->running) { -- spin_unlock(&output->lock); ++ + ci = kzalloc(sizeof(*ci), GFP_KERNEL); + if (!ci) - return; -- } -- output->stat = ddbreadl(DMA_BUFFER_CURRENT(output->nr + 8)); -- wake_up(&output->wq); -- spin_unlock(&output->lock); ++ return; + memcpy(&ci->en, &en_templ, sizeof(en_templ)); + ci->en.data = ci; + port->en = &ci->en; + ci->port = port; + ci->nr = port->nr - 2; - } - ++} ++ +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + - --static struct cxd2099_cfg cxd_cfg = { -- .bitrate = 62000, ++static int write_creg(struct ddb_ci *ci, u8 data, u8 mask) ++{ ++ struct i2c_adapter *i2c = &ci->port->i2c->adap; ++ u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13; ++ ++ ci->port->creg = (ci->port->creg & ~mask) | data; ++ return i2c_write_reg(i2c, adr, 0x02, ci->port->creg); ++} ++ ++static int read_attribute_mem_xo2(struct dvb_ca_en50221 *ca, ++ int slot, int address) ++{ ++ struct ddb_ci *ci = ca->data; ++ struct i2c_adapter *i2c = &ci->port->i2c->adap; ++ u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13; ++ int res; ++ u8 val; ++ ++ res = i2c_read_reg16(i2c, adr, 0x8000 | address, &val); ++ return res ? res : val; ++} ++ ++static int write_attribute_mem_xo2(struct dvb_ca_en50221 *ca, int slot, ++ int address, u8 value) ++{ ++ struct ddb_ci *ci = ca->data; ++ struct i2c_adapter *i2c = &ci->port->i2c->adap; ++ u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13; ++ ++ return i2c_write_reg16(i2c, adr, 0x8000 | address, value); ++} ++ ++static int read_cam_control_xo2(struct dvb_ca_en50221 *ca, ++ int slot, u8 address) ++{ ++ struct ddb_ci *ci = ca->data; ++ struct i2c_adapter *i2c = &ci->port->i2c->adap; ++ u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13; ++ u8 val; ++ int res; ++ ++ res = i2c_read_reg(i2c, adr, 0x20 | (address & 3), &val); ++ return res ? res : val; ++} ++ ++static int write_cam_control_xo2(struct dvb_ca_en50221 *ca, int slot, ++ u8 address, u8 value) ++{ ++ struct ddb_ci *ci = ca->data; ++ struct i2c_adapter *i2c = &ci->port->i2c->adap; ++ u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13; ++ ++ return i2c_write_reg(i2c, adr, 0x20 | (address & 3), value); ++} ++ ++static int slot_reset_xo2(struct dvb_ca_en50221 *ca, int slot) ++{ ++ struct ddb_ci *ci = ca->data; ++ ++ pr_info("%s\n", __func__); ++ write_creg(ci, 0x01, 0x01); ++ write_creg(ci, 0x04, 0x04); ++ msleep(20); ++ write_creg(ci, 0x02, 0x02); ++ write_creg(ci, 0x00, 0x04); ++ write_creg(ci, 0x18, 0x18); ++ return 0; ++} ++ ++static int slot_shutdown_xo2(struct dvb_ca_en50221 *ca, int slot) ++{ ++ struct ddb_ci *ci = ca->data; ++ ++ pr_info("%s\n", __func__); ++ write_creg(ci, 0x10, 0xff); ++ write_creg(ci, 0x08, 0x08); ++ return 0; ++} ++ ++static int slot_ts_enable_xo2(struct dvb_ca_en50221 *ca, int slot) ++{ ++ struct ddb_ci *ci = ca->data; ++ ++ pr_info("%s\n", __func__); ++ write_creg(ci, 0x00, 0x10); ++ return 0; ++} ++ ++static int poll_slot_status_xo2(struct dvb_ca_en50221 *ca, int slot, int open) ++{ ++ struct ddb_ci *ci = ca->data; ++ struct i2c_adapter *i2c = &ci->port->i2c->adap; ++ u8 adr = (ci->port->type == DDB_CI_EXTERNAL_XO2) ? 0x12 : 0x13; ++ u8 val = 0; ++ int stat = 0; ++ ++ i2c_read_reg(i2c, adr, 0x01, &val); ++ ++ if (val & 2) ++ stat |= DVB_CA_EN50221_POLL_CAM_PRESENT; ++ if (val & 1) ++ stat |= DVB_CA_EN50221_POLL_CAM_READY; ++ return stat; ++} ++ ++static struct dvb_ca_en50221 en_xo2_templ = { ++ .read_attribute_mem = read_attribute_mem_xo2, ++ .write_attribute_mem = write_attribute_mem_xo2, ++ .read_cam_control = read_cam_control_xo2, ++ .write_cam_control = write_cam_control_xo2, ++ .slot_reset = slot_reset_xo2, ++ .slot_shutdown = slot_shutdown_xo2, ++ .slot_ts_enable = slot_ts_enable_xo2, ++ .poll_slot_status = poll_slot_status_xo2, ++}; ++ ++static void ci_xo2_attach(struct ddb_port *port) ++{ ++ struct ddb_ci *ci = 0; ++ struct i2c_adapter *i2c; ++ ++ ci = kzalloc(sizeof(*ci), GFP_KERNEL); ++ if (!ci) ++ return; ++ memcpy(&ci->en, &en_xo2_templ, sizeof(en_xo2_templ)); ++ ci->en.data = ci; ++ port->en = &ci->en; ++ ci->port = port; ++ ci->nr = port->nr - 2; ++ ci->port->creg = 0; ++ i2c = &ci->port->i2c->adap; ++ write_creg(ci, 0x10, 0xff); ++ write_creg(ci, 0x08, 0x08); ++} ++ ++/****************************************************************************/ ++/****************************************************************************/ ++/****************************************************************************/ ++ ++ +struct cxd2099_cfg cxd_cfg = { + .bitrate = 72000, - .adr = 0x40, - .polarity = 1, - .clock_mode = 1, -@@ -1045,28 +2163,21 @@ static struct cxd2099_cfg cxd_cfg = { - - static int ddb_ci_attach(struct ddb_port *port) - { -- int ret; -- -- ret = dvb_register_adapter(&port->output->adap, -- "DDBridge", -- THIS_MODULE, -- &port->dev->pdev->dev, -- adapter_nr); -- if (ret < 0) -- return ret; -- port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap); -- if (!port->en) { -- dvb_unregister_adapter(&port->output->adap); -- return -ENODEV; -+ if (port->type == DDB_CI_EXTERNAL_SONY) { ++ .adr = 0x40, ++ .polarity = 1, ++ .clock_mode = 1, ++ .max_i2c = 512, ++}; ++ ++static int ddb_ci_attach(struct ddb_port *port) ++{ ++ switch (port->type) { ++ case DDB_CI_EXTERNAL_SONY: + cxd_cfg.bitrate = ci_bitrate; + port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap); + if (!port->en) + return -ENODEV; + dvb_ca_en50221_init(port->dvb[0].adap, + port->en, 0, 1); - } -- ddb_input_start(port->input[0]); -- ddb_output_start(port->output); -- dvb_ca_en50221_init(&port->output->adap, -- port->en, 0, 1); -- ret = dvb_register_device(&port->output->adap, &port->output->dev, -- &dvbdev_ci, (void *) port->output, -- DVB_DEVICE_SEC); -- return ret; -+ if (port->type == DDB_CI_INTERNAL) { ++ break; ++ ++ case DDB_CI_EXTERNAL_XO2: ++ case DDB_CI_EXTERNAL_XO2_B: ++ ci_xo2_attach(port); ++ if (!port->en) ++ return -ENODEV; ++ dvb_ca_en50221_init(port->dvb[0].adap, port->en, 0, 1); ++ break; ++ ++ case DDB_CI_INTERNAL: + ci_attach(port); + if (!port->en) + return -ENODEV; + dvb_ca_en50221_init(port->dvb[0].adap, port->en, 0, 1); ++ break; + } + return 0; - } - - static int ddb_port_attach(struct ddb_port *port) -@@ -1079,15 +2190,32 @@ static int ddb_port_attach(struct ddb_port *port) - if (ret < 0) - break; - ret = dvb_input_attach(port->input[1]); ++} ++ ++static int ddb_port_attach(struct ddb_port *port) ++{ ++ int ret = 0; ++ ++ switch (port->class) { ++ case DDB_PORT_TUNER: ++ ret = dvb_input_attach(port->input[0]); ++ if (ret < 0) ++ break; ++ ret = dvb_input_attach(port->input[1]); + if (ret < 0) + break; + port->input[0]->redi = port->input[0]; + port->input[1]->redi = port->input[1]; - break; - case DDB_PORT_CI: - ret = ddb_ci_attach(port); ++ break; ++ case DDB_PORT_CI: ++ ret = ddb_ci_attach(port); + if (ret < 0) + break; + case DDB_PORT_LOOP: + ret = dvb_register_device(port->dvb[0].adap, + &port->dvb[0].dev, + &dvbdev_ci, (void *) port->output, -+ DVB_DEVICE_CI); ++ DVB_DEVICE_CI, 0); + break; + case DDB_PORT_MOD: + ret = dvb_register_device(port->dvb[0].adap, + &port->dvb[0].dev, + &dvbdev_mod, (void *) port->output, -+ DVB_DEVICE_MOD); - break; - default: - break; - } - if (ret < 0) -- printk(KERN_ERR "port_attach on port %d failed\n", port->nr); ++ DVB_DEVICE_MOD, 0); ++ break; ++ default: ++ break; ++ } ++ if (ret < 0) + pr_err("port_attach on port %d failed\n", port->nr); - return ret; - } - -@@ -1096,6 +2224,21 @@ static int ddb_ports_attach(struct ddb *dev) - int i, ret = 0; - struct ddb_port *port; - -+ if (dev->ids.devid == 0x0301dd01) -+ dev->ns_num = 15; -+ else -+ dev->ns_num = dev->info->ns_num; ++ return ret; ++} ++ ++static int ddb_ports_attach(struct ddb *dev) ++{ ++ int i, ret = 0; ++ struct ddb_port *port; ++ ++ dev->ns_num = dev->link[0].info->ns_num; + for (i = 0; i < dev->ns_num; i++) + dev->ns[i].nr = i; + pr_info("%d netstream channels\n", dev->ns_num); + -+ if (dev->info->port_num) { ++ if (dev->port_num) { + ret = dvb_register_adapters(dev); + if (ret < 0) { + pr_err("Registering adapters failed. Check DVB_MAX_ADAPTERS in config.\n"); + return ret; + } + } - for (i = 0; i < dev->info->port_num; i++) { - port = &dev->port[i]; - ret = ddb_port_attach(port); -@@ -1112,124 +2255,259 @@ static void ddb_ports_detach(struct ddb *dev) - - for (i = 0; i < dev->info->port_num; i++) { - port = &dev->port[i]; ++ for (i = 0; i < dev->port_num; i++) { ++ port = &dev->port[i]; ++ ret = ddb_port_attach(port); ++ } ++ return ret; ++} + - switch (port->class) { - case DDB_PORT_TUNER: - dvb_input_detach(port->input[0]); - dvb_input_detach(port->input[1]); - break; - case DDB_PORT_CI: -- dvb_unregister_device(port->output->dev); ++static void ddb_ports_detach(struct ddb *dev) ++{ ++ int i; ++ struct ddb_port *port; ++ ++ for (i = 0; i < dev->port_num; i++) { ++ port = &dev->port[i]; ++ ++ switch (port->class) { ++ case DDB_PORT_TUNER: ++ dvb_input_detach(port->input[0]); ++ dvb_input_detach(port->input[1]); ++ break; ++ case DDB_PORT_CI: + case DDB_PORT_LOOP: + if (port->dvb[0].dev) + dvb_unregister_device(port->dvb[0].dev); - if (port->en) { -- ddb_input_stop(port->input[0]); -- ddb_output_stop(port->output); - dvb_ca_en50221_release(port->en); - kfree(port->en); -- port->en = NULL; -- dvb_unregister_adapter(&port->output->adap); -+ port->en = 0; - } - break; ++ if (port->en) { ++ dvb_ca_en50221_release(port->en); ++ kfree(port->en); ++ port->en = NULL; ++ } ++ break; + case DDB_PORT_MOD: + if (port->dvb[0].dev) + dvb_unregister_device(port->dvb[0].dev); + break; - } - } ++ } ++ } + dvb_unregister_adapters(dev); - } - --/****************************************************************************/ --/****************************************************************************/ - --static int port_has_ci(struct ddb_port *port) ++} ++ ++ +/* Copy input DMA pointers to output DMA and ACK. */ + +static void input_write_output(struct ddb_input *input, + struct ddb_output *output) - { -- u8 val; -- return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1; ++{ + ddbwritel(output->port->dev, + input->dma->stat, DMA_BUFFER_ACK(output->dma->nr)); + output->dma->cbuf = (input->dma->stat >> 11) & 0x1f; + output->dma->coff = (input->dma->stat & 0x7ff) << 7; - } - --static int port_has_stv0900(struct ddb_port *port) ++} ++ +static void output_ack_input(struct ddb_output *output, + struct ddb_input *input) - { -- u8 val; -- if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0) -- return 0; -- return 1; ++{ + ddbwritel(input->port->dev, + output->dma->stat, DMA_BUFFER_ACK(input->dma->nr)); - } - --static int port_has_stv0900_aa(struct ddb_port *port) ++} ++ +static void input_write_dvb(struct ddb_input *input, + struct ddb_input *input2) - { -- u8 val; -- if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0) -- return 0; -- return 1; ++{ + struct ddb_dvb *dvb = &input2->port->dvb[input2->nr & 1]; + struct ddb_dma *dma, *dma2; + struct ddb *dev = input->port->dev; -+ int noack = 0; ++ int ack = 1; + + dma = dma2 = input->dma; + /* if there also is an output connected, do not ACK. -+ input_write_output will ACK. */ ++ * input_write_output will ACK. ++ */ + if (input->redo) { + dma2 = input->redo->dma; -+ noack = 1; ++ ack = 0; + } + while (dma->cbuf != ((dma->stat >> 11) & 0x1f) + || (4 & dma->ctrl)) { + if (4 & dma->ctrl) { + /*pr_err("Overflow dma %d\n", dma->nr);*/ -+ if (noack) -+ noack = 0; ++ ack = 1; + } +#ifdef DDB_ALT_DMA + dma_sync_single_for_cpu(dev->dev, dma2->pbuf[dma->cbuf], @@ -25560,24 +21283,17 @@ index 9e3492e..c2fc010 100644 + dma2->vbuf[dma->cbuf], + dma2->size / 188); + dma->cbuf = (dma->cbuf + 1) % dma2->num; -+ if (!noack) ++ if (ack) + ddbwritel(dev, (dma->cbuf << 11), + DMA_BUFFER_ACK(dma->nr)); + dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); + dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr)); + } - } - --static int port_has_drxks(struct ddb_port *port) ++} ++ +#ifdef DDB_USE_WORK +static void input_work(struct work_struct *work) - { -- u8 val; -- if (i2c_read(&port->i2c->adap, 0x29, &val) < 0) -- return 0; -- if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0) -- return 0; -- return 1; ++{ + struct ddb_dma *dma = container_of(work, struct ddb_dma, work); + struct ddb_input *input = (struct ddb_input *) dma->io; +#else @@ -25587,59 +21303,34 @@ index 9e3492e..c2fc010 100644 + struct ddb_dma *dma = input->dma; +#endif + struct ddb *dev = input->port->dev; ++ unsigned long flags; + -+ spin_lock(&dma->lock); ++ spin_lock_irqsave(&dma->lock, flags); + if (!dma->running) { -+ spin_unlock(&dma->lock); ++ spin_unlock_irqrestore(&dma->lock, flags); + return; + } + dma->stat = ddbreadl(dev, DMA_BUFFER_CURRENT(dma->nr)); + dma->ctrl = ddbreadl(dev, DMA_BUFFER_CONTROL(dma->nr)); + -+#if 0 -+ if (4 & dma->ctrl) -+ pr_err("Overflow dma %d\n", dma->nr); -+#endif + if (input->redi) + input_write_dvb(input, input->redi); + if (input->redo) + input_write_output(input, input->redo); + wake_up(&dma->wq); -+ spin_unlock(&dma->lock); - } - --static void ddb_port_probe(struct ddb_port *port) ++ spin_unlock_irqrestore(&dma->lock, flags); ++} ++ +static void input_handler(unsigned long data) - { -- struct ddb *dev = port->dev; -- char *modname = "NO MODULE"; ++{ + struct ddb_input *input = (struct ddb_input *) data; + struct ddb_dma *dma = input->dma; - -- port->class = DDB_PORT_NONE; - -- if (port_has_ci(port)) { -- modname = "CI"; -- port->class = DDB_PORT_CI; -- ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); -- } else if (port_has_stv0900(port)) { -- modname = "DUAL DVB-S2"; -- port->class = DDB_PORT_TUNER; -- port->type = DDB_TUNER_DVBS_ST; -- ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); -- } else if (port_has_stv0900_aa(port)) { -- modname = "DUAL DVB-S2"; -- port->class = DDB_PORT_TUNER; -- port->type = DDB_TUNER_DVBS_ST_AA; -- ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); -- } else if (port_has_drxks(port)) { -- modname = "DUAL DVB-C/T"; -- port->class = DDB_PORT_TUNER; -- port->type = DDB_TUNER_DVBCT_TR; -- ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); ++ ++ + /* If there is no input connected, input_tasklet() will -+ just copy pointers and ACK. So, there is no need to go -+ through the tasklet scheduler. */ ++ * just copy pointers and ACK. So, there is no need to go ++ * through the tasklet scheduler. ++ */ +#ifdef DDB_USE_WORK + if (input->redi) + queue_work(ddb_wq, &dma->work); @@ -25653,19 +21344,6 @@ index 9e3492e..c2fc010 100644 +#endif +} + -+/* hmm, don't really need this anymore. -+ The output IRQ just copies some pointers, acks and wakes. */ -+ -+#ifdef DDB_USE_WORK -+static void output_work(struct work_struct *work) -+{ -+} -+#else -+static void output_tasklet(unsigned long data) -+{ -+} -+#endif -+ +static void output_handler(unsigned long data) +{ + struct ddb_output *output = (struct ddb_output *) data; @@ -25701,11 +21379,6 @@ index 9e3492e..c2fc010 100644 + spin_lock_init(&dma->lock); + init_waitqueue_head(&dma->wq); + if (out) { -+#ifdef DDB_USE_WORK -+ INIT_WORK(&dma->work, output_work); -+#else -+ tasklet_init(&dma->tasklet, output_tasklet, priv); -+#endif + dma->num = OUTPUT_DMA_BUFS; + dma->size = OUTPUT_DMA_SIZE; + dma->div = OUTPUT_DMA_IRQ_DIV; @@ -25718,33 +21391,22 @@ index 9e3492e..c2fc010 100644 + dma->num = INPUT_DMA_BUFS; + dma->size = INPUT_DMA_SIZE; + dma->div = INPUT_DMA_IRQ_DIV; - } -- printk(KERN_INFO "Port %d (TAB %d): %s\n", -- port->nr, port->nr+1, modname); - } - --static void ddb_input_init(struct ddb_port *port, int nr) -+static void ddb_input_init(struct ddb_port *port, int nr, int pnr, int dma_nr) - { - struct ddb *dev = port->dev; - struct ddb_input *input = &dev->input[nr]; - ++ } ++} ++ ++static void ddb_input_init(struct ddb_port *port, int nr, int pnr, ++ int dma_nr, int anr) ++{ ++ struct ddb *dev = port->dev; ++ struct ddb_input *input = &dev->input[anr]; ++ + if (dev->has_dma) { + dev->handler[dma_nr + 8] = input_handler; + dev->handler_data[dma_nr + 8] = (unsigned long) input; + } + port->input[pnr] = input; - input->nr = nr; - input->port = port; -- input->dma_buf_num = INPUT_DMA_BUFS; -- input->dma_buf_size = INPUT_DMA_SIZE; -- ddbwritel(0, TS_INPUT_CONTROL(nr)); -- ddbwritel(2, TS_INPUT_CONTROL(nr)); -- ddbwritel(0, TS_INPUT_CONTROL(nr)); -- ddbwritel(0, DMA_BUFFER_ACK(nr)); -- tasklet_init(&input->tasklet, input_tasklet, (unsigned long) input); -- spin_lock_init(&input->lock); -- init_waitqueue_head(&input->wq); ++ input->nr = nr; ++ input->port = port; + if (dev->has_dma) { + input->dma = &dev->dma[dma_nr]; + ddb_dma_init(input->dma, dma_nr, (void *) input, 0); @@ -25752,31 +21414,22 @@ index 9e3492e..c2fc010 100644 + ddbwritel(dev, 0, TS_INPUT_CONTROL(nr)); + ddbwritel(dev, 2, TS_INPUT_CONTROL(nr)); + ddbwritel(dev, 0, TS_INPUT_CONTROL(nr)); -+ if (dev->has_dma) ++ if (input->dma) + ddbwritel(dev, 0, DMA_BUFFER_ACK(input->dma->nr)); - } - --static void ddb_output_init(struct ddb_port *port, int nr) ++} ++ +static void ddb_output_init(struct ddb_port *port, int nr, int dma_nr) - { - struct ddb *dev = port->dev; - struct ddb_output *output = &dev->output[nr]; ++{ ++ struct ddb *dev = port->dev; ++ struct ddb_output *output = &dev->output[nr]; + + if (dev->has_dma) { + dev->handler[dma_nr + 8] = output_handler; + dev->handler_data[dma_nr + 8] = (unsigned long) output; + } + port->output = output; - output->nr = nr; - output->port = port; -- output->dma_buf_num = OUTPUT_DMA_BUFS; -- output->dma_buf_size = OUTPUT_DMA_SIZE; -- -- ddbwritel(0, TS_OUTPUT_CONTROL(nr)); -- ddbwritel(2, TS_OUTPUT_CONTROL(nr)); -- ddbwritel(0, TS_OUTPUT_CONTROL(nr)); -- tasklet_init(&output->tasklet, output_tasklet, (unsigned long) output); -- init_waitqueue_head(&output->wq); ++ output->nr = nr; ++ output->port = port; + if (dev->has_dma) { + output->dma = &dev->dma[dma_nr]; + ddb_dma_init(output->dma, dma_nr, (void *) output, 1); @@ -25788,108 +21441,157 @@ index 9e3492e..c2fc010 100644 + ddbwritel(dev, 2, TS_OUTPUT_CONTROL(nr)); + ddbwritel(dev, 0, TS_OUTPUT_CONTROL(nr)); + } -+ if (dev->has_dma) ++ if (output->dma) + ddbwritel(dev, 0, DMA_BUFFER_ACK(output->dma->nr)); - } - - static void ddb_ports_init(struct ddb *dev) -@@ -1237,20 +2515,53 @@ static void ddb_ports_init(struct ddb *dev) - int i; - struct ddb_port *port; - -+ if (dev->info->board_control) { -+ ddbwritel(dev, 0, BOARD_CONTROL); -+ msleep(100); -+ ddbwritel(dev, 4, BOARD_CONTROL); -+ usleep_range(2000, 3000); -+ ddbwritel(dev, 4 | dev->info->board_control, BOARD_CONTROL); -+ usleep_range(2000, 3000); -+ } ++} + - for (i = 0; i < dev->info->port_num; i++) { - port = &dev->port[i]; - port->dev = dev; - port->nr = i; -- port->i2c = &dev->i2c[i]; -- port->input[0] = &dev->input[2 * i]; -- port->input[1] = &dev->input[2 * i + 1]; -- port->output = &dev->output[i]; -- -+ if (dev->info->i2c_num > i) ++static int ddb_port_match_i2c(struct ddb_port *port) ++{ ++ struct ddb *dev = port->dev; ++ u32 i; ++ ++ for (i = 0; i < dev->i2c_num; i++) { ++ if (dev->i2c[i].link == port->lnr && ++ dev->i2c[i].nr == port->nr) { + port->i2c = &dev->i2c[i]; -+ port->gap = 4; -+ port->obr = ci_bitrate; - mutex_init(&port->i2c_gate_lock); - ddb_port_probe(port); -- ddb_input_init(port, 2 * i); -- ddb_input_init(port, 2 * i + 1); -- ddb_output_init(port, i); -+ pr_info("Port %d (TAB %d): %s\n", -+ port->nr, port->nr + 1, port->name); ++ return 1; ++ } ++ } ++ return 0; ++} + -+ port->dvb[0].adap = &dev->adap[2 * i]; -+ port->dvb[1].adap = &dev->adap[2 * i + 1]; ++static void ddb_ports_init(struct ddb *dev) ++{ ++ u32 i, l, p, li2c; ++ struct ddb_port *port; ++ struct ddb_info *info; ++ struct ddb_regmap *rm; ++ int portmatch; + -+ if ((dev->info->type == DDB_OCTOPUS_CI) || -+ (dev->info->type == DDB_OCTONET) || -+ (dev->info->type == DDB_OCTOPUS)) { -+ if (i >= 2 && dev->info->type == DDB_OCTOPUS_CI) { -+ ddb_input_init(port, 2 + i, 0, 2 + i); -+ ddb_input_init(port, 4 + i, 1, 4 + i); -+ } else { -+ ddb_input_init(port, 2 * i, 0, 2 * i); -+ ddb_input_init(port, 2 * i + 1, 1, 2 * i + 1); ++ for (p = l = 0; l < DDB_MAX_LINK; l++) { ++ info = dev->link[l].info; ++ if (!info) ++ continue; ++ rm = info->regmap; ++ if (!rm) ++ continue; ++ for (li2c = 0; li2c < dev->i2c_num; li2c++) ++ if (dev->i2c[li2c].link == l) ++ break; ++ for (i = 0; i < info->port_num; i++, p++) { ++ port = &dev->port[p]; ++ port->dev = dev; ++ port->nr = i; ++ port->lnr = l; ++ port->pnr = p; ++ port->gap = 4; ++ port->obr = ci_bitrate; ++ mutex_init(&port->i2c_gate_lock); ++ ++ portmatch = ddb_port_match_i2c(port); ++ if (!portmatch) { ++ if (info->type == DDB_OCTOPUS_MAX) ++ port->i2c = &dev->i2c[li2c]; ++ } ++ ++ ddb_port_probe(port); ++ ++ port->dvb[0].adap = &dev->adap[2 * p]; ++ port->dvb[1].adap = &dev->adap[2 * p + 1]; ++ ++ if ((port->class == DDB_PORT_NONE) && i && ++ dev->port[p - 1].type == DDB_CI_EXTERNAL_XO2) { ++ port->class = DDB_PORT_CI; ++ port->type = DDB_CI_EXTERNAL_XO2_B; ++ port->name = "DuoFlex CI_B"; ++ port->i2c = dev->port[p - 1].i2c; ++ } ++ ++ pr_info("Port %u: Link %u, Link Port %u (TAB %u): %s\n", ++ port->pnr, port->lnr, port->nr, port->nr + 1, ++ port->name); ++ ++ if (port->class == DDB_PORT_CI && ++ port->type == DDB_CI_EXTERNAL_XO2) { ++ ddb_input_init(port, 2 * i, 0, 2 * i, 2 * i); ++ ddb_output_init(port, i, i + 8); ++ continue; ++ } ++ ++ if (port->class == DDB_PORT_CI && ++ port->type == DDB_CI_EXTERNAL_XO2_B) { ++ ddb_input_init(port, 2 * i - 1, 0, 2 * i - 1, ++ 2 * i - 1); ++ ddb_output_init(port, i, i + 8); ++ continue; ++ } ++ ++ switch (dev->link[l].info->type) { ++ case DDB_OCTOPUS_CI: ++ if (i >= 2) { ++ ddb_input_init(port, 2 + i, 0, 2 + i, ++ 2 + i); ++ ddb_input_init(port, 4 + i, 1, 4 + i, ++ 4 + i); ++ ddb_output_init(port, i, i + 8); ++ break; ++ } /* fallthrough */ ++ case DDB_OCTONET: ++ case DDB_OCTOPUS: ++ ddb_input_init(port, 2 * i, 0, 2 * i, 2 * i); ++ ddb_input_init(port, 2 * i + 1, 1, 2 * i + 1, ++ 2 * i + 1); ++ ddb_output_init(port, i, i + 8); ++ break; ++ case DDB_OCTOPUS_MAX: ++ case DDB_OCTOPUS_MAX_CT: ++ ddb_input_init(port, 2 * i, 0, 2 * i, 2 * p); ++ ddb_input_init(port, 2 * i + 1, 1, 2 * i + 1, ++ 2 * p + 1); ++ break; ++ case DDB_MOD: ++ ddb_output_init(port, i, i); ++ dev->handler[i + 18] = ddbridge_mod_rate_handler; ++ dev->handler_data[i + 18] = ++ (unsigned long) &dev->output[i]; ++ break; ++ default: ++ break; + } -+ ddb_output_init(port, i, i + 8); + } -+ if (dev->info->type == DDB_OCTOPUS_MAX) { -+ ddb_input_init(port, 2 * i, 0, 2 * i); -+ ddb_input_init(port, 2 * i + 1, 1, 2 * i + 1); -+ } -+ if (dev->info->type == DDB_MOD) { -+ ddb_output_init(port, i, i); -+ dev->handler[i + 18] = ddbridge_mod_rate_handler; -+ dev->handler_data[i + 18] = -+ (unsigned long) &dev->output[i]; -+ } - } - } - -@@ -1259,12 +2570,25 @@ static void ddb_ports_release(struct ddb *dev) - int i; - struct ddb_port *port; - -+ if (!dev->has_dma) -+ return; - for (i = 0; i < dev->info->port_num; i++) { - port = &dev->port[i]; -- port->dev = dev; -- tasklet_kill(&port->input[0]->tasklet); -- tasklet_kill(&port->input[1]->tasklet); -- tasklet_kill(&port->output->tasklet); ++ } ++ dev->port_num = p; ++} ++ ++static void ddb_ports_release(struct ddb *dev) ++{ ++ int i; ++ struct ddb_port *port; ++ ++ for (i = 0; i < dev->port_num; i++) { ++ port = &dev->port[i]; +#ifdef DDB_USE_WORK -+ if (port->input[0]) ++ if (port->input[0] && port->input[0]->dma) + cancel_work_sync(&port->input[0]->dma->work); -+ if (port->input[1]) ++ if (port->input[1] && port->input[1]->dma) + cancel_work_sync(&port->input[1]->dma->work); -+ if (port->output) ++ if (port->output && port->output->dma) + cancel_work_sync(&port->output->dma->work); +#else -+ if (port->input[0]) ++ if (port->input[0] && port->input[0]->dma) + tasklet_kill(&port->input[0]->dma->tasklet); -+ if (port->input[1]) ++ if (port->input[1] && port->input[1]->dma) + tasklet_kill(&port->input[1]->dma->tasklet); -+ if (port->output) ++ if (port->output && port->output->dma) + tasklet_kill(&port->output->dma->tasklet); +#endif - } - } - -@@ -1272,90 +2596,306 @@ static void ddb_ports_release(struct ddb *dev) - /****************************************************************************/ - /****************************************************************************/ - --static void irq_handle_i2c(struct ddb *dev, int n) ++ } ++} ++ ++/****************************************************************************/ ++/****************************************************************************/ ++/****************************************************************************/ ++ +#define IRQ_HANDLE(_nr) \ + do { if ((s & (1UL << _nr)) && dev->handler[_nr]) \ + dev->handler[_nr](dev->handler_data[_nr]); } \ @@ -25907,38 +21609,52 @@ index 9e3492e..c2fc010 100644 +static void irq_handle_io(struct ddb *dev, u32 s) +{ + dev->ts_irq++; -+ IRQ_HANDLE(8); -+ IRQ_HANDLE(9); -+ IRQ_HANDLE(10); -+ IRQ_HANDLE(11); -+ IRQ_HANDLE(12); -+ IRQ_HANDLE(13); -+ IRQ_HANDLE(14); -+ IRQ_HANDLE(15); -+ IRQ_HANDLE(16); -+ IRQ_HANDLE(17); -+ IRQ_HANDLE(18); -+ IRQ_HANDLE(19); -+ if (dev->info->type != DDB_MOD) -+ return; -+ IRQ_HANDLE(20); -+ IRQ_HANDLE(21); -+ IRQ_HANDLE(22); -+ IRQ_HANDLE(23); -+ IRQ_HANDLE(24); -+ IRQ_HANDLE(25); -+ IRQ_HANDLE(26); -+ IRQ_HANDLE(27); ++ if ((s & 0x000000f0)) { ++ IRQ_HANDLE(4); ++ IRQ_HANDLE(5); ++ IRQ_HANDLE(6); ++ IRQ_HANDLE(7); ++ } ++ if ((s & 0x0000ff00)) { ++ IRQ_HANDLE(8); ++ IRQ_HANDLE(9); ++ IRQ_HANDLE(10); ++ IRQ_HANDLE(11); ++ IRQ_HANDLE(12); ++ IRQ_HANDLE(13); ++ IRQ_HANDLE(14); ++ IRQ_HANDLE(15); ++ } ++ if ((s & 0x00ff0000)) { ++ IRQ_HANDLE(16); ++ IRQ_HANDLE(17); ++ IRQ_HANDLE(18); ++ IRQ_HANDLE(19); ++ IRQ_HANDLE(20); ++ IRQ_HANDLE(21); ++ IRQ_HANDLE(22); ++ IRQ_HANDLE(23); ++ } ++ if ((s & 0xff000000)) { ++ IRQ_HANDLE(24); ++ IRQ_HANDLE(25); ++ IRQ_HANDLE(26); ++ IRQ_HANDLE(27); ++ IRQ_HANDLE(28); ++ IRQ_HANDLE(29); ++ IRQ_HANDLE(30); ++ IRQ_HANDLE(31); ++ } +} + ++#ifdef DDB_USE_MSI_IRQHANDLERS +static irqreturn_t irq_handler0(int irq, void *dev_id) - { -- struct ddb_i2c *i2c = &dev->i2c[n]; ++{ + struct ddb *dev = (struct ddb *) dev_id; + u32 s = ddbreadl(dev, INTERRUPT_STATUS); + + do { -+ if (s & 0x80000000) ++ if (s == 0xffffffff) + return IRQ_NONE; + if (!(s & 0xfff00)) + return IRQ_NONE; @@ -25962,62 +21678,20 @@ index 9e3492e..c2fc010 100644 + ddbwritel(dev, s, INTERRUPT_ACK); + irq_handle_msg(dev, s); + } while ((s = ddbreadl(dev, INTERRUPT_STATUS))); - -- i2c->done = 1; -- wake_up(&i2c->wq); ++ + return IRQ_HANDLED; - } - - static irqreturn_t irq_handler(int irq, void *dev_id) - { - struct ddb *dev = (struct ddb *) dev_id; -- u32 s = ddbreadl(INTERRUPT_STATUS); ++} ++#endif ++ ++static irqreturn_t irq_handler(int irq, void *dev_id) ++{ ++ struct ddb *dev = (struct ddb *) dev_id; + u32 s = ddbreadl(dev, INTERRUPT_STATUS); + int ret = IRQ_HANDLED; - - if (!s) - return IRQ_NONE; -- - do { -- ddbwritel(s, INTERRUPT_ACK); -- -- if (s & 0x00000001) -- irq_handle_i2c(dev, 0); -- if (s & 0x00000002) -- irq_handle_i2c(dev, 1); -- if (s & 0x00000004) -- irq_handle_i2c(dev, 2); -- if (s & 0x00000008) -- irq_handle_i2c(dev, 3); -- -- if (s & 0x00000100) -- tasklet_schedule(&dev->input[0].tasklet); -- if (s & 0x00000200) -- tasklet_schedule(&dev->input[1].tasklet); -- if (s & 0x00000400) -- tasklet_schedule(&dev->input[2].tasklet); -- if (s & 0x00000800) -- tasklet_schedule(&dev->input[3].tasklet); -- if (s & 0x00001000) -- tasklet_schedule(&dev->input[4].tasklet); -- if (s & 0x00002000) -- tasklet_schedule(&dev->input[5].tasklet); -- if (s & 0x00004000) -- tasklet_schedule(&dev->input[6].tasklet); -- if (s & 0x00008000) -- tasklet_schedule(&dev->input[7].tasklet); -- -- if (s & 0x00010000) -- tasklet_schedule(&dev->output[0].tasklet); -- if (s & 0x00020000) -- tasklet_schedule(&dev->output[1].tasklet); -- if (s & 0x00040000) -- tasklet_schedule(&dev->output[2].tasklet); -- if (s & 0x00080000) -- tasklet_schedule(&dev->output[3].tasklet); -- -- /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */ -- } while ((s = ddbreadl(INTERRUPT_STATUS))); ++ ++ if (!s) ++ return IRQ_NONE; ++ do { + if (s & 0x80000000) + return IRQ_NONE; + ddbwritel(dev, s, INTERRUPT_ACK); @@ -26027,7 +21701,7 @@ index 9e3492e..c2fc010 100644 + if (s & 0x0fffff00) { + irq_handle_io(dev, s); +#ifdef DDB_TEST_THREADED -+ ret = IRQ_WAKE_THREAD; ++ ret = IRQ_WAKE_THREAD; +#endif + } + } while ((s = ddbreadl(dev, INTERRUPT_STATUS))); @@ -26041,26 +21715,21 @@ index 9e3492e..c2fc010 100644 + /* struct ddb *dev = (struct ddb *) dev_id; */ + + /*pr_info("%s\n", __func__);*/ - - return IRQ_HANDLED; - } ++ ++ return IRQ_HANDLED; ++} +#endif + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ + -+#ifdef DVB_NSD -+ +static ssize_t nsd_read(struct file *file, char *buf, + size_t count, loff_t *ppos) +{ + return 0; +} - --/******************************************************************************/ --/******************************************************************************/ --/******************************************************************************/ ++ +static unsigned int nsd_poll(struct file *file, poll_table *wait) +{ + return 0; @@ -26076,6 +21745,22 @@ index 9e3492e..c2fc010 100644 + return dvb_generic_open(inode, file); +} + ++static struct ddb_input *plugtoinput(struct ddb *dev, u8 plug) ++{ ++ int i, j; ++ ++ for (i = j = 0; i < dev->port_num; i++) { ++ if (dev->port[i].class == DDB_PORT_TUNER) { ++ if (j == plug) ++ return dev->port[i].input[0]; ++ if (j + 1 == plug) ++ return dev->port[i].input[1]; ++ j += 2; ++ } ++ } ++ return 0; ++} ++ +static int nsd_do_ioctl(struct file *file, unsigned int cmd, void *parg) +{ + struct dvb_device *dvbdev = file->private_data; @@ -26088,15 +21773,19 @@ index 9e3492e..c2fc010 100644 + case NSD_START_GET_TS: + { + struct dvb_nsd_ts *ts = parg; -+ u32 ctrl = ((ts->input & 7) << 8) | -+ ((ts->filter_mask & 3) << 2); ++ struct ddb_input *input = plugtoinput(dev, ts->input); ++ u32 ctrl; + u32 to; + ++ if (!input) ++ return -EINVAL; ++ ctrl = (input->port->lnr << 16) | ((input->nr & 7) << 8) | ++ ((ts->filter_mask & 3) << 2); + if (ddbreadl(dev, TS_CAPTURE_CONTROL) & 1) { + pr_info("ts capture busy\n"); + return -EBUSY; + } -+ ddb_dvb_input_start(&dev->input[ts->input & 7]); ++ ddb_dvb_ns_input_start(input); + + ddbwritel(dev, ctrl, TS_CAPTURE_CONTROL); + ddbwritel(dev, ts->pid, TS_CAPTURE_PID); @@ -26140,7 +21829,8 @@ index 9e3492e..c2fc010 100644 + case NSD_CANCEL_GET_TS: + { + u32 ctrl = 0; -+ pr_info("cancel ts capture: 0x%x\n", ctrl); ++ ++ /*pr_info("cancel ts capture: 0x%x\n", ctrl);*/ + ddbwritel(dev, ctrl, TS_CAPTURE_CONTROL); + ctrl = ddbreadl(dev, TS_CAPTURE_CONTROL); + /*pr_info("control register is 0x%x\n", ctrl);*/ @@ -26149,14 +21839,17 @@ index 9e3492e..c2fc010 100644 + case NSD_STOP_GET_TS: + { + struct dvb_nsd_ts *ts = parg; ++ struct ddb_input *input = plugtoinput(dev, ts->input); + u32 ctrl = ddbreadl(dev, TS_CAPTURE_CONTROL); + ++ if (!input) ++ return -EINVAL; + if (ctrl & 1) { + pr_info("cannot stop ts capture, while it was neither finished not canceled\n"); + return -EBUSY; + } + /*pr_info("ts capture stopped\n");*/ -+ ddb_dvb_input_stop(&dev->input[ts->input & 7]); ++ ddb_dvb_ns_input_stop(input); + break; + } + default: @@ -26193,15 +21886,20 @@ index 9e3492e..c2fc010 100644 +{ + int ret; + ++ if (!dev->link[0].info->ns_num) ++ return 0; + ret = dvb_register_device(&dev->adap[0], + &dev->nsd_dev, + &dvbdev_nsd, (void *) dev, -+ DVB_DEVICE_NSD); ++ DVB_DEVICE_NSD, 0); + return ret; +} + +static void ddb_nsd_detach(struct ddb *dev) +{ ++ if (!dev->link[0].info->ns_num) ++ return; ++ + if (dev->nsd_dev->users > 2) { + wait_event(dev->nsd_dev->wait_queue, + dev->nsd_dev->users == 2); @@ -26209,98 +21907,111 @@ index 9e3492e..c2fc010 100644 + dvb_unregister_device(dev->nsd_dev); +} + -+#endif + +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ - - static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) - { - u32 data, shift; - - if (wlen > 4) -- ddbwritel(1, SPI_CONTROL); -+ ddbwritel(dev, 1, SPI_CONTROL); - while (wlen > 4) { - /* FIXME: check for big-endian */ - data = swab32(*(u32 *)wbuf); - wbuf += 4; - wlen -= 4; -- ddbwritel(data, SPI_DATA); -- while (ddbreadl(SPI_CONTROL) & 0x0004) -+ ddbwritel(dev, data, SPI_DATA); -+ while (ddbreadl(dev, SPI_CONTROL) & 0x0004) - ; - } - - if (rlen) -- ddbwritel(0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); ++ ++static int reg_wait(struct ddb *dev, u32 reg, u32 bit) ++{ ++ u32 count = 0; ++ ++ while (ddbreadl(dev, reg) & bit) { ++ ndelay(10); ++ if (++count == 100) ++ return -1; ++ } ++ return 0; ++} ++ ++static int flashio(struct ddb *dev, u32 lnr, u8 *wbuf, u32 wlen, u8 *rbuf, ++ u32 rlen) ++{ ++ u32 data, shift; ++ u32 tag = DDB_LINK_TAG(lnr); ++ struct ddb_link *link = &dev->link[lnr]; ++ ++ mutex_lock(&link->flash_mutex); ++ if (wlen > 4) ++ ddbwritel(dev, 1, tag | SPI_CONTROL); ++ while (wlen > 4) { ++ /* FIXME: check for big-endian */ ++ data = swab32(*(u32 *) wbuf); ++ wbuf += 4; ++ wlen -= 4; ++ ddbwritel(dev, data, tag | SPI_DATA); ++ if (reg_wait(dev, tag | SPI_CONTROL, 4)) ++ goto fail; ++ } ++ if (rlen) + ddbwritel(dev, 0x0001 | ((wlen << (8 + 3)) & 0x1f00), -+ SPI_CONTROL); - else -- ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); ++ tag | SPI_CONTROL); ++ else + ddbwritel(dev, 0x0003 | ((wlen << (8 + 3)) & 0x1f00), -+ SPI_CONTROL); - - data = 0; - shift = ((4 - wlen) * 8); -@@ -1367,33 +2907,33 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) - } - if (shift) - data <<= shift; -- ddbwritel(data, SPI_DATA); -- while (ddbreadl(SPI_CONTROL) & 0x0004) -+ ddbwritel(dev, data, SPI_DATA); -+ while (ddbreadl(dev, SPI_CONTROL) & 0x0004) - ; - - if (!rlen) { -- ddbwritel(0, SPI_CONTROL); -+ ddbwritel(dev, 0, SPI_CONTROL); - return 0; - } - if (rlen > 4) -- ddbwritel(1, SPI_CONTROL); -+ ddbwritel(dev, 1, SPI_CONTROL); - - while (rlen > 4) { -- ddbwritel(0xffffffff, SPI_DATA); -- while (ddbreadl(SPI_CONTROL) & 0x0004) -+ ddbwritel(dev, 0xffffffff, SPI_DATA); -+ while (ddbreadl(dev, SPI_CONTROL) & 0x0004) - ; -- data = ddbreadl(SPI_DATA); -+ data = ddbreadl(dev, SPI_DATA); - *(u32 *) rbuf = swab32(data); - rbuf += 4; - rlen -= 4; - } -- ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL); -- ddbwritel(0xffffffff, SPI_DATA); -- while (ddbreadl(SPI_CONTROL) & 0x0004) -+ ddbwritel(dev, 0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL); -+ ddbwritel(dev, 0xffffffff, SPI_DATA); -+ while (ddbreadl(dev, SPI_CONTROL) & 0x0004) - ; - -- data = ddbreadl(SPI_DATA); -- ddbwritel(0, SPI_CONTROL); -+ data = ddbreadl(dev, SPI_DATA); -+ ddbwritel(dev, 0, SPI_CONTROL); - - if (rlen < 4) - data <<= ((4 - rlen) * 8); -@@ -1407,28 +2947,107 @@ static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) - return 0; - } - -+int ddbridge_flashread(struct ddb *dev, u8 *buf, u32 addr, u32 len) ++ tag | SPI_CONTROL); ++ ++ data = 0; ++ shift = ((4 - wlen) * 8); ++ while (wlen) { ++ data <<= 8; ++ data |= *wbuf; ++ wlen--; ++ wbuf++; ++ } ++ if (shift) ++ data <<= shift; ++ ddbwritel(dev, data, tag | SPI_DATA); ++ if (reg_wait(dev, tag | SPI_CONTROL, 4)) ++ goto fail; ++ ++ if (!rlen) { ++ ddbwritel(dev, 0, tag | SPI_CONTROL); ++ goto exit; ++ } ++ if (rlen > 4) ++ ddbwritel(dev, 1, tag | SPI_CONTROL); ++ ++ while (rlen > 4) { ++ ddbwritel(dev, 0xffffffff, tag | SPI_DATA); ++ if (reg_wait(dev, tag | SPI_CONTROL, 4)) ++ goto fail; ++ data = ddbreadl(dev, tag | SPI_DATA); ++ *(u32 *) rbuf = swab32(data); ++ rbuf += 4; ++ rlen -= 4; ++ } ++ ddbwritel(dev, 0x0003 | ((rlen << (8 + 3)) & 0x1F00), ++ tag | SPI_CONTROL); ++ ddbwritel(dev, 0xffffffff, tag | SPI_DATA); ++ if (reg_wait(dev, tag | SPI_CONTROL, 4)) ++ goto fail; ++ ++ data = ddbreadl(dev, tag | SPI_DATA); ++ ddbwritel(dev, 0, tag | SPI_CONTROL); ++ ++ if (rlen < 4) ++ data <<= ((4 - rlen) * 8); ++ ++ while (rlen > 0) { ++ *rbuf = ((data >> 24) & 0xff); ++ data <<= 8; ++ rbuf++; ++ rlen--; ++ } ++exit: ++ mutex_unlock(&link->flash_mutex); ++ return 0; ++fail: ++ mutex_unlock(&link->flash_mutex); ++ return -1; ++} ++ ++int ddbridge_flashread(struct ddb *dev, u32 link, u8 *buf, u32 addr, u32 len) +{ + u8 cmd[4] = {0x03, (addr >> 16) & 0xff, + (addr >> 8) & 0xff, addr & 0xff}; + -+ return flashio(dev, cmd, 4, buf, len); ++ return flashio(dev, link, cmd, 4, buf, len); +} + +static int mdio_write(struct ddb *dev, u8 adr, u8 reg, u16 val) @@ -26324,18 +22035,16 @@ index 9e3492e..c2fc010 100644 + return ddbreadl(dev, MDIO_VAL); +} + - #define DDB_MAGIC 'd' - - struct ddb_flashio { -- __user __u8 *write_buf; ++#define DDB_MAGIC 'd' ++ ++struct ddb_flashio { + __u8 *write_buf; - __u32 write_len; -- __user __u8 *read_buf; ++ __u32 write_len; + __u8 *read_buf; - __u32 read_len; - }; - --#define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio) ++ __u32 read_len; ++ __u32 link; ++}; ++ +struct ddb_gpio { + __u32 mask; + __u32 data; @@ -26367,6 +22076,15 @@ index 9e3492e..c2fc010 100644 + __u16 val; +}; + ++struct ddb_i2c_msg { ++ __u8 bus; ++ __u8 adr; ++ __u8 *hdr; ++ __u32 hlen; ++ __u8 *msg; ++ __u32 mlen; ++}; ++ +#define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio) +#define IOCTL_DDB_GPIO_IN _IOWR(DDB_MAGIC, 0x01, struct ddb_gpio) +#define IOCTL_DDB_GPIO_OUT _IOWR(DDB_MAGIC, 0x02, struct ddb_gpio) @@ -26377,13 +22095,13 @@ index 9e3492e..c2fc010 100644 +#define IOCTL_DDB_WRITE_MEM _IOR(DDB_MAGIC, 0x07, struct ddb_mem) +#define IOCTL_DDB_READ_MDIO _IOWR(DDB_MAGIC, 0x08, struct ddb_mdio) +#define IOCTL_DDB_WRITE_MDIO _IOR(DDB_MAGIC, 0x09, struct ddb_mdio) - - #define DDB_NAME "ddbridge" - - static u32 ddb_num; --static struct ddb *ddbs[32]; --static struct class *ddb_class; - static int ddb_major; ++#define IOCTL_DDB_READ_I2C _IOWR(DDB_MAGIC, 0x0a, struct ddb_i2c_msg) ++#define IOCTL_DDB_WRITE_I2C _IOR(DDB_MAGIC, 0x0b, struct ddb_i2c_msg) ++ ++#define DDB_NAME "ddbridge" ++ ++static u32 ddb_num; ++static int ddb_major; +static DEFINE_MUTEX(ddb_mutex); + +static int ddb_release(struct inode *inode, struct file *file) @@ -26393,41 +22111,56 @@ index 9e3492e..c2fc010 100644 + dev->ddb_dev_users--; + return 0; +} - - static int ddb_open(struct inode *inode, struct file *file) - { - struct ddb *dev = ddbs[iminor(inode)]; - ++ ++static int ddb_open(struct inode *inode, struct file *file) ++{ ++ struct ddb *dev = ddbs[iminor(inode)]; ++ + if (dev->ddb_dev_users) + return -EBUSY; + dev->ddb_dev_users++; - file->private_data = dev; - return 0; - } -@@ -1436,7 +3055,7 @@ static int ddb_open(struct inode *inode, struct file *file) - static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) - { - struct ddb *dev = file->private_data; -- __user void *parg = (__user void *)arg; ++ file->private_data = dev; ++ return 0; ++} ++ ++static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ struct ddb *dev = file->private_data; + void *parg = (void *)arg; - int res; - - switch (cmd) { -@@ -1447,7 +3066,6 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) - - if (copy_from_user(&fio, parg, sizeof(fio))) - return -EFAULT; -- - if (fio.write_len > 1028 || fio.read_len > 1028) - return -EINVAL; - if (fio.write_len + fio.read_len > 1028) -@@ -1465,6 +3083,107 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) - return -EFAULT; - break; - } ++ int res; ++ ++ switch (cmd) { ++ case IOCTL_DDB_FLASHIO: ++ { ++ struct ddb_flashio fio; ++ u8 *rbuf, *wbuf; ++ ++ if (copy_from_user(&fio, parg, sizeof(fio))) ++ return -EFAULT; ++ if (fio.write_len > 1028 || fio.read_len > 1028) ++ return -EINVAL; ++ if (fio.write_len + fio.read_len > 1028) ++ return -EINVAL; ++ if (fio.link > 3) ++ return -EINVAL; ++ ++ wbuf = &dev->iobuf[0]; ++ rbuf = wbuf + fio.write_len; ++ ++ if (copy_from_user(wbuf, fio.write_buf, fio.write_len)) ++ return -EFAULT; ++ res = flashio(dev, fio.link, wbuf, fio.write_len, rbuf, ++ fio.read_len); ++ if (res) ++ return res; ++ if (copy_to_user(fio.read_buf, rbuf, fio.read_len)) ++ return -EFAULT; ++ break; ++ } + case IOCTL_DDB_GPIO_OUT: + { + struct ddb_gpio gpio; ++ + if (copy_from_user(&gpio, parg, sizeof(gpio))) + return -EFAULT; + ddbwritel(dev, gpio.mask, GPIO_DIRECTION); @@ -26438,10 +22171,10 @@ index 9e3492e..c2fc010 100644 + { + struct ddb_id ddbid; + -+ ddbid.vendor = dev->ids.vendor; -+ ddbid.device = dev->ids.device; -+ ddbid.subvendor = dev->ids.subvendor; -+ ddbid.subdevice = dev->ids.subdevice; ++ ddbid.vendor = dev->link[0].ids.vendor; ++ ddbid.device = dev->link[0].ids.device; ++ ddbid.subvendor = dev->link[0].ids.subvendor; ++ ddbid.subdevice = dev->link[0].ids.subdevice; + ddbid.hw = ddbreadl(dev, 0); + ddbid.regmap = ddbreadl(dev, 4); + if (copy_to_user(parg, &ddbid, sizeof(ddbid))) @@ -26454,7 +22187,7 @@ index 9e3492e..c2fc010 100644 + + if (copy_from_user(®, parg, sizeof(reg))) + return -EFAULT; -+ if (reg.reg >= dev->regs_len) ++ if ((reg.reg & 0xfffffff) >= dev->regs_len) + return -EINVAL; + reg.val = ddbreadl(dev, reg.reg); + if (copy_to_user(parg, ®, sizeof(reg))) @@ -26467,7 +22200,7 @@ index 9e3492e..c2fc010 100644 + + if (copy_from_user(®, parg, sizeof(reg))) + return -EFAULT; -+ if (reg.reg >= dev->regs_len) ++ if ((reg.reg & 0xfffffff) >= dev->regs_len) + return -EINVAL; + ddbwritel(dev, reg.val, reg.reg); + break; @@ -26476,7 +22209,7 @@ index 9e3492e..c2fc010 100644 + { + struct ddb_mdio mdio; + -+ if (!dev->info->mdio_num) ++ if (!dev->link[0].info->mdio_num) + return -EIO; + if (copy_from_user(&mdio, parg, sizeof(mdio))) + return -EFAULT; @@ -26489,7 +22222,7 @@ index 9e3492e..c2fc010 100644 + { + struct ddb_mdio mdio; + -+ if (!dev->info->mdio_num) ++ if (!dev->link[0].info->mdio_num) + return -EIO; + if (copy_from_user(&mdio, parg, sizeof(mdio))) + return -EFAULT; @@ -26503,7 +22236,7 @@ index 9e3492e..c2fc010 100644 + + if (copy_from_user(&mem, parg, sizeof(mem))) + return -EFAULT; -+ if ((mem.len + mem.off > dev->regs_len) || ++ if ((((mem.len + mem.off) & 0xfffffff) > dev->regs_len) || + mem.len > 1024) + return -EINVAL; + ddbcpyfrom(dev, buf, mem.off, mem.len); @@ -26518,154 +22251,326 @@ index 9e3492e..c2fc010 100644 + + if (copy_from_user(&mem, parg, sizeof(mem))) + return -EFAULT; -+ if ((mem.len + mem.off > dev->regs_len) || ++ if ((((mem.len + mem.off) & 0xfffffff) > dev->regs_len) || + mem.len > 1024) + return -EINVAL; + if (copy_from_user(buf, mem.buf, mem.len)) + return -EFAULT; + ddbcpyto(dev, mem.off, buf, mem.len); -+ break; -+ } - default: - return -ENOTTY; + break; } -@@ -1474,284 +3193,508 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) - static const struct file_operations ddb_fops = { - .unlocked_ioctl = ddb_ioctl, - .open = ddb_open, -+ .release = ddb_release, - }; +- input->attached = 5; +- return 0; +-} ++ case IOCTL_DDB_READ_I2C: ++ { ++ struct ddb_i2c_msg i2c; ++ struct i2c_adapter *adap; ++ u8 *mbuf, *hbuf = &dev->iobuf[0]; -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) -+static char *ddb_devnode(struct device *device, mode_t *mode) -+#else - static char *ddb_devnode(struct device *device, umode_t *mode) -+#endif - { - struct ddb *dev = dev_get_drvdata(device); +-/****************************************************************************/ +-/****************************************************************************/ ++ if (copy_from_user(&i2c, parg, sizeof(i2c))) ++ return -EFAULT; ++ if (i2c.bus > dev->link[0].info->regmap->i2c->num) ++ return -EINVAL; ++ if (i2c.mlen + i2c.hlen > 512) ++ return -EINVAL; - return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr); +-static ssize_t ts_write(struct file *file, const __user char *buf, +- size_t count, loff_t *ppos) +-{ +- struct dvb_device *dvbdev = file->private_data; +- struct ddb_output *output = dvbdev->priv; +- size_t left = count; +- int stat; ++ adap = &dev->i2c[i2c.bus].adap; ++ mbuf = hbuf + i2c.hlen; + +- while (left) { +- if (ddb_output_free(output) < 188) { +- if (file->f_flags & O_NONBLOCK) +- break; +- if (wait_event_interruptible( +- output->wq, ddb_output_free(output) >= 188) < 0) +- break; +- } +- stat = ddb_output_write(output, buf, left); +- if (stat < 0) +- break; +- buf += stat; +- left -= stat; ++ ++ if (copy_from_user(hbuf, i2c.hdr, i2c.hlen)) ++ return -EFAULT; ++ if (i2c_io(adap, i2c.adr, hbuf, i2c.hlen, mbuf, i2c.mlen) < 0) ++ return -EIO; ++ if (copy_to_user(i2c.msg, mbuf, i2c.mlen)) ++ return -EFAULT; ++ break; + } +- return (left == count) ? -EAGAIN : (count - left); +-} ++ case IOCTL_DDB_WRITE_I2C: ++ { ++ struct ddb_i2c_msg i2c; ++ struct i2c_adapter *adap; ++ u8 *buf = &dev->iobuf[0]; + +-static ssize_t ts_read(struct file *file, __user char *buf, +- size_t count, loff_t *ppos) +-{ +- struct dvb_device *dvbdev = file->private_data; +- struct ddb_output *output = dvbdev->priv; +- struct ddb_input *input = output->port->input[0]; +- int left, read; ++ if (copy_from_user(&i2c, parg, sizeof(i2c))) ++ return -EFAULT; ++ if (i2c.bus > dev->link[0].info->regmap->i2c->num) ++ return -EINVAL; ++ if (i2c.mlen + i2c.hlen > 250) ++ return -EINVAL; + +- count -= count % 188; +- left = count; +- while (left) { +- if (ddb_input_avail(input) < 188) { +- if (file->f_flags & O_NONBLOCK) +- break; +- if (wait_event_interruptible( +- input->wq, ddb_input_avail(input) >= 188) < 0) +- break; +- } +- read = ddb_input_read(input, buf, left); +- if (read < 0) +- return read; +- left -= read; +- buf += read; ++ adap = &dev->i2c[i2c.bus].adap; ++ if (copy_from_user(buf, i2c.hdr, i2c.hlen)) ++ return -EFAULT; ++ if (copy_from_user(buf + i2c.hlen, i2c.msg, i2c.mlen)) ++ return -EFAULT; ++ if (i2c_write(adap, i2c.adr, buf, i2c.hlen + i2c.mlen) < 0) ++ return -EIO; ++ break; + } +- return (left == count) ? -EAGAIN : (count - left); ++ default: ++ return -ENOTTY; ++ } ++ return 0; } --static int ddb_class_create(void) +-static unsigned int ts_poll(struct file *file, poll_table *wait) -{ -- ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops); -- if (ddb_major < 0) -- return ddb_major; +- /* +- struct dvb_device *dvbdev = file->private_data; +- struct ddb_output *output = dvbdev->priv; +- struct ddb_input *input = output->port->input[0]; +- */ +- unsigned int mask = 0; ++static const struct file_operations ddb_fops = { ++ .unlocked_ioctl = ddb_ioctl, ++ .open = ddb_open, ++ .release = ddb_release, ++}; + +-#if 0 +- if (data_avail_to_read) +- mask |= POLLIN | POLLRDNORM; +- if (data_avail_to_write) +- mask |= POLLOUT | POLLWRNORM; ++static char *ddb_devnode(struct device *device, umode_t *mode) ++{ ++ struct ddb *dev = dev_get_drvdata(device); + +- poll_wait(file, &read_queue, wait); +- poll_wait(file, &write_queue, wait); +-#endif +- return mask; ++ return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr); + } + +-static const struct file_operations ci_fops = { +- .owner = THIS_MODULE, +- .read = ts_read, +- .write = ts_write, +- .open = dvb_generic_open, +- .release = dvb_generic_release, +- .poll = ts_poll, +-}; +- +-static struct dvb_device dvbdev_ci = { +- .readers = -1, +- .writers = -1, +- .users = -1, +- .fops = &ci_fops, +-}; +#define __ATTR_MRO(_name, _show) { \ + .attr = { .name = __stringify(_name), .mode = 0444 }, \ + .show = _show, \ +} -- ddb_class = class_create(THIS_MODULE, DDB_NAME); -- if (IS_ERR(ddb_class)) { -- unregister_chrdev(ddb_major, DDB_NAME); -- return PTR_ERR(ddb_class); -- } -- ddb_class->devnode = ddb_devnode; -- return 0; +-/****************************************************************************/ +-/****************************************************************************/ +-/****************************************************************************/ +#define __ATTR_MWO(_name, _store) { \ + .attr = { .name = __stringify(_name), .mode = 0222 }, \ + .store = _store, \ - } ++} --static void ddb_class_destroy(void) +-static void input_tasklet(unsigned long data) +static ssize_t ports_show(struct device *device, + struct device_attribute *attr, char *buf) { -- class_destroy(ddb_class); -- unregister_chrdev(ddb_major, DDB_NAME); +- struct ddb_input *input = (struct ddb_input *) data; +- struct ddb *dev = input->port->dev; + struct ddb *dev = dev_get_drvdata(device); -+ -+ return sprintf(buf, "%d\n", dev->info->port_num); - } --static int ddb_device_create(struct ddb *dev) +- spin_lock(&input->lock); +- if (!input->running) { +- spin_unlock(&input->lock); +- return; +- } +- input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); ++ return sprintf(buf, "%d\n", dev->link[0].info->port_num); ++} + +- if (input->port->class == DDB_PORT_TUNER) { +- if (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr))) +- printk(KERN_ERR "Overflow input %d\n", input->nr); +- while (input->cbuf != ((input->stat >> 11) & 0x1f) +- || (4&ddbreadl(DMA_BUFFER_CONTROL(input->nr)))) { +- dvb_dmx_swfilter_packets(&input->demux, +- input->vbuf[input->cbuf], +- input->dma_buf_size / 188); +static ssize_t ts_irq_show(struct device *device, + struct device_attribute *attr, char *buf) - { -- dev->nr = ddb_num++; -- dev->ddb_dev = device_create(ddb_class, NULL, -- MKDEV(ddb_major, dev->nr), -- dev, "ddbridge%d", dev->nr); -- ddbs[dev->nr] = dev; -- if (IS_ERR(dev->ddb_dev)) -- return -1; -- return 0; ++{ + struct ddb *dev = dev_get_drvdata(device); -+ + +- input->cbuf = (input->cbuf + 1) % input->dma_buf_num; +- ddbwritel((input->cbuf << 11), +- DMA_BUFFER_ACK(input->nr)); +- input->stat = ddbreadl(DMA_BUFFER_CURRENT(input->nr)); +- } +- } +- if (input->port->class == DDB_PORT_CI) +- wake_up(&input->wq); +- spin_unlock(&input->lock); + return sprintf(buf, "%d\n", dev->ts_irq); } --static void ddb_device_destroy(struct ddb *dev) +-static void output_tasklet(unsigned long data) +static ssize_t i2c_irq_show(struct device *device, + struct device_attribute *attr, char *buf) { -- ddb_num--; -- if (IS_ERR(dev->ddb_dev)) -- return; -- device_destroy(ddb_class, MKDEV(ddb_major, 0)); +- struct ddb_output *output = (struct ddb_output *) data; +- struct ddb *dev = output->port->dev; + struct ddb *dev = dev_get_drvdata(device); -+ + +- spin_lock(&output->lock); +- if (!output->running) { +- spin_unlock(&output->lock); +- return; +- } +- output->stat = ddbreadl(DMA_BUFFER_CURRENT(output->nr + 8)); +- wake_up(&output->wq); +- spin_unlock(&output->lock); + return sprintf(buf, "%d\n", dev->i2c_irq); } +- +-static struct cxd2099_cfg cxd_cfg = { +- .bitrate = 62000, +- .adr = 0x40, +- .polarity = 1, +- .clock_mode = 1, +static char *class_name[] = { -+ "NONE", "CI", "TUNER", "LOOP" -+}; ++ "NONE", "CI", "TUNER", "LOOP", "MOD" + }; --/****************************************************************************/ --/****************************************************************************/ --/****************************************************************************/ -+static char *type_name[] = { -+ "NONE", "DVBS_ST", "DVBS_ST_AA", "DVBCT_TR", -+ "DVBCT_ST", "INTERNAL", "CXD2099", "TYPE07", -+ "TYPE08", "TYPE09", "TYPE0A", "TYPE0B", -+ "TYPE0C", "TYPE0D", "TYPE0E", "TYPE0F", -+ "DVBS", "DVBCT2_SONY", "ISDBT_SONY", "DVBC2T2_SONY", -+ "ATSC_ST", "DVBC2T2_ST" -+}; - --static void ddb_unmap(struct ddb *dev) +-static int ddb_ci_attach(struct ddb_port *port) +static ssize_t fan_show(struct device *device, + struct device_attribute *attr, char *buf) { -- if (dev->regs) -- iounmap(dev->regs); -- vfree(dev); +- int ret; + struct ddb *dev = dev_get_drvdata(device); + u32 val; -+ + +- ret = dvb_register_adapter(&port->output->adap, +- "DDBridge", +- THIS_MODULE, +- &port->dev->pdev->dev, +- adapter_nr); +- if (ret < 0) +- return ret; +- port->en = cxd2099_attach(&cxd_cfg, port, &port->i2c->adap); +- if (!port->en) { +- dvb_unregister_adapter(&port->output->adap); +- return -ENODEV; +- } +- ddb_input_start(port->input[0]); +- ddb_output_start(port->output); +- dvb_ca_en50221_init(&port->output->adap, +- port->en, 0, 1); +- ret = dvb_register_device(&port->output->adap, &port->output->dev, +- &dvbdev_ci, (void *) port->output, +- DVB_DEVICE_SEC, 0); +- return ret; + val = ddbreadl(dev, GPIO_OUTPUT) & 1; + return sprintf(buf, "%d\n", val); } +-static int ddb_port_attach(struct ddb_port *port) +static ssize_t fan_store(struct device *device, struct device_attribute *d, + const char *buf, size_t count) -+{ + { +- int ret = 0; + struct ddb *dev = dev_get_drvdata(device); + unsigned val; -+ + +- switch (port->class) { +- case DDB_PORT_TUNER: +- ret = dvb_input_attach(port->input[0]); +- if (ret < 0) +- break; +- ret = dvb_input_attach(port->input[1]); +- break; +- case DDB_PORT_CI: +- ret = ddb_ci_attach(port); +- break; +- default: +- break; +- } +- if (ret < 0) +- printk(KERN_ERR "port_attach on port %d failed\n", port->nr); +- return ret; + if (sscanf(buf, "%u\n", &val) != 1) + return -EINVAL; + ddbwritel(dev, 1, GPIO_DIRECTION); + ddbwritel(dev, val & 1, GPIO_OUTPUT); + return count; -+} + } --static void ddb_remove(struct pci_dev *pdev) +-static int ddb_ports_attach(struct ddb *dev) +static ssize_t temp_show(struct device *device, + struct device_attribute *attr, char *buf) { -- struct ddb *dev = pci_get_drvdata(pdev); +- int i, ret = 0; +- struct ddb_port *port; + struct ddb *dev = dev_get_drvdata(device); + struct i2c_adapter *adap; + int temp, temp2, temp3, i; + u8 tmp[2]; -- ddb_ports_detach(dev); -- ddb_i2c_release(dev); -+ if (dev->info->type == DDB_MOD) { +- for (i = 0; i < dev->info->port_num; i++) { +- port = &dev->port[i]; +- ret = ddb_port_attach(port); +- if (ret < 0) +- break; ++ if (dev->link[0].info->type == DDB_MOD) { + ddbwritel(dev, 1, TEMPMON_CONTROL); + for (i = 0; i < 10; i++) { + if (0 == (1 & ddbreadl(dev, TEMPMON_CONTROL))) @@ -26682,15 +22587,16 @@ index 9e3492e..c2fc010 100644 + return sprintf(buf, "%d %d %d\n", temp, temp2, temp3); + } + return sprintf(buf, "%d %d\n", temp, temp2); -+ } -+ if (!dev->info->temp_num) + } +- return ret; ++ if (!dev->link[0].info->temp_num) + return sprintf(buf, "no sensor\n"); -+ adap = &dev->i2c[dev->info->temp_bus].adap; ++ adap = &dev->i2c[dev->link[0].info->temp_bus].adap; + if (i2c_read_regs(adap, 0x48, 0, tmp, 2) < 0) + return sprintf(buf, "read_error\n"); + temp = (tmp[0] << 3) | (tmp[1] >> 5); + temp *= 125; -+ if (dev->info->temp_num == 2) { ++ if (dev->link[0].info->temp_num == 2) { + if (i2c_read_regs(adap, 0x49, 0, tmp, 2) < 0) + return sprintf(buf, "read_error\n"); + temp2 = (tmp[0] << 3) | (tmp[1] >> 5); @@ -26698,77 +22604,90 @@ index 9e3492e..c2fc010 100644 + return sprintf(buf, "%d %d\n", temp, temp2); + } + return sprintf(buf, "%d\n", temp); -+} + } -- ddbwritel(0, INTERRUPT_ENABLE); -- free_irq(dev->pdev->irq, dev); --#ifdef CONFIG_PCI_MSI -- if (dev->msi) -- pci_disable_msi(dev->pdev); --#endif -- ddb_ports_release(dev); -- ddb_buffers_free(dev); -- ddb_device_destroy(dev); -+#if 0 -+static ssize_t qam_show(struct device *device, -+ struct device_attribute *attr, char *buf) -+{ +-static void ddb_ports_detach(struct ddb *dev) ++static ssize_t ctemp_show(struct device *device, ++ struct device_attribute *attr, char *buf) + { +- int i; +- struct ddb_port *port; + struct ddb *dev = dev_get_drvdata(device); + struct i2c_adapter *adap; -+ u8 tmp[4]; -+ s16 i, q; ++ int temp; ++ u8 tmp[2]; ++ int num = attr->attr.name[4] - 0x30; -- ddb_unmap(dev); -- pci_set_drvdata(pdev, NULL); -- pci_disable_device(pdev); -+ adap = &dev->i2c[1].adap; -+ if (i2c_read_regs16(adap, 0x1f, 0xf480, tmp, 4) < 0) -+ return sprintf(buf, "read_error\n"); -+ i = (s16) (((u16) tmp[1]) << 14) | (((u16) tmp[0]) << 6); -+ q = (s16) (((u16) tmp[3]) << 14) | (((u16) tmp[2]) << 6); -+ -+ return sprintf(buf, "%d %d\n", i, q); +- for (i = 0; i < dev->info->port_num; i++) { +- port = &dev->port[i]; +- switch (port->class) { +- case DDB_PORT_TUNER: +- dvb_input_detach(port->input[0]); +- dvb_input_detach(port->input[1]); +- break; +- case DDB_PORT_CI: +- dvb_unregister_device(port->output->dev); +- if (port->en) { +- ddb_input_stop(port->input[0]); +- ddb_output_stop(port->output); +- dvb_ca_en50221_release(port->en); +- kfree(port->en); +- port->en = NULL; +- dvb_unregister_adapter(&port->output->adap); +- } +- break; +- } +- } ++ adap = &dev->i2c[num].adap; ++ if (!adap) ++ return 0; ++ if (i2c_read_regs(adap, 0x49, 0, tmp, 2) < 0) ++ if (i2c_read_regs(adap, 0x4d, 0, tmp, 2) < 0) ++ return sprintf(buf, "no sensor\n"); ++ temp = tmp[0] * 1000; ++ return sprintf(buf, "%d\n", temp); } -+#endif -+ + +-/****************************************************************************/ +-/****************************************************************************/ +- +-static int port_has_ci(struct ddb_port *port) +static ssize_t mod_show(struct device *device, + struct device_attribute *attr, char *buf) -+{ + { +- u8 val; +- return i2c_read_reg(&port->i2c->adap, 0x40, 0, &val) ? 0 : 1; + struct ddb *dev = dev_get_drvdata(device); + int num = attr->attr.name[3] - 0x30; - ++ + return sprintf(buf, "%s:%s\n", + class_name[dev->port[num].class], -+ type_name[dev->port[num].type]); -+} ++ dev->port[num].type_name); + } --static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id) +-static int port_has_stv0900(struct ddb_port *port) +static ssize_t led_show(struct device *device, + struct device_attribute *attr, char *buf) { -- struct ddb *dev; -- int stat = 0; -- int irq_flag = IRQF_SHARED; +- u8 val; +- if (i2c_read_reg16(&port->i2c->adap, 0x69, 0xf100, &val) < 0) +- return 0; +- return 1; + struct ddb *dev = dev_get_drvdata(device); + int num = attr->attr.name[3] - 0x30; - -- if (pci_enable_device(pdev) < 0) -- return -ENODEV; ++ + return sprintf(buf, "%d\n", dev->leds & (1 << num) ? 1 : 0); -+} + } -- dev = vmalloc(sizeof(struct ddb)); -- if (dev == NULL) -- return -ENOMEM; -- memset(dev, 0, sizeof(struct ddb)); - -- dev->pdev = pdev; -- pci_set_drvdata(pdev, dev); -- dev->info = (struct ddb_info *) id->driver_data; -- printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name); +-static int port_has_stv0900_aa(struct ddb_port *port) ++ +static void ddb_set_led(struct ddb *dev, int num, int val) -+{ -+ if (!dev->info->led_num) + { +- u8 val; +- if (i2c_read_reg16(&port->i2c->adap, 0x68, 0xf100, &val) < 0) +- return 0; +- return 1; ++ if (!dev->link[0].info->led_num) + return; + switch (dev->port[num].class) { + case DDB_PORT_TUNER: @@ -26786,12 +22705,7 @@ index 9e3492e..c2fc010 100644 + case DDB_TUNER_XO2 ... DDB_TUNER_DVBC2T2_ST: + { + u8 v; - -- dev->regs = ioremap(pci_resource_start(dev->pdev, 0), -- pci_resource_len(dev->pdev, 0)); -- if (!dev->regs) { -- stat = -ENOMEM; -- goto fail; ++ + i2c_read_reg(&dev->i2c[num].adap, 0x10, 0x08, &v); + v = (v & ~0x10) | (val ? 0x10 : 0); + i2c_write_reg(&dev->i2c[num].adap, 0x10, 0x08, v); @@ -26801,14 +22715,20 @@ index 9e3492e..c2fc010 100644 + break; + } + break; - } -- printk(KERN_INFO "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4)); -+} -+ ++ } + } + +-static int port_has_drxks(struct ddb_port *port) +static ssize_t led_store(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) -+{ + { +- u8 val; +- if (i2c_read(&port->i2c->adap, 0x29, &val) < 0) +- return 0; +- if (i2c_read(&port->i2c->adap, 0x2a, &val) < 0) +- return 0; +- return 1; + struct ddb *dev = dev_get_drvdata(device); + int num = attr->attr.name[3] - 0x30; + unsigned val; @@ -26821,35 +22741,757 @@ index 9e3492e..c2fc010 100644 + dev->leds &= ~(1 << num); + ddb_set_led(dev, num, val); + return count; -+} -+ + } + +-static void ddb_port_probe(struct ddb_port *port) +static ssize_t snr_show(struct device *device, + struct device_attribute *attr, char *buf) -+{ + { +- struct ddb *dev = port->dev; +- char *modname = "NO MODULE"; +- +- port->class = DDB_PORT_NONE; + struct ddb *dev = dev_get_drvdata(device); + char snr[32]; + int num = attr->attr.name[3] - 0x30; +- if (port_has_ci(port)) { +- modname = "CI"; +- port->class = DDB_PORT_CI; +- ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); +- } else if (port_has_stv0900(port)) { +- modname = "DUAL DVB-S2"; +- port->class = DDB_PORT_TUNER; +- port->type = DDB_TUNER_DVBS_ST; +- ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); +- } else if (port_has_stv0900_aa(port)) { +- modname = "DUAL DVB-S2"; +- port->class = DDB_PORT_TUNER; +- port->type = DDB_TUNER_DVBS_ST_AA; +- ddbwritel(I2C_SPEED_100, port->i2c->regs + I2C_TIMING); +- } else if (port_has_drxks(port)) { +- modname = "DUAL DVB-C/T"; +- port->class = DDB_PORT_TUNER; +- port->type = DDB_TUNER_DVBCT_TR; +- ddbwritel(I2C_SPEED_400, port->i2c->regs + I2C_TIMING); ++ if (dev->port[num].type >= DDB_TUNER_XO2) { ++ if (i2c_read_regs(&dev->i2c[num].adap, 0x10, 0x10, snr, 16) < 0) ++ return sprintf(buf, "NO SNR\n"); ++ snr[16] = 0; ++ } else { ++ /* serial number at 0x100-0x11f */ ++ if (i2c_read_regs16(&dev->i2c[num].adap, ++ 0x57, 0x100, snr, 32) < 0) ++ if (i2c_read_regs16(&dev->i2c[num].adap, ++ 0x50, 0x100, snr, 32) < 0) ++ return sprintf(buf, "NO SNR\n"); ++ snr[31] = 0; /* in case it is not terminated on EEPROM */ + } +- printk(KERN_INFO "Port %d (TAB %d): %s\n", +- port->nr, port->nr+1, modname); ++ return sprintf(buf, "%s\n", snr); + } + +-static void ddb_input_init(struct ddb_port *port, int nr) +-{ +- struct ddb *dev = port->dev; +- struct ddb_input *input = &dev->input[nr]; + +- input->nr = nr; +- input->port = port; +- input->dma_buf_num = INPUT_DMA_BUFS; +- input->dma_buf_size = INPUT_DMA_SIZE; +- ddbwritel(0, TS_INPUT_CONTROL(nr)); +- ddbwritel(2, TS_INPUT_CONTROL(nr)); +- ddbwritel(0, TS_INPUT_CONTROL(nr)); +- ddbwritel(0, DMA_BUFFER_ACK(nr)); +- tasklet_init(&input->tasklet, input_tasklet, (unsigned long) input); +- spin_lock_init(&input->lock); +- init_waitqueue_head(&input->wq); ++static ssize_t snr_store(struct device *device, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct ddb *dev = dev_get_drvdata(device); ++ int num = attr->attr.name[3] - 0x30; ++ u8 snr[34] = { 0x01, 0x00 }; ++ ++ return 0; /* NOE: remove completely? */ ++ if (count > 31) ++ return -EINVAL; ++ if (dev->port[num].type >= DDB_TUNER_XO2) ++ return -EINVAL; ++ memcpy(snr + 2, buf, count); ++ i2c_write(&dev->i2c[num].adap, 0x57, snr, 34); ++ i2c_write(&dev->i2c[num].adap, 0x50, snr, 34); ++ return count; + } + +-static void ddb_output_init(struct ddb_port *port, int nr) ++static ssize_t bsnr_show(struct device *device, ++ struct device_attribute *attr, char *buf) + { +- struct ddb *dev = port->dev; +- struct ddb_output *output = &dev->output[nr]; +- output->nr = nr; +- output->port = port; +- output->dma_buf_num = OUTPUT_DMA_BUFS; +- output->dma_buf_size = OUTPUT_DMA_SIZE; ++ struct ddb *dev = dev_get_drvdata(device); ++ char snr[16]; + +- ddbwritel(0, TS_OUTPUT_CONTROL(nr)); +- ddbwritel(2, TS_OUTPUT_CONTROL(nr)); +- ddbwritel(0, TS_OUTPUT_CONTROL(nr)); +- tasklet_init(&output->tasklet, output_tasklet, (unsigned long) output); +- init_waitqueue_head(&output->wq); ++ ddbridge_flashread(dev, 0, snr, 0x10, 15); ++ snr[15] = 0; /* in case it is not terminated on EEPROM */ ++ return sprintf(buf, "%s\n", snr); + } + +-static void ddb_ports_init(struct ddb *dev) ++static ssize_t bpsnr_show(struct device *device, ++ struct device_attribute *attr, char *buf) + { +- int i; +- struct ddb_port *port; ++ struct ddb *dev = dev_get_drvdata(device); ++ char snr[32]; + +- for (i = 0; i < dev->info->port_num; i++) { +- port = &dev->port[i]; +- port->dev = dev; +- port->nr = i; +- port->i2c = &dev->i2c[i]; +- port->input[0] = &dev->input[2 * i]; +- port->input[1] = &dev->input[2 * i + 1]; +- port->output = &dev->output[i]; ++ if (!dev->i2c_num) ++ return 0; + +- mutex_init(&port->i2c_gate_lock); +- ddb_port_probe(port); +- ddb_input_init(port, 2 * i); +- ddb_input_init(port, 2 * i + 1); +- ddb_output_init(port, i); +- } ++ if (i2c_read_regs16(&dev->i2c[0].adap, ++ 0x50, 0x0000, snr, 32) < 0 || ++ snr[0] == 0xff) ++ return sprintf(buf, "NO SNR\n"); ++ snr[31] = 0; /* in case it is not terminated on EEPROM */ ++ return sprintf(buf, "%s\n", snr); + } + +-static void ddb_ports_release(struct ddb *dev) ++static ssize_t redirect_show(struct device *device, ++ struct device_attribute *attr, char *buf) + { +- int i; +- struct ddb_port *port; +- +- for (i = 0; i < dev->info->port_num; i++) { +- port = &dev->port[i]; +- port->dev = dev; +- tasklet_kill(&port->input[0]->tasklet); +- tasklet_kill(&port->input[1]->tasklet); +- tasklet_kill(&port->output->tasklet); +- } ++ return 0; + } + +-/****************************************************************************/ +-/****************************************************************************/ +-/****************************************************************************/ +- +-static void irq_handle_i2c(struct ddb *dev, int n) ++static ssize_t redirect_store(struct device *device, ++ struct device_attribute *attr, ++ const char *buf, size_t count) + { +- struct ddb_i2c *i2c = &dev->i2c[n]; ++ unsigned int i, p; ++ int res; + +- i2c->done = 1; +- wake_up(&i2c->wq); ++ if (sscanf(buf, "%x %x\n", &i, &p) != 2) ++ return -EINVAL; ++ res = ddb_redirect(i, p); ++ if (res < 0) ++ return res; ++ pr_info("redirect: %02x, %02x\n", i, p); ++ return count; + } + +-static irqreturn_t irq_handler(int irq, void *dev_id) ++static ssize_t gap_show(struct device *device, ++ struct device_attribute *attr, char *buf) + { +- struct ddb *dev = (struct ddb *) dev_id; +- u32 s = ddbreadl(INTERRUPT_STATUS); +- +- if (!s) +- return IRQ_NONE; ++ struct ddb *dev = dev_get_drvdata(device); ++ int num = attr->attr.name[3] - 0x30; + +- do { +- ddbwritel(s, INTERRUPT_ACK); +- +- if (s & 0x00000001) +- irq_handle_i2c(dev, 0); +- if (s & 0x00000002) +- irq_handle_i2c(dev, 1); +- if (s & 0x00000004) +- irq_handle_i2c(dev, 2); +- if (s & 0x00000008) +- irq_handle_i2c(dev, 3); +- +- if (s & 0x00000100) +- tasklet_schedule(&dev->input[0].tasklet); +- if (s & 0x00000200) +- tasklet_schedule(&dev->input[1].tasklet); +- if (s & 0x00000400) +- tasklet_schedule(&dev->input[2].tasklet); +- if (s & 0x00000800) +- tasklet_schedule(&dev->input[3].tasklet); +- if (s & 0x00001000) +- tasklet_schedule(&dev->input[4].tasklet); +- if (s & 0x00002000) +- tasklet_schedule(&dev->input[5].tasklet); +- if (s & 0x00004000) +- tasklet_schedule(&dev->input[6].tasklet); +- if (s & 0x00008000) +- tasklet_schedule(&dev->input[7].tasklet); +- +- if (s & 0x00010000) +- tasklet_schedule(&dev->output[0].tasklet); +- if (s & 0x00020000) +- tasklet_schedule(&dev->output[1].tasklet); +- if (s & 0x00040000) +- tasklet_schedule(&dev->output[2].tasklet); +- if (s & 0x00080000) +- tasklet_schedule(&dev->output[3].tasklet); +- +- /* if (s & 0x000f0000) printk(KERN_DEBUG "%08x\n", istat); */ +- } while ((s = ddbreadl(INTERRUPT_STATUS))); ++ return sprintf(buf, "%d\n", dev->port[num].gap); + +- return IRQ_HANDLED; + } + +-/******************************************************************************/ +-/******************************************************************************/ +-/******************************************************************************/ +- +-static int flashio(struct ddb *dev, u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) ++static ssize_t gap_store(struct device *device, struct device_attribute *attr, ++ const char *buf, size_t count) + { +- u32 data, shift; +- +- if (wlen > 4) +- ddbwritel(1, SPI_CONTROL); +- while (wlen > 4) { +- /* FIXME: check for big-endian */ +- data = swab32(*(u32 *)wbuf); +- wbuf += 4; +- wlen -= 4; +- ddbwritel(data, SPI_DATA); +- while (ddbreadl(SPI_CONTROL) & 0x0004) +- ; +- } +- +- if (rlen) +- ddbwritel(0x0001 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); +- else +- ddbwritel(0x0003 | ((wlen << (8 + 3)) & 0x1f00), SPI_CONTROL); ++ struct ddb *dev = dev_get_drvdata(device); ++ int num = attr->attr.name[3] - 0x30; ++ unsigned int val; ++ ++ if (sscanf(buf, "%u\n", &val) != 1) ++ return -EINVAL; ++ if (val > 20) ++ return -EINVAL; ++ dev->port[num].gap = val; ++ return count; ++} + +- data = 0; +- shift = ((4 - wlen) * 8); +- while (wlen) { +- data <<= 8; +- data |= *wbuf; +- wlen--; +- wbuf++; +- } +- if (shift) +- data <<= shift; +- ddbwritel(data, SPI_DATA); +- while (ddbreadl(SPI_CONTROL) & 0x0004) +- ; ++static ssize_t version_show(struct device *device, ++ struct device_attribute *attr, char *buf) ++{ ++ struct ddb *dev = dev_get_drvdata(device); + +- if (!rlen) { +- ddbwritel(0, SPI_CONTROL); +- return 0; +- } +- if (rlen > 4) +- ddbwritel(1, SPI_CONTROL); ++ return sprintf(buf, "%08x %08x\n", ++ dev->link[0].ids.hwid, dev->link[0].ids.regmapid); ++} + +- while (rlen > 4) { +- ddbwritel(0xffffffff, SPI_DATA); +- while (ddbreadl(SPI_CONTROL) & 0x0004) +- ; +- data = ddbreadl(SPI_DATA); +- *(u32 *) rbuf = swab32(data); +- rbuf += 4; +- rlen -= 4; +- } +- ddbwritel(0x0003 | ((rlen << (8 + 3)) & 0x1F00), SPI_CONTROL); +- ddbwritel(0xffffffff, SPI_DATA); +- while (ddbreadl(SPI_CONTROL) & 0x0004) +- ; ++static ssize_t hwid_show(struct device *device, ++ struct device_attribute *attr, char *buf) ++{ ++ struct ddb *dev = dev_get_drvdata(device); + +- data = ddbreadl(SPI_DATA); +- ddbwritel(0, SPI_CONTROL); ++ return sprintf(buf, "0x%08X\n", dev->link[0].ids.hwid); ++} + +- if (rlen < 4) +- data <<= ((4 - rlen) * 8); ++static ssize_t regmap_show(struct device *device, ++ struct device_attribute *attr, char *buf) ++{ ++ struct ddb *dev = dev_get_drvdata(device); + +- while (rlen > 0) { +- *rbuf = ((data >> 24) & 0xff); +- data <<= 8; +- rbuf++; +- rlen--; +- } +- return 0; ++ return sprintf(buf, "0x%08X\n", dev->link[0].ids.regmapid); + } + +-#define DDB_MAGIC 'd' ++static ssize_t vlan_show(struct device *device, ++ struct device_attribute *attr, char *buf) ++{ ++ struct ddb *dev = dev_get_drvdata(device); + +-struct ddb_flashio { +- __user __u8 *write_buf; +- __u32 write_len; +- __user __u8 *read_buf; +- __u32 read_len; +-}; ++ return sprintf(buf, "%u\n", dev->vlan); ++} + +-#define IOCTL_DDB_FLASHIO _IOWR(DDB_MAGIC, 0x00, struct ddb_flashio) ++static ssize_t vlan_store(struct device *device, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct ddb *dev = dev_get_drvdata(device); ++ unsigned int val; ++ ++ if (sscanf(buf, "%u\n", &val) != 1) ++ return -EINVAL; ++ if (val > 1) ++ return -EINVAL; ++ if (!dev->link[0].info->ns_num) ++ return -EINVAL; ++ ddbwritel(dev, 14 + (val ? 4 : 0), ETHER_LENGTH); ++ dev->vlan = val; ++ return count; ++} + +-#define DDB_NAME "ddbridge" ++static ssize_t fmode_show(struct device *device, ++ struct device_attribute *attr, char *buf) ++{ ++ int num = attr->attr.name[5] - 0x30; ++ struct ddb *dev = dev_get_drvdata(device); + +-static u32 ddb_num; +-static struct ddb *ddbs[32]; +-static struct class *ddb_class; +-static int ddb_major; ++ return sprintf(buf, "%u\n", dev->link[num].lnb.fmode); ++} + +-static int ddb_open(struct inode *inode, struct file *file) ++static ssize_t devid_show(struct device *device, ++ struct device_attribute *attr, char *buf) + { +- struct ddb *dev = ddbs[iminor(inode)]; ++ int num = attr->attr.name[5] - 0x30; ++ struct ddb *dev = dev_get_drvdata(device); + +- file->private_data = dev; +- return 0; ++ return sprintf(buf, "%08x\n", dev->link[num].ids.devid); + } + +-static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++static ssize_t fmode_store(struct device *device, struct device_attribute *attr, ++ const char *buf, size_t count) + { +- struct ddb *dev = file->private_data; +- __user void *parg = (__user void *)arg; +- int res; ++ struct ddb *dev = dev_get_drvdata(device); ++ int num = attr->attr.name[5] - 0x30; ++ unsigned int val; ++ ++ if (sscanf(buf, "%u\n", &val) != 1) ++ return -EINVAL; ++ if (val > 3) ++ return -EINVAL; ++ lnb_init_fmode(dev, &dev->link[num], val); ++ return count; ++} + +- switch (cmd) { +- case IOCTL_DDB_FLASHIO: +- { +- struct ddb_flashio fio; +- u8 *rbuf, *wbuf; ++static struct device_attribute ddb_attrs[] = { ++ __ATTR_RO(version), ++ __ATTR_RO(ports), ++ __ATTR_RO(ts_irq), ++ __ATTR_RO(i2c_irq), ++ __ATTR(gap0, 0664, gap_show, gap_store), ++ __ATTR(gap1, 0664, gap_show, gap_store), ++ __ATTR(gap2, 0664, gap_show, gap_store), ++ __ATTR(gap3, 0664, gap_show, gap_store), ++ __ATTR(vlan, 0664, vlan_show, vlan_store), ++ __ATTR(fmode0, 0664, fmode_show, fmode_store), ++ __ATTR(fmode1, 0664, fmode_show, fmode_store), ++ __ATTR(fmode2, 0664, fmode_show, fmode_store), ++ __ATTR(fmode3, 0664, fmode_show, fmode_store), ++ __ATTR_MRO(devid0, devid_show), ++ __ATTR_MRO(devid1, devid_show), ++ __ATTR_MRO(devid2, devid_show), ++ __ATTR_MRO(devid3, devid_show), ++ __ATTR_RO(hwid), ++ __ATTR_RO(regmap), ++ __ATTR(redirect, 0664, redirect_show, redirect_store), ++ __ATTR_MRO(snr, bsnr_show), ++ __ATTR_RO(bpsnr), ++ __ATTR_NULL, ++}; + +- if (copy_from_user(&fio, parg, sizeof(fio))) +- return -EFAULT; ++static struct device_attribute ddb_attrs_temp[] = { ++ __ATTR_RO(temp), ++}; + +- if (fio.write_len > 1028 || fio.read_len > 1028) +- return -EINVAL; +- if (fio.write_len + fio.read_len > 1028) +- return -EINVAL; ++static struct device_attribute ddb_attrs_mod[] = { ++ __ATTR_MRO(mod0, mod_show), ++ __ATTR_MRO(mod1, mod_show), ++ __ATTR_MRO(mod2, mod_show), ++ __ATTR_MRO(mod3, mod_show), ++ __ATTR_MRO(mod4, mod_show), ++ __ATTR_MRO(mod5, mod_show), ++ __ATTR_MRO(mod6, mod_show), ++ __ATTR_MRO(mod7, mod_show), ++ __ATTR_MRO(mod8, mod_show), ++ __ATTR_MRO(mod9, mod_show), ++}; + +- wbuf = &dev->iobuf[0]; +- rbuf = wbuf + fio.write_len; ++static struct device_attribute ddb_attrs_fan[] = { ++ __ATTR(fan, 0664, fan_show, fan_store), ++}; + +- if (copy_from_user(wbuf, fio.write_buf, fio.write_len)) +- return -EFAULT; +- res = flashio(dev, wbuf, fio.write_len, rbuf, fio.read_len); +- if (res) +- return res; +- if (copy_to_user(fio.read_buf, rbuf, fio.read_len)) +- return -EFAULT; +- break; +- } +- default: +- return -ENOTTY; +- } +- return 0; +-} ++static struct device_attribute ddb_attrs_snr[] = { ++ __ATTR(snr0, 0664, snr_show, snr_store), ++ __ATTR(snr1, 0664, snr_show, snr_store), ++ __ATTR(snr2, 0664, snr_show, snr_store), ++ __ATTR(snr3, 0664, snr_show, snr_store), ++}; + +-static const struct file_operations ddb_fops = { +- .unlocked_ioctl = ddb_ioctl, +- .open = ddb_open, ++static struct device_attribute ddb_attrs_ctemp[] = { ++ __ATTR_MRO(temp0, ctemp_show), ++ __ATTR_MRO(temp1, ctemp_show), ++ __ATTR_MRO(temp2, ctemp_show), ++ __ATTR_MRO(temp3, ctemp_show), + }; + +-static char *ddb_devnode(struct device *device, umode_t *mode) +-{ +- struct ddb *dev = dev_get_drvdata(device); ++static struct device_attribute ddb_attrs_led[] = { ++ __ATTR(led0, 0664, led_show, led_store), ++ __ATTR(led1, 0664, led_show, led_store), ++ __ATTR(led2, 0664, led_show, led_store), ++ __ATTR(led3, 0664, led_show, led_store), ++}; + +- return kasprintf(GFP_KERNEL, "ddbridge/card%d", dev->nr); +-} ++static struct class ddb_class = { ++ .name = "ddbridge", ++ .owner = THIS_MODULE, ++ .devnode = ddb_devnode, ++}; + + static int ddb_class_create(void) + { + ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops); + if (ddb_major < 0) + return ddb_major; +- +- ddb_class = class_create(THIS_MODULE, DDB_NAME); +- if (IS_ERR(ddb_class)) { +- unregister_chrdev(ddb_major, DDB_NAME); +- return PTR_ERR(ddb_class); +- } +- ddb_class->devnode = ddb_devnode; ++ if (class_register(&ddb_class) < 0) ++ return -1; + return 0; + } + + static void ddb_class_destroy(void) + { +- class_destroy(ddb_class); ++ class_unregister(&ddb_class); + unregister_chrdev(ddb_major, DDB_NAME); + } + ++static void ddb_device_attrs_del(struct ddb *dev) ++{ ++ int i; ++ ++ for (i = 0; i < dev->link[0].info->temp_num; i++) ++ device_remove_file(dev->ddb_dev, &ddb_attrs_temp[i]); ++ for (i = 0; i < dev->link[0].info->port_num; i++) ++ device_remove_file(dev->ddb_dev, &ddb_attrs_mod[i]); ++ for (i = 0; i < dev->link[0].info->fan_num; i++) ++ device_remove_file(dev->ddb_dev, &ddb_attrs_fan[i]); ++ for (i = 0; i < dev->i2c_num && i < 4; i++) { ++ if (dev->link[0].info->led_num) ++ device_remove_file(dev->ddb_dev, &ddb_attrs_led[i]); ++ device_remove_file(dev->ddb_dev, &ddb_attrs_snr[i]); ++ device_remove_file(dev->ddb_dev, &ddb_attrs_ctemp[i]); ++ } ++ for (i = 0; ddb_attrs[i].attr.name; i++) ++ device_remove_file(dev->ddb_dev, &ddb_attrs[i]); ++} ++ ++static int ddb_device_attrs_add(struct ddb *dev) ++{ ++ int i; ++ ++ for (i = 0; ddb_attrs[i].attr.name; i++) ++ if (device_create_file(dev->ddb_dev, &ddb_attrs[i])) ++ goto fail; ++ for (i = 0; i < dev->link[0].info->temp_num; i++) ++ if (device_create_file(dev->ddb_dev, &ddb_attrs_temp[i])) ++ goto fail; ++ for (i = 0; i < dev->link[0].info->port_num; i++) ++ if (device_create_file(dev->ddb_dev, &ddb_attrs_mod[i])) ++ goto fail; ++ for (i = 0; i < dev->link[0].info->fan_num; i++) ++ if (device_create_file(dev->ddb_dev, &ddb_attrs_fan[i])) ++ goto fail; ++ for (i = 0; i < dev->i2c_num && i < 4; i++) { ++ if (device_create_file(dev->ddb_dev, &ddb_attrs_snr[i])) ++ goto fail; ++ if (device_create_file(dev->ddb_dev, &ddb_attrs_ctemp[i])) ++ goto fail; ++ if (dev->link[0].info->led_num) ++ if (device_create_file(dev->ddb_dev, ++ &ddb_attrs_led[i])) ++ goto fail; ++ } ++ return 0; ++fail: ++ return -1; ++} ++ + static int ddb_device_create(struct ddb *dev) + { +- dev->nr = ddb_num++; +- dev->ddb_dev = device_create(ddb_class, NULL, ++ int res = 0; ++ ++ if (ddb_num == DDB_MAX_ADAPTER) ++ return -ENOMEM; ++ mutex_lock(&ddb_mutex); ++ dev->nr = ddb_num; ++ ddbs[dev->nr] = dev; ++ dev->ddb_dev = device_create(&ddb_class, dev->dev, + MKDEV(ddb_major, dev->nr), + dev, "ddbridge%d", dev->nr); +- ddbs[dev->nr] = dev; +- if (IS_ERR(dev->ddb_dev)) +- return -1; +- return 0; ++ if (IS_ERR(dev->ddb_dev)) { ++ res = PTR_ERR(dev->ddb_dev); ++ pr_info("Could not create ddbridge%d\n", dev->nr); ++ goto fail; ++ } ++ res = ddb_device_attrs_add(dev); ++ if (res) { ++ ddb_device_attrs_del(dev); ++ device_destroy(&ddb_class, MKDEV(ddb_major, dev->nr)); ++ ddbs[dev->nr] = 0; ++ dev->ddb_dev = ERR_PTR(-ENODEV); ++ } else ++ ddb_num++; ++fail: ++ mutex_unlock(&ddb_mutex); ++ return res; + } + + static void ddb_device_destroy(struct ddb *dev) + { +- ddb_num--; + if (IS_ERR(dev->ddb_dev)) + return; +- device_destroy(ddb_class, MKDEV(ddb_major, 0)); ++ ddb_device_attrs_del(dev); ++ device_destroy(&ddb_class, MKDEV(ddb_major, dev->nr)); + } + ++#define LINK_IRQ_HANDLE(_nr) \ ++ do { if ((s & (1UL << _nr)) && dev->handler[_nr + off]) \ ++ dev->handler[_nr + off](dev->handler_data[_nr + off]); } \ ++ while (0) + +-/****************************************************************************/ +-/****************************************************************************/ +-/****************************************************************************/ +- +-static void ddb_unmap(struct ddb *dev) ++static void gtl_link_handler(unsigned long priv) + { +- if (dev->regs) +- iounmap(dev->regs); +- vfree(dev); +-} ++ struct ddb *dev = (struct ddb *) priv; ++ u32 regs = dev->link[0].info->regmap->gtl->base; + ++ pr_info("GT link change: %u\n", ++ (1 & ddbreadl(dev, regs))); ++} + +-static void ddb_remove(struct pci_dev *pdev) ++static void link_tasklet(unsigned long data) + { +- struct ddb *dev = pci_get_drvdata(pdev); +- +- ddb_ports_detach(dev); +- ddb_i2c_release(dev); ++ struct ddb_link *link = (struct ddb_link *) data; ++ struct ddb *dev = link->dev; ++ u32 s, off = 32 * link->nr, tag = DDB_LINK_TAG(link->nr); + +- ddbwritel(0, INTERRUPT_ENABLE); +- free_irq(dev->pdev->irq, dev); +-#ifdef CONFIG_PCI_MSI +- if (dev->msi) +- pci_disable_msi(dev->pdev); +-#endif +- ddb_ports_release(dev); +- ddb_buffers_free(dev); +- ddb_device_destroy(dev); ++ s = ddbreadl(dev, tag | INTERRUPT_STATUS); ++ pr_info("gtl_irq %08x = %08x\n", tag | INTERRUPT_STATUS, s); + +- ddb_unmap(dev); +- pci_set_drvdata(pdev, NULL); +- pci_disable_device(pdev); ++ if (!s) ++ return; ++ ddbwritel(dev, s, tag | INTERRUPT_ACK); ++ LINK_IRQ_HANDLE(0); ++ LINK_IRQ_HANDLE(1); ++ LINK_IRQ_HANDLE(2); ++ LINK_IRQ_HANDLE(3); + } + +- +-static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id) ++static void gtl_irq_handler(unsigned long priv) + { +- struct ddb *dev; +- int stat = 0; +- int irq_flag = IRQF_SHARED; +- +- if (pci_enable_device(pdev) < 0) +- return -ENODEV; +- +- dev = vmalloc(sizeof(struct ddb)); +- if (dev == NULL) +- return -ENOMEM; +- memset(dev, 0, sizeof(struct ddb)); +- +- dev->pdev = pdev; +- pci_set_drvdata(pdev, dev); +- dev->info = (struct ddb_info *) id->driver_data; +- printk(KERN_INFO "DDBridge driver detected: %s\n", dev->info->name); +- +- dev->regs = ioremap(pci_resource_start(dev->pdev, 0), +- pci_resource_len(dev->pdev, 0)); +- if (!dev->regs) { +- stat = -ENOMEM; +- goto fail; +- } +- printk(KERN_INFO "HW %08x FW %08x\n", ddbreadl(0), ddbreadl(4)); +- -#ifdef CONFIG_PCI_MSI - if (pci_msi_enabled()) - stat = pci_enable_msi(dev->pdev); - if (stat) { - printk(KERN_INFO ": MSI not available.\n"); -+ if (dev->port[num].type >= DDB_TUNER_XO2) { -+ if (i2c_read_regs(&dev->i2c[num].adap, 0x10, 0x10, snr, 16) < 0) -+ return sprintf(buf, "NO SNR\n"); -+ snr[16] = 0; - } else { +- } else { - irq_flag = 0; - dev->msi = 1; -+ /* serial number at 0x100-0x11f */ -+ if (i2c_read_regs16(&dev->i2c[num].adap, -+ 0x50, 0x100, snr, 32) < 0) -+ if (i2c_read_regs16(&dev->i2c[num].adap, -+ 0x57, 0x100, snr, 32) < 0) -+ return sprintf(buf, "NO SNR\n"); -+ snr[31] = 0; /* in case it is not terminated on EEPROM */ - } +- } -#endif - stat = request_irq(dev->pdev->irq, irq_handler, - irq_flag, "DDBridge", (void *) dev); @@ -26867,48 +23509,22 @@ index 9e3492e..c2fc010 100644 - if (ddb_buffers_alloc(dev) < 0) { - printk(KERN_INFO ": Could not allocate buffer memory\n"); - goto fail2; -- } ++ struct ddb_link *link = (struct ddb_link *) priv; ++ struct ddb *dev = link->dev; ++ u32 s, off = 32 * link->nr, tag = DDB_LINK_TAG(link->nr); ++ ++ while ((s = ddbreadl(dev, tag | INTERRUPT_STATUS))) { ++ ddbwritel(dev, s, tag | INTERRUPT_ACK); ++ LINK_IRQ_HANDLE(0); ++ LINK_IRQ_HANDLE(1); ++ LINK_IRQ_HANDLE(2); ++ LINK_IRQ_HANDLE(3); + } - if (ddb_ports_attach(dev) < 0) - goto fail3; - ddb_device_create(dev); -+ return sprintf(buf, "%s\n", snr); -+} -+ -+ -+static ssize_t snr_store(struct device *device, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ int num = attr->attr.name[3] - 0x30; -+ u8 snr[34] = { 0x01, 0x00 }; -+ -+ if (count > 31) -+ return -EINVAL; -+ if (dev->port[num].type >= DDB_TUNER_XO2) -+ return -EINVAL; -+ memcpy(snr + 2, buf, count); -+ i2c_write(&dev->i2c[num].adap, 0x57, snr, 34); -+ i2c_write(&dev->i2c[num].adap, 0x50, snr, 34); -+ return count; -+} -+ -+static ssize_t bsnr_show(struct device *device, -+ struct device_attribute *attr, char *buf) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ char snr[16]; -+ -+ ddbridge_flashread(dev, snr, 0x10, 15); -+ snr[15] = 0; /* in case it is not terminated on EEPROM */ -+ return sprintf(buf, "%s\n", snr); -+} -+ -+static ssize_t redirect_show(struct device *device, -+ struct device_attribute *attr, char *buf) -+{ - return 0; -+} - +- return 0; +- -fail3: - ddb_ports_detach(dev); - printk(KERN_ERR "fail3\n"); @@ -26920,83 +23536,59 @@ index 9e3492e..c2fc010 100644 - printk(KERN_ERR "fail1\n"); - if (dev->msi) - pci_disable_msi(dev->pdev); -- free_irq(dev->pdev->irq, dev); +- if (stat == 0) +- free_irq(dev->pdev->irq, dev); -fail: - printk(KERN_ERR "fail\n"); - ddb_unmap(dev); - pci_set_drvdata(pdev, NULL); - pci_disable_device(pdev); - return -1; -+static ssize_t redirect_store(struct device *device, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ unsigned int i, p; -+ int res; -+ -+ if (sscanf(buf, "%x %x\n", &i, &p) != 2) -+ return -EINVAL; -+ res = ddb_redirect(i, p); -+ if (res < 0) -+ return res; -+ pr_info("redirect: %02x, %02x\n", i, p); -+ return count; } -/******************************************************************************/ -/******************************************************************************/ -/******************************************************************************/ -+static ssize_t gap_show(struct device *device, -+ struct device_attribute *attr, char *buf) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ int num = attr->attr.name[3] - 0x30; - +- -static struct ddb_info ddb_none = { - .type = DDB_NONE, - .name = "Digital Devices PCIe bridge", --}; -+ return sprintf(buf, "%d\n", dev->port[num].gap); ++static struct ddb_regset octopus_max_gtl_i2c = { ++ .base = 0x80, ++ .num = 0x01, ++ .size = 0x20, + }; -static struct ddb_info ddb_octopus = { - .type = DDB_OCTOPUS, - .name = "Digital Devices Octopus DVB adapter", - .port_num = 4, --}; -+} -+static ssize_t gap_store(struct device *device, struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ int num = attr->attr.name[3] - 0x30; -+ unsigned int val; -+ -+ if (sscanf(buf, "%u\n", &val) != 1) -+ return -EINVAL; -+ if (val > 20) -+ return -EINVAL; -+ dev->port[num].gap = val; -+ return count; -+} ++static struct ddb_regset octopus_max_gtl_i2c_buf = { ++ .base = 0x1000, ++ .num = 0x01, ++ .size = 0x200, + }; -static struct ddb_info ddb_octopus_le = { - .type = DDB_OCTOPUS, - .name = "Digital Devices Octopus LE DVB adapter", - .port_num = 2, --}; -+static ssize_t version_show(struct device *device, -+ struct device_attribute *attr, char *buf) -+{ -+ struct ddb *dev = dev_get_drvdata(device); ++static struct ddb_regmap octopus_max_gtl_map = { ++ .i2c = &octopus_max_gtl_i2c, ++ .i2c_buf = &octopus_max_gtl_i2c_buf, + }; -static struct ddb_info ddb_octopus_mini = { - .type = DDB_OCTOPUS, - .name = "Digital Devices Octopus Mini", -- .port_num = 4, --}; -+ return sprintf(buf, "%08x %08x\n", -+ ddbreadl(dev, 0), ddbreadl(dev, 4)); -+} ++static struct ddb_info octopus_max_gtl = { ++ .type = DDB_OCTOPUS_MAX, ++ .name = "Digital Devices Octopus MAX GTL", ++ .regmap = &octopus_max_gtl_map, + .port_num = 4, ++ .i2c_mask = 0x01, ++ .board_control = 1, + }; -static struct ddb_info ddb_v6 = { - .type = DDB_OCTOPUS, @@ -27007,72 +23599,44 @@ index 9e3492e..c2fc010 100644 - .type = DDB_OCTOPUS, - .name = "Digital Devices Cine S2 V6.5 DVB adapter", - .port_num = 4, -+static ssize_t hwid_show(struct device *device, -+ struct device_attribute *attr, char *buf) -+{ -+ struct ddb *dev = dev_get_drvdata(device); + -+ return sprintf(buf, "0x%08X\n", dev->ids.hwid); -+} -+ -+static ssize_t regmap_show(struct device *device, -+ struct device_attribute *attr, char *buf) -+{ -+ struct ddb *dev = dev_get_drvdata(device); -+ -+ return sprintf(buf, "0x%08X\n", dev->ids.regmapid); -+} -+ -+static struct device_attribute ddb_attrs[] = { -+ __ATTR_RO(version), -+ __ATTR_RO(ports), -+ __ATTR_RO(ts_irq), -+ __ATTR_RO(i2c_irq), -+ __ATTR(gap0, 0664, gap_show, gap_store), -+ __ATTR(gap1, 0664, gap_show, gap_store), -+ __ATTR(gap2, 0664, gap_show, gap_store), -+ __ATTR(gap3, 0664, gap_show, gap_store), -+ __ATTR_RO(hwid), -+ __ATTR_RO(regmap), -+#if 0 -+ __ATTR_RO(qam), -+#endif -+ __ATTR(redirect, 0664, redirect_show, redirect_store), -+ __ATTR_MRO(snr, bsnr_show), -+ __ATTR_NULL, ++static struct ddb_regset octopus_maxct_gtl_i2c = { ++ .base = 0x80, ++ .num = 0x04, ++ .size = 0x20, }; -static struct ddb_info ddb_dvbct = { - .type = DDB_OCTOPUS, - .name = "Digital Devices DVBCT V6.1 DVB adapter", - .port_num = 3, -+static struct device_attribute ddb_attrs_temp[] = { -+ __ATTR_RO(temp), ++static struct ddb_regset octopus_maxct_gtl_i2c_buf = { ++ .base = 0x1000, ++ .num = 0x04, ++ .size = 0x200, }; -static struct ddb_info ddb_satixS2v3 = { - .type = DDB_OCTOPUS, - .name = "Mystique SaTiX-S2 V3 DVB adapter", - .port_num = 3, -+static struct device_attribute ddb_attrs_mod[] = { -+ __ATTR_MRO(mod0, mod_show), -+ __ATTR_MRO(mod1, mod_show), -+ __ATTR_MRO(mod2, mod_show), -+ __ATTR_MRO(mod3, mod_show), -+ __ATTR_MRO(mod4, mod_show), -+ __ATTR_MRO(mod5, mod_show), -+ __ATTR_MRO(mod6, mod_show), -+ __ATTR_MRO(mod7, mod_show), -+ __ATTR_MRO(mod8, mod_show), -+ __ATTR_MRO(mod9, mod_show), ++static struct ddb_regmap octopus_maxct_gtl_map = { ++ .i2c = &octopus_maxct_gtl_i2c, ++ .i2c_buf = &octopus_maxct_gtl_i2c_buf, }; -static struct ddb_info ddb_octopusv3 = { - .type = DDB_OCTOPUS, - .name = "Digital Devices Octopus V3 DVB adapter", -- .port_num = 4, -+static struct device_attribute ddb_attrs_fan[] = { -+ __ATTR(fan, 0664, fan_show, fan_store), ++static struct ddb_info octopus_ct_gtl = { ++ .type = DDB_OCTOPUS_MAX_CT, ++ .name = "Digital Devices Octopus MAX CT GTL", ++ .regmap = &octopus_maxct_gtl_map, + .port_num = 4, ++ .i2c_mask = 0x0f, ++ .board_control = 0xff, ++ .board_control_2 = 0xf00, ++ .ts_quirks = TS_QUIRK_SERIAL, }; -#define DDVID 0xdd01 /* Digital Devices Vendor ID */ @@ -27095,58 +23659,91 @@ index 9e3492e..c2fc010 100644 - /* in case sub-ids got deleted in flash */ - DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none), - {0} -+static struct device_attribute ddb_attrs_snr[] = { -+ __ATTR(snr0, 0664, snr_show, snr_store), -+ __ATTR(snr1, 0664, snr_show, snr_store), -+ __ATTR(snr2, 0664, snr_show, snr_store), -+ __ATTR(snr3, 0664, snr_show, snr_store), - }; +-}; -MODULE_DEVICE_TABLE(pci, ddb_id_tbl); -+static struct device_attribute ddb_attrs_led[] = { -+ __ATTR(led0, 0664, led_show, led_store), -+ __ATTR(led1, 0664, led_show, led_store), -+ __ATTR(led2, 0664, led_show, led_store), -+ __ATTR(led3, 0664, led_show, led_store), -+}; ++static int ddb_gtl_init_link(struct ddb *dev, u32 l) ++{ ++ struct ddb_link *link = &dev->link[l]; ++ u32 regs = dev->link[0].info->regmap->gtl->base + ++ (l - 1) * dev->link[0].info->regmap->gtl->size; ++ u32 id; ++ ++ pr_info("Checking GT link %u: regs = %08x\n", l, regs); ++ ++ spin_lock_init(&link->lock); ++ mutex_init(&link->lnb.lock); ++ link->lnb.fmode = 0xffffffff; ++ mutex_init(&link->flash_mutex); ++ ++ if (!(1 & ddbreadl(dev, regs))) { ++ u32 c; ++ ++ for (c = 0; c < 5; c++) { ++ ddbwritel(dev, 2, regs); ++ msleep(20); ++ ddbwritel(dev, 0, regs); ++ msleep(200); ++ if (1 & ddbreadl(dev, regs)) ++ break; ++ } ++ if (c == 5) ++ return -1; ++ } ++ link->nr = l; ++ link->dev = dev; ++ link->regs = regs; ++ ++ id = ddbreadl(dev, DDB_LINK_TAG(l) | 8); ++ switch (id) { ++ case 0x0007dd01: ++ link->info = &octopus_max_gtl; ++ break; ++ case 0x0008dd01: ++ link->info = &octopus_ct_gtl; ++ break; ++ default: ++ pr_info("DDBridge: Detected GT link but found invalid ID %08x. You might have to update (flash) the add-on card first.", ++ id); ++ return -1; ++ } ++ link->ids.devid = id; ++ ++ ddbwritel(dev, 1, 0x1a0); -static struct pci_driver ddb_pci_driver = { - .name = "DDBridge", - .id_table = ddb_id_tbl, - .probe = ddb_probe, - .remove = ddb_remove, -+static struct class ddb_class = { -+ .name = "ddbridge", -+ .owner = THIS_MODULE, -+#if 0 -+ .dev_attrs = ddb_attrs, -+#endif -+ .devnode = ddb_devnode, - }; +-}; ++ dev->handler_data[11] = (unsigned long) link; ++ dev->handler[11] = gtl_irq_handler; ++ ++ pr_info("GTL %s\n", dev->link[l].info->name); ++ pr_info("GTL HW %08x REGMAP %08x\n", ++ ddbreadl(dev, DDB_LINK_TAG(l) | 0), ++ ddbreadl(dev, DDB_LINK_TAG(l) | 4)); ++ pr_info("GTL ID %08x\n", ++ ddbreadl(dev, DDB_LINK_TAG(l) | 8)); ++ ++ tasklet_init(&link->tasklet, link_tasklet, (unsigned long) link); ++ ddbwritel(dev, 0xffffffff, DDB_LINK_TAG(l) | INTERRUPT_ACK); ++ ddbwritel(dev, 0xf, DDB_LINK_TAG(l) | INTERRUPT_ENABLE); -static __init int module_init_ddbridge(void) -+static int ddb_class_create(void) - { -- int ret; -+ ddb_major = register_chrdev(0, DDB_NAME, &ddb_fops); -+ if (ddb_major < 0) -+ return ddb_major; -+ if (class_register(&ddb_class) < 0) -+ return -1; + return 0; +} + -+static void ddb_class_destroy(void) -+{ -+ class_unregister(&ddb_class); -+ unregister_chrdev(ddb_major, DDB_NAME); -+} ++static int ddb_gtl_init(struct ddb *dev) + { +- int ret; ++ u32 l; - printk(KERN_INFO "Digital Devices PCIE bridge driver, " - "Copyright (C) 2010-11 Digital Devices GmbH\n"); -+static void ddb_device_attrs_del(struct ddb *dev) -+{ -+ int i; ++ dev->handler_data[10] = (unsigned long) dev; ++ dev->handler[10] = gtl_link_handler; - ret = ddb_class_create(); - if (ret < 0) @@ -27155,107 +23752,101 @@ index 9e3492e..c2fc010 100644 - if (ret < 0) - ddb_class_destroy(); - return ret; -+ for (i = 0; i < dev->info->temp_num; i++) -+ device_remove_file(dev->ddb_dev, &ddb_attrs_temp[i]); -+ for (i = 0; i < dev->info->port_num; i++) -+ device_remove_file(dev->ddb_dev, &ddb_attrs_mod[i]); -+ for (i = 0; i < dev->info->fan_num; i++) -+ device_remove_file(dev->ddb_dev, &ddb_attrs_fan[i]); -+ for (i = 0; i < dev->info->i2c_num; i++) { -+ if (dev->info->led_num) -+ device_remove_file(dev->ddb_dev, &ddb_attrs_led[i]); -+ device_remove_file(dev->ddb_dev, &ddb_attrs_snr[i]); -+ } -+ for (i = 0; ddb_attrs[i].attr.name; i++) -+ device_remove_file(dev->ddb_dev, &ddb_attrs[i]); ++ for (l = 1; l < dev->link[0].info->regmap->gtl->num + 1; l++) ++ ddb_gtl_init_link(dev, l); ++ return 0; } -static __exit void module_exit_ddbridge(void) -+static int ddb_device_attrs_add(struct ddb *dev) ++static int ddb_init_boards(struct ddb *dev) { - pci_unregister_driver(&ddb_pci_driver); - ddb_class_destroy(); -+ int i; ++ struct ddb_info *info; ++ u32 l; + -+ for (i = 0; ddb_attrs[i].attr.name; i++) -+ if (device_create_file(dev->ddb_dev, &ddb_attrs[i])) -+ goto fail; -+ for (i = 0; i < dev->info->temp_num; i++) -+ if (device_create_file(dev->ddb_dev, &ddb_attrs_temp[i])) -+ goto fail; -+ for (i = 0; i < dev->info->port_num; i++) -+ if (device_create_file(dev->ddb_dev, &ddb_attrs_mod[i])) -+ goto fail; -+ for (i = 0; i < dev->info->fan_num; i++) -+ if (device_create_file(dev->ddb_dev, &ddb_attrs_fan[i])) -+ goto fail; -+ for (i = 0; i < dev->info->i2c_num; i++) { -+ if (device_create_file(dev->ddb_dev, &ddb_attrs_snr[i])) -+ goto fail; -+ if (dev->info->led_num) -+ if (device_create_file(dev->ddb_dev, -+ &ddb_attrs_led[i])) -+ goto fail; ++ for (l = 0; l < DDB_MAX_LINK; l++) { ++ info = dev->link[l].info; ++ if (!info) ++ continue; ++ if (info->board_control) { ++ ddbwritel(dev, 0, DDB_LINK_TAG(l) | BOARD_CONTROL); ++ msleep(100); ++ ddbwritel(dev, info->board_control_2, ++ DDB_LINK_TAG(l) | BOARD_CONTROL); ++ usleep_range(2000, 3000); ++ ddbwritel(dev, ++ info->board_control_2 | info->board_control, ++ DDB_LINK_TAG(l) | BOARD_CONTROL); ++ usleep_range(2000, 3000); ++ } + } + return 0; -+fail: -+ return -1; } -module_init(module_init_ddbridge); -module_exit(module_exit_ddbridge); -+static int ddb_device_create(struct ddb *dev) ++static int ddb_init(struct ddb *dev) +{ -+ int res = 0; -+ -+ if (ddb_num == DDB_MAX_ADAPTER) -+ return -ENOMEM; -+ mutex_lock(&ddb_mutex); -+ dev->nr = ddb_num; -+ ddbs[dev->nr] = dev; -+ dev->ddb_dev = device_create(&ddb_class, dev->dev, -+ MKDEV(ddb_major, dev->nr), -+ dev, "ddbridge%d", dev->nr); -+ if (IS_ERR(dev->ddb_dev)) { -+ res = PTR_ERR(dev->ddb_dev); -+ pr_info("Could not create ddbridge%d\n", dev->nr); -+ goto fail; ++ if (dev->link[0].info->ns_num) { ++ ddbwritel(dev, 1, ETHER_CONTROL); ++ dev->vlan = vlan; ++ ddbwritel(dev, 14 + (dev->vlan ? 4 : 0), ETHER_LENGTH); + } -+ res = ddb_device_attrs_add(dev); -+ if (res) { -+ ddb_device_attrs_del(dev); -+ device_destroy(&ddb_class, MKDEV(ddb_major, dev->nr)); -+ ddbs[dev->nr] = 0; -+ dev->ddb_dev = ERR_PTR(-ENODEV); -+ } else -+ ddb_num++; -+fail: -+ mutex_unlock(&ddb_mutex); -+ return res; -+} ++ ++ mutex_init(&dev->link[0].lnb.lock); ++ mutex_init(&dev->link[0].flash_mutex); ++ ++ if (dev->link[0].info->regmap->gtl) ++ ddb_gtl_init(dev); ++ ++ ddb_init_boards(dev); ++ ++ if (ddb_i2c_init(dev) < 0) ++ goto fail; ++ ddb_ports_init(dev); ++ if (ddb_buffers_alloc(dev) < 0) { ++ pr_info(": Could not allocate buffer memory\n"); ++ goto fail2; ++ } ++ ddb_ports_attach(dev); ++ ++ ddb_nsd_attach(dev); ++ ++ ddb_device_create(dev); ++ ++ if (dev->link[0].info->fan_num) { ++ ddbwritel(dev, 1, GPIO_DIRECTION); ++ ddbwritel(dev, 1, GPIO_OUTPUT); ++ } ++ if (dev->link[0].info->type == DDB_MOD) ++ ddbridge_mod_init(dev); ++ return 0; -MODULE_DESCRIPTION("Digital Devices PCIe Bridge"); -MODULE_AUTHOR("Ralph Metzler"); -MODULE_LICENSE("GPL"); -MODULE_VERSION("0.5"); -+static void ddb_device_destroy(struct ddb *dev) -+{ -+ if (IS_ERR(dev->ddb_dev)) -+ return; -+ ddb_device_attrs_del(dev); -+ device_destroy(&ddb_class, MKDEV(ddb_major, dev->nr)); ++fail2: ++ pr_err("fail2\n"); ++ ddb_buffers_free(dev); ++ ddb_i2c_release(dev); ++fail: ++ pr_err("fail1\n"); ++ return -1; +} diff --git a/drivers/media/pci/ddbridge/ddbridge-i2c.c b/drivers/media/pci/ddbridge/ddbridge-i2c.c new file mode 100644 -index 0000000..bd0d9b1 +index 0000000..1e2e1da --- /dev/null +++ b/drivers/media/pci/ddbridge/ddbridge-i2c.c -@@ -0,0 +1,257 @@ +@@ -0,0 +1,290 @@ +/* + * ddbridge-i2c.c: Digital Devices bridge i2c driver + * -+ * Copyright (C) 2010-2014 Digital Devices GmbH -+ * Ralph Metzler ++ * Copyright (C) 2010-2015 Digital Devices GmbH ++ * Ralph Metzler ++ * Marcus Metzler + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License @@ -27275,6 +23866,16 @@ index 0000000..bd0d9b1 + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + ++static int i2c_io(struct i2c_adapter *adapter, u8 adr, ++ u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) ++{ ++ struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, ++ .buf = wbuf, .len = wlen }, ++ {.addr = adr, .flags = I2C_M_RD, ++ .buf = rbuf, .len = rlen } }; ++ return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; ++} ++ +static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) +{ + struct i2c_msg msg = {.addr = adr, .flags = 0, @@ -27350,24 +23951,39 @@ index 0000000..bd0d9b1 +static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) +{ + struct ddb *dev = i2c->dev; -+ int stat; ++ unsigned long stat; + u32 val; + + ddbwritel(dev, (adr << 9) | cmd, i2c->regs + I2C_COMMAND); + stat = wait_for_completion_timeout(&i2c->completion, HZ); -+ if (stat <= 0) { -+ pr_err("DDBridge I2C timeout, card %d, port %d\n", -+ dev->nr, i2c->nr); -+#ifdef CONFIG_PCI_MSI -+ { /* MSI debugging*/ ++ val = ddbreadl(dev, i2c->regs + I2C_COMMAND); ++ if (stat == 0) { ++ pr_err("DDBridge I2C timeout, card %d, port %d, link %u\n", ++ dev->nr, i2c->nr, i2c->link); ++ { + u32 istat = ddbreadl(dev, INTERRUPT_STATUS); ++ + dev_err(dev->dev, "DDBridge IRS %08x\n", istat); -+ ddbwritel(dev, istat, INTERRUPT_ACK); ++ if (i2c->link) { ++ u32 listat = ddbreadl(dev, ++ DDB_LINK_TAG(i2c->link) | ++ INTERRUPT_STATUS); ++ ++ dev_err(dev->dev, "DDBridge link %u IRS %08x\n", ++ i2c->link, listat); ++ } ++ if (istat & 1) { ++ ddbwritel(dev, istat & 1, INTERRUPT_ACK); ++ } else { ++ u32 mon = ddbreadl(dev, ++ i2c->regs + I2C_MONITOR); ++ ++ dev_err(dev->dev, "I2C cmd=%08x mon=%08x\n", ++ val, mon); ++ } + } -+#endif + return -EIO; + } -+ val = ddbreadl(dev, i2c->regs + I2C_COMMAND); + if (val & 0x70000) + return -EIO; + return 0; @@ -27380,25 +23996,27 @@ index 0000000..bd0d9b1 + struct ddb *dev = i2c->dev; + u8 addr = 0; + -+ if (num) -+ addr = msg[0].addr; ++ if (num != 1 && num != 2) ++ return -EIO; ++ addr = msg[0].addr; ++ if (msg[0].len > i2c->bsize) ++ return -EIO; + if (num == 2 && msg[1].flags & I2C_M_RD && + !(msg[0].flags & I2C_M_RD)) { -+ memcpy_toio(dev->regs + I2C_TASKMEM_BASE + i2c->wbuf, -+ msg[0].buf, msg[0].len); -+ ddbwritel(dev, msg[0].len|(msg[1].len << 16), ++ if (msg[1].len > i2c->bsize) ++ return -EIO; ++ ddbcpyto(dev, i2c->wbuf, msg[0].buf, msg[0].len); ++ ddbwritel(dev, msg[0].len | (msg[1].len << 16), + i2c->regs + I2C_TASKLENGTH); + if (!ddb_i2c_cmd(i2c, addr, 1)) { -+ memcpy_fromio(msg[1].buf, -+ dev->regs + I2C_TASKMEM_BASE + -+ i2c->rbuf, -+ msg[1].len); ++ ddbcpyfrom(dev, msg[1].buf, ++ i2c->rbuf, ++ msg[1].len); + return num; + } + } + if (num == 1 && !(msg[0].flags & I2C_M_RD)) { -+ ddbcpyto(dev, I2C_TASKMEM_BASE + i2c->wbuf, -+ msg[0].buf, msg[0].len); ++ ddbcpyto(dev, i2c->wbuf, msg[0].buf, msg[0].len); + ddbwritel(dev, msg[0].len, i2c->regs + I2C_TASKLENGTH); + if (!ddb_i2c_cmd(i2c, addr, 2)) + return num; @@ -27407,34 +24025,16 @@ index 0000000..bd0d9b1 + ddbwritel(dev, msg[0].len << 16, i2c->regs + I2C_TASKLENGTH); + if (!ddb_i2c_cmd(i2c, addr, 3)) { + ddbcpyfrom(dev, msg[0].buf, -+ I2C_TASKMEM_BASE + i2c->rbuf, msg[0].len); ++ i2c->rbuf, msg[0].len); + return num; + } + } + return -EIO; +} + -+#if 0 -+static int ddb_i2c_master_xfer(struct i2c_adapter *adapter, -+ struct i2c_msg msg[], int num) -+{ -+ struct ddb_i2c *i2c = (struct ddb_i2c *) i2c_get_adapdata(adapter); -+ struct ddb *dev = i2c->dev; -+ int ret; -+ -+ if (dev->info->type != DDB_OCTONET || i2c->nr == 0 || i2c->nr == 3) -+ return ddb_i2c_master_xfer_locked(adapter, msg, num); -+ -+ mutex_lock(&dev->octonet_i2c_lock); -+ ret = ddb_i2c_master_xfer_locked(adapter, msg, num); -+ mutex_unlock(&dev->octonet_i2c_lock); -+ return ret; -+} -+#endif -+ +static u32 ddb_i2c_functionality(struct i2c_adapter *adap) +{ -+ return I2C_FUNC_SMBUS_EMUL; ++ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +struct i2c_algorithm ddb_i2c_algo = { @@ -27446,12 +24046,10 @@ index 0000000..bd0d9b1 +{ + int i; + struct ddb_i2c *i2c; -+ struct i2c_adapter *adap; + -+ for (i = 0; i < dev->info->i2c_num; i++) { ++ for (i = 0; i < dev->i2c_num; i++) { + i2c = &dev->i2c[i]; -+ adap = &i2c->adap; -+ i2c_del_adapter(adap); ++ i2c_del_adapter(&i2c->adap); + } +} + @@ -27462,63 +24060,89 @@ index 0000000..bd0d9b1 + complete(&i2c->completion); +} + -+static int ddb_i2c_init(struct ddb *dev) ++static int ddb_i2c_add(struct ddb *dev, struct ddb_i2c *i2c, ++ struct ddb_regmap *regmap, int link, int i, int num) +{ -+ int i, j, stat = 0; -+ struct ddb_i2c *i2c; + struct i2c_adapter *adap; + -+ for (i = 0; i < dev->info->i2c_num; i++) { -+ i2c = &dev->i2c[i]; -+ dev->handler[i] = i2c_handler; -+ dev->handler_data[i] = (unsigned long) i2c; -+ i2c->dev = dev; -+ i2c->nr = i; -+ i2c->wbuf = i * (I2C_TASKMEM_SIZE / 4); -+ i2c->rbuf = i2c->wbuf + (I2C_TASKMEM_SIZE / 8); -+ i2c->regs = 0x80 + i * 0x20; -+ ddbwritel(dev, I2C_SPEED_100, i2c->regs + I2C_TIMING); -+ ddbwritel(dev, (i2c->rbuf << 16) | i2c->wbuf, -+ i2c->regs + I2C_TASKADDRESS); -+ init_completion(&i2c->completion); ++ i2c->nr = i; ++ i2c->dev = dev; ++ i2c->link = link; ++ i2c->bsize = regmap->i2c_buf->size; ++ i2c->wbuf = DDB_LINK_TAG(link) | ++ (regmap->i2c_buf->base + i2c->bsize * i); ++ i2c->rbuf = i2c->wbuf; /* + i2c->bsize / 2 */ ++ i2c->regs = DDB_LINK_TAG(link) | ++ (regmap->i2c->base + regmap->i2c->size * i); ++ ddbwritel(dev, I2C_SPEED_100, i2c->regs + I2C_TIMING); ++ ddbwritel(dev, ((i2c->rbuf & 0xffff) << 16) | (i2c->wbuf & 0xffff), ++ i2c->regs + I2C_TASKADDRESS); ++ init_completion(&i2c->completion); + -+ adap = &i2c->adap; -+ i2c_set_adapdata(adap, i2c); ++ adap = &i2c->adap; ++ i2c_set_adapdata(adap, i2c); +#ifdef I2C_ADAP_CLASS_TV_DIGITAL -+ adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG; ++ adap->class = I2C_ADAP_CLASS_TV_DIGITAL|I2C_CLASS_TV_ANALOG; +#else +#ifdef I2C_CLASS_TV_ANALOG -+ adap->class = I2C_CLASS_TV_ANALOG; ++ adap->class = I2C_CLASS_TV_ANALOG; +#endif +#endif -+ strcpy(adap->name, "ddbridge"); -+ adap->algo = &ddb_i2c_algo; -+ adap->algo_data = (void *)i2c; -+ adap->dev.parent = dev->dev; -+ stat = i2c_add_adapter(adap); -+ if (stat) -+ break; ++ strcpy(adap->name, "ddbridge"); ++ adap->algo = &ddb_i2c_algo; ++ adap->algo_data = (void *)i2c; ++ adap->dev.parent = dev->dev; ++ return i2c_add_adapter(adap); ++} ++ ++static int ddb_i2c_init(struct ddb *dev) ++{ ++ int stat = 0; ++ u32 i, j, num = 0, l; ++ struct ddb_i2c *i2c; ++ struct i2c_adapter *adap; ++ struct ddb_regmap *regmap; ++ ++ for (l = 0; l < DDB_MAX_LINK; l++) { ++ if (!dev->link[l].info) ++ continue; ++ regmap = dev->link[l].info->regmap; ++ if (!regmap || !regmap->i2c) ++ continue; ++ for (i = 0; i < regmap->i2c->num; i++) { ++ if (!(dev->link[l].info->i2c_mask & (1 << i))) ++ continue; ++ i2c = &dev->i2c[num]; ++ dev->handler_data[i + l * 32] = (unsigned long) i2c; ++ dev->handler[i + l * 32] = i2c_handler; ++ stat = ddb_i2c_add(dev, i2c, regmap, l, i, num); ++ if (stat) ++ break; ++ num++; ++ } + } -+ if (stat) -+ for (j = 0; j < i; j++) { ++ if (stat) { ++ for (j = 0; j < num; j++) { + i2c = &dev->i2c[j]; + adap = &i2c->adap; + i2c_del_adapter(adap); + } ++ } else ++ dev->i2c_num = num; + return stat; +} -+ diff --git a/drivers/media/pci/ddbridge/ddbridge-i2c.h b/drivers/media/pci/ddbridge/ddbridge-i2c.h new file mode 100644 -index 0000000..4a9bc26 +index 0000000..c20a2ba --- /dev/null +++ b/drivers/media/pci/ddbridge/ddbridge-i2c.h -@@ -0,0 +1,105 @@ +@@ -0,0 +1,116 @@ +/* + * ddbridge-i2c.h: Digital Devices bridge i2c driver + * -+ * Copyright (C) 2010-2014 Digital Devices GmbH -+ * Ralph Metzler ++ * Copyright (C) 2010-2015 Digital Devices GmbH ++ * Marcus Metzler ++ * Ralph Metzler + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License @@ -27544,6 +24168,16 @@ index 0000000..4a9bc26 +#include +#include + ++static inline int i2c_io(struct i2c_adapter *adapter, u8 adr, ++ u8 *wbuf, u32 wlen, u8 *rbuf, u32 rlen) ++{ ++ struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, ++ .buf = wbuf, .len = wlen }, ++ {.addr = adr, .flags = I2C_M_RD, ++ .buf = rbuf, .len = rlen } }; ++ return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; ++} ++ +static inline int i2c_write(struct i2c_adapter *adap, u8 adr, + u8 *data, int len) +{ @@ -27621,16 +24255,16 @@ index 0000000..4a9bc26 +#endif diff --git a/drivers/media/pci/ddbridge/ddbridge-mod.c b/drivers/media/pci/ddbridge/ddbridge-mod.c new file mode 100644 -index 0000000..5a9c866 +index 0000000..fa1e92f --- /dev/null +++ b/drivers/media/pci/ddbridge/ddbridge-mod.c -@@ -0,0 +1,1148 @@ +@@ -0,0 +1,1118 @@ +/* + * ddbridge.c: Digital Devices PCIe bridge driver + * -+ * Copyright (C) 2010-2014 Digital Devices GmbH -+ * Ralph Metzler -+ * Marcus Metzler ++ * Copyright (C) 2010-2015 Digital Devices GmbH ++ * Marcus Metzler ++ * Ralph Metzler + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License @@ -27683,12 +24317,14 @@ index 0000000..5a9c866 +inline s64 RoundPCR(s64 a) +{ + s64 b = a + (HW_LSB_MASK>>1); ++ + return b & ~(HW_LSB_MASK - 1); +} + +inline s64 RoundPCRUp(s64 a) +{ + s64 b = a + (HW_LSB_MASK - 1); ++ + return b & ~(HW_LSB_MASK - 1); +} + @@ -27719,12 +24355,6 @@ index 0000000..5a9c866 + mod->State = CM_IDLE; + mod->Control = 0; + ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr)); -+#if 0 -+ udelay(10); -+ ddbwritel(dev, CHANNEL_CONTROL_RESET, CHANNEL_CONTROL(output->nr)); -+ udelay(10); -+ ddbwritel(dev, 0, CHANNEL_CONTROL(output->nr)); -+#endif + mod_busy(dev, output->nr); + pr_info("mod_output_stop %d.%d\n", dev->nr, output->nr); +} @@ -27992,6 +24622,7 @@ index 0000000..5a9c866 + HSDiv = Div; + } else { + int retry = 100; ++ + while (retry > 0) { + N = 0; + HSDiv = Div; @@ -28090,27 +24721,6 @@ index 0000000..5a9c866 + return 0; +} + -+#if 0 -+static void mod_peak(struct ddb *dev, u32 Time, s16 *pIPeak, s16 *pQPeak) -+{ -+ u32 val; -+ -+ val = ddbreadl(dev, IQOUTPUT_CONTROL); -+ val &= ~(IQOUTPUT_CONTROL_ENABLE_PEAK | IQOUTPUT_CONTROL_RESET_PEAK); -+ ddbwritel(dev, val, IQOUTPUT_CONTROL); -+ ddbwritel(dev, val | IQOUTPUT_CONTROL_RESET_PEAK, IQOUTPUT_CONTROL); -+ msleep(20); -+ ddbwritel(dev, val, IQOUTPUT_CONTROL); -+ ddbwritel(dev, val | IQOUTPUT_CONTROL_ENABLE_PEAK, IQOUTPUT_CONTROL); -+ msleep(Time); -+ ddbwritel(dev, val, IQOUTPUT_CONTROL); -+ val = ddbreadl(dev, IQOUTPUT_PEAK_DETECTOR); -+ -+ *pIPeak = val & 0xffff; -+ *pQPeak = (val >> 16) & 0xffff; -+} -+#endif -+ +static int mod_init_dac_input(struct ddb *dev) +{ + u8 Set = 0; @@ -28167,11 +24777,6 @@ index 0000000..5a9c866 + + Seek = 1; + for (Sample = 0; Sample < 32; Sample += 1) { -+ /* printk(" %2d: %d %2d %2d\n", -+ Sample, SeekTable[Sample], SetTable[Sample], -+ HldTable[Sample]); -+ */ -+ + if (Sample1 == 0xFF && SeekTable[Sample] == 1 && Seek == 0) + Sample1 = Sample; + if (Sample1 != 0xFF && Sample2 == 0xFF && @@ -28329,7 +24934,7 @@ index 0000000..5a9c866 + u32 s1 = 22, s2 = 33; + u64 amp = (1ULL << 17) - 1ULL; + u64 s = 0, c = (amp << s1), ss; -+ u64 frq = 0xC90FDAA22168C234ULL; ++ u64 frq = 0xC90FDAA22168C235ULL; /* PI << 62 */ + u32 *iqtab; + u32 iqtabadr; + u32 regval; @@ -28344,8 +24949,7 @@ index 0000000..5a9c866 + if (!(i & (fac - 1))) { + j = i / fac; + ss = s >> s1; -+ /*round? ss = ((s >> (s1 - 1)) + 1) >> 1; */ -+ ++ /* round? ss = ((s >> (s1 - 1)) + 1) >> 1; */ + iqtab[j] = iqtab[steps / 2 - j] = ss; + iqtab[steps / 2 + j] = iqtab[steps - j] = -ss; + } @@ -28384,7 +24988,7 @@ index 0000000..5a9c866 + if (mod > QAM_256 || mod < QAM_16) + return -EINVAL; + dev->mod[chan].modulation = mod; -+ dev->mod[chan].obitrate = 0x0061072787900000 * (mod + 3); ++ dev->mod[chan].obitrate = 0x0061072787900000ULL * (mod + 3); + dev->mod[chan].ibitrate = dev->mod[chan].obitrate; + ddbwritel(dev, qamtab[mod], CHANNEL_SETTINGS(chan)); + return 0; @@ -28446,7 +25050,7 @@ index 0000000..5a9c866 + return -ENOMEM; + flash = (struct DDMOD_FLASH *) buffer; + -+ ddbridge_flashread(dev, buffer, DDMOD_FLASH_START, 4096); ++ ddbridge_flashread(dev, 0, buffer, DDMOD_FLASH_START, 4096); + + if (flash->Magic != DDMOD_FLASH_MAGIC && flash->Magic != 1) { + stat = -EINVAL; @@ -28521,11 +25125,10 @@ index 0000000..5a9c866 +#define FACTOR (1ULL << 22) + +/* -+ double Increment = FACTOR*PACKET_CLOCKS/double(m_OutputBitrate); -+ double Decrement = FACTOR*PACKET_CLOCKS/double(m_InputBitrate); -+ -+ 27000000 * 1504 * 2^22 / (6900000 * 188 / 204) = 26785190066.1 -+*/ ++ * double Increment = FACTOR*PACKET_CLOCKS/double(m_OutputBitrate); ++ * double Decrement = FACTOR*PACKET_CLOCKS/double(m_InputBitrate); ++ * 27000000 * 1504 * 2^22 / (6900000 * 188 / 204) = 26785190066.1 ++ */ + +void ddbridge_mod_rate_handler(unsigned long data) +{ @@ -28585,12 +25188,13 @@ index 0000000..5a9c866 + if (mod->StateCounter) { + if (mod->StateCounter == 1) { + if (mod->ibitrate == 0) { -+ mul = (0x1000000 * (u64) (OutPacketDiff - -+ InPacketDiff - -+ InPacketDiff/1000)); ++ mul = (0x1000000 * ++ (u64) (OutPacketDiff - ++ InPacketDiff - ++ InPacketDiff/1000)); + if (OutPacketDiff) -+ mod->rate_inc = -+ div_u64(mul, OutPacketDiff); ++ mod->rate_inc = div_u64(mul, ++ OutPacketDiff); + else + mod->rate_inc = 0; + mod_set_rateinc(dev, output->nr); @@ -28598,10 +25202,10 @@ index 0000000..5a9c866 + div_u64(26785190066ULL, + mod->modulation + 3); + if (InPacketDiff) -+ mod->PCRDecrement = -+ div_u64(mod->PCRIncrement * -+ (u64) OutPacketDiff, -+ InPacketDiff); ++ mod->PCRDecrement = div_u64( ++ mod->PCRIncrement * ++ (u64) OutPacketDiff, ++ InPacketDiff); + else + mod->PCRDecrement = 0; + mod_set_incs(output); @@ -28775,15 +25379,16 @@ index 0000000..5a9c866 +} diff --git a/drivers/media/pci/ddbridge/ddbridge-ns.c b/drivers/media/pci/ddbridge/ddbridge-ns.c new file mode 100644 -index 0000000..9d86cba +index 0000000..7b6d659 --- /dev/null +++ b/drivers/media/pci/ddbridge/ddbridge-ns.c -@@ -0,0 +1,489 @@ +@@ -0,0 +1,491 @@ +/* + * ddbridge-ns.c: Digital Devices PCIe bridge driver net streaming + * -+ * Copyright (C) 2010-2014 Digital Devices GmbH -+ * Ralph Metzler ++ * Copyright (C) 2010-2015 Marcus Metzler ++ * Ralph Metzler ++ * Digital Devices GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License @@ -28803,8 +25408,8 @@ index 0000000..9d86cba + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + -+static int ddb_dvb_input_start(struct ddb_input *input); -+static int ddb_dvb_input_stop(struct ddb_input *input); ++static int ddb_dvb_ns_input_start(struct ddb_input *input); ++static int ddb_dvb_ns_input_stop(struct ddb_input *input); + +static u16 calc_pcs(struct dvb_ns_params *p) +{ @@ -28864,7 +25469,7 @@ index 0000000..9d86cba + if (dev->ns[i].input) + continue; + dev->ns[i].input = input; -+ dev->ns[i].fe = input->nr; ++ dev->ns[i].fe = input; + nss->priv = &dev->ns[i]; + ret = 0; + /*pr_info("%s i=%d fe=%d\n", __func__, i, input->nr); */ @@ -28882,7 +25487,7 @@ index 0000000..9d86cba + struct ddb *dev = input->port->dev; + struct ddb_ns *dns = (struct ddb_ns *) nss->priv; + -+ if (dev->ids.devid == 0x0301dd01) { ++ if (dev->link[0].ids.devid == 0x0301dd01) { + u32 sys = 0; + int pid, j = 1; + @@ -28913,8 +25518,7 @@ index 0000000..9d86cba + u8 bit = 1 << (pid & 7); + u32 off = STREAM_PIDS(dns->nr); + -+#if 1 -+ if (dev->ids.devid == 0x0301dd01) { ++ if (dev->link[0].ids.devid == 0x0301dd01) { + if (pid & 0x2000) { + if (pid & 0x8000) + memset(nss->pids, 0xff, 0x400); @@ -28935,15 +25539,13 @@ index 0000000..9d86cba + ddbmemset(dev, off, 0x00, 0x400); + } else { + u8 val = ddbreadb(dev, off + byte); ++ + if (pid & 0x8000) + ddbwriteb(dev, val | bit, off + byte); + else + ddbwriteb(dev, val & ~bit, off + byte); + } + } -+#else -+ ddbcpyto(dev, STREAM_PIDS(dns->nr), nss->pids, 0x400); -+#endif + return 0; +} + @@ -28951,7 +25553,7 @@ index 0000000..9d86cba +{ + int i, j; + -+ for (i = j = 0; i < dev->info->port_num; i++) { ++ for (i = j = 0; i < dev->link[0].info->port_num; i++) { + if (dev->port[i].class == DDB_PORT_CI) { + if (j == ci) + return i; @@ -28970,17 +25572,21 @@ index 0000000..9d86cba + int ciport; + + if (ci == 255) { -+ dns->fe = input->nr; ++ dns->fe = input; + return 0; + } + ciport = citoport(dev, ci); + if (ciport < 0) + return -EINVAL; -+ pr_info("input %d to ci %d at port %d\n", input->nr, ci, ciport); -+ ddbwritel(dev, (input->nr << 16) | 0x1c, TS_OUTPUT_CONTROL(ciport)); ++ ++ pr_info("input %d.%d to ci %d at port %d\n", input->port->lnr, ++ input->nr, ci, ciport); ++ ddbwritel(dev, (input->port->lnr << 21) | (input->nr << 16) | 0x1c, ++ TS_OUTPUT_CONTROL(ciport)); + usleep_range(1, 5); -+ ddbwritel(dev, (input->nr << 16) | 0x1d, TS_OUTPUT_CONTROL(ciport)); -+ dns->fe = ciport * 2; ++ ddbwritel(dev, (input->port->lnr << 21) | (input->nr << 16) | 0x1d, ++ TS_OUTPUT_CONTROL(ciport)); ++ dns->fe = dev->port[ciport].input[0]; + return 0; +} + @@ -29039,6 +25645,7 @@ index 0000000..9d86cba + dns->p[coff + dns->rtcp_len - 1] = (len & 0xff); + if (len & 3) { + u32 pad = 4 - (len & 3); ++ + memset(dns->p + coff + dns->rtcp_len + len, 0, pad); + len += pad; + } @@ -29055,7 +25662,8 @@ index 0000000..9d86cba + return 0; +} + -+static u32 set_nsbuf(struct dvb_ns_params *p, u8 *buf, u32 *udplen, int rtcp) ++static u32 set_nsbuf(struct dvb_ns_params *p, u8 *buf, ++ u32 *udplen, int rtcp, int vlan) +{ + u32 c = 0; + u16 pcs; @@ -29187,10 +25795,10 @@ index 0000000..9d86cba + u32 off = STREAM_PACKET_ADR(dns->nr); + u32 coff = 96; + -+ dns->ts_offset = set_nsbuf(p, dns->p, &dns->udplen, 0); ++ dns->ts_offset = set_nsbuf(p, dns->p, &dns->udplen, 0, dev->vlan); + if (nss->params.flags & DVB_NS_RTCP) + dns->rtcp_len = set_nsbuf(p, dns->p + coff, -+ &dns->rtcp_udplen, 1); ++ &dns->rtcp_udplen, 1, dev->vlan); + ddbcpyto(dev, off, dns->p, sizeof(dns->p)); + ddbwritel(dev, dns->udplen | (STREAM_PACKET_OFF(dns->nr) << 16), + STREAM_RTP_PACKET(dns->nr)); @@ -29208,7 +25816,6 @@ index 0000000..9d86cba + struct ddb *dev = input->port->dev; + u32 reg = 0x8003; + -+ + if (nss->params.flags & DVB_NS_RTCP) + reg |= 0x10; + if (nss->params.flags & DVB_NS_RTP_TO) @@ -29217,10 +25824,13 @@ index 0000000..9d86cba + reg |= 0x40; + if (nss->params.flags & DVB_NS_IPV6) + reg |= 0x80; -+ if (dns->fe != input->nr) -+ ddb_dvb_input_start(&dev->input[dns->fe]); -+ ddb_dvb_input_start(input); -+ ddbwritel(dev, reg | (dns->fe << 8), STREAM_CONTROL(dns->nr)); ++ if (dns->fe != input) ++ ddb_dvb_ns_input_start(dns->fe); ++ ddb_dvb_ns_input_start(input); ++ pr_info("ns start ns %u, fe %u link %u\n", ++ dns->nr, dns->fe->nr, dns->fe->port->lnr); ++ ddbwritel(dev, reg | (dns->fe->nr << 8) | (dns->fe->port->lnr << 16), ++ STREAM_CONTROL(dns->nr)); + return 0; +} + @@ -29232,9 +25842,9 @@ index 0000000..9d86cba + struct ddb *dev = input->port->dev; + + ddbwritel(dev, 0x00, STREAM_CONTROL(dns->nr)); -+ ddb_dvb_input_stop(input); -+ if (dns->fe != input->nr) -+ ddb_dvb_input_stop(&dev->input[dns->fe]); ++ ddb_dvb_ns_input_stop(input); ++ if (dns->fe != input) ++ ddb_dvb_ns_input_stop(dns->fe); + return 0; +} + @@ -29247,10 +25857,6 @@ index 0000000..9d86cba + int i, res; + + ddbmemset(dev, STREAM_PIDS(input->nr), 0x00, 0x400); -+ if (dev->ids.devid == 0x0301dd01) -+ dev->ns_num = 15; -+ else -+ dev->ns_num = 12; + for (i = 0; i < dev->ns_num; i++) + dev->ns[i].nr = i; + ns->priv = input; @@ -29269,7 +25875,7 @@ index 0000000..9d86cba + return res; +} diff --git a/drivers/media/pci/ddbridge/ddbridge-regs.h b/drivers/media/pci/ddbridge/ddbridge-regs.h -index a3ccb31..eca8574 100644 +index a3ccb31..596f322 100644 --- a/drivers/media/pci/ddbridge/ddbridge-regs.h +++ b/drivers/media/pci/ddbridge/ddbridge-regs.h @@ -1,7 +1,7 @@ @@ -29277,7 +25883,7 @@ index a3ccb31..eca8574 100644 * ddbridge-regs.h: Digital Devices PCIe bridge driver * - * Copyright (C) 2010-2011 Digital Devices GmbH -+ * Copyright (C) 2010-2014 Digital Devices GmbH ++ * Copyright (C) 2010-2015 Digital Devices GmbH * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -29315,18 +25921,18 @@ index a3ccb31..eca8574 100644 +#define MDIO_VAL 0x2C + +/* ------------------------------------------------------------------------- */ ++ ++#define BOARD_CONTROL 0x30 ++ ++/* ------------------------------------------------------------------------- */ -/* Interrupt controller */ -/* How many MSI's are available depends on HW (Min 2 max 8) */ -/* How many are usable also depends on Host platform */ -+#define BOARD_CONTROL 0x30 -+ -+/* ------------------------------------------------------------------------- */ -+ +/* Interrupt controller -+ How many MSI's are available depends on HW (Min 2 max 8) -+ How many are usable also depends on Host platform -+*/ ++ * How many MSI's are available depends on HW (Min 2 max 8) ++ * How many are usable also depends on Host platform ++ */ #define INTERRUPT_BASE (0x40) @@ -29340,10 +25946,13 @@ index a3ccb31..eca8574 100644 #define INTMASK_I2C1 (0x00000001) #define INTMASK_I2C2 (0x00000002) #define INTMASK_I2C3 (0x00000004) -@@ -81,6 +104,32 @@ +@@ -81,6 +104,35 @@ #define INTMASK_TSOUTPUT3 (0x00040000) #define INTMASK_TSOUTPUT4 (0x00080000) ++ ++ ++/* Modulator registers */ + +/* Clock Generator ( Sil598 @ 0xAA I2c ) */ +#define CLOCKGEN_BASE (0x80) @@ -29373,7 +25982,7 @@ index a3ccb31..eca8574 100644 /* ------------------------------------------------------------------------- */ /* I2C Master Controller */ -@@ -90,19 +139,14 @@ +@@ -90,19 +142,10 @@ #define I2C_TIMING (0x04) #define I2C_TASKLENGTH (0x08) /* High read, low write */ #define I2C_TASKADDRESS (0x0C) /* High read, low write */ @@ -29385,25 +25994,22 @@ index a3ccb31..eca8574 100644 -#define I2C_BASE_3 (I2C_BASE + 0x40) -#define I2C_BASE_4 (I2C_BASE + 0x60) - - #define I2C_BASE_N(i) (I2C_BASE + (i) * 0x20) - - #define I2C_TASKMEM_BASE (0x1000) /* Byte offset */ +-#define I2C_BASE_N(i) (I2C_BASE + (i) * 0x20) +- +-#define I2C_TASKMEM_BASE (0x1000) /* Byte offset */ -#define I2C_TASKMEM_SIZE (0x1000) -+#define I2C_TASKMEM_SIZE (0x0800) +#define I2C_SPEED_666 (0x02010202) #define I2C_SPEED_400 (0x04030404) #define I2C_SPEED_200 (0x09080909) #define I2C_SPEED_154 (0x0C0B0C0C) -@@ -117,35 +161,276 @@ +@@ -117,35 +160,273 @@ #define DMA_BASE_WRITE (0x100) #define DMA_BASE_READ (0x140) -#define DMA_CONTROL (0x00) /* 64 */ -#define DMA_ERROR (0x04) /* 65 ( only read instance ) */ -+#define DMA_CONTROL (0x00) -+#define DMA_ERROR (0x04) - +- -#define DMA_DIAG_CONTROL (0x1C) /* 71 */ -#define DMA_DIAG_PACKETCOUNTER_LOW (0x20) /* 72 */ -#define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) /* 73 */ @@ -29413,6 +26019,11 @@ index a3ccb31..eca8574 100644 -#define DMA_DIAG_WAITTIMEOUTINIT (0x34) /* 77 */ -#define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) /* 78 */ -#define DMA_DIAG_WAITCOUNTER (0x3C) /* 79 */ ++#define DMA_CONTROL (0x00) ++#define DMA_ERROR (0x04) + +-/* ------------------------------------------------------------------------- */ +-/* DMA Buffer */ +#define DMA_DIAG_CONTROL (0x1C) +#define DMA_DIAG_PACKETCOUNTER_LOW (0x20) +#define DMA_DIAG_PACKETCOUNTER_HIGH (0x24) @@ -29423,9 +26034,6 @@ index a3ccb31..eca8574 100644 +#define DMA_DIAG_WAITOVERFLOWCOUNTER (0x38) +#define DMA_DIAG_WAITCOUNTER (0x3C) - /* ------------------------------------------------------------------------- */ - /* DMA Buffer */ - #define TS_INPUT_BASE (0x200) -#define TS_INPUT_CONTROL(i) (TS_INPUT_BASE + (i) * 16 + 0x00) +#define TS_INPUT_CONTROL(i) (TS_INPUT_BASE + (i) * 0x10 + 0x00) @@ -29435,6 +26043,9 @@ index a3ccb31..eca8574 100644 -#define TS_OUTPUT_CONTROL(i) (TS_OUTPUT_BASE + (i) * 16 + 0x00) +#define TS_OUTPUT_CONTROL(i) (TS_OUTPUT_BASE + (i) * 0x10 + 0x00) +#define TS_OUTPUT_CONTROL2(i) (TS_OUTPUT_BASE + (i) * 0x10 + 0x04) ++ ++/* ------------------------------------------------------------------------- */ ++/* DMA Buffer */ #define DMA_BUFFER_BASE (0x300) @@ -29551,10 +26162,10 @@ index a3ccb31..eca8574 100644 + +#define RF_ATTENUATOR (0xD8) +/* 0x00 = 0 dB -+ 0x01 = 1 dB -+ ... -+ 0x1F = 31 dB -+*/ ++ * 0x01 = 1 dB ++ * ... ++ * 0x1F = 31 dB ++ */ + +#define RF_POWER (0xE0) +#define RF_POWER_BASE (0xE0) @@ -29568,8 +26179,8 @@ index a3ccb31..eca8574 100644 + + +/* -------------------------------------------------------------------------- -+ Output control -+*/ ++ * Output control ++ */ + +#define IQOUTPUT_BASE (0x240) +#define IQOUTPUT_CONTROL (IQOUTPUT_BASE + 0x00) @@ -29686,21 +26297,19 @@ index a3ccb31..eca8574 100644 +#define PID_FILTER_BASE (0x800) +#define PID_FILTER_SYSTEM_PIDS(i) (PID_FILTER_BASE + (i) * 0x20) +#define PID_FILTER_PID(i, j) (PID_FILTER_BASE + (i) * 0x20 + (j) * 4) -+ -+ -+ diff --git a/drivers/media/pci/ddbridge/ddbridge.c b/drivers/media/pci/ddbridge/ddbridge.c new file mode 100644 -index 0000000..9784f10 +index 0000000..b9d93f2 --- /dev/null +++ b/drivers/media/pci/ddbridge/ddbridge.c -@@ -0,0 +1,470 @@ +@@ -0,0 +1,541 @@ +/* + * ddbridge.c: Digital Devices PCIe bridge driver + * -+ * Copyright (C) 2010-2013 Digital Devices GmbH -+ * Ralph Metzler -+ * Marcus Metzler ++ * Copyright (C) 2010-2015 Digital Devices GmbH ++ * Ralph Metzler ++ * Marcus Metzler ++ * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License @@ -29735,10 +26344,19 @@ index 0000000..9784f10 + "0-one adapter per io, 1-one per tab with io, 2-one per tab, 3-one for all"); + +#ifdef CONFIG_PCI_MSI ++#define DDB_USE_MSI_IRQHANDLERS ++#ifdef CONFIG_DVB_DDBRIDGE_MSIENABLE +static int msi = 1; ++#else ++static int msi = 0; ++#endif +module_param(msi, int, 0444); +MODULE_PARM_DESC(msi, ++#ifdef CONFIG_DVB_DDBRIDGE_MSIENABLE + " Control MSI interrupts: 0-disable, 1-enable (default)"); ++#else ++ " Control MSI interrupts: 0-disable (default), 1-enable"); ++#endif +#endif + +#include "ddbridge-core.c" @@ -29755,14 +26373,19 @@ index 0000000..9784f10 +} + + -+static void __devexit ddb_remove(struct pci_dev *pdev) ++static void ddb_remove(struct pci_dev *pdev) +{ + struct ddb *dev = (struct ddb *) pci_get_drvdata(pdev); + ++ ddb_device_destroy(dev); ++ ddb_nsd_detach(dev); + ddb_ports_detach(dev); + ddb_i2c_release(dev); + ++ if (dev->link[0].info->ns_num) ++ ddbwritel(dev, 0, ETHER_CONTROL); + ddbwritel(dev, 0, INTERRUPT_ENABLE); ++ + ddbwritel(dev, 0, MSI1_ENABLE); + if (dev->msi == 2) + free_irq(dev->pdev->irq + 1, dev); @@ -29773,19 +26396,13 @@ index 0000000..9784f10 +#endif + ddb_ports_release(dev); + ddb_buffers_free(dev); -+ ddb_device_destroy(dev); + + ddb_unmap(dev); -+ pci_set_drvdata(pdev, 0); ++ pci_set_drvdata(pdev, NULL); + pci_disable_device(pdev); +} + -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) -+#define __devinit -+#define __devinitdata -+#endif -+ -+static int __devinit ddb_probe(struct pci_dev *pdev, ++static int ddb_probe(struct pci_dev *pdev, + const struct pci_device_id *id) +{ + struct ddb *dev; @@ -29799,22 +26416,25 @@ index 0000000..9784f10 + if (dev == NULL) + return -ENOMEM; + ++ mutex_init(&dev->mutex); + dev->has_dma = 1; + dev->pdev = pdev; + dev->dev = &pdev->dev; + pci_set_drvdata(pdev, dev); + -+ dev->ids.vendor = id->vendor; -+ dev->ids.device = id->device; -+ dev->ids.subvendor = id->subvendor; -+ dev->ids.subdevice = id->subdevice; ++ dev->link[0].ids.vendor = id->vendor; ++ dev->link[0].ids.device = id->device; ++ dev->link[0].ids.subvendor = id->subvendor; ++ dev->link[0].ids.subdevice = id->subdevice; + -+ dev->info = (struct ddb_info *) id->driver_data; -+ pr_info("DDBridge driver detected: %s\n", dev->info->name); ++ dev->link[0].dev = dev; ++ dev->link[0].info = (struct ddb_info *) id->driver_data; ++ pr_info("DDBridge driver detected: %s\n", dev->link[0].info->name); + + dev->regs_len = pci_resource_len(dev->pdev, 0); + dev->regs = ioremap(pci_resource_start(dev->pdev, 0), + pci_resource_len(dev->pdev, 0)); ++ + if (!dev->regs) { + pr_err("DDBridge: not enough memory for register map\n"); + stat = -ENOMEM; @@ -29826,12 +26446,20 @@ index 0000000..9784f10 + goto fail; + } + -+ dev->ids.hwid = ddbreadl(dev, 0); -+ dev->ids.regmapid = ddbreadl(dev, 4); ++ dev->link[0].ids.hwid = ddbreadl(dev, 0); ++ dev->link[0].ids.regmapid = ddbreadl(dev, 4); + -+ pr_info("HW %08x REGMAP %08x\n", -+ dev->ids.hwid, dev->ids.regmapid); ++ pr_info("DDBridge: HW %08x REGMAP %08x\n", ++ dev->link[0].ids.hwid, dev->link[0].ids.regmapid); + ++ if (dev->link[0].info->ns_num) { ++ int i; ++ ++ ddbwritel(dev, 0, ETHER_CONTROL); ++ for (i = 0; i < 16; i++) ++ ddbwritel(dev, 0x00, TS_OUTPUT_CONTROL(i)); ++ usleep_range(5000, 6000); ++ } + ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE); + ddbwritel(dev, 0x00000000, MSI1_ENABLE); + ddbwritel(dev, 0x00000000, MSI2_ENABLE); @@ -29843,29 +26471,14 @@ index 0000000..9784f10 + +#ifdef CONFIG_PCI_MSI + if (msi && pci_msi_enabled()) { -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) // OE + stat = pci_enable_msi_range(dev->pdev, 1, 2); + if (stat >= 1) { + dev->msi = stat; -+ pr_info(": Using %d MSI interrupts\n", dev->msi); ++ pr_info("DDBridge: using %d MSI interrupt(s)\n", ++ dev->msi); + irq_flag = 0; + } else -+ pr_info(": MSI not available.\n"); -+#else -+ stat = pci_enable_msi_block(dev->pdev, 2); -+ if (stat == 0) { -+ dev->msi = 1; -+ pr_info("DDBrige using 2 MSI interrupts\n"); -+ } -+ if (stat == 1) -+ stat = pci_enable_msi(dev->pdev); -+ if (stat < 0) { -+ pr_info(": MSI not available.\n"); -+ } else { -+ irq_flag = 0; -+ dev->msi++; -+ } -+#endif ++ pr_info("DDBridge: MSI not available.\n"); + } + if (dev->msi == 2) { + stat = request_irq(dev->pdev->irq, irq_handler0, @@ -29894,9 +26507,14 @@ index 0000000..9784f10 + goto fail0; + } + ddbwritel(dev, 0, DMA_BASE_READ); -+ if (dev->info->type != DDB_MOD) ++ if (dev->link[0].info->type != DDB_MOD) + ddbwritel(dev, 0, DMA_BASE_WRITE); + ++ if (dev->link[0].info->type == DDB_MOD) { ++ if (ddbreadl(dev, 0x1c) == 4) ++ dev->link[0].info->port_num = 4; ++ } ++ + /*ddbwritel(dev, 0xffffffff, INTERRUPT_ACK);*/ + if (dev->msi == 2) { + ddbwritel(dev, 0x0fffff00, INTERRUPT_ENABLE); @@ -29905,39 +26523,9 @@ index 0000000..9784f10 + ddbwritel(dev, 0x0fffff0f, INTERRUPT_ENABLE); + ddbwritel(dev, 0x00000000, MSI1_ENABLE); + } -+ mutex_init(&dev->lnb_lock); -+ if (ddb_i2c_init(dev) < 0) -+ goto fail1; -+ ddb_ports_init(dev); -+ if (ddb_buffers_alloc(dev) < 0) { -+ pr_info(": Could not allocate buffer memory\n"); -+ goto fail2; -+ } -+ if (ddb_ports_attach(dev) < 0) -+ goto fail3; ++ if (ddb_init(dev) == 0) ++ return 0; + -+ /* ignore if this fails */ -+ ddb_device_create(dev); -+ -+ if (dev->info->fan_num) { -+ ddbwritel(dev, 1, GPIO_DIRECTION); -+ ddbwritel(dev, 1, GPIO_OUTPUT); -+ } -+ if (dev->info->type == DDB_MOD) -+ ddbridge_mod_init(dev); -+ -+ return 0; -+ -+fail3: -+ ddb_ports_detach(dev); -+ pr_err("fail3\n"); -+ ddb_ports_release(dev); -+fail2: -+ pr_err("fail2\n"); -+ ddb_buffers_free(dev); -+ ddb_i2c_release(dev); -+fail1: -+ pr_err("fail1\n"); + ddbwritel(dev, 0, INTERRUPT_ENABLE); + ddbwritel(dev, 0, MSI1_ENABLE); + free_irq(dev->pdev->irq, dev); @@ -29949,8 +26537,9 @@ index 0000000..9784f10 + pci_disable_msi(dev->pdev); +fail: + pr_err("fail\n"); ++ + ddb_unmap(dev); -+ pci_set_drvdata(pdev, 0); ++ pci_set_drvdata(pdev, NULL); + pci_disable_device(pdev); + return -1; +} @@ -29965,10 +26554,31 @@ index 0000000..9784f10 + .size = 0x20, +}; + ++static struct ddb_regset octopus_i2c_buf = { ++ .base = 0x1000, ++ .num = 0x04, ++ .size = 0x200, ++}; ++ ++/****************************************************************************/ ++ ++ +static struct ddb_regmap octopus_map = { + .i2c = &octopus_i2c, ++ .i2c_buf = &octopus_i2c_buf, +}; + ++static struct ddb_regmap octopus_net_map = { ++ .i2c = &octopus_i2c, ++ .i2c_buf = &octopus_i2c_buf, ++}; ++ ++static struct ddb_regmap octopus_mod_map = { ++}; ++ ++ ++/****************************************************************************/ ++ +static struct ddb_info ddb_none = { + .type = DDB_NONE, + .name = "unknown Digital Devices PCIe card, install newer driver", @@ -29978,29 +26588,33 @@ index 0000000..9784f10 +static struct ddb_info ddb_octopus = { + .type = DDB_OCTOPUS, + .name = "Digital Devices Octopus DVB adapter", ++ .regmap = &octopus_map, + .port_num = 4, -+ .i2c_num = 4, ++ .i2c_mask = 0x0f, +}; + +static struct ddb_info ddb_octopusv3 = { + .type = DDB_OCTOPUS, + .name = "Digital Devices Octopus V3 DVB adapter", ++ .regmap = &octopus_map, + .port_num = 4, -+ .i2c_num = 4, ++ .i2c_mask = 0x0f, +}; + +static struct ddb_info ddb_octopus_le = { + .type = DDB_OCTOPUS, + .name = "Digital Devices Octopus LE DVB adapter", ++ .regmap = &octopus_map, + .port_num = 2, -+ .i2c_num = 2, ++ .i2c_mask = 0x03, +}; + +static struct ddb_info ddb_octopus_oem = { + .type = DDB_OCTOPUS, + .name = "Digital Devices Octopus OEM", ++ .regmap = &octopus_map, + .port_num = 4, -+ .i2c_num = 4, ++ .i2c_mask = 0x0f, + .led_num = 1, + .fan_num = 1, + .temp_num = 1, @@ -30010,83 +26624,134 @@ index 0000000..9784f10 +static struct ddb_info ddb_octopus_mini = { + .type = DDB_OCTOPUS, + .name = "Digital Devices Octopus Mini", ++ .regmap = &octopus_map, + .port_num = 4, -+ .i2c_num = 4, ++ .i2c_mask = 0x0f, +}; + +static struct ddb_info ddb_v6 = { + .type = DDB_OCTOPUS, + .name = "Digital Devices Cine S2 V6 DVB adapter", ++ .regmap = &octopus_map, + .port_num = 3, -+ .i2c_num = 3, ++ .i2c_mask = 0x07, +}; + +static struct ddb_info ddb_v6_5 = { + .type = DDB_OCTOPUS, + .name = "Digital Devices Cine S2 V6.5 DVB adapter", ++ .regmap = &octopus_map, + .port_num = 4, -+ .i2c_num = 4, ++ .i2c_mask = 0x0f, +}; + +static struct ddb_info ddb_v7 = { + .type = DDB_OCTOPUS, + .name = "Digital Devices Cine S2 V7 DVB adapter", ++ .regmap = &octopus_map, + .port_num = 4, -+ .i2c_num = 4, -+ .board_control = 2, -+}; -+ -+static struct ddb_info ddb_s2_48 = { -+ .type = DDB_OCTOPUS_MAX, -+ .name = "Digital Devices Cine S2 4/8", -+ .port_num = 4, -+ .i2c_num = 1, -+ .board_control = 1, ++ .i2c_mask = 0x0f, ++ .board_control = 2, ++ .board_control_2 = 4, ++ .ts_quirks = TS_QUIRK_REVERSED, +}; + +static struct ddb_info ddb_ctv7 = { + .type = DDB_OCTOPUS, + .name = "Digital Devices Cine CT V7 DVB adapter", ++ .regmap = &octopus_map, + .port_num = 4, -+ .i2c_num = 4, -+ .board_control = 3, ++ .i2c_mask = 0x0f, ++ .board_control = 3, ++ .board_control_2 = 4, +}; + +static struct ddb_info ddb_satixS2v3 = { + .type = DDB_OCTOPUS, + .name = "Mystique SaTiX-S2 V3 DVB adapter", ++ .regmap = &octopus_map, + .port_num = 3, -+ .i2c_num = 3, ++ .i2c_mask = 0x07, +}; + +static struct ddb_info ddb_ci = { + .type = DDB_OCTOPUS_CI, + .name = "Digital Devices Octopus CI", ++ .regmap = &octopus_map, + .port_num = 4, -+ .i2c_num = 2, ++ .i2c_mask = 0x03, +}; + +static struct ddb_info ddb_cis = { + .type = DDB_OCTOPUS_CI, + .name = "Digital Devices Octopus CI single", ++ .regmap = &octopus_map, + .port_num = 3, -+ .i2c_num = 2, ++ .i2c_mask = 0x03, ++}; ++ ++static struct ddb_info ddb_ci_s2_pro = { ++ .type = DDB_OCTOPUS_CI, ++ .name = "Digital Devices Octopus CI S2 Pro", ++ .regmap = &octopus_map, ++ .port_num = 4, ++ .i2c_mask = 0x01, ++ .board_control = 2, ++ .board_control_2 = 4, +}; + +static struct ddb_info ddb_dvbct = { + .type = DDB_OCTOPUS, + .name = "Digital Devices DVBCT V6.1 DVB adapter", ++ .regmap = &octopus_map, + .port_num = 3, -+ .i2c_num = 3, ++ .i2c_mask = 0x07, ++}; ++ ++/****************************************************************************/ ++ ++static struct ddb_info ddb_s2_48 = { ++ .type = DDB_OCTOPUS_MAX, ++ .name = "Digital Devices MAX S8 4/8", ++ .regmap = &octopus_map, ++ .port_num = 4, ++ .i2c_mask = 0x01, ++ .board_control = 1, ++}; ++ ++static struct ddb_info ddb_ct_8 = { ++ .type = DDB_OCTOPUS_MAX_CT, ++ .name = "Digital Devices MAX CT8", ++ .regmap = &octopus_map, ++ .port_num = 4, ++ .i2c_mask = 0x0f, ++ .board_control = 0x0ff, ++ .board_control_2 = 0xf00, ++ .ts_quirks = TS_QUIRK_SERIAL, +}; + +static struct ddb_info ddb_mod = { + .type = DDB_MOD, + .name = "Digital Devices DVB-C modulator", ++ .regmap = &octopus_mod_map, + .port_num = 10, + .temp_num = 1, +}; + ++static struct ddb_info ddb_octopus_net = { ++ .type = DDB_OCTONET, ++ .name = "Digital Devices OctopusNet network DVB adapter", ++ .regmap = &octopus_net_map, ++ .port_num = 10, ++ .i2c_mask = 0x3ff, ++ .ns_num = 12, ++ .mdio_num = 1, ++}; ++ ++/****************************************************************************/ ++/****************************************************************************/ ++/****************************************************************************/ ++ +#define DDVID 0xdd01 /* Digital Devices Vendor ID */ + +#define DDB_ID(_vend, _dev, _subvend, _subdev, _driverdata) { \ @@ -30094,13 +26759,14 @@ index 0000000..9784f10 + .subvendor = _subvend, .subdevice = _subdev, \ + .driver_data = (unsigned long)&_driverdata } + -+static const struct pci_device_id ddb_id_tbl[] __devinitconst = { ++static const struct pci_device_id ddb_id_tbl[] = { + DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus), + DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus), + DDB_ID(DDVID, 0x0005, DDVID, 0x0004, ddb_octopusv3), + DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le), + DDB_ID(DDVID, 0x0003, DDVID, 0x0003, ddb_octopus_oem), + DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus_mini), ++ DDB_ID(DDVID, 0x0005, DDVID, 0x0011, ddb_octopus_mini), + DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6), + DDB_ID(DDVID, 0x0003, DDVID, 0x0021, ddb_v6_5), + DDB_ID(DDVID, 0x0006, DDVID, 0x0022, ddb_v7), @@ -30110,13 +26776,26 @@ index 0000000..9784f10 + DDB_ID(DDVID, 0x0006, DDVID, 0x0032, ddb_ctv7), + DDB_ID(DDVID, 0x0006, DDVID, 0x0033, ddb_ctv7), + DDB_ID(DDVID, 0x0007, DDVID, 0x0023, ddb_s2_48), ++ DDB_ID(DDVID, 0x0008, DDVID, 0x0034, ddb_ct_8), ++ DDB_ID(DDVID, 0x0008, DDVID, 0x0035, ddb_ct_8), ++ DDB_ID(DDVID, 0x0008, DDVID, 0x0036, ddb_ct_8), + DDB_ID(DDVID, 0x0011, DDVID, 0x0040, ddb_ci), + DDB_ID(DDVID, 0x0011, DDVID, 0x0041, ddb_cis), ++ DDB_ID(DDVID, 0x0012, DDVID, 0x0042, ddb_ci), ++ DDB_ID(DDVID, 0x0013, DDVID, 0x0043, ddb_ci_s2_pro), + DDB_ID(DDVID, 0x0201, DDVID, 0x0001, ddb_mod), ++ DDB_ID(DDVID, 0x0201, DDVID, 0x0002, ddb_mod), ++ DDB_ID(DDVID, 0x0320, PCI_ANY_ID, PCI_ANY_ID, ddb_octopus_net), + /* in case sub-ids got deleted in flash */ + DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none), ++ DDB_ID(DDVID, 0x0005, PCI_ANY_ID, PCI_ANY_ID, ddb_none), ++ DDB_ID(DDVID, 0x0006, PCI_ANY_ID, PCI_ANY_ID, ddb_none), ++ DDB_ID(DDVID, 0x0007, PCI_ANY_ID, PCI_ANY_ID, ddb_none), ++ DDB_ID(DDVID, 0x0008, PCI_ANY_ID, PCI_ANY_ID, ddb_none), + DDB_ID(DDVID, 0x0011, PCI_ANY_ID, PCI_ANY_ID, ddb_none), ++ DDB_ID(DDVID, 0x0013, PCI_ANY_ID, PCI_ANY_ID, ddb_none), + DDB_ID(DDVID, 0x0201, PCI_ANY_ID, PCI_ANY_ID, ddb_none), ++ DDB_ID(DDVID, 0x0320, PCI_ANY_ID, PCI_ANY_ID, ddb_none), + {0} +}; +MODULE_DEVICE_TABLE(pci, ddb_id_tbl); @@ -30134,7 +26813,7 @@ index 0000000..9784f10 + + pr_info("Digital Devices PCIE bridge driver " + DDBRIDGE_VERSION -+ ", Copyright (C) 2010-14 Digital Devices GmbH\n"); ++ ", Copyright (C) 2010-15 Digital Devices GmbH\n"); + if (ddb_class_create() < 0) + return -1; + ddb_wq = create_workqueue("ddbridge"); @@ -30162,11 +26841,11 @@ index 0000000..9784f10 +module_exit(module_exit_ddbridge); + +MODULE_DESCRIPTION("Digital Devices PCIe Bridge"); -+MODULE_AUTHOR("Ralph Metzler, Metzler Brothers Systementwicklung"); ++MODULE_AUTHOR("Ralph and Marcus Metzler, Metzler Brothers Systementwicklung GbR"); +MODULE_LICENSE("GPL"); -+MODULE_VERSION(DDBRIDGE_VERSION); ++MODULE_VERSION(DDBRIDGE_VERSION); diff --git a/drivers/media/pci/ddbridge/ddbridge.h b/drivers/media/pci/ddbridge/ddbridge.h -index be87fbd..a02e91a 100644 +index be87fbd..edc42de 100644 --- a/drivers/media/pci/ddbridge/ddbridge.h +++ b/drivers/media/pci/ddbridge/ddbridge.h @@ -1,7 +1,8 @@ @@ -30174,23 +26853,15 @@ index be87fbd..a02e91a 100644 * ddbridge.h: Digital Devices PCIe bridge driver * - * Copyright (C) 2010-2011 Digital Devices GmbH -+ * Copyright (C) 2010-2014 Digital Devices GmbH ++ * Copyright (C) 2010-2015 Digital Devices GmbH + * Ralph Metzler * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License -@@ -24,16 +25,51 @@ +@@ -24,16 +25,41 @@ #ifndef _DDBRIDGE_H_ #define _DDBRIDGE_H_ -+#include -+ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) -+#define __devexit -+#define __devinit -+#define __devinitconst -+#endif -+ +#include +#include +#include @@ -30199,7 +26870,6 @@ index be87fbd..a02e91a 100644 +#include +#include +#include -+#include +#include +#include +#include @@ -30215,7 +26885,7 @@ index be87fbd..a02e91a 100644 #include #include #include - #include +-#include #include #include -#include @@ -30232,7 +26902,7 @@ index be87fbd..a02e91a 100644 #include "dmxdev.h" #include "dvbdev.h" #include "dvb_demux.h" -@@ -41,95 +77,167 @@ +@@ -41,143 +67,582 @@ #include "dvb_ringbuffer.h" #include "dvb_ca_en50221.h" #include "dvb_net.h" @@ -30242,22 +26912,23 @@ index be87fbd..a02e91a 100644 +#include "stv090x.h" +#include "lnbh24.h" +#include "drxk.h" -+#include "stv0367.h" +#include "stv0367dd.h" +#include "tda18212.h" -+#include "tda18212dd.h" +#include "cxd2843.h" #include "cxd2099.h" +#include "stv0910.h" +#include "stv6111.h" +#include "lnbh25.h" - - #define DDB_MAX_I2C 4 --#define DDB_MAX_PORT 4 -+#define DDB_MAX_PORT 10 - #define DDB_MAX_INPUT 8 --#define DDB_MAX_OUTPUT 4 ++#include "mxl5xx.h" ++ ++#define DDB_MAX_I2C 16 ++#define DDB_MAX_PORT 16 ++#define DDB_MAX_INPUT 44 +#define DDB_MAX_OUTPUT 10 ++#define DDB_MAX_LINK 4 ++#define DDB_LINK_SHIFT 28 ++ ++#define DDB_LINK_TAG(_x) (_x << DDB_LINK_SHIFT) + +struct ddb_regset { + u32 base; @@ -30265,7 +26936,14 @@ index be87fbd..a02e91a 100644 + u32 size; +}; + ++struct ddb_ports { ++ u32 base; ++ u32 num; ++ u32 size; ++}; ++ +struct ddb_regmap { ++ struct ddb_ports *bc; + struct ddb_regset *i2c; + struct ddb_regset *i2c_buf; + struct ddb_regset *dma; @@ -30276,8 +26954,13 @@ index be87fbd..a02e91a 100644 + struct ddb_regset *ci; + struct ddb_regset *pid_filter; + struct ddb_regset *ns; ++ struct ddb_regset *gtl; +}; -+ + +-#define DDB_MAX_I2C 4 +-#define DDB_MAX_PORT 4 +-#define DDB_MAX_INPUT 8 +-#define DDB_MAX_OUTPUT 4 +struct ddb_ids { + u16 vendor; + u16 device; @@ -30298,29 +26981,35 @@ index be87fbd..a02e91a 100644 +#define DDB_MOD 3 +#define DDB_OCTONET 4 +#define DDB_OCTOPUS_MAX 5 ++#define DDB_OCTOPUS_MAX_CT 6 char *name; - int port_num; - u32 port_type[DDB_MAX_PORT]; ++ u32 i2c_mask; + u8 port_num; -+ u8 i2c_num; + u8 led_num; + u8 fan_num; + u8 temp_num; + u8 temp_bus; -+ u8 board_control; ++ u32 board_control; ++ u32 board_control_2; + u8 ns_num; + u8 mdio_num; ++ u8 con_clock; /* use a continuous clock */ ++ u8 ts_quirks; ++#define TS_QUIRK_SERIAL 1 ++#define TS_QUIRK_REVERSED 2 + struct ddb_regmap *regmap; }; -/* DMA_SIZE MUST be divisible by 188 and 128 !!! */ - --#define INPUT_DMA_MAX_BUFS 32 /* hardware table limit */ +/* DMA_SIZE MUST be smaller than 256k and -+ MUST be divisible by 188 and 128 !!! */ ++ * MUST be divisible by 188 and 128 !!! ++ */ + +#define DMA_MAX_BUFS 32 /* hardware table limit */ -+ + +-#define INPUT_DMA_MAX_BUFS 32 /* hardware table limit */ #define INPUT_DMA_BUFS 8 #define INPUT_DMA_SIZE (128*47*21) +#define INPUT_DMA_IRQ_DIV 1 @@ -30370,6 +27059,7 @@ index be87fbd..a02e91a 100644 + struct dvb_adapter *adap; + int adap_registered; struct dvb_device *dev; ++ struct i2c_client *i2c_client[1]; struct dvb_frontend *fe; struct dvb_frontend *fe2; struct dmxdev dmxdev; @@ -30383,9 +27073,15 @@ index be87fbd..a02e91a 100644 + u32 attached; + u8 input; + ++ enum fe_sec_tone_mode tone; ++ enum fe_sec_voltage voltage; ++ + int (*i2c_gate_ctrl)(struct dvb_frontend *, int); -+ int (*set_voltage)(struct dvb_frontend* fe, fe_sec_voltage_t voltage); -+ int (*set_input)(struct dvb_frontend *fe); ++ int (*set_voltage)(struct dvb_frontend *fe, ++ enum fe_sec_voltage voltage); ++ int (*set_input)(struct dvb_frontend *fe, int input); ++ int (*diseqc_send_master_cmd)(struct dvb_frontend *fe, ++ struct dvb_diseqc_master_cmd *cmd); }; -struct ddb_output { @@ -30423,18 +27119,28 @@ index be87fbd..a02e91a 100644 struct ddb_i2c { struct ddb *dev; u32 nr; - struct i2c_adapter adap; +- struct i2c_adapter adap; - struct i2c_adapter adap2; u32 regs; ++ u32 link; ++ struct i2c_adapter adap; u32 rbuf; u32 wbuf; - int done; - wait_queue_head_t wq; ++ u32 bsize; + struct completion completion; }; struct ddb_port { -@@ -141,43 +249,250 @@ struct ddb_port { + struct ddb *dev; + u32 nr; ++ u32 pnr; ++ u32 regs; ++ u32 lnr; + struct ddb_i2c *i2c; + struct mutex i2c_gate_lock; + u32 class; #define DDB_PORT_NONE 0 #define DDB_PORT_CI 1 #define DDB_PORT_TUNER 2 @@ -30448,6 +27154,7 @@ index be87fbd..a02e91a 100644 +#define DDB_PORT_LOOP 3 +#define DDB_PORT_MOD 4 + char *name; ++ char *type_name; + u32 type; +#define DDB_TUNER_NONE 0 +#define DDB_TUNER_DVBS_ST 1 @@ -30461,28 +27168,29 @@ index be87fbd..a02e91a 100644 +#define DDB_TUNER_ISDBT_SONY_P 9 +#define DDB_TUNER_DVBS_STV0910_P 10 +#define DDB_TUNER_MXL5XX 11 - -+#define DDB_TUNER_XO2 16 -+#define DDB_TUNER_DVBS_STV0910 16 -+#define DDB_TUNER_DVBCT2_SONY 17 -+#define DDB_TUNER_ISDBT_SONY 18 -+#define DDB_TUNER_DVBC2T2_SONY 19 -+#define DDB_TUNER_ATSC_ST 20 -+#define DDB_TUNER_DVBC2T2_ST 21 ++#define DDB_CI_EXTERNAL_XO2 12 ++#define DDB_CI_EXTERNAL_XO2_B 13 ++#define DDB_TUNER_DVBS_STV0910_PR 14 + -+ u32 adr; ++#define DDB_TUNER_XO2 32 ++#define DDB_TUNER_DVBS_STV0910 (DDB_TUNER_XO2 + 0) ++#define DDB_TUNER_DVBCT2_SONY (DDB_TUNER_XO2 + 1) ++#define DDB_TUNER_ISDBT_SONY (DDB_TUNER_XO2 + 2) ++#define DDB_TUNER_DVBC2T2_SONY (DDB_TUNER_XO2 + 3) ++#define DDB_TUNER_ATSC_ST (DDB_TUNER_XO2 + 4) ++#define DDB_TUNER_DVBC2T2_ST (DDB_TUNER_XO2 + 5) + struct ddb_input *input[2]; struct ddb_output *output; struct dvb_ca_en50221 *en; + struct ddb_dvb dvb[2]; + u32 gap; + u32 obr; ++ u8 creg; +}; + -+ +struct mod_base { + u32 frequency; -+ + u32 flat_start; + u32 flat_end; +}; @@ -30533,12 +27241,33 @@ index be87fbd..a02e91a 100644 +struct ddb_ns { + struct ddb_input *input; + int nr; -+ int fe; ++ struct ddb_input *fe; + u32 rtcp_udplen; + u32 rtcp_len; + u32 ts_offset; + u32 udplen; + u8 p[512]; ++}; ++ ++struct ddb_lnb { ++ struct mutex lock; ++ u32 tone; ++ enum fe_sec_voltage oldvoltage[4]; ++ u32 voltage[4]; ++ u32 voltages; ++ u32 fmode; ++}; ++ ++struct ddb_link { ++ struct ddb *dev; ++ struct ddb_info *info; ++ u32 nr; ++ u32 regs; ++ spinlock_t lock; ++ struct mutex flash_mutex; ++ struct ddb_lnb lnb; ++ struct tasklet_struct tasklet; ++ struct ddb_ids ids; }; struct ddb { @@ -30546,25 +27275,25 @@ index be87fbd..a02e91a 100644 - unsigned char __iomem *regs; + struct platform_device *pfdev; + struct device *dev; -+ struct ddb_ids ids; -+ struct ddb_info *info; ++ + int msi; + struct workqueue_struct *wq; + u32 has_dma; + u32 has_ns; -+ -+ struct ddb_regmap regmap; ++ struct ddb_link link[DDB_MAX_LINK]; + unsigned char *regs; + u32 regs_len; ++ u32 port_num; struct ddb_port port[DDB_MAX_PORT]; ++ u32 i2c_num; struct ddb_i2c i2c[DDB_MAX_I2C]; struct ddb_input input[DDB_MAX_INPUT]; struct ddb_output output[DDB_MAX_OUTPUT]; + struct dvb_adapter adap[DDB_MAX_INPUT]; + struct ddb_dma dma[DDB_MAX_INPUT + DDB_MAX_OUTPUT]; + -+ void (*handler[32])(unsigned long); -+ unsigned long handler_data[32]; ++ void (*handler[128])(unsigned long); ++ unsigned long handler_data[128]; struct device *ddb_dev; - int nr; @@ -30577,9 +27306,10 @@ index be87fbd..a02e91a 100644 + u8 leds; + u32 ts_irq; + u32 i2c_irq; -+ + int ns_num; ++ + struct ddb_ns ns[DDB_NS_MAX]; ++ int vlan; + struct mutex mutex; + + struct dvb_device *nsd_dev; @@ -30587,59 +27317,167 @@ index be87fbd..a02e91a 100644 + + struct mod_base mod_base; + struct mod_state mod[10]; -+ -+ struct mutex octonet_i2c_lock; -+ struct mutex lnb_lock; -+ u32 lnb_tone; }; +-/****************************************************************************/ ++static inline void ddbwriteb(struct ddb *dev, u32 val, u32 adr) ++{ ++ writeb(val, (char *) (dev->regs + (adr))); ++} + - /****************************************************************************/ ++static inline u32 ddbreadb(struct ddb *dev, u32 adr) ++{ ++ return readb((char *) (dev->regs + (adr))); ++} ++ ++static inline void ddbwritel0(struct ddb_link *link, u32 val, u32 adr) ++{ ++ writel(val, (char *) (link->dev->regs + (adr))); ++} ++ ++static inline u32 ddbreadl0(struct ddb_link *link, u32 adr) ++{ ++ return readl((char *) (link->dev->regs + (adr))); ++} ++ ++static inline void gtlw(struct ddb_link *link) ++{ ++ while (1 & ddbreadl0(link, link->regs + 0x10)) ++ ; ++} ++ ++static u32 ddbreadl(struct ddb *dev, u32 adr) ++{ ++ if (unlikely(adr & 0xf0000000)) { ++ unsigned long flags; ++ u32 val, l = (adr >> DDB_LINK_SHIFT); ++ struct ddb_link *link = &dev->link[l]; ++ ++ spin_lock_irqsave(&link->lock, flags); ++ gtlw(link); ++ ddbwritel0(link, adr & 0xfffc, link->regs + 0x14); ++ ddbwritel0(link, 3, link->regs + 0x10); ++ gtlw(link); ++ val = ddbreadl0(link, link->regs + 0x1c); ++ spin_unlock_irqrestore(&link->lock, flags); ++ return val; ++ } ++ return readl((char *) (dev->regs + (adr))); ++} ++ ++static void ddbwritel(struct ddb *dev, u32 val, u32 adr) ++{ ++ if (unlikely(adr & 0xf0000000)) { ++ unsigned long flags; ++ u32 l = (adr >> DDB_LINK_SHIFT); ++ struct ddb_link *link = &dev->link[l]; -#define ddbwritel(_val, _adr) writel((_val), \ - dev->regs+(_adr)) -#define ddbreadl(_adr) readl(dev->regs+(_adr)) -#define ddbcpyto(_adr, _src, _count) memcpy_toio(dev->regs+(_adr), (_src), (_count)) -#define ddbcpyfrom(_dst, _adr, _count) memcpy_fromio((_dst), dev->regs+(_adr), (_count)) -+static inline void ddbwriteb(struct ddb *dev, u32 val, u32 adr) -+{ -+ writeb(val, (char *) (dev->regs+(adr))); -+} -+ -+static inline void ddbwritel(struct ddb *dev, u32 val, u32 adr) -+{ -+ writel(val, (char *) (dev->regs+(adr))); -+} -+ -+static inline void ddbwritew(struct ddb *dev, u16 val, u32 adr) -+{ -+ writew(val, (char *) (dev->regs+(adr))); -+} -+ -+static inline u32 ddbreadl(struct ddb *dev, u32 adr) -+{ -+ return readl((char *) (dev->regs+(adr))); -+} -+ -+static inline u32 ddbreadb(struct ddb *dev, u32 adr) -+{ -+ return readb((char *) (dev->regs+(adr))); ++ spin_lock_irqsave(&link->lock, flags); ++ gtlw(link); ++ ddbwritel0(link, 0xf0000 | (adr & 0xfffc), link->regs + 0x14); ++ ddbwritel0(link, val, link->regs + 0x18); ++ ddbwritel0(link, 1, link->regs + 0x10); ++ spin_unlock_irqrestore(&link->lock, flags); ++ return; ++ } ++ writel(val, (char *) (dev->regs + (adr))); +} -+#define ddbcpyto(_dev, _adr, _src, _count) \ -+ memcpy_toio((char *) (_dev->regs + (_adr)), (_src), (_count)) ++static void gtlcpyto(struct ddb *dev, u32 adr, const u8 *buf, ++ unsigned int count) ++{ ++ u32 val = 0, p = adr; ++ u32 aa = p & 3; + -+#define ddbcpyfrom(_dev, _dst, _adr, _count) \ -+ memcpy_fromio((_dst), (char *) (_dev->regs + (_adr)), (_count)) ++ if (aa) { ++ while (p & 3 && count) { ++ val >>= 8; ++ val |= *buf << 24; ++ p++; ++ buf++; ++ count--; ++ } ++ ddbwritel(dev, val, adr); ++ } ++ while (count >= 4) { ++ val = buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24); ++ ddbwritel(dev, val, p); ++ p += 4; ++ buf += 4; ++ count -= 4; ++ } ++ if (count) { ++ val = buf[0]; ++ if (count > 1) ++ val |= buf[1] << 8; ++ if (count > 2) ++ val |= buf[2] << 16; ++ ddbwritel(dev, val, p); ++ } ++} ++ ++static void gtlcpyfrom(struct ddb *dev, u8 *buf, u32 adr, long count) ++{ ++ u32 val = 0, p = adr; ++ u32 a = p & 3; ++ ++ if (a) { ++ val = ddbreadl(dev, p) >> (8 * a); ++ while (p & 3 && count) { ++ *buf = val & 0xff; ++ val >>= 8; ++ p++; ++ buf++; ++ count--; ++ } ++ } ++ while (count >= 4) { ++ val = ddbreadl(dev, p); ++ buf[0] = val & 0xff; ++ buf[1] = (val >> 8) & 0xff; ++ buf[2] = (val >> 16) & 0xff; ++ buf[3] = (val >> 24) & 0xff; ++ p += 4; ++ buf += 4; ++ count -= 4; ++ } ++ if (count) { ++ val = ddbreadl(dev, p); ++ buf[0] = val & 0xff; ++ if (count > 1) ++ buf[1] = (val >> 8) & 0xff; ++ if (count > 2) ++ buf[2] = (val >> 16) & 0xff; ++ } ++} ++ ++static void ddbcpyto(struct ddb *dev, u32 adr, void *src, long count) ++{ ++ if (unlikely(adr & 0xf0000000)) ++ return gtlcpyto(dev, adr, src, count); ++ return memcpy_toio((char *) (dev->regs + adr), src, count); ++} ++ ++static void ddbcpyfrom(struct ddb *dev, void *dst, u32 adr, long count) ++{ ++ if (unlikely(adr & 0xf0000000)) ++ return gtlcpyfrom(dev, dst, adr, count); ++ return memcpy_fromio(dst, (char *) (dev->regs + adr), count); ++} + +#define ddbmemset(_dev, _adr, _val, _count) \ + memset_io((char *) (_dev->regs + (_adr)), (_val), (_count)) + + -+/****************************************************************************/ +/****************************************************************************/ /****************************************************************************/ - ++/****************************************************************************/ ++ +#define dd_uint8 u8 +#define dd_uint16 u16 +#define dd_int16 s16 @@ -30696,22 +27534,23 @@ index be87fbd..a02e91a 100644 +void ddbridge_mod_rate_handler(unsigned long data); + + -+int ddbridge_flashread(struct ddb *dev, u8 *buf, u32 addr, u32 len); -+ -+#define DDBRIDGE_VERSION "0.9.15" ++int ddbridge_flashread(struct ddb *dev, u32 link, u8 *buf, u32 addr, u32 len); + ++#define DDBRIDGE_VERSION "0.9.23" + #endif diff --git a/drivers/media/pci/ddbridge/octonet.c b/drivers/media/pci/ddbridge/octonet.c new file mode 100644 -index 0000000..e803e73 +index 0000000..3546f96 --- /dev/null +++ b/drivers/media/pci/ddbridge/octonet.c -@@ -0,0 +1,199 @@ +@@ -0,0 +1,262 @@ +/* + * octonet.c: Digital Devices network tuner driver + * -+ * Copyright (C) 2012-14 Digital Devices GmbH -+ * Ralph Metzler ++ * Copyright (C) 2012-15 Digital Devices GmbH ++ * Marcus Metzler ++ * Ralph Metzler + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License @@ -30734,26 +27573,79 @@ index 0000000..e803e73 +#include "ddbridge.h" +#include "ddbridge-regs.h" + -+#include -+ +static int adapter_alloc = 3; +module_param(adapter_alloc, int, 0444); +MODULE_PARM_DESC(adapter_alloc, +"0-one adapter per io, 1-one per tab with io, 2-one per tab, 3-one for all"); + -+#define DVB_NSD -+ +#include "ddbridge-core.c" + ++static struct ddb_regset octopus_i2c = { ++ .base = 0x80, ++ .num = 0x04, ++ .size = 0x20, ++}; ++ ++static struct ddb_regset octopus_i2c_buf = { ++ .base = 0x1000, ++ .num = 0x04, ++ .size = 0x200, ++}; ++ ++static struct ddb_regmap octopus_net_map = { ++ .i2c = &octopus_i2c, ++ .i2c_buf = &octopus_i2c_buf, ++}; ++ ++static struct ddb_regset octopus_gtl = { ++ .base = 0x180, ++ .num = 0x01, ++ .size = 0x20, ++}; ++ ++static struct ddb_regmap octopus_net_gtl = { ++ .i2c = &octopus_i2c, ++ .i2c_buf = &octopus_i2c_buf, ++ .gtl = &octopus_gtl, ++}; ++ +static struct ddb_info ddb_octonet = { + .type = DDB_OCTONET, + .name = "Digital Devices OctopusNet network DVB adapter", ++ .regmap = &octopus_net_map, + .port_num = 4, -+ .i2c_num = 4, ++ .i2c_mask = 0x0f, + .ns_num = 12, + .mdio_num = 1, +}; + ++static struct ddb_info ddb_octonet_jse = { ++ .type = DDB_OCTONET, ++ .name = "Digital Devices OctopusNet network DVB adapter JSE", ++ .regmap = &octopus_net_map, ++ .port_num = 4, ++ .i2c_mask = 0x0f, ++ .ns_num = 15, ++ .mdio_num = 1, ++}; ++ ++static struct ddb_info ddb_octonet_gtl = { ++ .type = DDB_OCTONET, ++ .name = "Digital Devices OctopusNet GTL", ++ .regmap = &octopus_net_gtl, ++ .port_num = 4, ++ .i2c_mask = 0x05, ++ .ns_num = 12, ++ .mdio_num = 1, ++ .con_clock = 1, ++}; ++ ++static struct ddb_info ddb_octonet_tbd = { ++ .type = DDB_OCTONET, ++ .name = "Digital Devices OctopusNet", ++ .regmap = &octopus_net_map, ++}; ++ +static void octonet_unmap(struct ddb *dev) +{ + if (dev->regs) @@ -30761,31 +27653,33 @@ index 0000000..e803e73 + vfree(dev); +} + -+static int __exit octonet_remove(struct platform_device *pdev) ++static int octonet_remove(struct platform_device *pdev) +{ + struct ddb *dev; -+ ++ + dev = platform_get_drvdata(pdev); -+ ++ ++ ddb_device_destroy(dev); + ddb_nsd_detach(dev); + ddb_ports_detach(dev); + ddb_i2c_release(dev); + -+ ddbwritel(dev, 0, ETHER_CONTROL); ++ if (dev->link[0].info->ns_num) ++ ddbwritel(dev, 0, ETHER_CONTROL); + ddbwritel(dev, 0, INTERRUPT_ENABLE); -+ free_irq(platform_get_irq(dev->pfdev, 0), dev); + ++ free_irq(platform_get_irq(dev->pfdev, 0), dev); + ddb_ports_release(dev); -+ ddb_device_destroy(dev); + octonet_unmap(dev); + platform_set_drvdata(pdev, 0); + return 0; +} + -+static int __init octonet_probe(struct platform_device *pdev) ++static int octonet_probe(struct platform_device *pdev) +{ + struct ddb *dev; + struct resource *regs; ++ int irq; + int i; + + dev = vzalloc(sizeof(struct ddb)); @@ -30794,7 +27688,6 @@ index 0000000..e803e73 + platform_set_drvdata(pdev, dev); + dev->dev = &pdev->dev; + dev->pfdev = pdev; -+ dev->info = &ddb_octonet; + + mutex_init(&dev->mutex); + regs = platform_get_resource(dev->pfdev, IORESOURCE_MEM, 0); @@ -30804,23 +27697,36 @@ index 0000000..e803e73 + dev_info(dev->dev, "regs_start=%08x regs_len=%08x\n", + (u32) regs->start, (u32) dev->regs_len); + dev->regs = ioremap(regs->start, dev->regs_len); ++ + if (!dev->regs) { + dev_err(dev->dev, "ioremap failed\n"); + return -ENOMEM; + } + -+ dev->ids.hwid = ddbreadl(dev, 0); -+ dev->ids.regmapid = ddbreadl(dev, 4); -+ dev->ids.devid = ddbreadl(dev, 8); -+ dev->ids.mac = ddbreadl(dev, 12); ++ dev->link[0].ids.hwid = ddbreadl(dev, 0); ++ dev->link[0].ids.regmapid = ddbreadl(dev, 4); ++ dev->link[0].ids.devid = ddbreadl(dev, 8); ++ dev->link[0].ids.mac = ddbreadl(dev, 12); + -+ dev->ids.vendor = dev->ids.devid & 0xffff; -+ dev->ids.device = dev->ids.devid >> 16; -+ dev->ids.subvendor = dev->ids.devid & 0xffff; -+ dev->ids.subdevice = dev->ids.devid >> 16; ++ dev->link[0].ids.vendor = dev->link[0].ids.devid & 0xffff; ++ dev->link[0].ids.device = dev->link[0].ids.devid >> 16; ++ dev->link[0].ids.subvendor = dev->link[0].ids.devid & 0xffff; ++ dev->link[0].ids.subdevice = dev->link[0].ids.devid >> 16; + -+ pr_info("HW %08x REGMAP %08x\n", dev->ids.hwid, dev->ids.regmapid); -+ pr_info("MAC %08x DEVID %08x\n", dev->ids.mac, dev->ids.devid); ++ dev->link[0].dev = dev; ++ if (dev->link[0].ids.devid == 0x0300dd01) ++ dev->link[0].info = &ddb_octonet; ++ else if (dev->link[0].ids.devid == 0x0301dd01) ++ dev->link[0].info = &ddb_octonet_jse; ++ else if (dev->link[0].ids.devid == 0x0307dd01) ++ dev->link[0].info = &ddb_octonet_gtl; ++ else ++ dev->link[0].info = &ddb_octonet_tbd; ++ ++ pr_info("HW %08x REGMAP %08x\n", dev->link[0].ids.hwid, ++ dev->link[0].ids.regmapid); ++ pr_info("MAC %08x DEVID %08x\n", dev->link[0].ids.mac, ++ dev->link[0].ids.devid); + + ddbwritel(dev, 0, ETHER_CONTROL); + ddbwritel(dev, 0x00000000, INTERRUPT_ENABLE); @@ -30828,60 +27734,55 @@ index 0000000..e803e73 + for (i = 0; i < 16; i++) + ddbwritel(dev, 0x00, TS_OUTPUT_CONTROL(i)); + usleep_range(5000, 6000); -+ -+ if (request_irq(platform_get_irq(dev->pfdev, 0), irq_handler, ++ ++ irq = platform_get_irq(dev->pfdev, 0); ++ if (irq < 0) ++ goto fail; ++ if (request_irq(irq, irq_handler, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, + "octonet-dvb", (void *) dev) < 0) + goto fail; -+ + ddbwritel(dev, 0x0fffff0f, INTERRUPT_ENABLE); -+ ddbwritel(dev, 0x1, ETHER_CONTROL); -+ ddbwritel(dev, 14 + (vlan ? 4 : 0), ETHER_LENGTH); + ++ if (ddb_init(dev) == 0) ++ return 0; + -+ mutex_init(&dev->octonet_i2c_lock); -+ if (ddb_i2c_init(dev) < 0) -+ goto fail1; -+ -+ ddb_ports_init(dev); -+ if (ddb_ports_attach(dev) < 0) -+ goto fail3; -+ -+ ddb_nsd_attach(dev); -+ -+ ddb_device_create(dev); -+ -+ return 0; -+ -+fail3: -+ ddb_ports_detach(dev); -+ dev_err(dev->dev, "fail3\n"); -+fail1: -+ dev_err(dev->dev, "fail1\n"); +fail: + dev_err(dev->dev, "fail\n"); + ddbwritel(dev, 0, ETHER_CONTROL); + ddbwritel(dev, 0, INTERRUPT_ENABLE); + octonet_unmap(dev); + platform_set_drvdata(pdev, 0); -+ return 0; ++ return -1; +} + ++#ifdef CONFIG_OF ++static const struct of_device_id octonet_dt_ids[] = { ++ { .compatible = "digitaldevices,octonet-dvb" }, ++ { /* sentinel */ } ++}; ++ ++MODULE_DEVICE_TABLE(of, octonet_dt_ids); ++#endif ++ +static struct platform_driver octonet_driver = { + .remove = __exit_p(octonet_remove), + .probe = octonet_probe, + .driver = { + .name = "octonet-dvb", + .owner = THIS_MODULE, ++#ifdef CONFIG_OF ++ .of_match_table = of_match_ptr(octonet_dt_ids), ++#endif + }, +}; + -+static __init int init_octonet(void) ++static int init_octonet(void) +{ + int res; + + pr_info("Digital Devices OctopusNet driver " DDBRIDGE_VERSION -+ ", Copyright (C) 2010-14 Digital Devices GmbH\n"); ++ ", Copyright (C) 2010-15 Digital Devices GmbH\n"); + res = ddb_class_create(); + if (res) + return res; @@ -30893,7 +27794,7 @@ index 0000000..e803e73 + return 0; +} + -+static __exit void exit_octonet(void) ++static void exit_octonet(void) +{ + platform_driver_unregister(&octonet_driver); + ddb_class_destroy(); @@ -30903,3136 +27804,633 @@ index 0000000..e803e73 +module_exit(exit_octonet); + +MODULE_DESCRIPTION("GPL"); -+MODULE_AUTHOR("Marcus and Ralph Metzler, Metzler Brothers Systementwicklung"); ++MODULE_AUTHOR("Marcus and Ralph Metzler, Metzler Brothers Systementwicklung GbR"); +MODULE_LICENSE("GPL"); -+MODULE_VERSION("0.5"); -diff --git a/drivers/media/pci/ngene/Kconfig b/drivers/media/pci/ngene/Kconfig -index 637d506..3896c12 100644 ---- a/drivers/media/pci/ngene/Kconfig -+++ b/drivers/media/pci/ngene/Kconfig -@@ -1,12 +1,16 @@ - config DVB_NGENE - tristate "Micronas nGene support" - depends on DVB_CORE && PCI && I2C -+ select DVB_CXD2099 - select DVB_LNBP21 if MEDIA_SUBDRV_AUTOSELECT - select DVB_STV6110x if MEDIA_SUBDRV_AUTOSELECT - select DVB_STV090x if MEDIA_SUBDRV_AUTOSELECT - select DVB_LGDT330X if MEDIA_SUBDRV_AUTOSELECT - select DVB_DRXK if MEDIA_SUBDRV_AUTOSELECT - select DVB_TDA18271C2DD if MEDIA_SUBDRV_AUTOSELECT -+ select DVB_STV0367DD if MEDIA_SUBDRV_AUTOSELECT -+ select DVB_TDA18212DD if MEDIA_SUBDRV_AUTOSELECT -+ select DVB_CXD2843 if MEDIA_SUBDRV_AUTOSELECT - select MEDIA_TUNER_MT2131 if MEDIA_SUBDRV_AUTOSELECT - ---help--- - Support for Micronas PCI express cards with nGene bridge. -diff --git a/drivers/media/pci/ngene/Makefile b/drivers/media/pci/ngene/Makefile -index 5c0b5d6..42c036a 100644 ---- a/drivers/media/pci/ngene/Makefile -+++ b/drivers/media/pci/ngene/Makefile -@@ -2,7 +2,8 @@ - # Makefile for the nGene device driver - # - --ngene-objs := ngene-core.o ngene-i2c.o ngene-cards.o ngene-dvb.o -+ngene-objs := ngene-core.o ngene-i2c.o ngene-cards.o ngene-av.o \ -+ ngene-eeprom.o ngene-dvb.o - - obj-$(CONFIG_DVB_NGENE) += ngene.o - -diff --git a/drivers/media/pci/ngene/ngene-av.c b/drivers/media/pci/ngene/ngene-av.c -new file mode 100644 -index 0000000..a86459e ---- /dev/null -+++ b/drivers/media/pci/ngene/ngene-av.c -@@ -0,0 +1,348 @@ -+/* -+ * ngene-av.c: nGene PCIe bridge driver - DVB video/audio support -+ * -+ * Copyright (C) 2005-2007 Micronas -+ * -+ * Copyright (C) 2008-2009 Ralph Metzler -+ * Modifications for new nGene firmware, -+ * support for EEPROM-copying, -+ * support for new dual DVB-S2 card prototype -+ * -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 only, as published by the Free Software Foundation. -+ * -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ * 02110-1301, USA -+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/* This file provides the support functions for DVB audio/video devices -+ (/dev/dvb/adapter0/[video|audio]), not to be confused with V4L2 support */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "ngene.h" -+ -+#if 0 -+ -+static void *ain_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags) -+{ -+ struct ngene_channel *chan = priv; -+ struct ngene *dev = chan->dev; -+ -+ if (dvb_ringbuffer_free(&dev->ain_rbuf) >= len) { -+ dvb_ringbuffer_write(&dev->ain_rbuf, buf, len); -+ wake_up_interruptible(&dev->ain_rbuf.queue); -+ } else -+ printk(KERN_INFO DEVICE_NAME ": Dropped ain packet.\n"); -+ -+ return 0; -+} -+ -+static void *vcap_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags) -+{ -+ -+ struct ngene_channel *chan = priv; -+ struct ngene *dev = chan->dev; -+ -+ if (len >= 1920 * 1080) -+ len = 1920 * 1080; -+ if (dvb_ringbuffer_free(&dev->vin_rbuf) >= len) { -+ dvb_ringbuffer_write(&dev->vin_rbuf, buf, len); -+ wake_up_interruptible(&dev->vin_rbuf.queue); -+ } else { -+ ;/*printk(KERN_INFO DEVICE_NAME ": Dropped vcap packet.\n"); */ -+ } -+ return 0; -+} -+ -+static ssize_t audio_write(struct file *file, -+ const char *buf, size_t count, loff_t *ppos) -+{ -+ return -EINVAL; -+} -+ -+ssize_t audio_read(struct file *file, char *buf, size_t count, loff_t *ppos) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ int left; -+ int avail; -+ -+ left = count; -+ while (left) { -+ if (wait_event_interruptible( -+ dev->ain_rbuf.queue, -+ dvb_ringbuffer_avail(&dev->ain_rbuf) > 0) < 0) -+ return -EAGAIN; -+ avail = dvb_ringbuffer_avail(&dev->ain_rbuf); -+ if (avail > left) -+ avail = left; -+ dvb_ringbuffer_read_user(&dev->ain_rbuf, buf, avail); -+ left -= avail; -+ buf += avail; -+ } -+ return count; -+} -+ -+static int audio_open(struct inode *inode, struct file *file) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ struct ngene_channel *chan2 = &chan->dev->channel[2]; -+ int ret; -+ -+ ret = dvb_generic_open(inode, file); -+ if (ret < 0) -+ return ret; -+ dvb_ringbuffer_flush(&dev->ain_rbuf); -+ -+ chan2->Capture1Length = MAX_AUDIO_BUFFER_SIZE; -+ chan2->pBufferExchange = ain_exchange; -+ ngene_command_stream_control(chan2->dev, chan2->number, 0x80, -+ SMODE_AUDIO_CAPTURE, 0); -+ return ret; -+} -+ -+static int audio_release(struct inode *inode, struct file *file) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ struct ngene_channel *chan2 = &chan->dev->channel[2]; -+ -+ ngene_command_stream_control(dev, 2, 0, 0, 0); -+ chan2->pBufferExchange = 0; -+ -+ return dvb_generic_release(inode, file); -+} -+ -+static const struct file_operations audio_fops = { -+ .owner = THIS_MODULE, -+ .read = audio_read, -+ .write = audio_write, -+ .open = audio_open, -+ .release = audio_release, -+}; -+ -+static struct dvb_device dvbdev_audio = { -+ .priv = 0, -+ .readers = -1, -+ .writers = 1, -+ .users = 1, -+ .fops = &audio_fops, -+}; -+ -+static int video_open(struct inode *inode, struct file *file) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ struct ngene_channel *chan0 = &chan->dev->channel[0]; -+ int ret; -+ -+ ret = dvb_generic_open(inode, file); -+ if (ret < 0) -+ return ret; -+ if ((file->f_flags & O_ACCMODE) != O_RDONLY) -+ return ret; -+ dvb_ringbuffer_flush(&dev->vin_rbuf); -+ -+ chan0->nBytesPerLine = 1920 * 2; -+ chan0->nLines = 540; -+ chan0->Capture1Length = 1920 * 2 * 540; -+ chan0->pBufferExchange = vcap_exchange; -+ chan0->itumode = 2; -+ ngene_command_stream_control(chan0->dev, chan0->number, -+ 0x80, SMODE_VIDEO_CAPTURE, 0); -+ return ret; -+} -+ -+static int video_release(struct inode *inode, struct file *file) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ struct ngene_channel *chan0 = &chan->dev->channel[0]; -+ -+ ngene_command_stream_control(dev, 0, 0, 0, 0); -+ chan0->pBufferExchange = 0; -+ -+ return dvb_generic_release(inode, file); -+} -+ -+static ssize_t video_write(struct file *file, -+ const char *buf, size_t count, loff_t *ppos) -+{ -+ return -EINVAL; -+} -+ -+ssize_t video_read(struct file *file, char *buf, size_t count, loff_t *ppos) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ int left, avail; -+ -+ left = count; -+ while (left) { -+ if (wait_event_interruptible( -+ dev->vin_rbuf.queue, -+ dvb_ringbuffer_avail(&dev->vin_rbuf) > 0) < 0) -+ return -EAGAIN; -+ avail = dvb_ringbuffer_avail(&dev->vin_rbuf); -+ if (avail > left) -+ avail = left; -+ dvb_ringbuffer_read_user(&dev->vin_rbuf, buf, avail); -+ left -= avail; -+ buf += avail; -+ } -+ return count; -+} -+ -+/* Why is this not exported from dvb_core ?!?! */ -+ -+static int dvb_usercopy2(struct inode *inode, struct file *file, -+ unsigned int cmd, unsigned long arg, -+ int (*func)(struct inode *inode, struct file *file, -+ unsigned int cmd, void *arg)) -+{ -+ char sbuf[128]; -+ void *mbuf = NULL; -+ void *parg = NULL; -+ int err = -EINVAL; -+ -+ /* Copy arguments into temp kernel buffer */ -+ switch (_IOC_DIR(cmd)) { -+ case _IOC_NONE: -+ /* -+ * For this command, the pointer is actually an integer -+ * argument. -+ */ -+ parg = (void *)arg; -+ break; -+ case _IOC_READ: /* some v4l ioctls are marked wrong ... */ -+ case _IOC_WRITE: -+ case (_IOC_WRITE | _IOC_READ): -+ if (_IOC_SIZE(cmd) <= sizeof(sbuf)) { -+ parg = sbuf; -+ } else { -+ /* too big to allocate from stack */ -+ mbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL); -+ if (NULL == mbuf) -+ return -ENOMEM; -+ parg = mbuf; -+ } -+ -+ err = -EFAULT; -+ if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd))) -+ goto out; -+ break; -+ } -+ -+ /* call driver */ -+ err = func(inode, file, cmd, parg); -+ if (err == -ENOIOCTLCMD) -+ err = -EINVAL; -+ -+ if (err < 0) -+ goto out; -+ -+ /* Copy results into user buffer */ -+ switch (_IOC_DIR(cmd)) { -+ case _IOC_READ: -+ case (_IOC_WRITE | _IOC_READ): -+ if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd))) -+ err = -EFAULT; -+ break; -+ } -+ -+out: -+ kfree(mbuf); -+ return err; -+} -+ -+static int video_do_ioctl(struct inode *inode, struct file *file, -+ unsigned int cmd, void *parg) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ int ret = 0; -+ unsigned long arg = (unsigned long)parg; -+ -+ switch (cmd) { -+ case VIDEO_SET_STREAMTYPE: -+ switch (arg) { -+ case VIDEO_CAP_MPEG2: -+ /* printk(KERN_INFO DEVICE_NAME ": setting MPEG2\n"); */ -+ send_cli(dev, "vdec mpeg2\n"); -+ break; -+ case VIDEO_CAP_AVC: -+ /* printk(KERN_INFO DEVICE_NAME ": setting H264\n"); */ -+ send_cli(dev, "vdec h264\n"); -+ break; -+ case VIDEO_CAP_VC1: -+ /* printk(KERN_INFO DEVICE_NAME ": setting VC1\n"); */ -+ send_cli(dev, "vdec vc1\n"); -+ break; -+ default: -+ ret = -EINVAL; -+ break; -+ } -+ break; -+ default: -+ ret = -ENOIOCTLCMD; -+ return -EINVAL; -+ } -+ return ret; -+} -+ -+static int video_ioctl(struct inode *inode, struct file *file, -+ unsigned int cmd, unsigned long arg) -+{ -+ return dvb_usercopy2(inode, file, cmd, arg, video_do_ioctl); -+} -+ -+static const struct file_operations video_fops = { -+ .owner = THIS_MODULE, -+ .read = video_read, -+ .write = video_write, -+ .open = video_open, -+ .release = video_release, -+ .ioctl = video_ioctl, -+}; -+ -+static struct dvb_device dvbdev_video = { -+ .priv = 0, -+ .readers = -1, -+ .writers = 1, -+ .users = -1, -+ .fops = &video_fops, -+}; -+#endif -diff --git a/drivers/media/pci/ngene/ngene-cards.c b/drivers/media/pci/ngene/ngene-cards.c -index 039bed3..a8a1a03 100644 ---- a/drivers/media/pci/ngene/ngene-cards.c -+++ b/drivers/media/pci/ngene/ngene-cards.c -@@ -42,8 +42,18 @@ - #include "mt2131.h" - #include "tda18271c2dd.h" - #include "drxk.h" --#include "drxd.h" --#include "dvb-pll.h" -+#include "tda18212dd.h" -+#include "stv0367dd.h" -+#include "cxd2843.h" -+ -+ -+enum DEMOD_TYPE { -+ DMD_NONE = 0, -+ DMD_STV0900, -+ DMD_DRXK, -+ DMD_STV0367, -+ DMD_CXD28xx, -+}; - - - /****************************************************************************/ -@@ -86,8 +96,98 @@ static int tuner_attach_stv6110(struct ngene_channel *chan) - return 0; - } - -+#if 0 -+static int tuner_attach_mt2060(struct ngene_channel *chan) -+{ -+ struct ngene *dev = chan->dev; -+ void *tconf = dev->card_info->tuner_config[chan->number]; -+ u8 drxa = dev->card_info->demoda[chan->number]; -+ struct dvb_frontend *fe = chan->fe, *fe2; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19) -+ fe->misc_priv = chan; -+#else -+ fe->sec_priv = chan; -+#endif -+ fe->ops.i2c_gate_ctrl = dev->card_info->gate_ctrl; -+ -+ dev->card_info->gate_ctrl(fe, 1); -+ fe2 = mt2060_attach(fe, &chan->i2c_adapter, tconf, 1220); -+ dev->card_info->gate_ctrl(fe, 0); -+ -+ i2c_write_register(&chan->i2c_adapter, drxa, 3, 4); -+ write_demod(&chan->i2c_adapter, drxa, 0x1012, 15); -+ write_demod(&chan->i2c_adapter, drxa, 0x1007, 0xc27); -+ write_demod(&chan->i2c_adapter, drxa, 0x0020, 0x003); -+ -+ return fe2 ? 0 : -ENODEV; -+} -+ -+static int tuner_attach_xc3028(struct ngene_channel *chan) -+{ -+ struct ngene *dev = chan->dev; -+ void *tconf = dev->card_info->tuner_config[chan->number]; -+ struct dvb_frontend *fe = chan->fe, *fe2; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19) -+ fe->misc_priv = chan; -+#else -+ fe->sec_priv = chan; -+#endif -+ fe->ops.i2c_gate_ctrl = dev->card_info->gate_ctrl; -+ -+ dev->card_info->gate_ctrl(fe, 1); -+ fe2 = xc3028_attach(fe, &chan->i2c_adapter, tconf); -+ dev->card_info->gate_ctrl(fe, 0); -+ -+ /*chan->fe->ops.tuner_ops.set_frequency(chan->fe,231250000);*/ -+ -+ return fe2 ? 0 : -ENODEV; -+} -+ -+static int demod_attach_drxd(struct ngene_channel *chan) -+{ -+ void *feconf = chan->dev->card_info->fe_config[chan->number]; -+ -+ chan->fe = drxd_attach(feconf, -+ chan, &chan->i2c_adapter, -+ &chan->dev->pci_dev->dev); -+ return (chan->fe) ? 0 : -ENODEV; -+} -+ -+static int demod_attach_drxh(struct ngene_channel *chan) -+{ -+ void *feconf = chan->dev->card_info->fe_config[chan->number]; -+ -+ chan->fe = drxh_attach(feconf, chan, -+ &chan->i2c_adapter, &chan->dev->pci_dev->dev); -+ return (chan->fe) ? 0 : -ENODEV; -+} -+ -+static int demod_attach_stb0899(struct ngene_channel *chan) -+{ -+ void *feconf = chan->dev->card_info->fe_config[chan->number]; -+ -+ chan->fe = stb0899_attach(feconf, -+ chan, &chan->i2c_adapter, -+ &chan->dev->pci_dev->dev); -+ if (chan->fe) { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18) -+ chan->set_tone = chan->fe->ops->set_tone; -+ chan->fe->ops->set_tone = lnbh21_set_tone; -+ chan->fe->ops->set_voltage = lnbh21_set_voltage; -+#else -+ chan->set_tone = chan->fe->ops.set_tone; -+ chan->fe->ops.set_tone = lnbh21_set_tone; -+ chan->fe->ops.set_voltage = lnbh21_set_voltage; -+#endif -+ } -+ -+ return (chan->fe) ? 0 : -ENODEV; -+} -+#endif - --static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) -+static int locked_gate_ctrl(struct dvb_frontend *fe, int enable) - { - struct ngene_channel *chan = fe->sec_priv; - int status; -@@ -121,12 +221,41 @@ static int tuner_attach_tda18271(struct ngene_channel *chan) - return 0; - } - -+static int tuner_attach_tda18212dd(struct ngene_channel *chan) -+{ -+ struct i2c_adapter *i2c; -+ struct dvb_frontend *fe; -+ u8 addr = (chan->number & 1) ? 0x63 : 0x60; -+ -+ if (chan->demod_type == DMD_CXD28xx && chan->number < 2) -+ addr ^= 0x04; -+ i2c = &chan->dev->channel[0].i2c_adapter; -+ fe = dvb_attach(tda18212dd_attach, chan->fe, i2c, addr); -+ if (!fe) { -+ printk(KERN_ERR "No TDA18212 found!\n"); -+ return -ENODEV; -+ } -+ return 0; -+} -+ - static int tuner_attach_probe(struct ngene_channel *chan) - { -- if (chan->demod_type == 0) -+ switch(chan->demod_type) -+ { -+ case DMD_STV0900: - return tuner_attach_stv6110(chan); -- if (chan->demod_type == 1) -+ -+ case DMD_DRXK: - return tuner_attach_tda18271(chan); -+ -+ case DMD_STV0367: -+ case DMD_CXD28xx: -+ return tuner_attach_tda18212dd(chan); -+ -+ default: -+ pr_err("Unknown demod %x\n", chan->demod_type); -+ break; -+ } - return -EINVAL; - } - -@@ -184,6 +313,26 @@ static int i2c_read(struct i2c_adapter *adapter, u8 adr, u8 *val) - return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; - } - -+static int i2c_read_regs(struct i2c_adapter *adapter, -+ u8 adr, u8 reg, u8 *val, u8 len) -+{ -+ struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, -+ .buf = ®, .len = 1 }, -+ {.addr = adr, .flags = I2C_M_RD, -+ .buf = val, .len = len } }; -+ return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; -+} -+ -+static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, -+ u8 reg, u8 *val) -+{ -+ struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, -+ .buf = ®, .len = 1}, -+ {.addr = adr, .flags = I2C_M_RD, -+ .buf = val, .len = 1} }; -+ return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; -+} -+ - static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr, - u16 reg, u8 *val) - { -@@ -195,6 +344,15 @@ static int i2c_read_reg16(struct i2c_adapter *adapter, u8 adr, - return (i2c_transfer(adapter, msgs, 2) == 2) ? 0 : -1; - } - -+static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr, -+ u8 reg, u8 val) -+{ -+ u8 msg[2] = {reg, val}; -+ struct i2c_msg msgs[1] = {{.addr = adr, .flags = 0, -+ .buf = msg, .len = 2 } }; -+ return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1; -+} -+ - static int port_has_stv0900(struct i2c_adapter *i2c, int port) - { - u8 val; -@@ -218,18 +376,154 @@ static int demod_attach_drxk(struct ngene_channel *chan, - struct drxk_config config; - - memset(&config, 0, sizeof(config)); -- config.microcode_name = "drxk_a3.mc"; -- config.qam_demod_parameter_count = 4; - config.adr = 0x29 + (chan->number ^ 2); -+ config.microcode_name = "drxk_a3.mc"; - -+#ifdef USE_API3 -+ chan->fe = dvb_attach(drxk_attach, &config, i2c, &chan->fe2); -+#else - chan->fe = dvb_attach(drxk_attach, &config, i2c); -+#endif - if (!chan->fe) { - printk(KERN_ERR "No DRXK found!\n"); - return -ENODEV; - } - chan->fe->sec_priv = chan; - chan->gate_ctrl = chan->fe->ops.i2c_gate_ctrl; -- chan->fe->ops.i2c_gate_ctrl = drxk_gate_ctrl; -+ chan->fe->ops.i2c_gate_ctrl = locked_gate_ctrl; -+ return 0; -+} -+ -+static int port_has_stv0367(struct i2c_adapter *i2c, int port) -+{ -+ u8 val; -+ -+ if (i2c_read_reg16(i2c, 0x1c + (port ^ 1), 0xf000, &val) < 0) -+ return 0; -+ if (val != 0x60) -+ return 0; -+ return 1; -+} -+ -+static int demod_attach_stv0367dd(struct ngene_channel *chan, -+ struct i2c_adapter *i2c) -+{ -+ struct stv0367_cfg cfg; -+ -+ memset(&cfg, 0, sizeof cfg); -+ cfg.adr = 0x1c + (chan->number ^ 1); -+ -+ chan->fe = dvb_attach(stv0367_attach, i2c, &cfg, &chan->fe2); -+ if (!chan->fe) { -+ printk(KERN_ERR "No stv0367 found!\n"); -+ return -ENODEV; -+ } -+ chan->fe->sec_priv = chan; -+ chan->gate_ctrl = chan->fe->ops.i2c_gate_ctrl; -+ chan->fe->ops.i2c_gate_ctrl = locked_gate_ctrl; -+ return 0; -+} -+ -+static int port_has_xo2(struct i2c_adapter *i2c, int port, u8 *id) -+{ -+ u8 addr = (port < 2) ? 0x14 : 0x10; -+ u8 val; -+ u8 probe[1] = { 0x00 }, data[4]; -+ struct i2c_msg msgs[2] = {{ .addr = addr, .flags = 0, -+ .buf = probe, .len = 1 }, -+ { .addr = addr, .flags = I2C_M_RD, -+ .buf = data, .len = 4 } }; -+#if 0 -+ u8 cfg[] = { 0x79, 0x00, 0x00 }; -+ struct i2c_msg cmsg = { .addr = 0x44, .flags = 0, -+ .buf = cfg, .len = 3 }; -+ if (port == 0) -+ i2c_transfer(i2c, &cmsg, 1); -+ pr_info("chan %d addr %x\n", port, addr); -+ msleep(1000); -+#endif -+ val = i2c_transfer(i2c, msgs, 2); -+ if (val != 2) -+ return 0; -+ -+ if (data[0] != 'D' || data[1] != 'F') -+ return 0; -+ -+ *id = data[2]; -+ return 1; -+} -+ -+static int init_xo2(struct i2c_adapter *i2c, int port) -+{ -+ u8 addr = (port < 2) ? 0x14 : 0x10; -+ u8 val, data[2]; -+ int res; -+ -+ if (port & 1) -+ return 0; -+ -+ res = i2c_read_regs(i2c, addr, 0x04, data, 2); -+ if (res < 0) -+ return res; -+ -+ if (data[0] != 0x01) { -+ pr_info("Invalid XO2\n"); -+ return -1; -+ } -+ -+ i2c_read_reg(i2c, addr, 0x08, &val); -+ if (val != 0) { -+ i2c_write_reg(i2c, addr, 0x08, 0x00); -+ msleep(100); -+ } -+ /* Enable tuner power, disable pll, reset demods */ -+ i2c_write_reg(i2c, addr, 0x08, 0x04); -+ usleep_range(2000, 3000); -+ /* Release demod resets */ -+ i2c_write_reg(i2c, addr, 0x08, 0x07); -+ usleep_range(2000, 3000); -+ /* Start XO2 PLL */ -+ i2c_write_reg(i2c, addr, 0x08, 0x87); -+ -+ return 0; -+} -+ -+#define DDB_TUNER_XO2 16 -+#define DDB_TUNER_DVBS_STV0910 16 -+#define DDB_TUNER_DVBCT2_SONY 17 -+#define DDB_TUNER_ISDBT_SONY 18 -+#define DDB_TUNER_DVBC2T2_SONY 19 -+#define DDB_TUNER_ATSC_ST 20 -+#define DDB_TUNER_DVBC2T2_ST 21 -+ -+static char *xo2names[] = { -+ "DUAL DVB-S2", -+ "DUAL DVB-C/T/T2", -+ "DUAL DVB-ISDBT", -+ "DUAL DVB-C/C2/T/T2", -+ "DUAL ATSC", -+ "DUAL DVB-C/C2/T/T2", -+ "", "" -+}; -+ -+struct cxd2843_cfg cxd2843[] = { -+ { .adr = 0x68, }, -+ { .adr = 0x69, }, -+ { .adr = 0x6c, }, -+ { .adr = 0x6d, }, -+}; -+ -+static int demod_attach_cxd2843(struct ngene_channel *chan, -+ struct i2c_adapter *i2c) -+{ -+ chan->fe = dvb_attach(cxd2843_attach, i2c, cxd2843+chan->number); -+ if (!chan->fe) { -+ pr_err("No cxd2837/38/43 found!\n"); -+ return -ENODEV; -+ } -+ chan->fe->sec_priv = chan; -+ chan->gate_ctrl = chan->fe->ops.i2c_gate_ctrl; -+ chan->fe->ops.i2c_gate_ctrl = locked_gate_ctrl; - return 0; - } - -@@ -240,6 +534,7 @@ static int cineS2_probe(struct ngene_channel *chan) - u8 buf[3]; - struct i2c_msg i2c_msg = { .flags = 0, .buf = buf }; - int rc; -+ u8 id; - - /* tuner 1+2: i2c adapter #0, tuner 3+4: i2c adapter #1 */ - if (chan->number < 2) -@@ -247,8 +542,33 @@ static int cineS2_probe(struct ngene_channel *chan) - else - i2c = &chan->dev->channel[1].i2c_adapter; - -- if (port_has_stv0900(i2c, chan->number)) { -- chan->demod_type = 0; -+ if (port_has_xo2(i2c, chan->number, &id)) { -+ id >>= 2; -+ if (id > 5) { -+ pr_info("Channel %d: Unknown XO2 DuoFlex %u\n", -+ chan->number, id); -+ return -ENODEV; -+ } -+ init_xo2(i2c, chan->number); -+ switch(DDB_TUNER_XO2 + id) -+ { -+ case DDB_TUNER_DVBCT2_SONY: -+ case DDB_TUNER_ISDBT_SONY: -+ case DDB_TUNER_DVBC2T2_SONY: -+ chan->demod_type = DMD_CXD28xx; -+ pr_info("Channel %d: %s\n", chan->number, xo2names[id]); -+ demod_attach_cxd2843(chan, i2c); -+ break; -+ default: -+ pr_info("Channel %d: %s not supported yet\n", -+ chan->number, xo2names[id]); -+ return -ENODEV; -+ } -+ -+ } else if (chan->dev->channel[0].demod_type != DMD_CXD28xx && -+ port_has_stv0900(i2c, chan->number)) { -+ chan->demod_type = DMD_STV0900; -+ pr_info("Channel %d: STV0900\n", chan->number); - fe_conf = chan->dev->card_info->fe_config[chan->number]; - /* demod found, attach it */ - rc = demod_attach_stv0900(chan); -@@ -276,9 +596,17 @@ static int cineS2_probe(struct ngene_channel *chan) - printk(KERN_ERR DEVICE_NAME ": could not setup DPNx\n"); - return -EIO; - } -+ - } else if (port_has_drxk(i2c, chan->number^2)) { -- chan->demod_type = 1; -+ chan->demod_type = DMD_DRXK; -+ pr_info("Channel %d: DRXK\n", chan->number); - demod_attach_drxk(chan, i2c); -+ -+ } else if (port_has_stv0367(i2c, chan->number)) { -+ chan->demod_type = DMD_STV0367; -+ pr_info("Channel %d: STV0367\n", chan->number); -+ demod_attach_stv0367dd(chan, i2c); -+ - } else { - printk(KERN_ERR "No demod found on chan %d\n", chan->number); - return -ENODEV; -@@ -315,249 +643,140 @@ static int demod_attach_lg330x(struct ngene_channel *chan) - return (chan->fe) ? 0 : -ENODEV; - } - --static int demod_attach_drxd(struct ngene_channel *chan) --{ -- struct drxd_config *feconf; -- -- feconf = chan->dev->card_info->fe_config[chan->number]; -- -- chan->fe = dvb_attach(drxd_attach, feconf, chan, -- &chan->i2c_adapter, &chan->dev->pci_dev->dev); -- if (!chan->fe) { -- pr_err("No DRXD found!\n"); -- return -ENODEV; -- } -- return 0; --} -+/****************************************************************************/ -+/* Switch control (I2C gates, etc.) *****************************************/ -+/****************************************************************************/ - --static int tuner_attach_dtt7520x(struct ngene_channel *chan) -+#if 0 -+static int avf_output(struct ngene_channel *chan, int state) - { -- struct drxd_config *feconf; -- -- feconf = chan->dev->card_info->fe_config[chan->number]; -- -- if (!dvb_attach(dvb_pll_attach, chan->fe, feconf->pll_address, -- &chan->i2c_adapter, -- feconf->pll_type)) { -- pr_err("No pll(%d) found!\n", feconf->pll_type); -- return -ENODEV; -- } -+ if (chan->dev->card_info->avf[chan->number]) -+ i2c_write_register(&chan->i2c_adapter, -+ chan->dev->card_info->avf[chan->number], -+ 0xf2, state ? 0x89 : 0x80); - return 0; - } - --/****************************************************************************/ --/* EEPROM TAGS **************************************************************/ --/****************************************************************************/ -- --#define MICNG_EE_START 0x0100 --#define MICNG_EE_END 0x0FF0 -- --#define MICNG_EETAG_END0 0x0000 --#define MICNG_EETAG_END1 0xFFFF -- --/* 0x0001 - 0x000F reserved for housekeeping */ --/* 0xFFFF - 0xFFFE reserved for housekeeping */ -- --/* Micronas assigned tags -- EEProm tags for hardware support */ -- --#define MICNG_EETAG_DRXD1_OSCDEVIATION 0x1000 /* 2 Bytes data */ --#define MICNG_EETAG_DRXD2_OSCDEVIATION 0x1001 /* 2 Bytes data */ -- --#define MICNG_EETAG_MT2060_1_1STIF 0x1100 /* 2 Bytes data */ --#define MICNG_EETAG_MT2060_2_1STIF 0x1101 /* 2 Bytes data */ -+/* Viper expander: sw11,sw12,sw21,sw22,i2csw1,i2csw2,tsen1,tsen2 */ - --/* Tag range for OEMs */ -+static int exp_set(struct ngene *dev) -+{ -+ return i2c_write(&dev->channel[0].i2c_adapter, -+ dev->card_info->exp, dev->exp_val); -+} - --#define MICNG_EETAG_OEM_FIRST 0xC000 --#define MICNG_EETAG_OEM_LAST 0xFFEF -+static int exp_init(struct ngene *dev) -+{ -+ if (!dev->card_info->exp) -+ return 0; -+ dev->exp_val = dev->card_info->exp_init; -+ return exp_set(dev); -+} - --static int i2c_write_eeprom(struct i2c_adapter *adapter, -- u8 adr, u16 reg, u8 data) -+static int exp_set_bit(struct ngene *dev, int bit, int val) - { -- u8 m[3] = {(reg >> 8), (reg & 0xff), data}; -- struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, -- .len = sizeof(m)}; -+ if (val) -+ set_bit(bit, &dev->exp_val); -+ else -+ clear_bit(bit, &dev->exp_val); -+ return exp_set(dev); -+} - -- if (i2c_transfer(adapter, &msg, 1) != 1) { -- pr_err(DEVICE_NAME ": Error writing EEPROM!\n"); -- return -EIO; -+static int viper_switch_ctrl(struct ngene_channel *chan, int type, int val) -+{ -+ switch (type) { -+ case 0: /* I2C tuner gate on/off */ -+ return exp_set_bit(chan->dev, 4 + chan->number, val); -+ case 1: /* Stream: 0=TS 1=ITU */ -+ avf_output(chan, val); -+ return exp_set_bit(chan->dev, 6 + chan->number, val); -+ case 2: /* Input: 0=digital 1=analog antenna input */ -+ exp_set_bit(chan->dev, 0 + chan->number * 2, val ? 0 : 1); -+ exp_set_bit(chan->dev, 1 + chan->number * 2, val ? 1 : 0); -+ break; - } - return 0; - } - --static int i2c_read_eeprom(struct i2c_adapter *adapter, -- u8 adr, u16 reg, u8 *data, int len) -+static int viper_switch_ctrl2(struct ngene_channel *chan, int type, int val) - { -- u8 msg[2] = {(reg >> 8), (reg & 0xff)}; -- struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, -- .buf = msg, .len = 2 }, -- {.addr = adr, .flags = I2C_M_RD, -- .buf = data, .len = len} }; -- -- if (i2c_transfer(adapter, msgs, 2) != 2) { -- pr_err(DEVICE_NAME ": Error reading EEPROM\n"); -- return -EIO; -+ switch (type) { -+ case 0: /* I2C tuner gate on/off */ -+ return exp_set_bit(chan->dev, 4 + chan->number, val); -+ case 1: /* Stream: 0=TS 1=ITU */ -+ avf_output(chan, val); -+ return exp_set_bit(chan->dev, 6 + chan->number, val); -+ case 2: /* Input: 0=digital 1=analog antenna input */ -+ exp_set_bit(chan->dev, 0 + chan->number * 2, val ? 0 : 1); -+ exp_set_bit(chan->dev, 1 + chan->number * 2, 0); -+ break; - } - return 0; - } - --static int ReadEEProm(struct i2c_adapter *adapter, -- u16 Tag, u32 MaxLen, u8 *data, u32 *pLength) -+static int viper_gate_ctrl(struct dvb_frontend *fe, int enable) - { -- int status = 0; -- u16 Addr = MICNG_EE_START, Length, tag = 0; -- u8 EETag[3]; -- -- while (Addr + sizeof(u16) + 1 < MICNG_EE_END) { -- if (i2c_read_eeprom(adapter, 0x50, Addr, EETag, sizeof(EETag))) -- return -1; -- tag = (EETag[0] << 8) | EETag[1]; -- if (tag == MICNG_EETAG_END0 || tag == MICNG_EETAG_END1) -- return -1; -- if (tag == Tag) -- break; -- Addr += sizeof(u16) + 1 + EETag[2]; -- } -- if (Addr + sizeof(u16) + 1 + EETag[2] > MICNG_EE_END) { -- pr_err(DEVICE_NAME -- ": Reached EOEE @ Tag = %04x Length = %3d\n", -- tag, EETag[2]); -- return -1; -- } -- Length = EETag[2]; -- if (Length > MaxLen) -- Length = (u16) MaxLen; -- if (Length > 0) { -- Addr += sizeof(u16) + 1; -- status = i2c_read_eeprom(adapter, 0x50, Addr, data, Length); -- if (!status) { -- *pLength = EETag[2]; --#if 0 -- if (Length < EETag[2]) -- status = STATUS_BUFFER_OVERFLOW; -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19) -+ struct ngene_channel *chan = fe->misc_priv; -+#else /* Why is there no misc_priv available anymore !?!?! */ -+ /* Well, just abuse sec :-) */ -+ struct ngene_channel *chan = fe->sec_priv; - #endif -- } -- } -- return status; -+ struct ngene *dev = chan->dev; -+ -+ return dev->card_info->switch_ctrl(chan, 0, enable); - } - --static int WriteEEProm(struct i2c_adapter *adapter, -- u16 Tag, u32 Length, u8 *data) -+static int python_switch_ctrl(struct ngene_channel *chan, int type, int val) - { -- int status = 0; -- u16 Addr = MICNG_EE_START; -- u8 EETag[3]; -- u16 tag = 0; -- int retry, i; -- -- while (Addr + sizeof(u16) + 1 < MICNG_EE_END) { -- if (i2c_read_eeprom(adapter, 0x50, Addr, EETag, sizeof(EETag))) -- return -1; -- tag = (EETag[0] << 8) | EETag[1]; -- if (tag == MICNG_EETAG_END0 || tag == MICNG_EETAG_END1) -- return -1; -- if (tag == Tag) -- break; -- Addr += sizeof(u16) + 1 + EETag[2]; -- } -- if (Addr + sizeof(u16) + 1 + EETag[2] > MICNG_EE_END) { -- pr_err(DEVICE_NAME -- ": Reached EOEE @ Tag = %04x Length = %3d\n", -- tag, EETag[2]); -- return -1; -- } -- -- if (Length > EETag[2]) -- return -EINVAL; -- /* Note: We write the data one byte at a time to avoid -- issues with page sizes. (which are different for -- each manufacture and eeprom size) -- */ -- Addr += sizeof(u16) + 1; -- for (i = 0; i < Length; i++, Addr++) { -- status = i2c_write_eeprom(adapter, 0x50, Addr, data[i]); -- -- if (status) -- break; -- -- /* Poll for finishing write cycle */ -- retry = 10; -- while (retry) { -- u8 Tmp; -- -- msleep(50); -- status = i2c_read_eeprom(adapter, 0x50, Addr, &Tmp, 1); -- if (status) -- break; -- if (Tmp != data[i]) -- pr_err(DEVICE_NAME -- "eeprom write error\n"); -- retry -= 1; -- } -- if (status) { -- pr_err(DEVICE_NAME -- ": Timeout polling eeprom\n"); -- break; -- } -+ switch (type) { -+ case 0: /* I2C tuner gate on/off */ -+ if (chan->number > 1) -+ return -EINVAL; -+ return ngene_command_gpio_set(chan->dev, 3 + chan->number, val); -+ case 1: /* Stream: 0=TS 1=ITU */ -+ avf_output(chan, val); -+ return 0; - } -- return status; -+ return 0; - } - --static int eeprom_read_ushort(struct i2c_adapter *adapter, u16 tag, u16 *data) -+static int viper_reset_xc(struct dvb_frontend *fe) - { -- int stat; -- u8 buf[2]; -- u32 len = 0; -- -- stat = ReadEEProm(adapter, tag, 2, buf, &len); -- if (stat) -- return stat; -- if (len != 2) -- return -EINVAL; -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19) -+ struct ngene_channel *chan = fe->misc_priv; -+#else -+ struct ngene_channel *chan = fe->sec_priv; -+#endif -+ struct ngene *dev = chan->dev; - -- *data = (buf[0] << 8) | buf[1]; -- return 0; --} -+ printk(KERN_INFO DEVICE_NAME ": Reset XC3028\n"); - --static int eeprom_write_ushort(struct i2c_adapter *adapter, u16 tag, u16 data) --{ -- int stat; -- u8 buf[2]; -+ if (chan->number > 1) -+ return -EINVAL; - -- buf[0] = data >> 8; -- buf[1] = data & 0xff; -- stat = WriteEEProm(adapter, tag, 2, buf); -- if (stat) -- return stat; -+ ngene_command_gpio_set(dev, 3 + chan->number, 0); -+ msleep(150); -+ ngene_command_gpio_set(dev, 3 + chan->number, 1); - return 0; - } - --static s16 osc_deviation(void *priv, s16 deviation, int flag) -+static int python_gate_ctrl(struct dvb_frontend *fe, int enable) - { -- struct ngene_channel *chan = priv; -- struct i2c_adapter *adap = &chan->i2c_adapter; -- u16 data = 0; -- -- if (flag) { -- data = (u16) deviation; -- pr_info(DEVICE_NAME ": write deviation %d\n", -- deviation); -- eeprom_write_ushort(adap, 0x1000 + chan->number, data); -- } else { -- if (eeprom_read_ushort(adap, 0x1000 + chan->number, &data)) -- data = 0; -- pr_info(DEVICE_NAME ": read deviation %d\n", -- (s16) data); -- } -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19) -+ struct ngene_channel *chan = fe->misc_priv; -+#else /* Why is there no misc_priv available anymore !?!?! */ -+ struct ngene_channel *chan = fe->sec_priv; -+#endif -+ struct ngene *dev = chan->dev; - -- return (s16) data; -+ if (chan->number == 0) -+ return ngene_command_gpio_set(dev, 3, enable); -+ if (chan->number == 1) -+ return ngene_command_gpio_set(dev, 4, enable); -+ return -EINVAL; - } -- --/****************************************************************************/ --/* Switch control (I2C gates, etc.) *****************************************/ --/****************************************************************************/ -- -+#endif - - static struct stv090x_config fe_cineS2 = { - .device = STV0900, -@@ -696,7 +915,7 @@ static struct ngene_info ngene_info_m780 = { - .demod_attach = { NULL, demod_attach_lg330x }, - - /* Ensure these are NULL else the frame will call them (as funcs) */ -- .tuner_attach = { NULL, NULL, NULL, NULL }, -+ .tuner_attach = { 0, 0, 0, 0 }, - .fe_config = { NULL, &aver_m780 }, - .avf = { 0 }, - -@@ -705,14 +924,18 @@ static struct ngene_info ngene_info_m780 = { - .fw_version = 15, ++MODULE_VERSION("0.6"); +diff --git a/drivers/media/platform/sti/c8sectpfe/c8sectpfe-dvb.c b/drivers/media/platform/sti/c8sectpfe/c8sectpfe-dvb.c +index 2c0015b..03688ee 100644 +--- a/drivers/media/platform/sti/c8sectpfe/c8sectpfe-dvb.c ++++ b/drivers/media/platform/sti/c8sectpfe/c8sectpfe-dvb.c +@@ -111,6 +111,7 @@ static struct tda18212_config tda18212_conf = { + .if_dvbt_7 = 4150, + .if_dvbt_8 = 4500, + .if_dvbc = 5000, ++ .init_flags = 0, }; -+/****************************************************************************/ -+ -+#if 0 - static struct drxd_config fe_terratec_dvbt_0 = { - .index = 0, - .demod_address = 0x70, - .demod_revision = 0xa2, - .demoda_address = 0x00, - .pll_address = 0x60, -- .pll_type = DVB_PLL_THOMSON_DTT7520X, -+ .pll_type = DRXD_PLL_DTT7520X, - .clock = 20000, -+ .pll_set = ngene_pll_set_th_dtt7520x, - .osc_deviation = osc_deviation, - }; - -@@ -722,8 +945,9 @@ static struct drxd_config fe_terratec_dvbt_1 = { - .demod_revision = 0xa2, - .demoda_address = 0x00, - .pll_address = 0x60, -- .pll_type = DVB_PLL_THOMSON_DTT7520X, -+ .pll_type = DRXD_PLL_DTT7520X, - .clock = 20000, -+ .pll_set = ngene_pll_set_th_dtt7520x, - .osc_deviation = osc_deviation, - }; - -@@ -732,13 +956,293 @@ static struct ngene_info ngene_info_terratec = { - .name = "Terratec Integra/Cinergy2400i Dual DVB-T", - .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, - .demod_attach = {demod_attach_drxd, demod_attach_drxd}, -- .tuner_attach = {tuner_attach_dtt7520x, tuner_attach_dtt7520x}, - .fe_config = {&fe_terratec_dvbt_0, &fe_terratec_dvbt_1}, - .i2c_access = 1, - }; - - /****************************************************************************/ - -+static struct mt2060_config tuner_python_0 = { -+ .i2c_address = 0x60, -+ .clock_out = 3, -+ .input = 0 -+}; -+ -+static struct mt2060_config tuner_python_1 = { -+ .i2c_address = 0x61, -+ .clock_out = 3, -+ .input = 1 -+}; -+ -+static struct drxd_config fe_python_0 = { -+ .index = 0, -+ .demod_address = 0x71, -+ .demod_revision = 0xb1, -+ .demoda_address = 0x41, -+ .clock = 16000, -+ .osc_deviation = osc_deviation, -+}; -+ -+static struct drxd_config fe_python_1 = { -+ .index = 1, -+ .demod_address = 0x70, -+ .demod_revision = 0xb1, -+ .demoda_address = 0x45, -+ .clock = 16000, -+ .osc_deviation = osc_deviation, -+}; -+ -+static struct ngene_info ngene_info_python = { -+ .type = NGENE_PYTHON, -+ .name = "Micronas MicPython/Hedgehog Dual DVB-T", -+ .io_type = {NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_AIN, NGENE_IO_AIN}, -+ .demod_attach = {demod_attach_drxd, demod_attach_drxd}, -+ .tuner_attach = {tuner_attach_mt2060, tuner_attach_mt2060}, -+ .fe_config = {&fe_python_0, &fe_python_1}, -+ .tuner_config = {&tuner_python_0, &tuner_python_1}, -+ .avf = {0x43, 0x47}, -+ .msp = {0x40, 0x42}, -+ .demoda = {0x41, 0x45}, -+ .gate_ctrl = python_gate_ctrl, -+ .switch_ctrl = python_switch_ctrl, -+}; -+ -+/****************************************************************************/ -+ -+static struct drxd_config fe_appb_dvbt_0 = { -+ .index = 0, -+ .demod_address = 0x71, -+ .demod_revision = 0xa2, -+ .demoda_address = 0x41, -+ .pll_address = 0x63, -+ .pll_type = DRXD_PLL_MT3X0823, -+ .clock = 20000, -+ .pll_set = ngene_pll_set_mt_3x0823, -+ .osc_deviation = osc_deviation, -+}; -+ -+static struct drxd_config fe_appb_dvbt_1 = { -+ .index = 1, -+ .demod_address = 0x70, -+ .demod_revision = 0xa2, -+ .demoda_address = 0x45, -+ .pll_address = 0x60, -+ .pll_type = DRXD_PLL_MT3X0823, -+ .clock = 20000, -+ .pll_set = ngene_pll_set_mt_3x0823, -+ .osc_deviation = osc_deviation, -+}; -+ -+static struct ngene_info ngene_info_appboard = { -+ .type = NGENE_APP, -+ .name = "Micronas Application Board Dual DVB-T", -+ .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, -+ .demod_attach = {demod_attach_drxd, demod_attach_drxd}, -+ .fe_config = {&fe_appb_dvbt_0, &fe_appb_dvbt_1}, -+ .avf = {0x43, 0x47}, -+}; -+ -+static struct ngene_info ngene_info_appboard_ntsc = { -+ .type = NGENE_APP, -+ .name = "Micronas Application Board Dual DVB-T", -+ .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, -+ .demod_attach = {demod_attach_drxd, demod_attach_drxd}, -+ .fe_config = {&fe_appb_dvbt_0, &fe_appb_dvbt_1}, -+ .avf = {0x43, 0x47}, -+ .ntsc = 1, -+}; -+ -+/****************************************************************************/ -+ -+static struct stb0899_config fe_sidewinder_0 = { -+ .demod_address = 0x68, -+ .pll_address = 0x63, -+}; -+ -+static struct stb0899_config fe_sidewinder_1 = { -+ .demod_address = 0x6b, -+ .pll_address = 0x60, -+}; -+ -+static struct ngene_info ngene_info_sidewinder = { -+ .type = NGENE_SIDEWINDER, -+ .name = "Micronas MicSquirrel/Sidewinder Dual DVB-S2", -+ .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, -+ .demod_attach = {demod_attach_stb0899, demod_attach_stb0899}, -+ .fe_config = {&fe_sidewinder_0, &fe_sidewinder_1}, -+ .lnb = {0x0b, 0x08}, -+}; -+ -+/****************************************************************************/ -+/* Yet unnamed S2 card with dual DVB-S2 demod */ -+/****************************************************************************/ -+ -+static struct stv0900_config fe_s2_0 = { -+ .addr = 0x68, -+ .pll = 0x63, -+ .pll_type = 0, -+ .nr = 0, -+}; -+ -+static struct stv0900_config fe_s2_1 = { -+ .addr = 0x68, -+ .pll = 0x60, -+ .pll_type = 0, -+ .nr = 1, -+}; -+ -+static struct ngene_info ngene_info_s2 = { -+ .type = NGENE_SIDEWINDER, -+ .name = "S2", -+ .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN, -+ NGENE_IO_TSIN, NGENE_IO_TSIN}, -+ .demod_attach = {demod_attach_stv0900, demod_attach_stv0900}, -+ .fe_config = {&fe_s2_0, &fe_s2_1}, -+ .lnb = {0x0b, 0x08}, -+ .tsf = {3, 3}, -+ .fw_version = 15, -+}; -+ -+static struct stv0900_config fe_s2b_0 = { -+ .addr = 0x68, -+ .pll = 0x60, -+ .pll_type = 0x10, -+ .nr = 0, -+}; -+ -+static struct stv0900_config fe_s2b_1 = { -+ .addr = 0x68, -+ .pll = 0x63, -+ .pll_type = 0x10, -+ .nr = 1, -+}; -+ -+static struct ngene_info ngene_info_s2_b = { -+ .type = NGENE_SIDEWINDER, -+ .name = "S2 V2", -+ .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN, -+ NGENE_IO_TSIN, NGENE_IO_TSIN}, -+ .demod_attach = {demod_attach_stv0900, demod_attach_stv0900}, -+ .fe_config = {&fe_s2b_0, &fe_s2b_1}, -+ .lnb = {0x0b, 0x08}, -+ .tsf = {3, 3}, -+ .fw_version = 17, -+}; -+ -+/****************************************************************************/ -+ -+static struct xc3028_config tuner_viper_0 = { -+ .adr = 0x61, -+ .reset = viper_reset_xc -+}; -+ -+static struct xc3028_config tuner_viper_1 = { -+ .adr = 0x64, -+ .reset = viper_reset_xc -+}; -+ -+static struct drxh_config fe_viper_h_0 = {.adr = 0x2b}; -+ -+static struct drxh_config fe_viper_h_1 = {.adr = 0x29}; -+ -+static struct drxh_config fe_viper_l_0 = {.adr = 0x2b, .type = 3931}; -+ -+static struct drxh_config fe_viper_l_1 = {.adr = 0x29, .type = 3931}; -+ -+static struct ngene_info ngene_info_viper_v1 = { -+ .type = NGENE_VIPER, -+ .name = "Micronas MicViper Dual ATSC DRXH", -+ .io_type = {NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_AIN, NGENE_IO_AIN}, -+ .demod_attach = {demod_attach_drxh, demod_attach_drxh}, -+ .fe_config = {&fe_viper_h_0, &fe_viper_h_1}, -+ .tuner_config = {&tuner_viper_0, &tuner_viper_1}, -+ .tuner_attach = {tuner_attach_xc3028, tuner_attach_xc3028}, -+ .avf = {0x43, 0x47}, -+ .msp = {0x40, 0x42}, -+ .exp = 0x20, -+ .exp_init = 0xf5, -+ .gate_ctrl = viper_gate_ctrl, -+ .switch_ctrl = viper_switch_ctrl, -+ .tsf = {2, 2}, -+}; -+ -+static struct ngene_info ngene_info_viper_v2 = { -+ .type = NGENE_VIPER, -+ .name = "Micronas MicViper Dual ATSC DRXL", -+ .io_type = {NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_AIN, NGENE_IO_AIN}, -+ .demod_attach = {demod_attach_drxh, demod_attach_drxh}, -+ .fe_config = {&fe_viper_l_0, &fe_viper_l_1}, -+ .tuner_config = {&tuner_viper_0, &tuner_viper_1}, -+ .tuner_attach = {tuner_attach_xc3028, tuner_attach_xc3028}, -+ .avf = {0x43, 0x47}, -+ .msp = {0x40, 0x42}, -+ .exp = 0x38, -+ .exp_init = 0xf5, -+ .gate_ctrl = viper_gate_ctrl, -+ .switch_ctrl = viper_switch_ctrl, -+ .tsf = {2, 2}, -+}; -+ -+/****************************************************************************/ -+ -+static struct ngene_info ngene_info_vbox_v1 = { -+ .type = NGENE_VBOX_V1, -+ .name = "VBox Cat's Eye 164E", -+ .io_type = {NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_AIN, NGENE_IO_AIN}, -+ .demod_attach = {demod_attach_drxh, demod_attach_drxh}, -+ .fe_config = {&fe_viper_h_0, &fe_viper_h_1}, -+ .tuner_config = {&tuner_viper_0, &tuner_viper_1}, -+ .tuner_attach = {tuner_attach_xc3028, tuner_attach_xc3028}, -+ .avf = {0x43, 0x47}, -+ .msp = {0x40, 0x42}, -+ .exp = 0x20, -+ .exp_init = 0xf5, -+ .gate_ctrl = viper_gate_ctrl, -+ .switch_ctrl = viper_switch_ctrl, -+ .tsf = {2, 2}, -+}; -+ -+/****************************************************************************/ -+ -+static struct ngene_info ngene_info_vbox_v2 = { -+ .type = NGENE_VBOX_V2, -+ .name = "VBox Cat's Eye 164E", -+ .io_type = {NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_TSIN | NGENE_IO_TV, -+ NGENE_IO_AIN, NGENE_IO_AIN}, -+ .demod_attach = {demod_attach_drxh, demod_attach_drxh}, -+ .fe_config = {&fe_viper_h_0, &fe_viper_h_1}, -+ .tuner_config = {&tuner_viper_0, &tuner_viper_1}, -+ .tuner_attach = {tuner_attach_xc3028, tuner_attach_xc3028}, -+ .avf = {0x43, 0x47}, -+ .msp = {0x40, 0x42}, -+ .exp = 0x20, -+ .exp_init = 0xf5, -+ .gate_ctrl = viper_gate_ctrl, -+ .switch_ctrl = viper_switch_ctrl2, -+ .tsf = {2, 2}, -+}; -+ -+/****************************************************************************/ -+ -+static struct ngene_info ngene_info_racer = { -+ .type = NGENE_RACER, -+ .name = "Micronas MicRacer HDTV Decoder Card", -+ .io_type = {NGENE_IO_HDTV, NGENE_IO_NONE, -+ NGENE_IO_AIN, NGENE_IO_NONE, -+ NGENE_IO_TSOUT}, -+ .i2s = {0, 0, 1, 0}, -+ .fw_version = 17, -+}; -+#endif - - - /****************************************************************************/ -@@ -753,6 +1257,8 @@ static struct ngene_info ngene_info_terratec = { - /****************************************************************************/ - - static const struct pci_device_id ngene_id_tbl[] = { -+ NGENE_ID(0x18c3, 0xab04, ngene_info_cineS2), -+ NGENE_ID(0x18c3, 0xab05, ngene_info_cineS2v5), - NGENE_ID(0x18c3, 0xabc3, ngene_info_cineS2), - NGENE_ID(0x18c3, 0xabc4, ngene_info_cineS2), - NGENE_ID(0x18c3, 0xdb01, ngene_info_satixS2), -@@ -761,7 +1267,32 @@ static const struct pci_device_id ngene_id_tbl[] = { - NGENE_ID(0x18c3, 0xdd10, ngene_info_duoFlex), - NGENE_ID(0x18c3, 0xdd20, ngene_info_duoFlex), - NGENE_ID(0x1461, 0x062e, ngene_info_m780), -+#if 0 /* not (yet?) supported */ -+ NGENE_ID(0x18c3, 0x0000, ngene_info_appboard), -+ NGENE_ID(0x18c3, 0x0004, ngene_info_appboard), -+ NGENE_ID(0x18c3, 0x8011, ngene_info_appboard), -+ NGENE_ID(0x18c3, 0x8015, ngene_info_appboard_ntsc), - NGENE_ID(0x153b, 0x1167, ngene_info_terratec), -+ NGENE_ID(0x18c3, 0x0030, ngene_info_python), -+ NGENE_ID(0x18c3, 0x0052, ngene_info_sidewinder), -+ NGENE_ID(0x18c3, 0x8f00, ngene_info_racer), -+ NGENE_ID(0x18c3, 0x0041, ngene_info_viper_v1), -+ NGENE_ID(0x18c3, 0x0042, ngene_info_viper_v2), -+ NGENE_ID(0x14f3, 0x0041, ngene_info_vbox_v1), -+ NGENE_ID(0x14f3, 0x0043, ngene_info_vbox_v2), -+ NGENE_ID(0x18c3, 0xabcd, ngene_info_s2), -+ NGENE_ID(0x18c3, 0xabc2, ngene_info_s2_b), -+ NGENE_ID(0x18c3, 0xabc3, ngene_info_s2_b), -+ NGENE_ID(0x18c3, 0x0001, ngene_info_appboard), -+ NGENE_ID(0x18c3, 0x0005, ngene_info_appboard), -+ NGENE_ID(0x18c3, 0x0009, ngene_info_appboard_atsc), -+ NGENE_ID(0x18c3, 0x000b, ngene_info_appboard_atsc), -+ NGENE_ID(0x18c3, 0x0010, ngene_info_shrek_50_fp), -+ NGENE_ID(0x18c3, 0x0011, ngene_info_shrek_60_fp), -+ NGENE_ID(0x18c3, 0x0012, ngene_info_shrek_50), -+ NGENE_ID(0x18c3, 0x0013, ngene_info_shrek_60), -+ NGENE_ID(0x18c3, 0x0000, ngene_info_hognose), -+#endif - {0} - }; - MODULE_DEVICE_TABLE(pci, ngene_id_tbl); -@@ -798,7 +1329,7 @@ static void ngene_resume(struct pci_dev *dev) - printk(KERN_INFO DEVICE_NAME ": resume\n"); - } - --static const struct pci_error_handlers ngene_errors = { -+static struct pci_error_handlers ngene_errors = { - .error_detected = ngene_error_detected, - .link_reset = ngene_link_reset, - .slot_reset = ngene_slot_reset, -diff --git a/drivers/media/pci/ngene/ngene-core.c b/drivers/media/pci/ngene/ngene-core.c -index e29bc3af..84510db 100644 ---- a/drivers/media/pci/ngene/ngene-core.c -+++ b/drivers/media/pci/ngene/ngene-core.c -@@ -57,13 +57,15 @@ DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); - - #define dprintk if (debug) printk - --#define ngwriteb(dat, adr) writeb((dat), dev->iomem + (adr)) --#define ngwritel(dat, adr) writel((dat), dev->iomem + (adr)) --#define ngwriteb(dat, adr) writeb((dat), dev->iomem + (adr)) -+#define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr))) -+#define ngwritel(dat, adr) writel((dat), (char *)(dev->iomem + (adr))) -+#define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr))) - #define ngreadl(adr) readl(dev->iomem + (adr)) - #define ngreadb(adr) readb(dev->iomem + (adr)) --#define ngcpyto(adr, src, count) memcpy_toio(dev->iomem + (adr), (src), (count)) --#define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), dev->iomem + (adr), (count)) -+#define ngcpyto(adr, src, count) memcpy_toio((char *) \ -+ (dev->iomem + (adr)), (src), (count)) -+#define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \ -+ (dev->iomem + (adr)), (count)) - - /****************************************************************************/ - /* nGene interrupt handler **************************************************/ -@@ -84,6 +86,14 @@ static void event_tasklet(unsigned long data) - if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify)) - dev->RxEventNotify(dev, Event.TimeStamp, - Event.RXCharacter); -+#if 0 -+ if ((Event.GPIOStatus & 0x80) && (dev->Gpio2EventNotify)) -+ dev->Gpio2EventNotify(dev, Event.TimeStamp, -+ Event.GPIOStatus & 0x1f); -+ if ((Event.GPIOStatus & 0x40) && (dev->Gpio3EventNotify)) -+ dev->Gpio3EventNotify(dev, Event.TimeStamp, -+ Event.GPIOStatus & 0x1f); -+#endif - } - } - -@@ -212,6 +222,13 @@ static irqreturn_t irq_handler(int irq, void *dev_id) - u8 nextWriteIndex = - (dev->EventQueueWriteIndex + 1) & - (EVENT_QUEUE_SIZE - 1); -+#if 0 -+ printk(KERN_ERR DEVICE_NAME -+ ": Event interrupt %02x Uart = %02x Gpio = %02x\n", -+ dev->EventBuffer->EventStatus, -+ dev->EventBuffer->UARTStatus, -+ dev->EventBuffer->GPIOStatus); -+#endif - if (nextWriteIndex != dev->EventQueueReadIndex) { - dev->EventQueue[dev->EventQueueWriteIndex] = - *(dev->EventBuffer); -@@ -256,16 +273,22 @@ static void dump_command_io(struct ngene *dev) - u8 buf[8], *b; - - ngcpyfrom(buf, HOST_TO_NGENE, 8); -- printk(KERN_ERR "host_to_ngene (%04x): %*ph\n", HOST_TO_NGENE, 8, buf); -+ printk(KERN_ERR "host_to_ngene (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n", -+ HOST_TO_NGENE, buf[0], buf[1], buf[2], buf[3], -+ buf[4], buf[5], buf[6], buf[7]); - - ngcpyfrom(buf, NGENE_TO_HOST, 8); -- printk(KERN_ERR "ngene_to_host (%04x): %*ph\n", NGENE_TO_HOST, 8, buf); -+ printk(KERN_ERR "ngene_to_host (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n", -+ NGENE_TO_HOST, buf[0], buf[1], buf[2], buf[3], -+ buf[4], buf[5], buf[6], buf[7]); - - b = dev->hosttongene; -- printk(KERN_ERR "dev->hosttongene (%p): %*ph\n", b, 8, b); -+ printk(KERN_ERR "dev->hosttongene (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n", -+ b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]); - - b = dev->ngenetohost; -- printk(KERN_ERR "dev->ngenetohost (%p): %*ph\n", b, 8, b); -+ printk(KERN_ERR "dev->ngenetohost (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n", -+ b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]); - } - - static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com) -@@ -314,12 +337,24 @@ static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com) - ngwritel(1, FORCE_INT); - - ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ); -+#if 0 -+ if (ret < 0) -+ return ret; -+ if (!dev->cmd_done) -+ ; -+#endif - if (!ret) { - /*ngwritel(0, FORCE_NMI);*/ - - printk(KERN_ERR DEVICE_NAME - ": Command timeout cmd=%02x prev=%02x\n", - com->cmd.hdr.Opcode, dev->prev_cmd); -+#if 0 -+ printk(KERN_ERR DEVICE_NAME ": Icounts=%08x\n", -+ ngreadl(NGENE_INT_COUNTS)); -+ if (ngreadl(NGENE_INT_COUNTS) == 0xffffffff) -+ ngwritel(0, NGENE_INT_ENABLE); -+#endif - dump_command_io(dev); - return -1; - } -@@ -346,6 +381,19 @@ int ngene_command(struct ngene *dev, struct ngene_command *com) - return result; - } - -+#if 0 -+int ngene_command_nop(struct ngene *dev) -+{ -+ struct ngene_command com; -+ -+ com.cmd.hdr.Opcode = CMD_NOP; -+ com.cmd.hdr.Length = 0; -+ com.in_len = 0; -+ com.out_len = 0; -+ -+ return ngene_command(dev, &com); -+} -+#endif - - static int ngene_command_load_firmware(struct ngene *dev, - u8 *ngene_fw, u32 size) -@@ -380,6 +428,83 @@ static int ngene_command_load_firmware(struct ngene *dev, - return ngene_command(dev, &com); - } - -+#if 0 -+int ngene_command_imem_read(struct ngene *dev, u8 adr, u8 *data, int type) -+{ -+ struct ngene_command com; -+ -+ com.cmd.hdr.Opcode = type ? CMD_SFR_READ : CMD_IRAM_READ; -+ com.cmd.hdr.Length = 1; -+ com.cmd.SfrIramRead.address = adr; -+ com.in_len = 1; -+ com.out_len = 2; -+ -+ if (ngene_command(dev, &com) < 0) -+ return -EIO; -+ -+ *data = com.cmd.raw8[1]; -+ return 0; -+} -+ -+int ngene_command_imem_write(struct ngene *dev, u8 adr, u8 data, int type) -+{ -+ struct ngene_command com; -+ -+ com.cmd.hdr.Opcode = type ? CMD_SFR_WRITE : CMD_IRAM_WRITE; -+ com.cmd.hdr.Length = 2; -+ com.cmd.SfrIramWrite.address = adr; -+ com.cmd.SfrIramWrite.data = data; -+ com.in_len = 2; -+ com.out_len = 1; -+ -+ if (ngene_command(dev, &com) < 0) -+ return -EIO; -+ -+ return 0; -+} -+ -+static int ngene_command_config_uart(struct ngene *dev, u8 config, -+ tx_cb_t *tx_cb, rx_cb_t *rx_cb) -+{ -+ struct ngene_command com; -+ -+ com.cmd.hdr.Opcode = CMD_CONFIGURE_UART; -+ com.cmd.hdr.Length = sizeof(struct FW_CONFIGURE_UART) - 2; -+ com.cmd.ConfigureUart.UartControl = config; -+ com.in_len = sizeof(struct FW_CONFIGURE_UART); -+ com.out_len = 0; -+ -+ if (ngene_command(dev, &com) < 0) -+ return -EIO; -+ -+ dev->TxEventNotify = tx_cb; -+ dev->RxEventNotify = rx_cb; -+ -+ dprintk(KERN_DEBUG DEVICE_NAME ": Set UART config %02x.\n", config); -+ -+ return 0; -+} -+ -+static void tx_cb(struct ngene *dev, u32 ts) -+{ -+ dev->tx_busy = 0; -+ wake_up_interruptible(&dev->tx_wq); -+} -+ -+static void rx_cb(struct ngene *dev, u32 ts, u8 c) -+{ -+ int rp = dev->uart_rp; -+ int nwp, wp = dev->uart_wp; -+ -+ /* dprintk(KERN_DEBUG DEVICE_NAME ": %c\n", c); */ -+ nwp = (wp + 1) % (UART_RBUF_LEN); -+ if (nwp == rp) -+ return; -+ dev->uart_rbuf[wp] = c; -+ dev->uart_wp = nwp; -+ wake_up_interruptible(&dev->rx_wq); -+} -+#endif - - static int ngene_command_config_buf(struct ngene *dev, u8 config) - { -@@ -425,6 +550,18 @@ int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level) - return ngene_command(dev, &com); - } - -+#if 0 -+/* The reset is only wired to GPIO4 on MicRacer Revision 1.10 ! -+ Also better set bootdelay to 1 in nvram or less. */ -+static void ngene_reset_decypher(struct ngene *dev) -+{ -+ printk(KERN_INFO DEVICE_NAME ": Resetting Decypher.\n"); -+ ngene_command_gpio_set(dev, 4, 0); -+ msleep(1); -+ ngene_command_gpio_set(dev, 4, 1); -+ msleep(2000); -+} -+#endif - - /* - 02000640 is sample on rising edge. -@@ -510,6 +647,17 @@ void FillTSBuffer(void *Buffer, int Length, u32 Flags) - } - } - -+#if 0 -+static void clear_tsin(struct ngene_channel *chan) -+{ -+ struct SBufferHeader *Cur = chan->nextBuffer; -+ -+ do { -+ memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR)); -+ Cur = Cur->Next; -+ } while (Cur != chan->nextBuffer); -+} -+#endif - - static void flush_buffers(struct ngene_channel *chan) - { -@@ -730,6 +878,14 @@ void set_transfer(struct ngene_channel *chan, int state) - if (dev->card_info->switch_ctrl) - dev->card_info->switch_ctrl(chan, 1, state ^ 1); - -+#if 0 -+ /* Disable AVF output if present. */ -+ if (dev->card_info->avf[chan->number]) -+ i2c_write_register(&chan->i2c_adapter, -+ chan->dev->card_info->avf[chan->number], -+ 0xf2, state ? 0x80 : 0x89); -+ -+#endif - if (state) { - spin_lock_irq(&chan->state_lock); - -@@ -750,8 +906,8 @@ void set_transfer(struct ngene_channel *chan, int state) - if (chan->mode & NGENE_IO_TSIN) - chan->pBufferExchange = tsin_exchange; - spin_unlock_irq(&chan->state_lock); -- } -- /* else printk(KERN_INFO DEVICE_NAME ": lock=%08x\n", -+ } else -+ ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n", - ngreadl(0x9310)); */ - - ret = ngene_command_stream_control(dev, chan->number, -@@ -769,6 +925,89 @@ void set_transfer(struct ngene_channel *chan, int state) - } - } - -+#if 0 -+/****************************************************************************/ -+/* Decypher firmware loading ************************************************/ -+/****************************************************************************/ -+ -+#define DECYPHER_FW "decypher.fw" -+ -+static int dec_ts_send(struct ngene *dev, u8 *buf, u32 len) -+{ -+#if 0 -+ if (wait_event_interruptible(dev->tsout_rbuf.queue, -+ dvb_ringbuffer_free -+ (&dev->tsout_rbuf) >= len) < 0) -+ return 0; -+#else -+ while (dvb_ringbuffer_free(&dev->tsout_rbuf) < len) -+ msleep(1); -+ -+#endif -+ -+ dvb_ringbuffer_write(&dev->tsout_rbuf, buf, len); -+ -+ return len; -+} -+ -+u8 dec_fw_fill_ts[188] = { 0x47, 0x09, 0x0e, 0x10, 0xff, 0xff, 0x00, 0x00 }; -+ -+int dec_fw_send(struct ngene *dev, u8 *fw, u32 size) -+{ -+ struct ngene_channel *chan = &dev->channel[4]; -+ u32 len = 180, cc = 0; -+ u8 buf[8] = { 0x47, 0x09, 0x0e, 0x10, 0x00, 0x00, 0x00, 0x00 }; -+ -+ set_transfer(chan, 1); -+ msleep(100); -+ while (size) { -+ len = 180; -+ if (len > size) -+ len = size; -+ buf[3] = 0x10 | (cc & 0x0f); -+ buf[4] = (cc >> 8); -+ buf[5] = cc & 0xff; -+ buf[6] = len; -+ -+ dec_ts_send(dev, buf, 8); -+ dec_ts_send(dev, fw, len); -+ if (len < 180) -+ dec_ts_send(dev, dec_fw_fill_ts + len + 8, 180 - len); -+ cc++; -+ size -= len; -+ fw += len; -+ } -+ for (len = 0; len < 512; len++) -+ dec_ts_send(dev, dec_fw_fill_ts, 188); -+ while (dvb_ringbuffer_avail(&dev->tsout_rbuf)) -+ msleep(10); -+ msleep(100); -+ set_transfer(chan, 0); -+ return 0; -+} -+ -+int dec_fw_boot(struct ngene *dev) -+{ -+ u32 size; -+ const struct firmware *fw = NULL; -+ u8 *dec_fw; -+ -+ if (request_firmware(&fw, DECYPHER_FW, &dev->pci_dev->dev) < 0) { -+ printk(KERN_ERR DEVICE_NAME -+ ": %s not found. Check hotplug directory.\n", -+ DECYPHER_FW); -+ return -1; -+ } -+ printk(KERN_INFO DEVICE_NAME ": Booting decypher firmware file %s\n", -+ DECYPHER_FW); -+ -+ size = fw->size; -+ dec_fw = (u8 *)fw->data; -+ dec_fw_send(dev, dec_fw, size); -+ release_firmware(fw); -+ return 0; -+} -+#endif - - /****************************************************************************/ - /* nGene hardware init and release functions ********************************/ -@@ -908,6 +1147,7 @@ static int AllocateRingBuffers(struct pci_dev *pci_dev, - { - dma_addr_t tmp; - u32 i, j; -+ int status = 0; - u32 SCListMemSize = pRingBuffer->NumBuffers - * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) : - NUM_SCATTER_GATHER_ENTRIES) -@@ -1007,12 +1247,14 @@ static int AllocateRingBuffers(struct pci_dev *pci_dev, - - } - -- return 0; -+ return status; - } - - static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer, - struct SRingBufferDescriptor *pRingBuffer) - { -+ int status = 0; -+ - /* Copy pointer to scatter gather list in TSRingbuffer - structure for buffer 2 - Load number of buffer -@@ -1033,7 +1275,7 @@ static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer, - pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1; - Cur = Cur->Next; - } -- return 0; -+ return status; - } - - static u32 RingBufferSizes[MAX_STREAM] = { -@@ -1060,6 +1302,85 @@ static u32 Buffer2Sizes[MAX_STREAM] = { - 0 - }; - -+#if 0 -+static int allocate_buffer(struct pci_dev *pci_dev, dma_addr_t of, -+ struct SRingBufferDescriptor *rbuf, -+ u32 entries, u32 size1, u32 size2) -+{ -+ if (create_ring_buffer(pci_dev, rbuf, entries) < 0) -+ return -ENOMEM; -+ -+ if (AllocateRingBuffers(pci_dev, of, rbuf, size1, size2) < 0) -+ return -ENOMEM; -+ -+ return 0; -+} -+ -+static int channel_allocate_buffers(struct ngene_channel *chan) -+{ -+ struct ngene *dev = chan->dev; -+ int type = dev->card_info->io_type[chan->number]; -+ int status; -+ -+ chan->State = KSSTATE_STOP; -+ -+ if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) { -+ status = create_ring_buffer(dev->pci_dev, -+ &chan->RingBuffer, -+ RingBufferSizes[chan->number]); -+ if (status < 0) -+ return -ENOMEM; -+ -+ if (type & (NGENE_IO_TV | NGENE_IO_AIN)) { -+ status = AllocateRingBuffers(dev->pci_dev, -+ dev->PAOverflowBuffer, -+ &chan->RingBuffer, -+ Buffer1Sizes[chan->number], -+ Buffer2Sizes[chan-> -+ number]); -+ if (status < 0) -+ return -ENOMEM; -+ } else if (type & NGENE_IO_HDTV) { -+ status = AllocateRingBuffers(dev->pci_dev, -+ dev->PAOverflowBuffer, -+ &chan->RingBuffer, -+ MAX_HDTV_BUFFER_SIZE, 0); -+ if (status < 0) -+ return -ENOMEM; -+ } -+ } -+ -+ if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { -+ -+ status = create_ring_buffer(dev->pci_dev, -+ &chan->TSRingBuffer, RING_SIZE_TS); -+ if (status < 0) -+ return -ENOMEM; -+ -+ status = AllocateRingBuffers(dev->pci_dev, -+ dev->PAOverflowBuffer, -+ &chan->TSRingBuffer, -+ MAX_TS_BUFFER_SIZE, 0); -+ if (status) -+ return -ENOMEM; -+ } -+ -+ if (type & NGENE_IO_TSOUT) { -+ status = create_ring_buffer(dev->pci_dev, -+ &chan->TSIdleBuffer, 1); -+ if (status < 0) -+ return -ENOMEM; -+ status = AllocateRingBuffers(dev->pci_dev, -+ dev->PAOverflowBuffer, -+ &chan->TSIdleBuffer, -+ MAX_TS_BUFFER_SIZE, 0); -+ if (status) -+ return -ENOMEM; -+ FillTSIdleBuffer(&chan->TSIdleBuffer, &chan->TSRingBuffer); -+ } -+ return 0; -+} -+#endif - - static int AllocCommonBuffers(struct ngene *dev) - { -@@ -1073,11 +1394,12 @@ static int AllocCommonBuffers(struct ngene *dev) - dev->ngenetohost = dev->FWInterfaceBuffer + 256; - dev->EventBuffer = dev->FWInterfaceBuffer + 512; - -- dev->OverflowBuffer = pci_zalloc_consistent(dev->pci_dev, -- OVERFLOW_BUFFER_SIZE, -- &dev->PAOverflowBuffer); -+ dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev, -+ OVERFLOW_BUFFER_SIZE, -+ &dev->PAOverflowBuffer); - if (!dev->OverflowBuffer) - return -ENOMEM; -+ memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE); - - for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) { - int type = dev->card_info->io_type[i]; -@@ -1312,6 +1634,10 @@ static int ngene_buffer_config(struct ngene *dev) - u8 tsin12_config[6] = { 0x60, 0x60, 0x00, 0x00, 0x00, 0x00 }; - u8 tsin1234_config[6] = { 0x30, 0x30, 0x00, 0x30, 0x30, 0x00 }; - u8 tsio1235_config[6] = { 0x30, 0x30, 0x00, 0x28, 0x00, 0x38 }; -+#if 0 -+ u8 tsin34_config[6] = { 0x00, 0x00, 0x00, 0x60, 0x60, 0x00 }; -+ u8 tsio35_config[6] = { 0x00, 0x00, 0x00, 0x60, 0x00, 0x60 }; -+#endif - u8 *bconf = tsin12_config; - - if (dev->card_info->io_type[2]&NGENE_IO_TSIN && -@@ -1321,10 +1647,22 @@ static int ngene_buffer_config(struct ngene *dev) - dev->ci.en) - bconf = tsio1235_config; - } -+#if 0 -+ if (dev->card_info->io_type[0] == NGENE_IO_HDTV) { -+ bconf = hdtv_config; -+ ngene_reset_decypher(dev); -+ } -+#endif - stat = ngene_command_config_free_buf(dev, bconf); - } else { - int bconf = BUFFER_CONFIG_4422; - -+#if 0 -+ if (dev->card_info->io_type[0] == NGENE_IO_HDTV) { -+ bconf = BUFFER_CONFIG_8022; -+ ngene_reset_decypher(dev); -+ } -+#endif - if (dev->card_info->io_type[3] == NGENE_IO_TSIN) - bconf = BUFFER_CONFIG_3333; - stat = ngene_command_config_buf(dev, bconf); -@@ -1397,8 +1735,10 @@ static int ngene_start(struct ngene *dev) - if (stat < 0) - goto fail; - -- return 0; -+ if (!stat) -+ return stat; - -+ /* otherwise error: fall through */ - fail: - ngwritel(0, NGENE_INT_ENABLE); - free_irq(dev->pci_dev->irq, dev); -@@ -1590,7 +1930,7 @@ static void cxd_detach(struct ngene *dev) - - dvb_ca_en50221_release(ci->en); - kfree(ci->en); -- ci->en = NULL; -+ ci->en = 0; - } - - /***********************************/ -@@ -1616,7 +1956,7 @@ static void ngene_unlink(struct ngene *dev) - - void ngene_shutdown(struct pci_dev *pdev) - { -- struct ngene *dev = pci_get_drvdata(pdev); -+ struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev); - - if (!dev || !shutdown_workaround) - return; -@@ -1642,6 +1982,7 @@ void ngene_remove(struct pci_dev *pdev) - cxd_detach(dev); - ngene_stop(dev); - ngene_release_buffers(dev); -+ pci_set_drvdata(pdev, NULL); - pci_disable_device(pdev); - } - -@@ -1681,10 +2022,36 @@ int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) - - - dev->i2c_current_bus = -1; -+#if 0 -+ exp_init(dev); -+ -+ /* Disable analog TV decoder chips if present */ -+ if (dev->card_info->msp[0]) -+ i2c_write_msp_register(&dev->channel[0].i2c_adapter, -+ dev->card_info->msp[0], 0x00, 0x0000); -+ if (dev->card_info->msp[1]) -+ i2c_write_msp_register(&dev->channel[1].i2c_adapter, -+ dev->card_info->msp[1], 0x00, 0x0000); -+ { -+ u16 data; -+ read_msp(&dev->channel[0].i2c_adapter, -+ dev->card_info->msp[0], 0x00, &data); -+ } -+ if (dev->card_info->avf[0]) -+ i2c_write_register(&dev->channel[0].i2c_adapter, -+ dev->card_info->avf[0], 0xf2, 0x80); -+ if (dev->card_info->avf[1]) -+ i2c_write_register(&dev->channel[1].i2c_adapter, -+ dev->card_info->avf[1], 0xf2, 0x80); -+ if (copy_eeprom) { -+ i2c_copy_eeprom(&dev->channel[0].i2c_adapter, 0x50, 0x52); -+ i2c_dump_eeprom(&dev->channel[0].i2c_adapter, 0x52); -+ } -+ /*i2c_check_eeprom(&dev->i2c_adapter);*/ -+#endif - - /* Register DVB adapters and devices for both channels */ -- stat = init_channels(dev); -- if (stat < 0) -+ if (init_channels(dev) < 0) - goto fail2; - - return 0; -@@ -1695,5 +2062,6 @@ fail1: - ngene_release_buffers(dev); - fail0: - pci_disable_device(pci_dev); -+ pci_set_drvdata(pci_dev, NULL); - return stat; - } -diff --git a/drivers/media/pci/ngene/ngene-dvb.c b/drivers/media/pci/ngene/ngene-dvb.c -index 59bb285..8049e2b 100644 ---- a/drivers/media/pci/ngene/ngene-dvb.c -+++ b/drivers/media/pci/ngene/ngene-dvb.c -@@ -42,12 +42,321 @@ - - #include "ngene.h" - -+#if 0 -+int ngene_stream_control(struct ngene *dev, u8 stream, u8 control, u8 mode, -+ u16 lines, u16 bpl, u16 vblines, u16 vbibpl) -+{ -+ if (!(mode & SMODE_TRANSPORT_STREAM)) -+ return -EINVAL; -+ -+ if (lines * bpl > MAX_VIDEO_BUFFER_SIZE) -+ return -EINVAL; -+ -+ if ((mode & SMODE_TRANSPORT_STREAM) && (((bpl * lines) & 0xff) != 0)) -+ return -EINVAL; -+ -+ if ((mode & SMODE_VIDEO_CAPTURE) && (bpl & 7) != 0) -+ return -EINVAL; -+ -+ return ngene_command_stream_control(dev, stream, control, mode, 0); -+} -+#endif - - /****************************************************************************/ - /* COMMAND API interface ****************************************************/ - /****************************************************************************/ -+#if 0 -+ -+static int command_do_ioctl(struct inode *inode, struct file *file, -+ unsigned int cmd, void *parg) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ int err = 0; -+ -+ switch (cmd) { -+ case IOCTL_MIC_NO_OP: -+ err = ngene_command_nop(dev); -+ break; -+ -+ case IOCTL_MIC_DOWNLOAD_FIRMWARE: -+ break; -+ -+ case IOCTL_MIC_I2C_READ: -+ { -+ MIC_I2C_READ *msg = parg; -+ -+ err = ngene_command_i2c_read(dev, msg->I2CAddress >> 1, -+ msg->OutData, msg->OutLength, -+ msg->OutData, msg->InLength, 1); -+ break; -+ } -+ -+ case IOCTL_MIC_I2C_WRITE: -+ { -+ MIC_I2C_WRITE *msg = parg; -+ -+ err = ngene_command_i2c_write(dev, msg->I2CAddress >> 1, -+ msg->Data, msg->Length); -+ break; -+ } -+ -+ case IOCTL_MIC_TEST_GETMEM: -+ { -+ MIC_MEM *m = parg; -+ -+ if (m->Length > 64 * 1024 || m->Start + m->Length > 64 * 1024) -+ return -EINVAL; -+ -+ /* WARNING, only use this on x86, -+ other archs may not swallow this */ -+ err = copy_to_user(m->Data, dev->iomem + m->Start, m->Length); -+ break; -+ } -+ -+ case IOCTL_MIC_TEST_SETMEM: -+ { -+ MIC_MEM *m = parg; -+ -+ if (m->Length > 64 * 1024 || m->Start + m->Length > 64 * 1024) -+ return -EINVAL; -+ -+ err = copy_from_user(dev->iomem + m->Start, m->Data, m->Length); -+ break; -+ } -+ -+ case IOCTL_MIC_SFR_READ: -+ { -+ MIC_IMEM *m = parg; -+ -+ err = ngene_command_imem_read(dev, m->Address, &m->Data, 1); -+ break; -+ } -+ -+ case IOCTL_MIC_SFR_WRITE: -+ { -+ MIC_IMEM *m = parg; -+ -+ err = ngene_command_imem_write(dev, m->Address, m->Data, 1); -+ break; -+ } -+ -+ case IOCTL_MIC_IRAM_READ: -+ { -+ MIC_IMEM *m = parg; -+ -+ err = ngene_command_imem_read(dev, m->Address, &m->Data, 0); -+ break; -+ } -+ -+ case IOCTL_MIC_IRAM_WRITE: -+ { -+ MIC_IMEM *m = parg; -+ -+ err = ngene_command_imem_write(dev, m->Address, m->Data, 0); -+ break; -+ } -+ -+ case IOCTL_MIC_STREAM_CONTROL: -+ { -+ MIC_STREAM_CONTROL *m = parg; -+ -+ err = ngene_stream_control(dev, m->Stream, m->Control, m->Mode, -+ m->nLines, m->nBytesPerLine, -+ m->nVBILines, m->nBytesPerVBILine); -+ break; -+ } -+ -+ default: -+ err = -EINVAL; -+ break; -+ } -+ return err; -+} -+ -+static int command_ioctl(struct inode *inode, struct file *file, -+ unsigned int cmd, unsigned long arg) -+{ -+ void *parg = (void *)arg, *pbuf = NULL; -+ char buf[64]; -+ int res = -EFAULT; -+ -+ if (_IOC_DIR(cmd) & _IOC_WRITE) { -+ parg = buf; -+ if (_IOC_SIZE(cmd) > sizeof(buf)) { -+ pbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL); -+ if (!pbuf) -+ return -ENOMEM; -+ parg = pbuf; -+ } -+ if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd))) -+ goto error; -+ } -+ res = command_do_ioctl(inode, file, cmd, parg); -+ if (res < 0) -+ goto error; -+ if (_IOC_DIR(cmd) & _IOC_READ) -+ if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd))) -+ res = -EFAULT; -+error: -+ kfree(pbuf); -+ return res; -+} -+ -+struct page *ngene_nopage(struct vm_area_struct *vma, -+ unsigned long address, int *type) -+{ -+ return 0; -+} -+ -+static int ngene_mmap(struct file *file, struct vm_area_struct *vma) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ -+ unsigned long size = vma->vm_end - vma->vm_start; -+ unsigned long off = vma->vm_pgoff << PAGE_SHIFT; -+ unsigned long padr = pci_resource_start(dev->pci_dev, 0) + off; -+ unsigned long psize = pci_resource_len(dev->pci_dev, 0) - off; -+ -+ if (size > psize) -+ return -EINVAL; -+ -+ if (io_remap_pfn_range(vma, vma->vm_start, padr >> PAGE_SHIFT, size, -+ vma->vm_page_prot)) -+ return -EAGAIN; -+ return 0; -+} -+ -+ -+static int write_uart(struct ngene *dev, u8 *data, int len) -+{ -+ struct ngene_command com; -+ -+ com.cmd.hdr.Opcode = CMD_WRITE_UART; -+ com.cmd.hdr.Length = len; -+ memcpy(com.cmd.WriteUart.Data, data, len); -+ com.cmd.WriteUart.Data[len] = 0; -+ com.cmd.WriteUart.Data[len + 1] = 0; -+ com.in_len = len; -+ com.out_len = 0; - --static ssize_t ts_write(struct file *file, const char __user *buf, -+ if (ngene_command(dev, &com) < 0) -+ return -EIO; -+ -+ return 0; -+} -+ -+static int send_cli(struct ngene *dev, char *cmd) -+{ -+ /* printk(KERN_INFO DEVICE_NAME ": %s", cmd); */ -+ return write_uart(dev, cmd, strlen(cmd)); -+} -+ -+static int send_cli_val(struct ngene *dev, char *cmd, u32 val) -+{ -+ char s[32]; -+ -+ snprintf(s, 32, "%s %d\n", cmd, val); -+ /* printk(KERN_INFO DEVICE_NAME ": %s", s); */ -+ return write_uart(dev, s, strlen(s)); -+} -+ -+static int ngene_command_write_uart_user(struct ngene *dev, -+ const u8 *data, int len) -+{ -+ struct ngene_command com; -+ -+ dev->tx_busy = 1; -+ com.cmd.hdr.Opcode = CMD_WRITE_UART; -+ com.cmd.hdr.Length = len; -+ -+ if (copy_from_user(com.cmd.WriteUart.Data, data, len)) -+ return -EFAULT; -+ com.in_len = len; -+ com.out_len = 0; -+ -+ if (ngene_command(dev, &com) < 0) -+ return -EIO; -+ -+ return 0; -+} -+ -+static ssize_t uart_write(struct file *file, const char *buf, -+ size_t count, loff_t *ppos) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ int len, ret = 0; -+ size_t left = count; -+ -+ while (left) { -+ len = left; -+ if (len > 250) -+ len = 250; -+ ret = wait_event_interruptible(dev->tx_wq, dev->tx_busy == 0); -+ if (ret < 0) -+ return ret; -+ ngene_command_write_uart_user(dev, buf, len); -+ left -= len; -+ buf += len; -+ } -+ return count; -+} -+ -+static ssize_t uart_read(struct file *file, char *buf, -+ size_t count, loff_t *ppos) -+{ -+ struct dvb_device *dvbdev = file->private_data; -+ struct ngene_channel *chan = dvbdev->priv; -+ struct ngene *dev = chan->dev; -+ int left; -+ int wp, rp, avail, len; -+ -+ if (!dev->uart_rbuf) -+ return -EINVAL; -+ if (count > 128) -+ count = 128; -+ left = count; -+ while (left) { -+ if (wait_event_interruptible(dev->rx_wq, -+ dev->uart_wp != dev->uart_rp) < 0) -+ return -EAGAIN; -+ wp = dev->uart_wp; -+ rp = dev->uart_rp; -+ avail = (wp - rp); -+ -+ if (avail < 0) -+ avail += UART_RBUF_LEN; -+ if (avail > left) -+ avail = left; -+ if (wp < rp) { -+ len = UART_RBUF_LEN - rp; -+ if (len > avail) -+ len = avail; -+ if (copy_to_user(buf, dev->uart_rbuf + rp, len)) -+ return -EFAULT; -+ if (len < avail) -+ if (copy_to_user(buf + len, dev->uart_rbuf, -+ avail - len)) -+ return -EFAULT; -+ } else { -+ if (copy_to_user(buf, dev->uart_rbuf + rp, avail)) -+ return -EFAULT; -+ } -+ dev->uart_rp = (rp + avail) % UART_RBUF_LEN; -+ left -= avail; -+ buf += avail; -+ } -+ return count; -+} -+ -+#endif -+ -+static ssize_t ts_write(struct file *file, const char *buf, - size_t count, loff_t *ppos) - { - struct dvb_device *dvbdev = file->private_data; -@@ -59,12 +368,12 @@ static ssize_t ts_write(struct file *file, const char __user *buf, - (&dev->tsout_rbuf) >= count) < 0) - return 0; - -- dvb_ringbuffer_write_user(&dev->tsout_rbuf, buf, count); -+ dvb_ringbuffer_write(&dev->tsout_rbuf, buf, count); - - return count; - } - --static ssize_t ts_read(struct file *file, char __user *buf, -+static ssize_t ts_read(struct file *file, char *buf, - size_t count, loff_t *ppos) - { - struct dvb_device *dvbdev = file->private_data; -@@ -97,6 +406,7 @@ static const struct file_operations ci_fops = { - }; - - struct dvb_device ngene_dvbdev_ci = { -+ .priv = 0, - .readers = -1, - .writers = -1, - .users = -1, -@@ -132,6 +442,11 @@ void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags) - struct ngene_channel *chan = priv; - struct ngene *dev = chan->dev; - -+#if 0 -+ printk(KERN_INFO DEVICE_NAME ": tsin %08x %02x %02x %02x %02x\n", -+ len, ((u8 *) buf)[512 * 188], ((u8 *) buf)[0], -+ ((u8 *) buf)[1], ((u8 *) buf)[2]); -+#endif - - if (flags & DF_SWAP32) - swap_buffer(buf, len); -@@ -190,12 +505,49 @@ void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags) - return buf; - } - -+#if 0 -+static void set_dto(struct ngene_channel *chan, u32 rate) -+{ -+ u64 val = rate * 0x89705f41ULL; /* times val for 2^26 Hz */ -+ -+ val = ((val >> 25) + 1) >> 1; -+ chan->AudioDTOValue = (u32) val; -+ /* chan->AudioDTOUpdated=1; */ -+ /* printk(KERN_INFO DEVICE_NAME ": Setting DTO to %08x\n", val); */ -+} -+#endif - - - int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed) - { - struct dvb_demux *dvbdmx = dvbdmxfeed->demux; - struct ngene_channel *chan = dvbdmx->priv; -+#if 0 -+ struct ngene *dev = chan->dev; -+ -+ if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) { -+ switch (dvbdmxfeed->pes_type) { -+ case DMX_TS_PES_VIDEO: -+ send_cli_val(dev, "vpid", dvbdmxfeed->pid); -+ send_cli(dev, "res 1080i50\n"); -+ /* send_cli(dev, "vdec mpeg2\n"); */ -+ break; -+ -+ case DMX_TS_PES_AUDIO: -+ send_cli_val(dev, "apid", dvbdmxfeed->pid); -+ send_cli(dev, "start\n"); -+ break; -+ -+ case DMX_TS_PES_PCR: -+ send_cli_val(dev, "pcrpid", dvbdmxfeed->pid); -+ break; -+ -+ default: -+ break; -+ } -+ -+ } -+#endif - - if (chan->users == 0) { - if (!chan->dev->cmd_timeout_workaround || !chan->running) -@@ -209,6 +561,27 @@ int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed) - { - struct dvb_demux *dvbdmx = dvbdmxfeed->demux; - struct ngene_channel *chan = dvbdmx->priv; -+#if 0 -+ struct ngene *dev = chan->dev; -+ -+ if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) { -+ switch (dvbdmxfeed->pes_type) { -+ case DMX_TS_PES_VIDEO: -+ send_cli(dev, "stop\n"); -+ break; -+ -+ case DMX_TS_PES_AUDIO: -+ break; -+ -+ case DMX_TS_PES_PCR: -+ break; -+ -+ default: -+ break; -+ } -+ -+ } -+#endif - - if (--chan->users) - return chan->users; -diff --git a/drivers/media/pci/ngene/ngene-eeprom.c b/drivers/media/pci/ngene/ngene-eeprom.c -new file mode 100644 -index 0000000..281d9f9 ---- /dev/null -+++ b/drivers/media/pci/ngene/ngene-eeprom.c -@@ -0,0 +1,284 @@ -+/* -+ * ngene-eeprom.c: nGene PCIe bridge driver - eeprom support -+ * -+ * Copyright (C) 2005-2007 Micronas -+ * -+ * Copyright (C) 2008-2009 Ralph Metzler -+ * Modifications for new nGene firmware, -+ * support for EEPROM-copying, -+ * support for new dual DVB-S2 card prototype -+ * -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 only, as published by the Free Software Foundation. -+ * -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ * 02110-1301, USA -+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+#if 0 -+static int copy_eeprom; -+module_param(copy_eeprom, int, 0444); -+MODULE_PARM_DESC(copy_eeprom, "Copy eeprom."); -+ -+#define MICNG_EE_START 0x0100 -+#define MICNG_EE_END 0x0FF0 -+ -+#define MICNG_EETAG_END0 0x0000 -+#define MICNG_EETAG_END1 0xFFFF -+ -+/* 0x0001 - 0x000F reserved for housekeeping */ -+/* 0xFFFF - 0xFFFE reserved for housekeeping */ -+ -+/* Micronas assigned tags -+ EEProm tags for hardware support */ -+ -+#define MICNG_EETAG_DRXD1_OSCDEVIATION 0x1000 /* 2 Bytes data */ -+#define MICNG_EETAG_DRXD2_OSCDEVIATION 0x1001 /* 2 Bytes data */ -+ -+#define MICNG_EETAG_MT2060_1_1STIF 0x1100 /* 2 Bytes data */ -+#define MICNG_EETAG_MT2060_2_1STIF 0x1101 /* 2 Bytes data */ -+ -+/* Tag range for OEMs */ -+ -+#define MICNG_EETAG_OEM_FIRST 0xC000 -+#define MICNG_EETAG_OEM_LAST 0xFFEF -+ -+static int i2c_write_eeprom(struct i2c_adapter *adapter, -+ u8 adr, u16 reg, u8 data) -+{ -+ u8 m[3] = {(reg >> 8), (reg & 0xff), data}; -+ struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, -+ .len = sizeof(m)}; -+ -+ if (i2c_transfer(adapter, &msg, 1) != 1) { -+ dprintk(KERN_ERR DEVICE_NAME ": Error writing EEPROM!\n"); -+ return -EIO; -+ } -+ return 0; -+} -+ -+static int i2c_read_eeprom(struct i2c_adapter *adapter, -+ u8 adr, u16 reg, u8 *data, int len) -+{ -+ u8 msg[2] = {(reg >> 8), (reg & 0xff)}; -+ struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, -+ .buf = msg, .len = 2 }, -+ {.addr = adr, .flags = I2C_M_RD, -+ .buf = data, .len = len} }; -+ -+ if (i2c_transfer(adapter, msgs, 2) != 2) { -+ dprintk(KERN_ERR DEVICE_NAME ": Error reading EEPROM\n"); -+ return -EIO; -+ } -+ return 0; -+} -+ -+static int ReadEEProm(struct i2c_adapter *adapter, -+ u16 Tag, u32 MaxLen, u8 *data, u32 *pLength) -+{ -+ int status = 0; -+ u16 Addr = MICNG_EE_START, Length, tag = 0; -+ u8 EETag[3]; -+ -+ while (Addr + sizeof(u16) + 1 < MICNG_EE_END) { -+ if (i2c_read_eeprom(adapter, 0x50, Addr, EETag, sizeof(EETag))) -+ return -1; -+ tag = (EETag[0] << 8) | EETag[1]; -+ if (tag == MICNG_EETAG_END0 || tag == MICNG_EETAG_END1) -+ return -1; -+ if (tag == Tag) -+ break; -+ Addr += sizeof(u16) + 1 + EETag[2]; -+ } -+ if (Addr + sizeof(u16) + 1 + EETag[2] > MICNG_EE_END) { -+ printk(KERN_ERR DEVICE_NAME -+ ": Reached EOEE @ Tag = %04x Length = %3d\n", -+ tag, EETag[2]); -+ return -1; -+ } -+ Length = EETag[2]; -+ if (Length > MaxLen) -+ Length = (u16) MaxLen; -+ if (Length > 0) { -+ Addr += sizeof(u16) + 1; -+ status = i2c_read_eeprom(adapter, 0x50, Addr, data, Length); -+ if (!status) { -+ *pLength = EETag[2]; -+ if (Length < EETag[2]) -+ ; /*status=STATUS_BUFFER_OVERFLOW; */ -+ } -+ } -+ return status; -+} -+ -+static int WriteEEProm(struct i2c_adapter *adapter, -+ u16 Tag, u32 Length, u8 *data) -+{ -+ int status = 0; -+ u16 Addr = MICNG_EE_START; -+ u8 EETag[3]; -+ u16 tag = 0; -+ int retry, i; -+ -+ while (Addr + sizeof(u16) + 1 < MICNG_EE_END) { -+ if (i2c_read_eeprom(adapter, 0x50, Addr, EETag, sizeof(EETag))) -+ return -1; -+ tag = (EETag[0] << 8) | EETag[1]; -+ if (tag == MICNG_EETAG_END0 || tag == MICNG_EETAG_END1) -+ return -1; -+ if (tag == Tag) -+ break; -+ Addr += sizeof(u16) + 1 + EETag[2]; -+ } -+ if (Addr + sizeof(u16) + 1 + EETag[2] > MICNG_EE_END) { -+ printk(KERN_ERR DEVICE_NAME -+ ": Reached EOEE @ Tag = %04x Length = %3d\n", -+ tag, EETag[2]); -+ return -1; -+ } -+ -+ if (Length > EETag[2]) -+ return -EINVAL; -+ /* Note: We write the data one byte at a time to avoid -+ issues with page sizes. (which are different for -+ each manufacture and eeprom size) + int c8sectpfe_frontend_attach(struct dvb_frontend **fe, +diff --git a/drivers/media/tuners/tda18212.c b/drivers/media/tuners/tda18212.c +index 7b80683..2488537 100644 +--- a/drivers/media/tuners/tda18212.c ++++ b/drivers/media/tuners/tda18212.c +@@ -220,6 +220,11 @@ static int tda18212_probe(struct i2c_client *client, + fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */ + + ret = regmap_read(dev->regmap, 0x00, &chip_id); ++ ++ /* retry probe if desired */ ++ if (ret && (cfg->init_flags & TDA18212_INIT_RETRY)) ++ ret = regmap_read(dev->regmap, 0x00, &chip_id); ++ + dev_dbg(&dev->client->dev, "chip_id=%02x\n", chip_id); + + if (fe->ops.i2c_gate_ctrl) +diff --git a/drivers/media/tuners/tda18212.h b/drivers/media/tuners/tda18212.h +index e58c909..457ae72 100644 +--- a/drivers/media/tuners/tda18212.h ++++ b/drivers/media/tuners/tda18212.h +@@ -24,6 +24,8 @@ + #include + #include "dvb_frontend.h" + ++#define TDA18212_INIT_RETRY (1 << 0) ++ + struct tda18212_config { + u16 if_dvbt_6; + u16 if_dvbt_7; +@@ -37,6 +39,11 @@ struct tda18212_config { + u16 if_atsc_qam; + + /* ++ * flags for tuner init control + */ -+ Addr += sizeof(u16) + 1; -+ for (i = 0; i < Length; i++, Addr++) { -+ status = i2c_write_eeprom(adapter, 0x50, Addr, data[i]); ++ u32 init_flags; + -+ if (status) -+ break; -+ -+ /* Poll for finishing write cycle */ -+ retry = 10; -+ while (retry) { -+ u8 Tmp; -+ -+ msleep(50); -+ status = i2c_read_eeprom(adapter, 0x50, Addr, &Tmp, 1); -+ if (status) -+ break; -+ if (Tmp != data[i]) -+ printk(KERN_ERR DEVICE_NAME -+ "eeprom write error\n"); -+ retry -= 1; -+ } -+ if (status) { -+ printk(KERN_ERR DEVICE_NAME -+ ": Timeout polling eeprom\n"); -+ break; -+ } -+ } -+ return status; -+} -+ -+static void i2c_init_eeprom(struct i2c_adapter *adapter) -+{ -+ u8 tags[] = {0x10, 0x00, 0x02, 0x00, 0x00, -+ 0x10, 0x01, 0x02, 0x00, 0x00, -+ 0x00, 0x00, 0x00}; -+ -+ int i; -+ -+ for (i = 0; i < sizeof(tags); i++) -+ i2c_write_eeprom(adapter, 0x50, 0x0100 + i, tags[i]); -+} -+ -+int eeprom_read_ushort(struct i2c_adapter *adapter, u16 tag, u16 *data) -+{ -+ int stat; -+ u8 buf[2]; -+ u32 len = 0; -+ -+ stat = ReadEEProm(adapter, tag, 2, buf, &len); -+ if (stat) -+ return stat; -+ if (len != 2) -+ return -EINVAL; -+ -+ *data = (buf[0] << 8) | buf[1]; -+ return 0; -+} -+ -+static int eeprom_write_ushort(struct i2c_adapter *adapter, u16 tag, u16 data) -+{ -+ int stat; -+ u8 buf[2]; -+ -+ buf[0] = data >> 8; -+ buf[1] = data & 0xff; -+ stat = WriteEEProm(adapter, tag, 2, buf); -+ if (stat) -+ return stat; -+ return 0; -+} -+ -+int i2c_dump_eeprom(struct i2c_adapter *adapter, u8 adr) -+{ -+ u8 buf[64]; -+ int i; -+ -+ if (i2c_read_eeprom(adapter, adr, 0x0000, buf, sizeof(buf))) { -+ printk(KERN_ERR DEVICE_NAME ": No EEPROM?\n"); -+ return -1; -+ } -+ for (i = 0; i < sizeof(buf); i++) { -+ if (!(i & 15)) -+ printk(KERN_DEBUG "\n"); -+ printk(KERN_DEBUG "%02x ", buf[i]); -+ } -+ printk("\n"); -+ -+ return 0; -+} -+ -+int i2c_copy_eeprom(struct i2c_adapter *adapter, u8 adr, u8 adr2) -+{ -+ u8 buf[64]; -+ int i; -+ -+ if (i2c_read_eeprom(adapter, adr, 0x0000, buf, sizeof(buf))) { -+ printk(KERN_ERR DEVICE_NAME ": No EEPROM?\n"); -+ return -1; -+ } -+ buf[36] = 0xc3; -+ buf[39] = 0xab; -+ for (i = 0; i < sizeof(buf); i++) { -+ i2c_write_eeprom(adapter, adr2, i, buf[i]); -+ msleep(10); -+ } -+ return 0; -+} -+ -+int i2c_check_eeprom(struct i2c_adapter *adapter) -+{ -+ u8 buf[13]; -+ -+ i2c_dump_eeprom(adapter); -+ -+ if (i2c_read_eeprom(adapter, 0x50, 0x0100, buf, sizeof(buf))) { -+ printk(KERN_ERR DEVICE_NAME ": No EEPROM?\n"); -+ return -1; -+ } -+ if (buf[0] != 0x10 || buf[1] != 0x00) { -+ printk(KERN_INFO DEVICE_NAME -+ ": Initializing EEPROM TAG area\n"); -+ i2c_init_eeprom(adapter); -+ } -+ return 0; -+} -+ -+#endif -diff --git a/drivers/media/pci/ngene/ngene-i2c.c b/drivers/media/pci/ngene/ngene-i2c.c -index d28554f..601bea4 100644 ---- a/drivers/media/pci/ngene/ngene-i2c.c -+++ b/drivers/media/pci/ngene/ngene-i2c.c -@@ -77,6 +77,11 @@ static int ngene_command_i2c_write(struct ngene *dev, u8 adr, - { - struct ngene_command com; - -+#if 0 -+ /* Probing by writing 0 bytes does not work */ -+ if (!outlen) -+ outlen++; -+#endif - - com.cmd.hdr.Opcode = CMD_I2C_WRITE; - com.cmd.hdr.Length = outlen + 1; -@@ -148,6 +153,39 @@ done: - return num; - } - -+#if 0 -+static int ngene_i2c_algo_control(struct i2c_adapter *adap, -+ unsigned int cmd, unsigned long arg) -+{ -+ struct ngene_channel *chan = -+ (struct ngene_channel *)i2c_get_adapdata(adap); -+ -+ switch (cmd) { -+ case IOCTL_MIC_TUN_RDY: -+ chan->tun_rdy = 1; -+ if (chan->dec_rdy == 1) -+ chan->tun_dec_rdy = 1; -+ break; -+ -+ case IOCTL_MIC_DEC_RDY: -+ chan->dec_rdy = 1; -+ if (chan->tun_rdy == 1) -+ chan->tun_dec_rdy = 1; -+ break; -+ -+ case IOCTL_MIC_TUN_DETECT: -+ { -+ int *palorbtsc = (int *)arg; -+ *palorbtsc = chan->dev->card_info->ntsc; -+ break; -+ } -+ -+ default: -+ break; -+ } -+ return 0; -+} -+#endif - - static u32 ngene_i2c_functionality(struct i2c_adapter *adap) - { -@@ -174,3 +212,78 @@ int ngene_i2c_init(struct ngene *dev, int dev_nr) - return i2c_add_adapter(adap); - } - -+#if 0 -+int i2c_write(struct i2c_adapter *adapter, u8 adr, u8 data) -+{ -+ u8 m[1] = {data}; -+ struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 1}; -+ -+ if (i2c_transfer(adapter, &msg, 1) != 1) { -+ printk(KERN_ERR DEVICE_NAME -+ ": Failed to write to I2C adr %02x!\n", adr); -+ return -1; -+ } -+ return 0; -+} -+ -+static int i2c_write_register(struct i2c_adapter *adapter, -+ u8 adr, u8 reg, u8 data) -+{ -+ u8 m[2] = {reg, data}; -+ struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2}; -+ -+ if (i2c_transfer(adapter, &msg, 1) != 1) { -+ printk(KERN_ERR DEVICE_NAME -+ ": Failed to write to I2C register %02x@%02x!\n", -+ reg, adr); -+ return -1; -+ } -+ return 0; -+} -+ -+static int i2c_write_read(struct i2c_adapter *adapter, -+ u8 adr, u8 *w, u8 wlen, u8 *r, u8 rlen) -+{ -+ struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, -+ .buf = w, .len = wlen}, -+ {.addr = adr, .flags = I2C_M_RD, -+ .buf = r, .len = rlen} }; -+ -+ if (i2c_transfer(adapter, msgs, 2) != 2) { -+ printk(KERN_ERR DEVICE_NAME ": error in i2c_write_read\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+static int test_dec_i2c(struct i2c_adapter *adapter, int reg) -+{ -+ u8 data[256] = { reg, 0x00, 0x93, 0x78, 0x43, 0x45 }; -+ u8 data2[256]; -+ int i; -+ -+ memset(data2, 0, 256); -+ i2c_write_read(adapter, 0x66, data, 2, data2, 4); -+ for (i = 0; i < 4; i++) -+ printk(KERN_DEBUG "%02x ", data2[i]); -+ printk(KERN_DEBUG "\n"); -+ -+ return 0; -+} -+ -+static int i2c_write_msp_register(struct i2c_adapter *adapter, -+ u8 adr, u8 reg, u16 data) -+{ -+ u8 m[3] = {reg, (data >> 8) & 0xff, data & 0xff}; -+ struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 3 }; -+ -+ if (i2c_transfer(adapter, &msg, 1) != 1) { -+ printk(KERN_ERR DEVICE_NAME -+ ": Failed to write to I2C register %02x@%02x!\n", -+ reg, adr); -+ return -1; -+ } -+ return 0; -+} -+ -+#endif -diff --git a/drivers/media/pci/ngene/ngene.h b/drivers/media/pci/ngene/ngene.h -index 51e2fbd..e3ae00c 100644 ---- a/drivers/media/pci/ngene/ngene.h -+++ b/drivers/media/pci/ngene/ngene.h -@@ -653,6 +653,11 @@ struct ngene_channel { - struct dmx_frontend mem_frontend; - int users; - struct video_device *v4l_dev; -+#if 0 -+ struct dvb_device *command_dev; -+ struct dvb_device *audio_dev; -+ struct dvb_device *video_dev; -+#endif - struct dvb_device *ci_dev; - struct tasklet_struct demux_tasklet; - -@@ -691,6 +696,9 @@ struct ngene_channel { - struct mychip *mychip; - struct snd_card *soundcard; - u8 *evenbuffer; -+#if 0 -+ u8 *soundbuffer; -+#endif - u8 dma_on; - int soundstreamon; - int audiomute; -@@ -737,7 +745,7 @@ typedef void (tx_cb_t)(struct ngene *, u32); - struct ngene { - int nr; - struct pci_dev *pci_dev; -- unsigned char __iomem *iomem; -+ unsigned char *iomem; - - /*struct i2c_adapter i2c_adapter;*/ - -@@ -849,6 +857,10 @@ struct ngene_info { - u8 lnb[4]; - int i2c_access; - u8 ntsc; -+#if 0 -+ u8 exp; -+ u8 exp_init; -+#endif - u8 tsf[4]; - u8 i2s[4]; - -@@ -885,6 +897,25 @@ struct ngene_buffer { ++ /* + * pointer to DVB frontend + */ + struct dvb_frontend *fe; +diff --git a/drivers/media/usb/dvb-usb-v2/anysee.c b/drivers/media/usb/dvb-usb-v2/anysee.c +index ae917c0..02d22eb 100644 +--- a/drivers/media/usb/dvb-usb-v2/anysee.c ++++ b/drivers/media/usb/dvb-usb-v2/anysee.c +@@ -336,6 +336,7 @@ static struct tda18212_config anysee_tda18212_config = { + .if_dvbt_7 = 4150, + .if_dvbt_8 = 4150, + .if_dvbc = 5000, ++ .init_flags = 0, }; - #endif -+#if 0 -+int ngene_command_stream_control(struct ngene *dev, -+ u8 stream, u8 control, u8 mode, u8 flags); -+int ngene_command_nop(struct ngene *dev); -+int ngene_command_i2c_read(struct ngene *dev, u8 adr, -+ u8 *out, u8 outlen, u8 *in, u8 inlen, int flag); -+int ngene_command_i2c_write(struct ngene *dev, u8 adr, u8 *out, u8 outlen); -+int ngene_command_imem_read(struct ngene *dev, u8 adr, u8 *data, int type); -+int ngene_command_imem_write(struct ngene *dev, u8 adr, u8 data, int type); -+int ngene_stream_control(struct ngene *dev, u8 stream, u8 control, u8 mode, -+ u16 lines, u16 bpl, u16 vblines, u16 vbibpl); + static struct tda18212_config anysee_tda18212_config2 = { +@@ -346,6 +347,7 @@ static struct tda18212_config anysee_tda18212_config2 = { + .if_dvbt2_7 = 4000, + .if_dvbt2_8 = 4000, + .if_dvbc = 5000, ++ .init_flags = 0, + }; + + static struct cx24116_config anysee_cx24116_config = { +diff --git a/drivers/media/usb/em28xx/em28xx-dvb.c b/drivers/media/usb/em28xx/em28xx-dvb.c +index 1a5c012..335d16a 100644 +--- a/drivers/media/usb/em28xx/em28xx-dvb.c ++++ b/drivers/media/usb/em28xx/em28xx-dvb.c +@@ -376,6 +376,7 @@ static struct tda18271_config kworld_ub435q_v2_config = { + static struct tda18212_config kworld_ub435q_v3_config = { + .if_atsc_vsb = 3600, + .if_atsc_qam = 3600, ++ .init_flags = 0, + }; + + static struct zl10353_config em28xx_zl10353_xc3028_no_i2c_gate = { +diff --git a/drivers/staging/media/cxd2099/cxd2099.c b/drivers/staging/media/cxd2099/cxd2099.c +index 692ba3e..a965edc 100644 +--- a/drivers/staging/media/cxd2099/cxd2099.c ++++ b/drivers/staging/media/cxd2099/cxd2099.c +@@ -1,7 +1,7 @@ + /* + * cxd2099.c: Driver for the CXD2099AR Common Interface Controller + * +- * Copyright (C) 2010-2011 Digital Devices GmbH ++ * Copyright (C) 2010-2013 Digital Devices GmbH + * + * + * This program is free software; you can redistribute it and/or +@@ -22,6 +22,7 @@ + * Or, point your browser to http://www.gnu.org/copyleft/gpl.html + */ + ++#include + #include + #include + #include +@@ -33,7 +34,9 @@ + + #include "cxd2099.h" + +-#define MAX_BUFFER_SIZE 248 ++/* #define BUFFER_MODE 1 */ + -+int ngene_v4l2_init(struct ngene_channel *chan); -+void ngene_v4l2_remove(struct ngene_channel *chan); -+int ngene_snd_exit(struct ngene_channel *chan); -+int ngene_snd_init(struct ngene_channel *chan); ++static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount); + + struct cxd { + struct dvb_ca_en50221 en; +@@ -48,6 +51,7 @@ struct cxd { + int mode; + int ready; + int dr; ++ int write_busy; + int slot_stat; + + u8 amem[1024]; +@@ -55,6 +59,9 @@ struct cxd { + + int cammode; + struct mutex lock; + -+struct i2c_client *avf4910a_attach(struct i2c_adapter *adap, int addr); -+#endif ++ u8 rbuf[1028]; ++ u8 wbuf[1028]; + }; - /* Provided by ngene-core.c */ - int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id); -@@ -914,6 +945,15 @@ int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, - struct dmx_frontend *mem_frontend, - struct dvb_adapter *dvb_adapter); + static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr, +@@ -73,7 +80,7 @@ static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr, + } -+/* Provided by ngene-eeprom.c */ -+#if 0 -+int i2c_copy_eeprom(struct i2c_adapter *adapter, u8 adr, u8 adr2); -+int i2c_dump_eeprom(struct i2c_adapter *adapter, u8 adr); -+int i2c_check_eeprom(struct i2c_adapter *adapter); -+int eeprom_write_ushort(struct i2c_adapter *adapter, u16 tag, u16 data); -+int eeprom_read_ushort(struct i2c_adapter *adapter, u16 tag, u16 *data); -+#endif + static int i2c_write(struct i2c_adapter *adapter, u8 adr, +- u8 *data, u8 len) ++ u8 *data, u16 len) + { + struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len}; + +@@ -100,7 +107,7 @@ static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr, + } + + static int i2c_read(struct i2c_adapter *adapter, u8 adr, +- u8 reg, u8 *data, u8 n) ++ u8 reg, u8 *data, u16 n) + { + struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, + .buf = ®, .len = 1}, +@@ -114,14 +121,27 @@ static int i2c_read(struct i2c_adapter *adapter, u8 adr, + return 0; + } + +-static int read_block(struct cxd *ci, u8 adr, u8 *data, u8 n) ++static int read_block(struct cxd *ci, u8 adr, u8 *data, u16 n) + { +- int status; ++ int status = 0; + +- status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr); ++ if (ci->lastaddress != adr) ++ status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr); + if (!status) { + ci->lastaddress = adr; +- status = i2c_read(ci->i2c, ci->cfg.adr, 1, data, n); + - #endif ++ while (n) { ++ int len = n; ++ ++ if (ci->cfg.max_i2c && ++ len > ci->cfg.max_i2c) ++ len = ci->cfg.max_i2c; ++ status = i2c_read(ci->i2c, ci->cfg.adr, 1, data, len); ++ if (status) ++ return status; ++ data += len; ++ n -= len; ++ } + } + return status; + } +@@ -181,46 +201,18 @@ static int write_io(struct cxd *ci, u16 address, u8 val) + return status; + } - /* LocalWords: Endif +-#if 0 +-static int read_io_data(struct cxd *ci, u8 *data, u8 n) +-{ +- int status; +- u8 addr[3] = { 2, 0, 0 }; +- +- status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); +- if (!status) +- status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n); +- return 0; +-} +- +-static int write_io_data(struct cxd *ci, u8 *data, u8 n) +-{ +- int status; +- u8 addr[3] = {2, 0, 0}; +- +- status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3); +- if (!status) { +- u8 buf[256] = {3}; +- +- memcpy(buf+1, data, n); +- status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1); +- } +- return 0; +-} +-#endif +- + static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask) + { +- int status; ++ int status = 0; + +- status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, reg); ++ if (ci->lastaddress != reg) ++ status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, reg); + if (!status && reg >= 6 && reg <= 8 && mask != 0xff) + status = i2c_read_reg(ci->i2c, ci->cfg.adr, 1, &ci->regs[reg]); ++ ci->lastaddress = reg; + ci->regs[reg] = (ci->regs[reg] & (~mask)) | val; +- if (!status) { +- ci->lastaddress = reg; ++ if (!status) + status = i2c_write_reg(ci->i2c, ci->cfg.adr, 1, ci->regs[reg]); +- } + if (reg == 0x20) + ci->regs[reg] &= 0x7f; + return status; +@@ -232,16 +224,32 @@ static int write_reg(struct cxd *ci, u8 reg, u8 val) + } + + #ifdef BUFFER_MODE +-static int write_block(struct cxd *ci, u8 adr, u8 *data, int n) ++static int write_block(struct cxd *ci, u8 adr, u8 *data, u16 n) + { +- int status; +- u8 buf[256] = {1}; +- +- status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr); +- if (!status) { +- ci->lastaddress = adr; +- memcpy(buf + 1, data, n); +- status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1); ++ int status = 0; ++ u8 *buf = ci->wbuf; ++ ++ if (ci->lastaddress != adr) ++ status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr); ++ if (status) ++ return status; ++ dev_info(&ci->i2c->dev, "write_block %d\n", n); ++ ++ ci->lastaddress = adr; ++ buf[0] = 1; ++ while (n) { ++ int len = n; ++ ++ if (ci->cfg.max_i2c && ++ len + 1 > ci->cfg.max_i2c) ++ len = ci->cfg.max_i2c - 1; ++ dev_info(&ci->i2c->dev, "write %d\n", len); ++ memcpy(buf + 1, data, len); ++ status = i2c_write(ci->i2c, ci->cfg.adr, buf, len + 1); ++ if (status) ++ return status; ++ n -= len; ++ data += len; + } + return status; + } +@@ -267,6 +275,8 @@ static void set_mode(struct cxd *ci, int mode) + + static void cam_mode(struct cxd *ci, int mode) + { ++ u8 dummy; ++ + if (mode == ci->cammode) + return; + +@@ -275,16 +285,15 @@ static void cam_mode(struct cxd *ci, int mode) + write_regm(ci, 0x20, 0x80, 0x80); + break; + case 0x01: +-#ifdef BUFFER_MODE + if (!ci->en.read_data) + return; ++ ci->write_busy = 0; + dev_info(&ci->i2c->dev, "enable cam buffer mode\n"); +- /* write_reg(ci, 0x0d, 0x00); */ +- /* write_reg(ci, 0x0e, 0x01); */ ++ write_reg(ci, 0x0d, 0x00); ++ write_reg(ci, 0x0e, 0x01); + write_regm(ci, 0x08, 0x40, 0x40); +- /* read_reg(ci, 0x12, &dummy); */ ++ read_reg(ci, 0x12, &dummy); + write_regm(ci, 0x08, 0x80, 0x80); +-#endif + break; + default: + break; +@@ -292,8 +301,6 @@ static void cam_mode(struct cxd *ci, int mode) + ci->cammode = mode; + } + +- +- + static int init(struct cxd *ci) + { + int status; +@@ -329,12 +336,6 @@ static int init(struct cxd *ci) + if (status < 0) + break; + +-#if 0 +- /* Input Mode C, BYPass Serial, TIVAL = low, MSB */ +- status = write_reg(ci, 0x09, 0x4D); +- if (status < 0) +- break; +-#endif + /* TOSTRT = 8, Mode B (gated clock), falling Edge, + * Serial, POL=HIGH, MSB */ + status = write_reg(ci, 0x0A, 0xA7); +@@ -361,7 +362,10 @@ static int init(struct cxd *ci) + if (status < 0) + break; + +- if (ci->cfg.clock_mode) { ++ if (ci->cfg.clock_mode == 2) { ++ /* bitrate*2^13/ 72000 */ ++ u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000; ++ + if (ci->cfg.polarity) { + status = write_reg(ci, 0x09, 0x6f); + if (status < 0) +@@ -371,6 +375,25 @@ static int init(struct cxd *ci) + if (status < 0) + break; + } ++ status = write_reg(ci, 0x20, 0x08); ++ if (status < 0) ++ break; ++ status = write_reg(ci, 0x21, (reg >> 8) & 0xff); ++ if (status < 0) ++ break; ++ status = write_reg(ci, 0x22, reg & 0xff); ++ if (status < 0) ++ break; ++ } else if (ci->cfg.clock_mode == 1) { ++ if (ci->cfg.polarity) { ++ status = write_reg(ci, 0x09, 0x6f); /* D */ ++ if (status < 0) ++ break; ++ } else { ++ status = write_reg(ci, 0x09, 0x6d); ++ if (status < 0) ++ break; ++ } + status = write_reg(ci, 0x20, 0x68); + if (status < 0) + break; +@@ -382,7 +405,7 @@ static int init(struct cxd *ci) + break; + } else { + if (ci->cfg.polarity) { +- status = write_reg(ci, 0x09, 0x4f); ++ status = write_reg(ci, 0x09, 0x4f); /* C */ + if (status < 0) + break; + } else { +@@ -390,7 +413,6 @@ static int init(struct cxd *ci) + if (status < 0) + break; + } +- + status = write_reg(ci, 0x20, 0x28); + if (status < 0) + break; +@@ -431,23 +453,6 @@ static int read_attribute_mem(struct dvb_ca_en50221 *ca, + int slot, int address) + { + struct cxd *ci = ca->data; +-#if 0 +- if (ci->amem_read) { +- if (address <= 0 || address > 1024) +- return -EIO; +- return ci->amem[address]; +- } +- +- mutex_lock(&ci->lock); +- write_regm(ci, 0x06, 0x00, 0x05); +- read_pccard(ci, 0, &ci->amem[0], 128); +- read_pccard(ci, 128, &ci->amem[0], 128); +- read_pccard(ci, 256, &ci->amem[0], 128); +- read_pccard(ci, 384, &ci->amem[0], 128); +- write_regm(ci, 0x06, 0x05, 0x05); +- mutex_unlock(&ci->lock); +- return ci->amem[address]; +-#else + u8 val; + + mutex_lock(&ci->lock); +@@ -456,7 +461,6 @@ static int read_attribute_mem(struct dvb_ca_en50221 *ca, + mutex_unlock(&ci->lock); + /* printk(KERN_INFO "%02x:%02x\n", address,val); */ + return val; +-#endif + } + + static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, +@@ -500,16 +504,10 @@ static int slot_reset(struct dvb_ca_en50221 *ca, int slot) + { + struct cxd *ci = ca->data; + ++ if (ci->cammode) ++ read_data(ca, slot, ci->rbuf, 0); ++ + mutex_lock(&ci->lock); +-#if 0 +- write_reg(ci, 0x00, 0x21); +- write_reg(ci, 0x06, 0x1F); +- write_reg(ci, 0x00, 0x31); +-#else +-#if 0 +- write_reg(ci, 0x06, 0x1F); +- write_reg(ci, 0x06, 0x2F); +-#else + cam_mode(ci, 0); + write_reg(ci, 0x00, 0x21); + write_reg(ci, 0x06, 0x1F); +@@ -517,25 +515,14 @@ static int slot_reset(struct dvb_ca_en50221 *ca, int slot) + write_regm(ci, 0x20, 0x80, 0x80); + write_reg(ci, 0x03, 0x02); + ci->ready = 0; +-#endif +-#endif + ci->mode = -1; + { + int i; +-#if 0 +- u8 val; +-#endif ++ + for (i = 0; i < 100; i++) { + usleep_range(10000, 11000); +-#if 0 +- read_reg(ci, 0x06, &val); +- dev_info(&ci->i2c->dev, "%d:%02x\n", i, val); +- if (!(val&0x10)) +- break; +-#else + if (ci->ready) + break; +-#endif + } + } + mutex_unlock(&ci->lock); +@@ -548,11 +535,19 @@ static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot) + struct cxd *ci = ca->data; + + dev_info(&ci->i2c->dev, "slot_shutdown\n"); ++ if (ci->cammode) ++ read_data(ca, slot, ci->rbuf, 0); + mutex_lock(&ci->lock); ++ write_reg(ci, 0x00, 0x21); ++ write_reg(ci, 0x06, 0x1F); ++ msleep(300); ++ + write_regm(ci, 0x09, 0x08, 0x08); + write_regm(ci, 0x20, 0x80, 0x80); /* Reset CAM Mode */ + write_regm(ci, 0x06, 0x07, 0x07); /* Clear IO Mode */ ++ + ci->mode = -1; ++ ci->write_busy = 0; + mutex_unlock(&ci->lock); + return 0; + } +@@ -564,9 +559,7 @@ static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot) + mutex_lock(&ci->lock); + write_regm(ci, 0x09, 0x00, 0x08); + set_mode(ci, 0); +-#ifdef BUFFER_MODE + cam_mode(ci, 1); +-#endif + mutex_unlock(&ci->lock); + return 0; + } +@@ -585,8 +578,10 @@ static int campoll(struct cxd *ci) + ci->dr = 1; + dev_info(&ci->i2c->dev, "DR\n"); + } +- if (istat&0x20) ++ if (istat&0x20) { ++ ci->write_busy = 0; + dev_info(&ci->i2c->dev, "WC\n"); ++ } + + if (istat&2) { + u8 slotstat; +@@ -594,7 +589,7 @@ static int campoll(struct cxd *ci) + read_reg(ci, 0x01, &slotstat); + if (!(2&slotstat)) { + if (!ci->slot_stat) { +- ci->slot_stat = DVB_CA_EN50221_POLL_CAM_PRESENT; ++ ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_PRESENT; + write_regm(ci, 0x03, 0x08, 0x08); + } + +@@ -606,8 +601,8 @@ static int campoll(struct cxd *ci) + ci->ready = 0; + } + } +- if (istat&8 && +- ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) { ++ if ((istat&8) && ++ (ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT)) { + ci->ready = 1; + ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY; + } +@@ -629,7 +624,6 @@ static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open) + return ci->slot_stat; + } + +-#ifdef BUFFER_MODE + static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount) + { + struct cxd *ci = ca->data; +@@ -647,23 +641,33 @@ static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount) + mutex_lock(&ci->lock); + read_reg(ci, 0x0f, &msb); + read_reg(ci, 0x10, &lsb); +- len = (msb<<8)|lsb; ++ len = ((u16) msb << 8) | lsb; ++ if (len > ecount || len < 2) { ++ /* read it anyway or cxd may hang */ ++ read_block(ci, 0x12, ci->rbuf, len); ++ mutex_unlock(&ci->lock); ++ return -EIO; ++ } + read_block(ci, 0x12, ebuf, len); + ci->dr = 0; + mutex_unlock(&ci->lock); +- + return len; + } + ++#ifdef BUFFER_MODE ++ + static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount) + { + struct cxd *ci = ca->data; + ++ if (ci->write_busy) ++ return -EAGAIN; + mutex_lock(&ci->lock); +- printk(kern_INFO "write_data %d\n", ecount); ++ dev_info(&ci->i2c->dev, "write_data %d\n", ecount); + write_reg(ci, 0x0d, ecount>>8); + write_reg(ci, 0x0e, ecount&0xff); + write_block(ci, 0x11, ebuf, ecount); ++ ci->write_busy = 1; + mutex_unlock(&ci->lock); + return ecount; + } +diff --git a/drivers/staging/media/cxd2099/cxd2099.h b/drivers/staging/media/cxd2099/cxd2099.h +index 0eb607c..f4b29b1 100644 +--- a/drivers/staging/media/cxd2099/cxd2099.h ++++ b/drivers/staging/media/cxd2099/cxd2099.h +@@ -30,8 +30,10 @@ + struct cxd2099_cfg { + u32 bitrate; + u8 adr; +- u8 polarity:1; +- u8 clock_mode:1; ++ u8 polarity; ++ u8 clock_mode; ++ ++ u32 max_i2c; + }; + + #if defined(CONFIG_DVB_CXD2099) || \ +diff --git a/include/uapi/linux/dvb/frontend.h b/include/uapi/linux/dvb/frontend.h +index 00a20cd..bf9d16b 100644 +--- a/include/uapi/linux/dvb/frontend.h ++++ b/include/uapi/linux/dvb/frontend.h +@@ -156,6 +156,8 @@ enum fe_code_rate { + FEC_3_5, + FEC_9_10, + FEC_2_5, ++ FEC_1_4, ++ FEC_1_3, + }; + + enum fe_modulation { +@@ -307,7 +309,9 @@ enum fe_interleaving { + #define DTV_STAT_ERROR_BLOCK_COUNT 68 + #define DTV_STAT_TOTAL_BLOCK_COUNT 69 + +-#define DTV_MAX_COMMAND DTV_STAT_TOTAL_BLOCK_COUNT ++#define DTV_INPUT 70 ++ ++#define DTV_MAX_COMMAND DTV_INPUT + + enum fe_pilot { + PILOT_ON, +@@ -342,6 +346,7 @@ enum fe_delivery_system { + SYS_DVBT2, + SYS_TURBO, + SYS_DVBC_ANNEX_C, ++ SYS_DVBC2, + }; + + /* backward compatibility */ diff --git a/include/uapi/linux/dvb/mod.h b/include/uapi/linux/dvb/mod.h new file mode 100644 -index 0000000..c733a39 +index 0000000..f595a2c --- /dev/null +++ b/include/uapi/linux/dvb/mod.h @@ -0,0 +1,22 @@ @@ -34044,13 +28442,13 @@ index 0000000..c733a39 + +struct dvb_mod_params { + __u32 base_frequency; -+ __u32 attenuator; ++ __u32 attenuator; +}; + +struct dvb_mod_channel_params { + enum fe_modulation modulation; + __u64 input_bitrate; /* 2^-32 Hz */ -+ int pcr_correction; ++ int pcr_correction; +}; + + @@ -34060,10 +28458,10 @@ index 0000000..c733a39 +#endif /*_UAPI_DVBMOD_H_*/ diff --git a/include/uapi/linux/dvb/ns.h b/include/uapi/linux/dvb/ns.h new file mode 100644 -index 0000000..691c65d +index 0000000..4cfd9f0 --- /dev/null +++ b/include/uapi/linux/dvb/ns.h -@@ -0,0 +1,68 @@ +@@ -0,0 +1,69 @@ +#ifndef _UAPI_DVBNS_H_ +#define _UAPI_DVBNS_H_ + @@ -34085,10 +28483,11 @@ index 0000000..691c65d + __u8 ttl; +}; + -+#define DVB_NS_IPV6 1 -+#define DVB_NS_RTP 2 -+#define DVB_NS_RTCP 4 -+#define DVB_NS_RTP_TO 8 ++#define DVB_NS_IPV6 0x01 ++#define DVB_NS_RTP 0x02 ++#define DVB_NS_RTCP 0x04 ++#define DVB_NS_RTP_TO 0x08 ++#define DVB_NS_VLAN 0x10 + +struct dvb_ns_rtcp { + __u8 *msg; @@ -34132,6 +28531,3 @@ index 0000000..691c65d +#define NS_SET_CI _IOW('o', 204, __u8) + +#endif /*_UAPI_DVBNS_H_*/ --- -2.1.4 - diff --git a/projects/Generic/linux/linux.x86_64.conf b/projects/Generic/linux/linux.x86_64.conf index 843564465c..e55f5aafe5 100644 --- a/projects/Generic/linux/linux.x86_64.conf +++ b/projects/Generic/linux/linux.x86_64.conf @@ -2808,6 +2808,7 @@ CONFIG_DVB_MANTIS=m # CONFIG_DVB_HOPPER is not set CONFIG_DVB_NGENE=m CONFIG_DVB_DDBRIDGE=m +# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set CONFIG_DVB_SMIPCIE=m # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_V4L_MEM2MEM_DRIVERS is not set diff --git a/projects/Virtual/linux/linux.x86_64.conf b/projects/Virtual/linux/linux.x86_64.conf index d953a18caa..cfd36d1672 100644 --- a/projects/Virtual/linux/linux.x86_64.conf +++ b/projects/Virtual/linux/linux.x86_64.conf @@ -2785,6 +2785,7 @@ CONFIG_DVB_MANTIS=m # CONFIG_DVB_HOPPER is not set CONFIG_DVB_NGENE=m CONFIG_DVB_DDBRIDGE=m +# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set CONFIG_DVB_SMIPCIE=m # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_V4L_MEM2MEM_DRIVERS is not set