From 34fb3e070927de8e956ec9f2fede41fe3dc767ee Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 9 Sep 2019 19:38:06 +0200 Subject: [PATCH] Allwinner: Update patches and config for Linux 5.3 --- projects/Allwinner/linux/linux.aarch64.conf | 184 +- projects/Allwinner/linux/linux.arm.conf | 298 +- .../linux/0001-hdmi-sound-improvements.patch | 31 +- .../linux/0002-backport-from-5.3.patch | 3200 ----------------- ...5.4.patch => 0002-backport-from-5.4.patch} | 0 .../linux/0006-wip-cec-improvements.patch | 5 +- 6 files changed, 342 insertions(+), 3376 deletions(-) delete mode 100644 projects/Allwinner/patches/linux/0002-backport-from-5.3.patch rename projects/Allwinner/patches/linux/{0003-backport-from-5.4.patch => 0002-backport-from-5.4.patch} (100%) diff --git a/projects/Allwinner/linux/linux.aarch64.conf b/projects/Allwinner/linux/linux.aarch64.conf index f53104c3cb..2efec5fdec 100644 --- a/projects/Allwinner/linux/linux.aarch64.conf +++ b/projects/Allwinner/linux/linux.aarch64.conf @@ -20,6 +20,7 @@ CONFIG_THREAD_INFO_IN_TASK=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set +# CONFIG_HEADER_TEST is not set CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" @@ -78,6 +79,7 @@ CONFIG_HIGH_RES_TIMERS=y # CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y CONFIG_PREEMPT_COUNT=y +CONFIG_PREEMPTION=y # # CPU/Task time and stats accounting @@ -116,6 +118,13 @@ CONFIG_LOG_BUF_SHIFT=17 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# CONFIG_UCLAMP_TASK is not set +# end of Scheduler features + CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_NUMA_BALANCING=y @@ -127,7 +136,6 @@ CONFIG_MEMCG_SWAP=y CONFIG_MEMCG_SWAP_ENABLED=y CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y -# CONFIG_DEBUG_BLK_CGROUP is not set CONFIG_CGROUP_WRITEBACK=y CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y @@ -244,7 +252,6 @@ CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CSUM=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ZONE_DMA32=y -CONFIG_HAVE_GENERIC_GUP=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_SMP=y CONFIG_KERNEL_MODE_NEON=y @@ -406,6 +413,7 @@ CONFIG_ARM64_PTR_AUTH=y CONFIG_ARM64_SVE=y CONFIG_ARM64_MODULE_PLTS=y +# CONFIG_ARM64_PSEUDO_NMI is not set # CONFIG_RANDOMIZE_BASE is not set # end of Kernel Features @@ -577,6 +585,7 @@ CONFIG_GENERIC_IDLE_POLL_SETUP=y CONFIG_ARCH_HAS_FORTIFY_SOURCE=y CONFIG_ARCH_HAS_KEEPINITRD=y CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y @@ -721,6 +730,7 @@ CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_FAST_GUP=y CONFIG_ARCH_KEEP_MEMBLOCK=y CONFIG_MEMORY_ISOLATION=y # CONFIG_MEMORY_HOTPLUG is not set @@ -750,6 +760,7 @@ CONFIG_CMA_AREAS=7 CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_FRAME_VECTOR=y # CONFIG_PERCPU_STATS is not set # CONFIG_GUP_BENCHMARK is not set @@ -1069,6 +1080,7 @@ CONFIG_IP6_NF_TARGET_MASQUERADE=m # end of IPv6: Netfilter Configuration CONFIG_NF_DEFRAG_IPV6=m +# CONFIG_NF_CONNTRACK_BRIDGE is not set # CONFIG_BRIDGE_NF_EBTABLES is not set # CONFIG_BPFILTER is not set # CONFIG_IP_DCCP is not set @@ -1206,6 +1218,7 @@ CONFIG_BT_QCA=m CONFIG_BT_HCIBTUSB=m # CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set CONFIG_BT_HCIBTUSB_BCM=y +# CONFIG_BT_HCIBTUSB_MTK is not set CONFIG_BT_HCIBTUSB_RTL=y # CONFIG_BT_HCIBTSDIO is not set CONFIG_BT_HCIUART=m @@ -1277,6 +1290,7 @@ CONFIG_NET_9P=y # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_PAGE_POOL=y CONFIG_FAILOVER=y CONFIG_HAVE_EBPF_JIT=y @@ -1304,6 +1318,7 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_COMPRESS is not set # end of Firmware loader CONFIG_WANT_DEV_COREDUMP=y @@ -1421,6 +1436,7 @@ CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_MTK_QUADSPI is not set # CONFIG_MTD_UBI is not set +# CONFIG_MTD_HYPERBUS is not set CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set @@ -1471,10 +1487,10 @@ CONFIG_BLK_DEV_NBD=m # CONFIG_SENSORS_APDS990X is not set # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set -# CONFIG_USB_SWITCH_FSA9480 is not set # CONFIG_LATTICE_ECP3_CONFIG is not set CONFIG_SRAM=y CONFIG_VEXPRESS_SYSCFG=y +# CONFIG_XILINX_SDFEC is not set # CONFIG_PVPANIC is not set # CONFIG_C2PORT is not set @@ -1557,7 +1573,6 @@ CONFIG_SCSI_DMA=y # CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set @@ -1716,6 +1731,7 @@ CONFIG_NET_VENDOR_CORTINA=y # CONFIG_DNET is not set CONFIG_NET_VENDOR_EZCHIP=y # CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set +# CONFIG_NET_VENDOR_GOOGLE is not set CONFIG_NET_VENDOR_HISILICON=y CONFIG_HIX5HD2_GMAC=y # CONFIG_HISI_FEMAC is not set @@ -1763,6 +1779,7 @@ CONFIG_SMSC911X=y CONFIG_NET_VENDOR_SOCIONEXT=y CONFIG_NET_VENDOR_STMICRO=y CONFIG_STMMAC_ETH=y +# CONFIG_STMMAC_SELFTESTS is not set CONFIG_STMMAC_PLATFORM=y # CONFIG_DWMAC_DWC_QOS_ETH is not set CONFIG_DWMAC_GENERIC=y @@ -1789,6 +1806,7 @@ CONFIG_MDIO_BUS_MUX_MMIOREG=y # CONFIG_MDIO_MSCC_MIIM is not set # CONFIG_MDIO_OCTEON is not set # CONFIG_MDIO_SUN4I is not set +CONFIG_PHYLINK=y CONFIG_PHYLIB=y CONFIG_SWPHY=y # CONFIG_LED_TRIGGER_PHY is not set @@ -1796,6 +1814,7 @@ CONFIG_SWPHY=y # # MII PHY device drivers # +# CONFIG_SFP is not set CONFIG_AC200_PHY=y # CONFIG_AMD_PHY is not set # CONFIG_AQUANTIA_PHY is not set @@ -1823,6 +1842,7 @@ CONFIG_MICROCHIP_PHY=m # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_QSEMI_PHY is not set CONFIG_REALTEK_PHY=y # CONFIG_RENESAS_PHY is not set @@ -2249,10 +2269,12 @@ CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y # CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set # end of Serial drivers +CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y # CONFIG_HVC_DCC is not set # CONFIG_IPMI_HANDLER is not set +# CONFIG_IPMB_DEVICE_INTERFACE is not set CONFIG_HW_RANDOM=m # CONFIG_HW_RANDOM_TIMERIOMEM is not set # CONFIG_RAW_DRIVER is not set @@ -2375,7 +2397,7 @@ CONFIG_SPI_SPIDEV=m # CONFIG_SPI_LOOPBACK_TEST is not set # CONFIG_SPI_TLE62X0 is not set # CONFIG_SPI_SLAVE is not set -CONFIG_SPMI=y +# CONFIG_SPMI is not set # CONFIG_HSI is not set CONFIG_PPS=y # CONFIG_PPS_DEBUG is not set @@ -2516,8 +2538,10 @@ CONFIG_POWER_RESET_SYSCON=y # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set CONFIG_REBOOT_MODE=y CONFIG_SYSCON_REBOOT_MODE=y +# CONFIG_NVMEM_REBOOT_MODE is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_PDA_POWER is not set # CONFIG_GENERIC_ADC_BATTERY is not set # CONFIG_TEST_POWER is not set @@ -2714,6 +2738,7 @@ CONFIG_WATCHDOG=y CONFIG_WATCHDOG_CORE=y # CONFIG_WATCHDOG_NOWAYOUT is not set CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set # @@ -2735,7 +2760,6 @@ CONFIG_ARM_SP805_WATCHDOG=y CONFIG_SUNXI_WATCHDOG=y # CONFIG_MAX63XX_WATCHDOG is not set # CONFIG_MAX77620_WATCHDOG is not set -# CONFIG_IMX_SC_WDT is not set # CONFIG_MEN_A21_WDT is not set # @@ -2836,7 +2860,7 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_TPS80031 is not set # CONFIG_TWL4030_CORE is not set # CONFIG_TWL6040_CORE is not set -# CONFIG_MFD_WL1273_CORE is not set +CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_LM3533 is not set # CONFIG_MFD_TC3589X is not set # CONFIG_MFD_TQMX86 is not set @@ -2849,6 +2873,7 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set CONFIG_MFD_VEXPRESS_SYSREG=y @@ -2892,11 +2917,11 @@ CONFIG_REGULATOR_MAX77620=y # CONFIG_REGULATOR_PV88080 is not set # CONFIG_REGULATOR_PV88090 is not set CONFIG_REGULATOR_PWM=y -CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_REGULATOR_RK808=y # CONFIG_REGULATOR_S2MPA01 is not set CONFIG_REGULATOR_S2MPS11=y # CONFIG_REGULATOR_S5M8767 is not set +# CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_SY8106A is not set # CONFIG_REGULATOR_TPS51632 is not set # CONFIG_REGULATOR_TPS62360 is not set @@ -2952,7 +2977,7 @@ CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_ANALOG_TV_SUPPORT=y CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -# CONFIG_MEDIA_RADIO_SUPPORT is not set +CONFIG_MEDIA_RADIO_SUPPORT=y # CONFIG_MEDIA_SDR_SUPPORT is not set CONFIG_MEDIA_CEC_SUPPORT=y # CONFIG_MEDIA_CEC_RC is not set @@ -2972,7 +2997,7 @@ CONFIG_VIDEOBUF_GEN=m CONFIG_VIDEOBUF_VMALLOC=m CONFIG_DVB_CORE=y # CONFIG_DVB_MMAP is not set -# CONFIG_DVB_NET is not set +CONFIG_DVB_NET=y CONFIG_TTPCI_EEPROM=m CONFIG_DVB_MAX_ADAPTERS=16 # CONFIG_DVB_DYNAMIC_MINORS is not set @@ -2987,58 +3012,8 @@ CONFIG_MEDIA_USB_SUPPORT=y # # Webcam devices # -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -# CONFIG_USB_M5602 is not set -# CONFIG_USB_STV06XX is not set -# CONFIG_USB_GL860 is not set -# CONFIG_USB_GSPCA_BENQ is not set -# CONFIG_USB_GSPCA_CONEX is not set -# CONFIG_USB_GSPCA_CPIA1 is not set -# CONFIG_USB_GSPCA_DTCS033 is not set -# CONFIG_USB_GSPCA_ETOMS is not set -# CONFIG_USB_GSPCA_FINEPIX is not set -# CONFIG_USB_GSPCA_JEILINJ is not set -# CONFIG_USB_GSPCA_JL2005BCD is not set -# CONFIG_USB_GSPCA_KINECT is not set -# CONFIG_USB_GSPCA_KONICA is not set -# CONFIG_USB_GSPCA_MARS is not set -# CONFIG_USB_GSPCA_MR97310A is not set -# CONFIG_USB_GSPCA_NW80X is not set -# CONFIG_USB_GSPCA_OV519 is not set -# CONFIG_USB_GSPCA_OV534 is not set -# CONFIG_USB_GSPCA_OV534_9 is not set -# CONFIG_USB_GSPCA_PAC207 is not set -# CONFIG_USB_GSPCA_PAC7302 is not set -# CONFIG_USB_GSPCA_PAC7311 is not set -# CONFIG_USB_GSPCA_SE401 is not set -# CONFIG_USB_GSPCA_SN9C2028 is not set -# CONFIG_USB_GSPCA_SN9C20X is not set -# CONFIG_USB_GSPCA_SONIXB is not set -# CONFIG_USB_GSPCA_SONIXJ is not set -# CONFIG_USB_GSPCA_SPCA500 is not set -# CONFIG_USB_GSPCA_SPCA501 is not set -# CONFIG_USB_GSPCA_SPCA505 is not set -# CONFIG_USB_GSPCA_SPCA506 is not set -# CONFIG_USB_GSPCA_SPCA508 is not set -# CONFIG_USB_GSPCA_SPCA561 is not set -# CONFIG_USB_GSPCA_SPCA1528 is not set -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -# CONFIG_USB_GSPCA_SQ930X is not set -# CONFIG_USB_GSPCA_STK014 is not set -# CONFIG_USB_GSPCA_STK1135 is not set -# CONFIG_USB_GSPCA_STV0680 is not set -# CONFIG_USB_GSPCA_SUNPLUS is not set -# CONFIG_USB_GSPCA_T613 is not set -# CONFIG_USB_GSPCA_TOPRO is not set -# CONFIG_USB_GSPCA_TOUPTEK is not set -# CONFIG_USB_GSPCA_TV8532 is not set -# CONFIG_USB_GSPCA_VC032X is not set -# CONFIG_USB_GSPCA_VICAM is not set -# CONFIG_USB_GSPCA_XIRLINK_CIT is not set -# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_USB_VIDEO_CLASS is not set +# CONFIG_USB_GSPCA is not set # CONFIG_USB_PWC is not set # CONFIG_VIDEO_CPIA2 is not set # CONFIG_USB_ZR364XX is not set @@ -3084,11 +3059,12 @@ CONFIG_DVB_USB=m CONFIG_DVB_USB_DIB3000MC=m CONFIG_DVB_USB_A800=m CONFIG_DVB_USB_DIBUSB_MB=m -# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y CONFIG_DVB_USB_DIBUSB_MC=m CONFIG_DVB_USB_DIB0700=m CONFIG_DVB_USB_UMT_010=m CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_CXUSB_ANALOG=y CONFIG_DVB_USB_M920X=m CONFIG_DVB_USB_DIGITV=m CONFIG_DVB_USB_VP7045=m @@ -3142,13 +3118,40 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set # CONFIG_VIDEO_SH_VEU is not set # CONFIG_V4L_TEST_DRIVERS is not set -# CONFIG_DVB_PLATFORM_DRIVERS is not set -# CONFIG_CEC_PLATFORM_DRIVERS is not set +CONFIG_DVB_PLATFORM_DRIVERS=y +CONFIG_CEC_PLATFORM_DRIVERS=y +# CONFIG_CEC_GPIO is not set # # Supported MMC/SDIO adapters # # CONFIG_SMS_SDIO_DRV is not set +CONFIG_RADIO_ADAPTERS=y +CONFIG_RADIO_TEA575X=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m +CONFIG_RADIO_SI4713=m +CONFIG_USB_SI4713=m +CONFIG_PLATFORM_SI4713=m +CONFIG_I2C_SI4713=m +CONFIG_USB_MR800=m +CONFIG_USB_DSBR=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_USB_KEENE=m +CONFIG_USB_RAREMONO=m +CONFIG_USB_MA901=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m + +# +# Texas Instruments WL128x FM driver (ST based) +# +# end of Texas Instruments WL128x FM driver (ST based) + CONFIG_MEDIA_COMMON_OPTIONS=y # @@ -3238,7 +3241,7 @@ CONFIG_VIDEO_MT9V011=m # # Media SPI Adapters # -# CONFIG_CXD2880_SPI_DRV is not set +CONFIG_CXD2880_SPI_DRV=m # end of Media SPI Adapters CONFIG_MEDIA_TUNER=y @@ -3248,6 +3251,8 @@ CONFIG_MEDIA_TUNER_TDA8290=y CONFIG_MEDIA_TUNER_TDA827X=y CONFIG_MEDIA_TUNER_TDA18271=y CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y CONFIG_MEDIA_TUNER_MT20XX=y CONFIG_MEDIA_TUNER_MT2060=m CONFIG_MEDIA_TUNER_MT2063=m @@ -3462,11 +3467,12 @@ CONFIG_DRM_PANEL=y # # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_LVDS is not set -CONFIG_DRM_PANEL_SIMPLE=m +# CONFIG_DRM_PANEL_SIMPLE is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set @@ -3733,6 +3739,7 @@ CONFIG_SND_SOC_AK4613=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set # CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CX2072X is not set # CONFIG_SND_SOC_DMIC is not set CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES7134 is not set @@ -3743,12 +3750,12 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_GTM601 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98357A is not set # CONFIG_SND_SOC_MAX98504 is not set # CONFIG_SND_SOC_MAX9867 is not set # CONFIG_SND_SOC_MAX98927 is not set # CONFIG_SND_SOC_MAX98373 is not set # CONFIG_SND_SOC_MAX9860 is not set -# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set # CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set # CONFIG_SND_SOC_PCM1681 is not set # CONFIG_SND_SOC_PCM1789_I2C is not set @@ -4244,6 +4251,8 @@ CONFIG_LEDS_PWM=y CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_MLXREG is not set # CONFIG_LEDS_USER is not set +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set # # LED Triggers @@ -4315,6 +4324,7 @@ CONFIG_RTC_DRV_RK808=m # CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BD70528 is not set # CONFIG_RTC_DRV_BQ32K is not set # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set @@ -4514,6 +4524,7 @@ CONFIG_RTL8723BS=m # end of Speakup console speech CONFIG_STAGING_MEDIA=y +# CONFIG_I2C_BCM2048 is not set CONFIG_VIDEO_SUNXI=y CONFIG_VIDEO_SUNXI_CEDRUS=y @@ -4563,6 +4574,7 @@ CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_MAX9485 is not set # CONFIG_COMMON_CLK_RK808 is not set CONFIG_COMMON_CLK_SCPI=y +# CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set # CONFIG_COMMON_CLK_SI514 is not set # CONFIG_COMMON_CLK_SI544 is not set @@ -4661,13 +4673,6 @@ CONFIG_SOC_BRCMSTB=y # # end of i.MX SoC drivers -# -# IXP4xx SoC drivers -# -# CONFIG_IXP4XX_QMGR is not set -# CONFIG_IXP4XX_NPE is not set -# end of IXP4xx SoC drivers - # # Qualcomm SoC drivers # @@ -4704,6 +4709,7 @@ CONFIG_EXTCON=y # Extcon Device Drivers # # CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_EXTCON_FSA9480 is not set # CONFIG_EXTCON_GPIO is not set # CONFIG_EXTCON_MAX3355 is not set # CONFIG_EXTCON_PTN5150 is not set @@ -4796,9 +4802,6 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_MCP3422 is not set # CONFIG_MCP3911 is not set # CONFIG_NAU7802 is not set -# CONFIG_QCOM_SPMI_IADC is not set -# CONFIG_QCOM_SPMI_VADC is not set -# CONFIG_QCOM_SPMI_ADC5 is not set # CONFIG_SD_ADC_MODULATOR is not set # CONFIG_TI_ADC081C is not set # CONFIG_TI_ADC0832 is not set @@ -4814,6 +4817,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_TLC4541 is not set # CONFIG_VF610_ADC is not set +# CONFIG_XILINX_XADC is not set # end of Analog to digital converters # @@ -4909,6 +4913,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # Phase-Locked Loop (PLL) frequency synthesizers # # CONFIG_ADF4350 is not set +# CONFIG_ADF4371 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL @@ -5070,6 +5075,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # # CONFIG_ABP060MG is not set # CONFIG_BMP280 is not set +# CONFIG_DPS310 is not set # CONFIG_HP03 is not set # CONFIG_MPL115_I2C is not set # CONFIG_MPL115_SPI is not set @@ -5135,6 +5141,7 @@ CONFIG_ARM_GIC=y CONFIG_ARM_GIC_MAX_NR=1 CONFIG_ARM_GIC_V3=y CONFIG_ARM_GIC_V3_ITS=y +# CONFIG_AL_FIC is not set CONFIG_PARTITION_PERCPU=y # end of IRQ chip support @@ -5144,7 +5151,6 @@ CONFIG_RESET_CONTROLLER=y CONFIG_RESET_SIMPLE=y CONFIG_RESET_SUNXI=y # CONFIG_RESET_TI_SYSCON is not set -# CONFIG_FMC is not set # # PHY Subsystem @@ -5160,6 +5166,7 @@ CONFIG_PHY_SUN50I_USB3=y # CONFIG_PHY_CADENCE_DPHY is not set # CONFIG_PHY_CADENCE_SIERRA is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_MIXEL_MIPI_DPHY is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set # CONFIG_PHY_CPCAP_USB is not set @@ -5478,6 +5485,7 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_KEYS=y CONFIG_KEYS_COMPAT=y +# CONFIG_KEYS_REQUEST_CACHE is not set # CONFIG_PERSISTENT_KEYRINGS is not set # CONFIG_BIG_KEYS is not set # CONFIG_TRUSTED_KEYS is not set @@ -5514,6 +5522,8 @@ CONFIG_LSM="yama,loadpin,safesetid,integrity" # Memory initialization # CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set # end of Memory initialization # end of Kernel hardening options # end of Security options @@ -5550,7 +5560,6 @@ CONFIG_CRYPTO_GF128MUL=y CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y # CONFIG_CRYPTO_PCRYPT is not set -CONFIG_CRYPTO_WORKQUEUE=y CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_AUTHENC=y # CONFIG_CRYPTO_TEST is not set @@ -5607,6 +5616,7 @@ CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CRC32=m +# CONFIG_CRYPTO_XXHASH is not set CONFIG_CRYPTO_CRCT10DIF=y CONFIG_CRYPTO_GHASH=m # CONFIG_CRYPTO_POLY1305 is not set @@ -5632,6 +5642,7 @@ CONFIG_CRYPTO_SM3=m CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set # CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_ARC4=m # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set @@ -5675,6 +5686,8 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y CONFIG_CRYPTO_USER_API_AEAD=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set # CONFIG_CRYPTO_DEV_CCP is not set # CONFIG_CRYPTO_DEV_CCREE is not set # CONFIG_CRYPTO_DEV_HISI_SEC is not set @@ -5787,12 +5800,16 @@ CONFIG_GLOB=y # CONFIG_GLOB_SELFTEST is not set CONFIG_NLATTR=y CONFIG_CLZ_TAB=y -# CONFIG_DDR is not set # CONFIG_IRQ_POLL is not set CONFIG_MPILIB=y +CONFIG_DIMLIB=y CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_COMPAT_VDSO=y +CONFIG_CROSS_COMPILE_COMPAT_VDSO="" CONFIG_FONT_SUPPORT=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y @@ -5833,7 +5850,7 @@ CONFIG_FRAME_WARN=2048 # CONFIG_READABLE_ASM is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set +# CONFIG_HEADERS_INSTALL is not set # CONFIG_OPTIMIZE_INLINING is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y @@ -5956,6 +5973,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_SORT is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set +# CONFIG_REED_SOLOMON_TEST is not set # CONFIG_INTERVAL_TREE_TEST is not set # CONFIG_PERCPU_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set @@ -5976,6 +5994,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_VMALLOC is not set # CONFIG_TEST_USER_COPY is not set # CONFIG_TEST_BPF is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set # CONFIG_FIND_BIT_BENCHMARK is not set # CONFIG_TEST_FIRMWARE is not set # CONFIG_TEST_SYSCTL is not set @@ -5984,6 +6003,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_KMOD is not set # CONFIG_TEST_MEMCAT_P is not set # CONFIG_TEST_STACKINIT is not set +# CONFIG_TEST_MEMINIT is not set CONFIG_MEMTEST=y # CONFIG_BUG_ON_DATA_CORRUPTION is not set # CONFIG_SAMPLES is not set diff --git a/projects/Allwinner/linux/linux.arm.conf b/projects/Allwinner/linux/linux.arm.conf index 37695336c7..1c385cd052 100644 --- a/projects/Allwinner/linux/linux.arm.conf +++ b/projects/Allwinner/linux/linux.arm.conf @@ -19,6 +19,7 @@ CONFIG_BUILDTIME_EXTABLE_SORT=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set +# CONFIG_HEADER_TEST is not set CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_BUILD_SALT="" @@ -115,6 +116,13 @@ CONFIG_LOG_BUF_SHIFT=17 CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# CONFIG_UCLAMP_TASK is not set +# end of Scheduler features + CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y CONFIG_MEMCG=y @@ -122,7 +130,6 @@ CONFIG_MEMCG_SWAP=y CONFIG_MEMCG_SWAP_ENABLED=y CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y -# CONFIG_DEBUG_BLK_CGROUP is not set CONFIG_CGROUP_WRITEBACK=y CONFIG_CGROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y @@ -252,7 +259,6 @@ CONFIG_ARCH_MULTIPLATFORM=y # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_NETX is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -365,6 +371,7 @@ CONFIG_ARM_THUMB=y CONFIG_ARM_VIRT_EXT=y CONFIG_SWP_EMULATE=y # CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set # CONFIG_CPU_BPREDICT_DISABLE is not set CONFIG_CPU_SPECTRE=y # CONFIG_HARDEN_BRANCH_PREDICTOR is not set @@ -396,13 +403,16 @@ CONFIG_ARM_ERRATA_643719=y # CONFIG_ARM_ERRATA_818325_852422 is not set # CONFIG_ARM_ERRATA_821420 is not set # CONFIG_ARM_ERRATA_825619 is not set +# CONFIG_ARM_ERRATA_857271 is not set # CONFIG_ARM_ERRATA_852421 is not set # CONFIG_ARM_ERRATA_852423 is not set +# CONFIG_ARM_ERRATA_857272 is not set # end of System Type # # Bus support # +# CONFIG_ARM_ERRATA_814220 is not set # end of Bus support # @@ -735,7 +745,9 @@ CONFIG_BINFMT_ELF=y CONFIG_ELFCORE=y CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y CONFIG_BINFMT_SCRIPT=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y # CONFIG_BINFMT_FLAT is not set +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y # CONFIG_BINFMT_MISC is not set CONFIG_COREDUMP=y # end of Executable file formats @@ -1049,6 +1061,7 @@ CONFIG_IP_NF_TARGET_REDIRECT=m # end of IPv6: Netfilter Configuration CONFIG_NF_DEFRAG_IPV6=m +# CONFIG_NF_CONNTRACK_BRIDGE is not set # CONFIG_BRIDGE_NF_EBTABLES is not set # CONFIG_BPFILTER is not set # CONFIG_IP_DCCP is not set @@ -1231,6 +1244,7 @@ CONFIG_BT_QCA=m CONFIG_BT_HCIBTUSB=m # CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set CONFIG_BT_HCIBTUSB_BCM=y +# CONFIG_BT_HCIBTUSB_MTK is not set CONFIG_BT_HCIBTUSB_RTL=y CONFIG_BT_HCIBTSDIO=m CONFIG_BT_HCIUART=m @@ -1299,6 +1313,7 @@ CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_PAGE_POOL=y # CONFIG_FAILOVER is not set CONFIG_HAVE_EBPF_JIT=y @@ -1325,6 +1340,7 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_COMPRESS is not set # end of Firmware loader CONFIG_WANT_DEV_COREDUMP=y @@ -1413,9 +1429,9 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_SENSORS_APDS990X is not set # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set -# CONFIG_USB_SWITCH_FSA9480 is not set # CONFIG_LATTICE_ECP3_CONFIG is not set # CONFIG_SRAM is not set +# CONFIG_XILINX_SDFEC is not set # CONFIG_PVPANIC is not set # CONFIG_C2PORT is not set @@ -1498,7 +1514,6 @@ CONFIG_SCSI_PROC_FS=y # CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set @@ -1644,6 +1659,7 @@ CONFIG_NET_VENDOR_CORTINA=y CONFIG_NET_VENDOR_EZCHIP=y # CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set # CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_GOOGLE is not set CONFIG_NET_VENDOR_HISILICON=y # CONFIG_HIX5HD2_GMAC is not set # CONFIG_HISI_FEMAC is not set @@ -1677,6 +1693,7 @@ CONFIG_NET_VENDOR_SOLARFLARE=y CONFIG_NET_VENDOR_SOCIONEXT=y CONFIG_NET_VENDOR_STMICRO=y CONFIG_STMMAC_ETH=y +# CONFIG_STMMAC_SELFTESTS is not set CONFIG_STMMAC_PLATFORM=y # CONFIG_DWMAC_DWC_QOS_ETH is not set CONFIG_DWMAC_GENERIC=y @@ -1686,6 +1703,7 @@ CONFIG_NET_VENDOR_SYNOPSYS=y # CONFIG_DWC_XLGMAC is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set CONFIG_MDIO_DEVICE=y CONFIG_MDIO_BUS=y # CONFIG_MDIO_BCM_UNIMAC is not set @@ -1697,6 +1715,7 @@ CONFIG_MDIO_BUS_MUX=y # CONFIG_MDIO_HISI_FEMAC is not set # CONFIG_MDIO_MSCC_MIIM is not set CONFIG_MDIO_SUN4I=y +CONFIG_PHYLINK=y CONFIG_PHYLIB=y CONFIG_SWPHY=y # CONFIG_LED_TRIGGER_PHY is not set @@ -1704,6 +1723,7 @@ CONFIG_SWPHY=y # # MII PHY device drivers # +# CONFIG_SFP is not set # CONFIG_AC200_PHY is not set # CONFIG_AMD_PHY is not set # CONFIG_AQUANTIA_PHY is not set @@ -1731,6 +1751,7 @@ CONFIG_FIXED_PHY=y # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_QSEMI_PHY is not set # CONFIG_REALTEK_PHY is not set # CONFIG_RENESAS_PHY is not set @@ -2104,6 +2125,7 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_ST_ASC is not set # end of Serial drivers +CONFIG_SERIAL_MCTRL_GPIO=y CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y # CONFIG_TTY_PRINTK is not set @@ -2342,6 +2364,7 @@ CONFIG_GPIO_SYSFS=y # CONFIG_POWER_RESET is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_PDA_POWER is not set # CONFIG_GENERIC_ADC_BATTERY is not set # CONFIG_TEST_POWER is not set @@ -2533,6 +2556,7 @@ CONFIG_WATCHDOG=y CONFIG_WATCHDOG_CORE=y # CONFIG_WATCHDOG_NOWAYOUT is not set CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 # CONFIG_WATCHDOG_SYSFS is not set # @@ -2552,7 +2576,6 @@ CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y # CONFIG_DW_WATCHDOG is not set CONFIG_SUNXI_WATCHDOG=y # CONFIG_MAX63XX_WATCHDOG is not set -# CONFIG_IMX_SC_WDT is not set # CONFIG_MEN_A21_WDT is not set # @@ -2680,6 +2703,7 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_STPMIC1 is not set # CONFIG_MFD_STMFX is not set # CONFIG_RAVE_SP_CORE is not set @@ -2719,6 +2743,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_PV88080 is not set # CONFIG_REGULATOR_PV88090 is not set # CONFIG_REGULATOR_PWM is not set +# CONFIG_REGULATOR_SLG51000 is not set CONFIG_REGULATOR_SY8106A=y # CONFIG_REGULATOR_TPS51632 is not set # CONFIG_REGULATOR_TPS62360 is not set @@ -2788,6 +2813,7 @@ CONFIG_VIDEO_V4L2=y # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_TUNER=m CONFIG_V4L2_MEM2MEM_DEV=y +CONFIG_V4L2_FWNODE=m CONFIG_VIDEOBUF_GEN=m CONFIG_VIDEOBUF_VMALLOC=m CONFIG_DVB_CORE=y @@ -2808,56 +2834,7 @@ CONFIG_MEDIA_USB_SUPPORT=y # Webcam devices # # CONFIG_USB_VIDEO_CLASS is not set -CONFIG_USB_GSPCA=m -# CONFIG_USB_M5602 is not set -# CONFIG_USB_STV06XX is not set -# CONFIG_USB_GL860 is not set -# CONFIG_USB_GSPCA_BENQ is not set -# CONFIG_USB_GSPCA_CONEX is not set -# CONFIG_USB_GSPCA_CPIA1 is not set -# CONFIG_USB_GSPCA_DTCS033 is not set -# CONFIG_USB_GSPCA_ETOMS is not set -# CONFIG_USB_GSPCA_FINEPIX is not set -# CONFIG_USB_GSPCA_JEILINJ is not set -# CONFIG_USB_GSPCA_JL2005BCD is not set -# CONFIG_USB_GSPCA_KINECT is not set -# CONFIG_USB_GSPCA_KONICA is not set -# CONFIG_USB_GSPCA_MARS is not set -# CONFIG_USB_GSPCA_MR97310A is not set -# CONFIG_USB_GSPCA_NW80X is not set -# CONFIG_USB_GSPCA_OV519 is not set -# CONFIG_USB_GSPCA_OV534 is not set -# CONFIG_USB_GSPCA_OV534_9 is not set -# CONFIG_USB_GSPCA_PAC207 is not set -# CONFIG_USB_GSPCA_PAC7302 is not set -# CONFIG_USB_GSPCA_PAC7311 is not set -# CONFIG_USB_GSPCA_SE401 is not set -# CONFIG_USB_GSPCA_SN9C2028 is not set -# CONFIG_USB_GSPCA_SN9C20X is not set -# CONFIG_USB_GSPCA_SONIXB is not set -# CONFIG_USB_GSPCA_SONIXJ is not set -# CONFIG_USB_GSPCA_SPCA500 is not set -# CONFIG_USB_GSPCA_SPCA501 is not set -# CONFIG_USB_GSPCA_SPCA505 is not set -# CONFIG_USB_GSPCA_SPCA506 is not set -# CONFIG_USB_GSPCA_SPCA508 is not set -# CONFIG_USB_GSPCA_SPCA561 is not set -# CONFIG_USB_GSPCA_SPCA1528 is not set -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -# CONFIG_USB_GSPCA_SQ930X is not set -# CONFIG_USB_GSPCA_STK014 is not set -# CONFIG_USB_GSPCA_STK1135 is not set -# CONFIG_USB_GSPCA_STV0680 is not set -# CONFIG_USB_GSPCA_SUNPLUS is not set -# CONFIG_USB_GSPCA_T613 is not set -# CONFIG_USB_GSPCA_TOPRO is not set -# CONFIG_USB_GSPCA_TOUPTEK is not set -# CONFIG_USB_GSPCA_TV8532 is not set -# CONFIG_USB_GSPCA_VC032X is not set -# CONFIG_USB_GSPCA_VICAM is not set -# CONFIG_USB_GSPCA_XIRLINK_CIT is not set -# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_USB_GSPCA is not set # CONFIG_USB_PWC is not set # CONFIG_VIDEO_CPIA2 is not set # CONFIG_USB_ZR364XX is not set @@ -2905,6 +2882,7 @@ CONFIG_DVB_USB_DIBUSB_MC=m CONFIG_DVB_USB_DIB0700=m CONFIG_DVB_USB_UMT_010=m CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_CXUSB_ANALOG=y CONFIG_DVB_USB_M920X=m CONFIG_DVB_USB_DIGITV=m CONFIG_DVB_USB_VP7045=m @@ -2983,56 +2961,158 @@ CONFIG_MEDIA_SUBDRV_AUTOSELECT=y CONFIG_MEDIA_ATTACH=y CONFIG_VIDEO_IR_I2C=y +# +# I2C Encoders, decoders, sensors and other helper chips +# + # # Audio decoders, processors and mixers # +CONFIG_VIDEO_TVAUDIO=m +CONFIG_VIDEO_TDA7432=m +CONFIG_VIDEO_TDA9840=m +CONFIG_VIDEO_TDA1997X=m +CONFIG_VIDEO_TEA6415C=m +CONFIG_VIDEO_TEA6420=m CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS3308=m +CONFIG_VIDEO_CS5345=m CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_TLV320AIC23B=m CONFIG_VIDEO_UDA1342=m CONFIG_VIDEO_WM8775=m +CONFIG_VIDEO_WM8739=m +CONFIG_VIDEO_VP27SMPX=m CONFIG_VIDEO_SONY_BTF_MPX=m # # RDS decoders # +CONFIG_VIDEO_SAA6588=m # # Video decoders # +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_ADV7183=m +CONFIG_VIDEO_ADV748X=m +CONFIG_VIDEO_ADV7604=m +CONFIG_VIDEO_ADV7604_CEC=y +CONFIG_VIDEO_ADV7842=m +CONFIG_VIDEO_ADV7842_CEC=y +CONFIG_VIDEO_BT819=m +CONFIG_VIDEO_BT856=m +CONFIG_VIDEO_BT866=m +CONFIG_VIDEO_KS0127=m +CONFIG_VIDEO_ML86V7667=m +CONFIG_VIDEO_SAA7110=m CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TC358743_CEC=y +CONFIG_VIDEO_TVP514X=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TVP7002=m CONFIG_VIDEO_TW2804=m CONFIG_VIDEO_TW9903=m CONFIG_VIDEO_TW9906=m +CONFIG_VIDEO_TW9910=m +CONFIG_VIDEO_VPX3220=m # # Video and audio decoders # +CONFIG_VIDEO_SAA717X=m CONFIG_VIDEO_CX25840=m # # Video encoders # +CONFIG_VIDEO_SAA7127=m +CONFIG_VIDEO_SAA7185=m +CONFIG_VIDEO_ADV7170=m +CONFIG_VIDEO_ADV7175=m +CONFIG_VIDEO_ADV7343=m +CONFIG_VIDEO_ADV7393=m +CONFIG_VIDEO_ADV7511=m +CONFIG_VIDEO_ADV7511_CEC=y +CONFIG_VIDEO_AD9389B=m +CONFIG_VIDEO_AK881X=m +CONFIG_VIDEO_THS8200=m # # Camera sensor devices # +# CONFIG_VIDEO_IMX214 is not set +# CONFIG_VIDEO_IMX258 is not set +# CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX319 is not set +# CONFIG_VIDEO_IMX355 is not set +# CONFIG_VIDEO_OV2640 is not set +# CONFIG_VIDEO_OV2659 is not set +# CONFIG_VIDEO_OV2680 is not set +# CONFIG_VIDEO_OV2685 is not set +# CONFIG_VIDEO_OV5640 is not set +# CONFIG_VIDEO_OV5645 is not set +# CONFIG_VIDEO_OV5647 is not set +# CONFIG_VIDEO_OV6650 is not set +# CONFIG_VIDEO_OV5670 is not set +# CONFIG_VIDEO_OV5695 is not set +# CONFIG_VIDEO_OV7251 is not set +# CONFIG_VIDEO_OV772X is not set CONFIG_VIDEO_OV7640=m +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_OV7740 is not set +# CONFIG_VIDEO_OV8856 is not set +# CONFIG_VIDEO_OV9640 is not set +# CONFIG_VIDEO_OV9650 is not set +# CONFIG_VIDEO_OV13858 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_MT9M001 is not set +# CONFIG_VIDEO_MT9M032 is not set +# CONFIG_VIDEO_MT9M111 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T001 is not set +# CONFIG_VIDEO_MT9T112 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_MT9V111 is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_M5MOLS is not set +# CONFIG_VIDEO_RJ54N1 is not set +# CONFIG_VIDEO_S5K6AA is not set +# CONFIG_VIDEO_S5K6A3 is not set +# CONFIG_VIDEO_S5K4ECGX is not set +# CONFIG_VIDEO_S5K5BAF is not set +# CONFIG_VIDEO_SMIAPP is not set +# CONFIG_VIDEO_ET8EK8 is not set +# CONFIG_VIDEO_S5C73M3 is not set # # Lens drivers # +# CONFIG_VIDEO_AD5820 is not set +# CONFIG_VIDEO_AK7375 is not set +# CONFIG_VIDEO_DW9714 is not set +# CONFIG_VIDEO_DW9807_VCM is not set # # Flash devices # +# CONFIG_VIDEO_ADP1653 is not set +# CONFIG_VIDEO_LM3560 is not set +# CONFIG_VIDEO_LM3646 is not set # # Video improvement chips # +CONFIG_VIDEO_UPD64031A=m +CONFIG_VIDEO_UPD64083=m # # Audio/Video compression chips # +CONFIG_VIDEO_SAA6752HS=m # # SDR tuner chips @@ -3041,6 +3121,17 @@ CONFIG_VIDEO_OV7640=m # # Miscellaneous helper chips # +CONFIG_VIDEO_THS7303=m +CONFIG_VIDEO_M52790=m +CONFIG_VIDEO_I2C=m +CONFIG_VIDEO_ST_MIPID02=m +# end of I2C Encoders, decoders, sensors and other helper chips + +# +# SPI helper chips +# +CONFIG_VIDEO_GS1662=m +# end of SPI helper chips # # Media SPI Adapters @@ -3049,16 +3140,24 @@ CONFIG_VIDEO_OV7640=m # end of Media SPI Adapters CONFIG_MEDIA_TUNER=y + +# +# Customize TV tuners +# CONFIG_MEDIA_TUNER_SIMPLE=y CONFIG_MEDIA_TUNER_TDA18250=m CONFIG_MEDIA_TUNER_TDA8290=y CONFIG_MEDIA_TUNER_TDA827X=y CONFIG_MEDIA_TUNER_TDA18271=y CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MSI001=m CONFIG_MEDIA_TUNER_MT20XX=y CONFIG_MEDIA_TUNER_MT2060=m CONFIG_MEDIA_TUNER_MT2063=m CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MT2131=m CONFIG_MEDIA_TUNER_QT1010=m CONFIG_MEDIA_TUNER_XC2028=y CONFIG_MEDIA_TUNER_XC5000=y @@ -3074,10 +3173,19 @@ CONFIG_MEDIA_TUNER_FC0013=m CONFIG_MEDIA_TUNER_TDA18212=m CONFIG_MEDIA_TUNER_E4000=m CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_M88RS6000T=m CONFIG_MEDIA_TUNER_TUA9001=m CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_TUNER_IT913X=m CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_MXL301RF=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +# end of Customize TV tuners + +# +# Customise DVB Frontends +# # # Multistandard (satellite) frontends @@ -3085,21 +3193,28 @@ CONFIG_MEDIA_TUNER_R820T=m CONFIG_DVB_STB0899=m CONFIG_DVB_STB6100=m CONFIG_DVB_STV090x=m +CONFIG_DVB_STV0910=m CONFIG_DVB_STV6110x=m +CONFIG_DVB_STV6111=m +CONFIG_DVB_MXL5XX=m CONFIG_DVB_M88DS3103=m # # Multistandard (cable + terrestrial) frontends # CONFIG_DVB_DRXK=m +CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_SI2165=m CONFIG_DVB_MN88472=m CONFIG_DVB_MN88473=m # # DVB-S (satellite) frontends # +CONFIG_DVB_CX24110=m CONFIG_DVB_CX24123=m CONFIG_DVB_MT312=m +CONFIG_DVB_ZL10036=m CONFIG_DVB_ZL10039=m CONFIG_DVB_S5H1420=m CONFIG_DVB_STV0288=m @@ -3107,20 +3222,33 @@ CONFIG_DVB_STB6000=m CONFIG_DVB_STV0299=m CONFIG_DVB_STV6110=m CONFIG_DVB_STV0900=m +CONFIG_DVB_TDA8083=m CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_VES1X93=m CONFIG_DVB_TUNER_ITD1000=m CONFIG_DVB_TUNER_CX24113=m CONFIG_DVB_TDA826X=m +CONFIG_DVB_TUA6100=m CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m CONFIG_DVB_CX24120=m CONFIG_DVB_SI21XX=m CONFIG_DVB_TS2020=m CONFIG_DVB_DS3000=m +CONFIG_DVB_MB86A16=m +CONFIG_DVB_TDA10071=m # # DVB-T (terrestrial) frontends # +CONFIG_DVB_SP8870=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_CX22700=m CONFIG_DVB_CX22702=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_L64781=m CONFIG_DVB_TDA1004X=m CONFIG_DVB_NXT6000=m CONFIG_DVB_MT352=m @@ -3129,9 +3257,11 @@ CONFIG_DVB_DIB3000MB=m CONFIG_DVB_DIB3000MC=m CONFIG_DVB_DIB7000M=m CONFIG_DVB_DIB7000P=m +CONFIG_DVB_DIB9000=m CONFIG_DVB_TDA10048=m CONFIG_DVB_AF9013=m CONFIG_DVB_EC100=m +CONFIG_DVB_STV0367=m CONFIG_DVB_CXD2820R=m CONFIG_DVB_CXD2841ER=m CONFIG_DVB_RTL2830=m @@ -3140,10 +3270,13 @@ CONFIG_DVB_SI2168=m CONFIG_DVB_AS102_FE=m CONFIG_DVB_ZD1301_DEMOD=m CONFIG_DVB_GP8PSK_FE=m +CONFIG_DVB_CXD2880=m # # DVB-C (cable) frontends # +CONFIG_DVB_VES1820=m +CONFIG_DVB_TDA10021=m CONFIG_DVB_TDA10023=m CONFIG_DVB_STV0297=m @@ -3151,9 +3284,12 @@ CONFIG_DVB_STV0297=m # ATSC (North American/Korean Terrestrial/Cable DTV) frontends # CONFIG_DVB_NXT200X=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_OR51132=m CONFIG_DVB_BCM3510=m CONFIG_DVB_LGDT330X=m CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m CONFIG_DVB_LG2160=m CONFIG_DVB_S5H1409=m CONFIG_DVB_AU8522=m @@ -3164,12 +3300,15 @@ CONFIG_DVB_S5H1411=m # # ISDB-T (terrestrial) frontends # +CONFIG_DVB_S921=m CONFIG_DVB_DIB8000=m +CONFIG_DVB_MB86A20S=m # # ISDB-S (satellite) & ISDB-T (terrestrial) frontends # CONFIG_DVB_TC90522=m +CONFIG_DVB_MN88443X=m # # Digital terrestrial only tuners/PLL @@ -3181,24 +3320,37 @@ CONFIG_DVB_TUNER_DIB0090=m # # SEC control devices for DVB-S # +CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_LNBH25=m +CONFIG_DVB_LNBH29=m CONFIG_DVB_LNBP21=m CONFIG_DVB_LNBP22=m +CONFIG_DVB_ISL6405=m CONFIG_DVB_ISL6421=m CONFIG_DVB_ISL6423=m +CONFIG_DVB_A8293=m +CONFIG_DVB_LGS8GL5=m CONFIG_DVB_LGS8GXX=m CONFIG_DVB_ATBM8830=m +CONFIG_DVB_TDA665x=m CONFIG_DVB_IX2505V=m CONFIG_DVB_M88RS2000=m CONFIG_DVB_AF9033=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_HELENE=m # # Common Interface (EN50221) controller drivers # +CONFIG_DVB_CXD2099=m CONFIG_DVB_SP2=m # # Tools to develop new frontends # +# CONFIG_DVB_DUMMY_FE is not set +# end of Customise DVB Frontends # # Graphics support @@ -3313,6 +3465,7 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_TVE200 is not set # CONFIG_DRM_LIMA is not set # CONFIG_DRM_PANFROST is not set +# CONFIG_DRM_MCDE is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y @@ -3509,6 +3662,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set # CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CX2072X is not set # CONFIG_SND_SOC_DMIC is not set CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_ES7134 is not set @@ -3519,6 +3673,7 @@ CONFIG_SND_SOC_HDMI_CODEC=y # CONFIG_SND_SOC_GTM601 is not set # CONFIG_SND_SOC_INNO_RK3036 is not set # CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98357A is not set # CONFIG_SND_SOC_MAX98504 is not set # CONFIG_SND_SOC_MAX9867 is not set # CONFIG_SND_SOC_MAX98927 is not set @@ -4022,6 +4177,8 @@ CONFIG_LEDS_GPIO=y # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_MLXREG is not set # CONFIG_LEDS_USER is not set +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set # # LED Triggers @@ -4090,6 +4247,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BD70528 is not set # CONFIG_RTC_DRV_BQ32K is not set # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set @@ -4323,6 +4481,7 @@ CONFIG_COMMON_CLK=y # # CONFIG_CLK_HSDK is not set # CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set # CONFIG_COMMON_CLK_SI514 is not set # CONFIG_COMMON_CLK_SI544 is not set @@ -4406,13 +4565,6 @@ CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y # # end of i.MX SoC drivers -# -# IXP4xx SoC drivers -# -# CONFIG_IXP4XX_QMGR is not set -# CONFIG_IXP4XX_NPE is not set -# end of IXP4xx SoC drivers - # # Qualcomm SoC drivers # @@ -4449,6 +4601,7 @@ CONFIG_EXTCON=y # Extcon Device Drivers # # CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_EXTCON_FSA9480 is not set # CONFIG_EXTCON_GPIO is not set # CONFIG_EXTCON_MAX3355 is not set # CONFIG_EXTCON_PTN5150 is not set @@ -4555,6 +4708,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_TLC4541 is not set # CONFIG_VF610_ADC is not set +# CONFIG_XILINX_XADC is not set # end of Analog to digital converters # @@ -4650,6 +4804,7 @@ CONFIG_SUN4I_GPADC=y # Phase-Locked Loop (PLL) frequency synthesizers # # CONFIG_ADF4350 is not set +# CONFIG_ADF4371 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL @@ -4804,6 +4959,7 @@ CONFIG_SUN4I_GPADC=y # # CONFIG_ABP060MG is not set # CONFIG_BMP280 is not set +# CONFIG_DPS310 is not set # CONFIG_HP03 is not set # CONFIG_MPL115_I2C is not set # CONFIG_MPL115_SPI is not set @@ -4867,6 +5023,7 @@ CONFIG_PWM_SUN4I=y CONFIG_IRQCHIP=y CONFIG_ARM_GIC=y CONFIG_ARM_GIC_MAX_NR=1 +# CONFIG_AL_FIC is not set # end of IRQ chip support # CONFIG_IPACK_BUS is not set @@ -4875,7 +5032,6 @@ CONFIG_RESET_CONTROLLER=y CONFIG_RESET_SIMPLE=y CONFIG_RESET_SUNXI=y # CONFIG_RESET_TI_SYSCON is not set -# CONFIG_FMC is not set # # PHY Subsystem @@ -4891,6 +5047,7 @@ CONFIG_PHY_SUN50I_USB3=y # CONFIG_PHY_CADENCE_DPHY is not set # CONFIG_PHY_CADENCE_SIERRA is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_MIXEL_MIPI_DPHY is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set # CONFIG_PHY_CPCAP_USB is not set @@ -5174,6 +5331,7 @@ CONFIG_NLS_UTF8=y # Security options # CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set # CONFIG_PERSISTENT_KEYRINGS is not set # CONFIG_BIG_KEYS is not set # CONFIG_ENCRYPTED_KEYS is not set @@ -5196,6 +5354,8 @@ CONFIG_LSM="yama,loadpin,safesetid,integrity" # Memory initialization # CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set # end of Memory initialization # end of Kernel hardening options # end of Security options @@ -5229,7 +5389,6 @@ CONFIG_CRYPTO_GF128MUL=m CONFIG_CRYPTO_NULL=y CONFIG_CRYPTO_NULL2=y # CONFIG_CRYPTO_PCRYPT is not set -CONFIG_CRYPTO_WORKQUEUE=y # CONFIG_CRYPTO_CRYPTD is not set CONFIG_CRYPTO_AUTHENC=m # CONFIG_CRYPTO_TEST is not set @@ -5285,6 +5444,7 @@ CONFIG_CRYPTO_HMAC=m # CONFIG_CRYPTO_CRC32C=y CONFIG_CRYPTO_CRC32=m +# CONFIG_CRYPTO_XXHASH is not set # CONFIG_CRYPTO_CRCT10DIF is not set CONFIG_CRYPTO_GHASH=m # CONFIG_CRYPTO_POLY1305 is not set @@ -5310,6 +5470,7 @@ CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set # CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_LIB_ARC4=m CONFIG_CRYPTO_ARC4=m # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set @@ -5353,6 +5514,8 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y CONFIG_CRYPTO_USER_API_AEAD=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set CONFIG_CRYPTO_DEV_SUN4I_SS=y # CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG is not set # CONFIG_CRYPTO_DEV_CCREE is not set @@ -5448,9 +5611,9 @@ CONFIG_GLOB=y # CONFIG_GLOB_SELFTEST is not set CONFIG_NLATTR=y CONFIG_CLZ_TAB=y -# CONFIG_DDR is not set # CONFIG_IRQ_POLL is not set CONFIG_MPILIB=y +# CONFIG_DIMLIB is not set CONFIG_LIBFDT=y CONFIG_OID_REGISTRY=y CONFIG_FONT_SUPPORT=y @@ -5488,7 +5651,7 @@ CONFIG_FRAME_WARN=1024 # CONFIG_READABLE_ASM is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set +# CONFIG_HEADERS_INSTALL is not set # CONFIG_OPTIMIZE_INLINING is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y @@ -5605,6 +5768,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_SORT is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_RBTREE_TEST is not set +# CONFIG_REED_SOLOMON_TEST is not set # CONFIG_INTERVAL_TREE_TEST is not set # CONFIG_PERCPU_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set @@ -5625,6 +5789,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_VMALLOC is not set # CONFIG_TEST_USER_COPY is not set # CONFIG_TEST_BPF is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set # CONFIG_FIND_BIT_BENCHMARK is not set # CONFIG_TEST_FIRMWARE is not set # CONFIG_TEST_SYSCTL is not set @@ -5633,6 +5798,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_KMOD is not set # CONFIG_TEST_MEMCAT_P is not set # CONFIG_TEST_STACKINIT is not set +# CONFIG_TEST_MEMINIT is not set # CONFIG_MEMTEST is not set # CONFIG_BUG_ON_DATA_CORRUPTION is not set # CONFIG_SAMPLES is not set diff --git a/projects/Allwinner/patches/linux/0001-hdmi-sound-improvements.patch b/projects/Allwinner/patches/linux/0001-hdmi-sound-improvements.patch index 1cfae37641..feb8b21abb 100644 --- a/projects/Allwinner/patches/linux/0001-hdmi-sound-improvements.patch +++ b/projects/Allwinner/patches/linux/0001-hdmi-sound-improvements.patch @@ -294,9 +294,9 @@ index fb2f0ac..bfb1519 100644 --- a/sound/soc/codecs/hdmi-codec.c +++ b/sound/soc/codecs/hdmi-codec.c @@ -285,6 +285,8 @@ struct hdmi_codec_priv { - uint8_t eld[MAX_ELD_BYTES]; struct snd_pcm_chmap *chmap_info; unsigned int chmap_idx; + struct mutex lock; + struct snd_card *snd_card; + struct snd_kcontrol *kctl; }; @@ -952,13 +952,12 @@ index bc128e2..2e3fc59 100644 #define SUN4I_I2S_CTRL_TX_EN BIT(2) #define SUN4I_I2S_CTRL_RX_EN BIT(1) #define SUN4I_I2S_CTRL_GL_EN BIT(0) -@@ -129,15 +130,16 @@ +@@ -129,14 +130,15 @@ * @has_chsel_offset: SoC uses offset for selecting dai operational mode. * @reg_offset_txdata: offset of the tx fifo. * @sun4i_i2s_regmap: regmap config to use. - * @mclk_offset: Value by which mclkdiv needs to be adjusted. - * @bclk_offset: Value by which bclkdiv needs to be adjusted. - * @fmt_offset: Value by which wss and sr needs to be adjusted. * @field_clkdiv_mclk_en: regmap field to enable mclk output. + * @field_clkdiv_mclk: regmap field for mclkdiv. + * @field_clkdiv_bclk: regmap field for bclkdiv. @@ -977,9 +976,9 @@ index bc128e2..2e3fc59 100644 const struct regmap_config *sun4i_i2s_regmap; - unsigned int mclk_offset; - unsigned int bclk_offset; - unsigned int fmt_offset; /* Register fields for i2s */ + struct reg_field field_clkdiv_mclk_en; @@ -163,6 +163,7 @@ struct sun4i_i2s_quirks { struct reg_field field_fmt_bclk; struct reg_field field_fmt_lrclk; @@ -1366,28 +1365,8 @@ index bc128e2..2e3fc59 100644 default: dev_err(dai->dev, "Unsupported physical sample width: %d\n", params_physical_width(params)); -@@ -405,7 +504,18 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, - sr = 0; - wss = 0; - break; -- -+ case 20: -+ sr = 1; -+ wss = 1; -+ break; -+ case 24: -+ sr = 2; -+ wss = 2; -+ break; -+ case 32: -+ sr = 4; -+ wss = 4; -+ break; - default: - dev_err(dai->dev, "Unsupported sample width: %d\n", - params_width(params)); @@ -418,14 +528,14 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, - sr + i2s->variant->fmt_offset); + regmap_field_write(i2s->field_fmt_sr, sr); return sun4i_i2s_set_clk_rate(dai, params_rate(params), - params_width(params)); @@ -1555,9 +1534,9 @@ index bc128e2..2e3fc59 100644 .sun4i_i2s_regmap = &sun8i_i2s_regmap_config, - .mclk_offset = 1, - .bclk_offset = 2, - .fmt_offset = 3, .has_fmt_set_lrck_period = true, .has_chcfg = true, + .has_chsel_tx_chen = true, @@ -948,6 +1081,7 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19), diff --git a/projects/Allwinner/patches/linux/0002-backport-from-5.3.patch b/projects/Allwinner/patches/linux/0002-backport-from-5.3.patch deleted file mode 100644 index e7b67b0c89..0000000000 --- a/projects/Allwinner/patches/linux/0002-backport-from-5.3.patch +++ /dev/null @@ -1,3200 +0,0 @@ -From 9bd1acf0cdd4dd78a130714ad42163eac20871a3 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 18 May 2019 18:24:04 +0200 -Subject: [PATCH] media: cedrus: Allow different mod clock rates - -Some VPU variants may run at higher clock speeds. They actually need -extra speed to be capable of decoding more complex codecs like HEVC or -bigger image sizes (4K). - -Expand variant structure with mod_rate information. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/sunxi/cedrus/cedrus.c | 11 ++++++++--- - drivers/staging/media/sunxi/cedrus/cedrus.h | 1 + - drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 2 +- - drivers/staging/media/sunxi/cedrus/cedrus_hw.h | 2 -- - 4 files changed, 10 insertions(+), 6 deletions(-) - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c -index d0429c0e6b6b..9349a082a29c 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -369,36 +369,41 @@ static int cedrus_remove(struct platform_device *pdev) - } - - static const struct cedrus_variant sun4i_a10_cedrus_variant = { -- /* No particular capability. */ -+ .mod_rate = 320000000, - }; - - static const struct cedrus_variant sun5i_a13_cedrus_variant = { -- /* No particular capability. */ -+ .mod_rate = 320000000, - }; - - static const struct cedrus_variant sun7i_a20_cedrus_variant = { -- /* No particular capability. */ -+ .mod_rate = 320000000, - }; - - static const struct cedrus_variant sun8i_a33_cedrus_variant = { - .capabilities = CEDRUS_CAPABILITY_UNTILED, -+ .mod_rate = 320000000, - }; - - static const struct cedrus_variant sun8i_h3_cedrus_variant = { - .capabilities = CEDRUS_CAPABILITY_UNTILED, -+ .mod_rate = 402000000, - }; - - static const struct cedrus_variant sun50i_a64_cedrus_variant = { - .capabilities = CEDRUS_CAPABILITY_UNTILED, -+ .mod_rate = 402000000, - }; - - static const struct cedrus_variant sun50i_h5_cedrus_variant = { - .capabilities = CEDRUS_CAPABILITY_UNTILED, -+ .mod_rate = 402000000, - }; - - static const struct cedrus_variant sun50i_h6_cedrus_variant = { - .capabilities = CEDRUS_CAPABILITY_UNTILED, - .quirks = CEDRUS_QUIRK_NO_DMA_OFFSET, -+ .mod_rate = 600000000, - }; - - static const struct of_device_id cedrus_dt_match[] = { -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index c57c04b41d2e..25ee1f80f2c7 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -94,6 +94,7 @@ struct cedrus_dec_ops { - struct cedrus_variant { - unsigned int capabilities; - unsigned int quirks; -+ unsigned int mod_rate; - }; - - struct cedrus_dev { -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -index fbfff7c1c771..60406b2d4595 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -@@ -236,7 +236,7 @@ int cedrus_hw_probe(struct cedrus_dev *dev) - goto err_sram; - } - -- ret = clk_set_rate(dev->mod_clk, CEDRUS_CLOCK_RATE_DEFAULT); -+ ret = clk_set_rate(dev->mod_clk, variant->mod_rate); - if (ret) { - dev_err(dev->dev, "Failed to set clock rate\n"); - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -index b43c77d54b95..27d0882397aa 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h -@@ -16,8 +16,6 @@ - #ifndef _CEDRUS_HW_H_ - #define _CEDRUS_HW_H_ - --#define CEDRUS_CLOCK_RATE_DEFAULT 320000000 -- - int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec); - void cedrus_engine_disable(struct cedrus_dev *dev); - --- -2.21.0 - -From 79084d4e9a6783688ce497b6d17e8ecf09950bf5 Mon Sep 17 00:00:00 2001 -From: Philipp Zabel -Date: Wed, 24 Apr 2019 12:43:47 +0200 -Subject: [PATCH] media: v4l2-ctrl: add MPEG-2 profile and level controls - -Add MPEG-2 CID definitions for profiles and levels defined in ITU-T Rec. -H.262. - -Signed-off-by: Philipp Zabel -Signed-off-by: Hans Verkuil ---- - .../media/uapi/v4l/ext-ctrls-codec.rst | 56 +++++++++++++++++++ - drivers/media/v4l2-core/v4l2-ctrls.c | 23 ++++++++ - include/uapi/linux/v4l2-controls.h | 18 ++++++ - 3 files changed, 97 insertions(+) - -diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -index 4a8446203085..843c93e8e7bc 100644 ---- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -+++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -@@ -759,6 +759,32 @@ enum v4l2_mpeg_video_h264_level - - - - -+.. _v4l2-mpeg-video-mpeg2-level: -+ -+``V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL`` -+ (enum) -+ -+enum v4l2_mpeg_video_mpeg2_level - -+ The level information for the MPEG2 elementary stream. Applicable to -+ MPEG2 codecs. Possible values are: -+ -+ -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ -+ * - ``V4L2_MPEG_VIDEO_MPEG2_LEVEL_LOW`` -+ - Low Level (LL) -+ * - ``V4L2_MPEG_VIDEO_MPEG2_LEVEL_MAIN`` -+ - Main Level (ML) -+ * - ``V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH_1440`` -+ - High-1440 Level (H-14) -+ * - ``V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH`` -+ - High Level (HL) -+ -+ -+ - .. _v4l2-mpeg-video-mpeg4-level: - - ``V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL`` -@@ -845,6 +871,36 @@ enum v4l2_mpeg_video_h264_profile - - - - -+.. _v4l2-mpeg-video-mpeg2-profile: -+ -+``V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE`` -+ (enum) -+ -+enum v4l2_mpeg_video_mpeg2_profile - -+ The profile information for MPEG2. Applicable to MPEG2 codecs. -+ Possible values are: -+ -+ -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ -+ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_SIMPLE`` -+ - Simple profile (SP) -+ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_MAIN`` -+ - Main profile (MP) -+ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_SNR_SCALABLE`` -+ - SNR Scalable profile (SNR) -+ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_SPATIALLY_SCALABLE`` -+ - Spatially Scalable profile (Spt) -+ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_HIGH`` -+ - High profile (HP) -+ * - ``V4L2_MPEG_VIDEO_MPEG2_PROFILE_MULTIVIEW`` -+ - Multi-view profile (MVP) -+ -+ -+ - .. _v4l2-mpeg-video-mpeg4-profile: - - ``V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE`` -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 420e3fc237cd..3380accc24ed 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -406,6 +406,21 @@ const char * const *v4l2_ctrl_get_menu(u32 id) - "Explicit", - NULL, - }; -+ static const char * const mpeg_mpeg2_level[] = { -+ "Low", -+ "Main", -+ "High 1440", -+ "High", -+ NULL, -+ }; -+ static const char * const mpeg2_profile[] = { -+ "Simple", -+ "Main", -+ "SNR Scalable", -+ "Spatially Scalable", -+ "High", -+ NULL, -+ }; - static const char * const mpeg_mpeg4_level[] = { - "0", - "0b", -@@ -622,6 +637,10 @@ const char * const *v4l2_ctrl_get_menu(u32 id) - return h264_fp_arrangement_type; - case V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE: - return h264_fmo_map_type; -+ case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: -+ return mpeg_mpeg2_level; -+ case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: -+ return mpeg2_profile; - case V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL: - return mpeg_mpeg4_level; - case V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE: -@@ -832,6 +851,8 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: return "H264 I-Frame Maximum QP Value"; - case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: return "H264 P-Frame Minimum QP Value"; - case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: return "H264 P-Frame Maximum QP Value"; -+ case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: return "MPEG2 Level"; -+ case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: return "MPEG2 Profile"; - case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; - case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP: return "MPEG4 P-Frame QP Value"; - case V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP: return "MPEG4 B-Frame QP Value"; -@@ -1197,6 +1218,8 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC: - case V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE: - case V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE: -+ case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: -+ case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: - case V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL: - case V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE: - case V4L2_CID_JPEG_CHROMA_SUBSAMPLING: -diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h -index 37807f23231e..d9f2c76b71bb 100644 ---- a/include/uapi/linux/v4l2-controls.h -+++ b/include/uapi/linux/v4l2-controls.h -@@ -404,6 +404,24 @@ enum v4l2_mpeg_video_multi_slice_mode { - #define V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE (V4L2_CID_MPEG_BASE+228) - #define V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME (V4L2_CID_MPEG_BASE+229) - -+/* CIDs for the MPEG-2 Part 2 (H.262) codec */ -+#define V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL (V4L2_CID_MPEG_BASE+270) -+enum v4l2_mpeg_video_mpeg2_level { -+ V4L2_MPEG_VIDEO_MPEG2_LEVEL_LOW = 0, -+ V4L2_MPEG_VIDEO_MPEG2_LEVEL_MAIN = 1, -+ V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH_1440 = 2, -+ V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH = 3, -+}; -+#define V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE (V4L2_CID_MPEG_BASE+271) -+enum v4l2_mpeg_video_mpeg2_profile { -+ V4L2_MPEG_VIDEO_MPEG2_PROFILE_SIMPLE = 0, -+ V4L2_MPEG_VIDEO_MPEG2_PROFILE_MAIN = 1, -+ V4L2_MPEG_VIDEO_MPEG2_PROFILE_SNR_SCALABLE = 2, -+ V4L2_MPEG_VIDEO_MPEG2_PROFILE_SPATIALLY_SCALABLE = 3, -+ V4L2_MPEG_VIDEO_MPEG2_PROFILE_HIGH = 4, -+ V4L2_MPEG_VIDEO_MPEG2_PROFILE_MULTIVIEW = 5, -+}; -+ - /* CIDs for the FWHT codec as used by the vicodec driver. */ - #define V4L2_CID_FWHT_I_FRAME_QP (V4L2_CID_MPEG_BASE + 290) - #define V4L2_CID_FWHT_P_FRAME_QP (V4L2_CID_MPEG_BASE + 291) --- -2.21.0 - -From e5929e797865802d8124a20de14f202ec143cafd Mon Sep 17 00:00:00 2001 -From: Pawel Osciak -Date: Fri, 24 May 2019 11:20:28 +0200 -Subject: [PATCH 05/12] media: uapi: Add H264 low-level decoder API compound - controls. - -Stateless video codecs will require both the H264 metadata and slices in -order to be able to decode frames. - -This introduces the definitions for the structures used to pass the -metadata from the userspace to the kernel. - -Reviewed-by: Paul Kocialkowski -Reviewed-by: Tomasz Figa -Signed-off-by: Pawel Osciak -Signed-off-by: Guenter Roeck -Co-developed-by: Maxime Ripard -Signed-off-by: Maxime Ripard -Signed-off-by: Hans Verkuil ---- - Documentation/media/uapi/v4l/biblio.rst | 9 + - .../media/uapi/v4l/ext-ctrls-codec.rst | 569 ++++++++++++++++++ - .../media/uapi/v4l/vidioc-queryctrl.rst | 30 + - .../media/videodev2.h.rst.exceptions | 5 + - drivers/media/v4l2-core/v4l2-ctrls.c | 42 ++ - include/media/v4l2-ctrls.h | 13 +- - 6 files changed, 667 insertions(+), 1 deletion(-) - -diff --git a/Documentation/media/uapi/v4l/biblio.rst b/Documentation/media/uapi/v4l/biblio.rst -index ec33768c055e..8f4eb8823d82 100644 ---- a/Documentation/media/uapi/v4l/biblio.rst -+++ b/Documentation/media/uapi/v4l/biblio.rst -@@ -122,6 +122,15 @@ ITU BT.1119 - - :author: International Telecommunication Union (http://www.itu.ch) - -+.. _h264: -+ -+ITU-T Rec. H.264 Specification (04/2017 Edition) -+================================================ -+ -+:title: ITU-T Recommendation H.264 "Advanced Video Coding for Generic Audiovisual Services" -+ -+:author: International Telecommunication Union (http://www.itu.ch) -+ - .. _jfif: - - JFIF -diff --git a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -index 843c93e8e7bc..b0c178f0ff9b 100644 ---- a/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -+++ b/Documentation/media/uapi/v4l/ext-ctrls-codec.rst -@@ -1451,6 +1451,575 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type - - - Layer number - - -+.. _v4l2-mpeg-h264: -+ -+``V4L2_CID_MPEG_VIDEO_H264_SPS (struct)`` -+ Specifies the sequence parameter set (as extracted from the -+ bitstream) for the associated H264 slice data. This includes the -+ necessary parameters for configuring a stateless hardware decoding -+ pipeline for H264. The bitstream parameters are defined according -+ to :ref:`h264`, section 7.4.2.1.1 "Sequence Parameter Set Data -+ Semantics". For further documentation, refer to the above -+ specification, unless there is an explicit comment stating -+ otherwise. -+ -+ .. note:: -+ -+ This compound control is not yet part of the public kernel API and -+ it is expected to change. -+ -+.. c:type:: v4l2_ctrl_h264_sps -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_h264_sps -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``profile_idc`` -+ - -+ * - __u8 -+ - ``constraint_set_flags`` -+ - See :ref:`Sequence Parameter Set Constraints Set Flags ` -+ * - __u8 -+ - ``level_idc`` -+ - -+ * - __u8 -+ - ``seq_parameter_set_id`` -+ - -+ * - __u8 -+ - ``chroma_format_idc`` -+ - -+ * - __u8 -+ - ``bit_depth_luma_minus8`` -+ - -+ * - __u8 -+ - ``bit_depth_chroma_minus8`` -+ - -+ * - __u8 -+ - ``log2_max_frame_num_minus4`` -+ - -+ * - __u8 -+ - ``pic_order_cnt_type`` -+ - -+ * - __u8 -+ - ``log2_max_pic_order_cnt_lsb_minus4`` -+ - -+ * - __u8 -+ - ``max_num_ref_frames`` -+ - -+ * - __u8 -+ - ``num_ref_frames_in_pic_order_cnt_cycle`` -+ - -+ * - __s32 -+ - ``offset_for_ref_frame[255]`` -+ - -+ * - __s32 -+ - ``offset_for_non_ref_pic`` -+ - -+ * - __s32 -+ - ``offset_for_top_to_bottom_field`` -+ - -+ * - __u16 -+ - ``pic_width_in_mbs_minus1`` -+ - -+ * - __u16 -+ - ``pic_height_in_map_units_minus1`` -+ - -+ * - __u32 -+ - ``flags`` -+ - See :ref:`Sequence Parameter Set Flags ` -+ -+.. _h264_sps_constraints_set_flags: -+ -+``Sequence Parameter Set Constraints Set Flags`` -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_H264_SPS_CONSTRAINT_SET0_FLAG`` -+ - 0x00000001 -+ - -+ * - ``V4L2_H264_SPS_CONSTRAINT_SET1_FLAG`` -+ - 0x00000002 -+ - -+ * - ``V4L2_H264_SPS_CONSTRAINT_SET2_FLAG`` -+ - 0x00000004 -+ - -+ * - ``V4L2_H264_SPS_CONSTRAINT_SET3_FLAG`` -+ - 0x00000008 -+ - -+ * - ``V4L2_H264_SPS_CONSTRAINT_SET4_FLAG`` -+ - 0x00000010 -+ - -+ * - ``V4L2_H264_SPS_CONSTRAINT_SET5_FLAG`` -+ - 0x00000020 -+ - -+ -+.. _h264_sps_flags: -+ -+``Sequence Parameter Set Flags`` -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE`` -+ - 0x00000001 -+ - -+ * - ``V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS`` -+ - 0x00000002 -+ - -+ * - ``V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO`` -+ - 0x00000004 -+ - -+ * - ``V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED`` -+ - 0x00000008 -+ - -+ * - ``V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY`` -+ - 0x00000010 -+ - -+ * - ``V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD`` -+ - 0x00000020 -+ - -+ * - ``V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE`` -+ - 0x00000040 -+ - -+ -+``V4L2_CID_MPEG_VIDEO_H264_PPS (struct)`` -+ Specifies the picture parameter set (as extracted from the -+ bitstream) for the associated H264 slice data. This includes the -+ necessary parameters for configuring a stateless hardware decoding -+ pipeline for H264. The bitstream parameters are defined according -+ to :ref:`h264`, section 7.4.2.2 "Picture Parameter Set RBSP -+ Semantics". For further documentation, refer to the above -+ specification, unless there is an explicit comment stating -+ otherwise. -+ -+ .. note:: -+ -+ This compound control is not yet part of the public kernel API and -+ it is expected to change. -+ -+.. c:type:: v4l2_ctrl_h264_pps -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_h264_pps -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``pic_parameter_set_id`` -+ - -+ * - __u8 -+ - ``seq_parameter_set_id`` -+ - -+ * - __u8 -+ - ``num_slice_groups_minus1`` -+ - -+ * - __u8 -+ - ``num_ref_idx_l0_default_active_minus1`` -+ - -+ * - __u8 -+ - ``num_ref_idx_l1_default_active_minus1`` -+ - -+ * - __u8 -+ - ``weighted_bipred_idc`` -+ - -+ * - __s8 -+ - ``pic_init_qp_minus26`` -+ - -+ * - __s8 -+ - ``pic_init_qs_minus26`` -+ - -+ * - __s8 -+ - ``chroma_qp_index_offset`` -+ - -+ * - __s8 -+ - ``second_chroma_qp_index_offset`` -+ - -+ * - __u16 -+ - ``flags`` -+ - See :ref:`Picture Parameter Set Flags ` -+ -+.. _h264_pps_flags: -+ -+``Picture Parameter Set Flags`` -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE`` -+ - 0x00000001 -+ - -+ * - ``V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT`` -+ - 0x00000002 -+ - -+ * - ``V4L2_H264_PPS_FLAG_WEIGHTED_PRED`` -+ - 0x00000004 -+ - -+ * - ``V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT`` -+ - 0x00000008 -+ - -+ * - ``V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED`` -+ - 0x00000010 -+ - -+ * - ``V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT`` -+ - 0x00000020 -+ - -+ * - ``V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE`` -+ - 0x00000040 -+ - -+ * - ``V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT`` -+ - 0x00000080 -+ - -+ -+``V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (struct)`` -+ Specifies the scaling matrix (as extracted from the bitstream) for -+ the associated H264 slice data. The bitstream parameters are -+ defined according to :ref:`h264`, section 7.4.2.1.1.1 "Scaling -+ List Semantics".For further documentation, refer to the above -+ specification, unless there is an explicit comment stating -+ otherwise. -+ -+ .. note:: -+ -+ This compound control is not yet part of the public kernel API and -+ it is expected to change. -+ -+.. c:type:: v4l2_ctrl_h264_scaling_matrix -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_h264_scaling_matrix -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``scaling_list_4x4[6][16]`` -+ - -+ * - __u8 -+ - ``scaling_list_8x8[6][64]`` -+ - -+ -+``V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS (struct)`` -+ Specifies the slice parameters (as extracted from the bitstream) -+ for the associated H264 slice data. This includes the necessary -+ parameters for configuring a stateless hardware decoding pipeline -+ for H264. The bitstream parameters are defined according to -+ :ref:`h264`, section 7.4.3 "Slice Header Semantics". For further -+ documentation, refer to the above specification, unless there is -+ an explicit comment stating otherwise. -+ -+ .. note:: -+ -+ This compound control is not yet part of the public kernel API -+ and it is expected to change. -+ -+ This structure is expected to be passed as an array, with one -+ entry for each slice included in the bitstream buffer. -+ -+.. c:type:: v4l2_ctrl_h264_slice_params -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_h264_slice_params -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u32 -+ - ``size`` -+ - -+ * - __u32 -+ - ``header_bit_size`` -+ - -+ * - __u16 -+ - ``first_mb_in_slice`` -+ - -+ * - __u8 -+ - ``slice_type`` -+ - -+ * - __u8 -+ - ``pic_parameter_set_id`` -+ - -+ * - __u8 -+ - ``colour_plane_id`` -+ - -+ * - __u8 -+ - ``redundant_pic_cnt`` -+ - -+ * - __u16 -+ - ``frame_num`` -+ - -+ * - __u16 -+ - ``idr_pic_id`` -+ - -+ * - __u16 -+ - ``pic_order_cnt_lsb`` -+ - -+ * - __s32 -+ - ``delta_pic_order_cnt_bottom`` -+ - -+ * - __s32 -+ - ``delta_pic_order_cnt0`` -+ - -+ * - __s32 -+ - ``delta_pic_order_cnt1`` -+ - -+ * - struct :c:type:`v4l2_h264_pred_weight_table` -+ - ``pred_weight_table`` -+ - -+ * - __u32 -+ - ``dec_ref_pic_marking_bit_size`` -+ - -+ * - __u32 -+ - ``pic_order_cnt_bit_size`` -+ - -+ * - __u8 -+ - ``cabac_init_idc`` -+ - -+ * - __s8 -+ - ``slice_qp_delta`` -+ - -+ * - __s8 -+ - ``slice_qs_delta`` -+ - -+ * - __u8 -+ - ``disable_deblocking_filter_idc`` -+ - -+ * - __s8 -+ - ``slice_alpha_c0_offset_div2`` -+ - -+ * - __s8 -+ - ``slice_beta_offset_div2`` -+ - -+ * - __u8 -+ - ``num_ref_idx_l0_active_minus1`` -+ - -+ * - __u8 -+ - ``num_ref_idx_l1_active_minus1`` -+ - -+ * - __u32 -+ - ``slice_group_change_cycle`` -+ - -+ * - __u8 -+ - ``ref_pic_list0[32]`` -+ - Reference picture list after applying the per-slice modifications -+ * - __u8 -+ - ``ref_pic_list1[32]`` -+ - Reference picture list after applying the per-slice modifications -+ * - __u32 -+ - ``flags`` -+ - See :ref:`Slice Parameter Flags ` -+ -+.. _h264_slice_flags: -+ -+``Slice Parameter Set Flags`` -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_H264_SLICE_FLAG_FIELD_PIC`` -+ - 0x00000001 -+ - -+ * - ``V4L2_H264_SLICE_FLAG_BOTTOM_FIELD`` -+ - 0x00000002 -+ - -+ * - ``V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED`` -+ - 0x00000004 -+ - -+ * - ``V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH`` -+ - 0x00000008 -+ - -+ -+``Prediction Weight Table`` -+ -+ The bitstream parameters are defined according to :ref:`h264`, -+ section 7.4.3.2 "Prediction Weight Table Semantics". For further -+ documentation, refer to the above specification, unless there is -+ an explicit comment stating otherwise. -+ -+.. c:type:: v4l2_h264_pred_weight_table -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_h264_pred_weight_table -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u16 -+ - ``luma_log2_weight_denom`` -+ - -+ * - __u16 -+ - ``chroma_log2_weight_denom`` -+ - -+ * - struct :c:type:`v4l2_h264_weight_factors` -+ - ``weight_factors[2]`` -+ - The weight factors at index 0 are the weight factors for the reference -+ list 0, the one at index 1 for the reference list 1. -+ -+.. c:type:: v4l2_h264_weight_factors -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_h264_weight_factors -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __s16 -+ - ``luma_weight[32]`` -+ - -+ * - __s16 -+ - ``luma_offset[32]`` -+ - -+ * - __s16 -+ - ``chroma_weight[32][2]`` -+ - -+ * - __s16 -+ - ``chroma_offset[32][2]`` -+ - -+ -+``V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS (struct)`` -+ Specifies the decode parameters (as extracted from the bitstream) -+ for the associated H264 slice data. This includes the necessary -+ parameters for configuring a stateless hardware decoding pipeline -+ for H264. The bitstream parameters are defined according to -+ :ref:`h264`. For further documentation, refer to the above -+ specification, unless there is an explicit comment stating -+ otherwise. -+ -+ .. note:: -+ -+ This compound control is not yet part of the public kernel API and -+ it is expected to change. -+ -+.. c:type:: v4l2_ctrl_h264_decode_params -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_h264_decode_params -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u32 -+ - ``num_slices`` -+ - Number of slices needed to decode the current frame -+ * - __u32 -+ - ``nal_ref_idc`` -+ - NAL reference ID value coming from the NAL Unit header -+ * - __u8 -+ - ``ref_pic_list_p0[32]`` -+ - Backward reference list used by P-frames in the original bitstream order -+ * - __u8 -+ - ``ref_pic_list_b0[32]`` -+ - Backward reference list used by B-frames in the original bitstream order -+ * - __u8 -+ - ``ref_pic_list_b1[32]`` -+ - Forward reference list used by B-frames in the original bitstream order -+ * - __s32 -+ - ``top_field_order_cnt`` -+ - Picture Order Count for the coded top field -+ * - __s32 -+ - ``bottom_field_order_cnt`` -+ - Picture Order Count for the coded bottom field -+ * - __u32 -+ - ``flags`` -+ - See :ref:`Decode Parameters Flags ` -+ * - struct :c:type:`v4l2_h264_dpb_entry` -+ - ``dpb[16]`` -+ - -+ -+.. _h264_decode_params_flags: -+ -+``Decode Parameters Flags`` -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC`` -+ - 0x00000001 -+ - That picture is an IDR picture -+ -+.. c:type:: v4l2_h264_dpb_entry -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_h264_dpb_entry -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u64 -+ - ``reference_ts`` -+ - Timestamp of the V4L2 capture buffer to use as reference, used -+ with B-coded and P-coded frames. The timestamp refers to the -+ ``timestamp`` field in struct :c:type:`v4l2_buffer`. Use the -+ :c:func:`v4l2_timeval_to_ns()` function to convert the struct -+ :c:type:`timeval` in struct :c:type:`v4l2_buffer` to a __u64. -+ * - __u16 -+ - ``frame_num`` -+ - -+ * - __u16 -+ - ``pic_num`` -+ - -+ * - __s32 -+ - ``top_field_order_cnt`` -+ - -+ * - __s32 -+ - ``bottom_field_order_cnt`` -+ - -+ * - __u32 -+ - ``flags`` -+ - See :ref:`DPB Entry Flags ` -+ -+.. _h264_dpb_flags: -+ -+``DPB Entries Flags`` -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_H264_DPB_ENTRY_FLAG_VALID`` -+ - 0x00000001 -+ - The DPB entry is valid and should be considered -+ * - ``V4L2_H264_DPB_ENTRY_FLAG_ACTIVE`` -+ - 0x00000002 -+ - The DPB entry is currently being used as a reference frame -+ * - ``V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM`` -+ - 0x00000004 -+ - The DPB entry is a long term reference frame - - .. _v4l2-mpeg-mpeg2: - -diff --git a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -index f824162d0ea9..dc500632095d 100644 ---- a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -+++ b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst -@@ -443,6 +443,36 @@ See also the examples in :ref:`control`. - - n/a - - A struct :c:type:`v4l2_ctrl_mpeg2_quantization`, containing MPEG-2 - quantization matrices for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_H264_SPS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_h264_sps`, containing H264 -+ sequence parameters for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_H264_PPS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_h264_pps`, containing H264 -+ picture parameters for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_H264_SCALING_MATRIX`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_h264_scaling_matrix`, containing H264 -+ scaling matrices for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_H264_SLICE_PARAMS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_h264_slice_params`, containing H264 -+ slice parameters for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_H264_DECODE_PARAMS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_h264_decode_params`, containing H264 -+ decode parameters for stateless video decoders. - - .. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.7cm}| - -diff --git a/Documentation/media/videodev2.h.rst.exceptions b/Documentation/media/videodev2.h.rst.exceptions -index 64d348e67df9..55cbe324b9fc 100644 ---- a/Documentation/media/videodev2.h.rst.exceptions -+++ b/Documentation/media/videodev2.h.rst.exceptions -@@ -136,6 +136,11 @@ replace symbol V4L2_CTRL_TYPE_U32 :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_U8 :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_MPEG2_SLICE_PARAMS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_MPEG2_QUANTIZATION :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_H264_SPS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_H264_PPS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_H264_SCALING_MATRIX :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_H264_SLICE_PARAMS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_H264_DECODE_PARAMS :c:type:`v4l2_ctrl_type` - - # V4L2 capability defines - replace define V4L2_CAP_VIDEO_CAPTURE device-capabilities -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 3380accc24ed..b72dc54ba638 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -851,6 +851,11 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: return "H264 I-Frame Maximum QP Value"; - case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: return "H264 P-Frame Minimum QP Value"; - case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: return "H264 P-Frame Maximum QP Value"; -+ case V4L2_CID_MPEG_VIDEO_H264_SPS: return "H264 Sequence Parameter Set"; -+ case V4L2_CID_MPEG_VIDEO_H264_PPS: return "H264 Picture Parameter Set"; -+ case V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX: return "H264 Scaling Matrix"; -+ case V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS: return "H264 Slice Parameters"; -+ case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: return "H264 Decode Parameters"; - case V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL: return "MPEG2 Level"; - case V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE: return "MPEG2 Profile"; - case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; -@@ -1337,6 +1342,21 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_FWHT_PARAMS: - *type = V4L2_CTRL_TYPE_FWHT_PARAMS; - break; -+ case V4L2_CID_MPEG_VIDEO_H264_SPS: -+ *type = V4L2_CTRL_TYPE_H264_SPS; -+ break; -+ case V4L2_CID_MPEG_VIDEO_H264_PPS: -+ *type = V4L2_CTRL_TYPE_H264_PPS; -+ break; -+ case V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX: -+ *type = V4L2_CTRL_TYPE_H264_SCALING_MATRIX; -+ break; -+ case V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS: -+ *type = V4L2_CTRL_TYPE_H264_SLICE_PARAMS; -+ break; -+ case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: -+ *type = V4L2_CTRL_TYPE_H264_DECODE_PARAMS; -+ break; - default: - *type = V4L2_CTRL_TYPE_INTEGER; - break; -@@ -1706,6 +1726,13 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, - case V4L2_CTRL_TYPE_FWHT_PARAMS: - return 0; - -+ case V4L2_CTRL_TYPE_H264_SPS: -+ case V4L2_CTRL_TYPE_H264_PPS: -+ case V4L2_CTRL_TYPE_H264_SCALING_MATRIX: -+ case V4L2_CTRL_TYPE_H264_SLICE_PARAMS: -+ case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: -+ return 0; -+ - default: - return -EINVAL; - } -@@ -2289,6 +2316,21 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, - case V4L2_CTRL_TYPE_FWHT_PARAMS: - elem_size = sizeof(struct v4l2_ctrl_fwht_params); - break; -+ case V4L2_CTRL_TYPE_H264_SPS: -+ elem_size = sizeof(struct v4l2_ctrl_h264_sps); -+ break; -+ case V4L2_CTRL_TYPE_H264_PPS: -+ elem_size = sizeof(struct v4l2_ctrl_h264_pps); -+ break; -+ case V4L2_CTRL_TYPE_H264_SCALING_MATRIX: -+ elem_size = sizeof(struct v4l2_ctrl_h264_scaling_matrix); -+ break; -+ case V4L2_CTRL_TYPE_H264_SLICE_PARAMS: -+ elem_size = sizeof(struct v4l2_ctrl_h264_slice_params); -+ break; -+ case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: -+ elem_size = sizeof(struct v4l2_ctrl_h264_decode_params); -+ break; - default: - if (type < V4L2_CTRL_COMPOUND_TYPES) - elem_size = sizeof(s32); -diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h -index ee026387f513..a8aede26491e 100644 ---- a/include/media/v4l2-ctrls.h -+++ b/include/media/v4l2-ctrls.h -@@ -23,11 +23,12 @@ - #include - - /* -- * Include the mpeg2 and fwht stateless codec compound control definitions. -+ * Include the stateless codec compound control definitions. - * This will move to the public headers once this API is fully stable. - */ - #include - #include -+#include - - /* forward references */ - struct file; -@@ -51,6 +52,11 @@ struct poll_table_struct; - * @p_mpeg2_slice_params: Pointer to a MPEG2 slice parameters structure. - * @p_mpeg2_quantization: Pointer to a MPEG2 quantization data structure. - * @p_fwht_params: Pointer to a FWHT stateless parameters structure. -+ * @p_h264_sps: Pointer to a struct v4l2_ctrl_h264_sps. -+ * @p_h264_pps: Pointer to a struct v4l2_ctrl_h264_pps. -+ * @p_h264_scaling_matrix: Pointer to a struct v4l2_ctrl_h264_scaling_matrix. -+ * @p_h264_slice_params: Pointer to a struct v4l2_ctrl_h264_slice_params. -+ * @p_h264_decode_params: Pointer to a struct v4l2_ctrl_h264_decode_params. - * @p: Pointer to a compound value. - */ - union v4l2_ctrl_ptr { -@@ -63,6 +69,11 @@ union v4l2_ctrl_ptr { - struct v4l2_ctrl_mpeg2_slice_params *p_mpeg2_slice_params; - struct v4l2_ctrl_mpeg2_quantization *p_mpeg2_quantization; - struct v4l2_ctrl_fwht_params *p_fwht_params; -+ struct v4l2_ctrl_h264_sps *p_h264_sps; -+ struct v4l2_ctrl_h264_pps *p_h264_pps; -+ struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix; -+ struct v4l2_ctrl_h264_slice_params *p_h264_slice_params; -+ struct v4l2_ctrl_h264_decode_params *p_h264_decode_params; - void *p; - }; - --- -2.21.0 - -From 973e931fe8eefc32616f8eadadd0a018cbd096b5 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Fri, 24 May 2019 11:20:29 +0200 -Subject: [PATCH 06/12] media: pixfmt: Add H264 Slice format - -The H264_SLICE_RAW format is meant to hold the parsed slice data without -the start code. This will be needed by stateless decoders. - -Signed-off-by: Maxime Ripard -Signed-off-by: Hans Verkuil ---- - drivers/media/v4l2-core/v4l2-ioctl.c | 1 + - include/media/h264-ctrls.h | 197 +++++++++++++++++++++++++++ - 2 files changed, 198 insertions(+) - create mode 100644 include/media/h264-ctrls.h - -diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index ac87c3e37280..f6e1254064d2 100644 ---- a/drivers/media/v4l2-core/v4l2-ioctl.c -+++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1325,6 +1325,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) - case V4L2_PIX_FMT_H264: descr = "H.264"; break; - case V4L2_PIX_FMT_H264_NO_SC: descr = "H.264 (No Start Codes)"; break; - case V4L2_PIX_FMT_H264_MVC: descr = "H.264 MVC"; break; -+ case V4L2_PIX_FMT_H264_SLICE_RAW: descr = "H.264 Parsed Slice Data"; break; - case V4L2_PIX_FMT_H263: descr = "H.263"; break; - case V4L2_PIX_FMT_MPEG1: descr = "MPEG-1 ES"; break; - case V4L2_PIX_FMT_MPEG2: descr = "MPEG-2 ES"; break; -diff --git a/include/media/h264-ctrls.h b/include/media/h264-ctrls.h -new file mode 100644 -index 000000000000..e1404d78d6ff ---- /dev/null -+++ b/include/media/h264-ctrls.h -@@ -0,0 +1,197 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * These are the H.264 state controls for use with stateless H.264 -+ * codec drivers. -+ * -+ * It turns out that these structs are not stable yet and will undergo -+ * more changes. So keep them private until they are stable and ready to -+ * become part of the official public API. -+ */ -+ -+#ifndef _H264_CTRLS_H_ -+#define _H264_CTRLS_H_ -+ -+#include -+ -+/* Our pixel format isn't stable at the moment */ -+#define V4L2_PIX_FMT_H264_SLICE_RAW v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */ -+ -+/* -+ * This is put insanely high to avoid conflicting with controls that -+ * would be added during the phase where those controls are not -+ * stable. It should be fixed eventually. -+ */ -+#define V4L2_CID_MPEG_VIDEO_H264_SPS (V4L2_CID_MPEG_BASE+1000) -+#define V4L2_CID_MPEG_VIDEO_H264_PPS (V4L2_CID_MPEG_BASE+1001) -+#define V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (V4L2_CID_MPEG_BASE+1002) -+#define V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS (V4L2_CID_MPEG_BASE+1003) -+#define V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS (V4L2_CID_MPEG_BASE+1004) -+ -+/* enum v4l2_ctrl_type type values */ -+#define V4L2_CTRL_TYPE_H264_SPS 0x0110 -+#define V4L2_CTRL_TYPE_H264_PPS 0x0111 -+#define V4L2_CTRL_TYPE_H264_SCALING_MATRIX 0x0112 -+#define V4L2_CTRL_TYPE_H264_SLICE_PARAMS 0x0113 -+#define V4L2_CTRL_TYPE_H264_DECODE_PARAMS 0x0114 -+ -+#define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG 0x01 -+#define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG 0x02 -+#define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG 0x04 -+#define V4L2_H264_SPS_CONSTRAINT_SET3_FLAG 0x08 -+#define V4L2_H264_SPS_CONSTRAINT_SET4_FLAG 0x10 -+#define V4L2_H264_SPS_CONSTRAINT_SET5_FLAG 0x20 -+ -+#define V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE 0x01 -+#define V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS 0x02 -+#define V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO 0x04 -+#define V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED 0x08 -+#define V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY 0x10 -+#define V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD 0x20 -+#define V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE 0x40 -+ -+struct v4l2_ctrl_h264_sps { -+ __u8 profile_idc; -+ __u8 constraint_set_flags; -+ __u8 level_idc; -+ __u8 seq_parameter_set_id; -+ __u8 chroma_format_idc; -+ __u8 bit_depth_luma_minus8; -+ __u8 bit_depth_chroma_minus8; -+ __u8 log2_max_frame_num_minus4; -+ __u8 pic_order_cnt_type; -+ __u8 log2_max_pic_order_cnt_lsb_minus4; -+ __u8 max_num_ref_frames; -+ __u8 num_ref_frames_in_pic_order_cnt_cycle; -+ __s32 offset_for_ref_frame[255]; -+ __s32 offset_for_non_ref_pic; -+ __s32 offset_for_top_to_bottom_field; -+ __u16 pic_width_in_mbs_minus1; -+ __u16 pic_height_in_map_units_minus1; -+ __u32 flags; -+}; -+ -+#define V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE 0x0001 -+#define V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT 0x0002 -+#define V4L2_H264_PPS_FLAG_WEIGHTED_PRED 0x0004 -+#define V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT 0x0008 -+#define V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED 0x0010 -+#define V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT 0x0020 -+#define V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE 0x0040 -+#define V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT 0x0080 -+ -+struct v4l2_ctrl_h264_pps { -+ __u8 pic_parameter_set_id; -+ __u8 seq_parameter_set_id; -+ __u8 num_slice_groups_minus1; -+ __u8 num_ref_idx_l0_default_active_minus1; -+ __u8 num_ref_idx_l1_default_active_minus1; -+ __u8 weighted_bipred_idc; -+ __s8 pic_init_qp_minus26; -+ __s8 pic_init_qs_minus26; -+ __s8 chroma_qp_index_offset; -+ __s8 second_chroma_qp_index_offset; -+ __u16 flags; -+}; -+ -+struct v4l2_ctrl_h264_scaling_matrix { -+ __u8 scaling_list_4x4[6][16]; -+ __u8 scaling_list_8x8[6][64]; -+}; -+ -+struct v4l2_h264_weight_factors { -+ __s16 luma_weight[32]; -+ __s16 luma_offset[32]; -+ __s16 chroma_weight[32][2]; -+ __s16 chroma_offset[32][2]; -+}; -+ -+struct v4l2_h264_pred_weight_table { -+ __u16 luma_log2_weight_denom; -+ __u16 chroma_log2_weight_denom; -+ struct v4l2_h264_weight_factors weight_factors[2]; -+}; -+ -+#define V4L2_H264_SLICE_TYPE_P 0 -+#define V4L2_H264_SLICE_TYPE_B 1 -+#define V4L2_H264_SLICE_TYPE_I 2 -+#define V4L2_H264_SLICE_TYPE_SP 3 -+#define V4L2_H264_SLICE_TYPE_SI 4 -+ -+#define V4L2_H264_SLICE_FLAG_FIELD_PIC 0x01 -+#define V4L2_H264_SLICE_FLAG_BOTTOM_FIELD 0x02 -+#define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x04 -+#define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH 0x08 -+ -+struct v4l2_ctrl_h264_slice_params { -+ /* Size in bytes, including header */ -+ __u32 size; -+ /* Offset in bits to slice_data() from the beginning of this slice. */ -+ __u32 header_bit_size; -+ -+ __u16 first_mb_in_slice; -+ __u8 slice_type; -+ __u8 pic_parameter_set_id; -+ __u8 colour_plane_id; -+ __u8 redundant_pic_cnt; -+ __u16 frame_num; -+ __u16 idr_pic_id; -+ __u16 pic_order_cnt_lsb; -+ __s32 delta_pic_order_cnt_bottom; -+ __s32 delta_pic_order_cnt0; -+ __s32 delta_pic_order_cnt1; -+ -+ struct v4l2_h264_pred_weight_table pred_weight_table; -+ /* Size in bits of dec_ref_pic_marking() syntax element. */ -+ __u32 dec_ref_pic_marking_bit_size; -+ /* Size in bits of pic order count syntax. */ -+ __u32 pic_order_cnt_bit_size; -+ -+ __u8 cabac_init_idc; -+ __s8 slice_qp_delta; -+ __s8 slice_qs_delta; -+ __u8 disable_deblocking_filter_idc; -+ __s8 slice_alpha_c0_offset_div2; -+ __s8 slice_beta_offset_div2; -+ __u8 num_ref_idx_l0_active_minus1; -+ __u8 num_ref_idx_l1_active_minus1; -+ __u32 slice_group_change_cycle; -+ -+ /* -+ * Entries on each list are indices into -+ * v4l2_ctrl_h264_decode_params.dpb[]. -+ */ -+ __u8 ref_pic_list0[32]; -+ __u8 ref_pic_list1[32]; -+ -+ __u32 flags; -+}; -+ -+#define V4L2_H264_DPB_ENTRY_FLAG_VALID 0x01 -+#define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x02 -+#define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x04 -+ -+struct v4l2_h264_dpb_entry { -+ __u64 reference_ts; -+ __u16 frame_num; -+ __u16 pic_num; -+ /* Note that field is indicated by v4l2_buffer.field */ -+ __s32 top_field_order_cnt; -+ __s32 bottom_field_order_cnt; -+ __u32 flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */ -+}; -+ -+#define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC 0x01 -+ -+struct v4l2_ctrl_h264_decode_params { -+ struct v4l2_h264_dpb_entry dpb[16]; -+ __u16 num_slices; -+ __u16 nal_ref_idc; -+ __u8 ref_pic_list_p0[32]; -+ __u8 ref_pic_list_b0[32]; -+ __u8 ref_pic_list_b1[32]; -+ __s32 top_field_order_cnt; -+ __s32 bottom_field_order_cnt; -+ __u32 flags; /* V4L2_H264_DECODE_PARAM_FLAG_* */ -+}; -+ -+#endif --- -2.21.0 - -From 129c7799b038de2a4fa90e6cff2bbb843187b06f Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Fri, 24 May 2019 11:20:30 +0200 -Subject: [PATCH 07/12] media: pixfmt: Add H264_SLICE_RAW format documentation - -The H264_SLICE_RAW format introduced before is meant for stateless -decoders that will need the H264 parsed slice data without the start code. - -Let's document it. - -Signed-off-by: Maxime Ripard -Signed-off-by: Hans Verkuil ---- - .../media/uapi/v4l/pixfmt-compressed.rst | 25 +++++++++++++++++++ - 1 file changed, 25 insertions(+) - -diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -index 6c961cfb74da..4b701fc7653e 100644 ---- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst -+++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst -@@ -52,6 +52,31 @@ Compressed Formats - - ``V4L2_PIX_FMT_H264_MVC`` - - 'M264' - - H264 MVC video elementary stream. -+ * .. _V4L2-PIX-FMT-H264-SLICE-RAW: -+ -+ - ``V4L2_PIX_FMT_H264_SLICE_RAW`` -+ - 'S264' -+ - H264 parsed slice data, without the start code and as -+ extracted from the H264 bitstream. This format is adapted for -+ stateless video decoders that implement an H264 pipeline -+ (using the :ref:`mem2mem` and :ref:`media-request-api`). -+ Metadata associated with the frame to decode are required to -+ be passed through the ``V4L2_CID_MPEG_VIDEO_H264_SPS``, -+ ``V4L2_CID_MPEG_VIDEO_H264_PPS``, -+ ``V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX``, -+ ``V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS`` and -+ ``V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS`` controls. See the -+ :ref:`associated Codec Control IDs `. Exactly -+ one output and one capture buffer must be provided for use -+ with this pixel format. The output buffer must contain the -+ appropriate number of macroblocks to decode a full -+ corresponding frame to the matching capture buffer. -+ -+ .. note:: -+ -+ This format is not yet part of the public kernel API and it -+ is expected to change. -+ - * .. _V4L2-PIX-FMT-H263: - - - ``V4L2_PIX_FMT_H263`` --- -2.21.0 - -From 83b448edec51503daf61a823643a50db5e68cb15 Mon Sep 17 00:00:00 2001 -From: Maxime Ripard -Date: Fri, 24 May 2019 11:20:31 +0200 -Subject: [PATCH 08/12] media: cedrus: Add H264 decoding support - -Introduce some basic H264 decoding support in cedrus. So far, only the -baseline profile videos have been tested, and some more advanced features -used in higher profiles are not even implemented. - -Reviewed-by: Jernej Skrabec -Reviewed-by: Paul Kocialkowski -Signed-off-by: Maxime Ripard -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/sunxi/cedrus/Makefile | 3 +- - drivers/staging/media/sunxi/cedrus/cedrus.c | 31 + - drivers/staging/media/sunxi/cedrus/cedrus.h | 38 +- - .../staging/media/sunxi/cedrus/cedrus_dec.c | 13 + - .../staging/media/sunxi/cedrus/cedrus_h264.c | 576 ++++++++++++++++++ - .../staging/media/sunxi/cedrus/cedrus_hw.c | 4 + - .../staging/media/sunxi/cedrus/cedrus_regs.h | 91 +++ - .../staging/media/sunxi/cedrus/cedrus_video.c | 9 + - 8 files changed, 763 insertions(+), 2 deletions(-) - create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_h264.c - -diff --git a/drivers/staging/media/sunxi/cedrus/Makefile b/drivers/staging/media/sunxi/cedrus/Makefile -index 808842f0119e..c85ac6db0302 100644 ---- a/drivers/staging/media/sunxi/cedrus/Makefile -+++ b/drivers/staging/media/sunxi/cedrus/Makefile -@@ -1,4 +1,5 @@ - # SPDX-License-Identifier: GPL-2.0 - obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += sunxi-cedrus.o - --sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o cedrus_mpeg2.o -+sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o \ -+ cedrus_mpeg2.o cedrus_h264.o -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c -index 9349a082a29c..370937edfc14 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c -@@ -40,6 +40,36 @@ static const struct cedrus_control cedrus_controls[] = { - .codec = CEDRUS_CODEC_MPEG2, - .required = false, - }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS, -+ .elem_size = sizeof(struct v4l2_ctrl_h264_decode_params), -+ .codec = CEDRUS_CODEC_H264, -+ .required = true, -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS, -+ .elem_size = sizeof(struct v4l2_ctrl_h264_slice_params), -+ .codec = CEDRUS_CODEC_H264, -+ .required = true, -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SPS, -+ .elem_size = sizeof(struct v4l2_ctrl_h264_sps), -+ .codec = CEDRUS_CODEC_H264, -+ .required = true, -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_PPS, -+ .elem_size = sizeof(struct v4l2_ctrl_h264_pps), -+ .codec = CEDRUS_CODEC_H264, -+ .required = true, -+ }, -+ { -+ .id = V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX, -+ .elem_size = sizeof(struct v4l2_ctrl_h264_scaling_matrix), -+ .codec = CEDRUS_CODEC_H264, -+ .required = true, -+ }, - }; - - #define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls) -@@ -278,6 +308,7 @@ static int cedrus_probe(struct platform_device *pdev) - } - - dev->dec_ops[CEDRUS_CODEC_MPEG2] = &cedrus_dec_ops_mpeg2; -+ dev->dec_ops[CEDRUS_CODEC_H264] = &cedrus_dec_ops_h264; - - mutex_init(&dev->dev_mutex); - -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h -index 25ee1f80f2c7..3f476d0fd981 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h -@@ -32,7 +32,7 @@ - - enum cedrus_codec { - CEDRUS_CODEC_MPEG2, -- -+ CEDRUS_CODEC_H264, - CEDRUS_CODEC_LAST, - }; - -@@ -42,6 +42,12 @@ enum cedrus_irq_status { - CEDRUS_IRQ_OK, - }; - -+enum cedrus_h264_pic_type { -+ CEDRUS_H264_PIC_TYPE_FRAME = 0, -+ CEDRUS_H264_PIC_TYPE_FIELD, -+ CEDRUS_H264_PIC_TYPE_MBAFF, -+}; -+ - struct cedrus_control { - u32 id; - u32 elem_size; -@@ -49,6 +55,14 @@ struct cedrus_control { - unsigned char required:1; - }; - -+struct cedrus_h264_run { -+ const struct v4l2_ctrl_h264_decode_params *decode_params; -+ const struct v4l2_ctrl_h264_pps *pps; -+ const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; -+ const struct v4l2_ctrl_h264_slice_params *slice_params; -+ const struct v4l2_ctrl_h264_sps *sps; -+}; -+ - struct cedrus_mpeg2_run { - const struct v4l2_ctrl_mpeg2_slice_params *slice_params; - const struct v4l2_ctrl_mpeg2_quantization *quantization; -@@ -59,12 +73,20 @@ struct cedrus_run { - struct vb2_v4l2_buffer *dst; - - union { -+ struct cedrus_h264_run h264; - struct cedrus_mpeg2_run mpeg2; - }; - }; - - struct cedrus_buffer { - struct v4l2_m2m_buffer m2m_buf; -+ -+ union { -+ struct { -+ unsigned int position; -+ enum cedrus_h264_pic_type pic_type; -+ } h264; -+ } codec; - }; - - struct cedrus_ctx { -@@ -79,6 +101,19 @@ struct cedrus_ctx { - struct v4l2_ctrl **ctrls; - - struct vb2_buffer *dst_bufs[VIDEO_MAX_FRAME]; -+ -+ union { -+ struct { -+ void *mv_col_buf; -+ dma_addr_t mv_col_buf_dma; -+ ssize_t mv_col_buf_field_size; -+ ssize_t mv_col_buf_size; -+ void *pic_info_buf; -+ dma_addr_t pic_info_buf_dma; -+ void *neighbor_info_buf; -+ dma_addr_t neighbor_info_buf_dma; -+ } h264; -+ } codec; - }; - - struct cedrus_dec_ops { -@@ -122,6 +157,7 @@ struct cedrus_dev { - }; - - extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2; -+extern struct cedrus_dec_ops cedrus_dec_ops_h264; - - static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val) - { -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -index 4d6d602cdde6..bdad87eb9d79 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c -@@ -46,6 +46,19 @@ void cedrus_device_run(void *priv) - V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION); - break; - -+ case V4L2_PIX_FMT_H264_SLICE_RAW: -+ run.h264.decode_params = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS); -+ run.h264.pps = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_H264_PPS); -+ run.h264.scaling_matrix = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX); -+ run.h264.slice_params = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS); -+ run.h264.sps = cedrus_find_control_data(ctx, -+ V4L2_CID_MPEG_VIDEO_H264_SPS); -+ break; -+ - default: - break; - } -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -new file mode 100644 -index 000000000000..a30bb283f69f ---- /dev/null -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c -@@ -0,0 +1,576 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Cedrus VPU driver -+ * -+ * Copyright (c) 2013 Jens Kuske -+ * Copyright (c) 2018 Bootlin -+ */ -+ -+#include -+ -+#include -+ -+#include "cedrus.h" -+#include "cedrus_hw.h" -+#include "cedrus_regs.h" -+ -+enum cedrus_h264_sram_off { -+ CEDRUS_SRAM_H264_PRED_WEIGHT_TABLE = 0x000, -+ CEDRUS_SRAM_H264_FRAMEBUFFER_LIST = 0x100, -+ CEDRUS_SRAM_H264_REF_LIST_0 = 0x190, -+ CEDRUS_SRAM_H264_REF_LIST_1 = 0x199, -+ CEDRUS_SRAM_H264_SCALING_LIST_8x8_0 = 0x200, -+ CEDRUS_SRAM_H264_SCALING_LIST_8x8_1 = 0x210, -+ CEDRUS_SRAM_H264_SCALING_LIST_4x4 = 0x220, -+}; -+ -+struct cedrus_h264_sram_ref_pic { -+ __le32 top_field_order_cnt; -+ __le32 bottom_field_order_cnt; -+ __le32 frame_info; -+ __le32 luma_ptr; -+ __le32 chroma_ptr; -+ __le32 mv_col_top_ptr; -+ __le32 mv_col_bot_ptr; -+ __le32 reserved; -+} __packed; -+ -+#define CEDRUS_H264_FRAME_NUM 18 -+ -+#define CEDRUS_NEIGHBOR_INFO_BUF_SIZE (16 * SZ_1K) -+#define CEDRUS_PIC_INFO_BUF_SIZE (128 * SZ_1K) -+ -+static void cedrus_h264_write_sram(struct cedrus_dev *dev, -+ enum cedrus_h264_sram_off off, -+ const void *data, size_t len) -+{ -+ const u32 *buffer = data; -+ size_t count = DIV_ROUND_UP(len, 4); -+ -+ cedrus_write(dev, VE_AVC_SRAM_PORT_OFFSET, off << 2); -+ -+ while (count--) -+ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, *buffer++); -+} -+ -+static dma_addr_t cedrus_h264_mv_col_buf_addr(struct cedrus_ctx *ctx, -+ unsigned int position, -+ unsigned int field) -+{ -+ dma_addr_t addr = ctx->codec.h264.mv_col_buf_dma; -+ -+ /* Adjust for the position */ -+ addr += position * ctx->codec.h264.mv_col_buf_field_size * 2; -+ -+ /* Adjust for the field */ -+ addr += field * ctx->codec.h264.mv_col_buf_field_size; -+ -+ return addr; -+} -+ -+static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx, -+ struct cedrus_buffer *buf, -+ unsigned int top_field_order_cnt, -+ unsigned int bottom_field_order_cnt, -+ struct cedrus_h264_sram_ref_pic *pic) -+{ -+ struct vb2_buffer *vbuf = &buf->m2m_buf.vb.vb2_buf; -+ unsigned int position = buf->codec.h264.position; -+ -+ pic->top_field_order_cnt = cpu_to_le32(top_field_order_cnt); -+ pic->bottom_field_order_cnt = cpu_to_le32(bottom_field_order_cnt); -+ pic->frame_info = cpu_to_le32(buf->codec.h264.pic_type << 8); -+ -+ pic->luma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 0)); -+ pic->chroma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 1)); -+ pic->mv_col_top_ptr = -+ cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 0)); -+ pic->mv_col_bot_ptr = -+ cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 1)); -+} -+ -+static void cedrus_write_frame_list(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ struct cedrus_h264_sram_ref_pic pic_list[CEDRUS_H264_FRAME_NUM]; -+ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; -+ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; -+ const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; -+ struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; -+ struct cedrus_buffer *output_buf; -+ struct cedrus_dev *dev = ctx->dev; -+ unsigned long used_dpbs = 0; -+ unsigned int position; -+ unsigned int output = 0; -+ unsigned int i; -+ -+ memset(pic_list, 0, sizeof(pic_list)); -+ -+ for (i = 0; i < ARRAY_SIZE(decode->dpb); i++) { -+ const struct v4l2_h264_dpb_entry *dpb = &decode->dpb[i]; -+ struct cedrus_buffer *cedrus_buf; -+ int buf_idx; -+ -+ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID)) -+ continue; -+ -+ buf_idx = vb2_find_timestamp(cap_q, dpb->reference_ts, 0); -+ if (buf_idx < 0) -+ continue; -+ -+ cedrus_buf = vb2_to_cedrus_buffer(ctx->dst_bufs[buf_idx]); -+ position = cedrus_buf->codec.h264.position; -+ used_dpbs |= BIT(position); -+ -+ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) -+ continue; -+ -+ cedrus_fill_ref_pic(ctx, cedrus_buf, -+ dpb->top_field_order_cnt, -+ dpb->bottom_field_order_cnt, -+ &pic_list[position]); -+ -+ output = max(position, output); -+ } -+ -+ position = find_next_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM, -+ output); -+ if (position >= CEDRUS_H264_FRAME_NUM) -+ position = find_first_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM); -+ -+ output_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf); -+ output_buf->codec.h264.position = position; -+ -+ if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) -+ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FIELD; -+ else if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) -+ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_MBAFF; -+ else -+ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FRAME; -+ -+ cedrus_fill_ref_pic(ctx, output_buf, -+ decode->top_field_order_cnt, -+ decode->bottom_field_order_cnt, -+ &pic_list[position]); -+ -+ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_FRAMEBUFFER_LIST, -+ pic_list, sizeof(pic_list)); -+ -+ cedrus_write(dev, VE_H264_OUTPUT_FRAME_IDX, position); -+} -+ -+#define CEDRUS_MAX_REF_IDX 32 -+ -+static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, -+ struct cedrus_run *run, -+ const u8 *ref_list, u8 num_ref, -+ enum cedrus_h264_sram_off sram) -+{ -+ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; -+ struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; -+ struct cedrus_dev *dev = ctx->dev; -+ u8 sram_array[CEDRUS_MAX_REF_IDX]; -+ unsigned int i; -+ size_t size; -+ -+ memset(sram_array, 0, sizeof(sram_array)); -+ -+ for (i = 0; i < num_ref; i++) { -+ const struct v4l2_h264_dpb_entry *dpb; -+ const struct cedrus_buffer *cedrus_buf; -+ const struct vb2_v4l2_buffer *ref_buf; -+ unsigned int position; -+ int buf_idx; -+ u8 dpb_idx; -+ -+ dpb_idx = ref_list[i]; -+ dpb = &decode->dpb[dpb_idx]; -+ -+ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) -+ continue; -+ -+ buf_idx = vb2_find_timestamp(cap_q, dpb->reference_ts, 0); -+ if (buf_idx < 0) -+ continue; -+ -+ ref_buf = to_vb2_v4l2_buffer(ctx->dst_bufs[buf_idx]); -+ cedrus_buf = vb2_v4l2_to_cedrus_buffer(ref_buf); -+ position = cedrus_buf->codec.h264.position; -+ -+ sram_array[i] |= position << 1; -+ if (ref_buf->field == V4L2_FIELD_BOTTOM) -+ sram_array[i] |= BIT(0); -+ } -+ -+ size = min_t(size_t, ALIGN(num_ref, 4), sizeof(sram_array)); -+ cedrus_h264_write_sram(dev, sram, &sram_array, size); -+} -+ -+static void cedrus_write_ref_list0(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; -+ -+ _cedrus_write_ref_list(ctx, run, -+ slice->ref_pic_list0, -+ slice->num_ref_idx_l0_active_minus1 + 1, -+ CEDRUS_SRAM_H264_REF_LIST_0); -+} -+ -+static void cedrus_write_ref_list1(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; -+ -+ _cedrus_write_ref_list(ctx, run, -+ slice->ref_pic_list1, -+ slice->num_ref_idx_l1_active_minus1 + 1, -+ CEDRUS_SRAM_H264_REF_LIST_1); -+} -+ -+static void cedrus_write_scaling_lists(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ const struct v4l2_ctrl_h264_scaling_matrix *scaling = -+ run->h264.scaling_matrix; -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_8x8_0, -+ scaling->scaling_list_8x8[0], -+ sizeof(scaling->scaling_list_8x8[0])); -+ -+ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_8x8_1, -+ scaling->scaling_list_8x8[3], -+ sizeof(scaling->scaling_list_8x8[3])); -+ -+ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_4x4, -+ scaling->scaling_list_4x4, -+ sizeof(scaling->scaling_list_4x4)); -+} -+ -+static void cedrus_write_pred_weight_table(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ const struct v4l2_ctrl_h264_slice_params *slice = -+ run->h264.slice_params; -+ const struct v4l2_h264_pred_weight_table *pred_weight = -+ &slice->pred_weight_table; -+ struct cedrus_dev *dev = ctx->dev; -+ int i, j, k; -+ -+ cedrus_write(dev, VE_H264_SHS_WP, -+ ((pred_weight->chroma_log2_weight_denom & 0x7) << 4) | -+ ((pred_weight->luma_log2_weight_denom & 0x7) << 0)); -+ -+ cedrus_write(dev, VE_AVC_SRAM_PORT_OFFSET, -+ CEDRUS_SRAM_H264_PRED_WEIGHT_TABLE << 2); -+ -+ for (i = 0; i < ARRAY_SIZE(pred_weight->weight_factors); i++) { -+ const struct v4l2_h264_weight_factors *factors = -+ &pred_weight->weight_factors[i]; -+ -+ for (j = 0; j < ARRAY_SIZE(factors->luma_weight); j++) { -+ u32 val; -+ -+ val = (((u32)factors->luma_offset[j] & 0x1ff) << 16) | -+ (factors->luma_weight[j] & 0x1ff); -+ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, val); -+ } -+ -+ for (j = 0; j < ARRAY_SIZE(factors->chroma_weight); j++) { -+ for (k = 0; k < ARRAY_SIZE(factors->chroma_weight[0]); k++) { -+ u32 val; -+ -+ val = (((u32)factors->chroma_offset[j][k] & 0x1ff) << 16) | -+ (factors->chroma_weight[j][k] & 0x1ff); -+ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, val); -+ } -+ } -+ } -+} -+ -+static void cedrus_set_params(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; -+ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; -+ const struct v4l2_ctrl_h264_pps *pps = run->h264.pps; -+ const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; -+ struct vb2_buffer *src_buf = &run->src->vb2_buf; -+ struct cedrus_dev *dev = ctx->dev; -+ dma_addr_t src_buf_addr; -+ u32 offset = slice->header_bit_size; -+ u32 len = (slice->size * 8) - offset; -+ u32 reg; -+ -+ cedrus_write(dev, VE_H264_VLD_LEN, len); -+ cedrus_write(dev, VE_H264_VLD_OFFSET, offset); -+ -+ src_buf_addr = vb2_dma_contig_plane_dma_addr(src_buf, 0); -+ cedrus_write(dev, VE_H264_VLD_END, -+ src_buf_addr + vb2_get_plane_payload(src_buf, 0)); -+ cedrus_write(dev, VE_H264_VLD_ADDR, -+ VE_H264_VLD_ADDR_VAL(src_buf_addr) | -+ VE_H264_VLD_ADDR_FIRST | VE_H264_VLD_ADDR_VALID | -+ VE_H264_VLD_ADDR_LAST); -+ -+ /* -+ * FIXME: Since the bitstream parsing is done in software, and -+ * in userspace, this shouldn't be needed anymore. But it -+ * turns out that removing it breaks the decoding process, -+ * without any clear indication why. -+ */ -+ cedrus_write(dev, VE_H264_TRIGGER_TYPE, -+ VE_H264_TRIGGER_TYPE_INIT_SWDEC); -+ -+ if (((pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && -+ (slice->slice_type == V4L2_H264_SLICE_TYPE_P || -+ slice->slice_type == V4L2_H264_SLICE_TYPE_SP)) || -+ (pps->weighted_bipred_idc == 1 && -+ slice->slice_type == V4L2_H264_SLICE_TYPE_B)) -+ cedrus_write_pred_weight_table(ctx, run); -+ -+ if ((slice->slice_type == V4L2_H264_SLICE_TYPE_P) || -+ (slice->slice_type == V4L2_H264_SLICE_TYPE_SP) || -+ (slice->slice_type == V4L2_H264_SLICE_TYPE_B)) -+ cedrus_write_ref_list0(ctx, run); -+ -+ if (slice->slice_type == V4L2_H264_SLICE_TYPE_B) -+ cedrus_write_ref_list1(ctx, run); -+ -+ // picture parameters -+ reg = 0; -+ /* -+ * FIXME: the kernel headers are allowing the default value to -+ * be passed, but the libva doesn't give us that. -+ */ -+ reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 10; -+ reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 5; -+ reg |= (pps->weighted_bipred_idc & 0x3) << 2; -+ if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) -+ reg |= VE_H264_PPS_ENTROPY_CODING_MODE; -+ if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) -+ reg |= VE_H264_PPS_WEIGHTED_PRED; -+ if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) -+ reg |= VE_H264_PPS_CONSTRAINED_INTRA_PRED; -+ if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) -+ reg |= VE_H264_PPS_TRANSFORM_8X8_MODE; -+ cedrus_write(dev, VE_H264_PPS, reg); -+ -+ // sequence parameters -+ reg = 0; -+ reg |= (sps->chroma_format_idc & 0x7) << 19; -+ reg |= (sps->pic_width_in_mbs_minus1 & 0xff) << 8; -+ reg |= sps->pic_height_in_map_units_minus1 & 0xff; -+ if (sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) -+ reg |= VE_H264_SPS_MBS_ONLY; -+ if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) -+ reg |= VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD; -+ if (sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) -+ reg |= VE_H264_SPS_DIRECT_8X8_INFERENCE; -+ cedrus_write(dev, VE_H264_SPS, reg); -+ -+ // slice parameters -+ reg = 0; -+ reg |= decode->nal_ref_idc ? BIT(12) : 0; -+ reg |= (slice->slice_type & 0xf) << 8; -+ reg |= slice->cabac_init_idc & 0x3; -+ reg |= VE_H264_SHS_FIRST_SLICE_IN_PIC; -+ if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) -+ reg |= VE_H264_SHS_FIELD_PIC; -+ if (slice->flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) -+ reg |= VE_H264_SHS_BOTTOM_FIELD; -+ if (slice->flags & V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED) -+ reg |= VE_H264_SHS_DIRECT_SPATIAL_MV_PRED; -+ cedrus_write(dev, VE_H264_SHS, reg); -+ -+ reg = 0; -+ reg |= VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD; -+ reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 24; -+ reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 16; -+ reg |= (slice->disable_deblocking_filter_idc & 0x3) << 8; -+ reg |= (slice->slice_alpha_c0_offset_div2 & 0xf) << 4; -+ reg |= slice->slice_beta_offset_div2 & 0xf; -+ cedrus_write(dev, VE_H264_SHS2, reg); -+ -+ reg = 0; -+ reg |= (pps->second_chroma_qp_index_offset & 0x3f) << 16; -+ reg |= (pps->chroma_qp_index_offset & 0x3f) << 8; -+ reg |= (pps->pic_init_qp_minus26 + 26 + slice->slice_qp_delta) & 0x3f; -+ cedrus_write(dev, VE_H264_SHS_QP, reg); -+ -+ // clear status flags -+ cedrus_write(dev, VE_H264_STATUS, cedrus_read(dev, VE_H264_STATUS)); -+ -+ // enable int -+ cedrus_write(dev, VE_H264_CTRL, -+ VE_H264_CTRL_SLICE_DECODE_INT | -+ VE_H264_CTRL_DECODE_ERR_INT | -+ VE_H264_CTRL_VLD_DATA_REQ_INT); -+} -+ -+static enum cedrus_irq_status -+cedrus_h264_irq_status(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ u32 reg = cedrus_read(dev, VE_H264_STATUS); -+ -+ if (reg & (VE_H264_STATUS_DECODE_ERR_INT | -+ VE_H264_STATUS_VLD_DATA_REQ_INT)) -+ return CEDRUS_IRQ_ERROR; -+ -+ if (reg & VE_H264_CTRL_SLICE_DECODE_INT) -+ return CEDRUS_IRQ_OK; -+ -+ return CEDRUS_IRQ_NONE; -+} -+ -+static void cedrus_h264_irq_clear(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_write(dev, VE_H264_STATUS, -+ VE_H264_STATUS_INT_MASK); -+} -+ -+static void cedrus_h264_irq_disable(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ u32 reg = cedrus_read(dev, VE_H264_CTRL); -+ -+ cedrus_write(dev, VE_H264_CTRL, -+ reg & ~VE_H264_CTRL_INT_MASK); -+} -+ -+static void cedrus_h264_setup(struct cedrus_ctx *ctx, -+ struct cedrus_run *run) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_engine_enable(dev, CEDRUS_CODEC_H264); -+ -+ cedrus_write(dev, VE_H264_SDROT_CTRL, 0); -+ cedrus_write(dev, VE_H264_EXTRA_BUFFER1, -+ ctx->codec.h264.pic_info_buf_dma); -+ cedrus_write(dev, VE_H264_EXTRA_BUFFER2, -+ ctx->codec.h264.neighbor_info_buf_dma); -+ -+ cedrus_write_scaling_lists(ctx, run); -+ cedrus_write_frame_list(ctx, run); -+ -+ cedrus_set_params(ctx, run); -+} -+ -+static int cedrus_h264_start(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ unsigned int field_size; -+ unsigned int mv_col_size; -+ int ret; -+ -+ /* -+ * FIXME: It seems that the H6 cedarX code is using a formula -+ * here based on the size of the frame, while all the older -+ * code is using a fixed size, so that might need to be -+ * changed at some point. -+ */ -+ ctx->codec.h264.pic_info_buf = -+ dma_alloc_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, -+ &ctx->codec.h264.pic_info_buf_dma, -+ GFP_KERNEL); -+ if (!ctx->codec.h264.pic_info_buf) -+ return -ENOMEM; -+ -+ /* -+ * That buffer is supposed to be 16kiB in size, and be aligned -+ * on 16kiB as well. However, dma_alloc_coherent provides the -+ * guarantee that we'll have a CPU and DMA address aligned on -+ * the smallest page order that is greater to the requested -+ * size, so we don't have to overallocate. -+ */ -+ ctx->codec.h264.neighbor_info_buf = -+ dma_alloc_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, -+ &ctx->codec.h264.neighbor_info_buf_dma, -+ GFP_KERNEL); -+ if (!ctx->codec.h264.neighbor_info_buf) { -+ ret = -ENOMEM; -+ goto err_pic_buf; -+ } -+ -+ field_size = DIV_ROUND_UP(ctx->src_fmt.width, 16) * -+ DIV_ROUND_UP(ctx->src_fmt.height, 16) * 16; -+ -+ /* -+ * FIXME: This is actually conditional to -+ * V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE not being set, we -+ * might have to rework this if memory efficiency ever is -+ * something we need to work on. -+ */ -+ field_size = field_size * 2; -+ -+ /* -+ * FIXME: This is actually conditional to -+ * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY not being set, we might -+ * have to rework this if memory efficiency ever is something -+ * we need to work on. -+ */ -+ field_size = field_size * 2; -+ ctx->codec.h264.mv_col_buf_field_size = field_size; -+ -+ mv_col_size = field_size * 2 * CEDRUS_H264_FRAME_NUM; -+ ctx->codec.h264.mv_col_buf_size = mv_col_size; -+ ctx->codec.h264.mv_col_buf = dma_alloc_coherent(dev->dev, -+ ctx->codec.h264.mv_col_buf_size, -+ &ctx->codec.h264.mv_col_buf_dma, -+ GFP_KERNEL); -+ if (!ctx->codec.h264.mv_col_buf) { -+ ret = -ENOMEM; -+ goto err_neighbor_buf; -+ } -+ -+ return 0; -+ -+err_neighbor_buf: -+ dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, -+ ctx->codec.h264.neighbor_info_buf, -+ ctx->codec.h264.neighbor_info_buf_dma); -+ -+err_pic_buf: -+ dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, -+ ctx->codec.h264.pic_info_buf, -+ ctx->codec.h264.pic_info_buf_dma); -+ return ret; -+} -+ -+static void cedrus_h264_stop(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ dma_free_coherent(dev->dev, ctx->codec.h264.mv_col_buf_size, -+ ctx->codec.h264.mv_col_buf, -+ ctx->codec.h264.mv_col_buf_dma); -+ dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, -+ ctx->codec.h264.neighbor_info_buf, -+ ctx->codec.h264.neighbor_info_buf_dma); -+ dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, -+ ctx->codec.h264.pic_info_buf, -+ ctx->codec.h264.pic_info_buf_dma); -+} -+ -+static void cedrus_h264_trigger(struct cedrus_ctx *ctx) -+{ -+ struct cedrus_dev *dev = ctx->dev; -+ -+ cedrus_write(dev, VE_H264_TRIGGER_TYPE, -+ VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE); -+} -+ -+struct cedrus_dec_ops cedrus_dec_ops_h264 = { -+ .irq_clear = cedrus_h264_irq_clear, -+ .irq_disable = cedrus_h264_irq_disable, -+ .irq_status = cedrus_h264_irq_status, -+ .setup = cedrus_h264_setup, -+ .start = cedrus_h264_start, -+ .stop = cedrus_h264_stop, -+ .trigger = cedrus_h264_trigger, -+}; -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -index 60406b2d4595..c34aec7c6e40 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c -@@ -46,6 +46,10 @@ int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) - reg |= VE_MODE_DEC_MPEG; - break; - -+ case CEDRUS_CODEC_H264: -+ reg |= VE_MODE_DEC_H264; -+ break; -+ - default: - return -EINVAL; - } -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -index de2d6b6f64bf..3e9931416e45 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h -@@ -232,4 +232,95 @@ - #define VE_DEC_MPEG_ROT_LUMA (VE_ENGINE_DEC_MPEG + 0xcc) - #define VE_DEC_MPEG_ROT_CHROMA (VE_ENGINE_DEC_MPEG + 0xd0) - -+#define VE_H264_SPS 0x200 -+#define VE_H264_SPS_MBS_ONLY BIT(18) -+#define VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD BIT(17) -+#define VE_H264_SPS_DIRECT_8X8_INFERENCE BIT(16) -+ -+#define VE_H264_PPS 0x204 -+#define VE_H264_PPS_ENTROPY_CODING_MODE BIT(15) -+#define VE_H264_PPS_WEIGHTED_PRED BIT(4) -+#define VE_H264_PPS_CONSTRAINED_INTRA_PRED BIT(1) -+#define VE_H264_PPS_TRANSFORM_8X8_MODE BIT(0) -+ -+#define VE_H264_SHS 0x208 -+#define VE_H264_SHS_FIRST_SLICE_IN_PIC BIT(5) -+#define VE_H264_SHS_FIELD_PIC BIT(4) -+#define VE_H264_SHS_BOTTOM_FIELD BIT(3) -+#define VE_H264_SHS_DIRECT_SPATIAL_MV_PRED BIT(2) -+ -+#define VE_H264_SHS2 0x20c -+#define VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD BIT(12) -+ -+#define VE_H264_SHS_WP 0x210 -+ -+#define VE_H264_SHS_QP 0x21c -+#define VE_H264_SHS_QP_SCALING_MATRIX_DEFAULT BIT(24) -+ -+#define VE_H264_CTRL 0x220 -+#define VE_H264_CTRL_VLD_DATA_REQ_INT BIT(2) -+#define VE_H264_CTRL_DECODE_ERR_INT BIT(1) -+#define VE_H264_CTRL_SLICE_DECODE_INT BIT(0) -+ -+#define VE_H264_CTRL_INT_MASK (VE_H264_CTRL_VLD_DATA_REQ_INT | \ -+ VE_H264_CTRL_DECODE_ERR_INT | \ -+ VE_H264_CTRL_SLICE_DECODE_INT) -+ -+#define VE_H264_TRIGGER_TYPE 0x224 -+#define VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE (8 << 0) -+#define VE_H264_TRIGGER_TYPE_INIT_SWDEC (7 << 0) -+ -+#define VE_H264_STATUS 0x228 -+#define VE_H264_STATUS_VLD_DATA_REQ_INT VE_H264_CTRL_VLD_DATA_REQ_INT -+#define VE_H264_STATUS_DECODE_ERR_INT VE_H264_CTRL_DECODE_ERR_INT -+#define VE_H264_STATUS_SLICE_DECODE_INT VE_H264_CTRL_SLICE_DECODE_INT -+ -+#define VE_H264_STATUS_INT_MASK VE_H264_CTRL_INT_MASK -+ -+#define VE_H264_CUR_MB_NUM 0x22c -+ -+#define VE_H264_VLD_ADDR 0x230 -+#define VE_H264_VLD_ADDR_FIRST BIT(30) -+#define VE_H264_VLD_ADDR_LAST BIT(29) -+#define VE_H264_VLD_ADDR_VALID BIT(28) -+#define VE_H264_VLD_ADDR_VAL(x) (((x) & 0x0ffffff0) | ((x) >> 28)) -+ -+#define VE_H264_VLD_OFFSET 0x234 -+#define VE_H264_VLD_LEN 0x238 -+#define VE_H264_VLD_END 0x23c -+#define VE_H264_SDROT_CTRL 0x240 -+#define VE_H264_OUTPUT_FRAME_IDX 0x24c -+#define VE_H264_EXTRA_BUFFER1 0x250 -+#define VE_H264_EXTRA_BUFFER2 0x254 -+#define VE_H264_BASIC_BITS 0x2dc -+#define VE_AVC_SRAM_PORT_OFFSET 0x2e0 -+#define VE_AVC_SRAM_PORT_DATA 0x2e4 -+ -+#define VE_ISP_INPUT_SIZE 0xa00 -+#define VE_ISP_INPUT_STRIDE 0xa04 -+#define VE_ISP_CTRL 0xa08 -+#define VE_ISP_INPUT_LUMA 0xa78 -+#define VE_ISP_INPUT_CHROMA 0xa7c -+ -+#define VE_AVC_PARAM 0xb04 -+#define VE_AVC_QP 0xb08 -+#define VE_AVC_MOTION_EST 0xb10 -+#define VE_AVC_CTRL 0xb14 -+#define VE_AVC_TRIGGER 0xb18 -+#define VE_AVC_STATUS 0xb1c -+#define VE_AVC_BASIC_BITS 0xb20 -+#define VE_AVC_UNK_BUF 0xb60 -+#define VE_AVC_VLE_ADDR 0xb80 -+#define VE_AVC_VLE_END 0xb84 -+#define VE_AVC_VLE_OFFSET 0xb88 -+#define VE_AVC_VLE_MAX 0xb8c -+#define VE_AVC_VLE_LENGTH 0xb90 -+#define VE_AVC_REF_LUMA 0xba0 -+#define VE_AVC_REF_CHROMA 0xba4 -+#define VE_AVC_REC_LUMA 0xbb0 -+#define VE_AVC_REC_CHROMA 0xbb4 -+#define VE_AVC_REF_SLUMA 0xbb8 -+#define VE_AVC_REC_SLUMA 0xbbc -+#define VE_AVC_MB_INFO 0xbc0 -+ - #endif -diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -index 9673874ece10..e2b530b1a956 100644 ---- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c -+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c -@@ -37,6 +37,10 @@ static struct cedrus_format cedrus_formats[] = { - .pixelformat = V4L2_PIX_FMT_MPEG2_SLICE, - .directions = CEDRUS_DECODE_SRC, - }, -+ { -+ .pixelformat = V4L2_PIX_FMT_H264_SLICE_RAW, -+ .directions = CEDRUS_DECODE_SRC, -+ }, - { - .pixelformat = V4L2_PIX_FMT_SUNXI_TILED_NV12, - .directions = CEDRUS_DECODE_DST, -@@ -100,6 +104,7 @@ static void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt) - - switch (pix_fmt->pixelformat) { - case V4L2_PIX_FMT_MPEG2_SLICE: -+ case V4L2_PIX_FMT_H264_SLICE_RAW: - /* Zero bytes per line for encoded source. */ - bytesperline = 0; - -@@ -464,6 +469,10 @@ static int cedrus_start_streaming(struct vb2_queue *vq, unsigned int count) - ctx->current_codec = CEDRUS_CODEC_MPEG2; - break; - -+ case V4L2_PIX_FMT_H264_SLICE_RAW: -+ ctx->current_codec = CEDRUS_CODEC_H264; -+ break; -+ - default: - return -EINVAL; - } --- -2.21.0 - -From ca0961011db57e39880df0b5708df8aa3339dc6f Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 18 May 2019 17:40:14 +0200 -Subject: [PATCH] ARM: dts: sun8i-h3: Fix wifi in Beelink X2 DT - -mmc1 node where wifi module is connected doesn't have properly defined -power supplies so wifi module is never powered up. Fix that by -specifying additional power supplies. - -Additionally, this STB may have either Realtek or Broadcom based wifi -module. One based on Broadcom module also needs external clock to work -properly. Fix that by adding clock property to wifi_pwrseq node. - -Fixes: e582b47a9252 ("ARM: dts: sun8i-h3: Add dts for the Beelink X2 STB") -Signed-off-by: Jernej Skrabec -Signed-off-by: Maxime Ripard ---- - arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts -index 6277f13f3eb3..ac9e26b1d906 100644 ---- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts -+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts -@@ -90,6 +90,8 @@ - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ -+ clocks = <&rtc 1>; -+ clock-names = "ext_clock"; - }; - - sound_spdif { -@@ -155,6 +157,8 @@ - - &mmc1 { - vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc3v3>; -+ mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; --- -2.21.0 - -From 85c6fadd185e495a3ef9cd8a60bb70b82b72d941 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 14 May 2019 22:54:45 +0200 -Subject: [PATCH] arm64: dts: allwinner: a64: orangepi-win: Add wifi and - bluetooth nodes - -The AP6212 is based on the Broadcom BCM43430 or BCM43438. The WiFi side -identifies as BCM43430, while the Bluetooth side identifies as BCM43438. - -WiFi is connected to mmc1 and the Bluetooth side is connected to UART1 -in a 4 wire configuration. Same as the WiFi side, due to being the same -chip and package, DLDO2 provides overall power via VBAT, and DLDO4 -provides I/O power via VDDIO. The RTC clock output provides the LPO low -power clock at 32.768 kHz. - -This patch enables WiFi and Bluetooth on OrangePi Win boards and adds -missing LPO clock on the WiFi side. PCM connection also exists for -Bluetooth audio, but it's not used here. - -Bluetooth UART speed is set to 1.5 MBaud in order to be able transmit -audio. While module supports even higher speeds, currently sunxi clock -driver doesn't support higher speed. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Maxime Ripard ---- - .../dts/allwinner/sun50i-a64-orangepi-win.dts | 23 +++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -index 510f661229dc..5ef3c62c765e 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts -@@ -109,6 +109,8 @@ - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ -+ clocks = <&rtc 1>; -+ clock-names = "ext_clock"; - }; - }; - -@@ -170,6 +172,14 @@ - bus-width = <4>; - non-removable; - status = "okay"; -+ -+ brcmf: wifi@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ interrupt-parent = <&r_pio>; -+ interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ -+ interrupt-names = "host-wake"; -+ }; - }; - - &ohci0 { -@@ -342,7 +352,20 @@ - &uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; -+ uart-has-rtscts; - status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm43438-bt"; -+ max-speed = <1500000>; -+ clocks = <&rtc 1>; -+ clock-names = "lpo"; -+ vbat-supply = <®_dldo2>; -+ vddio-supply = <®_dldo4>; -+ device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ -+ host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ -+ shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ -+ }; - }; - - /* On Pi-2 connector, RTS/CTS optional */ --- -2.21.0 - -From ae3ceed0a399fa0cc83410ce7bbf3a1675b733a9 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= -Date: Thu, 23 May 2019 17:10:49 +0200 -Subject: [PATCH] arm64: dts: allwinner: h6: add r_watchog node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Allwinner H6 has a r_watchdog similar to A64. - -Declare it in the device-tree. - -Signed-off-by: Clément Péron -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 13e70aebddbe..b9a7dc8d2a40 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -631,6 +631,13 @@ - #reset-cells = <1>; - }; - -+ r_watchdog: watchdog@7020400 { -+ compatible = "allwinner,sun50i-h6-wdt", -+ "allwinner,sun6i-a31-wdt"; -+ reg = <0x07020400 0x20>; -+ interrupts = ; -+ }; -+ - r_intc: interrupt-controller@7021000 { - compatible = "allwinner,sun50i-h6-r-intc", - "allwinner,sun6i-a31-r-intc"; --- -2.21.0 - -From 22538576beb671038bd21be4094432fa8070ad81 Mon Sep 17 00:00:00 2001 -From: Icenowy Zheng -Date: Fri, 3 May 2019 17:47:20 +0800 -Subject: [PATCH] arm64: dts: allwinner: h6: add PIO VCC bank supplies for Pine - H64 - -The Allwinner H6 SoC features tweakable VCC for PC, PD, PG, PL and PM -banks. - -This patch adds supplies for these banks except PL bank. PL bank is -where PMIC is attached, and currently if a PMIC regulator is added -for it a dependency loop will happen. - -Signed-off-by: Icenowy Zheng -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -index 4802902e128f..9e464d40cbff 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts -@@ -127,6 +127,12 @@ - status = "okay"; - }; - -+&pio { -+ vcc-pc-supply = <®_bldo2>; -+ vcc-pd-supply = <®_cldo1>; -+ vcc-pg-supply = <®_aldo1>; -+}; -+ - &r_i2c { - status = "okay"; - -@@ -247,6 +253,10 @@ - }; - }; - -+&r_pio { -+ vcc-pm-supply = <®_aldo1>; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; --- -2.21.0 - -From 43a90fc76a3ebe0ce3315725c7f0fa832df50c8e Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 27 May 2019 22:14:54 +0200 -Subject: [PATCH 1/4] dmaengine: sun6i: Add a quirk for additional mbus clock -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -H6 DMA controller needs additional mbus clock to be enabled. - -Add a quirk for it and handle it accordingly. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Clément Péron -Acked-by: Maxime Ripard -Signed-off-by: Vinod Koul ---- - drivers/dma/sun6i-dma.c | 23 ++++++++++++++++++++++- - 1 file changed, 22 insertions(+), 1 deletion(-) - -diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c -index 0cd13f17fc11..7d9606997251 100644 ---- a/drivers/dma/sun6i-dma.c -+++ b/drivers/dma/sun6i-dma.c -@@ -129,6 +129,7 @@ struct sun6i_dma_config { - u32 dst_burst_lengths; - u32 src_addr_widths; - u32 dst_addr_widths; -+ bool has_mbus_clk; - }; - - /* -@@ -182,6 +183,7 @@ struct sun6i_dma_dev { - struct dma_device slave; - void __iomem *base; - struct clk *clk; -+ struct clk *clk_mbus; - int irq; - spinlock_t lock; - struct reset_control *rstc; -@@ -1208,6 +1210,14 @@ static int sun6i_dma_probe(struct platform_device *pdev) - return PTR_ERR(sdc->clk); - } - -+ if (sdc->cfg->has_mbus_clk) { -+ sdc->clk_mbus = devm_clk_get(&pdev->dev, "mbus"); -+ if (IS_ERR(sdc->clk_mbus)) { -+ dev_err(&pdev->dev, "No mbus clock specified\n"); -+ return PTR_ERR(sdc->clk_mbus); -+ } -+ } -+ - sdc->rstc = devm_reset_control_get(&pdev->dev, NULL); - if (IS_ERR(sdc->rstc)) { - dev_err(&pdev->dev, "No reset controller specified\n"); -@@ -1312,11 +1322,19 @@ static int sun6i_dma_probe(struct platform_device *pdev) - goto err_reset_assert; - } - -+ if (sdc->cfg->has_mbus_clk) { -+ ret = clk_prepare_enable(sdc->clk_mbus); -+ if (ret) { -+ dev_err(&pdev->dev, "Couldn't enable mbus clock\n"); -+ goto err_clk_disable; -+ } -+ } -+ - ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0, - dev_name(&pdev->dev), sdc); - if (ret) { - dev_err(&pdev->dev, "Cannot request IRQ\n"); -- goto err_clk_disable; -+ goto err_mbus_clk_disable; - } - - ret = dma_async_device_register(&sdc->slave); -@@ -1341,6 +1359,8 @@ static int sun6i_dma_probe(struct platform_device *pdev) - dma_async_device_unregister(&sdc->slave); - err_irq_disable: - sun6i_kill_tasklet(sdc); -+err_mbus_clk_disable: -+ clk_disable_unprepare(sdc->clk_mbus); - err_clk_disable: - clk_disable_unprepare(sdc->clk); - err_reset_assert: -@@ -1359,6 +1379,7 @@ static int sun6i_dma_remove(struct platform_device *pdev) - - sun6i_kill_tasklet(sdc); - -+ clk_disable_unprepare(sdc->clk_mbus); - clk_disable_unprepare(sdc->clk); - reset_control_assert(sdc->rstc); - --- -2.22.0 - - -From 67f34055118cb6dcdfeea9e1980309afa80b2b7c Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 27 May 2019 22:14:55 +0200 -Subject: [PATCH 2/4] dmaengine: sun6i: Add a quirk for setting DRQ fields -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -H6 DMA has more than 32 possible DRQs. That means that current maximum -of 31 DRQs is not enough anymore. - -Add a quirk which will set source and destination DRQ number. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Clément Péron -Acked-by: Maxime Ripard -Signed-off-by: Vinod Koul ---- - drivers/dma/sun6i-dma.c | 48 ++++++++++++++++++++++++----------------- - 1 file changed, 28 insertions(+), 20 deletions(-) - -diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c -index 7d9606997251..f725b93fd21a 100644 ---- a/drivers/dma/sun6i-dma.c -+++ b/drivers/dma/sun6i-dma.c -@@ -68,15 +68,15 @@ - #define DMA_CHAN_LLI_ADDR 0x08 - - #define DMA_CHAN_CUR_CFG 0x0c --#define DMA_CHAN_MAX_DRQ 0x1f --#define DMA_CHAN_CFG_SRC_DRQ(x) ((x) & DMA_CHAN_MAX_DRQ) -+#define DMA_CHAN_MAX_DRQ_A31 0x1f -+#define DMA_CHAN_CFG_SRC_DRQ_A31(x) ((x) & DMA_CHAN_MAX_DRQ_A31) - #define DMA_CHAN_CFG_SRC_IO_MODE BIT(5) - #define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5) - #define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7) - #define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6) - #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9) - --#define DMA_CHAN_CFG_DST_DRQ(x) (DMA_CHAN_CFG_SRC_DRQ(x) << 16) -+#define DMA_CHAN_CFG_DST_DRQ_A31(x) (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16) - #define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16) - #define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16) - #define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16) -@@ -125,6 +125,7 @@ struct sun6i_dma_config { - */ - void (*clock_autogate_enable)(struct sun6i_dma_dev *); - void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst); -+ void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq); - u32 src_burst_lengths; - u32 dst_burst_lengths; - u32 src_addr_widths; -@@ -311,6 +312,12 @@ static void sun6i_set_burst_length_h3(u32 *p_cfg, s8 src_burst, s8 dst_burst) - DMA_CHAN_CFG_DST_BURST_H3(dst_burst); - } - -+static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq) -+{ -+ *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_A31(src_drq) | -+ DMA_CHAN_CFG_DST_DRQ_A31(dst_drq); -+} -+ - static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan) - { - struct sun6i_desc *txd = pchan->desc; -@@ -634,14 +641,13 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( - - burst = convert_burst(8); - width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES); -- v_lli->cfg = DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | -- DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | -- DMA_CHAN_CFG_DST_LINEAR_MODE | -+ v_lli->cfg = DMA_CHAN_CFG_DST_LINEAR_MODE | - DMA_CHAN_CFG_SRC_LINEAR_MODE | - DMA_CHAN_CFG_SRC_WIDTH(width) | - DMA_CHAN_CFG_DST_WIDTH(width); - - sdev->cfg->set_burst_length(&v_lli->cfg, burst, burst); -+ sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, DRQ_SDRAM); - - sun6i_dma_lli_add(NULL, v_lli, p_lli, txd); - -@@ -695,9 +701,8 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( - v_lli->dst = sconfig->dst_addr; - v_lli->cfg = lli_cfg | - DMA_CHAN_CFG_DST_IO_MODE | -- DMA_CHAN_CFG_SRC_LINEAR_MODE | -- DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | -- DMA_CHAN_CFG_DST_DRQ(vchan->port); -+ DMA_CHAN_CFG_SRC_LINEAR_MODE; -+ sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port); - - dev_dbg(chan2dev(chan), - "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", -@@ -710,9 +715,8 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( - v_lli->dst = sg_dma_address(sg); - v_lli->cfg = lli_cfg | - DMA_CHAN_CFG_DST_LINEAR_MODE | -- DMA_CHAN_CFG_SRC_IO_MODE | -- DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | -- DMA_CHAN_CFG_SRC_DRQ(vchan->port); -+ DMA_CHAN_CFG_SRC_IO_MODE; -+ sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM); - - dev_dbg(chan2dev(chan), - "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", -@@ -780,17 +784,15 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic( - v_lli->dst = sconfig->dst_addr; - v_lli->cfg = lli_cfg | - DMA_CHAN_CFG_DST_IO_MODE | -- DMA_CHAN_CFG_SRC_LINEAR_MODE | -- DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | -- DMA_CHAN_CFG_DST_DRQ(vchan->port); -+ DMA_CHAN_CFG_SRC_LINEAR_MODE; -+ sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port); - } else { - v_lli->src = sconfig->src_addr; - v_lli->dst = buf_addr + period_len * i; - v_lli->cfg = lli_cfg | - DMA_CHAN_CFG_DST_LINEAR_MODE | -- DMA_CHAN_CFG_SRC_IO_MODE | -- DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | -- DMA_CHAN_CFG_SRC_DRQ(vchan->port); -+ DMA_CHAN_CFG_SRC_IO_MODE; -+ sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM); - } - - prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd); -@@ -1055,6 +1057,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = { - .nr_max_requests = 30, - .nr_max_vchans = 53, - .set_burst_length = sun6i_set_burst_length_a31, -+ .set_drq = sun6i_set_drq_a31, - .src_burst_lengths = BIT(1) | BIT(8), - .dst_burst_lengths = BIT(1) | BIT(8), - .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | -@@ -1076,6 +1079,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = { - .nr_max_vchans = 37, - .clock_autogate_enable = sun6i_enable_clock_autogate_a23, - .set_burst_length = sun6i_set_burst_length_a31, -+ .set_drq = sun6i_set_drq_a31, - .src_burst_lengths = BIT(1) | BIT(8), - .dst_burst_lengths = BIT(1) | BIT(8), - .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | -@@ -1092,6 +1096,7 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg = { - .nr_max_vchans = 39, - .clock_autogate_enable = sun6i_enable_clock_autogate_a23, - .set_burst_length = sun6i_set_burst_length_a31, -+ .set_drq = sun6i_set_drq_a31, - .src_burst_lengths = BIT(1) | BIT(8), - .dst_burst_lengths = BIT(1) | BIT(8), - .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | -@@ -1115,6 +1120,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { - .nr_max_vchans = 34, - .clock_autogate_enable = sun6i_enable_clock_autogate_h3, - .set_burst_length = sun6i_set_burst_length_h3, -+ .set_drq = sun6i_set_drq_a31, - .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), - .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), - .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | -@@ -1134,6 +1140,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { - static struct sun6i_dma_config sun50i_a64_dma_cfg = { - .clock_autogate_enable = sun6i_enable_clock_autogate_h3, - .set_burst_length = sun6i_set_burst_length_h3, -+ .set_drq = sun6i_set_drq_a31, - .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), - .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), - .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | -@@ -1157,6 +1164,7 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = { - .nr_max_vchans = 24, - .clock_autogate_enable = sun6i_enable_clock_autogate_a23, - .set_burst_length = sun6i_set_burst_length_a31, -+ .set_drq = sun6i_set_drq_a31, - .src_burst_lengths = BIT(1) | BIT(8), - .dst_burst_lengths = BIT(1) | BIT(8), - .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | -@@ -1272,8 +1280,8 @@ static int sun6i_dma_probe(struct platform_device *pdev) - ret = of_property_read_u32(np, "dma-requests", &sdc->max_request); - if (ret && !sdc->max_request) { - dev_info(&pdev->dev, "Missing dma-requests, using %u.\n", -- DMA_CHAN_MAX_DRQ); -- sdc->max_request = DMA_CHAN_MAX_DRQ; -+ DMA_CHAN_MAX_DRQ_A31); -+ sdc->max_request = DMA_CHAN_MAX_DRQ_A31; - } - - /* --- -2.22.0 - - -From 802440bdf3b78721402f12495dffbb25522119bf Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 27 May 2019 22:14:56 +0200 -Subject: [PATCH 3/4] dmaengine: sun6i: Add a quirk for setting mode fields -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -H6 DMA has mode fields in different position than any other currently -supported DMA controller. - -Add a quirk for that. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Clément Péron -Acked-by: Maxime Ripard -Signed-off-by: Vinod Koul ---- - drivers/dma/sun6i-dma.c | 46 ++++++++++++++++++++++++----------------- - 1 file changed, 27 insertions(+), 19 deletions(-) - -diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c -index f725b93fd21a..f5cb5e89bf7b 100644 ---- a/drivers/dma/sun6i-dma.c -+++ b/drivers/dma/sun6i-dma.c -@@ -70,15 +70,13 @@ - #define DMA_CHAN_CUR_CFG 0x0c - #define DMA_CHAN_MAX_DRQ_A31 0x1f - #define DMA_CHAN_CFG_SRC_DRQ_A31(x) ((x) & DMA_CHAN_MAX_DRQ_A31) --#define DMA_CHAN_CFG_SRC_IO_MODE BIT(5) --#define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5) -+#define DMA_CHAN_CFG_SRC_MODE_A31(x) (((x) & 0x1) << 5) - #define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7) - #define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6) - #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9) - - #define DMA_CHAN_CFG_DST_DRQ_A31(x) (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16) --#define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16) --#define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16) -+#define DMA_CHAN_CFG_DST_MODE_A31(x) (DMA_CHAN_CFG_SRC_MODE_A31(x) << 16) - #define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16) - #define DMA_CHAN_CFG_DST_BURST_H3(x) (DMA_CHAN_CFG_SRC_BURST_H3(x) << 16) - #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16) -@@ -98,6 +96,8 @@ - #define LLI_LAST_ITEM 0xfffff800 - #define NORMAL_WAIT 8 - #define DRQ_SDRAM 1 -+#define LINEAR_MODE 0 -+#define IO_MODE 1 - - /* forward declaration */ - struct sun6i_dma_dev; -@@ -126,6 +126,7 @@ struct sun6i_dma_config { - void (*clock_autogate_enable)(struct sun6i_dma_dev *); - void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst); - void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq); -+ void (*set_mode)(u32 *p_cfg, s8 src_mode, s8 dst_mode); - u32 src_burst_lengths; - u32 dst_burst_lengths; - u32 src_addr_widths; -@@ -318,6 +319,12 @@ static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq) - DMA_CHAN_CFG_DST_DRQ_A31(dst_drq); - } - -+static void sun6i_set_mode_a31(u32 *p_cfg, s8 src_mode, s8 dst_mode) -+{ -+ *p_cfg |= DMA_CHAN_CFG_SRC_MODE_A31(src_mode) | -+ DMA_CHAN_CFG_DST_MODE_A31(dst_mode); -+} -+ - static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan) - { - struct sun6i_desc *txd = pchan->desc; -@@ -641,13 +648,12 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( - - burst = convert_burst(8); - width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES); -- v_lli->cfg = DMA_CHAN_CFG_DST_LINEAR_MODE | -- DMA_CHAN_CFG_SRC_LINEAR_MODE | -- DMA_CHAN_CFG_SRC_WIDTH(width) | -+ v_lli->cfg = DMA_CHAN_CFG_SRC_WIDTH(width) | - DMA_CHAN_CFG_DST_WIDTH(width); - - sdev->cfg->set_burst_length(&v_lli->cfg, burst, burst); - sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, DRQ_SDRAM); -+ sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, LINEAR_MODE); - - sun6i_dma_lli_add(NULL, v_lli, p_lli, txd); - -@@ -699,10 +705,9 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( - if (dir == DMA_MEM_TO_DEV) { - v_lli->src = sg_dma_address(sg); - v_lli->dst = sconfig->dst_addr; -- v_lli->cfg = lli_cfg | -- DMA_CHAN_CFG_DST_IO_MODE | -- DMA_CHAN_CFG_SRC_LINEAR_MODE; -+ v_lli->cfg = lli_cfg; - sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port); -+ sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE); - - dev_dbg(chan2dev(chan), - "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", -@@ -713,10 +718,9 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( - } else { - v_lli->src = sconfig->src_addr; - v_lli->dst = sg_dma_address(sg); -- v_lli->cfg = lli_cfg | -- DMA_CHAN_CFG_DST_LINEAR_MODE | -- DMA_CHAN_CFG_SRC_IO_MODE; -+ v_lli->cfg = lli_cfg; - sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM); -+ sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE); - - dev_dbg(chan2dev(chan), - "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", -@@ -782,17 +786,15 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic( - if (dir == DMA_MEM_TO_DEV) { - v_lli->src = buf_addr + period_len * i; - v_lli->dst = sconfig->dst_addr; -- v_lli->cfg = lli_cfg | -- DMA_CHAN_CFG_DST_IO_MODE | -- DMA_CHAN_CFG_SRC_LINEAR_MODE; -+ v_lli->cfg = lli_cfg; - sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port); -+ sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE); - } else { - v_lli->src = sconfig->src_addr; - v_lli->dst = buf_addr + period_len * i; -- v_lli->cfg = lli_cfg | -- DMA_CHAN_CFG_DST_LINEAR_MODE | -- DMA_CHAN_CFG_SRC_IO_MODE; -+ v_lli->cfg = lli_cfg; - sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM); -+ sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE); - } - - prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd); -@@ -1058,6 +1060,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = { - .nr_max_vchans = 53, - .set_burst_length = sun6i_set_burst_length_a31, - .set_drq = sun6i_set_drq_a31, -+ .set_mode = sun6i_set_mode_a31, - .src_burst_lengths = BIT(1) | BIT(8), - .dst_burst_lengths = BIT(1) | BIT(8), - .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | -@@ -1080,6 +1083,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = { - .clock_autogate_enable = sun6i_enable_clock_autogate_a23, - .set_burst_length = sun6i_set_burst_length_a31, - .set_drq = sun6i_set_drq_a31, -+ .set_mode = sun6i_set_mode_a31, - .src_burst_lengths = BIT(1) | BIT(8), - .dst_burst_lengths = BIT(1) | BIT(8), - .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | -@@ -1097,6 +1101,7 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg = { - .clock_autogate_enable = sun6i_enable_clock_autogate_a23, - .set_burst_length = sun6i_set_burst_length_a31, - .set_drq = sun6i_set_drq_a31, -+ .set_mode = sun6i_set_mode_a31, - .src_burst_lengths = BIT(1) | BIT(8), - .dst_burst_lengths = BIT(1) | BIT(8), - .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | -@@ -1121,6 +1126,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { - .clock_autogate_enable = sun6i_enable_clock_autogate_h3, - .set_burst_length = sun6i_set_burst_length_h3, - .set_drq = sun6i_set_drq_a31, -+ .set_mode = sun6i_set_mode_a31, - .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), - .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), - .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | -@@ -1141,6 +1147,7 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = { - .clock_autogate_enable = sun6i_enable_clock_autogate_h3, - .set_burst_length = sun6i_set_burst_length_h3, - .set_drq = sun6i_set_drq_a31, -+ .set_mode = sun6i_set_mode_a31, - .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), - .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), - .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | -@@ -1165,6 +1172,7 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = { - .clock_autogate_enable = sun6i_enable_clock_autogate_a23, - .set_burst_length = sun6i_set_burst_length_a31, - .set_drq = sun6i_set_drq_a31, -+ .set_mode = sun6i_set_mode_a31, - .src_burst_lengths = BIT(1) | BIT(8), - .dst_burst_lengths = BIT(1) | BIT(8), - .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | --- -2.22.0 - - -From 2fe5575f36cacaab860ed9822eb6b2ea7b6a52ba Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 27 May 2019 22:14:57 +0200 -Subject: [PATCH 4/4] dmaengine: sun6i: Add support for H6 DMA -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -H6 DMA has more than 32 supported DRQs, which means that configuration -register is slightly rearranged. It also needs additional clock to be -enabled. - -Add support for it. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Clément Péron -Acked-by: Maxime Ripard -Signed-off-by: Vinod Koul ---- - drivers/dma/sun6i-dma.c | 40 ++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 40 insertions(+) - -diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c -index f5cb5e89bf7b..ddef87ebdfdb 100644 ---- a/drivers/dma/sun6i-dma.c -+++ b/drivers/dma/sun6i-dma.c -@@ -69,14 +69,19 @@ - - #define DMA_CHAN_CUR_CFG 0x0c - #define DMA_CHAN_MAX_DRQ_A31 0x1f -+#define DMA_CHAN_MAX_DRQ_H6 0x3f - #define DMA_CHAN_CFG_SRC_DRQ_A31(x) ((x) & DMA_CHAN_MAX_DRQ_A31) -+#define DMA_CHAN_CFG_SRC_DRQ_H6(x) ((x) & DMA_CHAN_MAX_DRQ_H6) - #define DMA_CHAN_CFG_SRC_MODE_A31(x) (((x) & 0x1) << 5) -+#define DMA_CHAN_CFG_SRC_MODE_H6(x) (((x) & 0x1) << 8) - #define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7) - #define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6) - #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9) - - #define DMA_CHAN_CFG_DST_DRQ_A31(x) (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16) -+#define DMA_CHAN_CFG_DST_DRQ_H6(x) (DMA_CHAN_CFG_SRC_DRQ_H6(x) << 16) - #define DMA_CHAN_CFG_DST_MODE_A31(x) (DMA_CHAN_CFG_SRC_MODE_A31(x) << 16) -+#define DMA_CHAN_CFG_DST_MODE_H6(x) (DMA_CHAN_CFG_SRC_MODE_H6(x) << 16) - #define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16) - #define DMA_CHAN_CFG_DST_BURST_H3(x) (DMA_CHAN_CFG_SRC_BURST_H3(x) << 16) - #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16) -@@ -319,12 +324,24 @@ static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq) - DMA_CHAN_CFG_DST_DRQ_A31(dst_drq); - } - -+static void sun6i_set_drq_h6(u32 *p_cfg, s8 src_drq, s8 dst_drq) -+{ -+ *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_H6(src_drq) | -+ DMA_CHAN_CFG_DST_DRQ_H6(dst_drq); -+} -+ - static void sun6i_set_mode_a31(u32 *p_cfg, s8 src_mode, s8 dst_mode) - { - *p_cfg |= DMA_CHAN_CFG_SRC_MODE_A31(src_mode) | - DMA_CHAN_CFG_DST_MODE_A31(dst_mode); - } - -+static void sun6i_set_mode_h6(u32 *p_cfg, s8 src_mode, s8 dst_mode) -+{ -+ *p_cfg |= DMA_CHAN_CFG_SRC_MODE_H6(src_mode) | -+ DMA_CHAN_CFG_DST_MODE_H6(dst_mode); -+} -+ - static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan) - { - struct sun6i_desc *txd = pchan->desc; -@@ -1160,6 +1177,28 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = { - BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), - }; - -+/* -+ * The H6 binding uses the number of dma channels from the -+ * device tree node. -+ */ -+static struct sun6i_dma_config sun50i_h6_dma_cfg = { -+ .clock_autogate_enable = sun6i_enable_clock_autogate_h3, -+ .set_burst_length = sun6i_set_burst_length_h3, -+ .set_drq = sun6i_set_drq_h6, -+ .set_mode = sun6i_set_mode_h6, -+ .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), -+ .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), -+ .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | -+ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | -+ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | -+ BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), -+ .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | -+ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | -+ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | -+ BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), -+ .has_mbus_clk = true, -+}; -+ - /* - * The V3s have only 8 physical channels, a maximum DRQ port id of 23, - * and a total of 24 usable source and destination endpoints. -@@ -1190,6 +1229,7 @@ static const struct of_device_id sun6i_dma_match[] = { - { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg }, - { .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg }, - { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg }, -+ { .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, sun6i_dma_match); --- -2.22.0 - -From 9164665a390a2a42e9f56094eeec8c4a52748723 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 11 Jun 2019 23:40:55 +0200 -Subject: [PATCH] arm64: dts: allwinner: h6: Add DMA node -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -H6 has DMA controller which supports 16 channels. - -Add a node for it. - -Signed-off-by: Jernej Skrabec -Signed-off-by: Clément Péron -Signed-off-by: Maxime Ripard ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index b9a7dc8d2a40..7628a7c83096 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -203,6 +203,18 @@ - #reset-cells = <1>; - }; - -+ dma: dma-controller@3002000 { -+ compatible = "allwinner,sun50i-h6-dma"; -+ reg = <0x03002000 0x1000>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; -+ clock-names = "bus", "mbus"; -+ dma-channels = <16>; -+ dma-requests = <46>; -+ resets = <&ccu RST_BUS_DMA>; -+ #dma-cells = <1>; -+ }; -+ - sid: sid@3006000 { - compatible = "allwinner,sun50i-h6-sid"; - reg = <0x03006000 0x400>; --- -2.22.0 - -From f167675486c37b88620d344fbb12d06e34f11d47 Mon Sep 17 00:00:00 2001 -From: Ondrej Jirman -Date: Tue, 4 Jun 2019 17:40:36 +0200 -Subject: [PATCH] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate - register -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The current code defines W1 clock gate to be at 0x1cc, overlaying it -with the IR gate. - -Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver -causing interrupt floods on H6 (because interrupt flags can't be cleared, -due to IR module's bus being disabled). - -Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU") -Signed-off-by: Ondrej Jirman -Acked-by: Clément Péron -Signed-off-by: Maxime Ripard ---- - drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c -index 27554eaf6929..8d05d4f1f8a1 100644 ---- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c -+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c -@@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2", - static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir", "r-apb1", - 0x1cc, BIT(0), 0); - static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1", -- 0x1cc, BIT(0), 0); -+ 0x1ec, BIT(0), 0); - - /* Information of IR(RX) mod clock is gathered from BSP source code */ - static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" }; --- -2.22.0 - diff --git a/projects/Allwinner/patches/linux/0003-backport-from-5.4.patch b/projects/Allwinner/patches/linux/0002-backport-from-5.4.patch similarity index 100% rename from projects/Allwinner/patches/linux/0003-backport-from-5.4.patch rename to projects/Allwinner/patches/linux/0002-backport-from-5.4.patch diff --git a/projects/Allwinner/patches/linux/0006-wip-cec-improvements.patch b/projects/Allwinner/patches/linux/0006-wip-cec-improvements.patch index fc1b07d068..a76231d10e 100644 --- a/projects/Allwinner/patches/linux/0006-wip-cec-improvements.patch +++ b/projects/Allwinner/patches/linux/0006-wip-cec-improvements.patch @@ -113,10 +113,11 @@ diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i index 720c5aa8adc1..49ca001923e3 100644 --- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h -@@ -12,6 +12,7 @@ +@@ -12,6 +12,8 @@ #include #include #include ++#include +#include #define SUN8I_HDMI_PHY_DBG_CTRL_REG 0x0000 @@ -251,7 +252,7 @@ index 43643ad31730..d840bc07cba6 100644 + phy->cec_notifier = cec_notifier_get(dev); + if (!phy->cec_notifier) { + ret = -ENOMEM; -+ goto err_disable_clk_mod; ++ goto err_disable_clk_phy; + } + + phy->cec_adapter =