From 36bf5aa381769a595926ceeb9171c57d787d9d55 Mon Sep 17 00:00:00 2001 From: heitbaum Date: Tue, 11 May 2021 13:38:11 +0000 Subject: [PATCH] linux (Rockchip): update patches for 5.12 --- .../linux-0001-rockchip-from-5.11.patch | 3068 ----------------- .../linux-0002-rockchip-from-5.12.patch | 662 ---- .../linux-0004-rockchip-from-list.patch | 3 +- .../default/linux-0010-v4l2-from-list.patch | 13 +- .../default/linux-0020-drm-from-5.11.patch | 465 --- .../default/linux-0021-drm-from-list.patch | 28 - .../default/linux-1003-for-libreelec.patch | 11 +- .../linux-2000-v4l-wip-rkvdec-vp9.patch | 7 +- .../linux-2001-v4l-wip-rkvdec-hevc.patch | 30 +- .../linux-2002-v4l-wip-iep-driver.patch | 2 +- 10 files changed, 19 insertions(+), 4270 deletions(-) delete mode 100644 projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.11.patch delete mode 100644 projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-5.12.patch delete mode 100644 projects/Rockchip/patches/linux/default/linux-0020-drm-from-5.11.patch diff --git a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.11.patch b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.11.patch deleted file mode 100644 index 0bf1066b21..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.11.patch +++ /dev/null @@ -1,3068 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Robin Murphy -Date: Mon, 26 Oct 2020 11:17:20 +0000 -Subject: [PATCH] clk: rockchip: Add appropriate arch dependencies - -There's no point offering support for 32-bit platforms to users -configuring a 64-bit kernel - and vice-versa - unless they are -explicitly interested in compile-testing. - -Signed-off-by: Robin Murphy -Link: https://lore.kernel.org/r/72abb0f794b8ed77e274e8ee21c22e0bd3223dfd.1603710913.git.robin.murphy@arm.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/Kconfig | 12 +++++++++++- - 1 file changed, 11 insertions(+), 1 deletion(-) - -diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig -index 47cd6c5de837..effd05032e85 100644 ---- a/drivers/clk/rockchip/Kconfig -+++ b/drivers/clk/rockchip/Kconfig -@@ -11,67 +11,77 @@ config COMMON_CLK_ROCKCHIP - if COMMON_CLK_ROCKCHIP - config CLK_PX30 - bool "Rockchip PX30 clock controller support" -+ depends on (ARM64 || COMPILE_TEST) - default y - help - Build the driver for PX30 Clock Driver. - - config CLK_RV110X - bool "Rockchip RV110x clock controller support" -+ depends on (ARM || COMPILE_TEST) - default y - help - Build the driver for RV110x Clock Driver. - - config CLK_RK3036 - bool "Rockchip RK3036 clock controller support" -+ depends on (ARM || COMPILE_TEST) - default y - help - Build the driver for RK3036 Clock Driver. - - config CLK_RK312X - bool "Rockchip RK312x clock controller support" -+ depends on (ARM || COMPILE_TEST) - default y - help - Build the driver for RK312x Clock Driver. - - config CLK_RK3188 - bool "Rockchip RK3188 clock controller support" -+ depends on (ARM || COMPILE_TEST) - default y - help - Build the driver for RK3188 Clock Driver. - - config CLK_RK322X - bool "Rockchip RK322x clock controller support" -+ depends on (ARM || COMPILE_TEST) - default y - help - Build the driver for RK322x Clock Driver. - - config CLK_RK3288 - bool "Rockchip RK3288 clock controller support" -- depends on ARM -+ depends on (ARM || COMPILE_TEST) - default y - help - Build the driver for RK3288 Clock Driver. - - config CLK_RK3308 - bool "Rockchip RK3308 clock controller support" -+ depends on (ARM64 || COMPILE_TEST) - default y - help - Build the driver for RK3308 Clock Driver. - - config CLK_RK3328 - bool "Rockchip RK3328 clock controller support" -+ depends on (ARM64 || COMPILE_TEST) - default y - help - Build the driver for RK3328 Clock Driver. - - config CLK_RK3368 - bool "Rockchip RK3368 clock controller support" -+ depends on (ARM64 || COMPILE_TEST) - default y - help - Build the driver for RK3368 Clock Driver. - - config CLK_RK3399 - tristate "Rockchip RK3399 clock controller support" -+ depends on (ARM64 || COMPILE_TEST) - default y - help - Build the driver for RK3399 Clock Driver. - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Xu Wang -Date: Fri, 27 Nov 2020 09:05:51 +0000 -Subject: [PATCH] clk: rockchip: Remove redundant null check before - clk_prepare_enable - -Because clk_prepare_enable() already checked NULL clock parameter, -so the additional check is unnecessary, just remove it. - -Signed-off-by: Xu Wang -Acked-by: Stephen Boyd -Link: https://lore.kernel.org/r/20201127090551.50254-1-vulab@iscas.ac.cn -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c -index b443169dd408..336481bc6cc7 100644 ---- a/drivers/clk/rockchip/clk.c -+++ b/drivers/clk/rockchip/clk.c -@@ -603,8 +603,7 @@ void rockchip_clk_protect_critical(const char *const clocks[], - for (i = 0; i < nclocks; i++) { - struct clk *clk = __clk_lookup(clocks[i]); - -- if (clk) -- clk_prepare_enable(clk); -+ clk_prepare_enable(clk); - } - } - EXPORT_SYMBOL_GPL(rockchip_clk_protect_critical); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Wed, 18 Nov 2020 14:58:16 +0100 -Subject: [PATCH] clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a - i2s and uart clocks - -Add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks, -so that the parent COMPOSITE_FRACMUX and COMPOSITE_NOMUX -also update. - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20201118135822.9582-2-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3188.c | 28 ++++++++++++++-------------- - 1 file changed, 14 insertions(+), 14 deletions(-) - -diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c -index 730020fcc7fe..db8c588139de 100644 ---- a/drivers/clk/rockchip/clk-rk3188.c -+++ b/drivers/clk/rockchip/clk-rk3188.c -@@ -255,19 +255,19 @@ static struct rockchip_clk_branch common_spdif_fracmux __initdata = - RK2928_CLKSEL_CON(5), 8, 2, MFLAGS); - - static struct rockchip_clk_branch common_uart0_fracmux __initdata = -- MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, 0, -+ MUX(SCLK_UART0, "sclk_uart0", mux_sclk_uart0_p, CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(13), 8, 2, MFLAGS); - - static struct rockchip_clk_branch common_uart1_fracmux __initdata = -- MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, 0, -+ MUX(SCLK_UART1, "sclk_uart1", mux_sclk_uart1_p, CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(14), 8, 2, MFLAGS); - - static struct rockchip_clk_branch common_uart2_fracmux __initdata = -- MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, 0, -+ MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(15), 8, 2, MFLAGS); - - static struct rockchip_clk_branch common_uart3_fracmux __initdata = -- MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, 0, -+ MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(16), 8, 2, MFLAGS); - - static struct rockchip_clk_branch common_clk_branches[] __initdata = { -@@ -408,28 +408,28 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { - COMPOSITE_NOMUX(0, "uart0_pre", "uart_src", 0, - RK2928_CLKSEL_CON(13), 0, 7, DFLAGS, - RK2928_CLKGATE_CON(1), 8, GFLAGS), -- COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", 0, -+ COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(17), 0, - RK2928_CLKGATE_CON(1), 9, GFLAGS, - &common_uart0_fracmux), - COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0, - RK2928_CLKSEL_CON(14), 0, 7, DFLAGS, - RK2928_CLKGATE_CON(1), 10, GFLAGS), -- COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", 0, -+ COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(18), 0, - RK2928_CLKGATE_CON(1), 11, GFLAGS, - &common_uart1_fracmux), - COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0, - RK2928_CLKSEL_CON(15), 0, 7, DFLAGS, - RK2928_CLKGATE_CON(1), 12, GFLAGS), -- COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", 0, -+ COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(19), 0, - RK2928_CLKGATE_CON(1), 13, GFLAGS, - &common_uart2_fracmux), - COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0, - RK2928_CLKSEL_CON(16), 0, 7, DFLAGS, - RK2928_CLKGATE_CON(1), 14, GFLAGS), -- COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", 0, -+ COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(20), 0, - RK2928_CLKGATE_CON(1), 15, GFLAGS, - &common_uart3_fracmux), -@@ -543,15 +543,15 @@ static struct clk_div_table div_aclk_cpu_t[] = { - }; - - static struct rockchip_clk_branch rk3066a_i2s0_fracmux __initdata = -- MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, 0, -+ MUX(SCLK_I2S0, "sclk_i2s0", mux_sclk_i2s0_p, CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(2), 8, 2, MFLAGS); - - static struct rockchip_clk_branch rk3066a_i2s1_fracmux __initdata = -- MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, 0, -+ MUX(SCLK_I2S1, "sclk_i2s1", mux_sclk_i2s1_p, CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(3), 8, 2, MFLAGS); - - static struct rockchip_clk_branch rk3066a_i2s2_fracmux __initdata = -- MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, 0, -+ MUX(SCLK_I2S2, "sclk_i2s2", mux_sclk_i2s2_p, CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(4), 8, 2, MFLAGS); - - static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { -@@ -615,21 +615,21 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { - COMPOSITE_NOMUX(0, "i2s0_pre", "i2s_src", 0, - RK2928_CLKSEL_CON(2), 0, 7, DFLAGS, - RK2928_CLKGATE_CON(0), 7, GFLAGS), -- COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0, -+ COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(6), 0, - RK2928_CLKGATE_CON(0), 8, GFLAGS, - &rk3066a_i2s0_fracmux), - COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0, - RK2928_CLKSEL_CON(3), 0, 7, DFLAGS, - RK2928_CLKGATE_CON(0), 9, GFLAGS), -- COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", 0, -+ COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(7), 0, - RK2928_CLKGATE_CON(0), 10, GFLAGS, - &rk3066a_i2s1_fracmux), - COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0, - RK2928_CLKSEL_CON(4), 0, 7, DFLAGS, - RK2928_CLKGATE_CON(0), 11, GFLAGS), -- COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", 0, -+ COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", CLK_SET_RATE_PARENT, - RK2928_CLKSEL_CON(8), 0, - RK2928_CLKGATE_CON(0), 12, GFLAGS, - &rk3066a_i2s2_fracmux), - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Wed, 18 Nov 2020 14:58:17 +0100 -Subject: [PATCH] clk: rockchip: fix i2s gate bits on rk3066 and rk3188 - -The Rockchip PX2/RK3066 uses these bits in CRU_CLKGATE7_CON: - -hclk_i2s_8ch_gate_en bit 4 (dtsi: i2s0) -hclk_i2s0_2ch_gate_en bit 2 (dtsi: i2s1) -hclk_i2s1_2ch_gate_en bit 3 (dtsi: i2s2) - -The Rockchip PX3/RK3188 uses this bit in CRU_CLKGATE7_CON: - -hclk_i2s_2ch_gate_en bit 2 (dtsi: i2s0) - -The bits got somehow mixed up in the clk-rk3188.c file. -The labels in the dtsi files are not suppose to change. -The sclk and hclk names should match for -"trace_event=clk_disable,clk_enable", -so remove GATE HCLK_I2S0 from the common clock tree and -fix the bits in the rk3066 and rk3188 clock tree. - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20201118135822.9582-3-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - drivers/clk/rockchip/clk-rk3188.c | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - -diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c -index db8c588139de..0b76ad34de00 100644 ---- a/drivers/clk/rockchip/clk-rk3188.c -+++ b/drivers/clk/rockchip/clk-rk3188.c -@@ -449,7 +449,6 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { - - /* hclk_cpu gates */ - GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS), -- GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), - GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS), - GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS), - /* hclk_ahb2apb is part of a clk branch */ -@@ -634,8 +633,9 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = { - RK2928_CLKGATE_CON(0), 12, GFLAGS, - &rk3066a_i2s2_fracmux), - -- GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), -- GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), -+ GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), -+ GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), -+ GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), - GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS), - GATE(HCLK_HDMI, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), - -@@ -728,6 +728,7 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = { - RK2928_CLKGATE_CON(0), 10, GFLAGS, - &rk3188_i2s0_fracmux), - -+ GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), - GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), - GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS), - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alexandru Stan -Date: Wed, 21 Oct 2020 22:04:43 -0700 -Subject: [PATCH] ARM: dts: rockchip: Remove 0 point from brightness-levels on - rk3288-veyron - -The extra 0 only adds one point in the userspace visible range, -so this change is almost a noop with the current driver behavior. - -We don't need the 0% point, userspace seems to handle this just fine -because it uses the bl_power property to turn off the display. - -Furthermore after adding "backlight: pwm_bl: Fix interpolation" patch, -the backlight interpolation will work a little differently. So we need -to preemptively remove the 0-3 segment since otherwise we would have a -252 long interpolation that would slowly go between 0 and 3, looking -really bad in userspace. So it's almost a noop/cleanup now, but it will -be required in the future. - -Signed-off-by: Alexandru Stan -Reviewed-by: Douglas Anderson -Acked-by: Daniel Thompson -Link: https://lore.kernel.org/r/20201021220404.v3.1.I96b8d872ec51171f19274e43e96cadc092881271@changeid -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288-veyron-jaq.dts | 2 +- - arch/arm/boot/dts/rk3288-veyron-minnie.dts | 2 +- - arch/arm/boot/dts/rk3288-veyron-tiger.dts | 2 +- - 3 files changed, 3 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts -index af77ab20586d..4a148cf1defc 100644 ---- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts -+++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts -@@ -20,7 +20,7 @@ / { - - &backlight { - /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */ -- brightness-levels = <0 8 255>; -+ brightness-levels = <8 255>; - num-interpolated-steps = <247>; - }; - -diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts -index f8b69e0a16a0..82fc6fba9999 100644 ---- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts -+++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts -@@ -39,7 +39,7 @@ volum_up { - - &backlight { - /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ -- brightness-levels = <0 3 255>; -+ brightness-levels = <3 255>; - num-interpolated-steps = <252>; - }; - -diff --git a/arch/arm/boot/dts/rk3288-veyron-tiger.dts b/arch/arm/boot/dts/rk3288-veyron-tiger.dts -index 069f0c2c1fdf..52a84cbe7a90 100644 ---- a/arch/arm/boot/dts/rk3288-veyron-tiger.dts -+++ b/arch/arm/boot/dts/rk3288-veyron-tiger.dts -@@ -23,7 +23,7 @@ / { - - &backlight { - /* Tiger panel PWM must be >= 1%, so start non-zero brightness at 3 */ -- brightness-levels = <0 3 255>; -+ brightness-levels = <3 255>; - num-interpolated-steps = <252>; - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Mon, 16 Nov 2020 16:07:56 +0100 -Subject: [PATCH] ARM: dts: rockchip: rename wdt nodename to watchdog on rv1108 - -A test with the command below gives for example this error: - -/arch/arm/boot/dts/rv1108-evb.dt.yaml: -wdt@10360000: $nodename:0: 'wdt@10360000' -does not match '^watchdog(@.*|-[0-9a-f])?$' - -Fix it by renaming the wdt nodename to watchdog -in the rv1108.dtsi file. - -make ARCH=arm dtbs_check -DT_SCHEMA_FILES=Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20201116150756.14265-1-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rv1108.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi -index a1a08cb9364e..e491964b1c3d 100644 ---- a/arch/arm/boot/dts/rv1108.dtsi -+++ b/arch/arm/boot/dts/rv1108.dtsi -@@ -299,7 +299,7 @@ timer: timer@10350000 { - clock-names = "timer", "pclk"; - }; - -- watchdog: wdt@10360000 { -+ watchdog: watchdog@10360000 { - compatible = "snps,dw-wdt"; - reg = <0x10360000 0x100>; - interrupts = ; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 30 Nov 2020 14:28:14 +0100 -Subject: [PATCH] ARM: dts: rockchip: Add rtc node for VMARC SOM - -Add the hym8563 rtc found on the rk3288 variant of the VMARC SOM. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201023181814.220974-2-jagan@amarulasolutions.com -[split out of the original patch, as it was a change unrelated - to the commit description] -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi -index 4a373f5aa600..da80bfd5f2d5 100644 ---- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi -+++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi -@@ -231,6 +231,23 @@ regulator-state-mem { - }; - }; - -+&i2c1 { -+ clock-frequency = <400000>; -+ status = "okay"; -+ -+ hym8563: rtc@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ interrupt-parent = <&gpio5>; -+ interrupts = ; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "hym8563"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hym8563_int>; -+ }; -+}; -+ - &i2c5 { - status = "okay"; - }; -@@ -245,6 +262,12 @@ &io_domains { - }; - - &pinctrl { -+ hym8563 { -+ hym8563_int: hym8563-int { -+ rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ - pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { - drive-strength = <8>; - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Fri, 23 Oct 2020 23:48:14 +0530 -Subject: [PATCH] ARM: dts: rockchip: Add SDIO0 node for VMARC SOM - -Rockchip RK3288 and RK3399Pro based VMARC SOM has sdio0 for -connecting WiFi/BT devices as a pluggable card via M.2 E-Key. - -Add associated sdio0 nodes, properties. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201023181814.220974-2-jagan@amarulasolutions.com -[moved the unrelated rtc addition to a separate patch] -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288-vmarc-som.dtsi | 17 +++++++++++++++ - .../dts/rockchip-radxa-dalang-carrier.dtsi | 21 +++++++++++++++++++ - .../dts/rockchip/rk3399pro-vmarc-som.dtsi | 16 ++++++++++++++ - 3 files changed, 54 insertions(+) - -diff --git a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi -index da80bfd5f2d5..0ae2bd150e37 100644 ---- a/arch/arm/boot/dts/rk3288-vmarc-som.dtsi -+++ b/arch/arm/boot/dts/rk3288-vmarc-som.dtsi -@@ -258,6 +258,7 @@ &io_domains { - gpio1830-supply = <&vcc_18>; - gpio30-supply = <&vcc_io>; - sdcard-supply = <&vccio_sd>; -+ wifi-supply = <&vcc_wl>; - status = "okay"; - }; - -@@ -283,6 +284,12 @@ pmic_int: pmic-int { - }; - }; - -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - sdmmc { - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = -@@ -314,6 +321,16 @@ usb0_en_oc: usb0-en-oc { - }; - }; - -+&sdio_pwrseq { -+ /* -+ * On the module itself this is one of these (depending -+ * on the actual card populated): -+ * - SDIO_RESET_L_WL_REG_ON -+ * - PDN (power down when low) -+ */ -+ reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; /* WIFI_REG_ON */ -+}; -+ - &usbphy { - status = "okay"; - }; -diff --git a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi -index 26b53eac4706..da1d548b7330 100644 ---- a/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi -+++ b/arch/arm/boot/dts/rockchip-radxa-dalang-carrier.dtsi -@@ -15,6 +15,14 @@ clkin_gmac: external-gmac-clock { - #clock-cells = <0>; - }; - -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&hym8563>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_enable_h>; -+ }; -+ - vcc12v_dcin: vcc12v-dcin-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; -@@ -78,6 +86,19 @@ &pwm2 { - status = "okay"; - }; - -+&sdio0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; -+ - &sdmmc { - bus-width = <4>; - cap-mmc-highspeed; -diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi -index 5d087be04af8..7257494d2831 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi -@@ -353,6 +353,12 @@ pmic_int_l: pmic-int-l { - }; - }; - -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - vbus_host { - usb1_en_oc: usb1-en-oc { - rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; -@@ -371,6 +377,16 @@ &pmu_io_domains { - pmu1830-supply = <&vcc_1v8>; - }; - -+&sdio_pwrseq { -+ /* -+ * On the module itself this is one of these (depending -+ * on the actual card populated): -+ * - SDIO_RESET_L_WL_REG_ON -+ * - PDN (power down when low) -+ */ -+ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; -+}; -+ - &sdhci { - bus-width = <8>; - mmc-hs400-1_8v; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 9 Nov 2020 23:40:15 +0530 -Subject: [PATCH] arm64: defconfig: Enable ROCKCHIP_LVDS - -Now, some of the rockchip hardware platforms do enable -lvds in mainline tree. - -So, enable Rockchip LVDS driver via default defconfig. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-8-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/configs/defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index 5cfe3cf6f2ac..3ebba7dcb98f 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -646,6 +646,7 @@ CONFIG_ROCKCHIP_CDN_DP=y - CONFIG_ROCKCHIP_DW_HDMI=y - CONFIG_ROCKCHIP_DW_MIPI_DSI=y - CONFIG_ROCKCHIP_INNO_HDMI=y -+CONFIG_ROCKCHIP_LVDS=y - CONFIG_DRM_RCAR_DU=m - CONFIG_DRM_RCAR_DW_HDMI=m - CONFIG_DRM_SUN4I=m - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 9 Nov 2020 23:40:16 +0530 -Subject: [PATCH] arm64: defconfig: Enable PHY_ROCKCHIP_INNO_DSIDPHY - -In order to work LDVS, DSI in mainline tree for Rockchip based -hardware platforms, the associated PHY driver has to enable -in default defconfig. - -Enable rockchip DSI phy driver. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-9-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/configs/defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index 3ebba7dcb98f..d50826dd7d68 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -1011,6 +1011,7 @@ CONFIG_PHY_RCAR_GEN3_USB3=m - CONFIG_PHY_ROCKCHIP_EMMC=y - CONFIG_PHY_ROCKCHIP_INNO_HDMI=m - CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m - CONFIG_PHY_ROCKCHIP_PCIE=m - CONFIG_PHY_ROCKCHIP_TYPEC=y - CONFIG_PHY_UNIPHIER_USB2=y - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 9 Nov 2020 23:40:17 +0530 -Subject: [PATCH] arm64: defconfig: Enable USB_SERIAL_CP210X - -Some hardware platforms required CP20x USB to Serial converter -in order to work onboard functionalities like Bluetooth. - -An example of such a platform is from Engicam's PX30 (ARM64). - -Mark it as module in defconfig. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-10-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/configs/defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index d50826dd7d68..41a2d489f0a2 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -751,6 +751,7 @@ CONFIG_USB_CHIPIDEA_UDC=y - CONFIG_USB_CHIPIDEA_HOST=y - CONFIG_USB_ISP1760=y - CONFIG_USB_SERIAL=m -+CONFIG_USB_SERIAL_CP210X=m - CONFIG_USB_SERIAL_FTDI_SIO=m - CONFIG_USB_HSIC_USB3503=y - CONFIG_NOP_USB_XCEIV=y - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Fri, 23 Oct 2020 23:48:13 +0530 -Subject: [PATCH] arm64: defconfig: Enable RTC_DRV_HYM8563 - -RTC HYM8563 used in the ARM64 Rockchip SoC's SDIO power -sequence enablement. - -Enable it as module. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201023181814.220974-1-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/configs/defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index 41a2d489f0a2..699c204090b8 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -816,6 +816,7 @@ CONFIG_EDAC=y - CONFIG_EDAC_GHES=y - CONFIG_RTC_CLASS=y - CONFIG_RTC_DRV_DS1307=m -+CONFIG_RTC_DRV_HYM8563=m - CONFIG_RTC_DRV_MAX77686=y - CONFIG_RTC_DRV_RK808=m - CONFIG_RTC_DRV_PCF85363=m - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Lee Jones -Date: Tue, 3 Nov 2020 15:28:18 +0000 -Subject: [PATCH] soc: rockchip: io-domain: Remove incorrect and incomplete - comment header - -Fixes the following W=1 kernel build warning(s): - - drivers/soc/rockchip/io-domain.c:57: warning: Cannot understand * @supplies: voltage settings matching the register bits. - -Signed-off-by: Lee Jones -Cc: Heiko Stuebner -Cc: Liam Girdwood -Cc: Mark Brown -Cc: "Rafael J. Wysocki" -Cc: Doug Anderson -Cc: linux-rockchip@lists.infradead.org -Link: https://lore.kernel.org/r/20201103152838.1290217-6-lee.jones@linaro.org -Signed-off-by: Heiko Stuebner ---- - drivers/soc/rockchip/io-domain.c | 3 --- - 1 file changed, 3 deletions(-) - -diff --git a/drivers/soc/rockchip/io-domain.c b/drivers/soc/rockchip/io-domain.c -index b29e829e815e..cf8182fc3642 100644 ---- a/drivers/soc/rockchip/io-domain.c -+++ b/drivers/soc/rockchip/io-domain.c -@@ -53,9 +53,6 @@ - - struct rockchip_iodomain; - --/** -- * @supplies: voltage settings matching the register bits. -- */ - struct rockchip_iodomain_soc_data { - int grf_offset; - const char *supply_names[MAX_SUPPLIES]; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= -Date: Wed, 14 Oct 2020 22:00:29 +0200 -Subject: [PATCH] dt-bindings: vendor-prefixes: Add kobol prefix -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The prefix is already used in arm/armada-388-helios4.dts. - -Signed-off-by: Uwe Kleine-König -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20201014200030.845759-2-uwe@kleine-koenig.org -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml -index 2735be1a8470..259faf1b382c 100644 ---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml -+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml -@@ -553,6 +553,8 @@ patternProperties: - description: Kionix, Inc. - "^kobo,.*": - description: Rakuten Kobo Inc. -+ "^kobol,.*": -+ description: Kobol Innovations Pte. Ltd. - "^koe,.*": - description: Kaohsiung Opto-Electronics Inc. - "^kontron,.*": - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= -Date: Wed, 14 Oct 2020 22:00:30 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add basic support for Kobol's Helios64 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The hardware is described in detail on Kobol's wiki at -https://wiki.kobol.io/helios64/intro/. - -Up to now the following peripherals are working: - - - UART - - Micro-SD card - - eMMC - - ethernet port 1 - - status LED - - temperature sensor on i2c bus 2 - -Signed-off-by: Uwe Kleine-König -Link: https://lore.kernel.org/r/20201014200030.845759-3-uwe@kleine-koenig.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../dts/rockchip/rk3399-kobol-helios64.dts | 372 ++++++++++++++++++ - 2 files changed, 373 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index 26661c7b736b..28b26a874313 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-kobol-helios64.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -new file mode 100644 -index 000000000000..2a561be724b2 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -@@ -0,0 +1,372 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Aditya Prayoga -+ */ -+ -+/* -+ * The Kobol Helios64 is a board designed to operate as a NAS and optionally -+ * ships with an enclosing that can host five 2.5" hard disks. -+ * -+ * See https://wiki.kobol.io/helios64/intro/ for further details. -+ */ -+ -+/dts-v1/; -+#include "rk3399.dtsi" -+#include "rk3399-opp.dtsi" -+ -+/ { -+ model = "Kobol Helios64"; -+ compatible = "kobol,helios64", "rockchip,rk3399"; -+ -+ avdd_1v8_s0: avdd-1v8-s0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "avdd_1v8_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc3v3_sys_s3>; -+ }; -+ -+ clkin_gmac: external-gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "clkin_gmac"; -+ #clock-cells = <0>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sys_grn_led_on &sys_red_led_on>; -+ -+ led-0 { -+ label = "helios64:green:status"; -+ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ }; -+ -+ led-1 { -+ label = "helios64:red:fault"; -+ gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; -+ default-state = "keep"; -+ }; -+ }; -+ -+ vcc1v8_sys_s0: vcc1v8-sys-s0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc1v8_sys_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ vin-supply = <&vcc1v8_sys_s3>; -+ }; -+ -+ vcc3v0_sd: vcc3v0-sd { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; -+ regulator-name = "vcc3v0_sd"; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_pwr_h>; -+ vin-supply = <&vcc3v3_sys_s3>; -+ }; -+ -+ vcc3v3_sys_s3: vcc_lan: vcc3v3-sys-s3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin_bkup>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc12v_dcin: vcc12v-dcin { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ vcc12v_dcin_bkup: vcc12v-dcin-bkup { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin_bkup"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+}; -+ -+/* -+ * The system doesn't run stable with cpu freq enabled, so disallow the lower -+ * frequencies until this problem is properly understood and resolved. -+ */ -+&cluster0_opp { -+ /delete-node/ opp00; -+ /delete-node/ opp01; -+ /delete-node/ opp02; -+ /delete-node/ opp03; -+ /delete-node/ opp04; -+}; -+ -+&cluster1_opp { -+ /delete-node/ opp00; -+ /delete-node/ opp01; -+ /delete-node/ opp02; -+ /delete-node/ opp03; -+ /delete-node/ opp04; -+ /delete-node/ opp05; -+ /delete-node/ opp06; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&gmac { -+ assigned-clock-parents = <&clkin_gmac>; -+ assigned-clocks = <&cru SCLK_RMII_SRC>; -+ clock_in_out = "input"; -+ phy-mode = "rgmii"; -+ phy-supply = <&vcc_lan>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins &gphy_reset>; -+ rx_delay = <0x20>; -+ tx_delay = <0x28>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 10000 50000>; -+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <168>; -+ i2c-scl-falling-time-ns = <4>; -+ status = "okay"; -+ -+ rk808: pmic@1b { -+ compatible = "rockchip,rk808"; -+ reg = <0x1b>; -+ interrupt-parent = <&gpio0>; -+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>; -+ clock-output-names = "xin32k", "rk808-clkout2"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc6-supply = <&vcc5v0_sys>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc3v3_sys_s3>; -+ vcc9-supply = <&vcc5v0_sys>; -+ vcc10-supply = <&vcc5v0_sys>; -+ vcc11-supply = <&vcc5v0_sys>; -+ vcc12-supply = <&vcc3v3_sys_s3>; -+ vddio-supply = <&vcc3v0_s3>; -+ wakeup-source; -+ #clock-cells = <1>; -+ -+ regulators { -+ vdd_cpu_l: DCDC_REG2 { -+ regulator-name = "vdd_cpu_l"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_sys_s3: DCDC_REG4 { -+ regulator-name = "vcc1v8_sys_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_sdio_s0: LDO_REG4 { -+ regulator-name = "vcc_sdio_s0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc3v0_s3: LDO_REG8 { -+ regulator-name = "vcc3v0_s3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ }; -+ }; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <160>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+ -+ temp@4c { -+ compatible = "national,lm75"; -+ reg = <0x4c>; -+ }; -+}; -+ -+&io_domains { -+ audio-supply = <&vcc1v8_sys_s0>; -+ bt656-supply = <&vcc1v8_sys_s0>; -+ gpio1830-supply = <&vcc3v0_s3>; -+ sdmmc-supply = <&vcc_sdio_s0>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ gmac { -+ gphy_reset: gphy-reset { -+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; -+ }; -+ }; -+ -+ leds { -+ sys_grn_led_on: sys-grn-led-on { -+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ sys_red_led_on: sys-red-led-on { -+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ vcc3v0-sd { -+ sdmmc0_pwr_h: sdmmc0-pwr-h { -+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmu1830-supply = <&vcc3v0_s3>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-hs200-1_8v; -+ non-removable; -+ vqmmc-supply = <&vcc1v8_sys_s0>; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; -+ vmmc-supply = <&vcc3v0_sd>; -+ vqmmc-supply = <&vcc_sdio_s0>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= -Date: Mon, 2 Nov 2020 16:06:58 +0100 -Subject: [PATCH] dt-bindings: arm: rockchip: Add Kobol Helios64 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Document the new board by Kobol introduced recently in -rockchip/rk3399-kobol-helios64.dts. - -Signed-off-by: Uwe Kleine-König -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20201102150658.167161-1-uwe@kleine-koenig.org -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index b621752aaa65..ad1dbf349c33 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -381,6 +381,11 @@ properties: - - khadas,edge-v - - const: rockchip,rk3399 - -+ - description: Kobol Helios64 -+ items: -+ - const: kobol,helios64 -+ - const: rockchip,rk3399 -+ - - description: Mecer Xtreme Mini S6 - items: - - const: mecer,xms6 - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Sat, 4 Jul 2020 00:14:13 +0200 -Subject: [PATCH] arm64: dts: rockchip: add adc joystick to Odroid Go Advance - -Add the now usable adc-joystick node that describes the analog -joystick connected to two saradc channels from the rk3326 soc. - -Signed-off-by: Heiko Stuebner -Link: https://lore.kernel.org/r/20200703221413.269800-1-heiko@sntech.de ---- - .../boot/dts/rockchip/rk3326-odroid-go2.dts | 24 +++++++++++++++++++ - 1 file changed, 24 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts -index 337681038519..97fb93e1cc00 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts -@@ -18,6 +18,30 @@ chosen { - stdout-path = "serial2:115200n8"; - }; - -+ adc-joystick { -+ compatible = "adc-joystick"; -+ io-channels = <&saradc 1>, -+ <&saradc 2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ axis@0 { -+ reg = <0>; -+ abs-flat = <10>; -+ abs-fuzz = <10>; -+ abs-range = <172 772>; -+ linux,code = ; -+ }; -+ -+ axis@1 { -+ reg = <1>; -+ abs-flat = <10>; -+ abs-fuzz = <10>; -+ abs-range = <278 815>; -+ linux,code = ; -+ }; -+ }; -+ - backlight: backlight { - compatible = "pwm-backlight"; - power-supply = <&vcc_bl>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Tue, 29 Sep 2020 14:02:11 +0530 -Subject: [PATCH] dt-bindings: arm: rockchip: Add Engicam PX30.Core EDIMM2.2 - Starter Kit - -PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. - -EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive -Evaluation Board from Engicam. - -PX30.Core needs to mount on top of this Evaluation board for -creating complete PX30.Core EDIMM2.2 Starter Kit. - -Add bindings for it. - -Signed-off-by: Jagan Teki -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20200929083217.25406-2-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index ad1dbf349c33..cef95eb26ca6 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -70,6 +70,12 @@ properties: - - const: elgin,rv1108-r1 - - const: rockchip,rv1108 - -+ - description: Engicam PX30.Core EDIMM2.2 Starter Kit -+ items: -+ - const: engicam,px30-core-edimm2.2 -+ - const: engicam,px30-core -+ - const: rockchip,px30 -+ - - description: Firefly Firefly-RK3288 - items: - - enum: - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Tue, 29 Sep 2020 14:02:12 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add Engicam EDIMM2.2 Starter Kit - -Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive -Evaluation Board. - -Genaral features: -- LCD 7" C.Touch -- microSD slot -- Ethernet 1Gb -- Wifi/BT -- 2x LVDS Full HD interfaces -- 3x USB 2.0 -- 1x USB 3.0 -- HDMI Out -- Mini PCIe -- MIPI CSI -- 2x CAN -- Audio Out - -SOM's like PX30.Core needs to mount on top of this Evaluation board -for creating complete PX30.Core EDIMM2.2 Starter Kit. - -Add support for it. - -Signed-off-by: Jagan Teki -Signed-off-by: Michael Trimarchi -Link: https://lore.kernel.org/r/20200929083217.25406-3-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - .../dts/rockchip/px30-engicam-common.dtsi | 39 +++++++++++++++++++ - .../dts/rockchip/px30-engicam-edimm2.2.dtsi | 7 ++++ - 2 files changed, 46 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi - create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi - -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -new file mode 100644 -index 000000000000..bd5bde989e8d ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -@@ -0,0 +1,39 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Engicam srl -+ * Copyright (c) 2020 Amarula Solutions -+ * Copyright (c) 2020 Amarula Solutions(India) -+ */ -+ -+/ { -+ vcc5v0_sys: vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; /* +5V */ -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+}; -+ -+&gmac { -+ clock_in_out = "output"; -+ phy-supply = <&vcc_3v3>; /* +3V3_SOM */ -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 50000 50000>; -+ snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ cap-sd-highspeed; -+ card-detect-delay = <800>; -+ vmmc-supply = <&vcc_3v3>; /* +3V3_SOM */ -+ vqmmc-supply = <&vcc_3v3>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-0 = <&uart2m1_xfer>; -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi -new file mode 100644 -index 000000000000..cb00988953e9 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi -@@ -0,0 +1,7 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Engicam srl -+ * Copyright (c) 2020 Amarula Solutions(India) -+ */ -+ -+#include "px30-engicam-common.dtsi" - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Michael Trimarchi -Date: Tue, 29 Sep 2020 14:02:13 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add Engicam PX30.Core SOM - -PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. - -General features: -- Rockchip PX30 -- Up to 2GB DDR4 -- eMMC 4 GB expandible -- rest of PX30 features - -PX30.Core needs to mount on top of Engicam baseboards for creating -complete platform boards. - -Possible baseboards are, -- EDIMM2.2 -- C.TOUCH 2.0 - -Add support for it. - -Signed-off-by: Jagan Teki -Signed-off-by: Michael Trimarchi -Link: https://lore.kernel.org/r/20200929083217.25406-4-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - .../dts/rockchip/px30-engicam-px30-core.dtsi | 232 ++++++++++++++++++ - 1 file changed, 232 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi - -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi -new file mode 100644 -index 000000000000..db22f776c68f ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi -@@ -0,0 +1,232 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd -+ * Copyright (c) 2020 Engicam srl -+ * Copyright (c) 2020 Amarula Solutons -+ * Copyright (c) 2020 Amarula Solutons(India) -+ */ -+ -+#include -+#include -+ -+/ { -+ compatible = "engicam,px30-core", "rockchip,px30"; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_arm>; -+}; -+ -+&emmc { -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ non-removable; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ #clock-cells = <1>; -+ clock-output-names = "rk808-clkout1", "rk808-clkout2"; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc5-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc5v0_sys>; -+ -+ regulators { -+ vdd_log: DCDC_REG1 { -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <950000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <950000>; -+ }; -+ }; -+ -+ vdd_arm: DCDC_REG2 { -+ regulator-name = "vdd_arm"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <950000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <950000>; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: DCDC_REG4 { -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc3v3_sys: DCDC_REG5 { -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc_1v0: LDO_REG1 { -+ regulator-name = "vcc_1v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ -+ vcc_1v8: LDO_REG2 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdd_1v0: LDO_REG3 { -+ regulator-name = "vdd_1v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1000000>; -+ }; -+ }; -+ -+ vcc3v0_pmu: LDO_REG4 { -+ regulator-name = "vcc3v0_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc5v0_host: SWITCH_REG2 { -+ regulator-name = "vcc5v0_host"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ }; -+ }; -+}; -+ -+&io_domains { -+ vccio1-supply = <&vcc_3v3>; -+ vccio2-supply = <&vcc_3v3>; -+ vccio3-supply = <&vcc_3v3>; -+ vccio4-supply = <&vcc_3v3>; -+ vccio5-supply = <&vcc_3v3>; -+ vccio6-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ pmic { -+ pmic_int: pmic_int { -+ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmuio1-supply = <&vcc_3v3>; -+ pmuio2-supply = <&vcc_3v3>; -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <1>; -+ status = "okay"; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Tue, 29 Sep 2020 14:02:14 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add Engicam PX30.Core EDIMM2.2 Starter - Kit - -PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. - -EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive -Evaluation Board from Engicam. - -PX30.Core needs to mount on top of this Evaluation board for -creating complete PX30.Core EDIMM2.2 Starter Kit. - -Add support for it. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20200929083217.25406-5-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../px30-engicam-px30-core-edimm2.2.dts | 21 +++++++++++++++++++ - 2 files changed, 22 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index 28b26a874313..abf9dc621314 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -1,5 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts -new file mode 100644 -index 000000000000..e54d1e480daa ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts -@@ -0,0 +1,21 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd -+ * Copyright (c) 2020 Engicam srl -+ * Copyright (c) 2020 Amarula Solutions(India) -+ */ -+ -+/dts-v1/; -+#include "px30.dtsi" -+#include "px30-engicam-edimm2.2.dtsi" -+#include "px30-engicam-px30-core.dtsi" -+ -+/ { -+ model = "Engicam PX30.Core EDIMM2.2 Starter Kit"; -+ compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core", -+ "rockchip,px30"; -+ -+ chosen { -+ stdout-path = "serial2:115200n8"; -+ }; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Tue, 29 Sep 2020 14:02:15 +0530 -Subject: [PATCH] dt-bindings: arm: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 - -PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. - -C.TOUCH 2.0 is a general purpose carrier board with capacitive -touch interface support. - -PX30.Core needs to mount on top of this Carrier board for creating -complete PX30.Core C.TOUCH 2.0 board. - -Add bindings for it. - -Signed-off-by: Jagan Teki -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20200929083217.25406-6-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index cef95eb26ca6..37fd456170d2 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -70,6 +70,12 @@ properties: - - const: elgin,rv1108-r1 - - const: rockchip,rv1108 - -+ - description: Engicam PX30.Core C.TOUCH 2.0 -+ items: -+ - const: engicam,px30-core-ctouch2 -+ - const: engicam,px30-core -+ - const: rockchip,px30 -+ - - description: Engicam PX30.Core EDIMM2.2 Starter Kit - items: - - const: engicam,px30-core-edimm2.2 - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Tue, 29 Sep 2020 14:02:16 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add Engicam C.TOUCH 2.0 - -Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose -carrier board with capacitive touch interface. - -Genaral features: -- TFT 10.1" industrial, 1280x800 LVDS display -- Ethernet 10/100 -- Wifi/BT -- USB Type A/OTG -- Audio Out -- CAN -- LVDS panel connector - -SOM's like PX30.Core needs to mount on top of this Carrier board -for creating complete PX30.Core C.TOUCH 2.0 board. - -Add support for it. - -Signed-off-by: Jagan Teki -Signed-off-by: Michael Trimarchi -Link: https://lore.kernel.org/r/20200929083217.25406-7-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi | 8 ++++++++ - 1 file changed, 8 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi - -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi -new file mode 100644 -index 000000000000..58425b1e559f ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi -@@ -0,0 +1,8 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Engicam srl -+ * Copyright (c) 2020 Amarula Solutions -+ * Copyright (c) 2020 Amarula Solutions(India) -+ */ -+ -+#include "px30-engicam-common.dtsi" - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Tue, 29 Sep 2020 14:02:17 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 - -PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. - -C.TOUCH 2.0 is a general purpose carrier board with capacitive -touch interface support. - -PX30.Core needs to mount on top of this Carrier board for creating -complete PX30.Core C.TOUCH 2.0 board. - -Add support for it. - -Signed-off-by: Jagan Teki -Signed-off-by: Michael Trimarchi -Link: https://lore.kernel.org/r/20200929083217.25406-8-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../px30-engicam-px30-core-ctouch2.dts | 22 +++++++++++++++++++ - 2 files changed, 23 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index abf9dc621314..5a53979b7057 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -1,5 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts -new file mode 100644 -index 000000000000..5a0ecb8faecf ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2.dts -@@ -0,0 +1,22 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd -+ * Copyright (c) 2020 Engicam srl -+ * Copyright (c) 2020 Amarula Solutions -+ * Copyright (c) 2020 Amarula Solutions(India) -+ */ -+ -+/dts-v1/; -+#include "px30.dtsi" -+#include "px30-engicam-ctouch2.dtsi" -+#include "px30-engicam-px30-core.dtsi" -+ -+/ { -+ model = "Engicam PX30.Core C.TOUCH 2.0"; -+ compatible = "engicam,px30-core-ctouch2", "engicam,px30-core", -+ "rockchip,px30"; -+ -+ chosen { -+ stdout-path = "serial2:115200n8"; -+ }; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chen-Yu Tsai -Date: Thu, 26 Nov 2020 15:33:35 +0800 -Subject: [PATCH] arm64: dts: rockchip: Enable HDMI audio on rk3328-roc-cc - -The RK3328-ROC-CC already has HDMI display output enabled. Now that -audio for the HDMI controller is supported, it can be enabled as well. - -Enable the simple-audio-card, and the I2S interface the audio is fed -from. - -Signed-off-by: Chen-Yu Tsai -Link: https://lore.kernel.org/r/20201126073336.30794-3-wens@kernel.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -index b76282e704de..697fce709031 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -161,6 +161,10 @@ &hdmiphy { - status = "okay"; - }; - -+&hdmi_sound { -+ status = "okay"; -+}; -+ - &i2c1 { - status = "okay"; - -@@ -270,6 +274,10 @@ regulator-state-mem { - }; - }; - -+&i2s0 { -+ status = "okay"; -+}; -+ - &io_domains { - status = "okay"; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chen-Yu Tsai -Date: Thu, 26 Nov 2020 15:33:36 +0800 -Subject: [PATCH] arm64: dts: rockchip: Enable analog audio on rk3328-roc-cc - -Now that driver support for the RK3328's audio codec, and the plumbing -is defined at the SoC level, we can enable analog audio at the board -level. - -Enable analog audio by enabling the codec and the I2S interface -connected and the simple-audio-card that binds them together. - -Signed-off-by: Chen-Yu Tsai -Link: https://lore.kernel.org/r/20201126073336.30794-4-wens@kernel.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -index 697fce709031..19959bfba451 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -104,6 +104,14 @@ user_led: led-1 { - }; - }; - -+&analog_sound { -+ status = "okay"; -+}; -+ -+&codec { -+ status = "okay"; -+}; -+ - &cpu0 { - cpu-supply = <&vdd_arm>; - }; -@@ -278,6 +286,10 @@ &i2s0 { - status = "okay"; - }; - -+&i2s1 { -+ status = "okay"; -+}; -+ - &io_domains { - status = "okay"; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Mon, 16 Nov 2020 14:23:11 +0100 -Subject: [PATCH] arm64: dts: rockchip: rename sdhci nodename to mmc on rk3399 - -A test with the command below gives for example this error: - -/arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml: -sdhci@fe330000: $nodename:0: 'sdhci@fe330000' -does not match '^mmc(@.*)?$' - -Fix it by renaming sdhci to mmc. - -make ARCH=arm64 dtbs_check -DT_SCHEMA_FILES=Documentation/devicetree/bindings/ -mmc/arasan,sdhci.yaml - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20201116132311.8318-1-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 7e69603fb41c..4d9a2ea3e6bf 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -331,7 +331,7 @@ sdmmc: mmc@fe320000 { - status = "disabled"; - }; - -- sdhci: sdhci@fe330000 { -+ sdhci: mmc@fe330000 { - compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; - reg = <0x0 0xfe330000 0x0 0x10000>; - interrupts = ; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 9 Nov 2020 23:40:09 +0530 -Subject: [PATCH] arm64: dts: rockchip: Enable USB Host, OTG on px30-enagicam - -Engicam EDIMM2.2 and C.Touch 2.0 Kits support USB Host -and OTG ports. - -Add support to enable USB on these kits while mounting -px30-core SOM. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-2-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - .../dts/rockchip/px30-engicam-common.dtsi | 24 +++++++++++++++++++ - 1 file changed, 24 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -index bd5bde989e8d..fbbdbb0a40af 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -@@ -33,7 +33,31 @@ &sdmmc { - status = "okay"; - }; - -+&u2phy { -+ status = "okay"; -+ -+ u2phy_host: host-port { -+ status = "okay"; -+ }; -+ -+ u2phy_otg: otg-port { -+ status = "okay"; -+ }; -+}; -+ - &uart2 { - pinctrl-0 = <&uart2m1_xfer>; - status = "okay"; - }; -+ -+&usb20_otg { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 9 Nov 2020 23:40:10 +0530 -Subject: [PATCH] arm64: dts: rockchip: Enable LVDS panel on - px30-engicam-edimm2.2 - -Engicam PX30.Core EDIMM2.2 developement Kit has on board 10" LVDS -panel from yes-optoelectronics. - -This patch adds panel enablement nodes on respective dts(i) files. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-3-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - .../dts/rockchip/px30-engicam-common.dtsi | 4 ++ - .../dts/rockchip/px30-engicam-edimm2.2.dtsi | 59 +++++++++++++++++++ - .../dts/rockchip/px30-engicam-px30-core.dtsi | 5 ++ - 3 files changed, 68 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -index fbbdbb0a40af..8fdd7ff2fdf9 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -@@ -25,6 +25,10 @@ &gmac { - status = "okay"; - }; - -+&pwm0 { -+ status = "okay"; -+}; -+ - &sdmmc { - cap-sd-highspeed; - card-detect-delay = <800>; -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi -index cb00988953e9..449b8eb6454e 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-edimm2.2.dtsi -@@ -5,3 +5,62 @@ - */ - - #include "px30-engicam-common.dtsi" -+ -+/ { -+ backlight: backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm0 0 25000 0>; -+ }; -+ -+ panel { -+ compatible = "yes-optoelectronics,ytc700tlag-05-201c"; -+ backlight = <&backlight>; -+ data-mapping = "vesa-24"; -+ power-supply = <&vcc3v3_lcd>; -+ -+ port { -+ panel_in_lvds: endpoint { -+ remote-endpoint = <&lvds_out_panel>; -+ }; -+ }; -+ }; -+}; -+ -+&display_subsystem { -+ status = "okay"; -+}; -+ -+&dsi_dphy { -+ status = "okay"; -+}; -+ -+/* LVDS_B(secondary) */ -+&lvds { -+ status = "okay"; -+ -+ ports { -+ port@1 { -+ reg = <1>; -+ -+ lvds_out_panel: endpoint { -+ remote-endpoint = <&panel_in_lvds>; -+ }; -+ }; -+ }; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi -index db22f776c68f..cdacd3483600 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core.dtsi -@@ -192,6 +192,11 @@ regulator-state-mem { - }; - }; - -+ vcc3v3_lcd: SWITCH_REG1 { -+ regulator-boot-on; -+ regulator-name = "vcc3v3_lcd"; -+ }; -+ - vcc5v0_host: SWITCH_REG2 { - regulator-name = "vcc5v0_host"; - regulator-always-on; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 9 Nov 2020 23:40:11 +0530 -Subject: [PATCH] dt-bindings: arm: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 - 10.1" OF - -PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. - -C.TOUCH 2.0 is a general purpose carrier board with capacitive -touch interface support. - -10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. - -PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged -10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. - -Add bindings for it. - -Acked-by: Rob Herring -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-4-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index 37fd456170d2..ef4544ad6f82 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -76,6 +76,12 @@ properties: - - const: engicam,px30-core - - const: rockchip,px30 - -+ - description: Engicam PX30.Core C.TOUCH 2.0 10.1" Open Frame -+ items: -+ - const: engicam,px30-core-ctouch2-of10 -+ - const: engicam,px30-core -+ - const: rockchip,px30 -+ - - description: Engicam PX30.Core EDIMM2.2 Starter Kit - items: - - const: engicam,px30-core-edimm2.2 - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Mon, 9 Nov 2020 23:40:12 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add Engicam PX30.Core C.TOUCH 2.0 10.1" - OF - -PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. - -C.TOUCH 2.0 is a general purpose carrier board with capacitive -touch interface support. - -10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. - -PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged -10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. - -Add support for it. - -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-5-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../px30-engicam-px30-core-ctouch2-of10.dts | 77 +++++++++++++++++++ - 2 files changed, 78 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index 5a53979b7057..1ab55a124a87 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -1,6 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0 - dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts -new file mode 100644 -index 000000000000..47aa30505a42 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-ctouch2-of10.dts -@@ -0,0 +1,77 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd -+ * Copyright (c) 2020 Engicam srl -+ * Copyright (c) 2020 Amarula Solutions(India) -+ */ -+ -+/dts-v1/; -+#include "px30.dtsi" -+#include "px30-engicam-ctouch2.dtsi" -+#include "px30-engicam-px30-core.dtsi" -+ -+/ { -+ model = "Engicam PX30.Core C.TOUCH 2.0 10.1\" Open Frame"; -+ compatible = "engicam,px30-core-ctouch2-of10", "engicam,px30-core", -+ "rockchip,px30"; -+ -+ backlight: backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm0 0 25000 0>; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:115200n8"; -+ }; -+ -+ panel { -+ compatible = "ampire,am-1280800n3tzqw-t00h"; -+ backlight = <&backlight>; -+ power-supply = <&vcc3v3_lcd>; -+ data-mapping = "vesa-24"; -+ -+ port { -+ panel_in_lvds: endpoint { -+ remote-endpoint = <&lvds_out_panel>; -+ }; -+ }; -+ }; -+}; -+ -+&display_subsystem { -+ status = "okay"; -+}; -+ -+&dsi_dphy { -+ status = "okay"; -+}; -+ -+&lvds { -+ status = "okay"; -+ -+ ports { -+ port@1 { -+ reg = <1>; -+ -+ lvds_out_panel: endpoint { -+ remote-endpoint = <&panel_in_lvds>; -+ }; -+ }; -+ }; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Suniel Mahesh -Date: Mon, 9 Nov 2020 23:40:13 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add WiFi support on px30-engicam - -Engicam PX30 carrier boards like EDIMM2.2 and C.TOUCH2.0 have -an onboard Sterling-LWD Wifi/BT chip based on BCM43430 connected -on the SDIO bus. - -The SDIO power sequnce is connacted with exteernal 32KHz oscillator -and it require 3V3 regulator input. - -This patch adds WiFi enablement nodes for these respective boards. - -Signed-off-by: Michael Trimarchi -Signed-off-by: Suniel Mahesh -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-6-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - .../dts/rockchip/px30-engicam-common.dtsi | 45 +++++++++++++++++++ - .../dts/rockchip/px30-engicam-ctouch2.dtsi | 12 +++++ - .../px30-engicam-px30-core-edimm2.2.dts | 12 +++++ - 3 files changed, 69 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -index 8fdd7ff2fdf9..0e1a93ec3234 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -@@ -14,6 +14,51 @@ vcc5v0_sys: vcc5v0-sys { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&xin32k>; -+ clock-names = "ext_clock"; -+ post-power-on-delay-ms = <80>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_enable_h>; -+ }; -+ -+ vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_rf_aux_mod"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ xin32k: xin32k { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "xin32k"; -+ }; -+}; -+ -+&sdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ bus-width = <4>; -+ clock-frequency = <50000000>; -+ cap-sdio-irq; -+ cap-sd-highspeed; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ sd-uhs-sdr104; -+ status = "okay"; -+ -+ brcmf: wifi@1 { -+ compatible = "brcm,bcm4329-fmac"; -+ reg = <1>; -+ }; - }; - - &gmac { -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi -index 58425b1e559f..d5708779c285 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi -@@ -6,3 +6,15 @@ - */ - - #include "px30-engicam-common.dtsi" -+ -+&pinctrl { -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&sdio_pwrseq { -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts -index e54d1e480daa..913444548b59 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts -@@ -19,3 +19,15 @@ chosen { - stdout-path = "serial2:115200n8"; - }; - }; -+ -+&pinctrl { -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&sdio_pwrseq { -+ reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Suniel Mahesh -Date: Mon, 9 Nov 2020 23:40:14 +0530 -Subject: [PATCH] arm64: dts: rockchip: Add BT support on px30-engicam - -Engicam PX30 carrier boards like EDIMM2.2 and C.TOUCH2.0 have -an onboard Sterling-LWD Wifi/BT chip based on BCM43430 connected -on the UART bus. - -UART bus on the design routed via USB to UART CP20x bridge. This -bridge powered from 3V3 regualtor gpio. - -This patch adds BT enablement nodes for these respective boards. - -Signed-off-by: Michael Trimarchi -Signed-off-by: Suniel Mahesh -Signed-off-by: Jagan Teki -Link: https://lore.kernel.org/r/20201109181017.206834-7-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - .../arm64/boot/dts/rockchip/px30-engicam-common.dtsi | 12 ++++++++++++ - .../boot/dts/rockchip/px30-engicam-ctouch2.dtsi | 10 ++++++++++ - .../dts/rockchip/px30-engicam-px30-core-edimm2.2.dts | 10 ++++++++++ - 3 files changed, 32 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -index 0e1a93ec3234..08b0b9fbcbc9 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-common.dtsi -@@ -24,6 +24,18 @@ sdio_pwrseq: sdio-pwrseq { - pinctrl-0 = <&wifi_enable_h>; - }; - -+ vcc3v3_btreg: vcc3v3-btreg { -+ compatible = "regulator-gpio"; -+ enable-active-high; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_enable_h>; -+ regulator-name = "btreg-gpio-supply"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ states = <3300000 0x0>; -+ }; -+ - vcc3v3_rf_aux_mod: vcc3v3-rf-aux-mod { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_rf_aux_mod"; -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi -index d5708779c285..bf10a3d29fca 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi -@@ -8,6 +8,12 @@ - #include "px30-engicam-common.dtsi" - - &pinctrl { -+ bt { -+ bt_enable_h: bt-enable-h { -+ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -@@ -18,3 +24,7 @@ wifi_enable_h: wifi-enable-h { - &sdio_pwrseq { - reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; - }; -+ -+&vcc3v3_btreg { -+ enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts -index 913444548b59..d759478e1c84 100644 ---- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts -+++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts -@@ -21,6 +21,12 @@ chosen { - }; - - &pinctrl { -+ bt { -+ bt_enable_h: bt-enable-h { -+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - sdio-pwrseq { - wifi_enable_h: wifi-enable-h { - rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; -@@ -31,3 +37,7 @@ wifi_enable_h: wifi-enable-h { - &sdio_pwrseq { - reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; - }; -+ -+&vcc3v3_btreg { -+ enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alexis Ballier -Date: Thu, 22 Oct 2020 13:35:32 +0200 -Subject: [PATCH] arm64: dts: rockchip: Properly define the type C connector on - rk3399-orangepi - -Tested: -- USB3 Gigabit adapter -- USB2 mass storage - -The wiring is the same as the pinebook pro according to the schematics, -thus this patch is heavily based on its dts. - -Signed-off-by: Alexis Ballier -Cc: devicetree@vger.kernel.org -Cc: Heiko Stuebner -Cc: linux-arm-kernel@lists.infradead.org -Cc: linux-rockchip@lists.infradead.org -Cc: linux-kernel@vger.kernel.org -Link: https://lore.kernel.org/r/20201022113532.18470-1-aballier@gentoo.org -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3399-orangepi.dts | 62 ++++++++++++++++++- - 1 file changed, 61 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts -index 6163ae8063a7..ad7c4d00888f 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts -@@ -7,6 +7,7 @@ - - #include "dt-bindings/pwm/pwm.h" - #include "dt-bindings/input/input.h" -+#include "dt-bindings/usb/pd.h" - #include "rk3399.dtsi" - #include "rk3399-opp.dtsi" - -@@ -531,6 +532,43 @@ fusb302@22 { - pinctrl-names = "default"; - pinctrl-0 = <&chg_cc_int_l>; - vbus-supply = <&vbus_typec>; -+ -+ typec_con: connector { -+ compatible = "usb-c-connector"; -+ data-role = "host"; -+ label = "USB-C"; -+ op-sink-microwatt = <1000000>; -+ power-role = "dual"; -+ sink-pdos = -+ ; -+ source-pdos = -+ ; -+ try-power-role = "sink"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ typec_hs: endpoint { -+ remote-endpoint = <&u2phy0_typec_hs>; -+ }; -+ }; -+ port@1 { -+ reg = <1>; -+ typec_ss: endpoint { -+ remote-endpoint = <&tcphy0_typec_ss>; -+ }; -+ }; -+ port@2 { -+ reg = <2>; -+ typec_dp: endpoint { -+ remote-endpoint = <&tcphy0_typec_dp>; -+ }; -+ }; -+ }; -+ }; - }; - }; - -@@ -717,6 +755,22 @@ &tcphy0 { - status = "okay"; - }; - -+&tcphy0_dp { -+ port { -+ tcphy0_typec_dp: endpoint { -+ remote-endpoint = <&typec_dp>; -+ }; -+ }; -+}; -+ -+&tcphy0_usb3 { -+ port { -+ tcphy0_typec_ss: endpoint { -+ remote-endpoint = <&typec_ss>; -+ }; -+ }; -+}; -+ - &tcphy1 { - status = "okay"; - }; -@@ -739,6 +793,12 @@ u2phy0_host: host-port { - phy-supply = <&vcc5v0_host>; - status = "okay"; - }; -+ -+ port { -+ u2phy0_typec_hs: endpoint { -+ remote-endpoint = <&typec_hs>; -+ }; -+ }; - }; - - &u2phy1 { -@@ -799,7 +859,7 @@ &usbdrd3_0 { - - &usbdrd_dwc3_0 { - status = "okay"; -- dr_mode = "otg"; -+ dr_mode = "host"; - }; - - &usbdrd3_1 { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Shunqian Zheng -Date: Tue, 20 Oct 2020 16:38:49 -0300 -Subject: [PATCH] arm64: dts: rockchip: add isp0 node for rk3399 - -RK3399 has two ISPs, but only isp0 was tested. -Add isp0 node in rk3399 dtsi - -Verified with: -make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/media/rockchip-isp1.yaml - -Signed-off-by: Shunqian Zheng -Signed-off-by: Jacob Chen -Signed-off-by: Helen Koike -Link: https://lore.kernel.org/r/20201020193850.1460644-9-helen.koike@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26 ++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 4d9a2ea3e6bf..2551b238b97c 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1725,6 +1725,32 @@ vopb_mmu: iommu@ff903f00 { - status = "disabled"; - }; - -+ isp0: isp0@ff910000 { -+ compatible = "rockchip,rk3399-cif-isp"; -+ reg = <0x0 0xff910000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cru SCLK_ISP0>, -+ <&cru ACLK_ISP0_WRAPPER>, -+ <&cru HCLK_ISP0_WRAPPER>; -+ clock-names = "isp", "aclk", "hclk"; -+ iommus = <&isp0_mmu>; -+ phys = <&mipi_dphy_rx0>; -+ phy-names = "dphy"; -+ power-domains = <&power RK3399_PD_ISP0>; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ }; -+ - isp0_mmu: iommu@ff914000 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Eddie Cai -Date: Tue, 20 Oct 2020 16:38:50 -0300 -Subject: [PATCH] arm64: dts: rockchip: add isp and sensors for Scarlet - -Enable ISP and camera sensor ov2685 and ov5695 for Scarlet Chromebook - -Verified with: - make ARCH=arm64 dtbs_check - -Signed-off-by: Shunqian Zheng -Signed-off-by: Eddie Cai -Signed-off-by: Tomasz Figa -Signed-off-by: Helen Koike -Reviewed-by: Tomasz Figa -Link: https://lore.kernel.org/r/20201020193850.1460644-10-helen.koike@collabora.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 74 +++++++++++++++++++ - 1 file changed, 74 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi -index 60cd1c18cd4e..beee5fbb3443 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi -@@ -296,6 +296,52 @@ camera: &i2c7 { - - /* 24M mclk is shared between world and user cameras */ - pinctrl-0 = <&i2c7_xfer &test_clkout1>; -+ -+ /* Rear-facing camera */ -+ wcam: camera@36 { -+ compatible = "ovti,ov5695"; -+ reg = <0x36>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wcam_rst>; -+ -+ clocks = <&cru SCLK_TESTCLKOUT1>; -+ clock-names = "xvclk"; -+ -+ avdd-supply = <&pp2800_cam>; -+ dvdd-supply = <&pp1250_cam>; -+ dovdd-supply = <&pp1800_s0>; -+ reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; -+ -+ port { -+ wcam_out: endpoint { -+ remote-endpoint = <&mipi_in_wcam>; -+ data-lanes = <1 2>; -+ }; -+ }; -+ }; -+ -+ /* Front-facing camera */ -+ ucam: camera@3c { -+ compatible = "ovti,ov2685"; -+ reg = <0x3c>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ucam_rst>; -+ -+ clocks = <&cru SCLK_TESTCLKOUT1>; -+ clock-names = "xvclk"; -+ -+ avdd-supply = <&pp2800_cam>; -+ dovdd-supply = <&pp1800_s0>; -+ dvdd-supply = <&pp1800_s0>; -+ reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; -+ -+ port { -+ ucam_out: endpoint { -+ remote-endpoint = <&mipi_in_ucam>; -+ data-lanes = <1>; -+ }; -+ }; -+ }; - }; - - &cdn_dp { -@@ -353,10 +399,38 @@ &io_domains { - gpio1830-supply = <&pp1800_s0>; /* APIO4_VDD; 4c 4d */ - }; - -+&isp0 { -+ status = "okay"; -+ -+ ports { -+ port@0 { -+ mipi_in_wcam: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&wcam_out>; -+ data-lanes = <1 2>; -+ }; -+ -+ mipi_in_ucam: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&ucam_out>; -+ data-lanes = <1>; -+ }; -+ }; -+ }; -+}; -+ -+&isp0_mmu { -+ status = "okay"; -+}; -+ - &max98357a { - sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - }; - -+&mipi_dphy_rx0 { -+ status = "okay"; -+}; -+ - &mipi_dsi { - status = "okay"; - clock-master; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Vicente Bergas -Date: Tue, 1 Dec 2020 16:41:30 +0100 -Subject: [PATCH] arm64: dts: rockchip: fix supplies on rk3399-rock-pi-4 - -Based on the board schematics at -https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf -on page 18: -vcc_lan is not controllable by software, it is just an analog LC filter. -Because of this, it can not be turned off-in-suspend. - -and on page 17: -vcc_cam and vcc_mipi are not voltage regulators, they are just switches. -So, the voltage range is not applicable. -This silences an error message about not being able to adjust the voltage. - -Signed-off-by: Vicente Bergas -Link: https://lore.kernel.org/r/20201201154132.1286-2-vicencb@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 8 -------- - 1 file changed, 8 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -index 678a336010bf..06df2397bbb4 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -111,10 +111,6 @@ vcc_lan: vcc3v3-phy-regulator { - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; -- -- regulator-state-mem { -- regulator-off-in-suspend; -- }; - }; - - vdd_log: vdd-log { -@@ -362,8 +358,6 @@ vcc_cam: SWITCH_REG1 { - regulator-name = "vcc_cam"; - regulator-always-on; - regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; -@@ -373,8 +367,6 @@ vcc_mipi: SWITCH_REG2 { - regulator-name = "vcc_mipi"; - regulator-always-on; - regulator-boot-on; -- regulator-min-microvolt = <3300000>; -- regulator-max-microvolt = <3300000>; - regulator-state-mem { - regulator-off-in-suspend; - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Vicente Bergas -Date: Tue, 1 Dec 2020 16:41:31 +0100 -Subject: [PATCH] arm64: dts: rockchip: fix I2S conflict on rk3399-rock-pi-4 - -Based on the board schematics at -https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf -on page 14: -Only two channels of I2S are connected and the extra -I2S pins are in conflict with other functions like USB power. - -Signed-off-by: Vicente Bergas -Link: https://lore.kernel.org/r/20201201154132.1286-3-vicencb@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -index 06df2397bbb4..63b029a543c1 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -432,8 +432,9 @@ &i2c4 { - }; - - &i2s0 { -- rockchip,playback-channels = <8>; -- rockchip,capture-channels = <8>; -+ pinctrl-0 = <&i2s0_2ch_bus>; -+ rockchip,capture-channels = <2>; -+ rockchip,playback-channels = <2>; - status = "okay"; - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Vicente Bergas -Date: Tue, 1 Dec 2020 16:41:32 +0100 -Subject: [PATCH] arm64: dts: rockchip: use USB host by default on - rk3399-rock-pi-4 - -Based on the board schematics at -https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf -on page 19 there is an USB Type-A receptacle being used as an USB-OTG port. - -But the Type-A connector is not valid for OTG operation, for this reason -there is a switch to select host or device role. -This is non-compliant and error prone because switching is manual. -So, use host mode as it corresponds for a Type-A receptacle. - -Signed-off-by: Vicente Bergas -Link: https://lore.kernel.org/r/20201201154132.1286-4-vicencb@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -index 63b029a543c1..fb7599f07af4 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -673,7 +673,7 @@ &usbdrd3_0 { - - &usbdrd_dwc3_0 { - status = "okay"; -- dr_mode = "otg"; -+ dr_mode = "host"; - }; - - &usbdrd3_1 { diff --git a/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-5.12.patch b/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-5.12.patch deleted file mode 100644 index 00c2e2fa24..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-5.12.patch +++ /dev/null @@ -1,662 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Demetris Ierokipides -Date: Fri, 8 Jan 2021 17:10:35 +0200 -Subject: [PATCH] ARM: dts: rockchip: add gpu node to rk3288-miqi - -Add the Mali GPU node to the MiQi device-tree. - -Signed-off-by: Demetris Ierokipides -Link: https://lore.kernel.org/r/20210108151036.36434-2-ierokipides.dem@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288-miqi.dts | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts -index cf54d5ffff2f..713f55e143c6 100644 ---- a/arch/arm/boot/dts/rk3288-miqi.dts -+++ b/arch/arm/boot/dts/rk3288-miqi.dts -@@ -123,6 +123,11 @@ &gmac { - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ - &hdmi { - ddc-i2c-bus = <&i2c5>; - status = "okay"; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Sat, 19 Dec 2020 22:05:00 +0100 -Subject: [PATCH] arm64: dts: rockchip: assign a fixed index to mmc devices on - rk3328 boards - -Recently introduced async probe on mmc devices can shuffle block IDs. -Pin them to fixed values to ease booting in environments where UUIDs -are not practical. Use newly introduced aliases for mmcblk devices from [1]. - -[1] https://patchwork.kernel.org/patch/11747669/ - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20201219210500.3855-1-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 93c734d8a46c..17709faf651b 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -27,6 +27,9 @@ aliases { - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; -+ mmc0 = &sdmmc; -+ mmc1 = &sdio; -+ mmc2 = &emmc; - ethernet0 = &gmac2io; - ethernet1 = &gmac2phy; - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jagan Teki -Date: Fri, 31 Jul 2020 21:33:24 +0530 -Subject: [PATCH] arm64: defconfig: Enable REGULATOR_MP8859 - -RK3399 boards like ROC-RK3399-PC is using MP8859 DC/DC converter -for 12V supply. - -roc-rk3399-pc initially used 12V fixed regulator for this supply, -but the below commit has switched to use MP8859. - -commit <1fc61ed04d309b0b8b3562acf701ab988eee12de> "arm64: dts: rockchip: -Enable mp8859 regulator on rk3399-roc-pc" - -So, enable by default on the defconfig. - -Signed-off-by: Jagan Teki -Tested-by: Suniel Mahesh -Link: https://lore.kernel.org/r/20200731160324.142097-1-jagan@amarulasolutions.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/configs/defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index 699c204090b8..9365213589bb 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -588,6 +588,7 @@ CONFIG_REGULATOR_HI6421V530=y - CONFIG_REGULATOR_HI655X=y - CONFIG_REGULATOR_MAX77620=y - CONFIG_REGULATOR_MAX8973=y -+CONFIG_REGULATOR_MP8859=y - CONFIG_REGULATOR_PCA9450=y - CONFIG_REGULATOR_PFUZE100=y - CONFIG_REGULATOR_PWM=y - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Sun, 6 Dec 2020 11:37:08 +0100 -Subject: [PATCH] ARM: dts: rockchip: add QoS register compatibles for - rk3066/rk3188 - -With the conversion of syscon.yaml minItems for compatibles -was set to 2. Current Rockchip dtsi files only use "syscon" for -QoS registers. Add Rockchip QoS compatibles for rk3066/rk3188 -to reduce notifications produced with: - -make ARCH=arm dtbs_check -DT_SCHEMA_FILES=Documentation/devicetree/bindings/mfd/syscon.yaml - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20201206103711.7465-1-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3xxx.dtsi | 16 ++++++++-------- - 1 file changed, 8 insertions(+), 8 deletions(-) - -diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi -index 859a7477909f..49bcdf46d03c 100644 ---- a/arch/arm/boot/dts/rk3xxx.dtsi -+++ b/arch/arm/boot/dts/rk3xxx.dtsi -@@ -151,42 +151,42 @@ uart1: serial@10126000 { - }; - - qos_gpu: qos@1012d000 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012d000 0x20>; - }; - - qos_vpu: qos@1012e000 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012e000 0x20>; - }; - - qos_lcdc0: qos@1012f000 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f000 0x20>; - }; - - qos_cif0: qos@1012f080 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f080 0x20>; - }; - - qos_ipp: qos@1012f100 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f100 0x20>; - }; - - qos_lcdc1: qos@1012f180 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f180 0x20>; - }; - - qos_cif1: qos@1012f200 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f200 0x20>; - }; - - qos_rga: qos@1012f280 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3066-qos", "syscon"; - reg = <0x1012f280 0x20>; - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Sun, 6 Dec 2020 11:37:09 +0100 -Subject: [PATCH] ARM: dts: rockchip: add QoS register compatibles for rk3288 - -With the conversion of syscon.yaml minItems for compatibles -was set to 2. Current Rockchip dtsi files only use "syscon" for -QoS registers. Add Rockchip QoS compatibles for rk3288 -to reduce notifications produced with: - -make ARCH=arm dtbs_check -DT_SCHEMA_FILES=Documentation/devicetree/bindings/mfd/syscon.yaml - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20201206103711.7465-2-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm/boot/dts/rk3288.dtsi | 28 ++++++++++++++-------------- - 1 file changed, 14 insertions(+), 14 deletions(-) - -diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 68d5a58cfe88..01ea1f170f77 100644 ---- a/arch/arm/boot/dts/rk3288.dtsi -+++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1329,72 +1329,72 @@ opp-600000000 { - }; - - qos_gpu_r: qos@ffaa0000 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaa0000 0x0 0x20>; - }; - - qos_gpu_w: qos@ffaa0080 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaa0080 0x0 0x20>; - }; - - qos_vio1_vop: qos@ffad0000 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0000 0x0 0x20>; - }; - - qos_vio1_isp_w0: qos@ffad0100 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0100 0x0 0x20>; - }; - - qos_vio1_isp_w1: qos@ffad0180 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0180 0x0 0x20>; - }; - - qos_vio0_vop: qos@ffad0400 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0400 0x0 0x20>; - }; - - qos_vio0_vip: qos@ffad0480 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0480 0x0 0x20>; - }; - - qos_vio0_iep: qos@ffad0500 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0500 0x0 0x20>; - }; - - qos_vio2_rga_r: qos@ffad0800 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0800 0x0 0x20>; - }; - - qos_vio2_rga_w: qos@ffad0880 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0880 0x0 0x20>; - }; - - qos_vio1_isp_r: qos@ffad0900 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffad0900 0x0 0x20>; - }; - - qos_video: qos@ffae0000 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffae0000 0x0 0x20>; - }; - - qos_hevc_r: qos@ffaf0000 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaf0000 0x0 0x20>; - }; - - qos_hevc_w: qos@ffaf0080 { -- compatible = "syscon"; -+ compatible = "rockchip,rk3288-qos", "syscon"; - reg = <0x0 0xffaf0080 0x0 0x20>; - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Sun, 6 Dec 2020 11:37:11 +0100 -Subject: [PATCH] arm64: dts: rockchip: add QoS register compatibles for px30 - -With the conversion of syscon.yaml minItems for compatibles -was set to 2. Current Rockchip dtsi files only use "syscon" for -QoS registers. Add Rockchip QoS compatibles for px30 -to reduce notifications produced with: - -make ARCH=arm64 dtbs_check -DT_SCHEMA_FILES=Documentation/devicetree/bindings/mfd/syscon.yaml - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20201206103711.7465-4-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/px30.dtsi | 40 +++++++++++++------------- - 1 file changed, 20 insertions(+), 20 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi -index 64193292d26c..d8b673b486c9 100644 ---- a/arch/arm64/boot/dts/rockchip/px30.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi -@@ -1107,102 +1107,102 @@ vopl_mmu: iommu@ff470f00 { - }; - - qos_gmac: qos@ff518000 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff518000 0x0 0x20>; - }; - - qos_gpu: qos@ff520000 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff520000 0x0 0x20>; - }; - - qos_sdmmc: qos@ff52c000 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff52c000 0x0 0x20>; - }; - - qos_emmc: qos@ff538000 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff538000 0x0 0x20>; - }; - - qos_nand: qos@ff538080 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff538080 0x0 0x20>; - }; - - qos_sdio: qos@ff538100 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff538100 0x0 0x20>; - }; - - qos_sfc: qos@ff538180 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff538180 0x0 0x20>; - }; - - qos_usb_host: qos@ff540000 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff540000 0x0 0x20>; - }; - - qos_usb_otg: qos@ff540080 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff540080 0x0 0x20>; - }; - - qos_isp_128: qos@ff548000 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff548000 0x0 0x20>; - }; - - qos_isp_rd: qos@ff548080 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff548080 0x0 0x20>; - }; - - qos_isp_wr: qos@ff548100 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff548100 0x0 0x20>; - }; - - qos_isp_m1: qos@ff548180 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff548180 0x0 0x20>; - }; - - qos_vip: qos@ff548200 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff548200 0x0 0x20>; - }; - - qos_rga_rd: qos@ff550000 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff550000 0x0 0x20>; - }; - - qos_rga_wr: qos@ff550080 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff550080 0x0 0x20>; - }; - - qos_vop_m0: qos@ff550100 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff550100 0x0 0x20>; - }; - - qos_vop_m1: qos@ff550180 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff550180 0x0 0x20>; - }; - - qos_vpu: qos@ff558000 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff558000 0x0 0x20>; - }; - - qos_vpu_r128: qos@ff558080 { -- compatible = "syscon"; -+ compatible = "rockchip,px30-qos", "syscon"; - reg = <0x0 0xff558080 0x0 0x20>; - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Katsuhiro Suzuki -Date: Mon, 3 Aug 2020 00:42:31 +0900 -Subject: [PATCH] arm64: dts: rockchip: enable HDMI sound nodes for - rk3328-rock64 - -This patch enables HDMI sound (I2S0) and Analog sound (I2S1) which -are defined in rk3328.dtsi, and replace SPDIF nodes. - -We can use SPDIF pass-through with suitable ALSA settings and on -mpv or other media players. - - Settings: https://github.com/LibreELEC/LibreELEC.tv/blob/master/projects/Rockchip/filesystem/usr/share/alsa/cards/SPDIF.conf - - Ex.: mpv foo.ac3 --audio-spdif=ac3 --audio-device='alsa/SPDIF.pcm.iec958.0:SPDIF' - -[Why use simple-audio-card for SPDIF?] - -For newly adding nodes, ASoC guys recommend to use audio-graph-card. -But all other sound nodes for rk3328 have already been defined by -simple-audio-card. In this time, I chose for consistent sound nodes. - -[DMA allocation problem] - -After this patch is applied, UART2 will fail to allocate DMA resources -but UART driver can work fine without DMA. - -This error is related to the DMAC of rk3328 (pl330 or compatible). -DMAC connected to 16 DMA sources. Each sources have ID number that is -called 'Req number' in rk3328 TRM. After this patch is applied total 7 -of DMA sources will be activated as follows: - -| Req number | Source | Required | -| | | channels | -|------------+--------+-----------| -| 8, 9 | SPI0 | 2ch | -| 11, 12 | I2S0 | 2ch | -| 14, 15 | I2S1 | 2ch | -| 10 | SPDIF | 1ch | -|------------+--------+-----------| -| | Total | 7ch | -|------------+--------+-----------| -| 6, 7 | UART2 | 2ch | -> cannot get DMA channels - -Due to rk3328 DMAC specification we can use max 8 channels at same -time. If SPI0/I2S0/I2S1/SPDIF will be activated by this patch, -required DMAC channels reach to 7. So the last two channels (for -UART2) cannot get DMA resources. - -Virt-dma mechanism for pl0330 DMAC driver is needed to fix this -problem. - -Signed-off-by: Katsuhiro Suzuki -Link: https://lore.kernel.org/r/20200802154231.2639186-1-katsuhiro@katsuster.net -Signed-off-by: Heiko Stuebner ---- - .../arm64/boot/dts/rockchip/rk3328-rock64.dts | 56 ++++++++----------- - 1 file changed, 24 insertions(+), 32 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -index 86cfb5c50a94..c984662043da 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -@@ -84,34 +84,32 @@ standby_led: led-1 { - }; - }; - -- sound { -- compatible = "audio-graph-card"; -- label = "rockchip,rk3328"; -- dais = <&i2s1_p0 -- &spdif_p0>; -+ spdif_sound: spdif-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "SPDIF"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&spdif>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&spdif_dit>; -+ }; - }; - -- spdif-dit { -+ spdif_dit: spdif-dit { - compatible = "linux,spdif-dit"; - #sound-dai-cells = <0>; -- -- port { -- dit_p0_0: endpoint { -- remote-endpoint = <&spdif_p0_0>; -- }; -- }; - }; - }; - -+&analog_sound { -+ status = "okay"; -+}; -+ - &codec { - mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; - status = "okay"; -- -- port@0 { -- codec_p0_0: endpoint { -- remote-endpoint = <&i2s1_p0_0>; -- }; -- }; - }; - - &cpu0 { -@@ -163,6 +161,10 @@ &hdmi { - status = "okay"; - }; - -+&hdmi_sound { -+ status = "okay"; -+}; -+ - &hdmiphy { - status = "okay"; - }; -@@ -278,16 +280,12 @@ regulator-state-mem { - }; - }; - --&i2s1 { -+&i2s0 { - status = "okay"; -+}; - -- i2s1_p0: port { -- i2s1_p0_0: endpoint { -- dai-format = "i2s"; -- mclk-fs = <256>; -- remote-endpoint = <&codec_p0_0>; -- }; -- }; -+&i2s1 { -+ status = "okay"; - }; - - &io_domains { -@@ -337,12 +335,6 @@ &sdmmc { - &spdif { - pinctrl-0 = <&spdifm0_tx>; - status = "okay"; -- -- spdif_p0: port { -- spdif_p0_0: endpoint { -- remote-endpoint = <&dit_p0_0>; -- }; -- }; - }; - - &spi0 { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Katsuhiro Suzuki -Date: Mon, 10 Aug 2020 18:16:19 +0900 -Subject: [PATCH] arm64: dts: rockchip: add SPDIF node for rk3399-rockpro64 - -This patch adds 'disabled' SPDIF sound node and related settings -for rk3399-rockpro64. - -There are 2 reasons: - - All RK3399 dma-bus channels have been already used by I2S0/1/2 - - RockPro64 does not have SPDIF optical nor coaxial connector, - just have 3pins - -Signed-off-by: Katsuhiro Suzuki -Link: https://lore.kernel.org/r/20200810091619.3170534-1-katsuhiro@katsuster.net -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3399-rockpro64.dtsi | 27 +++++++++++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -index 6e553ff47534..58097245994a 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -@@ -76,6 +76,23 @@ sound { - dais = <&i2s1_p0>; - }; - -+ sound-dit { -+ compatible = "audio-graph-card"; -+ label = "rockchip,rk3399"; -+ dais = <&spdif_p0>; -+ }; -+ -+ spdif-dit { -+ compatible = "linux,spdif-dit"; -+ #sound-dai-cells = <0>; -+ -+ port { -+ dit_p0_0: endpoint { -+ remote-endpoint = <&spdif_p0_0>; -+ }; -+ }; -+ }; -+ - vcc12v_dcin: vcc12v-dcin { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; -@@ -698,6 +715,16 @@ &sdhci { - status = "okay"; - }; - -+&spdif { -+ pinctrl-0 = <&spdif_bus_1>; -+ -+ spdif_p0: port { -+ spdif_p0_0: endpoint { -+ remote-endpoint = <&dit_p0_0>; -+ }; -+ }; -+}; -+ - &spi1 { - status = "okay"; - diff --git a/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch index aeabfcd4cb..4fe61149e1 100644 --- a/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch @@ -784,10 +784,11 @@ diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index ae86da0dc5bd..f5eb7de10128 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile -@@ -51,3 +51,4 @@ obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o +@@ -51,4 +51,5 @@ obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o obj-$(CONFIG_USB_DWC3_OF_SIMPLE) += dwc3-of-simple.o obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o + obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o +obj-$(CONFIG_USB_DWC3_ROCKCHIP_INNO) += dwc3-rockchip-inno.o diff --git a/drivers/usb/dwc3/dwc3-rockchip-inno.c b/drivers/usb/dwc3/dwc3-rockchip-inno.c new file mode 100644 diff --git a/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch index d1d06c89bd..d12a43215d 100644 --- a/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch @@ -107,7 +107,7 @@ index 71a6b7b0b057..f405dd72ad93 100644 { + struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); + - if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_SPS) { + if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) { const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; + unsigned int width, height; /* @@ -567,17 +567,6 @@ index 000000000000..a8123be0baa3 + - Y + - C + - Y -diff --git a/Documentation/userspace-api/media/v4l/yuv-formats.rst b/Documentation/userspace-api/media/v4l/yuv-formats.rst -index 4a05a105a9e6..e08e5dbdacea 100644 ---- a/Documentation/userspace-api/media/v4l/yuv-formats.rst -+++ b/Documentation/userspace-api/media/v4l/yuv-formats.rst -@@ -54,4 +54,6 @@ to brightness information. - pixfmt-nv16 - pixfmt-nv16m - pixfmt-nv24 -+ pixfmt-nv15 -+ pixfmt-nv20 - pixfmt-m420 diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c index 4102c373b48a..0caac755d303 100644 --- a/drivers/media/v4l2-core/v4l2-common.c diff --git a/projects/Rockchip/patches/linux/default/linux-0020-drm-from-5.11.patch b/projects/Rockchip/patches/linux/default/linux-0020-drm-from-5.11.patch deleted file mode 100644 index 3ff851bdf3..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-0020-drm-from-5.11.patch +++ /dev/null @@ -1,465 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Thomas Zimmermann -Date: Wed, 23 Sep 2020 12:21:51 +0200 -Subject: [PATCH] drm/rockchip: Convert to drm_gem_object_funcs -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -GEM object functions deprecate several similar callback interfaces in -struct drm_driver. This patch replaces the per-driver callbacks with -per-instance callbacks in rockchip. The only exception is gem_prime_mmap, -which is non-trivial to convert. - -v3: - * update documentation - -Signed-off-by: Thomas Zimmermann -Reviewed-by: Daniel Vetter -Acked-by: Christian König -Link: https://patchwork.freedesktop.org/patch/msgid/20200923102159.24084-15-tzimmermann@suse.de -(cherry picked from commit 0d590af3140d0f84c537a9ad252aecc780ed7aa5) ---- - drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 5 ----- - drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 12 +++++++++++- - 2 files changed, 11 insertions(+), 6 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -index 0f3eb392fe39..b7654f5e4225 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -212,15 +212,10 @@ static const struct file_operations rockchip_drm_driver_fops = { - static struct drm_driver rockchip_drm_driver = { - .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, - .lastclose = drm_fb_helper_lastclose, -- .gem_vm_ops = &drm_gem_cma_vm_ops, -- .gem_free_object_unlocked = rockchip_gem_free_object, - .dumb_create = rockchip_gem_dumb_create, - .prime_handle_to_fd = drm_gem_prime_handle_to_fd, - .prime_fd_to_handle = drm_gem_prime_fd_to_handle, -- .gem_prime_get_sg_table = rockchip_gem_prime_get_sg_table, - .gem_prime_import_sg_table = rockchip_gem_prime_import_sg_table, -- .gem_prime_vmap = rockchip_gem_prime_vmap, -- .gem_prime_vunmap = rockchip_gem_prime_vunmap, - .gem_prime_mmap = rockchip_gem_mmap_buf, - .fops = &rockchip_drm_driver_fops, - .name = DRIVER_NAME, -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c -index 62e5d0970525..1cf4631461c9 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c -@@ -295,6 +295,14 @@ static void rockchip_gem_release_object(struct rockchip_gem_object *rk_obj) - kfree(rk_obj); - } - -+static const struct drm_gem_object_funcs rockchip_gem_object_funcs = { -+ .free = rockchip_gem_free_object, -+ .get_sg_table = rockchip_gem_prime_get_sg_table, -+ .vmap = rockchip_gem_prime_vmap, -+ .vunmap = rockchip_gem_prime_vunmap, -+ .vm_ops = &drm_gem_cma_vm_ops, -+}; -+ - static struct rockchip_gem_object * - rockchip_gem_alloc_object(struct drm_device *drm, unsigned int size) - { -@@ -309,6 +317,8 @@ static struct rockchip_gem_object * - - obj = &rk_obj->base; - -+ obj->funcs = &rockchip_gem_object_funcs; -+ - drm_gem_object_init(drm, obj, size); - - return rk_obj; -@@ -337,7 +347,7 @@ rockchip_gem_create_object(struct drm_device *drm, unsigned int size, - } - - /* -- * rockchip_gem_free_object - (struct drm_driver)->gem_free_object_unlocked -+ * rockchip_gem_free_object - (struct drm_gem_object_funcs)->free - * callback function - */ - void rockchip_gem_free_object(struct drm_gem_object *obj) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Thomas Zimmermann -Date: Mon, 28 Sep 2020 10:16:43 +0200 -Subject: [PATCH] drm/rockchip: Include for - drm_gem_cm_vm_ops -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Include to get drm_gem_cma_vm_ops. Fallout -from the recent conversion to GEM object functions. - -Signed-off-by: Thomas Zimmermann -Reviewed-by: Sam Ravnborg -Reported-by: kernel test robot -Fixes: 0d590af3140d ("drm/rockchip: Convert to drm_gem_object_funcs") -Cc: Thomas Zimmermann -Cc: Daniel Vetter -Cc: Christian König -Cc: Sandy Huang -Cc: "Heiko Stübner" -Cc: dri-devel@lists.freedesktop.org -Cc: linux-arm-kernel@lists.infradead.org -Cc: linux-rockchip@lists.infradead.org -Link: https://patchwork.freedesktop.org/patch/msgid/20200928081643.8575-1-tzimmermann@suse.de -(cherry picked from commit 8f7db83e6abf863c6a2cfddbe7086f1e3251fdbf) ---- - drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c -index 1cf4631461c9..7d5ebb10323b 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c -@@ -10,6 +10,7 @@ - - #include - #include -+#include - #include - #include - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Qinglang Miao -Date: Mon, 21 Sep 2020 21:10:19 +0800 -Subject: [PATCH] drm/panfrost: simplify the return expression of - cz_ih_hw_init() - -Simplify the return expression. - -Signed-off-by: Qinglang Miao -Reviewed-by: Philipp Zabel -Reviewed-by: Steven Price -Signed-off-by: Steven Price -Link: https://patchwork.freedesktop.org/patch/msgid/20200921131019.91558-1-miaoqinglang@huawei.com -(cherry picked from commit 3c4641d4e75618fa1b5501b9ae9c19f765d75725) ---- - drivers/gpu/drm/panfrost/panfrost_device.c | 8 +------- - 1 file changed, 1 insertion(+), 7 deletions(-) - -diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c -index bf7c34cfb84c..a83b2ff5837a 100644 ---- a/drivers/gpu/drm/panfrost/panfrost_device.c -+++ b/drivers/gpu/drm/panfrost/panfrost_device.c -@@ -18,19 +18,13 @@ - - static int panfrost_reset_init(struct panfrost_device *pfdev) - { -- int err; -- - pfdev->rstc = devm_reset_control_array_get(pfdev->dev, false, true); - if (IS_ERR(pfdev->rstc)) { - dev_err(pfdev->dev, "get reset failed %ld\n", PTR_ERR(pfdev->rstc)); - return PTR_ERR(pfdev->rstc); - } - -- err = reset_control_deassert(pfdev->rstc); -- if (err) -- return err; -- -- return 0; -+ return reset_control_deassert(pfdev->rstc); - } - - static void panfrost_reset_fini(struct panfrost_device *pfdev) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Qinglang Miao -Date: Mon, 21 Sep 2020 21:10:21 +0800 -Subject: [PATCH] drm/panfrost: simplify the return expression of - panfrost_devfreq_target() - -Simplify the return expression. - -Signed-off-by: Qinglang Miao -Reviewed-by: Steven Price -Signed-off-by: Steven Price -Link: https://patchwork.freedesktop.org/patch/msgid/20200921131021.91604-1-miaoqinglang@huawei.com -(cherry picked from commit 0c5036590bde1407a6250ea027e836815353820f) ---- - drivers/gpu/drm/panfrost/panfrost_devfreq.c | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - -diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c b/drivers/gpu/drm/panfrost/panfrost_devfreq.c -index 8ab025d0035f..913eaa6d0bc6 100644 ---- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c -+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c -@@ -29,18 +29,13 @@ static int panfrost_devfreq_target(struct device *dev, unsigned long *freq, - u32 flags) - { - struct dev_pm_opp *opp; -- int err; - - opp = devfreq_recommended_opp(dev, freq, flags); - if (IS_ERR(opp)) - return PTR_ERR(opp); - dev_pm_opp_put(opp); - -- err = dev_pm_opp_set_rate(dev, *freq); -- if (err) -- return err; -- -- return 0; -+ return dev_pm_opp_set_rate(dev, *freq); - } - - static void panfrost_devfreq_reset(struct panfrost_devfreq *pfdevfreq) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Rikard Falkeborn -Date: Sun, 4 Oct 2020 22:06:53 +0200 -Subject: [PATCH] drm: bridge: dw-hdmi: Constify dw_hdmi_i2s_ops - -The only usage of dw_hdmi_i2s_ops is to assign its address to the ops -field in the hdmi_codec_pdata struct, which is a const pointer. Make it -const to allow the compiler to put it in read-only memory. - -Signed-off-by: Rikard Falkeborn -Signed-off-by: Daniel Vetter -Link: https://patchwork.freedesktop.org/patch/msgid/20201004200653.14702-1-rikard.falkeborn@gmail.com -(cherry picked from commit f3d52908f6baffc21ba45058103d0226ca5cb073) ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -index 9fef6413741d..feb04f127b55 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c -@@ -170,7 +170,7 @@ static int dw_hdmi_i2s_hook_plugged_cb(struct device *dev, void *data, - return dw_hdmi_set_plugged_cb(hdmi, fn, codec_dev); - } - --static struct hdmi_codec_ops dw_hdmi_i2s_ops = { -+static const struct hdmi_codec_ops dw_hdmi_i2s_ops = { - .hw_params = dw_hdmi_i2s_hw_params, - .audio_startup = dw_hdmi_i2s_audio_startup, - .audio_shutdown = dw_hdmi_i2s_audio_shutdown, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Liu Shixin -Date: Sat, 19 Sep 2020 18:08:50 +0800 -Subject: [PATCH] drm/lima: simplify the return expression of - lima_devfreq_target - -Simplify the return expression. - -Signed-off-by: Liu Shixin -Signed-off-by: Qiang Yu -Link: https://patchwork.freedesktop.org/patch/msgid/20200919100850.1639111-1-liushixin2@huawei.com ---- - drivers/gpu/drm/lima/lima_devfreq.c | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - -diff --git a/drivers/gpu/drm/lima/lima_devfreq.c b/drivers/gpu/drm/lima/lima_devfreq.c -index bbe02817721b..5914442936ed 100644 ---- a/drivers/gpu/drm/lima/lima_devfreq.c -+++ b/drivers/gpu/drm/lima/lima_devfreq.c -@@ -35,18 +35,13 @@ static int lima_devfreq_target(struct device *dev, unsigned long *freq, - u32 flags) - { - struct dev_pm_opp *opp; -- int err; - - opp = devfreq_recommended_opp(dev, freq, flags); - if (IS_ERR(opp)) - return PTR_ERR(opp); - dev_pm_opp_put(opp); - -- err = dev_pm_opp_set_rate(dev, *freq); -- if (err) -- return err; -- -- return 0; -+ return dev_pm_opp_set_rate(dev, *freq); - } - - static void lima_devfreq_reset(struct lima_devfreq *devfreq) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Lee Jones -Date: Fri, 13 Nov 2020 13:49:13 +0000 -Subject: [PATCH] drm/lima/lima_drv: Demote kernel-doc formatting abuse - -Fixes the following W=1 kernel build warning(s): - - drivers/gpu/drm/lima/lima_drv.c:264: warning: cannot understand function prototype: 'const struct drm_driver lima_drm_driver = ' - -Cc: Qiang Yu -Cc: David Airlie -Cc: Daniel Vetter -Cc: dri-devel@lists.freedesktop.org -Cc: lima@lists.freedesktop.org -Signed-off-by: Lee Jones -Signed-off-by: Qiang Yu -Link: https://patchwork.freedesktop.org/patch/msgid/20201113134938.4004947-16-lee.jones@linaro.org ---- - drivers/gpu/drm/lima/lima_drv.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/lima/lima_drv.c b/drivers/gpu/drm/lima/lima_drv.c -index ab460121fd52..065c80c14d10 100644 ---- a/drivers/gpu/drm/lima/lima_drv.c -+++ b/drivers/gpu/drm/lima/lima_drv.c -@@ -255,7 +255,7 @@ static const struct drm_ioctl_desc lima_drm_driver_ioctls[] = { - - DEFINE_DRM_GEM_FOPS(lima_drm_driver_fops); - --/** -+/* - * Changelog: - * - * - 1.1.0 - add heap buffer support - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Lee Jones -Date: Fri, 13 Nov 2020 13:49:21 +0000 -Subject: [PATCH] drm/lima/lima_sched: Remove unused and unnecessary variable - 'ret' -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Fixes the following W=1 kernel build warning(s): - - drivers/gpu/drm/lima/lima_sched.c: In function ‘lima_sched_run_job’: - drivers/gpu/drm/lima/lima_sched.c:227:20: warning: variable ‘ret’ set but not used [-Wunused-but-set-variable] - -Cc: Qiang Yu -Cc: David Airlie -Cc: Daniel Vetter -Cc: Sumit Semwal -Cc: "Christian König" -Cc: dri-devel@lists.freedesktop.org -Cc: lima@lists.freedesktop.org -Cc: linux-media@vger.kernel.org -Cc: linaro-mm-sig@lists.linaro.org -Signed-off-by: Lee Jones -Signed-off-by: Qiang Yu -Link: https://patchwork.freedesktop.org/patch/msgid/20201113134938.4004947-24-lee.jones@linaro.org ---- - drivers/gpu/drm/lima/lima_sched.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/lima/lima_sched.c b/drivers/gpu/drm/lima/lima_sched.c -index f6e7a88a56f1..040ea27b28ce 100644 ---- a/drivers/gpu/drm/lima/lima_sched.c -+++ b/drivers/gpu/drm/lima/lima_sched.c -@@ -223,7 +223,6 @@ static struct dma_fence *lima_sched_run_job(struct drm_sched_job *job) - struct lima_sched_pipe *pipe = to_lima_pipe(job->sched); - struct lima_device *ldev = pipe->ldev; - struct lima_fence *fence; -- struct dma_fence *ret; - int i, err; - - /* after GPU reset */ -@@ -245,7 +244,7 @@ static struct dma_fence *lima_sched_run_job(struct drm_sched_job *job) - /* for caller usage of the fence, otherwise irq handler - * may consume the fence before caller use it - */ -- ret = dma_fence_get(task->fence); -+ dma_fence_get(task->fence); - - pipe->current_task = task; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Viresh Kumar -Date: Wed, 28 Oct 2020 12:14:21 +0530 -Subject: [PATCH] drm/lima: Unconditionally call dev_pm_opp_of_remove_table() - -dev_pm_opp_of_remove_table() doesn't report any errors when it fails to -find the OPP table with error -ENODEV (i.e. OPP table not present for -the device). And we can call dev_pm_opp_of_remove_table() -unconditionally here. - -Reviewed-by: Qiang Yu -Signed-off-by: Viresh Kumar -Signed-off-by: Qiang Yu -Link: https://patchwork.freedesktop.org/patch/msgid/c995335d16d8b4b4ff47b1273869c33e14782b32.1603867405.git.viresh.kumar@linaro.org ---- - drivers/gpu/drm/lima/lima_devfreq.c | 6 +----- - drivers/gpu/drm/lima/lima_devfreq.h | 1 - - 2 files changed, 1 insertion(+), 6 deletions(-) - -diff --git a/drivers/gpu/drm/lima/lima_devfreq.c b/drivers/gpu/drm/lima/lima_devfreq.c -index 5914442936ed..da7099d20bd5 100644 ---- a/drivers/gpu/drm/lima/lima_devfreq.c -+++ b/drivers/gpu/drm/lima/lima_devfreq.c -@@ -100,10 +100,7 @@ void lima_devfreq_fini(struct lima_device *ldev) - devfreq->devfreq = NULL; - } - -- if (devfreq->opp_of_table_added) { -- dev_pm_opp_of_remove_table(ldev->dev); -- devfreq->opp_of_table_added = false; -- } -+ dev_pm_opp_of_remove_table(ldev->dev); - - if (devfreq->regulators_opp_table) { - dev_pm_opp_put_regulators(devfreq->regulators_opp_table); -@@ -157,7 +154,6 @@ int lima_devfreq_init(struct lima_device *ldev) - ret = dev_pm_opp_of_add_table(dev); - if (ret) - goto err_fini; -- ldevfreq->opp_of_table_added = true; - - lima_devfreq_reset(ldevfreq); - -diff --git a/drivers/gpu/drm/lima/lima_devfreq.h b/drivers/gpu/drm/lima/lima_devfreq.h -index 5eed2975a375..2d9b3008ce77 100644 ---- a/drivers/gpu/drm/lima/lima_devfreq.h -+++ b/drivers/gpu/drm/lima/lima_devfreq.h -@@ -18,7 +18,6 @@ struct lima_devfreq { - struct opp_table *clkname_opp_table; - struct opp_table *regulators_opp_table; - struct thermal_cooling_device *cooling; -- bool opp_of_table_added; - - ktime_t busy_time; - ktime_t idle_time; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Viresh Kumar -Date: Fri, 6 Nov 2020 12:18:39 +0530 -Subject: [PATCH] drm/lima: dev_pm_opp_put_*() accepts NULL argument - -The dev_pm_opp_put_*() APIs now accepts a NULL opp_table pointer and so -there is no need for us to carry the extra check. Drop them. - -Reviewed-by: Qiang Yu -Signed-off-by: Viresh Kumar ---- - drivers/gpu/drm/lima/lima_devfreq.c | 13 ++++--------- - 1 file changed, 4 insertions(+), 9 deletions(-) - -diff --git a/drivers/gpu/drm/lima/lima_devfreq.c b/drivers/gpu/drm/lima/lima_devfreq.c -index da7099d20bd5..5686ad4aaf7c 100644 ---- a/drivers/gpu/drm/lima/lima_devfreq.c -+++ b/drivers/gpu/drm/lima/lima_devfreq.c -@@ -102,15 +102,10 @@ void lima_devfreq_fini(struct lima_device *ldev) - - dev_pm_opp_of_remove_table(ldev->dev); - -- if (devfreq->regulators_opp_table) { -- dev_pm_opp_put_regulators(devfreq->regulators_opp_table); -- devfreq->regulators_opp_table = NULL; -- } -- -- if (devfreq->clkname_opp_table) { -- dev_pm_opp_put_clkname(devfreq->clkname_opp_table); -- devfreq->clkname_opp_table = NULL; -- } -+ dev_pm_opp_put_regulators(devfreq->regulators_opp_table); -+ dev_pm_opp_put_clkname(devfreq->clkname_opp_table); -+ devfreq->regulators_opp_table = NULL; -+ devfreq->clkname_opp_table = NULL; - } - - int lima_devfreq_init(struct lima_device *ldev) diff --git a/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch index 244d6f5046..93bc774629 100644 --- a/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch @@ -362,34 +362,6 @@ index 41edd0a421b2..4d463d50a63a 100644 DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); return ret; -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Lukasz Luba -Date: Tue, 5 Jan 2021 16:41:11 +0000 -Subject: [PATCH] drm/panfrost: Use delayed timer as default in devfreq profile - -Devfreq framework supports 2 modes for monitoring devices. -Use delayed timer as default instead of deferrable timer -in order to monitor the GPU status regardless of CPU idle. - -Signed-off-by: Lukasz Luba -Reviewed-by: Steven Price ---- - drivers/gpu/drm/panfrost/panfrost_devfreq.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c b/drivers/gpu/drm/panfrost/panfrost_devfreq.c -index 913eaa6d0bc6..17d5fa6e0b83 100644 ---- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c -+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c -@@ -76,6 +76,7 @@ static int panfrost_devfreq_get_dev_status(struct device *dev, - } - - static struct devfreq_dev_profile panfrost_devfreq_profile = { -+ .timer = DEVFREQ_TIMER_DELAYED, - .polling_ms = 50, /* ~3 frames */ - .target = panfrost_devfreq_target, - .get_dev_status = panfrost_devfreq_get_dev_status, - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Thu, 21 Jan 2021 17:04:45 +0000 diff --git a/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch b/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch index ed11c9bfea..dbf18c3562 100644 --- a/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch +++ b/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch @@ -211,15 +211,14 @@ index 69c2c079d803..65fbffc4cbc7 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -1093,7 +1093,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, - drm_gem_object_put(obj); - return ret; - } + ret = obj->funcs->mmap(obj, vma); + if (ret) + goto err_drm_gem_object_put; - WARN_ON(!(vma->vm_flags & VM_DONTEXPAND)); + //WARN_ON(!(vma->vm_flags & VM_DONTEXPAND)); } else { - if (obj->funcs && obj->funcs->vm_ops) - vma->vm_ops = obj->funcs->vm_ops; - + if (!vma->vm_ops) { + ret = -EINVAL; From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 25 Mar 2018 22:17:06 +0200 diff --git a/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch b/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch index d8b5058087..3663de8756 100644 --- a/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch +++ b/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch @@ -941,8 +941,8 @@ index 000000000000..a14fffb3ad61 + +#define V4L2_PIX_FMT_VP9_FRAME v4l2_fourcc('V', 'P', '9', 'F') + -+#define V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(i) (V4L2_CID_MPEG_BASE + 4000 + (i)) -+#define V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS (V4L2_CID_MPEG_BASE + 4004) ++#define V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(i) (V4L2_CID_CODEC_BASE + 4000 + (i)) ++#define V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS (V4L2_CID_CODEC_BASE + 4004) +#define V4L2_CTRL_TYPE_VP9_FRAME_CONTEXT 0x400 +#define V4L2_CTRL_TYPE_VP9_FRAME_DECODE_PARAMS 0x404 + @@ -3026,13 +3026,12 @@ diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvde index c4e0ec16c285..f3578c5ea902 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -162,6 +162,40 @@ static const u32 rkvdec_h264_decoded_fmts[] = { +@@ -162,6 +162,39 @@ static const u32 rkvdec_h264_decoded_fmts[] = { V4L2_PIX_FMT_NV20, }; +static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = { + { -+ .mandatory = true, + .cfg.id = V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS, + }, + { diff --git a/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch b/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch index cb746a6920..246dda8da6 100644 --- a/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch +++ b/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch @@ -65,18 +65,6 @@ index 456488f2b5ca..81529b1d8d69 100644 ``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (enum)`` Specifies the decoding mode to use. Currently exposes slice-based and frame-based decoding but new modes might be added later on. -diff --git a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -index d585909bc4e2..f817c643761b 100644 ---- a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -+++ b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -@@ -200,6 +200,7 @@ Compressed Formats - * ``V4L2_CID_MPEG_VIDEO_HEVC_SPS`` - * ``V4L2_CID_MPEG_VIDEO_HEVC_PPS`` - * ``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS`` -+ * ``V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX`` - See the :ref:`associated Codec Control IDs `. - Buffers associated with this pixel format must contain the appropriate - number of macroblocks to decode a full corresponding frame. diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c index 7ed11f296008..a2609de88d26 100644 --- a/drivers/media/v4l2-core/v4l2-ctrls.c @@ -124,12 +112,12 @@ index 1009cf0891cc..1592e52c3614 100644 --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h @@ -19,6 +19,7 @@ - #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 1008) - #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 1009) - #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 1010) -+#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_MPEG_BASE + 1011) - #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_MPEG_BASE + 1015) - #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_MPEG_BASE + 1016) + #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_CODEC_BASE + 1008) + #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_CODEC_BASE + 1009) + #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_CODEC_BASE + 1010) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_CODEC_BASE + 1011) + #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_CODEC_BASE + 1015) + #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_CODEC_BASE + 1016) @@ -26,6 +27,7 @@ #define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 @@ -2901,28 +2889,24 @@ diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvde index f3578c5ea902..a44db1aa161e 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -162,6 +162,61 @@ static const u32 rkvdec_h264_decoded_fmts[] = { +@@ -162,6 +162,57 @@ static const u32 rkvdec_h264_decoded_fmts[] = { V4L2_PIX_FMT_NV20, }; +static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { + { -+ .mandatory = true, + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS, + // HACK: match ffmpeg v4l2 request api hwaccel size, + // we should support variable length up to 600 slices + .cfg.dims = { 16 }, + }, + { -+ .mandatory = true, + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, + }, + { -+ .mandatory = true, + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PPS, + }, + { -+ .mandatory = true, + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX, + }, + { diff --git a/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch b/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch index b62cdf056f..c74198a69a 100644 --- a/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch +++ b/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch @@ -142,9 +142,9 @@ index 62b6cdc8c730..f99a873818d5 100644 obj-$(CONFIG_VIDEO_RENESAS_VSP1) += vsp1/ +obj-$(CONFIG_VIDEO_ROCKCHIP_IEP) += rockchip/iep/ + obj-$(CONFIG_VIDEO_ROCKCHIP_ISP1) += rockchip/rkisp1/ obj-$(CONFIG_VIDEO_ROCKCHIP_RGA) += rockchip/rga/ - obj-y += omap/ diff --git a/drivers/media/platform/rockchip/iep/Makefile b/drivers/media/platform/rockchip/iep/Makefile new file mode 100644 index 000000000000..5c89b3277469