mirror of
https://github.com/LibreELEC/LibreELEC.tv.git
synced 2025-08-03 16:07:51 +00:00
linux (Generic/Allwinner): update to linux-5.3.10
This commit is contained in:
parent
5d3e48e697
commit
3751a442ef
@ -37,8 +37,8 @@ case "$LINUX" in
|
||||
PKG_SOURCE_NAME="linux-$LINUX-$PKG_VERSION.tar.gz"
|
||||
;;
|
||||
*)
|
||||
PKG_VERSION="5.3.9"
|
||||
PKG_SHA256="d72579aa732edd0e25779adfc43e68a53f77e80020c4aab5db2f5b28c247e98a"
|
||||
PKG_VERSION="5.3.10"
|
||||
PKG_SHA256="8162e0b88fb0ebf2b5982611709974a7f08aba2292a720fabaca700f960d9a22"
|
||||
PKG_URL="https://www.kernel.org/pub/linux/kernel/v5.x/$PKG_NAME-$PKG_VERSION.tar.xz"
|
||||
PKG_PATCH_DIRS="default"
|
||||
;;
|
||||
|
@ -5618,94 +5618,6 @@ index ba2876a64cf6..e877bf1d537c 100644
|
||||
--
|
||||
2.23.0
|
||||
|
||||
From 2511366797fa6ab4a404b4b000ef7cd262aaafe8 Mon Sep 17 00:00:00 2001
|
||||
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
Date: Mon, 9 Sep 2019 20:42:35 +0200
|
||||
Subject: [PATCH] arm64: dts: allwinner: a64: pine64-plus: Add PHY regulator
|
||||
delay
|
||||
|
||||
Depending on kernel and bootloader configuration, it's possible that
|
||||
Realtek ethernet PHY isn't powered on properly. According to the
|
||||
datasheet, it needs 30ms to power up and then some more time before it
|
||||
can be used.
|
||||
|
||||
Fix that by adding 100ms ramp delay to regulator responsible for
|
||||
powering PHY.
|
||||
|
||||
Fixes: 94dcfdc77fc5 ("arm64: allwinner: pine64-plus: Enable dwmac-sun8i")
|
||||
Suggested-by: Ondrej Jirman <megous@megous.com>
|
||||
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
Signed-off-by: Maxime Ripard <mripard@kernel.org>
|
||||
---
|
||||
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
|
||||
index 24f1aac366d6..d5b6e8159a33 100644
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
|
||||
@@ -63,3 +63,12 @@
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+®_dc1sw {
|
||||
+ /*
|
||||
+ * Ethernet PHY needs 30ms to properly power up and some more
|
||||
+ * to initialize. 100ms should be plenty of time to finish
|
||||
+ * whole process.
|
||||
+ */
|
||||
+ regulator-enable-ramp-delay = <100000>;
|
||||
+};
|
||||
--
|
||||
2.23.0
|
||||
|
||||
From ccdf3aaa27ded6db9a93eed3ca7468bb2353b8fe Mon Sep 17 00:00:00 2001
|
||||
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
Date: Sun, 29 Sep 2019 10:52:59 +0200
|
||||
Subject: [PATCH] arm64: dts: allwinner: a64: sopine-baseboard: Add PHY
|
||||
regulator delay
|
||||
|
||||
It turns out that sopine-baseboard needs same fix as pine64-plus
|
||||
for ethernet PHY. Here too Realtek ethernet PHY chip needs additional
|
||||
power on delay to properly initialize. Datasheet mentions that chip
|
||||
needs 30 ms to be properly powered on and that it needs some more time
|
||||
to be initialized.
|
||||
|
||||
Fix that by adding 100ms ramp delay to regulator responsible for
|
||||
powering PHY.
|
||||
|
||||
Note that issue was found out and fix tested on pine64-lts, but it's
|
||||
basically the same as sopine-baseboard, only layout and connectors
|
||||
differ.
|
||||
|
||||
Fixes: bdfe4cebea11 ("arm64: allwinner: a64: add Ethernet PHY regulator for several boards")
|
||||
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
Signed-off-by: Maxime Ripard <mripard@kernel.org>
|
||||
---
|
||||
.../boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
|
||||
index e6fb9683f213..25099202c52c 100644
|
||||
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
|
||||
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
|
||||
@@ -159,6 +159,12 @@
|
||||
};
|
||||
|
||||
®_dc1sw {
|
||||
+ /*
|
||||
+ * Ethernet PHY needs 30ms to properly power up and some more
|
||||
+ * to initialize. 100ms should be plenty of time to finish
|
||||
+ * whole process.
|
||||
+ */
|
||||
+ regulator-enable-ramp-delay = <100000>;
|
||||
regulator-name = "vcc-phy";
|
||||
};
|
||||
|
||||
--
|
||||
2.23.0
|
||||
|
||||
From 52c8c7a766ecc49ff2e4c1db30b0a24a019e31d4 Mon Sep 17 00:00:00 2001
|
||||
From: Ondrej Jirman <megous@megous.com>
|
||||
Date: Fri, 23 Aug 2019 12:31:36 +0200
|
||||
|
Loading…
x
Reference in New Issue
Block a user