diff --git a/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch index 8a3a76e468..62d7e0f68c 100644 --- a/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch @@ -232,3 +232,456 @@ index 80053d91a301..2c55e1852c3d 100644 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), .y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22), .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Qinglang Miao +Date: Tue, 1 Dec 2020 20:54:57 +0800 +Subject: [PATCH] drm/rockchip: cdn-dp: fix reference leak when + pm_runtime_get_sync fails + +The PM reference count is not expected to be incremented on +return in cdn_dp_clk_enable. + +However, pm_runtime_get_sync will increment the PM reference +count even failed. Forgetting to putting operation will result +in a reference leak here. + +Replace it with pm_runtime_resume_and_get to keep usage +counter balanced. + +Fixes: efe0220fc2d2 ("drm/rockchip: cdn-dp: Fix error handling") +Reported-by: Hulk Robot +Signed-off-by: Qinglang Miao +--- + drivers/gpu/drm/rockchip/cdn-dp-core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c +index a4a45daf93f2..9b4406191470 100644 +--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c ++++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c +@@ -98,7 +98,7 @@ static int cdn_dp_clk_enable(struct cdn_dp_device *dp) + goto err_core_clk; + } + +- ret = pm_runtime_get_sync(dp->dev); ++ ret = pm_runtime_resume_and_get(dp->dev); + if (ret < 0) { + DRM_DEV_ERROR(dp->dev, "cannot get pm runtime %d\n", ret); + goto err_pm_runtime_get; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Qinglang Miao +Date: Tue, 1 Dec 2020 20:54:58 +0800 +Subject: [PATCH] drm/rockchip: vop: fix reference leak when + pm_runtime_get_sync fails + +The PM reference count is not expected to be incremented on +return in functions vop_enable and vop_enable. + +However, pm_runtime_get_sync will increment the PM reference +count even failed. Forgetting to putting operation will result +in a reference leak here. + +Replace it with pm_runtime_resume_and_get to keep usage +counter balanced. + +Fixes: 5e570373c015 ("drm/rockchip: vop: Enable pm domain before vop_initial") +Reported-by: Hulk Robot +Signed-off-by: Qinglang Miao +--- + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +index eb663e25ad9e..c6c76e8ab66c 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +@@ -602,7 +602,7 @@ static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) + struct vop *vop = to_vop(crtc); + int ret, i; + +- ret = pm_runtime_get_sync(vop->dev); ++ ret = pm_runtime_resume_and_get(vop->dev); + if (ret < 0) { + DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); + return ret; +@@ -1933,7 +1933,7 @@ static int vop_initial(struct vop *vop) + return PTR_ERR(vop->dclk); + } + +- ret = pm_runtime_get_sync(vop->dev); ++ ret = pm_runtime_resume_and_get(vop->dev); + if (ret < 0) { + DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); + return ret; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Qinglang Miao +Date: Tue, 1 Dec 2020 20:54:59 +0800 +Subject: [PATCH] drm/rockchip: lvds: fix reference leak when + pm_runtime_get_sync fails + +The PM reference count is not expected to be incremented on +return in functions rk3288_lvds_poweron and px30_lvds_poweron. + +However, pm_runtime_get_sync will increment the PM reference +count even failed. Forgetting to putting operation will result +in a reference leak here. + +Replace it with pm_runtime_resume_and_get to keep usage +counter balanced. + +Fixes: cca1705c3d89 ("drm/rockchip: lvds: Add PX30 support") +Reported-by: Hulk Robot +Signed-off-by: Qinglang Miao +--- + drivers/gpu/drm/rockchip/rockchip_lvds.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c +index 41edd0a421b2..4d463d50a63a 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_lvds.c ++++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c +@@ -145,7 +145,7 @@ static int rk3288_lvds_poweron(struct rockchip_lvds *lvds) + DRM_DEV_ERROR(lvds->dev, "failed to enable lvds pclk %d\n", ret); + return ret; + } +- ret = pm_runtime_get_sync(lvds->dev); ++ ret = pm_runtime_resume_and_get(lvds->dev); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); + clk_disable(lvds->pclk); +@@ -329,7 +329,7 @@ static int px30_lvds_poweron(struct rockchip_lvds *lvds) + { + int ret; + +- ret = pm_runtime_get_sync(lvds->dev); ++ ret = pm_runtime_resume_and_get(lvds->dev); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); + return ret; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Lukasz Luba +Date: Tue, 5 Jan 2021 16:41:11 +0000 +Subject: [PATCH] drm/panfrost: Use delayed timer as default in devfreq profile + +Devfreq framework supports 2 modes for monitoring devices. +Use delayed timer as default instead of deferrable timer +in order to monitor the GPU status regardless of CPU idle. + +Signed-off-by: Lukasz Luba +Reviewed-by: Steven Price +--- + drivers/gpu/drm/panfrost/panfrost_devfreq.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c b/drivers/gpu/drm/panfrost/panfrost_devfreq.c +index 913eaa6d0bc6..17d5fa6e0b83 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c ++++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c +@@ -76,6 +76,7 @@ static int panfrost_devfreq_get_dev_status(struct device *dev, + } + + static struct devfreq_dev_profile panfrost_devfreq_profile = { ++ .timer = DEVFREQ_TIMER_DELAYED, + .polling_ms = 50, /* ~3 frames */ + .target = panfrost_devfreq_target, + .get_dev_status = panfrost_devfreq_get_dev_status, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Lukasz Luba +Date: Thu, 21 Jan 2021 17:04:45 +0000 +Subject: [PATCH] drm/panfrost: Add governor data with pre-defined thresholds + +The simple_ondemand devfreq governor uses two thresholds to decide about +the frequency change: upthreshold, downdifferential. These two tunable +change the behavior of the governor decision, e.g. how fast to increase +the frequency or how rapidly limit the frequency. This patch adds needed +governor data with thresholds values gathered experimentally in different +workloads. + +Signed-off-by: Lukasz Luba +--- + drivers/gpu/drm/panfrost/panfrost_devfreq.c | 10 +++++++++- + drivers/gpu/drm/panfrost/panfrost_devfreq.h | 2 ++ + 2 files changed, 11 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c b/drivers/gpu/drm/panfrost/panfrost_devfreq.c +index 17d5fa6e0b83..53e0188ce8e8 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c ++++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c +@@ -130,8 +130,16 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev) + panfrost_devfreq_profile.initial_freq = cur_freq; + dev_pm_opp_put(opp); + ++ /* ++ * Setup default thresholds for the simple_ondemand governor. ++ * The values are chosen based on experiments. ++ */ ++ pfdevfreq->gov_data.upthreshold = 45; ++ pfdevfreq->gov_data.downdifferential = 5; ++ + devfreq = devm_devfreq_add_device(dev, &panfrost_devfreq_profile, +- DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL); ++ DEVFREQ_GOV_SIMPLE_ONDEMAND, ++ &pfdevfreq->gov_data); + if (IS_ERR(devfreq)) { + DRM_DEV_ERROR(dev, "Couldn't initialize GPU devfreq\n"); + ret = PTR_ERR(devfreq); +diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.h b/drivers/gpu/drm/panfrost/panfrost_devfreq.h +index db6ea48e21f9..1e2a4de941aa 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.h ++++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.h +@@ -4,6 +4,7 @@ + #ifndef __PANFROST_DEVFREQ_H__ + #define __PANFROST_DEVFREQ_H__ + ++#include + #include + #include + +@@ -17,6 +18,7 @@ struct panfrost_devfreq { + struct devfreq *devfreq; + struct opp_table *regulators_opp_table; + struct thermal_cooling_device *cooling; ++ struct devfreq_simple_ondemand_data gov_data; + bool opp_of_table_added; + + ktime_t busy_time; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Boris Brezillon +Date: Fri, 5 Feb 2021 12:17:55 +0100 +Subject: [PATCH] drm/panfrost: Clear MMU irqs before handling the fault + +When a fault is handled it will unblock the GPU which will continue +executing its shader and might fault almost immediately on a different +page. If we clear interrupts after handling the fault we might miss new +faults, so clear them before. + +Cc: +Fixes: 187d2929206e ("drm/panfrost: Add support for GPU heap allocations") +Signed-off-by: Boris Brezillon +Reviewed-by: Steven Price +--- + drivers/gpu/drm/panfrost/panfrost_mmu.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c +index be8d68fb0e11..e5f7f647430f 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_mmu.c ++++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c +@@ -600,6 +600,8 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) + access_type = (fault_status >> 8) & 0x3; + source_id = (fault_status >> 16); + ++ mmu_write(pfdev, MMU_INT_CLEAR, mask); ++ + /* Page fault only */ + ret = -1; + if ((status & mask) == BIT(i) && (exception_type & 0xF8) == 0xC0) +@@ -623,8 +625,6 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) + access_type, access_type_name(pfdev, fault_status), + source_id); + +- mmu_write(pfdev, MMU_INT_CLEAR, mask); +- + status &= ~mask; + } + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Boris Brezillon +Date: Fri, 5 Feb 2021 12:17:56 +0100 +Subject: [PATCH] drm/panfrost: Don't try to map pages that are already mapped + +We allocate 2MB chunks at a time, so it might appear that a page fault +has already been handled by a previous page fault when we reach +panfrost_mmu_map_fault_addr(). Bail out in that case to avoid mapping the +same area twice. + +Cc: +Fixes: 187d2929206e ("drm/panfrost: Add support for GPU heap allocations") +Signed-off-by: Boris Brezillon +Reviewed-by: Steven Price +--- + drivers/gpu/drm/panfrost/panfrost_mmu.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c +index e5f7f647430f..198686216317 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_mmu.c ++++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c +@@ -495,8 +495,14 @@ static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as, + } + bo->base.pages = pages; + bo->base.pages_use_count = 1; +- } else ++ } else { + pages = bo->base.pages; ++ if (pages[page_offset]) { ++ /* Pages are already mapped, bail out. */ ++ mutex_unlock(&bo->base.pages_lock); ++ goto out; ++ } ++ } + + mapping = bo->base.base.filp->f_mapping; + mapping_set_unevictable(mapping); +@@ -529,6 +535,7 @@ static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as, + + dev_dbg(pfdev->dev, "mapped page fault @ AS%d %llx", as, addr); + ++out: + panfrost_gem_mapping_put(bomapping); + + return 0; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Boris Brezillon +Date: Fri, 5 Feb 2021 12:17:57 +0100 +Subject: [PATCH] drm/panfrost: Stay in the threaded MMU IRQ handler until + we've handled all IRQs + +Doing a hw-irq -> threaded-irq round-trip is counter-productive, stay +in the threaded irq handler as long as we can. + +v2: +* Rework the loop to avoid a goto + +Signed-off-by: Boris Brezillon +Reviewed-by: Steven Price +Reviewed-by: Rob Herring +--- + drivers/gpu/drm/panfrost/panfrost_mmu.c | 26 +++++++++++++------------ + 1 file changed, 14 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c +index 198686216317..5a3d18c05802 100644 +--- a/drivers/gpu/drm/panfrost/panfrost_mmu.c ++++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c +@@ -585,22 +585,20 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) + { + struct panfrost_device *pfdev = data; + u32 status = mmu_read(pfdev, MMU_INT_RAWSTAT); +- int i, ret; ++ int ret; + +- for (i = 0; status; i++) { +- u32 mask = BIT(i) | BIT(i + 16); ++ while (status) { ++ u32 as = ffs(status | (status >> 16)) - 1; ++ u32 mask = BIT(as) | BIT(as + 16); + u64 addr; + u32 fault_status; + u32 exception_type; + u32 access_type; + u32 source_id; + +- if (!(status & mask)) +- continue; +- +- fault_status = mmu_read(pfdev, AS_FAULTSTATUS(i)); +- addr = mmu_read(pfdev, AS_FAULTADDRESS_LO(i)); +- addr |= (u64)mmu_read(pfdev, AS_FAULTADDRESS_HI(i)) << 32; ++ fault_status = mmu_read(pfdev, AS_FAULTSTATUS(as)); ++ addr = mmu_read(pfdev, AS_FAULTADDRESS_LO(as)); ++ addr |= (u64)mmu_read(pfdev, AS_FAULTADDRESS_HI(as)) << 32; + + /* decode the fault status */ + exception_type = fault_status & 0xFF; +@@ -611,8 +609,8 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) + + /* Page fault only */ + ret = -1; +- if ((status & mask) == BIT(i) && (exception_type & 0xF8) == 0xC0) +- ret = panfrost_mmu_map_fault_addr(pfdev, i, addr); ++ if ((status & mask) == BIT(as) && (exception_type & 0xF8) == 0xC0) ++ ret = panfrost_mmu_map_fault_addr(pfdev, as, addr); + + if (ret) + /* terminal fault, print info about the fault */ +@@ -624,7 +622,7 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) + "exception type 0x%X: %s\n" + "access type 0x%X: %s\n" + "source id 0x%X\n", +- i, addr, ++ as, addr, + "TODO", + fault_status, + (fault_status & (1 << 10) ? "DECODER FAULT" : "SLAVE FAULT"), +@@ -633,6 +631,10 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data) + source_id); + + status &= ~mask; ++ ++ /* If we received new MMU interrupts, process them before returning. */ ++ if (!status) ++ status = mmu_read(pfdev, MMU_INT_RAWSTAT); + } + + mmu_write(pfdev, MMU_INT_MASK, ~0); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Wed, 27 Jan 2021 19:40:47 +0000 +Subject: [PATCH] drm/lima: add governor data with pre-defined thresholds + +This patch adapts the panfrost pre-defined thresholds change [0] to the +lima driver to improve real-world performance. The upthreshold value has +been set to ramp GPU frequency to max freq faster (compared to panfrost) +to compensate for the lower overall performance of utgard devices. + +[0] https://patchwork.kernel.org/project/dri-devel/patch/20210121170445.19761-1-lukasz.luba@arm.com/ + +Signed-off-by: Christian Hewitt +Reviewed-by: Lukasz Luba +Reviewed-by: Qiang Yu +--- + drivers/gpu/drm/lima/lima_devfreq.c | 10 +++++++++- + drivers/gpu/drm/lima/lima_devfreq.h | 2 ++ + 2 files changed, 11 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/lima/lima_devfreq.c b/drivers/gpu/drm/lima/lima_devfreq.c +index 5686ad4aaf7c..c9854315a0b5 100644 +--- a/drivers/gpu/drm/lima/lima_devfreq.c ++++ b/drivers/gpu/drm/lima/lima_devfreq.c +@@ -163,8 +163,16 @@ int lima_devfreq_init(struct lima_device *ldev) + lima_devfreq_profile.initial_freq = cur_freq; + dev_pm_opp_put(opp); + ++ /* ++ * Setup default thresholds for the simple_ondemand governor. ++ * The values are chosen based on experiments. ++ */ ++ ldevfreq->gov_data.upthreshold = 30; ++ ldevfreq->gov_data.downdifferential = 5; ++ + devfreq = devm_devfreq_add_device(dev, &lima_devfreq_profile, +- DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL); ++ DEVFREQ_GOV_SIMPLE_ONDEMAND, ++ &ldevfreq->gov_data); + if (IS_ERR(devfreq)) { + dev_err(dev, "Couldn't initialize GPU devfreq\n"); + ret = PTR_ERR(devfreq); +diff --git a/drivers/gpu/drm/lima/lima_devfreq.h b/drivers/gpu/drm/lima/lima_devfreq.h +index 2d9b3008ce77..b0c7c736e81a 100644 +--- a/drivers/gpu/drm/lima/lima_devfreq.h ++++ b/drivers/gpu/drm/lima/lima_devfreq.h +@@ -4,6 +4,7 @@ + #ifndef __LIMA_DEVFREQ_H__ + #define __LIMA_DEVFREQ_H__ + ++#include + #include + #include + +@@ -18,6 +19,7 @@ struct lima_devfreq { + struct opp_table *clkname_opp_table; + struct opp_table *regulators_opp_table; + struct thermal_cooling_device *cooling; ++ struct devfreq_simple_ondemand_data gov_data; + + ktime_t busy_time; + ktime_t idle_time; diff --git a/projects/Rockchip/patches/linux/default/linux-1003-RK3328-enable-USB3-for-supported-boards.patch b/projects/Rockchip/patches/linux/default/linux-1003-RK3328-enable-USB3-for-supported-boards.patch deleted file mode 100644 index 3d7702a4c0..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-1003-RK3328-enable-USB3-for-supported-boards.patch +++ /dev/null @@ -1,76 +0,0 @@ -From e7cc7e8e0812ce96035ad1d286d79a37f3ea81d2 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 16 Jan 2021 12:24:58 +0000 -Subject: [PATCH] ARM64: dts: rockchip: RK3328: enable USB3 for supported - boards - -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 21 +++++++++++++++++++ - .../arm64/boot/dts/rockchip/rk3328-rock64.dts | 21 +++++++++++++++++++ - 2 files changed, 42 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -index 37f307cfa4cc..4013f16bb368 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -@@ -352,6 +352,27 @@ &usb_host0_ehci { - status = "okay"; - }; - -+&usbdrd3 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb3phy { -+ status = "okay"; -+}; -+ -+&usb3phy_utmi { -+ status = "okay"; -+}; -+ -+&usb3phy_pipe { -+ status = "okay"; -+}; -+ - &vop { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -index c984662043da..89fde87f7650 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -@@ -384,6 +384,27 @@ &usb_host0_ohci { - status = "okay"; - }; - -+&usbdrd3 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb3phy { -+ status = "okay"; -+}; -+ -+&usb3phy_utmi { -+ status = "okay"; -+}; -+ -+&usb3phy_pipe { -+ status = "okay"; -+}; -+ - &vop { - status = "okay"; - }; diff --git a/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch b/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch new file mode 100644 index 0000000000..35a3c0f8a0 --- /dev/null +++ b/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch @@ -0,0 +1,452 @@ +From e7cc7e8e0812ce96035ad1d286d79a37f3ea81d2 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 16 Jan 2021 12:24:58 +0000 +Subject: [PATCH] ARM64: dts: rockchip: RK3328: enable USB3 for supported + boards + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 21 +++++++++++++++++++ + .../arm64/boot/dts/rockchip/rk3328-rock64.dts | 21 +++++++++++++++++++ + 2 files changed, 42 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +index 37f307cfa4cc..4013f16bb368 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +@@ -352,6 +352,27 @@ &usb_host0_ehci { + status = "okay"; + }; + ++&usbdrd3 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb3phy { ++ status = "okay"; ++}; ++ ++&usb3phy_utmi { ++ status = "okay"; ++}; ++ ++&usb3phy_pipe { ++ status = "okay"; ++}; ++ + &vop { + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +index c984662043da..89fde87f7650 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +@@ -384,6 +384,27 @@ &usb_host0_ohci { + status = "okay"; + }; + ++&usbdrd3 { ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb3phy { ++ status = "okay"; ++}; ++ ++&usb3phy_utmi { ++ status = "okay"; ++}; ++ ++&usb3phy_pipe { ++ status = "okay"; ++}; ++ + &vop { + status = "okay"; + }; +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 2 Sep 2020 19:52:02 +0200 +Subject: [PATCH] arm64: dts: rockchip: add gpu powerdomain, gpu opp-table and + cooling cell + +Note: since the regulator that supplies the GPU usually also supplies +other SoC components, we have to make sure voltage is never lower then +1050 mV. + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 33 ++++++++++++++++++++++++ + 1 file changed, 33 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index b54ff9055e5f..2fae7fa6b000 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -321,6 +321,10 @@ power: power-controller { + #address-cells = <1>; + #size-cells = <0>; + ++ pd_gpu@RK3328_PD_GPU { ++ reg = ; ++ clocks = <&cru ACLK_GPU>; ++ }; + pd_hevc@RK3328_PD_HEVC { + reg = ; + }; +@@ -546,6 +550,11 @@ map0 { + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; ++ map1 { ++ trip = <&target>; ++ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; ++ contribution = <4096>; ++ }; + }; + }; + +@@ -627,7 +636,31 @@ gpu: gpu@ff300000 { + "ppmmu1"; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "bus", "core"; ++ operating-points-v2 = <&gpu_opp_table>; ++ power-domains = <&power RK3328_PD_GPU>; + resets = <&cru SRST_GPU_A>; ++ #cooling-cells = <2>; ++ }; ++ ++ gpu_opp_table: gpu-opp-table { ++ compatible = "operating-points-v2"; ++ ++ opp-200000000 { ++ opp-hz = /bits/ 64 <200000000>; ++ opp-microvolt = <1050000>; ++ }; ++ opp-300000000 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <1050000>; ++ }; ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <1050000>; ++ }; ++ opp-500000000 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <1150000>; ++ }; + }; + + h265e_mmu: iommu@ff330200 { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 2 Sep 2020 21:22:31 +0200 +Subject: [PATCH] arm64: dts: rockchip: add rockchip,disable-mmu-reset for vdec + iommu + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 2fae7fa6b000..3d933d74c2b3 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -731,6 +731,7 @@ rkvdec_mmu: iommu@ff360480 { + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3328_PD_VIDEO>; ++ rockchip,disable-mmu-reset; + }; + + vop: vop@ff370000 { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Mon, 10 Feb 2020 19:22:41 +0100 +Subject: [PATCH] ARM64: dts: rk3328 add sdmmc ext node + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 3d933d74c2b3..bd1e5edfbf95 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -1104,6 +1104,20 @@ usbdrd_dwc3: dwc3@ff600000 { + }; + }; + ++ sdmmc_ext: dwmmc@ff5f0000 { ++ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; ++ reg = <0x0 0xff5f0000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, ++ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; ++ fifo-depth = <0x100>; ++ max-frequency = <150000000>; ++ resets = <&cru SRST_SDMMCEXT>; ++ reset-names = "reset"; ++ status = "disabled"; ++ }; ++ + gic: interrupt-controller@ff811000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Tue, 2 Feb 2021 17:22:21 +0200 +Subject: [PATCH] arm: dts: rk3288 miqi add hdmi sound nodes + +Signed-off-by: Alex Bee +--- + arch/arm/boot/dts/rk3288-miqi.dts | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts +index 713f55e143c6..2420d8e1c66f 100644 +--- a/arch/arm/boot/dts/rk3288-miqi.dts ++++ b/arch/arm/boot/dts/rk3288-miqi.dts +@@ -78,6 +78,21 @@ vcc_sys: vsys-regulator { + regulator-always-on; + regulator-boot-on; + }; ++ ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "rockchip,miqi-codec"; ++ simple-audio-card,mclk-fs = <512>; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s>; ++ }; ++ }; + }; + + &cpu0 { +@@ -284,6 +299,11 @@ &i2c5 { + status = "okay"; + }; + ++&i2s { ++ #sound-dai-cells = <0>; ++ status = "okay"; ++}; ++ + &io_domains { + status = "okay"; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 1 Jan 2021 12:11:12 +0200 +Subject: [PATCH] arm64: dts: rockchip: fix RK3399 vdec register witdh + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 418d16b0b648..4d5004c9c778 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1276,7 +1276,7 @@ vpu_mmu: iommu@ff650800 { + + vdec: video-codec@ff660000 { + compatible = "rockchip,rk3399-vdec"; +- reg = <0x0 0xff660000 0x0 0x400>; ++ reg = <0x0 0xff660000 0x0 0x480>; + interrupts = ; + interrupt-names = "vdpu"; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 10 Feb 2021 18:44:56 +0200 +Subject: [PATCH] HACK: drm/gem: suppress warning about missing vm_flags + +Signed-off-by: Alex Bee +--- + drivers/gpu/drm/drm_gem.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c +index 69c2c079d803..65fbffc4cbc7 100644 +--- a/drivers/gpu/drm/drm_gem.c ++++ b/drivers/gpu/drm/drm_gem.c +@@ -1093,7 +1093,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, + drm_gem_object_put(obj); + return ret; + } +- WARN_ON(!(vma->vm_flags & VM_DONTEXPAND)); ++ //WARN_ON(!(vma->vm_flags & VM_DONTEXPAND)); + } else { + if (obj->funcs && obj->funcs->vm_ops) + vma->vm_ops = obj->funcs->vm_ops; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 25 Mar 2018 22:17:06 +0200 +Subject: [PATCH] ASoC: hdmi-codec: fix channel allocation + +--- + sound/soc/codecs/hdmi-codec.c | 113 ++++++++++++++++------------------ + 1 file changed, 52 insertions(+), 61 deletions(-) + +diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c +index 403d4c6a49a8..7505c3eee4c1 100644 +--- a/sound/soc/codecs/hdmi-codec.c ++++ b/sound/soc/codecs/hdmi-codec.c +@@ -195,78 +195,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = { + */ + static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = { + { .ca_id = 0x00, .n_ch = 2, +- .mask = FL | FR}, +- /* 2.1 */ +- { .ca_id = 0x01, .n_ch = 4, +- .mask = FL | FR | LFE}, +- /* Dolby Surround */ ++ .mask = FL | FR }, ++ { .ca_id = 0x03, .n_ch = 4, ++ .mask = FL | FR | LFE | FC }, + { .ca_id = 0x02, .n_ch = 4, + .mask = FL | FR | FC }, +- /* surround51 */ ++ { .ca_id = 0x01, .n_ch = 4, ++ .mask = FL | FR | LFE }, + { .ca_id = 0x0b, .n_ch = 6, +- .mask = FL | FR | LFE | FC | RL | RR}, +- /* surround40 */ +- { .ca_id = 0x08, .n_ch = 6, +- .mask = FL | FR | RL | RR }, +- /* surround41 */ +- { .ca_id = 0x09, .n_ch = 6, +- .mask = FL | FR | LFE | RL | RR }, +- /* surround50 */ ++ .mask = FL | FR | LFE | FC | RL | RR }, + { .ca_id = 0x0a, .n_ch = 6, + .mask = FL | FR | FC | RL | RR }, +- /* 6.1 */ +- { .ca_id = 0x0f, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RL | RR | RC }, +- /* surround71 */ ++ { .ca_id = 0x09, .n_ch = 6, ++ .mask = FL | FR | LFE | RL | RR }, ++ { .ca_id = 0x08, .n_ch = 6, ++ .mask = FL | FR | RL | RR }, ++ { .ca_id = 0x07, .n_ch = 6, ++ .mask = FL | FR | LFE | FC | RC }, ++ { .ca_id = 0x06, .n_ch = 6, ++ .mask = FL | FR | FC | RC }, ++ { .ca_id = 0x05, .n_ch = 6, ++ .mask = FL | FR | LFE | RC }, ++ { .ca_id = 0x04, .n_ch = 6, ++ .mask = FL | FR | RC }, + { .ca_id = 0x13, .n_ch = 8, + .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC }, +- /* others */ +- { .ca_id = 0x03, .n_ch = 8, +- .mask = FL | FR | LFE | FC }, +- { .ca_id = 0x04, .n_ch = 8, +- .mask = FL | FR | RC}, +- { .ca_id = 0x05, .n_ch = 8, +- .mask = FL | FR | LFE | RC }, +- { .ca_id = 0x06, .n_ch = 8, +- .mask = FL | FR | FC | RC }, +- { .ca_id = 0x07, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RC }, +- { .ca_id = 0x0c, .n_ch = 8, +- .mask = FL | FR | RC | RL | RR }, +- { .ca_id = 0x0d, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | RC }, +- { .ca_id = 0x0e, .n_ch = 8, +- .mask = FL | FR | FC | RL | RR | RC }, +- { .ca_id = 0x10, .n_ch = 8, +- .mask = FL | FR | RL | RR | RLC | RRC }, +- { .ca_id = 0x11, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1f, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, + { .ca_id = 0x12, .n_ch = 8, + .mask = FL | FR | FC | RL | RR | RLC | RRC }, +- { .ca_id = 0x14, .n_ch = 8, +- .mask = FL | FR | FLC | FRC }, +- { .ca_id = 0x15, .n_ch = 8, +- .mask = FL | FR | LFE | FLC | FRC }, +- { .ca_id = 0x16, .n_ch = 8, +- .mask = FL | FR | FC | FLC | FRC }, +- { .ca_id = 0x17, .n_ch = 8, +- .mask = FL | FR | LFE | FC | FLC | FRC }, +- { .ca_id = 0x18, .n_ch = 8, +- .mask = FL | FR | RC | FLC | FRC }, +- { .ca_id = 0x19, .n_ch = 8, +- .mask = FL | FR | LFE | RC | FLC | FRC }, +- { .ca_id = 0x1a, .n_ch = 8, +- .mask = FL | FR | RC | FC | FLC | FRC }, +- { .ca_id = 0x1b, .n_ch = 8, +- .mask = FL | FR | LFE | RC | FC | FLC | FRC }, +- { .ca_id = 0x1c, .n_ch = 8, +- .mask = FL | FR | RL | RR | FLC | FRC }, +- { .ca_id = 0x1d, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | FLC | FRC }, + { .ca_id = 0x1e, .n_ch = 8, + .mask = FL | FR | FC | RL | RR | FLC | FRC }, +- { .ca_id = 0x1f, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, ++ { .ca_id = 0x11, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1d, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | FLC | FRC }, ++ { .ca_id = 0x10, .n_ch = 8, ++ .mask = FL | FR | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1c, .n_ch = 8, ++ .mask = FL | FR | RL | RR | FLC | FRC }, ++ { .ca_id = 0x0f, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | RL | RR | RC }, ++ { .ca_id = 0x1b, .n_ch = 8, ++ .mask = FL | FR | LFE | RC | FC | FLC | FRC }, ++ { .ca_id = 0x0e, .n_ch = 8, ++ .mask = FL | FR | FC | RL | RR | RC }, ++ { .ca_id = 0x1a, .n_ch = 8, ++ .mask = FL | FR | RC | FC | FLC | FRC }, ++ { .ca_id = 0x0d, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | RC }, ++ { .ca_id = 0x19, .n_ch = 8, ++ .mask = FL | FR | LFE | RC | FLC | FRC }, ++ { .ca_id = 0x0c, .n_ch = 8, ++ .mask = FL | FR | RC | RL | RR }, ++ { .ca_id = 0x18, .n_ch = 8, ++ .mask = FL | FR | RC | FLC | FRC }, ++ { .ca_id = 0x17, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | FLC | FRC }, ++ { .ca_id = 0x16, .n_ch = 8, ++ .mask = FL | FR | FC | FLC | FRC }, ++ { .ca_id = 0x15, .n_ch = 8, ++ .mask = FL | FR | LFE | FLC | FRC }, ++ { .ca_id = 0x14, .n_ch = 8, ++ .mask = FL | FR | FLC | FRC }, + }; + + struct hdmi_codec_priv {