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Merge pull request #9332 from heitbaum/nxp

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Update NXP Initial support Cadence MHDP8501(HDMI/DP) for i.MX8MQ patch and add support for Coral Edge TPU Development Board
This commit is contained in:
Jernej Škrabec 2024-10-04 06:32:17 +02:00 committed by GitHub
commit 4d9d2c5cf6
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GPG Key ID: B5690EEEBB952194
58 changed files with 6345 additions and 13393 deletions
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24
packages/linux-firmware/firmware-imx/package.mk
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@ -3,9 +3,9 @@
# Copyright (C) 2019-present Team LibreELEC (https://libreelec.tv)
PKG_NAME="firmware-imx"
PKG_VERSION="8.21"
PKG_SHA256="c3447f0f813415ccea9dc2ef12080cb3ac8bbc0c67392a74fc7d59205eb5a672"
PKG_ARCH="arm"
PKG_VERSION="8.25-27879f8"
PKG_SHA256="55766dad38961fde3ed3224ee6a46ab1c5aea62a5b947530228d8fbc4a7d2816"
PKG_ARCH="aarch64 arm"
PKG_LICENSE="other"
PKG_SITE="http://www.freescale.com"
PKG_URL="https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/${PKG_NAME}-${PKG_VERSION}.bin"
@ -20,11 +20,17 @@ unpack() {
makeinstall_target() {
mkdir -p ${INSTALL}/$(get_full_firmware_dir)/imx/sdma
cp -P firmware/sdma/sdma-imx6q.bin ${INSTALL}/$(get_full_firmware_dir)/imx/sdma
cp -P firmware/sdma/sdma-imx7d.bin ${INSTALL}/$(get_full_firmware_dir)/imx/sdma
mkdir -p ${INSTALL}/$(get_full_firmware_dir)/vpu
cp -P firmware/vpu/vpu_fw_imx6d.bin ${INSTALL}/$(get_full_firmware_dir)/vpu
cp -P firmware/vpu/vpu_fw_imx6q.bin ${INSTALL}/$(get_full_firmware_dir)/vpu
cp -P firmware/vpu/vpu_fw_imx8_dec.bin ${INSTALL}/$(get_full_firmware_dir)/vpu
case "${DEVICE}" in
"iMX6")
cp -P firmware/sdma/sdma-imx6q.bin ${INSTALL}/$(get_full_firmware_dir)/imx/sdma
cp -P firmware/vpu/vpu_fw_imx6d.bin ${INSTALL}/$(get_full_firmware_dir)/vpu
cp -P firmware/vpu/vpu_fw_imx6q.bin ${INSTALL}/$(get_full_firmware_dir)/vpu
;;
"iMX8")
cp -P firmware/sdma/sdma-imx7d.bin ${INSTALL}/$(get_full_firmware_dir)/imx/sdma
cp -P firmware/vpu/vpu_fw_imx8_dec.bin ${INSTALL}/$(get_full_firmware_dir)/vpu
;;
esac
}

15
projects/NXP/README.md Normal file
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@ -0,0 +1,15 @@
# NXP
This project is for NXP SoC devices
## Devices
**iMX6**
* [Cubox-i](devices/iMX6)
* [Udoo](devices/iMX6)
* [Wandboard](devices/iMX6)
**iMX8**
* [Coral Edge TPU Development Board](devices/iMX8)
* [i.MX8MQ EVK](devices/iMX8)
* [TechNexion PICO-PI-8M](devices/iMX8)

472
projects/NXP/devices/iMX8/linux/linux.aarch64.conf
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File diff suppressed because it is too large Load Diff

5662
projects/NXP/devices/iMX8/patches/linux/0001-Initial-support-Cadence-MHDP8501-HDMI-DP-for-i-MX8MQ.patch Normal file
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File diff suppressed because it is too large Load Diff

5938
projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch
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File diff suppressed because it is too large Load Diff

32
projects/NXP/devices/iMX8/patches/linux/0002-MLK-24065-1-drm-bridge-cadence-fix-dp_aux_transfer-w.patch
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@ -1,32 +0,0 @@
From 55eb19200d650ead73139ee8444db9119718fd31 Mon Sep 17 00:00:00 2001
From: Sergey Zhuravlevich <zhurxx@gmail.com>
Date: Tue, 12 May 2020 14:23:15 +0200
Subject: [PATCH 02/49] MLK-24065-1: drm: bridge: cadence: fix dp_aux_transfer
write return value
After exiting the loop in DP_AUX_NATIVE_WRITE it was returning 0. It's supposed
to return the number of bytes transferred on success.
Signed-off-by: Sergey Zhuravlevich <zhurxx@gmail.com>
Acked-by: Sandor Yu <sandor.yu@nxp.com>
Tested-By: Sandor Yu <sandor.yu@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-dp-core.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
index acb5c860da73..aa92029f44e9 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
@@ -67,6 +67,8 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *aux,
return ret;
}
+ msg->reply = DP_AUX_NATIVE_REPLY_ACK;
+ return msg->size;
}
if (msg->request == DP_AUX_NATIVE_READ) {
--
2.29.2

64
projects/NXP/devices/iMX8/patches/linux/0002-arm64-dts-fsl-imx8mq-evk-enable-DCSS-and-HDMI.patch Normal file
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@ -0,0 +1,64 @@
From 5825e6107062b231f1c7449502e04e559f8266e8 Mon Sep 17 00:00:00 2001
From: Lucas Stach <l.stach@pengutronix.de>
Date: Tue, 13 Feb 2018 12:47:09 +0100
Subject: [PATCH 1/4] arm64: dts: fsl: imx8mq-evk: enable DCSS and HDMI
Adapted for [PATCH v16] Initial support Cadence MHDP8501(HDMI/DP) for i.MX8MQ
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 31 ++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 7507548cdb16..267e32895aa0 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -139,6 +139,17 @@ sound-hdmi-arc {
spdif-controller = <&spdif2>;
spdif-in;
};
+
+ hdmi_connector: connector {
+ compatible = "hdmi-connector";
+ label = "X11";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ };
+ };
+ };
};
&A53_0 {
@@ -226,6 +237,26 @@ wl-reg-on-hog {
};
};
+&dcss {
+ status = "okay";
+};
+
+&hdmi_connector {
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&mhdp_out>;
+ };
+ };
+};
+
+&mhdp {
+ status = "okay";
+};
+
+&mhdp_out {
+ remote-endpoint = <&hdmi_connector_in>;
+};
+
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
--
2.43.0

66
projects/NXP/devices/iMX8/patches/linux/0003-MLK-24065-3-drm-bridge-cadence-use-the-lane-mapping-.patch
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@ -1,66 +0,0 @@
From 90e1a010995c0a87b0216706b1255ca5d0c36286 Mon Sep 17 00:00:00 2001
From: Sergey Zhuravlevich <zhurxx@gmail.com>
Date: Tue, 12 May 2020 14:23:15 +0200
Subject: [PATCH 03/49] MLK-24065-3: drm: bridge: cadence: use the lane mapping
from dt when setting host capabilities
Signed-off-by: Sergey Zhuravlevich <zhurxx@gmail.com>
Acked-by: Sandor Yu <sandor.yu@nxp.com>
Tested-By: Sandor Yu <sandor.yu@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-dp-core.c | 2 +-
drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c | 4 ++--
include/drm/bridge/cdns-mhdp.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
index aa92029f44e9..c059d56b4f46 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
@@ -152,7 +152,7 @@ static void cdns_dp_mode_set(struct cdns_mhdp_device *mhdp)
cdns_mhdp_reg_write(mhdp, LANES_CONFIG, 0x00400000 | lane_mapping);
/* Set DP host capability */
- ret = cdns_mhdp_set_host_cap(mhdp, false);
+ ret = cdns_mhdp_set_host_cap(mhdp);
if (ret) {
DRM_DEV_ERROR(mhdp->dev, "Failed to set host cap %d\n", ret);
return;
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
index 91d1cfd4b2af..9c0a2668e494 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
@@ -438,7 +438,7 @@ int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool enable)
}
EXPORT_SYMBOL(cdns_mhdp_set_firmware_active);
-int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp, bool flip)
+int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp)
{
u8 msg[8];
int ret;
@@ -449,7 +449,7 @@ int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp, bool flip)
msg[3] = PRE_EMPHASIS_LEVEL_3;
msg[4] = PTS1 | PTS2 | PTS3 | PTS4;
msg[5] = FAST_LT_NOT_SUPPORT;
- msg[6] = flip ? LANE_MAPPING_FLIPPED : LANE_MAPPING_NORMAL;
+ msg[6] = mhdp->lane_mapping;
msg[7] = ENHANCED;
ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
diff --git a/include/drm/bridge/cdns-mhdp.h b/include/drm/bridge/cdns-mhdp.h
index d76716d4edc6..4dc6e428b5f7 100644
--- a/include/drm/bridge/cdns-mhdp.h
+++ b/include/drm/bridge/cdns-mhdp.h
@@ -723,7 +723,7 @@ u32 cdns_mhdp_get_fw_clk(struct cdns_mhdp_device *mhdp);
int cdns_mhdp_load_firmware(struct cdns_mhdp_device *mhdp, const u32 *i_mem,
u32 i_size, const u32 *d_mem, u32 d_size);
int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool enable);
-int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp, bool flip);
+int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp);
int cdns_mhdp_event_config(struct cdns_mhdp_device *mhdp);
u32 cdns_mhdp_get_event(struct cdns_mhdp_device *mhdp);
int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8 value);
--
2.29.2

55
projects/NXP/devices/iMX8/patches/linux/0003-arm64-dts-fsl-imx8mq-pico-pi-enable-DCSS-and-HDMI.patch Normal file
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@ -0,0 +1,55 @@
From 6b9309988072e3b5b7b3900a1254507316eb72cf Mon Sep 17 00:00:00 2001
From: Lukas Rusak <lorusak@gmail.com>
Date: Tue, 9 Mar 2021 10:47:27 -0800
Subject: [PATCH 2/4] arm64: dts: fsl: imx8mq-pico-pi: enable DCSS and HDMI
Adapted for [PATCH v16] Initial support Cadence MHDP8501(HDMI/DP) for i.MX8MQ
---
.../boot/dts/freescale/imx8mq-pico-pi.dts | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
index 89cbec5c41b2..5e2b1a84a85e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
@@ -54,6 +54,37 @@ ethphy0: ethernet-phy@1 {
reg = <1>;
};
};
+
+ hdmi_connector: connector {
+ compatible = "hdmi-connector";
+ label = "X11";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ };
+ };
+ };
+};
+
+&dcss {
+ status = "okay";
+};
+
+&hdmi_connector {
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&mhdp_out>;
+ };
+ };
+};
+
+&mhdp {
+ status = "okay";
+};
+
+&mhdp_out {
+ remote-endpoint = <&hdmi_connector_in>;
};
&i2c1 {
--
2.43.0

31
projects/NXP/devices/iMX8/patches/linux/0004-MLK-24065-2-drm-bridge-cadence-print-error-when-cloc.patch
View File

@ -1,31 +0,0 @@
From 62c1852bc0f94efb6884d34c2c27dcf1efa3b282 Mon Sep 17 00:00:00 2001
From: Sergey Zhuravlevich <zhurxx@gmail.com>
Date: Tue, 12 May 2020 14:23:15 +0200
Subject: [PATCH 04/49] MLK-24065-2: drm: bridge: cadence: print error when
clock recovery fails
Signed-off-by: Sergey Zhuravlevich <zhurxx@gmail.com>
Acked-by: Sandor Yu <sandor.yu@nxp.com>
Tested-By: Sandor Yu <sandor.yu@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c
index f025c39d12ea..a032e19765a4 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-dp.c
@@ -106,7 +106,9 @@ static int cdns_mhdp_training_start(struct cdns_mhdp_device *mhdp)
if (ret)
goto err_training_start;
- if (event[1] & EQ_PHASE_FINISHED)
+ if (event[1] & CLK_RECOVERY_FAILED)
+ DRM_DEV_ERROR(mhdp->dev, "clock recovery failed\n");
+ else if (event[1] & EQ_PHASE_FINISHED)
return 0;
}
--
2.29.2

62
projects/NXP/devices/iMX8/patches/linux/0004-arm64-dts-fsl-imx8mq-phanbell.dts-enable-DCSS-and-HD.patch Normal file
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@ -0,0 +1,62 @@
From d7a46875e8cc330cc3f1082c054ecfb0c1b32727 Mon Sep 17 00:00:00 2001
From: Rudi Heitbaum <rudi@heitbaum.com>
Date: Sun, 29 Sep 2024 21:08:57 +1000
Subject: [PATCH 3/4] arm64: dts: fsl: imx8mq-phanbell.dts: enable DCSS and
HDMI
---
.../boot/dts/freescale/imx8mq-phanbell.dts | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
index a3b9d615a3b4..deba4a6f65d5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
@@ -46,6 +46,17 @@ fan: gpio-fan {
pinctrl-0 = <&pinctrl_gpio_fan>;
status = "okay";
};
+
+ hdmi_connector: connector {
+ compatible = "hdmi-connector";
+ label = "X11";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ };
+ };
+ };
};
&A53_0 {
@@ -111,6 +122,26 @@ map4 {
};
};
+&dcss {
+ status = "okay";
+};
+
+&hdmi_connector {
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&mhdp_out>;
+ };
+ };
+};
+
+&mhdp {
+ status = "okay";
+};
+
+&mhdp_out {
+ remote-endpoint = <&hdmi_connector_in>;
+};
+
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
--
2.43.0

37
projects/NXP/devices/iMX8/patches/linux/0005-LF-1511-drm-cdn-cec-replace-i-with-i-in-loop.patch
View File

@ -1,37 +0,0 @@
From eb19fd99254d6a0aa97bb08c09b9f82ebff306c5 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Fri, 19 Jun 2020 15:32:28 +0800
Subject: [PATCH 05/49] LF-1511: drm: cdn-cec: replace ++i with i++ in loop
replace ++i with i++ in loop to prevent Coverity issue.
Coverity ID 9000767
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c
index 5717bb0bcb75..029ad761606a 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c
@@ -163,13 +163,13 @@ static int mhdp_cec_set_logical_addr(struct cdns_mhdp_cec *cec, u32 la)
if (la == CEC_LOG_ADDR_INVALID)
/* invalid all LA address */
- for (i = 0; i < CEC_MAX_LOG_ADDRS; ++i) {
+ for (i = 0; i < CEC_MAX_LOG_ADDRS; i++) {
mhdp_cec_write(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF), 0);
return 0;
}
/* In fact cdns mhdp cec could support max 5 La address */
- for (i = 0; i < CEC_MAX_LOG_ADDRS; ++i) {
+ for (i = 0; i < CEC_MAX_LOG_ADDRS; i++) {
la_reg = mhdp_cec_read(cec, LOGICAL_ADDRESS_LA0 + (i * REG_ADDR_OFF));
/* Check LA already used */
if (la_reg & 0x10)
--
2.29.2

28
projects/NXP/devices/iMX8/patches/linux/0005-arm64-dts-fsl-imx8mq-phanbell.dts-enable-PCI.patch Normal file
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@ -0,0 +1,28 @@
From 352c7ed9d658a793eba747744e5ec330877e7f50 Mon Sep 17 00:00:00 2001
From: Rudi Heitbaum <rudi@heitbaum.com>
Date: Tue, 1 Oct 2024 06:53:51 +0000
Subject: [PATCH 4/4] arm64: dts: fsl: imx8mq-phanbell.dts: enable PCI
---
arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
index deba4a6f65d5..ed7d3e39af9a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
@@ -510,3 +510,11 @@ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
+
+&pcie0 {
+ status = "disabled";
+};
+
+&pcie1 {
+ status = "okay";
+};
--
2.43.0

30
projects/NXP/devices/iMX8/patches/linux/0006-LF-1512-drm-cdns-mhdp-avoid-potentially-overflowing.patch
View File

@ -1,30 +0,0 @@
From 09dfa5b8ba1a38050e4e95faab1cf07c6a509dad Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Fri, 19 Jun 2020 16:05:42 +0800
Subject: [PATCH 06/49] LF-1512: drm: cdns mhdp: avoid potentially overflowing
covert to unsigned 64 bits to avoid potentially overflowing.
Report by Coverity ID 6652952 6652952.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
index 9c0a2668e494..890add9b7c67 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
@@ -657,7 +657,7 @@ int cdns_mhdp_config_video(struct cdns_mhdp_device *mhdp)
*/
do {
tu_size_reg += 2;
- symbol = tu_size_reg * mode->clock * bit_per_pix;
+ symbol = (u64) tu_size_reg * mode->clock * bit_per_pix;
do_div(symbol, mhdp->dp.num_lanes * link_rate * 8);
rem = do_div(symbol, 1000);
if (tu_size_reg > 64) {
--
2.29.2

41
projects/NXP/devices/iMX8/patches/linux/0007-MLK-24335-drm-bridge-cdns-hdmi-support-work-in-DVI-m.patch
View File

@ -1,41 +0,0 @@
From a1b02ef19cbc24603e1e212f4f4258ca2c59aaad Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Thu, 18 Jun 2020 14:18:04 +0800
Subject: [PATCH 07/49] MLK-24335: drm: bridge: cdns: hdmi support work in DVI
mode
hdmi support work in DVI mode.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
index da40f62617ef..5f2442fa761f 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
@@ -32,8 +32,9 @@ static void hdmi_sink_config(struct cdns_mhdp_device *mhdp)
struct drm_scdc *scdc = &mhdp->connector.base.display_info.hdmi.scdc;
u8 buff = 0;
- /* Default work in HDMI1.4 */
- mhdp->hdmi.hdmi_type = MODE_HDMI_1_4;
+ /* return if hdmi work in DVI mode */
+ if (mhdp->hdmi.hdmi_type == MODE_DVI)
+ return;
/* check sink support SCDC or not */
if (scdc->supported != true) {
@@ -264,6 +265,8 @@ static int cdns_hdmi_connector_get_modes(struct drm_connector *connector)
edid->header[6], edid->header[7]);
drm_connector_update_edid_property(connector, edid);
num_modes = drm_add_edid_modes(connector, edid);
+ mhdp->hdmi.hdmi_type = drm_detect_hdmi_monitor(edid) ?
+ MODE_HDMI_1_4 : MODE_DVI;
kfree(edid);
}
--
2.29.2

42
projects/NXP/devices/iMX8/patches/linux/0008-LF-1762-21-gpu-drm-bridge-cadence-hdmi-update-API-.m.patch
View File

@ -1,42 +0,0 @@
From 83f932299b9969a1823b085d2269db677362f897 Mon Sep 17 00:00:00 2001
From: Dong Aisheng <aisheng.dong@nxp.com>
Date: Tue, 14 Jul 2020 19:18:25 +0800
Subject: [PATCH 08/49] LF-1762-21 gpu: drm: bridge: cadence: hdmi: update API
.mode_valid()
API changed since:
12c683e12cd8 ("drm: bridge: Pass drm_display_info to drm_bridge_funcs .mode_valid()")
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-dp-core.c | 1 +
drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
index c059d56b4f46..cb4897c664f0 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
@@ -256,6 +256,7 @@ static int cdns_dp_bridge_attach(struct drm_bridge *bridge,
static enum drm_mode_status
cdns_dp_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_info *info,
const struct drm_display_mode *mode)
{
enum drm_mode_status mode_status = MODE_OK;
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
index 5f2442fa761f..1e5130e295f7 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
@@ -359,6 +359,7 @@ static int cdns_hdmi_bridge_attach(struct drm_bridge *bridge,
static enum drm_mode_status
cdns_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_info *info,
const struct drm_display_mode *mode)
{
struct cdns_mhdp_device *mhdp = bridge->driver_private;
--
2.29.2

107
projects/NXP/devices/iMX8/patches/linux/0009-LF-2271-1-drm-bridge-cdns-Use-colorspace-connector-p.patch
View File

@ -1,107 +0,0 @@
From 150d291f3e5cb47a97790b89e79d8f1a5aa797dd Mon Sep 17 00:00:00 2001
From: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Date: Fri, 28 Aug 2020 10:26:31 +0300
Subject: [PATCH 09/49] LF-2271-1: drm/bridge/cdns: Use colorspace connector
property for imx8mq
This patch achieves 2 goals:
* Make use of colorspace property when setting up the color_depth and
color_fmt. The userspace can now choose which colorspace to use by changing
the colorspace property;
* Do not use drm_display_mode private_flags to signal CRTC which pixel encoding
is being used by connector. Upstream is getting rid of 'private_flags' usage
and the declaration will probably be removed in the next release;
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
---
.../gpu/drm/bridge/cadence/cdns-hdmi-core.c | 58 ++++++++++++-------
1 file changed, 36 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
index 1e5130e295f7..2796252adf68 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
@@ -412,6 +412,7 @@ bool cdns_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
struct drm_display_mode *adjusted_mode)
{
struct cdns_mhdp_device *mhdp = bridge->driver_private;
+ struct drm_connector_state *conn_state = mhdp->connector.base.state;
struct drm_display_info *di = &mhdp->connector.base.display_info;
struct video_info *video = &mhdp->video_info;
int vic = drm_match_cea_mode(mode);
@@ -428,36 +429,49 @@ bool cdns_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
}
/* imx8mq */
- if (vic == 97 || vic == 96) {
- if (di->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
- video->color_depth = 12;
- else if (di->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
- video->color_depth = 10;
-
- if (drm_mode_is_420_only(di, mode) ||
- (drm_mode_is_420_also(di, mode) &&
- video->color_depth > 8)) {
+ if (conn_state->colorspace == DRM_MODE_COLORIMETRY_DEFAULT)
+ return !drm_mode_is_420_only(di, mode);
+
+ if (conn_state->colorspace == DRM_MODE_COLORIMETRY_BT2020_RGB) {
+ if (drm_mode_is_420_only(di, mode))
+ return false;
+
+ /* 10b RGB is not supported for following VICs */
+ if (vic == 97 || vic == 96 || vic == 95 || vic == 93 || vic == 94)
+ return false;
+
+ video->color_depth = 10;
+
+ return true;
+ }
+
+ if (conn_state->colorspace == DRM_MODE_COLORIMETRY_BT2020_CYCC ||
+ conn_state->colorspace == DRM_MODE_COLORIMETRY_BT2020_YCC) {
+ if (drm_mode_is_420_only(di, mode)) {
video->color_fmt = YCBCR_4_2_0;
- adjusted_mode->private_flags = 1;
+ if (di->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)
+ video->color_depth = 12;
+ else if (di->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)
+ video->color_depth = 10;
+ else
+ return false;
+
return true;
}
- video->color_depth = 8;
- return true;
- }
+ video->color_fmt = YCBCR_4_2_2;
+
+ if (!(di->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36))
+ return false;
- /* Any defined maximum tmds clock limit we must not exceed*/
- if ((di->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36) &&
- (mode->clock * 3 / 2 <= di->max_tmds_clock))
video->color_depth = 12;
- else if ((di->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) &&
- (mode->clock * 5 / 4 <= di->max_tmds_clock))
- video->color_depth = 10;
- /* 10-bit color depth for the following modes is not supported */
- if ((vic == 95 || vic == 94 || vic == 93) && video->color_depth == 10)
- video->color_depth = 8;
+ return true;
+ }
+
+ video->color_fmt = drm_mode_is_420_only(di, mode) ? YCBCR_4_2_0 : YCBCR_4_4_4;
+ video->color_depth = 8;
return true;
}
--
2.29.2

34
projects/NXP/devices/iMX8/patches/linux/0010-MLK-24770-drm-mhdp-Sync-DPTX-capability-with-Cadence.patch
View File

@ -1,34 +0,0 @@
From 04a71f1da60e51f277d4979c698e52cacb028666 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Mon, 14 Sep 2020 15:06:35 +0800
Subject: [PATCH 10/49] MLK-24770: drm: mhdp: Sync DPTX capability with Cadence
sample code
Sync the max vswing and pre-emphasis setting with Cadence sample code.
The max vswing is VOLTAGE_LEVEL_3 and
the max pre-emphasis is PRE_EMPHASIS_LEVEL_2 now.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
index 890add9b7c67..2043016f176b 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
@@ -445,8 +445,8 @@ int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp)
msg[0] = drm_dp_link_rate_to_bw_code(mhdp->dp.rate);
msg[1] = mhdp->dp.num_lanes | SCRAMBLER_EN;
- msg[2] = VOLTAGE_LEVEL_2;
- msg[3] = PRE_EMPHASIS_LEVEL_3;
+ msg[2] = VOLTAGE_LEVEL_3;
+ msg[3] = PRE_EMPHASIS_LEVEL_2;
msg[4] = PTS1 | PTS2 | PTS3 | PTS4;
msg[5] = FAST_LT_NOT_SUPPORT;
msg[6] = mhdp->lane_mapping;
--
2.29.2

48
projects/NXP/devices/iMX8/patches/linux/0011-MLK-24520-drm-bridge-cdns-increase-maximum-width-fro.patch
View File

@ -1,48 +0,0 @@
From 11b66e4bdb8ba6dc4e6981ecef69534c3d6d8df8 Mon Sep 17 00:00:00 2001
From: "Oliver F. Brown" <oliver.brown@nxp.com>
Date: Thu, 23 Jul 2020 18:24:23 -0500
Subject: [PATCH 11/49] MLK-24520: drm: bridge: cdns: increase maximum width
from 4096 to 5120.
This patch increases the maximum width to 5120.
Signed-off-by: Oliver F. Brown <oliver.brown@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-dp-core.c | 4 ++--
drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
index cb4897c664f0..0f2a38d19a57 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
@@ -270,8 +270,8 @@ cdns_dp_bridge_mode_valid(struct drm_bridge *bridge,
if (mode->clock > 594000)
return MODE_CLOCK_HIGH;
- /* 4096x2160 is not supported now */
- if (mode->hdisplay > 3840)
+ /* 5120 x 2160 is the maximum supported resulution */
+ if (mode->hdisplay > 5120)
return MODE_BAD_HVALUE;
if (mode->vdisplay > 2160)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
index 2796252adf68..442df6284c49 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
@@ -375,8 +375,8 @@ cdns_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
if (mode->clock > 594000)
return MODE_CLOCK_HIGH;
- /* 4096x2160 is not supported */
- if (mode->hdisplay > 3840 || mode->vdisplay > 2160)
+ /* 5120 x 2160 is the maximum supported resolution */
+ if (mode->hdisplay > 5120 || mode->vdisplay > 2160)
return MODE_BAD_HVALUE;
mhdp->valid_mode = mode;
--
2.29.2

44
projects/NXP/devices/iMX8/patches/linux/0012-MLK-24521-drm-bridge-hdmi-Prevent-the-driver-from-re.patch
View File

@ -1,44 +0,0 @@
From 4cb4fe3262fbbf6b31731b6b076698bcf951b9a1 Mon Sep 17 00:00:00 2001
From: "Oliver F. Brown" <oliver.brown@nxp.com>
Date: Fri, 24 Jul 2020 14:28:05 -0500
Subject: [PATCH 12/49] MLK-24521: drm: bridge: hdmi: Prevent the driver from
rejecting VIC 0 modes
iMX8QM can support the non CEA modes, iMX8M cannot support non CEA modes.
So driver should allow non CEA modes for iMX8QM.
Signed-off-by: Oliver F. Brown <oliver.brown@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
index 442df6284c49..a8fa559de9e9 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
@@ -364,6 +364,7 @@ cdns_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
{
struct cdns_mhdp_device *mhdp = bridge->driver_private;
enum drm_mode_status mode_status = MODE_OK;
+ u32 vic;
int ret;
/* We don't support double-clocked and Interlaced modes */
@@ -379,6 +380,13 @@ cdns_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
if (mode->hdisplay > 5120 || mode->vdisplay > 2160)
return MODE_BAD_HVALUE;
+ /* imx8mq-hdmi does not support non CEA modes */
+ if (!strncmp("imx8mq-hdmi", mhdp->plat_data->plat_name, 11)) {
+ vic = drm_match_cea_mode(mode);
+ if (vic == 0)
+ return MODE_BAD;
+ }
+
mhdp->valid_mode = mode;
ret = cdns_mhdp_plat_call(mhdp, phy_video_valid);
if (ret == false)
--
2.29.2

116
projects/NXP/devices/iMX8/patches/linux/0013-MLK-23642-1-drm-bridge-cadence-support-HBR-and-6-cha.patch
View File

@ -1,116 +0,0 @@
From cd7804fc3777e0b53d69d34058fee39accc72072 Mon Sep 17 00:00:00 2001
From: Shengjiu Wang <shengjiu.wang@nxp.com>
Date: Wed, 29 Apr 2020 17:34:07 +0800
Subject: [PATCH 13/49] MLK-23642-1: drm: bridge: cadence: support HBR and 6
channel
Support HBR and 6 channel.
For HBR, it only support compressed bitstream, sample rate
is 192kHz, and 8 channels.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
---
.../gpu/drm/bridge/cadence/cdns-mhdp-audio.c | 33 ++++++++++++++-----
include/drm/bridge/cdns-mhdp.h | 1 +
2 files changed, 26 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c
index 86174fb633bc..fa1dcf781539 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c
@@ -72,6 +72,8 @@ static void hdmi_audio_avi_set(struct cdns_mhdp_device *mhdp,
frame.channel_allocation = 0;
else if (channels == 4)
frame.channel_allocation = 0x3;
+ else if (channels == 6)
+ frame.channel_allocation = 0xB;
else if (channels == 8)
frame.channel_allocation = 0x13;
@@ -143,26 +145,38 @@ static void cdns_mhdp_audio_config_i2s(struct cdns_mhdp_device *mhdp,
{
int sub_pckt_num = 1, i2s_port_en_val = 0xf, i;
int idx = select_N_index(mhdp->mode.clock);
+ int numofchannels = audio->channels;
u32 val, ncts;
+ u32 disable_port3 = 0;
+ u32 audio_type = 0x2; /* L-PCM */
+ u32 transmission_type = 0; /* not required for L-PCM */
- if (audio->channels == 2) {
+ if (numofchannels == 2) {
if (mhdp->dp.num_lanes == 1)
sub_pckt_num = 2;
else
sub_pckt_num = 4;
i2s_port_en_val = 1;
- } else if (audio->channels == 4) {
+ } else if (numofchannels == 4) {
i2s_port_en_val = 3;
+ } else if (numofchannels == 6) {
+ numofchannels = 8;
+ disable_port3 = 1;
+ } else if ((numofchannels == 8) && (audio->non_pcm)) {
+ audio_type = 0x9; /* HBR packet type */
+ transmission_type = 0x9; /* HBR packet type */
}
cdns_mhdp_bus_write(0x0, mhdp, SPDIF_CTRL_ADDR);
- cdns_mhdp_bus_write(SYNC_WR_TO_CH_ZERO, mhdp, FIFO_CNTL);
+ val = SYNC_WR_TO_CH_ZERO;
+ val |= disable_port3 << 4;
+ cdns_mhdp_bus_write(val, mhdp, FIFO_CNTL);
- val = MAX_NUM_CH(audio->channels);
- val |= NUM_OF_I2S_PORTS(audio->channels);
- val |= AUDIO_TYPE_LPCM;
+ val = MAX_NUM_CH(numofchannels);
+ val |= NUM_OF_I2S_PORTS(numofchannels);
+ val |= audio_type << 7;
val |= CFG_SUB_PCKT_NUM(sub_pckt_num);
cdns_mhdp_bus_write(val, mhdp, SMPL2PKT_CNFG);
@@ -173,12 +187,13 @@ static void cdns_mhdp_audio_config_i2s(struct cdns_mhdp_device *mhdp,
else
val = 2 << 9;
- val |= AUDIO_CH_NUM(audio->channels);
+ val |= AUDIO_CH_NUM(numofchannels);
val |= I2S_DEC_PORT_EN(i2s_port_en_val);
val |= TRANS_SMPL_WIDTH_32;
+ val |= transmission_type << 13;
cdns_mhdp_bus_write(val, mhdp, AUDIO_SRC_CNFG);
- for (i = 0; i < (audio->channels + 1) / 2; i++) {
+ for (i = 0; i < (numofchannels + 1) / 2; i++) {
if (audio->sample_width == 16)
val = (0x02 << 8) | (0x02 << 20);
else if (audio->sample_width == 24)
@@ -323,6 +338,8 @@ static int audio_hw_params(struct device *dev, void *data,
goto out;
}
+ audio.non_pcm = params->iec.status[0] & IEC958_AES0_NONAUDIO;
+
ret = cdns_mhdp_audio_config(mhdp, &audio);
if (!ret)
mhdp->audio_info = audio;
diff --git a/include/drm/bridge/cdns-mhdp.h b/include/drm/bridge/cdns-mhdp.h
index 4dc6e428b5f7..1f8fd024cdfa 100644
--- a/include/drm/bridge/cdns-mhdp.h
+++ b/include/drm/bridge/cdns-mhdp.h
@@ -564,6 +564,7 @@ struct audio_info {
int channels;
int sample_width;
int connector_type;
+ bool non_pcm;
};
enum vic_pxl_encoding_format {
--
2.29.2

157
projects/NXP/devices/iMX8/patches/linux/0014-MLK-24611-2-drm-bridge-cdns-Add-callback-function-fo.patch
View File

@ -1,157 +0,0 @@
From 46bf1dc2ba34440e8f83b3f70e3e4d6b3f9e6183 Mon Sep 17 00:00:00 2001
From: Shengjiu Wang <shengjiu.wang@nxp.com>
Date: Mon, 31 Aug 2020 14:50:29 +0800
Subject: [PATCH 14/49] MLK-24611-2: drm: bridge: cdns: Add callback function
for plug/unplug event
cdns-hdmi-core exports a function cdns_hdmi_set_plugged_cb so
platform device can register the callback
implement hook_plugged_cb to register callback function for hdmi cable
plug/unplug event.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
---
.../gpu/drm/bridge/cadence/cdns-hdmi-core.c | 41 +++++++++++++++++--
.../gpu/drm/bridge/cadence/cdns-mhdp-audio.c | 10 +++++
include/drm/bridge/cdns-mhdp.h | 6 +++
3 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
index a8fa559de9e9..5890da8aa1a1 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
@@ -225,11 +225,35 @@ void cdns_hdmi_mode_set(struct cdns_mhdp_device *mhdp)
}
}
+static void handle_plugged_change(struct cdns_mhdp_device *mhdp, bool plugged)
+{
+ if (mhdp->plugged_cb && mhdp->codec_dev)
+ mhdp->plugged_cb(mhdp->codec_dev, plugged);
+}
+
+int cdns_hdmi_set_plugged_cb(struct cdns_mhdp_device *mhdp,
+ hdmi_codec_plugged_cb fn,
+ struct device *codec_dev)
+{
+ bool plugged;
+
+ mutex_lock(&mhdp->lock);
+ mhdp->plugged_cb = fn;
+ mhdp->codec_dev = codec_dev;
+ plugged = mhdp->last_connector_result == connector_status_connected;
+ handle_plugged_change(mhdp, plugged);
+ mutex_unlock(&mhdp->lock);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(cdns_hdmi_set_plugged_cb);
+
static enum drm_connector_status
cdns_hdmi_connector_detect(struct drm_connector *connector, bool force)
{
struct cdns_mhdp_device *mhdp =
container_of(connector, struct cdns_mhdp_device, connector.base);
+ enum drm_connector_status result;
u8 hpd = 0xf;
@@ -237,15 +261,25 @@ cdns_hdmi_connector_detect(struct drm_connector *connector, bool force)
if (hpd == 1)
/* Cable Connected */
- return connector_status_connected;
+ result = connector_status_connected;
else if (hpd == 0)
/* Cable Disconnedted */
- return connector_status_disconnected;
+ result = connector_status_disconnected;
else {
/* Cable status unknown */
DRM_INFO("Unknow cable status, hdp=%u\n", hpd);
- return connector_status_unknown;
+ result = connector_status_unknown;
+ }
+
+ mutex_lock(&mhdp->lock);
+ if (result != mhdp->last_connector_result) {
+ handle_plugged_change(mhdp,
+ result == connector_status_connected);
+ mhdp->last_connector_result = result;
}
+ mutex_unlock(&mhdp->lock);
+
+ return result;
}
static int cdns_hdmi_connector_get_modes(struct drm_connector *connector)
@@ -624,6 +658,7 @@ static int __cdns_hdmi_probe(struct platform_device *pdev,
#ifdef CONFIG_OF
mhdp->bridge.base.of_node = dev->of_node;
#endif
+ mhdp->last_connector_result = connector_status_disconnected;
memset(&pdevinfo, 0, sizeof(pdevinfo));
pdevinfo.parent = dev;
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c
index fa1dcf781539..f4f3f9ca437c 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c
@@ -380,11 +380,21 @@ static int audio_get_eld(struct device *dev, void *data,
return 0;
}
+static int audio_hook_plugged_cb(struct device *dev, void *data,
+ hdmi_codec_plugged_cb fn,
+ struct device *codec_dev)
+{
+ struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev);
+
+ return cdns_hdmi_set_plugged_cb(mhdp, fn, codec_dev);
+}
+
static const struct hdmi_codec_ops audio_codec_ops = {
.hw_params = audio_hw_params,
.audio_shutdown = audio_shutdown,
.digital_mute = audio_digital_mute,
.get_eld = audio_get_eld,
+ .hook_plugged_cb = audio_hook_plugged_cb,
};
int cdns_mhdp_register_audio_driver(struct device *dev)
diff --git a/include/drm/bridge/cdns-mhdp.h b/include/drm/bridge/cdns-mhdp.h
index 1f8fd024cdfa..6bfd82a3d9a2 100644
--- a/include/drm/bridge/cdns-mhdp.h
+++ b/include/drm/bridge/cdns-mhdp.h
@@ -22,6 +22,7 @@
#include <drm/display/drm_dp_mst_helper.h>
#include <media/cec.h>
#include <linux/bitops.h>
+#include <sound/hdmi-codec.h>
#define ADDR_IMEM 0x10000
#define ADDR_DMEM 0x20000
@@ -714,6 +715,9 @@ struct cdns_mhdp_device {
};
const struct cdns_plat_data *plat_data;
+ hdmi_codec_plugged_cb plugged_cb;
+ struct device *codec_dev;
+ enum drm_connector_status last_connector_result;
};
u32 cdns_mhdp_bus_read(struct cdns_mhdp_device *mhdp, u32 offset);
@@ -796,6 +800,8 @@ void cdns_dp_remove(struct platform_device *pdev);
void cdns_dp_unbind(struct device *dev);
int cdns_dp_bind(struct platform_device *pdev,
struct drm_encoder *encoder, struct cdns_mhdp_device *mhdp);
+int cdns_hdmi_set_plugged_cb(struct cdns_mhdp_device *mhdp, hdmi_codec_plugged_cb fn,
+ struct device *codec_dev);
/* CEC */
#ifdef CONFIG_DRM_CDNS_HDMI_CEC
--
2.29.2

43
projects/NXP/devices/iMX8/patches/linux/0015-gpu-drm-dridge-hdp-audio-change-to-mute_stream.patch
View File

@ -1,43 +0,0 @@
From 1b0a179061890c0a2f6748426f03e8cd2176d3e2 Mon Sep 17 00:00:00 2001
From: Dong Aisheng <aisheng.dong@nxp.com>
Date: Wed, 5 Aug 2020 21:31:04 +0800
Subject: [PATCH 15/49] gpu: drm: dridge: hdp-audio: change to mute_stream
To cope with upstream API change:
e2978c45e5ed ("ASoC: soc-dai: remove .digital_mute")
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c
index f4f3f9ca437c..85f526175439 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-audio.c
@@ -358,8 +358,8 @@ static void audio_shutdown(struct device *dev, void *data)
mhdp->audio_info.format = AFMT_UNUSED;
}
-static int audio_digital_mute(struct device *dev, void *data,
- bool enable)
+static int audio_mute_stream(struct device *dev, void *data,
+ bool enable, int direction)
{
struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev);
int ret;
@@ -392,9 +392,10 @@ static int audio_hook_plugged_cb(struct device *dev, void *data,
static const struct hdmi_codec_ops audio_codec_ops = {
.hw_params = audio_hw_params,
.audio_shutdown = audio_shutdown,
- .digital_mute = audio_digital_mute,
+ .mute_stream = audio_mute_stream,
.get_eld = audio_get_eld,
.hook_plugged_cb = audio_hook_plugged_cb,
+ .no_capture_mute = 1,
};
int cdns_mhdp_register_audio_driver(struct device *dev)
--
2.29.2

40
projects/NXP/devices/iMX8/patches/linux/0016-LF-2744-drm-cdns-reset-force_mode_set-flag-in-atomic.patch
View File

@ -1,40 +0,0 @@
From 4a406e182a709718a769c37d33530ed2e6b23b39 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Tue, 17 Nov 2020 15:47:36 +0800
Subject: [PATCH 16/49] LF-2744: drm: cdns: reset force_mode_set flag in
atomic_check
Reset force_mode_set flag in atomic_check function
to avoid set mode_changed flag multi times when cable plugin.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
index 5890da8aa1a1..e796c2c0e895 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
@@ -1,7 +1,7 @@
/*
* Cadence High-Definition Multimedia Interface (HDMI) driver
*
- * Copyright (C) 2019 NXP Semiconductor, Inc.
+ * Copyright (C) 2019-2020 NXP Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -445,8 +445,6 @@ static void cdns_hdmi_bridge_mode_set(struct drm_bridge *bridge,
mutex_lock(&mhdp->lock);
cdns_hdmi_mode_set(mhdp);
mutex_unlock(&mhdp->lock);
- /* reset force mode set flag */
- mhdp->force_mode_set = false;
}
bool cdns_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
--
2.29.2

271
projects/NXP/devices/iMX8/patches/linux/0017-MLK-24081-03-drm-bridge-cdns-cec-support-hdmi-rx-cec.patch
View File

@ -1,271 +0,0 @@
From f7f5ec54b815df2c9a92f0fd6edea4f5d0700937 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Mon, 16 Nov 2020 10:56:44 +0800
Subject: [PATCH 17/49] MLK-24081-03: drm: bridge: cdns-cec: support hdmi rx
cec
Create struct cdns_mhdp_cec and cec specific bus_read/write function.
CEC driver could be reuse by hdmi rx.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
---
drivers/gpu/drm/bridge/cadence/Kconfig | 1 -
.../gpu/drm/bridge/cadence/cdns-hdmi-core.c | 18 ++++-
.../gpu/drm/bridge/cadence/cdns-mhdp-cec.c | 66 +++++++++++++------
.../gpu/drm/bridge/cadence/cdns-mhdp-common.c | 6 --
include/drm/bridge/cdns-mhdp.h | 19 +++---
5 files changed, 72 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig b/drivers/gpu/drm/bridge/cadence/Kconfig
index bb1865b15aca..c271ab24a99a 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -45,6 +45,5 @@ config DRM_CDNS_AUDIO
config DRM_CDNS_HDMI_CEC
tristate "Cadence MHDP HDMI CEC driver"
- depends on DRM_CDNS_HDMI
select CEC_CORE
select CEC_NOTIFIER
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
index e796c2c0e895..84c175997740 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
@@ -569,6 +569,19 @@ static void cdns_hdmi_parse_dt(struct cdns_mhdp_device *mhdp)
dev_info(mhdp->dev, "lane-mapping 0x%02x\n", mhdp->lane_mapping);
}
+#ifdef CONFIG_DRM_CDNS_HDMI_CEC
+static void cdns_mhdp_cec_init(struct cdns_mhdp_device *mhdp)
+{
+ struct cdns_mhdp_cec *cec = &mhdp->hdmi.cec;
+
+ cec->dev = mhdp->dev;
+ cec->iolock = &mhdp->iolock;
+ cec->regs_base = mhdp->regs_base;
+ cec->regs_sec = mhdp->regs_sec;
+ cec->bus_type = mhdp->bus_type;
+}
+#endif
+
static int __cdns_hdmi_probe(struct platform_device *pdev,
struct cdns_mhdp_device *mhdp)
{
@@ -669,7 +682,8 @@ static int __cdns_hdmi_probe(struct platform_device *pdev,
/* register cec driver */
#ifdef CONFIG_DRM_CDNS_HDMI_CEC
- cdns_mhdp_register_cec_driver(dev);
+ cdns_mhdp_cec_init(mhdp);
+ cdns_mhdp_register_cec_driver(&mhdp->hdmi.cec);
#endif
return 0;
@@ -679,7 +693,7 @@ static void __cdns_hdmi_remove(struct cdns_mhdp_device *mhdp)
{
/* unregister cec driver */
#ifdef CONFIG_DRM_CDNS_HDMI_CEC
- cdns_mhdp_unregister_cec_driver(mhdp->dev);
+ cdns_mhdp_unregister_cec_driver(&mhdp->hdmi.cec);
#endif
cdns_mhdp_unregister_audio_driver(mhdp->dev);
}
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c
index 029ad761606a..25cf9e91e64f 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -74,16 +74,49 @@ enum {
static u32 mhdp_cec_read(struct cdns_mhdp_cec *cec, u32 offset)
{
- struct cdns_mhdp_device *mhdp =
- container_of(cec, struct cdns_mhdp_device, hdmi.cec);
- return cdns_mhdp_bus_read(mhdp, offset);
+ u32 val;
+
+ mutex_lock(cec->iolock);
+
+ if (cec->bus_type == BUS_TYPE_LOW4K_HDMI_RX) {
+ /* Remap address to low 4K HDMI RX */
+ writel(offset >> 12, cec->regs_sec + 4);
+ val = readl((offset & 0xfff) + cec->regs_base);
+ } else if (cec->bus_type == BUS_TYPE_LOW4K_APB) {
+ /* Remap address to low 4K memory */
+ writel(offset >> 12, cec->regs_sec + 8);
+ val = readl((offset & 0xfff) + cec->regs_base);
+ } else
+ val = readl(cec->regs_base + offset);
+
+ mutex_unlock(cec->iolock);
+
+ return val;
}
static void mhdp_cec_write(struct cdns_mhdp_cec *cec, u32 offset, u32 val)
{
- struct cdns_mhdp_device *mhdp =
- container_of(cec, struct cdns_mhdp_device, hdmi.cec);
- cdns_mhdp_bus_write(val, mhdp, offset);
+ mutex_lock(cec->iolock);
+
+ if (cec->bus_type == BUS_TYPE_LOW4K_HDMI_RX) {
+ /* Remap address to low 4K SAPB bus */
+ writel(offset >> 12, cec->regs_sec + 4);
+ writel(val, (offset & 0xfff) + cec->regs_base);
+ } else if (cec->bus_type == BUS_TYPE_LOW4K_APB) {
+ /* Remap address to low 4K memory */
+ writel(offset >> 12, cec->regs_sec + 8);
+ writel(val, (offset & 0xfff) + cec->regs_base);
+ } else if (cec->bus_type == BUS_TYPE_NORMAL_SAPB)
+ writel(val, cec->regs_sec + offset);
+ else
+ writel(val, cec->regs_base + offset);
+
+ mutex_unlock(cec->iolock);
+}
+
+static u32 mhdp_get_fw_clk(struct cdns_mhdp_cec *cec)
+{
+ return mhdp_cec_read(cec, SW_CLK_H);
}
static void mhdp_cec_clear_rx_buffer(struct cdns_mhdp_cec *cec)
@@ -94,12 +127,10 @@ static void mhdp_cec_clear_rx_buffer(struct cdns_mhdp_cec *cec)
static void mhdp_cec_set_divider(struct cdns_mhdp_cec *cec)
{
- struct cdns_mhdp_device *mhdp =
- container_of(cec, struct cdns_mhdp_device, hdmi.cec);
u32 clk_div;
/* Set clock divider */
- clk_div = cdns_mhdp_get_fw_clk(mhdp) * 10;
+ clk_div = mhdp_get_fw_clk(cec) * 10;
mhdp_cec_write(cec, CLK_DIV_MSB,
(clk_div >> 8) & 0xFF);
@@ -291,10 +322,8 @@ static const struct cec_adap_ops cdns_mhdp_cec_adap_ops = {
.adap_transmit = mhdp_cec_adap_transmit,
};
-int cdns_mhdp_register_cec_driver(struct device *dev)
+int cdns_mhdp_register_cec_driver(struct cdns_mhdp_cec *cec)
{
- struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev);
- struct cdns_mhdp_cec *cec = &mhdp->hdmi.cec;
int ret;
cec->adap = cec_allocate_adapter(&cdns_mhdp_cec_adap_ops, cec,
@@ -305,29 +334,24 @@ int cdns_mhdp_register_cec_driver(struct device *dev)
ret = PTR_ERR_OR_ZERO(cec->adap);
if (ret)
return ret;
- ret = cec_register_adapter(cec->adap, dev);
+ ret = cec_register_adapter(cec->adap, cec->dev);
if (ret) {
cec_delete_adapter(cec->adap);
return ret;
}
- cec->dev = dev;
-
cec->cec_worker = kthread_create(mhdp_cec_poll_worker, cec, "cdns-mhdp-cec");
if (IS_ERR(cec->cec_worker))
dev_err(cec->dev, "failed create hdp cec thread\n");
wake_up_process(cec->cec_worker);
- dev_dbg(dev, "CEC successfuly probed\n");
+ dev_dbg(cec->dev, "CEC successfuly probed\n");
return 0;
}
-int cdns_mhdp_unregister_cec_driver(struct device *dev)
+int cdns_mhdp_unregister_cec_driver(struct cdns_mhdp_cec *cec)
{
- struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev);
- struct cdns_mhdp_cec *cec = &mhdp->hdmi.cec;
-
if (cec->cec_worker) {
kthread_stop(cec->cec_worker);
cec->cec_worker = NULL;
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
index 2043016f176b..ff37cc4e57e6 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
@@ -99,12 +99,6 @@ void cdns_mhdp_bus_write(u32 val, struct cdns_mhdp_device *mhdp, u32 offset)
}
EXPORT_SYMBOL(cdns_mhdp_bus_write);
-u32 cdns_mhdp_get_fw_clk(struct cdns_mhdp_device *mhdp)
-{
- return cdns_mhdp_bus_read(mhdp, SW_CLK_H);
-}
-EXPORT_SYMBOL(cdns_mhdp_get_fw_clk);
-
void cdns_mhdp_set_fw_clk(struct cdns_mhdp_device *mhdp, unsigned long clk)
{
cdns_mhdp_bus_write(clk / 1000000, mhdp, SW_CLK_H);
diff --git a/include/drm/bridge/cdns-mhdp.h b/include/drm/bridge/cdns-mhdp.h
index 6bfd82a3d9a2..338fa55b8bdf 100644
--- a/include/drm/bridge/cdns-mhdp.h
+++ b/include/drm/bridge/cdns-mhdp.h
@@ -509,6 +509,7 @@ enum {
BUS_TYPE_NORMAL_SAPB = 1,
BUS_TYPE_LOW4K_APB = 2,
BUS_TYPE_LOW4K_SAPB = 3,
+ BUS_TYPE_LOW4K_HDMI_RX = 4,
};
enum voltage_swing_level {
@@ -623,12 +624,15 @@ struct cdns_mhdp_connector {
};
struct cdns_mhdp_cec {
- struct cec_adapter *adap;
- struct device *dev;
- struct mutex lock;
+ struct cec_adapter *adap;
+ struct device *dev;
+ struct mutex *iolock;
+ void __iomem *regs_base;
+ void __iomem *regs_sec;
+ int bus_type;
- struct cec_msg msg;
- struct task_struct *cec_worker;
+ struct cec_msg msg;
+ struct task_struct *cec_worker;
};
struct cdns_plat_data {
@@ -724,7 +728,6 @@ u32 cdns_mhdp_bus_read(struct cdns_mhdp_device *mhdp, u32 offset);
void cdns_mhdp_bus_write(u32 val, struct cdns_mhdp_device *mhdp, u32 offset);
void cdns_mhdp_clock_reset(struct cdns_mhdp_device *mhdp);
void cdns_mhdp_set_fw_clk(struct cdns_mhdp_device *mhdp, unsigned long clk);
-u32 cdns_mhdp_get_fw_clk(struct cdns_mhdp_device *mhdp);
int cdns_mhdp_load_firmware(struct cdns_mhdp_device *mhdp, const u32 *i_mem,
u32 i_size, const u32 *d_mem, u32 d_size);
int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool enable);
@@ -805,8 +808,8 @@ int cdns_hdmi_set_plugged_cb(struct cdns_mhdp_device *mhdp, hdmi_codec_plugged_c
/* CEC */
#ifdef CONFIG_DRM_CDNS_HDMI_CEC
-int cdns_mhdp_register_cec_driver(struct device *dev);
-int cdns_mhdp_unregister_cec_driver(struct device *dev);
+int cdns_mhdp_register_cec_driver(struct cdns_mhdp_cec *cec);
+int cdns_mhdp_unregister_cec_driver(struct cdns_mhdp_cec *cec);
#endif
#endif /* CDNS_MHDP_H_ */
--
2.29.2

143
projects/NXP/devices/iMX8/patches/linux/0018-MLK-25199-3-drm-bridge-mhdp_common-add-apb-config-fu.patch
View File

@ -1,143 +0,0 @@
From 0021b4b1afc0d88c013e2484009004b19bc2ece4 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Wed, 30 Dec 2020 16:04:20 +0800
Subject: [PATCH 18/49] MLK-25199-3: drm: bridge: mhdp_common: add apb config
function
Add apb config function, move mhdp poll function
to mhdp head file, they will be used by hdcp driver.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
---
.../gpu/drm/bridge/cadence/cdns-mhdp-common.c | 54 ++++++++++---------
drivers/gpu/drm/bridge/cadence/cdns-mhdp.h | 25 ++++++++-
2 files changed, 54 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
index ff37cc4e57e6..2a8ab0872f25 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
@@ -27,31 +27,10 @@
#include <drm/drm_print.h>
#include <linux/regmap.h>
+#include "cdns-mhdp.h"
+
#define CDNS_DP_SPDIF_CLK 200000000
#define FW_ALIVE_TIMEOUT_US 1000000
-#define MAILBOX_RETRY_US 1000
-#define MAILBOX_TIMEOUT_US 5000000
-
-#define mhdp_readx_poll_timeout(op, addr, offset, val, cond, sleep_us, timeout_us) \
-({ \
- u64 __timeout_us = (timeout_us); \
- unsigned long __sleep_us = (sleep_us); \
- ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \
- might_sleep_if((__sleep_us) != 0); \
- for (;;) { \
- (val) = op(addr, offset); \
- if (cond) \
- break; \
- if (__timeout_us && \
- ktime_compare(ktime_get(), __timeout) > 0) { \
- (val) = op(addr, offset); \
- break; \
- } \
- if (__sleep_us) \
- usleep_range((__sleep_us >> 2) + 1, __sleep_us); \
- } \
- (cond) ? 0 : -ETIMEDOUT; \
-})
u32 cdns_mhdp_bus_read(struct cdns_mhdp_device *mhdp, u32 offset)
{
@@ -174,7 +153,7 @@ bool cdns_mhdp_check_alive(struct cdns_mhdp_device *mhdp)
}
EXPORT_SYMBOL(cdns_mhdp_check_alive);
-static int mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
+int mhdp_mailbox_read(struct cdns_mhdp_device *mhdp)
{
int val, ret;
@@ -432,6 +411,33 @@ int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp, bool enable)
}
EXPORT_SYMBOL(cdns_mhdp_set_firmware_active);
+int cdns_mhdp_apb_conf(struct cdns_mhdp_device *mhdp, u8 sel)
+{
+ u8 status;
+ int ret;
+
+ ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL, GENERAL_BUS_SETTINGS,
+ sizeof(sel), &sel);
+ if (ret)
+ goto err_apb_conf;
+
+ ret = cdns_mhdp_mailbox_validate_receive(mhdp, MB_MODULE_ID_GENERAL,
+ GENERAL_BUS_SETTINGS, sizeof(status));
+ if (ret)
+ goto err_apb_conf;
+
+ ret = cdns_mhdp_mailbox_read_receive(mhdp, &status, sizeof(status));
+ if (ret)
+ goto err_apb_conf;
+
+ return status;
+
+err_apb_conf:
+ DRM_ERROR("apb conf failed: %d\n", ret);
+ return ret;
+}
+EXPORT_SYMBOL(cdns_mhdp_apb_conf);
+
int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp)
{
u8 msg[8];
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h b/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h
index 399c3f6f86ad..8ad99eb8f86e 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp.h
@@ -174,7 +174,6 @@
#define CDNS_DP_MTPH_STATUS 0x226C
#define CDNS_DP_MTPH_ACT_STATUS BIT(0)
-
#define CDNS_DPTX_GLOBAL 0x02300
#define CDNS_DP_LANE_EN (CDNS_DPTX_GLOBAL + 0x00)
#define CDNS_DP_LANE_EN_LANES(x) GENMASK(x - 1, 0)
@@ -187,6 +186,30 @@
#define CDNS_MHDP_MAX_STREAMS 4
+#define MAILBOX_RETRY_US 1000
+#define MAILBOX_TIMEOUT_US 5000000
+
+#define mhdp_readx_poll_timeout(op, addr, offset, val, cond, sleep_us, timeout_us) \
+({ \
+ u64 __timeout_us = (timeout_us); \
+ unsigned long __sleep_us = (sleep_us); \
+ ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \
+ might_sleep_if((__sleep_us) != 0); \
+ for (;;) { \
+ (val) = op(addr, offset); \
+ if (cond) \
+ break; \
+ if (__timeout_us && \
+ ktime_compare(ktime_get(), __timeout) > 0) { \
+ (val) = op(addr, offset); \
+ break; \
+ } \
+ if (__sleep_us) \
+ usleep_range((__sleep_us >> 2) + 1, __sleep_us); \
+ } \
+ (cond) ? 0 : -ETIMEDOUT; \
+})
+
enum pixel_format {
PIXEL_FORMAT_RGB = 1,
PIXEL_FORMAT_YCBCR_444 = 2,
--
2.29.2

38
projects/NXP/devices/iMX8/patches/linux/0019-MLK-25199-4-drm-bridge-mhdp_hdmi-set-clear-avmute-bi.patch
View File

@ -1,38 +0,0 @@
From 1793e95601a15f93e5d9e2846281f86eb19e8fe4 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Wed, 30 Dec 2020 16:05:29 +0800
Subject: [PATCH 19/49] MLK-25199-4: drm: bridge: mhdp_hdmi: set clear avmute
bit
Sync HDMI TX configuation with 4.14 hdmi driver.
Clear avmute bit must be set otherwise imx8qm hdcp not work.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c
index c37a7ac6af9b..3ff43f7fb0a6 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdmi.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2019 NXP Semiconductor, Inc.
+ * Copyright (C) 2019-2021 NXP Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -205,7 +205,7 @@ int cdns_hdmi_ctrl_init(struct cdns_mhdp_device *mhdp,
/* set hdmi mode and preemble mode data enable */
val = F_HDMI_MODE(protocol) | F_HDMI2_PREAMBLE_EN(1) | F_DATA_EN(1) |
- F_HDMI2_CTRL_IL_MODE(1) | F_BCH_EN(1) | F_PIC_3D(0XF);
+ F_HDMI2_CTRL_IL_MODE(1) | F_BCH_EN(1) | F_PIC_3D(0XF) | F_CLEAR_AVMUTE(1);
ret = cdns_mhdp_reg_write(mhdp, HDTX_CONTROLLER, val);
return ret;
--
2.29.2

2007
projects/NXP/devices/iMX8/patches/linux/0020-MLK-25199-5-drm-bridge-mhdp_hdcp-add-HDMI-TX-HDCP-dr.patch
View File

File diff suppressed because it is too large Load Diff

30
projects/NXP/devices/iMX8/patches/linux/0021-LF-3272-drm-cdns_mhdp-fix-Coverity-Issue-11566406.patch
View File

@ -1,30 +0,0 @@
From 2a093769a29f03103195b34c269411ee21b646e2 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Wed, 20 Jan 2021 10:37:09 +0800
Subject: [PATCH 21/49] LF-3272: drm: cdns_mhdp: fix Coverity Issue: 11566406
Add default access hdcp bus to fix
Coverity Issue: 11566406 Uninitialized scalar variable.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdcp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdcp.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdcp.c
index 587c5f953489..b3c931382013 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdcp.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-hdcp.c
@@ -27,6 +27,8 @@ static u32 mhdp_hdcp_bus_read(struct cdns_mhdp_device *mhdp, u32 offset)
val = readl((offset & 0xfff) + mhdp->regs_base);
} else if (mhdp->bus_type == BUS_TYPE_NORMAL_APB)
val = readl(mhdp->regs_sec + offset);
+ else
+ val = readl(mhdp->regs_base + offset);
mutex_unlock(&mhdp->iolock);
--
2.29.2

28
projects/NXP/devices/iMX8/patches/linux/0022-LF-3271-drm-cdns-hdmi-fix-Coverity-Issue-11566407.patch
View File

@ -1,28 +0,0 @@
From 85ad1a878118a8dbaf9da5f85a2e088880d5ea01 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Wed, 20 Jan 2021 10:44:17 +0800
Subject: [PATCH 22/49] LF-3271: drm: cdns-hdmi: fix Coverity Issue: 11566407
Delete dead code to fix Coverity Issue: 11566407.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
index dc393f6b75e7..a89c8cba4788 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
@@ -150,7 +150,6 @@ ssize_t HDCPTX_Status_store(struct device *dev,
else
dev_err(dev, "%s &hdp->state invalid\n", __func__);
return -1;
- return count;
}
static void hdmi_sink_config(struct cdns_mhdp_device *mhdp)
--
2.29.2

40
projects/NXP/devices/iMX8/patches/linux/0023-LF-3270-drm-cdns-hdmi-fix-coverity-Issue-11566405.patch
View File

@ -1,40 +0,0 @@
From ddfa5aeb97c12fb7a67e6507ef2ae051658f112b Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Wed, 20 Jan 2021 10:49:13 +0800
Subject: [PATCH 23/49] LF-3270: drm: cdns-hdmi: fix coverity Issue: 11566405
Delete unused code to fix coverity Issue: 11566405.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
index a89c8cba4788..2300c3d8a91d 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
@@ -37,17 +37,15 @@ static struct device_attribute HDCPTX_do_reauth = __ATTR_WO(HDCPTX_do_reauth);
static ssize_t HDCPTX_do_reauth_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
- int value, ret;
+ int ret;
struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev);
ret = cdns_mhdp_hdcp_tx_reauth(mhdp, 1);
-
- sscanf(buf, "%d", &value);
-
if (ret < 0) {
dev_err(dev, "%s cdns_mhdp_hdcp_tx_reauth failed\n", __func__);
return -1;
}
+
return count;
}
--
2.29.2

35
projects/NXP/devices/iMX8/patches/linux/0024-LF-3269-drm-cdns-hdmi-fix-coverity-Issue-11566404.patch
View File

@ -1,35 +0,0 @@
From 2812d071eb348d903620f7ebadaf848024b3c672 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Wed, 20 Jan 2021 11:04:41 +0800
Subject: [PATCH 24/49] LF-3269: drm: cdns-hdmi: fix coverity Issue: 11566404
Check return value to fix coverity Issue: 11566404.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
index 2300c3d8a91d..df8ac87b3a54 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
@@ -59,9 +59,12 @@ static ssize_t HDCPTX_Version_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev);
- int value;
+ int value, ret;
+
+ ret = sscanf(buf, "%d", &value);
+ if (ret != 1)
+ return -EINVAL;
- sscanf(buf, "%d", &value);
if (value == 2)
mhdp->hdcp.config = 2;
else if (value == 1)
--
2.29.2

36
projects/NXP/devices/iMX8/patches/linux/0025-LF-3268-drm-cdns-hdmi-fix-Coverity-Issue-11566403.patch
View File

@ -1,36 +0,0 @@
From cd49375db5c05acb824fa18ae9d19290073cda08 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Wed, 20 Jan 2021 11:07:32 +0800
Subject: [PATCH 25/49] LF-3268: drm: cdns-hdmi: fix Coverity Issue: 11566403
Check return value to fix Coverity Issue: 11566403.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
index df8ac87b3a54..28193178140f 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
@@ -119,10 +119,13 @@ ssize_t HDCPTX_Status_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct cdns_mhdp_device *mhdp = dev_get_drvdata(dev);
- int value;
+ int value, ret;
if (count == 2) {
- sscanf(buf, "%d", &value);
+ ret = sscanf(buf, "%d", &value);
+ if (ret != 1)
+ return -EINVAL;
+
if ((value >= HDCP_STATE_NO_AKSV) && (value <= HDCP_STATE_AUTH_FAILED)) {
mhdp->hdcp.state = value;
return count;
--
2.29.2

45
projects/NXP/devices/iMX8/patches/linux/0026-LF-3367-1-drm-cdns_hdmi-HDCP_STATE_DISABLING-may-mis.patch
View File

@ -1,45 +0,0 @@
From 54a5d4d3ba2de923fa4a4e5ef5e90151fb7f2fd8 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Thu, 18 Feb 2021 16:25:52 +0800
Subject: [PATCH 26/49] LF-3367-1: drm: cdns_hdmi: HDCP_STATE_DISABLING may
missed by check link
Polling thread check_work is designed to handle all hdcp state change.
In HDCP disable function, check_work thread will be stopped after
hdcp.state is set to HDCP_STATE_DISABLING. check_work thread may miss
the state change, call check link function make sure HDCP_STATE_DISABLING
state is properly handled.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-hdmi-hdcp.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-hdcp.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-hdcp.c
index e2a3bc7fb42b..9119f2063098 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-hdcp.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-hdcp.c
@@ -988,6 +988,8 @@ int cdns_hdmi_hdcp_disable(struct cdns_mhdp_device *mhdp)
{
int ret = 0;
+ cancel_delayed_work_sync(&mhdp->hdcp.check_work);
+
mutex_lock(&mhdp->hdcp.mutex);
if (mhdp->hdcp.value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
@@ -998,7 +1000,8 @@ int cdns_hdmi_hdcp_disable(struct cdns_mhdp_device *mhdp)
mutex_unlock(&mhdp->hdcp.mutex);
- cancel_delayed_work_sync(&mhdp->hdcp.check_work);
+ /* Make sure HDCP_STATE_DISABLING state is handled */
+ hdmi_hdcp_check_link(mhdp);
return ret;
}
--
2.29.2

31
projects/NXP/devices/iMX8/patches/linux/0027-LF-3367-2-drm-mhdp-more-time-for-FW-alive-check.patch
View File

@ -1,31 +0,0 @@
From 42394af5975326eb20901d65eac47963847006e2 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Fri, 19 Feb 2021 16:41:31 +0800
Subject: [PATCH 27/49] LF-3367-2: drm: mhdp: more time for FW alive check
FW alive check function may return false in hdcp enable/disable stress test.
Add more time for FW alive check, make sure get correct state.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
index 2a8ab0872f25..3487a2fa335c 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
@@ -142,7 +142,7 @@ bool cdns_mhdp_check_alive(struct cdns_mhdp_device *mhdp)
alive = cdns_mhdp_bus_read(mhdp, KEEP_ALIVE);
while (retries_left--) {
- udelay(2);
+ msleep(1);
newalive = cdns_mhdp_bus_read(mhdp, KEEP_ALIVE);
if (alive == newalive)
--
2.29.2

62
projects/NXP/devices/iMX8/patches/linux/0028-LF-3367-3-drm-mhdp-hdcp-adjust-state-handle-priority.patch
View File

@ -1,62 +0,0 @@
From 60f6b8c90766663303f6005468502798eb2b0f44 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Fri, 19 Feb 2021 17:53:54 +0800
Subject: [PATCH 28/49] LF-3367-3: drm: mhdp-hdcp: adjust state handle priority
Handle HDCP_STATE_INACTIVE and HDCP_STATE_DISABLING state priority
to avoid unnecessary HPD state check, drm has check it when hdcp
enable/disable.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
---
.../gpu/drm/bridge/cadence/cdns-hdmi-hdcp.c | 24 ++++++++++---------
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-hdcp.c b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-hdcp.c
index 9119f2063098..5dfbd7943306 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-hdcp.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-hdcp.c
@@ -1048,6 +1048,15 @@ static int hdmi_hdcp_check_link(struct cdns_mhdp_device *mhdp)
mhdp->hdcp.reauth_in_progress = 0;
mutex_lock(&mhdp->lock);
+ if (mhdp->hdcp.state == HDCP_STATE_INACTIVE)
+ goto out;
+
+ if (mhdp->hdcp.state == HDCP_STATE_DISABLING) {
+ _hdmi_hdcp_disable(mhdp);
+ mhdp->hdcp.state = HDCP_STATE_INACTIVE;
+ goto out;
+ }
+
if ((mhdp->hdcp.state == HDCP_STATE_AUTHENTICATED) ||
(mhdp->hdcp.state == HDCP_STATE_AUTHENTICATING) ||
(mhdp->hdcp.state == HDCP_STATE_REAUTHENTICATING) ||
@@ -1056,18 +1065,11 @@ static int hdmi_hdcp_check_link(struct cdns_mhdp_device *mhdp)
/* In active states, check the HPD signal. Because of the IRQ
* debounce delay, the state might not reflect the disconnection.
* The FW could already have detected the HDP down and reported error */
- hpd_sts = cdns_mhdp_read_hpd(mhdp);
- if (1 != hpd_sts)
+ hpd_sts = cdns_mhdp_read_hpd(mhdp);
+ if (1 != hpd_sts) {
mhdp->hdcp.state = HDCP_STATE_DISABLING;
- }
-
- if (mhdp->hdcp.state == HDCP_STATE_INACTIVE)
- goto out;
-
- if (mhdp->hdcp.state == HDCP_STATE_DISABLING) {
- _hdmi_hdcp_disable(mhdp);
- mhdp->hdcp.state = HDCP_STATE_INACTIVE;
- goto out;
+ goto out;
+ }
}
/* TODO items:
--
2.29.2

42
projects/NXP/devices/iMX8/patches/linux/0029-clk-imx8mq-add-27MHz-PHY-ref-clock.patch
View File

@ -1,42 +0,0 @@
From afbe8e0ae318f407d64bbc48b784d93c782b6564 Mon Sep 17 00:00:00 2001
From: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Date: Thu, 5 Sep 2019 13:07:22 +0300
Subject: [PATCH 29/49] clk: imx8mq: add 27MHz PHY ref clock
This clock is a high precision clock on imx8mq-evk board that will be used by
HDMI phy.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
---
drivers/clk/imx/clk-imx8mq.c | 3 ++-
include/dt-bindings/clock/imx8mq-clock.h | 4 +++-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 06292d4a98ff..6bd2fe0ae71d 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -304,6 +304,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
hws[IMX8MQ_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2");
hws[IMX8MQ_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3");
hws[IMX8MQ_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4");
+ hws[IMX8MQ_CLK_PHY_27MHZ] = imx_get_clk_hw_by_name(np, "hdmi_phy_27m");
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop");
base = of_iomap(np, 0);
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
index 9b8045d75b8b..2a81f96b7c74 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -431,6 +431,7 @@
#define IMX8MQ_CLK_MON_SEL 301
#define IMX8MQ_CLK_MON_CLK2_OUT 302
+#define IMX8MQ_CLK_PHY_27MHZ 303
-#define IMX8MQ_CLK_END 303
+#define IMX8MQ_CLK_END 304
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
--
2.29.2

2656
projects/NXP/devices/iMX8/patches/linux/0030-drm-imx-Add-mhdp-dp-hdmi-driver-for-imx8x-platform.patch
View File

File diff suppressed because it is too large Load Diff

43
projects/NXP/devices/iMX8/patches/linux/0031-LF-1514-drm-cdns-mhdp-check-link-rate-index.patch
View File

@ -1,43 +0,0 @@
From 8aa7d7baa5eb142261ddafc91b0ba884aa670421 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Fri, 19 Jun 2020 16:17:55 +0800
Subject: [PATCH 31/49] LF-1514: drm: cdns-mhdp: check link rate index
Check link rate index to advoid negative array index read.
report by Coverity ID:6652950 6652949.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
---
drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c
index a6d03c94d196..5c75e7d40cc0 100644
--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c
+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c
@@ -198,6 +198,10 @@ static void dp_phy_pma_cmn_pll0_24mhz(struct cdns_mhdp_device *mhdp)
/* DP PHY PLL 24MHz configuration */
index = link_rate_index(link_rate);
+ if (index < 0) {
+ dev_err(mhdp->dev, "wrong link rate index\n");
+ return;
+ }
for (i = 0; i < ARRAY_SIZE(phy_pll_24m_cfg); i++)
cdns_phy_reg_write(mhdp, phy_pll_24m_cfg[i].addr, phy_pll_24m_cfg[i].val[index]);
@@ -320,6 +324,10 @@ static void dp_phy_pma_cmn_pll0_27mhz(struct cdns_mhdp_device *mhdp)
/* DP PHY PLL 27MHz configuration */
index = link_rate_index(link_rate);
+ if (index < 0) {
+ dev_err(mhdp->dev, "wrong link rate index\n");
+ return;
+ }
for (i = 0; i < ARRAY_SIZE(phy_pll_27m_cfg); i++)
cdns_phy_reg_write(mhdp, phy_pll_27m_cfg[i].addr, phy_pll_27m_cfg[i].val[index]);
--
2.29.2

31
projects/NXP/devices/iMX8/patches/linux/0032-LF-1516-drm-cdns-mhdp-fix-error-check-variable-name-.patch
View File

@ -1,31 +0,0 @@
From b2ea44969c5e51a5809622384728859d7f3a2b8a Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Fri, 19 Jun 2020 16:25:51 +0800
Subject: [PATCH 32/49] LF-1516: drm: cdns-mhdp: fix error check variable name
for clk_pxl_link
fix error check variable name for clk_pxl_link.
Report by Coverity ID:6652947
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
---
drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c
index a3ba3da4b05d..2ee4e8748b77 100644
--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c
+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c
@@ -167,7 +167,7 @@ int imx8qm_clocks_init(struct imx_mhdp_device *imx_mhdp)
}
clks->clk_pxl_link = devm_clk_get(dev, "clk_pxl_link");
- if (IS_ERR(clks->clk_pxl_mux)) {
+ if (IS_ERR(clks->clk_pxl_link)) {
dev_warn(dev, "failed to get pxl link clk\n");
return PTR_ERR(clks->clk_pxl_link);
}
--
2.29.2

58
projects/NXP/devices/iMX8/patches/linux/0033-MLK-24601-drm-imx-mhdp-DP-PHY-support-1-2-lanes-mode.patch
View File

@ -1,58 +0,0 @@
From c789945d09e4c77eb30af1a8db1425cefab52080 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Fri, 28 Aug 2020 10:09:12 +0800
Subject: [PATCH 33/49] MLK-24601: drm: imx: mhdp: DP PHY support 1/2 lanes
mode
All four lanes should be configurated for 1/2/4 lanes modes in driver.
The DP FW will power down unused PHY lanes after negotiation.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
---
drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c
index 5c75e7d40cc0..3d17840b0941 100644
--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c
+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c
@@ -137,7 +137,7 @@ static void dp_aux_cfg(struct cdns_mhdp_device *mhdp)
static void dp_phy_pma_cmn_cfg_24mhz(struct cdns_mhdp_device *mhdp)
{
int k;
- u32 num_lanes = mhdp->dp.num_lanes;
+ u32 num_lanes = 4;
u16 val;
val = cdns_phy_reg_read(mhdp, PHY_PMA_CMN_CTRL1);
@@ -157,7 +157,7 @@ static void dp_phy_pma_cmn_cfg_24mhz(struct cdns_mhdp_device *mhdp)
/* Valid for 24 MHz only */
static void dp_phy_pma_cmn_pll0_24mhz(struct cdns_mhdp_device *mhdp)
{
- u32 num_lanes = mhdp->dp.num_lanes;
+ u32 num_lanes = 4;
u32 link_rate = mhdp->dp.rate;
u16 val;
int index, i, k;
@@ -228,7 +228,7 @@ static void dp_phy_pma_cmn_pll0_24mhz(struct cdns_mhdp_device *mhdp)
/* PMA common configuration for 27MHz */
static void dp_phy_pma_cmn_cfg_27mhz(struct cdns_mhdp_device *mhdp)
{
- u32 num_lanes = mhdp->dp.num_lanes;
+ u32 num_lanes = 4;
u16 val;
int k;
@@ -279,7 +279,7 @@ static void dp_phy_pma_cmn_cfg_27mhz(struct cdns_mhdp_device *mhdp)
static void dp_phy_pma_cmn_pll0_27mhz(struct cdns_mhdp_device *mhdp)
{
- u32 num_lanes = mhdp->dp.num_lanes;
+ u32 num_lanes = 4;
u32 link_rate = mhdp->dp.rate;
u16 val;
int index, i, k;
--
2.29.2

30
projects/NXP/devices/iMX8/patches/linux/0034-MLK-24519-2-gpu-imx-Increase-maximum-single-pipe-wid.patch
View File

@ -1,30 +0,0 @@
From 7772a57acd0e05353caead7eb7d064e36bcb92e6 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Sun, 20 Sep 2020 19:32:28 +0800
Subject: [PATCH 34/49] MLK-24519-2 gpu: imx: Increase maximum single pipe
width to 2560
This patch increase the DPU single pipe maximum from 1920 to 2560 for HDMI/DP.
Signed-off-by: Oliver F. Brown <oliver.brown@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
---
drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c
index 2ee4e8748b77..cda4d245bab8 100644
--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c
+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c
@@ -22,7 +22,7 @@
#define PLL_800MHZ (800000000)
#define HDP_DUAL_MODE_MIN_PCLK_RATE 300000 /* KHz */
-#define HDP_SINGLE_MODE_MAX_WIDTH 1920
+#define HDP_SINGLE_MODE_MAX_WIDTH 2560
#define CSR_PIXEL_LINK_MUX_CTL 0x00
#define CSR_PIXEL_LINK_MUX_VCP_OFFSET 5
--
2.29.2

39
projects/NXP/devices/iMX8/patches/linux/0035-MLK-24072-drm-imx8-correct-mhdp-files-copyright.patch
View File

@ -1,39 +0,0 @@
From 60077991d60b1ba96e52d5a6568ae65ae7143ee2 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Wed, 20 May 2020 10:56:53 +0800
Subject: [PATCH 35/49] MLK-24072: drm: imx8: correct mhdp files copyright
Correct mhdp files copyright.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
---
drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c | 2 +-
drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c
index cda4d245bab8..38f9defa42f8 100644
--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c
+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c
@@ -1,5 +1,5 @@
/*
- * copyright (c) 2019 nxp semiconductor, inc.
+ * Copyright (c) 2019 NXP semiconductor, inc.
*
* this program is free software; you can redistribute it and/or modify
* it under the terms of the gnu general public license version 2 as
diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c
index 3acbdf575ee2..cc429fe48abd 100644
--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c
+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c
@@ -1,5 +1,5 @@
/*
- * copyright (c) 2019 nxp semiconductor, inc.
+ * Copyright (c) 2019 NXP semiconductor, inc.
*
* this program is free software; you can redistribute it and/or modify
* it under the terms of the gnu general public license version 2 as
--
2.29.2

42
projects/NXP/devices/iMX8/patches/linux/0036-LF-2744-drm-cdns-reset-force_mode_set-flag-in-atomic.patch
View File

@ -1,42 +0,0 @@
From 93502b984119af556f8a204bf80a62bc1c21fbfd Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Tue, 17 Nov 2020 15:47:36 +0800
Subject: [PATCH 36/49] LF-2744: drm: cdns: reset force_mode_set flag in
atomic_check
Reset force_mode_set flag in atomic_check function
to avoid set mode_changed flag multi times when cable plugin.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
---
drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c
index cc429fe48abd..9fa0df74ad7c 100644
--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c
+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 NXP semiconductor, inc.
+ * Copyright (c) 2019-2020 NXP semiconductor, inc.
*
* this program is free software; you can redistribute it and/or modify
* it under the terms of the gnu general public license version 2 as
@@ -44,8 +44,11 @@ static int cdns_mhdp_imx_encoder_atomic_check(struct drm_encoder *encoder,
if (mhdp->plat_data->video_format != 0)
imx_crtc_state->bus_format = mhdp->plat_data->video_format;
- if (mhdp->force_mode_set)
+ if (mhdp->force_mode_set) {
crtc_state->mode_changed = true;
+ /* reset force mode set flag */
+ mhdp->force_mode_set = false;
+ }
return 0;
}
--
2.29.2

161
projects/NXP/devices/iMX8/patches/linux/0037-MLK-25199-1-drm-mhdp-Add-hdmi-phy-reset-poweroff-fun.patch
View File

@ -1,161 +0,0 @@
From 38f1f4ecd038628f4ce7a47114455123e5db3367 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Wed, 30 Dec 2020 16:02:52 +0800
Subject: [PATCH 37/49] MLK-25199-1: drm: mhdp: Add hdmi phy reset/poweroff
function
Add hdmi phy reset and power off function.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
---
drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c | 28 ++++++++++++++++++-
drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx.h | 3 +-
drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c | 4 +--
drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c | 2 ++
drivers/gpu/drm/imx/mhdp/cdns-mhdp-phy.h | 3 +-
5 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c
index 120300e6a2df..212f3f4f1e26 100644
--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c
+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c
@@ -1,7 +1,7 @@
/*
* Cadence High-Definition Multimedia Interface (HDMI) driver
*
- * Copyright (C) 2019 NXP Semiconductor, Inc.
+ * Copyright (C) 2019-2021 NXP Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -21,6 +21,7 @@
#include <drm/bridge/cdns-mhdp.h>
#include "cdns-mhdp-phy.h"
+#include "cdns-mhdp-imx.h"
/* HDMI TX clock control settings */
struct hdmi_ctrl {
@@ -746,6 +747,7 @@ int cdns_hdmi_phy_set_imx8qm(struct cdns_mhdp_device *mhdp)
DRM_ERROR("NO HDMI FW running\n");
return -ENXIO;
}
+ imx8qm_phy_reset(0);
/* Configure PHY */
mhdp->hdmi.char_rate = hdmi_phy_cfg_ss28fdsoi(mhdp, mode);
@@ -753,6 +755,7 @@ int cdns_hdmi_phy_set_imx8qm(struct cdns_mhdp_device *mhdp)
DRM_ERROR("failed to set phy pclock\n");
return -EINVAL;
}
+ imx8qm_phy_reset(1);
ret = hdmi_phy_power_up(mhdp);
if (ret < 0)
@@ -762,3 +765,26 @@ int cdns_hdmi_phy_set_imx8qm(struct cdns_mhdp_device *mhdp)
return true;
}
+
+int cdns_hdmi_phy_shutdown(struct cdns_mhdp_device *mhdp)
+{
+ int timeout;
+ u32 reg_val;
+
+ reg_val = cdns_phy_reg_read(mhdp, PHY_HDP_MODE_CTRL);
+ reg_val &= 0xfff0;
+ /* PHY_DP_MODE_CTL set to A3 power state*/
+ cdns_phy_reg_write(mhdp, PHY_HDP_MODE_CTRL, reg_val | 0x8);
+
+ /* PHY_DP_MODE_CTL */
+ timeout = 0;
+ do {
+ reg_val = cdns_phy_reg_read(mhdp, PHY_HDP_MODE_CTRL);
+ DRM_INFO("Reg val is 0x%04x\n", reg_val);
+ timeout++;
+ msleep(100);
+ } while (!(reg_val & (0x8 << 4)) && (timeout < 10)); /* Wait for A3 acknowledge */
+
+ DRM_INFO("hdmi phy shutdown complete\n");
+ return 0;
+}
diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx.h b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx.h
index fc3247dada2d..a12005ae4c53 100644
--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx.h
+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx.h
@@ -1,7 +1,7 @@
/*
* Cadence High-Definition Multimedia Interface (HDMI) driver
*
- * Copyright (C) 2019 NXP Semiconductor, Inc.
+ * Copyright (C) 2019-2021 NXP Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -72,4 +72,5 @@ int cdns_mhdp_suspend_imx8qm(struct cdns_mhdp_device *mhdp);
int cdns_mhdp_power_on_imx8qm(struct cdns_mhdp_device *mhdp);
int cdns_mhdp_power_on_ls1028a(struct cdns_mhdp_device *mhdp);
void cdns_mhdp_pclk_rate_ls1028a(struct cdns_mhdp_device *mhdp);
+void imx8qm_phy_reset(u8 reset);
#endif /* CDNS_MHDP_IMX_H_ */
diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c
index 38f9defa42f8..46c0500da4c3 100644
--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c
+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 NXP semiconductor, inc.
+ * Copyright (c) 2019-2021 NXP semiconductor, inc.
*
* this program is free software; you can redistribute it and/or modify
* it under the terms of the gnu general public license version 2 as
@@ -102,7 +102,7 @@ static void imx8qm_pixel_link_sync_disable(u32 dual_mode)
imx_sc_misc_set_control(handle, IMX_SC_R_DC_0, IMX_SC_C_SYNC_CTRL0, 0);
}
-static void imx8qm_phy_reset(u8 reset)
+void imx8qm_phy_reset(u8 reset)
{
struct imx_sc_ipc *handle;
diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c
index 9fa0df74ad7c..4c4ce9d3c847 100644
--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c
+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c
@@ -22,6 +22,7 @@ static void cdns_mhdp_imx_encoder_disable(struct drm_encoder *encoder)
struct drm_bridge *bridge = drm_bridge_chain_get_first_bridge(encoder);
struct cdns_mhdp_device *mhdp = bridge->driver_private;
+ cdns_hdmi_phy_shutdown(mhdp);
cdns_mhdp_plat_call(mhdp, plat_init);
}
@@ -184,6 +185,7 @@ static int cdns_mhdp_imx_bind(struct device *dev, struct device *master,
imx_mhdp->mhdp.plat_data = plat_data;
imx_mhdp->mhdp.dev = dev;
+ imx_mhdp->mhdp.drm_dev = drm;
imx_mhdp->mhdp.bus_type = plat_data->bus_type;
ret = plat_data->bind(pdev, encoder, &imx_mhdp->mhdp);
/*
diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-phy.h b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-phy.h
index 5682b9fbc90f..9035f1f71eee 100644
--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-phy.h
+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-phy.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2019 NXP Semiconductor, Inc.
+ * Copyright (C) 2019-2021 NXP Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -152,4 +152,5 @@ bool cdns_hdmi_phy_video_valid_imx8mq(struct cdns_mhdp_device *hdp);
bool cdns_hdmi_phy_video_valid_imx8qm(struct cdns_mhdp_device *hdp);
int cdns_hdmi_phy_set_imx8mq(struct cdns_mhdp_device *hdp);
int cdns_hdmi_phy_set_imx8qm(struct cdns_mhdp_device *hdp);
+int cdns_hdmi_phy_shutdown(struct cdns_mhdp_device *mhdp);
#endif /* _CDNS_MHDP_PHY_H */
--
2.29.2

38
projects/NXP/devices/iMX8/patches/linux/0038-MLK-25199-2-drm-mhdp-Fix-typo-for-hdmi-phy-configura.patch
View File

@ -1,38 +0,0 @@
From d77cbee9949eda85baba634bdf6c6c2afe0b64e4 Mon Sep 17 00:00:00 2001
From: Sandor Yu <Sandor.yu@nxp.com>
Date: Thu, 31 Dec 2020 10:13:55 +0800
Subject: [PATCH 38/49] MLK-25199-2: drm: mhdp: Fix typo for hdmi phy
configuration table
Fix typo for imx8qm hdmi phy configuration table.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
---
drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c
index 212f3f4f1e26..f96b200885df 100644
--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c
+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c
@@ -95,11 +95,11 @@ static const struct hdmi_ctrl imx8qm_ctrl_table[] = {
{ 85000, 170000, 1000, 850000, 1700000, 0x11, 0x00, 0x07, 340, 0x146, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 2, 0x01, 85000, 170000},
{170000, 340000, 1000, 1700000, 3400000, 0x22, 0x01, 0x07, 340, 0x146, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 1, 0x00, 170000, 340000},
{340000, 600000, 1000, 3400000, 6000000, 0x3C, 0x03, 0x06, 600, 0x24A, 0x00A, 0, 0, 0, 3400000, 6000000, 1, 1, 1, 2, 1, 0x00, 340000, 600000},
-{ 25000, 34000, 1205, 312500, 425000, 0x04, 0x01, 0x01, 400, 0x182, 0x00A, 0, 0, 0, 2500000, 3400000, 0, 2, 2, 2, 4, 0x03, 31250, 42500},
-{ 34000, 68000, 1205, 425000, 850000, 0x06, 0x02, 0x01, 300, 0x11E, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 4, 0x02, 42500, 85000},
-{ 68000, 136000, 1205, 850000, 1700000, 0x0D, 0x02, 0x02, 325, 0x137, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 2, 0x01, 85000, 170000},
-{136000, 272000, 1205, 1700000, 3400000, 0x1A, 0x02, 0x04, 325, 0x137, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 1, 0x00, 170000, 340000},
-{272000, 480000, 1205, 3400000, 6000000, 0x30, 0x03, 0x05, 600, 0x24A, 0x00A, 0, 0, 0, 3400000, 6000000, 1, 1, 1, 2, 1, 0x00, 340000, 600000},
+{ 25000, 34000, 1250, 312500, 425000, 0x04, 0x01, 0x01, 400, 0x182, 0x00A, 0, 0, 0, 2500000, 3400000, 0, 2, 2, 2, 4, 0x03, 31250, 42500},
+{ 34000, 68000, 1250, 425000, 850000, 0x06, 0x02, 0x01, 300, 0x11E, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 4, 0x02, 42500, 85000},
+{ 68000, 136000, 1250, 850000, 1700000, 0x0D, 0x02, 0x02, 325, 0x137, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 2, 0x01, 85000, 170000},
+{136000, 272000, 1250, 1700000, 3400000, 0x1A, 0x02, 0x04, 325, 0x137, 0x00A, 0, 0, 0, 1700000, 3400000, 0, 1, 1, 2, 1, 0x00, 170000, 340000},
+{272000, 480000, 1250, 3400000, 6000000, 0x30, 0x03, 0x05, 600, 0x24A, 0x00A, 0, 0, 0, 3400000, 6000000, 1, 1, 1, 2, 1, 0x00, 340000, 600000},
{ 25000, 28000, 1500, 375000, 420000, 0x03, 0x01, 0x01, 360, 0x15A, 0x00A, 0, 0, 0, 3000000, 3360000, 0, 2, 2, 2, 4, 0x03, 37500, 42000},
{ 28000, 56000, 1500, 420000, 840000, 0x06, 0x02, 0x01, 360, 0x15A, 0x00A, 0, 0, 0, 1680000, 3360000, 0, 1, 1, 2, 4, 0x02, 42000, 84000},
{ 56000, 113000, 1500, 840000, 1695000, 0x0B, 0x00, 0x05, 330, 0x13C, 0x00A, 0, 0, 0, 1680000, 3390000, 0, 1, 1, 2, 2, 0x01, 84000, 169500},
--
2.29.2

108
projects/NXP/devices/iMX8/patches/linux/0040-drm-imx-dcss-use-the-external-27MHz-phy-clock.patch
View File

@ -1,108 +0,0 @@
From c2af9b24bfa69ffb12e72153f89ed3bb3245fafb Mon Sep 17 00:00:00 2001
From: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Date: Fri, 22 Nov 2019 10:00:56 +0200
Subject: [PATCH 40/49] drm/imx/dcss: use the external 27MHz phy clock
The 27MHz external oscillator offers a high precision low jitter clock and
is suitable for high pixel clocks modes(ie 4K@60).
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
---
drivers/gpu/drm/imx/dcss/dcss-dev.c | 25 +++++++++++++++++++------
drivers/gpu/drm/imx/dcss/dcss-dtg.c | 11 +++++++++++
2 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/imx/dcss/dcss-dev.c b/drivers/gpu/drm/imx/dcss/dcss-dev.c
index c849533ca83e..1977f6b058f8 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-dev.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-dev.c
@@ -17,6 +17,11 @@
static void dcss_clocks_enable(struct dcss_dev *dcss)
{
+ if (dcss->hdmi_output) {
+ clk_prepare_enable(dcss->pll_phy_ref_clk);
+ clk_prepare_enable(dcss->pll_src_clk);
+ }
+
clk_prepare_enable(dcss->axi_clk);
clk_prepare_enable(dcss->apb_clk);
clk_prepare_enable(dcss->rtrm_clk);
@@ -31,6 +36,11 @@ static void dcss_clocks_disable(struct dcss_dev *dcss)
clk_disable_unprepare(dcss->rtrm_clk);
clk_disable_unprepare(dcss->apb_clk);
clk_disable_unprepare(dcss->axi_clk);
+
+ if (dcss->hdmi_output) {
+ clk_disable_unprepare(dcss->pll_src_clk);
+ clk_disable_unprepare(dcss->pll_phy_ref_clk);
+ }
}
static void dcss_disable_dtg_and_ss_cb(void *data)
@@ -133,17 +143,20 @@ static int dcss_clks_init(struct dcss_dev *dcss)
struct {
const char *id;
struct clk **clk;
+ bool required;
} clks[] = {
- {"apb", &dcss->apb_clk},
- {"axi", &dcss->axi_clk},
- {"pix", &dcss->pix_clk},
- {"rtrm", &dcss->rtrm_clk},
- {"dtrc", &dcss->dtrc_clk},
+ {"apb", &dcss->apb_clk, true},
+ {"axi", &dcss->axi_clk, true},
+ {"pix", &dcss->pix_clk, true},
+ {"rtrm", &dcss->rtrm_clk, true},
+ {"dtrc", &dcss->dtrc_clk, true},
+ {"pll_src", &dcss->pll_src_clk, dcss->hdmi_output},
+ {"pll_phy_ref", &dcss->pll_phy_ref_clk, dcss->hdmi_output},
};
for (i = 0; i < ARRAY_SIZE(clks); i++) {
*clks[i].clk = devm_clk_get(dcss->dev, clks[i].id);
- if (IS_ERR(*clks[i].clk)) {
+ if (IS_ERR(*clks[i].clk) && clks[i].required) {
dev_err(dcss->dev, "failed to get %s clock\n",
clks[i].id);
return PTR_ERR(*clks[i].clk);
diff --git a/drivers/gpu/drm/imx/dcss/dcss-dtg.c b/drivers/gpu/drm/imx/dcss/dcss-dtg.c
index 30de00540f63..b70785d69ad9 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-dtg.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-dtg.c
@@ -83,6 +83,7 @@ struct dcss_dtg {
u32 ctx_id;
bool in_use;
+ bool hdmi_output;
u32 dis_ulc_x;
u32 dis_ulc_y;
@@ -159,6 +160,7 @@ int dcss_dtg_init(struct dcss_dev *dcss, unsigned long dtg_base)
dcss->dtg = dtg;
dtg->dev = dcss->dev;
dtg->ctxld = dcss->ctxld;
+ dtg->hdmi_output = dcss->hdmi_output;
dtg->base_reg = ioremap(dtg_base, SZ_4K);
if (!dtg->base_reg) {
@@ -221,6 +223,15 @@ void dcss_dtg_sync_set(struct dcss_dtg *dtg, struct videomode *vm)
vm->vactive - 1;
clk_disable_unprepare(dcss->pix_clk);
+ if (dcss->hdmi_output) {
+ int err;
+
+ clk_disable_unprepare(dcss->pll_src_clk);
+ err = clk_set_parent(dcss->pll_src_clk, dcss->pll_phy_ref_clk);
+ if (err < 0)
+ dev_warn(dcss->dev, "clk_set_parent() returned %d", err);
+ clk_prepare_enable(dcss->pll_src_clk);
+ }
clk_set_rate(dcss->pix_clk, vm->pixelclock);
clk_prepare_enable(dcss->pix_clk);
--
2.29.2

228
projects/NXP/devices/iMX8/patches/linux/0041-drm-imx-dcss-add-component-framework-functionality.patch
View File

@ -1,228 +0,0 @@
From ec59d2988d1ac50acea0fdaa63513f216ddf016d Mon Sep 17 00:00:00 2001
From: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Date: Thu, 9 Jul 2020 19:47:31 +0300
Subject: [PATCH 41/49] drm/imx/dcss: add component framework functionality
Component framework is needed by HDP driver.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
---
drivers/gpu/drm/imx/dcss/dcss-drv.c | 89 ++++++++++++++++++++++-------
drivers/gpu/drm/imx/dcss/dcss-kms.c | 23 +++++---
drivers/gpu/drm/imx/dcss/dcss-kms.h | 4 +-
3 files changed, 85 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/imx/dcss/dcss-drv.c b/drivers/gpu/drm/imx/dcss/dcss-drv.c
index 8dc2f85c514b..09d0ac28e28a 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-drv.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-drv.c
@@ -8,6 +8,7 @@
#include <linux/of.h>
#include <linux/platform_device.h>
#include <drm/drm_module.h>
+#include <linux/component.h>
#include <drm/drm_of.h>
#include "dcss-dev.h"
@@ -16,6 +17,8 @@
struct dcss_drv {
struct dcss_dev *dcss;
struct dcss_kms_dev *kms;
+
+ bool is_componentized;
};
struct dcss_dev *dcss_drv_dev_to_dcss(struct device *dev)
@@ -32,30 +35,18 @@ struct drm_device *dcss_drv_dev_to_drm(struct device *dev)
return mdrv ? &mdrv->kms->base : NULL;
}
-static int dcss_drv_platform_probe(struct platform_device *pdev)
+static int dcss_drv_init(struct device *dev, bool componentized)
{
- struct device *dev = &pdev->dev;
- struct device_node *remote;
struct dcss_drv *mdrv;
int err = 0;
- bool hdmi_output = true;
-
- if (!dev->of_node)
- return -ENODEV;
-
- remote = of_graph_get_remote_node(dev->of_node, 0, 0);
- if (!remote)
- return -ENODEV;
-
- hdmi_output = !of_device_is_compatible(remote, "fsl,imx8mq-nwl-dsi");
-
- of_node_put(remote);
mdrv = devm_kzalloc(dev, sizeof(*mdrv), GFP_KERNEL);
if (!mdrv)
return -ENOMEM;
- mdrv->dcss = dcss_dev_create(dev, hdmi_output);
+ mdrv->is_componentized = componentized;
+
+ mdrv->dcss = dcss_dev_create(dev, componentized);
if (IS_ERR(mdrv->dcss))
return PTR_ERR(mdrv->dcss);
@@ -61,7 +52,7 @@ static int dcss_drv_platform_probe(struct platform_device *pdev)
dev_set_drvdata(dev, mdrv);
- mdrv->kms = dcss_kms_attach(mdrv->dcss);
+ mdrv->kms = dcss_kms_attach(mdrv->dcss, componentized);
if (IS_ERR(mdrv->kms)) {
err = PTR_ERR(mdrv->kms);
dev_err_probe(dev, err, "Failed to initialize KMS\n");
@@ -76,12 +67,66 @@ static int dcss_drv_platform_probe(struct platform_device *pdev)
return err;
}
-static void dcss_drv_platform_remove(struct platform_device *pdev)
+static void dcss_drv_deinit(struct device *dev, bool componentized)
{
- struct dcss_drv *mdrv = dev_get_drvdata(&pdev->dev);
+ struct dcss_drv *mdrv = dev_get_drvdata(dev);
- dcss_kms_detach(mdrv->kms);
+ dcss_kms_detach(mdrv->kms, componentized);
dcss_dev_destroy(mdrv->dcss);
+}
+
+static int dcss_drv_bind(struct device *dev)
+{
+ return dcss_drv_init(dev, true);
+}
+
+static void dcss_drv_unbind(struct device *dev)
+{
+ return dcss_drv_deinit(dev, true);
+}
+
+static const struct component_master_ops dcss_master_ops = {
+ .bind = dcss_drv_bind,
+ .unbind = dcss_drv_unbind,
+};
+
+static int compare_of(struct device *dev, void *data)
+{
+ return dev->of_node == data;
+}
+
+static int dcss_drv_platform_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct component_match *match = NULL;
+ struct device_node *remote;
+
+ if (!dev->of_node)
+ return -ENODEV;
+
+ remote = of_graph_get_remote_node(dev->of_node, 0, 0);
+ if (!remote)
+ return -ENODEV;
+
+ if (of_device_is_compatible(remote, "fsl,imx8mq-nwl-dsi")) {
+ of_node_put(remote);
+ return dcss_drv_init(dev, false);
+ }
+
+ drm_of_component_match_add(dev, &match, compare_of, remote);
+ of_node_put(remote);
+
+ return component_master_add_with_match(dev, &dcss_master_ops, match);
+}
+
+static void dcss_drv_platform_remove(struct platform_device *pdev)
+{
+ struct dcss_drv *mdrv = dev_get_drvdata(&pdev->dev);
+
+ if (mdrv->is_componentized)
+ component_master_del(&pdev->dev, &dcss_master_ops);
+ else
+ dcss_drv_deinit(&pdev->dev, false);
}
static void dcss_drv_platform_shutdown(struct platform_device *pdev)
diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.c b/drivers/gpu/drm/imx/dcss/dcss-kms.c
index 135a62366ab8..cafb09df6c75 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-kms.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-kms.c
@@ -13,6 +13,7 @@
#include <drm/drm_of.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_vblank.h>
+#include <linux/component.h>
#include "dcss-dev.h"
#include "dcss-kms.h"
@@ -123,7 +124,7 @@ static int dcss_kms_bridge_connector_init(struct dcss_kms_dev *kms)
return 0;
}
-struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss)
+struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss, bool componentized)
{
struct dcss_kms_dev *kms;
struct drm_device *drm;
@@ -148,13 +149,16 @@ struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss)
goto cleanup_mode_config;
- ret = dcss_kms_bridge_connector_init(kms);
+ ret = dcss_crtc_init(crtc, drm);
if (ret)
goto cleanup_mode_config;
- ret = dcss_crtc_init(crtc, drm);
+ if (componentized)
+ ret = component_bind_all(dcss->dev, kms);
+ else
+ ret = dcss_kms_bridge_connector_init(kms);
if (ret)
- goto cleanup_mode_config;
+ goto cleanup_crtc;
drm_mode_config_reset(drm);
@@ -182,9 +188,10 @@ struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss)
return ERR_PTR(ret);
}
-void dcss_kms_detach(struct dcss_kms_dev *kms)
+void dcss_kms_detach(struct dcss_kms_dev *kms, bool componentized)
{
struct drm_device *drm = &kms->base;
+ struct dcss_dev *dcss = drm->dev_private;
drm_dev_unregister(drm);
drm_bridge_connector_disable_hpd(kms->connector);
@@ -194,5 +201,7 @@ void dcss_kms_detach(struct dcss_kms_dev *kms)
drm->irq_enabled = false;
drm_mode_config_cleanup(drm);
dcss_crtc_deinit(&kms->crtc, drm);
+ if (componentized)
+ component_unbind_all(dcss->dev, drm);
drm->dev_private = NULL;
}
diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.h b/drivers/gpu/drm/imx/dcss/dcss-kms.h
index dfe5dd99eea3..e98d9c587a43 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-kms.h
+++ b/drivers/gpu/drm/imx/dcss/dcss-kms.h
@@ -32,8 +32,8 @@ struct dcss_kms_dev {
struct drm_connector *connector;
};
-struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss);
-void dcss_kms_detach(struct dcss_kms_dev *kms);
+struct dcss_kms_dev *dcss_kms_attach(struct dcss_dev *dcss, bool componentized);
+void dcss_kms_detach(struct dcss_kms_dev *kms, bool componentized);
void dcss_kms_shutdown(struct dcss_kms_dev *kms);
int dcss_crtc_init(struct dcss_crtc *crtc, struct drm_device *drm);
void dcss_crtc_deinit(struct dcss_crtc *crtc, struct drm_device *drm);
--
2.29.2

49
projects/NXP/devices/iMX8/patches/linux/0043-arm64-dts-imx8mq-add-DCSS-node.patch
View File

@ -1,49 +0,0 @@
From bd9c83ea41380f584fdd8f2781112b530c84ebba Mon Sep 17 00:00:00 2001
From: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Date: Thu, 9 Jul 2020 19:47:33 +0300
Subject: [PATCH 43/49] arm64: dts: imx8mq: add DCSS node
This patch adds the node for iMX8MQ Display Controller Subsystem.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 5e0e7d0f1bc4..5a617f9ed8b5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1103,6 +1103,29 @@ bus@32c00000 { /* AIPS4 */
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
+ dcss: display-controller@32e00000 {
+ compatible = "nxp,imx8mq-dcss";
+ reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
+ interrupts = <6>, <8>, <9>;
+ interrupt-names = "ctxld", "ctxld_kick", "vblank";
+ interrupt-parent = <&irqsteer>;
+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
+ <&clk IMX8MQ_VIDEO2_PLL_OUT>,
+ <&clk IMX8MQ_CLK_DISP_DTRC>;
+ clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+ assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>,
+ <&clk IMX8MQ_CLK_DISP_RTRM>,
+ <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_CLK_27M>;
+ assigned-clock-rates = <800000000>,
+ <400000000>;
+ status = "disabled";
+ };
+
irqsteer: interrupt-controller@32e2d000 {
compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
reg = <0x32e2d000 0x1000>;
--
2.29.2

35
projects/NXP/devices/iMX8/patches/linux/0044-arm64-dts-imx8mq-add-DCSS-external-oscillator-suppor.patch
View File

@ -1,35 +0,0 @@
From 8e5a885158f430de3ea36b1439dd8c0058ce95df Mon Sep 17 00:00:00 2001
From: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Date: Fri, 22 Nov 2019 10:12:50 +0200
Subject: [PATCH 44/49] arm64: dts: imx8mq: add DCSS external oscillator
support
The external oscillator, which is high precision, will be used when DCSS output
goes to HDMI.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 5a617f9ed8b5..b75252a65c44 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1113,8 +1113,11 @@ dcss: display-controller@32e00000 {
<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
<&clk IMX8MQ_VIDEO2_PLL_OUT>,
- <&clk IMX8MQ_CLK_DISP_DTRC>;
- clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+ <&clk IMX8MQ_CLK_DISP_DTRC>,
+ <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>,
+ <&clk IMX8MQ_CLK_PHY_27MHZ>;
+ clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll_src",
+ "pll_phy_ref";
assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>,
<&clk IMX8MQ_CLK_DISP_RTRM>,
<&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
--
2.29.2

34
projects/NXP/devices/iMX8/patches/linux/0045-arm64-dts-fsl-imx8mq-add-HDP-bridge-node.patch
View File

@ -1,34 +0,0 @@
From 0327e9fc14269069711cd2d45d60130b318532fe Mon Sep 17 00:00:00 2001
From: Lucas Stach <l.stach@pengutronix.de>
Date: Tue, 13 Feb 2018 12:30:58 +0100
Subject: [PATCH 45/49] arm64: dts: fsl: imx8mq: add HDP bridge node
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index b75252a65c44..aad21d6f1da7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1103,6 +1103,16 @@ bus@32c00000 { /* AIPS4 */
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
+ hdmi: hdmi@32c00000 {
+ reg = <0x32c00000 0x33800>, /* HDP registers */
+ <0x32e40000 0x40000>, /* HDP SEC register */
+ <0x32e2f000 0x10>; /* RESET register */
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "plug_in", "plug_out";
+ status = "disabled";
+ };
+
dcss: display-controller@32e00000 {
compatible = "nxp,imx8mq-dcss";
reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
--
2.29.2

53
projects/NXP/devices/iMX8/patches/linux/0046-arm64-dts-fsl-imx8mq-evk-enable-DCSS-and-HDMI.patch
View File

@ -1,53 +0,0 @@
From 96ab278661207096c013ad1b39ed36f5f9a35ffd Mon Sep 17 00:00:00 2001
From: Lucas Stach <l.stach@pengutronix.de>
Date: Tue, 13 Feb 2018 12:47:09 +0100
Subject: [PATCH 46/49] arm64: dts: fsl: imx8mq-evk: enable DCSS and HDMI
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 22 ++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 2418cca00bc5..71eeda6de3d7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -132,6 +132,16 @@ opp-800M {
};
};
+&dcss {
+ status = "okay";
+
+ port {
+ dcss_out: endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+};
+
&dphy {
status = "okay";
};
@@ -168,6 +178,18 @@ wl-reg-on-hog {
};
};
+&hdmi {
+ compatible = "cdn,imx8mq-hdmi";
+ lane-mapping = <0xe4>;
+ status = "okay";
+
+ port {
+ hdmi_in: endpoint {
+ remote-endpoint = <&dcss_out>;
+ };
+ };
+};
+
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
--
2.29.2

52
projects/NXP/devices/iMX8/patches/linux/0047-arm64-dts-fsl-imx8mq-pico-pi-enable-DCSS-and-HDMI.patch
View File

@ -1,52 +0,0 @@
From 5a139d07d03076be7972db4b022558dffcfd685b Mon Sep 17 00:00:00 2001
From: Lukas Rusak <lorusak@gmail.com>
Date: Tue, 9 Mar 2021 10:47:27 -0800
Subject: [PATCH 47/49] arm64: dts: fsl: imx8mq-pico-pi: enable DCSS and HDMI
---
.../boot/dts/freescale/imx8mq-pico-pi.dts | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
index 89cbec5c41b2..03734145c50e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
@@ -37,6 +37,16 @@ reg_usb_otg_vbus: regulator-usb-otg-vbus {
};
};
+&dcss {
+ status = "okay";
+
+ port {
+ dcss_out: endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+};
+
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>;
@@ -56,6 +66,18 @@ ethphy0: ethernet-phy@1 {
};
};
+&hdmi {
+ compatible = "cdn,imx8mq-hdmi";
+ lane-mapping = <0xe4>;
+ status = "okay";
+
+ port {
+ hdmi_in: endpoint {
+ remote-endpoint = <&dcss_out>;
+ };
+ };
+};
+
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
--
2.29.2

23
projects/NXP/devices/iMX8/patches/linux/0048-drm-imx-mhdp-don-t-depend-on-DRM_IMX.patch
View File

@ -1,23 +0,0 @@
From f94717816b9a39869219ede859fe74af3f2ecd19 Mon Sep 17 00:00:00 2001
From: Lukas Rusak <lorusak@gmail.com>
Date: Wed, 24 Mar 2021 14:27:43 -0700
Subject: [PATCH 48/49] drm: imx: mhdp: don't depend on DRM_IMX
---
drivers/gpu/drm/imx/mhdp/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/imx/mhdp/Kconfig b/drivers/gpu/drm/imx/mhdp/Kconfig
index 86950badb947..cf7dfacdd434 100644
--- a/drivers/gpu/drm/imx/mhdp/Kconfig
+++ b/drivers/gpu/drm/imx/mhdp/Kconfig
@@ -6,6 +6,5 @@ config DRM_IMX_CDNS_MHDP
select DRM_CDNS_DP
select DRM_CDNS_HDMI
select DRM_CDNS_AUDIO
- depends on DRM_IMX
help
Choose this if you want to use HDMI on i.MX8.
--
2.29.2

27
projects/NXP/devices/iMX8/patches/linux/0049-drm-cadence-shutup-cec-logging.patch
View File

@ -1,27 +0,0 @@
From 3111faf58971c2c517457e62f84d138a3d62464e Mon Sep 17 00:00:00 2001
From: Lukas Rusak <lorusak@gmail.com>
Date: Wed, 24 Mar 2021 15:14:57 -0700
Subject: [PATCH 49/49] drm: cadence: shutup cec logging
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c
index 25cf9e91e64f..e91de13eae58 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-cec.c
@@ -171,8 +171,8 @@ static u32 mhdp_cec_write_message(struct cdns_mhdp_cec *cec, struct cec_msg *msg
return -EINVAL;
}
- for (i = 0; i < msg->len; ++i)
- printk("msg[%d]=0x%x\n",i, msg->msg[i]);
+ // for (i = 0; i < msg->len; ++i)
+ // printk("msg[%d]=0x%x\n",i, msg->msg[i]);
/* Write Message to register */
for (i = 0; i < msg->len; ++i) {
--
2.29.2

21
projects/NXP/devices/iMX8/patches/linux/0050-drm-display-drm-hdmi-helper-h.patch
View File

@ -1,21 +0,0 @@
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c 2022-06-28 15:48:27.254022595 +0000
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c 2022-06-28 15:46:14.919939083 +0000
@@ -14,6 +14,8 @@
#include <drm/drm_edid.h>
#include <drm/drm_encoder_slave.h>
#include <drm/display/drm_hdcp.h>
+#include <drm/display/drm_hdcp_helper.h>
+#include <drm/display/drm_hdmi_helper.h>
#include <drm/drm_of.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_print.h>
--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-hdcp.c 2022-06-28 15:53:59.618466556 +0000
+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-hdcp.c 2022-06-28 15:56:01.987635836 +0000
@@ -11,6 +11,7 @@
*/
#include <drm/bridge/cdns-mhdp.h>
#include <drm/display/drm_hdcp.h>
+#include <drm/display/drm_hdcp_helper.h>
#include <drm/drm_print.h>
#include <linux/firmware.h>

10
projects/NXP/devices/iMX8/patches/linux/0060-mhdp-dp-hdmi-add-missing-include-patch-for-6-3.patch
View File

@ -1,10 +0,0 @@
--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c 2023-04-24 10:04:54.095068512 +0000
+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c 2023-04-25 13:35:44.405261313 +0000
@@ -12,6 +12,7 @@
#include <drm/drm_vblank.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_encoder_slave.h>
+#include <drm/drm_modeset_helper_vtables.h>
#include <uapi/linux/media-bus-format.h>

4
scripts/uboot_helper
View File

@ -258,6 +258,10 @@ devices = \
'dtb' : 'imx8mq-evk.dtb',
'config' : 'imx8mq_evk_defconfig'
},
'phanbell' : {
'dtb' : 'imx8mq-phanbell.dtb',
'config' : 'imx8mq_phanbell_defconfig'
},
'pico-mq' : {
'dtb' : 'imx8mq-pico-pi.dtb',
'config' : 'pico-imx8mq_defconfig'