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linux: update to 6.6.57
deleted: projects/Rockchip/patches/linux/default/linux-0003-pinctrl--rockchip--correct-RK3328-iomux-width-flag-for-GPIO2-B-pins.patch modified: projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch removed hunks 11 and 47
This commit is contained in:
Peter Tuschy
parent
a0b38747d8
commit
4df04d47b2
@ -29,8 +29,8 @@ case "${LINUX}" in
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PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz"
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;;
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*)
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PKG_VERSION="6.6.46"
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PKG_SHA256="052f932396d9c7d84ceeda91226a8ef797c12188bde41e6c419602d990dd45f2"
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PKG_VERSION="6.6.57"
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PKG_SHA256="66ce426ef96f99b8e1ef7ac72e780c730ef8b970f7aa5708501c4274d7abb7b3"
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PKG_URL="https://www.kernel.org/pub/linux/kernel/v${PKG_VERSION/.*/}.x/${PKG_NAME}-${PKG_VERSION}.tar.xz"
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PKG_PATCH_DIRS="default"
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;;
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@ -1,55 +0,0 @@
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From e0e1d9a46cbcebf4faa5e3deacefe9934886bea1 Mon Sep 17 00:00:00 2001
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From: Huang-Huang Bao <i@eh5.me>
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Date: Tue, 9 Jul 2024 18:54:28 +0800
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Subject: pinctrl: rockchip: correct RK3328 iomux width flag for GPIO2-B pins
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commit 128f71fe014fc91efa1407ce549f94a9a9f1072c upstream.
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The base iomux offsets for each GPIO pin line are accumulatively
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calculated based off iomux width flag in rockchip_pinctrl_get_soc_data.
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If the iomux width flag is one of IOMUX_WIDTH_4BIT, IOMUX_WIDTH_3BIT or
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IOMUX_WIDTH_2BIT, the base offset for next pin line would increase by 8
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bytes, otherwise it would increase by 4 bytes.
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Despite most of GPIO2-B iomux have 2-bit data width, which can be fit
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into 4 bytes space with write mask, it actually take 8 bytes width for
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whole GPIO2-B line.
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Commit e8448a6c817c ("pinctrl: rockchip: fix pinmux bits for RK3328
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GPIO2-B pins") wrongly set iomux width flag to 0, causing all base
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iomux offset for line after GPIO2-B to be calculated wrong. Fix the
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iomux width flag to IOMUX_WIDTH_2BIT so the offset after GPIO2-B is
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correctly increased by 8, matching the actual width of GPIO2-B iomux.
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Fixes: e8448a6c817c ("pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins")
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Cc: stable@vger.kernel.org
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Reported-by: Richard Kojedzinszky <richard@kojedz.in>
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Closes: https://lore.kernel.org/linux-rockchip/4f29b743202397d60edfb3c725537415@kojedz.in/
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Tested-by: Richard Kojedzinszky <richard@kojedz.in>
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Signed-off-by: Huang-Huang Bao <i@eh5.me>
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Reviewed-by: Heiko Stuebner <heiko@sntech.de>
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Tested-by: Daniel Golle <daniel@makrotopia.org>
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Tested-by: Trevor Woerner <twoerner@gmail.com>
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Link: https://lore.kernel.org/20240709105428.1176375-1-i@eh5.me
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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drivers/pinctrl/pinctrl-rockchip.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
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index b02eaba010d101..b5a02335617d77 100644
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--- a/drivers/pinctrl/pinctrl-rockchip.c
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+++ b/drivers/pinctrl/pinctrl-rockchip.c
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@@ -3802,7 +3802,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
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PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
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- 0,
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+ IOMUX_WIDTH_2BIT,
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IOMUX_WIDTH_3BIT,
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0),
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PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
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--
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cgit 1.2.3-korg
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@ -631,30 +631,6 @@ index 38dded2baaf7..9e460b7e14a4 100644
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err_clk:
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regulator_disable(hdmi->avdd_1v8);
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Wed, 8 Jan 2020 21:07:50 +0000
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Subject: [PATCH] clk: rockchip: set parent rate for DCLK_VOP clock on rk3228
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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---
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drivers/clk/rockchip/clk-rk3228.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
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index a24a35553e13..7343d2d7676b 100644
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--- a/drivers/clk/rockchip/clk-rk3228.c
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+++ b/drivers/clk/rockchip/clk-rk3228.c
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@@ -409,7 +409,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
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DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
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RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
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- MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,
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+ MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
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FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Sat, 10 Oct 2020 14:32:21 +0000
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@ -2662,37 +2638,6 @@ index ae4c49e84470..92e621f2714f 100644
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static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Alex Bee <knaerzche@gmail.com>
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Date: Tue, 1 Jun 2021 19:24:37 +0200
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Subject: [PATCH] drm/rockchip: allow 4096px width modes
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There is not reason to limit vop output to 3840px width modes.
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Also drop the limitation from dw_hdmi_rockchip_mode_valid, since
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the max dimenstions of the actual vop version is validated in
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vop_crtc_mode_valid anyways.
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Signed-off-by: Alex Bee <knaerzche@gmail.com>
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---
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drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
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index ef0a078c22f4..49619f794061 100644
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--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
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+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
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@@ -424,8 +424,8 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
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if (info->is_yuv)
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is_yuv = true;
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- if (dst_w > 3840) {
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- DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
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+ if (dst_w > 4096) {
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+ DRM_DEV_ERROR(vop->dev, "Maximum dst width (4096) exceeded\n");
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return;
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}
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Tue, 1 Oct 2019 20:52:42 +0000
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