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Merge pull request #1089 from MilhouseVH/rm_intel_gpu_fix
linux: drop gpu fix, rejected by intel, may cause issues
This commit is contained in:
Christian Hewitt
GitHub
commit
4f8bbe3583
@ -1,184 +0,0 @@
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From patchwork Thu Sep 15 07:27:32 2016
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: DRM: i915: Fix random GPU hang, Bug 156851
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From: bobcao3 <bobcaocheng@163.com>
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X-Patchwork-Id: 9332989
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Message-Id: <20160915072732.11950-1-bobcaocheng@163.com>
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To: Daniel Vetter <daniel.vetter@intel.com>,
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Jani Nikula <jani.nikula@linux.intel.com>, David Airlie <airlied@linux.ie>
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Cc: Cheng Cao <bobcaocheng@163.com>, intel-gfx@lists.freedesktop.org,
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linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
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Icenowy Zheng <icenowy@aosc.xyz>
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Date: Thu, 15 Sep 2016 15:27:32 +0800
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Signed-off-by: Cheng Cao <bobcaocheng@163.com>
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---
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drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++++
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drivers/gpu/drm/i915/i915_gem_stolen.c | 61 ++++++++++++++++-----------------
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drivers/gpu/drm/i915/i915_reg.h | 6 ++++
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drivers/gpu/drm/i915/intel_ringbuffer.c | 20 ++++++++++-
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4 files changed, 60 insertions(+), 33 deletions(-)
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diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
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index 7a30af7..0b05dd9 100644
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--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
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+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
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@@ -2907,6 +2907,12 @@ static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
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if (bdw_gmch_ctl > 4)
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bdw_gmch_ctl = 4;
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#endif
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+#ifdef CONFIG_X86_64
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+ /* Limit 64b platforms to a 4GB GGTT */
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+ /* DMA 4GB protection */
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+ if (bdw_gmch_ctl > 8)
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+ bdw_gmch_ctl = 8;
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+#endif
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return bdw_gmch_ctl << 20;
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}
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diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
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index 66be299a1..da272ae 100644
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--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
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+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
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@@ -352,47 +352,44 @@ static void gen8_get_stolen_reserved(struct drm_i915_private *dev_priv,
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unsigned long *base, unsigned long *size)
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{
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uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
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+ unsigned long stolen_top;
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+ struct i915_ggtt *ggtt = &dev_priv->ggtt;
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*base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
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switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
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case GEN8_STOLEN_RESERVED_1M:
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- *size = 1024 * 1024;
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+ *size = 1 << 10 << 10;
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break;
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case GEN8_STOLEN_RESERVED_2M:
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- *size = 2 * 1024 * 1024;
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+ *size = 2 << 10 << 10;
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break;
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case GEN8_STOLEN_RESERVED_4M:
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- *size = 4 * 1024 * 1024;
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+ *size = 4 << 10 << 10;
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break;
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case GEN8_STOLEN_RESERVED_8M:
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- *size = 8 * 1024 * 1024;
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+ *size = 8 << 10 << 10;
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break;
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default:
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- *size = 8 * 1024 * 1024;
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- MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
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- }
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-}
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-
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-static void bdw_get_stolen_reserved(struct drm_i915_private *dev_priv,
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- unsigned long *base, unsigned long *size)
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-{
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- struct i915_ggtt *ggtt = &dev_priv->ggtt;
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- uint32_t reg_val = I915_READ(GEN6_STOLEN_RESERVED);
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- unsigned long stolen_top;
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+ /* Whatever if it is a BDW device or SKL device
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+ * Or others devices..
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+ * This way is always going to work on 5th
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+ * generation Intel Processer
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+ */
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+ stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size;
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- stolen_top = dev_priv->mm.stolen_base + ggtt->stolen_size;
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+ *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
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- *base = reg_val & GEN6_STOLEN_RESERVED_ADDR_MASK;
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+ /* MLIMIT - MBASE => PEG */
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+ /* -- mobile-5th-gen-core-family-datasheet-vol-2.pdf */
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+ if (*base == 0) {
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+ *size = 0;
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+ MISSING_CASE(reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK);
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+ } else
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+ *size = stolen_top - *base;
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- /* On these platforms, the register doesn't have a size field, so the
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- * size is the distance between the base and the top of the stolen
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- * memory. We also have the genuine case where base is zero and there's
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- * nothing reserved. */
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- if (*base == 0)
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- *size = 0;
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- else
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- *size = stolen_top - *base;
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+ break;
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+ }
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}
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int i915_gem_init_stolen(struct drm_device *dev)
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@@ -442,14 +439,14 @@ int i915_gem_init_stolen(struct drm_device *dev)
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gen7_get_stolen_reserved(dev_priv, &reserved_base,
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&reserved_size);
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break;
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+ case 8:
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+ gen8_get_stolen_reserved(dev_priv, &reserved_base,
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+ &reserved_size);
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+ break;
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default:
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- if (IS_BROADWELL(dev_priv) ||
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- IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev))
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- bdw_get_stolen_reserved(dev_priv, &reserved_base,
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- &reserved_size);
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- else
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- gen8_get_stolen_reserved(dev_priv, &reserved_base,
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- &reserved_size);
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+ // FIXME: This seemed like going to work
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+ gen8_get_stolen_reserved(dev_priv, &reserved_base,
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+ &reserved_size);
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break;
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}
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diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
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index bf2cad3..3dce37b 100644
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--- a/drivers/gpu/drm/i915/i915_reg.h
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+++ b/drivers/gpu/drm/i915/i915_reg.h
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@@ -1748,6 +1748,12 @@ enum skl_disp_power_wells {
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#define RING_INDIRECT_CTX_OFFSET(base) _MMIO((base)+0x1c8) /* gen8+ */
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#define RING_CTX_TIMESTAMP(base) _MMIO((base)+0x3a8) /* gen8+ */
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+// 64 bit, low 32 preserved
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+#define IOTLB_INVALID(base) _MMIO((base)+0x508 + 4) /* gen8+ */
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+#define IOTLB_INVALID_IVT (1<<31)
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+#define IOTLB_GLOBAL_INV_REQ (1<<28)
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+#define IOTLB_INVALID_IAIG (1<<25)
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+
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#define ERROR_GEN6 _MMIO(0x40a0)
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#define GEN7_ERR_INT _MMIO(0x44040)
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#define ERR_INT_POISON (1<<31)
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diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
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index 1d3161b..84dafcb 100644
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--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
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+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
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@@ -498,7 +498,25 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
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* arises: do we still need this and if so how should we go about
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* invalidating the TLB?
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*/
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- if (IS_GEN(dev_priv, 6, 7)) {
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+ /* Respond to this question:
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+ * According to mobile-5th-gen-core-family-datasheet-vol-2 from Intel
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+ * There are registers for invalidation, set those registers will
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+ * cause the hardware to perform IOTLB invalidation.
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+ */
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+ if (IS_GEN8(dev_priv)) {
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+ i915_reg_t reg = IOTLB_INVALID(engine->mmio_base);
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+
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+ /* ring should be idle before issuing a sync flush*/
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+ WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
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+
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+ I915_WRITE(reg, 0x0 | IOTLB_INVALID_IVT | IOTLB_GLOBAL_INV_REQ);
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+
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+ if (intel_wait_for_register(dev_priv,
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+ reg, IOTLB_INVALID_IAIG, 0,
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+ 1000))
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+ DRM_ERROR("%s: wait for TLB invalidation timed out\n",
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+ engine->name);
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+ } else if (IS_GEN(dev_priv, 6, 7)) {
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i915_reg_t reg = RING_INSTPM(engine->mmio_base);
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/* ring should be idle before issuing a sync flush*/
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