From 5273f889964c42e88fe02289290c3c6cb6086770 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sun, 2 Dec 2018 08:39:37 +0100 Subject: [PATCH] gpu-sunxi-midgard: Initial package --- .../gpu-sunxi-midgard/package.mk | 27 + .../patches/01-add-bus-clk-and-reset.patch | 89 + .../patches/02-restore-old-api.patch | 1880 +++++++++++++++++ ...-arm-Midgard-setup_timer-timer_setup.patch | 98 + ...Midgard-Replace-ACCESS_ONCE-by-READ_.patch | 35 + ...-midgard-Remove-sys_close-references.patch | 32 + .../patches/06-fix-4.20-build.patch | 60 + .../patches/07-some-fixes.patch | 30 + .../patches/08-fix-building-with-5.0.patch | 15 + 9 files changed, 2266 insertions(+) create mode 100644 packages/linux-drivers/gpu-sunxi-midgard/package.mk create mode 100644 packages/linux-drivers/gpu-sunxi-midgard/patches/01-add-bus-clk-and-reset.patch create mode 100644 packages/linux-drivers/gpu-sunxi-midgard/patches/02-restore-old-api.patch create mode 100644 packages/linux-drivers/gpu-sunxi-midgard/patches/03-gpu-arm-Midgard-setup_timer-timer_setup.patch create mode 100644 packages/linux-drivers/gpu-sunxi-midgard/patches/04-drivers-gpu-Arm-Midgard-Replace-ACCESS_ONCE-by-READ_.patch create mode 100644 packages/linux-drivers/gpu-sunxi-midgard/patches/05-gpu-arm-midgard-Remove-sys_close-references.patch create mode 100644 packages/linux-drivers/gpu-sunxi-midgard/patches/06-fix-4.20-build.patch create mode 100644 packages/linux-drivers/gpu-sunxi-midgard/patches/07-some-fixes.patch create mode 100644 packages/linux-drivers/gpu-sunxi-midgard/patches/08-fix-building-with-5.0.patch diff --git a/packages/linux-drivers/gpu-sunxi-midgard/package.mk b/packages/linux-drivers/gpu-sunxi-midgard/package.mk new file mode 100644 index 0000000000..1c6769acdf --- /dev/null +++ b/packages/linux-drivers/gpu-sunxi-midgard/package.mk @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv) + +PKG_NAME="gpu-sunxi-midgard" +PKG_VERSION="r22p0-01rel0" +PKG_SHA256="02f80e777dc945d645fce888afc926555ec61b70079c1da289bf1a3a9544452f" +PKG_ARCH="arm aarch64" +PKG_LICENSE="GPL" +PKG_SITE="https://developer.arm.com/products/software/mali-drivers/" +PKG_URL="https://developer.arm.com/-/media/Files/downloads/mali-drivers/kernel/mali-midgard-gpu/TX011-SW-99002-$PKG_VERSION.tgz" +PKG_DEPENDS_TARGET="toolchain linux" +PKG_NEED_UNPACK="$LINUX_DEPENDS" +PKG_LONGDESC="gpu-sunxi-midgard: Linux drivers for Mali GPUs found in Allwinner SoCs" +PKG_TOOLCHAIN="manual" +PKG_IS_KERNEL_PKG="yes" + +make_target() { + kernel_make -C $(kernel_path) M=$PKG_BUILD/driver/product/kernel/drivers/gpu/arm/midgard/ \ + EXTRA_CFLAGS="-DCONFIG_MALI_PLATFORM_DEVICETREE -DCONFIG_MALI_BACKEND=gpu -DCONFIG_MALI_DEVFREQ" CONFIG_MALI_DEVFREQ=y \ + CONFIG_MALI_MIDGARD=m CONFIG_MALI_PLATFORM_DEVICETREE=y CONFIG_MALI_BACKEND=gpu modules +} + +makeinstall_target() { + kernel_make -C $(kernel_path) M=$PKG_BUILD/driver/product/kernel/drivers/gpu/arm/midgard/ \ + INSTALL_MOD_PATH=$INSTALL/$(get_kernel_overlay_dir) INSTALL_MOD_STRIP=1 DEPMOD=: \ + modules_install +} diff --git a/packages/linux-drivers/gpu-sunxi-midgard/patches/01-add-bus-clk-and-reset.patch b/packages/linux-drivers/gpu-sunxi-midgard/patches/01-add-bus-clk-and-reset.patch new file mode 100644 index 0000000000..5474b90262 --- /dev/null +++ b/packages/linux-drivers/gpu-sunxi-midgard/patches/01-add-bus-clk-and-reset.patch @@ -0,0 +1,89 @@ +diff -Nur a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_core_linux.c b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_core_linux.c +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_core_linux.c 2018-03-06 18:05:25.000000000 +0100 ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_core_linux.c 2018-04-04 22:26:50.310273475 +0200 +@@ -3225,6 +3225,20 @@ + } + #endif /* LINUX_VERSION_CODE >= 3, 12, 0 */ + ++ kbdev->mali_rst = of_reset_control_get_by_index(kbdev->dev->of_node, 0); ++ if (IS_ERR(kbdev->mali_rst)) { ++ dev_err(kbdev->dev, "Couldn't get mali reset line\n"); ++ err = PTR_ERR(kbdev->mali_rst); ++ goto fail; ++ } ++ ++ kbdev->bus_clk = of_clk_get(kbdev->dev->of_node, 1); ++ if (IS_ERR(kbdev->bus_clk)) { ++ dev_err(kbdev->dev, "Couldn't get the mali bus clock\n"); ++ err = PTR_ERR(kbdev->bus_clk); ++ goto fail; ++ } ++ + kbdev->clock = of_clk_get(kbdev->dev->of_node, 0); + if (IS_ERR_OR_NULL(kbdev->clock)) { + err = PTR_ERR(kbdev->clock); +@@ -3236,6 +3250,8 @@ + dev_info(kbdev->dev, "Continuing without Mali clock control\n"); + /* Allow probe to continue without clock. */ + } else { ++ reset_control_deassert(kbdev->mali_rst); ++ clk_prepare_enable(kbdev->bus_clk); + err = clk_prepare_enable(kbdev->clock); + if (err) { + dev_err(kbdev->dev, +@@ -3268,6 +3284,16 @@ + kbdev->clock = NULL; + } + ++if (kbdev->bus_clk) { ++ clk_put(kbdev->bus_clk); ++ kbdev->bus_clk = NULL; ++} ++ ++if (kbdev->mali_rst) { ++ reset_control_put(kbdev->mali_rst); ++ kbdev->mali_rst = NULL; ++} ++ + #ifdef CONFIG_REGULATOR + if (NULL != kbdev->regulator) { + regulator_put(kbdev->regulator); +@@ -3293,6 +3319,18 @@ + kbdev->clock = NULL; + } + ++ if (kbdev->bus_clk) { ++ clk_disable_unprepare(kbdev->bus_clk); ++ clk_put(kbdev->bus_clk); ++ kbdev->bus_clk = NULL; ++ } ++ ++ if (kbdev->mali_rst) { ++ reset_control_assert(kbdev->mali_rst); ++ reset_control_put(kbdev->mali_rst); ++ kbdev->mali_rst = NULL; ++ } ++ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 12, 0)) && defined(CONFIG_OF) \ + && defined(CONFIG_REGULATOR) + if (kbdev->regulator) { +diff -Nur a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_defs.h b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_defs.h +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_defs.h 2018-03-06 18:05:25.000000000 +0100 ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_defs.h 2018-04-04 22:05:56.017916193 +0200 +@@ -68,6 +68,7 @@ + #endif /* CONFIG_MALI_DEVFREQ */ + + #include ++#include + #include + + #if defined(CONFIG_PM_RUNTIME) || \ +@@ -1434,6 +1435,8 @@ + } irqs[3]; + + struct clk *clock; ++ struct clk *bus_clk; ++ struct reset_control *mali_rst; + #ifdef CONFIG_REGULATOR + struct regulator *regulator; + #endif diff --git a/packages/linux-drivers/gpu-sunxi-midgard/patches/02-restore-old-api.patch b/packages/linux-drivers/gpu-sunxi-midgard/patches/02-restore-old-api.patch new file mode 100644 index 0000000000..5fee4fb948 --- /dev/null +++ b/packages/linux-drivers/gpu-sunxi-midgard/patches/02-restore-old-api.patch @@ -0,0 +1,1880 @@ +From 9614bc2e648a411a8d5b16ff637c24908d4d40d1 Mon Sep 17 00:00:00 2001 +From: Dominik Behr +Date: Wed, 07 Mar 2018 16:05:51 -0800 +Subject: [PATCH] CHROMIUM: mali: HACK: add backward compatibility for r12 userspace + +GPUCORE-14339: Make r22p0 backwards compatible + +This re-introduces the old UK 10.6 support (which includes support for +earlier 10.x versions). We had to back out the Kari support as it broke +pre-r18p0 clients due to a change in a prop query structure r18 +added support was not fixed. So pre-r18 clients expects a static +property query and thus can't handle adding new Kari properties. + +BUG=b:73501174 +TEST=build and run daisy, peach, minnie and kevin + +Change-Id: I89fd6521e367bebb223e1b04aa1077b348253d10 +Signed-off-by: Dominik Behr +Reviewed-on: https://chromium-review.googlesource.com/957586 +Reviewed-by: Stéphane Marchesin +--- + +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_base_hwconfig_features.h b/driver/product/kernel/drivers/gpu/arm/midgard/mali_base_hwconfig_features.h +index e0eebd8..a78fcef 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_base_hwconfig_features.h ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_base_hwconfig_features.h +@@ -58,7 +58,6 @@ + BASE_HW_FEATURE_PROTECTED_DEBUG_MODE, + BASE_HW_FEATURE_AARCH64_MMU, + BASE_HW_FEATURE_TLS_HASHING, +- BASE_HW_FEATURE_THREAD_GROUP_SPLIT, + BASE_HW_FEATURE_3BIT_EXT_RW_L2_MMU_CONFIG, + BASE_HW_FEATURE_END + }; +@@ -70,7 +69,6 @@ + static const enum base_hw_feature base_hw_features_t60x[] = { + BASE_HW_FEATURE_LD_ST_LEA_TEX, + BASE_HW_FEATURE_LINEAR_FILTER_FLOAT, +- BASE_HW_FEATURE_THREAD_GROUP_SPLIT, + BASE_HW_FEATURE_V4, + BASE_HW_FEATURE_END + }; +@@ -79,7 +77,6 @@ + BASE_HW_FEATURE_LD_ST_LEA_TEX, + BASE_HW_FEATURE_LINEAR_FILTER_FLOAT, + BASE_HW_FEATURE_ATTR_AUTO_TYPE_INFERRAL, +- BASE_HW_FEATURE_THREAD_GROUP_SPLIT, + BASE_HW_FEATURE_V4, + BASE_HW_FEATURE_END + }; +@@ -91,7 +88,6 @@ + BASE_HW_FEATURE_INTERPIPE_REG_ALIASING, + BASE_HW_FEATURE_OPTIMIZED_COVERAGE_MASK, + BASE_HW_FEATURE_T7XX_PAIRING_RULES, +- BASE_HW_FEATURE_THREAD_GROUP_SPLIT, + BASE_HW_FEATURE_WORKGROUP_ROUND_MULTIPLE_OF_4, + BASE_HW_FEATURE_WARPING, + BASE_HW_FEATURE_V4, +@@ -113,7 +109,6 @@ + BASE_HW_FEATURE_OUT_OF_ORDER_EXEC, + BASE_HW_FEATURE_T7XX_PAIRING_RULES, + BASE_HW_FEATURE_TEST4_DATUM_MODE, +- BASE_HW_FEATURE_THREAD_GROUP_SPLIT, + BASE_HW_FEATURE_END + }; + +@@ -134,7 +129,6 @@ + BASE_HW_FEATURE_OUT_OF_ORDER_EXEC, + BASE_HW_FEATURE_T7XX_PAIRING_RULES, + BASE_HW_FEATURE_TEST4_DATUM_MODE, +- BASE_HW_FEATURE_THREAD_GROUP_SPLIT, + BASE_HW_FEATURE_END + }; + +@@ -157,7 +151,6 @@ + BASE_HW_FEATURE_OUT_OF_ORDER_EXEC, + BASE_HW_FEATURE_T7XX_PAIRING_RULES, + BASE_HW_FEATURE_TEST4_DATUM_MODE, +- BASE_HW_FEATURE_THREAD_GROUP_SPLIT, + BASE_HW_FEATURE_END + }; + +@@ -180,7 +173,6 @@ + BASE_HW_FEATURE_OUT_OF_ORDER_EXEC, + BASE_HW_FEATURE_T7XX_PAIRING_RULES, + BASE_HW_FEATURE_TEST4_DATUM_MODE, +- BASE_HW_FEATURE_THREAD_GROUP_SPLIT, + BASE_HW_FEATURE_END + }; + +@@ -203,7 +195,6 @@ + BASE_HW_FEATURE_OUT_OF_ORDER_EXEC, + BASE_HW_FEATURE_T7XX_PAIRING_RULES, + BASE_HW_FEATURE_TEST4_DATUM_MODE, +- BASE_HW_FEATURE_THREAD_GROUP_SPLIT, + BASE_HW_FEATURE_FLUSH_REDUCTION, + BASE_HW_FEATURE_PROTECTED_MODE, + BASE_HW_FEATURE_COHERENCY_REG, +@@ -229,7 +220,6 @@ + BASE_HW_FEATURE_OUT_OF_ORDER_EXEC, + BASE_HW_FEATURE_T7XX_PAIRING_RULES, + BASE_HW_FEATURE_TEST4_DATUM_MODE, +- BASE_HW_FEATURE_THREAD_GROUP_SPLIT, + BASE_HW_FEATURE_FLUSH_REDUCTION, + BASE_HW_FEATURE_PROTECTED_MODE, + BASE_HW_FEATURE_PROTECTED_DEBUG_MODE, +@@ -257,7 +247,6 @@ + BASE_HW_FEATURE_OUT_OF_ORDER_EXEC, + BASE_HW_FEATURE_T7XX_PAIRING_RULES, + BASE_HW_FEATURE_TEST4_DATUM_MODE, +- BASE_HW_FEATURE_THREAD_GROUP_SPLIT, + BASE_HW_FEATURE_FLUSH_REDUCTION, + BASE_HW_FEATURE_PROTECTED_MODE, + BASE_HW_FEATURE_PROTECTED_DEBUG_MODE, +@@ -285,7 +274,6 @@ + BASE_HW_FEATURE_OUT_OF_ORDER_EXEC, + BASE_HW_FEATURE_T7XX_PAIRING_RULES, + BASE_HW_FEATURE_TEST4_DATUM_MODE, +- BASE_HW_FEATURE_THREAD_GROUP_SPLIT, + BASE_HW_FEATURE_FLUSH_REDUCTION, + BASE_HW_FEATURE_PROTECTED_MODE, + BASE_HW_FEATURE_PROTECTED_DEBUG_MODE, +@@ -312,7 +300,6 @@ + BASE_HW_FEATURE_OUT_OF_ORDER_EXEC, + BASE_HW_FEATURE_T7XX_PAIRING_RULES, + BASE_HW_FEATURE_TEST4_DATUM_MODE, +- BASE_HW_FEATURE_THREAD_GROUP_SPLIT, + BASE_HW_FEATURE_FLUSH_REDUCTION, + BASE_HW_FEATURE_PROTECTED_MODE, + BASE_HW_FEATURE_PROTECTED_DEBUG_MODE, +@@ -342,7 +329,6 @@ + BASE_HW_FEATURE_OUT_OF_ORDER_EXEC, + BASE_HW_FEATURE_T7XX_PAIRING_RULES, + BASE_HW_FEATURE_TEST4_DATUM_MODE, +- BASE_HW_FEATURE_THREAD_GROUP_SPLIT, + BASE_HW_FEATURE_FLUSH_REDUCTION, + BASE_HW_FEATURE_PROTECTED_MODE, + BASE_HW_FEATURE_PROTECTED_DEBUG_MODE, +@@ -453,7 +439,6 @@ + BASE_HW_FEATURE_OUT_OF_ORDER_EXEC, + BASE_HW_FEATURE_T7XX_PAIRING_RULES, + BASE_HW_FEATURE_TEST4_DATUM_MODE, +- BASE_HW_FEATURE_THREAD_GROUP_SPLIT, + BASE_HW_FEATURE_FLUSH_REDUCTION, + BASE_HW_FEATURE_PROTECTED_MODE, + BASE_HW_FEATURE_PROTECTED_DEBUG_MODE, +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_base_kernel.h b/driver/product/kernel/drivers/gpu/arm/midgard/mali_base_kernel.h +index e6b568f..2baeee14 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_base_kernel.h ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_base_kernel.h +@@ -29,6 +29,12 @@ + #ifndef _BASE_KERNEL_H_ + #define _BASE_KERNEL_H_ + ++/* Support UK10_2 IOCTLS */ ++#define BASE_LEGACY_UK10_2_SUPPORT 1 ++ ++/* Support UK10_4 IOCTLS */ ++#define BASE_LEGACY_UK10_4_SUPPORT 1 ++ + typedef struct base_mem_handle { + struct { + u64 handle; +@@ -51,7 +57,7 @@ + #define BASE_JD_SOFT_EVENT_SET ((unsigned char)1) + #define BASE_JD_SOFT_EVENT_RESET ((unsigned char)0) + +-#define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 4 ++#define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 3 + + #define BASE_MAX_COHERENT_GROUPS 16 + +@@ -1350,7 +1356,7 @@ + * @{ + */ + +-#define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 4 ++#define BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS 3 + + #define BASE_MAX_COHERENT_GROUPS 16 + +@@ -1382,10 +1388,23 @@ + + u16 padding; + +- /* The maximum GPU frequency. Reported to applications by +- * clGetDeviceInfo() ++ /** ++ * This property is deprecated since it has not contained the real current ++ * value of GPU clock speed. It is kept here only for backwards compatibility. ++ * For the new ioctl interface, it is ignored and is treated as a padding ++ * to keep the structure of the same size and retain the placement of its ++ * members. ++ */ ++ u32 gpu_speed_mhz; ++ ++ /** ++ * @usecase GPU clock max/min speed is required for computing best/worst case ++ * in tasks as job scheduling ant irq_throttling. (It is not specified in the ++ * Midgard Architecture). ++ * Also, GPU clock max speed is used for OpenCL's clGetDeviceInfo() function. + */ + u32 gpu_freq_khz_max; ++ u32 gpu_freq_khz_min; + + /** + * Size of the shader program counter, in bits. +@@ -1533,7 +1552,7 @@ + u32 js_present; + u32 js_features[GPU_MAX_JOB_SLOTS]; + u32 tiler_features; +- u32 texture_features[BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS]; ++ u32 texture_features[3]; + + u32 gpu_id; + +@@ -1700,6 +1719,20 @@ + base_jd_core_req fragment_core_req; + } base_jd_replay_payload; + ++#ifdef BASE_LEGACY_UK10_2_SUPPORT ++typedef struct base_jd_replay_payload_uk10_2 { ++ u64 tiler_jc_list; ++ u64 fragment_jc; ++ u64 tiler_heap_free; ++ u16 fragment_hierarchy_mask; ++ u16 tiler_hierarchy_mask; ++ u32 hierarchy_default_weight; ++ u16 tiler_core_req; ++ u16 fragment_core_req; ++ u8 padding[4]; ++} base_jd_replay_payload_uk10_2; ++#endif /* BASE_LEGACY_UK10_2_SUPPORT */ ++ + /** + * @brief An entry in the linked list of job chains to be replayed. This must + * be in GPU memory. +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase.h b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase.h +index 7174ef2..dd13893 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase.h ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase.h +@@ -48,6 +48,7 @@ + #include + + #include "mali_base_kernel.h" ++#include + #include + + /* +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_core_linux.c b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_core_linux.c +index 22c995a..69b4110 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_core_linux.c ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_core_linux.c +@@ -22,6 +22,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -97,6 +98,11 @@ + #define MMU_IRQ_TAG 1 + #define GPU_IRQ_TAG 2 + ++#if MALI_UNIT_TEST ++static struct kbase_exported_test_data shared_kernel_test_data; ++EXPORT_SYMBOL(shared_kernel_test_data); ++#endif /* MALI_UNIT_TEST */ ++ + static int kbase_dev_nr; + + static DEFINE_MUTEX(kbase_dev_list_lock); +@@ -108,6 +114,9 @@ + struct kbase_ioctl_version_check *version) + { + switch (version->major) { ++ case 10: /* we support 10.6 */ ++ version->minor = min_t(int, 6, (int)version->minor); ++ break; + case BASE_UK_VERSION_MAJOR: + /* set minor to be the lowest common */ + version->minor = min_t(int, BASE_UK_VERSION_MINOR, +@@ -178,6 +187,739 @@ + inited_ctx_sched = (1u << 22) + }; + ++/** ++ * kbase_legacy_dispatch - UKK dispatch function ++ * ++ * This is the dispatch function for the legacy UKK ioctl interface. No new ++ * ioctls should be added to this function, see kbase_ioctl instead. ++ * ++ * @kctx: The kernel context structure ++ * @args: Pointer to the data structure passed from/to user space ++ * @args_size: Size of the data structure ++ */ ++static int kbase_legacy_dispatch(struct kbase_context *kctx, ++ void * const args, u32 args_size) ++{ ++ struct kbase_device *kbdev; ++ union uk_header *ukh = args; ++ u32 id; ++ int ret = 0; ++ ++ KBASE_DEBUG_ASSERT(ukh != NULL); ++ ++ kbdev = kctx->kbdev; ++ id = ukh->id; ++ ukh->ret = MALI_ERROR_NONE; /* Be optimistic */ ++ ++#ifdef CONFIG_MALI_DEBUG ++ wait_event(kbdev->driver_inactive_wait, ++ kbdev->driver_inactive == false); ++#endif /* CONFIG_MALI_DEBUG */ ++ ++ if (UKP_FUNC_ID_CHECK_VERSION == id) { ++ struct uku_version_check_args *version_check; ++ struct kbase_ioctl_version_check version; ++ ++ if (args_size != sizeof(struct uku_version_check_args)) { ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ return 0; ++ } ++ version_check = (struct uku_version_check_args *)args; ++ version.minor = version_check->minor; ++ version.major = version_check->major; ++ ++ kbase_api_handshake(kctx, &version); ++ ++ version_check->minor = version.minor; ++ version_check->major = version.major; ++ ukh->ret = MALI_ERROR_NONE; ++ return 0; ++ } ++ ++ /* block calls until version handshake */ ++ if (kctx->api_version == 0) ++ return -EINVAL; ++ ++ if (!atomic_read(&kctx->setup_complete)) { ++ struct kbase_uk_set_flags *kbase_set_flags; ++ ++ /* setup pending, try to signal that we'll do the setup, ++ * if setup was already in progress, err this call ++ */ ++ if (atomic_cmpxchg(&kctx->setup_in_progress, 0, 1) != 0) ++ return -EINVAL; ++ ++ /* if unexpected call, will stay stuck in setup mode ++ * (is it the only call we accept?) ++ */ ++ if (id != KBASE_FUNC_SET_FLAGS) ++ return -EINVAL; ++ ++ kbase_set_flags = (struct kbase_uk_set_flags *)args; ++ ++ /* if not matching the expected call, stay in setup mode */ ++ if (sizeof(*kbase_set_flags) != args_size) ++ goto bad_size; ++ ++ /* if bad flags, will stay stuck in setup mode */ ++ if (kbase_context_set_create_flags(kctx, ++ kbase_set_flags->create_flags) != 0) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ ++ atomic_set(&kctx->setup_complete, 1); ++ return 0; ++ } ++ ++ /* setup complete, perform normal operation */ ++ switch (id) { ++ case KBASE_FUNC_MEM_JIT_INIT: ++ { ++ struct kbase_uk_mem_jit_init *jit_init = args; ++ ++ if (sizeof(*jit_init) != args_size) ++ goto bad_size; ++ ++ if (kbase_region_tracker_init_jit(kctx, ++ jit_init->va_pages)) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ break; ++ } ++ case KBASE_FUNC_MEM_ALLOC: ++ { ++ struct kbase_uk_mem_alloc *mem = args; ++ struct kbase_va_region *reg; ++ ++ if (sizeof(*mem) != args_size) ++ goto bad_size; ++ ++#if defined(CONFIG_64BIT) ++ if (!kbase_ctx_flag(kctx, KCTX_COMPAT)) { ++ /* force SAME_VA if a 64-bit client */ ++ mem->flags |= BASE_MEM_SAME_VA; ++ } ++#endif ++ ++ reg = kbase_mem_alloc(kctx, mem->va_pages, ++ mem->commit_pages, mem->extent, ++ &mem->flags, &mem->gpu_va); ++ mem->va_alignment = 0; ++ ++ if (!reg) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ break; ++ } ++ case KBASE_FUNC_MEM_IMPORT: { ++ struct kbase_uk_mem_import *mem_import = args; ++ void __user *phandle; ++ ++ if (sizeof(*mem_import) != args_size) ++ goto bad_size; ++#ifdef CONFIG_COMPAT ++ if (kbase_ctx_flag(kctx, KCTX_COMPAT)) ++ phandle = compat_ptr(mem_import->phandle); ++ else ++#endif ++ phandle = u64_to_user_ptr(mem_import->phandle); ++ ++ if (mem_import->type == BASE_MEM_IMPORT_TYPE_INVALID) { ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ break; ++ } ++ ++ if (kbase_mem_import(kctx, ++ (enum base_mem_import_type) ++ mem_import->type, ++ phandle, ++ 0, ++ &mem_import->gpu_va, ++ &mem_import->va_pages, ++ &mem_import->flags)) { ++ mem_import->type = BASE_MEM_IMPORT_TYPE_INVALID; ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ } ++ break; ++ } ++ case KBASE_FUNC_MEM_ALIAS: { ++ struct kbase_uk_mem_alias *alias = args; ++ struct base_mem_aliasing_info __user *user_ai; ++ struct base_mem_aliasing_info *ai; ++ ++ if (sizeof(*alias) != args_size) ++ goto bad_size; ++ ++ if (alias->nents > 2048) { ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ break; ++ } ++ if (!alias->nents) { ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ break; ++ } ++ ++#ifdef CONFIG_COMPAT ++ if (kbase_ctx_flag(kctx, KCTX_COMPAT)) ++ user_ai = compat_ptr(alias->ai); ++ else ++#endif ++ user_ai = u64_to_user_ptr(alias->ai); ++ ++ ai = vmalloc(sizeof(*ai) * alias->nents); ++ ++ if (!ai) { ++ ukh->ret = MALI_ERROR_OUT_OF_MEMORY; ++ break; ++ } ++ ++ if (copy_from_user(ai, user_ai, ++ sizeof(*ai) * alias->nents)) { ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ goto copy_failed; ++ } ++ ++ alias->gpu_va = kbase_mem_alias(kctx, &alias->flags, ++ alias->stride, ++ alias->nents, ai, ++ &alias->va_pages); ++ if (!alias->gpu_va) { ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ goto no_alias; ++ } ++no_alias: ++copy_failed: ++ vfree(ai); ++ break; ++ } ++ case KBASE_FUNC_MEM_COMMIT: ++ { ++ struct kbase_uk_mem_commit *commit = args; ++ int ret; ++ ++ if (sizeof(*commit) != args_size) ++ goto bad_size; ++ ++ ret = kbase_mem_commit(kctx, commit->gpu_addr, ++ commit->pages); ++ ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ commit->result_subcode = ++ BASE_BACKING_THRESHOLD_ERROR_INVALID_ARGUMENTS; ++ ++ if (ret == 0) { ++ ukh->ret = MALI_ERROR_NONE; ++ commit->result_subcode = ++ BASE_BACKING_THRESHOLD_OK; ++ } else if (ret == -ENOMEM) { ++ commit->result_subcode = ++ BASE_BACKING_THRESHOLD_ERROR_OOM; ++ } ++ ++ break; ++ } ++ ++ case KBASE_FUNC_MEM_QUERY: ++ { ++ struct kbase_uk_mem_query *query = args; ++ ++ if (sizeof(*query) != args_size) ++ goto bad_size; ++ ++ if (kbase_mem_query(kctx, query->gpu_addr, ++ query->query, &query->value) != 0) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ else ++ ukh->ret = MALI_ERROR_NONE; ++ break; ++ } ++ break; ++ ++ case KBASE_FUNC_MEM_FLAGS_CHANGE: ++ { ++ struct kbase_uk_mem_flags_change *fc = args; ++ ++ if (sizeof(*fc) != args_size) ++ goto bad_size; ++ ++ if (kbase_mem_flags_change(kctx, fc->gpu_va, ++ fc->flags, fc->mask) != 0) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ ++ break; ++ } ++ case KBASE_FUNC_MEM_FREE: ++ { ++ struct kbase_uk_mem_free *mem = args; ++ ++ if (sizeof(*mem) != args_size) ++ goto bad_size; ++ ++ if (kbase_mem_free(kctx, mem->gpu_addr) != 0) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ break; ++ } ++ ++ case KBASE_FUNC_JOB_SUBMIT: ++ { ++ struct kbase_uk_job_submit *job = args; ++ char __user *user_buf; ++ ++ if (sizeof(*job) != args_size) ++ goto bad_size; ++ ++#ifdef CONFIG_COMPAT ++ if (kbase_ctx_flag(kctx, KCTX_COMPAT)) ++ user_buf = compat_ptr(job->addr); ++ else ++#endif ++ user_buf = u64_to_user_ptr(job->addr); ++ ++ if (kbase_jd_submit(kctx, user_buf, ++ job->nr_atoms, ++ job->stride, ++ false) != 0) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ break; ++ } ++ ++ case KBASE_FUNC_SYNC: ++ { ++ struct kbase_uk_sync_now *sn = args; ++ ++ if (sizeof(*sn) != args_size) ++ goto bad_size; ++ ++ if (kbase_sync_now(kctx, &sn->sset.basep_sset) != 0) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ break; ++ } ++ ++ case KBASE_FUNC_DISJOINT_QUERY: ++ { ++ struct kbase_uk_disjoint_query *dquery = args; ++ ++ if (sizeof(*dquery) != args_size) ++ goto bad_size; ++ ++ /* Get the disjointness counter value. */ ++ dquery->counter = kbase_disjoint_event_get(kctx->kbdev); ++ break; ++ } ++ ++ case KBASE_FUNC_POST_TERM: ++ { ++ kbase_event_close(kctx); ++ break; ++ } ++ ++ case KBASE_FUNC_HWCNT_SETUP: ++ { ++ struct kbase_uk_hwcnt_setup *setup = args; ++ ++ if (sizeof(*setup) != args_size) ++ goto bad_size; ++ ++ mutex_lock(&kctx->vinstr_cli_lock); ++ if (kbase_vinstr_legacy_hwc_setup(kbdev->vinstr_ctx, ++ &kctx->vinstr_cli, setup) != 0) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ mutex_unlock(&kctx->vinstr_cli_lock); ++ break; ++ } ++ ++ case KBASE_FUNC_HWCNT_DUMP: ++ { ++ /* args ignored */ ++ mutex_lock(&kctx->vinstr_cli_lock); ++ if (kbase_vinstr_hwc_dump(kctx->vinstr_cli, ++ BASE_HWCNT_READER_EVENT_MANUAL) != 0) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ mutex_unlock(&kctx->vinstr_cli_lock); ++ break; ++ } ++ ++ case KBASE_FUNC_HWCNT_CLEAR: ++ { ++ /* args ignored */ ++ mutex_lock(&kctx->vinstr_cli_lock); ++ if (kbase_vinstr_hwc_clear(kctx->vinstr_cli) != 0) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ mutex_unlock(&kctx->vinstr_cli_lock); ++ break; ++ } ++ ++ case KBASE_FUNC_HWCNT_READER_SETUP: ++ { ++ struct kbase_uk_hwcnt_reader_setup *setup = args; ++ ++ if (sizeof(*setup) != args_size) ++ goto bad_size; ++ ++ mutex_lock(&kctx->vinstr_cli_lock); ++ if (kbase_vinstr_hwcnt_reader_setup(kbdev->vinstr_ctx, ++ setup) != 0) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ mutex_unlock(&kctx->vinstr_cli_lock); ++ break; ++ } ++ ++ case KBASE_FUNC_GPU_PROPS_REG_DUMP: ++ { ++ struct kbase_uk_gpuprops *setup = args; ++ ++ printk(KERN_ERR "%s sizeofs:\n", __func__); ++ printk(KERN_ERR "sizeof(kbase_uk_gpuprops) = %zd\n", sizeof(*setup)); ++ printk(KERN_ERR "sizeof(kbase_uk_gpuprops.header) = %zd\n", sizeof(setup->header)); ++ printk(KERN_ERR "sizeof(kbase_uk_gpuprops.props.core_props) = %zd\n", sizeof(setup->props.core_props)); ++ printk(KERN_ERR "sizeof(kbase_uk_gpuprops.props.l2_props) = %zd\n", sizeof(setup->props.l2_props)); ++ printk(KERN_ERR "sizeof(kbase_uk_gpuprops.props.tiler_props) = %zd\n", sizeof(setup->props.tiler_props)); ++ printk(KERN_ERR "sizeof(kbase_uk_gpuprops.props.thread_props) = %zd\n", sizeof(setup->props.thread_props)); ++ printk(KERN_ERR "sizeof(kbase_uk_gpuprops.props.raw_props) = %zd\n", sizeof(setup->props.raw_props)); ++ printk(KERN_ERR "sizeof(kbase_uk_gpuprops.props.coherency_info) = %zd\n", sizeof(setup->props.coherency_info)); ++ ++ ++ if (sizeof(*setup) != args_size) ++ goto bad_size; ++ ++ if (kbase_gpuprops_uk_get_props(kctx, setup) != 0) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ break; ++ } ++ case KBASE_FUNC_FIND_CPU_OFFSET: ++ { ++ struct kbase_uk_find_cpu_offset *find = args; ++ ++ if (sizeof(*find) != args_size) ++ goto bad_size; ++ ++ if (find->gpu_addr & ~PAGE_MASK) { ++ dev_warn(kbdev->dev, "kbase_legacy_dispatch case KBASE_FUNC_FIND_CPU_OFFSET: find->gpu_addr: passed parameter is invalid"); ++ goto out_bad; ++ } ++ ++ if (find->size > SIZE_MAX || find->cpu_addr > ULONG_MAX) { ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ } else { ++ int err; ++ ++ err = kbasep_find_enclosing_cpu_mapping_offset( ++ kctx, ++ find->cpu_addr, ++ find->size, ++ &find->offset); ++ ++ if (err) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ } ++ break; ++ } ++ case KBASE_FUNC_GET_VERSION: ++ { ++ struct kbase_uk_get_ddk_version *get_version = (struct kbase_uk_get_ddk_version *)args; ++ ++ if (sizeof(*get_version) != args_size) ++ goto bad_size; ++ ++ /* version buffer size check is made in compile time assert */ ++ memcpy(get_version->version_buffer, KERNEL_SIDE_DDK_VERSION_STRING, sizeof(KERNEL_SIDE_DDK_VERSION_STRING)); ++ get_version->version_string_size = sizeof(KERNEL_SIDE_DDK_VERSION_STRING); ++ break; ++ } ++ ++ case KBASE_FUNC_STREAM_CREATE: ++ { ++#if defined(CONFIG_SYNC) || defined(CONFIG_SYNC_FILE) ++ struct kbase_uk_stream_create *screate = (struct kbase_uk_stream_create *)args; ++ ++ if (sizeof(*screate) != args_size) ++ goto bad_size; ++ ++ if (strnlen(screate->name, sizeof(screate->name)) >= sizeof(screate->name)) { ++ /* not NULL terminated */ ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ break; ++ } ++ ++ if (kbase_sync_fence_stream_create(screate->name, ++ &screate->fd) != 0) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ else ++ ukh->ret = MALI_ERROR_NONE; ++#else /* CONFIG_SYNC || CONFIG_SYNC_FILE */ ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++#endif /* CONFIG_SYNC || CONFIG_SYNC_FILE */ ++ break; ++ } ++ case KBASE_FUNC_FENCE_VALIDATE: ++ { ++#if defined(CONFIG_SYNC) || defined(CONFIG_SYNC_FILE) ++ struct kbase_uk_fence_validate *fence_validate = (struct kbase_uk_fence_validate *)args; ++ ++ if (sizeof(*fence_validate) != args_size) ++ goto bad_size; ++ ++ if (kbase_sync_fence_validate(fence_validate->fd) != 0) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ else ++ ukh->ret = MALI_ERROR_NONE; ++#endif /* CONFIG_SYNC || CONFIG_SYNC_FILE */ ++ break; ++ } ++ ++ case KBASE_FUNC_SET_TEST_DATA: ++ { ++#if MALI_UNIT_TEST ++ struct kbase_uk_set_test_data *set_data = args; ++ ++ shared_kernel_test_data = set_data->test_data; ++ shared_kernel_test_data.kctx = (uintptr_t)kctx; ++ shared_kernel_test_data.mm = (uintptr_t)current->mm; ++ ukh->ret = MALI_ERROR_NONE; ++#endif /* MALI_UNIT_TEST */ ++ break; ++ } ++ ++ case KBASE_FUNC_INJECT_ERROR: ++ { ++#ifdef CONFIG_MALI_ERROR_INJECT ++ unsigned long flags; ++ struct kbase_error_params params = ((struct kbase_uk_error_params *)args)->params; ++ ++ /*mutex lock */ ++ spin_lock_irqsave(&kbdev->reg_op_lock, flags); ++ if (job_atom_inject_error(¶ms) != 0) ++ ukh->ret = MALI_ERROR_OUT_OF_MEMORY; ++ else ++ ukh->ret = MALI_ERROR_NONE; ++ spin_unlock_irqrestore(&kbdev->reg_op_lock, flags); ++ /*mutex unlock */ ++#endif /* CONFIG_MALI_ERROR_INJECT */ ++ break; ++ } ++ ++ case KBASE_FUNC_MODEL_CONTROL: ++ { ++#ifdef CONFIG_MALI_NO_MALI ++ unsigned long flags; ++ struct kbase_model_control_params params = ++ ((struct kbase_uk_model_control_params *)args)->params; ++ ++ /*mutex lock */ ++ spin_lock_irqsave(&kbdev->reg_op_lock, flags); ++ if (gpu_model_control(kbdev->model, ¶ms) != 0) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ else ++ ukh->ret = MALI_ERROR_NONE; ++ spin_unlock_irqrestore(&kbdev->reg_op_lock, flags); ++ /*mutex unlock */ ++#endif /* CONFIG_MALI_NO_MALI */ ++ break; ++ } ++ ++ case KBASE_FUNC_GET_PROFILING_CONTROLS: ++ { ++ struct kbase_uk_profiling_controls *controls = ++ (struct kbase_uk_profiling_controls *)args; ++ u32 i; ++ ++ if (sizeof(*controls) != args_size) ++ goto bad_size; ++ ++ for (i = FBDUMP_CONTROL_MIN; i < FBDUMP_CONTROL_MAX; i++) ++ controls->profiling_controls[i] = ++ kbdev->kbase_profiling_controls[i]; ++ ++ break; ++ } ++ ++ /* used only for testing purposes; these controls are to be set by gator through gator API */ ++ case KBASE_FUNC_SET_PROFILING_CONTROLS: ++ { ++ struct kbase_uk_profiling_controls *controls = ++ (struct kbase_uk_profiling_controls *)args; ++ u32 i; ++ ++ if (sizeof(*controls) != args_size) ++ goto bad_size; ++ ++ for (i = FBDUMP_CONTROL_MIN; i < FBDUMP_CONTROL_MAX; i++) ++ _mali_profiling_control(i, controls->profiling_controls[i]); ++ ++ break; ++ } ++ ++ case KBASE_FUNC_DEBUGFS_MEM_PROFILE_ADD: ++ { ++ struct kbase_uk_debugfs_mem_profile_add *add_data = ++ (struct kbase_uk_debugfs_mem_profile_add *)args; ++ char *buf; ++ char __user *user_buf; ++ ++ if (sizeof(*add_data) != args_size) ++ goto bad_size; ++ ++ if (add_data->len > KBASE_MEM_PROFILE_MAX_BUF_SIZE) { ++ dev_err(kbdev->dev, "buffer too big\n"); ++ goto out_bad; ++ } ++ ++#ifdef CONFIG_COMPAT ++ if (kbase_ctx_flag(kctx, KCTX_COMPAT)) ++ user_buf = compat_ptr(add_data->buf); ++ else ++#endif ++ user_buf = u64_to_user_ptr(add_data->buf); ++ ++ buf = kmalloc(add_data->len, GFP_KERNEL); ++ if (ZERO_OR_NULL_PTR(buf)) ++ goto out_bad; ++ ++ if (0 != copy_from_user(buf, user_buf, add_data->len)) { ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ kfree(buf); ++ goto out_bad; ++ } ++ ++ if (kbasep_mem_profile_debugfs_insert(kctx, buf, ++ add_data->len)) { ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ goto out_bad; ++ } ++ ++ break; ++ } ++ ++#ifdef CONFIG_MALI_NO_MALI ++ case KBASE_FUNC_SET_PRFCNT_VALUES: ++ { ++ ++ struct kbase_uk_prfcnt_values *params = ++ ((struct kbase_uk_prfcnt_values *)args); ++ gpu_model_set_dummy_prfcnt_sample(params->data, ++ params->size); ++ ++ break; ++ } ++#endif /* CONFIG_MALI_NO_MALI */ ++#ifdef BASE_LEGACY_UK10_4_SUPPORT ++ case KBASE_FUNC_TLSTREAM_ACQUIRE_V10_4: ++ { ++ struct kbase_uk_tlstream_acquire_v10_4 *tlstream_acquire ++ = args; ++ int ret; ++ ++ if (sizeof(*tlstream_acquire) != args_size) ++ goto bad_size; ++ ++ ret = kbase_tlstream_acquire( ++ kctx, 0); ++ if (ret < 0) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ else ++ tlstream_acquire->fd = ret; ++ break; ++ } ++#endif /* BASE_LEGACY_UK10_4_SUPPORT */ ++ case KBASE_FUNC_TLSTREAM_ACQUIRE: ++ { ++ struct kbase_uk_tlstream_acquire *tlstream_acquire = ++ args; ++ int ret; ++ ++ if (sizeof(*tlstream_acquire) != args_size) ++ goto bad_size; ++ ++ if (tlstream_acquire->flags & ~BASE_TLSTREAM_FLAGS_MASK) ++ goto out_bad; ++ ++ ret = kbase_tlstream_acquire( ++ kctx, tlstream_acquire->flags); ++ if (ret < 0) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ else ++ tlstream_acquire->fd = ret; ++ break; ++ } ++ case KBASE_FUNC_TLSTREAM_FLUSH: ++ { ++ struct kbase_uk_tlstream_flush *tlstream_flush = ++ args; ++ ++ if (sizeof(*tlstream_flush) != args_size) ++ goto bad_size; ++ ++ kbase_tlstream_flush_streams(); ++ break; ++ } ++#if MALI_UNIT_TEST ++ case KBASE_FUNC_TLSTREAM_TEST: ++ { ++ struct kbase_uk_tlstream_test *tlstream_test = args; ++ ++ if (sizeof(*tlstream_test) != args_size) ++ goto bad_size; ++ ++ kbase_tlstream_test( ++ tlstream_test->tpw_count, ++ tlstream_test->msg_delay, ++ tlstream_test->msg_count, ++ tlstream_test->aux_msg); ++ break; ++ } ++ case KBASE_FUNC_TLSTREAM_STATS: ++ { ++ struct kbase_uk_tlstream_stats *tlstream_stats = args; ++ ++ if (sizeof(*tlstream_stats) != args_size) ++ goto bad_size; ++ ++ kbase_tlstream_stats( ++ &tlstream_stats->bytes_collected, ++ &tlstream_stats->bytes_generated); ++ break; ++ } ++#endif /* MALI_UNIT_TEST */ ++ ++ case KBASE_FUNC_GET_CONTEXT_ID: ++ { ++ struct kbase_uk_context_id *info = args; ++ ++ info->id = kctx->id; ++ break; ++ } ++ ++ case KBASE_FUNC_SOFT_EVENT_UPDATE: ++ { ++ struct kbase_uk_soft_event_update *update = args; ++ ++ if (sizeof(*update) != args_size) ++ goto bad_size; ++ ++ if (((update->new_status != BASE_JD_SOFT_EVENT_SET) && ++ (update->new_status != BASE_JD_SOFT_EVENT_RESET)) || ++ (update->flags != 0)) ++ goto out_bad; ++ ++ if (kbase_soft_event_update(kctx, update->evt, ++ update->new_status)) ++ ukh->ret = MALI_ERROR_FUNCTION_FAILED; ++ ++ break; ++ } ++ ++ default: ++ dev_err(kbdev->dev, "unknown ioctl %u\n", id); ++ goto out_bad; ++ } ++ ++ return ret; ++ ++ bad_size: ++ dev_err(kbdev->dev, "Wrong syscall size (%d) for %08x\n", args_size, id); ++ out_bad: ++ return -EINVAL; ++} ++ ++ ++ + static struct kbase_device *to_kbase_device(struct device *dev) + { + return dev_get_drvdata(dev); +@@ -508,6 +1250,33 @@ + return 0; + } + ++#define CALL_MAX_SIZE 536 ++ ++static long kbase_legacy_ioctl(struct file *filp, unsigned int cmd, ++ unsigned long arg) ++{ ++ u64 msg[(CALL_MAX_SIZE + 7) >> 3] = { 0xdeadbeefdeadbeefull }; /* alignment fixup */ ++ u32 size = _IOC_SIZE(cmd); ++ struct kbase_context *kctx = filp->private_data; ++ ++ if (size > CALL_MAX_SIZE) ++ return -ENOTTY; ++ ++ if (0 != copy_from_user(&msg, (void __user *)arg, size)) { ++ dev_err(kctx->kbdev->dev, "failed to copy ioctl argument into kernel space\n"); ++ return -EFAULT; ++ } ++ ++ if (kbase_legacy_dispatch(kctx, &msg, size) != 0) ++ return -EFAULT; ++ ++ if (0 != copy_to_user((void __user *)arg, &msg, size)) { ++ dev_err(kctx->kbdev->dev, "failed to copy results of UK call back to user space\n"); ++ return -EFAULT; ++ } ++ return 0; ++} ++ + static int kbase_api_set_flags(struct kbase_context *kctx, + struct kbase_ioctl_set_flags *flags) + { +@@ -1067,6 +1836,20 @@ + struct kbase_device *kbdev = kctx->kbdev; + void __user *uarg = (void __user *)arg; + ++ /* The UK ioctl values overflow the cmd field causing the type to be ++ * incremented ++ */ ++ if (_IOC_TYPE(cmd) == LINUX_UK_BASE_MAGIC+2) ++ return kbase_legacy_ioctl(filp, cmd, arg); ++ ++ /* The UK version check IOCTL doesn't overflow the cmd field, so is ++ * handled separately here ++ */ ++ if (cmd == _IOC(_IOC_READ|_IOC_WRITE, LINUX_UK_BASE_MAGIC, ++ UKP_FUNC_ID_CHECK_VERSION, ++ sizeof(struct uku_version_check_args))) ++ return kbase_legacy_ioctl(filp, cmd, arg); ++ + /* Only these ioctls are available until setup is complete */ + switch (cmd) { + KBASE_HANDLE_IOCTL_INOUT(KBASE_IOCTL_VERSION_CHECK, +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_gpuprops.c b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_gpuprops.c +index 9a9ce2d9..091d10f 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_gpuprops.c ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_gpuprops.c +@@ -47,6 +47,55 @@ + #define KBASE_UBFX32(value, offset, size) \ + (((u32)(value) >> (u32)(offset)) & (u32)((1ULL << (u32)(size)) - 1)) + ++int kbase_gpuprops_uk_get_props(struct kbase_context *kctx, struct kbase_uk_gpuprops * const kbase_props) ++{ ++ typedef int (*kbase_gpu_clk_speed_func)(u32*); ++ kbase_gpu_clk_speed_func get_gpu_speed_mhz; ++ u32 gpu_speed_mhz; ++ int rc = 1; ++ ++ KBASE_DEBUG_ASSERT(NULL != kctx); ++ KBASE_DEBUG_ASSERT(NULL != kbase_props); ++ ++ /* Current GPU speed is requested from the system integrator via the GPU_SPEED_FUNC function. ++ * If that function fails, or the function is not provided by the system integrator, we report the maximum ++ * GPU speed as specified by GPU_FREQ_KHZ_MAX. ++ */ ++ get_gpu_speed_mhz = (kbase_gpu_clk_speed_func) NULL; ++ if (get_gpu_speed_mhz != NULL) { ++ rc = get_gpu_speed_mhz(&gpu_speed_mhz); ++#ifdef CONFIG_MALI_DEBUG ++ /* Issue a warning message when the reported GPU speed falls outside the min/max range */ ++ if (rc == 0) { ++ u32 gpu_speed_khz = gpu_speed_mhz * 1000; ++ ++ if (gpu_speed_khz < kctx->kbdev->gpu_props.props.core_props.gpu_freq_khz_min || ++ gpu_speed_khz > kctx->kbdev->gpu_props.props.core_props.gpu_freq_khz_max) ++ dev_warn(kctx->kbdev->dev, "GPU Speed is outside of min/max range (got %lu Khz, min %lu Khz, max %lu Khz)\n", ++ (unsigned long)gpu_speed_khz, ++ (unsigned long)kctx->kbdev->gpu_props.props.core_props.gpu_freq_khz_min, ++ (unsigned long)kctx->kbdev->gpu_props.props.core_props.gpu_freq_khz_max); ++ } ++#endif /* CONFIG_MALI_DEBUG */ ++ } ++ if (kctx->kbdev->clock) { ++ gpu_speed_mhz = clk_get_rate(kctx->kbdev->clock) / 1000000; ++ rc = 0; ++ } ++ if (rc != 0) ++ gpu_speed_mhz = kctx->kbdev->gpu_props.props.core_props.gpu_freq_khz_max / 1000; ++ ++ kctx->kbdev->gpu_props.props.core_props.gpu_speed_mhz = gpu_speed_mhz; ++ ++ memcpy(&kbase_props->props, &kctx->kbdev->gpu_props.props, sizeof(kbase_props->props)); ++ ++ /* Before API 8.2 they expect L3 cache info here, which was always 0 */ ++ if (kctx->api_version < KBASE_API_VERSION(8, 2)) ++ kbase_props->props.raw_props.suspend_size = 0; ++ ++ return 0; ++} ++ + static void kbase_gpuprops_construct_coherent_groups(base_gpu_props * const props) + { + struct mali_base_gpu_coherent_group *current_group; +@@ -288,9 +337,6 @@ + */ + gpu_props->raw_props.coherency_mode = regdump.coherency_features | + COHERENCY_FEATURE_BIT(COHERENCY_NONE); +- +- if (!kbase_hw_has_feature(kbdev, BASE_HW_FEATURE_THREAD_GROUP_SPLIT)) +- gpu_props->thread_props.max_thread_group_split = 0; + } + + static struct { +@@ -310,7 +356,6 @@ + PROP(TEXTURE_FEATURES_0, core_props.texture_features[0]), + PROP(TEXTURE_FEATURES_1, core_props.texture_features[1]), + PROP(TEXTURE_FEATURES_2, core_props.texture_features[2]), +- PROP(TEXTURE_FEATURES_3, core_props.texture_features[3]), + PROP(GPU_AVAILABLE_MEMORY_SIZE, core_props.gpu_available_memory_size), + + PROP(L2_LOG2_LINE_SIZE, l2_props.log2_line_size), +@@ -358,7 +403,6 @@ + PROP(RAW_TEXTURE_FEATURES_0, raw_props.texture_features[0]), + PROP(RAW_TEXTURE_FEATURES_1, raw_props.texture_features[1]), + PROP(RAW_TEXTURE_FEATURES_2, raw_props.texture_features[2]), +- PROP(RAW_TEXTURE_FEATURES_3, raw_props.texture_features[3]), + PROP(RAW_GPU_ID, raw_props.gpu_id), + PROP(RAW_THREAD_MAX_THREADS, raw_props.thread_max_threads), + PROP(RAW_THREAD_MAX_WORKGROUP_SIZE, +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_gpuprops.h b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_gpuprops.h +index 37d9c08..4c0c748 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_gpuprops.h ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_gpuprops.h +@@ -55,6 +55,18 @@ + void kbase_gpuprops_set_features(struct kbase_device *kbdev); + + /** ++ * @brief Provide GPU properties to userside through UKU call. ++ * ++ * Fill the struct kbase_uk_gpuprops with values from GPU configuration registers. ++ * ++ * @param kctx The struct kbase_context structure ++ * @param kbase_props A copy of the struct kbase_uk_gpuprops structure from userspace ++ * ++ * @return 0 on success. Any other value indicates failure. ++ */ ++int kbase_gpuprops_uk_get_props(struct kbase_context *kctx, struct kbase_uk_gpuprops * const kbase_props); ++ ++/** + * kbase_gpuprops_populate_user_buffer - Populate the GPU properties buffer + * @kbdev: The kbase device + * +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_ioctl.h b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_ioctl.h +index a8fe9cd..df125f0 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_ioctl.h ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_ioctl.h +@@ -32,6 +32,27 @@ + #define KBASE_IOCTL_TYPE 0x80 + + /* ++ * 10.1: ++ * - Do mmap in kernel for SAME_VA memory allocations rather then ++ * calling back into the kernel as a 2nd stage of the allocation request. ++ * ++ * 10.2: ++ * - Add KBASE_FUNC_MEM_JIT_INIT which allows clients to request a custom VA ++ * region for use with JIT (ignored on 32-bit platforms) ++ * ++ * 10.3: ++ * - base_jd_core_req typedef-ed to u32 (instead of to u16) ++ * - two flags added: BASE_JD_REQ_SKIP_CACHE_STAT / _END ++ * ++ * 10.4: ++ * - Removed KBASE_FUNC_EXT_BUFFER_LOCK used only in internal tests ++ * ++ * 10.5: ++ * - Reverted to performing mmap in user space so that tools like valgrind work. ++ * ++ * 10.6: ++ * - Add flags input variable to KBASE_FUNC_TLSTREAM_ACQUIRE ++ * + * 11.1: + * - Add BASE_MEM_TILER_ALIGN_TOP under base_mem_alloc_flags + * 11.2: +@@ -267,7 +288,6 @@ + * struct kbase_ioctl_get_ddk_version - Query the kernel version + * @version_buffer: Buffer to receive the kernel version string + * @size: Size of the buffer +- * @padding: Padding + * + * The ioctl will return the number of bytes written into version_buffer + * (which includes a NULL byte) or a negative error code +@@ -275,7 +295,6 @@ + struct kbase_ioctl_get_ddk_version { + __u64 version_buffer; + __u32 size; +- __u32 padding; + }; + + #define KBASE_IOCTL_GET_DDK_VERSION \ +@@ -495,12 +514,10 @@ + * struct kbase_ioctl_get_profiling_controls - Get the profiling controls + * @count: The size of @buffer in u32 words + * @buffer: The buffer to receive the profiling controls +- * @padding: Padding + */ + struct kbase_ioctl_get_profiling_controls { + __u64 buffer; + __u32 count; +- __u32 padding; + }; + + #define KBASE_IOCTL_GET_PROFILING_CONTROLS \ +@@ -775,9 +792,6 @@ + #define KBASE_GPUPROP_COHERENCY_GROUP_14 78 + #define KBASE_GPUPROP_COHERENCY_GROUP_15 79 + +-#define KBASE_GPUPROP_TEXTURE_FEATURES_3 80 +-#define KBASE_GPUPROP_RAW_TEXTURE_FEATURES_3 81 +- + #ifdef __cpluscplus + } + #endif +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_jd.c b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_jd.c +index 70277ad..11b035d 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_jd.c ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_jd.c +@@ -29,6 +29,7 @@ + #include + #endif + #include ++#include + #include + #include + #include +@@ -1142,6 +1143,12 @@ + break; + } + ++#ifdef BASE_LEGACY_UK10_2_SUPPORT ++ if (KBASE_API_VERSION(10, 3) > kctx->api_version) ++ user_atom.core_req = (u32)(user_atom.compat_core_req ++ & 0x7fff); ++#endif /* BASE_LEGACY_UK10_2_SUPPORT */ ++ + user_addr = (void __user *)((uintptr_t) user_addr + stride); + + mutex_lock(&jctx->lock); +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_mem_linux.c b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_mem_linux.c +index 4e6668e..75f39ef 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_mem_linux.c ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_mem_linux.c +@@ -49,7 +49,6 @@ + #include + #include + #include +-#include + + static int kbase_tracking_page_setup(struct kbase_context *kctx, struct vm_area_struct *vma); + +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_replay.c b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_replay.c +index 3d93922..3ba9344 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_replay.c ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_replay.c +@@ -777,6 +777,22 @@ + return -EINVAL; + } + ++#ifdef BASE_LEGACY_UK10_2_SUPPORT ++ if (KBASE_API_VERSION(10, 3) > replay_atom->kctx->api_version) { ++ base_jd_replay_payload_uk10_2 *payload_uk10_2; ++ u16 tiler_core_req; ++ u16 fragment_core_req; ++ ++ payload_uk10_2 = (base_jd_replay_payload_uk10_2 *) payload; ++ memcpy(&tiler_core_req, &payload_uk10_2->tiler_core_req, ++ sizeof(tiler_core_req)); ++ memcpy(&fragment_core_req, &payload_uk10_2->fragment_core_req, ++ sizeof(fragment_core_req)); ++ payload->tiler_core_req = (u32)(tiler_core_req & 0x7fff); ++ payload->fragment_core_req = (u32)(fragment_core_req & 0x7fff); ++ } ++#endif /* BASE_LEGACY_UK10_2_SUPPORT */ ++ + #ifdef CONFIG_MALI_DEBUG + dev_dbg(kctx->kbdev->dev, "kbasep_replay_parse_payload: payload=%p\n", payload); + dev_dbg(kctx->kbdev->dev, "Payload structure:\n" +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_uku.h b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_uku.h +new file mode 100644 +index 0000000..2363ef9 +--- /dev/null ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_uku.h +@@ -0,0 +1,506 @@ ++/* ++ * ++ * (C) COPYRIGHT 2008-2017 ARM Limited. All rights reserved. ++ * ++ * This program is free software and is provided to you under the terms of the ++ * GNU General Public License version 2 as published by the Free Software ++ * Foundation, and any use by you of this program is subject to the terms ++ * of such GNU licence. ++ * ++ * A copy of the licence is included with the program, and can also be obtained ++ * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ++ * Boston, MA 02110-1301, USA. ++ * ++ */ ++ ++ ++ ++#ifndef _KBASE_UKU_H_ ++#define _KBASE_UKU_H_ ++ ++#include "mali_uk.h" ++#include "mali_base_kernel.h" ++ ++/* This file needs to support being included from kernel and userside (which use different defines) */ ++#if defined(CONFIG_MALI_ERROR_INJECT) || MALI_ERROR_INJECT_ON ++#define SUPPORT_MALI_ERROR_INJECT ++#endif /* defined(CONFIG_MALI_ERROR_INJECT) || MALI_ERROR_INJECT_ON */ ++#if defined(CONFIG_MALI_NO_MALI) ++#define SUPPORT_MALI_NO_MALI ++#elif defined(MALI_NO_MALI) ++#if MALI_NO_MALI ++#define SUPPORT_MALI_NO_MALI ++#endif ++#endif ++ ++#if defined(SUPPORT_MALI_NO_MALI) || defined(SUPPORT_MALI_ERROR_INJECT) ++#include "backend/gpu/mali_kbase_model_dummy.h" ++#endif ++ ++#include "mali_kbase_gpuprops_types.h" ++ ++ ++#define LINUX_UK_BASE_MAGIC 0x80 ++ ++struct kbase_uk_mem_alloc { ++ union uk_header header; ++ /* IN */ ++ u64 va_pages; ++ u64 commit_pages; ++ u64 extent; ++ /* IN/OUT */ ++ u64 flags; ++ /* OUT */ ++ u64 gpu_va; ++ u16 va_alignment; ++ u8 padding[6]; ++}; ++ ++struct kbase_uk_mem_free { ++ union uk_header header; ++ /* IN */ ++ u64 gpu_addr; ++ /* OUT */ ++}; ++ ++struct kbase_uk_mem_alias { ++ union uk_header header; ++ /* IN/OUT */ ++ u64 flags; ++ /* IN */ ++ u64 stride; ++ u64 nents; ++ u64 ai; ++ /* OUT */ ++ u64 gpu_va; ++ u64 va_pages; ++}; ++ ++struct kbase_uk_mem_import { ++ union uk_header header; ++ /* IN */ ++ u64 phandle; ++ u32 type; ++ u32 padding; ++ /* IN/OUT */ ++ u64 flags; ++ /* OUT */ ++ u64 gpu_va; ++ u64 va_pages; ++}; ++ ++struct kbase_uk_mem_flags_change { ++ union uk_header header; ++ /* IN */ ++ u64 gpu_va; ++ u64 flags; ++ u64 mask; ++}; ++ ++struct kbase_uk_job_submit { ++ union uk_header header; ++ /* IN */ ++ u64 addr; ++ u32 nr_atoms; ++ u32 stride; /* bytes between atoms, i.e. sizeof(base_jd_atom_v2) */ ++ /* OUT */ ++}; ++ ++struct kbase_uk_post_term { ++ union uk_header header; ++}; ++ ++struct kbase_uk_sync_now { ++ union uk_header header; ++ ++ /* IN */ ++ struct base_syncset sset; ++ ++ /* OUT */ ++}; ++ ++struct kbase_uk_hwcnt_setup { ++ union uk_header header; ++ ++ /* IN */ ++ u64 dump_buffer; ++ u32 jm_bm; ++ u32 shader_bm; ++ u32 tiler_bm; ++ u32 unused_1; /* keep for backwards compatibility */ ++ u32 mmu_l2_bm; ++ u32 padding; ++ /* OUT */ ++}; ++ ++/** ++ * struct kbase_uk_hwcnt_reader_setup - User/Kernel space data exchange structure ++ * @header: UK structure header ++ * @buffer_count: requested number of dumping buffers ++ * @jm_bm: counters selection bitmask (JM) ++ * @shader_bm: counters selection bitmask (Shader) ++ * @tiler_bm: counters selection bitmask (Tiler) ++ * @mmu_l2_bm: counters selection bitmask (MMU_L2) ++ * @fd: dumping notification file descriptor ++ * ++ * This structure sets up HWC dumper/reader for this context. ++ * Multiple instances can be created for single context. ++ */ ++struct kbase_uk_hwcnt_reader_setup { ++ union uk_header header; ++ ++ /* IN */ ++ u32 buffer_count; ++ u32 jm_bm; ++ u32 shader_bm; ++ u32 tiler_bm; ++ u32 mmu_l2_bm; ++ ++ /* OUT */ ++ s32 fd; ++}; ++ ++struct kbase_uk_hwcnt_dump { ++ union uk_header header; ++}; ++ ++struct kbase_uk_hwcnt_clear { ++ union uk_header header; ++}; ++ ++struct kbase_uk_fence_validate { ++ union uk_header header; ++ /* IN */ ++ s32 fd; ++ u32 padding; ++ /* OUT */ ++}; ++ ++struct kbase_uk_stream_create { ++ union uk_header header; ++ /* IN */ ++ char name[32]; ++ /* OUT */ ++ s32 fd; ++ u32 padding; ++}; ++ ++struct kbase_uk_gpuprops { ++ union uk_header header; ++ ++ /* IN */ ++ struct base_gpu_props props; ++ /* OUT */ ++}; ++ ++struct kbase_uk_mem_query { ++ union uk_header header; ++ /* IN */ ++ u64 gpu_addr; ++#define KBASE_MEM_QUERY_COMMIT_SIZE 1 ++#define KBASE_MEM_QUERY_VA_SIZE 2 ++#define KBASE_MEM_QUERY_FLAGS 3 ++ u64 query; ++ /* OUT */ ++ u64 value; ++}; ++ ++struct kbase_uk_mem_commit { ++ union uk_header header; ++ /* IN */ ++ u64 gpu_addr; ++ u64 pages; ++ /* OUT */ ++ u32 result_subcode; ++ u32 padding; ++}; ++ ++struct kbase_uk_find_cpu_offset { ++ union uk_header header; ++ /* IN */ ++ u64 gpu_addr; ++ u64 cpu_addr; ++ u64 size; ++ /* OUT */ ++ u64 offset; ++}; ++ ++#define KBASE_GET_VERSION_BUFFER_SIZE 64 ++struct kbase_uk_get_ddk_version { ++ union uk_header header; ++ /* OUT */ ++ char version_buffer[KBASE_GET_VERSION_BUFFER_SIZE]; ++ u32 version_string_size; ++ u32 padding; ++}; ++ ++struct kbase_uk_disjoint_query { ++ union uk_header header; ++ /* OUT */ ++ u32 counter; ++ u32 padding; ++}; ++ ++struct kbase_uk_set_flags { ++ union uk_header header; ++ /* IN */ ++ u32 create_flags; ++ u32 padding; ++}; ++ ++#if MALI_UNIT_TEST ++#define TEST_ADDR_COUNT 4 ++#define KBASE_TEST_BUFFER_SIZE 128 ++struct kbase_exported_test_data { ++ u64 test_addr[TEST_ADDR_COUNT]; /**< memory address */ ++ u32 test_addr_pages[TEST_ADDR_COUNT]; /**< memory size in pages */ ++ u64 kctx; /**< base context created by process */ ++ u64 mm; /**< pointer to process address space */ ++ u8 buffer1[KBASE_TEST_BUFFER_SIZE]; /**< unit test defined parameter */ ++ u8 buffer2[KBASE_TEST_BUFFER_SIZE]; /**< unit test defined parameter */ ++}; ++ ++struct kbase_uk_set_test_data { ++ union uk_header header; ++ /* IN */ ++ struct kbase_exported_test_data test_data; ++}; ++ ++#endif /* MALI_UNIT_TEST */ ++ ++#ifdef SUPPORT_MALI_ERROR_INJECT ++struct kbase_uk_error_params { ++ union uk_header header; ++ /* IN */ ++ struct kbase_error_params params; ++}; ++#endif /* SUPPORT_MALI_ERROR_INJECT */ ++ ++#ifdef SUPPORT_MALI_NO_MALI ++struct kbase_uk_model_control_params { ++ union uk_header header; ++ /* IN */ ++ struct kbase_model_control_params params; ++}; ++#endif /* SUPPORT_MALI_NO_MALI */ ++ ++struct kbase_uk_profiling_controls { ++ union uk_header header; ++ u32 profiling_controls[FBDUMP_CONTROL_MAX]; ++}; ++ ++struct kbase_uk_debugfs_mem_profile_add { ++ union uk_header header; ++ u32 len; ++ u32 padding; ++ u64 buf; ++}; ++ ++struct kbase_uk_context_id { ++ union uk_header header; ++ /* OUT */ ++ int id; ++}; ++ ++/** ++ * struct kbase_uk_tlstream_acquire - User/Kernel space data exchange structure ++ * @header: UK structure header ++ * @flags: timeline stream flags ++ * @fd: timeline stream file descriptor ++ * ++ * This structure is used when performing a call to acquire kernel side timeline ++ * stream file descriptor. ++ */ ++struct kbase_uk_tlstream_acquire { ++ union uk_header header; ++ /* IN */ ++ u32 flags; ++ /* OUT */ ++ s32 fd; ++}; ++ ++/** ++ * struct kbase_uk_tlstream_acquire_v10_4 - User/Kernel space data exchange ++ * structure ++ * @header: UK structure header ++ * @fd: timeline stream file descriptor ++ * ++ * This structure is used when performing a call to acquire kernel side timeline ++ * stream file descriptor. ++ */ ++struct kbase_uk_tlstream_acquire_v10_4 { ++ union uk_header header; ++ /* IN */ ++ /* OUT */ ++ s32 fd; ++}; ++ ++/** ++ * struct kbase_uk_tlstream_flush - User/Kernel space data exchange structure ++ * @header: UK structure header ++ * ++ * This structure is used when performing a call to flush kernel side ++ * timeline streams. ++ */ ++struct kbase_uk_tlstream_flush { ++ union uk_header header; ++ /* IN */ ++ /* OUT */ ++}; ++ ++#if MALI_UNIT_TEST ++/** ++ * struct kbase_uk_tlstream_test - User/Kernel space data exchange structure ++ * @header: UK structure header ++ * @tpw_count: number of trace point writers in each context ++ * @msg_delay: time delay between tracepoints from one writer in milliseconds ++ * @msg_count: number of trace points written by one writer ++ * @aux_msg: if non-zero aux messages will be included ++ * ++ * This structure is used when performing a call to start timeline stream test ++ * embedded in kernel. ++ */ ++struct kbase_uk_tlstream_test { ++ union uk_header header; ++ /* IN */ ++ u32 tpw_count; ++ u32 msg_delay; ++ u32 msg_count; ++ u32 aux_msg; ++ /* OUT */ ++}; ++ ++/** ++ * struct kbase_uk_tlstream_stats - User/Kernel space data exchange structure ++ * @header: UK structure header ++ * @bytes_collected: number of bytes read by user ++ * @bytes_generated: number of bytes generated by tracepoints ++ * ++ * This structure is used when performing a call to obtain timeline stream ++ * statistics. ++ */ ++struct kbase_uk_tlstream_stats { ++ union uk_header header; /**< UK structure header. */ ++ /* IN */ ++ /* OUT */ ++ u32 bytes_collected; ++ u32 bytes_generated; ++}; ++#endif /* MALI_UNIT_TEST */ ++ ++/** ++ * struct struct kbase_uk_prfcnt_value for the KBASE_FUNC_SET_PRFCNT_VALUES ioctl ++ * @header: UK structure header ++ * @data: Counter samples for the dummy model ++ * @size:............Size of the counter sample data ++ */ ++struct kbase_uk_prfcnt_values { ++ union uk_header header; ++ /* IN */ ++ u32 *data; ++ u32 size; ++}; ++ ++/** ++ * struct kbase_uk_soft_event_update - User/Kernel space data exchange structure ++ * @header: UK structure header ++ * @evt: the GPU address containing the event ++ * @new_status: the new event status, must be either BASE_JD_SOFT_EVENT_SET or ++ * BASE_JD_SOFT_EVENT_RESET ++ * @flags: reserved for future uses, must be set to 0 ++ * ++ * This structure is used to update the status of a software event. If the ++ * event's status is set to BASE_JD_SOFT_EVENT_SET, any job currently waiting ++ * on this event will complete. ++ */ ++struct kbase_uk_soft_event_update { ++ union uk_header header; ++ /* IN */ ++ u64 evt; ++ u32 new_status; ++ u32 flags; ++}; ++ ++/** ++ * struct kbase_uk_mem_jit_init - User/Kernel space data exchange structure ++ * @header: UK structure header ++ * @va_pages: Number of virtual pages required for JIT ++ * ++ * This structure is used when requesting initialization of JIT. ++ */ ++struct kbase_uk_mem_jit_init { ++ union uk_header header; ++ /* IN */ ++ u64 va_pages; ++}; ++ ++enum kbase_uk_function_id { ++ KBASE_FUNC_MEM_ALLOC = (UK_FUNC_ID + 0), ++ KBASE_FUNC_MEM_IMPORT = (UK_FUNC_ID + 1), ++ KBASE_FUNC_MEM_COMMIT = (UK_FUNC_ID + 2), ++ KBASE_FUNC_MEM_QUERY = (UK_FUNC_ID + 3), ++ KBASE_FUNC_MEM_FREE = (UK_FUNC_ID + 4), ++ KBASE_FUNC_MEM_FLAGS_CHANGE = (UK_FUNC_ID + 5), ++ KBASE_FUNC_MEM_ALIAS = (UK_FUNC_ID + 6), ++ ++ /* UK_FUNC_ID + 7 not in use since BASE_LEGACY_UK6_SUPPORT dropped */ ++ ++ KBASE_FUNC_SYNC = (UK_FUNC_ID + 8), ++ ++ KBASE_FUNC_POST_TERM = (UK_FUNC_ID + 9), ++ ++ KBASE_FUNC_HWCNT_SETUP = (UK_FUNC_ID + 10), ++ KBASE_FUNC_HWCNT_DUMP = (UK_FUNC_ID + 11), ++ KBASE_FUNC_HWCNT_CLEAR = (UK_FUNC_ID + 12), ++ ++ KBASE_FUNC_GPU_PROPS_REG_DUMP = (UK_FUNC_ID + 14), ++ ++ KBASE_FUNC_FIND_CPU_OFFSET = (UK_FUNC_ID + 15), ++ ++ KBASE_FUNC_GET_VERSION = (UK_FUNC_ID + 16), ++ KBASE_FUNC_SET_FLAGS = (UK_FUNC_ID + 18), ++ ++ KBASE_FUNC_SET_TEST_DATA = (UK_FUNC_ID + 19), ++ KBASE_FUNC_INJECT_ERROR = (UK_FUNC_ID + 20), ++ KBASE_FUNC_MODEL_CONTROL = (UK_FUNC_ID + 21), ++ ++ /* UK_FUNC_ID + 22 not in use since BASE_LEGACY_UK8_SUPPORT dropped */ ++ ++ KBASE_FUNC_FENCE_VALIDATE = (UK_FUNC_ID + 23), ++ KBASE_FUNC_STREAM_CREATE = (UK_FUNC_ID + 24), ++ KBASE_FUNC_GET_PROFILING_CONTROLS = (UK_FUNC_ID + 25), ++ KBASE_FUNC_SET_PROFILING_CONTROLS = (UK_FUNC_ID + 26), ++ /* to be used only for testing ++ * purposes, otherwise these controls ++ * are set through gator API */ ++ ++ KBASE_FUNC_DEBUGFS_MEM_PROFILE_ADD = (UK_FUNC_ID + 27), ++ KBASE_FUNC_JOB_SUBMIT = (UK_FUNC_ID + 28), ++ KBASE_FUNC_DISJOINT_QUERY = (UK_FUNC_ID + 29), ++ ++ KBASE_FUNC_GET_CONTEXT_ID = (UK_FUNC_ID + 31), ++ ++ KBASE_FUNC_TLSTREAM_ACQUIRE_V10_4 = (UK_FUNC_ID + 32), ++#if MALI_UNIT_TEST ++ KBASE_FUNC_TLSTREAM_TEST = (UK_FUNC_ID + 33), ++ KBASE_FUNC_TLSTREAM_STATS = (UK_FUNC_ID + 34), ++#endif /* MALI_UNIT_TEST */ ++ KBASE_FUNC_TLSTREAM_FLUSH = (UK_FUNC_ID + 35), ++ ++ KBASE_FUNC_HWCNT_READER_SETUP = (UK_FUNC_ID + 36), ++ ++#ifdef SUPPORT_MALI_NO_MALI ++ KBASE_FUNC_SET_PRFCNT_VALUES = (UK_FUNC_ID + 37), ++#endif ++ ++ KBASE_FUNC_SOFT_EVENT_UPDATE = (UK_FUNC_ID + 38), ++ ++ KBASE_FUNC_MEM_JIT_INIT = (UK_FUNC_ID + 39), ++ ++ KBASE_FUNC_TLSTREAM_ACQUIRE = (UK_FUNC_ID + 40), ++ ++ KBASE_FUNC_MAX ++}; ++ ++#endif /* _KBASE_UKU_H_ */ ++ +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_vinstr.h b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_vinstr.h +index af7c7b6..c7cf33d 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_vinstr.h ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_vinstr.h +@@ -30,29 +30,6 @@ + struct kbase_vinstr_context; + struct kbase_vinstr_client; + +-struct kbase_uk_hwcnt_setup { +- /* IN */ +- u64 dump_buffer; +- u32 jm_bm; +- u32 shader_bm; +- u32 tiler_bm; +- u32 unused_1; /* keep for backwards compatibility */ +- u32 mmu_l2_bm; +- u32 padding; +- /* OUT */ +-}; +- +-struct kbase_uk_hwcnt_reader_setup { +- /* IN */ +- u32 buffer_count; +- u32 jm_bm; +- u32 shader_bm; +- u32 tiler_bm; +- u32 mmu_l2_bm; +- +- /* OUT */ +- s32 fd; +-}; + /*****************************************************************************/ + + /** +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_midg_regmap.h b/driver/product/kernel/drivers/gpu/arm/midgard/mali_midg_regmap.h +index 5e83ee8..3e698753 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_midg_regmap.h ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_midg_regmap.h +@@ -97,7 +97,6 @@ + #define TEXTURE_FEATURES_0 0x0B0 /* (RO) Support flags for indexed texture formats 0..31 */ + #define TEXTURE_FEATURES_1 0x0B4 /* (RO) Support flags for indexed texture formats 32..63 */ + #define TEXTURE_FEATURES_2 0x0B8 /* (RO) Support flags for indexed texture formats 64..95 */ +-#define TEXTURE_FEATURES_3 0x0BC /* (RO) Support flags for texture order */ + + #define TEXTURE_FEATURES_REG(n) GPU_CONTROL_REG(TEXTURE_FEATURES_0 + ((n) << 2)) + diff --git a/packages/linux-drivers/gpu-sunxi-midgard/patches/03-gpu-arm-Midgard-setup_timer-timer_setup.patch b/packages/linux-drivers/gpu-sunxi-midgard/patches/03-gpu-arm-Midgard-setup_timer-timer_setup.patch new file mode 100644 index 0000000000..f7d450afd9 --- /dev/null +++ b/packages/linux-drivers/gpu-sunxi-midgard/patches/03-gpu-arm-Midgard-setup_timer-timer_setup.patch @@ -0,0 +1,98 @@ +From ee7f0a678fff8316ec0be973f1b3780a63f50942 Mon Sep 17 00:00:00 2001 +From: Myy Miouyouyou +Date: Mon, 11 Dec 2017 21:04:56 +0100 +Subject: [PATCH] gpu: arm: Midgard: setup_timer() -> timer_setup() + +This patch is due the changes provoked by series of commit ending +at 513ae785c63c30741e46f43960213d4ae5382ec0, and removing the +setup_timer macros. +The previous patches replaced made sure that timers were all set +up with setup_timer and replaced setup_timer calls by timer_setup +calls. + +This changed was introduced in the 4.15-rc1. + +Signed-off-by: Myy Miouyouyou +--- + drivers/gpu/arm/midgard/mali_kbase.h | 2 +- + drivers/gpu/arm/midgard/mali_kbase_context.c | 4 ++-- + drivers/gpu/arm/midgard/mali_kbase_softjobs.c | 4 ++-- + drivers/gpu/arm/midgard/mali_kbase_tlstream.c | 6 ++---- + 4 files changed, 7 insertions(+), 9 deletions(-) + +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase.h b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase.h +index a4ceab9e0..27bde3b71 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase.h ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase.h +@@ -213,7 +213,7 @@ int kbase_soft_event_update(struct kbase_context *kctx, + + bool kbase_replay_process(struct kbase_jd_atom *katom); + +-void kbasep_soft_job_timeout_worker(unsigned long data); ++void kbasep_soft_job_timeout_worker(struct timer_list *t); + void kbasep_complete_triggered_soft_events(struct kbase_context *kctx, u64 evt); + + /* api used internally for register access. Contains validation and tracing */ +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_context.c b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_context.c +index f43db48fd..589df768c 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_context.c ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_context.c +@@ -165,9 +165,9 @@ kbase_create_context(struct kbase_device *kbdev, bool is_compat) + + mutex_init(&kctx->vinstr_cli_lock); + +- setup_timer(&kctx->soft_job_timeout, ++ timer_setup(&kctx->soft_job_timeout, + kbasep_soft_job_timeout_worker, +- (uintptr_t)kctx); ++ 0); + + return kctx; + +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_softjobs.c b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_softjobs.c +index 127ada07f..019edf562 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_softjobs.c ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_softjobs.c +@@ -370,9 +370,9 @@ static void kbase_fence_debug_timeout(struct kbase_jd_atom *katom) + } + #endif /* CONFIG_MALI_FENCE_DEBUG */ + +-void kbasep_soft_job_timeout_worker(unsigned long data) ++void kbasep_soft_job_timeout_worker(struct timer_list *t) + { +- struct kbase_context *kctx = (struct kbase_context *)data; ++ struct kbase_context *kctx = from_timer(kctx, t, soft_job_timeout); + u32 timeout_ms = (u32)atomic_read( + &kctx->kbdev->js_data.soft_job_timeout_ms); + struct timer_list *timer = &kctx->soft_job_timeout; +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_tlstream.c b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_tlstream.c +index d01aa23b2..11d8b59c7 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_tlstream.c ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_tlstream.c +@@ -1042,13 +1042,11 @@ static void kbasep_tlstream_flush_stream(enum tl_stream_type stype) + * Timer is executed periodically to check if any of the stream contains + * buffer ready to be submitted to user space. + */ +-static void kbasep_tlstream_autoflush_timer_callback(unsigned long data) ++static void kbasep_tlstream_autoflush_timer_callback(struct timer_list *unused) + { + enum tl_stream_type stype; + int rcode; + +- CSTD_UNUSED(data); +- + for (stype = 0; stype < TL_STREAM_TYPE_COUNT; stype++) { + struct tl_stream *stream = tl_stream[stype]; + unsigned long flags; +@@ -1371,7 +1369,7 @@ int kbase_tlstream_init(void) + + /* Initialize autoflush timer. */ + atomic_set(&autoflush_timer_active, 0); +- setup_timer(&autoflush_timer, ++ timer_setup(&autoflush_timer, + kbasep_tlstream_autoflush_timer_callback, + 0); + +-- +2.14.1 + diff --git a/packages/linux-drivers/gpu-sunxi-midgard/patches/04-drivers-gpu-Arm-Midgard-Replace-ACCESS_ONCE-by-READ_.patch b/packages/linux-drivers/gpu-sunxi-midgard/patches/04-drivers-gpu-Arm-Midgard-Replace-ACCESS_ONCE-by-READ_.patch new file mode 100644 index 0000000000..113c53d11c --- /dev/null +++ b/packages/linux-drivers/gpu-sunxi-midgard/patches/04-drivers-gpu-Arm-Midgard-Replace-ACCESS_ONCE-by-READ_.patch @@ -0,0 +1,35 @@ +From 44a5ba2e969adfb64c84f294c16490194988dcc7 Mon Sep 17 00:00:00 2001 +From: Myy Miouyouyou +Date: Sun, 24 Dec 2017 19:30:12 +0100 +Subject: [PATCH] drivers: gpu: Arm: Midgard: Replace ACCESS_ONCE by READ_ONCE + +The ACCESS_ONCE macro has now been removed in the 4.15.0-rc4, +and every ACCESS_ONCE call has been replaced by either READ_ONCE or +WRITE_ONCE calls. +Since the Midgard GPU drivers are not mainlined, the change +needs to be applied manually. + +See commit b899a850431e2dd0943205a63a68573f3e312d0d and its parents, +for more informations. + +Signed-off-by: Myy Miouyouyou +--- + drivers/gpu/arm/midgard/mali_kbase_mem.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_mem.h b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_mem.h +index e9a8d5dd6..eac685699 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_mem.h ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_mem.h +@@ -591,7 +591,7 @@ void kbase_mem_pool_free_pages(struct kbase_mem_pool *pool, size_t nr_pages, + */ + static inline size_t kbase_mem_pool_size(struct kbase_mem_pool *pool) + { +- return ACCESS_ONCE(pool->cur_size); ++ return READ_ONCE(pool->cur_size); + } + + /** +-- +2.14.1 + diff --git a/packages/linux-drivers/gpu-sunxi-midgard/patches/05-gpu-arm-midgard-Remove-sys_close-references.patch b/packages/linux-drivers/gpu-sunxi-midgard/patches/05-gpu-arm-midgard-Remove-sys_close-references.patch new file mode 100644 index 0000000000..cbf74b7271 --- /dev/null +++ b/packages/linux-drivers/gpu-sunxi-midgard/patches/05-gpu-arm-midgard-Remove-sys_close-references.patch @@ -0,0 +1,32 @@ +From 47e8aad9419ff8843a373c3e5aa2c9d261d8cd07 Mon Sep 17 00:00:00 2001 +From: Myy Miouyouyou +Date: Mon, 23 Apr 2018 20:54:13 +0200 +Subject: [PATCH] gpu: arm: midgard: Remove sys_close references + +sys_close is now replaced by ksys_close in an effort to remove +in-kernel system calls references. + +See 2ca2a09d6215fd9621aa3e2db7cc9428a61f2911 and +https://lkml.org/lkml/2018/3/25/93 for more details. + +Signed-off-by: Myy Miouyouyou +--- + drivers/gpu/arm/midgard/mali_kbase_sync.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_sync.h b/drivers/gpu/arm/midgard/mali_kbase_sync.h +index de72147d..33b58059 100644 +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_sync.h ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_sync.h +@@ -156,7 +156,7 @@ void kbase_sync_fence_out_remove(struct kbase_jd_atom *katom); + */ + static inline void kbase_sync_fence_close_fd(int fd) + { +- sys_close(fd); ++ ksys_close(fd); + } + + /** +-- +2.14.1 + diff --git a/packages/linux-drivers/gpu-sunxi-midgard/patches/06-fix-4.20-build.patch b/packages/linux-drivers/gpu-sunxi-midgard/patches/06-fix-4.20-build.patch new file mode 100644 index 0000000000..86711dcde5 --- /dev/null +++ b/packages/linux-drivers/gpu-sunxi-midgard/patches/06-fix-4.20-build.patch @@ -0,0 +1,60 @@ +diff -Nur a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_mem_linux.c c/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_mem_linux.c +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_mem_linux.c 2018-12-01 17:49:08.000000000 +0100 ++++ c/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_mem_linux.c 2018-12-01 20:27:42.057964019 +0100 +@@ -1668,6 +1668,7 @@ + struct kbase_cpu_mapping *map = vma->vm_private_data; + pgoff_t rel_pgoff; + size_t i; ++ int ret = VM_FAULT_SIGBUS; + pgoff_t addr; + + KBASE_DEBUG_ASSERT(map); +@@ -1693,9 +1694,9 @@ + addr = (pgoff_t)(vmf->address >> PAGE_SHIFT); + #endif + while (i < map->alloc->nents && (addr < vma->vm_end >> PAGE_SHIFT)) { +- int ret = vm_insert_pfn(vma, addr << PAGE_SHIFT, ++ ret = vmf_insert_pfn(vma, addr << PAGE_SHIFT, + PFN_DOWN(as_phys_addr_t(map->alloc->pages[i]))); +- if (ret < 0 && ret != -EBUSY) ++ if (unlikely(ret & VM_FAULT_ERROR)) + goto locked_bad_fault; + + i++; addr++; +@@ -1707,7 +1708,7 @@ + + locked_bad_fault: + kbase_gpu_vm_unlock(map->kctx); +- return VM_FAULT_SIGBUS; ++ return ret; + } + + const struct vm_operations_struct kbase_vm_ops = { +@@ -1776,10 +1777,11 @@ + phys_addr_t phys; + + phys = as_phys_addr_t(page_array[i + start_off]); +- err = vm_insert_pfn(vma, addr, PFN_DOWN(phys)); +- if (WARN_ON(err)) ++ err = vmf_insert_pfn(vma, addr, PFN_DOWN(phys)); ++ if (unlikely(WARN_ON(err & VM_FAULT_ERROR))) + break; + ++ err = 0; + addr += PAGE_SIZE; + } + } else { +diff -Nur a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_smc.c c/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_smc.c +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_smc.c 2018-01-13 23:26:00.000000000 +0100 ++++ c/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_smc.c 2018-12-01 20:03:30.071690693 +0100 +@@ -27,6 +27,10 @@ + + #include + ++#ifndef __asmeq ++#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" ++#endif ++ + static noinline u64 invoke_smc_fid(u64 function_id, + u64 arg0, u64 arg1, u64 arg2) + { diff --git a/packages/linux-drivers/gpu-sunxi-midgard/patches/07-some-fixes.patch b/packages/linux-drivers/gpu-sunxi-midgard/patches/07-some-fixes.patch new file mode 100644 index 0000000000..5875804fa1 --- /dev/null +++ b/packages/linux-drivers/gpu-sunxi-midgard/patches/07-some-fixes.patch @@ -0,0 +1,30 @@ +diff -Nur a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_core_linux.c b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_core_linux.c +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_core_linux.c 2018-12-01 21:10:15.000000000 +0100 ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_core_linux.c 2018-12-01 23:28:48.956901556 +0100 +@@ -3815,12 +3815,18 @@ + "Continuing without Mali regulator control\n"); + /* Allow probe to continue without regulator */ + } ++ err = regulator_enable(kbdev->regulator); ++ if (err) { ++ dev_err(kbdev->dev, "Failed to enable regulator\n"); ++ return err; ++ } + #endif /* LINUX_VERSION_CODE >= 3, 12, 0 */ + + kbdev->mali_rst = of_reset_control_get_by_index(kbdev->dev->of_node, 0); + if (IS_ERR(kbdev->mali_rst)) { + dev_err(kbdev->dev, "Couldn't get mali reset line\n"); + err = PTR_ERR(kbdev->mali_rst); ++ kbdev->mali_rst = NULL; + goto fail; + } + +@@ -3828,6 +3834,7 @@ + if (IS_ERR(kbdev->bus_clk)) { + dev_err(kbdev->dev, "Couldn't get the mali bus clock\n"); + err = PTR_ERR(kbdev->bus_clk); ++ kbdev->bus_clk = NULL; + goto fail; + } + diff --git a/packages/linux-drivers/gpu-sunxi-midgard/patches/08-fix-building-with-5.0.patch b/packages/linux-drivers/gpu-sunxi-midgard/patches/08-fix-building-with-5.0.patch new file mode 100644 index 0000000000..aedb6968eb --- /dev/null +++ b/packages/linux-drivers/gpu-sunxi-midgard/patches/08-fix-building-with-5.0.patch @@ -0,0 +1,15 @@ +diff -Nur a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_gpuprops.c b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_gpuprops.c +--- a/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_gpuprops.c 2019-02-09 23:20:20.000000000 +0100 ++++ b/driver/product/kernel/drivers/gpu/arm/midgard/mali_kbase_gpuprops.c 2019-02-10 08:26:47.874751287 +0100 +@@ -243,7 +243,11 @@ + /* Populate the base_gpu_props structure */ + kbase_gpuprops_update_core_props_gpu_id(gpu_props); + gpu_props->core_props.log2_program_counter_size = KBASE_GPU_PC_SIZE_LOG2; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0) ++ gpu_props->core_props.gpu_available_memory_size = totalram_pages() << PAGE_SHIFT; ++#else + gpu_props->core_props.gpu_available_memory_size = totalram_pages << PAGE_SHIFT; ++#endif + + for (i = 0; i < BASE_GPU_NUM_TEXTURE_FEATURES_REGISTERS; i++) + gpu_props->core_props.texture_features[i] = gpu_props->raw_props.texture_features[i];