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Revert "gcc: add patch to workaround aginst bug GCC-49423" not more needed if we dont build RTL8723AU
This reverts commit 46b82168713d454e584528f69b63289423a39f90.
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@ -1,118 +0,0 @@
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Date: Tue, 18 Jun 2013 16:42:13 +0100
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From: Julian Brown <julian at codesourcery dot com>
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To: <gcc-patches at gcc dot gnu dot org>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>, Ramana Radhakrishnan <ramrad01 at arm dot com>
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Subject: [PATCH, ARM] Reintroduce minipool ranges for zero-extension insn patterns
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Hi,
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The following patch removed pool_range/neg_pool_range attributes from
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several instructions as a cleanup, which I believe to have been
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incorrect:
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http://gcc.gnu.org/ml/gcc-patches/2010-07/msg01036.html
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On a Mentor-local branch, this caused problems with instructions like:
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(insn 77 53 87 (set (reg:SI 8 r8 [orig:197 s.4 ] [197])
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(zero_extend:SI (mem/u/c:HI (symbol_ref/u:SI ("*.LC0") [flags 0x2]) [7 S2 A16]))) [...] 161 {*arm_zero_extendhisi2_v6}
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(nil))
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The reasoning behind the cleanup was that the instructions in question
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have no immediate constraints -- but the minipool code is used for more
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than just immediates, e.g. in the above case where a symbol reference
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("m") is loaded.
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I don't have a test case for the problem on mainline at present, but I
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believe it is still a latent bug. Tested with the default multilibs (ARM
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& Thumb mode) on arm-none-eabi, with no regressions. (The patch has
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also been tested with more multilibs on our local branches for a while,
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and I did ensure previously that it did not adversely affect Bernd's
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patch linked above.)
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OK to apply?
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Thanks,
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Julian
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ChangeLog
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gcc/
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* arm.md (*thumb1_zero_extendhisi2, *arm_zero_extendhisi2)
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(*arm_zero_extendhisi2_v6, *thumb1_zero_extendqisi2)
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(*thumb1_zero_extendqisi2_v6, *arm_zero_extendqisi2)
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(*arm_zero_extendqisi2_v6): Add pool_range, neg_pool_range
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attributes.
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Index: gcc/config/arm/arm.md
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===================================================================
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--- a/gcc/config/arm/arm.md (revision 200171)
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+++ b/gcc/config/arm/arm.md (working copy)
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@@ -5313,7 +5313,8 @@
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[(if_then_else (eq_attr "is_arch6" "yes")
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(const_int 2) (const_int 4))
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(const_int 4)])
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- (set_attr "type" "simple_alu_shift, load_byte")]
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+ (set_attr "type" "simple_alu_shift, load_byte")
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+ (set_attr "pool_range" "*,60")]
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)
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(define_insn "*arm_zero_extendhisi2"
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@@ -5324,7 +5325,9 @@
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#
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ldr%(h%)\\t%0, %1"
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[(set_attr "type" "alu_shift,load_byte")
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- (set_attr "predicable" "yes")]
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+ (set_attr "predicable" "yes")
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+ (set_attr "pool_range" "*,256")
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+ (set_attr "neg_pool_range" "*,244")]
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)
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(define_insn "*arm_zero_extendhisi2_v6"
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@@ -5335,7 +5338,9 @@
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uxth%?\\t%0, %1
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ldr%(h%)\\t%0, %1"
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[(set_attr "predicable" "yes")
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- (set_attr "type" "simple_alu_shift,load_byte")]
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+ (set_attr "type" "simple_alu_shift,load_byte")
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+ (set_attr "pool_range" "*,256")
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+ (set_attr "neg_pool_range" "*,244")]
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)
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(define_insn "*arm_zero_extendhisi2addsi"
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@@ -5405,7 +5410,8 @@
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uxtb\\t%0, %1
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ldrb\\t%0, %1"
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[(set_attr "length" "2")
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- (set_attr "type" "simple_alu_shift,load_byte")]
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+ (set_attr "type" "simple_alu_shift,load_byte")
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+ (set_attr "pool_range" "*,32")]
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)
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(define_insn "*arm_zero_extendqisi2"
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@@ -5417,7 +5423,9 @@
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ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
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[(set_attr "length" "8,4")
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(set_attr "type" "alu_shift,load_byte")
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- (set_attr "predicable" "yes")]
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+ (set_attr "predicable" "yes")
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+ (set_attr "pool_range" "*,4096")
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+ (set_attr "neg_pool_range" "*,4084")]
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)
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(define_insn "*arm_zero_extendqisi2_v6"
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@@ -5428,7 +5436,9 @@
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uxtb%(%)\\t%0, %1
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ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
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[(set_attr "type" "simple_alu_shift,load_byte")
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- (set_attr "predicable" "yes")]
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+ (set_attr "predicable" "yes")
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+ (set_attr "pool_range" "*,4096")
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+ (set_attr "neg_pool_range" "*,4084")]
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)
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(define_insn "*arm_zero_extendqisi2addsi"
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--MP_/ERKB4.gCWGZVf9oWJO6IZSe--
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