linux: update to linux-3.18.4

Signed-off-by: Stephan Raue <stephan@openelec.tv>

packages/linux/package.mk

@@ -27,7 +27,7 @@ case "$LINUX" in
     PKG_URL="$DISTRO_SRC/$PKG_NAME-$PKG_VERSION.tar.xz"
     ;;
   *)
-    PKG_VERSION="3.18.3"
+    PKG_VERSION="3.18.4"
     PKG_URL="http://www.kernel.org/pub/linux/kernel/v3.x/$PKG_NAME-$PKG_VERSION.tar.xz"
     ;;
 esac

packages/linux/patches/3.18.3/linux-011-intel-force-cs-stall.patch

@@ -1,37 +0,0 @@
-From 78e2b1bdd84264d6a9d84759da26547f887552cd Mon Sep 17 00:00:00 2001
-From: Chris Wilson <chris@chris-wilson.co.uk>
-Date: Tue, 16 Dec 2014 08:44:32 +0000
-Subject: [PATCH] drm/i915: Force the CS stall for invalidate flushes
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-In order to act as a full command barrier by itself, we need to tell the
-pipecontrol to actually stall the command streamer while the flush runs.
-We require the full command barrier before operations like
-MI_SET_CONTEXT, which currently rely on a prior invalidate flush.
-
-References: https://bugs.freedesktop.org/show_bug.cgi?id=83677
-Cc: Simon Farnsworth <simon@farnz.org.uk>
-Cc: Daniel Vetter <daniel@ffwll.ch>
-Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
-Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
-Cc: stable@vger.kernel.org
-Signed-off-by: Jani Nikula <jani.nikula@intel.com>
----
- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
-index b02cf69..ae17e77 100644
---- a/drivers/gpu/drm/i915/intel_ringbuffer.c
-+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
-@@ -369,6 +369,8 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
- 		flags |= PIPE_CONTROL_QW_WRITE;
- 		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
- 
-+		flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
-+
- 		/* Workaround: we must issue a pipe_control with CS-stall bit
- 		 * set before a pipe_control command that has the state cache
- 		 * invalidate bit set. */

packages/linux/patches/3.18.3/linux-012-intel-fix-ivb-stall.patch

@@ -1,49 +0,0 @@
-From 32431fd81d65259d490e53e3cfc7e1a2ad781fe3 Mon Sep 17 00:00:00 2001
-From: Chris Wilson <chris@chris-wilson.co.uk>
-Date: Tue, 16 Dec 2014 08:44:31 +0000
-Subject: [PATCH] drm/i915: Invalidate media caches on gen7
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-In the gen7 pipe control there is an extra bit to flush the media
-caches, so let's set it during cache invalidation flushes.
-
-v2: Rename to MEDIA_STATE_CLEAR to be more inline with spec.
-
-Cc: Simon Farnsworth <simon@farnz.org.uk>
-Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
-Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
-Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
-Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-Cc: stable@vger.kernel.org
-Signed-off-by: Jani Nikula <jani.nikula@intel.com>
----
- drivers/gpu/drm/i915/i915_reg.h         | 1 +
- drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
- 2 files changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
-index c01e5f3..d9780e2 100644
---- a/drivers/gpu/drm/i915/i915_reg.h
-+++ b/drivers/gpu/drm/i915/i915_reg.h
-@@ -370,6 +370,7 @@
- #define   PIPE_CONTROL_STORE_DATA_INDEX			(1<<21)
- #define   PIPE_CONTROL_CS_STALL				(1<<20)
- #define   PIPE_CONTROL_TLB_INVALIDATE			(1<<18)
-+#define   PIPE_CONTROL_MEDIA_STATE_CLEAR		(1<<16)
- #define   PIPE_CONTROL_QW_WRITE				(1<<14)
- #define   PIPE_CONTROL_POST_SYNC_OP_MASK                (3<<14)
- #define   PIPE_CONTROL_DEPTH_STALL			(1<<13)
-diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
-index 0a80e41..b02cf69 100644
---- a/drivers/gpu/drm/i915/intel_ringbuffer.c
-+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
-@@ -362,6 +362,7 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
- 		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
- 		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
- 		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
-+		flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
- 		/*
- 		 * TLB invalidate requires a post-sync write.
- 		 */