From 55f7da3dbcfdd2828b7df309a4ed706f66dea412 Mon Sep 17 00:00:00 2001 From: Stephan Raue Date: Thu, 16 Oct 2014 14:29:11 +0200 Subject: [PATCH] linux: update to linux-3.17.1, update kernel config, update RPi support patch. TODO: rework some patches from packages/linux/patches/3.17.1/todo Signed-off-by: Stephan Raue --- packages/linux/package.mk | 2 +- ..._support_for_Xbox-One_controllers.patch.bk | 348 - ...-add_Adaptec_eHome_Infrared_Receiver.patch | 21 - .../linux-224-geniatech-t220-dvb-t2-fix.patch | 97 - .../linux-003-no_dev_console.patch | 0 .../linux-051-ouya_controller_support.patch | 0 .../linux-052-XBOX_remote_support.patch | 0 .../linux-053-spinelplus-remote-0.2.patch | 0 ...1056c5564eec8a1b169c6e84ff3.6.114c13.patch | 0 ...-add_Formosa_eHome_Infrared_Receiver.patch | 0 ...-add_Adaptec_eHome_Infrared_Receiver.patch | 21 + ..._Manufacturing_Inc_Infrared_Receiver.patch | 0 ..._sony-add_autorepeat_for_PS3_remotes.patch | 23 +- .../linux-058.06-hid_sony-add_SMK_link.patch | 0 .../linux-059-remove_some_xpad_pids-0.2.patch | 0 .../linux-060-add_AUGUST_DVB-T205.patch | 0 .../linux-062-imon_pad_ignore_diagonal.patch | 0 ...x-203-stb0899_enable_low_symbol_rate.patch | 0 .../{3.16.5 => 3.17.1}/linux-210-dvbsky.patch | 126 +- .../linux-211-dvbsky-s950v3-s952v3.patch | 2 +- ...linux-212-mantis_stb0899_faster_lock.patch | 0 .../linux-221-ngene-octopus.patch | 19779 ++++++++-------- .../linux-222-stb0899_signal_quality.patch | 0 ...-video-artifacts-with-tt-3600-s2-usb.patch | 0 .../linux-703-macmini2012-ethernet.patch | 0 ...Support-for-Buffalo-WLI-UC-G300HP-V1.patch | 0 .../linux-706-Sitecom-N300.patch | 0 .../linux-900-hide_tsc_error.patch | 0 ...x-950-saa716x_PCIe_interface_chipset.patch | 0 ...utputting-HDMI-audio-before-prepare-.patch | 0 .../linux-995-CX24120-13Z_frontend.patch | 0 ...able-async-suspend-resume-by-default.patch | 0 ...tomer-code-restriction-in-rc6-decode.patch | 0 .../todo}/linux-061-valve-xpad-rework.patch | 0 .../linux-701-linksys_aes2500_brcmfmac.patch | 0 projects/Generic/linux/linux.i386.conf | 134 +- projects/Generic/linux/linux.x86_64.conf | 141 +- projects/RPi/linux/linux.arm.conf | 175 +- .../patches/linux/linux-01-RPi_support.patch | 14008 +++++------ 39 files changed, 16657 insertions(+), 18220 deletions(-) delete mode 100644 packages/linux/patches/3.16.5/linux-050-xpad-add_support_for_Xbox-One_controllers.patch.bk delete mode 100644 packages/linux/patches/3.16.5/linux-056-add_Adaptec_eHome_Infrared_Receiver.patch delete mode 100644 packages/linux/patches/3.16.5/linux-224-geniatech-t220-dvb-t2-fix.patch rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-003-no_dev_console.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-051-ouya_controller_support.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-052-XBOX_remote_support.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-053-spinelplus-remote-0.2.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-054-nuvoton_revert_d7b290a1056c5564eec8a1b169c6e84ff3.6.114c13.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-055-add_Formosa_eHome_Infrared_Receiver.patch (100%) create mode 100644 packages/linux/patches/3.17.1/linux-056-add_Adaptec_eHome_Infrared_Receiver.patch rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-057-add_SMK_Manufacturing_Inc_Infrared_Receiver.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-058.05-hid_sony-add_autorepeat_for_PS3_remotes.patch (81%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-058.06-hid_sony-add_SMK_link.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-059-remove_some_xpad_pids-0.2.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-060-add_AUGUST_DVB-T205.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-062-imon_pad_ignore_diagonal.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-203-stb0899_enable_low_symbol_rate.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-210-dvbsky.patch (97%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-211-dvbsky-s950v3-s952v3.patch (99%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-212-mantis_stb0899_faster_lock.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-221-ngene-octopus.patch (98%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-222-stb0899_signal_quality.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-223-Fix-video-artifacts-with-tt-3600-s2-usb.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-703-macmini2012-ethernet.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-705-Support-for-Buffalo-WLI-UC-G300HP-V1.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-706-Sitecom-N300.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-900-hide_tsc_error.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-950-saa716x_PCIe_interface_chipset.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-990.06-hda-Avoid-outputting-HDMI-audio-before-prepare-.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-995-CX24120-13Z_frontend.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1}/linux-999.02-0001-pm-disable-async-suspend-resume-by-default.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1/todo}/linux-057-Removed-MCE-customer-code-restriction-in-rc6-decode.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1/todo}/linux-061-valve-xpad-rework.patch (100%) rename packages/linux/patches/{3.16.5 => 3.17.1/todo}/linux-701-linksys_aes2500_brcmfmac.patch (100%) diff --git a/packages/linux/package.mk b/packages/linux/package.mk index 3a6b51fb04..26454d9c1b 100644 --- a/packages/linux/package.mk +++ b/packages/linux/package.mk @@ -23,7 +23,7 @@ case "$LINUX" in PKG_URL="$DISTRO_SRC/$PKG_NAME-$PKG_VERSION.tar.xz" ;; *) - PKG_VERSION="3.16.5" + PKG_VERSION="3.17.1" PKG_URL="http://www.kernel.org/pub/linux/kernel/v3.x/$PKG_NAME-$PKG_VERSION.tar.xz" ;; esac diff --git a/packages/linux/patches/3.16.5/linux-050-xpad-add_support_for_Xbox-One_controllers.patch.bk b/packages/linux/patches/3.16.5/linux-050-xpad-add_support_for_Xbox-One_controllers.patch.bk deleted file mode 100644 index 12cc96015c..0000000000 --- a/packages/linux/patches/3.16.5/linux-050-xpad-add_support_for_Xbox-One_controllers.patch.bk +++ /dev/null @@ -1,348 +0,0 @@ -From 1a48ff81b3912be5fadae3fafde6c2f632246a4c Mon Sep 17 00:00:00 2001 -From: Ted Mielczarek -Date: Fri, 8 Aug 2014 11:21:59 -0700 -Subject: Input: xpad - add support for Xbox One controllers - -Xbox One controllers require an initialization message to start sending -data, so xpad_init_output becomes a required function. The Xbox One -controller does not have LEDs like the Xbox 360 controller, so that -functionality is not implemented. The format of messages controlling rumble -is currently undocumented, so rumble support is not yet implemented. - -Note that Xbox One controller advertises three interfaces with the same -interface class, subclass and protocol, so we have to also match against -interface number. - -Signed-off-by: Ted Mielczarek -Signed-off-by: Dmitry Torokhov - -diff --git a/drivers/input/joystick/xpad.c b/drivers/input/joystick/xpad.c -index 603fe0d..177602c 100644 ---- a/drivers/input/joystick/xpad.c -+++ b/drivers/input/joystick/xpad.c -@@ -95,7 +95,8 @@ - #define XTYPE_XBOX 0 - #define XTYPE_XBOX360 1 - #define XTYPE_XBOX360W 2 --#define XTYPE_UNKNOWN 3 -+#define XTYPE_XBOXONE 3 -+#define XTYPE_UNKNOWN 4 - - static bool dpad_to_buttons; - module_param(dpad_to_buttons, bool, S_IRUGO); -@@ -121,6 +122,7 @@ static const struct xpad_device { - { 0x045e, 0x0287, "Microsoft Xbox Controller S", 0, XTYPE_XBOX }, - { 0x045e, 0x0289, "Microsoft X-Box pad v2 (US)", 0, XTYPE_XBOX }, - { 0x045e, 0x028e, "Microsoft X-Box 360 pad", 0, XTYPE_XBOX360 }, -+ { 0x045e, 0x02d1, "Microsoft X-Box One pad", 0, XTYPE_XBOXONE }, - { 0x045e, 0x0291, "Xbox 360 Wireless Receiver (XBOX)", MAP_DPAD_TO_BUTTONS, XTYPE_XBOX360W }, - { 0x045e, 0x0719, "Xbox 360 Wireless Receiver", MAP_DPAD_TO_BUTTONS, XTYPE_XBOX360W }, - { 0x044f, 0x0f07, "Thrustmaster, Inc. Controller", 0, XTYPE_XBOX }, -@@ -231,10 +233,12 @@ static const signed short xpad_abs_triggers[] = { - -1 - }; - --/* Xbox 360 has a vendor-specific class, so we cannot match it with only -+/* -+ * Xbox 360 has a vendor-specific class, so we cannot match it with only - * USB_INTERFACE_INFO (also specifically refused by USB subsystem), so we - * match against vendor id as well. Wired Xbox 360 devices have protocol 1, -- * wireless controllers have protocol 129. */ -+ * wireless controllers have protocol 129. -+ */ - #define XPAD_XBOX360_VENDOR_PROTOCOL(vend,pr) \ - .match_flags = USB_DEVICE_ID_MATCH_VENDOR | USB_DEVICE_ID_MATCH_INT_INFO, \ - .idVendor = (vend), \ -@@ -245,9 +249,20 @@ static const signed short xpad_abs_triggers[] = { - { XPAD_XBOX360_VENDOR_PROTOCOL(vend,1) }, \ - { XPAD_XBOX360_VENDOR_PROTOCOL(vend,129) } - -+/* The Xbox One controller uses subclass 71 and protocol 208. */ -+#define XPAD_XBOXONE_VENDOR_PROTOCOL(vend, pr) \ -+ .match_flags = USB_DEVICE_ID_MATCH_VENDOR | USB_DEVICE_ID_MATCH_INT_INFO, \ -+ .idVendor = (vend), \ -+ .bInterfaceClass = USB_CLASS_VENDOR_SPEC, \ -+ .bInterfaceSubClass = 71, \ -+ .bInterfaceProtocol = (pr) -+#define XPAD_XBOXONE_VENDOR(vend) \ -+ { XPAD_XBOXONE_VENDOR_PROTOCOL(vend, 208) } -+ - static struct usb_device_id xpad_table[] = { - { USB_INTERFACE_INFO('X', 'B', 0) }, /* X-Box USB-IF not approved class */ - XPAD_XBOX360_VENDOR(0x045e), /* Microsoft X-Box 360 controllers */ -+ XPAD_XBOXONE_VENDOR(0x045e), /* Microsoft X-Box One controllers */ - XPAD_XBOX360_VENDOR(0x046d), /* Logitech X-Box 360 style controllers */ - XPAD_XBOX360_VENDOR(0x0738), /* Mad Catz X-Box 360 controllers */ - { USB_DEVICE(0x0738, 0x4540) }, /* Mad Catz Beat Pad */ -@@ -278,12 +293,10 @@ struct usb_xpad { - struct urb *bulk_out; - unsigned char *bdata; - --#if defined(CONFIG_JOYSTICK_XPAD_FF) || defined(CONFIG_JOYSTICK_XPAD_LEDS) - struct urb *irq_out; /* urb for interrupt out report */ - unsigned char *odata; /* output data */ - dma_addr_t odata_dma; - struct mutex odata_mutex; --#endif - - #if defined(CONFIG_JOYSTICK_XPAD_LEDS) - struct xpad_led *led; -@@ -470,6 +483,105 @@ static void xpad360w_process_packet(struct usb_xpad *xpad, u16 cmd, unsigned cha - xpad360_process_packet(xpad, cmd, &data[4]); - } - -+/* -+ * xpadone_process_buttons -+ * -+ * Process a button update packet from an Xbox one controller. -+ */ -+static void xpadone_process_buttons(struct usb_xpad *xpad, -+ struct input_dev *dev, -+ unsigned char *data) -+{ -+ /* menu/view buttons */ -+ input_report_key(dev, BTN_START, data[4] & 0x04); -+ input_report_key(dev, BTN_SELECT, data[4] & 0x08); -+ -+ /* buttons A,B,X,Y */ -+ input_report_key(dev, BTN_A, data[4] & 0x10); -+ input_report_key(dev, BTN_B, data[4] & 0x20); -+ input_report_key(dev, BTN_X, data[4] & 0x40); -+ input_report_key(dev, BTN_Y, data[4] & 0x80); -+ -+ /* digital pad */ -+ if (xpad->mapping & MAP_DPAD_TO_BUTTONS) { -+ /* dpad as buttons (left, right, up, down) */ -+ input_report_key(dev, BTN_TRIGGER_HAPPY1, data[5] & 0x04); -+ input_report_key(dev, BTN_TRIGGER_HAPPY2, data[5] & 0x08); -+ input_report_key(dev, BTN_TRIGGER_HAPPY3, data[5] & 0x01); -+ input_report_key(dev, BTN_TRIGGER_HAPPY4, data[5] & 0x02); -+ } else { -+ input_report_abs(dev, ABS_HAT0X, -+ !!(data[5] & 0x08) - !!(data[5] & 0x04)); -+ input_report_abs(dev, ABS_HAT0Y, -+ !!(data[5] & 0x02) - !!(data[5] & 0x01)); -+ } -+ -+ /* TL/TR */ -+ input_report_key(dev, BTN_TL, data[5] & 0x10); -+ input_report_key(dev, BTN_TR, data[5] & 0x20); -+ -+ /* stick press left/right */ -+ input_report_key(dev, BTN_THUMBL, data[5] & 0x40); -+ input_report_key(dev, BTN_THUMBR, data[5] & 0x80); -+ -+ if (!(xpad->mapping & MAP_STICKS_TO_NULL)) { -+ /* left stick */ -+ input_report_abs(dev, ABS_X, -+ (__s16) le16_to_cpup((__le16 *)(data + 10))); -+ input_report_abs(dev, ABS_Y, -+ ~(__s16) le16_to_cpup((__le16 *)(data + 12))); -+ -+ /* right stick */ -+ input_report_abs(dev, ABS_RX, -+ (__s16) le16_to_cpup((__le16 *)(data + 14))); -+ input_report_abs(dev, ABS_RY, -+ ~(__s16) le16_to_cpup((__le16 *)(data + 16))); -+ } -+ -+ /* triggers left/right */ -+ if (xpad->mapping & MAP_TRIGGERS_TO_BUTTONS) { -+ input_report_key(dev, BTN_TL2, -+ (__u16) le16_to_cpup((__le16 *)(data + 6))); -+ input_report_key(dev, BTN_TR2, -+ (__u16) le16_to_cpup((__le16 *)(data + 8))); -+ } else { -+ input_report_abs(dev, ABS_Z, -+ (__u16) le16_to_cpup((__le16 *)(data + 6))); -+ input_report_abs(dev, ABS_RZ, -+ (__u16) le16_to_cpup((__le16 *)(data + 8))); -+ } -+ -+ input_sync(dev); -+} -+ -+/* -+ * xpadone_process_packet -+ * -+ * Completes a request by converting the data into events for the -+ * input subsystem. This version is for the Xbox One controller. -+ * -+ * The report format was gleaned from -+ * https://github.com/kylelemons/xbox/blob/master/xbox.go -+ */ -+ -+static void xpadone_process_packet(struct usb_xpad *xpad, -+ u16 cmd, unsigned char *data) -+{ -+ struct input_dev *dev = xpad->dev; -+ -+ switch (data[0]) { -+ case 0x20: -+ xpadone_process_buttons(xpad, dev, data); -+ break; -+ -+ case 0x07: -+ /* the xbox button has its own special report */ -+ input_report_key(dev, BTN_MODE, data[4] & 0x01); -+ input_sync(dev); -+ break; -+ } -+} -+ - static void xpad_irq_in(struct urb *urb) - { - struct usb_xpad *xpad = urb->context; -@@ -502,6 +614,9 @@ static void xpad_irq_in(struct urb *urb) - case XTYPE_XBOX360W: - xpad360w_process_packet(xpad, 0, xpad->idata); - break; -+ case XTYPE_XBOXONE: -+ xpadone_process_packet(xpad, 0, xpad->idata); -+ break; - default: - xpad_process_packet(xpad, 0, xpad->idata); - } -@@ -535,7 +650,6 @@ static void xpad_bulk_out(struct urb *urb) - } - } - --#if defined(CONFIG_JOYSTICK_XPAD_FF) || defined(CONFIG_JOYSTICK_XPAD_LEDS) - static void xpad_irq_out(struct urb *urb) - { - struct usb_xpad *xpad = urb->context; -@@ -573,6 +687,7 @@ exit: - static int xpad_init_output(struct usb_interface *intf, struct usb_xpad *xpad) - { - struct usb_endpoint_descriptor *ep_irq_out; -+ int ep_irq_out_idx; - int error; - - if (xpad->xtype == XTYPE_UNKNOWN) -@@ -593,7 +708,10 @@ static int xpad_init_output(struct usb_interface *intf, struct usb_xpad *xpad) - goto fail2; - } - -- ep_irq_out = &intf->cur_altsetting->endpoint[1].desc; -+ /* Xbox One controller has in/out endpoints swapped. */ -+ ep_irq_out_idx = xpad->xtype == XTYPE_XBOXONE ? 0 : 1; -+ ep_irq_out = &intf->cur_altsetting->endpoint[ep_irq_out_idx].desc; -+ - usb_fill_int_urb(xpad->irq_out, xpad->udev, - usb_sndintpipe(xpad->udev, ep_irq_out->bEndpointAddress), - xpad->odata, XPAD_PKT_LEN, -@@ -621,11 +739,6 @@ static void xpad_deinit_output(struct usb_xpad *xpad) - xpad->odata, xpad->odata_dma); - } - } --#else --static int xpad_init_output(struct usb_interface *intf, struct usb_xpad *xpad) { return 0; } --static void xpad_deinit_output(struct usb_xpad *xpad) {} --static void xpad_stop_output(struct usb_xpad *xpad) {} --#endif - - #ifdef CONFIG_JOYSTICK_XPAD_FF - static int xpad_play_effect(struct input_dev *dev, void *data, struct ff_effect *effect) -@@ -692,7 +805,7 @@ static int xpad_play_effect(struct input_dev *dev, void *data, struct ff_effect - - static int xpad_init_ff(struct usb_xpad *xpad) - { -- if (xpad->xtype == XTYPE_UNKNOWN) -+ if (xpad->xtype == XTYPE_UNKNOWN || xpad->xtype == XTYPE_XBOXONE) - return 0; - - input_set_capability(xpad->dev, EV_FF, FF_RUMBLE); -@@ -801,6 +914,14 @@ static int xpad_open(struct input_dev *dev) - if (usb_submit_urb(xpad->irq_in, GFP_KERNEL)) - return -EIO; - -+ if (xpad->xtype == XTYPE_XBOXONE) { -+ /* Xbox one controller needs to be initialized. */ -+ xpad->odata[0] = 0x05; -+ xpad->odata[1] = 0x20; -+ xpad->irq_out->transfer_buffer_length = 2; -+ return usb_submit_urb(xpad->irq_out, GFP_KERNEL); -+ } -+ - return 0; - } - -@@ -816,6 +937,7 @@ static void xpad_close(struct input_dev *dev) - - static void xpad_set_up_abs(struct input_dev *input_dev, signed short abs) - { -+ struct usb_xpad *xpad = input_get_drvdata(input_dev); - set_bit(abs, input_dev->absbit); - - switch (abs) { -@@ -827,7 +949,10 @@ static void xpad_set_up_abs(struct input_dev *input_dev, signed short abs) - break; - case ABS_Z: - case ABS_RZ: /* the triggers (if mapped to axes) */ -- input_set_abs_params(input_dev, abs, 0, 255, 0, 0); -+ if (xpad->xtype == XTYPE_XBOXONE) -+ input_set_abs_params(input_dev, abs, 0, 1023, 0, 0); -+ else -+ input_set_abs_params(input_dev, abs, 0, 255, 0, 0); - break; - case ABS_HAT0X: - case ABS_HAT0Y: /* the d-pad (only if dpad is mapped to axes */ -@@ -842,6 +967,7 @@ static int xpad_probe(struct usb_interface *intf, const struct usb_device_id *id - struct usb_xpad *xpad; - struct input_dev *input_dev; - struct usb_endpoint_descriptor *ep_irq_in; -+ int ep_irq_in_idx; - int i, error; - - for (i = 0; xpad_device[i].idVendor; i++) { -@@ -850,6 +976,16 @@ static int xpad_probe(struct usb_interface *intf, const struct usb_device_id *id - break; - } - -+ if (xpad_device[i].xtype == XTYPE_XBOXONE && -+ intf->cur_altsetting->desc.bInterfaceNumber != 0) { -+ /* -+ * The Xbox One controller lists three interfaces all with the -+ * same interface class, subclass and protocol. Differentiate by -+ * interface number. -+ */ -+ return -ENODEV; -+ } -+ - xpad = kzalloc(sizeof(struct usb_xpad), GFP_KERNEL); - input_dev = input_allocate_device(); - if (!xpad || !input_dev) { -@@ -920,7 +1056,8 @@ static int xpad_probe(struct usb_interface *intf, const struct usb_device_id *id - __set_bit(xpad_common_btn[i], input_dev->keybit); - - /* set up model-specific ones */ -- if (xpad->xtype == XTYPE_XBOX360 || xpad->xtype == XTYPE_XBOX360W) { -+ if (xpad->xtype == XTYPE_XBOX360 || xpad->xtype == XTYPE_XBOX360W || -+ xpad->xtype == XTYPE_XBOXONE) { - for (i = 0; xpad360_btn[i] >= 0; i++) - __set_bit(xpad360_btn[i], input_dev->keybit); - } else { -@@ -933,7 +1070,7 @@ static int xpad_probe(struct usb_interface *intf, const struct usb_device_id *id - __set_bit(xpad_btn_pad[i], input_dev->keybit); - } else { - for (i = 0; xpad_abs_pad[i] >= 0; i++) -- xpad_set_up_abs(input_dev, xpad_abs_pad[i]); -+ xpad_set_up_abs(input_dev, xpad_abs_pad[i]); - } - - if (xpad->mapping & MAP_TRIGGERS_TO_BUTTONS) { -@@ -956,7 +1093,10 @@ static int xpad_probe(struct usb_interface *intf, const struct usb_device_id *id - if (error) - goto fail5; - -- ep_irq_in = &intf->cur_altsetting->endpoint[0].desc; -+ /* Xbox One controller has in/out endpoints swapped. */ -+ ep_irq_in_idx = xpad->xtype == XTYPE_XBOXONE ? 1 : 0; -+ ep_irq_in = &intf->cur_altsetting->endpoint[ep_irq_in_idx].desc; -+ - usb_fill_int_urb(xpad->irq_in, udev, - usb_rcvintpipe(udev, ep_irq_in->bEndpointAddress), - xpad->idata, XPAD_PKT_LEN, xpad_irq_in, --- -cgit v0.10.1 - diff --git a/packages/linux/patches/3.16.5/linux-056-add_Adaptec_eHome_Infrared_Receiver.patch b/packages/linux/patches/3.16.5/linux-056-add_Adaptec_eHome_Infrared_Receiver.patch deleted file mode 100644 index a063ac1425..0000000000 --- a/packages/linux/patches/3.16.5/linux-056-add_Adaptec_eHome_Infrared_Receiver.patch +++ /dev/null @@ -1,21 +0,0 @@ -diff --git a/drivers/media/rc/mceusb.c b/drivers/media/rc/mceusb.c -index baa1203..fee1f95 100644 ---- a/drivers/media/rc/mceusb.c -+++ b/drivers/media/rc/mceusb.c -@@ -200,6 +200,7 @@ static bool debug; - #define VENDOR_CONEXANT 0x0572 - #define VENDOR_TWISTEDMELON 0x2596 - #define VENDOR_HAUPPAUGE 0x2040 -+#define VENDOR_ADAPTEC 0x03f3 - - enum mceusb_model_type { - MCE_GEN2 = 0, /* Most boards */ -@@ -414,6 +415,8 @@ static struct usb_device_id mceusb_dev_table[] = { - /* Hauppauge WINTV-HVR-HVR 930C-HD - based on cx231xx */ - { USB_DEVICE(VENDOR_HAUPPAUGE, 0xb130), - .driver_info = HAUPPAUGE_CX_HYBRID_TV }, -+ /* Adaptec / HP eHome Receiver */ -+ { USB_DEVICE(VENDOR_ADAPTEC, 0x0094) }, - /* Terminating entry */ - { } - }; diff --git a/packages/linux/patches/3.16.5/linux-224-geniatech-t220-dvb-t2-fix.patch b/packages/linux/patches/3.16.5/linux-224-geniatech-t220-dvb-t2-fix.patch deleted file mode 100644 index 17488409ff..0000000000 --- a/packages/linux/patches/3.16.5/linux-224-geniatech-t220-dvb-t2-fix.patch +++ /dev/null @@ -1,97 +0,0 @@ -diff --git a/drivers/media/dvb-frontends/cxd2820r.h b/drivers/media/dvb-frontends/cxd2820r.h -index 82b3d93..6095dbc 100644 ---- a/drivers/media/dvb-frontends/cxd2820r.h -+++ b/drivers/media/dvb-frontends/cxd2820r.h -@@ -52,6 +52,12 @@ struct cxd2820r_config { - */ - u8 ts_mode; - -+ /* TS clock inverted. -+ * Default: 0 -+ * Values: 0, 1 -+ */ -+ bool ts_clock_inv; -+ - /* IF AGC polarity. - * Default: 0 - * Values: 0, 1 -diff --git a/drivers/media/dvb-frontends/cxd2820r_c.c b/drivers/media/dvb-frontends/cxd2820r_c.c -index 5c6ab49..0f4657e 100644 ---- a/drivers/media/dvb-frontends/cxd2820r_c.c -+++ b/drivers/media/dvb-frontends/cxd2820r_c.c -@@ -45,6 +45,7 @@ int cxd2820r_set_frontend_c(struct dvb_frontend *fe) - { 0x1008b, 0x07, 0xff }, - { 0x1001f, priv->cfg.if_agc_polarity << 7, 0x80 }, - { 0x10070, priv->cfg.ts_mode, 0xff }, -+ { 0x10071, !priv->cfg.ts_clock_inv << 4, 0x10 }, - }; - - dev_dbg(&priv->i2c->dev, "%s: frequency=%d symbol_rate=%d\n", __func__, -diff --git a/drivers/media/dvb-frontends/cxd2820r_t.c b/drivers/media/dvb-frontends/cxd2820r_t.c -index fa184ca..9b5a45b 100644 ---- a/drivers/media/dvb-frontends/cxd2820r_t.c -+++ b/drivers/media/dvb-frontends/cxd2820r_t.c -@@ -46,6 +46,7 @@ int cxd2820r_set_frontend_t(struct dvb_frontend *fe) - { 0x00088, 0x01, 0xff }, - - { 0x00070, priv->cfg.ts_mode, 0xff }, -+ { 0x00071, !priv->cfg.ts_clock_inv << 4, 0x10 }, - { 0x000cb, priv->cfg.if_agc_polarity << 6, 0x40 }, - { 0x000a5, 0x00, 0x01 }, - { 0x00082, 0x20, 0x60 }, -diff --git a/drivers/media/dvb-frontends/cxd2820r_t2.c b/drivers/media/dvb-frontends/cxd2820r_t2.c -index 2ba130e..9c0c4f4 100644 ---- a/drivers/media/dvb-frontends/cxd2820r_t2.c -+++ b/drivers/media/dvb-frontends/cxd2820r_t2.c -@@ -47,6 +47,7 @@ int cxd2820r_set_frontend_t2(struct dvb_frontend *fe) - { 0x02083, 0x0a, 0xff }, - { 0x020cb, priv->cfg.if_agc_polarity << 6, 0x40 }, - { 0x02070, priv->cfg.ts_mode, 0xff }, -+ { 0x02071, !priv->cfg.ts_clock_inv << 6, 0x40 }, - { 0x020b5, priv->cfg.spec_inv << 4, 0x10 }, - { 0x02567, 0x07, 0x0f }, - { 0x02569, 0x03, 0x03 }, -diff --git a/drivers/media/usb/dvb-usb/dw2102.c b/drivers/media/usb/dvb-usb/dw2102.c -index ae0f56a..7135a3e 100644 ---- a/drivers/media/usb/dvb-usb/dw2102.c -+++ b/drivers/media/usb/dvb-usb/dw2102.c -@@ -1109,6 +1109,7 @@ static struct ds3000_config su3000_ds3000_config = { - static struct cxd2820r_config cxd2820r_config = { - .i2c_address = 0x6c, /* (0xd8 >> 1) */ - .ts_mode = 0x38, -+ .ts_clock_inv = 1, - }; - - static struct tda18271_config tda18271_config = { -@@ -1387,20 +1388,27 @@ static int su3000_frontend_attach(struct dvb_usb_adapter *d) - - static int t220_frontend_attach(struct dvb_usb_adapter *d) - { -- u8 obuf[3] = { 0xe, 0x80, 0 }; -+ u8 obuf[3] = { 0xe, 0x87, 0 }; - u8 ibuf[] = { 0 }; - - if (dvb_usb_generic_rw(d->dev, obuf, 3, ibuf, 1, 0) < 0) - err("command 0x0e transfer failed."); - - obuf[0] = 0xe; -- obuf[1] = 0x83; -+ obuf[1] = 0x86; -+ obuf[2] = 1; -+ -+ if (dvb_usb_generic_rw(d->dev, obuf, 3, ibuf, 1, 0) < 0) -+ err("command 0x0e transfer failed."); -+ -+ obuf[0] = 0xe; -+ obuf[1] = 0x80; - obuf[2] = 0; - - if (dvb_usb_generic_rw(d->dev, obuf, 3, ibuf, 1, 0) < 0) - err("command 0x0e transfer failed."); - -- msleep(100); -+ msleep(50); - - obuf[0] = 0xe; - obuf[1] = 0x80; - diff --git a/packages/linux/patches/3.16.5/linux-003-no_dev_console.patch b/packages/linux/patches/3.17.1/linux-003-no_dev_console.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-003-no_dev_console.patch rename to packages/linux/patches/3.17.1/linux-003-no_dev_console.patch diff --git a/packages/linux/patches/3.16.5/linux-051-ouya_controller_support.patch b/packages/linux/patches/3.17.1/linux-051-ouya_controller_support.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-051-ouya_controller_support.patch rename to packages/linux/patches/3.17.1/linux-051-ouya_controller_support.patch diff --git a/packages/linux/patches/3.16.5/linux-052-XBOX_remote_support.patch b/packages/linux/patches/3.17.1/linux-052-XBOX_remote_support.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-052-XBOX_remote_support.patch rename to packages/linux/patches/3.17.1/linux-052-XBOX_remote_support.patch diff --git a/packages/linux/patches/3.16.5/linux-053-spinelplus-remote-0.2.patch b/packages/linux/patches/3.17.1/linux-053-spinelplus-remote-0.2.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-053-spinelplus-remote-0.2.patch rename to packages/linux/patches/3.17.1/linux-053-spinelplus-remote-0.2.patch diff --git a/packages/linux/patches/3.16.5/linux-054-nuvoton_revert_d7b290a1056c5564eec8a1b169c6e84ff3.6.114c13.patch b/packages/linux/patches/3.17.1/linux-054-nuvoton_revert_d7b290a1056c5564eec8a1b169c6e84ff3.6.114c13.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-054-nuvoton_revert_d7b290a1056c5564eec8a1b169c6e84ff3.6.114c13.patch rename to packages/linux/patches/3.17.1/linux-054-nuvoton_revert_d7b290a1056c5564eec8a1b169c6e84ff3.6.114c13.patch diff --git a/packages/linux/patches/3.16.5/linux-055-add_Formosa_eHome_Infrared_Receiver.patch b/packages/linux/patches/3.17.1/linux-055-add_Formosa_eHome_Infrared_Receiver.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-055-add_Formosa_eHome_Infrared_Receiver.patch rename to packages/linux/patches/3.17.1/linux-055-add_Formosa_eHome_Infrared_Receiver.patch diff --git a/packages/linux/patches/3.17.1/linux-056-add_Adaptec_eHome_Infrared_Receiver.patch b/packages/linux/patches/3.17.1/linux-056-add_Adaptec_eHome_Infrared_Receiver.patch new file mode 100644 index 0000000000..4116b9ff86 --- /dev/null +++ b/packages/linux/patches/3.17.1/linux-056-add_Adaptec_eHome_Infrared_Receiver.patch @@ -0,0 +1,21 @@ +diff -Naur linux-3.17.1/drivers/media/rc/mceusb.c linux-3.17.1.patch/drivers/media/rc/mceusb.c +--- linux-3.17.1/drivers/media/rc/mceusb.c 2014-10-15 12:29:30.000000000 +0200 ++++ linux-3.17.1.patch/drivers/media/rc/mceusb.c 2014-10-16 11:45:57.480176874 +0200 +@@ -188,6 +188,8 @@ + #define VENDOR_TWISTEDMELON 0x2596 + #define VENDOR_HAUPPAUGE 0x2040 + #define VENDOR_PCTV 0x2013 ++#define VENDOR_ADAPTEC 0x03f3 ++ + + enum mceusb_model_type { + MCE_GEN2 = 0, /* Most boards */ +@@ -401,6 +403,8 @@ + .driver_info = HAUPPAUGE_CX_HYBRID_TV }, + { USB_DEVICE(VENDOR_PCTV, 0x025e), + .driver_info = HAUPPAUGE_CX_HYBRID_TV }, ++ /* Adaptec / HP eHome Receiver */ ++ { USB_DEVICE(VENDOR_ADAPTEC, 0x0094) }, + + /* Terminating entry */ + { } diff --git a/packages/linux/patches/3.16.5/linux-057-add_SMK_Manufacturing_Inc_Infrared_Receiver.patch b/packages/linux/patches/3.17.1/linux-057-add_SMK_Manufacturing_Inc_Infrared_Receiver.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-057-add_SMK_Manufacturing_Inc_Infrared_Receiver.patch rename to packages/linux/patches/3.17.1/linux-057-add_SMK_Manufacturing_Inc_Infrared_Receiver.patch diff --git a/packages/linux/patches/3.16.5/linux-058.05-hid_sony-add_autorepeat_for_PS3_remotes.patch b/packages/linux/patches/3.17.1/linux-058.05-hid_sony-add_autorepeat_for_PS3_remotes.patch similarity index 81% rename from packages/linux/patches/3.16.5/linux-058.05-hid_sony-add_autorepeat_for_PS3_remotes.patch rename to packages/linux/patches/3.17.1/linux-058.05-hid_sony-add_autorepeat_for_PS3_remotes.patch index 7a1499b1f7..6fa866dfe8 100644 --- a/packages/linux/patches/3.16.5/linux-058.05-hid_sony-add_autorepeat_for_PS3_remotes.patch +++ b/packages/linux/patches/3.17.1/linux-058.05-hid_sony-add_autorepeat_for_PS3_remotes.patch @@ -3,7 +3,7 @@ From: Stefan Saraev Date: Tue, 22 Apr 2014 16:05:14 +0300 Subject: [PATCH] [RFC] hid/sony: add autorepeat for PS3 remotes -adapted to 3.16 +adapted to 3.17 Betreff: [RFC] hid/sony: add autorepeat for PS3 remotes Von: David Dillow @@ -24,13 +24,10 @@ This compiled against the hid-sony driver with the PS3 remote changes merged, but I have done no testing of it. If the approach seems reasonable, I'll try to test it when the MythTV is idle. --- - drivers/hid/hid-sony.c | 20 ++++++++++++++++++++ - 1 files changed, 20 insertions(+), 0 deletions(-) - -diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c ---- a/drivers/hid/hid-sony.c -+++ b/drivers/hid/hid-sony.c -@@ -819,6 +819,24 @@ static int ps3remote_mapping(struct hid_ +diff -Naur linux-3.17.1/drivers/hid/hid-sony.c linux-3.17.1.patch/drivers/hid/hid-sony.c +--- linux-3.17.1/drivers/hid/hid-sony.c 2014-10-15 12:29:30.000000000 +0200 ++++ linux-3.17.1.patch/drivers/hid/hid-sony.c 2014-10-16 12:55:43.979181366 +0200 +@@ -875,6 +875,25 @@ return 1; } @@ -52,10 +49,11 @@ diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c + + return 0; +} - - /* Sony Vaio VGX has wrongly mouse pointer declared as constant */ ++ static __u8 *sony_report_fixup(struct hid_device *hdev, __u8 *rdesc, -@@ -1892,6 +1910,8 @@ static int sony_probe(struct hid_device + unsigned int *rsize) + { +@@ -1932,6 +1951,8 @@ goto err_stop; sony_init_work(sc, dualshock4_state_worker); @@ -64,6 +62,3 @@ diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c } else { ret = 0; } --- -1.7.2.5 - diff --git a/packages/linux/patches/3.16.5/linux-058.06-hid_sony-add_SMK_link.patch b/packages/linux/patches/3.17.1/linux-058.06-hid_sony-add_SMK_link.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-058.06-hid_sony-add_SMK_link.patch rename to packages/linux/patches/3.17.1/linux-058.06-hid_sony-add_SMK_link.patch diff --git a/packages/linux/patches/3.16.5/linux-059-remove_some_xpad_pids-0.2.patch b/packages/linux/patches/3.17.1/linux-059-remove_some_xpad_pids-0.2.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-059-remove_some_xpad_pids-0.2.patch rename to packages/linux/patches/3.17.1/linux-059-remove_some_xpad_pids-0.2.patch diff --git a/packages/linux/patches/3.16.5/linux-060-add_AUGUST_DVB-T205.patch b/packages/linux/patches/3.17.1/linux-060-add_AUGUST_DVB-T205.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-060-add_AUGUST_DVB-T205.patch rename to packages/linux/patches/3.17.1/linux-060-add_AUGUST_DVB-T205.patch diff --git a/packages/linux/patches/3.16.5/linux-062-imon_pad_ignore_diagonal.patch b/packages/linux/patches/3.17.1/linux-062-imon_pad_ignore_diagonal.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-062-imon_pad_ignore_diagonal.patch rename to packages/linux/patches/3.17.1/linux-062-imon_pad_ignore_diagonal.patch diff --git a/packages/linux/patches/3.16.5/linux-203-stb0899_enable_low_symbol_rate.patch b/packages/linux/patches/3.17.1/linux-203-stb0899_enable_low_symbol_rate.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-203-stb0899_enable_low_symbol_rate.patch rename to packages/linux/patches/3.17.1/linux-203-stb0899_enable_low_symbol_rate.patch diff --git a/packages/linux/patches/3.16.5/linux-210-dvbsky.patch b/packages/linux/patches/3.17.1/linux-210-dvbsky.patch similarity index 97% rename from packages/linux/patches/3.16.5/linux-210-dvbsky.patch rename to packages/linux/patches/3.17.1/linux-210-dvbsky.patch index 7102fc318b..2e635d2f74 100644 --- a/packages/linux/patches/3.16.5/linux-210-dvbsky.patch +++ b/packages/linux/patches/3.17.1/linux-210-dvbsky.patch @@ -1,8 +1,49 @@ +From 36a453623c141f69f5f72337e0d0180dbc19b014 Mon Sep 17 00:00:00 2001 +From: Stefan Saraev +Date: Mon, 6 Oct 2014 12:39:47 +0300 +Subject: [PATCH] dvbsky + +--- + drivers/media/dvb-frontends/Kconfig | 14 + + drivers/media/dvb-frontends/Makefile | 3 +- + drivers/media/dvb-frontends/dvbsky_m88dc2800.c | 2124 ++++++++++++++++++++ + drivers/media/dvb-frontends/dvbsky_m88dc2800.h | 44 + + drivers/media/dvb-frontends/dvbsky_m88ds3103.c | 1707 ++++++++++++++++ + drivers/media/dvb-frontends/dvbsky_m88ds3103.h | 53 + + .../media/dvb-frontends/dvbsky_m88ds3103_priv.h | 403 ++++ + drivers/media/pci/cx23885/Kconfig | 2 + + drivers/media/pci/cx23885/cimax2.c | 23 +- + drivers/media/pci/cx23885/cimax2.h | 4 +- + drivers/media/pci/cx23885/cx23885-cards.c | 182 ++ + drivers/media/pci/cx23885/cx23885-core.c | 6 + + drivers/media/pci/cx23885/cx23885-dvb.c | 179 ++- + drivers/media/pci/cx23885/cx23885-input.c | 24 + + drivers/media/pci/cx23885/cx23885.h | 10 +- + drivers/media/pci/cx88/Kconfig | 1 + + drivers/media/pci/cx88/cx88-cards.c | 22 + + drivers/media/pci/cx88/cx88-dvb.c | 85 + + drivers/media/pci/cx88/cx88-input.c | 4 + + drivers/media/pci/cx88/cx88.h | 1 + + drivers/media/rc/keymaps/Makefile | 1 + + drivers/media/rc/keymaps/rc-dvbsky.c | 78 + + drivers/media/usb/dvb-usb-v2/Kconfig | 6 + + drivers/media/usb/dvb-usb-v2/Makefile | 3 + + drivers/media/usb/dvb-usb-v2/dvbsky.c | 739 +++++++ + include/media/rc-map.h | 1 + + 26 files changed, 5714 insertions(+), 5 deletions(-) + create mode 100644 drivers/media/dvb-frontends/dvbsky_m88dc2800.c + create mode 100644 drivers/media/dvb-frontends/dvbsky_m88dc2800.h + create mode 100644 drivers/media/dvb-frontends/dvbsky_m88ds3103.c + create mode 100644 drivers/media/dvb-frontends/dvbsky_m88ds3103.h + create mode 100644 drivers/media/dvb-frontends/dvbsky_m88ds3103_priv.h + create mode 100644 drivers/media/rc/keymaps/rc-dvbsky.c + create mode 100644 drivers/media/usb/dvb-usb-v2/dvbsky.c + diff --git a/drivers/media/dvb-frontends/Kconfig b/drivers/media/dvb-frontends/Kconfig -index 49db718..6ddcfc9 100644 +index 8587675..b78ad4b 100644 --- a/drivers/media/dvb-frontends/Kconfig +++ b/drivers/media/dvb-frontends/Kconfig -@@ -248,6 +248,20 @@ config DVB_CX24117 +@@ -230,6 +230,20 @@ config DVB_CX24117 help A Dual DVB-S/S2 tuner module. Say Y when you want to support this frontend. @@ -24,11 +65,11 @@ index 49db718..6ddcfc9 100644 tristate "Silicon Labs SI21XX based" depends on DVB_CORE && I2C diff --git a/drivers/media/dvb-frontends/Makefile b/drivers/media/dvb-frontends/Makefile -index 9b21488..edaae0d 100644 +index 4629ee8..941b247 100644 --- a/drivers/media/dvb-frontends/Makefile +++ b/drivers/media/dvb-frontends/Makefile -@@ -112,4 +112,5 @@ obj-$(CONFIG_DVB_RTL2830) += rtl2830.o - obj-$(CONFIG_DVB_RTL2832) += rtl2832.o +@@ -117,4 +117,5 @@ obj-$(CONFIG_DVB_RTL2832) += rtl2832.o + obj-$(CONFIG_DVB_RTL2832_SDR) += rtl2832_sdr.o obj-$(CONFIG_DVB_M88RS2000) += m88rs2000.o obj-$(CONFIG_DVB_AF9033) += af9033.o - @@ -4396,7 +4437,7 @@ index 0000000..dfb3f8b + +#endif /* dvbsky_m88ds3103_PRIV_H */ diff --git a/drivers/media/pci/cx23885/Kconfig b/drivers/media/pci/cx23885/Kconfig -index d1dcb1d..a5fbc89 100644 +index e12c006..7b769f7 100644 --- a/drivers/media/pci/cx23885/Kconfig +++ b/drivers/media/pci/cx23885/Kconfig @@ -23,6 +23,8 @@ config VIDEO_CX23885 @@ -4469,7 +4510,7 @@ index 518744a..39f3db7 100644 + #endif diff --git a/drivers/media/pci/cx23885/cx23885-cards.c b/drivers/media/pci/cx23885/cx23885-cards.c -index 79f20c8..cb00710 100644 +index c2b6080..51b8b56 100644 --- a/drivers/media/pci/cx23885/cx23885-cards.c +++ b/drivers/media/pci/cx23885/cx23885-cards.c @@ -613,6 +613,34 @@ struct cx23885_board cx23885_boards[] = { @@ -4507,7 +4548,7 @@ index 79f20c8..cb00710 100644 [CX23885_BOARD_PROF_8000] = { .name = "Prof Revolution DVB-S2 8000", .portb = CX23885_MPEG_DVB, -@@ -874,6 +902,30 @@ struct cx23885_subid cx23885_subids[] = { +@@ -903,6 +931,30 @@ struct cx23885_subid cx23885_subids[] = { .subdevice = 0x9022, .card = CX23885_BOARD_TEVII_S471, }, { @@ -4538,7 +4579,7 @@ index 79f20c8..cb00710 100644 .subvendor = 0x8000, .subdevice = 0x3034, .card = CX23885_BOARD_PROF_8000, -@@ -1483,9 +1535,84 @@ void cx23885_gpio_setup(struct cx23885_dev *dev) +@@ -1528,9 +1580,84 @@ void cx23885_gpio_setup(struct cx23885_dev *dev) cx_set(GP0_IO, 0x00040004); mdelay(60); break; @@ -4623,7 +4664,7 @@ index 79f20c8..cb00710 100644 int cx23885_ir_init(struct cx23885_dev *dev) { static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = { -@@ -1573,6 +1700,23 @@ int cx23885_ir_init(struct cx23885_dev *dev) +@@ -1618,6 +1745,23 @@ int cx23885_ir_init(struct cx23885_dev *dev) v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config, ir_rx_pin_cfg_count, ir_rx_pin_cfg); break; @@ -4647,7 +4688,7 @@ index 79f20c8..cb00710 100644 case CX23885_BOARD_HAUPPAUGE_HVR1250: if (!enable_885_ir) break; -@@ -1602,6 +1746,12 @@ void cx23885_ir_fini(struct cx23885_dev *dev) +@@ -1648,6 +1792,12 @@ void cx23885_ir_fini(struct cx23885_dev *dev) cx23888_ir_remove(dev); dev->sd_ir = NULL; break; @@ -4660,7 +4701,7 @@ index 79f20c8..cb00710 100644 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: case CX23885_BOARD_TEVII_S470: case CX23885_BOARD_HAUPPAUGE_HVR1250: -@@ -1649,6 +1799,12 @@ void cx23885_ir_pci_int_enable(struct cx23885_dev *dev) +@@ -1695,6 +1845,12 @@ void cx23885_ir_pci_int_enable(struct cx23885_dev *dev) if (dev->sd_ir) cx23885_irq_add_enable(dev, PCI_MSK_IR); break; @@ -4673,7 +4714,7 @@ index 79f20c8..cb00710 100644 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: case CX23885_BOARD_TEVII_S470: case CX23885_BOARD_HAUPPAUGE_HVR1250: -@@ -1752,6 +1908,10 @@ void cx23885_card_setup(struct cx23885_dev *dev) +@@ -1800,6 +1956,10 @@ void cx23885_card_setup(struct cx23885_dev *dev) ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; break; @@ -4684,9 +4725,9 @@ index 79f20c8..cb00710 100644 case CX23885_BOARD_TEVII_S470: case CX23885_BOARD_TEVII_S471: case CX23885_BOARD_DVBWORLD_2005: -@@ -1800,6 +1960,22 @@ void cx23885_card_setup(struct cx23885_dev *dev) - ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ - ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; +@@ -1851,6 +2011,22 @@ void cx23885_card_setup(struct cx23885_dev *dev) + ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ + ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; break; + case CX23885_BOARD_DVBSKY_S952: + ts1->gen_ctrl_val = 0x5; /* Parallel */ @@ -4707,7 +4748,7 @@ index 79f20c8..cb00710 100644 case CX23885_BOARD_HAUPPAUGE_HVR1250: case CX23885_BOARD_HAUPPAUGE_HVR1500: case CX23885_BOARD_HAUPPAUGE_HVR1500Q: -@@ -1857,6 +2033,12 @@ void cx23885_card_setup(struct cx23885_dev *dev) +@@ -1910,6 +2086,12 @@ void cx23885_card_setup(struct cx23885_dev *dev) case CX23885_BOARD_MPX885: case CX23885_BOARD_MYGICA_X8507: case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: @@ -4745,10 +4786,10 @@ index edcd79d..4b57eef 100644 break; } diff --git a/drivers/media/pci/cx23885/cx23885-dvb.c b/drivers/media/pci/cx23885/cx23885-dvb.c -index 0549205..201523a 100644 +index 968fecc..966e1d0 100644 --- a/drivers/media/pci/cx23885/cx23885-dvb.c +++ b/drivers/media/pci/cx23885/cx23885-dvb.c -@@ -52,6 +52,8 @@ +@@ -53,6 +53,8 @@ #include "lnbh24.h" #include "cx24116.h" #include "cx24117.h" @@ -4757,7 +4798,7 @@ index 0549205..201523a 100644 #include "cimax2.h" #include "lgs8gxx.h" #include "netup-eeprom.h" -@@ -507,6 +509,93 @@ static struct xc5000_config mygica_x8507_xc5000_config = { +@@ -515,6 +517,93 @@ static struct xc5000_config mygica_x8507_xc5000_config = { .if_khz = 4000, }; @@ -4851,7 +4892,7 @@ index 0549205..201523a 100644 static struct stv090x_config prof_8000_stv090x_config = { .device = STV0903, .demod_mode = STV090x_SINGLE, -@@ -1311,6 +1400,57 @@ static int dvb_register(struct cx23885_tsport *port) +@@ -1452,6 +1541,57 @@ static int dvb_register(struct cx23885_tsport *port) &tevii_ts2020_config, &i2c_bus->i2c_adap); } break; @@ -4909,7 +4950,7 @@ index 0549205..201523a 100644 case CX23885_BOARD_PROF_8000: i2c_bus = &dev->i2c_bus[0]; -@@ -1386,7 +1526,7 @@ static int dvb_register(struct cx23885_tsport *port) +@@ -1548,7 +1688,7 @@ static int dvb_register(struct cx23885_tsport *port) printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n", port->nr, port->frontends.adapter.proposed_mac); @@ -4918,7 +4959,7 @@ index 0549205..201523a 100644 break; } case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: { -@@ -1413,6 +1553,41 @@ static int dvb_register(struct cx23885_tsport *port) +@@ -1575,6 +1715,41 @@ static int dvb_register(struct cx23885_tsport *port) memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6); break; } @@ -4960,7 +5001,7 @@ index 0549205..201523a 100644 } return ret; -@@ -1495,6 +1670,8 @@ int cx23885_dvb_unregister(struct cx23885_tsport *port) +@@ -1657,6 +1832,8 @@ int cx23885_dvb_unregister(struct cx23885_tsport *port) switch (port->dev->board) { case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: @@ -4970,7 +5011,7 @@ index 0549205..201523a 100644 break; case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: diff --git a/drivers/media/pci/cx23885/cx23885-input.c b/drivers/media/pci/cx23885/cx23885-input.c -index 8a49e7c..a5e4639 100644 +index 1940c18..af20f25 100644 --- a/drivers/media/pci/cx23885/cx23885-input.c +++ b/drivers/media/pci/cx23885/cx23885-input.c @@ -89,6 +89,12 @@ void cx23885_input_rx_work_handler(struct cx23885_dev *dev, u32 events) @@ -5019,14 +5060,14 @@ index 8a49e7c..a5e4639 100644 /* Integrated CX23885 IR controller */ driver_type = RC_DRIVER_IR_RAW; diff --git a/drivers/media/pci/cx23885/cx23885.h b/drivers/media/pci/cx23885/cx23885.h -index 0fa4048..7084a4e 100644 +index 0e086c0..f870b83 100644 --- a/drivers/media/pci/cx23885/cx23885.h +++ b/drivers/media/pci/cx23885/cx23885.h -@@ -97,6 +97,14 @@ - #define CX23885_BOARD_TBS_6980 41 - #define CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200 42 +@@ -99,6 +99,14 @@ + #define CX23885_BOARD_HAUPPAUGE_IMPACTVCBE 43 + #define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2 44 -+#define CX23885_BOARD_BASE_INDEX 43 ++#define CX23885_BOARD_BASE_INDEX 45 +#define CX23885_BOARD_BST_PS8512 (CX23885_BOARD_BASE_INDEX) +#define CX23885_BOARD_DVBSKY_S952 (CX23885_BOARD_BASE_INDEX+1) +#define CX23885_BOARD_DVBSKY_S950 (CX23885_BOARD_BASE_INDEX+2) @@ -5037,7 +5078,7 @@ index 0fa4048..7084a4e 100644 #define GPIO_0 0x00000001 #define GPIO_1 0x00000002 #define GPIO_2 0x00000004 -@@ -234,7 +242,7 @@ struct cx23885_board { +@@ -236,7 +244,7 @@ struct cx23885_board { */ u32 clk_freq; struct cx23885_input input[MAX_CX23885_INPUT]; @@ -5223,11 +5264,11 @@ index 053ed1b..955b916 100644 case CX88_BOARD_TBS_8920: case CX88_BOARD_PROF_7300: diff --git a/drivers/media/pci/cx88/cx88-input.c b/drivers/media/pci/cx88/cx88-input.c -index f29e18c..42a911c 100644 +index 3f1342c..2d1fd27 100644 --- a/drivers/media/pci/cx88/cx88-input.c +++ b/drivers/media/pci/cx88/cx88-input.c -@@ -419,6 +419,10 @@ int cx88_ir_init(struct cx88_core *core, struct pci_dev *pci) - rc_type = RC_BIT_NEC; +@@ -435,6 +435,10 @@ int cx88_ir_init(struct cx88_core *core, struct pci_dev *pci) + ir_codes = RC_MAP_TWINHAN_VP1027_DVBS; ir->sampling = 0xff00; /* address */ break; + case CX88_BOARD_BST_PS8312: @@ -5346,10 +5387,10 @@ index 0000000..bfc41fb +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Nibble Max "); diff --git a/drivers/media/usb/dvb-usb-v2/Kconfig b/drivers/media/usb/dvb-usb-v2/Kconfig -index 2059d0c..24a4ec2 100644 +index 66645b0..e2f282b 100644 --- a/drivers/media/usb/dvb-usb-v2/Kconfig +++ b/drivers/media/usb/dvb-usb-v2/Kconfig -@@ -147,3 +147,9 @@ config DVB_USB_RTL28XXU +@@ -141,3 +141,9 @@ config DVB_USB_RTL28XXU help Say Y here to support the Realtek RTL28xxU DVB USB receiver. @@ -5360,10 +5401,10 @@ index 2059d0c..24a4ec2 100644 + help + Say Y here to support the USB receivers from DVBSky. diff --git a/drivers/media/usb/dvb-usb-v2/Makefile b/drivers/media/usb/dvb-usb-v2/Makefile -index 2c06714..926f12d 100644 +index bc38f03..f10d4df 100644 --- a/drivers/media/usb/dvb-usb-v2/Makefile +++ b/drivers/media/usb/dvb-usb-v2/Makefile -@@ -40,6 +40,9 @@ obj-$(CONFIG_DVB_USB_MXL111SF) += mxl111sf-tuner.o +@@ -37,6 +37,9 @@ obj-$(CONFIG_DVB_USB_MXL111SF) += mxl111sf-tuner.o dvb-usb-rtl28xxu-objs := rtl28xxu.o obj-$(CONFIG_DVB_USB_RTL28XXU) += dvb-usb-rtl28xxu.o @@ -5858,7 +5899,7 @@ index 0000000..9033d92 + dprintk("rc code: %x", code); + toggle = (code & 0x800) ? 1 : 0; + code &= 0x3f; -+ rc_keydown(d->rc_dev, code, toggle); ++ rc_keydown(d->rc_dev, RC_TYPE_UNKNOWN, code, toggle); + } + return 0; +} @@ -6119,10 +6160,10 @@ index 0000000..9033d92 +MODULE_DESCRIPTION("Driver for DVBSky USB2.0"); +MODULE_LICENSE("GPL"); diff --git a/include/media/rc-map.h b/include/media/rc-map.h -index a20ed97..73f8c92 100644 +index 80f9518..e7a1514 100644 --- a/include/media/rc-map.h +++ b/include/media/rc-map.h -@@ -119,6 +119,7 @@ void rc_map_init(void); +@@ -135,6 +135,7 @@ void rc_map_init(void); #define RC_MAP_DM1105_NEC "rc-dm1105-nec" #define RC_MAP_DNTV_LIVE_DVBT_PRO "rc-dntv-live-dvbt-pro" #define RC_MAP_DNTV_LIVE_DVB_T "rc-dntv-live-dvb-t" @@ -6130,3 +6171,6 @@ index a20ed97..73f8c92 100644 #define RC_MAP_EMPTY "rc-empty" #define RC_MAP_EM_TERRATEC "rc-em-terratec" #define RC_MAP_ENCORE_ENLTV2 "rc-encore-enltv2" +-- +1.7.2.5 + diff --git a/packages/linux/patches/3.16.5/linux-211-dvbsky-s950v3-s952v3.patch b/packages/linux/patches/3.17.1/linux-211-dvbsky-s950v3-s952v3.patch similarity index 99% rename from packages/linux/patches/3.16.5/linux-211-dvbsky-s950v3-s952v3.patch rename to packages/linux/patches/3.17.1/linux-211-dvbsky-s950v3-s952v3.patch index 9505198ab9..6be7dd609d 100644 --- a/packages/linux/patches/3.16.5/linux-211-dvbsky-s950v3-s952v3.patch +++ b/packages/linux/patches/3.17.1/linux-211-dvbsky-s950v3-s952v3.patch @@ -2267,7 +2267,7 @@ index 0000000..f4777f2 + rc5_system = (dwIRCode & 0x7C0) >> 6; + toggle = (dwIRCode & 0x800) ? 1 : 0; + scancode = rc5_system << 8 | rc5_command; -+ rc_keydown(rc_dev, scancode, toggle); ++ rc_keydown(rc_dev, RC_TYPE_UNKNOWN, scancode, toggle); + } + + /* diff --git a/packages/linux/patches/3.16.5/linux-212-mantis_stb0899_faster_lock.patch b/packages/linux/patches/3.17.1/linux-212-mantis_stb0899_faster_lock.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-212-mantis_stb0899_faster_lock.patch rename to packages/linux/patches/3.17.1/linux-212-mantis_stb0899_faster_lock.patch diff --git a/packages/linux/patches/3.16.5/linux-221-ngene-octopus.patch b/packages/linux/patches/3.17.1/linux-221-ngene-octopus.patch similarity index 98% rename from packages/linux/patches/3.16.5/linux-221-ngene-octopus.patch rename to packages/linux/patches/3.17.1/linux-221-ngene-octopus.patch index 9f050f501a..4cf1add609 100644 --- a/packages/linux/patches/3.16.5/linux-221-ngene-octopus.patch +++ b/packages/linux/patches/3.17.1/linux-221-ngene-octopus.patch @@ -1,6 +1,6 @@ -From e5d98e8b261526ab41234b2fbc090c99bd009631 Mon Sep 17 00:00:00 2001 +From 8bd7907427f0153920b81e615b08e9f6e9c9ee40 Mon Sep 17 00:00:00 2001 From: Stefan Saraev -Date: Thu, 22 May 2014 20:00:40 +0300 +Date: Mon, 6 Oct 2014 13:42:00 +0300 Subject: [PATCH] dvb: ngene/octopus source: http://linuxtv.org/hg/~endriss/media_build_experimental/ @@ -31,11 +31,11 @@ note: SYS_DVBC2 not added. ci extensions (en50221) not added. drivers/media/dvb-frontends/stv6111.h | 5 + drivers/media/dvb-frontends/tda18212dd.c | 974 +++++++ drivers/media/dvb-frontends/tda18212dd.h | 5 + - drivers/media/dvb-frontends/tda18271c2dd.c | 15 +- + drivers/media/dvb-frontends/tda18271c2dd.c | 17 +- drivers/media/dvb-frontends/tda18271c2dd.h | 6 +- drivers/media/pci/ddbridge/Kconfig | 11 +- drivers/media/pci/ddbridge/Makefile | 2 - - drivers/media/pci/ddbridge/ddbridge-core.c | 3707 ++++++++++++++++++------ + drivers/media/pci/ddbridge/ddbridge-core.c | 3718 ++++++++++++++++++------ drivers/media/pci/ddbridge/ddbridge-i2c.c | 257 ++ drivers/media/pci/ddbridge/ddbridge-i2c.h | 105 + drivers/media/pci/ddbridge/ddbridge-mod.c | 1131 ++++++++ @@ -48,14 +48,14 @@ note: SYS_DVBC2 not added. ci extensions (en50221) not added. drivers/media/pci/ngene/Makefile | 3 +- drivers/media/pci/ngene/ngene-av.c | 348 +++ drivers/media/pci/ngene/ngene-cards.c | 778 +++-- - drivers/media/pci/ngene/ngene-core.c | 382 ++- + drivers/media/pci/ngene/ngene-core.c | 396 ++- drivers/media/pci/ngene/ngene-dvb.c | 372 +++ drivers/media/pci/ngene/ngene-eeprom.c | 284 ++ drivers/media/pci/ngene/ngene-i2c.c | 113 + drivers/media/pci/ngene/ngene.h | 40 + include/uapi/linux/dvb/mod.h | 22 + include/uapi/linux/dvb/ns.h | 68 + - 48 files changed, 25191 insertions(+), 3431 deletions(-) + 48 files changed, 25183 insertions(+), 3466 deletions(-) create mode 100644 drivers/media/dvb-core/dvb_netstream.c create mode 100644 drivers/media/dvb-core/dvb_netstream.h create mode 100644 drivers/media/dvb-frontends/cxd2843.c @@ -517,7 +517,7 @@ index 983db75..a813389 100644 static int dvb_uevent(struct device *dev, struct kobj_uevent_env *env) { diff --git a/drivers/media/dvb-core/dvbdev.h b/drivers/media/dvb-core/dvbdev.h -index 93a9470..e534ef1 100644 +index f96b28e..f901b54 100644 --- a/drivers/media/dvb-core/dvbdev.h +++ b/drivers/media/dvb-core/dvbdev.h @@ -47,6 +47,10 @@ @@ -532,12 +532,12 @@ index 93a9470..e534ef1 100644 #define DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr) \ static short adapter_nr[] = \ diff --git a/drivers/media/dvb-frontends/Kconfig b/drivers/media/dvb-frontends/Kconfig -index 025fc54..a080569 100644 +index fe0ddcc..b0be45b 100644 --- a/drivers/media/dvb-frontends/Kconfig +++ b/drivers/media/dvb-frontends/Kconfig -@@ -63,6 +63,33 @@ config DVB_TDA18271C2DD +@@ -72,6 +72,33 @@ config DVB_SI2165 - Say Y when you want to support this tuner. + Say Y when you want to support this frontend. +config DVB_STV0367DD + tristate "STV 0367 (DD)" @@ -570,13 +570,13 @@ index 025fc54..a080569 100644 depends on DVB_CORE diff --git a/drivers/media/dvb-frontends/Makefile b/drivers/media/dvb-frontends/Makefile -index 282aba2..fac3f5f 100644 +index edf103d..912ac69 100644 --- a/drivers/media/dvb-frontends/Makefile +++ b/drivers/media/dvb-frontends/Makefile -@@ -99,6 +99,9 @@ obj-$(CONFIG_DVB_STV0367) += stv0367.o - obj-$(CONFIG_DVB_CXD2820R) += cxd2820r.o +@@ -106,6 +106,9 @@ obj-$(CONFIG_DVB_CXD2820R) += cxd2820r.o obj-$(CONFIG_DVB_DRXK) += drxk.o obj-$(CONFIG_DVB_TDA18271C2DD) += tda18271c2dd.o + obj-$(CONFIG_DVB_SI2165) += si2165.o +obj-$(CONFIG_DVB_STV0367DD) += stv0367dd.o +obj-$(CONFIG_DVB_TDA18212DD) += tda18212dd.o +obj-$(CONFIG_DVB_CXD2843) += cxd2843.o @@ -9715,2337 +9715,2337 @@ index 0000000..64f7970 --- /dev/null +++ b/drivers/media/dvb-frontends/stv0367dd.c @@ -0,0 +1,2331 @@ -+/* -+ * stv0367dd: STV0367 DVB-C/T demodulator driver -+ * -+ * Copyright (C) 2011 Digital Devices GmbH -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 only, as published by the Free Software Foundation. -+ * -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA -+ * 02110-1301, USA -+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "dvb_frontend.h" -+#include "stv0367dd.h" -+#include "stv0367dd_regs.h" -+ -+enum omode { OM_NONE, OM_DVBT, OM_DVBC, OM_QAM_ITU_C }; -+enum { QAM_MOD_QAM4 = 0, -+ QAM_MOD_QAM16, -+ QAM_MOD_QAM32, -+ QAM_MOD_QAM64, -+ QAM_MOD_QAM128, -+ QAM_MOD_QAM256, -+ QAM_MOD_QAM512, -+ QAM_MOD_QAM1024 -+}; -+ -+enum {QAM_SPECT_NORMAL, QAM_SPECT_INVERTED }; -+ -+enum { -+ QAM_FEC_A = 1, /* J83 Annex A */ -+ QAM_FEC_B = (1<<1), /* J83 Annex B */ -+ QAM_FEC_C = (1<<2) /* J83 Annex C */ -+}; -+ -+enum EDemodState { Off, QAMSet, OFDMSet, QAMStarted, OFDMStarted }; -+ -+struct stv_state { -+#ifdef USE_API3 -+ struct dvb_frontend c_frontend; -+ struct dvb_frontend t_frontend; -+#else -+ struct dvb_frontend frontend; -+#endif -+ fe_modulation_t modulation; -+ u32 symbol_rate; -+ u32 bandwidth; -+ struct device *dev; -+ -+ struct i2c_adapter *i2c; -+ u8 adr; -+ void *priv; -+ -+ struct mutex mutex; -+ struct mutex ctlock; -+ -+ u32 master_clock; -+ u32 adc_clock; -+ u8 ID; -+ u8 I2CRPT; -+ u32 omode; -+ u8 qam_inversion; -+ -+ s32 IF; -+ -+ s32 m_FECTimeOut; -+ s32 m_DemodTimeOut; -+ s32 m_SignalTimeOut; -+ s32 m_DemodLockTime; -+ s32 m_FFTTimeOut; -+ s32 m_TSTimeOut; -+ -+ bool m_bFirstTimeLock; -+ -+ u8 m_Save_QAM_AGC_CTL; -+ -+ enum EDemodState demod_state; -+ -+ u8 m_OFDM_FFTMode; // 0 = 2k, 1 = 8k, 2 = 4k -+ u8 m_OFDM_Modulation; // -+ u8 m_OFDM_FEC; // -+ u8 m_OFDM_Guard; -+ -+ u32 ucblocks; -+ u32 ber; -+}; -+ -+struct init_table { -+ u16 adr; -+ u8 data; -+}; -+ -+struct init_table base_init[] = { -+ { R367_IOCFG0, 0x80 }, -+ { R367_DAC0R, 0x00 }, -+ { R367_IOCFG1, 0x00 }, -+ { R367_DAC1R, 0x00 }, -+ { R367_IOCFG2, 0x00 }, -+ { R367_SDFR, 0x00 }, -+ { R367_AUX_CLK, 0x00 }, -+ { R367_FREESYS1, 0x00 }, -+ { R367_FREESYS2, 0x00 }, -+ { R367_FREESYS3, 0x00 }, -+ { R367_GPIO_CFG, 0x55 }, -+ { R367_GPIO_CMD, 0x01 }, -+ { R367_TSTRES, 0x00 }, -+ { R367_ANACTRL, 0x00 }, -+ { R367_TSTBUS, 0x00 }, -+ { R367_RF_AGC2, 0x20 }, -+ { R367_ANADIGCTRL, 0x0b }, -+ { R367_PLLMDIV, 0x01 }, -+ { R367_PLLNDIV, 0x08 }, -+ { R367_PLLSETUP, 0x18 }, -+ { R367_DUAL_AD12, 0x04 }, -+ { R367_TSTBIST, 0x00 }, -+ { 0x0000, 0x00 } -+}; -+ -+struct init_table qam_init[] = { -+ { R367_QAM_CTRL_1, 0x06 },// Orginal 0x04 -+ { R367_QAM_CTRL_2, 0x03 }, -+ { R367_QAM_IT_STATUS1, 0x2b }, -+ { R367_QAM_IT_STATUS2, 0x08 }, -+ { R367_QAM_IT_EN1, 0x00 }, -+ { R367_QAM_IT_EN2, 0x00 }, -+ { R367_QAM_CTRL_STATUS, 0x04 }, -+ { R367_QAM_TEST_CTL, 0x00 }, -+ { R367_QAM_AGC_CTL, 0x73 }, -+ { R367_QAM_AGC_IF_CFG, 0x50 }, -+ { R367_QAM_AGC_RF_CFG, 0x02 },// RF Freeze -+ { R367_QAM_AGC_PWM_CFG, 0x03 }, -+ { R367_QAM_AGC_PWR_REF_L, 0x5a }, -+ { R367_QAM_AGC_PWR_REF_H, 0x00 }, -+ { R367_QAM_AGC_RF_TH_L, 0xff }, -+ { R367_QAM_AGC_RF_TH_H, 0x07 }, -+ { R367_QAM_AGC_IF_LTH_L, 0x00 }, -+ { R367_QAM_AGC_IF_LTH_H, 0x08 }, -+ { R367_QAM_AGC_IF_HTH_L, 0xff }, -+ { R367_QAM_AGC_IF_HTH_H, 0x07 }, -+ { R367_QAM_AGC_PWR_RD_L, 0xa0 }, -+ { R367_QAM_AGC_PWR_RD_M, 0xe9 }, -+ { R367_QAM_AGC_PWR_RD_H, 0x03 }, -+ { R367_QAM_AGC_PWM_IFCMD_L, 0xe4 }, -+ { R367_QAM_AGC_PWM_IFCMD_H, 0x00 }, -+ { R367_QAM_AGC_PWM_RFCMD_L, 0xff }, -+ { R367_QAM_AGC_PWM_RFCMD_H, 0x07 }, -+ { R367_QAM_IQDEM_CFG, 0x01 }, -+ { R367_QAM_MIX_NCO_LL, 0x22 }, -+ { R367_QAM_MIX_NCO_HL, 0x96 }, -+ { R367_QAM_MIX_NCO_HH, 0x55 }, -+ { R367_QAM_SRC_NCO_LL, 0xff }, -+ { R367_QAM_SRC_NCO_LH, 0x0c }, -+ { R367_QAM_SRC_NCO_HL, 0xf5 }, -+ { R367_QAM_SRC_NCO_HH, 0x20 }, -+ { R367_QAM_IQDEM_GAIN_SRC_L, 0x06 }, -+ { R367_QAM_IQDEM_GAIN_SRC_H, 0x01 }, -+ { R367_QAM_IQDEM_DCRM_CFG_LL, 0xfe }, -+ { R367_QAM_IQDEM_DCRM_CFG_LH, 0xff }, -+ { R367_QAM_IQDEM_DCRM_CFG_HL, 0x0f }, -+ { R367_QAM_IQDEM_DCRM_CFG_HH, 0x00 }, -+ { R367_QAM_IQDEM_ADJ_COEFF0, 0x34 }, -+ { R367_QAM_IQDEM_ADJ_COEFF1, 0xae }, -+ { R367_QAM_IQDEM_ADJ_COEFF2, 0x46 }, -+ { R367_QAM_IQDEM_ADJ_COEFF3, 0x77 }, -+ { R367_QAM_IQDEM_ADJ_COEFF4, 0x96 }, -+ { R367_QAM_IQDEM_ADJ_COEFF5, 0x69 }, -+ { R367_QAM_IQDEM_ADJ_COEFF6, 0xc7 }, -+ { R367_QAM_IQDEM_ADJ_COEFF7, 0x01 }, -+ { R367_QAM_IQDEM_ADJ_EN, 0x04 }, -+ { R367_QAM_IQDEM_ADJ_AGC_REF, 0x94 }, -+ { R367_QAM_ALLPASSFILT1, 0xc9 }, -+ { R367_QAM_ALLPASSFILT2, 0x2d }, -+ { R367_QAM_ALLPASSFILT3, 0xa3 }, -+ { R367_QAM_ALLPASSFILT4, 0xfb }, -+ { R367_QAM_ALLPASSFILT5, 0xf6 }, -+ { R367_QAM_ALLPASSFILT6, 0x45 }, -+ { R367_QAM_ALLPASSFILT7, 0x6f }, -+ { R367_QAM_ALLPASSFILT8, 0x7e }, -+ { R367_QAM_ALLPASSFILT9, 0x05 }, -+ { R367_QAM_ALLPASSFILT10, 0x0a }, -+ { R367_QAM_ALLPASSFILT11, 0x51 }, -+ { R367_QAM_TRL_AGC_CFG, 0x20 }, -+ { R367_QAM_TRL_LPF_CFG, 0x28 }, -+ { R367_QAM_TRL_LPF_ACQ_GAIN, 0x44 }, -+ { R367_QAM_TRL_LPF_TRK_GAIN, 0x22 }, -+ { R367_QAM_TRL_LPF_OUT_GAIN, 0x03 }, -+ { R367_QAM_TRL_LOCKDET_LTH, 0x04 }, -+ { R367_QAM_TRL_LOCKDET_HTH, 0x11 }, -+ { R367_QAM_TRL_LOCKDET_TRGVAL, 0x20 }, -+ { R367_QAM_IQ_QAM, 0x01 }, -+ { R367_QAM_FSM_STATE, 0xa0 }, -+ { R367_QAM_FSM_CTL, 0x08 }, -+ { R367_QAM_FSM_STS, 0x0c }, -+ { R367_QAM_FSM_SNR0_HTH, 0x00 }, -+ { R367_QAM_FSM_SNR1_HTH, 0x00 }, -+ { R367_QAM_FSM_SNR2_HTH, 0x00 }, -+ { R367_QAM_FSM_SNR0_LTH, 0x00 }, -+ { R367_QAM_FSM_SNR1_LTH, 0x00 }, -+ { R367_QAM_FSM_EQA1_HTH, 0x00 }, -+ { R367_QAM_FSM_TEMPO, 0x32 }, -+ { R367_QAM_FSM_CONFIG, 0x03 }, -+ { R367_QAM_EQU_I_TESTTAP_L, 0x11 }, -+ { R367_QAM_EQU_I_TESTTAP_M, 0x00 }, -+ { R367_QAM_EQU_I_TESTTAP_H, 0x00 }, -+ { R367_QAM_EQU_TESTAP_CFG, 0x00 }, -+ { R367_QAM_EQU_Q_TESTTAP_L, 0xff }, -+ { R367_QAM_EQU_Q_TESTTAP_M, 0x00 }, -+ { R367_QAM_EQU_Q_TESTTAP_H, 0x00 }, -+ { R367_QAM_EQU_TAP_CTRL, 0x00 }, -+ { R367_QAM_EQU_CTR_CRL_CONTROL_L, 0x11 }, -+ { R367_QAM_EQU_CTR_CRL_CONTROL_H, 0x05 }, -+ { R367_QAM_EQU_CTR_HIPOW_L, 0x00 }, -+ { R367_QAM_EQU_CTR_HIPOW_H, 0x00 }, -+ { R367_QAM_EQU_I_EQU_LO, 0xef }, -+ { R367_QAM_EQU_I_EQU_HI, 0x00 }, -+ { R367_QAM_EQU_Q_EQU_LO, 0xee }, -+ { R367_QAM_EQU_Q_EQU_HI, 0x00 }, -+ { R367_QAM_EQU_MAPPER, 0xc5 }, -+ { R367_QAM_EQU_SWEEP_RATE, 0x80 }, -+ { R367_QAM_EQU_SNR_LO, 0x64 }, -+ { R367_QAM_EQU_SNR_HI, 0x03 }, -+ { R367_QAM_EQU_GAMMA_LO, 0x00 }, -+ { R367_QAM_EQU_GAMMA_HI, 0x00 }, -+ { R367_QAM_EQU_ERR_GAIN, 0x36 }, -+ { R367_QAM_EQU_RADIUS, 0xaa }, -+ { R367_QAM_EQU_FFE_MAINTAP, 0x00 }, -+ { R367_QAM_EQU_FFE_LEAKAGE, 0x63 }, -+ { R367_QAM_EQU_FFE_MAINTAP_POS, 0xdf }, -+ { R367_QAM_EQU_GAIN_WIDE, 0x88 }, -+ { R367_QAM_EQU_GAIN_NARROW, 0x41 }, -+ { R367_QAM_EQU_CTR_LPF_GAIN, 0xd1 }, -+ { R367_QAM_EQU_CRL_LPF_GAIN, 0xa7 }, -+ { R367_QAM_EQU_GLOBAL_GAIN, 0x06 }, -+ { R367_QAM_EQU_CRL_LD_SEN, 0x85 }, -+ { R367_QAM_EQU_CRL_LD_VAL, 0xe2 }, -+ { R367_QAM_EQU_CRL_TFR, 0x20 }, -+ { R367_QAM_EQU_CRL_BISTH_LO, 0x00 }, -+ { R367_QAM_EQU_CRL_BISTH_HI, 0x00 }, -+ { R367_QAM_EQU_SWEEP_RANGE_LO, 0x00 }, -+ { R367_QAM_EQU_SWEEP_RANGE_HI, 0x00 }, -+ { R367_QAM_EQU_CRL_LIMITER, 0x40 }, -+ { R367_QAM_EQU_MODULUS_MAP, 0x90 }, -+ { R367_QAM_EQU_PNT_GAIN, 0xa7 }, -+ { R367_QAM_FEC_AC_CTR_0, 0x16 }, -+ { R367_QAM_FEC_AC_CTR_1, 0x0b }, -+ { R367_QAM_FEC_AC_CTR_2, 0x88 }, -+ { R367_QAM_FEC_AC_CTR_3, 0x02 }, -+ { R367_QAM_FEC_STATUS, 0x12 }, -+ { R367_QAM_RS_COUNTER_0, 0x7d }, -+ { R367_QAM_RS_COUNTER_1, 0xd0 }, -+ { R367_QAM_RS_COUNTER_2, 0x19 }, -+ { R367_QAM_RS_COUNTER_3, 0x0b }, -+ { R367_QAM_RS_COUNTER_4, 0xa3 }, -+ { R367_QAM_RS_COUNTER_5, 0x00 }, -+ { R367_QAM_BERT_0, 0x01 }, -+ { R367_QAM_BERT_1, 0x25 }, -+ { R367_QAM_BERT_2, 0x41 }, -+ { R367_QAM_BERT_3, 0x39 }, -+ { R367_QAM_OUTFORMAT_0, 0xc2 }, -+ { R367_QAM_OUTFORMAT_1, 0x22 }, -+ { R367_QAM_SMOOTHER_2, 0x28 }, -+ { R367_QAM_TSMF_CTRL_0, 0x01 }, -+ { R367_QAM_TSMF_CTRL_1, 0xc6 }, -+ { R367_QAM_TSMF_CTRL_3, 0x43 }, -+ { R367_QAM_TS_ON_ID_0, 0x00 }, -+ { R367_QAM_TS_ON_ID_1, 0x00 }, -+ { R367_QAM_TS_ON_ID_2, 0x00 }, -+ { R367_QAM_TS_ON_ID_3, 0x00 }, -+ { R367_QAM_RE_STATUS_0, 0x00 }, -+ { R367_QAM_RE_STATUS_1, 0x00 }, -+ { R367_QAM_RE_STATUS_2, 0x00 }, -+ { R367_QAM_RE_STATUS_3, 0x00 }, -+ { R367_QAM_TS_STATUS_0, 0x00 }, -+ { R367_QAM_TS_STATUS_1, 0x00 }, -+ { R367_QAM_TS_STATUS_2, 0xa0 }, -+ { R367_QAM_TS_STATUS_3, 0x00 }, -+ { R367_QAM_T_O_ID_0, 0x00 }, -+ { R367_QAM_T_O_ID_1, 0x00 }, -+ { R367_QAM_T_O_ID_2, 0x00 }, -+ { R367_QAM_T_O_ID_3, 0x00 }, -+ { 0x0000, 0x00 } // EOT -+}; -+ -+struct init_table ofdm_init[] = { -+ //{R367_OFDM_ID ,0x60}, -+ //{R367_OFDM_I2CRPT ,0x22}, -+ //{R367_OFDM_TOPCTRL ,0x02}, -+ //{R367_OFDM_IOCFG0 ,0x40}, -+ //{R367_OFDM_DAC0R ,0x00}, -+ //{R367_OFDM_IOCFG1 ,0x00}, -+ //{R367_OFDM_DAC1R ,0x00}, -+ //{R367_OFDM_IOCFG2 ,0x62}, -+ //{R367_OFDM_SDFR ,0x00}, -+ //{R367_OFDM_STATUS ,0xf8}, -+ //{R367_OFDM_AUX_CLK ,0x0a}, -+ //{R367_OFDM_FREESYS1 ,0x00}, -+ //{R367_OFDM_FREESYS2 ,0x00}, -+ //{R367_OFDM_FREESYS3 ,0x00}, -+ //{R367_OFDM_GPIO_CFG ,0x55}, -+ //{R367_OFDM_GPIO_CMD ,0x00}, -+ {R367_OFDM_AGC2MAX ,0xff}, -+ {R367_OFDM_AGC2MIN ,0x00}, -+ {R367_OFDM_AGC1MAX ,0xff}, -+ {R367_OFDM_AGC1MIN ,0x00}, -+ {R367_OFDM_AGCR ,0xbc}, -+ {R367_OFDM_AGC2TH ,0x00}, -+ //{R367_OFDM_AGC12C ,0x01}, //Note: This defines AGC pins, also needed for QAM -+ {R367_OFDM_AGCCTRL1 ,0x85}, -+ {R367_OFDM_AGCCTRL2 ,0x1f}, -+ {R367_OFDM_AGC1VAL1 ,0x00}, -+ {R367_OFDM_AGC1VAL2 ,0x00}, -+ {R367_OFDM_AGC2VAL1 ,0x6f}, -+ {R367_OFDM_AGC2VAL2 ,0x05}, -+ {R367_OFDM_AGC2PGA ,0x00}, -+ {R367_OFDM_OVF_RATE1 ,0x00}, -+ {R367_OFDM_OVF_RATE2 ,0x00}, -+ {R367_OFDM_GAIN_SRC1 ,0x2b}, -+ {R367_OFDM_GAIN_SRC2 ,0x04}, -+ {R367_OFDM_INC_DEROT1 ,0x55}, -+ {R367_OFDM_INC_DEROT2 ,0x55}, -+ {R367_OFDM_PPM_CPAMP_DIR ,0x2c}, -+ {R367_OFDM_PPM_CPAMP_INV ,0x00}, -+ {R367_OFDM_FREESTFE_1 ,0x00}, -+ {R367_OFDM_FREESTFE_2 ,0x1c}, -+ {R367_OFDM_DCOFFSET ,0x00}, -+ {R367_OFDM_EN_PROCESS ,0x05}, -+ {R367_OFDM_SDI_SMOOTHER ,0x80}, -+ {R367_OFDM_FE_LOOP_OPEN ,0x1c}, -+ {R367_OFDM_FREQOFF1 ,0x00}, -+ {R367_OFDM_FREQOFF2 ,0x00}, -+ {R367_OFDM_FREQOFF3 ,0x00}, -+ {R367_OFDM_TIMOFF1 ,0x00}, -+ {R367_OFDM_TIMOFF2 ,0x00}, -+ {R367_OFDM_EPQ ,0x02}, -+ {R367_OFDM_EPQAUTO ,0x01}, -+ {R367_OFDM_SYR_UPDATE ,0xf5}, -+ {R367_OFDM_CHPFREE ,0x00}, -+ {R367_OFDM_PPM_STATE_MAC ,0x23}, -+ {R367_OFDM_INR_THRESHOLD ,0xff}, -+ {R367_OFDM_EPQ_TPS_ID_CELL ,0xf9}, -+ {R367_OFDM_EPQ_CFG ,0x00}, -+ {R367_OFDM_EPQ_STATUS ,0x01}, -+ {R367_OFDM_AUTORELOCK ,0x81}, -+ {R367_OFDM_BER_THR_VMSB ,0x00}, -+ {R367_OFDM_BER_THR_MSB ,0x00}, -+ {R367_OFDM_BER_THR_LSB ,0x00}, -+ {R367_OFDM_CCD ,0x83}, -+ {R367_OFDM_SPECTR_CFG ,0x00}, -+ {R367_OFDM_CHC_DUMMY ,0x18}, -+ {R367_OFDM_INC_CTL ,0x88}, -+ {R367_OFDM_INCTHRES_COR1 ,0xb4}, -+ {R367_OFDM_INCTHRES_COR2 ,0x96}, -+ {R367_OFDM_INCTHRES_DET1 ,0x0e}, -+ {R367_OFDM_INCTHRES_DET2 ,0x11}, -+ {R367_OFDM_IIR_CELLNB ,0x8d}, -+ {R367_OFDM_IIRCX_COEFF1_MSB ,0x00}, -+ {R367_OFDM_IIRCX_COEFF1_LSB ,0x00}, -+ {R367_OFDM_IIRCX_COEFF2_MSB ,0x09}, -+ {R367_OFDM_IIRCX_COEFF2_LSB ,0x18}, -+ {R367_OFDM_IIRCX_COEFF3_MSB ,0x14}, -+ {R367_OFDM_IIRCX_COEFF3_LSB ,0x9c}, -+ {R367_OFDM_IIRCX_COEFF4_MSB ,0x00}, -+ {R367_OFDM_IIRCX_COEFF4_LSB ,0x00}, -+ {R367_OFDM_IIRCX_COEFF5_MSB ,0x36}, -+ {R367_OFDM_IIRCX_COEFF5_LSB ,0x42}, -+ {R367_OFDM_FEPATH_CFG ,0x00}, -+ {R367_OFDM_PMC1_FUNC ,0x65}, -+ {R367_OFDM_PMC1_FOR ,0x00}, -+ {R367_OFDM_PMC2_FUNC ,0x00}, -+ {R367_OFDM_STATUS_ERR_DA ,0xe0}, -+ {R367_OFDM_DIG_AGC_R ,0xfe}, -+ {R367_OFDM_COMAGC_TARMSB ,0x0b}, -+ {R367_OFDM_COM_AGC_TAR_ENMODE ,0x41}, -+ {R367_OFDM_COM_AGC_CFG ,0x3e}, -+ {R367_OFDM_COM_AGC_GAIN1 ,0x39}, -+ {R367_OFDM_AUT_AGC_TARGETMSB ,0x0b}, -+ {R367_OFDM_LOCK_DET_MSB ,0x01}, -+ {R367_OFDM_AGCTAR_LOCK_LSBS ,0x40}, -+ {R367_OFDM_AUT_GAIN_EN ,0xf4}, -+ {R367_OFDM_AUT_CFG ,0xf0}, -+ {R367_OFDM_LOCKN ,0x23}, -+ {R367_OFDM_INT_X_3 ,0x00}, -+ {R367_OFDM_INT_X_2 ,0x03}, -+ {R367_OFDM_INT_X_1 ,0x8d}, -+ {R367_OFDM_INT_X_0 ,0xa0}, -+ {R367_OFDM_MIN_ERRX_MSB ,0x00}, -+ {R367_OFDM_COR_CTL ,0x00}, -+ {R367_OFDM_COR_STAT ,0xf6}, -+ {R367_OFDM_COR_INTEN ,0x00}, -+ {R367_OFDM_COR_INTSTAT ,0x3f}, -+ {R367_OFDM_COR_MODEGUARD ,0x03}, -+ {R367_OFDM_AGC_CTL ,0x08}, -+ {R367_OFDM_AGC_MANUAL1 ,0x00}, -+ {R367_OFDM_AGC_MANUAL2 ,0x00}, -+ {R367_OFDM_AGC_TARG ,0x16}, -+ {R367_OFDM_AGC_GAIN1 ,0x53}, -+ {R367_OFDM_AGC_GAIN2 ,0x1d}, -+ {R367_OFDM_RESERVED_1 ,0x00}, -+ {R367_OFDM_RESERVED_2 ,0x00}, -+ {R367_OFDM_RESERVED_3 ,0x00}, -+ {R367_OFDM_CAS_CTL ,0x44}, -+ {R367_OFDM_CAS_FREQ ,0xb3}, -+ {R367_OFDM_CAS_DAGCGAIN ,0x12}, -+ {R367_OFDM_SYR_CTL ,0x04}, -+ {R367_OFDM_SYR_STAT ,0x10}, -+ {R367_OFDM_SYR_NCO1 ,0x00}, -+ {R367_OFDM_SYR_NCO2 ,0x00}, -+ {R367_OFDM_SYR_OFFSET1 ,0x00}, -+ {R367_OFDM_SYR_OFFSET2 ,0x00}, -+ {R367_OFDM_FFT_CTL ,0x00}, -+ {R367_OFDM_SCR_CTL ,0x70}, -+ {R367_OFDM_PPM_CTL1 ,0xf8}, -+ {R367_OFDM_TRL_CTL ,0xac}, -+ {R367_OFDM_TRL_NOMRATE1 ,0x1e}, -+ {R367_OFDM_TRL_NOMRATE2 ,0x58}, -+ {R367_OFDM_TRL_TIME1 ,0x1d}, -+ {R367_OFDM_TRL_TIME2 ,0xfc}, -+ {R367_OFDM_CRL_CTL ,0x24}, -+ {R367_OFDM_CRL_FREQ1 ,0xad}, -+ {R367_OFDM_CRL_FREQ2 ,0x9d}, -+ {R367_OFDM_CRL_FREQ3 ,0xff}, -+ {R367_OFDM_CHC_CTL ,0x01}, -+ {R367_OFDM_CHC_SNR ,0xf0}, -+ {R367_OFDM_BDI_CTL ,0x00}, -+ {R367_OFDM_DMP_CTL ,0x00}, -+ {R367_OFDM_TPS_RCVD1 ,0x30}, -+ {R367_OFDM_TPS_RCVD2 ,0x02}, -+ {R367_OFDM_TPS_RCVD3 ,0x01}, -+ {R367_OFDM_TPS_RCVD4 ,0x00}, -+ {R367_OFDM_TPS_ID_CELL1 ,0x00}, -+ {R367_OFDM_TPS_ID_CELL2 ,0x00}, -+ {R367_OFDM_TPS_RCVD5_SET1 ,0x02}, -+ {R367_OFDM_TPS_SET2 ,0x02}, -+ {R367_OFDM_TPS_SET3 ,0x01}, -+ {R367_OFDM_TPS_CTL ,0x00}, -+ {R367_OFDM_CTL_FFTOSNUM ,0x34}, -+ {R367_OFDM_TESTSELECT ,0x09}, -+ {R367_OFDM_MSC_REV ,0x0a}, -+ {R367_OFDM_PIR_CTL ,0x00}, -+ {R367_OFDM_SNR_CARRIER1 ,0xa1}, -+ {R367_OFDM_SNR_CARRIER2 ,0x9a}, -+ {R367_OFDM_PPM_CPAMP ,0x2c}, -+ {R367_OFDM_TSM_AP0 ,0x00}, -+ {R367_OFDM_TSM_AP1 ,0x00}, -+ {R367_OFDM_TSM_AP2 ,0x00}, -+ {R367_OFDM_TSM_AP3 ,0x00}, -+ {R367_OFDM_TSM_AP4 ,0x00}, -+ {R367_OFDM_TSM_AP5 ,0x00}, -+ {R367_OFDM_TSM_AP6 ,0x00}, -+ {R367_OFDM_TSM_AP7 ,0x00}, -+ //{R367_OFDM_TSTRES ,0x00}, -+ //{R367_OFDM_ANACTRL ,0x0D},/*caution PLL stopped, to be restarted at init!!!*/ -+ //{R367_OFDM_TSTBUS ,0x00}, -+ //{R367_OFDM_TSTRATE ,0x00}, -+ {R367_OFDM_CONSTMODE ,0x01}, -+ {R367_OFDM_CONSTCARR1 ,0x00}, -+ {R367_OFDM_CONSTCARR2 ,0x00}, -+ {R367_OFDM_ICONSTEL ,0x0a}, -+ {R367_OFDM_QCONSTEL ,0x15}, -+ {R367_OFDM_TSTBISTRES0 ,0x00}, -+ {R367_OFDM_TSTBISTRES1 ,0x00}, -+ {R367_OFDM_TSTBISTRES2 ,0x28}, -+ {R367_OFDM_TSTBISTRES3 ,0x00}, -+ //{R367_OFDM_RF_AGC1 ,0xff}, -+ //{R367_OFDM_RF_AGC2 ,0x83}, -+ //{R367_OFDM_ANADIGCTRL ,0x19}, -+ //{R367_OFDM_PLLMDIV ,0x0c}, -+ //{R367_OFDM_PLLNDIV ,0x55}, -+ //{R367_OFDM_PLLSETUP ,0x18}, -+ //{R367_OFDM_DUAL_AD12 ,0x00}, -+ //{R367_OFDM_TSTBIST ,0x00}, -+ //{R367_OFDM_PAD_COMP_CTRL ,0x00}, -+ //{R367_OFDM_PAD_COMP_WR ,0x00}, -+ //{R367_OFDM_PAD_COMP_RD ,0xe0}, -+ {R367_OFDM_SYR_TARGET_FFTADJT_MSB ,0x00}, -+ {R367_OFDM_SYR_TARGET_FFTADJT_LSB ,0x00}, -+ {R367_OFDM_SYR_TARGET_CHCADJT_MSB ,0x00}, -+ {R367_OFDM_SYR_TARGET_CHCADJT_LSB ,0x00}, -+ {R367_OFDM_SYR_FLAG ,0x00}, -+ {R367_OFDM_CRL_TARGET1 ,0x00}, -+ {R367_OFDM_CRL_TARGET2 ,0x00}, -+ {R367_OFDM_CRL_TARGET3 ,0x00}, -+ {R367_OFDM_CRL_TARGET4 ,0x00}, -+ {R367_OFDM_CRL_FLAG ,0x00}, -+ {R367_OFDM_TRL_TARGET1 ,0x00}, -+ {R367_OFDM_TRL_TARGET2 ,0x00}, -+ {R367_OFDM_TRL_CHC ,0x00}, -+ {R367_OFDM_CHC_SNR_TARG ,0x00}, -+ {R367_OFDM_TOP_TRACK ,0x00}, -+ {R367_OFDM_TRACKER_FREE1 ,0x00}, -+ {R367_OFDM_ERROR_CRL1 ,0x00}, -+ {R367_OFDM_ERROR_CRL2 ,0x00}, -+ {R367_OFDM_ERROR_CRL3 ,0x00}, -+ {R367_OFDM_ERROR_CRL4 ,0x00}, -+ {R367_OFDM_DEC_NCO1 ,0x2c}, -+ {R367_OFDM_DEC_NCO2 ,0x0f}, -+ {R367_OFDM_DEC_NCO3 ,0x20}, -+ {R367_OFDM_SNR ,0xf1}, -+ {R367_OFDM_SYR_FFTADJ1 ,0x00}, -+ {R367_OFDM_SYR_FFTADJ2 ,0x00}, -+ {R367_OFDM_SYR_CHCADJ1 ,0x00}, -+ {R367_OFDM_SYR_CHCADJ2 ,0x00}, -+ {R367_OFDM_SYR_OFF ,0x00}, -+ {R367_OFDM_PPM_OFFSET1 ,0x00}, -+ {R367_OFDM_PPM_OFFSET2 ,0x03}, -+ {R367_OFDM_TRACKER_FREE2 ,0x00}, -+ {R367_OFDM_DEBG_LT10 ,0x00}, -+ {R367_OFDM_DEBG_LT11 ,0x00}, -+ {R367_OFDM_DEBG_LT12 ,0x00}, -+ {R367_OFDM_DEBG_LT13 ,0x00}, -+ {R367_OFDM_DEBG_LT14 ,0x00}, -+ {R367_OFDM_DEBG_LT15 ,0x00}, -+ {R367_OFDM_DEBG_LT16 ,0x00}, -+ {R367_OFDM_DEBG_LT17 ,0x00}, -+ {R367_OFDM_DEBG_LT18 ,0x00}, -+ {R367_OFDM_DEBG_LT19 ,0x00}, -+ {R367_OFDM_DEBG_LT1A ,0x00}, -+ {R367_OFDM_DEBG_LT1B ,0x00}, -+ {R367_OFDM_DEBG_LT1C ,0x00}, -+ {R367_OFDM_DEBG_LT1D ,0x00}, -+ {R367_OFDM_DEBG_LT1E ,0x00}, -+ {R367_OFDM_DEBG_LT1F ,0x00}, -+ {R367_OFDM_RCCFGH ,0x00}, -+ {R367_OFDM_RCCFGM ,0x00}, -+ {R367_OFDM_RCCFGL ,0x00}, -+ {R367_OFDM_RCINSDELH ,0x00}, -+ {R367_OFDM_RCINSDELM ,0x00}, -+ {R367_OFDM_RCINSDELL ,0x00}, -+ {R367_OFDM_RCSTATUS ,0x00}, -+ {R367_OFDM_RCSPEED ,0x6f}, -+ {R367_OFDM_RCDEBUGM ,0xe7}, -+ {R367_OFDM_RCDEBUGL ,0x9b}, -+ {R367_OFDM_RCOBSCFG ,0x00}, -+ {R367_OFDM_RCOBSM ,0x00}, -+ {R367_OFDM_RCOBSL ,0x00}, -+ {R367_OFDM_RCFECSPY ,0x00}, -+ {R367_OFDM_RCFSPYCFG ,0x00}, -+ {R367_OFDM_RCFSPYDATA ,0x00}, -+ {R367_OFDM_RCFSPYOUT ,0x00}, -+ {R367_OFDM_RCFSTATUS ,0x00}, -+ {R367_OFDM_RCFGOODPACK ,0x00}, -+ {R367_OFDM_RCFPACKCNT ,0x00}, -+ {R367_OFDM_RCFSPYMISC ,0x00}, -+ {R367_OFDM_RCFBERCPT4 ,0x00}, -+ {R367_OFDM_RCFBERCPT3 ,0x00}, -+ {R367_OFDM_RCFBERCPT2 ,0x00}, -+ {R367_OFDM_RCFBERCPT1 ,0x00}, -+ {R367_OFDM_RCFBERCPT0 ,0x00}, -+ {R367_OFDM_RCFBERERR2 ,0x00}, -+ {R367_OFDM_RCFBERERR1 ,0x00}, -+ {R367_OFDM_RCFBERERR0 ,0x00}, -+ {R367_OFDM_RCFSTATESM ,0x00}, -+ {R367_OFDM_RCFSTATESL ,0x00}, -+ {R367_OFDM_RCFSPYBER ,0x00}, -+ {R367_OFDM_RCFSPYDISTM ,0x00}, -+ {R367_OFDM_RCFSPYDISTL ,0x00}, -+ {R367_OFDM_RCFSPYOBS7 ,0x00}, -+ {R367_OFDM_RCFSPYOBS6 ,0x00}, -+ {R367_OFDM_RCFSPYOBS5 ,0x00}, -+ {R367_OFDM_RCFSPYOBS4 ,0x00}, -+ {R367_OFDM_RCFSPYOBS3 ,0x00}, -+ {R367_OFDM_RCFSPYOBS2 ,0x00}, -+ {R367_OFDM_RCFSPYOBS1 ,0x00}, -+ {R367_OFDM_RCFSPYOBS0 ,0x00}, -+ //{R367_OFDM_TSGENERAL ,0x00}, -+ //{R367_OFDM_RC1SPEED ,0x6f}, -+ //{R367_OFDM_TSGSTATUS ,0x18}, -+ {R367_OFDM_FECM ,0x01}, -+ {R367_OFDM_VTH12 ,0xff}, -+ {R367_OFDM_VTH23 ,0xa1}, -+ {R367_OFDM_VTH34 ,0x64}, -+ {R367_OFDM_VTH56 ,0x40}, -+ {R367_OFDM_VTH67 ,0x00}, -+ {R367_OFDM_VTH78 ,0x2c}, -+ {R367_OFDM_VITCURPUN ,0x12}, -+ {R367_OFDM_VERROR ,0x01}, -+ {R367_OFDM_PRVIT ,0x3f}, -+ {R367_OFDM_VAVSRVIT ,0x00}, -+ {R367_OFDM_VSTATUSVIT ,0xbd}, -+ {R367_OFDM_VTHINUSE ,0xa1}, -+ {R367_OFDM_KDIV12 ,0x20}, -+ {R367_OFDM_KDIV23 ,0x40}, -+ {R367_OFDM_KDIV34 ,0x20}, -+ {R367_OFDM_KDIV56 ,0x30}, -+ {R367_OFDM_KDIV67 ,0x00}, -+ {R367_OFDM_KDIV78 ,0x30}, -+ {R367_OFDM_SIGPOWER ,0x54}, -+ {R367_OFDM_DEMAPVIT ,0x40}, -+ {R367_OFDM_VITSCALE ,0x00}, -+ {R367_OFDM_FFEC1PRG ,0x00}, -+ {R367_OFDM_FVITCURPUN ,0x12}, -+ {R367_OFDM_FVERROR ,0x01}, -+ {R367_OFDM_FVSTATUSVIT ,0xbd}, -+ {R367_OFDM_DEBUG_LT1 ,0x00}, -+ {R367_OFDM_DEBUG_LT2 ,0x00}, -+ {R367_OFDM_DEBUG_LT3 ,0x00}, -+ {R367_OFDM_TSTSFMET ,0x00}, -+ {R367_OFDM_SELOUT ,0x00}, -+ {R367_OFDM_TSYNC ,0x00}, -+ {R367_OFDM_TSTERR ,0x00}, -+ {R367_OFDM_TSFSYNC ,0x00}, -+ {R367_OFDM_TSTSFERR ,0x00}, -+ {R367_OFDM_TSTTSSF1 ,0x01}, -+ {R367_OFDM_TSTTSSF2 ,0x1f}, -+ {R367_OFDM_TSTTSSF3 ,0x00}, -+ {R367_OFDM_TSTTS1 ,0x00}, -+ {R367_OFDM_TSTTS2 ,0x1f}, -+ {R367_OFDM_TSTTS3 ,0x01}, -+ {R367_OFDM_TSTTS4 ,0x00}, -+ {R367_OFDM_TSTTSRC ,0x00}, -+ {R367_OFDM_TSTTSRS ,0x00}, -+ {R367_OFDM_TSSTATEM ,0xb0}, -+ {R367_OFDM_TSSTATEL ,0x40}, -+ {R367_OFDM_TSCFGH ,0x80}, -+ {R367_OFDM_TSCFGM ,0x00}, -+ {R367_OFDM_TSCFGL ,0x20}, -+ {R367_OFDM_TSSYNC ,0x00}, -+ {R367_OFDM_TSINSDELH ,0x00}, -+ {R367_OFDM_TSINSDELM ,0x00}, -+ {R367_OFDM_TSINSDELL ,0x00}, -+ {R367_OFDM_TSDIVN ,0x03}, -+ {R367_OFDM_TSDIVPM ,0x00}, -+ {R367_OFDM_TSDIVPL ,0x00}, -+ {R367_OFDM_TSDIVQM ,0x00}, -+ {R367_OFDM_TSDIVQL ,0x00}, -+ {R367_OFDM_TSDILSTKM ,0x00}, -+ {R367_OFDM_TSDILSTKL ,0x00}, -+ {R367_OFDM_TSSPEED ,0x6f}, -+ {R367_OFDM_TSSTATUS ,0x81}, -+ {R367_OFDM_TSSTATUS2 ,0x6a}, -+ {R367_OFDM_TSBITRATEM ,0x0f}, -+ {R367_OFDM_TSBITRATEL ,0xc6}, -+ {R367_OFDM_TSPACKLENM ,0x00}, -+ {R367_OFDM_TSPACKLENL ,0xfc}, -+ {R367_OFDM_TSBLOCLENM ,0x0a}, -+ {R367_OFDM_TSBLOCLENL ,0x80}, -+ {R367_OFDM_TSDLYH ,0x90}, -+ {R367_OFDM_TSDLYM ,0x68}, -+ {R367_OFDM_TSDLYL ,0x01}, -+ {R367_OFDM_TSNPDAV ,0x00}, -+ {R367_OFDM_TSBUFSTATH ,0x00}, -+ {R367_OFDM_TSBUFSTATM ,0x00}, -+ {R367_OFDM_TSBUFSTATL ,0x00}, -+ {R367_OFDM_TSDEBUGM ,0xcf}, -+ {R367_OFDM_TSDEBUGL ,0x1e}, -+ {R367_OFDM_TSDLYSETH ,0x00}, -+ {R367_OFDM_TSDLYSETM ,0x68}, -+ {R367_OFDM_TSDLYSETL ,0x00}, -+ {R367_OFDM_TSOBSCFG ,0x00}, -+ {R367_OFDM_TSOBSM ,0x47}, -+ {R367_OFDM_TSOBSL ,0x1f}, -+ {R367_OFDM_ERRCTRL1 ,0x95}, -+ {R367_OFDM_ERRCNT1H ,0x80}, -+ {R367_OFDM_ERRCNT1M ,0x00}, -+ {R367_OFDM_ERRCNT1L ,0x00}, -+ {R367_OFDM_ERRCTRL2 ,0x95}, -+ {R367_OFDM_ERRCNT2H ,0x00}, -+ {R367_OFDM_ERRCNT2M ,0x00}, -+ {R367_OFDM_ERRCNT2L ,0x00}, -+ {R367_OFDM_FECSPY ,0x88}, -+ {R367_OFDM_FSPYCFG ,0x2c}, -+ {R367_OFDM_FSPYDATA ,0x3a}, -+ {R367_OFDM_FSPYOUT ,0x06}, -+ {R367_OFDM_FSTATUS ,0x61}, -+ {R367_OFDM_FGOODPACK ,0xff}, -+ {R367_OFDM_FPACKCNT ,0xff}, -+ {R367_OFDM_FSPYMISC ,0x66}, -+ {R367_OFDM_FBERCPT4 ,0x00}, -+ {R367_OFDM_FBERCPT3 ,0x00}, -+ {R367_OFDM_FBERCPT2 ,0x36}, -+ {R367_OFDM_FBERCPT1 ,0x36}, -+ {R367_OFDM_FBERCPT0 ,0x14}, -+ {R367_OFDM_FBERERR2 ,0x00}, -+ {R367_OFDM_FBERERR1 ,0x03}, -+ {R367_OFDM_FBERERR0 ,0x28}, -+ {R367_OFDM_FSTATESM ,0x00}, -+ {R367_OFDM_FSTATESL ,0x02}, -+ {R367_OFDM_FSPYBER ,0x00}, -+ {R367_OFDM_FSPYDISTM ,0x01}, -+ {R367_OFDM_FSPYDISTL ,0x9f}, -+ {R367_OFDM_FSPYOBS7 ,0xc9}, -+ {R367_OFDM_FSPYOBS6 ,0x99}, -+ {R367_OFDM_FSPYOBS5 ,0x08}, -+ {R367_OFDM_FSPYOBS4 ,0xec}, -+ {R367_OFDM_FSPYOBS3 ,0x01}, -+ {R367_OFDM_FSPYOBS2 ,0x0f}, -+ {R367_OFDM_FSPYOBS1 ,0xf5}, -+ {R367_OFDM_FSPYOBS0 ,0x08}, -+ {R367_OFDM_SFDEMAP ,0x40}, -+ {R367_OFDM_SFERROR ,0x00}, -+ {R367_OFDM_SFAVSR ,0x30}, -+ {R367_OFDM_SFECSTATUS ,0xcc}, -+ {R367_OFDM_SFKDIV12 ,0x20}, -+ {R367_OFDM_SFKDIV23 ,0x40}, -+ {R367_OFDM_SFKDIV34 ,0x20}, -+ {R367_OFDM_SFKDIV56 ,0x20}, -+ {R367_OFDM_SFKDIV67 ,0x00}, -+ {R367_OFDM_SFKDIV78 ,0x20}, -+ {R367_OFDM_SFDILSTKM ,0x00}, -+ {R367_OFDM_SFDILSTKL ,0x00}, -+ {R367_OFDM_SFSTATUS ,0xb5}, -+ {R367_OFDM_SFDLYH ,0x90}, -+ {R367_OFDM_SFDLYM ,0x60}, -+ {R367_OFDM_SFDLYL ,0x01}, -+ {R367_OFDM_SFDLYSETH ,0xc0}, -+ {R367_OFDM_SFDLYSETM ,0x60}, -+ {R367_OFDM_SFDLYSETL ,0x00}, -+ {R367_OFDM_SFOBSCFG ,0x00}, -+ {R367_OFDM_SFOBSM ,0x47}, -+ {R367_OFDM_SFOBSL ,0x05}, -+ {R367_OFDM_SFECINFO ,0x40}, -+ {R367_OFDM_SFERRCTRL ,0x74}, -+ {R367_OFDM_SFERRCNTH ,0x80}, -+ {R367_OFDM_SFERRCNTM ,0x00}, -+ {R367_OFDM_SFERRCNTL ,0x00}, -+ {R367_OFDM_SYMBRATEM ,0x2f}, -+ {R367_OFDM_SYMBRATEL ,0x50}, -+ {R367_OFDM_SYMBSTATUS ,0x7f}, -+ {R367_OFDM_SYMBCFG ,0x00}, -+ {R367_OFDM_SYMBFIFOM ,0xf4}, -+ {R367_OFDM_SYMBFIFOL ,0x0d}, -+ {R367_OFDM_SYMBOFFSM ,0xf0}, -+ {R367_OFDM_SYMBOFFSL ,0x2d}, -+ //{R367_OFDM_DEBUG_LT4 ,0x00}, -+ //{R367_OFDM_DEBUG_LT5 ,0x00}, -+ //{R367_OFDM_DEBUG_LT6 ,0x00}, -+ //{R367_OFDM_DEBUG_LT7 ,0x00}, -+ //{R367_OFDM_DEBUG_LT8 ,0x00}, -+ //{R367_OFDM_DEBUG_LT9 ,0x00}, -+ { 0x0000, 0x00 } // EOT -+}; -+ -+static inline u32 MulDiv32(u32 a, u32 b, u32 c) -+{ -+ u64 tmp64; -+ -+ tmp64 = (u64)a * (u64)b; -+ do_div(tmp64, c); -+ -+ return (u32) tmp64; -+} -+ -+static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) -+{ -+ struct i2c_msg msg = -+ {.addr = adr, .flags = 0, .buf = data, .len = len}; -+ -+ if (i2c_transfer(adap, &msg, 1) != 1) { -+ printk("stv0367: i2c_write error\n"); -+ return -1; -+ } -+ return 0; -+} -+ -+#if 0 -+static int i2c_read(struct i2c_adapter *adap, -+ u8 adr, u8 *msg, int len, u8 *answ, int alen) -+{ -+ struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, -+ .buf = msg, .len = len}, -+ { .addr = adr, .flags = I2C_M_RD, -+ .buf = answ, .len = alen } }; -+ if (i2c_transfer(adap, msgs, 2) != 2) { -+ printk("stv0367: i2c_read error\n"); -+ return -1; -+ } -+ return 0; -+} -+#endif -+ -+static int writereg(struct stv_state *state, u16 reg, u8 dat) -+{ -+ u8 mm[3] = { (reg >> 8), reg & 0xff, dat }; -+ -+ return i2c_write(state->i2c, state->adr, mm, 3); -+} -+ -+static int readreg(struct stv_state *state, u16 reg, u8 *val) -+{ -+ u8 msg[2] = {reg >> 8, reg & 0xff}; -+ struct i2c_msg msgs[2] = {{.addr = state->adr, .flags = 0, -+ .buf = msg, .len = 2}, -+ {.addr = state->adr, .flags = I2C_M_RD, -+ .buf = val, .len = 1}}; -+ return (i2c_transfer(state->i2c, msgs, 2) == 2) ? 0 : -1; -+} -+ -+static int readregs(struct stv_state *state, u16 reg, u8 *val, int count) -+{ -+ u8 msg[2] = {reg >> 8, reg & 0xff}; -+ struct i2c_msg msgs[2] = {{.addr = state->adr, .flags = 0, -+ .buf = msg, .len = 2}, -+ {.addr = state->adr, .flags = I2C_M_RD, -+ .buf = val, .len = count}}; -+ return (i2c_transfer(state->i2c, msgs, 2) == 2) ? 0 : -1; -+} -+ -+static int write_init_table(struct stv_state *state, struct init_table *tab) -+{ -+ while (1) { -+ if (!tab->adr) -+ break; -+ if (writereg(state, tab->adr, tab->data) < 0) -+ return -1; -+ tab++; -+ } -+ return 0; -+} -+ -+static int qam_set_modulation(struct stv_state *state) -+{ -+ int stat = 0; -+ -+ switch(state->modulation) { -+ case QAM_16: -+ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM16 ); -+ writereg(state, R367_QAM_AGC_PWR_REF_L,0x64); /* Set analog AGC reference */ -+ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ -+ writereg(state, R367_QAM_FSM_STATE,0x90); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); -+ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x95); -+ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,0x8a); -+ break; -+ case QAM_32: -+ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM32 ); -+ writereg(state, R367_QAM_AGC_PWR_REF_L,0x6e); /* Set analog AGC reference */ -+ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ -+ writereg(state, R367_QAM_FSM_STATE,0xb0); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xb7); -+ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x9d); -+ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x7f); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); -+ break; -+ case QAM_64: -+ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM64 ); -+ writereg(state, R367_QAM_AGC_PWR_REF_L,0x5a); /* Set analog AGC reference */ -+ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x82); /* Set digital AGC reference */ -+ if(state->symbol_rate>4500000) -+ { -+ writereg(state, R367_QAM_FSM_STATE,0xb0); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa5); -+ } -+ else if(state->symbol_rate>2500000) // 25000000 -+ { -+ writereg(state, R367_QAM_FSM_STATE,0xa0); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa6); -+ } -+ else -+ { -+ writereg(state, R367_QAM_FSM_STATE,0xa0); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xd1); -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); -+ } -+ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x95); -+ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,0x99); -+ break; -+ case QAM_128: -+ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM128 ); -+ writereg(state, R367_QAM_AGC_PWR_REF_L,0x76); /* Set analog AGC reference */ -+ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ -+ writereg(state, R367_QAM_FSM_STATE,0x90); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xb1); -+ if(state->symbol_rate>4500000) // 45000000 -+ { -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); -+ } -+ else if(state->symbol_rate>2500000) // 25000000 -+ { -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa6); -+ } -+ else -+ { -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0x97); -+ } -+ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x8e); -+ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x7f); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); -+ break; -+ case QAM_256: -+ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM256 ); -+ writereg(state, R367_QAM_AGC_PWR_REF_L,0x5a); /* Set analog AGC reference */ -+ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x94); /* Set digital AGC reference */ -+ writereg(state, R367_QAM_FSM_STATE,0xa0); -+ if(state->symbol_rate>4500000) // 45000000 -+ { -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ } -+ else if(state->symbol_rate>2500000) // 25000000 -+ { -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); -+ } -+ else -+ { -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xd1); -+ } -+ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); -+ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x85); -+ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); -+ break; -+ default: -+ stat = -EINVAL; -+ break; -+ } -+ return stat; -+} -+ -+ -+static int QAM_SetSymbolRate(struct stv_state *state) -+{ -+ int status = 0; -+ u32 sr = state->symbol_rate; -+ u32 Corr = 0; -+ u32 Temp, Temp1, AdpClk; -+ -+ switch(state->modulation) { -+ default: -+ case QAM_16: Corr = 1032; break; -+ case QAM_32: Corr = 954; break; -+ case QAM_64: Corr = 983; break; -+ case QAM_128: Corr = 957; break; -+ case QAM_256: Corr = 948; break; -+ } -+ -+ // Transfer ration -+ Temp = (256*sr) / state->adc_clock; -+ writereg(state, R367_QAM_EQU_CRL_TFR,(Temp)); -+ -+ /* Symbol rate and SRC gain calculation */ -+ AdpClk = (state->master_clock) / 2000; /* TRL works at half the system clock */ -+ -+ Temp = state->symbol_rate; -+ Temp1 = sr; -+ -+ if(sr < 2097152) /* 2097152 = 2^21 */ -+ { -+ Temp = ((((sr * 2048) / AdpClk) * 16384 ) / 125 ) * 8; -+ Temp1 = (((((sr * 2048) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 10000000; -+ } -+ else if(sr < 4194304) /* 4194304 = 2**22 */ -+ { -+ Temp = ((((sr * 1024) / AdpClk) * 16384 ) / 125 ) * 16; -+ Temp1 = (((((sr * 1024) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 5000000; -+ } -+ else if(sr < 8388608) /* 8388608 = 2**23 */ -+ { -+ Temp = ((((sr * 512) / AdpClk) * 16384 ) / 125 ) * 32; -+ Temp1 = (((((sr * 512) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 2500000; -+ } -+ else -+ { -+ Temp = ((((sr * 256) / AdpClk) * 16384 ) / 125 ) * 64; -+ Temp1 = (((((sr * 256) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 1250000; -+ } -+ -+ ///* Filters' coefficients are calculated and written into registers only if the filters are enabled */ -+ //if (ChipGetField(hChip,F367qam_ADJ_EN)) // Is disabled from init! -+ //{ -+ // FE_367qam_SetIirAdjacentcoefficient(hChip, MasterClk_Hz, SymbolRate); -+ //} -+ ///* AllPass filter is never used on this IC */ -+ //ChipSetField(hChip,F367qam_ALLPASSFILT_EN,0); // should be disabled from init! -+ -+ writereg(state, R367_QAM_SRC_NCO_LL,(Temp)); -+ writereg(state, R367_QAM_SRC_NCO_LH,(Temp>>8)); -+ writereg(state, R367_QAM_SRC_NCO_HL,(Temp>>16)); -+ writereg(state, R367_QAM_SRC_NCO_HH,(Temp>>24)); -+ -+ writereg(state, R367_QAM_IQDEM_GAIN_SRC_L,(Temp1)); -+ writereg(state, R367_QAM_IQDEM_GAIN_SRC_H,(Temp1>>8)); -+ return status; -+} -+ -+ -+static int QAM_SetDerotFrequency(struct stv_state *state, u32 DerotFrequency) -+{ -+ int status = 0; -+ u32 Sampled_IF; -+ -+ do { -+ //if (DerotFrequency < 1000000) -+ // DerotFrequency = state->adc_clock/4; /* ZIF operation */ -+ if (DerotFrequency > state->adc_clock) -+ DerotFrequency = DerotFrequency - state->adc_clock; // User Alias -+ -+ Sampled_IF = ((32768 * (DerotFrequency/1000)) / (state->adc_clock/1000)) * 256; -+ if(Sampled_IF > 8388607) -+ Sampled_IF = 8388607; -+ -+ writereg(state, R367_QAM_MIX_NCO_LL, (Sampled_IF)); -+ writereg(state, R367_QAM_MIX_NCO_HL, (Sampled_IF>>8)); -+ writereg(state, R367_QAM_MIX_NCO_HH, (Sampled_IF>>16)); -+ } while(0); -+ -+ return status; -+} -+ -+ -+ -+static int QAM_Start(struct stv_state *state, s32 offsetFreq,s32 IntermediateFrequency) -+{ -+ int status = 0; -+ u32 AGCTimeOut = 25; -+ u32 TRLTimeOut = 100000000 / state->symbol_rate; -+ u32 CRLSymbols = 0; -+ u32 EQLTimeOut = 100; -+ u32 SearchRange = state->symbol_rate / 25; -+ u32 CRLTimeOut; -+ u8 Temp; -+ -+ if( state->demod_state != QAMSet ) { -+ writereg(state, R367_DEBUG_LT4,0x00); -+ writereg(state, R367_DEBUG_LT5,0x01); -+ writereg(state, R367_DEBUG_LT6,0x06);// R367_QAM_CTRL_1 -+ writereg(state, R367_DEBUG_LT7,0x03);// R367_QAM_CTRL_2 -+ writereg(state, R367_DEBUG_LT8,0x00); -+ writereg(state, R367_DEBUG_LT9,0x00); -+ -+ // Tuner Setup -+ writereg(state, R367_ANADIGCTRL,0x8B); /* Buffer Q disabled, I Enabled, signed ADC */ -+ writereg(state, R367_DUAL_AD12,0x04); /* ADCQ disabled */ -+ -+ // Clock setup -+ writereg(state, R367_ANACTRL,0x0D); /* PLL bypassed and disabled */ -+ writereg(state, R367_TOPCTRL,0x10); // Set QAM -+ -+ writereg(state, R367_PLLMDIV,27); /* IC runs at 58 MHz with a 27 MHz crystal */ -+ writereg(state, R367_PLLNDIV,232); -+ writereg(state, R367_PLLSETUP,0x18); /* ADC clock is equal to system clock */ -+ -+ msleep(50); -+ writereg(state, R367_ANACTRL,0x00); /* PLL enabled and used */ -+ -+ state->master_clock = 58000000; -+ state->adc_clock = 58000000; -+ -+ state->demod_state = QAMSet; -+ } -+ -+ state->m_bFirstTimeLock = true; -+ state->m_DemodLockTime = -1; -+ -+ qam_set_modulation(state); -+ QAM_SetSymbolRate(state); -+ -+ // Will make problems on low symbol rates ( < 2500000 ) -+ -+ switch(state->modulation) { -+ default: -+ case QAM_16: CRLSymbols = 150000; break; -+ case QAM_32: CRLSymbols = 250000; break; -+ case QAM_64: CRLSymbols = 200000; break; -+ case QAM_128: CRLSymbols = 250000; break; -+ case QAM_256: CRLSymbols = 250000; break; -+ } -+ -+ CRLTimeOut = (25 * CRLSymbols * (SearchRange/1000)) / (state->symbol_rate/1000); -+ CRLTimeOut = (1000 * CRLTimeOut) / state->symbol_rate; -+ if( CRLTimeOut < 50 ) CRLTimeOut = 50; -+ -+ state->m_FECTimeOut = 20; -+ state->m_DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut; -+ state->m_SignalTimeOut = AGCTimeOut + TRLTimeOut; -+ -+ // QAM_AGC_ACCUMRSTSEL = 0; -+ readreg(state, R367_QAM_AGC_CTL,&state->m_Save_QAM_AGC_CTL); -+ writereg(state, R367_QAM_AGC_CTL,state->m_Save_QAM_AGC_CTL & ~0x0F); -+ -+ // QAM_MODULUSMAP_EN = 0 -+ readreg(state, R367_QAM_EQU_PNT_GAIN,&Temp); -+ writereg(state, R367_QAM_EQU_PNT_GAIN,Temp & ~0x40); -+ -+ // QAM_SWEEP_EN = 0 -+ readreg(state, R367_QAM_EQU_CTR_LPF_GAIN,&Temp); -+ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,Temp & ~0x08); -+ -+ QAM_SetDerotFrequency(state, IntermediateFrequency); -+ -+ // Release TRL -+ writereg(state, R367_QAM_CTRL_1,0x00); -+ -+ state->IF = IntermediateFrequency; -+ state->demod_state = QAMStarted; -+ -+ return status; -+} -+ -+static int OFDM_Start(struct stv_state *state, s32 offsetFreq,s32 IntermediateFrequency) -+{ -+ int status = 0; -+ u8 GAIN_SRC1; -+ u32 Derot; -+ u8 SYR_CTL; -+ u8 tmp1; -+ u8 tmp2; -+ -+ if ( state->demod_state != OFDMSet ) { -+ // QAM Disable -+ writereg(state, R367_DEBUG_LT4, 0x00); -+ writereg(state, R367_DEBUG_LT5, 0x00); -+ writereg(state, R367_DEBUG_LT6, 0x00);// R367_QAM_CTRL_1 -+ writereg(state, R367_DEBUG_LT7, 0x00);// R367_QAM_CTRL_2 -+ writereg(state, R367_DEBUG_LT8, 0x00); -+ writereg(state, R367_DEBUG_LT9, 0x00); -+ -+ // Tuner Setup -+ writereg(state, R367_ANADIGCTRL, 0x89); /* Buffer Q disabled, I Enabled, unsigned ADC */ -+ writereg(state, R367_DUAL_AD12, 0x04); /* ADCQ disabled */ -+ -+ // Clock setup -+ writereg(state, R367_ANACTRL, 0x0D); /* PLL bypassed and disabled */ -+ writereg(state, R367_TOPCTRL, 0x00); // Set OFDM -+ -+ writereg(state, R367_PLLMDIV, 1); /* IC runs at 54 MHz with a 27 MHz crystal */ -+ writereg(state, R367_PLLNDIV, 8); -+ writereg(state, R367_PLLSETUP, 0x18); /* ADC clock is equal to system clock */ -+ -+ msleep(50); -+ writereg(state, R367_ANACTRL, 0x00); /* PLL enabled and used */ -+ -+ state->master_clock = 54000000; -+ state->adc_clock = 54000000; -+ -+ state->demod_state = OFDMSet; -+ } -+ -+ state->m_bFirstTimeLock = true; -+ state->m_DemodLockTime = -1; -+ -+ // Set inversion in GAIN_SRC1 (fixed from init) -+ // is in GAIN_SRC1, see below -+ -+ GAIN_SRC1 = 0xA0; -+ // Bandwidth -+ -+ // Fixed values for 54 MHz -+ switch(state->bandwidth) { -+ case 0: -+ case 8000000: -+ // Normrate = 44384; -+ writereg(state, R367_OFDM_TRL_CTL,0x14); -+ writereg(state, R367_OFDM_TRL_NOMRATE1,0xB0); -+ writereg(state, R367_OFDM_TRL_NOMRATE2,0x56); -+ // Gain SRC = 2774 -+ writereg(state, R367_OFDM_GAIN_SRC1,0x0A | GAIN_SRC1); -+ writereg(state, R367_OFDM_GAIN_SRC2,0xD6); -+ break; -+ case 7000000: -+ // Normrate = 38836; -+ writereg(state, R367_OFDM_TRL_CTL,0x14); -+ writereg(state, R367_OFDM_TRL_NOMRATE1,0xDA); -+ writereg(state, R367_OFDM_TRL_NOMRATE2,0x4B); -+ // Gain SRC = 2427 -+ writereg(state, R367_OFDM_GAIN_SRC1,0x09 | GAIN_SRC1); -+ writereg(state, R367_OFDM_GAIN_SRC2,0x7B); -+ break; -+ case 6000000: -+ // Normrate = 33288; -+ writereg(state, R367_OFDM_TRL_CTL,0x14); -+ writereg(state, R367_OFDM_TRL_NOMRATE1,0x04); -+ writereg(state, R367_OFDM_TRL_NOMRATE2,0x41); -+ // Gain SRC = 2080 -+ writereg(state, R367_OFDM_GAIN_SRC1,0x08 | GAIN_SRC1); -+ writereg(state, R367_OFDM_GAIN_SRC2,0x20); -+ break; -+ default: -+ return -EINVAL; -+ break; -+ } -+ -+ Derot = ((IntermediateFrequency / 1000) * 65536) / (state->master_clock / 1000); -+ -+ writereg(state, R367_OFDM_INC_DEROT1,(Derot>>8)); -+ writereg(state, R367_OFDM_INC_DEROT2,(Derot)); -+ -+ readreg(state, R367_OFDM_SYR_CTL,&SYR_CTL); -+ SYR_CTL &= ~0x78; -+ writereg(state, R367_OFDM_SYR_CTL,SYR_CTL); // EchoPos = 0 -+ -+ -+ writereg(state, R367_OFDM_COR_MODEGUARD,0x03); // Force = 0, Mode = 0, Guard = 3 -+ SYR_CTL &= 0x01; -+ writereg(state, R367_OFDM_SYR_CTL,SYR_CTL); // SYR_TR_DIS = 0 -+ -+ msleep(5); -+ -+ writereg(state, R367_OFDM_COR_CTL,0x20); // Start core -+ -+ // -- Begin M.V. -+ // Reset FEC and Read Solomon -+ readreg(state, R367_OFDM_SFDLYSETH,&tmp1); -+ readreg(state, R367_TSGENERAL,&tmp2); -+ writereg(state, R367_OFDM_SFDLYSETH,tmp1 | 0x08); -+ writereg(state, R367_TSGENERAL,tmp2 | 0x01); -+ // -- End M.V. -+ -+ state->m_SignalTimeOut = 200; -+ state->IF = IntermediateFrequency; -+ state->demod_state = OFDMStarted; -+ state->m_DemodTimeOut = 0; -+ state->m_FECTimeOut = 0; -+ state->m_TSTimeOut = 0; -+ -+ return status; -+} -+ -+#if 0 -+static int Stop(struct stv_state *state) -+{ -+ int status = 0; -+ -+ switch(state->demod_state) -+ { -+ case QAMStarted: -+ status = writereg(state, R367_QAM_CTRL_1,0x06); -+ state->demod_state = QAMSet; -+ break; -+ case OFDMStarted: -+ status = writereg(state, R367_OFDM_COR_CTL,0x00); -+ state->demod_state = OFDMSet; -+ break; -+ default: -+ break; -+ } -+ return status; -+} -+#endif -+ -+static s32 Log10x100(u32 x) -+{ -+ static u32 LookupTable[100] = { -+ 101157945, 103514217, 105925373, 108392691, 110917482, -+ 113501082, 116144861, 118850223, 121618600, 124451461, // 800.5 - 809.5 -+ 127350308, 130316678, 133352143, 136458314, 139636836, -+ 142889396, 146217717, 149623566, 153108746, 156675107, // 810.5 - 819.5 -+ 160324539, 164058977, 167880402, 171790839, 175792361, -+ 179887092, 184077200, 188364909, 192752491, 197242274, // 820.5 - 829.5 -+ 201836636, 206538016, 211348904, 216271852, 221309471, -+ 226464431, 231739465, 237137371, 242661010, 248313311, // 830.5 - 839.5 -+ 254097271, 260015956, 266072506, 272270131, 278612117, -+ 285101827, 291742701, 298538262, 305492111, 312607937, // 840.5 - 849.5 -+ 319889511, 327340695, 334965439, 342767787, 350751874, -+ 358921935, 367282300, 375837404, 384591782, 393550075, // 850.5 - 859.5 -+ 402717034, 412097519, 421696503, 431519077, 441570447, -+ 451855944, 462381021, 473151259, 484172368, 495450191, // 860.5 - 869.5 -+ 506990708, 518800039, 530884444, 543250331, 555904257, -+ 568852931, 582103218, 595662144, 609536897, 623734835, // 870.5 - 879.5 -+ 638263486, 653130553, 668343918, 683911647, 699841996, -+ 716143410, 732824533, 749894209, 767361489, 785235635, // 880.5 - 889.5 -+ 803526122, 822242650, 841395142, 860993752, 881048873, -+ 901571138, 922571427, 944060876, 966050879, 988553095, // 890.5 - 899.5 -+ }; -+ s32 y; -+ int i; -+ -+ if (x == 0) -+ return 0; -+ y = 800; -+ if (x >= 1000000000) { -+ x /= 10; -+ y += 100; -+ } -+ -+ while (x < 100000000) { -+ x *= 10; -+ y -= 100; -+ } -+ i = 0; -+ while (i < 100 && x > LookupTable[i]) -+ i += 1; -+ y += i; -+ return y; -+} -+ -+static int QAM_GetSignalToNoise(struct stv_state *state, s32 *pSignalToNoise) -+{ -+ u32 RegValAvg = 0; -+ u8 RegVal[2]; -+ int status = 0, i; -+ -+ *pSignalToNoise = 0; -+ for (i = 0; i < 10; i += 1 ) { -+ readregs(state, R367_QAM_EQU_SNR_LO, RegVal, 2); -+ RegValAvg += RegVal[0] + 256 * RegVal[1]; -+ } -+ if (RegValAvg != 0) { -+ s32 Power = 1; -+ switch(state->modulation) { -+ case QAM_16: -+ Power = 20480; -+ break; -+ case QAM_32: -+ Power = 23040; -+ break; -+ case QAM_64: -+ Power = 21504; -+ break; -+ case QAM_128: -+ Power = 23616; -+ break; -+ case QAM_256: -+ Power = 21760; -+ break; -+ default: -+ break; -+ } -+ *pSignalToNoise = Log10x100((Power * 320) / RegValAvg); -+ } else { -+ *pSignalToNoise = 380; -+ } -+ return status; -+} -+ -+static int OFDM_GetSignalToNoise(struct stv_state *state, s32 *pSignalToNoise) -+{ -+ u8 CHC_SNR = 0; -+ -+ int status = readreg(state, R367_OFDM_CHC_SNR, &CHC_SNR); -+ if (status >= 0) { -+ // Note: very unclear documentation on this. -+ // Datasheet states snr = CHC_SNR/4 dB -> way to high values! -+ // Software snr = ( 1000 * CHC_SNR ) / 8 / 32 / 10; -> to low values -+ // Comment in SW states this should be ( 1000 * CHC_SNR ) / 4 / 32 / 10; for the 367 -+ // 361/362 Datasheet: snr = CHC_SNR/8 dB -> this looks best -+ *pSignalToNoise = ( (s32)CHC_SNR * 10) / 8; -+ } -+ //printk("SNR %d\n", *pSignalToNoise); -+ return status; -+} -+ -+#if 0 -+static int DVBC_GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) -+{ -+ *pQuality = 100; -+ return 0; -+}; -+ -+static int DVBT_GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) -+{ -+ static s32 QE_SN[] = { -+ 51, // QPSK 1/2 -+ 69, // QPSK 2/3 -+ 79, // QPSK 3/4 -+ 89, // QPSK 5/6 -+ 97, // QPSK 7/8 -+ 108, // 16-QAM 1/2 -+ 131, // 16-QAM 2/3 -+ 146, // 16-QAM 3/4 -+ 156, // 16-QAM 5/6 -+ 160, // 16-QAM 7/8 -+ 165, // 64-QAM 1/2 -+ 187, // 64-QAM 2/3 -+ 202, // 64-QAM 3/4 -+ 216, // 64-QAM 5/6 -+ 225, // 64-QAM 7/8 -+ }; -+ u8 TPS_Received[2]; -+ int Constellation; -+ int CodeRate; -+ s32 SignalToNoiseRel, BERQuality; -+ -+ *pQuality = 0; -+ readregs(state, R367_OFDM_TPS_RCVD2, TPS_Received, sizeof(TPS_Received)); -+ Constellation = TPS_Received[0] & 0x03; -+ CodeRate = TPS_Received[1] & 0x07; -+ -+ if( Constellation > 2 || CodeRate > 5 ) -+ return -1; -+ SignalToNoiseRel = SignalToNoise - QE_SN[Constellation * 5 + CodeRate]; -+ BERQuality = 100; -+ -+ if( SignalToNoiseRel < -70 ) -+ *pQuality = 0; -+ else if( SignalToNoiseRel < 30 ) { -+ *pQuality = ((SignalToNoiseRel + 70) * BERQuality)/100; -+ } else -+ *pQuality = BERQuality; -+ return 0; -+}; -+ -+static s32 DVBCQuality(struct stv_state *state, s32 SignalToNoise) -+{ -+ s32 SignalToNoiseRel = 0; -+ s32 Quality = 0; -+ s32 BERQuality = 100; -+ -+ switch(state->modulation) { -+ case QAM_16: SignalToNoiseRel = SignalToNoise - 200 ; break; -+ case QAM_32: SignalToNoiseRel = SignalToNoise - 230 ; break; // Not in NorDig -+ case QAM_64: SignalToNoiseRel = SignalToNoise - 260 ; break; -+ case QAM_128: SignalToNoiseRel = SignalToNoise - 290 ; break; -+ case QAM_256: SignalToNoiseRel = SignalToNoise - 320 ; break; -+ } -+ -+ if( SignalToNoiseRel < -70 ) Quality = 0; -+ else if( SignalToNoiseRel < 30 ) -+ { -+ Quality = ((SignalToNoiseRel + 70) * BERQuality)/100; -+ } -+ else -+ Quality = BERQuality; -+ -+ return Quality; -+} -+ -+static int GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) -+{ -+ *pQuality = 0; -+ switch(state->demod_state) -+ { -+ case QAMStarted: -+ *pQuality = DVBCQuality(state, SignalToNoise); -+ break; -+ case OFDMStarted: -+ return DVBT_GetQuality(state, SignalToNoise, pQuality); -+ } -+ return 0; -+}; -+#endif -+ -+static int attach_init(struct stv_state *state) -+{ -+ int stat = 0; -+ -+ stat = readreg(state, R367_ID, &state->ID); -+ if ( stat < 0 || state->ID != 0x60 ) -+ return -ENODEV; -+ printk("stv0367 found\n"); -+ -+ writereg(state, R367_TOPCTRL, 0x10); -+ write_init_table(state, base_init); -+ write_init_table(state, qam_init); -+ -+ writereg(state, R367_TOPCTRL, 0x00); -+ write_init_table(state, ofdm_init); -+ -+ writereg(state, R367_OFDM_GAIN_SRC1, 0x2A); -+ writereg(state, R367_OFDM_GAIN_SRC2, 0xD6); -+ writereg(state, R367_OFDM_INC_DEROT1, 0x55); -+ writereg(state, R367_OFDM_INC_DEROT2, 0x55); -+ writereg(state, R367_OFDM_TRL_CTL, 0x14); -+ writereg(state, R367_OFDM_TRL_NOMRATE1, 0xAE); -+ writereg(state, R367_OFDM_TRL_NOMRATE2, 0x56); -+ writereg(state, R367_OFDM_FEPATH_CFG, 0x0); -+ -+ // OFDM TS Setup -+ -+ writereg(state, R367_OFDM_TSCFGH, 0x70); -+ writereg(state, R367_OFDM_TSCFGM, 0xC0); -+ writereg(state, R367_OFDM_TSCFGL, 0x20); -+ writereg(state, R367_OFDM_TSSPEED, 0x40); // Fixed at 54 MHz -+ //writereg(state, R367_TSTBUS, 0x80); // Invert CLK -+ -+ writereg(state, R367_OFDM_TSCFGH, 0x71); -+ writereg(state, R367_OFDM_TSCFGH, 0x70); -+ -+ writereg(state, R367_TOPCTRL, 0x10); -+ -+ // Also needed for QAM -+ writereg(state, R367_OFDM_AGC12C, 0x01); // AGC Pin setup -+ -+ writereg(state, R367_OFDM_AGCCTRL1, 0x8A); // -+ -+ // QAM TS setup, note exact format also depends on descrambler settings -+ writereg(state, R367_QAM_OUTFORMAT_0, 0x85); // Inverted Clock, Swap, serial -+ // writereg(state, R367_QAM_OUTFORMAT_1, 0x00); // -+ -+ // Clock setup -+ writereg(state, R367_ANACTRL, 0x0D); /* PLL bypassed and disabled */ -+ -+ if( state->master_clock == 58000000 ) { -+ writereg(state, R367_PLLMDIV,27); /* IC runs at 58 MHz with a 27 MHz crystal */ -+ writereg(state, R367_PLLNDIV,232); -+ } else { -+ writereg(state, R367_PLLMDIV,1); /* IC runs at 54 MHz with a 27 MHz crystal */ -+ writereg(state, R367_PLLNDIV,8); -+ } -+ writereg(state, R367_PLLSETUP, 0x18); /* ADC clock is equal to system clock */ -+ -+ // Tuner setup -+ writereg(state, R367_ANADIGCTRL, 0x8b); /* Buffer Q disabled, I Enabled, signed ADC */ -+ writereg(state, R367_DUAL_AD12, 0x04); /* ADCQ disabled */ -+ -+ writereg(state, R367_QAM_FSM_SNR2_HTH, 0x23); /* Improves the C/N lock limit */ -+ writereg(state, R367_QAM_IQ_QAM, 0x01); /* ZIF/IF Automatic mode */ -+ writereg(state, R367_QAM_EQU_FFE_LEAKAGE, 0x83); /* Improving burst noise performances */ -+ writereg(state, R367_QAM_IQDEM_ADJ_EN, 0x05); /* Improving ACI performances */ -+ -+ writereg(state, R367_ANACTRL, 0x00); /* PLL enabled and used */ -+ -+ writereg(state, R367_I2CRPT, state->I2CRPT); -+ state->demod_state = QAMSet; -+ return stat; -+} -+ -+#ifdef USE_API3 -+static void c_release(struct dvb_frontend* fe) -+#else -+static void release(struct dvb_frontend* fe) -+#endif -+{ -+ struct stv_state *state=fe->demodulator_priv; -+ printk("%s\n", __FUNCTION__); -+ kfree(state); -+} -+ -+#ifdef USE_API3 -+static int c_init (struct dvb_frontend *fe) -+{ -+ struct stv_state *state=fe->demodulator_priv; -+ -+ if (mutex_trylock(&state->ctlock)==0) -+ return -EBUSY; -+ state->omode = OM_DVBC; -+ return 0; -+} -+ -+static int c_sleep(struct dvb_frontend* fe) -+{ -+ struct stv_state *state=fe->demodulator_priv; -+ -+ mutex_unlock(&state->ctlock); -+ return 0; -+} -+#endif -+ -+static int gate_ctrl(struct dvb_frontend *fe, int enable) -+{ -+ struct stv_state *state = fe->demodulator_priv; -+ u8 i2crpt = state->I2CRPT & ~0x80; -+ -+ if (enable) -+ i2crpt |= 0x80; -+ if (writereg(state, R367_I2CRPT, i2crpt) < 0) -+ return -1; -+ state->I2CRPT = i2crpt; -+ return 0; -+} -+ -+#if 0 -+static int c_track(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -+{ -+ return DVBFE_ALGO_SEARCH_AGAIN; -+} -+#endif -+ -+#if 0 -+int (*set_property)(struct dvb_frontend* fe, struct dtv_property* tvp); -+int (*get_property)(struct dvb_frontend* fe, struct dtv_property* tvp); -+#endif -+ -+static int ofdm_lock(struct stv_state *state) -+{ -+ int status = 0; -+ u8 OFDM_Status; -+ s32 DemodTimeOut = 10; -+ s32 FECTimeOut = 0; -+ s32 TSTimeOut = 0; -+ u8 CPAMPMin = 255; -+ u8 CPAMPValue; -+ u8 SYR_STAT; -+ u8 FFTMode; -+ u8 TSStatus; -+ -+ msleep(state->m_SignalTimeOut); -+ readreg(state, R367_OFDM_STATUS,&OFDM_Status); -+ -+ if (!(OFDM_Status & 0x40)) -+ return -1; -+ //printk("lock 1\n"); -+ -+ readreg(state, R367_OFDM_SYR_STAT,&SYR_STAT); -+ FFTMode = (SYR_STAT & 0x0C) >> 2; -+ -+ switch(FFTMode) -+ { -+ case 0: // 2K -+ DemodTimeOut = 10; -+ FECTimeOut = 150; -+ TSTimeOut = 125; -+ CPAMPMin = 20; -+ break; -+ case 1: // 8K -+ DemodTimeOut = 55; -+ FECTimeOut = 600; -+ TSTimeOut = 500; -+ CPAMPMin = 80; -+ break; -+ case 2: // 4K -+ DemodTimeOut = 40; -+ FECTimeOut = 300; -+ TSTimeOut = 250; -+ CPAMPMin = 30; -+ break; -+ } -+ state->m_OFDM_FFTMode = FFTMode; -+ readreg(state, R367_OFDM_PPM_CPAMP_DIR,&CPAMPValue); -+ msleep(DemodTimeOut); -+ { -+ // Release FEC and Read Solomon Reset -+ u8 tmp1; -+ u8 tmp2; -+ readreg(state, R367_OFDM_SFDLYSETH,&tmp1); -+ readreg(state, R367_TSGENERAL,&tmp2); -+ writereg(state, R367_OFDM_SFDLYSETH,tmp1 & ~0x08); -+ writereg(state, R367_TSGENERAL,tmp2 & ~0x01); -+ } -+ msleep(FECTimeOut); -+ if( (OFDM_Status & 0x98) != 0x98 ) -+ ;//return -1; -+ //printk("lock 2\n"); -+ -+ { -+ u8 Guard = (SYR_STAT & 0x03); -+ if(Guard < 2) -+ { -+ u8 tmp; -+ readreg(state, R367_OFDM_SYR_CTL,&tmp); -+ writereg(state, R367_OFDM_SYR_CTL,tmp & ~0x04); // Clear AUTO_LE_EN -+ readreg(state, R367_OFDM_SYR_UPDATE,&tmp); -+ writereg(state, R367_OFDM_SYR_UPDATE,tmp & ~0x10); // Clear SYR_FILTER -+ } else { -+ u8 tmp; -+ readreg(state, R367_OFDM_SYR_CTL,&tmp); -+ writereg(state, R367_OFDM_SYR_CTL,tmp | 0x04); // Set AUTO_LE_EN -+ readreg(state, R367_OFDM_SYR_UPDATE,&tmp); -+ writereg(state, R367_OFDM_SYR_UPDATE,tmp | 0x10); // Set SYR_FILTER -+ } -+ -+ // apply Sfec workaround if 8K 64QAM CR!=1/2 -+ if( FFTMode == 1) -+ { -+ u8 tmp[2]; -+ readregs(state, R367_OFDM_TPS_RCVD2, tmp, 2); -+ if( ((tmp[0] & 0x03) == 0x02) && (( tmp[1] & 0x07 ) != 0) ) -+ { -+ writereg(state, R367_OFDM_SFDLYSETH,0xc0); -+ writereg(state, R367_OFDM_SFDLYSETM,0x60); -+ writereg(state, R367_OFDM_SFDLYSETL,0x00); -+ } -+ else -+ { -+ writereg(state, R367_OFDM_SFDLYSETH,0x00); -+ } -+ } -+ } -+ msleep(TSTimeOut); -+ readreg(state, R367_OFDM_TSSTATUS,&TSStatus); -+ if( (TSStatus & 0x80) != 0x80 ) -+ return -1; -+ //printk("lock 3\n"); -+ return status; -+} -+ -+ -+#ifdef USE_API3 -+static int set_parameters(struct dvb_frontend *fe, -+ struct dvb_frontend_parameters *p) -+{ -+ int stat; -+ struct stv_state *state = fe->demodulator_priv; -+ u32 OF = 0; -+ u32 IF; -+ -+ if (fe->ops.tuner_ops.set_params) -+ fe->ops.tuner_ops.set_params(fe, p); -+ -+ switch (state->omode) { -+ case OM_DVBC: -+ case OM_QAM_ITU_C: -+ state->modulation = p->u.qam.modulation; -+ state->symbol_rate = p->u.qam.symbol_rate; -+ break; -+ case OM_DVBT: -+ switch (p->u.ofdm.bandwidth) { -+ case BANDWIDTH_AUTO: -+ case BANDWIDTH_8_MHZ: -+ state->bandwidth = 8000000; -+ break; -+ case BANDWIDTH_7_MHZ: -+ state->bandwidth = 7000000; -+ break; -+ case BANDWIDTH_6_MHZ: -+ state->bandwidth = 6000000; -+ break; -+ default: -+ return -EINVAL; -+ } -+ break; -+ default: -+ return -EINVAL; -+ } -+#else -+static int set_parameters(struct dvb_frontend *fe) -+{ -+ int stat; -+ struct stv_state *state = fe->demodulator_priv; -+ u32 OF = 0; -+ u32 IF; -+ -+ switch (fe->dtv_property_cache.delivery_system) { -+ case SYS_DVBC_ANNEX_A: -+ state->omode = OM_DVBC; -+ /* symbol rate 0 might cause an oops */ -+ if (fe->dtv_property_cache.symbol_rate == 0) { -+ printk(KERN_ERR "stv0367dd: Invalid symbol rate\n"); -+ return -EINVAL; -+ } -+ break; -+ case SYS_DVBT: -+ state->omode = OM_DVBT; -+ break; -+ default: -+ return -EINVAL; -+ } -+ if (fe->ops.tuner_ops.set_params) -+ fe->ops.tuner_ops.set_params(fe); -+ state->modulation = fe->dtv_property_cache.modulation; -+ state->symbol_rate = fe->dtv_property_cache.symbol_rate; -+ state->bandwidth = fe->dtv_property_cache.bandwidth_hz; -+#endif -+ fe->ops.tuner_ops.get_if_frequency(fe, &IF); -+ //fe->ops.tuner_ops.get_frequency(fe, &IF); -+ -+ switch(state->omode) { -+ case OM_DVBT: -+ stat = OFDM_Start(state, OF, IF); -+ ofdm_lock(state); -+ break; -+ case OM_DVBC: -+ case OM_QAM_ITU_C: -+ stat = QAM_Start(state, OF, IF); -+ break; -+ default: -+ stat = -EINVAL; -+ } -+ //printk("%s IF=%d OF=%d done\n", __FUNCTION__, IF, OF); -+ return stat; -+} -+ -+#if 0 -+static int c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -+{ -+ //struct stv_state *state = fe->demodulator_priv; -+ //printk("%s\n", __FUNCTION__); -+ return 0; -+} -+ -+static int OFDM_GetLockStatus(struct stv_state *state, LOCK_STATUS* pLockStatus, s32 Time) -+{ -+ int status = STATUS_SUCCESS; -+ u8 OFDM_Status; -+ s32 DemodTimeOut = 0; -+ s32 FECTimeOut = 0; -+ s32 TSTimeOut = 0; -+ u8 CPAMPMin = 255; -+ u8 CPAMPValue; -+ bool SYRLock; -+ u8 SYR_STAT; -+ u8 FFTMode; -+ u8 TSStatus; -+ -+ readreg(state, R367_OFDM_STATUS,&OFDM_Status); -+ -+ SYRLock = (OFDM_Status & 0x40) != 0; -+ -+ if( Time > m_SignalTimeOut && !SYRLock ) -+ { -+ *pLockStatus = NEVER_LOCK; -+ break; -+ } -+ -+ if( !SYRLock ) break; -+ -+ *pLockStatus = SIGNAL_PRESENT; -+ -+ // Check Mode -+ -+ readreg(state, R367_OFDM_SYR_STAT,&SYR_STAT); -+ FFTMode = (SYR_STAT & 0x0C) >> 2; -+ -+ switch(FFTMode) -+ { -+ case 0: // 2K -+ DemodTimeOut = 10; -+ FECTimeOut = 150; -+ TSTimeOut = 125; -+ CPAMPMin = 20; -+ break; -+ case 1: // 8K -+ DemodTimeOut = 55; -+ FECTimeOut = 600; -+ TSTimeOut = 500; -+ CPAMPMin = 80; -+ break; -+ case 2: // 4K -+ DemodTimeOut = 40; -+ FECTimeOut = 300; -+ TSTimeOut = 250; -+ CPAMPMin = 30; -+ break; -+ } -+ -+ m_OFDM_FFTMode = FFTMode; -+ -+ if( m_DemodTimeOut == 0 && m_bFirstTimeLock ) -+ { -+ m_DemodTimeOut = Time + DemodTimeOut; -+ //break; -+ } -+ -+ readreg(state, R367_OFDM_PPM_CPAMP_DIR,&CPAMPValue); -+ -+ if( Time <= m_DemodTimeOut && CPAMPValue < CPAMPMin ) -+ { -+ break; -+ } -+ -+ if( CPAMPValue < CPAMPMin && m_bFirstTimeLock ) -+ { -+ // initiate retry -+ *pLockStatus = NEVER_LOCK; -+ break; -+ } -+ -+ if( CPAMPValue < CPAMPMin ) break; -+ -+ *pLockStatus = DEMOD_LOCK; -+ -+ if( m_FECTimeOut == 0 && m_bFirstTimeLock ) -+ { -+ // Release FEC and Read Solomon Reset -+ u8 tmp1; -+ u8 tmp2; -+ readreg(state, R367_OFDM_SFDLYSETH,&tmp1); -+ readreg(state, R367_TSGENERAL,&tmp2); -+ writereg(state, R367_OFDM_SFDLYSETH,tmp1 & ~0x08); -+ writereg(state, R367_TSGENERAL,tmp2 & ~0x01); -+ -+ m_FECTimeOut = Time + FECTimeOut; -+ } -+ -+ // Wait for TSP_LOCK, LK, PRF -+ if( (OFDM_Status & 0x98) != 0x98 ) -+ { -+ if( Time > m_FECTimeOut ) *pLockStatus = NEVER_LOCK; -+ break; -+ } -+ -+ if( m_bFirstTimeLock && m_TSTimeOut == 0) -+ { -+ u8 Guard = (SYR_STAT & 0x03); -+ if(Guard < 2) -+ { -+ u8 tmp; -+ readreg(state, R367_OFDM_SYR_CTL,&tmp); -+ writereg(state, R367_OFDM_SYR_CTL,tmp & ~0x04); // Clear AUTO_LE_EN -+ readreg(state, R367_OFDM_SYR_UPDATE,&tmp); -+ writereg(state, R367_OFDM_SYR_UPDATE,tmp & ~0x10); // Clear SYR_FILTER -+ } else { -+ u8 tmp; -+ readreg(state, R367_OFDM_SYR_CTL,&tmp); -+ writereg(state, R367_OFDM_SYR_CTL,tmp | 0x04); // Set AUTO_LE_EN -+ readreg(state, R367_OFDM_SYR_UPDATE,&tmp); -+ writereg(state, R367_OFDM_SYR_UPDATE,tmp | 0x10); // Set SYR_FILTER -+ } -+ -+ // apply Sfec workaround if 8K 64QAM CR!=1/2 -+ if( FFTMode == 1) -+ { -+ u8 tmp[2]; -+ readreg(state, R367_OFDM_TPS_RCVD2,tmp,2); -+ if( ((tmp[0] & 0x03) == 0x02) && (( tmp[1] & 0x07 ) != 0) ) -+ { -+ writereg(state, R367_OFDM_SFDLYSETH,0xc0); -+ writereg(state, R367_OFDM_SFDLYSETM,0x60); -+ writereg(state, R367_OFDM_SFDLYSETL,0x00); -+ } -+ else -+ { -+ writereg(state, R367_OFDM_SFDLYSETH,0x00); -+ } -+ } -+ -+ m_TSTimeOut = Time + TSTimeOut; -+ } -+ readreg(state, R367_OFDM_TSSTATUS,&TSStatus); -+ if( (TSStatus & 0x80) != 0x80 ) -+ { -+ if( Time > m_TSTimeOut ) *pLockStatus = NEVER_LOCK; -+ break; -+ } -+ *pLockStatus = MPEG_LOCK; -+ m_bFirstTimeLock = false; -+ return status; -+} -+ -+#endif -+ -+static int read_status(struct dvb_frontend *fe, fe_status_t *status) -+{ -+ struct stv_state *state = fe->demodulator_priv; -+ *status=0; -+ -+ switch(state->demod_state) { -+ case QAMStarted: -+ { -+ u8 FEC_Lock; -+ u8 QAM_Lock; -+ -+ readreg(state, R367_QAM_FSM_STS, &QAM_Lock); -+ QAM_Lock &= 0x0F; -+ if (QAM_Lock >10) -+ *status|=0x07; -+ readreg(state, R367_QAM_FEC_STATUS,&FEC_Lock); -+ if (FEC_Lock&2) -+ *status|=0x1f; -+ if (state->m_bFirstTimeLock) { -+ state->m_bFirstTimeLock = false; -+ // QAM_AGC_ACCUMRSTSEL to Tracking; -+ writereg(state, R367_QAM_AGC_CTL, state->m_Save_QAM_AGC_CTL); -+ } -+ break; -+ } -+ case OFDMStarted: -+ { -+ u8 OFDM_Status; -+ u8 TSStatus; -+ -+ readreg(state, R367_OFDM_TSSTATUS, &TSStatus); -+ -+ readreg(state, R367_OFDM_STATUS, &OFDM_Status); -+ if (OFDM_Status & 0x40) -+ *status |= FE_HAS_SIGNAL; -+ -+ if ((OFDM_Status & 0x98) == 0x98) -+ *status|=0x0f; -+ -+ if (TSStatus & 0x80) -+ *status |= 0x1f; -+ break; -+ } -+ default: -+ break; -+ } -+ return 0; -+} -+ -+static int read_ber_ter(struct dvb_frontend *fe, u32 *ber) -+{ -+ struct stv_state *state = fe->demodulator_priv; -+ u32 err; -+ u8 cnth, cntm, cntl; -+ -+#if 1 -+ readreg(state, R367_OFDM_SFERRCNTH, &cnth); -+ -+ if (cnth & 0x80) { -+ *ber = state->ber; -+ return 0; -+ } -+ -+ readreg(state, R367_OFDM_SFERRCNTM, &cntm); -+ readreg(state, R367_OFDM_SFERRCNTL, &cntl); -+ -+ err = ((cnth & 0x7f) << 16) | (cntm << 8) | cntl; -+ -+#if 0 -+ { -+ u64 err64; -+ err64 = (u64) err; -+ err64 *= 1000000000ULL; -+ err64 >>= 21; -+ err = err64; -+ } -+#endif -+#else -+ readreg(state, R367_OFDM_ERRCNT1HM, &cnth); -+ -+#endif -+ *ber = state->ber = err; -+ return 0; -+} -+ -+static int read_ber_cab(struct dvb_frontend *fe, u32 *ber) -+{ -+ struct stv_state *state = fe->demodulator_priv; -+ u32 err; -+ u8 cntm, cntl, ctrl; -+ -+ readreg(state, R367_QAM_BERT_1, &ctrl); -+ if (!(ctrl & 0x20)) { -+ readreg(state, R367_QAM_BERT_2, &cntl); -+ readreg(state, R367_QAM_BERT_3, &cntm); -+ err = (cntm << 8) | cntl; -+ //printk("err %04x\n", err); -+ state->ber = err; -+ writereg(state, R367_QAM_BERT_1, 0x27); -+ } -+ *ber = (u32) state->ber; -+ return 0; -+} -+ -+static int read_ber(struct dvb_frontend *fe, u32 *ber) -+{ -+ struct stv_state *state = fe->demodulator_priv; -+ -+ if (state->demod_state == QAMStarted) -+ return read_ber_cab(fe, ber); -+ if (state->demod_state == OFDMStarted) -+ return read_ber_ter(fe, ber); -+ *ber = 0; -+ return 0; -+} -+ -+static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) -+{ -+ if (fe->ops.tuner_ops.get_rf_strength) -+ fe->ops.tuner_ops.get_rf_strength(fe, strength); -+ else -+ *strength = 0; -+ return 0; -+} -+ -+static int read_snr(struct dvb_frontend *fe, u16 *snr) -+{ -+ struct stv_state *state = fe->demodulator_priv; -+ s32 snr2 = 0; -+ -+ switch(state->demod_state) { -+ case QAMStarted: -+ QAM_GetSignalToNoise(state, &snr2); -+ break; -+ case OFDMStarted: -+ OFDM_GetSignalToNoise(state, &snr2); -+ break; -+ default: -+ break; -+ } -+ *snr = snr2&0xffff; -+ return 0; -+} -+ -+static int read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) -+{ -+ struct stv_state *state = fe->demodulator_priv; -+ u8 errl, errm, errh; -+ u8 val; -+ -+ switch(state->demod_state) { -+ case QAMStarted: -+ readreg(state, R367_QAM_RS_COUNTER_4, &errl); -+ readreg(state, R367_QAM_RS_COUNTER_5, &errm); -+ *ucblocks = (errm << 8) | errl; -+ break; -+ case OFDMStarted: -+ readreg(state, R367_OFDM_SFERRCNTH, &val); -+ if ((val & 0x80) == 0) { -+ readreg(state, R367_OFDM_ERRCNT1H, &errh); -+ readreg(state, R367_OFDM_ERRCNT1M, &errl); -+ readreg(state, R367_OFDM_ERRCNT1L, &errm); -+ state->ucblocks = (errh <<16) | (errm << 8) | errl; -+ } -+ *ucblocks = state->ucblocks; -+ break; -+ default: -+ *ucblocks = 0; -+ break; -+ } -+ return 0; -+} -+ -+static int c_get_tune_settings(struct dvb_frontend *fe, -+ struct dvb_frontend_tune_settings *sets) -+{ -+ sets->min_delay_ms=3000; -+ sets->max_drift=0; -+ sets->step_size=0; -+ return 0; -+} -+ -+#ifndef USE_API3 -+static int get_tune_settings(struct dvb_frontend *fe, -+ struct dvb_frontend_tune_settings *sets) -+{ -+ switch (fe->dtv_property_cache.delivery_system) { -+ case SYS_DVBC_ANNEX_A: -+ case SYS_DVBC_ANNEX_C: -+ return c_get_tune_settings(fe, sets); -+ default: -+ /* DVB-T: Use info.frequency_stepsize. */ -+ return -EINVAL; -+ } -+} -+#endif -+ -+#ifdef USE_API3 -+static void t_release(struct dvb_frontend* fe) -+{ -+ //struct stv_state *state=fe->demodulator_priv; -+ //printk("%s\n", __FUNCTION__); -+ //kfree(state); -+} -+ -+static int t_init (struct dvb_frontend *fe) -+{ -+ struct stv_state *state=fe->demodulator_priv; -+ if (mutex_trylock(&state->ctlock)==0) -+ return -EBUSY; -+ state->omode = OM_DVBT; -+ return 0; -+} -+ -+static int t_sleep(struct dvb_frontend* fe) -+{ -+ struct stv_state *state=fe->demodulator_priv; -+ mutex_unlock(&state->ctlock); -+ return 0; -+} -+#endif -+ -+#if 0 -+static int t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) -+{ -+ //struct stv_state *state = fe->demodulator_priv; -+ //printk("%s\n", __FUNCTION__); -+ return 0; -+} -+ -+static enum dvbfe_algo algo(struct dvb_frontend *fe) -+{ -+ return DVBFE_ALGO_CUSTOM; -+} -+#endif -+ -+#ifdef USE_API3 -+static struct dvb_frontend_ops c_ops = { -+ .info = { -+ .name = "STV0367 DVB-C", -+ .type = FE_QAM, -+ .frequency_stepsize = 62500, -+ .frequency_min = 47000000, -+ .frequency_max = 862000000, -+ .symbol_rate_min = 870000, -+ .symbol_rate_max = 11700000, -+ .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | -+ FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO -+ }, -+ .release = c_release, -+ .init = c_init, -+ .sleep = c_sleep, -+ .i2c_gate_ctrl = gate_ctrl, -+ -+ .get_tune_settings = c_get_tune_settings, -+ -+ .read_status = read_status, -+ .read_ber = read_ber, -+ .read_signal_strength = read_signal_strength, -+ .read_snr = read_snr, -+ .read_ucblocks = read_ucblocks, -+ -+#if 1 -+ .set_frontend = set_parameters, -+#else -+ .get_frontend_algo = algo, -+ .search = search, -+#endif -+}; -+ -+static struct dvb_frontend_ops t_ops = { -+ .info = { -+ .name = "STV0367 DVB-T", -+ .type = FE_OFDM, -+ .frequency_min = 47125000, -+ .frequency_max = 865000000, -+ .frequency_stepsize = 166667, -+ .frequency_tolerance = 0, -+ .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | -+ FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | -+ FE_CAN_FEC_AUTO | -+ FE_CAN_QAM_16 | FE_CAN_QAM_64 | -+ FE_CAN_QAM_AUTO | -+ FE_CAN_TRANSMISSION_MODE_AUTO | -+ FE_CAN_GUARD_INTERVAL_AUTO | -+ FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | -+ FE_CAN_MUTE_TS -+ }, -+ .release = t_release, -+ .init = t_init, -+ .sleep = t_sleep, -+ .i2c_gate_ctrl = gate_ctrl, -+ -+ .set_frontend = set_parameters, -+ -+ .read_status = read_status, -+ .read_ber = read_ber, -+ .read_signal_strength = read_signal_strength, -+ .read_snr = read_snr, -+ .read_ucblocks = read_ucblocks, -+}; -+ -+#else -+ -+static struct dvb_frontend_ops common_ops = { -+ .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT }, -+ .info = { -+ .name = "STV0367 DVB-C DVB-T", -+ .frequency_stepsize = 166667, /* DVB-T only */ -+ .frequency_min = 47000000, /* DVB-T: 47125000 */ -+ .frequency_max = 865000000, /* DVB-C: 862000000 */ -+ .symbol_rate_min = 870000, -+ .symbol_rate_max = 11700000, -+ .caps = /* DVB-C */ -+ FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | -+ FE_CAN_QAM_128 | FE_CAN_QAM_256 | -+ FE_CAN_FEC_AUTO | -+ /* DVB-T */ -+ FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | -+ FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | -+ FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | -+ FE_CAN_TRANSMISSION_MODE_AUTO | -+ FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | -+ FE_CAN_RECOVER | FE_CAN_MUTE_TS -+ }, -+ .release = release, -+ .i2c_gate_ctrl = gate_ctrl, -+ -+ .get_tune_settings = get_tune_settings, -+ -+ .set_frontend = set_parameters, -+ -+ .read_status = read_status, -+ .read_ber = read_ber, -+ .read_signal_strength = read_signal_strength, -+ .read_snr = read_snr, -+ .read_ucblocks = read_ucblocks, -+}; -+#endif -+ -+ -+static void init_state(struct stv_state *state, struct stv0367_cfg *cfg) -+{ -+ u32 ulENARPTLEVEL = 5; -+ u32 ulQAMInversion = 2; -+ state->omode = OM_NONE; -+ state->adr = cfg->adr; -+ -+ mutex_init(&state->mutex); -+ mutex_init(&state->ctlock); -+ -+#ifdef USE_API3 -+ memcpy(&state->c_frontend.ops, &c_ops, sizeof(struct dvb_frontend_ops)); -+ memcpy(&state->t_frontend.ops, &t_ops, sizeof(struct dvb_frontend_ops)); -+ state->c_frontend.demodulator_priv = state; -+ state->t_frontend.demodulator_priv = state; -+#else -+ memcpy(&state->frontend.ops, &common_ops, sizeof(struct dvb_frontend_ops)); -+ state->frontend.demodulator_priv = state; -+#endif -+ -+ state->master_clock = 58000000; -+ state->adc_clock = 58000000; -+ state->I2CRPT = 0x08 | ((ulENARPTLEVEL & 0x07) << 4); -+ state->qam_inversion = ((ulQAMInversion & 3) << 6 ); -+ state->demod_state = Off; -+} -+ -+ -+struct dvb_frontend *stv0367_attach(struct i2c_adapter *i2c, struct stv0367_cfg *cfg, -+ struct dvb_frontend **fe_t) -+{ -+ struct stv_state *state = NULL; -+ -+ state = kzalloc(sizeof(struct stv_state), GFP_KERNEL); -+ if (!state) -+ return NULL; -+ -+ state->i2c = i2c; -+ init_state(state, cfg); -+ -+ if (attach_init(state)<0) -+ goto error; -+#ifdef USE_API3 -+ *fe_t = &state->t_frontend; -+ return &state->c_frontend; -+#else -+ return &state->frontend; -+#endif -+ -+error: -+ printk("stv0367: not found\n"); -+ kfree(state); -+ return NULL; -+} -+ -+ -+MODULE_DESCRIPTION("STV0367DD driver"); -+MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); -+MODULE_LICENSE("GPL"); -+ -+EXPORT_SYMBOL(stv0367_attach); -+ -+ -+ ++/* ++ * stv0367dd: STV0367 DVB-C/T demodulator driver ++ * ++ * Copyright (C) 2011 Digital Devices GmbH ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 only, as published by the Free Software Foundation. ++ * ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA ++ * 02110-1301, USA ++ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "dvb_frontend.h" ++#include "stv0367dd.h" ++#include "stv0367dd_regs.h" ++ ++enum omode { OM_NONE, OM_DVBT, OM_DVBC, OM_QAM_ITU_C }; ++enum { QAM_MOD_QAM4 = 0, ++ QAM_MOD_QAM16, ++ QAM_MOD_QAM32, ++ QAM_MOD_QAM64, ++ QAM_MOD_QAM128, ++ QAM_MOD_QAM256, ++ QAM_MOD_QAM512, ++ QAM_MOD_QAM1024 ++}; ++ ++enum {QAM_SPECT_NORMAL, QAM_SPECT_INVERTED }; ++ ++enum { ++ QAM_FEC_A = 1, /* J83 Annex A */ ++ QAM_FEC_B = (1<<1), /* J83 Annex B */ ++ QAM_FEC_C = (1<<2) /* J83 Annex C */ ++}; ++ ++enum EDemodState { Off, QAMSet, OFDMSet, QAMStarted, OFDMStarted }; ++ ++struct stv_state { ++#ifdef USE_API3 ++ struct dvb_frontend c_frontend; ++ struct dvb_frontend t_frontend; ++#else ++ struct dvb_frontend frontend; ++#endif ++ fe_modulation_t modulation; ++ u32 symbol_rate; ++ u32 bandwidth; ++ struct device *dev; ++ ++ struct i2c_adapter *i2c; ++ u8 adr; ++ void *priv; ++ ++ struct mutex mutex; ++ struct mutex ctlock; ++ ++ u32 master_clock; ++ u32 adc_clock; ++ u8 ID; ++ u8 I2CRPT; ++ u32 omode; ++ u8 qam_inversion; ++ ++ s32 IF; ++ ++ s32 m_FECTimeOut; ++ s32 m_DemodTimeOut; ++ s32 m_SignalTimeOut; ++ s32 m_DemodLockTime; ++ s32 m_FFTTimeOut; ++ s32 m_TSTimeOut; ++ ++ bool m_bFirstTimeLock; ++ ++ u8 m_Save_QAM_AGC_CTL; ++ ++ enum EDemodState demod_state; ++ ++ u8 m_OFDM_FFTMode; // 0 = 2k, 1 = 8k, 2 = 4k ++ u8 m_OFDM_Modulation; // ++ u8 m_OFDM_FEC; // ++ u8 m_OFDM_Guard; ++ ++ u32 ucblocks; ++ u32 ber; ++}; ++ ++struct init_table { ++ u16 adr; ++ u8 data; ++}; ++ ++struct init_table base_init[] = { ++ { R367_IOCFG0, 0x80 }, ++ { R367_DAC0R, 0x00 }, ++ { R367_IOCFG1, 0x00 }, ++ { R367_DAC1R, 0x00 }, ++ { R367_IOCFG2, 0x00 }, ++ { R367_SDFR, 0x00 }, ++ { R367_AUX_CLK, 0x00 }, ++ { R367_FREESYS1, 0x00 }, ++ { R367_FREESYS2, 0x00 }, ++ { R367_FREESYS3, 0x00 }, ++ { R367_GPIO_CFG, 0x55 }, ++ { R367_GPIO_CMD, 0x01 }, ++ { R367_TSTRES, 0x00 }, ++ { R367_ANACTRL, 0x00 }, ++ { R367_TSTBUS, 0x00 }, ++ { R367_RF_AGC2, 0x20 }, ++ { R367_ANADIGCTRL, 0x0b }, ++ { R367_PLLMDIV, 0x01 }, ++ { R367_PLLNDIV, 0x08 }, ++ { R367_PLLSETUP, 0x18 }, ++ { R367_DUAL_AD12, 0x04 }, ++ { R367_TSTBIST, 0x00 }, ++ { 0x0000, 0x00 } ++}; ++ ++struct init_table qam_init[] = { ++ { R367_QAM_CTRL_1, 0x06 },// Orginal 0x04 ++ { R367_QAM_CTRL_2, 0x03 }, ++ { R367_QAM_IT_STATUS1, 0x2b }, ++ { R367_QAM_IT_STATUS2, 0x08 }, ++ { R367_QAM_IT_EN1, 0x00 }, ++ { R367_QAM_IT_EN2, 0x00 }, ++ { R367_QAM_CTRL_STATUS, 0x04 }, ++ { R367_QAM_TEST_CTL, 0x00 }, ++ { R367_QAM_AGC_CTL, 0x73 }, ++ { R367_QAM_AGC_IF_CFG, 0x50 }, ++ { R367_QAM_AGC_RF_CFG, 0x02 },// RF Freeze ++ { R367_QAM_AGC_PWM_CFG, 0x03 }, ++ { R367_QAM_AGC_PWR_REF_L, 0x5a }, ++ { R367_QAM_AGC_PWR_REF_H, 0x00 }, ++ { R367_QAM_AGC_RF_TH_L, 0xff }, ++ { R367_QAM_AGC_RF_TH_H, 0x07 }, ++ { R367_QAM_AGC_IF_LTH_L, 0x00 }, ++ { R367_QAM_AGC_IF_LTH_H, 0x08 }, ++ { R367_QAM_AGC_IF_HTH_L, 0xff }, ++ { R367_QAM_AGC_IF_HTH_H, 0x07 }, ++ { R367_QAM_AGC_PWR_RD_L, 0xa0 }, ++ { R367_QAM_AGC_PWR_RD_M, 0xe9 }, ++ { R367_QAM_AGC_PWR_RD_H, 0x03 }, ++ { R367_QAM_AGC_PWM_IFCMD_L, 0xe4 }, ++ { R367_QAM_AGC_PWM_IFCMD_H, 0x00 }, ++ { R367_QAM_AGC_PWM_RFCMD_L, 0xff }, ++ { R367_QAM_AGC_PWM_RFCMD_H, 0x07 }, ++ { R367_QAM_IQDEM_CFG, 0x01 }, ++ { R367_QAM_MIX_NCO_LL, 0x22 }, ++ { R367_QAM_MIX_NCO_HL, 0x96 }, ++ { R367_QAM_MIX_NCO_HH, 0x55 }, ++ { R367_QAM_SRC_NCO_LL, 0xff }, ++ { R367_QAM_SRC_NCO_LH, 0x0c }, ++ { R367_QAM_SRC_NCO_HL, 0xf5 }, ++ { R367_QAM_SRC_NCO_HH, 0x20 }, ++ { R367_QAM_IQDEM_GAIN_SRC_L, 0x06 }, ++ { R367_QAM_IQDEM_GAIN_SRC_H, 0x01 }, ++ { R367_QAM_IQDEM_DCRM_CFG_LL, 0xfe }, ++ { R367_QAM_IQDEM_DCRM_CFG_LH, 0xff }, ++ { R367_QAM_IQDEM_DCRM_CFG_HL, 0x0f }, ++ { R367_QAM_IQDEM_DCRM_CFG_HH, 0x00 }, ++ { R367_QAM_IQDEM_ADJ_COEFF0, 0x34 }, ++ { R367_QAM_IQDEM_ADJ_COEFF1, 0xae }, ++ { R367_QAM_IQDEM_ADJ_COEFF2, 0x46 }, ++ { R367_QAM_IQDEM_ADJ_COEFF3, 0x77 }, ++ { R367_QAM_IQDEM_ADJ_COEFF4, 0x96 }, ++ { R367_QAM_IQDEM_ADJ_COEFF5, 0x69 }, ++ { R367_QAM_IQDEM_ADJ_COEFF6, 0xc7 }, ++ { R367_QAM_IQDEM_ADJ_COEFF7, 0x01 }, ++ { R367_QAM_IQDEM_ADJ_EN, 0x04 }, ++ { R367_QAM_IQDEM_ADJ_AGC_REF, 0x94 }, ++ { R367_QAM_ALLPASSFILT1, 0xc9 }, ++ { R367_QAM_ALLPASSFILT2, 0x2d }, ++ { R367_QAM_ALLPASSFILT3, 0xa3 }, ++ { R367_QAM_ALLPASSFILT4, 0xfb }, ++ { R367_QAM_ALLPASSFILT5, 0xf6 }, ++ { R367_QAM_ALLPASSFILT6, 0x45 }, ++ { R367_QAM_ALLPASSFILT7, 0x6f }, ++ { R367_QAM_ALLPASSFILT8, 0x7e }, ++ { R367_QAM_ALLPASSFILT9, 0x05 }, ++ { R367_QAM_ALLPASSFILT10, 0x0a }, ++ { R367_QAM_ALLPASSFILT11, 0x51 }, ++ { R367_QAM_TRL_AGC_CFG, 0x20 }, ++ { R367_QAM_TRL_LPF_CFG, 0x28 }, ++ { R367_QAM_TRL_LPF_ACQ_GAIN, 0x44 }, ++ { R367_QAM_TRL_LPF_TRK_GAIN, 0x22 }, ++ { R367_QAM_TRL_LPF_OUT_GAIN, 0x03 }, ++ { R367_QAM_TRL_LOCKDET_LTH, 0x04 }, ++ { R367_QAM_TRL_LOCKDET_HTH, 0x11 }, ++ { R367_QAM_TRL_LOCKDET_TRGVAL, 0x20 }, ++ { R367_QAM_IQ_QAM, 0x01 }, ++ { R367_QAM_FSM_STATE, 0xa0 }, ++ { R367_QAM_FSM_CTL, 0x08 }, ++ { R367_QAM_FSM_STS, 0x0c }, ++ { R367_QAM_FSM_SNR0_HTH, 0x00 }, ++ { R367_QAM_FSM_SNR1_HTH, 0x00 }, ++ { R367_QAM_FSM_SNR2_HTH, 0x00 }, ++ { R367_QAM_FSM_SNR0_LTH, 0x00 }, ++ { R367_QAM_FSM_SNR1_LTH, 0x00 }, ++ { R367_QAM_FSM_EQA1_HTH, 0x00 }, ++ { R367_QAM_FSM_TEMPO, 0x32 }, ++ { R367_QAM_FSM_CONFIG, 0x03 }, ++ { R367_QAM_EQU_I_TESTTAP_L, 0x11 }, ++ { R367_QAM_EQU_I_TESTTAP_M, 0x00 }, ++ { R367_QAM_EQU_I_TESTTAP_H, 0x00 }, ++ { R367_QAM_EQU_TESTAP_CFG, 0x00 }, ++ { R367_QAM_EQU_Q_TESTTAP_L, 0xff }, ++ { R367_QAM_EQU_Q_TESTTAP_M, 0x00 }, ++ { R367_QAM_EQU_Q_TESTTAP_H, 0x00 }, ++ { R367_QAM_EQU_TAP_CTRL, 0x00 }, ++ { R367_QAM_EQU_CTR_CRL_CONTROL_L, 0x11 }, ++ { R367_QAM_EQU_CTR_CRL_CONTROL_H, 0x05 }, ++ { R367_QAM_EQU_CTR_HIPOW_L, 0x00 }, ++ { R367_QAM_EQU_CTR_HIPOW_H, 0x00 }, ++ { R367_QAM_EQU_I_EQU_LO, 0xef }, ++ { R367_QAM_EQU_I_EQU_HI, 0x00 }, ++ { R367_QAM_EQU_Q_EQU_LO, 0xee }, ++ { R367_QAM_EQU_Q_EQU_HI, 0x00 }, ++ { R367_QAM_EQU_MAPPER, 0xc5 }, ++ { R367_QAM_EQU_SWEEP_RATE, 0x80 }, ++ { R367_QAM_EQU_SNR_LO, 0x64 }, ++ { R367_QAM_EQU_SNR_HI, 0x03 }, ++ { R367_QAM_EQU_GAMMA_LO, 0x00 }, ++ { R367_QAM_EQU_GAMMA_HI, 0x00 }, ++ { R367_QAM_EQU_ERR_GAIN, 0x36 }, ++ { R367_QAM_EQU_RADIUS, 0xaa }, ++ { R367_QAM_EQU_FFE_MAINTAP, 0x00 }, ++ { R367_QAM_EQU_FFE_LEAKAGE, 0x63 }, ++ { R367_QAM_EQU_FFE_MAINTAP_POS, 0xdf }, ++ { R367_QAM_EQU_GAIN_WIDE, 0x88 }, ++ { R367_QAM_EQU_GAIN_NARROW, 0x41 }, ++ { R367_QAM_EQU_CTR_LPF_GAIN, 0xd1 }, ++ { R367_QAM_EQU_CRL_LPF_GAIN, 0xa7 }, ++ { R367_QAM_EQU_GLOBAL_GAIN, 0x06 }, ++ { R367_QAM_EQU_CRL_LD_SEN, 0x85 }, ++ { R367_QAM_EQU_CRL_LD_VAL, 0xe2 }, ++ { R367_QAM_EQU_CRL_TFR, 0x20 }, ++ { R367_QAM_EQU_CRL_BISTH_LO, 0x00 }, ++ { R367_QAM_EQU_CRL_BISTH_HI, 0x00 }, ++ { R367_QAM_EQU_SWEEP_RANGE_LO, 0x00 }, ++ { R367_QAM_EQU_SWEEP_RANGE_HI, 0x00 }, ++ { R367_QAM_EQU_CRL_LIMITER, 0x40 }, ++ { R367_QAM_EQU_MODULUS_MAP, 0x90 }, ++ { R367_QAM_EQU_PNT_GAIN, 0xa7 }, ++ { R367_QAM_FEC_AC_CTR_0, 0x16 }, ++ { R367_QAM_FEC_AC_CTR_1, 0x0b }, ++ { R367_QAM_FEC_AC_CTR_2, 0x88 }, ++ { R367_QAM_FEC_AC_CTR_3, 0x02 }, ++ { R367_QAM_FEC_STATUS, 0x12 }, ++ { R367_QAM_RS_COUNTER_0, 0x7d }, ++ { R367_QAM_RS_COUNTER_1, 0xd0 }, ++ { R367_QAM_RS_COUNTER_2, 0x19 }, ++ { R367_QAM_RS_COUNTER_3, 0x0b }, ++ { R367_QAM_RS_COUNTER_4, 0xa3 }, ++ { R367_QAM_RS_COUNTER_5, 0x00 }, ++ { R367_QAM_BERT_0, 0x01 }, ++ { R367_QAM_BERT_1, 0x25 }, ++ { R367_QAM_BERT_2, 0x41 }, ++ { R367_QAM_BERT_3, 0x39 }, ++ { R367_QAM_OUTFORMAT_0, 0xc2 }, ++ { R367_QAM_OUTFORMAT_1, 0x22 }, ++ { R367_QAM_SMOOTHER_2, 0x28 }, ++ { R367_QAM_TSMF_CTRL_0, 0x01 }, ++ { R367_QAM_TSMF_CTRL_1, 0xc6 }, ++ { R367_QAM_TSMF_CTRL_3, 0x43 }, ++ { R367_QAM_TS_ON_ID_0, 0x00 }, ++ { R367_QAM_TS_ON_ID_1, 0x00 }, ++ { R367_QAM_TS_ON_ID_2, 0x00 }, ++ { R367_QAM_TS_ON_ID_3, 0x00 }, ++ { R367_QAM_RE_STATUS_0, 0x00 }, ++ { R367_QAM_RE_STATUS_1, 0x00 }, ++ { R367_QAM_RE_STATUS_2, 0x00 }, ++ { R367_QAM_RE_STATUS_3, 0x00 }, ++ { R367_QAM_TS_STATUS_0, 0x00 }, ++ { R367_QAM_TS_STATUS_1, 0x00 }, ++ { R367_QAM_TS_STATUS_2, 0xa0 }, ++ { R367_QAM_TS_STATUS_3, 0x00 }, ++ { R367_QAM_T_O_ID_0, 0x00 }, ++ { R367_QAM_T_O_ID_1, 0x00 }, ++ { R367_QAM_T_O_ID_2, 0x00 }, ++ { R367_QAM_T_O_ID_3, 0x00 }, ++ { 0x0000, 0x00 } // EOT ++}; ++ ++struct init_table ofdm_init[] = { ++ //{R367_OFDM_ID ,0x60}, ++ //{R367_OFDM_I2CRPT ,0x22}, ++ //{R367_OFDM_TOPCTRL ,0x02}, ++ //{R367_OFDM_IOCFG0 ,0x40}, ++ //{R367_OFDM_DAC0R ,0x00}, ++ //{R367_OFDM_IOCFG1 ,0x00}, ++ //{R367_OFDM_DAC1R ,0x00}, ++ //{R367_OFDM_IOCFG2 ,0x62}, ++ //{R367_OFDM_SDFR ,0x00}, ++ //{R367_OFDM_STATUS ,0xf8}, ++ //{R367_OFDM_AUX_CLK ,0x0a}, ++ //{R367_OFDM_FREESYS1 ,0x00}, ++ //{R367_OFDM_FREESYS2 ,0x00}, ++ //{R367_OFDM_FREESYS3 ,0x00}, ++ //{R367_OFDM_GPIO_CFG ,0x55}, ++ //{R367_OFDM_GPIO_CMD ,0x00}, ++ {R367_OFDM_AGC2MAX ,0xff}, ++ {R367_OFDM_AGC2MIN ,0x00}, ++ {R367_OFDM_AGC1MAX ,0xff}, ++ {R367_OFDM_AGC1MIN ,0x00}, ++ {R367_OFDM_AGCR ,0xbc}, ++ {R367_OFDM_AGC2TH ,0x00}, ++ //{R367_OFDM_AGC12C ,0x01}, //Note: This defines AGC pins, also needed for QAM ++ {R367_OFDM_AGCCTRL1 ,0x85}, ++ {R367_OFDM_AGCCTRL2 ,0x1f}, ++ {R367_OFDM_AGC1VAL1 ,0x00}, ++ {R367_OFDM_AGC1VAL2 ,0x00}, ++ {R367_OFDM_AGC2VAL1 ,0x6f}, ++ {R367_OFDM_AGC2VAL2 ,0x05}, ++ {R367_OFDM_AGC2PGA ,0x00}, ++ {R367_OFDM_OVF_RATE1 ,0x00}, ++ {R367_OFDM_OVF_RATE2 ,0x00}, ++ {R367_OFDM_GAIN_SRC1 ,0x2b}, ++ {R367_OFDM_GAIN_SRC2 ,0x04}, ++ {R367_OFDM_INC_DEROT1 ,0x55}, ++ {R367_OFDM_INC_DEROT2 ,0x55}, ++ {R367_OFDM_PPM_CPAMP_DIR ,0x2c}, ++ {R367_OFDM_PPM_CPAMP_INV ,0x00}, ++ {R367_OFDM_FREESTFE_1 ,0x00}, ++ {R367_OFDM_FREESTFE_2 ,0x1c}, ++ {R367_OFDM_DCOFFSET ,0x00}, ++ {R367_OFDM_EN_PROCESS ,0x05}, ++ {R367_OFDM_SDI_SMOOTHER ,0x80}, ++ {R367_OFDM_FE_LOOP_OPEN ,0x1c}, ++ {R367_OFDM_FREQOFF1 ,0x00}, ++ {R367_OFDM_FREQOFF2 ,0x00}, ++ {R367_OFDM_FREQOFF3 ,0x00}, ++ {R367_OFDM_TIMOFF1 ,0x00}, ++ {R367_OFDM_TIMOFF2 ,0x00}, ++ {R367_OFDM_EPQ ,0x02}, ++ {R367_OFDM_EPQAUTO ,0x01}, ++ {R367_OFDM_SYR_UPDATE ,0xf5}, ++ {R367_OFDM_CHPFREE ,0x00}, ++ {R367_OFDM_PPM_STATE_MAC ,0x23}, ++ {R367_OFDM_INR_THRESHOLD ,0xff}, ++ {R367_OFDM_EPQ_TPS_ID_CELL ,0xf9}, ++ {R367_OFDM_EPQ_CFG ,0x00}, ++ {R367_OFDM_EPQ_STATUS ,0x01}, ++ {R367_OFDM_AUTORELOCK ,0x81}, ++ {R367_OFDM_BER_THR_VMSB ,0x00}, ++ {R367_OFDM_BER_THR_MSB ,0x00}, ++ {R367_OFDM_BER_THR_LSB ,0x00}, ++ {R367_OFDM_CCD ,0x83}, ++ {R367_OFDM_SPECTR_CFG ,0x00}, ++ {R367_OFDM_CHC_DUMMY ,0x18}, ++ {R367_OFDM_INC_CTL ,0x88}, ++ {R367_OFDM_INCTHRES_COR1 ,0xb4}, ++ {R367_OFDM_INCTHRES_COR2 ,0x96}, ++ {R367_OFDM_INCTHRES_DET1 ,0x0e}, ++ {R367_OFDM_INCTHRES_DET2 ,0x11}, ++ {R367_OFDM_IIR_CELLNB ,0x8d}, ++ {R367_OFDM_IIRCX_COEFF1_MSB ,0x00}, ++ {R367_OFDM_IIRCX_COEFF1_LSB ,0x00}, ++ {R367_OFDM_IIRCX_COEFF2_MSB ,0x09}, ++ {R367_OFDM_IIRCX_COEFF2_LSB ,0x18}, ++ {R367_OFDM_IIRCX_COEFF3_MSB ,0x14}, ++ {R367_OFDM_IIRCX_COEFF3_LSB ,0x9c}, ++ {R367_OFDM_IIRCX_COEFF4_MSB ,0x00}, ++ {R367_OFDM_IIRCX_COEFF4_LSB ,0x00}, ++ {R367_OFDM_IIRCX_COEFF5_MSB ,0x36}, ++ {R367_OFDM_IIRCX_COEFF5_LSB ,0x42}, ++ {R367_OFDM_FEPATH_CFG ,0x00}, ++ {R367_OFDM_PMC1_FUNC ,0x65}, ++ {R367_OFDM_PMC1_FOR ,0x00}, ++ {R367_OFDM_PMC2_FUNC ,0x00}, ++ {R367_OFDM_STATUS_ERR_DA ,0xe0}, ++ {R367_OFDM_DIG_AGC_R ,0xfe}, ++ {R367_OFDM_COMAGC_TARMSB ,0x0b}, ++ {R367_OFDM_COM_AGC_TAR_ENMODE ,0x41}, ++ {R367_OFDM_COM_AGC_CFG ,0x3e}, ++ {R367_OFDM_COM_AGC_GAIN1 ,0x39}, ++ {R367_OFDM_AUT_AGC_TARGETMSB ,0x0b}, ++ {R367_OFDM_LOCK_DET_MSB ,0x01}, ++ {R367_OFDM_AGCTAR_LOCK_LSBS ,0x40}, ++ {R367_OFDM_AUT_GAIN_EN ,0xf4}, ++ {R367_OFDM_AUT_CFG ,0xf0}, ++ {R367_OFDM_LOCKN ,0x23}, ++ {R367_OFDM_INT_X_3 ,0x00}, ++ {R367_OFDM_INT_X_2 ,0x03}, ++ {R367_OFDM_INT_X_1 ,0x8d}, ++ {R367_OFDM_INT_X_0 ,0xa0}, ++ {R367_OFDM_MIN_ERRX_MSB ,0x00}, ++ {R367_OFDM_COR_CTL ,0x00}, ++ {R367_OFDM_COR_STAT ,0xf6}, ++ {R367_OFDM_COR_INTEN ,0x00}, ++ {R367_OFDM_COR_INTSTAT ,0x3f}, ++ {R367_OFDM_COR_MODEGUARD ,0x03}, ++ {R367_OFDM_AGC_CTL ,0x08}, ++ {R367_OFDM_AGC_MANUAL1 ,0x00}, ++ {R367_OFDM_AGC_MANUAL2 ,0x00}, ++ {R367_OFDM_AGC_TARG ,0x16}, ++ {R367_OFDM_AGC_GAIN1 ,0x53}, ++ {R367_OFDM_AGC_GAIN2 ,0x1d}, ++ {R367_OFDM_RESERVED_1 ,0x00}, ++ {R367_OFDM_RESERVED_2 ,0x00}, ++ {R367_OFDM_RESERVED_3 ,0x00}, ++ {R367_OFDM_CAS_CTL ,0x44}, ++ {R367_OFDM_CAS_FREQ ,0xb3}, ++ {R367_OFDM_CAS_DAGCGAIN ,0x12}, ++ {R367_OFDM_SYR_CTL ,0x04}, ++ {R367_OFDM_SYR_STAT ,0x10}, ++ {R367_OFDM_SYR_NCO1 ,0x00}, ++ {R367_OFDM_SYR_NCO2 ,0x00}, ++ {R367_OFDM_SYR_OFFSET1 ,0x00}, ++ {R367_OFDM_SYR_OFFSET2 ,0x00}, ++ {R367_OFDM_FFT_CTL ,0x00}, ++ {R367_OFDM_SCR_CTL ,0x70}, ++ {R367_OFDM_PPM_CTL1 ,0xf8}, ++ {R367_OFDM_TRL_CTL ,0xac}, ++ {R367_OFDM_TRL_NOMRATE1 ,0x1e}, ++ {R367_OFDM_TRL_NOMRATE2 ,0x58}, ++ {R367_OFDM_TRL_TIME1 ,0x1d}, ++ {R367_OFDM_TRL_TIME2 ,0xfc}, ++ {R367_OFDM_CRL_CTL ,0x24}, ++ {R367_OFDM_CRL_FREQ1 ,0xad}, ++ {R367_OFDM_CRL_FREQ2 ,0x9d}, ++ {R367_OFDM_CRL_FREQ3 ,0xff}, ++ {R367_OFDM_CHC_CTL ,0x01}, ++ {R367_OFDM_CHC_SNR ,0xf0}, ++ {R367_OFDM_BDI_CTL ,0x00}, ++ {R367_OFDM_DMP_CTL ,0x00}, ++ {R367_OFDM_TPS_RCVD1 ,0x30}, ++ {R367_OFDM_TPS_RCVD2 ,0x02}, ++ {R367_OFDM_TPS_RCVD3 ,0x01}, ++ {R367_OFDM_TPS_RCVD4 ,0x00}, ++ {R367_OFDM_TPS_ID_CELL1 ,0x00}, ++ {R367_OFDM_TPS_ID_CELL2 ,0x00}, ++ {R367_OFDM_TPS_RCVD5_SET1 ,0x02}, ++ {R367_OFDM_TPS_SET2 ,0x02}, ++ {R367_OFDM_TPS_SET3 ,0x01}, ++ {R367_OFDM_TPS_CTL ,0x00}, ++ {R367_OFDM_CTL_FFTOSNUM ,0x34}, ++ {R367_OFDM_TESTSELECT ,0x09}, ++ {R367_OFDM_MSC_REV ,0x0a}, ++ {R367_OFDM_PIR_CTL ,0x00}, ++ {R367_OFDM_SNR_CARRIER1 ,0xa1}, ++ {R367_OFDM_SNR_CARRIER2 ,0x9a}, ++ {R367_OFDM_PPM_CPAMP ,0x2c}, ++ {R367_OFDM_TSM_AP0 ,0x00}, ++ {R367_OFDM_TSM_AP1 ,0x00}, ++ {R367_OFDM_TSM_AP2 ,0x00}, ++ {R367_OFDM_TSM_AP3 ,0x00}, ++ {R367_OFDM_TSM_AP4 ,0x00}, ++ {R367_OFDM_TSM_AP5 ,0x00}, ++ {R367_OFDM_TSM_AP6 ,0x00}, ++ {R367_OFDM_TSM_AP7 ,0x00}, ++ //{R367_OFDM_TSTRES ,0x00}, ++ //{R367_OFDM_ANACTRL ,0x0D},/*caution PLL stopped, to be restarted at init!!!*/ ++ //{R367_OFDM_TSTBUS ,0x00}, ++ //{R367_OFDM_TSTRATE ,0x00}, ++ {R367_OFDM_CONSTMODE ,0x01}, ++ {R367_OFDM_CONSTCARR1 ,0x00}, ++ {R367_OFDM_CONSTCARR2 ,0x00}, ++ {R367_OFDM_ICONSTEL ,0x0a}, ++ {R367_OFDM_QCONSTEL ,0x15}, ++ {R367_OFDM_TSTBISTRES0 ,0x00}, ++ {R367_OFDM_TSTBISTRES1 ,0x00}, ++ {R367_OFDM_TSTBISTRES2 ,0x28}, ++ {R367_OFDM_TSTBISTRES3 ,0x00}, ++ //{R367_OFDM_RF_AGC1 ,0xff}, ++ //{R367_OFDM_RF_AGC2 ,0x83}, ++ //{R367_OFDM_ANADIGCTRL ,0x19}, ++ //{R367_OFDM_PLLMDIV ,0x0c}, ++ //{R367_OFDM_PLLNDIV ,0x55}, ++ //{R367_OFDM_PLLSETUP ,0x18}, ++ //{R367_OFDM_DUAL_AD12 ,0x00}, ++ //{R367_OFDM_TSTBIST ,0x00}, ++ //{R367_OFDM_PAD_COMP_CTRL ,0x00}, ++ //{R367_OFDM_PAD_COMP_WR ,0x00}, ++ //{R367_OFDM_PAD_COMP_RD ,0xe0}, ++ {R367_OFDM_SYR_TARGET_FFTADJT_MSB ,0x00}, ++ {R367_OFDM_SYR_TARGET_FFTADJT_LSB ,0x00}, ++ {R367_OFDM_SYR_TARGET_CHCADJT_MSB ,0x00}, ++ {R367_OFDM_SYR_TARGET_CHCADJT_LSB ,0x00}, ++ {R367_OFDM_SYR_FLAG ,0x00}, ++ {R367_OFDM_CRL_TARGET1 ,0x00}, ++ {R367_OFDM_CRL_TARGET2 ,0x00}, ++ {R367_OFDM_CRL_TARGET3 ,0x00}, ++ {R367_OFDM_CRL_TARGET4 ,0x00}, ++ {R367_OFDM_CRL_FLAG ,0x00}, ++ {R367_OFDM_TRL_TARGET1 ,0x00}, ++ {R367_OFDM_TRL_TARGET2 ,0x00}, ++ {R367_OFDM_TRL_CHC ,0x00}, ++ {R367_OFDM_CHC_SNR_TARG ,0x00}, ++ {R367_OFDM_TOP_TRACK ,0x00}, ++ {R367_OFDM_TRACKER_FREE1 ,0x00}, ++ {R367_OFDM_ERROR_CRL1 ,0x00}, ++ {R367_OFDM_ERROR_CRL2 ,0x00}, ++ {R367_OFDM_ERROR_CRL3 ,0x00}, ++ {R367_OFDM_ERROR_CRL4 ,0x00}, ++ {R367_OFDM_DEC_NCO1 ,0x2c}, ++ {R367_OFDM_DEC_NCO2 ,0x0f}, ++ {R367_OFDM_DEC_NCO3 ,0x20}, ++ {R367_OFDM_SNR ,0xf1}, ++ {R367_OFDM_SYR_FFTADJ1 ,0x00}, ++ {R367_OFDM_SYR_FFTADJ2 ,0x00}, ++ {R367_OFDM_SYR_CHCADJ1 ,0x00}, ++ {R367_OFDM_SYR_CHCADJ2 ,0x00}, ++ {R367_OFDM_SYR_OFF ,0x00}, ++ {R367_OFDM_PPM_OFFSET1 ,0x00}, ++ {R367_OFDM_PPM_OFFSET2 ,0x03}, ++ {R367_OFDM_TRACKER_FREE2 ,0x00}, ++ {R367_OFDM_DEBG_LT10 ,0x00}, ++ {R367_OFDM_DEBG_LT11 ,0x00}, ++ {R367_OFDM_DEBG_LT12 ,0x00}, ++ {R367_OFDM_DEBG_LT13 ,0x00}, ++ {R367_OFDM_DEBG_LT14 ,0x00}, ++ {R367_OFDM_DEBG_LT15 ,0x00}, ++ {R367_OFDM_DEBG_LT16 ,0x00}, ++ {R367_OFDM_DEBG_LT17 ,0x00}, ++ {R367_OFDM_DEBG_LT18 ,0x00}, ++ {R367_OFDM_DEBG_LT19 ,0x00}, ++ {R367_OFDM_DEBG_LT1A ,0x00}, ++ {R367_OFDM_DEBG_LT1B ,0x00}, ++ {R367_OFDM_DEBG_LT1C ,0x00}, ++ {R367_OFDM_DEBG_LT1D ,0x00}, ++ {R367_OFDM_DEBG_LT1E ,0x00}, ++ {R367_OFDM_DEBG_LT1F ,0x00}, ++ {R367_OFDM_RCCFGH ,0x00}, ++ {R367_OFDM_RCCFGM ,0x00}, ++ {R367_OFDM_RCCFGL ,0x00}, ++ {R367_OFDM_RCINSDELH ,0x00}, ++ {R367_OFDM_RCINSDELM ,0x00}, ++ {R367_OFDM_RCINSDELL ,0x00}, ++ {R367_OFDM_RCSTATUS ,0x00}, ++ {R367_OFDM_RCSPEED ,0x6f}, ++ {R367_OFDM_RCDEBUGM ,0xe7}, ++ {R367_OFDM_RCDEBUGL ,0x9b}, ++ {R367_OFDM_RCOBSCFG ,0x00}, ++ {R367_OFDM_RCOBSM ,0x00}, ++ {R367_OFDM_RCOBSL ,0x00}, ++ {R367_OFDM_RCFECSPY ,0x00}, ++ {R367_OFDM_RCFSPYCFG ,0x00}, ++ {R367_OFDM_RCFSPYDATA ,0x00}, ++ {R367_OFDM_RCFSPYOUT ,0x00}, ++ {R367_OFDM_RCFSTATUS ,0x00}, ++ {R367_OFDM_RCFGOODPACK ,0x00}, ++ {R367_OFDM_RCFPACKCNT ,0x00}, ++ {R367_OFDM_RCFSPYMISC ,0x00}, ++ {R367_OFDM_RCFBERCPT4 ,0x00}, ++ {R367_OFDM_RCFBERCPT3 ,0x00}, ++ {R367_OFDM_RCFBERCPT2 ,0x00}, ++ {R367_OFDM_RCFBERCPT1 ,0x00}, ++ {R367_OFDM_RCFBERCPT0 ,0x00}, ++ {R367_OFDM_RCFBERERR2 ,0x00}, ++ {R367_OFDM_RCFBERERR1 ,0x00}, ++ {R367_OFDM_RCFBERERR0 ,0x00}, ++ {R367_OFDM_RCFSTATESM ,0x00}, ++ {R367_OFDM_RCFSTATESL ,0x00}, ++ {R367_OFDM_RCFSPYBER ,0x00}, ++ {R367_OFDM_RCFSPYDISTM ,0x00}, ++ {R367_OFDM_RCFSPYDISTL ,0x00}, ++ {R367_OFDM_RCFSPYOBS7 ,0x00}, ++ {R367_OFDM_RCFSPYOBS6 ,0x00}, ++ {R367_OFDM_RCFSPYOBS5 ,0x00}, ++ {R367_OFDM_RCFSPYOBS4 ,0x00}, ++ {R367_OFDM_RCFSPYOBS3 ,0x00}, ++ {R367_OFDM_RCFSPYOBS2 ,0x00}, ++ {R367_OFDM_RCFSPYOBS1 ,0x00}, ++ {R367_OFDM_RCFSPYOBS0 ,0x00}, ++ //{R367_OFDM_TSGENERAL ,0x00}, ++ //{R367_OFDM_RC1SPEED ,0x6f}, ++ //{R367_OFDM_TSGSTATUS ,0x18}, ++ {R367_OFDM_FECM ,0x01}, ++ {R367_OFDM_VTH12 ,0xff}, ++ {R367_OFDM_VTH23 ,0xa1}, ++ {R367_OFDM_VTH34 ,0x64}, ++ {R367_OFDM_VTH56 ,0x40}, ++ {R367_OFDM_VTH67 ,0x00}, ++ {R367_OFDM_VTH78 ,0x2c}, ++ {R367_OFDM_VITCURPUN ,0x12}, ++ {R367_OFDM_VERROR ,0x01}, ++ {R367_OFDM_PRVIT ,0x3f}, ++ {R367_OFDM_VAVSRVIT ,0x00}, ++ {R367_OFDM_VSTATUSVIT ,0xbd}, ++ {R367_OFDM_VTHINUSE ,0xa1}, ++ {R367_OFDM_KDIV12 ,0x20}, ++ {R367_OFDM_KDIV23 ,0x40}, ++ {R367_OFDM_KDIV34 ,0x20}, ++ {R367_OFDM_KDIV56 ,0x30}, ++ {R367_OFDM_KDIV67 ,0x00}, ++ {R367_OFDM_KDIV78 ,0x30}, ++ {R367_OFDM_SIGPOWER ,0x54}, ++ {R367_OFDM_DEMAPVIT ,0x40}, ++ {R367_OFDM_VITSCALE ,0x00}, ++ {R367_OFDM_FFEC1PRG ,0x00}, ++ {R367_OFDM_FVITCURPUN ,0x12}, ++ {R367_OFDM_FVERROR ,0x01}, ++ {R367_OFDM_FVSTATUSVIT ,0xbd}, ++ {R367_OFDM_DEBUG_LT1 ,0x00}, ++ {R367_OFDM_DEBUG_LT2 ,0x00}, ++ {R367_OFDM_DEBUG_LT3 ,0x00}, ++ {R367_OFDM_TSTSFMET ,0x00}, ++ {R367_OFDM_SELOUT ,0x00}, ++ {R367_OFDM_TSYNC ,0x00}, ++ {R367_OFDM_TSTERR ,0x00}, ++ {R367_OFDM_TSFSYNC ,0x00}, ++ {R367_OFDM_TSTSFERR ,0x00}, ++ {R367_OFDM_TSTTSSF1 ,0x01}, ++ {R367_OFDM_TSTTSSF2 ,0x1f}, ++ {R367_OFDM_TSTTSSF3 ,0x00}, ++ {R367_OFDM_TSTTS1 ,0x00}, ++ {R367_OFDM_TSTTS2 ,0x1f}, ++ {R367_OFDM_TSTTS3 ,0x01}, ++ {R367_OFDM_TSTTS4 ,0x00}, ++ {R367_OFDM_TSTTSRC ,0x00}, ++ {R367_OFDM_TSTTSRS ,0x00}, ++ {R367_OFDM_TSSTATEM ,0xb0}, ++ {R367_OFDM_TSSTATEL ,0x40}, ++ {R367_OFDM_TSCFGH ,0x80}, ++ {R367_OFDM_TSCFGM ,0x00}, ++ {R367_OFDM_TSCFGL ,0x20}, ++ {R367_OFDM_TSSYNC ,0x00}, ++ {R367_OFDM_TSINSDELH ,0x00}, ++ {R367_OFDM_TSINSDELM ,0x00}, ++ {R367_OFDM_TSINSDELL ,0x00}, ++ {R367_OFDM_TSDIVN ,0x03}, ++ {R367_OFDM_TSDIVPM ,0x00}, ++ {R367_OFDM_TSDIVPL ,0x00}, ++ {R367_OFDM_TSDIVQM ,0x00}, ++ {R367_OFDM_TSDIVQL ,0x00}, ++ {R367_OFDM_TSDILSTKM ,0x00}, ++ {R367_OFDM_TSDILSTKL ,0x00}, ++ {R367_OFDM_TSSPEED ,0x6f}, ++ {R367_OFDM_TSSTATUS ,0x81}, ++ {R367_OFDM_TSSTATUS2 ,0x6a}, ++ {R367_OFDM_TSBITRATEM ,0x0f}, ++ {R367_OFDM_TSBITRATEL ,0xc6}, ++ {R367_OFDM_TSPACKLENM ,0x00}, ++ {R367_OFDM_TSPACKLENL ,0xfc}, ++ {R367_OFDM_TSBLOCLENM ,0x0a}, ++ {R367_OFDM_TSBLOCLENL ,0x80}, ++ {R367_OFDM_TSDLYH ,0x90}, ++ {R367_OFDM_TSDLYM ,0x68}, ++ {R367_OFDM_TSDLYL ,0x01}, ++ {R367_OFDM_TSNPDAV ,0x00}, ++ {R367_OFDM_TSBUFSTATH ,0x00}, ++ {R367_OFDM_TSBUFSTATM ,0x00}, ++ {R367_OFDM_TSBUFSTATL ,0x00}, ++ {R367_OFDM_TSDEBUGM ,0xcf}, ++ {R367_OFDM_TSDEBUGL ,0x1e}, ++ {R367_OFDM_TSDLYSETH ,0x00}, ++ {R367_OFDM_TSDLYSETM ,0x68}, ++ {R367_OFDM_TSDLYSETL ,0x00}, ++ {R367_OFDM_TSOBSCFG ,0x00}, ++ {R367_OFDM_TSOBSM ,0x47}, ++ {R367_OFDM_TSOBSL ,0x1f}, ++ {R367_OFDM_ERRCTRL1 ,0x95}, ++ {R367_OFDM_ERRCNT1H ,0x80}, ++ {R367_OFDM_ERRCNT1M ,0x00}, ++ {R367_OFDM_ERRCNT1L ,0x00}, ++ {R367_OFDM_ERRCTRL2 ,0x95}, ++ {R367_OFDM_ERRCNT2H ,0x00}, ++ {R367_OFDM_ERRCNT2M ,0x00}, ++ {R367_OFDM_ERRCNT2L ,0x00}, ++ {R367_OFDM_FECSPY ,0x88}, ++ {R367_OFDM_FSPYCFG ,0x2c}, ++ {R367_OFDM_FSPYDATA ,0x3a}, ++ {R367_OFDM_FSPYOUT ,0x06}, ++ {R367_OFDM_FSTATUS ,0x61}, ++ {R367_OFDM_FGOODPACK ,0xff}, ++ {R367_OFDM_FPACKCNT ,0xff}, ++ {R367_OFDM_FSPYMISC ,0x66}, ++ {R367_OFDM_FBERCPT4 ,0x00}, ++ {R367_OFDM_FBERCPT3 ,0x00}, ++ {R367_OFDM_FBERCPT2 ,0x36}, ++ {R367_OFDM_FBERCPT1 ,0x36}, ++ {R367_OFDM_FBERCPT0 ,0x14}, ++ {R367_OFDM_FBERERR2 ,0x00}, ++ {R367_OFDM_FBERERR1 ,0x03}, ++ {R367_OFDM_FBERERR0 ,0x28}, ++ {R367_OFDM_FSTATESM ,0x00}, ++ {R367_OFDM_FSTATESL ,0x02}, ++ {R367_OFDM_FSPYBER ,0x00}, ++ {R367_OFDM_FSPYDISTM ,0x01}, ++ {R367_OFDM_FSPYDISTL ,0x9f}, ++ {R367_OFDM_FSPYOBS7 ,0xc9}, ++ {R367_OFDM_FSPYOBS6 ,0x99}, ++ {R367_OFDM_FSPYOBS5 ,0x08}, ++ {R367_OFDM_FSPYOBS4 ,0xec}, ++ {R367_OFDM_FSPYOBS3 ,0x01}, ++ {R367_OFDM_FSPYOBS2 ,0x0f}, ++ {R367_OFDM_FSPYOBS1 ,0xf5}, ++ {R367_OFDM_FSPYOBS0 ,0x08}, ++ {R367_OFDM_SFDEMAP ,0x40}, ++ {R367_OFDM_SFERROR ,0x00}, ++ {R367_OFDM_SFAVSR ,0x30}, ++ {R367_OFDM_SFECSTATUS ,0xcc}, ++ {R367_OFDM_SFKDIV12 ,0x20}, ++ {R367_OFDM_SFKDIV23 ,0x40}, ++ {R367_OFDM_SFKDIV34 ,0x20}, ++ {R367_OFDM_SFKDIV56 ,0x20}, ++ {R367_OFDM_SFKDIV67 ,0x00}, ++ {R367_OFDM_SFKDIV78 ,0x20}, ++ {R367_OFDM_SFDILSTKM ,0x00}, ++ {R367_OFDM_SFDILSTKL ,0x00}, ++ {R367_OFDM_SFSTATUS ,0xb5}, ++ {R367_OFDM_SFDLYH ,0x90}, ++ {R367_OFDM_SFDLYM ,0x60}, ++ {R367_OFDM_SFDLYL ,0x01}, ++ {R367_OFDM_SFDLYSETH ,0xc0}, ++ {R367_OFDM_SFDLYSETM ,0x60}, ++ {R367_OFDM_SFDLYSETL ,0x00}, ++ {R367_OFDM_SFOBSCFG ,0x00}, ++ {R367_OFDM_SFOBSM ,0x47}, ++ {R367_OFDM_SFOBSL ,0x05}, ++ {R367_OFDM_SFECINFO ,0x40}, ++ {R367_OFDM_SFERRCTRL ,0x74}, ++ {R367_OFDM_SFERRCNTH ,0x80}, ++ {R367_OFDM_SFERRCNTM ,0x00}, ++ {R367_OFDM_SFERRCNTL ,0x00}, ++ {R367_OFDM_SYMBRATEM ,0x2f}, ++ {R367_OFDM_SYMBRATEL ,0x50}, ++ {R367_OFDM_SYMBSTATUS ,0x7f}, ++ {R367_OFDM_SYMBCFG ,0x00}, ++ {R367_OFDM_SYMBFIFOM ,0xf4}, ++ {R367_OFDM_SYMBFIFOL ,0x0d}, ++ {R367_OFDM_SYMBOFFSM ,0xf0}, ++ {R367_OFDM_SYMBOFFSL ,0x2d}, ++ //{R367_OFDM_DEBUG_LT4 ,0x00}, ++ //{R367_OFDM_DEBUG_LT5 ,0x00}, ++ //{R367_OFDM_DEBUG_LT6 ,0x00}, ++ //{R367_OFDM_DEBUG_LT7 ,0x00}, ++ //{R367_OFDM_DEBUG_LT8 ,0x00}, ++ //{R367_OFDM_DEBUG_LT9 ,0x00}, ++ { 0x0000, 0x00 } // EOT ++}; ++ ++static inline u32 MulDiv32(u32 a, u32 b, u32 c) ++{ ++ u64 tmp64; ++ ++ tmp64 = (u64)a * (u64)b; ++ do_div(tmp64, c); ++ ++ return (u32) tmp64; ++} ++ ++static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len) ++{ ++ struct i2c_msg msg = ++ {.addr = adr, .flags = 0, .buf = data, .len = len}; ++ ++ if (i2c_transfer(adap, &msg, 1) != 1) { ++ printk("stv0367: i2c_write error\n"); ++ return -1; ++ } ++ return 0; ++} ++ ++#if 0 ++static int i2c_read(struct i2c_adapter *adap, ++ u8 adr, u8 *msg, int len, u8 *answ, int alen) ++{ ++ struct i2c_msg msgs[2] = { { .addr = adr, .flags = 0, ++ .buf = msg, .len = len}, ++ { .addr = adr, .flags = I2C_M_RD, ++ .buf = answ, .len = alen } }; ++ if (i2c_transfer(adap, msgs, 2) != 2) { ++ printk("stv0367: i2c_read error\n"); ++ return -1; ++ } ++ return 0; ++} ++#endif ++ ++static int writereg(struct stv_state *state, u16 reg, u8 dat) ++{ ++ u8 mm[3] = { (reg >> 8), reg & 0xff, dat }; ++ ++ return i2c_write(state->i2c, state->adr, mm, 3); ++} ++ ++static int readreg(struct stv_state *state, u16 reg, u8 *val) ++{ ++ u8 msg[2] = {reg >> 8, reg & 0xff}; ++ struct i2c_msg msgs[2] = {{.addr = state->adr, .flags = 0, ++ .buf = msg, .len = 2}, ++ {.addr = state->adr, .flags = I2C_M_RD, ++ .buf = val, .len = 1}}; ++ return (i2c_transfer(state->i2c, msgs, 2) == 2) ? 0 : -1; ++} ++ ++static int readregs(struct stv_state *state, u16 reg, u8 *val, int count) ++{ ++ u8 msg[2] = {reg >> 8, reg & 0xff}; ++ struct i2c_msg msgs[2] = {{.addr = state->adr, .flags = 0, ++ .buf = msg, .len = 2}, ++ {.addr = state->adr, .flags = I2C_M_RD, ++ .buf = val, .len = count}}; ++ return (i2c_transfer(state->i2c, msgs, 2) == 2) ? 0 : -1; ++} ++ ++static int write_init_table(struct stv_state *state, struct init_table *tab) ++{ ++ while (1) { ++ if (!tab->adr) ++ break; ++ if (writereg(state, tab->adr, tab->data) < 0) ++ return -1; ++ tab++; ++ } ++ return 0; ++} ++ ++static int qam_set_modulation(struct stv_state *state) ++{ ++ int stat = 0; ++ ++ switch(state->modulation) { ++ case QAM_16: ++ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM16 ); ++ writereg(state, R367_QAM_AGC_PWR_REF_L,0x64); /* Set analog AGC reference */ ++ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ ++ writereg(state, R367_QAM_FSM_STATE,0x90); ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); ++ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x95); ++ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); ++ writereg(state, R367_QAM_EQU_PNT_GAIN,0x8a); ++ break; ++ case QAM_32: ++ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM32 ); ++ writereg(state, R367_QAM_AGC_PWR_REF_L,0x6e); /* Set analog AGC reference */ ++ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ ++ writereg(state, R367_QAM_FSM_STATE,0xb0); ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xb7); ++ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x9d); ++ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x7f); ++ writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); ++ break; ++ case QAM_64: ++ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM64 ); ++ writereg(state, R367_QAM_AGC_PWR_REF_L,0x5a); /* Set analog AGC reference */ ++ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x82); /* Set digital AGC reference */ ++ if(state->symbol_rate>4500000) ++ { ++ writereg(state, R367_QAM_FSM_STATE,0xb0); ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa5); ++ } ++ else if(state->symbol_rate>2500000) // 25000000 ++ { ++ writereg(state, R367_QAM_FSM_STATE,0xa0); ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa6); ++ } ++ else ++ { ++ writereg(state, R367_QAM_FSM_STATE,0xa0); ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xd1); ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); ++ } ++ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x95); ++ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); ++ writereg(state, R367_QAM_EQU_PNT_GAIN,0x99); ++ break; ++ case QAM_128: ++ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM128 ); ++ writereg(state, R367_QAM_AGC_PWR_REF_L,0x76); /* Set analog AGC reference */ ++ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x00); /* Set digital AGC reference */ ++ writereg(state, R367_QAM_FSM_STATE,0x90); ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xb1); ++ if(state->symbol_rate>4500000) // 45000000 ++ { ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); ++ } ++ else if(state->symbol_rate>2500000) // 25000000 ++ { ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa6); ++ } ++ else ++ { ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0x97); ++ } ++ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x8e); ++ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x7f); ++ writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); ++ break; ++ case QAM_256: ++ writereg(state, R367_QAM_EQU_MAPPER,state->qam_inversion | QAM_MOD_QAM256 ); ++ writereg(state, R367_QAM_AGC_PWR_REF_L,0x5a); /* Set analog AGC reference */ ++ writereg(state, R367_QAM_IQDEM_ADJ_AGC_REF,0x94); /* Set digital AGC reference */ ++ writereg(state, R367_QAM_FSM_STATE,0xa0); ++ if(state->symbol_rate>4500000) // 45000000 ++ { ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); ++ } ++ else if(state->symbol_rate>2500000) // 25000000 ++ { ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xc1); ++ } ++ else ++ { ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,0xd1); ++ } ++ writereg(state, R367_QAM_EQU_CRL_LPF_GAIN,0xa7); ++ writereg(state, R367_QAM_EQU_CRL_LD_SEN,0x85); ++ writereg(state, R367_QAM_EQU_CRL_LIMITER,0x40); ++ writereg(state, R367_QAM_EQU_PNT_GAIN,0xa7); ++ break; ++ default: ++ stat = -EINVAL; ++ break; ++ } ++ return stat; ++} ++ ++ ++static int QAM_SetSymbolRate(struct stv_state *state) ++{ ++ int status = 0; ++ u32 sr = state->symbol_rate; ++ u32 Corr = 0; ++ u32 Temp, Temp1, AdpClk; ++ ++ switch(state->modulation) { ++ default: ++ case QAM_16: Corr = 1032; break; ++ case QAM_32: Corr = 954; break; ++ case QAM_64: Corr = 983; break; ++ case QAM_128: Corr = 957; break; ++ case QAM_256: Corr = 948; break; ++ } ++ ++ // Transfer ration ++ Temp = (256*sr) / state->adc_clock; ++ writereg(state, R367_QAM_EQU_CRL_TFR,(Temp)); ++ ++ /* Symbol rate and SRC gain calculation */ ++ AdpClk = (state->master_clock) / 2000; /* TRL works at half the system clock */ ++ ++ Temp = state->symbol_rate; ++ Temp1 = sr; ++ ++ if(sr < 2097152) /* 2097152 = 2^21 */ ++ { ++ Temp = ((((sr * 2048) / AdpClk) * 16384 ) / 125 ) * 8; ++ Temp1 = (((((sr * 2048) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 10000000; ++ } ++ else if(sr < 4194304) /* 4194304 = 2**22 */ ++ { ++ Temp = ((((sr * 1024) / AdpClk) * 16384 ) / 125 ) * 16; ++ Temp1 = (((((sr * 1024) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 5000000; ++ } ++ else if(sr < 8388608) /* 8388608 = 2**23 */ ++ { ++ Temp = ((((sr * 512) / AdpClk) * 16384 ) / 125 ) * 32; ++ Temp1 = (((((sr * 512) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 2500000; ++ } ++ else ++ { ++ Temp = ((((sr * 256) / AdpClk) * 16384 ) / 125 ) * 64; ++ Temp1 = (((((sr * 256) / 439 ) * 256 ) / AdpClk ) * Corr * 9 ) / 1250000; ++ } ++ ++ ///* Filters' coefficients are calculated and written into registers only if the filters are enabled */ ++ //if (ChipGetField(hChip,F367qam_ADJ_EN)) // Is disabled from init! ++ //{ ++ // FE_367qam_SetIirAdjacentcoefficient(hChip, MasterClk_Hz, SymbolRate); ++ //} ++ ///* AllPass filter is never used on this IC */ ++ //ChipSetField(hChip,F367qam_ALLPASSFILT_EN,0); // should be disabled from init! ++ ++ writereg(state, R367_QAM_SRC_NCO_LL,(Temp)); ++ writereg(state, R367_QAM_SRC_NCO_LH,(Temp>>8)); ++ writereg(state, R367_QAM_SRC_NCO_HL,(Temp>>16)); ++ writereg(state, R367_QAM_SRC_NCO_HH,(Temp>>24)); ++ ++ writereg(state, R367_QAM_IQDEM_GAIN_SRC_L,(Temp1)); ++ writereg(state, R367_QAM_IQDEM_GAIN_SRC_H,(Temp1>>8)); ++ return status; ++} ++ ++ ++static int QAM_SetDerotFrequency(struct stv_state *state, u32 DerotFrequency) ++{ ++ int status = 0; ++ u32 Sampled_IF; ++ ++ do { ++ //if (DerotFrequency < 1000000) ++ // DerotFrequency = state->adc_clock/4; /* ZIF operation */ ++ if (DerotFrequency > state->adc_clock) ++ DerotFrequency = DerotFrequency - state->adc_clock; // User Alias ++ ++ Sampled_IF = ((32768 * (DerotFrequency/1000)) / (state->adc_clock/1000)) * 256; ++ if(Sampled_IF > 8388607) ++ Sampled_IF = 8388607; ++ ++ writereg(state, R367_QAM_MIX_NCO_LL, (Sampled_IF)); ++ writereg(state, R367_QAM_MIX_NCO_HL, (Sampled_IF>>8)); ++ writereg(state, R367_QAM_MIX_NCO_HH, (Sampled_IF>>16)); ++ } while(0); ++ ++ return status; ++} ++ ++ ++ ++static int QAM_Start(struct stv_state *state, s32 offsetFreq,s32 IntermediateFrequency) ++{ ++ int status = 0; ++ u32 AGCTimeOut = 25; ++ u32 TRLTimeOut = 100000000 / state->symbol_rate; ++ u32 CRLSymbols = 0; ++ u32 EQLTimeOut = 100; ++ u32 SearchRange = state->symbol_rate / 25; ++ u32 CRLTimeOut; ++ u8 Temp; ++ ++ if( state->demod_state != QAMSet ) { ++ writereg(state, R367_DEBUG_LT4,0x00); ++ writereg(state, R367_DEBUG_LT5,0x01); ++ writereg(state, R367_DEBUG_LT6,0x06);// R367_QAM_CTRL_1 ++ writereg(state, R367_DEBUG_LT7,0x03);// R367_QAM_CTRL_2 ++ writereg(state, R367_DEBUG_LT8,0x00); ++ writereg(state, R367_DEBUG_LT9,0x00); ++ ++ // Tuner Setup ++ writereg(state, R367_ANADIGCTRL,0x8B); /* Buffer Q disabled, I Enabled, signed ADC */ ++ writereg(state, R367_DUAL_AD12,0x04); /* ADCQ disabled */ ++ ++ // Clock setup ++ writereg(state, R367_ANACTRL,0x0D); /* PLL bypassed and disabled */ ++ writereg(state, R367_TOPCTRL,0x10); // Set QAM ++ ++ writereg(state, R367_PLLMDIV,27); /* IC runs at 58 MHz with a 27 MHz crystal */ ++ writereg(state, R367_PLLNDIV,232); ++ writereg(state, R367_PLLSETUP,0x18); /* ADC clock is equal to system clock */ ++ ++ msleep(50); ++ writereg(state, R367_ANACTRL,0x00); /* PLL enabled and used */ ++ ++ state->master_clock = 58000000; ++ state->adc_clock = 58000000; ++ ++ state->demod_state = QAMSet; ++ } ++ ++ state->m_bFirstTimeLock = true; ++ state->m_DemodLockTime = -1; ++ ++ qam_set_modulation(state); ++ QAM_SetSymbolRate(state); ++ ++ // Will make problems on low symbol rates ( < 2500000 ) ++ ++ switch(state->modulation) { ++ default: ++ case QAM_16: CRLSymbols = 150000; break; ++ case QAM_32: CRLSymbols = 250000; break; ++ case QAM_64: CRLSymbols = 200000; break; ++ case QAM_128: CRLSymbols = 250000; break; ++ case QAM_256: CRLSymbols = 250000; break; ++ } ++ ++ CRLTimeOut = (25 * CRLSymbols * (SearchRange/1000)) / (state->symbol_rate/1000); ++ CRLTimeOut = (1000 * CRLTimeOut) / state->symbol_rate; ++ if( CRLTimeOut < 50 ) CRLTimeOut = 50; ++ ++ state->m_FECTimeOut = 20; ++ state->m_DemodTimeOut = AGCTimeOut + TRLTimeOut + CRLTimeOut + EQLTimeOut; ++ state->m_SignalTimeOut = AGCTimeOut + TRLTimeOut; ++ ++ // QAM_AGC_ACCUMRSTSEL = 0; ++ readreg(state, R367_QAM_AGC_CTL,&state->m_Save_QAM_AGC_CTL); ++ writereg(state, R367_QAM_AGC_CTL,state->m_Save_QAM_AGC_CTL & ~0x0F); ++ ++ // QAM_MODULUSMAP_EN = 0 ++ readreg(state, R367_QAM_EQU_PNT_GAIN,&Temp); ++ writereg(state, R367_QAM_EQU_PNT_GAIN,Temp & ~0x40); ++ ++ // QAM_SWEEP_EN = 0 ++ readreg(state, R367_QAM_EQU_CTR_LPF_GAIN,&Temp); ++ writereg(state, R367_QAM_EQU_CTR_LPF_GAIN,Temp & ~0x08); ++ ++ QAM_SetDerotFrequency(state, IntermediateFrequency); ++ ++ // Release TRL ++ writereg(state, R367_QAM_CTRL_1,0x00); ++ ++ state->IF = IntermediateFrequency; ++ state->demod_state = QAMStarted; ++ ++ return status; ++} ++ ++static int OFDM_Start(struct stv_state *state, s32 offsetFreq,s32 IntermediateFrequency) ++{ ++ int status = 0; ++ u8 GAIN_SRC1; ++ u32 Derot; ++ u8 SYR_CTL; ++ u8 tmp1; ++ u8 tmp2; ++ ++ if ( state->demod_state != OFDMSet ) { ++ // QAM Disable ++ writereg(state, R367_DEBUG_LT4, 0x00); ++ writereg(state, R367_DEBUG_LT5, 0x00); ++ writereg(state, R367_DEBUG_LT6, 0x00);// R367_QAM_CTRL_1 ++ writereg(state, R367_DEBUG_LT7, 0x00);// R367_QAM_CTRL_2 ++ writereg(state, R367_DEBUG_LT8, 0x00); ++ writereg(state, R367_DEBUG_LT9, 0x00); ++ ++ // Tuner Setup ++ writereg(state, R367_ANADIGCTRL, 0x89); /* Buffer Q disabled, I Enabled, unsigned ADC */ ++ writereg(state, R367_DUAL_AD12, 0x04); /* ADCQ disabled */ ++ ++ // Clock setup ++ writereg(state, R367_ANACTRL, 0x0D); /* PLL bypassed and disabled */ ++ writereg(state, R367_TOPCTRL, 0x00); // Set OFDM ++ ++ writereg(state, R367_PLLMDIV, 1); /* IC runs at 54 MHz with a 27 MHz crystal */ ++ writereg(state, R367_PLLNDIV, 8); ++ writereg(state, R367_PLLSETUP, 0x18); /* ADC clock is equal to system clock */ ++ ++ msleep(50); ++ writereg(state, R367_ANACTRL, 0x00); /* PLL enabled and used */ ++ ++ state->master_clock = 54000000; ++ state->adc_clock = 54000000; ++ ++ state->demod_state = OFDMSet; ++ } ++ ++ state->m_bFirstTimeLock = true; ++ state->m_DemodLockTime = -1; ++ ++ // Set inversion in GAIN_SRC1 (fixed from init) ++ // is in GAIN_SRC1, see below ++ ++ GAIN_SRC1 = 0xA0; ++ // Bandwidth ++ ++ // Fixed values for 54 MHz ++ switch(state->bandwidth) { ++ case 0: ++ case 8000000: ++ // Normrate = 44384; ++ writereg(state, R367_OFDM_TRL_CTL,0x14); ++ writereg(state, R367_OFDM_TRL_NOMRATE1,0xB0); ++ writereg(state, R367_OFDM_TRL_NOMRATE2,0x56); ++ // Gain SRC = 2774 ++ writereg(state, R367_OFDM_GAIN_SRC1,0x0A | GAIN_SRC1); ++ writereg(state, R367_OFDM_GAIN_SRC2,0xD6); ++ break; ++ case 7000000: ++ // Normrate = 38836; ++ writereg(state, R367_OFDM_TRL_CTL,0x14); ++ writereg(state, R367_OFDM_TRL_NOMRATE1,0xDA); ++ writereg(state, R367_OFDM_TRL_NOMRATE2,0x4B); ++ // Gain SRC = 2427 ++ writereg(state, R367_OFDM_GAIN_SRC1,0x09 | GAIN_SRC1); ++ writereg(state, R367_OFDM_GAIN_SRC2,0x7B); ++ break; ++ case 6000000: ++ // Normrate = 33288; ++ writereg(state, R367_OFDM_TRL_CTL,0x14); ++ writereg(state, R367_OFDM_TRL_NOMRATE1,0x04); ++ writereg(state, R367_OFDM_TRL_NOMRATE2,0x41); ++ // Gain SRC = 2080 ++ writereg(state, R367_OFDM_GAIN_SRC1,0x08 | GAIN_SRC1); ++ writereg(state, R367_OFDM_GAIN_SRC2,0x20); ++ break; ++ default: ++ return -EINVAL; ++ break; ++ } ++ ++ Derot = ((IntermediateFrequency / 1000) * 65536) / (state->master_clock / 1000); ++ ++ writereg(state, R367_OFDM_INC_DEROT1,(Derot>>8)); ++ writereg(state, R367_OFDM_INC_DEROT2,(Derot)); ++ ++ readreg(state, R367_OFDM_SYR_CTL,&SYR_CTL); ++ SYR_CTL &= ~0x78; ++ writereg(state, R367_OFDM_SYR_CTL,SYR_CTL); // EchoPos = 0 ++ ++ ++ writereg(state, R367_OFDM_COR_MODEGUARD,0x03); // Force = 0, Mode = 0, Guard = 3 ++ SYR_CTL &= 0x01; ++ writereg(state, R367_OFDM_SYR_CTL,SYR_CTL); // SYR_TR_DIS = 0 ++ ++ msleep(5); ++ ++ writereg(state, R367_OFDM_COR_CTL,0x20); // Start core ++ ++ // -- Begin M.V. ++ // Reset FEC and Read Solomon ++ readreg(state, R367_OFDM_SFDLYSETH,&tmp1); ++ readreg(state, R367_TSGENERAL,&tmp2); ++ writereg(state, R367_OFDM_SFDLYSETH,tmp1 | 0x08); ++ writereg(state, R367_TSGENERAL,tmp2 | 0x01); ++ // -- End M.V. ++ ++ state->m_SignalTimeOut = 200; ++ state->IF = IntermediateFrequency; ++ state->demod_state = OFDMStarted; ++ state->m_DemodTimeOut = 0; ++ state->m_FECTimeOut = 0; ++ state->m_TSTimeOut = 0; ++ ++ return status; ++} ++ ++#if 0 ++static int Stop(struct stv_state *state) ++{ ++ int status = 0; ++ ++ switch(state->demod_state) ++ { ++ case QAMStarted: ++ status = writereg(state, R367_QAM_CTRL_1,0x06); ++ state->demod_state = QAMSet; ++ break; ++ case OFDMStarted: ++ status = writereg(state, R367_OFDM_COR_CTL,0x00); ++ state->demod_state = OFDMSet; ++ break; ++ default: ++ break; ++ } ++ return status; ++} ++#endif ++ ++static s32 Log10x100(u32 x) ++{ ++ static u32 LookupTable[100] = { ++ 101157945, 103514217, 105925373, 108392691, 110917482, ++ 113501082, 116144861, 118850223, 121618600, 124451461, // 800.5 - 809.5 ++ 127350308, 130316678, 133352143, 136458314, 139636836, ++ 142889396, 146217717, 149623566, 153108746, 156675107, // 810.5 - 819.5 ++ 160324539, 164058977, 167880402, 171790839, 175792361, ++ 179887092, 184077200, 188364909, 192752491, 197242274, // 820.5 - 829.5 ++ 201836636, 206538016, 211348904, 216271852, 221309471, ++ 226464431, 231739465, 237137371, 242661010, 248313311, // 830.5 - 839.5 ++ 254097271, 260015956, 266072506, 272270131, 278612117, ++ 285101827, 291742701, 298538262, 305492111, 312607937, // 840.5 - 849.5 ++ 319889511, 327340695, 334965439, 342767787, 350751874, ++ 358921935, 367282300, 375837404, 384591782, 393550075, // 850.5 - 859.5 ++ 402717034, 412097519, 421696503, 431519077, 441570447, ++ 451855944, 462381021, 473151259, 484172368, 495450191, // 860.5 - 869.5 ++ 506990708, 518800039, 530884444, 543250331, 555904257, ++ 568852931, 582103218, 595662144, 609536897, 623734835, // 870.5 - 879.5 ++ 638263486, 653130553, 668343918, 683911647, 699841996, ++ 716143410, 732824533, 749894209, 767361489, 785235635, // 880.5 - 889.5 ++ 803526122, 822242650, 841395142, 860993752, 881048873, ++ 901571138, 922571427, 944060876, 966050879, 988553095, // 890.5 - 899.5 ++ }; ++ s32 y; ++ int i; ++ ++ if (x == 0) ++ return 0; ++ y = 800; ++ if (x >= 1000000000) { ++ x /= 10; ++ y += 100; ++ } ++ ++ while (x < 100000000) { ++ x *= 10; ++ y -= 100; ++ } ++ i = 0; ++ while (i < 100 && x > LookupTable[i]) ++ i += 1; ++ y += i; ++ return y; ++} ++ ++static int QAM_GetSignalToNoise(struct stv_state *state, s32 *pSignalToNoise) ++{ ++ u32 RegValAvg = 0; ++ u8 RegVal[2]; ++ int status = 0, i; ++ ++ *pSignalToNoise = 0; ++ for (i = 0; i < 10; i += 1 ) { ++ readregs(state, R367_QAM_EQU_SNR_LO, RegVal, 2); ++ RegValAvg += RegVal[0] + 256 * RegVal[1]; ++ } ++ if (RegValAvg != 0) { ++ s32 Power = 1; ++ switch(state->modulation) { ++ case QAM_16: ++ Power = 20480; ++ break; ++ case QAM_32: ++ Power = 23040; ++ break; ++ case QAM_64: ++ Power = 21504; ++ break; ++ case QAM_128: ++ Power = 23616; ++ break; ++ case QAM_256: ++ Power = 21760; ++ break; ++ default: ++ break; ++ } ++ *pSignalToNoise = Log10x100((Power * 320) / RegValAvg); ++ } else { ++ *pSignalToNoise = 380; ++ } ++ return status; ++} ++ ++static int OFDM_GetSignalToNoise(struct stv_state *state, s32 *pSignalToNoise) ++{ ++ u8 CHC_SNR = 0; ++ ++ int status = readreg(state, R367_OFDM_CHC_SNR, &CHC_SNR); ++ if (status >= 0) { ++ // Note: very unclear documentation on this. ++ // Datasheet states snr = CHC_SNR/4 dB -> way to high values! ++ // Software snr = ( 1000 * CHC_SNR ) / 8 / 32 / 10; -> to low values ++ // Comment in SW states this should be ( 1000 * CHC_SNR ) / 4 / 32 / 10; for the 367 ++ // 361/362 Datasheet: snr = CHC_SNR/8 dB -> this looks best ++ *pSignalToNoise = ( (s32)CHC_SNR * 10) / 8; ++ } ++ //printk("SNR %d\n", *pSignalToNoise); ++ return status; ++} ++ ++#if 0 ++static int DVBC_GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) ++{ ++ *pQuality = 100; ++ return 0; ++}; ++ ++static int DVBT_GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) ++{ ++ static s32 QE_SN[] = { ++ 51, // QPSK 1/2 ++ 69, // QPSK 2/3 ++ 79, // QPSK 3/4 ++ 89, // QPSK 5/6 ++ 97, // QPSK 7/8 ++ 108, // 16-QAM 1/2 ++ 131, // 16-QAM 2/3 ++ 146, // 16-QAM 3/4 ++ 156, // 16-QAM 5/6 ++ 160, // 16-QAM 7/8 ++ 165, // 64-QAM 1/2 ++ 187, // 64-QAM 2/3 ++ 202, // 64-QAM 3/4 ++ 216, // 64-QAM 5/6 ++ 225, // 64-QAM 7/8 ++ }; ++ u8 TPS_Received[2]; ++ int Constellation; ++ int CodeRate; ++ s32 SignalToNoiseRel, BERQuality; ++ ++ *pQuality = 0; ++ readregs(state, R367_OFDM_TPS_RCVD2, TPS_Received, sizeof(TPS_Received)); ++ Constellation = TPS_Received[0] & 0x03; ++ CodeRate = TPS_Received[1] & 0x07; ++ ++ if( Constellation > 2 || CodeRate > 5 ) ++ return -1; ++ SignalToNoiseRel = SignalToNoise - QE_SN[Constellation * 5 + CodeRate]; ++ BERQuality = 100; ++ ++ if( SignalToNoiseRel < -70 ) ++ *pQuality = 0; ++ else if( SignalToNoiseRel < 30 ) { ++ *pQuality = ((SignalToNoiseRel + 70) * BERQuality)/100; ++ } else ++ *pQuality = BERQuality; ++ return 0; ++}; ++ ++static s32 DVBCQuality(struct stv_state *state, s32 SignalToNoise) ++{ ++ s32 SignalToNoiseRel = 0; ++ s32 Quality = 0; ++ s32 BERQuality = 100; ++ ++ switch(state->modulation) { ++ case QAM_16: SignalToNoiseRel = SignalToNoise - 200 ; break; ++ case QAM_32: SignalToNoiseRel = SignalToNoise - 230 ; break; // Not in NorDig ++ case QAM_64: SignalToNoiseRel = SignalToNoise - 260 ; break; ++ case QAM_128: SignalToNoiseRel = SignalToNoise - 290 ; break; ++ case QAM_256: SignalToNoiseRel = SignalToNoise - 320 ; break; ++ } ++ ++ if( SignalToNoiseRel < -70 ) Quality = 0; ++ else if( SignalToNoiseRel < 30 ) ++ { ++ Quality = ((SignalToNoiseRel + 70) * BERQuality)/100; ++ } ++ else ++ Quality = BERQuality; ++ ++ return Quality; ++} ++ ++static int GetQuality(struct stv_state *state, s32 SignalToNoise, s32 *pQuality) ++{ ++ *pQuality = 0; ++ switch(state->demod_state) ++ { ++ case QAMStarted: ++ *pQuality = DVBCQuality(state, SignalToNoise); ++ break; ++ case OFDMStarted: ++ return DVBT_GetQuality(state, SignalToNoise, pQuality); ++ } ++ return 0; ++}; ++#endif ++ ++static int attach_init(struct stv_state *state) ++{ ++ int stat = 0; ++ ++ stat = readreg(state, R367_ID, &state->ID); ++ if ( stat < 0 || state->ID != 0x60 ) ++ return -ENODEV; ++ printk("stv0367 found\n"); ++ ++ writereg(state, R367_TOPCTRL, 0x10); ++ write_init_table(state, base_init); ++ write_init_table(state, qam_init); ++ ++ writereg(state, R367_TOPCTRL, 0x00); ++ write_init_table(state, ofdm_init); ++ ++ writereg(state, R367_OFDM_GAIN_SRC1, 0x2A); ++ writereg(state, R367_OFDM_GAIN_SRC2, 0xD6); ++ writereg(state, R367_OFDM_INC_DEROT1, 0x55); ++ writereg(state, R367_OFDM_INC_DEROT2, 0x55); ++ writereg(state, R367_OFDM_TRL_CTL, 0x14); ++ writereg(state, R367_OFDM_TRL_NOMRATE1, 0xAE); ++ writereg(state, R367_OFDM_TRL_NOMRATE2, 0x56); ++ writereg(state, R367_OFDM_FEPATH_CFG, 0x0); ++ ++ // OFDM TS Setup ++ ++ writereg(state, R367_OFDM_TSCFGH, 0x70); ++ writereg(state, R367_OFDM_TSCFGM, 0xC0); ++ writereg(state, R367_OFDM_TSCFGL, 0x20); ++ writereg(state, R367_OFDM_TSSPEED, 0x40); // Fixed at 54 MHz ++ //writereg(state, R367_TSTBUS, 0x80); // Invert CLK ++ ++ writereg(state, R367_OFDM_TSCFGH, 0x71); ++ writereg(state, R367_OFDM_TSCFGH, 0x70); ++ ++ writereg(state, R367_TOPCTRL, 0x10); ++ ++ // Also needed for QAM ++ writereg(state, R367_OFDM_AGC12C, 0x01); // AGC Pin setup ++ ++ writereg(state, R367_OFDM_AGCCTRL1, 0x8A); // ++ ++ // QAM TS setup, note exact format also depends on descrambler settings ++ writereg(state, R367_QAM_OUTFORMAT_0, 0x85); // Inverted Clock, Swap, serial ++ // writereg(state, R367_QAM_OUTFORMAT_1, 0x00); // ++ ++ // Clock setup ++ writereg(state, R367_ANACTRL, 0x0D); /* PLL bypassed and disabled */ ++ ++ if( state->master_clock == 58000000 ) { ++ writereg(state, R367_PLLMDIV,27); /* IC runs at 58 MHz with a 27 MHz crystal */ ++ writereg(state, R367_PLLNDIV,232); ++ } else { ++ writereg(state, R367_PLLMDIV,1); /* IC runs at 54 MHz with a 27 MHz crystal */ ++ writereg(state, R367_PLLNDIV,8); ++ } ++ writereg(state, R367_PLLSETUP, 0x18); /* ADC clock is equal to system clock */ ++ ++ // Tuner setup ++ writereg(state, R367_ANADIGCTRL, 0x8b); /* Buffer Q disabled, I Enabled, signed ADC */ ++ writereg(state, R367_DUAL_AD12, 0x04); /* ADCQ disabled */ ++ ++ writereg(state, R367_QAM_FSM_SNR2_HTH, 0x23); /* Improves the C/N lock limit */ ++ writereg(state, R367_QAM_IQ_QAM, 0x01); /* ZIF/IF Automatic mode */ ++ writereg(state, R367_QAM_EQU_FFE_LEAKAGE, 0x83); /* Improving burst noise performances */ ++ writereg(state, R367_QAM_IQDEM_ADJ_EN, 0x05); /* Improving ACI performances */ ++ ++ writereg(state, R367_ANACTRL, 0x00); /* PLL enabled and used */ ++ ++ writereg(state, R367_I2CRPT, state->I2CRPT); ++ state->demod_state = QAMSet; ++ return stat; ++} ++ ++#ifdef USE_API3 ++static void c_release(struct dvb_frontend* fe) ++#else ++static void release(struct dvb_frontend* fe) ++#endif ++{ ++ struct stv_state *state=fe->demodulator_priv; ++ printk("%s\n", __FUNCTION__); ++ kfree(state); ++} ++ ++#ifdef USE_API3 ++static int c_init (struct dvb_frontend *fe) ++{ ++ struct stv_state *state=fe->demodulator_priv; ++ ++ if (mutex_trylock(&state->ctlock)==0) ++ return -EBUSY; ++ state->omode = OM_DVBC; ++ return 0; ++} ++ ++static int c_sleep(struct dvb_frontend* fe) ++{ ++ struct stv_state *state=fe->demodulator_priv; ++ ++ mutex_unlock(&state->ctlock); ++ return 0; ++} ++#endif ++ ++static int gate_ctrl(struct dvb_frontend *fe, int enable) ++{ ++ struct stv_state *state = fe->demodulator_priv; ++ u8 i2crpt = state->I2CRPT & ~0x80; ++ ++ if (enable) ++ i2crpt |= 0x80; ++ if (writereg(state, R367_I2CRPT, i2crpt) < 0) ++ return -1; ++ state->I2CRPT = i2crpt; ++ return 0; ++} ++ ++#if 0 ++static int c_track(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) ++{ ++ return DVBFE_ALGO_SEARCH_AGAIN; ++} ++#endif ++ ++#if 0 ++int (*set_property)(struct dvb_frontend* fe, struct dtv_property* tvp); ++int (*get_property)(struct dvb_frontend* fe, struct dtv_property* tvp); ++#endif ++ ++static int ofdm_lock(struct stv_state *state) ++{ ++ int status = 0; ++ u8 OFDM_Status; ++ s32 DemodTimeOut = 10; ++ s32 FECTimeOut = 0; ++ s32 TSTimeOut = 0; ++ u8 CPAMPMin = 255; ++ u8 CPAMPValue; ++ u8 SYR_STAT; ++ u8 FFTMode; ++ u8 TSStatus; ++ ++ msleep(state->m_SignalTimeOut); ++ readreg(state, R367_OFDM_STATUS,&OFDM_Status); ++ ++ if (!(OFDM_Status & 0x40)) ++ return -1; ++ //printk("lock 1\n"); ++ ++ readreg(state, R367_OFDM_SYR_STAT,&SYR_STAT); ++ FFTMode = (SYR_STAT & 0x0C) >> 2; ++ ++ switch(FFTMode) ++ { ++ case 0: // 2K ++ DemodTimeOut = 10; ++ FECTimeOut = 150; ++ TSTimeOut = 125; ++ CPAMPMin = 20; ++ break; ++ case 1: // 8K ++ DemodTimeOut = 55; ++ FECTimeOut = 600; ++ TSTimeOut = 500; ++ CPAMPMin = 80; ++ break; ++ case 2: // 4K ++ DemodTimeOut = 40; ++ FECTimeOut = 300; ++ TSTimeOut = 250; ++ CPAMPMin = 30; ++ break; ++ } ++ state->m_OFDM_FFTMode = FFTMode; ++ readreg(state, R367_OFDM_PPM_CPAMP_DIR,&CPAMPValue); ++ msleep(DemodTimeOut); ++ { ++ // Release FEC and Read Solomon Reset ++ u8 tmp1; ++ u8 tmp2; ++ readreg(state, R367_OFDM_SFDLYSETH,&tmp1); ++ readreg(state, R367_TSGENERAL,&tmp2); ++ writereg(state, R367_OFDM_SFDLYSETH,tmp1 & ~0x08); ++ writereg(state, R367_TSGENERAL,tmp2 & ~0x01); ++ } ++ msleep(FECTimeOut); ++ if( (OFDM_Status & 0x98) != 0x98 ) ++ ;//return -1; ++ //printk("lock 2\n"); ++ ++ { ++ u8 Guard = (SYR_STAT & 0x03); ++ if(Guard < 2) ++ { ++ u8 tmp; ++ readreg(state, R367_OFDM_SYR_CTL,&tmp); ++ writereg(state, R367_OFDM_SYR_CTL,tmp & ~0x04); // Clear AUTO_LE_EN ++ readreg(state, R367_OFDM_SYR_UPDATE,&tmp); ++ writereg(state, R367_OFDM_SYR_UPDATE,tmp & ~0x10); // Clear SYR_FILTER ++ } else { ++ u8 tmp; ++ readreg(state, R367_OFDM_SYR_CTL,&tmp); ++ writereg(state, R367_OFDM_SYR_CTL,tmp | 0x04); // Set AUTO_LE_EN ++ readreg(state, R367_OFDM_SYR_UPDATE,&tmp); ++ writereg(state, R367_OFDM_SYR_UPDATE,tmp | 0x10); // Set SYR_FILTER ++ } ++ ++ // apply Sfec workaround if 8K 64QAM CR!=1/2 ++ if( FFTMode == 1) ++ { ++ u8 tmp[2]; ++ readregs(state, R367_OFDM_TPS_RCVD2, tmp, 2); ++ if( ((tmp[0] & 0x03) == 0x02) && (( tmp[1] & 0x07 ) != 0) ) ++ { ++ writereg(state, R367_OFDM_SFDLYSETH,0xc0); ++ writereg(state, R367_OFDM_SFDLYSETM,0x60); ++ writereg(state, R367_OFDM_SFDLYSETL,0x00); ++ } ++ else ++ { ++ writereg(state, R367_OFDM_SFDLYSETH,0x00); ++ } ++ } ++ } ++ msleep(TSTimeOut); ++ readreg(state, R367_OFDM_TSSTATUS,&TSStatus); ++ if( (TSStatus & 0x80) != 0x80 ) ++ return -1; ++ //printk("lock 3\n"); ++ return status; ++} ++ ++ ++#ifdef USE_API3 ++static int set_parameters(struct dvb_frontend *fe, ++ struct dvb_frontend_parameters *p) ++{ ++ int stat; ++ struct stv_state *state = fe->demodulator_priv; ++ u32 OF = 0; ++ u32 IF; ++ ++ if (fe->ops.tuner_ops.set_params) ++ fe->ops.tuner_ops.set_params(fe, p); ++ ++ switch (state->omode) { ++ case OM_DVBC: ++ case OM_QAM_ITU_C: ++ state->modulation = p->u.qam.modulation; ++ state->symbol_rate = p->u.qam.symbol_rate; ++ break; ++ case OM_DVBT: ++ switch (p->u.ofdm.bandwidth) { ++ case BANDWIDTH_AUTO: ++ case BANDWIDTH_8_MHZ: ++ state->bandwidth = 8000000; ++ break; ++ case BANDWIDTH_7_MHZ: ++ state->bandwidth = 7000000; ++ break; ++ case BANDWIDTH_6_MHZ: ++ state->bandwidth = 6000000; ++ break; ++ default: ++ return -EINVAL; ++ } ++ break; ++ default: ++ return -EINVAL; ++ } ++#else ++static int set_parameters(struct dvb_frontend *fe) ++{ ++ int stat; ++ struct stv_state *state = fe->demodulator_priv; ++ u32 OF = 0; ++ u32 IF; ++ ++ switch (fe->dtv_property_cache.delivery_system) { ++ case SYS_DVBC_ANNEX_A: ++ state->omode = OM_DVBC; ++ /* symbol rate 0 might cause an oops */ ++ if (fe->dtv_property_cache.symbol_rate == 0) { ++ printk(KERN_ERR "stv0367dd: Invalid symbol rate\n"); ++ return -EINVAL; ++ } ++ break; ++ case SYS_DVBT: ++ state->omode = OM_DVBT; ++ break; ++ default: ++ return -EINVAL; ++ } ++ if (fe->ops.tuner_ops.set_params) ++ fe->ops.tuner_ops.set_params(fe); ++ state->modulation = fe->dtv_property_cache.modulation; ++ state->symbol_rate = fe->dtv_property_cache.symbol_rate; ++ state->bandwidth = fe->dtv_property_cache.bandwidth_hz; ++#endif ++ fe->ops.tuner_ops.get_if_frequency(fe, &IF); ++ //fe->ops.tuner_ops.get_frequency(fe, &IF); ++ ++ switch(state->omode) { ++ case OM_DVBT: ++ stat = OFDM_Start(state, OF, IF); ++ ofdm_lock(state); ++ break; ++ case OM_DVBC: ++ case OM_QAM_ITU_C: ++ stat = QAM_Start(state, OF, IF); ++ break; ++ default: ++ stat = -EINVAL; ++ } ++ //printk("%s IF=%d OF=%d done\n", __FUNCTION__, IF, OF); ++ return stat; ++} ++ ++#if 0 ++static int c_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) ++{ ++ //struct stv_state *state = fe->demodulator_priv; ++ //printk("%s\n", __FUNCTION__); ++ return 0; ++} ++ ++static int OFDM_GetLockStatus(struct stv_state *state, LOCK_STATUS* pLockStatus, s32 Time) ++{ ++ int status = STATUS_SUCCESS; ++ u8 OFDM_Status; ++ s32 DemodTimeOut = 0; ++ s32 FECTimeOut = 0; ++ s32 TSTimeOut = 0; ++ u8 CPAMPMin = 255; ++ u8 CPAMPValue; ++ bool SYRLock; ++ u8 SYR_STAT; ++ u8 FFTMode; ++ u8 TSStatus; ++ ++ readreg(state, R367_OFDM_STATUS,&OFDM_Status); ++ ++ SYRLock = (OFDM_Status & 0x40) != 0; ++ ++ if( Time > m_SignalTimeOut && !SYRLock ) ++ { ++ *pLockStatus = NEVER_LOCK; ++ break; ++ } ++ ++ if( !SYRLock ) break; ++ ++ *pLockStatus = SIGNAL_PRESENT; ++ ++ // Check Mode ++ ++ readreg(state, R367_OFDM_SYR_STAT,&SYR_STAT); ++ FFTMode = (SYR_STAT & 0x0C) >> 2; ++ ++ switch(FFTMode) ++ { ++ case 0: // 2K ++ DemodTimeOut = 10; ++ FECTimeOut = 150; ++ TSTimeOut = 125; ++ CPAMPMin = 20; ++ break; ++ case 1: // 8K ++ DemodTimeOut = 55; ++ FECTimeOut = 600; ++ TSTimeOut = 500; ++ CPAMPMin = 80; ++ break; ++ case 2: // 4K ++ DemodTimeOut = 40; ++ FECTimeOut = 300; ++ TSTimeOut = 250; ++ CPAMPMin = 30; ++ break; ++ } ++ ++ m_OFDM_FFTMode = FFTMode; ++ ++ if( m_DemodTimeOut == 0 && m_bFirstTimeLock ) ++ { ++ m_DemodTimeOut = Time + DemodTimeOut; ++ //break; ++ } ++ ++ readreg(state, R367_OFDM_PPM_CPAMP_DIR,&CPAMPValue); ++ ++ if( Time <= m_DemodTimeOut && CPAMPValue < CPAMPMin ) ++ { ++ break; ++ } ++ ++ if( CPAMPValue < CPAMPMin && m_bFirstTimeLock ) ++ { ++ // initiate retry ++ *pLockStatus = NEVER_LOCK; ++ break; ++ } ++ ++ if( CPAMPValue < CPAMPMin ) break; ++ ++ *pLockStatus = DEMOD_LOCK; ++ ++ if( m_FECTimeOut == 0 && m_bFirstTimeLock ) ++ { ++ // Release FEC and Read Solomon Reset ++ u8 tmp1; ++ u8 tmp2; ++ readreg(state, R367_OFDM_SFDLYSETH,&tmp1); ++ readreg(state, R367_TSGENERAL,&tmp2); ++ writereg(state, R367_OFDM_SFDLYSETH,tmp1 & ~0x08); ++ writereg(state, R367_TSGENERAL,tmp2 & ~0x01); ++ ++ m_FECTimeOut = Time + FECTimeOut; ++ } ++ ++ // Wait for TSP_LOCK, LK, PRF ++ if( (OFDM_Status & 0x98) != 0x98 ) ++ { ++ if( Time > m_FECTimeOut ) *pLockStatus = NEVER_LOCK; ++ break; ++ } ++ ++ if( m_bFirstTimeLock && m_TSTimeOut == 0) ++ { ++ u8 Guard = (SYR_STAT & 0x03); ++ if(Guard < 2) ++ { ++ u8 tmp; ++ readreg(state, R367_OFDM_SYR_CTL,&tmp); ++ writereg(state, R367_OFDM_SYR_CTL,tmp & ~0x04); // Clear AUTO_LE_EN ++ readreg(state, R367_OFDM_SYR_UPDATE,&tmp); ++ writereg(state, R367_OFDM_SYR_UPDATE,tmp & ~0x10); // Clear SYR_FILTER ++ } else { ++ u8 tmp; ++ readreg(state, R367_OFDM_SYR_CTL,&tmp); ++ writereg(state, R367_OFDM_SYR_CTL,tmp | 0x04); // Set AUTO_LE_EN ++ readreg(state, R367_OFDM_SYR_UPDATE,&tmp); ++ writereg(state, R367_OFDM_SYR_UPDATE,tmp | 0x10); // Set SYR_FILTER ++ } ++ ++ // apply Sfec workaround if 8K 64QAM CR!=1/2 ++ if( FFTMode == 1) ++ { ++ u8 tmp[2]; ++ readreg(state, R367_OFDM_TPS_RCVD2,tmp,2); ++ if( ((tmp[0] & 0x03) == 0x02) && (( tmp[1] & 0x07 ) != 0) ) ++ { ++ writereg(state, R367_OFDM_SFDLYSETH,0xc0); ++ writereg(state, R367_OFDM_SFDLYSETM,0x60); ++ writereg(state, R367_OFDM_SFDLYSETL,0x00); ++ } ++ else ++ { ++ writereg(state, R367_OFDM_SFDLYSETH,0x00); ++ } ++ } ++ ++ m_TSTimeOut = Time + TSTimeOut; ++ } ++ readreg(state, R367_OFDM_TSSTATUS,&TSStatus); ++ if( (TSStatus & 0x80) != 0x80 ) ++ { ++ if( Time > m_TSTimeOut ) *pLockStatus = NEVER_LOCK; ++ break; ++ } ++ *pLockStatus = MPEG_LOCK; ++ m_bFirstTimeLock = false; ++ return status; ++} ++ ++#endif ++ ++static int read_status(struct dvb_frontend *fe, fe_status_t *status) ++{ ++ struct stv_state *state = fe->demodulator_priv; ++ *status=0; ++ ++ switch(state->demod_state) { ++ case QAMStarted: ++ { ++ u8 FEC_Lock; ++ u8 QAM_Lock; ++ ++ readreg(state, R367_QAM_FSM_STS, &QAM_Lock); ++ QAM_Lock &= 0x0F; ++ if (QAM_Lock >10) ++ *status|=0x07; ++ readreg(state, R367_QAM_FEC_STATUS,&FEC_Lock); ++ if (FEC_Lock&2) ++ *status|=0x1f; ++ if (state->m_bFirstTimeLock) { ++ state->m_bFirstTimeLock = false; ++ // QAM_AGC_ACCUMRSTSEL to Tracking; ++ writereg(state, R367_QAM_AGC_CTL, state->m_Save_QAM_AGC_CTL); ++ } ++ break; ++ } ++ case OFDMStarted: ++ { ++ u8 OFDM_Status; ++ u8 TSStatus; ++ ++ readreg(state, R367_OFDM_TSSTATUS, &TSStatus); ++ ++ readreg(state, R367_OFDM_STATUS, &OFDM_Status); ++ if (OFDM_Status & 0x40) ++ *status |= FE_HAS_SIGNAL; ++ ++ if ((OFDM_Status & 0x98) == 0x98) ++ *status|=0x0f; ++ ++ if (TSStatus & 0x80) ++ *status |= 0x1f; ++ break; ++ } ++ default: ++ break; ++ } ++ return 0; ++} ++ ++static int read_ber_ter(struct dvb_frontend *fe, u32 *ber) ++{ ++ struct stv_state *state = fe->demodulator_priv; ++ u32 err; ++ u8 cnth, cntm, cntl; ++ ++#if 1 ++ readreg(state, R367_OFDM_SFERRCNTH, &cnth); ++ ++ if (cnth & 0x80) { ++ *ber = state->ber; ++ return 0; ++ } ++ ++ readreg(state, R367_OFDM_SFERRCNTM, &cntm); ++ readreg(state, R367_OFDM_SFERRCNTL, &cntl); ++ ++ err = ((cnth & 0x7f) << 16) | (cntm << 8) | cntl; ++ ++#if 0 ++ { ++ u64 err64; ++ err64 = (u64) err; ++ err64 *= 1000000000ULL; ++ err64 >>= 21; ++ err = err64; ++ } ++#endif ++#else ++ readreg(state, R367_OFDM_ERRCNT1HM, &cnth); ++ ++#endif ++ *ber = state->ber = err; ++ return 0; ++} ++ ++static int read_ber_cab(struct dvb_frontend *fe, u32 *ber) ++{ ++ struct stv_state *state = fe->demodulator_priv; ++ u32 err; ++ u8 cntm, cntl, ctrl; ++ ++ readreg(state, R367_QAM_BERT_1, &ctrl); ++ if (!(ctrl & 0x20)) { ++ readreg(state, R367_QAM_BERT_2, &cntl); ++ readreg(state, R367_QAM_BERT_3, &cntm); ++ err = (cntm << 8) | cntl; ++ //printk("err %04x\n", err); ++ state->ber = err; ++ writereg(state, R367_QAM_BERT_1, 0x27); ++ } ++ *ber = (u32) state->ber; ++ return 0; ++} ++ ++static int read_ber(struct dvb_frontend *fe, u32 *ber) ++{ ++ struct stv_state *state = fe->demodulator_priv; ++ ++ if (state->demod_state == QAMStarted) ++ return read_ber_cab(fe, ber); ++ if (state->demod_state == OFDMStarted) ++ return read_ber_ter(fe, ber); ++ *ber = 0; ++ return 0; ++} ++ ++static int read_signal_strength(struct dvb_frontend *fe, u16 *strength) ++{ ++ if (fe->ops.tuner_ops.get_rf_strength) ++ fe->ops.tuner_ops.get_rf_strength(fe, strength); ++ else ++ *strength = 0; ++ return 0; ++} ++ ++static int read_snr(struct dvb_frontend *fe, u16 *snr) ++{ ++ struct stv_state *state = fe->demodulator_priv; ++ s32 snr2 = 0; ++ ++ switch(state->demod_state) { ++ case QAMStarted: ++ QAM_GetSignalToNoise(state, &snr2); ++ break; ++ case OFDMStarted: ++ OFDM_GetSignalToNoise(state, &snr2); ++ break; ++ default: ++ break; ++ } ++ *snr = snr2&0xffff; ++ return 0; ++} ++ ++static int read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) ++{ ++ struct stv_state *state = fe->demodulator_priv; ++ u8 errl, errm, errh; ++ u8 val; ++ ++ switch(state->demod_state) { ++ case QAMStarted: ++ readreg(state, R367_QAM_RS_COUNTER_4, &errl); ++ readreg(state, R367_QAM_RS_COUNTER_5, &errm); ++ *ucblocks = (errm << 8) | errl; ++ break; ++ case OFDMStarted: ++ readreg(state, R367_OFDM_SFERRCNTH, &val); ++ if ((val & 0x80) == 0) { ++ readreg(state, R367_OFDM_ERRCNT1H, &errh); ++ readreg(state, R367_OFDM_ERRCNT1M, &errl); ++ readreg(state, R367_OFDM_ERRCNT1L, &errm); ++ state->ucblocks = (errh <<16) | (errm << 8) | errl; ++ } ++ *ucblocks = state->ucblocks; ++ break; ++ default: ++ *ucblocks = 0; ++ break; ++ } ++ return 0; ++} ++ ++static int c_get_tune_settings(struct dvb_frontend *fe, ++ struct dvb_frontend_tune_settings *sets) ++{ ++ sets->min_delay_ms=3000; ++ sets->max_drift=0; ++ sets->step_size=0; ++ return 0; ++} ++ ++#ifndef USE_API3 ++static int get_tune_settings(struct dvb_frontend *fe, ++ struct dvb_frontend_tune_settings *sets) ++{ ++ switch (fe->dtv_property_cache.delivery_system) { ++ case SYS_DVBC_ANNEX_A: ++ case SYS_DVBC_ANNEX_C: ++ return c_get_tune_settings(fe, sets); ++ default: ++ /* DVB-T: Use info.frequency_stepsize. */ ++ return -EINVAL; ++ } ++} ++#endif ++ ++#ifdef USE_API3 ++static void t_release(struct dvb_frontend* fe) ++{ ++ //struct stv_state *state=fe->demodulator_priv; ++ //printk("%s\n", __FUNCTION__); ++ //kfree(state); ++} ++ ++static int t_init (struct dvb_frontend *fe) ++{ ++ struct stv_state *state=fe->demodulator_priv; ++ if (mutex_trylock(&state->ctlock)==0) ++ return -EBUSY; ++ state->omode = OM_DVBT; ++ return 0; ++} ++ ++static int t_sleep(struct dvb_frontend* fe) ++{ ++ struct stv_state *state=fe->demodulator_priv; ++ mutex_unlock(&state->ctlock); ++ return 0; ++} ++#endif ++ ++#if 0 ++static int t_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) ++{ ++ //struct stv_state *state = fe->demodulator_priv; ++ //printk("%s\n", __FUNCTION__); ++ return 0; ++} ++ ++static enum dvbfe_algo algo(struct dvb_frontend *fe) ++{ ++ return DVBFE_ALGO_CUSTOM; ++} ++#endif ++ ++#ifdef USE_API3 ++static struct dvb_frontend_ops c_ops = { ++ .info = { ++ .name = "STV0367 DVB-C", ++ .type = FE_QAM, ++ .frequency_stepsize = 62500, ++ .frequency_min = 47000000, ++ .frequency_max = 862000000, ++ .symbol_rate_min = 870000, ++ .symbol_rate_max = 11700000, ++ .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | ++ FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO ++ }, ++ .release = c_release, ++ .init = c_init, ++ .sleep = c_sleep, ++ .i2c_gate_ctrl = gate_ctrl, ++ ++ .get_tune_settings = c_get_tune_settings, ++ ++ .read_status = read_status, ++ .read_ber = read_ber, ++ .read_signal_strength = read_signal_strength, ++ .read_snr = read_snr, ++ .read_ucblocks = read_ucblocks, ++ ++#if 1 ++ .set_frontend = set_parameters, ++#else ++ .get_frontend_algo = algo, ++ .search = search, ++#endif ++}; ++ ++static struct dvb_frontend_ops t_ops = { ++ .info = { ++ .name = "STV0367 DVB-T", ++ .type = FE_OFDM, ++ .frequency_min = 47125000, ++ .frequency_max = 865000000, ++ .frequency_stepsize = 166667, ++ .frequency_tolerance = 0, ++ .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | ++ FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | ++ FE_CAN_FEC_AUTO | ++ FE_CAN_QAM_16 | FE_CAN_QAM_64 | ++ FE_CAN_QAM_AUTO | ++ FE_CAN_TRANSMISSION_MODE_AUTO | ++ FE_CAN_GUARD_INTERVAL_AUTO | ++ FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | ++ FE_CAN_MUTE_TS ++ }, ++ .release = t_release, ++ .init = t_init, ++ .sleep = t_sleep, ++ .i2c_gate_ctrl = gate_ctrl, ++ ++ .set_frontend = set_parameters, ++ ++ .read_status = read_status, ++ .read_ber = read_ber, ++ .read_signal_strength = read_signal_strength, ++ .read_snr = read_snr, ++ .read_ucblocks = read_ucblocks, ++}; ++ ++#else ++ ++static struct dvb_frontend_ops common_ops = { ++ .delsys = { SYS_DVBC_ANNEX_A, SYS_DVBT }, ++ .info = { ++ .name = "STV0367 DVB-C DVB-T", ++ .frequency_stepsize = 166667, /* DVB-T only */ ++ .frequency_min = 47000000, /* DVB-T: 47125000 */ ++ .frequency_max = 865000000, /* DVB-C: 862000000 */ ++ .symbol_rate_min = 870000, ++ .symbol_rate_max = 11700000, ++ .caps = /* DVB-C */ ++ FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | ++ FE_CAN_QAM_128 | FE_CAN_QAM_256 | ++ FE_CAN_FEC_AUTO | ++ /* DVB-T */ ++ FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO | ++ FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | ++ FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | ++ FE_CAN_TRANSMISSION_MODE_AUTO | ++ FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | ++ FE_CAN_RECOVER | FE_CAN_MUTE_TS ++ }, ++ .release = release, ++ .i2c_gate_ctrl = gate_ctrl, ++ ++ .get_tune_settings = get_tune_settings, ++ ++ .set_frontend = set_parameters, ++ ++ .read_status = read_status, ++ .read_ber = read_ber, ++ .read_signal_strength = read_signal_strength, ++ .read_snr = read_snr, ++ .read_ucblocks = read_ucblocks, ++}; ++#endif ++ ++ ++static void init_state(struct stv_state *state, struct stv0367_cfg *cfg) ++{ ++ u32 ulENARPTLEVEL = 5; ++ u32 ulQAMInversion = 2; ++ state->omode = OM_NONE; ++ state->adr = cfg->adr; ++ ++ mutex_init(&state->mutex); ++ mutex_init(&state->ctlock); ++ ++#ifdef USE_API3 ++ memcpy(&state->c_frontend.ops, &c_ops, sizeof(struct dvb_frontend_ops)); ++ memcpy(&state->t_frontend.ops, &t_ops, sizeof(struct dvb_frontend_ops)); ++ state->c_frontend.demodulator_priv = state; ++ state->t_frontend.demodulator_priv = state; ++#else ++ memcpy(&state->frontend.ops, &common_ops, sizeof(struct dvb_frontend_ops)); ++ state->frontend.demodulator_priv = state; ++#endif ++ ++ state->master_clock = 58000000; ++ state->adc_clock = 58000000; ++ state->I2CRPT = 0x08 | ((ulENARPTLEVEL & 0x07) << 4); ++ state->qam_inversion = ((ulQAMInversion & 3) << 6 ); ++ state->demod_state = Off; ++} ++ ++ ++struct dvb_frontend *stv0367_attach(struct i2c_adapter *i2c, struct stv0367_cfg *cfg, ++ struct dvb_frontend **fe_t) ++{ ++ struct stv_state *state = NULL; ++ ++ state = kzalloc(sizeof(struct stv_state), GFP_KERNEL); ++ if (!state) ++ return NULL; ++ ++ state->i2c = i2c; ++ init_state(state, cfg); ++ ++ if (attach_init(state)<0) ++ goto error; ++#ifdef USE_API3 ++ *fe_t = &state->t_frontend; ++ return &state->c_frontend; ++#else ++ return &state->frontend; ++#endif ++ ++error: ++ printk("stv0367: not found\n"); ++ kfree(state); ++ return NULL; ++} ++ ++ ++MODULE_DESCRIPTION("STV0367DD driver"); ++MODULE_AUTHOR("Ralph Metzler, Manfred Voelkel"); ++MODULE_LICENSE("GPL"); ++ ++EXPORT_SYMBOL(stv0367_attach); ++ ++ ++ diff --git a/drivers/media/dvb-frontends/stv0367dd.h b/drivers/media/dvb-frontends/stv0367dd.h new file mode 100644 index 0000000..665d4c8 @@ -12075,3437 +12075,3437 @@ index 0000000..eec0f57 --- /dev/null +++ b/drivers/media/dvb-frontends/stv0367dd_regs.h @@ -0,0 +1,3431 @@ -+// @DVB-C/DVB-T STMicroelectronics STV0367 register defintions -+// Author Manfred Völkel, Februar 2011 -+// (c) 2010 DigitalDevices GmbH Germany. All rights reserved -+ -+// $Id: DD_STV0367Register.h 357 2011-04-27 02:39:13Z manfred $ -+ -+/* ======================================================================= -+ -- Registers Declaration -+ -- ------------------------- -+ -- Each register (R367_XXXXX) is defined by its address (2 bytes). -+ -- -+ -- Each field (F367_XXXXX)is defined as follow: -+ -- [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] -+ ======================================================================= */ -+ -+/* ID */ -+#define R367_ID 0xF000 -+#define F367_IDENTIFICATIONREG 0xF00000FF -+ -+/* I2CRPT */ -+#define R367_I2CRPT 0xF001 -+#define F367_I2CT_ON 0xF0010080 -+#define F367_ENARPT_LEVEL 0xF0010070 -+#define F367_SCLT_DELAY 0xF0010008 -+#define F367_SCLT_NOD 0xF0010004 -+#define F367_STOP_ENABLE 0xF0010002 -+#define F367_SDAT_NOD 0xF0010001 -+ -+/* TOPCTRL */ -+#define R367_TOPCTRL 0xF002 -+#define F367_STDBY 0xF0020080 -+#define F367_STDBY_FEC 0xF0020040 -+#define F367_STDBY_CORE 0xF0020020 -+#define F367_QAM_COFDM 0xF0020010 -+#define F367_TS_DIS 0xF0020008 -+#define F367_DIR_CLK_216 0xF0020004 -+#define F367_TUNER_BB 0xF0020002 -+#define F367_DVBT_H 0xF0020001 -+ -+/* IOCFG0 */ -+#define R367_IOCFG0 0xF003 -+#define F367_OP0_SD 0xF0030080 -+#define F367_OP0_VAL 0xF0030040 -+#define F367_OP0_OD 0xF0030020 -+#define F367_OP0_INV 0xF0030010 -+#define F367_OP0_DACVALUE_HI 0xF003000F -+ -+/* DAC0R */ -+#define R367_DAC0R 0xF004 -+#define F367_OP0_DACVALUE_LO 0xF00400FF -+ -+/* IOCFG1 */ -+#define R367_IOCFG1 0xF005 -+#define F367_IP0 0xF0050040 -+#define F367_OP1_OD 0xF0050020 -+#define F367_OP1_INV 0xF0050010 -+#define F367_OP1_DACVALUE_HI 0xF005000F -+ -+/* DAC1R */ -+#define R367_DAC1R 0xF006 -+#define F367_OP1_DACVALUE_LO 0xF00600FF -+ -+/* IOCFG2 */ -+#define R367_IOCFG2 0xF007 -+#define F367_OP2_LOCK_CONF 0xF00700E0 -+#define F367_OP2_OD 0xF0070010 -+#define F367_OP2_VAL 0xF0070008 -+#define F367_OP1_LOCK_CONF 0xF0070007 -+ -+/* SDFR */ -+#define R367_SDFR 0xF008 -+#define F367_OP0_FREQ 0xF00800F0 -+#define F367_OP1_FREQ 0xF008000F -+ -+/* STATUS */ -+#define R367_OFDM_STATUS 0xF009 -+#define F367_TPS_LOCK 0xF0090080 -+#define F367_SYR_LOCK 0xF0090040 -+#define F367_AGC_LOCK 0xF0090020 -+#define F367_PRF 0xF0090010 -+#define F367_LK 0xF0090008 -+#define F367_PR 0xF0090007 -+ -+/* AUX_CLK */ -+#define R367_AUX_CLK 0xF00A -+#define F367_AUXFEC_CTL 0xF00A00C0 -+#define F367_DIS_CKX4 0xF00A0020 -+#define F367_CKSEL 0xF00A0018 -+#define F367_CKDIV_PROG 0xF00A0006 -+#define F367_AUXCLK_ENA 0xF00A0001 -+ -+/* FREESYS1 */ -+#define R367_FREESYS1 0xF00B -+#define F367_FREE_SYS1 0xF00B00FF -+ -+/* FREESYS2 */ -+#define R367_FREESYS2 0xF00C -+#define F367_FREE_SYS2 0xF00C00FF -+ -+/* FREESYS3 */ -+#define R367_FREESYS3 0xF00D -+#define F367_FREE_SYS3 0xF00D00FF -+ -+/* GPIO_CFG */ -+#define R367_GPIO_CFG 0xF00E -+#define F367_GPIO7_NOD 0xF00E0080 -+#define F367_GPIO7_CFG 0xF00E0040 -+#define F367_GPIO6_NOD 0xF00E0020 -+#define F367_GPIO6_CFG 0xF00E0010 -+#define F367_GPIO5_NOD 0xF00E0008 -+#define F367_GPIO5_CFG 0xF00E0004 -+#define F367_GPIO4_NOD 0xF00E0002 -+#define F367_GPIO4_CFG 0xF00E0001 -+ -+/* GPIO_CMD */ -+#define R367_GPIO_CMD 0xF00F -+#define F367_GPIO7_VAL 0xF00F0008 -+#define F367_GPIO6_VAL 0xF00F0004 -+#define F367_GPIO5_VAL 0xF00F0002 -+#define F367_GPIO4_VAL 0xF00F0001 -+ -+/* AGC2MAX */ -+#define R367_OFDM_AGC2MAX 0xF010 -+#define F367_OFDM_AGC2_MAX 0xF01000FF -+ -+/* AGC2MIN */ -+#define R367_OFDM_AGC2MIN 0xF011 -+#define F367_OFDM_AGC2_MIN 0xF01100FF -+ -+/* AGC1MAX */ -+#define R367_OFDM_AGC1MAX 0xF012 -+#define F367_OFDM_AGC1_MAX 0xF01200FF -+ -+/* AGC1MIN */ -+#define R367_OFDM_AGC1MIN 0xF013 -+#define F367_OFDM_AGC1_MIN 0xF01300FF -+ -+/* AGCR */ -+#define R367_OFDM_AGCR 0xF014 -+#define F367_OFDM_RATIO_A 0xF01400E0 -+#define F367_OFDM_RATIO_B 0xF0140018 -+#define F367_OFDM_RATIO_C 0xF0140007 -+ -+/* AGC2TH */ -+#define R367_OFDM_AGC2TH 0xF015 -+#define F367_OFDM_AGC2_THRES 0xF01500FF -+ -+/* AGC12C */ -+#define R367_OFDM_AGC12C 0xF016 -+#define F367_OFDM_AGC1_IV 0xF0160080 -+#define F367_OFDM_AGC1_OD 0xF0160040 -+#define F367_OFDM_AGC1_LOAD 0xF0160020 -+#define F367_OFDM_AGC2_IV 0xF0160010 -+#define F367_OFDM_AGC2_OD 0xF0160008 -+#define F367_OFDM_AGC2_LOAD 0xF0160004 -+#define F367_OFDM_AGC12_MODE 0xF0160003 -+ -+/* AGCCTRL1 */ -+#define R367_OFDM_AGCCTRL1 0xF017 -+#define F367_OFDM_DAGC_ON 0xF0170080 -+#define F367_OFDM_INVERT_AGC12 0xF0170040 -+#define F367_OFDM_AGC1_MODE 0xF0170008 -+#define F367_OFDM_AGC2_MODE 0xF0170007 -+ -+/* AGCCTRL2 */ -+#define R367_OFDM_AGCCTRL2 0xF018 -+#define F367_OFDM_FRZ2_CTRL 0xF0180060 -+#define F367_OFDM_FRZ1_CTRL 0xF0180018 -+#define F367_OFDM_TIME_CST 0xF0180007 -+ -+/* AGC1VAL1 */ -+#define R367_OFDM_AGC1VAL1 0xF019 -+#define F367_OFDM_AGC1_VAL_LO 0xF01900FF -+ -+/* AGC1VAL2 */ -+#define R367_OFDM_AGC1VAL2 0xF01A -+#define F367_OFDM_AGC1_VAL_HI 0xF01A000F -+ -+/* AGC2VAL1 */ -+#define R367_OFDM_AGC2VAL1 0xF01B -+#define F367_OFDM_AGC2_VAL_LO 0xF01B00FF -+ -+/* AGC2VAL2 */ -+#define R367_OFDM_AGC2VAL2 0xF01C -+#define F367_OFDM_AGC2_VAL_HI 0xF01C000F -+ -+/* AGC2PGA */ -+#define R367_OFDM_AGC2PGA 0xF01D -+#define F367_OFDM_AGC2_PGA 0xF01D00FF -+ -+/* OVF_RATE1 */ -+#define R367_OFDM_OVF_RATE1 0xF01E -+#define F367_OFDM_OVF_RATE_HI 0xF01E000F -+ -+/* OVF_RATE2 */ -+#define R367_OFDM_OVF_RATE2 0xF01F -+#define F367_OFDM_OVF_RATE_LO 0xF01F00FF -+ -+/* GAIN_SRC1 */ -+#define R367_OFDM_GAIN_SRC1 0xF020 -+#define F367_OFDM_INV_SPECTR 0xF0200080 -+#define F367_OFDM_IQ_INVERT 0xF0200040 -+#define F367_OFDM_INR_BYPASS 0xF0200020 -+#define F367_OFDM_STATUS_INV_SPECRUM 0xF0200010 -+#define F367_OFDM_GAIN_SRC_HI 0xF020000F -+ -+/* GAIN_SRC2 */ -+#define R367_OFDM_GAIN_SRC2 0xF021 -+#define F367_OFDM_GAIN_SRC_LO 0xF02100FF -+ -+/* INC_DEROT1 */ -+#define R367_OFDM_INC_DEROT1 0xF022 -+#define F367_OFDM_INC_DEROT_HI 0xF02200FF -+ -+/* INC_DEROT2 */ -+#define R367_OFDM_INC_DEROT2 0xF023 -+#define F367_OFDM_INC_DEROT_LO 0xF02300FF -+ -+/* PPM_CPAMP_DIR */ -+#define R367_OFDM_PPM_CPAMP_DIR 0xF024 -+#define F367_OFDM_PPM_CPAMP_DIRECT 0xF02400FF -+ -+/* PPM_CPAMP_INV */ -+#define R367_OFDM_PPM_CPAMP_INV 0xF025 -+#define F367_OFDM_PPM_CPAMP_INVER 0xF02500FF -+ -+/* FREESTFE_1 */ -+#define R367_OFDM_FREESTFE_1 0xF026 -+#define F367_OFDM_SYMBOL_NUMBER_INC 0xF02600C0 -+#define F367_OFDM_SEL_LSB 0xF0260004 -+#define F367_OFDM_AVERAGE_ON 0xF0260002 -+#define F367_OFDM_DC_ADJ 0xF0260001 -+ -+/* FREESTFE_2 */ -+#define R367_OFDM_FREESTFE_2 0xF027 -+#define F367_OFDM_SEL_SRCOUT 0xF02700C0 -+#define F367_OFDM_SEL_SYRTHR 0xF027001F -+ -+/* DCOFFSET */ -+#define R367_OFDM_DCOFFSET 0xF028 -+#define F367_OFDM_SELECT_I_Q 0xF0280080 -+#define F367_OFDM_DC_OFFSET 0xF028007F -+ -+/* EN_PROCESS */ -+#define R367_OFDM_EN_PROCESS 0xF029 -+#define F367_OFDM_FREE 0xF02900F0 -+#define F367_OFDM_ENAB_MANUAL 0xF0290001 -+ -+/* SDI_SMOOTHER */ -+#define R367_OFDM_SDI_SMOOTHER 0xF02A -+#define F367_OFDM_DIS_SMOOTH 0xF02A0080 -+#define F367_OFDM_SDI_INC_SMOOTHER 0xF02A007F -+ -+/* FE_LOOP_OPEN */ -+#define R367_OFDM_FE_LOOP_OPEN 0xF02B -+#define F367_OFDM_TRL_LOOP_OP 0xF02B0002 -+#define F367_OFDM_CRL_LOOP_OP 0xF02B0001 -+ -+/* FREQOFF1 */ -+#define R367_OFDM_FREQOFF1 0xF02C -+#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_VHI 0xF02C00FF -+ -+/* FREQOFF2 */ -+#define R367_OFDM_FREQOFF2 0xF02D -+#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_HI 0xF02D00FF -+ -+/* FREQOFF3 */ -+#define R367_OFDM_FREQOFF3 0xF02E -+#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_LO 0xF02E00FF -+ -+/* TIMOFF1 */ -+#define R367_OFDM_TIMOFF1 0xF02F -+#define F367_OFDM_TIM_OFFSET_LOOP_OPEN_HI 0xF02F00FF -+ -+/* TIMOFF2 */ -+#define R367_OFDM_TIMOFF2 0xF030 -+#define F367_OFDM_TIM_OFFSET_LOOP_OPEN_LO 0xF03000FF -+ -+/* EPQ */ -+#define R367_OFDM_EPQ 0xF031 -+#define F367_OFDM_EPQ1 0xF03100FF -+ -+/* EPQAUTO */ -+#define R367_OFDM_EPQAUTO 0xF032 -+#define F367_OFDM_EPQ2 0xF03200FF -+ -+/* SYR_UPDATE */ -+#define R367_OFDM_SYR_UPDATE 0xF033 -+#define F367_OFDM_SYR_PROTV 0xF0330080 -+#define F367_OFDM_SYR_PROTV_GAIN 0xF0330060 -+#define F367_OFDM_SYR_FILTER 0xF0330010 -+#define F367_OFDM_SYR_TRACK_THRES 0xF033000C -+ -+/* CHPFREE */ -+#define R367_OFDM_CHPFREE 0xF034 -+#define F367_OFDM_CHP_FREE 0xF03400FF -+ -+/* PPM_STATE_MAC */ -+#define R367_OFDM_PPM_STATE_MAC 0xF035 -+#define F367_OFDM_PPM_STATE_MACHINE_DECODER 0xF035003F -+ -+/* INR_THRESHOLD */ -+#define R367_OFDM_INR_THRESHOLD 0xF036 -+#define F367_OFDM_INR_THRESH 0xF03600FF -+ -+/* EPQ_TPS_ID_CELL */ -+#define R367_OFDM_EPQ_TPS_ID_CELL 0xF037 -+#define F367_OFDM_ENABLE_LGTH_TO_CF 0xF0370080 -+#define F367_OFDM_DIS_TPS_RSVD 0xF0370040 -+#define F367_OFDM_DIS_BCH 0xF0370020 -+#define F367_OFDM_DIS_ID_CEL 0xF0370010 -+#define F367_OFDM_TPS_ADJUST_SYM 0xF037000F -+ -+/* EPQ_CFG */ -+#define R367_OFDM_EPQ_CFG 0xF038 -+#define F367_OFDM_EPQ_RANGE 0xF0380002 -+#define F367_OFDM_EPQ_SOFT 0xF0380001 -+ -+/* EPQ_STATUS */ -+#define R367_OFDM_EPQ_STATUS 0xF039 -+#define F367_OFDM_SLOPE_INC 0xF03900FC -+#define F367_OFDM_TPS_FIELD 0xF0390003 -+ -+/* AUTORELOCK */ -+#define R367_OFDM_AUTORELOCK 0xF03A -+#define F367_OFDM_BYPASS_BER_TEMPO 0xF03A0080 -+#define F367_OFDM_BER_TEMPO 0xF03A0070 -+#define F367_OFDM_BYPASS_COFDM_TEMPO 0xF03A0008 -+#define F367_OFDM_COFDM_TEMPO 0xF03A0007 -+ -+/* BER_THR_VMSB */ -+#define R367_OFDM_BER_THR_VMSB 0xF03B -+#define F367_OFDM_BER_THRESHOLD_HI 0xF03B00FF -+ -+/* BER_THR_MSB */ -+#define R367_OFDM_BER_THR_MSB 0xF03C -+#define F367_OFDM_BER_THRESHOLD_MID 0xF03C00FF -+ -+/* BER_THR_LSB */ -+#define R367_OFDM_BER_THR_LSB 0xF03D -+#define F367_OFDM_BER_THRESHOLD_LO 0xF03D00FF -+ -+/* CCD */ -+#define R367_OFDM_CCD 0xF03E -+#define F367_OFDM_CCD_DETECTED 0xF03E0080 -+#define F367_OFDM_CCD_RESET 0xF03E0040 -+#define F367_OFDM_CCD_THRESHOLD 0xF03E000F -+ -+/* SPECTR_CFG */ -+#define R367_OFDM_SPECTR_CFG 0xF03F -+#define F367_OFDM_SPECT_CFG 0xF03F0003 -+ -+/* CONSTMU_MSB */ -+#define R367_OFDM_CONSTMU_MSB 0xF040 -+#define F367_OFDM_CONSTMU_FREEZE 0xF0400080 -+#define F367_OFDM_CONSTNU_FORCE_EN 0xF0400040 -+#define F367_OFDM_CONST_MU_MSB 0xF040003F -+ -+/* CONSTMU_LSB */ -+#define R367_OFDM_CONSTMU_LSB 0xF041 -+#define F367_OFDM_CONST_MU_LSB 0xF04100FF -+ -+/* CONSTMU_MAX_MSB */ -+#define R367_OFDM_CONSTMU_MAX_MSB 0xF042 -+#define F367_OFDM_CONST_MU_MAX_MSB 0xF042003F -+ -+/* CONSTMU_MAX_LSB */ -+#define R367_OFDM_CONSTMU_MAX_LSB 0xF043 -+#define F367_OFDM_CONST_MU_MAX_LSB 0xF04300FF -+ -+/* ALPHANOISE */ -+#define R367_OFDM_ALPHANOISE 0xF044 -+#define F367_OFDM_USE_ALLFILTER 0xF0440080 -+#define F367_OFDM_INTER_ON 0xF0440040 -+#define F367_OFDM_ALPHA_NOISE 0xF044001F -+ -+/* MAXGP_MSB */ -+#define R367_OFDM_MAXGP_MSB 0xF045 -+#define F367_OFDM_MUFILTER_LENGTH 0xF04500F0 -+#define F367_OFDM_MAX_GP_MSB 0xF045000F -+ -+/* MAXGP_LSB */ -+#define R367_OFDM_MAXGP_LSB 0xF046 -+#define F367_OFDM_MAX_GP_LSB 0xF04600FF -+ -+/* ALPHAMSB */ -+#define R367_OFDM_ALPHAMSB 0xF047 -+#define F367_OFDM_CHC_DATARATE 0xF04700C0 -+#define F367_OFDM_ALPHA_MSB 0xF047003F -+ -+/* ALPHALSB */ -+#define R367_OFDM_ALPHALSB 0xF048 -+#define F367_OFDM_ALPHA_LSB 0xF04800FF -+ -+/* PILOT_ACCU */ -+#define R367_OFDM_PILOT_ACCU 0xF049 -+#define F367_OFDM_USE_SCAT4ADDAPT 0xF0490080 -+#define F367_OFDM_PILOT_ACC 0xF049001F -+ -+/* PILOTMU_ACCU */ -+#define R367_OFDM_PILOTMU_ACCU 0xF04A -+#define F367_OFDM_DISCARD_BAD_SP 0xF04A0080 -+#define F367_OFDM_DISCARD_BAD_CP 0xF04A0040 -+#define F367_OFDM_PILOT_MU_ACCU 0xF04A001F -+ -+/* FILT_CHANNEL_EST */ -+#define R367_OFDM_FILT_CHANNEL_EST 0xF04B -+#define F367_OFDM_USE_FILT_PILOT 0xF04B0080 -+#define F367_OFDM_FILT_CHANNEL 0xF04B007F -+ -+/* ALPHA_NOPISE_FREQ */ -+#define R367_OFDM_ALPHA_NOPISE_FREQ 0xF04C -+#define F367_OFDM_NOISE_FREQ_FILT 0xF04C0040 -+#define F367_OFDM_ALPHA_NOISE_FREQ 0xF04C003F -+ -+/* RATIO_PILOT */ -+#define R367_OFDM_RATIO_PILOT 0xF04D -+#define F367_OFDM_RATIO_MEAN_SP 0xF04D00F0 -+#define F367_OFDM_RATIO_MEAN_CP 0xF04D000F -+ -+/* CHC_CTL */ -+#define R367_OFDM_CHC_CTL 0xF04E -+#define F367_OFDM_TRACK_EN 0xF04E0080 -+#define F367_OFDM_NOISE_NORM_EN 0xF04E0040 -+#define F367_OFDM_FORCE_CHC_RESET 0xF04E0020 -+#define F367_OFDM_SHORT_TIME 0xF04E0010 -+#define F367_OFDM_FORCE_STATE_EN 0xF04E0008 -+#define F367_OFDM_FORCE_STATE 0xF04E0007 -+ -+/* EPQ_ADJUST */ -+#define R367_OFDM_EPQ_ADJUST 0xF04F -+#define F367_OFDM_ADJUST_SCAT_IND 0xF04F00C0 -+#define F367_OFDM_ONE_SYMBOL 0xF04F0010 -+#define F367_OFDM_EPQ_DECAY 0xF04F000E -+#define F367_OFDM_HOLD_SLOPE 0xF04F0001 -+ -+/* EPQ_THRES */ -+#define R367_OFDM_EPQ_THRES 0xF050 -+#define F367_OFDM_EPQ_THR 0xF05000FF -+ -+/* OMEGA_CTL */ -+#define R367_OFDM_OMEGA_CTL 0xF051 -+#define F367_OFDM_OMEGA_RST 0xF0510080 -+#define F367_OFDM_FREEZE_OMEGA 0xF0510040 -+#define F367_OFDM_OMEGA_SEL 0xF051003F -+ -+/* GP_CTL */ -+#define R367_OFDM_GP_CTL 0xF052 -+#define F367_OFDM_CHC_STATE 0xF05200E0 -+#define F367_OFDM_FREEZE_GP 0xF0520010 -+#define F367_OFDM_GP_SEL 0xF052000F -+ -+/* MUMSB */ -+#define R367_OFDM_MUMSB 0xF053 -+#define F367_OFDM_MU_MSB 0xF053007F -+ -+/* MULSB */ -+#define R367_OFDM_MULSB 0xF054 -+#define F367_OFDM_MU_LSB 0xF05400FF -+ -+/* GPMSB */ -+#define R367_OFDM_GPMSB 0xF055 -+#define F367_OFDM_CSI_THRESHOLD 0xF05500E0 -+#define F367_OFDM_GP_MSB 0xF055000F -+ -+/* GPLSB */ -+#define R367_OFDM_GPLSB 0xF056 -+#define F367_OFDM_GP_LSB 0xF05600FF -+ -+/* OMEGAMSB */ -+#define R367_OFDM_OMEGAMSB 0xF057 -+#define F367_OFDM_OMEGA_MSB 0xF057007F -+ -+/* OMEGALSB */ -+#define R367_OFDM_OMEGALSB 0xF058 -+#define F367_OFDM_OMEGA_LSB 0xF05800FF -+ -+/* SCAT_NB */ -+#define R367_OFDM_SCAT_NB 0xF059 -+#define F367_OFDM_CHC_TEST 0xF05900F8 -+#define F367_OFDM_SCAT_NUMB 0xF0590003 -+ -+/* CHC_DUMMY */ -+#define R367_OFDM_CHC_DUMMY 0xF05A -+#define F367_OFDM_CHC_DUM 0xF05A00FF -+ -+/* INC_CTL */ -+#define R367_OFDM_INC_CTL 0xF05B -+#define F367_OFDM_INC_BYPASS 0xF05B0080 -+#define F367_OFDM_INC_NDEPTH 0xF05B000C -+#define F367_OFDM_INC_MADEPTH 0xF05B0003 -+ -+/* INCTHRES_COR1 */ -+#define R367_OFDM_INCTHRES_COR1 0xF05C -+#define F367_OFDM_INC_THRES_COR1 0xF05C00FF -+ -+/* INCTHRES_COR2 */ -+#define R367_OFDM_INCTHRES_COR2 0xF05D -+#define F367_OFDM_INC_THRES_COR2 0xF05D00FF -+ -+/* INCTHRES_DET1 */ -+#define R367_OFDM_INCTHRES_DET1 0xF05E -+#define F367_OFDM_INC_THRES_DET1 0xF05E003F -+ -+/* INCTHRES_DET2 */ -+#define R367_OFDM_INCTHRES_DET2 0xF05F -+#define F367_OFDM_INC_THRES_DET2 0xF05F003F -+ -+/* IIR_CELLNB */ -+#define R367_OFDM_IIR_CELLNB 0xF060 -+#define F367_OFDM_NRST_IIR 0xF0600080 -+#define F367_OFDM_IIR_CELL_NB 0xF0600007 -+ -+/* IIRCX_COEFF1_MSB */ -+#define R367_OFDM_IIRCX_COEFF1_MSB 0xF061 -+#define F367_OFDM_IIR_CX_COEFF1_MSB 0xF06100FF -+ -+/* IIRCX_COEFF1_LSB */ -+#define R367_OFDM_IIRCX_COEFF1_LSB 0xF062 -+#define F367_OFDM_IIR_CX_COEFF1_LSB 0xF06200FF -+ -+/* IIRCX_COEFF2_MSB */ -+#define R367_OFDM_IIRCX_COEFF2_MSB 0xF063 -+#define F367_OFDM_IIR_CX_COEFF2_MSB 0xF06300FF -+ -+/* IIRCX_COEFF2_LSB */ -+#define R367_OFDM_IIRCX_COEFF2_LSB 0xF064 -+#define F367_OFDM_IIR_CX_COEFF2_LSB 0xF06400FF -+ -+/* IIRCX_COEFF3_MSB */ -+#define R367_OFDM_IIRCX_COEFF3_MSB 0xF065 -+#define F367_OFDM_IIR_CX_COEFF3_MSB 0xF06500FF -+ -+/* IIRCX_COEFF3_LSB */ -+#define R367_OFDM_IIRCX_COEFF3_LSB 0xF066 -+#define F367_OFDM_IIR_CX_COEFF3_LSB 0xF06600FF -+ -+/* IIRCX_COEFF4_MSB */ -+#define R367_OFDM_IIRCX_COEFF4_MSB 0xF067 -+#define F367_OFDM_IIR_CX_COEFF4_MSB 0xF06700FF -+ -+/* IIRCX_COEFF4_LSB */ -+#define R367_OFDM_IIRCX_COEFF4_LSB 0xF068 -+#define F367_OFDM_IIR_CX_COEFF4_LSB 0xF06800FF -+ -+/* IIRCX_COEFF5_MSB */ -+#define R367_OFDM_IIRCX_COEFF5_MSB 0xF069 -+#define F367_OFDM_IIR_CX_COEFF5_MSB 0xF06900FF -+ -+/* IIRCX_COEFF5_LSB */ -+#define R367_OFDM_IIRCX_COEFF5_LSB 0xF06A -+#define F367_OFDM_IIR_CX_COEFF5_LSB 0xF06A00FF -+ -+/* FEPATH_CFG */ -+#define R367_OFDM_FEPATH_CFG 0xF06B -+#define F367_OFDM_DEMUX_SWAP 0xF06B0004 -+#define F367_OFDM_DIGAGC_SWAP 0xF06B0002 -+#define F367_OFDM_LONGPATH_IF 0xF06B0001 -+ -+/* PMC1_FUNC */ -+#define R367_OFDM_PMC1_FUNC 0xF06C -+#define F367_OFDM_SOFT_RSTN 0xF06C0080 -+#define F367_OFDM_PMC1_AVERAGE_TIME 0xF06C0078 -+#define F367_OFDM_PMC1_WAIT_TIME 0xF06C0006 -+#define F367_OFDM_PMC1_2N_SEL 0xF06C0001 -+ -+/* PMC1_FOR */ -+#define R367_OFDM_PMC1_FOR 0xF06D -+#define F367_OFDM_PMC1_FORCE 0xF06D0080 -+#define F367_OFDM_PMC1_FORCE_VALUE 0xF06D007C -+ -+/* PMC2_FUNC */ -+#define R367_OFDM_PMC2_FUNC 0xF06E -+#define F367_OFDM_PMC2_SOFT_STN 0xF06E0080 -+#define F367_OFDM_PMC2_ACCU_TIME 0xF06E0070 -+#define F367_OFDM_PMC2_CMDP_MN 0xF06E0008 -+#define F367_OFDM_PMC2_SWAP 0xF06E0004 -+ -+/* STATUS_ERR_DA */ -+#define R367_OFDM_STATUS_ERR_DA 0xF06F -+#define F367_OFDM_COM_USEGAINTRK 0xF06F0080 -+#define F367_OFDM_COM_AGCLOCK 0xF06F0040 -+#define F367_OFDM_AUT_AGCLOCK 0xF06F0020 -+#define F367_OFDM_MIN_ERR_X_LSB 0xF06F000F -+ -+/* DIG_AGC_R */ -+#define R367_OFDM_DIG_AGC_R 0xF070 -+#define F367_OFDM_COM_SOFT_RSTN 0xF0700080 -+#define F367_OFDM_COM_AGC_ON 0xF0700040 -+#define F367_OFDM_COM_EARLY 0xF0700020 -+#define F367_OFDM_AUT_SOFT_RESETN 0xF0700010 -+#define F367_OFDM_AUT_AGC_ON 0xF0700008 -+#define F367_OFDM_AUT_EARLY 0xF0700004 -+#define F367_OFDM_AUT_ROT_EN 0xF0700002 -+#define F367_OFDM_LOCK_SOFT_RESETN 0xF0700001 -+ -+/* COMAGC_TARMSB */ -+#define R367_OFDM_COMAGC_TARMSB 0xF071 -+#define F367_OFDM_COM_AGC_TARGET_MSB 0xF07100FF -+ -+/* COM_AGC_TAR_ENMODE */ -+#define R367_OFDM_COM_AGC_TAR_ENMODE 0xF072 -+#define F367_OFDM_COM_AGC_TARGET_LSB 0xF07200F0 -+#define F367_OFDM_COM_ENMODE 0xF072000F -+ -+/* COM_AGC_CFG */ -+#define R367_OFDM_COM_AGC_CFG 0xF073 -+#define F367_OFDM_COM_N 0xF07300F8 -+#define F367_OFDM_COM_STABMODE 0xF0730006 -+#define F367_OFDM_ERR_SEL 0xF0730001 -+ -+/* COM_AGC_GAIN1 */ -+#define R367_OFDM_COM_AGC_GAIN1 0xF074 -+#define F367_OFDM_COM_GAIN1ACK 0xF07400F0 -+#define F367_OFDM_COM_GAIN1TRK 0xF074000F -+ -+/* AUT_AGC_TARGETMSB */ -+#define R367_OFDM_AUT_AGC_TARGETMSB 0xF075 -+#define F367_OFDM_AUT_AGC_TARGET_MSB 0xF07500FF -+ -+/* LOCK_DET_MSB */ -+#define R367_OFDM_LOCK_DET_MSB 0xF076 -+#define F367_OFDM_LOCK_DETECT_MSB 0xF07600FF -+ -+/* AGCTAR_LOCK_LSBS */ -+#define R367_OFDM_AGCTAR_LOCK_LSBS 0xF077 -+#define F367_OFDM_AUT_AGC_TARGET_LSB 0xF07700F0 -+#define F367_OFDM_LOCK_DETECT_LSB 0xF077000F -+ -+/* AUT_GAIN_EN */ -+#define R367_OFDM_AUT_GAIN_EN 0xF078 -+#define F367_OFDM_AUT_ENMODE 0xF07800F0 -+#define F367_OFDM_AUT_GAIN2 0xF078000F -+ -+/* AUT_CFG */ -+#define R367_OFDM_AUT_CFG 0xF079 -+#define F367_OFDM_AUT_N 0xF07900F8 -+#define F367_OFDM_INT_CHOICE 0xF0790006 -+#define F367_OFDM_INT_LOAD 0xF0790001 -+ -+/* LOCKN */ -+#define R367_OFDM_LOCKN 0xF07A -+#define F367_OFDM_LOCK_N 0xF07A00F8 -+#define F367_OFDM_SEL_IQNTAR 0xF07A0004 -+#define F367_OFDM_LOCK_DETECT_CHOICE 0xF07A0003 -+ -+/* INT_X_3 */ -+#define R367_OFDM_INT_X_3 0xF07B -+#define F367_OFDM_INT_X3 0xF07B00FF -+ -+/* INT_X_2 */ -+#define R367_OFDM_INT_X_2 0xF07C -+#define F367_OFDM_INT_X2 0xF07C00FF -+ -+/* INT_X_1 */ -+#define R367_OFDM_INT_X_1 0xF07D -+#define F367_OFDM_INT_X1 0xF07D00FF -+ -+/* INT_X_0 */ -+#define R367_OFDM_INT_X_0 0xF07E -+#define F367_OFDM_INT_X0 0xF07E00FF -+ -+/* MIN_ERRX_MSB */ -+#define R367_OFDM_MIN_ERRX_MSB 0xF07F -+#define F367_OFDM_MIN_ERR_X_MSB 0xF07F00FF -+ -+/* COR_CTL */ -+#define R367_OFDM_COR_CTL 0xF080 -+#define F367_OFDM_CORE_ACTIVE 0xF0800020 -+#define F367_OFDM_HOLD 0xF0800010 -+#define F367_OFDM_CORE_STATE_CTL 0xF080000F -+ -+/* COR_STAT */ -+#define R367_OFDM_COR_STAT 0xF081 -+#define F367_OFDM_SCATT_LOCKED 0xF0810080 -+#define F367_OFDM_TPS_LOCKED 0xF0810040 -+#define F367_OFDM_SYR_LOCKED_COR 0xF0810020 -+#define F367_OFDM_AGC_LOCKED_STAT 0xF0810010 -+#define F367_OFDM_CORE_STATE_STAT 0xF081000F -+ -+/* COR_INTEN */ -+#define R367_OFDM_COR_INTEN 0xF082 -+#define F367_OFDM_INTEN 0xF0820080 -+#define F367_OFDM_INTEN_SYR 0xF0820020 -+#define F367_OFDM_INTEN_FFT 0xF0820010 -+#define F367_OFDM_INTEN_AGC 0xF0820008 -+#define F367_OFDM_INTEN_TPS1 0xF0820004 -+#define F367_OFDM_INTEN_TPS2 0xF0820002 -+#define F367_OFDM_INTEN_TPS3 0xF0820001 -+ -+/* COR_INTSTAT */ -+#define R367_OFDM_COR_INTSTAT 0xF083 -+#define F367_OFDM_INTSTAT_SYR 0xF0830020 -+#define F367_OFDM_INTSTAT_FFT 0xF0830010 -+#define F367_OFDM_INTSAT_AGC 0xF0830008 -+#define F367_OFDM_INTSTAT_TPS1 0xF0830004 -+#define F367_OFDM_INTSTAT_TPS2 0xF0830002 -+#define F367_OFDM_INTSTAT_TPS3 0xF0830001 -+ -+/* COR_MODEGUARD */ -+#define R367_OFDM_COR_MODEGUARD 0xF084 -+#define F367_OFDM_FORCE 0xF0840010 -+#define F367_OFDM_MODE 0xF084000C -+#define F367_OFDM_GUARD 0xF0840003 -+ -+/* AGC_CTL */ -+#define R367_OFDM_AGC_CTL 0xF085 -+#define F367_OFDM_AGC_TIMING_FACTOR 0xF08500E0 -+#define F367_OFDM_AGC_LAST 0xF0850010 -+#define F367_OFDM_AGC_GAIN 0xF085000C -+#define F367_OFDM_AGC_NEG 0xF0850002 -+#define F367_OFDM_AGC_SET 0xF0850001 -+ -+/* AGC_MANUAL1 */ -+#define R367_OFDM_AGC_MANUAL1 0xF086 -+#define F367_OFDM_AGC_VAL_LO 0xF08600FF -+ -+/* AGC_MANUAL2 */ -+#define R367_OFDM_AGC_MANUAL2 0xF087 -+#define F367_OFDM_AGC_VAL_HI 0xF087000F -+ -+/* AGC_TARG */ -+#define R367_OFDM_AGC_TARG 0xF088 -+#define F367_OFDM_AGC_TARGET 0xF08800FF -+ -+/* AGC_GAIN1 */ -+#define R367_OFDM_AGC_GAIN1 0xF089 -+#define F367_OFDM_AGC_GAIN_LO 0xF08900FF -+ -+/* AGC_GAIN2 */ -+#define R367_OFDM_AGC_GAIN2 0xF08A -+#define F367_OFDM_AGC_LOCKED_GAIN2 0xF08A0010 -+#define F367_OFDM_AGC_GAIN_HI 0xF08A000F -+ -+/* RESERVED_1 */ -+#define R367_OFDM_RESERVED_1 0xF08B -+#define F367_OFDM_RESERVED1 0xF08B00FF -+ -+/* RESERVED_2 */ -+#define R367_OFDM_RESERVED_2 0xF08C -+#define F367_OFDM_RESERVED2 0xF08C00FF -+ -+/* RESERVED_3 */ -+#define R367_OFDM_RESERVED_3 0xF08D -+#define F367_OFDM_RESERVED3 0xF08D00FF -+ -+/* CAS_CTL */ -+#define R367_OFDM_CAS_CTL 0xF08E -+#define F367_OFDM_CCS_ENABLE 0xF08E0080 -+#define F367_OFDM_ACS_DISABLE 0xF08E0040 -+#define F367_OFDM_DAGC_DIS 0xF08E0020 -+#define F367_OFDM_DAGC_GAIN 0xF08E0018 -+#define F367_OFDM_CCSMU 0xF08E0007 -+ -+/* CAS_FREQ */ -+#define R367_OFDM_CAS_FREQ 0xF08F -+#define F367_OFDM_CCS_FREQ 0xF08F00FF -+ -+/* CAS_DAGCGAIN */ -+#define R367_OFDM_CAS_DAGCGAIN 0xF090 -+#define F367_OFDM_CAS_DAGC_GAIN 0xF09000FF -+ -+/* SYR_CTL */ -+#define R367_OFDM_SYR_CTL 0xF091 -+#define F367_OFDM_SICTH_ENABLE 0xF0910080 -+#define F367_OFDM_LONG_ECHO 0xF0910078 -+#define F367_OFDM_AUTO_LE_EN 0xF0910004 -+#define F367_OFDM_SYR_BYPASS 0xF0910002 -+#define F367_OFDM_SYR_TR_DIS 0xF0910001 -+ -+/* SYR_STAT */ -+#define R367_OFDM_SYR_STAT 0xF092 -+#define F367_OFDM_SYR_LOCKED_STAT 0xF0920010 -+#define F367_OFDM_SYR_MODE 0xF092000C -+#define F367_OFDM_SYR_GUARD 0xF0920003 -+ -+/* SYR_NCO1 */ -+#define R367_OFDM_SYR_NCO1 0xF093 -+#define F367_OFDM_SYR_NCO_LO 0xF09300FF -+ -+/* SYR_NCO2 */ -+#define R367_OFDM_SYR_NCO2 0xF094 -+#define F367_OFDM_SYR_NCO_HI 0xF094003F -+ -+/* SYR_OFFSET1 */ -+#define R367_OFDM_SYR_OFFSET1 0xF095 -+#define F367_OFDM_SYR_OFFSET_LO 0xF09500FF -+ -+/* SYR_OFFSET2 */ -+#define R367_OFDM_SYR_OFFSET2 0xF096 -+#define F367_OFDM_SYR_OFFSET_HI 0xF096003F -+ -+/* FFT_CTL */ -+#define R367_OFDM_FFT_CTL 0xF097 -+#define F367_OFDM_SHIFT_FFT_TRIG 0xF0970018 -+#define F367_OFDM_FFT_TRIGGER 0xF0970004 -+#define F367_OFDM_FFT_MANUAL 0xF0970002 -+#define F367_OFDM_IFFT_MODE 0xF0970001 -+ -+/* SCR_CTL */ -+#define R367_OFDM_SCR_CTL 0xF098 -+#define F367_OFDM_SYRADJDECAY 0xF0980070 -+#define F367_OFDM_SCR_CPEDIS 0xF0980002 -+#define F367_OFDM_SCR_DIS 0xF0980001 -+ -+/* PPM_CTL1 */ -+#define R367_OFDM_PPM_CTL1 0xF099 -+#define F367_OFDM_PPM_MAXFREQ 0xF0990030 -+#define F367_OFDM_PPM_MAXTIM 0xF0990008 -+#define F367_OFDM_PPM_INVSEL 0xF0990004 -+#define F367_OFDM_PPM_SCATDIS 0xF0990002 -+#define F367_OFDM_PPM_BYP 0xF0990001 -+ -+/* TRL_CTL */ -+#define R367_OFDM_TRL_CTL 0xF09A -+#define F367_OFDM_TRL_NOMRATE_LSB 0xF09A0080 -+#define F367_OFDM_TRL_GAIN_FACTOR 0xF09A0078 -+#define F367_OFDM_TRL_LOOPGAIN 0xF09A0007 -+ -+/* TRL_NOMRATE1 */ -+#define R367_OFDM_TRL_NOMRATE1 0xF09B -+#define F367_OFDM_TRL_NOMRATE_LO 0xF09B00FF -+ -+/* TRL_NOMRATE2 */ -+#define R367_OFDM_TRL_NOMRATE2 0xF09C -+#define F367_OFDM_TRL_NOMRATE_HI 0xF09C00FF -+ -+/* TRL_TIME1 */ -+#define R367_OFDM_TRL_TIME1 0xF09D -+#define F367_OFDM_TRL_TOFFSET_LO 0xF09D00FF -+ -+/* TRL_TIME2 */ -+#define R367_OFDM_TRL_TIME2 0xF09E -+#define F367_OFDM_TRL_TOFFSET_HI 0xF09E00FF -+ -+/* CRL_CTL */ -+#define R367_OFDM_CRL_CTL 0xF09F -+#define F367_OFDM_CRL_DIS 0xF09F0080 -+#define F367_OFDM_CRL_GAIN_FACTOR 0xF09F0078 -+#define F367_OFDM_CRL_LOOPGAIN 0xF09F0007 -+ -+/* CRL_FREQ1 */ -+#define R367_OFDM_CRL_FREQ1 0xF0A0 -+#define F367_OFDM_CRL_FOFFSET_LO 0xF0A000FF -+ -+/* CRL_FREQ2 */ -+#define R367_OFDM_CRL_FREQ2 0xF0A1 -+#define F367_OFDM_CRL_FOFFSET_HI 0xF0A100FF -+ -+/* CRL_FREQ3 */ -+#define R367_OFDM_CRL_FREQ3 0xF0A2 -+#define F367_OFDM_CRL_FOFFSET_VHI 0xF0A200FF -+ -+/* TPS_SFRAME_CTL */ -+#define R367_OFDM_TPS_SFRAME_CTL 0xF0A3 -+#define F367_OFDM_TPS_SFRAME_SYNC 0xF0A30001 -+ -+/* CHC_SNR */ -+#define R367_OFDM_CHC_SNR 0xF0A4 -+#define F367_OFDM_CHCSNR 0xF0A400FF -+ -+/* BDI_CTL */ -+#define R367_OFDM_BDI_CTL 0xF0A5 -+#define F367_OFDM_BDI_LPSEL 0xF0A50002 -+#define F367_OFDM_BDI_SERIAL 0xF0A50001 -+ -+/* DMP_CTL */ -+#define R367_OFDM_DMP_CTL 0xF0A6 -+#define F367_OFDM_DMP_SCALING_FACTOR 0xF0A6001E -+#define F367_OFDM_DMP_SDDIS 0xF0A60001 -+ -+/* TPS_RCVD1 */ -+#define R367_OFDM_TPS_RCVD1 0xF0A7 -+#define F367_OFDM_TPS_CHANGE 0xF0A70040 -+#define F367_OFDM_BCH_OK 0xF0A70020 -+#define F367_OFDM_TPS_SYNC 0xF0A70010 -+#define F367_OFDM_TPS_FRAME 0xF0A70003 -+ -+/* TPS_RCVD2 */ -+#define R367_OFDM_TPS_RCVD2 0xF0A8 -+#define F367_OFDM_TPS_HIERMODE 0xF0A80070 -+#define F367_OFDM_TPS_CONST 0xF0A80003 -+ -+/* TPS_RCVD3 */ -+#define R367_OFDM_TPS_RCVD3 0xF0A9 -+#define F367_OFDM_TPS_LPCODE 0xF0A90070 -+#define F367_OFDM_TPS_HPCODE 0xF0A90007 -+ -+/* TPS_RCVD4 */ -+#define R367_OFDM_TPS_RCVD4 0xF0AA -+#define F367_OFDM_TPS_GUARD 0xF0AA0030 -+#define F367_OFDM_TPS_MODE 0xF0AA0003 -+ -+/* TPS_ID_CELL1 */ -+#define R367_OFDM_TPS_ID_CELL1 0xF0AB -+#define F367_OFDM_TPS_ID_CELL_LO 0xF0AB00FF -+ -+/* TPS_ID_CELL2 */ -+#define R367_OFDM_TPS_ID_CELL2 0xF0AC -+#define F367_OFDM_TPS_ID_CELL_HI 0xF0AC00FF -+ -+/* TPS_RCVD5_SET1 */ -+#define R367_OFDM_TPS_RCVD5_SET1 0xF0AD -+#define F367_OFDM_TPS_NA 0xF0AD00FC -+#define F367_OFDM_TPS_SETFRAME 0xF0AD0003 -+ -+/* TPS_SET2 */ -+#define R367_OFDM_TPS_SET2 0xF0AE -+#define F367_OFDM_TPS_SETHIERMODE 0xF0AE0070 -+#define F367_OFDM_TPS_SETCONST 0xF0AE0003 -+ -+/* TPS_SET3 */ -+#define R367_OFDM_TPS_SET3 0xF0AF -+#define F367_OFDM_TPS_SETLPCODE 0xF0AF0070 -+#define F367_OFDM_TPS_SETHPCODE 0xF0AF0007 -+ -+/* TPS_CTL */ -+#define R367_OFDM_TPS_CTL 0xF0B0 -+#define F367_OFDM_TPS_IMM 0xF0B00004 -+#define F367_OFDM_TPS_BCHDIS 0xF0B00002 -+#define F367_OFDM_TPS_UPDDIS 0xF0B00001 -+ -+/* CTL_FFTOSNUM */ -+#define R367_OFDM_CTL_FFTOSNUM 0xF0B1 -+#define F367_OFDM_SYMBOL_NUMBER 0xF0B1007F -+ -+/* TESTSELECT */ -+#define R367_OFDM_TESTSELECT 0xF0B2 -+#define F367_OFDM_TEST_SELECT 0xF0B2001F -+ -+/* MSC_REV */ -+#define R367_OFDM_MSC_REV 0xF0B3 -+#define F367_OFDM_REV_NUMBER 0xF0B300FF -+ -+/* PIR_CTL */ -+#define R367_OFDM_PIR_CTL 0xF0B4 -+#define F367_OFDM_FREEZE 0xF0B40001 -+ -+/* SNR_CARRIER1 */ -+#define R367_OFDM_SNR_CARRIER1 0xF0B5 -+#define F367_OFDM_SNR_CARRIER_LO 0xF0B500FF -+ -+/* SNR_CARRIER2 */ -+#define R367_OFDM_SNR_CARRIER2 0xF0B6 -+#define F367_OFDM_MEAN 0xF0B600C0 -+#define F367_OFDM_SNR_CARRIER_HI 0xF0B6001F -+ -+/* PPM_CPAMP */ -+#define R367_OFDM_PPM_CPAMP 0xF0B7 -+#define F367_OFDM_PPM_CPC 0xF0B700FF -+ -+/* TSM_AP0 */ -+#define R367_OFDM_TSM_AP0 0xF0B8 -+#define F367_OFDM_ADDRESS_BYTE_0 0xF0B800FF -+ -+/* TSM_AP1 */ -+#define R367_OFDM_TSM_AP1 0xF0B9 -+#define F367_OFDM_ADDRESS_BYTE_1 0xF0B900FF -+ -+/* TSM_AP2 */ -+#define R367_OFDM_TSM_AP2 0xF0BA -+#define F367_OFDM_DATA_BYTE_0 0xF0BA00FF -+ -+/* TSM_AP3 */ -+#define R367_OFDM_TSM_AP3 0xF0BB -+#define F367_OFDM_DATA_BYTE_1 0xF0BB00FF -+ -+/* TSM_AP4 */ -+#define R367_OFDM_TSM_AP4 0xF0BC -+#define F367_OFDM_DATA_BYTE_2 0xF0BC00FF -+ -+/* TSM_AP5 */ -+#define R367_OFDM_TSM_AP5 0xF0BD -+#define F367_OFDM_DATA_BYTE_3 0xF0BD00FF -+ -+/* TSM_AP6 */ -+#define R367_OFDM_TSM_AP6 0xF0BE -+#define F367_OFDM_TSM_AP_6 0xF0BE00FF -+ -+/* TSM_AP7 */ -+#define R367_OFDM_TSM_AP7 0xF0BF -+#define F367_OFDM_MEM_SELECT_BYTE 0xF0BF00FF -+ -+/* TSTRES */ -+#define R367_TSTRES 0xF0C0 -+#define F367_FRES_DISPLAY 0xF0C00080 -+#define F367_FRES_FIFO_AD 0xF0C00020 -+#define F367_FRESRS 0xF0C00010 -+#define F367_FRESACS 0xF0C00008 -+#define F367_FRESFEC 0xF0C00004 -+#define F367_FRES_PRIF 0xF0C00002 -+#define F367_FRESCORE 0xF0C00001 -+ -+/* ANACTRL */ -+#define R367_ANACTRL 0xF0C1 -+#define F367_BYPASS_XTAL 0xF0C10040 -+#define F367_BYPASS_PLLXN 0xF0C1000C -+#define F367_DIS_PAD_OSC 0xF0C10002 -+#define F367_STDBY_PLLXN 0xF0C10001 -+ -+/* TSTBUS */ -+#define R367_TSTBUS 0xF0C2 -+#define F367_TS_BYTE_CLK_INV 0xF0C20080 -+#define F367_CFG_IP 0xF0C20070 -+#define F367_CFG_TST 0xF0C2000F -+ -+/* TSTRATE */ -+#define R367_TSTRATE 0xF0C6 -+#define F367_FORCEPHA 0xF0C60080 -+#define F367_FNEWPHA 0xF0C60010 -+#define F367_FROT90 0xF0C60008 -+#define F367_FR 0xF0C60007 -+ -+/* CONSTMODE */ -+#define R367_OFDM_CONSTMODE 0xF0CB -+#define F367_OFDM_TST_PRIF 0xF0CB00E0 -+#define F367_OFDM_CAR_TYPE 0xF0CB0018 -+#define F367_OFDM_CONST_MODE 0xF0CB0003 -+ -+/* CONSTCARR1 */ -+#define R367_OFDM_CONSTCARR1 0xF0CC -+#define F367_OFDM_CONST_CARR_LO 0xF0CC00FF -+ -+/* CONSTCARR2 */ -+#define R367_OFDM_CONSTCARR2 0xF0CD -+#define F367_OFDM_CONST_CARR_HI 0xF0CD001F -+ -+/* ICONSTEL */ -+#define R367_OFDM_ICONSTEL 0xF0CE -+#define F367_OFDM_PICONSTEL 0xF0CE00FF -+ -+/* QCONSTEL */ -+#define R367_OFDM_QCONSTEL 0xF0CF -+#define F367_OFDM_PQCONSTEL 0xF0CF00FF -+ -+/* TSTBISTRES0 */ -+#define R367_OFDM_TSTBISTRES0 0xF0D0 -+#define F367_OFDM_BEND_PPM 0xF0D00080 -+#define F367_OFDM_BBAD_PPM 0xF0D00040 -+#define F367_OFDM_BEND_FFTW 0xF0D00020 -+#define F367_OFDM_BBAD_FFTW 0xF0D00010 -+#define F367_OFDM_BEND_FFT_BUF 0xF0D00008 -+#define F367_OFDM_BBAD_FFT_BUF 0xF0D00004 -+#define F367_OFDM_BEND_SYR 0xF0D00002 -+#define F367_OFDM_BBAD_SYR 0xF0D00001 -+ -+/* TSTBISTRES1 */ -+#define R367_OFDM_TSTBISTRES1 0xF0D1 -+#define F367_OFDM_BEND_CHC_CP 0xF0D10080 -+#define F367_OFDM_BBAD_CHC_CP 0xF0D10040 -+#define F367_OFDM_BEND_CHCI 0xF0D10020 -+#define F367_OFDM_BBAD_CHCI 0xF0D10010 -+#define F367_OFDM_BEND_BDI 0xF0D10008 -+#define F367_OFDM_BBAD_BDI 0xF0D10004 -+#define F367_OFDM_BEND_SDI 0xF0D10002 -+#define F367_OFDM_BBAD_SDI 0xF0D10001 -+ -+/* TSTBISTRES2 */ -+#define R367_OFDM_TSTBISTRES2 0xF0D2 -+#define F367_OFDM_BEND_CHC_INC 0xF0D20080 -+#define F367_OFDM_BBAD_CHC_INC 0xF0D20040 -+#define F367_OFDM_BEND_CHC_SPP 0xF0D20020 -+#define F367_OFDM_BBAD_CHC_SPP 0xF0D20010 -+#define F367_OFDM_BEND_CHC_CPP 0xF0D20008 -+#define F367_OFDM_BBAD_CHC_CPP 0xF0D20004 -+#define F367_OFDM_BEND_CHC_SP 0xF0D20002 -+#define F367_OFDM_BBAD_CHC_SP 0xF0D20001 -+ -+/* TSTBISTRES3 */ -+#define R367_OFDM_TSTBISTRES3 0xF0D3 -+#define F367_OFDM_BEND_QAM 0xF0D30080 -+#define F367_OFDM_BBAD_QAM 0xF0D30040 -+#define F367_OFDM_BEND_SFEC_VIT 0xF0D30020 -+#define F367_OFDM_BBAD_SFEC_VIT 0xF0D30010 -+#define F367_OFDM_BEND_SFEC_DLINE 0xF0D30008 -+#define F367_OFDM_BBAD_SFEC_DLINE 0xF0D30004 -+#define F367_OFDM_BEND_SFEC_HW 0xF0D30002 -+#define F367_OFDM_BBAD_SFEC_HW 0xF0D30001 -+ -+/* RF_AGC1 */ -+#define R367_RF_AGC1 0xF0D4 -+#define F367_RF_AGC1_LEVEL_HI 0xF0D400FF -+ -+/* RF_AGC2 */ -+#define R367_RF_AGC2 0xF0D5 -+#define F367_REF_ADGP 0xF0D50080 -+#define F367_STDBY_ADCGP 0xF0D50020 -+#define F367_CHANNEL_SEL 0xF0D5001C -+#define F367_RF_AGC1_LEVEL_LO 0xF0D50003 -+ -+/* ANADIGCTRL */ -+#define R367_ANADIGCTRL 0xF0D7 -+#define F367_SEL_CLKDEM 0xF0D70020 -+#define F367_EN_BUFFER_Q 0xF0D70010 -+#define F367_EN_BUFFER_I 0xF0D70008 -+#define F367_ADC_RIS_EGDE 0xF0D70004 -+#define F367_SGN_ADC 0xF0D70002 -+#define F367_SEL_AD12_SYNC 0xF0D70001 -+ -+/* PLLMDIV */ -+#define R367_PLLMDIV 0xF0D8 -+#define F367_PLL_MDIV 0xF0D800FF -+ -+/* PLLNDIV */ -+#define R367_PLLNDIV 0xF0D9 -+#define F367_PLL_NDIV 0xF0D900FF -+ -+/* PLLSETUP */ -+#define R367_PLLSETUP 0xF0DA -+#define F367_PLL_PDIV 0xF0DA0070 -+#define F367_PLL_KDIV 0xF0DA000F -+ -+/* DUAL_AD12 */ -+#define R367_DUAL_AD12 0xF0DB -+#define F367_FS20M 0xF0DB0020 -+#define F367_FS50M 0xF0DB0010 -+#define F367_INMODE0 0xF0DB0008 -+#define F367_POFFQ 0xF0DB0004 -+#define F367_POFFI 0xF0DB0002 -+#define F367_INMODE1 0xF0DB0001 -+ -+/* TSTBIST */ -+#define R367_TSTBIST 0xF0DC -+#define F367_TST_BYP_CLK 0xF0DC0080 -+#define F367_TST_GCLKENA_STD 0xF0DC0040 -+#define F367_TST_GCLKENA 0xF0DC0020 -+#define F367_TST_MEMBIST 0xF0DC001F -+ -+/* PAD_COMP_CTRL */ -+#define R367_PAD_COMP_CTRL 0xF0DD -+#define F367_COMPTQ 0xF0DD0010 -+#define F367_COMPEN 0xF0DD0008 -+#define F367_FREEZE2 0xF0DD0004 -+#define F367_SLEEP_INHBT 0xF0DD0002 -+#define F367_CHIP_SLEEP 0xF0DD0001 -+ -+/* PAD_COMP_WR */ -+#define R367_PAD_COMP_WR 0xF0DE -+#define F367_WR_ASRC 0xF0DE007F -+ -+/* PAD_COMP_RD */ -+#define R367_PAD_COMP_RD 0xF0DF -+#define F367_COMPOK 0xF0DF0080 -+#define F367_RD_ASRC 0xF0DF007F -+ -+/* SYR_TARGET_FFTADJT_MSB */ -+#define R367_OFDM_SYR_TARGET_FFTADJT_MSB 0xF100 -+#define F367_OFDM_SYR_START 0xF1000080 -+#define F367_OFDM_SYR_TARGET_FFTADJ_HI 0xF100000F -+ -+/* SYR_TARGET_FFTADJT_LSB */ -+#define R367_OFDM_SYR_TARGET_FFTADJT_LSB 0xF101 -+#define F367_OFDM_SYR_TARGET_FFTADJ_LO 0xF10100FF -+ -+/* SYR_TARGET_CHCADJT_MSB */ -+#define R367_OFDM_SYR_TARGET_CHCADJT_MSB 0xF102 -+#define F367_OFDM_SYR_TARGET_CHCADJ_HI 0xF102000F -+ -+/* SYR_TARGET_CHCADJT_LSB */ -+#define R367_OFDM_SYR_TARGET_CHCADJT_LSB 0xF103 -+#define F367_OFDM_SYR_TARGET_CHCADJ_LO 0xF10300FF -+ -+/* SYR_FLAG */ -+#define R367_OFDM_SYR_FLAG 0xF104 -+#define F367_OFDM_TRIG_FLG1 0xF1040080 -+#define F367_OFDM_TRIG_FLG0 0xF1040040 -+#define F367_OFDM_FFT_FLG1 0xF1040008 -+#define F367_OFDM_FFT_FLG0 0xF1040004 -+#define F367_OFDM_CHC_FLG1 0xF1040002 -+#define F367_OFDM_CHC_FLG0 0xF1040001 -+ -+/* CRL_TARGET1 */ -+#define R367_OFDM_CRL_TARGET1 0xF105 -+#define F367_OFDM_CRL_START 0xF1050080 -+#define F367_OFDM_CRL_TARGET_VHI 0xF105000F -+ -+/* CRL_TARGET2 */ -+#define R367_OFDM_CRL_TARGET2 0xF106 -+#define F367_OFDM_CRL_TARGET_HI 0xF10600FF -+ -+/* CRL_TARGET3 */ -+#define R367_OFDM_CRL_TARGET3 0xF107 -+#define F367_OFDM_CRL_TARGET_LO 0xF10700FF -+ -+/* CRL_TARGET4 */ -+#define R367_OFDM_CRL_TARGET4 0xF108 -+#define F367_OFDM_CRL_TARGET_VLO 0xF10800FF -+ -+/* CRL_FLAG */ -+#define R367_OFDM_CRL_FLAG 0xF109 -+#define F367_OFDM_CRL_FLAG1 0xF1090002 -+#define F367_OFDM_CRL_FLAG0 0xF1090001 -+ -+/* TRL_TARGET1 */ -+#define R367_OFDM_TRL_TARGET1 0xF10A -+#define F367_OFDM_TRL_TARGET_HI 0xF10A00FF -+ -+/* TRL_TARGET2 */ -+#define R367_OFDM_TRL_TARGET2 0xF10B -+#define F367_OFDM_TRL_TARGET_LO 0xF10B00FF -+ -+/* TRL_CHC */ -+#define R367_OFDM_TRL_CHC 0xF10C -+#define F367_OFDM_TRL_START 0xF10C0080 -+#define F367_OFDM_CHC_START 0xF10C0040 -+#define F367_OFDM_TRL_FLAG1 0xF10C0002 -+#define F367_OFDM_TRL_FLAG0 0xF10C0001 -+ -+/* CHC_SNR_TARG */ -+#define R367_OFDM_CHC_SNR_TARG 0xF10D -+#define F367_OFDM_CHC_SNR_TARGET 0xF10D00FF -+ -+/* TOP_TRACK */ -+#define R367_OFDM_TOP_TRACK 0xF10E -+#define F367_OFDM_TOP_START 0xF10E0080 -+#define F367_OFDM_FIRST_FLAG 0xF10E0070 -+#define F367_OFDM_TOP_FLAG1 0xF10E0008 -+#define F367_OFDM_TOP_FLAG0 0xF10E0004 -+#define F367_OFDM_CHC_FLAG1 0xF10E0002 -+#define F367_OFDM_CHC_FLAG0 0xF10E0001 -+ -+/* TRACKER_FREE1 */ -+#define R367_OFDM_TRACKER_FREE1 0xF10F -+#define F367_OFDM_TRACKER_FREE_1 0xF10F00FF -+ -+/* ERROR_CRL1 */ -+#define R367_OFDM_ERROR_CRL1 0xF110 -+#define F367_OFDM_ERROR_CRL_VHI 0xF11000FF -+ -+/* ERROR_CRL2 */ -+#define R367_OFDM_ERROR_CRL2 0xF111 -+#define F367_OFDM_ERROR_CRL_HI 0xF11100FF -+ -+/* ERROR_CRL3 */ -+#define R367_OFDM_ERROR_CRL3 0xF112 -+#define F367_OFDM_ERROR_CRL_LOI 0xF11200FF -+ -+/* ERROR_CRL4 */ -+#define R367_OFDM_ERROR_CRL4 0xF113 -+#define F367_OFDM_ERROR_CRL_VLO 0xF11300FF -+ -+/* DEC_NCO1 */ -+#define R367_OFDM_DEC_NCO1 0xF114 -+#define F367_OFDM_DEC_NCO_VHI 0xF11400FF -+ -+/* DEC_NCO2 */ -+#define R367_OFDM_DEC_NCO2 0xF115 -+#define F367_OFDM_DEC_NCO_HI 0xF11500FF -+ -+/* DEC_NCO3 */ -+#define R367_OFDM_DEC_NCO3 0xF116 -+#define F367_OFDM_DEC_NCO_LO 0xF11600FF -+ -+/* SNR */ -+#define R367_OFDM_SNR 0xF117 -+#define F367_OFDM_SNRATIO 0xF11700FF -+ -+/* SYR_FFTADJ1 */ -+#define R367_OFDM_SYR_FFTADJ1 0xF118 -+#define F367_OFDM_SYR_FFTADJ_HI 0xF11800FF -+ -+/* SYR_FFTADJ2 */ -+#define R367_OFDM_SYR_FFTADJ2 0xF119 -+#define F367_OFDM_SYR_FFTADJ_LO 0xF11900FF -+ -+/* SYR_CHCADJ1 */ -+#define R367_OFDM_SYR_CHCADJ1 0xF11A -+#define F367_OFDM_SYR_CHCADJ_HI 0xF11A00FF -+ -+/* SYR_CHCADJ2 */ -+#define R367_OFDM_SYR_CHCADJ2 0xF11B -+#define F367_OFDM_SYR_CHCADJ_LO 0xF11B00FF -+ -+/* SYR_OFF */ -+#define R367_OFDM_SYR_OFF 0xF11C -+#define F367_OFDM_SYR_OFFSET 0xF11C00FF -+ -+/* PPM_OFFSET1 */ -+#define R367_OFDM_PPM_OFFSET1 0xF11D -+#define F367_OFDM_PPM_OFFSET_HI 0xF11D00FF -+ -+/* PPM_OFFSET2 */ -+#define R367_OFDM_PPM_OFFSET2 0xF11E -+#define F367_OFDM_PPM_OFFSET_LO 0xF11E00FF -+ -+/* TRACKER_FREE2 */ -+#define R367_OFDM_TRACKER_FREE2 0xF11F -+#define F367_OFDM_TRACKER_FREE_2 0xF11F00FF -+ -+/* DEBG_LT10 */ -+#define R367_OFDM_DEBG_LT10 0xF120 -+#define F367_OFDM_DEBUG_LT10 0xF12000FF -+ -+/* DEBG_LT11 */ -+#define R367_OFDM_DEBG_LT11 0xF121 -+#define F367_OFDM_DEBUG_LT11 0xF12100FF -+ -+/* DEBG_LT12 */ -+#define R367_OFDM_DEBG_LT12 0xF122 -+#define F367_OFDM_DEBUG_LT12 0xF12200FF -+ -+/* DEBG_LT13 */ -+#define R367_OFDM_DEBG_LT13 0xF123 -+#define F367_OFDM_DEBUG_LT13 0xF12300FF -+ -+/* DEBG_LT14 */ -+#define R367_OFDM_DEBG_LT14 0xF124 -+#define F367_OFDM_DEBUG_LT14 0xF12400FF -+ -+/* DEBG_LT15 */ -+#define R367_OFDM_DEBG_LT15 0xF125 -+#define F367_OFDM_DEBUG_LT15 0xF12500FF -+ -+/* DEBG_LT16 */ -+#define R367_OFDM_DEBG_LT16 0xF126 -+#define F367_OFDM_DEBUG_LT16 0xF12600FF -+ -+/* DEBG_LT17 */ -+#define R367_OFDM_DEBG_LT17 0xF127 -+#define F367_OFDM_DEBUG_LT17 0xF12700FF -+ -+/* DEBG_LT18 */ -+#define R367_OFDM_DEBG_LT18 0xF128 -+#define F367_OFDM_DEBUG_LT18 0xF12800FF -+ -+/* DEBG_LT19 */ -+#define R367_OFDM_DEBG_LT19 0xF129 -+#define F367_OFDM_DEBUG_LT19 0xF12900FF -+ -+/* DEBG_LT1A */ -+#define R367_OFDM_DEBG_LT1A 0xF12A -+#define F367_OFDM_DEBUG_LT1A 0xF12A00FF -+ -+/* DEBG_LT1B */ -+#define R367_OFDM_DEBG_LT1B 0xF12B -+#define F367_OFDM_DEBUG_LT1B 0xF12B00FF -+ -+/* DEBG_LT1C */ -+#define R367_OFDM_DEBG_LT1C 0xF12C -+#define F367_OFDM_DEBUG_LT1C 0xF12C00FF -+ -+/* DEBG_LT1D */ -+#define R367_OFDM_DEBG_LT1D 0xF12D -+#define F367_OFDM_DEBUG_LT1D 0xF12D00FF -+ -+/* DEBG_LT1E */ -+#define R367_OFDM_DEBG_LT1E 0xF12E -+#define F367_OFDM_DEBUG_LT1E 0xF12E00FF -+ -+/* DEBG_LT1F */ -+#define R367_OFDM_DEBG_LT1F 0xF12F -+#define F367_OFDM_DEBUG_LT1F 0xF12F00FF -+ -+/* RCCFGH */ -+#define R367_OFDM_RCCFGH 0xF200 -+#define F367_OFDM_TSRCFIFO_DVBCI 0xF2000080 -+#define F367_OFDM_TSRCFIFO_SERIAL 0xF2000040 -+#define F367_OFDM_TSRCFIFO_DISABLE 0xF2000020 -+#define F367_OFDM_TSFIFO_2TORC 0xF2000010 -+#define F367_OFDM_TSRCFIFO_HSGNLOUT 0xF2000008 -+#define F367_OFDM_TSRCFIFO_ERRMODE 0xF2000006 -+#define F367_OFDM_RCCFGH_0 0xF2000001 -+ -+/* RCCFGM */ -+#define R367_OFDM_RCCFGM 0xF201 -+#define F367_OFDM_TSRCFIFO_MANSPEED 0xF20100C0 -+#define F367_OFDM_TSRCFIFO_PERMDATA 0xF2010020 -+#define F367_OFDM_TSRCFIFO_NONEWSGNL 0xF2010010 -+#define F367_OFDM_RCBYTE_OVERSAMPLING 0xF201000E -+#define F367_OFDM_TSRCFIFO_INVDATA 0xF2010001 -+ -+/* RCCFGL */ -+#define R367_OFDM_RCCFGL 0xF202 -+#define F367_OFDM_TSRCFIFO_BCLKDEL1CK 0xF20200C0 -+#define F367_OFDM_RCCFGL_5 0xF2020020 -+#define F367_OFDM_TSRCFIFO_DUTY50 0xF2020010 -+#define F367_OFDM_TSRCFIFO_NSGNL2DATA 0xF2020008 -+#define F367_OFDM_TSRCFIFO_DISSERMUX 0xF2020004 -+#define F367_OFDM_RCCFGL_1 0xF2020002 -+#define F367_OFDM_TSRCFIFO_STOPCKDIS 0xF2020001 -+ -+/* RCINSDELH */ -+#define R367_OFDM_RCINSDELH 0xF203 -+#define F367_OFDM_TSRCDEL_SYNCBYTE 0xF2030080 -+#define F367_OFDM_TSRCDEL_XXHEADER 0xF2030040 -+#define F367_OFDM_TSRCDEL_BBHEADER 0xF2030020 -+#define F367_OFDM_TSRCDEL_DATAFIELD 0xF2030010 -+#define F367_OFDM_TSRCINSDEL_ISCR 0xF2030008 -+#define F367_OFDM_TSRCINSDEL_NPD 0xF2030004 -+#define F367_OFDM_TSRCINSDEL_RSPARITY 0xF2030002 -+#define F367_OFDM_TSRCINSDEL_CRC8 0xF2030001 -+ -+/* RCINSDELM */ -+#define R367_OFDM_RCINSDELM 0xF204 -+#define F367_OFDM_TSRCINS_BBPADDING 0xF2040080 -+#define F367_OFDM_TSRCINS_BCHFEC 0xF2040040 -+#define F367_OFDM_TSRCINS_LDPCFEC 0xF2040020 -+#define F367_OFDM_TSRCINS_EMODCOD 0xF2040010 -+#define F367_OFDM_TSRCINS_TOKEN 0xF2040008 -+#define F367_OFDM_TSRCINS_XXXERR 0xF2040004 -+#define F367_OFDM_TSRCINS_MATYPE 0xF2040002 -+#define F367_OFDM_TSRCINS_UPL 0xF2040001 -+ -+/* RCINSDELL */ -+#define R367_OFDM_RCINSDELL 0xF205 -+#define F367_OFDM_TSRCINS_DFL 0xF2050080 -+#define F367_OFDM_TSRCINS_SYNCD 0xF2050040 -+#define F367_OFDM_TSRCINS_BLOCLEN 0xF2050020 -+#define F367_OFDM_TSRCINS_SIGPCOUNT 0xF2050010 -+#define F367_OFDM_TSRCINS_FIFO 0xF2050008 -+#define F367_OFDM_TSRCINS_REALPACK 0xF2050004 -+#define F367_OFDM_TSRCINS_TSCONFIG 0xF2050002 -+#define F367_OFDM_TSRCINS_LATENCY 0xF2050001 -+ -+/* RCSTATUS */ -+#define R367_OFDM_RCSTATUS 0xF206 -+#define F367_OFDM_TSRCFIFO_LINEOK 0xF2060080 -+#define F367_OFDM_TSRCFIFO_ERROR 0xF2060040 -+#define F367_OFDM_TSRCFIFO_DATA7 0xF2060020 -+#define F367_OFDM_RCSTATUS_4 0xF2060010 -+#define F367_OFDM_TSRCFIFO_DEMODSEL 0xF2060008 -+#define F367_OFDM_TSRC1FIFOSPEED_STORE 0xF2060004 -+#define F367_OFDM_RCSTATUS_1 0xF2060002 -+#define F367_OFDM_TSRCSERIAL_IMPOSSIBLE 0xF2060001 -+ -+/* RCSPEED */ -+#define R367_OFDM_RCSPEED 0xF207 -+#define F367_OFDM_TSRCFIFO_OUTSPEED 0xF20700FF -+ -+/* RCDEBUGM */ -+#define R367_OFDM_RCDEBUGM 0xF208 -+#define F367_OFDM_SD_UNSYNC 0xF2080080 -+#define F367_OFDM_ULFLOCK_DETECTM 0xF2080040 -+#define F367_OFDM_SUL_SELECTOS 0xF2080020 -+#define F367_OFDM_DILUL_NOSCRBLE 0xF2080010 -+#define F367_OFDM_NUL_SCRB 0xF2080008 -+#define F367_OFDM_UL_SCRB 0xF2080004 -+#define F367_OFDM_SCRAULBAD 0xF2080002 -+#define F367_OFDM_SCRAUL_UNSYNC 0xF2080001 -+ -+/* RCDEBUGL */ -+#define R367_OFDM_RCDEBUGL 0xF209 -+#define F367_OFDM_RS_ERR 0xF2090080 -+#define F367_OFDM_LLFLOCK_DETECTM 0xF2090040 -+#define F367_OFDM_NOT_SUL_SELECTOS 0xF2090020 -+#define F367_OFDM_DILLL_NOSCRBLE 0xF2090010 -+#define F367_OFDM_NLL_SCRB 0xF2090008 -+#define F367_OFDM_LL_SCRB 0xF2090004 -+#define F367_OFDM_SCRALLBAD 0xF2090002 -+#define F367_OFDM_SCRALL_UNSYNC 0xF2090001 -+ -+/* RCOBSCFG */ -+#define R367_OFDM_RCOBSCFG 0xF20A -+#define F367_OFDM_TSRCFIFO_OBSCFG 0xF20A00FF -+ -+/* RCOBSM */ -+#define R367_OFDM_RCOBSM 0xF20B -+#define F367_OFDM_TSRCFIFO_OBSDATA_HI 0xF20B00FF -+ -+/* RCOBSL */ -+#define R367_OFDM_RCOBSL 0xF20C -+#define F367_OFDM_TSRCFIFO_OBSDATA_LO 0xF20C00FF -+ -+/* RCFECSPY */ -+#define R367_OFDM_RCFECSPY 0xF210 -+#define F367_OFDM_SPYRC_ENABLE 0xF2100080 -+#define F367_OFDM_RCNO_SYNCBYTE 0xF2100040 -+#define F367_OFDM_RCSERIAL_MODE 0xF2100020 -+#define F367_OFDM_RCUNUSUAL_PACKET 0xF2100010 -+#define F367_OFDM_BERRCMETER_DATAMODE 0xF210000C -+#define F367_OFDM_BERRCMETER_LMODE 0xF2100002 -+#define F367_OFDM_BERRCMETER_RESET 0xF2100001 -+ -+/* RCFSPYCFG */ -+#define R367_OFDM_RCFSPYCFG 0xF211 -+#define F367_OFDM_FECSPYRC_INPUT 0xF21100C0 -+#define F367_OFDM_RCRST_ON_ERROR 0xF2110020 -+#define F367_OFDM_RCONE_SHOT 0xF2110010 -+#define F367_OFDM_RCI2C_MODE 0xF211000C -+#define F367_OFDM_SPYRC_HSTERESIS 0xF2110003 -+ -+/* RCFSPYDATA */ -+#define R367_OFDM_RCFSPYDATA 0xF212 -+#define F367_OFDM_SPYRC_STUFFING 0xF2120080 -+#define F367_OFDM_RCNOERR_PKTJITTER 0xF2120040 -+#define F367_OFDM_SPYRC_CNULLPKT 0xF2120020 -+#define F367_OFDM_SPYRC_OUTDATA_MODE 0xF212001F -+ -+/* RCFSPYOUT */ -+#define R367_OFDM_RCFSPYOUT 0xF213 -+#define F367_OFDM_FSPYRC_DIRECT 0xF2130080 -+#define F367_OFDM_RCFSPYOUT_6 0xF2130040 -+#define F367_OFDM_SPYRC_OUTDATA_BUS 0xF2130038 -+#define F367_OFDM_RCSTUFF_MODE 0xF2130007 -+ -+/* RCFSTATUS */ -+#define R367_OFDM_RCFSTATUS 0xF214 -+#define F367_OFDM_SPYRC_ENDSIM 0xF2140080 -+#define F367_OFDM_RCVALID_SIM 0xF2140040 -+#define F367_OFDM_RCFOUND_SIGNAL 0xF2140020 -+#define F367_OFDM_RCDSS_SYNCBYTE 0xF2140010 -+#define F367_OFDM_RCRESULT_STATE 0xF214000F -+ -+/* RCFGOODPACK */ -+#define R367_OFDM_RCFGOODPACK 0xF215 -+#define F367_OFDM_RCGOOD_PACKET 0xF21500FF -+ -+/* RCFPACKCNT */ -+#define R367_OFDM_RCFPACKCNT 0xF216 -+#define F367_OFDM_RCPACKET_COUNTER 0xF21600FF -+ -+/* RCFSPYMISC */ -+#define R367_OFDM_RCFSPYMISC 0xF217 -+#define F367_OFDM_RCLABEL_COUNTER 0xF21700FF -+ -+/* RCFBERCPT4 */ -+#define R367_OFDM_RCFBERCPT4 0xF218 -+#define F367_OFDM_FBERRCMETER_CPT_MMMMSB 0xF21800FF -+ -+/* RCFBERCPT3 */ -+#define R367_OFDM_RCFBERCPT3 0xF219 -+#define F367_OFDM_FBERRCMETER_CPT_MMMSB 0xF21900FF -+ -+/* RCFBERCPT2 */ -+#define R367_OFDM_RCFBERCPT2 0xF21A -+#define F367_OFDM_FBERRCMETER_CPT_MMSB 0xF21A00FF -+ -+/* RCFBERCPT1 */ -+#define R367_OFDM_RCFBERCPT1 0xF21B -+#define F367_OFDM_FBERRCMETER_CPT_MSB 0xF21B00FF -+ -+/* RCFBERCPT0 */ -+#define R367_OFDM_RCFBERCPT0 0xF21C -+#define F367_OFDM_FBERRCMETER_CPT_LSB 0xF21C00FF -+ -+/* RCFBERERR2 */ -+#define R367_OFDM_RCFBERERR2 0xF21D -+#define F367_OFDM_FBERRCMETER_ERR_HI 0xF21D00FF -+ -+/* RCFBERERR1 */ -+#define R367_OFDM_RCFBERERR1 0xF21E -+#define F367_OFDM_FBERRCMETER_ERR 0xF21E00FF -+ -+/* RCFBERERR0 */ -+#define R367_OFDM_RCFBERERR0 0xF21F -+#define F367_OFDM_FBERRCMETER_ERR_LO 0xF21F00FF -+ -+/* RCFSTATESM */ -+#define R367_OFDM_RCFSTATESM 0xF220 -+#define F367_OFDM_RCRSTATE_F 0xF2200080 -+#define F367_OFDM_RCRSTATE_E 0xF2200040 -+#define F367_OFDM_RCRSTATE_D 0xF2200020 -+#define F367_OFDM_RCRSTATE_C 0xF2200010 -+#define F367_OFDM_RCRSTATE_B 0xF2200008 -+#define F367_OFDM_RCRSTATE_A 0xF2200004 -+#define F367_OFDM_RCRSTATE_9 0xF2200002 -+#define F367_OFDM_RCRSTATE_8 0xF2200001 -+ -+/* RCFSTATESL */ -+#define R367_OFDM_RCFSTATESL 0xF221 -+#define F367_OFDM_RCRSTATE_7 0xF2210080 -+#define F367_OFDM_RCRSTATE_6 0xF2210040 -+#define F367_OFDM_RCRSTATE_5 0xF2210020 -+#define F367_OFDM_RCRSTATE_4 0xF2210010 -+#define F367_OFDM_RCRSTATE_3 0xF2210008 -+#define F367_OFDM_RCRSTATE_2 0xF2210004 -+#define F367_OFDM_RCRSTATE_1 0xF2210002 -+#define F367_OFDM_RCRSTATE_0 0xF2210001 -+ -+/* RCFSPYBER */ -+#define R367_OFDM_RCFSPYBER 0xF222 -+#define F367_OFDM_RCFSPYBER_7 0xF2220080 -+#define F367_OFDM_SPYRCOBS_XORREAD 0xF2220040 -+#define F367_OFDM_FSPYRCBER_OBSMODE 0xF2220020 -+#define F367_OFDM_FSPYRCBER_SYNCBYT 0xF2220010 -+#define F367_OFDM_FSPYRCBER_UNSYNC 0xF2220008 -+#define F367_OFDM_FSPYRCBER_CTIME 0xF2220007 -+ -+/* RCFSPYDISTM */ -+#define R367_OFDM_RCFSPYDISTM 0xF223 -+#define F367_OFDM_RCPKTTIME_DISTANCE_HI 0xF22300FF -+ -+/* RCFSPYDISTL */ -+#define R367_OFDM_RCFSPYDISTL 0xF224 -+#define F367_OFDM_RCPKTTIME_DISTANCE_LO 0xF22400FF -+ -+/* RCFSPYOBS7 */ -+#define R367_OFDM_RCFSPYOBS7 0xF228 -+#define F367_OFDM_RCSPYOBS_SPYFAIL 0xF2280080 -+#define F367_OFDM_RCSPYOBS_SPYFAIL1 0xF2280040 -+#define F367_OFDM_RCSPYOBS_ERROR 0xF2280020 -+#define F367_OFDM_RCSPYOBS_STROUT 0xF2280010 -+#define F367_OFDM_RCSPYOBS_RESULTSTATE1 0xF228000F -+ -+/* RCFSPYOBS6 */ -+#define R367_OFDM_RCFSPYOBS6 0xF229 -+#define F367_OFDM_RCSPYOBS_RESULTSTATE0 0xF22900F0 -+#define F367_OFDM_RCSPYOBS_RESULTSTATEM1 0xF229000F -+ -+/* RCFSPYOBS5 */ -+#define R367_OFDM_RCFSPYOBS5 0xF22A -+#define F367_OFDM_RCSPYOBS_BYTEOFPACKET1 0xF22A00FF -+ -+/* RCFSPYOBS4 */ -+#define R367_OFDM_RCFSPYOBS4 0xF22B -+#define F367_OFDM_RCSPYOBS_BYTEVALUE1 0xF22B00FF -+ -+/* RCFSPYOBS3 */ -+#define R367_OFDM_RCFSPYOBS3 0xF22C -+#define F367_OFDM_RCSPYOBS_DATA1 0xF22C00FF -+ -+/* RCFSPYOBS2 */ -+#define R367_OFDM_RCFSPYOBS2 0xF22D -+#define F367_OFDM_RCSPYOBS_DATA0 0xF22D00FF -+ -+/* RCFSPYOBS1 */ -+#define R367_OFDM_RCFSPYOBS1 0xF22E -+#define F367_OFDM_RCSPYOBS_DATAM1 0xF22E00FF -+ -+/* RCFSPYOBS0 */ -+#define R367_OFDM_RCFSPYOBS0 0xF22F -+#define F367_OFDM_RCSPYOBS_DATAM2 0xF22F00FF -+ -+/* TSGENERAL */ -+#define R367_TSGENERAL 0xF230 -+#define F367_TSGENERAL_7 0xF2300080 -+#define F367_TSGENERAL_6 0xF2300040 -+#define F367_TSFIFO_BCLK1ALL 0xF2300020 -+#define F367_TSGENERAL_4 0xF2300010 -+#define F367_MUXSTREAM_OUTMODE 0xF2300008 -+#define F367_TSFIFO_PERMPARAL 0xF2300006 -+#define F367_RST_REEDSOLO 0xF2300001 -+ -+/* RC1SPEED */ -+#define R367_RC1SPEED 0xF231 -+#define F367_TSRCFIFO1_OUTSPEED 0xF23100FF -+ -+/* TSGSTATUS */ -+#define R367_TSGSTATUS 0xF232 -+#define F367_TSGSTATUS_7 0xF2320080 -+#define F367_TSGSTATUS_6 0xF2320040 -+#define F367_RSMEM_FULL 0xF2320020 -+#define F367_RS_MULTCALC 0xF2320010 -+#define F367_RSIN_OVERTIME 0xF2320008 -+#define F367_TSFIFO3_DEMODSEL 0xF2320004 -+#define F367_TSFIFO2_DEMODSEL 0xF2320002 -+#define F367_TSFIFO1_DEMODSEL 0xF2320001 -+ -+ -+/* FECM */ -+#define R367_OFDM_FECM 0xF233 -+#define F367_OFDM_DSS_DVB 0xF2330080 -+#define F367_OFDM_DEMOD_BYPASS 0xF2330040 -+#define F367_OFDM_CMP_SLOWMODE 0xF2330020 -+#define F367_OFDM_DSS_SRCH 0xF2330010 -+#define F367_OFDM_FECM_3 0xF2330008 -+#define F367_OFDM_DIFF_MODEVIT 0xF2330004 -+#define F367_OFDM_SYNCVIT 0xF2330002 -+#define F367_OFDM_I2CSYM 0xF2330001 -+ -+/* VTH12 */ -+#define R367_OFDM_VTH12 0xF234 -+#define F367_OFDM_VTH_12 0xF23400FF -+ -+/* VTH23 */ -+#define R367_OFDM_VTH23 0xF235 -+#define F367_OFDM_VTH_23 0xF23500FF -+ -+/* VTH34 */ -+#define R367_OFDM_VTH34 0xF236 -+#define F367_OFDM_VTH_34 0xF23600FF -+ -+/* VTH56 */ -+#define R367_OFDM_VTH56 0xF237 -+#define F367_OFDM_VTH_56 0xF23700FF -+ -+/* VTH67 */ -+#define R367_OFDM_VTH67 0xF238 -+#define F367_OFDM_VTH_67 0xF23800FF -+ -+/* VTH78 */ -+#define R367_OFDM_VTH78 0xF239 -+#define F367_OFDM_VTH_78 0xF23900FF -+ -+/* VITCURPUN */ -+#define R367_OFDM_VITCURPUN 0xF23A -+#define F367_OFDM_VIT_MAPPING 0xF23A00E0 -+#define F367_OFDM_VIT_CURPUN 0xF23A001F -+ -+/* VERROR */ -+#define R367_OFDM_VERROR 0xF23B -+#define F367_OFDM_REGERR_VIT 0xF23B00FF -+ -+/* PRVIT */ -+#define R367_OFDM_PRVIT 0xF23C -+#define F367_OFDM_PRVIT_7 0xF23C0080 -+#define F367_OFDM_DIS_VTHLOCK 0xF23C0040 -+#define F367_OFDM_E7_8VIT 0xF23C0020 -+#define F367_OFDM_E6_7VIT 0xF23C0010 -+#define F367_OFDM_E5_6VIT 0xF23C0008 -+#define F367_OFDM_E3_4VIT 0xF23C0004 -+#define F367_OFDM_E2_3VIT 0xF23C0002 -+#define F367_OFDM_E1_2VIT 0xF23C0001 -+ -+/* VAVSRVIT */ -+#define R367_OFDM_VAVSRVIT 0xF23D -+#define F367_OFDM_AMVIT 0xF23D0080 -+#define F367_OFDM_FROZENVIT 0xF23D0040 -+#define F367_OFDM_SNVIT 0xF23D0030 -+#define F367_OFDM_TOVVIT 0xF23D000C -+#define F367_OFDM_HYPVIT 0xF23D0003 -+ -+/* VSTATUSVIT */ -+#define R367_OFDM_VSTATUSVIT 0xF23E -+#define F367_OFDM_VITERBI_ON 0xF23E0080 -+#define F367_OFDM_END_LOOPVIT 0xF23E0040 -+#define F367_OFDM_VITERBI_DEPRF 0xF23E0020 -+#define F367_OFDM_PRFVIT 0xF23E0010 -+#define F367_OFDM_LOCKEDVIT 0xF23E0008 -+#define F367_OFDM_VITERBI_DELOCK 0xF23E0004 -+#define F367_OFDM_VIT_DEMODSEL 0xF23E0002 -+#define F367_OFDM_VITERBI_COMPOUT 0xF23E0001 -+ -+/* VTHINUSE */ -+#define R367_OFDM_VTHINUSE 0xF23F -+#define F367_OFDM_VIT_INUSE 0xF23F00FF -+ -+/* KDIV12 */ -+#define R367_OFDM_KDIV12 0xF240 -+#define F367_OFDM_KDIV12_MANUAL 0xF2400080 -+#define F367_OFDM_K_DIVIDER_12 0xF240007F -+ -+/* KDIV23 */ -+#define R367_OFDM_KDIV23 0xF241 -+#define F367_OFDM_KDIV23_MANUAL 0xF2410080 -+#define F367_OFDM_K_DIVIDER_23 0xF241007F -+ -+/* KDIV34 */ -+#define R367_OFDM_KDIV34 0xF242 -+#define F367_OFDM_KDIV34_MANUAL 0xF2420080 -+#define F367_OFDM_K_DIVIDER_34 0xF242007F -+ -+/* KDIV56 */ -+#define R367_OFDM_KDIV56 0xF243 -+#define F367_OFDM_KDIV56_MANUAL 0xF2430080 -+#define F367_OFDM_K_DIVIDER_56 0xF243007F -+ -+/* KDIV67 */ -+#define R367_OFDM_KDIV67 0xF244 -+#define F367_OFDM_KDIV67_MANUAL 0xF2440080 -+#define F367_OFDM_K_DIVIDER_67 0xF244007F -+ -+/* KDIV78 */ -+#define R367_OFDM_KDIV78 0xF245 -+#define F367_OFDM_KDIV78_MANUAL 0xF2450080 -+#define F367_OFDM_K_DIVIDER_78 0xF245007F -+ -+/* SIGPOWER */ -+#define R367_OFDM_SIGPOWER 0xF246 -+#define F367_OFDM_SIGPOWER_MANUAL 0xF2460080 -+#define F367_OFDM_SIG_POWER 0xF246007F -+ -+/* DEMAPVIT */ -+#define R367_OFDM_DEMAPVIT 0xF247 -+#define F367_OFDM_DEMAPVIT_7 0xF2470080 -+#define F367_OFDM_K_DIVIDER_VIT 0xF247007F -+ -+/* VITSCALE */ -+#define R367_OFDM_VITSCALE 0xF248 -+#define F367_OFDM_NVTH_NOSRANGE 0xF2480080 -+#define F367_OFDM_VERROR_MAXMODE 0xF2480040 -+#define F367_OFDM_KDIV_MODE 0xF2480030 -+#define F367_OFDM_NSLOWSN_LOCKED 0xF2480008 -+#define F367_OFDM_DELOCK_PRFLOSS 0xF2480004 -+#define F367_OFDM_DIS_RSFLOCK 0xF2480002 -+#define F367_OFDM_VITSCALE_0 0xF2480001 -+ -+/* FFEC1PRG */ -+#define R367_OFDM_FFEC1PRG 0xF249 -+#define F367_OFDM_FDSS_DVB 0xF2490080 -+#define F367_OFDM_FDSS_SRCH 0xF2490040 -+#define F367_OFDM_FFECPROG_5 0xF2490020 -+#define F367_OFDM_FFECPROG_4 0xF2490010 -+#define F367_OFDM_FFECPROG_3 0xF2490008 -+#define F367_OFDM_FFECPROG_2 0xF2490004 -+#define F367_OFDM_FTS1_DISABLE 0xF2490002 -+#define F367_OFDM_FTS2_DISABLE 0xF2490001 -+ -+/* FVITCURPUN */ -+#define R367_OFDM_FVITCURPUN 0xF24A -+#define F367_OFDM_FVIT_MAPPING 0xF24A00E0 -+#define F367_OFDM_FVIT_CURPUN 0xF24A001F -+ -+/* FVERROR */ -+#define R367_OFDM_FVERROR 0xF24B -+#define F367_OFDM_FREGERR_VIT 0xF24B00FF -+ -+/* FVSTATUSVIT */ -+#define R367_OFDM_FVSTATUSVIT 0xF24C -+#define F367_OFDM_FVITERBI_ON 0xF24C0080 -+#define F367_OFDM_F1END_LOOPVIT 0xF24C0040 -+#define F367_OFDM_FVITERBI_DEPRF 0xF24C0020 -+#define F367_OFDM_FPRFVIT 0xF24C0010 -+#define F367_OFDM_FLOCKEDVIT 0xF24C0008 -+#define F367_OFDM_FVITERBI_DELOCK 0xF24C0004 -+#define F367_OFDM_FVIT_DEMODSEL 0xF24C0002 -+#define F367_OFDM_FVITERBI_COMPOUT 0xF24C0001 -+ -+/* DEBUG_LT1 */ -+#define R367_OFDM_DEBUG_LT1 0xF24D -+#define F367_OFDM_DBG_LT1 0xF24D00FF -+ -+/* DEBUG_LT2 */ -+#define R367_OFDM_DEBUG_LT2 0xF24E -+#define F367_OFDM_DBG_LT2 0xF24E00FF -+ -+/* DEBUG_LT3 */ -+#define R367_OFDM_DEBUG_LT3 0xF24F -+#define F367_OFDM_DBG_LT3 0xF24F00FF -+ -+ /* TSTSFMET */ -+#define R367_OFDM_TSTSFMET 0xF250 -+#define F367_OFDM_TSTSFEC_METRIQUES 0xF25000FF -+ -+ /* SELOUT */ -+#define R367_OFDM_SELOUT 0xF252 -+#define F367_OFDM_EN_SYNC 0xF2520080 -+#define F367_OFDM_EN_TBUSDEMAP 0xF2520040 -+#define F367_OFDM_SELOUT_5 0xF2520020 -+#define F367_OFDM_SELOUT_4 0xF2520010 -+#define F367_OFDM_TSTSYNCHRO_MODE 0xF2520002 -+ -+ /* TSYNC */ -+#define R367_OFDM_TSYNC 0xF253 -+#define F367_OFDM_CURPUN_INCMODE 0xF2530080 -+#define F367_OFDM_CERR_TSTMODE 0xF2530040 -+#define F367_OFDM_SHIFTSOF_MODE 0xF2530030 -+#define F367_OFDM_SLOWPHA_MODE 0xF2530008 -+#define F367_OFDM_PXX_BYPALL 0xF2530004 -+#define F367_OFDM_FROTA45_FIRST 0xF2530002 -+#define F367_OFDM_TST_BCHERROR 0xF2530001 -+ -+ /* TSTERR */ -+#define R367_OFDM_TSTERR 0xF254 -+#define F367_OFDM_TST_LONGPKT 0xF2540080 -+#define F367_OFDM_TST_ISSYION 0xF2540040 -+#define F367_OFDM_TST_NPDON 0xF2540020 -+#define F367_OFDM_TSTERR_4 0xF2540010 -+#define F367_OFDM_TRACEBACK_MODE 0xF2540008 -+#define F367_OFDM_TST_RSPARITY 0xF2540004 -+#define F367_OFDM_METRIQUE_MODE 0xF2540003 -+ -+ /* TSFSYNC */ -+#define R367_OFDM_TSFSYNC 0xF255 -+#define F367_OFDM_EN_SFECSYNC 0xF2550080 -+#define F367_OFDM_EN_SFECDEMAP 0xF2550040 -+#define F367_OFDM_SFCERR_TSTMODE 0xF2550020 -+#define F367_OFDM_SFECPXX_BYPALL 0xF2550010 -+#define F367_OFDM_SFECTSTSYNCHRO_MODE 0xF255000F -+ -+ /* TSTSFERR */ -+#define R367_OFDM_TSTSFERR 0xF256 -+#define F367_OFDM_TSTSTERR_7 0xF2560080 -+#define F367_OFDM_TSTSTERR_6 0xF2560040 -+#define F367_OFDM_TSTSTERR_5 0xF2560020 -+#define F367_OFDM_TSTSTERR_4 0xF2560010 -+#define F367_OFDM_SFECTRACEBACK_MODE 0xF2560008 -+#define F367_OFDM_SFEC_NCONVPROG 0xF2560004 -+#define F367_OFDM_SFECMETRIQUE_MODE 0xF2560003 -+ -+ /* TSTTSSF1 */ -+#define R367_OFDM_TSTTSSF1 0xF258 -+#define F367_OFDM_TSTERSSF 0xF2580080 -+#define F367_OFDM_TSTTSSFEN 0xF2580040 -+#define F367_OFDM_SFEC_OUTMODE 0xF2580030 -+#define F367_OFDM_XLSF_NOFTHRESHOLD 0xF2580008 -+#define F367_OFDM_TSTTSSF_STACKSEL 0xF2580007 -+ -+ /* TSTTSSF2 */ -+#define R367_OFDM_TSTTSSF2 0xF259 -+#define F367_OFDM_DILSF_DBBHEADER 0xF2590080 -+#define F367_OFDM_TSTTSSF_DISBUG 0xF2590040 -+#define F367_OFDM_TSTTSSF_NOBADSTART 0xF2590020 -+#define F367_OFDM_TSTTSSF_SELECT 0xF259001F -+ -+ /* TSTTSSF3 */ -+#define R367_OFDM_TSTTSSF3 0xF25A -+#define F367_OFDM_TSTTSSF3_7 0xF25A0080 -+#define F367_OFDM_TSTTSSF3_6 0xF25A0040 -+#define F367_OFDM_TSTTSSF3_5 0xF25A0020 -+#define F367_OFDM_TSTTSSF3_4 0xF25A0010 -+#define F367_OFDM_TSTTSSF3_3 0xF25A0008 -+#define F367_OFDM_TSTTSSF3_2 0xF25A0004 -+#define F367_OFDM_TSTTSSF3_1 0xF25A0002 -+#define F367_OFDM_DISSF_CLKENABLE 0xF25A0001 -+ -+ /* TSTTS1 */ -+#define R367_OFDM_TSTTS1 0xF25C -+#define F367_OFDM_TSTERS 0xF25C0080 -+#define F367_OFDM_TSFIFO_DSSSYNCB 0xF25C0040 -+#define F367_OFDM_TSTTS_FSPYBEFRS 0xF25C0020 -+#define F367_OFDM_NFORCE_SYNCBYTE 0xF25C0010 -+#define F367_OFDM_XL_NOFTHRESHOLD 0xF25C0008 -+#define F367_OFDM_TSTTS_FRFORCEPKT 0xF25C0004 -+#define F367_OFDM_DESCR_NOTAUTO 0xF25C0002 -+#define F367_OFDM_TSTTSEN 0xF25C0001 -+ -+ /* TSTTS2 */ -+#define R367_OFDM_TSTTS2 0xF25D -+#define F367_OFDM_DIL_DBBHEADER 0xF25D0080 -+#define F367_OFDM_TSTTS_NOBADXXX 0xF25D0040 -+#define F367_OFDM_TSFIFO_DELSPEEDUP 0xF25D0020 -+#define F367_OFDM_TSTTS_SELECT 0xF25D001F -+ -+ /* TSTTS3 */ -+#define R367_OFDM_TSTTS3 0xF25E -+#define F367_OFDM_TSTTS_NOPKTGAIN 0xF25E0080 -+#define F367_OFDM_TSTTS_NOPKTENE 0xF25E0040 -+#define F367_OFDM_TSTTS_ISOLATION 0xF25E0020 -+#define F367_OFDM_TSTTS_DISBUG 0xF25E0010 -+#define F367_OFDM_TSTTS_NOBADSTART 0xF25E0008 -+#define F367_OFDM_TSTTS_STACKSEL 0xF25E0007 -+ -+ /* TSTTS4 */ -+#define R367_OFDM_TSTTS4 0xF25F -+#define F367_OFDM_TSTTS4_7 0xF25F0080 -+#define F367_OFDM_TSTTS4_6 0xF25F0040 -+#define F367_OFDM_TSTTS4_5 0xF25F0020 -+#define F367_OFDM_TSTTS_DISDSTATE 0xF25F0010 -+#define F367_OFDM_TSTTS_FASTNOSYNC 0xF25F0008 -+#define F367_OFDM_EXT_FECSPYIN 0xF25F0004 -+#define F367_OFDM_TSTTS_NODPZERO 0xF25F0002 -+#define F367_OFDM_TSTTS_NODIV3 0xF25F0001 -+ -+ /* TSTTSRC */ -+#define R367_OFDM_TSTTSRC 0xF26C -+#define F367_OFDM_TSTTSRC_7 0xF26C0080 -+#define F367_OFDM_TSRCFIFO_DSSSYNCB 0xF26C0040 -+#define F367_OFDM_TSRCFIFO_DPUNACTIVE 0xF26C0020 -+#define F367_OFDM_TSRCFIFO_DELSPEEDUP 0xF26C0010 -+#define F367_OFDM_TSTTSRC_NODIV3 0xF26C0008 -+#define F367_OFDM_TSTTSRC_FRFORCEPKT 0xF26C0004 -+#define F367_OFDM_SAT25_SDDORIGINE 0xF26C0002 -+#define F367_OFDM_TSTTSRC_INACTIVE 0xF26C0001 -+ -+ /* TSTTSRS */ -+#define R367_OFDM_TSTTSRS 0xF26D -+#define F367_OFDM_TSTTSRS_7 0xF26D0080 -+#define F367_OFDM_TSTTSRS_6 0xF26D0040 -+#define F367_OFDM_TSTTSRS_5 0xF26D0020 -+#define F367_OFDM_TSTTSRS_4 0xF26D0010 -+#define F367_OFDM_TSTTSRS_3 0xF26D0008 -+#define F367_OFDM_TSTTSRS_2 0xF26D0004 -+#define F367_OFDM_TSTRS_DISRS2 0xF26D0002 -+#define F367_OFDM_TSTRS_DISRS1 0xF26D0001 -+ -+/* TSSTATEM */ -+#define R367_OFDM_TSSTATEM 0xF270 -+#define F367_OFDM_TSDIL_ON 0xF2700080 -+#define F367_OFDM_TSSKIPRS_ON 0xF2700040 -+#define F367_OFDM_TSRS_ON 0xF2700020 -+#define F367_OFDM_TSDESCRAMB_ON 0xF2700010 -+#define F367_OFDM_TSFRAME_MODE 0xF2700008 -+#define F367_OFDM_TS_DISABLE 0xF2700004 -+#define F367_OFDM_TSACM_MODE 0xF2700002 -+#define F367_OFDM_TSOUT_NOSYNC 0xF2700001 -+ -+/* TSSTATEL */ -+#define R367_OFDM_TSSTATEL 0xF271 -+#define F367_OFDM_TSNOSYNCBYTE 0xF2710080 -+#define F367_OFDM_TSPARITY_ON 0xF2710040 -+#define F367_OFDM_TSSYNCOUTRS_ON 0xF2710020 -+#define F367_OFDM_TSDVBS2_MODE 0xF2710010 -+#define F367_OFDM_TSISSYI_ON 0xF2710008 -+#define F367_OFDM_TSNPD_ON 0xF2710004 -+#define F367_OFDM_TSCRC8_ON 0xF2710002 -+#define F367_OFDM_TSDSS_PACKET 0xF2710001 -+ -+/* TSCFGH */ -+#define R367_OFDM_TSCFGH 0xF272 -+#define F367_OFDM_TSFIFO_DVBCI 0xF2720080 -+#define F367_OFDM_TSFIFO_SERIAL 0xF2720040 -+#define F367_OFDM_TSFIFO_TEIUPDATE 0xF2720020 -+#define F367_OFDM_TSFIFO_DUTY50 0xF2720010 -+#define F367_OFDM_TSFIFO_HSGNLOUT 0xF2720008 -+#define F367_OFDM_TSFIFO_ERRMODE 0xF2720006 -+#define F367_OFDM_RST_HWARE 0xF2720001 -+ -+/* TSCFGM */ -+#define R367_OFDM_TSCFGM 0xF273 -+#define F367_OFDM_TSFIFO_MANSPEED 0xF27300C0 -+#define F367_OFDM_TSFIFO_PERMDATA 0xF2730020 -+#define F367_OFDM_TSFIFO_NONEWSGNL 0xF2730010 -+#define F367_OFDM_TSFIFO_BITSPEED 0xF2730008 -+#define F367_OFDM_NPD_SPECDVBS2 0xF2730004 -+#define F367_OFDM_TSFIFO_STOPCKDIS 0xF2730002 -+#define F367_OFDM_TSFIFO_INVDATA 0xF2730001 -+ -+/* TSCFGL */ -+#define R367_OFDM_TSCFGL 0xF274 -+#define F367_OFDM_TSFIFO_BCLKDEL1CK 0xF27400C0 -+#define F367_OFDM_BCHERROR_MODE 0xF2740030 -+#define F367_OFDM_TSFIFO_NSGNL2DATA 0xF2740008 -+#define F367_OFDM_TSFIFO_EMBINDVB 0xF2740004 -+#define F367_OFDM_TSFIFO_DPUNACT 0xF2740002 -+#define F367_OFDM_TSFIFO_NPDOFF 0xF2740001 -+ -+/* TSSYNC */ -+#define R367_OFDM_TSSYNC 0xF275 -+#define F367_OFDM_TSFIFO_PERMUTE 0xF2750080 -+#define F367_OFDM_TSFIFO_FISCR3B 0xF2750060 -+#define F367_OFDM_TSFIFO_SYNCMODE 0xF2750018 -+#define F367_OFDM_TSFIFO_SYNCSEL 0xF2750007 -+ -+/* TSINSDELH */ -+#define R367_OFDM_TSINSDELH 0xF276 -+#define F367_OFDM_TSDEL_SYNCBYTE 0xF2760080 -+#define F367_OFDM_TSDEL_XXHEADER 0xF2760040 -+#define F367_OFDM_TSDEL_BBHEADER 0xF2760020 -+#define F367_OFDM_TSDEL_DATAFIELD 0xF2760010 -+#define F367_OFDM_TSINSDEL_ISCR 0xF2760008 -+#define F367_OFDM_TSINSDEL_NPD 0xF2760004 -+#define F367_OFDM_TSINSDEL_RSPARITY 0xF2760002 -+#define F367_OFDM_TSINSDEL_CRC8 0xF2760001 -+ -+/* TSINSDELM */ -+#define R367_OFDM_TSINSDELM 0xF277 -+#define F367_OFDM_TSINS_BBPADDING 0xF2770080 -+#define F367_OFDM_TSINS_BCHFEC 0xF2770040 -+#define F367_OFDM_TSINS_LDPCFEC 0xF2770020 -+#define F367_OFDM_TSINS_EMODCOD 0xF2770010 -+#define F367_OFDM_TSINS_TOKEN 0xF2770008 -+#define F367_OFDM_TSINS_XXXERR 0xF2770004 -+#define F367_OFDM_TSINS_MATYPE 0xF2770002 -+#define F367_OFDM_TSINS_UPL 0xF2770001 -+ -+/* TSINSDELL */ -+#define R367_OFDM_TSINSDELL 0xF278 -+#define F367_OFDM_TSINS_DFL 0xF2780080 -+#define F367_OFDM_TSINS_SYNCD 0xF2780040 -+#define F367_OFDM_TSINS_BLOCLEN 0xF2780020 -+#define F367_OFDM_TSINS_SIGPCOUNT 0xF2780010 -+#define F367_OFDM_TSINS_FIFO 0xF2780008 -+#define F367_OFDM_TSINS_REALPACK 0xF2780004 -+#define F367_OFDM_TSINS_TSCONFIG 0xF2780002 -+#define F367_OFDM_TSINS_LATENCY 0xF2780001 -+ -+/* TSDIVN */ -+#define R367_OFDM_TSDIVN 0xF279 -+#define F367_OFDM_TSFIFO_LOWSPEED 0xF2790080 -+#define F367_OFDM_BYTE_OVERSAMPLING 0xF2790070 -+#define F367_OFDM_TSMANUAL_PACKETNBR 0xF279000F -+ -+/* TSDIVPM */ -+#define R367_OFDM_TSDIVPM 0xF27A -+#define F367_OFDM_TSMANUAL_P_HI 0xF27A00FF -+ -+/* TSDIVPL */ -+#define R367_OFDM_TSDIVPL 0xF27B -+#define F367_OFDM_TSMANUAL_P_LO 0xF27B00FF -+ -+/* TSDIVQM */ -+#define R367_OFDM_TSDIVQM 0xF27C -+#define F367_OFDM_TSMANUAL_Q_HI 0xF27C00FF -+ -+/* TSDIVQL */ -+#define R367_OFDM_TSDIVQL 0xF27D -+#define F367_OFDM_TSMANUAL_Q_LO 0xF27D00FF -+ -+/* TSDILSTKM */ -+#define R367_OFDM_TSDILSTKM 0xF27E -+#define F367_OFDM_TSFIFO_DILSTK_HI 0xF27E00FF -+ -+/* TSDILSTKL */ -+#define R367_OFDM_TSDILSTKL 0xF27F -+#define F367_OFDM_TSFIFO_DILSTK_LO 0xF27F00FF -+ -+/* TSSPEED */ -+#define R367_OFDM_TSSPEED 0xF280 -+#define F367_OFDM_TSFIFO_OUTSPEED 0xF28000FF -+ -+/* TSSTATUS */ -+#define R367_OFDM_TSSTATUS 0xF281 -+#define F367_OFDM_TSFIFO_LINEOK 0xF2810080 -+#define F367_OFDM_TSFIFO_ERROR 0xF2810040 -+#define F367_OFDM_TSFIFO_DATA7 0xF2810020 -+#define F367_OFDM_TSFIFO_NOSYNC 0xF2810010 -+#define F367_OFDM_ISCR_INITIALIZED 0xF2810008 -+#define F367_OFDM_ISCR_UPDATED 0xF2810004 -+#define F367_OFDM_SOFFIFO_UNREGUL 0xF2810002 -+#define F367_OFDM_DIL_READY 0xF2810001 -+ -+/* TSSTATUS2 */ -+#define R367_OFDM_TSSTATUS2 0xF282 -+#define F367_OFDM_TSFIFO_DEMODSEL 0xF2820080 -+#define F367_OFDM_TSFIFOSPEED_STORE 0xF2820040 -+#define F367_OFDM_DILXX_RESET 0xF2820020 -+#define F367_OFDM_TSSERIAL_IMPOSSIBLE 0xF2820010 -+#define F367_OFDM_TSFIFO_UNDERSPEED 0xF2820008 -+#define F367_OFDM_BITSPEED_EVENT 0xF2820004 -+#define F367_OFDM_UL_SCRAMBDETECT 0xF2820002 -+#define F367_OFDM_ULDTV67_FALSELOCK 0xF2820001 -+ -+/* TSBITRATEM */ -+#define R367_OFDM_TSBITRATEM 0xF283 -+#define F367_OFDM_TSFIFO_BITRATE_HI 0xF28300FF -+ -+/* TSBITRATEL */ -+#define R367_OFDM_TSBITRATEL 0xF284 -+#define F367_OFDM_TSFIFO_BITRATE_LO 0xF28400FF -+ -+/* TSPACKLENM */ -+#define R367_OFDM_TSPACKLENM 0xF285 -+#define F367_OFDM_TSFIFO_PACKCPT 0xF28500E0 -+#define F367_OFDM_DIL_RPLEN_HI 0xF285001F -+ -+/* TSPACKLENL */ -+#define R367_OFDM_TSPACKLENL 0xF286 -+#define F367_OFDM_DIL_RPLEN_LO 0xF28600FF -+ -+/* TSBLOCLENM */ -+#define R367_OFDM_TSBLOCLENM 0xF287 -+#define F367_OFDM_TSFIFO_PFLEN_HI 0xF28700FF -+ -+/* TSBLOCLENL */ -+#define R367_OFDM_TSBLOCLENL 0xF288 -+#define F367_OFDM_TSFIFO_PFLEN_LO 0xF28800FF -+ -+/* TSDLYH */ -+#define R367_OFDM_TSDLYH 0xF289 -+#define F367_OFDM_SOFFIFO_TSTIMEVALID 0xF2890080 -+#define F367_OFDM_SOFFIFO_SPEEDUP 0xF2890040 -+#define F367_OFDM_SOFFIFO_STOP 0xF2890020 -+#define F367_OFDM_SOFFIFO_REGULATED 0xF2890010 -+#define F367_OFDM_SOFFIFO_REALSBOFF_HI 0xF289000F -+ -+/* TSDLYM */ -+#define R367_OFDM_TSDLYM 0xF28A -+#define F367_OFDM_SOFFIFO_REALSBOFF_MED 0xF28A00FF -+ -+/* TSDLYL */ -+#define R367_OFDM_TSDLYL 0xF28B -+#define F367_OFDM_SOFFIFO_REALSBOFF_LO 0xF28B00FF -+ -+/* TSNPDAV */ -+#define R367_OFDM_TSNPDAV 0xF28C -+#define F367_OFDM_TSNPD_AVERAGE 0xF28C00FF -+ -+/* TSBUFSTATH */ -+#define R367_OFDM_TSBUFSTATH 0xF28D -+#define F367_OFDM_TSISCR_3BYTES 0xF28D0080 -+#define F367_OFDM_TSISCR_NEWDATA 0xF28D0040 -+#define F367_OFDM_TSISCR_BUFSTAT_HI 0xF28D003F -+ -+/* TSBUFSTATM */ -+#define R367_OFDM_TSBUFSTATM 0xF28E -+#define F367_OFDM_TSISCR_BUFSTAT_MED 0xF28E00FF -+ -+/* TSBUFSTATL */ -+#define R367_OFDM_TSBUFSTATL 0xF28F -+#define F367_OFDM_TSISCR_BUFSTAT_LO 0xF28F00FF -+ -+/* TSDEBUGM */ -+#define R367_OFDM_TSDEBUGM 0xF290 -+#define F367_OFDM_TSFIFO_ILLPACKET 0xF2900080 -+#define F367_OFDM_DIL_NOSYNC 0xF2900040 -+#define F367_OFDM_DIL_ISCR 0xF2900020 -+#define F367_OFDM_DILOUT_BSYNCB 0xF2900010 -+#define F367_OFDM_TSFIFO_EMPTYPKT 0xF2900008 -+#define F367_OFDM_TSFIFO_EMPTYRD 0xF2900004 -+#define F367_OFDM_SOFFIFO_STOPM 0xF2900002 -+#define F367_OFDM_SOFFIFO_SPEEDUPM 0xF2900001 -+ -+/* TSDEBUGL */ -+#define R367_OFDM_TSDEBUGL 0xF291 -+#define F367_OFDM_TSFIFO_PACKLENFAIL 0xF2910080 -+#define F367_OFDM_TSFIFO_SYNCBFAIL 0xF2910040 -+#define F367_OFDM_TSFIFO_VITLIBRE 0xF2910020 -+#define F367_OFDM_TSFIFO_BOOSTSPEEDM 0xF2910010 -+#define F367_OFDM_TSFIFO_UNDERSPEEDM 0xF2910008 -+#define F367_OFDM_TSFIFO_ERROR_EVNT 0xF2910004 -+#define F367_OFDM_TSFIFO_FULL 0xF2910002 -+#define F367_OFDM_TSFIFO_OVERFLOWM 0xF2910001 -+ -+/* TSDLYSETH */ -+#define R367_OFDM_TSDLYSETH 0xF292 -+#define F367_OFDM_SOFFIFO_OFFSET 0xF29200E0 -+#define F367_OFDM_SOFFIFO_SYMBOFFSET_HI 0xF292001F -+ -+/* TSDLYSETM */ -+#define R367_OFDM_TSDLYSETM 0xF293 -+#define F367_OFDM_SOFFIFO_SYMBOFFSET_MED 0xF29300FF -+ -+/* TSDLYSETL */ -+#define R367_OFDM_TSDLYSETL 0xF294 -+#define F367_OFDM_SOFFIFO_SYMBOFFSET_LO 0xF29400FF -+ -+/* TSOBSCFG */ -+#define R367_OFDM_TSOBSCFG 0xF295 -+#define F367_OFDM_TSFIFO_OBSCFG 0xF29500FF -+ -+/* TSOBSM */ -+#define R367_OFDM_TSOBSM 0xF296 -+#define F367_OFDM_TSFIFO_OBSDATA_HI 0xF29600FF -+ -+/* TSOBSL */ -+#define R367_OFDM_TSOBSL 0xF297 -+#define F367_OFDM_TSFIFO_OBSDATA_LO 0xF29700FF -+ -+/* ERRCTRL1 */ -+#define R367_OFDM_ERRCTRL1 0xF298 -+#define F367_OFDM_ERR_SRC1 0xF29800F0 -+#define F367_OFDM_ERRCTRL1_3 0xF2980008 -+#define F367_OFDM_NUM_EVT1 0xF2980007 -+ -+/* ERRCNT1H */ -+#define R367_OFDM_ERRCNT1H 0xF299 -+#define F367_OFDM_ERRCNT1_OLDVALUE 0xF2990080 -+#define F367_OFDM_ERR_CNT1 0xF299007F -+ -+/* ERRCNT1M */ -+#define R367_OFDM_ERRCNT1M 0xF29A -+#define F367_OFDM_ERR_CNT1_HI 0xF29A00FF -+ -+/* ERRCNT1L */ -+#define R367_OFDM_ERRCNT1L 0xF29B -+#define F367_OFDM_ERR_CNT1_LO 0xF29B00FF -+ -+/* ERRCTRL2 */ -+#define R367_OFDM_ERRCTRL2 0xF29C -+#define F367_OFDM_ERR_SRC2 0xF29C00F0 -+#define F367_OFDM_ERRCTRL2_3 0xF29C0008 -+#define F367_OFDM_NUM_EVT2 0xF29C0007 -+ -+/* ERRCNT2H */ -+#define R367_OFDM_ERRCNT2H 0xF29D -+#define F367_OFDM_ERRCNT2_OLDVALUE 0xF29D0080 -+#define F367_OFDM_ERR_CNT2_HI 0xF29D007F -+ -+/* ERRCNT2M */ -+#define R367_OFDM_ERRCNT2M 0xF29E -+#define F367_OFDM_ERR_CNT2_MED 0xF29E00FF -+ -+/* ERRCNT2L */ -+#define R367_OFDM_ERRCNT2L 0xF29F -+#define F367_OFDM_ERR_CNT2_LO 0xF29F00FF -+ -+/* FECSPY */ -+#define R367_OFDM_FECSPY 0xF2A0 -+#define F367_OFDM_SPY_ENABLE 0xF2A00080 -+#define F367_OFDM_NO_SYNCBYTE 0xF2A00040 -+#define F367_OFDM_SERIAL_MODE 0xF2A00020 -+#define F367_OFDM_UNUSUAL_PACKET 0xF2A00010 -+#define F367_OFDM_BERMETER_DATAMODE 0xF2A0000C -+#define F367_OFDM_BERMETER_LMODE 0xF2A00002 -+#define F367_OFDM_BERMETER_RESET 0xF2A00001 -+ -+/* FSPYCFG */ -+#define R367_OFDM_FSPYCFG 0xF2A1 -+#define F367_OFDM_FECSPY_INPUT 0xF2A100C0 -+#define F367_OFDM_RST_ON_ERROR 0xF2A10020 -+#define F367_OFDM_ONE_SHOT 0xF2A10010 -+#define F367_OFDM_I2C_MOD 0xF2A1000C -+#define F367_OFDM_SPY_HYSTERESIS 0xF2A10003 -+ -+/* FSPYDATA */ -+#define R367_OFDM_FSPYDATA 0xF2A2 -+#define F367_OFDM_SPY_STUFFING 0xF2A20080 -+#define F367_OFDM_NOERROR_PKTJITTER 0xF2A20040 -+#define F367_OFDM_SPY_CNULLPKT 0xF2A20020 -+#define F367_OFDM_SPY_OUTDATA_MODE 0xF2A2001F -+ -+/* FSPYOUT */ -+#define R367_OFDM_FSPYOUT 0xF2A3 -+#define F367_OFDM_FSPY_DIRECT 0xF2A30080 -+#define F367_OFDM_FSPYOUT_6 0xF2A30040 -+#define F367_OFDM_SPY_OUTDATA_BUS 0xF2A30038 -+#define F367_OFDM_STUFF_MODE 0xF2A30007 -+ -+/* FSTATUS */ -+#define R367_OFDM_FSTATUS 0xF2A4 -+#define F367_OFDM_SPY_ENDSIM 0xF2A40080 -+#define F367_OFDM_VALID_SIM 0xF2A40040 -+#define F367_OFDM_FOUND_SIGNAL 0xF2A40020 -+#define F367_OFDM_DSS_SYNCBYTE 0xF2A40010 -+#define F367_OFDM_RESULT_STATE 0xF2A4000F -+ -+/* FGOODPACK */ -+#define R367_OFDM_FGOODPACK 0xF2A5 -+#define F367_OFDM_FGOOD_PACKET 0xF2A500FF -+ -+/* FPACKCNT */ -+#define R367_OFDM_FPACKCNT 0xF2A6 -+#define F367_OFDM_FPACKET_COUNTER 0xF2A600FF -+ -+/* FSPYMISC */ -+#define R367_OFDM_FSPYMISC 0xF2A7 -+#define F367_OFDM_FLABEL_COUNTER 0xF2A700FF -+ -+/* FBERCPT4 */ -+#define R367_OFDM_FBERCPT4 0xF2A8 -+#define F367_OFDM_FBERMETER_CPT5 0xF2A800FF -+ -+/* FBERCPT3 */ -+#define R367_OFDM_FBERCPT3 0xF2A9 -+#define F367_OFDM_FBERMETER_CPT4 0xF2A900FF -+ -+/* FBERCPT2 */ -+#define R367_OFDM_FBERCPT2 0xF2AA -+#define F367_OFDM_FBERMETER_CPT3 0xF2AA00FF -+ -+/* FBERCPT1 */ -+#define R367_OFDM_FBERCPT1 0xF2AB -+#define F367_OFDM_FBERMETER_CPT2 0xF2AB00FF -+ -+/* FBERCPT0 */ -+#define R367_OFDM_FBERCPT0 0xF2AC -+#define F367_OFDM_FBERMETER_CPT1 0xF2AC00FF -+ -+/* FBERERR2 */ -+#define R367_OFDM_FBERERR2 0xF2AD -+#define F367_OFDM_FBERMETER_ERR_HI 0xF2AD00FF -+ -+/* FBERERR1 */ -+#define R367_OFDM_FBERERR1 0xF2AE -+#define F367_OFDM_FBERMETER_ERR_MED 0xF2AE00FF -+ -+/* FBERERR0 */ -+#define R367_OFDM_FBERERR0 0xF2AF -+#define F367_OFDM_FBERMETER_ERR_LO 0xF2AF00FF -+ -+/* FSTATESM */ -+#define R367_OFDM_FSTATESM 0xF2B0 -+#define F367_OFDM_RSTATE_F 0xF2B00080 -+#define F367_OFDM_RSTATE_E 0xF2B00040 -+#define F367_OFDM_RSTATE_D 0xF2B00020 -+#define F367_OFDM_RSTATE_C 0xF2B00010 -+#define F367_OFDM_RSTATE_B 0xF2B00008 -+#define F367_OFDM_RSTATE_A 0xF2B00004 -+#define F367_OFDM_RSTATE_9 0xF2B00002 -+#define F367_OFDM_RSTATE_8 0xF2B00001 -+ -+/* FSTATESL */ -+#define R367_OFDM_FSTATESL 0xF2B1 -+#define F367_OFDM_RSTATE_7 0xF2B10080 -+#define F367_OFDM_RSTATE_6 0xF2B10040 -+#define F367_OFDM_RSTATE_5 0xF2B10020 -+#define F367_OFDM_RSTATE_4 0xF2B10010 -+#define F367_OFDM_RSTATE_3 0xF2B10008 -+#define F367_OFDM_RSTATE_2 0xF2B10004 -+#define F367_OFDM_RSTATE_1 0xF2B10002 -+#define F367_OFDM_RSTATE_0 0xF2B10001 -+ -+/* FSPYBER */ -+#define R367_OFDM_FSPYBER 0xF2B2 -+#define F367_OFDM_FSPYBER_7 0xF2B20080 -+#define F367_OFDM_FSPYOBS_XORREAD 0xF2B20040 -+#define F367_OFDM_FSPYBER_OBSMODE 0xF2B20020 -+#define F367_OFDM_FSPYBER_SYNCBYTE 0xF2B20010 -+#define F367_OFDM_FSPYBER_UNSYNC 0xF2B20008 -+#define F367_OFDM_FSPYBER_CTIME 0xF2B20007 -+ -+/* FSPYDISTM */ -+#define R367_OFDM_FSPYDISTM 0xF2B3 -+#define F367_OFDM_PKTTIME_DISTANCE_HI 0xF2B300FF -+ -+/* FSPYDISTL */ -+#define R367_OFDM_FSPYDISTL 0xF2B4 -+#define F367_OFDM_PKTTIME_DISTANCE_LO 0xF2B400FF -+ -+/* FSPYOBS7 */ -+#define R367_OFDM_FSPYOBS7 0xF2B8 -+#define F367_OFDM_FSPYOBS_SPYFAIL 0xF2B80080 -+#define F367_OFDM_FSPYOBS_SPYFAIL1 0xF2B80040 -+#define F367_OFDM_FSPYOBS_ERROR 0xF2B80020 -+#define F367_OFDM_FSPYOBS_STROUT 0xF2B80010 -+#define F367_OFDM_FSPYOBS_RESULTSTATE1 0xF2B8000F -+ -+/* FSPYOBS6 */ -+#define R367_OFDM_FSPYOBS6 0xF2B9 -+#define F367_OFDM_FSPYOBS_RESULTSTATE0 0xF2B900F0 -+#define F367_OFDM_FSPYOBS_RESULTSTATEM1 0xF2B9000F -+ -+/* FSPYOBS5 */ -+#define R367_OFDM_FSPYOBS5 0xF2BA -+#define F367_OFDM_FSPYOBS_BYTEOFPACKET1 0xF2BA00FF -+ -+/* FSPYOBS4 */ -+#define R367_OFDM_FSPYOBS4 0xF2BB -+#define F367_OFDM_FSPYOBS_BYTEVALUE1 0xF2BB00FF -+ -+/* FSPYOBS3 */ -+#define R367_OFDM_FSPYOBS3 0xF2BC -+#define F367_OFDM_FSPYOBS_DATA1 0xF2BC00FF -+ -+/* FSPYOBS2 */ -+#define R367_OFDM_FSPYOBS2 0xF2BD -+#define F367_OFDM_FSPYOBS_DATA0 0xF2BD00FF -+ -+/* FSPYOBS1 */ -+#define R367_OFDM_FSPYOBS1 0xF2BE -+#define F367_OFDM_FSPYOBS_DATAM1 0xF2BE00FF -+ -+/* FSPYOBS0 */ -+#define R367_OFDM_FSPYOBS0 0xF2BF -+#define F367_OFDM_FSPYOBS_DATAM2 0xF2BF00FF -+ -+/* SFDEMAP */ -+#define R367_OFDM_SFDEMAP 0xF2C0 -+#define F367_OFDM_SFDEMAP_7 0xF2C00080 -+#define F367_OFDM_SFEC_K_DIVIDER_VIT 0xF2C0007F -+ -+/* SFERROR */ -+#define R367_OFDM_SFERROR 0xF2C1 -+#define F367_OFDM_SFEC_REGERR_VIT 0xF2C100FF -+ -+/* SFAVSR */ -+#define R367_OFDM_SFAVSR 0xF2C2 -+#define F367_OFDM_SFEC_SUMERRORS 0xF2C20080 -+#define F367_OFDM_SERROR_MAXMODE 0xF2C20040 -+#define F367_OFDM_SN_SFEC 0xF2C20030 -+#define F367_OFDM_KDIV_MODE_SFEC 0xF2C2000C -+#define F367_OFDM_SFAVSR_1 0xF2C20002 -+#define F367_OFDM_SFAVSR_0 0xF2C20001 -+ -+/* SFECSTATUS */ -+#define R367_OFDM_SFECSTATUS 0xF2C3 -+#define F367_OFDM_SFEC_ON 0xF2C30080 -+#define F367_OFDM_SFSTATUS_6 0xF2C30040 -+#define F367_OFDM_SFSTATUS_5 0xF2C30020 -+#define F367_OFDM_SFSTATUS_4 0xF2C30010 -+#define F367_OFDM_LOCKEDSFEC 0xF2C30008 -+#define F367_OFDM_SFEC_DELOCK 0xF2C30004 -+#define F367_OFDM_SFEC_DEMODSEL1 0xF2C30002 -+#define F367_OFDM_SFEC_OVFON 0xF2C30001 -+ -+/* SFKDIV12 */ -+#define R367_OFDM_SFKDIV12 0xF2C4 -+#define F367_OFDM_SFECKDIV12_MAN 0xF2C40080 -+#define F367_OFDM_SFEC_K_DIVIDER_12 0xF2C4007F -+ -+/* SFKDIV23 */ -+#define R367_OFDM_SFKDIV23 0xF2C5 -+#define F367_OFDM_SFECKDIV23_MAN 0xF2C50080 -+#define F367_OFDM_SFEC_K_DIVIDER_23 0xF2C5007F -+ -+/* SFKDIV34 */ -+#define R367_OFDM_SFKDIV34 0xF2C6 -+#define F367_OFDM_SFECKDIV34_MAN 0xF2C60080 -+#define F367_OFDM_SFEC_K_DIVIDER_34 0xF2C6007F -+ -+/* SFKDIV56 */ -+#define R367_OFDM_SFKDIV56 0xF2C7 -+#define F367_OFDM_SFECKDIV56_MAN 0xF2C70080 -+#define F367_OFDM_SFEC_K_DIVIDER_56 0xF2C7007F -+ -+/* SFKDIV67 */ -+#define R367_OFDM_SFKDIV67 0xF2C8 -+#define F367_OFDM_SFECKDIV67_MAN 0xF2C80080 -+#define F367_OFDM_SFEC_K_DIVIDER_67 0xF2C8007F -+ -+/* SFKDIV78 */ -+#define R367_OFDM_SFKDIV78 0xF2C9 -+#define F367_OFDM_SFECKDIV78_MAN 0xF2C90080 -+#define F367_OFDM_SFEC_K_DIVIDER_78 0xF2C9007F -+ -+/* SFDILSTKM */ -+#define R367_OFDM_SFDILSTKM 0xF2CA -+#define F367_OFDM_SFEC_PACKCPT 0xF2CA00E0 -+#define F367_OFDM_SFEC_DILSTK_HI 0xF2CA001F -+ -+/* SFDILSTKL */ -+#define R367_OFDM_SFDILSTKL 0xF2CB -+#define F367_OFDM_SFEC_DILSTK_LO 0xF2CB00FF -+ -+/* SFSTATUS */ -+#define R367_OFDM_SFSTATUS 0xF2CC -+#define F367_OFDM_SFEC_LINEOK 0xF2CC0080 -+#define F367_OFDM_SFEC_ERROR 0xF2CC0040 -+#define F367_OFDM_SFEC_DATA7 0xF2CC0020 -+#define F367_OFDM_SFEC_OVERFLOW 0xF2CC0010 -+#define F367_OFDM_SFEC_DEMODSEL2 0xF2CC0008 -+#define F367_OFDM_SFEC_NOSYNC 0xF2CC0004 -+#define F367_OFDM_SFEC_UNREGULA 0xF2CC0002 -+#define F367_OFDM_SFEC_READY 0xF2CC0001 -+ -+/* SFDLYH */ -+#define R367_OFDM_SFDLYH 0xF2CD -+#define F367_OFDM_SFEC_TSTIMEVALID 0xF2CD0080 -+#define F367_OFDM_SFEC_SPEEDUP 0xF2CD0040 -+#define F367_OFDM_SFEC_STOP 0xF2CD0020 -+#define F367_OFDM_SFEC_REGULATED 0xF2CD0010 -+#define F367_OFDM_SFEC_REALSYMBOFFSET 0xF2CD000F -+ -+/* SFDLYM */ -+#define R367_OFDM_SFDLYM 0xF2CE -+#define F367_OFDM_SFEC_REALSYMBOFFSET_HI 0xF2CE00FF -+ -+/* SFDLYL */ -+#define R367_OFDM_SFDLYL 0xF2CF -+#define F367_OFDM_SFEC_REALSYMBOFFSET_LO 0xF2CF00FF -+ -+/* SFDLYSETH */ -+#define R367_OFDM_SFDLYSETH 0xF2D0 -+#define F367_OFDM_SFEC_OFFSET 0xF2D000E0 -+#define F367_OFDM_SFECDLYSETH_4 0xF2D00010 -+#define F367_OFDM_RST_SFEC 0xF2D00008 -+#define F367_OFDM_SFECDLYSETH_2 0xF2D00004 -+#define F367_OFDM_SFEC_DISABLE 0xF2D00002 -+#define F367_OFDM_SFEC_UNREGUL 0xF2D00001 -+ -+/* SFDLYSETM */ -+#define R367_OFDM_SFDLYSETM 0xF2D1 -+#define F367_OFDM_SFECDLYSETM_7 0xF2D10080 -+#define F367_OFDM_SFEC_SYMBOFFSET_HI 0xF2D1007F -+ -+/* SFDLYSETL */ -+#define R367_OFDM_SFDLYSETL 0xF2D2 -+#define F367_OFDM_SFEC_SYMBOFFSET_LO 0xF2D200FF -+ -+/* SFOBSCFG */ -+#define R367_OFDM_SFOBSCFG 0xF2D3 -+#define F367_OFDM_SFEC_OBSCFG 0xF2D300FF -+ -+/* SFOBSM */ -+#define R367_OFDM_SFOBSM 0xF2D4 -+#define F367_OFDM_SFEC_OBSDATA_HI 0xF2D400FF -+ -+/* SFOBSL */ -+#define R367_OFDM_SFOBSL 0xF2D5 -+#define F367_OFDM_SFEC_OBSDATA_LO 0xF2D500FF -+ -+/* SFECINFO */ -+#define R367_OFDM_SFECINFO 0xF2D6 -+#define F367_OFDM_SFECINFO_7 0xF2D60080 -+#define F367_OFDM_SFEC_SYNCDLSB 0xF2D60070 -+#define F367_OFDM_SFCE_S1CPHASE 0xF2D6000F -+ -+/* SFERRCTRL */ -+#define R367_OFDM_SFERRCTRL 0xF2D8 -+#define F367_OFDM_SFEC_ERR_SOURCE 0xF2D800F0 -+#define F367_OFDM_SFERRCTRL_3 0xF2D80008 -+#define F367_OFDM_SFEC_NUM_EVENT 0xF2D80007 -+ -+/* SFERRCNTH */ -+#define R367_OFDM_SFERRCNTH 0xF2D9 -+#define F367_OFDM_SFERRC_OLDVALUE 0xF2D90080 -+#define F367_OFDM_SFEC_ERR_CNT 0xF2D9007F -+ -+/* SFERRCNTM */ -+#define R367_OFDM_SFERRCNTM 0xF2DA -+#define F367_OFDM_SFEC_ERR_CNT_HI 0xF2DA00FF -+ -+/* SFERRCNTL */ -+#define R367_OFDM_SFERRCNTL 0xF2DB -+#define F367_OFDM_SFEC_ERR_CNT_LO 0xF2DB00FF -+ -+/* SYMBRATEM */ -+#define R367_OFDM_SYMBRATEM 0xF2E0 -+#define F367_OFDM_DEFGEN_SYMBRATE_HI 0xF2E000FF -+ -+/* SYMBRATEL */ -+#define R367_OFDM_SYMBRATEL 0xF2E1 -+#define F367_OFDM_DEFGEN_SYMBRATE_LO 0xF2E100FF -+ -+/* SYMBSTATUS */ -+#define R367_OFDM_SYMBSTATUS 0xF2E2 -+#define F367_OFDM_SYMBDLINE2_OFF 0xF2E20080 -+#define F367_OFDM_SDDL_REINIT1 0xF2E20040 -+#define F367_OFDM_SDD_REINIT1 0xF2E20020 -+#define F367_OFDM_TOKENID_ERROR 0xF2E20010 -+#define F367_OFDM_SYMBRATE_OVERFLOW 0xF2E20008 -+#define F367_OFDM_SYMBRATE_UNDERFLOW 0xF2E20004 -+#define F367_OFDM_TOKENID_RSTEVENT 0xF2E20002 -+#define F367_OFDM_TOKENID_RESET1 0xF2E20001 -+ -+/* SYMBCFG */ -+#define R367_OFDM_SYMBCFG 0xF2E3 -+#define F367_OFDM_SYMBCFG_7 0xF2E30080 -+#define F367_OFDM_SYMBCFG_6 0xF2E30040 -+#define F367_OFDM_SYMBCFG_5 0xF2E30020 -+#define F367_OFDM_SYMBCFG_4 0xF2E30010 -+#define F367_OFDM_SYMRATE_FSPEED 0xF2E3000C -+#define F367_OFDM_SYMRATE_SSPEED 0xF2E30003 -+ -+/* SYMBFIFOM */ -+#define R367_OFDM_SYMBFIFOM 0xF2E4 -+#define F367_OFDM_SYMBFIFOM_7 0xF2E40080 -+#define F367_OFDM_SYMBFIFOM_6 0xF2E40040 -+#define F367_OFDM_DEFGEN_SYMFIFO_HI 0xF2E4003F -+ -+/* SYMBFIFOL */ -+#define R367_OFDM_SYMBFIFOL 0xF2E5 -+#define F367_OFDM_DEFGEN_SYMFIFO_LO 0xF2E500FF -+ -+/* SYMBOFFSM */ -+#define R367_OFDM_SYMBOFFSM 0xF2E6 -+#define F367_OFDM_TOKENID_RESET2 0xF2E60080 -+#define F367_OFDM_SDDL_REINIT2 0xF2E60040 -+#define F367_OFDM_SDD_REINIT2 0xF2E60020 -+#define F367_OFDM_SYMBOFFSM_4 0xF2E60010 -+#define F367_OFDM_SYMBOFFSM_3 0xF2E60008 -+#define F367_OFDM_DEFGEN_SYMBOFFSET_HI 0xF2E60007 -+ -+/* SYMBOFFSL */ -+#define R367_OFDM_SYMBOFFSL 0xF2E7 -+#define F367_OFDM_DEFGEN_SYMBOFFSET_LO 0xF2E700FF -+ -+/* DEBUG_LT4 */ -+#define R367_DEBUG_LT4 0xF400 -+#define F367_F_DEBUG_LT4 0xF40000FF -+ -+/* DEBUG_LT5 */ -+#define R367_DEBUG_LT5 0xF401 -+#define F367_F_DEBUG_LT5 0xF40100FF -+ -+/* DEBUG_LT6 */ -+#define R367_DEBUG_LT6 0xF402 -+#define F367_F_DEBUG_LT6 0xF40200FF -+ -+/* DEBUG_LT7 */ -+#define R367_DEBUG_LT7 0xF403 -+#define F367_F_DEBUG_LT7 0xF40300FF -+ -+/* DEBUG_LT8 */ -+#define R367_DEBUG_LT8 0xF404 -+#define F367_F_DEBUG_LT8 0xF40400FF -+ -+/* DEBUG_LT9 */ -+#define R367_DEBUG_LT9 0xF405 -+#define F367_F_DEBUG_LT9 0xF40500FF -+ -+/* CTRL_1 */ -+#define R367_QAM_CTRL_1 0xF402 -+#define F367_QAM_SOFT_RST 0xF4020080 -+#define F367_QAM_EQU_RST 0xF4020008 -+#define F367_QAM_CRL_RST 0xF4020004 -+#define F367_QAM_TRL_RST 0xF4020002 -+#define F367_QAM_AGC_RST 0xF4020001 -+ -+/* CTRL_2 */ -+#define R367_QAM_CTRL_2 0xF403 -+#define F367_QAM_DEINT_RST 0xF4030008 -+#define F367_QAM_RS_RST 0xF4030004 -+ -+/* IT_STATUS1 */ -+#define R367_QAM_IT_STATUS1 0xF408 -+#define F367_QAM_SWEEP_OUT 0xF4080080 -+#define F367_QAM_FSM_CRL 0xF4080040 -+#define F367_QAM_CRL_LOCK 0xF4080020 -+#define F367_QAM_MFSM 0xF4080010 -+#define F367_QAM_TRL_LOCK 0xF4080008 -+#define F367_QAM_TRL_AGC_LIMIT 0xF4080004 -+#define F367_QAM_ADJ_AGC_LOCK 0xF4080002 -+#define F367_QAM_AGC_QAM_LOCK 0xF4080001 -+ -+/* IT_STATUS2 */ -+#define R367_QAM_IT_STATUS2 0xF409 -+#define F367_QAM_TSMF_CNT 0xF4090080 -+#define F367_QAM_TSMF_EOF 0xF4090040 -+#define F367_QAM_TSMF_RDY 0xF4090020 -+#define F367_QAM_FEC_NOCORR 0xF4090010 -+#define F367_QAM_SYNCSTATE 0xF4090008 -+#define F367_QAM_DEINT_LOCK 0xF4090004 -+#define F367_QAM_FADDING_FRZ 0xF4090002 -+#define F367_QAM_TAPMON_ALARM 0xF4090001 -+ -+/* IT_EN1 */ -+#define R367_QAM_IT_EN1 0xF40A -+#define F367_QAM_SWEEP_OUTE 0xF40A0080 -+#define F367_QAM_FSM_CRLE 0xF40A0040 -+#define F367_QAM_CRL_LOCKE 0xF40A0020 -+#define F367_QAM_MFSME 0xF40A0010 -+#define F367_QAM_TRL_LOCKE 0xF40A0008 -+#define F367_QAM_TRL_AGC_LIMITE 0xF40A0004 -+#define F367_QAM_ADJ_AGC_LOCKE 0xF40A0002 -+#define F367_QAM_AGC_LOCKE 0xF40A0001 -+ -+/* IT_EN2 */ -+#define R367_QAM_IT_EN2 0xF40B -+#define F367_QAM_TSMF_CNTE 0xF40B0080 -+#define F367_QAM_TSMF_EOFE 0xF40B0040 -+#define F367_QAM_TSMF_RDYE 0xF40B0020 -+#define F367_QAM_FEC_NOCORRE 0xF40B0010 -+#define F367_QAM_SYNCSTATEE 0xF40B0008 -+#define F367_QAM_DEINT_LOCKE 0xF40B0004 -+#define F367_QAM_FADDING_FRZE 0xF40B0002 -+#define F367_QAM_TAPMON_ALARME 0xF40B0001 -+ -+/* CTRL_STATUS */ -+#define R367_QAM_CTRL_STATUS 0xF40C -+#define F367_QAM_QAMFEC_LOCK 0xF40C0004 -+#define F367_QAM_TSMF_LOCK 0xF40C0002 -+#define F367_QAM_TSMF_ERROR 0xF40C0001 -+ -+/* TEST_CTL */ -+#define R367_QAM_TEST_CTL 0xF40F -+#define F367_QAM_TST_BLK_SEL 0xF40F0060 -+#define F367_QAM_TST_BUS_SEL 0xF40F001F -+ -+/* AGC_CTL */ -+#define R367_QAM_AGC_CTL 0xF410 -+#define F367_QAM_AGC_LCK_TH 0xF41000F0 -+#define F367_QAM_AGC_ACCUMRSTSEL 0xF4100007 -+ -+/* AGC_IF_CFG */ -+#define R367_QAM_AGC_IF_CFG 0xF411 -+#define F367_QAM_AGC_IF_BWSEL 0xF41100F0 -+#define F367_QAM_AGC_IF_FREEZE 0xF4110002 -+ -+/* AGC_RF_CFG */ -+#define R367_QAM_AGC_RF_CFG 0xF412 -+#define F367_QAM_AGC_RF_BWSEL 0xF4120070 -+#define F367_QAM_AGC_RF_FREEZE 0xF4120002 -+ -+/* AGC_PWM_CFG */ -+#define R367_QAM_AGC_PWM_CFG 0xF413 -+#define F367_QAM_AGC_RF_PWM_TST 0xF4130080 -+#define F367_QAM_AGC_RF_PWM_INV 0xF4130040 -+#define F367_QAM_AGC_IF_PWM_TST 0xF4130008 -+#define F367_QAM_AGC_IF_PWM_INV 0xF4130004 -+#define F367_QAM_AGC_PWM_CLKDIV 0xF4130003 -+ -+/* AGC_PWR_REF_L */ -+#define R367_QAM_AGC_PWR_REF_L 0xF414 -+#define F367_QAM_AGC_PWRREF_LO 0xF41400FF -+ -+/* AGC_PWR_REF_H */ -+#define R367_QAM_AGC_PWR_REF_H 0xF415 -+#define F367_QAM_AGC_PWRREF_HI 0xF4150003 -+ -+/* AGC_RF_TH_L */ -+#define R367_QAM_AGC_RF_TH_L 0xF416 -+#define F367_QAM_AGC_RF_TH_LO 0xF41600FF -+ -+/* AGC_RF_TH_H */ -+#define R367_QAM_AGC_RF_TH_H 0xF417 -+#define F367_QAM_AGC_RF_TH_HI 0xF417000F -+ -+/* AGC_IF_LTH_L */ -+#define R367_QAM_AGC_IF_LTH_L 0xF418 -+#define F367_QAM_AGC_IF_THLO_LO 0xF41800FF -+ -+/* AGC_IF_LTH_H */ -+#define R367_QAM_AGC_IF_LTH_H 0xF419 -+#define F367_QAM_AGC_IF_THLO_HI 0xF419000F -+ -+/* AGC_IF_HTH_L */ -+#define R367_QAM_AGC_IF_HTH_L 0xF41A -+#define F367_QAM_AGC_IF_THHI_LO 0xF41A00FF -+ -+/* AGC_IF_HTH_H */ -+#define R367_QAM_AGC_IF_HTH_H 0xF41B -+#define F367_QAM_AGC_IF_THHI_HI 0xF41B000F -+ -+/* AGC_PWR_RD_L */ -+#define R367_QAM_AGC_PWR_RD_L 0xF41C -+#define F367_QAM_AGC_PWR_WORD_LO 0xF41C00FF -+ -+/* AGC_PWR_RD_M */ -+#define R367_QAM_AGC_PWR_RD_M 0xF41D -+#define F367_QAM_AGC_PWR_WORD_ME 0xF41D00FF -+ -+/* AGC_PWR_RD_H */ -+#define R367_QAM_AGC_PWR_RD_H 0xF41E -+#define F367_QAM_AGC_PWR_WORD_HI 0xF41E0003 -+ -+/* AGC_PWM_IFCMD_L */ -+#define R367_QAM_AGC_PWM_IFCMD_L 0xF420 -+#define F367_QAM_AGC_IF_PWMCMD_LO 0xF42000FF -+ -+/* AGC_PWM_IFCMD_H */ -+#define R367_QAM_AGC_PWM_IFCMD_H 0xF421 -+#define F367_QAM_AGC_IF_PWMCMD_HI 0xF421000F -+ -+/* AGC_PWM_RFCMD_L */ -+#define R367_QAM_AGC_PWM_RFCMD_L 0xF422 -+#define F367_QAM_AGC_RF_PWMCMD_LO 0xF42200FF -+ -+/* AGC_PWM_RFCMD_H */ -+#define R367_QAM_AGC_PWM_RFCMD_H 0xF423 -+#define F367_QAM_AGC_RF_PWMCMD_HI 0xF423000F -+ -+/* IQDEM_CFG */ -+#define R367_QAM_IQDEM_CFG 0xF424 -+#define F367_QAM_IQDEM_CLK_SEL 0xF4240004 -+#define F367_QAM_IQDEM_INVIQ 0xF4240002 -+#define F367_QAM_IQDEM_A2DTYPE 0xF4240001 -+ -+/* MIX_NCO_LL */ -+#define R367_QAM_MIX_NCO_LL 0xF425 -+#define F367_QAM_MIX_NCO_INC_LL 0xF42500FF -+ -+/* MIX_NCO_HL */ -+#define R367_QAM_MIX_NCO_HL 0xF426 -+#define F367_QAM_MIX_NCO_INC_HL 0xF42600FF -+ -+/* MIX_NCO_HH */ -+#define R367_QAM_MIX_NCO_HH 0xF427 -+#define F367_QAM_MIX_NCO_INVCNST 0xF4270080 -+#define F367_QAM_MIX_NCO_INC_HH 0xF427007F -+ -+/* SRC_NCO_LL */ -+#define R367_QAM_SRC_NCO_LL 0xF428 -+#define F367_QAM_SRC_NCO_INC_LL 0xF42800FF -+ -+/* SRC_NCO_LH */ -+#define R367_QAM_SRC_NCO_LH 0xF429 -+#define F367_QAM_SRC_NCO_INC_LH 0xF42900FF -+ -+/* SRC_NCO_HL */ -+#define R367_QAM_SRC_NCO_HL 0xF42A -+#define F367_QAM_SRC_NCO_INC_HL 0xF42A00FF -+ -+/* SRC_NCO_HH */ -+#define R367_QAM_SRC_NCO_HH 0xF42B -+#define F367_QAM_SRC_NCO_INC_HH 0xF42B007F -+ -+/* IQDEM_GAIN_SRC_L */ -+#define R367_QAM_IQDEM_GAIN_SRC_L 0xF42C -+#define F367_QAM_GAIN_SRC_LO 0xF42C00FF -+ -+/* IQDEM_GAIN_SRC_H */ -+#define R367_QAM_IQDEM_GAIN_SRC_H 0xF42D -+#define F367_QAM_GAIN_SRC_HI 0xF42D0003 -+ -+/* IQDEM_DCRM_CFG_LL */ -+#define R367_QAM_IQDEM_DCRM_CFG_LL 0xF430 -+#define F367_QAM_DCRM0_DCIN_L 0xF43000FF -+ -+/* IQDEM_DCRM_CFG_LH */ -+#define R367_QAM_IQDEM_DCRM_CFG_LH 0xF431 -+#define F367_QAM_DCRM1_I_DCIN_L 0xF43100FC -+#define F367_QAM_DCRM0_DCIN_H 0xF4310003 -+ -+/* IQDEM_DCRM_CFG_HL */ -+#define R367_QAM_IQDEM_DCRM_CFG_HL 0xF432 -+#define F367_QAM_DCRM1_Q_DCIN_L 0xF43200F0 -+#define F367_QAM_DCRM1_I_DCIN_H 0xF432000F -+ -+/* IQDEM_DCRM_CFG_HH */ -+#define R367_QAM_IQDEM_DCRM_CFG_HH 0xF433 -+#define F367_QAM_DCRM1_FRZ 0xF4330080 -+#define F367_QAM_DCRM0_FRZ 0xF4330040 -+#define F367_QAM_DCRM1_Q_DCIN_H 0xF433003F -+ -+/* IQDEM_ADJ_COEFF0 */ -+#define R367_QAM_IQDEM_ADJ_COEFF0 0xF434 -+#define F367_QAM_ADJIIR_COEFF10_L 0xF43400FF -+ -+/* IQDEM_ADJ_COEFF1 */ -+#define R367_QAM_IQDEM_ADJ_COEFF1 0xF435 -+#define F367_QAM_ADJIIR_COEFF11_L 0xF43500FC -+#define F367_QAM_ADJIIR_COEFF10_H 0xF4350003 -+ -+/* IQDEM_ADJ_COEFF2 */ -+#define R367_QAM_IQDEM_ADJ_COEFF2 0xF436 -+#define F367_QAM_ADJIIR_COEFF12_L 0xF43600F0 -+#define F367_QAM_ADJIIR_COEFF11_H 0xF436000F -+ -+/* IQDEM_ADJ_COEFF3 */ -+#define R367_QAM_IQDEM_ADJ_COEFF3 0xF437 -+#define F367_QAM_ADJIIR_COEFF20_L 0xF43700C0 -+#define F367_QAM_ADJIIR_COEFF12_H 0xF437003F -+ -+/* IQDEM_ADJ_COEFF4 */ -+#define R367_QAM_IQDEM_ADJ_COEFF4 0xF438 -+#define F367_QAM_ADJIIR_COEFF20_H 0xF43800FF -+ -+/* IQDEM_ADJ_COEFF5 */ -+#define R367_QAM_IQDEM_ADJ_COEFF5 0xF439 -+#define F367_QAM_ADJIIR_COEFF21_L 0xF43900FF -+ -+/* IQDEM_ADJ_COEFF6 */ -+#define R367_QAM_IQDEM_ADJ_COEFF6 0xF43A -+#define F367_QAM_ADJIIR_COEFF22_L 0xF43A00FC -+#define F367_QAM_ADJIIR_COEFF21_H 0xF43A0003 -+ -+/* IQDEM_ADJ_COEFF7 */ -+#define R367_QAM_IQDEM_ADJ_COEFF7 0xF43B -+#define F367_QAM_ADJIIR_COEFF22_H 0xF43B000F -+ -+/* IQDEM_ADJ_EN */ -+#define R367_QAM_IQDEM_ADJ_EN 0xF43C -+#define F367_QAM_ALLPASSFILT_EN 0xF43C0008 -+#define F367_QAM_ADJ_AGC_EN 0xF43C0004 -+#define F367_QAM_ADJ_COEFF_FRZ 0xF43C0002 -+#define F367_QAM_ADJ_EN 0xF43C0001 -+ -+/* IQDEM_ADJ_AGC_REF */ -+#define R367_QAM_IQDEM_ADJ_AGC_REF 0xF43D -+#define F367_QAM_ADJ_AGC_REF 0xF43D00FF -+ -+/* ALLPASSFILT1 */ -+#define R367_QAM_ALLPASSFILT1 0xF440 -+#define F367_QAM_ALLPASSFILT_COEFF1_LO 0xF44000FF -+ -+/* ALLPASSFILT2 */ -+#define R367_QAM_ALLPASSFILT2 0xF441 -+#define F367_QAM_ALLPASSFILT_COEFF1_ME 0xF44100FF -+ -+/* ALLPASSFILT3 */ -+#define R367_QAM_ALLPASSFILT3 0xF442 -+#define F367_QAM_ALLPASSFILT_COEFF2_LO 0xF44200C0 -+#define F367_QAM_ALLPASSFILT_COEFF1_HI 0xF442003F -+ -+/* ALLPASSFILT4 */ -+#define R367_QAM_ALLPASSFILT4 0xF443 -+#define F367_QAM_ALLPASSFILT_COEFF2_MEL 0xF44300FF -+ -+/* ALLPASSFILT5 */ -+#define R367_QAM_ALLPASSFILT5 0xF444 -+#define F367_QAM_ALLPASSFILT_COEFF2_MEH 0xF44400FF -+ -+/* ALLPASSFILT6 */ -+#define R367_QAM_ALLPASSFILT6 0xF445 -+#define F367_QAM_ALLPASSFILT_COEFF3_LO 0xF44500F0 -+#define F367_QAM_ALLPASSFILT_COEFF2_HI 0xF445000F -+ -+/* ALLPASSFILT7 */ -+#define R367_QAM_ALLPASSFILT7 0xF446 -+#define F367_QAM_ALLPASSFILT_COEFF3_MEL 0xF44600FF -+ -+/* ALLPASSFILT8 */ -+#define R367_QAM_ALLPASSFILT8 0xF447 -+#define F367_QAM_ALLPASSFILT_COEFF3_MEH 0xF44700FF -+ -+/* ALLPASSFILT9 */ -+#define R367_QAM_ALLPASSFILT9 0xF448 -+#define F367_QAM_ALLPASSFILT_COEFF4_LO 0xF44800FC -+#define F367_QAM_ALLPASSFILT_COEFF3_HI 0xF4480003 -+ -+/* ALLPASSFILT10 */ -+#define R367_QAM_ALLPASSFILT10 0xF449 -+#define F367_QAM_ALLPASSFILT_COEFF4_ME 0xF44900FF -+ -+/* ALLPASSFILT11 */ -+#define R367_QAM_ALLPASSFILT11 0xF44A -+#define F367_QAM_ALLPASSFILT_COEFF4_HI 0xF44A00FF -+ -+/* TRL_AGC_CFG */ -+#define R367_QAM_TRL_AGC_CFG 0xF450 -+#define F367_QAM_TRL_AGC_FREEZE 0xF4500080 -+#define F367_QAM_TRL_AGC_REF 0xF450007F -+ -+/* TRL_LPF_CFG */ -+#define R367_QAM_TRL_LPF_CFG 0xF454 -+#define F367_QAM_NYQPOINT_INV 0xF4540040 -+#define F367_QAM_TRL_SHIFT 0xF4540030 -+#define F367_QAM_NYQ_COEFF_SEL 0xF454000C -+#define F367_QAM_TRL_LPF_FREEZE 0xF4540002 -+#define F367_QAM_TRL_LPF_CRT 0xF4540001 -+ -+/* TRL_LPF_ACQ_GAIN */ -+#define R367_QAM_TRL_LPF_ACQ_GAIN 0xF455 -+#define F367_QAM_TRL_GDIR_ACQ 0xF4550070 -+#define F367_QAM_TRL_GINT_ACQ 0xF4550007 -+ -+/* TRL_LPF_TRK_GAIN */ -+#define R367_QAM_TRL_LPF_TRK_GAIN 0xF456 -+#define F367_QAM_TRL_GDIR_TRK 0xF4560070 -+#define F367_QAM_TRL_GINT_TRK 0xF4560007 -+ -+/* TRL_LPF_OUT_GAIN */ -+#define R367_QAM_TRL_LPF_OUT_GAIN 0xF457 -+#define F367_QAM_TRL_GAIN_OUT 0xF4570007 -+ -+/* TRL_LOCKDET_LTH */ -+#define R367_QAM_TRL_LOCKDET_LTH 0xF458 -+#define F367_QAM_TRL_LCK_THLO 0xF4580007 -+ -+/* TRL_LOCKDET_HTH */ -+#define R367_QAM_TRL_LOCKDET_HTH 0xF459 -+#define F367_QAM_TRL_LCK_THHI 0xF45900FF -+ -+/* TRL_LOCKDET_TRGVAL */ -+#define R367_QAM_TRL_LOCKDET_TRGVAL 0xF45A -+#define F367_QAM_TRL_LCK_TRG 0xF45A00FF -+ -+/* IQ_QAM */ -+#define R367_QAM_IQ_QAM 0xF45C -+#define F367_QAM_IQ_INPUT 0xF45C0008 -+#define F367_QAM_DETECT_MODE 0xF45C0007 -+ -+/* FSM_STATE */ -+#define R367_QAM_FSM_STATE 0xF460 -+#define F367_QAM_CRL_DFE 0xF4600080 -+#define F367_QAM_DFE_START 0xF4600040 -+#define F367_QAM_CTRLG_START 0xF4600030 -+#define F367_QAM_FSM_FORCESTATE 0xF460000F -+ -+/* FSM_CTL */ -+#define R367_QAM_FSM_CTL 0xF461 -+#define F367_QAM_FEC2_EN 0xF4610040 -+#define F367_QAM_SIT_EN 0xF4610020 -+#define F367_QAM_TRL_AHEAD 0xF4610010 -+#define F367_QAM_TRL2_EN 0xF4610008 -+#define F367_QAM_FSM_EQA1_EN 0xF4610004 -+#define F367_QAM_FSM_BKP_DIS 0xF4610002 -+#define F367_QAM_FSM_FORCE_EN 0xF4610001 -+ -+/* FSM_STS */ -+#define R367_QAM_FSM_STS 0xF462 -+#define F367_QAM_FSM_STATUS 0xF462000F -+ -+/* FSM_SNR0_HTH */ -+#define R367_QAM_FSM_SNR0_HTH 0xF463 -+#define F367_QAM_SNR0_HTH 0xF46300FF -+ -+/* FSM_SNR1_HTH */ -+#define R367_QAM_FSM_SNR1_HTH 0xF464 -+#define F367_QAM_SNR1_HTH 0xF46400FF -+ -+/* FSM_SNR2_HTH */ -+#define R367_QAM_FSM_SNR2_HTH 0xF465 -+#define F367_QAM_SNR2_HTH 0xF46500FF -+ -+/* FSM_SNR0_LTH */ -+#define R367_QAM_FSM_SNR0_LTH 0xF466 -+#define F367_QAM_SNR0_LTH 0xF46600FF -+ -+/* FSM_SNR1_LTH */ -+#define R367_QAM_FSM_SNR1_LTH 0xF467 -+#define F367_QAM_SNR1_LTH 0xF46700FF -+ -+/* FSM_EQA1_HTH */ -+#define R367_QAM_FSM_EQA1_HTH 0xF468 -+#define F367_QAM_SNR3_HTH_LO 0xF46800F0 -+#define F367_QAM_EQA1_HTH 0xF468000F -+ -+/* FSM_TEMPO */ -+#define R367_QAM_FSM_TEMPO 0xF469 -+#define F367_QAM_SIT 0xF46900C0 -+#define F367_QAM_WST 0xF4690038 -+#define F367_QAM_ELT 0xF4690006 -+#define F367_QAM_SNR3_HTH_HI 0xF4690001 -+ -+/* FSM_CONFIG */ -+#define R367_QAM_FSM_CONFIG 0xF46A -+#define F367_QAM_FEC2_DFEOFF 0xF46A0004 -+#define F367_QAM_PRIT_STATE 0xF46A0002 -+#define F367_QAM_MODMAP_STATE 0xF46A0001 -+ -+/* EQU_I_TESTTAP_L */ -+#define R367_QAM_EQU_I_TESTTAP_L 0xF474 -+#define F367_QAM_I_TEST_TAP_L 0xF47400FF -+ -+/* EQU_I_TESTTAP_M */ -+#define R367_QAM_EQU_I_TESTTAP_M 0xF475 -+#define F367_QAM_I_TEST_TAP_M 0xF47500FF -+ -+/* EQU_I_TESTTAP_H */ -+#define R367_QAM_EQU_I_TESTTAP_H 0xF476 -+#define F367_QAM_I_TEST_TAP_H 0xF476001F -+ -+/* EQU_TESTAP_CFG */ -+#define R367_QAM_EQU_TESTAP_CFG 0xF477 -+#define F367_QAM_TEST_FFE_DFE_SEL 0xF4770040 -+#define F367_QAM_TEST_TAP_SELECT 0xF477003F -+ -+/* EQU_Q_TESTTAP_L */ -+#define R367_QAM_EQU_Q_TESTTAP_L 0xF478 -+#define F367_QAM_Q_TEST_TAP_L 0xF47800FF -+ -+/* EQU_Q_TESTTAP_M */ -+#define R367_QAM_EQU_Q_TESTTAP_M 0xF479 -+#define F367_QAM_Q_TEST_TAP_M 0xF47900FF -+ -+/* EQU_Q_TESTTAP_H */ -+#define R367_QAM_EQU_Q_TESTTAP_H 0xF47A -+#define F367_QAM_Q_TEST_TAP_H 0xF47A001F -+ -+/* EQU_TAP_CTRL */ -+#define R367_QAM_EQU_TAP_CTRL 0xF47B -+#define F367_QAM_MTAP_FRZ 0xF47B0010 -+#define F367_QAM_PRE_FREEZE 0xF47B0008 -+#define F367_QAM_DFE_TAPMON_EN 0xF47B0004 -+#define F367_QAM_FFE_TAPMON_EN 0xF47B0002 -+#define F367_QAM_MTAP_ONLY 0xF47B0001 -+ -+/* EQU_CTR_CRL_CONTROL_L */ -+#define R367_QAM_EQU_CTR_CRL_CONTROL_L 0xF47C -+#define F367_QAM_EQU_CTR_CRL_CONTROL_LO 0xF47C00FF -+ -+/* EQU_CTR_CRL_CONTROL_H */ -+#define R367_QAM_EQU_CTR_CRL_CONTROL_H 0xF47D -+#define F367_QAM_EQU_CTR_CRL_CONTROL_HI 0xF47D00FF -+ -+/* EQU_CTR_HIPOW_L */ -+#define R367_QAM_EQU_CTR_HIPOW_L 0xF47E -+#define F367_QAM_CTR_HIPOW_L 0xF47E00FF -+ -+/* EQU_CTR_HIPOW_H */ -+#define R367_QAM_EQU_CTR_HIPOW_H 0xF47F -+#define F367_QAM_CTR_HIPOW_H 0xF47F00FF -+ -+/* EQU_I_EQU_LO */ -+#define R367_QAM_EQU_I_EQU_LO 0xF480 -+#define F367_QAM_EQU_I_EQU_L 0xF48000FF -+ -+/* EQU_I_EQU_HI */ -+#define R367_QAM_EQU_I_EQU_HI 0xF481 -+#define F367_QAM_EQU_I_EQU_H 0xF4810003 -+ -+/* EQU_Q_EQU_LO */ -+#define R367_QAM_EQU_Q_EQU_LO 0xF482 -+#define F367_QAM_EQU_Q_EQU_L 0xF48200FF -+ -+/* EQU_Q_EQU_HI */ -+#define R367_QAM_EQU_Q_EQU_HI 0xF483 -+#define F367_QAM_EQU_Q_EQU_H 0xF4830003 -+ -+/* EQU_MAPPER */ -+#define R367_QAM_EQU_MAPPER 0xF484 -+#define F367_QAM_QUAD_AUTO 0xF4840080 -+#define F367_QAM_QUAD_INV 0xF4840040 -+#define F367_QAM_QAM_MODE 0xF4840007 -+ -+/* EQU_SWEEP_RATE */ -+#define R367_QAM_EQU_SWEEP_RATE 0xF485 -+#define F367_QAM_SNR_PER 0xF48500C0 -+#define F367_QAM_SWEEP_RATE 0xF485003F -+ -+/* EQU_SNR_LO */ -+#define R367_QAM_EQU_SNR_LO 0xF486 -+#define F367_QAM_SNR_LO 0xF48600FF -+ -+/* EQU_SNR_HI */ -+#define R367_QAM_EQU_SNR_HI 0xF487 -+#define F367_QAM_SNR_HI 0xF48700FF -+ -+/* EQU_GAMMA_LO */ -+#define R367_QAM_EQU_GAMMA_LO 0xF488 -+#define F367_QAM_GAMMA_LO 0xF48800FF -+ -+/* EQU_GAMMA_HI */ -+#define R367_QAM_EQU_GAMMA_HI 0xF489 -+#define F367_QAM_GAMMA_ME 0xF48900FF -+ -+/* EQU_ERR_GAIN */ -+#define R367_QAM_EQU_ERR_GAIN 0xF48A -+#define F367_QAM_EQA1MU 0xF48A0070 -+#define F367_QAM_CRL2MU 0xF48A000E -+#define F367_QAM_GAMMA_HI 0xF48A0001 -+ -+/* EQU_RADIUS */ -+#define R367_QAM_EQU_RADIUS 0xF48B -+#define F367_QAM_RADIUS 0xF48B00FF -+ -+/* EQU_FFE_MAINTAP */ -+#define R367_QAM_EQU_FFE_MAINTAP 0xF48C -+#define F367_QAM_FFE_MAINTAP_INIT 0xF48C00FF -+ -+/* EQU_FFE_LEAKAGE */ -+#define R367_QAM_EQU_FFE_LEAKAGE 0xF48E -+#define F367_QAM_LEAK_PER 0xF48E00F0 -+#define F367_QAM_EQU_OUTSEL 0xF48E0002 -+#define F367_QAM_PNT2DFE 0xF48E0001 -+ -+/* EQU_FFE_MAINTAP_POS */ -+#define R367_QAM_EQU_FFE_MAINTAP_POS 0xF48F -+#define F367_QAM_FFE_LEAK_EN 0xF48F0080 -+#define F367_QAM_DFE_LEAK_EN 0xF48F0040 -+#define F367_QAM_FFE_MAINTAP_POS 0xF48F003F -+ -+/* EQU_GAIN_WIDE */ -+#define R367_QAM_EQU_GAIN_WIDE 0xF490 -+#define F367_QAM_DFE_GAIN_WIDE 0xF49000F0 -+#define F367_QAM_FFE_GAIN_WIDE 0xF490000F -+ -+/* EQU_GAIN_NARROW */ -+#define R367_QAM_EQU_GAIN_NARROW 0xF491 -+#define F367_QAM_DFE_GAIN_NARROW 0xF49100F0 -+#define F367_QAM_FFE_GAIN_NARROW 0xF491000F -+ -+/* EQU_CTR_LPF_GAIN */ -+#define R367_QAM_EQU_CTR_LPF_GAIN 0xF492 -+#define F367_QAM_CTR_GTO 0xF4920080 -+#define F367_QAM_CTR_GDIR 0xF4920070 -+#define F367_QAM_SWEEP_EN 0xF4920008 -+#define F367_QAM_CTR_GINT 0xF4920007 -+ -+/* EQU_CRL_LPF_GAIN */ -+#define R367_QAM_EQU_CRL_LPF_GAIN 0xF493 -+#define F367_QAM_CRL_GTO 0xF4930080 -+#define F367_QAM_CRL_GDIR 0xF4930070 -+#define F367_QAM_SWEEP_DIR 0xF4930008 -+#define F367_QAM_CRL_GINT 0xF4930007 -+ -+/* EQU_GLOBAL_GAIN */ -+#define R367_QAM_EQU_GLOBAL_GAIN 0xF494 -+#define F367_QAM_CRL_GAIN 0xF49400F8 -+#define F367_QAM_CTR_INC_GAIN 0xF4940004 -+#define F367_QAM_CTR_FRAC 0xF4940003 -+ -+/* EQU_CRL_LD_SEN */ -+#define R367_QAM_EQU_CRL_LD_SEN 0xF495 -+#define F367_QAM_CTR_BADPOINT_EN 0xF4950080 -+#define F367_QAM_CTR_GAIN 0xF4950070 -+#define F367_QAM_LIMANEN 0xF4950008 -+#define F367_QAM_CRL_LD_SEN 0xF4950007 -+ -+/* EQU_CRL_LD_VAL */ -+#define R367_QAM_EQU_CRL_LD_VAL 0xF496 -+#define F367_QAM_CRL_BISTH_LIMIT 0xF4960080 -+#define F367_QAM_CARE_EN 0xF4960040 -+#define F367_QAM_CRL_LD_PER 0xF4960030 -+#define F367_QAM_CRL_LD_WST 0xF496000C -+#define F367_QAM_CRL_LD_TFS 0xF4960003 -+ -+/* EQU_CRL_TFR */ -+#define R367_QAM_EQU_CRL_TFR 0xF497 -+#define F367_QAM_CRL_LD_TFR 0xF49700FF -+ -+/* EQU_CRL_BISTH_LO */ -+#define R367_QAM_EQU_CRL_BISTH_LO 0xF498 -+#define F367_QAM_CRL_BISTH_LO 0xF49800FF -+ -+/* EQU_CRL_BISTH_HI */ -+#define R367_QAM_EQU_CRL_BISTH_HI 0xF499 -+#define F367_QAM_CRL_BISTH_HI 0xF49900FF -+ -+/* EQU_SWEEP_RANGE_LO */ -+#define R367_QAM_EQU_SWEEP_RANGE_LO 0xF49A -+#define F367_QAM_SWEEP_RANGE_LO 0xF49A00FF -+ -+/* EQU_SWEEP_RANGE_HI */ -+#define R367_QAM_EQU_SWEEP_RANGE_HI 0xF49B -+#define F367_QAM_SWEEP_RANGE_HI 0xF49B00FF -+ -+/* EQU_CRL_LIMITER */ -+#define R367_QAM_EQU_CRL_LIMITER 0xF49C -+#define F367_QAM_BISECTOR_EN 0xF49C0080 -+#define F367_QAM_PHEST128_EN 0xF49C0040 -+#define F367_QAM_CRL_LIM 0xF49C003F -+ -+/* EQU_MODULUS_MAP */ -+#define R367_QAM_EQU_MODULUS_MAP 0xF49D -+#define F367_QAM_PNT_DEPTH 0xF49D00E0 -+#define F367_QAM_MODULUS_CMP 0xF49D001F -+ -+/* EQU_PNT_GAIN */ -+#define R367_QAM_EQU_PNT_GAIN 0xF49E -+#define F367_QAM_PNT_EN 0xF49E0080 -+#define F367_QAM_MODULUSMAP_EN 0xF49E0040 -+#define F367_QAM_PNT_GAIN 0xF49E003F -+ -+/* FEC_AC_CTR_0 */ -+#define R367_QAM_FEC_AC_CTR_0 0xF4A8 -+#define F367_QAM_BE_BYPASS 0xF4A80020 -+#define F367_QAM_REFRESH47 0xF4A80010 -+#define F367_QAM_CT_NBST 0xF4A80008 -+#define F367_QAM_TEI_ENA 0xF4A80004 -+#define F367_QAM_DS_ENA 0xF4A80002 -+#define F367_QAM_TSMF_EN 0xF4A80001 -+ -+/* FEC_AC_CTR_1 */ -+#define R367_QAM_FEC_AC_CTR_1 0xF4A9 -+#define F367_QAM_DEINT_DEPTH 0xF4A900FF -+ -+/* FEC_AC_CTR_2 */ -+#define R367_QAM_FEC_AC_CTR_2 0xF4AA -+#define F367_QAM_DEINT_M 0xF4AA00F8 -+#define F367_QAM_DIS_UNLOCK 0xF4AA0004 -+#define F367_QAM_DESCR_MODE 0xF4AA0003 -+ -+/* FEC_AC_CTR_3 */ -+#define R367_QAM_FEC_AC_CTR_3 0xF4AB -+#define F367_QAM_DI_UNLOCK 0xF4AB0080 -+#define F367_QAM_DI_FREEZE 0xF4AB0040 -+#define F367_QAM_MISMATCH 0xF4AB0030 -+#define F367_QAM_ACQ_MODE 0xF4AB000C -+#define F367_QAM_TRK_MODE 0xF4AB0003 -+ -+/* FEC_STATUS */ -+#define R367_QAM_FEC_STATUS 0xF4AC -+#define F367_QAM_DEINT_SMCNTR 0xF4AC00E0 -+#define F367_QAM_DEINT_SYNCSTATE 0xF4AC0018 -+#define F367_QAM_DEINT_SYNLOST 0xF4AC0004 -+#define F367_QAM_DESCR_SYNCSTATE 0xF4AC0002 -+ -+/* RS_COUNTER_0 */ -+#define R367_QAM_RS_COUNTER_0 0xF4AE -+#define F367_QAM_BK_CT_L 0xF4AE00FF -+ -+/* RS_COUNTER_1 */ -+#define R367_QAM_RS_COUNTER_1 0xF4AF -+#define F367_QAM_BK_CT_H 0xF4AF00FF -+ -+/* RS_COUNTER_2 */ -+#define R367_QAM_RS_COUNTER_2 0xF4B0 -+#define F367_QAM_CORR_CT_L 0xF4B000FF -+ -+/* RS_COUNTER_3 */ -+#define R367_QAM_RS_COUNTER_3 0xF4B1 -+#define F367_QAM_CORR_CT_H 0xF4B100FF -+ -+/* RS_COUNTER_4 */ -+#define R367_QAM_RS_COUNTER_4 0xF4B2 -+#define F367_QAM_UNCORR_CT_L 0xF4B200FF -+ -+/* RS_COUNTER_5 */ -+#define R367_QAM_RS_COUNTER_5 0xF4B3 -+#define F367_QAM_UNCORR_CT_H 0xF4B300FF -+ -+/* BERT_0 */ -+#define R367_QAM_BERT_0 0xF4B4 -+#define F367_QAM_RS_NOCORR 0xF4B40004 -+#define F367_QAM_CT_HOLD 0xF4B40002 -+#define F367_QAM_CT_CLEAR 0xF4B40001 -+ -+/* BERT_1 */ -+#define R367_QAM_BERT_1 0xF4B5 -+#define F367_QAM_BERT_ON 0xF4B50020 -+#define F367_QAM_BERT_ERR_SRC 0xF4B50010 -+#define F367_QAM_BERT_ERR_MODE 0xF4B50008 -+#define F367_QAM_BERT_NBYTE 0xF4B50007 -+ -+/* BERT_2 */ -+#define R367_QAM_BERT_2 0xF4B6 -+#define F367_QAM_BERT_ERRCOUNT_L 0xF4B600FF -+ -+/* BERT_3 */ -+#define R367_QAM_BERT_3 0xF4B7 -+#define F367_QAM_BERT_ERRCOUNT_H 0xF4B700FF -+ -+/* OUTFORMAT_0 */ -+#define R367_QAM_OUTFORMAT_0 0xF4B8 -+#define F367_QAM_CLK_POLARITY 0xF4B80080 -+#define F367_QAM_FEC_TYPE 0xF4B80040 -+#define F367_QAM_SYNC_STRIP 0xF4B80008 -+#define F367_QAM_TS_SWAP 0xF4B80004 -+#define F367_QAM_OUTFORMAT 0xF4B80003 -+ -+/* OUTFORMAT_1 */ -+#define R367_QAM_OUTFORMAT_1 0xF4B9 -+#define F367_QAM_CI_DIVRANGE 0xF4B900FF -+ -+/* SMOOTHER_2 */ -+#define R367_QAM_SMOOTHER_2 0xF4BE -+#define F367_QAM_FIFO_BYPASS 0xF4BE0020 -+ -+/* TSMF_CTRL_0 */ -+#define R367_QAM_TSMF_CTRL_0 0xF4C0 -+#define F367_QAM_TS_NUMBER 0xF4C0001E -+#define F367_QAM_SEL_MODE 0xF4C00001 -+ -+/* TSMF_CTRL_1 */ -+#define R367_QAM_TSMF_CTRL_1 0xF4C1 -+#define F367_QAM_CHECK_ERROR_BIT 0xF4C10080 -+#define F367_QAM_CHCK_F_SYNC 0xF4C10040 -+#define F367_QAM_H_MODE 0xF4C10008 -+#define F367_QAM_D_V_MODE 0xF4C10004 -+#define F367_QAM_MODE 0xF4C10003 -+ -+/* TSMF_CTRL_3 */ -+#define R367_QAM_TSMF_CTRL_3 0xF4C3 -+#define F367_QAM_SYNC_IN_COUNT 0xF4C300F0 -+#define F367_QAM_SYNC_OUT_COUNT 0xF4C3000F -+ -+/* TS_ON_ID_0 */ -+#define R367_QAM_TS_ON_ID_0 0xF4C4 -+#define F367_QAM_TS_ID_L 0xF4C400FF -+ -+/* TS_ON_ID_1 */ -+#define R367_QAM_TS_ON_ID_1 0xF4C5 -+#define F367_QAM_TS_ID_H 0xF4C500FF -+ -+/* TS_ON_ID_2 */ -+#define R367_QAM_TS_ON_ID_2 0xF4C6 -+#define F367_QAM_ON_ID_L 0xF4C600FF -+ -+/* TS_ON_ID_3 */ -+#define R367_QAM_TS_ON_ID_3 0xF4C7 -+#define F367_QAM_ON_ID_H 0xF4C700FF -+ -+/* RE_STATUS_0 */ -+#define R367_QAM_RE_STATUS_0 0xF4C8 -+#define F367_QAM_RECEIVE_STATUS_L 0xF4C800FF -+ -+/* RE_STATUS_1 */ -+#define R367_QAM_RE_STATUS_1 0xF4C9 -+#define F367_QAM_RECEIVE_STATUS_LH 0xF4C900FF -+ -+/* RE_STATUS_2 */ -+#define R367_QAM_RE_STATUS_2 0xF4CA -+#define F367_QAM_RECEIVE_STATUS_HL 0xF4CA00FF -+ -+/* RE_STATUS_3 */ -+#define R367_QAM_RE_STATUS_3 0xF4CB -+#define F367_QAM_RECEIVE_STATUS_HH 0xF4CB003F -+ -+/* TS_STATUS_0 */ -+#define R367_QAM_TS_STATUS_0 0xF4CC -+#define F367_QAM_TS_STATUS_L 0xF4CC00FF -+ -+/* TS_STATUS_1 */ -+#define R367_QAM_TS_STATUS_1 0xF4CD -+#define F367_QAM_TS_STATUS_H 0xF4CD007F -+ -+/* TS_STATUS_2 */ -+#define R367_QAM_TS_STATUS_2 0xF4CE -+#define F367_QAM_ERROR 0xF4CE0080 -+#define F367_QAM_EMERGENCY 0xF4CE0040 -+#define F367_QAM_CRE_TS 0xF4CE0030 -+#define F367_QAM_VER 0xF4CE000E -+#define F367_QAM_M_LOCK 0xF4CE0001 -+ -+/* TS_STATUS_3 */ -+#define R367_QAM_TS_STATUS_3 0xF4CF -+#define F367_QAM_UPDATE_READY 0xF4CF0080 -+#define F367_QAM_END_FRAME_HEADER 0xF4CF0040 -+#define F367_QAM_CONTCNT 0xF4CF0020 -+#define F367_QAM_TS_IDENTIFIER_SEL 0xF4CF000F -+ -+/* T_O_ID_0 */ -+#define R367_QAM_T_O_ID_0 0xF4D0 -+#define F367_QAM_ON_ID_I_L 0xF4D000FF -+ -+/* T_O_ID_1 */ -+#define R367_QAM_T_O_ID_1 0xF4D1 -+#define F367_QAM_ON_ID_I_H 0xF4D100FF -+ -+/* T_O_ID_2 */ -+#define R367_QAM_T_O_ID_2 0xF4D2 -+#define F367_QAM_TS_ID_I_L 0xF4D200FF -+ -+/* T_O_ID_3 */ -+#define R367_QAM_T_O_ID_3 0xF4D3 -+#define F367_QAM_TS_ID_I_H 0xF4D300FF -+ ++// @DVB-C/DVB-T STMicroelectronics STV0367 register defintions ++// Author Manfred Völkel, Februar 2011 ++// (c) 2010 DigitalDevices GmbH Germany. All rights reserved ++ ++// $Id: DD_STV0367Register.h 357 2011-04-27 02:39:13Z manfred $ ++ ++/* ======================================================================= ++ -- Registers Declaration ++ -- ------------------------- ++ -- Each register (R367_XXXXX) is defined by its address (2 bytes). ++ -- ++ -- Each field (F367_XXXXX)is defined as follow: ++ -- [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] ++ ======================================================================= */ ++ ++/* ID */ ++#define R367_ID 0xF000 ++#define F367_IDENTIFICATIONREG 0xF00000FF ++ ++/* I2CRPT */ ++#define R367_I2CRPT 0xF001 ++#define F367_I2CT_ON 0xF0010080 ++#define F367_ENARPT_LEVEL 0xF0010070 ++#define F367_SCLT_DELAY 0xF0010008 ++#define F367_SCLT_NOD 0xF0010004 ++#define F367_STOP_ENABLE 0xF0010002 ++#define F367_SDAT_NOD 0xF0010001 ++ ++/* TOPCTRL */ ++#define R367_TOPCTRL 0xF002 ++#define F367_STDBY 0xF0020080 ++#define F367_STDBY_FEC 0xF0020040 ++#define F367_STDBY_CORE 0xF0020020 ++#define F367_QAM_COFDM 0xF0020010 ++#define F367_TS_DIS 0xF0020008 ++#define F367_DIR_CLK_216 0xF0020004 ++#define F367_TUNER_BB 0xF0020002 ++#define F367_DVBT_H 0xF0020001 ++ ++/* IOCFG0 */ ++#define R367_IOCFG0 0xF003 ++#define F367_OP0_SD 0xF0030080 ++#define F367_OP0_VAL 0xF0030040 ++#define F367_OP0_OD 0xF0030020 ++#define F367_OP0_INV 0xF0030010 ++#define F367_OP0_DACVALUE_HI 0xF003000F ++ ++/* DAC0R */ ++#define R367_DAC0R 0xF004 ++#define F367_OP0_DACVALUE_LO 0xF00400FF ++ ++/* IOCFG1 */ ++#define R367_IOCFG1 0xF005 ++#define F367_IP0 0xF0050040 ++#define F367_OP1_OD 0xF0050020 ++#define F367_OP1_INV 0xF0050010 ++#define F367_OP1_DACVALUE_HI 0xF005000F ++ ++/* DAC1R */ ++#define R367_DAC1R 0xF006 ++#define F367_OP1_DACVALUE_LO 0xF00600FF ++ ++/* IOCFG2 */ ++#define R367_IOCFG2 0xF007 ++#define F367_OP2_LOCK_CONF 0xF00700E0 ++#define F367_OP2_OD 0xF0070010 ++#define F367_OP2_VAL 0xF0070008 ++#define F367_OP1_LOCK_CONF 0xF0070007 ++ ++/* SDFR */ ++#define R367_SDFR 0xF008 ++#define F367_OP0_FREQ 0xF00800F0 ++#define F367_OP1_FREQ 0xF008000F ++ ++/* STATUS */ ++#define R367_OFDM_STATUS 0xF009 ++#define F367_TPS_LOCK 0xF0090080 ++#define F367_SYR_LOCK 0xF0090040 ++#define F367_AGC_LOCK 0xF0090020 ++#define F367_PRF 0xF0090010 ++#define F367_LK 0xF0090008 ++#define F367_PR 0xF0090007 ++ ++/* AUX_CLK */ ++#define R367_AUX_CLK 0xF00A ++#define F367_AUXFEC_CTL 0xF00A00C0 ++#define F367_DIS_CKX4 0xF00A0020 ++#define F367_CKSEL 0xF00A0018 ++#define F367_CKDIV_PROG 0xF00A0006 ++#define F367_AUXCLK_ENA 0xF00A0001 ++ ++/* FREESYS1 */ ++#define R367_FREESYS1 0xF00B ++#define F367_FREE_SYS1 0xF00B00FF ++ ++/* FREESYS2 */ ++#define R367_FREESYS2 0xF00C ++#define F367_FREE_SYS2 0xF00C00FF ++ ++/* FREESYS3 */ ++#define R367_FREESYS3 0xF00D ++#define F367_FREE_SYS3 0xF00D00FF ++ ++/* GPIO_CFG */ ++#define R367_GPIO_CFG 0xF00E ++#define F367_GPIO7_NOD 0xF00E0080 ++#define F367_GPIO7_CFG 0xF00E0040 ++#define F367_GPIO6_NOD 0xF00E0020 ++#define F367_GPIO6_CFG 0xF00E0010 ++#define F367_GPIO5_NOD 0xF00E0008 ++#define F367_GPIO5_CFG 0xF00E0004 ++#define F367_GPIO4_NOD 0xF00E0002 ++#define F367_GPIO4_CFG 0xF00E0001 ++ ++/* GPIO_CMD */ ++#define R367_GPIO_CMD 0xF00F ++#define F367_GPIO7_VAL 0xF00F0008 ++#define F367_GPIO6_VAL 0xF00F0004 ++#define F367_GPIO5_VAL 0xF00F0002 ++#define F367_GPIO4_VAL 0xF00F0001 ++ ++/* AGC2MAX */ ++#define R367_OFDM_AGC2MAX 0xF010 ++#define F367_OFDM_AGC2_MAX 0xF01000FF ++ ++/* AGC2MIN */ ++#define R367_OFDM_AGC2MIN 0xF011 ++#define F367_OFDM_AGC2_MIN 0xF01100FF ++ ++/* AGC1MAX */ ++#define R367_OFDM_AGC1MAX 0xF012 ++#define F367_OFDM_AGC1_MAX 0xF01200FF ++ ++/* AGC1MIN */ ++#define R367_OFDM_AGC1MIN 0xF013 ++#define F367_OFDM_AGC1_MIN 0xF01300FF ++ ++/* AGCR */ ++#define R367_OFDM_AGCR 0xF014 ++#define F367_OFDM_RATIO_A 0xF01400E0 ++#define F367_OFDM_RATIO_B 0xF0140018 ++#define F367_OFDM_RATIO_C 0xF0140007 ++ ++/* AGC2TH */ ++#define R367_OFDM_AGC2TH 0xF015 ++#define F367_OFDM_AGC2_THRES 0xF01500FF ++ ++/* AGC12C */ ++#define R367_OFDM_AGC12C 0xF016 ++#define F367_OFDM_AGC1_IV 0xF0160080 ++#define F367_OFDM_AGC1_OD 0xF0160040 ++#define F367_OFDM_AGC1_LOAD 0xF0160020 ++#define F367_OFDM_AGC2_IV 0xF0160010 ++#define F367_OFDM_AGC2_OD 0xF0160008 ++#define F367_OFDM_AGC2_LOAD 0xF0160004 ++#define F367_OFDM_AGC12_MODE 0xF0160003 ++ ++/* AGCCTRL1 */ ++#define R367_OFDM_AGCCTRL1 0xF017 ++#define F367_OFDM_DAGC_ON 0xF0170080 ++#define F367_OFDM_INVERT_AGC12 0xF0170040 ++#define F367_OFDM_AGC1_MODE 0xF0170008 ++#define F367_OFDM_AGC2_MODE 0xF0170007 ++ ++/* AGCCTRL2 */ ++#define R367_OFDM_AGCCTRL2 0xF018 ++#define F367_OFDM_FRZ2_CTRL 0xF0180060 ++#define F367_OFDM_FRZ1_CTRL 0xF0180018 ++#define F367_OFDM_TIME_CST 0xF0180007 ++ ++/* AGC1VAL1 */ ++#define R367_OFDM_AGC1VAL1 0xF019 ++#define F367_OFDM_AGC1_VAL_LO 0xF01900FF ++ ++/* AGC1VAL2 */ ++#define R367_OFDM_AGC1VAL2 0xF01A ++#define F367_OFDM_AGC1_VAL_HI 0xF01A000F ++ ++/* AGC2VAL1 */ ++#define R367_OFDM_AGC2VAL1 0xF01B ++#define F367_OFDM_AGC2_VAL_LO 0xF01B00FF ++ ++/* AGC2VAL2 */ ++#define R367_OFDM_AGC2VAL2 0xF01C ++#define F367_OFDM_AGC2_VAL_HI 0xF01C000F ++ ++/* AGC2PGA */ ++#define R367_OFDM_AGC2PGA 0xF01D ++#define F367_OFDM_AGC2_PGA 0xF01D00FF ++ ++/* OVF_RATE1 */ ++#define R367_OFDM_OVF_RATE1 0xF01E ++#define F367_OFDM_OVF_RATE_HI 0xF01E000F ++ ++/* OVF_RATE2 */ ++#define R367_OFDM_OVF_RATE2 0xF01F ++#define F367_OFDM_OVF_RATE_LO 0xF01F00FF ++ ++/* GAIN_SRC1 */ ++#define R367_OFDM_GAIN_SRC1 0xF020 ++#define F367_OFDM_INV_SPECTR 0xF0200080 ++#define F367_OFDM_IQ_INVERT 0xF0200040 ++#define F367_OFDM_INR_BYPASS 0xF0200020 ++#define F367_OFDM_STATUS_INV_SPECRUM 0xF0200010 ++#define F367_OFDM_GAIN_SRC_HI 0xF020000F ++ ++/* GAIN_SRC2 */ ++#define R367_OFDM_GAIN_SRC2 0xF021 ++#define F367_OFDM_GAIN_SRC_LO 0xF02100FF ++ ++/* INC_DEROT1 */ ++#define R367_OFDM_INC_DEROT1 0xF022 ++#define F367_OFDM_INC_DEROT_HI 0xF02200FF ++ ++/* INC_DEROT2 */ ++#define R367_OFDM_INC_DEROT2 0xF023 ++#define F367_OFDM_INC_DEROT_LO 0xF02300FF ++ ++/* PPM_CPAMP_DIR */ ++#define R367_OFDM_PPM_CPAMP_DIR 0xF024 ++#define F367_OFDM_PPM_CPAMP_DIRECT 0xF02400FF ++ ++/* PPM_CPAMP_INV */ ++#define R367_OFDM_PPM_CPAMP_INV 0xF025 ++#define F367_OFDM_PPM_CPAMP_INVER 0xF02500FF ++ ++/* FREESTFE_1 */ ++#define R367_OFDM_FREESTFE_1 0xF026 ++#define F367_OFDM_SYMBOL_NUMBER_INC 0xF02600C0 ++#define F367_OFDM_SEL_LSB 0xF0260004 ++#define F367_OFDM_AVERAGE_ON 0xF0260002 ++#define F367_OFDM_DC_ADJ 0xF0260001 ++ ++/* FREESTFE_2 */ ++#define R367_OFDM_FREESTFE_2 0xF027 ++#define F367_OFDM_SEL_SRCOUT 0xF02700C0 ++#define F367_OFDM_SEL_SYRTHR 0xF027001F ++ ++/* DCOFFSET */ ++#define R367_OFDM_DCOFFSET 0xF028 ++#define F367_OFDM_SELECT_I_Q 0xF0280080 ++#define F367_OFDM_DC_OFFSET 0xF028007F ++ ++/* EN_PROCESS */ ++#define R367_OFDM_EN_PROCESS 0xF029 ++#define F367_OFDM_FREE 0xF02900F0 ++#define F367_OFDM_ENAB_MANUAL 0xF0290001 ++ ++/* SDI_SMOOTHER */ ++#define R367_OFDM_SDI_SMOOTHER 0xF02A ++#define F367_OFDM_DIS_SMOOTH 0xF02A0080 ++#define F367_OFDM_SDI_INC_SMOOTHER 0xF02A007F ++ ++/* FE_LOOP_OPEN */ ++#define R367_OFDM_FE_LOOP_OPEN 0xF02B ++#define F367_OFDM_TRL_LOOP_OP 0xF02B0002 ++#define F367_OFDM_CRL_LOOP_OP 0xF02B0001 ++ ++/* FREQOFF1 */ ++#define R367_OFDM_FREQOFF1 0xF02C ++#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_VHI 0xF02C00FF ++ ++/* FREQOFF2 */ ++#define R367_OFDM_FREQOFF2 0xF02D ++#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_HI 0xF02D00FF ++ ++/* FREQOFF3 */ ++#define R367_OFDM_FREQOFF3 0xF02E ++#define F367_OFDM_FREQ_OFFSET_LOOP_OPEN_LO 0xF02E00FF ++ ++/* TIMOFF1 */ ++#define R367_OFDM_TIMOFF1 0xF02F ++#define F367_OFDM_TIM_OFFSET_LOOP_OPEN_HI 0xF02F00FF ++ ++/* TIMOFF2 */ ++#define R367_OFDM_TIMOFF2 0xF030 ++#define F367_OFDM_TIM_OFFSET_LOOP_OPEN_LO 0xF03000FF ++ ++/* EPQ */ ++#define R367_OFDM_EPQ 0xF031 ++#define F367_OFDM_EPQ1 0xF03100FF ++ ++/* EPQAUTO */ ++#define R367_OFDM_EPQAUTO 0xF032 ++#define F367_OFDM_EPQ2 0xF03200FF ++ ++/* SYR_UPDATE */ ++#define R367_OFDM_SYR_UPDATE 0xF033 ++#define F367_OFDM_SYR_PROTV 0xF0330080 ++#define F367_OFDM_SYR_PROTV_GAIN 0xF0330060 ++#define F367_OFDM_SYR_FILTER 0xF0330010 ++#define F367_OFDM_SYR_TRACK_THRES 0xF033000C ++ ++/* CHPFREE */ ++#define R367_OFDM_CHPFREE 0xF034 ++#define F367_OFDM_CHP_FREE 0xF03400FF ++ ++/* PPM_STATE_MAC */ ++#define R367_OFDM_PPM_STATE_MAC 0xF035 ++#define F367_OFDM_PPM_STATE_MACHINE_DECODER 0xF035003F ++ ++/* INR_THRESHOLD */ ++#define R367_OFDM_INR_THRESHOLD 0xF036 ++#define F367_OFDM_INR_THRESH 0xF03600FF ++ ++/* EPQ_TPS_ID_CELL */ ++#define R367_OFDM_EPQ_TPS_ID_CELL 0xF037 ++#define F367_OFDM_ENABLE_LGTH_TO_CF 0xF0370080 ++#define F367_OFDM_DIS_TPS_RSVD 0xF0370040 ++#define F367_OFDM_DIS_BCH 0xF0370020 ++#define F367_OFDM_DIS_ID_CEL 0xF0370010 ++#define F367_OFDM_TPS_ADJUST_SYM 0xF037000F ++ ++/* EPQ_CFG */ ++#define R367_OFDM_EPQ_CFG 0xF038 ++#define F367_OFDM_EPQ_RANGE 0xF0380002 ++#define F367_OFDM_EPQ_SOFT 0xF0380001 ++ ++/* EPQ_STATUS */ ++#define R367_OFDM_EPQ_STATUS 0xF039 ++#define F367_OFDM_SLOPE_INC 0xF03900FC ++#define F367_OFDM_TPS_FIELD 0xF0390003 ++ ++/* AUTORELOCK */ ++#define R367_OFDM_AUTORELOCK 0xF03A ++#define F367_OFDM_BYPASS_BER_TEMPO 0xF03A0080 ++#define F367_OFDM_BER_TEMPO 0xF03A0070 ++#define F367_OFDM_BYPASS_COFDM_TEMPO 0xF03A0008 ++#define F367_OFDM_COFDM_TEMPO 0xF03A0007 ++ ++/* BER_THR_VMSB */ ++#define R367_OFDM_BER_THR_VMSB 0xF03B ++#define F367_OFDM_BER_THRESHOLD_HI 0xF03B00FF ++ ++/* BER_THR_MSB */ ++#define R367_OFDM_BER_THR_MSB 0xF03C ++#define F367_OFDM_BER_THRESHOLD_MID 0xF03C00FF ++ ++/* BER_THR_LSB */ ++#define R367_OFDM_BER_THR_LSB 0xF03D ++#define F367_OFDM_BER_THRESHOLD_LO 0xF03D00FF ++ ++/* CCD */ ++#define R367_OFDM_CCD 0xF03E ++#define F367_OFDM_CCD_DETECTED 0xF03E0080 ++#define F367_OFDM_CCD_RESET 0xF03E0040 ++#define F367_OFDM_CCD_THRESHOLD 0xF03E000F ++ ++/* SPECTR_CFG */ ++#define R367_OFDM_SPECTR_CFG 0xF03F ++#define F367_OFDM_SPECT_CFG 0xF03F0003 ++ ++/* CONSTMU_MSB */ ++#define R367_OFDM_CONSTMU_MSB 0xF040 ++#define F367_OFDM_CONSTMU_FREEZE 0xF0400080 ++#define F367_OFDM_CONSTNU_FORCE_EN 0xF0400040 ++#define F367_OFDM_CONST_MU_MSB 0xF040003F ++ ++/* CONSTMU_LSB */ ++#define R367_OFDM_CONSTMU_LSB 0xF041 ++#define F367_OFDM_CONST_MU_LSB 0xF04100FF ++ ++/* CONSTMU_MAX_MSB */ ++#define R367_OFDM_CONSTMU_MAX_MSB 0xF042 ++#define F367_OFDM_CONST_MU_MAX_MSB 0xF042003F ++ ++/* CONSTMU_MAX_LSB */ ++#define R367_OFDM_CONSTMU_MAX_LSB 0xF043 ++#define F367_OFDM_CONST_MU_MAX_LSB 0xF04300FF ++ ++/* ALPHANOISE */ ++#define R367_OFDM_ALPHANOISE 0xF044 ++#define F367_OFDM_USE_ALLFILTER 0xF0440080 ++#define F367_OFDM_INTER_ON 0xF0440040 ++#define F367_OFDM_ALPHA_NOISE 0xF044001F ++ ++/* MAXGP_MSB */ ++#define R367_OFDM_MAXGP_MSB 0xF045 ++#define F367_OFDM_MUFILTER_LENGTH 0xF04500F0 ++#define F367_OFDM_MAX_GP_MSB 0xF045000F ++ ++/* MAXGP_LSB */ ++#define R367_OFDM_MAXGP_LSB 0xF046 ++#define F367_OFDM_MAX_GP_LSB 0xF04600FF ++ ++/* ALPHAMSB */ ++#define R367_OFDM_ALPHAMSB 0xF047 ++#define F367_OFDM_CHC_DATARATE 0xF04700C0 ++#define F367_OFDM_ALPHA_MSB 0xF047003F ++ ++/* ALPHALSB */ ++#define R367_OFDM_ALPHALSB 0xF048 ++#define F367_OFDM_ALPHA_LSB 0xF04800FF ++ ++/* PILOT_ACCU */ ++#define R367_OFDM_PILOT_ACCU 0xF049 ++#define F367_OFDM_USE_SCAT4ADDAPT 0xF0490080 ++#define F367_OFDM_PILOT_ACC 0xF049001F ++ ++/* PILOTMU_ACCU */ ++#define R367_OFDM_PILOTMU_ACCU 0xF04A ++#define F367_OFDM_DISCARD_BAD_SP 0xF04A0080 ++#define F367_OFDM_DISCARD_BAD_CP 0xF04A0040 ++#define F367_OFDM_PILOT_MU_ACCU 0xF04A001F ++ ++/* FILT_CHANNEL_EST */ ++#define R367_OFDM_FILT_CHANNEL_EST 0xF04B ++#define F367_OFDM_USE_FILT_PILOT 0xF04B0080 ++#define F367_OFDM_FILT_CHANNEL 0xF04B007F ++ ++/* ALPHA_NOPISE_FREQ */ ++#define R367_OFDM_ALPHA_NOPISE_FREQ 0xF04C ++#define F367_OFDM_NOISE_FREQ_FILT 0xF04C0040 ++#define F367_OFDM_ALPHA_NOISE_FREQ 0xF04C003F ++ ++/* RATIO_PILOT */ ++#define R367_OFDM_RATIO_PILOT 0xF04D ++#define F367_OFDM_RATIO_MEAN_SP 0xF04D00F0 ++#define F367_OFDM_RATIO_MEAN_CP 0xF04D000F ++ ++/* CHC_CTL */ ++#define R367_OFDM_CHC_CTL 0xF04E ++#define F367_OFDM_TRACK_EN 0xF04E0080 ++#define F367_OFDM_NOISE_NORM_EN 0xF04E0040 ++#define F367_OFDM_FORCE_CHC_RESET 0xF04E0020 ++#define F367_OFDM_SHORT_TIME 0xF04E0010 ++#define F367_OFDM_FORCE_STATE_EN 0xF04E0008 ++#define F367_OFDM_FORCE_STATE 0xF04E0007 ++ ++/* EPQ_ADJUST */ ++#define R367_OFDM_EPQ_ADJUST 0xF04F ++#define F367_OFDM_ADJUST_SCAT_IND 0xF04F00C0 ++#define F367_OFDM_ONE_SYMBOL 0xF04F0010 ++#define F367_OFDM_EPQ_DECAY 0xF04F000E ++#define F367_OFDM_HOLD_SLOPE 0xF04F0001 ++ ++/* EPQ_THRES */ ++#define R367_OFDM_EPQ_THRES 0xF050 ++#define F367_OFDM_EPQ_THR 0xF05000FF ++ ++/* OMEGA_CTL */ ++#define R367_OFDM_OMEGA_CTL 0xF051 ++#define F367_OFDM_OMEGA_RST 0xF0510080 ++#define F367_OFDM_FREEZE_OMEGA 0xF0510040 ++#define F367_OFDM_OMEGA_SEL 0xF051003F ++ ++/* GP_CTL */ ++#define R367_OFDM_GP_CTL 0xF052 ++#define F367_OFDM_CHC_STATE 0xF05200E0 ++#define F367_OFDM_FREEZE_GP 0xF0520010 ++#define F367_OFDM_GP_SEL 0xF052000F ++ ++/* MUMSB */ ++#define R367_OFDM_MUMSB 0xF053 ++#define F367_OFDM_MU_MSB 0xF053007F ++ ++/* MULSB */ ++#define R367_OFDM_MULSB 0xF054 ++#define F367_OFDM_MU_LSB 0xF05400FF ++ ++/* GPMSB */ ++#define R367_OFDM_GPMSB 0xF055 ++#define F367_OFDM_CSI_THRESHOLD 0xF05500E0 ++#define F367_OFDM_GP_MSB 0xF055000F ++ ++/* GPLSB */ ++#define R367_OFDM_GPLSB 0xF056 ++#define F367_OFDM_GP_LSB 0xF05600FF ++ ++/* OMEGAMSB */ ++#define R367_OFDM_OMEGAMSB 0xF057 ++#define F367_OFDM_OMEGA_MSB 0xF057007F ++ ++/* OMEGALSB */ ++#define R367_OFDM_OMEGALSB 0xF058 ++#define F367_OFDM_OMEGA_LSB 0xF05800FF ++ ++/* SCAT_NB */ ++#define R367_OFDM_SCAT_NB 0xF059 ++#define F367_OFDM_CHC_TEST 0xF05900F8 ++#define F367_OFDM_SCAT_NUMB 0xF0590003 ++ ++/* CHC_DUMMY */ ++#define R367_OFDM_CHC_DUMMY 0xF05A ++#define F367_OFDM_CHC_DUM 0xF05A00FF ++ ++/* INC_CTL */ ++#define R367_OFDM_INC_CTL 0xF05B ++#define F367_OFDM_INC_BYPASS 0xF05B0080 ++#define F367_OFDM_INC_NDEPTH 0xF05B000C ++#define F367_OFDM_INC_MADEPTH 0xF05B0003 ++ ++/* INCTHRES_COR1 */ ++#define R367_OFDM_INCTHRES_COR1 0xF05C ++#define F367_OFDM_INC_THRES_COR1 0xF05C00FF ++ ++/* INCTHRES_COR2 */ ++#define R367_OFDM_INCTHRES_COR2 0xF05D ++#define F367_OFDM_INC_THRES_COR2 0xF05D00FF ++ ++/* INCTHRES_DET1 */ ++#define R367_OFDM_INCTHRES_DET1 0xF05E ++#define F367_OFDM_INC_THRES_DET1 0xF05E003F ++ ++/* INCTHRES_DET2 */ ++#define R367_OFDM_INCTHRES_DET2 0xF05F ++#define F367_OFDM_INC_THRES_DET2 0xF05F003F ++ ++/* IIR_CELLNB */ ++#define R367_OFDM_IIR_CELLNB 0xF060 ++#define F367_OFDM_NRST_IIR 0xF0600080 ++#define F367_OFDM_IIR_CELL_NB 0xF0600007 ++ ++/* IIRCX_COEFF1_MSB */ ++#define R367_OFDM_IIRCX_COEFF1_MSB 0xF061 ++#define F367_OFDM_IIR_CX_COEFF1_MSB 0xF06100FF ++ ++/* IIRCX_COEFF1_LSB */ ++#define R367_OFDM_IIRCX_COEFF1_LSB 0xF062 ++#define F367_OFDM_IIR_CX_COEFF1_LSB 0xF06200FF ++ ++/* IIRCX_COEFF2_MSB */ ++#define R367_OFDM_IIRCX_COEFF2_MSB 0xF063 ++#define F367_OFDM_IIR_CX_COEFF2_MSB 0xF06300FF ++ ++/* IIRCX_COEFF2_LSB */ ++#define R367_OFDM_IIRCX_COEFF2_LSB 0xF064 ++#define F367_OFDM_IIR_CX_COEFF2_LSB 0xF06400FF ++ ++/* IIRCX_COEFF3_MSB */ ++#define R367_OFDM_IIRCX_COEFF3_MSB 0xF065 ++#define F367_OFDM_IIR_CX_COEFF3_MSB 0xF06500FF ++ ++/* IIRCX_COEFF3_LSB */ ++#define R367_OFDM_IIRCX_COEFF3_LSB 0xF066 ++#define F367_OFDM_IIR_CX_COEFF3_LSB 0xF06600FF ++ ++/* IIRCX_COEFF4_MSB */ ++#define R367_OFDM_IIRCX_COEFF4_MSB 0xF067 ++#define F367_OFDM_IIR_CX_COEFF4_MSB 0xF06700FF ++ ++/* IIRCX_COEFF4_LSB */ ++#define R367_OFDM_IIRCX_COEFF4_LSB 0xF068 ++#define F367_OFDM_IIR_CX_COEFF4_LSB 0xF06800FF ++ ++/* IIRCX_COEFF5_MSB */ ++#define R367_OFDM_IIRCX_COEFF5_MSB 0xF069 ++#define F367_OFDM_IIR_CX_COEFF5_MSB 0xF06900FF ++ ++/* IIRCX_COEFF5_LSB */ ++#define R367_OFDM_IIRCX_COEFF5_LSB 0xF06A ++#define F367_OFDM_IIR_CX_COEFF5_LSB 0xF06A00FF ++ ++/* FEPATH_CFG */ ++#define R367_OFDM_FEPATH_CFG 0xF06B ++#define F367_OFDM_DEMUX_SWAP 0xF06B0004 ++#define F367_OFDM_DIGAGC_SWAP 0xF06B0002 ++#define F367_OFDM_LONGPATH_IF 0xF06B0001 ++ ++/* PMC1_FUNC */ ++#define R367_OFDM_PMC1_FUNC 0xF06C ++#define F367_OFDM_SOFT_RSTN 0xF06C0080 ++#define F367_OFDM_PMC1_AVERAGE_TIME 0xF06C0078 ++#define F367_OFDM_PMC1_WAIT_TIME 0xF06C0006 ++#define F367_OFDM_PMC1_2N_SEL 0xF06C0001 ++ ++/* PMC1_FOR */ ++#define R367_OFDM_PMC1_FOR 0xF06D ++#define F367_OFDM_PMC1_FORCE 0xF06D0080 ++#define F367_OFDM_PMC1_FORCE_VALUE 0xF06D007C ++ ++/* PMC2_FUNC */ ++#define R367_OFDM_PMC2_FUNC 0xF06E ++#define F367_OFDM_PMC2_SOFT_STN 0xF06E0080 ++#define F367_OFDM_PMC2_ACCU_TIME 0xF06E0070 ++#define F367_OFDM_PMC2_CMDP_MN 0xF06E0008 ++#define F367_OFDM_PMC2_SWAP 0xF06E0004 ++ ++/* STATUS_ERR_DA */ ++#define R367_OFDM_STATUS_ERR_DA 0xF06F ++#define F367_OFDM_COM_USEGAINTRK 0xF06F0080 ++#define F367_OFDM_COM_AGCLOCK 0xF06F0040 ++#define F367_OFDM_AUT_AGCLOCK 0xF06F0020 ++#define F367_OFDM_MIN_ERR_X_LSB 0xF06F000F ++ ++/* DIG_AGC_R */ ++#define R367_OFDM_DIG_AGC_R 0xF070 ++#define F367_OFDM_COM_SOFT_RSTN 0xF0700080 ++#define F367_OFDM_COM_AGC_ON 0xF0700040 ++#define F367_OFDM_COM_EARLY 0xF0700020 ++#define F367_OFDM_AUT_SOFT_RESETN 0xF0700010 ++#define F367_OFDM_AUT_AGC_ON 0xF0700008 ++#define F367_OFDM_AUT_EARLY 0xF0700004 ++#define F367_OFDM_AUT_ROT_EN 0xF0700002 ++#define F367_OFDM_LOCK_SOFT_RESETN 0xF0700001 ++ ++/* COMAGC_TARMSB */ ++#define R367_OFDM_COMAGC_TARMSB 0xF071 ++#define F367_OFDM_COM_AGC_TARGET_MSB 0xF07100FF ++ ++/* COM_AGC_TAR_ENMODE */ ++#define R367_OFDM_COM_AGC_TAR_ENMODE 0xF072 ++#define F367_OFDM_COM_AGC_TARGET_LSB 0xF07200F0 ++#define F367_OFDM_COM_ENMODE 0xF072000F ++ ++/* COM_AGC_CFG */ ++#define R367_OFDM_COM_AGC_CFG 0xF073 ++#define F367_OFDM_COM_N 0xF07300F8 ++#define F367_OFDM_COM_STABMODE 0xF0730006 ++#define F367_OFDM_ERR_SEL 0xF0730001 ++ ++/* COM_AGC_GAIN1 */ ++#define R367_OFDM_COM_AGC_GAIN1 0xF074 ++#define F367_OFDM_COM_GAIN1ACK 0xF07400F0 ++#define F367_OFDM_COM_GAIN1TRK 0xF074000F ++ ++/* AUT_AGC_TARGETMSB */ ++#define R367_OFDM_AUT_AGC_TARGETMSB 0xF075 ++#define F367_OFDM_AUT_AGC_TARGET_MSB 0xF07500FF ++ ++/* LOCK_DET_MSB */ ++#define R367_OFDM_LOCK_DET_MSB 0xF076 ++#define F367_OFDM_LOCK_DETECT_MSB 0xF07600FF ++ ++/* AGCTAR_LOCK_LSBS */ ++#define R367_OFDM_AGCTAR_LOCK_LSBS 0xF077 ++#define F367_OFDM_AUT_AGC_TARGET_LSB 0xF07700F0 ++#define F367_OFDM_LOCK_DETECT_LSB 0xF077000F ++ ++/* AUT_GAIN_EN */ ++#define R367_OFDM_AUT_GAIN_EN 0xF078 ++#define F367_OFDM_AUT_ENMODE 0xF07800F0 ++#define F367_OFDM_AUT_GAIN2 0xF078000F ++ ++/* AUT_CFG */ ++#define R367_OFDM_AUT_CFG 0xF079 ++#define F367_OFDM_AUT_N 0xF07900F8 ++#define F367_OFDM_INT_CHOICE 0xF0790006 ++#define F367_OFDM_INT_LOAD 0xF0790001 ++ ++/* LOCKN */ ++#define R367_OFDM_LOCKN 0xF07A ++#define F367_OFDM_LOCK_N 0xF07A00F8 ++#define F367_OFDM_SEL_IQNTAR 0xF07A0004 ++#define F367_OFDM_LOCK_DETECT_CHOICE 0xF07A0003 ++ ++/* INT_X_3 */ ++#define R367_OFDM_INT_X_3 0xF07B ++#define F367_OFDM_INT_X3 0xF07B00FF ++ ++/* INT_X_2 */ ++#define R367_OFDM_INT_X_2 0xF07C ++#define F367_OFDM_INT_X2 0xF07C00FF ++ ++/* INT_X_1 */ ++#define R367_OFDM_INT_X_1 0xF07D ++#define F367_OFDM_INT_X1 0xF07D00FF ++ ++/* INT_X_0 */ ++#define R367_OFDM_INT_X_0 0xF07E ++#define F367_OFDM_INT_X0 0xF07E00FF ++ ++/* MIN_ERRX_MSB */ ++#define R367_OFDM_MIN_ERRX_MSB 0xF07F ++#define F367_OFDM_MIN_ERR_X_MSB 0xF07F00FF ++ ++/* COR_CTL */ ++#define R367_OFDM_COR_CTL 0xF080 ++#define F367_OFDM_CORE_ACTIVE 0xF0800020 ++#define F367_OFDM_HOLD 0xF0800010 ++#define F367_OFDM_CORE_STATE_CTL 0xF080000F ++ ++/* COR_STAT */ ++#define R367_OFDM_COR_STAT 0xF081 ++#define F367_OFDM_SCATT_LOCKED 0xF0810080 ++#define F367_OFDM_TPS_LOCKED 0xF0810040 ++#define F367_OFDM_SYR_LOCKED_COR 0xF0810020 ++#define F367_OFDM_AGC_LOCKED_STAT 0xF0810010 ++#define F367_OFDM_CORE_STATE_STAT 0xF081000F ++ ++/* COR_INTEN */ ++#define R367_OFDM_COR_INTEN 0xF082 ++#define F367_OFDM_INTEN 0xF0820080 ++#define F367_OFDM_INTEN_SYR 0xF0820020 ++#define F367_OFDM_INTEN_FFT 0xF0820010 ++#define F367_OFDM_INTEN_AGC 0xF0820008 ++#define F367_OFDM_INTEN_TPS1 0xF0820004 ++#define F367_OFDM_INTEN_TPS2 0xF0820002 ++#define F367_OFDM_INTEN_TPS3 0xF0820001 ++ ++/* COR_INTSTAT */ ++#define R367_OFDM_COR_INTSTAT 0xF083 ++#define F367_OFDM_INTSTAT_SYR 0xF0830020 ++#define F367_OFDM_INTSTAT_FFT 0xF0830010 ++#define F367_OFDM_INTSAT_AGC 0xF0830008 ++#define F367_OFDM_INTSTAT_TPS1 0xF0830004 ++#define F367_OFDM_INTSTAT_TPS2 0xF0830002 ++#define F367_OFDM_INTSTAT_TPS3 0xF0830001 ++ ++/* COR_MODEGUARD */ ++#define R367_OFDM_COR_MODEGUARD 0xF084 ++#define F367_OFDM_FORCE 0xF0840010 ++#define F367_OFDM_MODE 0xF084000C ++#define F367_OFDM_GUARD 0xF0840003 ++ ++/* AGC_CTL */ ++#define R367_OFDM_AGC_CTL 0xF085 ++#define F367_OFDM_AGC_TIMING_FACTOR 0xF08500E0 ++#define F367_OFDM_AGC_LAST 0xF0850010 ++#define F367_OFDM_AGC_GAIN 0xF085000C ++#define F367_OFDM_AGC_NEG 0xF0850002 ++#define F367_OFDM_AGC_SET 0xF0850001 ++ ++/* AGC_MANUAL1 */ ++#define R367_OFDM_AGC_MANUAL1 0xF086 ++#define F367_OFDM_AGC_VAL_LO 0xF08600FF ++ ++/* AGC_MANUAL2 */ ++#define R367_OFDM_AGC_MANUAL2 0xF087 ++#define F367_OFDM_AGC_VAL_HI 0xF087000F ++ ++/* AGC_TARG */ ++#define R367_OFDM_AGC_TARG 0xF088 ++#define F367_OFDM_AGC_TARGET 0xF08800FF ++ ++/* AGC_GAIN1 */ ++#define R367_OFDM_AGC_GAIN1 0xF089 ++#define F367_OFDM_AGC_GAIN_LO 0xF08900FF ++ ++/* AGC_GAIN2 */ ++#define R367_OFDM_AGC_GAIN2 0xF08A ++#define F367_OFDM_AGC_LOCKED_GAIN2 0xF08A0010 ++#define F367_OFDM_AGC_GAIN_HI 0xF08A000F ++ ++/* RESERVED_1 */ ++#define R367_OFDM_RESERVED_1 0xF08B ++#define F367_OFDM_RESERVED1 0xF08B00FF ++ ++/* RESERVED_2 */ ++#define R367_OFDM_RESERVED_2 0xF08C ++#define F367_OFDM_RESERVED2 0xF08C00FF ++ ++/* RESERVED_3 */ ++#define R367_OFDM_RESERVED_3 0xF08D ++#define F367_OFDM_RESERVED3 0xF08D00FF ++ ++/* CAS_CTL */ ++#define R367_OFDM_CAS_CTL 0xF08E ++#define F367_OFDM_CCS_ENABLE 0xF08E0080 ++#define F367_OFDM_ACS_DISABLE 0xF08E0040 ++#define F367_OFDM_DAGC_DIS 0xF08E0020 ++#define F367_OFDM_DAGC_GAIN 0xF08E0018 ++#define F367_OFDM_CCSMU 0xF08E0007 ++ ++/* CAS_FREQ */ ++#define R367_OFDM_CAS_FREQ 0xF08F ++#define F367_OFDM_CCS_FREQ 0xF08F00FF ++ ++/* CAS_DAGCGAIN */ ++#define R367_OFDM_CAS_DAGCGAIN 0xF090 ++#define F367_OFDM_CAS_DAGC_GAIN 0xF09000FF ++ ++/* SYR_CTL */ ++#define R367_OFDM_SYR_CTL 0xF091 ++#define F367_OFDM_SICTH_ENABLE 0xF0910080 ++#define F367_OFDM_LONG_ECHO 0xF0910078 ++#define F367_OFDM_AUTO_LE_EN 0xF0910004 ++#define F367_OFDM_SYR_BYPASS 0xF0910002 ++#define F367_OFDM_SYR_TR_DIS 0xF0910001 ++ ++/* SYR_STAT */ ++#define R367_OFDM_SYR_STAT 0xF092 ++#define F367_OFDM_SYR_LOCKED_STAT 0xF0920010 ++#define F367_OFDM_SYR_MODE 0xF092000C ++#define F367_OFDM_SYR_GUARD 0xF0920003 ++ ++/* SYR_NCO1 */ ++#define R367_OFDM_SYR_NCO1 0xF093 ++#define F367_OFDM_SYR_NCO_LO 0xF09300FF ++ ++/* SYR_NCO2 */ ++#define R367_OFDM_SYR_NCO2 0xF094 ++#define F367_OFDM_SYR_NCO_HI 0xF094003F ++ ++/* SYR_OFFSET1 */ ++#define R367_OFDM_SYR_OFFSET1 0xF095 ++#define F367_OFDM_SYR_OFFSET_LO 0xF09500FF ++ ++/* SYR_OFFSET2 */ ++#define R367_OFDM_SYR_OFFSET2 0xF096 ++#define F367_OFDM_SYR_OFFSET_HI 0xF096003F ++ ++/* FFT_CTL */ ++#define R367_OFDM_FFT_CTL 0xF097 ++#define F367_OFDM_SHIFT_FFT_TRIG 0xF0970018 ++#define F367_OFDM_FFT_TRIGGER 0xF0970004 ++#define F367_OFDM_FFT_MANUAL 0xF0970002 ++#define F367_OFDM_IFFT_MODE 0xF0970001 ++ ++/* SCR_CTL */ ++#define R367_OFDM_SCR_CTL 0xF098 ++#define F367_OFDM_SYRADJDECAY 0xF0980070 ++#define F367_OFDM_SCR_CPEDIS 0xF0980002 ++#define F367_OFDM_SCR_DIS 0xF0980001 ++ ++/* PPM_CTL1 */ ++#define R367_OFDM_PPM_CTL1 0xF099 ++#define F367_OFDM_PPM_MAXFREQ 0xF0990030 ++#define F367_OFDM_PPM_MAXTIM 0xF0990008 ++#define F367_OFDM_PPM_INVSEL 0xF0990004 ++#define F367_OFDM_PPM_SCATDIS 0xF0990002 ++#define F367_OFDM_PPM_BYP 0xF0990001 ++ ++/* TRL_CTL */ ++#define R367_OFDM_TRL_CTL 0xF09A ++#define F367_OFDM_TRL_NOMRATE_LSB 0xF09A0080 ++#define F367_OFDM_TRL_GAIN_FACTOR 0xF09A0078 ++#define F367_OFDM_TRL_LOOPGAIN 0xF09A0007 ++ ++/* TRL_NOMRATE1 */ ++#define R367_OFDM_TRL_NOMRATE1 0xF09B ++#define F367_OFDM_TRL_NOMRATE_LO 0xF09B00FF ++ ++/* TRL_NOMRATE2 */ ++#define R367_OFDM_TRL_NOMRATE2 0xF09C ++#define F367_OFDM_TRL_NOMRATE_HI 0xF09C00FF ++ ++/* TRL_TIME1 */ ++#define R367_OFDM_TRL_TIME1 0xF09D ++#define F367_OFDM_TRL_TOFFSET_LO 0xF09D00FF ++ ++/* TRL_TIME2 */ ++#define R367_OFDM_TRL_TIME2 0xF09E ++#define F367_OFDM_TRL_TOFFSET_HI 0xF09E00FF ++ ++/* CRL_CTL */ ++#define R367_OFDM_CRL_CTL 0xF09F ++#define F367_OFDM_CRL_DIS 0xF09F0080 ++#define F367_OFDM_CRL_GAIN_FACTOR 0xF09F0078 ++#define F367_OFDM_CRL_LOOPGAIN 0xF09F0007 ++ ++/* CRL_FREQ1 */ ++#define R367_OFDM_CRL_FREQ1 0xF0A0 ++#define F367_OFDM_CRL_FOFFSET_LO 0xF0A000FF ++ ++/* CRL_FREQ2 */ ++#define R367_OFDM_CRL_FREQ2 0xF0A1 ++#define F367_OFDM_CRL_FOFFSET_HI 0xF0A100FF ++ ++/* CRL_FREQ3 */ ++#define R367_OFDM_CRL_FREQ3 0xF0A2 ++#define F367_OFDM_CRL_FOFFSET_VHI 0xF0A200FF ++ ++/* TPS_SFRAME_CTL */ ++#define R367_OFDM_TPS_SFRAME_CTL 0xF0A3 ++#define F367_OFDM_TPS_SFRAME_SYNC 0xF0A30001 ++ ++/* CHC_SNR */ ++#define R367_OFDM_CHC_SNR 0xF0A4 ++#define F367_OFDM_CHCSNR 0xF0A400FF ++ ++/* BDI_CTL */ ++#define R367_OFDM_BDI_CTL 0xF0A5 ++#define F367_OFDM_BDI_LPSEL 0xF0A50002 ++#define F367_OFDM_BDI_SERIAL 0xF0A50001 ++ ++/* DMP_CTL */ ++#define R367_OFDM_DMP_CTL 0xF0A6 ++#define F367_OFDM_DMP_SCALING_FACTOR 0xF0A6001E ++#define F367_OFDM_DMP_SDDIS 0xF0A60001 ++ ++/* TPS_RCVD1 */ ++#define R367_OFDM_TPS_RCVD1 0xF0A7 ++#define F367_OFDM_TPS_CHANGE 0xF0A70040 ++#define F367_OFDM_BCH_OK 0xF0A70020 ++#define F367_OFDM_TPS_SYNC 0xF0A70010 ++#define F367_OFDM_TPS_FRAME 0xF0A70003 ++ ++/* TPS_RCVD2 */ ++#define R367_OFDM_TPS_RCVD2 0xF0A8 ++#define F367_OFDM_TPS_HIERMODE 0xF0A80070 ++#define F367_OFDM_TPS_CONST 0xF0A80003 ++ ++/* TPS_RCVD3 */ ++#define R367_OFDM_TPS_RCVD3 0xF0A9 ++#define F367_OFDM_TPS_LPCODE 0xF0A90070 ++#define F367_OFDM_TPS_HPCODE 0xF0A90007 ++ ++/* TPS_RCVD4 */ ++#define R367_OFDM_TPS_RCVD4 0xF0AA ++#define F367_OFDM_TPS_GUARD 0xF0AA0030 ++#define F367_OFDM_TPS_MODE 0xF0AA0003 ++ ++/* TPS_ID_CELL1 */ ++#define R367_OFDM_TPS_ID_CELL1 0xF0AB ++#define F367_OFDM_TPS_ID_CELL_LO 0xF0AB00FF ++ ++/* TPS_ID_CELL2 */ ++#define R367_OFDM_TPS_ID_CELL2 0xF0AC ++#define F367_OFDM_TPS_ID_CELL_HI 0xF0AC00FF ++ ++/* TPS_RCVD5_SET1 */ ++#define R367_OFDM_TPS_RCVD5_SET1 0xF0AD ++#define F367_OFDM_TPS_NA 0xF0AD00FC ++#define F367_OFDM_TPS_SETFRAME 0xF0AD0003 ++ ++/* TPS_SET2 */ ++#define R367_OFDM_TPS_SET2 0xF0AE ++#define F367_OFDM_TPS_SETHIERMODE 0xF0AE0070 ++#define F367_OFDM_TPS_SETCONST 0xF0AE0003 ++ ++/* TPS_SET3 */ ++#define R367_OFDM_TPS_SET3 0xF0AF ++#define F367_OFDM_TPS_SETLPCODE 0xF0AF0070 ++#define F367_OFDM_TPS_SETHPCODE 0xF0AF0007 ++ ++/* TPS_CTL */ ++#define R367_OFDM_TPS_CTL 0xF0B0 ++#define F367_OFDM_TPS_IMM 0xF0B00004 ++#define F367_OFDM_TPS_BCHDIS 0xF0B00002 ++#define F367_OFDM_TPS_UPDDIS 0xF0B00001 ++ ++/* CTL_FFTOSNUM */ ++#define R367_OFDM_CTL_FFTOSNUM 0xF0B1 ++#define F367_OFDM_SYMBOL_NUMBER 0xF0B1007F ++ ++/* TESTSELECT */ ++#define R367_OFDM_TESTSELECT 0xF0B2 ++#define F367_OFDM_TEST_SELECT 0xF0B2001F ++ ++/* MSC_REV */ ++#define R367_OFDM_MSC_REV 0xF0B3 ++#define F367_OFDM_REV_NUMBER 0xF0B300FF ++ ++/* PIR_CTL */ ++#define R367_OFDM_PIR_CTL 0xF0B4 ++#define F367_OFDM_FREEZE 0xF0B40001 ++ ++/* SNR_CARRIER1 */ ++#define R367_OFDM_SNR_CARRIER1 0xF0B5 ++#define F367_OFDM_SNR_CARRIER_LO 0xF0B500FF ++ ++/* SNR_CARRIER2 */ ++#define R367_OFDM_SNR_CARRIER2 0xF0B6 ++#define F367_OFDM_MEAN 0xF0B600C0 ++#define F367_OFDM_SNR_CARRIER_HI 0xF0B6001F ++ ++/* PPM_CPAMP */ ++#define R367_OFDM_PPM_CPAMP 0xF0B7 ++#define F367_OFDM_PPM_CPC 0xF0B700FF ++ ++/* TSM_AP0 */ ++#define R367_OFDM_TSM_AP0 0xF0B8 ++#define F367_OFDM_ADDRESS_BYTE_0 0xF0B800FF ++ ++/* TSM_AP1 */ ++#define R367_OFDM_TSM_AP1 0xF0B9 ++#define F367_OFDM_ADDRESS_BYTE_1 0xF0B900FF ++ ++/* TSM_AP2 */ ++#define R367_OFDM_TSM_AP2 0xF0BA ++#define F367_OFDM_DATA_BYTE_0 0xF0BA00FF ++ ++/* TSM_AP3 */ ++#define R367_OFDM_TSM_AP3 0xF0BB ++#define F367_OFDM_DATA_BYTE_1 0xF0BB00FF ++ ++/* TSM_AP4 */ ++#define R367_OFDM_TSM_AP4 0xF0BC ++#define F367_OFDM_DATA_BYTE_2 0xF0BC00FF ++ ++/* TSM_AP5 */ ++#define R367_OFDM_TSM_AP5 0xF0BD ++#define F367_OFDM_DATA_BYTE_3 0xF0BD00FF ++ ++/* TSM_AP6 */ ++#define R367_OFDM_TSM_AP6 0xF0BE ++#define F367_OFDM_TSM_AP_6 0xF0BE00FF ++ ++/* TSM_AP7 */ ++#define R367_OFDM_TSM_AP7 0xF0BF ++#define F367_OFDM_MEM_SELECT_BYTE 0xF0BF00FF ++ ++/* TSTRES */ ++#define R367_TSTRES 0xF0C0 ++#define F367_FRES_DISPLAY 0xF0C00080 ++#define F367_FRES_FIFO_AD 0xF0C00020 ++#define F367_FRESRS 0xF0C00010 ++#define F367_FRESACS 0xF0C00008 ++#define F367_FRESFEC 0xF0C00004 ++#define F367_FRES_PRIF 0xF0C00002 ++#define F367_FRESCORE 0xF0C00001 ++ ++/* ANACTRL */ ++#define R367_ANACTRL 0xF0C1 ++#define F367_BYPASS_XTAL 0xF0C10040 ++#define F367_BYPASS_PLLXN 0xF0C1000C ++#define F367_DIS_PAD_OSC 0xF0C10002 ++#define F367_STDBY_PLLXN 0xF0C10001 ++ ++/* TSTBUS */ ++#define R367_TSTBUS 0xF0C2 ++#define F367_TS_BYTE_CLK_INV 0xF0C20080 ++#define F367_CFG_IP 0xF0C20070 ++#define F367_CFG_TST 0xF0C2000F ++ ++/* TSTRATE */ ++#define R367_TSTRATE 0xF0C6 ++#define F367_FORCEPHA 0xF0C60080 ++#define F367_FNEWPHA 0xF0C60010 ++#define F367_FROT90 0xF0C60008 ++#define F367_FR 0xF0C60007 ++ ++/* CONSTMODE */ ++#define R367_OFDM_CONSTMODE 0xF0CB ++#define F367_OFDM_TST_PRIF 0xF0CB00E0 ++#define F367_OFDM_CAR_TYPE 0xF0CB0018 ++#define F367_OFDM_CONST_MODE 0xF0CB0003 ++ ++/* CONSTCARR1 */ ++#define R367_OFDM_CONSTCARR1 0xF0CC ++#define F367_OFDM_CONST_CARR_LO 0xF0CC00FF ++ ++/* CONSTCARR2 */ ++#define R367_OFDM_CONSTCARR2 0xF0CD ++#define F367_OFDM_CONST_CARR_HI 0xF0CD001F ++ ++/* ICONSTEL */ ++#define R367_OFDM_ICONSTEL 0xF0CE ++#define F367_OFDM_PICONSTEL 0xF0CE00FF ++ ++/* QCONSTEL */ ++#define R367_OFDM_QCONSTEL 0xF0CF ++#define F367_OFDM_PQCONSTEL 0xF0CF00FF ++ ++/* TSTBISTRES0 */ ++#define R367_OFDM_TSTBISTRES0 0xF0D0 ++#define F367_OFDM_BEND_PPM 0xF0D00080 ++#define F367_OFDM_BBAD_PPM 0xF0D00040 ++#define F367_OFDM_BEND_FFTW 0xF0D00020 ++#define F367_OFDM_BBAD_FFTW 0xF0D00010 ++#define F367_OFDM_BEND_FFT_BUF 0xF0D00008 ++#define F367_OFDM_BBAD_FFT_BUF 0xF0D00004 ++#define F367_OFDM_BEND_SYR 0xF0D00002 ++#define F367_OFDM_BBAD_SYR 0xF0D00001 ++ ++/* TSTBISTRES1 */ ++#define R367_OFDM_TSTBISTRES1 0xF0D1 ++#define F367_OFDM_BEND_CHC_CP 0xF0D10080 ++#define F367_OFDM_BBAD_CHC_CP 0xF0D10040 ++#define F367_OFDM_BEND_CHCI 0xF0D10020 ++#define F367_OFDM_BBAD_CHCI 0xF0D10010 ++#define F367_OFDM_BEND_BDI 0xF0D10008 ++#define F367_OFDM_BBAD_BDI 0xF0D10004 ++#define F367_OFDM_BEND_SDI 0xF0D10002 ++#define F367_OFDM_BBAD_SDI 0xF0D10001 ++ ++/* TSTBISTRES2 */ ++#define R367_OFDM_TSTBISTRES2 0xF0D2 ++#define F367_OFDM_BEND_CHC_INC 0xF0D20080 ++#define F367_OFDM_BBAD_CHC_INC 0xF0D20040 ++#define F367_OFDM_BEND_CHC_SPP 0xF0D20020 ++#define F367_OFDM_BBAD_CHC_SPP 0xF0D20010 ++#define F367_OFDM_BEND_CHC_CPP 0xF0D20008 ++#define F367_OFDM_BBAD_CHC_CPP 0xF0D20004 ++#define F367_OFDM_BEND_CHC_SP 0xF0D20002 ++#define F367_OFDM_BBAD_CHC_SP 0xF0D20001 ++ ++/* TSTBISTRES3 */ ++#define R367_OFDM_TSTBISTRES3 0xF0D3 ++#define F367_OFDM_BEND_QAM 0xF0D30080 ++#define F367_OFDM_BBAD_QAM 0xF0D30040 ++#define F367_OFDM_BEND_SFEC_VIT 0xF0D30020 ++#define F367_OFDM_BBAD_SFEC_VIT 0xF0D30010 ++#define F367_OFDM_BEND_SFEC_DLINE 0xF0D30008 ++#define F367_OFDM_BBAD_SFEC_DLINE 0xF0D30004 ++#define F367_OFDM_BEND_SFEC_HW 0xF0D30002 ++#define F367_OFDM_BBAD_SFEC_HW 0xF0D30001 ++ ++/* RF_AGC1 */ ++#define R367_RF_AGC1 0xF0D4 ++#define F367_RF_AGC1_LEVEL_HI 0xF0D400FF ++ ++/* RF_AGC2 */ ++#define R367_RF_AGC2 0xF0D5 ++#define F367_REF_ADGP 0xF0D50080 ++#define F367_STDBY_ADCGP 0xF0D50020 ++#define F367_CHANNEL_SEL 0xF0D5001C ++#define F367_RF_AGC1_LEVEL_LO 0xF0D50003 ++ ++/* ANADIGCTRL */ ++#define R367_ANADIGCTRL 0xF0D7 ++#define F367_SEL_CLKDEM 0xF0D70020 ++#define F367_EN_BUFFER_Q 0xF0D70010 ++#define F367_EN_BUFFER_I 0xF0D70008 ++#define F367_ADC_RIS_EGDE 0xF0D70004 ++#define F367_SGN_ADC 0xF0D70002 ++#define F367_SEL_AD12_SYNC 0xF0D70001 ++ ++/* PLLMDIV */ ++#define R367_PLLMDIV 0xF0D8 ++#define F367_PLL_MDIV 0xF0D800FF ++ ++/* PLLNDIV */ ++#define R367_PLLNDIV 0xF0D9 ++#define F367_PLL_NDIV 0xF0D900FF ++ ++/* PLLSETUP */ ++#define R367_PLLSETUP 0xF0DA ++#define F367_PLL_PDIV 0xF0DA0070 ++#define F367_PLL_KDIV 0xF0DA000F ++ ++/* DUAL_AD12 */ ++#define R367_DUAL_AD12 0xF0DB ++#define F367_FS20M 0xF0DB0020 ++#define F367_FS50M 0xF0DB0010 ++#define F367_INMODE0 0xF0DB0008 ++#define F367_POFFQ 0xF0DB0004 ++#define F367_POFFI 0xF0DB0002 ++#define F367_INMODE1 0xF0DB0001 ++ ++/* TSTBIST */ ++#define R367_TSTBIST 0xF0DC ++#define F367_TST_BYP_CLK 0xF0DC0080 ++#define F367_TST_GCLKENA_STD 0xF0DC0040 ++#define F367_TST_GCLKENA 0xF0DC0020 ++#define F367_TST_MEMBIST 0xF0DC001F ++ ++/* PAD_COMP_CTRL */ ++#define R367_PAD_COMP_CTRL 0xF0DD ++#define F367_COMPTQ 0xF0DD0010 ++#define F367_COMPEN 0xF0DD0008 ++#define F367_FREEZE2 0xF0DD0004 ++#define F367_SLEEP_INHBT 0xF0DD0002 ++#define F367_CHIP_SLEEP 0xF0DD0001 ++ ++/* PAD_COMP_WR */ ++#define R367_PAD_COMP_WR 0xF0DE ++#define F367_WR_ASRC 0xF0DE007F ++ ++/* PAD_COMP_RD */ ++#define R367_PAD_COMP_RD 0xF0DF ++#define F367_COMPOK 0xF0DF0080 ++#define F367_RD_ASRC 0xF0DF007F ++ ++/* SYR_TARGET_FFTADJT_MSB */ ++#define R367_OFDM_SYR_TARGET_FFTADJT_MSB 0xF100 ++#define F367_OFDM_SYR_START 0xF1000080 ++#define F367_OFDM_SYR_TARGET_FFTADJ_HI 0xF100000F ++ ++/* SYR_TARGET_FFTADJT_LSB */ ++#define R367_OFDM_SYR_TARGET_FFTADJT_LSB 0xF101 ++#define F367_OFDM_SYR_TARGET_FFTADJ_LO 0xF10100FF ++ ++/* SYR_TARGET_CHCADJT_MSB */ ++#define R367_OFDM_SYR_TARGET_CHCADJT_MSB 0xF102 ++#define F367_OFDM_SYR_TARGET_CHCADJ_HI 0xF102000F ++ ++/* SYR_TARGET_CHCADJT_LSB */ ++#define R367_OFDM_SYR_TARGET_CHCADJT_LSB 0xF103 ++#define F367_OFDM_SYR_TARGET_CHCADJ_LO 0xF10300FF ++ ++/* SYR_FLAG */ ++#define R367_OFDM_SYR_FLAG 0xF104 ++#define F367_OFDM_TRIG_FLG1 0xF1040080 ++#define F367_OFDM_TRIG_FLG0 0xF1040040 ++#define F367_OFDM_FFT_FLG1 0xF1040008 ++#define F367_OFDM_FFT_FLG0 0xF1040004 ++#define F367_OFDM_CHC_FLG1 0xF1040002 ++#define F367_OFDM_CHC_FLG0 0xF1040001 ++ ++/* CRL_TARGET1 */ ++#define R367_OFDM_CRL_TARGET1 0xF105 ++#define F367_OFDM_CRL_START 0xF1050080 ++#define F367_OFDM_CRL_TARGET_VHI 0xF105000F ++ ++/* CRL_TARGET2 */ ++#define R367_OFDM_CRL_TARGET2 0xF106 ++#define F367_OFDM_CRL_TARGET_HI 0xF10600FF ++ ++/* CRL_TARGET3 */ ++#define R367_OFDM_CRL_TARGET3 0xF107 ++#define F367_OFDM_CRL_TARGET_LO 0xF10700FF ++ ++/* CRL_TARGET4 */ ++#define R367_OFDM_CRL_TARGET4 0xF108 ++#define F367_OFDM_CRL_TARGET_VLO 0xF10800FF ++ ++/* CRL_FLAG */ ++#define R367_OFDM_CRL_FLAG 0xF109 ++#define F367_OFDM_CRL_FLAG1 0xF1090002 ++#define F367_OFDM_CRL_FLAG0 0xF1090001 ++ ++/* TRL_TARGET1 */ ++#define R367_OFDM_TRL_TARGET1 0xF10A ++#define F367_OFDM_TRL_TARGET_HI 0xF10A00FF ++ ++/* TRL_TARGET2 */ ++#define R367_OFDM_TRL_TARGET2 0xF10B ++#define F367_OFDM_TRL_TARGET_LO 0xF10B00FF ++ ++/* TRL_CHC */ ++#define R367_OFDM_TRL_CHC 0xF10C ++#define F367_OFDM_TRL_START 0xF10C0080 ++#define F367_OFDM_CHC_START 0xF10C0040 ++#define F367_OFDM_TRL_FLAG1 0xF10C0002 ++#define F367_OFDM_TRL_FLAG0 0xF10C0001 ++ ++/* CHC_SNR_TARG */ ++#define R367_OFDM_CHC_SNR_TARG 0xF10D ++#define F367_OFDM_CHC_SNR_TARGET 0xF10D00FF ++ ++/* TOP_TRACK */ ++#define R367_OFDM_TOP_TRACK 0xF10E ++#define F367_OFDM_TOP_START 0xF10E0080 ++#define F367_OFDM_FIRST_FLAG 0xF10E0070 ++#define F367_OFDM_TOP_FLAG1 0xF10E0008 ++#define F367_OFDM_TOP_FLAG0 0xF10E0004 ++#define F367_OFDM_CHC_FLAG1 0xF10E0002 ++#define F367_OFDM_CHC_FLAG0 0xF10E0001 ++ ++/* TRACKER_FREE1 */ ++#define R367_OFDM_TRACKER_FREE1 0xF10F ++#define F367_OFDM_TRACKER_FREE_1 0xF10F00FF ++ ++/* ERROR_CRL1 */ ++#define R367_OFDM_ERROR_CRL1 0xF110 ++#define F367_OFDM_ERROR_CRL_VHI 0xF11000FF ++ ++/* ERROR_CRL2 */ ++#define R367_OFDM_ERROR_CRL2 0xF111 ++#define F367_OFDM_ERROR_CRL_HI 0xF11100FF ++ ++/* ERROR_CRL3 */ ++#define R367_OFDM_ERROR_CRL3 0xF112 ++#define F367_OFDM_ERROR_CRL_LOI 0xF11200FF ++ ++/* ERROR_CRL4 */ ++#define R367_OFDM_ERROR_CRL4 0xF113 ++#define F367_OFDM_ERROR_CRL_VLO 0xF11300FF ++ ++/* DEC_NCO1 */ ++#define R367_OFDM_DEC_NCO1 0xF114 ++#define F367_OFDM_DEC_NCO_VHI 0xF11400FF ++ ++/* DEC_NCO2 */ ++#define R367_OFDM_DEC_NCO2 0xF115 ++#define F367_OFDM_DEC_NCO_HI 0xF11500FF ++ ++/* DEC_NCO3 */ ++#define R367_OFDM_DEC_NCO3 0xF116 ++#define F367_OFDM_DEC_NCO_LO 0xF11600FF ++ ++/* SNR */ ++#define R367_OFDM_SNR 0xF117 ++#define F367_OFDM_SNRATIO 0xF11700FF ++ ++/* SYR_FFTADJ1 */ ++#define R367_OFDM_SYR_FFTADJ1 0xF118 ++#define F367_OFDM_SYR_FFTADJ_HI 0xF11800FF ++ ++/* SYR_FFTADJ2 */ ++#define R367_OFDM_SYR_FFTADJ2 0xF119 ++#define F367_OFDM_SYR_FFTADJ_LO 0xF11900FF ++ ++/* SYR_CHCADJ1 */ ++#define R367_OFDM_SYR_CHCADJ1 0xF11A ++#define F367_OFDM_SYR_CHCADJ_HI 0xF11A00FF ++ ++/* SYR_CHCADJ2 */ ++#define R367_OFDM_SYR_CHCADJ2 0xF11B ++#define F367_OFDM_SYR_CHCADJ_LO 0xF11B00FF ++ ++/* SYR_OFF */ ++#define R367_OFDM_SYR_OFF 0xF11C ++#define F367_OFDM_SYR_OFFSET 0xF11C00FF ++ ++/* PPM_OFFSET1 */ ++#define R367_OFDM_PPM_OFFSET1 0xF11D ++#define F367_OFDM_PPM_OFFSET_HI 0xF11D00FF ++ ++/* PPM_OFFSET2 */ ++#define R367_OFDM_PPM_OFFSET2 0xF11E ++#define F367_OFDM_PPM_OFFSET_LO 0xF11E00FF ++ ++/* TRACKER_FREE2 */ ++#define R367_OFDM_TRACKER_FREE2 0xF11F ++#define F367_OFDM_TRACKER_FREE_2 0xF11F00FF ++ ++/* DEBG_LT10 */ ++#define R367_OFDM_DEBG_LT10 0xF120 ++#define F367_OFDM_DEBUG_LT10 0xF12000FF ++ ++/* DEBG_LT11 */ ++#define R367_OFDM_DEBG_LT11 0xF121 ++#define F367_OFDM_DEBUG_LT11 0xF12100FF ++ ++/* DEBG_LT12 */ ++#define R367_OFDM_DEBG_LT12 0xF122 ++#define F367_OFDM_DEBUG_LT12 0xF12200FF ++ ++/* DEBG_LT13 */ ++#define R367_OFDM_DEBG_LT13 0xF123 ++#define F367_OFDM_DEBUG_LT13 0xF12300FF ++ ++/* DEBG_LT14 */ ++#define R367_OFDM_DEBG_LT14 0xF124 ++#define F367_OFDM_DEBUG_LT14 0xF12400FF ++ ++/* DEBG_LT15 */ ++#define R367_OFDM_DEBG_LT15 0xF125 ++#define F367_OFDM_DEBUG_LT15 0xF12500FF ++ ++/* DEBG_LT16 */ ++#define R367_OFDM_DEBG_LT16 0xF126 ++#define F367_OFDM_DEBUG_LT16 0xF12600FF ++ ++/* DEBG_LT17 */ ++#define R367_OFDM_DEBG_LT17 0xF127 ++#define F367_OFDM_DEBUG_LT17 0xF12700FF ++ ++/* DEBG_LT18 */ ++#define R367_OFDM_DEBG_LT18 0xF128 ++#define F367_OFDM_DEBUG_LT18 0xF12800FF ++ ++/* DEBG_LT19 */ ++#define R367_OFDM_DEBG_LT19 0xF129 ++#define F367_OFDM_DEBUG_LT19 0xF12900FF ++ ++/* DEBG_LT1A */ ++#define R367_OFDM_DEBG_LT1A 0xF12A ++#define F367_OFDM_DEBUG_LT1A 0xF12A00FF ++ ++/* DEBG_LT1B */ ++#define R367_OFDM_DEBG_LT1B 0xF12B ++#define F367_OFDM_DEBUG_LT1B 0xF12B00FF ++ ++/* DEBG_LT1C */ ++#define R367_OFDM_DEBG_LT1C 0xF12C ++#define F367_OFDM_DEBUG_LT1C 0xF12C00FF ++ ++/* DEBG_LT1D */ ++#define R367_OFDM_DEBG_LT1D 0xF12D ++#define F367_OFDM_DEBUG_LT1D 0xF12D00FF ++ ++/* DEBG_LT1E */ ++#define R367_OFDM_DEBG_LT1E 0xF12E ++#define F367_OFDM_DEBUG_LT1E 0xF12E00FF ++ ++/* DEBG_LT1F */ ++#define R367_OFDM_DEBG_LT1F 0xF12F ++#define F367_OFDM_DEBUG_LT1F 0xF12F00FF ++ ++/* RCCFGH */ ++#define R367_OFDM_RCCFGH 0xF200 ++#define F367_OFDM_TSRCFIFO_DVBCI 0xF2000080 ++#define F367_OFDM_TSRCFIFO_SERIAL 0xF2000040 ++#define F367_OFDM_TSRCFIFO_DISABLE 0xF2000020 ++#define F367_OFDM_TSFIFO_2TORC 0xF2000010 ++#define F367_OFDM_TSRCFIFO_HSGNLOUT 0xF2000008 ++#define F367_OFDM_TSRCFIFO_ERRMODE 0xF2000006 ++#define F367_OFDM_RCCFGH_0 0xF2000001 ++ ++/* RCCFGM */ ++#define R367_OFDM_RCCFGM 0xF201 ++#define F367_OFDM_TSRCFIFO_MANSPEED 0xF20100C0 ++#define F367_OFDM_TSRCFIFO_PERMDATA 0xF2010020 ++#define F367_OFDM_TSRCFIFO_NONEWSGNL 0xF2010010 ++#define F367_OFDM_RCBYTE_OVERSAMPLING 0xF201000E ++#define F367_OFDM_TSRCFIFO_INVDATA 0xF2010001 ++ ++/* RCCFGL */ ++#define R367_OFDM_RCCFGL 0xF202 ++#define F367_OFDM_TSRCFIFO_BCLKDEL1CK 0xF20200C0 ++#define F367_OFDM_RCCFGL_5 0xF2020020 ++#define F367_OFDM_TSRCFIFO_DUTY50 0xF2020010 ++#define F367_OFDM_TSRCFIFO_NSGNL2DATA 0xF2020008 ++#define F367_OFDM_TSRCFIFO_DISSERMUX 0xF2020004 ++#define F367_OFDM_RCCFGL_1 0xF2020002 ++#define F367_OFDM_TSRCFIFO_STOPCKDIS 0xF2020001 ++ ++/* RCINSDELH */ ++#define R367_OFDM_RCINSDELH 0xF203 ++#define F367_OFDM_TSRCDEL_SYNCBYTE 0xF2030080 ++#define F367_OFDM_TSRCDEL_XXHEADER 0xF2030040 ++#define F367_OFDM_TSRCDEL_BBHEADER 0xF2030020 ++#define F367_OFDM_TSRCDEL_DATAFIELD 0xF2030010 ++#define F367_OFDM_TSRCINSDEL_ISCR 0xF2030008 ++#define F367_OFDM_TSRCINSDEL_NPD 0xF2030004 ++#define F367_OFDM_TSRCINSDEL_RSPARITY 0xF2030002 ++#define F367_OFDM_TSRCINSDEL_CRC8 0xF2030001 ++ ++/* RCINSDELM */ ++#define R367_OFDM_RCINSDELM 0xF204 ++#define F367_OFDM_TSRCINS_BBPADDING 0xF2040080 ++#define F367_OFDM_TSRCINS_BCHFEC 0xF2040040 ++#define F367_OFDM_TSRCINS_LDPCFEC 0xF2040020 ++#define F367_OFDM_TSRCINS_EMODCOD 0xF2040010 ++#define F367_OFDM_TSRCINS_TOKEN 0xF2040008 ++#define F367_OFDM_TSRCINS_XXXERR 0xF2040004 ++#define F367_OFDM_TSRCINS_MATYPE 0xF2040002 ++#define F367_OFDM_TSRCINS_UPL 0xF2040001 ++ ++/* RCINSDELL */ ++#define R367_OFDM_RCINSDELL 0xF205 ++#define F367_OFDM_TSRCINS_DFL 0xF2050080 ++#define F367_OFDM_TSRCINS_SYNCD 0xF2050040 ++#define F367_OFDM_TSRCINS_BLOCLEN 0xF2050020 ++#define F367_OFDM_TSRCINS_SIGPCOUNT 0xF2050010 ++#define F367_OFDM_TSRCINS_FIFO 0xF2050008 ++#define F367_OFDM_TSRCINS_REALPACK 0xF2050004 ++#define F367_OFDM_TSRCINS_TSCONFIG 0xF2050002 ++#define F367_OFDM_TSRCINS_LATENCY 0xF2050001 ++ ++/* RCSTATUS */ ++#define R367_OFDM_RCSTATUS 0xF206 ++#define F367_OFDM_TSRCFIFO_LINEOK 0xF2060080 ++#define F367_OFDM_TSRCFIFO_ERROR 0xF2060040 ++#define F367_OFDM_TSRCFIFO_DATA7 0xF2060020 ++#define F367_OFDM_RCSTATUS_4 0xF2060010 ++#define F367_OFDM_TSRCFIFO_DEMODSEL 0xF2060008 ++#define F367_OFDM_TSRC1FIFOSPEED_STORE 0xF2060004 ++#define F367_OFDM_RCSTATUS_1 0xF2060002 ++#define F367_OFDM_TSRCSERIAL_IMPOSSIBLE 0xF2060001 ++ ++/* RCSPEED */ ++#define R367_OFDM_RCSPEED 0xF207 ++#define F367_OFDM_TSRCFIFO_OUTSPEED 0xF20700FF ++ ++/* RCDEBUGM */ ++#define R367_OFDM_RCDEBUGM 0xF208 ++#define F367_OFDM_SD_UNSYNC 0xF2080080 ++#define F367_OFDM_ULFLOCK_DETECTM 0xF2080040 ++#define F367_OFDM_SUL_SELECTOS 0xF2080020 ++#define F367_OFDM_DILUL_NOSCRBLE 0xF2080010 ++#define F367_OFDM_NUL_SCRB 0xF2080008 ++#define F367_OFDM_UL_SCRB 0xF2080004 ++#define F367_OFDM_SCRAULBAD 0xF2080002 ++#define F367_OFDM_SCRAUL_UNSYNC 0xF2080001 ++ ++/* RCDEBUGL */ ++#define R367_OFDM_RCDEBUGL 0xF209 ++#define F367_OFDM_RS_ERR 0xF2090080 ++#define F367_OFDM_LLFLOCK_DETECTM 0xF2090040 ++#define F367_OFDM_NOT_SUL_SELECTOS 0xF2090020 ++#define F367_OFDM_DILLL_NOSCRBLE 0xF2090010 ++#define F367_OFDM_NLL_SCRB 0xF2090008 ++#define F367_OFDM_LL_SCRB 0xF2090004 ++#define F367_OFDM_SCRALLBAD 0xF2090002 ++#define F367_OFDM_SCRALL_UNSYNC 0xF2090001 ++ ++/* RCOBSCFG */ ++#define R367_OFDM_RCOBSCFG 0xF20A ++#define F367_OFDM_TSRCFIFO_OBSCFG 0xF20A00FF ++ ++/* RCOBSM */ ++#define R367_OFDM_RCOBSM 0xF20B ++#define F367_OFDM_TSRCFIFO_OBSDATA_HI 0xF20B00FF ++ ++/* RCOBSL */ ++#define R367_OFDM_RCOBSL 0xF20C ++#define F367_OFDM_TSRCFIFO_OBSDATA_LO 0xF20C00FF ++ ++/* RCFECSPY */ ++#define R367_OFDM_RCFECSPY 0xF210 ++#define F367_OFDM_SPYRC_ENABLE 0xF2100080 ++#define F367_OFDM_RCNO_SYNCBYTE 0xF2100040 ++#define F367_OFDM_RCSERIAL_MODE 0xF2100020 ++#define F367_OFDM_RCUNUSUAL_PACKET 0xF2100010 ++#define F367_OFDM_BERRCMETER_DATAMODE 0xF210000C ++#define F367_OFDM_BERRCMETER_LMODE 0xF2100002 ++#define F367_OFDM_BERRCMETER_RESET 0xF2100001 ++ ++/* RCFSPYCFG */ ++#define R367_OFDM_RCFSPYCFG 0xF211 ++#define F367_OFDM_FECSPYRC_INPUT 0xF21100C0 ++#define F367_OFDM_RCRST_ON_ERROR 0xF2110020 ++#define F367_OFDM_RCONE_SHOT 0xF2110010 ++#define F367_OFDM_RCI2C_MODE 0xF211000C ++#define F367_OFDM_SPYRC_HSTERESIS 0xF2110003 ++ ++/* RCFSPYDATA */ ++#define R367_OFDM_RCFSPYDATA 0xF212 ++#define F367_OFDM_SPYRC_STUFFING 0xF2120080 ++#define F367_OFDM_RCNOERR_PKTJITTER 0xF2120040 ++#define F367_OFDM_SPYRC_CNULLPKT 0xF2120020 ++#define F367_OFDM_SPYRC_OUTDATA_MODE 0xF212001F ++ ++/* RCFSPYOUT */ ++#define R367_OFDM_RCFSPYOUT 0xF213 ++#define F367_OFDM_FSPYRC_DIRECT 0xF2130080 ++#define F367_OFDM_RCFSPYOUT_6 0xF2130040 ++#define F367_OFDM_SPYRC_OUTDATA_BUS 0xF2130038 ++#define F367_OFDM_RCSTUFF_MODE 0xF2130007 ++ ++/* RCFSTATUS */ ++#define R367_OFDM_RCFSTATUS 0xF214 ++#define F367_OFDM_SPYRC_ENDSIM 0xF2140080 ++#define F367_OFDM_RCVALID_SIM 0xF2140040 ++#define F367_OFDM_RCFOUND_SIGNAL 0xF2140020 ++#define F367_OFDM_RCDSS_SYNCBYTE 0xF2140010 ++#define F367_OFDM_RCRESULT_STATE 0xF214000F ++ ++/* RCFGOODPACK */ ++#define R367_OFDM_RCFGOODPACK 0xF215 ++#define F367_OFDM_RCGOOD_PACKET 0xF21500FF ++ ++/* RCFPACKCNT */ ++#define R367_OFDM_RCFPACKCNT 0xF216 ++#define F367_OFDM_RCPACKET_COUNTER 0xF21600FF ++ ++/* RCFSPYMISC */ ++#define R367_OFDM_RCFSPYMISC 0xF217 ++#define F367_OFDM_RCLABEL_COUNTER 0xF21700FF ++ ++/* RCFBERCPT4 */ ++#define R367_OFDM_RCFBERCPT4 0xF218 ++#define F367_OFDM_FBERRCMETER_CPT_MMMMSB 0xF21800FF ++ ++/* RCFBERCPT3 */ ++#define R367_OFDM_RCFBERCPT3 0xF219 ++#define F367_OFDM_FBERRCMETER_CPT_MMMSB 0xF21900FF ++ ++/* RCFBERCPT2 */ ++#define R367_OFDM_RCFBERCPT2 0xF21A ++#define F367_OFDM_FBERRCMETER_CPT_MMSB 0xF21A00FF ++ ++/* RCFBERCPT1 */ ++#define R367_OFDM_RCFBERCPT1 0xF21B ++#define F367_OFDM_FBERRCMETER_CPT_MSB 0xF21B00FF ++ ++/* RCFBERCPT0 */ ++#define R367_OFDM_RCFBERCPT0 0xF21C ++#define F367_OFDM_FBERRCMETER_CPT_LSB 0xF21C00FF ++ ++/* RCFBERERR2 */ ++#define R367_OFDM_RCFBERERR2 0xF21D ++#define F367_OFDM_FBERRCMETER_ERR_HI 0xF21D00FF ++ ++/* RCFBERERR1 */ ++#define R367_OFDM_RCFBERERR1 0xF21E ++#define F367_OFDM_FBERRCMETER_ERR 0xF21E00FF ++ ++/* RCFBERERR0 */ ++#define R367_OFDM_RCFBERERR0 0xF21F ++#define F367_OFDM_FBERRCMETER_ERR_LO 0xF21F00FF ++ ++/* RCFSTATESM */ ++#define R367_OFDM_RCFSTATESM 0xF220 ++#define F367_OFDM_RCRSTATE_F 0xF2200080 ++#define F367_OFDM_RCRSTATE_E 0xF2200040 ++#define F367_OFDM_RCRSTATE_D 0xF2200020 ++#define F367_OFDM_RCRSTATE_C 0xF2200010 ++#define F367_OFDM_RCRSTATE_B 0xF2200008 ++#define F367_OFDM_RCRSTATE_A 0xF2200004 ++#define F367_OFDM_RCRSTATE_9 0xF2200002 ++#define F367_OFDM_RCRSTATE_8 0xF2200001 ++ ++/* RCFSTATESL */ ++#define R367_OFDM_RCFSTATESL 0xF221 ++#define F367_OFDM_RCRSTATE_7 0xF2210080 ++#define F367_OFDM_RCRSTATE_6 0xF2210040 ++#define F367_OFDM_RCRSTATE_5 0xF2210020 ++#define F367_OFDM_RCRSTATE_4 0xF2210010 ++#define F367_OFDM_RCRSTATE_3 0xF2210008 ++#define F367_OFDM_RCRSTATE_2 0xF2210004 ++#define F367_OFDM_RCRSTATE_1 0xF2210002 ++#define F367_OFDM_RCRSTATE_0 0xF2210001 ++ ++/* RCFSPYBER */ ++#define R367_OFDM_RCFSPYBER 0xF222 ++#define F367_OFDM_RCFSPYBER_7 0xF2220080 ++#define F367_OFDM_SPYRCOBS_XORREAD 0xF2220040 ++#define F367_OFDM_FSPYRCBER_OBSMODE 0xF2220020 ++#define F367_OFDM_FSPYRCBER_SYNCBYT 0xF2220010 ++#define F367_OFDM_FSPYRCBER_UNSYNC 0xF2220008 ++#define F367_OFDM_FSPYRCBER_CTIME 0xF2220007 ++ ++/* RCFSPYDISTM */ ++#define R367_OFDM_RCFSPYDISTM 0xF223 ++#define F367_OFDM_RCPKTTIME_DISTANCE_HI 0xF22300FF ++ ++/* RCFSPYDISTL */ ++#define R367_OFDM_RCFSPYDISTL 0xF224 ++#define F367_OFDM_RCPKTTIME_DISTANCE_LO 0xF22400FF ++ ++/* RCFSPYOBS7 */ ++#define R367_OFDM_RCFSPYOBS7 0xF228 ++#define F367_OFDM_RCSPYOBS_SPYFAIL 0xF2280080 ++#define F367_OFDM_RCSPYOBS_SPYFAIL1 0xF2280040 ++#define F367_OFDM_RCSPYOBS_ERROR 0xF2280020 ++#define F367_OFDM_RCSPYOBS_STROUT 0xF2280010 ++#define F367_OFDM_RCSPYOBS_RESULTSTATE1 0xF228000F ++ ++/* RCFSPYOBS6 */ ++#define R367_OFDM_RCFSPYOBS6 0xF229 ++#define F367_OFDM_RCSPYOBS_RESULTSTATE0 0xF22900F0 ++#define F367_OFDM_RCSPYOBS_RESULTSTATEM1 0xF229000F ++ ++/* RCFSPYOBS5 */ ++#define R367_OFDM_RCFSPYOBS5 0xF22A ++#define F367_OFDM_RCSPYOBS_BYTEOFPACKET1 0xF22A00FF ++ ++/* RCFSPYOBS4 */ ++#define R367_OFDM_RCFSPYOBS4 0xF22B ++#define F367_OFDM_RCSPYOBS_BYTEVALUE1 0xF22B00FF ++ ++/* RCFSPYOBS3 */ ++#define R367_OFDM_RCFSPYOBS3 0xF22C ++#define F367_OFDM_RCSPYOBS_DATA1 0xF22C00FF ++ ++/* RCFSPYOBS2 */ ++#define R367_OFDM_RCFSPYOBS2 0xF22D ++#define F367_OFDM_RCSPYOBS_DATA0 0xF22D00FF ++ ++/* RCFSPYOBS1 */ ++#define R367_OFDM_RCFSPYOBS1 0xF22E ++#define F367_OFDM_RCSPYOBS_DATAM1 0xF22E00FF ++ ++/* RCFSPYOBS0 */ ++#define R367_OFDM_RCFSPYOBS0 0xF22F ++#define F367_OFDM_RCSPYOBS_DATAM2 0xF22F00FF ++ ++/* TSGENERAL */ ++#define R367_TSGENERAL 0xF230 ++#define F367_TSGENERAL_7 0xF2300080 ++#define F367_TSGENERAL_6 0xF2300040 ++#define F367_TSFIFO_BCLK1ALL 0xF2300020 ++#define F367_TSGENERAL_4 0xF2300010 ++#define F367_MUXSTREAM_OUTMODE 0xF2300008 ++#define F367_TSFIFO_PERMPARAL 0xF2300006 ++#define F367_RST_REEDSOLO 0xF2300001 ++ ++/* RC1SPEED */ ++#define R367_RC1SPEED 0xF231 ++#define F367_TSRCFIFO1_OUTSPEED 0xF23100FF ++ ++/* TSGSTATUS */ ++#define R367_TSGSTATUS 0xF232 ++#define F367_TSGSTATUS_7 0xF2320080 ++#define F367_TSGSTATUS_6 0xF2320040 ++#define F367_RSMEM_FULL 0xF2320020 ++#define F367_RS_MULTCALC 0xF2320010 ++#define F367_RSIN_OVERTIME 0xF2320008 ++#define F367_TSFIFO3_DEMODSEL 0xF2320004 ++#define F367_TSFIFO2_DEMODSEL 0xF2320002 ++#define F367_TSFIFO1_DEMODSEL 0xF2320001 ++ ++ ++/* FECM */ ++#define R367_OFDM_FECM 0xF233 ++#define F367_OFDM_DSS_DVB 0xF2330080 ++#define F367_OFDM_DEMOD_BYPASS 0xF2330040 ++#define F367_OFDM_CMP_SLOWMODE 0xF2330020 ++#define F367_OFDM_DSS_SRCH 0xF2330010 ++#define F367_OFDM_FECM_3 0xF2330008 ++#define F367_OFDM_DIFF_MODEVIT 0xF2330004 ++#define F367_OFDM_SYNCVIT 0xF2330002 ++#define F367_OFDM_I2CSYM 0xF2330001 ++ ++/* VTH12 */ ++#define R367_OFDM_VTH12 0xF234 ++#define F367_OFDM_VTH_12 0xF23400FF ++ ++/* VTH23 */ ++#define R367_OFDM_VTH23 0xF235 ++#define F367_OFDM_VTH_23 0xF23500FF ++ ++/* VTH34 */ ++#define R367_OFDM_VTH34 0xF236 ++#define F367_OFDM_VTH_34 0xF23600FF ++ ++/* VTH56 */ ++#define R367_OFDM_VTH56 0xF237 ++#define F367_OFDM_VTH_56 0xF23700FF ++ ++/* VTH67 */ ++#define R367_OFDM_VTH67 0xF238 ++#define F367_OFDM_VTH_67 0xF23800FF ++ ++/* VTH78 */ ++#define R367_OFDM_VTH78 0xF239 ++#define F367_OFDM_VTH_78 0xF23900FF ++ ++/* VITCURPUN */ ++#define R367_OFDM_VITCURPUN 0xF23A ++#define F367_OFDM_VIT_MAPPING 0xF23A00E0 ++#define F367_OFDM_VIT_CURPUN 0xF23A001F ++ ++/* VERROR */ ++#define R367_OFDM_VERROR 0xF23B ++#define F367_OFDM_REGERR_VIT 0xF23B00FF ++ ++/* PRVIT */ ++#define R367_OFDM_PRVIT 0xF23C ++#define F367_OFDM_PRVIT_7 0xF23C0080 ++#define F367_OFDM_DIS_VTHLOCK 0xF23C0040 ++#define F367_OFDM_E7_8VIT 0xF23C0020 ++#define F367_OFDM_E6_7VIT 0xF23C0010 ++#define F367_OFDM_E5_6VIT 0xF23C0008 ++#define F367_OFDM_E3_4VIT 0xF23C0004 ++#define F367_OFDM_E2_3VIT 0xF23C0002 ++#define F367_OFDM_E1_2VIT 0xF23C0001 ++ ++/* VAVSRVIT */ ++#define R367_OFDM_VAVSRVIT 0xF23D ++#define F367_OFDM_AMVIT 0xF23D0080 ++#define F367_OFDM_FROZENVIT 0xF23D0040 ++#define F367_OFDM_SNVIT 0xF23D0030 ++#define F367_OFDM_TOVVIT 0xF23D000C ++#define F367_OFDM_HYPVIT 0xF23D0003 ++ ++/* VSTATUSVIT */ ++#define R367_OFDM_VSTATUSVIT 0xF23E ++#define F367_OFDM_VITERBI_ON 0xF23E0080 ++#define F367_OFDM_END_LOOPVIT 0xF23E0040 ++#define F367_OFDM_VITERBI_DEPRF 0xF23E0020 ++#define F367_OFDM_PRFVIT 0xF23E0010 ++#define F367_OFDM_LOCKEDVIT 0xF23E0008 ++#define F367_OFDM_VITERBI_DELOCK 0xF23E0004 ++#define F367_OFDM_VIT_DEMODSEL 0xF23E0002 ++#define F367_OFDM_VITERBI_COMPOUT 0xF23E0001 ++ ++/* VTHINUSE */ ++#define R367_OFDM_VTHINUSE 0xF23F ++#define F367_OFDM_VIT_INUSE 0xF23F00FF ++ ++/* KDIV12 */ ++#define R367_OFDM_KDIV12 0xF240 ++#define F367_OFDM_KDIV12_MANUAL 0xF2400080 ++#define F367_OFDM_K_DIVIDER_12 0xF240007F ++ ++/* KDIV23 */ ++#define R367_OFDM_KDIV23 0xF241 ++#define F367_OFDM_KDIV23_MANUAL 0xF2410080 ++#define F367_OFDM_K_DIVIDER_23 0xF241007F ++ ++/* KDIV34 */ ++#define R367_OFDM_KDIV34 0xF242 ++#define F367_OFDM_KDIV34_MANUAL 0xF2420080 ++#define F367_OFDM_K_DIVIDER_34 0xF242007F ++ ++/* KDIV56 */ ++#define R367_OFDM_KDIV56 0xF243 ++#define F367_OFDM_KDIV56_MANUAL 0xF2430080 ++#define F367_OFDM_K_DIVIDER_56 0xF243007F ++ ++/* KDIV67 */ ++#define R367_OFDM_KDIV67 0xF244 ++#define F367_OFDM_KDIV67_MANUAL 0xF2440080 ++#define F367_OFDM_K_DIVIDER_67 0xF244007F ++ ++/* KDIV78 */ ++#define R367_OFDM_KDIV78 0xF245 ++#define F367_OFDM_KDIV78_MANUAL 0xF2450080 ++#define F367_OFDM_K_DIVIDER_78 0xF245007F ++ ++/* SIGPOWER */ ++#define R367_OFDM_SIGPOWER 0xF246 ++#define F367_OFDM_SIGPOWER_MANUAL 0xF2460080 ++#define F367_OFDM_SIG_POWER 0xF246007F ++ ++/* DEMAPVIT */ ++#define R367_OFDM_DEMAPVIT 0xF247 ++#define F367_OFDM_DEMAPVIT_7 0xF2470080 ++#define F367_OFDM_K_DIVIDER_VIT 0xF247007F ++ ++/* VITSCALE */ ++#define R367_OFDM_VITSCALE 0xF248 ++#define F367_OFDM_NVTH_NOSRANGE 0xF2480080 ++#define F367_OFDM_VERROR_MAXMODE 0xF2480040 ++#define F367_OFDM_KDIV_MODE 0xF2480030 ++#define F367_OFDM_NSLOWSN_LOCKED 0xF2480008 ++#define F367_OFDM_DELOCK_PRFLOSS 0xF2480004 ++#define F367_OFDM_DIS_RSFLOCK 0xF2480002 ++#define F367_OFDM_VITSCALE_0 0xF2480001 ++ ++/* FFEC1PRG */ ++#define R367_OFDM_FFEC1PRG 0xF249 ++#define F367_OFDM_FDSS_DVB 0xF2490080 ++#define F367_OFDM_FDSS_SRCH 0xF2490040 ++#define F367_OFDM_FFECPROG_5 0xF2490020 ++#define F367_OFDM_FFECPROG_4 0xF2490010 ++#define F367_OFDM_FFECPROG_3 0xF2490008 ++#define F367_OFDM_FFECPROG_2 0xF2490004 ++#define F367_OFDM_FTS1_DISABLE 0xF2490002 ++#define F367_OFDM_FTS2_DISABLE 0xF2490001 ++ ++/* FVITCURPUN */ ++#define R367_OFDM_FVITCURPUN 0xF24A ++#define F367_OFDM_FVIT_MAPPING 0xF24A00E0 ++#define F367_OFDM_FVIT_CURPUN 0xF24A001F ++ ++/* FVERROR */ ++#define R367_OFDM_FVERROR 0xF24B ++#define F367_OFDM_FREGERR_VIT 0xF24B00FF ++ ++/* FVSTATUSVIT */ ++#define R367_OFDM_FVSTATUSVIT 0xF24C ++#define F367_OFDM_FVITERBI_ON 0xF24C0080 ++#define F367_OFDM_F1END_LOOPVIT 0xF24C0040 ++#define F367_OFDM_FVITERBI_DEPRF 0xF24C0020 ++#define F367_OFDM_FPRFVIT 0xF24C0010 ++#define F367_OFDM_FLOCKEDVIT 0xF24C0008 ++#define F367_OFDM_FVITERBI_DELOCK 0xF24C0004 ++#define F367_OFDM_FVIT_DEMODSEL 0xF24C0002 ++#define F367_OFDM_FVITERBI_COMPOUT 0xF24C0001 ++ ++/* DEBUG_LT1 */ ++#define R367_OFDM_DEBUG_LT1 0xF24D ++#define F367_OFDM_DBG_LT1 0xF24D00FF ++ ++/* DEBUG_LT2 */ ++#define R367_OFDM_DEBUG_LT2 0xF24E ++#define F367_OFDM_DBG_LT2 0xF24E00FF ++ ++/* DEBUG_LT3 */ ++#define R367_OFDM_DEBUG_LT3 0xF24F ++#define F367_OFDM_DBG_LT3 0xF24F00FF ++ ++ /* TSTSFMET */ ++#define R367_OFDM_TSTSFMET 0xF250 ++#define F367_OFDM_TSTSFEC_METRIQUES 0xF25000FF ++ ++ /* SELOUT */ ++#define R367_OFDM_SELOUT 0xF252 ++#define F367_OFDM_EN_SYNC 0xF2520080 ++#define F367_OFDM_EN_TBUSDEMAP 0xF2520040 ++#define F367_OFDM_SELOUT_5 0xF2520020 ++#define F367_OFDM_SELOUT_4 0xF2520010 ++#define F367_OFDM_TSTSYNCHRO_MODE 0xF2520002 ++ ++ /* TSYNC */ ++#define R367_OFDM_TSYNC 0xF253 ++#define F367_OFDM_CURPUN_INCMODE 0xF2530080 ++#define F367_OFDM_CERR_TSTMODE 0xF2530040 ++#define F367_OFDM_SHIFTSOF_MODE 0xF2530030 ++#define F367_OFDM_SLOWPHA_MODE 0xF2530008 ++#define F367_OFDM_PXX_BYPALL 0xF2530004 ++#define F367_OFDM_FROTA45_FIRST 0xF2530002 ++#define F367_OFDM_TST_BCHERROR 0xF2530001 ++ ++ /* TSTERR */ ++#define R367_OFDM_TSTERR 0xF254 ++#define F367_OFDM_TST_LONGPKT 0xF2540080 ++#define F367_OFDM_TST_ISSYION 0xF2540040 ++#define F367_OFDM_TST_NPDON 0xF2540020 ++#define F367_OFDM_TSTERR_4 0xF2540010 ++#define F367_OFDM_TRACEBACK_MODE 0xF2540008 ++#define F367_OFDM_TST_RSPARITY 0xF2540004 ++#define F367_OFDM_METRIQUE_MODE 0xF2540003 ++ ++ /* TSFSYNC */ ++#define R367_OFDM_TSFSYNC 0xF255 ++#define F367_OFDM_EN_SFECSYNC 0xF2550080 ++#define F367_OFDM_EN_SFECDEMAP 0xF2550040 ++#define F367_OFDM_SFCERR_TSTMODE 0xF2550020 ++#define F367_OFDM_SFECPXX_BYPALL 0xF2550010 ++#define F367_OFDM_SFECTSTSYNCHRO_MODE 0xF255000F ++ ++ /* TSTSFERR */ ++#define R367_OFDM_TSTSFERR 0xF256 ++#define F367_OFDM_TSTSTERR_7 0xF2560080 ++#define F367_OFDM_TSTSTERR_6 0xF2560040 ++#define F367_OFDM_TSTSTERR_5 0xF2560020 ++#define F367_OFDM_TSTSTERR_4 0xF2560010 ++#define F367_OFDM_SFECTRACEBACK_MODE 0xF2560008 ++#define F367_OFDM_SFEC_NCONVPROG 0xF2560004 ++#define F367_OFDM_SFECMETRIQUE_MODE 0xF2560003 ++ ++ /* TSTTSSF1 */ ++#define R367_OFDM_TSTTSSF1 0xF258 ++#define F367_OFDM_TSTERSSF 0xF2580080 ++#define F367_OFDM_TSTTSSFEN 0xF2580040 ++#define F367_OFDM_SFEC_OUTMODE 0xF2580030 ++#define F367_OFDM_XLSF_NOFTHRESHOLD 0xF2580008 ++#define F367_OFDM_TSTTSSF_STACKSEL 0xF2580007 ++ ++ /* TSTTSSF2 */ ++#define R367_OFDM_TSTTSSF2 0xF259 ++#define F367_OFDM_DILSF_DBBHEADER 0xF2590080 ++#define F367_OFDM_TSTTSSF_DISBUG 0xF2590040 ++#define F367_OFDM_TSTTSSF_NOBADSTART 0xF2590020 ++#define F367_OFDM_TSTTSSF_SELECT 0xF259001F ++ ++ /* TSTTSSF3 */ ++#define R367_OFDM_TSTTSSF3 0xF25A ++#define F367_OFDM_TSTTSSF3_7 0xF25A0080 ++#define F367_OFDM_TSTTSSF3_6 0xF25A0040 ++#define F367_OFDM_TSTTSSF3_5 0xF25A0020 ++#define F367_OFDM_TSTTSSF3_4 0xF25A0010 ++#define F367_OFDM_TSTTSSF3_3 0xF25A0008 ++#define F367_OFDM_TSTTSSF3_2 0xF25A0004 ++#define F367_OFDM_TSTTSSF3_1 0xF25A0002 ++#define F367_OFDM_DISSF_CLKENABLE 0xF25A0001 ++ ++ /* TSTTS1 */ ++#define R367_OFDM_TSTTS1 0xF25C ++#define F367_OFDM_TSTERS 0xF25C0080 ++#define F367_OFDM_TSFIFO_DSSSYNCB 0xF25C0040 ++#define F367_OFDM_TSTTS_FSPYBEFRS 0xF25C0020 ++#define F367_OFDM_NFORCE_SYNCBYTE 0xF25C0010 ++#define F367_OFDM_XL_NOFTHRESHOLD 0xF25C0008 ++#define F367_OFDM_TSTTS_FRFORCEPKT 0xF25C0004 ++#define F367_OFDM_DESCR_NOTAUTO 0xF25C0002 ++#define F367_OFDM_TSTTSEN 0xF25C0001 ++ ++ /* TSTTS2 */ ++#define R367_OFDM_TSTTS2 0xF25D ++#define F367_OFDM_DIL_DBBHEADER 0xF25D0080 ++#define F367_OFDM_TSTTS_NOBADXXX 0xF25D0040 ++#define F367_OFDM_TSFIFO_DELSPEEDUP 0xF25D0020 ++#define F367_OFDM_TSTTS_SELECT 0xF25D001F ++ ++ /* TSTTS3 */ ++#define R367_OFDM_TSTTS3 0xF25E ++#define F367_OFDM_TSTTS_NOPKTGAIN 0xF25E0080 ++#define F367_OFDM_TSTTS_NOPKTENE 0xF25E0040 ++#define F367_OFDM_TSTTS_ISOLATION 0xF25E0020 ++#define F367_OFDM_TSTTS_DISBUG 0xF25E0010 ++#define F367_OFDM_TSTTS_NOBADSTART 0xF25E0008 ++#define F367_OFDM_TSTTS_STACKSEL 0xF25E0007 ++ ++ /* TSTTS4 */ ++#define R367_OFDM_TSTTS4 0xF25F ++#define F367_OFDM_TSTTS4_7 0xF25F0080 ++#define F367_OFDM_TSTTS4_6 0xF25F0040 ++#define F367_OFDM_TSTTS4_5 0xF25F0020 ++#define F367_OFDM_TSTTS_DISDSTATE 0xF25F0010 ++#define F367_OFDM_TSTTS_FASTNOSYNC 0xF25F0008 ++#define F367_OFDM_EXT_FECSPYIN 0xF25F0004 ++#define F367_OFDM_TSTTS_NODPZERO 0xF25F0002 ++#define F367_OFDM_TSTTS_NODIV3 0xF25F0001 ++ ++ /* TSTTSRC */ ++#define R367_OFDM_TSTTSRC 0xF26C ++#define F367_OFDM_TSTTSRC_7 0xF26C0080 ++#define F367_OFDM_TSRCFIFO_DSSSYNCB 0xF26C0040 ++#define F367_OFDM_TSRCFIFO_DPUNACTIVE 0xF26C0020 ++#define F367_OFDM_TSRCFIFO_DELSPEEDUP 0xF26C0010 ++#define F367_OFDM_TSTTSRC_NODIV3 0xF26C0008 ++#define F367_OFDM_TSTTSRC_FRFORCEPKT 0xF26C0004 ++#define F367_OFDM_SAT25_SDDORIGINE 0xF26C0002 ++#define F367_OFDM_TSTTSRC_INACTIVE 0xF26C0001 ++ ++ /* TSTTSRS */ ++#define R367_OFDM_TSTTSRS 0xF26D ++#define F367_OFDM_TSTTSRS_7 0xF26D0080 ++#define F367_OFDM_TSTTSRS_6 0xF26D0040 ++#define F367_OFDM_TSTTSRS_5 0xF26D0020 ++#define F367_OFDM_TSTTSRS_4 0xF26D0010 ++#define F367_OFDM_TSTTSRS_3 0xF26D0008 ++#define F367_OFDM_TSTTSRS_2 0xF26D0004 ++#define F367_OFDM_TSTRS_DISRS2 0xF26D0002 ++#define F367_OFDM_TSTRS_DISRS1 0xF26D0001 ++ ++/* TSSTATEM */ ++#define R367_OFDM_TSSTATEM 0xF270 ++#define F367_OFDM_TSDIL_ON 0xF2700080 ++#define F367_OFDM_TSSKIPRS_ON 0xF2700040 ++#define F367_OFDM_TSRS_ON 0xF2700020 ++#define F367_OFDM_TSDESCRAMB_ON 0xF2700010 ++#define F367_OFDM_TSFRAME_MODE 0xF2700008 ++#define F367_OFDM_TS_DISABLE 0xF2700004 ++#define F367_OFDM_TSACM_MODE 0xF2700002 ++#define F367_OFDM_TSOUT_NOSYNC 0xF2700001 ++ ++/* TSSTATEL */ ++#define R367_OFDM_TSSTATEL 0xF271 ++#define F367_OFDM_TSNOSYNCBYTE 0xF2710080 ++#define F367_OFDM_TSPARITY_ON 0xF2710040 ++#define F367_OFDM_TSSYNCOUTRS_ON 0xF2710020 ++#define F367_OFDM_TSDVBS2_MODE 0xF2710010 ++#define F367_OFDM_TSISSYI_ON 0xF2710008 ++#define F367_OFDM_TSNPD_ON 0xF2710004 ++#define F367_OFDM_TSCRC8_ON 0xF2710002 ++#define F367_OFDM_TSDSS_PACKET 0xF2710001 ++ ++/* TSCFGH */ ++#define R367_OFDM_TSCFGH 0xF272 ++#define F367_OFDM_TSFIFO_DVBCI 0xF2720080 ++#define F367_OFDM_TSFIFO_SERIAL 0xF2720040 ++#define F367_OFDM_TSFIFO_TEIUPDATE 0xF2720020 ++#define F367_OFDM_TSFIFO_DUTY50 0xF2720010 ++#define F367_OFDM_TSFIFO_HSGNLOUT 0xF2720008 ++#define F367_OFDM_TSFIFO_ERRMODE 0xF2720006 ++#define F367_OFDM_RST_HWARE 0xF2720001 ++ ++/* TSCFGM */ ++#define R367_OFDM_TSCFGM 0xF273 ++#define F367_OFDM_TSFIFO_MANSPEED 0xF27300C0 ++#define F367_OFDM_TSFIFO_PERMDATA 0xF2730020 ++#define F367_OFDM_TSFIFO_NONEWSGNL 0xF2730010 ++#define F367_OFDM_TSFIFO_BITSPEED 0xF2730008 ++#define F367_OFDM_NPD_SPECDVBS2 0xF2730004 ++#define F367_OFDM_TSFIFO_STOPCKDIS 0xF2730002 ++#define F367_OFDM_TSFIFO_INVDATA 0xF2730001 ++ ++/* TSCFGL */ ++#define R367_OFDM_TSCFGL 0xF274 ++#define F367_OFDM_TSFIFO_BCLKDEL1CK 0xF27400C0 ++#define F367_OFDM_BCHERROR_MODE 0xF2740030 ++#define F367_OFDM_TSFIFO_NSGNL2DATA 0xF2740008 ++#define F367_OFDM_TSFIFO_EMBINDVB 0xF2740004 ++#define F367_OFDM_TSFIFO_DPUNACT 0xF2740002 ++#define F367_OFDM_TSFIFO_NPDOFF 0xF2740001 ++ ++/* TSSYNC */ ++#define R367_OFDM_TSSYNC 0xF275 ++#define F367_OFDM_TSFIFO_PERMUTE 0xF2750080 ++#define F367_OFDM_TSFIFO_FISCR3B 0xF2750060 ++#define F367_OFDM_TSFIFO_SYNCMODE 0xF2750018 ++#define F367_OFDM_TSFIFO_SYNCSEL 0xF2750007 ++ ++/* TSINSDELH */ ++#define R367_OFDM_TSINSDELH 0xF276 ++#define F367_OFDM_TSDEL_SYNCBYTE 0xF2760080 ++#define F367_OFDM_TSDEL_XXHEADER 0xF2760040 ++#define F367_OFDM_TSDEL_BBHEADER 0xF2760020 ++#define F367_OFDM_TSDEL_DATAFIELD 0xF2760010 ++#define F367_OFDM_TSINSDEL_ISCR 0xF2760008 ++#define F367_OFDM_TSINSDEL_NPD 0xF2760004 ++#define F367_OFDM_TSINSDEL_RSPARITY 0xF2760002 ++#define F367_OFDM_TSINSDEL_CRC8 0xF2760001 ++ ++/* TSINSDELM */ ++#define R367_OFDM_TSINSDELM 0xF277 ++#define F367_OFDM_TSINS_BBPADDING 0xF2770080 ++#define F367_OFDM_TSINS_BCHFEC 0xF2770040 ++#define F367_OFDM_TSINS_LDPCFEC 0xF2770020 ++#define F367_OFDM_TSINS_EMODCOD 0xF2770010 ++#define F367_OFDM_TSINS_TOKEN 0xF2770008 ++#define F367_OFDM_TSINS_XXXERR 0xF2770004 ++#define F367_OFDM_TSINS_MATYPE 0xF2770002 ++#define F367_OFDM_TSINS_UPL 0xF2770001 ++ ++/* TSINSDELL */ ++#define R367_OFDM_TSINSDELL 0xF278 ++#define F367_OFDM_TSINS_DFL 0xF2780080 ++#define F367_OFDM_TSINS_SYNCD 0xF2780040 ++#define F367_OFDM_TSINS_BLOCLEN 0xF2780020 ++#define F367_OFDM_TSINS_SIGPCOUNT 0xF2780010 ++#define F367_OFDM_TSINS_FIFO 0xF2780008 ++#define F367_OFDM_TSINS_REALPACK 0xF2780004 ++#define F367_OFDM_TSINS_TSCONFIG 0xF2780002 ++#define F367_OFDM_TSINS_LATENCY 0xF2780001 ++ ++/* TSDIVN */ ++#define R367_OFDM_TSDIVN 0xF279 ++#define F367_OFDM_TSFIFO_LOWSPEED 0xF2790080 ++#define F367_OFDM_BYTE_OVERSAMPLING 0xF2790070 ++#define F367_OFDM_TSMANUAL_PACKETNBR 0xF279000F ++ ++/* TSDIVPM */ ++#define R367_OFDM_TSDIVPM 0xF27A ++#define F367_OFDM_TSMANUAL_P_HI 0xF27A00FF ++ ++/* TSDIVPL */ ++#define R367_OFDM_TSDIVPL 0xF27B ++#define F367_OFDM_TSMANUAL_P_LO 0xF27B00FF ++ ++/* TSDIVQM */ ++#define R367_OFDM_TSDIVQM 0xF27C ++#define F367_OFDM_TSMANUAL_Q_HI 0xF27C00FF ++ ++/* TSDIVQL */ ++#define R367_OFDM_TSDIVQL 0xF27D ++#define F367_OFDM_TSMANUAL_Q_LO 0xF27D00FF ++ ++/* TSDILSTKM */ ++#define R367_OFDM_TSDILSTKM 0xF27E ++#define F367_OFDM_TSFIFO_DILSTK_HI 0xF27E00FF ++ ++/* TSDILSTKL */ ++#define R367_OFDM_TSDILSTKL 0xF27F ++#define F367_OFDM_TSFIFO_DILSTK_LO 0xF27F00FF ++ ++/* TSSPEED */ ++#define R367_OFDM_TSSPEED 0xF280 ++#define F367_OFDM_TSFIFO_OUTSPEED 0xF28000FF ++ ++/* TSSTATUS */ ++#define R367_OFDM_TSSTATUS 0xF281 ++#define F367_OFDM_TSFIFO_LINEOK 0xF2810080 ++#define F367_OFDM_TSFIFO_ERROR 0xF2810040 ++#define F367_OFDM_TSFIFO_DATA7 0xF2810020 ++#define F367_OFDM_TSFIFO_NOSYNC 0xF2810010 ++#define F367_OFDM_ISCR_INITIALIZED 0xF2810008 ++#define F367_OFDM_ISCR_UPDATED 0xF2810004 ++#define F367_OFDM_SOFFIFO_UNREGUL 0xF2810002 ++#define F367_OFDM_DIL_READY 0xF2810001 ++ ++/* TSSTATUS2 */ ++#define R367_OFDM_TSSTATUS2 0xF282 ++#define F367_OFDM_TSFIFO_DEMODSEL 0xF2820080 ++#define F367_OFDM_TSFIFOSPEED_STORE 0xF2820040 ++#define F367_OFDM_DILXX_RESET 0xF2820020 ++#define F367_OFDM_TSSERIAL_IMPOSSIBLE 0xF2820010 ++#define F367_OFDM_TSFIFO_UNDERSPEED 0xF2820008 ++#define F367_OFDM_BITSPEED_EVENT 0xF2820004 ++#define F367_OFDM_UL_SCRAMBDETECT 0xF2820002 ++#define F367_OFDM_ULDTV67_FALSELOCK 0xF2820001 ++ ++/* TSBITRATEM */ ++#define R367_OFDM_TSBITRATEM 0xF283 ++#define F367_OFDM_TSFIFO_BITRATE_HI 0xF28300FF ++ ++/* TSBITRATEL */ ++#define R367_OFDM_TSBITRATEL 0xF284 ++#define F367_OFDM_TSFIFO_BITRATE_LO 0xF28400FF ++ ++/* TSPACKLENM */ ++#define R367_OFDM_TSPACKLENM 0xF285 ++#define F367_OFDM_TSFIFO_PACKCPT 0xF28500E0 ++#define F367_OFDM_DIL_RPLEN_HI 0xF285001F ++ ++/* TSPACKLENL */ ++#define R367_OFDM_TSPACKLENL 0xF286 ++#define F367_OFDM_DIL_RPLEN_LO 0xF28600FF ++ ++/* TSBLOCLENM */ ++#define R367_OFDM_TSBLOCLENM 0xF287 ++#define F367_OFDM_TSFIFO_PFLEN_HI 0xF28700FF ++ ++/* TSBLOCLENL */ ++#define R367_OFDM_TSBLOCLENL 0xF288 ++#define F367_OFDM_TSFIFO_PFLEN_LO 0xF28800FF ++ ++/* TSDLYH */ ++#define R367_OFDM_TSDLYH 0xF289 ++#define F367_OFDM_SOFFIFO_TSTIMEVALID 0xF2890080 ++#define F367_OFDM_SOFFIFO_SPEEDUP 0xF2890040 ++#define F367_OFDM_SOFFIFO_STOP 0xF2890020 ++#define F367_OFDM_SOFFIFO_REGULATED 0xF2890010 ++#define F367_OFDM_SOFFIFO_REALSBOFF_HI 0xF289000F ++ ++/* TSDLYM */ ++#define R367_OFDM_TSDLYM 0xF28A ++#define F367_OFDM_SOFFIFO_REALSBOFF_MED 0xF28A00FF ++ ++/* TSDLYL */ ++#define R367_OFDM_TSDLYL 0xF28B ++#define F367_OFDM_SOFFIFO_REALSBOFF_LO 0xF28B00FF ++ ++/* TSNPDAV */ ++#define R367_OFDM_TSNPDAV 0xF28C ++#define F367_OFDM_TSNPD_AVERAGE 0xF28C00FF ++ ++/* TSBUFSTATH */ ++#define R367_OFDM_TSBUFSTATH 0xF28D ++#define F367_OFDM_TSISCR_3BYTES 0xF28D0080 ++#define F367_OFDM_TSISCR_NEWDATA 0xF28D0040 ++#define F367_OFDM_TSISCR_BUFSTAT_HI 0xF28D003F ++ ++/* TSBUFSTATM */ ++#define R367_OFDM_TSBUFSTATM 0xF28E ++#define F367_OFDM_TSISCR_BUFSTAT_MED 0xF28E00FF ++ ++/* TSBUFSTATL */ ++#define R367_OFDM_TSBUFSTATL 0xF28F ++#define F367_OFDM_TSISCR_BUFSTAT_LO 0xF28F00FF ++ ++/* TSDEBUGM */ ++#define R367_OFDM_TSDEBUGM 0xF290 ++#define F367_OFDM_TSFIFO_ILLPACKET 0xF2900080 ++#define F367_OFDM_DIL_NOSYNC 0xF2900040 ++#define F367_OFDM_DIL_ISCR 0xF2900020 ++#define F367_OFDM_DILOUT_BSYNCB 0xF2900010 ++#define F367_OFDM_TSFIFO_EMPTYPKT 0xF2900008 ++#define F367_OFDM_TSFIFO_EMPTYRD 0xF2900004 ++#define F367_OFDM_SOFFIFO_STOPM 0xF2900002 ++#define F367_OFDM_SOFFIFO_SPEEDUPM 0xF2900001 ++ ++/* TSDEBUGL */ ++#define R367_OFDM_TSDEBUGL 0xF291 ++#define F367_OFDM_TSFIFO_PACKLENFAIL 0xF2910080 ++#define F367_OFDM_TSFIFO_SYNCBFAIL 0xF2910040 ++#define F367_OFDM_TSFIFO_VITLIBRE 0xF2910020 ++#define F367_OFDM_TSFIFO_BOOSTSPEEDM 0xF2910010 ++#define F367_OFDM_TSFIFO_UNDERSPEEDM 0xF2910008 ++#define F367_OFDM_TSFIFO_ERROR_EVNT 0xF2910004 ++#define F367_OFDM_TSFIFO_FULL 0xF2910002 ++#define F367_OFDM_TSFIFO_OVERFLOWM 0xF2910001 ++ ++/* TSDLYSETH */ ++#define R367_OFDM_TSDLYSETH 0xF292 ++#define F367_OFDM_SOFFIFO_OFFSET 0xF29200E0 ++#define F367_OFDM_SOFFIFO_SYMBOFFSET_HI 0xF292001F ++ ++/* TSDLYSETM */ ++#define R367_OFDM_TSDLYSETM 0xF293 ++#define F367_OFDM_SOFFIFO_SYMBOFFSET_MED 0xF29300FF ++ ++/* TSDLYSETL */ ++#define R367_OFDM_TSDLYSETL 0xF294 ++#define F367_OFDM_SOFFIFO_SYMBOFFSET_LO 0xF29400FF ++ ++/* TSOBSCFG */ ++#define R367_OFDM_TSOBSCFG 0xF295 ++#define F367_OFDM_TSFIFO_OBSCFG 0xF29500FF ++ ++/* TSOBSM */ ++#define R367_OFDM_TSOBSM 0xF296 ++#define F367_OFDM_TSFIFO_OBSDATA_HI 0xF29600FF ++ ++/* TSOBSL */ ++#define R367_OFDM_TSOBSL 0xF297 ++#define F367_OFDM_TSFIFO_OBSDATA_LO 0xF29700FF ++ ++/* ERRCTRL1 */ ++#define R367_OFDM_ERRCTRL1 0xF298 ++#define F367_OFDM_ERR_SRC1 0xF29800F0 ++#define F367_OFDM_ERRCTRL1_3 0xF2980008 ++#define F367_OFDM_NUM_EVT1 0xF2980007 ++ ++/* ERRCNT1H */ ++#define R367_OFDM_ERRCNT1H 0xF299 ++#define F367_OFDM_ERRCNT1_OLDVALUE 0xF2990080 ++#define F367_OFDM_ERR_CNT1 0xF299007F ++ ++/* ERRCNT1M */ ++#define R367_OFDM_ERRCNT1M 0xF29A ++#define F367_OFDM_ERR_CNT1_HI 0xF29A00FF ++ ++/* ERRCNT1L */ ++#define R367_OFDM_ERRCNT1L 0xF29B ++#define F367_OFDM_ERR_CNT1_LO 0xF29B00FF ++ ++/* ERRCTRL2 */ ++#define R367_OFDM_ERRCTRL2 0xF29C ++#define F367_OFDM_ERR_SRC2 0xF29C00F0 ++#define F367_OFDM_ERRCTRL2_3 0xF29C0008 ++#define F367_OFDM_NUM_EVT2 0xF29C0007 ++ ++/* ERRCNT2H */ ++#define R367_OFDM_ERRCNT2H 0xF29D ++#define F367_OFDM_ERRCNT2_OLDVALUE 0xF29D0080 ++#define F367_OFDM_ERR_CNT2_HI 0xF29D007F ++ ++/* ERRCNT2M */ ++#define R367_OFDM_ERRCNT2M 0xF29E ++#define F367_OFDM_ERR_CNT2_MED 0xF29E00FF ++ ++/* ERRCNT2L */ ++#define R367_OFDM_ERRCNT2L 0xF29F ++#define F367_OFDM_ERR_CNT2_LO 0xF29F00FF ++ ++/* FECSPY */ ++#define R367_OFDM_FECSPY 0xF2A0 ++#define F367_OFDM_SPY_ENABLE 0xF2A00080 ++#define F367_OFDM_NO_SYNCBYTE 0xF2A00040 ++#define F367_OFDM_SERIAL_MODE 0xF2A00020 ++#define F367_OFDM_UNUSUAL_PACKET 0xF2A00010 ++#define F367_OFDM_BERMETER_DATAMODE 0xF2A0000C ++#define F367_OFDM_BERMETER_LMODE 0xF2A00002 ++#define F367_OFDM_BERMETER_RESET 0xF2A00001 ++ ++/* FSPYCFG */ ++#define R367_OFDM_FSPYCFG 0xF2A1 ++#define F367_OFDM_FECSPY_INPUT 0xF2A100C0 ++#define F367_OFDM_RST_ON_ERROR 0xF2A10020 ++#define F367_OFDM_ONE_SHOT 0xF2A10010 ++#define F367_OFDM_I2C_MOD 0xF2A1000C ++#define F367_OFDM_SPY_HYSTERESIS 0xF2A10003 ++ ++/* FSPYDATA */ ++#define R367_OFDM_FSPYDATA 0xF2A2 ++#define F367_OFDM_SPY_STUFFING 0xF2A20080 ++#define F367_OFDM_NOERROR_PKTJITTER 0xF2A20040 ++#define F367_OFDM_SPY_CNULLPKT 0xF2A20020 ++#define F367_OFDM_SPY_OUTDATA_MODE 0xF2A2001F ++ ++/* FSPYOUT */ ++#define R367_OFDM_FSPYOUT 0xF2A3 ++#define F367_OFDM_FSPY_DIRECT 0xF2A30080 ++#define F367_OFDM_FSPYOUT_6 0xF2A30040 ++#define F367_OFDM_SPY_OUTDATA_BUS 0xF2A30038 ++#define F367_OFDM_STUFF_MODE 0xF2A30007 ++ ++/* FSTATUS */ ++#define R367_OFDM_FSTATUS 0xF2A4 ++#define F367_OFDM_SPY_ENDSIM 0xF2A40080 ++#define F367_OFDM_VALID_SIM 0xF2A40040 ++#define F367_OFDM_FOUND_SIGNAL 0xF2A40020 ++#define F367_OFDM_DSS_SYNCBYTE 0xF2A40010 ++#define F367_OFDM_RESULT_STATE 0xF2A4000F ++ ++/* FGOODPACK */ ++#define R367_OFDM_FGOODPACK 0xF2A5 ++#define F367_OFDM_FGOOD_PACKET 0xF2A500FF ++ ++/* FPACKCNT */ ++#define R367_OFDM_FPACKCNT 0xF2A6 ++#define F367_OFDM_FPACKET_COUNTER 0xF2A600FF ++ ++/* FSPYMISC */ ++#define R367_OFDM_FSPYMISC 0xF2A7 ++#define F367_OFDM_FLABEL_COUNTER 0xF2A700FF ++ ++/* FBERCPT4 */ ++#define R367_OFDM_FBERCPT4 0xF2A8 ++#define F367_OFDM_FBERMETER_CPT5 0xF2A800FF ++ ++/* FBERCPT3 */ ++#define R367_OFDM_FBERCPT3 0xF2A9 ++#define F367_OFDM_FBERMETER_CPT4 0xF2A900FF ++ ++/* FBERCPT2 */ ++#define R367_OFDM_FBERCPT2 0xF2AA ++#define F367_OFDM_FBERMETER_CPT3 0xF2AA00FF ++ ++/* FBERCPT1 */ ++#define R367_OFDM_FBERCPT1 0xF2AB ++#define F367_OFDM_FBERMETER_CPT2 0xF2AB00FF ++ ++/* FBERCPT0 */ ++#define R367_OFDM_FBERCPT0 0xF2AC ++#define F367_OFDM_FBERMETER_CPT1 0xF2AC00FF ++ ++/* FBERERR2 */ ++#define R367_OFDM_FBERERR2 0xF2AD ++#define F367_OFDM_FBERMETER_ERR_HI 0xF2AD00FF ++ ++/* FBERERR1 */ ++#define R367_OFDM_FBERERR1 0xF2AE ++#define F367_OFDM_FBERMETER_ERR_MED 0xF2AE00FF ++ ++/* FBERERR0 */ ++#define R367_OFDM_FBERERR0 0xF2AF ++#define F367_OFDM_FBERMETER_ERR_LO 0xF2AF00FF ++ ++/* FSTATESM */ ++#define R367_OFDM_FSTATESM 0xF2B0 ++#define F367_OFDM_RSTATE_F 0xF2B00080 ++#define F367_OFDM_RSTATE_E 0xF2B00040 ++#define F367_OFDM_RSTATE_D 0xF2B00020 ++#define F367_OFDM_RSTATE_C 0xF2B00010 ++#define F367_OFDM_RSTATE_B 0xF2B00008 ++#define F367_OFDM_RSTATE_A 0xF2B00004 ++#define F367_OFDM_RSTATE_9 0xF2B00002 ++#define F367_OFDM_RSTATE_8 0xF2B00001 ++ ++/* FSTATESL */ ++#define R367_OFDM_FSTATESL 0xF2B1 ++#define F367_OFDM_RSTATE_7 0xF2B10080 ++#define F367_OFDM_RSTATE_6 0xF2B10040 ++#define F367_OFDM_RSTATE_5 0xF2B10020 ++#define F367_OFDM_RSTATE_4 0xF2B10010 ++#define F367_OFDM_RSTATE_3 0xF2B10008 ++#define F367_OFDM_RSTATE_2 0xF2B10004 ++#define F367_OFDM_RSTATE_1 0xF2B10002 ++#define F367_OFDM_RSTATE_0 0xF2B10001 ++ ++/* FSPYBER */ ++#define R367_OFDM_FSPYBER 0xF2B2 ++#define F367_OFDM_FSPYBER_7 0xF2B20080 ++#define F367_OFDM_FSPYOBS_XORREAD 0xF2B20040 ++#define F367_OFDM_FSPYBER_OBSMODE 0xF2B20020 ++#define F367_OFDM_FSPYBER_SYNCBYTE 0xF2B20010 ++#define F367_OFDM_FSPYBER_UNSYNC 0xF2B20008 ++#define F367_OFDM_FSPYBER_CTIME 0xF2B20007 ++ ++/* FSPYDISTM */ ++#define R367_OFDM_FSPYDISTM 0xF2B3 ++#define F367_OFDM_PKTTIME_DISTANCE_HI 0xF2B300FF ++ ++/* FSPYDISTL */ ++#define R367_OFDM_FSPYDISTL 0xF2B4 ++#define F367_OFDM_PKTTIME_DISTANCE_LO 0xF2B400FF ++ ++/* FSPYOBS7 */ ++#define R367_OFDM_FSPYOBS7 0xF2B8 ++#define F367_OFDM_FSPYOBS_SPYFAIL 0xF2B80080 ++#define F367_OFDM_FSPYOBS_SPYFAIL1 0xF2B80040 ++#define F367_OFDM_FSPYOBS_ERROR 0xF2B80020 ++#define F367_OFDM_FSPYOBS_STROUT 0xF2B80010 ++#define F367_OFDM_FSPYOBS_RESULTSTATE1 0xF2B8000F ++ ++/* FSPYOBS6 */ ++#define R367_OFDM_FSPYOBS6 0xF2B9 ++#define F367_OFDM_FSPYOBS_RESULTSTATE0 0xF2B900F0 ++#define F367_OFDM_FSPYOBS_RESULTSTATEM1 0xF2B9000F ++ ++/* FSPYOBS5 */ ++#define R367_OFDM_FSPYOBS5 0xF2BA ++#define F367_OFDM_FSPYOBS_BYTEOFPACKET1 0xF2BA00FF ++ ++/* FSPYOBS4 */ ++#define R367_OFDM_FSPYOBS4 0xF2BB ++#define F367_OFDM_FSPYOBS_BYTEVALUE1 0xF2BB00FF ++ ++/* FSPYOBS3 */ ++#define R367_OFDM_FSPYOBS3 0xF2BC ++#define F367_OFDM_FSPYOBS_DATA1 0xF2BC00FF ++ ++/* FSPYOBS2 */ ++#define R367_OFDM_FSPYOBS2 0xF2BD ++#define F367_OFDM_FSPYOBS_DATA0 0xF2BD00FF ++ ++/* FSPYOBS1 */ ++#define R367_OFDM_FSPYOBS1 0xF2BE ++#define F367_OFDM_FSPYOBS_DATAM1 0xF2BE00FF ++ ++/* FSPYOBS0 */ ++#define R367_OFDM_FSPYOBS0 0xF2BF ++#define F367_OFDM_FSPYOBS_DATAM2 0xF2BF00FF ++ ++/* SFDEMAP */ ++#define R367_OFDM_SFDEMAP 0xF2C0 ++#define F367_OFDM_SFDEMAP_7 0xF2C00080 ++#define F367_OFDM_SFEC_K_DIVIDER_VIT 0xF2C0007F ++ ++/* SFERROR */ ++#define R367_OFDM_SFERROR 0xF2C1 ++#define F367_OFDM_SFEC_REGERR_VIT 0xF2C100FF ++ ++/* SFAVSR */ ++#define R367_OFDM_SFAVSR 0xF2C2 ++#define F367_OFDM_SFEC_SUMERRORS 0xF2C20080 ++#define F367_OFDM_SERROR_MAXMODE 0xF2C20040 ++#define F367_OFDM_SN_SFEC 0xF2C20030 ++#define F367_OFDM_KDIV_MODE_SFEC 0xF2C2000C ++#define F367_OFDM_SFAVSR_1 0xF2C20002 ++#define F367_OFDM_SFAVSR_0 0xF2C20001 ++ ++/* SFECSTATUS */ ++#define R367_OFDM_SFECSTATUS 0xF2C3 ++#define F367_OFDM_SFEC_ON 0xF2C30080 ++#define F367_OFDM_SFSTATUS_6 0xF2C30040 ++#define F367_OFDM_SFSTATUS_5 0xF2C30020 ++#define F367_OFDM_SFSTATUS_4 0xF2C30010 ++#define F367_OFDM_LOCKEDSFEC 0xF2C30008 ++#define F367_OFDM_SFEC_DELOCK 0xF2C30004 ++#define F367_OFDM_SFEC_DEMODSEL1 0xF2C30002 ++#define F367_OFDM_SFEC_OVFON 0xF2C30001 ++ ++/* SFKDIV12 */ ++#define R367_OFDM_SFKDIV12 0xF2C4 ++#define F367_OFDM_SFECKDIV12_MAN 0xF2C40080 ++#define F367_OFDM_SFEC_K_DIVIDER_12 0xF2C4007F ++ ++/* SFKDIV23 */ ++#define R367_OFDM_SFKDIV23 0xF2C5 ++#define F367_OFDM_SFECKDIV23_MAN 0xF2C50080 ++#define F367_OFDM_SFEC_K_DIVIDER_23 0xF2C5007F ++ ++/* SFKDIV34 */ ++#define R367_OFDM_SFKDIV34 0xF2C6 ++#define F367_OFDM_SFECKDIV34_MAN 0xF2C60080 ++#define F367_OFDM_SFEC_K_DIVIDER_34 0xF2C6007F ++ ++/* SFKDIV56 */ ++#define R367_OFDM_SFKDIV56 0xF2C7 ++#define F367_OFDM_SFECKDIV56_MAN 0xF2C70080 ++#define F367_OFDM_SFEC_K_DIVIDER_56 0xF2C7007F ++ ++/* SFKDIV67 */ ++#define R367_OFDM_SFKDIV67 0xF2C8 ++#define F367_OFDM_SFECKDIV67_MAN 0xF2C80080 ++#define F367_OFDM_SFEC_K_DIVIDER_67 0xF2C8007F ++ ++/* SFKDIV78 */ ++#define R367_OFDM_SFKDIV78 0xF2C9 ++#define F367_OFDM_SFECKDIV78_MAN 0xF2C90080 ++#define F367_OFDM_SFEC_K_DIVIDER_78 0xF2C9007F ++ ++/* SFDILSTKM */ ++#define R367_OFDM_SFDILSTKM 0xF2CA ++#define F367_OFDM_SFEC_PACKCPT 0xF2CA00E0 ++#define F367_OFDM_SFEC_DILSTK_HI 0xF2CA001F ++ ++/* SFDILSTKL */ ++#define R367_OFDM_SFDILSTKL 0xF2CB ++#define F367_OFDM_SFEC_DILSTK_LO 0xF2CB00FF ++ ++/* SFSTATUS */ ++#define R367_OFDM_SFSTATUS 0xF2CC ++#define F367_OFDM_SFEC_LINEOK 0xF2CC0080 ++#define F367_OFDM_SFEC_ERROR 0xF2CC0040 ++#define F367_OFDM_SFEC_DATA7 0xF2CC0020 ++#define F367_OFDM_SFEC_OVERFLOW 0xF2CC0010 ++#define F367_OFDM_SFEC_DEMODSEL2 0xF2CC0008 ++#define F367_OFDM_SFEC_NOSYNC 0xF2CC0004 ++#define F367_OFDM_SFEC_UNREGULA 0xF2CC0002 ++#define F367_OFDM_SFEC_READY 0xF2CC0001 ++ ++/* SFDLYH */ ++#define R367_OFDM_SFDLYH 0xF2CD ++#define F367_OFDM_SFEC_TSTIMEVALID 0xF2CD0080 ++#define F367_OFDM_SFEC_SPEEDUP 0xF2CD0040 ++#define F367_OFDM_SFEC_STOP 0xF2CD0020 ++#define F367_OFDM_SFEC_REGULATED 0xF2CD0010 ++#define F367_OFDM_SFEC_REALSYMBOFFSET 0xF2CD000F ++ ++/* SFDLYM */ ++#define R367_OFDM_SFDLYM 0xF2CE ++#define F367_OFDM_SFEC_REALSYMBOFFSET_HI 0xF2CE00FF ++ ++/* SFDLYL */ ++#define R367_OFDM_SFDLYL 0xF2CF ++#define F367_OFDM_SFEC_REALSYMBOFFSET_LO 0xF2CF00FF ++ ++/* SFDLYSETH */ ++#define R367_OFDM_SFDLYSETH 0xF2D0 ++#define F367_OFDM_SFEC_OFFSET 0xF2D000E0 ++#define F367_OFDM_SFECDLYSETH_4 0xF2D00010 ++#define F367_OFDM_RST_SFEC 0xF2D00008 ++#define F367_OFDM_SFECDLYSETH_2 0xF2D00004 ++#define F367_OFDM_SFEC_DISABLE 0xF2D00002 ++#define F367_OFDM_SFEC_UNREGUL 0xF2D00001 ++ ++/* SFDLYSETM */ ++#define R367_OFDM_SFDLYSETM 0xF2D1 ++#define F367_OFDM_SFECDLYSETM_7 0xF2D10080 ++#define F367_OFDM_SFEC_SYMBOFFSET_HI 0xF2D1007F ++ ++/* SFDLYSETL */ ++#define R367_OFDM_SFDLYSETL 0xF2D2 ++#define F367_OFDM_SFEC_SYMBOFFSET_LO 0xF2D200FF ++ ++/* SFOBSCFG */ ++#define R367_OFDM_SFOBSCFG 0xF2D3 ++#define F367_OFDM_SFEC_OBSCFG 0xF2D300FF ++ ++/* SFOBSM */ ++#define R367_OFDM_SFOBSM 0xF2D4 ++#define F367_OFDM_SFEC_OBSDATA_HI 0xF2D400FF ++ ++/* SFOBSL */ ++#define R367_OFDM_SFOBSL 0xF2D5 ++#define F367_OFDM_SFEC_OBSDATA_LO 0xF2D500FF ++ ++/* SFECINFO */ ++#define R367_OFDM_SFECINFO 0xF2D6 ++#define F367_OFDM_SFECINFO_7 0xF2D60080 ++#define F367_OFDM_SFEC_SYNCDLSB 0xF2D60070 ++#define F367_OFDM_SFCE_S1CPHASE 0xF2D6000F ++ ++/* SFERRCTRL */ ++#define R367_OFDM_SFERRCTRL 0xF2D8 ++#define F367_OFDM_SFEC_ERR_SOURCE 0xF2D800F0 ++#define F367_OFDM_SFERRCTRL_3 0xF2D80008 ++#define F367_OFDM_SFEC_NUM_EVENT 0xF2D80007 ++ ++/* SFERRCNTH */ ++#define R367_OFDM_SFERRCNTH 0xF2D9 ++#define F367_OFDM_SFERRC_OLDVALUE 0xF2D90080 ++#define F367_OFDM_SFEC_ERR_CNT 0xF2D9007F ++ ++/* SFERRCNTM */ ++#define R367_OFDM_SFERRCNTM 0xF2DA ++#define F367_OFDM_SFEC_ERR_CNT_HI 0xF2DA00FF ++ ++/* SFERRCNTL */ ++#define R367_OFDM_SFERRCNTL 0xF2DB ++#define F367_OFDM_SFEC_ERR_CNT_LO 0xF2DB00FF ++ ++/* SYMBRATEM */ ++#define R367_OFDM_SYMBRATEM 0xF2E0 ++#define F367_OFDM_DEFGEN_SYMBRATE_HI 0xF2E000FF ++ ++/* SYMBRATEL */ ++#define R367_OFDM_SYMBRATEL 0xF2E1 ++#define F367_OFDM_DEFGEN_SYMBRATE_LO 0xF2E100FF ++ ++/* SYMBSTATUS */ ++#define R367_OFDM_SYMBSTATUS 0xF2E2 ++#define F367_OFDM_SYMBDLINE2_OFF 0xF2E20080 ++#define F367_OFDM_SDDL_REINIT1 0xF2E20040 ++#define F367_OFDM_SDD_REINIT1 0xF2E20020 ++#define F367_OFDM_TOKENID_ERROR 0xF2E20010 ++#define F367_OFDM_SYMBRATE_OVERFLOW 0xF2E20008 ++#define F367_OFDM_SYMBRATE_UNDERFLOW 0xF2E20004 ++#define F367_OFDM_TOKENID_RSTEVENT 0xF2E20002 ++#define F367_OFDM_TOKENID_RESET1 0xF2E20001 ++ ++/* SYMBCFG */ ++#define R367_OFDM_SYMBCFG 0xF2E3 ++#define F367_OFDM_SYMBCFG_7 0xF2E30080 ++#define F367_OFDM_SYMBCFG_6 0xF2E30040 ++#define F367_OFDM_SYMBCFG_5 0xF2E30020 ++#define F367_OFDM_SYMBCFG_4 0xF2E30010 ++#define F367_OFDM_SYMRATE_FSPEED 0xF2E3000C ++#define F367_OFDM_SYMRATE_SSPEED 0xF2E30003 ++ ++/* SYMBFIFOM */ ++#define R367_OFDM_SYMBFIFOM 0xF2E4 ++#define F367_OFDM_SYMBFIFOM_7 0xF2E40080 ++#define F367_OFDM_SYMBFIFOM_6 0xF2E40040 ++#define F367_OFDM_DEFGEN_SYMFIFO_HI 0xF2E4003F ++ ++/* SYMBFIFOL */ ++#define R367_OFDM_SYMBFIFOL 0xF2E5 ++#define F367_OFDM_DEFGEN_SYMFIFO_LO 0xF2E500FF ++ ++/* SYMBOFFSM */ ++#define R367_OFDM_SYMBOFFSM 0xF2E6 ++#define F367_OFDM_TOKENID_RESET2 0xF2E60080 ++#define F367_OFDM_SDDL_REINIT2 0xF2E60040 ++#define F367_OFDM_SDD_REINIT2 0xF2E60020 ++#define F367_OFDM_SYMBOFFSM_4 0xF2E60010 ++#define F367_OFDM_SYMBOFFSM_3 0xF2E60008 ++#define F367_OFDM_DEFGEN_SYMBOFFSET_HI 0xF2E60007 ++ ++/* SYMBOFFSL */ ++#define R367_OFDM_SYMBOFFSL 0xF2E7 ++#define F367_OFDM_DEFGEN_SYMBOFFSET_LO 0xF2E700FF ++ ++/* DEBUG_LT4 */ ++#define R367_DEBUG_LT4 0xF400 ++#define F367_F_DEBUG_LT4 0xF40000FF ++ ++/* DEBUG_LT5 */ ++#define R367_DEBUG_LT5 0xF401 ++#define F367_F_DEBUG_LT5 0xF40100FF ++ ++/* DEBUG_LT6 */ ++#define R367_DEBUG_LT6 0xF402 ++#define F367_F_DEBUG_LT6 0xF40200FF ++ ++/* DEBUG_LT7 */ ++#define R367_DEBUG_LT7 0xF403 ++#define F367_F_DEBUG_LT7 0xF40300FF ++ ++/* DEBUG_LT8 */ ++#define R367_DEBUG_LT8 0xF404 ++#define F367_F_DEBUG_LT8 0xF40400FF ++ ++/* DEBUG_LT9 */ ++#define R367_DEBUG_LT9 0xF405 ++#define F367_F_DEBUG_LT9 0xF40500FF ++ ++/* CTRL_1 */ ++#define R367_QAM_CTRL_1 0xF402 ++#define F367_QAM_SOFT_RST 0xF4020080 ++#define F367_QAM_EQU_RST 0xF4020008 ++#define F367_QAM_CRL_RST 0xF4020004 ++#define F367_QAM_TRL_RST 0xF4020002 ++#define F367_QAM_AGC_RST 0xF4020001 ++ ++/* CTRL_2 */ ++#define R367_QAM_CTRL_2 0xF403 ++#define F367_QAM_DEINT_RST 0xF4030008 ++#define F367_QAM_RS_RST 0xF4030004 ++ ++/* IT_STATUS1 */ ++#define R367_QAM_IT_STATUS1 0xF408 ++#define F367_QAM_SWEEP_OUT 0xF4080080 ++#define F367_QAM_FSM_CRL 0xF4080040 ++#define F367_QAM_CRL_LOCK 0xF4080020 ++#define F367_QAM_MFSM 0xF4080010 ++#define F367_QAM_TRL_LOCK 0xF4080008 ++#define F367_QAM_TRL_AGC_LIMIT 0xF4080004 ++#define F367_QAM_ADJ_AGC_LOCK 0xF4080002 ++#define F367_QAM_AGC_QAM_LOCK 0xF4080001 ++ ++/* IT_STATUS2 */ ++#define R367_QAM_IT_STATUS2 0xF409 ++#define F367_QAM_TSMF_CNT 0xF4090080 ++#define F367_QAM_TSMF_EOF 0xF4090040 ++#define F367_QAM_TSMF_RDY 0xF4090020 ++#define F367_QAM_FEC_NOCORR 0xF4090010 ++#define F367_QAM_SYNCSTATE 0xF4090008 ++#define F367_QAM_DEINT_LOCK 0xF4090004 ++#define F367_QAM_FADDING_FRZ 0xF4090002 ++#define F367_QAM_TAPMON_ALARM 0xF4090001 ++ ++/* IT_EN1 */ ++#define R367_QAM_IT_EN1 0xF40A ++#define F367_QAM_SWEEP_OUTE 0xF40A0080 ++#define F367_QAM_FSM_CRLE 0xF40A0040 ++#define F367_QAM_CRL_LOCKE 0xF40A0020 ++#define F367_QAM_MFSME 0xF40A0010 ++#define F367_QAM_TRL_LOCKE 0xF40A0008 ++#define F367_QAM_TRL_AGC_LIMITE 0xF40A0004 ++#define F367_QAM_ADJ_AGC_LOCKE 0xF40A0002 ++#define F367_QAM_AGC_LOCKE 0xF40A0001 ++ ++/* IT_EN2 */ ++#define R367_QAM_IT_EN2 0xF40B ++#define F367_QAM_TSMF_CNTE 0xF40B0080 ++#define F367_QAM_TSMF_EOFE 0xF40B0040 ++#define F367_QAM_TSMF_RDYE 0xF40B0020 ++#define F367_QAM_FEC_NOCORRE 0xF40B0010 ++#define F367_QAM_SYNCSTATEE 0xF40B0008 ++#define F367_QAM_DEINT_LOCKE 0xF40B0004 ++#define F367_QAM_FADDING_FRZE 0xF40B0002 ++#define F367_QAM_TAPMON_ALARME 0xF40B0001 ++ ++/* CTRL_STATUS */ ++#define R367_QAM_CTRL_STATUS 0xF40C ++#define F367_QAM_QAMFEC_LOCK 0xF40C0004 ++#define F367_QAM_TSMF_LOCK 0xF40C0002 ++#define F367_QAM_TSMF_ERROR 0xF40C0001 ++ ++/* TEST_CTL */ ++#define R367_QAM_TEST_CTL 0xF40F ++#define F367_QAM_TST_BLK_SEL 0xF40F0060 ++#define F367_QAM_TST_BUS_SEL 0xF40F001F ++ ++/* AGC_CTL */ ++#define R367_QAM_AGC_CTL 0xF410 ++#define F367_QAM_AGC_LCK_TH 0xF41000F0 ++#define F367_QAM_AGC_ACCUMRSTSEL 0xF4100007 ++ ++/* AGC_IF_CFG */ ++#define R367_QAM_AGC_IF_CFG 0xF411 ++#define F367_QAM_AGC_IF_BWSEL 0xF41100F0 ++#define F367_QAM_AGC_IF_FREEZE 0xF4110002 ++ ++/* AGC_RF_CFG */ ++#define R367_QAM_AGC_RF_CFG 0xF412 ++#define F367_QAM_AGC_RF_BWSEL 0xF4120070 ++#define F367_QAM_AGC_RF_FREEZE 0xF4120002 ++ ++/* AGC_PWM_CFG */ ++#define R367_QAM_AGC_PWM_CFG 0xF413 ++#define F367_QAM_AGC_RF_PWM_TST 0xF4130080 ++#define F367_QAM_AGC_RF_PWM_INV 0xF4130040 ++#define F367_QAM_AGC_IF_PWM_TST 0xF4130008 ++#define F367_QAM_AGC_IF_PWM_INV 0xF4130004 ++#define F367_QAM_AGC_PWM_CLKDIV 0xF4130003 ++ ++/* AGC_PWR_REF_L */ ++#define R367_QAM_AGC_PWR_REF_L 0xF414 ++#define F367_QAM_AGC_PWRREF_LO 0xF41400FF ++ ++/* AGC_PWR_REF_H */ ++#define R367_QAM_AGC_PWR_REF_H 0xF415 ++#define F367_QAM_AGC_PWRREF_HI 0xF4150003 ++ ++/* AGC_RF_TH_L */ ++#define R367_QAM_AGC_RF_TH_L 0xF416 ++#define F367_QAM_AGC_RF_TH_LO 0xF41600FF ++ ++/* AGC_RF_TH_H */ ++#define R367_QAM_AGC_RF_TH_H 0xF417 ++#define F367_QAM_AGC_RF_TH_HI 0xF417000F ++ ++/* AGC_IF_LTH_L */ ++#define R367_QAM_AGC_IF_LTH_L 0xF418 ++#define F367_QAM_AGC_IF_THLO_LO 0xF41800FF ++ ++/* AGC_IF_LTH_H */ ++#define R367_QAM_AGC_IF_LTH_H 0xF419 ++#define F367_QAM_AGC_IF_THLO_HI 0xF419000F ++ ++/* AGC_IF_HTH_L */ ++#define R367_QAM_AGC_IF_HTH_L 0xF41A ++#define F367_QAM_AGC_IF_THHI_LO 0xF41A00FF ++ ++/* AGC_IF_HTH_H */ ++#define R367_QAM_AGC_IF_HTH_H 0xF41B ++#define F367_QAM_AGC_IF_THHI_HI 0xF41B000F ++ ++/* AGC_PWR_RD_L */ ++#define R367_QAM_AGC_PWR_RD_L 0xF41C ++#define F367_QAM_AGC_PWR_WORD_LO 0xF41C00FF ++ ++/* AGC_PWR_RD_M */ ++#define R367_QAM_AGC_PWR_RD_M 0xF41D ++#define F367_QAM_AGC_PWR_WORD_ME 0xF41D00FF ++ ++/* AGC_PWR_RD_H */ ++#define R367_QAM_AGC_PWR_RD_H 0xF41E ++#define F367_QAM_AGC_PWR_WORD_HI 0xF41E0003 ++ ++/* AGC_PWM_IFCMD_L */ ++#define R367_QAM_AGC_PWM_IFCMD_L 0xF420 ++#define F367_QAM_AGC_IF_PWMCMD_LO 0xF42000FF ++ ++/* AGC_PWM_IFCMD_H */ ++#define R367_QAM_AGC_PWM_IFCMD_H 0xF421 ++#define F367_QAM_AGC_IF_PWMCMD_HI 0xF421000F ++ ++/* AGC_PWM_RFCMD_L */ ++#define R367_QAM_AGC_PWM_RFCMD_L 0xF422 ++#define F367_QAM_AGC_RF_PWMCMD_LO 0xF42200FF ++ ++/* AGC_PWM_RFCMD_H */ ++#define R367_QAM_AGC_PWM_RFCMD_H 0xF423 ++#define F367_QAM_AGC_RF_PWMCMD_HI 0xF423000F ++ ++/* IQDEM_CFG */ ++#define R367_QAM_IQDEM_CFG 0xF424 ++#define F367_QAM_IQDEM_CLK_SEL 0xF4240004 ++#define F367_QAM_IQDEM_INVIQ 0xF4240002 ++#define F367_QAM_IQDEM_A2DTYPE 0xF4240001 ++ ++/* MIX_NCO_LL */ ++#define R367_QAM_MIX_NCO_LL 0xF425 ++#define F367_QAM_MIX_NCO_INC_LL 0xF42500FF ++ ++/* MIX_NCO_HL */ ++#define R367_QAM_MIX_NCO_HL 0xF426 ++#define F367_QAM_MIX_NCO_INC_HL 0xF42600FF ++ ++/* MIX_NCO_HH */ ++#define R367_QAM_MIX_NCO_HH 0xF427 ++#define F367_QAM_MIX_NCO_INVCNST 0xF4270080 ++#define F367_QAM_MIX_NCO_INC_HH 0xF427007F ++ ++/* SRC_NCO_LL */ ++#define R367_QAM_SRC_NCO_LL 0xF428 ++#define F367_QAM_SRC_NCO_INC_LL 0xF42800FF ++ ++/* SRC_NCO_LH */ ++#define R367_QAM_SRC_NCO_LH 0xF429 ++#define F367_QAM_SRC_NCO_INC_LH 0xF42900FF ++ ++/* SRC_NCO_HL */ ++#define R367_QAM_SRC_NCO_HL 0xF42A ++#define F367_QAM_SRC_NCO_INC_HL 0xF42A00FF ++ ++/* SRC_NCO_HH */ ++#define R367_QAM_SRC_NCO_HH 0xF42B ++#define F367_QAM_SRC_NCO_INC_HH 0xF42B007F ++ ++/* IQDEM_GAIN_SRC_L */ ++#define R367_QAM_IQDEM_GAIN_SRC_L 0xF42C ++#define F367_QAM_GAIN_SRC_LO 0xF42C00FF ++ ++/* IQDEM_GAIN_SRC_H */ ++#define R367_QAM_IQDEM_GAIN_SRC_H 0xF42D ++#define F367_QAM_GAIN_SRC_HI 0xF42D0003 ++ ++/* IQDEM_DCRM_CFG_LL */ ++#define R367_QAM_IQDEM_DCRM_CFG_LL 0xF430 ++#define F367_QAM_DCRM0_DCIN_L 0xF43000FF ++ ++/* IQDEM_DCRM_CFG_LH */ ++#define R367_QAM_IQDEM_DCRM_CFG_LH 0xF431 ++#define F367_QAM_DCRM1_I_DCIN_L 0xF43100FC ++#define F367_QAM_DCRM0_DCIN_H 0xF4310003 ++ ++/* IQDEM_DCRM_CFG_HL */ ++#define R367_QAM_IQDEM_DCRM_CFG_HL 0xF432 ++#define F367_QAM_DCRM1_Q_DCIN_L 0xF43200F0 ++#define F367_QAM_DCRM1_I_DCIN_H 0xF432000F ++ ++/* IQDEM_DCRM_CFG_HH */ ++#define R367_QAM_IQDEM_DCRM_CFG_HH 0xF433 ++#define F367_QAM_DCRM1_FRZ 0xF4330080 ++#define F367_QAM_DCRM0_FRZ 0xF4330040 ++#define F367_QAM_DCRM1_Q_DCIN_H 0xF433003F ++ ++/* IQDEM_ADJ_COEFF0 */ ++#define R367_QAM_IQDEM_ADJ_COEFF0 0xF434 ++#define F367_QAM_ADJIIR_COEFF10_L 0xF43400FF ++ ++/* IQDEM_ADJ_COEFF1 */ ++#define R367_QAM_IQDEM_ADJ_COEFF1 0xF435 ++#define F367_QAM_ADJIIR_COEFF11_L 0xF43500FC ++#define F367_QAM_ADJIIR_COEFF10_H 0xF4350003 ++ ++/* IQDEM_ADJ_COEFF2 */ ++#define R367_QAM_IQDEM_ADJ_COEFF2 0xF436 ++#define F367_QAM_ADJIIR_COEFF12_L 0xF43600F0 ++#define F367_QAM_ADJIIR_COEFF11_H 0xF436000F ++ ++/* IQDEM_ADJ_COEFF3 */ ++#define R367_QAM_IQDEM_ADJ_COEFF3 0xF437 ++#define F367_QAM_ADJIIR_COEFF20_L 0xF43700C0 ++#define F367_QAM_ADJIIR_COEFF12_H 0xF437003F ++ ++/* IQDEM_ADJ_COEFF4 */ ++#define R367_QAM_IQDEM_ADJ_COEFF4 0xF438 ++#define F367_QAM_ADJIIR_COEFF20_H 0xF43800FF ++ ++/* IQDEM_ADJ_COEFF5 */ ++#define R367_QAM_IQDEM_ADJ_COEFF5 0xF439 ++#define F367_QAM_ADJIIR_COEFF21_L 0xF43900FF ++ ++/* IQDEM_ADJ_COEFF6 */ ++#define R367_QAM_IQDEM_ADJ_COEFF6 0xF43A ++#define F367_QAM_ADJIIR_COEFF22_L 0xF43A00FC ++#define F367_QAM_ADJIIR_COEFF21_H 0xF43A0003 ++ ++/* IQDEM_ADJ_COEFF7 */ ++#define R367_QAM_IQDEM_ADJ_COEFF7 0xF43B ++#define F367_QAM_ADJIIR_COEFF22_H 0xF43B000F ++ ++/* IQDEM_ADJ_EN */ ++#define R367_QAM_IQDEM_ADJ_EN 0xF43C ++#define F367_QAM_ALLPASSFILT_EN 0xF43C0008 ++#define F367_QAM_ADJ_AGC_EN 0xF43C0004 ++#define F367_QAM_ADJ_COEFF_FRZ 0xF43C0002 ++#define F367_QAM_ADJ_EN 0xF43C0001 ++ ++/* IQDEM_ADJ_AGC_REF */ ++#define R367_QAM_IQDEM_ADJ_AGC_REF 0xF43D ++#define F367_QAM_ADJ_AGC_REF 0xF43D00FF ++ ++/* ALLPASSFILT1 */ ++#define R367_QAM_ALLPASSFILT1 0xF440 ++#define F367_QAM_ALLPASSFILT_COEFF1_LO 0xF44000FF ++ ++/* ALLPASSFILT2 */ ++#define R367_QAM_ALLPASSFILT2 0xF441 ++#define F367_QAM_ALLPASSFILT_COEFF1_ME 0xF44100FF ++ ++/* ALLPASSFILT3 */ ++#define R367_QAM_ALLPASSFILT3 0xF442 ++#define F367_QAM_ALLPASSFILT_COEFF2_LO 0xF44200C0 ++#define F367_QAM_ALLPASSFILT_COEFF1_HI 0xF442003F ++ ++/* ALLPASSFILT4 */ ++#define R367_QAM_ALLPASSFILT4 0xF443 ++#define F367_QAM_ALLPASSFILT_COEFF2_MEL 0xF44300FF ++ ++/* ALLPASSFILT5 */ ++#define R367_QAM_ALLPASSFILT5 0xF444 ++#define F367_QAM_ALLPASSFILT_COEFF2_MEH 0xF44400FF ++ ++/* ALLPASSFILT6 */ ++#define R367_QAM_ALLPASSFILT6 0xF445 ++#define F367_QAM_ALLPASSFILT_COEFF3_LO 0xF44500F0 ++#define F367_QAM_ALLPASSFILT_COEFF2_HI 0xF445000F ++ ++/* ALLPASSFILT7 */ ++#define R367_QAM_ALLPASSFILT7 0xF446 ++#define F367_QAM_ALLPASSFILT_COEFF3_MEL 0xF44600FF ++ ++/* ALLPASSFILT8 */ ++#define R367_QAM_ALLPASSFILT8 0xF447 ++#define F367_QAM_ALLPASSFILT_COEFF3_MEH 0xF44700FF ++ ++/* ALLPASSFILT9 */ ++#define R367_QAM_ALLPASSFILT9 0xF448 ++#define F367_QAM_ALLPASSFILT_COEFF4_LO 0xF44800FC ++#define F367_QAM_ALLPASSFILT_COEFF3_HI 0xF4480003 ++ ++/* ALLPASSFILT10 */ ++#define R367_QAM_ALLPASSFILT10 0xF449 ++#define F367_QAM_ALLPASSFILT_COEFF4_ME 0xF44900FF ++ ++/* ALLPASSFILT11 */ ++#define R367_QAM_ALLPASSFILT11 0xF44A ++#define F367_QAM_ALLPASSFILT_COEFF4_HI 0xF44A00FF ++ ++/* TRL_AGC_CFG */ ++#define R367_QAM_TRL_AGC_CFG 0xF450 ++#define F367_QAM_TRL_AGC_FREEZE 0xF4500080 ++#define F367_QAM_TRL_AGC_REF 0xF450007F ++ ++/* TRL_LPF_CFG */ ++#define R367_QAM_TRL_LPF_CFG 0xF454 ++#define F367_QAM_NYQPOINT_INV 0xF4540040 ++#define F367_QAM_TRL_SHIFT 0xF4540030 ++#define F367_QAM_NYQ_COEFF_SEL 0xF454000C ++#define F367_QAM_TRL_LPF_FREEZE 0xF4540002 ++#define F367_QAM_TRL_LPF_CRT 0xF4540001 ++ ++/* TRL_LPF_ACQ_GAIN */ ++#define R367_QAM_TRL_LPF_ACQ_GAIN 0xF455 ++#define F367_QAM_TRL_GDIR_ACQ 0xF4550070 ++#define F367_QAM_TRL_GINT_ACQ 0xF4550007 ++ ++/* TRL_LPF_TRK_GAIN */ ++#define R367_QAM_TRL_LPF_TRK_GAIN 0xF456 ++#define F367_QAM_TRL_GDIR_TRK 0xF4560070 ++#define F367_QAM_TRL_GINT_TRK 0xF4560007 ++ ++/* TRL_LPF_OUT_GAIN */ ++#define R367_QAM_TRL_LPF_OUT_GAIN 0xF457 ++#define F367_QAM_TRL_GAIN_OUT 0xF4570007 ++ ++/* TRL_LOCKDET_LTH */ ++#define R367_QAM_TRL_LOCKDET_LTH 0xF458 ++#define F367_QAM_TRL_LCK_THLO 0xF4580007 ++ ++/* TRL_LOCKDET_HTH */ ++#define R367_QAM_TRL_LOCKDET_HTH 0xF459 ++#define F367_QAM_TRL_LCK_THHI 0xF45900FF ++ ++/* TRL_LOCKDET_TRGVAL */ ++#define R367_QAM_TRL_LOCKDET_TRGVAL 0xF45A ++#define F367_QAM_TRL_LCK_TRG 0xF45A00FF ++ ++/* IQ_QAM */ ++#define R367_QAM_IQ_QAM 0xF45C ++#define F367_QAM_IQ_INPUT 0xF45C0008 ++#define F367_QAM_DETECT_MODE 0xF45C0007 ++ ++/* FSM_STATE */ ++#define R367_QAM_FSM_STATE 0xF460 ++#define F367_QAM_CRL_DFE 0xF4600080 ++#define F367_QAM_DFE_START 0xF4600040 ++#define F367_QAM_CTRLG_START 0xF4600030 ++#define F367_QAM_FSM_FORCESTATE 0xF460000F ++ ++/* FSM_CTL */ ++#define R367_QAM_FSM_CTL 0xF461 ++#define F367_QAM_FEC2_EN 0xF4610040 ++#define F367_QAM_SIT_EN 0xF4610020 ++#define F367_QAM_TRL_AHEAD 0xF4610010 ++#define F367_QAM_TRL2_EN 0xF4610008 ++#define F367_QAM_FSM_EQA1_EN 0xF4610004 ++#define F367_QAM_FSM_BKP_DIS 0xF4610002 ++#define F367_QAM_FSM_FORCE_EN 0xF4610001 ++ ++/* FSM_STS */ ++#define R367_QAM_FSM_STS 0xF462 ++#define F367_QAM_FSM_STATUS 0xF462000F ++ ++/* FSM_SNR0_HTH */ ++#define R367_QAM_FSM_SNR0_HTH 0xF463 ++#define F367_QAM_SNR0_HTH 0xF46300FF ++ ++/* FSM_SNR1_HTH */ ++#define R367_QAM_FSM_SNR1_HTH 0xF464 ++#define F367_QAM_SNR1_HTH 0xF46400FF ++ ++/* FSM_SNR2_HTH */ ++#define R367_QAM_FSM_SNR2_HTH 0xF465 ++#define F367_QAM_SNR2_HTH 0xF46500FF ++ ++/* FSM_SNR0_LTH */ ++#define R367_QAM_FSM_SNR0_LTH 0xF466 ++#define F367_QAM_SNR0_LTH 0xF46600FF ++ ++/* FSM_SNR1_LTH */ ++#define R367_QAM_FSM_SNR1_LTH 0xF467 ++#define F367_QAM_SNR1_LTH 0xF46700FF ++ ++/* FSM_EQA1_HTH */ ++#define R367_QAM_FSM_EQA1_HTH 0xF468 ++#define F367_QAM_SNR3_HTH_LO 0xF46800F0 ++#define F367_QAM_EQA1_HTH 0xF468000F ++ ++/* FSM_TEMPO */ ++#define R367_QAM_FSM_TEMPO 0xF469 ++#define F367_QAM_SIT 0xF46900C0 ++#define F367_QAM_WST 0xF4690038 ++#define F367_QAM_ELT 0xF4690006 ++#define F367_QAM_SNR3_HTH_HI 0xF4690001 ++ ++/* FSM_CONFIG */ ++#define R367_QAM_FSM_CONFIG 0xF46A ++#define F367_QAM_FEC2_DFEOFF 0xF46A0004 ++#define F367_QAM_PRIT_STATE 0xF46A0002 ++#define F367_QAM_MODMAP_STATE 0xF46A0001 ++ ++/* EQU_I_TESTTAP_L */ ++#define R367_QAM_EQU_I_TESTTAP_L 0xF474 ++#define F367_QAM_I_TEST_TAP_L 0xF47400FF ++ ++/* EQU_I_TESTTAP_M */ ++#define R367_QAM_EQU_I_TESTTAP_M 0xF475 ++#define F367_QAM_I_TEST_TAP_M 0xF47500FF ++ ++/* EQU_I_TESTTAP_H */ ++#define R367_QAM_EQU_I_TESTTAP_H 0xF476 ++#define F367_QAM_I_TEST_TAP_H 0xF476001F ++ ++/* EQU_TESTAP_CFG */ ++#define R367_QAM_EQU_TESTAP_CFG 0xF477 ++#define F367_QAM_TEST_FFE_DFE_SEL 0xF4770040 ++#define F367_QAM_TEST_TAP_SELECT 0xF477003F ++ ++/* EQU_Q_TESTTAP_L */ ++#define R367_QAM_EQU_Q_TESTTAP_L 0xF478 ++#define F367_QAM_Q_TEST_TAP_L 0xF47800FF ++ ++/* EQU_Q_TESTTAP_M */ ++#define R367_QAM_EQU_Q_TESTTAP_M 0xF479 ++#define F367_QAM_Q_TEST_TAP_M 0xF47900FF ++ ++/* EQU_Q_TESTTAP_H */ ++#define R367_QAM_EQU_Q_TESTTAP_H 0xF47A ++#define F367_QAM_Q_TEST_TAP_H 0xF47A001F ++ ++/* EQU_TAP_CTRL */ ++#define R367_QAM_EQU_TAP_CTRL 0xF47B ++#define F367_QAM_MTAP_FRZ 0xF47B0010 ++#define F367_QAM_PRE_FREEZE 0xF47B0008 ++#define F367_QAM_DFE_TAPMON_EN 0xF47B0004 ++#define F367_QAM_FFE_TAPMON_EN 0xF47B0002 ++#define F367_QAM_MTAP_ONLY 0xF47B0001 ++ ++/* EQU_CTR_CRL_CONTROL_L */ ++#define R367_QAM_EQU_CTR_CRL_CONTROL_L 0xF47C ++#define F367_QAM_EQU_CTR_CRL_CONTROL_LO 0xF47C00FF ++ ++/* EQU_CTR_CRL_CONTROL_H */ ++#define R367_QAM_EQU_CTR_CRL_CONTROL_H 0xF47D ++#define F367_QAM_EQU_CTR_CRL_CONTROL_HI 0xF47D00FF ++ ++/* EQU_CTR_HIPOW_L */ ++#define R367_QAM_EQU_CTR_HIPOW_L 0xF47E ++#define F367_QAM_CTR_HIPOW_L 0xF47E00FF ++ ++/* EQU_CTR_HIPOW_H */ ++#define R367_QAM_EQU_CTR_HIPOW_H 0xF47F ++#define F367_QAM_CTR_HIPOW_H 0xF47F00FF ++ ++/* EQU_I_EQU_LO */ ++#define R367_QAM_EQU_I_EQU_LO 0xF480 ++#define F367_QAM_EQU_I_EQU_L 0xF48000FF ++ ++/* EQU_I_EQU_HI */ ++#define R367_QAM_EQU_I_EQU_HI 0xF481 ++#define F367_QAM_EQU_I_EQU_H 0xF4810003 ++ ++/* EQU_Q_EQU_LO */ ++#define R367_QAM_EQU_Q_EQU_LO 0xF482 ++#define F367_QAM_EQU_Q_EQU_L 0xF48200FF ++ ++/* EQU_Q_EQU_HI */ ++#define R367_QAM_EQU_Q_EQU_HI 0xF483 ++#define F367_QAM_EQU_Q_EQU_H 0xF4830003 ++ ++/* EQU_MAPPER */ ++#define R367_QAM_EQU_MAPPER 0xF484 ++#define F367_QAM_QUAD_AUTO 0xF4840080 ++#define F367_QAM_QUAD_INV 0xF4840040 ++#define F367_QAM_QAM_MODE 0xF4840007 ++ ++/* EQU_SWEEP_RATE */ ++#define R367_QAM_EQU_SWEEP_RATE 0xF485 ++#define F367_QAM_SNR_PER 0xF48500C0 ++#define F367_QAM_SWEEP_RATE 0xF485003F ++ ++/* EQU_SNR_LO */ ++#define R367_QAM_EQU_SNR_LO 0xF486 ++#define F367_QAM_SNR_LO 0xF48600FF ++ ++/* EQU_SNR_HI */ ++#define R367_QAM_EQU_SNR_HI 0xF487 ++#define F367_QAM_SNR_HI 0xF48700FF ++ ++/* EQU_GAMMA_LO */ ++#define R367_QAM_EQU_GAMMA_LO 0xF488 ++#define F367_QAM_GAMMA_LO 0xF48800FF ++ ++/* EQU_GAMMA_HI */ ++#define R367_QAM_EQU_GAMMA_HI 0xF489 ++#define F367_QAM_GAMMA_ME 0xF48900FF ++ ++/* EQU_ERR_GAIN */ ++#define R367_QAM_EQU_ERR_GAIN 0xF48A ++#define F367_QAM_EQA1MU 0xF48A0070 ++#define F367_QAM_CRL2MU 0xF48A000E ++#define F367_QAM_GAMMA_HI 0xF48A0001 ++ ++/* EQU_RADIUS */ ++#define R367_QAM_EQU_RADIUS 0xF48B ++#define F367_QAM_RADIUS 0xF48B00FF ++ ++/* EQU_FFE_MAINTAP */ ++#define R367_QAM_EQU_FFE_MAINTAP 0xF48C ++#define F367_QAM_FFE_MAINTAP_INIT 0xF48C00FF ++ ++/* EQU_FFE_LEAKAGE */ ++#define R367_QAM_EQU_FFE_LEAKAGE 0xF48E ++#define F367_QAM_LEAK_PER 0xF48E00F0 ++#define F367_QAM_EQU_OUTSEL 0xF48E0002 ++#define F367_QAM_PNT2DFE 0xF48E0001 ++ ++/* EQU_FFE_MAINTAP_POS */ ++#define R367_QAM_EQU_FFE_MAINTAP_POS 0xF48F ++#define F367_QAM_FFE_LEAK_EN 0xF48F0080 ++#define F367_QAM_DFE_LEAK_EN 0xF48F0040 ++#define F367_QAM_FFE_MAINTAP_POS 0xF48F003F ++ ++/* EQU_GAIN_WIDE */ ++#define R367_QAM_EQU_GAIN_WIDE 0xF490 ++#define F367_QAM_DFE_GAIN_WIDE 0xF49000F0 ++#define F367_QAM_FFE_GAIN_WIDE 0xF490000F ++ ++/* EQU_GAIN_NARROW */ ++#define R367_QAM_EQU_GAIN_NARROW 0xF491 ++#define F367_QAM_DFE_GAIN_NARROW 0xF49100F0 ++#define F367_QAM_FFE_GAIN_NARROW 0xF491000F ++ ++/* EQU_CTR_LPF_GAIN */ ++#define R367_QAM_EQU_CTR_LPF_GAIN 0xF492 ++#define F367_QAM_CTR_GTO 0xF4920080 ++#define F367_QAM_CTR_GDIR 0xF4920070 ++#define F367_QAM_SWEEP_EN 0xF4920008 ++#define F367_QAM_CTR_GINT 0xF4920007 ++ ++/* EQU_CRL_LPF_GAIN */ ++#define R367_QAM_EQU_CRL_LPF_GAIN 0xF493 ++#define F367_QAM_CRL_GTO 0xF4930080 ++#define F367_QAM_CRL_GDIR 0xF4930070 ++#define F367_QAM_SWEEP_DIR 0xF4930008 ++#define F367_QAM_CRL_GINT 0xF4930007 ++ ++/* EQU_GLOBAL_GAIN */ ++#define R367_QAM_EQU_GLOBAL_GAIN 0xF494 ++#define F367_QAM_CRL_GAIN 0xF49400F8 ++#define F367_QAM_CTR_INC_GAIN 0xF4940004 ++#define F367_QAM_CTR_FRAC 0xF4940003 ++ ++/* EQU_CRL_LD_SEN */ ++#define R367_QAM_EQU_CRL_LD_SEN 0xF495 ++#define F367_QAM_CTR_BADPOINT_EN 0xF4950080 ++#define F367_QAM_CTR_GAIN 0xF4950070 ++#define F367_QAM_LIMANEN 0xF4950008 ++#define F367_QAM_CRL_LD_SEN 0xF4950007 ++ ++/* EQU_CRL_LD_VAL */ ++#define R367_QAM_EQU_CRL_LD_VAL 0xF496 ++#define F367_QAM_CRL_BISTH_LIMIT 0xF4960080 ++#define F367_QAM_CARE_EN 0xF4960040 ++#define F367_QAM_CRL_LD_PER 0xF4960030 ++#define F367_QAM_CRL_LD_WST 0xF496000C ++#define F367_QAM_CRL_LD_TFS 0xF4960003 ++ ++/* EQU_CRL_TFR */ ++#define R367_QAM_EQU_CRL_TFR 0xF497 ++#define F367_QAM_CRL_LD_TFR 0xF49700FF ++ ++/* EQU_CRL_BISTH_LO */ ++#define R367_QAM_EQU_CRL_BISTH_LO 0xF498 ++#define F367_QAM_CRL_BISTH_LO 0xF49800FF ++ ++/* EQU_CRL_BISTH_HI */ ++#define R367_QAM_EQU_CRL_BISTH_HI 0xF499 ++#define F367_QAM_CRL_BISTH_HI 0xF49900FF ++ ++/* EQU_SWEEP_RANGE_LO */ ++#define R367_QAM_EQU_SWEEP_RANGE_LO 0xF49A ++#define F367_QAM_SWEEP_RANGE_LO 0xF49A00FF ++ ++/* EQU_SWEEP_RANGE_HI */ ++#define R367_QAM_EQU_SWEEP_RANGE_HI 0xF49B ++#define F367_QAM_SWEEP_RANGE_HI 0xF49B00FF ++ ++/* EQU_CRL_LIMITER */ ++#define R367_QAM_EQU_CRL_LIMITER 0xF49C ++#define F367_QAM_BISECTOR_EN 0xF49C0080 ++#define F367_QAM_PHEST128_EN 0xF49C0040 ++#define F367_QAM_CRL_LIM 0xF49C003F ++ ++/* EQU_MODULUS_MAP */ ++#define R367_QAM_EQU_MODULUS_MAP 0xF49D ++#define F367_QAM_PNT_DEPTH 0xF49D00E0 ++#define F367_QAM_MODULUS_CMP 0xF49D001F ++ ++/* EQU_PNT_GAIN */ ++#define R367_QAM_EQU_PNT_GAIN 0xF49E ++#define F367_QAM_PNT_EN 0xF49E0080 ++#define F367_QAM_MODULUSMAP_EN 0xF49E0040 ++#define F367_QAM_PNT_GAIN 0xF49E003F ++ ++/* FEC_AC_CTR_0 */ ++#define R367_QAM_FEC_AC_CTR_0 0xF4A8 ++#define F367_QAM_BE_BYPASS 0xF4A80020 ++#define F367_QAM_REFRESH47 0xF4A80010 ++#define F367_QAM_CT_NBST 0xF4A80008 ++#define F367_QAM_TEI_ENA 0xF4A80004 ++#define F367_QAM_DS_ENA 0xF4A80002 ++#define F367_QAM_TSMF_EN 0xF4A80001 ++ ++/* FEC_AC_CTR_1 */ ++#define R367_QAM_FEC_AC_CTR_1 0xF4A9 ++#define F367_QAM_DEINT_DEPTH 0xF4A900FF ++ ++/* FEC_AC_CTR_2 */ ++#define R367_QAM_FEC_AC_CTR_2 0xF4AA ++#define F367_QAM_DEINT_M 0xF4AA00F8 ++#define F367_QAM_DIS_UNLOCK 0xF4AA0004 ++#define F367_QAM_DESCR_MODE 0xF4AA0003 ++ ++/* FEC_AC_CTR_3 */ ++#define R367_QAM_FEC_AC_CTR_3 0xF4AB ++#define F367_QAM_DI_UNLOCK 0xF4AB0080 ++#define F367_QAM_DI_FREEZE 0xF4AB0040 ++#define F367_QAM_MISMATCH 0xF4AB0030 ++#define F367_QAM_ACQ_MODE 0xF4AB000C ++#define F367_QAM_TRK_MODE 0xF4AB0003 ++ ++/* FEC_STATUS */ ++#define R367_QAM_FEC_STATUS 0xF4AC ++#define F367_QAM_DEINT_SMCNTR 0xF4AC00E0 ++#define F367_QAM_DEINT_SYNCSTATE 0xF4AC0018 ++#define F367_QAM_DEINT_SYNLOST 0xF4AC0004 ++#define F367_QAM_DESCR_SYNCSTATE 0xF4AC0002 ++ ++/* RS_COUNTER_0 */ ++#define R367_QAM_RS_COUNTER_0 0xF4AE ++#define F367_QAM_BK_CT_L 0xF4AE00FF ++ ++/* RS_COUNTER_1 */ ++#define R367_QAM_RS_COUNTER_1 0xF4AF ++#define F367_QAM_BK_CT_H 0xF4AF00FF ++ ++/* RS_COUNTER_2 */ ++#define R367_QAM_RS_COUNTER_2 0xF4B0 ++#define F367_QAM_CORR_CT_L 0xF4B000FF ++ ++/* RS_COUNTER_3 */ ++#define R367_QAM_RS_COUNTER_3 0xF4B1 ++#define F367_QAM_CORR_CT_H 0xF4B100FF ++ ++/* RS_COUNTER_4 */ ++#define R367_QAM_RS_COUNTER_4 0xF4B2 ++#define F367_QAM_UNCORR_CT_L 0xF4B200FF ++ ++/* RS_COUNTER_5 */ ++#define R367_QAM_RS_COUNTER_5 0xF4B3 ++#define F367_QAM_UNCORR_CT_H 0xF4B300FF ++ ++/* BERT_0 */ ++#define R367_QAM_BERT_0 0xF4B4 ++#define F367_QAM_RS_NOCORR 0xF4B40004 ++#define F367_QAM_CT_HOLD 0xF4B40002 ++#define F367_QAM_CT_CLEAR 0xF4B40001 ++ ++/* BERT_1 */ ++#define R367_QAM_BERT_1 0xF4B5 ++#define F367_QAM_BERT_ON 0xF4B50020 ++#define F367_QAM_BERT_ERR_SRC 0xF4B50010 ++#define F367_QAM_BERT_ERR_MODE 0xF4B50008 ++#define F367_QAM_BERT_NBYTE 0xF4B50007 ++ ++/* BERT_2 */ ++#define R367_QAM_BERT_2 0xF4B6 ++#define F367_QAM_BERT_ERRCOUNT_L 0xF4B600FF ++ ++/* BERT_3 */ ++#define R367_QAM_BERT_3 0xF4B7 ++#define F367_QAM_BERT_ERRCOUNT_H 0xF4B700FF ++ ++/* OUTFORMAT_0 */ ++#define R367_QAM_OUTFORMAT_0 0xF4B8 ++#define F367_QAM_CLK_POLARITY 0xF4B80080 ++#define F367_QAM_FEC_TYPE 0xF4B80040 ++#define F367_QAM_SYNC_STRIP 0xF4B80008 ++#define F367_QAM_TS_SWAP 0xF4B80004 ++#define F367_QAM_OUTFORMAT 0xF4B80003 ++ ++/* OUTFORMAT_1 */ ++#define R367_QAM_OUTFORMAT_1 0xF4B9 ++#define F367_QAM_CI_DIVRANGE 0xF4B900FF ++ ++/* SMOOTHER_2 */ ++#define R367_QAM_SMOOTHER_2 0xF4BE ++#define F367_QAM_FIFO_BYPASS 0xF4BE0020 ++ ++/* TSMF_CTRL_0 */ ++#define R367_QAM_TSMF_CTRL_0 0xF4C0 ++#define F367_QAM_TS_NUMBER 0xF4C0001E ++#define F367_QAM_SEL_MODE 0xF4C00001 ++ ++/* TSMF_CTRL_1 */ ++#define R367_QAM_TSMF_CTRL_1 0xF4C1 ++#define F367_QAM_CHECK_ERROR_BIT 0xF4C10080 ++#define F367_QAM_CHCK_F_SYNC 0xF4C10040 ++#define F367_QAM_H_MODE 0xF4C10008 ++#define F367_QAM_D_V_MODE 0xF4C10004 ++#define F367_QAM_MODE 0xF4C10003 ++ ++/* TSMF_CTRL_3 */ ++#define R367_QAM_TSMF_CTRL_3 0xF4C3 ++#define F367_QAM_SYNC_IN_COUNT 0xF4C300F0 ++#define F367_QAM_SYNC_OUT_COUNT 0xF4C3000F ++ ++/* TS_ON_ID_0 */ ++#define R367_QAM_TS_ON_ID_0 0xF4C4 ++#define F367_QAM_TS_ID_L 0xF4C400FF ++ ++/* TS_ON_ID_1 */ ++#define R367_QAM_TS_ON_ID_1 0xF4C5 ++#define F367_QAM_TS_ID_H 0xF4C500FF ++ ++/* TS_ON_ID_2 */ ++#define R367_QAM_TS_ON_ID_2 0xF4C6 ++#define F367_QAM_ON_ID_L 0xF4C600FF ++ ++/* TS_ON_ID_3 */ ++#define R367_QAM_TS_ON_ID_3 0xF4C7 ++#define F367_QAM_ON_ID_H 0xF4C700FF ++ ++/* RE_STATUS_0 */ ++#define R367_QAM_RE_STATUS_0 0xF4C8 ++#define F367_QAM_RECEIVE_STATUS_L 0xF4C800FF ++ ++/* RE_STATUS_1 */ ++#define R367_QAM_RE_STATUS_1 0xF4C9 ++#define F367_QAM_RECEIVE_STATUS_LH 0xF4C900FF ++ ++/* RE_STATUS_2 */ ++#define R367_QAM_RE_STATUS_2 0xF4CA ++#define F367_QAM_RECEIVE_STATUS_HL 0xF4CA00FF ++ ++/* RE_STATUS_3 */ ++#define R367_QAM_RE_STATUS_3 0xF4CB ++#define F367_QAM_RECEIVE_STATUS_HH 0xF4CB003F ++ ++/* TS_STATUS_0 */ ++#define R367_QAM_TS_STATUS_0 0xF4CC ++#define F367_QAM_TS_STATUS_L 0xF4CC00FF ++ ++/* TS_STATUS_1 */ ++#define R367_QAM_TS_STATUS_1 0xF4CD ++#define F367_QAM_TS_STATUS_H 0xF4CD007F ++ ++/* TS_STATUS_2 */ ++#define R367_QAM_TS_STATUS_2 0xF4CE ++#define F367_QAM_ERROR 0xF4CE0080 ++#define F367_QAM_EMERGENCY 0xF4CE0040 ++#define F367_QAM_CRE_TS 0xF4CE0030 ++#define F367_QAM_VER 0xF4CE000E ++#define F367_QAM_M_LOCK 0xF4CE0001 ++ ++/* TS_STATUS_3 */ ++#define R367_QAM_TS_STATUS_3 0xF4CF ++#define F367_QAM_UPDATE_READY 0xF4CF0080 ++#define F367_QAM_END_FRAME_HEADER 0xF4CF0040 ++#define F367_QAM_CONTCNT 0xF4CF0020 ++#define F367_QAM_TS_IDENTIFIER_SEL 0xF4CF000F ++ ++/* T_O_ID_0 */ ++#define R367_QAM_T_O_ID_0 0xF4D0 ++#define F367_QAM_ON_ID_I_L 0xF4D000FF ++ ++/* T_O_ID_1 */ ++#define R367_QAM_T_O_ID_1 0xF4D1 ++#define F367_QAM_ON_ID_I_H 0xF4D100FF ++ ++/* T_O_ID_2 */ ++#define R367_QAM_T_O_ID_2 0xF4D2 ++#define F367_QAM_TS_ID_I_L 0xF4D200FF ++ ++/* T_O_ID_3 */ ++#define R367_QAM_T_O_ID_3 0xF4D3 ++#define F367_QAM_TS_ID_I_H 0xF4D300FF ++ diff --git a/drivers/media/dvb-frontends/stv0910.c b/drivers/media/dvb-frontends/stv0910.c new file mode 100644 index 0000000..89d7d1f @@ -16923,4004 +16923,4004 @@ index 0000000..16e922f --- /dev/null +++ b/drivers/media/dvb-frontends/stv0910_regs.h @@ -0,0 +1,3998 @@ -+// @DVB-S/DVB-S2 STMicroelectronics STV0900 register defintions -+// Author Manfred Völkel, August 2013 -+// (c) 2013 Digital Devices GmbH Germany. All rights reserved -+ -+// $Id: DD_STV0910Register.h 504 2013-09-02 23:02:14Z manfred $ -+ -+/* ======================================================================= -+-- Registers Declaration (Internal ST, All Applications ) -+-- ------------------------- -+-- Each register (RSTV0910__XXXXX) is defined by its address (2 bytes). -+-- -+-- Each field (FSTV0910__XXXXX)is defined as follow: -+-- [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] -+ ======================================================================= */ -+ -+/*MID*/ -+#define RSTV0910_MID 0xf100 -+#define FSTV0910_MCHIP_IDENT 0xf10000f0 -+#define FSTV0910_MRELEASE 0xf100000f -+ -+/*DID*/ -+#define RSTV0910_DID 0xf101 -+#define FSTV0910_DEVICE_ID 0xf10100ff -+ -+/*DACR1*/ -+#define RSTV0910_DACR1 0xf113 -+#define FSTV0910_DAC_MODE 0xf11300e0 -+#define FSTV0910_DAC_VALUE1 0xf113000f -+ -+/*DACR2*/ -+#define RSTV0910_DACR2 0xf114 -+#define FSTV0910_DAC_VALUE0 0xf11400ff -+ -+/*PADCFG*/ -+#define RSTV0910_PADCFG 0xf11a -+#define FSTV0910_AGCRF2_OPD 0xf11a0008 -+#define FSTV0910_AGCRF2_XOR 0xf11a0004 -+#define FSTV0910_AGCRF1_OPD 0xf11a0002 -+#define FSTV0910_AGCRF1_XOR 0xf11a0001 -+ -+/*OUTCFG2*/ -+#define RSTV0910_OUTCFG2 0xf11b -+#define FSTV0910_TS2_ERROR_XOR 0xf11b0080 -+#define FSTV0910_TS2_DPN_XOR 0xf11b0040 -+#define FSTV0910_TS2_STROUT_XOR 0xf11b0020 -+#define FSTV0910_TS2_CLOCKOUT_XOR 0xf11b0010 -+#define FSTV0910_TS1_ERROR_XOR 0xf11b0008 -+#define FSTV0910_TS1_DPN_XOR 0xf11b0004 -+#define FSTV0910_TS1_STROUT_XOR 0xf11b0002 -+#define FSTV0910_TS1_CLOCKOUT_XOR 0xf11b0001 -+ -+/*OUTCFG*/ -+#define RSTV0910_OUTCFG 0xf11c -+#define FSTV0910_INV_DATA6 0xf11c0080 -+#define FSTV0910_TS2_OUTSER_HZ 0xf11c0020 -+#define FSTV0910_TS1_OUTSER_HZ 0xf11c0010 -+#define FSTV0910_TS2_OUTPAR_HZ 0xf11c0008 -+#define FSTV0910_TS1_OUTPAR_HZ 0xf11c0004 -+#define FSTV0910_TS_SERDATA0 0xf11c0002 -+ -+/*IRQSTATUS3*/ -+#define RSTV0910_IRQSTATUS3 0xf120 -+#define FSTV0910_SPLL_LOCK 0xf1200020 -+#define FSTV0910_SSTREAM_LCK_1 0xf1200010 -+#define FSTV0910_SSTREAM_LCK_2 0xf1200008 -+#define FSTV0910_SDVBS1_PRF_2 0xf1200002 -+#define FSTV0910_SDVBS1_PRF_1 0xf1200001 -+ -+/*IRQSTATUS2*/ -+#define RSTV0910_IRQSTATUS2 0xf121 -+#define FSTV0910_SSPY_ENDSIM_1 0xf1210080 -+#define FSTV0910_SSPY_ENDSIM_2 0xf1210040 -+#define FSTV0910_SPKTDEL_ERROR_2 0xf1210010 -+#define FSTV0910_SPKTDEL_LOCKB_2 0xf1210008 -+#define FSTV0910_SPKTDEL_LOCK_2 0xf1210004 -+#define FSTV0910_SPKTDEL_ERROR_1 0xf1210002 -+#define FSTV0910_SPKTDEL_LOCKB_1 0xf1210001 -+ -+/*IRQSTATUS1*/ -+#define RSTV0910_IRQSTATUS1 0xf122 -+#define FSTV0910_SPKTDEL_LOCK_1 0xf1220080 -+#define FSTV0910_SFEC_LOCKB_2 0xf1220040 -+#define FSTV0910_SFEC_LOCK_2 0xf1220020 -+#define FSTV0910_SFEC_LOCKB_1 0xf1220010 -+#define FSTV0910_SFEC_LOCK_1 0xf1220008 -+#define FSTV0910_SDEMOD_LOCKB_2 0xf1220004 -+#define FSTV0910_SDEMOD_LOCK_2 0xf1220002 -+#define FSTV0910_SDEMOD_IRQ_2 0xf1220001 -+ -+/*IRQSTATUS0*/ -+#define RSTV0910_IRQSTATUS0 0xf123 -+#define FSTV0910_SDEMOD_LOCKB_1 0xf1230080 -+#define FSTV0910_SDEMOD_LOCK_1 0xf1230040 -+#define FSTV0910_SDEMOD_IRQ_1 0xf1230020 -+#define FSTV0910_SBCH_ERRFLAG 0xf1230010 -+#define FSTV0910_SECW2_IRQ 0xf1230008 -+#define FSTV0910_SDISEQC2_IRQ 0xf1230004 -+#define FSTV0910_SECW1_IRQ 0xf1230002 -+#define FSTV0910_SDISEQC1_IRQ 0xf1230001 -+ -+/*IRQMASK3*/ -+#define RSTV0910_IRQMASK3 0xf124 -+#define FSTV0910_MPLL_LOCK 0xf1240020 -+#define FSTV0910_MSTREAM_LCK_1 0xf1240010 -+#define FSTV0910_MSTREAM_LCK_2 0xf1240008 -+#define FSTV0910_MDVBS1_PRF_2 0xf1240002 -+#define FSTV0910_MDVBS1_PRF_1 0xf1240001 -+ -+/*IRQMASK2*/ -+#define RSTV0910_IRQMASK2 0xf125 -+#define FSTV0910_MSPY_ENDSIM_1 0xf1250080 -+#define FSTV0910_MSPY_ENDSIM_2 0xf1250040 -+#define FSTV0910_MPKTDEL_ERROR_2 0xf1250010 -+#define FSTV0910_MPKTDEL_LOCKB_2 0xf1250008 -+#define FSTV0910_MPKTDEL_LOCK_2 0xf1250004 -+#define FSTV0910_MPKTDEL_ERROR_1 0xf1250002 -+#define FSTV0910_MPKTDEL_LOCKB_1 0xf1250001 -+ -+/*IRQMASK1*/ -+#define RSTV0910_IRQMASK1 0xf126 -+#define FSTV0910_MPKTDEL_LOCK_1 0xf1260080 -+#define FSTV0910_MFEC_LOCKB_2 0xf1260040 -+#define FSTV0910_MFEC_LOCK_2 0xf1260020 -+#define FSTV0910_MFEC_LOCKB_1 0xf1260010 -+#define FSTV0910_MFEC_LOCK_1 0xf1260008 -+#define FSTV0910_MDEMOD_LOCKB_2 0xf1260004 -+#define FSTV0910_MDEMOD_LOCK_2 0xf1260002 -+#define FSTV0910_MDEMOD_IRQ_2 0xf1260001 -+ -+/*IRQMASK0*/ -+#define RSTV0910_IRQMASK0 0xf127 -+#define FSTV0910_MDEMOD_LOCKB_1 0xf1270080 -+#define FSTV0910_MDEMOD_LOCK_1 0xf1270040 -+#define FSTV0910_MDEMOD_IRQ_1 0xf1270020 -+#define FSTV0910_MBCH_ERRFLAG 0xf1270010 -+#define FSTV0910_MECW2_IRQ 0xf1270008 -+#define FSTV0910_MDISEQC2_IRQ 0xf1270004 -+#define FSTV0910_MECW1_IRQ 0xf1270002 -+#define FSTV0910_MDISEQC1_IRQ 0xf1270001 -+ -+/*I2CCFG*/ -+#define RSTV0910_I2CCFG 0xf129 -+#define FSTV0910_I2C2_FASTMODE 0xf1290080 -+#define FSTV0910_STATUS_WR2 0xf1290040 -+#define FSTV0910_I2C2ADDR_INC 0xf1290030 -+#define FSTV0910_I2C_FASTMODE 0xf1290008 -+#define FSTV0910_STATUS_WR 0xf1290004 -+#define FSTV0910_I2CADDR_INC 0xf1290003 -+ -+/*P1_I2CRPT*/ -+#define RSTV0910_P1_I2CRPT 0xf12a -+#define FSTV0910_P1_I2CT_ON 0xf12a0080 -+#define FSTV0910_P1_ENARPT_LEVEL 0xf12a0070 -+#define FSTV0910_P1_SCLT_DELAY 0xf12a0008 -+#define FSTV0910_P1_STOP_ENABLE 0xf12a0004 -+#define FSTV0910_P1_STOP_SDAT2SDA 0xf12a0002 -+ -+/*P2_I2CRPT*/ -+#define RSTV0910_P2_I2CRPT 0xf12b -+#define FSTV0910_P2_I2CT_ON 0xf12b0080 -+#define FSTV0910_P2_ENARPT_LEVEL 0xf12b0070 -+#define FSTV0910_P2_SCLT_DELAY 0xf12b0008 -+#define FSTV0910_P2_STOP_ENABLE 0xf12b0004 -+#define FSTV0910_P2_STOP_SDAT2SDA 0xf12b0002 -+ -+/*GPIO0CFG*/ -+#define RSTV0910_GPIO0CFG 0xf140 -+#define FSTV0910_GPIO0_OPD 0xf1400080 -+#define FSTV0910_GPIO0_CONFIG 0xf140007e -+#define FSTV0910_GPIO0_XOR 0xf1400001 -+ -+/*GPIO1CFG*/ -+#define RSTV0910_GPIO1CFG 0xf141 -+#define FSTV0910_GPIO1_OPD 0xf1410080 -+#define FSTV0910_GPIO1_CONFIG 0xf141007e -+#define FSTV0910_GPIO1_XOR 0xf1410001 -+ -+/*GPIO2CFG*/ -+#define RSTV0910_GPIO2CFG 0xf142 -+#define FSTV0910_GPIO2_OPD 0xf1420080 -+#define FSTV0910_GPIO2_CONFIG 0xf142007e -+#define FSTV0910_GPIO2_XOR 0xf1420001 -+ -+/*GPIO3CFG*/ -+#define RSTV0910_GPIO3CFG 0xf143 -+#define FSTV0910_GPIO3_OPD 0xf1430080 -+#define FSTV0910_GPIO3_CONFIG 0xf143007e -+#define FSTV0910_GPIO3_XOR 0xf1430001 -+ -+/*GPIO4CFG*/ -+#define RSTV0910_GPIO4CFG 0xf144 -+#define FSTV0910_GPIO4_OPD 0xf1440080 -+#define FSTV0910_GPIO4_CONFIG 0xf144007e -+#define FSTV0910_GPIO4_XOR 0xf1440001 -+ -+/*GPIO5CFG*/ -+#define RSTV0910_GPIO5CFG 0xf145 -+#define FSTV0910_GPIO5_OPD 0xf1450080 -+#define FSTV0910_GPIO5_CONFIG 0xf145007e -+#define FSTV0910_GPIO5_XOR 0xf1450001 -+ -+/*GPIO6CFG*/ -+#define RSTV0910_GPIO6CFG 0xf146 -+#define FSTV0910_GPIO6_OPD 0xf1460080 -+#define FSTV0910_GPIO6_CONFIG 0xf146007e -+#define FSTV0910_GPIO6_XOR 0xf1460001 -+ -+/*GPIO7CFG*/ -+#define RSTV0910_GPIO7CFG 0xf147 -+#define FSTV0910_GPIO7_OPD 0xf1470080 -+#define FSTV0910_GPIO7_CONFIG 0xf147007e -+#define FSTV0910_GPIO7_XOR 0xf1470001 -+ -+/*GPIO8CFG*/ -+#define RSTV0910_GPIO8CFG 0xf148 -+#define FSTV0910_GPIO8_OPD 0xf1480080 -+#define FSTV0910_GPIO8_CONFIG 0xf148007e -+#define FSTV0910_GPIO8_XOR 0xf1480001 -+ -+/*GPIO9CFG*/ -+#define RSTV0910_GPIO9CFG 0xf149 -+#define FSTV0910_GPIO9_OPD 0xf1490080 -+#define FSTV0910_GPIO9_CONFIG 0xf149007e -+#define FSTV0910_GPIO9_XOR 0xf1490001 -+ -+/*GPIO10CFG*/ -+#define RSTV0910_GPIO10CFG 0xf14a -+#define FSTV0910_GPIO10_OPD 0xf14a0080 -+#define FSTV0910_GPIO10_CONFIG 0xf14a007e -+#define FSTV0910_GPIO10_XOR 0xf14a0001 -+ -+/*GPIO11CFG*/ -+#define RSTV0910_GPIO11CFG 0xf14b -+#define FSTV0910_GPIO11_OPD 0xf14b0080 -+#define FSTV0910_GPIO11_CONFIG 0xf14b007e -+#define FSTV0910_GPIO11_XOR 0xf14b0001 -+ -+/*GPIO12CFG*/ -+#define RSTV0910_GPIO12CFG 0xf14c -+#define FSTV0910_GPIO12_OPD 0xf14c0080 -+#define FSTV0910_GPIO12_CONFIG 0xf14c007e -+#define FSTV0910_GPIO12_XOR 0xf14c0001 -+ -+/*GPIO13CFG*/ -+#define RSTV0910_GPIO13CFG 0xf14d -+#define FSTV0910_GPIO13_OPD 0xf14d0080 -+#define FSTV0910_GPIO13_CONFIG 0xf14d007e -+#define FSTV0910_GPIO13_XOR 0xf14d0001 -+ -+/*GPIO14CFG*/ -+#define RSTV0910_GPIO14CFG 0xf14e -+#define FSTV0910_GPIO14_OPD 0xf14e0080 -+#define FSTV0910_GPIO14_CONFIG 0xf14e007e -+#define FSTV0910_GPIO14_XOR 0xf14e0001 -+ -+/*GPIO15CFG*/ -+#define RSTV0910_GPIO15CFG 0xf14f -+#define FSTV0910_GPIO15_OPD 0xf14f0080 -+#define FSTV0910_GPIO15_CONFIG 0xf14f007e -+#define FSTV0910_GPIO15_XOR 0xf14f0001 -+ -+/*GPIO16CFG*/ -+#define RSTV0910_GPIO16CFG 0xf150 -+#define FSTV0910_GPIO16_OPD 0xf1500080 -+#define FSTV0910_GPIO16_CONFIG 0xf150007e -+#define FSTV0910_GPIO16_XOR 0xf1500001 -+ -+/*GPIO17CFG*/ -+#define RSTV0910_GPIO17CFG 0xf151 -+#define FSTV0910_GPIO17_OPD 0xf1510080 -+#define FSTV0910_GPIO17_CONFIG 0xf151007e -+#define FSTV0910_GPIO17_XOR 0xf1510001 -+ -+/*GPIO18CFG*/ -+#define RSTV0910_GPIO18CFG 0xf152 -+#define FSTV0910_GPIO18_OPD 0xf1520080 -+#define FSTV0910_GPIO18_CONFIG 0xf152007e -+#define FSTV0910_GPIO18_XOR 0xf1520001 -+ -+/*GPIO19CFG*/ -+#define RSTV0910_GPIO19CFG 0xf153 -+#define FSTV0910_GPIO19_OPD 0xf1530080 -+#define FSTV0910_GPIO19_CONFIG 0xf153007e -+#define FSTV0910_GPIO19_XOR 0xf1530001 -+ -+/*GPIO20CFG*/ -+#define RSTV0910_GPIO20CFG 0xf154 -+#define FSTV0910_GPIO20_OPD 0xf1540080 -+#define FSTV0910_GPIO20_CONFIG 0xf154007e -+#define FSTV0910_GPIO20_XOR 0xf1540001 -+ -+/*GPIO21CFG*/ -+#define RSTV0910_GPIO21CFG 0xf155 -+#define FSTV0910_GPIO21_OPD 0xf1550080 -+#define FSTV0910_GPIO21_CONFIG 0xf155007e -+#define FSTV0910_GPIO21_XOR 0xf1550001 -+ -+/*GPIO22CFG*/ -+#define RSTV0910_GPIO22CFG 0xf156 -+#define FSTV0910_GPIO22_OPD 0xf1560080 -+#define FSTV0910_GPIO22_CONFIG 0xf156007e -+#define FSTV0910_GPIO22_XOR 0xf1560001 -+ -+/*STRSTATUS1*/ -+#define RSTV0910_STRSTATUS1 0xf16a -+#define FSTV0910_STRSTATUS_SEL2 0xf16a00f0 -+#define FSTV0910_STRSTATUS_SEL1 0xf16a000f -+ -+/*STRSTATUS2*/ -+#define RSTV0910_STRSTATUS2 0xf16b -+#define FSTV0910_STRSTATUS_SEL4 0xf16b00f0 -+#define FSTV0910_STRSTATUS_SEL3 0xf16b000f -+ -+/*STRSTATUS3*/ -+#define RSTV0910_STRSTATUS3 0xf16c -+#define FSTV0910_STRSTATUS_SEL6 0xf16c00f0 -+#define FSTV0910_STRSTATUS_SEL5 0xf16c000f -+ -+/*FSKTFC2*/ -+#define RSTV0910_FSKTFC2 0xf170 -+#define FSTV0910_FSKT_KMOD 0xf17000fc -+#define FSTV0910_FSKT_CAR2 0xf1700003 -+ -+/*FSKTFC1*/ -+#define RSTV0910_FSKTFC1 0xf171 -+#define FSTV0910_FSKT_CAR1 0xf17100ff -+ -+/*FSKTFC0*/ -+#define RSTV0910_FSKTFC0 0xf172 -+#define FSTV0910_FSKT_CAR0 0xf17200ff -+ -+/*FSKTDELTAF1*/ -+#define RSTV0910_FSKTDELTAF1 0xf173 -+#define FSTV0910_FSKT_DELTAF1 0xf173000f -+ -+/*FSKTDELTAF0*/ -+#define RSTV0910_FSKTDELTAF0 0xf174 -+#define FSTV0910_FSKT_DELTAF0 0xf17400ff -+ -+/*FSKTCTRL*/ -+#define RSTV0910_FSKTCTRL 0xf175 -+#define FSTV0910_FSKT_PINSEL 0xf1750080 -+#define FSTV0910_FSKT_EN_SGN 0xf1750040 -+#define FSTV0910_FSKT_MOD_SGN 0xf1750020 -+#define FSTV0910_FSKT_MOD_EN 0xf175001c -+#define FSTV0910_FSKT_DACMODE 0xf1750003 -+ -+/*FSKRFC2*/ -+#define RSTV0910_FSKRFC2 0xf176 -+#define FSTV0910_FSKR_DETSGN 0xf1760040 -+#define FSTV0910_FSKR_OUTSGN 0xf1760020 -+#define FSTV0910_FSKR_KAGC 0xf176001c -+#define FSTV0910_FSKR_CAR2 0xf1760003 -+ -+/*FSKRFC1*/ -+#define RSTV0910_FSKRFC1 0xf177 -+#define FSTV0910_FSKR_CAR1 0xf17700ff -+ -+/*FSKRFC0*/ -+#define RSTV0910_FSKRFC0 0xf178 -+#define FSTV0910_FSKR_CAR0 0xf17800ff -+ -+/*FSKRK1*/ -+#define RSTV0910_FSKRK1 0xf179 -+#define FSTV0910_FSKR_K1_EXP 0xf17900e0 -+#define FSTV0910_FSKR_K1_MANT 0xf179001f -+ -+/*FSKRK2*/ -+#define RSTV0910_FSKRK2 0xf17a -+#define FSTV0910_FSKR_K2_EXP 0xf17a00e0 -+#define FSTV0910_FSKR_K2_MANT 0xf17a001f -+ -+/*FSKRAGCR*/ -+#define RSTV0910_FSKRAGCR 0xf17b -+#define FSTV0910_FSKR_OUTCTL 0xf17b00c0 -+#define FSTV0910_FSKR_AGC_REF 0xf17b003f -+ -+/*FSKRAGC*/ -+#define RSTV0910_FSKRAGC 0xf17c -+#define FSTV0910_FSKR_AGC_ACCU 0xf17c00ff -+ -+/*FSKRALPHA*/ -+#define RSTV0910_FSKRALPHA 0xf17d -+#define FSTV0910_FSKR_ALPHA_EXP 0xf17d001c -+#define FSTV0910_FSKR_ALPHA_M 0xf17d0003 -+ -+/*FSKRPLTH1*/ -+#define RSTV0910_FSKRPLTH1 0xf17e -+#define FSTV0910_FSKR_BETA 0xf17e00f0 -+#define FSTV0910_FSKR_PLL_TRESH1 0xf17e000f -+ -+/*FSKRPLTH0*/ -+#define RSTV0910_FSKRPLTH0 0xf17f -+#define FSTV0910_FSKR_PLL_TRESH0 0xf17f00ff -+ -+/*FSKRDF1*/ -+#define RSTV0910_FSKRDF1 0xf180 -+#define FSTV0910_FSKR_OUT 0xf1800080 -+#define FSTV0910_FSKR_STATE 0xf1800060 -+#define FSTV0910_FSKR_DELTAF1 0xf180001f -+ -+/*FSKRDF0*/ -+#define RSTV0910_FSKRDF0 0xf181 -+#define FSTV0910_FSKR_DELTAF0 0xf18100ff -+ -+/*FSKRSTEPP*/ -+#define RSTV0910_FSKRSTEPP 0xf182 -+#define FSTV0910_FSKR_STEP_PLUS 0xf18200ff -+ -+/*FSKRSTEPM*/ -+#define RSTV0910_FSKRSTEPM 0xf183 -+#define FSTV0910_FSKR_STEP_MINUS 0xf18300ff -+ -+/*FSKRDET1*/ -+#define RSTV0910_FSKRDET1 0xf184 -+#define FSTV0910_FSKR_DETECT 0xf1840080 -+#define FSTV0910_FSKR_CARDET_ACCU1 0xf184000f -+ -+/*FSKRDET0*/ -+#define RSTV0910_FSKRDET0 0xf185 -+#define FSTV0910_FSKR_CARDET_ACCU0 0xf18500ff -+ -+/*FSKRDTH1*/ -+#define RSTV0910_FSKRDTH1 0xf186 -+#define FSTV0910_FSKR_CARLOSS_THRESH1 0xf18600f0 -+#define FSTV0910_FSKR_CARDET_THRESH1 0xf186000f -+ -+/*FSKRDTH0*/ -+#define RSTV0910_FSKRDTH0 0xf187 -+#define FSTV0910_FSKR_CARDET_THRESH0 0xf18700ff -+ -+/*FSKRLOSS*/ -+#define RSTV0910_FSKRLOSS 0xf188 -+#define FSTV0910_FSKR_CARLOSS_THRESH0 0xf18800ff -+ -+/*NCOARSE*/ -+#define RSTV0910_NCOARSE 0xf1b3 -+#define FSTV0910_CP 0xf1b300f8 -+#define FSTV0910_IDF 0xf1b30007 -+ -+/*NCOARSE1*/ -+#define RSTV0910_NCOARSE1 0xf1b4 -+#define FSTV0910_N_DIV 0xf1b400ff -+ -+/*NCOARSE2*/ -+#define RSTV0910_NCOARSE2 0xf1b5 -+#define FSTV0910_ODF 0xf1b5003f -+ -+/*SYNTCTRL*/ -+#define RSTV0910_SYNTCTRL 0xf1b6 -+#define FSTV0910_STANDBY 0xf1b60080 -+#define FSTV0910_BYPASSPLLCORE 0xf1b60040 -+#define FSTV0910_STOP_PLL 0xf1b60008 -+#define FSTV0910_OSCI_E 0xf1b60002 -+ -+/*FILTCTRL*/ -+#define RSTV0910_FILTCTRL 0xf1b7 -+#define FSTV0910_INV_CLKFSK 0xf1b70002 -+#define FSTV0910_BYPASS_APPLI 0xf1b70001 -+ -+/*PLLSTAT*/ -+#define RSTV0910_PLLSTAT 0xf1b8 -+#define FSTV0910_PLL_BIST_END 0xf1b80004 -+#define FSTV0910_PLLLOCK 0xf1b80001 -+ -+/*STOPCLK1*/ -+#define RSTV0910_STOPCLK1 0xf1c2 -+#define FSTV0910_INV_CLKADCI2 0xf1c20004 -+#define FSTV0910_INV_CLKADCI1 0xf1c20001 -+ -+/*STOPCLK2*/ -+#define RSTV0910_STOPCLK2 0xf1c3 -+#define FSTV0910_STOP_DVBS2FEC2 0xf1c30020 -+#define FSTV0910_STOP_DVBS2FEC 0xf1c30010 -+#define FSTV0910_STOP_DVBS1FEC2 0xf1c30008 -+#define FSTV0910_STOP_DVBS1FEC 0xf1c30004 -+#define FSTV0910_STOP_DEMOD2 0xf1c30002 -+#define FSTV0910_STOP_DEMOD 0xf1c30001 -+ -+/*PREGCTL*/ -+#define RSTV0910_PREGCTL 0xf1c8 -+#define FSTV0910_REG3V3TO2V5_POFF 0xf1c80080 -+ -+/*TSTTNR0*/ -+#define RSTV0910_TSTTNR0 0xf1df -+#define FSTV0910_FSK_PON 0xf1df0004 -+#define FSTV0910_FSK_OPENLOOP 0xf1df0002 -+ -+/*TSTTNR1*/ -+#define RSTV0910_TSTTNR1 0xf1e0 -+#define FSTV0910_BYPASS_ADC1 0xf1e00080 -+#define FSTV0910_INVADC1_CKOUT 0xf1e00040 -+#define FSTV0910_SELIQSRC1 0xf1e00030 -+#define FSTV0910_DEMOD2_SELADC 0xf1e00008 -+#define FSTV0910_DEMOD1_SELADC 0xf1e00004 -+#define FSTV0910_ADC1_PON 0xf1e00002 -+ -+/*TSTTNR2*/ -+#define RSTV0910_TSTTNR2 0xf1e1 -+#define FSTV0910_I2C_DISEQC_BYPASS 0xf1e10080 -+#define FSTV0910_I2C_DISEQC_ENCH 0xf1e10040 -+#define FSTV0910_I2C_DISEQC_PON 0xf1e10020 -+#define FSTV0910_DISEQC_CLKDIV 0xf1e1000f -+ -+/*TSTTNR3*/ -+#define RSTV0910_TSTTNR3 0xf1e2 -+#define FSTV0910_BYPASS_ADC2 0xf1e20080 -+#define FSTV0910_INVADC2_CKOUT 0xf1e20040 -+#define FSTV0910_SELIQSRC2 0xf1e20030 -+#define FSTV0910_ADC2_PON 0xf1e20002 -+ -+/*P2_IQCONST*/ -+#define RSTV0910_P2_IQCONST 0xf200 -+#define FSTV0910_P2_CONSTEL_SELECT 0xf2000060 -+#define FSTV0910_P2_IQSYMB_SEL 0xf200001f -+ -+/*P2_NOSCFG*/ -+#define RSTV0910_P2_NOSCFG 0xf201 -+#define FSTV0910_P2_DIS_ACMRATIO 0xf2010080 -+#define FSTV0910_P2_NOSIN_EGALSEL 0xf2010040 -+#define FSTV0910_P2_DUMMYPL_NOSDATA 0xf2010020 -+#define FSTV0910_P2_NOSPLH_BETA 0xf2010018 -+#define FSTV0910_P2_NOSDATA_BETA 0xf2010007 -+ -+/*P2_ISYMB*/ -+#define RSTV0910_P2_ISYMB 0xf202 -+#define FSTV0910_P2_I_SYMBOL 0xf20201ff -+ -+/*P2_QSYMB*/ -+#define RSTV0910_P2_QSYMB 0xf203 -+#define FSTV0910_P2_Q_SYMBOL 0xf20301ff -+ -+/*P2_AGC1CFG*/ -+#define RSTV0910_P2_AGC1CFG 0xf204 -+#define FSTV0910_P2_DC_FROZEN 0xf2040080 -+#define FSTV0910_P2_DC_CORRECT 0xf2040040 -+#define FSTV0910_P2_AMM_FROZEN 0xf2040020 -+#define FSTV0910_P2_AMM_CORRECT 0xf2040010 -+#define FSTV0910_P2_QUAD_FROZEN 0xf2040008 -+#define FSTV0910_P2_QUAD_CORRECT 0xf2040004 -+#define FSTV0910_P2_DCCOMP_SLOW 0xf2040002 -+#define FSTV0910_P2_IQMISM_SLOW 0xf2040001 -+ -+/*P2_AGC1CN*/ -+#define RSTV0910_P2_AGC1CN 0xf206 -+#define FSTV0910_P2_AGC1_LOCKED 0xf2060080 -+#define FSTV0910_P2_AGC1_OVERFLOW 0xf2060040 -+#define FSTV0910_P2_AGC1_NOSLOWLK 0xf2060020 -+#define FSTV0910_P2_AGC1_MINPOWER 0xf2060010 -+#define FSTV0910_P2_AGCOUT_FAST 0xf2060008 -+#define FSTV0910_P2_AGCIQ_BETA 0xf2060007 -+ -+/*P2_AGC1REF*/ -+#define RSTV0910_P2_AGC1REF 0xf207 -+#define FSTV0910_P2_AGCIQ_REF 0xf20700ff -+ -+/*P2_IDCCOMP*/ -+#define RSTV0910_P2_IDCCOMP 0xf208 -+#define FSTV0910_P2_IAVERAGE_ADJ 0xf20801ff -+ -+/*P2_QDCCOMP*/ -+#define RSTV0910_P2_QDCCOMP 0xf209 -+#define FSTV0910_P2_QAVERAGE_ADJ 0xf20901ff -+ -+/*P2_POWERI*/ -+#define RSTV0910_P2_POWERI 0xf20a -+#define FSTV0910_P2_POWER_I 0xf20a00ff -+ -+/*P2_POWERQ*/ -+#define RSTV0910_P2_POWERQ 0xf20b -+#define FSTV0910_P2_POWER_Q 0xf20b00ff -+ -+/*P2_AGC1AMM*/ -+#define RSTV0910_P2_AGC1AMM 0xf20c -+#define FSTV0910_P2_AMM_VALUE 0xf20c00ff -+ -+/*P2_AGC1QUAD*/ -+#define RSTV0910_P2_AGC1QUAD 0xf20d -+#define FSTV0910_P2_QUAD_VALUE 0xf20d01ff -+ -+/*P2_AGCIQIN1*/ -+#define RSTV0910_P2_AGCIQIN1 0xf20e -+#define FSTV0910_P2_AGCIQ_VALUE1 0xf20e00ff -+ -+/*P2_AGCIQIN0*/ -+#define RSTV0910_P2_AGCIQIN0 0xf20f -+#define FSTV0910_P2_AGCIQ_VALUE0 0xf20f00ff -+ -+/*P2_DEMOD*/ -+#define RSTV0910_P2_DEMOD 0xf210 -+#define FSTV0910_P2_MANUALS2_ROLLOFF 0xf2100080 -+#define FSTV0910_P2_SPECINV_CONTROL 0xf2100030 -+#define FSTV0910_P2_MANUALSX_ROLLOFF 0xf2100004 -+#define FSTV0910_P2_ROLLOFF_CONTROL 0xf2100003 -+ -+/*P2_DMDMODCOD*/ -+#define RSTV0910_P2_DMDMODCOD 0xf211 -+#define FSTV0910_P2_MANUAL_MODCOD 0xf2110080 -+#define FSTV0910_P2_DEMOD_MODCOD 0xf211007c -+#define FSTV0910_P2_DEMOD_TYPE 0xf2110003 -+ -+/*P2_DSTATUS*/ -+#define RSTV0910_P2_DSTATUS 0xf212 -+#define FSTV0910_P2_CAR_LOCK 0xf2120080 -+#define FSTV0910_P2_TMGLOCK_QUALITY 0xf2120060 -+#define FSTV0910_P2_SDVBS1_ENABLE 0xf2120010 -+#define FSTV0910_P2_LOCK_DEFINITIF 0xf2120008 -+#define FSTV0910_P2_TIMING_IS_LOCKED 0xf2120004 -+#define FSTV0910_P2_DEMOD_SYSCFG 0xf2120002 -+#define FSTV0910_P2_OVADC_DETECT 0xf2120001 -+ -+/*P2_DSTATUS2*/ -+#define RSTV0910_P2_DSTATUS2 0xf213 -+#define FSTV0910_P2_DEMOD_DELOCK 0xf2130080 -+#define FSTV0910_P2_DEMOD_TIMEOUT 0xf2130040 -+#define FSTV0910_P2_MODCODRQ_SYNCTAG 0xf2130020 -+#define FSTV0910_P2_POLYPH_SATEVENT 0xf2130010 -+#define FSTV0910_P2_AGC1_NOSIGNALACK 0xf2130008 -+#define FSTV0910_P2_AGC2_OVERFLOW 0xf2130004 -+#define FSTV0910_P2_CFR_OVERFLOW 0xf2130002 -+#define FSTV0910_P2_GAMMA_OVERUNDER 0xf2130001 -+ -+/*P2_DMDCFGMD*/ -+#define RSTV0910_P2_DMDCFGMD 0xf214 -+#define FSTV0910_P2_DVBS2_ENABLE 0xf2140080 -+#define FSTV0910_P2_DVBS1_ENABLE 0xf2140040 -+#define FSTV0910_P2_SCAN_ENABLE 0xf2140010 -+#define FSTV0910_P2_CFR_AUTOSCAN 0xf2140008 -+#define FSTV0910_P2_NOFORCE_RELOCK 0xf2140004 -+#define FSTV0910_P2_TUN_RNG 0xf2140003 -+ -+/*P2_DMDCFG2*/ -+#define RSTV0910_P2_DMDCFG2 0xf215 -+#define FSTV0910_P2_AGC1_WAITLOCK 0xf2150080 -+#define FSTV0910_P2_S1S2_SEQUENTIAL 0xf2150040 -+#define FSTV0910_P2_BLINDPEA_MODE 0xf2150020 -+#define FSTV0910_P2_INFINITE_RELOCK 0xf2150010 -+#define FSTV0910_P2_BWOFFSET_COLDWARM 0xf2150008 -+#define FSTV0910_P2_TMGLOCK_NSCANSTOP 0xf2150004 -+#define FSTV0910_P2_COARSE_LK3MODE 0xf2150002 -+#define FSTV0910_P2_COARSE_LK2MODE 0xf2150001 -+ -+/*P2_DMDISTATE*/ -+#define RSTV0910_P2_DMDISTATE 0xf216 -+#define FSTV0910_P2_I2C_NORESETDMODE 0xf2160080 -+#define FSTV0910_P2_FORCE_ETAPED 0xf2160040 -+#define FSTV0910_P2_SDMDRST_DIRCLK 0xf2160020 -+#define FSTV0910_P2_I2C_DEMOD_MODE 0xf216001f -+ -+/*P2_DMDT0M*/ -+#define RSTV0910_P2_DMDT0M 0xf217 -+#define FSTV0910_P2_DMDT0_MIN 0xf21700ff -+ -+/*P2_DMDSTATE*/ -+#define RSTV0910_P2_DMDSTATE 0xf21b -+#define FSTV0910_P2_DEMOD_LOCKED 0xf21b0080 -+#define FSTV0910_P2_HEADER_MODE 0xf21b0060 -+#define FSTV0910_P2_DEMOD_MODE 0xf21b001f -+ -+/*P2_DMDFLYW*/ -+#define RSTV0910_P2_DMDFLYW 0xf21c -+#define FSTV0910_P2_I2C_IRQVAL 0xf21c00f0 -+#define FSTV0910_P2_FLYWHEEL_CPT 0xf21c000f -+ -+/*P2_DSTATUS3*/ -+#define RSTV0910_P2_DSTATUS3 0xf21d -+#define FSTV0910_P2_CFR_ZIGZAG 0xf21d0080 -+#define FSTV0910_P2_DEMOD_CFGMODE 0xf21d0060 -+#define FSTV0910_P2_GAMMA_LOWBAUDRATE 0xf21d0010 -+#define FSTV0910_P2_RELOCK_MODE 0xf21d0008 -+#define FSTV0910_P2_DEMOD_FAIL 0xf21d0004 -+#define FSTV0910_P2_ETAPE1A_DVBXMEM 0xf21d0003 -+ -+/*P2_DMDCFG3*/ -+#define RSTV0910_P2_DMDCFG3 0xf21e -+#define FSTV0910_P2_DVBS1_TMGWAIT 0xf21e0080 -+#define FSTV0910_P2_NO_BWCENTERING 0xf21e0040 -+#define FSTV0910_P2_INV_SEQSRCH 0xf21e0020 -+#define FSTV0910_P2_DIS_SFRUPLOW_TRK 0xf21e0010 -+#define FSTV0910_P2_NOSTOP_FIFOFULL 0xf21e0008 -+#define FSTV0910_P2_LOCKTIME_MODE 0xf21e0007 -+ -+/*P2_DMDCFG4*/ -+#define RSTV0910_P2_DMDCFG4 0xf21f -+#define FSTV0910_P2_DIS_VITLOCK 0xf21f0080 -+#define FSTV0910_P2_S1S2TOUT_FAST 0xf21f0040 -+#define FSTV0910_P2_DEMOD_FASTLOCK 0xf21f0020 -+#define FSTV0910_P2_S1HIER_ENABLE 0xf21f0010 -+#define FSTV0910_P2_TUNER_NRELAUNCH 0xf21f0008 -+#define FSTV0910_P2_DIS_CLKENABLE 0xf21f0004 -+#define FSTV0910_P2_DIS_HDRDIVLOCK 0xf21f0002 -+#define FSTV0910_P2_NO_TNRWBINIT 0xf21f0001 -+ -+/*P2_CORRELMANT*/ -+#define RSTV0910_P2_CORRELMANT 0xf220 -+#define FSTV0910_P2_CORREL_MANT 0xf22000ff -+ -+/*P2_CORRELABS*/ -+#define RSTV0910_P2_CORRELABS 0xf221 -+#define FSTV0910_P2_CORREL_ABS 0xf22100ff -+ -+/*P2_CORRELEXP*/ -+#define RSTV0910_P2_CORRELEXP 0xf222 -+#define FSTV0910_P2_CORREL_ABSEXP 0xf22200f0 -+#define FSTV0910_P2_CORREL_EXP 0xf222000f -+ -+/*P2_PLHMODCOD*/ -+#define RSTV0910_P2_PLHMODCOD 0xf224 -+#define FSTV0910_P2_SPECINV_DEMOD 0xf2240080 -+#define FSTV0910_P2_PLH_MODCOD 0xf224007c -+#define FSTV0910_P2_PLH_TYPE 0xf2240003 -+ -+/*P2_DMDREG*/ -+#define RSTV0910_P2_DMDREG 0xf225 -+#define FSTV0910_P2_EXTPSK_MODE 0xf2250080 -+#define FSTV0910_P2_HIER_SHORTFRAME 0xf2250002 -+#define FSTV0910_P2_DECIM_PLFRAMES 0xf2250001 -+ -+/*P2_AGC2O*/ -+#define RSTV0910_P2_AGC2O 0xf22c -+#define FSTV0910_P2_CSTENV_MODE 0xf22c00c0 -+#define FSTV0910_P2_AGC2_LKSQRT 0xf22c0020 -+#define FSTV0910_P2_AGC2_LKMODE 0xf22c0010 -+#define FSTV0910_P2_AGC2_LKEQUA 0xf22c0008 -+#define FSTV0910_P2_AGC2_COEF 0xf22c0007 -+ -+/*P2_AGC2REF*/ -+#define RSTV0910_P2_AGC2REF 0xf22d -+#define FSTV0910_P2_AGC2_REF 0xf22d00ff -+ -+/*P2_AGC1ADJ*/ -+#define RSTV0910_P2_AGC1ADJ 0xf22e -+#define FSTV0910_P2_AGC1ADJ_MANUAL 0xf22e0080 -+#define FSTV0910_P2_AGC1_ADJUSTED 0xf22e007f -+ -+/*P2_AGC2I1*/ -+#define RSTV0910_P2_AGC2I1 0xf236 -+#define FSTV0910_P2_AGC2_INTEGRATOR1 0xf23600ff -+ -+/*P2_AGC2I0*/ -+#define RSTV0910_P2_AGC2I0 0xf237 -+#define FSTV0910_P2_AGC2_INTEGRATOR0 0xf23700ff -+ -+/*P2_CARCFG*/ -+#define RSTV0910_P2_CARCFG 0xf238 -+#define FSTV0910_P2_CFRUPLOW_AUTO 0xf2380080 -+#define FSTV0910_P2_CFRUPLOW_TEST 0xf2380040 -+#define FSTV0910_P2_WIDE_FREQDET 0xf2380020 -+#define FSTV0910_P2_CARHDR_NODIV8 0xf2380010 -+#define FSTV0910_P2_I2C_ROTA 0xf2380008 -+#define FSTV0910_P2_ROTAON 0xf2380004 -+#define FSTV0910_P2_PH_DET_ALGO 0xf2380003 -+ -+/*P2_ACLC*/ -+#define RSTV0910_P2_ACLC 0xf239 -+#define FSTV0910_P2_CARS1_ANOSAUTO 0xf2390040 -+#define FSTV0910_P2_CAR_ALPHA_MANT 0xf2390030 -+#define FSTV0910_P2_CAR_ALPHA_EXP 0xf239000f -+ -+/*P2_BCLC*/ -+#define RSTV0910_P2_BCLC 0xf23a -+#define FSTV0910_P2_CARS1_BNOSAUTO 0xf23a0040 -+#define FSTV0910_P2_CAR_BETA_MANT 0xf23a0030 -+#define FSTV0910_P2_CAR_BETA_EXP 0xf23a000f -+ -+/*P2_CARFREQ*/ -+#define RSTV0910_P2_CARFREQ 0xf23d -+#define FSTV0910_P2_KC_COARSE_EXP 0xf23d00f0 -+#define FSTV0910_P2_BETA_FREQ 0xf23d000f -+ -+/*P2_CARHDR*/ -+#define RSTV0910_P2_CARHDR 0xf23e -+#define FSTV0910_P2_K_FREQ_HDR 0xf23e00ff -+ -+/*P2_LDT*/ -+#define RSTV0910_P2_LDT 0xf23f -+#define FSTV0910_P2_CARLOCK_THRES 0xf23f01ff -+ -+/*P2_LDT2*/ -+#define RSTV0910_P2_LDT2 0xf240 -+#define FSTV0910_P2_CARLOCK_THRES2 0xf24001ff -+ -+/*P2_CFRICFG*/ -+#define RSTV0910_P2_CFRICFG 0xf241 -+#define FSTV0910_P2_CFRINIT_UNVALRNG 0xf2410080 -+#define FSTV0910_P2_CFRINIT_LUNVALCPT 0xf2410040 -+#define FSTV0910_P2_CFRINIT_ABORTDBL 0xf2410020 -+#define FSTV0910_P2_CFRINIT_ABORTPRED 0xf2410010 -+#define FSTV0910_P2_CFRINIT_UNVALSKIP 0xf2410008 -+#define FSTV0910_P2_CFRINIT_CSTINC 0xf2410004 -+#define FSTV0910_P2_CFRIROLL_GARDER 0xf2410002 -+#define FSTV0910_P2_NEG_CFRSTEP 0xf2410001 -+ -+/*P2_CFRUP1*/ -+#define RSTV0910_P2_CFRUP1 0xf242 -+#define FSTV0910_P2_CFR_UP1 0xf24201ff -+ -+/*P2_CFRUP0*/ -+#define RSTV0910_P2_CFRUP0 0xf243 -+#define FSTV0910_P2_CFR_UP0 0xf24300ff -+ -+/*P2_CFRIBASE1*/ -+#define RSTV0910_P2_CFRIBASE1 0xf244 -+#define FSTV0910_P2_CFRINIT_BASE1 0xf24400ff -+ -+/*P2_CFRIBASE0*/ -+#define RSTV0910_P2_CFRIBASE0 0xf245 -+#define FSTV0910_P2_CFRINIT_BASE0 0xf24500ff -+ -+/*P2_CFRLOW1*/ -+#define RSTV0910_P2_CFRLOW1 0xf246 -+#define FSTV0910_P2_CFR_LOW1 0xf24601ff -+ -+/*P2_CFRLOW0*/ -+#define RSTV0910_P2_CFRLOW0 0xf247 -+#define FSTV0910_P2_CFR_LOW0 0xf24700ff -+ -+/*P2_CFRINIT1*/ -+#define RSTV0910_P2_CFRINIT1 0xf248 -+#define FSTV0910_P2_CFR_INIT1 0xf24801ff -+ -+/*P2_CFRINIT0*/ -+#define RSTV0910_P2_CFRINIT0 0xf249 -+#define FSTV0910_P2_CFR_INIT0 0xf24900ff -+ -+/*P2_CFRINC1*/ -+#define RSTV0910_P2_CFRINC1 0xf24a -+#define FSTV0910_P2_MANUAL_CFRINC 0xf24a0080 -+#define FSTV0910_P2_CFR_INC1 0xf24a003f -+ -+/*P2_CFRINC0*/ -+#define RSTV0910_P2_CFRINC0 0xf24b -+#define FSTV0910_P2_CFR_INC0 0xf24b00ff -+ -+/*P2_CFR2*/ -+#define RSTV0910_P2_CFR2 0xf24c -+#define FSTV0910_P2_CAR_FREQ2 0xf24c01ff -+ -+/*P2_CFR1*/ -+#define RSTV0910_P2_CFR1 0xf24d -+#define FSTV0910_P2_CAR_FREQ1 0xf24d00ff -+ -+/*P2_CFR0*/ -+#define RSTV0910_P2_CFR0 0xf24e -+#define FSTV0910_P2_CAR_FREQ0 0xf24e00ff -+ -+/*P2_LDI*/ -+#define RSTV0910_P2_LDI 0xf24f -+#define FSTV0910_P2_LOCK_DET_INTEGR 0xf24f01ff -+ -+/*P2_TMGCFG*/ -+#define RSTV0910_P2_TMGCFG 0xf250 -+#define FSTV0910_P2_TMGLOCK_BETA 0xf25000c0 -+#define FSTV0910_P2_DO_TIMING_CORR 0xf2500010 -+#define FSTV0910_P2_MANUAL_SCAN 0xf250000c -+#define FSTV0910_P2_TMG_MINFREQ 0xf2500003 -+ -+/*P2_RTC*/ -+#define RSTV0910_P2_RTC 0xf251 -+#define FSTV0910_P2_TMGALPHA_EXP 0xf25100f0 -+#define FSTV0910_P2_TMGBETA_EXP 0xf251000f -+ -+/*P2_RTCS2*/ -+#define RSTV0910_P2_RTCS2 0xf252 -+#define FSTV0910_P2_TMGALPHAS2_EXP 0xf25200f0 -+#define FSTV0910_P2_TMGBETAS2_EXP 0xf252000f -+ -+/*P2_TMGTHRISE*/ -+#define RSTV0910_P2_TMGTHRISE 0xf253 -+#define FSTV0910_P2_TMGLOCK_THRISE 0xf25300ff -+ -+/*P2_TMGTHFALL*/ -+#define RSTV0910_P2_TMGTHFALL 0xf254 -+#define FSTV0910_P2_TMGLOCK_THFALL 0xf25400ff -+ -+/*P2_SFRUPRATIO*/ -+#define RSTV0910_P2_SFRUPRATIO 0xf255 -+#define FSTV0910_P2_SFR_UPRATIO 0xf25500ff -+ -+/*P2_SFRLOWRATIO*/ -+#define RSTV0910_P2_SFRLOWRATIO 0xf256 -+#define FSTV0910_P2_SFR_LOWRATIO 0xf25600ff -+ -+/*P2_KTTMG*/ -+#define RSTV0910_P2_KTTMG 0xf257 -+#define FSTV0910_P2_KT_TMG_EXP 0xf25700f0 -+ -+/*P2_KREFTMG*/ -+#define RSTV0910_P2_KREFTMG 0xf258 -+#define FSTV0910_P2_KREF_TMG 0xf25800ff -+ -+/*P2_SFRSTEP*/ -+#define RSTV0910_P2_SFRSTEP 0xf259 -+#define FSTV0910_P2_SFR_SCANSTEP 0xf25900f0 -+#define FSTV0910_P2_SFR_CENTERSTEP 0xf259000f -+ -+/*P2_TMGCFG2*/ -+#define RSTV0910_P2_TMGCFG2 0xf25a -+#define FSTV0910_P2_KREFTMG2_DECMODE 0xf25a00c0 -+#define FSTV0910_P2_DIS_AUTOSAMP 0xf25a0008 -+#define FSTV0910_P2_SCANINIT_QUART 0xf25a0004 -+#define FSTV0910_P2_NOTMG_DVBS1DERAT 0xf25a0002 -+#define FSTV0910_P2_SFRRATIO_FINE 0xf25a0001 -+ -+/*P2_KREFTMG2*/ -+#define RSTV0910_P2_KREFTMG2 0xf25b -+#define FSTV0910_P2_KREF_TMG2 0xf25b00ff -+ -+/*P2_TMGCFG3*/ -+#define RSTV0910_P2_TMGCFG3 0xf25d -+#define FSTV0910_P2_CFRINC_MODE 0xf25d0070 -+#define FSTV0910_P2_CONT_TMGCENTER 0xf25d0008 -+#define FSTV0910_P2_AUTO_GUP 0xf25d0004 -+#define FSTV0910_P2_AUTO_GLOW 0xf25d0002 -+#define FSTV0910_P2_SFRVAL_MINMODE 0xf25d0001 -+ -+/*P2_SFRINIT1*/ -+#define RSTV0910_P2_SFRINIT1 0xf25e -+#define FSTV0910_P2_SFR_INIT1 0xf25e00ff -+ -+/*P2_SFRINIT0*/ -+#define RSTV0910_P2_SFRINIT0 0xf25f -+#define FSTV0910_P2_SFR_INIT0 0xf25f00ff -+ -+/*P2_SFRUP1*/ -+#define RSTV0910_P2_SFRUP1 0xf260 -+#define FSTV0910_P2_SYMB_FREQ_UP1 0xf26000ff -+ -+/*P2_SFRUP0*/ -+#define RSTV0910_P2_SFRUP0 0xf261 -+#define FSTV0910_P2_SYMB_FREQ_UP0 0xf26100ff -+ -+/*P2_SFRLOW1*/ -+#define RSTV0910_P2_SFRLOW1 0xf262 -+#define FSTV0910_P2_SYMB_FREQ_LOW1 0xf26200ff -+ -+/*P2_SFRLOW0*/ -+#define RSTV0910_P2_SFRLOW0 0xf263 -+#define FSTV0910_P2_SYMB_FREQ_LOW0 0xf26300ff -+ -+/*P2_SFR3*/ -+#define RSTV0910_P2_SFR3 0xf264 -+#define FSTV0910_P2_SYMB_FREQ3 0xf26400ff -+ -+/*P2_SFR2*/ -+#define RSTV0910_P2_SFR2 0xf265 -+#define FSTV0910_P2_SYMB_FREQ2 0xf26500ff -+ -+/*P2_SFR1*/ -+#define RSTV0910_P2_SFR1 0xf266 -+#define FSTV0910_P2_SYMB_FREQ1 0xf26600ff -+ -+/*P2_SFR0*/ -+#define RSTV0910_P2_SFR0 0xf267 -+#define FSTV0910_P2_SYMB_FREQ0 0xf26700ff -+ -+/*P2_TMGREG2*/ -+#define RSTV0910_P2_TMGREG2 0xf268 -+#define FSTV0910_P2_TMGREG2 0xf26800ff -+ -+/*P2_TMGREG1*/ -+#define RSTV0910_P2_TMGREG1 0xf269 -+#define FSTV0910_P2_TMGREG1 0xf26900ff -+ -+/*P2_TMGREG0*/ -+#define RSTV0910_P2_TMGREG0 0xf26a -+#define FSTV0910_P2_TMGREG0 0xf26a00ff -+ -+/*P2_TMGLOCK1*/ -+#define RSTV0910_P2_TMGLOCK1 0xf26b -+#define FSTV0910_P2_TMGLOCK_LEVEL1 0xf26b01ff -+ -+/*P2_TMGLOCK0*/ -+#define RSTV0910_P2_TMGLOCK0 0xf26c -+#define FSTV0910_P2_TMGLOCK_LEVEL0 0xf26c00ff -+ -+/*P2_TMGOBS*/ -+#define RSTV0910_P2_TMGOBS 0xf26d -+#define FSTV0910_P2_ROLLOFF_STATUS 0xf26d00c0 -+#define FSTV0910_P2_SCAN_SIGN 0xf26d0030 -+#define FSTV0910_P2_TMG_SCANNING 0xf26d0008 -+#define FSTV0910_P2_CHCENTERING_MODE 0xf26d0004 -+#define FSTV0910_P2_TMG_SCANFAIL 0xf26d0002 -+ -+/*P2_EQUALCFG*/ -+#define RSTV0910_P2_EQUALCFG 0xf26f -+#define FSTV0910_P2_NOTMG_NEGALWAIT 0xf26f0080 -+#define FSTV0910_P2_EQUAL_ON 0xf26f0040 -+#define FSTV0910_P2_SEL_EQUALCOR 0xf26f0038 -+#define FSTV0910_P2_MU_EQUALDFE 0xf26f0007 -+ -+/*P2_EQUAI1*/ -+#define RSTV0910_P2_EQUAI1 0xf270 -+#define FSTV0910_P2_EQUA_ACCI1 0xf27001ff -+ -+/*P2_EQUAQ1*/ -+#define RSTV0910_P2_EQUAQ1 0xf271 -+#define FSTV0910_P2_EQUA_ACCQ1 0xf27101ff -+ -+/*P2_EQUAI2*/ -+#define RSTV0910_P2_EQUAI2 0xf272 -+#define FSTV0910_P2_EQUA_ACCI2 0xf27201ff -+ -+/*P2_EQUAQ2*/ -+#define RSTV0910_P2_EQUAQ2 0xf273 -+#define FSTV0910_P2_EQUA_ACCQ2 0xf27301ff -+ -+/*P2_EQUAI3*/ -+#define RSTV0910_P2_EQUAI3 0xf274 -+#define FSTV0910_P2_EQUA_ACCI3 0xf27401ff -+ -+/*P2_EQUAQ3*/ -+#define RSTV0910_P2_EQUAQ3 0xf275 -+#define FSTV0910_P2_EQUA_ACCQ3 0xf27501ff -+ -+/*P2_EQUAI4*/ -+#define RSTV0910_P2_EQUAI4 0xf276 -+#define FSTV0910_P2_EQUA_ACCI4 0xf27601ff -+ -+/*P2_EQUAQ4*/ -+#define RSTV0910_P2_EQUAQ4 0xf277 -+#define FSTV0910_P2_EQUA_ACCQ4 0xf27701ff -+ -+/*P2_EQUAI5*/ -+#define RSTV0910_P2_EQUAI5 0xf278 -+#define FSTV0910_P2_EQUA_ACCI5 0xf27801ff -+ -+/*P2_EQUAQ5*/ -+#define RSTV0910_P2_EQUAQ5 0xf279 -+#define FSTV0910_P2_EQUA_ACCQ5 0xf27901ff -+ -+/*P2_EQUAI6*/ -+#define RSTV0910_P2_EQUAI6 0xf27a -+#define FSTV0910_P2_EQUA_ACCI6 0xf27a01ff -+ -+/*P2_EQUAQ6*/ -+#define RSTV0910_P2_EQUAQ6 0xf27b -+#define FSTV0910_P2_EQUA_ACCQ6 0xf27b01ff -+ -+/*P2_EQUAI7*/ -+#define RSTV0910_P2_EQUAI7 0xf27c -+#define FSTV0910_P2_EQUA_ACCI7 0xf27c01ff -+ -+/*P2_EQUAQ7*/ -+#define RSTV0910_P2_EQUAQ7 0xf27d -+#define FSTV0910_P2_EQUA_ACCQ7 0xf27d01ff -+ -+/*P2_EQUAI8*/ -+#define RSTV0910_P2_EQUAI8 0xf27e -+#define FSTV0910_P2_EQUA_ACCI8 0xf27e01ff -+ -+/*P2_EQUAQ8*/ -+#define RSTV0910_P2_EQUAQ8 0xf27f -+#define FSTV0910_P2_EQUA_ACCQ8 0xf27f01ff -+ -+/*P2_NNOSDATAT1*/ -+#define RSTV0910_P2_NNOSDATAT1 0xf280 -+#define FSTV0910_P2_NOSDATAT_NORMED1 0xf28000ff -+ -+/*P2_NNOSDATAT0*/ -+#define RSTV0910_P2_NNOSDATAT0 0xf281 -+#define FSTV0910_P2_NOSDATAT_NORMED0 0xf28100ff -+ -+/*P2_NNOSDATA1*/ -+#define RSTV0910_P2_NNOSDATA1 0xf282 -+#define FSTV0910_P2_NOSDATA_NORMED1 0xf28200ff -+ -+/*P2_NNOSDATA0*/ -+#define RSTV0910_P2_NNOSDATA0 0xf283 -+#define FSTV0910_P2_NOSDATA_NORMED0 0xf28300ff -+ -+/*P2_NNOSPLHT1*/ -+#define RSTV0910_P2_NNOSPLHT1 0xf284 -+#define FSTV0910_P2_NOSPLHT_NORMED1 0xf28400ff -+ -+/*P2_NNOSPLHT0*/ -+#define RSTV0910_P2_NNOSPLHT0 0xf285 -+#define FSTV0910_P2_NOSPLHT_NORMED0 0xf28500ff -+ -+/*P2_NNOSPLH1*/ -+#define RSTV0910_P2_NNOSPLH1 0xf286 -+#define FSTV0910_P2_NOSPLH_NORMED1 0xf28600ff -+ -+/*P2_NNOSPLH0*/ -+#define RSTV0910_P2_NNOSPLH0 0xf287 -+#define FSTV0910_P2_NOSPLH_NORMED0 0xf28700ff -+ -+/*P2_NOSDATAT1*/ -+#define RSTV0910_P2_NOSDATAT1 0xf288 -+#define FSTV0910_P2_NOSDATAT_UNNORMED1 0xf28800ff -+ -+/*P2_NOSDATAT0*/ -+#define RSTV0910_P2_NOSDATAT0 0xf289 -+#define FSTV0910_P2_NOSDATAT_UNNORMED0 0xf28900ff -+ -+/*P2_NNOSFRAME1*/ -+#define RSTV0910_P2_NNOSFRAME1 0xf28a -+#define FSTV0910_P2_NOSFRAME_NORMED1 0xf28a00ff -+ -+/*P2_NNOSFRAME0*/ -+#define RSTV0910_P2_NNOSFRAME0 0xf28b -+#define FSTV0910_P2_NOSFRAME_NORMED0 0xf28b00ff -+ -+/*P2_NNOSRAD1*/ -+#define RSTV0910_P2_NNOSRAD1 0xf28c -+#define FSTV0910_P2_NOSRADIAL_NORMED1 0xf28c00ff -+ -+/*P2_NNOSRAD0*/ -+#define RSTV0910_P2_NNOSRAD0 0xf28d -+#define FSTV0910_P2_NOSRADIAL_NORMED0 0xf28d00ff -+ -+/*P2_NOSCFGF1*/ -+#define RSTV0910_P2_NOSCFGF1 0xf28e -+#define FSTV0910_P2_LOWNOISE_MESURE 0xf28e0080 -+#define FSTV0910_P2_NOS_DELFRAME 0xf28e0040 -+#define FSTV0910_P2_NOSDATA_MODE 0xf28e0030 -+#define FSTV0910_P2_FRAMESEL_TYPESEL 0xf28e000c -+#define FSTV0910_P2_FRAMESEL_TYPE 0xf28e0003 -+ -+/*P2_CAR2CFG*/ -+#define RSTV0910_P2_CAR2CFG 0xf290 -+#define FSTV0910_P2_DESCRAMB_OFF 0xf2900080 -+#define FSTV0910_P2_EN_PHNOSRAM 0xf2900020 -+#define FSTV0910_P2_STOP_CFR2UPDATE 0xf2900010 -+#define FSTV0910_P2_STOP_NCO2UPDATE 0xf2900008 -+#define FSTV0910_P2_ROTA2ON 0xf2900004 -+#define FSTV0910_P2_PH_DET_ALGO2 0xf2900003 -+ -+/*P2_CFR2CFR1*/ -+#define RSTV0910_P2_CFR2CFR1 0xf291 -+#define FSTV0910_P2_CFR2_S2CONTROL 0xf29100c0 -+#define FSTV0910_P2_EN_S2CAR2CENTER 0xf2910020 -+#define FSTV0910_P2_BCHERRCFR2_MODE 0xf2910018 -+#define FSTV0910_P2_CFR2TOCFR1_BETA 0xf2910007 -+ -+/*P2_CAR3CFG*/ -+#define RSTV0910_P2_CAR3CFG 0xf292 -+#define FSTV0910_P2_CARRIER23_MODE 0xf29200c0 -+#define FSTV0910_P2_CAR3INTERM_DVBS1 0xf2920020 -+#define FSTV0910_P2_ABAMPLIF_MODE 0xf2920018 -+#define FSTV0910_P2_CARRIER3_ALPHA3DL 0xf2920007 -+ -+/*P2_CFR22*/ -+#define RSTV0910_P2_CFR22 0xf293 -+#define FSTV0910_P2_CAR2_FREQ2 0xf29301ff -+ -+/*P2_CFR21*/ -+#define RSTV0910_P2_CFR21 0xf294 -+#define FSTV0910_P2_CAR2_FREQ1 0xf29400ff -+ -+/*P2_CFR20*/ -+#define RSTV0910_P2_CFR20 0xf295 -+#define FSTV0910_P2_CAR2_FREQ0 0xf29500ff -+ -+/*P2_ACLC2S2Q*/ -+#define RSTV0910_P2_ACLC2S2Q 0xf297 -+#define FSTV0910_P2_ENAB_SPSKSYMB 0xf2970080 -+#define FSTV0910_P2_CAR2S2_QANOSAUTO 0xf2970040 -+#define FSTV0910_P2_CAR2S2_Q_ALPH_M 0xf2970030 -+#define FSTV0910_P2_CAR2S2_Q_ALPH_E 0xf297000f -+ -+/*P2_ACLC2S28*/ -+#define RSTV0910_P2_ACLC2S28 0xf298 -+#define FSTV0910_P2_OLDI3Q_MODE 0xf2980080 -+#define FSTV0910_P2_CAR2S2_8ANOSAUTO 0xf2980040 -+#define FSTV0910_P2_CAR2S2_8_ALPH_M 0xf2980030 -+#define FSTV0910_P2_CAR2S2_8_ALPH_E 0xf298000f -+ -+/*P2_ACLC2S216A*/ -+#define RSTV0910_P2_ACLC2S216A 0xf299 -+#define FSTV0910_P2_CAR2S2_16ANOSAUTO 0xf2990040 -+#define FSTV0910_P2_CAR2S2_16A_ALPH_M 0xf2990030 -+#define FSTV0910_P2_CAR2S2_16A_ALPH_E 0xf299000f -+ -+/*P2_ACLC2S232A*/ -+#define RSTV0910_P2_ACLC2S232A 0xf29a -+#define FSTV0910_P2_CAR2S2_32ANOSUATO 0xf29a0040 -+#define FSTV0910_P2_CAR2S2_32A_ALPH_M 0xf29a0030 -+#define FSTV0910_P2_CAR2S2_32A_ALPH_E 0xf29a000f -+ -+/*P2_BCLC2S2Q*/ -+#define RSTV0910_P2_BCLC2S2Q 0xf29c -+#define FSTV0910_P2_DVBS2S2Q_NIP 0xf29c0080 -+#define FSTV0910_P2_CAR2S2_QBNOSAUTO 0xf29c0040 -+#define FSTV0910_P2_CAR2S2_Q_BETA_M 0xf29c0030 -+#define FSTV0910_P2_CAR2S2_Q_BETA_E 0xf29c000f -+ -+/*P2_BCLC2S28*/ -+#define RSTV0910_P2_BCLC2S28 0xf29d -+#define FSTV0910_P2_DVBS2S28_NIP 0xf29d0080 -+#define FSTV0910_P2_CAR2S2_8BNOSAUTO 0xf29d0040 -+#define FSTV0910_P2_CAR2S2_8_BETA_M 0xf29d0030 -+#define FSTV0910_P2_CAR2S2_8_BETA_E 0xf29d000f -+ -+/*P2_PLROOT2*/ -+#define RSTV0910_P2_PLROOT2 0xf2ac -+#define FSTV0910_P2_PLHAUTO_DISPLH 0xf2ac0040 -+#define FSTV0910_P2_PLHAUTO_FASTMODE 0xf2ac0020 -+#define FSTV0910_P2_PLHAUTO_ENABLE 0xf2ac0010 -+#define FSTV0910_P2_PLSCRAMB_MODE 0xf2ac000c -+#define FSTV0910_P2_PLSCRAMB_ROOT2 0xf2ac0003 -+ -+/*P2_PLROOT1*/ -+#define RSTV0910_P2_PLROOT1 0xf2ad -+#define FSTV0910_P2_PLSCRAMB_ROOT1 0xf2ad00ff -+ -+/*P2_PLROOT0*/ -+#define RSTV0910_P2_PLROOT0 0xf2ae -+#define FSTV0910_P2_PLSCRAMB_ROOT0 0xf2ae00ff -+ -+/*P2_MODCODLST7*/ -+#define RSTV0910_P2_MODCODLST7 0xf2b7 -+#define FSTV0910_P2_MODCOD_NNOSFILTER 0xf2b70080 -+#define FSTV0910_P2_MODCODLST_NOSTYPE 0xf2b70040 -+#define FSTV0910_P2_DIS_8PSK_9_10 0xf2b70030 -+#define FSTV0910_P2_DIS_8P_8_9 0xf2b7000f -+ -+/*P2_MODCODLST8*/ -+#define RSTV0910_P2_MODCODLST8 0xf2b8 -+#define FSTV0910_P2_DIS_8P_5_6 0xf2b800f0 -+#define FSTV0910_P2_DIS_8P_3_4 0xf2b8000f -+ -+/*P2_MODCODLST9*/ -+#define RSTV0910_P2_MODCODLST9 0xf2b9 -+#define FSTV0910_P2_DIS_8P_2_3 0xf2b900f0 -+#define FSTV0910_P2_DIS_8P_3_5 0xf2b9000f -+ -+/*P2_MODCODLSTA*/ -+#define RSTV0910_P2_MODCODLSTA 0xf2ba -+#define FSTV0910_P2_NOSFILTER_LIMITE 0xf2ba0080 -+#define FSTV0910_P2_NOSFILTER_MODE 0xf2ba0040 -+#define FSTV0910_P2_DIS_QPSK_9_10 0xf2ba0030 -+#define FSTV0910_P2_DIS_QP_8_9 0xf2ba000f -+ -+/*P2_MODCODLSTB*/ -+#define RSTV0910_P2_MODCODLSTB 0xf2bb -+#define FSTV0910_P2_DIS_QP_5_6 0xf2bb00f0 -+#define FSTV0910_P2_DIS_QP_4_5 0xf2bb000f -+ -+/*P2_MODCODLSTC*/ -+#define RSTV0910_P2_MODCODLSTC 0xf2bc -+#define FSTV0910_P2_DIS_QP_3_4 0xf2bc00f0 -+#define FSTV0910_P2_DIS_QP_2_3 0xf2bc000f -+ -+/*P2_MODCODLSTD*/ -+#define RSTV0910_P2_MODCODLSTD 0xf2bd -+#define FSTV0910_P2_DIS_QPSK_3_5 0xf2bd00f0 -+#define FSTV0910_P2_DIS_QPSK_1_2 0xf2bd000f -+ -+/*P2_GAUSSR0*/ -+#define RSTV0910_P2_GAUSSR0 0xf2c0 -+#define FSTV0910_P2_EN_CCIMODE 0xf2c00080 -+#define FSTV0910_P2_R0_GAUSSIEN 0xf2c0007f -+ -+/*P2_CCIR0*/ -+#define RSTV0910_P2_CCIR0 0xf2c1 -+#define FSTV0910_P2_CCIDETECT_PLHONLY 0xf2c10080 -+#define FSTV0910_P2_R0_CCI 0xf2c1007f -+ -+/*P2_CCIQUANT*/ -+#define RSTV0910_P2_CCIQUANT 0xf2c2 -+#define FSTV0910_P2_CCI_BETA 0xf2c200e0 -+#define FSTV0910_P2_CCI_QUANT 0xf2c2001f -+ -+/*P2_CCITHRES*/ -+#define RSTV0910_P2_CCITHRES 0xf2c3 -+#define FSTV0910_P2_CCI_THRESHOLD 0xf2c300ff -+ -+/*P2_CCIACC*/ -+#define RSTV0910_P2_CCIACC 0xf2c4 -+#define FSTV0910_P2_CCI_VALUE 0xf2c400ff -+ -+/*P2_DSTATUS4*/ -+#define RSTV0910_P2_DSTATUS4 0xf2c5 -+#define FSTV0910_P2_RAINFADE_DETECT 0xf2c50080 -+#define FSTV0910_P2_NOTHRES2_FAIL 0xf2c50040 -+#define FSTV0910_P2_NOTHRES1_FAIL 0xf2c50020 -+#define FSTV0910_P2_PILOT_FAILDETECT 0xf2c50010 -+#define FSTV0910_P2_HIER_DETECT 0xf2c50008 -+#define FSTV0910_P2_DMDPROG_ERROR 0xf2c50004 -+#define FSTV0910_P2_CSTENV_DETECT 0xf2c50002 -+#define FSTV0910_P2_DETECTION_TRIAX 0xf2c50001 -+ -+/*P2_DMDRESCFG*/ -+#define RSTV0910_P2_DMDRESCFG 0xf2c6 -+#define FSTV0910_P2_DMDRES_RESET 0xf2c60080 -+#define FSTV0910_P2_DMDRES_NOISESQR 0xf2c60010 -+#define FSTV0910_P2_DMDRES_STRALL 0xf2c60008 -+#define FSTV0910_P2_DMDRES_NEWONLY 0xf2c60004 -+#define FSTV0910_P2_DMDRES_NOSTORE 0xf2c60002 -+#define FSTV0910_P2_DMDRES_AGC2MEM 0xf2c60001 -+ -+/*P2_DMDRESADR*/ -+#define RSTV0910_P2_DMDRESADR 0xf2c7 -+#define FSTV0910_P2_SUSP_PREDCANAL 0xf2c70080 -+#define FSTV0910_P2_DMDRES_VALIDCFR 0xf2c70040 -+#define FSTV0910_P2_DMDRES_MEMFULL 0xf2c70030 -+#define FSTV0910_P2_DMDRES_RESNBR 0xf2c7000f -+ -+/*P2_DMDRESDATA7*/ -+#define RSTV0910_P2_DMDRESDATA7 0xf2c8 -+#define FSTV0910_P2_DMDRES_DATA7 0xf2c800ff -+ -+/*P2_DMDRESDATA6*/ -+#define RSTV0910_P2_DMDRESDATA6 0xf2c9 -+#define FSTV0910_P2_DMDRES_DATA6 0xf2c900ff -+ -+/*P2_DMDRESDATA5*/ -+#define RSTV0910_P2_DMDRESDATA5 0xf2ca -+#define FSTV0910_P2_DMDRES_DATA5 0xf2ca00ff -+ -+/*P2_DMDRESDATA4*/ -+#define RSTV0910_P2_DMDRESDATA4 0xf2cb -+#define FSTV0910_P2_DMDRES_DATA4 0xf2cb00ff -+ -+/*P2_DMDRESDATA3*/ -+#define RSTV0910_P2_DMDRESDATA3 0xf2cc -+#define FSTV0910_P2_DMDRES_DATA3 0xf2cc00ff -+ -+/*P2_DMDRESDATA2*/ -+#define RSTV0910_P2_DMDRESDATA2 0xf2cd -+#define FSTV0910_P2_DMDRES_DATA2 0xf2cd00ff -+ -+/*P2_DMDRESDATA1*/ -+#define RSTV0910_P2_DMDRESDATA1 0xf2ce -+#define FSTV0910_P2_DMDRES_DATA1 0xf2ce00ff -+ -+/*P2_DMDRESDATA0*/ -+#define RSTV0910_P2_DMDRESDATA0 0xf2cf -+#define FSTV0910_P2_DMDRES_DATA0 0xf2cf00ff -+ -+/*P2_FFEI1*/ -+#define RSTV0910_P2_FFEI1 0xf2d0 -+#define FSTV0910_P2_FFE_ACCI1 0xf2d001ff -+ -+/*P2_FFEQ1*/ -+#define RSTV0910_P2_FFEQ1 0xf2d1 -+#define FSTV0910_P2_FFE_ACCQ1 0xf2d101ff -+ -+/*P2_FFEI2*/ -+#define RSTV0910_P2_FFEI2 0xf2d2 -+#define FSTV0910_P2_FFE_ACCI2 0xf2d201ff -+ -+/*P2_FFEQ2*/ -+#define RSTV0910_P2_FFEQ2 0xf2d3 -+#define FSTV0910_P2_FFE_ACCQ2 0xf2d301ff -+ -+/*P2_FFEI3*/ -+#define RSTV0910_P2_FFEI3 0xf2d4 -+#define FSTV0910_P2_FFE_ACCI3 0xf2d401ff -+ -+/*P2_FFEQ3*/ -+#define RSTV0910_P2_FFEQ3 0xf2d5 -+#define FSTV0910_P2_FFE_ACCQ3 0xf2d501ff -+ -+/*P2_FFEI4*/ -+#define RSTV0910_P2_FFEI4 0xf2d6 -+#define FSTV0910_P2_FFE_ACCI4 0xf2d601ff -+ -+/*P2_FFEQ4*/ -+#define RSTV0910_P2_FFEQ4 0xf2d7 -+#define FSTV0910_P2_FFE_ACCQ4 0xf2d701ff -+ -+/*P2_FFECFG*/ -+#define RSTV0910_P2_FFECFG 0xf2d8 -+#define FSTV0910_P2_EQUALFFE_ON 0xf2d80040 -+#define FSTV0910_P2_EQUAL_USEDSYMB 0xf2d80030 -+#define FSTV0910_P2_MU_EQUALFFE 0xf2d80007 -+ -+/*P2_TNRCFG2*/ -+#define RSTV0910_P2_TNRCFG2 0xf2e1 -+#define FSTV0910_P2_TUN_IQSWAP 0xf2e10080 -+#define FSTV0910_P2_STB6110_STEP2MHZ 0xf2e10040 -+#define FSTV0910_P2_STB6120_DBLI2C 0xf2e10020 -+#define FSTV0910_P2_TUNER_WIDEBAND 0xf2e10010 -+#define FSTV0910_P2_TUNER_OBSPAGE 0xf2e10008 -+#define FSTV0910_P2_DIS_BWCALC 0xf2e10004 -+#define FSTV0910_P2_SHORT_WAITSTATES 0xf2e10002 -+#define FSTV0910_P2_DIS_2BWAGC1 0xf2e10001 -+ -+/*P2_SMAPCOEF7*/ -+#define RSTV0910_P2_SMAPCOEF7 0xf300 -+#define FSTV0910_P2_DIS_QSCALE 0xf3000080 -+#define FSTV0910_P2_SMAPCOEF_Q_LLR12 0xf300017f -+ -+/*P2_SMAPCOEF6*/ -+#define RSTV0910_P2_SMAPCOEF6 0xf301 -+#define FSTV0910_P2_DIS_AGC2SCALE 0xf3010080 -+#define FSTV0910_P2_DIS_16IQMULT 0xf3010040 -+#define FSTV0910_P2_OLD_16APSK47 0xf3010020 -+#define FSTV0910_P2_OLD_16APSK12 0xf3010010 -+#define FSTV0910_P2_DIS_NEWSCALE 0xf3010008 -+#define FSTV0910_P2_ADJ_8PSKLLR1 0xf3010004 -+#define FSTV0910_P2_OLD_8PSKLLR1 0xf3010002 -+#define FSTV0910_P2_DIS_AB8PSK 0xf3010001 -+ -+/*P2_SMAPCOEF5*/ -+#define RSTV0910_P2_SMAPCOEF5 0xf302 -+#define FSTV0910_P2_DIS_8SCALE 0xf3020080 -+#define FSTV0910_P2_SMAPCOEF_8P_LLR23 0xf302017f -+ -+/*P2_NOSTHRES1*/ -+#define RSTV0910_P2_NOSTHRES1 0xf309 -+#define FSTV0910_P2_NOS_THRESHOLD1 0xf30900ff -+ -+/*P2_NOSTHRES2*/ -+#define RSTV0910_P2_NOSTHRES2 0xf30a -+#define FSTV0910_P2_NOS_THRESHOLD2 0xf30a00ff -+ -+/*P2_NOSDIFF1*/ -+#define RSTV0910_P2_NOSDIFF1 0xf30b -+#define FSTV0910_P2_NOSTHRES1_DIFF 0xf30b00ff -+ -+/*P2_RAINFADE*/ -+#define RSTV0910_P2_RAINFADE 0xf30c -+#define FSTV0910_P2_NOSTHRES_DATAT 0xf30c0080 -+#define FSTV0910_P2_RAINFADE_CNLIMIT 0xf30c0070 -+#define FSTV0910_P2_RAINFADE_TIMEOUT 0xf30c0007 -+ -+/*P2_NOSRAMCFG*/ -+#define RSTV0910_P2_NOSRAMCFG 0xf30d -+#define FSTV0910_P2_NOSRAM_DVBS2DATA 0xf30d0080 -+#define FSTV0910_P2_NOSRAM_QUADRAT 0xf30d0040 -+#define FSTV0910_P2_NOSRAM_ACTIVATION 0xf30d0030 -+#define FSTV0910_P2_NOSRAM_CNRONLY 0xf30d0008 -+#define FSTV0910_P2_NOSRAM_LGNCNR1 0xf30d0007 -+ -+/*P2_NOSRAMPOS*/ -+#define RSTV0910_P2_NOSRAMPOS 0xf30e -+#define FSTV0910_P2_NOSRAM_LGNCNR0 0xf30e00f0 -+#define FSTV0910_P2_NOSRAM_VALIDE 0xf30e0004 -+#define FSTV0910_P2_NOSRAM_CNRVAL1 0xf30e0003 -+ -+/*P2_NOSRAMVAL*/ -+#define RSTV0910_P2_NOSRAMVAL 0xf30f -+#define FSTV0910_P2_NOSRAM_CNRVAL0 0xf30f00ff -+ -+/*P2_DMDPLHSTAT*/ -+#define RSTV0910_P2_DMDPLHSTAT 0xf320 -+#define FSTV0910_P2_PLH_STATISTIC 0xf32000ff -+ -+/*P2_LOCKTIME3*/ -+#define RSTV0910_P2_LOCKTIME3 0xf322 -+#define FSTV0910_P2_DEMOD_LOCKTIME3 0xf32200ff -+ -+/*P2_LOCKTIME2*/ -+#define RSTV0910_P2_LOCKTIME2 0xf323 -+#define FSTV0910_P2_DEMOD_LOCKTIME2 0xf32300ff -+ -+/*P2_LOCKTIME1*/ -+#define RSTV0910_P2_LOCKTIME1 0xf324 -+#define FSTV0910_P2_DEMOD_LOCKTIME1 0xf32400ff -+ -+/*P2_LOCKTIME0*/ -+#define RSTV0910_P2_LOCKTIME0 0xf325 -+#define FSTV0910_P2_DEMOD_LOCKTIME0 0xf32500ff -+ -+/*P2_VITSCALE*/ -+#define RSTV0910_P2_VITSCALE 0xf332 -+#define FSTV0910_P2_NVTH_NOSRANGE 0xf3320080 -+#define FSTV0910_P2_VERROR_MAXMODE 0xf3320040 -+#define FSTV0910_P2_KDIV_MODE 0xf3320030 -+#define FSTV0910_P2_NSLOWSN_LOCKED 0xf3320008 -+#define FSTV0910_P2_DELOCK_PRFLOSS 0xf3320004 -+#define FSTV0910_P2_DIS_RSFLOCK 0xf3320002 -+ -+/*P2_FECM*/ -+#define RSTV0910_P2_FECM 0xf333 -+#define FSTV0910_P2_DSS_DVB 0xf3330080 -+#define FSTV0910_P2_DEMOD_BYPASS 0xf3330040 -+#define FSTV0910_P2_CMP_SLOWMODE 0xf3330020 -+#define FSTV0910_P2_DSS_SRCH 0xf3330010 -+#define FSTV0910_P2_DIFF_MODEVIT 0xf3330004 -+#define FSTV0910_P2_SYNCVIT 0xf3330002 -+#define FSTV0910_P2_IQINV 0xf3330001 -+ -+/*P2_VTH12*/ -+#define RSTV0910_P2_VTH12 0xf334 -+#define FSTV0910_P2_VTH12 0xf33400ff -+ -+/*P2_VTH23*/ -+#define RSTV0910_P2_VTH23 0xf335 -+#define FSTV0910_P2_VTH23 0xf33500ff -+ -+/*P2_VTH34*/ -+#define RSTV0910_P2_VTH34 0xf336 -+#define FSTV0910_P2_VTH34 0xf33600ff -+ -+/*P2_VTH56*/ -+#define RSTV0910_P2_VTH56 0xf337 -+#define FSTV0910_P2_VTH56 0xf33700ff -+ -+/*P2_VTH67*/ -+#define RSTV0910_P2_VTH67 0xf338 -+#define FSTV0910_P2_VTH67 0xf33800ff -+ -+/*P2_VTH78*/ -+#define RSTV0910_P2_VTH78 0xf339 -+#define FSTV0910_P2_VTH78 0xf33900ff -+ -+/*P2_VITCURPUN*/ -+#define RSTV0910_P2_VITCURPUN 0xf33a -+#define FSTV0910_P2_CYCLESLIP_VIT 0xf33a0080 -+#define FSTV0910_P2_VIT_ROTA180 0xf33a0040 -+#define FSTV0910_P2_VIT_ROTA90 0xf33a0020 -+#define FSTV0910_P2_VIT_CURPUN 0xf33a001f -+ -+/*P2_VERROR*/ -+#define RSTV0910_P2_VERROR 0xf33b -+#define FSTV0910_P2_REGERR_VIT 0xf33b00ff -+ -+/*P2_PRVIT*/ -+#define RSTV0910_P2_PRVIT 0xf33c -+#define FSTV0910_P2_DIS_VTHLOCK 0xf33c0040 -+#define FSTV0910_P2_E7_8VIT 0xf33c0020 -+#define FSTV0910_P2_E6_7VIT 0xf33c0010 -+#define FSTV0910_P2_E5_6VIT 0xf33c0008 -+#define FSTV0910_P2_E3_4VIT 0xf33c0004 -+#define FSTV0910_P2_E2_3VIT 0xf33c0002 -+#define FSTV0910_P2_E1_2VIT 0xf33c0001 -+ -+/*P2_VAVSRVIT*/ -+#define RSTV0910_P2_VAVSRVIT 0xf33d -+#define FSTV0910_P2_AMVIT 0xf33d0080 -+#define FSTV0910_P2_FROZENVIT 0xf33d0040 -+#define FSTV0910_P2_SNVIT 0xf33d0030 -+#define FSTV0910_P2_TOVVIT 0xf33d000c -+#define FSTV0910_P2_HYPVIT 0xf33d0003 -+ -+/*P2_VSTATUSVIT*/ -+#define RSTV0910_P2_VSTATUSVIT 0xf33e -+#define FSTV0910_P2_VITERBI_ON 0xf33e0080 -+#define FSTV0910_P2_END_LOOPVIT 0xf33e0040 -+#define FSTV0910_P2_VITERBI_DEPRF 0xf33e0020 -+#define FSTV0910_P2_PRFVIT 0xf33e0010 -+#define FSTV0910_P2_LOCKEDVIT 0xf33e0008 -+#define FSTV0910_P2_VITERBI_DELOCK 0xf33e0004 -+#define FSTV0910_P2_VIT_DEMODSEL 0xf33e0002 -+#define FSTV0910_P2_VITERBI_COMPOUT 0xf33e0001 -+ -+/*P2_VTHINUSE*/ -+#define RSTV0910_P2_VTHINUSE 0xf33f -+#define FSTV0910_P2_VIT_INUSE 0xf33f00ff -+ -+/*P2_KDIV12*/ -+#define RSTV0910_P2_KDIV12 0xf340 -+#define FSTV0910_P2_KDIV12_MANUAL 0xf3400080 -+#define FSTV0910_P2_K_DIVIDER_12 0xf340007f -+ -+/*P2_KDIV23*/ -+#define RSTV0910_P2_KDIV23 0xf341 -+#define FSTV0910_P2_KDIV23_MANUAL 0xf3410080 -+#define FSTV0910_P2_K_DIVIDER_23 0xf341007f -+ -+/*P2_KDIV34*/ -+#define RSTV0910_P2_KDIV34 0xf342 -+#define FSTV0910_P2_KDIV34_MANUAL 0xf3420080 -+#define FSTV0910_P2_K_DIVIDER_34 0xf342007f -+ -+/*P2_KDIV56*/ -+#define RSTV0910_P2_KDIV56 0xf343 -+#define FSTV0910_P2_KDIV56_MANUAL 0xf3430080 -+#define FSTV0910_P2_K_DIVIDER_56 0xf343007f -+ -+/*P2_KDIV67*/ -+#define RSTV0910_P2_KDIV67 0xf344 -+#define FSTV0910_P2_KDIV67_MANUAL 0xf3440080 -+#define FSTV0910_P2_K_DIVIDER_67 0xf344007f -+ -+/*P2_KDIV78*/ -+#define RSTV0910_P2_KDIV78 0xf345 -+#define FSTV0910_P2_KDIV78_MANUAL 0xf3450080 -+#define FSTV0910_P2_K_DIVIDER_78 0xf345007f -+ -+/*P2_PDELCTRL0*/ -+#define RSTV0910_P2_PDELCTRL0 0xf34f -+#define FSTV0910_P2_ISIOBS_MODE 0xf34f0030 -+#define FSTV0910_P2_PDELDIS_BITWISE 0xf34f0004 -+ -+/*P2_PDELCTRL1*/ -+#define RSTV0910_P2_PDELCTRL1 0xf350 -+#define FSTV0910_P2_INV_MISMASK 0xf3500080 -+#define FSTV0910_P2_FORCE_ACCEPTED 0xf3500040 -+#define FSTV0910_P2_FILTER_EN 0xf3500020 -+#define FSTV0910_P2_FORCE_PKTDELINUSE 0xf3500010 -+#define FSTV0910_P2_HYSTEN 0xf3500008 -+#define FSTV0910_P2_HYSTSWRST 0xf3500004 -+#define FSTV0910_P2_EN_MIS00 0xf3500002 -+#define FSTV0910_P2_ALGOSWRST 0xf3500001 -+ -+/*P2_PDELCTRL2*/ -+#define RSTV0910_P2_PDELCTRL2 0xf351 -+#define FSTV0910_P2_FORCE_CONTINUOUS 0xf3510080 -+#define FSTV0910_P2_RESET_UPKO_COUNT 0xf3510040 -+#define FSTV0910_P2_USER_PKTDELIN_NB 0xf3510020 -+#define FSTV0910_P2_DATA_UNBBSCRAMBLED 0xf3510008 -+#define FSTV0910_P2_FORCE_LONGPKT 0xf3510004 -+#define FSTV0910_P2_FRAME_MODE 0xf3510002 -+ -+/*P2_HYSTTHRESH*/ -+#define RSTV0910_P2_HYSTTHRESH 0xf354 -+#define FSTV0910_P2_DELIN_LOCKTHRES 0xf35400f0 -+#define FSTV0910_P2_DELIN_UNLOCKTHRES 0xf354000f -+ -+/*P2_ISIENTRY*/ -+#define RSTV0910_P2_ISIENTRY 0xf35e -+#define FSTV0910_P2_ISI_ENTRY 0xf35e00ff -+ -+/*P2_ISIBITENA*/ -+#define RSTV0910_P2_ISIBITENA 0xf35f -+#define FSTV0910_P2_ISI_BIT_EN 0xf35f00ff -+ -+/*P2_MATSTR1*/ -+#define RSTV0910_P2_MATSTR1 0xf360 -+#define FSTV0910_P2_MATYPE_CURRENT1 0xf36000ff -+ -+/*P2_MATSTR0*/ -+#define RSTV0910_P2_MATSTR0 0xf361 -+#define FSTV0910_P2_MATYPE_CURRENT0 0xf36100ff -+ -+/*P2_UPLSTR1*/ -+#define RSTV0910_P2_UPLSTR1 0xf362 -+#define FSTV0910_P2_UPL_CURRENT1 0xf36200ff -+ -+/*P2_UPLSTR0*/ -+#define RSTV0910_P2_UPLSTR0 0xf363 -+#define FSTV0910_P2_UPL_CURRENT0 0xf36300ff -+ -+/*P2_DFLSTR1*/ -+#define RSTV0910_P2_DFLSTR1 0xf364 -+#define FSTV0910_P2_DFL_CURRENT1 0xf36400ff -+ -+/*P2_DFLSTR0*/ -+#define RSTV0910_P2_DFLSTR0 0xf365 -+#define FSTV0910_P2_DFL_CURRENT0 0xf36500ff -+ -+/*P2_SYNCSTR*/ -+#define RSTV0910_P2_SYNCSTR 0xf366 -+#define FSTV0910_P2_SYNC_CURRENT 0xf36600ff -+ -+/*P2_SYNCDSTR1*/ -+#define RSTV0910_P2_SYNCDSTR1 0xf367 -+#define FSTV0910_P2_SYNCD_CURRENT1 0xf36700ff -+ -+/*P2_SYNCDSTR0*/ -+#define RSTV0910_P2_SYNCDSTR0 0xf368 -+#define FSTV0910_P2_SYNCD_CURRENT0 0xf36800ff -+ -+/*P2_PDELSTATUS1*/ -+#define RSTV0910_P2_PDELSTATUS1 0xf369 -+#define FSTV0910_P2_PKTDELIN_DELOCK 0xf3690080 -+#define FSTV0910_P2_SYNCDUPDFL_BADDFL 0xf3690040 -+#define FSTV0910_P2_CONTINUOUS_STREAM 0xf3690020 -+#define FSTV0910_P2_UNACCEPTED_STREAM 0xf3690010 -+#define FSTV0910_P2_BCH_ERROR_FLAG 0xf3690008 -+#define FSTV0910_P2_BBHCRCKO 0xf3690004 -+#define FSTV0910_P2_PKTDELIN_LOCK 0xf3690002 -+#define FSTV0910_P2_FIRST_LOCK 0xf3690001 -+ -+/*P2_PDELSTATUS2*/ -+#define RSTV0910_P2_PDELSTATUS2 0xf36a -+#define FSTV0910_P2_PKTDEL_DEMODSEL 0xf36a0080 -+#define FSTV0910_P2_FRAME_MODCOD 0xf36a007c -+#define FSTV0910_P2_FRAME_TYPE 0xf36a0003 -+ -+/*P2_BBFCRCKO1*/ -+#define RSTV0910_P2_BBFCRCKO1 0xf36b -+#define FSTV0910_P2_BBHCRC_KOCNT1 0xf36b00ff -+ -+/*P2_BBFCRCKO0*/ -+#define RSTV0910_P2_BBFCRCKO0 0xf36c -+#define FSTV0910_P2_BBHCRC_KOCNT0 0xf36c00ff -+ -+/*P2_UPCRCKO1*/ -+#define RSTV0910_P2_UPCRCKO1 0xf36d -+#define FSTV0910_P2_PKTCRC_KOCNT1 0xf36d00ff -+ -+/*P2_UPCRCKO0*/ -+#define RSTV0910_P2_UPCRCKO0 0xf36e -+#define FSTV0910_P2_PKTCRC_KOCNT0 0xf36e00ff -+ -+/*P2_PDELCTRL3*/ -+#define RSTV0910_P2_PDELCTRL3 0xf36f -+#define FSTV0910_P2_PKTDEL_CONTFAIL 0xf36f0080 -+#define FSTV0910_P2_PKTDEL_ENLONGPKT 0xf36f0040 -+#define FSTV0910_P2_NOFIFO_BCHERR 0xf36f0020 -+#define FSTV0910_P2_PKTDELIN_DELACMERR 0xf36f0010 -+#define FSTV0910_P2_SATURATE_BBPKTKO 0xf36f0004 -+#define FSTV0910_P2_PKTDEL_BCHERRCONT 0xf36f0002 -+#define FSTV0910_P2_ETHERNET_DISFCS 0xf36f0001 -+ -+/*P2_TSSTATEM*/ -+#define RSTV0910_P2_TSSTATEM 0xf370 -+#define FSTV0910_P2_TSDIL_ON 0xf3700080 -+#define FSTV0910_P2_TSSKIPRS_ON 0xf3700040 -+#define FSTV0910_P2_TSRS_ON 0xf3700020 -+#define FSTV0910_P2_TSDESCRAMB_ON 0xf3700010 -+#define FSTV0910_P2_TSFRAME_MODE 0xf3700008 -+#define FSTV0910_P2_TS_DISABLE 0xf3700004 -+#define FSTV0910_P2_TSACM_MODE 0xf3700002 -+#define FSTV0910_P2_TSOUT_NOSYNC 0xf3700001 -+ -+/*P2_TSCFGH*/ -+#define RSTV0910_P2_TSCFGH 0xf372 -+#define FSTV0910_P2_TSFIFO_DVBCI 0xf3720080 -+#define FSTV0910_P2_TSFIFO_SERIAL 0xf3720040 -+#define FSTV0910_P2_TSFIFO_TEIUPDATE 0xf3720020 -+#define FSTV0910_P2_TSFIFO_DUTY50 0xf3720010 -+#define FSTV0910_P2_TSFIFO_HSGNLOUT 0xf3720008 -+#define FSTV0910_P2_TSFIFO_ERRMODE 0xf3720006 -+#define FSTV0910_P2_RST_HWARE 0xf3720001 -+ -+/*P2_TSCFGM*/ -+#define RSTV0910_P2_TSCFGM 0xf373 -+#define FSTV0910_P2_TSFIFO_MANSPEED 0xf37300c0 -+#define FSTV0910_P2_TSFIFO_PERMDATA 0xf3730020 -+#define FSTV0910_P2_TSFIFO_NONEWSGNL 0xf3730010 -+#define FSTV0910_P2_NPD_SPECDVBS2 0xf3730004 -+#define FSTV0910_P2_TSFIFO_DPUNACTIVE 0xf3730002 -+#define FSTV0910_P2_TSFIFO_INVDATA 0xf3730001 -+ -+/*P2_TSCFGL*/ -+#define RSTV0910_P2_TSCFGL 0xf374 -+#define FSTV0910_P2_TSFIFO_BCLKDEL1CK 0xf37400c0 -+#define FSTV0910_P2_BCHERROR_MODE 0xf3740030 -+#define FSTV0910_P2_TSFIFO_NSGNL2DATA 0xf3740008 -+#define FSTV0910_P2_TSFIFO_EMBINDVB 0xf3740004 -+#define FSTV0910_P2_TSFIFO_BITSPEED 0xf3740003 -+ -+/*P2_TSINSDELH*/ -+#define RSTV0910_P2_TSINSDELH 0xf376 -+#define FSTV0910_P2_TSDEL_SYNCBYTE 0xf3760080 -+#define FSTV0910_P2_TSDEL_XXHEADER 0xf3760040 -+#define FSTV0910_P2_TSDEL_BBHEADER 0xf3760020 -+#define FSTV0910_P2_TSDEL_DATAFIELD 0xf3760010 -+#define FSTV0910_P2_TSINSDEL_ISCR 0xf3760008 -+#define FSTV0910_P2_TSINSDEL_NPD 0xf3760004 -+#define FSTV0910_P2_TSINSDEL_RSPARITY 0xf3760002 -+#define FSTV0910_P2_TSINSDEL_CRC8 0xf3760001 -+ -+/*P2_TSDIVN*/ -+#define RSTV0910_P2_TSDIVN 0xf379 -+#define FSTV0910_P2_TSFIFO_SPEEDMODE 0xf37900c0 -+#define FSTV0910_P2_BYTE_OVERSAMPLING 0xf3790038 -+#define FSTV0910_P2_TSFIFO_RISEOK 0xf3790007 -+ -+/*P2_TSCFG4*/ -+#define RSTV0910_P2_TSCFG4 0xf37a -+#define FSTV0910_P2_TSFIFO_TSSPEEDMODE 0xf37a00c0 -+#define FSTV0910_P2_TSFIFO_HIERSEL 0xf37a0020 -+#define FSTV0910_P2_TSFIFO_SPECTOKEN 0xf37a0010 -+#define FSTV0910_P2_TSFIFO_MAXMODE 0xf37a0008 -+#define FSTV0910_P2_TSFIFO_FRFORCEPKT 0xf37a0004 -+#define FSTV0910_P2_EXT_FECSPYIN 0xf37a0002 -+#define FSTV0910_P2_TSFIFO_DELSPEEDUP 0xf37a0001 -+ -+/*P2_TSSPEED*/ -+#define RSTV0910_P2_TSSPEED 0xf380 -+#define FSTV0910_P2_TSFIFO_OUTSPEED 0xf38000ff -+ -+/*P2_TSSTATUS*/ -+#define RSTV0910_P2_TSSTATUS 0xf381 -+#define FSTV0910_P2_TSFIFO_LINEOK 0xf3810080 -+#define FSTV0910_P2_TSFIFO_ERROR 0xf3810040 -+#define FSTV0910_P2_TSFIFO_DATA7 0xf3810020 -+#define FSTV0910_P2_TSFIFO_NOSYNC 0xf3810010 -+#define FSTV0910_P2_ISCR_INITIALIZED 0xf3810008 -+#define FSTV0910_P2_TSREGUL_ERROR 0xf3810004 -+#define FSTV0910_P2_SOFFIFO_UNREGUL 0xf3810002 -+#define FSTV0910_P2_DIL_READY 0xf3810001 -+ -+/*P2_TSSTATUS2*/ -+#define RSTV0910_P2_TSSTATUS2 0xf382 -+#define FSTV0910_P2_TSFIFO_DEMODSEL 0xf3820080 -+#define FSTV0910_P2_TSFIFOSPEED_STORE 0xf3820040 -+#define FSTV0910_P2_DILXX_RESET 0xf3820020 -+#define FSTV0910_P2_TSSPEED_IMPOSSIBLE 0xf3820010 -+#define FSTV0910_P2_TSFIFO_LINENOK 0xf3820008 -+#define FSTV0910_P2_TSFIFO_MUXSTREAM 0xf3820004 -+#define FSTV0910_P2_SCRAMBDETECT 0xf3820002 -+#define FSTV0910_P2_ULDTV67_FALSELOCK 0xf3820001 -+ -+/*P2_TSBITRATE1*/ -+#define RSTV0910_P2_TSBITRATE1 0xf383 -+#define FSTV0910_P2_TSFIFO_BITRATE1 0xf38300ff -+ -+/*P2_TSBITRATE0*/ -+#define RSTV0910_P2_TSBITRATE0 0xf384 -+#define FSTV0910_P2_TSFIFO_BITRATE0 0xf38400ff -+ -+/*P2_ERRCTRL1*/ -+#define RSTV0910_P2_ERRCTRL1 0xf398 -+#define FSTV0910_P2_ERR_SOURCE1 0xf39800f0 -+#define FSTV0910_P2_NUM_EVENT1 0xf3980007 -+ -+/*P2_ERRCNT12*/ -+#define RSTV0910_P2_ERRCNT12 0xf399 -+#define FSTV0910_P2_ERRCNT1_OLDVALUE 0xf3990080 -+#define FSTV0910_P2_ERR_CNT12 0xf399007f -+ -+/*P2_ERRCNT11*/ -+#define RSTV0910_P2_ERRCNT11 0xf39a -+#define FSTV0910_P2_ERR_CNT11 0xf39a00ff -+ -+/*P2_ERRCNT10*/ -+#define RSTV0910_P2_ERRCNT10 0xf39b -+#define FSTV0910_P2_ERR_CNT10 0xf39b00ff -+ -+/*P2_ERRCTRL2*/ -+#define RSTV0910_P2_ERRCTRL2 0xf39c -+#define FSTV0910_P2_ERR_SOURCE2 0xf39c00f0 -+#define FSTV0910_P2_NUM_EVENT2 0xf39c0007 -+ -+/*P2_ERRCNT22*/ -+#define RSTV0910_P2_ERRCNT22 0xf39d -+#define FSTV0910_P2_ERRCNT2_OLDVALUE 0xf39d0080 -+#define FSTV0910_P2_ERR_CNT22 0xf39d007f -+ -+/*P2_ERRCNT21*/ -+#define RSTV0910_P2_ERRCNT21 0xf39e -+#define FSTV0910_P2_ERR_CNT21 0xf39e00ff -+ -+/*P2_ERRCNT20*/ -+#define RSTV0910_P2_ERRCNT20 0xf39f -+#define FSTV0910_P2_ERR_CNT20 0xf39f00ff -+ -+/*P2_FECSPY*/ -+#define RSTV0910_P2_FECSPY 0xf3a0 -+#define FSTV0910_P2_SPY_ENABLE 0xf3a00080 -+#define FSTV0910_P2_NO_SYNCBYTE 0xf3a00040 -+#define FSTV0910_P2_SERIAL_MODE 0xf3a00020 -+#define FSTV0910_P2_UNUSUAL_PACKET 0xf3a00010 -+#define FSTV0910_P2_BERMETER_DATAMODE 0xf3a0000c -+#define FSTV0910_P2_BERMETER_LMODE 0xf3a00002 -+#define FSTV0910_P2_BERMETER_RESET 0xf3a00001 -+ -+/*P2_FSPYCFG*/ -+#define RSTV0910_P2_FSPYCFG 0xf3a1 -+#define FSTV0910_P2_FECSPY_INPUT 0xf3a100c0 -+#define FSTV0910_P2_RST_ON_ERROR 0xf3a10020 -+#define FSTV0910_P2_ONE_SHOT 0xf3a10010 -+#define FSTV0910_P2_I2C_MODE 0xf3a1000c -+#define FSTV0910_P2_SPY_HYSTERESIS 0xf3a10003 -+ -+/*P2_FSPYDATA*/ -+#define RSTV0910_P2_FSPYDATA 0xf3a2 -+#define FSTV0910_P2_SPY_STUFFING 0xf3a20080 -+#define FSTV0910_P2_NOERROR_PKTJITTER 0xf3a20040 -+#define FSTV0910_P2_SPY_CNULLPKT 0xf3a20020 -+#define FSTV0910_P2_SPY_OUTDATA_MODE 0xf3a2001f -+ -+/*P2_FSPYOUT*/ -+#define RSTV0910_P2_FSPYOUT 0xf3a3 -+#define FSTV0910_P2_FSPY_DIRECT 0xf3a30080 -+#define FSTV0910_P2_SPY_OUTDATA_BUS 0xf3a30038 -+#define FSTV0910_P2_STUFF_MODE 0xf3a30007 -+ -+/*P2_FSTATUS*/ -+#define RSTV0910_P2_FSTATUS 0xf3a4 -+#define FSTV0910_P2_SPY_ENDSIM 0xf3a40080 -+#define FSTV0910_P2_VALID_SIM 0xf3a40040 -+#define FSTV0910_P2_FOUND_SIGNAL 0xf3a40020 -+#define FSTV0910_P2_DSS_SYNCBYTE 0xf3a40010 -+#define FSTV0910_P2_RESULT_STATE 0xf3a4000f -+ -+/*P2_FBERCPT4*/ -+#define RSTV0910_P2_FBERCPT4 0xf3a8 -+#define FSTV0910_P2_FBERMETER_CPT4 0xf3a800ff -+ -+/*P2_FBERCPT3*/ -+#define RSTV0910_P2_FBERCPT3 0xf3a9 -+#define FSTV0910_P2_FBERMETER_CPT3 0xf3a900ff -+ -+/*P2_FBERCPT2*/ -+#define RSTV0910_P2_FBERCPT2 0xf3aa -+#define FSTV0910_P2_FBERMETER_CPT2 0xf3aa00ff -+ -+/*P2_FBERCPT1*/ -+#define RSTV0910_P2_FBERCPT1 0xf3ab -+#define FSTV0910_P2_FBERMETER_CPT1 0xf3ab00ff -+ -+/*P2_FBERCPT0*/ -+#define RSTV0910_P2_FBERCPT0 0xf3ac -+#define FSTV0910_P2_FBERMETER_CPT0 0xf3ac00ff -+ -+/*P2_FBERERR2*/ -+#define RSTV0910_P2_FBERERR2 0xf3ad -+#define FSTV0910_P2_FBERMETER_ERR2 0xf3ad00ff -+ -+/*P2_FBERERR1*/ -+#define RSTV0910_P2_FBERERR1 0xf3ae -+#define FSTV0910_P2_FBERMETER_ERR1 0xf3ae00ff -+ -+/*P2_FBERERR0*/ -+#define RSTV0910_P2_FBERERR0 0xf3af -+#define FSTV0910_P2_FBERMETER_ERR0 0xf3af00ff -+ -+/*P2_FSPYBER*/ -+#define RSTV0910_P2_FSPYBER 0xf3b2 -+#define FSTV0910_P2_FSPYOBS_XORREAD 0xf3b20040 -+#define FSTV0910_P2_FSPYBER_OBSMODE 0xf3b20020 -+#define FSTV0910_P2_FSPYBER_SYNCBYTE 0xf3b20010 -+#define FSTV0910_P2_FSPYBER_UNSYNC 0xf3b20008 -+#define FSTV0910_P2_FSPYBER_CTIME 0xf3b20007 -+ -+/*P2_SFERROR*/ -+#define RSTV0910_P2_SFERROR 0xf3c1 -+#define FSTV0910_P2_SFEC_REGERR_VIT 0xf3c100ff -+ -+/*P2_SFECSTATUS*/ -+#define RSTV0910_P2_SFECSTATUS 0xf3c3 -+#define FSTV0910_P2_SFEC_ON 0xf3c30080 -+#define FSTV0910_P2_SFEC_OFF 0xf3c30040 -+#define FSTV0910_P2_LOCKEDSFEC 0xf3c30008 -+#define FSTV0910_P2_SFEC_DELOCK 0xf3c30004 -+#define FSTV0910_P2_SFEC_DEMODSEL 0xf3c30002 -+#define FSTV0910_P2_SFEC_OVFON 0xf3c30001 -+ -+/*P2_SFKDIV12*/ -+#define RSTV0910_P2_SFKDIV12 0xf3c4 -+#define FSTV0910_P2_SFECKDIV12_MAN 0xf3c40080 -+#define FSTV0910_P2_SFEC_K_DIVIDER_12 0xf3c4007f -+ -+/*P2_SFKDIV23*/ -+#define RSTV0910_P2_SFKDIV23 0xf3c5 -+#define FSTV0910_P2_SFECKDIV23_MAN 0xf3c50080 -+#define FSTV0910_P2_SFEC_K_DIVIDER_23 0xf3c5007f -+ -+/*P2_SFKDIV34*/ -+#define RSTV0910_P2_SFKDIV34 0xf3c6 -+#define FSTV0910_P2_SFECKDIV34_MAN 0xf3c60080 -+#define FSTV0910_P2_SFEC_K_DIVIDER_34 0xf3c6007f -+ -+/*P2_SFKDIV56*/ -+#define RSTV0910_P2_SFKDIV56 0xf3c7 -+#define FSTV0910_P2_SFECKDIV56_MAN 0xf3c70080 -+#define FSTV0910_P2_SFEC_K_DIVIDER_56 0xf3c7007f -+ -+/*P2_SFKDIV67*/ -+#define RSTV0910_P2_SFKDIV67 0xf3c8 -+#define FSTV0910_P2_SFECKDIV67_MAN 0xf3c80080 -+#define FSTV0910_P2_SFEC_K_DIVIDER_67 0xf3c8007f -+ -+/*P2_SFKDIV78*/ -+#define RSTV0910_P2_SFKDIV78 0xf3c9 -+#define FSTV0910_P2_SFECKDIV78_MAN 0xf3c90080 -+#define FSTV0910_P2_SFEC_K_DIVIDER_78 0xf3c9007f -+ -+/*P2_SFSTATUS*/ -+#define RSTV0910_P2_SFSTATUS 0xf3cc -+#define FSTV0910_P2_SFEC_LINEOK 0xf3cc0080 -+#define FSTV0910_P2_SFEC_ERROR 0xf3cc0040 -+#define FSTV0910_P2_SFEC_DATA7 0xf3cc0020 -+#define FSTV0910_P2_SFEC_PKTDNBRFAIL 0xf3cc0010 -+#define FSTV0910_P2_TSSFEC_DEMODSEL 0xf3cc0008 -+#define FSTV0910_P2_SFEC_NOSYNC 0xf3cc0004 -+#define FSTV0910_P2_SFEC_UNREGULA 0xf3cc0002 -+#define FSTV0910_P2_SFEC_READY 0xf3cc0001 -+ -+/*P2_SFDLYSET2*/ -+#define RSTV0910_P2_SFDLYSET2 0xf3d0 -+#define FSTV0910_P2_SFEC_OFFSET 0xf3d000c0 -+#define FSTV0910_P2_RST_SFEC 0xf3d00008 -+#define FSTV0910_P2_DILDLINE_ERROR 0xf3d00004 -+#define FSTV0910_P2_SFEC_DISABLE 0xf3d00002 -+#define FSTV0910_P2_SFEC_UNREGUL 0xf3d00001 -+ -+/*P2_SFERRCTRL*/ -+#define RSTV0910_P2_SFERRCTRL 0xf3d8 -+#define FSTV0910_P2_SFEC_ERR_SOURCE 0xf3d800f0 -+#define FSTV0910_P2_SFEC_NUM_EVENT 0xf3d80007 -+ -+/*P2_SFERRCNT2*/ -+#define RSTV0910_P2_SFERRCNT2 0xf3d9 -+#define FSTV0910_P2_SFERRC_OLDVALUE 0xf3d90080 -+#define FSTV0910_P2_SFEC_ERR_CNT2 0xf3d9007f -+ -+/*P2_SFERRCNT1*/ -+#define RSTV0910_P2_SFERRCNT1 0xf3da -+#define FSTV0910_P2_SFEC_ERR_CNT1 0xf3da00ff -+ -+/*P2_SFERRCNT0*/ -+#define RSTV0910_P2_SFERRCNT0 0xf3db -+#define FSTV0910_P2_SFEC_ERR_CNT0 0xf3db00ff -+ -+/*P1_IQCONST*/ -+#define RSTV0910_P1_IQCONST 0xf400 -+#define FSTV0910_P1_CONSTEL_SELECT 0xf4000060 -+#define FSTV0910_P1_IQSYMB_SEL 0xf400001f -+ -+/*P1_NOSCFG*/ -+#define RSTV0910_P1_NOSCFG 0xf401 -+#define FSTV0910_P1_DIS_ACMRATIO 0xf4010080 -+#define FSTV0910_P1_NOSIN_EGALSEL 0xf4010040 -+#define FSTV0910_P1_DUMMYPL_NOSDATA 0xf4010020 -+#define FSTV0910_P1_NOSPLH_BETA 0xf4010018 -+#define FSTV0910_P1_NOSDATA_BETA 0xf4010007 -+ -+/*P1_ISYMB*/ -+#define RSTV0910_P1_ISYMB 0xf402 -+#define FSTV0910_P1_I_SYMBOL 0xf40201ff -+ -+/*P1_QSYMB*/ -+#define RSTV0910_P1_QSYMB 0xf403 -+#define FSTV0910_P1_Q_SYMBOL 0xf40301ff -+ -+/*P1_AGC1CFG*/ -+#define RSTV0910_P1_AGC1CFG 0xf404 -+#define FSTV0910_P1_DC_FROZEN 0xf4040080 -+#define FSTV0910_P1_DC_CORRECT 0xf4040040 -+#define FSTV0910_P1_AMM_FROZEN 0xf4040020 -+#define FSTV0910_P1_AMM_CORRECT 0xf4040010 -+#define FSTV0910_P1_QUAD_FROZEN 0xf4040008 -+#define FSTV0910_P1_QUAD_CORRECT 0xf4040004 -+#define FSTV0910_P1_DCCOMP_SLOW 0xf4040002 -+#define FSTV0910_P1_IQMISM_SLOW 0xf4040001 -+ -+/*P1_AGC1CN*/ -+#define RSTV0910_P1_AGC1CN 0xf406 -+#define FSTV0910_P1_AGC1_LOCKED 0xf4060080 -+#define FSTV0910_P1_AGC1_OVERFLOW 0xf4060040 -+#define FSTV0910_P1_AGC1_NOSLOWLK 0xf4060020 -+#define FSTV0910_P1_AGC1_MINPOWER 0xf4060010 -+#define FSTV0910_P1_AGCOUT_FAST 0xf4060008 -+#define FSTV0910_P1_AGCIQ_BETA 0xf4060007 -+ -+/*P1_AGC1REF*/ -+#define RSTV0910_P1_AGC1REF 0xf407 -+#define FSTV0910_P1_AGCIQ_REF 0xf40700ff -+ -+/*P1_IDCCOMP*/ -+#define RSTV0910_P1_IDCCOMP 0xf408 -+#define FSTV0910_P1_IAVERAGE_ADJ 0xf40801ff -+ -+/*P1_QDCCOMP*/ -+#define RSTV0910_P1_QDCCOMP 0xf409 -+#define FSTV0910_P1_QAVERAGE_ADJ 0xf40901ff -+ -+/*P1_POWERI*/ -+#define RSTV0910_P1_POWERI 0xf40a -+#define FSTV0910_P1_POWER_I 0xf40a00ff -+ -+/*P1_POWERQ*/ -+#define RSTV0910_P1_POWERQ 0xf40b -+#define FSTV0910_P1_POWER_Q 0xf40b00ff -+ -+/*P1_AGC1AMM*/ -+#define RSTV0910_P1_AGC1AMM 0xf40c -+#define FSTV0910_P1_AMM_VALUE 0xf40c00ff -+ -+/*P1_AGC1QUAD*/ -+#define RSTV0910_P1_AGC1QUAD 0xf40d -+#define FSTV0910_P1_QUAD_VALUE 0xf40d01ff -+ -+/*P1_AGCIQIN1*/ -+#define RSTV0910_P1_AGCIQIN1 0xf40e -+#define FSTV0910_P1_AGCIQ_VALUE1 0xf40e00ff -+ -+/*P1_AGCIQIN0*/ -+#define RSTV0910_P1_AGCIQIN0 0xf40f -+#define FSTV0910_P1_AGCIQ_VALUE0 0xf40f00ff -+ -+/*P1_DEMOD*/ -+#define RSTV0910_P1_DEMOD 0xf410 -+#define FSTV0910_P1_MANUALS2_ROLLOFF 0xf4100080 -+#define FSTV0910_P1_SPECINV_CONTROL 0xf4100030 -+#define FSTV0910_P1_MANUALSX_ROLLOFF 0xf4100004 -+#define FSTV0910_P1_ROLLOFF_CONTROL 0xf4100003 -+ -+/*P1_DMDMODCOD*/ -+#define RSTV0910_P1_DMDMODCOD 0xf411 -+#define FSTV0910_P1_MANUAL_MODCOD 0xf4110080 -+#define FSTV0910_P1_DEMOD_MODCOD 0xf411007c -+#define FSTV0910_P1_DEMOD_TYPE 0xf4110003 -+ -+/*P1_DSTATUS*/ -+#define RSTV0910_P1_DSTATUS 0xf412 -+#define FSTV0910_P1_CAR_LOCK 0xf4120080 -+#define FSTV0910_P1_TMGLOCK_QUALITY 0xf4120060 -+#define FSTV0910_P1_SDVBS1_ENABLE 0xf4120010 -+#define FSTV0910_P1_LOCK_DEFINITIF 0xf4120008 -+#define FSTV0910_P1_TIMING_IS_LOCKED 0xf4120004 -+#define FSTV0910_P1_DEMOD_SYSCFG 0xf4120002 -+#define FSTV0910_P1_OVADC_DETECT 0xf4120001 -+ -+/*P1_DSTATUS2*/ -+#define RSTV0910_P1_DSTATUS2 0xf413 -+#define FSTV0910_P1_DEMOD_DELOCK 0xf4130080 -+#define FSTV0910_P1_DEMOD_TIMEOUT 0xf4130040 -+#define FSTV0910_P1_MODCODRQ_SYNCTAG 0xf4130020 -+#define FSTV0910_P1_POLYPH_SATEVENT 0xf4130010 -+#define FSTV0910_P1_AGC1_NOSIGNALACK 0xf4130008 -+#define FSTV0910_P1_AGC2_OVERFLOW 0xf4130004 -+#define FSTV0910_P1_CFR_OVERFLOW 0xf4130002 -+#define FSTV0910_P1_GAMMA_OVERUNDER 0xf4130001 -+ -+/*P1_DMDCFGMD*/ -+#define RSTV0910_P1_DMDCFGMD 0xf414 -+#define FSTV0910_P1_DVBS2_ENABLE 0xf4140080 -+#define FSTV0910_P1_DVBS1_ENABLE 0xf4140040 -+#define FSTV0910_P1_SCAN_ENABLE 0xf4140010 -+#define FSTV0910_P1_CFR_AUTOSCAN 0xf4140008 -+#define FSTV0910_P1_NOFORCE_RELOCK 0xf4140004 -+#define FSTV0910_P1_TUN_RNG 0xf4140003 -+ -+/*P1_DMDCFG2*/ -+#define RSTV0910_P1_DMDCFG2 0xf415 -+#define FSTV0910_P1_AGC1_WAITLOCK 0xf4150080 -+#define FSTV0910_P1_S1S2_SEQUENTIAL 0xf4150040 -+#define FSTV0910_P1_BLINDPEA_MODE 0xf4150020 -+#define FSTV0910_P1_INFINITE_RELOCK 0xf4150010 -+#define FSTV0910_P1_BWOFFSET_COLDWARM 0xf4150008 -+#define FSTV0910_P1_TMGLOCK_NSCANSTOP 0xf4150004 -+#define FSTV0910_P1_COARSE_LK3MODE 0xf4150002 -+#define FSTV0910_P1_COARSE_LK2MODE 0xf4150001 -+ -+/*P1_DMDISTATE*/ -+#define RSTV0910_P1_DMDISTATE 0xf416 -+#define FSTV0910_P1_I2C_NORESETDMODE 0xf4160080 -+#define FSTV0910_P1_FORCE_ETAPED 0xf4160040 -+#define FSTV0910_P1_SDMDRST_DIRCLK 0xf4160020 -+#define FSTV0910_P1_I2C_DEMOD_MODE 0xf416001f -+ -+/*P1_DMDT0M*/ -+#define RSTV0910_P1_DMDT0M 0xf417 -+#define FSTV0910_P1_DMDT0_MIN 0xf41700ff -+ -+/*P1_DMDSTATE*/ -+#define RSTV0910_P1_DMDSTATE 0xf41b -+#define FSTV0910_P1_DEMOD_LOCKED 0xf41b0080 -+#define FSTV0910_P1_HEADER_MODE 0xf41b0060 -+#define FSTV0910_P1_DEMOD_MODE 0xf41b001f -+ -+/*P1_DMDFLYW*/ -+#define RSTV0910_P1_DMDFLYW 0xf41c -+#define FSTV0910_P1_I2C_IRQVAL 0xf41c00f0 -+#define FSTV0910_P1_FLYWHEEL_CPT 0xf41c000f -+ -+/*P1_DSTATUS3*/ -+#define RSTV0910_P1_DSTATUS3 0xf41d -+#define FSTV0910_P1_CFR_ZIGZAG 0xf41d0080 -+#define FSTV0910_P1_DEMOD_CFGMODE 0xf41d0060 -+#define FSTV0910_P1_GAMMA_LOWBAUDRATE 0xf41d0010 -+#define FSTV0910_P1_RELOCK_MODE 0xf41d0008 -+#define FSTV0910_P1_DEMOD_FAIL 0xf41d0004 -+#define FSTV0910_P1_ETAPE1A_DVBXMEM 0xf41d0003 -+ -+/*P1_DMDCFG3*/ -+#define RSTV0910_P1_DMDCFG3 0xf41e -+#define FSTV0910_P1_DVBS1_TMGWAIT 0xf41e0080 -+#define FSTV0910_P1_NO_BWCENTERING 0xf41e0040 -+#define FSTV0910_P1_INV_SEQSRCH 0xf41e0020 -+#define FSTV0910_P1_DIS_SFRUPLOW_TRK 0xf41e0010 -+#define FSTV0910_P1_NOSTOP_FIFOFULL 0xf41e0008 -+#define FSTV0910_P1_LOCKTIME_MODE 0xf41e0007 -+ -+/*P1_DMDCFG4*/ -+#define RSTV0910_P1_DMDCFG4 0xf41f -+#define FSTV0910_P1_DIS_VITLOCK 0xf41f0080 -+#define FSTV0910_P1_S1S2TOUT_FAST 0xf41f0040 -+#define FSTV0910_P1_DEMOD_FASTLOCK 0xf41f0020 -+#define FSTV0910_P1_S1HIER_ENABLE 0xf41f0010 -+#define FSTV0910_P1_TUNER_NRELAUNCH 0xf41f0008 -+#define FSTV0910_P1_DIS_CLKENABLE 0xf41f0004 -+#define FSTV0910_P1_DIS_HDRDIVLOCK 0xf41f0002 -+#define FSTV0910_P1_NO_TNRWBINIT 0xf41f0001 -+ -+/*P1_CORRELMANT*/ -+#define RSTV0910_P1_CORRELMANT 0xf420 -+#define FSTV0910_P1_CORREL_MANT 0xf42000ff -+ -+/*P1_CORRELABS*/ -+#define RSTV0910_P1_CORRELABS 0xf421 -+#define FSTV0910_P1_CORREL_ABS 0xf42100ff -+ -+/*P1_CORRELEXP*/ -+#define RSTV0910_P1_CORRELEXP 0xf422 -+#define FSTV0910_P1_CORREL_ABSEXP 0xf42200f0 -+#define FSTV0910_P1_CORREL_EXP 0xf422000f -+ -+/*P1_PLHMODCOD*/ -+#define RSTV0910_P1_PLHMODCOD 0xf424 -+#define FSTV0910_P1_SPECINV_DEMOD 0xf4240080 -+#define FSTV0910_P1_PLH_MODCOD 0xf424007c -+#define FSTV0910_P1_PLH_TYPE 0xf4240003 -+ -+/*P1_DMDREG*/ -+#define RSTV0910_P1_DMDREG 0xf425 -+#define FSTV0910_P1_EXTPSK_MODE 0xf4250080 -+#define FSTV0910_P1_HIER_SHORTFRAME 0xf4250002 -+#define FSTV0910_P1_DECIM_PLFRAMES 0xf4250001 -+ -+/*P1_AGC2O*/ -+#define RSTV0910_P1_AGC2O 0xf42c -+#define FSTV0910_P1_CSTENV_MODE 0xf42c00c0 -+#define FSTV0910_P1_AGC2_LKSQRT 0xf42c0020 -+#define FSTV0910_P1_AGC2_LKMODE 0xf42c0010 -+#define FSTV0910_P1_AGC2_LKEQUA 0xf42c0008 -+#define FSTV0910_P1_AGC2_COEF 0xf42c0007 -+ -+/*P1_AGC2REF*/ -+#define RSTV0910_P1_AGC2REF 0xf42d -+#define FSTV0910_P1_AGC2_REF 0xf42d00ff -+ -+/*P1_AGC1ADJ*/ -+#define RSTV0910_P1_AGC1ADJ 0xf42e -+#define FSTV0910_P1_AGC1ADJ_MANUAL 0xf42e0080 -+#define FSTV0910_P1_AGC1_ADJUSTED 0xf42e007f -+ -+/*P1_AGC2I1*/ -+#define RSTV0910_P1_AGC2I1 0xf436 -+#define FSTV0910_P1_AGC2_INTEGRATOR1 0xf43600ff -+ -+/*P1_AGC2I0*/ -+#define RSTV0910_P1_AGC2I0 0xf437 -+#define FSTV0910_P1_AGC2_INTEGRATOR0 0xf43700ff -+ -+/*P1_CARCFG*/ -+#define RSTV0910_P1_CARCFG 0xf438 -+#define FSTV0910_P1_CFRUPLOW_AUTO 0xf4380080 -+#define FSTV0910_P1_CFRUPLOW_TEST 0xf4380040 -+#define FSTV0910_P1_WIDE_FREQDET 0xf4380020 -+#define FSTV0910_P1_CARHDR_NODIV8 0xf4380010 -+#define FSTV0910_P1_I2C_ROTA 0xf4380008 -+#define FSTV0910_P1_ROTAON 0xf4380004 -+#define FSTV0910_P1_PH_DET_ALGO 0xf4380003 -+ -+/*P1_ACLC*/ -+#define RSTV0910_P1_ACLC 0xf439 -+#define FSTV0910_P1_CARS1_ANOSAUTO 0xf4390040 -+#define FSTV0910_P1_CAR_ALPHA_MANT 0xf4390030 -+#define FSTV0910_P1_CAR_ALPHA_EXP 0xf439000f -+ -+/*P1_BCLC*/ -+#define RSTV0910_P1_BCLC 0xf43a -+#define FSTV0910_P1_CARS1_BNOSAUTO 0xf43a0040 -+#define FSTV0910_P1_CAR_BETA_MANT 0xf43a0030 -+#define FSTV0910_P1_CAR_BETA_EXP 0xf43a000f -+ -+/*P1_CARFREQ*/ -+#define RSTV0910_P1_CARFREQ 0xf43d -+#define FSTV0910_P1_KC_COARSE_EXP 0xf43d00f0 -+#define FSTV0910_P1_BETA_FREQ 0xf43d000f -+ -+/*P1_CARHDR*/ -+#define RSTV0910_P1_CARHDR 0xf43e -+#define FSTV0910_P1_K_FREQ_HDR 0xf43e00ff -+ -+/*P1_LDT*/ -+#define RSTV0910_P1_LDT 0xf43f -+#define FSTV0910_P1_CARLOCK_THRES 0xf43f01ff -+ -+/*P1_LDT2*/ -+#define RSTV0910_P1_LDT2 0xf440 -+#define FSTV0910_P1_CARLOCK_THRES2 0xf44001ff -+ -+/*P1_CFRICFG*/ -+#define RSTV0910_P1_CFRICFG 0xf441 -+#define FSTV0910_P1_CFRINIT_UNVALRNG 0xf4410080 -+#define FSTV0910_P1_CFRINIT_LUNVALCPT 0xf4410040 -+#define FSTV0910_P1_CFRINIT_ABORTDBL 0xf4410020 -+#define FSTV0910_P1_CFRINIT_ABORTPRED 0xf4410010 -+#define FSTV0910_P1_CFRINIT_UNVALSKIP 0xf4410008 -+#define FSTV0910_P1_CFRINIT_CSTINC 0xf4410004 -+#define FSTV0910_P1_CFRIROLL_GARDER 0xf4410002 -+#define FSTV0910_P1_NEG_CFRSTEP 0xf4410001 -+ -+/*P1_CFRUP1*/ -+#define RSTV0910_P1_CFRUP1 0xf442 -+#define FSTV0910_P1_CFR_UP1 0xf44201ff -+ -+/*P1_CFRUP0*/ -+#define RSTV0910_P1_CFRUP0 0xf443 -+#define FSTV0910_P1_CFR_UP0 0xf44300ff -+ -+/*P1_CFRIBASE1*/ -+#define RSTV0910_P1_CFRIBASE1 0xf444 -+#define FSTV0910_P1_CFRINIT_BASE1 0xf44400ff -+ -+/*P1_CFRIBASE0*/ -+#define RSTV0910_P1_CFRIBASE0 0xf445 -+#define FSTV0910_P1_CFRINIT_BASE0 0xf44500ff -+ -+/*P1_CFRLOW1*/ -+#define RSTV0910_P1_CFRLOW1 0xf446 -+#define FSTV0910_P1_CFR_LOW1 0xf44601ff -+ -+/*P1_CFRLOW0*/ -+#define RSTV0910_P1_CFRLOW0 0xf447 -+#define FSTV0910_P1_CFR_LOW0 0xf44700ff -+ -+/*P1_CFRINIT1*/ -+#define RSTV0910_P1_CFRINIT1 0xf448 -+#define FSTV0910_P1_CFR_INIT1 0xf44801ff -+ -+/*P1_CFRINIT0*/ -+#define RSTV0910_P1_CFRINIT0 0xf449 -+#define FSTV0910_P1_CFR_INIT0 0xf44900ff -+ -+/*P1_CFRINC1*/ -+#define RSTV0910_P1_CFRINC1 0xf44a -+#define FSTV0910_P1_MANUAL_CFRINC 0xf44a0080 -+#define FSTV0910_P1_CFR_INC1 0xf44a003f -+ -+/*P1_CFRINC0*/ -+#define RSTV0910_P1_CFRINC0 0xf44b -+#define FSTV0910_P1_CFR_INC0 0xf44b00ff -+ -+/*P1_CFR2*/ -+#define RSTV0910_P1_CFR2 0xf44c -+#define FSTV0910_P1_CAR_FREQ2 0xf44c01ff -+ -+/*P1_CFR1*/ -+#define RSTV0910_P1_CFR1 0xf44d -+#define FSTV0910_P1_CAR_FREQ1 0xf44d00ff -+ -+/*P1_CFR0*/ -+#define RSTV0910_P1_CFR0 0xf44e -+#define FSTV0910_P1_CAR_FREQ0 0xf44e00ff -+ -+/*P1_LDI*/ -+#define RSTV0910_P1_LDI 0xf44f -+#define FSTV0910_P1_LOCK_DET_INTEGR 0xf44f01ff -+ -+/*P1_TMGCFG*/ -+#define RSTV0910_P1_TMGCFG 0xf450 -+#define FSTV0910_P1_TMGLOCK_BETA 0xf45000c0 -+#define FSTV0910_P1_DO_TIMING_CORR 0xf4500010 -+#define FSTV0910_P1_MANUAL_SCAN 0xf450000c -+#define FSTV0910_P1_TMG_MINFREQ 0xf4500003 -+ -+/*P1_RTC*/ -+#define RSTV0910_P1_RTC 0xf451 -+#define FSTV0910_P1_TMGALPHA_EXP 0xf45100f0 -+#define FSTV0910_P1_TMGBETA_EXP 0xf451000f -+ -+/*P1_RTCS2*/ -+#define RSTV0910_P1_RTCS2 0xf452 -+#define FSTV0910_P1_TMGALPHAS2_EXP 0xf45200f0 -+#define FSTV0910_P1_TMGBETAS2_EXP 0xf452000f -+ -+/*P1_TMGTHRISE*/ -+#define RSTV0910_P1_TMGTHRISE 0xf453 -+#define FSTV0910_P1_TMGLOCK_THRISE 0xf45300ff -+ -+/*P1_TMGTHFALL*/ -+#define RSTV0910_P1_TMGTHFALL 0xf454 -+#define FSTV0910_P1_TMGLOCK_THFALL 0xf45400ff -+ -+/*P1_SFRUPRATIO*/ -+#define RSTV0910_P1_SFRUPRATIO 0xf455 -+#define FSTV0910_P1_SFR_UPRATIO 0xf45500ff -+ -+/*P1_SFRLOWRATIO*/ -+#define RSTV0910_P1_SFRLOWRATIO 0xf456 -+#define FSTV0910_P1_SFR_LOWRATIO 0xf45600ff -+ -+/*P1_KTTMG*/ -+#define RSTV0910_P1_KTTMG 0xf457 -+#define FSTV0910_P1_KT_TMG_EXP 0xf45700f0 -+ -+/*P1_KREFTMG*/ -+#define RSTV0910_P1_KREFTMG 0xf458 -+#define FSTV0910_P1_KREF_TMG 0xf45800ff -+ -+/*P1_SFRSTEP*/ -+#define RSTV0910_P1_SFRSTEP 0xf459 -+#define FSTV0910_P1_SFR_SCANSTEP 0xf45900f0 -+#define FSTV0910_P1_SFR_CENTERSTEP 0xf459000f -+ -+/*P1_TMGCFG2*/ -+#define RSTV0910_P1_TMGCFG2 0xf45a -+#define FSTV0910_P1_KREFTMG2_DECMODE 0xf45a00c0 -+#define FSTV0910_P1_DIS_AUTOSAMP 0xf45a0008 -+#define FSTV0910_P1_SCANINIT_QUART 0xf45a0004 -+#define FSTV0910_P1_NOTMG_DVBS1DERAT 0xf45a0002 -+#define FSTV0910_P1_SFRRATIO_FINE 0xf45a0001 -+ -+/*P1_KREFTMG2*/ -+#define RSTV0910_P1_KREFTMG2 0xf45b -+#define FSTV0910_P1_KREF_TMG2 0xf45b00ff -+ -+/*P1_TMGCFG3*/ -+#define RSTV0910_P1_TMGCFG3 0xf45d -+#define FSTV0910_P1_CFRINC_MODE 0xf45d0070 -+#define FSTV0910_P1_CONT_TMGCENTER 0xf45d0008 -+#define FSTV0910_P1_AUTO_GUP 0xf45d0004 -+#define FSTV0910_P1_AUTO_GLOW 0xf45d0002 -+#define FSTV0910_P1_SFRVAL_MINMODE 0xf45d0001 -+ -+/*P1_SFRINIT1*/ -+#define RSTV0910_P1_SFRINIT1 0xf45e -+#define FSTV0910_P1_SFR_INIT1 0xf45e00ff -+ -+/*P1_SFRINIT0*/ -+#define RSTV0910_P1_SFRINIT0 0xf45f -+#define FSTV0910_P1_SFR_INIT0 0xf45f00ff -+ -+/*P1_SFRUP1*/ -+#define RSTV0910_P1_SFRUP1 0xf460 -+#define FSTV0910_P1_SYMB_FREQ_UP1 0xf46000ff -+ -+/*P1_SFRUP0*/ -+#define RSTV0910_P1_SFRUP0 0xf461 -+#define FSTV0910_P1_SYMB_FREQ_UP0 0xf46100ff -+ -+/*P1_SFRLOW1*/ -+#define RSTV0910_P1_SFRLOW1 0xf462 -+#define FSTV0910_P1_SYMB_FREQ_LOW1 0xf46200ff -+ -+/*P1_SFRLOW0*/ -+#define RSTV0910_P1_SFRLOW0 0xf463 -+#define FSTV0910_P1_SYMB_FREQ_LOW0 0xf46300ff -+ -+/*P1_SFR3*/ -+#define RSTV0910_P1_SFR3 0xf464 -+#define FSTV0910_P1_SYMB_FREQ3 0xf46400ff -+ -+/*P1_SFR2*/ -+#define RSTV0910_P1_SFR2 0xf465 -+#define FSTV0910_P1_SYMB_FREQ2 0xf46500ff -+ -+/*P1_SFR1*/ -+#define RSTV0910_P1_SFR1 0xf466 -+#define FSTV0910_P1_SYMB_FREQ1 0xf46600ff -+ -+/*P1_SFR0*/ -+#define RSTV0910_P1_SFR0 0xf467 -+#define FSTV0910_P1_SYMB_FREQ0 0xf46700ff -+ -+/*P1_TMGREG2*/ -+#define RSTV0910_P1_TMGREG2 0xf468 -+#define FSTV0910_P1_TMGREG2 0xf46800ff -+ -+/*P1_TMGREG1*/ -+#define RSTV0910_P1_TMGREG1 0xf469 -+#define FSTV0910_P1_TMGREG1 0xf46900ff -+ -+/*P1_TMGREG0*/ -+#define RSTV0910_P1_TMGREG0 0xf46a -+#define FSTV0910_P1_TMGREG0 0xf46a00ff -+ -+/*P1_TMGLOCK1*/ -+#define RSTV0910_P1_TMGLOCK1 0xf46b -+#define FSTV0910_P1_TMGLOCK_LEVEL1 0xf46b01ff -+ -+/*P1_TMGLOCK0*/ -+#define RSTV0910_P1_TMGLOCK0 0xf46c -+#define FSTV0910_P1_TMGLOCK_LEVEL0 0xf46c00ff -+ -+/*P1_TMGOBS*/ -+#define RSTV0910_P1_TMGOBS 0xf46d -+#define FSTV0910_P1_ROLLOFF_STATUS 0xf46d00c0 -+#define FSTV0910_P1_SCAN_SIGN 0xf46d0030 -+#define FSTV0910_P1_TMG_SCANNING 0xf46d0008 -+#define FSTV0910_P1_CHCENTERING_MODE 0xf46d0004 -+#define FSTV0910_P1_TMG_SCANFAIL 0xf46d0002 -+ -+/*P1_EQUALCFG*/ -+#define RSTV0910_P1_EQUALCFG 0xf46f -+#define FSTV0910_P1_NOTMG_NEGALWAIT 0xf46f0080 -+#define FSTV0910_P1_EQUAL_ON 0xf46f0040 -+#define FSTV0910_P1_SEL_EQUALCOR 0xf46f0038 -+#define FSTV0910_P1_MU_EQUALDFE 0xf46f0007 -+ -+/*P1_EQUAI1*/ -+#define RSTV0910_P1_EQUAI1 0xf470 -+#define FSTV0910_P1_EQUA_ACCI1 0xf47001ff -+ -+/*P1_EQUAQ1*/ -+#define RSTV0910_P1_EQUAQ1 0xf471 -+#define FSTV0910_P1_EQUA_ACCQ1 0xf47101ff -+ -+/*P1_EQUAI2*/ -+#define RSTV0910_P1_EQUAI2 0xf472 -+#define FSTV0910_P1_EQUA_ACCI2 0xf47201ff -+ -+/*P1_EQUAQ2*/ -+#define RSTV0910_P1_EQUAQ2 0xf473 -+#define FSTV0910_P1_EQUA_ACCQ2 0xf47301ff -+ -+/*P1_EQUAI3*/ -+#define RSTV0910_P1_EQUAI3 0xf474 -+#define FSTV0910_P1_EQUA_ACCI3 0xf47401ff -+ -+/*P1_EQUAQ3*/ -+#define RSTV0910_P1_EQUAQ3 0xf475 -+#define FSTV0910_P1_EQUA_ACCQ3 0xf47501ff -+ -+/*P1_EQUAI4*/ -+#define RSTV0910_P1_EQUAI4 0xf476 -+#define FSTV0910_P1_EQUA_ACCI4 0xf47601ff -+ -+/*P1_EQUAQ4*/ -+#define RSTV0910_P1_EQUAQ4 0xf477 -+#define FSTV0910_P1_EQUA_ACCQ4 0xf47701ff -+ -+/*P1_EQUAI5*/ -+#define RSTV0910_P1_EQUAI5 0xf478 -+#define FSTV0910_P1_EQUA_ACCI5 0xf47801ff -+ -+/*P1_EQUAQ5*/ -+#define RSTV0910_P1_EQUAQ5 0xf479 -+#define FSTV0910_P1_EQUA_ACCQ5 0xf47901ff -+ -+/*P1_EQUAI6*/ -+#define RSTV0910_P1_EQUAI6 0xf47a -+#define FSTV0910_P1_EQUA_ACCI6 0xf47a01ff -+ -+/*P1_EQUAQ6*/ -+#define RSTV0910_P1_EQUAQ6 0xf47b -+#define FSTV0910_P1_EQUA_ACCQ6 0xf47b01ff -+ -+/*P1_EQUAI7*/ -+#define RSTV0910_P1_EQUAI7 0xf47c -+#define FSTV0910_P1_EQUA_ACCI7 0xf47c01ff -+ -+/*P1_EQUAQ7*/ -+#define RSTV0910_P1_EQUAQ7 0xf47d -+#define FSTV0910_P1_EQUA_ACCQ7 0xf47d01ff -+ -+/*P1_EQUAI8*/ -+#define RSTV0910_P1_EQUAI8 0xf47e -+#define FSTV0910_P1_EQUA_ACCI8 0xf47e01ff -+ -+/*P1_EQUAQ8*/ -+#define RSTV0910_P1_EQUAQ8 0xf47f -+#define FSTV0910_P1_EQUA_ACCQ8 0xf47f01ff -+ -+/*P1_NNOSDATAT1*/ -+#define RSTV0910_P1_NNOSDATAT1 0xf480 -+#define FSTV0910_P1_NOSDATAT_NORMED1 0xf48000ff -+ -+/*P1_NNOSDATAT0*/ -+#define RSTV0910_P1_NNOSDATAT0 0xf481 -+#define FSTV0910_P1_NOSDATAT_NORMED0 0xf48100ff -+ -+/*P1_NNOSDATA1*/ -+#define RSTV0910_P1_NNOSDATA1 0xf482 -+#define FSTV0910_P1_NOSDATA_NORMED1 0xf48200ff -+ -+/*P1_NNOSDATA0*/ -+#define RSTV0910_P1_NNOSDATA0 0xf483 -+#define FSTV0910_P1_NOSDATA_NORMED0 0xf48300ff -+ -+/*P1_NNOSPLHT1*/ -+#define RSTV0910_P1_NNOSPLHT1 0xf484 -+#define FSTV0910_P1_NOSPLHT_NORMED1 0xf48400ff -+ -+/*P1_NNOSPLHT0*/ -+#define RSTV0910_P1_NNOSPLHT0 0xf485 -+#define FSTV0910_P1_NOSPLHT_NORMED0 0xf48500ff -+ -+/*P1_NNOSPLH1*/ -+#define RSTV0910_P1_NNOSPLH1 0xf486 -+#define FSTV0910_P1_NOSPLH_NORMED1 0xf48600ff -+ -+/*P1_NNOSPLH0*/ -+#define RSTV0910_P1_NNOSPLH0 0xf487 -+#define FSTV0910_P1_NOSPLH_NORMED0 0xf48700ff -+ -+/*P1_NOSDATAT1*/ -+#define RSTV0910_P1_NOSDATAT1 0xf488 -+#define FSTV0910_P1_NOSDATAT_UNNORMED1 0xf48800ff -+ -+/*P1_NOSDATAT0*/ -+#define RSTV0910_P1_NOSDATAT0 0xf489 -+#define FSTV0910_P1_NOSDATAT_UNNORMED0 0xf48900ff -+ -+/*P1_NNOSFRAME1*/ -+#define RSTV0910_P1_NNOSFRAME1 0xf48a -+#define FSTV0910_P1_NOSFRAME_NORMED1 0xf48a00ff -+ -+/*P1_NNOSFRAME0*/ -+#define RSTV0910_P1_NNOSFRAME0 0xf48b -+#define FSTV0910_P1_NOSFRAME_NORMED0 0xf48b00ff -+ -+/*P1_NNOSRAD1*/ -+#define RSTV0910_P1_NNOSRAD1 0xf48c -+#define FSTV0910_P1_NOSRADIAL_NORMED1 0xf48c00ff -+ -+/*P1_NNOSRAD0*/ -+#define RSTV0910_P1_NNOSRAD0 0xf48d -+#define FSTV0910_P1_NOSRADIAL_NORMED0 0xf48d00ff -+ -+/*P1_NOSCFGF1*/ -+#define RSTV0910_P1_NOSCFGF1 0xf48e -+#define FSTV0910_P1_LOWNOISE_MESURE 0xf48e0080 -+#define FSTV0910_P1_NOS_DELFRAME 0xf48e0040 -+#define FSTV0910_P1_NOSDATA_MODE 0xf48e0030 -+#define FSTV0910_P1_FRAMESEL_TYPESEL 0xf48e000c -+#define FSTV0910_P1_FRAMESEL_TYPE 0xf48e0003 -+ -+/*P1_CAR2CFG*/ -+#define RSTV0910_P1_CAR2CFG 0xf490 -+#define FSTV0910_P1_DESCRAMB_OFF 0xf4900080 -+#define FSTV0910_P1_EN_PHNOSRAM 0xf4900020 -+#define FSTV0910_P1_STOP_CFR2UPDATE 0xf4900010 -+#define FSTV0910_P1_STOP_NCO2UPDATE 0xf4900008 -+#define FSTV0910_P1_ROTA2ON 0xf4900004 -+#define FSTV0910_P1_PH_DET_ALGO2 0xf4900003 -+ -+/*P1_CFR2CFR1*/ -+#define RSTV0910_P1_CFR2CFR1 0xf491 -+#define FSTV0910_P1_CFR2_S2CONTROL 0xf49100c0 -+#define FSTV0910_P1_EN_S2CAR2CENTER 0xf4910020 -+#define FSTV0910_P1_BCHERRCFR2_MODE 0xf4910018 -+#define FSTV0910_P1_CFR2TOCFR1_BETA 0xf4910007 -+ -+/*P1_CAR3CFG*/ -+#define RSTV0910_P1_CAR3CFG 0xf492 -+#define FSTV0910_P1_CARRIER23_MODE 0xf49200c0 -+#define FSTV0910_P1_CAR3INTERM_DVBS1 0xf4920020 -+#define FSTV0910_P1_ABAMPLIF_MODE 0xf4920018 -+#define FSTV0910_P1_CARRIER3_ALPHA3DL 0xf4920007 -+ -+/*P1_CFR22*/ -+#define RSTV0910_P1_CFR22 0xf493 -+#define FSTV0910_P1_CAR2_FREQ2 0xf49301ff -+ -+/*P1_CFR21*/ -+#define RSTV0910_P1_CFR21 0xf494 -+#define FSTV0910_P1_CAR2_FREQ1 0xf49400ff -+ -+/*P1_CFR20*/ -+#define RSTV0910_P1_CFR20 0xf495 -+#define FSTV0910_P1_CAR2_FREQ0 0xf49500ff -+ -+/*P1_ACLC2S2Q*/ -+#define RSTV0910_P1_ACLC2S2Q 0xf497 -+#define FSTV0910_P1_ENAB_SPSKSYMB 0xf4970080 -+#define FSTV0910_P1_CAR2S2_QANOSAUTO 0xf4970040 -+#define FSTV0910_P1_CAR2S2_Q_ALPH_M 0xf4970030 -+#define FSTV0910_P1_CAR2S2_Q_ALPH_E 0xf497000f -+ -+/*P1_ACLC2S28*/ -+#define RSTV0910_P1_ACLC2S28 0xf498 -+#define FSTV0910_P1_OLDI3Q_MODE 0xf4980080 -+#define FSTV0910_P1_CAR2S2_8ANOSAUTO 0xf4980040 -+#define FSTV0910_P1_CAR2S2_8_ALPH_M 0xf4980030 -+#define FSTV0910_P1_CAR2S2_8_ALPH_E 0xf498000f -+ -+/*P1_ACLC2S216A*/ -+#define RSTV0910_P1_ACLC2S216A 0xf499 -+#define FSTV0910_P1_CAR2S2_16ANOSAUTO 0xf4990040 -+#define FSTV0910_P1_CAR2S2_16A_ALPH_M 0xf4990030 -+#define FSTV0910_P1_CAR2S2_16A_ALPH_E 0xf499000f -+ -+/*P1_ACLC2S232A*/ -+#define RSTV0910_P1_ACLC2S232A 0xf49a -+#define FSTV0910_P1_CAR2S2_32ANOSUATO 0xf49a0040 -+#define FSTV0910_P1_CAR2S2_32A_ALPH_M 0xf49a0030 -+#define FSTV0910_P1_CAR2S2_32A_ALPH_E 0xf49a000f -+ -+/*P1_BCLC2S2Q*/ -+#define RSTV0910_P1_BCLC2S2Q 0xf49c -+#define FSTV0910_P1_DVBS2S2Q_NIP 0xf49c0080 -+#define FSTV0910_P1_CAR2S2_QBNOSAUTO 0xf49c0040 -+#define FSTV0910_P1_CAR2S2_Q_BETA_M 0xf49c0030 -+#define FSTV0910_P1_CAR2S2_Q_BETA_E 0xf49c000f -+ -+/*P1_BCLC2S28*/ -+#define RSTV0910_P1_BCLC2S28 0xf49d -+#define FSTV0910_P1_DVBS2S28_NIP 0xf49d0080 -+#define FSTV0910_P1_CAR2S2_8BNOSAUTO 0xf49d0040 -+#define FSTV0910_P1_CAR2S2_8_BETA_M 0xf49d0030 -+#define FSTV0910_P1_CAR2S2_8_BETA_E 0xf49d000f -+ -+/*P1_PLROOT2*/ -+#define RSTV0910_P1_PLROOT2 0xf4ac -+#define FSTV0910_P1_PLHAUTO_DISPLH 0xf4ac0040 -+#define FSTV0910_P1_PLHAUTO_FASTMODE 0xf4ac0020 -+#define FSTV0910_P1_PLHAUTO_ENABLE 0xf4ac0010 -+#define FSTV0910_P1_PLSCRAMB_MODE 0xf4ac000c -+#define FSTV0910_P1_PLSCRAMB_ROOT2 0xf4ac0003 -+ -+/*P1_PLROOT1*/ -+#define RSTV0910_P1_PLROOT1 0xf4ad -+#define FSTV0910_P1_PLSCRAMB_ROOT1 0xf4ad00ff -+ -+/*P1_PLROOT0*/ -+#define RSTV0910_P1_PLROOT0 0xf4ae -+#define FSTV0910_P1_PLSCRAMB_ROOT0 0xf4ae00ff -+ -+/*P1_MODCODLST7*/ -+#define RSTV0910_P1_MODCODLST7 0xf4b7 -+#define FSTV0910_P1_MODCOD_NNOSFILTER 0xf4b70080 -+#define FSTV0910_P1_MODCODLST_NOSTYPE 0xf4b70040 -+#define FSTV0910_P1_DIS_8PSK_9_10 0xf4b70030 -+#define FSTV0910_P1_DIS_8P_8_9 0xf4b7000f -+ -+/*P1_MODCODLST8*/ -+#define RSTV0910_P1_MODCODLST8 0xf4b8 -+#define FSTV0910_P1_DIS_8P_5_6 0xf4b800f0 -+#define FSTV0910_P1_DIS_8P_3_4 0xf4b8000f -+ -+/*P1_MODCODLST9*/ -+#define RSTV0910_P1_MODCODLST9 0xf4b9 -+#define FSTV0910_P1_DIS_8P_2_3 0xf4b900f0 -+#define FSTV0910_P1_DIS_8P_3_5 0xf4b9000f -+ -+/*P1_MODCODLSTA*/ -+#define RSTV0910_P1_MODCODLSTA 0xf4ba -+#define FSTV0910_P1_NOSFILTER_LIMITE 0xf4ba0080 -+#define FSTV0910_P1_NOSFILTER_MODE 0xf4ba0040 -+#define FSTV0910_P1_DIS_QPSK_9_10 0xf4ba0030 -+#define FSTV0910_P1_DIS_QP_8_9 0xf4ba000f -+ -+/*P1_MODCODLSTB*/ -+#define RSTV0910_P1_MODCODLSTB 0xf4bb -+#define FSTV0910_P1_DIS_QP_5_6 0xf4bb00f0 -+#define FSTV0910_P1_DIS_QP_4_5 0xf4bb000f -+ -+/*P1_MODCODLSTC*/ -+#define RSTV0910_P1_MODCODLSTC 0xf4bc -+#define FSTV0910_P1_DIS_QP_3_4 0xf4bc00f0 -+#define FSTV0910_P1_DIS_QP_2_3 0xf4bc000f -+ -+/*P1_MODCODLSTD*/ -+#define RSTV0910_P1_MODCODLSTD 0xf4bd -+#define FSTV0910_P1_DIS_QPSK_3_5 0xf4bd00f0 -+#define FSTV0910_P1_DIS_QPSK_1_2 0xf4bd000f -+ -+/*P1_GAUSSR0*/ -+#define RSTV0910_P1_GAUSSR0 0xf4c0 -+#define FSTV0910_P1_EN_CCIMODE 0xf4c00080 -+#define FSTV0910_P1_R0_GAUSSIEN 0xf4c0007f -+ -+/*P1_CCIR0*/ -+#define RSTV0910_P1_CCIR0 0xf4c1 -+#define FSTV0910_P1_CCIDETECT_PLHONLY 0xf4c10080 -+#define FSTV0910_P1_R0_CCI 0xf4c1007f -+ -+/*P1_CCIQUANT*/ -+#define RSTV0910_P1_CCIQUANT 0xf4c2 -+#define FSTV0910_P1_CCI_BETA 0xf4c200e0 -+#define FSTV0910_P1_CCI_QUANT 0xf4c2001f -+ -+/*P1_CCITHRES*/ -+#define RSTV0910_P1_CCITHRES 0xf4c3 -+#define FSTV0910_P1_CCI_THRESHOLD 0xf4c300ff -+ -+/*P1_CCIACC*/ -+#define RSTV0910_P1_CCIACC 0xf4c4 -+#define FSTV0910_P1_CCI_VALUE 0xf4c400ff -+ -+/*P1_DSTATUS4*/ -+#define RSTV0910_P1_DSTATUS4 0xf4c5 -+#define FSTV0910_P1_RAINFADE_DETECT 0xf4c50080 -+#define FSTV0910_P1_NOTHRES2_FAIL 0xf4c50040 -+#define FSTV0910_P1_NOTHRES1_FAIL 0xf4c50020 -+#define FSTV0910_P1_PILOT_FAILDETECT 0xf4c50010 -+#define FSTV0910_P1_HIER_DETECT 0xf4c50008 -+#define FSTV0910_P1_DMDPROG_ERROR 0xf4c50004 -+#define FSTV0910_P1_CSTENV_DETECT 0xf4c50002 -+#define FSTV0910_P1_DETECTION_TRIAX 0xf4c50001 -+ -+/*P1_DMDRESCFG*/ -+#define RSTV0910_P1_DMDRESCFG 0xf4c6 -+#define FSTV0910_P1_DMDRES_RESET 0xf4c60080 -+#define FSTV0910_P1_DMDRES_NOISESQR 0xf4c60010 -+#define FSTV0910_P1_DMDRES_STRALL 0xf4c60008 -+#define FSTV0910_P1_DMDRES_NEWONLY 0xf4c60004 -+#define FSTV0910_P1_DMDRES_NOSTORE 0xf4c60002 -+#define FSTV0910_P1_DMDRES_AGC2MEM 0xf4c60001 -+ -+/*P1_DMDRESADR*/ -+#define RSTV0910_P1_DMDRESADR 0xf4c7 -+#define FSTV0910_P1_SUSP_PREDCANAL 0xf4c70080 -+#define FSTV0910_P1_DMDRES_VALIDCFR 0xf4c70040 -+#define FSTV0910_P1_DMDRES_MEMFULL 0xf4c70030 -+#define FSTV0910_P1_DMDRES_RESNBR 0xf4c7000f -+ -+/*P1_DMDRESDATA7*/ -+#define RSTV0910_P1_DMDRESDATA7 0xf4c8 -+#define FSTV0910_P1_DMDRES_DATA7 0xf4c800ff -+ -+/*P1_DMDRESDATA6*/ -+#define RSTV0910_P1_DMDRESDATA6 0xf4c9 -+#define FSTV0910_P1_DMDRES_DATA6 0xf4c900ff -+ -+/*P1_DMDRESDATA5*/ -+#define RSTV0910_P1_DMDRESDATA5 0xf4ca -+#define FSTV0910_P1_DMDRES_DATA5 0xf4ca00ff -+ -+/*P1_DMDRESDATA4*/ -+#define RSTV0910_P1_DMDRESDATA4 0xf4cb -+#define FSTV0910_P1_DMDRES_DATA4 0xf4cb00ff -+ -+/*P1_DMDRESDATA3*/ -+#define RSTV0910_P1_DMDRESDATA3 0xf4cc -+#define FSTV0910_P1_DMDRES_DATA3 0xf4cc00ff -+ -+/*P1_DMDRESDATA2*/ -+#define RSTV0910_P1_DMDRESDATA2 0xf4cd -+#define FSTV0910_P1_DMDRES_DATA2 0xf4cd00ff -+ -+/*P1_DMDRESDATA1*/ -+#define RSTV0910_P1_DMDRESDATA1 0xf4ce -+#define FSTV0910_P1_DMDRES_DATA1 0xf4ce00ff -+ -+/*P1_DMDRESDATA0*/ -+#define RSTV0910_P1_DMDRESDATA0 0xf4cf -+#define FSTV0910_P1_DMDRES_DATA0 0xf4cf00ff -+ -+/*P1_FFEI1*/ -+#define RSTV0910_P1_FFEI1 0xf4d0 -+#define FSTV0910_P1_FFE_ACCI1 0xf4d001ff -+ -+/*P1_FFEQ1*/ -+#define RSTV0910_P1_FFEQ1 0xf4d1 -+#define FSTV0910_P1_FFE_ACCQ1 0xf4d101ff -+ -+/*P1_FFEI2*/ -+#define RSTV0910_P1_FFEI2 0xf4d2 -+#define FSTV0910_P1_FFE_ACCI2 0xf4d201ff -+ -+/*P1_FFEQ2*/ -+#define RSTV0910_P1_FFEQ2 0xf4d3 -+#define FSTV0910_P1_FFE_ACCQ2 0xf4d301ff -+ -+/*P1_FFEI3*/ -+#define RSTV0910_P1_FFEI3 0xf4d4 -+#define FSTV0910_P1_FFE_ACCI3 0xf4d401ff -+ -+/*P1_FFEQ3*/ -+#define RSTV0910_P1_FFEQ3 0xf4d5 -+#define FSTV0910_P1_FFE_ACCQ3 0xf4d501ff -+ -+/*P1_FFEI4*/ -+#define RSTV0910_P1_FFEI4 0xf4d6 -+#define FSTV0910_P1_FFE_ACCI4 0xf4d601ff -+ -+/*P1_FFEQ4*/ -+#define RSTV0910_P1_FFEQ4 0xf4d7 -+#define FSTV0910_P1_FFE_ACCQ4 0xf4d701ff -+ -+/*P1_FFECFG*/ -+#define RSTV0910_P1_FFECFG 0xf4d8 -+#define FSTV0910_P1_EQUALFFE_ON 0xf4d80040 -+#define FSTV0910_P1_EQUAL_USEDSYMB 0xf4d80030 -+#define FSTV0910_P1_MU_EQUALFFE 0xf4d80007 -+ -+/*P1_TNRCFG2*/ -+#define RSTV0910_P1_TNRCFG2 0xf4e1 -+#define FSTV0910_P1_TUN_IQSWAP 0xf4e10080 -+#define FSTV0910_P1_STB6110_STEP2MHZ 0xf4e10040 -+#define FSTV0910_P1_STB6120_DBLI2C 0xf4e10020 -+#define FSTV0910_P1_TUNER_WIDEBAND 0xf4e10010 -+#define FSTV0910_P1_TUNER_OBSPAGE 0xf4e10008 -+#define FSTV0910_P1_DIS_BWCALC 0xf4e10004 -+#define FSTV0910_P1_SHORT_WAITSTATES 0xf4e10002 -+#define FSTV0910_P1_DIS_2BWAGC1 0xf4e10001 -+ -+/*P1_SMAPCOEF7*/ -+#define RSTV0910_P1_SMAPCOEF7 0xf500 -+#define FSTV0910_P1_DIS_QSCALE 0xf5000080 -+#define FSTV0910_P1_SMAPCOEF_Q_LLR12 0xf500017f -+ -+/*P1_SMAPCOEF6*/ -+#define RSTV0910_P1_SMAPCOEF6 0xf501 -+#define FSTV0910_P1_DIS_AGC2SCALE 0xf5010080 -+#define FSTV0910_P1_DIS_16IQMULT 0xf5010040 -+#define FSTV0910_P1_OLD_16APSK47 0xf5010020 -+#define FSTV0910_P1_OLD_16APSK12 0xf5010010 -+#define FSTV0910_P1_DIS_NEWSCALE 0xf5010008 -+#define FSTV0910_P1_ADJ_8PSKLLR1 0xf5010004 -+#define FSTV0910_P1_OLD_8PSKLLR1 0xf5010002 -+#define FSTV0910_P1_DIS_AB8PSK 0xf5010001 -+ -+/*P1_SMAPCOEF5*/ -+#define RSTV0910_P1_SMAPCOEF5 0xf502 -+#define FSTV0910_P1_DIS_8SCALE 0xf5020080 -+#define FSTV0910_P1_SMAPCOEF_8P_LLR23 0xf502017f -+ -+/*P1_NOSTHRES1*/ -+#define RSTV0910_P1_NOSTHRES1 0xf509 -+#define FSTV0910_P1_NOS_THRESHOLD1 0xf50900ff -+ -+/*P1_NOSTHRES2*/ -+#define RSTV0910_P1_NOSTHRES2 0xf50a -+#define FSTV0910_P1_NOS_THRESHOLD2 0xf50a00ff -+ -+/*P1_NOSDIFF1*/ -+#define RSTV0910_P1_NOSDIFF1 0xf50b -+#define FSTV0910_P1_NOSTHRES1_DIFF 0xf50b00ff -+ -+/*P1_RAINFADE*/ -+#define RSTV0910_P1_RAINFADE 0xf50c -+#define FSTV0910_P1_NOSTHRES_DATAT 0xf50c0080 -+#define FSTV0910_P1_RAINFADE_CNLIMIT 0xf50c0070 -+#define FSTV0910_P1_RAINFADE_TIMEOUT 0xf50c0007 -+ -+/*P1_NOSRAMCFG*/ -+#define RSTV0910_P1_NOSRAMCFG 0xf50d -+#define FSTV0910_P1_NOSRAM_DVBS2DATA 0xf50d0080 -+#define FSTV0910_P1_NOSRAM_QUADRAT 0xf50d0040 -+#define FSTV0910_P1_NOSRAM_ACTIVATION 0xf50d0030 -+#define FSTV0910_P1_NOSRAM_CNRONLY 0xf50d0008 -+#define FSTV0910_P1_NOSRAM_LGNCNR1 0xf50d0007 -+ -+/*P1_NOSRAMPOS*/ -+#define RSTV0910_P1_NOSRAMPOS 0xf50e -+#define FSTV0910_P1_NOSRAM_LGNCNR0 0xf50e00f0 -+#define FSTV0910_P1_NOSRAM_VALIDE 0xf50e0004 -+#define FSTV0910_P1_NOSRAM_CNRVAL1 0xf50e0003 -+ -+/*P1_NOSRAMVAL*/ -+#define RSTV0910_P1_NOSRAMVAL 0xf50f -+#define FSTV0910_P1_NOSRAM_CNRVAL0 0xf50f00ff -+ -+/*P1_DMDPLHSTAT*/ -+#define RSTV0910_P1_DMDPLHSTAT 0xf520 -+#define FSTV0910_P1_PLH_STATISTIC 0xf52000ff -+ -+/*P1_LOCKTIME3*/ -+#define RSTV0910_P1_LOCKTIME3 0xf522 -+#define FSTV0910_P1_DEMOD_LOCKTIME3 0xf52200ff -+ -+/*P1_LOCKTIME2*/ -+#define RSTV0910_P1_LOCKTIME2 0xf523 -+#define FSTV0910_P1_DEMOD_LOCKTIME2 0xf52300ff -+ -+/*P1_LOCKTIME1*/ -+#define RSTV0910_P1_LOCKTIME1 0xf524 -+#define FSTV0910_P1_DEMOD_LOCKTIME1 0xf52400ff -+ -+/*P1_LOCKTIME0*/ -+#define RSTV0910_P1_LOCKTIME0 0xf525 -+#define FSTV0910_P1_DEMOD_LOCKTIME0 0xf52500ff -+ -+/*P1_VITSCALE*/ -+#define RSTV0910_P1_VITSCALE 0xf532 -+#define FSTV0910_P1_NVTH_NOSRANGE 0xf5320080 -+#define FSTV0910_P1_VERROR_MAXMODE 0xf5320040 -+#define FSTV0910_P1_KDIV_MODE 0xf5320030 -+#define FSTV0910_P1_NSLOWSN_LOCKED 0xf5320008 -+#define FSTV0910_P1_DELOCK_PRFLOSS 0xf5320004 -+#define FSTV0910_P1_DIS_RSFLOCK 0xf5320002 -+ -+/*P1_FECM*/ -+#define RSTV0910_P1_FECM 0xf533 -+#define FSTV0910_P1_DSS_DVB 0xf5330080 -+#define FSTV0910_P1_DEMOD_BYPASS 0xf5330040 -+#define FSTV0910_P1_CMP_SLOWMODE 0xf5330020 -+#define FSTV0910_P1_DSS_SRCH 0xf5330010 -+#define FSTV0910_P1_DIFF_MODEVIT 0xf5330004 -+#define FSTV0910_P1_SYNCVIT 0xf5330002 -+#define FSTV0910_P1_IQINV 0xf5330001 -+ -+/*P1_VTH12*/ -+#define RSTV0910_P1_VTH12 0xf534 -+#define FSTV0910_P1_VTH12 0xf53400ff -+ -+/*P1_VTH23*/ -+#define RSTV0910_P1_VTH23 0xf535 -+#define FSTV0910_P1_VTH23 0xf53500ff -+ -+/*P1_VTH34*/ -+#define RSTV0910_P1_VTH34 0xf536 -+#define FSTV0910_P1_VTH34 0xf53600ff -+ -+/*P1_VTH56*/ -+#define RSTV0910_P1_VTH56 0xf537 -+#define FSTV0910_P1_VTH56 0xf53700ff -+ -+/*P1_VTH67*/ -+#define RSTV0910_P1_VTH67 0xf538 -+#define FSTV0910_P1_VTH67 0xf53800ff -+ -+/*P1_VTH78*/ -+#define RSTV0910_P1_VTH78 0xf539 -+#define FSTV0910_P1_VTH78 0xf53900ff -+ -+/*P1_VITCURPUN*/ -+#define RSTV0910_P1_VITCURPUN 0xf53a -+#define FSTV0910_P1_CYCLESLIP_VIT 0xf53a0080 -+#define FSTV0910_P1_VIT_ROTA180 0xf53a0040 -+#define FSTV0910_P1_VIT_ROTA90 0xf53a0020 -+#define FSTV0910_P1_VIT_CURPUN 0xf53a001f -+ -+/*P1_VERROR*/ -+#define RSTV0910_P1_VERROR 0xf53b -+#define FSTV0910_P1_REGERR_VIT 0xf53b00ff -+ -+/*P1_PRVIT*/ -+#define RSTV0910_P1_PRVIT 0xf53c -+#define FSTV0910_P1_DIS_VTHLOCK 0xf53c0040 -+#define FSTV0910_P1_E7_8VIT 0xf53c0020 -+#define FSTV0910_P1_E6_7VIT 0xf53c0010 -+#define FSTV0910_P1_E5_6VIT 0xf53c0008 -+#define FSTV0910_P1_E3_4VIT 0xf53c0004 -+#define FSTV0910_P1_E2_3VIT 0xf53c0002 -+#define FSTV0910_P1_E1_2VIT 0xf53c0001 -+ -+/*P1_VAVSRVIT*/ -+#define RSTV0910_P1_VAVSRVIT 0xf53d -+#define FSTV0910_P1_AMVIT 0xf53d0080 -+#define FSTV0910_P1_FROZENVIT 0xf53d0040 -+#define FSTV0910_P1_SNVIT 0xf53d0030 -+#define FSTV0910_P1_TOVVIT 0xf53d000c -+#define FSTV0910_P1_HYPVIT 0xf53d0003 -+ -+/*P1_VSTATUSVIT*/ -+#define RSTV0910_P1_VSTATUSVIT 0xf53e -+#define FSTV0910_P1_VITERBI_ON 0xf53e0080 -+#define FSTV0910_P1_END_LOOPVIT 0xf53e0040 -+#define FSTV0910_P1_VITERBI_DEPRF 0xf53e0020 -+#define FSTV0910_P1_PRFVIT 0xf53e0010 -+#define FSTV0910_P1_LOCKEDVIT 0xf53e0008 -+#define FSTV0910_P1_VITERBI_DELOCK 0xf53e0004 -+#define FSTV0910_P1_VIT_DEMODSEL 0xf53e0002 -+#define FSTV0910_P1_VITERBI_COMPOUT 0xf53e0001 -+ -+/*P1_VTHINUSE*/ -+#define RSTV0910_P1_VTHINUSE 0xf53f -+#define FSTV0910_P1_VIT_INUSE 0xf53f00ff -+ -+/*P1_KDIV12*/ -+#define RSTV0910_P1_KDIV12 0xf540 -+#define FSTV0910_P1_KDIV12_MANUAL 0xf5400080 -+#define FSTV0910_P1_K_DIVIDER_12 0xf540007f -+ -+/*P1_KDIV23*/ -+#define RSTV0910_P1_KDIV23 0xf541 -+#define FSTV0910_P1_KDIV23_MANUAL 0xf5410080 -+#define FSTV0910_P1_K_DIVIDER_23 0xf541007f -+ -+/*P1_KDIV34*/ -+#define RSTV0910_P1_KDIV34 0xf542 -+#define FSTV0910_P1_KDIV34_MANUAL 0xf5420080 -+#define FSTV0910_P1_K_DIVIDER_34 0xf542007f -+ -+/*P1_KDIV56*/ -+#define RSTV0910_P1_KDIV56 0xf543 -+#define FSTV0910_P1_KDIV56_MANUAL 0xf5430080 -+#define FSTV0910_P1_K_DIVIDER_56 0xf543007f -+ -+/*P1_KDIV67*/ -+#define RSTV0910_P1_KDIV67 0xf544 -+#define FSTV0910_P1_KDIV67_MANUAL 0xf5440080 -+#define FSTV0910_P1_K_DIVIDER_67 0xf544007f -+ -+/*P1_KDIV78*/ -+#define RSTV0910_P1_KDIV78 0xf545 -+#define FSTV0910_P1_KDIV78_MANUAL 0xf5450080 -+#define FSTV0910_P1_K_DIVIDER_78 0xf545007f -+ -+/*P1_PDELCTRL0*/ -+#define RSTV0910_P1_PDELCTRL0 0xf54f -+#define FSTV0910_P1_ISIOBS_MODE 0xf54f0030 -+#define FSTV0910_P1_PDELDIS_BITWISE 0xf54f0004 -+ -+/*P1_PDELCTRL1*/ -+#define RSTV0910_P1_PDELCTRL1 0xf550 -+#define FSTV0910_P1_INV_MISMASK 0xf5500080 -+#define FSTV0910_P1_FORCE_ACCEPTED 0xf5500040 -+#define FSTV0910_P1_FILTER_EN 0xf5500020 -+#define FSTV0910_P1_FORCE_PKTDELINUSE 0xf5500010 -+#define FSTV0910_P1_HYSTEN 0xf5500008 -+#define FSTV0910_P1_HYSTSWRST 0xf5500004 -+#define FSTV0910_P1_EN_MIS00 0xf5500002 -+#define FSTV0910_P1_ALGOSWRST 0xf5500001 -+ -+/*P1_PDELCTRL2*/ -+#define RSTV0910_P1_PDELCTRL2 0xf551 -+#define FSTV0910_P1_FORCE_CONTINUOUS 0xf5510080 -+#define FSTV0910_P1_RESET_UPKO_COUNT 0xf5510040 -+#define FSTV0910_P1_USER_PKTDELIN_NB 0xf5510020 -+#define FSTV0910_P1_DATA_UNBBSCRAMBLED 0xf5510008 -+#define FSTV0910_P1_FORCE_LONGPKT 0xf5510004 -+#define FSTV0910_P1_FRAME_MODE 0xf5510002 -+ -+/*P1_HYSTTHRESH*/ -+#define RSTV0910_P1_HYSTTHRESH 0xf554 -+#define FSTV0910_P1_DELIN_LOCKTHRES 0xf55400f0 -+#define FSTV0910_P1_DELIN_UNLOCKTHRES 0xf554000f -+ -+/*P1_ISIENTRY*/ -+#define RSTV0910_P1_ISIENTRY 0xf55e -+#define FSTV0910_P1_ISI_ENTRY 0xf55e00ff -+ -+/*P1_ISIBITENA*/ -+#define RSTV0910_P1_ISIBITENA 0xf55f -+#define FSTV0910_P1_ISI_BIT_EN 0xf55f00ff -+ -+/*P1_MATSTR1*/ -+#define RSTV0910_P1_MATSTR1 0xf560 -+#define FSTV0910_P1_MATYPE_CURRENT1 0xf56000ff -+ -+/*P1_MATSTR0*/ -+#define RSTV0910_P1_MATSTR0 0xf561 -+#define FSTV0910_P1_MATYPE_CURRENT0 0xf56100ff -+ -+/*P1_UPLSTR1*/ -+#define RSTV0910_P1_UPLSTR1 0xf562 -+#define FSTV0910_P1_UPL_CURRENT1 0xf56200ff -+ -+/*P1_UPLSTR0*/ -+#define RSTV0910_P1_UPLSTR0 0xf563 -+#define FSTV0910_P1_UPL_CURRENT0 0xf56300ff -+ -+/*P1_DFLSTR1*/ -+#define RSTV0910_P1_DFLSTR1 0xf564 -+#define FSTV0910_P1_DFL_CURRENT1 0xf56400ff -+ -+/*P1_DFLSTR0*/ -+#define RSTV0910_P1_DFLSTR0 0xf565 -+#define FSTV0910_P1_DFL_CURRENT0 0xf56500ff -+ -+/*P1_SYNCSTR*/ -+#define RSTV0910_P1_SYNCSTR 0xf566 -+#define FSTV0910_P1_SYNC_CURRENT 0xf56600ff -+ -+/*P1_SYNCDSTR1*/ -+#define RSTV0910_P1_SYNCDSTR1 0xf567 -+#define FSTV0910_P1_SYNCD_CURRENT1 0xf56700ff -+ -+/*P1_SYNCDSTR0*/ -+#define RSTV0910_P1_SYNCDSTR0 0xf568 -+#define FSTV0910_P1_SYNCD_CURRENT0 0xf56800ff -+ -+/*P1_PDELSTATUS1*/ -+#define RSTV0910_P1_PDELSTATUS1 0xf569 -+#define FSTV0910_P1_PKTDELIN_DELOCK 0xf5690080 -+#define FSTV0910_P1_SYNCDUPDFL_BADDFL 0xf5690040 -+#define FSTV0910_P1_CONTINUOUS_STREAM 0xf5690020 -+#define FSTV0910_P1_UNACCEPTED_STREAM 0xf5690010 -+#define FSTV0910_P1_BCH_ERROR_FLAG 0xf5690008 -+#define FSTV0910_P1_BBHCRCKO 0xf5690004 -+#define FSTV0910_P1_PKTDELIN_LOCK 0xf5690002 -+#define FSTV0910_P1_FIRST_LOCK 0xf5690001 -+ -+/*P1_PDELSTATUS2*/ -+#define RSTV0910_P1_PDELSTATUS2 0xf56a -+#define FSTV0910_P1_PKTDEL_DEMODSEL 0xf56a0080 -+#define FSTV0910_P1_FRAME_MODCOD 0xf56a007c -+#define FSTV0910_P1_FRAME_TYPE 0xf56a0003 -+ -+/*P1_BBFCRCKO1*/ -+#define RSTV0910_P1_BBFCRCKO1 0xf56b -+#define FSTV0910_P1_BBHCRC_KOCNT1 0xf56b00ff -+ -+/*P1_BBFCRCKO0*/ -+#define RSTV0910_P1_BBFCRCKO0 0xf56c -+#define FSTV0910_P1_BBHCRC_KOCNT0 0xf56c00ff -+ -+/*P1_UPCRCKO1*/ -+#define RSTV0910_P1_UPCRCKO1 0xf56d -+#define FSTV0910_P1_PKTCRC_KOCNT1 0xf56d00ff -+ -+/*P1_UPCRCKO0*/ -+#define RSTV0910_P1_UPCRCKO0 0xf56e -+#define FSTV0910_P1_PKTCRC_KOCNT0 0xf56e00ff -+ -+/*P1_PDELCTRL3*/ -+#define RSTV0910_P1_PDELCTRL3 0xf56f -+#define FSTV0910_P1_PKTDEL_CONTFAIL 0xf56f0080 -+#define FSTV0910_P1_PKTDEL_ENLONGPKT 0xf56f0040 -+#define FSTV0910_P1_NOFIFO_BCHERR 0xf56f0020 -+#define FSTV0910_P1_PKTDELIN_DELACMERR 0xf56f0010 -+#define FSTV0910_P1_SATURATE_BBPKTKO 0xf56f0004 -+#define FSTV0910_P1_PKTDEL_BCHERRCONT 0xf56f0002 -+#define FSTV0910_P1_ETHERNET_DISFCS 0xf56f0001 -+ -+/*P1_TSSTATEM*/ -+#define RSTV0910_P1_TSSTATEM 0xf570 -+#define FSTV0910_P1_TSDIL_ON 0xf5700080 -+#define FSTV0910_P1_TSSKIPRS_ON 0xf5700040 -+#define FSTV0910_P1_TSRS_ON 0xf5700020 -+#define FSTV0910_P1_TSDESCRAMB_ON 0xf5700010 -+#define FSTV0910_P1_TSFRAME_MODE 0xf5700008 -+#define FSTV0910_P1_TS_DISABLE 0xf5700004 -+#define FSTV0910_P1_TSACM_MODE 0xf5700002 -+#define FSTV0910_P1_TSOUT_NOSYNC 0xf5700001 -+ -+/*P1_TSCFGH*/ -+#define RSTV0910_P1_TSCFGH 0xf572 -+#define FSTV0910_P1_TSFIFO_DVBCI 0xf5720080 -+#define FSTV0910_P1_TSFIFO_SERIAL 0xf5720040 -+#define FSTV0910_P1_TSFIFO_TEIUPDATE 0xf5720020 -+#define FSTV0910_P1_TSFIFO_DUTY50 0xf5720010 -+#define FSTV0910_P1_TSFIFO_HSGNLOUT 0xf5720008 -+#define FSTV0910_P1_TSFIFO_ERRMODE 0xf5720006 -+#define FSTV0910_P1_RST_HWARE 0xf5720001 -+ -+/*P1_TSCFGM*/ -+#define RSTV0910_P1_TSCFGM 0xf573 -+#define FSTV0910_P1_TSFIFO_MANSPEED 0xf57300c0 -+#define FSTV0910_P1_TSFIFO_PERMDATA 0xf5730020 -+#define FSTV0910_P1_TSFIFO_NONEWSGNL 0xf5730010 -+#define FSTV0910_P1_NPD_SPECDVBS2 0xf5730004 -+#define FSTV0910_P1_TSFIFO_DPUNACTIVE 0xf5730002 -+#define FSTV0910_P1_TSFIFO_INVDATA 0xf5730001 -+ -+/*P1_TSCFGL*/ -+#define RSTV0910_P1_TSCFGL 0xf574 -+#define FSTV0910_P1_TSFIFO_BCLKDEL1CK 0xf57400c0 -+#define FSTV0910_P1_BCHERROR_MODE 0xf5740030 -+#define FSTV0910_P1_TSFIFO_NSGNL2DATA 0xf5740008 -+#define FSTV0910_P1_TSFIFO_EMBINDVB 0xf5740004 -+#define FSTV0910_P1_TSFIFO_BITSPEED 0xf5740003 -+ -+/*P1_TSINSDELH*/ -+#define RSTV0910_P1_TSINSDELH 0xf576 -+#define FSTV0910_P1_TSDEL_SYNCBYTE 0xf5760080 -+#define FSTV0910_P1_TSDEL_XXHEADER 0xf5760040 -+#define FSTV0910_P1_TSDEL_BBHEADER 0xf5760020 -+#define FSTV0910_P1_TSDEL_DATAFIELD 0xf5760010 -+#define FSTV0910_P1_TSINSDEL_ISCR 0xf5760008 -+#define FSTV0910_P1_TSINSDEL_NPD 0xf5760004 -+#define FSTV0910_P1_TSINSDEL_RSPARITY 0xf5760002 -+#define FSTV0910_P1_TSINSDEL_CRC8 0xf5760001 -+ -+/*P1_TSDIVN*/ -+#define RSTV0910_P1_TSDIVN 0xf579 -+#define FSTV0910_P1_TSFIFO_SPEEDMODE 0xf57900c0 -+#define FSTV0910_P1_BYTE_OVERSAMPLING 0xf5790038 -+#define FSTV0910_P1_TSFIFO_RISEOK 0xf5790007 -+ -+/*P1_TSCFG4*/ -+#define RSTV0910_P1_TSCFG4 0xf57a -+#define FSTV0910_P1_TSFIFO_TSSPEEDMODE 0xf57a00c0 -+#define FSTV0910_P1_TSFIFO_HIERSEL 0xf57a0020 -+#define FSTV0910_P1_TSFIFO_SPECTOKEN 0xf57a0010 -+#define FSTV0910_P1_TSFIFO_MAXMODE 0xf57a0008 -+#define FSTV0910_P1_TSFIFO_FRFORCEPKT 0xf57a0004 -+#define FSTV0910_P1_EXT_FECSPYIN 0xf57a0002 -+#define FSTV0910_P1_TSFIFO_DELSPEEDUP 0xf57a0001 -+ -+/*P1_TSSPEED*/ -+#define RSTV0910_P1_TSSPEED 0xf580 -+#define FSTV0910_P1_TSFIFO_OUTSPEED 0xf58000ff -+ -+/*P1_TSSTATUS*/ -+#define RSTV0910_P1_TSSTATUS 0xf581 -+#define FSTV0910_P1_TSFIFO_LINEOK 0xf5810080 -+#define FSTV0910_P1_TSFIFO_ERROR 0xf5810040 -+#define FSTV0910_P1_TSFIFO_DATA7 0xf5810020 -+#define FSTV0910_P1_TSFIFO_NOSYNC 0xf5810010 -+#define FSTV0910_P1_ISCR_INITIALIZED 0xf5810008 -+#define FSTV0910_P1_TSREGUL_ERROR 0xf5810004 -+#define FSTV0910_P1_SOFFIFO_UNREGUL 0xf5810002 -+#define FSTV0910_P1_DIL_READY 0xf5810001 -+ -+/*P1_TSSTATUS2*/ -+#define RSTV0910_P1_TSSTATUS2 0xf582 -+#define FSTV0910_P1_TSFIFO_DEMODSEL 0xf5820080 -+#define FSTV0910_P1_TSFIFOSPEED_STORE 0xf5820040 -+#define FSTV0910_P1_DILXX_RESET 0xf5820020 -+#define FSTV0910_P1_TSSPEED_IMPOSSIBLE 0xf5820010 -+#define FSTV0910_P1_TSFIFO_LINENOK 0xf5820008 -+#define FSTV0910_P1_TSFIFO_MUXSTREAM 0xf5820004 -+#define FSTV0910_P1_SCRAMBDETECT 0xf5820002 -+#define FSTV0910_P1_ULDTV67_FALSELOCK 0xf5820001 -+ -+/*P1_TSBITRATE1*/ -+#define RSTV0910_P1_TSBITRATE1 0xf583 -+#define FSTV0910_P1_TSFIFO_BITRATE1 0xf58300ff -+ -+/*P1_TSBITRATE0*/ -+#define RSTV0910_P1_TSBITRATE0 0xf584 -+#define FSTV0910_P1_TSFIFO_BITRATE0 0xf58400ff -+ -+/*P1_ERRCTRL1*/ -+#define RSTV0910_P1_ERRCTRL1 0xf598 -+#define FSTV0910_P1_ERR_SOURCE1 0xf59800f0 -+#define FSTV0910_P1_NUM_EVENT1 0xf5980007 -+ -+/*P1_ERRCNT12*/ -+#define RSTV0910_P1_ERRCNT12 0xf599 -+#define FSTV0910_P1_ERRCNT1_OLDVALUE 0xf5990080 -+#define FSTV0910_P1_ERR_CNT12 0xf599007f -+ -+/*P1_ERRCNT11*/ -+#define RSTV0910_P1_ERRCNT11 0xf59a -+#define FSTV0910_P1_ERR_CNT11 0xf59a00ff -+ -+/*P1_ERRCNT10*/ -+#define RSTV0910_P1_ERRCNT10 0xf59b -+#define FSTV0910_P1_ERR_CNT10 0xf59b00ff -+ -+/*P1_ERRCTRL2*/ -+#define RSTV0910_P1_ERRCTRL2 0xf59c -+#define FSTV0910_P1_ERR_SOURCE2 0xf59c00f0 -+#define FSTV0910_P1_NUM_EVENT2 0xf59c0007 -+ -+/*P1_ERRCNT22*/ -+#define RSTV0910_P1_ERRCNT22 0xf59d -+#define FSTV0910_P1_ERRCNT2_OLDVALUE 0xf59d0080 -+#define FSTV0910_P1_ERR_CNT22 0xf59d007f -+ -+/*P1_ERRCNT21*/ -+#define RSTV0910_P1_ERRCNT21 0xf59e -+#define FSTV0910_P1_ERR_CNT21 0xf59e00ff -+ -+/*P1_ERRCNT20*/ -+#define RSTV0910_P1_ERRCNT20 0xf59f -+#define FSTV0910_P1_ERR_CNT20 0xf59f00ff -+ -+/*P1_FECSPY*/ -+#define RSTV0910_P1_FECSPY 0xf5a0 -+#define FSTV0910_P1_SPY_ENABLE 0xf5a00080 -+#define FSTV0910_P1_NO_SYNCBYTE 0xf5a00040 -+#define FSTV0910_P1_SERIAL_MODE 0xf5a00020 -+#define FSTV0910_P1_UNUSUAL_PACKET 0xf5a00010 -+#define FSTV0910_P1_BERMETER_DATAMODE 0xf5a0000c -+#define FSTV0910_P1_BERMETER_LMODE 0xf5a00002 -+#define FSTV0910_P1_BERMETER_RESET 0xf5a00001 -+ -+/*P1_FSPYCFG*/ -+#define RSTV0910_P1_FSPYCFG 0xf5a1 -+#define FSTV0910_P1_FECSPY_INPUT 0xf5a100c0 -+#define FSTV0910_P1_RST_ON_ERROR 0xf5a10020 -+#define FSTV0910_P1_ONE_SHOT 0xf5a10010 -+#define FSTV0910_P1_I2C_MODE 0xf5a1000c -+#define FSTV0910_P1_SPY_HYSTERESIS 0xf5a10003 -+ -+/*P1_FSPYDATA*/ -+#define RSTV0910_P1_FSPYDATA 0xf5a2 -+#define FSTV0910_P1_SPY_STUFFING 0xf5a20080 -+#define FSTV0910_P1_NOERROR_PKTJITTER 0xf5a20040 -+#define FSTV0910_P1_SPY_CNULLPKT 0xf5a20020 -+#define FSTV0910_P1_SPY_OUTDATA_MODE 0xf5a2001f -+ -+/*P1_FSPYOUT*/ -+#define RSTV0910_P1_FSPYOUT 0xf5a3 -+#define FSTV0910_P1_FSPY_DIRECT 0xf5a30080 -+#define FSTV0910_P1_SPY_OUTDATA_BUS 0xf5a30038 -+#define FSTV0910_P1_STUFF_MODE 0xf5a30007 -+ -+/*P1_FSTATUS*/ -+#define RSTV0910_P1_FSTATUS 0xf5a4 -+#define FSTV0910_P1_SPY_ENDSIM 0xf5a40080 -+#define FSTV0910_P1_VALID_SIM 0xf5a40040 -+#define FSTV0910_P1_FOUND_SIGNAL 0xf5a40020 -+#define FSTV0910_P1_DSS_SYNCBYTE 0xf5a40010 -+#define FSTV0910_P1_RESULT_STATE 0xf5a4000f -+ -+/*P1_FBERCPT4*/ -+#define RSTV0910_P1_FBERCPT4 0xf5a8 -+#define FSTV0910_P1_FBERMETER_CPT4 0xf5a800ff -+ -+/*P1_FBERCPT3*/ -+#define RSTV0910_P1_FBERCPT3 0xf5a9 -+#define FSTV0910_P1_FBERMETER_CPT3 0xf5a900ff -+ -+/*P1_FBERCPT2*/ -+#define RSTV0910_P1_FBERCPT2 0xf5aa -+#define FSTV0910_P1_FBERMETER_CPT2 0xf5aa00ff -+ -+/*P1_FBERCPT1*/ -+#define RSTV0910_P1_FBERCPT1 0xf5ab -+#define FSTV0910_P1_FBERMETER_CPT1 0xf5ab00ff -+ -+/*P1_FBERCPT0*/ -+#define RSTV0910_P1_FBERCPT0 0xf5ac -+#define FSTV0910_P1_FBERMETER_CPT0 0xf5ac00ff -+ -+/*P1_FBERERR2*/ -+#define RSTV0910_P1_FBERERR2 0xf5ad -+#define FSTV0910_P1_FBERMETER_ERR2 0xf5ad00ff -+ -+/*P1_FBERERR1*/ -+#define RSTV0910_P1_FBERERR1 0xf5ae -+#define FSTV0910_P1_FBERMETER_ERR1 0xf5ae00ff -+ -+/*P1_FBERERR0*/ -+#define RSTV0910_P1_FBERERR0 0xf5af -+#define FSTV0910_P1_FBERMETER_ERR0 0xf5af00ff -+ -+/*P1_FSPYBER*/ -+#define RSTV0910_P1_FSPYBER 0xf5b2 -+#define FSTV0910_P1_FSPYOBS_XORREAD 0xf5b20040 -+#define FSTV0910_P1_FSPYBER_OBSMODE 0xf5b20020 -+#define FSTV0910_P1_FSPYBER_SYNCBYTE 0xf5b20010 -+#define FSTV0910_P1_FSPYBER_UNSYNC 0xf5b20008 -+#define FSTV0910_P1_FSPYBER_CTIME 0xf5b20007 -+ -+/*P1_SFERROR*/ -+#define RSTV0910_P1_SFERROR 0xf5c1 -+#define FSTV0910_P1_SFEC_REGERR_VIT 0xf5c100ff -+ -+/*P1_SFECSTATUS*/ -+#define RSTV0910_P1_SFECSTATUS 0xf5c3 -+#define FSTV0910_P1_SFEC_ON 0xf5c30080 -+#define FSTV0910_P1_SFEC_OFF 0xf5c30040 -+#define FSTV0910_P1_LOCKEDSFEC 0xf5c30008 -+#define FSTV0910_P1_SFEC_DELOCK 0xf5c30004 -+#define FSTV0910_P1_SFEC_DEMODSEL 0xf5c30002 -+#define FSTV0910_P1_SFEC_OVFON 0xf5c30001 -+ -+/*P1_SFKDIV12*/ -+#define RSTV0910_P1_SFKDIV12 0xf5c4 -+#define FSTV0910_P1_SFECKDIV12_MAN 0xf5c40080 -+#define FSTV0910_P1_SFEC_K_DIVIDER_12 0xf5c4007f -+ -+/*P1_SFKDIV23*/ -+#define RSTV0910_P1_SFKDIV23 0xf5c5 -+#define FSTV0910_P1_SFECKDIV23_MAN 0xf5c50080 -+#define FSTV0910_P1_SFEC_K_DIVIDER_23 0xf5c5007f -+ -+/*P1_SFKDIV34*/ -+#define RSTV0910_P1_SFKDIV34 0xf5c6 -+#define FSTV0910_P1_SFECKDIV34_MAN 0xf5c60080 -+#define FSTV0910_P1_SFEC_K_DIVIDER_34 0xf5c6007f -+ -+/*P1_SFKDIV56*/ -+#define RSTV0910_P1_SFKDIV56 0xf5c7 -+#define FSTV0910_P1_SFECKDIV56_MAN 0xf5c70080 -+#define FSTV0910_P1_SFEC_K_DIVIDER_56 0xf5c7007f -+ -+/*P1_SFKDIV67*/ -+#define RSTV0910_P1_SFKDIV67 0xf5c8 -+#define FSTV0910_P1_SFECKDIV67_MAN 0xf5c80080 -+#define FSTV0910_P1_SFEC_K_DIVIDER_67 0xf5c8007f -+ -+/*P1_SFKDIV78*/ -+#define RSTV0910_P1_SFKDIV78 0xf5c9 -+#define FSTV0910_P1_SFECKDIV78_MAN 0xf5c90080 -+#define FSTV0910_P1_SFEC_K_DIVIDER_78 0xf5c9007f -+ -+/*P1_SFSTATUS*/ -+#define RSTV0910_P1_SFSTATUS 0xf5cc -+#define FSTV0910_P1_SFEC_LINEOK 0xf5cc0080 -+#define FSTV0910_P1_SFEC_ERROR 0xf5cc0040 -+#define FSTV0910_P1_SFEC_DATA7 0xf5cc0020 -+#define FSTV0910_P1_SFEC_PKTDNBRFAIL 0xf5cc0010 -+#define FSTV0910_P1_TSSFEC_DEMODSEL 0xf5cc0008 -+#define FSTV0910_P1_SFEC_NOSYNC 0xf5cc0004 -+#define FSTV0910_P1_SFEC_UNREGULA 0xf5cc0002 -+#define FSTV0910_P1_SFEC_READY 0xf5cc0001 -+ -+/*P1_SFDLYSET2*/ -+#define RSTV0910_P1_SFDLYSET2 0xf5d0 -+#define FSTV0910_P1_SFEC_OFFSET 0xf5d000c0 -+#define FSTV0910_P1_RST_SFEC 0xf5d00008 -+#define FSTV0910_P1_DILDLINE_ERROR 0xf5d00004 -+#define FSTV0910_P1_SFEC_DISABLE 0xf5d00002 -+#define FSTV0910_P1_SFEC_UNREGUL 0xf5d00001 -+ -+/*P1_SFERRCTRL*/ -+#define RSTV0910_P1_SFERRCTRL 0xf5d8 -+#define FSTV0910_P1_SFEC_ERR_SOURCE 0xf5d800f0 -+#define FSTV0910_P1_SFEC_NUM_EVENT 0xf5d80007 -+ -+/*P1_SFERRCNT2*/ -+#define RSTV0910_P1_SFERRCNT2 0xf5d9 -+#define FSTV0910_P1_SFERRC_OLDVALUE 0xf5d90080 -+#define FSTV0910_P1_SFEC_ERR_CNT2 0xf5d9007f -+ -+/*P1_SFERRCNT1*/ -+#define RSTV0910_P1_SFERRCNT1 0xf5da -+#define FSTV0910_P1_SFEC_ERR_CNT1 0xf5da00ff -+ -+/*P1_SFERRCNT0*/ -+#define RSTV0910_P1_SFERRCNT0 0xf5db -+#define FSTV0910_P1_SFEC_ERR_CNT0 0xf5db00ff -+ -+/*TSGENERAL*/ -+#define RSTV0910_TSGENERAL 0xf630 -+#define FSTV0910_EN_LGNERROR 0xf6300080 -+#define FSTV0910_TSFIFO_DISTS2PAR 0xf6300040 -+#define FSTV0910_MUXSTREAM_COMPMOSE 0xf6300030 -+#define FSTV0910_MUXSTREAM_OUTMODE 0xf6300008 -+#define FSTV0910_TSFIFO_PERMPARAL 0xf6300006 -+#define FSTV0910_RST_REEDSOLO 0xf6300001 -+ -+/*P1_DISIRQCFG*/ -+#define RSTV0910_P1_DISIRQCFG 0xf700 -+#define FSTV0910_P1_ENRXEND 0xf7000040 -+#define FSTV0910_P1_ENRXFIFO8B 0xf7000020 -+#define FSTV0910_P1_ENTRFINISH 0xf7000010 -+#define FSTV0910_P1_ENTIMEOUT 0xf7000008 -+#define FSTV0910_P1_ENTXEND 0xf7000004 -+#define FSTV0910_P1_ENTXFIFO64B 0xf7000002 -+#define FSTV0910_P1_ENGAPBURST 0xf7000001 -+ -+/*P1_DISIRQSTAT*/ -+#define RSTV0910_P1_DISIRQSTAT 0xf701 -+#define FSTV0910_P1_IRQRXEND 0xf7010040 -+#define FSTV0910_P1_IRQRXFIFO8B 0xf7010020 -+#define FSTV0910_P1_IRQTRFINISH 0xf7010010 -+#define FSTV0910_P1_IRQTIMEOUT 0xf7010008 -+#define FSTV0910_P1_IRQTXEND 0xf7010004 -+#define FSTV0910_P1_IRQTXFIFO64B 0xf7010002 -+#define FSTV0910_P1_IRQGAPBURST 0xf7010001 -+ -+/*P1_DISTXCFG*/ -+#define RSTV0910_P1_DISTXCFG 0xf702 -+#define FSTV0910_P1_DISTX_RESET 0xf7020080 -+#define FSTV0910_P1_TIM_OFF 0xf7020040 -+#define FSTV0910_P1_TIM_CMD 0xf7020030 -+#define FSTV0910_P1_ENVELOP 0xf7020008 -+#define FSTV0910_P1_DIS_PRECHARGE 0xf7020004 -+#define FSTV0910_P1_DISEQC_MODE 0xf7020003 -+ -+/*P1_DISTXSTATUS*/ -+#define RSTV0910_P1_DISTXSTATUS 0xf703 -+#define FSTV0910_P1_TX_FIFO_FULL 0xf7030040 -+#define FSTV0910_P1_TX_IDLE 0xf7030020 -+#define FSTV0910_P1_GAP_BURST 0xf7030010 -+#define FSTV0910_P1_TX_FIFO64B 0xf7030008 -+#define FSTV0910_P1_TX_END 0xf7030004 -+#define FSTV0910_P1_TR_TIMEOUT 0xf7030002 -+#define FSTV0910_P1_TR_FINISH 0xf7030001 -+ -+/*P1_DISTXBYTES*/ -+#define RSTV0910_P1_DISTXBYTES 0xf704 -+#define FSTV0910_P1_TXFIFO_BYTES 0xf70400ff -+ -+/*P1_DISTXFIFO*/ -+#define RSTV0910_P1_DISTXFIFO 0xf705 -+#define FSTV0910_P1_DISEQC_TX_FIFO 0xf70500ff -+ -+/*P1_DISTXF22*/ -+#define RSTV0910_P1_DISTXF22 0xf706 -+#define FSTV0910_P1_F22TX 0xf70600ff -+ -+/*P1_DISTIMEOCFG*/ -+#define RSTV0910_P1_DISTIMEOCFG 0xf708 -+#define FSTV0910_P1_RXCHOICE 0xf7080006 -+#define FSTV0910_P1_TIMEOUT_OFF 0xf7080001 -+ -+/*P1_DISTIMEOUT*/ -+#define RSTV0910_P1_DISTIMEOUT 0xf709 -+#define FSTV0910_P1_TIMEOUT_COUNT 0xf70900ff -+ -+/*P1_DISRXCFG*/ -+#define RSTV0910_P1_DISRXCFG 0xf70a -+#define FSTV0910_P1_DISRX_RESET 0xf70a0080 -+#define FSTV0910_P1_EXTENVELOP 0xf70a0040 -+#define FSTV0910_P1_PINSELECT 0xf70a0038 -+#define FSTV0910_P1_IGNORE_SHORT22K 0xf70a0004 -+#define FSTV0910_P1_SIGNED_RXIN 0xf70a0002 -+#define FSTV0910_P1_DISRX_ON 0xf70a0001 -+ -+/*P1_DISRXSTAT1*/ -+#define RSTV0910_P1_DISRXSTAT1 0xf70b -+#define FSTV0910_P1_RXEND 0xf70b0080 -+#define FSTV0910_P1_RXACTIVE 0xf70b0040 -+#define FSTV0910_P1_RXDETECT 0xf70b0020 -+#define FSTV0910_P1_CONTTONE 0xf70b0010 -+#define FSTV0910_P1_8BFIFOREADY 0xf70b0008 -+#define FSTV0910_P1_FIFOEMPTY 0xf70b0004 -+ -+/*P1_DISRXSTAT0*/ -+#define RSTV0910_P1_DISRXSTAT0 0xf70c -+#define FSTV0910_P1_RXFAIL 0xf70c0080 -+#define FSTV0910_P1_FIFOPFAIL 0xf70c0040 -+#define FSTV0910_P1_RXNONBYTE 0xf70c0020 -+#define FSTV0910_P1_FIFOOVF 0xf70c0010 -+#define FSTV0910_P1_SHORT22K 0xf70c0008 -+#define FSTV0910_P1_RXMSGLOST 0xf70c0004 -+ -+/*P1_DISRXBYTES*/ -+#define RSTV0910_P1_DISRXBYTES 0xf70d -+#define FSTV0910_P1_RXFIFO_BYTES 0xf70d001f -+ -+/*P1_DISRXPARITY1*/ -+#define RSTV0910_P1_DISRXPARITY1 0xf70e -+#define FSTV0910_P1_DISRX_PARITY1 0xf70e00ff -+ -+/*P1_DISRXPARITY0*/ -+#define RSTV0910_P1_DISRXPARITY0 0xf70f -+#define FSTV0910_P1_DISRX_PARITY0 0xf70f00ff -+ -+/*P1_DISRXFIFO*/ -+#define RSTV0910_P1_DISRXFIFO 0xf710 -+#define FSTV0910_P1_DISEQC_RX_FIFO 0xf71000ff -+ -+/*P1_DISRXDC1*/ -+#define RSTV0910_P1_DISRXDC1 0xf711 -+#define FSTV0910_P1_DC_VALUE1 0xf7110103 -+ -+/*P1_DISRXDC0*/ -+#define RSTV0910_P1_DISRXDC0 0xf712 -+#define FSTV0910_P1_DC_VALUE0 0xf71200ff -+ -+/*P1_DISRXF221*/ -+#define RSTV0910_P1_DISRXF221 0xf714 -+#define FSTV0910_P1_F22RX1 0xf714000f -+ -+/*P1_DISRXF220*/ -+#define RSTV0910_P1_DISRXF220 0xf715 -+#define FSTV0910_P1_F22RX0 0xf71500ff -+ -+/*P1_DISRXF100*/ -+#define RSTV0910_P1_DISRXF100 0xf716 -+#define FSTV0910_P1_F100RX 0xf71600ff -+ -+/*P1_DISRXSHORT22K*/ -+#define RSTV0910_P1_DISRXSHORT22K 0xf71c -+#define FSTV0910_P1_SHORT22K_LENGTH 0xf71c001f -+ -+/*P1_ACRPRESC*/ -+#define RSTV0910_P1_ACRPRESC 0xf71e -+#define FSTV0910_P1_ACR_CODFRDY 0xf71e0008 -+#define FSTV0910_P1_ACR_PRESC 0xf71e0007 -+ -+/*P1_ACRDIV*/ -+#define RSTV0910_P1_ACRDIV 0xf71f -+#define FSTV0910_P1_ACR_DIV 0xf71f00ff -+ -+/*P2_DISIRQCFG*/ -+#define RSTV0910_P2_DISIRQCFG 0xf740 -+#define FSTV0910_P2_ENRXEND 0xf7400040 -+#define FSTV0910_P2_ENRXFIFO8B 0xf7400020 -+#define FSTV0910_P2_ENTRFINISH 0xf7400010 -+#define FSTV0910_P2_ENTIMEOUT 0xf7400008 -+#define FSTV0910_P2_ENTXEND 0xf7400004 -+#define FSTV0910_P2_ENTXFIFO64B 0xf7400002 -+#define FSTV0910_P2_ENGAPBURST 0xf7400001 -+ -+/*P2_DISIRQSTAT*/ -+#define RSTV0910_P2_DISIRQSTAT 0xf741 -+#define FSTV0910_P2_IRQRXEND 0xf7410040 -+#define FSTV0910_P2_IRQRXFIFO8B 0xf7410020 -+#define FSTV0910_P2_IRQTRFINISH 0xf7410010 -+#define FSTV0910_P2_IRQTIMEOUT 0xf7410008 -+#define FSTV0910_P2_IRQTXEND 0xf7410004 -+#define FSTV0910_P2_IRQTXFIFO64B 0xf7410002 -+#define FSTV0910_P2_IRQGAPBURST 0xf7410001 -+ -+/*P2_DISTXCFG*/ -+#define RSTV0910_P2_DISTXCFG 0xf742 -+#define FSTV0910_P2_DISTX_RESET 0xf7420080 -+#define FSTV0910_P2_TIM_OFF 0xf7420040 -+#define FSTV0910_P2_TIM_CMD 0xf7420030 -+#define FSTV0910_P2_ENVELOP 0xf7420008 -+#define FSTV0910_P2_DIS_PRECHARGE 0xf7420004 -+#define FSTV0910_P2_DISEQC_MODE 0xf7420003 -+ -+/*P2_DISTXSTATUS*/ -+#define RSTV0910_P2_DISTXSTATUS 0xf743 -+#define FSTV0910_P2_TX_FIFO_FULL 0xf7430040 -+#define FSTV0910_P2_TX_IDLE 0xf7430020 -+#define FSTV0910_P2_GAP_BURST 0xf7430010 -+#define FSTV0910_P2_TX_FIFO64B 0xf7430008 -+#define FSTV0910_P2_TX_END 0xf7430004 -+#define FSTV0910_P2_TR_TIMEOUT 0xf7430002 -+#define FSTV0910_P2_TR_FINISH 0xf7430001 -+ -+/*P2_DISTXBYTES*/ -+#define RSTV0910_P2_DISTXBYTES 0xf744 -+#define FSTV0910_P2_TXFIFO_BYTES 0xf74400ff -+ -+/*P2_DISTXFIFO*/ -+#define RSTV0910_P2_DISTXFIFO 0xf745 -+#define FSTV0910_P2_DISEQC_TX_FIFO 0xf74500ff -+ -+/*P2_DISTXF22*/ -+#define RSTV0910_P2_DISTXF22 0xf746 -+#define FSTV0910_P2_F22TX 0xf74600ff -+ -+/*P2_DISTIMEOCFG*/ -+#define RSTV0910_P2_DISTIMEOCFG 0xf748 -+#define FSTV0910_P2_RXCHOICE 0xf7480006 -+#define FSTV0910_P2_TIMEOUT_OFF 0xf7480001 -+ -+/*P2_DISTIMEOUT*/ -+#define RSTV0910_P2_DISTIMEOUT 0xf749 -+#define FSTV0910_P2_TIMEOUT_COUNT 0xf74900ff -+ -+/*P2_DISRXCFG*/ -+#define RSTV0910_P2_DISRXCFG 0xf74a -+#define FSTV0910_P2_DISRX_RESET 0xf74a0080 -+#define FSTV0910_P2_EXTENVELOP 0xf74a0040 -+#define FSTV0910_P2_PINSELECT 0xf74a0038 -+#define FSTV0910_P2_IGNORE_SHORT22K 0xf74a0004 -+#define FSTV0910_P2_SIGNED_RXIN 0xf74a0002 -+#define FSTV0910_P2_DISRX_ON 0xf74a0001 -+ -+/*P2_DISRXSTAT1*/ -+#define RSTV0910_P2_DISRXSTAT1 0xf74b -+#define FSTV0910_P2_RXEND 0xf74b0080 -+#define FSTV0910_P2_RXACTIVE 0xf74b0040 -+#define FSTV0910_P2_RXDETECT 0xf74b0020 -+#define FSTV0910_P2_CONTTONE 0xf74b0010 -+#define FSTV0910_P2_8BFIFOREADY 0xf74b0008 -+#define FSTV0910_P2_FIFOEMPTY 0xf74b0004 -+ -+/*P2_DISRXSTAT0*/ -+#define RSTV0910_P2_DISRXSTAT0 0xf74c -+#define FSTV0910_P2_RXFAIL 0xf74c0080 -+#define FSTV0910_P2_FIFOPFAIL 0xf74c0040 -+#define FSTV0910_P2_RXNONBYTE 0xf74c0020 -+#define FSTV0910_P2_FIFOOVF 0xf74c0010 -+#define FSTV0910_P2_SHORT22K 0xf74c0008 -+#define FSTV0910_P2_RXMSGLOST 0xf74c0004 -+ -+/*P2_DISRXBYTES*/ -+#define RSTV0910_P2_DISRXBYTES 0xf74d -+#define FSTV0910_P2_RXFIFO_BYTES 0xf74d001f -+ -+/*P2_DISRXPARITY1*/ -+#define RSTV0910_P2_DISRXPARITY1 0xf74e -+#define FSTV0910_P2_DISRX_PARITY1 0xf74e00ff -+ -+/*P2_DISRXPARITY0*/ -+#define RSTV0910_P2_DISRXPARITY0 0xf74f -+#define FSTV0910_P2_DISRX_PARITY0 0xf74f00ff -+ -+/*P2_DISRXFIFO*/ -+#define RSTV0910_P2_DISRXFIFO 0xf750 -+#define FSTV0910_P2_DISEQC_RX_FIFO 0xf75000ff -+ -+/*P2_DISRXDC1*/ -+#define RSTV0910_P2_DISRXDC1 0xf751 -+#define FSTV0910_P2_DC_VALUE1 0xf7510103 -+ -+/*P2_DISRXDC0*/ -+#define RSTV0910_P2_DISRXDC0 0xf752 -+#define FSTV0910_P2_DC_VALUE0 0xf75200ff -+ -+/*P2_DISRXF221*/ -+#define RSTV0910_P2_DISRXF221 0xf754 -+#define FSTV0910_P2_F22RX1 0xf754000f -+ -+/*P2_DISRXF220*/ -+#define RSTV0910_P2_DISRXF220 0xf755 -+#define FSTV0910_P2_F22RX0 0xf75500ff -+ -+/*P2_DISRXF100*/ -+#define RSTV0910_P2_DISRXF100 0xf756 -+#define FSTV0910_P2_F100RX 0xf75600ff -+ -+/*P2_DISRXSHORT22K*/ -+#define RSTV0910_P2_DISRXSHORT22K 0xf75c -+#define FSTV0910_P2_SHORT22K_LENGTH 0xf75c001f -+ -+/*P2_ACRPRESC*/ -+#define RSTV0910_P2_ACRPRESC 0xf75e -+#define FSTV0910_P2_ACR_CODFRDY 0xf75e0008 -+#define FSTV0910_P2_ACR_PRESC 0xf75e0007 -+ -+/*P2_ACRDIV*/ -+#define RSTV0910_P2_ACRDIV 0xf75f -+#define FSTV0910_P2_ACR_DIV 0xf75f00ff -+ -+/*P1_NBITER_NF4*/ -+#define RSTV0910_P1_NBITER_NF4 0xfa03 -+#define FSTV0910_P1_NBITER_NF_QPSK_1_2 0xfa0300ff -+ -+/*P1_NBITER_NF5*/ -+#define RSTV0910_P1_NBITER_NF5 0xfa04 -+#define FSTV0910_P1_NBITER_NF_QPSK_3_5 0xfa0400ff -+ -+/*P1_NBITER_NF6*/ -+#define RSTV0910_P1_NBITER_NF6 0xfa05 -+#define FSTV0910_P1_NBITER_NF_QPSK_2_3 0xfa0500ff -+ -+/*P1_NBITER_NF7*/ -+#define RSTV0910_P1_NBITER_NF7 0xfa06 -+#define FSTV0910_P1_NBITER_NF_QPSK_3_4 0xfa0600ff -+ -+/*P1_NBITER_NF8*/ -+#define RSTV0910_P1_NBITER_NF8 0xfa07 -+#define FSTV0910_P1_NBITER_NF_QPSK_4_5 0xfa0700ff -+ -+/*P1_NBITER_NF9*/ -+#define RSTV0910_P1_NBITER_NF9 0xfa08 -+#define FSTV0910_P1_NBITER_NF_QPSK_5_6 0xfa0800ff -+ -+/*P1_NBITER_NF10*/ -+#define RSTV0910_P1_NBITER_NF10 0xfa09 -+#define FSTV0910_P1_NBITER_NF_QPSK_8_9 0xfa0900ff -+ -+/*P1_NBITER_NF11*/ -+#define RSTV0910_P1_NBITER_NF11 0xfa0a -+#define FSTV0910_P1_NBITER_NF_QPSK_9_10 0xfa0a00ff -+ -+/*P1_NBITER_NF12*/ -+#define RSTV0910_P1_NBITER_NF12 0xfa0b -+#define FSTV0910_P1_NBITER_NF_8PSK_3_5 0xfa0b00ff -+ -+/*P1_NBITER_NF13*/ -+#define RSTV0910_P1_NBITER_NF13 0xfa0c -+#define FSTV0910_P1_NBITER_NF_8PSK_2_3 0xfa0c00ff -+ -+/*P1_NBITER_NF14*/ -+#define RSTV0910_P1_NBITER_NF14 0xfa0d -+#define FSTV0910_P1_NBITER_NF_8PSK_3_4 0xfa0d00ff -+ -+/*P1_NBITER_NF15*/ -+#define RSTV0910_P1_NBITER_NF15 0xfa0e -+#define FSTV0910_P1_NBITER_NF_8PSK_5_6 0xfa0e00ff -+ -+/*P1_NBITER_NF16*/ -+#define RSTV0910_P1_NBITER_NF16 0xfa0f -+#define FSTV0910_P1_NBITER_NF_8PSK_8_9 0xfa0f00ff -+ -+/*P1_NBITER_NF17*/ -+#define RSTV0910_P1_NBITER_NF17 0xfa10 -+#define FSTV0910_P1_NBITER_NF_8PSK_9_10 0xfa1000ff -+ -+/*GAINLLR_NF4*/ -+#define RSTV0910_GAINLLR_NF4 0xfa43 -+#define FSTV0910_GAINLLR_NF_QPSK_1_2 0xfa43007f -+ -+/*GAINLLR_NF5*/ -+#define RSTV0910_GAINLLR_NF5 0xfa44 -+#define FSTV0910_GAINLLR_NF_QPSK_3_5 0xfa44007f -+ -+/*GAINLLR_NF6*/ -+#define RSTV0910_GAINLLR_NF6 0xfa45 -+#define FSTV0910_GAINLLR_NF_QPSK_2_3 0xfa45007f -+ -+/*GAINLLR_NF7*/ -+#define RSTV0910_GAINLLR_NF7 0xfa46 -+#define FSTV0910_GAINLLR_NF_QPSK_3_4 0xfa46007f -+ -+/*GAINLLR_NF8*/ -+#define RSTV0910_GAINLLR_NF8 0xfa47 -+#define FSTV0910_GAINLLR_NF_QPSK_4_5 0xfa47007f -+ -+/*GAINLLR_NF9*/ -+#define RSTV0910_GAINLLR_NF9 0xfa48 -+#define FSTV0910_GAINLLR_NF_QPSK_5_6 0xfa48007f -+ -+/*GAINLLR_NF10*/ -+#define RSTV0910_GAINLLR_NF10 0xfa49 -+#define FSTV0910_GAINLLR_NF_QPSK_8_9 0xfa49007f -+ -+/*GAINLLR_NF11*/ -+#define RSTV0910_GAINLLR_NF11 0xfa4a -+#define FSTV0910_GAINLLR_NF_QPSK_9_10 0xfa4a007f -+ -+/*GAINLLR_NF12*/ -+#define RSTV0910_GAINLLR_NF12 0xfa4b -+#define FSTV0910_GAINLLR_NF_8PSK_3_5 0xfa4b007f -+ -+/*GAINLLR_NF13*/ -+#define RSTV0910_GAINLLR_NF13 0xfa4c -+#define FSTV0910_GAINLLR_NF_8PSK_2_3 0xfa4c007f -+ -+/*GAINLLR_NF14*/ -+#define RSTV0910_GAINLLR_NF14 0xfa4d -+#define FSTV0910_GAINLLR_NF_8PSK_3_4 0xfa4d007f -+ -+/*GAINLLR_NF15*/ -+#define RSTV0910_GAINLLR_NF15 0xfa4e -+#define FSTV0910_GAINLLR_NF_8PSK_5_6 0xfa4e007f -+ -+/*GAINLLR_NF16*/ -+#define RSTV0910_GAINLLR_NF16 0xfa4f -+#define FSTV0910_GAINLLR_NF_8PSK_8_9 0xfa4f007f -+ -+/*GAINLLR_NF17*/ -+#define RSTV0910_GAINLLR_NF17 0xfa50 -+#define FSTV0910_GAINLLR_NF_8PSK_9_10 0xfa50007f -+ -+/*CFGEXT*/ -+#define RSTV0910_CFGEXT 0xfa80 -+#define FSTV0910_BYPFIFOBCH 0xfa800080 -+#define FSTV0910_BYPBCH 0xfa800040 -+#define FSTV0910_BYPLDPC 0xfa800020 -+#define FSTV0910_BYPFIFOBCHF 0xfa800010 -+#define FSTV0910_INVLLRSIGN 0xfa800008 -+#define FSTV0910_SHORTMULT 0xfa800004 -+#define FSTV0910_ENSTOPDEC 0xfa800002 -+ -+/*GENCFG*/ -+#define RSTV0910_GENCFG 0xfa86 -+#define FSTV0910_LEG_ITER 0xfa860040 -+#define FSTV0910_NOSHFRD1 0xfa860020 -+#define FSTV0910_BROADCAST 0xfa860010 -+#define FSTV0910_NOSHFRD2 0xfa860008 -+#define FSTV0910_BCHERRFLAG 0xfa860004 -+#define FSTV0910_CROSSINPUT 0xfa860002 -+#define FSTV0910_DDEMOD 0xfa860001 -+ -+/*LDPCERR1*/ -+#define RSTV0910_LDPCERR1 0xfa96 -+#define FSTV0910_LDPC_ERRORS1 0xfa9600ff -+ -+/*LDPCERR0*/ -+#define RSTV0910_LDPCERR0 0xfa97 -+#define FSTV0910_LDPC_ERRORS0 0xfa9700ff -+ -+/*BCHERR*/ -+#define RSTV0910_BCHERR 0xfa98 -+#define FSTV0910_ERRORFLAG 0xfa980010 -+#define FSTV0910_BCH_ERRORS_COUNTER 0xfa98000f -+ -+/*P1_MAXEXTRAITER*/ -+#define RSTV0910_P1_MAXEXTRAITER 0xfab1 -+#define FSTV0910_P1_MAX_EXTRA_ITER 0xfab100ff -+ -+/*P2_MAXEXTRAITER*/ -+#define RSTV0910_P2_MAXEXTRAITER 0xfab6 -+#define FSTV0910_P2_MAX_EXTRA_ITER 0xfab600ff -+ -+/*P1_STATUSITER*/ -+#define RSTV0910_P1_STATUSITER 0xfabc -+#define FSTV0910_P1_STATUS_ITER 0xfabc00ff -+ -+/*P1_STATUSMAXITER*/ -+#define RSTV0910_P1_STATUSMAXITER 0xfabd -+#define FSTV0910_P1_STATUS_MAX_ITER 0xfabd00ff -+ -+/*P2_STATUSITER*/ -+#define RSTV0910_P2_STATUSITER 0xfabe -+#define FSTV0910_P2_STATUS_ITER 0xfabe00ff -+ -+/*P2_STATUSMAXITER*/ -+#define RSTV0910_P2_STATUSMAXITER 0xfabf -+#define FSTV0910_P2_STATUS_MAX_ITER 0xfabf00ff -+ -+/*P2_NBITER_NF4*/ -+#define RSTV0910_P2_NBITER_NF4 0xfac3 -+#define FSTV0910_P2_NBITER_NF_QPSK_1_2 0xfac300ff -+ -+/*P2_NBITER_NF5*/ -+#define RSTV0910_P2_NBITER_NF5 0xfac4 -+#define FSTV0910_P2_NBITER_NF_QPSK_3_5 0xfac400ff -+ -+/*P2_NBITER_NF6*/ -+#define RSTV0910_P2_NBITER_NF6 0xfac5 -+#define FSTV0910_P2_NBITER_NF_QPSK_2_3 0xfac500ff -+ -+/*P2_NBITER_NF7*/ -+#define RSTV0910_P2_NBITER_NF7 0xfac6 -+#define FSTV0910_P2_NBITER_NF_QPSK_3_4 0xfac600ff -+ -+/*P2_NBITER_NF8*/ -+#define RSTV0910_P2_NBITER_NF8 0xfac7 -+#define FSTV0910_P2_NBITER_NF_QPSK_4_5 0xfac700ff -+ -+/*P2_NBITER_NF9*/ -+#define RSTV0910_P2_NBITER_NF9 0xfac8 -+#define FSTV0910_P2_NBITER_NF_QPSK_5_6 0xfac800ff -+ -+/*P2_NBITER_NF10*/ -+#define RSTV0910_P2_NBITER_NF10 0xfac9 -+#define FSTV0910_P2_NBITER_NF_QPSK_8_9 0xfac900ff -+ -+/*P2_NBITER_NF11*/ -+#define RSTV0910_P2_NBITER_NF11 0xfaca -+#define FSTV0910_P2_NBITER_NF_QPSK_9_10 0xfaca00ff -+ -+/*P2_NBITER_NF12*/ -+#define RSTV0910_P2_NBITER_NF12 0xfacb -+#define FSTV0910_P2_NBITER_NF_8PSK_3_5 0xfacb00ff -+ -+/*P2_NBITER_NF13*/ -+#define RSTV0910_P2_NBITER_NF13 0xfacc -+#define FSTV0910_P2_NBITER_NF_8PSK_2_3 0xfacc00ff -+ -+/*P2_NBITER_NF14*/ -+#define RSTV0910_P2_NBITER_NF14 0xfacd -+#define FSTV0910_P2_NBITER_NF_8PSK_3_4 0xfacd00ff -+ -+/*P2_NBITER_NF15*/ -+#define RSTV0910_P2_NBITER_NF15 0xface -+#define FSTV0910_P2_NBITER_NF_8PSK_5_6 0xface00ff -+ -+/*P2_NBITER_NF16*/ -+#define RSTV0910_P2_NBITER_NF16 0xfacf -+#define FSTV0910_P2_NBITER_NF_8PSK_8_9 0xfacf00ff -+ -+/*P2_NBITER_NF17*/ -+#define RSTV0910_P2_NBITER_NF17 0xfad0 -+#define FSTV0910_P2_NBITER_NF_8PSK_9_10 0xfad000ff -+ -+/*TSTRES0*/ -+#define RSTV0910_TSTRES0 0xff11 -+#define FSTV0910_FRESFEC 0xff110080 -+#define FSTV0910_FRESTS 0xff110040 -+#define FSTV0910_FRESVIT1 0xff110020 -+#define FSTV0910_FRESVIT2 0xff110010 -+#define FSTV0910_FRESSYM1 0xff110008 -+#define FSTV0910_FRESSYM2 0xff110004 -+#define FSTV0910_FRESMAS 0xff110002 -+#define FSTV0910_FRESINT 0xff110001 -+ -+/*P2_TCTL4*/ -+#define RSTV0910_P2_TCTL4 0xff28 -+#define FSTV0910_P2_CFR2TOCFR1_DVBS1 0xff2800c0 -+#define FSTV0910_P2_TSTINV_PHERR 0xff280020 -+#define FSTV0910_P2_EN_PLHCALC 0xff280010 -+#define FSTV0910_P2_TETA3L_RSTTETA3D 0xff280008 -+#define FSTV0910_P2_DIS_FORCEBETA2 0xff280004 -+#define FSTV0910_P2_CAR3_NOTRACEBACK 0xff280002 -+#define FSTV0910_P2_CAR3_NOFORWARD 0xff280001 -+ -+/*P1_TCTL4*/ -+#define RSTV0910_P1_TCTL4 0xff48 -+#define FSTV0910_P1_CFR2TOCFR1_DVBS1 0xff4800c0 -+#define FSTV0910_P1_TSTINV_PHERR 0xff480020 -+#define FSTV0910_P1_EN_PLHCALC 0xff480010 -+#define FSTV0910_P1_TETA3L_RSTTETA3D 0xff480008 -+#define FSTV0910_P1_DIS_FORCEBETA2 0xff480004 -+#define FSTV0910_P1_CAR3_NOTRACEBACK 0xff480002 -+#define FSTV0910_P1_CAR3_NOFORWARD 0xff480001 -+ -+#define STV0910_NBREGS 735 -+#define STV0910_NBFIELDS 1776 ++// @DVB-S/DVB-S2 STMicroelectronics STV0900 register defintions ++// Author Manfred Völkel, August 2013 ++// (c) 2013 Digital Devices GmbH Germany. All rights reserved ++ ++// $Id: DD_STV0910Register.h 504 2013-09-02 23:02:14Z manfred $ ++ ++/* ======================================================================= ++-- Registers Declaration (Internal ST, All Applications ) ++-- ------------------------- ++-- Each register (RSTV0910__XXXXX) is defined by its address (2 bytes). ++-- ++-- Each field (FSTV0910__XXXXX)is defined as follow: ++-- [register address -- 2bytes][field sign -- 1byte][field mask -- 1byte] ++ ======================================================================= */ ++ ++/*MID*/ ++#define RSTV0910_MID 0xf100 ++#define FSTV0910_MCHIP_IDENT 0xf10000f0 ++#define FSTV0910_MRELEASE 0xf100000f ++ ++/*DID*/ ++#define RSTV0910_DID 0xf101 ++#define FSTV0910_DEVICE_ID 0xf10100ff ++ ++/*DACR1*/ ++#define RSTV0910_DACR1 0xf113 ++#define FSTV0910_DAC_MODE 0xf11300e0 ++#define FSTV0910_DAC_VALUE1 0xf113000f ++ ++/*DACR2*/ ++#define RSTV0910_DACR2 0xf114 ++#define FSTV0910_DAC_VALUE0 0xf11400ff ++ ++/*PADCFG*/ ++#define RSTV0910_PADCFG 0xf11a ++#define FSTV0910_AGCRF2_OPD 0xf11a0008 ++#define FSTV0910_AGCRF2_XOR 0xf11a0004 ++#define FSTV0910_AGCRF1_OPD 0xf11a0002 ++#define FSTV0910_AGCRF1_XOR 0xf11a0001 ++ ++/*OUTCFG2*/ ++#define RSTV0910_OUTCFG2 0xf11b ++#define FSTV0910_TS2_ERROR_XOR 0xf11b0080 ++#define FSTV0910_TS2_DPN_XOR 0xf11b0040 ++#define FSTV0910_TS2_STROUT_XOR 0xf11b0020 ++#define FSTV0910_TS2_CLOCKOUT_XOR 0xf11b0010 ++#define FSTV0910_TS1_ERROR_XOR 0xf11b0008 ++#define FSTV0910_TS1_DPN_XOR 0xf11b0004 ++#define FSTV0910_TS1_STROUT_XOR 0xf11b0002 ++#define FSTV0910_TS1_CLOCKOUT_XOR 0xf11b0001 ++ ++/*OUTCFG*/ ++#define RSTV0910_OUTCFG 0xf11c ++#define FSTV0910_INV_DATA6 0xf11c0080 ++#define FSTV0910_TS2_OUTSER_HZ 0xf11c0020 ++#define FSTV0910_TS1_OUTSER_HZ 0xf11c0010 ++#define FSTV0910_TS2_OUTPAR_HZ 0xf11c0008 ++#define FSTV0910_TS1_OUTPAR_HZ 0xf11c0004 ++#define FSTV0910_TS_SERDATA0 0xf11c0002 ++ ++/*IRQSTATUS3*/ ++#define RSTV0910_IRQSTATUS3 0xf120 ++#define FSTV0910_SPLL_LOCK 0xf1200020 ++#define FSTV0910_SSTREAM_LCK_1 0xf1200010 ++#define FSTV0910_SSTREAM_LCK_2 0xf1200008 ++#define FSTV0910_SDVBS1_PRF_2 0xf1200002 ++#define FSTV0910_SDVBS1_PRF_1 0xf1200001 ++ ++/*IRQSTATUS2*/ ++#define RSTV0910_IRQSTATUS2 0xf121 ++#define FSTV0910_SSPY_ENDSIM_1 0xf1210080 ++#define FSTV0910_SSPY_ENDSIM_2 0xf1210040 ++#define FSTV0910_SPKTDEL_ERROR_2 0xf1210010 ++#define FSTV0910_SPKTDEL_LOCKB_2 0xf1210008 ++#define FSTV0910_SPKTDEL_LOCK_2 0xf1210004 ++#define FSTV0910_SPKTDEL_ERROR_1 0xf1210002 ++#define FSTV0910_SPKTDEL_LOCKB_1 0xf1210001 ++ ++/*IRQSTATUS1*/ ++#define RSTV0910_IRQSTATUS1 0xf122 ++#define FSTV0910_SPKTDEL_LOCK_1 0xf1220080 ++#define FSTV0910_SFEC_LOCKB_2 0xf1220040 ++#define FSTV0910_SFEC_LOCK_2 0xf1220020 ++#define FSTV0910_SFEC_LOCKB_1 0xf1220010 ++#define FSTV0910_SFEC_LOCK_1 0xf1220008 ++#define FSTV0910_SDEMOD_LOCKB_2 0xf1220004 ++#define FSTV0910_SDEMOD_LOCK_2 0xf1220002 ++#define FSTV0910_SDEMOD_IRQ_2 0xf1220001 ++ ++/*IRQSTATUS0*/ ++#define RSTV0910_IRQSTATUS0 0xf123 ++#define FSTV0910_SDEMOD_LOCKB_1 0xf1230080 ++#define FSTV0910_SDEMOD_LOCK_1 0xf1230040 ++#define FSTV0910_SDEMOD_IRQ_1 0xf1230020 ++#define FSTV0910_SBCH_ERRFLAG 0xf1230010 ++#define FSTV0910_SECW2_IRQ 0xf1230008 ++#define FSTV0910_SDISEQC2_IRQ 0xf1230004 ++#define FSTV0910_SECW1_IRQ 0xf1230002 ++#define FSTV0910_SDISEQC1_IRQ 0xf1230001 ++ ++/*IRQMASK3*/ ++#define RSTV0910_IRQMASK3 0xf124 ++#define FSTV0910_MPLL_LOCK 0xf1240020 ++#define FSTV0910_MSTREAM_LCK_1 0xf1240010 ++#define FSTV0910_MSTREAM_LCK_2 0xf1240008 ++#define FSTV0910_MDVBS1_PRF_2 0xf1240002 ++#define FSTV0910_MDVBS1_PRF_1 0xf1240001 ++ ++/*IRQMASK2*/ ++#define RSTV0910_IRQMASK2 0xf125 ++#define FSTV0910_MSPY_ENDSIM_1 0xf1250080 ++#define FSTV0910_MSPY_ENDSIM_2 0xf1250040 ++#define FSTV0910_MPKTDEL_ERROR_2 0xf1250010 ++#define FSTV0910_MPKTDEL_LOCKB_2 0xf1250008 ++#define FSTV0910_MPKTDEL_LOCK_2 0xf1250004 ++#define FSTV0910_MPKTDEL_ERROR_1 0xf1250002 ++#define FSTV0910_MPKTDEL_LOCKB_1 0xf1250001 ++ ++/*IRQMASK1*/ ++#define RSTV0910_IRQMASK1 0xf126 ++#define FSTV0910_MPKTDEL_LOCK_1 0xf1260080 ++#define FSTV0910_MFEC_LOCKB_2 0xf1260040 ++#define FSTV0910_MFEC_LOCK_2 0xf1260020 ++#define FSTV0910_MFEC_LOCKB_1 0xf1260010 ++#define FSTV0910_MFEC_LOCK_1 0xf1260008 ++#define FSTV0910_MDEMOD_LOCKB_2 0xf1260004 ++#define FSTV0910_MDEMOD_LOCK_2 0xf1260002 ++#define FSTV0910_MDEMOD_IRQ_2 0xf1260001 ++ ++/*IRQMASK0*/ ++#define RSTV0910_IRQMASK0 0xf127 ++#define FSTV0910_MDEMOD_LOCKB_1 0xf1270080 ++#define FSTV0910_MDEMOD_LOCK_1 0xf1270040 ++#define FSTV0910_MDEMOD_IRQ_1 0xf1270020 ++#define FSTV0910_MBCH_ERRFLAG 0xf1270010 ++#define FSTV0910_MECW2_IRQ 0xf1270008 ++#define FSTV0910_MDISEQC2_IRQ 0xf1270004 ++#define FSTV0910_MECW1_IRQ 0xf1270002 ++#define FSTV0910_MDISEQC1_IRQ 0xf1270001 ++ ++/*I2CCFG*/ ++#define RSTV0910_I2CCFG 0xf129 ++#define FSTV0910_I2C2_FASTMODE 0xf1290080 ++#define FSTV0910_STATUS_WR2 0xf1290040 ++#define FSTV0910_I2C2ADDR_INC 0xf1290030 ++#define FSTV0910_I2C_FASTMODE 0xf1290008 ++#define FSTV0910_STATUS_WR 0xf1290004 ++#define FSTV0910_I2CADDR_INC 0xf1290003 ++ ++/*P1_I2CRPT*/ ++#define RSTV0910_P1_I2CRPT 0xf12a ++#define FSTV0910_P1_I2CT_ON 0xf12a0080 ++#define FSTV0910_P1_ENARPT_LEVEL 0xf12a0070 ++#define FSTV0910_P1_SCLT_DELAY 0xf12a0008 ++#define FSTV0910_P1_STOP_ENABLE 0xf12a0004 ++#define FSTV0910_P1_STOP_SDAT2SDA 0xf12a0002 ++ ++/*P2_I2CRPT*/ ++#define RSTV0910_P2_I2CRPT 0xf12b ++#define FSTV0910_P2_I2CT_ON 0xf12b0080 ++#define FSTV0910_P2_ENARPT_LEVEL 0xf12b0070 ++#define FSTV0910_P2_SCLT_DELAY 0xf12b0008 ++#define FSTV0910_P2_STOP_ENABLE 0xf12b0004 ++#define FSTV0910_P2_STOP_SDAT2SDA 0xf12b0002 ++ ++/*GPIO0CFG*/ ++#define RSTV0910_GPIO0CFG 0xf140 ++#define FSTV0910_GPIO0_OPD 0xf1400080 ++#define FSTV0910_GPIO0_CONFIG 0xf140007e ++#define FSTV0910_GPIO0_XOR 0xf1400001 ++ ++/*GPIO1CFG*/ ++#define RSTV0910_GPIO1CFG 0xf141 ++#define FSTV0910_GPIO1_OPD 0xf1410080 ++#define FSTV0910_GPIO1_CONFIG 0xf141007e ++#define FSTV0910_GPIO1_XOR 0xf1410001 ++ ++/*GPIO2CFG*/ ++#define RSTV0910_GPIO2CFG 0xf142 ++#define FSTV0910_GPIO2_OPD 0xf1420080 ++#define FSTV0910_GPIO2_CONFIG 0xf142007e ++#define FSTV0910_GPIO2_XOR 0xf1420001 ++ ++/*GPIO3CFG*/ ++#define RSTV0910_GPIO3CFG 0xf143 ++#define FSTV0910_GPIO3_OPD 0xf1430080 ++#define FSTV0910_GPIO3_CONFIG 0xf143007e ++#define FSTV0910_GPIO3_XOR 0xf1430001 ++ ++/*GPIO4CFG*/ ++#define RSTV0910_GPIO4CFG 0xf144 ++#define FSTV0910_GPIO4_OPD 0xf1440080 ++#define FSTV0910_GPIO4_CONFIG 0xf144007e ++#define FSTV0910_GPIO4_XOR 0xf1440001 ++ ++/*GPIO5CFG*/ ++#define RSTV0910_GPIO5CFG 0xf145 ++#define FSTV0910_GPIO5_OPD 0xf1450080 ++#define FSTV0910_GPIO5_CONFIG 0xf145007e ++#define FSTV0910_GPIO5_XOR 0xf1450001 ++ ++/*GPIO6CFG*/ ++#define RSTV0910_GPIO6CFG 0xf146 ++#define FSTV0910_GPIO6_OPD 0xf1460080 ++#define FSTV0910_GPIO6_CONFIG 0xf146007e ++#define FSTV0910_GPIO6_XOR 0xf1460001 ++ ++/*GPIO7CFG*/ ++#define RSTV0910_GPIO7CFG 0xf147 ++#define FSTV0910_GPIO7_OPD 0xf1470080 ++#define FSTV0910_GPIO7_CONFIG 0xf147007e ++#define FSTV0910_GPIO7_XOR 0xf1470001 ++ ++/*GPIO8CFG*/ ++#define RSTV0910_GPIO8CFG 0xf148 ++#define FSTV0910_GPIO8_OPD 0xf1480080 ++#define FSTV0910_GPIO8_CONFIG 0xf148007e ++#define FSTV0910_GPIO8_XOR 0xf1480001 ++ ++/*GPIO9CFG*/ ++#define RSTV0910_GPIO9CFG 0xf149 ++#define FSTV0910_GPIO9_OPD 0xf1490080 ++#define FSTV0910_GPIO9_CONFIG 0xf149007e ++#define FSTV0910_GPIO9_XOR 0xf1490001 ++ ++/*GPIO10CFG*/ ++#define RSTV0910_GPIO10CFG 0xf14a ++#define FSTV0910_GPIO10_OPD 0xf14a0080 ++#define FSTV0910_GPIO10_CONFIG 0xf14a007e ++#define FSTV0910_GPIO10_XOR 0xf14a0001 ++ ++/*GPIO11CFG*/ ++#define RSTV0910_GPIO11CFG 0xf14b ++#define FSTV0910_GPIO11_OPD 0xf14b0080 ++#define FSTV0910_GPIO11_CONFIG 0xf14b007e ++#define FSTV0910_GPIO11_XOR 0xf14b0001 ++ ++/*GPIO12CFG*/ ++#define RSTV0910_GPIO12CFG 0xf14c ++#define FSTV0910_GPIO12_OPD 0xf14c0080 ++#define FSTV0910_GPIO12_CONFIG 0xf14c007e ++#define FSTV0910_GPIO12_XOR 0xf14c0001 ++ ++/*GPIO13CFG*/ ++#define RSTV0910_GPIO13CFG 0xf14d ++#define FSTV0910_GPIO13_OPD 0xf14d0080 ++#define FSTV0910_GPIO13_CONFIG 0xf14d007e ++#define FSTV0910_GPIO13_XOR 0xf14d0001 ++ ++/*GPIO14CFG*/ ++#define RSTV0910_GPIO14CFG 0xf14e ++#define FSTV0910_GPIO14_OPD 0xf14e0080 ++#define FSTV0910_GPIO14_CONFIG 0xf14e007e ++#define FSTV0910_GPIO14_XOR 0xf14e0001 ++ ++/*GPIO15CFG*/ ++#define RSTV0910_GPIO15CFG 0xf14f ++#define FSTV0910_GPIO15_OPD 0xf14f0080 ++#define FSTV0910_GPIO15_CONFIG 0xf14f007e ++#define FSTV0910_GPIO15_XOR 0xf14f0001 ++ ++/*GPIO16CFG*/ ++#define RSTV0910_GPIO16CFG 0xf150 ++#define FSTV0910_GPIO16_OPD 0xf1500080 ++#define FSTV0910_GPIO16_CONFIG 0xf150007e ++#define FSTV0910_GPIO16_XOR 0xf1500001 ++ ++/*GPIO17CFG*/ ++#define RSTV0910_GPIO17CFG 0xf151 ++#define FSTV0910_GPIO17_OPD 0xf1510080 ++#define FSTV0910_GPIO17_CONFIG 0xf151007e ++#define FSTV0910_GPIO17_XOR 0xf1510001 ++ ++/*GPIO18CFG*/ ++#define RSTV0910_GPIO18CFG 0xf152 ++#define FSTV0910_GPIO18_OPD 0xf1520080 ++#define FSTV0910_GPIO18_CONFIG 0xf152007e ++#define FSTV0910_GPIO18_XOR 0xf1520001 ++ ++/*GPIO19CFG*/ ++#define RSTV0910_GPIO19CFG 0xf153 ++#define FSTV0910_GPIO19_OPD 0xf1530080 ++#define FSTV0910_GPIO19_CONFIG 0xf153007e ++#define FSTV0910_GPIO19_XOR 0xf1530001 ++ ++/*GPIO20CFG*/ ++#define RSTV0910_GPIO20CFG 0xf154 ++#define FSTV0910_GPIO20_OPD 0xf1540080 ++#define FSTV0910_GPIO20_CONFIG 0xf154007e ++#define FSTV0910_GPIO20_XOR 0xf1540001 ++ ++/*GPIO21CFG*/ ++#define RSTV0910_GPIO21CFG 0xf155 ++#define FSTV0910_GPIO21_OPD 0xf1550080 ++#define FSTV0910_GPIO21_CONFIG 0xf155007e ++#define FSTV0910_GPIO21_XOR 0xf1550001 ++ ++/*GPIO22CFG*/ ++#define RSTV0910_GPIO22CFG 0xf156 ++#define FSTV0910_GPIO22_OPD 0xf1560080 ++#define FSTV0910_GPIO22_CONFIG 0xf156007e ++#define FSTV0910_GPIO22_XOR 0xf1560001 ++ ++/*STRSTATUS1*/ ++#define RSTV0910_STRSTATUS1 0xf16a ++#define FSTV0910_STRSTATUS_SEL2 0xf16a00f0 ++#define FSTV0910_STRSTATUS_SEL1 0xf16a000f ++ ++/*STRSTATUS2*/ ++#define RSTV0910_STRSTATUS2 0xf16b ++#define FSTV0910_STRSTATUS_SEL4 0xf16b00f0 ++#define FSTV0910_STRSTATUS_SEL3 0xf16b000f ++ ++/*STRSTATUS3*/ ++#define RSTV0910_STRSTATUS3 0xf16c ++#define FSTV0910_STRSTATUS_SEL6 0xf16c00f0 ++#define FSTV0910_STRSTATUS_SEL5 0xf16c000f ++ ++/*FSKTFC2*/ ++#define RSTV0910_FSKTFC2 0xf170 ++#define FSTV0910_FSKT_KMOD 0xf17000fc ++#define FSTV0910_FSKT_CAR2 0xf1700003 ++ ++/*FSKTFC1*/ ++#define RSTV0910_FSKTFC1 0xf171 ++#define FSTV0910_FSKT_CAR1 0xf17100ff ++ ++/*FSKTFC0*/ ++#define RSTV0910_FSKTFC0 0xf172 ++#define FSTV0910_FSKT_CAR0 0xf17200ff ++ ++/*FSKTDELTAF1*/ ++#define RSTV0910_FSKTDELTAF1 0xf173 ++#define FSTV0910_FSKT_DELTAF1 0xf173000f ++ ++/*FSKTDELTAF0*/ ++#define RSTV0910_FSKTDELTAF0 0xf174 ++#define FSTV0910_FSKT_DELTAF0 0xf17400ff ++ ++/*FSKTCTRL*/ ++#define RSTV0910_FSKTCTRL 0xf175 ++#define FSTV0910_FSKT_PINSEL 0xf1750080 ++#define FSTV0910_FSKT_EN_SGN 0xf1750040 ++#define FSTV0910_FSKT_MOD_SGN 0xf1750020 ++#define FSTV0910_FSKT_MOD_EN 0xf175001c ++#define FSTV0910_FSKT_DACMODE 0xf1750003 ++ ++/*FSKRFC2*/ ++#define RSTV0910_FSKRFC2 0xf176 ++#define FSTV0910_FSKR_DETSGN 0xf1760040 ++#define FSTV0910_FSKR_OUTSGN 0xf1760020 ++#define FSTV0910_FSKR_KAGC 0xf176001c ++#define FSTV0910_FSKR_CAR2 0xf1760003 ++ ++/*FSKRFC1*/ ++#define RSTV0910_FSKRFC1 0xf177 ++#define FSTV0910_FSKR_CAR1 0xf17700ff ++ ++/*FSKRFC0*/ ++#define RSTV0910_FSKRFC0 0xf178 ++#define FSTV0910_FSKR_CAR0 0xf17800ff ++ ++/*FSKRK1*/ ++#define RSTV0910_FSKRK1 0xf179 ++#define FSTV0910_FSKR_K1_EXP 0xf17900e0 ++#define FSTV0910_FSKR_K1_MANT 0xf179001f ++ ++/*FSKRK2*/ ++#define RSTV0910_FSKRK2 0xf17a ++#define FSTV0910_FSKR_K2_EXP 0xf17a00e0 ++#define FSTV0910_FSKR_K2_MANT 0xf17a001f ++ ++/*FSKRAGCR*/ ++#define RSTV0910_FSKRAGCR 0xf17b ++#define FSTV0910_FSKR_OUTCTL 0xf17b00c0 ++#define FSTV0910_FSKR_AGC_REF 0xf17b003f ++ ++/*FSKRAGC*/ ++#define RSTV0910_FSKRAGC 0xf17c ++#define FSTV0910_FSKR_AGC_ACCU 0xf17c00ff ++ ++/*FSKRALPHA*/ ++#define RSTV0910_FSKRALPHA 0xf17d ++#define FSTV0910_FSKR_ALPHA_EXP 0xf17d001c ++#define FSTV0910_FSKR_ALPHA_M 0xf17d0003 ++ ++/*FSKRPLTH1*/ ++#define RSTV0910_FSKRPLTH1 0xf17e ++#define FSTV0910_FSKR_BETA 0xf17e00f0 ++#define FSTV0910_FSKR_PLL_TRESH1 0xf17e000f ++ ++/*FSKRPLTH0*/ ++#define RSTV0910_FSKRPLTH0 0xf17f ++#define FSTV0910_FSKR_PLL_TRESH0 0xf17f00ff ++ ++/*FSKRDF1*/ ++#define RSTV0910_FSKRDF1 0xf180 ++#define FSTV0910_FSKR_OUT 0xf1800080 ++#define FSTV0910_FSKR_STATE 0xf1800060 ++#define FSTV0910_FSKR_DELTAF1 0xf180001f ++ ++/*FSKRDF0*/ ++#define RSTV0910_FSKRDF0 0xf181 ++#define FSTV0910_FSKR_DELTAF0 0xf18100ff ++ ++/*FSKRSTEPP*/ ++#define RSTV0910_FSKRSTEPP 0xf182 ++#define FSTV0910_FSKR_STEP_PLUS 0xf18200ff ++ ++/*FSKRSTEPM*/ ++#define RSTV0910_FSKRSTEPM 0xf183 ++#define FSTV0910_FSKR_STEP_MINUS 0xf18300ff ++ ++/*FSKRDET1*/ ++#define RSTV0910_FSKRDET1 0xf184 ++#define FSTV0910_FSKR_DETECT 0xf1840080 ++#define FSTV0910_FSKR_CARDET_ACCU1 0xf184000f ++ ++/*FSKRDET0*/ ++#define RSTV0910_FSKRDET0 0xf185 ++#define FSTV0910_FSKR_CARDET_ACCU0 0xf18500ff ++ ++/*FSKRDTH1*/ ++#define RSTV0910_FSKRDTH1 0xf186 ++#define FSTV0910_FSKR_CARLOSS_THRESH1 0xf18600f0 ++#define FSTV0910_FSKR_CARDET_THRESH1 0xf186000f ++ ++/*FSKRDTH0*/ ++#define RSTV0910_FSKRDTH0 0xf187 ++#define FSTV0910_FSKR_CARDET_THRESH0 0xf18700ff ++ ++/*FSKRLOSS*/ ++#define RSTV0910_FSKRLOSS 0xf188 ++#define FSTV0910_FSKR_CARLOSS_THRESH0 0xf18800ff ++ ++/*NCOARSE*/ ++#define RSTV0910_NCOARSE 0xf1b3 ++#define FSTV0910_CP 0xf1b300f8 ++#define FSTV0910_IDF 0xf1b30007 ++ ++/*NCOARSE1*/ ++#define RSTV0910_NCOARSE1 0xf1b4 ++#define FSTV0910_N_DIV 0xf1b400ff ++ ++/*NCOARSE2*/ ++#define RSTV0910_NCOARSE2 0xf1b5 ++#define FSTV0910_ODF 0xf1b5003f ++ ++/*SYNTCTRL*/ ++#define RSTV0910_SYNTCTRL 0xf1b6 ++#define FSTV0910_STANDBY 0xf1b60080 ++#define FSTV0910_BYPASSPLLCORE 0xf1b60040 ++#define FSTV0910_STOP_PLL 0xf1b60008 ++#define FSTV0910_OSCI_E 0xf1b60002 ++ ++/*FILTCTRL*/ ++#define RSTV0910_FILTCTRL 0xf1b7 ++#define FSTV0910_INV_CLKFSK 0xf1b70002 ++#define FSTV0910_BYPASS_APPLI 0xf1b70001 ++ ++/*PLLSTAT*/ ++#define RSTV0910_PLLSTAT 0xf1b8 ++#define FSTV0910_PLL_BIST_END 0xf1b80004 ++#define FSTV0910_PLLLOCK 0xf1b80001 ++ ++/*STOPCLK1*/ ++#define RSTV0910_STOPCLK1 0xf1c2 ++#define FSTV0910_INV_CLKADCI2 0xf1c20004 ++#define FSTV0910_INV_CLKADCI1 0xf1c20001 ++ ++/*STOPCLK2*/ ++#define RSTV0910_STOPCLK2 0xf1c3 ++#define FSTV0910_STOP_DVBS2FEC2 0xf1c30020 ++#define FSTV0910_STOP_DVBS2FEC 0xf1c30010 ++#define FSTV0910_STOP_DVBS1FEC2 0xf1c30008 ++#define FSTV0910_STOP_DVBS1FEC 0xf1c30004 ++#define FSTV0910_STOP_DEMOD2 0xf1c30002 ++#define FSTV0910_STOP_DEMOD 0xf1c30001 ++ ++/*PREGCTL*/ ++#define RSTV0910_PREGCTL 0xf1c8 ++#define FSTV0910_REG3V3TO2V5_POFF 0xf1c80080 ++ ++/*TSTTNR0*/ ++#define RSTV0910_TSTTNR0 0xf1df ++#define FSTV0910_FSK_PON 0xf1df0004 ++#define FSTV0910_FSK_OPENLOOP 0xf1df0002 ++ ++/*TSTTNR1*/ ++#define RSTV0910_TSTTNR1 0xf1e0 ++#define FSTV0910_BYPASS_ADC1 0xf1e00080 ++#define FSTV0910_INVADC1_CKOUT 0xf1e00040 ++#define FSTV0910_SELIQSRC1 0xf1e00030 ++#define FSTV0910_DEMOD2_SELADC 0xf1e00008 ++#define FSTV0910_DEMOD1_SELADC 0xf1e00004 ++#define FSTV0910_ADC1_PON 0xf1e00002 ++ ++/*TSTTNR2*/ ++#define RSTV0910_TSTTNR2 0xf1e1 ++#define FSTV0910_I2C_DISEQC_BYPASS 0xf1e10080 ++#define FSTV0910_I2C_DISEQC_ENCH 0xf1e10040 ++#define FSTV0910_I2C_DISEQC_PON 0xf1e10020 ++#define FSTV0910_DISEQC_CLKDIV 0xf1e1000f ++ ++/*TSTTNR3*/ ++#define RSTV0910_TSTTNR3 0xf1e2 ++#define FSTV0910_BYPASS_ADC2 0xf1e20080 ++#define FSTV0910_INVADC2_CKOUT 0xf1e20040 ++#define FSTV0910_SELIQSRC2 0xf1e20030 ++#define FSTV0910_ADC2_PON 0xf1e20002 ++ ++/*P2_IQCONST*/ ++#define RSTV0910_P2_IQCONST 0xf200 ++#define FSTV0910_P2_CONSTEL_SELECT 0xf2000060 ++#define FSTV0910_P2_IQSYMB_SEL 0xf200001f ++ ++/*P2_NOSCFG*/ ++#define RSTV0910_P2_NOSCFG 0xf201 ++#define FSTV0910_P2_DIS_ACMRATIO 0xf2010080 ++#define FSTV0910_P2_NOSIN_EGALSEL 0xf2010040 ++#define FSTV0910_P2_DUMMYPL_NOSDATA 0xf2010020 ++#define FSTV0910_P2_NOSPLH_BETA 0xf2010018 ++#define FSTV0910_P2_NOSDATA_BETA 0xf2010007 ++ ++/*P2_ISYMB*/ ++#define RSTV0910_P2_ISYMB 0xf202 ++#define FSTV0910_P2_I_SYMBOL 0xf20201ff ++ ++/*P2_QSYMB*/ ++#define RSTV0910_P2_QSYMB 0xf203 ++#define FSTV0910_P2_Q_SYMBOL 0xf20301ff ++ ++/*P2_AGC1CFG*/ ++#define RSTV0910_P2_AGC1CFG 0xf204 ++#define FSTV0910_P2_DC_FROZEN 0xf2040080 ++#define FSTV0910_P2_DC_CORRECT 0xf2040040 ++#define FSTV0910_P2_AMM_FROZEN 0xf2040020 ++#define FSTV0910_P2_AMM_CORRECT 0xf2040010 ++#define FSTV0910_P2_QUAD_FROZEN 0xf2040008 ++#define FSTV0910_P2_QUAD_CORRECT 0xf2040004 ++#define FSTV0910_P2_DCCOMP_SLOW 0xf2040002 ++#define FSTV0910_P2_IQMISM_SLOW 0xf2040001 ++ ++/*P2_AGC1CN*/ ++#define RSTV0910_P2_AGC1CN 0xf206 ++#define FSTV0910_P2_AGC1_LOCKED 0xf2060080 ++#define FSTV0910_P2_AGC1_OVERFLOW 0xf2060040 ++#define FSTV0910_P2_AGC1_NOSLOWLK 0xf2060020 ++#define FSTV0910_P2_AGC1_MINPOWER 0xf2060010 ++#define FSTV0910_P2_AGCOUT_FAST 0xf2060008 ++#define FSTV0910_P2_AGCIQ_BETA 0xf2060007 ++ ++/*P2_AGC1REF*/ ++#define RSTV0910_P2_AGC1REF 0xf207 ++#define FSTV0910_P2_AGCIQ_REF 0xf20700ff ++ ++/*P2_IDCCOMP*/ ++#define RSTV0910_P2_IDCCOMP 0xf208 ++#define FSTV0910_P2_IAVERAGE_ADJ 0xf20801ff ++ ++/*P2_QDCCOMP*/ ++#define RSTV0910_P2_QDCCOMP 0xf209 ++#define FSTV0910_P2_QAVERAGE_ADJ 0xf20901ff ++ ++/*P2_POWERI*/ ++#define RSTV0910_P2_POWERI 0xf20a ++#define FSTV0910_P2_POWER_I 0xf20a00ff ++ ++/*P2_POWERQ*/ ++#define RSTV0910_P2_POWERQ 0xf20b ++#define FSTV0910_P2_POWER_Q 0xf20b00ff ++ ++/*P2_AGC1AMM*/ ++#define RSTV0910_P2_AGC1AMM 0xf20c ++#define FSTV0910_P2_AMM_VALUE 0xf20c00ff ++ ++/*P2_AGC1QUAD*/ ++#define RSTV0910_P2_AGC1QUAD 0xf20d ++#define FSTV0910_P2_QUAD_VALUE 0xf20d01ff ++ ++/*P2_AGCIQIN1*/ ++#define RSTV0910_P2_AGCIQIN1 0xf20e ++#define FSTV0910_P2_AGCIQ_VALUE1 0xf20e00ff ++ ++/*P2_AGCIQIN0*/ ++#define RSTV0910_P2_AGCIQIN0 0xf20f ++#define FSTV0910_P2_AGCIQ_VALUE0 0xf20f00ff ++ ++/*P2_DEMOD*/ ++#define RSTV0910_P2_DEMOD 0xf210 ++#define FSTV0910_P2_MANUALS2_ROLLOFF 0xf2100080 ++#define FSTV0910_P2_SPECINV_CONTROL 0xf2100030 ++#define FSTV0910_P2_MANUALSX_ROLLOFF 0xf2100004 ++#define FSTV0910_P2_ROLLOFF_CONTROL 0xf2100003 ++ ++/*P2_DMDMODCOD*/ ++#define RSTV0910_P2_DMDMODCOD 0xf211 ++#define FSTV0910_P2_MANUAL_MODCOD 0xf2110080 ++#define FSTV0910_P2_DEMOD_MODCOD 0xf211007c ++#define FSTV0910_P2_DEMOD_TYPE 0xf2110003 ++ ++/*P2_DSTATUS*/ ++#define RSTV0910_P2_DSTATUS 0xf212 ++#define FSTV0910_P2_CAR_LOCK 0xf2120080 ++#define FSTV0910_P2_TMGLOCK_QUALITY 0xf2120060 ++#define FSTV0910_P2_SDVBS1_ENABLE 0xf2120010 ++#define FSTV0910_P2_LOCK_DEFINITIF 0xf2120008 ++#define FSTV0910_P2_TIMING_IS_LOCKED 0xf2120004 ++#define FSTV0910_P2_DEMOD_SYSCFG 0xf2120002 ++#define FSTV0910_P2_OVADC_DETECT 0xf2120001 ++ ++/*P2_DSTATUS2*/ ++#define RSTV0910_P2_DSTATUS2 0xf213 ++#define FSTV0910_P2_DEMOD_DELOCK 0xf2130080 ++#define FSTV0910_P2_DEMOD_TIMEOUT 0xf2130040 ++#define FSTV0910_P2_MODCODRQ_SYNCTAG 0xf2130020 ++#define FSTV0910_P2_POLYPH_SATEVENT 0xf2130010 ++#define FSTV0910_P2_AGC1_NOSIGNALACK 0xf2130008 ++#define FSTV0910_P2_AGC2_OVERFLOW 0xf2130004 ++#define FSTV0910_P2_CFR_OVERFLOW 0xf2130002 ++#define FSTV0910_P2_GAMMA_OVERUNDER 0xf2130001 ++ ++/*P2_DMDCFGMD*/ ++#define RSTV0910_P2_DMDCFGMD 0xf214 ++#define FSTV0910_P2_DVBS2_ENABLE 0xf2140080 ++#define FSTV0910_P2_DVBS1_ENABLE 0xf2140040 ++#define FSTV0910_P2_SCAN_ENABLE 0xf2140010 ++#define FSTV0910_P2_CFR_AUTOSCAN 0xf2140008 ++#define FSTV0910_P2_NOFORCE_RELOCK 0xf2140004 ++#define FSTV0910_P2_TUN_RNG 0xf2140003 ++ ++/*P2_DMDCFG2*/ ++#define RSTV0910_P2_DMDCFG2 0xf215 ++#define FSTV0910_P2_AGC1_WAITLOCK 0xf2150080 ++#define FSTV0910_P2_S1S2_SEQUENTIAL 0xf2150040 ++#define FSTV0910_P2_BLINDPEA_MODE 0xf2150020 ++#define FSTV0910_P2_INFINITE_RELOCK 0xf2150010 ++#define FSTV0910_P2_BWOFFSET_COLDWARM 0xf2150008 ++#define FSTV0910_P2_TMGLOCK_NSCANSTOP 0xf2150004 ++#define FSTV0910_P2_COARSE_LK3MODE 0xf2150002 ++#define FSTV0910_P2_COARSE_LK2MODE 0xf2150001 ++ ++/*P2_DMDISTATE*/ ++#define RSTV0910_P2_DMDISTATE 0xf216 ++#define FSTV0910_P2_I2C_NORESETDMODE 0xf2160080 ++#define FSTV0910_P2_FORCE_ETAPED 0xf2160040 ++#define FSTV0910_P2_SDMDRST_DIRCLK 0xf2160020 ++#define FSTV0910_P2_I2C_DEMOD_MODE 0xf216001f ++ ++/*P2_DMDT0M*/ ++#define RSTV0910_P2_DMDT0M 0xf217 ++#define FSTV0910_P2_DMDT0_MIN 0xf21700ff ++ ++/*P2_DMDSTATE*/ ++#define RSTV0910_P2_DMDSTATE 0xf21b ++#define FSTV0910_P2_DEMOD_LOCKED 0xf21b0080 ++#define FSTV0910_P2_HEADER_MODE 0xf21b0060 ++#define FSTV0910_P2_DEMOD_MODE 0xf21b001f ++ ++/*P2_DMDFLYW*/ ++#define RSTV0910_P2_DMDFLYW 0xf21c ++#define FSTV0910_P2_I2C_IRQVAL 0xf21c00f0 ++#define FSTV0910_P2_FLYWHEEL_CPT 0xf21c000f ++ ++/*P2_DSTATUS3*/ ++#define RSTV0910_P2_DSTATUS3 0xf21d ++#define FSTV0910_P2_CFR_ZIGZAG 0xf21d0080 ++#define FSTV0910_P2_DEMOD_CFGMODE 0xf21d0060 ++#define FSTV0910_P2_GAMMA_LOWBAUDRATE 0xf21d0010 ++#define FSTV0910_P2_RELOCK_MODE 0xf21d0008 ++#define FSTV0910_P2_DEMOD_FAIL 0xf21d0004 ++#define FSTV0910_P2_ETAPE1A_DVBXMEM 0xf21d0003 ++ ++/*P2_DMDCFG3*/ ++#define RSTV0910_P2_DMDCFG3 0xf21e ++#define FSTV0910_P2_DVBS1_TMGWAIT 0xf21e0080 ++#define FSTV0910_P2_NO_BWCENTERING 0xf21e0040 ++#define FSTV0910_P2_INV_SEQSRCH 0xf21e0020 ++#define FSTV0910_P2_DIS_SFRUPLOW_TRK 0xf21e0010 ++#define FSTV0910_P2_NOSTOP_FIFOFULL 0xf21e0008 ++#define FSTV0910_P2_LOCKTIME_MODE 0xf21e0007 ++ ++/*P2_DMDCFG4*/ ++#define RSTV0910_P2_DMDCFG4 0xf21f ++#define FSTV0910_P2_DIS_VITLOCK 0xf21f0080 ++#define FSTV0910_P2_S1S2TOUT_FAST 0xf21f0040 ++#define FSTV0910_P2_DEMOD_FASTLOCK 0xf21f0020 ++#define FSTV0910_P2_S1HIER_ENABLE 0xf21f0010 ++#define FSTV0910_P2_TUNER_NRELAUNCH 0xf21f0008 ++#define FSTV0910_P2_DIS_CLKENABLE 0xf21f0004 ++#define FSTV0910_P2_DIS_HDRDIVLOCK 0xf21f0002 ++#define FSTV0910_P2_NO_TNRWBINIT 0xf21f0001 ++ ++/*P2_CORRELMANT*/ ++#define RSTV0910_P2_CORRELMANT 0xf220 ++#define FSTV0910_P2_CORREL_MANT 0xf22000ff ++ ++/*P2_CORRELABS*/ ++#define RSTV0910_P2_CORRELABS 0xf221 ++#define FSTV0910_P2_CORREL_ABS 0xf22100ff ++ ++/*P2_CORRELEXP*/ ++#define RSTV0910_P2_CORRELEXP 0xf222 ++#define FSTV0910_P2_CORREL_ABSEXP 0xf22200f0 ++#define FSTV0910_P2_CORREL_EXP 0xf222000f ++ ++/*P2_PLHMODCOD*/ ++#define RSTV0910_P2_PLHMODCOD 0xf224 ++#define FSTV0910_P2_SPECINV_DEMOD 0xf2240080 ++#define FSTV0910_P2_PLH_MODCOD 0xf224007c ++#define FSTV0910_P2_PLH_TYPE 0xf2240003 ++ ++/*P2_DMDREG*/ ++#define RSTV0910_P2_DMDREG 0xf225 ++#define FSTV0910_P2_EXTPSK_MODE 0xf2250080 ++#define FSTV0910_P2_HIER_SHORTFRAME 0xf2250002 ++#define FSTV0910_P2_DECIM_PLFRAMES 0xf2250001 ++ ++/*P2_AGC2O*/ ++#define RSTV0910_P2_AGC2O 0xf22c ++#define FSTV0910_P2_CSTENV_MODE 0xf22c00c0 ++#define FSTV0910_P2_AGC2_LKSQRT 0xf22c0020 ++#define FSTV0910_P2_AGC2_LKMODE 0xf22c0010 ++#define FSTV0910_P2_AGC2_LKEQUA 0xf22c0008 ++#define FSTV0910_P2_AGC2_COEF 0xf22c0007 ++ ++/*P2_AGC2REF*/ ++#define RSTV0910_P2_AGC2REF 0xf22d ++#define FSTV0910_P2_AGC2_REF 0xf22d00ff ++ ++/*P2_AGC1ADJ*/ ++#define RSTV0910_P2_AGC1ADJ 0xf22e ++#define FSTV0910_P2_AGC1ADJ_MANUAL 0xf22e0080 ++#define FSTV0910_P2_AGC1_ADJUSTED 0xf22e007f ++ ++/*P2_AGC2I1*/ ++#define RSTV0910_P2_AGC2I1 0xf236 ++#define FSTV0910_P2_AGC2_INTEGRATOR1 0xf23600ff ++ ++/*P2_AGC2I0*/ ++#define RSTV0910_P2_AGC2I0 0xf237 ++#define FSTV0910_P2_AGC2_INTEGRATOR0 0xf23700ff ++ ++/*P2_CARCFG*/ ++#define RSTV0910_P2_CARCFG 0xf238 ++#define FSTV0910_P2_CFRUPLOW_AUTO 0xf2380080 ++#define FSTV0910_P2_CFRUPLOW_TEST 0xf2380040 ++#define FSTV0910_P2_WIDE_FREQDET 0xf2380020 ++#define FSTV0910_P2_CARHDR_NODIV8 0xf2380010 ++#define FSTV0910_P2_I2C_ROTA 0xf2380008 ++#define FSTV0910_P2_ROTAON 0xf2380004 ++#define FSTV0910_P2_PH_DET_ALGO 0xf2380003 ++ ++/*P2_ACLC*/ ++#define RSTV0910_P2_ACLC 0xf239 ++#define FSTV0910_P2_CARS1_ANOSAUTO 0xf2390040 ++#define FSTV0910_P2_CAR_ALPHA_MANT 0xf2390030 ++#define FSTV0910_P2_CAR_ALPHA_EXP 0xf239000f ++ ++/*P2_BCLC*/ ++#define RSTV0910_P2_BCLC 0xf23a ++#define FSTV0910_P2_CARS1_BNOSAUTO 0xf23a0040 ++#define FSTV0910_P2_CAR_BETA_MANT 0xf23a0030 ++#define FSTV0910_P2_CAR_BETA_EXP 0xf23a000f ++ ++/*P2_CARFREQ*/ ++#define RSTV0910_P2_CARFREQ 0xf23d ++#define FSTV0910_P2_KC_COARSE_EXP 0xf23d00f0 ++#define FSTV0910_P2_BETA_FREQ 0xf23d000f ++ ++/*P2_CARHDR*/ ++#define RSTV0910_P2_CARHDR 0xf23e ++#define FSTV0910_P2_K_FREQ_HDR 0xf23e00ff ++ ++/*P2_LDT*/ ++#define RSTV0910_P2_LDT 0xf23f ++#define FSTV0910_P2_CARLOCK_THRES 0xf23f01ff ++ ++/*P2_LDT2*/ ++#define RSTV0910_P2_LDT2 0xf240 ++#define FSTV0910_P2_CARLOCK_THRES2 0xf24001ff ++ ++/*P2_CFRICFG*/ ++#define RSTV0910_P2_CFRICFG 0xf241 ++#define FSTV0910_P2_CFRINIT_UNVALRNG 0xf2410080 ++#define FSTV0910_P2_CFRINIT_LUNVALCPT 0xf2410040 ++#define FSTV0910_P2_CFRINIT_ABORTDBL 0xf2410020 ++#define FSTV0910_P2_CFRINIT_ABORTPRED 0xf2410010 ++#define FSTV0910_P2_CFRINIT_UNVALSKIP 0xf2410008 ++#define FSTV0910_P2_CFRINIT_CSTINC 0xf2410004 ++#define FSTV0910_P2_CFRIROLL_GARDER 0xf2410002 ++#define FSTV0910_P2_NEG_CFRSTEP 0xf2410001 ++ ++/*P2_CFRUP1*/ ++#define RSTV0910_P2_CFRUP1 0xf242 ++#define FSTV0910_P2_CFR_UP1 0xf24201ff ++ ++/*P2_CFRUP0*/ ++#define RSTV0910_P2_CFRUP0 0xf243 ++#define FSTV0910_P2_CFR_UP0 0xf24300ff ++ ++/*P2_CFRIBASE1*/ ++#define RSTV0910_P2_CFRIBASE1 0xf244 ++#define FSTV0910_P2_CFRINIT_BASE1 0xf24400ff ++ ++/*P2_CFRIBASE0*/ ++#define RSTV0910_P2_CFRIBASE0 0xf245 ++#define FSTV0910_P2_CFRINIT_BASE0 0xf24500ff ++ ++/*P2_CFRLOW1*/ ++#define RSTV0910_P2_CFRLOW1 0xf246 ++#define FSTV0910_P2_CFR_LOW1 0xf24601ff ++ ++/*P2_CFRLOW0*/ ++#define RSTV0910_P2_CFRLOW0 0xf247 ++#define FSTV0910_P2_CFR_LOW0 0xf24700ff ++ ++/*P2_CFRINIT1*/ ++#define RSTV0910_P2_CFRINIT1 0xf248 ++#define FSTV0910_P2_CFR_INIT1 0xf24801ff ++ ++/*P2_CFRINIT0*/ ++#define RSTV0910_P2_CFRINIT0 0xf249 ++#define FSTV0910_P2_CFR_INIT0 0xf24900ff ++ ++/*P2_CFRINC1*/ ++#define RSTV0910_P2_CFRINC1 0xf24a ++#define FSTV0910_P2_MANUAL_CFRINC 0xf24a0080 ++#define FSTV0910_P2_CFR_INC1 0xf24a003f ++ ++/*P2_CFRINC0*/ ++#define RSTV0910_P2_CFRINC0 0xf24b ++#define FSTV0910_P2_CFR_INC0 0xf24b00ff ++ ++/*P2_CFR2*/ ++#define RSTV0910_P2_CFR2 0xf24c ++#define FSTV0910_P2_CAR_FREQ2 0xf24c01ff ++ ++/*P2_CFR1*/ ++#define RSTV0910_P2_CFR1 0xf24d ++#define FSTV0910_P2_CAR_FREQ1 0xf24d00ff ++ ++/*P2_CFR0*/ ++#define RSTV0910_P2_CFR0 0xf24e ++#define FSTV0910_P2_CAR_FREQ0 0xf24e00ff ++ ++/*P2_LDI*/ ++#define RSTV0910_P2_LDI 0xf24f ++#define FSTV0910_P2_LOCK_DET_INTEGR 0xf24f01ff ++ ++/*P2_TMGCFG*/ ++#define RSTV0910_P2_TMGCFG 0xf250 ++#define FSTV0910_P2_TMGLOCK_BETA 0xf25000c0 ++#define FSTV0910_P2_DO_TIMING_CORR 0xf2500010 ++#define FSTV0910_P2_MANUAL_SCAN 0xf250000c ++#define FSTV0910_P2_TMG_MINFREQ 0xf2500003 ++ ++/*P2_RTC*/ ++#define RSTV0910_P2_RTC 0xf251 ++#define FSTV0910_P2_TMGALPHA_EXP 0xf25100f0 ++#define FSTV0910_P2_TMGBETA_EXP 0xf251000f ++ ++/*P2_RTCS2*/ ++#define RSTV0910_P2_RTCS2 0xf252 ++#define FSTV0910_P2_TMGALPHAS2_EXP 0xf25200f0 ++#define FSTV0910_P2_TMGBETAS2_EXP 0xf252000f ++ ++/*P2_TMGTHRISE*/ ++#define RSTV0910_P2_TMGTHRISE 0xf253 ++#define FSTV0910_P2_TMGLOCK_THRISE 0xf25300ff ++ ++/*P2_TMGTHFALL*/ ++#define RSTV0910_P2_TMGTHFALL 0xf254 ++#define FSTV0910_P2_TMGLOCK_THFALL 0xf25400ff ++ ++/*P2_SFRUPRATIO*/ ++#define RSTV0910_P2_SFRUPRATIO 0xf255 ++#define FSTV0910_P2_SFR_UPRATIO 0xf25500ff ++ ++/*P2_SFRLOWRATIO*/ ++#define RSTV0910_P2_SFRLOWRATIO 0xf256 ++#define FSTV0910_P2_SFR_LOWRATIO 0xf25600ff ++ ++/*P2_KTTMG*/ ++#define RSTV0910_P2_KTTMG 0xf257 ++#define FSTV0910_P2_KT_TMG_EXP 0xf25700f0 ++ ++/*P2_KREFTMG*/ ++#define RSTV0910_P2_KREFTMG 0xf258 ++#define FSTV0910_P2_KREF_TMG 0xf25800ff ++ ++/*P2_SFRSTEP*/ ++#define RSTV0910_P2_SFRSTEP 0xf259 ++#define FSTV0910_P2_SFR_SCANSTEP 0xf25900f0 ++#define FSTV0910_P2_SFR_CENTERSTEP 0xf259000f ++ ++/*P2_TMGCFG2*/ ++#define RSTV0910_P2_TMGCFG2 0xf25a ++#define FSTV0910_P2_KREFTMG2_DECMODE 0xf25a00c0 ++#define FSTV0910_P2_DIS_AUTOSAMP 0xf25a0008 ++#define FSTV0910_P2_SCANINIT_QUART 0xf25a0004 ++#define FSTV0910_P2_NOTMG_DVBS1DERAT 0xf25a0002 ++#define FSTV0910_P2_SFRRATIO_FINE 0xf25a0001 ++ ++/*P2_KREFTMG2*/ ++#define RSTV0910_P2_KREFTMG2 0xf25b ++#define FSTV0910_P2_KREF_TMG2 0xf25b00ff ++ ++/*P2_TMGCFG3*/ ++#define RSTV0910_P2_TMGCFG3 0xf25d ++#define FSTV0910_P2_CFRINC_MODE 0xf25d0070 ++#define FSTV0910_P2_CONT_TMGCENTER 0xf25d0008 ++#define FSTV0910_P2_AUTO_GUP 0xf25d0004 ++#define FSTV0910_P2_AUTO_GLOW 0xf25d0002 ++#define FSTV0910_P2_SFRVAL_MINMODE 0xf25d0001 ++ ++/*P2_SFRINIT1*/ ++#define RSTV0910_P2_SFRINIT1 0xf25e ++#define FSTV0910_P2_SFR_INIT1 0xf25e00ff ++ ++/*P2_SFRINIT0*/ ++#define RSTV0910_P2_SFRINIT0 0xf25f ++#define FSTV0910_P2_SFR_INIT0 0xf25f00ff ++ ++/*P2_SFRUP1*/ ++#define RSTV0910_P2_SFRUP1 0xf260 ++#define FSTV0910_P2_SYMB_FREQ_UP1 0xf26000ff ++ ++/*P2_SFRUP0*/ ++#define RSTV0910_P2_SFRUP0 0xf261 ++#define FSTV0910_P2_SYMB_FREQ_UP0 0xf26100ff ++ ++/*P2_SFRLOW1*/ ++#define RSTV0910_P2_SFRLOW1 0xf262 ++#define FSTV0910_P2_SYMB_FREQ_LOW1 0xf26200ff ++ ++/*P2_SFRLOW0*/ ++#define RSTV0910_P2_SFRLOW0 0xf263 ++#define FSTV0910_P2_SYMB_FREQ_LOW0 0xf26300ff ++ ++/*P2_SFR3*/ ++#define RSTV0910_P2_SFR3 0xf264 ++#define FSTV0910_P2_SYMB_FREQ3 0xf26400ff ++ ++/*P2_SFR2*/ ++#define RSTV0910_P2_SFR2 0xf265 ++#define FSTV0910_P2_SYMB_FREQ2 0xf26500ff ++ ++/*P2_SFR1*/ ++#define RSTV0910_P2_SFR1 0xf266 ++#define FSTV0910_P2_SYMB_FREQ1 0xf26600ff ++ ++/*P2_SFR0*/ ++#define RSTV0910_P2_SFR0 0xf267 ++#define FSTV0910_P2_SYMB_FREQ0 0xf26700ff ++ ++/*P2_TMGREG2*/ ++#define RSTV0910_P2_TMGREG2 0xf268 ++#define FSTV0910_P2_TMGREG2 0xf26800ff ++ ++/*P2_TMGREG1*/ ++#define RSTV0910_P2_TMGREG1 0xf269 ++#define FSTV0910_P2_TMGREG1 0xf26900ff ++ ++/*P2_TMGREG0*/ ++#define RSTV0910_P2_TMGREG0 0xf26a ++#define FSTV0910_P2_TMGREG0 0xf26a00ff ++ ++/*P2_TMGLOCK1*/ ++#define RSTV0910_P2_TMGLOCK1 0xf26b ++#define FSTV0910_P2_TMGLOCK_LEVEL1 0xf26b01ff ++ ++/*P2_TMGLOCK0*/ ++#define RSTV0910_P2_TMGLOCK0 0xf26c ++#define FSTV0910_P2_TMGLOCK_LEVEL0 0xf26c00ff ++ ++/*P2_TMGOBS*/ ++#define RSTV0910_P2_TMGOBS 0xf26d ++#define FSTV0910_P2_ROLLOFF_STATUS 0xf26d00c0 ++#define FSTV0910_P2_SCAN_SIGN 0xf26d0030 ++#define FSTV0910_P2_TMG_SCANNING 0xf26d0008 ++#define FSTV0910_P2_CHCENTERING_MODE 0xf26d0004 ++#define FSTV0910_P2_TMG_SCANFAIL 0xf26d0002 ++ ++/*P2_EQUALCFG*/ ++#define RSTV0910_P2_EQUALCFG 0xf26f ++#define FSTV0910_P2_NOTMG_NEGALWAIT 0xf26f0080 ++#define FSTV0910_P2_EQUAL_ON 0xf26f0040 ++#define FSTV0910_P2_SEL_EQUALCOR 0xf26f0038 ++#define FSTV0910_P2_MU_EQUALDFE 0xf26f0007 ++ ++/*P2_EQUAI1*/ ++#define RSTV0910_P2_EQUAI1 0xf270 ++#define FSTV0910_P2_EQUA_ACCI1 0xf27001ff ++ ++/*P2_EQUAQ1*/ ++#define RSTV0910_P2_EQUAQ1 0xf271 ++#define FSTV0910_P2_EQUA_ACCQ1 0xf27101ff ++ ++/*P2_EQUAI2*/ ++#define RSTV0910_P2_EQUAI2 0xf272 ++#define FSTV0910_P2_EQUA_ACCI2 0xf27201ff ++ ++/*P2_EQUAQ2*/ ++#define RSTV0910_P2_EQUAQ2 0xf273 ++#define FSTV0910_P2_EQUA_ACCQ2 0xf27301ff ++ ++/*P2_EQUAI3*/ ++#define RSTV0910_P2_EQUAI3 0xf274 ++#define FSTV0910_P2_EQUA_ACCI3 0xf27401ff ++ ++/*P2_EQUAQ3*/ ++#define RSTV0910_P2_EQUAQ3 0xf275 ++#define FSTV0910_P2_EQUA_ACCQ3 0xf27501ff ++ ++/*P2_EQUAI4*/ ++#define RSTV0910_P2_EQUAI4 0xf276 ++#define FSTV0910_P2_EQUA_ACCI4 0xf27601ff ++ ++/*P2_EQUAQ4*/ ++#define RSTV0910_P2_EQUAQ4 0xf277 ++#define FSTV0910_P2_EQUA_ACCQ4 0xf27701ff ++ ++/*P2_EQUAI5*/ ++#define RSTV0910_P2_EQUAI5 0xf278 ++#define FSTV0910_P2_EQUA_ACCI5 0xf27801ff ++ ++/*P2_EQUAQ5*/ ++#define RSTV0910_P2_EQUAQ5 0xf279 ++#define FSTV0910_P2_EQUA_ACCQ5 0xf27901ff ++ ++/*P2_EQUAI6*/ ++#define RSTV0910_P2_EQUAI6 0xf27a ++#define FSTV0910_P2_EQUA_ACCI6 0xf27a01ff ++ ++/*P2_EQUAQ6*/ ++#define RSTV0910_P2_EQUAQ6 0xf27b ++#define FSTV0910_P2_EQUA_ACCQ6 0xf27b01ff ++ ++/*P2_EQUAI7*/ ++#define RSTV0910_P2_EQUAI7 0xf27c ++#define FSTV0910_P2_EQUA_ACCI7 0xf27c01ff ++ ++/*P2_EQUAQ7*/ ++#define RSTV0910_P2_EQUAQ7 0xf27d ++#define FSTV0910_P2_EQUA_ACCQ7 0xf27d01ff ++ ++/*P2_EQUAI8*/ ++#define RSTV0910_P2_EQUAI8 0xf27e ++#define FSTV0910_P2_EQUA_ACCI8 0xf27e01ff ++ ++/*P2_EQUAQ8*/ ++#define RSTV0910_P2_EQUAQ8 0xf27f ++#define FSTV0910_P2_EQUA_ACCQ8 0xf27f01ff ++ ++/*P2_NNOSDATAT1*/ ++#define RSTV0910_P2_NNOSDATAT1 0xf280 ++#define FSTV0910_P2_NOSDATAT_NORMED1 0xf28000ff ++ ++/*P2_NNOSDATAT0*/ ++#define RSTV0910_P2_NNOSDATAT0 0xf281 ++#define FSTV0910_P2_NOSDATAT_NORMED0 0xf28100ff ++ ++/*P2_NNOSDATA1*/ ++#define RSTV0910_P2_NNOSDATA1 0xf282 ++#define FSTV0910_P2_NOSDATA_NORMED1 0xf28200ff ++ ++/*P2_NNOSDATA0*/ ++#define RSTV0910_P2_NNOSDATA0 0xf283 ++#define FSTV0910_P2_NOSDATA_NORMED0 0xf28300ff ++ ++/*P2_NNOSPLHT1*/ ++#define RSTV0910_P2_NNOSPLHT1 0xf284 ++#define FSTV0910_P2_NOSPLHT_NORMED1 0xf28400ff ++ ++/*P2_NNOSPLHT0*/ ++#define RSTV0910_P2_NNOSPLHT0 0xf285 ++#define FSTV0910_P2_NOSPLHT_NORMED0 0xf28500ff ++ ++/*P2_NNOSPLH1*/ ++#define RSTV0910_P2_NNOSPLH1 0xf286 ++#define FSTV0910_P2_NOSPLH_NORMED1 0xf28600ff ++ ++/*P2_NNOSPLH0*/ ++#define RSTV0910_P2_NNOSPLH0 0xf287 ++#define FSTV0910_P2_NOSPLH_NORMED0 0xf28700ff ++ ++/*P2_NOSDATAT1*/ ++#define RSTV0910_P2_NOSDATAT1 0xf288 ++#define FSTV0910_P2_NOSDATAT_UNNORMED1 0xf28800ff ++ ++/*P2_NOSDATAT0*/ ++#define RSTV0910_P2_NOSDATAT0 0xf289 ++#define FSTV0910_P2_NOSDATAT_UNNORMED0 0xf28900ff ++ ++/*P2_NNOSFRAME1*/ ++#define RSTV0910_P2_NNOSFRAME1 0xf28a ++#define FSTV0910_P2_NOSFRAME_NORMED1 0xf28a00ff ++ ++/*P2_NNOSFRAME0*/ ++#define RSTV0910_P2_NNOSFRAME0 0xf28b ++#define FSTV0910_P2_NOSFRAME_NORMED0 0xf28b00ff ++ ++/*P2_NNOSRAD1*/ ++#define RSTV0910_P2_NNOSRAD1 0xf28c ++#define FSTV0910_P2_NOSRADIAL_NORMED1 0xf28c00ff ++ ++/*P2_NNOSRAD0*/ ++#define RSTV0910_P2_NNOSRAD0 0xf28d ++#define FSTV0910_P2_NOSRADIAL_NORMED0 0xf28d00ff ++ ++/*P2_NOSCFGF1*/ ++#define RSTV0910_P2_NOSCFGF1 0xf28e ++#define FSTV0910_P2_LOWNOISE_MESURE 0xf28e0080 ++#define FSTV0910_P2_NOS_DELFRAME 0xf28e0040 ++#define FSTV0910_P2_NOSDATA_MODE 0xf28e0030 ++#define FSTV0910_P2_FRAMESEL_TYPESEL 0xf28e000c ++#define FSTV0910_P2_FRAMESEL_TYPE 0xf28e0003 ++ ++/*P2_CAR2CFG*/ ++#define RSTV0910_P2_CAR2CFG 0xf290 ++#define FSTV0910_P2_DESCRAMB_OFF 0xf2900080 ++#define FSTV0910_P2_EN_PHNOSRAM 0xf2900020 ++#define FSTV0910_P2_STOP_CFR2UPDATE 0xf2900010 ++#define FSTV0910_P2_STOP_NCO2UPDATE 0xf2900008 ++#define FSTV0910_P2_ROTA2ON 0xf2900004 ++#define FSTV0910_P2_PH_DET_ALGO2 0xf2900003 ++ ++/*P2_CFR2CFR1*/ ++#define RSTV0910_P2_CFR2CFR1 0xf291 ++#define FSTV0910_P2_CFR2_S2CONTROL 0xf29100c0 ++#define FSTV0910_P2_EN_S2CAR2CENTER 0xf2910020 ++#define FSTV0910_P2_BCHERRCFR2_MODE 0xf2910018 ++#define FSTV0910_P2_CFR2TOCFR1_BETA 0xf2910007 ++ ++/*P2_CAR3CFG*/ ++#define RSTV0910_P2_CAR3CFG 0xf292 ++#define FSTV0910_P2_CARRIER23_MODE 0xf29200c0 ++#define FSTV0910_P2_CAR3INTERM_DVBS1 0xf2920020 ++#define FSTV0910_P2_ABAMPLIF_MODE 0xf2920018 ++#define FSTV0910_P2_CARRIER3_ALPHA3DL 0xf2920007 ++ ++/*P2_CFR22*/ ++#define RSTV0910_P2_CFR22 0xf293 ++#define FSTV0910_P2_CAR2_FREQ2 0xf29301ff ++ ++/*P2_CFR21*/ ++#define RSTV0910_P2_CFR21 0xf294 ++#define FSTV0910_P2_CAR2_FREQ1 0xf29400ff ++ ++/*P2_CFR20*/ ++#define RSTV0910_P2_CFR20 0xf295 ++#define FSTV0910_P2_CAR2_FREQ0 0xf29500ff ++ ++/*P2_ACLC2S2Q*/ ++#define RSTV0910_P2_ACLC2S2Q 0xf297 ++#define FSTV0910_P2_ENAB_SPSKSYMB 0xf2970080 ++#define FSTV0910_P2_CAR2S2_QANOSAUTO 0xf2970040 ++#define FSTV0910_P2_CAR2S2_Q_ALPH_M 0xf2970030 ++#define FSTV0910_P2_CAR2S2_Q_ALPH_E 0xf297000f ++ ++/*P2_ACLC2S28*/ ++#define RSTV0910_P2_ACLC2S28 0xf298 ++#define FSTV0910_P2_OLDI3Q_MODE 0xf2980080 ++#define FSTV0910_P2_CAR2S2_8ANOSAUTO 0xf2980040 ++#define FSTV0910_P2_CAR2S2_8_ALPH_M 0xf2980030 ++#define FSTV0910_P2_CAR2S2_8_ALPH_E 0xf298000f ++ ++/*P2_ACLC2S216A*/ ++#define RSTV0910_P2_ACLC2S216A 0xf299 ++#define FSTV0910_P2_CAR2S2_16ANOSAUTO 0xf2990040 ++#define FSTV0910_P2_CAR2S2_16A_ALPH_M 0xf2990030 ++#define FSTV0910_P2_CAR2S2_16A_ALPH_E 0xf299000f ++ ++/*P2_ACLC2S232A*/ ++#define RSTV0910_P2_ACLC2S232A 0xf29a ++#define FSTV0910_P2_CAR2S2_32ANOSUATO 0xf29a0040 ++#define FSTV0910_P2_CAR2S2_32A_ALPH_M 0xf29a0030 ++#define FSTV0910_P2_CAR2S2_32A_ALPH_E 0xf29a000f ++ ++/*P2_BCLC2S2Q*/ ++#define RSTV0910_P2_BCLC2S2Q 0xf29c ++#define FSTV0910_P2_DVBS2S2Q_NIP 0xf29c0080 ++#define FSTV0910_P2_CAR2S2_QBNOSAUTO 0xf29c0040 ++#define FSTV0910_P2_CAR2S2_Q_BETA_M 0xf29c0030 ++#define FSTV0910_P2_CAR2S2_Q_BETA_E 0xf29c000f ++ ++/*P2_BCLC2S28*/ ++#define RSTV0910_P2_BCLC2S28 0xf29d ++#define FSTV0910_P2_DVBS2S28_NIP 0xf29d0080 ++#define FSTV0910_P2_CAR2S2_8BNOSAUTO 0xf29d0040 ++#define FSTV0910_P2_CAR2S2_8_BETA_M 0xf29d0030 ++#define FSTV0910_P2_CAR2S2_8_BETA_E 0xf29d000f ++ ++/*P2_PLROOT2*/ ++#define RSTV0910_P2_PLROOT2 0xf2ac ++#define FSTV0910_P2_PLHAUTO_DISPLH 0xf2ac0040 ++#define FSTV0910_P2_PLHAUTO_FASTMODE 0xf2ac0020 ++#define FSTV0910_P2_PLHAUTO_ENABLE 0xf2ac0010 ++#define FSTV0910_P2_PLSCRAMB_MODE 0xf2ac000c ++#define FSTV0910_P2_PLSCRAMB_ROOT2 0xf2ac0003 ++ ++/*P2_PLROOT1*/ ++#define RSTV0910_P2_PLROOT1 0xf2ad ++#define FSTV0910_P2_PLSCRAMB_ROOT1 0xf2ad00ff ++ ++/*P2_PLROOT0*/ ++#define RSTV0910_P2_PLROOT0 0xf2ae ++#define FSTV0910_P2_PLSCRAMB_ROOT0 0xf2ae00ff ++ ++/*P2_MODCODLST7*/ ++#define RSTV0910_P2_MODCODLST7 0xf2b7 ++#define FSTV0910_P2_MODCOD_NNOSFILTER 0xf2b70080 ++#define FSTV0910_P2_MODCODLST_NOSTYPE 0xf2b70040 ++#define FSTV0910_P2_DIS_8PSK_9_10 0xf2b70030 ++#define FSTV0910_P2_DIS_8P_8_9 0xf2b7000f ++ ++/*P2_MODCODLST8*/ ++#define RSTV0910_P2_MODCODLST8 0xf2b8 ++#define FSTV0910_P2_DIS_8P_5_6 0xf2b800f0 ++#define FSTV0910_P2_DIS_8P_3_4 0xf2b8000f ++ ++/*P2_MODCODLST9*/ ++#define RSTV0910_P2_MODCODLST9 0xf2b9 ++#define FSTV0910_P2_DIS_8P_2_3 0xf2b900f0 ++#define FSTV0910_P2_DIS_8P_3_5 0xf2b9000f ++ ++/*P2_MODCODLSTA*/ ++#define RSTV0910_P2_MODCODLSTA 0xf2ba ++#define FSTV0910_P2_NOSFILTER_LIMITE 0xf2ba0080 ++#define FSTV0910_P2_NOSFILTER_MODE 0xf2ba0040 ++#define FSTV0910_P2_DIS_QPSK_9_10 0xf2ba0030 ++#define FSTV0910_P2_DIS_QP_8_9 0xf2ba000f ++ ++/*P2_MODCODLSTB*/ ++#define RSTV0910_P2_MODCODLSTB 0xf2bb ++#define FSTV0910_P2_DIS_QP_5_6 0xf2bb00f0 ++#define FSTV0910_P2_DIS_QP_4_5 0xf2bb000f ++ ++/*P2_MODCODLSTC*/ ++#define RSTV0910_P2_MODCODLSTC 0xf2bc ++#define FSTV0910_P2_DIS_QP_3_4 0xf2bc00f0 ++#define FSTV0910_P2_DIS_QP_2_3 0xf2bc000f ++ ++/*P2_MODCODLSTD*/ ++#define RSTV0910_P2_MODCODLSTD 0xf2bd ++#define FSTV0910_P2_DIS_QPSK_3_5 0xf2bd00f0 ++#define FSTV0910_P2_DIS_QPSK_1_2 0xf2bd000f ++ ++/*P2_GAUSSR0*/ ++#define RSTV0910_P2_GAUSSR0 0xf2c0 ++#define FSTV0910_P2_EN_CCIMODE 0xf2c00080 ++#define FSTV0910_P2_R0_GAUSSIEN 0xf2c0007f ++ ++/*P2_CCIR0*/ ++#define RSTV0910_P2_CCIR0 0xf2c1 ++#define FSTV0910_P2_CCIDETECT_PLHONLY 0xf2c10080 ++#define FSTV0910_P2_R0_CCI 0xf2c1007f ++ ++/*P2_CCIQUANT*/ ++#define RSTV0910_P2_CCIQUANT 0xf2c2 ++#define FSTV0910_P2_CCI_BETA 0xf2c200e0 ++#define FSTV0910_P2_CCI_QUANT 0xf2c2001f ++ ++/*P2_CCITHRES*/ ++#define RSTV0910_P2_CCITHRES 0xf2c3 ++#define FSTV0910_P2_CCI_THRESHOLD 0xf2c300ff ++ ++/*P2_CCIACC*/ ++#define RSTV0910_P2_CCIACC 0xf2c4 ++#define FSTV0910_P2_CCI_VALUE 0xf2c400ff ++ ++/*P2_DSTATUS4*/ ++#define RSTV0910_P2_DSTATUS4 0xf2c5 ++#define FSTV0910_P2_RAINFADE_DETECT 0xf2c50080 ++#define FSTV0910_P2_NOTHRES2_FAIL 0xf2c50040 ++#define FSTV0910_P2_NOTHRES1_FAIL 0xf2c50020 ++#define FSTV0910_P2_PILOT_FAILDETECT 0xf2c50010 ++#define FSTV0910_P2_HIER_DETECT 0xf2c50008 ++#define FSTV0910_P2_DMDPROG_ERROR 0xf2c50004 ++#define FSTV0910_P2_CSTENV_DETECT 0xf2c50002 ++#define FSTV0910_P2_DETECTION_TRIAX 0xf2c50001 ++ ++/*P2_DMDRESCFG*/ ++#define RSTV0910_P2_DMDRESCFG 0xf2c6 ++#define FSTV0910_P2_DMDRES_RESET 0xf2c60080 ++#define FSTV0910_P2_DMDRES_NOISESQR 0xf2c60010 ++#define FSTV0910_P2_DMDRES_STRALL 0xf2c60008 ++#define FSTV0910_P2_DMDRES_NEWONLY 0xf2c60004 ++#define FSTV0910_P2_DMDRES_NOSTORE 0xf2c60002 ++#define FSTV0910_P2_DMDRES_AGC2MEM 0xf2c60001 ++ ++/*P2_DMDRESADR*/ ++#define RSTV0910_P2_DMDRESADR 0xf2c7 ++#define FSTV0910_P2_SUSP_PREDCANAL 0xf2c70080 ++#define FSTV0910_P2_DMDRES_VALIDCFR 0xf2c70040 ++#define FSTV0910_P2_DMDRES_MEMFULL 0xf2c70030 ++#define FSTV0910_P2_DMDRES_RESNBR 0xf2c7000f ++ ++/*P2_DMDRESDATA7*/ ++#define RSTV0910_P2_DMDRESDATA7 0xf2c8 ++#define FSTV0910_P2_DMDRES_DATA7 0xf2c800ff ++ ++/*P2_DMDRESDATA6*/ ++#define RSTV0910_P2_DMDRESDATA6 0xf2c9 ++#define FSTV0910_P2_DMDRES_DATA6 0xf2c900ff ++ ++/*P2_DMDRESDATA5*/ ++#define RSTV0910_P2_DMDRESDATA5 0xf2ca ++#define FSTV0910_P2_DMDRES_DATA5 0xf2ca00ff ++ ++/*P2_DMDRESDATA4*/ ++#define RSTV0910_P2_DMDRESDATA4 0xf2cb ++#define FSTV0910_P2_DMDRES_DATA4 0xf2cb00ff ++ ++/*P2_DMDRESDATA3*/ ++#define RSTV0910_P2_DMDRESDATA3 0xf2cc ++#define FSTV0910_P2_DMDRES_DATA3 0xf2cc00ff ++ ++/*P2_DMDRESDATA2*/ ++#define RSTV0910_P2_DMDRESDATA2 0xf2cd ++#define FSTV0910_P2_DMDRES_DATA2 0xf2cd00ff ++ ++/*P2_DMDRESDATA1*/ ++#define RSTV0910_P2_DMDRESDATA1 0xf2ce ++#define FSTV0910_P2_DMDRES_DATA1 0xf2ce00ff ++ ++/*P2_DMDRESDATA0*/ ++#define RSTV0910_P2_DMDRESDATA0 0xf2cf ++#define FSTV0910_P2_DMDRES_DATA0 0xf2cf00ff ++ ++/*P2_FFEI1*/ ++#define RSTV0910_P2_FFEI1 0xf2d0 ++#define FSTV0910_P2_FFE_ACCI1 0xf2d001ff ++ ++/*P2_FFEQ1*/ ++#define RSTV0910_P2_FFEQ1 0xf2d1 ++#define FSTV0910_P2_FFE_ACCQ1 0xf2d101ff ++ ++/*P2_FFEI2*/ ++#define RSTV0910_P2_FFEI2 0xf2d2 ++#define FSTV0910_P2_FFE_ACCI2 0xf2d201ff ++ ++/*P2_FFEQ2*/ ++#define RSTV0910_P2_FFEQ2 0xf2d3 ++#define FSTV0910_P2_FFE_ACCQ2 0xf2d301ff ++ ++/*P2_FFEI3*/ ++#define RSTV0910_P2_FFEI3 0xf2d4 ++#define FSTV0910_P2_FFE_ACCI3 0xf2d401ff ++ ++/*P2_FFEQ3*/ ++#define RSTV0910_P2_FFEQ3 0xf2d5 ++#define FSTV0910_P2_FFE_ACCQ3 0xf2d501ff ++ ++/*P2_FFEI4*/ ++#define RSTV0910_P2_FFEI4 0xf2d6 ++#define FSTV0910_P2_FFE_ACCI4 0xf2d601ff ++ ++/*P2_FFEQ4*/ ++#define RSTV0910_P2_FFEQ4 0xf2d7 ++#define FSTV0910_P2_FFE_ACCQ4 0xf2d701ff ++ ++/*P2_FFECFG*/ ++#define RSTV0910_P2_FFECFG 0xf2d8 ++#define FSTV0910_P2_EQUALFFE_ON 0xf2d80040 ++#define FSTV0910_P2_EQUAL_USEDSYMB 0xf2d80030 ++#define FSTV0910_P2_MU_EQUALFFE 0xf2d80007 ++ ++/*P2_TNRCFG2*/ ++#define RSTV0910_P2_TNRCFG2 0xf2e1 ++#define FSTV0910_P2_TUN_IQSWAP 0xf2e10080 ++#define FSTV0910_P2_STB6110_STEP2MHZ 0xf2e10040 ++#define FSTV0910_P2_STB6120_DBLI2C 0xf2e10020 ++#define FSTV0910_P2_TUNER_WIDEBAND 0xf2e10010 ++#define FSTV0910_P2_TUNER_OBSPAGE 0xf2e10008 ++#define FSTV0910_P2_DIS_BWCALC 0xf2e10004 ++#define FSTV0910_P2_SHORT_WAITSTATES 0xf2e10002 ++#define FSTV0910_P2_DIS_2BWAGC1 0xf2e10001 ++ ++/*P2_SMAPCOEF7*/ ++#define RSTV0910_P2_SMAPCOEF7 0xf300 ++#define FSTV0910_P2_DIS_QSCALE 0xf3000080 ++#define FSTV0910_P2_SMAPCOEF_Q_LLR12 0xf300017f ++ ++/*P2_SMAPCOEF6*/ ++#define RSTV0910_P2_SMAPCOEF6 0xf301 ++#define FSTV0910_P2_DIS_AGC2SCALE 0xf3010080 ++#define FSTV0910_P2_DIS_16IQMULT 0xf3010040 ++#define FSTV0910_P2_OLD_16APSK47 0xf3010020 ++#define FSTV0910_P2_OLD_16APSK12 0xf3010010 ++#define FSTV0910_P2_DIS_NEWSCALE 0xf3010008 ++#define FSTV0910_P2_ADJ_8PSKLLR1 0xf3010004 ++#define FSTV0910_P2_OLD_8PSKLLR1 0xf3010002 ++#define FSTV0910_P2_DIS_AB8PSK 0xf3010001 ++ ++/*P2_SMAPCOEF5*/ ++#define RSTV0910_P2_SMAPCOEF5 0xf302 ++#define FSTV0910_P2_DIS_8SCALE 0xf3020080 ++#define FSTV0910_P2_SMAPCOEF_8P_LLR23 0xf302017f ++ ++/*P2_NOSTHRES1*/ ++#define RSTV0910_P2_NOSTHRES1 0xf309 ++#define FSTV0910_P2_NOS_THRESHOLD1 0xf30900ff ++ ++/*P2_NOSTHRES2*/ ++#define RSTV0910_P2_NOSTHRES2 0xf30a ++#define FSTV0910_P2_NOS_THRESHOLD2 0xf30a00ff ++ ++/*P2_NOSDIFF1*/ ++#define RSTV0910_P2_NOSDIFF1 0xf30b ++#define FSTV0910_P2_NOSTHRES1_DIFF 0xf30b00ff ++ ++/*P2_RAINFADE*/ ++#define RSTV0910_P2_RAINFADE 0xf30c ++#define FSTV0910_P2_NOSTHRES_DATAT 0xf30c0080 ++#define FSTV0910_P2_RAINFADE_CNLIMIT 0xf30c0070 ++#define FSTV0910_P2_RAINFADE_TIMEOUT 0xf30c0007 ++ ++/*P2_NOSRAMCFG*/ ++#define RSTV0910_P2_NOSRAMCFG 0xf30d ++#define FSTV0910_P2_NOSRAM_DVBS2DATA 0xf30d0080 ++#define FSTV0910_P2_NOSRAM_QUADRAT 0xf30d0040 ++#define FSTV0910_P2_NOSRAM_ACTIVATION 0xf30d0030 ++#define FSTV0910_P2_NOSRAM_CNRONLY 0xf30d0008 ++#define FSTV0910_P2_NOSRAM_LGNCNR1 0xf30d0007 ++ ++/*P2_NOSRAMPOS*/ ++#define RSTV0910_P2_NOSRAMPOS 0xf30e ++#define FSTV0910_P2_NOSRAM_LGNCNR0 0xf30e00f0 ++#define FSTV0910_P2_NOSRAM_VALIDE 0xf30e0004 ++#define FSTV0910_P2_NOSRAM_CNRVAL1 0xf30e0003 ++ ++/*P2_NOSRAMVAL*/ ++#define RSTV0910_P2_NOSRAMVAL 0xf30f ++#define FSTV0910_P2_NOSRAM_CNRVAL0 0xf30f00ff ++ ++/*P2_DMDPLHSTAT*/ ++#define RSTV0910_P2_DMDPLHSTAT 0xf320 ++#define FSTV0910_P2_PLH_STATISTIC 0xf32000ff ++ ++/*P2_LOCKTIME3*/ ++#define RSTV0910_P2_LOCKTIME3 0xf322 ++#define FSTV0910_P2_DEMOD_LOCKTIME3 0xf32200ff ++ ++/*P2_LOCKTIME2*/ ++#define RSTV0910_P2_LOCKTIME2 0xf323 ++#define FSTV0910_P2_DEMOD_LOCKTIME2 0xf32300ff ++ ++/*P2_LOCKTIME1*/ ++#define RSTV0910_P2_LOCKTIME1 0xf324 ++#define FSTV0910_P2_DEMOD_LOCKTIME1 0xf32400ff ++ ++/*P2_LOCKTIME0*/ ++#define RSTV0910_P2_LOCKTIME0 0xf325 ++#define FSTV0910_P2_DEMOD_LOCKTIME0 0xf32500ff ++ ++/*P2_VITSCALE*/ ++#define RSTV0910_P2_VITSCALE 0xf332 ++#define FSTV0910_P2_NVTH_NOSRANGE 0xf3320080 ++#define FSTV0910_P2_VERROR_MAXMODE 0xf3320040 ++#define FSTV0910_P2_KDIV_MODE 0xf3320030 ++#define FSTV0910_P2_NSLOWSN_LOCKED 0xf3320008 ++#define FSTV0910_P2_DELOCK_PRFLOSS 0xf3320004 ++#define FSTV0910_P2_DIS_RSFLOCK 0xf3320002 ++ ++/*P2_FECM*/ ++#define RSTV0910_P2_FECM 0xf333 ++#define FSTV0910_P2_DSS_DVB 0xf3330080 ++#define FSTV0910_P2_DEMOD_BYPASS 0xf3330040 ++#define FSTV0910_P2_CMP_SLOWMODE 0xf3330020 ++#define FSTV0910_P2_DSS_SRCH 0xf3330010 ++#define FSTV0910_P2_DIFF_MODEVIT 0xf3330004 ++#define FSTV0910_P2_SYNCVIT 0xf3330002 ++#define FSTV0910_P2_IQINV 0xf3330001 ++ ++/*P2_VTH12*/ ++#define RSTV0910_P2_VTH12 0xf334 ++#define FSTV0910_P2_VTH12 0xf33400ff ++ ++/*P2_VTH23*/ ++#define RSTV0910_P2_VTH23 0xf335 ++#define FSTV0910_P2_VTH23 0xf33500ff ++ ++/*P2_VTH34*/ ++#define RSTV0910_P2_VTH34 0xf336 ++#define FSTV0910_P2_VTH34 0xf33600ff ++ ++/*P2_VTH56*/ ++#define RSTV0910_P2_VTH56 0xf337 ++#define FSTV0910_P2_VTH56 0xf33700ff ++ ++/*P2_VTH67*/ ++#define RSTV0910_P2_VTH67 0xf338 ++#define FSTV0910_P2_VTH67 0xf33800ff ++ ++/*P2_VTH78*/ ++#define RSTV0910_P2_VTH78 0xf339 ++#define FSTV0910_P2_VTH78 0xf33900ff ++ ++/*P2_VITCURPUN*/ ++#define RSTV0910_P2_VITCURPUN 0xf33a ++#define FSTV0910_P2_CYCLESLIP_VIT 0xf33a0080 ++#define FSTV0910_P2_VIT_ROTA180 0xf33a0040 ++#define FSTV0910_P2_VIT_ROTA90 0xf33a0020 ++#define FSTV0910_P2_VIT_CURPUN 0xf33a001f ++ ++/*P2_VERROR*/ ++#define RSTV0910_P2_VERROR 0xf33b ++#define FSTV0910_P2_REGERR_VIT 0xf33b00ff ++ ++/*P2_PRVIT*/ ++#define RSTV0910_P2_PRVIT 0xf33c ++#define FSTV0910_P2_DIS_VTHLOCK 0xf33c0040 ++#define FSTV0910_P2_E7_8VIT 0xf33c0020 ++#define FSTV0910_P2_E6_7VIT 0xf33c0010 ++#define FSTV0910_P2_E5_6VIT 0xf33c0008 ++#define FSTV0910_P2_E3_4VIT 0xf33c0004 ++#define FSTV0910_P2_E2_3VIT 0xf33c0002 ++#define FSTV0910_P2_E1_2VIT 0xf33c0001 ++ ++/*P2_VAVSRVIT*/ ++#define RSTV0910_P2_VAVSRVIT 0xf33d ++#define FSTV0910_P2_AMVIT 0xf33d0080 ++#define FSTV0910_P2_FROZENVIT 0xf33d0040 ++#define FSTV0910_P2_SNVIT 0xf33d0030 ++#define FSTV0910_P2_TOVVIT 0xf33d000c ++#define FSTV0910_P2_HYPVIT 0xf33d0003 ++ ++/*P2_VSTATUSVIT*/ ++#define RSTV0910_P2_VSTATUSVIT 0xf33e ++#define FSTV0910_P2_VITERBI_ON 0xf33e0080 ++#define FSTV0910_P2_END_LOOPVIT 0xf33e0040 ++#define FSTV0910_P2_VITERBI_DEPRF 0xf33e0020 ++#define FSTV0910_P2_PRFVIT 0xf33e0010 ++#define FSTV0910_P2_LOCKEDVIT 0xf33e0008 ++#define FSTV0910_P2_VITERBI_DELOCK 0xf33e0004 ++#define FSTV0910_P2_VIT_DEMODSEL 0xf33e0002 ++#define FSTV0910_P2_VITERBI_COMPOUT 0xf33e0001 ++ ++/*P2_VTHINUSE*/ ++#define RSTV0910_P2_VTHINUSE 0xf33f ++#define FSTV0910_P2_VIT_INUSE 0xf33f00ff ++ ++/*P2_KDIV12*/ ++#define RSTV0910_P2_KDIV12 0xf340 ++#define FSTV0910_P2_KDIV12_MANUAL 0xf3400080 ++#define FSTV0910_P2_K_DIVIDER_12 0xf340007f ++ ++/*P2_KDIV23*/ ++#define RSTV0910_P2_KDIV23 0xf341 ++#define FSTV0910_P2_KDIV23_MANUAL 0xf3410080 ++#define FSTV0910_P2_K_DIVIDER_23 0xf341007f ++ ++/*P2_KDIV34*/ ++#define RSTV0910_P2_KDIV34 0xf342 ++#define FSTV0910_P2_KDIV34_MANUAL 0xf3420080 ++#define FSTV0910_P2_K_DIVIDER_34 0xf342007f ++ ++/*P2_KDIV56*/ ++#define RSTV0910_P2_KDIV56 0xf343 ++#define FSTV0910_P2_KDIV56_MANUAL 0xf3430080 ++#define FSTV0910_P2_K_DIVIDER_56 0xf343007f ++ ++/*P2_KDIV67*/ ++#define RSTV0910_P2_KDIV67 0xf344 ++#define FSTV0910_P2_KDIV67_MANUAL 0xf3440080 ++#define FSTV0910_P2_K_DIVIDER_67 0xf344007f ++ ++/*P2_KDIV78*/ ++#define RSTV0910_P2_KDIV78 0xf345 ++#define FSTV0910_P2_KDIV78_MANUAL 0xf3450080 ++#define FSTV0910_P2_K_DIVIDER_78 0xf345007f ++ ++/*P2_PDELCTRL0*/ ++#define RSTV0910_P2_PDELCTRL0 0xf34f ++#define FSTV0910_P2_ISIOBS_MODE 0xf34f0030 ++#define FSTV0910_P2_PDELDIS_BITWISE 0xf34f0004 ++ ++/*P2_PDELCTRL1*/ ++#define RSTV0910_P2_PDELCTRL1 0xf350 ++#define FSTV0910_P2_INV_MISMASK 0xf3500080 ++#define FSTV0910_P2_FORCE_ACCEPTED 0xf3500040 ++#define FSTV0910_P2_FILTER_EN 0xf3500020 ++#define FSTV0910_P2_FORCE_PKTDELINUSE 0xf3500010 ++#define FSTV0910_P2_HYSTEN 0xf3500008 ++#define FSTV0910_P2_HYSTSWRST 0xf3500004 ++#define FSTV0910_P2_EN_MIS00 0xf3500002 ++#define FSTV0910_P2_ALGOSWRST 0xf3500001 ++ ++/*P2_PDELCTRL2*/ ++#define RSTV0910_P2_PDELCTRL2 0xf351 ++#define FSTV0910_P2_FORCE_CONTINUOUS 0xf3510080 ++#define FSTV0910_P2_RESET_UPKO_COUNT 0xf3510040 ++#define FSTV0910_P2_USER_PKTDELIN_NB 0xf3510020 ++#define FSTV0910_P2_DATA_UNBBSCRAMBLED 0xf3510008 ++#define FSTV0910_P2_FORCE_LONGPKT 0xf3510004 ++#define FSTV0910_P2_FRAME_MODE 0xf3510002 ++ ++/*P2_HYSTTHRESH*/ ++#define RSTV0910_P2_HYSTTHRESH 0xf354 ++#define FSTV0910_P2_DELIN_LOCKTHRES 0xf35400f0 ++#define FSTV0910_P2_DELIN_UNLOCKTHRES 0xf354000f ++ ++/*P2_ISIENTRY*/ ++#define RSTV0910_P2_ISIENTRY 0xf35e ++#define FSTV0910_P2_ISI_ENTRY 0xf35e00ff ++ ++/*P2_ISIBITENA*/ ++#define RSTV0910_P2_ISIBITENA 0xf35f ++#define FSTV0910_P2_ISI_BIT_EN 0xf35f00ff ++ ++/*P2_MATSTR1*/ ++#define RSTV0910_P2_MATSTR1 0xf360 ++#define FSTV0910_P2_MATYPE_CURRENT1 0xf36000ff ++ ++/*P2_MATSTR0*/ ++#define RSTV0910_P2_MATSTR0 0xf361 ++#define FSTV0910_P2_MATYPE_CURRENT0 0xf36100ff ++ ++/*P2_UPLSTR1*/ ++#define RSTV0910_P2_UPLSTR1 0xf362 ++#define FSTV0910_P2_UPL_CURRENT1 0xf36200ff ++ ++/*P2_UPLSTR0*/ ++#define RSTV0910_P2_UPLSTR0 0xf363 ++#define FSTV0910_P2_UPL_CURRENT0 0xf36300ff ++ ++/*P2_DFLSTR1*/ ++#define RSTV0910_P2_DFLSTR1 0xf364 ++#define FSTV0910_P2_DFL_CURRENT1 0xf36400ff ++ ++/*P2_DFLSTR0*/ ++#define RSTV0910_P2_DFLSTR0 0xf365 ++#define FSTV0910_P2_DFL_CURRENT0 0xf36500ff ++ ++/*P2_SYNCSTR*/ ++#define RSTV0910_P2_SYNCSTR 0xf366 ++#define FSTV0910_P2_SYNC_CURRENT 0xf36600ff ++ ++/*P2_SYNCDSTR1*/ ++#define RSTV0910_P2_SYNCDSTR1 0xf367 ++#define FSTV0910_P2_SYNCD_CURRENT1 0xf36700ff ++ ++/*P2_SYNCDSTR0*/ ++#define RSTV0910_P2_SYNCDSTR0 0xf368 ++#define FSTV0910_P2_SYNCD_CURRENT0 0xf36800ff ++ ++/*P2_PDELSTATUS1*/ ++#define RSTV0910_P2_PDELSTATUS1 0xf369 ++#define FSTV0910_P2_PKTDELIN_DELOCK 0xf3690080 ++#define FSTV0910_P2_SYNCDUPDFL_BADDFL 0xf3690040 ++#define FSTV0910_P2_CONTINUOUS_STREAM 0xf3690020 ++#define FSTV0910_P2_UNACCEPTED_STREAM 0xf3690010 ++#define FSTV0910_P2_BCH_ERROR_FLAG 0xf3690008 ++#define FSTV0910_P2_BBHCRCKO 0xf3690004 ++#define FSTV0910_P2_PKTDELIN_LOCK 0xf3690002 ++#define FSTV0910_P2_FIRST_LOCK 0xf3690001 ++ ++/*P2_PDELSTATUS2*/ ++#define RSTV0910_P2_PDELSTATUS2 0xf36a ++#define FSTV0910_P2_PKTDEL_DEMODSEL 0xf36a0080 ++#define FSTV0910_P2_FRAME_MODCOD 0xf36a007c ++#define FSTV0910_P2_FRAME_TYPE 0xf36a0003 ++ ++/*P2_BBFCRCKO1*/ ++#define RSTV0910_P2_BBFCRCKO1 0xf36b ++#define FSTV0910_P2_BBHCRC_KOCNT1 0xf36b00ff ++ ++/*P2_BBFCRCKO0*/ ++#define RSTV0910_P2_BBFCRCKO0 0xf36c ++#define FSTV0910_P2_BBHCRC_KOCNT0 0xf36c00ff ++ ++/*P2_UPCRCKO1*/ ++#define RSTV0910_P2_UPCRCKO1 0xf36d ++#define FSTV0910_P2_PKTCRC_KOCNT1 0xf36d00ff ++ ++/*P2_UPCRCKO0*/ ++#define RSTV0910_P2_UPCRCKO0 0xf36e ++#define FSTV0910_P2_PKTCRC_KOCNT0 0xf36e00ff ++ ++/*P2_PDELCTRL3*/ ++#define RSTV0910_P2_PDELCTRL3 0xf36f ++#define FSTV0910_P2_PKTDEL_CONTFAIL 0xf36f0080 ++#define FSTV0910_P2_PKTDEL_ENLONGPKT 0xf36f0040 ++#define FSTV0910_P2_NOFIFO_BCHERR 0xf36f0020 ++#define FSTV0910_P2_PKTDELIN_DELACMERR 0xf36f0010 ++#define FSTV0910_P2_SATURATE_BBPKTKO 0xf36f0004 ++#define FSTV0910_P2_PKTDEL_BCHERRCONT 0xf36f0002 ++#define FSTV0910_P2_ETHERNET_DISFCS 0xf36f0001 ++ ++/*P2_TSSTATEM*/ ++#define RSTV0910_P2_TSSTATEM 0xf370 ++#define FSTV0910_P2_TSDIL_ON 0xf3700080 ++#define FSTV0910_P2_TSSKIPRS_ON 0xf3700040 ++#define FSTV0910_P2_TSRS_ON 0xf3700020 ++#define FSTV0910_P2_TSDESCRAMB_ON 0xf3700010 ++#define FSTV0910_P2_TSFRAME_MODE 0xf3700008 ++#define FSTV0910_P2_TS_DISABLE 0xf3700004 ++#define FSTV0910_P2_TSACM_MODE 0xf3700002 ++#define FSTV0910_P2_TSOUT_NOSYNC 0xf3700001 ++ ++/*P2_TSCFGH*/ ++#define RSTV0910_P2_TSCFGH 0xf372 ++#define FSTV0910_P2_TSFIFO_DVBCI 0xf3720080 ++#define FSTV0910_P2_TSFIFO_SERIAL 0xf3720040 ++#define FSTV0910_P2_TSFIFO_TEIUPDATE 0xf3720020 ++#define FSTV0910_P2_TSFIFO_DUTY50 0xf3720010 ++#define FSTV0910_P2_TSFIFO_HSGNLOUT 0xf3720008 ++#define FSTV0910_P2_TSFIFO_ERRMODE 0xf3720006 ++#define FSTV0910_P2_RST_HWARE 0xf3720001 ++ ++/*P2_TSCFGM*/ ++#define RSTV0910_P2_TSCFGM 0xf373 ++#define FSTV0910_P2_TSFIFO_MANSPEED 0xf37300c0 ++#define FSTV0910_P2_TSFIFO_PERMDATA 0xf3730020 ++#define FSTV0910_P2_TSFIFO_NONEWSGNL 0xf3730010 ++#define FSTV0910_P2_NPD_SPECDVBS2 0xf3730004 ++#define FSTV0910_P2_TSFIFO_DPUNACTIVE 0xf3730002 ++#define FSTV0910_P2_TSFIFO_INVDATA 0xf3730001 ++ ++/*P2_TSCFGL*/ ++#define RSTV0910_P2_TSCFGL 0xf374 ++#define FSTV0910_P2_TSFIFO_BCLKDEL1CK 0xf37400c0 ++#define FSTV0910_P2_BCHERROR_MODE 0xf3740030 ++#define FSTV0910_P2_TSFIFO_NSGNL2DATA 0xf3740008 ++#define FSTV0910_P2_TSFIFO_EMBINDVB 0xf3740004 ++#define FSTV0910_P2_TSFIFO_BITSPEED 0xf3740003 ++ ++/*P2_TSINSDELH*/ ++#define RSTV0910_P2_TSINSDELH 0xf376 ++#define FSTV0910_P2_TSDEL_SYNCBYTE 0xf3760080 ++#define FSTV0910_P2_TSDEL_XXHEADER 0xf3760040 ++#define FSTV0910_P2_TSDEL_BBHEADER 0xf3760020 ++#define FSTV0910_P2_TSDEL_DATAFIELD 0xf3760010 ++#define FSTV0910_P2_TSINSDEL_ISCR 0xf3760008 ++#define FSTV0910_P2_TSINSDEL_NPD 0xf3760004 ++#define FSTV0910_P2_TSINSDEL_RSPARITY 0xf3760002 ++#define FSTV0910_P2_TSINSDEL_CRC8 0xf3760001 ++ ++/*P2_TSDIVN*/ ++#define RSTV0910_P2_TSDIVN 0xf379 ++#define FSTV0910_P2_TSFIFO_SPEEDMODE 0xf37900c0 ++#define FSTV0910_P2_BYTE_OVERSAMPLING 0xf3790038 ++#define FSTV0910_P2_TSFIFO_RISEOK 0xf3790007 ++ ++/*P2_TSCFG4*/ ++#define RSTV0910_P2_TSCFG4 0xf37a ++#define FSTV0910_P2_TSFIFO_TSSPEEDMODE 0xf37a00c0 ++#define FSTV0910_P2_TSFIFO_HIERSEL 0xf37a0020 ++#define FSTV0910_P2_TSFIFO_SPECTOKEN 0xf37a0010 ++#define FSTV0910_P2_TSFIFO_MAXMODE 0xf37a0008 ++#define FSTV0910_P2_TSFIFO_FRFORCEPKT 0xf37a0004 ++#define FSTV0910_P2_EXT_FECSPYIN 0xf37a0002 ++#define FSTV0910_P2_TSFIFO_DELSPEEDUP 0xf37a0001 ++ ++/*P2_TSSPEED*/ ++#define RSTV0910_P2_TSSPEED 0xf380 ++#define FSTV0910_P2_TSFIFO_OUTSPEED 0xf38000ff ++ ++/*P2_TSSTATUS*/ ++#define RSTV0910_P2_TSSTATUS 0xf381 ++#define FSTV0910_P2_TSFIFO_LINEOK 0xf3810080 ++#define FSTV0910_P2_TSFIFO_ERROR 0xf3810040 ++#define FSTV0910_P2_TSFIFO_DATA7 0xf3810020 ++#define FSTV0910_P2_TSFIFO_NOSYNC 0xf3810010 ++#define FSTV0910_P2_ISCR_INITIALIZED 0xf3810008 ++#define FSTV0910_P2_TSREGUL_ERROR 0xf3810004 ++#define FSTV0910_P2_SOFFIFO_UNREGUL 0xf3810002 ++#define FSTV0910_P2_DIL_READY 0xf3810001 ++ ++/*P2_TSSTATUS2*/ ++#define RSTV0910_P2_TSSTATUS2 0xf382 ++#define FSTV0910_P2_TSFIFO_DEMODSEL 0xf3820080 ++#define FSTV0910_P2_TSFIFOSPEED_STORE 0xf3820040 ++#define FSTV0910_P2_DILXX_RESET 0xf3820020 ++#define FSTV0910_P2_TSSPEED_IMPOSSIBLE 0xf3820010 ++#define FSTV0910_P2_TSFIFO_LINENOK 0xf3820008 ++#define FSTV0910_P2_TSFIFO_MUXSTREAM 0xf3820004 ++#define FSTV0910_P2_SCRAMBDETECT 0xf3820002 ++#define FSTV0910_P2_ULDTV67_FALSELOCK 0xf3820001 ++ ++/*P2_TSBITRATE1*/ ++#define RSTV0910_P2_TSBITRATE1 0xf383 ++#define FSTV0910_P2_TSFIFO_BITRATE1 0xf38300ff ++ ++/*P2_TSBITRATE0*/ ++#define RSTV0910_P2_TSBITRATE0 0xf384 ++#define FSTV0910_P2_TSFIFO_BITRATE0 0xf38400ff ++ ++/*P2_ERRCTRL1*/ ++#define RSTV0910_P2_ERRCTRL1 0xf398 ++#define FSTV0910_P2_ERR_SOURCE1 0xf39800f0 ++#define FSTV0910_P2_NUM_EVENT1 0xf3980007 ++ ++/*P2_ERRCNT12*/ ++#define RSTV0910_P2_ERRCNT12 0xf399 ++#define FSTV0910_P2_ERRCNT1_OLDVALUE 0xf3990080 ++#define FSTV0910_P2_ERR_CNT12 0xf399007f ++ ++/*P2_ERRCNT11*/ ++#define RSTV0910_P2_ERRCNT11 0xf39a ++#define FSTV0910_P2_ERR_CNT11 0xf39a00ff ++ ++/*P2_ERRCNT10*/ ++#define RSTV0910_P2_ERRCNT10 0xf39b ++#define FSTV0910_P2_ERR_CNT10 0xf39b00ff ++ ++/*P2_ERRCTRL2*/ ++#define RSTV0910_P2_ERRCTRL2 0xf39c ++#define FSTV0910_P2_ERR_SOURCE2 0xf39c00f0 ++#define FSTV0910_P2_NUM_EVENT2 0xf39c0007 ++ ++/*P2_ERRCNT22*/ ++#define RSTV0910_P2_ERRCNT22 0xf39d ++#define FSTV0910_P2_ERRCNT2_OLDVALUE 0xf39d0080 ++#define FSTV0910_P2_ERR_CNT22 0xf39d007f ++ ++/*P2_ERRCNT21*/ ++#define RSTV0910_P2_ERRCNT21 0xf39e ++#define FSTV0910_P2_ERR_CNT21 0xf39e00ff ++ ++/*P2_ERRCNT20*/ ++#define RSTV0910_P2_ERRCNT20 0xf39f ++#define FSTV0910_P2_ERR_CNT20 0xf39f00ff ++ ++/*P2_FECSPY*/ ++#define RSTV0910_P2_FECSPY 0xf3a0 ++#define FSTV0910_P2_SPY_ENABLE 0xf3a00080 ++#define FSTV0910_P2_NO_SYNCBYTE 0xf3a00040 ++#define FSTV0910_P2_SERIAL_MODE 0xf3a00020 ++#define FSTV0910_P2_UNUSUAL_PACKET 0xf3a00010 ++#define FSTV0910_P2_BERMETER_DATAMODE 0xf3a0000c ++#define FSTV0910_P2_BERMETER_LMODE 0xf3a00002 ++#define FSTV0910_P2_BERMETER_RESET 0xf3a00001 ++ ++/*P2_FSPYCFG*/ ++#define RSTV0910_P2_FSPYCFG 0xf3a1 ++#define FSTV0910_P2_FECSPY_INPUT 0xf3a100c0 ++#define FSTV0910_P2_RST_ON_ERROR 0xf3a10020 ++#define FSTV0910_P2_ONE_SHOT 0xf3a10010 ++#define FSTV0910_P2_I2C_MODE 0xf3a1000c ++#define FSTV0910_P2_SPY_HYSTERESIS 0xf3a10003 ++ ++/*P2_FSPYDATA*/ ++#define RSTV0910_P2_FSPYDATA 0xf3a2 ++#define FSTV0910_P2_SPY_STUFFING 0xf3a20080 ++#define FSTV0910_P2_NOERROR_PKTJITTER 0xf3a20040 ++#define FSTV0910_P2_SPY_CNULLPKT 0xf3a20020 ++#define FSTV0910_P2_SPY_OUTDATA_MODE 0xf3a2001f ++ ++/*P2_FSPYOUT*/ ++#define RSTV0910_P2_FSPYOUT 0xf3a3 ++#define FSTV0910_P2_FSPY_DIRECT 0xf3a30080 ++#define FSTV0910_P2_SPY_OUTDATA_BUS 0xf3a30038 ++#define FSTV0910_P2_STUFF_MODE 0xf3a30007 ++ ++/*P2_FSTATUS*/ ++#define RSTV0910_P2_FSTATUS 0xf3a4 ++#define FSTV0910_P2_SPY_ENDSIM 0xf3a40080 ++#define FSTV0910_P2_VALID_SIM 0xf3a40040 ++#define FSTV0910_P2_FOUND_SIGNAL 0xf3a40020 ++#define FSTV0910_P2_DSS_SYNCBYTE 0xf3a40010 ++#define FSTV0910_P2_RESULT_STATE 0xf3a4000f ++ ++/*P2_FBERCPT4*/ ++#define RSTV0910_P2_FBERCPT4 0xf3a8 ++#define FSTV0910_P2_FBERMETER_CPT4 0xf3a800ff ++ ++/*P2_FBERCPT3*/ ++#define RSTV0910_P2_FBERCPT3 0xf3a9 ++#define FSTV0910_P2_FBERMETER_CPT3 0xf3a900ff ++ ++/*P2_FBERCPT2*/ ++#define RSTV0910_P2_FBERCPT2 0xf3aa ++#define FSTV0910_P2_FBERMETER_CPT2 0xf3aa00ff ++ ++/*P2_FBERCPT1*/ ++#define RSTV0910_P2_FBERCPT1 0xf3ab ++#define FSTV0910_P2_FBERMETER_CPT1 0xf3ab00ff ++ ++/*P2_FBERCPT0*/ ++#define RSTV0910_P2_FBERCPT0 0xf3ac ++#define FSTV0910_P2_FBERMETER_CPT0 0xf3ac00ff ++ ++/*P2_FBERERR2*/ ++#define RSTV0910_P2_FBERERR2 0xf3ad ++#define FSTV0910_P2_FBERMETER_ERR2 0xf3ad00ff ++ ++/*P2_FBERERR1*/ ++#define RSTV0910_P2_FBERERR1 0xf3ae ++#define FSTV0910_P2_FBERMETER_ERR1 0xf3ae00ff ++ ++/*P2_FBERERR0*/ ++#define RSTV0910_P2_FBERERR0 0xf3af ++#define FSTV0910_P2_FBERMETER_ERR0 0xf3af00ff ++ ++/*P2_FSPYBER*/ ++#define RSTV0910_P2_FSPYBER 0xf3b2 ++#define FSTV0910_P2_FSPYOBS_XORREAD 0xf3b20040 ++#define FSTV0910_P2_FSPYBER_OBSMODE 0xf3b20020 ++#define FSTV0910_P2_FSPYBER_SYNCBYTE 0xf3b20010 ++#define FSTV0910_P2_FSPYBER_UNSYNC 0xf3b20008 ++#define FSTV0910_P2_FSPYBER_CTIME 0xf3b20007 ++ ++/*P2_SFERROR*/ ++#define RSTV0910_P2_SFERROR 0xf3c1 ++#define FSTV0910_P2_SFEC_REGERR_VIT 0xf3c100ff ++ ++/*P2_SFECSTATUS*/ ++#define RSTV0910_P2_SFECSTATUS 0xf3c3 ++#define FSTV0910_P2_SFEC_ON 0xf3c30080 ++#define FSTV0910_P2_SFEC_OFF 0xf3c30040 ++#define FSTV0910_P2_LOCKEDSFEC 0xf3c30008 ++#define FSTV0910_P2_SFEC_DELOCK 0xf3c30004 ++#define FSTV0910_P2_SFEC_DEMODSEL 0xf3c30002 ++#define FSTV0910_P2_SFEC_OVFON 0xf3c30001 ++ ++/*P2_SFKDIV12*/ ++#define RSTV0910_P2_SFKDIV12 0xf3c4 ++#define FSTV0910_P2_SFECKDIV12_MAN 0xf3c40080 ++#define FSTV0910_P2_SFEC_K_DIVIDER_12 0xf3c4007f ++ ++/*P2_SFKDIV23*/ ++#define RSTV0910_P2_SFKDIV23 0xf3c5 ++#define FSTV0910_P2_SFECKDIV23_MAN 0xf3c50080 ++#define FSTV0910_P2_SFEC_K_DIVIDER_23 0xf3c5007f ++ ++/*P2_SFKDIV34*/ ++#define RSTV0910_P2_SFKDIV34 0xf3c6 ++#define FSTV0910_P2_SFECKDIV34_MAN 0xf3c60080 ++#define FSTV0910_P2_SFEC_K_DIVIDER_34 0xf3c6007f ++ ++/*P2_SFKDIV56*/ ++#define RSTV0910_P2_SFKDIV56 0xf3c7 ++#define FSTV0910_P2_SFECKDIV56_MAN 0xf3c70080 ++#define FSTV0910_P2_SFEC_K_DIVIDER_56 0xf3c7007f ++ ++/*P2_SFKDIV67*/ ++#define RSTV0910_P2_SFKDIV67 0xf3c8 ++#define FSTV0910_P2_SFECKDIV67_MAN 0xf3c80080 ++#define FSTV0910_P2_SFEC_K_DIVIDER_67 0xf3c8007f ++ ++/*P2_SFKDIV78*/ ++#define RSTV0910_P2_SFKDIV78 0xf3c9 ++#define FSTV0910_P2_SFECKDIV78_MAN 0xf3c90080 ++#define FSTV0910_P2_SFEC_K_DIVIDER_78 0xf3c9007f ++ ++/*P2_SFSTATUS*/ ++#define RSTV0910_P2_SFSTATUS 0xf3cc ++#define FSTV0910_P2_SFEC_LINEOK 0xf3cc0080 ++#define FSTV0910_P2_SFEC_ERROR 0xf3cc0040 ++#define FSTV0910_P2_SFEC_DATA7 0xf3cc0020 ++#define FSTV0910_P2_SFEC_PKTDNBRFAIL 0xf3cc0010 ++#define FSTV0910_P2_TSSFEC_DEMODSEL 0xf3cc0008 ++#define FSTV0910_P2_SFEC_NOSYNC 0xf3cc0004 ++#define FSTV0910_P2_SFEC_UNREGULA 0xf3cc0002 ++#define FSTV0910_P2_SFEC_READY 0xf3cc0001 ++ ++/*P2_SFDLYSET2*/ ++#define RSTV0910_P2_SFDLYSET2 0xf3d0 ++#define FSTV0910_P2_SFEC_OFFSET 0xf3d000c0 ++#define FSTV0910_P2_RST_SFEC 0xf3d00008 ++#define FSTV0910_P2_DILDLINE_ERROR 0xf3d00004 ++#define FSTV0910_P2_SFEC_DISABLE 0xf3d00002 ++#define FSTV0910_P2_SFEC_UNREGUL 0xf3d00001 ++ ++/*P2_SFERRCTRL*/ ++#define RSTV0910_P2_SFERRCTRL 0xf3d8 ++#define FSTV0910_P2_SFEC_ERR_SOURCE 0xf3d800f0 ++#define FSTV0910_P2_SFEC_NUM_EVENT 0xf3d80007 ++ ++/*P2_SFERRCNT2*/ ++#define RSTV0910_P2_SFERRCNT2 0xf3d9 ++#define FSTV0910_P2_SFERRC_OLDVALUE 0xf3d90080 ++#define FSTV0910_P2_SFEC_ERR_CNT2 0xf3d9007f ++ ++/*P2_SFERRCNT1*/ ++#define RSTV0910_P2_SFERRCNT1 0xf3da ++#define FSTV0910_P2_SFEC_ERR_CNT1 0xf3da00ff ++ ++/*P2_SFERRCNT0*/ ++#define RSTV0910_P2_SFERRCNT0 0xf3db ++#define FSTV0910_P2_SFEC_ERR_CNT0 0xf3db00ff ++ ++/*P1_IQCONST*/ ++#define RSTV0910_P1_IQCONST 0xf400 ++#define FSTV0910_P1_CONSTEL_SELECT 0xf4000060 ++#define FSTV0910_P1_IQSYMB_SEL 0xf400001f ++ ++/*P1_NOSCFG*/ ++#define RSTV0910_P1_NOSCFG 0xf401 ++#define FSTV0910_P1_DIS_ACMRATIO 0xf4010080 ++#define FSTV0910_P1_NOSIN_EGALSEL 0xf4010040 ++#define FSTV0910_P1_DUMMYPL_NOSDATA 0xf4010020 ++#define FSTV0910_P1_NOSPLH_BETA 0xf4010018 ++#define FSTV0910_P1_NOSDATA_BETA 0xf4010007 ++ ++/*P1_ISYMB*/ ++#define RSTV0910_P1_ISYMB 0xf402 ++#define FSTV0910_P1_I_SYMBOL 0xf40201ff ++ ++/*P1_QSYMB*/ ++#define RSTV0910_P1_QSYMB 0xf403 ++#define FSTV0910_P1_Q_SYMBOL 0xf40301ff ++ ++/*P1_AGC1CFG*/ ++#define RSTV0910_P1_AGC1CFG 0xf404 ++#define FSTV0910_P1_DC_FROZEN 0xf4040080 ++#define FSTV0910_P1_DC_CORRECT 0xf4040040 ++#define FSTV0910_P1_AMM_FROZEN 0xf4040020 ++#define FSTV0910_P1_AMM_CORRECT 0xf4040010 ++#define FSTV0910_P1_QUAD_FROZEN 0xf4040008 ++#define FSTV0910_P1_QUAD_CORRECT 0xf4040004 ++#define FSTV0910_P1_DCCOMP_SLOW 0xf4040002 ++#define FSTV0910_P1_IQMISM_SLOW 0xf4040001 ++ ++/*P1_AGC1CN*/ ++#define RSTV0910_P1_AGC1CN 0xf406 ++#define FSTV0910_P1_AGC1_LOCKED 0xf4060080 ++#define FSTV0910_P1_AGC1_OVERFLOW 0xf4060040 ++#define FSTV0910_P1_AGC1_NOSLOWLK 0xf4060020 ++#define FSTV0910_P1_AGC1_MINPOWER 0xf4060010 ++#define FSTV0910_P1_AGCOUT_FAST 0xf4060008 ++#define FSTV0910_P1_AGCIQ_BETA 0xf4060007 ++ ++/*P1_AGC1REF*/ ++#define RSTV0910_P1_AGC1REF 0xf407 ++#define FSTV0910_P1_AGCIQ_REF 0xf40700ff ++ ++/*P1_IDCCOMP*/ ++#define RSTV0910_P1_IDCCOMP 0xf408 ++#define FSTV0910_P1_IAVERAGE_ADJ 0xf40801ff ++ ++/*P1_QDCCOMP*/ ++#define RSTV0910_P1_QDCCOMP 0xf409 ++#define FSTV0910_P1_QAVERAGE_ADJ 0xf40901ff ++ ++/*P1_POWERI*/ ++#define RSTV0910_P1_POWERI 0xf40a ++#define FSTV0910_P1_POWER_I 0xf40a00ff ++ ++/*P1_POWERQ*/ ++#define RSTV0910_P1_POWERQ 0xf40b ++#define FSTV0910_P1_POWER_Q 0xf40b00ff ++ ++/*P1_AGC1AMM*/ ++#define RSTV0910_P1_AGC1AMM 0xf40c ++#define FSTV0910_P1_AMM_VALUE 0xf40c00ff ++ ++/*P1_AGC1QUAD*/ ++#define RSTV0910_P1_AGC1QUAD 0xf40d ++#define FSTV0910_P1_QUAD_VALUE 0xf40d01ff ++ ++/*P1_AGCIQIN1*/ ++#define RSTV0910_P1_AGCIQIN1 0xf40e ++#define FSTV0910_P1_AGCIQ_VALUE1 0xf40e00ff ++ ++/*P1_AGCIQIN0*/ ++#define RSTV0910_P1_AGCIQIN0 0xf40f ++#define FSTV0910_P1_AGCIQ_VALUE0 0xf40f00ff ++ ++/*P1_DEMOD*/ ++#define RSTV0910_P1_DEMOD 0xf410 ++#define FSTV0910_P1_MANUALS2_ROLLOFF 0xf4100080 ++#define FSTV0910_P1_SPECINV_CONTROL 0xf4100030 ++#define FSTV0910_P1_MANUALSX_ROLLOFF 0xf4100004 ++#define FSTV0910_P1_ROLLOFF_CONTROL 0xf4100003 ++ ++/*P1_DMDMODCOD*/ ++#define RSTV0910_P1_DMDMODCOD 0xf411 ++#define FSTV0910_P1_MANUAL_MODCOD 0xf4110080 ++#define FSTV0910_P1_DEMOD_MODCOD 0xf411007c ++#define FSTV0910_P1_DEMOD_TYPE 0xf4110003 ++ ++/*P1_DSTATUS*/ ++#define RSTV0910_P1_DSTATUS 0xf412 ++#define FSTV0910_P1_CAR_LOCK 0xf4120080 ++#define FSTV0910_P1_TMGLOCK_QUALITY 0xf4120060 ++#define FSTV0910_P1_SDVBS1_ENABLE 0xf4120010 ++#define FSTV0910_P1_LOCK_DEFINITIF 0xf4120008 ++#define FSTV0910_P1_TIMING_IS_LOCKED 0xf4120004 ++#define FSTV0910_P1_DEMOD_SYSCFG 0xf4120002 ++#define FSTV0910_P1_OVADC_DETECT 0xf4120001 ++ ++/*P1_DSTATUS2*/ ++#define RSTV0910_P1_DSTATUS2 0xf413 ++#define FSTV0910_P1_DEMOD_DELOCK 0xf4130080 ++#define FSTV0910_P1_DEMOD_TIMEOUT 0xf4130040 ++#define FSTV0910_P1_MODCODRQ_SYNCTAG 0xf4130020 ++#define FSTV0910_P1_POLYPH_SATEVENT 0xf4130010 ++#define FSTV0910_P1_AGC1_NOSIGNALACK 0xf4130008 ++#define FSTV0910_P1_AGC2_OVERFLOW 0xf4130004 ++#define FSTV0910_P1_CFR_OVERFLOW 0xf4130002 ++#define FSTV0910_P1_GAMMA_OVERUNDER 0xf4130001 ++ ++/*P1_DMDCFGMD*/ ++#define RSTV0910_P1_DMDCFGMD 0xf414 ++#define FSTV0910_P1_DVBS2_ENABLE 0xf4140080 ++#define FSTV0910_P1_DVBS1_ENABLE 0xf4140040 ++#define FSTV0910_P1_SCAN_ENABLE 0xf4140010 ++#define FSTV0910_P1_CFR_AUTOSCAN 0xf4140008 ++#define FSTV0910_P1_NOFORCE_RELOCK 0xf4140004 ++#define FSTV0910_P1_TUN_RNG 0xf4140003 ++ ++/*P1_DMDCFG2*/ ++#define RSTV0910_P1_DMDCFG2 0xf415 ++#define FSTV0910_P1_AGC1_WAITLOCK 0xf4150080 ++#define FSTV0910_P1_S1S2_SEQUENTIAL 0xf4150040 ++#define FSTV0910_P1_BLINDPEA_MODE 0xf4150020 ++#define FSTV0910_P1_INFINITE_RELOCK 0xf4150010 ++#define FSTV0910_P1_BWOFFSET_COLDWARM 0xf4150008 ++#define FSTV0910_P1_TMGLOCK_NSCANSTOP 0xf4150004 ++#define FSTV0910_P1_COARSE_LK3MODE 0xf4150002 ++#define FSTV0910_P1_COARSE_LK2MODE 0xf4150001 ++ ++/*P1_DMDISTATE*/ ++#define RSTV0910_P1_DMDISTATE 0xf416 ++#define FSTV0910_P1_I2C_NORESETDMODE 0xf4160080 ++#define FSTV0910_P1_FORCE_ETAPED 0xf4160040 ++#define FSTV0910_P1_SDMDRST_DIRCLK 0xf4160020 ++#define FSTV0910_P1_I2C_DEMOD_MODE 0xf416001f ++ ++/*P1_DMDT0M*/ ++#define RSTV0910_P1_DMDT0M 0xf417 ++#define FSTV0910_P1_DMDT0_MIN 0xf41700ff ++ ++/*P1_DMDSTATE*/ ++#define RSTV0910_P1_DMDSTATE 0xf41b ++#define FSTV0910_P1_DEMOD_LOCKED 0xf41b0080 ++#define FSTV0910_P1_HEADER_MODE 0xf41b0060 ++#define FSTV0910_P1_DEMOD_MODE 0xf41b001f ++ ++/*P1_DMDFLYW*/ ++#define RSTV0910_P1_DMDFLYW 0xf41c ++#define FSTV0910_P1_I2C_IRQVAL 0xf41c00f0 ++#define FSTV0910_P1_FLYWHEEL_CPT 0xf41c000f ++ ++/*P1_DSTATUS3*/ ++#define RSTV0910_P1_DSTATUS3 0xf41d ++#define FSTV0910_P1_CFR_ZIGZAG 0xf41d0080 ++#define FSTV0910_P1_DEMOD_CFGMODE 0xf41d0060 ++#define FSTV0910_P1_GAMMA_LOWBAUDRATE 0xf41d0010 ++#define FSTV0910_P1_RELOCK_MODE 0xf41d0008 ++#define FSTV0910_P1_DEMOD_FAIL 0xf41d0004 ++#define FSTV0910_P1_ETAPE1A_DVBXMEM 0xf41d0003 ++ ++/*P1_DMDCFG3*/ ++#define RSTV0910_P1_DMDCFG3 0xf41e ++#define FSTV0910_P1_DVBS1_TMGWAIT 0xf41e0080 ++#define FSTV0910_P1_NO_BWCENTERING 0xf41e0040 ++#define FSTV0910_P1_INV_SEQSRCH 0xf41e0020 ++#define FSTV0910_P1_DIS_SFRUPLOW_TRK 0xf41e0010 ++#define FSTV0910_P1_NOSTOP_FIFOFULL 0xf41e0008 ++#define FSTV0910_P1_LOCKTIME_MODE 0xf41e0007 ++ ++/*P1_DMDCFG4*/ ++#define RSTV0910_P1_DMDCFG4 0xf41f ++#define FSTV0910_P1_DIS_VITLOCK 0xf41f0080 ++#define FSTV0910_P1_S1S2TOUT_FAST 0xf41f0040 ++#define FSTV0910_P1_DEMOD_FASTLOCK 0xf41f0020 ++#define FSTV0910_P1_S1HIER_ENABLE 0xf41f0010 ++#define FSTV0910_P1_TUNER_NRELAUNCH 0xf41f0008 ++#define FSTV0910_P1_DIS_CLKENABLE 0xf41f0004 ++#define FSTV0910_P1_DIS_HDRDIVLOCK 0xf41f0002 ++#define FSTV0910_P1_NO_TNRWBINIT 0xf41f0001 ++ ++/*P1_CORRELMANT*/ ++#define RSTV0910_P1_CORRELMANT 0xf420 ++#define FSTV0910_P1_CORREL_MANT 0xf42000ff ++ ++/*P1_CORRELABS*/ ++#define RSTV0910_P1_CORRELABS 0xf421 ++#define FSTV0910_P1_CORREL_ABS 0xf42100ff ++ ++/*P1_CORRELEXP*/ ++#define RSTV0910_P1_CORRELEXP 0xf422 ++#define FSTV0910_P1_CORREL_ABSEXP 0xf42200f0 ++#define FSTV0910_P1_CORREL_EXP 0xf422000f ++ ++/*P1_PLHMODCOD*/ ++#define RSTV0910_P1_PLHMODCOD 0xf424 ++#define FSTV0910_P1_SPECINV_DEMOD 0xf4240080 ++#define FSTV0910_P1_PLH_MODCOD 0xf424007c ++#define FSTV0910_P1_PLH_TYPE 0xf4240003 ++ ++/*P1_DMDREG*/ ++#define RSTV0910_P1_DMDREG 0xf425 ++#define FSTV0910_P1_EXTPSK_MODE 0xf4250080 ++#define FSTV0910_P1_HIER_SHORTFRAME 0xf4250002 ++#define FSTV0910_P1_DECIM_PLFRAMES 0xf4250001 ++ ++/*P1_AGC2O*/ ++#define RSTV0910_P1_AGC2O 0xf42c ++#define FSTV0910_P1_CSTENV_MODE 0xf42c00c0 ++#define FSTV0910_P1_AGC2_LKSQRT 0xf42c0020 ++#define FSTV0910_P1_AGC2_LKMODE 0xf42c0010 ++#define FSTV0910_P1_AGC2_LKEQUA 0xf42c0008 ++#define FSTV0910_P1_AGC2_COEF 0xf42c0007 ++ ++/*P1_AGC2REF*/ ++#define RSTV0910_P1_AGC2REF 0xf42d ++#define FSTV0910_P1_AGC2_REF 0xf42d00ff ++ ++/*P1_AGC1ADJ*/ ++#define RSTV0910_P1_AGC1ADJ 0xf42e ++#define FSTV0910_P1_AGC1ADJ_MANUAL 0xf42e0080 ++#define FSTV0910_P1_AGC1_ADJUSTED 0xf42e007f ++ ++/*P1_AGC2I1*/ ++#define RSTV0910_P1_AGC2I1 0xf436 ++#define FSTV0910_P1_AGC2_INTEGRATOR1 0xf43600ff ++ ++/*P1_AGC2I0*/ ++#define RSTV0910_P1_AGC2I0 0xf437 ++#define FSTV0910_P1_AGC2_INTEGRATOR0 0xf43700ff ++ ++/*P1_CARCFG*/ ++#define RSTV0910_P1_CARCFG 0xf438 ++#define FSTV0910_P1_CFRUPLOW_AUTO 0xf4380080 ++#define FSTV0910_P1_CFRUPLOW_TEST 0xf4380040 ++#define FSTV0910_P1_WIDE_FREQDET 0xf4380020 ++#define FSTV0910_P1_CARHDR_NODIV8 0xf4380010 ++#define FSTV0910_P1_I2C_ROTA 0xf4380008 ++#define FSTV0910_P1_ROTAON 0xf4380004 ++#define FSTV0910_P1_PH_DET_ALGO 0xf4380003 ++ ++/*P1_ACLC*/ ++#define RSTV0910_P1_ACLC 0xf439 ++#define FSTV0910_P1_CARS1_ANOSAUTO 0xf4390040 ++#define FSTV0910_P1_CAR_ALPHA_MANT 0xf4390030 ++#define FSTV0910_P1_CAR_ALPHA_EXP 0xf439000f ++ ++/*P1_BCLC*/ ++#define RSTV0910_P1_BCLC 0xf43a ++#define FSTV0910_P1_CARS1_BNOSAUTO 0xf43a0040 ++#define FSTV0910_P1_CAR_BETA_MANT 0xf43a0030 ++#define FSTV0910_P1_CAR_BETA_EXP 0xf43a000f ++ ++/*P1_CARFREQ*/ ++#define RSTV0910_P1_CARFREQ 0xf43d ++#define FSTV0910_P1_KC_COARSE_EXP 0xf43d00f0 ++#define FSTV0910_P1_BETA_FREQ 0xf43d000f ++ ++/*P1_CARHDR*/ ++#define RSTV0910_P1_CARHDR 0xf43e ++#define FSTV0910_P1_K_FREQ_HDR 0xf43e00ff ++ ++/*P1_LDT*/ ++#define RSTV0910_P1_LDT 0xf43f ++#define FSTV0910_P1_CARLOCK_THRES 0xf43f01ff ++ ++/*P1_LDT2*/ ++#define RSTV0910_P1_LDT2 0xf440 ++#define FSTV0910_P1_CARLOCK_THRES2 0xf44001ff ++ ++/*P1_CFRICFG*/ ++#define RSTV0910_P1_CFRICFG 0xf441 ++#define FSTV0910_P1_CFRINIT_UNVALRNG 0xf4410080 ++#define FSTV0910_P1_CFRINIT_LUNVALCPT 0xf4410040 ++#define FSTV0910_P1_CFRINIT_ABORTDBL 0xf4410020 ++#define FSTV0910_P1_CFRINIT_ABORTPRED 0xf4410010 ++#define FSTV0910_P1_CFRINIT_UNVALSKIP 0xf4410008 ++#define FSTV0910_P1_CFRINIT_CSTINC 0xf4410004 ++#define FSTV0910_P1_CFRIROLL_GARDER 0xf4410002 ++#define FSTV0910_P1_NEG_CFRSTEP 0xf4410001 ++ ++/*P1_CFRUP1*/ ++#define RSTV0910_P1_CFRUP1 0xf442 ++#define FSTV0910_P1_CFR_UP1 0xf44201ff ++ ++/*P1_CFRUP0*/ ++#define RSTV0910_P1_CFRUP0 0xf443 ++#define FSTV0910_P1_CFR_UP0 0xf44300ff ++ ++/*P1_CFRIBASE1*/ ++#define RSTV0910_P1_CFRIBASE1 0xf444 ++#define FSTV0910_P1_CFRINIT_BASE1 0xf44400ff ++ ++/*P1_CFRIBASE0*/ ++#define RSTV0910_P1_CFRIBASE0 0xf445 ++#define FSTV0910_P1_CFRINIT_BASE0 0xf44500ff ++ ++/*P1_CFRLOW1*/ ++#define RSTV0910_P1_CFRLOW1 0xf446 ++#define FSTV0910_P1_CFR_LOW1 0xf44601ff ++ ++/*P1_CFRLOW0*/ ++#define RSTV0910_P1_CFRLOW0 0xf447 ++#define FSTV0910_P1_CFR_LOW0 0xf44700ff ++ ++/*P1_CFRINIT1*/ ++#define RSTV0910_P1_CFRINIT1 0xf448 ++#define FSTV0910_P1_CFR_INIT1 0xf44801ff ++ ++/*P1_CFRINIT0*/ ++#define RSTV0910_P1_CFRINIT0 0xf449 ++#define FSTV0910_P1_CFR_INIT0 0xf44900ff ++ ++/*P1_CFRINC1*/ ++#define RSTV0910_P1_CFRINC1 0xf44a ++#define FSTV0910_P1_MANUAL_CFRINC 0xf44a0080 ++#define FSTV0910_P1_CFR_INC1 0xf44a003f ++ ++/*P1_CFRINC0*/ ++#define RSTV0910_P1_CFRINC0 0xf44b ++#define FSTV0910_P1_CFR_INC0 0xf44b00ff ++ ++/*P1_CFR2*/ ++#define RSTV0910_P1_CFR2 0xf44c ++#define FSTV0910_P1_CAR_FREQ2 0xf44c01ff ++ ++/*P1_CFR1*/ ++#define RSTV0910_P1_CFR1 0xf44d ++#define FSTV0910_P1_CAR_FREQ1 0xf44d00ff ++ ++/*P1_CFR0*/ ++#define RSTV0910_P1_CFR0 0xf44e ++#define FSTV0910_P1_CAR_FREQ0 0xf44e00ff ++ ++/*P1_LDI*/ ++#define RSTV0910_P1_LDI 0xf44f ++#define FSTV0910_P1_LOCK_DET_INTEGR 0xf44f01ff ++ ++/*P1_TMGCFG*/ ++#define RSTV0910_P1_TMGCFG 0xf450 ++#define FSTV0910_P1_TMGLOCK_BETA 0xf45000c0 ++#define FSTV0910_P1_DO_TIMING_CORR 0xf4500010 ++#define FSTV0910_P1_MANUAL_SCAN 0xf450000c ++#define FSTV0910_P1_TMG_MINFREQ 0xf4500003 ++ ++/*P1_RTC*/ ++#define RSTV0910_P1_RTC 0xf451 ++#define FSTV0910_P1_TMGALPHA_EXP 0xf45100f0 ++#define FSTV0910_P1_TMGBETA_EXP 0xf451000f ++ ++/*P1_RTCS2*/ ++#define RSTV0910_P1_RTCS2 0xf452 ++#define FSTV0910_P1_TMGALPHAS2_EXP 0xf45200f0 ++#define FSTV0910_P1_TMGBETAS2_EXP 0xf452000f ++ ++/*P1_TMGTHRISE*/ ++#define RSTV0910_P1_TMGTHRISE 0xf453 ++#define FSTV0910_P1_TMGLOCK_THRISE 0xf45300ff ++ ++/*P1_TMGTHFALL*/ ++#define RSTV0910_P1_TMGTHFALL 0xf454 ++#define FSTV0910_P1_TMGLOCK_THFALL 0xf45400ff ++ ++/*P1_SFRUPRATIO*/ ++#define RSTV0910_P1_SFRUPRATIO 0xf455 ++#define FSTV0910_P1_SFR_UPRATIO 0xf45500ff ++ ++/*P1_SFRLOWRATIO*/ ++#define RSTV0910_P1_SFRLOWRATIO 0xf456 ++#define FSTV0910_P1_SFR_LOWRATIO 0xf45600ff ++ ++/*P1_KTTMG*/ ++#define RSTV0910_P1_KTTMG 0xf457 ++#define FSTV0910_P1_KT_TMG_EXP 0xf45700f0 ++ ++/*P1_KREFTMG*/ ++#define RSTV0910_P1_KREFTMG 0xf458 ++#define FSTV0910_P1_KREF_TMG 0xf45800ff ++ ++/*P1_SFRSTEP*/ ++#define RSTV0910_P1_SFRSTEP 0xf459 ++#define FSTV0910_P1_SFR_SCANSTEP 0xf45900f0 ++#define FSTV0910_P1_SFR_CENTERSTEP 0xf459000f ++ ++/*P1_TMGCFG2*/ ++#define RSTV0910_P1_TMGCFG2 0xf45a ++#define FSTV0910_P1_KREFTMG2_DECMODE 0xf45a00c0 ++#define FSTV0910_P1_DIS_AUTOSAMP 0xf45a0008 ++#define FSTV0910_P1_SCANINIT_QUART 0xf45a0004 ++#define FSTV0910_P1_NOTMG_DVBS1DERAT 0xf45a0002 ++#define FSTV0910_P1_SFRRATIO_FINE 0xf45a0001 ++ ++/*P1_KREFTMG2*/ ++#define RSTV0910_P1_KREFTMG2 0xf45b ++#define FSTV0910_P1_KREF_TMG2 0xf45b00ff ++ ++/*P1_TMGCFG3*/ ++#define RSTV0910_P1_TMGCFG3 0xf45d ++#define FSTV0910_P1_CFRINC_MODE 0xf45d0070 ++#define FSTV0910_P1_CONT_TMGCENTER 0xf45d0008 ++#define FSTV0910_P1_AUTO_GUP 0xf45d0004 ++#define FSTV0910_P1_AUTO_GLOW 0xf45d0002 ++#define FSTV0910_P1_SFRVAL_MINMODE 0xf45d0001 ++ ++/*P1_SFRINIT1*/ ++#define RSTV0910_P1_SFRINIT1 0xf45e ++#define FSTV0910_P1_SFR_INIT1 0xf45e00ff ++ ++/*P1_SFRINIT0*/ ++#define RSTV0910_P1_SFRINIT0 0xf45f ++#define FSTV0910_P1_SFR_INIT0 0xf45f00ff ++ ++/*P1_SFRUP1*/ ++#define RSTV0910_P1_SFRUP1 0xf460 ++#define FSTV0910_P1_SYMB_FREQ_UP1 0xf46000ff ++ ++/*P1_SFRUP0*/ ++#define RSTV0910_P1_SFRUP0 0xf461 ++#define FSTV0910_P1_SYMB_FREQ_UP0 0xf46100ff ++ ++/*P1_SFRLOW1*/ ++#define RSTV0910_P1_SFRLOW1 0xf462 ++#define FSTV0910_P1_SYMB_FREQ_LOW1 0xf46200ff ++ ++/*P1_SFRLOW0*/ ++#define RSTV0910_P1_SFRLOW0 0xf463 ++#define FSTV0910_P1_SYMB_FREQ_LOW0 0xf46300ff ++ ++/*P1_SFR3*/ ++#define RSTV0910_P1_SFR3 0xf464 ++#define FSTV0910_P1_SYMB_FREQ3 0xf46400ff ++ ++/*P1_SFR2*/ ++#define RSTV0910_P1_SFR2 0xf465 ++#define FSTV0910_P1_SYMB_FREQ2 0xf46500ff ++ ++/*P1_SFR1*/ ++#define RSTV0910_P1_SFR1 0xf466 ++#define FSTV0910_P1_SYMB_FREQ1 0xf46600ff ++ ++/*P1_SFR0*/ ++#define RSTV0910_P1_SFR0 0xf467 ++#define FSTV0910_P1_SYMB_FREQ0 0xf46700ff ++ ++/*P1_TMGREG2*/ ++#define RSTV0910_P1_TMGREG2 0xf468 ++#define FSTV0910_P1_TMGREG2 0xf46800ff ++ ++/*P1_TMGREG1*/ ++#define RSTV0910_P1_TMGREG1 0xf469 ++#define FSTV0910_P1_TMGREG1 0xf46900ff ++ ++/*P1_TMGREG0*/ ++#define RSTV0910_P1_TMGREG0 0xf46a ++#define FSTV0910_P1_TMGREG0 0xf46a00ff ++ ++/*P1_TMGLOCK1*/ ++#define RSTV0910_P1_TMGLOCK1 0xf46b ++#define FSTV0910_P1_TMGLOCK_LEVEL1 0xf46b01ff ++ ++/*P1_TMGLOCK0*/ ++#define RSTV0910_P1_TMGLOCK0 0xf46c ++#define FSTV0910_P1_TMGLOCK_LEVEL0 0xf46c00ff ++ ++/*P1_TMGOBS*/ ++#define RSTV0910_P1_TMGOBS 0xf46d ++#define FSTV0910_P1_ROLLOFF_STATUS 0xf46d00c0 ++#define FSTV0910_P1_SCAN_SIGN 0xf46d0030 ++#define FSTV0910_P1_TMG_SCANNING 0xf46d0008 ++#define FSTV0910_P1_CHCENTERING_MODE 0xf46d0004 ++#define FSTV0910_P1_TMG_SCANFAIL 0xf46d0002 ++ ++/*P1_EQUALCFG*/ ++#define RSTV0910_P1_EQUALCFG 0xf46f ++#define FSTV0910_P1_NOTMG_NEGALWAIT 0xf46f0080 ++#define FSTV0910_P1_EQUAL_ON 0xf46f0040 ++#define FSTV0910_P1_SEL_EQUALCOR 0xf46f0038 ++#define FSTV0910_P1_MU_EQUALDFE 0xf46f0007 ++ ++/*P1_EQUAI1*/ ++#define RSTV0910_P1_EQUAI1 0xf470 ++#define FSTV0910_P1_EQUA_ACCI1 0xf47001ff ++ ++/*P1_EQUAQ1*/ ++#define RSTV0910_P1_EQUAQ1 0xf471 ++#define FSTV0910_P1_EQUA_ACCQ1 0xf47101ff ++ ++/*P1_EQUAI2*/ ++#define RSTV0910_P1_EQUAI2 0xf472 ++#define FSTV0910_P1_EQUA_ACCI2 0xf47201ff ++ ++/*P1_EQUAQ2*/ ++#define RSTV0910_P1_EQUAQ2 0xf473 ++#define FSTV0910_P1_EQUA_ACCQ2 0xf47301ff ++ ++/*P1_EQUAI3*/ ++#define RSTV0910_P1_EQUAI3 0xf474 ++#define FSTV0910_P1_EQUA_ACCI3 0xf47401ff ++ ++/*P1_EQUAQ3*/ ++#define RSTV0910_P1_EQUAQ3 0xf475 ++#define FSTV0910_P1_EQUA_ACCQ3 0xf47501ff ++ ++/*P1_EQUAI4*/ ++#define RSTV0910_P1_EQUAI4 0xf476 ++#define FSTV0910_P1_EQUA_ACCI4 0xf47601ff ++ ++/*P1_EQUAQ4*/ ++#define RSTV0910_P1_EQUAQ4 0xf477 ++#define FSTV0910_P1_EQUA_ACCQ4 0xf47701ff ++ ++/*P1_EQUAI5*/ ++#define RSTV0910_P1_EQUAI5 0xf478 ++#define FSTV0910_P1_EQUA_ACCI5 0xf47801ff ++ ++/*P1_EQUAQ5*/ ++#define RSTV0910_P1_EQUAQ5 0xf479 ++#define FSTV0910_P1_EQUA_ACCQ5 0xf47901ff ++ ++/*P1_EQUAI6*/ ++#define RSTV0910_P1_EQUAI6 0xf47a ++#define FSTV0910_P1_EQUA_ACCI6 0xf47a01ff ++ ++/*P1_EQUAQ6*/ ++#define RSTV0910_P1_EQUAQ6 0xf47b ++#define FSTV0910_P1_EQUA_ACCQ6 0xf47b01ff ++ ++/*P1_EQUAI7*/ ++#define RSTV0910_P1_EQUAI7 0xf47c ++#define FSTV0910_P1_EQUA_ACCI7 0xf47c01ff ++ ++/*P1_EQUAQ7*/ ++#define RSTV0910_P1_EQUAQ7 0xf47d ++#define FSTV0910_P1_EQUA_ACCQ7 0xf47d01ff ++ ++/*P1_EQUAI8*/ ++#define RSTV0910_P1_EQUAI8 0xf47e ++#define FSTV0910_P1_EQUA_ACCI8 0xf47e01ff ++ ++/*P1_EQUAQ8*/ ++#define RSTV0910_P1_EQUAQ8 0xf47f ++#define FSTV0910_P1_EQUA_ACCQ8 0xf47f01ff ++ ++/*P1_NNOSDATAT1*/ ++#define RSTV0910_P1_NNOSDATAT1 0xf480 ++#define FSTV0910_P1_NOSDATAT_NORMED1 0xf48000ff ++ ++/*P1_NNOSDATAT0*/ ++#define RSTV0910_P1_NNOSDATAT0 0xf481 ++#define FSTV0910_P1_NOSDATAT_NORMED0 0xf48100ff ++ ++/*P1_NNOSDATA1*/ ++#define RSTV0910_P1_NNOSDATA1 0xf482 ++#define FSTV0910_P1_NOSDATA_NORMED1 0xf48200ff ++ ++/*P1_NNOSDATA0*/ ++#define RSTV0910_P1_NNOSDATA0 0xf483 ++#define FSTV0910_P1_NOSDATA_NORMED0 0xf48300ff ++ ++/*P1_NNOSPLHT1*/ ++#define RSTV0910_P1_NNOSPLHT1 0xf484 ++#define FSTV0910_P1_NOSPLHT_NORMED1 0xf48400ff ++ ++/*P1_NNOSPLHT0*/ ++#define RSTV0910_P1_NNOSPLHT0 0xf485 ++#define FSTV0910_P1_NOSPLHT_NORMED0 0xf48500ff ++ ++/*P1_NNOSPLH1*/ ++#define RSTV0910_P1_NNOSPLH1 0xf486 ++#define FSTV0910_P1_NOSPLH_NORMED1 0xf48600ff ++ ++/*P1_NNOSPLH0*/ ++#define RSTV0910_P1_NNOSPLH0 0xf487 ++#define FSTV0910_P1_NOSPLH_NORMED0 0xf48700ff ++ ++/*P1_NOSDATAT1*/ ++#define RSTV0910_P1_NOSDATAT1 0xf488 ++#define FSTV0910_P1_NOSDATAT_UNNORMED1 0xf48800ff ++ ++/*P1_NOSDATAT0*/ ++#define RSTV0910_P1_NOSDATAT0 0xf489 ++#define FSTV0910_P1_NOSDATAT_UNNORMED0 0xf48900ff ++ ++/*P1_NNOSFRAME1*/ ++#define RSTV0910_P1_NNOSFRAME1 0xf48a ++#define FSTV0910_P1_NOSFRAME_NORMED1 0xf48a00ff ++ ++/*P1_NNOSFRAME0*/ ++#define RSTV0910_P1_NNOSFRAME0 0xf48b ++#define FSTV0910_P1_NOSFRAME_NORMED0 0xf48b00ff ++ ++/*P1_NNOSRAD1*/ ++#define RSTV0910_P1_NNOSRAD1 0xf48c ++#define FSTV0910_P1_NOSRADIAL_NORMED1 0xf48c00ff ++ ++/*P1_NNOSRAD0*/ ++#define RSTV0910_P1_NNOSRAD0 0xf48d ++#define FSTV0910_P1_NOSRADIAL_NORMED0 0xf48d00ff ++ ++/*P1_NOSCFGF1*/ ++#define RSTV0910_P1_NOSCFGF1 0xf48e ++#define FSTV0910_P1_LOWNOISE_MESURE 0xf48e0080 ++#define FSTV0910_P1_NOS_DELFRAME 0xf48e0040 ++#define FSTV0910_P1_NOSDATA_MODE 0xf48e0030 ++#define FSTV0910_P1_FRAMESEL_TYPESEL 0xf48e000c ++#define FSTV0910_P1_FRAMESEL_TYPE 0xf48e0003 ++ ++/*P1_CAR2CFG*/ ++#define RSTV0910_P1_CAR2CFG 0xf490 ++#define FSTV0910_P1_DESCRAMB_OFF 0xf4900080 ++#define FSTV0910_P1_EN_PHNOSRAM 0xf4900020 ++#define FSTV0910_P1_STOP_CFR2UPDATE 0xf4900010 ++#define FSTV0910_P1_STOP_NCO2UPDATE 0xf4900008 ++#define FSTV0910_P1_ROTA2ON 0xf4900004 ++#define FSTV0910_P1_PH_DET_ALGO2 0xf4900003 ++ ++/*P1_CFR2CFR1*/ ++#define RSTV0910_P1_CFR2CFR1 0xf491 ++#define FSTV0910_P1_CFR2_S2CONTROL 0xf49100c0 ++#define FSTV0910_P1_EN_S2CAR2CENTER 0xf4910020 ++#define FSTV0910_P1_BCHERRCFR2_MODE 0xf4910018 ++#define FSTV0910_P1_CFR2TOCFR1_BETA 0xf4910007 ++ ++/*P1_CAR3CFG*/ ++#define RSTV0910_P1_CAR3CFG 0xf492 ++#define FSTV0910_P1_CARRIER23_MODE 0xf49200c0 ++#define FSTV0910_P1_CAR3INTERM_DVBS1 0xf4920020 ++#define FSTV0910_P1_ABAMPLIF_MODE 0xf4920018 ++#define FSTV0910_P1_CARRIER3_ALPHA3DL 0xf4920007 ++ ++/*P1_CFR22*/ ++#define RSTV0910_P1_CFR22 0xf493 ++#define FSTV0910_P1_CAR2_FREQ2 0xf49301ff ++ ++/*P1_CFR21*/ ++#define RSTV0910_P1_CFR21 0xf494 ++#define FSTV0910_P1_CAR2_FREQ1 0xf49400ff ++ ++/*P1_CFR20*/ ++#define RSTV0910_P1_CFR20 0xf495 ++#define FSTV0910_P1_CAR2_FREQ0 0xf49500ff ++ ++/*P1_ACLC2S2Q*/ ++#define RSTV0910_P1_ACLC2S2Q 0xf497 ++#define FSTV0910_P1_ENAB_SPSKSYMB 0xf4970080 ++#define FSTV0910_P1_CAR2S2_QANOSAUTO 0xf4970040 ++#define FSTV0910_P1_CAR2S2_Q_ALPH_M 0xf4970030 ++#define FSTV0910_P1_CAR2S2_Q_ALPH_E 0xf497000f ++ ++/*P1_ACLC2S28*/ ++#define RSTV0910_P1_ACLC2S28 0xf498 ++#define FSTV0910_P1_OLDI3Q_MODE 0xf4980080 ++#define FSTV0910_P1_CAR2S2_8ANOSAUTO 0xf4980040 ++#define FSTV0910_P1_CAR2S2_8_ALPH_M 0xf4980030 ++#define FSTV0910_P1_CAR2S2_8_ALPH_E 0xf498000f ++ ++/*P1_ACLC2S216A*/ ++#define RSTV0910_P1_ACLC2S216A 0xf499 ++#define FSTV0910_P1_CAR2S2_16ANOSAUTO 0xf4990040 ++#define FSTV0910_P1_CAR2S2_16A_ALPH_M 0xf4990030 ++#define FSTV0910_P1_CAR2S2_16A_ALPH_E 0xf499000f ++ ++/*P1_ACLC2S232A*/ ++#define RSTV0910_P1_ACLC2S232A 0xf49a ++#define FSTV0910_P1_CAR2S2_32ANOSUATO 0xf49a0040 ++#define FSTV0910_P1_CAR2S2_32A_ALPH_M 0xf49a0030 ++#define FSTV0910_P1_CAR2S2_32A_ALPH_E 0xf49a000f ++ ++/*P1_BCLC2S2Q*/ ++#define RSTV0910_P1_BCLC2S2Q 0xf49c ++#define FSTV0910_P1_DVBS2S2Q_NIP 0xf49c0080 ++#define FSTV0910_P1_CAR2S2_QBNOSAUTO 0xf49c0040 ++#define FSTV0910_P1_CAR2S2_Q_BETA_M 0xf49c0030 ++#define FSTV0910_P1_CAR2S2_Q_BETA_E 0xf49c000f ++ ++/*P1_BCLC2S28*/ ++#define RSTV0910_P1_BCLC2S28 0xf49d ++#define FSTV0910_P1_DVBS2S28_NIP 0xf49d0080 ++#define FSTV0910_P1_CAR2S2_8BNOSAUTO 0xf49d0040 ++#define FSTV0910_P1_CAR2S2_8_BETA_M 0xf49d0030 ++#define FSTV0910_P1_CAR2S2_8_BETA_E 0xf49d000f ++ ++/*P1_PLROOT2*/ ++#define RSTV0910_P1_PLROOT2 0xf4ac ++#define FSTV0910_P1_PLHAUTO_DISPLH 0xf4ac0040 ++#define FSTV0910_P1_PLHAUTO_FASTMODE 0xf4ac0020 ++#define FSTV0910_P1_PLHAUTO_ENABLE 0xf4ac0010 ++#define FSTV0910_P1_PLSCRAMB_MODE 0xf4ac000c ++#define FSTV0910_P1_PLSCRAMB_ROOT2 0xf4ac0003 ++ ++/*P1_PLROOT1*/ ++#define RSTV0910_P1_PLROOT1 0xf4ad ++#define FSTV0910_P1_PLSCRAMB_ROOT1 0xf4ad00ff ++ ++/*P1_PLROOT0*/ ++#define RSTV0910_P1_PLROOT0 0xf4ae ++#define FSTV0910_P1_PLSCRAMB_ROOT0 0xf4ae00ff ++ ++/*P1_MODCODLST7*/ ++#define RSTV0910_P1_MODCODLST7 0xf4b7 ++#define FSTV0910_P1_MODCOD_NNOSFILTER 0xf4b70080 ++#define FSTV0910_P1_MODCODLST_NOSTYPE 0xf4b70040 ++#define FSTV0910_P1_DIS_8PSK_9_10 0xf4b70030 ++#define FSTV0910_P1_DIS_8P_8_9 0xf4b7000f ++ ++/*P1_MODCODLST8*/ ++#define RSTV0910_P1_MODCODLST8 0xf4b8 ++#define FSTV0910_P1_DIS_8P_5_6 0xf4b800f0 ++#define FSTV0910_P1_DIS_8P_3_4 0xf4b8000f ++ ++/*P1_MODCODLST9*/ ++#define RSTV0910_P1_MODCODLST9 0xf4b9 ++#define FSTV0910_P1_DIS_8P_2_3 0xf4b900f0 ++#define FSTV0910_P1_DIS_8P_3_5 0xf4b9000f ++ ++/*P1_MODCODLSTA*/ ++#define RSTV0910_P1_MODCODLSTA 0xf4ba ++#define FSTV0910_P1_NOSFILTER_LIMITE 0xf4ba0080 ++#define FSTV0910_P1_NOSFILTER_MODE 0xf4ba0040 ++#define FSTV0910_P1_DIS_QPSK_9_10 0xf4ba0030 ++#define FSTV0910_P1_DIS_QP_8_9 0xf4ba000f ++ ++/*P1_MODCODLSTB*/ ++#define RSTV0910_P1_MODCODLSTB 0xf4bb ++#define FSTV0910_P1_DIS_QP_5_6 0xf4bb00f0 ++#define FSTV0910_P1_DIS_QP_4_5 0xf4bb000f ++ ++/*P1_MODCODLSTC*/ ++#define RSTV0910_P1_MODCODLSTC 0xf4bc ++#define FSTV0910_P1_DIS_QP_3_4 0xf4bc00f0 ++#define FSTV0910_P1_DIS_QP_2_3 0xf4bc000f ++ ++/*P1_MODCODLSTD*/ ++#define RSTV0910_P1_MODCODLSTD 0xf4bd ++#define FSTV0910_P1_DIS_QPSK_3_5 0xf4bd00f0 ++#define FSTV0910_P1_DIS_QPSK_1_2 0xf4bd000f ++ ++/*P1_GAUSSR0*/ ++#define RSTV0910_P1_GAUSSR0 0xf4c0 ++#define FSTV0910_P1_EN_CCIMODE 0xf4c00080 ++#define FSTV0910_P1_R0_GAUSSIEN 0xf4c0007f ++ ++/*P1_CCIR0*/ ++#define RSTV0910_P1_CCIR0 0xf4c1 ++#define FSTV0910_P1_CCIDETECT_PLHONLY 0xf4c10080 ++#define FSTV0910_P1_R0_CCI 0xf4c1007f ++ ++/*P1_CCIQUANT*/ ++#define RSTV0910_P1_CCIQUANT 0xf4c2 ++#define FSTV0910_P1_CCI_BETA 0xf4c200e0 ++#define FSTV0910_P1_CCI_QUANT 0xf4c2001f ++ ++/*P1_CCITHRES*/ ++#define RSTV0910_P1_CCITHRES 0xf4c3 ++#define FSTV0910_P1_CCI_THRESHOLD 0xf4c300ff ++ ++/*P1_CCIACC*/ ++#define RSTV0910_P1_CCIACC 0xf4c4 ++#define FSTV0910_P1_CCI_VALUE 0xf4c400ff ++ ++/*P1_DSTATUS4*/ ++#define RSTV0910_P1_DSTATUS4 0xf4c5 ++#define FSTV0910_P1_RAINFADE_DETECT 0xf4c50080 ++#define FSTV0910_P1_NOTHRES2_FAIL 0xf4c50040 ++#define FSTV0910_P1_NOTHRES1_FAIL 0xf4c50020 ++#define FSTV0910_P1_PILOT_FAILDETECT 0xf4c50010 ++#define FSTV0910_P1_HIER_DETECT 0xf4c50008 ++#define FSTV0910_P1_DMDPROG_ERROR 0xf4c50004 ++#define FSTV0910_P1_CSTENV_DETECT 0xf4c50002 ++#define FSTV0910_P1_DETECTION_TRIAX 0xf4c50001 ++ ++/*P1_DMDRESCFG*/ ++#define RSTV0910_P1_DMDRESCFG 0xf4c6 ++#define FSTV0910_P1_DMDRES_RESET 0xf4c60080 ++#define FSTV0910_P1_DMDRES_NOISESQR 0xf4c60010 ++#define FSTV0910_P1_DMDRES_STRALL 0xf4c60008 ++#define FSTV0910_P1_DMDRES_NEWONLY 0xf4c60004 ++#define FSTV0910_P1_DMDRES_NOSTORE 0xf4c60002 ++#define FSTV0910_P1_DMDRES_AGC2MEM 0xf4c60001 ++ ++/*P1_DMDRESADR*/ ++#define RSTV0910_P1_DMDRESADR 0xf4c7 ++#define FSTV0910_P1_SUSP_PREDCANAL 0xf4c70080 ++#define FSTV0910_P1_DMDRES_VALIDCFR 0xf4c70040 ++#define FSTV0910_P1_DMDRES_MEMFULL 0xf4c70030 ++#define FSTV0910_P1_DMDRES_RESNBR 0xf4c7000f ++ ++/*P1_DMDRESDATA7*/ ++#define RSTV0910_P1_DMDRESDATA7 0xf4c8 ++#define FSTV0910_P1_DMDRES_DATA7 0xf4c800ff ++ ++/*P1_DMDRESDATA6*/ ++#define RSTV0910_P1_DMDRESDATA6 0xf4c9 ++#define FSTV0910_P1_DMDRES_DATA6 0xf4c900ff ++ ++/*P1_DMDRESDATA5*/ ++#define RSTV0910_P1_DMDRESDATA5 0xf4ca ++#define FSTV0910_P1_DMDRES_DATA5 0xf4ca00ff ++ ++/*P1_DMDRESDATA4*/ ++#define RSTV0910_P1_DMDRESDATA4 0xf4cb ++#define FSTV0910_P1_DMDRES_DATA4 0xf4cb00ff ++ ++/*P1_DMDRESDATA3*/ ++#define RSTV0910_P1_DMDRESDATA3 0xf4cc ++#define FSTV0910_P1_DMDRES_DATA3 0xf4cc00ff ++ ++/*P1_DMDRESDATA2*/ ++#define RSTV0910_P1_DMDRESDATA2 0xf4cd ++#define FSTV0910_P1_DMDRES_DATA2 0xf4cd00ff ++ ++/*P1_DMDRESDATA1*/ ++#define RSTV0910_P1_DMDRESDATA1 0xf4ce ++#define FSTV0910_P1_DMDRES_DATA1 0xf4ce00ff ++ ++/*P1_DMDRESDATA0*/ ++#define RSTV0910_P1_DMDRESDATA0 0xf4cf ++#define FSTV0910_P1_DMDRES_DATA0 0xf4cf00ff ++ ++/*P1_FFEI1*/ ++#define RSTV0910_P1_FFEI1 0xf4d0 ++#define FSTV0910_P1_FFE_ACCI1 0xf4d001ff ++ ++/*P1_FFEQ1*/ ++#define RSTV0910_P1_FFEQ1 0xf4d1 ++#define FSTV0910_P1_FFE_ACCQ1 0xf4d101ff ++ ++/*P1_FFEI2*/ ++#define RSTV0910_P1_FFEI2 0xf4d2 ++#define FSTV0910_P1_FFE_ACCI2 0xf4d201ff ++ ++/*P1_FFEQ2*/ ++#define RSTV0910_P1_FFEQ2 0xf4d3 ++#define FSTV0910_P1_FFE_ACCQ2 0xf4d301ff ++ ++/*P1_FFEI3*/ ++#define RSTV0910_P1_FFEI3 0xf4d4 ++#define FSTV0910_P1_FFE_ACCI3 0xf4d401ff ++ ++/*P1_FFEQ3*/ ++#define RSTV0910_P1_FFEQ3 0xf4d5 ++#define FSTV0910_P1_FFE_ACCQ3 0xf4d501ff ++ ++/*P1_FFEI4*/ ++#define RSTV0910_P1_FFEI4 0xf4d6 ++#define FSTV0910_P1_FFE_ACCI4 0xf4d601ff ++ ++/*P1_FFEQ4*/ ++#define RSTV0910_P1_FFEQ4 0xf4d7 ++#define FSTV0910_P1_FFE_ACCQ4 0xf4d701ff ++ ++/*P1_FFECFG*/ ++#define RSTV0910_P1_FFECFG 0xf4d8 ++#define FSTV0910_P1_EQUALFFE_ON 0xf4d80040 ++#define FSTV0910_P1_EQUAL_USEDSYMB 0xf4d80030 ++#define FSTV0910_P1_MU_EQUALFFE 0xf4d80007 ++ ++/*P1_TNRCFG2*/ ++#define RSTV0910_P1_TNRCFG2 0xf4e1 ++#define FSTV0910_P1_TUN_IQSWAP 0xf4e10080 ++#define FSTV0910_P1_STB6110_STEP2MHZ 0xf4e10040 ++#define FSTV0910_P1_STB6120_DBLI2C 0xf4e10020 ++#define FSTV0910_P1_TUNER_WIDEBAND 0xf4e10010 ++#define FSTV0910_P1_TUNER_OBSPAGE 0xf4e10008 ++#define FSTV0910_P1_DIS_BWCALC 0xf4e10004 ++#define FSTV0910_P1_SHORT_WAITSTATES 0xf4e10002 ++#define FSTV0910_P1_DIS_2BWAGC1 0xf4e10001 ++ ++/*P1_SMAPCOEF7*/ ++#define RSTV0910_P1_SMAPCOEF7 0xf500 ++#define FSTV0910_P1_DIS_QSCALE 0xf5000080 ++#define FSTV0910_P1_SMAPCOEF_Q_LLR12 0xf500017f ++ ++/*P1_SMAPCOEF6*/ ++#define RSTV0910_P1_SMAPCOEF6 0xf501 ++#define FSTV0910_P1_DIS_AGC2SCALE 0xf5010080 ++#define FSTV0910_P1_DIS_16IQMULT 0xf5010040 ++#define FSTV0910_P1_OLD_16APSK47 0xf5010020 ++#define FSTV0910_P1_OLD_16APSK12 0xf5010010 ++#define FSTV0910_P1_DIS_NEWSCALE 0xf5010008 ++#define FSTV0910_P1_ADJ_8PSKLLR1 0xf5010004 ++#define FSTV0910_P1_OLD_8PSKLLR1 0xf5010002 ++#define FSTV0910_P1_DIS_AB8PSK 0xf5010001 ++ ++/*P1_SMAPCOEF5*/ ++#define RSTV0910_P1_SMAPCOEF5 0xf502 ++#define FSTV0910_P1_DIS_8SCALE 0xf5020080 ++#define FSTV0910_P1_SMAPCOEF_8P_LLR23 0xf502017f ++ ++/*P1_NOSTHRES1*/ ++#define RSTV0910_P1_NOSTHRES1 0xf509 ++#define FSTV0910_P1_NOS_THRESHOLD1 0xf50900ff ++ ++/*P1_NOSTHRES2*/ ++#define RSTV0910_P1_NOSTHRES2 0xf50a ++#define FSTV0910_P1_NOS_THRESHOLD2 0xf50a00ff ++ ++/*P1_NOSDIFF1*/ ++#define RSTV0910_P1_NOSDIFF1 0xf50b ++#define FSTV0910_P1_NOSTHRES1_DIFF 0xf50b00ff ++ ++/*P1_RAINFADE*/ ++#define RSTV0910_P1_RAINFADE 0xf50c ++#define FSTV0910_P1_NOSTHRES_DATAT 0xf50c0080 ++#define FSTV0910_P1_RAINFADE_CNLIMIT 0xf50c0070 ++#define FSTV0910_P1_RAINFADE_TIMEOUT 0xf50c0007 ++ ++/*P1_NOSRAMCFG*/ ++#define RSTV0910_P1_NOSRAMCFG 0xf50d ++#define FSTV0910_P1_NOSRAM_DVBS2DATA 0xf50d0080 ++#define FSTV0910_P1_NOSRAM_QUADRAT 0xf50d0040 ++#define FSTV0910_P1_NOSRAM_ACTIVATION 0xf50d0030 ++#define FSTV0910_P1_NOSRAM_CNRONLY 0xf50d0008 ++#define FSTV0910_P1_NOSRAM_LGNCNR1 0xf50d0007 ++ ++/*P1_NOSRAMPOS*/ ++#define RSTV0910_P1_NOSRAMPOS 0xf50e ++#define FSTV0910_P1_NOSRAM_LGNCNR0 0xf50e00f0 ++#define FSTV0910_P1_NOSRAM_VALIDE 0xf50e0004 ++#define FSTV0910_P1_NOSRAM_CNRVAL1 0xf50e0003 ++ ++/*P1_NOSRAMVAL*/ ++#define RSTV0910_P1_NOSRAMVAL 0xf50f ++#define FSTV0910_P1_NOSRAM_CNRVAL0 0xf50f00ff ++ ++/*P1_DMDPLHSTAT*/ ++#define RSTV0910_P1_DMDPLHSTAT 0xf520 ++#define FSTV0910_P1_PLH_STATISTIC 0xf52000ff ++ ++/*P1_LOCKTIME3*/ ++#define RSTV0910_P1_LOCKTIME3 0xf522 ++#define FSTV0910_P1_DEMOD_LOCKTIME3 0xf52200ff ++ ++/*P1_LOCKTIME2*/ ++#define RSTV0910_P1_LOCKTIME2 0xf523 ++#define FSTV0910_P1_DEMOD_LOCKTIME2 0xf52300ff ++ ++/*P1_LOCKTIME1*/ ++#define RSTV0910_P1_LOCKTIME1 0xf524 ++#define FSTV0910_P1_DEMOD_LOCKTIME1 0xf52400ff ++ ++/*P1_LOCKTIME0*/ ++#define RSTV0910_P1_LOCKTIME0 0xf525 ++#define FSTV0910_P1_DEMOD_LOCKTIME0 0xf52500ff ++ ++/*P1_VITSCALE*/ ++#define RSTV0910_P1_VITSCALE 0xf532 ++#define FSTV0910_P1_NVTH_NOSRANGE 0xf5320080 ++#define FSTV0910_P1_VERROR_MAXMODE 0xf5320040 ++#define FSTV0910_P1_KDIV_MODE 0xf5320030 ++#define FSTV0910_P1_NSLOWSN_LOCKED 0xf5320008 ++#define FSTV0910_P1_DELOCK_PRFLOSS 0xf5320004 ++#define FSTV0910_P1_DIS_RSFLOCK 0xf5320002 ++ ++/*P1_FECM*/ ++#define RSTV0910_P1_FECM 0xf533 ++#define FSTV0910_P1_DSS_DVB 0xf5330080 ++#define FSTV0910_P1_DEMOD_BYPASS 0xf5330040 ++#define FSTV0910_P1_CMP_SLOWMODE 0xf5330020 ++#define FSTV0910_P1_DSS_SRCH 0xf5330010 ++#define FSTV0910_P1_DIFF_MODEVIT 0xf5330004 ++#define FSTV0910_P1_SYNCVIT 0xf5330002 ++#define FSTV0910_P1_IQINV 0xf5330001 ++ ++/*P1_VTH12*/ ++#define RSTV0910_P1_VTH12 0xf534 ++#define FSTV0910_P1_VTH12 0xf53400ff ++ ++/*P1_VTH23*/ ++#define RSTV0910_P1_VTH23 0xf535 ++#define FSTV0910_P1_VTH23 0xf53500ff ++ ++/*P1_VTH34*/ ++#define RSTV0910_P1_VTH34 0xf536 ++#define FSTV0910_P1_VTH34 0xf53600ff ++ ++/*P1_VTH56*/ ++#define RSTV0910_P1_VTH56 0xf537 ++#define FSTV0910_P1_VTH56 0xf53700ff ++ ++/*P1_VTH67*/ ++#define RSTV0910_P1_VTH67 0xf538 ++#define FSTV0910_P1_VTH67 0xf53800ff ++ ++/*P1_VTH78*/ ++#define RSTV0910_P1_VTH78 0xf539 ++#define FSTV0910_P1_VTH78 0xf53900ff ++ ++/*P1_VITCURPUN*/ ++#define RSTV0910_P1_VITCURPUN 0xf53a ++#define FSTV0910_P1_CYCLESLIP_VIT 0xf53a0080 ++#define FSTV0910_P1_VIT_ROTA180 0xf53a0040 ++#define FSTV0910_P1_VIT_ROTA90 0xf53a0020 ++#define FSTV0910_P1_VIT_CURPUN 0xf53a001f ++ ++/*P1_VERROR*/ ++#define RSTV0910_P1_VERROR 0xf53b ++#define FSTV0910_P1_REGERR_VIT 0xf53b00ff ++ ++/*P1_PRVIT*/ ++#define RSTV0910_P1_PRVIT 0xf53c ++#define FSTV0910_P1_DIS_VTHLOCK 0xf53c0040 ++#define FSTV0910_P1_E7_8VIT 0xf53c0020 ++#define FSTV0910_P1_E6_7VIT 0xf53c0010 ++#define FSTV0910_P1_E5_6VIT 0xf53c0008 ++#define FSTV0910_P1_E3_4VIT 0xf53c0004 ++#define FSTV0910_P1_E2_3VIT 0xf53c0002 ++#define FSTV0910_P1_E1_2VIT 0xf53c0001 ++ ++/*P1_VAVSRVIT*/ ++#define RSTV0910_P1_VAVSRVIT 0xf53d ++#define FSTV0910_P1_AMVIT 0xf53d0080 ++#define FSTV0910_P1_FROZENVIT 0xf53d0040 ++#define FSTV0910_P1_SNVIT 0xf53d0030 ++#define FSTV0910_P1_TOVVIT 0xf53d000c ++#define FSTV0910_P1_HYPVIT 0xf53d0003 ++ ++/*P1_VSTATUSVIT*/ ++#define RSTV0910_P1_VSTATUSVIT 0xf53e ++#define FSTV0910_P1_VITERBI_ON 0xf53e0080 ++#define FSTV0910_P1_END_LOOPVIT 0xf53e0040 ++#define FSTV0910_P1_VITERBI_DEPRF 0xf53e0020 ++#define FSTV0910_P1_PRFVIT 0xf53e0010 ++#define FSTV0910_P1_LOCKEDVIT 0xf53e0008 ++#define FSTV0910_P1_VITERBI_DELOCK 0xf53e0004 ++#define FSTV0910_P1_VIT_DEMODSEL 0xf53e0002 ++#define FSTV0910_P1_VITERBI_COMPOUT 0xf53e0001 ++ ++/*P1_VTHINUSE*/ ++#define RSTV0910_P1_VTHINUSE 0xf53f ++#define FSTV0910_P1_VIT_INUSE 0xf53f00ff ++ ++/*P1_KDIV12*/ ++#define RSTV0910_P1_KDIV12 0xf540 ++#define FSTV0910_P1_KDIV12_MANUAL 0xf5400080 ++#define FSTV0910_P1_K_DIVIDER_12 0xf540007f ++ ++/*P1_KDIV23*/ ++#define RSTV0910_P1_KDIV23 0xf541 ++#define FSTV0910_P1_KDIV23_MANUAL 0xf5410080 ++#define FSTV0910_P1_K_DIVIDER_23 0xf541007f ++ ++/*P1_KDIV34*/ ++#define RSTV0910_P1_KDIV34 0xf542 ++#define FSTV0910_P1_KDIV34_MANUAL 0xf5420080 ++#define FSTV0910_P1_K_DIVIDER_34 0xf542007f ++ ++/*P1_KDIV56*/ ++#define RSTV0910_P1_KDIV56 0xf543 ++#define FSTV0910_P1_KDIV56_MANUAL 0xf5430080 ++#define FSTV0910_P1_K_DIVIDER_56 0xf543007f ++ ++/*P1_KDIV67*/ ++#define RSTV0910_P1_KDIV67 0xf544 ++#define FSTV0910_P1_KDIV67_MANUAL 0xf5440080 ++#define FSTV0910_P1_K_DIVIDER_67 0xf544007f ++ ++/*P1_KDIV78*/ ++#define RSTV0910_P1_KDIV78 0xf545 ++#define FSTV0910_P1_KDIV78_MANUAL 0xf5450080 ++#define FSTV0910_P1_K_DIVIDER_78 0xf545007f ++ ++/*P1_PDELCTRL0*/ ++#define RSTV0910_P1_PDELCTRL0 0xf54f ++#define FSTV0910_P1_ISIOBS_MODE 0xf54f0030 ++#define FSTV0910_P1_PDELDIS_BITWISE 0xf54f0004 ++ ++/*P1_PDELCTRL1*/ ++#define RSTV0910_P1_PDELCTRL1 0xf550 ++#define FSTV0910_P1_INV_MISMASK 0xf5500080 ++#define FSTV0910_P1_FORCE_ACCEPTED 0xf5500040 ++#define FSTV0910_P1_FILTER_EN 0xf5500020 ++#define FSTV0910_P1_FORCE_PKTDELINUSE 0xf5500010 ++#define FSTV0910_P1_HYSTEN 0xf5500008 ++#define FSTV0910_P1_HYSTSWRST 0xf5500004 ++#define FSTV0910_P1_EN_MIS00 0xf5500002 ++#define FSTV0910_P1_ALGOSWRST 0xf5500001 ++ ++/*P1_PDELCTRL2*/ ++#define RSTV0910_P1_PDELCTRL2 0xf551 ++#define FSTV0910_P1_FORCE_CONTINUOUS 0xf5510080 ++#define FSTV0910_P1_RESET_UPKO_COUNT 0xf5510040 ++#define FSTV0910_P1_USER_PKTDELIN_NB 0xf5510020 ++#define FSTV0910_P1_DATA_UNBBSCRAMBLED 0xf5510008 ++#define FSTV0910_P1_FORCE_LONGPKT 0xf5510004 ++#define FSTV0910_P1_FRAME_MODE 0xf5510002 ++ ++/*P1_HYSTTHRESH*/ ++#define RSTV0910_P1_HYSTTHRESH 0xf554 ++#define FSTV0910_P1_DELIN_LOCKTHRES 0xf55400f0 ++#define FSTV0910_P1_DELIN_UNLOCKTHRES 0xf554000f ++ ++/*P1_ISIENTRY*/ ++#define RSTV0910_P1_ISIENTRY 0xf55e ++#define FSTV0910_P1_ISI_ENTRY 0xf55e00ff ++ ++/*P1_ISIBITENA*/ ++#define RSTV0910_P1_ISIBITENA 0xf55f ++#define FSTV0910_P1_ISI_BIT_EN 0xf55f00ff ++ ++/*P1_MATSTR1*/ ++#define RSTV0910_P1_MATSTR1 0xf560 ++#define FSTV0910_P1_MATYPE_CURRENT1 0xf56000ff ++ ++/*P1_MATSTR0*/ ++#define RSTV0910_P1_MATSTR0 0xf561 ++#define FSTV0910_P1_MATYPE_CURRENT0 0xf56100ff ++ ++/*P1_UPLSTR1*/ ++#define RSTV0910_P1_UPLSTR1 0xf562 ++#define FSTV0910_P1_UPL_CURRENT1 0xf56200ff ++ ++/*P1_UPLSTR0*/ ++#define RSTV0910_P1_UPLSTR0 0xf563 ++#define FSTV0910_P1_UPL_CURRENT0 0xf56300ff ++ ++/*P1_DFLSTR1*/ ++#define RSTV0910_P1_DFLSTR1 0xf564 ++#define FSTV0910_P1_DFL_CURRENT1 0xf56400ff ++ ++/*P1_DFLSTR0*/ ++#define RSTV0910_P1_DFLSTR0 0xf565 ++#define FSTV0910_P1_DFL_CURRENT0 0xf56500ff ++ ++/*P1_SYNCSTR*/ ++#define RSTV0910_P1_SYNCSTR 0xf566 ++#define FSTV0910_P1_SYNC_CURRENT 0xf56600ff ++ ++/*P1_SYNCDSTR1*/ ++#define RSTV0910_P1_SYNCDSTR1 0xf567 ++#define FSTV0910_P1_SYNCD_CURRENT1 0xf56700ff ++ ++/*P1_SYNCDSTR0*/ ++#define RSTV0910_P1_SYNCDSTR0 0xf568 ++#define FSTV0910_P1_SYNCD_CURRENT0 0xf56800ff ++ ++/*P1_PDELSTATUS1*/ ++#define RSTV0910_P1_PDELSTATUS1 0xf569 ++#define FSTV0910_P1_PKTDELIN_DELOCK 0xf5690080 ++#define FSTV0910_P1_SYNCDUPDFL_BADDFL 0xf5690040 ++#define FSTV0910_P1_CONTINUOUS_STREAM 0xf5690020 ++#define FSTV0910_P1_UNACCEPTED_STREAM 0xf5690010 ++#define FSTV0910_P1_BCH_ERROR_FLAG 0xf5690008 ++#define FSTV0910_P1_BBHCRCKO 0xf5690004 ++#define FSTV0910_P1_PKTDELIN_LOCK 0xf5690002 ++#define FSTV0910_P1_FIRST_LOCK 0xf5690001 ++ ++/*P1_PDELSTATUS2*/ ++#define RSTV0910_P1_PDELSTATUS2 0xf56a ++#define FSTV0910_P1_PKTDEL_DEMODSEL 0xf56a0080 ++#define FSTV0910_P1_FRAME_MODCOD 0xf56a007c ++#define FSTV0910_P1_FRAME_TYPE 0xf56a0003 ++ ++/*P1_BBFCRCKO1*/ ++#define RSTV0910_P1_BBFCRCKO1 0xf56b ++#define FSTV0910_P1_BBHCRC_KOCNT1 0xf56b00ff ++ ++/*P1_BBFCRCKO0*/ ++#define RSTV0910_P1_BBFCRCKO0 0xf56c ++#define FSTV0910_P1_BBHCRC_KOCNT0 0xf56c00ff ++ ++/*P1_UPCRCKO1*/ ++#define RSTV0910_P1_UPCRCKO1 0xf56d ++#define FSTV0910_P1_PKTCRC_KOCNT1 0xf56d00ff ++ ++/*P1_UPCRCKO0*/ ++#define RSTV0910_P1_UPCRCKO0 0xf56e ++#define FSTV0910_P1_PKTCRC_KOCNT0 0xf56e00ff ++ ++/*P1_PDELCTRL3*/ ++#define RSTV0910_P1_PDELCTRL3 0xf56f ++#define FSTV0910_P1_PKTDEL_CONTFAIL 0xf56f0080 ++#define FSTV0910_P1_PKTDEL_ENLONGPKT 0xf56f0040 ++#define FSTV0910_P1_NOFIFO_BCHERR 0xf56f0020 ++#define FSTV0910_P1_PKTDELIN_DELACMERR 0xf56f0010 ++#define FSTV0910_P1_SATURATE_BBPKTKO 0xf56f0004 ++#define FSTV0910_P1_PKTDEL_BCHERRCONT 0xf56f0002 ++#define FSTV0910_P1_ETHERNET_DISFCS 0xf56f0001 ++ ++/*P1_TSSTATEM*/ ++#define RSTV0910_P1_TSSTATEM 0xf570 ++#define FSTV0910_P1_TSDIL_ON 0xf5700080 ++#define FSTV0910_P1_TSSKIPRS_ON 0xf5700040 ++#define FSTV0910_P1_TSRS_ON 0xf5700020 ++#define FSTV0910_P1_TSDESCRAMB_ON 0xf5700010 ++#define FSTV0910_P1_TSFRAME_MODE 0xf5700008 ++#define FSTV0910_P1_TS_DISABLE 0xf5700004 ++#define FSTV0910_P1_TSACM_MODE 0xf5700002 ++#define FSTV0910_P1_TSOUT_NOSYNC 0xf5700001 ++ ++/*P1_TSCFGH*/ ++#define RSTV0910_P1_TSCFGH 0xf572 ++#define FSTV0910_P1_TSFIFO_DVBCI 0xf5720080 ++#define FSTV0910_P1_TSFIFO_SERIAL 0xf5720040 ++#define FSTV0910_P1_TSFIFO_TEIUPDATE 0xf5720020 ++#define FSTV0910_P1_TSFIFO_DUTY50 0xf5720010 ++#define FSTV0910_P1_TSFIFO_HSGNLOUT 0xf5720008 ++#define FSTV0910_P1_TSFIFO_ERRMODE 0xf5720006 ++#define FSTV0910_P1_RST_HWARE 0xf5720001 ++ ++/*P1_TSCFGM*/ ++#define RSTV0910_P1_TSCFGM 0xf573 ++#define FSTV0910_P1_TSFIFO_MANSPEED 0xf57300c0 ++#define FSTV0910_P1_TSFIFO_PERMDATA 0xf5730020 ++#define FSTV0910_P1_TSFIFO_NONEWSGNL 0xf5730010 ++#define FSTV0910_P1_NPD_SPECDVBS2 0xf5730004 ++#define FSTV0910_P1_TSFIFO_DPUNACTIVE 0xf5730002 ++#define FSTV0910_P1_TSFIFO_INVDATA 0xf5730001 ++ ++/*P1_TSCFGL*/ ++#define RSTV0910_P1_TSCFGL 0xf574 ++#define FSTV0910_P1_TSFIFO_BCLKDEL1CK 0xf57400c0 ++#define FSTV0910_P1_BCHERROR_MODE 0xf5740030 ++#define FSTV0910_P1_TSFIFO_NSGNL2DATA 0xf5740008 ++#define FSTV0910_P1_TSFIFO_EMBINDVB 0xf5740004 ++#define FSTV0910_P1_TSFIFO_BITSPEED 0xf5740003 ++ ++/*P1_TSINSDELH*/ ++#define RSTV0910_P1_TSINSDELH 0xf576 ++#define FSTV0910_P1_TSDEL_SYNCBYTE 0xf5760080 ++#define FSTV0910_P1_TSDEL_XXHEADER 0xf5760040 ++#define FSTV0910_P1_TSDEL_BBHEADER 0xf5760020 ++#define FSTV0910_P1_TSDEL_DATAFIELD 0xf5760010 ++#define FSTV0910_P1_TSINSDEL_ISCR 0xf5760008 ++#define FSTV0910_P1_TSINSDEL_NPD 0xf5760004 ++#define FSTV0910_P1_TSINSDEL_RSPARITY 0xf5760002 ++#define FSTV0910_P1_TSINSDEL_CRC8 0xf5760001 ++ ++/*P1_TSDIVN*/ ++#define RSTV0910_P1_TSDIVN 0xf579 ++#define FSTV0910_P1_TSFIFO_SPEEDMODE 0xf57900c0 ++#define FSTV0910_P1_BYTE_OVERSAMPLING 0xf5790038 ++#define FSTV0910_P1_TSFIFO_RISEOK 0xf5790007 ++ ++/*P1_TSCFG4*/ ++#define RSTV0910_P1_TSCFG4 0xf57a ++#define FSTV0910_P1_TSFIFO_TSSPEEDMODE 0xf57a00c0 ++#define FSTV0910_P1_TSFIFO_HIERSEL 0xf57a0020 ++#define FSTV0910_P1_TSFIFO_SPECTOKEN 0xf57a0010 ++#define FSTV0910_P1_TSFIFO_MAXMODE 0xf57a0008 ++#define FSTV0910_P1_TSFIFO_FRFORCEPKT 0xf57a0004 ++#define FSTV0910_P1_EXT_FECSPYIN 0xf57a0002 ++#define FSTV0910_P1_TSFIFO_DELSPEEDUP 0xf57a0001 ++ ++/*P1_TSSPEED*/ ++#define RSTV0910_P1_TSSPEED 0xf580 ++#define FSTV0910_P1_TSFIFO_OUTSPEED 0xf58000ff ++ ++/*P1_TSSTATUS*/ ++#define RSTV0910_P1_TSSTATUS 0xf581 ++#define FSTV0910_P1_TSFIFO_LINEOK 0xf5810080 ++#define FSTV0910_P1_TSFIFO_ERROR 0xf5810040 ++#define FSTV0910_P1_TSFIFO_DATA7 0xf5810020 ++#define FSTV0910_P1_TSFIFO_NOSYNC 0xf5810010 ++#define FSTV0910_P1_ISCR_INITIALIZED 0xf5810008 ++#define FSTV0910_P1_TSREGUL_ERROR 0xf5810004 ++#define FSTV0910_P1_SOFFIFO_UNREGUL 0xf5810002 ++#define FSTV0910_P1_DIL_READY 0xf5810001 ++ ++/*P1_TSSTATUS2*/ ++#define RSTV0910_P1_TSSTATUS2 0xf582 ++#define FSTV0910_P1_TSFIFO_DEMODSEL 0xf5820080 ++#define FSTV0910_P1_TSFIFOSPEED_STORE 0xf5820040 ++#define FSTV0910_P1_DILXX_RESET 0xf5820020 ++#define FSTV0910_P1_TSSPEED_IMPOSSIBLE 0xf5820010 ++#define FSTV0910_P1_TSFIFO_LINENOK 0xf5820008 ++#define FSTV0910_P1_TSFIFO_MUXSTREAM 0xf5820004 ++#define FSTV0910_P1_SCRAMBDETECT 0xf5820002 ++#define FSTV0910_P1_ULDTV67_FALSELOCK 0xf5820001 ++ ++/*P1_TSBITRATE1*/ ++#define RSTV0910_P1_TSBITRATE1 0xf583 ++#define FSTV0910_P1_TSFIFO_BITRATE1 0xf58300ff ++ ++/*P1_TSBITRATE0*/ ++#define RSTV0910_P1_TSBITRATE0 0xf584 ++#define FSTV0910_P1_TSFIFO_BITRATE0 0xf58400ff ++ ++/*P1_ERRCTRL1*/ ++#define RSTV0910_P1_ERRCTRL1 0xf598 ++#define FSTV0910_P1_ERR_SOURCE1 0xf59800f0 ++#define FSTV0910_P1_NUM_EVENT1 0xf5980007 ++ ++/*P1_ERRCNT12*/ ++#define RSTV0910_P1_ERRCNT12 0xf599 ++#define FSTV0910_P1_ERRCNT1_OLDVALUE 0xf5990080 ++#define FSTV0910_P1_ERR_CNT12 0xf599007f ++ ++/*P1_ERRCNT11*/ ++#define RSTV0910_P1_ERRCNT11 0xf59a ++#define FSTV0910_P1_ERR_CNT11 0xf59a00ff ++ ++/*P1_ERRCNT10*/ ++#define RSTV0910_P1_ERRCNT10 0xf59b ++#define FSTV0910_P1_ERR_CNT10 0xf59b00ff ++ ++/*P1_ERRCTRL2*/ ++#define RSTV0910_P1_ERRCTRL2 0xf59c ++#define FSTV0910_P1_ERR_SOURCE2 0xf59c00f0 ++#define FSTV0910_P1_NUM_EVENT2 0xf59c0007 ++ ++/*P1_ERRCNT22*/ ++#define RSTV0910_P1_ERRCNT22 0xf59d ++#define FSTV0910_P1_ERRCNT2_OLDVALUE 0xf59d0080 ++#define FSTV0910_P1_ERR_CNT22 0xf59d007f ++ ++/*P1_ERRCNT21*/ ++#define RSTV0910_P1_ERRCNT21 0xf59e ++#define FSTV0910_P1_ERR_CNT21 0xf59e00ff ++ ++/*P1_ERRCNT20*/ ++#define RSTV0910_P1_ERRCNT20 0xf59f ++#define FSTV0910_P1_ERR_CNT20 0xf59f00ff ++ ++/*P1_FECSPY*/ ++#define RSTV0910_P1_FECSPY 0xf5a0 ++#define FSTV0910_P1_SPY_ENABLE 0xf5a00080 ++#define FSTV0910_P1_NO_SYNCBYTE 0xf5a00040 ++#define FSTV0910_P1_SERIAL_MODE 0xf5a00020 ++#define FSTV0910_P1_UNUSUAL_PACKET 0xf5a00010 ++#define FSTV0910_P1_BERMETER_DATAMODE 0xf5a0000c ++#define FSTV0910_P1_BERMETER_LMODE 0xf5a00002 ++#define FSTV0910_P1_BERMETER_RESET 0xf5a00001 ++ ++/*P1_FSPYCFG*/ ++#define RSTV0910_P1_FSPYCFG 0xf5a1 ++#define FSTV0910_P1_FECSPY_INPUT 0xf5a100c0 ++#define FSTV0910_P1_RST_ON_ERROR 0xf5a10020 ++#define FSTV0910_P1_ONE_SHOT 0xf5a10010 ++#define FSTV0910_P1_I2C_MODE 0xf5a1000c ++#define FSTV0910_P1_SPY_HYSTERESIS 0xf5a10003 ++ ++/*P1_FSPYDATA*/ ++#define RSTV0910_P1_FSPYDATA 0xf5a2 ++#define FSTV0910_P1_SPY_STUFFING 0xf5a20080 ++#define FSTV0910_P1_NOERROR_PKTJITTER 0xf5a20040 ++#define FSTV0910_P1_SPY_CNULLPKT 0xf5a20020 ++#define FSTV0910_P1_SPY_OUTDATA_MODE 0xf5a2001f ++ ++/*P1_FSPYOUT*/ ++#define RSTV0910_P1_FSPYOUT 0xf5a3 ++#define FSTV0910_P1_FSPY_DIRECT 0xf5a30080 ++#define FSTV0910_P1_SPY_OUTDATA_BUS 0xf5a30038 ++#define FSTV0910_P1_STUFF_MODE 0xf5a30007 ++ ++/*P1_FSTATUS*/ ++#define RSTV0910_P1_FSTATUS 0xf5a4 ++#define FSTV0910_P1_SPY_ENDSIM 0xf5a40080 ++#define FSTV0910_P1_VALID_SIM 0xf5a40040 ++#define FSTV0910_P1_FOUND_SIGNAL 0xf5a40020 ++#define FSTV0910_P1_DSS_SYNCBYTE 0xf5a40010 ++#define FSTV0910_P1_RESULT_STATE 0xf5a4000f ++ ++/*P1_FBERCPT4*/ ++#define RSTV0910_P1_FBERCPT4 0xf5a8 ++#define FSTV0910_P1_FBERMETER_CPT4 0xf5a800ff ++ ++/*P1_FBERCPT3*/ ++#define RSTV0910_P1_FBERCPT3 0xf5a9 ++#define FSTV0910_P1_FBERMETER_CPT3 0xf5a900ff ++ ++/*P1_FBERCPT2*/ ++#define RSTV0910_P1_FBERCPT2 0xf5aa ++#define FSTV0910_P1_FBERMETER_CPT2 0xf5aa00ff ++ ++/*P1_FBERCPT1*/ ++#define RSTV0910_P1_FBERCPT1 0xf5ab ++#define FSTV0910_P1_FBERMETER_CPT1 0xf5ab00ff ++ ++/*P1_FBERCPT0*/ ++#define RSTV0910_P1_FBERCPT0 0xf5ac ++#define FSTV0910_P1_FBERMETER_CPT0 0xf5ac00ff ++ ++/*P1_FBERERR2*/ ++#define RSTV0910_P1_FBERERR2 0xf5ad ++#define FSTV0910_P1_FBERMETER_ERR2 0xf5ad00ff ++ ++/*P1_FBERERR1*/ ++#define RSTV0910_P1_FBERERR1 0xf5ae ++#define FSTV0910_P1_FBERMETER_ERR1 0xf5ae00ff ++ ++/*P1_FBERERR0*/ ++#define RSTV0910_P1_FBERERR0 0xf5af ++#define FSTV0910_P1_FBERMETER_ERR0 0xf5af00ff ++ ++/*P1_FSPYBER*/ ++#define RSTV0910_P1_FSPYBER 0xf5b2 ++#define FSTV0910_P1_FSPYOBS_XORREAD 0xf5b20040 ++#define FSTV0910_P1_FSPYBER_OBSMODE 0xf5b20020 ++#define FSTV0910_P1_FSPYBER_SYNCBYTE 0xf5b20010 ++#define FSTV0910_P1_FSPYBER_UNSYNC 0xf5b20008 ++#define FSTV0910_P1_FSPYBER_CTIME 0xf5b20007 ++ ++/*P1_SFERROR*/ ++#define RSTV0910_P1_SFERROR 0xf5c1 ++#define FSTV0910_P1_SFEC_REGERR_VIT 0xf5c100ff ++ ++/*P1_SFECSTATUS*/ ++#define RSTV0910_P1_SFECSTATUS 0xf5c3 ++#define FSTV0910_P1_SFEC_ON 0xf5c30080 ++#define FSTV0910_P1_SFEC_OFF 0xf5c30040 ++#define FSTV0910_P1_LOCKEDSFEC 0xf5c30008 ++#define FSTV0910_P1_SFEC_DELOCK 0xf5c30004 ++#define FSTV0910_P1_SFEC_DEMODSEL 0xf5c30002 ++#define FSTV0910_P1_SFEC_OVFON 0xf5c30001 ++ ++/*P1_SFKDIV12*/ ++#define RSTV0910_P1_SFKDIV12 0xf5c4 ++#define FSTV0910_P1_SFECKDIV12_MAN 0xf5c40080 ++#define FSTV0910_P1_SFEC_K_DIVIDER_12 0xf5c4007f ++ ++/*P1_SFKDIV23*/ ++#define RSTV0910_P1_SFKDIV23 0xf5c5 ++#define FSTV0910_P1_SFECKDIV23_MAN 0xf5c50080 ++#define FSTV0910_P1_SFEC_K_DIVIDER_23 0xf5c5007f ++ ++/*P1_SFKDIV34*/ ++#define RSTV0910_P1_SFKDIV34 0xf5c6 ++#define FSTV0910_P1_SFECKDIV34_MAN 0xf5c60080 ++#define FSTV0910_P1_SFEC_K_DIVIDER_34 0xf5c6007f ++ ++/*P1_SFKDIV56*/ ++#define RSTV0910_P1_SFKDIV56 0xf5c7 ++#define FSTV0910_P1_SFECKDIV56_MAN 0xf5c70080 ++#define FSTV0910_P1_SFEC_K_DIVIDER_56 0xf5c7007f ++ ++/*P1_SFKDIV67*/ ++#define RSTV0910_P1_SFKDIV67 0xf5c8 ++#define FSTV0910_P1_SFECKDIV67_MAN 0xf5c80080 ++#define FSTV0910_P1_SFEC_K_DIVIDER_67 0xf5c8007f ++ ++/*P1_SFKDIV78*/ ++#define RSTV0910_P1_SFKDIV78 0xf5c9 ++#define FSTV0910_P1_SFECKDIV78_MAN 0xf5c90080 ++#define FSTV0910_P1_SFEC_K_DIVIDER_78 0xf5c9007f ++ ++/*P1_SFSTATUS*/ ++#define RSTV0910_P1_SFSTATUS 0xf5cc ++#define FSTV0910_P1_SFEC_LINEOK 0xf5cc0080 ++#define FSTV0910_P1_SFEC_ERROR 0xf5cc0040 ++#define FSTV0910_P1_SFEC_DATA7 0xf5cc0020 ++#define FSTV0910_P1_SFEC_PKTDNBRFAIL 0xf5cc0010 ++#define FSTV0910_P1_TSSFEC_DEMODSEL 0xf5cc0008 ++#define FSTV0910_P1_SFEC_NOSYNC 0xf5cc0004 ++#define FSTV0910_P1_SFEC_UNREGULA 0xf5cc0002 ++#define FSTV0910_P1_SFEC_READY 0xf5cc0001 ++ ++/*P1_SFDLYSET2*/ ++#define RSTV0910_P1_SFDLYSET2 0xf5d0 ++#define FSTV0910_P1_SFEC_OFFSET 0xf5d000c0 ++#define FSTV0910_P1_RST_SFEC 0xf5d00008 ++#define FSTV0910_P1_DILDLINE_ERROR 0xf5d00004 ++#define FSTV0910_P1_SFEC_DISABLE 0xf5d00002 ++#define FSTV0910_P1_SFEC_UNREGUL 0xf5d00001 ++ ++/*P1_SFERRCTRL*/ ++#define RSTV0910_P1_SFERRCTRL 0xf5d8 ++#define FSTV0910_P1_SFEC_ERR_SOURCE 0xf5d800f0 ++#define FSTV0910_P1_SFEC_NUM_EVENT 0xf5d80007 ++ ++/*P1_SFERRCNT2*/ ++#define RSTV0910_P1_SFERRCNT2 0xf5d9 ++#define FSTV0910_P1_SFERRC_OLDVALUE 0xf5d90080 ++#define FSTV0910_P1_SFEC_ERR_CNT2 0xf5d9007f ++ ++/*P1_SFERRCNT1*/ ++#define RSTV0910_P1_SFERRCNT1 0xf5da ++#define FSTV0910_P1_SFEC_ERR_CNT1 0xf5da00ff ++ ++/*P1_SFERRCNT0*/ ++#define RSTV0910_P1_SFERRCNT0 0xf5db ++#define FSTV0910_P1_SFEC_ERR_CNT0 0xf5db00ff ++ ++/*TSGENERAL*/ ++#define RSTV0910_TSGENERAL 0xf630 ++#define FSTV0910_EN_LGNERROR 0xf6300080 ++#define FSTV0910_TSFIFO_DISTS2PAR 0xf6300040 ++#define FSTV0910_MUXSTREAM_COMPMOSE 0xf6300030 ++#define FSTV0910_MUXSTREAM_OUTMODE 0xf6300008 ++#define FSTV0910_TSFIFO_PERMPARAL 0xf6300006 ++#define FSTV0910_RST_REEDSOLO 0xf6300001 ++ ++/*P1_DISIRQCFG*/ ++#define RSTV0910_P1_DISIRQCFG 0xf700 ++#define FSTV0910_P1_ENRXEND 0xf7000040 ++#define FSTV0910_P1_ENRXFIFO8B 0xf7000020 ++#define FSTV0910_P1_ENTRFINISH 0xf7000010 ++#define FSTV0910_P1_ENTIMEOUT 0xf7000008 ++#define FSTV0910_P1_ENTXEND 0xf7000004 ++#define FSTV0910_P1_ENTXFIFO64B 0xf7000002 ++#define FSTV0910_P1_ENGAPBURST 0xf7000001 ++ ++/*P1_DISIRQSTAT*/ ++#define RSTV0910_P1_DISIRQSTAT 0xf701 ++#define FSTV0910_P1_IRQRXEND 0xf7010040 ++#define FSTV0910_P1_IRQRXFIFO8B 0xf7010020 ++#define FSTV0910_P1_IRQTRFINISH 0xf7010010 ++#define FSTV0910_P1_IRQTIMEOUT 0xf7010008 ++#define FSTV0910_P1_IRQTXEND 0xf7010004 ++#define FSTV0910_P1_IRQTXFIFO64B 0xf7010002 ++#define FSTV0910_P1_IRQGAPBURST 0xf7010001 ++ ++/*P1_DISTXCFG*/ ++#define RSTV0910_P1_DISTXCFG 0xf702 ++#define FSTV0910_P1_DISTX_RESET 0xf7020080 ++#define FSTV0910_P1_TIM_OFF 0xf7020040 ++#define FSTV0910_P1_TIM_CMD 0xf7020030 ++#define FSTV0910_P1_ENVELOP 0xf7020008 ++#define FSTV0910_P1_DIS_PRECHARGE 0xf7020004 ++#define FSTV0910_P1_DISEQC_MODE 0xf7020003 ++ ++/*P1_DISTXSTATUS*/ ++#define RSTV0910_P1_DISTXSTATUS 0xf703 ++#define FSTV0910_P1_TX_FIFO_FULL 0xf7030040 ++#define FSTV0910_P1_TX_IDLE 0xf7030020 ++#define FSTV0910_P1_GAP_BURST 0xf7030010 ++#define FSTV0910_P1_TX_FIFO64B 0xf7030008 ++#define FSTV0910_P1_TX_END 0xf7030004 ++#define FSTV0910_P1_TR_TIMEOUT 0xf7030002 ++#define FSTV0910_P1_TR_FINISH 0xf7030001 ++ ++/*P1_DISTXBYTES*/ ++#define RSTV0910_P1_DISTXBYTES 0xf704 ++#define FSTV0910_P1_TXFIFO_BYTES 0xf70400ff ++ ++/*P1_DISTXFIFO*/ ++#define RSTV0910_P1_DISTXFIFO 0xf705 ++#define FSTV0910_P1_DISEQC_TX_FIFO 0xf70500ff ++ ++/*P1_DISTXF22*/ ++#define RSTV0910_P1_DISTXF22 0xf706 ++#define FSTV0910_P1_F22TX 0xf70600ff ++ ++/*P1_DISTIMEOCFG*/ ++#define RSTV0910_P1_DISTIMEOCFG 0xf708 ++#define FSTV0910_P1_RXCHOICE 0xf7080006 ++#define FSTV0910_P1_TIMEOUT_OFF 0xf7080001 ++ ++/*P1_DISTIMEOUT*/ ++#define RSTV0910_P1_DISTIMEOUT 0xf709 ++#define FSTV0910_P1_TIMEOUT_COUNT 0xf70900ff ++ ++/*P1_DISRXCFG*/ ++#define RSTV0910_P1_DISRXCFG 0xf70a ++#define FSTV0910_P1_DISRX_RESET 0xf70a0080 ++#define FSTV0910_P1_EXTENVELOP 0xf70a0040 ++#define FSTV0910_P1_PINSELECT 0xf70a0038 ++#define FSTV0910_P1_IGNORE_SHORT22K 0xf70a0004 ++#define FSTV0910_P1_SIGNED_RXIN 0xf70a0002 ++#define FSTV0910_P1_DISRX_ON 0xf70a0001 ++ ++/*P1_DISRXSTAT1*/ ++#define RSTV0910_P1_DISRXSTAT1 0xf70b ++#define FSTV0910_P1_RXEND 0xf70b0080 ++#define FSTV0910_P1_RXACTIVE 0xf70b0040 ++#define FSTV0910_P1_RXDETECT 0xf70b0020 ++#define FSTV0910_P1_CONTTONE 0xf70b0010 ++#define FSTV0910_P1_8BFIFOREADY 0xf70b0008 ++#define FSTV0910_P1_FIFOEMPTY 0xf70b0004 ++ ++/*P1_DISRXSTAT0*/ ++#define RSTV0910_P1_DISRXSTAT0 0xf70c ++#define FSTV0910_P1_RXFAIL 0xf70c0080 ++#define FSTV0910_P1_FIFOPFAIL 0xf70c0040 ++#define FSTV0910_P1_RXNONBYTE 0xf70c0020 ++#define FSTV0910_P1_FIFOOVF 0xf70c0010 ++#define FSTV0910_P1_SHORT22K 0xf70c0008 ++#define FSTV0910_P1_RXMSGLOST 0xf70c0004 ++ ++/*P1_DISRXBYTES*/ ++#define RSTV0910_P1_DISRXBYTES 0xf70d ++#define FSTV0910_P1_RXFIFO_BYTES 0xf70d001f ++ ++/*P1_DISRXPARITY1*/ ++#define RSTV0910_P1_DISRXPARITY1 0xf70e ++#define FSTV0910_P1_DISRX_PARITY1 0xf70e00ff ++ ++/*P1_DISRXPARITY0*/ ++#define RSTV0910_P1_DISRXPARITY0 0xf70f ++#define FSTV0910_P1_DISRX_PARITY0 0xf70f00ff ++ ++/*P1_DISRXFIFO*/ ++#define RSTV0910_P1_DISRXFIFO 0xf710 ++#define FSTV0910_P1_DISEQC_RX_FIFO 0xf71000ff ++ ++/*P1_DISRXDC1*/ ++#define RSTV0910_P1_DISRXDC1 0xf711 ++#define FSTV0910_P1_DC_VALUE1 0xf7110103 ++ ++/*P1_DISRXDC0*/ ++#define RSTV0910_P1_DISRXDC0 0xf712 ++#define FSTV0910_P1_DC_VALUE0 0xf71200ff ++ ++/*P1_DISRXF221*/ ++#define RSTV0910_P1_DISRXF221 0xf714 ++#define FSTV0910_P1_F22RX1 0xf714000f ++ ++/*P1_DISRXF220*/ ++#define RSTV0910_P1_DISRXF220 0xf715 ++#define FSTV0910_P1_F22RX0 0xf71500ff ++ ++/*P1_DISRXF100*/ ++#define RSTV0910_P1_DISRXF100 0xf716 ++#define FSTV0910_P1_F100RX 0xf71600ff ++ ++/*P1_DISRXSHORT22K*/ ++#define RSTV0910_P1_DISRXSHORT22K 0xf71c ++#define FSTV0910_P1_SHORT22K_LENGTH 0xf71c001f ++ ++/*P1_ACRPRESC*/ ++#define RSTV0910_P1_ACRPRESC 0xf71e ++#define FSTV0910_P1_ACR_CODFRDY 0xf71e0008 ++#define FSTV0910_P1_ACR_PRESC 0xf71e0007 ++ ++/*P1_ACRDIV*/ ++#define RSTV0910_P1_ACRDIV 0xf71f ++#define FSTV0910_P1_ACR_DIV 0xf71f00ff ++ ++/*P2_DISIRQCFG*/ ++#define RSTV0910_P2_DISIRQCFG 0xf740 ++#define FSTV0910_P2_ENRXEND 0xf7400040 ++#define FSTV0910_P2_ENRXFIFO8B 0xf7400020 ++#define FSTV0910_P2_ENTRFINISH 0xf7400010 ++#define FSTV0910_P2_ENTIMEOUT 0xf7400008 ++#define FSTV0910_P2_ENTXEND 0xf7400004 ++#define FSTV0910_P2_ENTXFIFO64B 0xf7400002 ++#define FSTV0910_P2_ENGAPBURST 0xf7400001 ++ ++/*P2_DISIRQSTAT*/ ++#define RSTV0910_P2_DISIRQSTAT 0xf741 ++#define FSTV0910_P2_IRQRXEND 0xf7410040 ++#define FSTV0910_P2_IRQRXFIFO8B 0xf7410020 ++#define FSTV0910_P2_IRQTRFINISH 0xf7410010 ++#define FSTV0910_P2_IRQTIMEOUT 0xf7410008 ++#define FSTV0910_P2_IRQTXEND 0xf7410004 ++#define FSTV0910_P2_IRQTXFIFO64B 0xf7410002 ++#define FSTV0910_P2_IRQGAPBURST 0xf7410001 ++ ++/*P2_DISTXCFG*/ ++#define RSTV0910_P2_DISTXCFG 0xf742 ++#define FSTV0910_P2_DISTX_RESET 0xf7420080 ++#define FSTV0910_P2_TIM_OFF 0xf7420040 ++#define FSTV0910_P2_TIM_CMD 0xf7420030 ++#define FSTV0910_P2_ENVELOP 0xf7420008 ++#define FSTV0910_P2_DIS_PRECHARGE 0xf7420004 ++#define FSTV0910_P2_DISEQC_MODE 0xf7420003 ++ ++/*P2_DISTXSTATUS*/ ++#define RSTV0910_P2_DISTXSTATUS 0xf743 ++#define FSTV0910_P2_TX_FIFO_FULL 0xf7430040 ++#define FSTV0910_P2_TX_IDLE 0xf7430020 ++#define FSTV0910_P2_GAP_BURST 0xf7430010 ++#define FSTV0910_P2_TX_FIFO64B 0xf7430008 ++#define FSTV0910_P2_TX_END 0xf7430004 ++#define FSTV0910_P2_TR_TIMEOUT 0xf7430002 ++#define FSTV0910_P2_TR_FINISH 0xf7430001 ++ ++/*P2_DISTXBYTES*/ ++#define RSTV0910_P2_DISTXBYTES 0xf744 ++#define FSTV0910_P2_TXFIFO_BYTES 0xf74400ff ++ ++/*P2_DISTXFIFO*/ ++#define RSTV0910_P2_DISTXFIFO 0xf745 ++#define FSTV0910_P2_DISEQC_TX_FIFO 0xf74500ff ++ ++/*P2_DISTXF22*/ ++#define RSTV0910_P2_DISTXF22 0xf746 ++#define FSTV0910_P2_F22TX 0xf74600ff ++ ++/*P2_DISTIMEOCFG*/ ++#define RSTV0910_P2_DISTIMEOCFG 0xf748 ++#define FSTV0910_P2_RXCHOICE 0xf7480006 ++#define FSTV0910_P2_TIMEOUT_OFF 0xf7480001 ++ ++/*P2_DISTIMEOUT*/ ++#define RSTV0910_P2_DISTIMEOUT 0xf749 ++#define FSTV0910_P2_TIMEOUT_COUNT 0xf74900ff ++ ++/*P2_DISRXCFG*/ ++#define RSTV0910_P2_DISRXCFG 0xf74a ++#define FSTV0910_P2_DISRX_RESET 0xf74a0080 ++#define FSTV0910_P2_EXTENVELOP 0xf74a0040 ++#define FSTV0910_P2_PINSELECT 0xf74a0038 ++#define FSTV0910_P2_IGNORE_SHORT22K 0xf74a0004 ++#define FSTV0910_P2_SIGNED_RXIN 0xf74a0002 ++#define FSTV0910_P2_DISRX_ON 0xf74a0001 ++ ++/*P2_DISRXSTAT1*/ ++#define RSTV0910_P2_DISRXSTAT1 0xf74b ++#define FSTV0910_P2_RXEND 0xf74b0080 ++#define FSTV0910_P2_RXACTIVE 0xf74b0040 ++#define FSTV0910_P2_RXDETECT 0xf74b0020 ++#define FSTV0910_P2_CONTTONE 0xf74b0010 ++#define FSTV0910_P2_8BFIFOREADY 0xf74b0008 ++#define FSTV0910_P2_FIFOEMPTY 0xf74b0004 ++ ++/*P2_DISRXSTAT0*/ ++#define RSTV0910_P2_DISRXSTAT0 0xf74c ++#define FSTV0910_P2_RXFAIL 0xf74c0080 ++#define FSTV0910_P2_FIFOPFAIL 0xf74c0040 ++#define FSTV0910_P2_RXNONBYTE 0xf74c0020 ++#define FSTV0910_P2_FIFOOVF 0xf74c0010 ++#define FSTV0910_P2_SHORT22K 0xf74c0008 ++#define FSTV0910_P2_RXMSGLOST 0xf74c0004 ++ ++/*P2_DISRXBYTES*/ ++#define RSTV0910_P2_DISRXBYTES 0xf74d ++#define FSTV0910_P2_RXFIFO_BYTES 0xf74d001f ++ ++/*P2_DISRXPARITY1*/ ++#define RSTV0910_P2_DISRXPARITY1 0xf74e ++#define FSTV0910_P2_DISRX_PARITY1 0xf74e00ff ++ ++/*P2_DISRXPARITY0*/ ++#define RSTV0910_P2_DISRXPARITY0 0xf74f ++#define FSTV0910_P2_DISRX_PARITY0 0xf74f00ff ++ ++/*P2_DISRXFIFO*/ ++#define RSTV0910_P2_DISRXFIFO 0xf750 ++#define FSTV0910_P2_DISEQC_RX_FIFO 0xf75000ff ++ ++/*P2_DISRXDC1*/ ++#define RSTV0910_P2_DISRXDC1 0xf751 ++#define FSTV0910_P2_DC_VALUE1 0xf7510103 ++ ++/*P2_DISRXDC0*/ ++#define RSTV0910_P2_DISRXDC0 0xf752 ++#define FSTV0910_P2_DC_VALUE0 0xf75200ff ++ ++/*P2_DISRXF221*/ ++#define RSTV0910_P2_DISRXF221 0xf754 ++#define FSTV0910_P2_F22RX1 0xf754000f ++ ++/*P2_DISRXF220*/ ++#define RSTV0910_P2_DISRXF220 0xf755 ++#define FSTV0910_P2_F22RX0 0xf75500ff ++ ++/*P2_DISRXF100*/ ++#define RSTV0910_P2_DISRXF100 0xf756 ++#define FSTV0910_P2_F100RX 0xf75600ff ++ ++/*P2_DISRXSHORT22K*/ ++#define RSTV0910_P2_DISRXSHORT22K 0xf75c ++#define FSTV0910_P2_SHORT22K_LENGTH 0xf75c001f ++ ++/*P2_ACRPRESC*/ ++#define RSTV0910_P2_ACRPRESC 0xf75e ++#define FSTV0910_P2_ACR_CODFRDY 0xf75e0008 ++#define FSTV0910_P2_ACR_PRESC 0xf75e0007 ++ ++/*P2_ACRDIV*/ ++#define RSTV0910_P2_ACRDIV 0xf75f ++#define FSTV0910_P2_ACR_DIV 0xf75f00ff ++ ++/*P1_NBITER_NF4*/ ++#define RSTV0910_P1_NBITER_NF4 0xfa03 ++#define FSTV0910_P1_NBITER_NF_QPSK_1_2 0xfa0300ff ++ ++/*P1_NBITER_NF5*/ ++#define RSTV0910_P1_NBITER_NF5 0xfa04 ++#define FSTV0910_P1_NBITER_NF_QPSK_3_5 0xfa0400ff ++ ++/*P1_NBITER_NF6*/ ++#define RSTV0910_P1_NBITER_NF6 0xfa05 ++#define FSTV0910_P1_NBITER_NF_QPSK_2_3 0xfa0500ff ++ ++/*P1_NBITER_NF7*/ ++#define RSTV0910_P1_NBITER_NF7 0xfa06 ++#define FSTV0910_P1_NBITER_NF_QPSK_3_4 0xfa0600ff ++ ++/*P1_NBITER_NF8*/ ++#define RSTV0910_P1_NBITER_NF8 0xfa07 ++#define FSTV0910_P1_NBITER_NF_QPSK_4_5 0xfa0700ff ++ ++/*P1_NBITER_NF9*/ ++#define RSTV0910_P1_NBITER_NF9 0xfa08 ++#define FSTV0910_P1_NBITER_NF_QPSK_5_6 0xfa0800ff ++ ++/*P1_NBITER_NF10*/ ++#define RSTV0910_P1_NBITER_NF10 0xfa09 ++#define FSTV0910_P1_NBITER_NF_QPSK_8_9 0xfa0900ff ++ ++/*P1_NBITER_NF11*/ ++#define RSTV0910_P1_NBITER_NF11 0xfa0a ++#define FSTV0910_P1_NBITER_NF_QPSK_9_10 0xfa0a00ff ++ ++/*P1_NBITER_NF12*/ ++#define RSTV0910_P1_NBITER_NF12 0xfa0b ++#define FSTV0910_P1_NBITER_NF_8PSK_3_5 0xfa0b00ff ++ ++/*P1_NBITER_NF13*/ ++#define RSTV0910_P1_NBITER_NF13 0xfa0c ++#define FSTV0910_P1_NBITER_NF_8PSK_2_3 0xfa0c00ff ++ ++/*P1_NBITER_NF14*/ ++#define RSTV0910_P1_NBITER_NF14 0xfa0d ++#define FSTV0910_P1_NBITER_NF_8PSK_3_4 0xfa0d00ff ++ ++/*P1_NBITER_NF15*/ ++#define RSTV0910_P1_NBITER_NF15 0xfa0e ++#define FSTV0910_P1_NBITER_NF_8PSK_5_6 0xfa0e00ff ++ ++/*P1_NBITER_NF16*/ ++#define RSTV0910_P1_NBITER_NF16 0xfa0f ++#define FSTV0910_P1_NBITER_NF_8PSK_8_9 0xfa0f00ff ++ ++/*P1_NBITER_NF17*/ ++#define RSTV0910_P1_NBITER_NF17 0xfa10 ++#define FSTV0910_P1_NBITER_NF_8PSK_9_10 0xfa1000ff ++ ++/*GAINLLR_NF4*/ ++#define RSTV0910_GAINLLR_NF4 0xfa43 ++#define FSTV0910_GAINLLR_NF_QPSK_1_2 0xfa43007f ++ ++/*GAINLLR_NF5*/ ++#define RSTV0910_GAINLLR_NF5 0xfa44 ++#define FSTV0910_GAINLLR_NF_QPSK_3_5 0xfa44007f ++ ++/*GAINLLR_NF6*/ ++#define RSTV0910_GAINLLR_NF6 0xfa45 ++#define FSTV0910_GAINLLR_NF_QPSK_2_3 0xfa45007f ++ ++/*GAINLLR_NF7*/ ++#define RSTV0910_GAINLLR_NF7 0xfa46 ++#define FSTV0910_GAINLLR_NF_QPSK_3_4 0xfa46007f ++ ++/*GAINLLR_NF8*/ ++#define RSTV0910_GAINLLR_NF8 0xfa47 ++#define FSTV0910_GAINLLR_NF_QPSK_4_5 0xfa47007f ++ ++/*GAINLLR_NF9*/ ++#define RSTV0910_GAINLLR_NF9 0xfa48 ++#define FSTV0910_GAINLLR_NF_QPSK_5_6 0xfa48007f ++ ++/*GAINLLR_NF10*/ ++#define RSTV0910_GAINLLR_NF10 0xfa49 ++#define FSTV0910_GAINLLR_NF_QPSK_8_9 0xfa49007f ++ ++/*GAINLLR_NF11*/ ++#define RSTV0910_GAINLLR_NF11 0xfa4a ++#define FSTV0910_GAINLLR_NF_QPSK_9_10 0xfa4a007f ++ ++/*GAINLLR_NF12*/ ++#define RSTV0910_GAINLLR_NF12 0xfa4b ++#define FSTV0910_GAINLLR_NF_8PSK_3_5 0xfa4b007f ++ ++/*GAINLLR_NF13*/ ++#define RSTV0910_GAINLLR_NF13 0xfa4c ++#define FSTV0910_GAINLLR_NF_8PSK_2_3 0xfa4c007f ++ ++/*GAINLLR_NF14*/ ++#define RSTV0910_GAINLLR_NF14 0xfa4d ++#define FSTV0910_GAINLLR_NF_8PSK_3_4 0xfa4d007f ++ ++/*GAINLLR_NF15*/ ++#define RSTV0910_GAINLLR_NF15 0xfa4e ++#define FSTV0910_GAINLLR_NF_8PSK_5_6 0xfa4e007f ++ ++/*GAINLLR_NF16*/ ++#define RSTV0910_GAINLLR_NF16 0xfa4f ++#define FSTV0910_GAINLLR_NF_8PSK_8_9 0xfa4f007f ++ ++/*GAINLLR_NF17*/ ++#define RSTV0910_GAINLLR_NF17 0xfa50 ++#define FSTV0910_GAINLLR_NF_8PSK_9_10 0xfa50007f ++ ++/*CFGEXT*/ ++#define RSTV0910_CFGEXT 0xfa80 ++#define FSTV0910_BYPFIFOBCH 0xfa800080 ++#define FSTV0910_BYPBCH 0xfa800040 ++#define FSTV0910_BYPLDPC 0xfa800020 ++#define FSTV0910_BYPFIFOBCHF 0xfa800010 ++#define FSTV0910_INVLLRSIGN 0xfa800008 ++#define FSTV0910_SHORTMULT 0xfa800004 ++#define FSTV0910_ENSTOPDEC 0xfa800002 ++ ++/*GENCFG*/ ++#define RSTV0910_GENCFG 0xfa86 ++#define FSTV0910_LEG_ITER 0xfa860040 ++#define FSTV0910_NOSHFRD1 0xfa860020 ++#define FSTV0910_BROADCAST 0xfa860010 ++#define FSTV0910_NOSHFRD2 0xfa860008 ++#define FSTV0910_BCHERRFLAG 0xfa860004 ++#define FSTV0910_CROSSINPUT 0xfa860002 ++#define FSTV0910_DDEMOD 0xfa860001 ++ ++/*LDPCERR1*/ ++#define RSTV0910_LDPCERR1 0xfa96 ++#define FSTV0910_LDPC_ERRORS1 0xfa9600ff ++ ++/*LDPCERR0*/ ++#define RSTV0910_LDPCERR0 0xfa97 ++#define FSTV0910_LDPC_ERRORS0 0xfa9700ff ++ ++/*BCHERR*/ ++#define RSTV0910_BCHERR 0xfa98 ++#define FSTV0910_ERRORFLAG 0xfa980010 ++#define FSTV0910_BCH_ERRORS_COUNTER 0xfa98000f ++ ++/*P1_MAXEXTRAITER*/ ++#define RSTV0910_P1_MAXEXTRAITER 0xfab1 ++#define FSTV0910_P1_MAX_EXTRA_ITER 0xfab100ff ++ ++/*P2_MAXEXTRAITER*/ ++#define RSTV0910_P2_MAXEXTRAITER 0xfab6 ++#define FSTV0910_P2_MAX_EXTRA_ITER 0xfab600ff ++ ++/*P1_STATUSITER*/ ++#define RSTV0910_P1_STATUSITER 0xfabc ++#define FSTV0910_P1_STATUS_ITER 0xfabc00ff ++ ++/*P1_STATUSMAXITER*/ ++#define RSTV0910_P1_STATUSMAXITER 0xfabd ++#define FSTV0910_P1_STATUS_MAX_ITER 0xfabd00ff ++ ++/*P2_STATUSITER*/ ++#define RSTV0910_P2_STATUSITER 0xfabe ++#define FSTV0910_P2_STATUS_ITER 0xfabe00ff ++ ++/*P2_STATUSMAXITER*/ ++#define RSTV0910_P2_STATUSMAXITER 0xfabf ++#define FSTV0910_P2_STATUS_MAX_ITER 0xfabf00ff ++ ++/*P2_NBITER_NF4*/ ++#define RSTV0910_P2_NBITER_NF4 0xfac3 ++#define FSTV0910_P2_NBITER_NF_QPSK_1_2 0xfac300ff ++ ++/*P2_NBITER_NF5*/ ++#define RSTV0910_P2_NBITER_NF5 0xfac4 ++#define FSTV0910_P2_NBITER_NF_QPSK_3_5 0xfac400ff ++ ++/*P2_NBITER_NF6*/ ++#define RSTV0910_P2_NBITER_NF6 0xfac5 ++#define FSTV0910_P2_NBITER_NF_QPSK_2_3 0xfac500ff ++ ++/*P2_NBITER_NF7*/ ++#define RSTV0910_P2_NBITER_NF7 0xfac6 ++#define FSTV0910_P2_NBITER_NF_QPSK_3_4 0xfac600ff ++ ++/*P2_NBITER_NF8*/ ++#define RSTV0910_P2_NBITER_NF8 0xfac7 ++#define FSTV0910_P2_NBITER_NF_QPSK_4_5 0xfac700ff ++ ++/*P2_NBITER_NF9*/ ++#define RSTV0910_P2_NBITER_NF9 0xfac8 ++#define FSTV0910_P2_NBITER_NF_QPSK_5_6 0xfac800ff ++ ++/*P2_NBITER_NF10*/ ++#define RSTV0910_P2_NBITER_NF10 0xfac9 ++#define FSTV0910_P2_NBITER_NF_QPSK_8_9 0xfac900ff ++ ++/*P2_NBITER_NF11*/ ++#define RSTV0910_P2_NBITER_NF11 0xfaca ++#define FSTV0910_P2_NBITER_NF_QPSK_9_10 0xfaca00ff ++ ++/*P2_NBITER_NF12*/ ++#define RSTV0910_P2_NBITER_NF12 0xfacb ++#define FSTV0910_P2_NBITER_NF_8PSK_3_5 0xfacb00ff ++ ++/*P2_NBITER_NF13*/ ++#define RSTV0910_P2_NBITER_NF13 0xfacc ++#define FSTV0910_P2_NBITER_NF_8PSK_2_3 0xfacc00ff ++ ++/*P2_NBITER_NF14*/ ++#define RSTV0910_P2_NBITER_NF14 0xfacd ++#define FSTV0910_P2_NBITER_NF_8PSK_3_4 0xfacd00ff ++ ++/*P2_NBITER_NF15*/ ++#define RSTV0910_P2_NBITER_NF15 0xface ++#define FSTV0910_P2_NBITER_NF_8PSK_5_6 0xface00ff ++ ++/*P2_NBITER_NF16*/ ++#define RSTV0910_P2_NBITER_NF16 0xfacf ++#define FSTV0910_P2_NBITER_NF_8PSK_8_9 0xfacf00ff ++ ++/*P2_NBITER_NF17*/ ++#define RSTV0910_P2_NBITER_NF17 0xfad0 ++#define FSTV0910_P2_NBITER_NF_8PSK_9_10 0xfad000ff ++ ++/*TSTRES0*/ ++#define RSTV0910_TSTRES0 0xff11 ++#define FSTV0910_FRESFEC 0xff110080 ++#define FSTV0910_FRESTS 0xff110040 ++#define FSTV0910_FRESVIT1 0xff110020 ++#define FSTV0910_FRESVIT2 0xff110010 ++#define FSTV0910_FRESSYM1 0xff110008 ++#define FSTV0910_FRESSYM2 0xff110004 ++#define FSTV0910_FRESMAS 0xff110002 ++#define FSTV0910_FRESINT 0xff110001 ++ ++/*P2_TCTL4*/ ++#define RSTV0910_P2_TCTL4 0xff28 ++#define FSTV0910_P2_CFR2TOCFR1_DVBS1 0xff2800c0 ++#define FSTV0910_P2_TSTINV_PHERR 0xff280020 ++#define FSTV0910_P2_EN_PLHCALC 0xff280010 ++#define FSTV0910_P2_TETA3L_RSTTETA3D 0xff280008 ++#define FSTV0910_P2_DIS_FORCEBETA2 0xff280004 ++#define FSTV0910_P2_CAR3_NOTRACEBACK 0xff280002 ++#define FSTV0910_P2_CAR3_NOFORWARD 0xff280001 ++ ++/*P1_TCTL4*/ ++#define RSTV0910_P1_TCTL4 0xff48 ++#define FSTV0910_P1_CFR2TOCFR1_DVBS1 0xff4800c0 ++#define FSTV0910_P1_TSTINV_PHERR 0xff480020 ++#define FSTV0910_P1_EN_PLHCALC 0xff480010 ++#define FSTV0910_P1_TETA3L_RSTTETA3D 0xff480008 ++#define FSTV0910_P1_DIS_FORCEBETA2 0xff480004 ++#define FSTV0910_P1_CAR3_NOTRACEBACK 0xff480002 ++#define FSTV0910_P1_CAR3_NOFORWARD 0xff480001 ++ ++#define STV0910_NBREGS 735 ++#define STV0910_NBFIELDS 1776 diff --git a/drivers/media/dvb-frontends/stv6111.c b/drivers/media/dvb-frontends/stv6111.c new file mode 100644 index 0000000..fbd6365 @@ -22380,7 +22380,7 @@ index 0000000..687fab4a + struct i2c_adapter *i2c, u8 adr); +#endif diff --git a/drivers/media/dvb-frontends/tda18271c2dd.c b/drivers/media/dvb-frontends/tda18271c2dd.c -index 2c54586..ad7c72e 100644 +index de0a1c1..ad7c72e 100644 --- a/drivers/media/dvb-frontends/tda18271c2dd.c +++ b/drivers/media/dvb-frontends/tda18271c2dd.c @@ -32,10 +32,6 @@ @@ -22415,6 +22415,15 @@ index 2c54586..ad7c72e 100644 } static int WriteReg(struct tda_state *state, u8 SubAddr, u8 Reg) +@@ -1030,7 +1019,7 @@ static int ChannelConfiguration(struct tda_state *state, + state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital; + + if ((Standard == HF_FM_Radio) && state->m_bFMInput) +- state->m_Regs[EP4] |= 0x80; ++ state->m_Regs[EP4] |= 80; + + state->m_Regs[MPD] &= ~0x80; + if (Standard > HF_AnalogMax) diff --git a/drivers/media/dvb-frontends/tda18271c2dd.h b/drivers/media/dvb-frontends/tda18271c2dd.h index dd84f7b..1389c74 100644 --- a/drivers/media/dvb-frontends/tda18271c2dd.h @@ -22476,7 +22485,7 @@ index 7446c8b..2610161 100644 ccflags-y += -Idrivers/media/dvb-core/ diff --git a/drivers/media/pci/ddbridge/ddbridge-core.c b/drivers/media/pci/ddbridge/ddbridge-core.c -index fb52bda..c85796a 100644 +index da8f848..9cd98a4 100644 --- a/drivers/media/pci/ddbridge/ddbridge-core.c +++ b/drivers/media/pci/ddbridge/ddbridge-core.c @@ -1,7 +1,8 @@ @@ -24230,9 +24239,7 @@ index fb52bda..c85796a 100644 + } + dvb->attached = 0x00; +} - -- case 2: -- dvb_dmx_release(&input->demux); ++ +static int dvb_register_adapters(struct ddb *dev) +{ + int i, ret = 0; @@ -24255,9 +24262,7 @@ index fb52bda..c85796a 100644 + } + return 0; + } - -- case 1: -- dvb_unregister_adapter(adap); ++ + for (i = 0; i < dev->info->port_num; i++) { + port = &dev->port[i]; + switch (port->class) { @@ -24284,7 +24289,9 @@ index fb52bda..c85796a 100644 + return ret; + port->dvb[1].adap_registered = 1; + break; -+ + +- case 2: +- dvb_dmx_release(&input->demux); + case DDB_PORT_CI: + case DDB_PORT_LOOP: + adap = port->dvb[0].adap; @@ -24312,7 +24319,9 @@ index fb52bda..c85796a 100644 + } + return ret; +} -+ + +- case 1: +- dvb_unregister_adapter(adap); +static void dvb_unregister_adapters(struct ddb *dev) +{ + int i; @@ -24634,13 +24643,13 @@ index fb52bda..c85796a 100644 + struct i2c_adapter *i2c = &port->i2c->adap; + u8 val; + int res; - -- poll_wait(file, &read_queue, wait); -- poll_wait(file, &write_queue, wait); ++ + res = i2c_read_reg(i2c, 0x10, 0x04, &val); + if (res < 0) + return res; -+ + +- poll_wait(file, &read_queue, wait); +- poll_wait(file, &write_queue, wait); + if (val != 0x02) { + pr_info("Port %d: invalid XO2\n", port->nr); + return -1; @@ -25853,10 +25862,7 @@ index fb52bda..c85796a 100644 + DVB_DEVICE_NSD); + return ret; +} - --/******************************************************************************/ --/******************************************************************************/ --/******************************************************************************/ ++ +static void ddb_nsd_detach(struct ddb *dev) +{ + if (dev->nsd_dev->users > 2) { @@ -25867,7 +25873,10 @@ index fb52bda..c85796a 100644 +} + +#endif -+ + +-/******************************************************************************/ +-/******************************************************************************/ +-/******************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ +/****************************************************************************/ @@ -26169,7 +26178,7 @@ index fb52bda..c85796a 100644 default: return -ENOTTY; } -@@ -1477,251 +3073,508 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +@@ -1477,284 +3073,494 @@ static long ddb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) static const struct file_operations ddb_fops = { .unlocked_ioctl = ddb_ioctl, .open = ddb_open, @@ -26357,16 +26366,16 @@ index fb52bda..c85796a 100644 + struct i2c_adapter *adap; + u8 tmp[4]; + s16 i, q; -+ + +- ddb_unmap(dev); +- pci_set_drvdata(pdev, 0); +- pci_disable_device(pdev); + adap = &dev->i2c[1].adap; + if (i2c_read_regs16(adap, 0x1f, 0xf480, tmp, 4) < 0) + return sprintf(buf, "read_error\n"); + i = (s16) (((u16) tmp[1]) << 14) | (((u16) tmp[0]) << 6); + q = (s16) (((u16) tmp[3]) << 14) | (((u16) tmp[2]) << 6); - -- ddb_unmap(dev); -- pci_set_drvdata(pdev, 0); -- pci_disable_device(pdev); ++ + return sprintf(buf, "%d %d\n", i, q); } +#endif @@ -26462,19 +26471,19 @@ index fb52bda..c85796a 100644 + ddb_set_led(dev, num, val); + return count; +} - --#ifdef CONFIG_PCI_MSI -- if (pci_msi_enabled()) -- stat = pci_enable_msi(dev->pdev); -- if (stat) { -- printk(KERN_INFO ": MSI not available.\n"); ++ +static ssize_t snr_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + char snr[32]; + int num = attr->attr.name[3] - 0x30; -+ + +-#ifdef CONFIG_PCI_MSI +- if (pci_msi_enabled()) +- stat = pci_enable_msi(dev->pdev); +- if (stat) { +- printk(KERN_INFO ": MSI not available.\n"); + if (dev->port[num].type >= DDB_TUNER_XO2) { + if (i2c_read_regs(&dev->i2c[num].adap, 0x10, 0x10, snr, 16) < 0) + return sprintf(buf, "NO SNR\n"); @@ -26581,16 +26590,28 @@ index fb52bda..c85796a 100644 + return res; + pr_info("redirect: %02x, %02x\n", i, p); + return count; -+} -+ + } + +-/******************************************************************************/ +-/******************************************************************************/ +-/******************************************************************************/ +static ssize_t gap_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); + int num = attr->attr.name[3] - 0x30; -+ + +-static struct ddb_info ddb_none = { +- .type = DDB_NONE, +- .name = "Digital Devices PCIe bridge", +-}; + return sprintf(buf, "%d\n", dev->port[num].gap); -+ + +-static struct ddb_info ddb_octopus = { +- .type = DDB_OCTOPUS, +- .name = "Digital Devices Octopus DVB adapter", +- .port_num = 4, +-}; +} +static ssize_t gap_store(struct device *device, struct device_attribute *attr, + const char *buf, size_t count) @@ -26606,19 +26627,35 @@ index fb52bda..c85796a 100644 + dev->port[num].gap = val; + return count; +} -+ + +-static struct ddb_info ddb_octopus_le = { +- .type = DDB_OCTOPUS, +- .name = "Digital Devices Octopus LE DVB adapter", +- .port_num = 2, +-}; +static ssize_t version_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct ddb *dev = dev_get_drvdata(device); -+ + +-static struct ddb_info ddb_octopus_mini = { +- .type = DDB_OCTOPUS, +- .name = "Digital Devices Octopus Mini", +- .port_num = 4, +-}; + return sprintf(buf, "%08x %08x\n", + ddbreadl(dev, 0), ddbreadl(dev, 4)); - } ++} --/******************************************************************************/ --/******************************************************************************/ --/******************************************************************************/ +-static struct ddb_info ddb_v6 = { +- .type = DDB_OCTOPUS, +- .name = "Digital Devices Cine S2 V6 DVB adapter", +- .port_num = 3, +-}; +-static struct ddb_info ddb_v6_5 = { +- .type = DDB_OCTOPUS, +- .name = "Digital Devices Cine S2 V6.5 DVB adapter", +- .port_num = 4, +static ssize_t hwid_show(struct device *device, + struct device_attribute *attr, char *buf) +{ @@ -26634,41 +26671,33 @@ index fb52bda..c85796a 100644 + + return sprintf(buf, "0x%08X\n", dev->ids.regmapid); +} - --static struct ddb_info ddb_none = { -- .type = DDB_NONE, -- .name = "Digital Devices PCIe bridge", ++ +static struct device_attribute ddb_attrs[] = { + __ATTR_RO(version), + __ATTR_RO(ports), + __ATTR_RO(ts_irq), + __ATTR_RO(i2c_irq), -+ __ATTR(gap0, 0666, gap_show, gap_store), -+ __ATTR(gap1, 0666, gap_show, gap_store), -+ __ATTR(gap2, 0666, gap_show, gap_store), -+ __ATTR(gap3, 0666, gap_show, gap_store), + __ATTR_RO(hwid), + __ATTR_RO(regmap), +#if 0 + __ATTR_RO(qam), +#endif -+ __ATTR(redirect, 0666, redirect_show, redirect_store), + __ATTR_MRO(snr, bsnr_show), + __ATTR_NULL, }; --static struct ddb_info ddb_octopus = { +-static struct ddb_info ddb_dvbct = { - .type = DDB_OCTOPUS, -- .name = "Digital Devices Octopus DVB adapter", -- .port_num = 4, +- .name = "Digital Devices DVBCT V6.1 DVB adapter", +- .port_num = 3, +static struct device_attribute ddb_attrs_temp[] = { + __ATTR_RO(temp), }; --static struct ddb_info ddb_octopus_le = { +-static struct ddb_info ddb_satixS2v3 = { - .type = DDB_OCTOPUS, -- .name = "Digital Devices Octopus LE DVB adapter", -- .port_num = 2, +- .name = "Mystique SaTiX-S2 V3 DVB adapter", +- .port_num = 3, +static struct device_attribute ddb_attrs_mod[] = { + __ATTR_MRO(mod0, mod_show), + __ATTR_MRO(mod1, mod_show), @@ -26682,12 +26711,11 @@ index fb52bda..c85796a 100644 + __ATTR_MRO(mod9, mod_show), }; --static struct ddb_info ddb_v6 = { +-static struct ddb_info ddb_octopusv3 = { - .type = DDB_OCTOPUS, -- .name = "Digital Devices Cine S2 V6 DVB adapter", -- .port_num = 3, +- .name = "Digital Devices Octopus V3 DVB adapter", +- .port_num = 4, +static struct device_attribute ddb_attrs_fan[] = { -+ __ATTR(fan, 0666, fan_show, fan_store), }; -#define DDVID 0xdd01 /* Digital Devices Vendor ID */ @@ -26701,24 +26729,20 @@ index fb52bda..c85796a 100644 - DDB_ID(DDVID, 0x0002, DDVID, 0x0001, ddb_octopus), - DDB_ID(DDVID, 0x0003, DDVID, 0x0001, ddb_octopus), - DDB_ID(DDVID, 0x0003, DDVID, 0x0002, ddb_octopus_le), -- DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus), +- DDB_ID(DDVID, 0x0003, DDVID, 0x0010, ddb_octopus_mini), - DDB_ID(DDVID, 0x0003, DDVID, 0x0020, ddb_v6), +- DDB_ID(DDVID, 0x0003, DDVID, 0x0021, ddb_v6_5), +- DDB_ID(DDVID, 0x0003, DDVID, 0x0030, ddb_dvbct), +- DDB_ID(DDVID, 0x0003, DDVID, 0xdb03, ddb_satixS2v3), +- DDB_ID(DDVID, 0x0005, DDVID, 0x0004, ddb_octopusv3), - /* in case sub-ids got deleted in flash */ - DDB_ID(DDVID, 0x0003, PCI_ANY_ID, PCI_ANY_ID, ddb_none), - {0} +static struct device_attribute ddb_attrs_snr[] = { -+ __ATTR(snr0, 0666, snr_show, snr_store), -+ __ATTR(snr1, 0666, snr_show, snr_store), -+ __ATTR(snr2, 0666, snr_show, snr_store), -+ __ATTR(snr3, 0666, snr_show, snr_store), }; -MODULE_DEVICE_TABLE(pci, ddb_id_tbl); +static struct device_attribute ddb_attrs_led[] = { -+ __ATTR(led0, 0666, led_show, led_store), -+ __ATTR(led1, 0666, led_show, led_store), -+ __ATTR(led2, 0666, led_show, led_store), -+ __ATTR(led3, 0666, led_show, led_store), +}; -static struct pci_driver ddb_pci_driver = { @@ -29259,7 +29283,7 @@ index a3ccb31..0c064ae 100644 + diff --git a/drivers/media/pci/ddbridge/ddbridge.c b/drivers/media/pci/ddbridge/ddbridge.c new file mode 100644 -index 0000000..d48c860 +index 0000000..a2c3c43 --- /dev/null +++ b/drivers/media/pci/ddbridge/ddbridge.c @@ -0,0 +1,449 @@ @@ -31754,7 +31778,7 @@ index 9e82d21..c9b1bd4 100644 .link_reset = ngene_link_reset, .slot_reset = ngene_slot_reset, diff --git a/drivers/media/pci/ngene/ngene-core.c b/drivers/media/pci/ngene/ngene-core.c -index 970e833..84510db 100644 +index 4930b55..84510db 100644 --- a/drivers/media/pci/ngene/ngene-core.c +++ b/drivers/media/pci/ngene/ngene-core.c @@ -86,6 +86,14 @@ static void event_tasklet(unsigned long data) @@ -32095,7 +32119,40 @@ index 970e833..84510db 100644 /****************************************************************************/ /* nGene hardware init and release functions ********************************/ -@@ -1065,6 +1302,85 @@ static u32 Buffer2Sizes[MAX_STREAM] = { +@@ -910,6 +1147,7 @@ static int AllocateRingBuffers(struct pci_dev *pci_dev, + { + dma_addr_t tmp; + u32 i, j; ++ int status = 0; + u32 SCListMemSize = pRingBuffer->NumBuffers + * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) : + NUM_SCATTER_GATHER_ENTRIES) +@@ -1009,12 +1247,14 @@ static int AllocateRingBuffers(struct pci_dev *pci_dev, + + } + +- return 0; ++ return status; + } + + static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer, + struct SRingBufferDescriptor *pRingBuffer) + { ++ int status = 0; ++ + /* Copy pointer to scatter gather list in TSRingbuffer + structure for buffer 2 + Load number of buffer +@@ -1035,7 +1275,7 @@ static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer, + pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1; + Cur = Cur->Next; + } +- return 0; ++ return status; + } + + static u32 RingBufferSizes[MAX_STREAM] = { +@@ -1062,6 +1302,85 @@ static u32 Buffer2Sizes[MAX_STREAM] = { 0 }; @@ -32181,7 +32238,23 @@ index 970e833..84510db 100644 static int AllocCommonBuffers(struct ngene *dev) { -@@ -1318,6 +1634,10 @@ static int ngene_buffer_config(struct ngene *dev) +@@ -1075,11 +1394,12 @@ static int AllocCommonBuffers(struct ngene *dev) + dev->ngenetohost = dev->FWInterfaceBuffer + 256; + dev->EventBuffer = dev->FWInterfaceBuffer + 512; + +- dev->OverflowBuffer = pci_zalloc_consistent(dev->pci_dev, +- OVERFLOW_BUFFER_SIZE, +- &dev->PAOverflowBuffer); ++ dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev, ++ OVERFLOW_BUFFER_SIZE, ++ &dev->PAOverflowBuffer); + if (!dev->OverflowBuffer) + return -ENOMEM; ++ memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE); + + for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) { + int type = dev->card_info->io_type[i]; +@@ -1314,6 +1634,10 @@ static int ngene_buffer_config(struct ngene *dev) u8 tsin12_config[6] = { 0x60, 0x60, 0x00, 0x00, 0x00, 0x00 }; u8 tsin1234_config[6] = { 0x30, 0x30, 0x00, 0x30, 0x30, 0x00 }; u8 tsio1235_config[6] = { 0x30, 0x30, 0x00, 0x28, 0x00, 0x38 }; @@ -32192,7 +32265,7 @@ index 970e833..84510db 100644 u8 *bconf = tsin12_config; if (dev->card_info->io_type[2]&NGENE_IO_TSIN && -@@ -1327,10 +1647,22 @@ static int ngene_buffer_config(struct ngene *dev) +@@ -1323,10 +1647,22 @@ static int ngene_buffer_config(struct ngene *dev) dev->ci.en) bconf = tsio1235_config; } @@ -32215,7 +32288,7 @@ index 970e833..84510db 100644 if (dev->card_info->io_type[3] == NGENE_IO_TSIN) bconf = BUFFER_CONFIG_3333; stat = ngene_command_config_buf(dev, bconf); -@@ -1403,8 +1735,10 @@ static int ngene_start(struct ngene *dev) +@@ -1399,8 +1735,10 @@ static int ngene_start(struct ngene *dev) if (stat < 0) goto fail; @@ -32227,7 +32300,7 @@ index 970e833..84510db 100644 fail: ngwritel(0, NGENE_INT_ENABLE); free_irq(dev->pci_dev->irq, dev); -@@ -1622,7 +1956,7 @@ static void ngene_unlink(struct ngene *dev) +@@ -1618,7 +1956,7 @@ static void ngene_unlink(struct ngene *dev) void ngene_shutdown(struct pci_dev *pdev) { @@ -32236,7 +32309,7 @@ index 970e833..84510db 100644 if (!dev || !shutdown_workaround) return; -@@ -1648,6 +1982,7 @@ void ngene_remove(struct pci_dev *pdev) +@@ -1644,6 +1982,7 @@ void ngene_remove(struct pci_dev *pdev) cxd_detach(dev); ngene_stop(dev); ngene_release_buffers(dev); @@ -32244,7 +32317,7 @@ index 970e833..84510db 100644 pci_disable_device(pdev); } -@@ -1687,10 +2022,36 @@ int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) +@@ -1683,10 +2022,36 @@ int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) dev->i2c_current_bus = -1; @@ -32283,7 +32356,7 @@ index 970e833..84510db 100644 goto fail2; return 0; -@@ -1701,5 +2062,6 @@ fail1: +@@ -1697,5 +2062,6 @@ fail1: ngene_release_buffers(dev); fail0: pci_disable_device(pci_dev); diff --git a/packages/linux/patches/3.16.5/linux-222-stb0899_signal_quality.patch b/packages/linux/patches/3.17.1/linux-222-stb0899_signal_quality.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-222-stb0899_signal_quality.patch rename to packages/linux/patches/3.17.1/linux-222-stb0899_signal_quality.patch diff --git a/packages/linux/patches/3.16.5/linux-223-Fix-video-artifacts-with-tt-3600-s2-usb.patch b/packages/linux/patches/3.17.1/linux-223-Fix-video-artifacts-with-tt-3600-s2-usb.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-223-Fix-video-artifacts-with-tt-3600-s2-usb.patch rename to packages/linux/patches/3.17.1/linux-223-Fix-video-artifacts-with-tt-3600-s2-usb.patch diff --git a/packages/linux/patches/3.16.5/linux-703-macmini2012-ethernet.patch b/packages/linux/patches/3.17.1/linux-703-macmini2012-ethernet.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-703-macmini2012-ethernet.patch rename to packages/linux/patches/3.17.1/linux-703-macmini2012-ethernet.patch diff --git a/packages/linux/patches/3.16.5/linux-705-Support-for-Buffalo-WLI-UC-G300HP-V1.patch b/packages/linux/patches/3.17.1/linux-705-Support-for-Buffalo-WLI-UC-G300HP-V1.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-705-Support-for-Buffalo-WLI-UC-G300HP-V1.patch rename to packages/linux/patches/3.17.1/linux-705-Support-for-Buffalo-WLI-UC-G300HP-V1.patch diff --git a/packages/linux/patches/3.16.5/linux-706-Sitecom-N300.patch b/packages/linux/patches/3.17.1/linux-706-Sitecom-N300.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-706-Sitecom-N300.patch rename to packages/linux/patches/3.17.1/linux-706-Sitecom-N300.patch diff --git a/packages/linux/patches/3.16.5/linux-900-hide_tsc_error.patch b/packages/linux/patches/3.17.1/linux-900-hide_tsc_error.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-900-hide_tsc_error.patch rename to packages/linux/patches/3.17.1/linux-900-hide_tsc_error.patch diff --git a/packages/linux/patches/3.16.5/linux-950-saa716x_PCIe_interface_chipset.patch b/packages/linux/patches/3.17.1/linux-950-saa716x_PCIe_interface_chipset.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-950-saa716x_PCIe_interface_chipset.patch rename to packages/linux/patches/3.17.1/linux-950-saa716x_PCIe_interface_chipset.patch diff --git a/packages/linux/patches/3.16.5/linux-990.06-hda-Avoid-outputting-HDMI-audio-before-prepare-.patch b/packages/linux/patches/3.17.1/linux-990.06-hda-Avoid-outputting-HDMI-audio-before-prepare-.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-990.06-hda-Avoid-outputting-HDMI-audio-before-prepare-.patch rename to packages/linux/patches/3.17.1/linux-990.06-hda-Avoid-outputting-HDMI-audio-before-prepare-.patch diff --git a/packages/linux/patches/3.16.5/linux-995-CX24120-13Z_frontend.patch b/packages/linux/patches/3.17.1/linux-995-CX24120-13Z_frontend.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-995-CX24120-13Z_frontend.patch rename to packages/linux/patches/3.17.1/linux-995-CX24120-13Z_frontend.patch diff --git a/packages/linux/patches/3.16.5/linux-999.02-0001-pm-disable-async-suspend-resume-by-default.patch b/packages/linux/patches/3.17.1/linux-999.02-0001-pm-disable-async-suspend-resume-by-default.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-999.02-0001-pm-disable-async-suspend-resume-by-default.patch rename to packages/linux/patches/3.17.1/linux-999.02-0001-pm-disable-async-suspend-resume-by-default.patch diff --git a/packages/linux/patches/3.16.5/linux-057-Removed-MCE-customer-code-restriction-in-rc6-decode.patch b/packages/linux/patches/3.17.1/todo/linux-057-Removed-MCE-customer-code-restriction-in-rc6-decode.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-057-Removed-MCE-customer-code-restriction-in-rc6-decode.patch rename to packages/linux/patches/3.17.1/todo/linux-057-Removed-MCE-customer-code-restriction-in-rc6-decode.patch diff --git a/packages/linux/patches/3.16.5/linux-061-valve-xpad-rework.patch b/packages/linux/patches/3.17.1/todo/linux-061-valve-xpad-rework.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-061-valve-xpad-rework.patch rename to packages/linux/patches/3.17.1/todo/linux-061-valve-xpad-rework.patch diff --git a/packages/linux/patches/3.16.5/linux-701-linksys_aes2500_brcmfmac.patch b/packages/linux/patches/3.17.1/todo/linux-701-linksys_aes2500_brcmfmac.patch similarity index 100% rename from packages/linux/patches/3.16.5/linux-701-linksys_aes2500_brcmfmac.patch rename to packages/linux/patches/3.17.1/todo/linux-701-linksys_aes2500_brcmfmac.patch diff --git a/projects/Generic/linux/linux.i386.conf b/projects/Generic/linux/linux.i386.conf index da99705936..0ab8488a76 100644 --- a/projects/Generic/linux/linux.i386.conf +++ b/projects/Generic/linux/linux.i386.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/i386 3.16.3 Kernel Configuration +# Linux/i386 3.17.1 Kernel Configuration # # CONFIG_64BIT is not set CONFIG_X86_32=y @@ -87,8 +87,8 @@ CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y CONFIG_CLOCKSOURCE_WATCHDOG=y CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_KTIME_SCALAR=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y @@ -126,9 +126,11 @@ CONFIG_RCU_FANOUT_LEAF=16 CONFIG_RCU_FAST_NO_HZ=y # CONFIG_TREE_RCU_TRACE is not set # CONFIG_RCU_NOCB_CPU is not set +CONFIG_BUILD_BIN2C=y CONFIG_IKCONFIG=m CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y CONFIG_ARCH_WANTS_PROT_NUMA_PROT_NONE=y CONFIG_CGROUPS=y @@ -437,6 +439,7 @@ CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y CONFIG_CLEANCACHE=y # CONFIG_FRONTSWAP is not set # CONFIG_CMA is not set +# CONFIG_ZPOOL is not set # CONFIG_ZBUD is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y @@ -497,6 +500,8 @@ CONFIG_PM_SLEEP_DEBUG=y CONFIG_PM_CLK=y # CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set CONFIG_ACPI=y +CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y +CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y CONFIG_ACPI_SLEEP=y # CONFIG_ACPI_PROCFS_POWER is not set # CONFIG_ACPI_EC_DEBUGFS is not set @@ -521,6 +526,8 @@ CONFIG_ACPI_CONTAINER=y # CONFIG_ACPI_CUSTOM_METHOD is not set # CONFIG_ACPI_BGRT is not set # CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +CONFIG_HAVE_ACPI_APEI=y +CONFIG_HAVE_ACPI_APEI_NMI=y # CONFIG_ACPI_APEI is not set # CONFIG_SFI is not set # CONFIG_APM is not set @@ -572,7 +579,6 @@ CONFIG_X86_SPEEDSTEP_LIB=y # CPU Idle # CONFIG_CPU_IDLE=y -# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y # CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set @@ -640,6 +646,7 @@ CONFIG_BINFMT_MISC=y # CONFIG_COREDUMP is not set CONFIG_HAVE_ATOMIC_IOMAP=y CONFIG_IOSF_MBI=m +CONFIG_PMC_ATOM=y CONFIG_NET=y # @@ -665,6 +672,7 @@ CONFIG_IP_MROUTE=y # CONFIG_IP_PIMSM_V1 is not set # CONFIG_IP_PIMSM_V2 is not set # CONFIG_SYN_COOKIES is not set +# CONFIG_NET_UDP_TUNNEL is not set # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set @@ -762,6 +770,7 @@ CONFIG_NETFILTER_XTABLES=m # CONFIG_NETFILTER_XT_TARGET_LED is not set # CONFIG_NETFILTER_XT_TARGET_LOG is not set # CONFIG_NETFILTER_XT_TARGET_MARK is not set +CONFIG_NETFILTER_XT_NAT=m # CONFIG_NETFILTER_XT_TARGET_NETMAP is not set # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set # CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set @@ -824,6 +833,11 @@ CONFIG_NETFILTER_XT_MATCH_STATE=m # CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m +# CONFIG_NF_LOG_ARP is not set +# CONFIG_NF_LOG_IPV4 is not set +CONFIG_NF_NAT_IPV4=m +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_H323 is not set CONFIG_IP_NF_IPTABLES=m # CONFIG_IP_NF_MATCH_AH is not set # CONFIG_IP_NF_MATCH_ECN is not set @@ -831,13 +845,10 @@ CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m # CONFIG_IP_NF_TARGET_SYNPROXY is not set -# CONFIG_IP_NF_TARGET_ULOG is not set -CONFIG_NF_NAT_IPV4=m +CONFIG_IP_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m # CONFIG_IP_NF_TARGET_NETMAP is not set # CONFIG_IP_NF_TARGET_REDIRECT is not set -# CONFIG_NF_NAT_PPTP is not set -# CONFIG_NF_NAT_H323 is not set # CONFIG_IP_NF_MANGLE is not set # CONFIG_IP_NF_RAW is not set # CONFIG_IP_NF_ARPTABLES is not set @@ -847,6 +858,8 @@ CONFIG_IP_NF_TARGET_MASQUERADE=m # CONFIG_NF_DEFRAG_IPV6=m CONFIG_NF_CONNTRACK_IPV6=m +# CONFIG_NF_LOG_IPV6 is not set +CONFIG_NF_NAT_IPV6=m CONFIG_IP6_NF_IPTABLES=m # CONFIG_IP6_NF_MATCH_AH is not set # CONFIG_IP6_NF_MATCH_EUI64 is not set @@ -861,7 +874,9 @@ CONFIG_IP6_NF_TARGET_REJECT=m # CONFIG_IP6_NF_TARGET_SYNPROXY is not set # CONFIG_IP6_NF_MANGLE is not set # CONFIG_IP6_NF_RAW is not set -# CONFIG_NF_NAT_IPV6 is not set +CONFIG_IP6_NF_NAT=m +# CONFIG_IP6_NF_TARGET_MASQUERADE is not set +# CONFIG_IP6_NF_TARGET_NPT is not set # CONFIG_BRIDGE_NF_EBTABLES is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set @@ -885,8 +900,8 @@ CONFIG_LLC=m # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_PHONET is not set +CONFIG_6LOWPAN=m # CONFIG_IEEE802154 is not set -CONFIG_6LOWPAN_IPHC=m # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set CONFIG_DNS_RESOLVER=y @@ -914,7 +929,7 @@ CONFIG_NET_FLOW_LIMIT=y # CONFIG_CAN is not set # CONFIG_IRDA is not set CONFIG_BT=m -CONFIG_BT_6LOWPAN=y +CONFIG_BT_6LOWPAN=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m @@ -957,7 +972,6 @@ CONFIG_LIB80211_CRYPT_TKIP=m # CONFIG_LIB80211_DEBUG is not set CONFIG_MAC80211=m CONFIG_MAC80211_HAS_RC=y -# CONFIG_MAC80211_RC_PID is not set CONFIG_MAC80211_RC_MINSTREL=y CONFIG_MAC80211_RC_MINSTREL_HT=y CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y @@ -990,7 +1004,7 @@ CONFIG_FW_LOADER=y CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_EXTRA_FIRMWARE="bnx2/bnx2-mips-06-6.2.1.fw bnx2/bnx2-mips-09-6.2.1a.fw bnx2/bnx2-rv2p-06-6.0.15.fw bnx2/bnx2-rv2p-09-6.0.17.fw bnx2/bnx2-rv2p-09ax-6.0.17.fw tigon/tg3.bin tigon/tg3_tso5.bin tigon/tg3_tso.bin rtl_nic/rtl8105e-1.fw rtl_nic/rtl8106e-1.fw rtl_nic/rtl8106e-2.fw rtl_nic/rtl8168d-1.fw rtl_nic/rtl8168d-2.fw rtl_nic/rtl8168e-1.fw rtl_nic/rtl8168e-2.fw rtl_nic/rtl8168e-3.fw rtl_nic/rtl8168f-1.fw rtl_nic/rtl8168f-2.fw rtl_nic/rtl8168g-1.fw rtl_nic/rtl8168g-2.fw rtl_nic/rtl8168g-3.fw rtl_nic/rtl8402-1.fw rtl_nic/rtl8411-1.fw rtl_nic/rtl8411-2.fw radeon/ARUBA_me.bin radeon/ARUBA_pfp.bin radeon/ARUBA_rlc.bin radeon/BARTS_mc.bin radeon/BARTS_me.bin radeon/BARTS_pfp.bin radeon/BARTS_smc.bin radeon/BONAIRE_ce.bin radeon/BONAIRE_mc.bin radeon/BONAIRE_mc2.bin radeon/BONAIRE_me.bin radeon/BONAIRE_mec.bin radeon/BONAIRE_pfp.bin radeon/BONAIRE_rlc.bin radeon/BONAIRE_sdma.bin radeon/BONAIRE_smc.bin radeon/BONAIRE_uvd.bin radeon/BONAIRE_vce.bin radeon/BTC_rlc.bin radeon/CAICOS_mc.bin radeon/CAICOS_me.bin radeon/CAICOS_pfp.bin radeon/CAICOS_smc.bin radeon/CAYMAN_mc.bin radeon/CAYMAN_me.bin radeon/CAYMAN_pfp.bin radeon/CAYMAN_rlc.bin radeon/CAYMAN_smc.bin radeon/CEDAR_me.bin radeon/CEDAR_pfp.bin radeon/CEDAR_rlc.bin radeon/CEDAR_smc.bin radeon/CYPRESS_me.bin radeon/CYPRESS_pfp.bin radeon/CYPRESS_rlc.bin radeon/CYPRESS_smc.bin radeon/CYPRESS_uvd.bin radeon/HAINAN_ce.bin radeon/HAINAN_mc.bin radeon/HAINAN_mc2.bin radeon/HAINAN_me.bin radeon/HAINAN_pfp.bin radeon/HAINAN_rlc.bin radeon/HAINAN_smc.bin radeon/HAWAII_ce.bin radeon/HAWAII_mc.bin radeon/HAWAII_mc2.bin radeon/HAWAII_me.bin radeon/HAWAII_mec.bin radeon/HAWAII_pfp.bin radeon/HAWAII_rlc.bin radeon/HAWAII_sdma.bin radeon/HAWAII_smc.bin radeon/JUNIPER_me.bin radeon/JUNIPER_pfp.bin radeon/JUNIPER_rlc.bin radeon/JUNIPER_smc.bin radeon/KABINI_ce.bin radeon/KABINI_me.bin radeon/KABINI_mec.bin radeon/KABINI_pfp.bin radeon/KABINI_rlc.bin radeon/KABINI_sdma.bin radeon/KAVERI_ce.bin radeon/KAVERI_me.bin radeon/KAVERI_mec.bin radeon/KAVERI_pfp.bin radeon/KAVERI_rlc.bin radeon/KAVERI_sdma.bin radeon/LICENSE.radeon radeon/MULLINS_ce.bin radeon/MULLINS_me.bin radeon/MULLINS_mec.bin radeon/MULLINS_pfp.bin radeon/MULLINS_rlc.bin radeon/MULLINS_sdma.bin radeon/OLAND_ce.bin radeon/OLAND_mc.bin radeon/OLAND_mc2.bin radeon/OLAND_me.bin radeon/OLAND_pfp.bin radeon/OLAND_rlc.bin radeon/OLAND_smc.bin radeon/PALM_me.bin radeon/PALM_pfp.bin radeon/PITCAIRN_ce.bin radeon/PITCAIRN_mc.bin radeon/PITCAIRN_mc2.bin radeon/PITCAIRN_me.bin radeon/PITCAIRN_pfp.bin radeon/PITCAIRN_rlc.bin radeon/PITCAIRN_smc.bin radeon/R100_cp.bin radeon/R200_cp.bin radeon/R300_cp.bin radeon/R420_cp.bin radeon/R520_cp.bin radeon/R600_me.bin radeon/R600_pfp.bin radeon/R600_rlc.bin radeon/R600_uvd.bin radeon/R700_rlc.bin radeon/REDWOOD_me.bin radeon/REDWOOD_pfp.bin radeon/REDWOOD_rlc.bin radeon/REDWOOD_smc.bin radeon/RS600_cp.bin radeon/RS690_cp.bin radeon/RS780_me.bin radeon/RS780_pfp.bin radeon/RS780_uvd.bin radeon/RV610_me.bin radeon/RV610_pfp.bin radeon/RV620_me.bin radeon/RV620_pfp.bin radeon/RV630_me.bin radeon/RV630_pfp.bin radeon/RV635_me.bin radeon/RV635_pfp.bin radeon/RV670_me.bin radeon/RV670_pfp.bin radeon/RV710_me.bin radeon/RV710_pfp.bin radeon/RV710_smc.bin radeon/RV710_uvd.bin radeon/RV730_me.bin radeon/RV730_pfp.bin radeon/RV730_smc.bin radeon/RV740_smc.bin radeon/RV770_me.bin radeon/RV770_pfp.bin radeon/RV770_smc.bin radeon/RV770_uvd.bin radeon/SUMO2_me.bin radeon/SUMO2_pfp.bin radeon/SUMO_me.bin radeon/SUMO_pfp.bin radeon/SUMO_rlc.bin radeon/SUMO_uvd.bin radeon/TAHITI_ce.bin radeon/TAHITI_mc.bin radeon/TAHITI_mc2.bin radeon/TAHITI_me.bin radeon/TAHITI_pfp.bin radeon/TAHITI_rlc.bin radeon/TAHITI_smc.bin radeon/TAHITI_uvd.bin radeon/TURKS_mc.bin radeon/TURKS_me.bin radeon/TURKS_pfp.bin radeon/TURKS_smc.bin radeon/VERDE_ce.bin radeon/VERDE_mc.bin radeon/VERDE_mc2.bin radeon/VERDE_me.bin radeon/VERDE_pfp.bin radeon/VERDE_rlc.bin radeon/VERDE_smc.bin" CONFIG_EXTRA_FIRMWARE_DIR="firmware" -# CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set @@ -999,6 +1013,7 @@ CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=m CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_FENCE_TRACE is not set # # Bus devices @@ -1088,6 +1103,10 @@ CONFIG_EEPROM_93CX6=m CONFIG_ALTERA_STAPL=m # CONFIG_VMWARE_VMCI is not set +# +# Intel MIC Bus Driver +# + # # Intel MIC Host Driver # @@ -1106,7 +1125,6 @@ CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set # CONFIG_SCSI_PROC_FS is not set @@ -1120,7 +1138,6 @@ CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SR_VENDOR is not set CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set -CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set CONFIG_SCSI_SCAN_ASYNC=y @@ -1142,7 +1159,6 @@ CONFIG_ISCSI_BOOT_SYSFS=y # CONFIG_SCSI_CXGB3_ISCSI is not set # CONFIG_SCSI_CXGB4_ISCSI is not set # CONFIG_SCSI_BNX2_ISCSI is not set -# CONFIG_SCSI_BNX2X_FCOE is not set # CONFIG_BE2ISCSI is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_SCSI_HPSA is not set @@ -1170,10 +1186,6 @@ CONFIG_SCSI_MVSAS=y # CONFIG_SCSI_HPTIOP is not set # CONFIG_SCSI_BUSLOGIC is not set # CONFIG_VMWARE_PVSCSI is not set -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_FCOE is not set -# CONFIG_FCOE_FNIC is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_EATA is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set @@ -1186,18 +1198,13 @@ CONFIG_SCSI_MVSAS=y # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_IPR is not set # CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLA_FC is not set # CONFIG_SCSI_QLA_ISCSI is not set -# CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_PMCRAID is not set # CONFIG_SCSI_PM8001 is not set -# CONFIG_SCSI_SRP is not set -# CONFIG_SCSI_BFA_FC is not set -# CONFIG_SCSI_CHELSIO_FCOE is not set # CONFIG_SCSI_DH is not set # CONFIG_SCSI_OSD_INITIATOR is not set CONFIG_ATA=y @@ -1352,6 +1359,7 @@ CONFIG_VORTEX=y CONFIG_NET_VENDOR_AMD=y # CONFIG_AMD8111_ETH is not set CONFIG_PCNET32=y +# CONFIG_NET_XGENE is not set CONFIG_NET_VENDOR_ARC=y CONFIG_NET_VENDOR_ATHEROS=y CONFIG_ATL2=y @@ -1369,7 +1377,6 @@ CONFIG_CNIC=y CONFIG_TIGON3=y # CONFIG_BNX2X is not set # CONFIG_NET_VENDOR_BROCADE is not set -# CONFIG_NET_CALXEDA_XGMAC is not set # CONFIG_NET_VENDOR_CHELSIO is not set # CONFIG_NET_VENDOR_CISCO is not set # CONFIG_CX_ECAT is not set @@ -1431,7 +1438,6 @@ CONFIG_8139TOO=y # CONFIG_8139TOO_8129 is not set # CONFIG_8139_OLD_RX_RESET is not set CONFIG_R8169=y -# CONFIG_SH_ETH is not set # CONFIG_NET_VENDOR_RDC is not set # CONFIG_NET_VENDOR_SAMSUNG is not set # CONFIG_NET_VENDOR_SEEQ is not set @@ -1489,10 +1495,7 @@ CONFIG_PPP_ASYNC=m # CONFIG_PPP_SYNC_TTY is not set # CONFIG_SLIP is not set CONFIG_SLHC=y - -# -# USB Network Adapters -# +CONFIG_USB_NET_DRIVERS=y # CONFIG_USB_CATC is not set # CONFIG_USB_KAWETH is not set # CONFIG_USB_PEGASUS is not set @@ -1581,6 +1584,7 @@ CONFIG_B43_PCICORE_AUTOSELECT=y CONFIG_B43_SDIO=y CONFIG_B43_BCMA_PIO=y CONFIG_B43_PIO=y +CONFIG_B43_PHY_G=y CONFIG_B43_PHY_N=y CONFIG_B43_PHY_LP=y CONFIG_B43_PHY_HT=y @@ -1599,8 +1603,11 @@ CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y CONFIG_BRCMUTIL=m # CONFIG_BRCMSMAC is not set CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_PROTO_MSGBUF=y # CONFIG_BRCMFMAC_SDIO is not set CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMFMAC_PCIE=y # CONFIG_BRCM_TRACING is not set # CONFIG_BRCMDBG is not set CONFIG_HOSTAP=m @@ -1892,7 +1899,12 @@ CONFIG_SERIAL_CORE=y # CONFIG_TCG_TPM is not set # CONFIG_TELCLOCK is not set CONFIG_DEVPORT=y + +# +# I2C support +# CONFIG_I2C=y +CONFIG_ACPI_I2C_OPREGION=y CONFIG_I2C_BOARDINFO=y # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y @@ -1999,8 +2011,6 @@ CONFIG_PINCTRL=y # # Pin controllers # -# CONFIG_PINMUX is not set -# CONFIG_PINCONF is not set # CONFIG_DEBUG_PINCTRL is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y # CONFIG_GPIOLIB is not set @@ -2066,6 +2076,7 @@ CONFIG_SENSORS_FAM15H_POWER=m CONFIG_SENSORS_CORETEMP=y CONFIG_SENSORS_IT87=m # CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LINEAGE is not set # CONFIG_SENSORS_LTC2945 is not set # CONFIG_SENSORS_LTC4151 is not set @@ -2126,6 +2137,7 @@ CONFIG_SENSORS_IT87=m # CONFIG_SENSORS_INA2XX is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set # CONFIG_SENSORS_VIA_CPUTEMP is not set @@ -2212,6 +2224,7 @@ CONFIG_MFD_CORE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_LPC_ICH is not set CONFIG_LPC_SCH=y +# CONFIG_INTEL_SOC_PMIC is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set # CONFIG_MFD_88PM800 is not set @@ -2270,6 +2283,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_ANALOG_TV_SUPPORT=y CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y # CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_SDR_SUPPORT is not set CONFIG_MEDIA_RC_SUPPORT=y # CONFIG_MEDIA_CONTROLLER is not set CONFIG_VIDEO_DEV=m @@ -2305,10 +2319,10 @@ CONFIG_IR_RC5_DECODER=m CONFIG_IR_RC6_DECODER=m CONFIG_IR_JVC_DECODER=m CONFIG_IR_SONY_DECODER=m -CONFIG_IR_RC5_SZ_DECODER=m CONFIG_IR_SANYO_DECODER=m CONFIG_IR_SHARP_DECODER=m CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_XMP_DECODER=m CONFIG_RC_DEVICES=y CONFIG_RC_ATI_REMOTE=m CONFIG_IR_ENE=m @@ -2352,12 +2366,14 @@ CONFIG_VIDEO_PVRUSB2_DVB=y CONFIG_VIDEO_STK1160_COMMON=m # CONFIG_VIDEO_STK1160_AC97 is not set CONFIG_VIDEO_STK1160=m +# CONFIG_VIDEO_GO7007 is not set # # Analog/digital TV USB devices # CONFIG_VIDEO_AU0828=m CONFIG_VIDEO_AU0828_V4L2=y +CONFIG_VIDEO_AU0828_RC=y CONFIG_VIDEO_CX231XX=m CONFIG_VIDEO_CX231XX_RC=y # CONFIG_VIDEO_CX231XX_ALSA is not set @@ -2437,6 +2453,7 @@ CONFIG_MEDIA_PCI_SUPPORT=y # CONFIG_VIDEO_HEXIUM_GEMINI is not set # CONFIG_VIDEO_HEXIUM_ORION is not set # CONFIG_VIDEO_MXB is not set +# CONFIG_VIDEO_SOLO6X10 is not set # # Media capture/analog/hybrid TV support @@ -2623,6 +2640,7 @@ CONFIG_DVB_M88DS3103=m # CONFIG_DVB_DRXK=m CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_SI2165=m CONFIG_DVB_STV0367DD=m CONFIG_DVB_TDA18212DD=m CONFIG_DVB_CXD2843=m @@ -3075,6 +3093,7 @@ CONFIG_DRAGONRISE_FF=y # CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y # CONFIG_HID_HOLTEK is not set +# CONFIG_HID_GT683R is not set # CONFIG_HID_HUION is not set # CONFIG_HID_KEYTOUCH is not set CONFIG_HID_KYE=y @@ -3085,7 +3104,7 @@ CONFIG_HID_GYRATION=y CONFIG_HID_TWINHAN=y CONFIG_HID_KENSINGTON=y CONFIG_HID_LCPOWER=y -CONFIG_HID_LENOVO_TPKBD=y +CONFIG_HID_LENOVO=y CONFIG_HID_LOGITECH=y CONFIG_HID_LOGITECH_DJ=y CONFIG_LOGITECH_FF=y @@ -3221,6 +3240,7 @@ CONFIG_USB_UAS=y # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set # CONFIG_USB_DWC2 is not set @@ -3308,6 +3328,7 @@ CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_YUREX is not set # CONFIG_USB_EZUSB_FX2 is not set # CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set # # USB Physical Layer drivers @@ -3447,6 +3468,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_PCF8523 is not set # CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF85063 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set # CONFIG_RTC_DRV_BQ32K is not set @@ -3469,6 +3491,8 @@ CONFIG_RTC_DRV_CMOS=y # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +CONFIG_RTC_DRV_EFI=y # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set # CONFIG_RTC_DRV_M48T35 is not set @@ -3477,12 +3501,10 @@ CONFIG_RTC_DRV_CMOS=y # CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set -# CONFIG_RTC_DRV_DS2404 is not set # # on-CPU RTC drivers # -# CONFIG_RTC_DRV_MOXART is not set # CONFIG_RTC_DRV_XGENE is not set # @@ -3514,8 +3536,6 @@ CONFIG_UIO=y CONFIG_STAGING=y CONFIG_ET131X=y # CONFIG_SLICOSS is not set -# CONFIG_USBIP_CORE is not set -CONFIG_W35UND=m # CONFIG_PRISM2_USB is not set # CONFIG_COMEDI is not set CONFIG_RTL8192U=m @@ -3526,17 +3546,10 @@ CONFIG_R8192EE=m CONFIG_R8821AE=m CONFIG_RTS5208=y # CONFIG_RTS5208_DEBUG is not set -# CONFIG_TRANZPORT is not set -# CONFIG_IDE_PHISON is not set # CONFIG_LINE6_USB is not set -# CONFIG_USB_SERIAL_QUATECH2 is not set # CONFIG_VT6655 is not set CONFIG_VT6656=m -# CONFIG_DX_SEP is not set -# CONFIG_CRYSTALHD is not set # CONFIG_FB_XGI is not set -# CONFIG_ACPI_QUICKSTART is not set -# CONFIG_USB_ENESTORAGE is not set # CONFIG_BCM_WIMAX is not set # CONFIG_FT1000 is not set @@ -3549,11 +3562,7 @@ CONFIG_STAGING_MEDIA=y CONFIG_DVB_AS102=m CONFIG_DVB_CXD2099=m # CONFIG_VIDEO_DT3155 is not set -# CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_TCM825X is not set -# CONFIG_USB_SN9C102 is not set -# CONFIG_SOLO6X10 is not set -CONFIG_DVB_RTL2832_SDR=m CONFIG_LIRC_STAGING=y # CONFIG_LIRC_BT829 is not set CONFIG_LIRC_IGORPLUGUSB=m @@ -3572,11 +3581,6 @@ CONFIG_LIRC_XBOX=m # CONFIG_USB_WPAN_HCD is not set # CONFIG_WIMAX_GDM72XX is not set # CONFIG_LTE_GDM724X is not set -CONFIG_NET_VENDOR_SILICOM=y -# CONFIG_SBYPASS is not set -# CONFIG_BPCTL is not set -# CONFIG_CED1401 is not set -# CONFIG_DGRP is not set # CONFIG_FIREWIRE_SERIAL is not set # CONFIG_LUSTRE_FS is not set # CONFIG_XILLYBUS is not set @@ -3606,6 +3610,7 @@ CONFIG_ACPI_WMI=m # CONFIG_TOPSTAR_LAPTOP is not set # CONFIG_ACPI_TOSHIBA is not set # CONFIG_TOSHIBA_BT_RFKILL is not set +# CONFIG_TOSHIBA_HAPS is not set # CONFIG_ACPI_CMPC is not set # CONFIG_INTEL_IPS is not set # CONFIG_IBM_RTL is not set @@ -3633,6 +3638,10 @@ CONFIG_COMMON_CLK=y # # Hardware Spinlock drivers # + +# +# Clock Source drivers +# CONFIG_CLKSRC_I8253=y CONFIG_CLKEVT_I8253=y CONFIG_CLKBLD_I8253=y @@ -3667,10 +3676,11 @@ CONFIG_CLKBLD_I8253=y # # CONFIG_GENERIC_PHY is not set # CONFIG_BCM_KONA_USB2_PHY is not set -# CONFIG_PHY_SAMSUNG_USB2 is not set CONFIG_POWERCAP=y CONFIG_INTEL_RAPL=m # CONFIG_MCB is not set +CONFIG_RAS=y +CONFIG_THUNDERBOLT=m # # Firmware Drivers @@ -3690,6 +3700,7 @@ CONFIG_ISCSI_IBFT=y # EFI (Extensible Firmware Interface) Support # CONFIG_EFI_VARS=y +CONFIG_EFI_RUNTIME_WRAPPERS=y # # File systems @@ -3918,7 +3929,7 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y # printk and dmesg options # CONFIG_PRINTK_TIME=y -CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_DYNAMIC_DEBUG is not set @@ -3986,7 +3997,6 @@ CONFIG_PANIC_TIMEOUT=0 # Lock Debugging (spinlocks, mutexes, etc...) # # CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_MUTEXES is not set # CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set @@ -3996,6 +4006,7 @@ CONFIG_PANIC_TIMEOUT=0 # CONFIG_DEBUG_ATOMIC_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_STACKTRACE is not set # CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_LIST is not set @@ -4023,7 +4034,6 @@ CONFIG_USER_STACKTRACE_SUPPORT=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST=y -CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y @@ -4044,11 +4054,14 @@ CONFIG_TRACING_SUPPORT=y # CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_TEST_STRING_HELPERS is not set # CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_RHASHTABLE is not set # CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set # CONFIG_DMA_API_DEBUG is not set # CONFIG_TEST_MODULE is not set # CONFIG_TEST_USER_COPY is not set # CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -4206,6 +4219,7 @@ CONFIG_CRYPTO_DES=y # Random Number Generation # # CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_DRBG_MENU is not set # CONFIG_CRYPTO_USER_API_HASH is not set # CONFIG_CRYPTO_USER_API_SKCIPHER is not set # CONFIG_CRYPTO_HW is not set @@ -4226,6 +4240,7 @@ CONFIG_GENERIC_FIND_FIRST_BIT=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_IOMAP=y CONFIG_GENERIC_IO=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_CRC_CCITT=y CONFIG_CRC16=y # CONFIG_CRC_T10DIF is not set @@ -4263,6 +4278,8 @@ CONFIG_HAS_DMA=y CONFIG_CHECK_SIGNATURE=y CONFIG_CPU_RMAP=y CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set CONFIG_NLATTR=y CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y CONFIG_AVERAGE=y @@ -4274,3 +4291,4 @@ CONFIG_FONT_SUPPORT=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y +CONFIG_ARCH_HAS_SG_CHAIN=y diff --git a/projects/Generic/linux/linux.x86_64.conf b/projects/Generic/linux/linux.x86_64.conf index 5bc148bd6a..84ed1b08ac 100644 --- a/projects/Generic/linux/linux.x86_64.conf +++ b/projects/Generic/linux/linux.x86_64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/x86_64 3.16.3 Kernel Configuration +# Linux/x86_64 3.17.1 Kernel Configuration # CONFIG_64BIT=y CONFIG_X86_64=y @@ -88,6 +88,7 @@ CONFIG_IRQ_FORCED_THREADING=y CONFIG_SPARSE_IRQ=y CONFIG_CLOCKSOURCE_WATCHDOG=y CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -132,10 +133,14 @@ CONFIG_RCU_FANOUT_LEAF=16 CONFIG_RCU_FAST_NO_HZ=y # CONFIG_TREE_RCU_TRACE is not set CONFIG_RCU_NOCB_CPU=y +# CONFIG_RCU_NOCB_CPU_NONE is not set +# CONFIG_RCU_NOCB_CPU_ZERO is not set CONFIG_RCU_NOCB_CPU_ALL=y +CONFIG_BUILD_BIN2C=y CONFIG_IKCONFIG=m CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y CONFIG_ARCH_SUPPORTS_INT128=y @@ -433,6 +438,7 @@ CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y CONFIG_CLEANCACHE=y # CONFIG_FRONTSWAP is not set # CONFIG_CMA is not set +# CONFIG_ZPOOL is not set # CONFIG_ZBUD is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y @@ -492,6 +498,8 @@ CONFIG_PM_SLEEP_DEBUG=y CONFIG_PM_CLK=y # CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set CONFIG_ACPI=y +CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y +CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y CONFIG_ACPI_SLEEP=y # CONFIG_ACPI_PROCFS_POWER is not set # CONFIG_ACPI_EC_DEBUGFS is not set @@ -517,6 +525,8 @@ CONFIG_ACPI_CONTAINER=y # CONFIG_ACPI_CUSTOM_METHOD is not set # CONFIG_ACPI_BGRT is not set # CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +CONFIG_HAVE_ACPI_APEI=y +CONFIG_HAVE_ACPI_APEI_NMI=y # CONFIG_ACPI_APEI is not set # CONFIG_SFI is not set @@ -558,7 +568,6 @@ CONFIG_X86_SPEEDSTEP_LIB=y # CPU Idle # CONFIG_CPU_IDLE=y -# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y # CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set @@ -627,6 +636,7 @@ CONFIG_SYSVIPC_COMPAT=y CONFIG_KEYS_COMPAT=y CONFIG_X86_DEV_DMA_OPS=y CONFIG_IOSF_MBI=m +CONFIG_PMC_ATOM=y CONFIG_NET=y CONFIG_COMPAT_NETLINK_MESSAGES=y @@ -653,6 +663,7 @@ CONFIG_IP_MROUTE=y # CONFIG_IP_PIMSM_V1 is not set # CONFIG_IP_PIMSM_V2 is not set # CONFIG_SYN_COOKIES is not set +# CONFIG_NET_UDP_TUNNEL is not set # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set @@ -750,6 +761,7 @@ CONFIG_NETFILTER_XTABLES=m # CONFIG_NETFILTER_XT_TARGET_LED is not set # CONFIG_NETFILTER_XT_TARGET_LOG is not set # CONFIG_NETFILTER_XT_TARGET_MARK is not set +CONFIG_NETFILTER_XT_NAT=m # CONFIG_NETFILTER_XT_TARGET_NETMAP is not set # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set # CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set @@ -812,6 +824,11 @@ CONFIG_NETFILTER_XT_MATCH_STATE=m # CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m +# CONFIG_NF_LOG_ARP is not set +# CONFIG_NF_LOG_IPV4 is not set +CONFIG_NF_NAT_IPV4=m +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_H323 is not set CONFIG_IP_NF_IPTABLES=m # CONFIG_IP_NF_MATCH_AH is not set # CONFIG_IP_NF_MATCH_ECN is not set @@ -819,13 +836,10 @@ CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m # CONFIG_IP_NF_TARGET_SYNPROXY is not set -# CONFIG_IP_NF_TARGET_ULOG is not set -CONFIG_NF_NAT_IPV4=m +CONFIG_IP_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m # CONFIG_IP_NF_TARGET_NETMAP is not set # CONFIG_IP_NF_TARGET_REDIRECT is not set -# CONFIG_NF_NAT_PPTP is not set -# CONFIG_NF_NAT_H323 is not set # CONFIG_IP_NF_MANGLE is not set # CONFIG_IP_NF_RAW is not set # CONFIG_IP_NF_ARPTABLES is not set @@ -835,6 +849,8 @@ CONFIG_IP_NF_TARGET_MASQUERADE=m # CONFIG_NF_DEFRAG_IPV6=m CONFIG_NF_CONNTRACK_IPV6=m +# CONFIG_NF_LOG_IPV6 is not set +CONFIG_NF_NAT_IPV6=m CONFIG_IP6_NF_IPTABLES=m # CONFIG_IP6_NF_MATCH_AH is not set # CONFIG_IP6_NF_MATCH_EUI64 is not set @@ -849,7 +865,9 @@ CONFIG_IP6_NF_TARGET_REJECT=m # CONFIG_IP6_NF_TARGET_SYNPROXY is not set # CONFIG_IP6_NF_MANGLE is not set # CONFIG_IP6_NF_RAW is not set -# CONFIG_NF_NAT_IPV6 is not set +CONFIG_IP6_NF_NAT=m +# CONFIG_IP6_NF_TARGET_MASQUERADE is not set +# CONFIG_IP6_NF_TARGET_NPT is not set # CONFIG_BRIDGE_NF_EBTABLES is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set @@ -873,8 +891,8 @@ CONFIG_LLC=m # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_PHONET is not set +CONFIG_6LOWPAN=m # CONFIG_IEEE802154 is not set -CONFIG_6LOWPAN_IPHC=m # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set CONFIG_DNS_RESOLVER=y @@ -903,7 +921,7 @@ CONFIG_NET_FLOW_LIMIT=y # CONFIG_CAN is not set # CONFIG_IRDA is not set CONFIG_BT=m -CONFIG_BT_6LOWPAN=y +CONFIG_BT_6LOWPAN=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y CONFIG_BT_BNEP=m @@ -946,7 +964,6 @@ CONFIG_LIB80211_CRYPT_TKIP=m # CONFIG_LIB80211_DEBUG is not set CONFIG_MAC80211=m CONFIG_MAC80211_HAS_RC=y -# CONFIG_MAC80211_RC_PID is not set CONFIG_MAC80211_RC_MINSTREL=y CONFIG_MAC80211_RC_MINSTREL_HT=y CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y @@ -980,7 +997,7 @@ CONFIG_FW_LOADER=y CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_EXTRA_FIRMWARE="bnx2/bnx2-mips-06-6.2.1.fw bnx2/bnx2-mips-09-6.2.1a.fw bnx2/bnx2-rv2p-06-6.0.15.fw bnx2/bnx2-rv2p-09-6.0.17.fw bnx2/bnx2-rv2p-09ax-6.0.17.fw tigon/tg3.bin tigon/tg3_tso5.bin tigon/tg3_tso.bin rtl_nic/rtl8105e-1.fw rtl_nic/rtl8106e-1.fw rtl_nic/rtl8106e-2.fw rtl_nic/rtl8168d-1.fw rtl_nic/rtl8168d-2.fw rtl_nic/rtl8168e-1.fw rtl_nic/rtl8168e-2.fw rtl_nic/rtl8168e-3.fw rtl_nic/rtl8168f-1.fw rtl_nic/rtl8168f-2.fw rtl_nic/rtl8168g-1.fw rtl_nic/rtl8168g-2.fw rtl_nic/rtl8168g-3.fw rtl_nic/rtl8402-1.fw rtl_nic/rtl8411-1.fw rtl_nic/rtl8411-2.fw radeon/ARUBA_me.bin radeon/ARUBA_pfp.bin radeon/ARUBA_rlc.bin radeon/BARTS_mc.bin radeon/BARTS_me.bin radeon/BARTS_pfp.bin radeon/BARTS_smc.bin radeon/BONAIRE_ce.bin radeon/BONAIRE_mc.bin radeon/BONAIRE_mc2.bin radeon/BONAIRE_me.bin radeon/BONAIRE_mec.bin radeon/BONAIRE_pfp.bin radeon/BONAIRE_rlc.bin radeon/BONAIRE_sdma.bin radeon/BONAIRE_smc.bin radeon/BONAIRE_uvd.bin radeon/BONAIRE_vce.bin radeon/BTC_rlc.bin radeon/CAICOS_mc.bin radeon/CAICOS_me.bin radeon/CAICOS_pfp.bin radeon/CAICOS_smc.bin radeon/CAYMAN_mc.bin radeon/CAYMAN_me.bin radeon/CAYMAN_pfp.bin radeon/CAYMAN_rlc.bin radeon/CAYMAN_smc.bin radeon/CEDAR_me.bin radeon/CEDAR_pfp.bin radeon/CEDAR_rlc.bin radeon/CEDAR_smc.bin radeon/CYPRESS_me.bin radeon/CYPRESS_pfp.bin radeon/CYPRESS_rlc.bin radeon/CYPRESS_smc.bin radeon/CYPRESS_uvd.bin radeon/HAINAN_ce.bin radeon/HAINAN_mc.bin radeon/HAINAN_mc2.bin radeon/HAINAN_me.bin radeon/HAINAN_pfp.bin radeon/HAINAN_rlc.bin radeon/HAINAN_smc.bin radeon/HAWAII_ce.bin radeon/HAWAII_mc.bin radeon/HAWAII_mc2.bin radeon/HAWAII_me.bin radeon/HAWAII_mec.bin radeon/HAWAII_pfp.bin radeon/HAWAII_rlc.bin radeon/HAWAII_sdma.bin radeon/HAWAII_smc.bin radeon/JUNIPER_me.bin radeon/JUNIPER_pfp.bin radeon/JUNIPER_rlc.bin radeon/JUNIPER_smc.bin radeon/KABINI_ce.bin radeon/KABINI_me.bin radeon/KABINI_mec.bin radeon/KABINI_pfp.bin radeon/KABINI_rlc.bin radeon/KABINI_sdma.bin radeon/KAVERI_ce.bin radeon/KAVERI_me.bin radeon/KAVERI_mec.bin radeon/KAVERI_pfp.bin radeon/KAVERI_rlc.bin radeon/KAVERI_sdma.bin radeon/LICENSE.radeon radeon/MULLINS_ce.bin radeon/MULLINS_me.bin radeon/MULLINS_mec.bin radeon/MULLINS_pfp.bin radeon/MULLINS_rlc.bin radeon/MULLINS_sdma.bin radeon/OLAND_ce.bin radeon/OLAND_mc.bin radeon/OLAND_mc2.bin radeon/OLAND_me.bin radeon/OLAND_pfp.bin radeon/OLAND_rlc.bin radeon/OLAND_smc.bin radeon/PALM_me.bin radeon/PALM_pfp.bin radeon/PITCAIRN_ce.bin radeon/PITCAIRN_mc.bin radeon/PITCAIRN_mc2.bin radeon/PITCAIRN_me.bin radeon/PITCAIRN_pfp.bin radeon/PITCAIRN_rlc.bin radeon/PITCAIRN_smc.bin radeon/R100_cp.bin radeon/R200_cp.bin radeon/R300_cp.bin radeon/R420_cp.bin radeon/R520_cp.bin radeon/R600_me.bin radeon/R600_pfp.bin radeon/R600_rlc.bin radeon/R600_uvd.bin radeon/R700_rlc.bin radeon/REDWOOD_me.bin radeon/REDWOOD_pfp.bin radeon/REDWOOD_rlc.bin radeon/REDWOOD_smc.bin radeon/RS600_cp.bin radeon/RS690_cp.bin radeon/RS780_me.bin radeon/RS780_pfp.bin radeon/RS780_uvd.bin radeon/RV610_me.bin radeon/RV610_pfp.bin radeon/RV620_me.bin radeon/RV620_pfp.bin radeon/RV630_me.bin radeon/RV630_pfp.bin radeon/RV635_me.bin radeon/RV635_pfp.bin radeon/RV670_me.bin radeon/RV670_pfp.bin radeon/RV710_me.bin radeon/RV710_pfp.bin radeon/RV710_smc.bin radeon/RV710_uvd.bin radeon/RV730_me.bin radeon/RV730_pfp.bin radeon/RV730_smc.bin radeon/RV740_smc.bin radeon/RV770_me.bin radeon/RV770_pfp.bin radeon/RV770_smc.bin radeon/RV770_uvd.bin radeon/SUMO2_me.bin radeon/SUMO2_pfp.bin radeon/SUMO_me.bin radeon/SUMO_pfp.bin radeon/SUMO_rlc.bin radeon/SUMO_uvd.bin radeon/TAHITI_ce.bin radeon/TAHITI_mc.bin radeon/TAHITI_mc2.bin radeon/TAHITI_me.bin radeon/TAHITI_pfp.bin radeon/TAHITI_rlc.bin radeon/TAHITI_smc.bin radeon/TAHITI_uvd.bin radeon/TURKS_mc.bin radeon/TURKS_me.bin radeon/TURKS_pfp.bin radeon/TURKS_smc.bin radeon/VERDE_ce.bin radeon/VERDE_mc.bin radeon/VERDE_mc2.bin radeon/VERDE_me.bin radeon/VERDE_pfp.bin radeon/VERDE_rlc.bin radeon/VERDE_smc.bin" CONFIG_EXTRA_FIRMWARE_DIR="firmware" -# CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set @@ -989,6 +1006,7 @@ CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_REGMAP=y CONFIG_REGMAP_I2C=m CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_FENCE_TRACE is not set # # Bus devices @@ -1078,15 +1096,18 @@ CONFIG_EEPROM_93CX6=m CONFIG_ALTERA_STAPL=m # CONFIG_VMWARE_VMCI is not set +# +# Intel MIC Bus Driver +# +# CONFIG_INTEL_MIC_BUS is not set + # # Intel MIC Host Driver # -# CONFIG_INTEL_MIC_HOST is not set # # Intel MIC Card Driver # -# CONFIG_INTEL_MIC_CARD is not set # CONFIG_GENWQE is not set # CONFIG_ECHO is not set CONFIG_HAVE_IDE=y @@ -1099,7 +1120,6 @@ CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set # CONFIG_SCSI_PROC_FS is not set @@ -1113,7 +1133,6 @@ CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SR_VENDOR is not set CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set -CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set CONFIG_SCSI_SCAN_ASYNC=y @@ -1135,7 +1154,6 @@ CONFIG_ISCSI_BOOT_SYSFS=y # CONFIG_SCSI_CXGB3_ISCSI is not set # CONFIG_SCSI_CXGB4_ISCSI is not set # CONFIG_SCSI_BNX2_ISCSI is not set -# CONFIG_SCSI_BNX2X_FCOE is not set # CONFIG_BE2ISCSI is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_SCSI_HPSA is not set @@ -1163,10 +1181,6 @@ CONFIG_SCSI_MVSAS=y # CONFIG_SCSI_HPTIOP is not set # CONFIG_SCSI_BUSLOGIC is not set # CONFIG_VMWARE_PVSCSI is not set -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set -# CONFIG_FCOE is not set -# CONFIG_FCOE_FNIC is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_EATA is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set @@ -1179,17 +1193,12 @@ CONFIG_SCSI_MVSAS=y # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_IPR is not set # CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLA_FC is not set # CONFIG_SCSI_QLA_ISCSI is not set -# CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_PMCRAID is not set # CONFIG_SCSI_PM8001 is not set -# CONFIG_SCSI_SRP is not set -# CONFIG_SCSI_BFA_FC is not set -# CONFIG_SCSI_CHELSIO_FCOE is not set # CONFIG_SCSI_DH is not set # CONFIG_SCSI_OSD_INITIATOR is not set CONFIG_ATA=y @@ -1339,6 +1348,7 @@ CONFIG_VORTEX=y CONFIG_NET_VENDOR_AMD=y # CONFIG_AMD8111_ETH is not set CONFIG_PCNET32=y +# CONFIG_NET_XGENE is not set CONFIG_NET_VENDOR_ARC=y CONFIG_NET_VENDOR_ATHEROS=y CONFIG_ATL2=y @@ -1356,7 +1366,6 @@ CONFIG_CNIC=y CONFIG_TIGON3=y # CONFIG_BNX2X is not set # CONFIG_NET_VENDOR_BROCADE is not set -# CONFIG_NET_CALXEDA_XGMAC is not set # CONFIG_NET_VENDOR_CHELSIO is not set # CONFIG_NET_VENDOR_CISCO is not set # CONFIG_CX_ECAT is not set @@ -1418,7 +1427,6 @@ CONFIG_8139TOO=y # CONFIG_8139TOO_8129 is not set # CONFIG_8139_OLD_RX_RESET is not set CONFIG_R8169=y -# CONFIG_SH_ETH is not set # CONFIG_NET_VENDOR_RDC is not set # CONFIG_NET_VENDOR_SAMSUNG is not set # CONFIG_NET_VENDOR_SEEQ is not set @@ -1476,10 +1484,7 @@ CONFIG_PPP_ASYNC=m # CONFIG_PPP_SYNC_TTY is not set # CONFIG_SLIP is not set CONFIG_SLHC=y - -# -# USB Network Adapters -# +CONFIG_USB_NET_DRIVERS=y # CONFIG_USB_CATC is not set # CONFIG_USB_KAWETH is not set # CONFIG_USB_PEGASUS is not set @@ -1568,6 +1573,7 @@ CONFIG_B43_PCICORE_AUTOSELECT=y CONFIG_B43_SDIO=y CONFIG_B43_BCMA_PIO=y CONFIG_B43_PIO=y +CONFIG_B43_PHY_G=y CONFIG_B43_PHY_N=y CONFIG_B43_PHY_LP=y CONFIG_B43_PHY_HT=y @@ -1586,8 +1592,11 @@ CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y CONFIG_BRCMUTIL=m # CONFIG_BRCMSMAC is not set CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_PROTO_MSGBUF=y # CONFIG_BRCMFMAC_SDIO is not set CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMFMAC_PCIE=y # CONFIG_BRCM_TRACING is not set # CONFIG_BRCMDBG is not set CONFIG_HOSTAP=m @@ -1873,7 +1882,12 @@ CONFIG_SERIAL_CORE=y # CONFIG_TCG_TPM is not set # CONFIG_TELCLOCK is not set CONFIG_DEVPORT=y + +# +# I2C support +# CONFIG_I2C=y +CONFIG_ACPI_I2C_OPREGION=y CONFIG_I2C_BOARDINFO=y # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y @@ -1977,8 +1991,6 @@ CONFIG_PINCTRL=y # # Pin controllers # -# CONFIG_PINMUX is not set -# CONFIG_PINCONF is not set # CONFIG_DEBUG_PINCTRL is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y # CONFIG_GPIOLIB is not set @@ -2044,6 +2056,7 @@ CONFIG_SENSORS_FAM15H_POWER=m CONFIG_SENSORS_CORETEMP=y CONFIG_SENSORS_IT87=m # CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LINEAGE is not set # CONFIG_SENSORS_LTC2945 is not set # CONFIG_SENSORS_LTC4151 is not set @@ -2104,6 +2117,7 @@ CONFIG_SENSORS_IT87=m # CONFIG_SENSORS_INA2XX is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set # CONFIG_SENSORS_VIA_CPUTEMP is not set @@ -2176,7 +2190,6 @@ CONFIG_BCMA_DRIVER_GMAC_CMN=y # Multifunction device drivers # CONFIG_MFD_CORE=y -# CONFIG_MFD_CS5535 is not set # CONFIG_MFD_AS3711 is not set # CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_BCM590XX is not set @@ -2190,6 +2203,7 @@ CONFIG_MFD_CORE=y # CONFIG_HTC_PASIC3 is not set # CONFIG_LPC_ICH is not set CONFIG_LPC_SCH=y +# CONFIG_INTEL_SOC_PMIC is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set # CONFIG_MFD_88PM800 is not set @@ -2248,6 +2262,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_ANALOG_TV_SUPPORT=y CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y # CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_SDR_SUPPORT is not set CONFIG_MEDIA_RC_SUPPORT=y # CONFIG_MEDIA_CONTROLLER is not set CONFIG_VIDEO_DEV=m @@ -2283,10 +2298,10 @@ CONFIG_IR_RC5_DECODER=m CONFIG_IR_RC6_DECODER=m CONFIG_IR_JVC_DECODER=m CONFIG_IR_SONY_DECODER=m -CONFIG_IR_RC5_SZ_DECODER=m CONFIG_IR_SANYO_DECODER=m CONFIG_IR_SHARP_DECODER=m CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_XMP_DECODER=m CONFIG_RC_DEVICES=y CONFIG_RC_ATI_REMOTE=m CONFIG_IR_ENE=m @@ -2330,12 +2345,14 @@ CONFIG_VIDEO_PVRUSB2_DVB=y CONFIG_VIDEO_STK1160_COMMON=m # CONFIG_VIDEO_STK1160_AC97 is not set CONFIG_VIDEO_STK1160=m +# CONFIG_VIDEO_GO7007 is not set # # Analog/digital TV USB devices # CONFIG_VIDEO_AU0828=m CONFIG_VIDEO_AU0828_V4L2=y +CONFIG_VIDEO_AU0828_RC=y CONFIG_VIDEO_CX231XX=m CONFIG_VIDEO_CX231XX_RC=y # CONFIG_VIDEO_CX231XX_ALSA is not set @@ -2415,6 +2432,7 @@ CONFIG_MEDIA_PCI_SUPPORT=y # CONFIG_VIDEO_HEXIUM_GEMINI is not set # CONFIG_VIDEO_HEXIUM_ORION is not set # CONFIG_VIDEO_MXB is not set +# CONFIG_VIDEO_SOLO6X10 is not set # # Media capture/analog/hybrid TV support @@ -2601,6 +2619,7 @@ CONFIG_DVB_M88DS3103=m # CONFIG_DVB_DRXK=m CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_SI2165=m CONFIG_DVB_STV0367DD=m CONFIG_DVB_TDA18212DD=m CONFIG_DVB_CXD2843=m @@ -3042,6 +3061,7 @@ CONFIG_DRAGONRISE_FF=y # CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y # CONFIG_HID_HOLTEK is not set +# CONFIG_HID_GT683R is not set # CONFIG_HID_HUION is not set # CONFIG_HID_KEYTOUCH is not set CONFIG_HID_KYE=y @@ -3052,7 +3072,7 @@ CONFIG_HID_GYRATION=y CONFIG_HID_TWINHAN=y CONFIG_HID_KENSINGTON=y CONFIG_HID_LCPOWER=y -CONFIG_HID_LENOVO_TPKBD=y +CONFIG_HID_LENOVO=y CONFIG_HID_LOGITECH=y CONFIG_HID_LOGITECH_DJ=y CONFIG_LOGITECH_FF=y @@ -3188,6 +3208,7 @@ CONFIG_USB_UAS=y # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set # CONFIG_USB_DWC2 is not set @@ -3275,6 +3296,7 @@ CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_YUREX is not set # CONFIG_USB_EZUSB_FX2 is not set # CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set # # USB Physical Layer drivers @@ -3413,6 +3435,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_PCF8523 is not set # CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF85063 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set # CONFIG_RTC_DRV_BQ32K is not set @@ -3435,6 +3458,8 @@ CONFIG_RTC_DRV_CMOS=y # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +CONFIG_RTC_DRV_EFI=y # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set # CONFIG_RTC_DRV_M48T35 is not set @@ -3443,12 +3468,10 @@ CONFIG_RTC_DRV_CMOS=y # CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set -# CONFIG_RTC_DRV_DS2404 is not set # # on-CPU RTC drivers # -# CONFIG_RTC_DRV_MOXART is not set # CONFIG_RTC_DRV_XGENE is not set # @@ -3480,8 +3503,6 @@ CONFIG_UIO=y CONFIG_STAGING=y CONFIG_ET131X=y # CONFIG_SLICOSS is not set -# CONFIG_USBIP_CORE is not set -CONFIG_W35UND=m # CONFIG_PRISM2_USB is not set # CONFIG_COMEDI is not set CONFIG_RTL8192U=m @@ -3492,17 +3513,10 @@ CONFIG_R8192EE=m CONFIG_R8821AE=m CONFIG_RTS5208=y # CONFIG_RTS5208_DEBUG is not set -# CONFIG_TRANZPORT is not set -# CONFIG_IDE_PHISON is not set # CONFIG_LINE6_USB is not set -# CONFIG_USB_SERIAL_QUATECH2 is not set # CONFIG_VT6655 is not set CONFIG_VT6656=m -# CONFIG_DX_SEP is not set -# CONFIG_CRYSTALHD is not set # CONFIG_FB_XGI is not set -# CONFIG_ACPI_QUICKSTART is not set -# CONFIG_USB_ENESTORAGE is not set # CONFIG_BCM_WIMAX is not set # CONFIG_FT1000 is not set @@ -3515,11 +3529,7 @@ CONFIG_STAGING_MEDIA=y CONFIG_DVB_AS102=m CONFIG_DVB_CXD2099=m # CONFIG_VIDEO_DT3155 is not set -# CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_TCM825X is not set -# CONFIG_USB_SN9C102 is not set -# CONFIG_SOLO6X10 is not set -CONFIG_DVB_RTL2832_SDR=m CONFIG_LIRC_STAGING=y # CONFIG_LIRC_BT829 is not set CONFIG_LIRC_IGORPLUGUSB=m @@ -3538,11 +3548,6 @@ CONFIG_LIRC_XBOX=m # CONFIG_USB_WPAN_HCD is not set # CONFIG_WIMAX_GDM72XX is not set # CONFIG_LTE_GDM724X is not set -CONFIG_NET_VENDOR_SILICOM=y -# CONFIG_SBYPASS is not set -# CONFIG_BPCTL is not set -# CONFIG_CED1401 is not set -# CONFIG_DGRP is not set # CONFIG_FIREWIRE_SERIAL is not set # CONFIG_LUSTRE_FS is not set # CONFIG_XILLYBUS is not set @@ -3551,6 +3556,7 @@ CONFIG_NET_VENDOR_SILICOM=y # CONFIG_GS_FPGABOOT is not set # CONFIG_CRYPTO_SKEIN is not set # CONFIG_CRYPTO_THREEFISH is not set +# CONFIG_UNISYSSPAR is not set CONFIG_X86_PLATFORM_DEVICES=y # CONFIG_ACER_WMI is not set # CONFIG_ACERHDF is not set @@ -3573,6 +3579,7 @@ CONFIG_ACPI_WMI=m # CONFIG_TOPSTAR_LAPTOP is not set # CONFIG_ACPI_TOSHIBA is not set # CONFIG_TOSHIBA_BT_RFKILL is not set +# CONFIG_TOSHIBA_HAPS is not set # CONFIG_ACPI_CMPC is not set # CONFIG_INTEL_IPS is not set # CONFIG_IBM_RTL is not set @@ -3600,6 +3607,10 @@ CONFIG_COMMON_CLK=y # # Hardware Spinlock drivers # + +# +# Clock Source drivers +# CONFIG_CLKEVT_I8253=y CONFIG_CLKBLD_I8253=y # CONFIG_SH_TIMER_CMT is not set @@ -3633,10 +3644,11 @@ CONFIG_CLKBLD_I8253=y # # CONFIG_GENERIC_PHY is not set # CONFIG_BCM_KONA_USB2_PHY is not set -# CONFIG_PHY_SAMSUNG_USB2 is not set CONFIG_POWERCAP=y CONFIG_INTEL_RAPL=m # CONFIG_MCB is not set +CONFIG_RAS=y +CONFIG_THUNDERBOLT=m # # Firmware Drivers @@ -3656,6 +3668,7 @@ CONFIG_ISCSI_IBFT=y # EFI (Extensible Firmware Interface) Support # CONFIG_EFI_VARS=y +CONFIG_EFI_RUNTIME_WRAPPERS=y # # File systems @@ -3884,7 +3897,7 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y # printk and dmesg options # CONFIG_PRINTK_TIME=y -CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_DYNAMIC_DEBUG is not set @@ -3951,7 +3964,6 @@ CONFIG_PANIC_TIMEOUT=0 # Lock Debugging (spinlocks, mutexes, etc...) # # CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_MUTEXES is not set # CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set @@ -3961,6 +3973,7 @@ CONFIG_PANIC_TIMEOUT=0 # CONFIG_DEBUG_ATOMIC_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_STACKTRACE is not set # CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_LIST is not set @@ -3988,7 +4001,6 @@ CONFIG_USER_STACKTRACE_SUPPORT=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_FP_TEST=y -CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y @@ -4010,11 +4022,14 @@ CONFIG_TRACING_SUPPORT=y # CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_TEST_STRING_HELPERS is not set # CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_RHASHTABLE is not set # CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set # CONFIG_DMA_API_DEBUG is not set # CONFIG_TEST_MODULE is not set # CONFIG_TEST_USER_COPY is not set # CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -4159,6 +4174,7 @@ CONFIG_CRYPTO_ARC4=y # CONFIG_CRYPTO_CAST6 is not set # CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_SALSA20 is not set @@ -4187,6 +4203,7 @@ CONFIG_CRYPTO_DES=y # Random Number Generation # # CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_DRBG_MENU is not set # CONFIG_CRYPTO_USER_API_HASH is not set # CONFIG_CRYPTO_USER_API_SKCIPHER is not set # CONFIG_CRYPTO_HW is not set @@ -4208,6 +4225,7 @@ CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_IOMAP=y CONFIG_GENERIC_IO=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_CRC_CCITT=y CONFIG_CRC16=y # CONFIG_CRC_T10DIF is not set @@ -4245,6 +4263,8 @@ CONFIG_HAS_DMA=y CONFIG_CHECK_SIGNATURE=y CONFIG_CPU_RMAP=y CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set CONFIG_NLATTR=y CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y CONFIG_AVERAGE=y @@ -4256,3 +4276,4 @@ CONFIG_FONT_SUPPORT=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y +CONFIG_ARCH_HAS_SG_CHAIN=y diff --git a/projects/RPi/linux/linux.arm.conf b/projects/RPi/linux/linux.arm.conf index 29e3ffbe0e..9ad60e3ae0 100644 --- a/projects/RPi/linux/linux.arm.conf +++ b/projects/RPi/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 3.16.3 Kernel Configuration +# Linux/arm 3.17.1 Kernel Configuration # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -17,9 +17,9 @@ CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_FIQ=y CONFIG_VECTORS_BASE=0xffff0000 # CONFIG_ARM_PATCH_PHYS_VIRT is not set -CONFIG_NEED_MACH_GPIO_H=y CONFIG_NEED_MACH_IO_H=y CONFIG_NEED_MACH_MEMORY_H=y +CONFIG_PHYS_OFFSET=0x0 CONFIG_GENERIC_BUG=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_IRQ_WORK=y @@ -65,7 +65,6 @@ CONFIG_HARDIRQS_SW_RESEND=y CONFIG_IRQ_DOMAIN=y # CONFIG_IRQ_DOMAIN_DEBUG is not set CONFIG_IRQ_FORCED_THREADING=y -CONFIG_KTIME_SCALAR=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -105,9 +104,11 @@ CONFIG_RCU_NOCB_CPU=y # CONFIG_RCU_NOCB_CPU_NONE is not set # CONFIG_RCU_NOCB_CPU_ZERO is not set CONFIG_RCU_NOCB_CPU_ALL=y +CONFIG_BUILD_BIN2C=y CONFIG_IKCONFIG=m CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=17 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 CONFIG_GENERIC_SCHED_CLOCK=y CONFIG_CGROUPS=y # CONFIG_CGROUP_DEBUG is not set @@ -287,7 +288,6 @@ CONFIG_ARCH_BCM2708=y # CONFIG_ARCH_IOP33X is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_KIRKWOOD is not set # CONFIG_ARCH_MV78XX0 is not set # CONFIG_ARCH_ORION5X is not set # CONFIG_ARCH_MMP is not set @@ -301,9 +301,6 @@ CONFIG_ARCH_BCM2708=y # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C24XX is not set # CONFIG_ARCH_S3C64XX is not set -# CONFIG_ARCH_S5P64X0 is not set -# CONFIG_ARCH_S5PC100 is not set -# CONFIG_ARCH_S5PV210 is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP1 is not set # CONFIG_PLAT_SPEAR is not set @@ -403,8 +400,10 @@ CONFIG_CLEANCACHE=y CONFIG_FRONTSWAP=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set -# CONFIG_ZBUD is not set +CONFIG_CMA_AREAS=7 # CONFIG_ZSWAP is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set # CONFIG_ZSMALLOC is not set CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_ALIGNMENT_TRAP=y @@ -461,7 +460,6 @@ CONFIG_ARM_BCM2835_CPUFREQ=y # CPU Idle # CONFIG_CPU_IDLE=y -# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y @@ -524,6 +522,7 @@ CONFIG_IP_MROUTE=y # CONFIG_IP_PIMSM_V1 is not set # CONFIG_IP_PIMSM_V2 is not set # CONFIG_SYN_COOKIES is not set +# CONFIG_NET_UDP_TUNNEL is not set # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set @@ -621,6 +620,7 @@ CONFIG_NETFILTER_XTABLES=m # CONFIG_NETFILTER_XT_TARGET_LED is not set # CONFIG_NETFILTER_XT_TARGET_LOG is not set # CONFIG_NETFILTER_XT_TARGET_MARK is not set +CONFIG_NETFILTER_XT_NAT=m # CONFIG_NETFILTER_XT_TARGET_NETMAP is not set # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set # CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set @@ -683,6 +683,11 @@ CONFIG_NETFILTER_XT_MATCH_STATE=m # CONFIG_NF_DEFRAG_IPV4=m CONFIG_NF_CONNTRACK_IPV4=m +# CONFIG_NF_LOG_ARP is not set +# CONFIG_NF_LOG_IPV4 is not set +CONFIG_NF_NAT_IPV4=m +# CONFIG_NF_NAT_PPTP is not set +# CONFIG_NF_NAT_H323 is not set CONFIG_IP_NF_IPTABLES=m # CONFIG_IP_NF_MATCH_AH is not set # CONFIG_IP_NF_MATCH_ECN is not set @@ -690,13 +695,10 @@ CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m # CONFIG_IP_NF_TARGET_SYNPROXY is not set -# CONFIG_IP_NF_TARGET_ULOG is not set -CONFIG_NF_NAT_IPV4=m +CONFIG_IP_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m # CONFIG_IP_NF_TARGET_NETMAP is not set # CONFIG_IP_NF_TARGET_REDIRECT is not set -# CONFIG_NF_NAT_PPTP is not set -# CONFIG_NF_NAT_H323 is not set # CONFIG_IP_NF_MANGLE is not set # CONFIG_IP_NF_RAW is not set # CONFIG_IP_NF_ARPTABLES is not set @@ -706,6 +708,8 @@ CONFIG_IP_NF_TARGET_MASQUERADE=m # CONFIG_NF_DEFRAG_IPV6=m CONFIG_NF_CONNTRACK_IPV6=m +# CONFIG_NF_LOG_IPV6 is not set +CONFIG_NF_NAT_IPV6=m CONFIG_IP6_NF_IPTABLES=m # CONFIG_IP6_NF_MATCH_AH is not set # CONFIG_IP6_NF_MATCH_EUI64 is not set @@ -720,7 +724,9 @@ CONFIG_IP6_NF_TARGET_REJECT=m # CONFIG_IP6_NF_TARGET_SYNPROXY is not set # CONFIG_IP6_NF_MANGLE is not set # CONFIG_IP6_NF_RAW is not set -# CONFIG_NF_NAT_IPV6 is not set +CONFIG_IP6_NF_NAT=m +# CONFIG_IP6_NF_TARGET_MASQUERADE is not set +# CONFIG_IP6_NF_TARGET_NPT is not set # CONFIG_BRIDGE_NF_EBTABLES is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set @@ -744,8 +750,8 @@ CONFIG_LLC=m # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_PHONET is not set +CONFIG_6LOWPAN=m # CONFIG_IEEE802154 is not set -CONFIG_6LOWPAN_IPHC=m # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set CONFIG_DNS_RESOLVER=y @@ -770,7 +776,7 @@ CONFIG_BQL=y # CONFIG_CAN is not set # CONFIG_IRDA is not set CONFIG_BT=m -CONFIG_BT_6LOWPAN=y +CONFIG_BT_6LOWPAN=m CONFIG_BT_RFCOMM=m CONFIG_BT_RFCOMM_TTY=y # CONFIG_BT_BNEP is not set @@ -806,7 +812,6 @@ CONFIG_CFG80211_WEXT=y # CONFIG_LIB80211 is not set CONFIG_MAC80211=m CONFIG_MAC80211_HAS_RC=y -# CONFIG_MAC80211_RC_PID is not set CONFIG_MAC80211_RC_MINSTREL=y CONFIG_MAC80211_RC_MINSTREL_HT=y CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y @@ -818,6 +823,7 @@ CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_DEBUG_MENU is not set # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set +# CONFIG_RFKILL_REGULATOR is not set # CONFIG_NET_9P is not set # CONFIG_CAIF is not set # CONFIG_CEPH_LIB is not set @@ -839,7 +845,7 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_EXTRA_FIRMWARE="" -# CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set @@ -848,7 +854,9 @@ CONFIG_REGMAP=y CONFIG_REGMAP_I2C=m CONFIG_REGMAP_SPI=m CONFIG_REGMAP_MMIO=m +CONFIG_REGMAP_IRQ=y CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_FENCE_TRACE is not set CONFIG_DMA_CMA=y # @@ -860,7 +868,6 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y # CONFIG_CMA_SIZE_SEL_MIN is not set # CONFIG_CMA_SIZE_SEL_MAX is not set CONFIG_CMA_ALIGNMENT=8 -CONFIG_CMA_AREAS=7 # # Bus devices @@ -935,6 +942,10 @@ CONFIG_EEPROM_93CX6=m # CONFIG_ALTERA_STAPL is not set CONFIG_BCM2708_VCHIQ=y +# +# Intel MIC Bus Driver +# + # # Intel MIC Host Driver # @@ -951,7 +962,6 @@ CONFIG_SCSI_MOD=y # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set # CONFIG_SCSI_PROC_FS is not set @@ -965,7 +975,6 @@ CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SR_VENDOR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set -CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set @@ -983,8 +992,6 @@ CONFIG_SCSI_LOWLEVEL=y CONFIG_ISCSI_TCP=y CONFIG_ISCSI_BOOT_SYSFS=y # CONFIG_SCSI_UFSHCD is not set -# CONFIG_LIBFC is not set -# CONFIG_LIBFCOE is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_DH is not set # CONFIG_SCSI_OSD_INITIATOR is not set @@ -1057,10 +1064,7 @@ CONFIG_PPP_ASYNC=m # CONFIG_PPP_SYNC_TTY is not set # CONFIG_SLIP is not set CONFIG_SLHC=y - -# -# USB Network Adapters -# +CONFIG_USB_NET_DRIVERS=y # CONFIG_USB_CATC is not set # CONFIG_USB_KAWETH is not set # CONFIG_USB_PEGASUS is not set @@ -1133,6 +1137,7 @@ CONFIG_B43_BUSES_BCMA_AND_SSB=y # CONFIG_B43_SDIO is not set CONFIG_B43_BCMA_PIO=y CONFIG_B43_PIO=y +CONFIG_B43_PHY_G=y CONFIG_B43_PHY_N=y CONFIG_B43_PHY_LP=y CONFIG_B43_PHY_HT=y @@ -1143,6 +1148,7 @@ CONFIG_B43_HWRNG=y CONFIG_BRCMUTIL=m # CONFIG_BRCMSMAC is not set CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PROTO_BCDC=y # CONFIG_BRCMFMAC_SDIO is not set CONFIG_BRCMFMAC_USB=y # CONFIG_BRCM_TRACING is not set @@ -1239,6 +1245,7 @@ CONFIG_JOYSTICK_XPAD_LEDS=y # CONFIG_INPUT_TOUCHSCREEN is not set CONFIG_INPUT_MISC=y # CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ARIZONA_HAPTICS is not set # CONFIG_INPUT_BMA150 is not set # CONFIG_INPUT_MMA8450 is not set # CONFIG_INPUT_MPU3050 is not set @@ -1318,6 +1325,10 @@ CONFIG_HW_RANDOM_BCM2708=m CONFIG_BRCM_CHAR_DRIVERS=y CONFIG_BCM_VC_CMA=y # CONFIG_BCM_VC_SM is not set + +# +# I2C support +# CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y # CONFIG_I2C_COMPAT is not set @@ -1385,6 +1396,7 @@ CONFIG_SPI_BCM2708=y # CONFIG_SPI_OC_TINY is not set # CONFIG_SPI_PL022 is not set # CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set # CONFIG_SPI_SC18IS602 is not set # CONFIG_SPI_XCOMM is not set # CONFIG_SPI_XILINX is not set @@ -1432,6 +1444,7 @@ CONFIG_GPIO_SYSFS=y # # I2C GPIO expanders: # +CONFIG_GPIO_ARIZONA=m # CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set @@ -1479,6 +1492,7 @@ CONFIG_POWER_SUPPLY=y # CONFIG_CHARGER_MAX8903 is not set # CONFIG_CHARGER_LP8727 is not set # CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_MANAGER is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24735 is not set @@ -1523,6 +1537,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_HIH6130 is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LINEAGE is not set # CONFIG_SENSORS_LTC2945 is not set # CONFIG_SENSORS_LTC4151 is not set @@ -1587,6 +1602,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_INA2XX is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set # CONFIG_SENSORS_VT1211 is not set @@ -1641,7 +1657,7 @@ CONFIG_BCMA_DRIVER_GMAC_CMN=y # # Multifunction device drivers # -CONFIG_MFD_CORE=m +CONFIG_MFD_CORE=y # CONFIG_MFD_AS3711 is not set # CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_AAT2870_CORE is not set @@ -1659,6 +1675,7 @@ CONFIG_MFD_CORE=m # CONFIG_HTC_EGPIO is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_HTC_I2CPLD is not set +# CONFIG_INTEL_SOC_PMIC is not set # CONFIG_MFD_KEMPLD is not set # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set @@ -1709,14 +1726,46 @@ CONFIG_MFD_RTSX_USB=m # CONFIG_MFD_T7L66XB is not set # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set -# CONFIG_MFD_ARIZONA_I2C is not set -# CONFIG_MFD_ARIZONA_SPI is not set +CONFIG_MFD_ARIZONA=y +CONFIG_MFD_ARIZONA_I2C=m +CONFIG_MFD_ARIZONA_SPI=m +CONFIG_MFD_WM5102=y +# CONFIG_MFD_WM5110 is not set +# CONFIG_MFD_WM8997 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X_I2C is not set # CONFIG_MFD_WM831X_SPI is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set -# CONFIG_REGULATOR is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=m +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +CONFIG_REGULATOR_ARIZONA=m +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS6524X is not set CONFIG_MEDIA_SUPPORT=m # @@ -1726,6 +1775,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_ANALOG_TV_SUPPORT=y CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y CONFIG_MEDIA_RADIO_SUPPORT=y +# CONFIG_MEDIA_SDR_SUPPORT is not set CONFIG_MEDIA_RC_SUPPORT=y # CONFIG_MEDIA_CONTROLLER is not set CONFIG_VIDEO_DEV=m @@ -1758,10 +1808,10 @@ CONFIG_IR_RC5_DECODER=m CONFIG_IR_RC6_DECODER=m CONFIG_IR_JVC_DECODER=m CONFIG_IR_SONY_DECODER=m -CONFIG_IR_RC5_SZ_DECODER=m CONFIG_IR_SANYO_DECODER=m CONFIG_IR_SHARP_DECODER=m CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_XMP_DECODER=m CONFIG_RC_DEVICES=y CONFIG_RC_ATI_REMOTE=m CONFIG_IR_IMON=m @@ -1800,12 +1850,14 @@ CONFIG_VIDEO_PVRUSB2_DVB=y CONFIG_VIDEO_STK1160_COMMON=m # CONFIG_VIDEO_STK1160_AC97 is not set CONFIG_VIDEO_STK1160=m +# CONFIG_VIDEO_GO7007 is not set # # Analog/digital TV USB devices # CONFIG_VIDEO_AU0828=m CONFIG_VIDEO_AU0828_V4L2=y +CONFIG_VIDEO_AU0828_RC=y CONFIG_VIDEO_CX231XX=m CONFIG_VIDEO_CX231XX_RC=y # CONFIG_VIDEO_CX231XX_ALSA is not set @@ -1994,6 +2046,7 @@ CONFIG_DVB_M88DS3103=m # CONFIG_DVB_DRXK=m CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_SI2165=m # # DVB-S (satellite) frontends @@ -2200,6 +2253,7 @@ CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m CONFIG_SND_BCM2708_SOC_RPI_DAC=m CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m +CONFIG_SND_BCM2708_SOC_RPI_CODEC_WSP=m # CONFIG_SND_DESIGNWARE_I2S is not set # @@ -2209,6 +2263,7 @@ CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m # # Common SoC Audio options for Freescale CPUs: # +# CONFIG_SND_SOC_FSL_ASRC is not set # CONFIG_SND_SOC_FSL_SAI is not set # CONFIG_SND_SOC_FSL_SSI is not set # CONFIG_SND_SOC_FSL_SPDIF is not set @@ -2219,6 +2274,8 @@ CONFIG_SND_SOC_I2C_AND_SPI=m # # CODEC drivers # +CONFIG_SND_SOC_ARIZONA=m +CONFIG_SND_SOC_WM_ADSP=m # CONFIG_SND_SOC_ADAU1701 is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4554 is not set @@ -2228,6 +2285,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=m # CONFIG_SND_SOC_CS42L52 is not set # CONFIG_SND_SOC_CS42L56 is not set # CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4265 is not set # CONFIG_SND_SOC_CS4270 is not set # CONFIG_SND_SOC_CS4271 is not set # CONFIG_SND_SOC_CS42XX8_I2C is not set @@ -2243,9 +2301,12 @@ CONFIG_SND_SOC_PCM5102A=m # CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set # CONFIG_SND_SOC_SPDIF is not set # CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_TAS2552 is not set # CONFIG_SND_SOC_TAS5086 is not set CONFIG_SND_SOC_TAS5713=m +# CONFIG_SND_SOC_TLV320AIC31XX is not set # CONFIG_SND_SOC_TLV320AIC3X is not set +CONFIG_SND_SOC_WM5102=m # CONFIG_SND_SOC_WM8510 is not set # CONFIG_SND_SOC_WM8523 is not set # CONFIG_SND_SOC_WM8580 is not set @@ -2296,6 +2357,7 @@ CONFIG_DRAGONRISE_FF=y # CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y # CONFIG_HID_HOLTEK is not set +# CONFIG_HID_GT683R is not set # CONFIG_HID_HUION is not set # CONFIG_HID_KEYTOUCH is not set CONFIG_HID_KYE=y @@ -2306,7 +2368,7 @@ CONFIG_HID_GYRATION=y CONFIG_HID_TWINHAN=y CONFIG_HID_KENSINGTON=y CONFIG_HID_LCPOWER=y -CONFIG_HID_LENOVO_TPKBD=y +CONFIG_HID_LENOVO=y CONFIG_HID_LOGITECH=y CONFIG_HID_LOGITECH_DJ=y CONFIG_LOGITECH_FF=y @@ -2435,6 +2497,7 @@ CONFIG_USB_UAS=y # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set # CONFIG_USB_DWC2 is not set @@ -2520,6 +2583,7 @@ CONFIG_USB_SERIAL_PL2303=m # CONFIG_USB_YUREX is not set # CONFIG_USB_EZUSB_FX2 is not set # CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set # # USB Physical Layer drivers @@ -2551,12 +2615,9 @@ CONFIG_MMC_BLOCK_BOUNCE=y # # CONFIG_MMC_ARMMMCI is not set CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_IO_ACCESSORS=y CONFIG_MMC_SDHCI_PLTFM=y # CONFIG_MMC_SDHCI_PXAV3 is not set # CONFIG_MMC_SDHCI_PXAV2 is not set -CONFIG_MMC_SDHCI_BCM2708=y -CONFIG_MMC_SDHCI_BCM2708_DMA=y CONFIG_MMC_BCM2835=y CONFIG_MMC_BCM2835_DMA=y CONFIG_MMC_BCM2835_PIO_DMA_BARRIER=2 @@ -2585,6 +2646,7 @@ CONFIG_LEDS_GPIO=y # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set # CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_REGULATOR is not set # CONFIG_LEDS_BD2802 is not set # CONFIG_LEDS_LT3593 is not set # CONFIG_LEDS_TCA6507 is not set @@ -2646,6 +2708,7 @@ CONFIG_RTC_DRV_DS1307=m # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_PCF8523 is not set # CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF85063 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set # CONFIG_RTC_DRV_BQ32K is not set @@ -2681,6 +2744,7 @@ CONFIG_RTC_DRV_DS1307=m # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set # CONFIG_RTC_DRV_M48T35 is not set @@ -2689,14 +2753,12 @@ CONFIG_RTC_DRV_DS1307=m # CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set -# CONFIG_RTC_DRV_DS2404 is not set # # on-CPU RTC drivers # # CONFIG_RTC_DRV_PL030 is not set # CONFIG_RTC_DRV_PL031 is not set -# CONFIG_RTC_DRV_MOXART is not set # CONFIG_RTC_DRV_XGENE is not set # @@ -2714,6 +2776,7 @@ CONFIG_DMADEVICES=y # CONFIG_DW_DMAC is not set # CONFIG_PL330_DMA is not set CONFIG_DMA_BCM2708=y +# CONFIG_NBPFAXI_DMA is not set CONFIG_DMA_ENGINE=y CONFIG_DMA_VIRTUAL_CHANNELS=y @@ -2735,18 +2798,13 @@ CONFIG_DMA_VIRTUAL_CHANNELS=y # Microsoft Hyper-V guest support # CONFIG_STAGING=y -# CONFIG_USBIP_CORE is not set -CONFIG_W35UND=m # CONFIG_PRISM2_USB is not set # CONFIG_COMEDI is not set # CONFIG_RTLLIB is not set CONFIG_R8712U=m # CONFIG_R8188EU is not set -# CONFIG_TRANZPORT is not set # CONFIG_LINE6_USB is not set -# CONFIG_USB_SERIAL_QUATECH2 is not set CONFIG_VT6656=m -# CONFIG_USB_ENESTORAGE is not set # CONFIG_BCM_WIMAX is not set # CONFIG_FT1000 is not set @@ -2758,12 +2816,7 @@ CONFIG_VT6656=m # CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set CONFIG_STAGING_MEDIA=y CONFIG_DVB_AS102=m -# CONFIG_VIDEO_GO7007 is not set -CONFIG_USB_MSI3101=m -CONFIG_MEDIA_TUNER_MSI001=m # CONFIG_VIDEO_TCM825X is not set -# CONFIG_USB_SN9C102 is not set -CONFIG_DVB_RTL2832_SDR=m CONFIG_LIRC_STAGING=y CONFIG_LIRC_IGORPLUGUSB=m # CONFIG_LIRC_IMON is not set @@ -2781,8 +2834,6 @@ CONFIG_LIRC_XBOX=m # CONFIG_USB_WPAN_HCD is not set # CONFIG_WIMAX_GDM72XX is not set # CONFIG_LTE_GDM724X is not set -# CONFIG_CED1401 is not set -# CONFIG_DGRP is not set # CONFIG_LUSTRE_FS is not set # CONFIG_DGAP is not set # CONFIG_GS_FPGABOOT is not set @@ -2802,6 +2853,10 @@ CONFIG_COMMON_CLK=y # # Hardware Spinlock drivers # + +# +# Clock Source drivers +# # CONFIG_SH_TIMER_CMT is not set # CONFIG_SH_TIMER_MTU2 is not set # CONFIG_SH_TIMER_TMU is not set @@ -2819,7 +2874,14 @@ CONFIG_COMMON_CLK=y # Rpmsg drivers # # CONFIG_PM_DEVFREQ is not set -# CONFIG_EXTCON is not set +CONFIG_EXTCON=m + +# +# Extcon Device Drivers +# +CONFIG_EXTCON_ARIZONA=m +# CONFIG_EXTCON_GPIO is not set +# CONFIG_EXTCON_SM5502 is not set # CONFIG_MEMORY is not set # CONFIG_IIO is not set # CONFIG_PWM is not set @@ -2832,7 +2894,6 @@ CONFIG_COMMON_CLK=y # # CONFIG_GENERIC_PHY is not set # CONFIG_BCM_KONA_USB2_PHY is not set -# CONFIG_PHY_SAMSUNG_USB2 is not set # CONFIG_POWERCAP is not set # CONFIG_MCB is not set @@ -3059,7 +3120,7 @@ CONFIG_NLS_UTF8=y # printk and dmesg options # CONFIG_PRINTK_TIME=y -CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_DYNAMIC_DEBUG is not set @@ -3115,7 +3176,6 @@ CONFIG_PANIC_TIMEOUT=0 # Lock Debugging (spinlocks, mutexes, etc...) # # CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_MUTEXES is not set # CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set @@ -3125,6 +3185,7 @@ CONFIG_PANIC_TIMEOUT=0 # CONFIG_DEBUG_ATOMIC_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_STACKTRACE is not set # CONFIG_DEBUG_KOBJECT is not set # CONFIG_DEBUG_BUGVERBOSE is not set # CONFIG_DEBUG_LIST is not set @@ -3136,7 +3197,6 @@ CONFIG_PANIC_TIMEOUT=0 # # RCU Debugging # -# CONFIG_PROVE_RCU_DELAY is not set # CONFIG_SPARSE_RCU_POINTER is not set # CONFIG_TORTURE_TEST is not set # CONFIG_RCU_TORTURE_TEST is not set @@ -3169,10 +3229,13 @@ CONFIG_TRACING_SUPPORT=y # CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_TEST_STRING_HELPERS is not set # CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_RHASHTABLE is not set # CONFIG_DMA_API_DEBUG is not set # CONFIG_TEST_MODULE is not set # CONFIG_TEST_USER_COPY is not set # CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -3310,6 +3373,7 @@ CONFIG_CRYPTO_LZO=y # Random Number Generation # # CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_DRBG_MENU is not set # CONFIG_CRYPTO_USER_API_HASH is not set # CONFIG_CRYPTO_USER_API_SKCIPHER is not set # CONFIG_CRYPTO_HW is not set @@ -3372,4 +3436,5 @@ CONFIG_FONT_SUPPORT=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y +# CONFIG_ARCH_HAS_SG_CHAIN is not set # CONFIG_VIRTUALIZATION is not set diff --git a/projects/RPi/patches/linux/linux-01-RPi_support.patch b/projects/RPi/patches/linux/linux-01-RPi_support.patch index 1172dd5a47..c6d9fff372 100644 --- a/projects/RPi/patches/linux/linux-01-RPi_support.patch +++ b/projects/RPi/patches/linux/linux-01-RPi_support.patch @@ -1,68 +1,55 @@ -From 142ed93e9354132b254ab0a3e183a0f89dbed292 Mon Sep 17 00:00:00 2001 +From 7f91d1a92bb546612ff6766f1ec75826cf483ad9 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Sun, 12 May 2013 12:24:19 +0100 -Subject: [PATCH 01/94] Main bcm2708 linux port +Subject: [PATCH 01/82] Main bcm2708 linux port Signed-off-by: popcornmix --- - arch/arm/Kconfig | 17 + - arch/arm/Kconfig.debug | 8 + - arch/arm/Makefile | 1 + - arch/arm/configs/bcmrpi_cutdown_defconfig | 474 ++++++++ - arch/arm/configs/bcmrpi_defconfig | 510 ++++++++ - arch/arm/configs/bcmrpi_emergency_defconfig | 532 +++++++++ - arch/arm/kernel/process.c | 10 + - arch/arm/mach-bcm2708/Kconfig | 34 + - arch/arm/mach-bcm2708/Makefile | 7 + - arch/arm/mach-bcm2708/Makefile.boot | 3 + - arch/arm/mach-bcm2708/armctrl.c | 208 ++++ - arch/arm/mach-bcm2708/armctrl.h | 27 + - arch/arm/mach-bcm2708/bcm2708.c | 721 +++++++++++ - arch/arm/mach-bcm2708/bcm2708.h | 49 + - arch/arm/mach-bcm2708/bcm2708_gpio.c | 361 ++++++ - arch/arm/mach-bcm2708/clock.c | 61 + - arch/arm/mach-bcm2708/clock.h | 24 + - arch/arm/mach-bcm2708/dma.c | 399 +++++++ - arch/arm/mach-bcm2708/include/mach/arm_control.h | 419 +++++++ - arch/arm/mach-bcm2708/include/mach/arm_power.h | 60 + - arch/arm/mach-bcm2708/include/mach/clkdev.h | 7 + - arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 + - arch/arm/mach-bcm2708/include/mach/dma.h | 86 ++ - arch/arm/mach-bcm2708/include/mach/entry-macro.S | 69 ++ - arch/arm/mach-bcm2708/include/mach/frc.h | 38 + - arch/arm/mach-bcm2708/include/mach/gpio.h | 17 + - arch/arm/mach-bcm2708/include/mach/hardware.h | 28 + - arch/arm/mach-bcm2708/include/mach/io.h | 27 + - arch/arm/mach-bcm2708/include/mach/irqs.h | 194 +++ - arch/arm/mach-bcm2708/include/mach/memory.h | 57 + - arch/arm/mach-bcm2708/include/mach/platform.h | 220 ++++ - arch/arm/mach-bcm2708/include/mach/power.h | 26 + - arch/arm/mach-bcm2708/include/mach/system.h | 38 + - arch/arm/mach-bcm2708/include/mach/timex.h | 23 + - arch/arm/mach-bcm2708/include/mach/uncompress.h | 84 ++ - arch/arm/mach-bcm2708/include/mach/vc_mem.h | 35 + - arch/arm/mach-bcm2708/include/mach/vcio.h | 141 +++ - arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 + - arch/arm/mach-bcm2708/power.c | 194 +++ - arch/arm/mach-bcm2708/vc_mem.c | 432 +++++++ - arch/arm/mach-bcm2708/vcio.c | 474 ++++++++ - arch/arm/mm/Kconfig | 2 +- - arch/arm/mm/proc-v6.S | 15 +- - arch/arm/tools/mach-types | 1 + - drivers/mmc/card/block.c | 2 +- - drivers/mmc/core/sd.c | 110 +- - drivers/mmc/host/Kconfig | 21 + - drivers/mmc/host/Makefile | 1 + - drivers/mmc/host/sdhci-bcm2708.c | 1394 ++++++++++++++++++++++ - drivers/mmc/host/sdhci.c | 170 ++- - drivers/mmc/host/sdhci.h | 34 + - drivers/tty/serial/amba-pl011.c | 2 +- - include/linux/mmc/host.h | 1 + - include/linux/mmc/sdhci.h | 1 + - 54 files changed, 7834 insertions(+), 77 deletions(-) - create mode 100644 arch/arm/configs/bcmrpi_cutdown_defconfig + arch/arm/Kconfig | 17 + + arch/arm/Kconfig.debug | 8 + + arch/arm/Makefile | 1 + + arch/arm/configs/bcmrpi_defconfig | 464 ++++++++++++++++ + arch/arm/kernel/process.c | 10 + + arch/arm/mach-bcm2708/Kconfig | 26 + + arch/arm/mach-bcm2708/Makefile | 6 + + arch/arm/mach-bcm2708/Makefile.boot | 3 + + arch/arm/mach-bcm2708/armctrl.c | 208 +++++++ + arch/arm/mach-bcm2708/armctrl.h | 27 + + arch/arm/mach-bcm2708/bcm2708.c | 662 +++++++++++++++++++++++ + arch/arm/mach-bcm2708/bcm2708.h | 49 ++ + arch/arm/mach-bcm2708/clock.c | 61 +++ + arch/arm/mach-bcm2708/clock.h | 24 + + arch/arm/mach-bcm2708/dma.c | 399 ++++++++++++++ + arch/arm/mach-bcm2708/include/mach/arm_control.h | 419 ++++++++++++++ + arch/arm/mach-bcm2708/include/mach/arm_power.h | 62 +++ + arch/arm/mach-bcm2708/include/mach/clkdev.h | 7 + + arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 + + arch/arm/mach-bcm2708/include/mach/dma.h | 88 +++ + arch/arm/mach-bcm2708/include/mach/entry-macro.S | 69 +++ + arch/arm/mach-bcm2708/include/mach/frc.h | 38 ++ + arch/arm/mach-bcm2708/include/mach/hardware.h | 28 + + arch/arm/mach-bcm2708/include/mach/io.h | 27 + + arch/arm/mach-bcm2708/include/mach/irqs.h | 194 +++++++ + arch/arm/mach-bcm2708/include/mach/memory.h | 57 ++ + arch/arm/mach-bcm2708/include/mach/platform.h | 228 ++++++++ + arch/arm/mach-bcm2708/include/mach/power.h | 26 + + arch/arm/mach-bcm2708/include/mach/system.h | 38 ++ + arch/arm/mach-bcm2708/include/mach/timex.h | 23 + + arch/arm/mach-bcm2708/include/mach/uncompress.h | 84 +++ + arch/arm/mach-bcm2708/include/mach/vc_mem.h | 35 ++ + arch/arm/mach-bcm2708/include/mach/vcio.h | 165 ++++++ + arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 + + arch/arm/mach-bcm2708/power.c | 194 +++++++ + arch/arm/mach-bcm2708/vc_mem.c | 432 +++++++++++++++ + arch/arm/mach-bcm2708/vcio.c | 474 ++++++++++++++++ + arch/arm/mm/Kconfig | 2 +- + arch/arm/mm/proc-v6.S | 15 +- + arch/arm/tools/mach-types | 1 + + drivers/tty/serial/amba-pl011.c | 2 +- + include/linux/mmc/host.h | 1 + + include/linux/mmc/sdhci.h | 1 + + 43 files changed, 4712 insertions(+), 5 deletions(-) create mode 100644 arch/arm/configs/bcmrpi_defconfig - create mode 100644 arch/arm/configs/bcmrpi_emergency_defconfig create mode 100644 arch/arm/mach-bcm2708/Kconfig create mode 100644 arch/arm/mach-bcm2708/Makefile create mode 100644 arch/arm/mach-bcm2708/Makefile.boot @@ -70,7 +57,6 @@ Signed-off-by: popcornmix create mode 100644 arch/arm/mach-bcm2708/armctrl.h create mode 100644 arch/arm/mach-bcm2708/bcm2708.c create mode 100644 arch/arm/mach-bcm2708/bcm2708.h - create mode 100644 arch/arm/mach-bcm2708/bcm2708_gpio.c create mode 100644 arch/arm/mach-bcm2708/clock.c create mode 100644 arch/arm/mach-bcm2708/clock.h create mode 100644 arch/arm/mach-bcm2708/dma.c @@ -81,7 +67,6 @@ Signed-off-by: popcornmix create mode 100644 arch/arm/mach-bcm2708/include/mach/dma.h create mode 100644 arch/arm/mach-bcm2708/include/mach/entry-macro.S create mode 100644 arch/arm/mach-bcm2708/include/mach/frc.h - create mode 100644 arch/arm/mach-bcm2708/include/mach/gpio.h create mode 100644 arch/arm/mach-bcm2708/include/mach/hardware.h create mode 100644 arch/arm/mach-bcm2708/include/mach/io.h create mode 100644 arch/arm/mach-bcm2708/include/mach/irqs.h @@ -97,13 +82,12 @@ Signed-off-by: popcornmix create mode 100644 arch/arm/mach-bcm2708/power.c create mode 100644 arch/arm/mach-bcm2708/vc_mem.c create mode 100644 arch/arm/mach-bcm2708/vcio.c - create mode 100644 drivers/mmc/host/sdhci-bcm2708.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index 290f02ee..bf32dc1 100644 +index 32cbbd5..aeb74cd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -374,6 +374,22 @@ config ARCH_AT91 +@@ -378,6 +378,22 @@ config ARCH_AT91 This enables support for systems based on Atmel AT91RM9200 and AT91SAM9* processors. @@ -126,7 +110,7 @@ index 290f02ee..bf32dc1 100644 config ARCH_CLPS711X bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" select ARCH_REQUIRE_GPIOLIB -@@ -1034,6 +1050,7 @@ source "arch/arm/plat-versatile/Kconfig" +@@ -964,6 +980,7 @@ source "arch/arm/plat-versatile/Kconfig" source "arch/arm/mach-vt8500/Kconfig" source "arch/arm/mach-w90x900/Kconfig" @@ -135,10 +119,10 @@ index 290f02ee..bf32dc1 100644 source "arch/arm/mach-zynq/Kconfig" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug -index 8f905950..2a4438d 100644 +index b11ad54..8160286 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug -@@ -937,6 +937,14 @@ choice +@@ -953,6 +953,14 @@ choice options; the platform specific options are deprecated and will be soon removed. @@ -154,10 +138,10 @@ index 8f905950..2a4438d 100644 config DEBUG_EXYNOS_UART diff --git a/arch/arm/Makefile b/arch/arm/Makefile -index 6721fab..08df04d 100644 +index 0ce9d0f..7c10625 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile -@@ -145,6 +145,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000 +@@ -148,6 +148,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000 machine-$(CONFIG_ARCH_AT91) += at91 machine-$(CONFIG_ARCH_AXXIA) += axxia machine-$(CONFIG_ARCH_BCM) += bcm @@ -165,500 +149,21 @@ index 6721fab..08df04d 100644 machine-$(CONFIG_ARCH_BERLIN) += berlin machine-$(CONFIG_ARCH_CLPS711X) += clps711x machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx -diff --git a/arch/arm/configs/bcmrpi_cutdown_defconfig b/arch/arm/configs/bcmrpi_cutdown_defconfig -new file mode 100644 -index 0000000..74f2dc9 ---- /dev/null -+++ b/arch/arm/configs/bcmrpi_cutdown_defconfig -@@ -0,0 +1,474 @@ -+CONFIG_EXPERIMENTAL=y -+# CONFIG_LOCALVERSION_AUTO is not set -+CONFIG_SYSVIPC=y -+CONFIG_POSIX_MQUEUE=y -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+# CONFIG_UID16 is not set -+# CONFIG_KALLSYMS is not set -+CONFIG_EMBEDDED=y -+# CONFIG_VM_EVENT_COUNTERS is not set -+# CONFIG_COMPAT_BRK is not set -+CONFIG_SLAB=y -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODVERSIONS=y -+CONFIG_MODULE_SRCVERSION_ALL=y -+# CONFIG_BLK_DEV_BSG is not set -+CONFIG_ARCH_BCM2708=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_AEABI=y -+CONFIG_ZBOOT_ROM_TEXT=0x0 -+CONFIG_ZBOOT_ROM_BSS=0x0 -+CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" -+CONFIG_CPU_IDLE=y -+CONFIG_VFP=y -+CONFIG_BINFMT_MISC=m -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_XFRM_USER=y -+CONFIG_NET_KEY=m -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_PNP_RARP=y -+CONFIG_SYN_COOKIES=y -+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -+# CONFIG_INET_XFRM_MODE_TUNNEL is not set -+# CONFIG_INET_XFRM_MODE_BEET is not set -+# CONFIG_INET_LRO is not set -+# CONFIG_INET_DIAG is not set -+# CONFIG_IPV6 is not set -+CONFIG_NET_PKTGEN=m -+CONFIG_IRDA=m -+CONFIG_IRLAN=m -+CONFIG_IRCOMM=m -+CONFIG_IRDA_ULTRA=y -+CONFIG_IRDA_CACHE_LAST_LSAP=y -+CONFIG_IRDA_FAST_RR=y -+CONFIG_IRTTY_SIR=m -+CONFIG_KINGSUN_DONGLE=m -+CONFIG_KSDAZZLE_DONGLE=m -+CONFIG_KS959_DONGLE=m -+CONFIG_USB_IRDA=m -+CONFIG_SIGMATEL_FIR=m -+CONFIG_MCS_FIR=m -+CONFIG_BT=m -+CONFIG_BT_L2CAP=y -+CONFIG_BT_SCO=y -+CONFIG_BT_RFCOMM=m -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=m -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=m -+CONFIG_BT_HCIBTUSB=m -+CONFIG_BT_HCIBCM203X=m -+CONFIG_BT_HCIBPA10X=m -+CONFIG_BT_HCIBFUSB=m -+CONFIG_BT_HCIVHCI=m -+CONFIG_BT_MRVL=m -+CONFIG_BT_MRVL_SDIO=m -+CONFIG_BT_ATH3K=m -+CONFIG_CFG80211=m -+CONFIG_MAC80211=m -+CONFIG_MAC80211_RC_PID=y -+CONFIG_MAC80211_MESH=y -+CONFIG_WIMAX=m -+CONFIG_NET_9P=m -+CONFIG_NFC=m -+CONFIG_NFC_PN533=m -+CONFIG_DEVTMPFS=y -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_CRYPTOLOOP=m -+CONFIG_BLK_DEV_NBD=m -+CONFIG_BLK_DEV_RAM=y -+CONFIG_CDROM_PKTCDVD=m -+CONFIG_MISC_DEVICES=y -+CONFIG_SCSI=y -+# CONFIG_SCSI_PROC_FS is not set -+CONFIG_BLK_DEV_SD=m -+CONFIG_BLK_DEV_SR=m -+CONFIG_SCSI_MULTI_LUN=y -+# CONFIG_SCSI_LOWLEVEL is not set -+CONFIG_NETDEVICES=y -+CONFIG_TUN=m -+CONFIG_PHYLIB=m -+CONFIG_MDIO_BITBANG=m -+CONFIG_NET_ETHERNET=y -+# CONFIG_NETDEV_1000 is not set -+# CONFIG_NETDEV_10000 is not set -+CONFIG_LIBERTAS_THINFIRM=m -+CONFIG_LIBERTAS_THINFIRM_USB=m -+CONFIG_AT76C50X_USB=m -+CONFIG_USB_ZD1201=m -+CONFIG_USB_NET_RNDIS_WLAN=m -+CONFIG_RTL8187=m -+CONFIG_MAC80211_HWSIM=m -+CONFIG_ATH_COMMON=m -+CONFIG_ATH9K=m -+CONFIG_ATH9K_HTC=m -+CONFIG_CARL9170=m -+CONFIG_B43=m -+CONFIG_B43LEGACY=m -+CONFIG_HOSTAP=m -+CONFIG_IWM=m -+CONFIG_LIBERTAS=m -+CONFIG_LIBERTAS_USB=m -+CONFIG_LIBERTAS_SDIO=m -+CONFIG_P54_COMMON=m -+CONFIG_P54_USB=m -+CONFIG_RT2X00=m -+CONFIG_RT2500USB=m -+CONFIG_RT73USB=m -+CONFIG_RT2800USB=m -+CONFIG_RT2800USB_RT53XX=y -+CONFIG_RTL8192CU=m -+CONFIG_WL1251=m -+CONFIG_WL12XX_MENU=m -+CONFIG_ZD1211RW=m -+CONFIG_MWIFIEX=m -+CONFIG_MWIFIEX_SDIO=m -+CONFIG_WIMAX_I2400M_USB=m -+CONFIG_USB_CATC=m -+CONFIG_USB_KAWETH=m -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m -+CONFIG_USB_USBNET=y -+CONFIG_USB_NET_AX8817X=m -+CONFIG_USB_NET_CDCETHER=m -+CONFIG_USB_NET_CDC_EEM=m -+CONFIG_USB_NET_DM9601=m -+CONFIG_USB_NET_SMSC75XX=m -+CONFIG_USB_NET_SMSC95XX=y -+CONFIG_USB_NET_GL620A=m -+CONFIG_USB_NET_NET1080=m -+CONFIG_USB_NET_PLUSB=m -+CONFIG_USB_NET_MCS7830=m -+CONFIG_USB_NET_CDC_SUBSET=m -+CONFIG_USB_ALI_M5632=y -+CONFIG_USB_AN2720=y -+CONFIG_USB_KC2190=y -+# CONFIG_USB_NET_ZAURUS is not set -+CONFIG_USB_NET_CX82310_ETH=m -+CONFIG_USB_NET_KALMIA=m -+CONFIG_USB_NET_INT51X1=m -+CONFIG_USB_IPHETH=m -+CONFIG_USB_SIERRA_NET=m -+CONFIG_USB_VL600=m -+CONFIG_PPP=m -+CONFIG_PPP_ASYNC=m -+CONFIG_PPP_SYNC_TTY=m -+CONFIG_PPP_DEFLATE=m -+CONFIG_PPP_BSDCOMP=m -+CONFIG_SLIP=m -+CONFIG_SLIP_COMPRESSED=y -+CONFIG_NETCONSOLE=m -+CONFIG_INPUT_POLLDEV=m -+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -+CONFIG_INPUT_JOYDEV=m -+CONFIG_INPUT_EVDEV=m -+# CONFIG_INPUT_KEYBOARD is not set -+# CONFIG_INPUT_MOUSE is not set -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_AD714X=m -+CONFIG_INPUT_ATI_REMOTE=m -+CONFIG_INPUT_ATI_REMOTE2=m -+CONFIG_INPUT_KEYSPAN_REMOTE=m -+CONFIG_INPUT_POWERMATE=m -+CONFIG_INPUT_YEALINK=m -+CONFIG_INPUT_CM109=m -+CONFIG_INPUT_UINPUT=m -+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m -+CONFIG_INPUT_ADXL34X=m -+CONFIG_INPUT_CMA3000=m -+CONFIG_SERIO=m -+CONFIG_SERIO_RAW=m -+CONFIG_GAMEPORT=m -+CONFIG_GAMEPORT_NS558=m -+CONFIG_GAMEPORT_L4=m -+CONFIG_VT_HW_CONSOLE_BINDING=y -+# CONFIG_LEGACY_PTYS is not set -+# CONFIG_DEVKMEM is not set -+CONFIG_SERIAL_AMBA_PL011=y -+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -+# CONFIG_HW_RANDOM is not set -+CONFIG_RAW_DRIVER=y -+CONFIG_GPIO_SYSFS=y -+# CONFIG_HWMON is not set -+CONFIG_WATCHDOG=y -+CONFIG_BCM2708_WDT=m -+# CONFIG_MFD_SUPPORT is not set -+CONFIG_FB=y -+CONFIG_FB_BCM2708=y -+CONFIG_FRAMEBUFFER_CONSOLE=y -+CONFIG_LOGO=y -+# CONFIG_LOGO_LINUX_MONO is not set -+# CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_HID_PID=y -+CONFIG_USB_HIDDEV=y -+CONFIG_HID_A4TECH=m -+CONFIG_HID_ACRUX=m -+CONFIG_HID_APPLE=m -+CONFIG_HID_BELKIN=m -+CONFIG_HID_CHERRY=m -+CONFIG_HID_CHICONY=m -+CONFIG_HID_CYPRESS=m -+CONFIG_HID_DRAGONRISE=m -+CONFIG_HID_EMS_FF=m -+CONFIG_HID_ELECOM=m -+CONFIG_HID_EZKEY=m -+CONFIG_HID_HOLTEK=m -+CONFIG_HID_KEYTOUCH=m -+CONFIG_HID_KYE=m -+CONFIG_HID_UCLOGIC=m -+CONFIG_HID_WALTOP=m -+CONFIG_HID_GYRATION=m -+CONFIG_HID_TWINHAN=m -+CONFIG_HID_KENSINGTON=m -+CONFIG_HID_LCPOWER=m -+CONFIG_HID_LOGITECH=m -+CONFIG_HID_MAGICMOUSE=m -+CONFIG_HID_MICROSOFT=m -+CONFIG_HID_MONTEREY=m -+CONFIG_HID_MULTITOUCH=m -+CONFIG_HID_NTRIG=m -+CONFIG_HID_ORTEK=m -+CONFIG_HID_PANTHERLORD=m -+CONFIG_HID_PETALYNX=m -+CONFIG_HID_PICOLCD=m -+CONFIG_HID_QUANTA=m -+CONFIG_HID_ROCCAT=m -+CONFIG_HID_SAMSUNG=m -+CONFIG_HID_SONY=m -+CONFIG_HID_SPEEDLINK=m -+CONFIG_HID_SUNPLUS=m -+CONFIG_HID_GREENASIA=m -+CONFIG_HID_SMARTJOYPLUS=m -+CONFIG_HID_TOPSEED=m -+CONFIG_HID_THRUSTMASTER=m -+CONFIG_HID_WACOM=m -+CONFIG_HID_WIIMOTE=m -+CONFIG_HID_ZEROPLUS=m -+CONFIG_HID_ZYDACRON=m -+CONFIG_USB=y -+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -+CONFIG_USB_MON=m -+CONFIG_USB_DWCOTG=y -+CONFIG_USB_STORAGE=y -+CONFIG_USB_STORAGE_REALTEK=m -+CONFIG_USB_STORAGE_DATAFAB=m -+CONFIG_USB_STORAGE_FREECOM=m -+CONFIG_USB_STORAGE_ISD200=m -+CONFIG_USB_STORAGE_USBAT=m -+CONFIG_USB_STORAGE_SDDR09=m -+CONFIG_USB_STORAGE_SDDR55=m -+CONFIG_USB_STORAGE_JUMPSHOT=m -+CONFIG_USB_STORAGE_ALAUDA=m -+CONFIG_USB_STORAGE_ONETOUCH=m -+CONFIG_USB_STORAGE_KARMA=m -+CONFIG_USB_STORAGE_CYPRESS_ATACB=m -+CONFIG_USB_STORAGE_ENE_UB6250=m -+CONFIG_USB_UAS=m -+CONFIG_USB_LIBUSUAL=y -+CONFIG_USB_MDC800=m -+CONFIG_USB_MICROTEK=m -+CONFIG_USB_SERIAL=m -+CONFIG_USB_SERIAL_GENERIC=y -+CONFIG_USB_SERIAL_AIRCABLE=m -+CONFIG_USB_SERIAL_ARK3116=m -+CONFIG_USB_SERIAL_BELKIN=m -+CONFIG_USB_SERIAL_CH341=m -+CONFIG_USB_SERIAL_WHITEHEAT=m -+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -+CONFIG_USB_SERIAL_CP210X=m -+CONFIG_USB_SERIAL_CYPRESS_M8=m -+CONFIG_USB_SERIAL_EMPEG=m -+CONFIG_USB_SERIAL_FTDI_SIO=m -+CONFIG_USB_SERIAL_FUNSOFT=m -+CONFIG_USB_SERIAL_VISOR=m -+CONFIG_USB_SERIAL_IPAQ=m -+CONFIG_USB_SERIAL_IR=m -+CONFIG_USB_SERIAL_EDGEPORT=m -+CONFIG_USB_SERIAL_EDGEPORT_TI=m -+CONFIG_USB_SERIAL_GARMIN=m -+CONFIG_USB_SERIAL_IPW=m -+CONFIG_USB_SERIAL_IUU=m -+CONFIG_USB_SERIAL_KEYSPAN_PDA=m -+CONFIG_USB_SERIAL_KEYSPAN=m -+CONFIG_USB_SERIAL_KLSI=m -+CONFIG_USB_SERIAL_KOBIL_SCT=m -+CONFIG_USB_SERIAL_MCT_U232=m -+CONFIG_USB_SERIAL_MOS7720=m -+CONFIG_USB_SERIAL_MOS7840=m -+CONFIG_USB_SERIAL_MOTOROLA=m -+CONFIG_USB_SERIAL_NAVMAN=m -+CONFIG_USB_SERIAL_PL2303=m -+CONFIG_USB_SERIAL_OTI6858=m -+CONFIG_USB_SERIAL_QCAUX=m -+CONFIG_USB_SERIAL_QUALCOMM=m -+CONFIG_USB_SERIAL_SPCP8X5=m -+CONFIG_USB_SERIAL_HP4X=m -+CONFIG_USB_SERIAL_SAFE=m -+CONFIG_USB_SERIAL_SIEMENS_MPI=m -+CONFIG_USB_SERIAL_SIERRAWIRELESS=m -+CONFIG_USB_SERIAL_SYMBOL=m -+CONFIG_USB_SERIAL_TI=m -+CONFIG_USB_SERIAL_CYBERJACK=m -+CONFIG_USB_SERIAL_XIRCOM=m -+CONFIG_USB_SERIAL_OPTION=m -+CONFIG_USB_SERIAL_OMNINET=m -+CONFIG_USB_SERIAL_OPTICON=m -+CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m -+CONFIG_USB_SERIAL_ZIO=m -+CONFIG_USB_SERIAL_SSU100=m -+CONFIG_USB_SERIAL_DEBUG=m -+CONFIG_USB_EMI62=m -+CONFIG_USB_EMI26=m -+CONFIG_USB_ADUTUX=m -+CONFIG_USB_SEVSEG=m -+CONFIG_USB_RIO500=m -+CONFIG_USB_LEGOTOWER=m -+CONFIG_USB_LCD=m -+CONFIG_USB_LED=m -+CONFIG_USB_CYPRESS_CY7C63=m -+CONFIG_USB_CYTHERM=m -+CONFIG_USB_IDMOUSE=m -+CONFIG_USB_FTDI_ELAN=m -+CONFIG_USB_APPLEDISPLAY=m -+CONFIG_USB_LD=m -+CONFIG_USB_TRANCEVIBRATOR=m -+CONFIG_USB_IOWARRIOR=m -+CONFIG_USB_TEST=m -+CONFIG_USB_ISIGHTFW=m -+CONFIG_USB_YUREX=m -+CONFIG_MMC=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_BCM2708=y -+CONFIG_MMC_SDHCI_BCM2708_DMA=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_TRIGGER_TIMER=m -+CONFIG_LEDS_TRIGGER_HEARTBEAT=m -+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m -+CONFIG_UIO=m -+CONFIG_UIO_PDRV=m -+CONFIG_UIO_PDRV_GENIRQ=m -+# CONFIG_IOMMU_SUPPORT is not set -+CONFIG_EXT4_FS=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_EXT4_FS_SECURITY=y -+CONFIG_REISERFS_FS=m -+CONFIG_REISERFS_FS_XATTR=y -+CONFIG_REISERFS_FS_POSIX_ACL=y -+CONFIG_REISERFS_FS_SECURITY=y -+CONFIG_JFS_FS=m -+CONFIG_JFS_POSIX_ACL=y -+CONFIG_JFS_SECURITY=y -+CONFIG_XFS_FS=m -+CONFIG_XFS_QUOTA=y -+CONFIG_XFS_POSIX_ACL=y -+CONFIG_XFS_RT=y -+CONFIG_GFS2_FS=m -+CONFIG_OCFS2_FS=m -+CONFIG_BTRFS_FS=m -+CONFIG_BTRFS_FS_POSIX_ACL=y -+CONFIG_NILFS2_FS=m -+CONFIG_AUTOFS4_FS=y -+CONFIG_FUSE_FS=m -+CONFIG_CUSE=m -+CONFIG_FSCACHE=y -+CONFIG_CACHEFILES=y -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=m -+CONFIG_MSDOS_FS=y -+CONFIG_VFAT_FS=y -+CONFIG_FAT_DEFAULT_IOCHARSET="ascii" -+CONFIG_NTFS_FS=m -+CONFIG_TMPFS=y -+CONFIG_TMPFS_POSIX_ACL=y -+CONFIG_CONFIGFS_FS=y -+CONFIG_SQUASHFS=m -+CONFIG_SQUASHFS_XATTR=y -+CONFIG_SQUASHFS_LZO=y -+CONFIG_SQUASHFS_XZ=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V3=y -+CONFIG_NFS_V3_ACL=y -+CONFIG_NFS_V4=y -+CONFIG_ROOT_NFS=y -+CONFIG_NFS_FSCACHE=y -+CONFIG_CIFS=m -+CONFIG_CIFS_WEAK_PW_HASH=y -+CONFIG_CIFS_XATTR=y -+CONFIG_CIFS_POSIX=y -+CONFIG_9P_FS=m -+CONFIG_PARTITION_ADVANCED=y -+CONFIG_MAC_PARTITION=y -+CONFIG_EFI_PARTITION=y -+CONFIG_NLS_DEFAULT="utf8" -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_CODEPAGE_737=m -+CONFIG_NLS_CODEPAGE_775=m -+CONFIG_NLS_CODEPAGE_850=m -+CONFIG_NLS_CODEPAGE_852=m -+CONFIG_NLS_CODEPAGE_855=m -+CONFIG_NLS_CODEPAGE_857=m -+CONFIG_NLS_CODEPAGE_860=m -+CONFIG_NLS_CODEPAGE_861=m -+CONFIG_NLS_CODEPAGE_862=m -+CONFIG_NLS_CODEPAGE_863=m -+CONFIG_NLS_CODEPAGE_864=m -+CONFIG_NLS_CODEPAGE_865=m -+CONFIG_NLS_CODEPAGE_866=m -+CONFIG_NLS_CODEPAGE_869=m -+CONFIG_NLS_CODEPAGE_936=m -+CONFIG_NLS_CODEPAGE_950=m -+CONFIG_NLS_CODEPAGE_932=m -+CONFIG_NLS_CODEPAGE_949=m -+CONFIG_NLS_CODEPAGE_874=m -+CONFIG_NLS_ISO8859_8=m -+CONFIG_NLS_CODEPAGE_1250=m -+CONFIG_NLS_CODEPAGE_1251=m -+CONFIG_NLS_ASCII=y -+CONFIG_NLS_ISO8859_1=m -+CONFIG_NLS_ISO8859_2=m -+CONFIG_NLS_ISO8859_3=m -+CONFIG_NLS_ISO8859_4=m -+CONFIG_NLS_ISO8859_5=m -+CONFIG_NLS_ISO8859_6=m -+CONFIG_NLS_ISO8859_7=m -+CONFIG_NLS_ISO8859_9=m -+CONFIG_NLS_ISO8859_13=m -+CONFIG_NLS_ISO8859_14=m -+CONFIG_NLS_ISO8859_15=m -+CONFIG_NLS_KOI8_R=m -+CONFIG_NLS_KOI8_U=m -+CONFIG_NLS_UTF8=m -+# CONFIG_SCHED_DEBUG is not set -+# CONFIG_DEBUG_BUGVERBOSE is not set -+# CONFIG_FTRACE is not set -+# CONFIG_ARM_UNWIND is not set -+CONFIG_CRYPTO_AUTHENC=m -+CONFIG_CRYPTO_SEQIV=m -+CONFIG_CRYPTO_CBC=y -+CONFIG_CRYPTO_HMAC=y -+CONFIG_CRYPTO_XCBC=m -+CONFIG_CRYPTO_MD5=y -+CONFIG_CRYPTO_SHA1=y -+CONFIG_CRYPTO_SHA256=m -+CONFIG_CRYPTO_SHA512=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_DES=y -+CONFIG_CRYPTO_DEFLATE=m -+# CONFIG_CRYPTO_ANSI_CPRNG is not set -+# CONFIG_CRYPTO_HW is not set -+CONFIG_CRC_ITU_T=y -+CONFIG_LIBCRC32C=y diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig new file mode 100644 -index 0000000..339aabf +index 0000000..8950e53 --- /dev/null +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -0,0 +1,510 @@ -+CONFIG_EXPERIMENTAL=y +@@ -0,0 +1,464 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y -+CONFIG_BSD_PROCESS_ACCT=y -+CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_FHANDLE=y +CONFIG_AUDIT=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_BSD_PROCESS_ACCT=y ++CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUP_FREEZER=y @@ -680,13 +185,12 @@ index 0000000..339aabf +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_BLK_DEV_THROTTLING=y ++CONFIG_PARTITION_ADVANCED=y ++CONFIG_MAC_PARTITION=y +CONFIG_CFQ_GROUP_IOSCHED=y +CONFIG_ARCH_BCM2708=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y +CONFIG_AEABI=y +CONFIG_SECCOMP=y -+CONFIG_CC_STACKPROTECTOR=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" @@ -726,8 +230,6 @@ index 0000000..339aabf +CONFIG_SIGMATEL_FIR=m +CONFIG_MCS_FIR=m +CONFIG_BT=m -+CONFIG_BT_L2CAP=y -+CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m @@ -744,7 +246,6 @@ index 0000000..339aabf +CONFIG_BT_ATH3K=m +CONFIG_CFG80211=m +CONFIG_MAC80211=m -+CONFIG_MAC80211_RC_PID=y +CONFIG_MAC80211_MESH=y +CONFIG_WIMAX=m +CONFIG_NET_9P=m @@ -756,53 +257,23 @@ index 0000000..339aabf +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_CDROM_PKTCDVD=m -+CONFIG_MISC_DEVICES=y +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=m +CONFIG_BLK_DEV_SR=m -+CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_MD=y +CONFIG_NETDEVICES=y ++CONFIG_NETCONSOLE=m +CONFIG_TUN=m -+CONFIG_PHYLIB=m +CONFIG_MDIO_BITBANG=m -+CONFIG_NET_ETHERNET=y -+# CONFIG_NETDEV_1000 is not set -+# CONFIG_NETDEV_10000 is not set -+CONFIG_LIBERTAS_THINFIRM=m -+CONFIG_LIBERTAS_THINFIRM_USB=m -+CONFIG_AT76C50X_USB=m -+CONFIG_USB_ZD1201=m -+CONFIG_USB_NET_RNDIS_WLAN=m -+CONFIG_RTL8187=m -+CONFIG_MAC80211_HWSIM=m -+CONFIG_ATH_COMMON=m -+CONFIG_ATH9K=m -+CONFIG_ATH9K_HTC=m -+CONFIG_CARL9170=m -+CONFIG_B43=m -+CONFIG_B43LEGACY=m -+CONFIG_HOSTAP=m -+CONFIG_IWM=m -+CONFIG_LIBERTAS=m -+CONFIG_LIBERTAS_USB=m -+CONFIG_LIBERTAS_SDIO=m -+CONFIG_P54_COMMON=m -+CONFIG_P54_USB=m -+CONFIG_RT2X00=m -+CONFIG_RT2500USB=m -+CONFIG_RT73USB=m -+CONFIG_RT2800USB=m -+CONFIG_RT2800USB_RT53XX=y -+CONFIG_RTL8192CU=m -+CONFIG_WL1251=m -+CONFIG_WL12XX_MENU=m -+CONFIG_ZD1211RW=m -+CONFIG_MWIFIEX=m -+CONFIG_MWIFIEX_SDIO=m -+CONFIG_WIMAX_I2400M_USB=m ++CONFIG_PPP=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m @@ -829,14 +300,31 @@ index 0000000..339aabf +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m -+CONFIG_PPP=m -+CONFIG_PPP_ASYNC=m -+CONFIG_PPP_SYNC_TTY=m -+CONFIG_PPP_DEFLATE=m -+CONFIG_PPP_BSDCOMP=m -+CONFIG_SLIP=m -+CONFIG_SLIP_COMPRESSED=y -+CONFIG_NETCONSOLE=m ++CONFIG_LIBERTAS_THINFIRM=m ++CONFIG_LIBERTAS_THINFIRM_USB=m ++CONFIG_AT76C50X_USB=m ++CONFIG_USB_ZD1201=m ++CONFIG_USB_NET_RNDIS_WLAN=m ++CONFIG_RTL8187=m ++CONFIG_MAC80211_HWSIM=m ++CONFIG_B43=m ++CONFIG_B43LEGACY=m ++CONFIG_HOSTAP=m ++CONFIG_LIBERTAS=m ++CONFIG_LIBERTAS_USB=m ++CONFIG_LIBERTAS_SDIO=m ++CONFIG_P54_COMMON=m ++CONFIG_P54_USB=m ++CONFIG_RT2X00=m ++CONFIG_RT2500USB=m ++CONFIG_RT73USB=m ++CONFIG_RT2800USB=m ++CONFIG_RT2800USB_RT53XX=y ++CONFIG_RTL8192CU=m ++CONFIG_ZD1211RW=m ++CONFIG_MWIFIEX=m ++CONFIG_MWIFIEX_SDIO=m ++CONFIG_WIMAX_I2400M_USB=m +CONFIG_INPUT_POLLDEV=m +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_JOYDEV=m @@ -845,14 +333,12 @@ index 0000000..339aabf +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m -+CONFIG_INPUT_ATI_REMOTE=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_UINPUT=m -+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_CMA3000=m +CONFIG_SERIO=m @@ -860,26 +346,19 @@ index 0000000..339aabf +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m -+CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_RAW_DRIVER=y -+CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y -+CONFIG_BCM2708_WDT=m -+# CONFIG_MFD_SUPPORT is not set +CONFIG_FB=y -+CONFIG_FB_BCM2708=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_HID_PID=y -+CONFIG_USB_HIDDEV=y +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_APPLE=m @@ -910,7 +389,6 @@ index 0000000..339aabf +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m -+CONFIG_HID_QUANTA=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m @@ -924,10 +402,11 @@ index 0000000..339aabf +CONFIG_HID_WIIMOTE=m +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m ++CONFIG_HID_PID=y ++CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_MON=m -+CONFIG_USB_DWCOTG=y +CONFIG_USB_STORAGE=y +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_DATAFAB=m @@ -943,7 +422,6 @@ index 0000000..339aabf +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m -+CONFIG_USB_LIBUSUAL=y +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USB_SERIAL=m @@ -958,7 +436,6 @@ index 0000000..339aabf +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m -+CONFIG_USB_SERIAL_FUNSOFT=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m @@ -974,16 +451,13 @@ index 0000000..339aabf +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m -+CONFIG_USB_SERIAL_MOTOROLA=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m -+CONFIG_USB_SERIAL_HP4X=m +CONFIG_USB_SERIAL_SAFE=m -+CONFIG_USB_SERIAL_SIEMENS_MPI=m +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m @@ -992,8 +466,6 @@ index 0000000..339aabf +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m -+CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m -+CONFIG_USB_SERIAL_ZIO=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_EMI62=m @@ -1018,14 +490,7 @@ index 0000000..339aabf +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_BCM2708=y -+CONFIG_MMC_SDHCI_BCM2708_DMA=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_TRIGGER_TIMER=m -+CONFIG_LEDS_TRIGGER_HEARTBEAT=m -+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +CONFIG_UIO=m -+CONFIG_UIO_PDRV=m +CONFIG_UIO_PDRV_GENIRQ=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXT4_FS=y @@ -1072,7 +537,6 @@ index 0000000..339aabf +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_NFS_FS=y -+CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y @@ -1083,9 +547,6 @@ index 0000000..339aabf +CONFIG_CIFS_POSIX=y +CONFIG_9P_FS=m +CONFIG_9P_FS_POSIX_ACL=y -+CONFIG_PARTITION_ADVANCED=y -+CONFIG_MAC_PARTITION=y -+CONFIG_EFI_PARTITION=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m @@ -1126,14 +587,13 @@ index 0000000..339aabf +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +CONFIG_PRINTK_TIME=y ++CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_DEBUG_INFO=y ++CONFIG_DEBUG_STACK_USAGE=y ++CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_TIMER_STATS=y -+CONFIG_DEBUG_STACK_USAGE=y -+CONFIG_DEBUG_INFO=y -+CONFIG_DEBUG_MEMORY_INIT=y -+CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_LATENCYTOP=y -+CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_IRQSOFF_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_STACK_TRACER=y @@ -1144,551 +604,11 @@ index 0000000..339aabf +CONFIG_KDB_KEYBOARD=y +CONFIG_STRICT_DEVMEM=y +CONFIG_CRYPTO_AUTHENC=m -+CONFIG_CRYPTO_SEQIV=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_SHA1=y -+CONFIG_CRYPTO_SHA256=m -+CONFIG_CRYPTO_SHA512=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_DES=y -+CONFIG_CRYPTO_DEFLATE=m -+# CONFIG_CRYPTO_ANSI_CPRNG is not set -+# CONFIG_CRYPTO_HW is not set -+CONFIG_CRC_ITU_T=y -+CONFIG_LIBCRC32C=y -diff --git a/arch/arm/configs/bcmrpi_emergency_defconfig b/arch/arm/configs/bcmrpi_emergency_defconfig -new file mode 100644 -index 0000000..3b40c49 ---- /dev/null -+++ b/arch/arm/configs/bcmrpi_emergency_defconfig -@@ -0,0 +1,532 @@ -+CONFIG_EXPERIMENTAL=y -+# CONFIG_LOCALVERSION_AUTO is not set -+CONFIG_SYSVIPC=y -+CONFIG_POSIX_MQUEUE=y -+CONFIG_BSD_PROCESS_ACCT=y -+CONFIG_BSD_PROCESS_ACCT_V3=y -+CONFIG_FHANDLE=y -+CONFIG_AUDIT=y -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_INITRAMFS_SOURCE="../target_fs" -+CONFIG_CGROUP_FREEZER=y -+CONFIG_CGROUP_DEVICE=y -+CONFIG_CGROUP_CPUACCT=y -+CONFIG_RESOURCE_COUNTERS=y -+CONFIG_BLK_CGROUP=y -+CONFIG_NAMESPACES=y -+CONFIG_SCHED_AUTOGROUP=y -+CONFIG_EMBEDDED=y -+# CONFIG_COMPAT_BRK is not set -+CONFIG_SLAB=y -+CONFIG_PROFILING=y -+CONFIG_OPROFILE=m -+CONFIG_KPROBES=y -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODVERSIONS=y -+CONFIG_MODULE_SRCVERSION_ALL=y -+# CONFIG_BLK_DEV_BSG is not set -+CONFIG_BLK_DEV_THROTTLING=y -+CONFIG_CFQ_GROUP_IOSCHED=y -+CONFIG_ARCH_BCM2708=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_AEABI=y -+CONFIG_SECCOMP=y -+CONFIG_CC_STACKPROTECTOR=y -+CONFIG_ZBOOT_ROM_TEXT=0x0 -+CONFIG_ZBOOT_ROM_BSS=0x0 -+CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" -+CONFIG_KEXEC=y -+CONFIG_CPU_IDLE=y -+CONFIG_VFP=y -+CONFIG_BINFMT_MISC=m -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_XFRM_USER=y -+CONFIG_NET_KEY=m -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_PNP_RARP=y -+CONFIG_SYN_COOKIES=y -+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -+# CONFIG_INET_XFRM_MODE_TUNNEL is not set -+# CONFIG_INET_XFRM_MODE_BEET is not set -+# CONFIG_INET_LRO is not set -+# CONFIG_INET_DIAG is not set -+# CONFIG_IPV6 is not set -+CONFIG_NET_PKTGEN=m -+CONFIG_IRDA=m -+CONFIG_IRLAN=m -+CONFIG_IRCOMM=m -+CONFIG_IRDA_ULTRA=y -+CONFIG_IRDA_CACHE_LAST_LSAP=y -+CONFIG_IRDA_FAST_RR=y -+CONFIG_IRTTY_SIR=m -+CONFIG_KINGSUN_DONGLE=m -+CONFIG_KSDAZZLE_DONGLE=m -+CONFIG_KS959_DONGLE=m -+CONFIG_USB_IRDA=m -+CONFIG_SIGMATEL_FIR=m -+CONFIG_MCS_FIR=m -+CONFIG_BT=m -+CONFIG_BT_L2CAP=y -+CONFIG_BT_SCO=y -+CONFIG_BT_RFCOMM=m -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=m -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=m -+CONFIG_BT_HCIBTUSB=m -+CONFIG_BT_HCIBCM203X=m -+CONFIG_BT_HCIBPA10X=m -+CONFIG_BT_HCIBFUSB=m -+CONFIG_BT_HCIVHCI=m -+CONFIG_BT_MRVL=m -+CONFIG_BT_MRVL_SDIO=m -+CONFIG_BT_ATH3K=m -+CONFIG_CFG80211=m -+CONFIG_MAC80211=m -+CONFIG_MAC80211_RC_PID=y -+CONFIG_MAC80211_MESH=y -+CONFIG_WIMAX=m -+CONFIG_NET_9P=m -+CONFIG_NFC=m -+CONFIG_NFC_PN533=m -+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_CRYPTOLOOP=m -+CONFIG_BLK_DEV_NBD=m -+CONFIG_BLK_DEV_RAM=y -+CONFIG_CDROM_PKTCDVD=m -+CONFIG_MISC_DEVICES=y -+CONFIG_SCSI=y -+# CONFIG_SCSI_PROC_FS is not set -+CONFIG_BLK_DEV_SD=y -+CONFIG_BLK_DEV_SR=m -+CONFIG_SCSI_MULTI_LUN=y -+# CONFIG_SCSI_LOWLEVEL is not set -+CONFIG_MD=y -+CONFIG_NETDEVICES=y -+CONFIG_TUN=m -+CONFIG_PHYLIB=m -+CONFIG_MDIO_BITBANG=m -+CONFIG_NET_ETHERNET=y -+# CONFIG_NETDEV_1000 is not set -+# CONFIG_NETDEV_10000 is not set -+CONFIG_LIBERTAS_THINFIRM=m -+CONFIG_LIBERTAS_THINFIRM_USB=m -+CONFIG_AT76C50X_USB=m -+CONFIG_USB_ZD1201=m -+CONFIG_USB_NET_RNDIS_WLAN=m -+CONFIG_RTL8187=m -+CONFIG_MAC80211_HWSIM=m -+CONFIG_ATH_COMMON=m -+CONFIG_ATH9K=m -+CONFIG_ATH9K_HTC=m -+CONFIG_CARL9170=m -+CONFIG_B43=m -+CONFIG_B43LEGACY=m -+CONFIG_HOSTAP=m -+CONFIG_IWM=m -+CONFIG_LIBERTAS=m -+CONFIG_LIBERTAS_USB=m -+CONFIG_LIBERTAS_SDIO=m -+CONFIG_P54_COMMON=m -+CONFIG_P54_USB=m -+CONFIG_RT2X00=m -+CONFIG_RT2500USB=m -+CONFIG_RT73USB=m -+CONFIG_RT2800USB=m -+CONFIG_RT2800USB_RT53XX=y -+CONFIG_RTL8192CU=m -+CONFIG_WL1251=m -+CONFIG_WL12XX_MENU=m -+CONFIG_ZD1211RW=m -+CONFIG_MWIFIEX=m -+CONFIG_MWIFIEX_SDIO=m -+CONFIG_WIMAX_I2400M_USB=m -+CONFIG_USB_CATC=m -+CONFIG_USB_KAWETH=m -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m -+CONFIG_USB_USBNET=y -+CONFIG_USB_NET_AX8817X=m -+CONFIG_USB_NET_CDCETHER=m -+CONFIG_USB_NET_CDC_EEM=m -+CONFIG_USB_NET_DM9601=m -+CONFIG_USB_NET_SMSC75XX=m -+CONFIG_USB_NET_SMSC95XX=y -+CONFIG_USB_NET_GL620A=m -+CONFIG_USB_NET_NET1080=m -+CONFIG_USB_NET_PLUSB=m -+CONFIG_USB_NET_MCS7830=m -+CONFIG_USB_NET_CDC_SUBSET=m -+CONFIG_USB_ALI_M5632=y -+CONFIG_USB_AN2720=y -+CONFIG_USB_KC2190=y -+# CONFIG_USB_NET_ZAURUS is not set -+CONFIG_USB_NET_CX82310_ETH=m -+CONFIG_USB_NET_KALMIA=m -+CONFIG_USB_NET_INT51X1=m -+CONFIG_USB_IPHETH=m -+CONFIG_USB_SIERRA_NET=m -+CONFIG_USB_VL600=m -+CONFIG_PPP=m -+CONFIG_PPP_ASYNC=m -+CONFIG_PPP_SYNC_TTY=m -+CONFIG_PPP_DEFLATE=m -+CONFIG_PPP_BSDCOMP=m -+CONFIG_SLIP=m -+CONFIG_SLIP_COMPRESSED=y -+CONFIG_NETCONSOLE=m -+CONFIG_INPUT_POLLDEV=m -+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -+CONFIG_INPUT_JOYDEV=m -+CONFIG_INPUT_EVDEV=m -+# CONFIG_INPUT_KEYBOARD is not set -+# CONFIG_INPUT_MOUSE is not set -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_AD714X=m -+CONFIG_INPUT_ATI_REMOTE=m -+CONFIG_INPUT_ATI_REMOTE2=m -+CONFIG_INPUT_KEYSPAN_REMOTE=m -+CONFIG_INPUT_POWERMATE=m -+CONFIG_INPUT_YEALINK=m -+CONFIG_INPUT_CM109=m -+CONFIG_INPUT_UINPUT=m -+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m -+CONFIG_INPUT_ADXL34X=m -+CONFIG_INPUT_CMA3000=m -+CONFIG_SERIO=m -+CONFIG_SERIO_RAW=m -+CONFIG_GAMEPORT=m -+CONFIG_GAMEPORT_NS558=m -+CONFIG_GAMEPORT_L4=m -+CONFIG_VT_HW_CONSOLE_BINDING=y -+# CONFIG_LEGACY_PTYS is not set -+# CONFIG_DEVKMEM is not set -+CONFIG_SERIAL_AMBA_PL011=y -+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -+# CONFIG_HW_RANDOM is not set -+CONFIG_RAW_DRIVER=y -+CONFIG_GPIO_SYSFS=y -+# CONFIG_HWMON is not set -+CONFIG_WATCHDOG=y -+CONFIG_BCM2708_WDT=m -+# CONFIG_MFD_SUPPORT is not set -+CONFIG_FB=y -+CONFIG_FB_BCM2708=y -+CONFIG_FRAMEBUFFER_CONSOLE=y -+CONFIG_LOGO=y -+# CONFIG_LOGO_LINUX_MONO is not set -+# CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_SOUND=y -+CONFIG_SND=m -+CONFIG_SND_SEQUENCER=m -+CONFIG_SND_SEQ_DUMMY=m -+CONFIG_SND_MIXER_OSS=m -+CONFIG_SND_PCM_OSS=m -+CONFIG_SND_SEQUENCER_OSS=y -+CONFIG_SND_HRTIMER=m -+CONFIG_SND_DUMMY=m -+CONFIG_SND_ALOOP=m -+CONFIG_SND_VIRMIDI=m -+CONFIG_SND_MTPAV=m -+CONFIG_SND_SERIAL_U16550=m -+CONFIG_SND_MPU401=m -+CONFIG_SND_BCM2835=m -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_USB_UA101=m -+CONFIG_SND_USB_CAIAQ=m -+CONFIG_SND_USB_6FIRE=m -+CONFIG_SOUND_PRIME=m -+CONFIG_HID_PID=y -+CONFIG_USB_HIDDEV=y -+CONFIG_HID_A4TECH=m -+CONFIG_HID_ACRUX=m -+CONFIG_HID_APPLE=m -+CONFIG_HID_BELKIN=m -+CONFIG_HID_CHERRY=m -+CONFIG_HID_CHICONY=m -+CONFIG_HID_CYPRESS=m -+CONFIG_HID_DRAGONRISE=m -+CONFIG_HID_EMS_FF=m -+CONFIG_HID_ELECOM=m -+CONFIG_HID_EZKEY=m -+CONFIG_HID_HOLTEK=m -+CONFIG_HID_KEYTOUCH=m -+CONFIG_HID_KYE=m -+CONFIG_HID_UCLOGIC=m -+CONFIG_HID_WALTOP=m -+CONFIG_HID_GYRATION=m -+CONFIG_HID_TWINHAN=m -+CONFIG_HID_KENSINGTON=m -+CONFIG_HID_LCPOWER=m -+CONFIG_HID_LOGITECH=m -+CONFIG_HID_MAGICMOUSE=m -+CONFIG_HID_MICROSOFT=m -+CONFIG_HID_MONTEREY=m -+CONFIG_HID_MULTITOUCH=m -+CONFIG_HID_NTRIG=m -+CONFIG_HID_ORTEK=m -+CONFIG_HID_PANTHERLORD=m -+CONFIG_HID_PETALYNX=m -+CONFIG_HID_PICOLCD=m -+CONFIG_HID_QUANTA=m -+CONFIG_HID_ROCCAT=m -+CONFIG_HID_SAMSUNG=m -+CONFIG_HID_SONY=m -+CONFIG_HID_SPEEDLINK=m -+CONFIG_HID_SUNPLUS=m -+CONFIG_HID_GREENASIA=m -+CONFIG_HID_SMARTJOYPLUS=m -+CONFIG_HID_TOPSEED=m -+CONFIG_HID_THRUSTMASTER=m -+CONFIG_HID_WACOM=m -+CONFIG_HID_WIIMOTE=m -+CONFIG_HID_ZEROPLUS=m -+CONFIG_HID_ZYDACRON=m -+CONFIG_USB=y -+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -+CONFIG_USB_MON=m -+CONFIG_USB_DWCOTG=y -+CONFIG_USB_STORAGE=y -+CONFIG_USB_STORAGE_REALTEK=m -+CONFIG_USB_STORAGE_DATAFAB=m -+CONFIG_USB_STORAGE_FREECOM=m -+CONFIG_USB_STORAGE_ISD200=m -+CONFIG_USB_STORAGE_USBAT=m -+CONFIG_USB_STORAGE_SDDR09=m -+CONFIG_USB_STORAGE_SDDR55=m -+CONFIG_USB_STORAGE_JUMPSHOT=m -+CONFIG_USB_STORAGE_ALAUDA=m -+CONFIG_USB_STORAGE_ONETOUCH=m -+CONFIG_USB_STORAGE_KARMA=m -+CONFIG_USB_STORAGE_CYPRESS_ATACB=m -+CONFIG_USB_STORAGE_ENE_UB6250=m -+CONFIG_USB_UAS=y -+CONFIG_USB_LIBUSUAL=y -+CONFIG_USB_MDC800=m -+CONFIG_USB_MICROTEK=m -+CONFIG_USB_SERIAL=m -+CONFIG_USB_SERIAL_GENERIC=y -+CONFIG_USB_SERIAL_AIRCABLE=m -+CONFIG_USB_SERIAL_ARK3116=m -+CONFIG_USB_SERIAL_BELKIN=m -+CONFIG_USB_SERIAL_CH341=m -+CONFIG_USB_SERIAL_WHITEHEAT=m -+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -+CONFIG_USB_SERIAL_CP210X=m -+CONFIG_USB_SERIAL_CYPRESS_M8=m -+CONFIG_USB_SERIAL_EMPEG=m -+CONFIG_USB_SERIAL_FTDI_SIO=m -+CONFIG_USB_SERIAL_FUNSOFT=m -+CONFIG_USB_SERIAL_VISOR=m -+CONFIG_USB_SERIAL_IPAQ=m -+CONFIG_USB_SERIAL_IR=m -+CONFIG_USB_SERIAL_EDGEPORT=m -+CONFIG_USB_SERIAL_EDGEPORT_TI=m -+CONFIG_USB_SERIAL_GARMIN=m -+CONFIG_USB_SERIAL_IPW=m -+CONFIG_USB_SERIAL_IUU=m -+CONFIG_USB_SERIAL_KEYSPAN_PDA=m -+CONFIG_USB_SERIAL_KEYSPAN=m -+CONFIG_USB_SERIAL_KLSI=m -+CONFIG_USB_SERIAL_KOBIL_SCT=m -+CONFIG_USB_SERIAL_MCT_U232=m -+CONFIG_USB_SERIAL_MOS7720=m -+CONFIG_USB_SERIAL_MOS7840=m -+CONFIG_USB_SERIAL_MOTOROLA=m -+CONFIG_USB_SERIAL_NAVMAN=m -+CONFIG_USB_SERIAL_PL2303=m -+CONFIG_USB_SERIAL_OTI6858=m -+CONFIG_USB_SERIAL_QCAUX=m -+CONFIG_USB_SERIAL_QUALCOMM=m -+CONFIG_USB_SERIAL_SPCP8X5=m -+CONFIG_USB_SERIAL_HP4X=m -+CONFIG_USB_SERIAL_SAFE=m -+CONFIG_USB_SERIAL_SIEMENS_MPI=m -+CONFIG_USB_SERIAL_SIERRAWIRELESS=m -+CONFIG_USB_SERIAL_SYMBOL=m -+CONFIG_USB_SERIAL_TI=m -+CONFIG_USB_SERIAL_CYBERJACK=m -+CONFIG_USB_SERIAL_XIRCOM=m -+CONFIG_USB_SERIAL_OPTION=m -+CONFIG_USB_SERIAL_OMNINET=m -+CONFIG_USB_SERIAL_OPTICON=m -+CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m -+CONFIG_USB_SERIAL_ZIO=m -+CONFIG_USB_SERIAL_SSU100=m -+CONFIG_USB_SERIAL_DEBUG=m -+CONFIG_USB_EMI62=m -+CONFIG_USB_EMI26=m -+CONFIG_USB_ADUTUX=m -+CONFIG_USB_SEVSEG=m -+CONFIG_USB_RIO500=m -+CONFIG_USB_LEGOTOWER=m -+CONFIG_USB_LCD=m -+CONFIG_USB_LED=m -+CONFIG_USB_CYPRESS_CY7C63=m -+CONFIG_USB_CYTHERM=m -+CONFIG_USB_IDMOUSE=m -+CONFIG_USB_FTDI_ELAN=m -+CONFIG_USB_APPLEDISPLAY=m -+CONFIG_USB_LD=m -+CONFIG_USB_TRANCEVIBRATOR=m -+CONFIG_USB_IOWARRIOR=m -+CONFIG_USB_TEST=m -+CONFIG_USB_ISIGHTFW=m -+CONFIG_USB_YUREX=m -+CONFIG_MMC=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_BCM2708=y -+CONFIG_MMC_SDHCI_BCM2708_DMA=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_TRIGGER_TIMER=m -+CONFIG_LEDS_TRIGGER_HEARTBEAT=m -+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m -+CONFIG_UIO=m -+CONFIG_UIO_PDRV=m -+CONFIG_UIO_PDRV_GENIRQ=m -+# CONFIG_IOMMU_SUPPORT is not set -+CONFIG_EXT4_FS=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_EXT4_FS_SECURITY=y -+CONFIG_REISERFS_FS=m -+CONFIG_REISERFS_FS_XATTR=y -+CONFIG_REISERFS_FS_POSIX_ACL=y -+CONFIG_REISERFS_FS_SECURITY=y -+CONFIG_JFS_FS=m -+CONFIG_JFS_POSIX_ACL=y -+CONFIG_JFS_SECURITY=y -+CONFIG_JFS_STATISTICS=y -+CONFIG_XFS_FS=m -+CONFIG_XFS_QUOTA=y -+CONFIG_XFS_POSIX_ACL=y -+CONFIG_XFS_RT=y -+CONFIG_GFS2_FS=m -+CONFIG_OCFS2_FS=m -+CONFIG_BTRFS_FS=m -+CONFIG_BTRFS_FS_POSIX_ACL=y -+CONFIG_NILFS2_FS=m -+CONFIG_FANOTIFY=y -+CONFIG_AUTOFS4_FS=y -+CONFIG_FUSE_FS=m -+CONFIG_CUSE=m -+CONFIG_FSCACHE=y -+CONFIG_FSCACHE_STATS=y -+CONFIG_FSCACHE_HISTOGRAM=y -+CONFIG_CACHEFILES=y -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=m -+CONFIG_MSDOS_FS=y -+CONFIG_VFAT_FS=y -+CONFIG_FAT_DEFAULT_IOCHARSET="ascii" -+CONFIG_NTFS_FS=m -+CONFIG_TMPFS=y -+CONFIG_TMPFS_POSIX_ACL=y -+CONFIG_CONFIGFS_FS=y -+CONFIG_SQUASHFS=m -+CONFIG_SQUASHFS_XATTR=y -+CONFIG_SQUASHFS_LZO=y -+CONFIG_SQUASHFS_XZ=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V3=y -+CONFIG_NFS_V3_ACL=y -+CONFIG_NFS_V4=y -+CONFIG_ROOT_NFS=y -+CONFIG_NFS_FSCACHE=y -+CONFIG_CIFS=m -+CONFIG_CIFS_WEAK_PW_HASH=y -+CONFIG_CIFS_XATTR=y -+CONFIG_CIFS_POSIX=y -+CONFIG_9P_FS=m -+CONFIG_9P_FS_POSIX_ACL=y -+CONFIG_PARTITION_ADVANCED=y -+CONFIG_MAC_PARTITION=y -+CONFIG_EFI_PARTITION=y -+CONFIG_NLS_DEFAULT="utf8" -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_CODEPAGE_737=m -+CONFIG_NLS_CODEPAGE_775=m -+CONFIG_NLS_CODEPAGE_850=m -+CONFIG_NLS_CODEPAGE_852=m -+CONFIG_NLS_CODEPAGE_855=m -+CONFIG_NLS_CODEPAGE_857=m -+CONFIG_NLS_CODEPAGE_860=m -+CONFIG_NLS_CODEPAGE_861=m -+CONFIG_NLS_CODEPAGE_862=m -+CONFIG_NLS_CODEPAGE_863=m -+CONFIG_NLS_CODEPAGE_864=m -+CONFIG_NLS_CODEPAGE_865=m -+CONFIG_NLS_CODEPAGE_866=m -+CONFIG_NLS_CODEPAGE_869=m -+CONFIG_NLS_CODEPAGE_936=m -+CONFIG_NLS_CODEPAGE_950=m -+CONFIG_NLS_CODEPAGE_932=m -+CONFIG_NLS_CODEPAGE_949=m -+CONFIG_NLS_CODEPAGE_874=m -+CONFIG_NLS_ISO8859_8=m -+CONFIG_NLS_CODEPAGE_1250=m -+CONFIG_NLS_CODEPAGE_1251=m -+CONFIG_NLS_ASCII=y -+CONFIG_NLS_ISO8859_1=m -+CONFIG_NLS_ISO8859_2=m -+CONFIG_NLS_ISO8859_3=m -+CONFIG_NLS_ISO8859_4=m -+CONFIG_NLS_ISO8859_5=m -+CONFIG_NLS_ISO8859_6=m -+CONFIG_NLS_ISO8859_7=m -+CONFIG_NLS_ISO8859_9=m -+CONFIG_NLS_ISO8859_13=m -+CONFIG_NLS_ISO8859_14=m -+CONFIG_NLS_ISO8859_15=m -+CONFIG_NLS_KOI8_R=m -+CONFIG_NLS_KOI8_U=m -+CONFIG_NLS_UTF8=m -+CONFIG_PRINTK_TIME=y -+CONFIG_DETECT_HUNG_TASK=y -+CONFIG_TIMER_STATS=y -+CONFIG_DEBUG_STACK_USAGE=y -+CONFIG_DEBUG_INFO=y -+CONFIG_DEBUG_MEMORY_INIT=y -+CONFIG_BOOT_PRINTK_DELAY=y -+CONFIG_LATENCYTOP=y -+CONFIG_SYSCTL_SYSCALL_CHECK=y -+CONFIG_IRQSOFF_TRACER=y -+CONFIG_SCHED_TRACER=y -+CONFIG_STACK_TRACER=y -+CONFIG_BLK_DEV_IO_TRACE=y -+CONFIG_FUNCTION_PROFILER=y -+CONFIG_KGDB=y -+CONFIG_KGDB_KDB=y -+CONFIG_KDB_KEYBOARD=y -+CONFIG_STRICT_DEVMEM=y -+CONFIG_CRYPTO_AUTHENC=m -+CONFIG_CRYPTO_SEQIV=m -+CONFIG_CRYPTO_CBC=y -+CONFIG_CRYPTO_HMAC=y -+CONFIG_CRYPTO_XCBC=m -+CONFIG_CRYPTO_MD5=y -+CONFIG_CRYPTO_SHA1=y -+CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m @@ -1700,7 +620,7 @@ index 0000000..3b40c49 +CONFIG_CRC_ITU_T=y +CONFIG_LIBCRC32C=y diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c -index 81ef686..c5ed46f 100644 +index a35f6eb..ee0ef19 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -171,6 +171,16 @@ void arch_cpu_idle_dead(void) @@ -1722,10 +642,10 @@ index 81ef686..c5ed46f 100644 * diff --git a/arch/arm/mach-bcm2708/Kconfig b/arch/arm/mach-bcm2708/Kconfig new file mode 100644 -index 0000000..9355841 +index 0000000..1f11478 --- /dev/null +++ b/arch/arm/mach-bcm2708/Kconfig -@@ -0,0 +1,34 @@ +@@ -0,0 +1,26 @@ +menu "Broadcom BCM2708 Implementations" + depends on ARCH_BCM2708 + @@ -1737,14 +657,6 @@ index 0000000..9355841 + help + Include support for the Broadcom(R) BCM2708 platform. + -+config BCM2708_GPIO -+ bool "BCM2708 gpio support" -+ depends on MACH_BCM2708 -+ select ARCH_REQUIRE_GPIOLIB -+ default y -+ help -+ Include support for the Broadcom(R) BCM2708 gpio. -+ +config BCM2708_VCMEM + bool "Videocore Memory" + depends on MACH_BCM2708 @@ -1762,16 +674,15 @@ index 0000000..9355841 +endmenu diff --git a/arch/arm/mach-bcm2708/Makefile b/arch/arm/mach-bcm2708/Makefile new file mode 100644 -index 0000000..a722f3f +index 0000000..c76f39bc --- /dev/null +++ b/arch/arm/mach-bcm2708/Makefile -@@ -0,0 +1,7 @@ +@@ -0,0 +1,6 @@ +# +# Makefile for the linux kernel. +# + +obj-$(CONFIG_MACH_BCM2708) += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o -+obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o +obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o diff --git a/arch/arm/mach-bcm2708/Makefile.boot b/arch/arm/mach-bcm2708/Makefile.boot new file mode 100644 @@ -2031,10 +942,10 @@ index 0000000..0aa916e +#endif diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c new file mode 100644 -index 0000000..632023a +index 0000000..9b4e709 --- /dev/null +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -0,0 +1,721 @@ +@@ -0,0 +1,662 @@ +/* + * linux/arch/arm/mach-bcm2708/bcm2708.c + * @@ -2368,31 +1279,6 @@ index 0000000..632023a + }, +}; + -+#ifdef CONFIG_BCM2708_GPIO -+#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" -+ -+static struct resource bcm2708_gpio_resources[] = { -+ [0] = { /* general purpose I/O */ -+ .start = GPIO_BASE, -+ .end = GPIO_BASE + SZ_4K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); -+ -+static struct platform_device bcm2708_gpio_device = { -+ .name = BCM_GPIO_DRIVER_NAME, -+ .id = -1, /* only one VideoCore I/O area */ -+ .resource = bcm2708_gpio_resources, -+ .num_resources = ARRAY_SIZE(bcm2708_gpio_resources), -+ .dev = { -+ .dma_mask = &gpio_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), -+ }, -+}; -+#endif -+ +static struct resource bcm2708_systemtimer_resources[] = { + [0] = { /* system timer access */ + .start = ST_BASE, @@ -2420,34 +1306,6 @@ index 0000000..632023a + }, +}; + -+#ifdef CONFIG_MMC_SDHCI_BCM2708 /* Arasan emmc SD */ -+static struct resource bcm2708_emmc_resources[] = { -+ [0] = { -+ .start = EMMC_BASE, -+ .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */ -+ /* the memory map actually makes SZ_4K available */ -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = IRQ_ARASANSDIO, -+ .end = IRQ_ARASANSDIO, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static u64 bcm2708_emmc_dmamask = 0xffffffffUL; -+ -+struct platform_device bcm2708_emmc_device = { -+ .name = "bcm2708_sdhci", -+ .id = 0, -+ .num_resources = ARRAY_SIZE(bcm2708_emmc_resources), -+ .resource = bcm2708_emmc_resources, -+ .dev = { -+ .dma_mask = &bcm2708_emmc_dmamask, -+ .coherent_dma_mask = 0xffffffffUL}, -+}; -+#endif /* CONFIG_MMC_SDHCI_BCM2708 */ -+ +static struct resource bcm2708_powerman_resources[] = { + [0] = { + .start = PM_BASE, @@ -2563,18 +1421,12 @@ index 0000000..632023a + + bcm_register_device(&bcm2708_dmaman_device); + bcm_register_device(&bcm2708_vcio_device); -+#ifdef CONFIG_BCM2708_GPIO -+ bcm_register_device(&bcm2708_gpio_device); -+#endif + bcm_register_device(&bcm2708_systemtimer_device); + bcm_register_device(&bcm2708_fb_device); + bcm_register_device(&bcm2708_usb_device); + bcm_register_device(&bcm2708_uart1_device); + bcm_register_device(&bcm2708_powerman_device); + -+#ifdef CONFIG_MMC_SDHCI_BCM2708 -+ bcm_register_device(&bcm2708_emmc_device); -+#endif + bcm2708_init_led(); + + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { @@ -2811,373 +1663,6 @@ index 0000000..e339a93 +} + +#endif -diff --git a/arch/arm/mach-bcm2708/bcm2708_gpio.c b/arch/arm/mach-bcm2708/bcm2708_gpio.c -new file mode 100644 -index 0000000..120929ff ---- /dev/null -+++ b/arch/arm/mach-bcm2708/bcm2708_gpio.c -@@ -0,0 +1,361 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" -+#define DRIVER_NAME BCM_GPIO_DRIVER_NAME -+#define BCM_GPIO_USE_IRQ 1 -+ -+#define GPIOFSEL(x) (0x00+(x)*4) -+#define GPIOSET(x) (0x1c+(x)*4) -+#define GPIOCLR(x) (0x28+(x)*4) -+#define GPIOLEV(x) (0x34+(x)*4) -+#define GPIOEDS(x) (0x40+(x)*4) -+#define GPIOREN(x) (0x4c+(x)*4) -+#define GPIOFEN(x) (0x58+(x)*4) -+#define GPIOHEN(x) (0x64+(x)*4) -+#define GPIOLEN(x) (0x70+(x)*4) -+#define GPIOAREN(x) (0x7c+(x)*4) -+#define GPIOAFEN(x) (0x88+(x)*4) -+#define GPIOUD(x) (0x94+(x)*4) -+#define GPIOUDCLK(x) (0x98+(x)*4) -+ -+enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT, -+ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4, -+ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1, -+ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3, -+}; -+ -+ /* Each of the two spinlocks protects a different set of hardware -+ * regiters and data structurs. This decouples the code of the IRQ from -+ * the GPIO code. This also makes the case of a GPIO routine call from -+ * the IRQ code simpler. -+ */ -+static DEFINE_SPINLOCK(lock); /* GPIO registers */ -+ -+struct bcm2708_gpio { -+ struct list_head list; -+ void __iomem *base; -+ struct gpio_chip gc; -+ unsigned long rising; -+ unsigned long falling; -+ unsigned long high; -+ unsigned long low; -+}; -+ -+static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset, -+ int function) -+{ -+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); -+ unsigned long flags; -+ unsigned gpiodir; -+ unsigned gpio_bank = offset / 10; -+ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; -+ -+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function); -+ if (offset >= BCM2708_NR_GPIOS) -+ return -EINVAL; -+ -+ spin_lock_irqsave(&lock, flags); -+ -+ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); -+ gpiodir &= ~(7 << gpio_field_offset); -+ gpiodir |= function << gpio_field_offset; -+ writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank)); -+ spin_unlock_irqrestore(&lock, flags); -+ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); -+ -+ return 0; -+} -+ -+static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset) -+{ -+ return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT); -+} -+ -+static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value); -+static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset, -+ int value) -+{ -+ int ret; -+ ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT); -+ if (ret >= 0) -+ bcm2708_gpio_set(gc, offset, value); -+ return ret; -+} -+ -+static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset) -+{ -+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); -+ unsigned gpio_bank = offset / 32; -+ unsigned gpio_field_offset = (offset - 32 * gpio_bank); -+ unsigned lev; -+ -+ if (offset >= BCM2708_NR_GPIOS) -+ return 0; -+ lev = readl(gpio->base + GPIOLEV(gpio_bank)); -+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset)); -+ return 0x1 & (lev >> gpio_field_offset); -+} -+ -+static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value) -+{ -+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); -+ unsigned gpio_bank = offset / 32; -+ unsigned gpio_field_offset = (offset - 32 * gpio_bank); -+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value); -+ if (offset >= BCM2708_NR_GPIOS) -+ return; -+ if (value) -+ writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank)); -+ else -+ writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank)); -+} -+ -+/************************************************************************************************************************* -+ * bcm2708 GPIO IRQ -+ */ -+ -+#if BCM_GPIO_USE_IRQ -+ -+static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) -+{ -+ return gpio_to_irq(gpio); -+} -+ -+static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type) -+{ -+ unsigned irq = d->irq; -+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); -+ -+ gpio->rising &= ~(1 << irq_to_gpio(irq)); -+ gpio->falling &= ~(1 << irq_to_gpio(irq)); -+ gpio->high &= ~(1 << irq_to_gpio(irq)); -+ gpio->low &= ~(1 << irq_to_gpio(irq)); -+ -+ if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) -+ return -EINVAL; -+ -+ if (type & IRQ_TYPE_EDGE_RISING) -+ gpio->rising |= (1 << irq_to_gpio(irq)); -+ if (type & IRQ_TYPE_EDGE_FALLING) -+ gpio->falling |= (1 << irq_to_gpio(irq)); -+ if (type & IRQ_TYPE_LEVEL_HIGH) -+ gpio->high |= (1 << irq_to_gpio(irq)); -+ if (type & IRQ_TYPE_LEVEL_LOW) -+ gpio->low |= (1 << irq_to_gpio(irq)); -+ return 0; -+} -+ -+static void bcm2708_gpio_irq_mask(struct irq_data *d) -+{ -+ unsigned irq = d->irq; -+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); -+ unsigned gn = irq_to_gpio(irq); -+ unsigned gb = gn / 32; -+ unsigned long rising = readl(gpio->base + GPIOREN(gb)); -+ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); -+ unsigned long high = readl(gpio->base + GPIOHEN(gb)); -+ unsigned long low = readl(gpio->base + GPIOLEN(gb)); -+ -+ gn = gn % 32; -+ -+ writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb)); -+ writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb)); -+ writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb)); -+ writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb)); -+} -+ -+static void bcm2708_gpio_irq_unmask(struct irq_data *d) -+{ -+ unsigned irq = d->irq; -+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); -+ unsigned gn = irq_to_gpio(irq); -+ unsigned gb = gn / 32; -+ unsigned long rising = readl(gpio->base + GPIOREN(gb)); -+ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); -+ unsigned long high = readl(gpio->base + GPIOHEN(gb)); -+ unsigned long low = readl(gpio->base + GPIOLEN(gb)); -+ -+ gn = gn % 32; -+ -+ writel(1 << gn, gpio->base + GPIOEDS(gb)); -+ -+ if (gpio->rising & (1 << gn)) { -+ writel(rising | (1 << gn), gpio->base + GPIOREN(gb)); -+ } else { -+ writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb)); -+ } -+ -+ if (gpio->falling & (1 << gn)) { -+ writel(falling | (1 << gn), gpio->base + GPIOFEN(gb)); -+ } else { -+ writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb)); -+ } -+ -+ if (gpio->high & (1 << gn)) { -+ writel(high | (1 << gn), gpio->base + GPIOHEN(gb)); -+ } else { -+ writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb)); -+ } -+ -+ if (gpio->low & (1 << gn)) { -+ writel(low | (1 << gn), gpio->base + GPIOLEN(gb)); -+ } else { -+ writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb)); -+ } -+} -+ -+static struct irq_chip bcm2708_irqchip = { -+ .name = "GPIO", -+ .irq_enable = bcm2708_gpio_irq_unmask, -+ .irq_disable = bcm2708_gpio_irq_mask, -+ .irq_unmask = bcm2708_gpio_irq_unmask, -+ .irq_mask = bcm2708_gpio_irq_mask, -+ .irq_set_type = bcm2708_gpio_irq_set_type, -+}; -+ -+static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id) -+{ -+ unsigned long edsr; -+ unsigned bank; -+ int i; -+ unsigned gpio; -+ for (bank = 0; bank <= 1; bank++) { -+ edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank)); -+ for_each_set_bit(i, &edsr, 32) { -+ gpio = i + bank * 32; -+ generic_handle_irq(gpio_to_irq(gpio)); -+ } -+ writel(0xffffffff, __io_address(GPIO_BASE) + GPIOEDS(bank)); -+ } -+ return IRQ_HANDLED; -+} -+ -+static struct irqaction bcm2708_gpio_irq = { -+ .name = "BCM2708 GPIO catchall handler", -+ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, -+ .handler = bcm2708_gpio_interrupt, -+}; -+ -+static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb) -+{ -+ unsigned irq; -+ -+ ucb->gc.to_irq = bcm2708_gpio_to_irq; -+ -+ for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) { -+ irq_set_chip_data(irq, ucb); -+ irq_set_chip(irq, &bcm2708_irqchip); -+ set_irq_flags(irq, IRQF_VALID); -+ } -+ setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq); -+} -+ -+#else -+ -+static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb) -+{ -+} -+ -+#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */ -+ -+static int bcm2708_gpio_probe(struct platform_device *dev) -+{ -+ struct bcm2708_gpio *ucb; -+ struct resource *res; -+ int err = 0; -+ -+ printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev); -+ -+ ucb = kzalloc(sizeof(*ucb), GFP_KERNEL); -+ if (NULL == ucb) { -+ printk(KERN_ERR DRIVER_NAME ": failed to allocate " -+ "mailbox memory\n"); -+ err = -ENOMEM; -+ goto err; -+ } -+ -+ res = platform_get_resource(dev, IORESOURCE_MEM, 0); -+ -+ platform_set_drvdata(dev, ucb); -+ ucb->base = __io_address(GPIO_BASE); -+ -+ ucb->gc.label = "bcm2708_gpio"; -+ ucb->gc.base = 0; -+ ucb->gc.ngpio = BCM2708_NR_GPIOS; -+ ucb->gc.owner = THIS_MODULE; -+ -+ ucb->gc.direction_input = bcm2708_gpio_dir_in; -+ ucb->gc.direction_output = bcm2708_gpio_dir_out; -+ ucb->gc.get = bcm2708_gpio_get; -+ ucb->gc.set = bcm2708_gpio_set; -+ ucb->gc.can_sleep = 0; -+ -+ bcm2708_gpio_irq_init(ucb); -+ -+ err = gpiochip_add(&ucb->gc); -+ if (err) -+ goto err; -+ -+err: -+ return err; -+ -+} -+ -+static int bcm2708_gpio_remove(struct platform_device *dev) -+{ -+ int err = 0; -+ struct bcm2708_gpio *ucb = platform_get_drvdata(dev); -+ -+ printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev); -+ -+ err = gpiochip_remove(&ucb->gc); -+ -+ platform_set_drvdata(dev, NULL); -+ kfree(ucb); -+ -+ return err; -+} -+ -+static struct platform_driver bcm2708_gpio_driver = { -+ .probe = bcm2708_gpio_probe, -+ .remove = bcm2708_gpio_remove, -+ .driver = { -+ .name = "bcm2708_gpio"}, -+}; -+ -+static int __init bcm2708_gpio_init(void) -+{ -+ return platform_driver_register(&bcm2708_gpio_driver); -+} -+ -+static void __exit bcm2708_gpio_exit(void) -+{ -+ platform_driver_unregister(&bcm2708_gpio_driver); -+} -+ -+module_init(bcm2708_gpio_init); -+module_exit(bcm2708_gpio_exit); -+ -+MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver"); -+MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-bcm2708/clock.c b/arch/arm/mach-bcm2708/clock.c new file mode 100644 index 0000000..4fc556e @@ -4107,10 +2592,10 @@ index 0000000..a82bb92 +#endif diff --git a/arch/arm/mach-bcm2708/include/mach/arm_power.h b/arch/arm/mach-bcm2708/include/mach/arm_power.h new file mode 100644 -index 0000000..aae9136 +index 0000000..d3bf245 --- /dev/null +++ b/arch/arm/mach-bcm2708/include/mach/arm_power.h -@@ -0,0 +1,60 @@ +@@ -0,0 +1,62 @@ +/* + * linux/arch/arm/mach-bcm2708/include/mach/arm_power.h + * @@ -4151,6 +2636,7 @@ index 0000000..aae9136 + PREFIX(POWER_I2C2_BIT), + PREFIX(POWER_SPI_BIT), + PREFIX(POWER_CCP2TX_BIT), ++ PREFIX(POWER_DSI_BIT), + + PREFIX(POWER_MAX) +}; @@ -4165,6 +2651,7 @@ index 0000000..aae9136 + PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)), + PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)), + PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)), ++ PREFIX(POWER_DSI) = (1 << PREFIX(POWER_DSI_BIT)), + + PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1, + PREFIX(POWER_NONE) = 0 @@ -4214,10 +2701,10 @@ index 0000000..b24304a +#include diff --git a/arch/arm/mach-bcm2708/include/mach/dma.h b/arch/arm/mach-bcm2708/include/mach/dma.h new file mode 100644 -index 0000000..ac7a4a0 +index 0000000..f2568d4 --- /dev/null +++ b/arch/arm/mach-bcm2708/include/mach/dma.h -@@ -0,0 +1,86 @@ +@@ -0,0 +1,88 @@ +/* + * linux/arch/arm/mach-bcm2708/include/mach/dma.h + * @@ -4265,6 +2752,8 @@ index 0000000..ac7a4a0 +#define BCM2708_DMA_ADDR 0x04 +/* the current control block appears in the following registers - read only */ +#define BCM2708_DMA_INFO 0x08 ++#define BCM2708_DMA_SOURCE_AD 0x0c ++#define BCM2708_DMA_DEST_AD 0x10 +#define BCM2708_DMA_NEXTCB 0x1C +#define BCM2708_DMA_DEBUG 0x20 + @@ -4423,29 +2912,6 @@ index 0000000..dd51e07 +extern unsigned long long frc_clock_ticks63(void); + +#endif -diff --git a/arch/arm/mach-bcm2708/include/mach/gpio.h b/arch/arm/mach-bcm2708/include/mach/gpio.h -new file mode 100644 -index 0000000..7965a97 ---- /dev/null -+++ b/arch/arm/mach-bcm2708/include/mach/gpio.h -@@ -0,0 +1,17 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/gpio.h -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ASM_ARCH_GPIO_H -+#define __ASM_ARCH_GPIO_H -+ -+#define BCM2708_NR_GPIOS 54 // number of gpio lines -+ -+#define gpio_to_irq(x) ((x) + GPIO_IRQ_START) -+#define irq_to_gpio(x) ((x) - GPIO_IRQ_START) -+ -+#endif diff --git a/arch/arm/mach-bcm2708/include/mach/hardware.h b/arch/arm/mach-bcm2708/include/mach/hardware.h new file mode 100644 index 0000000..c2954e8 @@ -4715,7 +3181,7 @@ index 0000000..faf5d1a +#endif /* _BCM2708_IRQS_H_ */ diff --git a/arch/arm/mach-bcm2708/include/mach/memory.h b/arch/arm/mach-bcm2708/include/mach/memory.h new file mode 100644 -index 0000000..521540d +index 0000000..7548a52 --- /dev/null +++ b/arch/arm/mach-bcm2708/include/mach/memory.h @@ -0,0 +1,57 @@ @@ -4753,7 +3219,7 @@ index 0000000..521540d +/* + * Physical DRAM offset. + */ -+#define PLAT_PHYS_OFFSET UL(0x00000000) ++#define BCM_PLAT_PHYS_OFFSET UL(0x00000000) +#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */ + +#ifdef CONFIG_BCM2708_NOL2CACHE @@ -4772,16 +3238,16 @@ index 0000000..521540d +#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET) +#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET)) +#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET)) -+#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PLAT_PHYS_OFFSET)) -+#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PLAT_PHYS_OFFSET)) ++#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET)) ++#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET)) + +#endif diff --git a/arch/arm/mach-bcm2708/include/mach/platform.h b/arch/arm/mach-bcm2708/include/mach/platform.h new file mode 100644 -index 0000000..110ce07 +index 0000000..2e7e1bb --- /dev/null +++ b/arch/arm/mach-bcm2708/include/mach/platform.h -@@ -0,0 +1,220 @@ +@@ -0,0 +1,228 @@ +/* + * arch/arm/mach-bcm2708/include/mach/platform.h + * @@ -4840,16 +3306,24 @@ index 0000000..110ce07 + */ + +#define BCM2708_PERI_BASE 0x20000000 ++#define IC0_BASE (BCM2708_PERI_BASE + 0x2000) +#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */ ++#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */ +#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */ +#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */ +#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */ ++#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */ ++#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */ +#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */ +#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */ +#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */ ++#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */ ++#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */ ++#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */ +#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */ +#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */ +#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */ ++#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */ +#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */ +#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/ + @@ -5240,10 +3714,10 @@ index 0000000..4a4a338 +#endif /* VC_MEM_H */ diff --git a/arch/arm/mach-bcm2708/include/mach/vcio.h b/arch/arm/mach-bcm2708/include/mach/vcio.h new file mode 100644 -index 0000000..9935e02 +index 0000000..8e11d67 --- /dev/null +++ b/arch/arm/mach-bcm2708/include/mach/vcio.h -@@ -0,0 +1,141 @@ +@@ -0,0 +1,165 @@ +/* + * arch/arm/mach-bcm2708/include/mach/vcio.h + * @@ -5279,17 +3753,24 @@ index 0000000..9935e02 +#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */ +#define MBOX_CHAN_COUNT 9 + ++enum { ++ VCMSG_PROCESS_REQUEST = 0x00000000 ++}; ++enum { ++ VCMSG_REQUEST_SUCCESSFUL = 0x80000000, ++ VCMSG_REQUEST_FAILED = 0x80000001 ++}; +/* Mailbox property tags */ +enum { + VCMSG_PROPERTY_END = 0x00000000, + VCMSG_GET_FIRMWARE_REVISION = 0x00000001, + VCMSG_GET_BOARD_MODEL = 0x00010001, -+ VCMSG_GET_BOARD_REVISION = 0x00020002, -+ VCMSG_GET_BOARD_MAC_ADDRESS = 0x00020003, -+ VCMSG_GET_BOARD_SERIAL = 0x00020004, -+ VCMSG_GET_ARM_MEMORY = 0x00020005, -+ VCMSG_GET_VC_MEMORY = 0x00020006, -+ VCMSG_GET_CLOCKS = 0x00020007, ++ VCMSG_GET_BOARD_REVISION = 0x00010002, ++ VCMSG_GET_BOARD_MAC_ADDRESS = 0x00010003, ++ VCMSG_GET_BOARD_SERIAL = 0x00010004, ++ VCMSG_GET_ARM_MEMORY = 0x00010005, ++ VCMSG_GET_VC_MEMORY = 0x00010006, ++ VCMSG_GET_CLOCKS = 0x00010007, + VCMSG_GET_COMMAND_LINE = 0x00050001, + VCMSG_GET_DMA_CHANNELS = 0x00060001, + VCMSG_GET_POWER_STATE = 0x00020001, @@ -5307,7 +3788,20 @@ index 0000000..9935e02 + VCMSG_GET_MIN_CLOCK = 0x00030007, + VCMSG_GET_MIN_VOLTAGE = 0x00030008, + VCMSG_GET_TURBO = 0x00030009, ++ VCMSG_GET_MAX_TEMPERATURE = 0x0003000a, ++ VCMSG_GET_STC = 0x0003000b, + VCMSG_SET_TURBO = 0x00038009, ++ VCMSG_SET_ALLOCATE_MEM = 0x0003000c, ++ VCMSG_SET_LOCK_MEM = 0x0003000d, ++ VCMSG_SET_UNLOCK_MEM = 0x0003000e, ++ VCMSG_SET_RELEASE_MEM = 0x0003000f, ++ VCMSG_SET_EXECUTE_CODE = 0x00030010, ++ VCMSG_SET_EXECUTE_QPU = 0x00030011, ++ VCMSG_SET_ENABLE_QPU = 0x00030012, ++ VCMSG_GET_RESOURCE_HANDLE = 0x00030014, ++ VCMSG_GET_EDID_BLOCK = 0x00030020, ++ VCMSG_GET_CUSTOMER_OTP = 0x00030021, ++ VCMSG_SET_CUSTOMER_OTP = 0x00038021, + VCMSG_SET_ALLOCATE_BUFFER = 0x00040001, + VCMSG_SET_RELEASE_BUFFER = 0x00048001, + VCMSG_SET_BLANK_SCREEN = 0x00040002, @@ -5345,6 +3839,10 @@ index 0000000..9935e02 + VCMSG_GET_TRANSFORM = 0x0004000d, + VCMSG_TST_TRANSFORM = 0x0004400d, + VCMSG_SET_TRANSFORM = 0x0004800d, ++ VCMSG_TST_VSYNC = 0x0004400e, ++ VCMSG_SET_VSYNC = 0x0004800e, ++ VCMSG_SET_CURSOR_INFO = 0x00008010, ++ VCMSG_SET_CURSOR_STATE = 0x00008011, +}; + +extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28); @@ -5382,7 +3880,7 @@ index 0000000..9935e02 +/* + * The name of the device file + */ -+#define DEVICE_FILE_NAME "char_dev" ++#define DEVICE_FILE_NAME "vcio" + +#endif diff --git a/arch/arm/mach-bcm2708/include/mach/vmalloc.h b/arch/arm/mach-bcm2708/include/mach/vmalloc.h @@ -6530,7 +5028,7 @@ index 0000000..5e43e85 +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:bcm-mbox"); diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig -index c348eae..4f31fbf 100644 +index ae69809..3ec1ca4 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -358,7 +358,7 @@ config CPU_PJ4B @@ -6543,7 +5041,7 @@ index c348eae..4f31fbf 100644 select CPU_ABRT_EV6 select CPU_CACHE_V6 diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S -index 32b3558..4712ccb 100644 +index d0390f4..a042de8 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -73,10 +73,19 @@ ENDPROC(cpu_v6_reset) @@ -6566,7 +5064,7 @@ index 32b3558..4712ccb 100644 + nop + nop + bne 1b - mov pc, lr + ret lr ENTRY(cpu_v6_dcache_clean_area) diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types @@ -6581,2062 +5079,8 @@ index a10297d..c9ddd87 100644 ag5evm MACH_AG5EVM AG5EVM 3189 ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206 wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207 -diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c -index 452782b..eee5aef 100644 ---- a/drivers/mmc/card/block.c -+++ b/drivers/mmc/card/block.c -@@ -1404,7 +1404,7 @@ static void mmc_blk_rw_rq_prep(struct mmc_queue_req *mqrq, - brq->data.blocks = 1; - } - -- if (brq->data.blocks > 1 || do_rel_wr) { -+ if (brq->data.blocks > 1 || do_rel_wr || card->host->caps2 & MMC_CAP2_FORCE_MULTIBLOCK) { - /* SPI multiblock writes terminate using a special - * token, not a STOP_TRANSMISSION request. - */ -diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c -index 0c44510..eb511d6 100644 ---- a/drivers/mmc/core/sd.c -+++ b/drivers/mmc/core/sd.c -@@ -15,6 +15,8 @@ - #include - #include - #include -+#include -+#include - - #include - #include -@@ -67,6 +69,15 @@ static const unsigned int sd_au_size[] = { - __res & __mask; \ - }) - -+// timeout for tries -+static const unsigned long retry_timeout_ms= 10*1000; -+ -+// try at least 10 times, even if timeout is reached -+static const int retry_min_tries= 10; -+ -+// delay between tries -+static const unsigned long retry_delay_ms= 10; -+ - /* - * Given the decoded CSD structure, decode the raw CID to our CID structure. - */ -@@ -219,12 +230,63 @@ static int mmc_decode_scr(struct mmc_card *card) - } - - /* -- * Fetch and process SD Status register. -+ * Fetch and process SD Configuration Register. -+ */ -+static int mmc_read_scr(struct mmc_card *card) -+{ -+ unsigned long timeout_at; -+ int err, tries; -+ -+ timeout_at= jiffies + msecs_to_jiffies( retry_timeout_ms ); -+ tries= 0; -+ -+ while( tries < retry_min_tries || time_before( jiffies, timeout_at ) ) -+ { -+ unsigned long delay_at; -+ tries++; -+ -+ err = mmc_app_send_scr(card, card->raw_scr); -+ if( !err ) -+ break; // success!!! -+ -+ touch_nmi_watchdog(); // we are still alive! -+ -+ // delay -+ delay_at= jiffies + msecs_to_jiffies( retry_delay_ms ); -+ while( time_before( jiffies, delay_at ) ) -+ { -+ mdelay( 1 ); -+ touch_nmi_watchdog(); // we are still alive! -+ } -+ } -+ -+ if( err) -+ { -+ pr_err("%s: failed to read SD Configuration register (SCR) after %d tries during %lu ms, error %d\n", mmc_hostname(card->host), tries, retry_timeout_ms, err ); -+ return err; -+ } -+ -+ if( tries > 1 ) -+ { -+ pr_info("%s: could read SD Configuration register (SCR) at the %dth attempt\n", mmc_hostname(card->host), tries ); -+ } -+ -+ err = mmc_decode_scr(card); -+ if (err) -+ return err; -+ -+ return err; -+} -+ -+/* -+ * Fetch and process SD Status Register. - */ - static int mmc_read_ssr(struct mmc_card *card) - { -+ unsigned long timeout_at; - unsigned int au, es, et, eo; - int err, i; -+ int tries; - u32 *ssr; - - if (!(card->csd.cmdclass & CCC_APP_SPEC)) { -@@ -237,14 +299,40 @@ static int mmc_read_ssr(struct mmc_card *card) - if (!ssr) - return -ENOMEM; - -- err = mmc_app_sd_status(card, ssr); -- if (err) { -- pr_warning("%s: problem reading SD Status " -- "register.\n", mmc_hostname(card->host)); -- err = 0; -+ timeout_at= jiffies + msecs_to_jiffies( retry_timeout_ms ); -+ tries= 0; -+ -+ while( tries < retry_min_tries || time_before( jiffies, timeout_at ) ) -+ { -+ unsigned long delay_at; -+ tries++; -+ -+ err= mmc_app_sd_status(card, ssr); -+ if( !err ) -+ break; // sucess!!! -+ -+ touch_nmi_watchdog(); // we are still alive! -+ -+ // delay -+ delay_at= jiffies + msecs_to_jiffies( retry_delay_ms ); -+ while( time_before( jiffies, delay_at ) ) -+ { -+ mdelay( 1 ); -+ touch_nmi_watchdog(); // we are still alive! -+ } -+ } -+ -+ if( err) -+ { -+ pr_err("%s: failed to read SD Status register (SSR) after %d tries during %lu ms, error %d\n", mmc_hostname(card->host), tries, retry_timeout_ms, err ); - goto out; - } - -+ if( tries > 1 ) -+ { -+ pr_info("%s: read SD Status register (SSR) after %d attempts\n", mmc_hostname(card->host), tries ); -+ } -+ - for (i = 0; i < 16; i++) - ssr[i] = be32_to_cpu(ssr[i]); - -@@ -818,14 +906,10 @@ int mmc_sd_setup_card(struct mmc_host *host, struct mmc_card *card, - - if (!reinit) { - /* -- * Fetch SCR from card. -+ * Fetch and decode SD Configuration register. - */ -- err = mmc_app_send_scr(card, card->raw_scr); -- if (err) -- return err; -- -- err = mmc_decode_scr(card); -- if (err) -+ err = mmc_read_scr(card); -+ if( err ) - return err; - - /* -diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig -index a565254..b152bb3 100644 ---- a/drivers/mmc/host/Kconfig -+++ b/drivers/mmc/host/Kconfig -@@ -270,6 +270,27 @@ config MMC_SDHCI_BCM_KONA - - If you have a controller with this interface, say Y or M here. - -+config MMC_SDHCI_BCM2708 -+ tristate "SDHCI support on BCM2708" -+ depends on MMC_SDHCI && MACH_BCM2708 -+ select MMC_SDHCI_IO_ACCESSORS -+ help -+ This selects the Secure Digital Host Controller Interface (SDHCI) -+ often referrered to as the eMMC block. -+ -+ If you have a controller with this interface, say Y or M here. -+ -+ If unsure, say N. -+ -+config MMC_SDHCI_BCM2708_DMA -+ bool "DMA support on BCM2708 Arasan controller" -+ depends on MMC_SDHCI_BCM2708 -+ help -+ Enable DMA support on the Arasan SDHCI controller in Broadcom 2708 -+ based chips. -+ -+ If unsure, say N. -+ - config MMC_SDHCI_BCM2835 - tristate "SDHCI platform support for the BCM2835 SD/MMC Controller" - depends on ARCH_BCM2835 -diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile -index 7f81ddf..635064e 100644 ---- a/drivers/mmc/host/Makefile -+++ b/drivers/mmc/host/Makefile -@@ -16,6 +16,7 @@ obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o - obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o - obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o - obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o -+obj-$(CONFIG_MMC_SDHCI_BCM2708) += sdhci-bcm2708.o - obj-$(CONFIG_MMC_WBSD) += wbsd.o - obj-$(CONFIG_MMC_AU1X) += au1xmmc.o - obj-$(CONFIG_MMC_OMAP) += omap.o -diff --git a/drivers/mmc/host/sdhci-bcm2708.c b/drivers/mmc/host/sdhci-bcm2708.c -new file mode 100644 -index 0000000..6e777f4 ---- /dev/null -+++ b/drivers/mmc/host/sdhci-bcm2708.c -@@ -0,0 +1,1394 @@ -+/* -+ * sdhci-bcm2708.c Support for SDHCI device on BCM2708 -+ * Copyright (c) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+/* Supports: -+ * SDHCI platform device - Arasan SD controller in BCM2708 -+ * -+ * Inspired by sdhci-pci.c, by Pierre Ossman -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "sdhci.h" -+ -+/*****************************************************************************\ -+ * * -+ * Configuration * -+ * * -+\*****************************************************************************/ -+ -+#define DRIVER_NAME "bcm2708_sdhci" -+ -+/* for the time being insist on DMA mode - PIO seems not to work */ -+#ifndef CONFIG_MMC_SDHCI_BCM2708_DMA -+#warning Non-DMA (PIO) version of this driver currently unavailable -+#endif -+#undef CONFIG_MMC_SDHCI_BCM2708_DMA -+#define CONFIG_MMC_SDHCI_BCM2708_DMA y -+ -+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA -+/* #define CHECK_DMA_USE */ -+#endif -+//#define LOG_REGISTERS -+ -+#define USE_SCHED_TIME -+#define USE_SPACED_WRITES_2CLK 1 /* space consecutive register writes */ -+#define USE_SOFTWARE_TIMEOUTS 1 /* not hardware timeouts */ -+#define SOFTWARE_ERASE_TIMEOUT_SEC 30 -+ -+#define SDHCI_BCM_DMA_CHAN 4 /* this default is normally overriden */ -+#define SDHCI_BCM_DMA_WAITS 0 /* delays slowing DMA transfers: 0-31 */ -+/* We are worried that SD card DMA use may be blocking the AXI bus for others */ -+ -+/*! TODO: obtain these from the physical address */ -+#define DMA_SDHCI_BASE 0x7e300000 /* EMMC register block on Videocore */ -+#define DMA_SDHCI_BUFFER (DMA_SDHCI_BASE + SDHCI_BUFFER) -+ -+#define BCM2708_SDHCI_SLEEP_TIMEOUT 1000 /* msecs */ -+ -+/* Mhz clock that the EMMC core is running at. Should match the platform clockman settings */ -+#define BCM2708_EMMC_CLOCK_FREQ 50000000 -+ -+#define REG_EXRDFIFO_EN 0x80 -+#define REG_EXRDFIFO_CFG 0x84 -+ -+int cycle_delay=2; -+ -+/*****************************************************************************\ -+ * * -+ * Debug * -+ * * -+\*****************************************************************************/ -+ -+ -+ -+#define DBG(f, x...) \ -+ pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) -+// printk(KERN_INFO DRIVER_NAME " [%s()]: " f, __func__,## x)//GRAYG -+ -+ -+/*****************************************************************************\ -+ * * -+ * High Precision Time * -+ * * -+\*****************************************************************************/ -+ -+#ifdef USE_SCHED_TIME -+ -+#include -+ -+typedef unsigned long hptime_t; -+ -+#define FMT_HPT "lu" -+ -+static inline hptime_t hptime(void) -+{ -+ return frc_clock_ticks32(); -+} -+ -+#define HPTIME_CLK_NS 1000ul -+ -+#else -+ -+typedef unsigned long hptime_t; -+ -+#define FMT_HPT "lu" -+ -+static inline hptime_t hptime(void) -+{ -+ return jiffies; -+} -+ -+#define HPTIME_CLK_NS (1000000000ul/HZ) -+ -+#endif -+ -+static inline unsigned long int since_ns(hptime_t t) -+{ -+ return (unsigned long)((hptime() - t) * HPTIME_CLK_NS); -+} -+ -+static bool allow_highspeed = 1; -+static int emmc_clock_freq = BCM2708_EMMC_CLOCK_FREQ; -+static bool sync_after_dma = 1; -+static bool missing_status = 1; -+bool extra_messages = 0; -+ -+#if 0 -+static void hptime_test(void) -+{ -+ hptime_t now; -+ hptime_t later; -+ -+ now = hptime(); -+ msleep(10); -+ later = hptime(); -+ -+ printk(KERN_INFO DRIVER_NAME": 10ms = %"FMT_HPT" clks " -+ "(from %"FMT_HPT" to %"FMT_HPT") = %luns\n", -+ later-now, now, later, -+ (unsigned long)(HPTIME_CLK_NS * (later - now))); -+ -+ now = hptime(); -+ msleep(1000); -+ later = hptime(); -+ -+ printk(KERN_INFO DRIVER_NAME": 1s = %"FMT_HPT" clks " -+ "(from %"FMT_HPT" to %"FMT_HPT") = %luns\n", -+ later-now, now, later, -+ (unsigned long)(HPTIME_CLK_NS * (later - now))); -+} -+#endif -+ -+/*****************************************************************************\ -+ * * -+ * SDHCI core callbacks * -+ * * -+\*****************************************************************************/ -+ -+ -+#ifdef CHECK_DMA_USE -+/*#define CHECK_DMA_REG_USE*/ -+#endif -+ -+#ifdef CHECK_DMA_REG_USE -+/* we don't expect anything to be using these registers during a -+ DMA (except the IRQ status) - so check */ -+static void check_dma_reg_use(struct sdhci_host *host, int reg); -+#else -+#define check_dma_reg_use(host, reg) -+#endif -+ -+ -+static inline u32 sdhci_bcm2708_raw_readl(struct sdhci_host *host, int reg) -+{ -+ return readl(host->ioaddr + reg); -+} -+ -+u32 sdhci_bcm2708_readl(struct sdhci_host *host, int reg) -+{ -+ u32 l = sdhci_bcm2708_raw_readl(host, reg); -+ -+#ifdef LOG_REGISTERS -+ printk(KERN_ERR "%s: readl from 0x%02x, value 0x%08x\n", -+ mmc_hostname(host->mmc), reg, l); -+#endif -+ check_dma_reg_use(host, reg); -+ -+ return l; -+} -+ -+u16 sdhci_bcm2708_readw(struct sdhci_host *host, int reg) -+{ -+ u32 l = sdhci_bcm2708_raw_readl(host, reg & ~3); -+ u32 w = l >> (reg << 3 & 0x18) & 0xffff; -+ -+#ifdef LOG_REGISTERS -+ printk(KERN_ERR "%s: readw from 0x%02x, value 0x%04x\n", -+ mmc_hostname(host->mmc), reg, w); -+#endif -+ check_dma_reg_use(host, reg); -+ -+ return (u16)w; -+} -+ -+u8 sdhci_bcm2708_readb(struct sdhci_host *host, int reg) -+{ -+ u32 l = sdhci_bcm2708_raw_readl(host, reg & ~3); -+ u32 b = l >> (reg << 3 & 0x18) & 0xff; -+ -+#ifdef LOG_REGISTERS -+ printk(KERN_ERR "%s: readb from 0x%02x, value 0x%02x\n", -+ mmc_hostname(host->mmc), reg, b); -+#endif -+ check_dma_reg_use(host, reg); -+ -+ return (u8)b; -+} -+ -+ -+static void sdhci_bcm2708_raw_writel(struct sdhci_host *host, u32 val, int reg) -+{ -+ u32 ier; -+ -+#if USE_SPACED_WRITES_2CLK -+ static bool timeout_disabled = false; -+ unsigned int ns_2clk = 0; -+ -+ /* The Arasan has a bugette whereby it may lose the content of -+ * successive writes to registers that are within two SD-card clock -+ * cycles of each other (a clock domain crossing problem). -+ * It seems, however, that the data register does not have this problem. -+ * (Which is just as well - otherwise we'd have to nobble the DMA engine -+ * too) -+ */ -+ if (reg != SDHCI_BUFFER && host->clock != 0) { -+ /* host->clock is the clock freq in Hz */ -+ static hptime_t last_write_hpt; -+ hptime_t now = hptime(); -+ ns_2clk = cycle_delay*1000000/(host->clock/1000); -+ -+ if (now == last_write_hpt || now == last_write_hpt+1) { -+ /* we can't guarantee any significant time has -+ * passed - we'll have to wait anyway ! */ -+ ndelay(ns_2clk); -+ } else -+ { -+ /* we must have waited at least this many ns: */ -+ unsigned int ns_wait = HPTIME_CLK_NS * -+ (now - last_write_hpt - 1); -+ if (ns_wait < ns_2clk) -+ ndelay(ns_2clk - ns_wait); -+ } -+ last_write_hpt = now; -+ } -+#if USE_SOFTWARE_TIMEOUTS -+ /* The Arasan is clocked for timeouts using the SD clock which is too -+ * fast for ERASE commands and causes issues. So we disable timeouts -+ * for ERASE */ -+ if (host->cmd != NULL && host->cmd->opcode == MMC_ERASE && -+ reg == (SDHCI_COMMAND & ~3)) { -+ mod_timer(&host->timer, -+ jiffies + SOFTWARE_ERASE_TIMEOUT_SEC * HZ); -+ ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE); -+ ier &= ~SDHCI_INT_DATA_TIMEOUT; -+ writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE); -+ timeout_disabled = true; -+ ndelay(ns_2clk); -+ } else if (timeout_disabled) { -+ ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE); -+ ier |= SDHCI_INT_DATA_TIMEOUT; -+ writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE); -+ timeout_disabled = false; -+ ndelay(ns_2clk); -+ } -+#endif -+ writel(val, host->ioaddr + reg); -+#else -+ void __iomem * regaddr = host->ioaddr + reg; -+ -+ writel(val, regaddr); -+ -+ if (reg != SDHCI_BUFFER && reg != SDHCI_INT_STATUS && host->clock != 0) -+ { -+ int timeout = 100000; -+ while (val != readl(regaddr) && --timeout > 0) -+ continue; -+ -+ if (timeout <= 0) -+ printk(KERN_ERR "%s: writing 0x%X to reg 0x%X " -+ "always gives 0x%X\n", -+ mmc_hostname(host->mmc), -+ val, reg, readl(regaddr)); -+ BUG_ON(timeout <= 0); -+ } -+#endif -+} -+ -+ -+void sdhci_bcm2708_writel(struct sdhci_host *host, u32 val, int reg) -+{ -+#ifdef LOG_REGISTERS -+ printk(KERN_ERR "%s: writel to 0x%02x, value 0x%08x\n", -+ mmc_hostname(host->mmc), reg, val); -+#endif -+ check_dma_reg_use(host, reg); -+ -+ sdhci_bcm2708_raw_writel(host, val, reg); -+} -+ -+void sdhci_bcm2708_writew(struct sdhci_host *host, u16 val, int reg) -+{ -+ static u32 shadow = 0; -+ -+ u32 p = reg == SDHCI_COMMAND ? shadow : -+ sdhci_bcm2708_raw_readl(host, reg & ~3); -+ u32 s = reg << 3 & 0x18; -+ u32 l = val << s; -+ u32 m = 0xffff << s; -+ -+#ifdef LOG_REGISTERS -+ printk(KERN_ERR "%s: writew to 0x%02x, value 0x%04x\n", -+ mmc_hostname(host->mmc), reg, val); -+#endif -+ -+ if (reg == SDHCI_TRANSFER_MODE) -+ shadow = (p & ~m) | l; -+ else { -+ check_dma_reg_use(host, reg); -+ sdhci_bcm2708_raw_writel(host, (p & ~m) | l, reg & ~3); -+ } -+} -+ -+void sdhci_bcm2708_writeb(struct sdhci_host *host, u8 val, int reg) -+{ -+ u32 p = sdhci_bcm2708_raw_readl(host, reg & ~3); -+ u32 s = reg << 3 & 0x18; -+ u32 l = val << s; -+ u32 m = 0xff << s; -+ -+#ifdef LOG_REGISTERS -+ printk(KERN_ERR "%s: writeb to 0x%02x, value 0x%02x\n", -+ mmc_hostname(host->mmc), reg, val); -+#endif -+ -+ check_dma_reg_use(host, reg); -+ sdhci_bcm2708_raw_writel(host, (p & ~m) | l, reg & ~3); -+} -+ -+static unsigned int sdhci_bcm2708_get_max_clock(struct sdhci_host *host) -+{ -+ return emmc_clock_freq; -+} -+ -+/*****************************************************************************\ -+ * * -+ * DMA Operation * -+ * * -+\*****************************************************************************/ -+ -+struct sdhci_bcm2708_priv { -+ int dma_chan; -+ int dma_irq; -+ void __iomem *dma_chan_base; -+ struct bcm2708_dma_cb *cb_base; /* DMA control blocks */ -+ dma_addr_t cb_handle; -+ /* tracking scatter gather progress */ -+ unsigned sg_ix; /* scatter gather list index */ -+ unsigned sg_done; /* bytes in current sg_ix done */ -+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA -+ unsigned char dma_wanted; /* DMA transfer requested */ -+ unsigned char dma_waits; /* wait states in DMAs */ -+#ifdef CHECK_DMA_USE -+ unsigned char dmas_pending; /* no of unfinished DMAs */ -+ hptime_t when_started; -+ hptime_t when_reset; -+ hptime_t when_stopped; -+#endif -+#endif -+ /* signalling the end of a transfer */ -+ void (*complete)(struct sdhci_host *); -+}; -+ -+#define SDHCI_HOST_PRIV(host) \ -+ (struct sdhci_bcm2708_priv *)((struct sdhci_host *)(host)+1) -+ -+ -+ -+#ifdef CHECK_DMA_REG_USE -+static void check_dma_reg_use(struct sdhci_host *host, int reg) -+{ -+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); -+ if (host_priv->dma_wanted && reg != SDHCI_INT_STATUS) { -+ printk(KERN_INFO"%s: accessing register 0x%x during DMA\n", -+ mmc_hostname(host->mmc), reg); -+ } -+} -+#endif -+ -+ -+ -+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA -+ -+static void sdhci_clear_set_irqgen(struct sdhci_host *host, u32 clear, u32 set) -+{ -+ u32 ier; -+ -+ ier = sdhci_bcm2708_raw_readl(host, SDHCI_SIGNAL_ENABLE); -+ ier &= ~clear; -+ ier |= set; -+ /* change which requests generate IRQs - makes no difference to -+ the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */ -+ sdhci_bcm2708_raw_writel(host, ier, SDHCI_SIGNAL_ENABLE); -+} -+ -+static void sdhci_signal_irqs(struct sdhci_host *host, u32 irqs) -+{ -+ sdhci_clear_set_irqgen(host, 0, irqs); -+} -+ -+static void sdhci_unsignal_irqs(struct sdhci_host *host, u32 irqs) -+{ -+ sdhci_clear_set_irqgen(host, irqs, 0); -+} -+ -+ -+ -+static void schci_bcm2708_cb_read(struct sdhci_bcm2708_priv *host, -+ int ix, -+ dma_addr_t dma_addr, unsigned len, -+ int /*bool*/ is_last) -+{ -+ struct bcm2708_dma_cb *cb = &host->cb_base[ix]; -+ unsigned char dmawaits = host->dma_waits; -+ -+ cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) | -+ BCM2708_DMA_WAITS(dmawaits) | -+ BCM2708_DMA_S_DREQ | -+ BCM2708_DMA_D_WIDTH | -+ BCM2708_DMA_D_INC; -+ cb->src = DMA_SDHCI_BUFFER; /* DATA register DMA address */ -+ cb->dst = dma_addr; -+ cb->length = len; -+ cb->stride = 0; -+ -+ if (is_last) { -+ cb->info |= BCM2708_DMA_INT_EN | -+ BCM2708_DMA_WAIT_RESP; -+ cb->next = 0; -+ } else -+ cb->next = host->cb_handle + -+ (ix+1)*sizeof(struct bcm2708_dma_cb); -+ -+ cb->pad[0] = 0; -+ cb->pad[1] = 0; -+} -+ -+static void schci_bcm2708_cb_write(struct sdhci_bcm2708_priv *host, -+ int ix, -+ dma_addr_t dma_addr, unsigned len, -+ int /*bool*/ is_last) -+{ -+ struct bcm2708_dma_cb *cb = &host->cb_base[ix]; -+ unsigned char dmawaits = host->dma_waits; -+ -+ /* We can make arbitrarily large writes as long as we specify DREQ to -+ pace the delivery of bytes to the Arasan hardware */ -+ cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) | -+ BCM2708_DMA_WAITS(dmawaits) | -+ BCM2708_DMA_D_DREQ | -+ BCM2708_DMA_S_WIDTH | -+ BCM2708_DMA_S_INC; -+ cb->src = dma_addr; -+ cb->dst = DMA_SDHCI_BUFFER; /* DATA register DMA address */ -+ cb->length = len; -+ cb->stride = 0; -+ -+ if (is_last) { -+ cb->info |= BCM2708_DMA_INT_EN | -+ BCM2708_DMA_WAIT_RESP; -+ cb->next = 0; -+ } else -+ cb->next = host->cb_handle + -+ (ix+1)*sizeof(struct bcm2708_dma_cb); -+ -+ cb->pad[0] = 0; -+ cb->pad[1] = 0; -+} -+ -+ -+static void schci_bcm2708_dma_go(struct sdhci_host *host) -+{ -+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); -+ void __iomem *dma_chan_base = host_priv->dma_chan_base; -+ -+ BUG_ON(host_priv->dma_wanted); -+#ifdef CHECK_DMA_USE -+ if (host_priv->dma_wanted) -+ printk(KERN_ERR "%s: DMA already in progress - " -+ "now %"FMT_HPT", last started %lu " -+ "reset %lu stopped %lu\n", -+ mmc_hostname(host->mmc), -+ hptime(), since_ns(host_priv->when_started), -+ since_ns(host_priv->when_reset), -+ since_ns(host_priv->when_stopped)); -+ else if (host_priv->dmas_pending > 0) -+ printk(KERN_INFO "%s: note - new DMA when %d reset DMAs " -+ "already in progress - " -+ "now %"FMT_HPT", started %lu reset %lu stopped %lu\n", -+ mmc_hostname(host->mmc), -+ host_priv->dmas_pending, -+ hptime(), since_ns(host_priv->when_started), -+ since_ns(host_priv->when_reset), -+ since_ns(host_priv->when_stopped)); -+ host_priv->dmas_pending += 1; -+ host_priv->when_started = hptime(); -+#endif -+ host_priv->dma_wanted = 1; -+ DBG("PDMA go - base %p handle %08X\n", dma_chan_base, -+ host_priv->cb_handle); -+ bcm_dma_start(dma_chan_base, host_priv->cb_handle); -+} -+ -+ -+static void -+sdhci_platdma_read(struct sdhci_host *host, dma_addr_t dma_addr, size_t len) -+{ -+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); -+ -+ DBG("PDMA to read %d bytes\n", len); -+ host_priv->sg_done += len; -+ schci_bcm2708_cb_read(host_priv, 0, dma_addr, len, 1/*TRUE*/); -+ schci_bcm2708_dma_go(host); -+} -+ -+ -+static void -+sdhci_platdma_write(struct sdhci_host *host, dma_addr_t dma_addr, size_t len) -+{ -+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); -+ -+ DBG("PDMA to write %d bytes\n", len); -+ //BUG_ON(0 != (len & 0x1ff)); -+ -+ host_priv->sg_done += len; -+ schci_bcm2708_cb_write(host_priv, 0, dma_addr, len, 1/*TRUE*/); -+ schci_bcm2708_dma_go(host); -+} -+ -+/*! space is avaiable to receive into or data is available to write -+ Platform DMA exported function -+*/ -+void -+sdhci_bcm2708_platdma_avail(struct sdhci_host *host, unsigned int *ref_intmask, -+ void(*completion_callback)(struct sdhci_host *host)) -+{ -+ struct mmc_data *data = host->data; -+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); -+ int sg_ix; -+ size_t bytes; -+ dma_addr_t addr; -+ -+ BUG_ON(NULL == data); -+ BUG_ON(0 == data->blksz); -+ -+ host_priv->complete = completion_callback; -+ -+ sg_ix = host_priv->sg_ix; -+ BUG_ON(sg_ix >= data->sg_len); -+ -+ /* we can DMA blocks larger than blksz - it may hang the DMA -+ channel but we are its only user */ -+ bytes = sg_dma_len(&data->sg[sg_ix]) - host_priv->sg_done; -+ addr = sg_dma_address(&data->sg[sg_ix]) + host_priv->sg_done; -+ -+ if (bytes > 0) { -+ /* We're going to poll for read/write available state until -+ we finish this DMA -+ */ -+ -+ if (data->flags & MMC_DATA_READ) { -+ if (*ref_intmask & SDHCI_INT_DATA_AVAIL) { -+ sdhci_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL | -+ SDHCI_INT_SPACE_AVAIL); -+ sdhci_platdma_read(host, addr, bytes); -+ } -+ } else { -+ if (*ref_intmask & SDHCI_INT_SPACE_AVAIL) { -+ sdhci_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL | -+ SDHCI_INT_SPACE_AVAIL); -+ sdhci_platdma_write(host, addr, bytes); -+ } -+ } -+ } -+ /* else: -+ we have run out of bytes that need transferring (e.g. we may be in -+ the middle of the last DMA transfer), or -+ it is also possible that we've been called when another IRQ is -+ signalled, even though we've turned off signalling of our own IRQ */ -+ -+ *ref_intmask &= ~SDHCI_INT_DATA_END; -+ /* don't let the main sdhci driver act on this .. we'll deal with it -+ when we respond to the DMA - if one is currently in progress */ -+} -+ -+/* is it possible to DMA the given mmc_data structure? -+ Platform DMA exported function -+*/ -+int /*bool*/ -+sdhci_bcm2708_platdma_dmaable(struct sdhci_host *host, struct mmc_data *data) -+{ -+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); -+ int ok = bcm_sg_suitable_for_dma(data->sg, data->sg_len); -+ -+ if (!ok) -+ DBG("Reverting to PIO - bad cache alignment\n"); -+ -+ else { -+ host_priv->sg_ix = 0; /* first SG index */ -+ host_priv->sg_done = 0; /* no bytes done */ -+ } -+ -+ return ok; -+} -+ -+#include //GRAYG -+/*! the current SD transacton has been abandonned -+ We need to tidy up if we were in the middle of a DMA -+ Platform DMA exported function -+*/ -+void -+sdhci_bcm2708_platdma_reset(struct sdhci_host *host, struct mmc_data *data) -+{ -+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); -+// unsigned long flags; -+ -+ BUG_ON(NULL == host); -+ -+// spin_lock_irqsave(&host->lock, flags); -+ -+ if (host_priv->dma_wanted) { -+ if (NULL == data) { -+ printk(KERN_ERR "%s: ongoing DMA reset - no data!\n", -+ mmc_hostname(host->mmc)); -+ BUG_ON(NULL == data); -+ } else { -+ struct scatterlist *sg; -+ int sg_len; -+ int sg_todo; -+ int rc; -+ unsigned long cs; -+ -+ sg = data->sg; -+ sg_len = data->sg_len; -+ sg_todo = sg_dma_len(&sg[host_priv->sg_ix]); -+ -+ cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS); -+ -+ if (!(BCM2708_DMA_ACTIVE & cs)) -+ { -+ if (extra_messages) -+ printk(KERN_INFO "%s: missed completion of " -+ "cmd DMA (%d/%d [%d]/[%d]) - " -+ "ignoring it\n", -+ mmc_hostname(host->mmc), -+ host_priv->sg_done, sg_todo, -+ host_priv->sg_ix+1, sg_len); -+ } -+ else -+ printk(KERN_INFO "%s: resetting ongoing cmd" -+ "DMA before %d/%d [%d]/[%d] complete\n", -+ mmc_hostname(host->mmc), -+ host_priv->sg_done, sg_todo, -+ host_priv->sg_ix+1, sg_len); -+#ifdef CHECK_DMA_USE -+ printk(KERN_INFO "%s: now %"FMT_HPT" started %lu " -+ "last reset %lu last stopped %lu\n", -+ mmc_hostname(host->mmc), -+ hptime(), since_ns(host_priv->when_started), -+ since_ns(host_priv->when_reset), -+ since_ns(host_priv->when_stopped)); -+ { unsigned long info, debug; -+ void __iomem *base; -+ unsigned long pend0, pend1, pend2; -+ -+ base = host_priv->dma_chan_base; -+ cs = readl(base + BCM2708_DMA_CS); -+ info = readl(base + BCM2708_DMA_INFO); -+ debug = readl(base + BCM2708_DMA_DEBUG); -+ printk(KERN_INFO "%s: DMA%d CS=%08lX TI=%08lX " -+ "DEBUG=%08lX\n", -+ mmc_hostname(host->mmc), -+ host_priv->dma_chan, -+ cs, info, debug); -+ pend0 = readl(__io_address(ARM_IRQ_PEND0)); -+ pend1 = readl(__io_address(ARM_IRQ_PEND1)); -+ pend2 = readl(__io_address(ARM_IRQ_PEND2)); -+ -+ printk(KERN_INFO "%s: PEND0=%08lX " -+ "PEND1=%08lX PEND2=%08lX\n", -+ mmc_hostname(host->mmc), -+ pend0, pend1, pend2); -+ -+ //gintsts = readl(__io_address(GINTSTS)); -+ //gintmsk = readl(__io_address(GINTMSK)); -+ //printk(KERN_INFO "%s: USB GINTSTS=%08lX" -+ // "GINTMSK=%08lX\n", -+ // mmc_hostname(host->mmc), gintsts, gintmsk); -+ } -+#endif -+ rc = bcm_dma_abort(host_priv->dma_chan_base); -+ BUG_ON(rc != 0); -+ } -+ host_priv->dma_wanted = 0; -+#ifdef CHECK_DMA_USE -+ host_priv->when_reset = hptime(); -+#endif -+ } -+ -+// spin_unlock_irqrestore(&host->lock, flags); -+} -+ -+ -+static void sdhci_bcm2708_dma_complete_irq(struct sdhci_host *host, -+ u32 dma_cs) -+{ -+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); -+ struct mmc_data *data; -+ struct scatterlist *sg; -+ int sg_len; -+ int sg_ix; -+ int sg_todo; -+// unsigned long flags; -+ -+ BUG_ON(NULL == host); -+ -+// spin_lock_irqsave(&host->lock, flags); -+ data = host->data; -+ -+#ifdef CHECK_DMA_USE -+ if (host_priv->dmas_pending <= 0) -+ DBG("on completion no DMA in progress - " -+ "now %"FMT_HPT" started %lu reset %lu stopped %lu\n", -+ hptime(), since_ns(host_priv->when_started), -+ since_ns(host_priv->when_reset), -+ since_ns(host_priv->when_stopped)); -+ else if (host_priv->dmas_pending > 1) -+ DBG("still %d DMA in progress after completion - " -+ "now %"FMT_HPT" started %lu reset %lu stopped %lu\n", -+ host_priv->dmas_pending - 1, -+ hptime(), since_ns(host_priv->when_started), -+ since_ns(host_priv->when_reset), -+ since_ns(host_priv->when_stopped)); -+ BUG_ON(host_priv->dmas_pending <= 0); -+ host_priv->dmas_pending -= 1; -+ host_priv->when_stopped = hptime(); -+#endif -+ host_priv->dma_wanted = 0; -+ -+ if (NULL == data) { -+ DBG("PDMA unused completion - status 0x%X\n", dma_cs); -+// spin_unlock_irqrestore(&host->lock, flags); -+ return; -+ } -+ sg = data->sg; -+ sg_len = data->sg_len; -+ sg_todo = sg_dma_len(&sg[host_priv->sg_ix]); -+ -+ DBG("PDMA complete %d/%d [%d]/[%d]..\n", -+ host_priv->sg_done, sg_todo, -+ host_priv->sg_ix+1, sg_len); -+ -+ BUG_ON(host_priv->sg_done > sg_todo); -+ -+ if (host_priv->sg_done >= sg_todo) { -+ host_priv->sg_ix++; -+ host_priv->sg_done = 0; -+ } -+ -+ sg_ix = host_priv->sg_ix; -+ if (sg_ix < sg_len) { -+ u32 irq_mask; -+ /* Set off next DMA if we've got the capacity */ -+ -+ if (data->flags & MMC_DATA_READ) -+ irq_mask = SDHCI_INT_DATA_AVAIL; -+ else -+ irq_mask = SDHCI_INT_SPACE_AVAIL; -+ -+ /* We have to use the interrupt status register on the BCM2708 -+ rather than the SDHCI_PRESENT_STATE register because latency -+ in the glue logic means that the information retrieved from -+ the latter is not always up-to-date w.r.t the DMA engine - -+ it may not indicate that a read or a write is ready yet */ -+ if (sdhci_bcm2708_raw_readl(host, SDHCI_INT_STATUS) & -+ irq_mask) { -+ size_t bytes = sg_dma_len(&sg[sg_ix]) - -+ host_priv->sg_done; -+ dma_addr_t addr = sg_dma_address(&data->sg[sg_ix]) + -+ host_priv->sg_done; -+ -+ /* acknowledge interrupt */ -+ sdhci_bcm2708_raw_writel(host, irq_mask, -+ SDHCI_INT_STATUS); -+ -+ BUG_ON(0 == bytes); -+ -+ if (data->flags & MMC_DATA_READ) -+ sdhci_platdma_read(host, addr, bytes); -+ else -+ sdhci_platdma_write(host, addr, bytes); -+ } else { -+ DBG("PDMA - wait avail\n"); -+ /* may generate an IRQ if already present */ -+ sdhci_signal_irqs(host, SDHCI_INT_DATA_AVAIL | -+ SDHCI_INT_SPACE_AVAIL); -+ } -+ } else { -+ if (sync_after_dma) { -+ /* On the Arasan controller the stop command (which will be -+ scheduled after this completes) does not seem to work -+ properly if we allow it to be issued when we are -+ transferring data to/from the SD card. -+ We get CRC and DEND errors unless we wait for -+ the SD controller to finish reading/writing to the card. */ -+ u32 state_mask; -+ int timeout=3*1000*1000; -+ -+ DBG("PDMA over - sync card\n"); -+ if (data->flags & MMC_DATA_READ) -+ state_mask = SDHCI_DOING_READ; -+ else -+ state_mask = SDHCI_DOING_WRITE; -+ -+ while (0 != (sdhci_bcm2708_raw_readl(host, SDHCI_PRESENT_STATE) -+ & state_mask) && --timeout > 0) -+ { -+ udelay(1); -+ continue; -+ } -+ if (timeout <= 0) -+ printk(KERN_ERR"%s: final %s to SD card still " -+ "running\n", -+ mmc_hostname(host->mmc), -+ data->flags & MMC_DATA_READ? "read": "write"); -+ } -+ if (host_priv->complete) { -+ (*host_priv->complete)(host); -+ DBG("PDMA %s complete\n", -+ data->flags & MMC_DATA_READ?"read":"write"); -+ sdhci_signal_irqs(host, SDHCI_INT_DATA_AVAIL | -+ SDHCI_INT_SPACE_AVAIL); -+ } -+ } -+// spin_unlock_irqrestore(&host->lock, flags); -+} -+ -+static irqreturn_t sdhci_bcm2708_dma_irq(int irq, void *dev_id) -+{ -+ irqreturn_t result = IRQ_NONE; -+ struct sdhci_host *host = dev_id; -+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); -+ u32 dma_cs; /* control and status register */ -+ unsigned long flags; -+ -+ BUG_ON(NULL == dev_id); -+ BUG_ON(NULL == host_priv->dma_chan_base); -+ -+ spin_lock_irqsave(&host->lock, flags); -+ -+ dma_cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS); -+ -+ if (dma_cs & BCM2708_DMA_ERR) { -+ unsigned long debug; -+ debug = readl(host_priv->dma_chan_base + -+ BCM2708_DMA_DEBUG); -+ printk(KERN_ERR "%s: DMA error - CS %lX DEBUG %lX\n", -+ mmc_hostname(host->mmc), (unsigned long)dma_cs, -+ (unsigned long)debug); -+ /* reset error */ -+ writel(debug, host_priv->dma_chan_base + -+ BCM2708_DMA_DEBUG); -+ } -+ if (dma_cs & BCM2708_DMA_INT) { -+ /* acknowledge interrupt */ -+ writel(BCM2708_DMA_INT, -+ host_priv->dma_chan_base + BCM2708_DMA_CS); -+ -+ dsb(); /* ARM data synchronization (push) operation */ -+ -+ if (!host_priv->dma_wanted) { -+ /* ignore this interrupt - it was reset */ -+ if (extra_messages) -+ printk(KERN_INFO "%s: DMA IRQ %X ignored - " -+ "results were reset\n", -+ mmc_hostname(host->mmc), dma_cs); -+#ifdef CHECK_DMA_USE -+ printk(KERN_INFO "%s: now %"FMT_HPT -+ " started %lu reset %lu stopped %lu\n", -+ mmc_hostname(host->mmc), hptime(), -+ since_ns(host_priv->when_started), -+ since_ns(host_priv->when_reset), -+ since_ns(host_priv->when_stopped)); -+ host_priv->dmas_pending--; -+#endif -+ } else -+ sdhci_bcm2708_dma_complete_irq(host, dma_cs); -+ -+ result = IRQ_HANDLED; -+ } -+ spin_unlock_irqrestore(&host->lock, flags); -+ -+ return result; -+} -+#endif /* CONFIG_MMC_SDHCI_BCM2708_DMA */ -+ -+ -+/***************************************************************************** \ -+ * * -+ * Device Attributes * -+ * * -+\*****************************************************************************/ -+ -+ -+/** -+ * Show the DMA-using status -+ */ -+static ssize_t attr_dma_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev); -+ -+ if (host) { -+ int use_dma = (host->flags & SDHCI_USE_PLATDMA? 1:0); -+ return sprintf(buf, "%d\n", use_dma); -+ } else -+ return -EINVAL; -+} -+ -+/** -+ * Set the DMA-using status -+ */ -+static ssize_t attr_dma_store(struct device *_dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev); -+ -+ if (host) { -+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA -+ int on = simple_strtol(buf, NULL, 0); -+ if (on) { -+ host->flags |= SDHCI_USE_PLATDMA; -+ sdhci_bcm2708_writel(host, 1, REG_EXRDFIFO_EN); -+ printk(KERN_INFO "%s: DMA enabled\n", -+ mmc_hostname(host->mmc)); -+ } else { -+ host->flags &= ~(SDHCI_USE_PLATDMA | SDHCI_REQ_USE_DMA); -+ sdhci_bcm2708_writel(host, 0, REG_EXRDFIFO_EN); -+ printk(KERN_INFO "%s: DMA disabled\n", -+ mmc_hostname(host->mmc)); -+ } -+#endif -+ return count; -+ } else -+ return -EINVAL; -+} -+ -+static DEVICE_ATTR(use_dma, S_IRUGO | S_IWUGO, attr_dma_show, attr_dma_store); -+ -+ -+/** -+ * Show the DMA wait states used -+ */ -+static ssize_t attr_dmawait_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev); -+ -+ if (host) { -+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); -+ int dmawait = host_priv->dma_waits; -+ return sprintf(buf, "%d\n", dmawait); -+ } else -+ return -EINVAL; -+} -+ -+/** -+ * Set the DMA wait state used -+ */ -+static ssize_t attr_dmawait_store(struct device *_dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev); -+ -+ if (host) { -+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA -+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); -+ int dma_waits = simple_strtol(buf, NULL, 0); -+ if (dma_waits >= 0 && dma_waits < 32) -+ host_priv->dma_waits = dma_waits; -+ else -+ printk(KERN_ERR "%s: illegal dma_waits value - %d", -+ mmc_hostname(host->mmc), dma_waits); -+#endif -+ return count; -+ } else -+ return -EINVAL; -+} -+ -+static DEVICE_ATTR(dma_wait, S_IRUGO | S_IWUGO, -+ attr_dmawait_show, attr_dmawait_store); -+ -+ -+/** -+ * Show the DMA-using status -+ */ -+static ssize_t attr_status_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev); -+ -+ if (host) { -+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); -+ return sprintf(buf, -+ "present: yes\n" -+ "power: %s\n" -+ "clock: %u Hz\n" -+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA -+ "dma: %s (%d waits)\n", -+#else -+ "dma: unconfigured\n", -+#endif -+ "always on", -+ host->clock -+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA -+ , (host->flags & SDHCI_USE_PLATDMA)? "on": "off" -+ , host_priv->dma_waits -+#endif -+ ); -+ } else -+ return -EINVAL; -+} -+ -+static DEVICE_ATTR(status, S_IRUGO, attr_status_show, NULL); -+ -+/***************************************************************************** \ -+ * * -+ * Power Management * -+ * * -+\*****************************************************************************/ -+ -+ -+#ifdef CONFIG_PM -+static int sdhci_bcm2708_suspend(struct platform_device *dev, pm_message_t state) -+{ -+ struct sdhci_host *host = (struct sdhci_host *) -+ platform_get_drvdata(dev); -+ int ret = 0; -+ -+ if (host->mmc) { -+ //ret = mmc_suspend_host(host->mmc); -+ } -+ -+ return ret; -+} -+ -+static int sdhci_bcm2708_resume(struct platform_device *dev) -+{ -+ struct sdhci_host *host = (struct sdhci_host *) -+ platform_get_drvdata(dev); -+ int ret = 0; -+ -+ if (host->mmc) { -+ //ret = mmc_resume_host(host->mmc); -+ } -+ -+ return ret; -+} -+#endif -+ -+ -+/*****************************************************************************\ -+ * * -+ * Device quirk functions. Implemented as local ops because the flags * -+ * field is out of space with newer kernels. This implementation can be * -+ * back ported to older kernels as well. * -+\****************************************************************************/ -+static unsigned int sdhci_bcm2708_quirk_extra_ints(struct sdhci_host *host) -+{ -+ return 1; -+} -+ -+static unsigned int sdhci_bcm2708_missing_status(struct sdhci_host *host) -+{ -+ return 1; -+} -+ -+/***************************************************************************** \ -+ * * -+ * Device ops * -+ * * -+\*****************************************************************************/ -+ -+static struct sdhci_ops sdhci_bcm2708_ops = { -+#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS -+ .read_l = sdhci_bcm2708_readl, -+ .read_w = sdhci_bcm2708_readw, -+ .read_b = sdhci_bcm2708_readb, -+ .write_l = sdhci_bcm2708_writel, -+ .write_w = sdhci_bcm2708_writew, -+ .write_b = sdhci_bcm2708_writeb, -+#else -+#error The BCM2708 SDHCI driver needs CONFIG_MMC_SDHCI_IO_ACCESSORS to be set -+#endif -+ .get_max_clock = sdhci_bcm2708_get_max_clock, -+ -+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA -+ // Platform DMA operations -+ .pdma_able = sdhci_bcm2708_platdma_dmaable, -+ .pdma_avail = sdhci_bcm2708_platdma_avail, -+ .pdma_reset = sdhci_bcm2708_platdma_reset, -+#endif -+ .extra_ints = sdhci_bcm2708_quirk_extra_ints, -+ -+ .set_clock = sdhci_set_clock, -+ .set_bus_width = sdhci_set_bus_width, -+ .reset = sdhci_reset, -+ .set_uhs_signaling = sdhci_set_uhs_signaling, -+}; -+ -+/*****************************************************************************\ -+ * * -+ * Device probing/removal * -+ * * -+\*****************************************************************************/ -+ -+static int sdhci_bcm2708_probe(struct platform_device *pdev) -+{ -+ struct sdhci_host *host; -+ struct resource *iomem; -+ struct sdhci_bcm2708_priv *host_priv; -+ int ret; -+ -+ BUG_ON(pdev == NULL); -+ -+ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!iomem) { -+ ret = -ENOMEM; -+ goto err; -+ } -+ -+ if (resource_size(iomem) != 0x100) -+ dev_err(&pdev->dev, "Invalid iomem size. You may " -+ "experience problems.\n"); -+ -+ if (pdev->dev.parent) -+ host = sdhci_alloc_host(pdev->dev.parent, -+ sizeof(struct sdhci_bcm2708_priv)); -+ else -+ host = sdhci_alloc_host(&pdev->dev, -+ sizeof(struct sdhci_bcm2708_priv)); -+ -+ if (IS_ERR(host)) { -+ ret = PTR_ERR(host); -+ goto err; -+ } -+ if (missing_status) { -+ sdhci_bcm2708_ops.missing_status = sdhci_bcm2708_missing_status; -+ } -+ -+ host->hw_name = "BCM2708_Arasan"; -+ host->ops = &sdhci_bcm2708_ops; -+ host->irq = platform_get_irq(pdev, 0); -+ -+ host->quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | -+ SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | -+ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | -+ SDHCI_QUIRK_MISSING_CAPS | -+ SDHCI_QUIRK_NO_HISPD_BIT | -+ (sync_after_dma ? 0:SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12); -+ -+ -+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA -+ host->flags = SDHCI_USE_PLATDMA; -+#endif -+ -+ if (!request_mem_region(iomem->start, resource_size(iomem), -+ mmc_hostname(host->mmc))) { -+ dev_err(&pdev->dev, "cannot request region\n"); -+ ret = -EBUSY; -+ goto err_request; -+ } -+ -+ host->ioaddr = ioremap(iomem->start, resource_size(iomem)); -+ if (!host->ioaddr) { -+ dev_err(&pdev->dev, "failed to remap registers\n"); -+ ret = -ENOMEM; -+ goto err_remap; -+ } -+ -+ host_priv = SDHCI_HOST_PRIV(host); -+ -+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA -+ host_priv->dma_wanted = 0; -+#ifdef CHECK_DMA_USE -+ host_priv->dmas_pending = 0; -+ host_priv->when_started = 0; -+ host_priv->when_reset = 0; -+ host_priv->when_stopped = 0; -+#endif -+ host_priv->sg_ix = 0; -+ host_priv->sg_done = 0; -+ host_priv->complete = NULL; -+ host_priv->dma_waits = SDHCI_BCM_DMA_WAITS; -+ -+ host_priv->cb_base = dma_alloc_writecombine(&pdev->dev, SZ_4K, -+ &host_priv->cb_handle, -+ GFP_KERNEL); -+ if (!host_priv->cb_base) { -+ dev_err(&pdev->dev, "cannot allocate DMA CBs\n"); -+ ret = -ENOMEM; -+ goto err_alloc_cb; -+ } -+ -+ ret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST, -+ &host_priv->dma_chan_base, -+ &host_priv->dma_irq); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "couldn't allocate a DMA channel\n"); -+ goto err_add_dma; -+ } -+ host_priv->dma_chan = ret; -+ -+ ret = request_irq(host_priv->dma_irq, sdhci_bcm2708_dma_irq, -+ IRQF_SHARED, DRIVER_NAME " (dma)", host); -+ if (ret) { -+ dev_err(&pdev->dev, "cannot set DMA IRQ\n"); -+ goto err_add_dma_irq; -+ } -+ DBG("DMA CBs %p handle %08X DMA%d %p DMA IRQ %d\n", -+ host_priv->cb_base, (unsigned)host_priv->cb_handle, -+ host_priv->dma_chan, host_priv->dma_chan_base, -+ host_priv->dma_irq); -+ -+ // we support 3.3V -+ host->caps |= SDHCI_CAN_VDD_330; -+ if (allow_highspeed) -+ host->mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; -+ -+ /* single block writes cause data loss with some SD cards! */ -+ host->mmc->caps2 |= MMC_CAP2_FORCE_MULTIBLOCK; -+#endif -+ -+ ret = sdhci_add_host(host); -+ if (ret) -+ goto err_add_host; -+ -+ platform_set_drvdata(pdev, host); -+ ret = device_create_file(&pdev->dev, &dev_attr_use_dma); -+ ret = device_create_file(&pdev->dev, &dev_attr_dma_wait); -+ ret = device_create_file(&pdev->dev, &dev_attr_status); -+ -+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA -+ /* enable extension fifo for paced DMA transfers */ -+ sdhci_bcm2708_writel(host, 1, REG_EXRDFIFO_EN); -+ sdhci_bcm2708_writel(host, 4, REG_EXRDFIFO_CFG); -+#endif -+ -+ printk(KERN_INFO "%s: BCM2708 SDHC host at 0x%08llx DMA %d IRQ %d\n", -+ mmc_hostname(host->mmc), (unsigned long long)iomem->start, -+ host_priv->dma_chan, host_priv->dma_irq); -+ -+ return 0; -+ -+err_add_host: -+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA -+ free_irq(host_priv->dma_irq, host); -+err_add_dma_irq: -+ bcm_dma_chan_free(host_priv->dma_chan); -+err_add_dma: -+ dma_free_writecombine(&pdev->dev, SZ_4K, host_priv->cb_base, -+ host_priv->cb_handle); -+err_alloc_cb: -+#endif -+ iounmap(host->ioaddr); -+err_remap: -+ release_mem_region(iomem->start, resource_size(iomem)); -+err_request: -+ sdhci_free_host(host); -+err: -+ dev_err(&pdev->dev, "probe failed, err %d\n", ret); -+ return ret; -+} -+ -+static int sdhci_bcm2708_remove(struct platform_device *pdev) -+{ -+ struct sdhci_host *host = platform_get_drvdata(pdev); -+ struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); -+ int dead; -+ u32 scratch; -+ -+ dead = 0; -+ scratch = sdhci_bcm2708_readl(host, SDHCI_INT_STATUS); -+ if (scratch == (u32)-1) -+ dead = 1; -+ -+ device_remove_file(&pdev->dev, &dev_attr_status); -+ device_remove_file(&pdev->dev, &dev_attr_dma_wait); -+ device_remove_file(&pdev->dev, &dev_attr_use_dma); -+ -+#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA -+ free_irq(host_priv->dma_irq, host); -+ dma_free_writecombine(&pdev->dev, SZ_4K, host_priv->cb_base, -+ host_priv->cb_handle); -+#endif -+ sdhci_remove_host(host, dead); -+ iounmap(host->ioaddr); -+ release_mem_region(iomem->start, resource_size(iomem)); -+ sdhci_free_host(host); -+ platform_set_drvdata(pdev, NULL); -+ -+ return 0; -+} -+ -+static struct platform_driver sdhci_bcm2708_driver = { -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ }, -+ .probe = sdhci_bcm2708_probe, -+ .remove = sdhci_bcm2708_remove, -+ -+#ifdef CONFIG_PM -+ .suspend = sdhci_bcm2708_suspend, -+ .resume = sdhci_bcm2708_resume, -+#endif -+ -+}; -+ -+/*****************************************************************************\ -+ * * -+ * Driver init/exit * -+ * * -+\*****************************************************************************/ -+ -+static int __init sdhci_drv_init(void) -+{ -+ return platform_driver_register(&sdhci_bcm2708_driver); -+} -+ -+static void __exit sdhci_drv_exit(void) -+{ -+ platform_driver_unregister(&sdhci_bcm2708_driver); -+} -+ -+module_init(sdhci_drv_init); -+module_exit(sdhci_drv_exit); -+ -+module_param(allow_highspeed, bool, 0444); -+module_param(emmc_clock_freq, int, 0444); -+module_param(sync_after_dma, bool, 0444); -+module_param(missing_status, bool, 0444); -+module_param(cycle_delay, int, 0444); -+module_param(extra_messages, bool, 0444); -+ -+MODULE_DESCRIPTION("Secure Digital Host Controller Interface platform driver"); -+MODULE_AUTHOR("Broadcom "); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:"DRIVER_NAME); -+ -+MODULE_PARM_DESC(allow_highspeed, "Allow high speed transfers modes"); -+MODULE_PARM_DESC(emmc_clock_freq, "Specify the speed of emmc clock"); -+MODULE_PARM_DESC(sync_after_dma, "Block in driver until dma complete"); -+MODULE_PARM_DESC(missing_status, "Use the missing status quirk"); -+MODULE_PARM_DESC(extra_messages, "Enable more sdcard warning messages"); -+ -+ -diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c -index 47055f3..e47c346 100644 ---- a/drivers/mmc/host/sdhci.c -+++ b/drivers/mmc/host/sdhci.c -@@ -28,6 +28,7 @@ - #include - #include - #include -+#include - #include - - #include "sdhci.h" -@@ -312,7 +313,7 @@ static void sdhci_read_block_pio(struct sdhci_host *host) - u32 uninitialized_var(scratch); - u8 *buf; - -- DBG("PIO reading\n"); -+ DBG("PIO reading %db\n", host->data->blksz); - - blksize = host->data->blksz; - chunk = 0; -@@ -357,7 +358,7 @@ static void sdhci_write_block_pio(struct sdhci_host *host) - u32 scratch; - u8 *buf; - -- DBG("PIO writing\n"); -+ DBG("PIO writing %db\n", host->data->blksz); - - blksize = host->data->blksz; - chunk = 0; -@@ -396,19 +397,28 @@ static void sdhci_write_block_pio(struct sdhci_host *host) - local_irq_restore(flags); - } - --static void sdhci_transfer_pio(struct sdhci_host *host) -+static void sdhci_transfer_pio(struct sdhci_host *host, u32 intstate) - { - u32 mask; -+ u32 state = 0; -+ u32 intmask; -+ int available; - - BUG_ON(!host->data); - - if (host->blocks == 0) - return; - -- if (host->data->flags & MMC_DATA_READ) -+ if (host->data->flags & MMC_DATA_READ) { - mask = SDHCI_DATA_AVAILABLE; -- else -+ intmask = SDHCI_INT_DATA_AVAIL; -+ } else { - mask = SDHCI_SPACE_AVAILABLE; -+ intmask = SDHCI_INT_SPACE_AVAIL; -+ } -+ -+ /* initially we can see whether we can procede using intstate */ -+ available = (intstate & intmask); - - /* - * Some controllers (JMicron JMB38x) mess up the buffer bits -@@ -419,7 +429,7 @@ static void sdhci_transfer_pio(struct sdhci_host *host) - (host->data->blocks == 1)) - mask = ~0; - -- while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { -+ while (available) { - if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) - udelay(100); - -@@ -431,9 +441,12 @@ static void sdhci_transfer_pio(struct sdhci_host *host) - host->blocks--; - if (host->blocks == 0) - break; -+ state = sdhci_readl(host, SDHCI_PRESENT_STATE); -+ available = state & mask; -+ break; - } - -- DBG("PIO transfer complete.\n"); -+ DBG("PIO transfer complete - %d blocks left.\n", host->blocks); - } - - static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) -@@ -698,7 +711,9 @@ static void sdhci_set_transfer_irqs(struct sdhci_host *host) - u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; - u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; - -- if (host->flags & SDHCI_REQ_USE_DMA) -+ /* platform DMA will begin on receipt of PIO irqs */ -+ if ((host->flags & SDHCI_REQ_USE_DMA) && -+ !(host->flags & SDHCI_USE_PLATDMA)) - host->ier = (host->ier & ~pio_irqs) | dma_irqs; - else - host->ier = (host->ier & ~dma_irqs) | pio_irqs; -@@ -733,44 +748,25 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) - host->data_early = 0; - host->data->bytes_xfered = 0; - -- if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) -+ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA | SDHCI_USE_PLATDMA)) - host->flags |= SDHCI_REQ_USE_DMA; - - /* - * FIXME: This doesn't account for merging when mapping the - * scatterlist. - */ -- if (host->flags & SDHCI_REQ_USE_DMA) { -- int broken, i; -- struct scatterlist *sg; -- -- broken = 0; -- if (host->flags & SDHCI_USE_ADMA) { -- if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) -- broken = 1; -- } else { -- if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) -- broken = 1; -- } -- -- if (unlikely(broken)) { -- for_each_sg(data->sg, sg, data->sg_len, i) { -- if (sg->length & 0x3) { -- DBG("Reverting to PIO because of " -- "transfer size (%d)\n", -- sg->length); -- host->flags &= ~SDHCI_REQ_USE_DMA; -- break; -- } -- } -- } -- } - - /* - * The assumption here being that alignment is the same after - * translation to device address space. - */ -- if (host->flags & SDHCI_REQ_USE_DMA) { -+ if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_PLATDMA)) == -+ (SDHCI_REQ_USE_DMA | SDHCI_USE_PLATDMA)) { -+ -+ if (! sdhci_platdma_dmaable(host, data)) -+ host->flags &= ~SDHCI_REQ_USE_DMA; -+ -+ } else if (host->flags & SDHCI_REQ_USE_DMA) { - int broken, i; - struct scatterlist *sg; - -@@ -829,7 +825,8 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) - */ - WARN_ON(1); - host->flags &= ~SDHCI_REQ_USE_DMA; -- } else { -+ } else -+ if (!(host->flags & SDHCI_USE_PLATDMA)) { - WARN_ON(sg_cnt != 1); - sdhci_writel(host, sg_dma_address(data->sg), - SDHCI_DMA_ADDRESS); -@@ -845,11 +842,13 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) - if (host->version >= SDHCI_SPEC_200) { - ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); - ctrl &= ~SDHCI_CTRL_DMA_MASK; -+ if (! (host->flags & SDHCI_USE_PLATDMA)) { - if ((host->flags & SDHCI_REQ_USE_DMA) && - (host->flags & SDHCI_USE_ADMA)) - ctrl |= SDHCI_CTRL_ADMA32; - else - ctrl |= SDHCI_CTRL_SDMA; -+ } - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); - } - -@@ -906,7 +905,8 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host, - - if (data->flags & MMC_DATA_READ) - mode |= SDHCI_TRNS_READ; -- if (host->flags & SDHCI_REQ_USE_DMA) -+ if ((host->flags & SDHCI_REQ_USE_DMA) && -+ !(host->flags & SDHCI_USE_PLATDMA)) - mode |= SDHCI_TRNS_DMA; - - sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); -@@ -922,13 +922,16 @@ static void sdhci_finish_data(struct sdhci_host *host) - host->data = NULL; - - if (host->flags & SDHCI_REQ_USE_DMA) { -- if (host->flags & SDHCI_USE_ADMA) -- sdhci_adma_table_post(host, data); -- else { -+ /* we may have to abandon an ongoing platform DMA */ -+ if (host->flags & SDHCI_USE_PLATDMA) -+ sdhci_platdma_reset(host, data); -+ -+ if (host->flags & (SDHCI_USE_PLATDMA | SDHCI_USE_SDMA)) { - dma_unmap_sg(mmc_dev(host->mmc), data->sg, - data->sg_len, (data->flags & MMC_DATA_READ) ? - DMA_FROM_DEVICE : DMA_TO_DEVICE); -- } -+ } else if (host->flags & SDHCI_USE_ADMA) -+ sdhci_adma_table_post(host, data); - } - - /* -@@ -981,6 +984,12 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) - if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) - mask |= SDHCI_DATA_INHIBIT; - -+ if(host->ops->missing_status && (cmd->opcode == MMC_SEND_STATUS)) { -+ timeout = 5000; // Really obscenely large delay to send the status, due to bug in controller -+ // which might cause the STATUS command to get stuck when a data operation is in flow -+ mask |= SDHCI_DATA_INHIBIT; -+ } -+ - /* We shouldn't wait for data inihibit for stop commands, even - though they might use busy signaling */ - if (host->mrq->data && (cmd == host->mrq->data->stop)) -@@ -998,6 +1007,8 @@ void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) - timeout--; - mdelay(1); - } -+ DBG("send cmd %d - wait 0x%X irq 0x%x\n", cmd->opcode, mask, -+ sdhci_readl(host, SDHCI_INT_STATUS)); - - timeout = jiffies; - if (!cmd->data && cmd->busy_timeout > 9000) -@@ -2205,10 +2216,13 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) - BUG_ON(intmask == 0); - - if (!host->cmd) { -+ if (!(host->ops->extra_ints)) { - pr_err("%s: Got command interrupt 0x%08x even " - "though no command operation was in progress.\n", - mmc_hostname(host->mmc), (unsigned)intmask); - sdhci_dumpregs(host); -+ } else -+ DBG("cmd irq 0x%08x cmd complete\n", (unsigned)intmask); - return; - } - -@@ -2278,6 +2292,19 @@ static void sdhci_show_adma_error(struct sdhci_host *host) - static void sdhci_show_adma_error(struct sdhci_host *host) { } - #endif - -+static void sdhci_data_end(struct sdhci_host *host) -+{ -+ if (host->cmd) { -+ /* -+ * Data managed to finish before the -+ * command completed. Make sure we do -+ * things in the proper order. -+ */ -+ host->data_early = 1; -+ } else -+ sdhci_finish_data(host); -+} -+ - static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) - { - u32 command; -@@ -2307,10 +2334,13 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) - } - } - -+ if (!(host->ops->extra_ints)) { - pr_err("%s: Got data interrupt 0x%08x even " - "though no data operation was in progress.\n", - mmc_hostname(host->mmc), (unsigned)intmask); - sdhci_dumpregs(host); -+ } else -+ DBG("data irq 0x%08x but no data\n", (unsigned)intmask); - - return; - } -@@ -2334,8 +2364,14 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) - if (host->data->error) - sdhci_finish_data(host); - else { -- if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) -- sdhci_transfer_pio(host); -+ if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { -+ if (host->flags & SDHCI_REQ_USE_DMA) { -+ /* possible only in PLATDMA mode */ -+ sdhci_platdma_avail(host, &intmask, -+ &sdhci_data_end); -+ } else -+ sdhci_transfer_pio(host, intmask); -+ } - - /* - * We currently don't do anything fancy with DMA -@@ -2364,18 +2400,8 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) - sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); - } - -- if (intmask & SDHCI_INT_DATA_END) { -- if (host->cmd) { -- /* -- * Data managed to finish before the -- * command completed. Make sure we do -- * things in the proper order. -- */ -- host->data_early = 1; -- } else { -- sdhci_finish_data(host); -- } -- } -+ if (intmask & SDHCI_INT_DATA_END) -+ sdhci_data_end(host); - } - } - -@@ -2438,6 +2464,22 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id) - result = IRQ_WAKE_THREAD; - } - -+ if (intmask & SDHCI_INT_ERROR_MASK & ~SDHCI_INT_ERROR) -+ DBG("controller reports error 0x%x -" -+ "%s%s%s%s%s%s%s%s%s%s", -+ intmask, -+ intmask & SDHCI_INT_TIMEOUT? " timeout": "", -+ intmask & SDHCI_INT_CRC ? " crc": "", -+ intmask & SDHCI_INT_END_BIT? " endbit": "", -+ intmask & SDHCI_INT_INDEX? " index": "", -+ intmask & SDHCI_INT_DATA_TIMEOUT? " data_timeout": "", -+ intmask & SDHCI_INT_DATA_CRC? " data_crc": "", -+ intmask & SDHCI_INT_DATA_END_BIT? " data_endbit": "", -+ intmask & SDHCI_INT_BUS_POWER? " buspower": "", -+ intmask & SDHCI_INT_ACMD12ERR? " acmd12": "", -+ intmask & SDHCI_INT_ADMA_ERROR? " adma": "" -+ ); -+ - if (intmask & SDHCI_INT_CMD_MASK) - sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); - -@@ -2459,6 +2501,14 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id) - SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | - SDHCI_INT_CARD_INT); - -+ if (intmask & SDHCI_INT_ERROR_MASK) { -+ /* collect any uncovered errors */ -+ sdhci_writel(host, intmask & SDHCI_INT_ERROR_MASK, -+ SDHCI_INT_STATUS); -+ } -+ -+ intmask &= ~SDHCI_INT_ERROR_MASK; -+ - if (intmask) { - unexpected |= intmask; - sdhci_writel(host, intmask, SDHCI_INT_STATUS); -@@ -2571,7 +2621,8 @@ int sdhci_resume_host(struct sdhci_host *host) - { - int ret = 0; - -- if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { -+ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA | -+ SDHCI_USE_PLATDMA)) { - if (host->ops->enable_dma) - host->ops->enable_dma(host); - } -@@ -2802,14 +2853,16 @@ int sdhci_add_host(struct sdhci_host *host) - host->flags &= ~SDHCI_USE_ADMA; - } - -- if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { -+ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA | -+ SDHCI_USE_PLATDMA)) { - if (host->ops->enable_dma) { - if (host->ops->enable_dma(host)) { - pr_warning("%s: No suitable DMA " - "available. Falling back to PIO.\n", - mmc_hostname(mmc)); - host->flags &= -- ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); -+ ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA | -+ SDHCI_USE_PLATDMA); - } - } - } -@@ -3249,6 +3302,7 @@ int sdhci_add_host(struct sdhci_host *host) - - pr_info("%s: SDHCI controller on %s [%s] using %s\n", - mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), -+ (host->flags & SDHCI_USE_PLATDMA) ? "platform's DMA" : - (host->flags & SDHCI_USE_ADMA) ? "ADMA" : - (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); - -diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h -index 4a5cd5e..ffa4175 100644 ---- a/drivers/mmc/host/sdhci.h -+++ b/drivers/mmc/host/sdhci.h -@@ -288,6 +288,17 @@ struct sdhci_ops { - void (*reset)(struct sdhci_host *host, u8 mask); - int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode); - void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); -+ -+ int (*pdma_able)(struct sdhci_host *host, -+ struct mmc_data *data); -+ void (*pdma_avail)(struct sdhci_host *host, -+ unsigned int *ref_intmask, -+ void(*complete)(struct sdhci_host *)); -+ void (*pdma_reset)(struct sdhci_host *host, -+ struct mmc_data *data); -+ unsigned int (*extra_ints)(struct sdhci_host *host); -+ unsigned int (*missing_status)(struct sdhci_host *host); -+ - void (*hw_reset)(struct sdhci_host *host); - void (*adma_workaround)(struct sdhci_host *host, u32 intmask); - void (*platform_init)(struct sdhci_host *host); -@@ -409,6 +420,29 @@ extern int sdhci_resume_host(struct sdhci_host *host); - extern void sdhci_enable_irq_wakeups(struct sdhci_host *host); - #endif - -+static inline int /*bool*/ -+sdhci_platdma_dmaable(struct sdhci_host *host, struct mmc_data *data) -+{ -+ if (host->ops->pdma_able) -+ return host->ops->pdma_able(host, data); -+ else -+ return 1; -+} -+static inline void -+sdhci_platdma_avail(struct sdhci_host *host, unsigned int *ref_intmask, -+ void(*completion_callback)(struct sdhci_host *)) -+{ -+ if (host->ops->pdma_avail) -+ host->ops->pdma_avail(host, ref_intmask, completion_callback); -+} -+ -+static inline void -+sdhci_platdma_reset(struct sdhci_host *host, struct mmc_data *data) -+{ -+ if (host->ops->pdma_reset) -+ host->ops->pdma_reset(host, data); -+} -+ - #ifdef CONFIG_PM_RUNTIME - extern int sdhci_runtime_suspend_host(struct sdhci_host *host); - extern int sdhci_runtime_resume_host(struct sdhci_host *host); diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c -index 0e26dcb..adc0e47 100644 +index 8572f2a..4041738 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -84,7 +84,7 @@ struct vendor_data { @@ -8661,10 +5105,10 @@ index 7960424..b82f5cd 100644 mmc_pm_flag_t pm_caps; /* supported pm features */ diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h -index 08abe99..544da76 100644 +index 09ebe57..582ce64 100644 --- a/include/linux/mmc/sdhci.h +++ b/include/linux/mmc/sdhci.h -@@ -131,6 +131,7 @@ struct sdhci_host { +@@ -128,6 +128,7 @@ struct sdhci_host { #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ #define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */ #define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */ @@ -8673,10 +5117,572 @@ index 08abe99..544da76 100644 unsigned int version; /* SDHCI spec. version */ -From 4cba41b92db49cf41fbc274e92684230d0c4df34 Mon Sep 17 00:00:00 2001 +From 19d789c43ab2b18b37ee9ea76d5100faf3a3673b Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Wed, 8 Oct 2014 18:50:05 +0100 +Subject: [PATCH 02/82] Add bcm2708_gpio driver + +Signed-off-by: popcornmix + +bcm2708: Add extension to configure internal pulls + +The bcm2708 gpio controller supports internal pulls to be used as pull-up, +pull-down or being entirely disabled. As it can be useful for a driver to +change the pull configuration from it's default pull-down state, add an +extension which allows configuring the pull per gpio. + +Signed-off-by: Julian Scheel +--- + arch/arm/mach-bcm2708/Kconfig | 8 + + arch/arm/mach-bcm2708/Makefile | 1 + + arch/arm/mach-bcm2708/bcm2708.c | 28 +++ + arch/arm/mach-bcm2708/bcm2708_gpio.c | 401 ++++++++++++++++++++++++++++++ + arch/arm/mach-bcm2708/include/mach/gpio.h | 17 ++ + include/linux/platform_data/bcm2708.h | 23 ++ + 6 files changed, 478 insertions(+) + create mode 100644 arch/arm/mach-bcm2708/bcm2708_gpio.c + create mode 100644 arch/arm/mach-bcm2708/include/mach/gpio.h + create mode 100644 include/linux/platform_data/bcm2708.h + +diff --git a/arch/arm/mach-bcm2708/Kconfig b/arch/arm/mach-bcm2708/Kconfig +index 1f11478..9355841 100644 +--- a/arch/arm/mach-bcm2708/Kconfig ++++ b/arch/arm/mach-bcm2708/Kconfig +@@ -9,6 +9,14 @@ config MACH_BCM2708 + help + Include support for the Broadcom(R) BCM2708 platform. + ++config BCM2708_GPIO ++ bool "BCM2708 gpio support" ++ depends on MACH_BCM2708 ++ select ARCH_REQUIRE_GPIOLIB ++ default y ++ help ++ Include support for the Broadcom(R) BCM2708 gpio. ++ + config BCM2708_VCMEM + bool "Videocore Memory" + depends on MACH_BCM2708 +diff --git a/arch/arm/mach-bcm2708/Makefile b/arch/arm/mach-bcm2708/Makefile +index c76f39bc..a722f3f 100644 +--- a/arch/arm/mach-bcm2708/Makefile ++++ b/arch/arm/mach-bcm2708/Makefile +@@ -3,4 +3,5 @@ + # + + obj-$(CONFIG_MACH_BCM2708) += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o ++obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o + obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o +diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c +index 9b4e709..7503649 100644 +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -331,6 +331,31 @@ static struct platform_device bcm2708_vcio_device = { + }, + }; + ++#ifdef CONFIG_BCM2708_GPIO ++#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" ++ ++static struct resource bcm2708_gpio_resources[] = { ++ [0] = { /* general purpose I/O */ ++ .start = GPIO_BASE, ++ .end = GPIO_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_gpio_device = { ++ .name = BCM_GPIO_DRIVER_NAME, ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_gpio_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_gpio_resources), ++ .dev = { ++ .dma_mask = &gpio_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++#endif ++ + static struct resource bcm2708_systemtimer_resources[] = { + [0] = { /* system timer access */ + .start = ST_BASE, +@@ -473,6 +498,9 @@ void __init bcm2708_init(void) + + bcm_register_device(&bcm2708_dmaman_device); + bcm_register_device(&bcm2708_vcio_device); ++#ifdef CONFIG_BCM2708_GPIO ++ bcm_register_device(&bcm2708_gpio_device); ++#endif + bcm_register_device(&bcm2708_systemtimer_device); + bcm_register_device(&bcm2708_fb_device); + bcm_register_device(&bcm2708_usb_device); +diff --git a/arch/arm/mach-bcm2708/bcm2708_gpio.c b/arch/arm/mach-bcm2708/bcm2708_gpio.c +new file mode 100644 +index 0000000..86cafa7 +--- /dev/null ++++ b/arch/arm/mach-bcm2708/bcm2708_gpio.c +@@ -0,0 +1,401 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" ++#define DRIVER_NAME BCM_GPIO_DRIVER_NAME ++#define BCM_GPIO_USE_IRQ 1 ++ ++#define GPIOFSEL(x) (0x00+(x)*4) ++#define GPIOSET(x) (0x1c+(x)*4) ++#define GPIOCLR(x) (0x28+(x)*4) ++#define GPIOLEV(x) (0x34+(x)*4) ++#define GPIOEDS(x) (0x40+(x)*4) ++#define GPIOREN(x) (0x4c+(x)*4) ++#define GPIOFEN(x) (0x58+(x)*4) ++#define GPIOHEN(x) (0x64+(x)*4) ++#define GPIOLEN(x) (0x70+(x)*4) ++#define GPIOAREN(x) (0x7c+(x)*4) ++#define GPIOAFEN(x) (0x88+(x)*4) ++#define GPIOUD(x) (0x94+(x)*4) ++#define GPIOUDCLK(x) (0x98+(x)*4) ++ ++enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT, ++ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4, ++ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1, ++ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3, ++}; ++ ++ /* Each of the two spinlocks protects a different set of hardware ++ * regiters and data structurs. This decouples the code of the IRQ from ++ * the GPIO code. This also makes the case of a GPIO routine call from ++ * the IRQ code simpler. ++ */ ++static DEFINE_SPINLOCK(lock); /* GPIO registers */ ++ ++struct bcm2708_gpio { ++ struct list_head list; ++ void __iomem *base; ++ struct gpio_chip gc; ++ unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32]; ++ unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32]; ++ unsigned long high[(BCM2708_NR_GPIOS + 31) / 32]; ++ unsigned long low[(BCM2708_NR_GPIOS + 31) / 32]; ++}; ++ ++static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset, ++ int function) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned long flags; ++ unsigned gpiodir; ++ unsigned gpio_bank = offset / 10; ++ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; ++ ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function); ++ if (offset >= BCM2708_NR_GPIOS) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&lock, flags); ++ ++ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); ++ gpiodir &= ~(7 << gpio_field_offset); ++ gpiodir |= function << gpio_field_offset; ++ writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank)); ++ spin_unlock_irqrestore(&lock, flags); ++ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); ++ ++ return 0; ++} ++ ++static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset) ++{ ++ return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT); ++} ++ ++static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value); ++static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset, ++ int value) ++{ ++ int ret; ++ ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT); ++ if (ret >= 0) ++ bcm2708_gpio_set(gc, offset, value); ++ return ret; ++} ++ ++static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++ unsigned lev; ++ ++ if (offset >= BCM2708_NR_GPIOS) ++ return 0; ++ lev = readl(gpio->base + GPIOLEV(gpio_bank)); ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset)); ++ return 0x1 & (lev >> gpio_field_offset); ++} ++ ++static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value); ++ if (offset >= BCM2708_NR_GPIOS) ++ return; ++ if (value) ++ writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank)); ++ else ++ writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank)); ++} ++ ++/********************** ++ * extension to configure pullups ++ */ ++int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset, ++ bcm2708_gpio_pull_t value) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++ ++ if (offset >= BCM2708_NR_GPIOS) ++ return -EINVAL; ++ ++ switch (value) { ++ case BCM2708_PULL_UP: ++ writel(2, gpio->base + GPIOUD(0)); ++ break; ++ case BCM2708_PULL_DOWN: ++ writel(1, gpio->base + GPIOUD(0)); ++ break; ++ case BCM2708_PULL_OFF: ++ writel(0, gpio->base + GPIOUD(0)); ++ break; ++ } ++ ++ udelay(5); ++ writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank)); ++ udelay(5); ++ writel(0, gpio->base + GPIOUD(0)); ++ writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank)); ++ ++ return 0; ++} ++EXPORT_SYMBOL(bcm2708_gpio_setpull); ++ ++/************************************************************************************************************************* ++ * bcm2708 GPIO IRQ ++ */ ++ ++#if BCM_GPIO_USE_IRQ ++ ++static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) ++{ ++ return gpio_to_irq(gpio); ++} ++ ++static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type) ++{ ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = irq_to_gpio(irq); ++ unsigned gb = gn / 32; ++ unsigned go = gn % 32; ++ ++ gpio->rising[gb] &= ~(1 << go); ++ gpio->falling[gb] &= ~(1 << go); ++ gpio->high[gb] &= ~(1 << go); ++ gpio->low[gb] &= ~(1 << go); ++ ++ if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) ++ return -EINVAL; ++ ++ if (type & IRQ_TYPE_EDGE_RISING) ++ gpio->rising[gb] |= (1 << go); ++ if (type & IRQ_TYPE_EDGE_FALLING) ++ gpio->falling[gb] |= (1 << go); ++ if (type & IRQ_TYPE_LEVEL_HIGH) ++ gpio->high[gb] |= (1 << go); ++ if (type & IRQ_TYPE_LEVEL_LOW) ++ gpio->low[gb] |= (1 << go); ++ return 0; ++} ++ ++static void bcm2708_gpio_irq_mask(struct irq_data *d) ++{ ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = irq_to_gpio(irq); ++ unsigned gb = gn / 32; ++ unsigned long rising = readl(gpio->base + GPIOREN(gb)); ++ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); ++ unsigned long high = readl(gpio->base + GPIOHEN(gb)); ++ unsigned long low = readl(gpio->base + GPIOLEN(gb)); ++ ++ gn = gn % 32; ++ ++ writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb)); ++ writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb)); ++ writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb)); ++ writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb)); ++} ++ ++static void bcm2708_gpio_irq_unmask(struct irq_data *d) ++{ ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = irq_to_gpio(irq); ++ unsigned gb = gn / 32; ++ unsigned go = gn % 32; ++ unsigned long rising = readl(gpio->base + GPIOREN(gb)); ++ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); ++ unsigned long high = readl(gpio->base + GPIOHEN(gb)); ++ unsigned long low = readl(gpio->base + GPIOLEN(gb)); ++ ++ writel(1 << go, gpio->base + GPIOEDS(gb)); ++ ++ if (gpio->rising[gb] & (1 << go)) { ++ writel(rising | (1 << go), gpio->base + GPIOREN(gb)); ++ } else { ++ writel(rising & ~(1 << go), gpio->base + GPIOREN(gb)); ++ } ++ ++ if (gpio->falling[gb] & (1 << go)) { ++ writel(falling | (1 << go), gpio->base + GPIOFEN(gb)); ++ } else { ++ writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb)); ++ } ++ ++ if (gpio->high[gb] & (1 << go)) { ++ writel(high | (1 << go), gpio->base + GPIOHEN(gb)); ++ } else { ++ writel(high & ~(1 << go), gpio->base + GPIOHEN(gb)); ++ } ++ ++ if (gpio->low[gb] & (1 << go)) { ++ writel(low | (1 << go), gpio->base + GPIOLEN(gb)); ++ } else { ++ writel(low & ~(1 << go), gpio->base + GPIOLEN(gb)); ++ } ++} ++ ++static struct irq_chip bcm2708_irqchip = { ++ .name = "GPIO", ++ .irq_enable = bcm2708_gpio_irq_unmask, ++ .irq_disable = bcm2708_gpio_irq_mask, ++ .irq_unmask = bcm2708_gpio_irq_unmask, ++ .irq_mask = bcm2708_gpio_irq_mask, ++ .irq_set_type = bcm2708_gpio_irq_set_type, ++}; ++ ++static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id) ++{ ++ unsigned long edsr; ++ unsigned bank; ++ int i; ++ unsigned gpio; ++ for (bank = 0; bank <= 1; bank++) { ++ edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank)); ++ for_each_set_bit(i, &edsr, 32) { ++ gpio = i + bank * 32; ++ generic_handle_irq(gpio_to_irq(gpio)); ++ } ++ writel(0xffffffff, __io_address(GPIO_BASE) + GPIOEDS(bank)); ++ } ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction bcm2708_gpio_irq = { ++ .name = "BCM2708 GPIO catchall handler", ++ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, ++ .handler = bcm2708_gpio_interrupt, ++}; ++ ++static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb) ++{ ++ unsigned irq; ++ ++ ucb->gc.to_irq = bcm2708_gpio_to_irq; ++ ++ for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) { ++ irq_set_chip_data(irq, ucb); ++ irq_set_chip(irq, &bcm2708_irqchip); ++ set_irq_flags(irq, IRQF_VALID); ++ } ++ setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq); ++} ++ ++#else ++ ++static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb) ++{ ++} ++ ++#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */ ++ ++static int bcm2708_gpio_probe(struct platform_device *dev) ++{ ++ struct bcm2708_gpio *ucb; ++ struct resource *res; ++ int err = 0; ++ ++ printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev); ++ ++ ucb = kzalloc(sizeof(*ucb), GFP_KERNEL); ++ if (NULL == ucb) { ++ printk(KERN_ERR DRIVER_NAME ": failed to allocate " ++ "mailbox memory\n"); ++ err = -ENOMEM; ++ goto err; ++ } ++ ++ res = platform_get_resource(dev, IORESOURCE_MEM, 0); ++ ++ platform_set_drvdata(dev, ucb); ++ ucb->base = __io_address(GPIO_BASE); ++ ++ ucb->gc.label = "bcm2708_gpio"; ++ ucb->gc.base = 0; ++ ucb->gc.ngpio = BCM2708_NR_GPIOS; ++ ucb->gc.owner = THIS_MODULE; ++ ++ ucb->gc.direction_input = bcm2708_gpio_dir_in; ++ ucb->gc.direction_output = bcm2708_gpio_dir_out; ++ ucb->gc.get = bcm2708_gpio_get; ++ ucb->gc.set = bcm2708_gpio_set; ++ ucb->gc.can_sleep = 0; ++ ++ bcm2708_gpio_irq_init(ucb); ++ ++ err = gpiochip_add(&ucb->gc); ++ if (err) ++ goto err; ++ ++err: ++ return err; ++ ++} ++ ++static int bcm2708_gpio_remove(struct platform_device *dev) ++{ ++ int err = 0; ++ struct bcm2708_gpio *ucb = platform_get_drvdata(dev); ++ ++ printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev); ++ ++ err = gpiochip_remove(&ucb->gc); ++ ++ platform_set_drvdata(dev, NULL); ++ kfree(ucb); ++ ++ return err; ++} ++ ++static struct platform_driver bcm2708_gpio_driver = { ++ .probe = bcm2708_gpio_probe, ++ .remove = bcm2708_gpio_remove, ++ .driver = { ++ .name = "bcm2708_gpio"}, ++}; ++ ++static int __init bcm2708_gpio_init(void) ++{ ++ return platform_driver_register(&bcm2708_gpio_driver); ++} ++ ++static void __exit bcm2708_gpio_exit(void) ++{ ++ platform_driver_unregister(&bcm2708_gpio_driver); ++} ++ ++module_init(bcm2708_gpio_init); ++module_exit(bcm2708_gpio_exit); ++ ++MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver"); ++MODULE_LICENSE("GPL"); +diff --git a/arch/arm/mach-bcm2708/include/mach/gpio.h b/arch/arm/mach-bcm2708/include/mach/gpio.h +new file mode 100644 +index 0000000..7965a97 +--- /dev/null ++++ b/arch/arm/mach-bcm2708/include/mach/gpio.h +@@ -0,0 +1,17 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/gpio.h ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++#ifndef __ASM_ARCH_GPIO_H ++#define __ASM_ARCH_GPIO_H ++ ++#define BCM2708_NR_GPIOS 54 // number of gpio lines ++ ++#define gpio_to_irq(x) ((x) + GPIO_IRQ_START) ++#define irq_to_gpio(x) ((x) - GPIO_IRQ_START) ++ ++#endif +diff --git a/include/linux/platform_data/bcm2708.h b/include/linux/platform_data/bcm2708.h +new file mode 100644 +index 0000000..fb69624 +--- /dev/null ++++ b/include/linux/platform_data/bcm2708.h +@@ -0,0 +1,23 @@ ++/* ++ * include/linux/platform_data/bcm2708.h ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * (C) 2014 Julian Scheel ++ * ++ */ ++#ifndef __BCM2708_H_ ++#define __BCM2708_H_ ++ ++typedef enum { ++ BCM2708_PULL_OFF, ++ BCM2708_PULL_UP, ++ BCM2708_PULL_DOWN ++} bcm2708_gpio_pull_t; ++ ++extern int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset, ++ bcm2708_gpio_pull_t value); ++ ++#endif + +From 60215ba646e6b3b2cdc9d61b283de53cf96b3358 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 7 May 2013 22:20:24 +0100 -Subject: [PATCH 02/94] Add quick config. +Subject: [PATCH 03/82] Add quick config. This is designed for quick compiling when developing. No modules are needed and it includes all Pi specific drivers @@ -8889,12 +5895,20 @@ index 0000000..e5efe75 +CONFIG_CRC_ITU_T=y +CONFIG_LIBCRC32C=y -From a21b1e9ada71dcdfb8bb069fd7ef6691b75b4b3a Mon Sep 17 00:00:00 2001 +From d6ed20c144ed3a83747f2bc27130a8f74b91ffe9 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 1 May 2013 19:46:17 +0100 -Subject: [PATCH 03/94] Add dwc_otg driver +Subject: [PATCH 04/82] Add dwc_otg driver Signed-off-by: popcornmix + +usb: dwc: fix lockdep false positive + +Signed-off-by: Kari Suvanto + +usb: dwc: fix inconsistent lock state + +Signed-off-by: Kari Suvanto --- drivers/usb/Makefile | 1 + drivers/usb/core/generic.c | 1 + @@ -8911,7 +5925,7 @@ Signed-off-by: popcornmix drivers/usb/host/dwc_common_port/dwc_cc.c | 532 ++ drivers/usb/host/dwc_common_port/dwc_cc.h | 224 + drivers/usb/host/dwc_common_port/dwc_common_fbsd.c | 1308 ++++ - .../usb/host/dwc_common_port/dwc_common_linux.c | 1421 ++++ + .../usb/host/dwc_common_port/dwc_common_linux.c | 1429 ++++ drivers/usb/host/dwc_common_port/dwc_common_nbsd.c | 1275 ++++ drivers/usb/host/dwc_common_port/dwc_crypto.c | 308 + drivers/usb/host/dwc_common_port/dwc_crypto.h | 111 + @@ -8923,7 +5937,7 @@ Signed-off-by: popcornmix drivers/usb/host/dwc_common_port/dwc_modpow.h | 34 + drivers/usb/host/dwc_common_port/dwc_notifier.c | 319 + drivers/usb/host/dwc_common_port/dwc_notifier.h | 122 + - drivers/usb/host/dwc_common_port/dwc_os.h | 1260 ++++ + drivers/usb/host/dwc_common_port/dwc_os.h | 1274 ++++ drivers/usb/host/dwc_common_port/usb.h | 946 +++ drivers/usb/host/dwc_otg/Makefile | 80 + drivers/usb/host/dwc_otg/doc/doxygen.cfg | 224 + @@ -8942,15 +5956,15 @@ Signed-off-by: popcornmix drivers/usb/host/dwc_otg/dwc_otg_dbg.h | 116 + drivers/usb/host/dwc_otg/dwc_otg_driver.c | 1700 +++++ drivers/usb/host/dwc_otg/dwc_otg_driver.h | 86 + - drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 3473 ++++++++++ + drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 3479 ++++++++++ drivers/usb/host/dwc_otg/dwc_otg_hcd.h | 824 +++ drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c | 1133 ++++ drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h | 412 ++ drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 2106 ++++++ drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 893 +++ - drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c | 922 +++ + drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c | 923 +++ drivers/usb/host/dwc_otg/dwc_otg_os_dep.h | 185 + - drivers/usb/host/dwc_otg/dwc_otg_pcd.c | 2708 ++++++++ + drivers/usb/host/dwc_otg/dwc_otg_pcd.c | 2712 ++++++++ drivers/usb/host/dwc_otg/dwc_otg_pcd.h | 266 + drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h | 360 + drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c | 5147 ++++++++++++++ @@ -8960,7 +5974,7 @@ Signed-off-by: popcornmix drivers/usb/host/dwc_otg/test/dwc_otg_test.pm | 337 + drivers/usb/host/dwc_otg/test/test_mod_param.pl | 133 + drivers/usb/host/dwc_otg/test/test_sysfs.pl | 193 + - 64 files changed, 56440 insertions(+), 43 deletions(-) + 64 files changed, 56473 insertions(+), 43 deletions(-) create mode 100644 drivers/usb/gadget/file_storage.c create mode 100644 drivers/usb/host/dwc_common_port/Makefile create mode 100644 drivers/usb/host/dwc_common_port/Makefile.fbsd @@ -9021,7 +6035,7 @@ Signed-off-by: popcornmix create mode 100644 drivers/usb/host/dwc_otg/test/test_sysfs.pl diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile -index 3cba892..7aec507 100644 +index d7be717..f48b630 100644 --- a/drivers/usb/Makefile +++ b/drivers/usb/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_USB_U132_HCD) += host/ @@ -13031,10 +10045,10 @@ index 0000000..a896d73 +} +module_exit(fsg_cleanup); diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig -index 03314f8..16790e3 100644 +index 82800a7..5fb1bea 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig -@@ -713,6 +713,19 @@ config USB_HWA_HCD +@@ -721,6 +721,19 @@ config USB_HWA_HCD To compile this driver a module, choose M here: the module will be called "hwa-hc". @@ -13055,10 +10069,10 @@ index 03314f8..16790e3 100644 tristate "i.MX21 HCD support" depends on ARM && ARCH_MXC diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile -index af89a90..6e624e9 100644 +index 144c038..7672a59 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile -@@ -66,6 +66,8 @@ obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o +@@ -69,6 +69,8 @@ obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o @@ -15749,10 +12763,10 @@ index 0000000..6dd04b5 +} diff --git a/drivers/usb/host/dwc_common_port/dwc_common_linux.c b/drivers/usb/host/dwc_common_port/dwc_common_linux.c new file mode 100644 -index 0000000..440bcfc +index 0000000..1668f10 --- /dev/null +++ b/drivers/usb/host/dwc_common_port/dwc_common_linux.c -@@ -0,0 +1,1421 @@ +@@ -0,0 +1,1429 @@ +#include +#include +#include @@ -16515,7 +13529,11 @@ index 0000000..440bcfc + goto no_name; + } + ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) ++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(t->lock); ++#else + t->lock = DWC_SPINLOCK_ALLOC(); ++#endif + if (!t->lock) { + DWC_ERROR("Cannot allocate memory for lock"); + goto no_lock; @@ -16827,7 +13845,11 @@ index 0000000..440bcfc + + wq->pending = 0; + ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) ++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(wq->lock); ++#else + wq->lock = DWC_SPINLOCK_ALLOC(); ++#endif + if (!wq->lock) { + goto no_lock; + } @@ -21283,10 +18305,10 @@ index 0000000..4a8cdfe +#endif /* __DWC_NOTIFIER_H__ */ diff --git a/drivers/usb/host/dwc_common_port/dwc_os.h b/drivers/usb/host/dwc_common_port/dwc_os.h new file mode 100644 -index 0000000..9ffe929 +index 0000000..8117731 --- /dev/null +++ b/drivers/usb/host/dwc_common_port/dwc_os.h -@@ -0,0 +1,1260 @@ +@@ -0,0 +1,1274 @@ +/* ========================================================================= + * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_os.h $ + * $Revision: #14 $ @@ -21348,6 +18370,7 @@ index 0000000..9ffe929 +# ifdef CONFIG_DEBUG_MUTEXES +# include +# endif ++# include +# include +# include +#endif @@ -22326,9 +19349,22 @@ index 0000000..9ffe929 +/** Returns an initialized lock variable. This function should allocate and + * initialize the OS-specific data structure used for locking. This data + * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should -+ * be freed by the DWC_FREE_LOCK when it is no longer used. */ ++ * be freed by the DWC_FREE_LOCK when it is no longer used. ++ * ++ * For Linux Spinlock Debugging make it macro because the debugging routines use ++ * the symbol name to determine recursive locking. Using a wrapper function ++ * makes it falsely think recursive locking occurs. */ ++#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK) ++#define DWC_SPINLOCK_ALLOC_LINUX_DEBUG(lock) ({ \ ++ lock = DWC_ALLOC(sizeof(spinlock_t)); \ ++ if (lock) { \ ++ spin_lock_init((spinlock_t *)lock); \ ++ } \ ++}) ++#else +extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void); +#define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC() ++#endif + +/** Frees an initialized lock variable. */ +extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock); @@ -42838,10 +39874,10 @@ index 0000000..6a8be63 +#endif diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c new file mode 100644 -index 0000000..ab935c0 +index 0000000..1e89549 --- /dev/null +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -@@ -0,0 +1,3473 @@ +@@ -0,0 +1,3479 @@ + +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $ @@ -43688,7 +40724,13 @@ index 0000000..ab935c0 + int i; + dwc_hc_t *channel; + ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) ++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->lock); ++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->channel_lock); ++#else + hcd->lock = DWC_SPINLOCK_ALLOC(); ++ hcd->channel_lock = DWC_SPINLOCK_ALLOC(); ++#endif + DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n", + hcd, core_if); + if (!hcd->lock) { @@ -51715,10 +48757,10 @@ index 0000000..e4787f5 +#endif /* DWC_DEVICE_ONLY */ diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c new file mode 100644 -index 0000000..9761566 +index 0000000..0a1cbb7 --- /dev/null +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c -@@ -0,0 +1,922 @@ +@@ -0,0 +1,923 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $ + * $Revision: #44 $ @@ -51776,9 +48818,10 @@ index 0000000..9761566 +void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) +{ + dwc_otg_qtd_t *qtd, *qtd_tmp; ++ dwc_irqflags_t flags; + + /* Free each QTD in the QTD list */ -+ DWC_SPINLOCK(hcd->lock); ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) { + DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry); + dwc_otg_hcd_qtd_free(qtd); @@ -51797,7 +48840,7 @@ index 0000000..9761566 + } + + DWC_FREE(qh); -+ DWC_SPINUNLOCK(hcd->lock); ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); + return; +} + @@ -52834,10 +49877,10 @@ index 0000000..e46d9bb +#endif /* _DWC_OS_DEP_H_ */ diff --git a/drivers/usb/host/dwc_otg/dwc_otg_pcd.c b/drivers/usb/host/dwc_otg/dwc_otg_pcd.c new file mode 100644 -index 0000000..40fb25c +index 0000000..ae0c72d --- /dev/null +++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.c -@@ -0,0 +1,2708 @@ +@@ -0,0 +1,2712 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $ + * $Revision: #101 $ @@ -53960,7 +51003,11 @@ index 0000000..40fb25c + return NULL; + } + ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) ++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(pcd->lock); ++#else + pcd->lock = DWC_SPINLOCK_ALLOC(); ++#endif + DWC_DEBUGPL(DBG_HCDV, "Init of PCD %p given core_if %p\n", + pcd, core_if);//GRAYG + if (!pcd->lock) { @@ -65961,10 +63008,10 @@ index 0000000..cdc9963 +test_main(); +0; -From 60fec707423c59edf2d774f667c57f07e8ef8e92 Mon Sep 17 00:00:00 2001 +From 1409f72285e830413ddcb46ae8e8cacc5a5ca77d Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 1 May 2013 19:54:32 +0100 -Subject: [PATCH 04/94] bcm2708 watchdog driver +Subject: [PATCH 05/82] bcm2708 watchdog driver Signed-off-by: popcornmix --- @@ -65975,7 +63022,7 @@ Signed-off-by: popcornmix create mode 100644 drivers/watchdog/bcm2708_wdog.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig -index 76dd541..a29b6b4 100644 +index f57312f..c0eb247 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -413,6 +413,12 @@ config RETU_WATCHDOG @@ -66392,10 +63439,10 @@ index 0000000..8a27d68 +MODULE_ALIAS_MISCDEV(TEMP_MINOR); +MODULE_LICENSE("GPL"); -From 669ccd96ae050d4b9dac0b7fc06cd73bb2591b9d Mon Sep 17 00:00:00 2001 +From 292907b0937a222dd53ac17cdf3fb495d441536b Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 1 May 2013 19:55:09 +0100 -Subject: [PATCH 05/94] bcm2708 framebuffer driver +Subject: [PATCH 06/82] bcm2708 framebuffer driver Signed-off-by: popcornmix --- @@ -66407,7 +63454,7 @@ Signed-off-by: popcornmix create mode 100644 drivers/video/fbdev/bcm2708_fb.c diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig -index 59c98bfd..76c3235 100644 +index e911b9c..96a4d2b 100644 --- a/drivers/video/fbdev/Kconfig +++ b/drivers/video/fbdev/Kconfig @@ -220,6 +220,20 @@ config FB_TILEBLITTING @@ -66432,7 +63479,7 @@ index 59c98bfd..76c3235 100644 tristate "Aeroflex Gaisler framebuffer support" depends on FB && SPARC diff --git a/drivers/video/fbdev/Makefile b/drivers/video/fbdev/Makefile -index 0284f2a..13c0664 100644 +index 1979aff..57181ad 100644 --- a/drivers/video/fbdev/Makefile +++ b/drivers/video/fbdev/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_FB_MACMODES) += macmodes.o @@ -66442,7 +63489,7 @@ index 0284f2a..13c0664 100644 +obj-$(CONFIG_FB_BCM2708) += bcm2708_fb.o obj-$(CONFIG_FB_AMIGA) += amifb.o c2p_planar.o obj-$(CONFIG_FB_ARC) += arcfb.o - obj-$(CONFIG_FB_CLPS711X) += clps711xfb.o + obj-$(CONFIG_FB_CLPS711X) += clps711x-fb.o diff --git a/drivers/video/fbdev/bcm2708_fb.c b/drivers/video/fbdev/bcm2708_fb.c new file mode 100644 index 0000000..54cd760 @@ -69439,10 +66486,10 @@ index 3c14e43..7626beb 100644 +0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +0 0 0 0 0 0 0 0 0 -From 00039394d686f6b185294f2767ad5f94c0a936b1 Mon Sep 17 00:00:00 2001 +From f045a809d32f2a376e9520d61bffd0a607d79903 Mon Sep 17 00:00:00 2001 From: Harm Hanemaaijer Date: Thu, 20 Jun 2013 20:21:39 +0200 -Subject: [PATCH 06/94] Speed up console framebuffer imageblit function +Subject: [PATCH 07/82] Speed up console framebuffer imageblit function Especially on platforms with a slower CPU but a relatively high framebuffer fill bandwidth, like current ARM devices, the existing @@ -69651,10 +66698,10 @@ index a2bb276..436494f 100644 start_index, pitch_index); } else -From b84be90e342ab3f83163a862f92a604e33afd5c9 Mon Sep 17 00:00:00 2001 +From b517c335008c58056c0fc0693840b2906a4c6d10 Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Mon, 17 Jun 2013 13:32:11 +0300 -Subject: [PATCH 07/94] fbdev: add FBIOCOPYAREA ioctl +Subject: [PATCH 08/82] fbdev: add FBIOCOPYAREA ioctl Based on the patch authored by Ali Gholami Rudi at https://lkml.org/lkml/2009/7/13/153 @@ -69747,10 +66794,10 @@ index fb795c3..fa72af0 100644 #define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */ #define FB_TYPE_PLANES 1 /* Non interleaved planes */ -From 1c026d22590b4cd639158bb5dc522b4ff724a7e8 Mon Sep 17 00:00:00 2001 +From 81c3864101489fa5be7656d5ef19f5841a843b44 Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Mon, 17 Jun 2013 16:00:25 +0300 -Subject: [PATCH 08/94] bcm2708_fb: DMA acceleration for fb_copyarea +Subject: [PATCH 09/82] bcm2708_fb: DMA acceleration for fb_copyarea Based on http://www.raspberrypi.org/phpBB3/viewtopic.php?p=62425#p62425 Also used Simon's dmaer_master module as a reference for tweaking DMA @@ -69814,10 +66861,10 @@ index 51d147a..1da2413 100644 Does nothing if there is no DMA in progress. This routine waits for the current AXI transfer to complete before diff --git a/arch/arm/mach-bcm2708/include/mach/dma.h b/arch/arm/mach-bcm2708/include/mach/dma.h -index ac7a4a0..6d2f9a0 100644 +index f2568d4..a4aac4c 100644 --- a/arch/arm/mach-bcm2708/include/mach/dma.h +++ b/arch/arm/mach-bcm2708/include/mach/dma.h -@@ -62,11 +62,13 @@ struct bcm2708_dma_cb { +@@ -64,11 +64,13 @@ struct bcm2708_dma_cb { unsigned long next; unsigned long pad[2]; }; @@ -70234,10 +67281,10 @@ index 54cd760..b3b1e04 100644 return 0; -From 6862cfc59ee9a58cbe2c4d0858b9f581d5e5b4d5 Mon Sep 17 00:00:00 2001 +From 1de03fcd31d206282898620c182cfaa1751bd7c5 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 2 Jul 2013 23:42:01 +0100 -Subject: [PATCH 09/94] bcm2708 vchiq driver +Subject: [PATCH 10/82] bcm2708 vchiq driver Signed-off-by: popcornmix @@ -70252,6 +67299,23 @@ Signed-off-by: Daniel Stone vchiq: export additional symbols Signed-off-by: Daniel Stone + +VCHIQ: Make service closure fully synchronous (drv) + +This is one half of a two-part patch, the other half of which is to +the vchiq_lib user library. With these patches, calls to +vchiq_close_service and vchiq_remove_service won't return until any +associated callbacks have been delivered to the callback thread. + +VCHIQ: Add per-service tracing + +The new service option VCHIQ_SERVICE_OPTION_TRACE is a boolean that +toggles tracing for the specified service. + +This commit also introduces vchi_service_set_option and the associated +option VCHI_SERVICE_OPTION_TRACE. + +vchiq: Make the synchronous-CLOSE logic more tolerant --- drivers/misc/Kconfig | 1 + drivers/misc/Makefile | 1 + @@ -70259,34 +67323,34 @@ Signed-off-by: Daniel Stone drivers/misc/vc04_services/Makefile | 17 + .../interface/vchi/connections/connection.h | 328 ++ .../interface/vchi/message_drivers/message.h | 204 ++ - drivers/misc/vc04_services/interface/vchi/vchi.h | 373 ++ + drivers/misc/vc04_services/interface/vchi/vchi.h | 378 ++ .../misc/vc04_services/interface/vchi/vchi_cfg.h | 224 ++ .../interface/vchi/vchi_cfg_internal.h | 71 + - .../vc04_services/interface/vchi/vchi_common.h | 163 + + .../vc04_services/interface/vchi/vchi_common.h | 174 + .../misc/vc04_services/interface/vchi/vchi_mh.h | 42 + .../misc/vc04_services/interface/vchiq_arm/vchiq.h | 40 + .../vc04_services/interface/vchiq_arm/vchiq_2835.h | 42 + .../interface/vchiq_arm/vchiq_2835_arm.c | 561 +++ - .../vc04_services/interface/vchiq_arm/vchiq_arm.c | 2813 ++++++++++++++ + .../vc04_services/interface/vchiq_arm/vchiq_arm.c | 2907 +++++++++++++++ .../vc04_services/interface/vchiq_arm/vchiq_arm.h | 212 ++ .../interface/vchiq_arm/vchiq_build_info.h | 37 + - .../vc04_services/interface/vchiq_arm/vchiq_cfg.h | 60 + + .../vc04_services/interface/vchiq_arm/vchiq_cfg.h | 66 + .../interface/vchiq_arm/vchiq_connected.c | 119 + .../interface/vchiq_arm/vchiq_connected.h | 50 + - .../vc04_services/interface/vchiq_arm/vchiq_core.c | 3824 ++++++++++++++++++++ - .../vc04_services/interface/vchiq_arm/vchiq_core.h | 706 ++++ + .../vc04_services/interface/vchiq_arm/vchiq_core.c | 3859 ++++++++++++++++++++ + .../vc04_services/interface/vchiq_arm/vchiq_core.h | 711 ++++ .../interface/vchiq_arm/vchiq_genversion | 87 + - .../vc04_services/interface/vchiq_arm/vchiq_if.h | 188 + - .../interface/vchiq_arm/vchiq_ioctl.h | 129 + + .../vc04_services/interface/vchiq_arm/vchiq_if.h | 189 + + .../interface/vchiq_arm/vchiq_ioctl.h | 131 + .../interface/vchiq_arm/vchiq_kern_lib.c | 456 +++ .../interface/vchiq_arm/vchiq_memdrv.h | 71 + .../interface/vchiq_arm/vchiq_pagelist.h | 58 + .../vc04_services/interface/vchiq_arm/vchiq_proc.c | 253 ++ - .../vc04_services/interface/vchiq_arm/vchiq_shim.c | 828 +++++ + .../vc04_services/interface/vchiq_arm/vchiq_shim.c | 853 +++++ .../vc04_services/interface/vchiq_arm/vchiq_util.c | 151 + .../vc04_services/interface/vchiq_arm/vchiq_util.h | 81 + .../interface/vchiq_arm/vchiq_version.c | 59 + - 33 files changed, 12258 insertions(+) + 33 files changed, 12442 insertions(+) create mode 100644 drivers/misc/vc04_services/Kconfig create mode 100644 drivers/misc/vc04_services/Makefile create mode 100644 drivers/misc/vc04_services/interface/vchi/connections/connection.h @@ -70320,10 +67384,10 @@ Signed-off-by: Daniel Stone create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig -index ee94023..be9232c 100644 +index b841180..526082a 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig -@@ -534,6 +534,7 @@ source "drivers/misc/carma/Kconfig" +@@ -524,6 +524,7 @@ source "drivers/misc/carma/Kconfig" source "drivers/misc/altera-stapl/Kconfig" source "drivers/misc/mei/Kconfig" source "drivers/misc/vmw_vmci/Kconfig" @@ -70332,10 +67396,10 @@ index ee94023..be9232c 100644 source "drivers/misc/genwqe/Kconfig" source "drivers/misc/echo/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile -index d59ce12..95f2e53 100644 +index 5497d02..99defa0 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile -@@ -52,6 +52,7 @@ obj-$(CONFIG_INTEL_MEI) += mei/ +@@ -51,6 +51,7 @@ obj-$(CONFIG_INTEL_MEI) += mei/ obj-$(CONFIG_VMWARE_VMCI) += vmw_vmci/ obj-$(CONFIG_LATTICE_ECP3_CONFIG) += lattice-ecp3-config.o obj-$(CONFIG_SRAM) += sram.o @@ -70927,10 +67991,10 @@ index 0000000..8b3f767 +/****************************** End of file ***********************************/ diff --git a/drivers/misc/vc04_services/interface/vchi/vchi.h b/drivers/misc/vc04_services/interface/vchi/vchi.h new file mode 100644 -index 0000000..cee5291 +index 0000000..1b17e98 --- /dev/null +++ b/drivers/misc/vc04_services/interface/vchi/vchi.h -@@ -0,0 +1,373 @@ +@@ -0,0 +1,378 @@ +/** + * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * @@ -71153,7 +68217,12 @@ index 0000000..cee5291 +// Routine to decrement ref count on a named service +extern int32_t vchi_service_release( const VCHI_SERVICE_HANDLE_T handle ); + -+// Routine to send a message accross a service ++// Routine to set a control option for a named service ++extern int32_t vchi_service_set_option( const VCHI_SERVICE_HANDLE_T handle, ++ VCHI_SERVICE_OPTION_T option, ++ int value); ++ ++// Routine to send a message across a service +extern int32_t vchi_msg_queue( VCHI_SERVICE_HANDLE_T handle, + const void *data, + uint32_t data_size, @@ -71613,10 +68682,10 @@ index 0000000..35dcba4 +#endif /*VCHI_CFG_INTERNAL_H_*/ diff --git a/drivers/misc/vc04_services/interface/vchi/vchi_common.h b/drivers/misc/vc04_services/interface/vchi/vchi_common.h new file mode 100644 -index 0000000..9e6c00e +index 0000000..d76118c --- /dev/null +++ b/drivers/misc/vc04_services/interface/vchi/vchi_common.h -@@ -0,0 +1,163 @@ +@@ -0,0 +1,174 @@ +/** + * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * @@ -71729,7 +68798,18 @@ index 0000000..9e6c00e + VCHI_CALLBACK_REASON_MAX +} VCHI_CALLBACK_REASON_T; + -+//Calback used by all services / bulk transfers ++// service control options ++typedef enum ++{ ++ VCHI_SERVICE_OPTION_MIN, ++ ++ VCHI_SERVICE_OPTION_TRACE, ++ ++ VCHI_SERVICE_OPTION_MAX ++} VCHI_SERVICE_OPTION_T; ++ ++ ++//Callback used by all services / bulk transfers +typedef void (*VCHI_CALLBACK_T)( void *callback_param, //my service local param + VCHI_CALLBACK_REASON_T reason, + void *handle ); //for transmitting msg's only @@ -72491,10 +69571,10 @@ index 0000000..b3bdaa2 +} diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c new file mode 100644 -index 0000000..c1fb8c3 +index 0000000..b7269909 --- /dev/null +++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c -@@ -0,0 +1,2813 @@ +@@ -0,0 +1,2907 @@ +/** + * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * @@ -72609,13 +69689,15 @@ index 0000000..c1fb8c3 + VCHIQ_SERVICE_T *service; + void *userdata; + VCHIQ_INSTANCE_T instance; -+ int is_vchi; -+ int dequeue_pending; ++ char is_vchi; ++ char dequeue_pending; ++ char close_pending; + int message_available_pos; + int msg_insert; + int msg_remove; + struct semaphore insert_event; + struct semaphore remove_event; ++ struct semaphore close_event; + VCHIQ_HEADER_T * msg_queue[MSG_QUEUE_SIZE]; +} USER_SERVICE_T; + @@ -72638,6 +69720,7 @@ index 0000000..c1fb8c3 + int closing; + int pid; + int mark; ++ int use_close_delivered; + + struct list_head bulk_waiter_list; + struct mutex bulk_waiter_list_mutex; @@ -72675,7 +69758,9 @@ index 0000000..c1fb8c3 + "USE_SERVICE", + "RELEASE_SERVICE", + "SET_SERVICE_OPTION", -+ "DUMP_PHYS_MEM" ++ "DUMP_PHYS_MEM", ++ "LIB_VERSION", ++ "CLOSE_DELIVERED" +}; + +vchiq_static_assert((sizeof(ioctl_names)/sizeof(ioctl_names[0])) == @@ -72727,10 +69812,13 @@ index 0000000..c1fb8c3 + completion->service_userdata = user_service->service; + completion->bulk_userdata = bulk_userdata; + -+ if (reason == VCHIQ_SERVICE_CLOSED) ++ if (reason == VCHIQ_SERVICE_CLOSED) { + /* Take an extra reference, to be held until + this CLOSED notification is delivered. */ + lock_service(user_service->service); ++ if (instance->use_close_delivered) ++ user_service->close_pending = 1; ++ } + + /* A write barrier is needed here to ensure that the entire completion + record is written out before the insert point. */ @@ -72777,10 +69865,10 @@ index 0000000..c1fb8c3 + return VCHIQ_SUCCESS; + + vchiq_log_trace(vchiq_arm_log_level, -+ "service_callback - service %lx(%d), reason %d, header %lx, " ++ "service_callback - service %lx(%d,%p), reason %d, header %lx, " + "instance %lx, bulk_userdata %lx", + (unsigned long)user_service, -+ service->localport, ++ service->localport, user_service->userdata, + reason, (unsigned long)header, + (unsigned long)instance, (unsigned long)bulk_userdata); + @@ -72867,10 +69955,31 @@ index 0000000..c1fb8c3 + +/**************************************************************************** +* ++* close_delivered ++* ++***************************************************************************/ ++static void close_delivered(USER_SERVICE_T *user_service) ++{ ++ vchiq_log_info(vchiq_arm_log_level, ++ "close_delivered(handle=%x)", ++ user_service->service->handle); ++ ++ if (user_service->close_pending) { ++ /* Allow the underlying service to be culled */ ++ unlock_service(user_service->service); ++ ++ /* Wake the user-thread blocked in close_ or remove_service */ ++ up(&user_service->close_event); ++ ++ user_service->close_pending = 0; ++ } ++} ++ ++/**************************************************************************** ++* +* vchiq_ioctl +* +***************************************************************************/ -+ +static long +vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ @@ -72981,14 +70090,16 @@ index 0000000..c1fb8c3 + user_service->service = service; + user_service->userdata = userdata; + user_service->instance = instance; -+ user_service->is_vchi = args.is_vchi; ++ user_service->is_vchi = (args.is_vchi != 0); + user_service->dequeue_pending = 0; ++ user_service->close_pending = 0; + user_service->message_available_pos = + instance->completion_remove - 1; + user_service->msg_insert = 0; + user_service->msg_remove = 0; + sema_init(&user_service->insert_event, 0); + sema_init(&user_service->remove_event, 0); ++ sema_init(&user_service->close_event, 0); + + if (args.is_open) { + status = vchiq_open_service_internal @@ -73022,8 +70133,24 @@ index 0000000..c1fb8c3 + VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; + + service = find_service_for_instance(instance, handle); -+ if (service != NULL) -+ status = vchiq_close_service(service->handle); ++ if (service != NULL) { ++ USER_SERVICE_T *user_service = ++ (USER_SERVICE_T *)service->base.userdata; ++ /* close_pending is false on first entry, and when the ++ wait in vchiq_close_service has been interrupted. */ ++ if (!user_service->close_pending) { ++ status = vchiq_close_service(service->handle); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ } ++ ++ /* close_pending is true once the underlying service ++ has been closed until the client library calls the ++ CLOSE_DELIVERED ioctl, signalling close_event. */ ++ if (user_service->close_pending && ++ down_interruptible(&user_service->close_event)) ++ status = VCHIQ_RETRY; ++ } + else + ret = -EINVAL; + } break; @@ -73032,8 +70159,24 @@ index 0000000..c1fb8c3 + VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; + + service = find_service_for_instance(instance, handle); -+ if (service != NULL) -+ status = vchiq_remove_service(service->handle); ++ if (service != NULL) { ++ USER_SERVICE_T *user_service = ++ (USER_SERVICE_T *)service->base.userdata; ++ /* close_pending is false on first entry, and when the ++ wait in vchiq_close_service has been interrupted. */ ++ if (!user_service->close_pending) { ++ status = vchiq_remove_service(service->handle); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ } ++ ++ /* close_pending is true once the underlying service ++ has been closed until the client library calls the ++ CLOSE_DELIVERED ioctl, signalling close_event. */ ++ if (user_service->close_pending && ++ down_interruptible(&user_service->close_event)) ++ status = VCHIQ_RETRY; ++ } + else + ret = -EINVAL; + } break; @@ -73300,8 +70443,9 @@ index 0000000..c1fb8c3 + completion->header = msgbuf; + } + -+ if (completion->reason == -+ VCHIQ_SERVICE_CLOSED) ++ if ((completion->reason == ++ VCHIQ_SERVICE_CLOSED) && ++ !instance->use_close_delivered) + unlock_service(service); + + if (copy_to_user((void __user *)( @@ -73479,6 +70623,28 @@ index 0000000..c1fb8c3 + dump_phys_mem(args.virt_addr, args.num_bytes); + } break; + ++ case VCHIQ_IOC_LIB_VERSION: { ++ unsigned int lib_version = (unsigned int)arg; ++ ++ if (lib_version < VCHIQ_VERSION_MIN) ++ ret = -EINVAL; ++ else if (lib_version >= VCHIQ_VERSION_CLOSE_DELIVERED) ++ instance->use_close_delivered = 1; ++ } break; ++ ++ case VCHIQ_IOC_CLOSE_DELIVERED: { ++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; ++ ++ service = find_closed_service_for_instance(instance, handle); ++ if (service != NULL) { ++ USER_SERVICE_T *user_service = ++ (USER_SERVICE_T *)service->base.userdata; ++ close_delivered(user_service); ++ } ++ else ++ ret = -EINVAL; ++ } break; ++ + default: + ret = -ENOTTY; + break; @@ -73666,7 +70832,15 @@ index 0000000..c1fb8c3 + (MAX_COMPLETIONS - 1)]; + service = completion->service_userdata; + if (completion->reason == VCHIQ_SERVICE_CLOSED) ++ { ++ USER_SERVICE_T *user_service = ++ service->base.userdata; ++ ++ /* Wake any blocked user-thread */ ++ if (instance->use_close_delivered) ++ up(&user_service->close_event); + unlock_service(service); ++ } + instance->completion_remove++; + } + @@ -75571,12 +72745,12 @@ index 0000000..df64581 +const char *vchiq_get_build_date(void); diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h new file mode 100644 -index 0000000..493c86c +index 0000000..c382740 --- /dev/null +++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h -@@ -0,0 +1,60 @@ +@@ -0,0 +1,66 @@ +/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * Copyright (c) 2010-2014 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions @@ -75613,11 +72787,17 @@ index 0000000..493c86c + +#define VCHIQ_MAGIC VCHIQ_MAKE_FOURCC('V', 'C', 'H', 'I') +/* The version of VCHIQ - change with any non-trivial change */ -+#define VCHIQ_VERSION 6 ++#define VCHIQ_VERSION 7 +/* The minimum compatible version - update to match VCHIQ_VERSION with any +** incompatible change */ +#define VCHIQ_VERSION_MIN 3 + ++/* The version that introduced the VCHIQ_IOC_LIB_VERSION ioctl */ ++#define VCHIQ_VERSION_LIB_VERSION 7 ++ ++/* The version that introduced the VCHIQ_IOC_CLOSE_DELIVERED ioctl */ ++#define VCHIQ_VERSION_CLOSE_DELIVERED 7 ++ +#define VCHIQ_MAX_STATES 1 +#define VCHIQ_MAX_SERVICES 4096 +#define VCHIQ_MAX_SLOTS 128 @@ -75818,10 +72998,10 @@ index 0000000..863b3e3 +#endif /* VCHIQ_CONNECTED_H */ diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c new file mode 100644 -index 0000000..f35ed4f +index 0000000..18887b1 --- /dev/null +++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c -@@ -0,0 +1,3824 @@ +@@ -0,0 +1,3859 @@ +/** + * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * @@ -75871,9 +73051,12 @@ index 0000000..f35ed4f +#define SLOT_QUEUE_INDEX_FROM_POS(pos) \ + ((int)((unsigned int)(pos) / VCHIQ_SLOT_SIZE)) + -+ +#define BULK_INDEX(x) (x & (VCHIQ_NUM_SERVICE_BULKS - 1)) + ++#define SRVTRACE_LEVEL(srv) \ ++ (((srv) && (srv)->trace) ? VCHIQ_LOG_TRACE : vchiq_core_msg_log_level) ++#define SRVTRACE_ENABLED(srv, lev) \ ++ (((srv) && (srv)->trace) || (vchiq_core_msg_log_level >= (lev))) + +struct vchiq_open_payload { + int fourcc; @@ -76047,6 +73230,31 @@ index 0000000..f35ed4f +} + +VCHIQ_SERVICE_T * ++find_closed_service_for_instance(VCHIQ_INSTANCE_T instance, ++ VCHIQ_SERVICE_HANDLE_T handle) { ++ VCHIQ_SERVICE_T *service; ++ ++ spin_lock(&service_spinlock); ++ service = handle_to_service(handle); ++ if (service && ++ ((service->srvstate == VCHIQ_SRVSTATE_FREE) || ++ (service->srvstate == VCHIQ_SRVSTATE_CLOSED)) && ++ (service->handle == handle) && ++ (service->instance == instance)) { ++ BUG_ON(service->ref_count == 0); ++ service->ref_count++; ++ } else ++ service = NULL; ++ spin_unlock(&service_spinlock); ++ ++ if (!service) ++ vchiq_log_info(vchiq_core_log_level, ++ "Invalid service handle 0x%x", handle); ++ ++ return service; ++} ++ ++VCHIQ_SERVICE_T * +next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance, + int *pidx) +{ @@ -76673,8 +73881,8 @@ index 0000000..f35ed4f + return VCHIQ_ERROR; + } + if (i == 0) { -+ if (vchiq_core_msg_log_level >= -+ VCHIQ_LOG_INFO) ++ if (SRVTRACE_ENABLED(service, ++ VCHIQ_LOG_INFO)) + vchiq_log_dump_mem("Sent", 0, + header->data + pos, + min(64u, @@ -76740,7 +73948,7 @@ index 0000000..f35ed4f + ? service->base.fourcc + : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); + -+ vchiq_log_info(vchiq_core_msg_log_level, ++ vchiq_log_info(SRVTRACE_LEVEL(service), + "Sent Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d", + msg_type_str(VCHIQ_MSG_TYPE(msgid)), + VCHIQ_MSG_TYPE(msgid), @@ -77132,11 +74340,11 @@ index 0000000..f35ed4f + vchiq_transfer_bulk(bulk); + mutex_unlock(&state->bulk_transfer_mutex); + -+ if (vchiq_core_msg_log_level >= VCHIQ_LOG_INFO) { ++ if (SRVTRACE_ENABLED(service, VCHIQ_LOG_INFO)) { + const char *header = (queue == &service->bulk_tx) ? + "Send Bulk to" : "Recv Bulk from"; + if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) -+ vchiq_log_info(vchiq_core_msg_log_level, ++ vchiq_log_info(SRVTRACE_LEVEL(service), + "%s %c%c%c%c d:%d len:%d %x<->%x", + header, + VCHIQ_FOURCC_AS_4CHARS( @@ -77146,7 +74354,7 @@ index 0000000..f35ed4f + (unsigned int)bulk->data, + (unsigned int)bulk->remote_data); + else -+ vchiq_log_info(vchiq_core_msg_log_level, ++ vchiq_log_info(SRVTRACE_LEVEL(service), + "%s %c%c%c%c d:%d ABORTED - tx len:%d," + " rx len:%d %x<->%x", + header, @@ -77193,7 +74401,7 @@ index 0000000..f35ed4f + if (queue->process != queue->local_insert) { + vchiq_complete_bulk(bulk); + -+ vchiq_log_info(vchiq_core_msg_log_level, ++ vchiq_log_info(SRVTRACE_LEVEL(service), + "%s %c%c%c%c d:%d ABORTED - tx len:%d, " + "rx len:%d", + is_tx ? "Send Bulk to" : "Recv Bulk from", @@ -77479,13 +74687,13 @@ index 0000000..f35ed4f + break; + } + -+ if (vchiq_core_msg_log_level >= VCHIQ_LOG_INFO) { ++ if (SRVTRACE_ENABLED(service, VCHIQ_LOG_INFO)) { + int svc_fourcc; + + svc_fourcc = service + ? service->base.fourcc + : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); -+ vchiq_log_info(vchiq_core_msg_log_level, ++ vchiq_log_info(SRVTRACE_LEVEL(service), + "Rcvd Msg %s(%u) from %c%c%c%c s:%d d:%d " + "len:%d", + msg_type_str(type), type, @@ -78327,6 +75535,7 @@ index 0000000..f35ed4f + service->auto_close = 1; + service->sync = 0; + service->closing = 0; ++ service->trace = 0; + atomic_set(&service->poll_flags, 0); + service->version = params->version; + service->version_min = params->version_min; @@ -78455,6 +75664,7 @@ index 0000000..f35ed4f + VCHIQ_MAKE_MSG(VCHIQ_MSG_OPEN, service->localport, 0), + &body, 1, sizeof(payload), 1); + if (status == VCHIQ_SUCCESS) { ++ /* Wait for the ACK/NAK */ + if (down_interruptible(&service->remove_event) != 0) { + status = VCHIQ_RETRY; + vchiq_release_service_internal(service); @@ -79336,6 +76546,11 @@ index 0000000..f35ed4f + } + break; + ++ case VCHIQ_SERVICE_OPTION_TRACE: ++ service->trace = value; ++ status = VCHIQ_SUCCESS; ++ break; ++ + default: + break; + } @@ -79648,10 +76863,10 @@ index 0000000..f35ed4f +} diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h new file mode 100644 -index 0000000..47cdf27 +index 0000000..1b27917 --- /dev/null +++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h -@@ -0,0 +1,706 @@ +@@ -0,0 +1,711 @@ +/** + * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * @@ -79948,6 +77163,7 @@ index 0000000..47cdf27 + char auto_close; + char sync; + char closing; ++ char trace; + atomic_t poll_flags; + short version; + short version_min; @@ -80259,6 +77475,10 @@ index 0000000..47cdf27 + VCHIQ_SERVICE_HANDLE_T handle); + +extern VCHIQ_SERVICE_T * ++find_closed_service_for_instance(VCHIQ_INSTANCE_T instance, ++ VCHIQ_SERVICE_HANDLE_T handle); ++ ++extern VCHIQ_SERVICE_T * +next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance, + int *pidx); + @@ -80453,10 +77673,10 @@ index 0000000..9f5b634 +EOF diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h new file mode 100644 -index 0000000..50359b0 +index 0000000..8067bbe --- /dev/null +++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h -@@ -0,0 +1,188 @@ +@@ -0,0 +1,189 @@ +/** + * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * @@ -80533,7 +77753,8 @@ index 0000000..50359b0 + VCHIQ_SERVICE_OPTION_AUTOCLOSE, + VCHIQ_SERVICE_OPTION_SLOT_QUOTA, + VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA, -+ VCHIQ_SERVICE_OPTION_SYNCHRONOUS ++ VCHIQ_SERVICE_OPTION_SYNCHRONOUS, ++ VCHIQ_SERVICE_OPTION_TRACE +} VCHIQ_SERVICE_OPTION_T; + +typedef struct vchiq_header_struct { @@ -80647,10 +77868,10 @@ index 0000000..50359b0 +#endif /* VCHIQ_IF_H */ diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h new file mode 100644 -index 0000000..e248037 +index 0000000..6137ae9 --- /dev/null +++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h -@@ -0,0 +1,129 @@ +@@ -0,0 +1,131 @@ +/** + * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * @@ -80777,7 +77998,9 @@ index 0000000..e248037 + _IOW(VCHIQ_IOC_MAGIC, 14, VCHIQ_SET_SERVICE_OPTION_T) +#define VCHIQ_IOC_DUMP_PHYS_MEM \ + _IOW(VCHIQ_IOC_MAGIC, 15, VCHIQ_DUMP_MEM_T) -+#define VCHIQ_IOC_MAX 15 ++#define VCHIQ_IOC_LIB_VERSION _IO(VCHIQ_IOC_MAGIC, 16) ++#define VCHIQ_IOC_CLOSE_DELIVERED _IO(VCHIQ_IOC_MAGIC, 17) ++#define VCHIQ_IOC_MAX 17 + +#endif diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c @@ -81644,10 +78867,10 @@ index 0000000..8e59676 +#endif diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c new file mode 100644 -index 0000000..a0b069d +index 0000000..72eacdaf --- /dev/null +++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c -@@ -0,0 +1,828 @@ +@@ -0,0 +1,853 @@ +/** + * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * @@ -82107,8 +79330,6 @@ index 0000000..a0b069d + * Name: vchi_initialise + * + * Arguments: VCHI_INSTANCE_T *instance_handle -+ * VCHI_CONNECTION_T **connections -+ * const uint32_t num_connections + * + * Description: Initialises the hardware but does not transmit anything + * When run as a Host App this will be called twice hence the need @@ -82375,6 +79596,33 @@ index 0000000..a0b069d +} +EXPORT_SYMBOL(vchi_service_destroy); + ++int32_t vchi_service_set_option(const VCHI_SERVICE_HANDLE_T handle, ++ VCHI_SERVICE_OPTION_T option, ++ int value) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_SERVICE_OPTION_T vchiq_option; ++ switch (option) { ++ case VCHI_SERVICE_OPTION_TRACE: ++ vchiq_option = VCHIQ_SERVICE_OPTION_TRACE; ++ break; ++ default: ++ service = NULL; ++ break; ++ } ++ if (service) { ++ VCHIQ_STATUS_T status = ++ vchiq_set_service_option(service->handle, ++ vchiq_option, ++ value); ++ ++ ret = vchiq_status_to_vchi(status); ++ } ++ return ret; ++} ++EXPORT_SYMBOL(vchi_service_set_option); ++ +int32_t vchi_get_peer_version( const VCHI_SERVICE_HANDLE_T handle, short *peer_version ) +{ + int32_t ret = -1; @@ -82786,10 +80034,10 @@ index 0000000..b6bfa21 + return vchiq_build_time; +} -From 56cf9d835d83750c3451c4ba4db78cb9c6391a67 Mon Sep 17 00:00:00 2001 +From b7c6aa3f2630514ebc7faa4adfd10cd0e01bf9cb Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 12 May 2014 15:12:02 +0100 -Subject: [PATCH 10/94] vchiq: Avoid high load when blocked and unkillable +Subject: [PATCH 11/82] vchiq: Avoid high load when blocked and unkillable vchiq: Include SIGSTOP and SIGCONT in list of signals not-masked by vchiq to allow gdb to work --- @@ -82816,7 +80064,7 @@ index b3bdaa2..7e7b09f 100644 #define MAX_FRAGMENTS (VCHIQ_NUM_CURRENT_BULKS * 2) diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c -index c1fb8c3..99c8967 100644 +index b7269909..98edf1b 100644 --- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c +++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c @@ -49,6 +49,7 @@ @@ -82840,7 +80088,7 @@ index 65f4b52..5efc62f 100644 #include diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c -index f35ed4f..71ed0a5 100644 +index 18887b1..b69b803 100644 --- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c +++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c @@ -32,6 +32,7 @@ @@ -82951,10 +80199,10 @@ index c2eefef..05e7979 100644 static inline int is_pow2(int i) { -From 7d423949a4dd497f206002e4cd7f5c70a16b0bf8 Mon Sep 17 00:00:00 2001 +From ea12a1f69fc4073a1b96a5cd8e9cb20df3a30626 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:31:47 +0100 -Subject: [PATCH 11/94] cma: Add vc_cma driver to enable use of CMA +Subject: [PATCH 12/82] cma: Add vc_cma driver to enable use of CMA Signed-off-by: popcornmix --- @@ -84195,10 +81443,10 @@ index 0000000..a635f9f +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Broadcom Corporation"); diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile -index 95f2e53..33916ff 100644 +index 99defa0..7b281b7 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile -@@ -52,7 +52,7 @@ obj-$(CONFIG_INTEL_MEI) += mei/ +@@ -51,7 +51,7 @@ obj-$(CONFIG_INTEL_MEI) += mei/ obj-$(CONFIG_VMWARE_VMCI) += vmw_vmci/ obj-$(CONFIG_LATTICE_ECP3_CONFIG) += lattice-ecp3-config.o obj-$(CONFIG_SRAM) += sram.o @@ -84243,10 +81491,10 @@ index 0000000..5325832 + +#endif /* VC_CMA_H */ -From d65c5ba4eca012f2e803ddc47eb45fd5ec44738a Mon Sep 17 00:00:00 2001 +From 0a880716a1d5c8c5c8bec5b961b1e83667e8cd8d Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 26 Mar 2012 22:15:50 +0100 -Subject: [PATCH 12/94] bcm2708: alsa sound driver +Subject: [PATCH 13/82] bcm2708: alsa sound driver Signed-off-by: popcornmix @@ -84267,7 +81515,6 @@ Avoids an issue when closing and opening vchiq where a message can arrive before alsa: reduce severity of expected warning message --- - arch/arm/configs/bcmrpi_cutdown_defconfig | 20 + arch/arm/configs/bcmrpi_defconfig | 20 + arch/arm/mach-bcm2708/bcm2708.c | 54 ++ .../interface/vchiq_arm/vchiq_kern_lib.c | 7 +- @@ -84280,7 +81527,7 @@ alsa: reduce severity of expected warning message sound/arm/bcm2835.c | 420 ++++++++++ sound/arm/bcm2835.h | 167 ++++ sound/arm/vc_vchi_audioserv_defs.h | 116 +++ - 13 files changed, 2593 insertions(+), 7 deletions(-) + 12 files changed, 2573 insertions(+), 7 deletions(-) create mode 100755 sound/arm/bcm2835-ctl.c create mode 100755 sound/arm/bcm2835-pcm.c create mode 100755 sound/arm/bcm2835-vchiq.c @@ -84288,42 +81535,11 @@ alsa: reduce severity of expected warning message create mode 100755 sound/arm/bcm2835.h create mode 100644 sound/arm/vc_vchi_audioserv_defs.h -diff --git a/arch/arm/configs/bcmrpi_cutdown_defconfig b/arch/arm/configs/bcmrpi_cutdown_defconfig -index 74f2dc9..e519412 100644 ---- a/arch/arm/configs/bcmrpi_cutdown_defconfig -+++ b/arch/arm/configs/bcmrpi_cutdown_defconfig -@@ -208,6 +208,26 @@ CONFIG_FRAMEBUFFER_CONSOLE=y - CONFIG_LOGO=y - # CONFIG_LOGO_LINUX_MONO is not set - # CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_SOUND=y -+CONFIG_SND=m -+CONFIG_SND_SEQUENCER=m -+CONFIG_SND_SEQ_DUMMY=m -+CONFIG_SND_MIXER_OSS=m -+CONFIG_SND_PCM_OSS=m -+CONFIG_SND_SEQUENCER_OSS=y -+CONFIG_SND_HRTIMER=m -+CONFIG_SND_DUMMY=m -+CONFIG_SND_ALOOP=m -+CONFIG_SND_VIRMIDI=m -+CONFIG_SND_MTPAV=m -+CONFIG_SND_SERIAL_U16550=m -+CONFIG_SND_MPU401=m -+CONFIG_SND_BCM2835=m -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_USB_UA101=m -+CONFIG_SND_USB_CAIAQ=m -+CONFIG_SND_USB_6FIRE=m -+CONFIG_SOUND_PRIME=m - CONFIG_HID_PID=y - CONFIG_USB_HIDDEV=y - CONFIG_HID_A4TECH=m diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 339aabf..df947e5 100644 +index 8950e53..63cb6a4 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -225,6 +225,26 @@ CONFIG_FRAMEBUFFER_CONSOLE=y +@@ -202,6 +202,26 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set @@ -84347,14 +81563,14 @@ index 339aabf..df947e5 100644 +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_6FIRE=m +CONFIG_SOUND_PRIME=m - CONFIG_HID_PID=y - CONFIG_USB_HIDDEV=y CONFIG_HID_A4TECH=m + CONFIG_HID_ACRUX=m + CONFIG_HID_APPLE=m diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 632023a..ab06b52 100644 +index 7503649..f3dccae 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -431,6 +431,58 @@ struct platform_device bcm2708_powerman_device = { +@@ -403,6 +403,58 @@ struct platform_device bcm2708_powerman_device = { .coherent_dma_mask = 0xffffffffUL}, }; @@ -84413,9 +81629,9 @@ index 632023a..ab06b52 100644 int __init bcm_register_device(struct platform_device *pdev) { int ret; -@@ -539,6 +591,8 @@ void __init bcm2708_init(void) - bcm_register_device(&bcm2708_emmc_device); - #endif +@@ -508,6 +560,8 @@ void __init bcm2708_init(void) + bcm_register_device(&bcm2708_powerman_device); + bcm2708_init_led(); + for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) + bcm_register_device(&bcm2708_alsa_devices[i]); @@ -84443,10 +81659,10 @@ index 5a4182e..25e7011 100644 failed: diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c -index a0b069d..bc27bea 100644 +index 72eacdaf..c26eff7 100644 --- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c +++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c -@@ -636,6 +636,9 @@ int32_t vchi_service_open(VCHI_INSTANCE_T instance_handle, +@@ -634,6 +634,9 @@ int32_t vchi_service_open(VCHI_INSTANCE_T instance_handle, { VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; SHIM_SERVICE_T *service = service_alloc(instance, setup); @@ -84456,7 +81672,7 @@ index a0b069d..bc27bea 100644 if (service) { VCHIQ_SERVICE_PARAMS_T params; VCHIQ_STATUS_T status; -@@ -652,11 +655,10 @@ int32_t vchi_service_open(VCHI_INSTANCE_T instance_handle, +@@ -650,11 +653,10 @@ int32_t vchi_service_open(VCHI_INSTANCE_T instance_handle, if (status != VCHIQ_SUCCESS) { service_free(service); service = NULL; @@ -84469,7 +81685,7 @@ index a0b069d..bc27bea 100644 return (service != NULL) ? 0 : -1; } EXPORT_SYMBOL(vchi_service_open); -@@ -667,6 +669,9 @@ int32_t vchi_service_create(VCHI_INSTANCE_T instance_handle, +@@ -665,6 +667,9 @@ int32_t vchi_service_create(VCHI_INSTANCE_T instance_handle, { VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; SHIM_SERVICE_T *service = service_alloc(instance, setup); @@ -84479,7 +81695,7 @@ index a0b069d..bc27bea 100644 if (service) { VCHIQ_SERVICE_PARAMS_T params; VCHIQ_STATUS_T status; -@@ -682,11 +687,10 @@ int32_t vchi_service_create(VCHI_INSTANCE_T instance_handle, +@@ -680,11 +685,10 @@ int32_t vchi_service_create(VCHI_INSTANCE_T instance_handle, if (status != VCHIQ_SUCCESS) { service_free(service); service = NULL; @@ -87034,31 +84250,18 @@ index 0000000..af3e6eb + +#endif // _VC_AUDIO_DEFS_H_ -From 68a4967c1eca9b0ce44c2319eaef468dfdfadd9e Mon Sep 17 00:00:00 2001 +From 659f372e3355bb4fc83920f9dcc559d9af7b2726 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:51:55 +0100 -Subject: [PATCH 13/94] Add hwrng (hardware random number generator) driver +Subject: [PATCH 14/82] Add hwrng (hardware random number generator) driver --- - arch/arm/mach-bcm2708/include/mach/platform.h | 1 + - drivers/char/hw_random/Kconfig | 11 +++ - drivers/char/hw_random/Makefile | 1 + - drivers/char/hw_random/bcm2708-rng.c | 118 ++++++++++++++++++++++++++ - 4 files changed, 131 insertions(+) + drivers/char/hw_random/Kconfig | 11 ++++ + drivers/char/hw_random/Makefile | 1 + + drivers/char/hw_random/bcm2708-rng.c | 118 +++++++++++++++++++++++++++++++++++ + 3 files changed, 130 insertions(+) create mode 100755 drivers/char/hw_random/bcm2708-rng.c -diff --git a/arch/arm/mach-bcm2708/include/mach/platform.h b/arch/arm/mach-bcm2708/include/mach/platform.h -index 110ce07..ecd854e 100644 ---- a/arch/arm/mach-bcm2708/include/mach/platform.h -+++ b/arch/arm/mach-bcm2708/include/mach/platform.h -@@ -60,6 +60,7 @@ - #define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */ - #define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */ - #define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */ -+#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */ - #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */ - #define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */ - #define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */ diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index 836b061..e6d1fd1 100644 --- a/drivers/char/hw_random/Kconfig @@ -87216,18 +84419,30 @@ index 0000000..340f004 +MODULE_DESCRIPTION("BCM2708 H/W Random Number Generator (RNG) driver"); +MODULE_LICENSE("GPL and additional rights"); -From 3bd26bded4ce506f3f4b52c40331c3ffa82ed2f7 Mon Sep 17 00:00:00 2001 +From c272b29e5e3d3c32d0c485be53d9d0840c8ef759 Mon Sep 17 00:00:00 2001 From: Aron Szabo Date: Sat, 16 Jun 2012 12:15:55 +0200 -Subject: [PATCH 14/94] lirc: added support for RaspberryPi GPIO +Subject: [PATCH 15/82] lirc: added support for RaspberryPi GPIO lirc_rpi: Use read_current_timer to determine transmitter delay. Thanks to jjmz and others See: https://github.com/raspberrypi/linux/issues/525 + +lirc: Remove restriction on gpio pins that can be used with lirc + +Compute Module, for example could use different pins + +lirc_rpi: Add parameter to specify input pin pull + +Depending on the connected IR circuitry it might be desirable to change the +gpios internal pull from it pull-down default behaviour. Add a module +parameter to allow the user to set it explicitly. + +Signed-off-by: Julian Scheel --- drivers/staging/media/lirc/Kconfig | 6 + drivers/staging/media/lirc/Makefile | 1 + - drivers/staging/media/lirc/lirc_rpi.c | 695 ++++++++++++++++++++++++++++++++++ - 3 files changed, 702 insertions(+) + drivers/staging/media/lirc/lirc_rpi.c | 689 ++++++++++++++++++++++++++++++++++ + 3 files changed, 696 insertions(+) create mode 100644 drivers/staging/media/lirc/lirc_rpi.c diff --git a/drivers/staging/media/lirc/Kconfig b/drivers/staging/media/lirc/Kconfig @@ -87261,10 +84476,10 @@ index b90fcab..2b227fd 100644 obj-$(CONFIG_LIRC_SIR) += lirc_sir.o diff --git a/drivers/staging/media/lirc/lirc_rpi.c b/drivers/staging/media/lirc/lirc_rpi.c new file mode 100644 -index 0000000..57ffacf +index 0000000..887c36b --- /dev/null +++ b/drivers/staging/media/lirc/lirc_rpi.c -@@ -0,0 +1,695 @@ +@@ -0,0 +1,689 @@ +/* + * lirc_rpi.c + * @@ -87305,8 +84520,11 @@ index 0000000..57ffacf +#include +#include +#include ++#include +#include + ++#include ++ +#define LIRC_DRIVER_NAME "lirc_rpi" +#define RBUF_LEN 256 +#define LIRC_TRANSMITTER_LATENCY 50 @@ -87328,6 +84546,8 @@ index 0000000..57ffacf + +/* set the default GPIO input pin */ +static int gpio_in_pin = 18; ++/* set the default pull behaviour for input pin */ ++static int gpio_in_pull = BCM2708_PULL_DOWN; +/* set the default GPIO output pin */ +static int gpio_out_pin = 17; +/* enable debugging messages */ @@ -87348,9 +84568,6 @@ index 0000000..57ffacf +static void send_space(long length); +static void lirc_rpi_exit(void); + -+int valid_gpio_pins[] = { 0, 1, 2, 3, 4, 7, 8, 9, 10, 11, 14, 15, 17, 18, 21, -+ 22, 23, 24, 25 ,27, 28, 29, 30, 31 }; -+ +static struct platform_device *lirc_rpi_dev; +static struct timeval lasttv = { 0, 0 }; +static struct lirc_buffer rbuf; @@ -87587,6 +84804,7 @@ index 0000000..57ffacf + goto exit_gpio_free_out_pin; + } + ++ bcm2708_gpio_setpull(gpiochip, gpio_in_pin, gpio_in_pull); + gpiochip->direction_input(gpiochip, gpio_in_pin); + gpiochip->direction_output(gpiochip, gpio_out_pin, 1); + gpiochip->set(gpiochip, gpio_out_pin, invert); @@ -87866,24 +85084,13 @@ index 0000000..57ffacf + +static int __init lirc_rpi_init_module(void) +{ -+ int result, i; ++ int result; + + result = lirc_rpi_init(); + if (result) + return result; + -+ /* check if the module received valid gpio pin numbers */ -+ result = 0; -+ if (gpio_in_pin != gpio_out_pin) { -+ for(i = 0; (i < ARRAY_SIZE(valid_gpio_pins)) && (result != 2); i++) { -+ if (gpio_in_pin == valid_gpio_pins[i] || -+ gpio_out_pin == valid_gpio_pins[i]) { -+ result++; -+ } -+ } -+ } -+ -+ if (result != 2) { ++ if (gpio_in_pin >= BCM2708_NR_GPIOS || gpio_out_pin >= BCM2708_NR_GPIOS) { + result = -EINVAL; + printk(KERN_ERR LIRC_DRIVER_NAME + ": invalid GPIO pin(s) specified!\n"); @@ -87940,13 +85147,15 @@ index 0000000..57ffacf + +module_param(gpio_out_pin, int, S_IRUGO); +MODULE_PARM_DESC(gpio_out_pin, "GPIO output/transmitter pin number of the BCM" -+ " processor. Valid pin numbers are: 0, 1, 4, 8, 7, 9, 10, 11," -+ " 14, 15, 17, 18, 21, 22, 23, 24, 25, default 17"); ++ " processor. (default 17"); + +module_param(gpio_in_pin, int, S_IRUGO); +MODULE_PARM_DESC(gpio_in_pin, "GPIO input pin number of the BCM processor." -+ " Valid pin numbers are: 0, 1, 4, 8, 7, 9, 10, 11, 14, 15," -+ " 17, 18, 21, 22, 23, 24, 25, default 18"); ++ " (default 18"); ++ ++module_param(gpio_in_pull, int, S_IRUGO); ++MODULE_PARM_DESC(gpio_in_pull, "GPIO input pin pull configuration." ++ " (0 = off, 1 = up, 2 = down, default down)"); + +module_param(sense, int, S_IRUGO); +MODULE_PARM_DESC(sense, "Override autodetection of IR receiver circuit" @@ -87961,10 +85170,10 @@ index 0000000..57ffacf +module_param(debug, bool, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(debug, "Enable debugging messages"); -From 360423b2167a280bc8ca38063dd7c50f10d8fab1 Mon Sep 17 00:00:00 2001 +From 2d0eafa48750d6f6874d0138bc5492aefc3797ee Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:49:20 +0100 -Subject: [PATCH 15/94] Add cpufreq driver +Subject: [PATCH 16/82] Add cpufreq driver --- arch/arm/Kconfig | 1 + @@ -87975,10 +85184,10 @@ Subject: [PATCH 15/94] Add cpufreq driver create mode 100755 drivers/cpufreq/bcm2835-cpufreq.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index bf32dc1..cb53c45 100644 +index aeb74cd..2b7243f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -383,6 +383,7 @@ config ARCH_BCM2708 +@@ -387,6 +387,7 @@ config ARCH_BCM2708 select NEED_MACH_GPIO_H select NEED_MACH_MEMORY_H select CLKDEV_LOOKUP @@ -88263,10 +85472,10 @@ index 0000000..7bc55bd +module_init(bcm2835_cpufreq_module_init); +module_exit(bcm2835_cpufreq_module_exit); -From db98f80199c117cb9c04acae917936a1a06ed956 Mon Sep 17 00:00:00 2001 +From 1162e1a02edd5d721f587d5e2afdc51e5013d560 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 26 Mar 2013 19:24:24 +0000 -Subject: [PATCH 16/94] Added hwmon/thermal driver for reporting core +Subject: [PATCH 17/82] Added hwmon/thermal driver for reporting core temperature. Thanks Dorian --- @@ -88282,10 +85491,10 @@ Subject: [PATCH 16/94] Added hwmon/thermal driver for reporting core create mode 100644 drivers/thermal/bcm2835-thermal.c diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index ab06b52..e66fc4b 100644 +index f3dccae..af57d11 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -483,6 +483,14 @@ static struct platform_device bcm2708_alsa_devices[] = { +@@ -455,6 +455,14 @@ static struct platform_device bcm2708_alsa_devices[] = { }, }; @@ -88300,7 +85509,7 @@ index ab06b52..e66fc4b 100644 int __init bcm_register_device(struct platform_device *pdev) { int ret; -@@ -594,6 +602,9 @@ void __init bcm2708_init(void) +@@ -563,6 +571,9 @@ void __init bcm2708_init(void) for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) bcm_register_device(&bcm2708_alsa_devices[i]); @@ -88311,10 +85520,10 @@ index ab06b52..e66fc4b 100644 struct amba_device *d = amba_devs[i]; amba_device_register(d, &iomem_resource); diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig -index 02d3d85..ad95ee5 100644 +index f00d048..20a8679 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig -@@ -1624,6 +1624,16 @@ config SENSORS_ULTRA45 +@@ -1669,6 +1669,16 @@ config SENSORS_ULTRA45 This driver provides support for the Ultra45 workstation environmental sensors. @@ -88332,10 +85541,10 @@ index 02d3d85..ad95ee5 100644 comment "ACPI drivers" diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile -index 3dc0f02..83b687d 100644 +index be28152..7fabf32 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile -@@ -148,6 +148,7 @@ obj-$(CONFIG_SENSORS_W83L785TS) += w83l785ts.o +@@ -152,6 +152,7 @@ obj-$(CONFIG_SENSORS_W83L785TS) += w83l785ts.o obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o @@ -88569,7 +85778,7 @@ index 0000000..5bbed45 + +module_platform_driver(bcm2835_hwmon_driver); diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig -index f9a1386..94cf128 100644 +index 693208e..fb11a9f 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -196,6 +196,12 @@ config INTEL_POWERCLAMP @@ -88586,7 +85795,7 @@ index f9a1386..94cf128 100644 tristate "X86 package temperature thermal driver" depends on X86_THERMAL_VECTOR diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile -index de0636a..77ea718 100644 +index 31e232f..8e956ca 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o @@ -88788,10 +85997,10 @@ index 0000000..85fceb5 + +module_platform_driver(bcm2835_thermal_driver); -From afb0616a3fda709d0e2b1dbae2ea77b8e170eebe Mon Sep 17 00:00:00 2001 +From 34da3ce697d69b71c68e2af279381a88afe295f2 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Tue, 26 Mar 2013 17:26:38 +0000 -Subject: [PATCH 17/94] Allow mac address to be set in smsc95xx +Subject: [PATCH 18/82] Allow mac address to be set in smsc95xx Signed-off-by: popcornmix --- @@ -88882,10 +86091,10 @@ index d07bf4c..5ae60ab 100644 if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, dev->net->dev_addr) == 0) { -From 977e8f91bf1d77cf7a6165608cfae630864343bb Mon Sep 17 00:00:00 2001 +From 2eba886406b0c97b6270d2f34e7ee2589ef28946 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 4 Nov 2013 18:56:10 +0000 -Subject: [PATCH 18/94] Add Chris Boot's i2c and spi drivers. +Subject: [PATCH 19/82] Add Chris Boot's i2c and spi drivers. i2c-bcm2708: fixed baudrate @@ -88896,43 +86105,24 @@ Example: 3500Hz -> CDIV=0x11704 -> CDIV(16bit)=0x1704 -> 42430Hz After correction: 3500Hz -> CDIV=0x11704 -> CDIV(16bit)=0xffff -> 3815Hz The correct baudrate is shown in the log after the cdiv > 0xffff correction. --- - arch/arm/configs/bcmrpi_cutdown_defconfig | 9 + - arch/arm/configs/bcmrpi_defconfig | 6 + - arch/arm/mach-bcm2708/Kconfig | 7 + - arch/arm/mach-bcm2708/bcm2708.c | 104 ++++- - arch/arm/mach-bcm2708/include/mach/platform.h | 3 + - drivers/i2c/busses/Kconfig | 19 + - drivers/i2c/busses/Makefile | 1 + - drivers/i2c/busses/i2c-bcm2708.c | 419 +++++++++++++++++ - drivers/spi/Kconfig | 8 + - drivers/spi/Makefile | 1 + - drivers/spi/spi-bcm2708.c | 626 ++++++++++++++++++++++++++ - 11 files changed, 1201 insertions(+), 2 deletions(-) + arch/arm/configs/bcmrpi_defconfig | 7 + + arch/arm/mach-bcm2708/Kconfig | 7 + + arch/arm/mach-bcm2708/bcm2708.c | 104 ++++++- + drivers/i2c/busses/Kconfig | 19 ++ + drivers/i2c/busses/Makefile | 1 + + drivers/i2c/busses/i2c-bcm2708.c | 419 +++++++++++++++++++++++++ + drivers/spi/Kconfig | 8 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-bcm2708.c | 626 ++++++++++++++++++++++++++++++++++++++ + 9 files changed, 1190 insertions(+), 2 deletions(-) create mode 100644 drivers/i2c/busses/i2c-bcm2708.c create mode 100644 drivers/spi/spi-bcm2708.c -diff --git a/arch/arm/configs/bcmrpi_cutdown_defconfig b/arch/arm/configs/bcmrpi_cutdown_defconfig -index e519412..2c2e29e 100644 ---- a/arch/arm/configs/bcmrpi_cutdown_defconfig -+++ b/arch/arm/configs/bcmrpi_cutdown_defconfig -@@ -492,3 +492,12 @@ CONFIG_CRYPTO_DEFLATE=m - # CONFIG_CRYPTO_HW is not set - CONFIG_CRC_ITU_T=y - CONFIG_LIBCRC32C=y -+CONFIG_I2C=y -+CONFIG_I2C_BOARDINFO=y -+CONFIG_I2C_COMPAT=y -+CONFIG_I2C_CHARDEV=m -+CONFIG_I2C_HELPER_AUTO=y -+CONFIG_I2C_BCM2708=m -+CONFIG_SPI=y -+CONFIG_SPI_MASTER=y -+CONFIG_SPI_BCM2708=m diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index df947e5..31f5afaa 100644 +index 63cb6a4..6d2eae1 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -214,6 +214,12 @@ CONFIG_SERIAL_AMBA_PL011=y +@@ -195,6 +195,13 @@ CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_RAW_DRIVER=y @@ -88942,9 +86132,10 @@ index df947e5..31f5afaa 100644 +CONFIG_SPI=y +CONFIG_SPI_BCM2708=m +CONFIG_SPI_SPIDEV=m - CONFIG_GPIO_SYSFS=y ++CONFIG_GPIO_SYSFS=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y + CONFIG_FB=y diff --git a/arch/arm/mach-bcm2708/Kconfig b/arch/arm/mach-bcm2708/Kconfig index 9355841..e151ed4 100644 --- a/arch/arm/mach-bcm2708/Kconfig @@ -88962,7 +86153,7 @@ index 9355841..e151ed4 100644 + Binds spidev driver to the SPI0 master endmenu diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index e66fc4b..f225e5b 100644 +index af57d11..82f56fb 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c @@ -31,6 +31,7 @@ @@ -89005,7 +86196,7 @@ index e66fc4b..f225e5b 100644 } }; -@@ -483,6 +491,89 @@ static struct platform_device bcm2708_alsa_devices[] = { +@@ -455,6 +463,89 @@ static struct platform_device bcm2708_alsa_devices[] = { }, }; @@ -89095,7 +86286,7 @@ index e66fc4b..f225e5b 100644 static struct platform_device bcm2835_hwmon_device = { .name = "bcm2835_hwmon", }; -@@ -602,6 +693,10 @@ void __init bcm2708_init(void) +@@ -571,6 +662,10 @@ void __init bcm2708_init(void) for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) bcm_register_device(&bcm2708_alsa_devices[i]); @@ -89106,7 +86297,7 @@ index e66fc4b..f225e5b 100644 bcm_register_device(&bcm2835_hwmon_device); bcm_register_device(&bcm2835_thermal_device); -@@ -611,6 +706,11 @@ void __init bcm2708_init(void) +@@ -580,6 +675,11 @@ void __init bcm2708_init(void) } system_rev = boardrev; system_serial_low = serial; @@ -89118,28 +86309,11 @@ index e66fc4b..f225e5b 100644 } static void timer_set_mode(enum clock_event_mode mode, -diff --git a/arch/arm/mach-bcm2708/include/mach/platform.h b/arch/arm/mach-bcm2708/include/mach/platform.h -index ecd854e..f4bb733 100644 ---- a/arch/arm/mach-bcm2708/include/mach/platform.h -+++ b/arch/arm/mach-bcm2708/include/mach/platform.h -@@ -64,9 +64,12 @@ - #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */ - #define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */ - #define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */ -+#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */ -+#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */ - #define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */ - #define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */ - #define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */ -+#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */ - #define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */ - #define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/ - diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig -index 9f7d585..6426811 100644 +index 2ac87fa..d8f8e2a 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig -@@ -348,6 +348,25 @@ config I2C_BCM2835 +@@ -349,6 +349,25 @@ config I2C_BCM2835 This support is also available as a module. If so, the module will be called i2c-bcm2835. @@ -89166,7 +86340,7 @@ index 9f7d585..6426811 100644 tristate "BCM Kona I2C adapter" depends on ARCH_BCM_MOBILE diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile -index dd9a7f8..359bc30 100644 +index 49bf07e..66a704e 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o @@ -89603,7 +86777,7 @@ index 0000000..f266f10 +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig -index 213b5cb..cb20594 100644 +index 62e2242..6a7943c 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -85,6 +85,14 @@ config SPI_BCM2835 @@ -89622,7 +86796,7 @@ index 213b5cb..cb20594 100644 tristate "SPI controller driver for ADI Blackfin5xx" depends on BLACKFIN && !BF60x diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile -index 929c9f5..60871de 100644 +index 762da07..2b4be86 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o @@ -90266,10 +87440,10 @@ index 0000000..b04a57d +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); -From 732163f2565eeb4e2cc8a9e75af77163a4c3ac61 Mon Sep 17 00:00:00 2001 +From 0a6f1f3290e53bd26b9177169cb80044f397525f Mon Sep 17 00:00:00 2001 From: cbeytas Date: Mon, 24 Jun 2013 00:05:40 -0400 -Subject: [PATCH 19/94] Perform I2C combined transactions when possible +Subject: [PATCH 20/82] Perform I2C combined transactions when possible Perform I2C combined transactions whenever possible, within the restrictions of the Broadcomm Serial Controller. @@ -90341,10 +87515,10 @@ index f266f10..8750634 100644 } -From 72f63745f25941f5114b69e0e03847812325222c Mon Sep 17 00:00:00 2001 +From 48331c6f062108082daddbb9edbcf97678841765 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 8 May 2013 11:46:50 +0100 -Subject: [PATCH 20/94] enabling the realtime clock 1-wire chip DS1307 and +Subject: [PATCH 21/82] enabling the realtime clock 1-wire chip DS1307 and 1-wire on GPIO4 (as a module) 1-wire: Add support for configuring pin for w1-gpio kernel module @@ -90370,7 +87544,7 @@ Signed-off-by: Alex J Lennon 5 files changed, 114 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index f225e5b..16307ab 100644 +index 82f56fb..7dd89a7f 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c @@ -32,6 +32,7 @@ @@ -90422,7 +87596,7 @@ index f225e5b..16307ab 100644 static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); static struct platform_device bcm2708_fb_device = { -@@ -680,6 +702,11 @@ void __init bcm2708_init(void) +@@ -652,6 +674,11 @@ void __init bcm2708_init(void) #ifdef CONFIG_BCM2708_GPIO bcm_register_device(&bcm2708_gpio_device); #endif @@ -90434,7 +87608,7 @@ index f225e5b..16307ab 100644 bcm_register_device(&bcm2708_systemtimer_device); bcm_register_device(&bcm2708_fb_device); bcm_register_device(&bcm2708_usb_device); -@@ -884,3 +911,5 @@ module_param(uart_clock, uint, 0644); +@@ -853,3 +880,5 @@ module_param(uart_clock, uint, 0644); module_param(disk_led_gpio, uint, 0644); module_param(disk_led_active_low, uint, 0644); module_param(reboot_part, uint, 0644); @@ -90561,12 +87735,12 @@ index 56a49ba..881d728 100644 u8, w1_slave_found_callback); }; diff --git a/drivers/w1/w1_int.c b/drivers/w1/w1_int.c -index 728039d2..b68c179 100644 +index 47249a3..a4b4a8d 100644 --- a/drivers/w1/w1_int.c +++ b/drivers/w1/w1_int.c -@@ -124,6 +124,20 @@ int w1_add_master_device(struct w1_bus_master *master) +@@ -123,6 +123,20 @@ int w1_add_master_device(struct w1_bus_master *master) return(-EINVAL); - } + } + /* bitbanging hardware uses bitbang_pullup, other hardware uses set_pullup + * and takes care of timing itself */ @@ -90616,33 +87790,29 @@ index 2820924..fd0550f 100644 } } -From b6c327d2034a59f96c6458454a9a50721125357f Mon Sep 17 00:00:00 2001 +From 89f17effaf34de81af1918f01df5d7b756c21109 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Fri, 12 Apr 2013 23:58:47 +0100 -Subject: [PATCH 24/94] config: add missing options from 3.6.y kernel +Subject: [PATCH 23/82] config: add missing options from 3.6.y kernel --- - arch/arm/configs/bcmrpi_defconfig | 757 ++++++++++++++++++++++++++++++++------ - 1 file changed, 651 insertions(+), 106 deletions(-) + arch/arm/configs/bcmrpi_defconfig | 629 ++++++++++++++++++++++++++++++++++++-- + 1 file changed, 610 insertions(+), 19 deletions(-) diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 31f5afaa..5b69e83 100644 +index 6d2eae1..ae787a6 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -1,11 +1,17 @@ --CONFIG_EXPERIMENTAL=y +@@ -1,3 +1,5 @@ +# CONFIG_ARM_PATCH_PHYS_VIRT is not set ++CONFIG_PHYS_OFFSET=0 # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y --CONFIG_BSD_PROCESS_ACCT=y --CONFIG_BSD_PROCESS_ACCT_V3=y - CONFIG_FHANDLE=y - CONFIG_AUDIT=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_BSD_PROCESS_ACCT=y -+CONFIG_BSD_PROCESS_ACCT_V3=y +@@ -7,6 +9,10 @@ CONFIG_NO_HZ=y + CONFIG_HIGH_RES_TIMERS=y + CONFIG_BSD_PROCESS_ACCT=y + CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y @@ -90650,11 +87820,10 @@ index 31f5afaa..5b69e83 100644 CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_CGROUP_FREEZER=y -@@ -15,29 +21,42 @@ CONFIG_RESOURCE_COUNTERS=y +@@ -16,28 +22,40 @@ CONFIG_RESOURCE_COUNTERS=y CONFIG_BLK_CGROUP=y CONFIG_NAMESPACES=y CONFIG_SCHED_AUTOGROUP=y -+CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y CONFIG_EMBEDDED=y # CONFIG_COMPAT_BRK is not set @@ -90669,12 +87838,10 @@ index 31f5afaa..5b69e83 100644 CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set CONFIG_BLK_DEV_THROTTLING=y -+CONFIG_PARTITION_ADVANCED=y -+CONFIG_MAC_PARTITION=y + CONFIG_PARTITION_ADVANCED=y + CONFIG_MAC_PARTITION=y CONFIG_CFQ_GROUP_IOSCHED=y CONFIG_ARCH_BCM2708=y --CONFIG_NO_HZ=y --CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y CONFIG_AEABI=y +CONFIG_CLEANCACHE=y @@ -90682,7 +87849,6 @@ index 31f5afaa..5b69e83 100644 +CONFIG_CMA=y +CONFIG_UACCESS_WITH_MEMCPY=y CONFIG_SECCOMP=y --CONFIG_CC_STACKPROTECTOR=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" @@ -90691,15 +87857,14 @@ index 31f5afaa..5b69e83 100644 +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=m +CONFIG_CPU_FREQ_STAT_DETAILS=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPU_IDLE=y CONFIG_VFP=y CONFIG_BINFMT_MISC=m -@@ -48,19 +67,278 @@ CONFIG_XFRM_USER=y +@@ -48,19 +66,272 @@ CONFIG_XFRM_USER=y CONFIG_NET_KEY=m CONFIG_INET=y CONFIG_IP_MULTICAST=y @@ -90848,17 +88013,13 @@ index 31f5afaa..5b69e83 100644 +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_NF_CONNTRACK_IPV4=m ++CONFIG_NF_NAT_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m -+CONFIG_IP_NF_TARGET_ULOG=m -+CONFIG_NF_NAT_IPV4=m -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+CONFIG_IP_NF_TARGET_NETMAP=m -+CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m @@ -90867,6 +88028,7 @@ index 31f5afaa..5b69e83 100644 +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NF_CONNTRACK_IPV6=m ++CONFIG_NF_NAT_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m @@ -90881,9 +88043,6 @@ index 31f5afaa..5b69e83 100644 +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m -+CONFIG_NF_NAT_IPV6=m -+CONFIG_IP6_NF_TARGET_MASQUERADE=m -+CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m @@ -90904,9 +88063,9 @@ index 31f5afaa..5b69e83 100644 +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m -+CONFIG_BRIDGE_EBT_ULOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_SCTP_COOKIE_HMAC_SHA1=y ++CONFIG_ATM=m +CONFIG_L2TP=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m @@ -90984,16 +88143,7 @@ index 31f5afaa..5b69e83 100644 CONFIG_IRCOMM=m CONFIG_IRDA_ULTRA=y CONFIG_IRDA_CACHE_LAST_LSAP=y -@@ -73,8 +351,6 @@ CONFIG_USB_IRDA=m - CONFIG_SIGMATEL_FIR=m - CONFIG_MCS_FIR=m - CONFIG_BT=m --CONFIG_BT_L2CAP=y --CONFIG_BT_SCO=y - CONFIG_BT_RFCOMM=m - CONFIG_BT_RFCOMM_TTY=y - CONFIG_BT_BNEP=m -@@ -89,35 +365,106 @@ CONFIG_BT_HCIVHCI=m +@@ -87,44 +358,84 @@ CONFIG_BT_HCIVHCI=m CONFIG_BT_MRVL=m CONFIG_BT_MRVL_SDIO=m CONFIG_BT_ATH3K=m @@ -91001,7 +88151,6 @@ index 31f5afaa..5b69e83 100644 CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=m - CONFIG_MAC80211_RC_PID=y CONFIG_MAC80211_MESH=y CONFIG_WIMAX=m +CONFIG_RFKILL=m @@ -91020,7 +88169,6 @@ index 31f5afaa..5b69e83 100644 CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_CDROM_PKTCDVD=m --CONFIG_MISC_DEVICES=y +CONFIG_EEPROM_AT24=m CONFIG_SCSI=y # CONFIG_SCSI_PROC_FS is not set @@ -91029,9 +88177,8 @@ index 31f5afaa..5b69e83 100644 +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m CONFIG_BLK_DEV_SR=m -+CONFIG_CHR_DEV_SG=m - CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_LOWLEVEL is not set ++CONFIG_CHR_DEV_SG=m +CONFIG_SCSI_ISCSI_ATTRS=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m @@ -91051,72 +88198,62 @@ index 31f5afaa..5b69e83 100644 +CONFIG_DUMMY=m +CONFIG_IFB=m +CONFIG_MACVLAN=m -+CONFIG_NETCONSOLE=m + CONFIG_NETCONSOLE=m CONFIG_TUN=m --CONFIG_PHYLIB=m +CONFIG_VETH=m CONFIG_MDIO_BITBANG=m --CONFIG_NET_ETHERNET=y --# CONFIG_NETDEV_1000 is not set --# CONFIG_NETDEV_10000 is not set -+CONFIG_PPP=m -+CONFIG_PPP_BSDCOMP=m -+CONFIG_PPP_DEFLATE=m + CONFIG_PPP=m + CONFIG_PPP_BSDCOMP=m + CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y ++CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m -+CONFIG_PPP_ASYNC=m -+CONFIG_PPP_SYNC_TTY=m -+CONFIG_SLIP=m -+CONFIG_SLIP_COMPRESSED=y + CONFIG_PPP_ASYNC=m + CONFIG_PPP_SYNC_TTY=m + CONFIG_SLIP=m + CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y -+CONFIG_USB_CATC=m -+CONFIG_USB_KAWETH=m -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m + CONFIG_USB_CATC=m + CONFIG_USB_KAWETH=m + CONFIG_USB_PEGASUS=m + CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m -+CONFIG_USB_USBNET=y -+CONFIG_USB_NET_AX8817X=m + CONFIG_USB_USBNET=y + CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m -+CONFIG_USB_NET_CDCETHER=m -+CONFIG_USB_NET_CDC_EEM=m + CONFIG_USB_NET_CDCETHER=m + CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m -+CONFIG_USB_NET_DM9601=m -+CONFIG_USB_NET_SMSC75XX=m -+CONFIG_USB_NET_SMSC95XX=y -+CONFIG_USB_NET_GL620A=m -+CONFIG_USB_NET_NET1080=m -+CONFIG_USB_NET_PLUSB=m -+CONFIG_USB_NET_MCS7830=m -+CONFIG_USB_NET_CDC_SUBSET=m -+CONFIG_USB_ALI_M5632=y -+CONFIG_USB_AN2720=y + CONFIG_USB_NET_DM9601=m + CONFIG_USB_NET_SMSC75XX=m + CONFIG_USB_NET_SMSC95XX=y +@@ -135,10 +446,13 @@ CONFIG_USB_NET_MCS7830=m + CONFIG_USB_NET_CDC_SUBSET=m + CONFIG_USB_ALI_M5632=y + CONFIG_USB_AN2720=y +CONFIG_USB_EPSON2888=y -+CONFIG_USB_KC2190=y + CONFIG_USB_KC2190=y +-# CONFIG_USB_NET_ZAURUS is not set +CONFIG_USB_NET_ZAURUS=m -+CONFIG_USB_NET_CX82310_ETH=m -+CONFIG_USB_NET_KALMIA=m + CONFIG_USB_NET_CX82310_ETH=m + CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m -+CONFIG_USB_NET_INT51X1=m -+CONFIG_USB_IPHETH=m -+CONFIG_USB_SIERRA_NET=m -+CONFIG_USB_VL600=m - CONFIG_LIBERTAS_THINFIRM=m - CONFIG_LIBERTAS_THINFIRM_USB=m - CONFIG_AT76C50X_USB=m -@@ -125,14 +472,17 @@ CONFIG_USB_ZD1201=m + CONFIG_USB_NET_INT51X1=m + CONFIG_USB_IPHETH=m + CONFIG_USB_SIERRA_NET=m +@@ -150,7 +464,15 @@ CONFIG_USB_ZD1201=m CONFIG_USB_NET_RNDIS_WLAN=m CONFIG_RTL8187=m CONFIG_MAC80211_HWSIM=m --CONFIG_ATH_COMMON=m +CONFIG_ATH_CARDS=m - CONFIG_ATH9K=m - CONFIG_ATH9K_HTC=m - CONFIG_CARL9170=m ++CONFIG_ATH9K=m ++CONFIG_ATH9K_HTC=m ++CONFIG_CARL9170=m +CONFIG_ATH6KL=m +CONFIG_ATH6KL_USB=m +CONFIG_AR5523=m @@ -91124,11 +88261,8 @@ index 31f5afaa..5b69e83 100644 +# CONFIG_B43_PHY_N is not set CONFIG_B43LEGACY=m CONFIG_HOSTAP=m --CONFIG_IWM=m CONFIG_LIBERTAS=m - CONFIG_LIBERTAS_USB=m - CONFIG_LIBERTAS_SDIO=m -@@ -142,57 +492,28 @@ CONFIG_RT2X00=m +@@ -162,7 +484,10 @@ CONFIG_RT2X00=m CONFIG_RT2500USB=m CONFIG_RT73USB=m CONFIG_RT2800USB=m @@ -91137,49 +88271,9 @@ index 31f5afaa..5b69e83 100644 +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y CONFIG_RTL8192CU=m --CONFIG_WL1251=m --CONFIG_WL12XX_MENU=m CONFIG_ZD1211RW=m CONFIG_MWIFIEX=m - CONFIG_MWIFIEX_SDIO=m - CONFIG_WIMAX_I2400M_USB=m --CONFIG_USB_CATC=m --CONFIG_USB_KAWETH=m --CONFIG_USB_PEGASUS=m --CONFIG_USB_RTL8150=m --CONFIG_USB_USBNET=y --CONFIG_USB_NET_AX8817X=m --CONFIG_USB_NET_CDCETHER=m --CONFIG_USB_NET_CDC_EEM=m --CONFIG_USB_NET_DM9601=m --CONFIG_USB_NET_SMSC75XX=m --CONFIG_USB_NET_SMSC95XX=y --CONFIG_USB_NET_GL620A=m --CONFIG_USB_NET_NET1080=m --CONFIG_USB_NET_PLUSB=m --CONFIG_USB_NET_MCS7830=m --CONFIG_USB_NET_CDC_SUBSET=m --CONFIG_USB_ALI_M5632=y --CONFIG_USB_AN2720=y --CONFIG_USB_KC2190=y --# CONFIG_USB_NET_ZAURUS is not set --CONFIG_USB_NET_CX82310_ETH=m --CONFIG_USB_NET_KALMIA=m --CONFIG_USB_NET_INT51X1=m --CONFIG_USB_IPHETH=m --CONFIG_USB_SIERRA_NET=m --CONFIG_USB_VL600=m --CONFIG_PPP=m --CONFIG_PPP_ASYNC=m --CONFIG_PPP_SYNC_TTY=m --CONFIG_PPP_DEFLATE=m --CONFIG_PPP_BSDCOMP=m --CONFIG_SLIP=m --CONFIG_SLIP_COMPRESSED=y --CONFIG_NETCONSOLE=m - CONFIG_INPUT_POLLDEV=m - # CONFIG_INPUT_MOUSEDEV_PSAUX is not set - CONFIG_INPUT_JOYDEV=m +@@ -174,6 +499,11 @@ CONFIG_INPUT_JOYDEV=m CONFIG_INPUT_EVDEV=m # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set @@ -91190,15 +88284,11 @@ index 31f5afaa..5b69e83 100644 +CONFIG_JOYSTICK_XPAD_FF=y CONFIG_INPUT_MISC=y CONFIG_INPUT_AD714X=m --CONFIG_INPUT_ATI_REMOTE=m CONFIG_INPUT_ATI_REMOTE2=m - CONFIG_INPUT_KEYSPAN_REMOTE=m - CONFIG_INPUT_POWERMATE=m -@@ -207,26 +528,191 @@ CONFIG_SERIO_RAW=m +@@ -189,22 +519,190 @@ CONFIG_SERIO_RAW=m CONFIG_GAMEPORT=m CONFIG_GAMEPORT_NS558=m CONFIG_GAMEPORT_L4=m --CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y # CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set @@ -91241,8 +88331,7 @@ index 31f5afaa..5b69e83 100644 +CONFIG_THERMAL=y +CONFIG_THERMAL_BCM2835=y CONFIG_WATCHDOG=y - CONFIG_BCM2708_WDT=m --# CONFIG_MFD_SUPPORT is not set ++CONFIG_BCM2708_WDT=m +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y @@ -91360,7 +88449,6 @@ index 31f5afaa..5b69e83 100644 +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m -+CONFIG_DVB_USB_IT913X=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m @@ -91385,33 +88473,23 @@ index 31f5afaa..5b69e83 100644 +CONFIG_RADIO_WL1273=m +CONFIG_RADIO_WL128X=m CONFIG_FB=y - CONFIG_FB_BCM2708=y ++CONFIG_FB_BCM2708=y +# CONFIG_BACKLIGHT_GENERIC is not set CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set -@@ -249,10 +735,10 @@ CONFIG_SND_BCM2835=m +@@ -227,8 +725,10 @@ CONFIG_SND_BCM2835=m CONFIG_SND_USB_AUDIO=m CONFIG_SND_USB_UA101=m CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y CONFIG_SND_USB_6FIRE=m CONFIG_SOUND_PRIME=m --CONFIG_HID_PID=y --CONFIG_USB_HIDDEV=y +CONFIG_HIDRAW=y CONFIG_HID_A4TECH=m CONFIG_HID_ACRUX=m CONFIG_HID_APPLE=m -@@ -283,7 +769,6 @@ CONFIG_HID_ORTEK=m - CONFIG_HID_PANTHERLORD=m - CONFIG_HID_PETALYNX=m - CONFIG_HID_PICOLCD=m --CONFIG_HID_QUANTA=m - CONFIG_HID_ROCCAT=m - CONFIG_HID_SAMSUNG=m - CONFIG_HID_SONY=m -@@ -292,15 +777,20 @@ CONFIG_HID_SUNPLUS=m +@@ -267,9 +767,11 @@ CONFIG_HID_SUNPLUS=m CONFIG_HID_GREENASIA=m CONFIG_HID_SMARTJOYPLUS=m CONFIG_HID_TOPSEED=m @@ -91422,32 +88500,17 @@ index 31f5afaa..5b69e83 100644 +CONFIG_HID_XINMO=m CONFIG_HID_ZEROPLUS=m CONFIG_HID_ZYDACRON=m -+CONFIG_HID_PID=y -+CONFIG_USB_HIDDEV=y + CONFIG_HID_PID=y +@@ -277,6 +779,8 @@ CONFIG_USB_HIDDEV=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_MON=m - CONFIG_USB_DWCOTG=y ++CONFIG_USB_DWCOTG=y +CONFIG_USB_PRINTER=m CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE_REALTEK=m CONFIG_USB_STORAGE_DATAFAB=m -@@ -315,8 +805,6 @@ CONFIG_USB_STORAGE_ONETOUCH=m - CONFIG_USB_STORAGE_KARMA=m - CONFIG_USB_STORAGE_CYPRESS_ATACB=m - CONFIG_USB_STORAGE_ENE_UB6250=m --CONFIG_USB_UAS=m --CONFIG_USB_LIBUSUAL=y - CONFIG_USB_MDC800=m - CONFIG_USB_MICROTEK=m - CONFIG_USB_SERIAL=m -@@ -331,12 +819,12 @@ CONFIG_USB_SERIAL_CP210X=m - CONFIG_USB_SERIAL_CYPRESS_M8=m - CONFIG_USB_SERIAL_EMPEG=m - CONFIG_USB_SERIAL_FTDI_SIO=m --CONFIG_USB_SERIAL_FUNSOFT=m - CONFIG_USB_SERIAL_VISOR=m - CONFIG_USB_SERIAL_IPAQ=m +@@ -311,6 +815,7 @@ CONFIG_USB_SERIAL_IPAQ=m CONFIG_USB_SERIAL_IR=m CONFIG_USB_SERIAL_EDGEPORT=m CONFIG_USB_SERIAL_EDGEPORT_TI=m @@ -91455,32 +88518,18 @@ index 31f5afaa..5b69e83 100644 CONFIG_USB_SERIAL_GARMIN=m CONFIG_USB_SERIAL_IPW=m CONFIG_USB_SERIAL_IUU=m -@@ -345,18 +833,16 @@ CONFIG_USB_SERIAL_KEYSPAN=m +@@ -319,6 +824,7 @@ CONFIG_USB_SERIAL_KEYSPAN=m CONFIG_USB_SERIAL_KLSI=m CONFIG_USB_SERIAL_KOBIL_SCT=m CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m CONFIG_USB_SERIAL_MOS7720=m CONFIG_USB_SERIAL_MOS7840=m --CONFIG_USB_SERIAL_MOTOROLA=m CONFIG_USB_SERIAL_NAVMAN=m - CONFIG_USB_SERIAL_PL2303=m - CONFIG_USB_SERIAL_OTI6858=m - CONFIG_USB_SERIAL_QCAUX=m - CONFIG_USB_SERIAL_QUALCOMM=m - CONFIG_USB_SERIAL_SPCP8X5=m --CONFIG_USB_SERIAL_HP4X=m - CONFIG_USB_SERIAL_SAFE=m --CONFIG_USB_SERIAL_SIEMENS_MPI=m - CONFIG_USB_SERIAL_SIERRAWIRELESS=m - CONFIG_USB_SERIAL_SYMBOL=m - CONFIG_USB_SERIAL_TI=m -@@ -365,9 +851,11 @@ CONFIG_USB_SERIAL_XIRCOM=m +@@ -336,7 +842,11 @@ CONFIG_USB_SERIAL_XIRCOM=m CONFIG_USB_SERIAL_OPTION=m CONFIG_USB_SERIAL_OMNINET=m CONFIG_USB_SERIAL_OPTICON=m --CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m --CONFIG_USB_SERIAL_ZIO=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_ZTE=m @@ -91489,19 +88538,19 @@ index 31f5afaa..5b69e83 100644 CONFIG_USB_SERIAL_DEBUG=m CONFIG_USB_EMI62=m CONFIG_USB_EMI26=m -@@ -389,17 +877,74 @@ CONFIG_USB_TEST=m +@@ -357,11 +867,76 @@ CONFIG_USB_IOWARRIOR=m + CONFIG_USB_TEST=m CONFIG_USB_ISIGHTFW=m CONFIG_USB_YUREX=m ++CONFIG_USB_ATM=m ++CONFIG_USB_SPEEDTOUCH=m ++CONFIG_USB_CXACRU=m ++CONFIG_USB_UEAGLEATM=m ++CONFIG_USB_XUSBATM=m CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y - CONFIG_MMC_SDHCI_BCM2708=y - CONFIG_MMC_SDHCI_BCM2708_DMA=y --CONFIG_LEDS_GPIO=y --CONFIG_LEDS_TRIGGER_TIMER=m --CONFIG_LEDS_TRIGGER_HEARTBEAT=m --CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +CONFIG_MMC_SPI=m +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_TRIGGER_TIMER=y @@ -91548,10 +88597,8 @@ index 31f5afaa..5b69e83 100644 +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_RX4581=m CONFIG_UIO=m --CONFIG_UIO_PDRV=m CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_STAGING=y -+CONFIG_W35UND=m +CONFIG_PRISM2_USB=m +CONFIG_R8712U=m +CONFIG_VT6656=m @@ -91559,7 +88606,6 @@ index 31f5afaa..5b69e83 100644 +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_STAGING_MEDIA=y +CONFIG_DVB_AS102=m -+CONFIG_USB_SN9C102=m +CONFIG_LIRC_STAGING=y +CONFIG_LIRC_IGORPLUGUSB=m +CONFIG_LIRC_IMON=m @@ -91569,7 +88615,7 @@ index 31f5afaa..5b69e83 100644 # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y -@@ -422,6 +967,8 @@ CONFIG_BTRFS_FS=m +@@ -384,6 +959,8 @@ CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y CONFIG_NILFS2_FS=m CONFIG_FANOTIFY=y @@ -91578,7 +88624,7 @@ index 31f5afaa..5b69e83 100644 CONFIG_AUTOFS4_FS=y CONFIG_FUSE_FS=m CONFIG_CUSE=m -@@ -437,28 +984,32 @@ CONFIG_MSDOS_FS=y +@@ -399,18 +976,26 @@ CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_NTFS_FS=m @@ -91595,7 +88641,6 @@ index 31f5afaa..5b69e83 100644 CONFIG_SQUASHFS_XZ=y +CONFIG_F2FS_FS=y CONFIG_NFS_FS=y --CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y @@ -91606,56 +88651,42 @@ index 31f5afaa..5b69e83 100644 CONFIG_CIFS=m CONFIG_CIFS_WEAK_PW_HASH=y CONFIG_CIFS_XATTR=y - CONFIG_CIFS_POSIX=y - CONFIG_9P_FS=m - CONFIG_9P_FS_POSIX_ACL=y --CONFIG_PARTITION_ADVANCED=y --CONFIG_MAC_PARTITION=y --CONFIG_EFI_PARTITION=y - CONFIG_NLS_DEFAULT="utf8" - CONFIG_NLS_CODEPAGE_437=y - CONFIG_NLS_CODEPAGE_737=m -@@ -497,39 +1048,33 @@ CONFIG_NLS_ISO8859_14=m +@@ -455,7 +1040,7 @@ CONFIG_NLS_ISO8859_14=m CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=m +CONFIG_DLM=m CONFIG_PRINTK_TIME=y -+CONFIG_BOOT_PRINTK_DELAY=y -+CONFIG_DEBUG_FS=y -+CONFIG_DEBUG_MEMORY_INIT=y + CONFIG_BOOT_PRINTK_DELAY=y + CONFIG_DEBUG_INFO=y +@@ -463,28 +1048,34 @@ CONFIG_DEBUG_STACK_USAGE=y + CONFIG_DEBUG_MEMORY_INIT=y CONFIG_DETECT_HUNG_TASK=y CONFIG_TIMER_STATS=y --CONFIG_DEBUG_STACK_USAGE=y --CONFIG_DEBUG_INFO=y --CONFIG_DEBUG_MEMORY_INIT=y --CONFIG_BOOT_PRINTK_DELAY=y +# CONFIG_DEBUG_PREEMPT is not set CONFIG_LATENCYTOP=y --CONFIG_SYSCTL_SYSCALL_CHECK=y --CONFIG_IRQSOFF_TRACER=y --CONFIG_SCHED_TRACER=y --CONFIG_STACK_TRACER=y --CONFIG_BLK_DEV_IO_TRACE=y --CONFIG_FUNCTION_PROFILER=y + CONFIG_IRQSOFF_TRACER=y + CONFIG_SCHED_TRACER=y + CONFIG_STACK_TRACER=y + CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_KPROBE_EVENT is not set + CONFIG_FUNCTION_PROFILER=y CONFIG_KGDB=y CONFIG_KGDB_KDB=y CONFIG_KDB_KEYBOARD=y CONFIG_STRICT_DEVMEM=y -CONFIG_CRYPTO_AUTHENC=m --CONFIG_CRYPTO_SEQIV=m +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_HMAC=y ++CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_XTS=m CONFIG_CRYPTO_XCBC=m --CONFIG_CRYPTO_MD5=y --CONFIG_CRYPTO_SHA1=y --CONFIG_CRYPTO_SHA256=m + CONFIG_CRYPTO_MD5=y + CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA1_ARM=m CONFIG_CRYPTO_SHA512=m CONFIG_CRYPTO_TGR192=m @@ -91668,10 +88699,10 @@ index 31f5afaa..5b69e83 100644 # CONFIG_CRYPTO_HW is not set CONFIG_CRC_ITU_T=y -From a7f9ef3115b9bd9d2ab0267980c67ac79d74471b Mon Sep 17 00:00:00 2001 +From 2d11277534ec321bb9707b54a45098891fca635a Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 18 Dec 2013 22:16:19 +0000 -Subject: [PATCH 25/94] config: Enable CONFIG_MEMCG, but leave it disabled (due +Subject: [PATCH 24/82] config: Enable CONFIG_MEMCG, but leave it disabled (due to memory cost). Enable with cgroup_enable=memory. --- @@ -91681,10 +88712,10 @@ Subject: [PATCH 25/94] config: Enable CONFIG_MEMCG, but leave it disabled (due 3 files changed, 25 insertions(+) diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 5b69e83..11c6f8f 100644 +index ae787a6..6ce900c 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -18,6 +18,7 @@ CONFIG_CGROUP_FREEZER=y +@@ -19,6 +19,7 @@ CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_RESOURCE_COUNTERS=y @@ -91693,10 +88724,10 @@ index 5b69e83..11c6f8f 100644 CONFIG_NAMESPACES=y CONFIG_SCHED_AUTOGROUP=y diff --git a/kernel/cgroup.c b/kernel/cgroup.c -index 70776ae..4662d09 100644 +index 3a73f99..077246c 100644 --- a/kernel/cgroup.c +++ b/kernel/cgroup.c -@@ -5205,6 +5205,29 @@ static int __init cgroup_disable(char *str) +@@ -5400,6 +5400,29 @@ static int __init cgroup_disable(char *str) } __setup("cgroup_disable=", cgroup_disable); @@ -91723,26 +88754,26 @@ index 70776ae..4662d09 100644 +} +__setup("cgroup_enable=", cgroup_enable); + - /** - * css_tryget_online_from_dir - get corresponding css from a cgroup dentry - * @dentry: directory dentry of interest + static int __init cgroup_set_legacy_files_on_dfl(char *str) + { + printk("cgroup: using legacy files on the default hierarchy\n"); diff --git a/mm/memcontrol.c b/mm/memcontrol.c -index 1f14a43..403173e 100644 +index 28928ce..33d37c3 100644 --- a/mm/memcontrol.c +++ b/mm/memcontrol.c -@@ -7029,6 +7029,7 @@ struct cgroup_subsys memory_cgrp_subsys = { +@@ -6334,6 +6334,7 @@ struct cgroup_subsys memory_cgrp_subsys = { .bind = mem_cgroup_bind, - .base_cftypes = mem_cgroup_files, + .legacy_cftypes = mem_cgroup_files, .early_init = 0, + .disabled = 1, }; #ifdef CONFIG_MEMCG_SWAP -From d44502238ff6807b97718b9396da51c3ac9c9957 Mon Sep 17 00:00:00 2001 +From 1fefc19d8c277b0612c8ba710c4d79916d4b4853 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Jul 2013 00:46:42 +0100 -Subject: [PATCH 26/94] Add FIQ patch to dwc_otg driver. Enable with +Subject: [PATCH 25/82] Add FIQ patch to dwc_otg driver. Enable with dwc_otg.fiq_fix_enable=1. Should give about 10% more ARM performance. Thanks to Gordon and Costas @@ -92000,7 +89031,6 @@ incarnations. arch/arm/mach-bcm2708/armctrl.c | 19 +- arch/arm/mach-bcm2708/bcm2708.c | 29 +- arch/arm/mach-bcm2708/include/mach/irqs.h | 155 ++--- - arch/arm/mach-bcm2708/include/mach/platform.h | 2 + .../usb/host/dwc_common_port/dwc_common_linux.c | 11 + drivers/usb/host/dwc_common_port/dwc_list.h | 14 +- drivers/usb/host/dwc_common_port/dwc_os.h | 2 + @@ -92009,7 +89039,7 @@ incarnations. drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c | 47 +- drivers/usb/host/dwc_otg/dwc_otg_dbg.h | 1 + drivers/usb/host/dwc_otg/dwc_otg_driver.c | 52 +- - drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 304 +++++++-- + drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 303 +++++++-- drivers/usb/host/dwc_otg/dwc_otg_hcd.h | 37 +- drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c | 3 +- drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h | 5 + @@ -92020,15 +89050,15 @@ incarnations. drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h | 48 ++ drivers/usb/host/dwc_otg/dwc_otg_os_dep.h | 3 + drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c | 2 +- - 26 files changed, 1548 insertions(+), 252 deletions(-) + 25 files changed, 1545 insertions(+), 252 deletions(-) create mode 100755 drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.c create mode 100755 drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index cb53c45..d0c3229 100644 +index 2b7243f..8303659 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -388,6 +388,7 @@ config ARCH_BCM2708 +@@ -392,6 +392,7 @@ config ARCH_BCM2708 select ARM_ERRATA_411920 select MACH_BCM2708 select VC4 @@ -92067,12 +89097,12 @@ index 3b763d6..5770408 100644 : "r" (flags) : "memory", "cc"); diff --git a/arch/arm/kernel/fiqasm.S b/arch/arm/kernel/fiqasm.S -index 207f9d6..5233d54 100644 +index 8dd26e1..eef4847 100644 --- a/arch/arm/kernel/fiqasm.S +++ b/arch/arm/kernel/fiqasm.S @@ -47,3 +47,7 @@ ENTRY(__get_fiq_regs) mov r0, r0 @ avoid hazard prior to ARMv4 - mov pc, lr + ret lr ENDPROC(__get_fiq_regs) + +ENTRY(__FIQ_Branch) @@ -92122,7 +89152,7 @@ index efade23..d4c5333 100644 return 0; } diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 16307ab..d0dfac5 100644 +index 7dd89a7f..dc59a6b 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c @@ -321,12 +321,32 @@ static struct resource bcm2708_usb_resources[] = { @@ -92160,7 +89190,7 @@ index 16307ab..d0dfac5 100644 static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); static struct platform_device bcm2708_usb_device = { -@@ -709,6 +729,11 @@ void __init bcm2708_init(void) +@@ -681,6 +701,11 @@ void __init bcm2708_init(void) #endif bcm_register_device(&bcm2708_systemtimer_device); bcm_register_device(&bcm2708_fb_device); @@ -92345,22 +89375,8 @@ index faf5d1a..4299054 100644 +#define NR_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_IRQS) #endif /* _BCM2708_IRQS_H_ */ -diff --git a/arch/arm/mach-bcm2708/include/mach/platform.h b/arch/arm/mach-bcm2708/include/mach/platform.h -index f4bb733..992a630 100644 ---- a/arch/arm/mach-bcm2708/include/mach/platform.h -+++ b/arch/arm/mach-bcm2708/include/mach/platform.h -@@ -56,7 +56,9 @@ - */ - - #define BCM2708_PERI_BASE 0x20000000 -+#define IC0_BASE (BCM2708_PERI_BASE + 0x2000) - #define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */ -+#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */ - #define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */ - #define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */ - #define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */ diff --git a/drivers/usb/host/dwc_common_port/dwc_common_linux.c b/drivers/usb/host/dwc_common_port/dwc_common_linux.c -index 440bcfc..6d01261 100644 +index 1668f10..5c50a8b 100644 --- a/drivers/usb/host/dwc_common_port/dwc_common_linux.c +++ b/drivers/usb/host/dwc_common_port/dwc_common_linux.c @@ -580,7 +580,13 @@ void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value) @@ -92377,7 +89393,7 @@ index 440bcfc..6d01261 100644 } #if 0 -@@ -991,6 +997,11 @@ void DWC_TASK_SCHEDULE(dwc_tasklet_t *task) +@@ -995,6 +1001,11 @@ void DWC_TASK_SCHEDULE(dwc_tasklet_t *task) tasklet_schedule(&task->t); } @@ -92419,10 +89435,10 @@ index 89cc325..4ce560d 100644 /* * Tail queue functions. diff --git a/drivers/usb/host/dwc_common_port/dwc_os.h b/drivers/usb/host/dwc_common_port/dwc_os.h -index 9ffe929..09ed244 100644 +index 8117731..a2bbe23 100644 --- a/drivers/usb/host/dwc_common_port/dwc_os.h +++ b/drivers/usb/host/dwc_common_port/dwc_os.h -@@ -981,6 +981,8 @@ extern void DWC_TASK_FREE(dwc_tasklet_t *task); +@@ -982,6 +982,8 @@ extern void DWC_TASK_FREE(dwc_tasklet_t *task); extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task); #define dwc_task_schedule DWC_TASK_SCHEDULE @@ -92730,7 +89746,7 @@ index ac2c846..f06c3d22 100644 * * The following parameters may be specified when starting the module. diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -index ab935c0..22300f0 100644 +index 1e89549..986d361 100644 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c @@ -40,10 +40,14 @@ @@ -93012,15 +90028,7 @@ index ab935c0..22300f0 100644 #ifdef DWC_DEV_SRPCAP if (dwc_otg_hcd->core_if->power_down == 2 && -@@ -845,6 +927,7 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) - dwc_hc_t *channel; - - hcd->lock = DWC_SPINLOCK_ALLOC(); -+ hcd->channel_lock = DWC_SPINLOCK_ALLOC(); - DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n", - hcd, core_if); - if (!hcd->lock) { -@@ -868,7 +951,7 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) +@@ -874,7 +956,7 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) DWC_LIST_INIT(&hcd->periodic_sched_ready); DWC_LIST_INIT(&hcd->periodic_sched_assigned); DWC_LIST_INIT(&hcd->periodic_sched_queued); @@ -93029,7 +90037,7 @@ index ab935c0..22300f0 100644 /* * Create a host channel descriptor for each host channel implemented * in the controller. Initialize the channel descriptor array. -@@ -906,6 +989,9 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) +@@ -912,6 +994,9 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) /* Initialize reset tasklet. */ hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd); @@ -93039,7 +90047,7 @@ index ab935c0..22300f0 100644 #ifdef DWC_DEV_SRPCAP if (hcd->core_if->power_down == 2) { /* Initialize Power on timer for Host power up in case hibernation */ -@@ -938,6 +1024,12 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) +@@ -944,6 +1029,12 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) hcd->frame_list = NULL; hcd->frame_list_dma = 0; hcd->periodic_qh_count = 0; @@ -93052,7 +90060,7 @@ index ab935c0..22300f0 100644 out: return retval; } -@@ -1083,7 +1175,12 @@ static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) +@@ -1089,7 +1180,12 @@ static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) uint32_t hub_addr, port_addr; hc->do_split = 1; hc->xact_pos = qtd->isoc_split_pos; @@ -93066,7 +90074,7 @@ index ab935c0..22300f0 100644 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr); hc->hub_addr = (uint8_t) hub_addr; hc->port_addr = (uint8_t) port_addr; -@@ -1230,6 +1327,65 @@ static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) +@@ -1236,6 +1332,65 @@ static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) hc->qh = qh; } @@ -93132,7 +90140,7 @@ index ab935c0..22300f0 100644 /** * This function selects transactions from the HCD transfer schedule and * assigns them to available host channels. It is called from HCD interrupt -@@ -1243,9 +1399,10 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) +@@ -1249,9 +1404,10 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) { dwc_list_link_t *qh_ptr; dwc_otg_qh_t *qh; @@ -93144,7 +90152,7 @@ index ab935c0..22300f0 100644 dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE; #ifdef DEBUG_SOF -@@ -1263,11 +1420,29 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) +@@ -1269,11 +1425,29 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) while (qh_ptr != &hcd->periodic_sched_ready && !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { @@ -93174,7 +90182,7 @@ index ab935c0..22300f0 100644 break; } hcd->available_host_channels--; -@@ -1288,8 +1463,6 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) +@@ -1294,8 +1468,6 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned, &qh->qh_list_entry); DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); @@ -93183,7 +90191,7 @@ index ab935c0..22300f0 100644 } /* -@@ -1304,6 +1477,31 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) +@@ -1310,6 +1482,31 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) num_channels - hcd->periodic_channels) && !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { @@ -93215,7 +90223,7 @@ index ab935c0..22300f0 100644 if (microframe_schedule) { DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); if (hcd->available_host_channels < 1) { -@@ -1316,7 +1514,6 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) +@@ -1322,7 +1519,6 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) last_sel_trans_num_nonper_scheduled++; #endif /* DEBUG_HOST_CHANNELS */ } @@ -93223,7 +90231,7 @@ index ab935c0..22300f0 100644 assign_and_init_hc(hcd, qh); -@@ -1330,21 +1527,22 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) +@@ -1336,21 +1532,22 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) &qh->qh_list_entry); DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); @@ -93253,7 +90261,7 @@ index ab935c0..22300f0 100644 return ret_val; } -@@ -1458,6 +1656,15 @@ static void process_periodic_channels(dwc_otg_hcd_t * hcd) +@@ -1464,6 +1661,15 @@ static void process_periodic_channels(dwc_otg_hcd_t * hcd) qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); @@ -93269,7 +90277,7 @@ index ab935c0..22300f0 100644 /* * Set a flag if we're queuing high-bandwidth in slave mode. * The flag prevents any halts to get into the request queue in -@@ -1587,6 +1794,15 @@ static void process_non_periodic_channels(dwc_otg_hcd_t * hcd) +@@ -1593,6 +1799,15 @@ static void process_non_periodic_channels(dwc_otg_hcd_t * hcd) qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry); @@ -93285,7 +90293,7 @@ index ab935c0..22300f0 100644 status = queue_transaction(hcd, qh->channel, tx_status.b.nptxfspcavail); -@@ -3112,17 +3328,13 @@ dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd, +@@ -3118,17 +3333,13 @@ dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd, else dwc_otg_urb = DWC_ALLOC(size); @@ -94698,7 +91706,7 @@ index e4787f5..ee8eec9 100644 usb_hcd_giveback_urb(hcd, urb); #else diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c -index 9761566..db95851 100644 +index 0a1cbb7..5c22b6c 100644 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c @@ -41,6 +41,7 @@ @@ -94709,7 +91717,7 @@ index 9761566..db95851 100644 extern bool microframe_schedule; -@@ -181,6 +182,7 @@ void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb) +@@ -182,6 +183,7 @@ void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb) if (microframe_schedule) qh->speed = dev_speed; @@ -94717,7 +91725,7 @@ index 9761566..db95851 100644 if (((dev_speed == USB_SPEED_LOW) || (dev_speed == USB_SPEED_FULL)) && -@@ -190,6 +192,7 @@ void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb) +@@ -191,6 +193,7 @@ void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb) dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr, hub_port); qh->do_split = 1; @@ -94725,7 +91733,7 @@ index 9761566..db95851 100644 } if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) { -@@ -572,6 +575,9 @@ static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) +@@ -573,6 +576,9 @@ static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) return status; } @@ -94735,7 +91743,7 @@ index 9761566..db95851 100644 /** * Schedules an interrupt or isochronous transfer in the periodic schedule. * -@@ -630,8 +636,13 @@ static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) +@@ -631,8 +637,13 @@ static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry); } else { @@ -94751,7 +91759,7 @@ index 9761566..db95851 100644 } if (!microframe_schedule) { -@@ -645,6 +656,7 @@ static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) +@@ -646,6 +657,7 @@ static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) return status; } @@ -94759,7 +91767,7 @@ index 9761566..db95851 100644 /** * This function adds a QH to either the non periodic or periodic schedule if * it is not already in the schedule. If the QH is already in the schedule, no -@@ -667,6 +679,7 @@ int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) +@@ -668,6 +680,7 @@ int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) /* Always start in the inactive schedule. */ DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive, &qh->qh_list_entry); @@ -94767,7 +91775,7 @@ index 9761566..db95851 100644 } else { status = schedule_periodic(hcd, qh); if ( !hcd->periodic_qh_count ) { -@@ -726,6 +739,9 @@ void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) +@@ -727,6 +740,9 @@ void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) hcd->non_periodic_qh_ptr->next; } DWC_LIST_REMOVE_INIT(&qh->qh_list_entry); @@ -94777,7 +91785,7 @@ index 9761566..db95851 100644 } else { deschedule_periodic(hcd, qh); hcd->periodic_qh_count--; -@@ -754,6 +770,24 @@ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, +@@ -755,6 +771,24 @@ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int sched_next_periodic_split) { if (dwc_qh_is_non_per(qh)) { @@ -94802,7 +91810,7 @@ index 9761566..db95851 100644 dwc_otg_hcd_qh_remove(hcd, qh); if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { /* Add back to inactive non-periodic schedule. */ -@@ -767,6 +801,7 @@ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, +@@ -768,6 +802,7 @@ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, if (sched_next_periodic_split) { qh->sched_frame = frame_number; @@ -94810,7 +91818,7 @@ index 9761566..db95851 100644 if (dwc_frame_num_le(frame_number, dwc_frame_num_inc (qh->start_split_frame, -@@ -815,6 +850,11 @@ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, +@@ -816,6 +851,11 @@ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, &qh->qh_list_entry); } else { @@ -94822,7 +91830,7 @@ index 9761566..db95851 100644 DWC_LIST_MOVE_HEAD (&hcd->periodic_sched_inactive, &qh->qh_list_entry); -@@ -879,6 +919,7 @@ void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb) +@@ -880,6 +920,7 @@ void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb) * QH to place the QTD into. If it does not find a QH, then it will create a * new QH. If the QH to which the QTD is added is not currently scheduled, it * is placed into the proper schedule based on its EP type. @@ -94830,7 +91838,7 @@ index 9761566..db95851 100644 * * @param[in] qtd The QTD to add * @param[in] hcd The DWC HCD structure -@@ -891,8 +932,6 @@ int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, +@@ -892,8 +933,6 @@ int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh, int atomic_alloc) { int retval = 0; @@ -94839,7 +91847,7 @@ index 9761566..db95851 100644 dwc_otg_hcd_urb_t *urb = qtd->urb; /* -@@ -902,18 +941,16 @@ int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, +@@ -903,18 +942,16 @@ int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, if (*qh == NULL) { *qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc); if (*qh == NULL) { @@ -95061,10 +92069,10 @@ index 1b1f83c..c8590b5 100644 if (status.b.sr) { -From 67aabc6b5dd6e3bb605ba2bca7952ec39e22e178 Mon Sep 17 00:00:00 2001 +From 918d8d80064d99000e52a25b77efacf5337f6a57 Mon Sep 17 00:00:00 2001 From: P33M Date: Wed, 19 Mar 2014 12:58:23 +0000 -Subject: [PATCH 27/94] dwc_otg: fiq_fsm: Base commit for driver rewrite +Subject: [PATCH 26/82] dwc_otg: fiq_fsm: Base commit for driver rewrite This commit removes the previous FIQ fixes entirely and adds fiq_fsm. @@ -95185,7 +92193,7 @@ fiq_fsm: Enable by default delete mode 100755 drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index d0dfac5..a6eb08e 100644 +index dc59a6b..a740344 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c @@ -330,22 +330,13 @@ static struct resource bcm2708_usb_resources[] = { @@ -95216,7 +92224,7 @@ index d0dfac5..a6eb08e 100644 static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); -@@ -729,11 +720,6 @@ void __init bcm2708_init(void) +@@ -701,11 +692,6 @@ void __init bcm2708_init(void) #endif bcm_register_device(&bcm2708_systemtimer_device); bcm_register_device(&bcm2708_fb_device); @@ -97219,7 +94227,7 @@ index 0000000..8cfe364 +END(_dwc_otg_fiq_stub) + diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -index 22300f0..daea770 100644 +index 986d361..ebc3553 100644 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c @@ -45,9 +45,10 @@ @@ -97369,7 +94377,7 @@ index 22300f0..daea770 100644 #ifdef DWC_DEV_SRPCAP if (dwc_otg_hcd->core_if->power_down == 2 && -@@ -979,6 +1004,59 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) +@@ -984,6 +1009,59 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) channel); } @@ -97429,7 +94437,7 @@ index 22300f0..daea770 100644 /* Initialize the Connection timeout timer. */ hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer", dwc_otg_hcd_connect_timeout, 0); -@@ -1176,7 +1254,8 @@ static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) +@@ -1181,7 +1259,8 @@ static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) hc->do_split = 1; hc->xact_pos = qtd->isoc_split_pos; /* We don't need to do complete splits anymore */ @@ -97439,7 +94447,7 @@ index 22300f0..daea770 100644 hc->complete_split = qtd->complete_split = 0; else hc->complete_split = qtd->complete_split; -@@ -1327,62 +1406,487 @@ static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) +@@ -1332,62 +1411,487 @@ static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) hc->qh = qh; } @@ -97966,7 +94974,7 @@ index 22300f0..daea770 100644 } -@@ -1399,16 +1903,11 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) +@@ -1404,16 +1908,11 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) { dwc_list_link_t *qh_ptr; dwc_otg_qh_t *qh; @@ -97983,7 +94991,7 @@ index 22300f0..daea770 100644 #ifdef DEBUG_HOST_CHANNELS last_sel_trans_num_per_scheduled = 0; last_sel_trans_num_nonper_scheduled = 0; -@@ -1423,26 +1922,11 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) +@@ -1428,26 +1927,11 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); @@ -98010,7 +95018,7 @@ index 22300f0..daea770 100644 break; } hcd->available_host_channels--; -@@ -1478,27 +1962,24 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) +@@ -1483,27 +1967,24 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); @@ -98051,7 +95059,7 @@ index 22300f0..daea770 100644 } } -@@ -1527,12 +2008,31 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) +@@ -1532,12 +2013,31 @@ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) &qh->qh_list_entry); DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); @@ -98085,7 +95093,7 @@ index 22300f0..daea770 100644 if(!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) ret_val |= DWC_OTG_TRANSACTION_PERIODIC; -@@ -1577,6 +2077,12 @@ static int queue_transaction(dwc_otg_hcd_t * hcd, +@@ -1582,6 +2082,12 @@ static int queue_transaction(dwc_otg_hcd_t * hcd, hc->qh->ping_state = 0; } } else if (!hc->xfer_started) { @@ -98098,7 +95106,7 @@ index 22300f0..daea770 100644 dwc_otg_hc_start_transfer(hcd->core_if, hc); hc->qh->ping_state = 0; } -@@ -1629,7 +2135,7 @@ static void process_periodic_channels(dwc_otg_hcd_t * hcd) +@@ -1634,7 +2140,7 @@ static void process_periodic_channels(dwc_otg_hcd_t * hcd) hptxsts_data_t tx_status; dwc_list_link_t *qh_ptr; dwc_otg_qh_t *qh; @@ -98107,7 +95115,7 @@ index 22300f0..daea770 100644 int no_queue_space = 0; int no_fifo_space = 0; -@@ -1658,27 +2164,34 @@ static void process_periodic_channels(dwc_otg_hcd_t * hcd) +@@ -1663,27 +2169,34 @@ static void process_periodic_channels(dwc_otg_hcd_t * hcd) // Do not send a split start transaction any later than frame .6 // Note, we have to schedule a periodic in .5 to make it go in .6 @@ -98158,7 +95166,7 @@ index 22300f0..daea770 100644 } /* -@@ -1795,25 +2308,19 @@ static void process_non_periodic_channels(dwc_otg_hcd_t * hcd) +@@ -1800,25 +2313,19 @@ static void process_non_periodic_channels(dwc_otg_hcd_t * hcd) qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry); @@ -99647,7 +96655,7 @@ index ee8eec9..07b1808 100644 #ifdef DEBUG diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c -index db95851..8706a5c 100644 +index 5c22b6c..17d3030 100644 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c @@ -41,7 +41,6 @@ @@ -99658,7 +96666,7 @@ index db95851..8706a5c 100644 extern bool microframe_schedule; -@@ -576,7 +575,6 @@ static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) +@@ -577,7 +576,6 @@ static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) } @@ -99666,7 +96674,7 @@ index db95851..8706a5c 100644 /** * Schedules an interrupt or isochronous transfer in the periodic schedule. -@@ -636,9 +634,9 @@ static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) +@@ -637,9 +635,9 @@ static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry); } else { @@ -99678,7 +96686,7 @@ index db95851..8706a5c 100644 } /* Always start in the inactive schedule. */ -@@ -679,7 +677,7 @@ int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) +@@ -680,7 +678,7 @@ int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) /* Always start in the inactive schedule. */ DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive, &qh->qh_list_entry); @@ -99687,7 +96695,7 @@ index db95851..8706a5c 100644 } else { status = schedule_periodic(hcd, qh); if ( !hcd->periodic_qh_count ) { -@@ -739,13 +737,12 @@ void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) +@@ -740,13 +738,12 @@ void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) hcd->non_periodic_qh_ptr->next; } DWC_LIST_REMOVE_INIT(&qh->qh_list_entry); @@ -99704,7 +96712,7 @@ index db95851..8706a5c 100644 intr_mask.b.sofintr = 1; DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0); -@@ -770,28 +767,11 @@ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, +@@ -771,28 +768,11 @@ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int sched_next_periodic_split) { if (dwc_qh_is_non_per(qh)) { @@ -99734,7 +96742,7 @@ index db95851..8706a5c 100644 } } else { uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd); -@@ -850,9 +830,9 @@ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, +@@ -851,9 +831,9 @@ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, &qh->qh_list_entry); } else { @@ -99746,7 +96754,7 @@ index db95851..8706a5c 100644 } DWC_LIST_MOVE_HEAD -@@ -943,6 +923,9 @@ int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, +@@ -944,6 +924,9 @@ int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, if (*qh == NULL) { retval = -DWC_E_NO_MEMORY; goto done; @@ -99960,10 +96968,10 @@ index 5d310df..4b32941 100644 return -EBUSY; } -From 9c51ea5408ebf250f609d9eab680207cb01cab9e Mon Sep 17 00:00:00 2001 +From e38fd6510256d509c5487925bb29ba8940ce0d76 Mon Sep 17 00:00:00 2001 From: Vincent Sanders Date: Wed, 30 Jan 2013 12:45:18 +0000 -Subject: [PATCH 28/94] bcm2835: add v4l2 camera device +Subject: [PATCH 27/82] bcm2835: add v4l2 camera device - Supports raw YUV capture, preview, JPEG and H264. - Uses videobuf2 for data transfer, using dma_buf. @@ -99979,7 +96987,7 @@ Signed-off-by: Luke Diamand drivers/media/platform/Makefile | 2 + drivers/media/platform/bcm2835/Kconfig | 25 + drivers/media/platform/bcm2835/Makefile | 5 + - drivers/media/platform/bcm2835/bcm2835-camera.c | 1478 +++++++++++++++++ + drivers/media/platform/bcm2835/bcm2835-camera.c | 1476 +++++++++++++++++ drivers/media/platform/bcm2835/bcm2835-camera.h | 113 ++ drivers/media/platform/bcm2835/controls.c | 725 ++++++++ drivers/media/platform/bcm2835/mmal-common.h | 52 + @@ -99991,7 +96999,7 @@ Signed-off-by: Luke Diamand drivers/media/platform/bcm2835/mmal-parameters.h | 539 ++++++ drivers/media/platform/bcm2835/mmal-vchiq.c | 1916 ++++++++++++++++++++++ drivers/media/platform/bcm2835/mmal-vchiq.h | 178 ++ - 17 files changed, 5829 insertions(+) + 17 files changed, 5827 insertions(+) create mode 100644 Documentation/video4linux/bcm2835-v4l2.txt create mode 100644 drivers/media/platform/bcm2835/Kconfig create mode 100644 drivers/media/platform/bcm2835/Makefile @@ -100075,10 +97083,10 @@ index 0000000..c585a8f + +$ v4l2-ctl --list-formats diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig -index 8108c69..76c70d6 100644 +index 6d86646..06069fa 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig -@@ -120,6 +120,7 @@ config VIDEO_S3C_CAMIF +@@ -121,6 +121,7 @@ config VIDEO_S3C_CAMIF source "drivers/media/platform/soc_camera/Kconfig" source "drivers/media/platform/exynos4-is/Kconfig" source "drivers/media/platform/s5p-tv/Kconfig" @@ -100141,10 +97149,10 @@ index 0000000..f17c79c +ccflags-$(CONFIG_VIDEO_BCM2835) += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel -D__VCCOREVER__=0x04000000 diff --git a/drivers/media/platform/bcm2835/bcm2835-camera.c b/drivers/media/platform/bcm2835/bcm2835-camera.c new file mode 100644 -index 0000000..b805c03 +index 0000000..1c9d9d5 --- /dev/null +++ b/drivers/media/platform/bcm2835/bcm2835-camera.c -@@ -0,0 +1,1478 @@ +@@ -0,0 +1,1476 @@ +/* + * Broadcom BM2835 V4L2 driver + * @@ -101466,8 +98474,6 @@ index 0000000..b805c03 + + vfd->queue = &dev->capture.vb_vidq; + -+ set_bit(V4L2_FL_USE_FH_PRIO, &vfd->flags); -+ + /* video device needs to be able to access instance data */ + video_set_drvdata(vfd, dev); + @@ -105948,10 +102954,10 @@ index 0000000..9d1d11e + +#endif /* MMAL_VCHIQ_H */ -From 955f36274d222d969074b99d38ad11b6b5facede Mon Sep 17 00:00:00 2001 +From 3fecd7e096c3e2d8fae870e4aa42547fb30a7a4b Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Mon, 9 Dec 2013 10:58:01 +0000 -Subject: [PATCH 29/94] V4L2: Fixes from 6by9 +Subject: [PATCH 28/82] V4L2: Fixes from 6by9 V4L2: Fix EV values. Add manual shutter speed control @@ -106181,10 +103187,10 @@ Signed-off-by: Dave Stevenson 8 files changed, 1292 insertions(+), 178 deletions(-) diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 11c6f8f..0c58172 100644 +index 6ce900c..d77317c 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -696,6 +696,9 @@ CONFIG_DVB_B2C2_FLEXCOP_USB=m +@@ -686,6 +686,9 @@ CONFIG_DVB_B2C2_FLEXCOP_USB=m CONFIG_VIDEO_EM28XX=m CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m @@ -106195,7 +103201,7 @@ index 11c6f8f..0c58172 100644 CONFIG_USB_SI470X=m CONFIG_I2C_SI470X=m diff --git a/drivers/media/platform/bcm2835/bcm2835-camera.c b/drivers/media/platform/bcm2835/bcm2835-camera.c -index b805c03..c0826aa 100644 +index 1c9d9d5..33fa37c 100644 --- a/drivers/media/platform/bcm2835/bcm2835-camera.c +++ b/drivers/media/platform/bcm2835/bcm2835-camera.c @@ -36,7 +36,8 @@ @@ -106994,7 +104000,7 @@ index b805c03..c0826aa 100644 vfd->v4l2_dev = &dev->v4l2_dev; -@@ -1328,8 +1673,9 @@ static int __init bm2835_mmal_init_device(struct bm2835_mmal_dev *dev, +@@ -1326,8 +1671,9 @@ static int __init bm2835_mmal_init_device(struct bm2835_mmal_dev *dev, if (ret < 0) return ret; @@ -107006,7 +104012,7 @@ index b805c03..c0826aa 100644 return 0; } -@@ -1337,9 +1683,9 @@ static int __init bm2835_mmal_init_device(struct bm2835_mmal_dev *dev, +@@ -1335,9 +1681,9 @@ static int __init bm2835_mmal_init_device(struct bm2835_mmal_dev *dev, static struct v4l2_format default_v4l2_format = { .fmt.pix.pixelformat = V4L2_PIX_FMT_JPEG, .fmt.pix.width = 1024, @@ -107018,7 +104024,7 @@ index b805c03..c0826aa 100644 }; static int __init bm2835_mmal_init(void) -@@ -1402,6 +1748,9 @@ static int __init bm2835_mmal_init(void) +@@ -1400,6 +1746,9 @@ static int __init bm2835_mmal_init(void) if (ret < 0) goto unreg_dev; @@ -108323,27 +105329,63 @@ index a06fb44..76f249e 100644 release_msg: -From 951d2a7db1e94e10c47f4146b5aa89ebed472b99 Mon Sep 17 00:00:00 2001 +From a61195e6feea9ca5929e46e5820b49d1e10272e5 Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 14:22:53 +0100 -Subject: [PATCH 30/94] dmaengine: Add support for BCM2708 +Subject: [PATCH 29/82] dmaengine: Add support for BCM2708 Add support for DMA controller of BCM2708 as used in the Raspberry Pi. Currently it only supports cyclic DMA. Signed-off-by: Florian Meier + +dmaengine: expand functionality by supporting scatter/gather transfers sdhci-bcm2708 and dma.c: fix for LITE channels --- - drivers/dma/Kconfig | 6 + - drivers/dma/Makefile | 1 + - drivers/dma/bcm2708-dmaengine.c | 588 ++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 595 insertions(+) + arch/arm/mach-bcm2708/dma.c | 2 + + arch/arm/mach-bcm2708/include/mach/dma.h | 6 +- + drivers/dma/Kconfig | 6 + + drivers/dma/Makefile | 1 + + drivers/dma/bcm2708-dmaengine.c | 1041 ++++++++++++++++++++++++++++++ + 5 files changed, 1055 insertions(+), 1 deletion(-) create mode 100644 drivers/dma/bcm2708-dmaengine.c +diff --git a/arch/arm/mach-bcm2708/dma.c b/arch/arm/mach-bcm2708/dma.c +index 1da2413..a5e58d1 100644 +--- a/arch/arm/mach-bcm2708/dma.c ++++ b/arch/arm/mach-bcm2708/dma.c +@@ -156,6 +156,8 @@ static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base, + dmaman->chan_available = chans_available; + dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* chans 2 & 3 */ + dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* chan 0 */ ++ dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe; /* chans 1 to 7 */ ++ dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00; /* chans 8 to 14 */ + } + + static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman, +diff --git a/arch/arm/mach-bcm2708/include/mach/dma.h b/arch/arm/mach-bcm2708/include/mach/dma.h +index a4aac4c..d03e7b5 100644 +--- a/arch/arm/mach-bcm2708/include/mach/dma.h ++++ b/arch/arm/mach-bcm2708/include/mach/dma.h +@@ -77,9 +77,13 @@ extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base); + those with higher priority smaller ordinal numbers */ + #define BCM_DMA_FEATURE_FAST_ORD 0 + #define BCM_DMA_FEATURE_BULK_ORD 1 ++#define BCM_DMA_FEATURE_NORMAL_ORD 2 ++#define BCM_DMA_FEATURE_LITE_ORD 3 + #define BCM_DMA_FEATURE_FAST (1< -+ * Copyright 2013 ++ * Gellert Weisz ++ * Copyright 2013-2014 + * + * Based on + * OMAP DMAengine support by Russell King @@ -108405,6 +105447,7 @@ index 0000000..b244293 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ ++ +#include +#include +#include @@ -108416,21 +105459,40 @@ index 0000000..b244293 +#include +#include +#include -+#include ++ ++#ifndef CONFIG_OF ++ ++/* dma manager */ ++#include ++ ++//#define DMA_COMPLETE DMA_SUCCESS ++ ++#endif ++ ++#include ++#include + +#include "virt-dma.h" + -+#include -+#include + -+struct bcm2708_dmadev { ++struct bcm2835_dmadev { + struct dma_device ddev; + spinlock_t lock; + void __iomem *base; + struct device_dma_parameters dma_parms; +}; + -+struct bcm2708_chan { ++struct bcm2835_dma_cb { ++ uint32_t info; ++ uint32_t src; ++ uint32_t dst; ++ uint32_t length; ++ uint32_t stride; ++ uint32_t next; ++ uint32_t pad[2]; ++}; ++ ++struct bcm2835_chan { + struct virt_dma_chan vc; + struct list_head node; + @@ -108438,48 +105500,106 @@ index 0000000..b244293 + bool cyclic; + + int ch; -+ struct bcm2708_desc *desc; ++ struct bcm2835_desc *desc; + + void __iomem *chan_base; + int irq_number; ++ ++ unsigned int dreq; +}; + -+struct bcm2708_desc { ++struct bcm2835_desc { + struct virt_dma_desc vd; + enum dma_transfer_direction dir; + + unsigned int control_block_size; -+ struct bcm2708_dma_cb *control_block_base; ++ struct bcm2835_dma_cb *control_block_base; + dma_addr_t control_block_base_phys; + -+ unsigned frames; ++ unsigned int frames; + size_t size; +}; + -+#define BCM2708_DMA_DATA_TYPE_S8 1 -+#define BCM2708_DMA_DATA_TYPE_S16 2 -+#define BCM2708_DMA_DATA_TYPE_S32 4 -+#define BCM2708_DMA_DATA_TYPE_S128 16 ++#define BCM2835_DMA_CS 0x00 ++#define BCM2835_DMA_ADDR 0x04 ++#define BCM2835_DMA_SOURCE_AD 0x0c ++#define BCM2835_DMA_DEST_AD 0x10 ++#define BCM2835_DMA_NEXTCB 0x1C + -+static inline struct bcm2708_dmadev *to_bcm2708_dma_dev(struct dma_device *d) ++/* DMA CS Control and Status bits */ ++#define BCM2835_DMA_ACTIVE BIT(0) ++#define BCM2835_DMA_INT BIT(2) ++#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */ ++#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */ ++#define BCM2835_DMA_ERR BIT(8) ++#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */ ++#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */ ++ ++#define BCM2835_DMA_INT_EN BIT(0) ++#define BCM2835_DMA_WAIT_RESP BIT(3) ++#define BCM2835_DMA_D_INC BIT(4) ++#define BCM2835_DMA_D_WIDTH BIT(5) ++#define BCM2835_DMA_D_DREQ BIT(6) ++#define BCM2835_DMA_S_INC BIT(8) ++#define BCM2835_DMA_S_WIDTH BIT(9) ++#define BCM2835_DMA_S_DREQ BIT(10) ++ ++#define BCM2835_DMA_PER_MAP(x) ((x) << 16) ++#define BCM2835_DMA_WAITS(x) (((x)&0x1f) << 21) ++ ++#define SDHCI_BCM_DMA_WAITS 20 /* delays slowing DMA transfers: 0-31 */ ++ ++#define BCM2835_DMA_DATA_TYPE_S8 1 ++#define BCM2835_DMA_DATA_TYPE_S16 2 ++#define BCM2835_DMA_DATA_TYPE_S32 4 ++#define BCM2835_DMA_DATA_TYPE_S128 16 ++ ++#define BCM2835_DMA_BULK_MASK BIT(0) ++#define BCM2835_DMA_FIQ_MASK (BIT(2) | BIT(3)) ++ ++ ++/* Valid only for channels 0 - 14, 15 has its own base address */ ++#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */ ++#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n)) ++ ++#define MAX_LITE_TRANSFER 32768 ++#define MAX_NORMAL_TRANSFER 1073741824 ++ ++static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d) +{ -+ return container_of(d, struct bcm2708_dmadev, ddev); ++ return container_of(d, struct bcm2835_dmadev, ddev); +} + -+static inline struct bcm2708_chan *to_bcm2708_dma_chan(struct dma_chan *c) ++static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c) +{ -+ return container_of(c, struct bcm2708_chan, vc.chan); ++ return container_of(c, struct bcm2835_chan, vc.chan); +} + -+static inline struct bcm2708_desc *to_bcm2708_dma_desc( ++static inline struct bcm2835_desc *to_bcm2835_dma_desc( + struct dma_async_tx_descriptor *t) +{ -+ return container_of(t, struct bcm2708_desc, vd.tx); ++ return container_of(t, struct bcm2835_desc, vd.tx); +} + -+static void bcm2708_dma_desc_free(struct virt_dma_desc *vd) ++static void dma_dumpregs(struct bcm2835_chan *c) +{ -+ struct bcm2708_desc *desc = container_of(vd, struct bcm2708_desc, vd); ++ pr_debug("-------------DMA DUMPREGS-------------\n"); ++ pr_debug("CS= %u\n", ++ readl(c->chan_base + BCM2835_DMA_CS)); ++ pr_debug("ADDR= %u\n", ++ readl(c->chan_base + BCM2835_DMA_ADDR)); ++ pr_debug("SOURCE_ADDR= %u\n", ++ readl(c->chan_base + BCM2835_DMA_SOURCE_AD)); ++ pr_debug("DEST_AD= %u\n", ++ readl(c->chan_base + BCM2835_DMA_DEST_AD)); ++ pr_debug("NEXTCB= %u\n", ++ readl(c->chan_base + BCM2835_DMA_NEXTCB)); ++ pr_debug("--------------------------------------\n"); ++} ++ ++static void bcm2835_dma_desc_free(struct virt_dma_desc *vd) ++{ ++ struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd); + dma_free_coherent(desc->vd.tx.chan->device->dev, + desc->control_block_size, + desc->control_block_base, @@ -108487,10 +105607,46 @@ index 0000000..b244293 + kfree(desc); +} + -+static void bcm2708_dma_start_desc(struct bcm2708_chan *c) ++static int bcm2835_dma_abort(void __iomem *chan_base) ++{ ++ unsigned long cs; ++ long int timeout = 10000; ++ ++ cs = readl(chan_base + BCM2835_DMA_CS); ++ if (!(cs & BCM2835_DMA_ACTIVE)) ++ return 0; ++ ++ /* Write 0 to the active bit - Pause the DMA */ ++ writel(0, chan_base + BCM2835_DMA_CS); ++ ++ /* Wait for any current AXI transfer to complete */ ++ while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) { ++ cpu_relax(); ++ cs = readl(chan_base + BCM2835_DMA_CS); ++ } ++ ++ /* We'll un-pause when we set of our next DMA */ ++ if (!timeout) ++ return -ETIMEDOUT; ++ ++ if (!(cs & BCM2835_DMA_ACTIVE)) ++ return 0; ++ ++ /* Terminate the control block chain */ ++ writel(0, chan_base + BCM2835_DMA_NEXTCB); ++ ++ /* Abort the whole DMA */ ++ writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE, ++ chan_base + BCM2835_DMA_CS); ++ ++ return 0; ++} ++ ++ ++static void bcm2835_dma_start_desc(struct bcm2835_chan *c) +{ + struct virt_dma_desc *vd = vchan_next_desc(&c->vc); -+ struct bcm2708_desc *d; ++ struct bcm2835_desc *d; + + if (!vd) { + c->desc = NULL; @@ -108499,49 +105655,62 @@ index 0000000..b244293 + + list_del(&vd->node); + -+ c->desc = d = to_bcm2708_dma_desc(&vd->tx); ++ c->desc = d = to_bcm2835_dma_desc(&vd->tx); ++ ++ writel(d->control_block_base_phys, c->chan_base + BCM2835_DMA_ADDR); ++ writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); + -+ bcm_dma_start(c->chan_base, d->control_block_base_phys); +} + -+static irqreturn_t bcm2708_dma_callback(int irq, void *data) ++static irqreturn_t bcm2835_dma_callback(int irq, void *data) +{ -+ struct bcm2708_chan *c = data; -+ struct bcm2708_desc *d; ++ struct bcm2835_chan *c = data; ++ struct bcm2835_desc *d; + unsigned long flags; + + spin_lock_irqsave(&c->vc.lock, flags); + + /* Acknowledge interrupt */ -+ writel(BCM2708_DMA_INT, c->chan_base + BCM2708_DMA_CS); ++ writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS); + + d = c->desc; + + if (d) { -+ /* TODO Only works for cyclic DMA */ -+ vchan_cyclic_callback(&d->vd); -+ } ++ if (c->cyclic) { ++ vchan_cyclic_callback(&d->vd); + -+ /* Keep the DMA engine running */ -+ dsb(); /* ARM synchronization barrier */ -+ writel(BCM2708_DMA_ACTIVE, c->chan_base + BCM2708_DMA_CS); ++ /* Keep the DMA engine running */ ++ writel(BCM2835_DMA_ACTIVE, ++ c->chan_base + BCM2835_DMA_CS); ++ ++ } else { ++ vchan_cookie_complete(&c->desc->vd); ++ bcm2835_dma_start_desc(c); ++ } ++ } + + spin_unlock_irqrestore(&c->vc.lock, flags); + + return IRQ_HANDLED; +} + -+static int bcm2708_dma_alloc_chan_resources(struct dma_chan *chan) ++static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan) +{ -+ struct bcm2708_chan *c = to_bcm2708_dma_chan(chan); ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ int ret; + -+ return request_irq(c->irq_number, -+ bcm2708_dma_callback, 0, "DMA IRQ", c); ++ dev_dbg(c->vc.chan.device->dev, ++ "Allocating DMA channel %d\n", c->ch); ++ ++ ret = request_irq(c->irq_number, ++ bcm2835_dma_callback, 0, "DMA IRQ", c); ++ ++ return ret; +} + -+static void bcm2708_dma_free_chan_resources(struct dma_chan *chan) ++static void bcm2835_dma_free_chan_resources(struct dma_chan *chan) +{ -+ struct bcm2708_chan *c = to_bcm2708_dma_chan(chan); ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); + + vchan_free_chan_resources(&c->vc); + free_irq(c->irq_number, c); @@ -108549,18 +105718,18 @@ index 0000000..b244293 + dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch); +} + -+static size_t bcm2708_dma_desc_size(struct bcm2708_desc *d) ++static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d) +{ + return d->size; +} + -+static size_t bcm2708_dma_desc_size_pos(struct bcm2708_desc *d, dma_addr_t addr) ++static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr) +{ -+ unsigned i; ++ unsigned int i; + size_t size; + + for (size = i = 0; i < d->frames; i++) { -+ struct bcm2708_dma_cb *control_block = ++ struct bcm2835_dma_cb *control_block = + &d->control_block_base[i]; + size_t this_size = control_block->length; + dma_addr_t dma; @@ -108579,13 +105748,15 @@ index 0000000..b244293 + return size; +} + -+static enum dma_status bcm2708_dma_tx_status(struct dma_chan *chan, ++static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, struct dma_tx_state *txstate) +{ -+ struct bcm2708_chan *c = to_bcm2708_dma_chan(chan); ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ struct bcm2835_desc *d; + struct virt_dma_desc *vd; + enum dma_status ret; + unsigned long flags; ++ dma_addr_t pos; + + ret = dma_cookie_status(chan, cookie, txstate); + if (ret == DMA_COMPLETE || !txstate) @@ -108595,19 +105766,18 @@ index 0000000..b244293 + vd = vchan_find_desc(&c->vc, cookie); + if (vd) { + txstate->residue = -+ bcm2708_dma_desc_size(to_bcm2708_dma_desc(&vd->tx)); ++ bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx)); + } else if (c->desc && c->desc->vd.tx.cookie == cookie) { -+ struct bcm2708_desc *d = c->desc; -+ dma_addr_t pos; ++ d = c->desc; + + if (d->dir == DMA_MEM_TO_DEV) -+ pos = readl(c->chan_base + BCM2708_DMA_SOURCE_AD); ++ pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD); + else if (d->dir == DMA_DEV_TO_MEM) -+ pos = readl(c->chan_base + BCM2708_DMA_DEST_AD); ++ pos = readl(c->chan_base + BCM2835_DMA_DEST_AD); + else + pos = 0; + -+ txstate->residue = bcm2708_dma_desc_size_pos(d, pos); ++ txstate->residue = bcm2835_dma_desc_size_pos(d, pos); + } else { + txstate->residue = 0; + } @@ -108617,50 +105787,50 @@ index 0000000..b244293 + return ret; +} + -+static void bcm2708_dma_issue_pending(struct dma_chan *chan) ++static void bcm2835_dma_issue_pending(struct dma_chan *chan) +{ -+ struct bcm2708_chan *c = to_bcm2708_dma_chan(chan); ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); + unsigned long flags; + -+ c->cyclic = true; /* Nothing else is implemented */ -+ + spin_lock_irqsave(&c->vc.lock, flags); + if (vchan_issue_pending(&c->vc) && !c->desc) -+ bcm2708_dma_start_desc(c); ++ bcm2835_dma_start_desc(c); + + spin_unlock_irqrestore(&c->vc.lock, flags); +} + -+static struct dma_async_tx_descriptor *bcm2708_dma_prep_dma_cyclic( ++static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( + struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, + size_t period_len, enum dma_transfer_direction direction, -+ unsigned long flags, void *context) ++ unsigned long flags) +{ -+ struct bcm2708_chan *c = to_bcm2708_dma_chan(chan); ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); + enum dma_slave_buswidth dev_width; -+ struct bcm2708_desc *d; ++ struct bcm2835_desc *d; + dma_addr_t dev_addr; -+ unsigned es, sync_type; -+ unsigned frame; ++ unsigned int es, sync_type; ++ unsigned int frame; + + /* Grab configuration */ ++ if (!is_slave_direction(direction)) { ++ dev_err(chan->device->dev, "%s: bad direction?\n", __func__); ++ return NULL; ++ } ++ + if (direction == DMA_DEV_TO_MEM) { + dev_addr = c->cfg.src_addr; + dev_width = c->cfg.src_addr_width; -+ sync_type = BCM2708_DMA_S_DREQ; -+ } else if (direction == DMA_MEM_TO_DEV) { ++ sync_type = BCM2835_DMA_S_DREQ; ++ } else { + dev_addr = c->cfg.dst_addr; + dev_width = c->cfg.dst_addr_width; -+ sync_type = BCM2708_DMA_D_DREQ; -+ } else { -+ dev_err(chan->device->dev, "%s: bad direction?\n", __func__); -+ return NULL; ++ sync_type = BCM2835_DMA_D_DREQ; + } + + /* Bus width translates to the element size (ES) */ + switch (dev_width) { + case DMA_SLAVE_BUSWIDTH_4_BYTES: -+ es = BCM2708_DMA_DATA_TYPE_S32; ++ es = BCM2835_DMA_DATA_TYPE_S32; + break; + default: + return NULL; @@ -108675,7 +105845,7 @@ index 0000000..b244293 + d->frames = buf_len / period_len; + + /* Allocate memory for control blocks */ -+ d->control_block_size = d->frames * sizeof(struct bcm2708_dma_cb); ++ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb); + d->control_block_base = dma_zalloc_coherent(chan->device->dev, + d->control_block_size, &d->control_block_base_phys, + GFP_NOWAIT); @@ -108690,22 +105860,22 @@ index 0000000..b244293 + * for each frame and link them together. + */ + for (frame = 0; frame < d->frames; frame++) { -+ struct bcm2708_dma_cb *control_block = ++ struct bcm2835_dma_cb *control_block = + &d->control_block_base[frame]; + + /* Setup adresses */ + if (d->dir == DMA_DEV_TO_MEM) { -+ control_block->info = BCM2708_DMA_D_INC; ++ control_block->info = BCM2835_DMA_D_INC; + control_block->src = dev_addr; + control_block->dst = buf_addr + frame * period_len; + } else { -+ control_block->info = BCM2708_DMA_S_INC; ++ control_block->info = BCM2835_DMA_S_INC; + control_block->src = buf_addr + frame * period_len; + control_block->dst = dev_addr; + } + + /* Enable interrupt */ -+ control_block->info |= BCM2708_DMA_INT_EN; ++ control_block->info |= BCM2835_DMA_INT_EN; + + /* Setup synchronization */ + if (sync_type != 0) @@ -108714,7 +105884,7 @@ index 0000000..b244293 + /* Setup DREQ channel */ + if (c->cfg.slave_id != 0) + control_block->info |= -+ BCM2708_DMA_PER_MAP(c->cfg.slave_id); ++ BCM2835_DMA_PER_MAP(c->cfg.slave_id); + + /* Length of a frame */ + control_block->length = period_len; @@ -108722,18 +105892,166 @@ index 0000000..b244293 + + /* + * Next block is the next frame. -+ * This DMA engine driver currently only supports cyclic DMA. ++ * This function is called on cyclic DMA transfers. + * Therefore, wrap around at number of frames. + */ + control_block->next = d->control_block_base_phys + -+ sizeof(struct bcm2708_dma_cb) ++ sizeof(struct bcm2835_dma_cb) + * ((frame + 1) % d->frames); + } + ++ c->cyclic = true; ++ + return vchan_tx_prep(&c->vc, &d->vd, flags); +} + -+static int bcm2708_dma_slave_config(struct bcm2708_chan *c, ++ ++static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg( ++ struct dma_chan *chan, struct scatterlist *sgl, ++ unsigned int sg_len, enum dma_transfer_direction direction, ++ unsigned long flags, void *context) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ enum dma_slave_buswidth dev_width; ++ struct bcm2835_desc *d; ++ dma_addr_t dev_addr; ++ struct scatterlist *sgent; ++ unsigned int es, sync_type; ++ unsigned int i, j, splitct, max_size; ++ ++ if (!is_slave_direction(direction)) { ++ dev_err(chan->device->dev, "%s: bad direction?\n", __func__); ++ return NULL; ++ } ++ ++ if (direction == DMA_DEV_TO_MEM) { ++ dev_addr = c->cfg.src_addr; ++ dev_width = c->cfg.src_addr_width; ++ sync_type = BCM2835_DMA_S_DREQ; ++ } else { ++ dev_addr = c->cfg.dst_addr; ++ dev_width = c->cfg.dst_addr_width; ++ sync_type = BCM2835_DMA_D_DREQ; ++ } ++ ++ /* Bus width translates to the element size (ES) */ ++ switch (dev_width) { ++ case DMA_SLAVE_BUSWIDTH_4_BYTES: ++ es = BCM2835_DMA_DATA_TYPE_S32; ++ break; ++ default: ++ return NULL; ++ } ++ ++ /* Now allocate and setup the descriptor. */ ++ d = kzalloc(sizeof(*d), GFP_NOWAIT); ++ if (!d) ++ return NULL; ++ ++ d->dir = direction; ++ ++ if (c->ch >= 8) /* we have a LITE channel */ ++ max_size = MAX_LITE_TRANSFER; ++ else ++ max_size = MAX_NORMAL_TRANSFER; ++ ++ /* We store the length of the SG list in d->frames ++ taking care to account for splitting up transfers ++ too large for a LITE channel */ ++ ++ d->frames = 0; ++ for_each_sg(sgl, sgent, sg_len, i) { ++ uint32_t len = sg_dma_len(sgent); ++ d->frames += 1 + len / max_size; ++ } ++ ++ /* Allocate memory for control blocks */ ++ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb); ++ d->control_block_base = dma_zalloc_coherent(chan->device->dev, ++ d->control_block_size, &d->control_block_base_phys, ++ GFP_NOWAIT); ++ ++ if (!d->control_block_base) { ++ kfree(d); ++ return NULL; ++ } ++ ++ /* ++ * Iterate over all SG entries, create a control block ++ * for each frame and link them together. ++ */ ++ ++ /* we count the number of times an SG entry had to be splitct ++ as a result of using a LITE channel */ ++ splitct = 0; ++ ++ for_each_sg(sgl, sgent, sg_len, i) { ++ dma_addr_t addr = sg_dma_address(sgent); ++ uint32_t len = sg_dma_len(sgent); ++ ++ for (j = 0; j < len; j += max_size) { ++ struct bcm2835_dma_cb *control_block = ++ &d->control_block_base[i+splitct]; ++ ++ /* Setup adresses */ ++ if (d->dir == DMA_DEV_TO_MEM) { ++ control_block->info = BCM2835_DMA_D_INC | ++ BCM2835_DMA_D_WIDTH | BCM2835_DMA_S_DREQ; ++ control_block->src = dev_addr; ++ control_block->dst = addr + (dma_addr_t)j; ++ } else { ++ control_block->info = BCM2835_DMA_S_INC | ++ BCM2835_DMA_S_WIDTH | BCM2835_DMA_D_DREQ; ++ control_block->src = addr + (dma_addr_t)j; ++ control_block->dst = dev_addr; ++ } ++ ++ /* Common part */ ++ control_block->info |= BCM2835_DMA_WAITS(SDHCI_BCM_DMA_WAITS); ++ control_block->info |= BCM2835_DMA_WAIT_RESP; ++ ++ /* Enable */ ++ if (i == sg_len-1 && len-j <= max_size) ++ control_block->info |= BCM2835_DMA_INT_EN; ++ ++ /* Setup synchronization */ ++ if (sync_type != 0) ++ control_block->info |= sync_type; ++ ++ /* Setup DREQ channel */ ++ c->dreq = c->cfg.slave_id; /* DREQ loaded from config */ ++ ++ if (c->dreq != 0) ++ control_block->info |= ++ BCM2835_DMA_PER_MAP(c->dreq); ++ ++ /* Length of a frame */ ++ control_block->length = min(len-j, max_size); ++ d->size += control_block->length; ++ ++ /* ++ * Next block is the next frame. ++ */ ++ if (i < sg_len-1 || len-j > max_size) { ++ /* next block is the next frame. */ ++ control_block->next = d->control_block_base_phys + ++ sizeof(struct bcm2835_dma_cb) * (i + splitct + 1); ++ } else { ++ /* next block is empty. */ ++ control_block->next = 0; ++ } ++ ++ if (len-j > max_size) ++ splitct++; ++ } ++ } ++ ++ c->cyclic = false; ++ ++ return vchan_tx_prep(&c->vc, &d->vd, flags); ++} ++ ++static int bcm2835_dma_slave_config(struct bcm2835_chan *c, + struct dma_slave_config *cfg) +{ + if ((cfg->direction == DMA_DEV_TO_MEM && @@ -108749,9 +106067,9 @@ index 0000000..b244293 + return 0; +} + -+static int bcm2708_dma_terminate_all(struct bcm2708_chan *c) ++static int bcm2835_dma_terminate_all(struct bcm2835_chan *c) +{ -+ struct bcm2708_dmadev *d = to_bcm2708_dma_dev(c->vc.chan.device); ++ struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device); + unsigned long flags; + int timeout = 10000; + LIST_HEAD(head); @@ -108770,19 +106088,18 @@ index 0000000..b244293 + */ + if (c->desc) { + c->desc = NULL; -+ bcm_dma_abort(c->chan_base); ++ bcm2835_dma_abort(c->chan_base); + + /* Wait for stopping */ -+ while (timeout > 0) { -+ timeout--; -+ if (!(readl(c->chan_base + BCM2708_DMA_CS) & -+ BCM2708_DMA_ACTIVE)) ++ while (--timeout) { ++ if (!(readl(c->chan_base + BCM2835_DMA_CS) & ++ BCM2835_DMA_ACTIVE)) + break; + + cpu_relax(); + } + -+ if (timeout <= 0) ++ if (!timeout) + dev_err(d->ddev.dev, "DMA transfer could not be terminated\n"); + } + @@ -108793,34 +106110,57 @@ index 0000000..b244293 + return 0; +} + -+static int bcm2708_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, ++static int bcm2835_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, + unsigned long arg) +{ -+ struct bcm2708_chan *c = to_bcm2708_dma_chan(chan); ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); + + switch (cmd) { + case DMA_SLAVE_CONFIG: -+ return bcm2708_dma_slave_config(c, ++ return bcm2835_dma_slave_config(c, + (struct dma_slave_config *)arg); + + case DMA_TERMINATE_ALL: -+ return bcm2708_dma_terminate_all(c); ++ return bcm2835_dma_terminate_all(c); + + default: + return -ENXIO; + } +} + -+static int bcm2708_dma_chan_init(struct bcm2708_dmadev *d, void __iomem* chan_base, -+ int chan_id, int irq) ++#ifdef CONFIG_OF ++static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq) +{ -+ struct bcm2708_chan *c; ++ struct bcm2835_chan *c; + + c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL); + if (!c) + return -ENOMEM; + -+ c->vc.desc_free = bcm2708_dma_desc_free; ++ c->vc.desc_free = bcm2835_dma_desc_free; ++ vchan_init(&c->vc, &d->ddev); ++ INIT_LIST_HEAD(&c->node); ++ ++ d->ddev.chancnt++; ++ ++ c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id); ++ c->ch = chan_id; ++ c->irq_number = irq; ++ ++ return 0; ++} ++#endif ++ ++static int bcm2708_dma_chan_init(struct bcm2835_dmadev *d, ++ void __iomem *chan_base, int chan_id, int irq) ++{ ++ struct bcm2835_chan *c; ++ ++ c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL); ++ if (!c) ++ return -ENOMEM; ++ ++ c->vc.desc_free = bcm2835_dma_desc_free; + vchan_init(&c->vc, &d->ddev); + INIT_LIST_HEAD(&c->node); + @@ -108833,30 +106173,81 @@ index 0000000..b244293 + return 0; +} + -+static void bcm2708_dma_free(struct bcm2708_dmadev *od) -+{ -+ while (!list_empty(&od->ddev.channels)) { -+ struct bcm2708_chan *c = list_first_entry(&od->ddev.channels, -+ struct bcm2708_chan, vc.chan.device_node); + ++static void bcm2835_dma_free(struct bcm2835_dmadev *od) ++{ ++ struct bcm2835_chan *c, *next; ++ ++ list_for_each_entry_safe(c, next, &od->ddev.channels, ++ vc.chan.device_node) { + list_del(&c->vc.chan.device_node); + tasklet_kill(&c->vc.task); + } +} + -+static int bcm2708_dma_probe(struct platform_device *pdev) ++static const struct of_device_id bcm2835_dma_of_match[] = { ++ { .compatible = "brcm,bcm2835-dma", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match); ++ ++#ifdef CONFIG_OF ++static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec, ++ struct of_dma *ofdma) +{ -+ struct bcm2708_dmadev *od; -+ int rc, i; ++ struct bcm2835_dmadev *d = ofdma->of_dma_data; ++ struct dma_chan *chan; ++ ++ chan = dma_get_any_slave_channel(&d->ddev); ++ if (!chan) ++ return NULL; ++ ++ /* Set DREQ from param */ ++ to_bcm2835_dma_chan(chan)->dreq = spec->args[0]; ++ ++ return chan; ++} ++#endif ++ ++static int bcm2835_dma_device_slave_caps(struct dma_chan *dchan, ++ struct dma_slave_caps *caps) ++{ ++ caps->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); ++ caps->dstn_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); ++ caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); ++ caps->cmd_pause = false; ++ caps->cmd_terminate = true; ++ ++ return 0; ++} ++ ++static int bcm2835_dma_probe(struct platform_device *pdev) ++{ ++ struct bcm2835_dmadev *od; ++#ifdef CONFIG_OF ++ struct resource *res; ++ void __iomem *base; ++ uint32_t chans_available; ++#endif ++ int rc; ++ int i; ++ int irq; ++ + + if (!pdev->dev.dma_mask) + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; + ++ /* If CONFIG_OF is selected, device tree is used */ ++ /* hence the difference between probing */ ++ ++#ifndef CONFIG_OF ++ + rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); + if (rc) + return rc; + dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); + ++ + od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); + if (!od) + return -ENOMEM; @@ -108864,25 +106255,29 @@ index 0000000..b244293 + pdev->dev.dma_parms = &od->dma_parms; + dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF); + ++ + dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); ++ dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask); + dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); -+ od->ddev.device_alloc_chan_resources = bcm2708_dma_alloc_chan_resources; -+ od->ddev.device_free_chan_resources = bcm2708_dma_free_chan_resources; -+ od->ddev.device_tx_status = bcm2708_dma_tx_status; -+ od->ddev.device_issue_pending = bcm2708_dma_issue_pending; -+ od->ddev.device_prep_dma_cyclic = bcm2708_dma_prep_dma_cyclic; -+ od->ddev.device_control = bcm2708_dma_control; ++ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources; ++ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources; ++ od->ddev.device_tx_status = bcm2835_dma_tx_status; ++ od->ddev.device_issue_pending = bcm2835_dma_issue_pending; ++ od->ddev.device_slave_caps = bcm2835_dma_device_slave_caps; ++ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic; ++ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg; ++ od->ddev.device_control = bcm2835_dma_control; + od->ddev.dev = &pdev->dev; + INIT_LIST_HEAD(&od->ddev.channels); + spin_lock_init(&od->lock); + + platform_set_drvdata(pdev, od); + -+ for (i = 0; i < 16; i++) { -+ void __iomem* chan_base; -+ int chan_id, irq; ++ for (i = 0; i < 5; i++) { ++ void __iomem *chan_base; ++ int chan_id; + -+ chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST, ++ chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_LITE, + &chan_base, + &irq); + @@ -108890,38 +106285,121 @@ index 0000000..b244293 + break; + + rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq); -+ if (rc) { -+ bcm2708_dma_free(od); -+ return rc; ++ if (rc) ++ goto err_no_dma; ++ } ++#else ++ rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); ++ if (rc) ++ return rc; ++ ++ ++ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); ++ if (!od) ++ return -ENOMEM; ++ ++ pdev->dev.dma_parms = &od->dma_parms; ++ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF); ++ ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ od->base = base; ++ ++ ++ dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); ++ dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask); ++ dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); ++ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources; ++ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources; ++ od->ddev.device_tx_status = bcm2835_dma_tx_status; ++ od->ddev.device_issue_pending = bcm2835_dma_issue_pending; ++ od->ddev.device_slave_caps = bcm2835_dma_device_slave_caps; ++ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic; ++ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg; ++ od->ddev.device_control = bcm2835_dma_control; ++ od->ddev.dev = &pdev->dev; ++ INIT_LIST_HEAD(&od->ddev.channels); ++ spin_lock_init(&od->lock); ++ ++ platform_set_drvdata(pdev, od); ++ ++ ++ /* Request DMA channel mask from device tree */ ++ if (of_property_read_u32(pdev->dev.of_node, ++ "brcm,dma-channel-mask", ++ &chans_available)) { ++ dev_err(&pdev->dev, "Failed to get channel mask\n"); ++ rc = -EINVAL; ++ goto err_no_dma; ++ } ++ ++ ++ /* ++ * Do not use the FIQ and BULK channels, ++ * because they are used by the GPU. ++ */ ++ chans_available &= ~(BCM2835_DMA_FIQ_MASK | BCM2835_DMA_BULK_MASK); ++ ++ ++ for (i = 0; i < pdev->num_resources; i++) { ++ irq = platform_get_irq(pdev, i); ++ if (irq < 0) ++ break; ++ ++ if (chans_available & (1 << i)) { ++ rc = bcm2835_dma_chan_init(od, i, irq); ++ if (rc) ++ goto err_no_dma; + } + } + ++ dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i); ++ ++ /* Device-tree DMA controller registration */ ++ rc = of_dma_controller_register(pdev->dev.of_node, ++ bcm2835_dma_xlate, od); ++ if (rc) { ++ dev_err(&pdev->dev, "Failed to register DMA controller\n"); ++ goto err_no_dma; ++ } ++#endif ++ + rc = dma_async_device_register(&od->ddev); + if (rc) { + dev_err(&pdev->dev, + "Failed to register slave DMA engine device: %d\n", rc); -+ bcm2708_dma_free(od); -+ return rc; ++ goto err_no_dma; + } + -+ dev_dbg(&pdev->dev, "Load BCM2708 DMA engine driver\n"); ++ dev_info(&pdev->dev, "Load BCM2835 DMA engine driver\n"); + ++ return 0; ++ ++err_no_dma: ++ bcm2835_dma_free(od); + return rc; +} + -+static int bcm2708_dma_remove(struct platform_device *pdev) ++static int bcm2835_dma_remove(struct platform_device *pdev) +{ -+ struct bcm2708_dmadev *od = platform_get_drvdata(pdev); ++ struct bcm2835_dmadev *od = platform_get_drvdata(pdev); + + dma_async_device_unregister(&od->ddev); -+ bcm2708_dma_free(od); ++ bcm2835_dma_free(od); + + return 0; +} + -+static struct platform_driver bcm2708_dma_driver = { -+ .probe = bcm2708_dma_probe, -+ .remove = bcm2708_dma_remove, ++#ifndef CONFIG_OF ++ ++ ++static struct platform_driver bcm2835_dma_driver = { ++ .probe = bcm2835_dma_probe, ++ .remove = bcm2835_dma_remove, + .driver = { + .name = "bcm2708-dmaengine", + .owner = THIS_MODULE, @@ -108930,43 +106408,60 @@ index 0000000..b244293 + +static struct platform_device *pdev; + -+static const struct platform_device_info bcm2708_dma_dev_info = { ++static const struct platform_device_info bcm2835_dma_dev_info = { + .name = "bcm2708-dmaengine", + .id = -1, +}; + -+static int bcm2708_dma_init(void) ++static int bcm2835_dma_init(void) +{ -+ int rc = platform_driver_register(&bcm2708_dma_driver); ++ int rc = platform_driver_register(&bcm2835_dma_driver); + + if (rc == 0) { -+ pdev = platform_device_register_full(&bcm2708_dma_dev_info); ++ pdev = platform_device_register_full(&bcm2835_dma_dev_info); + if (IS_ERR(pdev)) { -+ platform_driver_unregister(&bcm2708_dma_driver); ++ platform_driver_unregister(&bcm2835_dma_driver); + rc = PTR_ERR(pdev); + } + } + + return rc; +} -+subsys_initcall(bcm2708_dma_init); ++module_init(bcm2835_dma_init); /* preferable to subsys_initcall */ + -+static void __exit bcm2708_dma_exit(void) ++static void __exit bcm2835_dma_exit(void) +{ + platform_device_unregister(pdev); -+ platform_driver_unregister(&bcm2708_dma_driver); ++ platform_driver_unregister(&bcm2835_dma_driver); +} -+module_exit(bcm2708_dma_exit); ++module_exit(bcm2835_dma_exit); + -+MODULE_ALIAS("platform:bcm2708-dma"); -+MODULE_DESCRIPTION("BCM2708 DMA engine driver"); ++#else ++ ++static struct platform_driver bcm2835_dma_driver = { ++ .probe = bcm2835_dma_probe, ++ .remove = bcm2835_dma_remove, ++ .driver = { ++ .name = "bcm2835-dma", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(bcm2835_dma_of_match), ++ }, ++}; ++ ++module_platform_driver(bcm2835_dma_driver); ++ ++#endif ++ ++MODULE_ALIAS("platform:bcm2835-dma"); ++MODULE_DESCRIPTION("BCM2835 DMA engine driver"); +MODULE_AUTHOR("Florian Meier "); ++MODULE_AUTHOR("Gellert Weisz "); +MODULE_LICENSE("GPL v2"); -From 8e79544f1ff0c54df986325c4347f4c8d554370c Mon Sep 17 00:00:00 2001 +From d6c86289d22b49d6ff94876c4797e506189e358d Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 14:33:38 +0100 -Subject: [PATCH 31/94] ASoC: Add support for BCM2708 +Subject: [PATCH 30/82] ASoC: Add support for BCM2708 This driver adds support for digital audio (I2S) for the BCM2708 SoC that is used by the @@ -109961,55 +107456,10 @@ index 0000000..ebaf3d6 +MODULE_AUTHOR("Florian Meier "); +MODULE_LICENSE("GPL v2"); -From b66e706776ad1c098c03c7c0a08e1b49a909b001 Mon Sep 17 00:00:00 2001 -From: Florian Meier -Date: Fri, 22 Nov 2013 14:37:51 +0100 -Subject: [PATCH 32/94] BCM2708: Extend mach header - -Extend the headers of the mach-bcm2708 -in order to support I2S and DMA engine. - -Signed-off-by: Florian Meier ---- - arch/arm/mach-bcm2708/include/mach/dma.h | 2 ++ - arch/arm/mach-bcm2708/include/mach/platform.h | 2 ++ - 2 files changed, 4 insertions(+) - -diff --git a/arch/arm/mach-bcm2708/include/mach/dma.h b/arch/arm/mach-bcm2708/include/mach/dma.h -index 6d2f9a0..a4aac4c 100644 ---- a/arch/arm/mach-bcm2708/include/mach/dma.h -+++ b/arch/arm/mach-bcm2708/include/mach/dma.h -@@ -45,6 +45,8 @@ - #define BCM2708_DMA_ADDR 0x04 - /* the current control block appears in the following registers - read only */ - #define BCM2708_DMA_INFO 0x08 -+#define BCM2708_DMA_SOURCE_AD 0x0c -+#define BCM2708_DMA_DEST_AD 0x10 - #define BCM2708_DMA_NEXTCB 0x1C - #define BCM2708_DMA_DEBUG 0x20 - -diff --git a/arch/arm/mach-bcm2708/include/mach/platform.h b/arch/arm/mach-bcm2708/include/mach/platform.h -index 992a630..2e7e1bb 100644 ---- a/arch/arm/mach-bcm2708/include/mach/platform.h -+++ b/arch/arm/mach-bcm2708/include/mach/platform.h -@@ -62,10 +62,12 @@ - #define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */ - #define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */ - #define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */ -+#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */ - #define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */ - #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */ - #define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */ - #define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */ -+#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */ - #define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */ - #define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */ - #define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */ - -From f965994b1704ecbdf5988279fa2675416ec24689 Mon Sep 17 00:00:00 2001 +From 8ed750f6a8efc0038dabef1b4e75064d27e98495 Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 14:59:51 +0100 -Subject: [PATCH 33/94] ASoC: Add support for PCM5102A codec +Subject: [PATCH 31/82] ASoC: Add support for PCM5102A codec Some definitions to support the PCM5102A codec by Texas Instruments. @@ -110023,20 +107473,20 @@ Signed-off-by: Florian Meier create mode 100644 sound/soc/codecs/pcm5102a.c diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig -index 0b9571c..73804ca 100644 +index 8838838e..d9be496 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig -@@ -74,6 +74,7 @@ config SND_SOC_ALL_CODECS - select SND_SOC_PCM3008 +@@ -76,6 +76,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_PCM512x_I2C if I2C select SND_SOC_PCM512x_SPI if SPI_MASTER -+ select SND_SOC_PCM5102A + select SND_SOC_RT286 if I2C ++ select SND_SOC_PCM5102A if I2C select SND_SOC_RT5631 if I2C select SND_SOC_RT5640 if I2C select SND_SOC_RT5645 if I2C -@@ -449,6 +450,9 @@ config SND_SOC_RL6231 - default m if SND_SOC_RT5645=m - default m if SND_SOC_RT5651=m +@@ -465,6 +466,9 @@ config SND_SOC_RL6231 + config SND_SOC_RT286 + tristate +config SND_SOC_PCM5102A + tristate @@ -110045,21 +107495,21 @@ index 0b9571c..73804ca 100644 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile -index 1bd6e1c..f540cf3 100644 +index 20afe0f..c5f6390 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile -@@ -68,6 +68,7 @@ snd-soc-pcm512x-objs := pcm512x.o - snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o +@@ -70,6 +70,7 @@ snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o snd-soc-pcm512x-spi-objs := pcm512x-spi.o snd-soc-rl6231-objs := rl6231.o + snd-soc-rt286-objs := rt286.o +snd-soc-pcm5102a-objs := pcm5102a.o snd-soc-rt5631-objs := rt5631.o snd-soc-rt5640-objs := rt5640.o snd-soc-rt5645-objs := rt5645.o -@@ -235,6 +236,7 @@ obj-$(CONFIG_SND_SOC_PCM512x) += snd-soc-pcm512x.o - obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o +@@ -241,6 +242,7 @@ obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o + obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o +obj-$(CONFIG_SND_SOC_PCM5102A) += snd-soc-pcm5102a.o obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o @@ -110134,10 +107584,10 @@ index 0000000..126f1e9 +MODULE_AUTHOR("Florian Meier "); +MODULE_LICENSE("GPL v2"); -From 59d1e13538d2251dad81db291c769a47023efd24 Mon Sep 17 00:00:00 2001 +From ba6776792cfab454c1da7f2e0521993a2a74c76c Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 19:04:54 +0100 -Subject: [PATCH 34/94] BCM2708: Add I2S support to board file +Subject: [PATCH 32/82] BCM2708: Add I2S support to board file Adds the required initializations for I2S to the board file of mach-bcm2708. @@ -110148,10 +107598,10 @@ Signed-off-by: Florian Meier 1 file changed, 26 insertions(+) diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index a6eb08e..27e47d5 100644 +index a740344..dca28ad 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -615,6 +615,28 @@ static struct platform_device bcm2835_thermal_device = { +@@ -587,6 +587,28 @@ static struct platform_device bcm2835_thermal_device = { .name = "bcm2835_thermal", }; @@ -110180,7 +107630,7 @@ index a6eb08e..27e47d5 100644 int __init bcm_register_device(struct platform_device *pdev) { int ret; -@@ -738,6 +760,10 @@ void __init bcm2708_init(void) +@@ -707,6 +729,10 @@ void __init bcm2708_init(void) bcm_register_device(&bcm2835_hwmon_device); bcm_register_device(&bcm2835_thermal_device); @@ -110192,10 +107642,10 @@ index a6eb08e..27e47d5 100644 struct amba_device *d = amba_devs[i]; amba_device_register(d, &iomem_resource); -From f5ef93926fbc0047c70fd094a8e6a7115f76959f Mon Sep 17 00:00:00 2001 +From 3356823e1106386979002a7b3aba4f07bf03d4cf Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 19:19:08 +0100 -Subject: [PATCH 35/94] ASoC: Add support for HifiBerry DAC +Subject: [PATCH 33/82] ASoC: Add support for HifiBerry DAC This adds a machine driver for the HifiBerry DAC. It is a sound card that can @@ -110344,10 +107794,10 @@ index 0000000..4b70b45 +MODULE_DESCRIPTION("ASoC Driver for HifiBerry DAC"); +MODULE_LICENSE("GPL v2"); -From 65d21fa1077ab0de2fff08711085a573b249b70a Mon Sep 17 00:00:00 2001 +From 8513da82d5ec4283e05f25d4a481f840179ffccc Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 22 Nov 2013 19:21:34 +0100 -Subject: [PATCH 36/94] BCM2708: Add HifiBerry DAC to board file +Subject: [PATCH 34/82] BCM2708: Add HifiBerry DAC to board file This adds the initalization of the HifiBerry DAC to the mach-bcm2708 board file. @@ -110358,10 +107808,10 @@ Signed-off-by: Florian Meier 1 file changed, 19 insertions(+) diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 27e47d5..fafd8d0 100644 +index dca28ad..50d4991 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -637,6 +637,20 @@ static struct platform_device bcm2708_i2s_device = { +@@ -609,6 +609,20 @@ static struct platform_device bcm2708_i2s_device = { }; #endif @@ -110382,7 +107832,7 @@ index 27e47d5..fafd8d0 100644 int __init bcm_register_device(struct platform_device *pdev) { int ret; -@@ -764,6 +778,11 @@ void __init bcm2708_init(void) +@@ -733,6 +747,11 @@ void __init bcm2708_init(void) bcm_register_device(&bcm2708_i2s_device); #endif @@ -110395,10 +107845,10 @@ index 27e47d5..fafd8d0 100644 struct amba_device *d = amba_devs[i]; amba_device_register(d, &iomem_resource); -From bdfd5b66ade61b7d8add0a972efb58b0db431b56 Mon Sep 17 00:00:00 2001 +From 7b6218d551bf4b7e84e9b73eaed83bc3bb136080 Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 6 Dec 2013 18:55:53 +0100 -Subject: [PATCH 37/94] ASoC: BCM2708: Add 24 bit support +Subject: [PATCH 35/82] ASoC: BCM2708: Add 24 bit support This adds 24 bit support to the I2S driver of the BCM2708. Besides enabling the 24 bit flags, it includes two bug fixes: @@ -110470,59 +107920,87 @@ index ebaf3d6..a179216 100644 .period_bytes_min = 32, .period_bytes_max = 64 * PAGE_SIZE, -From d5c67474b3103119085c63a6baf25ed2eb550a58 Mon Sep 17 00:00:00 2001 +From 0122f7477ee81be5ca768904bb6c23570f956504 Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Sat, 13 Sep 2014 10:52:04 +0100 +Subject: [PATCH 36/82] bcm2708-i2s: Update bclk_ratio to more correct values + +--- + sound/soc/bcm/bcm2708-i2s.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/sound/soc/bcm/bcm2708-i2s.c b/sound/soc/bcm/bcm2708-i2s.c +index a179216..fd50e2d 100644 +--- a/sound/soc/bcm/bcm2708-i2s.c ++++ b/sound/soc/bcm/bcm2708-i2s.c +@@ -344,15 +344,15 @@ static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream, + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + data_length = 16; +- bclk_ratio = 40; ++ bclk_ratio = 50; + break; + case SNDRV_PCM_FORMAT_S24_LE: + data_length = 24; +- bclk_ratio = 40; ++ bclk_ratio = 50; + break; + case SNDRV_PCM_FORMAT_S32_LE: + data_length = 32; +- bclk_ratio = 80; ++ bclk_ratio = 100; + break; + default: + return -EINVAL; + +From 58cff69a0e46077a6ac3cfa0dba80f4ec8d9a685 Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Mon, 2 Dec 2013 20:28:22 +0100 -Subject: [PATCH 38/94] BCM2708: Add I2S and DMA support to default config +Subject: [PATCH 37/82] BCM2708: Add I2S and DMA support to default config This commit adds several modules that are needed for I2S support for the Raspberry Pi to the defconfig. Signed-off-by: Florian Meier --- - arch/arm/configs/bcmrpi_defconfig | 11 +++++++++++ - 1 file changed, 11 insertions(+) + arch/arm/configs/bcmrpi_defconfig | 6 ++++++ + 1 file changed, 6 insertions(+) diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 0c58172..38ccd22 100644 +index d77317c..4fb22fc 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -741,6 +741,13 @@ CONFIG_SND_USB_UA101=m +@@ -731,6 +731,10 @@ CONFIG_SND_USB_UA101=m CONFIG_SND_USB_CAIAQ=m CONFIG_SND_USB_CAIAQ_INPUT=y CONFIG_SND_USB_6FIRE=m +CONFIG_SND_SOC=m -+CONFIG_SND_SOC_DMAENGINE_PCM=y -+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +CONFIG_SND_BCM2708_SOC_I2S=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m -+CONFIG_SND_SOC_I2C_AND_SPI=m -+CONFIG_SND_SOC_PCM5102A=m ++CONFIG_SND_SIMPLE_CARD=m CONFIG_SOUND_PRIME=m CONFIG_HIDRAW=y CONFIG_HID_A4TECH=m -@@ -931,6 +938,10 @@ CONFIG_RTC_DRV_RS5C348=m +@@ -925,6 +929,8 @@ CONFIG_RTC_DRV_RS5C348=m CONFIG_RTC_DRV_DS3234=m CONFIG_RTC_DRV_PCF2123=m CONFIG_RTC_DRV_RX4581=m +CONFIG_DMADEVICES=y -+CONFIG_DMA_BCM2708=m -+CONFIG_DMA_ENGINE=y -+CONFIG_DMA_VIRTUAL_CHANNELS=m ++CONFIG_DMA_BCM2708=y CONFIG_UIO=m CONFIG_UIO_PDRV_GENIRQ=m CONFIG_STAGING=y -From 384db42ed68bc4fceccee99c9461f14709c28828 Mon Sep 17 00:00:00 2001 +From 01322b6bd87f4dfad730f8ae59c380f9539d2666 Mon Sep 17 00:00:00 2001 From: Florian Meier Date: Fri, 6 Dec 2013 20:50:28 +0100 -Subject: [PATCH 39/94] ASoC: BCM2708: Add support for RPi-DAC +Subject: [PATCH 38/82] ASoC: BCM2708: Add support for RPi-DAC This adds a machine driver for the RPi-DAC. Signed-off-by: Florian Meier --- - arch/arm/configs/bcmrpi_defconfig | 2 + + arch/arm/configs/bcmrpi_defconfig | 1 + arch/arm/mach-bcm2708/bcm2708.c | 19 ++++++++ sound/soc/bcm/Kconfig | 7 +++ sound/soc/bcm/Makefile | 2 + @@ -110530,30 +108008,27 @@ Signed-off-by: Florian Meier sound/soc/codecs/Kconfig | 4 ++ sound/soc/codecs/Makefile | 2 + sound/soc/codecs/pcm1794a.c | 62 +++++++++++++++++++++++++ - 8 files changed, 195 insertions(+) + 8 files changed, 194 insertions(+) create mode 100644 sound/soc/bcm/rpi-dac.c create mode 100644 sound/soc/codecs/pcm1794a.c diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 38ccd22..5e049f9 100644 +index 4fb22fc..5f402ac 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -746,8 +746,10 @@ CONFIG_SND_SOC_DMAENGINE_PCM=y - CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +@@ -734,6 +734,7 @@ CONFIG_SND_USB_6FIRE=m + CONFIG_SND_SOC=m CONFIG_SND_BCM2708_SOC_I2S=m CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m +CONFIG_SND_BCM2708_SOC_RPI_DAC=m - CONFIG_SND_SOC_I2C_AND_SPI=m - CONFIG_SND_SOC_PCM5102A=m -+CONFIG_SND_SOC_PCM1794A=m + CONFIG_SND_SIMPLE_CARD=m CONFIG_SOUND_PRIME=m CONFIG_HIDRAW=y - CONFIG_HID_A4TECH=m diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index fafd8d0..238f165 100644 +index 50d4991..100c223 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -651,6 +651,20 @@ static struct platform_device snd_pcm5102a_codec_device = { +@@ -623,6 +623,20 @@ static struct platform_device snd_pcm5102a_codec_device = { }; #endif @@ -110574,7 +108049,7 @@ index fafd8d0..238f165 100644 int __init bcm_register_device(struct platform_device *pdev) { int ret; -@@ -783,6 +797,11 @@ void __init bcm2708_init(void) +@@ -752,6 +766,11 @@ void __init bcm2708_init(void) bcm_register_device(&snd_pcm5102a_codec_device); #endif @@ -110615,7 +108090,7 @@ index be90a49cb..ccc9809 100644 +obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o diff --git a/sound/soc/bcm/rpi-dac.c b/sound/soc/bcm/rpi-dac.c new file mode 100644 -index 0000000..ef3cd93 +index 0000000..6d6e0ba --- /dev/null +++ b/sound/soc/bcm/rpi-dac.c @@ -0,0 +1,97 @@ @@ -110665,8 +108140,8 @@ index 0000000..ef3cd93 + +static struct snd_soc_dai_link snd_rpi_rpi_dac_dai[] = { +{ -+ .name = "HifiBerry Mini", -+ .stream_name = "HifiBerry Mini HiFi", ++ .name = "RPi-DAC", ++ .stream_name = "RPi-DAC HiFi", + .cpu_dai_name = "bcm2708-i2s.0", + .codec_dai_name = "pcm1794a-hifi", + .platform_name = "bcm2708-i2s.0", @@ -110717,20 +108192,20 @@ index 0000000..ef3cd93 +MODULE_DESCRIPTION("ASoC Driver for RPi-DAC"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig -index 73804ca..0309507 100644 +index d9be496..f252baa 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig -@@ -74,6 +74,7 @@ config SND_SOC_ALL_CODECS - select SND_SOC_PCM3008 - select SND_SOC_PCM512x_I2C if I2C +@@ -77,6 +77,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_PCM512x_SPI if SPI_MASTER -+ select SND_SOC_PCM1794A - select SND_SOC_PCM5102A + select SND_SOC_RT286 if I2C + select SND_SOC_PCM5102A if I2C ++ select SND_SOC_PCM1794A if I2C select SND_SOC_RT5631 if I2C select SND_SOC_RT5640 if I2C -@@ -450,6 +451,9 @@ config SND_SOC_RL6231 - default m if SND_SOC_RT5645=m - default m if SND_SOC_RT5651=m + select SND_SOC_RT5645 if I2C +@@ -466,6 +467,9 @@ config SND_SOC_RL6231 + config SND_SOC_RT286 + tristate +config SND_SOC_PCM1794A + tristate @@ -110739,21 +108214,21 @@ index 73804ca..0309507 100644 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile -index f540cf3..64a04fb 100644 +index c5f6390..b4a8a98 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile -@@ -68,6 +68,7 @@ snd-soc-pcm512x-objs := pcm512x.o - snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o +@@ -70,6 +70,7 @@ snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o snd-soc-pcm512x-spi-objs := pcm512x-spi.o snd-soc-rl6231-objs := rl6231.o + snd-soc-rt286-objs := rt286.o +snd-soc-pcm1794a-objs := pcm1794a.o snd-soc-pcm5102a-objs := pcm5102a.o snd-soc-rt5631-objs := rt5631.o snd-soc-rt5640-objs := rt5640.o -@@ -236,6 +237,7 @@ obj-$(CONFIG_SND_SOC_PCM512x) += snd-soc-pcm512x.o - obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o +@@ -242,6 +243,7 @@ obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o + obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o +obj-$(CONFIG_SND_SOC_PCM1794A) += snd-soc-pcm1794a.o obj-$(CONFIG_SND_SOC_PCM5102A) += snd-soc-pcm5102a.o obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o @@ -110827,10 +108302,10 @@ index 0000000..b4eaa44 +MODULE_AUTHOR("Florian Meier "); +MODULE_LICENSE("GPL v2"); -From 02323e41c0527ef3763cb29dfda6ef0f41c1d80f Mon Sep 17 00:00:00 2001 +From 7a1d5a33253ab9b4eabed87df78c2fcd116b38c9 Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Wed, 15 Jan 2014 21:41:23 +0100 -Subject: [PATCH 40/94] ASoC: wm8804: Implement MCLK configuration options, add +Subject: [PATCH 39/82] ASoC: wm8804: Implement MCLK configuration options, add 32bit support WM8804 can run with PLL frequencies of 256xfs and 128xfs for most sample rates. At 192kHz only 128xfs is supported. The existing driver selects 128xfs automatically for some lower samples rates. By using an @@ -110849,14 +108324,14 @@ Signed-off-by: Daniel Matuschek 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sound/soc/codecs/wm8804.c b/sound/soc/codecs/wm8804.c -index d96e5963..9a7a289 100644 +index 0ea01df..4724553 100644 --- a/sound/soc/codecs/wm8804.c +++ b/sound/soc/codecs/wm8804.c @@ -278,6 +278,7 @@ static int wm8804_hw_params(struct snd_pcm_substream *substream, blen = 0x1; break; - case SNDRV_PCM_FORMAT_S24_LE: -+ case SNDRV_PCM_FORMAT_S32_LE: + case 24: ++ case 32: blen = 0x2; break; default: @@ -110870,10 +108345,10 @@ index d96e5963..9a7a289 100644 #define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \ -From 93383b9b50befba8e959c7f9dfec1e9252ee42ba Mon Sep 17 00:00:00 2001 +From 544fbd99d8a1351a98f7264d62daf1020f0a1ad0 Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Wed, 15 Jan 2014 21:42:08 +0100 -Subject: [PATCH 41/94] ASoC: BCM:Add support for HiFiBerry Digi. Driver is +Subject: [PATCH 40/82] ASoC: BCM:Add support for HiFiBerry Digi. Driver is based on the patched WM8804 driver. Signed-off-by: Daniel Matuschek @@ -111076,10 +108551,10 @@ index 0000000..e4f769d +MODULE_DESCRIPTION("ASoC Driver for HifiBerry Digi"); +MODULE_LICENSE("GPL v2"); -From 0e6318ea66a835f331e8f194519f6d03a6ae4dd5 Mon Sep 17 00:00:00 2001 +From 0010956551eab2ce3f82ba83c5d67172460ce3f6 Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Thu, 16 Jan 2014 07:26:08 +0100 -Subject: [PATCH 42/94] BCM2708: Added support for HiFiBerry Digi board Board +Subject: [PATCH 41/82] BCM2708: Added support for HiFiBerry Digi board Board initalization by I2C Signed-off-by: Daniel Matuschek @@ -111088,10 +108563,10 @@ Signed-off-by: Daniel Matuschek 1 file changed, 20 insertions(+) diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 238f165..139045b 100644 +index 100c223..a57cb85 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -651,6 +651,21 @@ static struct platform_device snd_pcm5102a_codec_device = { +@@ -623,6 +623,21 @@ static struct platform_device snd_pcm5102a_codec_device = { }; #endif @@ -111113,7 +108588,7 @@ index 238f165..139045b 100644 #if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) static struct platform_device snd_rpi_dac_device = { .name = "snd-rpi-dac", -@@ -797,6 +812,11 @@ void __init bcm2708_init(void) +@@ -766,6 +781,11 @@ void __init bcm2708_init(void) bcm_register_device(&snd_pcm5102a_codec_device); #endif @@ -111126,38 +108601,35 @@ index 238f165..139045b 100644 bcm_register_device(&snd_rpi_dac_device); bcm_register_device(&snd_pcm1794a_codec_device); -From 943a8e128f3a685b1ffb7abd67ddc4c262002897 Mon Sep 17 00:00:00 2001 +From a2d24d68441d60519bfce05150edbdf70db96160 Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Thu, 16 Jan 2014 07:27:28 +0100 -Subject: [PATCH 43/94] BCM2708: Added HiFiBerry Digi configuration option It +Subject: [PATCH 42/82] BCM2708: Added HiFiBerry Digi configuration option It will be compiled as a module by default. This also includes the WM8804 driver. Signed-off-by: Daniel Matuschek --- - arch/arm/configs/bcmrpi_defconfig | 2 ++ - 1 file changed, 2 insertions(+) + arch/arm/configs/bcmrpi_defconfig | 1 + + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 5e049f9..4f6bb90 100644 +index 5f402ac..070ee49 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -744,8 +744,10 @@ CONFIG_SND_USB_6FIRE=m +@@ -734,6 +734,7 @@ CONFIG_SND_USB_6FIRE=m CONFIG_SND_SOC=m - CONFIG_SND_SOC_DMAENGINE_PCM=y - CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y -+CONFIG_SND_SOC_WM8804=m CONFIG_SND_BCM2708_SOC_I2S=m CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m CONFIG_SND_BCM2708_SOC_RPI_DAC=m - CONFIG_SND_SOC_I2C_AND_SPI=m - CONFIG_SND_SOC_PCM5102A=m + CONFIG_SND_SIMPLE_CARD=m + CONFIG_SOUND_PRIME=m -From 601a38140c26626d4f2917bea04fc6b8e096884d Mon Sep 17 00:00:00 2001 +From 0bfe07a263797f9a04fcf728d2d7d9c2c03b486e Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Thu, 16 Jan 2014 07:36:35 +0100 -Subject: [PATCH 44/94] ASoC: wm8804: Set idle_bias_off to false Idle bias has +Subject: [PATCH 43/82] ASoC: wm8804: Set idle_bias_off to false Idle bias has been change to remove warning on driver startup Signed-off-by: Daniel Matuschek @@ -111166,7 +108638,7 @@ Signed-off-by: Daniel Matuschek 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/codecs/wm8804.c b/sound/soc/codecs/wm8804.c -index 9a7a289..32e199a 100644 +index 4724553..5d4140e 100644 --- a/sound/soc/codecs/wm8804.c +++ b/sound/soc/codecs/wm8804.c @@ -675,7 +675,7 @@ static struct snd_soc_codec_driver soc_codec_dev_wm8804 = { @@ -111179,48 +108651,10 @@ index 9a7a289..32e199a 100644 .controls = wm8804_snd_controls, .num_controls = ARRAY_SIZE(wm8804_snd_controls), -From 5b9e91c82dfebd32160d62ec77ef802bf3fe3e39 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Wed, 12 Mar 2014 11:46:34 +0000 -Subject: [PATCH 45/94] ASoc: Don't report S24_LE support, it produces white - noise with xbmc - ---- - sound/soc/bcm/bcm2708-i2s.c | 2 +- - sound/soc/codecs/pcm5102a.c | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/sound/soc/bcm/bcm2708-i2s.c b/sound/soc/bcm/bcm2708-i2s.c -index a179216..b25e158 100644 ---- a/sound/soc/bcm/bcm2708-i2s.c -+++ b/sound/soc/bcm/bcm2708-i2s.c -@@ -718,7 +718,7 @@ static struct snd_soc_dai_driver bcm2708_i2s_dai = { - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE -- | SNDRV_PCM_FMTBIT_S24_LE -+ // | SNDRV_PCM_FMTBIT_S24_LE : disable for now, it causes white noise with xbmc - | SNDRV_PCM_FMTBIT_S32_LE - }, - .capture = { -diff --git a/sound/soc/codecs/pcm5102a.c b/sound/soc/codecs/pcm5102a.c -index 126f1e9..7812d34 100644 ---- a/sound/soc/codecs/pcm5102a.c -+++ b/sound/soc/codecs/pcm5102a.c -@@ -28,7 +28,7 @@ static struct snd_soc_dai_driver pcm5102a_dai = { - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | -- SNDRV_PCM_FMTBIT_S24_LE | -+ // SNDRV_PCM_FMTBIT_S24_LE | : disable for now, it causes white noise with xbmc - SNDRV_PCM_FMTBIT_S32_LE - }, - }; - -From 6cfb5d9808b9b905c3e33e406b6599a7358ec3ff Mon Sep 17 00:00:00 2001 +From ac1dd319acaae07171260b1b1e741000ce6cf8d9 Mon Sep 17 00:00:00 2001 From: Gordon Garrity Date: Sat, 8 Mar 2014 16:56:57 +0000 -Subject: [PATCH 46/94] Add IQaudIO Sound Card support for Raspberry Pi +Subject: [PATCH 44/82] Add IQaudIO Sound Card support for Raspberry Pi --- arch/arm/configs/bcmrpi_defconfig | 1 + @@ -111232,22 +108666,22 @@ Subject: [PATCH 46/94] Add IQaudIO Sound Card support for Raspberry Pi create mode 100644 sound/soc/bcm/iqaudio-dac.c diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 4f6bb90..105bcbe 100644 +index 070ee49..db259ae 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -752,6 +752,7 @@ CONFIG_SND_BCM2708_SOC_RPI_DAC=m - CONFIG_SND_SOC_I2C_AND_SPI=m - CONFIG_SND_SOC_PCM5102A=m - CONFIG_SND_SOC_PCM1794A=m +@@ -736,6 +736,7 @@ CONFIG_SND_BCM2708_SOC_I2S=m + CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m + CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m + CONFIG_SND_BCM2708_SOC_RPI_DAC=m +CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m + CONFIG_SND_SIMPLE_CARD=m CONFIG_SOUND_PRIME=m CONFIG_HIDRAW=y - CONFIG_HID_A4TECH=m diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 139045b..f717a59 100644 +index a57cb85..633be19 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -680,6 +680,22 @@ static struct platform_device snd_pcm1794a_codec_device = { +@@ -652,6 +652,22 @@ static struct platform_device snd_pcm1794a_codec_device = { }; #endif @@ -111270,7 +108704,7 @@ index 139045b..f717a59 100644 int __init bcm_register_device(struct platform_device *pdev) { int ret; -@@ -822,6 +838,12 @@ void __init bcm2708_init(void) +@@ -791,6 +807,12 @@ void __init bcm2708_init(void) bcm_register_device(&snd_pcm1794a_codec_device); #endif @@ -111430,10 +108864,10 @@ index 0000000..8d0e2ae +MODULE_DESCRIPTION("ASoC Driver for IQAudio DAC"); +MODULE_LICENSE("GPL v2"); -From 5e1cad035f3e1576fdd35adca79ddff557173f9c Mon Sep 17 00:00:00 2001 +From dbda0b55f5024ce83050bfbbd872fb7d77925f64 Mon Sep 17 00:00:00 2001 From: Howard Mitchell Date: Wed, 30 Jul 2014 21:43:37 +0100 -Subject: [PATCH 47/94] soc-core: Fix volsw_range funcs so +Subject: [PATCH 45/82] soc-core: Fix volsw_range funcs so SOC_DOUBLE_R_RANGE_TLV works. This is so that the correct range of values as specified @@ -111444,10 +108878,10 @@ hardware for both the normal and invert cases. 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c -index b87d7d8..1f3d03e 100644 +index d074aa9..3d5fefd 100644 --- a/sound/soc/soc-core.c +++ b/sound/soc/soc-core.c -@@ -2973,8 +2973,8 @@ int snd_soc_info_volsw_range(struct snd_kcontrol *kcontrol, +@@ -2995,8 +2995,8 @@ int snd_soc_info_volsw_range(struct snd_kcontrol *kcontrol, uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->count = snd_soc_volsw_is_stereo(mc) ? 2 : 1; @@ -111458,7 +108892,7 @@ index b87d7d8..1f3d03e 100644 return 0; } -@@ -3005,9 +3005,10 @@ int snd_soc_put_volsw_range(struct snd_kcontrol *kcontrol, +@@ -3027,9 +3027,10 @@ int snd_soc_put_volsw_range(struct snd_kcontrol *kcontrol, unsigned int val, val_mask; int ret; @@ -111471,7 +108905,7 @@ index b87d7d8..1f3d03e 100644 val_mask = mask << shift; val = val << shift; -@@ -3016,9 +3017,10 @@ int snd_soc_put_volsw_range(struct snd_kcontrol *kcontrol, +@@ -3038,9 +3039,10 @@ int snd_soc_put_volsw_range(struct snd_kcontrol *kcontrol, return ret; if (snd_soc_volsw_is_stereo(mc)) { @@ -111484,7 +108918,7 @@ index b87d7d8..1f3d03e 100644 val_mask = mask << shift; val = val << shift; -@@ -3062,9 +3064,7 @@ int snd_soc_get_volsw_range(struct snd_kcontrol *kcontrol, +@@ -3084,9 +3086,7 @@ int snd_soc_get_volsw_range(struct snd_kcontrol *kcontrol, ucontrol->value.integer.value[0] = (val >> shift) & mask; if (invert) ucontrol->value.integer.value[0] = @@ -111495,7 +108929,7 @@ index b87d7d8..1f3d03e 100644 if (snd_soc_volsw_is_stereo(mc)) { ret = snd_soc_component_read(component, rreg, &val); -@@ -3074,9 +3074,7 @@ int snd_soc_get_volsw_range(struct snd_kcontrol *kcontrol, +@@ -3096,9 +3096,7 @@ int snd_soc_get_volsw_range(struct snd_kcontrol *kcontrol, ucontrol->value.integer.value[1] = (val >> shift) & mask; if (invert) ucontrol->value.integer.value[1] = @@ -111507,10 +108941,10 @@ index b87d7d8..1f3d03e 100644 return 0; -From 9776eb7b723a9a1c8b1b821981b7373c13d393de Mon Sep 17 00:00:00 2001 +From 07f408267f733baf3b580c87f00dc1500a1f2132 Mon Sep 17 00:00:00 2001 From: Howard Mitchell Date: Fri, 28 Mar 2014 16:40:31 +0000 -Subject: [PATCH 48/94] pcm512x: Use a range macro for Volume and rename to +Subject: [PATCH 46/82] pcm512x: Use a range macro for Volume and rename to PCM. This allows limiting the output gain to avoid clipping in the @@ -111520,14 +108954,14 @@ DAC ouput stages. 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/pcm512x.c b/sound/soc/codecs/pcm512x.c -index 163ec38..1466955 100644 +index 0c8aefa..8252e6d 100644 --- a/sound/soc/codecs/pcm512x.c +++ b/sound/soc/codecs/pcm512x.c @@ -259,8 +259,8 @@ static const struct soc_enum pcm512x_veds = pcm512x_ramp_step_text); static const struct snd_kcontrol_new pcm512x_controls[] = { --SOC_DOUBLE_R_TLV("Playback Digital Volume", PCM512x_DIGITAL_VOLUME_2, +-SOC_DOUBLE_R_TLV("Digital Playback Volume", PCM512x_DIGITAL_VOLUME_2, - PCM512x_DIGITAL_VOLUME_3, 0, 255, 1, digital_tlv), +SOC_DOUBLE_R_RANGE_TLV("PCM", PCM512x_DIGITAL_VOLUME_2, + PCM512x_DIGITAL_VOLUME_3, 0, 40, 255, 1, digital_tlv), @@ -111535,10 +108969,10 @@ index 163ec38..1466955 100644 PCM512x_LAGN_SHIFT, PCM512x_RAGN_SHIFT, 1, 1, analog_tlv), SOC_DOUBLE_TLV("Playback Boost Volume", PCM512x_ANALOG_GAIN_BOOST, -From 1735fd793c3693f19f465396fa8de1d52ad5500b Mon Sep 17 00:00:00 2001 +From 1c5a6fdc9411601c9c5772812377f3ae44a837e8 Mon Sep 17 00:00:00 2001 From: Gordon Hollingworth Date: Fri, 2 May 2014 16:13:59 +0100 -Subject: [PATCH 49/94] Move GPIO setup to hw_params. +Subject: [PATCH 47/82] Move GPIO setup to hw_params. This is used to stop the I2S driver from breaking the GPIO setup for other uses of the PCM interface @@ -111547,7 +108981,7 @@ the GPIO setup for other uses of the PCM interface 1 file changed, 28 insertions(+), 27 deletions(-) diff --git a/sound/soc/bcm/bcm2708-i2s.c b/sound/soc/bcm/bcm2708-i2s.c -index b25e158..9976571 100644 +index fd50e2d..0c20d4d 100644 --- a/sound/soc/bcm/bcm2708-i2s.c +++ b/sound/soc/bcm/bcm2708-i2s.c @@ -305,6 +305,31 @@ static int bcm2708_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai, @@ -111634,10 +109068,10 @@ index b25e158..9976571 100644 dev->clk_regmap = regmap[1]; -From 61b6816da3847b9241a7eb6c38e8bcf356abe135 Mon Sep 17 00:00:00 2001 +From ab018fb7d84e887607a1953cfd293ea7d411e90f Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 18 Jun 2014 13:42:01 +0100 -Subject: [PATCH 50/94] vmstat: Workaround for issue where dirty page count +Subject: [PATCH 48/82] vmstat: Workaround for issue where dirty page count goes negative See: @@ -111664,10 +109098,10 @@ index 82e7db7..f87d16d 100644 static inline void __inc_zone_page_state(struct page *page, -From 8ba5c5f91663aecc77b3eed5c43c3053c0c450bc Mon Sep 17 00:00:00 2001 +From 79cb93bd5d38be118bdf9a54dbfdf1c5f02e54d6 Mon Sep 17 00:00:00 2001 From: P33M Date: Fri, 20 Jun 2014 16:03:12 +0100 -Subject: [PATCH 51/94] dwc_otg: Fix various issues with root port and +Subject: [PATCH 49/82] dwc_otg: Fix various issues with root port and transaction errors Process the host port interrupts correctly (and don't trample them). @@ -111737,10 +109171,10 @@ index d3e2035..6182d3e 100644 fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "RESET "); } -From 47614d6b2e379e784720eacc2e271b5f89dbfc97 Mon Sep 17 00:00:00 2001 +From 16557844a1b480d65a7e66308a0b81e8c3f96506 Mon Sep 17 00:00:00 2001 From: P33M Date: Fri, 20 Jun 2014 17:23:20 +0100 -Subject: [PATCH 52/94] fiq_fsm: Implement hack for Split Interrupt +Subject: [PATCH 50/82] fiq_fsm: Implement hack for Split Interrupt transactions Hubs aren't too picky about which endpoint we send Control type split @@ -111759,10 +109193,10 @@ Original idea by Hans Petter Selasky @ FreeBSD.org. 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -index daea770..35721e5 100644 +index ebc3553..c39ef31 100644 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -@@ -1050,10 +1050,11 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) +@@ -1055,10 +1055,11 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) for (i=0; i < hcd->core_if->core_params->host_channels; i++) { dwc_otg_cleanup_fiq_channel(hcd, i); } @@ -111776,7 +109210,7 @@ index daea770..35721e5 100644 } } -@@ -1784,6 +1785,20 @@ int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) +@@ -1789,6 +1790,20 @@ int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) st->hcintmsk_copy.b.chhltd = 1; st->hcintmsk_copy.b.ahberr = 1; @@ -111797,7 +109231,7 @@ index daea770..35721e5 100644 DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32); DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32); DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32); -@@ -1837,6 +1852,9 @@ int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) +@@ -1842,6 +1857,9 @@ int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) } } } @@ -111807,7 +109241,7 @@ index daea770..35721e5 100644 fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d %01d", hc->hc_num, start_immediate); fiq_print(FIQDBG_INT, hcd->fiq_state, "%08d", hfnum.b.frrem); //fiq_print(FIQDBG_INT, hcd->fiq_state, "H:%02dP:%02d", hub_addr, port_addr); -@@ -1868,11 +1886,13 @@ int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) +@@ -1873,11 +1891,13 @@ int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) } break; case UE_INTERRUPT: @@ -111826,10 +109260,10 @@ index daea770..35721e5 100644 break; } -From 4c6a19f732d959989328ba7bdda2d75286736f1e Mon Sep 17 00:00:00 2001 +From 5adf83fe8754c3f75e71334689816411f4e61e20 Mon Sep 17 00:00:00 2001 From: notro Date: Sun, 6 Jul 2014 12:07:25 +0200 -Subject: [PATCH 53/94] spi-bcm2708: Prepare for Common Clock Framework +Subject: [PATCH 51/82] spi-bcm2708: Prepare for Common Clock Framework migration As part of migrating to use the Common Clock Framework, replace clk_enable() @@ -111874,10 +109308,10 @@ index b04a57d..349d21f 100644 free_irq(bs->irq, master); iounmap(bs->base); -From 8419618a20b32f53091e548de8b3179efb443b71 Mon Sep 17 00:00:00 2001 +From 4ec46a65f299aed7ce5360cfa5dee1153af6120c Mon Sep 17 00:00:00 2001 From: notro Date: Sun, 6 Jul 2014 12:09:30 +0200 -Subject: [PATCH 54/94] BCM2708: Migrate to the Common Clock Framework +Subject: [PATCH 52/82] BCM2708: Migrate to the Common Clock Framework As part of moving towards using Device Tree, the Common Clock Framework has to be used instead of the BCM2708 clock implementation. @@ -111898,10 +109332,10 @@ Signed-off-by: Noralf Tronnes delete mode 100644 arch/arm/mach-bcm2708/clock.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index d0c3229..9ff6999 100644 +index 8303659..fa220bc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -378,11 +378,10 @@ config ARCH_BCM2708 +@@ -382,11 +382,10 @@ config ARCH_BCM2708 bool "Broadcom BCM2708 family" select CPU_V6 select ARM_AMBA @@ -111927,7 +109361,7 @@ index a722f3f..21e3521 100644 obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index f717a59..674e5aa 100644 +index 633be19..ef12cb8 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c @@ -27,6 +27,8 @@ @@ -112036,7 +109470,7 @@ index f717a59..674e5aa 100644 #define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ } #define UART0_DMA { 15, 14 } -@@ -783,11 +772,7 @@ void __init bcm2708_init(void) +@@ -755,11 +744,7 @@ void __init bcm2708_init(void) printk("bcm2708.uart_clock = %d\n", uart_clock); pm_power_off = bcm2708_power_off; @@ -112147,10 +109581,10 @@ index 5f9d725..0000000 - unsigned long rate; -}; -From 2b75bfbf32d5a53497215f51259e4e123accd3f7 Mon Sep 17 00:00:00 2001 +From 9d238e8eab9bd67713b04ce5c6979ed7a98f62d8 Mon Sep 17 00:00:00 2001 From: notro Date: Wed, 9 Jul 2014 14:46:08 +0200 -Subject: [PATCH 55/94] BCM2708: Add core Device Tree support +Subject: [PATCH 53/82] BCM2708: Add core Device Tree support Add the bare minimum needed to boot BCM2708 from a Device Tree. @@ -112166,7 +109600,7 @@ Signed-off-by: Noralf Tronnes create mode 100644 arch/arm/boot/dts/bcm2708.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile -index adb5ed9..942249e 100644 +index b8c5cd3..147c543 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb @@ -112244,7 +109678,7 @@ index e151ed4..182e7ba 100644 bool "BCM2708 gpio support" depends on MACH_BCM2708 diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 674e5aa..83277d1f 100644 +index ef12cb8..747e27a 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c @@ -33,6 +33,7 @@ @@ -112255,7 +109689,7 @@ index 674e5aa..83277d1f 100644 #include #include -@@ -762,6 +763,22 @@ static void bcm2708_power_off(void) +@@ -734,6 +735,22 @@ static void bcm2708_power_off(void) } } @@ -112278,7 +109712,7 @@ index 674e5aa..83277d1f 100644 void __init bcm2708_init(void) { int i; -@@ -773,6 +790,7 @@ void __init bcm2708_init(void) +@@ -745,6 +762,7 @@ void __init bcm2708_init(void) pm_power_off = bcm2708_power_off; bcm2708_init_clocks(); @@ -112286,7 +109720,7 @@ index 674e5aa..83277d1f 100644 bcm_register_device(&bcm2708_dmaman_device); bcm_register_device(&bcm2708_vcio_device); -@@ -996,6 +1014,11 @@ static void __init board_reserve(void) +@@ -965,6 +983,11 @@ static void __init board_reserve(void) #endif } @@ -112298,7 +109732,7 @@ index 674e5aa..83277d1f 100644 MACHINE_START(BCM2708, "BCM2708") /* Maintainer: Broadcom Europe Ltd. */ .map_io = bcm2708_map_io, -@@ -1005,6 +1028,7 @@ MACHINE_START(BCM2708, "BCM2708") +@@ -974,6 +997,7 @@ MACHINE_START(BCM2708, "BCM2708") .init_early = bcm2708_init_early, .reserve = board_reserve, .restart = bcm2708_restart, @@ -112307,10 +109741,10 @@ index 674e5aa..83277d1f 100644 module_param(boardrev, uint, 0644); -From 63dd6c49103610f1f0f4ec0ca6a53e2e27153194 Mon Sep 17 00:00:00 2001 +From 12e35a04c0d6c8cf052f890471fd5ca8508214fc Mon Sep 17 00:00:00 2001 From: notro Date: Wed, 9 Jul 2014 14:47:48 +0200 -Subject: [PATCH 56/94] BCM2708: armctrl: Add IRQ Device Tree support +Subject: [PATCH 54/82] BCM2708: armctrl: Add IRQ Device Tree support Add Device Tree IRQ support for BCM2708. Usage is the same as for irq-bcm2835. @@ -112474,10 +109908,10 @@ index d4c5333..42f5e1c 100644 return 0; } -From 0e49e16f168532089aba638b33d3b202ec7de426 Mon Sep 17 00:00:00 2001 +From c8f19659618ef44a8c8451aa2949a0de39fe4262 Mon Sep 17 00:00:00 2001 From: notro Date: Thu, 10 Jul 2014 13:59:47 +0200 -Subject: [PATCH 57/94] pinctrl: add bcm2708 driver +Subject: [PATCH 55/82] pinctrl: add bcm2708 driver This driver is a verbatim copy of the pinctrl-bcm2835 driver, except for: * changed 2835 to 2708 @@ -112533,10 +109967,10 @@ index 182e7ba..05945d6 100644 Enable Device Tree support for BCM2708 diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig -index 0042ccb..6b55773 100644 +index bfd2c2e..977b4d6 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig -@@ -102,6 +102,11 @@ config PINCTRL_BAYTRAIL +@@ -79,6 +79,11 @@ config PINCTRL_BAYTRAIL Requires ACPI device enumeration code to set up a platform device. @@ -112549,10 +109983,10 @@ index 0042ccb..6b55773 100644 bool select PINMUX diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile -index c4b5d40..916fc61 100644 +index 05d2275..2014825 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile -@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o +@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o @@ -113340,10 +110774,10 @@ index 0000000..40d9c86 +MODULE_DESCRIPTION("BCM2708 Pin control driver"); +MODULE_LICENSE("GPL"); -From 9fc6a169ddea8269fe1df58c9004abab104f7f48 Mon Sep 17 00:00:00 2001 +From 72c98df333121827570f09791f5c4b5abcc6e577 Mon Sep 17 00:00:00 2001 From: popcornmix Date: Mon, 14 Jul 2014 22:02:09 +0100 -Subject: [PATCH 58/94] hid: Reduce default mouse polling interval to 60Hz +Subject: [PATCH 56/82] hid: Reduce default mouse polling interval to 60Hz Reduces overhead when using X --- @@ -113351,7 +110785,7 @@ Reduces overhead when using X 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/hid/usbhid/hid-core.c b/drivers/hid/usbhid/hid-core.c -index 7b88f4c..016a485 100644 +index 79cf503..db5ebe7 100644 --- a/drivers/hid/usbhid/hid-core.c +++ b/drivers/hid/usbhid/hid-core.c @@ -49,7 +49,7 @@ @@ -113363,7 +110797,7 @@ index 7b88f4c..016a485 100644 module_param_named(mousepoll, hid_mousepoll_interval, uint, 0644); MODULE_PARM_DESC(mousepoll, "Polling interval of mice"); -@@ -1090,8 +1090,12 @@ static int usbhid_start(struct hid_device *hid) +@@ -1091,8 +1091,12 @@ static int usbhid_start(struct hid_device *hid) } /* Change the polling interval of mice. */ @@ -113379,10 +110813,10 @@ index 7b88f4c..016a485 100644 ret = -ENOMEM; if (usb_endpoint_dir_in(endpoint)) { -From e20b16f3b5dfcf6371790f16f5cdecde921b5130 Mon Sep 17 00:00:00 2001 +From 62253dc0f499215fcc78175b6c56abc68c082078 Mon Sep 17 00:00:00 2001 From: notro Date: Fri, 18 Jul 2014 18:15:57 +0200 -Subject: [PATCH 59/94] BCM2708: DT: change 'axi' nodename to 'soc' +Subject: [PATCH 57/82] BCM2708: DT: change 'axi' nodename to 'soc' Change DT node named 'axi' to 'soc' so it matches ARCH_BCM2835. The VC4 bootloader fills in certain properties in the 'axi' subtree, @@ -113407,10 +110841,10 @@ index 3f884b3..e02e67b 100644 #address-cells = <1>; #size-cells = <1>; -From d6cc30d753e10383f8abe7799caec57d27a3a600 Mon Sep 17 00:00:00 2001 +From df1dfe707af557bed838c72368580d3ae38d7781 Mon Sep 17 00:00:00 2001 From: notro Date: Sun, 27 Jul 2014 20:12:58 +0200 -Subject: [PATCH 60/94] spi: bcm2708: add device tree support +Subject: [PATCH 58/82] spi: bcm2708: add device tree support Add DT support to driver and add to .dtsi file. Setup pins and spidev in .dts file. @@ -113529,10 +110963,10 @@ index 349d21f..041b5e2 100644 .probe = bcm2708_spi_probe, .remove = bcm2708_spi_remove, -From 0ba6413e40b88c218a91e38eae5b0e869dd8d87f Mon Sep 17 00:00:00 2001 +From ae499db61586a7362ecb7a53bf83e71d82b7fbdf Mon Sep 17 00:00:00 2001 From: notro Date: Sun, 27 Jul 2014 20:13:44 +0200 -Subject: [PATCH 61/94] BCM2708: don't register SPI controller when using DT +Subject: [PATCH 59/82] BCM2708: don't register SPI controller when using DT The device for the SPI controller is in the Device Tree. Only register the device when not using DT. @@ -113557,10 +110991,10 @@ index 05945d6..1f29d7d 100644 default y help diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index 83277d1f..a4286e9 100644 +index 747e27a..0434cbf 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -514,6 +514,7 @@ static struct platform_device bcm2708_alsa_devices[] = { +@@ -486,6 +486,7 @@ static struct platform_device bcm2708_alsa_devices[] = { }, }; @@ -113568,7 +111002,7 @@ index 83277d1f..a4286e9 100644 static struct resource bcm2708_spi_resources[] = { { .start = SPI0_BASE, -@@ -537,6 +538,7 @@ static struct platform_device bcm2708_spi_device = { +@@ -509,6 +510,7 @@ static struct platform_device bcm2708_spi_device = { .dma_mask = &bcm2708_spi_dmamask, .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)}, }; @@ -113576,7 +111010,7 @@ index 83277d1f..a4286e9 100644 #ifdef CONFIG_BCM2708_SPIDEV static struct spi_board_info bcm2708_spi_devices[] = { -@@ -698,6 +700,16 @@ int __init bcm_register_device(struct platform_device *pdev) +@@ -670,6 +672,16 @@ int __init bcm_register_device(struct platform_device *pdev) return ret; } @@ -113593,7 +111027,7 @@ index 83277d1f..a4286e9 100644 int calc_rsts(int partition) { return PM_PASSWORD | -@@ -815,7 +827,7 @@ void __init bcm2708_init(void) +@@ -784,7 +796,7 @@ void __init bcm2708_init(void) for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) bcm_register_device(&bcm2708_alsa_devices[i]); @@ -113603,10 +111037,10 @@ index 83277d1f..a4286e9 100644 bcm_register_device(&bcm2708_bsc1_device); -From 6aaedef2fbf03ada1f5061390771291e0a4b0ba2 Mon Sep 17 00:00:00 2001 +From 3a48251da38791c8fbd3db6d5deccee869c2edf8 Mon Sep 17 00:00:00 2001 From: notro Date: Sun, 27 Jul 2014 20:14:05 +0200 -Subject: [PATCH 62/94] spi: bcm2835: make driver available on ARCH_BCM2708 +Subject: [PATCH 60/82] spi: bcm2835: make driver available on ARCH_BCM2708 Make this driver available on ARCH_BCM2708 @@ -113616,7 +111050,7 @@ Signed-off-by: Noralf Tronnes 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig -index cb20594..54aac0f 100644 +index 6a7943c..6600723 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -76,7 +76,7 @@ config SPI_ATMEL @@ -113629,10 +111063,10 @@ index cb20594..54aac0f 100644 This selects a driver for the Broadcom BCM2835 SPI master. -From dcc9c0bc8624de2ee2f77b093f348ecfeef7dd6b Mon Sep 17 00:00:00 2001 +From 4512e24fd6757653c0eb4311ca56c1d63396da5d Mon Sep 17 00:00:00 2001 From: notro Date: Tue, 29 Jul 2014 11:04:49 +0200 -Subject: [PATCH 63/94] i2c: bcm2708: add device tree support +Subject: [PATCH 61/82] i2c: bcm2708: add device tree support Add DT support to driver and add to .dtsi file. Setup pins in .dts file. @@ -113797,10 +111231,10 @@ index 8750634..728cb69 100644 .probe = bcm2708_i2c_probe, .remove = bcm2708_i2c_remove, -From 07ded1952cc830dc6db189b5412aa75f7af20d21 Mon Sep 17 00:00:00 2001 +From 87ca98a34f4ca7f95f8a9ff0a3770aab096f16cb Mon Sep 17 00:00:00 2001 From: notro Date: Tue, 29 Jul 2014 11:05:18 +0200 -Subject: [PATCH 64/94] bcm2708: don't register i2c controllers when using DT +Subject: [PATCH 62/82] bcm2708: don't register i2c controllers when using DT The devices for the i2c controllers are in the Device Tree. Only register devices when not using DT. @@ -113811,10 +111245,10 @@ Signed-off-by: Noralf Tronnes 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index a4286e9..a19f54d 100644 +index 0434cbf..902f8c7 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -560,6 +560,7 @@ static struct spi_board_info bcm2708_spi_devices[] = { +@@ -532,6 +532,7 @@ static struct spi_board_info bcm2708_spi_devices[] = { }; #endif @@ -113822,7 +111256,7 @@ index a4286e9..a19f54d 100644 static struct resource bcm2708_bsc0_resources[] = { { .start = BSC0_BASE, -@@ -598,6 +599,7 @@ static struct platform_device bcm2708_bsc1_device = { +@@ -570,6 +571,7 @@ static struct platform_device bcm2708_bsc1_device = { .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources), .resource = bcm2708_bsc1_resources, }; @@ -113830,7 +111264,7 @@ index a4286e9..a19f54d 100644 static struct platform_device bcm2835_hwmon_device = { .name = "bcm2835_hwmon", -@@ -828,8 +830,8 @@ void __init bcm2708_init(void) +@@ -797,8 +799,8 @@ void __init bcm2708_init(void) bcm_register_device(&bcm2708_alsa_devices[i]); bcm_register_device_dt(&bcm2708_spi_device); @@ -113842,10 +111276,10 @@ index a4286e9..a19f54d 100644 bcm_register_device(&bcm2835_hwmon_device); bcm_register_device(&bcm2835_thermal_device); -From 0b7ede139e83da2ab7151e5cbf49f5a2581cf77e Mon Sep 17 00:00:00 2001 +From d3953edb6932ecf0e738e8fd0b169c144ed79b6e Mon Sep 17 00:00:00 2001 From: notro Date: Tue, 29 Jul 2014 11:05:39 +0200 -Subject: [PATCH 65/94] i2c: bcm2835: make driver available on ARCH_BCM2708 +Subject: [PATCH 63/82] i2c: bcm2835: make driver available on ARCH_BCM2708 Make this driver available on ARCH_BCM2708 @@ -113855,10 +111289,10 @@ Signed-off-by: Noralf Tronnes 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig -index 6426811..73c9cfd 100644 +index d8f8e2a..5f62d88 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig -@@ -338,7 +338,7 @@ config I2C_AU1550 +@@ -339,7 +339,7 @@ config I2C_AU1550 config I2C_BCM2835 tristate "Broadcom BCM2835 I2C controller" @@ -113868,24 +111302,26 @@ index 6426811..73c9cfd 100644 If you say yes to this option, support will be included for the BCM2835 I2C controller. -From 30f0ba5a38268e6d665954f5cfc5ef4921da9a30 Mon Sep 17 00:00:00 2001 +From a4eb1378588a26b20fb9f43934005e42be5a1ffe Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Fri, 25 Jul 2014 07:08:09 +0200 -Subject: [PATCH 66/94] Configure GPIOs for I2S based on revision/card settings +Subject: [PATCH 64/82] Configure GPIOs for I2S based on revision/card settings With RPi model B+, assignment of the I2S GPIO pins has changed. This patch uses the board revision to auto-detect the GPIOs used for I2S. It also allows sound card drivers to set the GPIOs that should be used. This is especially important with the Compute Module. + +bcm2708-i2s: Avoid leak from iomap when accessing gpio --- - sound/soc/bcm/bcm2708-i2s.c | 51 +++++++++++++++++++++++++++++++++++++++------ - sound/soc/bcm/bcm2708-i2s.h | 35 +++++++++++++++++++++++++++++++ - 2 files changed, 80 insertions(+), 6 deletions(-) + sound/soc/bcm/bcm2708-i2s.c | 72 ++++++++++++++++++++++++++++++++++++++------- + sound/soc/bcm/bcm2708-i2s.h | 35 ++++++++++++++++++++++ + 2 files changed, 96 insertions(+), 11 deletions(-) create mode 100644 sound/soc/bcm/bcm2708-i2s.h diff --git a/sound/soc/bcm/bcm2708-i2s.c b/sound/soc/bcm/bcm2708-i2s.c -index 9976571..905f076 100644 +index 0c20d4d..9023984 100644 --- a/sound/soc/bcm/bcm2708-i2s.c +++ b/sound/soc/bcm/bcm2708-i2s.c @@ -31,6 +31,8 @@ @@ -113897,7 +111333,15 @@ index 9976571..905f076 100644 #include #include #include -@@ -46,6 +48,8 @@ +@@ -38,6 +40,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -46,6 +49,8 @@ #include #include @@ -113906,7 +111350,7 @@ index 9976571..905f076 100644 /* Clock registers */ #define BCM2708_CLK_PCMCTL_REG 0x00 #define BCM2708_CLK_PCMDIV_REG 0x04 -@@ -163,6 +167,9 @@ static const unsigned int bcm2708_clk_freq[BCM2708_CLK_SRC_HDMI+1] = { +@@ -163,6 +168,9 @@ static const unsigned int bcm2708_clk_freq[BCM2708_CLK_SRC_HDMI+1] = { #define BCM2708_DMA_DREQ_PCM_TX 2 #define BCM2708_DMA_DREQ_PCM_RX 3 @@ -113916,7 +111360,7 @@ index 9976571..905f076 100644 /* General device struct */ struct bcm2708_i2s_dev { struct device *dev; -@@ -174,6 +181,12 @@ struct bcm2708_i2s_dev { +@@ -174,6 +182,12 @@ struct bcm2708_i2s_dev { struct regmap *clk_regmap; }; @@ -113929,31 +111373,44 @@ index 9976571..905f076 100644 static void bcm2708_i2s_start_clock(struct bcm2708_i2s_dev *dev) { /* Start the clock if in master mode */ -@@ -305,7 +318,6 @@ static int bcm2708_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai, - return 0; +@@ -306,6 +320,25 @@ static int bcm2708_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai, } -- + ++static int bcm2708_i2s_set_function(unsigned offset, int function) ++{ ++ #define GPIOFSEL(x) (0x00+(x)*4) ++ void __iomem *gpio = __io_address(GPIO_BASE); ++ unsigned alt = function <= 3 ? function + 4: function == 4 ? 3 : 2; ++ unsigned gpiodir; ++ unsigned gpio_bank = offset / 10; ++ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; ++ ++ if (offset >= BCM2708_NR_GPIOS) ++ return -EINVAL; ++ ++ gpiodir = readl(gpio + GPIOFSEL(gpio_bank)); ++ gpiodir &= ~(7 << gpio_field_offset); ++ gpiodir |= alt << gpio_field_offset; ++ writel(gpiodir, gpio + GPIOFSEL(gpio_bank)); ++ return 0; ++} ++ static void bcm2708_i2s_setup_gpio(void) { /* -@@ -318,14 +330,41 @@ static void bcm2708_i2s_setup_gpio(void) - #define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) - - unsigned int *gpio; -- int pin; +@@ -314,20 +347,37 @@ static void bcm2708_i2s_setup_gpio(void) + * TODO Better way would be to handle + * this in the device tree! + */ +-#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3)) +-#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) + int pin,pinconfig,startpin,alt; + - gpio = ioremap(GPIO_BASE, SZ_16K); - -- /* SPI is on GPIO 7..11 */ -- for (pin = 28; pin <= 31; pin++) { -- INP_GPIO(pin); /* set mode to GPIO input first */ -- SET_GPIO_ALT(pin, 2); /* set mode to ALT 0 */ + /* SPI is on different GPIOs on different boards */ + /* for Raspberry Pi B+, this is pin GPIO18-21, for original on 28-31 */ + if (bcm2708_i2s_gpio==BCM2708_I2S_GPIO_AUTO) { -+ if (system_rev >= 0x10) { ++ if ((system_rev & 0xffffff) >= 0x10) { + /* Model B+ */ + pinconfig=BCM2708_I2S_GPIO_PIN18; + } else { @@ -113963,7 +111420,10 @@ index 9976571..905f076 100644 + } else { + pinconfig=bcm2708_i2s_gpio; + } -+ + +- unsigned int *gpio; +- int pin; +- gpio = ioremap(GPIO_BASE, SZ_16K); + if (pinconfig==BCM2708_I2S_GPIO_PIN18) { + startpin=18; + alt=BCM2708_I2S_GPIO_PIN18_ALT; @@ -113974,16 +111434,20 @@ index 9976571..905f076 100644 + printk(KERN_INFO "Can't configure I2S GPIOs, unknown pin mode for I2S: %i\n",pinconfig); + return; + } -+ + +- /* SPI is on GPIO 7..11 */ +- for (pin = 28; pin <= 31; pin++) { +- INP_GPIO(pin); /* set mode to GPIO input first */ +- SET_GPIO_ALT(pin, 2); /* set mode to ALT 0 */ + /* configure I2S pins to correct ALT mode */ + for (pin = startpin; pin <= startpin+3; pin++) { -+ INP_GPIO(pin); /* set mode to GPIO input first */ -+ SET_GPIO_ALT(pin, alt); /* set mode to ALT */ ++ bcm2708_i2s_set_function(pin, alt); } -+ - #undef INP_GPIO - #undef SET_GPIO_ALT +-#undef INP_GPIO +-#undef SET_GPIO_ALT } + + static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream, diff --git a/sound/soc/bcm/bcm2708-i2s.h b/sound/soc/bcm/bcm2708-i2s.h new file mode 100644 index 0000000..94fed6a @@ -114026,10 +111490,10 @@ index 0000000..94fed6a + +#endif -From e1b3205dea5df5f79f1a79efbb28d0cdb417a801 Mon Sep 17 00:00:00 2001 +From 6d36ce61af48e3985386d55689b45909ba13ab43 Mon Sep 17 00:00:00 2001 From: P33M Date: Thu, 24 Jul 2014 21:24:03 +0100 -Subject: [PATCH 67/94] usb: core: make overcurrent messages more prominent +Subject: [PATCH 65/82] usb: core: make overcurrent messages more prominent Hub overcurrent messages are more serious than "debug". Increase loglevel. --- @@ -114037,10 +111501,10 @@ Hub overcurrent messages are more serious than "debug". Increase loglevel. 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c -index 27f2171..7c88f04 100644 +index dc84915..e9e061e 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c -@@ -4897,7 +4897,7 @@ static void port_event(struct usb_hub *hub, int port1) +@@ -4915,7 +4915,7 @@ static void port_event(struct usb_hub *hub, int port1) if (portchange & USB_PORT_STAT_C_OVERCURRENT) { u16 status = 0, unused; @@ -114050,10 +111514,10 @@ index 27f2171..7c88f04 100644 USB_PORT_FEAT_C_OVER_CURRENT); msleep(100); /* Cool down */ -From 45902ee57f86aab877156829d5ec20f5896b7bee Mon Sep 17 00:00:00 2001 +From b284b3f967a974ca6af7fb5088d7b4f0808578e5 Mon Sep 17 00:00:00 2001 From: Tim Gover Date: Tue, 22 Jul 2014 15:41:04 +0100 -Subject: [PATCH 68/94] vcsm: VideoCore shared memory service for BCM2835 +Subject: [PATCH 66/82] vcsm: VideoCore shared memory service for BCM2835 Add experimental support for the VideoCore shared memory service. This allows user processes to allocate memory from VideoCore's @@ -118386,10 +115850,10 @@ index 0000000..da1c523 +MODULE_DESCRIPTION("VideoCore SharedMemory Driver"); +MODULE_LICENSE("GPL v2"); -From 8d75c89327ad590f4dbc606e97fc9e1bfa7fbf49 Mon Sep 17 00:00:00 2001 +From 83850fd7d44d21476e23ca70b73402bf88c5204a Mon Sep 17 00:00:00 2001 From: popcornmix Date: Thu, 7 Aug 2014 02:03:50 +0100 -Subject: [PATCH 69/94] Revert "ARM: dma: Use dma_pfn_offset for dma address +Subject: [PATCH 67/82] Revert "ARM: dma: Use dma_pfn_offset for dma address translation" This reverts commit 6ce0d20016925d031f1e24d64302e4c976d7cec6. @@ -118441,1684 +115905,40 @@ index c45b61a..0af6bd0 100644 } -From fbabba459c67f823b397a33882a980028502ea3d Mon Sep 17 00:00:00 2001 -From: Phil Elwell -Date: Fri, 8 Aug 2014 16:22:59 +0100 -Subject: [PATCH 70/94] VCHIQ: Make service closure fully synchronous (drv) - -This is one half of a two-part patch, the other half of which is to -the vchiq_lib user library. With these patches, calls to -vchiq_close_service and vchiq_remove_service won't return until any -associated callbacks have been delivered to the callback thread. ---- - .../vc04_services/interface/vchiq_arm/vchiq_arm.c | 122 ++++++++++++++++++--- - .../vc04_services/interface/vchiq_arm/vchiq_cfg.h | 10 +- - .../vc04_services/interface/vchiq_arm/vchiq_core.c | 26 +++++ - .../vc04_services/interface/vchiq_arm/vchiq_core.h | 4 + - .../interface/vchiq_arm/vchiq_ioctl.h | 4 +- - 5 files changed, 149 insertions(+), 17 deletions(-) - -diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c -index 99c8967..793e1e9 100644 ---- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c -+++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c -@@ -113,13 +113,15 @@ typedef struct user_service_struct { - VCHIQ_SERVICE_T *service; - void *userdata; - VCHIQ_INSTANCE_T instance; -- int is_vchi; -- int dequeue_pending; -+ char is_vchi; -+ char dequeue_pending; -+ char close_pending; - int message_available_pos; - int msg_insert; - int msg_remove; - struct semaphore insert_event; - struct semaphore remove_event; -+ struct semaphore close_event; - VCHIQ_HEADER_T * msg_queue[MSG_QUEUE_SIZE]; - } USER_SERVICE_T; - -@@ -142,6 +144,7 @@ struct vchiq_instance_struct { - int closing; - int pid; - int mark; -+ int use_close_delivered; - - struct list_head bulk_waiter_list; - struct mutex bulk_waiter_list_mutex; -@@ -179,7 +182,9 @@ static const char *const ioctl_names[] = { - "USE_SERVICE", - "RELEASE_SERVICE", - "SET_SERVICE_OPTION", -- "DUMP_PHYS_MEM" -+ "DUMP_PHYS_MEM", -+ "LIB_VERSION", -+ "CLOSE_DELIVERED" - }; - - vchiq_static_assert((sizeof(ioctl_names)/sizeof(ioctl_names[0])) == -@@ -231,10 +236,13 @@ add_completion(VCHIQ_INSTANCE_T instance, VCHIQ_REASON_T reason, - completion->service_userdata = user_service->service; - completion->bulk_userdata = bulk_userdata; - -- if (reason == VCHIQ_SERVICE_CLOSED) -+ if (reason == VCHIQ_SERVICE_CLOSED) { - /* Take an extra reference, to be held until - this CLOSED notification is delivered. */ - lock_service(user_service->service); -+ if (instance->use_close_delivered) -+ user_service->close_pending = 1; -+ } - - /* A write barrier is needed here to ensure that the entire completion - record is written out before the insert point. */ -@@ -281,10 +289,10 @@ service_callback(VCHIQ_REASON_T reason, VCHIQ_HEADER_T *header, - return VCHIQ_SUCCESS; - - vchiq_log_trace(vchiq_arm_log_level, -- "service_callback - service %lx(%d), reason %d, header %lx, " -+ "service_callback - service %lx(%d,%p), reason %d, header %lx, " - "instance %lx, bulk_userdata %lx", - (unsigned long)user_service, -- service->localport, -+ service->localport, user_service->userdata, - reason, (unsigned long)header, - (unsigned long)instance, (unsigned long)bulk_userdata); - -@@ -371,10 +379,31 @@ user_service_free(void *userdata) - - /**************************************************************************** - * --* vchiq_ioctl -+* close_delivered - * - ***************************************************************************/ -+static void close_delivered(USER_SERVICE_T *user_service) -+{ -+ vchiq_log_info(vchiq_arm_log_level, -+ "close_delivered(handle=%x)", -+ user_service->service->handle); -+ -+ WARN_ON(user_service->close_pending == 0); - -+ /* Allow the underlying service to be culled */ -+ unlock_service(user_service->service); -+ -+ /* Wake the user-thread blocked in close_ or remove_service */ -+ up(&user_service->close_event); -+ -+ user_service->close_pending = 0; -+} -+ -+/**************************************************************************** -+* -+* vchiq_ioctl -+* -+***************************************************************************/ - static long - vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) - { -@@ -485,14 +514,16 @@ vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) - user_service->service = service; - user_service->userdata = userdata; - user_service->instance = instance; -- user_service->is_vchi = args.is_vchi; -+ user_service->is_vchi = (args.is_vchi != 0); - user_service->dequeue_pending = 0; -+ user_service->close_pending = 0; - user_service->message_available_pos = - instance->completion_remove - 1; - user_service->msg_insert = 0; - user_service->msg_remove = 0; - sema_init(&user_service->insert_event, 0); - sema_init(&user_service->remove_event, 0); -+ sema_init(&user_service->close_event, 0); - - if (args.is_open) { - status = vchiq_open_service_internal -@@ -526,8 +557,24 @@ vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) - VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; - - service = find_service_for_instance(instance, handle); -- if (service != NULL) -- status = vchiq_close_service(service->handle); -+ if (service != NULL) { -+ USER_SERVICE_T *user_service = -+ (USER_SERVICE_T *)service->base.userdata; -+ /* close_pending is false on first entry, and when the -+ wait in vchiq_close_service has been interrupted. */ -+ if (!user_service->close_pending) { -+ status = vchiq_close_service(service->handle); -+ if (status != VCHIQ_SUCCESS) -+ break; -+ } -+ -+ /* close_pending is true once the underlying service -+ has been closed until the client library calls the -+ CLOSE_DELIVERED ioctl, signalling close_event. */ -+ if (user_service->close_pending && -+ down_interruptible(&user_service->close_event)) -+ status = VCHIQ_RETRY; -+ } - else - ret = -EINVAL; - } break; -@@ -536,8 +583,24 @@ vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) - VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; - - service = find_service_for_instance(instance, handle); -- if (service != NULL) -- status = vchiq_remove_service(service->handle); -+ if (service != NULL) { -+ USER_SERVICE_T *user_service = -+ (USER_SERVICE_T *)service->base.userdata; -+ /* close_pending is false on first entry, and when the -+ wait in vchiq_close_service has been interrupted. */ -+ if (!user_service->close_pending) { -+ status = vchiq_remove_service(service->handle); -+ if (status != VCHIQ_SUCCESS) -+ break; -+ } -+ -+ /* close_pending is true once the underlying service -+ has been closed until the client library calls the -+ CLOSE_DELIVERED ioctl, signalling close_event. */ -+ if (user_service->close_pending && -+ down_interruptible(&user_service->close_event)) -+ status = VCHIQ_RETRY; -+ } - else - ret = -EINVAL; - } break; -@@ -804,8 +867,9 @@ vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) - completion->header = msgbuf; - } - -- if (completion->reason == -- VCHIQ_SERVICE_CLOSED) -+ if ((completion->reason == -+ VCHIQ_SERVICE_CLOSED) && -+ !instance->use_close_delivered) - unlock_service(service); - - if (copy_to_user((void __user *)( -@@ -983,6 +1047,28 @@ vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) - dump_phys_mem(args.virt_addr, args.num_bytes); - } break; - -+ case VCHIQ_IOC_LIB_VERSION: { -+ unsigned int lib_version = (unsigned int)arg; -+ -+ if (lib_version < VCHIQ_VERSION_MIN) -+ ret = -EINVAL; -+ else if (lib_version >= VCHIQ_VERSION_CLOSE_DELIVERED) -+ instance->use_close_delivered = 1; -+ } break; -+ -+ case VCHIQ_IOC_CLOSE_DELIVERED: { -+ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; -+ -+ service = find_closed_service_for_instance(instance, handle); -+ if (service != NULL) { -+ USER_SERVICE_T *user_service = -+ (USER_SERVICE_T *)service->base.userdata; -+ close_delivered(user_service); -+ } -+ else -+ ret = -EINVAL; -+ } break; -+ - default: - ret = -ENOTTY; - break; -@@ -1170,7 +1256,15 @@ vchiq_release(struct inode *inode, struct file *file) - (MAX_COMPLETIONS - 1)]; - service = completion->service_userdata; - if (completion->reason == VCHIQ_SERVICE_CLOSED) -+ { -+ USER_SERVICE_T *user_service = -+ service->base.userdata; -+ -+ /* Wake any blocked user-thread */ -+ if (instance->use_close_delivered) -+ up(&user_service->close_event); - unlock_service(service); -+ } - instance->completion_remove++; - } - -diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h -index 493c86c..c382740 100644 ---- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h -+++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h -@@ -1,5 +1,5 @@ - /** -- * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * Copyright (c) 2010-2014 Broadcom. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions -@@ -36,11 +36,17 @@ - - #define VCHIQ_MAGIC VCHIQ_MAKE_FOURCC('V', 'C', 'H', 'I') - /* The version of VCHIQ - change with any non-trivial change */ --#define VCHIQ_VERSION 6 -+#define VCHIQ_VERSION 7 - /* The minimum compatible version - update to match VCHIQ_VERSION with any - ** incompatible change */ - #define VCHIQ_VERSION_MIN 3 - -+/* The version that introduced the VCHIQ_IOC_LIB_VERSION ioctl */ -+#define VCHIQ_VERSION_LIB_VERSION 7 -+ -+/* The version that introduced the VCHIQ_IOC_CLOSE_DELIVERED ioctl */ -+#define VCHIQ_VERSION_CLOSE_DELIVERED 7 -+ - #define VCHIQ_MAX_STATES 1 - #define VCHIQ_MAX_SERVICES 4096 - #define VCHIQ_MAX_SLOTS 128 -diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c -index 71ed0a5..726107e 100644 ---- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c -+++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c -@@ -224,6 +224,31 @@ find_service_for_instance(VCHIQ_INSTANCE_T instance, - } - - VCHIQ_SERVICE_T * -+find_closed_service_for_instance(VCHIQ_INSTANCE_T instance, -+ VCHIQ_SERVICE_HANDLE_T handle) { -+ VCHIQ_SERVICE_T *service; -+ -+ spin_lock(&service_spinlock); -+ service = handle_to_service(handle); -+ if (service && -+ ((service->srvstate == VCHIQ_SRVSTATE_FREE) || -+ (service->srvstate == VCHIQ_SRVSTATE_CLOSED)) && -+ (service->handle == handle) && -+ (service->instance == instance)) { -+ BUG_ON(service->ref_count == 0); -+ service->ref_count++; -+ } else -+ service = NULL; -+ spin_unlock(&service_spinlock); -+ -+ if (!service) -+ vchiq_log_info(vchiq_core_log_level, -+ "Invalid service handle 0x%x", handle); -+ -+ return service; -+} -+ -+VCHIQ_SERVICE_T * - next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance, - int *pidx) - { -@@ -2632,6 +2657,7 @@ vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id) - VCHIQ_MAKE_MSG(VCHIQ_MSG_OPEN, service->localport, 0), - &body, 1, sizeof(payload), 1); - if (status == VCHIQ_SUCCESS) { -+ /* Wait for the ACK/NAK */ - if (down_interruptible(&service->remove_event) != 0) { - status = VCHIQ_RETRY; - vchiq_release_service_internal(service); -diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h -index 47cdf27..4baf536 100644 ---- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h -+++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h -@@ -605,6 +605,10 @@ find_service_for_instance(VCHIQ_INSTANCE_T instance, - VCHIQ_SERVICE_HANDLE_T handle); - - extern VCHIQ_SERVICE_T * -+find_closed_service_for_instance(VCHIQ_INSTANCE_T instance, -+ VCHIQ_SERVICE_HANDLE_T handle); -+ -+extern VCHIQ_SERVICE_T * - next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance, - int *pidx); - -diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h -index e248037..6137ae9 100644 ---- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h -+++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h -@@ -124,6 +124,8 @@ typedef struct { - _IOW(VCHIQ_IOC_MAGIC, 14, VCHIQ_SET_SERVICE_OPTION_T) - #define VCHIQ_IOC_DUMP_PHYS_MEM \ - _IOW(VCHIQ_IOC_MAGIC, 15, VCHIQ_DUMP_MEM_T) --#define VCHIQ_IOC_MAX 15 -+#define VCHIQ_IOC_LIB_VERSION _IO(VCHIQ_IOC_MAGIC, 16) -+#define VCHIQ_IOC_CLOSE_DELIVERED _IO(VCHIQ_IOC_MAGIC, 17) -+#define VCHIQ_IOC_MAX 17 - - #endif - -From 233b56a327a92c3aa78fe599c59c192b3ad224cc Mon Sep 17 00:00:00 2001 -From: gellert -Date: Tue, 29 Jul 2014 17:43:37 +0100 -Subject: [PATCH 71/94] dmaengine: expand functionality by supporting - scatter/gather transfers sdhci-bcm2708 and dma.c: fix for LITE channels - ---- - arch/arm/mach-bcm2708/dma.c | 2 + - arch/arm/mach-bcm2708/include/mach/dma.h | 6 +- - drivers/dma/bcm2708-dmaengine.c | 731 +++++++++++++++++++++++++------ - drivers/mmc/host/sdhci-bcm2708.c | 113 +++-- - 4 files changed, 667 insertions(+), 185 deletions(-) - -diff --git a/arch/arm/mach-bcm2708/dma.c b/arch/arm/mach-bcm2708/dma.c -index 1da2413..a5e58d1 100644 ---- a/arch/arm/mach-bcm2708/dma.c -+++ b/arch/arm/mach-bcm2708/dma.c -@@ -156,6 +156,8 @@ static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base, - dmaman->chan_available = chans_available; - dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* chans 2 & 3 */ - dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* chan 0 */ -+ dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe; /* chans 1 to 7 */ -+ dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00; /* chans 8 to 14 */ - } - - static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman, -diff --git a/arch/arm/mach-bcm2708/include/mach/dma.h b/arch/arm/mach-bcm2708/include/mach/dma.h -index a4aac4c..d03e7b5 100644 ---- a/arch/arm/mach-bcm2708/include/mach/dma.h -+++ b/arch/arm/mach-bcm2708/include/mach/dma.h -@@ -77,9 +77,13 @@ extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base); - those with higher priority smaller ordinal numbers */ - #define BCM_DMA_FEATURE_FAST_ORD 0 - #define BCM_DMA_FEATURE_BULK_ORD 1 -+#define BCM_DMA_FEATURE_NORMAL_ORD 2 -+#define BCM_DMA_FEATURE_LITE_ORD 3 - #define BCM_DMA_FEATURE_FAST (1< -- * Copyright 2013 -+ * Gellert Weisz -+ * Copyright 2013-2014 - * - * Based on - * OMAP DMAengine support by Russell King -@@ -29,6 +29,7 @@ - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -+ - #include - #include - #include -@@ -40,21 +41,40 @@ - #include - #include - #include --#include - --#include "virt-dma.h" -+#ifndef CONFIG_OF - -+/* dma manager */ - #include --#include - --struct bcm2708_dmadev { -+//#define DMA_COMPLETE DMA_SUCCESS -+ -+#endif -+ -+#include -+#include -+ -+#include "virt-dma.h" -+ -+ -+struct bcm2835_dmadev { - struct dma_device ddev; - spinlock_t lock; - void __iomem *base; - struct device_dma_parameters dma_parms; - }; - --struct bcm2708_chan { -+struct bcm2835_dma_cb { -+ uint32_t info; -+ uint32_t src; -+ uint32_t dst; -+ uint32_t length; -+ uint32_t stride; -+ uint32_t next; -+ uint32_t pad[2]; -+}; -+ -+struct bcm2835_chan { - struct virt_dma_chan vc; - struct list_head node; - -@@ -62,48 +82,106 @@ struct bcm2708_chan { - bool cyclic; - - int ch; -- struct bcm2708_desc *desc; -+ struct bcm2835_desc *desc; - - void __iomem *chan_base; - int irq_number; -+ -+ unsigned int dreq; - }; - --struct bcm2708_desc { -+struct bcm2835_desc { - struct virt_dma_desc vd; - enum dma_transfer_direction dir; - - unsigned int control_block_size; -- struct bcm2708_dma_cb *control_block_base; -+ struct bcm2835_dma_cb *control_block_base; - dma_addr_t control_block_base_phys; - -- unsigned frames; -+ unsigned int frames; - size_t size; - }; - --#define BCM2708_DMA_DATA_TYPE_S8 1 --#define BCM2708_DMA_DATA_TYPE_S16 2 --#define BCM2708_DMA_DATA_TYPE_S32 4 --#define BCM2708_DMA_DATA_TYPE_S128 16 -+#define BCM2835_DMA_CS 0x00 -+#define BCM2835_DMA_ADDR 0x04 -+#define BCM2835_DMA_SOURCE_AD 0x0c -+#define BCM2835_DMA_DEST_AD 0x10 -+#define BCM2835_DMA_NEXTCB 0x1C -+ -+/* DMA CS Control and Status bits */ -+#define BCM2835_DMA_ACTIVE BIT(0) -+#define BCM2835_DMA_INT BIT(2) -+#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */ -+#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */ -+#define BCM2835_DMA_ERR BIT(8) -+#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */ -+#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */ -+ -+#define BCM2835_DMA_INT_EN BIT(0) -+#define BCM2835_DMA_WAIT_RESP BIT(3) -+#define BCM2835_DMA_D_INC BIT(4) -+#define BCM2835_DMA_D_WIDTH BIT(5) -+#define BCM2835_DMA_D_DREQ BIT(6) -+#define BCM2835_DMA_S_INC BIT(8) -+#define BCM2835_DMA_S_WIDTH BIT(9) -+#define BCM2835_DMA_S_DREQ BIT(10) - --static inline struct bcm2708_dmadev *to_bcm2708_dma_dev(struct dma_device *d) -+#define BCM2835_DMA_PER_MAP(x) ((x) << 16) -+#define BCM2835_DMA_WAITS(x) (((x)&0x1f) << 21) -+ -+#define SDHCI_BCM_DMA_WAITS 0 /* delays slowing DMA transfers: 0-31 */ -+ -+#define BCM2835_DMA_DATA_TYPE_S8 1 -+#define BCM2835_DMA_DATA_TYPE_S16 2 -+#define BCM2835_DMA_DATA_TYPE_S32 4 -+#define BCM2835_DMA_DATA_TYPE_S128 16 -+ -+#define BCM2835_DMA_BULK_MASK BIT(0) -+#define BCM2835_DMA_FIQ_MASK (BIT(2) | BIT(3)) -+ -+ -+/* Valid only for channels 0 - 14, 15 has its own base address */ -+#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */ -+#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n)) -+ -+#define MAX_LITE_TRANSFER 32768 -+#define MAX_NORMAL_TRANSFER 1073741824 -+ -+static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d) - { -- return container_of(d, struct bcm2708_dmadev, ddev); -+ return container_of(d, struct bcm2835_dmadev, ddev); - } - --static inline struct bcm2708_chan *to_bcm2708_dma_chan(struct dma_chan *c) -+static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c) - { -- return container_of(c, struct bcm2708_chan, vc.chan); -+ return container_of(c, struct bcm2835_chan, vc.chan); - } - --static inline struct bcm2708_desc *to_bcm2708_dma_desc( -+static inline struct bcm2835_desc *to_bcm2835_dma_desc( - struct dma_async_tx_descriptor *t) - { -- return container_of(t, struct bcm2708_desc, vd.tx); -+ return container_of(t, struct bcm2835_desc, vd.tx); - } - --static void bcm2708_dma_desc_free(struct virt_dma_desc *vd) -+static void dma_dumpregs(struct bcm2835_chan *c) - { -- struct bcm2708_desc *desc = container_of(vd, struct bcm2708_desc, vd); -+ pr_debug("-------------DMA DUMPREGS-------------\n"); -+ pr_debug("CS= %u\n", -+ readl(c->chan_base + BCM2835_DMA_CS)); -+ pr_debug("ADDR= %u\n", -+ readl(c->chan_base + BCM2835_DMA_ADDR)); -+ pr_debug("SOURCE_ADDR= %u\n", -+ readl(c->chan_base + BCM2835_DMA_SOURCE_AD)); -+ pr_debug("DEST_AD= %u\n", -+ readl(c->chan_base + BCM2835_DMA_DEST_AD)); -+ pr_debug("NEXTCB= %u\n", -+ readl(c->chan_base + BCM2835_DMA_NEXTCB)); -+ pr_debug("--------------------------------------\n"); -+} -+ -+static void bcm2835_dma_desc_free(struct virt_dma_desc *vd) -+{ -+ struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd); - dma_free_coherent(desc->vd.tx.chan->device->dev, - desc->control_block_size, - desc->control_block_base, -@@ -111,10 +189,46 @@ static void bcm2708_dma_desc_free(struct virt_dma_desc *vd) - kfree(desc); - } - --static void bcm2708_dma_start_desc(struct bcm2708_chan *c) -+static int bcm2835_dma_abort(void __iomem *chan_base) -+{ -+ unsigned long cs; -+ long int timeout = 10000; -+ -+ cs = readl(chan_base + BCM2835_DMA_CS); -+ if (!(cs & BCM2835_DMA_ACTIVE)) -+ return 0; -+ -+ /* Write 0 to the active bit - Pause the DMA */ -+ writel(0, chan_base + BCM2835_DMA_CS); -+ -+ /* Wait for any current AXI transfer to complete */ -+ while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) { -+ cpu_relax(); -+ cs = readl(chan_base + BCM2835_DMA_CS); -+ } -+ -+ /* We'll un-pause when we set of our next DMA */ -+ if (!timeout) -+ return -ETIMEDOUT; -+ -+ if (!(cs & BCM2835_DMA_ACTIVE)) -+ return 0; -+ -+ /* Terminate the control block chain */ -+ writel(0, chan_base + BCM2835_DMA_NEXTCB); -+ -+ /* Abort the whole DMA */ -+ writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE, -+ chan_base + BCM2835_DMA_CS); -+ -+ return 0; -+} -+ -+ -+static void bcm2835_dma_start_desc(struct bcm2835_chan *c) - { - struct virt_dma_desc *vd = vchan_next_desc(&c->vc); -- struct bcm2708_desc *d; -+ struct bcm2835_desc *d; - - if (!vd) { - c->desc = NULL; -@@ -123,49 +237,62 @@ static void bcm2708_dma_start_desc(struct bcm2708_chan *c) - - list_del(&vd->node); - -- c->desc = d = to_bcm2708_dma_desc(&vd->tx); -+ c->desc = d = to_bcm2835_dma_desc(&vd->tx); -+ -+ writel(d->control_block_base_phys, c->chan_base + BCM2835_DMA_ADDR); -+ writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); - -- bcm_dma_start(c->chan_base, d->control_block_base_phys); - } - --static irqreturn_t bcm2708_dma_callback(int irq, void *data) -+static irqreturn_t bcm2835_dma_callback(int irq, void *data) - { -- struct bcm2708_chan *c = data; -- struct bcm2708_desc *d; -+ struct bcm2835_chan *c = data; -+ struct bcm2835_desc *d; - unsigned long flags; - - spin_lock_irqsave(&c->vc.lock, flags); - - /* Acknowledge interrupt */ -- writel(BCM2708_DMA_INT, c->chan_base + BCM2708_DMA_CS); -+ writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS); - - d = c->desc; - - if (d) { -- /* TODO Only works for cyclic DMA */ -- vchan_cyclic_callback(&d->vd); -- } -+ if (c->cyclic) { -+ vchan_cyclic_callback(&d->vd); - -- /* Keep the DMA engine running */ -- dsb(); /* ARM synchronization barrier */ -- writel(BCM2708_DMA_ACTIVE, c->chan_base + BCM2708_DMA_CS); -+ /* Keep the DMA engine running */ -+ writel(BCM2835_DMA_ACTIVE, -+ c->chan_base + BCM2835_DMA_CS); -+ -+ } else { -+ vchan_cookie_complete(&c->desc->vd); -+ bcm2835_dma_start_desc(c); -+ } -+ } - - spin_unlock_irqrestore(&c->vc.lock, flags); - - return IRQ_HANDLED; - } - --static int bcm2708_dma_alloc_chan_resources(struct dma_chan *chan) -+static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan) - { -- struct bcm2708_chan *c = to_bcm2708_dma_chan(chan); -+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); -+ int ret; -+ -+ dev_dbg(c->vc.chan.device->dev, -+ "Allocating DMA channel %d\n", c->ch); -+ -+ ret = request_irq(c->irq_number, -+ bcm2835_dma_callback, 0, "DMA IRQ", c); - -- return request_irq(c->irq_number, -- bcm2708_dma_callback, 0, "DMA IRQ", c); -+ return ret; - } - --static void bcm2708_dma_free_chan_resources(struct dma_chan *chan) -+static void bcm2835_dma_free_chan_resources(struct dma_chan *chan) - { -- struct bcm2708_chan *c = to_bcm2708_dma_chan(chan); -+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); - - vchan_free_chan_resources(&c->vc); - free_irq(c->irq_number, c); -@@ -173,18 +300,18 @@ static void bcm2708_dma_free_chan_resources(struct dma_chan *chan) - dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch); - } - --static size_t bcm2708_dma_desc_size(struct bcm2708_desc *d) -+static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d) - { - return d->size; - } - --static size_t bcm2708_dma_desc_size_pos(struct bcm2708_desc *d, dma_addr_t addr) -+static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr) - { -- unsigned i; -+ unsigned int i; - size_t size; - - for (size = i = 0; i < d->frames; i++) { -- struct bcm2708_dma_cb *control_block = -+ struct bcm2835_dma_cb *control_block = - &d->control_block_base[i]; - size_t this_size = control_block->length; - dma_addr_t dma; -@@ -203,13 +330,15 @@ static size_t bcm2708_dma_desc_size_pos(struct bcm2708_desc *d, dma_addr_t addr) - return size; - } - --static enum dma_status bcm2708_dma_tx_status(struct dma_chan *chan, -+static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan, - dma_cookie_t cookie, struct dma_tx_state *txstate) - { -- struct bcm2708_chan *c = to_bcm2708_dma_chan(chan); -+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); -+ struct bcm2835_desc *d; - struct virt_dma_desc *vd; - enum dma_status ret; - unsigned long flags; -+ dma_addr_t pos; - - ret = dma_cookie_status(chan, cookie, txstate); - if (ret == DMA_COMPLETE || !txstate) -@@ -219,19 +348,18 @@ static enum dma_status bcm2708_dma_tx_status(struct dma_chan *chan, - vd = vchan_find_desc(&c->vc, cookie); - if (vd) { - txstate->residue = -- bcm2708_dma_desc_size(to_bcm2708_dma_desc(&vd->tx)); -+ bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx)); - } else if (c->desc && c->desc->vd.tx.cookie == cookie) { -- struct bcm2708_desc *d = c->desc; -- dma_addr_t pos; -+ d = c->desc; - - if (d->dir == DMA_MEM_TO_DEV) -- pos = readl(c->chan_base + BCM2708_DMA_SOURCE_AD); -+ pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD); - else if (d->dir == DMA_DEV_TO_MEM) -- pos = readl(c->chan_base + BCM2708_DMA_DEST_AD); -+ pos = readl(c->chan_base + BCM2835_DMA_DEST_AD); - else - pos = 0; - -- txstate->residue = bcm2708_dma_desc_size_pos(d, pos); -+ txstate->residue = bcm2835_dma_desc_size_pos(d, pos); - } else { - txstate->residue = 0; - } -@@ -241,50 +369,50 @@ static enum dma_status bcm2708_dma_tx_status(struct dma_chan *chan, - return ret; - } - --static void bcm2708_dma_issue_pending(struct dma_chan *chan) -+static void bcm2835_dma_issue_pending(struct dma_chan *chan) - { -- struct bcm2708_chan *c = to_bcm2708_dma_chan(chan); -+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); - unsigned long flags; - -- c->cyclic = true; /* Nothing else is implemented */ -- - spin_lock_irqsave(&c->vc.lock, flags); - if (vchan_issue_pending(&c->vc) && !c->desc) -- bcm2708_dma_start_desc(c); -+ bcm2835_dma_start_desc(c); - - spin_unlock_irqrestore(&c->vc.lock, flags); - } - --static struct dma_async_tx_descriptor *bcm2708_dma_prep_dma_cyclic( -+static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( - struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, - size_t period_len, enum dma_transfer_direction direction, - unsigned long flags, void *context) - { -- struct bcm2708_chan *c = to_bcm2708_dma_chan(chan); -+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); - enum dma_slave_buswidth dev_width; -- struct bcm2708_desc *d; -+ struct bcm2835_desc *d; - dma_addr_t dev_addr; -- unsigned es, sync_type; -- unsigned frame; -+ unsigned int es, sync_type; -+ unsigned int frame; - - /* Grab configuration */ -+ if (!is_slave_direction(direction)) { -+ dev_err(chan->device->dev, "%s: bad direction?\n", __func__); -+ return NULL; -+ } -+ - if (direction == DMA_DEV_TO_MEM) { - dev_addr = c->cfg.src_addr; - dev_width = c->cfg.src_addr_width; -- sync_type = BCM2708_DMA_S_DREQ; -- } else if (direction == DMA_MEM_TO_DEV) { -+ sync_type = BCM2835_DMA_S_DREQ; -+ } else { - dev_addr = c->cfg.dst_addr; - dev_width = c->cfg.dst_addr_width; -- sync_type = BCM2708_DMA_D_DREQ; -- } else { -- dev_err(chan->device->dev, "%s: bad direction?\n", __func__); -- return NULL; -+ sync_type = BCM2835_DMA_D_DREQ; - } - - /* Bus width translates to the element size (ES) */ - switch (dev_width) { - case DMA_SLAVE_BUSWIDTH_4_BYTES: -- es = BCM2708_DMA_DATA_TYPE_S32; -+ es = BCM2835_DMA_DATA_TYPE_S32; - break; - default: - return NULL; -@@ -299,7 +427,7 @@ static struct dma_async_tx_descriptor *bcm2708_dma_prep_dma_cyclic( - d->frames = buf_len / period_len; - - /* Allocate memory for control blocks */ -- d->control_block_size = d->frames * sizeof(struct bcm2708_dma_cb); -+ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb); - d->control_block_base = dma_zalloc_coherent(chan->device->dev, - d->control_block_size, &d->control_block_base_phys, - GFP_NOWAIT); -@@ -314,22 +442,22 @@ static struct dma_async_tx_descriptor *bcm2708_dma_prep_dma_cyclic( - * for each frame and link them together. - */ - for (frame = 0; frame < d->frames; frame++) { -- struct bcm2708_dma_cb *control_block = -+ struct bcm2835_dma_cb *control_block = - &d->control_block_base[frame]; - - /* Setup adresses */ - if (d->dir == DMA_DEV_TO_MEM) { -- control_block->info = BCM2708_DMA_D_INC; -+ control_block->info = BCM2835_DMA_D_INC; - control_block->src = dev_addr; - control_block->dst = buf_addr + frame * period_len; - } else { -- control_block->info = BCM2708_DMA_S_INC; -+ control_block->info = BCM2835_DMA_S_INC; - control_block->src = buf_addr + frame * period_len; - control_block->dst = dev_addr; - } - - /* Enable interrupt */ -- control_block->info |= BCM2708_DMA_INT_EN; -+ control_block->info |= BCM2835_DMA_INT_EN; - - /* Setup synchronization */ - if (sync_type != 0) -@@ -338,7 +466,7 @@ static struct dma_async_tx_descriptor *bcm2708_dma_prep_dma_cyclic( - /* Setup DREQ channel */ - if (c->cfg.slave_id != 0) - control_block->info |= -- BCM2708_DMA_PER_MAP(c->cfg.slave_id); -+ BCM2835_DMA_PER_MAP(c->cfg.slave_id); - - /* Length of a frame */ - control_block->length = period_len; -@@ -346,18 +474,166 @@ static struct dma_async_tx_descriptor *bcm2708_dma_prep_dma_cyclic( - - /* - * Next block is the next frame. -- * This DMA engine driver currently only supports cyclic DMA. -+ * This function is called on cyclic DMA transfers. - * Therefore, wrap around at number of frames. - */ - control_block->next = d->control_block_base_phys + -- sizeof(struct bcm2708_dma_cb) -+ sizeof(struct bcm2835_dma_cb) - * ((frame + 1) % d->frames); - } - -+ c->cyclic = true; -+ - return vchan_tx_prep(&c->vc, &d->vd, flags); - } - --static int bcm2708_dma_slave_config(struct bcm2708_chan *c, -+ -+static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg( -+ struct dma_chan *chan, struct scatterlist *sgl, -+ unsigned int sg_len, enum dma_transfer_direction direction, -+ unsigned long flags, void *context) -+{ -+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); -+ enum dma_slave_buswidth dev_width; -+ struct bcm2835_desc *d; -+ dma_addr_t dev_addr; -+ struct scatterlist *sgent; -+ unsigned int es, sync_type; -+ unsigned int i, j, splitct, max_size; -+ -+ if (!is_slave_direction(direction)) { -+ dev_err(chan->device->dev, "%s: bad direction?\n", __func__); -+ return NULL; -+ } -+ -+ if (direction == DMA_DEV_TO_MEM) { -+ dev_addr = c->cfg.src_addr; -+ dev_width = c->cfg.src_addr_width; -+ sync_type = BCM2835_DMA_S_DREQ; -+ } else { -+ dev_addr = c->cfg.dst_addr; -+ dev_width = c->cfg.dst_addr_width; -+ sync_type = BCM2835_DMA_D_DREQ; -+ } -+ -+ /* Bus width translates to the element size (ES) */ -+ switch (dev_width) { -+ case DMA_SLAVE_BUSWIDTH_4_BYTES: -+ es = BCM2835_DMA_DATA_TYPE_S32; -+ break; -+ default: -+ return NULL; -+ } -+ -+ /* Now allocate and setup the descriptor. */ -+ d = kzalloc(sizeof(*d), GFP_NOWAIT); -+ if (!d) -+ return NULL; -+ -+ d->dir = direction; -+ -+ if (c->ch >= 8) /* we have a LITE channel */ -+ max_size = MAX_LITE_TRANSFER; -+ else -+ max_size = MAX_NORMAL_TRANSFER; -+ -+ /* We store the length of the SG list in d->frames -+ taking care to account for splitting up transfers -+ too large for a LITE channel */ -+ -+ d->frames = 0; -+ for_each_sg(sgl, sgent, sg_len, i) { -+ uint32_t len = sg_dma_len(sgent); -+ d->frames += 1 + len / max_size; -+ } -+ -+ /* Allocate memory for control blocks */ -+ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb); -+ d->control_block_base = dma_zalloc_coherent(chan->device->dev, -+ d->control_block_size, &d->control_block_base_phys, -+ GFP_NOWAIT); -+ -+ if (!d->control_block_base) { -+ kfree(d); -+ return NULL; -+ } -+ -+ /* -+ * Iterate over all SG entries, create a control block -+ * for each frame and link them together. -+ */ -+ -+ /* we count the number of times an SG entry had to be splitct -+ as a result of using a LITE channel */ -+ splitct = 0; -+ -+ for_each_sg(sgl, sgent, sg_len, i) { -+ dma_addr_t addr = sg_dma_address(sgent); -+ uint32_t len = sg_dma_len(sgent); -+ -+ for (j = 0; j < len; j += max_size) { -+ struct bcm2835_dma_cb *control_block = -+ &d->control_block_base[i+splitct]; -+ -+ /* Setup adresses */ -+ if (d->dir == DMA_DEV_TO_MEM) { -+ control_block->info = BCM2835_DMA_D_INC | -+ BCM2835_DMA_D_WIDTH | BCM2835_DMA_S_DREQ; -+ control_block->src = dev_addr; -+ control_block->dst = addr + (dma_addr_t)j; -+ } else { -+ control_block->info = BCM2835_DMA_S_INC | -+ BCM2835_DMA_S_WIDTH | BCM2835_DMA_D_DREQ; -+ control_block->src = addr + (dma_addr_t)j; -+ control_block->dst = dev_addr; -+ } -+ -+ /* Common part */ -+ control_block->info |= BCM2835_DMA_WAITS(SDHCI_BCM_DMA_WAITS); -+ control_block->info |= BCM2835_DMA_WAIT_RESP; -+ -+ /* Enable */ -+ if (i == sg_len-1 && len-j <= max_size) -+ control_block->info |= BCM2835_DMA_INT_EN; -+ -+ /* Setup synchronization */ -+ if (sync_type != 0) -+ control_block->info |= sync_type; -+ -+ /* Setup DREQ channel */ -+ c->dreq = c->cfg.slave_id; /* DREQ loaded from config */ -+ -+ if (c->dreq != 0) -+ control_block->info |= -+ BCM2835_DMA_PER_MAP(c->dreq); -+ -+ /* Length of a frame */ -+ control_block->length = min(len-j, max_size); -+ d->size += control_block->length; -+ -+ /* -+ * Next block is the next frame. -+ */ -+ if (i < sg_len-1 || len-j > max_size) { -+ /* next block is the next frame. */ -+ control_block->next = d->control_block_base_phys + -+ sizeof(struct bcm2835_dma_cb) * (i + splitct + 1); -+ } else { -+ /* next block is empty. */ -+ control_block->next = 0; -+ } -+ -+ if (len-j > max_size) -+ splitct++; -+ } -+ } -+ -+ c->cyclic = false; -+ -+ return vchan_tx_prep(&c->vc, &d->vd, flags); -+} -+ -+static int bcm2835_dma_slave_config(struct bcm2835_chan *c, - struct dma_slave_config *cfg) - { - if ((cfg->direction == DMA_DEV_TO_MEM && -@@ -373,9 +649,9 @@ static int bcm2708_dma_slave_config(struct bcm2708_chan *c, - return 0; - } - --static int bcm2708_dma_terminate_all(struct bcm2708_chan *c) -+static int bcm2835_dma_terminate_all(struct bcm2835_chan *c) - { -- struct bcm2708_dmadev *d = to_bcm2708_dma_dev(c->vc.chan.device); -+ struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device); - unsigned long flags; - int timeout = 10000; - LIST_HEAD(head); -@@ -394,19 +670,18 @@ static int bcm2708_dma_terminate_all(struct bcm2708_chan *c) - */ - if (c->desc) { - c->desc = NULL; -- bcm_dma_abort(c->chan_base); -+ bcm2835_dma_abort(c->chan_base); - - /* Wait for stopping */ -- while (timeout > 0) { -- timeout--; -- if (!(readl(c->chan_base + BCM2708_DMA_CS) & -- BCM2708_DMA_ACTIVE)) -+ while (--timeout) { -+ if (!(readl(c->chan_base + BCM2835_DMA_CS) & -+ BCM2835_DMA_ACTIVE)) - break; - - cpu_relax(); - } - -- if (timeout <= 0) -+ if (!timeout) - dev_err(d->ddev.dev, "DMA transfer could not be terminated\n"); - } - -@@ -417,34 +692,57 @@ static int bcm2708_dma_terminate_all(struct bcm2708_chan *c) - return 0; - } - --static int bcm2708_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, -+static int bcm2835_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, - unsigned long arg) - { -- struct bcm2708_chan *c = to_bcm2708_dma_chan(chan); -+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); - - switch (cmd) { - case DMA_SLAVE_CONFIG: -- return bcm2708_dma_slave_config(c, -+ return bcm2835_dma_slave_config(c, - (struct dma_slave_config *)arg); - - case DMA_TERMINATE_ALL: -- return bcm2708_dma_terminate_all(c); -+ return bcm2835_dma_terminate_all(c); - - default: - return -ENXIO; - } - } - --static int bcm2708_dma_chan_init(struct bcm2708_dmadev *d, void __iomem* chan_base, -- int chan_id, int irq) -+#ifdef CONFIG_OF -+static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq) - { -- struct bcm2708_chan *c; -+ struct bcm2835_chan *c; - - c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL); - if (!c) - return -ENOMEM; - -- c->vc.desc_free = bcm2708_dma_desc_free; -+ c->vc.desc_free = bcm2835_dma_desc_free; -+ vchan_init(&c->vc, &d->ddev); -+ INIT_LIST_HEAD(&c->node); -+ -+ d->ddev.chancnt++; -+ -+ c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id); -+ c->ch = chan_id; -+ c->irq_number = irq; -+ -+ return 0; -+} -+#endif -+ -+static int bcm2708_dma_chan_init(struct bcm2835_dmadev *d, -+ void __iomem *chan_base, int chan_id, int irq) -+{ -+ struct bcm2835_chan *c; -+ -+ c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL); -+ if (!c) -+ return -ENOMEM; -+ -+ c->vc.desc_free = bcm2835_dma_desc_free; - vchan_init(&c->vc, &d->ddev); - INIT_LIST_HEAD(&c->node); - -@@ -457,30 +755,81 @@ static int bcm2708_dma_chan_init(struct bcm2708_dmadev *d, void __iomem* chan_ba - return 0; - } - --static void bcm2708_dma_free(struct bcm2708_dmadev *od) -+ -+static void bcm2835_dma_free(struct bcm2835_dmadev *od) - { -- while (!list_empty(&od->ddev.channels)) { -- struct bcm2708_chan *c = list_first_entry(&od->ddev.channels, -- struct bcm2708_chan, vc.chan.device_node); -+ struct bcm2835_chan *c, *next; - -+ list_for_each_entry_safe(c, next, &od->ddev.channels, -+ vc.chan.device_node) { - list_del(&c->vc.chan.device_node); - tasklet_kill(&c->vc.task); - } - } - --static int bcm2708_dma_probe(struct platform_device *pdev) -+static const struct of_device_id bcm2835_dma_of_match[] = { -+ { .compatible = "brcm,bcm2835-dma", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match); -+ -+#ifdef CONFIG_OF -+static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec, -+ struct of_dma *ofdma) -+{ -+ struct bcm2835_dmadev *d = ofdma->of_dma_data; -+ struct dma_chan *chan; -+ -+ chan = dma_get_any_slave_channel(&d->ddev); -+ if (!chan) -+ return NULL; -+ -+ /* Set DREQ from param */ -+ to_bcm2835_dma_chan(chan)->dreq = spec->args[0]; -+ -+ return chan; -+} -+#endif -+ -+static int bcm2835_dma_device_slave_caps(struct dma_chan *dchan, -+ struct dma_slave_caps *caps) - { -- struct bcm2708_dmadev *od; -- int rc, i; -+ caps->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); -+ caps->dstn_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); -+ caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); -+ caps->cmd_pause = false; -+ caps->cmd_terminate = true; -+ -+ return 0; -+} -+ -+static int bcm2835_dma_probe(struct platform_device *pdev) -+{ -+ struct bcm2835_dmadev *od; -+#ifdef CONFIG_OF -+ struct resource *res; -+ void __iomem *base; -+ uint32_t chans_available; -+#endif -+ int rc; -+ int i; -+ int irq; -+ - - if (!pdev->dev.dma_mask) - pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; - -+ /* If CONFIG_OF is selected, device tree is used */ -+ /* hence the difference between probing */ -+ -+#ifndef CONFIG_OF -+ - rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); - if (rc) - return rc; - dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); - -+ - od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); - if (!od) - return -ENOMEM; -@@ -488,25 +837,29 @@ static int bcm2708_dma_probe(struct platform_device *pdev) - pdev->dev.dma_parms = &od->dma_parms; - dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF); - -+ - dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); -+ dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask); - dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); -- od->ddev.device_alloc_chan_resources = bcm2708_dma_alloc_chan_resources; -- od->ddev.device_free_chan_resources = bcm2708_dma_free_chan_resources; -- od->ddev.device_tx_status = bcm2708_dma_tx_status; -- od->ddev.device_issue_pending = bcm2708_dma_issue_pending; -- od->ddev.device_prep_dma_cyclic = bcm2708_dma_prep_dma_cyclic; -- od->ddev.device_control = bcm2708_dma_control; -+ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources; -+ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources; -+ od->ddev.device_tx_status = bcm2835_dma_tx_status; -+ od->ddev.device_issue_pending = bcm2835_dma_issue_pending; -+ od->ddev.device_slave_caps = bcm2835_dma_device_slave_caps; -+ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic; -+ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg; -+ od->ddev.device_control = bcm2835_dma_control; - od->ddev.dev = &pdev->dev; - INIT_LIST_HEAD(&od->ddev.channels); - spin_lock_init(&od->lock); - - platform_set_drvdata(pdev, od); - -- for (i = 0; i < 16; i++) { -- void __iomem* chan_base; -- int chan_id, irq; -+ for (i = 0; i < 5; i++) { -+ void __iomem *chan_base; -+ int chan_id; - -- chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST, -+ chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_LITE, - &chan_base, - &irq); - -@@ -514,38 +867,121 @@ static int bcm2708_dma_probe(struct platform_device *pdev) - break; - - rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq); -- if (rc) { -- bcm2708_dma_free(od); -- return rc; -+ if (rc) -+ goto err_no_dma; -+ } -+#else -+ rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); -+ if (rc) -+ return rc; -+ -+ -+ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); -+ if (!od) -+ return -ENOMEM; -+ -+ pdev->dev.dma_parms = &od->dma_parms; -+ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF); -+ -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ od->base = base; -+ -+ -+ dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); -+ dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask); -+ dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); -+ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources; -+ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources; -+ od->ddev.device_tx_status = bcm2835_dma_tx_status; -+ od->ddev.device_issue_pending = bcm2835_dma_issue_pending; -+ od->ddev.device_slave_caps = bcm2835_dma_device_slave_caps; -+ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic; -+ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg; -+ od->ddev.device_control = bcm2835_dma_control; -+ od->ddev.dev = &pdev->dev; -+ INIT_LIST_HEAD(&od->ddev.channels); -+ spin_lock_init(&od->lock); -+ -+ platform_set_drvdata(pdev, od); -+ -+ -+ /* Request DMA channel mask from device tree */ -+ if (of_property_read_u32(pdev->dev.of_node, -+ "brcm,dma-channel-mask", -+ &chans_available)) { -+ dev_err(&pdev->dev, "Failed to get channel mask\n"); -+ rc = -EINVAL; -+ goto err_no_dma; -+ } -+ -+ -+ /* -+ * Do not use the FIQ and BULK channels, -+ * because they are used by the GPU. -+ */ -+ chans_available &= ~(BCM2835_DMA_FIQ_MASK | BCM2835_DMA_BULK_MASK); -+ -+ -+ for (i = 0; i < pdev->num_resources; i++) { -+ irq = platform_get_irq(pdev, i); -+ if (irq < 0) -+ break; -+ -+ if (chans_available & (1 << i)) { -+ rc = bcm2835_dma_chan_init(od, i, irq); -+ if (rc) -+ goto err_no_dma; - } - } - -+ dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i); -+ -+ /* Device-tree DMA controller registration */ -+ rc = of_dma_controller_register(pdev->dev.of_node, -+ bcm2835_dma_xlate, od); -+ if (rc) { -+ dev_err(&pdev->dev, "Failed to register DMA controller\n"); -+ goto err_no_dma; -+ } -+#endif -+ - rc = dma_async_device_register(&od->ddev); - if (rc) { - dev_err(&pdev->dev, - "Failed to register slave DMA engine device: %d\n", rc); -- bcm2708_dma_free(od); -- return rc; -+ goto err_no_dma; - } - -- dev_dbg(&pdev->dev, "Load BCM2708 DMA engine driver\n"); -+ dev_info(&pdev->dev, "Load BCM2835 DMA engine driver\n"); - -+ return 0; -+ -+err_no_dma: -+ bcm2835_dma_free(od); - return rc; - } - --static int bcm2708_dma_remove(struct platform_device *pdev) -+static int bcm2835_dma_remove(struct platform_device *pdev) - { -- struct bcm2708_dmadev *od = platform_get_drvdata(pdev); -+ struct bcm2835_dmadev *od = platform_get_drvdata(pdev); - - dma_async_device_unregister(&od->ddev); -- bcm2708_dma_free(od); -+ bcm2835_dma_free(od); - - return 0; - } - --static struct platform_driver bcm2708_dma_driver = { -- .probe = bcm2708_dma_probe, -- .remove = bcm2708_dma_remove, -+#ifndef CONFIG_OF -+ -+ -+static struct platform_driver bcm2835_dma_driver = { -+ .probe = bcm2835_dma_probe, -+ .remove = bcm2835_dma_remove, - .driver = { - .name = "bcm2708-dmaengine", - .owner = THIS_MODULE, -@@ -554,35 +990,52 @@ static struct platform_driver bcm2708_dma_driver = { - - static struct platform_device *pdev; - --static const struct platform_device_info bcm2708_dma_dev_info = { -+static const struct platform_device_info bcm2835_dma_dev_info = { - .name = "bcm2708-dmaengine", - .id = -1, - }; - --static int bcm2708_dma_init(void) -+static int bcm2835_dma_init(void) - { -- int rc = platform_driver_register(&bcm2708_dma_driver); -+ int rc = platform_driver_register(&bcm2835_dma_driver); - - if (rc == 0) { -- pdev = platform_device_register_full(&bcm2708_dma_dev_info); -+ pdev = platform_device_register_full(&bcm2835_dma_dev_info); - if (IS_ERR(pdev)) { -- platform_driver_unregister(&bcm2708_dma_driver); -+ platform_driver_unregister(&bcm2835_dma_driver); - rc = PTR_ERR(pdev); - } - } - - return rc; - } --subsys_initcall(bcm2708_dma_init); -+module_init(bcm2835_dma_init); /* preferable to subsys_initcall */ - --static void __exit bcm2708_dma_exit(void) -+static void __exit bcm2835_dma_exit(void) - { - platform_device_unregister(pdev); -- platform_driver_unregister(&bcm2708_dma_driver); -+ platform_driver_unregister(&bcm2835_dma_driver); - } --module_exit(bcm2708_dma_exit); -+module_exit(bcm2835_dma_exit); -+ -+#else -+ -+static struct platform_driver bcm2835_dma_driver = { -+ .probe = bcm2835_dma_probe, -+ .remove = bcm2835_dma_remove, -+ .driver = { -+ .name = "bcm2835-dma", -+ .owner = THIS_MODULE, -+ .of_match_table = of_match_ptr(bcm2835_dma_of_match), -+ }, -+}; -+ -+module_platform_driver(bcm2835_dma_driver); -+ -+#endif - --MODULE_ALIAS("platform:bcm2708-dma"); --MODULE_DESCRIPTION("BCM2708 DMA engine driver"); -+MODULE_ALIAS("platform:bcm2835-dma"); -+MODULE_DESCRIPTION("BCM2835 DMA engine driver"); - MODULE_AUTHOR("Florian Meier "); -+MODULE_AUTHOR("Gellert Weisz "); - MODULE_LICENSE("GPL v2"); -diff --git a/drivers/mmc/host/sdhci-bcm2708.c b/drivers/mmc/host/sdhci-bcm2708.c -index 6e777f4..15445215 100644 ---- a/drivers/mmc/host/sdhci-bcm2708.c -+++ b/drivers/mmc/host/sdhci-bcm2708.c -@@ -69,6 +69,9 @@ - #define DMA_SDHCI_BASE 0x7e300000 /* EMMC register block on Videocore */ - #define DMA_SDHCI_BUFFER (DMA_SDHCI_BASE + SDHCI_BUFFER) - -+#define MAX_LITE_TRANSFER 32768 -+#define MAX_NORMAL_TRANSFER 1073741824 -+ - #define BCM2708_SDHCI_SLEEP_TIMEOUT 1000 /* msecs */ - - /* Mhz clock that the EMMC core is running at. Should match the platform clockman settings */ -@@ -444,29 +447,39 @@ static void schci_bcm2708_cb_read(struct sdhci_bcm2708_priv *host, - dma_addr_t dma_addr, unsigned len, - int /*bool*/ is_last) - { -- struct bcm2708_dma_cb *cb = &host->cb_base[ix]; -- unsigned char dmawaits = host->dma_waits; -- -- cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) | -- BCM2708_DMA_WAITS(dmawaits) | -- BCM2708_DMA_S_DREQ | -- BCM2708_DMA_D_WIDTH | -- BCM2708_DMA_D_INC; -- cb->src = DMA_SDHCI_BUFFER; /* DATA register DMA address */ -- cb->dst = dma_addr; -- cb->length = len; -- cb->stride = 0; -- -- if (is_last) { -- cb->info |= BCM2708_DMA_INT_EN | -- BCM2708_DMA_WAIT_RESP; -- cb->next = 0; -- } else -- cb->next = host->cb_handle + -- (ix+1)*sizeof(struct bcm2708_dma_cb); -+ struct bcm2708_dma_cb *cb; -+ unsigned char dmawaits = host->dma_waits; -+ unsigned i, max_size; - -- cb->pad[0] = 0; -- cb->pad[1] = 0; -+ if (host->dma_chan >= 8) /* we have a LITE channel */ -+ max_size = MAX_LITE_TRANSFER; -+ else -+ max_size = MAX_NORMAL_TRANSFER; -+ -+ for (i = 0; i < len; i += max_size) { -+ cb = &host->cb_base[ix+i/max_size]; -+ -+ cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) | -+ BCM2708_DMA_WAITS(dmawaits) | -+ BCM2708_DMA_WAIT_RESP | -+ BCM2708_DMA_S_DREQ | -+ BCM2708_DMA_D_WIDTH | -+ BCM2708_DMA_D_INC; -+ cb->src = DMA_SDHCI_BUFFER; /* DATA register DMA address */ -+ cb->dst = dma_addr + (dma_addr_t)i; -+ cb->length = min(len-i, max_size); -+ cb->stride = 0; -+ -+ if (is_last && len-i <= max_size) { -+ cb->info |= BCM2708_DMA_INT_EN; -+ cb->next = 0; -+ } else -+ cb->next = host->cb_handle + -+ (ix+1 + i/max_size)*sizeof(struct bcm2708_dma_cb); -+ -+ cb->pad[0] = 0; -+ cb->pad[1] = 0; -+ } - } - - static void schci_bcm2708_cb_write(struct sdhci_bcm2708_priv *host, -@@ -475,30 +488,42 @@ static void schci_bcm2708_cb_write(struct sdhci_bcm2708_priv *host, - int /*bool*/ is_last) - { - struct bcm2708_dma_cb *cb = &host->cb_base[ix]; -- unsigned char dmawaits = host->dma_waits; -+ unsigned char dmawaits = host->dma_waits; -+ unsigned i, max_size; -+ -+ if (host->dma_chan >= 8) /* we have a LITE channel */ -+ max_size = MAX_LITE_TRANSFER; -+ else -+ max_size = MAX_NORMAL_TRANSFER; - - /* We can make arbitrarily large writes as long as we specify DREQ to -- pace the delivery of bytes to the Arasan hardware */ -- cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) | -- BCM2708_DMA_WAITS(dmawaits) | -- BCM2708_DMA_D_DREQ | -- BCM2708_DMA_S_WIDTH | -- BCM2708_DMA_S_INC; -- cb->src = dma_addr; -- cb->dst = DMA_SDHCI_BUFFER; /* DATA register DMA address */ -- cb->length = len; -- cb->stride = 0; -- -- if (is_last) { -- cb->info |= BCM2708_DMA_INT_EN | -- BCM2708_DMA_WAIT_RESP; -- cb->next = 0; -- } else -- cb->next = host->cb_handle + -- (ix+1)*sizeof(struct bcm2708_dma_cb); -+ pace the delivery of bytes to the Arasan hardware. However we need -+ to take care when using LITE channels */ -+ -+ for (i = 0; i < len; i += max_size) { -+ cb = &host->cb_base[ix+i/max_size]; -+ -+ cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) | -+ BCM2708_DMA_WAITS(dmawaits) | -+ BCM2708_DMA_WAIT_RESP | -+ BCM2708_DMA_D_DREQ | -+ BCM2708_DMA_S_WIDTH | -+ BCM2708_DMA_S_INC; -+ cb->src = dma_addr + (dma_addr_t)i; -+ cb->dst = DMA_SDHCI_BUFFER; /* DATA register DMA address */ -+ cb->length = min(len-i, max_size); -+ cb->stride = 0; -+ -+ if (is_last && len-i <= max_size) { -+ cb->info |= BCM2708_DMA_INT_EN; -+ cb->next = 0; -+ } else -+ cb->next = host->cb_handle + -+ (ix+1 + i/max_size)*sizeof(struct bcm2708_dma_cb); - -- cb->pad[0] = 0; -- cb->pad[1] = 0; -+ cb->pad[0] = 0; -+ cb->pad[1] = 0; -+ } - } - - -@@ -1390,5 +1415,3 @@ MODULE_PARM_DESC(emmc_clock_freq, "Specify the speed of emmc clock"); - MODULE_PARM_DESC(sync_after_dma, "Block in driver until dma complete"); - MODULE_PARM_DESC(missing_status, "Use the missing status quirk"); - MODULE_PARM_DESC(extra_messages, "Enable more sdcard warning messages"); -- -- - -From 9bbcdf6daf5c3c7d857ff9969431b8b41089c194 Mon Sep 17 00:00:00 2001 +From 6c1e4792016e0bb0d1712fb120154c32eabb17b4 Mon Sep 17 00:00:00 2001 From: gellert Date: Fri, 15 Aug 2014 16:35:06 +0100 -Subject: [PATCH 72/94] MMC: added alternative MMC driver +Subject: [PATCH 68/82] MMC: added alternative MMC driver --- - arch/arm/mach-bcm2708/bcm2708.c | 37 +- - drivers/mmc/host/Kconfig | 29 + - drivers/mmc/host/Makefile | 1 + - drivers/mmc/host/bcm2835-mmc.c | 1546 +++++++++++++++++++++++++++++++++++++++ - 4 files changed, 1612 insertions(+), 1 deletion(-) + arch/arm/configs/bcmrpi_defconfig | 2 + + arch/arm/mach-bcm2708/bcm2708.c | 31 + + drivers/mmc/host/Kconfig | 40 +- + drivers/mmc/host/Makefile | 1 + + drivers/mmc/host/bcm2835-mmc.c | 1547 +++++++++++++++++++++++++++++++++++++ + 5 files changed, 1610 insertions(+), 11 deletions(-) create mode 100644 drivers/mmc/host/bcm2835-mmc.c +diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig +index db259ae..f88d2d6 100644 +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -887,6 +887,8 @@ CONFIG_MMC=y + CONFIG_MMC_BLOCK_MINORS=32 + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_PLTFM=y ++CONFIG_MMC_BCM2835=y ++CONFIG_MMC_BCM2835_DMA=y + CONFIG_MMC_SPI=m + CONFIG_LEDS_GPIO=m + CONFIG_LEDS_TRIGGER_TIMER=y diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index a19f54d..a37ad15 100644 +index 902f8c7..c9e3038 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -92,6 +92,7 @@ static unsigned disk_led_active_low = 1; - static unsigned reboot_part = 0; - static unsigned w1_gpio_pin = W1_GPIO; - static unsigned w1_gpio_pullup = W1_PULLUP; -+static unsigned bcm2835_mmc = 0; - - static void __init bcm2708_init_led(void); - -@@ -442,6 +443,34 @@ struct platform_device bcm2708_emmc_device = { +@@ -414,6 +414,34 @@ static struct platform_device bcm2708_systemtimer_device = { + }, }; - #endif /* CONFIG_MMC_SDHCI_BCM2708 */ +#ifdef CONFIG_MMC_BCM2835 /* Arasan emmc SD (new) */ +static struct resource bcm2835_emmc_resources[] = { @@ -120151,32 +115971,41 @@ index a19f54d..a37ad15 100644 static struct resource bcm2708_powerman_resources[] = { [0] = { .start = PM_BASE, -@@ -823,7 +852,12 @@ void __init bcm2708_init(void) +@@ -794,6 +822,9 @@ void __init bcm2708_init(void) + bcm_register_device(&bcm2708_uart1_device); bcm_register_device(&bcm2708_powerman_device); - #ifdef CONFIG_MMC_SDHCI_BCM2708 -- bcm_register_device(&bcm2708_emmc_device); -+ if (!bcm2835_mmc) -+ bcm_register_device(&bcm2708_emmc_device); -+#endif +#ifdef CONFIG_MMC_BCM2835 -+ if (bcm2835_mmc) -+ bcm_register_device(&bcm2835_emmc_device); - #endif ++ bcm_register_device(&bcm2835_emmc_device); ++#endif bcm2708_init_led(); for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) -@@ -1053,3 +1087,4 @@ module_param(disk_led_active_low, uint, 0644); - module_param(reboot_part, uint, 0644); - module_param(w1_gpio_pin, uint, 0644); - module_param(w1_gpio_pullup, uint, 0644); -+module_param(bcm2835_mmc, uint, 0644); + bcm_register_device(&bcm2708_alsa_devices[i]); diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig -index b152bb3..67f409a 100644 +index 4511358..edf18c6 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig -@@ -311,6 +311,35 @@ config MMC_MOXART - be found on some embedded hardware such as UC-7112-LX. - If you have a controller with this interface, say Y here. +@@ -270,17 +270,6 @@ config MMC_SDHCI_BCM_KONA + + If you have a controller with this interface, say Y or M here. + +-config MMC_SDHCI_BCM2835 +- tristate "SDHCI platform support for the BCM2835 SD/MMC Controller" +- depends on ARCH_BCM2835 +- depends on MMC_SDHCI_PLTFM +- select MMC_SDHCI_IO_ACCESSORS +- help +- This selects the BCM2835 SD/MMC controller. If you have a BCM2835 +- platform with SD or MMC devices, say Y or M here. +- +- If unsure, say N. +- + config MMC_MOXART + tristate "MOXART SD/MMC Host Controller support" + depends on ARCH_MOXART && MMC +@@ -302,6 +291,35 @@ config MMC_SDHCI_ST + If you have a controller with this interface, say Y or M here. + If unsure, say N. +config MMC_BCM2835 + tristate "MMC support on BCM2835" @@ -120211,23 +116040,23 @@ index b152bb3..67f409a 100644 tristate "TI OMAP Multimedia Card Interface support" depends on ARCH_OMAP diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile -index 635064e..402ded1 100644 +index f211eed..5baa507 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o +@@ -16,6 +16,7 @@ obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o + obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o - obj-$(CONFIG_MMC_SDHCI_BCM2708) += sdhci-bcm2708.o +obj-$(CONFIG_MMC_BCM2835) += bcm2835-mmc.o obj-$(CONFIG_MMC_WBSD) += wbsd.o obj-$(CONFIG_MMC_AU1X) += au1xmmc.o obj-$(CONFIG_MMC_OMAP) += omap.o diff --git a/drivers/mmc/host/bcm2835-mmc.c b/drivers/mmc/host/bcm2835-mmc.c new file mode 100644 -index 0000000..c50ff43 +index 0000000..123ff94 --- /dev/null +++ b/drivers/mmc/host/bcm2835-mmc.c -@@ -0,0 +1,1546 @@ +@@ -0,0 +1,1547 @@ +/* + * BCM2835 MMC host driver. + * @@ -120252,6 +116081,26 @@ index 0000000..c50ff43 + * along with this program. If not, see . + */ + ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "sdhci.h" ++ ++ +#ifndef CONFIG_OF + #define BCM2835_CLOCK_FREQ 250000000 +#endif @@ -120284,25 +116133,6 @@ index 0000000..c50ff43 +/* FIXME: Needs IOMMU support */ +#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE) + -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "sdhci.h" -+ + +struct bcm2835_host { + spinlock_t lock; @@ -121775,46 +117605,10 @@ index 0000000..c50ff43 +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Gellert Weisz"); -From 89e297b793f62c7bf6c725419b37928d00a6c900 Mon Sep 17 00:00:00 2001 -From: gellert -Date: Fri, 15 Aug 2014 16:35:59 +0100 -Subject: [PATCH 73/94] turn on new MMC driver - ---- - arch/arm/configs/bcmrpi_defconfig | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 105bcbe..1b06882 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -894,6 +894,9 @@ CONFIG_USB_ISIGHTFW=m - CONFIG_USB_YUREX=m - CONFIG_MMC=y - CONFIG_MMC_BLOCK_MINORS=32 -+CONFIG_MMC_BCM2835=y -+CONFIG_MMC_BCM2835_DMA=y -+CONFIG_MMC_BCM2835_PIO_DMA_BARRIER=2 - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_PLTFM=y - CONFIG_MMC_SDHCI_BCM2708=y -@@ -944,9 +947,9 @@ CONFIG_RTC_DRV_DS3234=m - CONFIG_RTC_DRV_PCF2123=m - CONFIG_RTC_DRV_RX4581=m - CONFIG_DMADEVICES=y --CONFIG_DMA_BCM2708=m -+CONFIG_DMA_BCM2708=y - CONFIG_DMA_ENGINE=y --CONFIG_DMA_VIRTUAL_CHANNELS=m -+CONFIG_DMA_VIRTUAL_CHANNELS=y - CONFIG_UIO=m - CONFIG_UIO_PDRV_GENIRQ=m - CONFIG_STAGING=y - -From 9e15b1d99263bd5bb80de6a9d408688e0ce0c9a4 Mon Sep 17 00:00:00 2001 +From e5a1e8951507bd8708d239a6f7c0ba1a31d7573c Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Mon, 4 Aug 2014 10:06:56 +0200 -Subject: [PATCH 74/94] Added support for HiFiBerry DAC+ +Subject: [PATCH 69/82] Added support for HiFiBerry DAC+ The driver is based on the HiFiBerry DAC driver. However HiFiBerry DAC+ uses a different codec chip (PCM5122), therefore a new driver is necessary. @@ -121828,22 +117622,22 @@ a different codec chip (PCM5122), therefore a new driver is necessary. create mode 100644 sound/soc/bcm/hifiberry_dacplus.c diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 1b06882..4d70168 100644 +index f88d2d6..f0bc183 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -747,6 +747,7 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y - CONFIG_SND_SOC_WM8804=m +@@ -734,6 +734,7 @@ CONFIG_SND_USB_6FIRE=m + CONFIG_SND_SOC=m CONFIG_SND_BCM2708_SOC_I2S=m CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m CONFIG_SND_BCM2708_SOC_RPI_DAC=m - CONFIG_SND_SOC_I2C_AND_SPI=m + CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index a37ad15..cf421ee 100644 +index c9e3038..5c19350 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -674,6 +674,20 @@ static struct platform_device snd_pcm5102a_codec_device = { +@@ -645,6 +645,20 @@ static struct platform_device snd_pcm5102a_codec_device = { }; #endif @@ -121864,7 +117658,7 @@ index a37ad15..cf421ee 100644 #if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE) static struct platform_device snd_hifiberry_digi_device = { .name = "snd-hifiberry-digi", -@@ -879,6 +893,11 @@ void __init bcm2708_init(void) +@@ -845,6 +859,11 @@ void __init bcm2708_init(void) bcm_register_device(&snd_pcm5102a_codec_device); #endif @@ -122038,339 +117832,10 @@ index 0000000..c63387b +MODULE_DESCRIPTION("ASoC Driver for HiFiBerry DAC+"); +MODULE_LICENSE("GPL v2"); -From 06411e077731eea2573931325379ed81958c7c08 Mon Sep 17 00:00:00 2001 -From: Florian Meier -Date: Mon, 4 Aug 2014 16:47:36 +0200 -Subject: [PATCH 75/94] ASoC: BCM: Typo in RPi-DAC driver - -This patch corrects a typo that originated from -inattentive copy and paste. - -Signed-off-by: Florian Meier ---- - sound/soc/bcm/rpi-dac.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/sound/soc/bcm/rpi-dac.c b/sound/soc/bcm/rpi-dac.c -index ef3cd93..6d6e0ba 100644 ---- a/sound/soc/bcm/rpi-dac.c -+++ b/sound/soc/bcm/rpi-dac.c -@@ -44,8 +44,8 @@ static struct snd_soc_ops snd_rpi_rpi_dac_ops = { - - static struct snd_soc_dai_link snd_rpi_rpi_dac_dai[] = { - { -- .name = "HifiBerry Mini", -- .stream_name = "HifiBerry Mini HiFi", -+ .name = "RPi-DAC", -+ .stream_name = "RPi-DAC HiFi", - .cpu_dai_name = "bcm2708-i2s.0", - .codec_dai_name = "pcm1794a-hifi", - .platform_name = "bcm2708-i2s.0", - -From 0a267ea51fa04dfa7cdfa7ae2f87120640ff0d63 Mon Sep 17 00:00:00 2001 -From: Kari Suvanto -Date: Tue, 19 Aug 2014 14:25:28 +0300 -Subject: [PATCH 76/94] usb: dwc: fix lockdep false positive - -Os wrapper function for spinlock init causes lockdep to show this -false positive splat during boot: -[ 3.789851] ============================================= -[ 3.796603] [ INFO: possible recursive locking detected ] -[ 3.803320] 3.16.1+ #5 Not tainted -[ 3.808015] --------------------------------------------- -[ 3.814730] khubd/18 is trying to acquire lock: -[ 3.820537] (&(sl)->rlock){-.-...}, at: [] DWC_SPINLOCK_IRQSAVE+0xc/0x14 -[ 3.830932] -[ 3.830932] but task is already holding lock: -[ 3.839274] (&(sl)->rlock){-.-...}, at: [] DWC_SPINLOCK_IRQSAVE+0xc/0x14 -[ 3.849704] -[ 3.849704] other info that might help us debug this: -[ 3.858826] Possible unsafe locking scenario: -[ 3.858826] -[ 3.867334] CPU0 -[ 3.871052] ---- -[ 3.874721] lock(&(sl)->rlock); -[ 3.879302] lock(&(sl)->rlock); -[ 3.883815] -[ 3.883815] *** DEADLOCK *** -[ 3.883815] -[ 3.892869] May be due to missing lock nesting notation -[ 3.892869] -[ 3.901736] 4 locks held by khubd/18: -[ 3.906438] #0: (&dev->mutex){......}, at: [] hub_thread+0x98/0x1000 -[ 3.916026] #1: (&port_dev->status_lock){+.+.+.}, at: [] hub_thread+0x63c/0x1000 -[ 3.926847] #2: (&bus->usb_address0_mutex){+.+.+.}, at: [] hub_port_init+0x5c/0xb24 -[ 3.938015] #3: (&(sl)->rlock){-.-...}, at: [] DWC_SPINLOCK_IRQSAVE+0xc/0x14 -[ 3.948730] -[ 3.948730] stack backtrace: -[ 3.955457] CPU: 0 PID: 18 Comm: khubd Not tainted 3.16.1+ #5 -[ 3.962541] [] (unwind_backtrace) from [] (show_stack+0x10/0x14) -[ 3.972998] [] (show_stack) from [] (__lock_acquire+0x1420/0x1ae0) -[ 3.983910] [] (__lock_acquire) from [] (lock_acquire+0x6c/0x8c) -[ 3.994908] [] (lock_acquire) from [] (_raw_spin_lock_irqsave+0x50/0x64) -[ 4.006756] [] (_raw_spin_lock_irqsave) from [] (DWC_SPINLOCK_IRQSAVE+0xc/0x14) -[ 4.019382] [] (DWC_SPINLOCK_IRQSAVE) from [] (dwc_otg_hcd_select_transactions+0x20c/0x368) -[ 4.033064] [] (dwc_otg_hcd_select_transactions) from [] (dwc_otg_hcd_urb_enqueue+0x158/0x1ec) -[ 4.047017] [] (dwc_otg_hcd_urb_enqueue) from [] (dwc_otg_urb_enqueue+0x1a8/0x2e0) -[ 4.059889] [] (dwc_otg_urb_enqueue) from [] (usb_hcd_submit_urb+0xb8/0x870) -[ 4.072316] [] (usb_hcd_submit_urb) from [] (usb_start_wait_urb+0x44/0xbc) -[ 4.084786] [] (usb_start_wait_urb) from [] (usb_control_msg+0xb4/0xec) -[ 4.097045] [] (usb_control_msg) from [] (hub_port_init+0x420/0xb24) -[ 4.109018] [] (hub_port_init) from [] (hub_thread+0x650/0x1000) -[ 4.120667] [] (hub_thread) from [] (kthread+0xc8/0xe4) -[ 4.129668] [] (kthread) from [] (ret_from_fork+0x14/0x2c) - -This is false positive because the lockdep uses the lock variable name -to keep track of locks. To fix this, the spin_lock_init function can't be in a -wrapper function for spinlock name to recorder correctly. I noticed similar fix -was already made for mutex debugging so used similar approach and added extra -macro to be used to spinlock allocation when spinlock debugging is on. - -Signed-off-by: Kari Suvanto ---- - drivers/usb/host/dwc_common_port/dwc_common_linux.c | 8 ++++++++ - drivers/usb/host/dwc_common_port/dwc_os.h | 16 +++++++++++++++- - drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 5 +++++ - drivers/usb/host/dwc_otg/dwc_otg_pcd.c | 4 ++++ - 4 files changed, 32 insertions(+), 1 deletion(-) - -diff --git a/drivers/usb/host/dwc_common_port/dwc_common_linux.c b/drivers/usb/host/dwc_common_port/dwc_common_linux.c -index 6d01261..5c50a8b 100644 ---- a/drivers/usb/host/dwc_common_port/dwc_common_linux.c -+++ b/drivers/usb/host/dwc_common_port/dwc_common_linux.c -@@ -766,7 +766,11 @@ dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data) - goto no_name; - } - -+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) -+ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(t->lock); -+#else - t->lock = DWC_SPINLOCK_ALLOC(); -+#endif - if (!t->lock) { - DWC_ERROR("Cannot allocate memory for lock"); - goto no_lock; -@@ -1083,7 +1087,11 @@ dwc_workq_t *DWC_WORKQ_ALLOC(char *name) - - wq->pending = 0; - -+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) -+ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(wq->lock); -+#else - wq->lock = DWC_SPINLOCK_ALLOC(); -+#endif - if (!wq->lock) { - goto no_lock; - } -diff --git a/drivers/usb/host/dwc_common_port/dwc_os.h b/drivers/usb/host/dwc_common_port/dwc_os.h -index 09ed244..a2bbe23 100644 ---- a/drivers/usb/host/dwc_common_port/dwc_os.h -+++ b/drivers/usb/host/dwc_common_port/dwc_os.h -@@ -59,6 +59,7 @@ extern "C" { - # ifdef CONFIG_DEBUG_MUTEXES - # include - # endif -+# include - # include - # include - #endif -@@ -1039,9 +1040,22 @@ typedef unsigned long dwc_irqflags_t; - /** Returns an initialized lock variable. This function should allocate and - * initialize the OS-specific data structure used for locking. This data - * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should -- * be freed by the DWC_FREE_LOCK when it is no longer used. */ -+ * be freed by the DWC_FREE_LOCK when it is no longer used. -+ * -+ * For Linux Spinlock Debugging make it macro because the debugging routines use -+ * the symbol name to determine recursive locking. Using a wrapper function -+ * makes it falsely think recursive locking occurs. */ -+#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK) -+#define DWC_SPINLOCK_ALLOC_LINUX_DEBUG(lock) ({ \ -+ lock = DWC_ALLOC(sizeof(spinlock_t)); \ -+ if (lock) { \ -+ spin_lock_init((spinlock_t *)lock); \ -+ } \ -+}) -+#else - extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void); - #define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC() -+#endif - - /** Frees an initialized lock variable. */ - extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock); -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -index 35721e5..c39ef31 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c -@@ -951,8 +951,13 @@ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) - int i; - dwc_hc_t *channel; - -+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) -+ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->lock); -+ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->channel_lock); -+#else - hcd->lock = DWC_SPINLOCK_ALLOC(); - hcd->channel_lock = DWC_SPINLOCK_ALLOC(); -+#endif - DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n", - hcd, core_if); - if (!hcd->lock) { -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_pcd.c b/drivers/usb/host/dwc_otg/dwc_otg_pcd.c -index 40fb25c..ae0c72d 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_pcd.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd.c -@@ -1120,7 +1120,11 @@ dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if) - return NULL; - } - -+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) -+ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(pcd->lock); -+#else - pcd->lock = DWC_SPINLOCK_ALLOC(); -+#endif - DWC_DEBUGPL(DBG_HCDV, "Init of PCD %p given core_if %p\n", - pcd, core_if);//GRAYG - if (!pcd->lock) { - -From 92463750c77bf0040424411fd70b26204db5cdc1 Mon Sep 17 00:00:00 2001 -From: Kari Suvanto -Date: Tue, 19 Aug 2014 14:38:24 +0300 -Subject: [PATCH 77/94] usb: dwc: fix inconsistent lock state - -Lockdep gives this splat during boot: -[ 4.136748] ================================= -[ 4.145487] [ INFO: inconsistent lock state ] -[ 4.154157] 3.16.1+ #12 Not tainted -[ 4.161852] --------------------------------- -[ 4.170459] inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage. -[ 4.180776] khubd/18 [HC0[0]:SC0[0]:HE1:SE1] takes: -[ 4.189971] (&((spinlock_t *)hcd->lock)->rlock){?.-...}, at: [] dwc_otg_hcd_qh_free+0x18/0xcc -[ 4.204074] {IN-HARDIRQ-W} state was registered at: -[ 4.213359] [] _raw_spin_lock+0x40/0x50 -[ 4.222743] [] dwc_otg_handle_common_intr+0x44/0xd90 -[ 4.233133] [] dwc_otg_common_irq+0xc/0x18 -[ 4.242739] [] handle_irq_event_percpu+0x34/0x150 -[ 4.252955] [] handle_irq_event+0x3c/0x5c -[ 4.262395] [] handle_level_irq+0x8c/0x130 -[ 4.271972] [] generic_handle_irq+0x28/0x40 -[ 4.281489] [] handle_IRQ+0x30/0x84 -[ 4.290442] [] __irq_svc+0x38/0xd0 -[ 4.299164] [] DWC_MODIFY_REG32+0x64/0x84 -[ 4.308613] [] dwc_otg_driver_probe+0x720/0x7a8 -[ 4.318523] [] platform_drv_probe+0x18/0x48 -[ 4.328141] [] really_probe+0x68/0x200 -[ 4.337334] [] __driver_attach+0xa0/0xa4 -[ 4.346592] [] bus_for_each_dev+0x60/0x94 -[ 4.355998] [] bus_add_driver+0x140/0x1ec -[ 4.365262] [] driver_register+0x78/0xf8 -[ 4.374561] [] dwc_otg_driver_init+0x58/0x114 -[ 4.384271] [] do_one_initcall+0x80/0x1cc -[ 4.393661] [] kernel_init_freeable+0xf0/0x1b0 -[ 4.403501] [] kernel_init+0x8/0xec -[ 4.412308] [] ret_from_fork+0x14/0x2c -[ 4.421444] irq event stamp: 2351 -[ 4.428928] hardirqs last enabled at (2351): [] _raw_spin_unlock_irqrestore+0x7c/0x94 -[ 4.442100] hardirqs last disabled at (2350): [] _raw_spin_lock_irqsave+0x1c/0x64 -[ 4.454802] softirqs last enabled at (2320): [] __do_softirq+0x1ac/0x26c -[ 4.466739] softirqs last disabled at (2297): [] irq_exit+0xac/0x100 -[ 4.478260] -[ 4.478260] other info that might help us debug this: -[ 4.493215] Possible unsafe locking scenario: -[ 4.493215] -[ 4.507451] CPU0 -[ 4.513932] ---- -[ 4.520505] lock(&((spinlock_t *)hcd->lock)->rlock); -[ 4.529767] -[ 4.536515] lock(&((spinlock_t *)hcd->lock)->rlock); -[ 4.545951] -[ 4.545951] *** DEADLOCK *** -[ 4.545951] -[ 4.564132] 3 locks held by khubd/18: -[ 4.571884] #0: (&dev->mutex){......}, at: [] hub_thread+0x98/0x1000 -[ 4.583536] #1: (&port_dev->status_lock){+.+.+.}, at: [] hub_thread+0x63c/0x1000 -[ 4.596241] #2: (&bus->usb_address0_mutex){+.+.+.}, at: [] hub_port_init+0x5c/0xb24 -[ 4.609307] -[ 4.609307] stack backtrace: -[ 4.621705] CPU: 0 PID: 18 Comm: khubd Not tainted 3.16.1+ #12 -[ 4.631643] [] (unwind_backtrace) from [] (show_stack+0x10/0x14) -[ 4.643580] [] (show_stack) from [] (print_usage_bug+0x240/0x2b0) -[ 4.655608] [] (print_usage_bug) from [] (mark_lock+0x1d0/0x67c) -[ 4.667527] [] (mark_lock) from [] (__lock_acquire+0x5d4/0x1ae0) -[ 4.679551] [] (__lock_acquire) from [] (lock_acquire+0x6c/0x8c) -[ 4.691610] [] (lock_acquire) from [] (_raw_spin_lock+0x40/0x50) -[ 4.703584] [] (_raw_spin_lock) from [] (dwc_otg_hcd_qh_free+0x18/0xcc) -[ 4.716305] [] (dwc_otg_hcd_qh_free) from [] (dwc_otg_hcd_endpoint_disable+0x9c/0xb0) -[ 4.730246] [] (dwc_otg_hcd_endpoint_disable) from [] (endpoint_disable+0x18/0x24) -[ 4.743919] [] (endpoint_disable) from [] (usb_ep0_reinit+0x14/0x38) -[ 4.756379] [] (usb_ep0_reinit) from [] (hub_port_init+0x2a4/0xb24) -[ 4.768652] [] (hub_port_init) from [] (hub_thread+0x650/0x1000) -[ 4.780824] [] (hub_thread) from [] (kthread+0xc8/0xe4) -[ 4.792231] [] (kthread) from [] (ret_from_fork+0x14/0x2c) - -This splat shows that the hcd spinlock is used from hard irq context and also from -process context with irqs on. - -To fix this, use spinlock_irqsave instead of spinlock in dwc_otg_hcd_qh_free. - -Signed-off-by: Kari Suvanto ---- - drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - -diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c -index 8706a5c..17d3030 100644 ---- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c -+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c -@@ -55,9 +55,10 @@ extern bool microframe_schedule; - void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) - { - dwc_otg_qtd_t *qtd, *qtd_tmp; -+ dwc_irqflags_t flags; - - /* Free each QTD in the QTD list */ -- DWC_SPINLOCK(hcd->lock); -+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); - DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) { - DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry); - dwc_otg_hcd_qtd_free(qtd); -@@ -76,7 +77,7 @@ void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) - } - - DWC_FREE(qh); -- DWC_SPINUNLOCK(hcd->lock); -+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); - return; - } - - -From 16c3f0f68eb7a2f4751a9f93babf22d3c3830b3f Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Tue, 19 Aug 2014 00:25:00 +0100 -Subject: [PATCH 78/94] bcm2708: Enable bcm2835_mmc by default - ---- - arch/arm/mach-bcm2708/bcm2708.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index cf421ee..ac30e14 100644 ---- a/arch/arm/mach-bcm2708/bcm2708.c -+++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -92,7 +92,7 @@ static unsigned disk_led_active_low = 1; - static unsigned reboot_part = 0; - static unsigned w1_gpio_pin = W1_GPIO; - static unsigned w1_gpio_pullup = W1_PULLUP; --static unsigned bcm2835_mmc = 0; -+static unsigned bcm2835_mmc = 1; - - static void __init bcm2708_init_led(void); - - -From 8e288e5e667d46d5acb696cb5e4e84c6249f8905 Mon Sep 17 00:00:00 2001 +From 2f2b25463b8345c39ecc077614810cea585eb650 Mon Sep 17 00:00:00 2001 From: android Date: Mon, 25 Aug 2014 06:54:19 +0100 -Subject: [PATCH 79/94] bcm2708_fb : Implement blanking support using the +Subject: [PATCH 70/82] bcm2708_fb : Implement blanking support using the mailbox property interface This implementation uses the userspace request style of an array of unsigned @@ -122381,36 +117846,9 @@ vcio.h : Renamed DEVICE_FILE_NAME to something more appropriate. users of the vcio api will be unaffected by this change as the device node is created manually in userspace --- - arch/arm/mach-bcm2708/include/mach/vcio.h | 9 ++++++++- - drivers/video/fbdev/bcm2708_fb.c | 31 +++++++++++++++++++++++++++---- - 2 files changed, 35 insertions(+), 5 deletions(-) + drivers/video/fbdev/bcm2708_fb.c | 31 +++++++++++++++++++++++++++---- + 1 file changed, 27 insertions(+), 4 deletions(-) -diff --git a/arch/arm/mach-bcm2708/include/mach/vcio.h b/arch/arm/mach-bcm2708/include/mach/vcio.h -index 9935e02..62e052e 100644 ---- a/arch/arm/mach-bcm2708/include/mach/vcio.h -+++ b/arch/arm/mach-bcm2708/include/mach/vcio.h -@@ -33,6 +33,13 @@ - #define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */ - #define MBOX_CHAN_COUNT 9 - -+enum { -+ VCMSG_PROCESS_REQUEST = 0x00000000 -+}; -+enum { -+ VCMSG_REQUEST_SUCCESSFUL = 0x80000000, -+ VCMSG_REQUEST_FAILED = 0x80000001 -+}; - /* Mailbox property tags */ - enum { - VCMSG_PROPERTY_END = 0x00000000, -@@ -136,6 +143,6 @@ extern int /*rc*/ bcm_mailbox_property(void *data, int size); - /* - * The name of the device file - */ --#define DEVICE_FILE_NAME "char_dev" -+#define DEVICE_FILE_NAME "vcio" - - #endif diff --git a/drivers/video/fbdev/bcm2708_fb.c b/drivers/video/fbdev/bcm2708_fb.c index b3b1e04..b25dd5b 100644 --- a/drivers/video/fbdev/bcm2708_fb.c @@ -122457,45 +117895,45 @@ index b3b1e04..b25dd5b 100644 const struct fb_fillrect *rect) { -From 7be5982a8515bb345dee85a5f0fb2c19ff4ce53d Mon Sep 17 00:00:00 2001 +From 5ed8458f11368f365e4280cb714cc77b4b10e9f5 Mon Sep 17 00:00:00 2001 From: Daniel Matuschek Date: Mon, 4 Aug 2014 11:09:58 +0200 -Subject: [PATCH 80/94] Added driver for HiFiBerry Amp amplifier add-on board +Subject: [PATCH 71/82] Added driver for HiFiBerry Amp amplifier add-on board The driver contains a low-level hardware driver for the TAS5713 and the drivers for the Raspberry Pi I2S subsystem. --- arch/arm/configs/bcmrpi_defconfig | 1 + - arch/arm/mach-bcm2708/bcm2708.c | 20 ++ + arch/arm/mach-bcm2708/bcm2708.c | 20 +++ sound/soc/bcm/Kconfig | 7 + sound/soc/bcm/Makefile | 2 + sound/soc/bcm/hifiberry_amp.c | 106 +++++++++++ sound/soc/codecs/Kconfig | 4 + sound/soc/codecs/Makefile | 2 + - sound/soc/codecs/tas5713.c | 371 ++++++++++++++++++++++++++++++++++++++ - sound/soc/codecs/tas5713.h | 210 +++++++++++++++++++++ - 9 files changed, 723 insertions(+) + sound/soc/codecs/tas5713.c | 363 ++++++++++++++++++++++++++++++++++++++ + sound/soc/codecs/tas5713.h | 210 ++++++++++++++++++++++ + 9 files changed, 715 insertions(+) create mode 100644 sound/soc/bcm/hifiberry_amp.c create mode 100644 sound/soc/codecs/tas5713.c create mode 100644 sound/soc/codecs/tas5713.h diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 4d70168..742548f 100644 +index f0bc183..873a32e 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -749,6 +749,7 @@ CONFIG_SND_BCM2708_SOC_I2S=m +@@ -736,6 +736,7 @@ CONFIG_SND_BCM2708_SOC_I2S=m CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m CONFIG_SND_BCM2708_SOC_RPI_DAC=m - CONFIG_SND_SOC_I2C_AND_SPI=m - CONFIG_SND_SOC_PCM5102A=m + CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m + CONFIG_SND_SIMPLE_CARD=m diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c -index ac30e14..527deaa 100644 +index 5c19350..2f2e11f 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c -@@ -703,6 +703,20 @@ static struct i2c_board_info __initdata snd_wm8804_i2c_devices[] = { +@@ -674,6 +674,20 @@ static struct i2c_board_info __initdata snd_wm8804_i2c_devices[] = { #endif @@ -122516,7 +117954,7 @@ index ac30e14..527deaa 100644 #if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) static struct platform_device snd_rpi_dac_device = { .name = "snd-rpi-dac", -@@ -903,6 +917,12 @@ void __init bcm2708_init(void) +@@ -869,6 +883,12 @@ void __init bcm2708_init(void) i2c_register_board_info(1, snd_wm8804_i2c_devices, ARRAY_SIZE(snd_wm8804_i2c_devices)); #endif @@ -122678,10 +118116,10 @@ index 0000000..1e87ee0 +MODULE_DESCRIPTION("ASoC driver for HiFiBerry-AMP"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig -index 0309507..569c18b 100644 +index f252baa..abba3ef 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig -@@ -96,6 +96,7 @@ config SND_SOC_ALL_CODECS +@@ -100,6 +100,7 @@ config SND_SOC_ALL_CODECS select SND_SOC_TAS5086 if I2C select SND_SOC_TLV320AIC23_I2C if I2C select SND_SOC_TLV320AIC23_SPI if SPI_MASTER @@ -122689,7 +118127,7 @@ index 0309507..569c18b 100644 select SND_SOC_TLV320AIC26 if SPI_MASTER select SND_SOC_TLV320AIC31XX if I2C select SND_SOC_TLV320AIC32X4 if I2C -@@ -533,6 +534,9 @@ config SND_SOC_TAS5086 +@@ -556,6 +557,9 @@ config SND_SOC_TAS5086 tristate "Texas Instruments TAS5086 speaker amplifier" depends on I2C @@ -122700,10 +118138,10 @@ index 0309507..569c18b 100644 tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile -index 64a04fb..edfa85c 100644 +index b4a8a98..e200d60 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile -@@ -95,6 +95,7 @@ snd-soc-sta350-objs := sta350.o +@@ -98,6 +98,7 @@ snd-soc-sta350-objs := sta350.o snd-soc-sta529-objs := sta529.o snd-soc-stac9766-objs := stac9766.o snd-soc-tas5086-objs := tas5086.o @@ -122711,9 +118149,9 @@ index 64a04fb..edfa85c 100644 snd-soc-tlv320aic23-objs := tlv320aic23.o snd-soc-tlv320aic23-i2c-objs := tlv320aic23-i2c.o snd-soc-tlv320aic23-spi-objs := tlv320aic23-spi.o -@@ -260,6 +261,7 @@ obj-$(CONFIG_SND_SOC_STA350) += snd-soc-sta350.o - obj-$(CONFIG_SND_SOC_STA529) += snd-soc-sta529.o +@@ -268,6 +269,7 @@ obj-$(CONFIG_SND_SOC_STA529) += snd-soc-sta529.o obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o + obj-$(CONFIG_SND_SOC_TAS2552) += snd-soc-tas2552.o obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o +obj-$(CONFIG_SND_SOC_TAS5713) += snd-soc-tas5713.o obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o @@ -122721,10 +118159,10 @@ index 64a04fb..edfa85c 100644 obj-$(CONFIG_SND_SOC_TLV320AIC23_SPI) += snd-soc-tlv320aic23-spi.o diff --git a/sound/soc/codecs/tas5713.c b/sound/soc/codecs/tas5713.c new file mode 100644 -index 0000000..ee96a12 +index 0000000..90accc2 --- /dev/null +++ b/sound/soc/codecs/tas5713.c -@@ -0,0 +1,371 @@ +@@ -0,0 +1,363 @@ +/* + * ASoC Driver for TAS5713 + * @@ -122907,14 +118345,6 @@ index 0000000..ee96a12 + + tas5713 = snd_soc_codec_get_drvdata(codec); + -+ codec->control_data = tas5713->regmap; -+ -+ ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP); -+ if (ret < 0) { -+ dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret); -+ return ret; -+ } -+ + // Reset error + ret = snd_soc_write(codec, TAS5713_ERROR_STATUS, 0x00); + @@ -123313,111 +118743,17 @@ index 0000000..8f019e0 + +#endif /* _TAS5713_H */ -From 0f0f41157f6f1525ec47cd92e87667c3cd574b02 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Fri, 12 Sep 2014 14:33:41 +0100 -Subject: [PATCH 81/94] Revert "ASoc: Don't report S24_LE support, it produces - white noise with xbmc" - -This reverts commit db761a2a596f655673d41d329bcfc954c68e6e02. ---- - sound/soc/bcm/bcm2708-i2s.c | 2 +- - sound/soc/codecs/pcm5102a.c | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/sound/soc/bcm/bcm2708-i2s.c b/sound/soc/bcm/bcm2708-i2s.c -index 905f076..128c158 100644 ---- a/sound/soc/bcm/bcm2708-i2s.c -+++ b/sound/soc/bcm/bcm2708-i2s.c -@@ -785,7 +785,7 @@ static struct snd_soc_dai_driver bcm2708_i2s_dai = { - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE -- // | SNDRV_PCM_FMTBIT_S24_LE : disable for now, it causes white noise with xbmc -+ | SNDRV_PCM_FMTBIT_S24_LE - | SNDRV_PCM_FMTBIT_S32_LE - }, - .capture = { -diff --git a/sound/soc/codecs/pcm5102a.c b/sound/soc/codecs/pcm5102a.c -index 7812d34..126f1e9 100644 ---- a/sound/soc/codecs/pcm5102a.c -+++ b/sound/soc/codecs/pcm5102a.c -@@ -28,7 +28,7 @@ static struct snd_soc_dai_driver pcm5102a_dai = { - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | -- // SNDRV_PCM_FMTBIT_S24_LE | : disable for now, it causes white noise with xbmc -+ SNDRV_PCM_FMTBIT_S24_LE | - SNDRV_PCM_FMTBIT_S32_LE - }, - }; - -From 737341cede36eba1f41f0193dc4957624398e46d Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Sat, 13 Sep 2014 10:52:04 +0100 -Subject: [PATCH 82/94] bcm2708-i2s: Update bclk_ratio to more correct values - ---- - sound/soc/bcm/bcm2708-i2s.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/sound/soc/bcm/bcm2708-i2s.c b/sound/soc/bcm/bcm2708-i2s.c -index 128c158..f1859b2 100644 ---- a/sound/soc/bcm/bcm2708-i2s.c -+++ b/sound/soc/bcm/bcm2708-i2s.c -@@ -411,15 +411,15 @@ static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream, - switch (params_format(params)) { - case SNDRV_PCM_FORMAT_S16_LE: - data_length = 16; -- bclk_ratio = 40; -+ bclk_ratio = 50; - break; - case SNDRV_PCM_FORMAT_S24_LE: - data_length = 24; -- bclk_ratio = 40; -+ bclk_ratio = 50; - break; - case SNDRV_PCM_FORMAT_S32_LE: - data_length = 32; -- bclk_ratio = 80; -+ bclk_ratio = 100; - break; - default: - return -EINVAL; - -From ba76bd6851e91bdd554ef9f210e7f31ed12159f9 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Tue, 16 Sep 2014 15:10:10 +0100 -Subject: [PATCH 83/94] config: Add module SND_SIMPLE_CARD - ---- - arch/arm/configs/bcmrpi_defconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig -index 742548f..73fcb9d 100644 ---- a/arch/arm/configs/bcmrpi_defconfig -+++ b/arch/arm/configs/bcmrpi_defconfig -@@ -755,6 +755,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=m - CONFIG_SND_SOC_PCM5102A=m - CONFIG_SND_SOC_PCM1794A=m - CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m -+CONFIG_SND_SIMPLE_CARD=m - CONFIG_SOUND_PRIME=m - CONFIG_HIDRAW=y - CONFIG_HID_A4TECH=m - -From fcf9c64552775b27c1416a9eefaa73cb1cf831eb Mon Sep 17 00:00:00 2001 +From 4699dad488b935bed0f33f09ada533f73acba16a Mon Sep 17 00:00:00 2001 From: popcornmix Date: Wed, 3 Sep 2014 23:35:44 +0100 -Subject: [PATCH 84/94] bcm2708_fb: Add pan and vsync controls +Subject: [PATCH 72/82] bcm2708_fb: Add pan and vsync controls --- - drivers/video/fbdev/bcm2708_fb.c | 53 ++++++++++++++++++++++++++++++++-------- - 1 file changed, 43 insertions(+), 10 deletions(-) + drivers/video/fbdev/bcm2708_fb.c | 56 ++++++++++++++++++++++++++++++++-------- + 1 file changed, 45 insertions(+), 11 deletions(-) diff --git a/drivers/video/fbdev/bcm2708_fb.c b/drivers/video/fbdev/bcm2708_fb.c -index b25dd5b..ffa584b 100644 +index b25dd5b..32aaaf5 100644 --- a/drivers/video/fbdev/bcm2708_fb.c +++ b/drivers/video/fbdev/bcm2708_fb.c @@ -38,6 +38,9 @@ @@ -123450,17 +118786,18 @@ index b25dd5b..ffa584b 100644 p[0] = 28; // size = sizeof u32 * length of p p[1] = VCMSG_PROCESS_REQUEST; // process request p[2] = VCMSG_SET_BLANK_SCREEN; // (the tag id) -@@ -395,15 +396,45 @@ static int bcm2708_fb_blank(int blank_mode, struct fb_info *info) +@@ -395,15 +396,46 @@ static int bcm2708_fb_blank(int blank_mode, struct fb_info *info) bcm_mailbox_property(&p, p[0]); - pr_info("bcm2708_fb_blank returns=%d p[1]=0x%x\n",p[5],p[1]); -+ pr_info("bcm2708_fb_blank(%d) returns=%d p[1]=0x%x\n", blank_mode, p[5], p[1]); - +- if ( p[1] == VCMSG_REQUEST_SUCCESSFUL ) - result = 0 ; - + result = 0; ++ else ++ pr_err("bcm2708_fb_blank(%d) returns=%d p[1]=0x%x\n", blank_mode, p[5], p[1]); } return result; +} @@ -123471,7 +118808,8 @@ index b25dd5b..ffa584b 100644 + info->var.xoffset = var->xoffset; + info->var.yoffset = var->yoffset; + result = bcm2708_fb_set_par(info); -+ pr_info("bcm2708_fb_pan_display(%d,%d) returns=%d\n", var->xoffset, var->yoffset, result); ++ if (result != 0) ++ pr_err("bcm2708_fb_pan_display(%d,%d) returns=%d\n", var->xoffset, var->yoffset, result); + return result; +} @@ -123499,7 +118837,7 @@ index b25dd5b..ffa584b 100644 } static void bcm2708_fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) -@@ -590,6 +621,8 @@ static struct fb_ops bcm2708_fb_ops = { +@@ -590,6 +622,8 @@ static struct fb_ops bcm2708_fb_ops = { .fb_fillrect = bcm2708_fb_fillrect, .fb_copyarea = bcm2708_fb_copyarea, .fb_imageblit = bcm2708_fb_imageblit, @@ -123508,7 +118846,7 @@ index b25dd5b..ffa584b 100644 }; static int bcm2708_fb_register(struct bcm2708_fb *fb) -@@ -616,8 +649,8 @@ static int bcm2708_fb_register(struct bcm2708_fb *fb) +@@ -616,8 +650,8 @@ static int bcm2708_fb_register(struct bcm2708_fb *fb) strncpy(fb->fb.fix.id, bcm2708_name, sizeof(fb->fb.fix.id)); fb->fb.fix.type = FB_TYPE_PACKED_PIXELS; fb->fb.fix.type_aux = 0; @@ -123520,625 +118858,3953 @@ index b25dd5b..ffa584b 100644 fb->fb.fix.accel = FB_ACCEL_NONE; -From d3f8c5720354f6a5d6b1ec5080d8d1e53ae4203d Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Tue, 16 Sep 2014 15:07:30 +0100 -Subject: [PATCH 85/94] bcm2708_fb: Reduce dmesg spam +From 56c05623e005be2c02cb1f0f56456da12ef76ba7 Mon Sep 17 00:00:00 2001 +From: Nikesh Oswal +Date: Fri, 25 Jul 2014 12:17:36 +0100 +Subject: [PATCH 73/82] ARM: bcm2708: Limit the boot time interrupt allocation +Limit the boot time interrupt allocation to RPi related +interrupts only + +Signed-off-by: Nikesh Oswal +Signed-off-by: Manish Gupta --- - drivers/video/fbdev/bcm2708_fb.c | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) + arch/arm/mach-bcm2708/armctrl.c | 2 +- + arch/arm/mach-bcm2708/include/mach/irqs.h | 6 +++++- + 2 files changed, 6 insertions(+), 2 deletions(-) -diff --git a/drivers/video/fbdev/bcm2708_fb.c b/drivers/video/fbdev/bcm2708_fb.c -index ffa584b..32aaaf5 100644 ---- a/drivers/video/fbdev/bcm2708_fb.c -+++ b/drivers/video/fbdev/bcm2708_fb.c -@@ -396,10 +396,10 @@ static int bcm2708_fb_blank(int blank_mode, struct fb_info *info) - - bcm_mailbox_property(&p, p[0]); - -- pr_info("bcm2708_fb_blank(%d) returns=%d p[1]=0x%x\n", blank_mode, p[5], p[1]); -- - if ( p[1] == VCMSG_REQUEST_SUCCESSFUL ) - result = 0; -+ else -+ pr_err("bcm2708_fb_blank(%d) returns=%d p[1]=0x%x\n", blank_mode, p[5], p[1]); - } - return result; - } -@@ -410,7 +410,8 @@ static int bcm2708_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info - info->var.xoffset = var->xoffset; - info->var.yoffset = var->yoffset; - result = bcm2708_fb_set_par(info); -- pr_info("bcm2708_fb_pan_display(%d,%d) returns=%d\n", var->xoffset, var->yoffset, result); -+ if (result != 0) -+ pr_err("bcm2708_fb_pan_display(%d,%d) returns=%d\n", var->xoffset, var->yoffset, result); - return result; - } +diff --git a/arch/arm/mach-bcm2708/armctrl.c b/arch/arm/mach-bcm2708/armctrl.c +index 42f5e1c..33e1c8b 100644 +--- a/arch/arm/mach-bcm2708/armctrl.c ++++ b/arch/arm/mach-bcm2708/armctrl.c +@@ -298,7 +298,7 @@ int __init armctrl_init(void __iomem * base, unsigned int irq_start, + { + unsigned int irq; +- for (irq = 0; irq < NR_IRQS; irq++) { ++ for (irq = 0; irq < CORE_IRQS; irq++) { + unsigned int data = irq; + if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO) + data = remap_irqs[irq - INTERRUPT_JPEG]; +diff --git a/arch/arm/mach-bcm2708/include/mach/irqs.h b/arch/arm/mach-bcm2708/include/mach/irqs.h +index 4299054..9e3299a 100644 +--- a/arch/arm/mach-bcm2708/include/mach/irqs.h ++++ b/arch/arm/mach-bcm2708/include/mach/irqs.h +@@ -192,6 +192,10 @@ + #define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS) + #define GPIO_IRQS (32*5) + #define SPARE_IRQS (64) +-#define NR_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_IRQS) ++#define CORE_IRQS HARD_IRQS+FIQ_IRQS+GPIO_IRQS ++ ++#define BOARD_AUDIO_IRQS 130 ++ ++#define NR_IRQS CORE_IRQS+BOARD_AUDIO_IRQS + + #endif /* _BCM2708_IRQS_H_ */ -From 93cbf976b7a7d19b0daf5f2ac054aff33425fa74 Mon Sep 17 00:00:00 2001 -From: ghollingworth -Date: Wed, 20 Aug 2014 20:52:31 +0100 -Subject: [PATCH 86/94] gpio: Fix for GPIO interrupts higher than pin 32 +From 8407c0887209b899b0fb8a1ef0bc82fa25d19cc6 Mon Sep 17 00:00:00 2001 +From: Nikesh Oswal +Date: Tue, 19 Aug 2014 15:52:31 +0100 +Subject: [PATCH 74/82] ARM:bcm2708: Add Support for Wolfson Audio Card +Support for Wolfson Audio card in the BSP + +Signed-off-by: Nikesh Oswal +Signed-off-by: Manish Gupta --- - arch/arm/mach-bcm2708/bcm2708_gpio.c | 56 +++++++++++++++++++----------------- - 1 file changed, 29 insertions(+), 27 deletions(-) + arch/arm/mach-bcm2708/bcm2708.c | 154 +++++++++++++++++++++++++- + arch/arm/mach-bcm2708/include/mach/platform.h | 1 + + 2 files changed, 153 insertions(+), 2 deletions(-) -diff --git a/arch/arm/mach-bcm2708/bcm2708_gpio.c b/arch/arm/mach-bcm2708/bcm2708_gpio.c -index 120929ff..5fb845a 100644 ---- a/arch/arm/mach-bcm2708/bcm2708_gpio.c -+++ b/arch/arm/mach-bcm2708/bcm2708_gpio.c -@@ -56,10 +56,10 @@ struct bcm2708_gpio { - struct list_head list; - void __iomem *base; - struct gpio_chip gc; -- unsigned long rising; -- unsigned long falling; -- unsigned long high; -- unsigned long low; -+ unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32]; -+ unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32]; -+ unsigned long high[(BCM2708_NR_GPIOS + 31) / 32]; -+ unsigned long low[(BCM2708_NR_GPIOS + 31) / 32]; +diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c +index 2f2e11f..7839e31 100644 +--- a/arch/arm/mach-bcm2708/bcm2708.c ++++ b/arch/arm/mach-bcm2708/bcm2708.c +@@ -62,10 +62,17 @@ + #include "bcm2708.h" + #include "armctrl.h" + ++#include ++#include ++#include ++ + #ifdef CONFIG_BCM_VC_CMA + #include + #endif + ++#define GPIO_WM5102_IRQ 27 ++#define GPIO_WM5102_RST 17 ++#define GPIO_WM5102_LDOEN 22 + + /* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to + * give us IO access only to 64Mbytes of physical memory (26 bits). We could +@@ -609,7 +616,7 @@ static struct platform_device bcm2835_thermal_device = { + .name = "bcm2835_thermal", }; - static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset, -@@ -146,23 +146,26 @@ static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type) - { - unsigned irq = d->irq; - struct bcm2708_gpio *gpio = irq_get_chip_data(irq); -+ unsigned gn = irq_to_gpio(irq); -+ unsigned gb = gn / 32; -+ unsigned go = gn % 32; - -- gpio->rising &= ~(1 << irq_to_gpio(irq)); -- gpio->falling &= ~(1 << irq_to_gpio(irq)); -- gpio->high &= ~(1 << irq_to_gpio(irq)); -- gpio->low &= ~(1 << irq_to_gpio(irq)); -+ gpio->rising[gb] &= ~(1 << go); -+ gpio->falling[gb] &= ~(1 << go); -+ gpio->high[gb] &= ~(1 << go); -+ gpio->low[gb] &= ~(1 << go); - - if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) - return -EINVAL; - - if (type & IRQ_TYPE_EDGE_RISING) -- gpio->rising |= (1 << irq_to_gpio(irq)); -+ gpio->rising[gb] |= (1 << go); - if (type & IRQ_TYPE_EDGE_FALLING) -- gpio->falling |= (1 << irq_to_gpio(irq)); -+ gpio->falling[gb] |= (1 << go); - if (type & IRQ_TYPE_LEVEL_HIGH) -- gpio->high |= (1 << irq_to_gpio(irq)); -+ gpio->high[gb] |= (1 << go); - if (type & IRQ_TYPE_LEVEL_LOW) -- gpio->low |= (1 << irq_to_gpio(irq)); -+ gpio->low[gb] |= (1 << go); - return 0; - } - -@@ -191,37 +194,36 @@ static void bcm2708_gpio_irq_unmask(struct irq_data *d) - struct bcm2708_gpio *gpio = irq_get_chip_data(irq); - unsigned gn = irq_to_gpio(irq); - unsigned gb = gn / 32; -+ unsigned go = gn % 32; - unsigned long rising = readl(gpio->base + GPIOREN(gb)); - unsigned long falling = readl(gpio->base + GPIOFEN(gb)); - unsigned long high = readl(gpio->base + GPIOHEN(gb)); - unsigned long low = readl(gpio->base + GPIOLEN(gb)); - -- gn = gn % 32; -- -- writel(1 << gn, gpio->base + GPIOEDS(gb)); -+ writel(1 << go, gpio->base + GPIOEDS(gb)); - -- if (gpio->rising & (1 << gn)) { -- writel(rising | (1 << gn), gpio->base + GPIOREN(gb)); -+ if (gpio->rising[gb] & (1 << go)) { -+ writel(rising | (1 << go), gpio->base + GPIOREN(gb)); - } else { -- writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb)); -+ writel(rising & ~(1 << go), gpio->base + GPIOREN(gb)); - } - -- if (gpio->falling & (1 << gn)) { -- writel(falling | (1 << gn), gpio->base + GPIOFEN(gb)); -+ if (gpio->falling[gb] & (1 << go)) { -+ writel(falling | (1 << go), gpio->base + GPIOFEN(gb)); - } else { -- writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb)); -+ writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb)); - } - -- if (gpio->high & (1 << gn)) { -- writel(high | (1 << gn), gpio->base + GPIOHEN(gb)); -+ if (gpio->high[gb] & (1 << go)) { -+ writel(high | (1 << go), gpio->base + GPIOHEN(gb)); - } else { -- writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb)); -+ writel(high & ~(1 << go), gpio->base + GPIOHEN(gb)); - } - -- if (gpio->low & (1 << gn)) { -- writel(low | (1 << gn), gpio->base + GPIOLEN(gb)); -+ if (gpio->low[gb] & (1 << go)) { -+ writel(low | (1 << go), gpio->base + GPIOLEN(gb)); - } else { -- writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb)); -+ writel(low & ~(1 << go), gpio->base + GPIOLEN(gb)); - } - } - - -From e57780aae5cd3f785ade99d0e3ebe15504239a32 Mon Sep 17 00:00:00 2001 -From: Serge Schneider -Date: Wed, 3 Sep 2014 17:28:53 +0100 -Subject: [PATCH 87/94] power: Add defines for contolling DSI power through - mailbox interface - ---- - arch/arm/mach-bcm2708/include/mach/arm_power.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/arm/mach-bcm2708/include/mach/arm_power.h b/arch/arm/mach-bcm2708/include/mach/arm_power.h -index aae9136..d3bf245 100644 ---- a/arch/arm/mach-bcm2708/include/mach/arm_power.h -+++ b/arch/arm/mach-bcm2708/include/mach/arm_power.h -@@ -38,6 +38,7 @@ enum { - PREFIX(POWER_I2C2_BIT), - PREFIX(POWER_SPI_BIT), - PREFIX(POWER_CCP2TX_BIT), -+ PREFIX(POWER_DSI_BIT), - - PREFIX(POWER_MAX) +-#ifdef CONFIG_SND_BCM2708_SOC_I2S_MODULE ++#if defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE) || defined(CONFIG_SND_BCM2708_SOC_I2S) + static struct resource bcm2708_i2s_resources[] = { + { + .start = I2S_BASE, +@@ -631,6 +638,138 @@ static struct platform_device bcm2708_i2s_device = { }; -@@ -52,6 +53,7 @@ enum { - PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)), - PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)), - PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)), -+ PREFIX(POWER_DSI) = (1 << PREFIX(POWER_DSI_BIT)), - - PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1, - PREFIX(POWER_NONE) = 0 - -From dabe7b7d8898de714d73bcdf57a86fa045b9047a Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Wed, 3 Sep 2014 23:34:17 +0100 -Subject: [PATCH 88/94] vcio: Fix incorrect and add new mailbox tags - ---- - arch/arm/mach-bcm2708/include/mach/vcio.h | 29 +++++++++++++++++++++++------ - 1 file changed, 23 insertions(+), 6 deletions(-) - -diff --git a/arch/arm/mach-bcm2708/include/mach/vcio.h b/arch/arm/mach-bcm2708/include/mach/vcio.h -index 62e052e..8e11d67 100644 ---- a/arch/arm/mach-bcm2708/include/mach/vcio.h -+++ b/arch/arm/mach-bcm2708/include/mach/vcio.h -@@ -45,12 +45,12 @@ enum { - VCMSG_PROPERTY_END = 0x00000000, - VCMSG_GET_FIRMWARE_REVISION = 0x00000001, - VCMSG_GET_BOARD_MODEL = 0x00010001, -- VCMSG_GET_BOARD_REVISION = 0x00020002, -- VCMSG_GET_BOARD_MAC_ADDRESS = 0x00020003, -- VCMSG_GET_BOARD_SERIAL = 0x00020004, -- VCMSG_GET_ARM_MEMORY = 0x00020005, -- VCMSG_GET_VC_MEMORY = 0x00020006, -- VCMSG_GET_CLOCKS = 0x00020007, -+ VCMSG_GET_BOARD_REVISION = 0x00010002, -+ VCMSG_GET_BOARD_MAC_ADDRESS = 0x00010003, -+ VCMSG_GET_BOARD_SERIAL = 0x00010004, -+ VCMSG_GET_ARM_MEMORY = 0x00010005, -+ VCMSG_GET_VC_MEMORY = 0x00010006, -+ VCMSG_GET_CLOCKS = 0x00010007, - VCMSG_GET_COMMAND_LINE = 0x00050001, - VCMSG_GET_DMA_CHANNELS = 0x00060001, - VCMSG_GET_POWER_STATE = 0x00020001, -@@ -68,7 +68,20 @@ enum { - VCMSG_GET_MIN_CLOCK = 0x00030007, - VCMSG_GET_MIN_VOLTAGE = 0x00030008, - VCMSG_GET_TURBO = 0x00030009, -+ VCMSG_GET_MAX_TEMPERATURE = 0x0003000a, -+ VCMSG_GET_STC = 0x0003000b, - VCMSG_SET_TURBO = 0x00038009, -+ VCMSG_SET_ALLOCATE_MEM = 0x0003000c, -+ VCMSG_SET_LOCK_MEM = 0x0003000d, -+ VCMSG_SET_UNLOCK_MEM = 0x0003000e, -+ VCMSG_SET_RELEASE_MEM = 0x0003000f, -+ VCMSG_SET_EXECUTE_CODE = 0x00030010, -+ VCMSG_SET_EXECUTE_QPU = 0x00030011, -+ VCMSG_SET_ENABLE_QPU = 0x00030012, -+ VCMSG_GET_RESOURCE_HANDLE = 0x00030014, -+ VCMSG_GET_EDID_BLOCK = 0x00030020, -+ VCMSG_GET_CUSTOMER_OTP = 0x00030021, -+ VCMSG_SET_CUSTOMER_OTP = 0x00038021, - VCMSG_SET_ALLOCATE_BUFFER = 0x00040001, - VCMSG_SET_RELEASE_BUFFER = 0x00048001, - VCMSG_SET_BLANK_SCREEN = 0x00040002, -@@ -106,6 +119,10 @@ enum { - VCMSG_GET_TRANSFORM = 0x0004000d, - VCMSG_TST_TRANSFORM = 0x0004400d, - VCMSG_SET_TRANSFORM = 0x0004800d, -+ VCMSG_TST_VSYNC = 0x0004400e, -+ VCMSG_SET_VSYNC = 0x0004800e, -+ VCMSG_SET_CURSOR_INFO = 0x00008010, -+ VCMSG_SET_CURSOR_STATE = 0x00008011, - }; - - extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28); - -From ee6bb56a54b1407ee814cb3e320d0f31de1a0d40 Mon Sep 17 00:00:00 2001 -From: ghollingworth -Date: Wed, 20 Aug 2014 21:18:21 +0100 -Subject: [PATCH 89/94] lirc: Remove restriction on gpio pins that can be used - with lirc - -Compute Module, for example could use different pins ---- - drivers/staging/media/lirc/lirc_rpi.c | 25 +++++-------------------- - 1 file changed, 5 insertions(+), 20 deletions(-) - -diff --git a/drivers/staging/media/lirc/lirc_rpi.c b/drivers/staging/media/lirc/lirc_rpi.c -index 57ffacf..1da6a9f 100644 ---- a/drivers/staging/media/lirc/lirc_rpi.c -+++ b/drivers/staging/media/lirc/lirc_rpi.c -@@ -38,6 +38,7 @@ - #include - #include - #include -+#include - #include - - #define LIRC_DRIVER_NAME "lirc_rpi" -@@ -81,9 +82,6 @@ static long send_pulse(unsigned long length); - static void send_space(long length); - static void lirc_rpi_exit(void); - --int valid_gpio_pins[] = { 0, 1, 2, 3, 4, 7, 8, 9, 10, 11, 14, 15, 17, 18, 21, -- 22, 23, 24, 25 ,27, 28, 29, 30, 31 }; -- - static struct platform_device *lirc_rpi_dev; - static struct timeval lasttv = { 0, 0 }; - static struct lirc_buffer rbuf; -@@ -599,24 +597,13 @@ static void lirc_rpi_exit(void) - - static int __init lirc_rpi_init_module(void) - { -- int result, i; -+ int result; - - result = lirc_rpi_init(); - if (result) - return result; - -- /* check if the module received valid gpio pin numbers */ -- result = 0; -- if (gpio_in_pin != gpio_out_pin) { -- for(i = 0; (i < ARRAY_SIZE(valid_gpio_pins)) && (result != 2); i++) { -- if (gpio_in_pin == valid_gpio_pins[i] || -- gpio_out_pin == valid_gpio_pins[i]) { -- result++; -- } -- } -- } -- -- if (result != 2) { -+ if (gpio_in_pin >= BCM2708_NR_GPIOS || gpio_out_pin >= BCM2708_NR_GPIOS) { - result = -EINVAL; - printk(KERN_ERR LIRC_DRIVER_NAME - ": invalid GPIO pin(s) specified!\n"); -@@ -673,13 +660,11 @@ MODULE_LICENSE("GPL"); - - module_param(gpio_out_pin, int, S_IRUGO); - MODULE_PARM_DESC(gpio_out_pin, "GPIO output/transmitter pin number of the BCM" -- " processor. Valid pin numbers are: 0, 1, 4, 8, 7, 9, 10, 11," -- " 14, 15, 17, 18, 21, 22, 23, 24, 25, default 17"); -+ " processor. (default 17"); - - module_param(gpio_in_pin, int, S_IRUGO); - MODULE_PARM_DESC(gpio_in_pin, "GPIO input pin number of the BCM processor." -- " Valid pin numbers are: 0, 1, 4, 8, 7, 9, 10, 11, 14, 15," -- " 17, 18, 21, 22, 23, 24, 25, default 18"); -+ " (default 18"); - - module_param(sense, int, S_IRUGO); - MODULE_PARM_DESC(sense, "Override autodetection of IR receiver circuit" - -From eb9ade7441940042ab3533effddf644faa1c4856 Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Wed, 17 Sep 2014 22:23:21 +0100 -Subject: [PATCH 90/94] tas5713: snd_soc_codec_set_cache_io has gone in 3.16 - ---- - sound/soc/codecs/tas5713.c | 8 -------- - 1 file changed, 8 deletions(-) - -diff --git a/sound/soc/codecs/tas5713.c b/sound/soc/codecs/tas5713.c -index ee96a12..90accc2 100644 ---- a/sound/soc/codecs/tas5713.c -+++ b/sound/soc/codecs/tas5713.c -@@ -180,14 +180,6 @@ static int tas5713_probe(struct snd_soc_codec *codec) - - tas5713 = snd_soc_codec_get_drvdata(codec); - -- codec->control_data = tas5713->regmap; -- -- ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP); -- if (ret < 0) { -- dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret); -- return ret; -- } -- - // Reset error - ret = snd_soc_write(codec, TAS5713_ERROR_STATUS, 0x00); - - -From 16fbce12df7480b49311dce1065770e2f76a971d Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Wed, 17 Sep 2014 22:22:13 +0100 -Subject: [PATCH 91/94] bcm2708-i2s: Avoid leak from iomap when accessing gpio - ---- - sound/soc/bcm/bcm2708-i2s.c | 33 ++++++++++++++++++++++----------- - 1 file changed, 22 insertions(+), 11 deletions(-) - -diff --git a/sound/soc/bcm/bcm2708-i2s.c b/sound/soc/bcm/bcm2708-i2s.c -index f1859b2..2ea78c9 100644 ---- a/sound/soc/bcm/bcm2708-i2s.c -+++ b/sound/soc/bcm/bcm2708-i2s.c -@@ -40,6 +40,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -318,6 +319,26 @@ static int bcm2708_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai, - return 0; - } + #endif ++#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE) ++static struct regulator_consumer_supply dc1v8_consumers[] = { ++ REGULATOR_SUPPLY("LDOVDD", "spi0.1"), ++ REGULATOR_SUPPLY("AVDD", "spi0.1"), ++ REGULATOR_SUPPLY("DBVDD1", "spi0.1"), ++ REGULATOR_SUPPLY("CPVDD", "spi0.1"), ++ REGULATOR_SUPPLY("DBVDD2", "wm5102-codec"), ++ REGULATOR_SUPPLY("DBVDD3", "wm5102-codec"), ++ REGULATOR_SUPPLY("CPVDD", "wm5102-codec"), ++ REGULATOR_SUPPLY("PVDD", "1-003a"), ++ REGULATOR_SUPPLY("DVDD", "1-003a"), ++}; + -+static int bcm2708_i2s_set_function(unsigned offset, int function) -+{ -+ #define GPIOFSEL(x) (0x00+(x)*4) -+ void __iomem *gpio = __io_address(GPIO_BASE); -+ unsigned alt = function <= 3 ? function + 4: function == 4 ? 3 : 2; -+ unsigned gpiodir; -+ unsigned gpio_bank = offset / 10; -+ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; ++static struct regulator_init_data dc1v8_data = { ++ .constraints = { ++ .always_on = 1, ++ }, ++ .num_consumer_supplies = ARRAY_SIZE(dc1v8_consumers), ++ .consumer_supplies = dc1v8_consumers, ++}; + -+ if (offset >= BCM2708_NR_GPIOS) -+ return -EINVAL; ++static struct fixed_voltage_config dc1v8vdd_pdata = { ++ .supply_name = "DC_1V8", ++ .microvolts = 1800000, ++ .init_data = &dc1v8_data, ++ .gpio = -1, ++}; + -+ gpiodir = readl(gpio + GPIOFSEL(gpio_bank)); -+ gpiodir &= ~(7 << gpio_field_offset); -+ gpiodir |= alt << gpio_field_offset; -+ writel(gpiodir, gpio + GPIOFSEL(gpio_bank)); -+ return 0; -+} ++static struct platform_device dc1v8_device = { ++ .name = "reg-fixed-voltage", ++ .id = 0, ++ .dev = { ++ .platform_data = &dc1v8vdd_pdata, ++ }, ++}; + - static void bcm2708_i2s_setup_gpio(void) - { - /* -@@ -326,14 +347,8 @@ static void bcm2708_i2s_setup_gpio(void) - * TODO Better way would be to handle - * this in the device tree! - */ --#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3)) --#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) -- -- unsigned int *gpio; - int pin,pinconfig,startpin,alt; - -- gpio = ioremap(GPIO_BASE, SZ_16K); -- - /* SPI is on different GPIOs on different boards */ - /* for Raspberry Pi B+, this is pin GPIO18-21, for original on 28-31 */ - if (bcm2708_i2s_gpio==BCM2708_I2S_GPIO_AUTO) { -@@ -361,12 +376,8 @@ static void bcm2708_i2s_setup_gpio(void) - - /* configure I2S pins to correct ALT mode */ - for (pin = startpin; pin <= startpin+3; pin++) { -- INP_GPIO(pin); /* set mode to GPIO input first */ -- SET_GPIO_ALT(pin, alt); /* set mode to ALT */ -+ bcm2708_i2s_set_function(pin, alt); - } -- --#undef INP_GPIO --#undef SET_GPIO_ALT - } - - static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream, - -From ba27be53aa6ef038d3e4bdb6c6da83225b28cb3d Mon Sep 17 00:00:00 2001 -From: popcornmix -Date: Sat, 30 Aug 2014 16:24:19 +0100 -Subject: [PATCH 92/94] bcm2708-i2s: Fix check for B+ board revision to exclude - flags like warranty bit - ---- - sound/soc/bcm/bcm2708-i2s.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/sound/soc/bcm/bcm2708-i2s.c b/sound/soc/bcm/bcm2708-i2s.c -index 2ea78c9..9023984 100644 ---- a/sound/soc/bcm/bcm2708-i2s.c -+++ b/sound/soc/bcm/bcm2708-i2s.c -@@ -352,7 +352,7 @@ static void bcm2708_i2s_setup_gpio(void) - /* SPI is on different GPIOs on different boards */ - /* for Raspberry Pi B+, this is pin GPIO18-21, for original on 28-31 */ - if (bcm2708_i2s_gpio==BCM2708_I2S_GPIO_AUTO) { -- if (system_rev >= 0x10) { -+ if ((system_rev & 0xffffff) >= 0x10) { - /* Model B+ */ - pinconfig=BCM2708_I2S_GPIO_PIN18; - } else { - -From fc1f587ff7f9a2f49cb8a320569a76e827027cb8 Mon Sep 17 00:00:00 2001 -From: Julian Scheel -Date: Thu, 14 Aug 2014 08:40:24 +0200 -Subject: [PATCH 93/94] bcm2708: Add extension to configure internal pulls - -The bcm2708 gpio controller supports internal pulls to be used as pull-up, -pull-down or being entirely disabled. As it can be useful for a driver to -change the pull configuration from it's default pull-down state, add an -extension which allows configuring the pull per gpio. - -Signed-off-by: Julian Scheel ---- - arch/arm/mach-bcm2708/bcm2708_gpio.c | 38 +++++++++++++++++++++++++++++++++++ - include/linux/platform_data/bcm2708.h | 23 +++++++++++++++++++++ - 2 files changed, 61 insertions(+) - create mode 100644 include/linux/platform_data/bcm2708.h - -diff --git a/arch/arm/mach-bcm2708/bcm2708_gpio.c b/arch/arm/mach-bcm2708/bcm2708_gpio.c -index 5fb845a..86cafa7 100644 ---- a/arch/arm/mach-bcm2708/bcm2708_gpio.c -+++ b/arch/arm/mach-bcm2708/bcm2708_gpio.c -@@ -11,6 +11,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -21,6 +22,8 @@ - #include - #include - -+#include ++static struct regulator_consumer_supply dc5v_consumers[] = { ++ REGULATOR_SUPPLY("SPKVDDL", "wm5102-codec"), ++ REGULATOR_SUPPLY("SPKVDDR", "wm5102-codec"), ++}; + - #define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" - #define DRIVER_NAME BCM_GPIO_DRIVER_NAME - #define BCM_GPIO_USE_IRQ 1 -@@ -131,6 +134,41 @@ static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value) - writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank)); - } - -+/********************** -+ * extension to configure pullups -+ */ -+int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset, -+ bcm2708_gpio_pull_t value) -+{ -+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); -+ unsigned gpio_bank = offset / 32; -+ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++static struct regulator_init_data dc5v_data = { ++ .constraints = { ++ .always_on = 1, ++ }, ++ .num_consumer_supplies = ARRAY_SIZE(dc5v_consumers), ++ .consumer_supplies = dc5v_consumers, ++}; + -+ if (offset >= BCM2708_NR_GPIOS) -+ return -EINVAL; ++static struct fixed_voltage_config dc5vvdd_pdata = { ++ .supply_name = "DC_5V", ++ .microvolts = 5000000, ++ .init_data = &dc5v_data, ++ .gpio = -1, ++}; + -+ switch (value) { -+ case BCM2708_PULL_UP: -+ writel(2, gpio->base + GPIOUD(0)); -+ break; -+ case BCM2708_PULL_DOWN: -+ writel(1, gpio->base + GPIOUD(0)); -+ break; -+ case BCM2708_PULL_OFF: -+ writel(0, gpio->base + GPIOUD(0)); -+ break; ++static struct platform_device dc5v_device = { ++ .name = "reg-fixed-voltage", ++ .id = 1, ++ .dev = { ++ .platform_data = &dc5vvdd_pdata, ++ }, ++}; ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_RPI_CODEC_WSP_MODULE) || defined(CONFIG_SND_BCM2708_SOC_RPI_CODEC_WSP) ++#include ++ ++static struct resource bcm2708_clock_resources[] = { ++ { ++ .start = GPIO_BASE, ++ .end = GPIO_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = GPxCLT_BASE, ++ .end = GPxCLT_BASE + 0x14, ++ .flags = IORESOURCE_MEM, + } ++}; + -+ udelay(5); -+ writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank)); -+ udelay(5); -+ writel(0, gpio->base + GPIOUD(0)); -+ writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank)); ++static struct platform_device snd_rpi_wsp_device = { ++ .name = "snd-rpi-wsp", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_clock_resources), ++ .resource = bcm2708_clock_resources, ++}; + -+ return 0; -+} -+EXPORT_SYMBOL(bcm2708_gpio_setpull); ++static struct arizona_micd_config wm5102_micd[] = { ++ { 0, 1 << ARIZONA_MICD_BIAS_SRC_SHIFT, 0 }, ++}; + - /************************************************************************************************************************* - * bcm2708 GPIO IRQ - */ -diff --git a/include/linux/platform_data/bcm2708.h b/include/linux/platform_data/bcm2708.h ++static struct arizona_pdata snd_rpi_wsp_spi_platform_data = { ++ .reset = GPIO_WM5102_RST, ++ .ldoena = GPIO_WM5102_LDOEN, ++ .irq_flags = IRQF_TRIGGER_HIGH, ++ .gpio_defaults = { ++ [2] = 0x04, /* OPCLK */ ++ [3] = 0x3d, /* ASYNC OPCLK */ ++ }, ++ .micd_configs = wm5102_micd, ++ .num_micd_configs = ARRAY_SIZE(wm5102_micd), ++ .dmic_ref = { ++ [1] = ARIZONA_DMIC_MICBIAS2, ++ }, ++ .inmode = { ++ [1] = ARIZONA_INMODE_DMIC, ++ [2] = ARIZONA_INMODE_SE, ++ }, ++ .clk32k_src = ARIZONA_32KZ_NONE, ++}; ++ ++static struct spi_board_info __initdata snd_rpi_wsp_spi_devices[] = { ++ { ++ .modalias = "wm5102", ++ .platform_data = &snd_rpi_wsp_spi_platform_data, ++ .max_speed_hz = 500000, ++ .bus_num = 0, ++ .chip_select = 1, ++ .mode = SPI_MODE_0, ++ .irq = GPIO_WM5102_IRQ, ++ } ++}; ++ ++static struct i2c_board_info __initdata snd_rpi_wsp_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("wm8804", 0x3A), ++ }, ++}; ++ ++#endif ++ + #if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE) + static struct platform_device snd_hifiberry_dac_device = { + .name = "snd-hifiberry-dac", +@@ -864,7 +1003,7 @@ void __init bcm2708_init(void) + bcm_register_device(&bcm2835_hwmon_device); + bcm_register_device(&bcm2835_thermal_device); + +-#ifdef CONFIG_SND_BCM2708_SOC_I2S_MODULE ++#if defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE) || defined(CONFIG_SND_BCM2708_SOC_I2S) + bcm_register_device(&bcm2708_i2s_device); + #endif + +@@ -899,6 +1038,17 @@ void __init bcm2708_init(void) + i2c_register_board_info(1, snd_pcm512x_i2c_devices, ARRAY_SIZE(snd_pcm512x_i2c_devices)); + #endif + ++#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE) ++ bcm_register_device(&dc1v8_device); ++ bcm_register_device(&dc5v_device); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_RPI_CODEC_WSP_MODULE) || defined(CONFIG_SND_BCM2708_SOC_RPI_CODEC_WSP) ++ bcm_register_device(&snd_rpi_wsp_device); ++ spi_register_board_info(snd_rpi_wsp_spi_devices, ARRAY_SIZE(snd_rpi_wsp_spi_devices)); ++ i2c_register_board_info(1, snd_rpi_wsp_i2c_devices, ++ ARRAY_SIZE(snd_rpi_wsp_i2c_devices)); ++#endif + + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; +diff --git a/arch/arm/mach-bcm2708/include/mach/platform.h b/arch/arm/mach-bcm2708/include/mach/platform.h +index 2e7e1bb..af6bc91 100644 +--- a/arch/arm/mach-bcm2708/include/mach/platform.h ++++ b/arch/arm/mach-bcm2708/include/mach/platform.h +@@ -62,6 +62,7 @@ + #define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */ + #define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */ + #define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */ ++#define GPxCLT_BASE (BCM2708_PERI_BASE + 0x101070) /* Clock Manager General Purpose Clocks Control */ + #define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */ + #define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */ + #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */ + +From 02264312a27efec56d3ea541fa26bb91ec173fa6 Mon Sep 17 00:00:00 2001 +From: Nikesh Oswal +Date: Tue, 19 Aug 2014 16:02:53 +0100 +Subject: [PATCH 75/82] ASOC: RPI : Add support for Wolfson Audio Card + +Support for Wolfson Audio Card.Added the machine driver. + +Signed-off-by: Nikesh Oswal +Signed-off-by: Manish Gupta +Signed-off-by: ajit.pandey +--- + sound/soc/bcm/Kconfig | 8 + + sound/soc/bcm/Makefile | 2 + + sound/soc/bcm/rpi-wolfson-sound-pi.c | 806 +++++++++++++++++++++++++++++++++++ + 3 files changed, 816 insertions(+) + create mode 100644 sound/soc/bcm/rpi-wolfson-sound-pi.c + +diff --git a/sound/soc/bcm/Kconfig b/sound/soc/bcm/Kconfig +index a562ddf..d97eb34 100644 +--- a/sound/soc/bcm/Kconfig ++++ b/sound/soc/bcm/Kconfig +@@ -60,3 +60,11 @@ config SND_BCM2708_SOC_IQAUDIO_DAC + select SND_SOC_PCM512x_I2C + help + Say Y or M if you want to add support for IQaudIO-DAC. ++ ++config SND_BCM2708_SOC_RPI_CODEC_WSP ++ tristate "Support for Wolfson sound pi" ++ depends on SND_BCM2708_SOC_I2S ++ select SND_SOC_WM5102 ++ select SND_SOC_WM8804 ++ help ++ Say Y if you want to add support for Wolfson sound pi +diff --git a/sound/soc/bcm/Makefile b/sound/soc/bcm/Makefile +index 17ea2b0..feec9b5 100644 +--- a/sound/soc/bcm/Makefile ++++ b/sound/soc/bcm/Makefile +@@ -15,6 +15,7 @@ snd-soc-hifiberry-digi-objs := hifiberry_digi.o + snd-soc-hifiberry-amp-objs := hifiberry_amp.o + snd-soc-rpi-dac-objs := rpi-dac.o + snd-soc-iqaudio-dac-objs := iqaudio-dac.o ++snd-soc-rpi-wsp-objs := rpi-wolfson-sound-pi.o + + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o +@@ -22,3 +23,4 @@ obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o + obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o + obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o + obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o ++obj-$(CONFIG_SND_BCM2708_SOC_RPI_CODEC_WSP) += snd-soc-rpi-wsp.o +diff --git a/sound/soc/bcm/rpi-wolfson-sound-pi.c b/sound/soc/bcm/rpi-wolfson-sound-pi.c new file mode 100644 -index 0000000..fb69624 +index 0000000..40e04fd --- /dev/null -+++ b/include/linux/platform_data/bcm2708.h -@@ -0,0 +1,23 @@ ++++ b/sound/soc/bcm/rpi-wolfson-sound-pi.c +@@ -0,0 +1,806 @@ +/* -+ * include/linux/platform_data/bcm2708.h ++ * ASoC machine driver for Wolfson Audio Card (with a WM5102 and WM8804 codecs ) ++ * connected to a Raspberry Pi ++ * ++ * Author: Nikesh Oswal, ++ * Copyright 2013/2014 ++ * ++ * Author: Florian Meier, ++ * Copyright 2013 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. -+ * -+ * (C) 2014 Julian Scheel -+ * + */ -+#ifndef __BCM2708_H_ -+#define __BCM2708_H_ + -+typedef enum { -+ BCM2708_PULL_OFF, -+ BCM2708_PULL_UP, -+ BCM2708_PULL_DOWN -+} bcm2708_gpio_pull_t; ++#include ++#include + -+extern int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset, -+ bcm2708_gpio_pull_t value); ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include + -+#endif ++#include "../codecs/wm5102.h" ++#include "../codecs/wm8804.h" ++ ++#define WM8804_CLKOUT_HZ 12000000 ++#define RPI_WSP_DEFAULT_MCLK2 24000000 ++ ++/*TODO: Shift this to platform data*/ ++#define GPIO_WM8804_RST 8 ++#define GPIO_WM8804_MODE 2 ++#define GPIO_WM8804_SW_MODE 23 ++#define GPIO_WM8804_I2C_ADDR 18 ++#define RPI_WLF_SR 44100 ++#define WM5102_MAX_SYSCLK_1 49152000 /*max sysclk for 4K family*/ ++#define WM5102_MAX_SYSCLK_2 45158400 /*max sysclk for 11.025K family*/ ++ ++static struct snd_soc_card snd_rpi_wsp; ++ ++struct wm5102_machine_priv { ++ void __iomem *gpio_base; ++ void __iomem *gpctl_base; ++ struct snd_soc_codec *codec; ++ struct snd_soc_dai *aif[3]; ++ int aif1rate; ++ int wm8804_sr; ++}; ++ ++/* Output clock from GPIO_GCLK(GPIO4) */ ++#define GPIOFSEL(x) (0x00+(x)*4) ++#define GP0CTL (0x00) ++#define GP0DIV (0x04) ++ ++/* Clock register settings */ ++#define BCM2708_CLK_PASSWD (0x5a000000) ++#define BCM2708_CLK_MASH(v) ((v) << 9) ++#define BCM2708_CLK_FLIP (1 << 8) ++#define BCM2708_CLK_BUSY (1 << 7) ++#define BCM2708_CLK_KILL (1 << 5) ++#define BCM2708_CLK_ENAB (1 << 4) ++#define BCM2708_CLK_SRC(v) (v) ++ ++#define BCM2708_CLK_DIVI(v) ((v) << 12) ++#define BCM2708_CLK_DIVF(v) (v) ++ ++static inline void bcm2708_gpio_write_reg(struct wm5102_machine_priv *dev, ++ int reg, u32 val) ++{ ++ __raw_writel(val, dev->gpio_base + reg); ++} ++ ++static inline u32 bcm2708_gpio_read_reg(struct wm5102_machine_priv *dev, int reg) ++{ ++ return __raw_readl(dev->gpio_base + reg); ++} ++ ++static inline void bcm2708_gpctl_write_reg(struct wm5102_machine_priv *dev, ++ int reg, u32 val) ++{ ++ __raw_writel(val, dev->gpctl_base + reg); ++} ++ ++static inline u32 bcm2708_gpctl_read_reg(struct wm5102_machine_priv *dev, int reg) ++{ ++ return __raw_readl(dev->gpctl_base + reg); ++} ++ ++enum { ++ GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT, ++ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4, ++ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1, ++ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3, ++}; ++ ++struct GPCTL { ++ char SRC : 4; ++ char ENAB : 1; ++ char KILL : 1; ++ char : 1; ++ char BUSY : 1; ++ char FLIP : 1; ++ char MASH : 2; ++ unsigned int : 13; ++ char PASSWD : 8; ++}; ++ ++enum { ++ BCM2708_CLK_MASH_0 = 0, ++ BCM2708_CLK_MASH_1, ++ BCM2708_CLK_MASH_2, ++ BCM2708_CLK_MASH_3, ++}; ++ ++enum { ++ BCM2708_CLK_SRC_GND = 0, ++ BCM2708_CLK_SRC_OSC, ++ BCM2708_CLK_SRC_DBG0, ++ BCM2708_CLK_SRC_DBG1, ++ BCM2708_CLK_SRC_PLLA, ++ BCM2708_CLK_SRC_PLLC, ++ BCM2708_CLK_SRC_PLLD, ++ BCM2708_CLK_SRC_HDMI, ++}; ++ ++/* Most clocks are not useable (freq = 0) */ ++static const unsigned int bcm2708_clk_freq[BCM2708_CLK_SRC_HDMI+1] = { ++ [BCM2708_CLK_SRC_GND] = 0, ++ [BCM2708_CLK_SRC_OSC] = 19200000, ++ [BCM2708_CLK_SRC_DBG0] = 0, ++ [BCM2708_CLK_SRC_DBG1] = 0, ++ [BCM2708_CLK_SRC_PLLA] = 0, ++ [BCM2708_CLK_SRC_PLLC] = 0, ++ [BCM2708_CLK_SRC_PLLD] = 500000000, ++ [BCM2708_CLK_SRC_HDMI] = 0, ++}; ++ ++static void gpio_gclk_init(void) ++{ ++ unsigned gpiodir; ++ struct snd_soc_card *card = &snd_rpi_wsp; ++ struct wm5102_machine_priv *wm5102 = snd_soc_card_get_drvdata(card); ++ ++ gpiodir = bcm2708_gpio_read_reg(wm5102, GPIOFSEL(0)); ++ gpiodir &= ~(7 << 12); ++ gpiodir |= GPIO_FSEL_ALT0 << 12; ++ bcm2708_gpio_write_reg(wm5102, GPIOFSEL(0), gpiodir); ++} ++ ++static void set_gclk_clock_rate(int clock_rate) ++{ ++ struct snd_soc_card *card = &snd_rpi_wsp; ++ struct wm5102_machine_priv *wm5102 = snd_soc_card_get_drvdata(card); ++ unsigned int mash = BCM2708_CLK_MASH_1; ++ int clk_src = -1; ++ uint64_t dividend; ++ unsigned int divi, divf; ++ ++ clk_src = BCM2708_CLK_SRC_PLLD; ++ ++ dividend = bcm2708_clk_freq[clk_src]; ++ dividend *= 1024; ++ do_div(dividend, clock_rate); ++ divi = dividend / 1024; ++ divf = dividend % 1024; ++ dev_dbg(wm5102->codec->dev, "divi %d, divf %d\n", divi, divf); ++ ++ /* Set clock divider */ ++ bcm2708_gpctl_write_reg(wm5102, GP0DIV, BCM2708_CLK_PASSWD ++ | BCM2708_CLK_DIVI(divi) ++ | BCM2708_CLK_DIVF(divf)); ++ ++ /* Setup clock, but don't start it yet */ ++ bcm2708_gpctl_write_reg(wm5102, GP0CTL, BCM2708_CLK_PASSWD ++ | BCM2708_CLK_MASH(mash) ++ | BCM2708_CLK_SRC(clk_src)); ++} ++ ++static void enable_gclk_clock(bool enable) ++{ ++ unsigned int clkreg; ++ struct snd_soc_card *card = &snd_rpi_wsp; ++ struct wm5102_machine_priv *wm5102 = snd_soc_card_get_drvdata(card); ++ if (enable) { ++ /* start clock*/ ++ clkreg = bcm2708_gpctl_read_reg(wm5102, ++ GP0CTL); ++ bcm2708_gpctl_write_reg(wm5102, GP0CTL, ++ BCM2708_CLK_PASSWD | clkreg | BCM2708_CLK_ENAB); ++ } else { ++ /* stop clock */ ++ clkreg = bcm2708_gpctl_read_reg(wm5102, GP0CTL); ++ bcm2708_gpctl_write_reg(wm5102, GP0CTL, ~(BCM2708_CLK_ENAB) ++ & (BCM2708_CLK_PASSWD | clkreg)); ++ } ++} ++ ++static const struct snd_kcontrol_new rpi_wsp_controls[] = { ++ SOC_DAPM_PIN_SWITCH("DMIC"), ++ SOC_DAPM_PIN_SWITCH("Headset Mic"), ++ SOC_DAPM_PIN_SWITCH("SPDIF out"), ++ SOC_DAPM_PIN_SWITCH("SPDIF in"), ++}; ++ ++const struct snd_soc_dapm_widget rpi_wsp_dapm_widgets[] = { ++ SND_SOC_DAPM_MIC("DMIC", NULL), ++ SND_SOC_DAPM_MIC("Headset Mic", NULL), ++ SND_SOC_DAPM_MIC("Line Input", NULL), ++ /* Create widgets for SPDIF output and input */ ++ SND_SOC_DAPM_OUTPUT("SPDIF out"), ++ SND_SOC_DAPM_INPUT("SPDIF in"), ++}; ++ ++const struct snd_soc_dapm_route rpi_wsp_dapm_routes[] = { ++ { "IN1L", NULL, "Headset Mic" }, ++ { "IN1R", NULL, "Headset Mic" }, ++ { "Headset Mic", NULL, "MICBIAS1" }, ++ ++ { "IN2L", NULL, "DMIC" }, ++ { "IN2R", NULL, "DMIC" }, ++ { "DMIC", NULL, "MICBIAS2" }, ++ ++ { "IN3L", NULL, "Line Input" }, ++ { "IN3R", NULL, "Line Input" }, ++ { "Line Input", NULL, "MICVDD" }, ++ ++ { "SPDIF out", NULL, "Playback" }, ++ { "Capture", NULL, "SPDIF in" }, ++ { "SYSCLK", NULL, "OPCLK" }, ++ { "ASYNCCLK", NULL, "ASYNCOPCLK" }, ++}; ++static int rpi_set_bias_level(struct snd_soc_card *card, ++ struct snd_soc_dapm_context *dapm, ++ enum snd_soc_bias_level level) ++{ ++ struct snd_soc_codec *wm8804_codec = card->rtd[1].codec; ++ ++ switch (level) { ++ case SND_SOC_BIAS_STANDBY: ++ if (dapm->bias_level != SND_SOC_BIAS_OFF) ++ break; ++ ++ snd_soc_update_bits(wm8804_codec, WM8804_PWRDN, 0x8, 0x0); ++ break; ++ case SND_SOC_BIAS_PREPARE: ++ if (dapm->bias_level != SND_SOC_BIAS_STANDBY) ++ break; ++ ++ snd_soc_update_bits(wm8804_codec, WM8804_PWRDN, 0x1, 0x0); ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++static int rpi_set_bias_level_post(struct snd_soc_card *card, ++ struct snd_soc_dapm_context *dapm, ++ enum snd_soc_bias_level level) ++{ ++ struct snd_soc_codec *wm8804_codec = card->rtd[1].codec; ++ ++ switch (level) { ++ case SND_SOC_BIAS_OFF: ++ snd_soc_update_bits(wm8804_codec, WM8804_PWRDN, 0x8, 0x8); ++ break; ++ case SND_SOC_BIAS_STANDBY: ++ snd_soc_update_bits(wm8804_codec, WM8804_PWRDN, 0x1, 0x1); ++ break; ++ default: ++ break; ++ } ++ ++ dapm->bias_level = level; ++ ++ return 0; ++} ++static void bcm2708_set_gpio_out(int pin) ++{ ++ /* ++ * This is the common way to handle the GPIO pins for ++ * the Raspberry Pi. ++ * TODO This is a hack. Use pinmux / pinctrl. ++ */ ++#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3)) ++#define SET_GPIO_OUT(g) *(gpio+(((g)/10))) |= (1<<(((g)%10)*3)) ++ unsigned int *gpio; ++ gpio = ioremap(GPIO_BASE, SZ_16K); ++ INP_GPIO(pin); ++ SET_GPIO_OUT(pin); ++ iounmap(gpio); ++#undef INP_GPIO ++#undef SET_GPIO_OUT ++ ++} ++ ++static void bcm2708_set_gpio_alt(int pin, int alt) ++{ ++ /* ++ * This is the common way to handle the GPIO pins for ++ * the Raspberry Pi. ++ * TODO This is a hack. Use pinmux / pinctrl. ++ */ ++#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3)) ++#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) ++ unsigned int *gpio; ++ gpio = ioremap(GPIO_BASE, SZ_16K); ++ INP_GPIO(pin); ++ SET_GPIO_ALT(pin, alt); ++ iounmap(gpio); ++#undef INP_GPIO ++#undef SET_GPIO_ALT ++} ++ ++static int wm8804_reset(void) ++ { ++ int ret; ++ ++ if (!gpio_is_valid(GPIO_WM8804_RST)) { ++ pr_err("Skipping unavailable gpio %d (%s)\n", GPIO_WM8804_RST, "wm8804_rst"); ++ return -ENOMEM; ++ } ++ ++ if (!gpio_is_valid(GPIO_WM8804_MODE)) { ++ pr_err("Skipping unavailable gpio %d (%s)\n", GPIO_WM8804_MODE, "wm8804_mode"); ++ return -ENOMEM; ++ } ++ ++ if (!gpio_is_valid(GPIO_WM8804_SW_MODE)) { ++ pr_err("Skipping unavailable gpio %d (%s)\n", GPIO_WM8804_SW_MODE, "wm8804_sw_mode"); ++ return -ENOMEM; ++ } ++ ++ if (!gpio_is_valid(GPIO_WM8804_I2C_ADDR)) { ++ pr_err("Skipping unavailable gpio %d (%s)\n", GPIO_WM8804_I2C_ADDR, "wm8804_i2c_addr"); ++ return -ENOMEM; ++ } ++ ++ ret = gpio_request(GPIO_WM8804_RST, "wm8804_rst"); ++ if (ret < 0) { ++ pr_err("gpio_request wm8804_rst failed\n"); ++ return ret; ++ } ++ ++ /*GPIO2 is used for SW/HW Mode Select and after Reset the same pin is used as ++ I2C data line, so initially it is configured as GPIO OUT from BCM perspective*/ ++ bcm2708_set_gpio_out(GPIO_WM8804_MODE); ++ ++ ret = gpio_request(GPIO_WM8804_MODE, "wm8804_mode"); ++ if (ret < 0) { ++ pr_err("gpio_request wm8804_mode failed\n"); ++ return ret; ++ } ++ ++ ret = gpio_request(GPIO_WM8804_SW_MODE, "wm8804_sw_mode"); ++ if (ret < 0) { ++ pr_err("gpio_request wm8804_sw_mode failed\n"); ++ return ret; ++ } ++ ++ ret = gpio_request(GPIO_WM8804_I2C_ADDR, "wm8804_i2c_addr"); ++ if (ret < 0) { ++ pr_err("gpio_request wm8804_i2c_addr failed\n"); ++ return ret; ++ } ++ ++ /*Set SW Mode*/ ++ ret = gpio_direction_output(GPIO_WM8804_MODE, 1); ++ if (ret < 0) { ++ pr_err("gpio_direction_output wm8804_mode failed\n"); ++ } ++ ++ /*Set 2 Wire (I2C) Mode*/ ++ ret = gpio_direction_output(GPIO_WM8804_SW_MODE, 0); ++ if (ret < 0) { ++ pr_err("gpio_direction_output wm8804_sw_mode failed\n"); ++ } ++ ++ /*Set 2 Wire (I2C) Addr to 0x3A, writing 1 will make the Addr as 0x3B*/ ++ ret = gpio_direction_output(GPIO_WM8804_I2C_ADDR, 0); ++ if (ret < 0) { ++ pr_err("gpio_direction_output wm8804_i2c_addr failed\n"); ++ } ++ ++ /*Take WM8804 out of reset*/ ++ ret = gpio_direction_output(GPIO_WM8804_RST, 1); ++ if (ret < 0) { ++ pr_err("gpio_direction_output wm8804_rst failed\n"); ++ } ++ ++ /*Put WM8804 in reset*/ ++ gpio_set_value(GPIO_WM8804_RST, 0); ++ mdelay(500); ++ /*Take WM8804 out of reset*/ ++ gpio_set_value(GPIO_WM8804_RST, 1); ++ mdelay(500); ++ ++ gpio_free(GPIO_WM8804_RST); ++ gpio_free(GPIO_WM8804_MODE); ++ gpio_free(GPIO_WM8804_SW_MODE); ++ gpio_free(GPIO_WM8804_I2C_ADDR); ++ ++ /*GPIO2 is used for SW/HW Mode Select and after Reset the same pin is used as ++ I2C data line, so after reset it is configured as I2C data line i.e ALT0 function*/ ++ bcm2708_set_gpio_alt(GPIO_WM8804_MODE, 0); ++ ++ return ret; ++} ++ ++static int snd_rpi_wsp_config_5102_clks(struct snd_soc_codec *wm5102_codec, int sr, bool enable_fllsync) ++{ ++ int ret; ++ int sr_mult = (sr % 4000 == 0) ? (WM5102_MAX_SYSCLK_1/sr) : (WM5102_MAX_SYSCLK_2/sr); ++ ++ /*reset FLL1*/ ++ snd_soc_codec_set_pll(wm5102_codec, WM5102_FLL1_REFCLK, ++ ARIZONA_FLL_SRC_NONE, 0, 0); ++ snd_soc_codec_set_pll(wm5102_codec, WM5102_FLL1, ++ ARIZONA_FLL_SRC_NONE, 0, 0); ++ ++ if (enable_fllsync) { ++ ret = snd_soc_codec_set_pll(wm5102_codec, WM5102_FLL1_REFCLK, ++ ARIZONA_CLK_SRC_MCLK1, ++ WM8804_CLKOUT_HZ, ++ sr * sr_mult); ++ if (ret != 0) { ++ dev_err(wm5102_codec->dev, "Failed to enable FLL1 with Ref Clock Loop: %d\n", ret); ++ return ret; ++ } ++ ++ ret = snd_soc_codec_set_pll(wm5102_codec, WM5102_FLL1, ++ ARIZONA_CLK_SRC_AIF2BCLK, ++ sr * 64, sr * sr_mult); ++ if (ret != 0) { ++ dev_err(wm5102_codec->dev, "Failed to enable FLL1 Sync Clock Loop: %d\n", ret); ++ return ret; ++ } ++ } else { ++ ret = snd_soc_codec_set_pll(wm5102_codec, WM5102_FLL1, ++ ARIZONA_CLK_SRC_MCLK1, ++ WM8804_CLKOUT_HZ, ++ sr * sr_mult); ++ if (ret != 0) { ++ dev_err(wm5102_codec->dev, "Failed to enable FLL1 with Ref Clock Loop: %d\n", ret); ++ return ret; ++ } ++ } ++ ++ ret = snd_soc_codec_set_sysclk(wm5102_codec, ++ ARIZONA_CLK_SYSCLK, ++ ARIZONA_CLK_SRC_FLL1, ++ sr * sr_mult, ++ SND_SOC_CLOCK_IN); ++ if (ret != 0) { ++ dev_err(wm5102_codec->dev, "Failed to set AYNCCLK: %d\n", ret); ++ return ret; ++ } ++ ++ ret = snd_soc_codec_set_sysclk(wm5102_codec, ++ ARIZONA_CLK_OPCLK, 0, ++ sr * sr_mult, ++ SND_SOC_CLOCK_OUT); ++ if (ret != 0) { ++ dev_err(wm5102_codec->dev, "Failed to set OPCLK: %d\n", ret); ++ return ret; ++ } ++ ++ return 0; ++ } ++ ++static int snd_rpi_wsp_config_8804_clks(struct snd_soc_codec *wm8804_codec, ++ struct snd_soc_dai *wm8804_dai, int sr) ++ { ++ int ret; ++ ++ /*Set OSC(12MHz) to CLK2 freq*/ ++ /*Based on MCLKDIV it will be 128fs (MCLKDIV=1) or 256fs mode (MCLKDIV=0)*/ ++ /*BCLK will be MCLK/2 (MCLKDIV=1) or MCLK/4 (MCLKDIV=0) so BCLK is 64fs always*/ ++ ret = snd_soc_dai_set_pll(wm8804_dai, 0, 0, WM8804_CLKOUT_HZ, sr * 256); ++ if (ret != 0) { ++ dev_err(wm8804_codec->dev, "Failed to set OSC to CLK2 frequency: %d\n", ret); ++ return ret; ++ } ++ ++ /*Set MCLK as PLL Output*/ ++ ret = snd_soc_dai_set_sysclk(wm8804_dai, WM8804_TX_CLKSRC_PLL, sr * 256, 0); ++ if (ret != 0) { ++ dev_err(wm8804_codec->dev, "Failed to set MCLK as PLL Output: %d\n", ret); ++ return ret; ++ } ++ ++ /*Fix MCLKDIV=0 for 256fs to avoid any issues switching between TX and RX. RX always expects 256fs*/ ++ ret = snd_soc_dai_set_clkdiv(wm8804_dai, WM8804_MCLK_DIV, 0 ); ++ if (ret != 0) { ++ dev_err(wm8804_codec->dev, "Failed to set MCLK_DIV to 256fs: %d\n", ret); ++ return ret; ++ } ++ ++ /*Set CLKOUT as OSC Frequency*/ ++ ret = snd_soc_dai_set_sysclk(wm8804_dai, WM8804_CLKOUT_SRC_OSCCLK, WM8804_CLKOUT_HZ, 0); ++ if (ret != 0) { ++ dev_err(wm8804_codec->dev, "Failed to set CLKOUT as OSC Frequency: %d\n", ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int snd_rpi_wsp_config_clks(struct snd_soc_codec *wm8804_codec, ++ struct snd_soc_codec *wm5102_codec, struct snd_soc_dai *wm8804_dai, ++ int sr, bool enable_fllsync,int wm8804_rxtx_status) ++{ ++ int ret=0,rx_disabled,tx_disabled; ++ ++ rx_disabled = wm8804_rxtx_status & 0x2; ++ tx_disabled = wm8804_rxtx_status & 0x4; ++ ++ if(!rx_disabled || !tx_disabled){ ++ ret = snd_rpi_wsp_config_8804_clks(wm8804_codec, wm8804_dai,sr); ++ ++ if (ret != 0) { ++ dev_err(wm8804_codec->dev, "snd_rpi_wsp_config_8804_clks failed: %d\n", ret); ++ return ret; ++ } ++ ++ } ++ ++ ret = snd_rpi_wsp_config_5102_clks(wm5102_codec, sr, enable_fllsync); ++ if (ret != 0) { ++ dev_err(wm5102_codec->dev, "snd_rpi_wsp_config_5102_clks failed: %d\n", ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int snd_rpi_wsp_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_card *card = rtd->card; ++ struct snd_soc_codec *wm5102_codec = rtd->codec; ++ struct snd_soc_dai *bcm_i2s_dai = rtd->cpu_dai; ++ struct snd_soc_codec *wm8804_codec = card->rtd[1].codec; ++ struct snd_soc_dai *wm8804_codec_dai = card->rtd[1].codec_dai; ++ struct wm5102_machine_priv *priv = snd_soc_card_get_drvdata(card); ++ int ret, rxtx_status,rx_disabled,capture_stream_opened; ++ bool enable_fllsync; ++ unsigned int bclkratio; ++ ++ bclkratio = 2 * snd_pcm_format_physical_width(params_format(params)); ++ if (bcm_i2s_dai->driver->ops->set_bclk_ratio) { ++ ret = bcm_i2s_dai->driver->ops->set_bclk_ratio(bcm_i2s_dai, bclkratio); ++ if (ret < 0) { ++ dev_err(wm5102_codec->dev, "set_bclk_ratio failed: %d\n", ret); ++ return ret; ++ } ++ } ++ ++ rxtx_status = snd_soc_read(wm8804_codec, WM8804_PWRDN); ++ rx_disabled = rxtx_status & 0x2; ++ ++ capture_stream_opened = ++ substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream_opened; ++ ++ if (capture_stream_opened && !rx_disabled) ++ enable_fllsync = true; ++ else ++ enable_fllsync = false; ++ ++ ++ ret = snd_rpi_wsp_config_clks(wm8804_codec, wm5102_codec, ++ wm8804_codec_dai, ++ params_rate(params), ++ enable_fllsync, ++ rxtx_status); ++ ++ priv->wm8804_sr = params_rate(params); ++ ++ return 0; ++} ++ ++static int snd_rpi_wsp_hw_free(struct snd_pcm_substream *substream) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *wm5102_codec = rtd->codec; ++ int ret,playback_stream_opened,capture_stream_opened; ++ ++ playback_stream_opened = substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream_opened; ++ ++ capture_stream_opened = substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream_opened; ++ ++ if((playback_stream_opened + capture_stream_opened) == 1){ ++ ++ ret = snd_soc_codec_set_sysclk(wm5102_codec, ++ ARIZONA_CLK_SYSCLK, ++ ARIZONA_CLK_SRC_FLL1, ++ 0, ++ SND_SOC_CLOCK_IN); ++ ++ if (ret != 0) { ++ dev_err(wm5102_codec->dev, "Failed to set SYSCLK to Zero: %d\n", ret); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static struct snd_soc_ops snd_rpi_wsp_ops = { ++ .hw_params = snd_rpi_wsp_hw_params, ++ .hw_free = snd_rpi_wsp_hw_free, ++}; ++ ++static struct snd_soc_pcm_stream dai_link2_params = { ++ .formats = SNDRV_PCM_FMTBIT_S24_LE, ++ .rate_min = RPI_WLF_SR, ++ .rate_max = RPI_WLF_SR, ++ .channels_min = 2, ++ .channels_max = 2, ++}; ++ ++static struct snd_soc_dai_link snd_rpi_wsp_dai[] = { ++ { ++ .name = "WM5102", ++ .stream_name = "WM5102 AiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "wm5102-aif1", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "wm5102-codec", ++ .dai_fmt = SND_SOC_DAIFMT_I2S ++ | SND_SOC_DAIFMT_NB_NF ++ | SND_SOC_DAIFMT_CBM_CFM, ++ .ops = &snd_rpi_wsp_ops, ++ }, ++ { ++ .name = "WM5102 SPDIF", ++ .stream_name = "SPDIF Tx/Rx", ++ .cpu_dai_name = "wm5102-aif2", ++ .codec_dai_name = "wm8804-spdif", ++ .codec_name = "wm8804.1-003a", ++ .dai_fmt = SND_SOC_DAIFMT_I2S ++ | SND_SOC_DAIFMT_NB_NF ++ | SND_SOC_DAIFMT_CBM_CFM, ++ .ignore_suspend = 1, ++ .params = &dai_link2_params, ++ }, ++}; ++ ++static int snd_rpi_wsp_late_probe(struct snd_soc_card *card) ++{ ++ struct snd_soc_codec *codec = card->rtd[0].codec; ++ struct wm5102_machine_priv *priv = snd_soc_card_get_drvdata(codec->card); ++ int i, ret; ++ ++ priv->codec = codec; ++ priv->wm8804_sr = RPI_WLF_SR; ++ ++ for (i = 0; i < ARRAY_SIZE(snd_rpi_wsp_dai); i++) ++ priv->aif[i] = card->rtd[i].codec_dai; ++ ++ ret = snd_soc_codec_set_sysclk(card->rtd[0].codec, ARIZONA_CLK_SYSCLK, ARIZONA_CLK_SRC_FLL1, ++ 0, SND_SOC_CLOCK_IN); ++ if (ret != 0) { ++ dev_err(card->rtd[0].codec->dev, "Failed to set SYSCLK to Zero: %d\n", ret); ++ return ret; ++ } ++ ++ ret = snd_rpi_wsp_config_8804_clks(card->rtd[1].codec, card->rtd[1].codec_dai, RPI_WLF_SR); ++ ++ if (ret != 0) { ++ dev_err(card->rtd[1].codec->dev, "snd_rpi_wsp_config_8804_clks failed: %d\n", ret); ++ return ret; ++ } ++ ++ ret = snd_soc_dai_set_sysclk(card->rtd[0].codec_dai, ARIZONA_CLK_SYSCLK, 0, 0); ++ if (ret != 0) { ++ dev_err(card->rtd[0].codec->dev, "Failed to set codec dai clk domain: %d\n", ret); ++ return ret; ++ } ++ ++ ret = snd_soc_dai_set_sysclk(card->rtd[1].cpu_dai, ARIZONA_CLK_SYSCLK, 0, 0); ++ if (ret != 0) { ++ dev_err(card->rtd[0].codec->dev, "Failed to set codec dai clk domain: %d\n", ret); ++ return ret; ++ } ++ ++ /*Configure SAMPLE_RATE_1 and ASYNC_SAMPLE_RATE_1 by default to ++ 44.1KHz these values can be changed in runtime by corresponding ++ DAI hw_params callback */ ++ snd_soc_update_bits(card->rtd[0].codec, ARIZONA_SAMPLE_RATE_1, ++ ARIZONA_SAMPLE_RATE_1_MASK, 0x0B); ++ snd_soc_update_bits(card->rtd[0].codec, ARIZONA_ASYNC_SAMPLE_RATE_1, ++ ARIZONA_ASYNC_SAMPLE_RATE_MASK, 0x0B); ++ ++ return 0; ++} ++ ++/* audio machine driver */ ++static struct snd_soc_card snd_rpi_wsp = { ++ .name = "snd_rpi_wsp", ++ .dai_link = snd_rpi_wsp_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_wsp_dai), ++ .late_probe = snd_rpi_wsp_late_probe, ++ .controls = rpi_wsp_controls, ++ .num_controls = ARRAY_SIZE(rpi_wsp_controls), ++ .dapm_widgets = rpi_wsp_dapm_widgets, ++ .num_dapm_widgets = ARRAY_SIZE(rpi_wsp_dapm_widgets), ++ .dapm_routes = rpi_wsp_dapm_routes, ++ .num_dapm_routes = ARRAY_SIZE(rpi_wsp_dapm_routes), ++ .set_bias_level = rpi_set_bias_level, ++ .set_bias_level_post = rpi_set_bias_level_post, ++}; ++ ++static int snd_rpi_wsp_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ int i; ++ struct wm5102_machine_priv *wm5102; ++ ++ void __iomem *base[2]; ++ ++ /* request both ioareas */ ++ for (i = 0; i < ARRAY_SIZE(base); i++) { ++ struct resource *mem, *ioarea; ++ mem = platform_get_resource(pdev, IORESOURCE_MEM, i); ++ if (!mem) { ++ dev_err(&pdev->dev, "%s: Memory resource could not be found\n", __func__); ++ return -ENODEV; ++ } ++ ++ ioarea = devm_request_mem_region(&pdev->dev, mem->start, ++ resource_size(mem), ++ pdev->name); ++ if (!ioarea) { ++ dev_err(&pdev->dev, "%s: Memory region already claimed\n", __func__); ++ return -EBUSY; ++ } ++ ++ base[i] = devm_ioremap(&pdev->dev, mem->start, ++ resource_size(mem)); ++ if (!base[i]) { ++ dev_err(&pdev->dev, "%s: ioremap failed\n", __func__); ++ return -ENOMEM; ++ } ++ } ++ ++ wm8804_reset(); ++ ++ wm5102 = kzalloc(sizeof *wm5102, GFP_KERNEL); ++ if (!wm5102) ++ return -ENOMEM; ++ ++ wm5102->gpio_base = base[0]; ++ wm5102->gpctl_base = base[1]; ++ ++ snd_soc_card_set_drvdata(&snd_rpi_wsp, wm5102); ++ ++ gpio_gclk_init(); ++ set_gclk_clock_rate(RPI_WSP_DEFAULT_MCLK2); ++ enable_gclk_clock(true); ++ ++ snd_rpi_wsp.dev = &pdev->dev; ++ ret = snd_soc_register_card(&snd_rpi_wsp); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to register card: %d\n", ret); ++ kfree(wm5102); ++ } ++ ++ return ret; ++} ++ ++static int snd_rpi_wsp_remove(struct platform_device *pdev) ++{ ++ struct snd_soc_card *card = &snd_rpi_wsp; ++ struct wm5102_machine_priv *wm5102 = snd_soc_card_get_drvdata(card); ++ ++ snd_soc_unregister_card(&snd_rpi_wsp); ++ enable_gclk_clock(false); ++ kfree(wm5102); ++ ++ return 0; ++} ++ ++static struct platform_driver snd_rpi_wsp_driver = { ++ .driver = { ++ .name = "snd-rpi-wsp", ++ .owner = THIS_MODULE, ++ }, ++ .probe = snd_rpi_wsp_probe, ++ .remove = snd_rpi_wsp_remove, ++}; ++ ++module_platform_driver(snd_rpi_wsp_driver); ++ ++MODULE_AUTHOR("Nikesh Oswal"); ++MODULE_AUTHOR("Liu Xin"); ++MODULE_DESCRIPTION("ASoC Driver for Raspberry Pi connected to Wolfson sound pi"); ++MODULE_LICENSE("GPL"); -From c40e93792b0d45327ba9d8c2b12dd6382d97d62d Mon Sep 17 00:00:00 2001 -From: Julian Scheel -Date: Thu, 14 Aug 2014 08:42:55 +0200 -Subject: [PATCH 94/94] lirc_rpi: Add parameter to specify input pin pull +From 937f9fd7c8e81ac26e9ea09cfc7b0d1828d9fecc Mon Sep 17 00:00:00 2001 +From: Manish Gupta +Date: Wed, 17 Sep 2014 10:44:19 +0100 +Subject: [PATCH 76/82] config:RPI: Add config support for wolfson audio card -Depending on the connected IR circuitry it might be desirable to change the -gpios internal pull from it pull-down default behaviour. Add a module -parameter to allow the user to set it explicitly. - -Signed-off-by: Julian Scheel +Signed-off-by: Manish Gupta +Signed-off-by: ajit.pandey --- - drivers/staging/media/lirc/lirc_rpi.c | 9 +++++++++ - 1 file changed, 9 insertions(+) + arch/arm/configs/bcmrpi_defconfig | 10 ++++++++++ + 1 file changed, 10 insertions(+) -diff --git a/drivers/staging/media/lirc/lirc_rpi.c b/drivers/staging/media/lirc/lirc_rpi.c -index 1da6a9f..887c36b 100644 ---- a/drivers/staging/media/lirc/lirc_rpi.c -+++ b/drivers/staging/media/lirc/lirc_rpi.c -@@ -41,6 +41,8 @@ - #include - #include +diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig +index 873a32e..ac14ae4 100644 +--- a/arch/arm/configs/bcmrpi_defconfig ++++ b/arch/arm/configs/bcmrpi_defconfig +@@ -538,6 +538,7 @@ CONFIG_SPI=y + CONFIG_SPI_BCM2708=m + CONFIG_SPI_SPIDEV=y + CONFIG_GPIO_SYSFS=y ++CONFIG_GPIO_ARIZONA=m + CONFIG_W1=m + CONFIG_W1_MASTER_DS2490=m + CONFIG_W1_MASTER_DS2482=m +@@ -561,6 +562,12 @@ CONFIG_THERMAL=y + CONFIG_THERMAL_BCM2835=y + CONFIG_WATCHDOG=y + CONFIG_BCM2708_WDT=m ++CONFIG_MFD_ARIZONA_I2C=m ++CONFIG_MFD_ARIZONA_SPI=m ++CONFIG_MFD_WM5102=y ++CONFIG_REGULATOR=y ++CONFIG_REGULATOR_FIXED_VOLTAGE=m ++CONFIG_REGULATOR_ARIZONA=m + CONFIG_MEDIA_SUPPORT=m + CONFIG_MEDIA_CAMERA_SUPPORT=y + CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +@@ -739,6 +746,7 @@ CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m + CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m + CONFIG_SND_BCM2708_SOC_RPI_DAC=m + CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m ++CONFIG_SND_BCM2708_SOC_RPI_CODEC_WSP=m + CONFIG_SND_SIMPLE_CARD=m + CONFIG_SOUND_PRIME=m + CONFIG_HIDRAW=y +@@ -955,6 +963,8 @@ CONFIG_LIRC_RPI=m + CONFIG_LIRC_SASEM=m + CONFIG_LIRC_SERIAL=m + # CONFIG_IOMMU_SUPPORT is not set ++CONFIG_EXTCON=m ++CONFIG_EXTCON_ARIZONA=m + CONFIG_EXT4_FS=y + CONFIG_EXT4_FS_POSIX_ACL=y + CONFIG_EXT4_FS_SECURITY=y + +From 1b50c00bfcdd05f63fb652445c4cde5693fe7144 Mon Sep 17 00:00:00 2001 +From: Manish Gupta +Date: Fri, 26 Sep 2014 16:24:07 +0530 +Subject: [PATCH 77/82] ASoC:RPI: DMA channels 2 and 3 to be set in FAST mode + +Changing th DMA Channels 2 and 3 to be registered under +fast mode and not lite mode.Lite engine mode certainly +half the bandwidth of a normal DMA engine. + +Signed-off-by: Manish Gupta +--- + drivers/dma/bcm2708-dmaengine.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/dma/bcm2708-dmaengine.c b/drivers/dma/bcm2708-dmaengine.c +index 6766799..9ad63e0 100644 +--- a/drivers/dma/bcm2708-dmaengine.c ++++ b/drivers/dma/bcm2708-dmaengine.c +@@ -859,7 +859,7 @@ static int bcm2835_dma_probe(struct platform_device *pdev) + void __iomem *chan_base; + int chan_id; -+#include +- chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_LITE, ++ chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST, + &chan_base, + &irq); + + +From 0fa6b31cec5d82bfffd0762765c82d5d6c1caaac Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Wed, 8 Oct 2014 21:14:48 +0100 +Subject: [PATCH 78/82] ASOC: RPI: Avoid build issue with 3.17 + +--- + sound/soc/bcm/rpi-wolfson-sound-pi.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/sound/soc/bcm/rpi-wolfson-sound-pi.c b/sound/soc/bcm/rpi-wolfson-sound-pi.c +index 40e04fd..900ce3d 100644 +--- a/sound/soc/bcm/rpi-wolfson-sound-pi.c ++++ b/sound/soc/bcm/rpi-wolfson-sound-pi.c +@@ -657,7 +657,7 @@ static struct snd_soc_dai_link snd_rpi_wsp_dai[] = { + static int snd_rpi_wsp_late_probe(struct snd_soc_card *card) + { + struct snd_soc_codec *codec = card->rtd[0].codec; +- struct wm5102_machine_priv *priv = snd_soc_card_get_drvdata(codec->card); ++ struct wm5102_machine_priv *priv = snd_soc_card_get_drvdata(card); + int i, ret; + + priv->codec = codec; + +From d8cd2263493ac6319708b38965ab00aebef358b1 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Thu, 9 Oct 2014 16:12:33 +0100 +Subject: [PATCH 79/82] vchiq: Move logging control into debugfs + +--- + drivers/misc/vc04_services/Makefile | 2 +- + .../vc04_services/interface/vchiq_arm/vchiq_arm.c | 138 +++----- + .../vc04_services/interface/vchiq_arm/vchiq_arm.h | 31 +- + .../interface/vchiq_arm/vchiq_debugfs.c | 383 +++++++++++++++++++++ + .../interface/vchiq_arm/vchiq_debugfs.h | 52 +++ + .../vc04_services/interface/vchiq_arm/vchiq_proc.c | 253 -------------- + 6 files changed, 514 insertions(+), 345 deletions(-) + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c + create mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h + delete mode 100644 drivers/misc/vc04_services/interface/vchiq_arm/vchiq_proc.c + +diff --git a/drivers/misc/vc04_services/Makefile b/drivers/misc/vc04_services/Makefile +index 4224f58..0c82520 100644 +--- a/drivers/misc/vc04_services/Makefile ++++ b/drivers/misc/vc04_services/Makefile +@@ -7,7 +7,7 @@ vchiq-objs := \ + interface/vchiq_arm/vchiq_arm.o \ + interface/vchiq_arm/vchiq_kern_lib.o \ + interface/vchiq_arm/vchiq_2835_arm.o \ +- interface/vchiq_arm/vchiq_proc.o \ ++ interface/vchiq_arm/vchiq_debugfs.o \ + interface/vchiq_arm/vchiq_shim.o \ + interface/vchiq_arm/vchiq_util.o \ + interface/vchiq_arm/vchiq_connected.o \ +diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c +index 98edf1b..dbd530c 100644 +--- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c +@@ -1,4 +1,5 @@ + /** ++ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved. + * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without +@@ -44,12 +45,12 @@ + #include + #include + #include +-#include + + #include "vchiq_core.h" + #include "vchiq_ioctl.h" + #include "vchiq_arm.h" + #include "vchiq_killable.h" ++#include "vchiq_debugfs.h" + + #define DEVICE_NAME "vchiq" + +@@ -105,8 +106,6 @@ static const char *const resume_state_names[] = { + + + static void suspend_timer_callback(unsigned long context); +-static int vchiq_proc_add_instance(VCHIQ_INSTANCE_T instance); +-static void vchiq_proc_remove_instance(VCHIQ_INSTANCE_T instance); + + + typedef struct user_service_struct { +@@ -145,11 +144,12 @@ struct vchiq_instance_struct { + int pid; + int mark; + int use_close_delivered; ++ int trace; + + struct list_head bulk_waiter_list; + struct mutex bulk_waiter_list_mutex; + +- struct proc_dir_entry *proc_entry; ++ VCHIQ_DEBUGFS_NODE_T debugfs_node; + }; + + typedef struct dump_context_struct { +@@ -1135,7 +1135,7 @@ vchiq_open(struct inode *inode, struct file *file) + instance->state = state; + instance->pid = current->tgid; + +- ret = vchiq_proc_add_instance(instance); ++ ret = vchiq_debugfs_add_instance(instance); + if (ret != 0) { + kfree(instance); + return ret; +@@ -1288,7 +1288,7 @@ vchiq_release(struct inode *inode, struct file *file) + } + } + +- vchiq_proc_remove_instance(instance); ++ vchiq_debugfs_remove_instance(instance); + + kfree(instance); + file->private_data = NULL; +@@ -2542,6 +2542,52 @@ vchiq_release_service_internal(VCHIQ_SERVICE_T *service) + return vchiq_release_internal(service->state, service); + } + ++VCHIQ_DEBUGFS_NODE_T * ++vchiq_instance_get_debugfs_node(VCHIQ_INSTANCE_T instance) ++{ ++ return &instance->debugfs_node; ++} + - #define LIRC_DRIVER_NAME "lirc_rpi" - #define RBUF_LEN 256 - #define LIRC_TRANSMITTER_LATENCY 50 -@@ -62,6 +64,8 @@ ++int ++vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_SERVICE_T *service; ++ int use_count = 0, i; ++ i = 0; ++ while ((service = next_service_by_instance(instance->state, ++ instance, &i)) != NULL) { ++ use_count += service->service_use_count; ++ unlock_service(service); ++ } ++ return use_count; ++} ++ ++int ++vchiq_instance_get_pid(VCHIQ_INSTANCE_T instance) ++{ ++ return instance->pid; ++} ++ ++int ++vchiq_instance_get_trace(VCHIQ_INSTANCE_T instance) ++{ ++ return instance->trace; ++} ++ ++void ++vchiq_instance_set_trace(VCHIQ_INSTANCE_T instance, int trace) ++{ ++ VCHIQ_SERVICE_T *service; ++ int i; ++ i = 0; ++ while ((service = next_service_by_instance(instance->state, ++ instance, &i)) != NULL) { ++ service->trace = trace; ++ unlock_service(service); ++ } ++ instance->trace = (trace != 0); ++} ++ + static void suspend_timer_callback(unsigned long context) + { + VCHIQ_STATE_T *state = (VCHIQ_STATE_T *)context; +@@ -2757,10 +2803,10 @@ vchiq_init(void) + int err; + void *ptr_err; - /* set the default GPIO input pin */ - static int gpio_in_pin = 18; -+/* set the default pull behaviour for input pin */ -+static int gpio_in_pull = BCM2708_PULL_DOWN; - /* set the default GPIO output pin */ - static int gpio_out_pin = 17; - /* enable debugging messages */ -@@ -318,6 +322,7 @@ static int init_port(void) - goto exit_gpio_free_out_pin; +- /* create proc entries */ +- err = vchiq_proc_init(); ++ /* create debugfs entries */ ++ err = vchiq_debugfs_init(); + if (err != 0) +- goto failed_proc_init; ++ goto failed_debugfs_init; + + err = alloc_chrdev_region(&vchiq_devid, VCHIQ_MINOR, 1, DEVICE_NAME); + if (err != 0) { +@@ -2810,82 +2856,12 @@ vchiq_init(void) + failed_cdev_add: + unregister_chrdev_region(vchiq_devid, 1); + failed_alloc_chrdev: +- vchiq_proc_deinit(); +-failed_proc_init: ++ vchiq_debugfs_deinit(); ++failed_debugfs_init: + vchiq_log_warning(vchiq_arm_log_level, "could not load vchiq"); + return err; + } + +-static int vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance) +-{ +- VCHIQ_SERVICE_T *service; +- int use_count = 0, i; +- i = 0; +- while ((service = next_service_by_instance(instance->state, +- instance, &i)) != NULL) { +- use_count += service->service_use_count; +- unlock_service(service); +- } +- return use_count; +-} +- +-/* read the per-process use-count */ +-static int proc_read_use_count(char *page, char **start, +- off_t off, int count, +- int *eof, void *data) +-{ +- VCHIQ_INSTANCE_T instance = data; +- int len, use_count; +- +- use_count = vchiq_instance_get_use_count(instance); +- len = snprintf(page+off, count, "%d\n", use_count); +- +- return len; +-} +- +-/* add an instance (process) to the proc entries */ +-static int vchiq_proc_add_instance(VCHIQ_INSTANCE_T instance) +-{ +-#if 1 +- return 0; +-#else +- char pidstr[32]; +- struct proc_dir_entry *top, *use_count; +- struct proc_dir_entry *clients = vchiq_clients_top(); +- int pid = instance->pid; +- +- snprintf(pidstr, sizeof(pidstr), "%d", pid); +- top = proc_mkdir(pidstr, clients); +- if (!top) +- goto fail_top; +- +- use_count = create_proc_read_entry("use_count", +- 0444, top, +- proc_read_use_count, +- instance); +- if (!use_count) +- goto fail_use_count; +- +- instance->proc_entry = top; +- +- return 0; +- +-fail_use_count: +- remove_proc_entry(top->name, clients); +-fail_top: +- return -ENOMEM; +-#endif +-} +- +-static void vchiq_proc_remove_instance(VCHIQ_INSTANCE_T instance) +-{ +-#if 0 +- struct proc_dir_entry *clients = vchiq_clients_top(); +- remove_proc_entry("use_count", instance->proc_entry); +- remove_proc_entry(instance->proc_entry->name, clients); +-#endif +-} +- + /**************************************************************************** + * + * vchiq_exit - called when the module is unloaded. +diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h +index 75ad4c6..d1e2741 100644 +--- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h +@@ -1,4 +1,5 @@ + /** ++ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved. + * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without +@@ -38,6 +39,7 @@ + #include + #include + #include "vchiq_core.h" ++#include "vchiq_debugfs.h" + + + enum vc_suspend_status { +@@ -155,8 +157,7 @@ vchiq_check_resume(VCHIQ_STATE_T *state); + + extern void + vchiq_check_suspend(VCHIQ_STATE_T *state); +- +-extern VCHIQ_STATUS_T ++ VCHIQ_STATUS_T + vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle); + + extern VCHIQ_STATUS_T +@@ -192,21 +193,31 @@ vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, + extern VCHIQ_STATUS_T + vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service); + +-void ++extern VCHIQ_DEBUGFS_NODE_T * ++vchiq_instance_get_debugfs_node(VCHIQ_INSTANCE_T instance); ++ ++extern int ++vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance); ++ ++extern int ++vchiq_instance_get_pid(VCHIQ_INSTANCE_T instance); ++ ++extern int ++vchiq_instance_get_trace(VCHIQ_INSTANCE_T instance); ++ ++extern void ++vchiq_instance_set_trace(VCHIQ_INSTANCE_T instance, int trace); ++ ++extern void + set_suspend_state(VCHIQ_ARM_STATE_T *arm_state, + enum vc_suspend_status new_state); + +-void ++extern void + set_resume_state(VCHIQ_ARM_STATE_T *arm_state, + enum vc_resume_status new_state); + +-void ++extern void + start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state); + +-extern int vchiq_proc_init(void); +-extern void vchiq_proc_deinit(void); +-extern struct proc_dir_entry *vchiq_proc_top(void); +-extern struct proc_dir_entry *vchiq_clients_top(void); +- + + #endif /* VCHIQ_ARM_H */ +diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c +new file mode 100644 +index 0000000..7e03213 +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c +@@ -0,0 +1,383 @@ ++/** ++ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved. ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ ++#include ++#include "vchiq_core.h" ++#include "vchiq_arm.h" ++#include "vchiq_debugfs.h" ++ ++#ifdef CONFIG_DEBUG_FS ++ ++/**************************************************************************** ++* ++* log category entries ++* ++***************************************************************************/ ++#define DEBUGFS_WRITE_BUF_SIZE 256 ++ ++#define VCHIQ_LOG_ERROR_STR "error" ++#define VCHIQ_LOG_WARNING_STR "warning" ++#define VCHIQ_LOG_INFO_STR "info" ++#define VCHIQ_LOG_TRACE_STR "trace" ++ ++ ++/* Top-level debug info */ ++struct vchiq_debugfs_info { ++ /* Global 'vchiq' debugfs entry used by all instances */ ++ struct dentry *vchiq_cfg_dir; ++ ++ /* one entry per client process */ ++ struct dentry *clients; ++ ++ /* log categories */ ++ struct dentry *log_categories; ++}; ++ ++static struct vchiq_debugfs_info debugfs_info; ++ ++/* Log category debugfs entries */ ++struct vchiq_debugfs_log_entry { ++ const char *name; ++ int *plevel; ++ struct dentry *dir; ++}; ++ ++static struct vchiq_debugfs_log_entry vchiq_debugfs_log_entries[] = { ++ { "core", &vchiq_core_log_level }, ++ { "msg", &vchiq_core_msg_log_level }, ++ { "sync", &vchiq_sync_log_level }, ++ { "susp", &vchiq_susp_log_level }, ++ { "arm", &vchiq_arm_log_level }, ++}; ++static int n_log_entries = ++ sizeof(vchiq_debugfs_log_entries)/sizeof(vchiq_debugfs_log_entries[0]); ++ ++ ++static struct dentry *vchiq_clients_top(void); ++static struct dentry *vchiq_debugfs_top(void); ++ ++static int debugfs_log_show(struct seq_file *f, void *offset) ++{ ++ int *levp = f->private; ++ char *log_value = NULL; ++ ++ switch (*levp) { ++ case VCHIQ_LOG_ERROR: ++ log_value = VCHIQ_LOG_ERROR_STR; ++ break; ++ case VCHIQ_LOG_WARNING: ++ log_value = VCHIQ_LOG_WARNING_STR; ++ break; ++ case VCHIQ_LOG_INFO: ++ log_value = VCHIQ_LOG_INFO_STR; ++ break; ++ case VCHIQ_LOG_TRACE: ++ log_value = VCHIQ_LOG_TRACE_STR; ++ break; ++ default: ++ break; ++ } ++ ++ seq_printf(f, "%s\n", log_value ? log_value : "(null)"); ++ ++ return 0; ++} ++ ++static int debugfs_log_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, debugfs_log_show, inode->i_private); ++} ++ ++static int debugfs_log_write(struct file *file, ++ const char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *f = (struct seq_file *)file->private_data; ++ int *levp = f->private; ++ char kbuf[DEBUGFS_WRITE_BUF_SIZE + 1]; ++ ++ memset(kbuf, 0, DEBUGFS_WRITE_BUF_SIZE + 1); ++ if (count >= DEBUGFS_WRITE_BUF_SIZE) ++ count = DEBUGFS_WRITE_BUF_SIZE; ++ ++ if (copy_from_user(kbuf, buffer, count) != 0) ++ return -EFAULT; ++ kbuf[count - 1] = 0; ++ ++ if (strncmp("error", kbuf, strlen("error")) == 0) ++ *levp = VCHIQ_LOG_ERROR; ++ else if (strncmp("warning", kbuf, strlen("warning")) == 0) ++ *levp = VCHIQ_LOG_WARNING; ++ else if (strncmp("info", kbuf, strlen("info")) == 0) ++ *levp = VCHIQ_LOG_INFO; ++ else if (strncmp("trace", kbuf, strlen("trace")) == 0) ++ *levp = VCHIQ_LOG_TRACE; ++ else ++ *levp = VCHIQ_LOG_DEFAULT; ++ ++ *ppos += count; ++ ++ return count; ++} ++ ++static const struct file_operations debugfs_log_fops = { ++ .owner = THIS_MODULE, ++ .open = debugfs_log_open, ++ .write = debugfs_log_write, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++/* create an entry under /vchiq/log for each log category */ ++static int vchiq_debugfs_create_log_entries(struct dentry *top) ++{ ++ struct dentry *dir; ++ size_t i; ++ int ret = 0; ++ dir = debugfs_create_dir("log", vchiq_debugfs_top()); ++ if (!dir) ++ return -ENOMEM; ++ debugfs_info.log_categories = dir; ++ ++ for (i = 0; i < n_log_entries; i++) { ++ void *levp = (void *)vchiq_debugfs_log_entries[i].plevel; ++ dir = debugfs_create_file(vchiq_debugfs_log_entries[i].name, ++ 0644, ++ debugfs_info.log_categories, ++ levp, ++ &debugfs_log_fops); ++ if (!dir) { ++ ret = -ENOMEM; ++ break; ++ } ++ ++ vchiq_debugfs_log_entries[i].dir = dir; ++ } ++ return ret; ++} ++ ++static int debugfs_usecount_show(struct seq_file *f, void *offset) ++{ ++ VCHIQ_INSTANCE_T instance = f->private; ++ int use_count; ++ ++ use_count = vchiq_instance_get_use_count(instance); ++ seq_printf(f, "%d\n", use_count); ++ ++ return 0; ++} ++ ++static int debugfs_usecount_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, debugfs_usecount_show, inode->i_private); ++} ++ ++static const struct file_operations debugfs_usecount_fops = { ++ .owner = THIS_MODULE, ++ .open = debugfs_usecount_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static int debugfs_trace_show(struct seq_file *f, void *offset) ++{ ++ VCHIQ_INSTANCE_T instance = f->private; ++ int trace; ++ ++ trace = vchiq_instance_get_trace(instance); ++ seq_printf(f, "%s\n", trace ? "Y" : "N"); ++ ++ return 0; ++} ++ ++static int debugfs_trace_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, debugfs_trace_show, inode->i_private); ++} ++ ++static int debugfs_trace_write(struct file *file, ++ const char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *f = (struct seq_file *)file->private_data; ++ VCHIQ_INSTANCE_T instance = f->private; ++ char firstchar; ++ ++ if (copy_from_user(&firstchar, buffer, 1) != 0) ++ return -EFAULT; ++ ++ switch (firstchar) { ++ case 'Y': ++ case 'y': ++ case '1': ++ vchiq_instance_set_trace(instance, 1); ++ break; ++ case 'N': ++ case 'n': ++ case '0': ++ vchiq_instance_set_trace(instance, 0); ++ break; ++ default: ++ break; ++ } ++ ++ *ppos += count; ++ ++ return count; ++} ++ ++static const struct file_operations debugfs_trace_fops = { ++ .owner = THIS_MODULE, ++ .open = debugfs_trace_open, ++ .write = debugfs_trace_write, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++/* add an instance (process) to the debugfs entries */ ++int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance) ++{ ++ char pidstr[16]; ++ struct dentry *top, *use_count, *trace; ++ struct dentry *clients = vchiq_clients_top(); ++ ++ snprintf(pidstr, sizeof(pidstr), "%d", ++ vchiq_instance_get_pid(instance)); ++ ++ top = debugfs_create_dir(pidstr, clients); ++ if (!top) ++ goto fail_top; ++ ++ use_count = debugfs_create_file("use_count", ++ 0444, top, ++ instance, ++ &debugfs_usecount_fops); ++ if (!use_count) ++ goto fail_use_count; ++ ++ trace = debugfs_create_file("trace", ++ 0644, top, ++ instance, ++ &debugfs_trace_fops); ++ if (!trace) ++ goto fail_trace; ++ ++ vchiq_instance_get_debugfs_node(instance)->dentry = top; ++ ++ return 0; ++ ++fail_trace: ++ debugfs_remove(use_count); ++fail_use_count: ++ debugfs_remove(top); ++fail_top: ++ return -ENOMEM; ++} ++ ++void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_DEBUGFS_NODE_T *node = vchiq_instance_get_debugfs_node(instance); ++ debugfs_remove_recursive(node->dentry); ++} ++ ++ ++int vchiq_debugfs_init(void) ++{ ++ BUG_ON(debugfs_info.vchiq_cfg_dir != NULL); ++ ++ debugfs_info.vchiq_cfg_dir = debugfs_create_dir("vchiq", NULL); ++ if (debugfs_info.vchiq_cfg_dir == NULL) ++ goto fail; ++ ++ debugfs_info.clients = debugfs_create_dir("clients", ++ vchiq_debugfs_top()); ++ if (!debugfs_info.clients) ++ goto fail; ++ ++ if (vchiq_debugfs_create_log_entries(vchiq_debugfs_top()) != 0) ++ goto fail; ++ ++ return 0; ++ ++fail: ++ vchiq_debugfs_deinit(); ++ vchiq_log_error(vchiq_arm_log_level, ++ "%s: failed to create debugfs directory", ++ __func__); ++ ++ return -ENOMEM; ++} ++ ++/* remove all the debugfs entries */ ++void vchiq_debugfs_deinit(void) ++{ ++ debugfs_remove_recursive(vchiq_debugfs_top()); ++} ++ ++static struct dentry *vchiq_clients_top(void) ++{ ++ return debugfs_info.clients; ++} ++ ++static struct dentry *vchiq_debugfs_top(void) ++{ ++ BUG_ON(debugfs_info.vchiq_cfg_dir == NULL); ++ return debugfs_info.vchiq_cfg_dir; ++} ++ ++#else /* CONFIG_DEBUG_FS */ ++ ++int vchiq_debugfs_init(void) ++{ ++ return 0; ++} ++ ++void vchiq_debugfs_deinit(void) ++{ ++} ++ ++int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance) ++{ ++ return 0; ++} ++ ++void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance) ++{ ++} ++ ++#endif /* CONFIG_DEBUG_FS */ +diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h +new file mode 100644 +index 0000000..4d6a378 +--- /dev/null ++++ b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h +@@ -0,0 +1,52 @@ ++/** ++ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_DEBUGFS_H ++#define VCHIQ_DEBUGFS_H ++ ++#include "vchiq_core.h" ++ ++typedef struct vchiq_debugfs_node_struct ++{ ++ struct dentry *dentry; ++} VCHIQ_DEBUGFS_NODE_T; ++ ++int vchiq_debugfs_init(void); ++ ++void vchiq_debugfs_deinit(void); ++ ++int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance); ++ ++void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance); ++ ++#endif /* VCHIQ_DEBUGFS_H */ +diff --git a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_proc.c b/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_proc.c +deleted file mode 100644 +index 8e59676..0000000 +--- a/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_proc.c ++++ /dev/null +@@ -1,253 +0,0 @@ +-/** +- * Copyright (c) 2010-2012 Broadcom. All rights reserved. +- * +- * Redistribution and use in source and binary forms, with or without +- * modification, are permitted provided that the following conditions +- * are met: +- * 1. Redistributions of source code must retain the above copyright +- * notice, this list of conditions, and the following disclaimer, +- * without modification. +- * 2. Redistributions in binary form must reproduce the above copyright +- * notice, this list of conditions and the following disclaimer in the +- * documentation and/or other materials provided with the distribution. +- * 3. The names of the above-listed copyright holders may not be used +- * to endorse or promote products derived from this software without +- * specific prior written permission. +- * +- * ALTERNATIVELY, this software may be distributed under the terms of the +- * GNU General Public License ("GPL") version 2, as published by the Free +- * Software Foundation. +- * +- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +- * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +- */ +- +- +-#include +-#include "vchiq_core.h" +-#include "vchiq_arm.h" +- +-#if 1 +- +-int vchiq_proc_init(void) +-{ +- return 0; +-} +- +-void vchiq_proc_deinit(void) +-{ +-} +- +-#else +- +-struct vchiq_proc_info { +- /* Global 'vc' proc entry used by all instances */ +- struct proc_dir_entry *vc_cfg_dir; +- +- /* one entry per client process */ +- struct proc_dir_entry *clients; +- +- /* log categories */ +- struct proc_dir_entry *log_categories; +-}; +- +-static struct vchiq_proc_info proc_info; +- +-struct proc_dir_entry *vchiq_proc_top(void) +-{ +- BUG_ON(proc_info.vc_cfg_dir == NULL); +- return proc_info.vc_cfg_dir; +-} +- +-/**************************************************************************** +-* +-* log category entries +-* +-***************************************************************************/ +-#define PROC_WRITE_BUF_SIZE 256 +- +-#define VCHIQ_LOG_ERROR_STR "error" +-#define VCHIQ_LOG_WARNING_STR "warning" +-#define VCHIQ_LOG_INFO_STR "info" +-#define VCHIQ_LOG_TRACE_STR "trace" +- +-static int log_cfg_read(char *buffer, +- char **start, +- off_t off, +- int count, +- int *eof, +- void *data) +-{ +- int len = 0; +- char *log_value = NULL; +- +- switch (*((int *)data)) { +- case VCHIQ_LOG_ERROR: +- log_value = VCHIQ_LOG_ERROR_STR; +- break; +- case VCHIQ_LOG_WARNING: +- log_value = VCHIQ_LOG_WARNING_STR; +- break; +- case VCHIQ_LOG_INFO: +- log_value = VCHIQ_LOG_INFO_STR; +- break; +- case VCHIQ_LOG_TRACE: +- log_value = VCHIQ_LOG_TRACE_STR; +- break; +- default: +- break; +- } +- +- len += sprintf(buffer + len, +- "%s\n", +- log_value ? log_value : "(null)"); +- +- return len; +-} +- +- +-static int log_cfg_write(struct file *file, +- const char __user *buffer, +- unsigned long count, +- void *data) +-{ +- int *log_module = data; +- char kbuf[PROC_WRITE_BUF_SIZE + 1]; +- +- (void)file; +- +- memset(kbuf, 0, PROC_WRITE_BUF_SIZE + 1); +- if (count >= PROC_WRITE_BUF_SIZE) +- count = PROC_WRITE_BUF_SIZE; +- +- if (copy_from_user(kbuf, +- buffer, +- count) != 0) +- return -EFAULT; +- kbuf[count - 1] = 0; +- +- if (strncmp("error", kbuf, strlen("error")) == 0) +- *log_module = VCHIQ_LOG_ERROR; +- else if (strncmp("warning", kbuf, strlen("warning")) == 0) +- *log_module = VCHIQ_LOG_WARNING; +- else if (strncmp("info", kbuf, strlen("info")) == 0) +- *log_module = VCHIQ_LOG_INFO; +- else if (strncmp("trace", kbuf, strlen("trace")) == 0) +- *log_module = VCHIQ_LOG_TRACE; +- else +- *log_module = VCHIQ_LOG_DEFAULT; +- +- return count; +-} +- +-/* Log category proc entries */ +-struct vchiq_proc_log_entry { +- const char *name; +- int *plevel; +- struct proc_dir_entry *dir; +-}; +- +-static struct vchiq_proc_log_entry vchiq_proc_log_entries[] = { +- { "core", &vchiq_core_log_level }, +- { "msg", &vchiq_core_msg_log_level }, +- { "sync", &vchiq_sync_log_level }, +- { "susp", &vchiq_susp_log_level }, +- { "arm", &vchiq_arm_log_level }, +-}; +-static int n_log_entries = +- sizeof(vchiq_proc_log_entries)/sizeof(vchiq_proc_log_entries[0]); +- +-/* create an entry under /proc/vc/log for each log category */ +-static int vchiq_proc_create_log_entries(struct proc_dir_entry *top) +-{ +- struct proc_dir_entry *dir; +- size_t i; +- int ret = 0; +- dir = proc_mkdir("log", proc_info.vc_cfg_dir); +- if (!dir) +- return -ENOMEM; +- proc_info.log_categories = dir; +- +- for (i = 0; i < n_log_entries; i++) { +- dir = create_proc_entry(vchiq_proc_log_entries[i].name, +- 0644, +- proc_info.log_categories); +- if (!dir) { +- ret = -ENOMEM; +- break; +- } +- +- dir->read_proc = &log_cfg_read; +- dir->write_proc = &log_cfg_write; +- dir->data = (void *)vchiq_proc_log_entries[i].plevel; +- +- vchiq_proc_log_entries[i].dir = dir; +- } +- return ret; +-} +- +- +-int vchiq_proc_init(void) +-{ +- BUG_ON(proc_info.vc_cfg_dir != NULL); +- +- proc_info.vc_cfg_dir = proc_mkdir("vc", NULL); +- if (proc_info.vc_cfg_dir == NULL) +- goto fail; +- +- proc_info.clients = proc_mkdir("clients", +- proc_info.vc_cfg_dir); +- if (!proc_info.clients) +- goto fail; +- +- if (vchiq_proc_create_log_entries(proc_info.vc_cfg_dir) != 0) +- goto fail; +- +- return 0; +- +-fail: +- vchiq_proc_deinit(); +- vchiq_log_error(vchiq_arm_log_level, +- "%s: failed to create proc directory", +- __func__); +- +- return -ENOMEM; +-} +- +-/* remove all the proc entries */ +-void vchiq_proc_deinit(void) +-{ +- /* log category entries */ +- if (proc_info.log_categories) { +- size_t i; +- for (i = 0; i < n_log_entries; i++) +- if (vchiq_proc_log_entries[i].dir) +- remove_proc_entry( +- vchiq_proc_log_entries[i].name, +- proc_info.log_categories); +- +- remove_proc_entry(proc_info.log_categories->name, +- proc_info.vc_cfg_dir); +- } +- if (proc_info.clients) +- remove_proc_entry(proc_info.clients->name, +- proc_info.vc_cfg_dir); +- if (proc_info.vc_cfg_dir) +- remove_proc_entry(proc_info.vc_cfg_dir->name, NULL); +-} +- +-struct proc_dir_entry *vchiq_clients_top(void) +-{ +- return proc_info.clients; +-} +- +-#endif + +From 752be8a6ccd72c60151d5ee1bf193d7083b0b1ab Mon Sep 17 00:00:00 2001 +From: popcornmix +Date: Sun, 12 Oct 2014 14:58:31 +0100 +Subject: [PATCH 80/82] bcm2835-cpufreq: Update to use target_index interface + to fix issues with 3.17 kernel + +--- + drivers/cpufreq/bcm2835-cpufreq.c | 81 ++++++++++++++++----------------------- + 1 file changed, 33 insertions(+), 48 deletions(-) + +diff --git a/drivers/cpufreq/bcm2835-cpufreq.c b/drivers/cpufreq/bcm2835-cpufreq.c +index 7bc55bd..447ca09 100755 +--- a/drivers/cpufreq/bcm2835-cpufreq.c ++++ b/drivers/cpufreq/bcm2835-cpufreq.c +@@ -63,6 +63,12 @@ struct vc_msg { + /* ---------- GLOBALS ---------- */ + static struct cpufreq_driver bcm2835_cpufreq_driver; /* the cpufreq driver global */ + ++static struct cpufreq_frequency_table bcm2835_freq_table[] = { ++ {0, 0, 0}, ++ {0, 0, 0}, ++ {0, 0, CPUFREQ_TABLE_END}, ++}; ++ + /* + =============================================== + clk_rate either gets or sets the clock rates. +@@ -157,78 +163,57 @@ static void __exit bcm2835_cpufreq_module_exit(void) + static int bcm2835_cpufreq_driver_init(struct cpufreq_policy *policy) + { + /* measured value of how long it takes to change frequency */ +- policy->cpuinfo.transition_latency = 355000; /* ns */ ++ const unsigned int transition_latency = 355000; /* ns */ + + /* now find out what the maximum and minimum frequencies are */ +- policy->min = policy->cpuinfo.min_freq = bcm2835_cpufreq_get_clock(VCMSG_GET_MIN_CLOCK); +- policy->max = policy->cpuinfo.max_freq = bcm2835_cpufreq_get_clock(VCMSG_GET_MAX_CLOCK); +- policy->cur = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE); ++ bcm2835_freq_table[0].frequency = bcm2835_cpufreq_get_clock(VCMSG_GET_MIN_CLOCK); ++ bcm2835_freq_table[1].frequency = bcm2835_cpufreq_get_clock(VCMSG_GET_MAX_CLOCK); + +- print_info("min=%d max=%d cur=%d\n", policy->min, policy->max, policy->cur); +- return 0; ++ print_info("min=%d max=%d\n", bcm2835_freq_table[0].frequency, bcm2835_freq_table[1].frequency); ++ return cpufreq_generic_init(policy, bcm2835_freq_table, transition_latency); + } + + /* +- ================================================================================= +- Target function chooses the most appropriate frequency from the table to enable +- ================================================================================= ++ ===================================================================== ++ Target index function chooses the requested frequency from the table ++ ===================================================================== + */ + +-static int bcm2835_cpufreq_driver_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation) ++static int bcm2835_cpufreq_driver_target_index(struct cpufreq_policy *policy, unsigned int state) + { +- unsigned int target = target_freq; +-#ifdef CPUFREQ_DEBUG_ENABLE +- unsigned int cur = policy->cur; +-#endif +- print_debug("%s: min=%d max=%d cur=%d target=%d\n",policy->governor->name,policy->min,policy->max,policy->cur,target_freq); ++ unsigned int target_freq = bcm2835_freq_table[state].frequency; ++ unsigned int cur = bcm2835_cpufreq_set_clock(policy->cur, target_freq); + +- /* if we are above min and using ondemand, then just use max */ +- if (strcmp("ondemand", policy->governor->name)==0 && target > policy->min) +- target = policy->max; +- /* if the frequency is the same, just quit */ +- if (target == policy->cur) +- return 0; +- +- /* otherwise were good to set the clock frequency */ +- policy->cur = bcm2835_cpufreq_set_clock(policy->cur, target); +- +- if (!policy->cur) ++ if (!cur) + { +- print_err("Error occurred setting a new frequency (%d)!\n", target); +- policy->cur = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE); ++ print_err("Error occurred setting a new frequency (%d)\n", target_freq); + return -EINVAL; } +- print_debug("Freq %d->%d (min=%d max=%d target=%d request=%d)\n", cur, policy->cur, policy->min, policy->max, target_freq, target); ++ print_debug("%s: %i: freq %d->%d\n", policy->governor->name, state, policy->cur, cur); + return 0; + } -+ bcm2708_gpio_setpull(gpiochip, gpio_in_pin, gpio_in_pull); - gpiochip->direction_input(gpiochip, gpio_in_pin); - gpiochip->direction_output(gpiochip, gpio_out_pin, 1); - gpiochip->set(gpiochip, gpio_out_pin, invert); -@@ -666,6 +671,10 @@ module_param(gpio_in_pin, int, S_IRUGO); - MODULE_PARM_DESC(gpio_in_pin, "GPIO input pin number of the BCM processor." - " (default 18"); +-static unsigned int bcm2835_cpufreq_driver_get(unsigned int cpu) +-{ +- unsigned int actual_rate = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE); +- print_debug("cpu=%d\n", actual_rate); +- return actual_rate; +-} +- + /* +- ================================================================================= +- Verify ensures that when a policy is changed, it is suitable for the CPU to use +- ================================================================================= ++ ====================================================== ++ Get function returns the current frequency from table ++ ====================================================== + */ -+module_param(gpio_in_pull, int, S_IRUGO); -+MODULE_PARM_DESC(gpio_in_pull, "GPIO input pin pull configuration." -+ " (0 = off, 1 = up, 2 = down, default down)"); +-static int bcm2835_cpufreq_driver_verify(struct cpufreq_policy *policy) ++static unsigned int bcm2835_cpufreq_driver_get(unsigned int cpu) + { +- print_info("switching to governor %s\n", policy->governor->name); +- return 0; ++ unsigned int actual_rate = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE); ++ print_debug("%d: freq=%d\n", cpu, actual_rate); ++ return actual_rate <= bcm2835_freq_table[0].frequency ? bcm2835_freq_table[0].frequency : bcm2835_freq_table[1].frequency; + } + +- + /* the CPUFreq driver */ + static struct cpufreq_driver bcm2835_cpufreq_driver = { +- .name = "BCM2835 CPUFreq", +- .init = bcm2835_cpufreq_driver_init, +- .verify = bcm2835_cpufreq_driver_verify, +- .target = bcm2835_cpufreq_driver_target, +- .get = bcm2835_cpufreq_driver_get ++ .name = "BCM2835 CPUFreq", ++ .init = bcm2835_cpufreq_driver_init, ++ .verify = cpufreq_generic_frequency_table_verify, ++ .target_index = bcm2835_cpufreq_driver_target_index, ++ .get = bcm2835_cpufreq_driver_get, ++ .attr = cpufreq_generic_attr, + }; + + MODULE_AUTHOR("Dorian Peake and Dom Cobley"); + +From 411ca756b4567458a9c57ace933a9f025ecd00c7 Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Mon, 13 Oct 2014 11:47:53 +0100 +Subject: [PATCH 81/82] Improve __copy_to_user and __copy_from_user performance + +Provide a __copy_from_user that uses memcpy. On BCM2708, use +optimised memcpy/memmove/memcmp/memset implementations. +--- + arch/arm/include/asm/string.h | 5 + + arch/arm/include/asm/uaccess.h | 1 + + arch/arm/lib/Makefile | 15 +- + arch/arm/lib/arm-mem.h | 159 ++++++++++++ + arch/arm/lib/copy_from_user.S | 4 +- + arch/arm/lib/exports_rpi.c | 37 +++ + arch/arm/lib/memcmp_rpi.S | 285 +++++++++++++++++++++ + arch/arm/lib/memcpy_rpi.S | 59 +++++ + arch/arm/lib/memcpymove.h | 506 +++++++++++++++++++++++++++++++++++++ + arch/arm/lib/memmove_rpi.S | 61 +++++ + arch/arm/lib/memset_rpi.S | 121 +++++++++ + arch/arm/lib/uaccess_with_memcpy.c | 112 +++++++- + 12 files changed, 1359 insertions(+), 6 deletions(-) + create mode 100644 arch/arm/lib/arm-mem.h + create mode 100644 arch/arm/lib/exports_rpi.c + create mode 100644 arch/arm/lib/memcmp_rpi.S + create mode 100644 arch/arm/lib/memcpy_rpi.S + create mode 100644 arch/arm/lib/memcpymove.h + create mode 100644 arch/arm/lib/memmove_rpi.S + create mode 100644 arch/arm/lib/memset_rpi.S + +diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h +index cf4f3aa..9fe7780 100644 +--- a/arch/arm/include/asm/string.h ++++ b/arch/arm/include/asm/string.h +@@ -24,6 +24,11 @@ extern void * memchr(const void *, int, __kernel_size_t); + #define __HAVE_ARCH_MEMSET + extern void * memset(void *, int, __kernel_size_t); + ++#ifdef CONFIG_MACH_BCM2708 ++#define __HAVE_ARCH_MEMCMP ++extern int memcmp(const void *, const void *, size_t); ++#endif + - module_param(sense, int, S_IRUGO); - MODULE_PARM_DESC(sense, "Override autodetection of IR receiver circuit" - " (0 = active high, 1 = active low )"); + extern void __memzero(void *ptr, __kernel_size_t n); + + #define memset(p,v,n) \ +diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h +index 4767eb9..bcd43de 100644 +--- a/arch/arm/include/asm/uaccess.h ++++ b/arch/arm/include/asm/uaccess.h +@@ -475,6 +475,7 @@ do { \ + + #ifdef CONFIG_MMU + extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n); ++extern unsigned long __must_check __copy_from_user_std(void *to, const void __user *from, unsigned long n); + extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n); + extern unsigned long __must_check __copy_to_user_std(void __user *to, const void *from, unsigned long n); + extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n); +diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile +index 0573faa..498f5dd 100644 +--- a/arch/arm/lib/Makefile ++++ b/arch/arm/lib/Makefile +@@ -6,15 +6,24 @@ + + lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \ + csumpartialcopy.o csumpartialcopyuser.o clearbit.o \ +- delay.o delay-loop.o findbit.o memchr.o memcpy.o \ +- memmove.o memset.o memzero.o setbit.o \ +- strchr.o strrchr.o \ ++ delay.o delay-loop.o findbit.o memchr.o memzero.o \ ++ setbit.o strchr.o strrchr.o \ + testchangebit.o testclearbit.o testsetbit.o \ + ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \ + ucmpdi2.o lib1funcs.o div64.o \ + io-readsb.o io-writesb.o io-readsl.o io-writesl.o \ + call_with_stack.o bswapsdi2.o + ++# Choose optimised implementations for Raspberry Pi ++ifeq ($(CONFIG_MACH_BCM2708),y) ++ CFLAGS_uaccess_with_memcpy.o += -DCOPY_FROM_USER_THRESHOLD=1600 ++ CFLAGS_uaccess_with_memcpy.o += -DCOPY_TO_USER_THRESHOLD=672 ++ obj-$(CONFIG_MODULES) += exports_rpi.o ++ lib-y += memcpy_rpi.o memmove_rpi.o memset_rpi.o memcmp_rpi.o ++else ++ lib-y += memcpy.o memmove.o memset.o ++endif ++ + mmu-y := clear_user.o copy_page.o getuser.o putuser.o + + # the code in uaccess.S is not preemption safe and +diff --git a/arch/arm/lib/arm-mem.h b/arch/arm/lib/arm-mem.h +new file mode 100644 +index 0000000..5d4bda1 +--- /dev/null ++++ b/arch/arm/lib/arm-mem.h +@@ -0,0 +1,159 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++.macro myfunc fname ++ .func fname ++ .global fname ++fname: ++.endm ++ ++.macro preload_leading_step1 backwards, ptr, base ++/* If the destination is already 16-byte aligned, then we need to preload ++ * between 0 and prefetch_distance (inclusive) cache lines ahead so there ++ * are no gaps when the inner loop starts. ++ */ ++ .if backwards ++ sub ptr, base, #1 ++ bic ptr, ptr, #31 ++ .else ++ bic ptr, base, #31 ++ .endif ++ .set OFFSET, 0 ++ .rept prefetch_distance+1 ++ pld [ptr, #OFFSET] ++ .if backwards ++ .set OFFSET, OFFSET-32 ++ .else ++ .set OFFSET, OFFSET+32 ++ .endif ++ .endr ++.endm ++ ++.macro preload_leading_step2 backwards, ptr, base, leading_bytes, tmp ++/* However, if the destination is not 16-byte aligned, we may need to ++ * preload one more cache line than that. The question we need to ask is: ++ * are the leading bytes more than the amount by which the source ++ * pointer will be rounded down for preloading, and if so, by how many ++ * cache lines? ++ */ ++ .if backwards ++/* Here we compare against how many bytes we are into the ++ * cache line, counting down from the highest such address. ++ * Effectively, we want to calculate ++ * leading_bytes = dst&15 ++ * cacheline_offset = 31-((src-leading_bytes-1)&31) ++ * extra_needed = leading_bytes - cacheline_offset ++ * and test if extra_needed is <= 0, or rearranging: ++ * leading_bytes + (src-leading_bytes-1)&31 <= 31 ++ */ ++ mov tmp, base, lsl #32-5 ++ sbc tmp, tmp, leading_bytes, lsl #32-5 ++ adds tmp, tmp, leading_bytes, lsl #32-5 ++ bcc 61f ++ pld [ptr, #-32*(prefetch_distance+1)] ++ .else ++/* Effectively, we want to calculate ++ * leading_bytes = (-dst)&15 ++ * cacheline_offset = (src+leading_bytes)&31 ++ * extra_needed = leading_bytes - cacheline_offset ++ * and test if extra_needed is <= 0. ++ */ ++ mov tmp, base, lsl #32-5 ++ add tmp, tmp, leading_bytes, lsl #32-5 ++ rsbs tmp, tmp, leading_bytes, lsl #32-5 ++ bls 61f ++ pld [ptr, #32*(prefetch_distance+1)] ++ .endif ++61: ++.endm ++ ++.macro preload_trailing backwards, base, remain, tmp ++ /* We need either 0, 1 or 2 extra preloads */ ++ .if backwards ++ rsb tmp, base, #0 ++ mov tmp, tmp, lsl #32-5 ++ .else ++ mov tmp, base, lsl #32-5 ++ .endif ++ adds tmp, tmp, remain, lsl #32-5 ++ adceqs tmp, tmp, #0 ++ /* The instruction above has two effects: ensures Z is only ++ * set if C was clear (so Z indicates that both shifted quantities ++ * were 0), and clears C if Z was set (so C indicates that the sum ++ * of the shifted quantities was greater and not equal to 32) */ ++ beq 82f ++ .if backwards ++ sub tmp, base, #1 ++ bic tmp, tmp, #31 ++ .else ++ bic tmp, base, #31 ++ .endif ++ bcc 81f ++ .if backwards ++ pld [tmp, #-32*(prefetch_distance+1)] ++81: ++ pld [tmp, #-32*prefetch_distance] ++ .else ++ pld [tmp, #32*(prefetch_distance+2)] ++81: ++ pld [tmp, #32*(prefetch_distance+1)] ++ .endif ++82: ++.endm ++ ++.macro preload_all backwards, narrow_case, shift, base, remain, tmp0, tmp1 ++ .if backwards ++ sub tmp0, base, #1 ++ bic tmp0, tmp0, #31 ++ pld [tmp0] ++ sub tmp1, base, remain, lsl #shift ++ .else ++ bic tmp0, base, #31 ++ pld [tmp0] ++ add tmp1, base, remain, lsl #shift ++ sub tmp1, tmp1, #1 ++ .endif ++ bic tmp1, tmp1, #31 ++ cmp tmp1, tmp0 ++ beq 92f ++ .if narrow_case ++ /* In this case, all the data fits in either 1 or 2 cache lines */ ++ pld [tmp1] ++ .else ++91: ++ .if backwards ++ sub tmp0, tmp0, #32 ++ .else ++ add tmp0, tmp0, #32 ++ .endif ++ cmp tmp0, tmp1 ++ pld [tmp0] ++ bne 91b ++ .endif ++92: ++.endm +diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S +index 66a477a..3faddf7 100644 +--- a/arch/arm/lib/copy_from_user.S ++++ b/arch/arm/lib/copy_from_user.S +@@ -84,11 +84,13 @@ + + .text + +-ENTRY(__copy_from_user) ++ENTRY(__copy_from_user_std) ++WEAK(__copy_from_user) + + #include "copy_template.S" + + ENDPROC(__copy_from_user) ++ENDPROC(__copy_from_user_std) + + .pushsection .fixup,"ax" + .align 0 +diff --git a/arch/arm/lib/exports_rpi.c b/arch/arm/lib/exports_rpi.c +new file mode 100644 +index 0000000..1f82604 +--- /dev/null ++++ b/arch/arm/lib/exports_rpi.c +@@ -0,0 +1,37 @@ ++/** ++ * Copyright (c) 2014, Raspberry Pi (Trading) Ltd. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++ ++EXPORT_SYMBOL(memcmp); +diff --git a/arch/arm/lib/memcmp_rpi.S b/arch/arm/lib/memcmp_rpi.S +new file mode 100644 +index 0000000..bf6e4ed +--- /dev/null ++++ b/arch/arm/lib/memcmp_rpi.S +@@ -0,0 +1,285 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++#include ++#include "arm-mem.h" ++ ++/* Prevent the stack from becoming executable */ ++#if defined(__linux__) && defined(__ELF__) ++.section .note.GNU-stack,"",%progbits ++#endif ++ ++ .text ++ .arch armv6 ++ .object_arch armv4 ++ .arm ++ .altmacro ++ .p2align 2 ++ ++.macro memcmp_process_head unaligned ++ .if unaligned ++ ldr DAT0, [S_1], #4 ++ ldr DAT1, [S_1], #4 ++ ldr DAT2, [S_1], #4 ++ ldr DAT3, [S_1], #4 ++ .else ++ ldmia S_1!, {DAT0, DAT1, DAT2, DAT3} ++ .endif ++ ldmia S_2!, {DAT4, DAT5, DAT6, DAT7} ++.endm ++ ++.macro memcmp_process_tail ++ cmp DAT0, DAT4 ++ cmpeq DAT1, DAT5 ++ cmpeq DAT2, DAT6 ++ cmpeq DAT3, DAT7 ++ bne 200f ++.endm ++ ++.macro memcmp_leading_31bytes ++ movs DAT0, OFF, lsl #31 ++ ldrmib DAT0, [S_1], #1 ++ ldrcsh DAT1, [S_1], #2 ++ ldrmib DAT4, [S_2], #1 ++ ldrcsh DAT5, [S_2], #2 ++ movpl DAT0, #0 ++ movcc DAT1, #0 ++ movpl DAT4, #0 ++ movcc DAT5, #0 ++ submi N, N, #1 ++ subcs N, N, #2 ++ cmp DAT0, DAT4 ++ cmpeq DAT1, DAT5 ++ bne 200f ++ movs DAT0, OFF, lsl #29 ++ ldrmi DAT0, [S_1], #4 ++ ldrcs DAT1, [S_1], #4 ++ ldrcs DAT2, [S_1], #4 ++ ldrmi DAT4, [S_2], #4 ++ ldmcsia S_2!, {DAT5, DAT6} ++ movpl DAT0, #0 ++ movcc DAT1, #0 ++ movcc DAT2, #0 ++ movpl DAT4, #0 ++ movcc DAT5, #0 ++ movcc DAT6, #0 ++ submi N, N, #4 ++ subcs N, N, #8 ++ cmp DAT0, DAT4 ++ cmpeq DAT1, DAT5 ++ cmpeq DAT2, DAT6 ++ bne 200f ++ tst OFF, #16 ++ beq 105f ++ memcmp_process_head 1 ++ sub N, N, #16 ++ memcmp_process_tail ++105: ++.endm ++ ++.macro memcmp_trailing_15bytes unaligned ++ movs N, N, lsl #29 ++ .if unaligned ++ ldrcs DAT0, [S_1], #4 ++ ldrcs DAT1, [S_1], #4 ++ .else ++ ldmcsia S_1!, {DAT0, DAT1} ++ .endif ++ ldrmi DAT2, [S_1], #4 ++ ldmcsia S_2!, {DAT4, DAT5} ++ ldrmi DAT6, [S_2], #4 ++ movcc DAT0, #0 ++ movcc DAT1, #0 ++ movpl DAT2, #0 ++ movcc DAT4, #0 ++ movcc DAT5, #0 ++ movpl DAT6, #0 ++ cmp DAT0, DAT4 ++ cmpeq DAT1, DAT5 ++ cmpeq DAT2, DAT6 ++ bne 200f ++ movs N, N, lsl #2 ++ ldrcsh DAT0, [S_1], #2 ++ ldrmib DAT1, [S_1] ++ ldrcsh DAT4, [S_2], #2 ++ ldrmib DAT5, [S_2] ++ movcc DAT0, #0 ++ movpl DAT1, #0 ++ movcc DAT4, #0 ++ movpl DAT5, #0 ++ cmp DAT0, DAT4 ++ cmpeq DAT1, DAT5 ++ bne 200f ++.endm ++ ++.macro memcmp_long_inner_loop unaligned ++110: ++ memcmp_process_head unaligned ++ pld [S_2, #prefetch_distance*32 + 16] ++ memcmp_process_tail ++ memcmp_process_head unaligned ++ pld [S_1, OFF] ++ memcmp_process_tail ++ subs N, N, #32 ++ bhs 110b ++ /* Just before the final (prefetch_distance+1) 32-byte blocks, ++ * deal with final preloads */ ++ preload_trailing 0, S_1, N, DAT0 ++ preload_trailing 0, S_2, N, DAT0 ++ add N, N, #(prefetch_distance+2)*32 - 16 ++120: ++ memcmp_process_head unaligned ++ memcmp_process_tail ++ subs N, N, #16 ++ bhs 120b ++ /* Trailing words and bytes */ ++ tst N, #15 ++ beq 199f ++ memcmp_trailing_15bytes unaligned ++199: /* Reached end without detecting a difference */ ++ mov a1, #0 ++ setend le ++ pop {DAT1-DAT6, pc} ++.endm ++ ++.macro memcmp_short_inner_loop unaligned ++ subs N, N, #16 /* simplifies inner loop termination */ ++ blo 122f ++120: ++ memcmp_process_head unaligned ++ memcmp_process_tail ++ subs N, N, #16 ++ bhs 120b ++122: /* Trailing words and bytes */ ++ tst N, #15 ++ beq 199f ++ memcmp_trailing_15bytes unaligned ++199: /* Reached end without detecting a difference */ ++ mov a1, #0 ++ setend le ++ pop {DAT1-DAT6, pc} ++.endm ++ ++/* ++ * int memcmp(const void *s1, const void *s2, size_t n); ++ * On entry: ++ * a1 = pointer to buffer 1 ++ * a2 = pointer to buffer 2 ++ * a3 = number of bytes to compare (as unsigned chars) ++ * On exit: ++ * a1 = >0/=0/<0 if s1 >/=/< s2 ++ */ ++ ++.set prefetch_distance, 2 ++ ++ENTRY(memcmp) ++ S_1 .req a1 ++ S_2 .req a2 ++ N .req a3 ++ DAT0 .req a4 ++ DAT1 .req v1 ++ DAT2 .req v2 ++ DAT3 .req v3 ++ DAT4 .req v4 ++ DAT5 .req v5 ++ DAT6 .req v6 ++ DAT7 .req ip ++ OFF .req lr ++ ++ push {DAT1-DAT6, lr} ++ setend be /* lowest-addressed bytes are most significant */ ++ ++ /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */ ++ cmp N, #(prefetch_distance+3)*32 - 1 ++ blo 170f ++ ++ /* Long case */ ++ /* Adjust N so that the decrement instruction can also test for ++ * inner loop termination. We want it to stop when there are ++ * (prefetch_distance+1) complete blocks to go. */ ++ sub N, N, #(prefetch_distance+2)*32 ++ preload_leading_step1 0, DAT0, S_1 ++ preload_leading_step1 0, DAT1, S_2 ++ tst S_2, #31 ++ beq 154f ++ rsb OFF, S_2, #0 /* no need to AND with 15 here */ ++ preload_leading_step2 0, DAT0, S_1, OFF, DAT2 ++ preload_leading_step2 0, DAT1, S_2, OFF, DAT2 ++ memcmp_leading_31bytes ++154: /* Second source now cacheline (32-byte) aligned; we have at ++ * least one prefetch to go. */ ++ /* Prefetch offset is best selected such that it lies in the ++ * first 8 of each 32 bytes - but it's just as easy to aim for ++ * the first one */ ++ and OFF, S_1, #31 ++ rsb OFF, OFF, #32*prefetch_distance ++ tst S_1, #3 ++ bne 140f ++ memcmp_long_inner_loop 0 ++140: memcmp_long_inner_loop 1 ++ ++170: /* Short case */ ++ teq N, #0 ++ beq 199f ++ preload_all 0, 0, 0, S_1, N, DAT0, DAT1 ++ preload_all 0, 0, 0, S_2, N, DAT0, DAT1 ++ tst S_2, #3 ++ beq 174f ++172: subs N, N, #1 ++ blo 199f ++ ldrb DAT0, [S_1], #1 ++ ldrb DAT4, [S_2], #1 ++ cmp DAT0, DAT4 ++ bne 200f ++ tst S_2, #3 ++ bne 172b ++174: /* Second source now 4-byte aligned; we have 0 or more bytes to go */ ++ tst S_1, #3 ++ bne 140f ++ memcmp_short_inner_loop 0 ++140: memcmp_short_inner_loop 1 ++ ++200: /* Difference found: determine sign. */ ++ movhi a1, #1 ++ movlo a1, #-1 ++ setend le ++ pop {DAT1-DAT6, pc} ++ ++ .unreq S_1 ++ .unreq S_2 ++ .unreq N ++ .unreq DAT0 ++ .unreq DAT1 ++ .unreq DAT2 ++ .unreq DAT3 ++ .unreq DAT4 ++ .unreq DAT5 ++ .unreq DAT6 ++ .unreq DAT7 ++ .unreq OFF ++ENDPROC(memcmp) +diff --git a/arch/arm/lib/memcpy_rpi.S b/arch/arm/lib/memcpy_rpi.S +new file mode 100644 +index 0000000..15ff2bd +--- /dev/null ++++ b/arch/arm/lib/memcpy_rpi.S +@@ -0,0 +1,59 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++#include ++#include "arm-mem.h" ++#include "memcpymove.h" ++ ++/* Prevent the stack from becoming executable */ ++#if defined(__linux__) && defined(__ELF__) ++.section .note.GNU-stack,"",%progbits ++#endif ++ ++ .text ++ .arch armv6 ++ .object_arch armv4 ++ .arm ++ .altmacro ++ .p2align 2 ++ ++/* ++ * void *memcpy(void * restrict s1, const void * restrict s2, size_t n); ++ * On entry: ++ * a1 = pointer to destination ++ * a2 = pointer to source ++ * a3 = number of bytes to copy ++ * On exit: ++ * a1 preserved ++ */ ++ ++.set prefetch_distance, 3 ++ ++ENTRY(memcpy) ++ memcpy 0 ++ENDPROC(memcpy) +diff --git a/arch/arm/lib/memcpymove.h b/arch/arm/lib/memcpymove.h +new file mode 100644 +index 0000000..d8be584 +--- /dev/null ++++ b/arch/arm/lib/memcpymove.h +@@ -0,0 +1,506 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++.macro unaligned_words backwards, align, use_pld, words, r0, r1, r2, r3, r4, r5, r6, r7, r8 ++ .if words == 1 ++ .if backwards ++ mov r1, r0, lsl #32-align*8 ++ ldr r0, [S, #-4]! ++ orr r1, r1, r0, lsr #align*8 ++ str r1, [D, #-4]! ++ .else ++ mov r0, r1, lsr #align*8 ++ ldr r1, [S, #4]! ++ orr r0, r0, r1, lsl #32-align*8 ++ str r0, [D], #4 ++ .endif ++ .elseif words == 2 ++ .if backwards ++ ldr r1, [S, #-4]! ++ mov r2, r0, lsl #32-align*8 ++ ldr r0, [S, #-4]! ++ orr r2, r2, r1, lsr #align*8 ++ mov r1, r1, lsl #32-align*8 ++ orr r1, r1, r0, lsr #align*8 ++ stmdb D!, {r1, r2} ++ .else ++ ldr r1, [S, #4]! ++ mov r0, r2, lsr #align*8 ++ ldr r2, [S, #4]! ++ orr r0, r0, r1, lsl #32-align*8 ++ mov r1, r1, lsr #align*8 ++ orr r1, r1, r2, lsl #32-align*8 ++ stmia D!, {r0, r1} ++ .endif ++ .elseif words == 4 ++ .if backwards ++ ldmdb S!, {r2, r3} ++ mov r4, r0, lsl #32-align*8 ++ ldmdb S!, {r0, r1} ++ orr r4, r4, r3, lsr #align*8 ++ mov r3, r3, lsl #32-align*8 ++ orr r3, r3, r2, lsr #align*8 ++ mov r2, r2, lsl #32-align*8 ++ orr r2, r2, r1, lsr #align*8 ++ mov r1, r1, lsl #32-align*8 ++ orr r1, r1, r0, lsr #align*8 ++ stmdb D!, {r1, r2, r3, r4} ++ .else ++ ldmib S!, {r1, r2} ++ mov r0, r4, lsr #align*8 ++ ldmib S!, {r3, r4} ++ orr r0, r0, r1, lsl #32-align*8 ++ mov r1, r1, lsr #align*8 ++ orr r1, r1, r2, lsl #32-align*8 ++ mov r2, r2, lsr #align*8 ++ orr r2, r2, r3, lsl #32-align*8 ++ mov r3, r3, lsr #align*8 ++ orr r3, r3, r4, lsl #32-align*8 ++ stmia D!, {r0, r1, r2, r3} ++ .endif ++ .elseif words == 8 ++ .if backwards ++ ldmdb S!, {r4, r5, r6, r7} ++ mov r8, r0, lsl #32-align*8 ++ ldmdb S!, {r0, r1, r2, r3} ++ .if use_pld ++ pld [S, OFF] ++ .endif ++ orr r8, r8, r7, lsr #align*8 ++ mov r7, r7, lsl #32-align*8 ++ orr r7, r7, r6, lsr #align*8 ++ mov r6, r6, lsl #32-align*8 ++ orr r6, r6, r5, lsr #align*8 ++ mov r5, r5, lsl #32-align*8 ++ orr r5, r5, r4, lsr #align*8 ++ mov r4, r4, lsl #32-align*8 ++ orr r4, r4, r3, lsr #align*8 ++ mov r3, r3, lsl #32-align*8 ++ orr r3, r3, r2, lsr #align*8 ++ mov r2, r2, lsl #32-align*8 ++ orr r2, r2, r1, lsr #align*8 ++ mov r1, r1, lsl #32-align*8 ++ orr r1, r1, r0, lsr #align*8 ++ stmdb D!, {r5, r6, r7, r8} ++ stmdb D!, {r1, r2, r3, r4} ++ .else ++ ldmib S!, {r1, r2, r3, r4} ++ mov r0, r8, lsr #align*8 ++ ldmib S!, {r5, r6, r7, r8} ++ .if use_pld ++ pld [S, OFF] ++ .endif ++ orr r0, r0, r1, lsl #32-align*8 ++ mov r1, r1, lsr #align*8 ++ orr r1, r1, r2, lsl #32-align*8 ++ mov r2, r2, lsr #align*8 ++ orr r2, r2, r3, lsl #32-align*8 ++ mov r3, r3, lsr #align*8 ++ orr r3, r3, r4, lsl #32-align*8 ++ mov r4, r4, lsr #align*8 ++ orr r4, r4, r5, lsl #32-align*8 ++ mov r5, r5, lsr #align*8 ++ orr r5, r5, r6, lsl #32-align*8 ++ mov r6, r6, lsr #align*8 ++ orr r6, r6, r7, lsl #32-align*8 ++ mov r7, r7, lsr #align*8 ++ orr r7, r7, r8, lsl #32-align*8 ++ stmia D!, {r0, r1, r2, r3} ++ stmia D!, {r4, r5, r6, r7} ++ .endif ++ .endif ++.endm ++ ++.macro memcpy_leading_15bytes backwards, align ++ movs DAT1, DAT2, lsl #31 ++ sub N, N, DAT2 ++ .if backwards ++ ldrmib DAT0, [S, #-1]! ++ ldrcsh DAT1, [S, #-2]! ++ strmib DAT0, [D, #-1]! ++ strcsh DAT1, [D, #-2]! ++ .else ++ ldrmib DAT0, [S], #1 ++ ldrcsh DAT1, [S], #2 ++ strmib DAT0, [D], #1 ++ strcsh DAT1, [D], #2 ++ .endif ++ movs DAT1, DAT2, lsl #29 ++ .if backwards ++ ldrmi DAT0, [S, #-4]! ++ .if align == 0 ++ ldmcsdb S!, {DAT1, DAT2} ++ .else ++ ldrcs DAT2, [S, #-4]! ++ ldrcs DAT1, [S, #-4]! ++ .endif ++ strmi DAT0, [D, #-4]! ++ stmcsdb D!, {DAT1, DAT2} ++ .else ++ ldrmi DAT0, [S], #4 ++ .if align == 0 ++ ldmcsia S!, {DAT1, DAT2} ++ .else ++ ldrcs DAT1, [S], #4 ++ ldrcs DAT2, [S], #4 ++ .endif ++ strmi DAT0, [D], #4 ++ stmcsia D!, {DAT1, DAT2} ++ .endif ++.endm ++ ++.macro memcpy_trailing_15bytes backwards, align ++ movs N, N, lsl #29 ++ .if backwards ++ .if align == 0 ++ ldmcsdb S!, {DAT0, DAT1} ++ .else ++ ldrcs DAT1, [S, #-4]! ++ ldrcs DAT0, [S, #-4]! ++ .endif ++ ldrmi DAT2, [S, #-4]! ++ stmcsdb D!, {DAT0, DAT1} ++ strmi DAT2, [D, #-4]! ++ .else ++ .if align == 0 ++ ldmcsia S!, {DAT0, DAT1} ++ .else ++ ldrcs DAT0, [S], #4 ++ ldrcs DAT1, [S], #4 ++ .endif ++ ldrmi DAT2, [S], #4 ++ stmcsia D!, {DAT0, DAT1} ++ strmi DAT2, [D], #4 ++ .endif ++ movs N, N, lsl #2 ++ .if backwards ++ ldrcsh DAT0, [S, #-2]! ++ ldrmib DAT1, [S, #-1] ++ strcsh DAT0, [D, #-2]! ++ strmib DAT1, [D, #-1] ++ .else ++ ldrcsh DAT0, [S], #2 ++ ldrmib DAT1, [S] ++ strcsh DAT0, [D], #2 ++ strmib DAT1, [D] ++ .endif ++.endm ++ ++.macro memcpy_long_inner_loop backwards, align ++ .if align != 0 ++ .if backwards ++ ldr DAT0, [S, #-align]! ++ .else ++ ldr LAST, [S, #-align]! ++ .endif ++ .endif ++110: ++ .if align == 0 ++ .if backwards ++ ldmdb S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} ++ pld [S, OFF] ++ stmdb D!, {DAT4, DAT5, DAT6, LAST} ++ stmdb D!, {DAT0, DAT1, DAT2, DAT3} ++ .else ++ ldmia S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} ++ pld [S, OFF] ++ stmia D!, {DAT0, DAT1, DAT2, DAT3} ++ stmia D!, {DAT4, DAT5, DAT6, LAST} ++ .endif ++ .else ++ unaligned_words backwards, align, 1, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST ++ .endif ++ subs N, N, #32 ++ bhs 110b ++ /* Just before the final (prefetch_distance+1) 32-byte blocks, deal with final preloads */ ++ preload_trailing backwards, S, N, OFF ++ add N, N, #(prefetch_distance+2)*32 - 32 ++120: ++ .if align == 0 ++ .if backwards ++ ldmdb S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} ++ stmdb D!, {DAT4, DAT5, DAT6, LAST} ++ stmdb D!, {DAT0, DAT1, DAT2, DAT3} ++ .else ++ ldmia S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} ++ stmia D!, {DAT0, DAT1, DAT2, DAT3} ++ stmia D!, {DAT4, DAT5, DAT6, LAST} ++ .endif ++ .else ++ unaligned_words backwards, align, 0, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST ++ .endif ++ subs N, N, #32 ++ bhs 120b ++ tst N, #16 ++ .if align == 0 ++ .if backwards ++ ldmnedb S!, {DAT0, DAT1, DAT2, LAST} ++ stmnedb D!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ ldmneia S!, {DAT0, DAT1, DAT2, LAST} ++ stmneia D!, {DAT0, DAT1, DAT2, LAST} ++ .endif ++ .else ++ beq 130f ++ unaligned_words backwards, align, 0, 4, DAT0, DAT1, DAT2, DAT3, LAST ++130: ++ .endif ++ /* Trailing words and bytes */ ++ tst N, #15 ++ beq 199f ++ .if align != 0 ++ add S, S, #align ++ .endif ++ memcpy_trailing_15bytes backwards, align ++199: ++ pop {DAT3, DAT4, DAT5, DAT6, DAT7} ++ pop {D, DAT1, DAT2, pc} ++.endm ++ ++.macro memcpy_medium_inner_loop backwards, align ++120: ++ .if backwards ++ .if align == 0 ++ ldmdb S!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ ldr LAST, [S, #-4]! ++ ldr DAT2, [S, #-4]! ++ ldr DAT1, [S, #-4]! ++ ldr DAT0, [S, #-4]! ++ .endif ++ stmdb D!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ .if align == 0 ++ ldmia S!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ ldr DAT0, [S], #4 ++ ldr DAT1, [S], #4 ++ ldr DAT2, [S], #4 ++ ldr LAST, [S], #4 ++ .endif ++ stmia D!, {DAT0, DAT1, DAT2, LAST} ++ .endif ++ subs N, N, #16 ++ bhs 120b ++ /* Trailing words and bytes */ ++ tst N, #15 ++ beq 199f ++ memcpy_trailing_15bytes backwards, align ++199: ++ pop {D, DAT1, DAT2, pc} ++.endm ++ ++.macro memcpy_short_inner_loop backwards, align ++ tst N, #16 ++ .if backwards ++ .if align == 0 ++ ldmnedb S!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ ldrne LAST, [S, #-4]! ++ ldrne DAT2, [S, #-4]! ++ ldrne DAT1, [S, #-4]! ++ ldrne DAT0, [S, #-4]! ++ .endif ++ stmnedb D!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ .if align == 0 ++ ldmneia S!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ ldrne DAT0, [S], #4 ++ ldrne DAT1, [S], #4 ++ ldrne DAT2, [S], #4 ++ ldrne LAST, [S], #4 ++ .endif ++ stmneia D!, {DAT0, DAT1, DAT2, LAST} ++ .endif ++ memcpy_trailing_15bytes backwards, align ++199: ++ pop {D, DAT1, DAT2, pc} ++.endm ++ ++.macro memcpy backwards ++ D .req a1 ++ S .req a2 ++ N .req a3 ++ DAT0 .req a4 ++ DAT1 .req v1 ++ DAT2 .req v2 ++ DAT3 .req v3 ++ DAT4 .req v4 ++ DAT5 .req v5 ++ DAT6 .req v6 ++ DAT7 .req sl ++ LAST .req ip ++ OFF .req lr ++ ++ .cfi_startproc ++ ++ push {D, DAT1, DAT2, lr} ++ ++ .cfi_def_cfa_offset 16 ++ .cfi_rel_offset D, 0 ++ .cfi_undefined S ++ .cfi_undefined N ++ .cfi_undefined DAT0 ++ .cfi_rel_offset DAT1, 4 ++ .cfi_rel_offset DAT2, 8 ++ .cfi_undefined LAST ++ .cfi_rel_offset lr, 12 ++ ++ .if backwards ++ add D, D, N ++ add S, S, N ++ .endif ++ ++ /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */ ++ cmp N, #31 ++ blo 170f ++ /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */ ++ cmp N, #(prefetch_distance+3)*32 - 1 ++ blo 160f ++ ++ /* Long case */ ++ push {DAT3, DAT4, DAT5, DAT6, DAT7} ++ ++ .cfi_def_cfa_offset 36 ++ .cfi_rel_offset D, 20 ++ .cfi_rel_offset DAT1, 24 ++ .cfi_rel_offset DAT2, 28 ++ .cfi_rel_offset DAT3, 0 ++ .cfi_rel_offset DAT4, 4 ++ .cfi_rel_offset DAT5, 8 ++ .cfi_rel_offset DAT6, 12 ++ .cfi_rel_offset DAT7, 16 ++ .cfi_rel_offset lr, 32 ++ ++ /* Adjust N so that the decrement instruction can also test for ++ * inner loop termination. We want it to stop when there are ++ * (prefetch_distance+1) complete blocks to go. */ ++ sub N, N, #(prefetch_distance+2)*32 ++ preload_leading_step1 backwards, DAT0, S ++ .if backwards ++ /* Bug in GAS: it accepts, but mis-assembles the instruction ++ * ands DAT2, D, #60, 2 ++ * which sets DAT2 to the number of leading bytes until destination is aligned and also clears C (sets borrow) ++ */ ++ .word 0xE210513C ++ beq 154f ++ .else ++ ands DAT2, D, #15 ++ beq 154f ++ rsb DAT2, DAT2, #16 /* number of leading bytes until destination aligned */ ++ .endif ++ preload_leading_step2 backwards, DAT0, S, DAT2, OFF ++ memcpy_leading_15bytes backwards, 1 ++154: /* Destination now 16-byte aligned; we have at least one prefetch as well as at least one 16-byte output block */ ++ /* Prefetch offset is best selected such that it lies in the first 8 of each 32 bytes - but it's just as easy to aim for the first one */ ++ .if backwards ++ rsb OFF, S, #3 ++ and OFF, OFF, #28 ++ sub OFF, OFF, #32*(prefetch_distance+1) ++ .else ++ and OFF, S, #28 ++ rsb OFF, OFF, #32*prefetch_distance ++ .endif ++ movs DAT0, S, lsl #31 ++ bhi 157f ++ bcs 156f ++ bmi 155f ++ memcpy_long_inner_loop backwards, 0 ++155: memcpy_long_inner_loop backwards, 1 ++156: memcpy_long_inner_loop backwards, 2 ++157: memcpy_long_inner_loop backwards, 3 ++ ++ .cfi_def_cfa_offset 16 ++ .cfi_rel_offset D, 0 ++ .cfi_rel_offset DAT1, 4 ++ .cfi_rel_offset DAT2, 8 ++ .cfi_same_value DAT3 ++ .cfi_same_value DAT4 ++ .cfi_same_value DAT5 ++ .cfi_same_value DAT6 ++ .cfi_same_value DAT7 ++ .cfi_rel_offset lr, 12 ++ ++160: /* Medium case */ ++ preload_all backwards, 0, 0, S, N, DAT2, OFF ++ sub N, N, #16 /* simplifies inner loop termination */ ++ .if backwards ++ ands DAT2, D, #15 ++ beq 164f ++ .else ++ ands DAT2, D, #15 ++ beq 164f ++ rsb DAT2, DAT2, #16 ++ .endif ++ memcpy_leading_15bytes backwards, align ++164: /* Destination now 16-byte aligned; we have at least one 16-byte output block */ ++ tst S, #3 ++ bne 140f ++ memcpy_medium_inner_loop backwards, 0 ++140: memcpy_medium_inner_loop backwards, 1 ++ ++170: /* Short case, less than 31 bytes, so no guarantee of at least one 16-byte block */ ++ teq N, #0 ++ beq 199f ++ preload_all backwards, 1, 0, S, N, DAT2, LAST ++ tst D, #3 ++ beq 174f ++172: subs N, N, #1 ++ blo 199f ++ .if backwards ++ ldrb DAT0, [S, #-1]! ++ strb DAT0, [D, #-1]! ++ .else ++ ldrb DAT0, [S], #1 ++ strb DAT0, [D], #1 ++ .endif ++ tst D, #3 ++ bne 172b ++174: /* Destination now 4-byte aligned; we have 0 or more output bytes to go */ ++ tst S, #3 ++ bne 140f ++ memcpy_short_inner_loop backwards, 0 ++140: memcpy_short_inner_loop backwards, 1 ++ ++ .cfi_endproc ++ ++ .unreq D ++ .unreq S ++ .unreq N ++ .unreq DAT0 ++ .unreq DAT1 ++ .unreq DAT2 ++ .unreq DAT3 ++ .unreq DAT4 ++ .unreq DAT5 ++ .unreq DAT6 ++ .unreq DAT7 ++ .unreq LAST ++ .unreq OFF ++.endm +diff --git a/arch/arm/lib/memmove_rpi.S b/arch/arm/lib/memmove_rpi.S +new file mode 100644 +index 0000000..8b0760c +--- /dev/null ++++ b/arch/arm/lib/memmove_rpi.S +@@ -0,0 +1,61 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++#include ++#include "arm-mem.h" ++#include "memcpymove.h" ++ ++/* Prevent the stack from becoming executable */ ++#if defined(__linux__) && defined(__ELF__) ++.section .note.GNU-stack,"",%progbits ++#endif ++ ++ .text ++ .arch armv6 ++ .object_arch armv4 ++ .arm ++ .altmacro ++ .p2align 2 ++ ++/* ++ * void *memmove(void *s1, const void *s2, size_t n); ++ * On entry: ++ * a1 = pointer to destination ++ * a2 = pointer to source ++ * a3 = number of bytes to copy ++ * On exit: ++ * a1 preserved ++ */ ++ ++.set prefetch_distance, 3 ++ ++ENTRY(memmove) ++ cmp a2, a1 ++ bpl memcpy /* pl works even over -1 - 0 and 0x7fffffff - 0x80000000 boundaries */ ++ memcpy 1 ++ENDPROC(memmove) +diff --git a/arch/arm/lib/memset_rpi.S b/arch/arm/lib/memset_rpi.S +new file mode 100644 +index 0000000..2cde883 +--- /dev/null ++++ b/arch/arm/lib/memset_rpi.S +@@ -0,0 +1,121 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++#include ++#include "arm-mem.h" ++ ++/* Prevent the stack from becoming executable */ ++#if defined(__linux__) && defined(__ELF__) ++.section .note.GNU-stack,"",%progbits ++#endif ++ ++ .text ++ .arch armv6 ++ .object_arch armv4 ++ .arm ++ .altmacro ++ .p2align 2 ++ ++/* ++ * void *memset(void *s, int c, size_t n); ++ * On entry: ++ * a1 = pointer to buffer to fill ++ * a2 = byte pattern to fill with (caller-narrowed) ++ * a3 = number of bytes to fill ++ * On exit: ++ * a1 preserved ++ */ ++ENTRY(memset) ++ S .req a1 ++ DAT0 .req a2 ++ N .req a3 ++ DAT1 .req a4 ++ DAT2 .req ip ++ DAT3 .req lr ++ ++ orr DAT0, DAT0, lsl #8 ++ push {S, lr} ++ orr DAT0, DAT0, lsl #16 ++ mov DAT1, DAT0 ++ ++ /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */ ++ cmp N, #31 ++ blo 170f ++ ++161: sub N, N, #16 /* simplifies inner loop termination */ ++ /* Leading words and bytes */ ++ tst S, #15 ++ beq 164f ++ rsb DAT3, S, #0 /* bits 0-3 = number of leading bytes until aligned */ ++ movs DAT2, DAT3, lsl #31 ++ submi N, N, #1 ++ strmib DAT0, [S], #1 ++ subcs N, N, #2 ++ strcsh DAT0, [S], #2 ++ movs DAT2, DAT3, lsl #29 ++ submi N, N, #4 ++ strmi DAT0, [S], #4 ++ subcs N, N, #8 ++ stmcsia S!, {DAT0, DAT1} ++164: /* Delayed set up of DAT2 and DAT3 so we could use them as scratch registers above */ ++ mov DAT2, DAT0 ++ mov DAT3, DAT0 ++ /* Now the inner loop of 16-byte stores */ ++165: stmia S!, {DAT0, DAT1, DAT2, DAT3} ++ subs N, N, #16 ++ bhs 165b ++166: /* Trailing words and bytes */ ++ movs N, N, lsl #29 ++ stmcsia S!, {DAT0, DAT1} ++ strmi DAT0, [S], #4 ++ movs N, N, lsl #2 ++ strcsh DAT0, [S], #2 ++ strmib DAT0, [S] ++199: pop {S, pc} ++ ++170: /* Short case */ ++ mov DAT2, DAT0 ++ mov DAT3, DAT0 ++ tst S, #3 ++ beq 174f ++172: subs N, N, #1 ++ blo 199b ++ strb DAT0, [S], #1 ++ tst S, #3 ++ bne 172b ++174: tst N, #16 ++ stmneia S!, {DAT0, DAT1, DAT2, DAT3} ++ b 166b ++ ++ .unreq S ++ .unreq DAT0 ++ .unreq N ++ .unreq DAT1 ++ .unreq DAT2 ++ .unreq DAT3 ++ENDPROC(memset) +diff --git a/arch/arm/lib/uaccess_with_memcpy.c b/arch/arm/lib/uaccess_with_memcpy.c +index 3e58d71..0622891 100644 +--- a/arch/arm/lib/uaccess_with_memcpy.c ++++ b/arch/arm/lib/uaccess_with_memcpy.c +@@ -22,6 +22,14 @@ + #include + #include + ++#ifndef COPY_FROM_USER_THRESHOLD ++#define COPY_FROM_USER_THRESHOLD 64 ++#endif ++ ++#ifndef COPY_TO_USER_THRESHOLD ++#define COPY_TO_USER_THRESHOLD 64 ++#endif ++ + static int + pin_page_for_write(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp) + { +@@ -85,7 +93,44 @@ pin_page_for_write(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp) + return 1; + } + +-static unsigned long noinline ++static int ++pin_page_for_read(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp) ++{ ++ unsigned long addr = (unsigned long)_addr; ++ pgd_t *pgd; ++ pmd_t *pmd; ++ pte_t *pte; ++ pud_t *pud; ++ spinlock_t *ptl; ++ ++ pgd = pgd_offset(current->mm, addr); ++ if (unlikely(pgd_none(*pgd) || pgd_bad(*pgd))) ++ { ++ return 0; ++ } ++ pud = pud_offset(pgd, addr); ++ if (unlikely(pud_none(*pud) || pud_bad(*pud))) ++ { ++ return 0; ++ } ++ ++ pmd = pmd_offset(pud, addr); ++ if (unlikely(pmd_none(*pmd) || pmd_bad(*pmd))) ++ return 0; ++ ++ pte = pte_offset_map_lock(current->mm, pmd, addr, &ptl); ++ if (unlikely(!pte_present(*pte) || !pte_young(*pte))) { ++ pte_unmap_unlock(pte, ptl); ++ return 0; ++ } ++ ++ *ptep = pte; ++ *ptlp = ptl; ++ ++ return 1; ++} ++ ++unsigned long noinline + __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n) + { + int atomic; +@@ -135,6 +180,54 @@ __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n) + return n; + } + ++unsigned long noinline ++__copy_from_user_memcpy(void *to, const void __user *from, unsigned long n) ++{ ++ int atomic; ++ ++ if (unlikely(segment_eq(get_fs(), KERNEL_DS))) { ++ memcpy(to, (const void *)from, n); ++ return 0; ++ } ++ ++ /* the mmap semaphore is taken only if not in an atomic context */ ++ atomic = in_atomic(); ++ ++ if (!atomic) ++ down_read(¤t->mm->mmap_sem); ++ while (n) { ++ pte_t *pte; ++ spinlock_t *ptl; ++ int tocopy; ++ ++ while (!pin_page_for_read(from, &pte, &ptl)) { ++ char temp; ++ if (!atomic) ++ up_read(¤t->mm->mmap_sem); ++ if (__get_user(temp, (char __user *)from)) ++ goto out; ++ if (!atomic) ++ down_read(¤t->mm->mmap_sem); ++ } ++ ++ tocopy = (~(unsigned long)from & ~PAGE_MASK) + 1; ++ if (tocopy > n) ++ tocopy = n; ++ ++ memcpy(to, (const void *)from, tocopy); ++ to += tocopy; ++ from += tocopy; ++ n -= tocopy; ++ ++ pte_unmap_unlock(pte, ptl); ++ } ++ if (!atomic) ++ up_read(¤t->mm->mmap_sem); ++ ++out: ++ return n; ++} ++ + unsigned long + __copy_to_user(void __user *to, const void *from, unsigned long n) + { +@@ -145,10 +238,25 @@ __copy_to_user(void __user *to, const void *from, unsigned long n) + * With frame pointer disabled, tail call optimization kicks in + * as well making this test almost invisible. + */ +- if (n < 64) ++ if (n < COPY_TO_USER_THRESHOLD) + return __copy_to_user_std(to, from, n); + return __copy_to_user_memcpy(to, from, n); + } ++ ++unsigned long ++__copy_from_user(void *to, const void __user *from, unsigned long n) ++{ ++ /* ++ * This test is stubbed out of the main function above to keep ++ * the overhead for small copies low by avoiding a large ++ * register dump on the stack just to reload them right away. ++ * With frame pointer disabled, tail call optimization kicks in ++ * as well making this test almost invisible. ++ */ ++ if (n < COPY_FROM_USER_THRESHOLD) ++ return __copy_from_user_std(to, from, n); ++ return __copy_from_user_memcpy(to, from, n); ++} + + static unsigned long noinline + __clear_user_memset(void __user *addr, unsigned long n) + +From 58eb5023f30411060f3e905df7b91f3efe9c437c Mon Sep 17 00:00:00 2001 +From: Phil Elwell +Date: Wed, 15 Oct 2014 11:34:37 +0100 +Subject: [PATCH 82/82] bcm2708: Eliminate i2s debugfs directory error + +Qualify the two regmap ranges uses by bcm2708-i2s ('-i2s' and '-clk') +to avoid the name clash when registering debugfs entries. +--- + sound/soc/bcm/bcm2708-i2s.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/sound/soc/bcm/bcm2708-i2s.c b/sound/soc/bcm/bcm2708-i2s.c +index 9023984..3fcb740 100644 +--- a/sound/soc/bcm/bcm2708-i2s.c ++++ b/sound/soc/bcm/bcm2708-i2s.c +@@ -853,6 +853,7 @@ static const struct regmap_config bcm2708_regmap_config[] = { + .precious_reg = bcm2708_i2s_precious_reg, + .volatile_reg = bcm2708_i2s_volatile_reg, + .cache_type = REGCACHE_RBTREE, ++ .name = "i2s", + }, + { + .reg_bits = 32, +@@ -861,6 +862,7 @@ static const struct regmap_config bcm2708_regmap_config[] = { + .max_register = BCM2708_CLK_PCMDIV_REG, + .volatile_reg = bcm2708_clk_volatile_reg, + .cache_type = REGCACHE_RBTREE, ++ .name = "clk", + }, + }; +