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RPi/RPi2: add kernel patch to fix I2S clock
rpi-4.9.y commit 76527b4e6a5dbe55e0b2d8ab533c2388b36c86be This fixes 48kHz samplerate not working on HifiBerry Amp+. See https://github.com/raspberrypi/linux/issues/2016 This patch can be dropped on the next RPi kernel bump. Signed-off-by: Matthias Reichl <hias@horus.com>
This commit is contained in:
Matthias Reichl
parent
2521cb30d5
commit
59be68f4b0
127
projects/RPi/patches/linux/linux-02-RPi_clk_fix.patch
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127
projects/RPi/patches/linux/linux-02-RPi_clk_fix.patch
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From 76527b4e6a5dbe55e0b2d8ab533c2388b36c86be Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.org>
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Date: Mon, 22 May 2017 13:56:41 +0100
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Subject: [PATCH] clk: bcm2835: Minimise clock jitter for PCM clock
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Fractional clock dividers generate accurate average frequencies but
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with jitter, particularly when the integer divisor is small.
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Introduce a new metric of clock accuracy to penalise clocks with a good
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average but worse jitter compared to clocks with an average which is no
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better but with lower jitter. The metric is the ideal rate minus the
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worse deviation from that ideal using the nearest integer divisors.
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Use this metric for parent selection for clocks requiring low jitter
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(currently just PCM).
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Signed-off-by: Phil Elwell <phil@raspberrypi.org>
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---
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drivers/clk/bcm/clk-bcm2835.c | 39 ++++++++++++++++++++++++++++++++++-----
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1 file changed, 34 insertions(+), 5 deletions(-)
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diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
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index c24b4de..db3ba74 100644
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -534,6 +534,7 @@ struct bcm2835_clock_data {
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bool is_vpu_clock;
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bool is_mash_clock;
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+ bool low_jitter;
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u32 tcnt_mux;
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};
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@@ -1154,7 +1155,8 @@ static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
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int parent_idx,
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unsigned long rate,
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u32 *div,
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- unsigned long *prate)
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+ unsigned long *prate,
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+ unsigned long *avgrate)
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{
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struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
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struct bcm2835_cprman *cprman = clock->cprman;
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@@ -1166,11 +1168,33 @@ static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
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parent = clk_hw_get_parent_by_index(hw, parent_idx);
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if (!(BIT(parent_idx) & data->set_rate_parent)) {
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+ unsigned long tmp_rate;
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+
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*prate = clk_hw_get_rate(parent);
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*div = bcm2835_clock_choose_div(hw, rate, *prate, true);
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- return bcm2835_clock_rate_from_divisor(clock, *prate,
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- *div);
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+ tmp_rate = bcm2835_clock_rate_from_divisor(clock, *prate, *div);
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+ *avgrate = tmp_rate;
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+
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+ if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) {
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+ unsigned long high, low;
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+ u32 idiv = *div & ~CM_DIV_FRAC_MASK;
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+
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+ high = bcm2835_clock_rate_from_divisor(clock, *prate,
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+ idiv);
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+ idiv += CM_DIV_FRAC_MASK + 1;
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+ low = bcm2835_clock_rate_from_divisor(clock, *prate,
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+ idiv);
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+
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+ /* Return a value which is the maximum deviation
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+ * below the ideal rate, for use as a metric.
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+ */
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+ if ((tmp_rate - low) < (high - tmp_rate))
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+ tmp_rate = low;
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+ else
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+ tmp_rate -= high - tmp_rate;
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+ }
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+ return tmp_rate;
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}
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if (data->frac_bits)
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@@ -1197,6 +1221,7 @@ static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
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*div = curdiv << CM_DIV_FRAC_BITS;
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*prate = curdiv * best_rate;
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+ *avgrate = best_rate;
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return best_rate;
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}
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@@ -1208,6 +1233,7 @@ static int bcm2835_clock_determine_rate(struct clk_hw *hw,
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bool current_parent_is_pllc;
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unsigned long rate, best_rate = 0;
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unsigned long prate, best_prate = 0;
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+ unsigned long avgrate, best_avgrate = 0;
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size_t i;
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u32 div;
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@@ -1232,11 +1258,13 @@ static int bcm2835_clock_determine_rate(struct clk_hw *hw,
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continue;
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rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate,
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- &div, &prate);
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+ &div, &prate,
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+ &avgrate);
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if (rate > best_rate && rate <= req->rate) {
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best_parent = parent;
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best_prate = prate;
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best_rate = rate;
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+ best_avgrate = avgrate;
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}
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}
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@@ -1246,7 +1274,7 @@ static int bcm2835_clock_determine_rate(struct clk_hw *hw,
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req->best_parent_hw = best_parent;
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req->best_parent_rate = best_prate;
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- req->rate = best_rate;
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+ req->rate = best_avgrate;
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return 0;
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}
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@@ -2061,6 +2089,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
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.int_bits = 12,
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.frac_bits = 12,
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.is_mash_clock = true,
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+ .low_jitter = true,
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.parents = bcm2835_pcm_per_parents,
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.tcnt_mux = 23),
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[BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
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127
projects/RPi2/patches/linux/linux-02-RPi_clk_fix.patch
Normal file
127
projects/RPi2/patches/linux/linux-02-RPi_clk_fix.patch
Normal file
@ -0,0 +1,127 @@
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From 76527b4e6a5dbe55e0b2d8ab533c2388b36c86be Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.org>
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Date: Mon, 22 May 2017 13:56:41 +0100
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Subject: [PATCH] clk: bcm2835: Minimise clock jitter for PCM clock
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Fractional clock dividers generate accurate average frequencies but
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with jitter, particularly when the integer divisor is small.
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Introduce a new metric of clock accuracy to penalise clocks with a good
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average but worse jitter compared to clocks with an average which is no
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better but with lower jitter. The metric is the ideal rate minus the
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worse deviation from that ideal using the nearest integer divisors.
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Use this metric for parent selection for clocks requiring low jitter
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(currently just PCM).
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Signed-off-by: Phil Elwell <phil@raspberrypi.org>
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---
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drivers/clk/bcm/clk-bcm2835.c | 39 ++++++++++++++++++++++++++++++++++-----
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1 file changed, 34 insertions(+), 5 deletions(-)
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diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
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index c24b4de..db3ba74 100644
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -534,6 +534,7 @@ struct bcm2835_clock_data {
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bool is_vpu_clock;
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bool is_mash_clock;
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+ bool low_jitter;
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u32 tcnt_mux;
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};
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@@ -1154,7 +1155,8 @@ static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
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int parent_idx,
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unsigned long rate,
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u32 *div,
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- unsigned long *prate)
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+ unsigned long *prate,
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+ unsigned long *avgrate)
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{
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struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
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struct bcm2835_cprman *cprman = clock->cprman;
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@@ -1166,11 +1168,33 @@ static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
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parent = clk_hw_get_parent_by_index(hw, parent_idx);
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if (!(BIT(parent_idx) & data->set_rate_parent)) {
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+ unsigned long tmp_rate;
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+
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*prate = clk_hw_get_rate(parent);
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*div = bcm2835_clock_choose_div(hw, rate, *prate, true);
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- return bcm2835_clock_rate_from_divisor(clock, *prate,
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- *div);
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+ tmp_rate = bcm2835_clock_rate_from_divisor(clock, *prate, *div);
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+ *avgrate = tmp_rate;
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+
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+ if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) {
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+ unsigned long high, low;
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+ u32 idiv = *div & ~CM_DIV_FRAC_MASK;
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+
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+ high = bcm2835_clock_rate_from_divisor(clock, *prate,
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+ idiv);
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+ idiv += CM_DIV_FRAC_MASK + 1;
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+ low = bcm2835_clock_rate_from_divisor(clock, *prate,
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+ idiv);
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+
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+ /* Return a value which is the maximum deviation
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+ * below the ideal rate, for use as a metric.
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+ */
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+ if ((tmp_rate - low) < (high - tmp_rate))
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+ tmp_rate = low;
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+ else
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+ tmp_rate -= high - tmp_rate;
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+ }
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+ return tmp_rate;
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}
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if (data->frac_bits)
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@@ -1197,6 +1221,7 @@ static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
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*div = curdiv << CM_DIV_FRAC_BITS;
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*prate = curdiv * best_rate;
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+ *avgrate = best_rate;
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return best_rate;
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}
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@@ -1208,6 +1233,7 @@ static int bcm2835_clock_determine_rate(struct clk_hw *hw,
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bool current_parent_is_pllc;
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unsigned long rate, best_rate = 0;
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unsigned long prate, best_prate = 0;
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+ unsigned long avgrate, best_avgrate = 0;
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size_t i;
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u32 div;
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@@ -1232,11 +1258,13 @@ static int bcm2835_clock_determine_rate(struct clk_hw *hw,
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continue;
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rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate,
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- &div, &prate);
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+ &div, &prate,
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+ &avgrate);
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if (rate > best_rate && rate <= req->rate) {
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best_parent = parent;
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best_prate = prate;
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best_rate = rate;
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+ best_avgrate = avgrate;
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}
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}
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@@ -1246,7 +1274,7 @@ static int bcm2835_clock_determine_rate(struct clk_hw *hw,
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req->best_parent_hw = best_parent;
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req->best_parent_rate = best_prate;
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- req->rate = best_rate;
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+ req->rate = best_avgrate;
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return 0;
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}
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@@ -2061,6 +2089,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
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.int_bits = 12,
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.frac_bits = 12,
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.is_mash_clock = true,
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+ .low_jitter = true,
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.parents = bcm2835_pcm_per_parents,
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.tcnt_mux = 23),
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[BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
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