From 5d568f9796ed6b0075a48ff160b994f8c0ca688c Mon Sep 17 00:00:00 2001 From: Lukas Rusak Date: Tue, 12 Apr 2016 22:01:47 -0700 Subject: [PATCH] Allwinner: initial project --- projects/Allwinner/bootloader/install | 4 + projects/Allwinner/bootloader/mkimage | 7 + projects/Allwinner/bootloader/update.sh | 38 + .../Allwinner/devices/A64/bootloader/release | 9 + .../usr/share/alsa/cards/sun50i-a64-audi.conf | 36 + projects/Allwinner/devices/A64/options | 35 + .../A64/patches/linux/01_a64_hdmi_audio.patch | 48 + .../patches/linux/02_hdmi_sound_cell.patch | 11 + .../patches/linux/08-enable-opi-win-ir.patch | 135 + .../Allwinner/devices/H3/bootloader/release | 9 + .../usr/share/alsa/cards/H3_Audio_Codec.conf | 36 + projects/Allwinner/devices/H3/options | 44 + .../linux/16-H3-add-HDMI-sound-nodes.patch | 56 + .../Allwinner/devices/H6/bootloader/release | 9 + projects/Allwinner/devices/H6/options | 35 + .../H6/patches/linux/01-add-mali-node.patch | 111 + .../02-allow-changing-gpu-parent-rate.patch | 13 + .../devices/H6/patches/linux/03-VPU.patch | 240 + .../devices/H6/patches/linux/04-dma.patch | 658 ++ .../H6/patches/linux/05-sound-hack.patch | 142 + .../linux/06-cedrus-increase-frequency.patch | 25 + .../linux/07-limit-max-pixel-clock.patch | 20 + .../H6/patches/linux/08-clock-fixes.patch | 96 + .../H6/patches/u-boot/001-update-dt.patch | 608 ++ .../lib/systemd/system/serial-console.service | 23 + .../usr/share/alsa/cards/allwinner-hdmi.conf | 34 + .../usr/share/alsa/cards/allwinner-spdif.conf | 34 + projects/Allwinner/kodi/appliance.xml | 22 + projects/Allwinner/linux/linux.aarch64.conf | 5620 +++++++++++++++++ projects/Allwinner/linux/linux.arm.conf | 5282 ++++++++++++++++ projects/Allwinner/options | 84 + .../0001-Remove-check-for-sw-format.patch | 18 + .../Allwinner/patches/kodi/0002-guisize.patch | 153 + .../linux/0001-hdmi-sound-improvements.patch | 1864 ++++++ .../patches/linux/0002-fixes-from-5.1.patch | 1824 ++++++ .../patches/linux/0003-fixes-from-5.2.patch | 676 ++ ...dia-cedrus-Add-H264-decoding-support.patch | 1420 +++++ ...tateless-support-for-V4L2-and-Cedrus.patch | 1628 +++++ .../linux/0007-H264-improvements.patch | 133 + .../linux/0008-HEVC-improvements.patch | 703 +++ .../patches/linux/0009-cedrus-h264-4k.patch | 358 ++ ...WIP-dw-hdmi-cec-sleep-100ms-on-error.patch | 62 + .../patches/linux/0013-cec-improvements.patch | 232 + .../0018-cedrus-increase-frequency.patch | 25 + ...3-Add-support-for-the-Beelink-x2-STB.patch | 280 + .../u-boot/002-disable-usb-keyboard.patch | 13 + .../patches/u-boot/003-fix-hdmi-clocks.patch | 135 + 47 files changed, 23048 insertions(+) create mode 100644 projects/Allwinner/bootloader/install create mode 100644 projects/Allwinner/bootloader/mkimage create mode 100644 projects/Allwinner/bootloader/update.sh create mode 100644 projects/Allwinner/devices/A64/bootloader/release create mode 100644 projects/Allwinner/devices/A64/filesystem/usr/share/alsa/cards/sun50i-a64-audi.conf create mode 100644 projects/Allwinner/devices/A64/options create mode 100644 projects/Allwinner/devices/A64/patches/linux/01_a64_hdmi_audio.patch create mode 100644 projects/Allwinner/devices/A64/patches/linux/02_hdmi_sound_cell.patch create mode 100644 projects/Allwinner/devices/A64/patches/linux/08-enable-opi-win-ir.patch create mode 100644 projects/Allwinner/devices/H3/bootloader/release create mode 100644 projects/Allwinner/devices/H3/filesystem/usr/share/alsa/cards/H3_Audio_Codec.conf create mode 100644 projects/Allwinner/devices/H3/options create mode 100644 projects/Allwinner/devices/H3/patches/linux/16-H3-add-HDMI-sound-nodes.patch create mode 100644 projects/Allwinner/devices/H6/bootloader/release create mode 100644 projects/Allwinner/devices/H6/options create mode 100644 projects/Allwinner/devices/H6/patches/linux/01-add-mali-node.patch create mode 100644 projects/Allwinner/devices/H6/patches/linux/02-allow-changing-gpu-parent-rate.patch create mode 100644 projects/Allwinner/devices/H6/patches/linux/03-VPU.patch create mode 100644 projects/Allwinner/devices/H6/patches/linux/04-dma.patch create mode 100644 projects/Allwinner/devices/H6/patches/linux/05-sound-hack.patch create mode 100644 projects/Allwinner/devices/H6/patches/linux/06-cedrus-increase-frequency.patch create mode 100644 projects/Allwinner/devices/H6/patches/linux/07-limit-max-pixel-clock.patch create mode 100644 projects/Allwinner/devices/H6/patches/linux/08-clock-fixes.patch create mode 100644 projects/Allwinner/devices/H6/patches/u-boot/001-update-dt.patch create mode 100644 projects/Allwinner/filesystem/usr/lib/systemd/system/serial-console.service create mode 100644 projects/Allwinner/filesystem/usr/share/alsa/cards/allwinner-hdmi.conf create mode 100644 projects/Allwinner/filesystem/usr/share/alsa/cards/allwinner-spdif.conf create mode 100644 projects/Allwinner/kodi/appliance.xml create mode 100644 projects/Allwinner/linux/linux.aarch64.conf create mode 100644 projects/Allwinner/linux/linux.arm.conf create mode 100644 projects/Allwinner/options create mode 100644 projects/Allwinner/patches/kodi/0001-Remove-check-for-sw-format.patch create mode 100644 projects/Allwinner/patches/kodi/0002-guisize.patch create mode 100644 projects/Allwinner/patches/linux/0001-hdmi-sound-improvements.patch create mode 100644 projects/Allwinner/patches/linux/0002-fixes-from-5.1.patch create mode 100644 projects/Allwinner/patches/linux/0003-fixes-from-5.2.patch create mode 100644 projects/Allwinner/patches/linux/0005-media-cedrus-Add-H264-decoding-support.patch create mode 100644 projects/Allwinner/patches/linux/0006-HEVC-H.265-stateless-support-for-V4L2-and-Cedrus.patch create mode 100644 projects/Allwinner/patches/linux/0007-H264-improvements.patch create mode 100644 projects/Allwinner/patches/linux/0008-HEVC-improvements.patch create mode 100644 projects/Allwinner/patches/linux/0009-cedrus-h264-4k.patch create mode 100644 projects/Allwinner/patches/linux/0010-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch create mode 100644 projects/Allwinner/patches/linux/0013-cec-improvements.patch create mode 100644 projects/Allwinner/patches/linux/0018-cedrus-increase-frequency.patch create mode 100644 projects/Allwinner/patches/u-boot/001-sun8i-h3-Add-support-for-the-Beelink-x2-STB.patch create mode 100644 projects/Allwinner/patches/u-boot/002-disable-usb-keyboard.patch create mode 100644 projects/Allwinner/patches/u-boot/003-fix-hdmi-clocks.patch diff --git a/projects/Allwinner/bootloader/install b/projects/Allwinner/bootloader/install new file mode 100644 index 0000000000..dbaeabee4b --- /dev/null +++ b/projects/Allwinner/bootloader/install @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2016-present Team LibreELEC (https://libreelec.tv) + +cp -av u-boot-sunxi-with-spl.bin $INSTALL/usr/share/bootloader diff --git a/projects/Allwinner/bootloader/mkimage b/projects/Allwinner/bootloader/mkimage new file mode 100644 index 0000000000..e9a02ed50e --- /dev/null +++ b/projects/Allwinner/bootloader/mkimage @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2016-present Team LibreELEC (https://libreelec.tv) + +if [ -f "$RELEASE_DIR/3rdparty/bootloader/u-boot-sunxi-with-spl.bin" ]; then + echo "Writing U-Boot to $(basename $DISK)" + dd if="$RELEASE_DIR/3rdparty/bootloader/u-boot-sunxi-with-spl.bin" of="$DISK" bs=1K seek=8 conv=fsync,notrunc >"$SAVE_ERROR" 2>&1 || show_error +fi diff --git a/projects/Allwinner/bootloader/update.sh b/projects/Allwinner/bootloader/update.sh new file mode 100644 index 0000000000..1b89f372d6 --- /dev/null +++ b/projects/Allwinner/bootloader/update.sh @@ -0,0 +1,38 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2016-present Team LibreELEC (https://libreelec.tv) + +[ -z "$BOOT_ROOT" ] && BOOT_ROOT="/flash" +[ -z "$BOOT_PART" ] && BOOT_PART=$(df "$BOOT_ROOT" | tail -1 | awk {' print $1 '}) +if [ -z "$BOOT_DISK" ]; then + case $BOOT_PART in + /dev/sd[a-z][0-9]*) + BOOT_DISK=$(echo $BOOT_PART | sed -e "s,[0-9]*,,g") + ;; + /dev/mmcblk*) + BOOT_DISK=$(echo $BOOT_PART | sed -e "s,p[0-9]*,,g") + ;; + esac +fi + +# mount $BOOT_ROOT r/w + mount -o remount,rw $BOOT_ROOT + +# update Device Tree Blobs + for all_dtb in /flash/*.dtb; do + dtb=$(basename $all_dtb) + if [ -f $SYSTEM_ROOT/usr/share/bootloader/$dtb ]; then + echo "*** updating Device Tree Blob: $dtb ..." + cp -p $SYSTEM_ROOT/usr/share/bootloader/$dtb $BOOT_ROOT + fi + done + +# update bootloader files + if [ -f $SYSTEM_ROOT/usr/share/bootloader/u-boot-sunxi-with-spl.bin ]; then + echo "*** updating U-Boot on: $BOOT_DISK ..." + dd if=$SYSTEM_ROOT/usr/share/bootloader/u-boot-sunxi-with-spl.bin of="$BOOT_DISK" bs=1k seek=8 conv=fsync &>/dev/null + fi + +# mount $BOOT_ROOT r/o + sync + mount -o remount,ro $BOOT_ROOT diff --git a/projects/Allwinner/devices/A64/bootloader/release b/projects/Allwinner/devices/A64/bootloader/release new file mode 100644 index 0000000000..682f6d2ae4 --- /dev/null +++ b/projects/Allwinner/devices/A64/bootloader/release @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv) + +mkdir -p $RELEASE_DIR/3rdparty/bootloader + if [ -n "$UBOOT_SYSTEM" ]; then + cp -a $(get_build_dir $BOOTLOADER)/u-boot-sunxi-with-spl.bin $RELEASE_DIR/3rdparty/bootloader + fi + + cp -a $(get_build_dir linux)/arch/$TARGET_KERNEL_ARCH/boot/dts/allwinner/sun50i-a64-*.dtb $RELEASE_DIR/3rdparty/bootloader diff --git a/projects/Allwinner/devices/A64/filesystem/usr/share/alsa/cards/sun50i-a64-audi.conf b/projects/Allwinner/devices/A64/filesystem/usr/share/alsa/cards/sun50i-a64-audi.conf new file mode 100644 index 0000000000..4f5a44708e --- /dev/null +++ b/projects/Allwinner/devices/A64/filesystem/usr/share/alsa/cards/sun50i-a64-audi.conf @@ -0,0 +1,36 @@ +# +# Configuration for H3 analog output +# + + + +sun50i-a64-audi.pcm.front.0 { + @args [ CARD ] + @args.CARD { + type string + } + type hooks + slave.pcm { + type hw + card $CARD + } + hooks.0 { + type ctl_elems + hook_args [ + { + name "Line Out Playback Volume" + lock true + preserve true + optional false + value 31 + } + { + name "Line Out Playback Switch" + lock true + preserve true + optional false + value [ on on ] + } + ] + } +} diff --git a/projects/Allwinner/devices/A64/options b/projects/Allwinner/devices/A64/options new file mode 100644 index 0000000000..f2794bbd5e --- /dev/null +++ b/projects/Allwinner/devices/A64/options @@ -0,0 +1,35 @@ +################################################################################ +# setup system defaults +################################################################################ + + # The TARGET_CPU variable controls which processor should be targeted for + # generated code. + case $TARGET_ARCH in + aarch64) + TARGET_CPU="cortex-a53" + TARGET_CPU_FLAGS="+crc+crypto" + TARGET_FEATURES="64bit" + TARGET_KERNEL_ARCH="arm64" + ;; + arm) + TARGET_KERNEL_ARCH="arm64" + TARGET_PATCH_ARCH="aarch64" + TARGET_FLOAT="hard" + TARGET_CPU="cortex-a53" + TARGET_CPU_FLAGS="+crc" + TARGET_FPU="crypto-neon-fp-armv8" + TARGET_FEATURES="32bit" + ;; + esac + + # Kernel target + KERNEL_TARGET="Image" + + # ATF platform + ATF_PLATFORM="sun50i_a64" + + # additional drivers to install: + ADDITIONAL_DRIVERS="$ADDITIONAL_DRIVERS gpu-sunxi" + + # Mali GPU family + MALI_FAMILY="400" diff --git a/projects/Allwinner/devices/A64/patches/linux/01_a64_hdmi_audio.patch b/projects/Allwinner/devices/A64/patches/linux/01_a64_hdmi_audio.patch new file mode 100644 index 0000000000..fbfb8be5bf --- /dev/null +++ b/projects/Allwinner/devices/A64/patches/linux/01_a64_hdmi_audio.patch @@ -0,0 +1,48 @@ +Date: Sun, 3 Dec 2017 11:43:08 -0800 +Subject: [PATCH] Add A64 HDMI sound node + +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 29 +++++++++++++++++++ + 2 files changed, 47 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index 0f69f35939755..0b44018361cbf 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -727,6 +727,36 @@ + status = "disabled"; + }; + ++ i2s2: i2s@1c22800 { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sun8i-h3-i2s"; ++ reg = <0x01c22800 0x400>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; ++ clock-names = "apb", "mod"; ++ dmas = <&dma 27>; ++ resets = <&ccu RST_BUS_I2S2>; ++ dma-names = "tx"; ++ allwinner,playback-channels = <8>; ++ }; ++ ++ sound_hdmi: sound_hdmi { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "allwinner-hdmi"; ++ simple-audio-card,mclk-fs = <256>; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s2>; ++ dai-tdm-slot-num = <2>; ++ dai-tdm-slot-width = <32>; ++ }; ++ }; ++ + rtc: rtc@1f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; diff --git a/projects/Allwinner/devices/A64/patches/linux/02_hdmi_sound_cell.patch b/projects/Allwinner/devices/A64/patches/linux/02_hdmi_sound_cell.patch new file mode 100644 index 0000000000..5fbe486aee --- /dev/null +++ b/projects/Allwinner/devices/A64/patches/linux/02_hdmi_sound_cell.patch @@ -0,0 +1,11 @@ +diff -Nur a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi 2018-11-17 18:26:20.000000000 +0100 ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi 2018-11-17 19:29:15.132911602 +0100 +@@ -892,6 +892,7 @@ + }; + + hdmi: hdmi@1ee0000 { ++ #sound-dai-cells = <0>; + compatible = "allwinner,sun50i-a64-dw-hdmi", + "allwinner,sun8i-a83t-dw-hdmi"; + reg = <0x01ee0000 0x10000>; diff --git a/projects/Allwinner/devices/A64/patches/linux/08-enable-opi-win-ir.patch b/projects/Allwinner/devices/A64/patches/linux/08-enable-opi-win-ir.patch new file mode 100644 index 0000000000..7953defbbc --- /dev/null +++ b/projects/Allwinner/devices/A64/patches/linux/08-enable-opi-win-ir.patch @@ -0,0 +1,135 @@ +From c642dca33a893b38770003f92de5708b2ef82878 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Thu, 10 Jan 2019 20:00:25 +0100 +Subject: [PATCH 1/4] media: dt: bindings: sunxi-ir: Add A64 compatible + +A64 IR is compatible with A13, so add A64 compatible with A13 as a +fallback. + +Signed-off-by: Jernej Skrabec +--- + Documentation/devicetree/bindings/media/sunxi-ir.txt | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt b/Documentation/devicetree/bindings/media/sunxi-ir.txt +index 278098987edb..ecac6964b69b 100644 +--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt ++++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt +@@ -1,7 +1,10 @@ + Device-Tree bindings for SUNXI IR controller found in sunXi SoC family + + Required properties: +-- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir" ++- compatible : value must be one of: ++ * "allwinner,sun4i-a10-ir" ++ * "allwinner,sun5i-a13-ir" ++ * "allwinner,sun50i-a64-ir", "allwinner,sun5i-a13-ir" + - clocks : list of clock specifiers, corresponding to + entries in clock-names property; + - clock-names : should contain "apb" and "ir" entries; +-- +2.20.1 + + +From 85923b765bbd31be033a7b7d8bf0018accb386dd Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Thu, 10 Jan 2019 20:50:15 +0100 +Subject: [PATCH 2/4] arm64: dts: allwinner: a64: Add IR pinmux + +IR on A64 has a dedicated pin. Add pinmux setting for it. + +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index 839b2ae88583..86ff1d3a4ffa 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -1043,6 +1043,11 @@ + function = "s_i2c"; + }; + ++ r_ir_pins: ir-pins { ++ pins = "PL11"; ++ function = "s_cir_rx"; ++ }; ++ + r_pwm_pin: pwm { + pins = "PL10"; + function = "s_pwm"; +-- +2.20.1 + + +From 943855104927268a641bd4f5f35c0592398e39ec Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Thu, 10 Jan 2019 20:19:32 +0100 +Subject: [PATCH 3/4] arm64: dts: allwinner: a64: Add IR node + +IR is similar to that in A13 and can use same driver. + +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index 86ff1d3a4ffa..8238caedd90e 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -1004,6 +1004,17 @@ + status = "disabled"; + }; + ++ r_ir: ir@1f02000 { ++ compatible = "allwinner,sun50i-a64-ir", ++ "allwinner,sun5i-a13-ir"; ++ reg = <0x01f02000 0x400>; ++ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; ++ clock-names = "apb", "ir"; ++ resets = <&r_ccu RST_APB0_IR>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ + r_i2c: i2c@1f02400 { + compatible = "allwinner,sun50i-a64-i2c", + "allwinner,sun6i-a31-i2c"; +-- +2.20.1 + + +From 3020e7d85fe574cda8e6803330ffd75fffdbbf6b Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Thu, 10 Jan 2019 20:25:18 +0100 +Subject: [PATCH 4/4] arm64: dts: allwinner: a64: Orange Pi Win: Enable IR + +OrangePi Win board contains IR receiver. Enable it. + +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +index b0c64f75792c..c6c759511f5e 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +@@ -144,6 +144,12 @@ + }; + }; + ++&r_ir { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&r_ir_pins>; ++ status = "okay"; ++}; ++ + &mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; +-- +2.20.1 + diff --git a/projects/Allwinner/devices/H3/bootloader/release b/projects/Allwinner/devices/H3/bootloader/release new file mode 100644 index 0000000000..fadd618a05 --- /dev/null +++ b/projects/Allwinner/devices/H3/bootloader/release @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2016-present Team LibreELEC (https://libreelec.tv) + +mkdir -p $RELEASE_DIR/3rdparty/bootloader + if [ -n "$UBOOT_SYSTEM" ]; then + cp -a $(get_build_dir $BOOTLOADER)/u-boot-sunxi-with-spl.bin $RELEASE_DIR/3rdparty/bootloader + fi + + cp -a $(get_build_dir linux)/arch/$TARGET_KERNEL_ARCH/boot/dts/sun8i-h3-*.dtb $RELEASE_DIR/3rdparty/bootloader diff --git a/projects/Allwinner/devices/H3/filesystem/usr/share/alsa/cards/H3_Audio_Codec.conf b/projects/Allwinner/devices/H3/filesystem/usr/share/alsa/cards/H3_Audio_Codec.conf new file mode 100644 index 0000000000..1331fd6ad4 --- /dev/null +++ b/projects/Allwinner/devices/H3/filesystem/usr/share/alsa/cards/H3_Audio_Codec.conf @@ -0,0 +1,36 @@ +# +# Configuration for H3 analog output +# + + + +H3_Audio_Codec.pcm.front.0 { + @args [ CARD ] + @args.CARD { + type string + } + type hooks + slave.pcm { + type hw + card $CARD + } + hooks.0 { + type ctl_elems + hook_args [ + { + name "Line Out Playback Volume" + lock true + preserve true + optional false + value 31 + } + { + name "Line Out Playback Switch" + lock true + preserve true + optional false + value [ on on ] + } + ] + } +} diff --git a/projects/Allwinner/devices/H3/options b/projects/Allwinner/devices/H3/options new file mode 100644 index 0000000000..d81632549e --- /dev/null +++ b/projects/Allwinner/devices/H3/options @@ -0,0 +1,44 @@ +################################################################################ +# setup system defaults +################################################################################ + + # The TARGET_CPU variable controls which processor should be targeted for + # generated code. + case $TARGET_ARCH in + arm) + # TARGET_CPU: + # arm2 arm250 arm3 arm6 arm60 arm600 arm610 arm620 arm7 arm7m arm7d + # arm7dm arm7di arm7dmi arm70 arm700 arm700i arm710 arm710c + # arm7100 arm720 arm7500 arm7500fe arm7tdmi arm7tdmi-s arm710t + # arm720t arm740t strongarm strongarm110 strongarm1100 + # strongarm1110 arm8 arm810 arm9 arm9e arm920 arm920t arm922t + # arm946e-s arm966e-s arm968e-s arm926ej-s arm940t arm9tdmi + # arm10tdmi arm1020t arm1026ej-s arm10e arm1020e arm1022e + # arm1136j-s arm1136jf-s mpcore mpcorenovfp arm1156t2-s + # arm1176jz-s arm1176jzf-s cortex-a8 cortex-a9 cortex-r4 + # cortex-r4f cortex-m3 cortex-m1 xscale iwmmxt iwmmxt2 ep9312. + TARGET_CPU="cortex-a7" + + # TARGET_FLOAT: + # Specifies which floating-point ABI to use. Permissible values are: + # soft softfp hard + TARGET_FLOAT="hard" + + # TARGET_FPU: + # This specifies what floating point hardware (or hardware emulation) is + # available on the target. Permissible names are: + # fpa fpe2 fpe3 maverick vfp vfpv3 vfpv3-fp16 vfpv3-d16 vfpv3-d16-fp16 + # vfpv3xd vfpv3xd-fp16 neon neon-fp16 vfpv4 vfpv4-d16 fpv4-sp-d16 + # neon-vfpv4. + TARGET_FPU="neon-vfpv4" + ;; + esac + + # Kernel target + KERNEL_TARGET="zImage" + + # additional drivers to install: + ADDITIONAL_DRIVERS="$ADDITIONAL_DRIVERS gpu-sunxi" + + # Mali GPU family + MALI_FAMILY="400" diff --git a/projects/Allwinner/devices/H3/patches/linux/16-H3-add-HDMI-sound-nodes.patch b/projects/Allwinner/devices/H3/patches/linux/16-H3-add-HDMI-sound-nodes.patch new file mode 100644 index 0000000000..607068c2c8 --- /dev/null +++ b/projects/Allwinner/devices/H3/patches/linux/16-H3-add-HDMI-sound-nodes.patch @@ -0,0 +1,56 @@ +diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi +index 8aa2befc..d3d70eac 100644 +--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi ++++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi +@@ -53,6 +53,23 @@ + #address-cells = <1>; + #size-cells = <1>; + ++ sound_hdmi: sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "allwinner-hdmi"; ++ simple-audio-card,mclk-fs = <256>; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s2>; ++ dai-tdm-slot-num = <2>; ++ dai-tdm-slot-width = <32>; ++ }; ++ }; ++ + clocks { + #address-cells = <1>; + #size-cells = <1>; +@@ -631,6 +648,19 @@ + status = "disabled"; + }; + ++ i2s2: i2s@1c22800 { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sun8i-h3-i2s"; ++ reg = <0x01c22800 0x400>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; ++ clock-names = "apb", "mod"; ++ dmas = <&dma 27>; ++ resets = <&ccu RST_BUS_I2S2>; ++ dma-names = "tx"; ++ allwinner,playback-channels = <8>; ++ }; ++ + codec: codec@1c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-h3-codec"; +@@ -110,6 +126,7 @@ + }; + + hdmi: hdmi@1ee0000 { ++ #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-h3-dw-hdmi", + "allwinner,sun8i-a83t-dw-hdmi"; + reg = <0x01ee0000 0x10000>; diff --git a/projects/Allwinner/devices/H6/bootloader/release b/projects/Allwinner/devices/H6/bootloader/release new file mode 100644 index 0000000000..30058f2207 --- /dev/null +++ b/projects/Allwinner/devices/H6/bootloader/release @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv) + +mkdir -p $RELEASE_DIR/3rdparty/bootloader + if [ -n "$UBOOT_SYSTEM" ]; then + cp -a $(get_build_dir $BOOTLOADER)/u-boot-sunxi-with-spl.bin $RELEASE_DIR/3rdparty/bootloader + fi + + cp -a $(get_build_dir linux)/arch/$TARGET_KERNEL_ARCH/boot/dts/allwinner/sun50i-h6-*.dtb $RELEASE_DIR/3rdparty/bootloader diff --git a/projects/Allwinner/devices/H6/options b/projects/Allwinner/devices/H6/options new file mode 100644 index 0000000000..7d66ff14b1 --- /dev/null +++ b/projects/Allwinner/devices/H6/options @@ -0,0 +1,35 @@ +################################################################################ +# setup system defaults +################################################################################ + + # The TARGET_CPU variable controls which processor should be targeted for + # generated code. + case $TARGET_ARCH in + aarch64) + TARGET_CPU="cortex-a53" + TARGET_CPU_FLAGS="+crc+crypto" + TARGET_FEATURES="64bit" + TARGET_KERNEL_ARCH="arm64" + ;; + arm) + TARGET_KERNEL_ARCH="arm64" + TARGET_PATCH_ARCH="aarch64" + TARGET_FLOAT="hard" + TARGET_CPU="cortex-a53" + TARGET_CPU_FLAGS="+crc" + TARGET_FPU="crypto-neon-fp-armv8" + TARGET_FEATURES="32bit" + ;; + esac + + # Kernel target + KERNEL_TARGET="Image" + + # ATF platform + ATF_PLATFORM="sun50i_h6" + + # additional drivers to install: + ADDITIONAL_DRIVERS="$ADDITIONAL_DRIVERS gpu-sunxi-midgard" + + # Mali GPU family + MALI_FAMILY="t720" diff --git a/projects/Allwinner/devices/H6/patches/linux/01-add-mali-node.patch b/projects/Allwinner/devices/H6/patches/linux/01-add-mali-node.patch new file mode 100644 index 0000000000..4f7213a10f --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/linux/01-add-mali-node.patch @@ -0,0 +1,111 @@ +diff -Nur a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi 2018-03-28 20:27:22.000000000 +0200 ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi 2018-04-16 19:28:43.842331161 +0200 +@@ -35,6 +35,72 @@ + }; + }; + ++ gpu_opp_table: opp_table1 { ++ compatible = "operating-points-v2", ++ "operating-points-v2-mali"; ++ ++ opp@756000000 { ++ opp-hz = /bits/ 64 <756000000>; ++ opp-microvolt = <1040000>; ++ }; ++ opp@624000000 { ++ opp-hz = /bits/ 64 <624000000>; ++ opp-microvolt = <950000>; ++ }; ++ opp@576000000 { ++ opp-hz = /bits/ 64 <576000000>; ++ opp-microvolt = <930000>; ++ }; ++ opp@540000000 { ++ opp-hz = /bits/ 64 <540000000>; ++ opp-microvolt = <910000>; ++ }; ++ opp@504000000 { ++ opp-hz = /bits/ 64 <504000000>; ++ opp-microvolt = <890000>; ++ }; ++ opp@456000000 { ++ opp-hz = /bits/ 64 <456000000>; ++ opp-microvolt = <870000>; ++ }; ++ opp@432000000 { ++ opp-hz = /bits/ 64 <432000000>; ++ opp-microvolt = <860000>; ++ }; ++ opp@420000000 { ++ opp-hz = /bits/ 64 <420000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp@408000000 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <840000>; ++ }; ++ opp@384000000 { ++ opp-hz = /bits/ 64 <384000000>; ++ opp-microvolt = <830000>; ++ }; ++ opp@360000000 { ++ opp-hz = /bits/ 64 <360000000>; ++ opp-microvolt = <820000>; ++ }; ++ opp@336000000 { ++ opp-hz = /bits/ 64 <336000000>; ++ opp-microvolt = <810000>; ++ }; ++ opp@312000000 { ++ opp-hz = /bits/ 64 <312000000>; ++ opp-microvolt = <810000>; ++ }; ++ opp@264000000 { ++ opp-hz = /bits/ 64 <264000000>; ++ opp-microvolt = <810000>; ++ }; ++ opp@216000000 { ++ opp-hz = /bits/ 64 <216000000>; ++ opp-microvolt = <810000>; ++ }; ++ }; ++ + cpus { + #address-cells = <1>; + #size-cells = <0>; +@@ -162,6 +228,20 @@ + }; + }; + ++ gpu: gpu@1800000 { ++ compatible = "arm,malit720", "arm,malit72x", "arm,malit7xx", "arm,mali-midgard"; ++ reg = <0x01800000 0x4000>; ++ interrupts = , ++ , ++ ; ++ interrupt-names = "JOB", "MMU", "GPU"; ++ ++ clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; ++ clock-names = "clk_mali", "clk_bus_mali"; ++ resets = <&ccu RST_BUS_GPU>; ++ operating-points-v2 = <&gpu_opp_table>; ++ }; ++ + syscon: syscon@3000000 { + compatible = "allwinner,sun50i-h6-system-controller", + "syscon"; +diff -Nur a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts 2018-03-28 20:27:22.000000000 +0200 ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts 2018-04-14 15:34:15.545094216 +0200 +@@ -89,6 +89,10 @@ + status = "okay"; + }; + ++&gpu { ++ mali-supply = <®_dcdcc>; ++}; ++ + &hdmi { + status = "okay"; + }; diff --git a/projects/Allwinner/devices/H6/patches/linux/02-allow-changing-gpu-parent-rate.patch b/projects/Allwinner/devices/H6/patches/linux/02-allow-changing-gpu-parent-rate.patch new file mode 100644 index 0000000000..7054bf24b5 --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/linux/02-allow-changing-gpu-parent-rate.patch @@ -0,0 +1,13 @@ +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +index 8a81f764abd0..46b72f2ed5cd 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +@@ -288,7 +288,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670, + 0, 3, /* M */ + 24, 1, /* mux */ + BIT(31), /* gate */ +- 0); ++ CLK_SET_RATE_PARENT); + + static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2", + 0x67c, BIT(0), 0); diff --git a/projects/Allwinner/devices/H6/patches/linux/03-VPU.patch b/projects/Allwinner/devices/H6/patches/linux/03-VPU.patch new file mode 100644 index 0000000000..53eb2a0463 --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/linux/03-VPU.patch @@ -0,0 +1,240 @@ +From ed19ec00d4d62a74857ad9c2ea1dbf9671ac3580 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 28 Jan 2019 19:36:54 +0100 +Subject: [PATCH 1/6] dt-bindings: media: cedrus: Add H6 compatible + +This adds a compatible for H6. H6 VPU supports 10-bit HEVC decoding and +additional AFBC output format for HEVC. + +Signed-off-by: Jernej Skrabec +--- + Documentation/devicetree/bindings/media/cedrus.txt | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/media/cedrus.txt b/Documentation/devicetree/bindings/media/cedrus.txt +index bce0705df953..20c82fb0c343 100644 +--- a/Documentation/devicetree/bindings/media/cedrus.txt ++++ b/Documentation/devicetree/bindings/media/cedrus.txt +@@ -13,6 +13,7 @@ Required properties: + - "allwinner,sun8i-h3-video-engine" + - "allwinner,sun50i-a64-video-engine" + - "allwinner,sun50i-h5-video-engine" ++ - "allwinner,sun50i-h6-video-engine" + - reg : register base and length of VE; + - clocks : list of clock specifiers, corresponding to entries in + the clock-names property; +-- +2.20.1 + + +From bb6b00e1225a5b382b723d3c2190429e15a4c607 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 28 Jan 2019 19:45:38 +0100 +Subject: [PATCH 2/6] media: cedrus: Add a quirk for not setting DMA offset + +H6 VPU doesn't work if DMA offset is set. + +Add a quirk for it. + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus.h | 3 +++ + drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 3 ++- + 2 files changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h +index 4aedd24a9848..c57c04b41d2e 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h +@@ -28,6 +28,8 @@ + + #define CEDRUS_CAPABILITY_UNTILED BIT(0) + ++#define CEDRUS_QUIRK_NO_DMA_OFFSET BIT(0) ++ + enum cedrus_codec { + CEDRUS_CODEC_MPEG2, + +@@ -91,6 +93,7 @@ struct cedrus_dec_ops { + + struct cedrus_variant { + unsigned int capabilities; ++ unsigned int quirks; + }; + + struct cedrus_dev { +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +index 0acf219a8c91..fbfff7c1c771 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +@@ -177,7 +177,8 @@ int cedrus_hw_probe(struct cedrus_dev *dev) + */ + + #ifdef PHYS_PFN_OFFSET +- dev->dev->dma_pfn_offset = PHYS_PFN_OFFSET; ++ if (!(variant->quirks & CEDRUS_QUIRK_NO_DMA_OFFSET)) ++ dev->dev->dma_pfn_offset = PHYS_PFN_OFFSET; + #endif + + ret = of_reserved_mem_device_init(dev->dev); +-- +2.20.1 + + +From 744c66f8c328ef40b6fb246f8b9f2daa9cce4d9d Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 28 Jan 2019 19:47:33 +0100 +Subject: [PATCH 3/6] media: cedrus: Add support for H6 + +H6 has improved VPU. It supports 10-bit HEVC decoding and AFBC output +format for HEVC. + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c +index ff11cbeba205..b98add3cdedd 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c +@@ -396,6 +396,11 @@ static const struct cedrus_variant sun50i_h5_cedrus_variant = { + .capabilities = CEDRUS_CAPABILITY_UNTILED, + }; + ++static const struct cedrus_variant sun50i_h6_cedrus_variant = { ++ .capabilities = CEDRUS_CAPABILITY_UNTILED | CEDRUS_CAPABILITY_H265_DEC, ++ .quirks = CEDRUS_QUIRK_NO_DMA_OFFSET, ++}; ++ + static const struct of_device_id cedrus_dt_match[] = { + { + .compatible = "allwinner,sun4i-a10-video-engine", +@@ -425,6 +430,10 @@ static const struct of_device_id cedrus_dt_match[] = { + .compatible = "allwinner,sun50i-h5-video-engine", + .data = &sun50i_h5_cedrus_variant, + }, ++ { ++ .compatible = "allwinner,sun50i-h6-video-engine", ++ .data = &sun50i_h6_cedrus_variant, ++ }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, cedrus_dt_match); +-- +2.20.1 + + +From b4ca53c594950b80d71ac320b3505a303e7f6092 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 28 Jan 2019 20:05:47 +0100 +Subject: [PATCH 4/6] dt-bindings: sram: sunxi: Add compatible for the H6 SRAM + C1 + +This introduces a new compatible for the H6 SRAM C1 section, that is +compatible with the SRAM C1 section as found on the A10. + +Signed-off-by: Jernej Skrabec +--- + Documentation/devicetree/bindings/sram/sunxi-sram.txt | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/sram/sunxi-sram.txt b/Documentation/devicetree/bindings/sram/sunxi-sram.txt +index ab5a70bb9a64..380246a805f2 100644 +--- a/Documentation/devicetree/bindings/sram/sunxi-sram.txt ++++ b/Documentation/devicetree/bindings/sram/sunxi-sram.txt +@@ -63,6 +63,7 @@ The valid sections compatible for H5 are: + + The valid sections compatible for H6 are: + - allwinner,sun50i-h6-sram-c, allwinner,sun50i-a64-sram-c ++ - allwinner,sun50i-h6-sram-c1, allwinner,sun4i-a10-sram-c1 + + The valid sections compatible for F1C100s are: + - allwinner,suniv-f1c100s-sram-d, allwinner,sun4i-a10-sram-d +-- +2.20.1 + + +From 6a505c910b90581b2a980e52f9b6fcb03d234cb7 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 28 Jan 2019 19:53:30 +0100 +Subject: [PATCH 5/6] arm64: dts: allwinner: h6: Add support for the SRAM C1 + section + +Add a node for H6 SRAM C1 section. + +Manual calls it VE SRAM, but for consistency with older SoCs, SRAM C1 +name is used. + +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index d93a7add67e7..247dc0a5ce89 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -167,6 +167,20 @@ + reg = <0x0000 0x1e000>; + }; + }; ++ ++ sram_c1: sram@1a00000 { ++ compatible = "mmio-sram"; ++ reg = <0x01a00000 0x200000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x01a00000 0x200000>; ++ ++ ve_sram: sram-section@0 { ++ compatible = "allwinner,sun50i-h6-sram-c1", ++ "allwinner,sun4i-a10-sram-c1"; ++ reg = <0x000000 0x200000>; ++ }; ++ }; + }; + + ccu: clock@3001000 { +-- +2.20.1 + + +From c1b3128ac98c05c0afde4e6e065d6b1f2ae1dfa7 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 28 Jan 2019 19:59:27 +0100 +Subject: [PATCH 6/6] arm64: dts: allwinner: h6: Add Video Engine node + +This adds the Video engine node for H6. It can use whole DRAM range so +there is no need for reserved memory node. + +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index 247dc0a5ce89..de4b7a1f1012 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -146,6 +146,17 @@ + }; + }; + ++ video-codec@1c0e000 { ++ compatible = "allwinner,sun50i-h6-video-engine"; ++ reg = <0x01c0e000 0x2000>; ++ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, ++ <&ccu CLK_MBUS_VE>; ++ clock-names = "ahb", "mod", "ram"; ++ resets = <&ccu RST_BUS_VE>; ++ interrupts = ; ++ allwinner,sram = <&ve_sram 1>; ++ }; ++ + syscon: syscon@3000000 { + compatible = "allwinner,sun50i-h6-system-control", + "allwinner,sun50i-a64-system-control"; +-- +2.20.1 + diff --git a/projects/Allwinner/devices/H6/patches/linux/04-dma.patch b/projects/Allwinner/devices/H6/patches/linux/04-dma.patch new file mode 100644 index 0000000000..a5c67e12bc --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/linux/04-dma.patch @@ -0,0 +1,658 @@ +From f04472a823847403fd9ea34915803c21b8c27175 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 26 Jan 2019 09:47:17 +0100 +Subject: [PATCH 01/12] dt-bindings: arm64: allwinner: h6: Add binding for DMA + controller + +DMA in H6 is similar to other DMA controller, except it is first which +supports more than 32 request sources and has 16 channels. It also needs +additional clock to be enabled. + +Signed-off-by: Jernej Skrabec +--- + Documentation/devicetree/bindings/dma/sun6i-dma.txt | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt b/Documentation/devicetree/bindings/dma/sun6i-dma.txt +index 7fccc20d8331..cae31f4e77ba 100644 +--- a/Documentation/devicetree/bindings/dma/sun6i-dma.txt ++++ b/Documentation/devicetree/bindings/dma/sun6i-dma.txt +@@ -28,12 +28,17 @@ Example: + }; + + ------------------------------------------------------------------------------ +-For A64 DMA controller: ++For A64 and H6 DMA controller: + + Required properties: +-- compatible: "allwinner,sun50i-a64-dma" ++- compatible: Must be one of ++ "allwinner,sun50i-a64-dma" ++ "allwinner,sun50i-h6-dma" + - dma-channels: Number of DMA channels supported by the controller. + Refer to Documentation/devicetree/bindings/dma/dma.txt ++- clocks: In addition to parent AHB clock, it should also contain mbus ++ clock (H6 only) ++- clock-names: Should contain "bus" and "mbus" (H6 only) + - all properties above, i.e. reg, interrupts, clocks, resets and #dma-cells + + Optional properties: +-- +2.20.1 + + +From 638f21d14b0f22c7e9709edb4ac7b52f0e2a744e Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 26 Jan 2019 09:55:38 +0100 +Subject: [PATCH 02/12] dmaengine: sun6i: Add a quirk for additional mbus clock + +H6 DMA controller needs additional mbus clock to be enabled. + +Add a quirk for it and handle it accordingly. + +Signed-off-by: Jernej Skrabec +--- + drivers/dma/sun6i-dma.c | 23 ++++++++++++++++++++++- + 1 file changed, 22 insertions(+), 1 deletion(-) + +diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c +index 0cd13f17fc11..761555080325 100644 +--- a/drivers/dma/sun6i-dma.c ++++ b/drivers/dma/sun6i-dma.c +@@ -129,6 +129,7 @@ struct sun6i_dma_config { + u32 dst_burst_lengths; + u32 src_addr_widths; + u32 dst_addr_widths; ++ bool mbus_clk; + }; + + /* +@@ -182,6 +183,7 @@ struct sun6i_dma_dev { + struct dma_device slave; + void __iomem *base; + struct clk *clk; ++ struct clk *clk_mbus; + int irq; + spinlock_t lock; + struct reset_control *rstc; +@@ -1208,6 +1210,14 @@ static int sun6i_dma_probe(struct platform_device *pdev) + return PTR_ERR(sdc->clk); + } + ++ if (sdc->cfg->mbus_clk) { ++ sdc->clk_mbus = devm_clk_get(&pdev->dev, "mbus"); ++ if (IS_ERR(sdc->clk_mbus)) { ++ dev_err(&pdev->dev, "No mbus clock specified\n"); ++ return PTR_ERR(sdc->clk_mbus); ++ } ++ } ++ + sdc->rstc = devm_reset_control_get(&pdev->dev, NULL); + if (IS_ERR(sdc->rstc)) { + dev_err(&pdev->dev, "No reset controller specified\n"); +@@ -1312,11 +1322,19 @@ static int sun6i_dma_probe(struct platform_device *pdev) + goto err_reset_assert; + } + ++ if (sdc->cfg->mbus_clk) { ++ ret = clk_prepare_enable(sdc->clk_mbus); ++ if (ret) { ++ dev_err(&pdev->dev, "Couldn't enable mbus clock\n"); ++ goto err_clk_disable; ++ } ++ } ++ + ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0, + dev_name(&pdev->dev), sdc); + if (ret) { + dev_err(&pdev->dev, "Cannot request IRQ\n"); +- goto err_clk_disable; ++ goto err_mbus_clk_disable; + } + + ret = dma_async_device_register(&sdc->slave); +@@ -1341,6 +1359,8 @@ static int sun6i_dma_probe(struct platform_device *pdev) + dma_async_device_unregister(&sdc->slave); + err_irq_disable: + sun6i_kill_tasklet(sdc); ++err_mbus_clk_disable: ++ clk_disable_unprepare(sdc->clk_mbus); + err_clk_disable: + clk_disable_unprepare(sdc->clk); + err_reset_assert: +@@ -1359,6 +1379,7 @@ static int sun6i_dma_remove(struct platform_device *pdev) + + sun6i_kill_tasklet(sdc); + ++ clk_disable_unprepare(sdc->clk_mbus); + clk_disable_unprepare(sdc->clk); + reset_control_assert(sdc->rstc); + +-- +2.20.1 + + +From 74a1f9f2f199e9b23ce0b9710efabbaee82f5605 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 26 Jan 2019 12:51:35 +0100 +Subject: [PATCH 03/12] dmaengine: sun6i: Add a quirk for setting DRQ fields + +H6 DMA has more than 32 possible DRQs. That means that current maximum +of 31 DRQs is not enough anymore. + +Add a quirk which will set source and destination DRQ number. + +Signed-off-by: Jernej Skrabec +--- + drivers/dma/sun6i-dma.c | 48 ++++++++++++++++++++++++----------------- + 1 file changed, 28 insertions(+), 20 deletions(-) + +diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c +index 761555080325..9dd23b76d841 100644 +--- a/drivers/dma/sun6i-dma.c ++++ b/drivers/dma/sun6i-dma.c +@@ -68,15 +68,15 @@ + #define DMA_CHAN_LLI_ADDR 0x08 + + #define DMA_CHAN_CUR_CFG 0x0c +-#define DMA_CHAN_MAX_DRQ 0x1f +-#define DMA_CHAN_CFG_SRC_DRQ(x) ((x) & DMA_CHAN_MAX_DRQ) ++#define DMA_CHAN_MAX_DRQ_A31 0x1f ++#define DMA_CHAN_CFG_SRC_DRQ_A31(x) ((x) & DMA_CHAN_MAX_DRQ_A31) + #define DMA_CHAN_CFG_SRC_IO_MODE BIT(5) + #define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5) + #define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7) + #define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6) + #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9) + +-#define DMA_CHAN_CFG_DST_DRQ(x) (DMA_CHAN_CFG_SRC_DRQ(x) << 16) ++#define DMA_CHAN_CFG_DST_DRQ_A31(x) (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16) + #define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16) + #define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16) + #define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16) +@@ -125,6 +125,7 @@ struct sun6i_dma_config { + */ + void (*clock_autogate_enable)(struct sun6i_dma_dev *); + void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst); ++ void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq); + u32 src_burst_lengths; + u32 dst_burst_lengths; + u32 src_addr_widths; +@@ -311,6 +312,12 @@ static void sun6i_set_burst_length_h3(u32 *p_cfg, s8 src_burst, s8 dst_burst) + DMA_CHAN_CFG_DST_BURST_H3(dst_burst); + } + ++static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq) ++{ ++ *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_A31(src_drq) | ++ DMA_CHAN_CFG_DST_DRQ_A31(dst_drq); ++} ++ + static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan) + { + struct sun6i_desc *txd = pchan->desc; +@@ -634,14 +641,13 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( + + burst = convert_burst(8); + width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES); +- v_lli->cfg = DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | +- DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | +- DMA_CHAN_CFG_DST_LINEAR_MODE | ++ v_lli->cfg = DMA_CHAN_CFG_DST_LINEAR_MODE | + DMA_CHAN_CFG_SRC_LINEAR_MODE | + DMA_CHAN_CFG_SRC_WIDTH(width) | + DMA_CHAN_CFG_DST_WIDTH(width); + + sdev->cfg->set_burst_length(&v_lli->cfg, burst, burst); ++ sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, DRQ_SDRAM); + + sun6i_dma_lli_add(NULL, v_lli, p_lli, txd); + +@@ -695,9 +701,8 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( + v_lli->dst = sconfig->dst_addr; + v_lli->cfg = lli_cfg | + DMA_CHAN_CFG_DST_IO_MODE | +- DMA_CHAN_CFG_SRC_LINEAR_MODE | +- DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | +- DMA_CHAN_CFG_DST_DRQ(vchan->port); ++ DMA_CHAN_CFG_SRC_LINEAR_MODE; ++ sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port); + + dev_dbg(chan2dev(chan), + "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", +@@ -710,9 +715,8 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( + v_lli->dst = sg_dma_address(sg); + v_lli->cfg = lli_cfg | + DMA_CHAN_CFG_DST_LINEAR_MODE | +- DMA_CHAN_CFG_SRC_IO_MODE | +- DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | +- DMA_CHAN_CFG_SRC_DRQ(vchan->port); ++ DMA_CHAN_CFG_SRC_IO_MODE; ++ sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM); + + dev_dbg(chan2dev(chan), + "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", +@@ -780,17 +784,15 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic( + v_lli->dst = sconfig->dst_addr; + v_lli->cfg = lli_cfg | + DMA_CHAN_CFG_DST_IO_MODE | +- DMA_CHAN_CFG_SRC_LINEAR_MODE | +- DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | +- DMA_CHAN_CFG_DST_DRQ(vchan->port); ++ DMA_CHAN_CFG_SRC_LINEAR_MODE; ++ sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port); + } else { + v_lli->src = sconfig->src_addr; + v_lli->dst = buf_addr + period_len * i; + v_lli->cfg = lli_cfg | + DMA_CHAN_CFG_DST_LINEAR_MODE | +- DMA_CHAN_CFG_SRC_IO_MODE | +- DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | +- DMA_CHAN_CFG_SRC_DRQ(vchan->port); ++ DMA_CHAN_CFG_SRC_IO_MODE; ++ sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM); + } + + prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd); +@@ -1055,6 +1057,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = { + .nr_max_requests = 30, + .nr_max_vchans = 53, + .set_burst_length = sun6i_set_burst_length_a31, ++ .set_drq = sun6i_set_drq_a31, + .src_burst_lengths = BIT(1) | BIT(8), + .dst_burst_lengths = BIT(1) | BIT(8), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | +@@ -1076,6 +1079,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = { + .nr_max_vchans = 37, + .clock_autogate_enable = sun6i_enable_clock_autogate_a23, + .set_burst_length = sun6i_set_burst_length_a31, ++ .set_drq = sun6i_set_drq_a31, + .src_burst_lengths = BIT(1) | BIT(8), + .dst_burst_lengths = BIT(1) | BIT(8), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | +@@ -1092,6 +1096,7 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg = { + .nr_max_vchans = 39, + .clock_autogate_enable = sun6i_enable_clock_autogate_a23, + .set_burst_length = sun6i_set_burst_length_a31, ++ .set_drq = sun6i_set_drq_a31, + .src_burst_lengths = BIT(1) | BIT(8), + .dst_burst_lengths = BIT(1) | BIT(8), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | +@@ -1115,6 +1120,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { + .nr_max_vchans = 34, + .clock_autogate_enable = sun6i_enable_clock_autogate_h3, + .set_burst_length = sun6i_set_burst_length_h3, ++ .set_drq = sun6i_set_drq_a31, + .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | +@@ -1134,6 +1140,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { + static struct sun6i_dma_config sun50i_a64_dma_cfg = { + .clock_autogate_enable = sun6i_enable_clock_autogate_h3, + .set_burst_length = sun6i_set_burst_length_h3, ++ .set_drq = sun6i_set_drq_a31, + .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | +@@ -1157,6 +1164,7 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = { + .nr_max_vchans = 24, + .clock_autogate_enable = sun6i_enable_clock_autogate_a23, + .set_burst_length = sun6i_set_burst_length_a31, ++ .set_drq = sun6i_set_drq_a31, + .src_burst_lengths = BIT(1) | BIT(8), + .dst_burst_lengths = BIT(1) | BIT(8), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | +@@ -1272,8 +1280,8 @@ static int sun6i_dma_probe(struct platform_device *pdev) + ret = of_property_read_u32(np, "dma-requests", &sdc->max_request); + if (ret && !sdc->max_request) { + dev_info(&pdev->dev, "Missing dma-requests, using %u.\n", +- DMA_CHAN_MAX_DRQ); +- sdc->max_request = DMA_CHAN_MAX_DRQ; ++ DMA_CHAN_MAX_DRQ_A31); ++ sdc->max_request = DMA_CHAN_MAX_DRQ_A31; + } + + /* +-- +2.20.1 + + +From 20465d9f33a6686cc283f5874428d80fbce29f46 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 26 Jan 2019 13:35:02 +0100 +Subject: [PATCH 04/12] dmaengine: sun6i: Add a quirk for setting mode fields + +H6 DMA has mode fields in different position than any other currently +supported DMA controller. + +Add a quirk for that. + +Signed-off-by: Jernej Skrabec +--- + drivers/dma/sun6i-dma.c | 46 ++++++++++++++++++++++++----------------- + 1 file changed, 27 insertions(+), 19 deletions(-) + +diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c +index 9dd23b76d841..6a37f8bb39b1 100644 +--- a/drivers/dma/sun6i-dma.c ++++ b/drivers/dma/sun6i-dma.c +@@ -70,15 +70,13 @@ + #define DMA_CHAN_CUR_CFG 0x0c + #define DMA_CHAN_MAX_DRQ_A31 0x1f + #define DMA_CHAN_CFG_SRC_DRQ_A31(x) ((x) & DMA_CHAN_MAX_DRQ_A31) +-#define DMA_CHAN_CFG_SRC_IO_MODE BIT(5) +-#define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5) ++#define DMA_CHAN_CFG_SRC_MODE_A31(x) (((x) & 0x1) << 5) + #define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7) + #define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6) + #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9) + + #define DMA_CHAN_CFG_DST_DRQ_A31(x) (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16) +-#define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16) +-#define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16) ++#define DMA_CHAN_CFG_DST_MODE_A31(x) (DMA_CHAN_CFG_SRC_MODE_A31(x) << 16) + #define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16) + #define DMA_CHAN_CFG_DST_BURST_H3(x) (DMA_CHAN_CFG_SRC_BURST_H3(x) << 16) + #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16) +@@ -98,6 +96,8 @@ + #define LLI_LAST_ITEM 0xfffff800 + #define NORMAL_WAIT 8 + #define DRQ_SDRAM 1 ++#define LINEAR_MODE 0 ++#define IO_MODE 1 + + /* forward declaration */ + struct sun6i_dma_dev; +@@ -126,6 +126,7 @@ struct sun6i_dma_config { + void (*clock_autogate_enable)(struct sun6i_dma_dev *); + void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst); + void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq); ++ void (*set_mode)(u32 *p_cfg, s8 src_mode, s8 dst_mode); + u32 src_burst_lengths; + u32 dst_burst_lengths; + u32 src_addr_widths; +@@ -318,6 +319,12 @@ static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq) + DMA_CHAN_CFG_DST_DRQ_A31(dst_drq); + } + ++static void sun6i_set_mode_a31(u32 *p_cfg, s8 src_mode, s8 dst_mode) ++{ ++ *p_cfg |= DMA_CHAN_CFG_SRC_MODE_A31(src_mode) | ++ DMA_CHAN_CFG_DST_MODE_A31(dst_mode); ++} ++ + static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan) + { + struct sun6i_desc *txd = pchan->desc; +@@ -641,13 +648,12 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( + + burst = convert_burst(8); + width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES); +- v_lli->cfg = DMA_CHAN_CFG_DST_LINEAR_MODE | +- DMA_CHAN_CFG_SRC_LINEAR_MODE | +- DMA_CHAN_CFG_SRC_WIDTH(width) | ++ v_lli->cfg = DMA_CHAN_CFG_SRC_WIDTH(width) | + DMA_CHAN_CFG_DST_WIDTH(width); + + sdev->cfg->set_burst_length(&v_lli->cfg, burst, burst); + sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, DRQ_SDRAM); ++ sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, LINEAR_MODE); + + sun6i_dma_lli_add(NULL, v_lli, p_lli, txd); + +@@ -699,10 +705,9 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( + if (dir == DMA_MEM_TO_DEV) { + v_lli->src = sg_dma_address(sg); + v_lli->dst = sconfig->dst_addr; +- v_lli->cfg = lli_cfg | +- DMA_CHAN_CFG_DST_IO_MODE | +- DMA_CHAN_CFG_SRC_LINEAR_MODE; ++ v_lli->cfg = lli_cfg; + sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port); ++ sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE); + + dev_dbg(chan2dev(chan), + "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", +@@ -713,10 +718,9 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( + } else { + v_lli->src = sconfig->src_addr; + v_lli->dst = sg_dma_address(sg); +- v_lli->cfg = lli_cfg | +- DMA_CHAN_CFG_DST_LINEAR_MODE | +- DMA_CHAN_CFG_SRC_IO_MODE; ++ v_lli->cfg = lli_cfg; + sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM); ++ sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE); + + dev_dbg(chan2dev(chan), + "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", +@@ -782,17 +786,15 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic( + if (dir == DMA_MEM_TO_DEV) { + v_lli->src = buf_addr + period_len * i; + v_lli->dst = sconfig->dst_addr; +- v_lli->cfg = lli_cfg | +- DMA_CHAN_CFG_DST_IO_MODE | +- DMA_CHAN_CFG_SRC_LINEAR_MODE; ++ v_lli->cfg = lli_cfg; + sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port); ++ sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE); + } else { + v_lli->src = sconfig->src_addr; + v_lli->dst = buf_addr + period_len * i; +- v_lli->cfg = lli_cfg | +- DMA_CHAN_CFG_DST_LINEAR_MODE | +- DMA_CHAN_CFG_SRC_IO_MODE; ++ v_lli->cfg = lli_cfg; + sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM); ++ sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE); + } + + prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd); +@@ -1058,6 +1060,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = { + .nr_max_vchans = 53, + .set_burst_length = sun6i_set_burst_length_a31, + .set_drq = sun6i_set_drq_a31, ++ .set_mode = sun6i_set_mode_a31, + .src_burst_lengths = BIT(1) | BIT(8), + .dst_burst_lengths = BIT(1) | BIT(8), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | +@@ -1080,6 +1083,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = { + .clock_autogate_enable = sun6i_enable_clock_autogate_a23, + .set_burst_length = sun6i_set_burst_length_a31, + .set_drq = sun6i_set_drq_a31, ++ .set_mode = sun6i_set_mode_a31, + .src_burst_lengths = BIT(1) | BIT(8), + .dst_burst_lengths = BIT(1) | BIT(8), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | +@@ -1097,6 +1101,7 @@ static struct sun6i_dma_config sun8i_a83t_dma_cfg = { + .clock_autogate_enable = sun6i_enable_clock_autogate_a23, + .set_burst_length = sun6i_set_burst_length_a31, + .set_drq = sun6i_set_drq_a31, ++ .set_mode = sun6i_set_mode_a31, + .src_burst_lengths = BIT(1) | BIT(8), + .dst_burst_lengths = BIT(1) | BIT(8), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | +@@ -1121,6 +1126,7 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { + .clock_autogate_enable = sun6i_enable_clock_autogate_h3, + .set_burst_length = sun6i_set_burst_length_h3, + .set_drq = sun6i_set_drq_a31, ++ .set_mode = sun6i_set_mode_a31, + .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | +@@ -1141,6 +1147,7 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = { + .clock_autogate_enable = sun6i_enable_clock_autogate_h3, + .set_burst_length = sun6i_set_burst_length_h3, + .set_drq = sun6i_set_drq_a31, ++ .set_mode = sun6i_set_mode_a31, + .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | +@@ -1165,6 +1172,7 @@ static struct sun6i_dma_config sun8i_v3s_dma_cfg = { + .clock_autogate_enable = sun6i_enable_clock_autogate_a23, + .set_burst_length = sun6i_set_burst_length_a31, + .set_drq = sun6i_set_drq_a31, ++ .set_mode = sun6i_set_mode_a31, + .src_burst_lengths = BIT(1) | BIT(8), + .dst_burst_lengths = BIT(1) | BIT(8), + .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | +-- +2.20.1 + + +From 7d4d497a1c5395d452930fdf0177f82520c09066 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 26 Jan 2019 13:50:24 +0100 +Subject: [PATCH 05/12] dmaengine: sun6i: Add support for H6 DMA + +H6 DMA has more than 32 supported DRQs, which means that configuration +register is slightly rearranged. It also needs additional clock to be +enabled. + +Add support for it. + +Signed-off-by: Jernej Skrabec +--- + drivers/dma/sun6i-dma.c | 44 +++++++++++++++++++++++++++++++++++++++-- + 1 file changed, 42 insertions(+), 2 deletions(-) + +diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c +index 6a37f8bb39b1..eceedd139651 100644 +--- a/drivers/dma/sun6i-dma.c ++++ b/drivers/dma/sun6i-dma.c +@@ -69,14 +69,19 @@ + + #define DMA_CHAN_CUR_CFG 0x0c + #define DMA_CHAN_MAX_DRQ_A31 0x1f ++#define DMA_CHAN_MAX_DRQ_H6 0x3f + #define DMA_CHAN_CFG_SRC_DRQ_A31(x) ((x) & DMA_CHAN_MAX_DRQ_A31) ++#define DMA_CHAN_CFG_SRC_DRQ_H6(x) ((x) & DMA_CHAN_MAX_DRQ_H6) + #define DMA_CHAN_CFG_SRC_MODE_A31(x) (((x) & 0x1) << 5) ++#define DMA_CHAN_CFG_SRC_MODE_H6(x) (((x) & 0x1) << 8) + #define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7) + #define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6) + #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9) + + #define DMA_CHAN_CFG_DST_DRQ_A31(x) (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16) ++#define DMA_CHAN_CFG_DST_DRQ_H6(x) (DMA_CHAN_CFG_SRC_DRQ_H6(x) << 16) + #define DMA_CHAN_CFG_DST_MODE_A31(x) (DMA_CHAN_CFG_SRC_MODE_A31(x) << 16) ++#define DMA_CHAN_CFG_DST_MODE_H6(x) (DMA_CHAN_CFG_SRC_MODE_H6(x) << 16) + #define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16) + #define DMA_CHAN_CFG_DST_BURST_H3(x) (DMA_CHAN_CFG_SRC_BURST_H3(x) << 16) + #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16) +@@ -319,12 +324,24 @@ static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq) + DMA_CHAN_CFG_DST_DRQ_A31(dst_drq); + } + ++static void sun6i_set_drq_h6(u32 *p_cfg, s8 src_drq, s8 dst_drq) ++{ ++ *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_H6(src_drq) | ++ DMA_CHAN_CFG_DST_DRQ_H6(dst_drq); ++} ++ + static void sun6i_set_mode_a31(u32 *p_cfg, s8 src_mode, s8 dst_mode) + { + *p_cfg |= DMA_CHAN_CFG_SRC_MODE_A31(src_mode) | + DMA_CHAN_CFG_DST_MODE_A31(dst_mode); + } + ++static void sun6i_set_mode_h6(u32 *p_cfg, s8 src_mode, s8 dst_mode) ++{ ++ *p_cfg |= DMA_CHAN_CFG_SRC_MODE_H6(src_mode) | ++ DMA_CHAN_CFG_DST_MODE_H6(dst_mode); ++} ++ + static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan) + { + struct sun6i_desc *txd = pchan->desc; +@@ -1160,6 +1177,28 @@ static struct sun6i_dma_config sun50i_a64_dma_cfg = { + BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), + }; + ++/* ++ * The H6 binding uses the number of dma channels from the ++ * device tree node. ++ */ ++static struct sun6i_dma_config sun50i_h6_dma_cfg = { ++ .clock_autogate_enable = sun6i_enable_clock_autogate_h3, ++ .set_burst_length = sun6i_set_burst_length_h3, ++ .set_drq = sun6i_set_drq_h6, ++ .set_mode = sun6i_set_mode_h6, ++ .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), ++ .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), ++ .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | ++ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | ++ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | ++ BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), ++ .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | ++ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | ++ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | ++ BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), ++ .mbus_clk = true, ++}; ++ + /* + * The V3s have only 8 physical channels, a maximum DRQ port id of 23, + * and a total of 24 usable source and destination endpoints. +@@ -1190,6 +1229,7 @@ static const struct of_device_id sun6i_dma_match[] = { + { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg }, + { .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg }, + { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg }, ++ { .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, sun6i_dma_match); +@@ -1288,8 +1328,8 @@ static int sun6i_dma_probe(struct platform_device *pdev) + ret = of_property_read_u32(np, "dma-requests", &sdc->max_request); + if (ret && !sdc->max_request) { + dev_info(&pdev->dev, "Missing dma-requests, using %u.\n", +- DMA_CHAN_MAX_DRQ_A31); +- sdc->max_request = DMA_CHAN_MAX_DRQ_A31; ++ DMA_CHAN_MAX_DRQ_H6); ++ sdc->max_request = DMA_CHAN_MAX_DRQ_H6; + } + + /* +-- +2.20.1 + + +From b9d20d1b5577e4d73b47b9303798484f6699cfd4 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 26 Jan 2019 14:20:21 +0100 +Subject: [PATCH 06/12] arm64: dts: allwinner: h6: Add DMA node + +H6 has DMA controller which supports 16 channels. + +Add a node for it. + +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index d93a7add67e7..62a0eae77639 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -178,6 +178,18 @@ + #reset-cells = <1>; + }; + ++ dma: dma-controller@3002000 { ++ compatible = "allwinner,sun50i-h6-dma"; ++ reg = <0x03002000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; ++ clock-names = "bus", "mbus"; ++ dma-channels = <16>; ++ dma-requests = <46>; ++ resets = <&ccu RST_BUS_DMA>; ++ #dma-cells = <1>; ++ }; ++ + gic: interrupt-controller@3021000 { + compatible = "arm,gic-400"; + reg = <0x03021000 0x1000>, +-- +2.20.1 diff --git a/projects/Allwinner/devices/H6/patches/linux/05-sound-hack.patch b/projects/Allwinner/devices/H6/patches/linux/05-sound-hack.patch new file mode 100644 index 0000000000..242bf577a5 --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/linux/05-sound-hack.patch @@ -0,0 +1,142 @@ +From 026ec1598d98a0bd45785a44a74ddb7063d2f776 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Tue, 22 Jan 2019 20:16:58 +0100 +Subject: [PATCH] AW H6 I2S WIP + +Signed-off-by: Jernej Skrabec +--- + arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 31 ++++++++++++++++++++ + drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 8 ++--- + sound/soc/sunxi/sun4i-i2s.c | 12 ++++---- + 3 files changed, 41 insertions(+), 10 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +index 62a0eae77639..f1c53aec6523 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +@@ -95,6 +95,23 @@ + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + ++ sound_hdmi: sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "allwinner-hdmi"; ++ simple-audio-card,mclk-fs = <256>; ++ ++ simple-audio-card,codec { ++ sound-dai = <&hdmi>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1>; ++ dai-tdm-slot-num = <2>; ++ dai-tdm-slot-width = <32>; ++ }; ++ }; ++ + soc { + compatible = "simple-bus"; + #address-cells = <1>; +@@ -357,6 +374,19 @@ + }; + }; + ++ i2s1: i2s@5091000 { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sun8i-h3-i2s"; ++ reg = <0x05091000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; ++ clock-names = "apb", "mod"; ++ dmas = <&dma 4>; ++ resets = <&ccu RST_BUS_I2S1>; ++ dma-names = "tx"; ++ allwinner,playback-channels = <8>; ++ }; ++ + usb2otg: usb@5100000 { + compatible = "allwinner,sun50i-h6-musb", + "allwinner,sun8i-a33-musb"; +@@ -440,6 +470,7 @@ + }; + + hdmi: hdmi@6000000 { ++ #sound-dai-cells = <0>; + compatible = "allwinner,sun50i-h6-dw-hdmi"; + reg = <0x06000000 0x10000>; + reg-io-width = <1>; +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +index 139e8389615c..bdb33266a3de 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +@@ -504,7 +504,7 @@ static struct ccu_div i2s3_clk = { + .hw.init = CLK_HW_INIT_PARENTS("i2s3", + audio_parents, + &ccu_div_ops, +- 0), ++ CLK_SET_RATE_PARENT), + }, + }; + +@@ -517,7 +517,7 @@ static struct ccu_div i2s0_clk = { + .hw.init = CLK_HW_INIT_PARENTS("i2s0", + audio_parents, + &ccu_div_ops, +- 0), ++ CLK_SET_RATE_PARENT), + }, + }; + +@@ -530,7 +530,7 @@ static struct ccu_div i2s1_clk = { + .hw.init = CLK_HW_INIT_PARENTS("i2s1", + audio_parents, + &ccu_div_ops, +- 0), ++ CLK_SET_RATE_PARENT), + }, + }; + +@@ -543,7 +543,7 @@ static struct ccu_div i2s2_clk = { + .hw.init = CLK_HW_INIT_PARENTS("i2s2", + audio_parents, + &ccu_div_ops, +- 0), ++ CLK_SET_RATE_PARENT), + }, + }; + +diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c +index d5ec1a20499d..f286b8bfcfb3 100644 +--- a/sound/soc/sunxi/sun4i-i2s.c ++++ b/sound/soc/sunxi/sun4i-i2s.c +@@ -108,12 +108,12 @@ + #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(2, 0) + #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1) + +-#define SUN8I_I2S_TX_CHAN_MAP_REG 0x44 ++#define SUN8I_I2S_TX_CHAN_MAP_REG 0x48 + #define SUN8I_I2S_TX_CHAN_SEL_REG 0x34 +-#define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 12) +-#define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12) +-#define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4) +-#define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4) ++#define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(21, 20) ++#define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 20) ++#define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(15, 0) ++#define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 0) + + #define SUN8I_I2S_RX_CHAN_SEL_REG 0x54 + #define SUN8I_I2S_RX_CHAN_MAP_REG 0x58 +@@ -946,7 +946,7 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { + .field_fmt_mode = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5), + .field_txchanmap = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31), + .field_rxchanmap = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31), +- .field_txchansel = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2), ++ .field_txchansel = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 16, 19), + .field_rxchansel = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2), + }; + +-- +2.21.0 + diff --git a/projects/Allwinner/devices/H6/patches/linux/06-cedrus-increase-frequency.patch b/projects/Allwinner/devices/H6/patches/linux/06-cedrus-increase-frequency.patch new file mode 100644 index 0000000000..7abb69bb99 --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/linux/06-cedrus-increase-frequency.patch @@ -0,0 +1,25 @@ +From 18c9a269e2b744ee84f32de9d5c6c66857725ef8 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 15 Dec 2018 12:56:53 +0100 +Subject: [PATCH 20/20] cedrus increase frequency + +--- + drivers/staging/media/sunxi/cedrus/cedrus_hw.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h +index b43c77d54b95..70677571f3d3 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h +@@ -16,7 +16,7 @@ + #ifndef _CEDRUS_HW_H_ + #define _CEDRUS_HW_H_ + +-#define CEDRUS_CLOCK_RATE_DEFAULT 402000000 ++#define CEDRUS_CLOCK_RATE_DEFAULT 600000000 + + int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec); + void cedrus_engine_disable(struct cedrus_dev *dev); +-- +2.20.0 + diff --git a/projects/Allwinner/devices/H6/patches/linux/07-limit-max-pixel-clock.patch b/projects/Allwinner/devices/H6/patches/linux/07-limit-max-pixel-clock.patch new file mode 100644 index 0000000000..29bd0ce45f --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/linux/07-limit-max-pixel-clock.patch @@ -0,0 +1,20 @@ +diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c +index caea5a9f8f1d..ba4ce576b471 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c ++++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c +@@ -48,8 +48,13 @@ static enum drm_mode_status + sun8i_dw_hdmi_mode_valid_h6(struct drm_connector *connector, + const struct drm_display_mode *mode) + { +- /* This is max for HDMI 2.0b (4K@60Hz) */ +- if (mode->clock > 594000) ++ /* ++ * Controller support maximum of 594 MHz, which correlates to ++ * 4K@60Hz 4:4:4 or RGB. However, for frequencies greater than ++ * 340 MHz scrambling has to be enabled. Because scrambling is ++ * not yet implemented, just limit to 340 MHz for now. ++ */ ++ if (mode->clock > 340000) + return MODE_CLOCK_HIGH; + + return MODE_OK; diff --git a/projects/Allwinner/devices/H6/patches/linux/08-clock-fixes.patch b/projects/Allwinner/devices/H6/patches/linux/08-clock-fixes.patch new file mode 100644 index 0000000000..68c1d5a8c8 --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/linux/08-clock-fixes.patch @@ -0,0 +1,96 @@ +From 9413130f5b213551519c97482462a6daea9a5343 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Tue, 2 Apr 2019 19:32:01 +0200 +Subject: [PATCH 1/2] clk: sunxi-ng: h6: Change CEC clock parent + +Signed-off-by: Jernej Skrabec +--- + drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +index daf78966555e..33980067b06e 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +@@ -656,6 +656,8 @@ static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" }; + static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = { + { .index = 1, .div = 36621 }, + }; ++ ++#define SUN50I_H6_HDMI_CEC_CLK_REG 0xb10 + static struct ccu_mux hdmi_cec_clk = { + .enable = BIT(31), + +@@ -1200,6 +1202,15 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev) + val &= ~(GENMASK(21, 16) | BIT(0)); + writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG); + ++ /* ++ * First clock parent (osc32K) is unusable for CEC. But since there ++ * is no good way to force parent switch (both run with same frequency), ++ * just set second clock parent here. ++ */ ++ val = readl(reg + SUN50I_H6_HDMI_CEC_CLK_REG); ++ val |= BIT(24); ++ writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG); ++ + return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_h6_ccu_desc); + } + +-- +2.21.0 + + +From eab64a1ccf6b7cda339fdfdbfa9e1973e4cc0c85 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Tue, 2 Apr 2019 21:15:45 +0200 +Subject: [PATCH 2/2] clk: sunxi-ng: h6: Allow video & vpu clocks to change + parent rate + +Video related clocks need to set rate as close as possible to the +requested one, so they should be able to change parent clock rate. + +VPU clock sometimes has to be set to higher than default parent clock +rate. This is requ + +Add CLK_SET_RATE_PARENT flag to tcon-lcd0, tcon-tv0 and ve. + +Signed-off-by: Jernej Skrabec +--- + drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +index 33980067b06e..3c32d7798f27 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +@@ -311,7 +311,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690, + 0, 3, /* M */ + 24, 1, /* mux */ + BIT(31), /* gate */ +- 0); ++ CLK_SET_RATE_PARENT); + + static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2", + 0x69c, BIT(0), 0); +@@ -691,7 +691,7 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", + tcon_lcd0_parents, 0xb60, + 24, 3, /* mux */ + BIT(31), /* gate */ +- 0); ++ CLK_SET_RATE_PARENT); + + static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3", + 0xb7c, BIT(0), 0); +@@ -706,7 +706,7 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", + 8, 2, /* P */ + 24, 3, /* mux */ + BIT(31), /* gate */ +- 0); ++ CLK_SET_RATE_PARENT); + + static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3", + 0xb9c, BIT(0), 0); +-- +2.21.0 + diff --git a/projects/Allwinner/devices/H6/patches/u-boot/001-update-dt.patch b/projects/Allwinner/devices/H6/patches/u-boot/001-update-dt.patch new file mode 100644 index 0000000000..47ca8b24ea --- /dev/null +++ b/projects/Allwinner/devices/H6/patches/u-boot/001-update-dt.patch @@ -0,0 +1,608 @@ +diff --git a/arch/arm/dts/sun50i-h6-pine-h64.dts b/arch/arm/dts/sun50i-h6-pine-h64.dts +index ceffc40810..bdb8470fc8 100644 +--- a/arch/arm/dts/sun50i-h6-pine-h64.dts ++++ b/arch/arm/dts/sun50i-h6-pine-h64.dts +@@ -14,6 +14,7 @@ + compatible = "pine64,pine-h64", "allwinner,sun50i-h6"; + + aliases { ++ ethernet0 = &emac; + serial0 = &uart0; + }; + +@@ -21,6 +22,17 @@ + stdout-path = "serial0:115200n8"; + }; + ++ connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -39,6 +51,56 @@ + gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */ + }; + }; ++ ++ reg_usb_vbus: vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb-vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ startup-delay-us = <100000>; ++ gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++}; ++ ++&emac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ext_rgmii_pins>; ++ phy-mode = "rgmii"; ++ phy-handle = <&ext_rgmii_phy>; ++ phy-supply = <®_aldo2>; ++ allwinner,rx-delay-ps = <200>; ++ allwinner,tx-delay-ps = <200>; ++ status = "okay"; ++}; ++ ++&mdio { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; + }; + + &mmc0 { +@@ -46,6 +108,7 @@ + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_cldo1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; ++ bus-width = <4>; + status = "okay"; + }; + +@@ -56,6 +119,15 @@ + vqmmc-supply = <®_bldo2>; + non-removable; + cap-mmc-hw-reset; ++ bus-width = <8>; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci3 { + status = "okay"; + }; + +@@ -83,6 +155,7 @@ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ac200"; ++ regulator-enable-ramp-delay = <100000>; + }; + + reg_aldo3: aldo3 { +@@ -183,3 +256,14 @@ + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; + }; ++ ++&usb2otg { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&usb2phy { ++ usb0_vbus-supply = <®_usb_vbus>; ++ usb3_vbus-supply = <®_usb_vbus>; ++ status = "okay"; ++}; +diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi +index cfa5fffcf6..c9e861a50a 100644 +--- a/arch/arm/dts/sun50i-h6.dtsi ++++ b/arch/arm/dts/sun50i-h6.dtsi +@@ -6,8 +6,11 @@ + #include + #include + #include ++#include ++#include + #include + #include ++#include + + / { + interrupt-parent = <&gic>; +@@ -19,34 +22,40 @@ + #size-cells = <0>; + + cpu0: cpu@0 { +- compatible = "arm,cortex-a53", "arm,armv8"; ++ compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { +- compatible = "arm,cortex-a53", "arm,armv8"; ++ compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { +- compatible = "arm,cortex-a53", "arm,armv8"; ++ compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { +- compatible = "arm,cortex-a53", "arm,armv8"; ++ compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; + }; + }; + ++ de: display-engine { ++ compatible = "allwinner,sun50i-h6-display-engine"; ++ allwinner,pipelines = <&mixer0>; ++ status = "disabled"; ++ }; ++ + iosc: internal-osc-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; +@@ -92,6 +101,88 @@ + #size-cells = <1>; + ranges; + ++ display-engine@1000000 { ++ compatible = "allwinner,sun50i-h6-de3", ++ "allwinner,sun50i-a64-de2"; ++ reg = <0x1000000 0x400000>; ++ allwinner,sram = <&de2_sram 1>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x1000000 0x400000>; ++ ++ display_clocks: clock@0 { ++ compatible = "allwinner,sun50i-h6-de3-clk"; ++ reg = <0x0 0x10000>; ++ clocks = <&ccu CLK_DE>, ++ <&ccu CLK_BUS_DE>; ++ clock-names = "mod", ++ "bus"; ++ resets = <&ccu RST_BUS_DE>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ mixer0: mixer@100000 { ++ compatible = "allwinner,sun50i-h6-de3-mixer-0"; ++ reg = <0x100000 0x100000>; ++ clocks = <&display_clocks CLK_BUS_MIXER0>, ++ <&display_clocks CLK_MIXER0>; ++ clock-names = "bus", ++ "mod"; ++ resets = <&display_clocks RST_MIXER0>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ mixer0_out: port@1 { ++ reg = <1>; ++ ++ mixer0_out_tcon_top_mixer0: endpoint { ++ remote-endpoint = <&tcon_top_mixer0_in_mixer0>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ syscon: syscon@3000000 { ++ compatible = "allwinner,sun50i-h6-system-control", ++ "allwinner,sun50i-a64-system-control"; ++ reg = <0x03000000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ sram_c: sram@28000 { ++ compatible = "mmio-sram"; ++ reg = <0x00028000 0x1e000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x00028000 0x1e000>; ++ ++ de2_sram: sram-section@0 { ++ compatible = "allwinner,sun50i-h6-sram-c", ++ "allwinner,sun50i-a64-sram-c"; ++ reg = <0x0000 0x1e000>; ++ }; ++ }; ++ ++ sram_c1: sram@1a00000 { ++ compatible = "mmio-sram"; ++ reg = <0x01a00000 0x200000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x01a00000 0x200000>; ++ ++ ve_sram: sram-section@0 { ++ compatible = "allwinner,sun50i-h6-sram-c1", ++ "allwinner,sun4i-a10-sram-c1"; ++ reg = <0x000000 0x200000>; ++ }; ++ }; ++ }; ++ + ccu: clock@3001000 { + compatible = "allwinner,sun50i-h6-ccu"; + reg = <0x03001000 0x1000>; +@@ -101,17 +192,6 @@ + #reset-cells = <1>; + }; + +- gic: interrupt-controller@3021000 { +- compatible = "arm,gic-400"; +- reg = <0x03021000 0x1000>, +- <0x03022000 0x2000>, +- <0x03024000 0x2000>, +- <0x03026000 0x2000>; +- interrupts = ; +- interrupt-controller; +- #interrupt-cells = <3>; +- }; +- + pio: pinctrl@300b000 { + compatible = "allwinner,sun50i-h6-pinctrl"; + reg = <0x0300b000 0x400>; +@@ -126,6 +206,19 @@ + interrupt-controller; + #interrupt-cells = <3>; + ++ ext_rgmii_pins: rgmii_pins { ++ pins = "PD0", "PD1", "PD2", "PD3", "PD4", ++ "PD5", "PD7", "PD8", "PD9", "PD10", ++ "PD11", "PD12", "PD13", "PD19", "PD20"; ++ function = "emac"; ++ drive-strength = <40>; ++ }; ++ ++ hdmi_pins: hdmi-pins { ++ pins = "PH8", "PH9", "PH10"; ++ function = "hdmi"; ++ }; ++ + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; +@@ -149,6 +242,17 @@ + }; + }; + ++ gic: interrupt-controller@3021000 { ++ compatible = "arm,gic-400"; ++ reg = <0x03021000 0x1000>, ++ <0x03022000 0x2000>, ++ <0x03024000 0x2000>, ++ <0x03026000 0x2000>; ++ interrupts = ; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ }; ++ + mmc0: mmc@4020000 { + compatible = "allwinner,sun50i-h6-mmc", + "allwinner,sun50i-a64-mmc"; +@@ -235,6 +339,250 @@ + status = "disabled"; + }; + ++ emac: ethernet@5020000 { ++ compatible = "allwinner,sun50i-h6-emac", ++ "allwinner,sun50i-a64-emac"; ++ syscon = <&syscon>; ++ reg = <0x05020000 0x10000>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ resets = <&ccu RST_BUS_EMAC>; ++ reset-names = "stmmaceth"; ++ clocks = <&ccu CLK_BUS_EMAC>; ++ clock-names = "stmmaceth"; ++ status = "disabled"; ++ ++ mdio: mdio { ++ compatible = "snps,dwmac-mdio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ ++ usb2otg: usb@5100000 { ++ compatible = "allwinner,sun50i-h6-musb", ++ "allwinner,sun8i-a33-musb"; ++ reg = <0x05100000 0x0400>; ++ clocks = <&ccu CLK_BUS_OTG>; ++ resets = <&ccu RST_BUS_OTG>; ++ interrupts = ; ++ interrupt-names = "mc"; ++ phys = <&usb2phy 0>; ++ phy-names = "usb"; ++ extcon = <&usb2phy 0>; ++ status = "disabled"; ++ }; ++ ++ usb2phy: phy@5100400 { ++ compatible = "allwinner,sun50i-h6-usb-phy"; ++ reg = <0x05100400 0x24>, ++ <0x05101800 0x4>, ++ <0x05311800 0x4>; ++ reg-names = "phy_ctrl", ++ "pmu0", ++ "pmu3"; ++ clocks = <&ccu CLK_USB_PHY0>, ++ <&ccu CLK_USB_PHY3>; ++ clock-names = "usb0_phy", ++ "usb3_phy"; ++ resets = <&ccu RST_USB_PHY0>, ++ <&ccu RST_USB_PHY3>; ++ reset-names = "usb0_reset", ++ "usb3_reset"; ++ status = "disabled"; ++ #phy-cells = <1>; ++ }; ++ ++ ehci0: usb@5101000 { ++ compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; ++ reg = <0x05101000 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI0>, ++ <&ccu CLK_BUS_EHCI0>, ++ <&ccu CLK_USB_OHCI0>; ++ resets = <&ccu RST_BUS_OHCI0>, ++ <&ccu RST_BUS_EHCI0>; ++ status = "disabled"; ++ }; ++ ++ ohci0: usb@5101400 { ++ compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; ++ reg = <0x05101400 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI0>, ++ <&ccu CLK_USB_OHCI0>; ++ resets = <&ccu RST_BUS_OHCI0>; ++ status = "disabled"; ++ }; ++ ++ ehci3: usb@5311000 { ++ compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; ++ reg = <0x05311000 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI3>, ++ <&ccu CLK_BUS_EHCI3>, ++ <&ccu CLK_USB_OHCI3>; ++ resets = <&ccu RST_BUS_OHCI3>, ++ <&ccu RST_BUS_EHCI3>; ++ phys = <&usb2phy 3>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ohci3: usb@5311400 { ++ compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; ++ reg = <0x05311400 0x100>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_OHCI3>, ++ <&ccu CLK_USB_OHCI3>; ++ resets = <&ccu RST_BUS_OHCI3>; ++ phys = <&usb2phy 3>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ hdmi: hdmi@6000000 { ++ compatible = "allwinner,sun50i-h6-dw-hdmi"; ++ reg = <0x06000000 0x10000>; ++ reg-io-width = <1>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, ++ <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, ++ <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; ++ clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", ++ "hdcp-bus"; ++ resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; ++ reset-names = "ctrl", "hdcp"; ++ phys = <&hdmi_phy>; ++ phy-names = "hdmi-phy"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmi_pins>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hdmi_in: port@0 { ++ reg = <0>; ++ ++ hdmi_in_tcon_top: endpoint { ++ remote-endpoint = <&tcon_top_hdmi_out_hdmi>; ++ }; ++ }; ++ ++ hdmi_out: port@1 { ++ reg = <1>; ++ }; ++ }; ++ }; ++ ++ hdmi_phy: hdmi-phy@6010000 { ++ compatible = "allwinner,sun50i-h6-hdmi-phy"; ++ reg = <0x06010000 0x10000>; ++ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; ++ clock-names = "bus", "mod"; ++ resets = <&ccu RST_BUS_HDMI>; ++ reset-names = "phy"; ++ #phy-cells = <0>; ++ }; ++ ++ tcon_top: tcon-top@6510000 { ++ compatible = "allwinner,sun50i-h6-tcon-top"; ++ reg = <0x06510000 0x1000>; ++ clocks = <&ccu CLK_BUS_TCON_TOP>, ++ <&ccu CLK_TCON_TV0>; ++ clock-names = "bus", ++ "tcon-tv0"; ++ clock-output-names = "tcon-top-tv0"; ++ resets = <&ccu RST_BUS_TCON_TOP>; ++ reset-names = "rst"; ++ #clock-cells = <1>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ tcon_top_mixer0_in: port@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ tcon_top_mixer0_in_mixer0: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&mixer0_out_tcon_top_mixer0>; ++ }; ++ }; ++ ++ tcon_top_mixer0_out: port@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ ++ tcon_top_mixer0_out_tcon_tv: endpoint@2 { ++ reg = <2>; ++ remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; ++ }; ++ }; ++ ++ tcon_top_hdmi_in: port@4 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <4>; ++ ++ tcon_top_hdmi_in_tcon_tv: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&tcon_tv_out_tcon_top>; ++ }; ++ }; ++ ++ tcon_top_hdmi_out: port@5 { ++ reg = <5>; ++ ++ tcon_top_hdmi_out_hdmi: endpoint { ++ remote-endpoint = <&hdmi_in_tcon_top>; ++ }; ++ }; ++ }; ++ }; ++ ++ tcon_tv: lcd-controller@6515000 { ++ compatible = "allwinner,sun50i-h6-tcon-tv", ++ "allwinner,sun8i-r40-tcon-tv"; ++ reg = <0x06515000 0x1000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_TCON_TV0>, ++ <&tcon_top CLK_TCON_TOP_TV0>; ++ clock-names = "ahb", ++ "tcon-ch1"; ++ resets = <&ccu RST_BUS_TCON_TV0>; ++ reset-names = "lcd"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ tcon_tv_in: port@0 { ++ reg = <0>; ++ ++ tcon_tv_in_tcon_top_mixer0: endpoint { ++ remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; ++ }; ++ }; ++ ++ tcon_tv_out: port@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ ++ tcon_tv_out_tcon_top: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; ++ }; ++ }; ++ }; ++ }; ++ + r_ccu: clock@7010000 { + compatible = "allwinner,sun50i-h6-r-ccu"; + reg = <0x07010000 0x400>; +diff --git a/include/dt-bindings/clock/sun8i-tcon-top.h b/include/dt-bindings/clock/sun8i-tcon-top.h +new file mode 100644 +index 0000000000..25164d7678 +--- /dev/null ++++ b/include/dt-bindings/clock/sun8i-tcon-top.h +@@ -0,0 +1,11 @@ ++/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ ++/* Copyright (C) 2018 Jernej Skrabec */ ++ ++#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ ++#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ ++ ++#define CLK_TCON_TOP_TV0 0 ++#define CLK_TCON_TOP_TV1 1 ++#define CLK_TCON_TOP_DSI 2 ++ ++#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */ diff --git a/projects/Allwinner/filesystem/usr/lib/systemd/system/serial-console.service b/projects/Allwinner/filesystem/usr/lib/systemd/system/serial-console.service new file mode 100644 index 0000000000..196e8c4a97 --- /dev/null +++ b/projects/Allwinner/filesystem/usr/lib/systemd/system/serial-console.service @@ -0,0 +1,23 @@ +[Unit] +Description=Debug Shell on /dev/console +DefaultDependencies=no +ConditionKernelCommandLine=console + +[Service] +WorkingDirectory=/storage +Environment="ENV=/etc/profile" +ExecStartPre=/bin/sh -c 'echo -en "\033[?25h"' +ExecStart=/bin/sh +Restart=always +RestartSec=0 +StandardInput=tty +TTYPath=/dev/console +TTYReset=yes +TTYVHangup=yes +KillMode=process +IgnoreSIGPIPE=no +# bash ignores SIGTERM +KillSignal=SIGHUP + +[Install] +WantedBy=sysinit.target diff --git a/projects/Allwinner/filesystem/usr/share/alsa/cards/allwinner-hdmi.conf b/projects/Allwinner/filesystem/usr/share/alsa/cards/allwinner-hdmi.conf new file mode 100644 index 0000000000..d9295919cd --- /dev/null +++ b/projects/Allwinner/filesystem/usr/share/alsa/cards/allwinner-hdmi.conf @@ -0,0 +1,34 @@ +# +# Configuration for HDMI +# + + + +allwinner-hdmi.pcm.hdmi.0 { + @args [ CARD AES0 AES1 AES2 AES3 ] + @args.CARD { type string } + @args.AES0 { type integer } + @args.AES1 { type integer } + @args.AES2 { type integer } + @args.AES3 { type integer } + type hooks + slave.pcm { + type hw + card $CARD + device 0 + } + hooks.0 { + type ctl_elems + hook_args [ + { + interface MIXER + name "IEC958 Playback Default" + lock true + preserve true + optional true + value [ $AES0 $AES1 $AES2 $AES3 ] + } + ] + } + hint.device 0 +} diff --git a/projects/Allwinner/filesystem/usr/share/alsa/cards/allwinner-spdif.conf b/projects/Allwinner/filesystem/usr/share/alsa/cards/allwinner-spdif.conf new file mode 100644 index 0000000000..a8e228a139 --- /dev/null +++ b/projects/Allwinner/filesystem/usr/share/alsa/cards/allwinner-spdif.conf @@ -0,0 +1,34 @@ +# +# Configuration for SPDIF +# + + + +On-board_SPDIF.pcm.iec958.0 { + @args [ CARD AES0 AES1 AES2 AES3 ] + @args.CARD { type string } + @args.AES0 { type integer } + @args.AES1 { type integer } + @args.AES2 { type integer } + @args.AES3 { type integer } + type hooks + slave.pcm { + type hw + card $CARD + device 0 + } + hooks.0 { + type ctl_elems + hook_args [ + { + interface MIXER + name "IEC958 Playback Default" + lock true + preserve true + optional true + value [ $AES0 $AES1 $AES2 $AES3 ] + } + ] + } + hint.device 0 +} diff --git a/projects/Allwinner/kodi/appliance.xml b/projects/Allwinner/kodi/appliance.xml new file mode 100644 index 0000000000..66832eaacb --- /dev/null +++ b/projects/Allwinner/kodi/appliance.xml @@ -0,0 +1,22 @@ + + + +
+ + + + false + 3 + + + + + + + ALSA:hdmi:CARD=allwinnerhdmi,DEV=0 + + + +
+ + diff --git a/projects/Allwinner/linux/linux.aarch64.conf b/projects/Allwinner/linux/linux.aarch64.conf new file mode 100644 index 0000000000..9a18ebe855 --- /dev/null +++ b/projects/Allwinner/linux/linux.aarch64.conf @@ -0,0 +1,5620 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm64 5.0.2 Kernel Configuration +# + +# +# Compiler: aarch64-linux-gnu-gcc.real (Linaro GCC 7.3-2018.05) 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] +# +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=70301 +CONFIG_CLANG_VERSION=0 +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_BUILD_SALT="" +CONFIG_DEFAULT_HOSTNAME="@DISTRONAME@" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_USELIB is not set +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_SCHED_AVG_IRQ=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +# CONFIG_PSI is not set +CONFIG_CPU_ISOLATION=y + +# +# RCU Subsystem +# +CONFIG_PREEMPT_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_BUILD_BIN2C=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_SWAP_ENABLED=y +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +# CONFIG_DEBUG_BLK_CGROUP is not set +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +# CONFIG_CGROUP_RDMA is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +# CONFIG_CHECKPOINT_RESTORE is not set +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_INITRAMFS_COMPRESSION=".gz" +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_BPF=y +# CONFIG_EXPERT is not set +CONFIG_UID16=y +CONFIG_MULTIUSER=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_BASE_RELATIVE=y +# CONFIG_BPF_SYSCALL is not set +# CONFIG_USERFAULTFD is not set +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_RSEQ=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SYSTEM_DATA_VERIFICATION=y +CONFIG_PROFILING=y +CONFIG_ARM64=y +CONFIG_64BIT=y +CONFIG_MMU=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_CONT_SHIFT=4 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=33 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_NO_IOPORT_MAP=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA32=y +CONFIG_HAVE_GENERIC_GUP=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_SMP=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=4 +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_PROC_KCORE_TEXT=y + +# +# Platform selection +# +# CONFIG_ARCH_ACTIONS is not set +CONFIG_ARCH_SUNXI=y +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_BRCMSTB is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_K3 is not set +# CONFIG_ARCH_LAYERSCAPE is not set +# CONFIG_ARCH_LG1K is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_REALTEK is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_SEATTLE is not set +# CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_SYNQUACER is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_SPRD is not set +# CONFIG_ARCH_THUNDER is not set +# CONFIG_ARCH_THUNDER2 is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_XGENE is not set +# CONFIG_ARCH_ZX is not set +# CONFIG_ARCH_ZYNQMP is not set + +# +# Kernel Features +# + +# +# ARM errata workarounds via the alternatives framework +# +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_832075=y +CONFIG_ARM64_ERRATUM_845719=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_ERRATUM_1024718=y +CONFIG_ARM64_ERRATUM_1188873=y +CONFIG_ARM64_ERRATUM_1165522=y +CONFIG_ARM64_ERRATUM_1286807=y +CONFIG_CAVIUM_ERRATUM_22375=y +CONFIG_CAVIUM_ERRATUM_23144=y +CONFIG_CAVIUM_ERRATUM_23154=y +CONFIG_CAVIUM_ERRATUM_27456=y +CONFIG_CAVIUM_ERRATUM_30115=y +CONFIG_QCOM_FALKOR_ERRATUM_1003=y +CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y +CONFIG_QCOM_FALKOR_ERRATUM_1009=y +CONFIG_QCOM_QDF2400_ERRATUM_0065=y +CONFIG_SOCIONEXT_SYNQUACER_PREITS=y +CONFIG_HISILICON_ERRATUM_161600802=y +CONFIG_QCOM_FALKOR_ERRATUM_E1041=y +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_16K_PAGES is not set +# CONFIG_ARM64_64K_PAGES is not set +# CONFIG_ARM64_VA_BITS_39 is not set +CONFIG_ARM64_VA_BITS_48=y +CONFIG_ARM64_VA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PA_BITS=48 +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_SCHED_MC=y +# CONFIG_SCHED_SMT is not set +CONFIG_NR_CPUS=64 +CONFIG_HOTPLUG_CPU=y +CONFIG_NUMA=y +CONFIG_NODES_SHIFT=2 +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_HAVE_SETUP_PER_CPU_AREA=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_HOLES_IN_ZONE=y +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_SCHED_HRTICK=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HW_PERF_EVENTS=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_SECCOMP=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +CONFIG_KEXEC=y +# CONFIG_KEXEC_FILE is not set +CONFIG_CRASH_DUMP=y +# CONFIG_XEN is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDEN_EL2_VECTORS=y +CONFIG_ARM64_SSBD=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +# CONFIG_ARMV8_DEPRECATED is not set +# CONFIG_ARM64_SW_TTBR0_PAN is not set + +# +# ARMv8.1 architectural features +# +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_PAN=y +CONFIG_ARM64_LSE_ATOMICS=y +CONFIG_ARM64_VHE=y + +# +# ARMv8.2 architectural features +# +CONFIG_ARM64_UAO=y +# CONFIG_ARM64_PMEM is not set +CONFIG_ARM64_RAS_EXTN=y +CONFIG_ARM64_CNP=y + +# +# ARMv8.3 architectural features +# +CONFIG_ARM64_PTR_AUTH=y +CONFIG_ARM64_SVE=y +CONFIG_ARM64_MODULE_PLTS=y +# CONFIG_RANDOMIZE_BASE is not set + +# +# Boot options +# +CONFIG_CMDLINE="" +# CONFIG_CMDLINE_FORCE is not set +CONFIG_EFI_STUB=y +CONFIG_EFI=y +CONFIG_DMI=y +CONFIG_COMPAT=y +CONFIG_SYSVIPC_COMPAT=y + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +CONFIG_PM_STD_PARTITION="" +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_CPU_PM=y +# CONFIG_ENERGY_MODEL is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y + +# +# CPU Power Management +# + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +# CONFIG_CPU_IDLE_GOV_LADDER is not set +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_DT_IDLE_STATES=y + +# +# ARM CPU Idle Drivers +# +CONFIG_ARM_CPUIDLE=y + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y + +# +# CPU frequency scaling drivers +# +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_ARM_SCPI_CPUFREQ=y +# CONFIG_QORIQ_CPUFREQ is not set + +# +# Firmware Drivers +# +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +# CONFIG_ARM_SCMI_PROTOCOL is not set +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_ARM_SCPI_POWER_DOMAIN=y +# CONFIG_ARM_SDE_INTERFACE is not set +CONFIG_DMIID=y +# CONFIG_DMI_SYSFS is not set +# CONFIG_INTEL_STRATIX10_SERVICE is not set +CONFIG_HAVE_ARM_SMCCC=y +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +# CONFIG_EFI_VARS is not set +CONFIG_EFI_ESRT=y +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_ARMSTUB=y +CONFIG_EFI_ARMSTUB_DTB_LOADER=y +CONFIG_EFI_CAPSULE_LOADER=y +# CONFIG_EFI_TEST is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set + +# +# Tegra firmware driver +# +CONFIG_ARCH_SUPPORTS_ACPI=y +# CONFIG_ACPI is not set +# CONFIG_VIRTUALIZATION is not set +CONFIG_ARM64_CRYPTO=y +CONFIG_CRYPTO_SHA256_ARM64=y +CONFIG_CRYPTO_SHA512_ARM64=m +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512_ARM64_CE=m +CONFIG_CRYPTO_SHA3_ARM64=m +CONFIG_CRYPTO_SM3_ARM64_CE=m +# CONFIG_CRYPTO_SM4_ARM64_CE is not set +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_NEON_BLK=m +CONFIG_CRYPTO_CHACHA20_NEON=m +# CONFIG_CRYPTO_NHPOLY1305_NEON is not set +CONFIG_CRYPTO_AES_ARM64_BS=m + +# +# General architecture-dependent options +# +CONFIG_CRASH_CORE=y +CONFIG_KEXEC_CORE=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_HAVE_RCU_TABLE_INVALIDATE=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_STACKLEAK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_CC_HAS_STACKPROTECTOR_NONE=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_COMPAT_OLD_SIGACTION=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_REFCOUNT_FULL=y +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_PLUGIN_HOSTCC="g++" +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +# CONFIG_BLK_DEV_ZONED is not set +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +# CONFIG_BLK_CMDLINE_PARSER is not set +# CONFIG_BLK_WBT is not set +CONFIG_BLK_CGROUP_IOLATENCY=y +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_BLOCK_COMPAT=y +CONFIG_BLK_PM=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_IOSCHED_BFQ is not set +CONFIG_ASN1=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_ELFCORE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Memory Management options +# +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_NEED_MULTIPLE_NODES=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_MEMORY_HOTPLUG is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +CONFIG_MEMORY_FAILURE=y +# CONFIG_HWPOISON_INJECT is not set +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +CONFIG_TRANSPARENT_HUGE_PAGECACHE=y +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_AREAS=7 +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FRAME_VECTOR=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_BENCHMARK is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_NET=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_NET_INGRESS=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +# CONFIG_TLS is not set +CONFIG_XFRM=y +CONFIG_XFRM_ALGO=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_INTERFACE is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=m +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +CONFIG_NET_UDP_TUNNEL=m +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +CONFIG_INET_ESP=y +# CONFIG_INET_ESP_OFFLOAD is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_RAW_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_ILA is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_NETLABEL is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=m + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_FAMILY_BRIDGE=y +# CONFIG_NETFILTER_NETLINK_ACCT is not set +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NETFILTER_NETLINK_OSF is not set +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_COMMON=m +# CONFIG_NF_LOG_NETDEV is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_ZONES is not set +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +# CONFIG_NF_CONNTRACK_LABELS is not set +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=m +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_NEEDED=y +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_REDIRECT=y +# CONFIG_NF_TABLES is not set +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +# CONFIG_NETFILTER_XT_MARK is not set +# CONFIG_NETFILTER_XT_CONNMARK is not set + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_LED is not set +CONFIG_NETFILTER_XT_TARGET_LOG=m +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +CONFIG_NETFILTER_XT_NAT=m +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_TPROXY is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +# CONFIG_NETFILTER_XT_MATCH_BPF is not set +# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ECN is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +CONFIG_NETFILTER_XT_MATCH_IPVS=m +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_IP_SET is not set +CONFIG_IP_VS=m +# CONFIG_IP_VS_IPV6 is not set +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +# CONFIG_IP_VS_PROTO_ESP is not set +# CONFIG_IP_VS_PROTO_AH is not set +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +# CONFIG_IP_VS_WRR is not set +# CONFIG_IP_VS_LC is not set +# CONFIG_IP_VS_WLC is not set +# CONFIG_IP_VS_FO is not set +# CONFIG_IP_VS_OVF is not set +# CONFIG_IP_VS_LBLC is not set +# CONFIG_IP_VS_LBLCR is not set +# CONFIG_IP_VS_DH is not set +# CONFIG_IP_VS_SH is not set +# CONFIG_IP_VS_MH is not set +# CONFIG_IP_VS_SED is not set +# CONFIG_IP_VS_NQ is not set + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS MH scheduler +# +CONFIG_IP_VS_MH_TAB_INDEX=12 + +# +# IPVS application helper +# +# CONFIG_IP_VS_FTP is not set +CONFIG_IP_VS_NFCT=y + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +# CONFIG_NF_SOCKET_IPV4 is not set +# CONFIG_NF_TPROXY_IPV4 is not set +# CONFIG_NF_DUP_IPV4 is not set +# CONFIG_NF_LOG_ARP is not set +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_NAT_IPV4=m +CONFIG_NF_NAT_MASQUERADE_IPV4=y +CONFIG_IP_NF_IPTABLES=m +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_RPFILTER is not set +# CONFIG_IP_NF_MATCH_TTL is not set +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +# CONFIG_IP_NF_TARGET_SYNPROXY is not set +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +# CONFIG_IP_NF_TARGET_NETMAP is not set +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_SECURITY is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_NF_SOCKET_IPV6 is not set +# CONFIG_NF_TPROXY_IPV6 is not set +# CONFIG_NF_DUP_IPV6 is not set +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_LOG_IPV6=m +CONFIG_NF_NAT_IPV6=m +CONFIG_NF_NAT_MASQUERADE_IPV6=y +CONFIG_IP6_NF_IPTABLES=m +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_RPFILTER is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_MATCH_SRH is not set +# CONFIG_IP6_NF_TARGET_HL is not set +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set +CONFIG_IP6_NF_MANGLE=m +# CONFIG_IP6_NF_RAW is not set +# CONFIG_IP6_NF_SECURITY is not set +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +# CONFIG_IP6_NF_TARGET_NPT is not set +CONFIG_NF_DEFRAG_IPV6=m +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_BPFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_MRP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_CBS is not set +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_TAPRIO is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_SKBPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_CODEL is not set +# CONFIG_NET_SCH_FQ_CODEL is not set +# CONFIG_NET_SCH_CAKE is not set +# CONFIG_NET_SCH_FQ is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_PIE is not set +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +CONFIG_NET_CLS_CGROUP=y +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOWER is not set +# CONFIG_NET_CLS_MATCHALL is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_NET_NSH is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +CONFIG_NET_L3_MASTER_DEV=y +# CONFIG_NET_NCSI is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_BPF_JIT=y +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +CONFIG_BT=m +CONFIG_BT_BREDR=y +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +# CONFIG_BT_HS is not set +CONFIG_BT_LE=y +CONFIG_BT_LEDS=y +# CONFIG_BT_SELFTEST is not set +# CONFIG_BT_DEBUGFS is not set + +# +# Bluetooth device drivers +# +CONFIG_BT_INTEL=m +CONFIG_BT_BCM=m +CONFIG_BT_RTL=m +CONFIG_BT_QCA=m +CONFIG_BT_HCIBTUSB=m +# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set +CONFIG_BT_HCIBTUSB_BCM=y +CONFIG_BT_HCIBTUSB_RTL=y +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_SERDEV=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_NOKIA=m +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_BT_MTKUART=m +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=m +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +# CONFIG_RFKILL_GPIO is not set +CONFIG_NET_9P=y +# CONFIG_NET_9P_DEBUG is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +# CONFIG_NET_IFE is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y +CONFIG_FAILOVER=y +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y +CONFIG_HAVE_PCI=y +# CONFIG_PCI is not set +# CONFIG_PCCARD is not set + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER is not set +CONFIG_WANT_DEV_COREDUMP=y +CONFIG_ALLOW_DEV_COREDUMP=y +CONFIG_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_SOC_BUS=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_IRQ=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_DMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +CONFIG_GENERIC_ARCH_TOPOLOGY=y + +# +# Bus devices +# +CONFIG_BRCMSTB_GISB_ARB=y +CONFIG_SIMPLE_PM_BUS=y +CONFIG_SUN50I_DE2_BUS=y +CONFIG_SUNXI_RSB=y +CONFIG_VEXPRESS_CONFIG=y +# CONFIG_CONNECTOR is not set +# CONFIG_GNSS is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# Partition parsers +# +# CONFIG_MTD_REDBOOT_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_ONENAND is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_ECC_BCH is not set +CONFIG_MTD_NAND_DENALI=y +CONFIG_MTD_NAND_DENALI_DT=y +# CONFIG_MTD_NAND_GPIO is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_BRCMNAND is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_NAND_SUNXI is not set +# CONFIG_MTD_SPI_NAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_MT81xx_NOR is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_MTD_UBI is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_RESOLVE=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_NUMA=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_RBD is not set + +# +# NVME Support +# +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_SRAM=y +CONFIG_VEXPRESS_SYSCFG=y +# CONFIG_PVPANIC is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +CONFIG_EEPROM_AT25=m +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC & related support +# + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set +# CONFIG_MISC_RTSX_USB is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +CONFIG_SCSI_SAS_ATTRS=y +CONFIG_SCSI_SAS_LIBSAS=y +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_HOST_SMP=y +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +CONFIG_SCSI_HISI_SAS=y +CONFIG_SCSI_UFSHCD=m +CONFIG_SCSI_UFSHCD_PLATFORM=m +# CONFIG_SCSI_UFS_CDNS_PLATFORM is not set +# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set +# CONFIG_SCSI_UFS_BSG is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_HAVE_PATA_PLATFORM=y +CONFIG_ATA=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_CEVA=y +# CONFIG_AHCI_SUNXI is not set +CONFIG_AHCI_XGENE=y +CONFIG_AHCI_QORIQ=y +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +# CONFIG_SATA_DWC is not set + +# +# PATA SFF controllers with BMDMA +# + +# +# PIO-only SFF controllers +# +CONFIG_PATA_PLATFORM=y +CONFIG_PATA_OF_PLATFORM=y + +# +# Generic fallback / legacy drivers +# +CONFIG_MD=y +# CONFIG_BLK_DEV_MD is not set +# CONFIG_BCACHE is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_BUFIO=m +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_PERSISTENT_DATA=m +# CONFIG_DM_UNSTRIPED is not set +# CONFIG_DM_CRYPT is not set +# CONFIG_DM_SNAPSHOT is not set +CONFIG_DM_THIN_PROVISIONING=m +# CONFIG_DM_CACHE is not set +# CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_VERITY is not set +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_DM_INTEGRITY is not set +# CONFIG_TARGET_CORE is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +CONFIG_DUMMY=m +# CONFIG_EQUALIZER is not set +# CONFIG_NET_TEAM is not set +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +# CONFIG_IPVTAP is not set +CONFIG_VXLAN=m +# CONFIG_GENEVE is not set +# CONFIG_GTP is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +CONFIG_TUN=y +CONFIG_TAP=m +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=m +# CONFIG_NLMON is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_ETHERNET=y +CONFIG_NET_VENDOR_ALACRITECH=y +CONFIG_NET_VENDOR_ALLWINNER=y +# CONFIG_SUN4I_EMAC is not set +# CONFIG_ALTERA_TSE is not set +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_NET_VENDOR_AMD=y +CONFIG_AMD_XGBE=y +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_AURORA=y +# CONFIG_AURORA_NB8800 is not set +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_BCMGENET is not set +# CONFIG_SYSTEMPORT is not set +CONFIG_NET_VENDOR_CADENCE=y +CONFIG_MACB=y +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_NET_VENDOR_CAVIUM=y +CONFIG_NET_VENDOR_CORTINA=y +# CONFIG_GEMINI_ETHERNET is not set +# CONFIG_DNET is not set +CONFIG_NET_VENDOR_EZCHIP=y +# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set +CONFIG_NET_VENDOR_HISILICON=y +CONFIG_HIX5HD2_GMAC=y +# CONFIG_HISI_FEMAC is not set +# CONFIG_HIP04_ETH is not set +CONFIG_HNS_MDIO=y +CONFIG_HNS=y +CONFIG_HNS_DSAF=y +CONFIG_HNS_ENET=y +CONFIG_NET_VENDOR_HUAWEI=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_MVMDIO=y +CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_MLXSW_CORE is not set +# CONFIG_MLXFW is not set +CONFIG_NET_VENDOR_MICREL=y +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_NET_VENDOR_MICROCHIP=y +# CONFIG_ENC28J60 is not set +# CONFIG_ENCX24J600 is not set +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NET_VENDOR_NETRONOME=y +CONFIG_NET_VENDOR_NI=y +# CONFIG_NI_XGE_MANAGEMENT_ENET is not set +CONFIG_NET_VENDOR_8390=y +# CONFIG_ETHOC is not set +CONFIG_NET_VENDOR_QUALCOMM=y +# CONFIG_QCA7000_SPI is not set +# CONFIG_QCA7000_UART is not set +CONFIG_QCOM_EMAC=m +# CONFIG_RMNET is not set +CONFIG_NET_VENDOR_RENESAS=y +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_NET_VENDOR_SAMSUNG=y +# CONFIG_SXGBE_ETH is not set +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SOLARFLARE=y +CONFIG_NET_VENDOR_SMSC=y +CONFIG_SMC91X=y +CONFIG_SMSC911X=y +CONFIG_NET_VENDOR_SOCIONEXT=y +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +# CONFIG_DWMAC_DWC_QOS_ETH is not set +CONFIG_DWMAC_GENERIC=y +CONFIG_DWMAC_SUNXI=y +CONFIG_DWMAC_SUN8I=y +CONFIG_NET_VENDOR_SYNOPSYS=y +# CONFIG_DWC_XLGMAC is not set +CONFIG_NET_VENDOR_VIA=y +# CONFIG_VIA_RHINE is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_NET_VENDOR_WIZNET=y +# CONFIG_WIZNET_W5100 is not set +# CONFIG_WIZNET_W5300 is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +# CONFIG_MDIO_BCM_UNIMAC is not set +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS_MUX=y +# CONFIG_MDIO_BUS_MUX_GPIO is not set +CONFIG_MDIO_BUS_MUX_MMIOREG=y +# CONFIG_MDIO_GPIO is not set +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_OCTEON is not set +# CONFIG_MDIO_SUN4I is not set +CONFIG_PHYLIB=y +CONFIG_SWPHY=y +# CONFIG_LED_TRIGGER_PHY is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_ASIX_PHY is not set +CONFIG_AT803X_PHY=m +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_10G_PHY=m +CONFIG_MICREL_PHY=y +CONFIG_MICROCHIP_PHY=m +# CONFIG_MICROCHIP_T1_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_REALTEK_PHY=y +# CONFIG_RENESAS_PHY is not set +CONFIG_ROCKCHIP_PHY=y +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +# CONFIG_USB_NET_CDC_EEM is not set +CONFIG_USB_NET_CDC_NCM=m +# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set +# CONFIG_USB_NET_CDC_MBIM is not set +CONFIG_USB_NET_DM9601=m +# CONFIG_USB_NET_SR9700 is not set +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +# CONFIG_USB_NET_GL620A is not set +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +# CONFIG_USB_NET_RNDIS_HOST is not set +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CDC_SUBSET=m +# CONFIG_USB_ALI_M5632 is not set +# CONFIG_USB_AN2720 is not set +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +# CONFIG_USB_EPSON2888 is not set +# CONFIG_USB_KC2190 is not set +CONFIG_USB_NET_ZAURUS=m +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_KALMIA is not set +# CONFIG_USB_NET_QMI_WWAN is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_USB_VL600 is not set +# CONFIG_USB_NET_CH9200 is not set +# CONFIG_USB_NET_AQC111 is not set +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_ATH_COMMON=m +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH9K is not set +# CONFIG_ATH9K_HTC is not set +# CONFIG_CARL9170 is not set +# CONFIG_ATH6KL is not set +# CONFIG_AR5523 is not set +CONFIG_ATH10K=m +CONFIG_ATH10K_CE=y +# CONFIG_ATH10K_SDIO is not set +# CONFIG_ATH10K_USB is not set +# CONFIG_ATH10K_DEBUG is not set +# CONFIG_ATH10K_DEBUGFS is not set +# CONFIG_WCN36XX is not set +CONFIG_WLAN_VENDOR_ATMEL=y +# CONFIG_AT76C50X_USB is not set +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +CONFIG_BRCMUTIL=m +# CONFIG_BRCMSMAC is not set +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_SDIO=y +# CONFIG_BRCMFMAC_USB is not set +# CONFIG_BRCM_TRACING is not set +# CONFIG_BRCMDBG is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +# CONFIG_HOSTAP is not set +# CONFIG_P54_COMMON is not set +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM is not set +CONFIG_MWIFIEX=m +# CONFIG_MWIFIEX_SDIO is not set +# CONFIG_MWIFIEX_USB is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +# CONFIG_MT7601U is not set +# CONFIG_MT76x0U is not set +# CONFIG_MT76x2U is not set +CONFIG_WLAN_VENDOR_RALINK=y +# CONFIG_RT2X00 is not set +CONFIG_WLAN_VENDOR_REALTEK=y +# CONFIG_RTL8187 is not set +CONFIG_RTL_CARDS=m +# CONFIG_RTL8192CU is not set +# CONFIG_RTL8XXXU is not set +CONFIG_WLAN_VENDOR_RSI=y +# CONFIG_RSI_91X is not set +CONFIG_WLAN_VENDOR_ST=y +# CONFIG_CW1200 is not set +CONFIG_WLAN_VENDOR_TI=y +# CONFIG_WL1251 is not set +# CONFIG_WL12XX is not set +CONFIG_WL18XX=m +CONFIG_WLCORE=m +# CONFIG_WLCORE_SPI is not set +CONFIG_WLCORE_SDIO=m +CONFIG_WILINK_PLATFORM_DATA=y +CONFIG_WLAN_VENDOR_ZYDAS=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_ZD1211RW is not set +CONFIG_WLAN_VENDOR_QUANTENNA=y +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_VIRT_WIFI is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_NETDEVSIM is not set +CONFIG_NET_FAILOVER=y +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_POLLDEV=m +# CONFIG_INPUT_SPARSEKMAP is not set +CONFIG_INPUT_MATRIXKMAP=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ADC=m +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_SUN4I_LRADC is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEYBOARD_CROS_EC=y +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_PROPERTIES=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_ADC is not set +# CONFIG_TOUCHSCREEN_AR1021_I2C is not set +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_BU21029 is not set +# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set +# CONFIG_TOUCHSCREEN_EXC3000 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_HIDEEP is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_S6SY761 is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_EKTF2127 is not set +# CONFIG_TOUCHSCREEN_ELAN is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_WACOM_I2C is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MMS114 is not set +# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_TSC2004 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_RM_TS is not set +# CONFIG_TOUCHSCREEN_SILEAD is not set +# CONFIG_TOUCHSCREEN_SIS_I2C is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_STMFTS is not set +# CONFIG_TOUCHSCREEN_SUN4I is not set +# CONFIG_TOUCHSCREEN_SUR40 is not set +# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set +# CONFIG_TOUCHSCREEN_SX8654 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_ZET6223 is not set +# CONFIG_TOUCHSCREEN_ZFORCE is not set +# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_DECODER is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_REGULATOR_HAPTIC is not set +CONFIG_INPUT_AXP20X_PEK=y +CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_PWM_VIBRA is not set +# CONFIG_INPUT_RK805_PWRKEY is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIO_AMBAKMI=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_APBPS2 is not set +# CONFIG_SERIO_OLPC_APSP is not set +# CONFIG_SERIO_SUN4I_PS2 is not set +# CONFIG_SERIO_GPIO_PS2 is not set +# CONFIG_USERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set +# CONFIG_SERIAL_8250_ASPEED_VUART is not set +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_DW=y +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_OF_PLATFORM=y + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=m +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +CONFIG_TCG_TPM=y +# CONFIG_TCG_TIS is not set +# CONFIG_TCG_TIS_SPI is not set +# CONFIG_TCG_TIS_I2C_ATMEL is not set +CONFIG_TCG_TIS_I2C_INFINEON=y +# CONFIG_TCG_TIS_I2C_NUVOTON is not set +# CONFIG_TCG_VTPM_PROXY is not set +# CONFIG_TCG_TIS_ST33ZP24_I2C is not set +# CONFIG_TCG_TIS_ST33ZP24_SPI is not set +# CONFIG_XILLYBUS is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_GPMUX is not set +# CONFIG_I2C_MUX_LTC4306 is not set +# CONFIG_I2C_MUX_PCA9541 is not set +CONFIG_I2C_MUX_PCA954x=y +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +# CONFIG_I2C_MUX_MLXCPLD is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CADENCE is not set +# CONFIG_I2C_CBUS_GPIO is not set +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +# CONFIG_I2C_DESIGNWARE_SLAVE is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_MV64XXX=y +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +CONFIG_I2C_RK3X=y +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +CONFIG_I2C_CROS_EC_TUNNEL=y +# CONFIG_I2C_STUB is not set +CONFIG_I2C_SLAVE=y +# CONFIG_I2C_SLAVE_EEPROM is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I3C is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +CONFIG_SPI_PL022=y +CONFIG_SPI_ROCKCHIP=y +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SUN4I is not set +# CONFIG_SPI_SUN6I is not set +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=m +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_SLAVE is not set +CONFIG_SPMI=y +# CONFIG_HSI is not set +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PINCTRL=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_PINMUX=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +CONFIG_PINCTRL_AXP209=y +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_MCP23S08 is not set +CONFIG_PINCTRL_SINGLE=y +# CONFIG_PINCTRL_SX150X is not set +CONFIG_PINCTRL_MAX77620=y +# CONFIG_PINCTRL_RK805 is not set +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_SUNXI=y +CONFIG_PINCTRL_SUN8I_H3_R=y +CONFIG_PINCTRL_SUN50I_A64=y +CONFIG_PINCTRL_SUN50I_A64_R=y +CONFIG_PINCTRL_SUN50I_H5=y +CONFIG_PINCTRL_SUN50I_H6=y +CONFIG_PINCTRL_SUN50I_H6_R=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set +CONFIG_GPIO_GENERIC=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_CADENCE is not set +CONFIG_GPIO_DWAPB=y +# CONFIG_GPIO_FTGPIO010 is not set +CONFIG_GPIO_GENERIC_PLATFORM=y +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_HLWD is not set +CONFIG_GPIO_MB86S7X=y +# CONFIG_GPIO_MOCKUP is not set +CONFIG_GPIO_PL061=y +# CONFIG_GPIO_SAMA5D2_PIOBU is not set +# CONFIG_GPIO_SYSCON is not set +CONFIG_GPIO_XGENE=y +# CONFIG_GPIO_XILINX is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_TPIC2810 is not set + +# +# MFD GPIO expanders +# +# CONFIG_GPIO_BD9571MWV is not set +CONFIG_GPIO_MAX77620=y + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_XRA1403 is not set + +# +# USB GPIO expanders +# +# CONFIG_W1 is not set +CONFIG_POWER_AVS=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_BRCMSTB=y +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_RESTART is not set +CONFIG_POWER_RESET_VEXPRESS=y +CONFIG_POWER_RESET_XGENE=y +CONFIG_POWER_RESET_SYSCON=y +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +CONFIG_REBOOT_MODE=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_GENERIC_ADC_BATTERY is not set +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_LEGO_EV3 is not set +CONFIG_BATTERY_SBS=m +# CONFIG_CHARGER_SBS is not set +# CONFIG_MANAGER_SBS is not set +CONFIG_BATTERY_BQ27XXX=y +CONFIG_BATTERY_BQ27XXX_I2C=y +# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set +CONFIG_AXP20X_POWER=y +# CONFIG_AXP288_FUEL_GAUGE is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_LTC3651 is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_CROS_USBPD is not set +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +CONFIG_SENSORS_ARM_SCPI=y +# CONFIG_SENSORS_ASPEED is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_FTSTEUTATES is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_IIO_HWMON is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX6621 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +CONFIG_SENSORS_LM90=m +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_PWM_FAN is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +CONFIG_SENSORS_INA2XX=m +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP108 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VEXPRESS is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83773G is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_THERMAL=y +# CONFIG_THERMAL_STATISTICS is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +# CONFIG_THERMAL_WRITABLE_TRIPS is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_BANG_BANG is not set +# CONFIG_THERMAL_GOV_USER_SPACE is not set +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +# CONFIG_CLOCK_THERMAL is not set +# CONFIG_DEVFREQ_THERMAL is not set +CONFIG_THERMAL_EMULATION=y +# CONFIG_MAX77620_THERMAL is not set +# CONFIG_QORIQ_THERMAL is not set +# CONFIG_GENERIC_ADC_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +CONFIG_ARM_SP805_WATCHDOG=y +# CONFIG_ARM_SBSA_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_SUNXI_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_MAX77620_WATCHDOG is not set +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_SUN4I_GPADC is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +CONFIG_MFD_BD9571MWV=y +# CONFIG_MFD_AC100 is not set +CONFIG_MFD_AXP20X=y +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_AXP20X_RSB=y +CONFIG_MFD_CROS_EC=y +CONFIG_MFD_CROS_EC_CHARDEV=m +# CONFIG_MFD_MADERA is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +CONFIG_MFD_HI6421_PMIC=y +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +CONFIG_MFD_MAX77620=y +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RC5T583 is not set +CONFIG_MFD_RK808=y +# CONFIG_MFD_RN5T618 is not set +CONFIG_MFD_SEC_CORE=y +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SUN6I_PRCM is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +CONFIG_MFD_VEXPRESS_SYSREG=y +# CONFIG_RAVE_SP_CORE is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_88PG86X is not set +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ANATOP is not set +CONFIG_REGULATOR_AXP20X=y +CONFIG_REGULATOR_BD9571MWV=y +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR_GPIO=y +# CONFIG_REGULATOR_HI6421 is not set +CONFIG_REGULATOR_HI6421V530=y +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_LTC3676 is not set +# CONFIG_REGULATOR_MAX1586 is not set +CONFIG_REGULATOR_MAX77620=y +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_QCOM_SPMI=y +CONFIG_REGULATOR_RK808=y +# CONFIG_REGULATOR_S2MPA01 is not set +CONFIG_REGULATOR_S2MPS11=y +# CONFIG_REGULATOR_S5M8767 is not set +# CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_REGULATOR_VCTRL=m +# CONFIG_REGULATOR_VEXPRESS is not set +CONFIG_CEC_CORE=y +CONFIG_CEC_NOTIFIER=y +CONFIG_CEC_PIN=y +CONFIG_RC_CORE=y +CONFIG_RC_MAP=y +CONFIG_LIRC=y +CONFIG_RC_DECODERS=y +CONFIG_IR_NEC_DECODER=y +CONFIG_IR_RC5_DECODER=y +CONFIG_IR_RC6_DECODER=y +CONFIG_IR_JVC_DECODER=y +CONFIG_IR_SONY_DECODER=y +CONFIG_IR_SANYO_DECODER=y +CONFIG_IR_SHARP_DECODER=y +CONFIG_IR_MCE_KBD_DECODER=y +CONFIG_IR_XMP_DECODER=y +CONFIG_IR_IMON_DECODER=y +CONFIG_IR_RCMM_DECODER=y +CONFIG_RC_DEVICES=y +# CONFIG_RC_ATI_REMOTE is not set +# CONFIG_IR_HIX5HD2 is not set +# CONFIG_IR_IMON is not set +# CONFIG_IR_IMON_RAW is not set +# CONFIG_IR_MCEUSB is not set +# CONFIG_IR_REDRAT3 is not set +# CONFIG_IR_SPI is not set +# CONFIG_IR_STREAMZAP is not set +# CONFIG_IR_IGORPLUGUSB is not set +# CONFIG_IR_IGUANA is not set +# CONFIG_IR_TTUSBIR is not set +# CONFIG_RC_LOOPBACK is not set +# CONFIG_IR_GPIO_CIR is not set +# CONFIG_IR_GPIO_TX is not set +# CONFIG_IR_PWM_TX is not set +CONFIG_IR_SUNXI=y +# CONFIG_IR_SERIAL is not set +# CONFIG_IR_SIR is not set +CONFIG_RC_XBOX_DVD=y +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_SDR_SUPPORT is not set +CONFIG_MEDIA_CEC_SUPPORT=y +# CONFIG_MEDIA_CEC_RC is not set +# CONFIG_CEC_PIN_ERROR_INJ is not set +CONFIG_MEDIA_CONTROLLER=y +# CONFIG_MEDIA_CONTROLLER_DVB is not set +CONFIG_MEDIA_CONTROLLER_REQUEST_API=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_V4L2=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_TUNER=m +CONFIG_V4L2_MEM2MEM_DEV=y +CONFIG_V4L2_FWNODE=m +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_VMALLOC=m +CONFIG_DVB_CORE=y +# CONFIG_DVB_MMAP is not set +# CONFIG_DVB_NET is not set +CONFIG_TTPCI_EEPROM=m +CONFIG_DVB_MAX_ADAPTERS=16 +# CONFIG_DVB_DYNAMIC_MINORS is not set +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_ULE_DEBUG is not set + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +# CONFIG_USB_M5602 is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_GL860 is not set +# CONFIG_USB_GSPCA_BENQ is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_CPIA1 is not set +# CONFIG_USB_GSPCA_DTCS033 is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_JEILINJ is not set +# CONFIG_USB_GSPCA_JL2005BCD is not set +# CONFIG_USB_GSPCA_KINECT is not set +# CONFIG_USB_GSPCA_KONICA is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_NW80X is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_OV534_9 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7302 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SE401 is not set +# CONFIG_USB_GSPCA_SN9C2028 is not set +# CONFIG_USB_GSPCA_SN9C20X is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SPCA1528 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_SQ930X is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_STK1135 is not set +# CONFIG_USB_GSPCA_STV0680 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TOPRO is not set +# CONFIG_USB_GSPCA_TOUPTEK is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_VICAM is not set +# CONFIG_USB_GSPCA_XIRLINK_CIT is not set +# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_USB_PWC is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_VIDEO_USBTV is not set + +# +# Analog TV USB devices +# +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_USBVISION=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_STK1160=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_LOADER=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m + +# +# Analog/digital TV USB devices +# +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_V4L2=y +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m + +# +# Digital TV USB devices +# +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_DIB3000MC=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_ZD1301=m +CONFIG_SMS_USB_DRV=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set +CONFIG_DVB_AS102=m + +# +# Webcam, TV (analog/digital) USB devices +# +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_VIDEO_EM28XX_RC=m + +# +# USB HDMI CEC adapters +# +# CONFIG_V4L_PLATFORM_DRIVERS is not set +CONFIG_V4L_MEM2MEM_DRIVERS=y +# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set +# CONFIG_VIDEO_SH_VEU is not set +# CONFIG_V4L_TEST_DRIVERS is not set +# CONFIG_DVB_PLATFORM_DRIVERS is not set +# CONFIG_CEC_PLATFORM_DRIVERS is not set + +# +# Supported MMC/SDIO adapters +# +# CONFIG_SMS_SDIO_DRV is not set +CONFIG_MEDIA_COMMON_OPTIONS=y + +# +# common driver options +# +CONFIG_VIDEO_CX2341X=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_CYPRESS_FIRMWARE=m +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_V4L2=y +CONFIG_VIDEOBUF2_MEMOPS=y +CONFIG_VIDEOBUF2_DMA_CONTIG=y +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_DVB_B2C2_FLEXCOP=m +CONFIG_SMS_SIANO_MDTV=m +CONFIG_SMS_SIANO_RC=y + +# +# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) +# +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y +CONFIG_MEDIA_ATTACH=y +CONFIG_VIDEO_IR_I2C=y + +# +# Audio decoders, processors and mixers +# +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_WM8775=m +CONFIG_VIDEO_SONY_BTF_MPX=m + +# +# RDS decoders +# + +# +# Video decoders +# +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m + +# +# Video and audio decoders +# +CONFIG_VIDEO_CX25840=m + +# +# Video encoders +# + +# +# Camera sensor devices +# +CONFIG_VIDEO_OV2640=m +CONFIG_VIDEO_OV7640=m +CONFIG_VIDEO_MT9V011=m + +# +# Flash devices +# + +# +# Video improvement chips +# + +# +# Audio/Video compression chips +# + +# +# SDR tuner chips +# + +# +# Miscellaneous helper chips +# + +# +# Sensors used on soc_camera driver +# + +# +# Media SPI Adapters +# +# CONFIG_CXD2880_SPI_DRV is not set +CONFIG_MEDIA_TUNER=y +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA827X=y +CONFIG_MEDIA_TUNER_TDA18271=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_XC4000=y +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m + +# +# Multistandard (satellite) frontends +# +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_M88DS3103=m + +# +# Multistandard (cable + terrestrial) frontends +# +CONFIG_DVB_DRXK=m +CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24123=m +CONFIG_DVB_MT312=m +CONFIG_DVB_ZL10039=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_TS2020=m +CONFIG_DVB_DS3000=m +CONFIG_DVB_TDA10071=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_CX22702=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_MT352=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_EC100=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_SI2168=m +CONFIG_DVB_AS102_FE=m +CONFIG_DVB_ZD1301_DEMOD=m +CONFIG_DVB_GP8PSK_FE=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_TDA10023=m +CONFIG_DVB_STV0297=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_NXT200X=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m +CONFIG_DVB_S5H1411=m + +# +# ISDB-T (terrestrial) frontends +# +CONFIG_DVB_S921=m +CONFIG_DVB_DIB8000=m +CONFIG_DVB_MB86A20S=m + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +CONFIG_DVB_TC90522=m + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_A8293=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_AF9033=m + +# +# Common Interface (EN50221) controller drivers +# +CONFIG_DVB_SP2=m + +# +# Tools to develop new frontends +# + +# +# Graphics support +# +CONFIG_DRM=y +# CONFIG_DRM_DP_AUX_CHARDEV is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_SELFTEST is not set +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_KMS_FB_HELPER=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +# CONFIG_DRM_DP_CEC is not set +CONFIG_DRM_GEM_CMA_HELPER=y +CONFIG_DRM_KMS_CMA_HELPER=y + +# +# I2C encoder or helper chips +# +CONFIG_DRM_I2C_CH7006=m +CONFIG_DRM_I2C_SIL164=m +# CONFIG_DRM_I2C_NXP_TDA998X is not set +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# CONFIG_DRM_HDLCD is not set +# CONFIG_DRM_MALI_DISPLAY is not set + +# +# ACP (Audio CoProcessor) Configuration +# + +# +# AMD Library routines +# +# CONFIG_DRM_VGEM is not set +# CONFIG_DRM_VKMS is not set +# CONFIG_DRM_UDL is not set +# CONFIG_DRM_RCAR_DW_HDMI is not set +# CONFIG_DRM_RCAR_LVDS is not set +CONFIG_DRM_SUN4I=y +# CONFIG_DRM_SUN4I_HDMI is not set +# CONFIG_DRM_SUN4I_BACKEND is not set +# CONFIG_DRM_SUN6I_DSI is not set +CONFIG_DRM_SUN8I_DW_HDMI=y +CONFIG_DRM_SUN8I_DW_HDMI_CEC=y +CONFIG_DRM_SUN8I_MIXER=y +CONFIG_DRM_SUN8I_TCON_TOP=y +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_LVDS is not set +CONFIG_DRM_PANEL_SIMPLE=m +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_DUMB_VGA_DAC is not set +# CONFIG_DRM_LVDS_ENCODER is not set +# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +# CONFIG_DRM_NXP_PTN3460 is not set +# CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_SIL_SII8620 is not set +# CONFIG_DRM_SII902X is not set +# CONFIG_DRM_SII9234 is not set +# CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TOSHIBA_TC358764 is not set +# CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_I2C_ADV7511 is not set +CONFIG_DRM_DW_HDMI=y +# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set +CONFIG_DRM_DW_HDMI_I2S_AUDIO=y +CONFIG_DRM_DW_HDMI_CEC=y +# CONFIG_DRM_ARCPGU is not set +# CONFIG_DRM_HISI_KIRIN is not set +# CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_TINYDRM is not set +# CONFIG_DRM_PL111 is not set +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_ARMCLCD=y +# CONFIG_FB_EFI is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SSD1307 is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +# CONFIG_LCD_AMS369FG06 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_HX8357 is not set +# CONFIG_LCD_OTM3225A is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=m +CONFIG_BACKLIGHT_PWM=m +# CONFIG_BACKLIGHT_PM8941_WLED is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +CONFIG_BACKLIGHT_LP855X=m +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# CONFIG_LOGO is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_DMAENGINE_PCM=y +CONFIG_SND_HWDEP=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +# CONFIG_SND_OSSEMUL is not set +CONFIG_SND_PCM_TIMER=y +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_PROC_FS=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# HD-Audio +# +CONFIG_SND_HDA_PREALLOC_SIZE=64 +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_VARIAX is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_DESIGNWARE_I2S is not set + +# +# SoC Audio for Freescale CPUs +# + +# +# Common SoC Audio options for Freescale CPUs: +# +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# CONFIG_SND_I2S_HI6210_I2S is not set +# CONFIG_SND_SOC_IMG is not set + +# +# STMicroelectronics STM32 SOC audio support +# + +# +# Allwinner SoC Audio support +# +CONFIG_SND_SUN4I_CODEC=y +CONFIG_SND_SUN8I_CODEC=y +CONFIG_SND_SUN8I_CODEC_ANALOG=y +CONFIG_SND_SUN50I_CODEC_ANALOG=y +CONFIG_SND_SUN4I_I2S=y +CONFIG_SND_SUN4I_SPDIF=y +CONFIG_SND_SUN8I_ADDA_PR_REGMAP=y +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +# CONFIG_ZX_TDM is not set +CONFIG_SND_SOC_I2C_AND_SPI=y + +# +# CODEC drivers +# +# CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_ADAU1761_I2C is not set +# CONFIG_SND_SOC_ADAU1761_SPI is not set +# CONFIG_SND_SOC_ADAU7002 is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4458 is not set +# CONFIG_SND_SOC_AK4554 is not set +CONFIG_SND_SOC_AK4613=m +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_AK5558 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_BD28623 is not set +# CONFIG_SND_SOC_BT_SCO is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS35L33 is not set +# CONFIG_SND_SOC_CS35L34 is not set +# CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS42L42 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_DMIC is not set +CONFIG_SND_SOC_HDMI_CODEC=y +# CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8316 is not set +# CONFIG_SND_SOC_ES8328_I2C is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_INNO_RK3036 is not set +# CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98504 is not set +# CONFIG_SND_SOC_MAX9867 is not set +# CONFIG_SND_SOC_MAX98927 is not set +# CONFIG_SND_SOC_MAX98373 is not set +# CONFIG_SND_SOC_MAX9860 is not set +# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1789_I2C is not set +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_I2C is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RT5616 is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set +# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TAS5720 is not set +# CONFIG_SND_SOC_TAS6424 is not set +# CONFIG_SND_SOC_TDA7419 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set +# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_TSCS42XX is not set +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8524 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8960 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_ZX_AUD96P22 is not set +# CONFIG_SND_SOC_MAX9759 is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_NAU8540 is not set +# CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8822 is not set +# CONFIG_SND_SOC_NAU8824 is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +CONFIG_SND_SIMPLE_CARD_UTILS=y +CONFIG_SND_SIMPLE_CARD=y +# CONFIG_SND_SIMPLE_SCU_CARD is not set +CONFIG_SND_AUDIO_GRAPH_CARD=y +# CONFIG_SND_AUDIO_GRAPH_SCU_CARD is not set + +# +# HID support +# +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HIDRAW is not set +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +# CONFIG_HID_ACCUTOUCH is not set +# CONFIG_HID_ACRUX is not set +CONFIG_HID_APPLE=y +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_ASUS is not set +# CONFIG_HID_AUREAL is not set +CONFIG_HID_BELKIN=y +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_BIGBEN_FF is not set +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +# CONFIG_HID_CORSAIR is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_CMEDIA is not set +CONFIG_HID_CYPRESS=y +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELAN is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +CONFIG_HID_EZKEY=y +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_GOOGLE_HAMMER is not set +# CONFIG_HID_GT683R is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +CONFIG_HID_ITE=y +# CONFIG_HID_JABRA is not set +# CONFIG_HID_TWINHAN is not set +CONFIG_HID_KENSINGTON=y +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LED is not set +# CONFIG_HID_LENOVO is not set +CONFIG_HID_LOGITECH=y +# CONFIG_HID_LOGITECH_HIDPP is not set +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGIG940_FF is not set +# CONFIG_LOGIWHEELS_FF is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MAYFLASH is not set +CONFIG_HID_REDRAGON=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTI is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_OUYA is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_RETRODE is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_ALPS is not set + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# I2C HID support +# +CONFIG_I2C_HID=m +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_OTG_FSM is not set +# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +CONFIG_USB_UAS=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +CONFIG_USB_MUSB_HDRC=y +# CONFIG_USB_MUSB_HOST is not set +# CONFIG_USB_MUSB_GADGET is not set +CONFIG_USB_MUSB_DUAL_ROLE=y + +# +# Platform Glue Layer +# +CONFIG_USB_MUSB_SUNXI=y + +# +# MUSB DMA mode +# +# CONFIG_MUSB_PIO_ONLY is not set +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_ULPI is not set +# CONFIG_USB_DWC3_HOST is not set +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_DUAL_ROLE=y + +# +# Platform Glue Driver Support +# +CONFIG_USB_DWC3_OF_SIMPLE=y +CONFIG_USB_DWC2=y +# CONFIG_USB_DWC2_HOST is not set + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_PERIPHERAL is not set +CONFIG_USB_DWC2_DUAL_ROLE=y +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_OF=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_ISP1760=y +CONFIG_USB_ISP1760_HCD=y +CONFIG_USB_ISP1761_UDC=y +# CONFIG_USB_ISP1760_HOST_ROLE is not set +# CONFIG_USB_ISP1760_GADGET_ROLE is not set +CONFIG_USB_ISP1760_DUAL_ROLE=y + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HUB_USB251XB is not set +CONFIG_USB_HSIC_USB3503=y +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_CHAOSKEY is not set + +# +# USB Physical Layer drivers +# +CONFIG_USB_PHY=y +CONFIG_NOP_USB_XCEIV=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +CONFIG_USB_ULPI=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 + +# +# USB Peripheral Controller +# +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_GR_UDC is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +CONFIG_USB_SNP_CORE=y +CONFIG_USB_SNP_UDC_PLAT=y +# CONFIG_USB_M66592 is not set +CONFIG_USB_BDC_UDC=y + +# +# Platform Support +# +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_DUMMY_HCD is not set +# CONFIG_USB_CONFIGFS is not set +# CONFIG_TYPEC is not set +# CONFIG_USB_ROLE_SWITCH is not set +# CONFIG_USB_LED_TRIG is not set +CONFIG_USB_ULPI_BUS=y +# CONFIG_UWB is not set +CONFIG_MMC=y +CONFIG_PWRSEQ_EMMC=y +# CONFIG_PWRSEQ_SD8787 is not set +CONFIG_PWRSEQ_SIMPLE=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=32 +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_STM32_SDMMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +# CONFIG_MMC_SDHCI_OF_AT91 is not set +# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_MMC_SDHCI_F_SDH30=y +CONFIG_MMC_SPI=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_PLTFM=y +# CONFIG_MMC_DW_BLUEFIELD is not set +CONFIG_MMC_DW_EXYNOS=y +CONFIG_MMC_DW_HI3798CV200=y +CONFIG_MMC_DW_K3=y +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_SUNXI=y +CONFIG_MMC_CQHCI=y +# CONFIG_MMC_MTK is not set +CONFIG_MMC_SDHCI_XENON=y +# CONFIG_MMC_SDHCI_OMAP is not set +# CONFIG_MMC_SDHCI_AM654 is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set + +# +# LED drivers +# +# CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LM3692X is not set +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP3952 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_DAC124S085 is not set +CONFIG_LEDS_PWM=y +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_IS31FL319X is not set +# CONFIG_LEDS_IS31FL32XX is not set + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +# CONFIG_LEDS_BLINKM is not set +CONFIG_LEDS_SYSCON=y +# CONFIG_LEDS_MLXREG is not set +# CONFIG_LEDS_USER is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +CONFIG_LEDS_TRIGGER_DISK=y +# CONFIG_LEDS_TRIGGER_MTD is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +CONFIG_LEDS_TRIGGER_CPU=y +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +CONFIG_LEDS_TRIGGER_PANIC=y +# CONFIG_LEDS_TRIGGER_NETDEV is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +# CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +CONFIG_RTC_DRV_MAX77686=y +CONFIG_RTC_DRV_RK808=m +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12026 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV8803 is not set +CONFIG_RTC_DRV_S5M=y + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +CONFIG_RTC_DRV_DS3232=y +CONFIG_RTC_DRV_DS3232_HWMON=y +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +CONFIG_RTC_DRV_EFI=y +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set +CONFIG_RTC_DRV_CROS_EC=y + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +CONFIG_RTC_DRV_PL031=y +CONFIG_RTC_DRV_SUN6I=y +# CONFIG_RTC_DRV_FTRTC010 is not set +# CONFIG_RTC_DRV_SNVS is not set +# CONFIG_RTC_DRV_R7301 is not set + +# +# HID Sensor RTC drivers +# +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DMA_OF=y +# CONFIG_ALTERA_MSGDMA is not set +# CONFIG_AMBA_PL08X is not set +CONFIG_BCM_SBA_RAID=m +CONFIG_DMA_SUN6I=y +# CONFIG_DW_AXI_DMAC is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_INTEL_IDMA64 is not set +CONFIG_MV_XOR_V2=y +CONFIG_PL330_DMA=y +# CONFIG_XILINX_DMA is not set +# CONFIG_XILINX_ZYNQMP_DMA is not set +CONFIG_QCOM_HIDMA_MGMT=y +CONFIG_QCOM_HIDMA=y +# CONFIG_DW_DMAC is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +CONFIG_DMA_ENGINE_RAID=y + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +# CONFIG_SW_SYNC is not set +# CONFIG_UDMABUF is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_VIRTIO_MENU is not set + +# +# Microsoft Hyper-V guest support +# +CONFIG_STAGING=y +# CONFIG_PRISM2_USB is not set +# CONFIG_COMEDI is not set +# CONFIG_RTLLIB is not set +CONFIG_RTL8723BS=m +# CONFIG_R8712U is not set +# CONFIG_R8188EU is not set +# CONFIG_VT6656 is not set + +# +# IIO staging drivers +# + +# +# Accelerometers +# +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16240 is not set + +# +# Analog to digital converters +# +# CONFIG_AD7606 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7280 is not set + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# CONFIG_AD7152 is not set +# CONFIG_AD7746 is not set + +# +# Direct Digital Synthesis +# +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set + +# +# Active energy metering IC +# +# CONFIG_ADE7854 is not set + +# +# Resolver to digital converters +# +# CONFIG_AD2S1210 is not set + +# +# Speakup console speech +# +# CONFIG_SPEAKUP is not set +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_SUNXI=y +CONFIG_VIDEO_SUNXI_CEDRUS=y + +# +# Android +# +# CONFIG_STAGING_BOARD is not set +# CONFIG_LTE_GDM724X is not set +# CONFIG_GS_FPGABOOT is not set +# CONFIG_UNISYSSPAR is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +# CONFIG_FB_TFT is not set +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +# CONFIG_MOST is not set +# CONFIG_KS7010 is not set +# CONFIG_GREYBUS is not set +# CONFIG_PI433 is not set +# CONFIG_MTK_MMC is not set + +# +# Gasket devices +# +# CONFIG_XIL_AXIS_FIFO is not set +# CONFIG_EROFS_FS is not set +# CONFIG_GOLDFISH is not set +CONFIG_CHROME_PLATFORMS=y +CONFIG_CROS_EC_CTL=m +CONFIG_CROS_EC_I2C=y +CONFIG_CROS_EC_SPI=y +CONFIG_CROS_EC_PROTO=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_VERSATILE is not set +# CONFIG_CLK_HSDK is not set +# CONFIG_COMMON_CLK_MAX77686 is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_RK808 is not set +CONFIG_COMMON_CLK_SCPI=y +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_S2MPS11 is not set +# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_XGENE is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_VC5 is not set +CONFIG_SUNXI_CCU=y +CONFIG_SUN50I_A64_CCU=y +CONFIG_SUN50I_H6_CCU=y +CONFIG_SUN50I_H6_R_CCU=y +# CONFIG_SUN8I_A83T_CCU is not set +CONFIG_SUN8I_H3_CCU=y +CONFIG_SUN8I_DE2_CCU=y +CONFIG_SUN8I_R_CCU=y +CONFIG_HWSPINLOCK=y + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_CLKSRC_MMIO=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +CONFIG_FSL_ERRATUM_A008585=y +CONFIG_HISILICON_ERRATUM_161010101=y +CONFIG_ARM64_ERRATUM_858921=y +CONFIG_SUN50I_ERRATUM_UNKNOWN1=y +CONFIG_ARM_TIMER_SP804=y +CONFIG_CLKSRC_VERSATILE=y +CONFIG_MAILBOX=y +CONFIG_ARM_MHU=y +CONFIG_PLATFORM_MHU=y +# CONFIG_PL320_MBOX is not set +# CONFIG_ALTERA_MBOX is not set +# CONFIG_MAILBOX_TEST is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set + +# +# Rpmsg drivers +# +CONFIG_RPMSG=y +# CONFIG_RPMSG_CHAR is not set +CONFIG_RPMSG_QCOM_GLINK_NATIVE=y +CONFIG_RPMSG_QCOM_GLINK_RPM=y +# CONFIG_RPMSG_VIRTIO is not set +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# + +# +# Broadcom SoC drivers +# +CONFIG_SOC_BRCMSTB=y + +# +# NXP/Freescale QorIQ SoC drivers +# + +# +# i.MX SoC drivers +# + +# +# Qualcomm SoC drivers +# +CONFIG_SUNXI_SRAM=y +CONFIG_SOC_TI=y + +# +# Xilinx SoC drivers +# +# CONFIG_XILINX_VCU is not set +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +# CONFIG_DEVFREQ_GOV_USERSPACE is not set +# CONFIG_DEVFREQ_GOV_PASSIVE is not set + +# +# DEVFREQ Drivers +# +# CONFIG_PM_DEVFREQ_EVENT is not set +CONFIG_EXTCON=y + +# +# Extcon Device Drivers +# +# CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_EXTCON_GPIO is not set +# CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +CONFIG_EXTCON_USB_GPIO=y +CONFIG_EXTCON_USBC_CROS_EC=y +CONFIG_MEMORY=y +# CONFIG_ARM_PL172_MPMC is not set +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +# CONFIG_IIO_BUFFER_CB is not set +# CONFIG_IIO_BUFFER_HW_CONSUMER is not set +CONFIG_IIO_KFIFO_BUF=m +CONFIG_IIO_TRIGGERED_BUFFER=m +# CONFIG_IIO_CONFIGFS is not set +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +# CONFIG_IIO_SW_DEVICE is not set +# CONFIG_IIO_SW_TRIGGER is not set + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADXL345_I2C is not set +# CONFIG_ADXL345_SPI is not set +# CONFIG_ADXL372_SPI is not set +# CONFIG_ADXL372_I2C is not set +# CONFIG_BMA180 is not set +# CONFIG_BMA220 is not set +# CONFIG_BMC150_ACCEL is not set +# CONFIG_DA280 is not set +# CONFIG_DA311 is not set +# CONFIG_DMARD06 is not set +# CONFIG_DMARD09 is not set +# CONFIG_DMARD10 is not set +# CONFIG_IIO_CROS_EC_ACCEL_LEGACY is not set +# CONFIG_IIO_ST_ACCEL_3AXIS is not set +# CONFIG_KXSD9 is not set +# CONFIG_KXCJK1013 is not set +# CONFIG_MC3230 is not set +# CONFIG_MMA7455_I2C is not set +# CONFIG_MMA7455_SPI is not set +# CONFIG_MMA7660 is not set +# CONFIG_MMA8452 is not set +# CONFIG_MMA9551 is not set +# CONFIG_MMA9553 is not set +# CONFIG_MXC4005 is not set +# CONFIG_MXC6255 is not set +# CONFIG_SCA3000 is not set +# CONFIG_STK8312 is not set +# CONFIG_STK8BA50 is not set + +# +# Analog to digital converters +# +# CONFIG_AD7124 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7291 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7766 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD7949 is not set +# CONFIG_AD799X is not set +# CONFIG_AXP20X_ADC is not set +# CONFIG_AXP288_ADC is not set +# CONFIG_CC10001_ADC is not set +# CONFIG_ENVELOPE_DETECTOR is not set +# CONFIG_HI8435 is not set +# CONFIG_HX711 is not set +# CONFIG_INA2XX_ADC is not set +# CONFIG_LTC2471 is not set +# CONFIG_LTC2485 is not set +# CONFIG_LTC2497 is not set +# CONFIG_MAX1027 is not set +# CONFIG_MAX11100 is not set +# CONFIG_MAX1118 is not set +# CONFIG_MAX1363 is not set +# CONFIG_MAX9611 is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +# CONFIG_MCP3911 is not set +# CONFIG_NAU7802 is not set +# CONFIG_QCOM_SPMI_IADC is not set +# CONFIG_QCOM_SPMI_VADC is not set +# CONFIG_QCOM_SPMI_ADC5 is not set +# CONFIG_SD_ADC_MODULATOR is not set +# CONFIG_TI_ADC081C is not set +# CONFIG_TI_ADC0832 is not set +# CONFIG_TI_ADC084S021 is not set +# CONFIG_TI_ADC12138 is not set +# CONFIG_TI_ADC108S102 is not set +# CONFIG_TI_ADC128S052 is not set +# CONFIG_TI_ADC161S626 is not set +# CONFIG_TI_ADS1015 is not set +# CONFIG_TI_ADS7950 is not set +# CONFIG_TI_ADS8688 is not set +# CONFIG_TI_TLC4541 is not set +# CONFIG_VF610_ADC is not set + +# +# Analog Front Ends +# +# CONFIG_IIO_RESCALE is not set + +# +# Amplifiers +# +# CONFIG_AD8366 is not set + +# +# Chemical Sensors +# +# CONFIG_ATLAS_PH_SENSOR is not set +# CONFIG_BME680 is not set +# CONFIG_CCS811 is not set +# CONFIG_IAQCORE is not set +# CONFIG_VZ89X is not set +CONFIG_IIO_CROS_EC_SENSORS_CORE=m +CONFIG_IIO_CROS_EC_SENSORS=m + +# +# Hid Sensor IIO Common +# + +# +# SSP Sensor Common +# +# CONFIG_IIO_SSP_SENSORHUB is not set + +# +# Counters +# + +# +# Digital to analog converters +# +# CONFIG_AD5064 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5592R is not set +# CONFIG_AD5593R is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_LTC1660 is not set +# CONFIG_LTC2632 is not set +# CONFIG_AD5686_SPI is not set +# CONFIG_AD5696_I2C is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5758 is not set +# CONFIG_AD5761 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5791 is not set +# CONFIG_AD7303 is not set +# CONFIG_AD8801 is not set +# CONFIG_DPOT_DAC is not set +# CONFIG_DS4424 is not set +# CONFIG_M62332 is not set +# CONFIG_MAX517 is not set +# CONFIG_MAX5821 is not set +# CONFIG_MCP4725 is not set +# CONFIG_MCP4922 is not set +# CONFIG_TI_DAC082S085 is not set +# CONFIG_TI_DAC5571 is not set +# CONFIG_TI_DAC7311 is not set +# CONFIG_VF610_DAC is not set + +# +# IIO dummy driver +# + +# +# Frequency Synthesizers DDS/PLL +# + +# +# Clock Generator/Distribution +# +# CONFIG_AD9523 is not set + +# +# Phase-Locked Loop (PLL) frequency synthesizers +# +# CONFIG_ADF4350 is not set + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADXRS450 is not set +# CONFIG_BMG160 is not set +# CONFIG_MPU3050_I2C is not set +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_ITG3200 is not set + +# +# Health Sensors +# + +# +# Heart Rate Monitors +# +# CONFIG_AFE4403 is not set +# CONFIG_AFE4404 is not set +# CONFIG_MAX30100 is not set +# CONFIG_MAX30102 is not set + +# +# Humidity sensors +# +# CONFIG_AM2315 is not set +# CONFIG_DHT11 is not set +# CONFIG_HDC100X is not set +# CONFIG_HTS221 is not set +# CONFIG_HTU21 is not set +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_BMI160_I2C is not set +# CONFIG_BMI160_SPI is not set +# CONFIG_KMX61 is not set +# CONFIG_INV_MPU6050_I2C is not set +# CONFIG_INV_MPU6050_SPI is not set +# CONFIG_IIO_ST_LSM6DSX is not set + +# +# Light sensors +# +# CONFIG_ADJD_S311 is not set +# CONFIG_AL3320A is not set +# CONFIG_APDS9300 is not set +# CONFIG_APDS9960 is not set +# CONFIG_BH1750 is not set +# CONFIG_BH1780 is not set +# CONFIG_CM32181 is not set +# CONFIG_CM3232 is not set +# CONFIG_CM3323 is not set +# CONFIG_CM3605 is not set +# CONFIG_CM36651 is not set +CONFIG_IIO_CROS_EC_LIGHT_PROX=m +# CONFIG_GP2AP020A00F is not set +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_ISL29125 is not set +# CONFIG_JSA1212 is not set +# CONFIG_RPR0521 is not set +# CONFIG_LTR501 is not set +# CONFIG_LV0104CS is not set +# CONFIG_MAX44000 is not set +# CONFIG_OPT3001 is not set +# CONFIG_PA12203001 is not set +# CONFIG_SI1133 is not set +# CONFIG_SI1145 is not set +# CONFIG_STK3310 is not set +# CONFIG_ST_UVIS25 is not set +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_TSL2583 is not set +# CONFIG_TSL2772 is not set +# CONFIG_TSL4531 is not set +# CONFIG_US5182D is not set +# CONFIG_VCNL4000 is not set +# CONFIG_VCNL4035 is not set +# CONFIG_VEML6070 is not set +# CONFIG_VL6180 is not set +# CONFIG_ZOPT2201 is not set + +# +# Magnetometer sensors +# +# CONFIG_AK8974 is not set +# CONFIG_AK8975 is not set +# CONFIG_AK09911 is not set +# CONFIG_BMC150_MAGN_I2C is not set +# CONFIG_BMC150_MAGN_SPI is not set +# CONFIG_MAG3110 is not set +# CONFIG_MMC35240 is not set +# CONFIG_IIO_ST_MAGN_3AXIS is not set +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +# CONFIG_SENSORS_RM3100_I2C is not set +# CONFIG_SENSORS_RM3100_SPI is not set + +# +# Multiplexers +# +# CONFIG_IIO_MUX is not set + +# +# Inclinometer sensors +# + +# +# Triggers - standalone +# +# CONFIG_IIO_INTERRUPT_TRIGGER is not set +# CONFIG_IIO_SYSFS_TRIGGER is not set + +# +# Digital potentiometers +# +# CONFIG_AD5272 is not set +# CONFIG_DS1803 is not set +# CONFIG_MAX5481 is not set +# CONFIG_MAX5487 is not set +# CONFIG_MCP4018 is not set +# CONFIG_MCP4131 is not set +# CONFIG_MCP4531 is not set +# CONFIG_MCP41010 is not set +# CONFIG_TPL0102 is not set + +# +# Digital potentiostats +# +# CONFIG_LMP91000 is not set + +# +# Pressure sensors +# +# CONFIG_ABP060MG is not set +# CONFIG_BMP280 is not set +CONFIG_IIO_CROS_EC_BARO=m +# CONFIG_HP03 is not set +# CONFIG_MPL115_I2C is not set +# CONFIG_MPL115_SPI is not set +# CONFIG_MPL3115 is not set +# CONFIG_MS5611 is not set +# CONFIG_MS5637 is not set +# CONFIG_IIO_ST_PRESS is not set +# CONFIG_T5403 is not set +# CONFIG_HP206C is not set +# CONFIG_ZPA2326 is not set + +# +# Lightning sensors +# +# CONFIG_AS3935 is not set + +# +# Proximity and distance sensors +# +# CONFIG_ISL29501 is not set +# CONFIG_LIDAR_LITE_V2 is not set +# CONFIG_RFD77402 is not set +# CONFIG_SRF04 is not set +# CONFIG_SX9500 is not set +# CONFIG_SRF08 is not set +# CONFIG_VL53L0X_I2C is not set + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set + +# +# Temperature sensors +# +# CONFIG_MAXIM_THERMOCOUPLE is not set +# CONFIG_MLX90614 is not set +# CONFIG_MLX90632 is not set +# CONFIG_TMP006 is not set +# CONFIG_TMP007 is not set +# CONFIG_TSYS01 is not set +# CONFIG_TSYS02D is not set +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +CONFIG_PWM_CROS_EC=m +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +# CONFIG_PWM_SUN4I is not set + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_PARTITION_PERCPU=y +# CONFIG_IPACK_BUS is not set +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_SUNXI=y +# CONFIG_RESET_TI_SYSCON is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +CONFIG_PHY_XGENE=y +CONFIG_PHY_SUN4I_USB=y +# CONFIG_PHY_SUN9I_USB is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_CADENCE_DP is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_OCELOT_SERDES is not set +CONFIG_PHY_QCOM_USB_HS=y +# CONFIG_PHY_QCOM_USB_HSIC is not set +CONFIG_PHY_SAMSUNG_USB2=y +# CONFIG_PHY_TUSB1210 is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_ARM_CCI_PMU is not set +# CONFIG_ARM_CCN is not set +CONFIG_ARM_PMU=y +# CONFIG_ARM_DSU_PMU is not set +# CONFIG_ARM_SPE_PMU is not set +CONFIG_RAS=y + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_LIBNVDIMM is not set +# CONFIG_DAX is not set +CONFIG_NVMEM=y +# CONFIG_NVMEM_SUNXI_SID is not set + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# CONFIG_FPGA is not set +# CONFIG_FSI is not set +# CONFIG_TEE is not set +CONFIG_PM_OPP=y +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_FS_IOMAP=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_ENCRYPTION is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_ONLINE_SCRUB is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_FS_REF_VERIFY is not set +# CONFIG_NILFS2_FS is not set +CONFIG_F2FS_FS=m +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_POSIX_ACL=y +# CONFIG_F2FS_FS_SECURITY is not set +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FS_ENCRYPTION is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +# CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QUOTA_DEBUG is not set +# CONFIG_QFMT_V1 is not set +# CONFIG_QFMT_V2 is not set +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVERLAY_FS_METACOPY is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_VMCORE=y +# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=y +CONFIG_EFIVAR_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +# CONFIG_SQUASHFS_DECOMP_SINGLE is not set +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_PSTORE=y +CONFIG_PSTORE_DEFLATE_COMPRESS=y +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +# CONFIG_PSTORE_LZ4HC_COMPRESS is not set +# CONFIG_PSTORE_842_COMPRESS is not set +# CONFIG_PSTORE_ZSTD_COMPRESS is not set +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +# CONFIG_PSTORE_RAM is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_SWAP is not set +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_PNFS_FILE_LAYOUT=y +CONFIG_PNFS_BLOCK=m +CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_SECURITY_LABEL=y +CONFIG_ROOT_NFS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_SUNRPC_BACKCHANNEL=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_9P_FS=y +# CONFIG_9P_FS_POSIX_ACL is not set +# CONFIG_9P_FS_SECURITY is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_COMPAT=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_TRUSTED_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +# CONFIG_SECURITY_NETWORK is not set +# CONFIG_SECURITY_PATH is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +# CONFIG_HARDENED_USERCOPY is not set +# CONFIG_FORTIFY_SOURCE is not set +# CONFIG_STATIC_USERMODEHELPER is not set +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +# CONFIG_SECURITY_APPARMOR is not set +# CONFIG_SECURITY_LOADPIN is not set +# CONFIG_SECURITY_YAMA is not set +CONFIG_INTEGRITY=y +# CONFIG_INTEGRITY_SIGNATURE is not set +CONFIG_INTEGRITY_AUDIT=y +# CONFIG_IMA is not set +# CONFIG_EVM is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA=y +CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA=y +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=m +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_RSA=y +# CONFIG_CRYPTO_DH is not set +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_SIMD=y + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_AEGIS128 is not set +# CONFIG_CRYPTO_AEGIS128L is not set +# CONFIG_CRYPTO_AEGIS256 is not set +# CONFIG_CRYPTO_MORUS640 is not set +# CONFIG_CRYPTO_MORUS1280 is not set +CONFIG_CRYPTO_SEQIV=m +CONFIG_CRYPTO_ECHAINIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CFB is not set +CONFIG_CRYPTO_CTR=m +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_ADIANTUM is not set + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_GHASH=m +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +CONFIG_CRYPTO_CHACHA20=m +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +# CONFIG_CRYPTO_DEV_HISI_SEC is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set + +# +# Certificates for signature checking +# +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set + +# +# Library routines +# +CONFIG_RAID6_PQ=m +CONFIG_RAID6_PQ_BENCHMARK=y +CONFIG_BITREVERSE=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_INDIRECT_PIO=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +CONFIG_CRC7=y +CONFIG_LIBCRC32C=m +# CONFIG_CRC8 is not set +CONFIG_XXHASH=y +CONFIG_AUDIT_GENERIC=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_AUDIT_COMPAT_GENERIC=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_COMPRESS=m +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_XARRAY_MULTI=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y +CONFIG_ARCH_HAS_DMA_MMAP_PGPROT=y +CONFIG_SWIOTLB=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_SGL_ALLOC=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_CLZ_TAB=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +CONFIG_MPILIB=y +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_SG_POOL=y +CONFIG_SBITMAP=y +# CONFIG_STRING_SELFTEST is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_PAGE_OWNER is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_DEBUG_KERNEL=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_RODATA_TEST is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_VM is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y +CONFIG_CC_HAS_KASAN_GENERIC=y +# CONFIG_KASAN is not set +CONFIG_KASAN_STACK=1 +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_SOFTLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SCHED_DEBUG is not set +CONFIG_SCHED_INFO=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_DEBUG_TIMEKEEPING is not set +# CONFIG_DEBUG_PREEMPT is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_STACKTRACE is not set +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_HAVE_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PI_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_RCU_PERF_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DMA_API_DEBUG is not set +CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_BITFIELD is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_XARRAY is not set +# CONFIG_TEST_OVERFLOW is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_TEST_IDA is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_KMOD is not set +# CONFIG_TEST_MEMCAT_P is not set +CONFIG_MEMTEST=y +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +CONFIG_STRICT_DEVMEM=y +# CONFIG_IO_STRICT_DEVMEM is not set +# CONFIG_ARM64_PTDUMP_DEBUGFS is not set +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set +# CONFIG_DEBUG_WX is not set +# CONFIG_DEBUG_ALIGN_RODATA is not set +# CONFIG_DEBUG_EFI is not set +# CONFIG_ARM64_RELOC_TEST is not set +# CONFIG_CORESIGHT is not set diff --git a/projects/Allwinner/linux/linux.arm.conf b/projects/Allwinner/linux/linux.arm.conf new file mode 100644 index 0000000000..cdb175ae28 --- /dev/null +++ b/projects/Allwinner/linux/linux.arm.conf @@ -0,0 +1,5282 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 5.0.2 Kernel Configuration +# + +# +# Compiler: armv7ve-libreelec-linux-gnueabi-gcc-8.2.0 (GCC) 8.2.0 +# +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=80200 +CONFIG_CLANG_VERSION=0 +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_BUILD_SALT="" +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +CONFIG_DEFAULT_HOSTNAME="@DISTRONAME@" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_USELIB is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_PSI is not set +CONFIG_CPU_ISOLATION=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_BUILD_BIN2C=y +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_SWAP_ENABLED=y +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +# CONFIG_DEBUG_BLK_CGROUP is not set +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +# CONFIG_CGROUP_RDMA is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_INITRAMFS_FORCE is not set +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_INITRAMFS_COMPRESSION=".gz" +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +# CONFIG_BPF_SYSCALL is not set +# CONFIG_USERFAULTFD is not set +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_MEMCG_SYSFS_ON is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SYSTEM_DATA_VERIFICATION=y +# CONFIG_PROFILING is not set +CONFIG_ARM=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_PGTABLE_LEVELS=2 + +# +# System Type +# +CONFIG_MMU=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Multiple platform selection +# + +# +# CPU Core family selection +# +# CONFIG_ARCH_MULTI_V6 is not set +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MULTI_V6_V7=y +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_ARTPEC is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCM is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_DIGICOLOR is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_KEYSTONE is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_NPCM is not set + +# +# TI OMAP/AM/DM/DRA Family +# +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_ARCH_OMAP4 is not set +# CONFIG_SOC_OMAP5 is not set +# CONFIG_SOC_AM33XX is not set +# CONFIG_SOC_AM43XX is not set +# CONFIG_SOC_DRA7XX is not set +# CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_RDA is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_STI is not set +# CONFIG_ARCH_STM32 is not set +CONFIG_ARCH_SUNXI=y +# CONFIG_MACH_SUN4I is not set +# CONFIG_MACH_SUN5I is not set +# CONFIG_MACH_SUN6I is not set +# CONFIG_MACH_SUN7I is not set +CONFIG_MACH_SUN8I=y +# CONFIG_MACH_SUN9I is not set +CONFIG_ARCH_SUNXI_MC_SMP=y +# CONFIG_ARCH_TANGO is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_WM8850 is not set +# CONFIG_ARCH_ZX is not set +# CONFIG_ARCH_ZYNQ is not set + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_SWP_EMULATE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_SPECTRE=y +# CONFIG_HARDEN_BRANCH_PREDICTOR is not set +CONFIG_KUSER_HELPERS=y +CONFIG_VDSO=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_CACHE_L2X0=y +# CONFIG_CACHE_L2X0_PMU is not set +# CONFIG_PL310_ERRATA_588369 is not set +# CONFIG_PL310_ERRATA_727915 is not set +# CONFIG_PL310_ERRATA_753970 is not set +# CONFIG_PL310_ERRATA_769419 is not set +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_ARM_HEAVY_MB=y +CONFIG_DEBUG_ALIGN_RODATA=y +# CONFIG_ARM_ERRATA_430973 is not set +CONFIG_ARM_ERRATA_643719=y +# CONFIG_ARM_ERRATA_720789 is not set +# CONFIG_ARM_ERRATA_754322 is not set +# CONFIG_ARM_ERRATA_754327 is not set +# CONFIG_ARM_ERRATA_764369 is not set +# CONFIG_ARM_ERRATA_775420 is not set +# CONFIG_ARM_ERRATA_798181 is not set +# CONFIG_ARM_ERRATA_773022 is not set +# CONFIG_ARM_ERRATA_818325_852422 is not set +# CONFIG_ARM_ERRATA_821420 is not set +# CONFIG_ARM_ERRATA_825619 is not set +# CONFIG_ARM_ERRATA_852421 is not set +# CONFIG_ARM_ERRATA_852423 is not set + +# +# Bus support +# + +# +# Kernel Features +# +CONFIG_HAVE_SMP=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_ARM_CPU_TOPOLOGY=y +# CONFIG_SCHED_MC is not set +# CONFIG_SCHED_SMT is not set +CONFIG_HAVE_ARM_ARCH_TIMER=y +# CONFIG_MCPM is not set +# CONFIG_BIG_LITTLE is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=8 +CONFIG_HOTPLUG_CPU=y +CONFIG_ARM_PSCI=y +CONFIG_ARCH_NR_GPIO=416 +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_ARM_PATCH_IDIV=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y +CONFIG_CPU_SW_DOMAIN_PAN=y +CONFIG_HW_PERF_EVENTS=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +# CONFIG_ARM_MODULE_PLTS is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +CONFIG_SECCOMP=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +# CONFIG_XEN is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +# CONFIG_ARM_APPENDED_DTB is not set +CONFIG_CMDLINE="root=/dev/ram0 rdinit=/init" +# CONFIG_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_CMDLINE_EXTEND=y +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y +# CONFIG_EFI is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_STAT is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y + +# +# CPU frequency scaling drivers +# +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set +# CONFIG_QORIQ_CPUFREQ is not set + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y + +# +# ARM CPU Idle Drivers +# +# CONFIG_ARM_CPUIDLE is not set +# CONFIG_ARM_HIGHBANK_CPUIDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y +# CONFIG_KERNEL_MODE_NEON is not set + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +# CONFIG_HIBERNATION is not set +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_APM_EMULATION is not set +CONFIG_PM_CLK=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_CPU_PM=y +# CONFIG_ENERGY_MODEL is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y + +# +# Firmware Drivers +# +CONFIG_ARM_PSCI_FW=y +# CONFIG_ARM_PSCI_CHECKER is not set +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_INTEL_STRATIX10_SERVICE is not set +CONFIG_HAVE_ARM_SMCCC=y +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# Tegra firmware driver +# +CONFIG_ARM_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM=y +CONFIG_CRYPTO_SHA256_ARM=y +CONFIG_CRYPTO_SHA512_ARM=y +CONFIG_CRYPTO_AES_ARM=y +# CONFIG_VIRTUALIZATION is not set + +# +# General architecture-dependent options +# +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP_FILTER=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_CC_HAS_STACKPROTECTOR_NONE=y +# CONFIG_STACKPROTECTOR is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS=8 +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_PHYS_TO_DMA=y +CONFIG_REFCOUNT_FULL=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_PLUGIN_HOSTCC="g++" +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_ZONED is not set +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +# CONFIG_BLK_CMDLINE_PARSER is not set +# CONFIG_BLK_WBT is not set +CONFIG_BLK_CGROUP_IOLATENCY=y +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set +CONFIG_BLK_PM=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_IOSCHED_BFQ is not set +CONFIG_ASN1=y +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_ELF_FDPIC is not set +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Memory Management options +# +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +CONFIG_BOUNCE=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_CLEANCACHE=y +CONFIG_FRONTSWAP=y +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_AREAS=7 +# CONFIG_ZSWAP is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FRAME_VECTOR=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_BENCHMARK is not set +CONFIG_NET=y +CONFIG_NET_INGRESS=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +# CONFIG_TLS is not set +CONFIG_XFRM=y +CONFIG_XFRM_ALGO=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_INTERFACE is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=m +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE=y +# CONFIG_IP_PIMSM_V1 is not set +# CONFIG_IP_PIMSM_V2 is not set +# CONFIG_SYN_COOKIES is not set +CONFIG_NET_UDP_TUNNEL=m +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +CONFIG_INET_ESP=m +# CONFIG_INET_ESP_OFFLOAD is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_ILA is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=m + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_FAMILY_BRIDGE=y +# CONFIG_NETFILTER_NETLINK_ACCT is not set +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NETFILTER_NETLINK_OSF is not set +CONFIG_NF_CONNTRACK=m +# CONFIG_NF_LOG_NETDEV is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_ZONES is not set +CONFIG_NF_CONNTRACK_PROCFS=y +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +# CONFIG_NF_CONNTRACK_LABELS is not set +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=m +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_NEEDED=y +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_REDIRECT=y +# CONFIG_NF_TABLES is not set +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +# CONFIG_NETFILTER_XT_MARK is not set +# CONFIG_NETFILTER_XT_CONNMARK is not set + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_LED is not set +# CONFIG_NETFILTER_XT_TARGET_LOG is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +CONFIG_NETFILTER_XT_NAT=m +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +# CONFIG_NETFILTER_XT_MATCH_BPF is not set +# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ECN is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +CONFIG_NETFILTER_XT_MATCH_IPVS=m +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set +# CONFIG_NETFILTER_XT_MATCH_STATE is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_IP_SET is not set +CONFIG_IP_VS=m +# CONFIG_IP_VS_IPV6 is not set +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +# CONFIG_IP_VS_PROTO_ESP is not set +# CONFIG_IP_VS_PROTO_AH is not set +# CONFIG_IP_VS_PROTO_SCTP is not set + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +# CONFIG_IP_VS_WRR is not set +# CONFIG_IP_VS_LC is not set +# CONFIG_IP_VS_WLC is not set +# CONFIG_IP_VS_FO is not set +# CONFIG_IP_VS_OVF is not set +# CONFIG_IP_VS_LBLC is not set +# CONFIG_IP_VS_LBLCR is not set +# CONFIG_IP_VS_DH is not set +# CONFIG_IP_VS_SH is not set +# CONFIG_IP_VS_MH is not set +# CONFIG_IP_VS_SED is not set +# CONFIG_IP_VS_NQ is not set + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS MH scheduler +# +CONFIG_IP_VS_MH_TAB_INDEX=12 + +# +# IPVS application helper +# +# CONFIG_IP_VS_FTP is not set +CONFIG_IP_VS_NFCT=y + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +# CONFIG_NF_SOCKET_IPV4 is not set +# CONFIG_NF_TPROXY_IPV4 is not set +# CONFIG_NF_DUP_IPV4 is not set +# CONFIG_NF_LOG_ARP is not set +# CONFIG_NF_LOG_IPV4 is not set +# CONFIG_NF_REJECT_IPV4 is not set +CONFIG_NF_NAT_IPV4=m +CONFIG_NF_NAT_MASQUERADE_IPV4=y +CONFIG_IP_NF_IPTABLES=m +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_TTL is not set +CONFIG_IP_NF_FILTER=m +# CONFIG_IP_NF_TARGET_REJECT is not set +# CONFIG_IP_NF_TARGET_SYNPROXY is not set +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +# CONFIG_IP_NF_TARGET_NETMAP is not set +CONFIG_IP_NF_TARGET_REDIRECT=m +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_NF_SOCKET_IPV6 is not set +# CONFIG_NF_TPROXY_IPV6 is not set +# CONFIG_NF_DUP_IPV6 is not set +# CONFIG_NF_REJECT_IPV6 is not set +# CONFIG_NF_LOG_IPV6 is not set +# CONFIG_NF_NAT_IPV6 is not set +# CONFIG_IP6_NF_IPTABLES is not set +CONFIG_NF_DEFRAG_IPV6=m +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_BPFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_BRIDGE_VLAN_FILTERING is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_CBS is not set +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_TAPRIO is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_SKBPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_CODEL is not set +# CONFIG_NET_SCH_FQ_CODEL is not set +# CONFIG_NET_SCH_CAKE is not set +# CONFIG_NET_SCH_FQ is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_PIE is not set +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +CONFIG_NET_CLS_CGROUP=y +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOWER is not set +# CONFIG_NET_CLS_MATCHALL is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_NET_NSH is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +CONFIG_NET_L3_MASTER_DEV=y +# CONFIG_NET_NCSI is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +CONFIG_CAN=y +CONFIG_CAN_RAW=y +CONFIG_CAN_BCM=y +CONFIG_CAN_GW=y + +# +# CAN Device Drivers +# +# CONFIG_CAN_VCAN is not set +# CONFIG_CAN_VXCAN is not set +# CONFIG_CAN_SLCAN is not set +CONFIG_CAN_DEV=y +CONFIG_CAN_CALC_BITTIMING=y +# CONFIG_CAN_FLEXCAN is not set +# CONFIG_CAN_GRCAN is not set +# CONFIG_CAN_TI_HECC is not set +# CONFIG_CAN_C_CAN is not set +# CONFIG_CAN_CC770 is not set +# CONFIG_CAN_IFI_CANFD is not set +# CONFIG_CAN_M_CAN is not set +# CONFIG_CAN_RCAR is not set +# CONFIG_CAN_RCAR_CANFD is not set +# CONFIG_CAN_SJA1000 is not set +# CONFIG_CAN_SOFTING is not set + +# +# CAN SPI interfaces +# +# CONFIG_CAN_HI311X is not set +# CONFIG_CAN_MCP251X is not set + +# +# CAN USB interfaces +# +# CONFIG_CAN_8DEV_USB is not set +# CONFIG_CAN_EMS_USB is not set +# CONFIG_CAN_ESD_USB2 is not set +# CONFIG_CAN_GS_USB is not set +# CONFIG_CAN_KVASER_USB is not set +# CONFIG_CAN_MCBA_USB is not set +# CONFIG_CAN_PEAK_USB is not set +# CONFIG_CAN_UCAN is not set +# CONFIG_CAN_DEBUG_DEVICES is not set +CONFIG_BT=m +CONFIG_BT_BREDR=y +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HS=y +CONFIG_BT_LE=y +CONFIG_BT_LEDS=y +# CONFIG_BT_SELFTEST is not set +# CONFIG_BT_DEBUGFS is not set + +# +# Bluetooth device drivers +# +CONFIG_BT_INTEL=m +CONFIG_BT_BCM=m +CONFIG_BT_RTL=m +CONFIG_BT_HCIBTUSB=m +# CONFIG_BT_HCIBTUSB_AUTOSUSPEND is not set +CONFIG_BT_HCIBTUSB_BCM=y +CONFIG_BT_HCIBTUSB_RTL=y +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +# CONFIG_NET_IFE is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y +# CONFIG_FAILOVER is not set +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_HAVE_PCI=y +# CONFIG_PCI is not set +# CONFIG_PCCARD is not set + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER is not set +CONFIG_WANT_DEV_COREDUMP=y +CONFIG_ALLOW_DEV_COREDUMP=y +CONFIG_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_IRQ=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_DMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +CONFIG_GENERIC_ARCH_TOPOLOGY=y + +# +# Bus devices +# +CONFIG_ARM_CCI=y +CONFIG_ARM_CCI400_COMMON=y +CONFIG_ARM_CCI400_PORT_CTRL=y +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_SIMPLE_PM_BUS is not set +CONFIG_SUN50I_DE2_BUS=y +CONFIG_SUNXI_RSB=y +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_CONNECTOR is not set +# CONFIG_GNSS is not set +# CONFIG_MTD is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_RESOLVE=y +CONFIG_OF_OVERLAY=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +CONFIG_BLK_DEV_NBD=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_RBD is not set + +# +# NVME Support +# +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_PVPANIC is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +CONFIG_EEPROM_93CX6=m +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC & related support +# + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set +# CONFIG_MISC_RTSX_USB is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +# CONFIG_SATA_AHCI_PLATFORM is not set +# CONFIG_AHCI_CEVA is not set +CONFIG_AHCI_SUNXI=y +# CONFIG_AHCI_QORIQ is not set +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +# CONFIG_SATA_DWC is not set + +# +# PATA SFF controllers with BMDMA +# + +# +# PIO-only SFF controllers +# +# CONFIG_PATA_PLATFORM is not set + +# +# Generic fallback / legacy drivers +# +CONFIG_MD=y +# CONFIG_BLK_DEV_MD is not set +# CONFIG_BCACHE is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_BUFIO=m +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_PERSISTENT_DATA=m +# CONFIG_DM_UNSTRIPED is not set +# CONFIG_DM_CRYPT is not set +# CONFIG_DM_SNAPSHOT is not set +CONFIG_DM_THIN_PROVISIONING=m +# CONFIG_DM_CACHE is not set +# CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_VERITY is not set +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_DM_INTEGRITY is not set +# CONFIG_TARGET_CORE is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +CONFIG_DUMMY=m +# CONFIG_EQUALIZER is not set +# CONFIG_NET_TEAM is not set +CONFIG_MACVLAN=m +# CONFIG_MACVTAP is not set +CONFIG_IPVLAN=m +# CONFIG_IPVTAP is not set +CONFIG_VXLAN=m +# CONFIG_GENEVE is not set +# CONFIG_GTP is not set +# CONFIG_MACSEC is not set +CONFIG_NETCONSOLE=y +# CONFIG_NETCONSOLE_DYNAMIC is not set +CONFIG_NETPOLL=y +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_TUN=y +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=m +# CONFIG_NLMON is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_ETHERNET=y +CONFIG_NET_VENDOR_ALACRITECH=y +CONFIG_NET_VENDOR_ALLWINNER=y +CONFIG_SUN4I_EMAC=y +# CONFIG_ALTERA_TSE is not set +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_NET_VENDOR_AQUANTIA=y +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +CONFIG_NET_VENDOR_CORTINA=y +# CONFIG_GEMINI_ETHERNET is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +CONFIG_NET_VENDOR_EZCHIP=y +# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set +# CONFIG_NET_VENDOR_FARADAY is not set +CONFIG_NET_VENDOR_HISILICON=y +# CONFIG_HIX5HD2_GMAC is not set +# CONFIG_HISI_FEMAC is not set +# CONFIG_HIP04_ETH is not set +# CONFIG_HNS is not set +# CONFIG_HNS_DSAF is not set +# CONFIG_HNS_ENET is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROSEMI=y +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_NET_VENDOR_NETRONOME=y +CONFIG_NET_VENDOR_NI=y +# CONFIG_NI_XGE_MANAGEMENT_ENET is not set +# CONFIG_ETHOC is not set +CONFIG_NET_VENDOR_QUALCOMM=y +# CONFIG_QCA7000_SPI is not set +# CONFIG_QCOM_EMAC is not set +# CONFIG_RMNET is not set +CONFIG_NET_VENDOR_RENESAS=y +CONFIG_NET_VENDOR_ROCKER=y +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_NET_VENDOR_SOLARFLARE=y +# CONFIG_NET_VENDOR_SMSC is not set +CONFIG_NET_VENDOR_SOCIONEXT=y +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +# CONFIG_DWMAC_DWC_QOS_ETH is not set +CONFIG_DWMAC_GENERIC=y +CONFIG_DWMAC_SUNXI=y +CONFIG_DWMAC_SUN8I=y +CONFIG_NET_VENDOR_SYNOPSYS=y +# CONFIG_DWC_XLGMAC is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_MDIO_BUS_MUX=y +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_MSCC_MIIM is not set +CONFIG_MDIO_SUN4I=y +CONFIG_PHYLIB=y +CONFIG_SWPHY=y +# CONFIG_LED_TRIGGER_PHY is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_ASIX_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_RENESAS_PHY is not set +# CONFIG_ROCKCHIP_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_MPPE=m +# CONFIG_PPP_MULTILINK is not set +CONFIG_PPPOE=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +# CONFIG_SLIP is not set +CONFIG_SLHC=m +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +CONFIG_USB_RTL8152=y +# CONFIG_USB_LAN78XX is not set +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +# CONFIG_USB_NET_CDC_EEM is not set +CONFIG_USB_NET_CDC_NCM=m +# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set +# CONFIG_USB_NET_CDC_MBIM is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SR9700 is not set +# CONFIG_USB_NET_SR9800 is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_GL620A is not set +CONFIG_USB_NET_NET1080=m +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_MCS7830 is not set +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CDC_SUBSET=m +# CONFIG_USB_ALI_M5632 is not set +# CONFIG_USB_AN2720 is not set +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +# CONFIG_USB_EPSON2888 is not set +# CONFIG_USB_KC2190 is not set +CONFIG_USB_NET_ZAURUS=m +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_KALMIA is not set +# CONFIG_USB_NET_QMI_WWAN is not set +# CONFIG_USB_NET_INT51X1 is not set +CONFIG_USB_IPHETH=m +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_USB_VL600 is not set +# CONFIG_USB_NET_CH9200 is not set +# CONFIG_USB_NET_AQC111 is not set +CONFIG_WLAN=y +# CONFIG_WIRELESS_WDS is not set +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_ATH_COMMON=m +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K_BTCOEX_SUPPORT=y +CONFIG_ATH9K=m +CONFIG_ATH9K_AHB=y +# CONFIG_ATH9K_DEBUGFS is not set +# CONFIG_ATH9K_DYNACK is not set +# CONFIG_ATH9K_WOW is not set +# CONFIG_ATH9K_CHANNEL_CONTEXT is not set +CONFIG_ATH9K_PCOEM=y +CONFIG_ATH9K_HTC=m +# CONFIG_ATH9K_HTC_DEBUGFS is not set +CONFIG_CARL9170=m +CONFIG_CARL9170_LEDS=y +CONFIG_CARL9170_WPC=y +CONFIG_ATH6KL=m +# CONFIG_ATH6KL_SDIO is not set +CONFIG_ATH6KL_USB=m +# CONFIG_ATH6KL_DEBUG is not set +CONFIG_AR5523=m +CONFIG_ATH10K=m +CONFIG_ATH10K_CE=y +# CONFIG_ATH10K_SDIO is not set +# CONFIG_ATH10K_USB is not set +# CONFIG_ATH10K_DEBUG is not set +# CONFIG_ATH10K_DEBUGFS is not set +CONFIG_WCN36XX=m +# CONFIG_WCN36XX_DEBUGFS is not set +CONFIG_WLAN_VENDOR_ATMEL=y +# CONFIG_AT76C50X_USB is not set +CONFIG_WLAN_VENDOR_BROADCOM=y +CONFIG_B43=m +CONFIG_B43_BCMA=y +CONFIG_B43_SSB=y +CONFIG_B43_BUSES_BCMA_AND_SSB=y +# CONFIG_B43_BUSES_BCMA is not set +# CONFIG_B43_BUSES_SSB is not set +# CONFIG_B43_SDIO is not set +CONFIG_B43_BCMA_PIO=y +CONFIG_B43_PIO=y +CONFIG_B43_PHY_G=y +CONFIG_B43_PHY_N=y +CONFIG_B43_PHY_LP=y +CONFIG_B43_PHY_HT=y +CONFIG_B43_LEDS=y +# CONFIG_B43_DEBUG is not set +# CONFIG_B43LEGACY is not set +CONFIG_BRCMUTIL=m +# CONFIG_BRCMSMAC is not set +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_SDIO=y +CONFIG_BRCMFMAC_USB=y +# CONFIG_BRCM_TRACING is not set +# CONFIG_BRCMDBG is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +# CONFIG_HOSTAP is not set +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +# CONFIG_P54_SPI is not set +CONFIG_P54_LEDS=y +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_MWIFIEX is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_MT7601U=m +CONFIG_MT76_CORE=m +CONFIG_MT76_LEDS=y +CONFIG_MT76_USB=m +CONFIG_MT76x02_LIB=m +CONFIG_MT76x02_USB=m +CONFIG_MT76x0_COMMON=m +CONFIG_MT76x0U=m +CONFIG_MT76x2_COMMON=m +CONFIG_MT76x2U=m +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RT2800_LIB=m +CONFIG_RT2X00_LIB_USB=m +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_LEDS=y +# CONFIG_RT2X00_DEBUG is not set +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_RTL8187=m +CONFIG_RTL8187_LEDS=y +CONFIG_RTL_CARDS=m +# CONFIG_RTL8192CU is not set +# CONFIG_RTL8XXXU is not set +CONFIG_WLAN_VENDOR_RSI=y +# CONFIG_RSI_91X is not set +CONFIG_WLAN_VENDOR_ST=y +# CONFIG_CW1200 is not set +CONFIG_WLAN_VENDOR_TI=y +# CONFIG_WL1251 is not set +# CONFIG_WL12XX is not set +# CONFIG_WL18XX is not set +# CONFIG_WLCORE is not set +CONFIG_WLAN_VENDOR_ZYDAS=y +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +# CONFIG_ZD1211RW_DEBUG is not set +CONFIG_WLAN_VENDOR_QUANTENNA=y +# CONFIG_MAC80211_HWSIM is not set +CONFIG_USB_NET_RNDIS_WLAN=m +# CONFIG_VIRT_WIFI is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_NETDEVSIM is not set +# CONFIG_NET_FAILOVER is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADC is not set +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +CONFIG_KEYBOARD_SUN4I_LRADC=y +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_DECODER is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_REGULATOR_HAPTIC is not set +CONFIG_INPUT_AXP20X_PEK=y +CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_PWM_VIBRA is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_APBPS2 is not set +# CONFIG_SERIO_OLPC_APSP is not set +# CONFIG_SERIO_SUN4I_PS2 is not set +# CONFIG_SERIO_GPIO_PS2 is not set +# CONFIG_USERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_NR_UARTS=8 +CONFIG_SERIAL_8250_RUNTIME_UARTS=8 +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_ASPEED_VUART is not set +CONFIG_SERIAL_8250_FSL=y +CONFIG_SERIAL_8250_DW=y +# CONFIG_SERIAL_8250_EM is not set +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_OF_PLATFORM=y + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +# CONFIG_I2C_MUX_GPIO is not set +# CONFIG_I2C_MUX_GPMUX is not set +# CONFIG_I2C_MUX_LTC4306 is not set +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +# CONFIG_I2C_MUX_MLXCPLD is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_MV64XXX=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I3C is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y +# CONFIG_SPI_MEM is not set + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +CONFIG_SPI_SUN4I=y +CONFIG_SPI_SUN6I=y +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_SLAVE is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PINCTRL=y +CONFIG_PINMUX=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_AXP209 is not set +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_SX150X is not set +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_SUNXI=y +CONFIG_PINCTRL_SUN4I_A10=y +CONFIG_PINCTRL_SUN8I_A23=y +CONFIG_PINCTRL_SUN8I_A33=y +CONFIG_PINCTRL_SUN8I_A83T=y +CONFIG_PINCTRL_SUN8I_A83T_R=y +CONFIG_PINCTRL_SUN8I_A23_R=y +CONFIG_PINCTRL_SUN8I_H3=y +CONFIG_PINCTRL_SUN8I_H3_R=y +CONFIG_PINCTRL_SUN8I_V3S=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_OF_GPIO=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_CADENCE is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_FTGPIO010 is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_MB86S7X is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPC8XXX is not set +# CONFIG_GPIO_SAMA5D2_PIOBU is not set +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_ZEVIO is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_TPIC2810 is not set + +# +# MFD GPIO expanders +# +# CONFIG_HTC_EGPIO is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_XRA1403 is not set + +# +# USB GPIO expanders +# +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +# CONFIG_POWER_RESET is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_GENERIC_ADC_BATTERY is not set +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_LEGO_EV3 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_CHARGER_SBS is not set +# CONFIG_MANAGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_AXP20X_POWER is not set +# CONFIG_AXP288_FUEL_GAUGE is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_LTC3651 is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_CHARGER_RT9455 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ASPEED is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_FTSTEUTATES is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_IIO_HWMON is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX6621 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_PWM_FAN is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP108 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83773G is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_THERMAL=y +# CONFIG_THERMAL_STATISTICS is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +# CONFIG_THERMAL_WRITABLE_TRIPS is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_BANG_BANG is not set +# CONFIG_THERMAL_GOV_USER_SPACE is not set +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +CONFIG_CLOCK_THERMAL=y +CONFIG_DEVFREQ_THERMAL=y +# CONFIG_THERMAL_EMULATION is not set +# CONFIG_QORIQ_THERMAL is not set +CONFIG_GENERIC_ADC_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_FTWDT010_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +CONFIG_SUNXI_WATCHDOG=y +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_SSB_POSSIBLE=y +CONFIG_SSB=m +CONFIG_SSB_BLOCKIO=y +CONFIG_SSB_SDIOHOST_POSSIBLE=y +# CONFIG_SSB_SDIOHOST is not set +# CONFIG_SSB_DRIVER_GPIO is not set +CONFIG_BCMA_POSSIBLE=y +CONFIG_BCMA=m +CONFIG_BCMA_BLOCKIO=y +# CONFIG_BCMA_HOST_SOC is not set +# CONFIG_BCMA_DRIVER_GMAC_CMN is not set +# CONFIG_BCMA_DRIVER_GPIO is not set +# CONFIG_BCMA_DEBUG is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_ACT8945A is not set +CONFIG_MFD_SUN4I_GPADC=y +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AC100 is not set +CONFIG_MFD_AXP20X=y +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_AXP20X_RSB=y +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8XXX is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SUN6I_PRCM=y +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_88PG86X is not set +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ANATOP is not set +CONFIG_REGULATOR_AXP20X=y +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +# CONFIG_REGULATOR_FAN53555 is not set +CONFIG_REGULATOR_GPIO=y +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_LTC3676 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MCP16502 is not set +# CONFIG_REGULATOR_MT6311 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +# CONFIG_REGULATOR_PWM is not set +CONFIG_REGULATOR_SY8106A=y +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_TPS6524X is not set +# CONFIG_REGULATOR_VCTRL is not set +CONFIG_CEC_CORE=y +CONFIG_CEC_NOTIFIER=y +CONFIG_CEC_PIN=y +CONFIG_RC_CORE=y +CONFIG_RC_MAP=y +CONFIG_LIRC=y +CONFIG_RC_DECODERS=y +CONFIG_IR_NEC_DECODER=y +CONFIG_IR_RC5_DECODER=y +CONFIG_IR_RC6_DECODER=y +CONFIG_IR_JVC_DECODER=y +CONFIG_IR_SONY_DECODER=y +CONFIG_IR_SANYO_DECODER=y +CONFIG_IR_SHARP_DECODER=y +CONFIG_IR_MCE_KBD_DECODER=y +CONFIG_IR_XMP_DECODER=y +CONFIG_IR_IMON_DECODER=y +CONFIG_IR_RCMM_DECODER=y +CONFIG_RC_DEVICES=y +# CONFIG_RC_ATI_REMOTE is not set +# CONFIG_IR_HIX5HD2 is not set +# CONFIG_IR_IMON is not set +# CONFIG_IR_IMON_RAW is not set +# CONFIG_IR_MCEUSB is not set +# CONFIG_IR_REDRAT3 is not set +# CONFIG_IR_SPI is not set +# CONFIG_IR_STREAMZAP is not set +# CONFIG_IR_IGORPLUGUSB is not set +# CONFIG_IR_IGUANA is not set +# CONFIG_IR_TTUSBIR is not set +# CONFIG_RC_LOOPBACK is not set +# CONFIG_IR_GPIO_CIR is not set +# CONFIG_IR_GPIO_TX is not set +# CONFIG_IR_PWM_TX is not set +CONFIG_IR_SUNXI=y +# CONFIG_IR_SERIAL is not set +# CONFIG_IR_SIR is not set +CONFIG_RC_XBOX_DVD=y +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_SDR_SUPPORT is not set +CONFIG_MEDIA_CEC_SUPPORT=y +# CONFIG_MEDIA_CEC_RC is not set +# CONFIG_CEC_PIN_ERROR_INJ is not set +CONFIG_MEDIA_CONTROLLER=y +# CONFIG_MEDIA_CONTROLLER_DVB is not set +CONFIG_MEDIA_CONTROLLER_REQUEST_API=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +CONFIG_VIDEO_V4L2=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_TUNER=m +CONFIG_V4L2_MEM2MEM_DEV=y +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_VMALLOC=m +CONFIG_DVB_CORE=y +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_NET=y +CONFIG_TTPCI_EEPROM=m +CONFIG_DVB_MAX_ADAPTERS=16 +# CONFIG_DVB_DYNAMIC_MINORS is not set +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_ULE_DEBUG is not set + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# +# CONFIG_USB_VIDEO_CLASS is not set +CONFIG_USB_GSPCA=m +# CONFIG_USB_M5602 is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_GL860 is not set +# CONFIG_USB_GSPCA_BENQ is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_CPIA1 is not set +# CONFIG_USB_GSPCA_DTCS033 is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_JEILINJ is not set +# CONFIG_USB_GSPCA_JL2005BCD is not set +# CONFIG_USB_GSPCA_KINECT is not set +# CONFIG_USB_GSPCA_KONICA is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_NW80X is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_OV534_9 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7302 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SE401 is not set +# CONFIG_USB_GSPCA_SN9C2028 is not set +# CONFIG_USB_GSPCA_SN9C20X is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SPCA1528 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_SQ930X is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_STK1135 is not set +# CONFIG_USB_GSPCA_STV0680 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TOPRO is not set +# CONFIG_USB_GSPCA_TOUPTEK is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_VICAM is not set +# CONFIG_USB_GSPCA_XIRLINK_CIT is not set +# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_USB_PWC is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_VIDEO_USBTV is not set + +# +# Analog TV USB devices +# +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_USBVISION=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_STK1160=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_LOADER=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m + +# +# Analog/digital TV USB devices +# +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_V4L2=y +CONFIG_VIDEO_AU0828_RC=y +# CONFIG_VIDEO_CX231XX is not set +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m + +# +# Digital TV USB devices +# +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_DIB3000MC=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_ZD1301=m +CONFIG_SMS_USB_DRV=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set +CONFIG_DVB_AS102=m + +# +# Webcam, TV (analog/digital) USB devices +# +# CONFIG_VIDEO_EM28XX is not set + +# +# USB HDMI CEC adapters +# +# CONFIG_V4L_PLATFORM_DRIVERS is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_V4L_TEST_DRIVERS is not set +# CONFIG_DVB_PLATFORM_DRIVERS is not set +# CONFIG_CEC_PLATFORM_DRIVERS is not set + +# +# Supported MMC/SDIO adapters +# +# CONFIG_SMS_SDIO_DRV is not set +CONFIG_MEDIA_COMMON_OPTIONS=y + +# +# common driver options +# +CONFIG_VIDEO_CX2341X=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_CYPRESS_FIRMWARE=m +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_V4L2=y +CONFIG_VIDEOBUF2_MEMOPS=y +CONFIG_VIDEOBUF2_DMA_CONTIG=y +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_DVB_B2C2_FLEXCOP=m +CONFIG_SMS_SIANO_MDTV=m +CONFIG_SMS_SIANO_RC=y + +# +# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) +# +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y +CONFIG_MEDIA_ATTACH=y +CONFIG_VIDEO_IR_I2C=y + +# +# Audio decoders, processors and mixers +# +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_WM8775=m +CONFIG_VIDEO_SONY_BTF_MPX=m + +# +# RDS decoders +# + +# +# Video decoders +# +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m + +# +# Video and audio decoders +# +CONFIG_VIDEO_CX25840=m + +# +# Video encoders +# + +# +# Camera sensor devices +# +CONFIG_VIDEO_OV7640=m + +# +# Flash devices +# + +# +# Video improvement chips +# + +# +# Audio/Video compression chips +# + +# +# SDR tuner chips +# + +# +# Miscellaneous helper chips +# + +# +# Sensors used on soc_camera driver +# + +# +# Media SPI Adapters +# +# CONFIG_CXD2880_SPI_DRV is not set +CONFIG_MEDIA_TUNER=y +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA827X=y +CONFIG_MEDIA_TUNER_TDA18271=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_XC4000=y +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_R820T=m + +# +# Multistandard (satellite) frontends +# +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_M88DS3103=m + +# +# Multistandard (cable + terrestrial) frontends +# +CONFIG_DVB_DRXK=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24123=m +CONFIG_DVB_MT312=m +CONFIG_DVB_ZL10039=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_TS2020=m +CONFIG_DVB_DS3000=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_CX22702=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_MT352=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_EC100=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_SI2168=m +CONFIG_DVB_AS102_FE=m +CONFIG_DVB_ZD1301_DEMOD=m +CONFIG_DVB_GP8PSK_FE=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_TDA10023=m +CONFIG_DVB_STV0297=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_NXT200X=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m +CONFIG_DVB_S5H1411=m + +# +# ISDB-T (terrestrial) frontends +# +CONFIG_DVB_DIB8000=m + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +CONFIG_DVB_TC90522=m + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_AF9033=m + +# +# Common Interface (EN50221) controller drivers +# +CONFIG_DVB_SP2=m + +# +# Tools to develop new frontends +# + +# +# Graphics support +# +# CONFIG_IMX_IPUV3_CORE is not set +CONFIG_DRM=y +CONFIG_DRM_MIPI_DSI=y +# CONFIG_DRM_DP_AUX_CHARDEV is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_SELFTEST is not set +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_KMS_FB_HELPER=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +# CONFIG_DRM_DP_CEC is not set +CONFIG_DRM_GEM_CMA_HELPER=y +CONFIG_DRM_KMS_CMA_HELPER=y + +# +# I2C encoder or helper chips +# +# CONFIG_DRM_I2C_CH7006 is not set +# CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I2C_NXP_TDA998X is not set +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# CONFIG_DRM_HDLCD is not set +# CONFIG_DRM_MALI_DISPLAY is not set + +# +# ACP (Audio CoProcessor) Configuration +# + +# +# AMD Library routines +# +# CONFIG_DRM_VGEM is not set +# CONFIG_DRM_VKMS is not set +# CONFIG_DRM_EXYNOS is not set +# CONFIG_DRM_UDL is not set +# CONFIG_DRM_ARMADA is not set +# CONFIG_DRM_RCAR_DW_HDMI is not set +# CONFIG_DRM_RCAR_LVDS is not set +CONFIG_DRM_SUN4I=y +CONFIG_DRM_SUN4I_HDMI=y +# CONFIG_DRM_SUN4I_HDMI_CEC is not set +CONFIG_DRM_SUN4I_BACKEND=y +CONFIG_DRM_SUN6I_DSI=y +CONFIG_DRM_SUN8I_DW_HDMI=y +CONFIG_DRM_SUN8I_DW_HDMI_CEC=y +CONFIG_DRM_SUN8I_MIXER=y +CONFIG_DRM_SUN8I_TCON_TOP=y +# CONFIG_DRM_OMAP is not set +# CONFIG_DRM_TILCDC is not set +# CONFIG_DRM_FSL_DCU is not set +# CONFIG_DRM_STM is not set +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_DUMB_VGA_DAC is not set +# CONFIG_DRM_LVDS_ENCODER is not set +# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +# CONFIG_DRM_NXP_PTN3460 is not set +# CONFIG_DRM_PARADE_PS8622 is not set +# CONFIG_DRM_SIL_SII8620 is not set +# CONFIG_DRM_SII902X is not set +# CONFIG_DRM_SII9234 is not set +# CONFIG_DRM_THINE_THC63LVD1024 is not set +# CONFIG_DRM_TOSHIBA_TC358764 is not set +# CONFIG_DRM_TOSHIBA_TC358767 is not set +# CONFIG_DRM_TI_TFP410 is not set +# CONFIG_DRM_TI_SN65DSI86 is not set +# CONFIG_DRM_I2C_ADV7511 is not set +CONFIG_DRM_DW_HDMI=y +# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set +CONFIG_DRM_DW_HDMI_I2S_AUDIO=y +CONFIG_DRM_DW_HDMI_CEC=y +# CONFIG_DRM_STI is not set +# CONFIG_DRM_ARCPGU is not set +# CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_TINYDRM is not set +# CONFIG_DRM_PL111 is not set +# CONFIG_DRM_TVE200 is not set +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +CONFIG_FB_SIMPLE=y +# CONFIG_FB_SSD1307 is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# CONFIG_LOGO is not set +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_DMAENGINE_PCM=y +CONFIG_SND_HWDEP=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +# CONFIG_SND_OSSEMUL is not set +CONFIG_SND_PCM_TIMER=y +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_PROC_FS=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# HD-Audio +# +CONFIG_SND_HDA_PREALLOC_SIZE=64 +CONFIG_SND_ARM=y +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +# CONFIG_SND_USB_HIFACE is not set +# CONFIG_SND_BCD2000 is not set +# CONFIG_SND_USB_POD is not set +# CONFIG_SND_USB_PODHD is not set +# CONFIG_SND_USB_TONEPORT is not set +# CONFIG_SND_USB_VARIAX is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_DESIGNWARE_I2S is not set + +# +# SoC Audio for Freescale CPUs +# + +# +# Common SoC Audio options for Freescale CPUs: +# +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# CONFIG_SND_I2S_HI6210_I2S is not set +# CONFIG_SND_SOC_IMG is not set + +# +# STMicroelectronics STM32 SOC audio support +# + +# +# Allwinner SoC Audio support +# +CONFIG_SND_SUN4I_CODEC=y +CONFIG_SND_SUN8I_CODEC=y +CONFIG_SND_SUN8I_CODEC_ANALOG=y +CONFIG_SND_SUN4I_I2S=y +CONFIG_SND_SUN4I_SPDIF=y +CONFIG_SND_SUN8I_ADDA_PR_REGMAP=y +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +# CONFIG_ZX_TDM is not set +CONFIG_SND_SOC_I2C_AND_SPI=y + +# +# CODEC drivers +# +# CONFIG_SND_SOC_AC97_CODEC is not set +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_ADAU1761_I2C is not set +# CONFIG_SND_SOC_ADAU1761_SPI is not set +# CONFIG_SND_SOC_ADAU7002 is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4458 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_AK5558 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_BD28623 is not set +# CONFIG_SND_SOC_BT_SCO is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS35L33 is not set +# CONFIG_SND_SOC_CS35L34 is not set +# CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS42L42 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_DMIC is not set +CONFIG_SND_SOC_HDMI_CODEC=y +# CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8316 is not set +# CONFIG_SND_SOC_ES8328_I2C is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_INNO_RK3036 is not set +# CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98504 is not set +# CONFIG_SND_SOC_MAX9867 is not set +# CONFIG_SND_SOC_MAX98927 is not set +# CONFIG_SND_SOC_MAX98373 is not set +# CONFIG_SND_SOC_MAX9860 is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1789_I2C is not set +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_I2C is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RT5616 is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set +# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TAS5720 is not set +# CONFIG_SND_SOC_TAS6424 is not set +# CONFIG_SND_SOC_TDA7419 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set +# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_TSCS42XX is not set +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8524 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8960 is not set +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_ZX_AUD96P22 is not set +# CONFIG_SND_SOC_MAX9759 is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_NAU8540 is not set +# CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8822 is not set +# CONFIG_SND_SOC_NAU8824 is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +CONFIG_SND_SIMPLE_CARD_UTILS=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_SND_SIMPLE_SCU_CARD=y +CONFIG_SND_AUDIO_GRAPH_CARD=y +CONFIG_SND_AUDIO_GRAPH_SCU_CARD=y + +# +# HID support +# +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HIDRAW is not set +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +# CONFIG_HID_ACCUTOUCH is not set +# CONFIG_HID_ACRUX is not set +CONFIG_HID_APPLE=y +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_ASUS is not set +# CONFIG_HID_AUREAL is not set +CONFIG_HID_BELKIN=y +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_BIGBEN_FF is not set +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +# CONFIG_HID_CORSAIR is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_CMEDIA is not set +CONFIG_HID_CYPRESS=y +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELAN is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +CONFIG_HID_EZKEY=y +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_GT683R is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set +# CONFIG_HID_TWINHAN is not set +CONFIG_HID_KENSINGTON=y +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LED is not set +# CONFIG_HID_LENOVO is not set +CONFIG_HID_LOGITECH=y +# CONFIG_HID_LOGITECH_HIDPP is not set +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGIG940_FF is not set +# CONFIG_LOGIWHEELS_FF is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_REDRAGON is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTI is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +CONFIG_HID_OUYA=y +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_RETRODE is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_ALPS is not set + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +CONFIG_USB_MON=m +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_BCMA is not set +# CONFIG_USB_HCD_SSB is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +CONFIG_USB_UAS=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +CONFIG_USB_MUSB_HDRC=y +# CONFIG_USB_MUSB_HOST is not set +# CONFIG_USB_MUSB_GADGET is not set +CONFIG_USB_MUSB_DUAL_ROLE=y + +# +# Platform Glue Layer +# +CONFIG_USB_MUSB_SUNXI=y + +# +# MUSB DMA mode +# +# CONFIG_MUSB_PIO_ONLY is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=m +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_SIMPLE is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_F8153X is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_METRO is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MXUPORT is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_XSENS_MT is not set +# CONFIG_USB_SERIAL_WISHBONE is not set +# CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_QT2 is not set +# CONFIG_USB_SERIAL_UPD78F0730 is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +CONFIG_USB_PHY=y +CONFIG_NOP_USB_XCEIV=y +# CONFIG_AM335X_PHY_USB is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 + +# +# USB Peripheral Controller +# +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_GR_UDC is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_SNP_UDC_PLAT is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_BDC_UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_DUMMY_HCD is not set +# CONFIG_USB_CONFIGFS is not set +# CONFIG_TYPEC is not set +# CONFIG_USB_ROLE_SWITCH is not set +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +CONFIG_PWRSEQ_EMMC=y +# CONFIG_PWRSEQ_SD8787 is not set +CONFIG_PWRSEQ_SIMPLE=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_SUNXI=y +# CONFIG_MMC_CQHCI is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set + +# +# LED drivers +# +# CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LM3692X is not set +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP3952 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_IS31FL319X is not set +# CONFIG_LEDS_IS31FL32XX is not set + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +# CONFIG_LEDS_BLINKM is not set +# CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_MLXREG is not set +# CONFIG_LEDS_USER is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +# CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +# CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +# CONFIG_RTC_INTF_SYSFS is not set +# CONFIG_RTC_INTF_PROC is not set +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12026 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV8803 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_SUN6I=y +# CONFIG_RTC_DRV_FTRTC010 is not set +# CONFIG_RTC_DRV_SNVS is not set +# CONFIG_RTC_DRV_R7301 is not set + +# +# HID Sensor RTC drivers +# +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DMA_OF=y +# CONFIG_ALTERA_MSGDMA is not set +CONFIG_DMA_SUN6I=y +# CONFIG_DW_AXI_DMAC is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set +# CONFIG_DW_DMAC is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +# CONFIG_SW_SYNC is not set +# CONFIG_UDMABUF is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_VIRTIO_MENU is not set + +# +# Microsoft Hyper-V guest support +# +CONFIG_STAGING=y +# CONFIG_PRISM2_USB is not set +# CONFIG_COMEDI is not set +# CONFIG_RTLLIB is not set +# CONFIG_RTL8723BS is not set +# CONFIG_R8712U is not set +# CONFIG_R8188EU is not set +# CONFIG_VT6656 is not set + +# +# IIO staging drivers +# + +# +# Accelerometers +# +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16240 is not set + +# +# Analog to digital converters +# +# CONFIG_AD7606 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7280 is not set + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# CONFIG_AD7152 is not set +# CONFIG_AD7746 is not set + +# +# Direct Digital Synthesis +# +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set + +# +# Active energy metering IC +# +# CONFIG_ADE7854 is not set + +# +# Resolver to digital converters +# +# CONFIG_AD2S1210 is not set + +# +# Speakup console speech +# +# CONFIG_SPEAKUP is not set +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_SUNXI=y +CONFIG_VIDEO_SUNXI_CEDRUS=y + +# +# Android +# +# CONFIG_STAGING_BOARD is not set +# CONFIG_LTE_GDM724X is not set +# CONFIG_GS_FPGABOOT is not set +# CONFIG_UNISYSSPAR is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +# CONFIG_FB_TFT is not set +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +# CONFIG_MOST is not set +# CONFIG_KS7010 is not set +# CONFIG_GREYBUS is not set +# CONFIG_PI433 is not set +# CONFIG_MTK_MMC is not set + +# +# Gasket devices +# +# CONFIG_XIL_AXIS_FIFO is not set +# CONFIG_EROFS_FS is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_CLK_HSDK is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_VC5 is not set +CONFIG_SUNXI_CCU=y +CONFIG_SUN8I_A23_CCU=y +CONFIG_SUN8I_A33_CCU=y +CONFIG_SUN8I_A83T_CCU=y +CONFIG_SUN8I_H3_CCU=y +CONFIG_SUN8I_V3S_CCU=y +CONFIG_SUN8I_DE2_CCU=y +# CONFIG_SUN8I_R40_CCU is not set +CONFIG_SUN8I_R_CCU=y +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_CLKSRC_MMIO=y +CONFIG_SUN4I_TIMER=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set + +# +# Rpmsg drivers +# +# CONFIG_RPMSG_VIRTIO is not set +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set + +# +# NXP/Freescale QorIQ SoC drivers +# + +# +# i.MX SoC drivers +# + +# +# Qualcomm SoC drivers +# +CONFIG_SUNXI_SRAM=y +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# CONFIG_XILINX_VCU is not set +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_DEVFREQ_GOV_PASSIVE=y + +# +# DEVFREQ Drivers +# +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_EXTCON=y + +# +# Extcon Device Drivers +# +# CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_EXTCON_GPIO is not set +# CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +# CONFIG_EXTCON_USB_GPIO is not set +# CONFIG_MEMORY is not set +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +# CONFIG_IIO_BUFFER_CB is not set +# CONFIG_IIO_BUFFER_HW_CONSUMER is not set +# CONFIG_IIO_KFIFO_BUF is not set +CONFIG_IIO_CONFIGFS=y +# CONFIG_IIO_TRIGGER is not set +# CONFIG_IIO_SW_DEVICE is not set +CONFIG_IIO_SW_TRIGGER=y + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADXL345_I2C is not set +# CONFIG_ADXL345_SPI is not set +# CONFIG_ADXL372_SPI is not set +# CONFIG_ADXL372_I2C is not set +# CONFIG_BMA180 is not set +# CONFIG_BMA220 is not set +# CONFIG_BMC150_ACCEL is not set +# CONFIG_DA280 is not set +# CONFIG_DA311 is not set +# CONFIG_DMARD06 is not set +# CONFIG_DMARD09 is not set +# CONFIG_DMARD10 is not set +# CONFIG_IIO_CROS_EC_ACCEL_LEGACY is not set +# CONFIG_IIO_ST_ACCEL_3AXIS is not set +# CONFIG_KXSD9 is not set +# CONFIG_KXCJK1013 is not set +# CONFIG_MC3230 is not set +# CONFIG_MMA7455_I2C is not set +# CONFIG_MMA7455_SPI is not set +# CONFIG_MMA7660 is not set +# CONFIG_MMA8452 is not set +# CONFIG_MMA9551 is not set +# CONFIG_MMA9553 is not set +# CONFIG_MXC4005 is not set +# CONFIG_MXC6255 is not set +# CONFIG_SCA3000 is not set +# CONFIG_STK8312 is not set +# CONFIG_STK8BA50 is not set + +# +# Analog to digital converters +# +# CONFIG_AD7124 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7291 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7766 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD7949 is not set +# CONFIG_AD799X is not set +# CONFIG_AXP20X_ADC is not set +# CONFIG_AXP288_ADC is not set +# CONFIG_CC10001_ADC is not set +# CONFIG_ENVELOPE_DETECTOR is not set +# CONFIG_HI8435 is not set +# CONFIG_HX711 is not set +# CONFIG_INA2XX_ADC is not set +# CONFIG_LTC2471 is not set +# CONFIG_LTC2485 is not set +# CONFIG_LTC2497 is not set +# CONFIG_MAX1027 is not set +# CONFIG_MAX11100 is not set +# CONFIG_MAX1118 is not set +# CONFIG_MAX1363 is not set +# CONFIG_MAX9611 is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +# CONFIG_MCP3911 is not set +# CONFIG_NAU7802 is not set +# CONFIG_SD_ADC_MODULATOR is not set +CONFIG_SUN4I_GPADC=y +# CONFIG_TI_ADC081C is not set +# CONFIG_TI_ADC0832 is not set +# CONFIG_TI_ADC084S021 is not set +# CONFIG_TI_ADC12138 is not set +# CONFIG_TI_ADC108S102 is not set +# CONFIG_TI_ADC128S052 is not set +# CONFIG_TI_ADC161S626 is not set +# CONFIG_TI_ADS1015 is not set +# CONFIG_TI_ADS7950 is not set +# CONFIG_TI_ADS8688 is not set +# CONFIG_TI_TLC4541 is not set +# CONFIG_VF610_ADC is not set + +# +# Analog Front Ends +# +# CONFIG_IIO_RESCALE is not set + +# +# Amplifiers +# +# CONFIG_AD8366 is not set + +# +# Chemical Sensors +# +# CONFIG_ATLAS_PH_SENSOR is not set +# CONFIG_BME680 is not set +# CONFIG_CCS811 is not set +# CONFIG_IAQCORE is not set +# CONFIG_VZ89X is not set + +# +# Hid Sensor IIO Common +# + +# +# SSP Sensor Common +# +# CONFIG_IIO_SSP_SENSORHUB is not set + +# +# Counters +# + +# +# Digital to analog converters +# +# CONFIG_AD5064 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5592R is not set +# CONFIG_AD5593R is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_LTC1660 is not set +# CONFIG_LTC2632 is not set +# CONFIG_AD5686_SPI is not set +# CONFIG_AD5696_I2C is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5758 is not set +# CONFIG_AD5761 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5791 is not set +# CONFIG_AD7303 is not set +# CONFIG_AD8801 is not set +# CONFIG_DPOT_DAC is not set +# CONFIG_DS4424 is not set +# CONFIG_M62332 is not set +# CONFIG_MAX517 is not set +# CONFIG_MAX5821 is not set +# CONFIG_MCP4725 is not set +# CONFIG_MCP4922 is not set +# CONFIG_TI_DAC082S085 is not set +# CONFIG_TI_DAC5571 is not set +# CONFIG_TI_DAC7311 is not set +# CONFIG_VF610_DAC is not set + +# +# IIO dummy driver +# + +# +# Frequency Synthesizers DDS/PLL +# + +# +# Clock Generator/Distribution +# +# CONFIG_AD9523 is not set + +# +# Phase-Locked Loop (PLL) frequency synthesizers +# +# CONFIG_ADF4350 is not set + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADXRS450 is not set +# CONFIG_BMG160 is not set +# CONFIG_MPU3050_I2C is not set +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_ITG3200 is not set + +# +# Health Sensors +# + +# +# Heart Rate Monitors +# +# CONFIG_AFE4403 is not set +# CONFIG_AFE4404 is not set +# CONFIG_MAX30100 is not set +# CONFIG_MAX30102 is not set + +# +# Humidity sensors +# +# CONFIG_AM2315 is not set +# CONFIG_DHT11 is not set +# CONFIG_HDC100X is not set +# CONFIG_HTS221 is not set +# CONFIG_HTU21 is not set +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_BMI160_I2C is not set +# CONFIG_BMI160_SPI is not set +# CONFIG_KMX61 is not set +# CONFIG_INV_MPU6050_I2C is not set +# CONFIG_INV_MPU6050_SPI is not set +# CONFIG_IIO_ST_LSM6DSX is not set + +# +# Light sensors +# +# CONFIG_ADJD_S311 is not set +# CONFIG_AL3320A is not set +# CONFIG_APDS9300 is not set +# CONFIG_APDS9960 is not set +# CONFIG_BH1750 is not set +# CONFIG_BH1780 is not set +# CONFIG_CM32181 is not set +# CONFIG_CM3232 is not set +# CONFIG_CM3323 is not set +# CONFIG_CM3605 is not set +# CONFIG_CM36651 is not set +# CONFIG_GP2AP020A00F is not set +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_ISL29125 is not set +# CONFIG_JSA1212 is not set +# CONFIG_RPR0521 is not set +# CONFIG_LTR501 is not set +# CONFIG_LV0104CS is not set +# CONFIG_MAX44000 is not set +# CONFIG_OPT3001 is not set +# CONFIG_PA12203001 is not set +# CONFIG_SI1133 is not set +# CONFIG_SI1145 is not set +# CONFIG_STK3310 is not set +# CONFIG_ST_UVIS25 is not set +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_TSL2583 is not set +# CONFIG_TSL2772 is not set +# CONFIG_TSL4531 is not set +# CONFIG_US5182D is not set +# CONFIG_VCNL4000 is not set +# CONFIG_VCNL4035 is not set +# CONFIG_VEML6070 is not set +# CONFIG_VL6180 is not set +# CONFIG_ZOPT2201 is not set + +# +# Magnetometer sensors +# +# CONFIG_AK8974 is not set +# CONFIG_AK8975 is not set +# CONFIG_AK09911 is not set +# CONFIG_BMC150_MAGN_I2C is not set +# CONFIG_BMC150_MAGN_SPI is not set +# CONFIG_MAG3110 is not set +# CONFIG_MMC35240 is not set +# CONFIG_IIO_ST_MAGN_3AXIS is not set +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +# CONFIG_SENSORS_RM3100_I2C is not set +# CONFIG_SENSORS_RM3100_SPI is not set + +# +# Multiplexers +# +# CONFIG_IIO_MUX is not set + +# +# Inclinometer sensors +# + +# +# Digital potentiometers +# +# CONFIG_AD5272 is not set +# CONFIG_DS1803 is not set +# CONFIG_MAX5481 is not set +# CONFIG_MAX5487 is not set +# CONFIG_MCP4018 is not set +# CONFIG_MCP4131 is not set +# CONFIG_MCP4531 is not set +# CONFIG_MCP41010 is not set +# CONFIG_TPL0102 is not set + +# +# Digital potentiostats +# +# CONFIG_LMP91000 is not set + +# +# Pressure sensors +# +# CONFIG_ABP060MG is not set +# CONFIG_BMP280 is not set +# CONFIG_HP03 is not set +# CONFIG_MPL115_I2C is not set +# CONFIG_MPL115_SPI is not set +# CONFIG_MPL3115 is not set +# CONFIG_MS5611 is not set +# CONFIG_MS5637 is not set +# CONFIG_IIO_ST_PRESS is not set +# CONFIG_T5403 is not set +# CONFIG_HP206C is not set +# CONFIG_ZPA2326 is not set + +# +# Lightning sensors +# +# CONFIG_AS3935 is not set + +# +# Proximity and distance sensors +# +# CONFIG_ISL29501 is not set +# CONFIG_LIDAR_LITE_V2 is not set +# CONFIG_RFD77402 is not set +# CONFIG_SRF04 is not set +# CONFIG_SX9500 is not set +# CONFIG_SRF08 is not set +# CONFIG_VL53L0X_I2C is not set + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set + +# +# Temperature sensors +# +# CONFIG_MAXIM_THERMOCOUPLE is not set +# CONFIG_MLX90614 is not set +# CONFIG_MLX90632 is not set +# CONFIG_TMP006 is not set +# CONFIG_TMP007 is not set +# CONFIG_TSYS01 is not set +# CONFIG_TSYS02D is not set +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +CONFIG_PWM_SUN4I=y + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_MAX_NR=1 +# CONFIG_IPACK_BUS is not set +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_SUNXI=y +# CONFIG_RESET_TI_SYSCON is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_SUN9I_USB=y +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_CADENCE_DP is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_OCELOT_SERDES is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_ARM_CCI_PMU is not set +# CONFIG_ARM_CCN is not set +CONFIG_ARM_PMU=y +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_DAX is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_SUNXI_SID=y + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# CONFIG_FPGA is not set +# CONFIG_FSI is not set +# CONFIG_TEE is not set +CONFIG_PM_OPP=y +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_FS_IOMAP=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_ENCRYPTION is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +CONFIG_JFS_FS=m +# CONFIG_JFS_POSIX_ACL is not set +# CONFIG_JFS_SECURITY is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_ONLINE_SCRUB is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_F2FS_FS=m +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_POSIX_ACL=y +# CONFIG_F2FS_FS_SECURITY is not set +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FS_ENCRYPTION is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_FUSE_FS=m +# CONFIG_CUSE is not set +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVERLAY_FS_METACOPY is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_MEMFD_CREATE=y +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +CONFIG_HFS_FS=y +CONFIG_HFSPLUS_FS=y +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +# CONFIG_SQUASHFS_DECOMP_SINGLE is not set +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_PNFS_FILE_LAYOUT=y +CONFIG_PNFS_BLOCK=m +CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +CONFIG_NFS_V4_1_MIGRATION=y +CONFIG_ROOT_NFS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_SWAP=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +# CONFIG_HARDENED_USERCOPY is not set +# CONFIG_FORTIFY_SOURCE is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=m +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=m +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_RSA=y +# CONFIG_CRYPTO_DH is not set +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_AEGIS128 is not set +# CONFIG_CRYPTO_AEGIS128L is not set +# CONFIG_CRYPTO_AEGIS256 is not set +# CONFIG_CRYPTO_MORUS640 is not set +# CONFIG_CRYPTO_MORUS1280 is not set +CONFIG_CRYPTO_SEQIV=m +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CFB is not set +CONFIG_CRYPTO_CTR=m +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_ADIANTUM is not set + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_HMAC=m +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=m +# CONFIG_CRYPTO_CRCT10DIF is not set +CONFIG_CRYPTO_GHASH=m +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=m +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=m +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=m +CONFIG_CRYPTO_JITTERENTROPY=m +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_SUN4I_SS=y +# CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set + +# +# Certificates for signature checking +# +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=m +# CONFIG_CRC8 is not set +CONFIG_XXHASH=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_DMA_REMAP=y +CONFIG_SGL_ALLOC=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_CLZ_TAB=y +CONFIG_CORDIC=m +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +CONFIG_MPILIB=y +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_SG_POOL=y +CONFIG_SBITMAP=y +# CONFIG_STRING_SELFTEST is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +# CONFIG_DEBUG_INFO is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_PAGE_OWNER is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_DEBUG_KERNEL=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_RODATA_TEST is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_VM is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_KASAN_STACK=1 +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_SOFTLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_STACKTRACE is not set +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PI_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_RCU_PERF_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DMA_API_DEBUG is not set +CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_BITFIELD is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_XARRAY is not set +# CONFIG_TEST_OVERFLOW is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_TEST_IDA is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_KMOD is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_MEMTEST is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_ARM_PTDUMP_DEBUGFS is not set +# CONFIG_DEBUG_WX is not set +# CONFIG_UNWINDER_FRAME_POINTER is not set +CONFIG_UNWINDER_ARM=y +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_LL is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_CORESIGHT is not set diff --git a/projects/Allwinner/options b/projects/Allwinner/options new file mode 100644 index 0000000000..7d319c6027 --- /dev/null +++ b/projects/Allwinner/options @@ -0,0 +1,84 @@ +################################################################################ +# setup system defaults +################################################################################ + + # Bootloader to use (syslinux / u-boot / bcm2835-bootloader) + BOOTLOADER="u-boot" + + # u-boot version to use (default) + UBOOT_VERSION="default" + + # Configuration for u-boot + UBOOT_CONFIG="" + + # Target Configfile for u-boot + UBOOT_CONFIGFILE="" + + # Kernel extra targets to build + KERNEL_UBOOT_EXTRA_TARGET="" + + # Additional kernel make parameters (for example to specify the u-boot loadaddress) + KERNEL_MAKE_EXTRACMD="dtbs" + + # Kernel to use. values can be: + # default: default mainline kernel + LINUX="default" + + EXTRA_CMDLINE="console=ttyS0,115200 console=tty1" + +################################################################################ +# setup build defaults +################################################################################ + + # Project CFLAGS + PROJECT_CFLAGS="" + + # SquashFS compression method (gzip / lzo / xz / zstd) + SQUASHFS_COMPRESSION="zstd" + +################################################################################ +# setup project defaults +################################################################################ + + # build and install ALSA Audio support (yes / no) + ALSA_SUPPORT="yes" + + # OpenGL(X) implementation to use (no / mesa) + OPENGL="no" + + # OpenGL-ES implementation to use (no / bcm2835-driver / gpu-viv-bin-mx6q) + OPENGLES="libmali" + + # include uvesafb support (yes / no) + UVESAFB_SUPPORT="no" + + # Displayserver to use (x11 / no) + DISPLAYSERVER="no" + + # Windowmanager to use (ratpoison / fluxbox / none) + WINDOWMANAGER="none" + + # Xorg Graphic drivers to use (all / i915,i965,r200,r300,r600,nvidia) + # Space separated list is supported, + # e.g. GRAPHIC_DRIVERS="i915 i965 r300 r600 radeonsi nvidia" + GRAPHIC_DRIVERS="" + + # KODI Player implementation to use (default / bcm2835-driver / libfslvpuwrap) + KODIPLAYER_DRIVER="$OPENGLES" + + # Modules to install in initramfs for early boot + INITRAMFS_MODULES="" + + # additional Firmware to use (dvb-firmware, misc-firmware, wlan-firmware) + # Space separated list is supported, + # e.g. FIRMWARE="dvb-firmware misc-firmware wlan-firmware" + FIRMWARE="misc-firmware wlan-firmware dvb-firmware" + + # build and install ATV IR remote support (yes / no) + ATVCLIENT_SUPPORT="no" + + # build and install CEC framework support (yes / no) + CEC_FRAMEWORK_SUPPORT="yes" + + # build with installer (yes / no) + INSTALLER_SUPPORT="no" diff --git a/projects/Allwinner/patches/kodi/0001-Remove-check-for-sw-format.patch b/projects/Allwinner/patches/kodi/0001-Remove-check-for-sw-format.patch new file mode 100644 index 0000000000..f52879752d --- /dev/null +++ b/projects/Allwinner/patches/kodi/0001-Remove-check-for-sw-format.patch @@ -0,0 +1,18 @@ +diff --git a/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.cpp b/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.cpp +index 3b0d0d832d..221f48f061 100644 +--- a/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.cpp ++++ b/xbmc/cores/VideoPlayer/DVDCodecs/Video/DVDVideoCodecDRMPRIME.cpp +@@ -243,12 +362,6 @@ bool CDVDVideoCodecDRMPRIME::Open(CDVDStreamInfo& hints, CDVDCodecOptions& optio + return false; + } + +- if (m_pCodecContext->pix_fmt != AV_PIX_FMT_DRM_PRIME) +- { +- CLog::Log(LOGNOTICE, "CDVDVideoCodecDRMPRIME::%s - unexpected pix fmt %s", __FUNCTION__, av_get_pix_fmt_name(m_pCodecContext->pix_fmt)); +- avcodec_free_context(&m_pCodecContext); +- return false; +- } + + const char* pixFmtName = av_get_pix_fmt_name(m_pCodecContext->pix_fmt); + m_processInfo.SetVideoPixelFormat(pixFmtName ? pixFmtName : ""); + diff --git a/projects/Allwinner/patches/kodi/0002-guisize.patch b/projects/Allwinner/patches/kodi/0002-guisize.patch new file mode 100644 index 0000000000..c421f5969f --- /dev/null +++ b/projects/Allwinner/patches/kodi/0002-guisize.patch @@ -0,0 +1,153 @@ +From 7a88b0ad7a90a8ac2266f87ccb08dca5df0c0867 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 14 Oct 2018 14:20:03 +0200 +Subject: [PATCH] WIP: windowing/gbm: add option to limit gui size + +--- + .../resources/strings.po | 52 ++++++++++++++++++- + system/settings/gbm.xml | 15 ++++++ + xbmc/windowing/gbm/DRMUtils.cpp | 28 ++++++++++ + 3 files changed, 94 insertions(+), 1 deletion(-) + +diff --git a/addons/resource.language.en_gb/resources/strings.po b/addons/resource.language.en_gb/resources/strings.po +index 97211d3b718a..eaa5b3fed759 100644 +--- a/addons/resource.language.en_gb/resources/strings.po ++++ b/addons/resource.language.en_gb/resources/strings.po +@@ -7256,7 +7256,57 @@ msgctxt "#13465" + msgid "EGL" + msgstr "" + +-#empty strings from id 13466 to 13504 ++#empty strings from id 13466 to 13485 ++ ++#. String for options 3 of setting with label #13482 "HDMI Quantization Range" ++#: system/settings/gbm.xml ++msgctxt "#13486" ++msgid "Limited" ++msgstr "" ++ ++#. Option for setting Limit GUI Size ++#: system/settings/gbm.xml ++msgctxt "#13487" ++msgid "Limit GUI Size" ++msgstr "" ++ ++#. Description of setting with label #13487 "Limit GUI Size" ++#: system/settings/gbm.xml ++msgctxt "#13488" ++msgid "This option limits GUI size for screen resolutions above 1080p. Requires restart." ++msgstr "" ++ ++#. String for options 1 of setting with label #13487 "Limit GUI Size" ++#: system/settings/gbm.xml ++msgctxt "#13489" ++msgid "No limit" ++msgstr "" ++ ++#. String for options 2 of setting with label #13487 "Limit GUI Size" ++#: system/settings/gbm.xml ++msgctxt "#13490" ++msgid "720p" ++msgstr "" ++ ++#. String for options 3 of setting with label #13487 "Limit GUI Size" ++#: system/settings/gbm.xml ++msgctxt "#13491" ++msgid "1080p / 720p (>30hz)" ++msgstr "" ++ ++#. String for options 4 of setting with label #13487 "Limit GUI Size" ++#: system/settings/gbm.xml ++msgctxt "#13492" ++msgid "1080p" ++msgstr "" ++ ++#. String for options 5 of setting with label #13487 "Limit GUI Size" ++#: system/settings/gbm.xml ++msgctxt "#13493" ++msgid "No limit / 1080p (>30hz)" ++msgstr "" ++ ++#empty strings from id 13494 to 13504 + + #: system/settings/settings.xml + msgctxt "#13505" +diff --git a/system/settings/gbm.xml b/system/settings/gbm.xml +index c5e4d98e0bef..830576c156a6 100644 +--- a/system/settings/gbm.xml ++++ b/system/settings/gbm.xml +@@ -41,6 +41,21 @@ + + false + ++ ++ false ++ 3 ++ 0 ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + + 3 + false +diff --git a/xbmc/windowing/gbm/DRMUtils.cpp b/xbmc/windowing/gbm/DRMUtils.cpp +index fceaf770d363..21a6f8f1b926 100644 +--- a/xbmc/windowing/gbm/DRMUtils.cpp ++++ b/xbmc/windowing/gbm/DRMUtils.cpp +@@ -17,6 +17,8 @@ + #include + + #include "platform/linux/XTimeUtils.h" ++#include "settings/Settings.h" ++#include "settings/SettingsComponent.h" + #include "utils/log.h" + #include "utils/StringUtils.h" + #include "windowing/GraphicContext.h" +@@ -25,6 +27,8 @@ + + using namespace KODI::WINDOWING::GBM; + ++const std::string SETTING_VIDEOSCREEN_LIMITGUISIZE = "videoscreen.limitguisize"; ++ + CDRMUtils::CDRMUtils() + : m_connector(new connector) + , m_encoder(new encoder) +@@ -731,6 +735,30 @@ RESOLUTION_INFO CDRMUtils::GetResolutionInfo(drmModeModeInfoPtr mode) + res.iWidth = res.iScreenWidth; + res.iHeight = res.iScreenHeight; + ++ int limit = CServiceBroker::GetSettingsComponent()->GetSettings()->GetInt(SETTING_VIDEOSCREEN_LIMITGUISIZE); ++ if (limit > 0 && res.iScreenWidth > 1920 && res.iScreenHeight > 1080) ++ { ++ switch (limit) ++ { ++ case 1: ++ res.iWidth = 1280; ++ res.iHeight = 720; ++ break; ++ case 2: ++ res.iWidth = mode->vrefresh > 30 ? 1280 : 1920; ++ res.iHeight = mode->vrefresh > 30 ? 720 : 1080; ++ break; ++ case 3: ++ res.iWidth = 1920; ++ res.iHeight = 1080; ++ break; ++ case 4: ++ res.iWidth = mode->vrefresh > 30 ? 1920 : res.iScreenWidth; ++ res.iHeight = mode->vrefresh > 30 ? 1080 : res.iScreenHeight; ++ break; ++ } ++ } ++ + if (mode->clock % 5 != 0) + res.fRefreshRate = static_cast(mode->vrefresh) * (1000.0f/1001.0f); + else diff --git a/projects/Allwinner/patches/linux/0001-hdmi-sound-improvements.patch b/projects/Allwinner/patches/linux/0001-hdmi-sound-improvements.patch new file mode 100644 index 0000000000..d62f69510e --- /dev/null +++ b/projects/Allwinner/patches/linux/0001-hdmi-sound-improvements.patch @@ -0,0 +1,1864 @@ +From 856cf7018cd05c18d1693b04cad6d81450ed2948 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 16 Dec 2018 10:22:09 +0100 +Subject: [PATCH 01/15] drm: dw-hdmi: extract dw_hdmi_connector_update_edid() + +Extract code that updates EDID into a dw_hdmi_connector_update_edid() helper, +it will be called from dw_hdmi_connector_detect(). + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 5971976284bf..e89efed80357 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -1905,7 +1905,8 @@ dw_hdmi_connector_detect(struct drm_connector *connector, bool force) + return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); + } + +-static int dw_hdmi_connector_get_modes(struct drm_connector *connector) ++static int dw_hdmi_connector_update_edid(struct drm_connector *connector, ++ bool add_modes) + { + struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, + connector); +@@ -1924,7 +1925,8 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) + hdmi->sink_has_audio = drm_detect_monitor_audio(edid); + drm_connector_update_edid_property(connector, edid); + cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); +- ret = drm_add_edid_modes(connector, edid); ++ if (add_modes) ++ ret = drm_add_edid_modes(connector, edid); + kfree(edid); + } else { + dev_dbg(hdmi->dev, "failed to get edid\n"); +@@ -1933,6 +1935,11 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) + return ret; + } + ++static int dw_hdmi_connector_get_modes(struct drm_connector *connector) ++{ ++ return dw_hdmi_connector_update_edid(connector, true); ++} ++ + static void dw_hdmi_connector_force(struct drm_connector *connector) + { + struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, +-- +2.20.0 + + +From 5176a54a40006c739c05b109ab32b361d5cae350 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 16 Dec 2018 11:38:43 +0100 +Subject: [PATCH 02/15] drm: dw-hdmi: move dw_hdmi_connector_detect() + +Move dw_hdmi_connector_detect() it will call dw_hdmi_connector_update_edid(). + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 30 +++++++++++------------ + 1 file changed, 15 insertions(+), 15 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index e89efed80357..b293290ac525 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -1890,21 +1890,6 @@ static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) + hdmi->rxsense); + } + +-static enum drm_connector_status +-dw_hdmi_connector_detect(struct drm_connector *connector, bool force) +-{ +- struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, +- connector); +- +- mutex_lock(&hdmi->mutex); +- hdmi->force = DRM_FORCE_UNSPECIFIED; +- dw_hdmi_update_power(hdmi); +- dw_hdmi_update_phy_mask(hdmi); +- mutex_unlock(&hdmi->mutex); +- +- return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); +-} +- + static int dw_hdmi_connector_update_edid(struct drm_connector *connector, + bool add_modes) + { +@@ -1935,6 +1920,21 @@ static int dw_hdmi_connector_update_edid(struct drm_connector *connector, + return ret; + } + ++static enum drm_connector_status ++dw_hdmi_connector_detect(struct drm_connector *connector, bool force) ++{ ++ struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, ++ connector); ++ ++ mutex_lock(&hdmi->mutex); ++ hdmi->force = DRM_FORCE_UNSPECIFIED; ++ dw_hdmi_update_power(hdmi); ++ dw_hdmi_update_phy_mask(hdmi); ++ mutex_unlock(&hdmi->mutex); ++ ++ return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); ++} ++ + static int dw_hdmi_connector_get_modes(struct drm_connector *connector) + { + return dw_hdmi_connector_update_edid(connector, true); +-- +2.20.0 + + +From 46f3c1a32813d7e822a62188ba820b15e87ba49c Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 16 Dec 2018 10:22:09 +0100 +Subject: [PATCH 03/15] drm: dw-hdmi: update CEC phys addr and EDID on HPD + event + +Update CEC phys addr and EDID on HPD event, fixes lost CEC phys addr and +stale EDID when HDMI cable is unplugged/replugged or AVR is powered on/off. + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 +++++++++----- + 1 file changed, 9 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index b293290ac525..6334bfe5c802 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -1923,6 +1923,7 @@ static int dw_hdmi_connector_update_edid(struct drm_connector *connector, + static enum drm_connector_status + dw_hdmi_connector_detect(struct drm_connector *connector, bool force) + { ++ enum drm_connector_status status; + struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, + connector); + +@@ -1932,7 +1933,14 @@ dw_hdmi_connector_detect(struct drm_connector *connector, bool force) + dw_hdmi_update_phy_mask(hdmi); + mutex_unlock(&hdmi->mutex); + +- return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); ++ status = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); ++ ++ if (status == connector_status_connected) ++ dw_hdmi_connector_update_edid(connector, false); ++ else ++ cec_notifier_set_phys_addr(hdmi->cec_notifier, CEC_PHYS_ADDR_INVALID); ++ ++ return status; + } + + static int dw_hdmi_connector_get_modes(struct drm_connector *connector) +@@ -2148,10 +2156,6 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) + dw_hdmi_setup_rx_sense(hdmi, + phy_stat & HDMI_PHY_HPD, + phy_stat & HDMI_PHY_RX_SENSE); +- +- if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) +- cec_notifier_set_phys_addr(hdmi->cec_notifier, +- CEC_PHYS_ADDR_INVALID); + } + + if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { +-- +2.20.0 + + +From 2d47e06b748342aa49c7d9871a1fac87f68341be Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 16 Dec 2018 10:22:09 +0100 +Subject: [PATCH 04/15] Revert "drm/edid: make drm_edid_to_eld() static" + +drm_edid_to_eld() is needed to update stale connector ELD on HPD event. + +This reverts part of commit 79436a1c9bccf5e38cb6ea26e4e4b9283baf2e20. + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/drm_edid.c | 5 +++-- + include/drm/drm_edid.h | 1 + + 2 files changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c +index b506e3622b08..694336e678f9 100644 +--- a/drivers/gpu/drm/drm_edid.c ++++ b/drivers/gpu/drm/drm_edid.c +@@ -3892,7 +3892,7 @@ static void clear_eld(struct drm_connector *connector) + connector->audio_latency[1] = 0; + } + +-/* ++/** + * drm_edid_to_eld - build ELD from EDID + * @connector: connector corresponding to the HDMI/DP sink + * @edid: EDID to parse +@@ -3900,7 +3900,7 @@ static void clear_eld(struct drm_connector *connector) + * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The + * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. + */ +-static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) ++void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) + { + uint8_t *eld = connector->eld; + u8 *cea; +@@ -3985,6 +3985,7 @@ static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) + DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", + drm_eld_size(eld), total_sad_count); + } ++EXPORT_SYMBOL(drm_edid_to_eld); + + /** + * drm_edid_to_sad - extracts SADs from EDID +diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h +index e3c404833115..3942d551be67 100644 +--- a/include/drm/drm_edid.h ++++ b/include/drm/drm_edid.h +@@ -333,6 +333,7 @@ struct drm_encoder; + struct drm_connector; + struct drm_display_mode; + ++void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid); + int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads); + int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb); + int drm_av_sync_delay(struct drm_connector *connector, +-- +2.20.0 + + +From c9c9158f4f78735c3c220624a89e0354fe4a2807 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 16 Dec 2018 10:22:09 +0100 +Subject: [PATCH 05/15] drm: dw-hdmi: update ELD on HPD event + +Update connector ELD on HPD event, fixes stale ELD when +HDMI cable is unplugged/replugged or AVR is powered on/off. + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 6334bfe5c802..1f36c6944e60 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -1912,6 +1912,8 @@ static int dw_hdmi_connector_update_edid(struct drm_connector *connector, + cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); + if (add_modes) + ret = drm_add_edid_modes(connector, edid); ++ else ++ drm_edid_to_eld(connector, edid); + kfree(edid); + } else { + dev_dbg(hdmi->dev, "failed to get edid\n"); +-- +2.20.0 + + +From f534ca70362421fa028bd64ec1ece3abf559357e Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 16 Dec 2018 10:22:09 +0100 +Subject: [PATCH 06/15] ASoC: hdmi-codec: add hdmi_codec_eld_notify() + +Add helper that will notify userspace when ELD control has changed. + +Signed-off-by: Jonas Karlman +--- + include/sound/hdmi-codec.h | 2 ++ + sound/soc/codecs/hdmi-codec.c | 24 ++++++++++++++++++++---- + 2 files changed, 22 insertions(+), 4 deletions(-) + +diff --git a/include/sound/hdmi-codec.h b/include/sound/hdmi-codec.h +index 9483c55f871b..7cf66a4c79fb 100644 +--- a/include/sound/hdmi-codec.h ++++ b/include/sound/hdmi-codec.h +@@ -107,6 +107,8 @@ struct hdmi_codec_pdata { + void *data; + }; + ++void hdmi_codec_eld_notify(struct device *dev); ++ + #define HDMI_CODEC_DRV_NAME "hdmi-audio-codec" + + #endif /* __HDMI_CODEC_H__ */ +diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c +index d00734d31e04..4bf9ec7f6650 100644 +--- a/sound/soc/codecs/hdmi-codec.c ++++ b/sound/soc/codecs/hdmi-codec.c +@@ -285,6 +285,8 @@ struct hdmi_codec_priv { + uint8_t eld[MAX_ELD_BYTES]; + struct snd_pcm_chmap *chmap_info; + unsigned int chmap_idx; ++ struct snd_card *snd_card; ++ struct snd_kcontrol *kctl; + }; + + static const struct snd_soc_dapm_widget hdmi_widgets[] = { +@@ -649,7 +651,6 @@ static int hdmi_codec_pcm_new(struct snd_soc_pcm_runtime *rtd, + { + struct snd_soc_dai_driver *drv = dai->driver; + struct hdmi_codec_priv *hcp = snd_soc_dai_get_drvdata(dai); +- struct snd_kcontrol *kctl; + struct snd_kcontrol_new hdmi_eld_ctl = { + .access = SNDRV_CTL_ELEM_ACCESS_READ | + SNDRV_CTL_ELEM_ACCESS_VOLATILE, +@@ -678,12 +679,27 @@ static int hdmi_codec_pcm_new(struct snd_soc_pcm_runtime *rtd, + hcp->chmap_idx = HDMI_CODEC_CHMAP_IDX_UNKNOWN; + + /* add ELD ctl with the device number corresponding to the PCM stream */ +- kctl = snd_ctl_new1(&hdmi_eld_ctl, dai->component); +- if (!kctl) ++ hcp->kctl = snd_ctl_new1(&hdmi_eld_ctl, dai->component); ++ if (!hcp->kctl) + return -ENOMEM; + +- return snd_ctl_add(rtd->card->snd_card, kctl); ++ hcp->snd_card = rtd->card->snd_card; ++ ++ return snd_ctl_add(hcp->snd_card, hcp->kctl); ++} ++ ++void hdmi_codec_eld_notify(struct device *dev) ++{ ++ struct hdmi_codec_priv *hcp = dev_get_drvdata(dev); ++ struct snd_ctl_elem_id id; ++ ++ if (!hcp->snd_card || !hcp->kctl) ++ return; ++ ++ id = hcp->kctl->id; ++ snd_ctl_notify(hcp->snd_card, SNDRV_CTL_EVENT_MASK_VALUE, &id); + } ++EXPORT_SYMBOL_GPL(hdmi_codec_eld_notify); + + static int hdmi_dai_probe(struct snd_soc_dai *dai) + { +-- +2.20.0 + + +From e6330c025b17045a1c050b85ac832a6ce5a9b3aa Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 16 Dec 2018 12:56:33 +0100 +Subject: [PATCH 07/15] drm: dw-hdmi: add dw_hdmi_update_eld() callback + +Signed-off-by: Jonas Karlman +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 15 +++++++++++++++ + include/drm/bridge/dw_hdmi.h | 2 ++ + 2 files changed, 17 insertions(+) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 1f36c6944e60..3664a89eddad 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -181,6 +181,7 @@ struct dw_hdmi { + struct regmap *regm; + void (*enable_audio)(struct dw_hdmi *hdmi); + void (*disable_audio)(struct dw_hdmi *hdmi); ++ void (*update_eld)(struct device *dev, u8 *eld); + + struct cec_notifier *cec_notifier; + }; +@@ -606,6 +607,19 @@ void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) + } + EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); + ++static void dw_hdmi_update_eld(struct dw_hdmi *hdmi, u8 *eld) ++{ ++ if (hdmi->audio && hdmi->update_eld) ++ hdmi->update_eld(&hdmi->audio->dev, eld); ++} ++ ++void dw_hdmi_set_update_eld(struct dw_hdmi *hdmi, ++ void (*update_eld)(struct device *dev, u8 *eld)) ++{ ++ hdmi->update_eld = update_eld; ++} ++EXPORT_SYMBOL_GPL(dw_hdmi_set_update_eld); ++ + static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) + { + switch (bus_format) { +@@ -1914,6 +1928,7 @@ static int dw_hdmi_connector_update_edid(struct drm_connector *connector, + ret = drm_add_edid_modes(connector, edid); + else + drm_edid_to_eld(connector, edid); ++ dw_hdmi_update_eld(hdmi, connector->eld); + kfree(edid); + } else { + dev_dbg(hdmi->dev, "failed to get edid\n"); +diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h +index ccb5aa8468e0..e78be449e763 100644 +--- a/include/drm/bridge/dw_hdmi.h ++++ b/include/drm/bridge/dw_hdmi.h +@@ -156,6 +156,8 @@ void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense); + void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate); + void dw_hdmi_audio_enable(struct dw_hdmi *hdmi); + void dw_hdmi_audio_disable(struct dw_hdmi *hdmi); ++void dw_hdmi_set_update_eld(struct dw_hdmi *hdmi, ++ void (*update_eld)(struct device *dev, u8 *eld)); + + /* PHY configuration */ + void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address); +-- +2.20.0 + + +From 43d6faaba7ff0d5d832f1642ea0ee6c87584e0f7 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 16 Dec 2018 10:22:09 +0100 +Subject: [PATCH 08/15] drm: dw-hdmi-i2s: add .get_eld callback for ALSA SoC + +Add get_eld() callback and call hdmi_codec_eld_notify() when ELD has changed. + +Signed-off-by: Jonas Karlman +--- + .../gpu/drm/bridge/synopsys/dw-hdmi-audio.h | 1 + + .../drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 36 ++++++++++++++++++- + 2 files changed, 36 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h +index 63b5756f463b..69b8a9734c34 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h +@@ -14,6 +14,7 @@ struct dw_hdmi_audio_data { + + struct dw_hdmi_i2s_audio_data { + struct dw_hdmi *hdmi; ++ u8 eld[128]; + + void (*write)(struct dw_hdmi *hdmi, u8 val, int offset); + u8 (*read)(struct dw_hdmi *hdmi, int offset); +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +index 8f9c8a6b46de..609ebad4bd0b 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +@@ -83,6 +83,32 @@ static void dw_hdmi_i2s_audio_shutdown(struct device *dev, void *data) + hdmi_write(audio, HDMI_AUD_CONF0_SW_RESET, HDMI_AUD_CONF0); + } + ++static void dw_hdmi_i2s_update_eld(struct device *dev, u8 *eld) ++{ ++ struct dw_hdmi_i2s_audio_data *audio = dev_get_platdata(dev); ++ struct platform_device *hcpdev = dev_get_drvdata(dev); ++ ++ if (!audio || !hcpdev) ++ return; ++ ++ if (!memcmp(audio->eld, eld, sizeof(audio->eld))) ++ return; ++ ++ memcpy(audio->eld, eld, sizeof(audio->eld)); ++ ++ hdmi_codec_eld_notify(&hcpdev->dev); ++} ++ ++static int dw_hdmi_i2s_get_eld(struct device *dev, void *data, ++ u8 *buf, size_t len) ++{ ++ struct dw_hdmi_i2s_audio_data *audio = data; ++ ++ memcpy(buf, audio->eld, min(sizeof(audio->eld), len)); ++ ++ return 0; ++} ++ + static int dw_hdmi_i2s_get_dai_id(struct snd_soc_component *component, + struct device_node *endpoint) + { +@@ -106,16 +132,19 @@ static int dw_hdmi_i2s_get_dai_id(struct snd_soc_component *component, + static struct hdmi_codec_ops dw_hdmi_i2s_ops = { + .hw_params = dw_hdmi_i2s_hw_params, + .audio_shutdown = dw_hdmi_i2s_audio_shutdown, ++ .get_eld = dw_hdmi_i2s_get_eld, + .get_dai_id = dw_hdmi_i2s_get_dai_id, + }; + + static int snd_dw_hdmi_probe(struct platform_device *pdev) + { +- struct dw_hdmi_i2s_audio_data *audio = pdev->dev.platform_data; ++ struct dw_hdmi_i2s_audio_data *audio = dev_get_platdata(&pdev->dev); + struct platform_device_info pdevinfo; + struct hdmi_codec_pdata pdata; + struct platform_device *platform; + ++ memset(audio->eld, 0, sizeof(audio->eld)); ++ + pdata.ops = &dw_hdmi_i2s_ops; + pdata.i2s = 1; + pdata.max_i2s_channels = 6; +@@ -135,13 +164,18 @@ static int snd_dw_hdmi_probe(struct platform_device *pdev) + + dev_set_drvdata(&pdev->dev, platform); + ++ dw_hdmi_set_update_eld(audio->hdmi, dw_hdmi_i2s_update_eld); ++ + return 0; + } + + static int snd_dw_hdmi_remove(struct platform_device *pdev) + { ++ struct dw_hdmi_i2s_audio_data *audio = dev_get_platdata(&pdev->dev); + struct platform_device *platform = dev_get_drvdata(&pdev->dev); + ++ dw_hdmi_set_update_eld(audio->hdmi, NULL); ++ + platform_device_unregister(platform); + + return 0; +-- +2.20.0 + + +From dc25172bb38b6e5a39c7254295bf73daf9296120 Mon Sep 17 00:00:00 2001 +From: Neil Armstrong +Date: Mon, 2 Jul 2018 12:21:55 +0200 +Subject: [PATCH 09/15] drm: bridge: dw-hdmi: Use AUTO CTS setup mode when + non-AHB audio + +Signed-off-by: Neil Armstrong +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 41 ++++++++++++++--------- + 1 file changed, 26 insertions(+), 15 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 3664a89eddad..3b3834ff2506 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -431,8 +431,12 @@ static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, + /* nshift factor = 0 */ + hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); + +- hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | +- HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); ++ /* Use Auto CTS mode with CTS is unknown */ ++ if (cts) ++ hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | ++ HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); ++ else ++ hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); + hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); + hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); + +@@ -502,24 +506,31 @@ static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, + { + unsigned long ftdms = pixel_clk; + unsigned int n, cts; ++ u8 config3; + u64 tmp; + + n = hdmi_compute_n(sample_rate, pixel_clk); + +- /* +- * Compute the CTS value from the N value. Note that CTS and N +- * can be up to 20 bits in total, so we need 64-bit math. Also +- * note that our TDMS clock is not fully accurate; it is accurate +- * to kHz. This can introduce an unnecessary remainder in the +- * calculation below, so we don't try to warn about that. +- */ +- tmp = (u64)ftdms * n; +- do_div(tmp, 128 * sample_rate); +- cts = tmp; ++ config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); + +- dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", +- __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, +- n, cts); ++ if (config3 & HDMI_CONFIG3_AHBAUDDMA) { ++ /* ++ * Compute the CTS value from the N value. Note that CTS and N ++ * can be up to 20 bits in total, so we need 64-bit math. Also ++ * note that our TDMS clock is not fully accurate; it is ++ * accurate to kHz. This can introduce an unnecessary remainder ++ * in the calculation below, so we don't try to warn about that. ++ */ ++ tmp = (u64)ftdms * n; ++ do_div(tmp, 128 * sample_rate); ++ cts = tmp; ++ ++ dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", ++ __func__, sample_rate, ++ ftdms / 1000000, (ftdms / 1000) % 1000, ++ n, cts); ++ } else ++ cts = 0; + + spin_lock_irq(&hdmi->audio_lock); + hdmi->audio_n = n; +-- +2.20.0 + + +From fd248f45d63ab907ffe75b2889d5a3fa63b68039 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 25 Mar 2018 22:17:06 +0200 +Subject: [PATCH 10/15] ASoC: hdmi-codec: fix channel allocation + +--- + sound/soc/codecs/hdmi-codec.c | 113 ++++++++++++++++------------------ + 1 file changed, 52 insertions(+), 61 deletions(-) + +diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c +index 4bf9ec7f6650..dc84bfbe7e87 100644 +--- a/sound/soc/codecs/hdmi-codec.c ++++ b/sound/soc/codecs/hdmi-codec.c +@@ -202,78 +202,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = { + */ + static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = { + { .ca_id = 0x00, .n_ch = 2, +- .mask = FL | FR}, +- /* 2.1 */ +- { .ca_id = 0x01, .n_ch = 4, +- .mask = FL | FR | LFE}, +- /* Dolby Surround */ ++ .mask = FL | FR }, ++ { .ca_id = 0x03, .n_ch = 4, ++ .mask = FL | FR | LFE | FC }, + { .ca_id = 0x02, .n_ch = 4, + .mask = FL | FR | FC }, +- /* surround51 */ ++ { .ca_id = 0x01, .n_ch = 4, ++ .mask = FL | FR | LFE }, + { .ca_id = 0x0b, .n_ch = 6, +- .mask = FL | FR | LFE | FC | RL | RR}, +- /* surround40 */ +- { .ca_id = 0x08, .n_ch = 6, +- .mask = FL | FR | RL | RR }, +- /* surround41 */ +- { .ca_id = 0x09, .n_ch = 6, +- .mask = FL | FR | LFE | RL | RR }, +- /* surround50 */ ++ .mask = FL | FR | LFE | FC | RL | RR }, + { .ca_id = 0x0a, .n_ch = 6, + .mask = FL | FR | FC | RL | RR }, +- /* 6.1 */ +- { .ca_id = 0x0f, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RL | RR | RC }, +- /* surround71 */ ++ { .ca_id = 0x09, .n_ch = 6, ++ .mask = FL | FR | LFE | RL | RR }, ++ { .ca_id = 0x08, .n_ch = 6, ++ .mask = FL | FR | RL | RR }, ++ { .ca_id = 0x07, .n_ch = 6, ++ .mask = FL | FR | LFE | FC | RC }, ++ { .ca_id = 0x06, .n_ch = 6, ++ .mask = FL | FR | FC | RC }, ++ { .ca_id = 0x05, .n_ch = 6, ++ .mask = FL | FR | LFE | RC }, ++ { .ca_id = 0x04, .n_ch = 6, ++ .mask = FL | FR | RC }, + { .ca_id = 0x13, .n_ch = 8, + .mask = FL | FR | LFE | FC | RL | RR | RLC | RRC }, +- /* others */ +- { .ca_id = 0x03, .n_ch = 8, +- .mask = FL | FR | LFE | FC }, +- { .ca_id = 0x04, .n_ch = 8, +- .mask = FL | FR | RC}, +- { .ca_id = 0x05, .n_ch = 8, +- .mask = FL | FR | LFE | RC }, +- { .ca_id = 0x06, .n_ch = 8, +- .mask = FL | FR | FC | RC }, +- { .ca_id = 0x07, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RC }, +- { .ca_id = 0x0c, .n_ch = 8, +- .mask = FL | FR | RC | RL | RR }, +- { .ca_id = 0x0d, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | RC }, +- { .ca_id = 0x0e, .n_ch = 8, +- .mask = FL | FR | FC | RL | RR | RC }, +- { .ca_id = 0x10, .n_ch = 8, +- .mask = FL | FR | RL | RR | RLC | RRC }, +- { .ca_id = 0x11, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1f, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, + { .ca_id = 0x12, .n_ch = 8, + .mask = FL | FR | FC | RL | RR | RLC | RRC }, +- { .ca_id = 0x14, .n_ch = 8, +- .mask = FL | FR | FLC | FRC }, +- { .ca_id = 0x15, .n_ch = 8, +- .mask = FL | FR | LFE | FLC | FRC }, +- { .ca_id = 0x16, .n_ch = 8, +- .mask = FL | FR | FC | FLC | FRC }, +- { .ca_id = 0x17, .n_ch = 8, +- .mask = FL | FR | LFE | FC | FLC | FRC }, +- { .ca_id = 0x18, .n_ch = 8, +- .mask = FL | FR | RC | FLC | FRC }, +- { .ca_id = 0x19, .n_ch = 8, +- .mask = FL | FR | LFE | RC | FLC | FRC }, +- { .ca_id = 0x1a, .n_ch = 8, +- .mask = FL | FR | RC | FC | FLC | FRC }, +- { .ca_id = 0x1b, .n_ch = 8, +- .mask = FL | FR | LFE | RC | FC | FLC | FRC }, +- { .ca_id = 0x1c, .n_ch = 8, +- .mask = FL | FR | RL | RR | FLC | FRC }, +- { .ca_id = 0x1d, .n_ch = 8, +- .mask = FL | FR | LFE | RL | RR | FLC | FRC }, + { .ca_id = 0x1e, .n_ch = 8, + .mask = FL | FR | FC | RL | RR | FLC | FRC }, +- { .ca_id = 0x1f, .n_ch = 8, +- .mask = FL | FR | LFE | FC | RL | RR | FLC | FRC }, ++ { .ca_id = 0x11, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1d, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | FLC | FRC }, ++ { .ca_id = 0x10, .n_ch = 8, ++ .mask = FL | FR | RL | RR | RLC | RRC }, ++ { .ca_id = 0x1c, .n_ch = 8, ++ .mask = FL | FR | RL | RR | FLC | FRC }, ++ { .ca_id = 0x0f, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | RL | RR | RC }, ++ { .ca_id = 0x1b, .n_ch = 8, ++ .mask = FL | FR | LFE | RC | FC | FLC | FRC }, ++ { .ca_id = 0x0e, .n_ch = 8, ++ .mask = FL | FR | FC | RL | RR | RC }, ++ { .ca_id = 0x1a, .n_ch = 8, ++ .mask = FL | FR | RC | FC | FLC | FRC }, ++ { .ca_id = 0x0d, .n_ch = 8, ++ .mask = FL | FR | LFE | RL | RR | RC }, ++ { .ca_id = 0x19, .n_ch = 8, ++ .mask = FL | FR | LFE | RC | FLC | FRC }, ++ { .ca_id = 0x0c, .n_ch = 8, ++ .mask = FL | FR | RC | RL | RR }, ++ { .ca_id = 0x18, .n_ch = 8, ++ .mask = FL | FR | RC | FLC | FRC }, ++ { .ca_id = 0x17, .n_ch = 8, ++ .mask = FL | FR | LFE | FC | FLC | FRC }, ++ { .ca_id = 0x16, .n_ch = 8, ++ .mask = FL | FR | FC | FLC | FRC }, ++ { .ca_id = 0x15, .n_ch = 8, ++ .mask = FL | FR | LFE | FLC | FRC }, ++ { .ca_id = 0x14, .n_ch = 8, ++ .mask = FL | FR | FLC | FRC }, + }; + + struct hdmi_codec_priv { +-- +2.20.0 + + +From c66fc8b2d97b6c03ab79791578a86c8eb4b099db Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Tue, 10 Jul 2018 20:54:33 +0200 +Subject: [PATCH 11/15] drm: dw-hdmi-i2s: add multi-channel lpcm support + +--- + .../gpu/drm/bridge/synopsys/dw-hdmi-audio.h | 1 + + .../drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 75 ++++++++++++++++++- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 + + drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 24 ++++++ + 4 files changed, 98 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h +index 69b8a9734c34..9e9cbf934d96 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-audio.h +@@ -18,6 +18,7 @@ struct dw_hdmi_i2s_audio_data { + + void (*write)(struct dw_hdmi *hdmi, u8 val, int offset); + u8 (*read)(struct dw_hdmi *hdmi, int offset); ++ void (*mod)(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg); + }; + + #endif +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +index 609ebad4bd0b..637ef1f567fc 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c +@@ -32,6 +32,14 @@ static inline u8 hdmi_read(struct dw_hdmi_i2s_audio_data *audio, int offset) + return audio->read(hdmi, offset); + } + ++static inline void hdmi_update_bits(struct dw_hdmi_i2s_audio_data *audio, ++ u8 data, u8 mask, unsigned int reg) ++{ ++ struct dw_hdmi *hdmi = audio->hdmi; ++ ++ audio->mod(hdmi, data, mask, reg); ++} ++ + static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, + struct hdmi_codec_daifmt *fmt, + struct hdmi_codec_params *hparms) +@@ -41,6 +49,7 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, + u8 conf0 = 0; + u8 conf1 = 0; + u8 inputclkfs = 0; ++ u8 val; + + /* it cares I2S only */ + if ((fmt->fmt != HDMI_I2S) || +@@ -49,8 +58,23 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, + return -EINVAL; + } + +- inputclkfs = HDMI_AUD_INPUTCLKFS_64FS; +- conf0 = HDMI_AUD_CONF0_I2S_ALL_ENABLE; ++ inputclkfs = HDMI_AUD_INPUTCLKFS_64FS; ++ ++ switch (hparms->channels) { ++ case 2: ++ conf0 = HDMI_AUD_CONF0_I2S_2CHANNEL_ENABLE; ++ break; ++ case 4: ++ conf0 = HDMI_AUD_CONF0_I2S_4CHANNEL_ENABLE; ++ break; ++ case 6: ++ conf0 = HDMI_AUD_CONF0_I2S_6CHANNEL_ENABLE; ++ break; ++ case 8: ++ default: ++ conf0 = HDMI_AUD_CONF0_I2S_ALL_ENABLE; ++ break; ++ } + + switch (hparms->sample_width) { + case 16: +@@ -62,12 +86,56 @@ static int dw_hdmi_i2s_hw_params(struct device *dev, void *data, + break; + } + ++ hdmi_update_bits(audio, HDMI_AUD_CONF0_SW_RESET, ++ HDMI_AUD_CONF0_SW_RESET, HDMI_AUD_CONF0); ++ hdmi_write(audio, (u8)~HDMI_MC_SWRSTZ_I2SSWRST_REQ, HDMI_MC_SWRSTZ); ++ + dw_hdmi_set_sample_rate(hdmi, hparms->sample_rate); + + hdmi_write(audio, inputclkfs, HDMI_AUD_INPUTCLKFS); + hdmi_write(audio, conf0, HDMI_AUD_CONF0); + hdmi_write(audio, conf1, HDMI_AUD_CONF1); + ++ val = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0; ++ if (hparms->channels > 2) ++ val = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1; ++ hdmi_update_bits(audio, val, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, ++ HDMI_FC_AUDSCONF); ++ ++ switch (hparms->sample_rate) { ++ case 32000: ++ val = HDMI_FC_AUDSCHNLS_SAMPFREQ_32K; ++ break; ++ case 44100: ++ val = HDMI_FC_AUDSCHNLS_SAMPFREQ_441K; ++ break; ++ case 48000: ++ val = HDMI_FC_AUDSCHNLS_SAMPFREQ_48K; ++ break; ++ case 88200: ++ val = HDMI_FC_AUDSCHNLS_SAMPFREQ_882K; ++ break; ++ case 96000: ++ val = HDMI_FC_AUDSCHNLS_SAMPFREQ_96K; ++ break; ++ case 176400: ++ val = HDMI_FC_AUDSCHNLS_SAMPFREQ_1764K; ++ break; ++ case 192000: ++ val = HDMI_FC_AUDSCHNLS_SAMPFREQ_192K; ++ break; ++ default: ++ val = HDMI_FC_AUDSCHNLS_SAMPFREQ_441K; ++ break; ++ } ++ ++ hdmi_update_bits(audio, val, HDMI_FC_AUDSCHNLS7_SAMPFREQ_MASK, ++ HDMI_FC_AUDSCHNLS7); ++ hdmi_update_bits(audio, ++ (hparms->channels - 1) << HDMI_FC_AUDICONF0_CC_OFFSET, ++ HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0); ++ hdmi_write(audio, hparms->cea.channel_allocation, HDMI_FC_AUDICONF2); ++ + dw_hdmi_audio_enable(hdmi); + + return 0; +@@ -81,6 +149,7 @@ static void dw_hdmi_i2s_audio_shutdown(struct device *dev, void *data) + dw_hdmi_audio_disable(hdmi); + + hdmi_write(audio, HDMI_AUD_CONF0_SW_RESET, HDMI_AUD_CONF0); ++ hdmi_write(audio, (u8)~HDMI_MC_SWRSTZ_I2SSWRST_REQ, HDMI_MC_SWRSTZ); + } + + static void dw_hdmi_i2s_update_eld(struct device *dev, u8 *eld) +@@ -147,7 +216,7 @@ static int snd_dw_hdmi_probe(struct platform_device *pdev) + + pdata.ops = &dw_hdmi_i2s_ops; + pdata.i2s = 1; +- pdata.max_i2s_channels = 6; ++ pdata.max_i2s_channels = 8; + pdata.data = audio; + + memset(&pdevinfo, 0, sizeof(pdevinfo)); +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index 3b3834ff2506..cad4800f5480 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -2542,6 +2542,7 @@ __dw_hdmi_probe(struct platform_device *pdev, + audio.hdmi = hdmi; + audio.write = hdmi_writeb; + audio.read = hdmi_readb; ++ audio.mod = hdmi_modb; + hdmi->enable_audio = dw_hdmi_i2s_audio_enable; + hdmi->disable_audio = dw_hdmi_i2s_audio_disable; + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h +index 9d90eb9c46e5..760a087d2c68 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.h +@@ -162,6 +162,15 @@ + #define HDMI_FC_SPDDEVICEINF 0x1062 + #define HDMI_FC_AUDSCONF 0x1063 + #define HDMI_FC_AUDSSTAT 0x1064 ++#define HDMI_FC_AUDSCHNLS0 0x1067 ++#define HDMI_FC_AUDSCHNLS1 0x1068 ++#define HDMI_FC_AUDSCHNLS2 0x1069 ++#define HDMI_FC_AUDSCHNLS3 0x106a ++#define HDMI_FC_AUDSCHNLS4 0x106b ++#define HDMI_FC_AUDSCHNLS5 0x106c ++#define HDMI_FC_AUDSCHNLS6 0x106d ++#define HDMI_FC_AUDSCHNLS7 0x106e ++#define HDMI_FC_AUDSCHNLS8 0x106f + #define HDMI_FC_DATACH0FILL 0x1070 + #define HDMI_FC_DATACH1FILL 0x1071 + #define HDMI_FC_DATACH2FILL 0x1072 +@@ -709,6 +718,8 @@ enum { + /* HDMI_FC_AUDSCHNLS7 field values */ + HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4, + HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30, ++ HDMI_FC_AUDSCHNLS7_SAMPFREQ_OFFSET = 0, ++ HDMI_FC_AUDSCHNLS7_SAMPFREQ_MASK = 0x0f, + + /* HDMI_FC_AUDSCHNLS8 field values */ + HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0, +@@ -716,6 +727,15 @@ enum { + HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f, + HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0, + ++/* HDMI_FC_AUDSCHNLS sampling frequency */ ++ HDMI_FC_AUDSCHNLS_SAMPFREQ_32K = 0x3, ++ HDMI_FC_AUDSCHNLS_SAMPFREQ_441K = 0x0, ++ HDMI_FC_AUDSCHNLS_SAMPFREQ_48K = 0x2, ++ HDMI_FC_AUDSCHNLS_SAMPFREQ_882K = 0x8, ++ HDMI_FC_AUDSCHNLS_SAMPFREQ_96K = 0xa, ++ HDMI_FC_AUDSCHNLS_SAMPFREQ_1764K = 0xc, ++ HDMI_FC_AUDSCHNLS_SAMPFREQ_192K = 0xe, ++ + /* FC_AUDSCONF field values */ + HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0, + HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4, +@@ -868,6 +888,9 @@ enum { + + /* AUD_CONF0 field values */ + HDMI_AUD_CONF0_SW_RESET = 0x80, ++ HDMI_AUD_CONF0_I2S_2CHANNEL_ENABLE = 0x21, ++ HDMI_AUD_CONF0_I2S_4CHANNEL_ENABLE = 0x23, ++ HDMI_AUD_CONF0_I2S_6CHANNEL_ENABLE = 0x27, + HDMI_AUD_CONF0_I2S_ALL_ENABLE = 0x2F, + + /* AUD_CONF1 field values */ +@@ -941,6 +964,7 @@ enum { + HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, + + /* MC_SWRSTZ field values */ ++ HDMI_MC_SWRSTZ_I2SSWRST_REQ = 0x08, + HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, + + /* MC_FLOWCTRL field values */ +-- +2.20.0 + + +From c2f0a0cfa278e061fbfd3b957603e5f41b525043 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 9 Jul 2018 21:25:15 +0200 +Subject: [PATCH 12/15] drm: dw-hdmi: call hdmi_set_cts_n after clock is + enabled + +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index cad4800f5480..f955a7c49c05 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -571,6 +571,11 @@ static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) + else + hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; + hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); ++ ++ if (enable) { ++ hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); ++ hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); ++ } + } + + static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) +-- +2.20.0 + + +From 9df27c0a0944343f565607bd8389222b18f1f2cc Mon Sep 17 00:00:00 2001 +From: Marcus Cooper +Date: Sun, 16 Dec 2018 15:04:16 +0100 +Subject: [PATCH 13/15] ASoC: sun4i-i2s: multichannel updates + +--- + sound/soc/sunxi/sun4i-i2s.c | 394 +++++++++++++++++++++++++----------- + 1 file changed, 281 insertions(+), 113 deletions(-) + +diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c +index d5ec1a20499d..2e3fc596ab64 100644 +--- a/sound/soc/sunxi/sun4i-i2s.c ++++ b/sound/soc/sunxi/sun4i-i2s.c +@@ -27,10 +27,11 @@ + + #define SUN4I_I2S_CTRL_REG 0x00 + #define SUN4I_I2S_CTRL_SDO_EN_MASK GENMASK(11, 8) +-#define SUN4I_I2S_CTRL_SDO_EN(sdo) BIT(8 + (sdo)) ++#define SUN4I_I2S_CTRL_SDO_EN(lines) (((1 << lines) - 1) << 8) + #define SUN4I_I2S_CTRL_MODE_MASK BIT(5) + #define SUN4I_I2S_CTRL_MODE_SLAVE (1 << 5) + #define SUN4I_I2S_CTRL_MODE_MASTER (0 << 5) ++#define SUN4I_I2S_CTRL_LOOP BIT(3) + #define SUN4I_I2S_CTRL_TX_EN BIT(2) + #define SUN4I_I2S_CTRL_RX_EN BIT(1) + #define SUN4I_I2S_CTRL_GL_EN BIT(0) +@@ -110,7 +111,7 @@ + + #define SUN8I_I2S_TX_CHAN_MAP_REG 0x44 + #define SUN8I_I2S_TX_CHAN_SEL_REG 0x34 +-#define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 11) ++#define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 12) + #define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12) + #define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4) + #define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4) +@@ -129,15 +130,16 @@ + * @has_chsel_offset: SoC uses offset for selecting dai operational mode. + * @reg_offset_txdata: offset of the tx fifo. + * @sun4i_i2s_regmap: regmap config to use. +- * @mclk_offset: Value by which mclkdiv needs to be adjusted. +- * @bclk_offset: Value by which bclkdiv needs to be adjusted. + * @fmt_offset: Value by which wss and sr needs to be adjusted. + * @field_clkdiv_mclk_en: regmap field to enable mclk output. ++ * @field_clkdiv_mclk: regmap field for mclkdiv. ++ * @field_clkdiv_bclk: regmap field for bclkdiv. + * @field_fmt_wss: regmap field to set word select size. + * @field_fmt_sr: regmap field to set sample resolution. + * @field_fmt_bclk: regmap field to set clk polarity. + * @field_fmt_lrclk: regmap field to set frame polarity. + * @field_fmt_mode: regmap field to set the operational mode. ++ * @field_fmt_sext: regmap field to set the sign extension. + * @field_txchanmap: location of the tx channel mapping register. + * @field_rxchanmap: location of the rx channel mapping register. + * @field_txchansel: location of the tx channel select bit fields. +@@ -152,8 +154,6 @@ struct sun4i_i2s_quirks { + bool has_chsel_offset; + unsigned int reg_offset_txdata; /* TX FIFO */ + const struct regmap_config *sun4i_i2s_regmap; +- unsigned int mclk_offset; +- unsigned int bclk_offset; + unsigned int fmt_offset; + + /* Register fields for i2s */ +@@ -163,6 +163,7 @@ struct sun4i_i2s_quirks { + struct reg_field field_fmt_bclk; + struct reg_field field_fmt_lrclk; + struct reg_field field_fmt_mode; ++ struct reg_field field_fmt_sext; + struct reg_field field_txchanmap; + struct reg_field field_rxchanmap; + struct reg_field field_txchansel; +@@ -187,12 +188,20 @@ struct sun4i_i2s { + struct regmap_field *field_fmt_bclk; + struct regmap_field *field_fmt_lrclk; + struct regmap_field *field_fmt_mode; ++ struct regmap_field *field_fmt_sext; + struct regmap_field *field_txchanmap; + struct regmap_field *field_rxchanmap; + struct regmap_field *field_txchansel; + struct regmap_field *field_rxchansel; + + const struct sun4i_i2s_quirks *variant; ++ ++ unsigned int tdm_slots; ++ bool bit_clk_master; ++ bool loopback; ++ ++ unsigned int slot_width; ++ unsigned int offset; + }; + + struct sun4i_i2s_clk_div { +@@ -207,7 +216,25 @@ static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = { + { .div = 8, .val = 3 }, + { .div = 12, .val = 4 }, + { .div = 16, .val = 5 }, +- /* TODO - extend divide ratio supported by newer SoCs */ ++}; ++ ++static const struct sun4i_i2s_clk_div sun8i_i2s_clk_div[] = { ++ { .div = 0, .val = 0 }, ++ { .div = 1, .val = 1 }, ++ { .div = 2, .val = 2 }, ++ { .div = 4, .val = 3 }, ++ { .div = 6, .val = 4 }, ++ { .div = 8, .val = 5 }, ++ { .div = 12, .val = 6 }, ++ { .div = 16, .val = 7 }, ++ { .div = 24, .val = 8 }, ++ { .div = 32, .val = 9 }, ++ { .div = 48, .val = 10 }, ++ { .div = 64, .val = 11 }, ++ { .div = 96, .val = 12 }, ++ { .div = 128, .val = 13 }, ++ { .div = 176, .val = 14 }, ++ { .div = 192, .val = 15 }, + }; + + static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = { +@@ -219,21 +246,21 @@ static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = { + { .div = 12, .val = 5 }, + { .div = 16, .val = 6 }, + { .div = 24, .val = 7 }, +- /* TODO - extend divide ratio supported by newer SoCs */ + }; + + static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s, + unsigned int oversample_rate, +- unsigned int word_size) ++ unsigned int word_size, ++ const struct sun4i_i2s_clk_div *bdiv, ++ unsigned int size) + { + int div = oversample_rate / word_size / 2; + int i; + +- for (i = 0; i < ARRAY_SIZE(sun4i_i2s_bclk_div); i++) { +- const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i]; +- ++ for (i = 0; i < size; i++) { + if (bdiv->div == div) + return bdiv->val; ++ bdiv++; + } + + return -EINVAL; +@@ -242,16 +269,17 @@ static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s, + static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s, + unsigned int oversample_rate, + unsigned int module_rate, +- unsigned int sampling_rate) ++ unsigned int sampling_rate, ++ const struct sun4i_i2s_clk_div *mdiv, ++ unsigned int size) + { + int div = module_rate / sampling_rate / oversample_rate; + int i; + +- for (i = 0; i < ARRAY_SIZE(sun4i_i2s_mclk_div); i++) { +- const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i]; +- ++ for (i = 0; i < size; i++) { + if (mdiv->div == div) + return mdiv->val; ++ mdiv++; + } + + return -EINVAL; +@@ -262,9 +290,10 @@ static bool sun4i_i2s_oversample_is_valid(unsigned int oversample) + { + int i; + +- for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++) ++ for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++) { + if (sun4i_i2s_oversample_rates[i] == oversample) + return true; ++ } + + return false; + } +@@ -278,73 +307,102 @@ static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai, + int bclk_div, mclk_div; + int ret; + +- switch (rate) { +- case 176400: +- case 88200: +- case 44100: +- case 22050: +- case 11025: +- clk_rate = 22579200; +- break; ++ if (i2s->bit_clk_master) { ++ switch (rate) { ++ case 176400: ++ case 88200: ++ case 44100: ++ case 22050: ++ case 11025: ++ clk_rate = 22579200; ++ break; + +- case 192000: +- case 128000: +- case 96000: +- case 64000: +- case 48000: +- case 32000: +- case 24000: +- case 16000: +- case 12000: +- case 8000: +- clk_rate = 24576000; +- break; ++ case 192000: ++ case 128000: ++ case 96000: ++ case 64000: ++ case 48000: ++ case 32000: ++ case 24000: ++ case 16000: ++ case 12000: ++ case 8000: ++ clk_rate = 24576000; ++ break; + +- default: +- dev_err(dai->dev, "Unsupported sample rate: %u\n", rate); +- return -EINVAL; +- } ++ default: ++ dev_err(dai->dev, "Unsupported sample rate: %u\n", rate); ++ return -EINVAL; ++ } + +- ret = clk_set_rate(i2s->mod_clk, clk_rate); +- if (ret) +- return ret; ++ ret = clk_set_rate(i2s->mod_clk, clk_rate); ++ if (ret) { ++ dev_err(dai->dev, "Unable to set clock\n"); ++ return ret; ++ } + +- oversample_rate = i2s->mclk_freq / rate; +- if (!sun4i_i2s_oversample_is_valid(oversample_rate)) { +- dev_err(dai->dev, "Unsupported oversample rate: %d\n", +- oversample_rate); +- return -EINVAL; +- } ++ oversample_rate = i2s->mclk_freq / rate; ++ if (!sun4i_i2s_oversample_is_valid(oversample_rate)) { ++ dev_err(dai->dev, "Unsupported oversample rate: %d\n", ++ oversample_rate); ++ return -EINVAL; ++ } + +- bclk_div = sun4i_i2s_get_bclk_div(i2s, oversample_rate, +- word_size); +- if (bclk_div < 0) { +- dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div); +- return -EINVAL; +- } ++ if (i2s->variant->has_fmt_set_lrck_period) ++ bclk_div = sun4i_i2s_get_bclk_div(i2s, clk_rate / rate, ++ word_size, ++ sun8i_i2s_clk_div, ++ ARRAY_SIZE(sun8i_i2s_clk_div)); ++ else ++ bclk_div = sun4i_i2s_get_bclk_div(i2s, oversample_rate, ++ word_size, ++ sun4i_i2s_bclk_div, ++ ARRAY_SIZE(sun4i_i2s_bclk_div)); ++ if (bclk_div < 0) { ++ dev_err(dai->dev, "Unsupported BCLK divider: %d\n", ++ bclk_div); ++ return -EINVAL; ++ } + +- mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate, +- clk_rate, rate); +- if (mclk_div < 0) { +- dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div); +- return -EINVAL; +- } + +- /* Adjust the clock division values if needed */ +- bclk_div += i2s->variant->bclk_offset; +- mclk_div += i2s->variant->mclk_offset; ++ if (i2s->variant->has_fmt_set_lrck_period) ++ mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate, ++ clk_rate, rate, ++ sun8i_i2s_clk_div, ++ ARRAY_SIZE(sun8i_i2s_clk_div)); ++ else ++ mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate, ++ clk_rate, rate, ++ sun4i_i2s_mclk_div, ++ ARRAY_SIZE(sun4i_i2s_mclk_div)); ++ if (mclk_div < 0) { ++ dev_err(dai->dev, "Unsupported MCLK divider: %d\n", ++ mclk_div); ++ return -EINVAL; ++ } + +- regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG, +- SUN4I_I2S_CLK_DIV_BCLK(bclk_div) | +- SUN4I_I2S_CLK_DIV_MCLK(mclk_div)); ++ regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG, ++ SUN4I_I2S_CLK_DIV_BCLK(bclk_div) | ++ SUN4I_I2S_CLK_DIV_MCLK(mclk_div)); + +- regmap_field_write(i2s->field_clkdiv_mclk_en, 1); ++ regmap_field_write(i2s->field_clkdiv_mclk_en, 1); ++ } + + /* Set sync period */ +- if (i2s->variant->has_fmt_set_lrck_period) ++ if (i2s->variant->has_fmt_set_lrck_period) { ++ int lrck; ++ if (i2s->bit_clk_master) ++ lrck = word_size; ++ else ++ lrck = i2s->mclk_freq / rate / 2; ++ + regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, + SUN8I_I2S_FMT0_LRCK_PERIOD_MASK, +- SUN8I_I2S_FMT0_LRCK_PERIOD(32)); ++ SUN8I_I2S_FMT0_LRCK_PERIOD(lrck)); ++ } ++ ++ /* Set sign extension to pad out LSB with 0 */ ++ regmap_field_write(i2s->field_fmt_sext, 0); + + return 0; + } +@@ -356,43 +414,84 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, + struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); + int sr, wss, channels; + u32 width; ++ int lines; + + channels = params_channels(params); +- if (channels != 2) { +- dev_err(dai->dev, "Unsupported number of channels: %d\n", +- channels); +- return -EINVAL; +- } +- +- if (i2s->variant->has_chcfg) { +- regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, +- SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK, +- SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels)); +- regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, +- SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK, +- SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels)); +- } +- +- /* Map the channels for playback and capture */ +- regmap_field_write(i2s->field_txchanmap, 0x76543210); +- regmap_field_write(i2s->field_rxchanmap, 0x00003210); ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ if ((channels > dai->driver->playback.channels_max) || ++ (channels < dai->driver->playback.channels_min)) { ++ dev_err(dai->dev, "Unsupported number of channels: %d\n", ++ channels); ++ return -EINVAL; ++ } + +- /* Configure the channels */ +- regmap_field_write(i2s->field_txchansel, +- SUN4I_I2S_CHAN_SEL(params_channels(params))); ++ lines = (channels + 1) / 2; + +- regmap_field_write(i2s->field_rxchansel, +- SUN4I_I2S_CHAN_SEL(params_channels(params))); ++ /* Enable the required output lines */ ++ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, ++ SUN4I_I2S_CTRL_SDO_EN_MASK, ++ SUN4I_I2S_CTRL_SDO_EN(lines)); + +- if (i2s->variant->has_chsel_tx_chen) +- regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, +- SUN8I_I2S_TX_CHAN_EN_MASK, +- SUN8I_I2S_TX_CHAN_EN(channels)); ++ if (i2s->variant->has_chcfg) ++ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, ++ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK, ++ SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels)); ++ else ++ /* Configure the channels */ ++ regmap_field_write(i2s->field_txchansel, SUN4I_I2S_CHAN_SEL(channels)); ++ ++ regmap_field_write(i2s->field_txchanmap, 0x10); ++ ++ if (i2s->variant->has_chsel_tx_chen) { ++ u32 chan_sel = SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset) | 0x1; ++ regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, ++ chan_sel | 0x30); ++ ++ if (channels > 2) { ++ regmap_write(i2s->regmap, ++ SUN8I_I2S_TX_CHAN_MAP_REG+4, 0x32); ++ regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG+4, ++ chan_sel | 0xC0); ++ } ++ if (channels > 4) { ++ regmap_write(i2s->regmap, ++ SUN8I_I2S_TX_CHAN_MAP_REG+8, 0x54); ++ regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG+8, ++ chan_sel | 0x300); ++ } ++ if (channels > 6) { ++ regmap_write(i2s->regmap, ++ SUN8I_I2S_TX_CHAN_MAP_REG+12, 0x76); ++ regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG+12, ++ chan_sel | 0xC00); ++ } ++ } ++ } else { ++ /* Map the channels for capture */ ++ regmap_field_write(i2s->field_rxchanmap, 0x00003210); ++ regmap_field_write(i2s->field_rxchansel, ++ SUN4I_I2S_CHAN_SEL(params_channels(params))); ++ ++ if (i2s->variant->has_chcfg) ++ regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG, ++ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK, ++ SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels)); ++ ++ if (i2s->variant->has_chsel_tx_chen) ++ regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG, ++ SUN8I_I2S_TX_CHAN_OFFSET_MASK, ++ SUN8I_I2S_TX_CHAN_OFFSET(i2s->offset)); ++ } + + switch (params_physical_width(params)) { + case 16: + width = DMA_SLAVE_BUSWIDTH_2_BYTES; + break; ++ case 20: ++ case 24: ++ case 32: ++ width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ break; + default: + dev_err(dai->dev, "Unsupported physical sample width: %d\n", + params_physical_width(params)); +@@ -405,7 +504,18 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, + sr = 0; + wss = 0; + break; +- ++ case 20: ++ sr = 1; ++ wss = 1; ++ break; ++ case 24: ++ sr = 2; ++ wss = 2; ++ break; ++ case 32: ++ sr = 4; ++ wss = 4; ++ break; + default: + dev_err(dai->dev, "Unsupported sample width: %d\n", + params_width(params)); +@@ -418,14 +528,14 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, + sr + i2s->variant->fmt_offset); + + return sun4i_i2s_set_clk_rate(dai, params_rate(params), +- params_width(params)); ++ i2s->tdm_slots ? ++ i2s->slot_width : params_width(params)); + } + + static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) + { + struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); + u32 val; +- u32 offset = 0; + u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; + u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL; + +@@ -433,7 +543,7 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + val = SUN4I_I2S_FMT0_FMT_I2S; +- offset = 1; ++ i2s->offset = 1; + break; + case SND_SOC_DAIFMT_LEFT_J: + val = SUN4I_I2S_FMT0_FMT_LEFT_J; +@@ -454,12 +564,8 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) + * i2s shares the same setting with the LJ format. Increment + * val so that the bit to value to write is correct. + */ +- if (offset > 0) ++ if (i2s->offset > 0) + val++; +- /* blck offset determines whether i2s or LJ */ +- regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG, +- SUN8I_I2S_TX_CHAN_OFFSET_MASK, +- SUN8I_I2S_TX_CHAN_OFFSET(offset)); + } + + regmap_field_write(i2s->field_fmt_mode, val); +@@ -496,10 +602,12 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) + case SND_SOC_DAIFMT_CBS_CFS: + /* BCLK and LRCLK master */ + val = SUN4I_I2S_CTRL_MODE_MASTER; ++ i2s->bit_clk_master = true; + break; + case SND_SOC_DAIFMT_CBM_CFM: + /* BCLK and LRCLK slave */ + val = SUN4I_I2S_CTRL_MODE_SLAVE; ++ i2s->bit_clk_master = false; + break; + default: + dev_err(dai->dev, "Unsupported slave setting: %d\n", +@@ -520,10 +628,12 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) + /* BCLK and LRCLK master */ + val = SUN8I_I2S_CTRL_BCLK_OUT | + SUN8I_I2S_CTRL_LRCK_OUT; ++ i2s->bit_clk_master = true; + break; + case SND_SOC_DAIFMT_CBM_CFM: + /* BCLK and LRCLK slave */ + val = 0; ++ i2s->bit_clk_master = false; + break; + default: + dev_err(dai->dev, "Unsupported slave setting: %d\n", +@@ -542,6 +652,7 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) + SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK, + SUN4I_I2S_FIFO_CTRL_TX_MODE(1) | + SUN4I_I2S_FIFO_CTRL_RX_MODE(1)); ++ + return 0; + } + +@@ -564,6 +675,11 @@ static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s) + regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG, + SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN, + SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN); ++ ++ /* Debugging without codec */ ++ if (i2s->loopback) ++ regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, ++ SUN4I_I2S_CTRL_LOOP, SUN4I_I2S_CTRL_LOOP); + } + + static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s) +@@ -657,11 +773,25 @@ static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id, + return 0; + } + ++static int sun4i_i2s_set_dai_tdm_slot(struct snd_soc_dai *dai, ++ unsigned int tx_mask, unsigned int rx_mask, ++ int slots, int width) ++{ ++ struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai); ++ ++ i2s->tdm_slots = slots; ++ ++ i2s->slot_width = width; ++ ++ return 0; ++} ++ + static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = { + .hw_params = sun4i_i2s_hw_params, + .set_fmt = sun4i_i2s_set_fmt, + .set_sysclk = sun4i_i2s_set_sysclk, + .trigger = sun4i_i2s_trigger, ++ .set_tdm_slot = sun4i_i2s_set_dai_tdm_slot, + }; + + static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai) +@@ -677,6 +807,13 @@ static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai) + return 0; + } + ++#define SUN4I_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ ++ SNDRV_PCM_FMTBIT_S20_3LE | \ ++ SNDRV_PCM_FMTBIT_S24_LE) ++ ++#define SUN8I_FORMATS (SUN4I_FORMATS | \ ++ SNDRV_PCM_FMTBIT_S32_LE) ++ + static struct snd_soc_dai_driver sun4i_i2s_dai = { + .probe = sun4i_i2s_dai_probe, + .capture = { +@@ -684,14 +821,14 @@ static struct snd_soc_dai_driver sun4i_i2s_dai = { + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, +- .formats = SNDRV_PCM_FMTBIT_S16_LE, ++ .formats = SUN4I_FORMATS, + }, + .playback = { + .stream_name = "Playback", + .channels_min = 2, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, +- .formats = SNDRV_PCM_FMTBIT_S16_LE, ++ .formats = SUN4I_FORMATS, + }, + .ops = &sun4i_i2s_dai_ops, + .symmetric_rates = 1, +@@ -887,6 +1024,7 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = { + .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), + .has_slave_select_bit = true, + .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), ++ .field_fmt_sext = REG_FIELD(SUN4I_I2S_FMT1_REG, 8, 8), + .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), + .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), + .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), +@@ -904,6 +1042,7 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = { + .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), + .has_slave_select_bit = true, + .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), ++ .field_fmt_sext = REG_FIELD(SUN4I_I2S_FMT1_REG, 8, 8), + .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), + .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), + .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), +@@ -931,8 +1070,6 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { + .has_reset = true, + .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG, + .sun4i_i2s_regmap = &sun8i_i2s_regmap_config, +- .mclk_offset = 1, +- .bclk_offset = 2, + .fmt_offset = 3, + .has_fmt_set_lrck_period = true, + .has_chcfg = true, +@@ -944,6 +1081,7 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = { + .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), + .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19), + .field_fmt_mode = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5), ++ .field_fmt_sext = REG_FIELD(SUN4I_I2S_FMT1_REG, 4, 5), + .field_txchanmap = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31), + .field_rxchanmap = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31), + .field_txchansel = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2), +@@ -961,6 +1099,7 @@ static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = { + .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6), + .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7), + .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1), ++ .field_fmt_sext = REG_FIELD(SUN4I_I2S_FMT1_REG, 8, 8), + .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31), + .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31), + .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2), +@@ -1006,6 +1145,12 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev, + if (IS_ERR(i2s->field_fmt_mode)) + return PTR_ERR(i2s->field_fmt_mode); + ++ i2s->field_fmt_sext = ++ devm_regmap_field_alloc(dev, i2s->regmap, ++ i2s->variant->field_fmt_sext); ++ if (IS_ERR(i2s->field_fmt_sext)) ++ return PTR_ERR(i2s->field_fmt_sext); ++ + i2s->field_txchanmap = + devm_regmap_field_alloc(dev, i2s->regmap, + i2s->variant->field_txchanmap); +@@ -1033,9 +1178,10 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev, + static int sun4i_i2s_probe(struct platform_device *pdev) + { + struct sun4i_i2s *i2s; ++ struct snd_soc_dai_driver *soc_dai; + struct resource *res; + void __iomem *regs; +- int irq, ret; ++ int irq, ret, val; + + i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); + if (!i2s) +@@ -1102,6 +1248,28 @@ static int sun4i_i2s_probe(struct platform_device *pdev) + i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG; + i2s->capture_dma_data.maxburst = 8; + ++ soc_dai = devm_kmemdup(&pdev->dev, &sun4i_i2s_dai, ++ sizeof(*soc_dai), GFP_KERNEL); ++ if (!soc_dai) { ++ ret = -ENOMEM; ++ goto err_pm_disable; ++ } ++ ++ if (i2s->variant->has_fmt_set_lrck_period) { ++ soc_dai->playback.formats = SUN8I_FORMATS; ++ soc_dai->capture.formats = SUN8I_FORMATS; ++ } ++ ++ if (!of_property_read_u32(pdev->dev.of_node, ++ "allwinner,playback-channels", &val)) { ++ dev_err(&pdev->dev, "Max playback channels changed from %d to %d\n", soc_dai->playback.channels_max, val); ++ if (val >= 2 && val <= 8) ++ soc_dai->playback.channels_max = val; ++ } ++ ++ if (of_property_read_bool(pdev->dev.of_node, "loopback")) ++ i2s->loopback = true; ++ + pm_runtime_enable(&pdev->dev); + if (!pm_runtime_enabled(&pdev->dev)) { + ret = sun4i_i2s_runtime_resume(&pdev->dev); +@@ -1111,7 +1279,7 @@ static int sun4i_i2s_probe(struct platform_device *pdev) + + ret = devm_snd_soc_register_component(&pdev->dev, + &sun4i_i2s_component, +- &sun4i_i2s_dai, 1); ++ soc_dai, 1); + if (ret) { + dev_err(&pdev->dev, "Could not register DAI\n"); + goto err_suspend; +-- +2.20.0 + + +From a5a9334b7830f1ef8d3f10221c067aeeaa24b12f Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 16 Dec 2018 15:00:59 +0100 +Subject: [PATCH 14/15] ASoC: sun4i-i2s: multichannel updates fixes + +--- + sound/soc/sunxi/sun4i-i2s.c | 20 +++++++++++++------- + 1 file changed, 13 insertions(+), 7 deletions(-) + +diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c +index 2e3fc596ab64..c0805bd928bf 100644 +--- a/sound/soc/sunxi/sun4i-i2s.c ++++ b/sound/soc/sunxi/sun4i-i2s.c +@@ -451,19 +451,19 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, + regmap_write(i2s->regmap, + SUN8I_I2S_TX_CHAN_MAP_REG+4, 0x32); + regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG+4, +- chan_sel | 0xC0); ++ chan_sel | 0x30); + } + if (channels > 4) { + regmap_write(i2s->regmap, + SUN8I_I2S_TX_CHAN_MAP_REG+8, 0x54); + regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG+8, +- chan_sel | 0x300); ++ chan_sel | 0x30); + } + if (channels > 6) { + regmap_write(i2s->regmap, + SUN8I_I2S_TX_CHAN_MAP_REG+12, 0x76); + regmap_write(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG+12, +- chan_sel | 0xC00); ++ chan_sel | 0x30); + } + } + } else { +@@ -659,9 +659,11 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) + static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s) + { + /* Flush RX FIFO */ ++ regcache_cache_bypass(i2s->regmap, true); + regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, + SUN4I_I2S_FIFO_CTRL_FLUSH_RX, + SUN4I_I2S_FIFO_CTRL_FLUSH_RX); ++ regcache_cache_bypass(i2s->regmap, false); + + /* Clear RX counter */ + regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0); +@@ -685,9 +687,11 @@ static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s) + static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s) + { + /* Flush TX FIFO */ ++ regcache_cache_bypass(i2s->regmap, true); + regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, + SUN4I_I2S_FIFO_CTRL_FLUSH_TX, + SUN4I_I2S_FIFO_CTRL_FLUSH_TX); ++ regcache_cache_bypass(i2s->regmap, false); + + /* Clear TX counter */ + regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0); +@@ -842,7 +846,7 @@ static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg) + { + switch (reg) { + case SUN4I_I2S_FIFO_TX_REG: +- return false; ++ return true; + + default: + return true; +@@ -865,6 +869,8 @@ static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg) + { + switch (reg) { + case SUN4I_I2S_FIFO_RX_REG: ++ case SUN4I_I2S_FIFO_TX_REG: ++ case SUN4I_I2S_FIFO_STA_REG: + case SUN4I_I2S_INT_STA_REG: + case SUN4I_I2S_RX_CNT_REG: + case SUN4I_I2S_TX_CNT_REG: +@@ -879,7 +885,7 @@ static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg) + { + switch (reg) { + case SUN8I_I2S_FIFO_TX_REG: +- return false; ++ return true; + + default: + return true; +@@ -891,7 +897,7 @@ static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg) + if (reg == SUN8I_I2S_INT_STA_REG) + return true; + if (reg == SUN8I_I2S_FIFO_TX_REG) +- return false; ++ return true; + + return sun4i_i2s_volatile_reg(dev, reg); + } +@@ -977,7 +983,7 @@ static int sun4i_i2s_runtime_resume(struct device *dev) + /* Enable the first output line */ + regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG, + SUN4I_I2S_CTRL_SDO_EN_MASK, +- SUN4I_I2S_CTRL_SDO_EN(0)); ++ SUN4I_I2S_CTRL_SDO_EN(1)); + + ret = clk_prepare_enable(i2s->mod_clk); + if (ret) { +-- +2.20.0 + + +From 7319e6b5ff8af1e23a669c235d5e1a3b165d8cd6 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 16 Dec 2018 20:31:25 +0100 +Subject: [PATCH 15/15] fixup! drm: dw-hdmi: add dw_hdmi_update_eld() callback + +--- + sound/soc/codecs/hdmi-codec.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c +index dc84bfbe7e87..eac79b2e123c 100644 +--- a/sound/soc/codecs/hdmi-codec.c ++++ b/sound/soc/codecs/hdmi-codec.c +@@ -684,7 +684,9 @@ void hdmi_codec_eld_notify(struct device *dev) + struct hdmi_codec_priv *hcp = dev_get_drvdata(dev); + struct snd_ctl_elem_id id; + +- if (!hcp->snd_card || !hcp->kctl) ++ if (!hcp || ++ !hcp->snd_card || ++ !hcp->kctl) + return; + + id = hcp->kctl->id; +-- +2.20.0 + diff --git a/projects/Allwinner/patches/linux/0002-fixes-from-5.1.patch b/projects/Allwinner/patches/linux/0002-fixes-from-5.1.patch new file mode 100644 index 0000000000..cab57cac3b --- /dev/null +++ b/projects/Allwinner/patches/linux/0002-fixes-from-5.1.patch @@ -0,0 +1,1824 @@ +From e2d8ffe2e76028457759988ba6216fd13eeea01b Mon Sep 17 00:00:00 2001 +From: Hans Verkuil +Date: Tue, 13 Nov 2018 03:52:18 -0500 +Subject: [PATCH] media: v4l2-mem2mem: add v4l2_m2m_buf_copy_data helper + function + +Memory-to-memory devices should copy various parts of +struct v4l2_buffer from the output buffer to the capture buffer. + +Add a helper function that does that to simplify the driver code. + +Signed-off-by: Hans Verkuil +Reviewed-by: Paul Kocialkowski +Reviewed-by: Alexandre Courbot +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/v4l2-core/v4l2-mem2mem.c | 20 ++++++++++++++++++++ + include/media/v4l2-mem2mem.h | 20 ++++++++++++++++++++ + 2 files changed, 40 insertions(+) + +diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c +index 5bbdec55b7d7..631f4e2aa942 100644 +--- a/drivers/media/v4l2-core/v4l2-mem2mem.c ++++ b/drivers/media/v4l2-core/v4l2-mem2mem.c +@@ -975,6 +975,26 @@ void v4l2_m2m_buf_queue(struct v4l2_m2m_ctx *m2m_ctx, + } + EXPORT_SYMBOL_GPL(v4l2_m2m_buf_queue); + ++void v4l2_m2m_buf_copy_data(const struct vb2_v4l2_buffer *out_vb, ++ struct vb2_v4l2_buffer *cap_vb, ++ bool copy_frame_flags) ++{ ++ u32 mask = V4L2_BUF_FLAG_TIMECODE | V4L2_BUF_FLAG_TSTAMP_SRC_MASK; ++ ++ if (copy_frame_flags) ++ mask |= V4L2_BUF_FLAG_KEYFRAME | V4L2_BUF_FLAG_PFRAME | ++ V4L2_BUF_FLAG_BFRAME; ++ ++ cap_vb->vb2_buf.timestamp = out_vb->vb2_buf.timestamp; ++ ++ if (out_vb->flags & V4L2_BUF_FLAG_TIMECODE) ++ cap_vb->timecode = out_vb->timecode; ++ cap_vb->field = out_vb->field; ++ cap_vb->flags &= ~mask; ++ cap_vb->flags |= out_vb->flags & mask; ++} ++EXPORT_SYMBOL_GPL(v4l2_m2m_buf_copy_data); ++ + void v4l2_m2m_request_queue(struct media_request *req) + { + struct media_request_object *obj, *obj_safe; +diff --git a/include/media/v4l2-mem2mem.h b/include/media/v4l2-mem2mem.h +index 5467264771ec..43e447dcf69d 100644 +--- a/include/media/v4l2-mem2mem.h ++++ b/include/media/v4l2-mem2mem.h +@@ -622,6 +622,26 @@ v4l2_m2m_dst_buf_remove_by_idx(struct v4l2_m2m_ctx *m2m_ctx, unsigned int idx) + return v4l2_m2m_buf_remove_by_idx(&m2m_ctx->cap_q_ctx, idx); + } + ++/** ++ * v4l2_m2m_buf_copy_data() - copy buffer data from the output buffer to the ++ * capture buffer ++ * ++ * @out_vb: the output buffer that is the source of the data. ++ * @cap_vb: the capture buffer that will receive the data. ++ * @copy_frame_flags: copy the KEY/B/PFRAME flags as well. ++ * ++ * This helper function copies the timestamp, timecode (if the TIMECODE ++ * buffer flag was set), field and the TIMECODE, KEYFRAME, BFRAME, PFRAME ++ * and TSTAMP_SRC_MASK flags from @out_vb to @cap_vb. ++ * ++ * If @copy_frame_flags is false, then the KEYFRAME, BFRAME and PFRAME ++ * flags are not copied. This is typically needed for encoders that ++ * set this bits explicitly. ++ */ ++void v4l2_m2m_buf_copy_data(const struct vb2_v4l2_buffer *out_vb, ++ struct vb2_v4l2_buffer *cap_vb, ++ bool copy_frame_flags); ++ + /* v4l2 request helper */ + + void v4l2_m2m_request_queue(struct media_request *req); +-- +2.20.1 + +From c2eb8effb265ac5cdd960d8e61ecb931e9c767cd Mon Sep 17 00:00:00 2001 +From: Hans Verkuil +Date: Wed, 24 Oct 2018 06:50:34 -0400 +Subject: [PATCH] media: videodev2.h: add v4l2_timeval_to_ns inline function + +We want to be able to uniquely identify buffers for stateless +codecs. The internal timestamp (a u64) as stored internally in the +kernel is a suitable candidate for that, but in struct v4l2_buffer +it is represented as a struct timeval. + +Add a v4l2_timeval_to_ns() function that converts the struct timeval +into a u64 in the same way that the kernel does. This makes it possible +to use this u64 elsewhere as a unique identifier of the buffer. + +Since timestamps are also copied from the output buffer to the +corresponding capture buffer(s) by M2M devices, the u64 can be +used to refer to both output and capture buffers. + +The plan is that in the future we redesign struct v4l2_buffer and use +u64 for the timestamp instead of a struct timeval (which has lots of +problems with 32 vs 64 bit and y2038 layout changes), and then there +is no more need to use this function. + +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + include/uapi/linux/videodev2.h | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h +index b5671ce2724f..d6eed479c3a6 100644 +--- a/include/uapi/linux/videodev2.h ++++ b/include/uapi/linux/videodev2.h +@@ -973,6 +973,18 @@ struct v4l2_buffer { + }; + }; + ++/** ++ * v4l2_timeval_to_ns - Convert timeval to nanoseconds ++ * @ts: pointer to the timeval variable to be converted ++ * ++ * Returns the scalar nanosecond representation of the timeval ++ * parameter. ++ */ ++static inline __u64 v4l2_timeval_to_ns(const struct timeval *tv) ++{ ++ return (__u64)tv->tv_sec * 1000000000ULL + tv->tv_usec * 1000; ++} ++ + /* Flags for 'flags' field */ + /* Buffer is mapped (flag) */ + #define V4L2_BUF_FLAG_MAPPED 0x00000001 +-- +2.20.1 + +From 245ede423b43a6e081e94e0e5d4e895bd1f31228 Mon Sep 17 00:00:00 2001 +From: Hans Verkuil +Date: Wed, 24 Oct 2018 06:51:01 -0400 +Subject: [PATCH] media: vb2: add vb2_find_timestamp() + +Use v4l2_timeval_to_ns instead of timeval_to_ns to ensure that +both kernelspace and userspace will use the same conversion +function. + +Next add a new vb2_find_timestamp() function to find buffers +with a specific timestamp. + +This function will only look at DEQUEUED and DONE buffers, i.e. +buffers that are already processed. + +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + .../media/common/videobuf2/videobuf2-v4l2.c | 19 ++++++++++++++++++- + include/media/videobuf2-v4l2.h | 17 +++++++++++++++++ + 2 files changed, 35 insertions(+), 1 deletion(-) + +diff --git a/drivers/media/common/videobuf2/videobuf2-v4l2.c b/drivers/media/common/videobuf2/videobuf2-v4l2.c +index 3a0ca2f9854f..75ea90e795d8 100644 +--- a/drivers/media/common/videobuf2/videobuf2-v4l2.c ++++ b/drivers/media/common/videobuf2/videobuf2-v4l2.c +@@ -143,7 +143,7 @@ static void __copy_timestamp(struct vb2_buffer *vb, const void *pb) + * and the timecode field and flag if needed. + */ + if (q->copy_timestamp) +- vb->timestamp = timeval_to_ns(&b->timestamp); ++ vb->timestamp = v4l2_timeval_to_ns(&b->timestamp); + vbuf->flags |= b->flags & V4L2_BUF_FLAG_TIMECODE; + if (b->flags & V4L2_BUF_FLAG_TIMECODE) + vbuf->timecode = b->timecode; +@@ -589,6 +589,23 @@ static const struct vb2_buf_ops v4l2_buf_ops = { + .copy_timestamp = __copy_timestamp, + }; + ++int vb2_find_timestamp(const struct vb2_queue *q, u64 timestamp, ++ unsigned int start_idx) ++{ ++ unsigned int i; ++ ++ for (i = start_idx; i < q->num_buffers; i++) { ++ struct vb2_buffer *vb = q->bufs[i]; ++ ++ if ((vb->state == VB2_BUF_STATE_DEQUEUED || ++ vb->state == VB2_BUF_STATE_DONE) && ++ vb->timestamp == timestamp) ++ return i; ++ } ++ return -1; ++} ++EXPORT_SYMBOL_GPL(vb2_find_timestamp); ++ + /* + * vb2_querybuf() - query video buffer information + * @q: videobuf queue +diff --git a/include/media/videobuf2-v4l2.h b/include/media/videobuf2-v4l2.h +index 727855463838..a9961bc776dc 100644 +--- a/include/media/videobuf2-v4l2.h ++++ b/include/media/videobuf2-v4l2.h +@@ -55,6 +55,23 @@ struct vb2_v4l2_buffer { + #define to_vb2_v4l2_buffer(vb) \ + container_of(vb, struct vb2_v4l2_buffer, vb2_buf) + ++/** ++ * vb2_find_timestamp() - Find buffer with given timestamp in the queue ++ * ++ * @q: pointer to &struct vb2_queue with videobuf2 queue. ++ * @timestamp: the timestamp to find. Only buffers in state DEQUEUED or DONE ++ * are considered. ++ * @start_idx: the start index (usually 0) in the buffer array to start ++ * searching from. Note that there may be multiple buffers ++ * with the same timestamp value, so you can restart the search ++ * by setting @start_idx to the previously found index + 1. ++ * ++ * Returns the buffer index of the buffer with the given @timestamp, or ++ * -1 if no buffer with @timestamp was found. ++ */ ++int vb2_find_timestamp(const struct vb2_queue *q, u64 timestamp, ++ unsigned int start_idx); ++ + int vb2_querybuf(struct vb2_queue *q, struct v4l2_buffer *b); + + /** +-- +2.20.1 + +From d998e03e322fc497454f584adfc35743713a44c5 Mon Sep 17 00:00:00 2001 +From: Hans Verkuil +Date: Fri, 9 Nov 2018 04:16:21 -0500 +Subject: [PATCH] media: cedrus: identify buffers by timestamp + +Use the new v4l2_m2m_buf_copy_data helper function and use +timestamps to refer to reference frames instead of using +buffer indices. + +Also remove the padding fields in the structs, that's a bad +idea. Just use the right types to keep everything aligned. + +Signed-off-by: Hans Verkuil +Tested-by: Paul Kocialkowski +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/v4l2-core/v4l2-ctrls.c | 9 -------- + drivers/staging/media/sunxi/cedrus/cedrus.h | 9 +++++--- + .../staging/media/sunxi/cedrus/cedrus_dec.c | 2 ++ + .../staging/media/sunxi/cedrus/cedrus_mpeg2.c | 23 +++++++++---------- + include/media/mpeg2-ctrls.h | 14 ++++------- + 5 files changed, 24 insertions(+), 33 deletions(-) + +diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c +index 5e3806feb5d7..e3bd441fa29a 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls.c +@@ -1661,15 +1661,6 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, + return -EINVAL; + } + +- if (p_mpeg2_slice_params->backward_ref_index >= VIDEO_MAX_FRAME || +- p_mpeg2_slice_params->forward_ref_index >= VIDEO_MAX_FRAME) +- return -EINVAL; +- +- if (p_mpeg2_slice_params->pad || +- p_mpeg2_slice_params->picture.pad || +- p_mpeg2_slice_params->sequence.pad) +- return -EINVAL; +- + return 0; + + case V4L2_CTRL_TYPE_MPEG2_QUANTIZATION: +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h +index 3acfdcf83691..4aedd24a9848 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h +@@ -140,11 +140,14 @@ static inline dma_addr_t cedrus_buf_addr(struct vb2_buffer *buf, + } + + static inline dma_addr_t cedrus_dst_buf_addr(struct cedrus_ctx *ctx, +- unsigned int index, +- unsigned int plane) ++ int index, unsigned int plane) + { +- struct vb2_buffer *buf = ctx->dst_bufs[index]; ++ struct vb2_buffer *buf; + ++ if (index < 0) ++ return 0; ++ ++ buf = ctx->dst_bufs[index]; + return buf ? cedrus_buf_addr(buf, &ctx->dst_fmt, plane) : 0; + } + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +index 591d191d4286..443fb037e1cf 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +@@ -50,6 +50,8 @@ void cedrus_device_run(void *priv) + break; + } + ++ v4l2_m2m_buf_copy_data(run.src, run.dst, true); ++ + dev->dec_ops[ctx->current_codec]->setup(ctx, &run); + + /* Complete request(s) controls if needed. */ +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c b/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c +index 9abd39cae38c..cb45fda9aaeb 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c +@@ -82,7 +82,10 @@ static void cedrus_mpeg2_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) + dma_addr_t fwd_luma_addr, fwd_chroma_addr; + dma_addr_t bwd_luma_addr, bwd_chroma_addr; + struct cedrus_dev *dev = ctx->dev; ++ struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; + const u8 *matrix; ++ int forward_idx; ++ int backward_idx; + unsigned int i; + u32 reg; + +@@ -156,23 +159,19 @@ static void cedrus_mpeg2_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) + cedrus_write(dev, VE_DEC_MPEG_PICBOUNDSIZE, reg); + + /* Forward and backward prediction reference buffers. */ ++ forward_idx = vb2_find_timestamp(cap_q, ++ slice_params->forward_ref_ts, 0); + +- fwd_luma_addr = cedrus_dst_buf_addr(ctx, +- slice_params->forward_ref_index, +- 0); +- fwd_chroma_addr = cedrus_dst_buf_addr(ctx, +- slice_params->forward_ref_index, +- 1); ++ fwd_luma_addr = cedrus_dst_buf_addr(ctx, forward_idx, 0); ++ fwd_chroma_addr = cedrus_dst_buf_addr(ctx, forward_idx, 1); + + cedrus_write(dev, VE_DEC_MPEG_FWD_REF_LUMA_ADDR, fwd_luma_addr); + cedrus_write(dev, VE_DEC_MPEG_FWD_REF_CHROMA_ADDR, fwd_chroma_addr); + +- bwd_luma_addr = cedrus_dst_buf_addr(ctx, +- slice_params->backward_ref_index, +- 0); +- bwd_chroma_addr = cedrus_dst_buf_addr(ctx, +- slice_params->backward_ref_index, +- 1); ++ backward_idx = vb2_find_timestamp(cap_q, ++ slice_params->backward_ref_ts, 0); ++ bwd_luma_addr = cedrus_dst_buf_addr(ctx, backward_idx, 0); ++ bwd_chroma_addr = cedrus_dst_buf_addr(ctx, backward_idx, 1); + + cedrus_write(dev, VE_DEC_MPEG_BWD_REF_LUMA_ADDR, bwd_luma_addr); + cedrus_write(dev, VE_DEC_MPEG_BWD_REF_CHROMA_ADDR, bwd_chroma_addr); +diff --git a/include/media/mpeg2-ctrls.h b/include/media/mpeg2-ctrls.h +index d21f40edc09e..6601455b3d5e 100644 +--- a/include/media/mpeg2-ctrls.h ++++ b/include/media/mpeg2-ctrls.h +@@ -30,10 +30,9 @@ struct v4l2_mpeg2_sequence { + __u32 vbv_buffer_size; + + /* ISO/IEC 13818-2, ITU-T Rec. H.262: Sequence extension */ +- __u8 profile_and_level_indication; ++ __u16 profile_and_level_indication; + __u8 progressive_sequence; + __u8 chroma_format; +- __u8 pad; + }; + + struct v4l2_mpeg2_picture { +@@ -51,23 +50,20 @@ struct v4l2_mpeg2_picture { + __u8 intra_vlc_format; + __u8 alternate_scan; + __u8 repeat_first_field; +- __u8 progressive_frame; +- __u8 pad; ++ __u16 progressive_frame; + }; + + struct v4l2_ctrl_mpeg2_slice_params { + __u32 bit_size; + __u32 data_bit_offset; ++ __u64 backward_ref_ts; ++ __u64 forward_ref_ts; + + struct v4l2_mpeg2_sequence sequence; + struct v4l2_mpeg2_picture picture; + + /* ISO/IEC 13818-2, ITU-T Rec. H.262: Slice */ +- __u8 quantiser_scale_code; +- +- __u8 backward_ref_index; +- __u8 forward_ref_index; +- __u8 pad; ++ __u32 quantiser_scale_code; + }; + + struct v4l2_ctrl_mpeg2_quantization { +-- +2.20.1 + +From 03535e7a3a9937da99ee18304309e0574d2504fc Mon Sep 17 00:00:00 2001 +From: Hans Verkuil +Date: Thu, 24 Jan 2019 06:47:49 -0200 +Subject: [PATCH] media: vb2: vb2_find_timestamp: drop restriction on buffer + state + +There really is no reason why vb2_find_timestamp can't just find +buffers in any state. Drop that part of the test. + +This also means that vb->timestamp should only be set to 0 when +the driver doesn't copy timestamps. + +This change allows for more efficient pipelining (i.e. you can use +a buffer for a reference frame even when it is queued). + +Signed-off-by: Hans Verkuil +Reviewed-by: Tomasz Figa +Reviewed-by: Alexandre Courbot +Reviewed-by: Paul Kocialkowski +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/common/videobuf2/videobuf2-v4l2.c | 11 +++-------- + include/media/videobuf2-v4l2.h | 3 +-- + 2 files changed, 4 insertions(+), 10 deletions(-) + +diff --git a/drivers/media/common/videobuf2/videobuf2-v4l2.c b/drivers/media/common/videobuf2/videobuf2-v4l2.c +index 75ea90e795d8..2f3b3ca5bde6 100644 +--- a/drivers/media/common/videobuf2/videobuf2-v4l2.c ++++ b/drivers/media/common/videobuf2/videobuf2-v4l2.c +@@ -567,7 +567,7 @@ static int __fill_vb2_buffer(struct vb2_buffer *vb, struct vb2_plane *planes) + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + unsigned int plane; + +- if (!vb->vb2_queue->is_output || !vb->vb2_queue->copy_timestamp) ++ if (!vb->vb2_queue->copy_timestamp) + vb->timestamp = 0; + + for (plane = 0; plane < vb->num_planes; ++plane) { +@@ -594,14 +594,9 @@ int vb2_find_timestamp(const struct vb2_queue *q, u64 timestamp, + { + unsigned int i; + +- for (i = start_idx; i < q->num_buffers; i++) { +- struct vb2_buffer *vb = q->bufs[i]; +- +- if ((vb->state == VB2_BUF_STATE_DEQUEUED || +- vb->state == VB2_BUF_STATE_DONE) && +- vb->timestamp == timestamp) ++ for (i = start_idx; i < q->num_buffers; i++) ++ if (q->bufs[i]->timestamp == timestamp) + return i; +- } + return -1; + } + EXPORT_SYMBOL_GPL(vb2_find_timestamp); +diff --git a/include/media/videobuf2-v4l2.h b/include/media/videobuf2-v4l2.h +index a9961bc776dc..8a10889dc2fd 100644 +--- a/include/media/videobuf2-v4l2.h ++++ b/include/media/videobuf2-v4l2.h +@@ -59,8 +59,7 @@ struct vb2_v4l2_buffer { + * vb2_find_timestamp() - Find buffer with given timestamp in the queue + * + * @q: pointer to &struct vb2_queue with videobuf2 queue. +- * @timestamp: the timestamp to find. Only buffers in state DEQUEUED or DONE +- * are considered. ++ * @timestamp: the timestamp to find. + * @start_idx: the start index (usually 0) in the buffer array to start + * searching from. Note that there may be multiple buffers + * with the same timestamp value, so you can restart the search +-- +2.20.1 + +From 2cc1802f62e562611e86f04d9dae1337c824991e Mon Sep 17 00:00:00 2001 +From: Pawel Osciak +Date: Thu, 24 Jan 2019 07:51:55 -0200 +Subject: [PATCH] media: vb2: Keep dma-buf buffers mapped until they are freed + +When using vb2 for video decoding, dequeued capture buffers may still +be accessed by the hardware: this is the case when they are used as +reference frames for decoding subsequent frames. + +When the buffer is imported with dma-buf, it needs to be mapped before +access. Until now, it was mapped when queuing and unmapped when +dequeuing, which doesn't work for access as a reference frames. + +One way to solve this would be to map the buffer again when it is +needed as a reference, but the mapping/unmapping operations can +seriously impact performance. As a result, map the buffer once (when it +is first needed when queued) and keep it mapped until it is freed. + +Reviewed-on: https://chromium-review.googlesource.com/334103 +[Paul: Updated for mainline and changed commit message] + +Signed-off-by: Pawel Osciak +Signed-off-by: Paul Kocialkowski +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/common/videobuf2/videobuf2-core.c | 11 +++-------- + 1 file changed, 3 insertions(+), 8 deletions(-) + +diff --git a/drivers/media/common/videobuf2/videobuf2-core.c b/drivers/media/common/videobuf2/videobuf2-core.c +index 70e8c3366f9c..ce9294a635cc 100644 +--- a/drivers/media/common/videobuf2/videobuf2-core.c ++++ b/drivers/media/common/videobuf2/videobuf2-core.c +@@ -1196,6 +1196,9 @@ static int __prepare_dmabuf(struct vb2_buffer *vb) + * userspace knows sooner rather than later if the dma-buf map fails. + */ + for (plane = 0; plane < vb->num_planes; ++plane) { ++ if (vb->planes[plane].dbuf_mapped) ++ continue; ++ + ret = call_memop(vb, map_dmabuf, vb->planes[plane].mem_priv); + if (ret) { + dprintk(1, "failed to map dmabuf for plane %d\n", +@@ -1758,14 +1761,6 @@ static void __vb2_dqbuf(struct vb2_buffer *vb) + + vb->state = VB2_BUF_STATE_DEQUEUED; + +- /* unmap DMABUF buffer */ +- if (q->memory == VB2_MEMORY_DMABUF) +- for (i = 0; i < vb->num_planes; ++i) { +- if (!vb->planes[i].dbuf_mapped) +- continue; +- call_void_memop(vb, unmap_dmabuf, vb->planes[i].mem_priv); +- vb->planes[i].dbuf_mapped = 0; +- } + call_void_bufop(q, init_buffer, vb); + } + +-- +2.20.1 + +From 6f2c6afa79e0513d339871337bfc8c6c621d3ab1 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Fri, 21 Dec 2018 11:56:41 -0500 +Subject: [PATCH] media: sunxi: cedrus: Fix missing error message context + +When cedrus_hw_probe is called, v4l2_dev is not yet initialized. +Use dev_err instead. + +Signed-off-by: Ondrej Jirman +Acked-by: Paul Kocialkowski +Signed-off-by: Mauro Carvalho Chehab +--- + .../staging/media/sunxi/cedrus/cedrus_hw.c | 28 +++++++++---------- + 1 file changed, 14 insertions(+), 14 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +index 300339fee1bc..0acf219a8c91 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +@@ -157,14 +157,14 @@ int cedrus_hw_probe(struct cedrus_dev *dev) + + irq_dec = platform_get_irq(dev->pdev, 0); + if (irq_dec <= 0) { +- v4l2_err(&dev->v4l2_dev, "Failed to get IRQ\n"); ++ dev_err(dev->dev, "Failed to get IRQ\n"); + + return irq_dec; + } + ret = devm_request_irq(dev->dev, irq_dec, cedrus_irq, + 0, dev_name(dev->dev), dev); + if (ret) { +- v4l2_err(&dev->v4l2_dev, "Failed to request IRQ\n"); ++ dev_err(dev->dev, "Failed to request IRQ\n"); + + return ret; + } +@@ -182,21 +182,21 @@ int cedrus_hw_probe(struct cedrus_dev *dev) + + ret = of_reserved_mem_device_init(dev->dev); + if (ret && ret != -ENODEV) { +- v4l2_err(&dev->v4l2_dev, "Failed to reserve memory\n"); ++ dev_err(dev->dev, "Failed to reserve memory\n"); + + return ret; + } + + ret = sunxi_sram_claim(dev->dev); + if (ret) { +- v4l2_err(&dev->v4l2_dev, "Failed to claim SRAM\n"); ++ dev_err(dev->dev, "Failed to claim SRAM\n"); + + goto err_mem; + } + + dev->ahb_clk = devm_clk_get(dev->dev, "ahb"); + if (IS_ERR(dev->ahb_clk)) { +- v4l2_err(&dev->v4l2_dev, "Failed to get AHB clock\n"); ++ dev_err(dev->dev, "Failed to get AHB clock\n"); + + ret = PTR_ERR(dev->ahb_clk); + goto err_sram; +@@ -204,7 +204,7 @@ int cedrus_hw_probe(struct cedrus_dev *dev) + + dev->mod_clk = devm_clk_get(dev->dev, "mod"); + if (IS_ERR(dev->mod_clk)) { +- v4l2_err(&dev->v4l2_dev, "Failed to get MOD clock\n"); ++ dev_err(dev->dev, "Failed to get MOD clock\n"); + + ret = PTR_ERR(dev->mod_clk); + goto err_sram; +@@ -212,7 +212,7 @@ int cedrus_hw_probe(struct cedrus_dev *dev) + + dev->ram_clk = devm_clk_get(dev->dev, "ram"); + if (IS_ERR(dev->ram_clk)) { +- v4l2_err(&dev->v4l2_dev, "Failed to get RAM clock\n"); ++ dev_err(dev->dev, "Failed to get RAM clock\n"); + + ret = PTR_ERR(dev->ram_clk); + goto err_sram; +@@ -220,7 +220,7 @@ int cedrus_hw_probe(struct cedrus_dev *dev) + + dev->rstc = devm_reset_control_get(dev->dev, NULL); + if (IS_ERR(dev->rstc)) { +- v4l2_err(&dev->v4l2_dev, "Failed to get reset control\n"); ++ dev_err(dev->dev, "Failed to get reset control\n"); + + ret = PTR_ERR(dev->rstc); + goto err_sram; +@@ -229,7 +229,7 @@ int cedrus_hw_probe(struct cedrus_dev *dev) + res = platform_get_resource(dev->pdev, IORESOURCE_MEM, 0); + dev->base = devm_ioremap_resource(dev->dev, res); + if (IS_ERR(dev->base)) { +- v4l2_err(&dev->v4l2_dev, "Failed to map registers\n"); ++ dev_err(dev->dev, "Failed to map registers\n"); + + ret = PTR_ERR(dev->base); + goto err_sram; +@@ -237,35 +237,35 @@ int cedrus_hw_probe(struct cedrus_dev *dev) + + ret = clk_set_rate(dev->mod_clk, CEDRUS_CLOCK_RATE_DEFAULT); + if (ret) { +- v4l2_err(&dev->v4l2_dev, "Failed to set clock rate\n"); ++ dev_err(dev->dev, "Failed to set clock rate\n"); + + goto err_sram; + } + + ret = clk_prepare_enable(dev->ahb_clk); + if (ret) { +- v4l2_err(&dev->v4l2_dev, "Failed to enable AHB clock\n"); ++ dev_err(dev->dev, "Failed to enable AHB clock\n"); + + goto err_sram; + } + + ret = clk_prepare_enable(dev->mod_clk); + if (ret) { +- v4l2_err(&dev->v4l2_dev, "Failed to enable MOD clock\n"); ++ dev_err(dev->dev, "Failed to enable MOD clock\n"); + + goto err_ahb_clk; + } + + ret = clk_prepare_enable(dev->ram_clk); + if (ret) { +- v4l2_err(&dev->v4l2_dev, "Failed to enable RAM clock\n"); ++ dev_err(dev->dev, "Failed to enable RAM clock\n"); + + goto err_mod_clk; + } + + ret = reset_control_reset(dev->rstc); + if (ret) { +- v4l2_err(&dev->v4l2_dev, "Failed to apply reset\n"); ++ dev_err(dev->dev, "Failed to apply reset\n"); + + goto err_ram_clk; + } +-- +2.20.1 + +From 6f4b9d9a6c08f692f627700c2d0e250e406ac81f Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski +Date: Wed, 9 Jan 2019 12:19:19 -0200 +Subject: [PATCH] media: cedrus: Cleanup duplicate declarations from cedrus_dec + header + +Some leftover declarations are still in the cedrus_dec header although +they were moved to cedrus_video already. Clean them up. + +Signed-off-by: Paul Kocialkowski +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/staging/media/sunxi/cedrus/cedrus_dec.h | 6 ------ + 1 file changed, 6 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.h b/drivers/staging/media/sunxi/cedrus/cedrus_dec.h +index 4f423d3a1cad..d1ae7903677b 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.h +@@ -16,12 +16,6 @@ + #ifndef _CEDRUS_DEC_H_ + #define _CEDRUS_DEC_H_ + +-extern const struct v4l2_ioctl_ops cedrus_ioctl_ops; +- +-void cedrus_device_work(struct work_struct *work); + void cedrus_device_run(void *priv); + +-int cedrus_queue_init(void *priv, struct vb2_queue *src_vq, +- struct vb2_queue *dst_vq); +- + #endif +-- +2.20.1 + +From 55ea54441fb3b6532d5d32417911ff5a10750903 Mon Sep 17 00:00:00 2001 +From: Christoph Hellwig +Date: Fri, 4 Jan 2019 10:42:49 +0100 +Subject: [PATCH] videobuf2: replace a layering violation with dma_map_resource + +vb2_dc_get_userptr pokes into arm direct mapping details to get the +resemblance of a dma address for a a physical address that does is +not backed by a page struct. Not only is this not portable to other +architectures with dma direct mapping offsets, but also not to uses +of IOMMUs of any kind. Switch to the proper dma_map_resource / +dma_unmap_resource interface instead. + +Signed-off-by: Christoph Hellwig +Acked-by: Mauro Carvalho Chehab +Tested-by: Marek Szyprowski +--- + .../common/videobuf2/videobuf2-dma-contig.c | 41 ++++--------------- + 1 file changed, 9 insertions(+), 32 deletions(-) + +diff --git a/drivers/media/common/videobuf2/videobuf2-dma-contig.c b/drivers/media/common/videobuf2/videobuf2-dma-contig.c +index aff0ab7bf83d..82389aead6ed 100644 +--- a/drivers/media/common/videobuf2/videobuf2-dma-contig.c ++++ b/drivers/media/common/videobuf2/videobuf2-dma-contig.c +@@ -439,42 +439,14 @@ static void vb2_dc_put_userptr(void *buf_priv) + set_page_dirty_lock(pages[i]); + sg_free_table(sgt); + kfree(sgt); ++ } else { ++ dma_unmap_resource(buf->dev, buf->dma_addr, buf->size, ++ buf->dma_dir, 0); + } + vb2_destroy_framevec(buf->vec); + kfree(buf); + } + +-/* +- * For some kind of reserved memory there might be no struct page available, +- * so all that can be done to support such 'pages' is to try to convert +- * pfn to dma address or at the last resort just assume that +- * dma address == physical address (like it has been assumed in earlier version +- * of videobuf2-dma-contig +- */ +- +-#ifdef __arch_pfn_to_dma +-static inline dma_addr_t vb2_dc_pfn_to_dma(struct device *dev, unsigned long pfn) +-{ +- return (dma_addr_t)__arch_pfn_to_dma(dev, pfn); +-} +-#elif defined(__pfn_to_bus) +-static inline dma_addr_t vb2_dc_pfn_to_dma(struct device *dev, unsigned long pfn) +-{ +- return (dma_addr_t)__pfn_to_bus(pfn); +-} +-#elif defined(__pfn_to_phys) +-static inline dma_addr_t vb2_dc_pfn_to_dma(struct device *dev, unsigned long pfn) +-{ +- return (dma_addr_t)__pfn_to_phys(pfn); +-} +-#else +-static inline dma_addr_t vb2_dc_pfn_to_dma(struct device *dev, unsigned long pfn) +-{ +- /* really, we cannot do anything better at this point */ +- return (dma_addr_t)(pfn) << PAGE_SHIFT; +-} +-#endif +- + static void *vb2_dc_get_userptr(struct device *dev, unsigned long vaddr, + unsigned long size, enum dma_data_direction dma_dir) + { +@@ -528,7 +500,12 @@ static void *vb2_dc_get_userptr(struct device *dev, unsigned long vaddr, + for (i = 1; i < n_pages; i++) + if (nums[i-1] + 1 != nums[i]) + goto fail_pfnvec; +- buf->dma_addr = vb2_dc_pfn_to_dma(buf->dev, nums[0]); ++ buf->dma_addr = dma_map_resource(buf->dev, ++ __pfn_to_phys(nums[0]), size, buf->dma_dir, 0); ++ if (dma_mapping_error(buf->dev, buf->dma_addr)) { ++ ret = -ENOMEM; ++ goto fail_pfnvec; ++ } + goto out; + } + +-- +2.20.1 + +From 28d77c21cbeb2c6039d48ef88401b87a56a7a07f Mon Sep 17 00:00:00 2001 +From: Hans Verkuil +Date: Wed, 16 Jan 2019 10:01:13 -0200 +Subject: [PATCH] media: vb2: add buf_out_validate callback + +When queueing a buffer to a request the 'field' value is not validated. +That field is only validated when the _buf_prepare() is called, +which happens when the request is queued. + +However, this validation should happen at QBUF time, since you want +to know about this as soon as possible. Also, the spec requires that +the 'field' value is validated at QBUF time. + +This patch adds a new buf_out_validate callback to validate the +output buffer at buf_prepare time or when QBUF queues an unprepared +buffer to a request. This callback is mandatory for output queues +that support requests. + +This issue was found by v4l2-compliance since it failed to replace +V4L2_FIELD_ANY by a proper field value when testing the vivid video +output in combination with requests. + +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + .../media/common/videobuf2/videobuf2-core.c | 22 ++++++++++++++++--- + include/media/videobuf2-core.h | 5 +++++ + 2 files changed, 24 insertions(+), 3 deletions(-) + +diff --git a/drivers/media/common/videobuf2/videobuf2-core.c b/drivers/media/common/videobuf2/videobuf2-core.c +index ce9294a635cc..e07b6bdb6982 100644 +--- a/drivers/media/common/videobuf2/videobuf2-core.c ++++ b/drivers/media/common/videobuf2/videobuf2-core.c +@@ -499,9 +499,9 @@ static int __vb2_queue_free(struct vb2_queue *q, unsigned int buffers) + pr_info(" buf_init: %u buf_cleanup: %u buf_prepare: %u buf_finish: %u\n", + vb->cnt_buf_init, vb->cnt_buf_cleanup, + vb->cnt_buf_prepare, vb->cnt_buf_finish); +- pr_info(" buf_queue: %u buf_done: %u buf_request_complete: %u\n", +- vb->cnt_buf_queue, vb->cnt_buf_done, +- vb->cnt_buf_request_complete); ++ pr_info(" buf_out_validate: %u buf_queue: %u buf_done: %u buf_request_complete: %u\n", ++ vb->cnt_buf_out_validate, vb->cnt_buf_queue, ++ vb->cnt_buf_done, vb->cnt_buf_request_complete); + pr_info(" alloc: %u put: %u prepare: %u finish: %u mmap: %u\n", + vb->cnt_mem_alloc, vb->cnt_mem_put, + vb->cnt_mem_prepare, vb->cnt_mem_finish, +@@ -1277,6 +1277,14 @@ static int __buf_prepare(struct vb2_buffer *vb) + return 0; + WARN_ON(vb->synced); + ++ if (q->is_output) { ++ ret = call_vb_qop(vb, buf_out_validate, vb); ++ if (ret) { ++ dprintk(1, "buffer validation failed\n"); ++ return ret; ++ } ++ } ++ + vb->state = VB2_BUF_STATE_PREPARING; + + switch (q->memory) { +@@ -1523,6 +1531,14 @@ int vb2_core_qbuf(struct vb2_queue *q, unsigned int index, void *pb, + return -EINVAL; + } + ++ if (q->is_output && !vb->prepared) { ++ ret = call_vb_qop(vb, buf_out_validate, vb); ++ if (ret) { ++ dprintk(1, "buffer validation failed\n"); ++ return ret; ++ } ++ } ++ + media_request_object_init(&vb->req_obj); + + /* Make sure the request is in a safe state for updating. */ +diff --git a/include/media/videobuf2-core.h b/include/media/videobuf2-core.h +index 4a737b2c610b..4849b865b908 100644 +--- a/include/media/videobuf2-core.h ++++ b/include/media/videobuf2-core.h +@@ -296,6 +296,7 @@ struct vb2_buffer { + u32 cnt_mem_num_users; + u32 cnt_mem_mmap; + ++ u32 cnt_buf_out_validate; + u32 cnt_buf_init; + u32 cnt_buf_prepare; + u32 cnt_buf_finish; +@@ -342,6 +343,9 @@ struct vb2_buffer { + * @wait_finish: reacquire all locks released in the previous callback; + * required to continue operation after sleeping while + * waiting for a new buffer to arrive. ++ * @buf_out_validate: called when the output buffer is prepared or queued ++ * to a request; drivers can use this to validate ++ * userspace-provided information; optional. + * @buf_init: called once after allocating a buffer (in MMAP case) + * or after acquiring a new USERPTR buffer; drivers may + * perform additional buffer-related initialization; +@@ -409,6 +413,7 @@ struct vb2_ops { + void (*wait_prepare)(struct vb2_queue *q); + void (*wait_finish)(struct vb2_queue *q); + ++ int (*buf_out_validate)(struct vb2_buffer *vb); + int (*buf_init)(struct vb2_buffer *vb); + int (*buf_prepare)(struct vb2_buffer *vb); + void (*buf_finish)(struct vb2_buffer *vb); +-- +2.20.1 + +From 1284ed59a147c27cb882e49213571f7d52976eb5 Mon Sep 17 00:00:00 2001 +From: Hans Verkuil +Date: Wed, 16 Jan 2019 10:01:17 -0200 +Subject: [PATCH] media: vb2: check that buf_out_validate is present + +The buf_out_validate is required for output queues in combination +with requests. Check this. + +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/common/videobuf2/videobuf2-v4l2.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/media/common/videobuf2/videobuf2-v4l2.c b/drivers/media/common/videobuf2/videobuf2-v4l2.c +index 2f3b3ca5bde6..3aeaea3af42a 100644 +--- a/drivers/media/common/videobuf2/videobuf2-v4l2.c ++++ b/drivers/media/common/videobuf2/videobuf2-v4l2.c +@@ -409,6 +409,15 @@ static int vb2_queue_or_prepare_buf(struct vb2_queue *q, struct media_device *md + */ + if (WARN_ON(!q->ops->buf_request_complete)) + return -EINVAL; ++ /* ++ * Make sure this op is implemented by the driver for the output queue. ++ * It's easy to forget this callback, but is it important to correctly ++ * validate the 'field' value at QBUF time. ++ */ ++ if (WARN_ON((q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT || ++ q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) && ++ !q->ops->buf_out_validate)) ++ return -EINVAL; + + if (vb->state != VB2_BUF_STATE_DEQUEUED) { + dprintk(1, "%s: buffer is not in dequeued state\n", opname); +-- +2.20.1 + +From 6b3e4c4cc162390b833e57de656644786ca88919 Mon Sep 17 00:00:00 2001 +From: Hans Verkuil +Date: Wed, 16 Jan 2019 10:01:16 -0200 +Subject: [PATCH] media: cedrus: add buf_out_validate callback + +Validate the field for an output buffer. This ensures that the +field is validated when the buffer is queued to a request, and +not when the request itself is queued, which is too late. + +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/staging/media/sunxi/cedrus/cedrus_video.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +index 8721b4a7d496..b5cc79389d67 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +@@ -416,6 +416,14 @@ static void cedrus_buf_cleanup(struct vb2_buffer *vb) + ctx->dst_bufs[vb->index] = NULL; + } + ++static int cedrus_buf_out_validate(struct vb2_buffer *vb) ++{ ++ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); ++ ++ vbuf->field = V4L2_FIELD_NONE; ++ return 0; ++} ++ + static int cedrus_buf_prepare(struct vb2_buffer *vb) + { + struct vb2_queue *vq = vb->vb2_queue; +@@ -493,6 +501,7 @@ static struct vb2_ops cedrus_qops = { + .buf_init = cedrus_buf_init, + .buf_cleanup = cedrus_buf_cleanup, + .buf_queue = cedrus_buf_queue, ++ .buf_out_validate = cedrus_buf_out_validate, + .buf_request_complete = cedrus_buf_request_complete, + .start_streaming = cedrus_start_streaming, + .stop_streaming = cedrus_stop_streaming, +-- +2.20.1 + +From a4d3d61254d3645d8de738102c3c473b176180a5 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Tue, 5 Feb 2019 16:20:33 -0500 +Subject: [PATCH] media: v4l2-mem2mem: Rename v4l2_m2m_buf_copy_data to + v4l2_m2m_buf_copy_metadata + +The v4l2_m2m_buf_copy_data helper is used to copy the buffer +metadata, such as its timestamp and its flags. + +Therefore, the v4l2_m2m_buf_copy_metadata name is more clear +and avoids confusion with a payload data copy. + +Signed-off-by: Ezequiel Garcia +Signed-off-by: Hans Verkuil +[hverkuil-cisco@xs4all.nl: also fix cedrus_dec.c] +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/v4l2-core/v4l2-mem2mem.c | 8 ++++---- + drivers/staging/media/sunxi/cedrus/cedrus_dec.c | 2 +- + include/media/v4l2-mem2mem.h | 14 +++++++------- + 5 files changed, 15 insertions(+), 15 deletions(-) + +diff --git a/drivers/media/v4l2-core/v4l2-mem2mem.c b/drivers/media/v4l2-core/v4l2-mem2mem.c +index 631f4e2aa942..1494d0d5951a 100644 +--- a/drivers/media/v4l2-core/v4l2-mem2mem.c ++++ b/drivers/media/v4l2-core/v4l2-mem2mem.c +@@ -975,9 +975,9 @@ void v4l2_m2m_buf_queue(struct v4l2_m2m_ctx *m2m_ctx, + } + EXPORT_SYMBOL_GPL(v4l2_m2m_buf_queue); + +-void v4l2_m2m_buf_copy_data(const struct vb2_v4l2_buffer *out_vb, +- struct vb2_v4l2_buffer *cap_vb, +- bool copy_frame_flags) ++void v4l2_m2m_buf_copy_metadata(const struct vb2_v4l2_buffer *out_vb, ++ struct vb2_v4l2_buffer *cap_vb, ++ bool copy_frame_flags) + { + u32 mask = V4L2_BUF_FLAG_TIMECODE | V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + +@@ -993,7 +993,7 @@ void v4l2_m2m_buf_copy_data(const struct vb2_v4l2_buffer *out_vb, + cap_vb->flags &= ~mask; + cap_vb->flags |= out_vb->flags & mask; + } +-EXPORT_SYMBOL_GPL(v4l2_m2m_buf_copy_data); ++EXPORT_SYMBOL_GPL(v4l2_m2m_buf_copy_metadata); + + void v4l2_m2m_request_queue(struct media_request *req) + { +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +index 443fb037e1cf..4d6d602cdde6 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +@@ -50,7 +50,7 @@ void cedrus_device_run(void *priv) + break; + } + +- v4l2_m2m_buf_copy_data(run.src, run.dst, true); ++ v4l2_m2m_buf_copy_metadata(run.src, run.dst, true); + + dev->dec_ops[ctx->current_codec]->setup(ctx, &run); + +diff --git a/include/media/v4l2-mem2mem.h b/include/media/v4l2-mem2mem.h +index 43e447dcf69d..47c6d9aa0bf4 100644 +--- a/include/media/v4l2-mem2mem.h ++++ b/include/media/v4l2-mem2mem.h +@@ -623,11 +623,11 @@ v4l2_m2m_dst_buf_remove_by_idx(struct v4l2_m2m_ctx *m2m_ctx, unsigned int idx) + } + + /** +- * v4l2_m2m_buf_copy_data() - copy buffer data from the output buffer to the +- * capture buffer ++ * v4l2_m2m_buf_copy_metadata() - copy buffer metadata from ++ * the output buffer to the capture buffer + * +- * @out_vb: the output buffer that is the source of the data. +- * @cap_vb: the capture buffer that will receive the data. ++ * @out_vb: the output buffer that is the source of the metadata. ++ * @cap_vb: the capture buffer that will receive the metadata. + * @copy_frame_flags: copy the KEY/B/PFRAME flags as well. + * + * This helper function copies the timestamp, timecode (if the TIMECODE +@@ -638,9 +638,9 @@ v4l2_m2m_dst_buf_remove_by_idx(struct v4l2_m2m_ctx *m2m_ctx, unsigned int idx) + * flags are not copied. This is typically needed for encoders that + * set this bits explicitly. + */ +-void v4l2_m2m_buf_copy_data(const struct vb2_v4l2_buffer *out_vb, +- struct vb2_v4l2_buffer *cap_vb, +- bool copy_frame_flags); ++void v4l2_m2m_buf_copy_metadata(const struct vb2_v4l2_buffer *out_vb, ++ struct vb2_v4l2_buffer *cap_vb, ++ bool copy_frame_flags); + + /* v4l2 request helper */ + +-- +2.20.1 + +From 50656bad786d001b294764e9f047c5d5b3e4db75 Mon Sep 17 00:00:00 2001 +From: Philipp Zabel +Date: Thu, 10 Jan 2019 11:56:09 -0500 +Subject: [PATCH] media: v4l2-ctrl: Add control to enable h.264 constrained + intra prediction + +Allow to enable h.264 constrained intra prediction (macroblocks using +intra prediction modes are not allowed to use residual data and decoded +samples of neighboring macroblocks coded using inter prediction modes). +This control directly corresponds to the constrained_intra_pred_flag +field in the h.264 picture parameter set. + +Signed-off-by: Philipp Zabel +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + Documentation/media/uapi/v4l/extended-controls.rst | 4 ++++ + drivers/media/v4l2-core/v4l2-ctrls.c | 2 ++ + include/uapi/linux/v4l2-controls.h | 1 + + 3 files changed, 7 insertions(+) + +diff --git a/Documentation/media/uapi/v4l/extended-controls.rst b/Documentation/media/uapi/v4l/extended-controls.rst +index af4273aa5e85..235d0c293983 100644 +--- a/Documentation/media/uapi/v4l/extended-controls.rst ++++ b/Documentation/media/uapi/v4l/extended-controls.rst +@@ -1154,6 +1154,10 @@ enum v4l2_mpeg_video_h264_entropy_mode - + ``V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM (boolean)`` + Enable 8X8 transform for H264. Applicable to the H264 encoder. + ++``V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION (boolean)`` ++ Enable constrained intra prediction for H264. Applicable to the H264 ++ encoder. ++ + ``V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (integer)`` + Cyclic intra macroblock refresh. This is the number of continuous + macroblocks refreshed every frame. Each frame a successive set of +diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c +index 8c47d8f00429..50b56185c02e 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls.c +@@ -825,6 +825,8 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER:return "H264 Number of HC Layers"; + case V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP: + return "H264 Set QP Value for HC Layers"; ++ case V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION: ++ return "H264 Constrained Intra Pred"; + case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; + case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP: return "MPEG4 P-Frame QP Value"; + case V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP: return "MPEG4 B-Frame QP Value"; +diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h +index 3dcfc6148f99..fd65c710b144 100644 +--- a/include/uapi/linux/v4l2-controls.h ++++ b/include/uapi/linux/v4l2-controls.h +@@ -533,6 +533,7 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type { + }; + #define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER (V4L2_CID_MPEG_BASE+381) + #define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP (V4L2_CID_MPEG_BASE+382) ++#define V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION (V4L2_CID_MPEG_BASE+383) + #define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400) + #define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401) + #define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402) +-- +2.21.0 + +From d034696cbe5a6e00f76ca4b7869c6cdef66aebd5 Mon Sep 17 00:00:00 2001 +From: Philipp Zabel +Date: Thu, 10 Jan 2019 11:56:10 -0500 +Subject: [PATCH] media: v4l2-ctrl: Add control for h.264 chroma qp offset + +Allow to add fixed quantization parameter offset between luma and +chroma quantization parameters. This control directly corresponds +to the chroma_qp_index_offset field of the h.264 picture parameter +set. + +Signed-off-by: Philipp Zabel +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + Documentation/media/uapi/v4l/extended-controls.rst | 5 +++++ + drivers/media/v4l2-core/v4l2-ctrls.c | 1 + + include/uapi/linux/v4l2-controls.h | 1 + + 3 files changed, 7 insertions(+) + +diff --git a/Documentation/media/uapi/v4l/extended-controls.rst b/Documentation/media/uapi/v4l/extended-controls.rst +index 235d0c293983..00934efdc9e4 100644 +--- a/Documentation/media/uapi/v4l/extended-controls.rst ++++ b/Documentation/media/uapi/v4l/extended-controls.rst +@@ -1158,6 +1158,11 @@ enum v4l2_mpeg_video_h264_entropy_mode - + Enable constrained intra prediction for H264. Applicable to the H264 + encoder. + ++``V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET (integer)`` ++ Specify the offset that should be added to the luma quantization ++ parameter to determine the chroma quantization parameter. Applicable ++ to the H264 encoder. ++ + ``V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (integer)`` + Cyclic intra macroblock refresh. This is the number of continuous + macroblocks refreshed every frame. Each frame a successive set of +diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c +index 50b56185c02e..99308dac2daa 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls.c +@@ -827,6 +827,7 @@ const char *v4l2_ctrl_get_name(u32 id) + return "H264 Set QP Value for HC Layers"; + case V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION: + return "H264 Constrained Intra Pred"; ++ case V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET: return "H264 Chroma QP Index Offset"; + case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; + case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP: return "MPEG4 P-Frame QP Value"; + case V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP: return "MPEG4 B-Frame QP Value"; +diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h +index fd65c710b144..06479f2fb3ae 100644 +--- a/include/uapi/linux/v4l2-controls.h ++++ b/include/uapi/linux/v4l2-controls.h +@@ -534,6 +534,7 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type { + #define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER (V4L2_CID_MPEG_BASE+381) + #define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP (V4L2_CID_MPEG_BASE+382) + #define V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION (V4L2_CID_MPEG_BASE+383) ++#define V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET (V4L2_CID_MPEG_BASE+384) + #define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_MPEG_BASE+400) + #define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_MPEG_BASE+401) + #define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_MPEG_BASE+402) +-- +2.21.0 + +From 97e15cb4614733f7ebad2c9527b5ff82557dc247 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Tue, 2 Apr 2019 19:31:14 +0200 +Subject: [PATCH] clk: sunxi-ng: nkmp: Avoid GENMASK(-1, 0) + +Signed-off-by: Jernej Skrabec +--- + drivers/clk/sunxi-ng/ccu_nkmp.c | 18 +++++++++++++----- + 1 file changed, 13 insertions(+), 5 deletions(-) + +diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c +index 9b49adb20d07..69dfc6de1c4e 100644 +--- a/drivers/clk/sunxi-ng/ccu_nkmp.c ++++ b/drivers/clk/sunxi-ng/ccu_nkmp.c +@@ -167,7 +167,7 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) + { + struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw); +- u32 n_mask, k_mask, m_mask, p_mask; ++ u32 n_mask = 0, k_mask = 0, m_mask = 0, p_mask = 0; + struct _ccu_nkmp _nkmp; + unsigned long flags; + u32 reg; +@@ -186,10 +186,18 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate, + + ccu_nkmp_find_best(parent_rate, rate, &_nkmp); + +- n_mask = GENMASK(nkmp->n.width + nkmp->n.shift - 1, nkmp->n.shift); +- k_mask = GENMASK(nkmp->k.width + nkmp->k.shift - 1, nkmp->k.shift); +- m_mask = GENMASK(nkmp->m.width + nkmp->m.shift - 1, nkmp->m.shift); +- p_mask = GENMASK(nkmp->p.width + nkmp->p.shift - 1, nkmp->p.shift); ++ if (nkmp->n.width) ++ n_mask = GENMASK(nkmp->n.width + nkmp->n.shift - 1, ++ nkmp->n.shift); ++ if (nkmp->k.width) ++ k_mask = GENMASK(nkmp->k.width + nkmp->k.shift - 1, ++ nkmp->k.shift); ++ if (nkmp->m.width) ++ m_mask = GENMASK(nkmp->m.width + nkmp->m.shift - 1, ++ nkmp->m.shift); ++ if (nkmp->p.width) ++ p_mask = GENMASK(nkmp->p.width + nkmp->p.shift - 1, ++ nkmp->p.shift); + + spin_lock_irqsave(nkmp->common.lock, flags); + +-- +2.21.0 + +From 6f3656f3552a3b32c625c93ddafcbe10bf0fea6d Mon Sep 17 00:00:00 2001 +From: Colin Ian King +Date: Sat, 22 Dec 2018 11:31:59 +0000 +Subject: [PATCH] regulator: axp20x: check rdev is null before dereferencing it + +Currently rdev is dereferenced when assigning desc before rdev is null +checked, hence there is a potential null pointer dereference on rdev. +Fix this by null checking rdev first. + +Detected by CoverityScan, CID#1476031 ("Dereference before null check") + +Fixes: 77e3e3b165db ("regulator: axp20x: add software based soft_start for AXP209 LDO3") +Signed-off-by: Colin Ian King +Signed-off-by: Mark Brown +--- + drivers/regulator/axp20x-regulator.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c +index 48af859fd053..0dfa4ea6bbdf 100644 +--- a/drivers/regulator/axp20x-regulator.c ++++ b/drivers/regulator/axp20x-regulator.c +@@ -367,7 +367,7 @@ static const int axp209_dcdc2_ldo3_slew_rates[] = { + static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp) + { + struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); +- const struct regulator_desc *desc = rdev->desc; ++ const struct regulator_desc *desc; + u8 reg, mask, enable, cfg = 0xff; + const int *slew_rates; + int rate_count = 0; +@@ -375,6 +375,8 @@ static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp) + if (!rdev) + return -EINVAL; + ++ desc = rdev->desc; ++ + switch (axp20x->variant) { + case AXP209_ID: + if (desc->id == AXP20X_DCDC2) { +@@ -436,11 +438,13 @@ static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp) + static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev) + { + struct axp20x_dev *axp20x = rdev_get_drvdata(rdev); +- const struct regulator_desc *desc = rdev->desc; ++ const struct regulator_desc *desc; + + if (!rdev) + return -EINVAL; + ++ desc = rdev->desc; ++ + switch (axp20x->variant) { + case AXP209_ID: + if ((desc->id == AXP20X_LDO3) && +-- +2.21.0 + +From d02337709390c854186c6a21f997dc39760591e1 Mon Sep 17 00:00:00 2001 +From: Axel Lin +Date: Mon, 28 Jan 2019 22:02:19 +0800 +Subject: [PATCH] regulator: axp20x: Fix incorrect vsel_mask settings + +Fix copy-paste mistake while converting to use defines for masks. + +Fixes: db4a555f7c4cf ("regulator: axp20x: use defines for masks") +Signed-off-by: Axel Lin +Signed-off-by: Mark Brown +--- + drivers/regulator/axp20x-regulator.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c +index 48af859fd053..dd0193d77960 100644 +--- a/drivers/regulator/axp20x-regulator.c ++++ b/drivers/regulator/axp20x-regulator.c +@@ -573,7 +573,7 @@ static const struct regulator_desc axp22x_regulators[] = { + AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK, + AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK), + AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20, +- AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT, ++ AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK, + AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK), + AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50, + AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK, +@@ -952,7 +952,7 @@ static const struct regulator_desc axp813_regulators[] = { + AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, + AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK), + AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100, +- AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT, ++ AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, + AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK), + AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100, + AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, +@@ -962,7 +962,7 @@ static const struct regulator_desc axp813_regulators[] = { + AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), + AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin", + axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, +- AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT, ++ AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, + AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), + AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100, + AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, +@@ -977,7 +977,7 @@ static const struct regulator_desc axp813_regulators[] = { + AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, + AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), + AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50, +- AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT, ++ AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, + AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), + /* to do / check ... */ + AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50, +-- +2.21.0 + +From 4afa60d3a88aae3d052e0e8e1e62d6fc15a2be82 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Mon, 18 Feb 2019 02:01:20 +0100 +Subject: [PATCH] regulator: axp20x: fix DCDCB and BLDO2 definitions for AXP806 + +This fixes another set of errors from the refactoring of literals +to mask preproccesor definitions. + +Found by debugging a broken voltage setup on Orange Pi One Plus. + +Fixes: db4a555f7c4cf ("regulator: axp20x: use defines for masks") +Signed-off-by: Ondrej Jirman +Acked-by: Chen-Yu Tsai +Signed-off-by: Mark Brown +--- + drivers/regulator/axp20x-regulator.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c +index 1b51d557ab55..62243957bd19 100644 +--- a/drivers/regulator/axp20x-regulator.c ++++ b/drivers/regulator/axp20x-regulator.c +@@ -791,7 +791,7 @@ static const struct regulator_desc axp806_regulators[] = { + AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK, + AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK), + AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50, +- AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL, ++ AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK, + AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK), + AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc", + axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES, +@@ -817,7 +817,7 @@ static const struct regulator_desc axp806_regulators[] = { + AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK, + AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK), + AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100, +- AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL, ++ AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK, + AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK), + AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100, + AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK, +-- +2.21.0 + +From 55ec26d6a4241363fa94f15377ebd8f1116fbfd7 Mon Sep 17 00:00:00 2001 +From: Samuel Holland +Date: Sat, 12 Jan 2019 20:17:19 -0600 +Subject: [PATCH] arm64: dts: allwinner: a64: Enable A64 timer workaround + +As instability in the architectural timer has been observed on multiple +devices using this SoC, inluding the Pine64 and the Orange Pi Win, +enable the workaround in the SoC's device tree. + +Acked-by: Maxime Ripard +Signed-off-by: Samuel Holland +Signed-off-by: Chen-Yu Tsai +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index bf9b719481c4..8171c0a7f265 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -200,6 +200,7 @@ + + timer { + compatible = "arm,armv8-timer"; ++ allwinner,erratum-unknown1; + interrupts = , + +Date: Sat, 12 Jan 2019 20:17:18 -0600 +Subject: [PATCH] clocksource/drivers/arch_timer: Workaround for Allwinner A64 + timer instability +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The Allwinner A64 SoC is known[1] to have an unstable architectural +timer, which manifests itself most obviously in the time jumping forward +a multiple of 95 years[2][3]. This coincides with 2^56 cycles at a +timer frequency of 24 MHz, implying that the time went slightly backward +(and this was interpreted by the kernel as it jumping forward and +wrapping around past the epoch). + +Investigation revealed instability in the low bits of CNTVCT at the +point a high bit rolls over. This leads to power-of-two cycle forward +and backward jumps. (Testing shows that forward jumps are about twice as +likely as backward jumps.) Since the counter value returns to normal +after an indeterminate read, each "jump" really consists of both a +forward and backward jump from the software perspective. + +Unless the kernel is trapping CNTVCT reads, a userspace program is able +to read the register in a loop faster than it changes. A test program +running on all 4 CPU cores that reported jumps larger than 100 ms was +run for 13.6 hours and reported the following: + + Count | Event +-------+--------------------------- + 9940 | jumped backward 699ms + 268 | jumped backward 1398ms + 1 | jumped backward 2097ms + 16020 | jumped forward 175ms + 6443 | jumped forward 699ms + 2976 | jumped forward 1398ms + 9 | jumped forward 356516ms + 9 | jumped forward 357215ms + 4 | jumped forward 714430ms + 1 | jumped forward 3578440ms + +This works out to a jump larger than 100 ms about every 5.5 seconds on +each CPU core. + +The largest jump (almost an hour!) was the following sequence of reads: + 0x0000007fffffffff → 0x00000093feffffff → 0x0000008000000000 + +Note that the middle bits don't necessarily all read as all zeroes or +all ones during the anomalous behavior; however the low 10 bits checked +by the function in this patch have never been observed with any other +value. + +Also note that smaller jumps are much more common, with backward jumps +of 2048 (2^11) cycles observed over 400 times per second on each core. +(Of course, this is partially explained by lower bits rolling over more +frequently.) Any one of these could have caused the 95 year time skip. + +Similar anomalies were observed while reading CNTPCT (after patching the +kernel to allow reads from userspace). However, the CNTPCT jumps are +much less frequent, and only small jumps were observed. The same program +as before (except now reading CNTPCT) observed after 72 hours: + + Count | Event +-------+--------------------------- + 17 | jumped backward 699ms + 52 | jumped forward 175ms + 2831 | jumped forward 699ms + 5 | jumped forward 1398ms + +Further investigation showed that the instability in CNTPCT/CNTVCT also +affected the respective timer's TVAL register. The following values were +observed immediately after writing CNVT_TVAL to 0x10000000: + + CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error +--------------------+------------+--------------------+----------------- + 0x000000d4a2d8bfff | 0x10003fff | 0x000000d4b2d8bfff | +0x00004000 + 0x000000d4a2d94000 | 0x0fffffff | 0x000000d4b2d97fff | -0x00004000 + 0x000000d4a2d97fff | 0x10003fff | 0x000000d4b2d97fff | +0x00004000 + 0x000000d4a2d9c000 | 0x0fffffff | 0x000000d4b2d9ffff | -0x00004000 + +The pattern of errors in CNTV_TVAL seemed to depend on exactly which +value was written to it. For example, after writing 0x10101010: + + CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error +--------------------+------------+--------------------+----------------- + 0x000001ac3effffff | 0x1110100f | 0x000001ac4f10100f | +0x1000000 + 0x000001ac40000000 | 0x1010100f | 0x000001ac5110100f | -0x1000000 + 0x000001ac58ffffff | 0x1110100f | 0x000001ac6910100f | +0x1000000 + 0x000001ac66000000 | 0x1010100f | 0x000001ac7710100f | -0x1000000 + 0x000001ac6affffff | 0x1110100f | 0x000001ac7b10100f | +0x1000000 + 0x000001ac6e000000 | 0x1010100f | 0x000001ac7f10100f | -0x1000000 + +I was also twice able to reproduce the issue covered by Allwinner's +workaround[4], that writing to TVAL sometimes fails, and both CVAL and +TVAL are left with entirely bogus values. One was the following values: + + CNTVCT | CNTV_TVAL | CNTV_CVAL +--------------------+------------+-------------------------------------- + 0x000000d4a2d6014c | 0x8fbd5721 | 0x000000d132935fff (615s in the past) +Reviewed-by: Marc Zyngier + +======================================================================== + +Because the CPU can read the CNTPCT/CNTVCT registers faster than they +change, performing two reads of the register and comparing the high bits +(like other workarounds) is not a workable solution. And because the +timer can jump both forward and backward, no pair of reads can +distinguish a good value from a bad one. The only way to guarantee a +good value from consecutive reads would be to read _three_ times, and +take the middle value only if the three values are 1) each unique and +2) increasing. This takes at minimum 3 counter cycles (125 ns), or more +if an anomaly is detected. + +However, since there is a distinct pattern to the bad values, we can +optimize the common case (1022/1024 of the time) to a single read by +simply ignoring values that match the error pattern. This still takes no +more than 3 cycles in the worst case, and requires much less code. As an +additional safety check, we still limit the loop iteration to the number +of max-frequency (1.2 GHz) CPU cycles in three 24 MHz counter periods. + +For the TVAL registers, the simple solution is to not use them. Instead, +read or write the CVAL and calculate the TVAL value in software. + +Although the manufacturer is aware of at least part of the erratum[4], +there is no official name for it. For now, use the kernel-internal name +"UNKNOWN1". + +[1]: https://github.com/armbian/build/commit/a08cd6fe7ae9 +[2]: https://forum.armbian.com/topic/3458-a64-datetime-clock-issue/ +[3]: https://irclog.whitequark.org/linux-sunxi/2018-01-26 +[4]: https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/drivers/clocksource/arm_arch_timer.c#L272 + +Acked-by: Maxime Ripard +Tested-by: Andre Przywara +Signed-off-by: Samuel Holland +Cc: stable@vger.kernel.org +Signed-off-by: Daniel Lezcano +--- + Documentation/arm64/silicon-errata.txt | 2 + + drivers/clocksource/Kconfig | 10 +++++ + drivers/clocksource/arm_arch_timer.c | 55 ++++++++++++++++++++++++++ + 3 files changed, 67 insertions(+) + +diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt +index 1f09d043d086..ddb8ce5333ba 100644 +--- a/Documentation/arm64/silicon-errata.txt ++++ b/Documentation/arm64/silicon-errata.txt +@@ -44,6 +44,8 @@ stable kernels. + + | Implementor | Component | Erratum ID | Kconfig | + +----------------+-----------------+-----------------+-----------------------------+ ++| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 | ++| | | | | + | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | + | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | + | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | +diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig +index a9e26f6a81a1..8dfd3bc448d0 100644 +--- a/drivers/clocksource/Kconfig ++++ b/drivers/clocksource/Kconfig +@@ -360,6 +360,16 @@ config ARM64_ERRATUM_858921 + The workaround will be dynamically enabled when an affected + core is detected. + ++config SUN50I_ERRATUM_UNKNOWN1 ++ bool "Workaround for Allwinner A64 erratum UNKNOWN1" ++ default y ++ depends on ARM_ARCH_TIMER && ARM64 && ARCH_SUNXI ++ select ARM_ARCH_TIMER_OOL_WORKAROUND ++ help ++ This option enables a workaround for instability in the timer on ++ the Allwinner A64 SoC. The workaround will only be active if the ++ allwinner,erratum-unknown1 property is found in the timer node. ++ + config ARM_GLOBAL_TIMER + bool "Support for the ARM global timer" if COMPILE_TEST + select TIMER_OF if OF +diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c +index 9a7d4dc00b6e..a8b20b65bd4b 100644 +--- a/drivers/clocksource/arm_arch_timer.c ++++ b/drivers/clocksource/arm_arch_timer.c +@@ -326,6 +326,48 @@ static u64 notrace arm64_1188873_read_cntvct_el0(void) + } + #endif + ++#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1 ++/* ++ * The low bits of the counter registers are indeterminate while bit 10 or ++ * greater is rolling over. Since the counter value can jump both backward ++ * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values ++ * with all ones or all zeros in the low bits. Bound the loop by the maximum ++ * number of CPU cycles in 3 consecutive 24 MHz counter periods. ++ */ ++#define __sun50i_a64_read_reg(reg) ({ \ ++ u64 _val; \ ++ int _retries = 150; \ ++ \ ++ do { \ ++ _val = read_sysreg(reg); \ ++ _retries--; \ ++ } while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries); \ ++ \ ++ WARN_ON_ONCE(!_retries); \ ++ _val; \ ++}) ++ ++static u64 notrace sun50i_a64_read_cntpct_el0(void) ++{ ++ return __sun50i_a64_read_reg(cntpct_el0); ++} ++ ++static u64 notrace sun50i_a64_read_cntvct_el0(void) ++{ ++ return __sun50i_a64_read_reg(cntvct_el0); ++} ++ ++static u32 notrace sun50i_a64_read_cntp_tval_el0(void) ++{ ++ return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0(); ++} ++ ++static u32 notrace sun50i_a64_read_cntv_tval_el0(void) ++{ ++ return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0(); ++} ++#endif ++ + #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND + DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround); + EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); +@@ -423,6 +465,19 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { + .read_cntvct_el0 = arm64_1188873_read_cntvct_el0, + }, + #endif ++#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1 ++ { ++ .match_type = ate_match_dt, ++ .id = "allwinner,erratum-unknown1", ++ .desc = "Allwinner erratum UNKNOWN1", ++ .read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0, ++ .read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0, ++ .read_cntpct_el0 = sun50i_a64_read_cntpct_el0, ++ .read_cntvct_el0 = sun50i_a64_read_cntvct_el0, ++ .set_next_event_phys = erratum_set_next_event_tval_phys, ++ .set_next_event_virt = erratum_set_next_event_tval_virt, ++ }, ++#endif + }; + + typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *, +-- +2.21.0 + +From patchwork Sat Jan 26 06:18:09 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Vasily Khoruzhick +X-Patchwork-Id: 1035824 +Return-Path: +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 1B380C282C3 + for ; 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+ Fri, 25 Jan 2019 22:18:17 -0800 (PST) +Received: from anarsoul-thinkpad.lan (216-71-193-140.dyn.novuscom.net. + [216.71.193.140]) + by smtp.gmail.com with ESMTPSA id + 85sm36537643pfw.17.2019.01.25.22.18.16 + (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); + Fri, 25 Jan 2019 22:18:16 -0800 (PST) +From: Vasily Khoruzhick +To: Liam Girdwood , + Mark Brown , Chen-Yu Tsai , + Olliver Schinagl , + linux-kernel@vger.kernel.org +Cc: Vasily Khoruzhick +Subject: [PATCH] regulator: axp20x: fix ALDO2, + DLDO2 and ELDO3 definitions for AXP803 +Date: Fri, 25 Jan 2019 22:18:09 -0800 +Message-Id: <20190126061809.18035-1-anarsoul@gmail.com> +X-Mailer: git-send-email 2.20.1 +MIME-Version: 1.0 +Sender: linux-kernel-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-kernel@vger.kernel.org + +Looks like refactoring didn't go well and left ALDO2, DLDO2 and ELDO3 +definitions broken for AXP803 - now they are using register address +instead of mask. Fix it by using mask where necessary. + +Fixes: db4a555f7c4cf ("regulator: axp20x: use defines for masks") +Signed-off-by: Vasily Khoruzhick +Reviewed-by: Chen-Yu Tsai +--- + drivers/regulator/axp20x-regulator.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c +index 48af859fd053..a808b03cae10 100644 +--- a/drivers/regulator/axp20x-regulator.c ++++ b/drivers/regulator/axp20x-regulator.c +@@ -719,7 +719,7 @@ static const struct regulator_desc axp803_regulators[] = { + AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK, + AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK), + AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100, +- AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT, ++ AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK, + AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK), + AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100, + AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK, +@@ -729,7 +729,7 @@ static const struct regulator_desc axp803_regulators[] = { + AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK), + AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin", + axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES, +- AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT, ++ AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK, + AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK), + AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100, + AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK, +@@ -744,7 +744,7 @@ static const struct regulator_desc axp803_regulators[] = { + AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK, + AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK), + AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50, +- AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT, ++ AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK, + AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK), + AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50, + AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK, diff --git a/projects/Allwinner/patches/linux/0003-fixes-from-5.2.patch b/projects/Allwinner/patches/linux/0003-fixes-from-5.2.patch new file mode 100644 index 0000000000..738a3a4b50 --- /dev/null +++ b/projects/Allwinner/patches/linux/0003-fixes-from-5.2.patch @@ -0,0 +1,676 @@ +From 2495f39ce1fa027aab0c3161c14f074295f81c71 Mon Sep 17 00:00:00 2001 +From: Dafna Hirschfeld +Date: Wed, 6 Mar 2019 16:13:40 -0500 +Subject: [PATCH] media: vicodec: Introducing stateless fwht defs and structs + +Add structs and definitions needed to implement stateless +decoder for fwht and add I/P-frames QP controls to the +public api. + +Signed-off-by: Dafna Hirschfeld +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/media/platform/vicodec/vicodec-core.c | 41 ++++++------------- + drivers/media/v4l2-core/v4l2-ctrls.c | 12 ++++++ + include/media/fwht-ctrls.h | 31 ++++++++++++++ + include/media/v4l2-ctrls.h | 5 ++- + include/uapi/linux/v4l2-controls.h | 4 ++ + include/uapi/linux/videodev2.h | 1 + + 6 files changed, 65 insertions(+), 29 deletions(-) + create mode 100644 include/media/fwht-ctrls.h + +diff --git a/drivers/media/platform/vicodec/vicodec-core.c b/drivers/media/platform/vicodec/vicodec-core.c +index b86985babdb1..a3a9d8ac4a33 100644 +--- a/drivers/media/platform/vicodec/vicodec-core.c ++++ b/drivers/media/platform/vicodec/vicodec-core.c +@@ -64,6 +64,10 @@ static const struct v4l2_fwht_pixfmt_info pixfmt_fwht = { + V4L2_PIX_FMT_FWHT, 0, 3, 1, 1, 1, 1, 1, 0, 1 + }; + ++static const struct v4l2_fwht_pixfmt_info pixfmt_stateless_fwht = { ++ V4L2_PIX_FMT_FWHT_STATELESS, 0, 3, 1, 1, 1, 1, 1, 0, 1 ++}; ++ + static void vicodec_dev_release(struct device *dev) + { + } +@@ -1524,10 +1528,6 @@ static int queue_init(void *priv, struct vb2_queue *src_vq, + return vb2_queue_init(dst_vq); + } + +-#define VICODEC_CID_CUSTOM_BASE (V4L2_CID_MPEG_BASE | 0xf000) +-#define VICODEC_CID_I_FRAME_QP (VICODEC_CID_CUSTOM_BASE + 0) +-#define VICODEC_CID_P_FRAME_QP (VICODEC_CID_CUSTOM_BASE + 1) +- + static int vicodec_s_ctrl(struct v4l2_ctrl *ctrl) + { + struct vicodec_ctx *ctx = container_of(ctrl->handler, +@@ -1537,10 +1537,10 @@ static int vicodec_s_ctrl(struct v4l2_ctrl *ctrl) + case V4L2_CID_MPEG_VIDEO_GOP_SIZE: + ctx->state.gop_size = ctrl->val; + return 0; +- case VICODEC_CID_I_FRAME_QP: ++ case V4L2_CID_FWHT_I_FRAME_QP: + ctx->state.i_frame_qp = ctrl->val; + return 0; +- case VICODEC_CID_P_FRAME_QP: ++ case V4L2_CID_FWHT_P_FRAME_QP: + ctx->state.p_frame_qp = ctrl->val; + return 0; + } +@@ -1551,26 +1551,9 @@ static const struct v4l2_ctrl_ops vicodec_ctrl_ops = { + .s_ctrl = vicodec_s_ctrl, + }; + +-static const struct v4l2_ctrl_config vicodec_ctrl_i_frame = { +- .ops = &vicodec_ctrl_ops, +- .id = VICODEC_CID_I_FRAME_QP, +- .name = "FWHT I-Frame QP Value", +- .type = V4L2_CTRL_TYPE_INTEGER, +- .min = 1, +- .max = 31, +- .def = 20, +- .step = 1, +-}; +- +-static const struct v4l2_ctrl_config vicodec_ctrl_p_frame = { +- .ops = &vicodec_ctrl_ops, +- .id = VICODEC_CID_P_FRAME_QP, +- .name = "FWHT P-Frame QP Value", +- .type = V4L2_CTRL_TYPE_INTEGER, +- .min = 1, +- .max = 31, +- .def = 20, +- .step = 1, ++static const struct v4l2_ctrl_config vicodec_ctrl_stateless_state = { ++ .id = V4L2_CID_MPEG_VIDEO_FWHT_PARAMS, ++ .elem_size = sizeof(struct v4l2_ctrl_fwht_params), + }; + + /* +@@ -1603,8 +1586,10 @@ static int vicodec_open(struct file *file) + v4l2_ctrl_handler_init(hdl, 4); + v4l2_ctrl_new_std(hdl, &vicodec_ctrl_ops, V4L2_CID_MPEG_VIDEO_GOP_SIZE, + 1, 16, 1, 10); +- v4l2_ctrl_new_custom(hdl, &vicodec_ctrl_i_frame, NULL); +- v4l2_ctrl_new_custom(hdl, &vicodec_ctrl_p_frame, NULL); ++ v4l2_ctrl_new_std(hdl, &vicodec_ctrl_ops, V4L2_CID_FWHT_I_FRAME_QP, ++ 1, 31, 1, 20); ++ v4l2_ctrl_new_std(hdl, &vicodec_ctrl_ops, V4L2_CID_FWHT_P_FRAME_QP, ++ 1, 31, 1, 20); + if (hdl->error) { + rc = hdl->error; + v4l2_ctrl_handler_free(hdl); +diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c +index 54d66dbc2a31..aed1c3a06500 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls.c +@@ -849,6 +849,9 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME: return "Force Key Frame"; + case V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS: return "MPEG-2 Slice Parameters"; + case V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION: return "MPEG-2 Quantization Matrices"; ++ case V4L2_CID_MPEG_VIDEO_FWHT_PARAMS: return "FWHT Stateless Parameters"; ++ case V4L2_CID_FWHT_I_FRAME_QP: return "FWHT I-Frame QP Value"; ++ case V4L2_CID_FWHT_P_FRAME_QP: return "FWHT P-Frame QP Value"; + + /* VPX controls */ + case V4L2_CID_MPEG_VIDEO_VPX_NUM_PARTITIONS: return "VPX Number of Partitions"; +@@ -1303,6 +1306,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, + case V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION: + *type = V4L2_CTRL_TYPE_MPEG2_QUANTIZATION; + break; ++ case V4L2_CID_MPEG_VIDEO_FWHT_PARAMS: ++ *type = V4L2_CTRL_TYPE_FWHT_PARAMS; ++ break; + default: + *type = V4L2_CTRL_TYPE_INTEGER; + break; +@@ -1669,6 +1675,9 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, + case V4L2_CTRL_TYPE_MPEG2_QUANTIZATION: + return 0; + ++ case V4L2_CTRL_TYPE_FWHT_PARAMS: ++ return 0; ++ + default: + return -EINVAL; + } +@@ -2249,6 +2258,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, + case V4L2_CTRL_TYPE_MPEG2_QUANTIZATION: + elem_size = sizeof(struct v4l2_ctrl_mpeg2_quantization); + break; ++ case V4L2_CTRL_TYPE_FWHT_PARAMS: ++ elem_size = sizeof(struct v4l2_ctrl_fwht_params); ++ break; + default: + if (type < V4L2_CTRL_COMPOUND_TYPES) + elem_size = sizeof(s32); +diff --git a/include/media/fwht-ctrls.h b/include/media/fwht-ctrls.h +new file mode 100644 +index 000000000000..615027410e47 +--- /dev/null ++++ b/include/media/fwht-ctrls.h +@@ -0,0 +1,31 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * These are the FWHT state controls for use with stateless FWHT ++ * codec drivers. ++ * ++ * It turns out that these structs are not stable yet and will undergo ++ * more changes. So keep them private until they are stable and ready to ++ * become part of the official public API. ++ */ ++ ++#ifndef _FWHT_CTRLS_H_ ++#define _FWHT_CTRLS_H_ ++ ++#define V4L2_CTRL_TYPE_FWHT_PARAMS 0x0105 ++ ++#define V4L2_CID_MPEG_VIDEO_FWHT_PARAMS (V4L2_CID_MPEG_BASE + 292) ++ ++struct v4l2_ctrl_fwht_params { ++ __u64 backward_ref_ts; ++ __u32 version; ++ __u32 width; ++ __u32 height; ++ __u32 flags; ++ __u32 colorspace; ++ __u32 xfer_func; ++ __u32 ycbcr_enc; ++ __u32 quantization; ++}; ++ ++ ++#endif +diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h +index 200f8a66ecaa..bd621cec65a5 100644 +--- a/include/media/v4l2-ctrls.h ++++ b/include/media/v4l2-ctrls.h +@@ -23,10 +23,11 @@ + #include + + /* +- * Include the mpeg2 stateless codec compound control definitions. ++ * Include the mpeg2 and fwht stateless codec compound control definitions. + * This will move to the public headers once this API is fully stable. + */ + #include ++#include + + /* forward references */ + struct file; +@@ -49,6 +50,7 @@ struct poll_table_struct; + * @p_char: Pointer to a string. + * @p_mpeg2_slice_params: Pointer to a MPEG2 slice parameters structure. + * @p_mpeg2_quantization: Pointer to a MPEG2 quantization data structure. ++ * @p_fwht_params: Pointer to a FWHT stateless parameters structure. + * @p: Pointer to a compound value. + */ + union v4l2_ctrl_ptr { +@@ -60,6 +62,7 @@ union v4l2_ctrl_ptr { + char *p_char; + struct v4l2_ctrl_mpeg2_slice_params *p_mpeg2_slice_params; + struct v4l2_ctrl_mpeg2_quantization *p_mpeg2_quantization; ++ struct v4l2_ctrl_fwht_params *p_fwht_params; + void *p; + }; + +diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h +index 06479f2fb3ae..78816ec88751 100644 +--- a/include/uapi/linux/v4l2-controls.h ++++ b/include/uapi/linux/v4l2-controls.h +@@ -404,6 +404,10 @@ enum v4l2_mpeg_video_multi_slice_mode { + #define V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE (V4L2_CID_MPEG_BASE+228) + #define V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME (V4L2_CID_MPEG_BASE+229) + ++/* CIDs for the FWHT codec as used by the vicodec driver. */ ++#define V4L2_CID_FWHT_I_FRAME_QP (V4L2_CID_MPEG_BASE + 290) ++#define V4L2_CID_FWHT_P_FRAME_QP (V4L2_CID_MPEG_BASE + 291) ++ + #define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_MPEG_BASE+300) + #define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_MPEG_BASE+301) + #define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP (V4L2_CID_MPEG_BASE+302) +diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h +index 1db220da3bcc..496e6453450c 100644 +--- a/include/uapi/linux/videodev2.h ++++ b/include/uapi/linux/videodev2.h +@@ -669,6 +669,7 @@ struct v4l2_pix_format { + #define V4L2_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0') /* VP9 */ + #define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* HEVC aka H.265 */ + #define V4L2_PIX_FMT_FWHT v4l2_fourcc('F', 'W', 'H', 'T') /* Fast Walsh Hadamard Transform (vicodec) */ ++#define V4L2_PIX_FMT_FWHT_STATELESS v4l2_fourcc('S', 'F', 'W', 'H') /* Stateless FWHT (vicodec) */ + + /* Vendor-specific formats */ + #define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */ +-- +2.21.0 + +From 97ed8eab2a0067bee21aa634c938454660e76a38 Mon Sep 17 00:00:00 2001 +From: Greg Kroah-Hartman +Date: Tue, 2 Apr 2019 12:31:49 +0200 +Subject: [PATCH] staging: add missing SPDX lines to Makefile files + +There are a few remaining drivers/staging/*/Makefile files that do not +have SPDX identifiers in them. Add the correct GPL-2.0 identifier to +them to make scanning tools happy. + +Reviewed-by: Mukesh Ojha +Signed-off-by: Greg Kroah-Hartman +--- + drivers/staging/media/sunxi/Makefile | 1 + + drivers/staging/media/sunxi/cedrus/Makefile | 1 + + 56 files changed, 56 insertions(+) + +diff --git a/drivers/staging/media/sunxi/Makefile b/drivers/staging/media/sunxi/Makefile +index cee2846c3ecf..b87140b0e15f 100644 +--- a/drivers/staging/media/sunxi/Makefile ++++ b/drivers/staging/media/sunxi/Makefile +@@ -1 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0 + obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += cedrus/ +diff --git a/drivers/staging/media/sunxi/cedrus/Makefile b/drivers/staging/media/sunxi/cedrus/Makefile +index e9dc68b7bcb6..808842f0119e 100644 +--- a/drivers/staging/media/sunxi/cedrus/Makefile ++++ b/drivers/staging/media/sunxi/cedrus/Makefile +@@ -1,3 +1,4 @@ ++# SPDX-License-Identifier: GPL-2.0 + obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += sunxi-cedrus.o + + sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o cedrus_mpeg2.o +-- +2.21.0 + +From 6ece1909256d809df8cf975a62bddd565d03eb1a Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Thu, 28 Feb 2019 18:57:48 +0100 +Subject: [PATCH 1/3] clk: sunxi-ng: Allow DE clock to set parent rate + +DE2/DE3 mixers have to run at specific frequency in order to work +optimally. This wasn't actually possible for some SoCs because "de" +clock wasn't allowed to adjust parent rate. + +Add CLK_SET_RATE_PARENT flag to all "de" clocks which didn't have it +yet. + +Signed-off-by: Jernej Skrabec +--- + drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 3 ++- + drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 2 +- + drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 ++- + 3 files changed, 5 insertions(+), 3 deletions(-) + +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +index 932836d26e2b..be0deee70182 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +@@ -531,7 +531,8 @@ static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram", + + static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" }; + static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, +- 0x104, 0, 4, 24, 3, BIT(31), 0); ++ 0x104, 0, 4, 24, 3, BIT(31), ++ CLK_SET_RATE_PARENT); + + static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" }; + static const u8 tcon0_table[] = { 0, 2, }; +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +index 139e8389615c..daf78966555e 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +@@ -266,7 +266,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600, + 0, 4, /* M */ + 24, 1, /* mux */ + BIT(31), /* gate */ +- 0); ++ CLK_SET_RATE_PARENT); + + static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2", + 0x60c, BIT(0), 0); +diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +index 621b1cd996db..ee170bf21cdf 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c ++++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c +@@ -325,7 +325,8 @@ static SUNXI_CCU_GATE(dram_ohci_clk, "dram-ohci", "dram", + + static const char * const de_parents[] = { "pll-video", "pll-periph0" }; + static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, +- 0x104, 0, 4, 24, 2, BIT(31), 0); ++ 0x104, 0, 4, 24, 2, BIT(31), ++ CLK_SET_RATE_PARENT); + + static const char * const tcon_parents[] = { "pll-video" }; + static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents, +-- +2.20.1 + + +From 3622c17fc40031cd2ca7b4030b83e6fad0c4e127 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 24 Dec 2018 18:11:56 +0100 +Subject: [PATCH 2/3] drm/sun4i: Add VI scaler line size quirk for DE2/DE3 + +While all RGB scalers have maximum line size of 2048, some YUV scalers +have maximum line size of 2048 and some have line size of 4096. + +Since there is no rule for that, add a quirk. + +Signed-off-by: Jernej Skrabec +--- + drivers/gpu/drm/sun4i/sun8i_mixer.c | 9 +++++++++ + drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 ++ + 2 files changed, 11 insertions(+) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c +index 44a9ba7d8433..e46edacb7ab4 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c +@@ -554,6 +554,7 @@ static int sun8i_mixer_remove(struct platform_device *pdev) + static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = { + .ccsc = 0, + .scaler_mask = 0xf, ++ .scanline_yuv = 2048, + .ui_num = 3, + .vi_num = 1, + }; +@@ -561,6 +562,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = { + static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = { + .ccsc = 1, + .scaler_mask = 0x3, ++ .scanline_yuv = 2048, + .ui_num = 1, + .vi_num = 1, + }; +@@ -569,6 +571,7 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = { + .ccsc = 0, + .mod_rate = 432000000, + .scaler_mask = 0xf, ++ .scanline_yuv = 2048, + .ui_num = 3, + .vi_num = 1, + }; +@@ -577,6 +580,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = { + .ccsc = 0, + .mod_rate = 297000000, + .scaler_mask = 0xf, ++ .scanline_yuv = 2048, + .ui_num = 3, + .vi_num = 1, + }; +@@ -585,6 +589,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = { + .ccsc = 1, + .mod_rate = 297000000, + .scaler_mask = 0x3, ++ .scanline_yuv = 2048, + .ui_num = 1, + .vi_num = 1, + }; +@@ -593,6 +598,7 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = { + .vi_num = 2, + .ui_num = 1, + .scaler_mask = 0x3, ++ .scanline_yuv = 2048, + .ccsc = 0, + .mod_rate = 150000000, + }; +@@ -601,6 +607,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = { + .ccsc = 0, + .mod_rate = 297000000, + .scaler_mask = 0xf, ++ .scanline_yuv = 4096, + .ui_num = 3, + .vi_num = 1, + }; +@@ -609,6 +616,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { + .ccsc = 1, + .mod_rate = 297000000, + .scaler_mask = 0x3, ++ .scanline_yuv = 2048, + .ui_num = 1, + .vi_num = 1, + }; +@@ -618,6 +626,7 @@ static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = { + .is_de3 = true, + .mod_rate = 600000000, + .scaler_mask = 0xf, ++ .scanline_yuv = 4096, + .ui_num = 3, + .vi_num = 1, + }; +diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h +index 913d14ce68b0..80e084caa084 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h ++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h +@@ -159,6 +159,7 @@ struct de2_fmt_info { + * @mod_rate: module clock rate that needs to be set in order to have + * a functional block. + * @is_de3: true, if this is next gen display engine 3.0, false otherwise. ++ * @scaline_yuv: size of a scanline for VI scaler for YUV formats. + */ + struct sun8i_mixer_cfg { + int vi_num; +@@ -167,6 +168,7 @@ struct sun8i_mixer_cfg { + int ccsc; + unsigned long mod_rate; + unsigned int is_de3 : 1; ++ unsigned int scanline_yuv; + }; + + struct sun8i_mixer { +-- +2.20.1 + + +From 6d1be62144db6bebfdbcb8c50a11ac428dcdc741 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 24 Dec 2018 18:16:50 +0100 +Subject: [PATCH 3/3] drm/sun4i: Improve VI scaling for DE2/DE3 + +VI planes support coarse scaling which helps to overcome VI scaler +limitations. While exact working of coarse scaling isn't known, it seems +that it just skips programmed amount of rows and columns. This is +especially useful for downscaling very big planes (4K down to 1080p). + +Horizontal coarse scaling is currently used to fit one line to VI scaler +buffer. + +Vertical coarse scaling is used to assure that VI scaler is actually +capable of processing framebuffer in one frame time. + +Signed-off-by: Jernej Skrabec +--- + drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 54 ++++++++++++++++++++++++-- + drivers/gpu/drm/sun4i/sun8i_vi_layer.h | 11 ++++++ + 2 files changed, 62 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +index 87be898f9b7a..ce42560aa9df 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c ++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +@@ -80,6 +80,8 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, + u32 bld_base, ch_base; + u32 outsize, insize; + u32 hphase, vphase; ++ u32 hn = 0, hm = 0; ++ u32 vn = 0, vm = 0; + bool subsampled; + + DRM_DEBUG_DRIVER("Updating VI channel %d overlay %d\n", +@@ -137,12 +139,41 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, + subsampled = format->hsub > 1 || format->vsub > 1; + + if (insize != outsize || subsampled || hphase || vphase) { +- u32 hscale, vscale; ++ unsigned int scanline, required; ++ struct drm_display_mode *mode; ++ u32 hscale, vscale, fps; ++ u64 ability; + + DRM_DEBUG_DRIVER("HW scaling is enabled\n"); + +- hscale = state->src_w / state->crtc_w; +- vscale = state->src_h / state->crtc_h; ++ mode = &plane->state->crtc->state->mode; ++ fps = (mode->clock * 1000) / (mode->vtotal * mode->htotal); ++ ability = clk_get_rate(mixer->mod_clk); ++ /* BSP algorithm assumes 80% efficiency of VI scaler unit */ ++ ability *= 80; ++ do_div(ability, mode->vdisplay * fps * max(src_w, dst_w)); ++ ++ required = src_h * 100 / dst_h; ++ ++ if (ability < required) { ++ DRM_DEBUG_DRIVER("Using vertical coarse scaling\n"); ++ vm = src_h; ++ vn = (u32)ability * dst_h / 100; ++ src_h = vn; ++ } ++ ++ /* it seems that every RGB scaler has buffer for 2048 pixels */ ++ scanline = subsampled ? mixer->cfg->scanline_yuv : 2048; ++ ++ if (src_w > scanline) { ++ DRM_DEBUG_DRIVER("Using horizontal coarse scaling\n"); ++ hm = src_w; ++ hn = scanline; ++ src_w = hn; ++ } ++ ++ hscale = (src_w << 16) / dst_w; ++ vscale = (src_h << 16) / dst_h; + + sun8i_vi_scaler_setup(mixer, channel, src_w, src_h, dst_w, + dst_h, hscale, vscale, hphase, vphase, +@@ -153,6 +184,23 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, + sun8i_vi_scaler_enable(mixer, channel, false); + } + ++ regmap_write(mixer->engine.regs, ++ SUN8I_MIXER_CHAN_VI_HDS_Y(ch_base), ++ SUN8I_MIXER_CHAN_VI_DS_N(hn) | ++ SUN8I_MIXER_CHAN_VI_DS_M(hm)); ++ regmap_write(mixer->engine.regs, ++ SUN8I_MIXER_CHAN_VI_HDS_UV(ch_base), ++ SUN8I_MIXER_CHAN_VI_DS_N(hn) | ++ SUN8I_MIXER_CHAN_VI_DS_M(hm)); ++ regmap_write(mixer->engine.regs, ++ SUN8I_MIXER_CHAN_VI_VDS_Y(ch_base), ++ SUN8I_MIXER_CHAN_VI_DS_N(vn) | ++ SUN8I_MIXER_CHAN_VI_DS_M(vm)); ++ regmap_write(mixer->engine.regs, ++ SUN8I_MIXER_CHAN_VI_VDS_UV(ch_base), ++ SUN8I_MIXER_CHAN_VI_DS_N(vn) | ++ SUN8I_MIXER_CHAN_VI_DS_M(vm)); ++ + /* Set base coordinates */ + DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n", + state->dst.x1, state->dst.y1); +diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h +index 8a5e6d01c85d..a223a4839f45 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h ++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h +@@ -24,6 +24,14 @@ + ((base) + 0x30 * (layer) + 0x18 + 4 * (plane)) + #define SUN8I_MIXER_CHAN_VI_OVL_SIZE(base) \ + ((base) + 0xe8) ++#define SUN8I_MIXER_CHAN_VI_HDS_Y(base) \ ++ ((base) + 0xf0) ++#define SUN8I_MIXER_CHAN_VI_HDS_UV(base) \ ++ ((base) + 0xf4) ++#define SUN8I_MIXER_CHAN_VI_VDS_Y(base) \ ++ ((base) + 0xf8) ++#define SUN8I_MIXER_CHAN_VI_VDS_UV(base) \ ++ ((base) + 0xfc) + + #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR_EN BIT(0) + /* RGB mode should be set for RGB formats and cleared for YCbCr */ +@@ -33,6 +41,9 @@ + #define SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK GENMASK(31, 24) + #define SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA(x) ((x) << 24) + ++#define SUN8I_MIXER_CHAN_VI_DS_N(x) ((x) << 16) ++#define SUN8I_MIXER_CHAN_VI_DS_M(x) ((x) << 0) ++ + struct sun8i_mixer; + + struct sun8i_vi_layer { +-- +2.20.1 + +From 05f640b80bb6797ec11c328d16e9905884653f98 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sun, 7 Apr 2019 20:36:40 +0200 +Subject: [PATCH] media: cedrus: Fix initialization order + +Currently, MEDIA_IOC_G_TOPOLOGY ioctl on cedrus fails due to incorrect +initialization order. Fix that by moving video_register_device() before +v4l2_m2m_register_media_controller() and while at it, fix error path. + +Reported-by: Jonas Karlman +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus.c | 24 ++++++++++----------- + 1 file changed, 12 insertions(+), 12 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c +index b98add3cdedd..d0429c0e6b6b 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c +@@ -300,7 +300,7 @@ static int cedrus_probe(struct platform_device *pdev) + "Failed to initialize V4L2 M2M device\n"); + ret = PTR_ERR(dev->m2m_dev); + +- goto err_video; ++ goto err_v4l2; + } + + dev->mdev.dev = &pdev->dev; +@@ -310,23 +310,23 @@ static int cedrus_probe(struct platform_device *pdev) + dev->mdev.ops = &cedrus_m2m_media_ops; + dev->v4l2_dev.mdev = &dev->mdev; + +- ret = v4l2_m2m_register_media_controller(dev->m2m_dev, vfd, +- MEDIA_ENT_F_PROC_VIDEO_DECODER); +- if (ret) { +- v4l2_err(&dev->v4l2_dev, +- "Failed to initialize V4L2 M2M media controller\n"); +- goto err_m2m; +- } +- + ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0); + if (ret) { + v4l2_err(&dev->v4l2_dev, "Failed to register video device\n"); +- goto err_v4l2; ++ goto err_m2m; + } + + v4l2_info(&dev->v4l2_dev, + "Device registered as /dev/video%d\n", vfd->num); + ++ ret = v4l2_m2m_register_media_controller(dev->m2m_dev, vfd, ++ MEDIA_ENT_F_PROC_VIDEO_DECODER); ++ if (ret) { ++ v4l2_err(&dev->v4l2_dev, ++ "Failed to initialize V4L2 M2M media controller\n"); ++ goto err_video; ++ } ++ + ret = media_device_register(&dev->mdev); + if (ret) { + v4l2_err(&dev->v4l2_dev, "Failed to register media device\n"); +@@ -339,10 +339,10 @@ static int cedrus_probe(struct platform_device *pdev) + + err_m2m_mc: + v4l2_m2m_unregister_media_controller(dev->m2m_dev); +-err_m2m: +- v4l2_m2m_release(dev->m2m_dev); + err_video: + video_unregister_device(&dev->vfd); ++err_m2m: ++ v4l2_m2m_release(dev->m2m_dev); + err_v4l2: + v4l2_device_unregister(&dev->v4l2_dev); + +-- +2.21.0 + diff --git a/projects/Allwinner/patches/linux/0005-media-cedrus-Add-H264-decoding-support.patch b/projects/Allwinner/patches/linux/0005-media-cedrus-Add-H264-decoding-support.patch new file mode 100644 index 0000000000..923ccba80d --- /dev/null +++ b/projects/Allwinner/patches/linux/0005-media-cedrus-Add-H264-decoding-support.patch @@ -0,0 +1,1420 @@ +Date: Thu, 4 Apr 2019 14:59:02 +0200 + +From: Pawel Osciak + +Stateless video codecs will require both the H264 metadata and slices in +order to be able to decode frames. + +This introduces the definitions for a new pixel format for H264 slices that +have been parsed, as well as the structures used to pass the metadata from +the userspace to the kernel. + +Reviewed-by: Tomasz Figa +Signed-off-by: Pawel Osciak +Signed-off-by: Guenter Roeck +Co-developed-by: Maxime Ripard +Signed-off-by: Maxime Ripard +--- + Documentation/media/uapi/v4l/biblio.rst | 9 +- + Documentation/media/uapi/v4l/ext-ctrls-codec.rst | 569 ++++++++++++++- + Documentation/media/uapi/v4l/pixfmt-compressed.rst | 19 +- + Documentation/media/uapi/v4l/vidioc-queryctrl.rst | 30 +- + Documentation/media/videodev2.h.rst.exceptions | 5 +- + drivers/media/v4l2-core/v4l2-ctrls.c | 42 +- + drivers/media/v4l2-core/v4l2-ioctl.c | 1 +- + include/media/h264-ctrls.h | 192 +++++- + include/media/v4l2-ctrls.h | 13 +- + include/uapi/linux/videodev2.h | 1 +- + 10 files changed, 880 insertions(+), 1 deletion(-) + create mode 100644 include/media/h264-ctrls.h + +diff --git a/Documentation/media/uapi/v4l/biblio.rst b/Documentation/media/uapi/v4l/biblio.rst +index ec33768c055e..8f4eb8823d82 100644 +--- a/Documentation/media/uapi/v4l/biblio.rst ++++ b/Documentation/media/uapi/v4l/biblio.rst +@@ -122,6 +122,15 @@ ITU BT.1119 + + :author: International Telecommunication Union (http://www.itu.ch) + ++.. _h264: ++ ++ITU-T Rec. H.264 Specification (04/2017 Edition) ++================================================ ++ ++:title: ITU-T Recommendation H.264 "Advanced Video Coding for Generic Audiovisual Services" ++ ++:author: International Telecommunication Union (http://www.itu.ch) ++ + .. _jfif: + + JFIF +diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst +index 6c961cfb74da..ea0a8a68759b 100644 +--- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst ++++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst +@@ -52,6 +52,25 @@ Compressed Formats + - ``V4L2_PIX_FMT_H264_MVC`` + - 'M264' + - H264 MVC video elementary stream. ++ * .. _V4L2-PIX-FMT-H264-SLICE: ++ ++ - ``V4L2_PIX_FMT_H264_SLICE_RAW`` ++ - 'S264' ++ - H264 parsed slice data, as extracted from the H264 bitstream. ++ This format is adapted for stateless video decoders that ++ implement an H264 pipeline (using the :ref:`codec` and ++ :ref:`media-request-api`). Metadata associated with the frame ++ to decode are required to be passed through the ++ ``V4L2_CID_MPEG_VIDEO_H264_SPS``, ++ ``V4L2_CID_MPEG_VIDEO_H264_PPS``, ++ ``V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX``, ++ ``V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS`` and ++ ``V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS`` controls. See the ++ :ref:`associated Codec Control IDs `. ++ Exactly one output and one capture buffer must be provided for ++ use with this pixel format. The output buffer must contain the ++ appropriate number of macroblocks to decode a full ++ corresponding frame to the matching capture buffer. + * .. _V4L2-PIX-FMT-H263: + + - ``V4L2_PIX_FMT_H263`` +diff --git a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst +index f824162d0ea9..dc500632095d 100644 +--- a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst ++++ b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst +@@ -443,6 +443,36 @@ See also the examples in :ref:`control`. + - n/a + - A struct :c:type:`v4l2_ctrl_mpeg2_quantization`, containing MPEG-2 + quantization matrices for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_H264_SPS`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_h264_sps`, containing H264 ++ sequence parameters for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_H264_PPS`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_h264_pps`, containing H264 ++ picture parameters for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_H264_SCALING_MATRIX`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_h264_scaling_matrix`, containing H264 ++ scaling matrices for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_H264_SLICE_PARAMS`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_h264_slice_params`, containing H264 ++ slice parameters for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_H264_DECODE_PARAMS`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_h264_decode_params`, containing H264 ++ decode parameters for stateless video decoders. + + .. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.7cm}| + +diff --git a/Documentation/media/videodev2.h.rst.exceptions b/Documentation/media/videodev2.h.rst.exceptions +index 64d348e67df9..55cbe324b9fc 100644 +--- a/Documentation/media/videodev2.h.rst.exceptions ++++ b/Documentation/media/videodev2.h.rst.exceptions +@@ -136,6 +136,11 @@ replace symbol V4L2_CTRL_TYPE_U32 :c:type:`v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_U8 :c:type:`v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_MPEG2_SLICE_PARAMS :c:type:`v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_MPEG2_QUANTIZATION :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_H264_SPS :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_H264_PPS :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_H264_SCALING_MATRIX :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_H264_SLICE_PARAMS :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_H264_DECODE_PARAMS :c:type:`v4l2_ctrl_type` + + # V4L2 capability defines + replace define V4L2_CAP_VIDEO_CAPTURE device-capabilities +diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c +index b1ae2e555c68..46aec8c3acde 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls.c +@@ -828,6 +828,11 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION: + return "H264 Constrained Intra Pred"; + case V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET: return "H264 Chroma QP Index Offset"; ++ case V4L2_CID_MPEG_VIDEO_H264_SPS: return "H264 Sequence Parameter Set"; ++ case V4L2_CID_MPEG_VIDEO_H264_PPS: return "H264 Picture Parameter Set"; ++ case V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX: return "H264 Scaling Matrix"; ++ case V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS: return "H264 Slice Parameters"; ++ case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: return "H264 Decode Parameters"; + case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP: return "MPEG4 I-Frame QP Value"; + case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP: return "MPEG4 P-Frame QP Value"; + case V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP: return "MPEG4 B-Frame QP Value"; +@@ -1309,6 +1314,21 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, + case V4L2_CID_MPEG_VIDEO_FWHT_PARAMS: + *type = V4L2_CTRL_TYPE_FWHT_PARAMS; + break; ++ case V4L2_CID_MPEG_VIDEO_H264_SPS: ++ *type = V4L2_CTRL_TYPE_H264_SPS; ++ break; ++ case V4L2_CID_MPEG_VIDEO_H264_PPS: ++ *type = V4L2_CTRL_TYPE_H264_PPS; ++ break; ++ case V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX: ++ *type = V4L2_CTRL_TYPE_H264_SCALING_MATRIX; ++ break; ++ case V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS: ++ *type = V4L2_CTRL_TYPE_H264_SLICE_PARAMS; ++ break; ++ case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: ++ *type = V4L2_CTRL_TYPE_H264_DECODE_PARAMS; ++ break; + default: + *type = V4L2_CTRL_TYPE_INTEGER; + break; +@@ -1678,6 +1698,13 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, + case V4L2_CTRL_TYPE_FWHT_PARAMS: + return 0; + ++ case V4L2_CTRL_TYPE_H264_SPS: ++ case V4L2_CTRL_TYPE_H264_PPS: ++ case V4L2_CTRL_TYPE_H264_SCALING_MATRIX: ++ case V4L2_CTRL_TYPE_H264_SLICE_PARAMS: ++ case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: ++ return 0; ++ + default: + return -EINVAL; + } +@@ -2261,6 +2288,21 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, + case V4L2_CTRL_TYPE_FWHT_PARAMS: + elem_size = sizeof(struct v4l2_ctrl_fwht_params); + break; ++ case V4L2_CTRL_TYPE_H264_SPS: ++ elem_size = sizeof(struct v4l2_ctrl_h264_sps); ++ break; ++ case V4L2_CTRL_TYPE_H264_PPS: ++ elem_size = sizeof(struct v4l2_ctrl_h264_pps); ++ break; ++ case V4L2_CTRL_TYPE_H264_SCALING_MATRIX: ++ elem_size = sizeof(struct v4l2_ctrl_h264_scaling_matrix); ++ break; ++ case V4L2_CTRL_TYPE_H264_SLICE_PARAMS: ++ elem_size = sizeof(struct v4l2_ctrl_h264_slice_params); ++ break; ++ case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: ++ elem_size = sizeof(struct v4l2_ctrl_h264_decode_params); ++ break; + default: + if (type < V4L2_CTRL_COMPOUND_TYPES) + elem_size = sizeof(s32); +diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c +index ac87c3e37280..f6e1254064d2 100644 +--- a/drivers/media/v4l2-core/v4l2-ioctl.c ++++ b/drivers/media/v4l2-core/v4l2-ioctl.c +@@ -1325,6 +1325,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) + case V4L2_PIX_FMT_H264: descr = "H.264"; break; + case V4L2_PIX_FMT_H264_NO_SC: descr = "H.264 (No Start Codes)"; break; + case V4L2_PIX_FMT_H264_MVC: descr = "H.264 MVC"; break; ++ case V4L2_PIX_FMT_H264_SLICE_RAW: descr = "H.264 Parsed Slice Data"; break; + case V4L2_PIX_FMT_H263: descr = "H.263"; break; + case V4L2_PIX_FMT_MPEG1: descr = "MPEG-1 ES"; break; + case V4L2_PIX_FMT_MPEG2: descr = "MPEG-2 ES"; break; +diff --git a/include/media/h264-ctrls.h b/include/media/h264-ctrls.h +new file mode 100644 +index 000000000000..e2f83b3cdbef +--- /dev/null ++++ b/include/media/h264-ctrls.h +@@ -0,0 +1,192 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * These are the H.264 state controls for use with stateless H.264 ++ * codec drivers. ++ * ++ * It turns out that these structs are not stable yet and will undergo ++ * more changes. So keep them private until they are stable and ready to ++ * become part of the official public API. ++ */ ++ ++#ifndef _H264_CTRLS_H_ ++#define _H264_CTRLS_H_ ++ ++/* ++ * This is put insanely high to avoid conflicting with controls that ++ * would be added during the phase where those controls are not ++ * stable. It should be fixed eventually. ++ */ ++#define V4L2_CID_MPEG_VIDEO_H264_SPS (V4L2_CID_MPEG_BASE+1000) ++#define V4L2_CID_MPEG_VIDEO_H264_PPS (V4L2_CID_MPEG_BASE+1001) ++#define V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (V4L2_CID_MPEG_BASE+1002) ++#define V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS (V4L2_CID_MPEG_BASE+1003) ++#define V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS (V4L2_CID_MPEG_BASE+1004) ++ ++/* enum v4l2_ctrl_type type values */ ++#define V4L2_CTRL_TYPE_H264_SPS 0x0110 ++#define V4L2_CTRL_TYPE_H264_PPS 0x0111 ++#define V4L2_CTRL_TYPE_H264_SCALING_MATRIX 0x0112 ++#define V4L2_CTRL_TYPE_H264_SLICE_PARAMS 0x0113 ++#define V4L2_CTRL_TYPE_H264_DECODE_PARAMS 0x0114 ++ ++#define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG 0x01 ++#define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG 0x02 ++#define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG 0x04 ++#define V4L2_H264_SPS_CONSTRAINT_SET3_FLAG 0x08 ++#define V4L2_H264_SPS_CONSTRAINT_SET4_FLAG 0x10 ++#define V4L2_H264_SPS_CONSTRAINT_SET5_FLAG 0x20 ++ ++#define V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE 0x01 ++#define V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS 0x02 ++#define V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO 0x04 ++#define V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED 0x08 ++#define V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY 0x10 ++#define V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD 0x20 ++#define V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE 0x40 ++ ++struct v4l2_ctrl_h264_sps { ++ __u8 profile_idc; ++ __u8 constraint_set_flags; ++ __u8 level_idc; ++ __u8 seq_parameter_set_id; ++ __u8 chroma_format_idc; ++ __u8 bit_depth_luma_minus8; ++ __u8 bit_depth_chroma_minus8; ++ __u8 log2_max_frame_num_minus4; ++ __u8 pic_order_cnt_type; ++ __u8 log2_max_pic_order_cnt_lsb_minus4; ++ __u8 max_num_ref_frames; ++ __u8 num_ref_frames_in_pic_order_cnt_cycle; ++ __s32 offset_for_ref_frame[255]; ++ __s32 offset_for_non_ref_pic; ++ __s32 offset_for_top_to_bottom_field; ++ __u16 pic_width_in_mbs_minus1; ++ __u16 pic_height_in_map_units_minus1; ++ __u32 flags; ++}; ++ ++#define V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE 0x0001 ++#define V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT 0x0002 ++#define V4L2_H264_PPS_FLAG_WEIGHTED_PRED 0x0004 ++#define V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT 0x0008 ++#define V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED 0x0010 ++#define V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT 0x0020 ++#define V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE 0x0040 ++#define V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT 0x0080 ++ ++struct v4l2_ctrl_h264_pps { ++ __u8 pic_parameter_set_id; ++ __u8 seq_parameter_set_id; ++ __u8 num_slice_groups_minus1; ++ __u8 num_ref_idx_l0_default_active_minus1; ++ __u8 num_ref_idx_l1_default_active_minus1; ++ __u8 weighted_bipred_idc; ++ __s8 pic_init_qp_minus26; ++ __s8 pic_init_qs_minus26; ++ __s8 chroma_qp_index_offset; ++ __s8 second_chroma_qp_index_offset; ++ __u16 flags; ++}; ++ ++struct v4l2_ctrl_h264_scaling_matrix { ++ __u8 scaling_list_4x4[6][16]; ++ __u8 scaling_list_8x8[6][64]; ++}; ++ ++struct v4l2_h264_weight_factors { ++ __s16 luma_weight[32]; ++ __s16 luma_offset[32]; ++ __s16 chroma_weight[32][2]; ++ __s16 chroma_offset[32][2]; ++}; ++ ++struct v4l2_h264_pred_weight_table { ++ __u16 luma_log2_weight_denom; ++ __u16 chroma_log2_weight_denom; ++ struct v4l2_h264_weight_factors weight_factors[2]; ++}; ++ ++#define V4L2_H264_SLICE_TYPE_P 0 ++#define V4L2_H264_SLICE_TYPE_B 1 ++#define V4L2_H264_SLICE_TYPE_I 2 ++#define V4L2_H264_SLICE_TYPE_SP 3 ++#define V4L2_H264_SLICE_TYPE_SI 4 ++ ++#define V4L2_H264_SLICE_FLAG_FIELD_PIC 0x01 ++#define V4L2_H264_SLICE_FLAG_BOTTOM_FIELD 0x02 ++#define V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED 0x04 ++#define V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH 0x08 ++ ++struct v4l2_ctrl_h264_slice_params { ++ /* Size in bytes, including header */ ++ __u32 size; ++ /* Offset in bits to slice_data() from the beginning of this slice. */ ++ __u32 header_bit_size; ++ ++ __u16 first_mb_in_slice; ++ __u8 slice_type; ++ __u8 pic_parameter_set_id; ++ __u8 colour_plane_id; ++ __u8 redundant_pic_cnt; ++ __u16 frame_num; ++ __u16 idr_pic_id; ++ __u16 pic_order_cnt_lsb; ++ __s32 delta_pic_order_cnt_bottom; ++ __s32 delta_pic_order_cnt0; ++ __s32 delta_pic_order_cnt1; ++ ++ struct v4l2_h264_pred_weight_table pred_weight_table; ++ /* Size in bits of dec_ref_pic_marking() syntax element. */ ++ __u32 dec_ref_pic_marking_bit_size; ++ /* Size in bits of pic order count syntax. */ ++ __u32 pic_order_cnt_bit_size; ++ ++ __u8 cabac_init_idc; ++ __s8 slice_qp_delta; ++ __s8 slice_qs_delta; ++ __u8 disable_deblocking_filter_idc; ++ __s8 slice_alpha_c0_offset_div2; ++ __s8 slice_beta_offset_div2; ++ __u8 num_ref_idx_l0_active_minus1; ++ __u8 num_ref_idx_l1_active_minus1; ++ __u32 slice_group_change_cycle; ++ ++ /* ++ * Entries on each list are indices into ++ * v4l2_ctrl_h264_decode_params.dpb[]. ++ */ ++ __u8 ref_pic_list0[32]; ++ __u8 ref_pic_list1[32]; ++ ++ __u32 flags; ++}; ++ ++#define V4L2_H264_DPB_ENTRY_FLAG_VALID 0x01 ++#define V4L2_H264_DPB_ENTRY_FLAG_ACTIVE 0x02 ++#define V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM 0x04 ++ ++struct v4l2_h264_dpb_entry { ++ __u64 reference_ts; ++ __u16 frame_num; ++ __u16 pic_num; ++ /* Note that field is indicated by v4l2_buffer.field */ ++ __s32 top_field_order_cnt; ++ __s32 bottom_field_order_cnt; ++ __u32 flags; /* V4L2_H264_DPB_ENTRY_FLAG_* */ ++}; ++ ++#define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC 0x01 ++ ++struct v4l2_ctrl_h264_decode_params { ++ struct v4l2_h264_dpb_entry dpb[16]; ++ __u16 num_slices; ++ __u16 nal_ref_idc; ++ __u8 ref_pic_list_p0[32]; ++ __u8 ref_pic_list_b0[32]; ++ __u8 ref_pic_list_b1[32]; ++ __s32 top_field_order_cnt; ++ __s32 bottom_field_order_cnt; ++ __u32 flags; /* V4L2_H264_DECODE_PARAM_FLAG_* */ ++}; ++ ++#endif +diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h +index bd621cec65a5..dce6f33fd749 100644 +--- a/include/media/v4l2-ctrls.h ++++ b/include/media/v4l2-ctrls.h +@@ -23,11 +23,12 @@ + #include + + /* +- * Include the mpeg2 and fwht stateless codec compound control definitions. ++ * Include the stateless codec compound control definitions. + * This will move to the public headers once this API is fully stable. + */ + #include + #include ++#include + + /* forward references */ + struct file; +@@ -51,6 +52,11 @@ struct poll_table_struct; + * @p_mpeg2_slice_params: Pointer to a MPEG2 slice parameters structure. + * @p_mpeg2_quantization: Pointer to a MPEG2 quantization data structure. + * @p_fwht_params: Pointer to a FWHT stateless parameters structure. ++ * @p_h264_sps: Pointer to a struct v4l2_ctrl_h264_sps. ++ * @p_h264_pps: Pointer to a struct v4l2_ctrl_h264_pps. ++ * @p_h264_scaling_matrix: Pointer to a struct v4l2_ctrl_h264_scaling_matrix. ++ * @p_h264_slice_param: Pointer to a struct v4l2_ctrl_h264_slice_params. ++ * @p_h264_decode_param: Pointer to a struct v4l2_ctrl_h264_decode_params. + * @p: Pointer to a compound value. + */ + union v4l2_ctrl_ptr { +@@ -63,6 +69,11 @@ union v4l2_ctrl_ptr { + struct v4l2_ctrl_mpeg2_slice_params *p_mpeg2_slice_params; + struct v4l2_ctrl_mpeg2_quantization *p_mpeg2_quantization; + struct v4l2_ctrl_fwht_params *p_fwht_params; ++ struct v4l2_ctrl_h264_sps *p_h264_sps; ++ struct v4l2_ctrl_h264_pps *p_h264_pps; ++ struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix; ++ struct v4l2_ctrl_h264_slice_params *p_h264_slice_param; ++ struct v4l2_ctrl_h264_decode_params *p_h264_decode_param; + void *p; + }; + +diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h +index 496e6453450c..838732acdefc 100644 +--- a/include/uapi/linux/videodev2.h ++++ b/include/uapi/linux/videodev2.h +@@ -657,6 +657,7 @@ struct v4l2_pix_format { + #define V4L2_PIX_FMT_H264 v4l2_fourcc('H', '2', '6', '4') /* H264 with start codes */ + #define V4L2_PIX_FMT_H264_NO_SC v4l2_fourcc('A', 'V', 'C', '1') /* H264 without start codes */ + #define V4L2_PIX_FMT_H264_MVC v4l2_fourcc('M', '2', '6', '4') /* H264 MVC */ ++#define V4L2_PIX_FMT_H264_SLICE_RAW v4l2_fourcc('S', '2', '6', '4') /* H264 parsed slices */ + #define V4L2_PIX_FMT_H263 v4l2_fourcc('H', '2', '6', '3') /* H263 */ + #define V4L2_PIX_FMT_MPEG1 v4l2_fourcc('M', 'P', 'G', '1') /* MPEG-1 ES */ + #define V4L2_PIX_FMT_MPEG2 v4l2_fourcc('M', 'P', 'G', '2') /* MPEG-2 ES */ +From patchwork Thu Apr 4 12:59:03 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [v8,2/2] media: cedrus: Add H264 decoding support +From: Maxime Ripard +X-Patchwork-Id: 55457 +Message-Id: <157519b5571e24c9ef4189d30f8434b5b61121b1.1554382670.git-series.maxime.ripard@bootlin.com> +X-Patchwork-Delegate: hverkuil@xs4all.nl +To: hans.verkuil@cisco.com, acourbot@chromium.org, + sakari.ailus@linux.intel.com, + Laurent Pinchart +Cc: tfiga@chromium.org, posciak@chromium.org, + Paul Kocialkowski , + Chen-Yu Tsai , linux-kernel@vger.kernel.org, + linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, + nicolas.dufresne@collabora.com, jenskuske@gmail.com, + jernej.skrabec@gmail.com, jonas@kwiboo.se, ezequiel@collabora.com, + linux-sunxi@googlegroups.com, + Thomas Petazzoni , + Maxime Ripard , + Jernej Skrabec +Date: Thu, 4 Apr 2019 14:59:03 +0200 + +Introduce some basic H264 decoding support in cedrus. So far, only the +baseline profile videos have been tested, and some more advanced features +used in higher profiles are not even implemented. + +Reviewed-by: Jernej Skrabec +Signed-off-by: Maxime Ripard +--- + drivers/staging/media/sunxi/cedrus/Makefile | 3 +- + drivers/staging/media/sunxi/cedrus/cedrus.c | 31 +- + drivers/staging/media/sunxi/cedrus/cedrus.h | 38 +- + drivers/staging/media/sunxi/cedrus/cedrus_dec.c | 13 +- + drivers/staging/media/sunxi/cedrus/cedrus_h264.c | 574 +++++++++++++++- + drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 4 +- + drivers/staging/media/sunxi/cedrus/cedrus_regs.h | 91 ++- + drivers/staging/media/sunxi/cedrus/cedrus_video.c | 9 +- + 8 files changed, 761 insertions(+), 2 deletions(-) + create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_h264.c + +diff --git a/drivers/staging/media/sunxi/cedrus/Makefile b/drivers/staging/media/sunxi/cedrus/Makefile +index 808842f0119e..c85ac6db0302 100644 +--- a/drivers/staging/media/sunxi/cedrus/Makefile ++++ b/drivers/staging/media/sunxi/cedrus/Makefile +@@ -1,4 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += sunxi-cedrus.o + +-sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o cedrus_mpeg2.o ++sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o \ ++ cedrus_mpeg2.o cedrus_h264.o +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c +index b98add3cdedd..d613f5c24a2f 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c +@@ -40,6 +40,36 @@ static const struct cedrus_control cedrus_controls[] = { + .codec = CEDRUS_CODEC_MPEG2, + .required = false, + }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS, ++ .elem_size = sizeof(struct v4l2_ctrl_h264_decode_params), ++ .codec = CEDRUS_CODEC_H264, ++ .required = true, ++ }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS, ++ .elem_size = sizeof(struct v4l2_ctrl_h264_slice_params), ++ .codec = CEDRUS_CODEC_H264, ++ .required = true, ++ }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_H264_SPS, ++ .elem_size = sizeof(struct v4l2_ctrl_h264_sps), ++ .codec = CEDRUS_CODEC_H264, ++ .required = true, ++ }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_H264_PPS, ++ .elem_size = sizeof(struct v4l2_ctrl_h264_pps), ++ .codec = CEDRUS_CODEC_H264, ++ .required = true, ++ }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX, ++ .elem_size = sizeof(struct v4l2_ctrl_h264_scaling_matrix), ++ .codec = CEDRUS_CODEC_H264, ++ .required = true, ++ }, + }; + + #define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls) +@@ -278,6 +308,7 @@ static int cedrus_probe(struct platform_device *pdev) + } + + dev->dec_ops[CEDRUS_CODEC_MPEG2] = &cedrus_dec_ops_mpeg2; ++ dev->dec_ops[CEDRUS_CODEC_H264] = &cedrus_dec_ops_h264; + + mutex_init(&dev->dev_mutex); + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h +index c57c04b41d2e..bef79f630520 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h +@@ -32,7 +32,7 @@ + + enum cedrus_codec { + CEDRUS_CODEC_MPEG2, +- ++ CEDRUS_CODEC_H264, + CEDRUS_CODEC_LAST, + }; + +@@ -42,6 +42,12 @@ enum cedrus_irq_status { + CEDRUS_IRQ_OK, + }; + ++enum cedrus_h264_pic_type { ++ CEDRUS_H264_PIC_TYPE_FRAME = 0, ++ CEDRUS_H264_PIC_TYPE_FIELD, ++ CEDRUS_H264_PIC_TYPE_MBAFF, ++}; ++ + struct cedrus_control { + u32 id; + u32 elem_size; +@@ -49,6 +55,14 @@ struct cedrus_control { + unsigned char required:1; + }; + ++struct cedrus_h264_run { ++ const struct v4l2_ctrl_h264_decode_params *decode_params; ++ const struct v4l2_ctrl_h264_pps *pps; ++ const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; ++ const struct v4l2_ctrl_h264_slice_params *slice_params; ++ const struct v4l2_ctrl_h264_sps *sps; ++}; ++ + struct cedrus_mpeg2_run { + const struct v4l2_ctrl_mpeg2_slice_params *slice_params; + const struct v4l2_ctrl_mpeg2_quantization *quantization; +@@ -59,12 +73,20 @@ struct cedrus_run { + struct vb2_v4l2_buffer *dst; + + union { ++ struct cedrus_h264_run h264; + struct cedrus_mpeg2_run mpeg2; + }; + }; + + struct cedrus_buffer { + struct v4l2_m2m_buffer m2m_buf; ++ ++ union { ++ struct { ++ unsigned int position; ++ enum cedrus_h264_pic_type pic_type; ++ } h264; ++ } codec; + }; + + struct cedrus_ctx { +@@ -79,6 +101,19 @@ struct cedrus_ctx { + struct v4l2_ctrl **ctrls; + + struct vb2_buffer *dst_bufs[VIDEO_MAX_FRAME]; ++ ++ union { ++ struct { ++ void *mv_col_buf; ++ dma_addr_t mv_col_buf_dma; ++ ssize_t mv_col_buf_field_size; ++ ssize_t mv_col_buf_size; ++ void *pic_info_buf; ++ dma_addr_t pic_info_buf_dma; ++ void *neighbor_info_buf; ++ dma_addr_t neighbor_info_buf_dma; ++ } h264; ++ } codec; + }; + + struct cedrus_dec_ops { +@@ -121,6 +156,7 @@ struct cedrus_dev { + }; + + extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2; ++extern struct cedrus_dec_ops cedrus_dec_ops_h264; + + static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val) + { +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +index 4d6d602cdde6..bdad87eb9d79 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +@@ -46,6 +46,19 @@ void cedrus_device_run(void *priv) + V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION); + break; + ++ case V4L2_PIX_FMT_H264_SLICE_RAW: ++ run.h264.decode_params = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS); ++ run.h264.pps = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_H264_PPS); ++ run.h264.scaling_matrix = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX); ++ run.h264.slice_params = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS); ++ run.h264.sps = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_H264_SPS); ++ break; ++ + default: + break; + } +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +new file mode 100644 +index 000000000000..2c98a3e46d2b +--- /dev/null ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +@@ -0,0 +1,574 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Cedrus VPU driver ++ * ++ * Copyright (c) 2013 Jens Kuske ++ * Copyright (c) 2018 Bootlin ++ */ ++ ++#include ++ ++#include ++ ++#include "cedrus.h" ++#include "cedrus_hw.h" ++#include "cedrus_regs.h" ++ ++enum cedrus_h264_sram_off { ++ CEDRUS_SRAM_H264_PRED_WEIGHT_TABLE = 0x000, ++ CEDRUS_SRAM_H264_FRAMEBUFFER_LIST = 0x100, ++ CEDRUS_SRAM_H264_REF_LIST_0 = 0x190, ++ CEDRUS_SRAM_H264_REF_LIST_1 = 0x199, ++ CEDRUS_SRAM_H264_SCALING_LIST_8x8_0 = 0x200, ++ CEDRUS_SRAM_H264_SCALING_LIST_8x8_1 = 0x210, ++ CEDRUS_SRAM_H264_SCALING_LIST_4x4 = 0x220, ++}; ++ ++struct cedrus_h264_sram_ref_pic { ++ __le32 top_field_order_cnt; ++ __le32 bottom_field_order_cnt; ++ __le32 frame_info; ++ __le32 luma_ptr; ++ __le32 chroma_ptr; ++ __le32 mv_col_top_ptr; ++ __le32 mv_col_bot_ptr; ++ __le32 reserved; ++} __packed; ++ ++#define CEDRUS_H264_FRAME_NUM 18 ++ ++#define CEDRUS_NEIGHBOR_INFO_BUF_SIZE (16 * SZ_1K) ++#define CEDRUS_PIC_INFO_BUF_SIZE (128 * SZ_1K) ++ ++static void cedrus_h264_write_sram(struct cedrus_dev *dev, ++ enum cedrus_h264_sram_off off, ++ const void *data, size_t len) ++{ ++ const u32 *buffer = data; ++ size_t count = DIV_ROUND_UP(len, 4); ++ ++ cedrus_write(dev, VE_AVC_SRAM_PORT_OFFSET, off << 2); ++ ++ while (count--) ++ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, *buffer++); ++} ++ ++static dma_addr_t cedrus_h264_mv_col_buf_addr(struct cedrus_ctx *ctx, ++ unsigned int position, ++ unsigned int field) ++{ ++ dma_addr_t addr = ctx->codec.h264.mv_col_buf_dma; ++ ++ /* Adjust for the position */ ++ addr += position * ctx->codec.h264.mv_col_buf_field_size * 2; ++ ++ /* Adjust for the field */ ++ addr += field * ctx->codec.h264.mv_col_buf_field_size; ++ ++ return addr; ++} ++ ++static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx, ++ struct cedrus_buffer *buf, ++ unsigned int top_field_order_cnt, ++ unsigned int bottom_field_order_cnt, ++ struct cedrus_h264_sram_ref_pic *pic) ++{ ++ struct vb2_buffer *vbuf = &buf->m2m_buf.vb.vb2_buf; ++ unsigned int position = buf->codec.h264.position; ++ ++ pic->top_field_order_cnt = top_field_order_cnt; ++ pic->bottom_field_order_cnt = bottom_field_order_cnt; ++ pic->frame_info = buf->codec.h264.pic_type << 8; ++ ++ pic->luma_ptr = cedrus_buf_addr(vbuf, &ctx->dst_fmt, 0); ++ pic->chroma_ptr = cedrus_buf_addr(vbuf, &ctx->dst_fmt, 1); ++ pic->mv_col_top_ptr = cedrus_h264_mv_col_buf_addr(ctx, position, 0); ++ pic->mv_col_bot_ptr = cedrus_h264_mv_col_buf_addr(ctx, position, 1); ++} ++ ++static void cedrus_write_frame_list(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ struct cedrus_h264_sram_ref_pic pic_list[CEDRUS_H264_FRAME_NUM]; ++ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; ++ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; ++ const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; ++ struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; ++ struct cedrus_buffer *output_buf; ++ struct cedrus_dev *dev = ctx->dev; ++ unsigned long used_dpbs = 0; ++ unsigned int position; ++ unsigned int output = 0; ++ unsigned int i; ++ ++ memset(pic_list, 0, sizeof(pic_list)); ++ ++ for (i = 0; i < ARRAY_SIZE(decode->dpb); i++) { ++ const struct v4l2_h264_dpb_entry *dpb = &decode->dpb[i]; ++ struct cedrus_buffer *cedrus_buf; ++ int buf_idx; ++ ++ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID)) ++ continue; ++ ++ buf_idx = vb2_find_timestamp(cap_q, dpb->reference_ts, 0); ++ if (buf_idx < 0) ++ continue; ++ ++ cedrus_buf = vb2_to_cedrus_buffer(ctx->dst_bufs[buf_idx]); ++ position = cedrus_buf->codec.h264.position; ++ used_dpbs |= BIT(position); ++ ++ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) ++ continue; ++ ++ cedrus_fill_ref_pic(ctx, cedrus_buf, ++ dpb->top_field_order_cnt, ++ dpb->bottom_field_order_cnt, ++ &pic_list[position]); ++ ++ output = max(position, output); ++ } ++ ++ position = find_next_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM, ++ output); ++ if (position >= CEDRUS_H264_FRAME_NUM) ++ position = find_first_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM); ++ ++ output_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf); ++ output_buf->codec.h264.position = position; ++ ++ if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) ++ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FIELD; ++ else if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) ++ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_MBAFF; ++ else ++ output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FRAME; ++ ++ cedrus_fill_ref_pic(ctx, output_buf, ++ decode->top_field_order_cnt, ++ decode->bottom_field_order_cnt, ++ &pic_list[position]); ++ ++ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_FRAMEBUFFER_LIST, ++ pic_list, sizeof(pic_list)); ++ ++ cedrus_write(dev, VE_H264_OUTPUT_FRAME_IDX, position); ++} ++ ++#define CEDRUS_MAX_REF_IDX 32 ++ ++static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, ++ struct cedrus_run *run, ++ const u8 *ref_list, u8 num_ref, ++ enum cedrus_h264_sram_off sram) ++{ ++ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; ++ struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; ++ struct cedrus_dev *dev = ctx->dev; ++ u8 sram_array[CEDRUS_MAX_REF_IDX]; ++ unsigned int i; ++ size_t size; ++ ++ memset(sram_array, 0, sizeof(sram_array)); ++ ++ for (i = 0; i < num_ref; i++) { ++ const struct v4l2_h264_dpb_entry *dpb; ++ const struct cedrus_buffer *cedrus_buf; ++ const struct vb2_v4l2_buffer *ref_buf; ++ unsigned int position; ++ int buf_idx; ++ u8 dpb_idx; ++ ++ dpb_idx = ref_list[i]; ++ dpb = &decode->dpb[dpb_idx]; ++ ++ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) ++ continue; ++ ++ buf_idx = vb2_find_timestamp(cap_q, dpb->reference_ts, 0); ++ if (buf_idx < 0) ++ continue; ++ ++ ref_buf = to_vb2_v4l2_buffer(ctx->dst_bufs[buf_idx]); ++ cedrus_buf = vb2_v4l2_to_cedrus_buffer(ref_buf); ++ position = cedrus_buf->codec.h264.position; ++ ++ sram_array[i] |= position << 1; ++ if (ref_buf->field == V4L2_FIELD_BOTTOM) ++ sram_array[i] |= BIT(0); ++ } ++ ++ size = min_t(size_t, ALIGN(num_ref, 4), sizeof(sram_array)); ++ cedrus_h264_write_sram(dev, sram, &sram_array, size); ++} ++ ++static void cedrus_write_ref_list0(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; ++ ++ _cedrus_write_ref_list(ctx, run, ++ slice->ref_pic_list0, ++ slice->num_ref_idx_l0_active_minus1 + 1, ++ CEDRUS_SRAM_H264_REF_LIST_0); ++} ++ ++static void cedrus_write_ref_list1(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; ++ ++ _cedrus_write_ref_list(ctx, run, ++ slice->ref_pic_list1, ++ slice->num_ref_idx_l1_active_minus1 + 1, ++ CEDRUS_SRAM_H264_REF_LIST_1); ++} ++ ++static void cedrus_write_scaling_lists(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_h264_scaling_matrix *scaling = ++ run->h264.scaling_matrix; ++ struct cedrus_dev *dev = ctx->dev; ++ ++ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_8x8_0, ++ scaling->scaling_list_8x8[0], ++ sizeof(scaling->scaling_list_8x8[0])); ++ ++ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_8x8_1, ++ scaling->scaling_list_8x8[3], ++ sizeof(scaling->scaling_list_8x8[3])); ++ ++ cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_4x4, ++ scaling->scaling_list_4x4, ++ sizeof(scaling->scaling_list_4x4)); ++} ++ ++static void cedrus_write_pred_weight_table(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_h264_slice_params *slice = ++ run->h264.slice_params; ++ const struct v4l2_h264_pred_weight_table *pred_weight = ++ &slice->pred_weight_table; ++ struct cedrus_dev *dev = ctx->dev; ++ int i, j, k; ++ ++ cedrus_write(dev, VE_H264_SHS_WP, ++ ((pred_weight->chroma_log2_weight_denom & 0x7) << 4) | ++ ((pred_weight->luma_log2_weight_denom & 0x7) << 0)); ++ ++ cedrus_write(dev, VE_AVC_SRAM_PORT_OFFSET, ++ CEDRUS_SRAM_H264_PRED_WEIGHT_TABLE << 2); ++ ++ for (i = 0; i < ARRAY_SIZE(pred_weight->weight_factors); i++) { ++ const struct v4l2_h264_weight_factors *factors = ++ &pred_weight->weight_factors[i]; ++ ++ for (j = 0; j < ARRAY_SIZE(factors->luma_weight); j++) { ++ u32 val; ++ ++ val = (((u32)factors->luma_offset[j] & 0x1ff) << 16) | ++ (factors->luma_weight[j] & 0x1ff); ++ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, val); ++ } ++ ++ for (j = 0; j < ARRAY_SIZE(factors->chroma_weight); j++) { ++ for (k = 0; k < ARRAY_SIZE(factors->chroma_weight[0]); k++) { ++ u32 val; ++ ++ val = (((u32)factors->chroma_offset[j][k] & 0x1ff) << 16) | ++ (factors->chroma_weight[j][k] & 0x1ff); ++ cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, val); ++ } ++ } ++ } ++} ++ ++static void cedrus_set_params(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; ++ const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; ++ const struct v4l2_ctrl_h264_pps *pps = run->h264.pps; ++ const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; ++ struct vb2_buffer *src_buf = &run->src->vb2_buf; ++ struct cedrus_dev *dev = ctx->dev; ++ dma_addr_t src_buf_addr; ++ u32 offset = slice->header_bit_size; ++ u32 len = (slice->size * 8) - offset; ++ u32 reg; ++ ++ cedrus_write(dev, VE_H264_VLD_LEN, len); ++ cedrus_write(dev, VE_H264_VLD_OFFSET, offset); ++ ++ src_buf_addr = vb2_dma_contig_plane_dma_addr(src_buf, 0); ++ cedrus_write(dev, VE_H264_VLD_END, ++ src_buf_addr + vb2_get_plane_payload(src_buf, 0)); ++ cedrus_write(dev, VE_H264_VLD_ADDR, ++ VE_H264_VLD_ADDR_VAL(src_buf_addr) | ++ VE_H264_VLD_ADDR_FIRST | VE_H264_VLD_ADDR_VALID | ++ VE_H264_VLD_ADDR_LAST); ++ ++ /* ++ * FIXME: Since the bitstream parsing is done in software, and ++ * in userspace, this shouldn't be needed anymore. But it ++ * turns out that removing it breaks the decoding process, ++ * without any clear indication why. ++ */ ++ cedrus_write(dev, VE_H264_TRIGGER_TYPE, ++ VE_H264_TRIGGER_TYPE_INIT_SWDEC); ++ ++ if (((pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && ++ (slice->slice_type == V4L2_H264_SLICE_TYPE_P || ++ slice->slice_type == V4L2_H264_SLICE_TYPE_SP)) || ++ (pps->weighted_bipred_idc == 1 && ++ slice->slice_type == V4L2_H264_SLICE_TYPE_B)) ++ cedrus_write_pred_weight_table(ctx, run); ++ ++ if ((slice->slice_type == V4L2_H264_SLICE_TYPE_P) || ++ (slice->slice_type == V4L2_H264_SLICE_TYPE_SP) || ++ (slice->slice_type == V4L2_H264_SLICE_TYPE_B)) ++ cedrus_write_ref_list0(ctx, run); ++ ++ if (slice->slice_type == V4L2_H264_SLICE_TYPE_B) ++ cedrus_write_ref_list1(ctx, run); ++ ++ // picture parameters ++ reg = 0; ++ /* ++ * FIXME: the kernel headers are allowing the default value to ++ * be passed, but the libva doesn't give us that. ++ */ ++ reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 10; ++ reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 5; ++ reg |= (pps->weighted_bipred_idc & 0x3) << 2; ++ if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) ++ reg |= VE_H264_PPS_ENTROPY_CODING_MODE; ++ if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) ++ reg |= VE_H264_PPS_WEIGHTED_PRED; ++ if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) ++ reg |= VE_H264_PPS_CONSTRAINED_INTRA_PRED; ++ if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) ++ reg |= VE_H264_PPS_TRANSFORM_8X8_MODE; ++ cedrus_write(dev, VE_H264_PPS, reg); ++ ++ // sequence parameters ++ reg = 0; ++ reg |= (sps->chroma_format_idc & 0x7) << 19; ++ reg |= (sps->pic_width_in_mbs_minus1 & 0xff) << 8; ++ reg |= sps->pic_height_in_map_units_minus1 & 0xff; ++ if (sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) ++ reg |= VE_H264_SPS_MBS_ONLY; ++ if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) ++ reg |= VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD; ++ if (sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) ++ reg |= VE_H264_SPS_DIRECT_8X8_INFERENCE; ++ cedrus_write(dev, VE_H264_SPS, reg); ++ ++ // slice parameters ++ reg = 0; ++ reg |= decode->nal_ref_idc ? BIT(12) : 0; ++ reg |= (slice->slice_type & 0xf) << 8; ++ reg |= slice->cabac_init_idc & 0x3; ++ reg |= VE_H264_SHS_FIRST_SLICE_IN_PIC; ++ if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) ++ reg |= VE_H264_SHS_FIELD_PIC; ++ if (slice->flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) ++ reg |= VE_H264_SHS_BOTTOM_FIELD; ++ if (slice->flags & V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED) ++ reg |= VE_H264_SHS_DIRECT_SPATIAL_MV_PRED; ++ cedrus_write(dev, VE_H264_SHS, reg); ++ ++ reg = 0; ++ reg |= VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD; ++ reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 24; ++ reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 16; ++ reg |= (slice->disable_deblocking_filter_idc & 0x3) << 8; ++ reg |= (slice->slice_alpha_c0_offset_div2 & 0xf) << 4; ++ reg |= slice->slice_beta_offset_div2 & 0xf; ++ cedrus_write(dev, VE_H264_SHS2, reg); ++ ++ reg = 0; ++ reg |= (pps->second_chroma_qp_index_offset & 0x3f) << 16; ++ reg |= (pps->chroma_qp_index_offset & 0x3f) << 8; ++ reg |= (pps->pic_init_qp_minus26 + 26 + slice->slice_qp_delta) & 0x3f; ++ cedrus_write(dev, VE_H264_SHS_QP, reg); ++ ++ // clear status flags ++ cedrus_write(dev, VE_H264_STATUS, cedrus_read(dev, VE_H264_STATUS)); ++ ++ // enable int ++ cedrus_write(dev, VE_H264_CTRL, ++ VE_H264_CTRL_SLICE_DECODE_INT | ++ VE_H264_CTRL_DECODE_ERR_INT | ++ VE_H264_CTRL_VLD_DATA_REQ_INT); ++} ++ ++static enum cedrus_irq_status ++cedrus_h264_irq_status(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ u32 reg = cedrus_read(dev, VE_H264_STATUS); ++ ++ if (reg & (VE_H264_STATUS_DECODE_ERR_INT | ++ VE_H264_STATUS_VLD_DATA_REQ_INT)) ++ return CEDRUS_IRQ_ERROR; ++ ++ if (reg & VE_H264_CTRL_SLICE_DECODE_INT) ++ return CEDRUS_IRQ_OK; ++ ++ return CEDRUS_IRQ_NONE; ++} ++ ++static void cedrus_h264_irq_clear(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ ++ cedrus_write(dev, VE_H264_STATUS, ++ VE_H264_STATUS_INT_MASK); ++} ++ ++static void cedrus_h264_irq_disable(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ u32 reg = cedrus_read(dev, VE_H264_CTRL); ++ ++ cedrus_write(dev, VE_H264_CTRL, ++ reg & ~VE_H264_CTRL_INT_MASK); ++} ++ ++static void cedrus_h264_setup(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ ++ cedrus_engine_enable(dev, CEDRUS_CODEC_H264); ++ ++ cedrus_write(dev, VE_H264_SDROT_CTRL, 0); ++ cedrus_write(dev, VE_H264_EXTRA_BUFFER1, ++ ctx->codec.h264.pic_info_buf_dma); ++ cedrus_write(dev, VE_H264_EXTRA_BUFFER2, ++ ctx->codec.h264.neighbor_info_buf_dma); ++ ++ cedrus_write_scaling_lists(ctx, run); ++ cedrus_write_frame_list(ctx, run); ++ ++ cedrus_set_params(ctx, run); ++} ++ ++static int cedrus_h264_start(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ unsigned int field_size; ++ unsigned int mv_col_size; ++ int ret; ++ ++ /* ++ * FIXME: It seems that the H6 cedarX code is using a formula ++ * here based on the size of the frame, while all the older ++ * code is using a fixed size, so that might need to be ++ * changed at some point. ++ */ ++ ctx->codec.h264.pic_info_buf = ++ dma_alloc_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, ++ &ctx->codec.h264.pic_info_buf_dma, ++ GFP_KERNEL); ++ if (!ctx->codec.h264.pic_info_buf) ++ return -ENOMEM; ++ ++ /* ++ * That buffer is supposed to be 16kiB in size, and be aligned ++ * on 16kiB as well. However, dma_alloc_coherent provides the ++ * guarantee that we'll have a CPU and DMA address aligned on ++ * the smallest page order that is greater to the requested ++ * size, so we don't have to overallocate. ++ */ ++ ctx->codec.h264.neighbor_info_buf = ++ dma_alloc_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, ++ &ctx->codec.h264.neighbor_info_buf_dma, ++ GFP_KERNEL); ++ if (!ctx->codec.h264.neighbor_info_buf) { ++ ret = -ENOMEM; ++ goto err_pic_buf; ++ } ++ ++ field_size = DIV_ROUND_UP(ctx->src_fmt.width, 16) * ++ DIV_ROUND_UP(ctx->src_fmt.height, 16) * 16; ++ ++ /* ++ * FIXME: This is actually conditional to ++ * V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE not being set, we ++ * might have to rework this if memory efficiency ever is ++ * something we need to work on. ++ */ ++ field_size = field_size * 2; ++ ++ /* ++ * FIXME: This is actually conditional to ++ * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY not being set, we might ++ * have to rework this if memory efficiency ever is something ++ * we need to work on. ++ */ ++ field_size = field_size * 2; ++ ctx->codec.h264.mv_col_buf_field_size = field_size; ++ ++ mv_col_size = field_size * 2 * CEDRUS_H264_FRAME_NUM; ++ ctx->codec.h264.mv_col_buf_size = mv_col_size; ++ ctx->codec.h264.mv_col_buf = dma_alloc_coherent(dev->dev, ++ ctx->codec.h264.mv_col_buf_size, ++ &ctx->codec.h264.mv_col_buf_dma, ++ GFP_KERNEL); ++ if (!ctx->codec.h264.mv_col_buf) { ++ ret = -ENOMEM; ++ goto err_neighbor_buf; ++ } ++ ++ return 0; ++ ++err_neighbor_buf: ++ dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, ++ ctx->codec.h264.neighbor_info_buf, ++ ctx->codec.h264.neighbor_info_buf_dma); ++ ++err_pic_buf: ++ dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, ++ ctx->codec.h264.pic_info_buf, ++ ctx->codec.h264.pic_info_buf_dma); ++ return ret; ++} ++ ++static void cedrus_h264_stop(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ ++ dma_free_coherent(dev->dev, ctx->codec.h264.mv_col_buf_size, ++ ctx->codec.h264.mv_col_buf, ++ ctx->codec.h264.mv_col_buf_dma); ++ dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, ++ ctx->codec.h264.neighbor_info_buf, ++ ctx->codec.h264.neighbor_info_buf_dma); ++ dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, ++ ctx->codec.h264.pic_info_buf, ++ ctx->codec.h264.pic_info_buf_dma); ++} ++ ++static void cedrus_h264_trigger(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ ++ cedrus_write(dev, VE_H264_TRIGGER_TYPE, ++ VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE); ++} ++ ++struct cedrus_dec_ops cedrus_dec_ops_h264 = { ++ .irq_clear = cedrus_h264_irq_clear, ++ .irq_disable = cedrus_h264_irq_disable, ++ .irq_status = cedrus_h264_irq_status, ++ .setup = cedrus_h264_setup, ++ .start = cedrus_h264_start, ++ .stop = cedrus_h264_stop, ++ .trigger = cedrus_h264_trigger, ++}; +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +index fbfff7c1c771..748f7f673547 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +@@ -46,6 +46,10 @@ int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) + reg |= VE_MODE_DEC_MPEG; + break; + ++ case CEDRUS_CODEC_H264: ++ reg |= VE_MODE_DEC_H264; ++ break; ++ + default: + return -EINVAL; + } +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +index de2d6b6f64bf..3e9931416e45 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +@@ -232,4 +232,95 @@ + #define VE_DEC_MPEG_ROT_LUMA (VE_ENGINE_DEC_MPEG + 0xcc) + #define VE_DEC_MPEG_ROT_CHROMA (VE_ENGINE_DEC_MPEG + 0xd0) + ++#define VE_H264_SPS 0x200 ++#define VE_H264_SPS_MBS_ONLY BIT(18) ++#define VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD BIT(17) ++#define VE_H264_SPS_DIRECT_8X8_INFERENCE BIT(16) ++ ++#define VE_H264_PPS 0x204 ++#define VE_H264_PPS_ENTROPY_CODING_MODE BIT(15) ++#define VE_H264_PPS_WEIGHTED_PRED BIT(4) ++#define VE_H264_PPS_CONSTRAINED_INTRA_PRED BIT(1) ++#define VE_H264_PPS_TRANSFORM_8X8_MODE BIT(0) ++ ++#define VE_H264_SHS 0x208 ++#define VE_H264_SHS_FIRST_SLICE_IN_PIC BIT(5) ++#define VE_H264_SHS_FIELD_PIC BIT(4) ++#define VE_H264_SHS_BOTTOM_FIELD BIT(3) ++#define VE_H264_SHS_DIRECT_SPATIAL_MV_PRED BIT(2) ++ ++#define VE_H264_SHS2 0x20c ++#define VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD BIT(12) ++ ++#define VE_H264_SHS_WP 0x210 ++ ++#define VE_H264_SHS_QP 0x21c ++#define VE_H264_SHS_QP_SCALING_MATRIX_DEFAULT BIT(24) ++ ++#define VE_H264_CTRL 0x220 ++#define VE_H264_CTRL_VLD_DATA_REQ_INT BIT(2) ++#define VE_H264_CTRL_DECODE_ERR_INT BIT(1) ++#define VE_H264_CTRL_SLICE_DECODE_INT BIT(0) ++ ++#define VE_H264_CTRL_INT_MASK (VE_H264_CTRL_VLD_DATA_REQ_INT | \ ++ VE_H264_CTRL_DECODE_ERR_INT | \ ++ VE_H264_CTRL_SLICE_DECODE_INT) ++ ++#define VE_H264_TRIGGER_TYPE 0x224 ++#define VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE (8 << 0) ++#define VE_H264_TRIGGER_TYPE_INIT_SWDEC (7 << 0) ++ ++#define VE_H264_STATUS 0x228 ++#define VE_H264_STATUS_VLD_DATA_REQ_INT VE_H264_CTRL_VLD_DATA_REQ_INT ++#define VE_H264_STATUS_DECODE_ERR_INT VE_H264_CTRL_DECODE_ERR_INT ++#define VE_H264_STATUS_SLICE_DECODE_INT VE_H264_CTRL_SLICE_DECODE_INT ++ ++#define VE_H264_STATUS_INT_MASK VE_H264_CTRL_INT_MASK ++ ++#define VE_H264_CUR_MB_NUM 0x22c ++ ++#define VE_H264_VLD_ADDR 0x230 ++#define VE_H264_VLD_ADDR_FIRST BIT(30) ++#define VE_H264_VLD_ADDR_LAST BIT(29) ++#define VE_H264_VLD_ADDR_VALID BIT(28) ++#define VE_H264_VLD_ADDR_VAL(x) (((x) & 0x0ffffff0) | ((x) >> 28)) ++ ++#define VE_H264_VLD_OFFSET 0x234 ++#define VE_H264_VLD_LEN 0x238 ++#define VE_H264_VLD_END 0x23c ++#define VE_H264_SDROT_CTRL 0x240 ++#define VE_H264_OUTPUT_FRAME_IDX 0x24c ++#define VE_H264_EXTRA_BUFFER1 0x250 ++#define VE_H264_EXTRA_BUFFER2 0x254 ++#define VE_H264_BASIC_BITS 0x2dc ++#define VE_AVC_SRAM_PORT_OFFSET 0x2e0 ++#define VE_AVC_SRAM_PORT_DATA 0x2e4 ++ ++#define VE_ISP_INPUT_SIZE 0xa00 ++#define VE_ISP_INPUT_STRIDE 0xa04 ++#define VE_ISP_CTRL 0xa08 ++#define VE_ISP_INPUT_LUMA 0xa78 ++#define VE_ISP_INPUT_CHROMA 0xa7c ++ ++#define VE_AVC_PARAM 0xb04 ++#define VE_AVC_QP 0xb08 ++#define VE_AVC_MOTION_EST 0xb10 ++#define VE_AVC_CTRL 0xb14 ++#define VE_AVC_TRIGGER 0xb18 ++#define VE_AVC_STATUS 0xb1c ++#define VE_AVC_BASIC_BITS 0xb20 ++#define VE_AVC_UNK_BUF 0xb60 ++#define VE_AVC_VLE_ADDR 0xb80 ++#define VE_AVC_VLE_END 0xb84 ++#define VE_AVC_VLE_OFFSET 0xb88 ++#define VE_AVC_VLE_MAX 0xb8c ++#define VE_AVC_VLE_LENGTH 0xb90 ++#define VE_AVC_REF_LUMA 0xba0 ++#define VE_AVC_REF_CHROMA 0xba4 ++#define VE_AVC_REC_LUMA 0xbb0 ++#define VE_AVC_REC_CHROMA 0xbb4 ++#define VE_AVC_REF_SLUMA 0xbb8 ++#define VE_AVC_REC_SLUMA 0xbbc ++#define VE_AVC_MB_INFO 0xbc0 ++ + #endif +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +index 9673874ece10..e2b530b1a956 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +@@ -38,6 +38,10 @@ static struct cedrus_format cedrus_formats[] = { + .directions = CEDRUS_DECODE_SRC, + }, + { ++ .pixelformat = V4L2_PIX_FMT_H264_SLICE_RAW, ++ .directions = CEDRUS_DECODE_SRC, ++ }, ++ { + .pixelformat = V4L2_PIX_FMT_SUNXI_TILED_NV12, + .directions = CEDRUS_DECODE_DST, + }, +@@ -100,6 +104,7 @@ static void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt) + + switch (pix_fmt->pixelformat) { + case V4L2_PIX_FMT_MPEG2_SLICE: ++ case V4L2_PIX_FMT_H264_SLICE_RAW: + /* Zero bytes per line for encoded source. */ + bytesperline = 0; + +@@ -464,6 +469,10 @@ static int cedrus_start_streaming(struct vb2_queue *vq, unsigned int count) + ctx->current_codec = CEDRUS_CODEC_MPEG2; + break; + ++ case V4L2_PIX_FMT_H264_SLICE_RAW: ++ ctx->current_codec = CEDRUS_CODEC_H264; ++ break; ++ + default: + return -EINVAL; + } diff --git a/projects/Allwinner/patches/linux/0006-HEVC-H.265-stateless-support-for-V4L2-and-Cedrus.patch b/projects/Allwinner/patches/linux/0006-HEVC-H.265-stateless-support-for-V4L2-and-Cedrus.patch new file mode 100644 index 0000000000..dd5aac6690 --- /dev/null +++ b/projects/Allwinner/patches/linux/0006-HEVC-H.265-stateless-support-for-V4L2-and-Cedrus.patch @@ -0,0 +1,1628 @@ +From patchwork Thu Feb 14 09:53:08 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Paul Kocialkowski +X-Patchwork-Id: 10812217 +Return-Path: +Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org + [172.30.200.125]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0E14113B4 + for ; + Thu, 14 Feb 2019 09:55:00 +0000 (UTC) +Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) + by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ED4C528703 + for ; + Thu, 14 Feb 2019 09:54:59 +0000 (UTC) +Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) + id E062E28758; Thu, 14 Feb 2019 09:54:59 +0000 (UTC) +X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on + pdx-wl-mail.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, + RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 +Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) + by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 388EF28703 + for ; + Thu, 14 Feb 2019 09:54:57 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S2392986AbfBNJyo (ORCPT + ); + Thu, 14 Feb 2019 04:54:44 -0500 +Received: from relay8-d.mail.gandi.net ([217.70.183.201]:58429 "EHLO + relay8-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S2392838AbfBNJyn (ORCPT + ); + Thu, 14 Feb 2019 04:54:43 -0500 +X-Originating-IP: 90.88.30.68 +Received: from localhost.localdomain + (aaubervilliers-681-1-89-68.w90-88.abo.wanadoo.fr [90.88.30.68]) + (Authenticated sender: paul.kocialkowski@bootlin.com) + by relay8-d.mail.gandi.net (Postfix) with ESMTPSA id 7E9C61BF20B; + Thu, 14 Feb 2019 09:54:37 +0000 (UTC) +From: Paul Kocialkowski +To: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, + devel@driverdev.osuosl.org, linux-arm-kernel@lists.infradead.org, + linux-sunxi@googlegroups.com +Cc: Mauro Carvalho Chehab , + Maxime Ripard , + Paul Kocialkowski , + Greg Kroah-Hartman , + Chen-Yu Tsai , + Thomas Petazzoni , + Hans Verkuil , + Sakari Ailus , + Randy Li , + Ezequiel Garcia , + Tomasz Figa , + Alexandre Courbot +Subject: [PATCH v3 1/2] media: v4l: Add definitions for the HEVC slice format + and controls +Date: Thu, 14 Feb 2019 10:53:08 +0100 +Message-Id: <20190214095309.19594-2-paul.kocialkowski@bootlin.com> +X-Mailer: git-send-email 2.20.1 +In-Reply-To: <20190214095309.19594-1-paul.kocialkowski@bootlin.com> +References: <20190214095309.19594-1-paul.kocialkowski@bootlin.com> +MIME-Version: 1.0 +Sender: linux-media-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-media@vger.kernel.org +X-Virus-Scanned: ClamAV using ClamSMTP + +This introduces the required definitions for HEVC decoding support with +stateless VPUs. The controls associated to the HEVC slice format provide +the required meta-data for decoding slices extracted from the bitstream. + +This interface comes with the following limitations: +* No custom quantization matrices (scaling lists); +* Support for a single temporal layer only; +* No slice entry point offsets support; +* No conformance window support; +* No VUI parameters support; +* No support for SPS extensions: range, multilayer, 3d, scc, 4 bits; +* No support for PPS extensions: range, multilayer, 3d, scc, 4 bits. + +Signed-off-by: Paul Kocialkowski +--- + Documentation/media/uapi/v4l/biblio.rst | 9 + + .../media/uapi/v4l/pixfmt-compressed.rst | 15 + + .../media/uapi/v4l/vidioc-queryctrl.rst | 18 + + .../media/videodev2.h.rst.exceptions | 3 + + drivers/media/v4l2-core/v4l2-ctrls.c | 26 ++ + drivers/media/v4l2-core/v4l2-ioctl.c | 1 + + include/media/hevc-ctrls.h | 181 ++++++++ + include/media/v4l2-ctrls.h | 7 + + include/uapi/linux/videodev2.h | 1 + + 10 files changed, 679 insertions(+) + create mode 100644 include/media/hevc-ctrls.h + +diff --git a/Documentation/media/uapi/v4l/biblio.rst b/Documentation/media/uapi/v4l/biblio.rst +index 3fc3f7ff338a..b4b3fcec55dd 100644 +--- a/Documentation/media/uapi/v4l/biblio.rst ++++ b/Documentation/media/uapi/v4l/biblio.rst +@@ -131,6 +131,15 @@ ITU H.264 + + :author: International Telecommunication Union (http://www.itu.ch) + ++.. _hevc: ++ ++ITU H.265/HEVC ++============== ++ ++:title: ITU-T Rec. H.265 | ISO/IEC 23008-2 "High Efficiency Video Coding" ++ ++:author: International Telecommunication Union (http://www.itu.ch), International Organisation for Standardisation (http://www.iso.ch) ++ + .. _jfif: + + JFIF +diff --git a/Documentation/media/uapi/v4l/pixfmt-compressed.rst b/Documentation/media/uapi/v4l/pixfmt-compressed.rst +index b6f857ac1a8e..ee82526cdc00 100644 +--- a/Documentation/media/uapi/v4l/pixfmt-compressed.rst ++++ b/Documentation/media/uapi/v4l/pixfmt-compressed.rst +@@ -138,6 +138,21 @@ Compressed Formats + - ``V4L2_PIX_FMT_HEVC`` + - 'HEVC' + - HEVC/H.265 video elementary stream. ++ * .. _V4L2-PIX-FMT-HEVC-SLICE: ++ ++ - ``V4L2_PIX_FMT_HEVC_SLICE`` ++ - 'S265' ++ - HEVC parsed slice data, as extracted from the HEVC bitstream. ++ This format is adapted for stateless video decoders that implement a ++ HEVC pipeline (using the :ref:`codec` and :ref:`media-request-api`). ++ Metadata associated with the frame to decode is required to be passed ++ through the following controls : ++ * ``V4L2_CID_MPEG_VIDEO_HEVC_SPS`` ++ * ``V4L2_CID_MPEG_VIDEO_HEVC_PPS`` ++ * ``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS`` ++ See the :ref:`associated Codec Control IDs `. ++ Buffers associated with this pixel format must contain the appropriate ++ number of macroblocks to decode a full corresponding frame. + * .. _V4L2-PIX-FMT-FWHT: + + - ``V4L2_PIX_FMT_FWHT`` +diff --git a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst +index bf29dc5b9758..f37cb377e258 100644 +--- a/Documentation/media/uapi/v4l/vidioc-queryctrl.rst ++++ b/Documentation/media/uapi/v4l/vidioc-queryctrl.rst +@@ -473,6 +473,24 @@ See also the examples in :ref:`control`. + - n/a + - A struct :c:type:`v4l2_ctrl_h264_decode_param`, containing H264 + decode parameters for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_HEVC_SPS`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_hevc_sps`, containing HEVC Sequence ++ Parameter Set for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_HEVC_PPS`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_hevc_pps`, containing HEVC Picture ++ Parameter Set for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_hevc_slice_params`, containing HEVC ++ slice parameters for stateless video decoders. + + .. tabularcolumns:: |p{6.6cm}|p{2.2cm}|p{8.7cm}| + +diff --git a/Documentation/media/videodev2.h.rst.exceptions b/Documentation/media/videodev2.h.rst.exceptions +index 55cbe324b9fc..afba7d71971a 100644 +--- a/Documentation/media/videodev2.h.rst.exceptions ++++ b/Documentation/media/videodev2.h.rst.exceptions +@@ -141,6 +141,9 @@ replace symbol V4L2_CTRL_TYPE_H264_PPS :c:type:`v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_H264_SCALING_MATRIX :c:type:`v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_H264_SLICE_PARAMS :c:type:`v4l2_ctrl_type` + replace symbol V4L2_CTRL_TYPE_H264_DECODE_PARAMS :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_HEVC_SPS :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_HEVC_PPS :c:type:`v4l2_ctrl_type` ++replace symbol V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS :c:type:`v4l2_ctrl_type` + + # V4L2 capability defines + replace define V4L2_CAP_VIDEO_CAPTURE device-capabilities +diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c +index 366200d31bc0..106c80ec9312 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls.c +@@ -916,6 +916,9 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD: return "HEVC Size of Length Field"; + case V4L2_CID_MPEG_VIDEO_REF_NUMBER_FOR_PFRAMES: return "Reference Frames for a P-Frame"; + case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: return "Prepend SPS and PPS to IDR"; ++ case V4L2_CID_MPEG_VIDEO_HEVC_SPS: return "HEVC Sequence Parameter Set"; ++ case V4L2_CID_MPEG_VIDEO_HEVC_PPS: return "HEVC Picture Parameter Set"; ++ case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: return "HEVC Slice Parameters"; + + /* CAMERA controls */ + /* Keep the order of the 'case's the same as in v4l2-controls.h! */ +@@ -1323,6 +1326,15 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, + case V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS: + *type = V4L2_CTRL_TYPE_H264_DECODE_PARAMS; + break; ++ case V4L2_CID_MPEG_VIDEO_HEVC_SPS: ++ *type = V4L2_CTRL_TYPE_HEVC_SPS; ++ break; ++ case V4L2_CID_MPEG_VIDEO_HEVC_PPS: ++ *type = V4L2_CTRL_TYPE_HEVC_PPS; ++ break; ++ case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: ++ *type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS; ++ break; + default: + *type = V4L2_CTRL_TYPE_INTEGER; + break; +@@ -1696,6 +1708,11 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, + case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: + return 0; + ++ case V4L2_CTRL_TYPE_HEVC_SPS: ++ case V4L2_CTRL_TYPE_HEVC_PPS: ++ case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: ++ return 0; ++ + default: + return -EINVAL; + } +@@ -2291,6 +2308,15 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, + case V4L2_CTRL_TYPE_H264_DECODE_PARAMS: + elem_size = sizeof(struct v4l2_ctrl_h264_decode_param); + break; ++ case V4L2_CTRL_TYPE_HEVC_SPS: ++ elem_size = sizeof(struct v4l2_ctrl_hevc_sps); ++ break; ++ case V4L2_CTRL_TYPE_HEVC_PPS: ++ elem_size = sizeof(struct v4l2_ctrl_hevc_pps); ++ break; ++ case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: ++ elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params); ++ break; + default: + if (type < V4L2_CTRL_COMPOUND_TYPES) + elem_size = sizeof(s32); +diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c +index 8aa7de17ecfa..e792fc97e263 100644 +--- a/drivers/media/v4l2-core/v4l2-ioctl.c ++++ b/drivers/media/v4l2-core/v4l2-ioctl.c +@@ -1331,6 +1331,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) + case V4L2_PIX_FMT_VP8: descr = "VP8"; break; + case V4L2_PIX_FMT_VP9: descr = "VP9"; break; + case V4L2_PIX_FMT_HEVC: descr = "HEVC"; break; /* aka H.265 */ ++ case V4L2_PIX_FMT_HEVC_SLICE: descr = "HEVC Parsed Slice Data"; break; + case V4L2_PIX_FMT_FWHT: descr = "FWHT"; break; /* used in vicodec */ + case V4L2_PIX_FMT_CPIA1: descr = "GSPCA CPiA YUV"; break; + case V4L2_PIX_FMT_WNVA: descr = "WNVA"; break; +diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h +new file mode 100644 +index 000000000000..005c71c67163 +--- /dev/null ++++ b/include/media/hevc-ctrls.h +@@ -0,0 +1,181 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * These are the HEVC state controls for use with stateless HEVC ++ * codec drivers. ++ * ++ * It turns out that these structs are not stable yet and will undergo ++ * more changes. So keep them private until they are stable and ready to ++ * become part of the official public API. ++ */ ++ ++#ifndef _HEVC_CTRLS_H_ ++#define _HEVC_CTRLS_H_ ++ ++#define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 645) ++#define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 646) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 647) ++ ++/* enum v4l2_ctrl_type type values */ ++#define V4L2_CTRL_TYPE_HEVC_SPS 0x0115 ++#define V4L2_CTRL_TYPE_HEVC_PPS 0x0116 ++#define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0117 ++ ++#define V4L2_HEVC_SLICE_TYPE_B 0 ++#define V4L2_HEVC_SLICE_TYPE_P 1 ++#define V4L2_HEVC_SLICE_TYPE_I 2 ++ ++struct v4l2_ctrl_hevc_sps { ++ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ ++ __u8 chroma_format_idc; ++ __u8 separate_colour_plane_flag; ++ __u16 pic_width_in_luma_samples; ++ __u16 pic_height_in_luma_samples; ++ __u8 bit_depth_luma_minus8; ++ __u8 bit_depth_chroma_minus8; ++ __u8 log2_max_pic_order_cnt_lsb_minus4; ++ __u8 sps_max_dec_pic_buffering_minus1; ++ __u8 sps_max_num_reorder_pics; ++ __u8 sps_max_latency_increase_plus1; ++ __u8 log2_min_luma_coding_block_size_minus3; ++ __u8 log2_diff_max_min_luma_coding_block_size; ++ __u8 log2_min_luma_transform_block_size_minus2; ++ __u8 log2_diff_max_min_luma_transform_block_size; ++ __u8 max_transform_hierarchy_depth_inter; ++ __u8 max_transform_hierarchy_depth_intra; ++ __u8 scaling_list_enabled_flag; ++ __u8 amp_enabled_flag; ++ __u8 sample_adaptive_offset_enabled_flag; ++ __u8 pcm_enabled_flag; ++ __u8 pcm_sample_bit_depth_luma_minus1; ++ __u8 pcm_sample_bit_depth_chroma_minus1; ++ __u8 log2_min_pcm_luma_coding_block_size_minus3; ++ __u8 log2_diff_max_min_pcm_luma_coding_block_size; ++ __u8 pcm_loop_filter_disabled_flag; ++ __u8 num_short_term_ref_pic_sets; ++ __u8 long_term_ref_pics_present_flag; ++ __u8 num_long_term_ref_pics_sps; ++ __u8 sps_temporal_mvp_enabled_flag; ++ __u8 strong_intra_smoothing_enabled_flag; ++}; ++ ++struct v4l2_ctrl_hevc_pps { ++ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ ++ __u8 dependent_slice_segment_flag; ++ __u8 output_flag_present_flag; ++ __u8 num_extra_slice_header_bits; ++ __u8 sign_data_hiding_enabled_flag; ++ __u8 cabac_init_present_flag; ++ __s8 init_qp_minus26; ++ __u8 constrained_intra_pred_flag; ++ __u8 transform_skip_enabled_flag; ++ __u8 cu_qp_delta_enabled_flag; ++ __u8 diff_cu_qp_delta_depth; ++ __s8 pps_cb_qp_offset; ++ __s8 pps_cr_qp_offset; ++ __u8 pps_slice_chroma_qp_offsets_present_flag; ++ __u8 weighted_pred_flag; ++ __u8 weighted_bipred_flag; ++ __u8 transquant_bypass_enabled_flag; ++ __u8 tiles_enabled_flag; ++ __u8 entropy_coding_sync_enabled_flag; ++ __u8 num_tile_columns_minus1; ++ __u8 num_tile_rows_minus1; ++ __u8 column_width_minus1[20]; ++ __u8 row_height_minus1[22]; ++ __u8 loop_filter_across_tiles_enabled_flag; ++ __u8 pps_loop_filter_across_slices_enabled_flag; ++ __u8 deblocking_filter_override_enabled_flag; ++ __u8 pps_disable_deblocking_filter_flag; ++ __s8 pps_beta_offset_div2; ++ __s8 pps_tc_offset_div2; ++ __u8 lists_modification_present_flag; ++ __u8 log2_parallel_merge_level_minus2; ++ __u8 slice_segment_header_extension_present_flag; ++ __u8 padding; ++}; ++ ++#define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_BEFORE 0x01 ++#define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_AFTER 0x02 ++#define V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR 0x03 ++ ++#define V4L2_HEVC_DPB_ENTRIES_NUM_MAX 16 ++ ++struct v4l2_hevc_dpb_entry { ++ __u64 timestamp; ++ __u8 rps; ++ __u8 field_pic; ++ __u16 pic_order_cnt[2]; ++ __u8 padding[2]; ++}; ++ ++struct v4l2_hevc_pred_weight_table { ++ __u8 luma_log2_weight_denom; ++ __s8 delta_chroma_log2_weight_denom; ++ ++ __s8 delta_luma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ __s8 luma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ __s8 delta_chroma_weight_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]; ++ __s8 chroma_offset_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]; ++ ++ __s8 delta_luma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ __s8 luma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ __s8 delta_chroma_weight_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]; ++ __s8 chroma_offset_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX][2]; ++ ++ __u8 padding[2]; ++}; ++ ++struct v4l2_ctrl_hevc_slice_params { ++ __u32 bit_size; ++ __u32 data_bit_offset; ++ ++ /* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */ ++ __u8 nal_unit_type; ++ __u8 nuh_temporal_id_plus1; ++ ++ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ ++ __u8 slice_type; ++ __u8 colour_plane_id; ++ __u16 slice_pic_order_cnt; ++ __u8 slice_sao_luma_flag; ++ __u8 slice_sao_chroma_flag; ++ __u8 slice_temporal_mvp_enabled_flag; ++ __u8 num_ref_idx_l0_active_minus1; ++ __u8 num_ref_idx_l1_active_minus1; ++ __u8 mvd_l1_zero_flag; ++ __u8 cabac_init_flag; ++ __u8 collocated_from_l0_flag; ++ __u8 collocated_ref_idx; ++ __u8 five_minus_max_num_merge_cand; ++ __u8 use_integer_mv_flag; ++ __s8 slice_qp_delta; ++ __s8 slice_cb_qp_offset; ++ __s8 slice_cr_qp_offset; ++ __s8 slice_act_y_qp_offset; ++ __s8 slice_act_cb_qp_offset; ++ __s8 slice_act_cr_qp_offset; ++ __u8 slice_deblocking_filter_disabled_flag; ++ __s8 slice_beta_offset_div2; ++ __s8 slice_tc_offset_div2; ++ __u8 slice_loop_filter_across_slices_enabled_flag; ++ ++ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture timing SEI message */ ++ __u8 pic_struct; ++ ++ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ ++ struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ __u8 num_active_dpb_entries; ++ __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ ++ __u8 num_rps_poc_st_curr_before; ++ __u8 num_rps_poc_st_curr_after; ++ __u8 num_rps_poc_lt_curr; ++ ++ /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ ++ struct v4l2_hevc_pred_weight_table pred_weight_table; ++ ++ __u8 padding[2]; ++}; ++ ++#endif +diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h +index 22b6d09c4764..f24a835e5920 100644 +--- a/include/media/v4l2-ctrls.h ++++ b/include/media/v4l2-ctrls.h +@@ -28,6 +28,7 @@ + */ + #include + #include ++#include + + /* forward references */ + struct file; +@@ -55,6 +56,9 @@ struct poll_table_struct; + * @p_h264_scaling_matrix: Pointer to a struct v4l2_ctrl_h264_scaling_matrix. + * @p_h264_slice_param: Pointer to a struct v4l2_ctrl_h264_slice_params. + * @p_h264_decode_param: Pointer to a struct v4l2_ctrl_h264_decode_params. ++ * @p_hevc_sps: Pointer to an HEVC sequence parameter set structure. ++ * @p_hevc_pps: Pointer to an HEVC picture parameter set structure. ++ * @p_hevc_slice_params Pointer to an HEVC slice parameters structure. + * @p: Pointer to a compound value. + */ + union v4l2_ctrl_ptr { +@@ -71,6 +75,9 @@ union v4l2_ctrl_ptr { + struct v4l2_ctrl_h264_scaling_matrix *p_h264_scaling_matrix; + struct v4l2_ctrl_h264_slice_params *p_h264_slice_param; + struct v4l2_ctrl_h264_decode_params *p_h264_decode_param; ++ struct v4l2_ctrl_hevc_sps *p_hevc_sps; ++ struct v4l2_ctrl_hevc_pps *p_hevc_pps; ++ struct v4l2_ctrl_hevc_slice_params *p_hevc_slice_params; + void *p; + }; + +diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h +index 673172c84fb9..5ae4f00f4078 100644 +--- a/include/uapi/linux/videodev2.h ++++ b/include/uapi/linux/videodev2.h +@@ -669,6 +669,7 @@ struct v4l2_pix_format { + #define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') /* VP8 */ + #define V4L2_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0') /* VP9 */ + #define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* HEVC aka H.265 */ ++#define V4L2_PIX_FMT_HEVC_SLICE v4l2_fourcc('S', '2', '6', '5') /* HEVC parsed slices */ + #define V4L2_PIX_FMT_FWHT v4l2_fourcc('F', 'W', 'H', 'T') /* Fast Walsh Hadamard Transform (vicodec) */ + + /* Vendor-specific formats */ + +From patchwork Thu Feb 14 09:53:09 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Paul Kocialkowski +X-Patchwork-Id: 10812215 +Return-Path: +Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org + [172.30.200.125]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BE979746 + for ; + Thu, 14 Feb 2019 09:54:56 +0000 (UTC) +Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) + by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AB33928703 + for ; + Thu, 14 Feb 2019 09:54:56 +0000 (UTC) +Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) + id 9ED1728752; Thu, 14 Feb 2019 09:54:56 +0000 (UTC) +X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on + pdx-wl-mail.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, + RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 +Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) + by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6651528703 + for ; + Thu, 14 Feb 2019 09:54:54 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S2438109AbfBNJys (ORCPT + ); + Thu, 14 Feb 2019 04:54:48 -0500 +Received: from relay8-d.mail.gandi.net ([217.70.183.201]:40921 "EHLO + relay8-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S2392881AbfBNJyq (ORCPT + ); + Thu, 14 Feb 2019 04:54:46 -0500 +X-Originating-IP: 90.88.30.68 +Received: from localhost.localdomain + (aaubervilliers-681-1-89-68.w90-88.abo.wanadoo.fr [90.88.30.68]) + (Authenticated sender: paul.kocialkowski@bootlin.com) + by relay8-d.mail.gandi.net (Postfix) with ESMTPSA id 2F2A01BF219; + Thu, 14 Feb 2019 09:54:39 +0000 (UTC) +From: Paul Kocialkowski +To: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, + devel@driverdev.osuosl.org, linux-arm-kernel@lists.infradead.org, + linux-sunxi@googlegroups.com +Cc: Mauro Carvalho Chehab , + Maxime Ripard , + Paul Kocialkowski , + Greg Kroah-Hartman , + Chen-Yu Tsai , + Thomas Petazzoni , + Hans Verkuil , + Sakari Ailus , + Randy Li , + Ezequiel Garcia , + Tomasz Figa , + Alexandre Courbot +Subject: [PATCH v3 2/2] media: cedrus: Add HEVC/H.265 decoding support +Date: Thu, 14 Feb 2019 10:53:09 +0100 +Message-Id: <20190214095309.19594-3-paul.kocialkowski@bootlin.com> +X-Mailer: git-send-email 2.20.1 +In-Reply-To: <20190214095309.19594-1-paul.kocialkowski@bootlin.com> +References: <20190214095309.19594-1-paul.kocialkowski@bootlin.com> +MIME-Version: 1.0 +Sender: linux-media-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-media@vger.kernel.org +X-Virus-Scanned: ClamAV using ClamSMTP + +This introduces support for HEVC/H.265 to the Cedrus VPU driver, with +both uni-directional and bi-directional prediction modes supported. + +Field-coded (interlaced) pictures, custom quantization matrices and +10-bit output are not supported at this point. + +Signed-off-by: Paul Kocialkowski +--- + drivers/staging/media/sunxi/cedrus/Makefile | 2 +- + drivers/staging/media/sunxi/cedrus/cedrus.c | 27 +- + drivers/staging/media/sunxi/cedrus/cedrus.h | 18 + + .../staging/media/sunxi/cedrus/cedrus_dec.c | 9 + + .../staging/media/sunxi/cedrus/cedrus_h265.c | 531 ++++++++++++++++++ + .../staging/media/sunxi/cedrus/cedrus_hw.c | 4 + + .../staging/media/sunxi/cedrus/cedrus_regs.h | 290 ++++++++++ + .../staging/media/sunxi/cedrus/cedrus_video.c | 10 + + 8 files changed, 887 insertions(+), 4 deletions(-) + create mode 100644 drivers/staging/media/sunxi/cedrus/cedrus_h265.c + +diff --git a/drivers/staging/media/sunxi/cedrus/Makefile b/drivers/staging/media/sunxi/cedrus/Makefile +index aaf141fc58b6..186cb6d01b67 100644 +--- a/drivers/staging/media/sunxi/cedrus/Makefile ++++ b/drivers/staging/media/sunxi/cedrus/Makefile +@@ -1,4 +1,4 @@ + obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += sunxi-cedrus.o + + sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o \ +- cedrus_mpeg2.o cedrus_h264.o ++ cedrus_mpeg2.o cedrus_h264.o cedrus_h265.o +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c +index b275607b8111..a713630ce7ba 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c +@@ -68,6 +68,23 @@ static const struct cedrus_control cedrus_controls[] = { + .id = V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX, + .elem_size = sizeof(struct v4l2_ctrl_h264_scaling_matrix), + .codec = CEDRUS_CODEC_H264, ++ }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, ++ .elem_size = sizeof(struct v4l2_ctrl_hevc_sps), ++ .codec = CEDRUS_CODEC_H265, ++ .required = true, ++ }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_HEVC_PPS, ++ .elem_size = sizeof(struct v4l2_ctrl_hevc_pps), ++ .codec = CEDRUS_CODEC_H265, ++ .required = true, ++ }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS, ++ .elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params), ++ .codec = CEDRUS_CODEC_H265, + .required = true, + }, + }; +@@ -309,6 +326,7 @@ static int cedrus_probe(struct platform_device *pdev) + + dev->dec_ops[CEDRUS_CODEC_MPEG2] = &cedrus_dec_ops_mpeg2; + dev->dec_ops[CEDRUS_CODEC_H264] = &cedrus_dec_ops_h264; ++ dev->dec_ops[CEDRUS_CODEC_H265] = &cedrus_dec_ops_h265; + + mutex_init(&dev->dev_mutex); + +@@ -416,15 +434,18 @@ static const struct cedrus_variant sun8i_a33_cedrus_variant = { + }; + + static const struct cedrus_variant sun8i_h3_cedrus_variant = { +- .capabilities = CEDRUS_CAPABILITY_UNTILED, ++ .capabilities = CEDRUS_CAPABILITY_UNTILED | ++ CEDRUS_CAPABILITY_H265_DEC, + }; + + static const struct cedrus_variant sun50i_a64_cedrus_variant = { +- .capabilities = CEDRUS_CAPABILITY_UNTILED, ++ .capabilities = CEDRUS_CAPABILITY_UNTILED | ++ CEDRUS_CAPABILITY_H265_DEC, + }; + + static const struct cedrus_variant sun50i_h5_cedrus_variant = { +- .capabilities = CEDRUS_CAPABILITY_UNTILED, ++ .capabilities = CEDRUS_CAPABILITY_UNTILED | ++ CEDRUS_CAPABILITY_H265_DEC, + }; + + static const struct of_device_id cedrus_dt_match[] = { +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h +index 8c64f9a27e9d..b5d083812bea 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h +@@ -27,10 +27,12 @@ + #define CEDRUS_NAME "cedrus" + + #define CEDRUS_CAPABILITY_UNTILED BIT(0) ++#define CEDRUS_CAPABILITY_H265_DEC BIT(1) + + enum cedrus_codec { + CEDRUS_CODEC_MPEG2, + CEDRUS_CODEC_H264, ++ CEDRUS_CODEC_H265, + CEDRUS_CODEC_LAST, + }; + +@@ -66,6 +68,12 @@ struct cedrus_mpeg2_run { + const struct v4l2_ctrl_mpeg2_quantization *quantization; + }; + ++struct cedrus_h265_run { ++ const struct v4l2_ctrl_hevc_sps *sps; ++ const struct v4l2_ctrl_hevc_pps *pps; ++ const struct v4l2_ctrl_hevc_slice_params *slice_params; ++}; ++ + struct cedrus_run { + struct vb2_v4l2_buffer *src; + struct vb2_v4l2_buffer *dst; +@@ -73,6 +81,7 @@ struct cedrus_run { + union { + struct cedrus_h264_run h264; + struct cedrus_mpeg2_run mpeg2; ++ struct cedrus_h265_run h265; + }; + }; + +@@ -111,6 +120,14 @@ struct cedrus_ctx { + void *neighbor_info_buf; + dma_addr_t neighbor_info_buf_dma; + } h264; ++ struct { ++ void *mv_col_buf; ++ dma_addr_t mv_col_buf_addr; ++ ssize_t mv_col_buf_size; ++ ssize_t mv_col_buf_unit_size; ++ void *neighbor_info_buf; ++ dma_addr_t neighbor_info_buf_addr; ++ } h265; + } codec; + }; + +@@ -154,6 +171,7 @@ struct cedrus_dev { + + extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2; + extern struct cedrus_dec_ops cedrus_dec_ops_h264; ++extern struct cedrus_dec_ops cedrus_dec_ops_h265; + + static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val) + { +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +index abf17dc18ecf..c50397f8692f 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +@@ -61,6 +61,15 @@ void cedrus_device_run(void *priv) + V4L2_CID_MPEG_VIDEO_H264_SPS); + break; + ++ case V4L2_PIX_FMT_HEVC_SLICE: ++ run.h265.sps = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_HEVC_SPS); ++ run.h265.pps = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_HEVC_PPS); ++ run.h265.slice_params = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS); ++ break; ++ + default: + break; + } +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +new file mode 100644 +index 000000000000..f1c3665e95ab +--- /dev/null ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +@@ -0,0 +1,531 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Cedrus VPU driver ++ * ++ * Copyright (C) 2013 Jens Kuske ++ * Copyright (C) 2018 Paul Kocialkowski ++ * Copyright (C) 2018 Bootlin ++ */ ++ ++#include ++ ++#include ++ ++#include "cedrus.h" ++#include "cedrus_hw.h" ++#include "cedrus_regs.h" ++ ++/* ++ * These are the sizes for side buffers required by the hardware for storing ++ * internal decoding metadata. They match the values used by the early BSP ++ * implementations, that were initially exposed in libvdpau-sunxi. ++ * Subsequent BSP implementations seem to double the neighbor info buffer size ++ * for the H6 SoC, which may be related to 10 bit H265 support. ++ */ ++#define CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE (397 * SZ_1K) ++#define CEDRUS_H265_ENTRY_POINTS_BUF_SIZE (4 * SZ_1K) ++#define CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE 160 ++ ++struct cedrus_h265_sram_frame_info { ++ __le32 top_pic_order_cnt; ++ __le32 bottom_pic_order_cnt; ++ __le32 top_mv_col_buf_addr; ++ __le32 bottom_mv_col_buf_addr; ++ __le32 luma_addr; ++ __le32 chroma_addr; ++} __packed; ++ ++struct cedrus_h265_sram_pred_weight { ++ __s8 delta_weight; ++ __s8 offset; ++} __packed; ++ ++static enum cedrus_irq_status cedrus_h265_irq_status(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ u32 reg; ++ ++ reg = cedrus_read(dev, VE_DEC_H265_STATUS); ++ reg &= VE_DEC_H265_STATUS_CHECK_MASK; ++ ++ if (reg & VE_DEC_H265_STATUS_CHECK_ERROR || ++ !(reg & VE_DEC_H265_STATUS_SUCCESS)) ++ return CEDRUS_IRQ_ERROR; ++ ++ return CEDRUS_IRQ_OK; ++} ++ ++static void cedrus_h265_irq_clear(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ ++ cedrus_write(dev, VE_DEC_H265_STATUS, VE_DEC_H265_STATUS_CHECK_MASK); ++} ++ ++static void cedrus_h265_irq_disable(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ u32 reg = cedrus_read(dev, VE_DEC_H265_CTRL); ++ ++ reg &= ~VE_DEC_H265_CTRL_IRQ_MASK; ++ ++ cedrus_write(dev, VE_DEC_H265_CTRL, reg); ++} ++ ++static void cedrus_h265_sram_write_offset(struct cedrus_dev *dev, u32 offset) ++{ ++ cedrus_write(dev, VE_DEC_H265_SRAM_OFFSET, offset); ++} ++ ++static void cedrus_h265_sram_write_data(struct cedrus_dev *dev, void *data, ++ unsigned int size) ++{ ++ u32 *word = data; ++ ++ while (size >= sizeof(u32)) { ++ cedrus_write(dev, VE_DEC_H265_SRAM_DATA, *word++); ++ size -= sizeof(u32); ++ } ++} ++ ++static inline dma_addr_t ++cedrus_h265_frame_info_mv_col_buf_addr(struct cedrus_ctx *ctx, ++ unsigned int index, unsigned int field) ++{ ++ return ctx->codec.h265.mv_col_buf_addr + index * ++ ctx->codec.h265.mv_col_buf_unit_size + ++ field * ctx->codec.h265.mv_col_buf_unit_size / 2; ++} ++ ++static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx, ++ unsigned int index, ++ bool field_pic, ++ u32 pic_order_cnt[], ++ int buffer_index) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ dma_addr_t dst_luma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 0); ++ dma_addr_t dst_chroma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 1); ++ dma_addr_t mv_col_buf_addr[2] = { ++ cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, 0), ++ cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, ++ field_pic ? 1 : 0) ++ }; ++ u32 offset = VE_DEC_H265_SRAM_OFFSET_FRAME_INFO + ++ VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT * index; ++ struct cedrus_h265_sram_frame_info frame_info = { ++ .top_pic_order_cnt = pic_order_cnt[0], ++ .bottom_pic_order_cnt = field_pic ? pic_order_cnt[1] : ++ pic_order_cnt[0], ++ .top_mv_col_buf_addr = ++ VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0]), ++ .bottom_mv_col_buf_addr = field_pic ? ++ VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[1]) : ++ VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0]), ++ .luma_addr = VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_luma_addr), ++ .chroma_addr = VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_chroma_addr), ++ }; ++ ++ cedrus_h265_sram_write_offset(dev, offset); ++ cedrus_h265_sram_write_data(dev, &frame_info, sizeof(frame_info)); ++} ++ ++static void cedrus_h265_frame_info_write_dpb(struct cedrus_ctx *ctx, ++ const struct v4l2_hevc_dpb_entry *dpb, ++ u8 num_active_dpb_entries) ++{ ++ struct vb2_queue *vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, ++ V4L2_BUF_TYPE_VIDEO_CAPTURE); ++ unsigned int i; ++ ++ for (i = 0; i < num_active_dpb_entries; i++) { ++ int buffer_index = vb2_find_timestamp(vq, dpb[i].timestamp, 0); ++ u32 pic_order_cnt[2] = { ++ dpb[i].pic_order_cnt[0], ++ dpb[i].pic_order_cnt[1] ++ }; ++ ++ cedrus_h265_frame_info_write_single(ctx, i, dpb[i].field_pic, ++ pic_order_cnt, ++ buffer_index); ++ } ++} ++ ++static void cedrus_h265_ref_pic_list_write(struct cedrus_dev *dev, ++ const struct v4l2_hevc_dpb_entry *dpb, ++ const u8 list[], ++ u8 num_ref_idx_active, ++ u32 sram_offset) ++{ ++ unsigned int i; ++ u32 word = 0; ++ ++ cedrus_h265_sram_write_offset(dev, sram_offset); ++ ++ for (i = 0; i < num_ref_idx_active; i++) { ++ unsigned int shift = (i % 4) * 8; ++ unsigned int index = list[i]; ++ u8 value = list[i]; ++ ++ if (dpb[index].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR) ++ value |= VE_DEC_H265_SRAM_REF_PIC_LIST_LT_REF; ++ ++ /* Each SRAM word gathers up to 4 references. */ ++ word |= value << shift; ++ ++ /* Write the word to SRAM and clear it for the next batch. */ ++ if ((i % 4) == 3 || i == (num_ref_idx_active - 1)) { ++ cedrus_h265_sram_write_data(dev, &word, sizeof(word)); ++ word = 0; ++ } ++ } ++} ++ ++static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev, ++ const s8 delta_luma_weight[], ++ const s8 luma_offset[], ++ const s8 delta_chroma_weight[][2], ++ const s8 chroma_offset[][2], ++ u8 num_ref_idx_active, ++ u32 sram_luma_offset, ++ u32 sram_chroma_offset) ++{ ++ struct cedrus_h265_sram_pred_weight pred_weight[2] = { 0 }; ++ unsigned int i, j; ++ ++ cedrus_h265_sram_write_offset(dev, sram_luma_offset); ++ ++ for (i = 0; i < num_ref_idx_active; i++) { ++ unsigned int index = i % 2; ++ ++ pred_weight[index].delta_weight = delta_luma_weight[i]; ++ pred_weight[index].offset = luma_offset[i]; ++ ++ if (index == 1 || i == (num_ref_idx_active - 1)) ++ cedrus_h265_sram_write_data(dev, (u32 *)&pred_weight, ++ sizeof(pred_weight)); ++ } ++ ++ cedrus_h265_sram_write_offset(dev, sram_chroma_offset); ++ ++ for (i = 0; i < num_ref_idx_active; i++) { ++ for (j = 0; j < 2; j++) { ++ pred_weight[j].delta_weight = delta_chroma_weight[i][j]; ++ pred_weight[j].offset = chroma_offset[i][j]; ++ } ++ ++ cedrus_h265_sram_write_data(dev, &pred_weight, ++ sizeof(pred_weight)); ++ } ++} ++ ++static void cedrus_h265_setup(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ const struct v4l2_ctrl_hevc_sps *sps; ++ const struct v4l2_ctrl_hevc_pps *pps; ++ const struct v4l2_ctrl_hevc_slice_params *slice_params; ++ const struct v4l2_hevc_pred_weight_table *pred_weight_table; ++ dma_addr_t src_buf_addr; ++ dma_addr_t src_buf_end_addr; ++ u32 chroma_log2_weight_denom; ++ u32 output_pic_list_index; ++ u32 pic_order_cnt[2]; ++ u32 reg; ++ ++ sps = run->h265.sps; ++ pps = run->h265.pps; ++ slice_params = run->h265.slice_params; ++ pred_weight_table = &slice_params->pred_weight_table; ++ ++ /* MV column buffer size and allocation. */ ++ if (!ctx->codec.h265.mv_col_buf_size) { ++ unsigned int num_buffers = ++ run->dst->vb2_buf.vb2_queue->num_buffers; ++ unsigned int log2_max_luma_coding_block_size = ++ sps->log2_min_luma_coding_block_size_minus3 + 3 + ++ sps->log2_diff_max_min_luma_coding_block_size; ++ unsigned int ctb_size_luma = ++ 1 << log2_max_luma_coding_block_size; ++ ++ /* ++ * Each CTB requires a MV col buffer with a specific unit size. ++ * Since the address is given with missing lsb bits, 1 KiB is ++ * added to each buffer to ensure proper alignment. ++ */ ++ ctx->codec.h265.mv_col_buf_unit_size = ++ DIV_ROUND_UP(ctx->src_fmt.width, ctb_size_luma) * ++ DIV_ROUND_UP(ctx->src_fmt.height, ctb_size_luma) * ++ CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE + SZ_1K; ++ ++ ctx->codec.h265.mv_col_buf_size = num_buffers * ++ ctx->codec.h265.mv_col_buf_unit_size; ++ ++ ctx->codec.h265.mv_col_buf = ++ dma_alloc_coherent(dev->dev, ++ ctx->codec.h265.mv_col_buf_size, ++ &ctx->codec.h265.mv_col_buf_addr, ++ GFP_KERNEL); ++ if (!ctx->codec.h265.mv_col_buf) { ++ ctx->codec.h265.mv_col_buf_size = 0; ++ // TODO: Abort the process here. ++ return; ++ } ++ } ++ ++ /* Activate H265 engine. */ ++ cedrus_engine_enable(dev, CEDRUS_CODEC_H265); ++ ++ /* Source offset and length in bits. */ ++ ++ reg = slice_params->data_bit_offset; ++ cedrus_write(dev, VE_DEC_H265_BITS_OFFSET, reg); ++ ++ reg = slice_params->bit_size - slice_params->data_bit_offset; ++ cedrus_write(dev, VE_DEC_H265_BITS_LEN, reg); ++ ++ /* Source beginning and end addresses. */ ++ ++ src_buf_addr = vb2_dma_contig_plane_dma_addr(&run->src->vb2_buf, 0); ++ ++ reg = VE_DEC_H265_BITS_ADDR_BASE(src_buf_addr); ++ reg |= VE_DEC_H265_BITS_ADDR_VALID_SLICE_DATA; ++ reg |= VE_DEC_H265_BITS_ADDR_LAST_SLICE_DATA; ++ reg |= VE_DEC_H265_BITS_ADDR_FIRST_SLICE_DATA; ++ ++ cedrus_write(dev, VE_DEC_H265_BITS_ADDR, reg); ++ ++ src_buf_end_addr = src_buf_addr + ++ DIV_ROUND_UP(slice_params->bit_size, 8); ++ ++ reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_end_addr); ++ cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg); ++ ++ /* Coding tree block address: start at the beginning. */ ++ reg = VE_DEC_H265_DEC_CTB_ADDR_X(0) | VE_DEC_H265_DEC_CTB_ADDR_Y(0); ++ cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg); ++ ++ cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0); ++ cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0); ++ ++ /* Clear the number of correctly-decoded coding tree blocks. */ ++ cedrus_write(dev, VE_DEC_H265_DEC_CTB_NUM, 0); ++ ++ /* Initialize bitstream access. */ ++ cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC); ++ ++ /* Bitstream parameters. */ ++ ++ reg = VE_DEC_H265_DEC_NAL_HDR_NAL_UNIT_TYPE(slice_params->nal_unit_type) | ++ VE_DEC_H265_DEC_NAL_HDR_NUH_TEMPORAL_ID_PLUS1(slice_params->nuh_temporal_id_plus1); ++ ++ cedrus_write(dev, VE_DEC_H265_DEC_NAL_HDR, reg); ++ ++ reg = VE_DEC_H265_DEC_SPS_HDR_STRONG_INTRA_SMOOTHING_ENABLE_FLAG(sps->strong_intra_smoothing_enabled_flag) | ++ VE_DEC_H265_DEC_SPS_HDR_SPS_TEMPORAL_MVP_ENABLED_FLAG(sps->sps_temporal_mvp_enabled_flag) | ++ VE_DEC_H265_DEC_SPS_HDR_SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG(sps->sample_adaptive_offset_enabled_flag) | ++ VE_DEC_H265_DEC_SPS_HDR_AMP_ENABLED_FLAG(sps->amp_enabled_flag) | ++ VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(sps->max_transform_hierarchy_depth_intra) | ++ VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(sps->max_transform_hierarchy_depth_inter) | ++ VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(sps->log2_diff_max_min_luma_transform_block_size) | ++ VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(sps->log2_min_luma_transform_block_size_minus2) | ++ VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_luma_coding_block_size) | ++ VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_luma_coding_block_size_minus3) | ++ VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(sps->bit_depth_chroma_minus8) | ++ VE_DEC_H265_DEC_SPS_HDR_SEPARATE_COLOUR_PLANE_FLAG(sps->separate_colour_plane_flag) | ++ VE_DEC_H265_DEC_SPS_HDR_CHROMA_FORMAT_IDC(sps->chroma_format_idc); ++ ++ cedrus_write(dev, VE_DEC_H265_DEC_SPS_HDR, reg); ++ ++ reg = VE_DEC_H265_DEC_PCM_CTRL_PCM_ENABLED_FLAG(sps->pcm_enabled_flag) | ++ VE_DEC_H265_DEC_PCM_CTRL_PCM_LOOP_FILTER_DISABLED_FLAG(sps->pcm_loop_filter_disabled_flag) | ++ VE_DEC_H265_DEC_PCM_CTRL_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_pcm_luma_coding_block_size) | ++ VE_DEC_H265_DEC_PCM_CTRL_LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_pcm_luma_coding_block_size_minus3) | ++ VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_CHROMA_MINUS1(sps->pcm_sample_bit_depth_chroma_minus1) | ++ VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_LUMA_MINUS1(sps->pcm_sample_bit_depth_luma_minus1); ++ ++ cedrus_write(dev, VE_DEC_H265_DEC_PCM_CTRL, reg); ++ ++ reg = VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(pps->pps_cr_qp_offset) | ++ VE_DEC_H265_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(pps->pps_cb_qp_offset) | ++ VE_DEC_H265_DEC_PPS_CTRL0_INIT_QP_MINUS26(pps->init_qp_minus26) | ++ VE_DEC_H265_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(pps->diff_cu_qp_delta_depth) | ++ VE_DEC_H265_DEC_PPS_CTRL0_CU_QP_DELTA_ENABLED_FLAG(pps->cu_qp_delta_enabled_flag) | ++ VE_DEC_H265_DEC_PPS_CTRL0_TRANSFORM_SKIP_ENABLED_FLAG(pps->transform_skip_enabled_flag) | ++ VE_DEC_H265_DEC_PPS_CTRL0_CONSTRAINED_INTRA_PRED_FLAG(pps->constrained_intra_pred_flag) | ++ VE_DEC_H265_DEC_PPS_CTRL0_SIGN_DATA_HIDING_FLAG(pps->sign_data_hiding_enabled_flag); ++ ++ cedrus_write(dev, VE_DEC_H265_DEC_PPS_CTRL0, reg); ++ ++ reg = VE_DEC_H265_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(pps->log2_parallel_merge_level_minus2) | ++ VE_DEC_H265_DEC_PPS_CTRL1_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG(pps->pps_loop_filter_across_slices_enabled_flag) | ++ VE_DEC_H265_DEC_PPS_CTRL1_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG(pps->loop_filter_across_tiles_enabled_flag) | ++ VE_DEC_H265_DEC_PPS_CTRL1_ENTROPY_CODING_SYNC_ENABLED_FLAG(pps->entropy_coding_sync_enabled_flag) | ++ VE_DEC_H265_DEC_PPS_CTRL1_TILES_ENABLED_FLAG(0) | ++ VE_DEC_H265_DEC_PPS_CTRL1_TRANSQUANT_BYPASS_ENABLE_FLAG(pps->transquant_bypass_enabled_flag) | ++ VE_DEC_H265_DEC_PPS_CTRL1_WEIGHTED_BIPRED_FLAG(pps->weighted_bipred_flag) | ++ VE_DEC_H265_DEC_PPS_CTRL1_WEIGHTED_PRED_FLAG(pps->weighted_pred_flag); ++ ++ cedrus_write(dev, VE_DEC_H265_DEC_PPS_CTRL1, reg); ++ ++ reg = VE_DEC_H265_DEC_SLICE_HDR_INFO0_PICTURE_TYPE(slice_params->pic_struct) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO0_FIVE_MINUS_MAX_NUM_MERGE_CAND(slice_params->five_minus_max_num_merge_cand) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L1_ACTIVE_MINUS1(slice_params->num_ref_idx_l1_active_minus1) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L0_ACTIVE_MINUS1(slice_params->num_ref_idx_l0_active_minus1) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLLOCATED_REF_IDX(slice_params->collocated_ref_idx) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLLOCATED_FROM_L0_FLAG(slice_params->collocated_from_l0_flag) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO0_CABAC_INIT_FLAG(slice_params->cabac_init_flag) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO0_MVD_L1_ZERO_FLAG(slice_params->mvd_l1_zero_flag) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_SAO_CHROMA_FLAG(slice_params->slice_sao_chroma_flag) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_SAO_LUMA_FLAG(slice_params->slice_sao_luma_flag) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TEMPORAL_MVP_ENABLE_FLAG(slice_params->slice_temporal_mvp_enabled_flag) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(slice_params->colour_plane_id) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TYPE(slice_params->slice_type) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO0_DEPENDENT_SLICE_SEGMENT_FLAG(pps->dependent_slice_segment_flag) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO0_FIRST_SLICE_SEGMENT_IN_PIC_FLAG(1); ++ ++ cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO0, reg); ++ ++ reg = VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(slice_params->slice_tc_offset_div2) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(slice_params->slice_beta_offset_div2) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_DEBLOCKING_FILTER_DISABLED_FLAG(slice_params->slice_deblocking_filter_disabled_flag) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG(slice_params->slice_loop_filter_across_slices_enabled_flag) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(slice_params->num_rps_poc_st_curr_after == 0) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(slice_params->slice_cr_qp_offset) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(slice_params->slice_cb_qp_offset) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(slice_params->slice_qp_delta); ++ ++ cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO1, reg); ++ ++ chroma_log2_weight_denom = pred_weight_table->luma_log2_weight_denom + ++ pred_weight_table->delta_chroma_log2_weight_denom; ++ reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(0) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(chroma_log2_weight_denom) | ++ VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(pred_weight_table->luma_log2_weight_denom); ++ ++ cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO2, reg); ++ ++ /* Decoded picture size. */ ++ ++ reg = VE_DEC_H265_DEC_PIC_SIZE_WIDTH(ctx->src_fmt.width) | ++ VE_DEC_H265_DEC_PIC_SIZE_HEIGHT(ctx->src_fmt.height); ++ ++ cedrus_write(dev, VE_DEC_H265_DEC_PIC_SIZE, reg); ++ ++ /* Scaling list. */ ++ ++ reg = VE_DEC_H265_SCALING_LIST_CTRL0_DEFAULT; ++ cedrus_write(dev, VE_DEC_H265_SCALING_LIST_CTRL0, reg); ++ ++ /* Neightbor information address. */ ++ reg = VE_DEC_H265_NEIGHBOR_INFO_ADDR_BASE(ctx->codec.h265.neighbor_info_buf_addr); ++ cedrus_write(dev, VE_DEC_H265_NEIGHBOR_INFO_ADDR, reg); ++ ++ /* Write decoded picture buffer in pic list. */ ++ cedrus_h265_frame_info_write_dpb(ctx, slice_params->dpb, ++ slice_params->num_active_dpb_entries); ++ ++ /* Output frame. */ ++ ++ output_pic_list_index = V4L2_HEVC_DPB_ENTRIES_NUM_MAX; ++ pic_order_cnt[0] = slice_params->slice_pic_order_cnt; ++ pic_order_cnt[1] = slice_params->slice_pic_order_cnt; ++ ++ cedrus_h265_frame_info_write_single(ctx, output_pic_list_index, ++ slice_params->pic_struct != 0, ++ pic_order_cnt, ++ run->dst->vb2_buf.index); ++ ++ cedrus_write(dev, VE_DEC_H265_OUTPUT_FRAME_IDX, output_pic_list_index); ++ ++ /* Reference picture list 0 (for P/B frames). */ ++ if (slice_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { ++ cedrus_h265_ref_pic_list_write(dev, slice_params->dpb, ++ slice_params->ref_idx_l0, ++ slice_params->num_ref_idx_l0_active_minus1 + 1, ++ VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0); ++ ++ if (pps->weighted_pred_flag || pps->weighted_bipred_flag) ++ cedrus_h265_pred_weight_write(dev, ++ pred_weight_table->delta_luma_weight_l0, ++ pred_weight_table->luma_offset_l0, ++ pred_weight_table->delta_chroma_weight_l0, ++ pred_weight_table->chroma_offset_l0, ++ slice_params->num_ref_idx_l0_active_minus1 + 1, ++ VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0, ++ VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0); ++ } ++ ++ /* Reference picture list 1 (for B frames). */ ++ if (slice_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) { ++ cedrus_h265_ref_pic_list_write(dev, slice_params->dpb, ++ slice_params->ref_idx_l1, ++ slice_params->num_ref_idx_l1_active_minus1 + 1, ++ VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1); ++ ++ if (pps->weighted_bipred_flag) ++ cedrus_h265_pred_weight_write(dev, ++ pred_weight_table->delta_luma_weight_l1, ++ pred_weight_table->luma_offset_l1, ++ pred_weight_table->delta_chroma_weight_l1, ++ pred_weight_table->chroma_offset_l1, ++ slice_params->num_ref_idx_l1_active_minus1 + 1, ++ VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1, ++ VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1); ++ } ++ ++ /* Enable appropriate interruptions. */ ++ cedrus_write(dev, VE_DEC_H265_CTRL, VE_DEC_H265_CTRL_IRQ_MASK); ++} ++ ++static int cedrus_h265_start(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ ++ /* The buffer size is calculated at setup time. */ ++ ctx->codec.h265.mv_col_buf_size = 0; ++ ++ ctx->codec.h265.neighbor_info_buf = ++ dma_alloc_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, ++ &ctx->codec.h265.neighbor_info_buf_addr, ++ GFP_KERNEL); ++ if (!ctx->codec.h265.neighbor_info_buf) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++static void cedrus_h265_stop(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ ++ if (ctx->codec.h265.mv_col_buf_size > 0) { ++ dma_free_coherent(dev->dev, ctx->codec.h265.mv_col_buf_size, ++ ctx->codec.h265.mv_col_buf, ++ ctx->codec.h265.mv_col_buf_addr); ++ ++ ctx->codec.h265.mv_col_buf_size = 0; ++ } ++ ++ dma_free_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, ++ ctx->codec.h265.neighbor_info_buf, ++ ctx->codec.h265.neighbor_info_buf_addr); ++} ++ ++static void cedrus_h265_trigger(struct cedrus_ctx *ctx) ++{ ++ struct cedrus_dev *dev = ctx->dev; ++ ++ cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_DEC_SLICE); ++} ++ ++struct cedrus_dec_ops cedrus_dec_ops_h265 = { ++ .irq_clear = cedrus_h265_irq_clear, ++ .irq_disable = cedrus_h265_irq_disable, ++ .irq_status = cedrus_h265_irq_status, ++ .setup = cedrus_h265_setup, ++ .start = cedrus_h265_start, ++ .stop = cedrus_h265_stop, ++ .trigger = cedrus_h265_trigger, ++}; +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +index ab402b0cac4e..6be604c52d5c 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +@@ -50,6 +50,10 @@ int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) + reg |= VE_MODE_DEC_H264; + break; + ++ case CEDRUS_CODEC_H265: ++ reg |= VE_MODE_DEC_H265; ++ break; ++ + default: + return -EINVAL; + } +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +index 3e9931416e45..87651d6b6227 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +@@ -18,10 +18,17 @@ + * * MC: Motion Compensation + * * STCD: Start Code Detect + * * SDRT: Scale Down and Rotate ++ * * WB: Writeback ++ * * BITS/BS: Bitstream ++ * * MB: Macroblock ++ * * CTU: Coding Tree Unit ++ * * CTB: Coding Tree Block ++ * * IDX: Index + */ + + #define VE_ENGINE_DEC_MPEG 0x100 + #define VE_ENGINE_DEC_H264 0x200 ++#define VE_ENGINE_DEC_H265 0x500 + + #define VE_MODE 0x00 + +@@ -232,6 +239,289 @@ + #define VE_DEC_MPEG_ROT_LUMA (VE_ENGINE_DEC_MPEG + 0xcc) + #define VE_DEC_MPEG_ROT_CHROMA (VE_ENGINE_DEC_MPEG + 0xd0) + ++#define VE_DEC_H265_DEC_NAL_HDR (VE_ENGINE_DEC_H265 + 0x00) ++ ++#define VE_DEC_H265_DEC_NAL_HDR_NUH_TEMPORAL_ID_PLUS1(v) \ ++ (((v) << 6) & GENMASK(8, 6)) ++#define VE_DEC_H265_DEC_NAL_HDR_NAL_UNIT_TYPE(v) \ ++ ((v) & GENMASK(5, 0)) ++ ++#define VE_DEC_H265_DEC_SPS_HDR (VE_ENGINE_DEC_H265 + 0x04) ++ ++#define VE_DEC_H265_DEC_SPS_HDR_STRONG_INTRA_SMOOTHING_ENABLE_FLAG(v) \ ++ ((v) ? BIT(26) : 0) ++#define VE_DEC_H265_DEC_SPS_HDR_SPS_TEMPORAL_MVP_ENABLED_FLAG(v) \ ++ ((v) ? BIT(25) : 0) ++#define VE_DEC_H265_DEC_SPS_HDR_SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG(v) \ ++ ((v) ? BIT(24) : 0) ++#define VE_DEC_H265_DEC_SPS_HDR_AMP_ENABLED_FLAG(v) \ ++ ((v) ? BIT(23) : 0) ++#define VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(v) \ ++ (((v) << 20) & GENMASK(22, 20)) ++#define VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(v) \ ++ (((v) << 17) & GENMASK(19, 17)) ++#define VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(v) \ ++ (((v) << 15) & GENMASK(16, 15)) ++#define VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(v) \ ++ (((v) << 13) & GENMASK(14, 13)) ++#define VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(v) \ ++ (((v) << 11) & GENMASK(12, 11)) ++#define VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(v) \ ++ (((v) << 9) & GENMASK(10, 9)) ++#define VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(v) \ ++ (((v) << 6) & GENMASK(8, 6)) ++#define VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_LUMA_MINUS8(v) \ ++ (((v) << 3) & GENMASK(5, 3)) ++#define VE_DEC_H265_DEC_SPS_HDR_SEPARATE_COLOUR_PLANE_FLAG(v) \ ++ ((v) ? BIT(2) : 0) ++#define VE_DEC_H265_DEC_SPS_HDR_CHROMA_FORMAT_IDC(v) \ ++ ((v) & GENMASK(1, 0)) ++ ++#define VE_DEC_H265_DEC_PIC_SIZE (VE_ENGINE_DEC_H265 + 0x08) ++ ++#define VE_DEC_H265_DEC_PIC_SIZE_WIDTH(w) (((w) << 0) & GENMASK(13, 0)) ++#define VE_DEC_H265_DEC_PIC_SIZE_HEIGHT(h) (((h) << 16) & GENMASK(29, 16)) ++ ++#define VE_DEC_H265_DEC_PCM_CTRL (VE_ENGINE_DEC_H265 + 0x0c) ++ ++#define VE_DEC_H265_DEC_PCM_CTRL_PCM_ENABLED_FLAG(v) \ ++ ((v) ? BIT(15) : 0) ++#define VE_DEC_H265_DEC_PCM_CTRL_PCM_LOOP_FILTER_DISABLED_FLAG(v) \ ++ ((v) ? BIT(14) : 0) ++#define VE_DEC_H265_DEC_PCM_CTRL_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE(v) \ ++ (((v) << 10) & GENMASK(11, 10)) ++#define VE_DEC_H265_DEC_PCM_CTRL_LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3(v) \ ++ (((v) << 8) & GENMASK(9, 8)) ++#define VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_CHROMA_MINUS1(v) \ ++ (((v) << 4) & GENMASK(7, 4)) ++#define VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_LUMA_MINUS1(v) \ ++ (((v) << 0) & GENMASK(3, 0)) ++ ++#define VE_DEC_H265_DEC_PPS_CTRL0 (VE_ENGINE_DEC_H265 + 0x10) ++ ++#define VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(v) \ ++ (((v) << 24) & GENMASK(29, 24)) ++#define VE_DEC_H265_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(v) \ ++ (((v) << 16) & GENMASK(21, 16)) ++#define VE_DEC_H265_DEC_PPS_CTRL0_INIT_QP_MINUS26(v) \ ++ (((v) << 8) & GENMASK(14, 8)) ++#define VE_DEC_H265_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(v) \ ++ (((v) << 4) & GENMASK(5, 4)) ++#define VE_DEC_H265_DEC_PPS_CTRL0_CU_QP_DELTA_ENABLED_FLAG(v) \ ++ ((v) ? BIT(3) : 0) ++#define VE_DEC_H265_DEC_PPS_CTRL0_TRANSFORM_SKIP_ENABLED_FLAG(v) \ ++ ((v) ? BIT(2) : 0) ++#define VE_DEC_H265_DEC_PPS_CTRL0_CONSTRAINED_INTRA_PRED_FLAG(v) \ ++ ((v) ? BIT(1) : 0) ++#define VE_DEC_H265_DEC_PPS_CTRL0_SIGN_DATA_HIDING_FLAG(v) \ ++ ((v) ? BIT(0) : 0) ++ ++#define VE_DEC_H265_DEC_PPS_CTRL1 (VE_ENGINE_DEC_H265 + 0x14) ++ ++#define VE_DEC_H265_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(v) \ ++ (((v) << 8) & GENMASK(10, 8)) ++#define VE_DEC_H265_DEC_PPS_CTRL1_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG(v) \ ++ ((v) ? BIT(6) : 0) ++#define VE_DEC_H265_DEC_PPS_CTRL1_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG(v) \ ++ ((v) ? BIT(5) : 0) ++#define VE_DEC_H265_DEC_PPS_CTRL1_ENTROPY_CODING_SYNC_ENABLED_FLAG(v) \ ++ ((v) ? BIT(4) : 0) ++#define VE_DEC_H265_DEC_PPS_CTRL1_TILES_ENABLED_FLAG(v) \ ++ ((v) ? BIT(3) : 0) ++#define VE_DEC_H265_DEC_PPS_CTRL1_TRANSQUANT_BYPASS_ENABLE_FLAG(v) \ ++ ((v) ? BIT(2) : 0) ++#define VE_DEC_H265_DEC_PPS_CTRL1_WEIGHTED_BIPRED_FLAG(v) \ ++ ((v) ? BIT(1) : 0) ++#define VE_DEC_H265_DEC_PPS_CTRL1_WEIGHTED_PRED_FLAG(v) \ ++ ((v) ? BIT(0) : 0) ++ ++#define VE_DEC_H265_SCALING_LIST_CTRL0 (VE_ENGINE_DEC_H265 + 0x18) ++ ++#define VE_DEC_H265_SCALING_LIST_CTRL0_ENABLED_FLAG(v) \ ++ ((v) ? BIT(31) : 0) ++#define VE_DEC_H265_SCALING_LIST_CTRL0_SRAM (0 << 30) ++#define VE_DEC_H265_SCALING_LIST_CTRL0_DEFAULT (1 << 30) ++ ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO0 (VE_ENGINE_DEC_H265 + 0x20) ++ ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_PICTURE_TYPE(v) \ ++ (((v) << 28) & GENMASK(29, 28)) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FIVE_MINUS_MAX_NUM_MERGE_CAND(v) \ ++ (((v) << 24) & GENMASK(26, 24)) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L1_ACTIVE_MINUS1(v) \ ++ (((v) << 20) & GENMASK(23, 20)) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L0_ACTIVE_MINUS1(v) \ ++ (((v) << 16) & GENMASK(19, 16)) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLLOCATED_REF_IDX(v) \ ++ (((v) << 12) & GENMASK(15, 12)) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLLOCATED_FROM_L0_FLAG(v) \ ++ ((v) ? BIT(11) : 0) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_CABAC_INIT_FLAG(v) \ ++ ((v) ? BIT(10) : 0) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_MVD_L1_ZERO_FLAG(v) \ ++ ((v) ? BIT(9) : 0) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_SAO_CHROMA_FLAG(v) \ ++ ((v) ? BIT(8) : 0) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_SAO_LUMA_FLAG(v) \ ++ ((v) ? BIT(7) : 0) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TEMPORAL_MVP_ENABLE_FLAG(v) \ ++ ((v) ? BIT(6) : 0) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(v) \ ++ (((v) << 4) & GENMASK(5, 4)) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TYPE(v) \ ++ (((v) << 2) & GENMASK(3, 2)) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_DEPENDENT_SLICE_SEGMENT_FLAG(v) \ ++ ((v) ? BIT(1) : 0) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FIRST_SLICE_SEGMENT_IN_PIC_FLAG(v) \ ++ ((v) ? BIT(0) : 0) ++ ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO1 (VE_ENGINE_DEC_H265 + 0x24) ++ ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(v) \ ++ (((v) << 28) & GENMASK(31, 28)) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(v) \ ++ (((v) << 24) & GENMASK(27, 24)) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_DEBLOCKING_FILTER_DISABLED_FLAG(v) \ ++ ((v) ? BIT(23) : 0) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG(v) \ ++ ((v) ? BIT(22) : 0) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(v) \ ++ ((v) ? BIT(21) : 0) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(v) \ ++ (((v) << 16) & GENMASK(20, 16)) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(v) \ ++ (((v) << 8) & GENMASK(12, 8)) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(v) \ ++ ((v) & GENMASK(6, 0)) ++ ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO2 (VE_ENGINE_DEC_H265 + 0x28) ++ ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(v) \ ++ (((v) << 8) & GENMASK(21, 8)) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(v) \ ++ (((v) << 4) & GENMASK(6, 4)) ++#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(v) \ ++ (((v) << 0) & GENMASK(2, 0)) ++ ++#define VE_DEC_H265_DEC_CTB_ADDR (VE_ENGINE_DEC_H265 + 0x2c) ++ ++#define VE_DEC_H265_DEC_CTB_ADDR_Y(y) (((y) << 16) & GENMASK(25, 16)) ++#define VE_DEC_H265_DEC_CTB_ADDR_X(x) (((x) << 0) & GENMASK(9, 0)) ++ ++#define VE_DEC_H265_CTRL (VE_ENGINE_DEC_H265 + 0x30) ++ ++#define VE_DEC_H265_CTRL_DDR_CONSISTENCY_EN BIT(31) ++#define VE_DEC_H265_CTRL_STCD_EN BIT(25) ++#define VE_DEC_H265_CTRL_EPTB_DEC_BYPASS_EN BIT(24) ++#define VE_DEC_H265_CTRL_TQ_BYPASS_EN BIT(12) ++#define VE_DEC_H265_CTRL_VLD_BYPASS_EN BIT(11) ++#define VE_DEC_H265_CTRL_NCRI_CACHE_DISABLE BIT(10) ++#define VE_DEC_H265_CTRL_ROTATE_SCALE_OUT_EN BIT(9) ++#define VE_DEC_H265_CTRL_MC_NO_WRITEBACK BIT(8) ++#define VE_DEC_H265_CTRL_VLD_DATA_REQ_IRQ_EN BIT(2) ++#define VE_DEC_H265_CTRL_ERROR_IRQ_EN BIT(1) ++#define VE_DEC_H265_CTRL_FINISH_IRQ_EN BIT(0) ++#define VE_DEC_H265_CTRL_IRQ_MASK \ ++ (VE_DEC_H265_CTRL_FINISH_IRQ_EN | VE_DEC_H265_CTRL_ERROR_IRQ_EN | \ ++ VE_DEC_H265_CTRL_VLD_DATA_REQ_IRQ_EN) ++ ++#define VE_DEC_H265_TRIGGER (VE_ENGINE_DEC_H265 + 0x34) ++ ++#define VE_DEC_H265_TRIGGER_STCD_VC1 (0x02 << 4) ++#define VE_DEC_H265_TRIGGER_STCD_AVS (0x01 << 4) ++#define VE_DEC_H265_TRIGGER_STCD_HEVC (0x00 << 4) ++#define VE_DEC_H265_TRIGGER_DEC_SLICE (0x08 << 0) ++#define VE_DEC_H265_TRIGGER_INIT_SWDEC (0x07 << 0) ++#define VE_DEC_H265_TRIGGER_BYTE_ALIGN (0x06 << 0) ++#define VE_DEC_H265_TRIGGER_GET_VLCUE (0x05 << 0) ++#define VE_DEC_H265_TRIGGER_GET_VLCSE (0x04 << 0) ++#define VE_DEC_H265_TRIGGER_FLUSH_BITS (0x03 << 0) ++#define VE_DEC_H265_TRIGGER_GET_BITS (0x02 << 0) ++#define VE_DEC_H265_TRIGGER_SHOW_BITS (0x01 << 0) ++ ++#define VE_DEC_H265_STATUS (VE_ENGINE_DEC_H265 + 0x38) ++ ++#define VE_DEC_H265_STATUS_STCD BIT(24) ++#define VE_DEC_H265_STATUS_STCD_BUSY BIT(21) ++#define VE_DEC_H265_STATUS_WB_BUSY BIT(20) ++#define VE_DEC_H265_STATUS_BS_DMA_BUSY BIT(19) ++#define VE_DEC_H265_STATUS_IQIT_BUSY BIT(18) ++#define VE_DEC_H265_STATUS_INTER_BUSY BIT(17) ++#define VE_DEC_H265_STATUS_MORE_DATA BIT(16) ++#define VE_DEC_H265_STATUS_VLD_BUSY BIT(14) ++#define VE_DEC_H265_STATUS_DEBLOCKING_BUSY BIT(13) ++#define VE_DEC_H265_STATUS_DEBLOCKING_DRAM_BUSY BIT(12) ++#define VE_DEC_H265_STATUS_INTRA_BUSY BIT(11) ++#define VE_DEC_H265_STATUS_SAO_BUSY BIT(10) ++#define VE_DEC_H265_STATUS_MVP_BUSY BIT(9) ++#define VE_DEC_H265_STATUS_SWDEC_BUSY BIT(8) ++#define VE_DEC_H265_STATUS_OVER_TIME BIT(3) ++#define VE_DEC_H265_STATUS_VLD_DATA_REQ BIT(2) ++#define VE_DEC_H265_STATUS_ERROR BIT(1) ++#define VE_DEC_H265_STATUS_SUCCESS BIT(0) ++#define VE_DEC_H265_STATUS_STCD_TYPE_MASK GENMASK(23, 22) ++#define VE_DEC_H265_STATUS_CHECK_MASK \ ++ (VE_DEC_H265_STATUS_SUCCESS | VE_DEC_H265_STATUS_ERROR | \ ++ VE_DEC_H265_STATUS_VLD_DATA_REQ) ++#define VE_DEC_H265_STATUS_CHECK_ERROR \ ++ (VE_DEC_H265_STATUS_ERROR | VE_DEC_H265_STATUS_VLD_DATA_REQ) ++ ++#define VE_DEC_H265_DEC_CTB_NUM (VE_ENGINE_DEC_H265 + 0x3c) ++ ++#define VE_DEC_H265_BITS_ADDR (VE_ENGINE_DEC_H265 + 0x40) ++ ++#define VE_DEC_H265_BITS_ADDR_FIRST_SLICE_DATA BIT(30) ++#define VE_DEC_H265_BITS_ADDR_LAST_SLICE_DATA BIT(29) ++#define VE_DEC_H265_BITS_ADDR_VALID_SLICE_DATA BIT(28) ++#define VE_DEC_H265_BITS_ADDR_BASE(a) (((a) >> 8) & GENMASK(27, 0)) ++ ++#define VE_DEC_H265_BITS_OFFSET (VE_ENGINE_DEC_H265 + 0x44) ++#define VE_DEC_H265_BITS_LEN (VE_ENGINE_DEC_H265 + 0x48) ++ ++#define VE_DEC_H265_BITS_END_ADDR (VE_ENGINE_DEC_H265 + 0x4c) ++ ++#define VE_DEC_H265_BITS_END_ADDR_BASE(a) ((a) >> 8) ++ ++#define VE_DEC_H265_SDRT_CTRL (VE_ENGINE_DEC_H265 + 0x50) ++#define VE_DEC_H265_SDRT_LUMA_ADDR (VE_ENGINE_DEC_H265 + 0x54) ++#define VE_DEC_H265_SDRT_CHROMA_ADDR (VE_ENGINE_DEC_H265 + 0x58) ++ ++#define VE_DEC_H265_OUTPUT_FRAME_IDX (VE_ENGINE_DEC_H265 + 0x5c) ++ ++#define VE_DEC_H265_NEIGHBOR_INFO_ADDR (VE_ENGINE_DEC_H265 + 0x60) ++ ++#define VE_DEC_H265_NEIGHBOR_INFO_ADDR_BASE(a) ((a) >> 8) ++ ++#define VE_DEC_H265_ENTRY_POINT_OFFSET_ADDR (VE_ENGINE_DEC_H265 + 0x64) ++#define VE_DEC_H265_TILE_START_CTB (VE_ENGINE_DEC_H265 + 0x68) ++#define VE_DEC_H265_TILE_END_CTB (VE_ENGINE_DEC_H265 + 0x6c) ++ ++#define VE_DEC_H265_LOW_ADDR (VE_ENGINE_DEC_H265 + 0x80) ++ ++#define VE_DEC_H265_LOW_ADDR_PRIMARY_CHROMA(a) \ ++ (((a) << 24) & GENMASK(31, 24)) ++#define VE_DEC_H265_LOW_ADDR_SECONDARY_CHROMA(a) \ ++ (((a) << 16) & GENMASK(23, 16)) ++#define VE_DEC_H265_LOW_ADDR_ENTRY_POINTS_BUF(a) \ ++ (((a) << 0) & GENMASK(7, 0)) ++ ++#define VE_DEC_H265_SRAM_OFFSET (VE_ENGINE_DEC_H265 + 0xe0) ++ ++#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0 0x00 ++#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0 0x20 ++#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1 0x60 ++#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1 0x80 ++#define VE_DEC_H265_SRAM_OFFSET_FRAME_INFO 0x400 ++#define VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT 0x20 ++#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS 0x800 ++#define VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0 0xc00 ++#define VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1 0xc10 ++ ++#define VE_DEC_H265_SRAM_DATA (VE_ENGINE_DEC_H265 + 0xe4) ++ ++#define VE_DEC_H265_SRAM_DATA_ADDR_BASE(a) ((a) >> 8) ++#define VE_DEC_H265_SRAM_REF_PIC_LIST_LT_REF BIT(7) ++ + #define VE_H264_SPS 0x200 + #define VE_H264_SPS_MBS_ONLY BIT(18) + #define VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD BIT(17) +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +index d1c0562d1a62..b871976b5ead 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +@@ -41,6 +41,11 @@ static struct cedrus_format cedrus_formats[] = { + .pixelformat = V4L2_PIX_FMT_H264_SLICE_RAW, + .directions = CEDRUS_DECODE_SRC, + }, ++ { ++ .pixelformat = V4L2_PIX_FMT_HEVC_SLICE, ++ .directions = CEDRUS_DECODE_SRC, ++ .capabilities = CEDRUS_CAPABILITY_H265_DEC, ++ }, + { + .pixelformat = V4L2_PIX_FMT_SUNXI_TILED_NV12, + .directions = CEDRUS_DECODE_DST, +@@ -105,6 +110,7 @@ static void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt) + switch (pix_fmt->pixelformat) { + case V4L2_PIX_FMT_MPEG2_SLICE: + case V4L2_PIX_FMT_H264_SLICE_RAW: ++ case V4L2_PIX_FMT_HEVC_SLICE: + /* Zero bytes per line for encoded source. */ + bytesperline = 0; + +@@ -473,6 +479,10 @@ static int cedrus_start_streaming(struct vb2_queue *vq, unsigned int count) + ctx->current_codec = CEDRUS_CODEC_H264; + break; + ++ case V4L2_PIX_FMT_HEVC_SLICE: ++ ctx->current_codec = CEDRUS_CODEC_H265; ++ break; ++ + default: + return -EINVAL; + } diff --git a/projects/Allwinner/patches/linux/0007-H264-improvements.patch b/projects/Allwinner/patches/linux/0007-H264-improvements.patch new file mode 100644 index 0000000000..0efa61a7fc --- /dev/null +++ b/projects/Allwinner/patches/linux/0007-H264-improvements.patch @@ -0,0 +1,133 @@ +From e41186f41a546d1c60797f090001da969f5eda5a Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Thu, 14 Feb 2019 22:50:12 +0100 +Subject: [PATCH] cedrus: Improve H264 + +Signed-off-by: Jernej Skrabec +--- + .../staging/media/sunxi/cedrus/cedrus_h264.c | 69 +++++++++++-------- + 1 file changed, 41 insertions(+), 28 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +index a5c5f13ffecb..405545947b85 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +@@ -38,7 +38,7 @@ struct cedrus_h264_sram_ref_pic { + #define CEDRUS_H264_FRAME_NUM 18 + + #define CEDRUS_NEIGHBOR_INFO_BUF_SIZE (16 * SZ_1K) +-#define CEDRUS_PIC_INFO_BUF_SIZE (128 * SZ_1K) ++#define CEDRUS_PIC_INFO_BUF_SIZE (336 * SZ_1K) + + static void cedrus_h264_write_sram(struct cedrus_dev *dev, + enum cedrus_h264_sram_off off, +@@ -101,7 +101,7 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, + struct cedrus_dev *dev = ctx->dev; + unsigned long used_dpbs = 0; + unsigned int position; +- unsigned int output = 0; ++ int output = -1; + unsigned int i; + + memset(pic_list, 0, sizeof(pic_list)); +@@ -126,6 +126,11 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, + position = cedrus_buf->codec.h264.position; + used_dpbs |= BIT(position); + ++ if (run->dst->vb2_buf.timestamp == dpb->reference_ts) { ++ output = position; ++ continue; ++ } ++ + if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) + continue; + +@@ -133,13 +138,11 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, + dpb->top_field_order_cnt, + dpb->bottom_field_order_cnt, + &pic_list[position]); +- +- output = max(position, output); + } + +- position = find_next_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM, +- output); +- if (position >= CEDRUS_H264_FRAME_NUM) ++ if (output >= 0) ++ position = output; ++ else + position = find_first_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM); + + output_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf); +@@ -165,6 +168,10 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, + + #define CEDRUS_MAX_REF_IDX 32 + ++#define REF_IDX(v) (v & GENMASK(5, 0)) ++#define REF_FIELD(v) (v >> 6) ++#define REF_FIELD_BOTTOM 2 ++ + static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, + struct cedrus_run *run, + const u8 *ref_list, u8 num_ref, +@@ -187,7 +194,7 @@ static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, + int buf_idx; + u8 dpb_idx; + +- dpb_idx = ref_list[i]; ++ dpb_idx = REF_IDX(ref_list[i]); + dpb = &decode->dpb[dpb_idx]; + + if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) +@@ -206,7 +213,8 @@ static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, + position = cedrus_buf->codec.h264.position; + + sram_array[i] |= position << 1; +- if (ref_buf->field == V4L2_FIELD_BOTTOM) ++ /* set bottom field flag when reference is to bottom field */ ++ if (REF_FIELD(ref_list[i]) == REF_FIELD_BOTTOM) + sram_array[i] |= BIT(0); + } + +@@ -309,6 +317,8 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, + dma_addr_t src_buf_addr; + u32 offset = slice->header_bit_size; + u32 len = (slice->size * 8) - offset; ++ unsigned int pic_width_in_mbs; ++ bool mbaff_picture; + u32 reg; + + cedrus_write(dev, VE_H264_VLD_LEN, len); +@@ -378,12 +387,19 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, + reg |= VE_H264_SPS_DIRECT_8X8_INFERENCE; + cedrus_write(dev, VE_H264_SPS, reg); + ++ mbaff_picture = !(slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) && ++ (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD); ++ pic_width_in_mbs = sps->pic_width_in_mbs_minus1 + 1; ++ + // slice parameters + reg = 0; ++ reg |= ((slice->first_mb_in_slice % pic_width_in_mbs) & 0xff) << 24; ++ reg |= (((slice->first_mb_in_slice / pic_width_in_mbs) * (mbaff_picture ? 2 : 1)) & 0xff) << 16; + reg |= decode->nal_ref_idc ? BIT(12) : 0; + reg |= (slice->slice_type & 0xf) << 8; + reg |= slice->cabac_init_idc & 0x3; +- reg |= VE_H264_SHS_FIRST_SLICE_IN_PIC; ++ if (decode->num_slices == 1) ++ reg |= VE_H264_SHS_FIRST_SLICE_IN_PIC; + if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) + reg |= VE_H264_SHS_FIELD_PIC; + if (slice->flags & V4L2_H264_SLICE_FLAG_BOTTOM_FIELD) +@@ -531,7 +541,7 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx) + * we need to work on. + */ + field_size = field_size * 2; +- ctx->codec.h264.mv_col_buf_field_size = field_size; ++ ctx->codec.h264.mv_col_buf_field_size = ALIGN(field_size, 1024); + + mv_col_size = field_size * 2 * CEDRUS_H264_FRAME_NUM; + ctx->codec.h264.mv_col_buf_size = mv_col_size; +-- +2.20.1 + diff --git a/projects/Allwinner/patches/linux/0008-HEVC-improvements.patch b/projects/Allwinner/patches/linux/0008-HEVC-improvements.patch new file mode 100644 index 0000000000..38c5f5f04c --- /dev/null +++ b/projects/Allwinner/patches/linux/0008-HEVC-improvements.patch @@ -0,0 +1,703 @@ +diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c +index 3bab9d4e3304..a14762dff91d 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls.c +@@ -916,6 +916,7 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_MPEG_VIDEO_HEVC_SPS: return "HEVC Sequence Parameter Set"; + case V4L2_CID_MPEG_VIDEO_HEVC_PPS: return "HEVC Picture Parameter Set"; + case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: return "HEVC Slice Parameters"; ++ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: return "HEVC Scaling Matrix"; + + /* CAMERA controls */ + /* Keep the order of the 'case's the same as in v4l2-controls.h! */ +@@ -1332,6 +1333,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, + case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: + *type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS; + break; ++ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: ++ *type = V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX; ++ break; + default: + *type = V4L2_CTRL_TYPE_INTEGER; + break; +@@ -1708,6 +1712,7 @@ static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, + case V4L2_CTRL_TYPE_HEVC_SPS: + case V4L2_CTRL_TYPE_HEVC_PPS: + case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: ++ case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: + return 0; + + default: +@@ -2314,6 +2319,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, + case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: + elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params); + break; ++ case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: ++ elem_size = sizeof(struct v4l2_ctrl_hevc_scaling_matrix); ++ break; + default: + if (type < V4L2_CTRL_COMPOUND_TYPES) + elem_size = sizeof(s32); +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c +index a713630ce7ba..3040f483e0a2 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c +@@ -87,6 +87,12 @@ static const struct cedrus_control cedrus_controls[] = { + .codec = CEDRUS_CODEC_H265, + .required = true, + }, ++ { ++ .id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX, ++ .elem_size = sizeof(struct v4l2_ctrl_hevc_scaling_matrix), ++ .codec = CEDRUS_CODEC_H265, ++ .required = true, ++ }, + }; + + #define CEDRUS_CONTROLS_COUNT ARRAY_SIZE(cedrus_controls) +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h +index b5d083812bea..deb9fa1de97c 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h +@@ -72,6 +72,7 @@ struct cedrus_h265_run { + const struct v4l2_ctrl_hevc_sps *sps; + const struct v4l2_ctrl_hevc_pps *pps; + const struct v4l2_ctrl_hevc_slice_params *slice_params; ++ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; + }; + + struct cedrus_run { +@@ -88,6 +89,10 @@ struct cedrus_run { + struct cedrus_buffer { + struct v4l2_m2m_buffer m2m_buf; + ++ void *mv_col_buf; ++ dma_addr_t mv_col_buf_dma; ++ ssize_t mv_col_buf_size; ++ + union { + struct { + unsigned int position; +@@ -121,12 +126,10 @@ struct cedrus_ctx { + dma_addr_t neighbor_info_buf_dma; + } h264; + struct { +- void *mv_col_buf; +- dma_addr_t mv_col_buf_addr; +- ssize_t mv_col_buf_size; +- ssize_t mv_col_buf_unit_size; + void *neighbor_info_buf; + dma_addr_t neighbor_info_buf_addr; ++ void *entry_points_buf; ++ dma_addr_t entry_points_buf_addr; + } h265; + } codec; + }; +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +index c50397f8692f..80c6d920142d 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c +@@ -68,6 +68,8 @@ void cedrus_device_run(void *priv) + V4L2_CID_MPEG_VIDEO_HEVC_PPS); + run.h265.slice_params = cedrus_find_control_data(ctx, + V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS); ++ run.h265.scaling_matrix = cedrus_find_control_data(ctx, ++ V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX); + break; + + default: +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +index f1c3665e95ab..2cc36d69548e 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +@@ -77,24 +77,25 @@ static void cedrus_h265_sram_write_offset(struct cedrus_dev *dev, u32 offset) + cedrus_write(dev, VE_DEC_H265_SRAM_OFFSET, offset); + } + +-static void cedrus_h265_sram_write_data(struct cedrus_dev *dev, void *data, ++static void cedrus_h265_sram_write_data(struct cedrus_dev *dev, const void *data, + unsigned int size) + { +- u32 *word = data; ++ size_t count = DIV_ROUND_UP(size, 4); ++ const u32 *word = data; + +- while (size >= sizeof(u32)) { ++ while (count--) + cedrus_write(dev, VE_DEC_H265_SRAM_DATA, *word++); +- size -= sizeof(u32); +- } + } + + static inline dma_addr_t + cedrus_h265_frame_info_mv_col_buf_addr(struct cedrus_ctx *ctx, +- unsigned int index, unsigned int field) ++ unsigned int index) + { +- return ctx->codec.h265.mv_col_buf_addr + index * +- ctx->codec.h265.mv_col_buf_unit_size + +- field * ctx->codec.h265.mv_col_buf_unit_size / 2; ++ struct cedrus_buffer *cedrus_buf; ++ ++ cedrus_buf = vb2_to_cedrus_buffer(ctx->dst_bufs[index]); ++ ++ return cedrus_buf->mv_col_buf_dma; + } + + static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx, +@@ -107,9 +108,8 @@ static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx, + dma_addr_t dst_luma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 0); + dma_addr_t dst_chroma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 1); + dma_addr_t mv_col_buf_addr[2] = { +- cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, 0), +- cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, +- field_pic ? 1 : 0) ++ cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index), ++ cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index) + }; + u32 offset = VE_DEC_H265_SRAM_OFFSET_FRAME_INFO + + VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT * index; +@@ -157,28 +157,24 @@ static void cedrus_h265_ref_pic_list_write(struct cedrus_dev *dev, + u8 num_ref_idx_active, + u32 sram_offset) + { ++ u8 sram_array[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + unsigned int i; +- u32 word = 0; ++ ++ memset(sram_array, 0, sizeof(sram_array)); ++ num_ref_idx_active = min(num_ref_idx_active, ++ (u8)V4L2_HEVC_DPB_ENTRIES_NUM_MAX); + + cedrus_h265_sram_write_offset(dev, sram_offset); + + for (i = 0; i < num_ref_idx_active; i++) { +- unsigned int shift = (i % 4) * 8; + unsigned int index = list[i]; +- u8 value = list[i]; + ++ sram_array[i] = index; + if (dpb[index].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR) +- value |= VE_DEC_H265_SRAM_REF_PIC_LIST_LT_REF; +- +- /* Each SRAM word gathers up to 4 references. */ +- word |= value << shift; +- +- /* Write the word to SRAM and clear it for the next batch. */ +- if ((i % 4) == 3 || i == (num_ref_idx_active - 1)) { +- cedrus_h265_sram_write_data(dev, &word, sizeof(word)); +- word = 0; +- } ++ sram_array[i] |= VE_DEC_H265_SRAM_REF_PIC_LIST_LT_REF; + } ++ ++ cedrus_h265_sram_write_data(dev, &sram_array, num_ref_idx_active); + } + + static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev, +@@ -219,6 +215,105 @@ static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev, + } + } + ++static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_hevc_scaling_matrix *scaling; ++ struct cedrus_dev *dev = ctx->dev; ++ ++ scaling = run->h265.scaling_matrix; ++ ++ cedrus_write(dev, VE_DEC_H265_SCALING_LIST_DC_COEF0, ++ (scaling->scaling_list_dc_coef_32x32[1] << 24) | ++ (scaling->scaling_list_dc_coef_32x32[0] << 16) | ++ (scaling->scaling_list_dc_coef_16x16[1] << 8) | ++ (scaling->scaling_list_dc_coef_16x16[0] << 0)); ++ ++ cedrus_write(dev, VE_DEC_H265_SCALING_LIST_DC_COEF1, ++ (scaling->scaling_list_dc_coef_16x16[5] << 24) | ++ (scaling->scaling_list_dc_coef_16x16[4] << 16) | ++ (scaling->scaling_list_dc_coef_16x16[3] << 8) | ++ (scaling->scaling_list_dc_coef_16x16[2] << 0)); ++ ++ cedrus_h265_sram_write_offset(dev, VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_8x8); ++ cedrus_h265_sram_write_data(dev, scaling->scaling_list_8x8, ++ sizeof(scaling->scaling_list_8x8)); ++ ++ cedrus_h265_sram_write_offset(dev, VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_32x32); ++ cedrus_h265_sram_write_data(dev, scaling->scaling_list_32x32, ++ sizeof(scaling->scaling_list_32x32)); ++ ++ cedrus_h265_sram_write_offset(dev, VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_16x16); ++ cedrus_h265_sram_write_data(dev, scaling->scaling_list_16x16, ++ sizeof(scaling->scaling_list_16x16)); ++ ++ cedrus_h265_sram_write_offset(dev, VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_4x4); ++ cedrus_h265_sram_write_data(dev, scaling->scaling_list_4x4, ++ sizeof(scaling->scaling_list_4x4)); ++} ++ ++static void write_entry_point_list(struct cedrus_ctx *ctx, ++ struct cedrus_run *run) ++{ ++ const struct v4l2_ctrl_hevc_slice_params *slice_params; ++ unsigned int ctb_size_luma, width_in_ctb_luma; ++ unsigned int log2_max_luma_coding_block_size; ++ const struct v4l2_ctrl_hevc_pps *pps; ++ const struct v4l2_ctrl_hevc_sps *sps; ++ struct cedrus_dev *dev = ctx->dev; ++ uint32_t *entry_points; ++ int i, x, tx, y, ty; ++ ++ pps = run->h265.pps; ++ sps = run->h265.sps; ++ slice_params = run->h265.slice_params; ++ ++ log2_max_luma_coding_block_size = ++ sps->log2_min_luma_coding_block_size_minus3 + 3 + ++ sps->log2_diff_max_min_luma_coding_block_size; ++ ctb_size_luma = 1 << log2_max_luma_coding_block_size; ++ width_in_ctb_luma = DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma); ++ ++ for (x = 0, tx = 0; tx < pps->num_tile_columns_minus1 + 1; tx++) { ++ if (x + pps->column_width_minus1[tx] + 1 > (slice_params->slice_segment_addr % width_in_ctb_luma)) ++ break; ++ ++ x += pps->column_width_minus1[tx] + 1; ++ } ++ ++ for (y = 0, ty = 0; ty < pps->num_tile_rows_minus1 + 1; ty++) { ++ if (y + pps->row_height_minus1[ty] + 1 > (slice_params->slice_segment_addr / width_in_ctb_luma)) ++ break; ++ ++ y += pps->row_height_minus1[ty] + 1; ++ } ++ ++ cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, (y << 16) | (x << 0)); ++ cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, ++ ((y + pps->row_height_minus1[ty]) << 16) | ++ ((x + pps->column_width_minus1[tx]) << 0)); ++ ++ entry_points = ctx->codec.h265.entry_points_buf; ++ if (pps->entropy_coding_sync_enabled_flag) { ++ for (i = 0; i < slice_params->num_entry_point_offsets; i++) ++ entry_points[i] = slice_params->entry_point_offset_minus1[i] + 1; ++ } else { ++ for (i = 0; i < slice_params->num_entry_point_offsets; i++) { ++ if (tx + 1 >= pps->num_tile_columns_minus1 + 1) { ++ x = tx = 0; ++ y += pps->row_height_minus1[ty++] + 1; ++ } else { ++ x += pps->column_width_minus1[tx++] + 1; ++ } ++ ++ entry_points[i * 4 + 0] = slice_params->entry_point_offset_minus1[i] + 1; ++ entry_points[i * 4 + 1] = 0x0; ++ entry_points[i * 4 + 2] = (y << 16) | (x << 0); ++ entry_points[i * 4 + 3] = ((y + pps->row_height_minus1[ty]) << 16) | ((x + pps->column_width_minus1[tx]) << 0); ++ } ++ } ++} ++ + static void cedrus_h265_setup(struct cedrus_ctx *ctx, + struct cedrus_run *run) + { +@@ -227,6 +322,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + const struct v4l2_ctrl_hevc_pps *pps; + const struct v4l2_ctrl_hevc_slice_params *slice_params; + const struct v4l2_hevc_pred_weight_table *pred_weight_table; ++ struct cedrus_buffer *cedrus_buf; + dma_addr_t src_buf_addr; + dma_addr_t src_buf_end_addr; + u32 chroma_log2_weight_denom; +@@ -239,43 +335,10 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + slice_params = run->h265.slice_params; + pred_weight_table = &slice_params->pred_weight_table; + +- /* MV column buffer size and allocation. */ +- if (!ctx->codec.h265.mv_col_buf_size) { +- unsigned int num_buffers = +- run->dst->vb2_buf.vb2_queue->num_buffers; +- unsigned int log2_max_luma_coding_block_size = +- sps->log2_min_luma_coding_block_size_minus3 + 3 + +- sps->log2_diff_max_min_luma_coding_block_size; +- unsigned int ctb_size_luma = +- 1 << log2_max_luma_coding_block_size; +- +- /* +- * Each CTB requires a MV col buffer with a specific unit size. +- * Since the address is given with missing lsb bits, 1 KiB is +- * added to each buffer to ensure proper alignment. +- */ +- ctx->codec.h265.mv_col_buf_unit_size = +- DIV_ROUND_UP(ctx->src_fmt.width, ctb_size_luma) * +- DIV_ROUND_UP(ctx->src_fmt.height, ctb_size_luma) * +- CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE + SZ_1K; +- +- ctx->codec.h265.mv_col_buf_size = num_buffers * +- ctx->codec.h265.mv_col_buf_unit_size; +- +- ctx->codec.h265.mv_col_buf = +- dma_alloc_coherent(dev->dev, +- ctx->codec.h265.mv_col_buf_size, +- &ctx->codec.h265.mv_col_buf_addr, +- GFP_KERNEL); +- if (!ctx->codec.h265.mv_col_buf) { +- ctx->codec.h265.mv_col_buf_size = 0; +- // TODO: Abort the process here. +- return; +- } +- } +- + /* Activate H265 engine. */ + cedrus_engine_enable(dev, CEDRUS_CODEC_H265); ++ if (sps->pic_width_in_luma_samples > 2048) ++ cedrus_write(dev, VE_MODE, cedrus_read(dev, VE_MODE) | BIT(21)); + + /* Source offset and length in bits. */ + +@@ -299,18 +362,35 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + src_buf_end_addr = src_buf_addr + + DIV_ROUND_UP(slice_params->bit_size, 8); + +- reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_end_addr); ++ reg = VE_DEC_H265_BITS_END_ADDR_BASE(ALIGN(src_buf_end_addr, 1024) - 1); + cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg); + +- /* Coding tree block address: start at the beginning. */ +- reg = VE_DEC_H265_DEC_CTB_ADDR_X(0) | VE_DEC_H265_DEC_CTB_ADDR_Y(0); +- cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg); +- + cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0); + cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0); + ++ if (pps->tiles_enabled_flag || pps->entropy_coding_sync_enabled_flag) ++ write_entry_point_list(ctx, run); ++ ++ /* Coding tree block address */ ++ reg = 0; ++ if (!slice_params->first_slice_segment_in_pic_flag) { ++ unsigned int ctb_size_luma, width_in_ctb_luma; ++ unsigned int log2_max_luma_coding_block_size; ++ ++ log2_max_luma_coding_block_size = ++ sps->log2_min_luma_coding_block_size_minus3 + 3 + ++ sps->log2_diff_max_min_luma_coding_block_size; ++ ctb_size_luma = 1 << log2_max_luma_coding_block_size; ++ width_in_ctb_luma = DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma); ++ ++ reg = VE_DEC_H265_DEC_CTB_ADDR_X(slice_params->slice_segment_addr % width_in_ctb_luma); ++ reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(slice_params->slice_segment_addr / width_in_ctb_luma); ++ } ++ cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg); ++ + /* Clear the number of correctly-decoded coding tree blocks. */ +- cedrus_write(dev, VE_DEC_H265_DEC_CTB_NUM, 0); ++ if (slice_params->first_slice_segment_in_pic_flag) ++ cedrus_write(dev, VE_DEC_H265_DEC_CTB_NUM, 0); + + /* Initialize bitstream access. */ + cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC); +@@ -333,6 +413,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_luma_coding_block_size) | + VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_luma_coding_block_size_minus3) | + VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(sps->bit_depth_chroma_minus8) | ++ VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_LUMA_MINUS8(sps->bit_depth_luma_minus8) | + VE_DEC_H265_DEC_SPS_HDR_SEPARATE_COLOUR_PLANE_FLAG(sps->separate_colour_plane_flag) | + VE_DEC_H265_DEC_SPS_HDR_CHROMA_FORMAT_IDC(sps->chroma_format_idc); + +@@ -362,7 +443,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + VE_DEC_H265_DEC_PPS_CTRL1_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG(pps->pps_loop_filter_across_slices_enabled_flag) | + VE_DEC_H265_DEC_PPS_CTRL1_LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG(pps->loop_filter_across_tiles_enabled_flag) | + VE_DEC_H265_DEC_PPS_CTRL1_ENTROPY_CODING_SYNC_ENABLED_FLAG(pps->entropy_coding_sync_enabled_flag) | +- VE_DEC_H265_DEC_PPS_CTRL1_TILES_ENABLED_FLAG(0) | ++ VE_DEC_H265_DEC_PPS_CTRL1_TILES_ENABLED_FLAG(pps->tiles_enabled_flag) | + VE_DEC_H265_DEC_PPS_CTRL1_TRANSQUANT_BYPASS_ENABLE_FLAG(pps->transquant_bypass_enabled_flag) | + VE_DEC_H265_DEC_PPS_CTRL1_WEIGHTED_BIPRED_FLAG(pps->weighted_bipred_flag) | + VE_DEC_H265_DEC_PPS_CTRL1_WEIGHTED_PRED_FLAG(pps->weighted_pred_flag); +@@ -383,7 +464,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(slice_params->colour_plane_id) | + VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TYPE(slice_params->slice_type) | + VE_DEC_H265_DEC_SLICE_HDR_INFO0_DEPENDENT_SLICE_SEGMENT_FLAG(pps->dependent_slice_segment_flag) | +- VE_DEC_H265_DEC_SLICE_HDR_INFO0_FIRST_SLICE_SEGMENT_IN_PIC_FLAG(1); ++ VE_DEC_H265_DEC_SLICE_HDR_INFO0_FIRST_SLICE_SEGMENT_IN_PIC_FLAG(slice_params->first_slice_segment_in_pic_flag); + + cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO0, reg); + +@@ -400,34 +481,68 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + + chroma_log2_weight_denom = pred_weight_table->luma_log2_weight_denom + + pred_weight_table->delta_chroma_log2_weight_denom; +- reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(0) | ++ reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(slice_params->num_entry_point_offsets) | + VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(chroma_log2_weight_denom) | + VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(pred_weight_table->luma_log2_weight_denom); + + cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO2, reg); + ++ cedrus_write(dev, VE_DEC_H265_ENTRY_POINT_OFFSET_ADDR, ctx->codec.h265.entry_points_buf_addr >> 8); ++ + /* Decoded picture size. */ + +- reg = VE_DEC_H265_DEC_PIC_SIZE_WIDTH(ctx->src_fmt.width) | +- VE_DEC_H265_DEC_PIC_SIZE_HEIGHT(ctx->src_fmt.height); ++ reg = VE_DEC_H265_DEC_PIC_SIZE_WIDTH(sps->pic_width_in_luma_samples) | ++ VE_DEC_H265_DEC_PIC_SIZE_HEIGHT(sps->pic_height_in_luma_samples); + + cedrus_write(dev, VE_DEC_H265_DEC_PIC_SIZE, reg); + +- /* Scaling list. */ ++ /* Scaling list */ + +- reg = VE_DEC_H265_SCALING_LIST_CTRL0_DEFAULT; ++ if (sps->scaling_list_enabled_flag) { ++ cedrus_h265_write_scaling_list(ctx, run); ++ reg = VE_DEC_H265_SCALING_LIST_CTRL0_ENABLED_FLAG(1); ++ } else { ++ reg = VE_DEC_H265_SCALING_LIST_CTRL0_DEFAULT; ++ } + cedrus_write(dev, VE_DEC_H265_SCALING_LIST_CTRL0, reg); + + /* Neightbor information address. */ + reg = VE_DEC_H265_NEIGHBOR_INFO_ADDR_BASE(ctx->codec.h265.neighbor_info_buf_addr); + cedrus_write(dev, VE_DEC_H265_NEIGHBOR_INFO_ADDR, reg); + ++ cedrus_write(dev, VE_DEC_H265_LOW_ADDR, 0); ++ + /* Write decoded picture buffer in pic list. */ + cedrus_h265_frame_info_write_dpb(ctx, slice_params->dpb, + slice_params->num_active_dpb_entries); + + /* Output frame. */ + ++ cedrus_buf = vb2_to_cedrus_buffer(ctx->dst_bufs[run->dst->vb2_buf.index]); ++ if (!cedrus_buf->mv_col_buf_size) { ++ unsigned int ctb_size_luma, width_in_ctb_luma; ++ unsigned int log2_max_luma_coding_block_size; ++ ++ log2_max_luma_coding_block_size = ++ sps->log2_min_luma_coding_block_size_minus3 + 3 + ++ sps->log2_diff_max_min_luma_coding_block_size; ++ ctb_size_luma = 1 << log2_max_luma_coding_block_size; ++ width_in_ctb_luma = DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma); ++ ++ cedrus_buf->mv_col_buf_size = ALIGN(width_in_ctb_luma * ++ DIV_ROUND_UP(sps->pic_height_in_luma_samples, ctb_size_luma) * ++ CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE, 1024); ++ ++ cedrus_buf->mv_col_buf = ++ dma_alloc_coherent(dev->dev, ++ cedrus_buf->mv_col_buf_size, ++ &cedrus_buf->mv_col_buf_dma, ++ GFP_KERNEL); ++ ++ if (!cedrus_buf->mv_col_buf) ++ cedrus_buf->mv_col_buf_size = 0; ++ } ++ + output_pic_list_index = V4L2_HEVC_DPB_ENTRIES_NUM_MAX; + pic_order_cnt[0] = slice_params->slice_pic_order_cnt; + pic_order_cnt[1] = slice_params->slice_pic_order_cnt; +@@ -443,36 +558,36 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + if (slice_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { + cedrus_h265_ref_pic_list_write(dev, slice_params->dpb, + slice_params->ref_idx_l0, +- slice_params->num_ref_idx_l0_active_minus1 + 1, +- VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0); ++ slice_params->num_ref_idx_l0_active_minus1 + 1, ++ VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0); + + if (pps->weighted_pred_flag || pps->weighted_bipred_flag) + cedrus_h265_pred_weight_write(dev, +- pred_weight_table->delta_luma_weight_l0, +- pred_weight_table->luma_offset_l0, +- pred_weight_table->delta_chroma_weight_l0, +- pred_weight_table->chroma_offset_l0, +- slice_params->num_ref_idx_l0_active_minus1 + 1, +- VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0, +- VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0); ++ pred_weight_table->delta_luma_weight_l0, ++ pred_weight_table->luma_offset_l0, ++ pred_weight_table->delta_chroma_weight_l0, ++ pred_weight_table->chroma_offset_l0, ++ slice_params->num_ref_idx_l0_active_minus1 + 1, ++ VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0, ++ VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0); + } + + /* Reference picture list 1 (for B frames). */ + if (slice_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) { + cedrus_h265_ref_pic_list_write(dev, slice_params->dpb, + slice_params->ref_idx_l1, +- slice_params->num_ref_idx_l1_active_minus1 + 1, +- VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1); ++ slice_params->num_ref_idx_l1_active_minus1 + 1, ++ VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1); + + if (pps->weighted_bipred_flag) + cedrus_h265_pred_weight_write(dev, +- pred_weight_table->delta_luma_weight_l1, +- pred_weight_table->luma_offset_l1, +- pred_weight_table->delta_chroma_weight_l1, +- pred_weight_table->chroma_offset_l1, +- slice_params->num_ref_idx_l1_active_minus1 + 1, +- VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1, +- VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1); ++ pred_weight_table->delta_luma_weight_l1, ++ pred_weight_table->luma_offset_l1, ++ pred_weight_table->delta_chroma_weight_l1, ++ pred_weight_table->chroma_offset_l1, ++ slice_params->num_ref_idx_l1_active_minus1 + 1, ++ VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1, ++ VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1); + } + + /* Enable appropriate interruptions. */ +@@ -483,9 +598,6 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx) + { + struct cedrus_dev *dev = ctx->dev; + +- /* The buffer size is calculated at setup time. */ +- ctx->codec.h265.mv_col_buf_size = 0; +- + ctx->codec.h265.neighbor_info_buf = + dma_alloc_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, + &ctx->codec.h265.neighbor_info_buf_addr, +@@ -493,6 +605,17 @@ static int cedrus_h265_start(struct cedrus_ctx *ctx) + if (!ctx->codec.h265.neighbor_info_buf) + return -ENOMEM; + ++ ctx->codec.h265.entry_points_buf = ++ dma_alloc_coherent(dev->dev, CEDRUS_H265_ENTRY_POINTS_BUF_SIZE, ++ &ctx->codec.h265.entry_points_buf_addr, ++ GFP_KERNEL); ++ if (!ctx->codec.h265.entry_points_buf) { ++ dma_free_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, ++ ctx->codec.h265.neighbor_info_buf, ++ ctx->codec.h265.neighbor_info_buf_addr); ++ return -ENOMEM; ++ } ++ + return 0; + } + +@@ -500,17 +623,12 @@ static void cedrus_h265_stop(struct cedrus_ctx *ctx) + { + struct cedrus_dev *dev = ctx->dev; + +- if (ctx->codec.h265.mv_col_buf_size > 0) { +- dma_free_coherent(dev->dev, ctx->codec.h265.mv_col_buf_size, +- ctx->codec.h265.mv_col_buf, +- ctx->codec.h265.mv_col_buf_addr); +- +- ctx->codec.h265.mv_col_buf_size = 0; +- } +- + dma_free_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, + ctx->codec.h265.neighbor_info_buf, + ctx->codec.h265.neighbor_info_buf_addr); ++ dma_free_coherent(dev->dev, CEDRUS_H265_ENTRY_POINTS_BUF_SIZE, ++ ctx->codec.h265.entry_points_buf, ++ ctx->codec.h265.entry_points_buf_addr); + } + + static void cedrus_h265_trigger(struct cedrus_ctx *ctx) +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +index 87651d6b6227..a2931f322c7a 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +@@ -496,6 +496,9 @@ + #define VE_DEC_H265_TILE_START_CTB (VE_ENGINE_DEC_H265 + 0x68) + #define VE_DEC_H265_TILE_END_CTB (VE_ENGINE_DEC_H265 + 0x6c) + ++#define VE_DEC_H265_SCALING_LIST_DC_COEF0 (VE_ENGINE_DEC_H265 + 0x78) ++#define VE_DEC_H265_SCALING_LIST_DC_COEF1 (VE_ENGINE_DEC_H265 + 0x7c) ++ + #define VE_DEC_H265_LOW_ADDR (VE_ENGINE_DEC_H265 + 0x80) + + #define VE_DEC_H265_LOW_ADDR_PRIMARY_CHROMA(a) \ +@@ -513,7 +516,10 @@ + #define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1 0x80 + #define VE_DEC_H265_SRAM_OFFSET_FRAME_INFO 0x400 + #define VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT 0x20 +-#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS 0x800 ++#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_8x8 0x800 ++#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_32x32 0x980 ++#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_16x16 0xa00 ++#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS_4x4 0xb80 + #define VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0 0xc00 + #define VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1 0xc10 + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +index b9acdc03c839..adf00513c15f 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +@@ -423,8 +423,18 @@ static void cedrus_buf_cleanup(struct vb2_buffer *vb) + struct vb2_queue *vq = vb->vb2_queue; + struct cedrus_ctx *ctx = vb2_get_drv_priv(vq); + +- if (!V4L2_TYPE_IS_OUTPUT(vq->type)) ++ if (!V4L2_TYPE_IS_OUTPUT(vq->type)) { ++ struct cedrus_buffer *cedrus_buf; ++ ++ cedrus_buf = vb2_to_cedrus_buffer(ctx->dst_bufs[vb->index]); ++ ++ if (cedrus_buf->mv_col_buf_size) ++ dma_free_coherent(ctx->dev->dev, ++ cedrus_buf->mv_col_buf_size, ++ cedrus_buf->mv_col_buf, ++ cedrus_buf->mv_col_buf_dma); + ctx->dst_bufs[vb->index] = NULL; ++ } + } + + static int cedrus_buf_out_validate(struct vb2_buffer *vb) +diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h +index 005c71c67163..4bf3d79047f4 100644 +--- a/include/media/hevc-ctrls.h ++++ b/include/media/hevc-ctrls.h +@@ -14,11 +14,13 @@ + #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_MPEG_BASE + 645) + #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_MPEG_BASE + 646) + #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_MPEG_BASE + 647) ++#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_MPEG_BASE + 648) + + /* enum v4l2_ctrl_type type values */ + #define V4L2_CTRL_TYPE_HEVC_SPS 0x0115 + #define V4L2_CTRL_TYPE_HEVC_PPS 0x0116 + #define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0117 ++#define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0118 + + #define V4L2_HEVC_SLICE_TYPE_B 0 + #define V4L2_HEVC_SLICE_TYPE_P 1 +@@ -91,7 +93,7 @@ struct v4l2_ctrl_hevc_pps { + __u8 lists_modification_present_flag; + __u8 log2_parallel_merge_level_minus2; + __u8 slice_segment_header_extension_present_flag; +- __u8 padding; ++ __u8 scaling_list_enable_flag; + }; + + #define V4L2_HEVC_DPB_ENTRY_RPS_ST_CURR_BEFORE 0x01 +@@ -175,7 +177,21 @@ struct v4l2_ctrl_hevc_slice_params { + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ + struct v4l2_hevc_pred_weight_table pred_weight_table; + +- __u8 padding[2]; ++ __u32 slice_segment_addr; ++ __u32 num_entry_point_offsets; ++ __u32 entry_point_offset_minus1[256]; ++ __u8 first_slice_segment_in_pic_flag; ++ ++ __u8 padding; ++}; ++ ++struct v4l2_ctrl_hevc_scaling_matrix { ++ __u8 scaling_list_4x4[6][16]; ++ __u8 scaling_list_8x8[6][64]; ++ __u8 scaling_list_16x16[6][64]; ++ __u8 scaling_list_32x32[2][64]; ++ __u8 scaling_list_dc_coef_16x16[6]; ++ __u8 scaling_list_dc_coef_32x32[2]; + }; + + #endif diff --git a/projects/Allwinner/patches/linux/0009-cedrus-h264-4k.patch b/projects/Allwinner/patches/linux/0009-cedrus-h264-4k.patch new file mode 100644 index 0000000000..40849ac4ab --- /dev/null +++ b/projects/Allwinner/patches/linux/0009-cedrus-h264-4k.patch @@ -0,0 +1,358 @@ +From bd5fed9f390fea4ef8df1abb5f4ac6b64fab5974 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Mon, 18 Feb 2019 21:51:31 +0100 +Subject: [PATCH] cedrus h264 4k + +Signed-off-by: Jernej Skrabec +--- + drivers/staging/media/sunxi/cedrus/cedrus.h | 12 +- + .../staging/media/sunxi/cedrus/cedrus_h264.c | 117 +++++++++++------- + .../staging/media/sunxi/cedrus/cedrus_h265.c | 4 +- + .../staging/media/sunxi/cedrus/cedrus_hw.c | 11 +- + .../staging/media/sunxi/cedrus/cedrus_hw.h | 3 +- + .../staging/media/sunxi/cedrus/cedrus_mpeg2.c | 2 +- + .../staging/media/sunxi/cedrus/cedrus_regs.h | 4 + + .../staging/media/sunxi/cedrus/cedrus_video.c | 4 +- + 8 files changed, 98 insertions(+), 59 deletions(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h +index deb9fa1de97c..8815332fe1c1 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h +@@ -116,14 +116,18 @@ struct cedrus_ctx { + + union { + struct { +- void *mv_col_buf; +- dma_addr_t mv_col_buf_dma; +- ssize_t mv_col_buf_field_size; +- ssize_t mv_col_buf_size; + void *pic_info_buf; + dma_addr_t pic_info_buf_dma; + void *neighbor_info_buf; + dma_addr_t neighbor_info_buf_dma; ++ ++ void *deblk_buf; ++ dma_addr_t deblk_buf_dma; ++ ssize_t deblk_buf_size; ++ ++ void *intra_pred_buf; ++ dma_addr_t intra_pred_buf_dma; ++ ssize_t intra_pred_buf_size; + } h264; + struct { + void *neighbor_info_buf; +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +index 405545947b85..737a317fd1ee 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_h264.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h264.c +@@ -55,16 +55,14 @@ static void cedrus_h264_write_sram(struct cedrus_dev *dev, + } + + static dma_addr_t cedrus_h264_mv_col_buf_addr(struct cedrus_ctx *ctx, +- unsigned int position, ++ struct cedrus_buffer *buf, + unsigned int field) + { +- dma_addr_t addr = ctx->codec.h264.mv_col_buf_dma; +- +- /* Adjust for the position */ +- addr += position * ctx->codec.h264.mv_col_buf_field_size * 2; ++ dma_addr_t addr = buf->mv_col_buf_dma; + + /* Adjust for the field */ +- addr += field * ctx->codec.h264.mv_col_buf_field_size; ++ if (field) ++ addr += buf->mv_col_buf_size / 2; + + return addr; + } +@@ -76,7 +74,6 @@ static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx, + struct cedrus_h264_sram_ref_pic *pic) + { + struct vb2_buffer *vbuf = &buf->m2m_buf.vb.vb2_buf; +- unsigned int position = buf->codec.h264.position; + + pic->top_field_order_cnt = top_field_order_cnt; + pic->bottom_field_order_cnt = bottom_field_order_cnt; +@@ -84,8 +81,8 @@ static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx, + + pic->luma_ptr = cedrus_buf_addr(vbuf, &ctx->dst_fmt, 0); + pic->chroma_ptr = cedrus_buf_addr(vbuf, &ctx->dst_fmt, 1); +- pic->mv_col_top_ptr = cedrus_h264_mv_col_buf_addr(ctx, position, 0); +- pic->mv_col_bot_ptr = cedrus_h264_mv_col_buf_addr(ctx, position, 1); ++ pic->mv_col_top_ptr = cedrus_h264_mv_col_buf_addr(ctx, buf, 0); ++ pic->mv_col_bot_ptr = cedrus_h264_mv_col_buf_addr(ctx, buf, 1); + } + + static void cedrus_write_frame_list(struct cedrus_ctx *ctx, +@@ -148,6 +145,28 @@ static void cedrus_write_frame_list(struct cedrus_ctx *ctx, + output_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf); + output_buf->codec.h264.position = position; + ++ if (!output_buf->mv_col_buf_size) { ++ const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; ++ unsigned int field_size; ++ ++ field_size = DIV_ROUND_UP(ctx->src_fmt.width, 16) * ++ DIV_ROUND_UP(ctx->src_fmt.height, 16) * 16; ++ if (!(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE)) ++ field_size = field_size * 2; ++ if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)) ++ field_size = field_size * 2; ++ ++ output_buf->mv_col_buf_size = ALIGN(field_size, 1024) * 2; ++ output_buf->mv_col_buf = ++ dma_alloc_coherent(dev->dev, ++ output_buf->mv_col_buf_size, ++ &output_buf->mv_col_buf_dma, ++ GFP_KERNEL); ++ ++ if (!output_buf->mv_col_buf) ++ output_buf->mv_col_buf_size = 0; ++ } ++ + if (slice->flags & V4L2_H264_SLICE_FLAG_FIELD_PIC) + output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FIELD; + else if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) +@@ -331,6 +350,14 @@ static void cedrus_set_params(struct cedrus_ctx *ctx, + VE_H264_VLD_ADDR_FIRST | VE_H264_VLD_ADDR_VALID | + VE_H264_VLD_ADDR_LAST); + ++ if (((sps->pic_width_in_mbs_minus1 + 1) * 16) > 2048) { ++ cedrus_write(dev, VE_DBLK_INTRAPRED_BUF_CTRL, 0x5); ++ cedrus_write(dev, VE_DBLK_DRAM_BUF_ADDR, ++ ctx->codec.h264.deblk_buf_dma); ++ cedrus_write(dev, VE_INTRAPRED_DRAM_BUF_ADDR, ++ ctx->codec.h264.intra_pred_buf_dma); ++ } ++ + /* + * FIXME: Since the bitstream parsing is done in software, and + * in userspace, this shouldn't be needed anymore. But it +@@ -471,7 +498,8 @@ static void cedrus_h264_setup(struct cedrus_ctx *ctx, + { + struct cedrus_dev *dev = ctx->dev; + +- cedrus_engine_enable(dev, CEDRUS_CODEC_H264); ++ cedrus_engine_enable(dev, CEDRUS_CODEC_H264, ++ ctx->src_fmt.width); + + cedrus_write(dev, VE_H264_SDROT_CTRL, 0); + cedrus_write(dev, VE_H264_EXTRA_BUFFER1, +@@ -490,8 +518,6 @@ static void cedrus_h264_setup(struct cedrus_ctx *ctx, + static int cedrus_h264_start(struct cedrus_ctx *ctx) + { + struct cedrus_dev *dev = ctx->dev; +- unsigned int field_size; +- unsigned int mv_col_size; + int ret; + + /* +@@ -523,44 +549,42 @@ static int cedrus_h264_start(struct cedrus_ctx *ctx) + goto err_pic_buf; + } + +- field_size = DIV_ROUND_UP(ctx->src_fmt.width, 16) * +- DIV_ROUND_UP(ctx->src_fmt.height, 16) * 16; +- +- /* +- * FIXME: This is actually conditional to +- * V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE not being set, we +- * might have to rework this if memory efficiency ever is +- * something we need to work on. +- */ +- field_size = field_size * 2; ++ if (ctx->src_fmt.width > 2048) { ++ ctx->codec.h264.deblk_buf_size = ++ ALIGN(ctx->src_fmt.width, 32) * 12; ++ ctx->codec.h264.deblk_buf = ++ dma_alloc_coherent(dev->dev, ++ ctx->codec.h264.deblk_buf_size, ++ &ctx->codec.h264.deblk_buf_dma, ++ GFP_KERNEL); ++ if (!ctx->codec.h264.deblk_buf) { ++ ret = -ENOMEM; ++ goto err_neighbor_buf; ++ } + +- /* +- * FIXME: This is actually conditional to +- * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY not being set, we might +- * have to rework this if memory efficiency ever is something +- * we need to work on. +- */ +- field_size = field_size * 2; +- ctx->codec.h264.mv_col_buf_field_size = ALIGN(field_size, 1024); +- +- mv_col_size = field_size * 2 * CEDRUS_H264_FRAME_NUM; +- ctx->codec.h264.mv_col_buf_size = mv_col_size; +- ctx->codec.h264.mv_col_buf = dma_alloc_coherent(dev->dev, +- ctx->codec.h264.mv_col_buf_size, +- &ctx->codec.h264.mv_col_buf_dma, +- GFP_KERNEL); +- if (!ctx->codec.h264.mv_col_buf) { +- ret = -ENOMEM; +- goto err_neighbor_buf; ++ ctx->codec.h264.intra_pred_buf_size = ++ ALIGN(ctx->src_fmt.width, 64) * 5; ++ ctx->codec.h264.intra_pred_buf = ++ dma_alloc_coherent(dev->dev, ++ ctx->codec.h264.intra_pred_buf_size, ++ &ctx->codec.h264.intra_pred_buf_dma, ++ GFP_KERNEL); ++ if (!ctx->codec.h264.intra_pred_buf) { ++ ret = -ENOMEM; ++ goto err_deblk_buf; ++ } + } + + return 0; + ++err_deblk_buf: ++ dma_free_coherent(dev->dev, ctx->codec.h264.deblk_buf_size, ++ ctx->codec.h264.deblk_buf, ++ ctx->codec.h264.deblk_buf_dma); + err_neighbor_buf: + dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, + ctx->codec.h264.neighbor_info_buf, + ctx->codec.h264.neighbor_info_buf_dma); +- + err_pic_buf: + dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, + ctx->codec.h264.pic_info_buf, +@@ -572,15 +596,20 @@ static void cedrus_h264_stop(struct cedrus_ctx *ctx) + { + struct cedrus_dev *dev = ctx->dev; + +- dma_free_coherent(dev->dev, ctx->codec.h264.mv_col_buf_size, +- ctx->codec.h264.mv_col_buf, +- ctx->codec.h264.mv_col_buf_dma); + dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, + ctx->codec.h264.neighbor_info_buf, + ctx->codec.h264.neighbor_info_buf_dma); + dma_free_coherent(dev->dev, CEDRUS_PIC_INFO_BUF_SIZE, + ctx->codec.h264.pic_info_buf, + ctx->codec.h264.pic_info_buf_dma); ++ if (ctx->codec.h264.deblk_buf_size) ++ dma_free_coherent(dev->dev, ctx->codec.h264.deblk_buf_size, ++ ctx->codec.h264.deblk_buf, ++ ctx->codec.h264.deblk_buf_dma); ++ if (ctx->codec.h264.intra_pred_buf_size) ++ dma_free_coherent(dev->dev, ctx->codec.h264.intra_pred_buf_size, ++ ctx->codec.h264.intra_pred_buf, ++ ctx->codec.h264.intra_pred_buf_dma); + } + + static void cedrus_h264_trigger(struct cedrus_ctx *ctx) +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +index 2cc36d69548e..246d747d3fa9 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c +@@ -336,9 +336,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx, + pred_weight_table = &slice_params->pred_weight_table; + + /* Activate H265 engine. */ +- cedrus_engine_enable(dev, CEDRUS_CODEC_H265); +- if (sps->pic_width_in_luma_samples > 2048) +- cedrus_write(dev, VE_MODE, cedrus_read(dev, VE_MODE) | BIT(21)); ++ cedrus_engine_enable(dev, CEDRUS_CODEC_H265, ctx->src_fmt.width); + + /* Source offset and length in bits. */ + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +index 6be604c52d5c..4b6c69010e39 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +@@ -30,7 +30,8 @@ + #include "cedrus_hw.h" + #include "cedrus_regs.h" + +-int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) ++int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec, ++ unsigned int width) + { + u32 reg = 0; + +@@ -58,6 +59,11 @@ int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) + return -EINVAL; + } + ++ if (width >= 4096) ++ reg |= BIT(22); ++ if (width > 2048) ++ reg |= BIT(21); ++ + cedrus_write(dev, VE_MODE, reg); + + return 0; +@@ -83,9 +89,6 @@ void cedrus_dst_format_set(struct cedrus_dev *dev, + reg = VE_PRIMARY_OUT_FMT_NV12; + cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg); + +- reg = VE_CHROMA_BUF_LEN_SDRT(chroma_size / 2); +- cedrus_write(dev, VE_CHROMA_BUF_LEN, reg); +- + reg = chroma_size / 2; + cedrus_write(dev, VE_PRIMARY_CHROMA_BUF_LEN, reg); + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h +index b43c77d54b95..40b44722b7c0 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h +@@ -18,7 +18,8 @@ + + #define CEDRUS_CLOCK_RATE_DEFAULT 320000000 + +-int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec); ++int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec, ++ unsigned int width); + void cedrus_engine_disable(struct cedrus_dev *dev); + + void cedrus_dst_format_set(struct cedrus_dev *dev, +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c b/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c +index cb45fda9aaeb..2f6384ca385d 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_mpeg2.c +@@ -96,7 +96,7 @@ static void cedrus_mpeg2_setup(struct cedrus_ctx *ctx, struct cedrus_run *run) + quantization = run->mpeg2.quantization; + + /* Activate MPEG engine. */ +- cedrus_engine_enable(dev, CEDRUS_CODEC_MPEG2); ++ cedrus_engine_enable(dev, CEDRUS_CODEC_MPEG2, ctx->src_fmt.width); + + /* Set intra quantization matrix. */ + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +index a2931f322c7a..df000b7c99be 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h +@@ -41,6 +41,10 @@ + #define VE_MODE_DEC_H264 (0x01 << 0) + #define VE_MODE_DEC_MPEG (0x00 << 0) + ++#define VE_DBLK_INTRAPRED_BUF_CTRL 0x50 ++#define VE_DBLK_DRAM_BUF_ADDR 0x54 ++#define VE_INTRAPRED_DRAM_BUF_ADDR 0x58 ++ + #define VE_PRIMARY_CHROMA_BUF_LEN 0xc4 + #define VE_PRIMARY_FB_LINE_STRIDE 0xc8 + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +index adf00513c15f..b24317b26fd2 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c +@@ -29,8 +29,8 @@ + + #define CEDRUS_MIN_WIDTH 16U + #define CEDRUS_MIN_HEIGHT 16U +-#define CEDRUS_MAX_WIDTH 3840U +-#define CEDRUS_MAX_HEIGHT 2160U ++#define CEDRUS_MAX_WIDTH 4096U ++#define CEDRUS_MAX_HEIGHT 2768U + + static struct cedrus_format cedrus_formats[] = { + { +-- +2.20.1 + diff --git a/projects/Allwinner/patches/linux/0010-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch b/projects/Allwinner/patches/linux/0010-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch new file mode 100644 index 0000000000..4ce824a326 --- /dev/null +++ b/projects/Allwinner/patches/linux/0010-WIP-dw-hdmi-cec-sleep-100ms-on-error.patch @@ -0,0 +1,62 @@ +From 9ce5c66f0f98cc968598307f7f7feb39a83d7342 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Tue, 26 Feb 2019 20:45:14 +0000 +Subject: [PATCH] WIP: dw-hdmi-cec: sleep 100ms on error + +--- + drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c | 18 ++++++++++++++++-- + 1 file changed, 16 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c +index 6c323510f128..b5a1a85c8700 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.c +@@ -7,6 +7,7 @@ + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ ++#include + #include + #include + #include +@@ -132,8 +133,15 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data) + + dw_hdmi_write(cec, stat, HDMI_IH_CEC_STAT0); + +- if (stat & CEC_STAT_ERROR_INIT) { +- cec->tx_status = CEC_TX_STATUS_ERROR; ++ /* Status with both done and error_initiator bits have been seen ++ * on Rockchip RK3328 devices, transmit attempt seems to have failed ++ * when this happens, report as low drive and block cec-framework ++ * 100ms before core retransmits the failed message, this seems to ++ * mitigate the issue with failed transmit attempts. ++ */ ++ if ((stat & (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) == (CEC_STAT_DONE|CEC_STAT_ERROR_INIT)) { ++ pr_info("dw_hdmi_cec_hardirq: stat=%02x LOW_DRIVE\n", stat); ++ cec->tx_status = CEC_TX_STATUS_LOW_DRIVE; + cec->tx_done = true; + ret = IRQ_WAKE_THREAD; + } else if (stat & CEC_STAT_DONE) { +@@ -144,6 +152,10 @@ static irqreturn_t dw_hdmi_cec_hardirq(int irq, void *data) + cec->tx_status = CEC_TX_STATUS_NACK; + cec->tx_done = true; + ret = IRQ_WAKE_THREAD; ++ } else if (stat & CEC_STAT_ERROR_INIT) { ++ cec->tx_status = CEC_TX_STATUS_ERROR; ++ cec->tx_done = true; ++ ret = IRQ_WAKE_THREAD; + } + + if (stat & CEC_STAT_EOM) { +@@ -176,6 +188,8 @@ static irqreturn_t dw_hdmi_cec_thread(int irq, void *data) + + if (cec->tx_done) { + cec->tx_done = false; ++ if (cec->tx_status == CEC_TX_STATUS_LOW_DRIVE) ++ msleep(100); + cec_transmit_attempt_done(adap, cec->tx_status); + } + if (cec->rx_done) { +-- +2.20.1 + diff --git a/projects/Allwinner/patches/linux/0013-cec-improvements.patch b/projects/Allwinner/patches/linux/0013-cec-improvements.patch new file mode 100644 index 0000000000..a7367c738d --- /dev/null +++ b/projects/Allwinner/patches/linux/0013-cec-improvements.patch @@ -0,0 +1,232 @@ +diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +index a63e5f0dae56..fdda26f8b056 100644 +--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c ++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +@@ -2634,7 +2634,7 @@ __dw_hdmi_probe(struct platform_device *pdev, + hdmi->audio = platform_device_register_full(&pdevinfo); + } + +- if (config0 & HDMI_CONFIG0_CEC) { ++ if (!plat_data->is_cec_unusable && (config0 & HDMI_CONFIG0_CEC)) { + cec.hdmi = hdmi; + cec.ops = &dw_hdmi_cec_ops; + cec.irq = irq; +diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig +index 1dbbc3a1b763..7149c72e44c8 100644 +--- a/drivers/gpu/drm/sun4i/Kconfig ++++ b/drivers/gpu/drm/sun4i/Kconfig +@@ -60,6 +60,16 @@ config DRM_SUN8I_DW_HDMI + DesignWare HDMI controller with custom HDMI PHY. If M is + selected the module will be called sun8i_dw_hdmi. + ++config DRM_SUN8I_DW_HDMI_CEC ++ bool "Allwinner DesignWare HDMI CEC Support for 40nm SoCs" ++ depends on DRM_SUN8I_DW_HDMI ++ select CEC_CORE ++ select CEC_PIN ++ help ++ Choose this option if you have an 40nm Allwinner SoC with ++ the DesignWare HDMI controller with custom HDMI PHY and ++ you want to use CEC. ++ + config DRM_SUN8I_MIXER + tristate "Support for Allwinner Display Engine 2.0 Mixer" + default MACH_SUN8I +diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +index 720c5aa8adc1..82dd84094638 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h ++++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + + #define SUN8I_HDMI_PHY_DBG_CTRL_REG 0x0000 + #define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK BIT(0) +@@ -144,6 +145,13 @@ + #define SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK GENMASK(5, 0) + + #define SUN8I_HDMI_PHY_CEC_REG 0x003c ++#define SUN8I_HDMI_PHY_CEC_PIN_CTRL BIT(7) ++/* ++ * Documentation says that this bit is output enable. However, ++ * it seems that this bit is actually output disable. ++ */ ++#define SUN8I_HDMI_PHY_CEC_OUT_DIS BIT(2) ++#define SUN8I_HDMI_PHY_CEC_IN_DATA BIT(1) + + struct sun8i_hdmi_phy; + +@@ -151,6 +159,7 @@ struct sun8i_hdmi_phy_variant { + bool has_phy_clk; + bool has_second_pll; + unsigned int is_custom_phy : 1; ++ unsigned int bit_bang_cec : 1; + const struct dw_hdmi_curr_ctrl *cur_ctr; + const struct dw_hdmi_mpll_config *mpll_cfg; + const struct dw_hdmi_phy_config *phy_cfg; +@@ -163,6 +172,8 @@ struct sun8i_hdmi_phy_variant { + }; + + struct sun8i_hdmi_phy { ++ struct cec_adapter *cec_adapter; ++ struct cec_notifier *cec_notifier; + struct clk *clk_bus; + struct clk *clk_mod; + struct clk *clk_phy; +diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +index 66ea3a902e36..70e291353569 100644 +--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c ++++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c +@@ -503,8 +503,9 @@ static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy) + regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, + SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK, 0); + +- /* set HW control of CEC pins */ +- regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, 0); ++ /* manual control of CEC pins */ ++ regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, ++ SUN8I_HDMI_PHY_CEC_PIN_CTRL); + + /* read calibration data */ + regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val); +@@ -530,8 +531,49 @@ void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy, + plat_data->cur_ctr = variant->cur_ctr; + plat_data->phy_config = variant->phy_cfg; + } ++ plat_data->is_cec_unusable = phy->variant->bit_bang_cec; + } + ++#ifdef CONFIG_DRM_SUN8I_DW_HDMI_CEC ++static bool sun8i_hdmi_phy_cec_pin_read(struct cec_adapter *adap) ++{ ++ struct sun8i_hdmi_phy *phy = cec_get_drvdata(adap); ++ unsigned int val; ++ ++ regmap_read(phy->regs, SUN8I_HDMI_PHY_CEC_REG, &val); ++ ++ return val & SUN8I_HDMI_PHY_CEC_IN_DATA; ++} ++ ++static void sun8i_hdmi_phy_cec_pin_low(struct cec_adapter *adap) ++{ ++ struct sun8i_hdmi_phy *phy = cec_get_drvdata(adap); ++ ++ /* Start driving the CEC pin low */ ++ regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, ++ SUN8I_HDMI_PHY_CEC_PIN_CTRL); ++} ++ ++static void sun8i_hdmi_phy_cec_pin_high(struct cec_adapter *adap) ++{ ++ struct sun8i_hdmi_phy *phy = cec_get_drvdata(adap); ++ ++ /* ++ * Stop driving the CEC pin, the pull up will take over ++ * unless another CEC device is driving the pin low. ++ */ ++ regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, ++ SUN8I_HDMI_PHY_CEC_PIN_CTRL | ++ SUN8I_HDMI_PHY_CEC_OUT_DIS); ++} ++ ++static const struct cec_pin_ops sun8i_hdmi_phy_cec_pin_ops = { ++ .read = sun8i_hdmi_phy_cec_pin_read, ++ .low = sun8i_hdmi_phy_cec_pin_low, ++ .high = sun8i_hdmi_phy_cec_pin_high, ++}; ++#endif ++ + static struct regmap_config sun8i_hdmi_phy_regmap_config = { + .reg_bits = 32, + .val_bits = 32, +@@ -548,6 +590,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = { + }; + + static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = { ++ .bit_bang_cec = true, + .has_phy_clk = true, + .is_custom_phy = true, + .phy_init = &sun8i_hdmi_phy_init_h3, +@@ -556,6 +599,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = { + }; + + static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = { ++ .bit_bang_cec = true, + .has_phy_clk = true, + .has_second_pll = true, + .is_custom_phy = true, +@@ -565,6 +609,7 @@ static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = { + }; + + static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = { ++ .bit_bang_cec = true, + .has_phy_clk = true, + .is_custom_phy = true, + .phy_init = &sun8i_hdmi_phy_init_h3, +@@ -708,10 +753,40 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) + goto err_disable_clk_bus; + } + ++#ifdef CONFIG_DRM_SUN8I_DW_HDMI_CEC ++ if (phy->variant->bit_bang_cec) { ++ phy->cec_notifier = cec_notifier_get(dev); ++ if (!phy->cec_notifier) { ++ ret = -ENOMEM; ++ goto err_disable_clk_mod; ++ } ++ ++ phy->cec_adapter = ++ cec_pin_allocate_adapter(&sun8i_hdmi_phy_cec_pin_ops, ++ phy, "sun8i-cec", ++ CEC_CAP_DEFAULTS); ++ ret = PTR_ERR_OR_ZERO(phy->cec_adapter); ++ if (ret < 0) ++ goto err_put_cec_notifier; ++ ++ ret = cec_register_adapter(phy->cec_adapter, dev); ++ if (ret < 0) ++ goto err_delete_cec_adapter; ++ ++ cec_register_cec_notifier(phy->cec_adapter, phy->cec_notifier); ++ } ++#endif ++ + hdmi->phy = phy; + + return 0; + ++err_delete_cec_adapter: ++ cec_delete_adapter(phy->cec_adapter); ++err_put_cec_notifier: ++ cec_notifier_put(phy->cec_notifier); ++err_disable_clk_mod: ++ clk_disable_unprepare(phy->clk_mod); + err_disable_clk_bus: + clk_disable_unprepare(phy->clk_bus); + err_deassert_rst_phy: +@@ -736,6 +811,10 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi) + { + struct sun8i_hdmi_phy *phy = hdmi->phy; + ++ cec_unregister_adapter(phy->cec_adapter); ++ if (phy->cec_notifier) ++ cec_notifier_put(phy->cec_notifier); ++ + clk_disable_unprepare(phy->clk_mod); + clk_disable_unprepare(phy->clk_bus); + clk_disable_unprepare(phy->clk_phy); +diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h +index 66e70770cce5..764b8bcfa62c 100644 +--- a/include/drm/bridge/dw_hdmi.h ++++ b/include/drm/bridge/dw_hdmi.h +@@ -144,6 +144,8 @@ struct dw_hdmi_plat_data { + int (*configure_phy)(struct dw_hdmi *hdmi, + const struct dw_hdmi_plat_data *pdata, + unsigned long mpixelclock); ++ ++ unsigned int is_cec_unusable : 1; + }; + + struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, diff --git a/projects/Allwinner/patches/linux/0018-cedrus-increase-frequency.patch b/projects/Allwinner/patches/linux/0018-cedrus-increase-frequency.patch new file mode 100644 index 0000000000..680adb5aff --- /dev/null +++ b/projects/Allwinner/patches/linux/0018-cedrus-increase-frequency.patch @@ -0,0 +1,25 @@ +From 18c9a269e2b744ee84f32de9d5c6c66857725ef8 Mon Sep 17 00:00:00 2001 +From: Jernej Skrabec +Date: Sat, 15 Dec 2018 12:56:53 +0100 +Subject: [PATCH 20/20] cedrus increase frequency + +--- + drivers/staging/media/sunxi/cedrus/cedrus_hw.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h +index b43c77d54b95..70677571f3d3 100644 +--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.h ++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.h +@@ -16,7 +16,7 @@ + #ifndef _CEDRUS_HW_H_ + #define _CEDRUS_HW_H_ + +-#define CEDRUS_CLOCK_RATE_DEFAULT 320000000 ++#define CEDRUS_CLOCK_RATE_DEFAULT 402000000 + + int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec); + void cedrus_engine_disable(struct cedrus_dev *dev); +-- +2.20.0 + diff --git a/projects/Allwinner/patches/u-boot/001-sun8i-h3-Add-support-for-the-Beelink-x2-STB.patch b/projects/Allwinner/patches/u-boot/001-sun8i-h3-Add-support-for-the-Beelink-x2-STB.patch new file mode 100644 index 0000000000..ab823e9d56 --- /dev/null +++ b/projects/Allwinner/patches/u-boot/001-sun8i-h3-Add-support-for-the-Beelink-x2-STB.patch @@ -0,0 +1,280 @@ +From patchwork Thu Nov 15 10:39:03 2018 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +Subject: [U-Boot,v3] sun8i: h3: Add support for the Beelink-x2 STB +X-Patchwork-Submitter: Code Kipper +X-Patchwork-Id: 998268 +Message-Id: <20181115103903.7348-1-codekipper@gmail.com> +To: maxime.ripard@free-electrons.com +Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com, jagan@openedev.com, + Marcus Cooper +Date: Thu, 15 Nov 2018 11:39:03 +0100 +From: codekipper@gmail.com +List-Id: U-Boot discussion + +From: Marcus Cooper + +The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot, +2 USB ports( 1 * USB-2 Host, 1 USB OTG), a 10/100M ethernet port using the +SoC's integrated PHY, Wifi via an sdio wifi chip, HDMI, an IR receiver, a +dual colour LED and an optical S/PDIF connector. + +Signed-off-by: Marcus Cooper +Acked-by: Maxime Ripard +--- +Changes in v3: +- Removed incorrect commit author +- Included v1-v2 change info + +Changes in v2: +- updated dts to reflex current linux kernel status + +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/sun8i-h3-beelink-x2.dts | 179 +++++++++++++++++++++++++++ + board/sunxi/MAINTAINERS | 5 + + configs/beelink_x2_defconfig | 19 +++ + 4 files changed, 204 insertions(+) + create mode 100644 arch/arm/dts/sun8i-h3-beelink-x2.dts + create mode 100644 configs/beelink_x2_defconfig + +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index 1cbb45d679..cc217d4f98 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -370,6 +370,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ + sun8i-h2-plus-orangepi-r1.dtb \ + sun8i-h2-plus-orangepi-zero.dtb \ + sun8i-h3-bananapi-m2-plus.dtb \ ++ sun8i-h3-beelink-x2.dtb \ + sun8i-h3-libretech-all-h3-cc.dtb \ + sun8i-h3-nanopi-m1.dtb \ + sun8i-h3-nanopi-m1-plus.dtb \ +diff --git a/arch/arm/dts/sun8i-h3-beelink-x2.dts b/arch/arm/dts/sun8i-h3-beelink-x2.dts +new file mode 100644 +index 0000000000..683c5c31a9 +--- /dev/null ++++ b/arch/arm/dts/sun8i-h3-beelink-x2.dts +@@ -0,0 +1,180 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++// ++// Device Tree Source for Beelink X2 ++// ++// Copyright (C) 2018 Marcus Cooper ++/dts-v1/; ++#include "sun8i-h3.dtsi" ++#include "sunxi-common-regulators.dtsi" ++ ++#include ++#include ++ ++/ { ++ model = "Beelink X2"; ++ compatible = "roofull,beelink-x2", "allwinner,sun8i-h3"; ++ ++ aliases { ++ serial0 = &uart0; ++ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ ++ ethernet0 = &emac; ++ ethernet1 = &sdiowifi; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ connector { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ blue { ++ label = "beelink-x2:blue:pwr"; ++ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ ++ default-state = "on"; ++ }; ++ ++ red { ++ label = "beelink-x2:red:standby"; ++ gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ ++ }; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ ++ }; ++ ++ sound_spdif { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "On-board SPDIF"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&spdif>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&spdif_out>; ++ }; ++ }; ++ ++ spdif_out: spdif-out { ++ #sound-dai-cells = <0>; ++ compatible = "linux,spdif-dit"; ++ }; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&emac { ++ phy-handle = <&int_mii_phy>; ++ phy-mode = "mii"; ++ allwinner,leds-active-low; ++ status = "okay"; ++}; ++ ++&hdmi { ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&ir { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ir_pins_a>; ++ status = "okay"; ++}; ++ ++&mmc0 { ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ status = "okay"; ++}; ++ ++&mmc1 { ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ /* ++ * Explicitly define the sdio device, so that we can add an ethernet ++ * alias for it (which e.g. makes u-boot set a mac-address). ++ */ ++ sdiowifi: sdio_wifi@1 { ++ reg = <1>; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_8bit_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++®_usb0_vbus { ++ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ ++ status = "okay"; ++}; ++ ++&spdif { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spdif_tx_pins_a>; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usb_otg { ++ dr_mode = "otg"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ /* USB VBUS is always on except for the OTG port */ ++ status = "okay"; ++ usb0_id_det-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA07 */ ++ usb0_vbus-supply = <®_usb0_vbus>; ++}; +diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS +index 478e37285f..6417158fd1 100644 +--- a/board/sunxi/MAINTAINERS ++++ b/board/sunxi/MAINTAINERS +@@ -159,6 +159,11 @@ M: Jagan Teki + S: Maintained + F: configs/bananapi_m64_defconfig + ++BEELINK X2 BOARD ++M: Marcus Cooper ++S: Maintained ++F: configs/beelink_x2_defconfig ++ + COLOMBUS BOARD + M: Maxime Ripard + S: Maintained +diff --git a/configs/beelink_x2_defconfig b/configs/beelink_x2_defconfig +new file mode 100644 +index 0000000000..6508e470a0 +--- /dev/null ++++ b/configs/beelink_x2_defconfig +@@ -0,0 +1,19 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_SPL=y ++CONFIG_MACH_SUN8I_H3=y ++CONFIG_DRAM_CLK=624 ++CONFIG_DRAM_ZQ=3881979 ++CONFIG_DRAM_ODT_EN=y ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-beelink-x2" ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_CONSOLE_MUX=y ++CONFIG_SPL_I2C_SUPPORT=y ++# CONFIG_CMD_FLASH is not set ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_SUN8I_EMAC=y ++CONFIG_SY8106A_POWER=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y diff --git a/projects/Allwinner/patches/u-boot/002-disable-usb-keyboard.patch b/projects/Allwinner/patches/u-boot/002-disable-usb-keyboard.patch new file mode 100644 index 0000000000..2b52175a60 --- /dev/null +++ b/projects/Allwinner/patches/u-boot/002-disable-usb-keyboard.patch @@ -0,0 +1,13 @@ +diff -Nur a/arch/arm/Kconfig usb/arch/arm/Kconfig +--- a/arch/arm/Kconfig 2016-09-12 16:05:51.000000000 +0200 ++++ usb/arch/arm/Kconfig 2016-09-21 19:19:44.533396743 +0200 +@@ -590,9 +590,8 @@ + select SPL_SYS_THUMB_BUILD if !ARM64 + select SYS_NS16550 + select SYS_THUMB_BUILD if !ARM64 + select USB if DISTRO_DEFAULTS +- select USB_KEYBOARD if DISTRO_DEFAULTS + select USB_STORAGE if DISTRO_DEFAULTS + select USE_TINY_PRINTF + imply CMD_DM + imply CMD_GPT diff --git a/projects/Allwinner/patches/u-boot/003-fix-hdmi-clocks.patch b/projects/Allwinner/patches/u-boot/003-fix-hdmi-clocks.patch new file mode 100644 index 0000000000..417c52b652 --- /dev/null +++ b/projects/Allwinner/patches/u-boot/003-fix-hdmi-clocks.patch @@ -0,0 +1,135 @@ +diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c +index 9dbea649a0..a2aced2cab 100644 +--- a/drivers/video/sunxi/sunxi_dw_hdmi.c ++++ b/drivers/video/sunxi/sunxi_dw_hdmi.c +@@ -132,7 +132,7 @@ static int sunxi_dw_hdmi_wait_for_hpd(void) + return -1; + } + +-static void sunxi_dw_hdmi_phy_set(uint clock) ++static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div) + { + struct sunxi_hdmi_phy * const phy = + (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS); +@@ -146,7 +146,7 @@ static void sunxi_dw_hdmi_phy_set(uint clock) + switch (div) { + case 1: + writel(0x30dc5fc0, &phy->pll); +- writel(0x800863C0, &phy->clk); ++ writel(0x800863C0 | (phy_div - 1), &phy->clk); + mdelay(10); + writel(0x00000001, &phy->unk3); + setbits_le32(&phy->pll, BIT(25)); +@@ -164,7 +164,7 @@ static void sunxi_dw_hdmi_phy_set(uint clock) + break; + case 2: + writel(0x39dc5040, &phy->pll); +- writel(0x80084381, &phy->clk); ++ writel(0x80084380 | (phy_div - 1), &phy->clk); + mdelay(10); + writel(0x00000001, &phy->unk3); + setbits_le32(&phy->pll, BIT(25)); +@@ -178,7 +178,7 @@ static void sunxi_dw_hdmi_phy_set(uint clock) + break; + case 4: + writel(0x39dc5040, &phy->pll); +- writel(0x80084343, &phy->clk); ++ writel(0x80084340 | (phy_div - 1), &phy->clk); + mdelay(10); + writel(0x00000001, &phy->unk3); + setbits_le32(&phy->pll, BIT(25)); +@@ -192,7 +192,7 @@ static void sunxi_dw_hdmi_phy_set(uint clock) + break; + case 11: + writel(0x39dc5040, &phy->pll); +- writel(0x8008430a, &phy->clk); ++ writel(0x80084300 | (phy_div - 1), &phy->clk); + mdelay(10); + writel(0x00000001, &phy->unk3); + setbits_le32(&phy->pll, BIT(25)); +@@ -207,36 +207,46 @@ static void sunxi_dw_hdmi_phy_set(uint clock) + } + } + +-static void sunxi_dw_hdmi_pll_set(uint clk_khz) ++static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div) + { +- int value, n, m, div = 0, diff; +- int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF; +- +- div = sunxi_dw_hdmi_get_divider(clk_khz * 1000); ++ int value, n, m, div, diff; ++ int best_n = 0, best_m = 0, best_div = 0, best_diff = 0x0FFFFFFF; + + /* + * Find the lowest divider resulting in a matching clock. If there + * is no match, pick the closest lower clock, as monitors tend to + * not sync to higher frequencies. + */ +- for (m = 1; m <= 16; m++) { +- n = (m * div * clk_khz) / 24000; +- +- if ((n >= 1) && (n <= 128)) { +- value = (24000 * n) / m / div; +- diff = clk_khz - value; +- if (diff < best_diff) { +- best_diff = diff; +- best_m = m; +- best_n = n; ++ for (div = 1; div <= 16; div++) { ++ int target = clk_khz * div; ++ ++ if (target < 192000) ++ continue; ++ if (target > 912000) ++ continue; ++ ++ for (m = 1; m <= 16; m++) { ++ n = (m * target) / 24000; ++ ++ if ((n >= 1) && (n <= 128)) { ++ value = (24000 * n) / m / div; ++ diff = clk_khz - value; ++ if (diff < best_diff) { ++ best_diff = diff; ++ best_m = m; ++ best_n = n; ++ best_div = div; ++ } + } + } + } + ++ *phy_div = best_div; ++ + clock_set_pll3_factors(best_m, best_n); + debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n", +- clk_khz, (clock_get_pll3() / 1000) / div, +- best_n, best_m, div); ++ clk_khz, (clock_get_pll3() / 1000) / best_div, ++ best_n, best_m, best_div); + } + + static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid, +@@ -244,7 +254,7 @@ static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid, + { + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; +- int div = sunxi_dw_hdmi_get_divider(edid->pixelclock.typ); ++ int div = clock_get_pll3() / edid->pixelclock.typ; + struct sunxi_lcdc_reg *lcdc; + + if (mux == 0) { +@@ -276,8 +286,10 @@ static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid, + + static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) + { +- sunxi_dw_hdmi_pll_set(mpixelclock/1000); +- sunxi_dw_hdmi_phy_set(mpixelclock); ++ int phy_div; ++ ++ sunxi_dw_hdmi_pll_set(mpixelclock/1000, &phy_div); ++ sunxi_dw_hdmi_phy_set(mpixelclock, phy_div); + + return 0; + }