diff --git a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.16.patch b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.16.patch deleted file mode 100644 index f917de4397..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.16.patch +++ /dev/null @@ -1,2262 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Sun, 11 Jul 2021 16:34:30 +0200 -Subject: [PATCH] arm64: dts: rockchip: remove interrupt-names from iommu nodes - -The iommu driver gets the interrupts by platform_get_irq(), -so remove interrupt-names property from iommu nodes. - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20210711143430.14347-2-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 5 ----- - arch/arm64/boot/dts/rockchip/rk3368.dtsi | 5 ----- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 -------- - 3 files changed, 18 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 8c821acb21ff..becc1c61b182 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -623,7 +623,6 @@ h265e_mmu: iommu@ff330200 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff330200 0 0x100>; - interrupts = ; -- interrupt-names = "h265e_mmu"; - clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -@@ -634,7 +633,6 @@ vepu_mmu: iommu@ff340800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff340800 0x0 0x40>; - interrupts = ; -- interrupt-names = "vepu_mmu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -@@ -656,7 +654,6 @@ vpu_mmu: iommu@ff350800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff350800 0x0 0x40>; - interrupts = ; -- interrupt-names = "vpu_mmu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -@@ -667,7 +664,6 @@ rkvdec_mmu: iommu@ff360480 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; - interrupts = ; -- interrupt-names = "rkvdec_mmu"; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -@@ -700,7 +696,6 @@ vop_mmu: iommu@ff373f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff373f00 0x0 0x100>; - interrupts = ; -- interrupt-names = "vop_mmu"; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi -index 4c64fbefb483..4217897cd454 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi -@@ -709,7 +709,6 @@ iep_mmu: iommu@ff900800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff900800 0x0 0x100>; - interrupts = ; -- interrupt-names = "iep_mmu"; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -@@ -721,7 +720,6 @@ isp_mmu: iommu@ff914000 { - reg = <0x0 0xff914000 0x0 0x100>, - <0x0 0xff915000 0x0 0x100>; - interrupts = ; -- interrupt-names = "isp_mmu"; - clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -@@ -733,7 +731,6 @@ vop_mmu: iommu@ff930300 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff930300 0x0 0x100>; - interrupts = ; -- interrupt-names = "vop_mmu"; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -@@ -745,7 +742,6 @@ hevc_mmu: iommu@ff9a0440 { - reg = <0x0 0xff9a0440 0x0 0x40>, - <0x0 0xff9a0480 0x0 0x40>; - interrupts = ; -- interrupt-names = "hevc_mmu"; - clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -@@ -757,7 +753,6 @@ vpu_mmu: iommu@ff9a0800 { - reg = <0x0 0xff9a0800 0x0 0x100>; - interrupts = , - ; -- interrupt-names = "vepu_mmu", "vdpu_mmu"; - clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 3871c7fd83b0..aa5d7dca3432 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1240,7 +1240,6 @@ vpu: video-codec@ff650000 { - reg = <0x0 0xff650000 0x0 0x800>; - interrupts = , - ; -- interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; -@@ -1251,7 +1250,6 @@ vpu_mmu: iommu@ff650800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff650800 0x0 0x40>; - interrupts = ; -- interrupt-names = "vpu_mmu"; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -@@ -1273,7 +1271,6 @@ vdec_mmu: iommu@ff660480 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; - interrupts = ; -- interrupt-names = "vdec_mmu"; - clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3399_PD_VDU>; -@@ -1284,7 +1281,6 @@ iep_mmu: iommu@ff670800 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff670800 0x0 0x40>; - interrupts = ; -- interrupt-names = "iep_mmu"; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -@@ -1666,7 +1662,6 @@ vopl_mmu: iommu@ff8f3f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff8f3f00 0x0 0x100>; - interrupts = ; -- interrupt-names = "vopl_mmu"; - clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3399_PD_VOPL>; -@@ -1723,7 +1718,6 @@ vopb_mmu: iommu@ff903f00 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff903f00 0x0 0x100>; - interrupts = ; -- interrupt-names = "vopb_mmu"; - clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3399_PD_VOPB>; -@@ -1761,7 +1755,6 @@ isp0_mmu: iommu@ff914000 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; - interrupts = ; -- interrupt-names = "isp0_mmu"; - clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -@@ -1773,7 +1766,6 @@ isp1_mmu: iommu@ff924000 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; - interrupts = ; -- interrupt-names = "isp1_mmu"; - clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Sun, 11 Jul 2021 16:59:00 +0200 -Subject: [PATCH] arm64: dts: rockchip: rename flash nodenames - -Nodes with compatible "jedec,spi-nor" are now checked with -jedec,spi-nor.yaml and mtd.yaml. The pattern is now -"^flash(@.*)?$", so change that for the boards with a -Rockchip SoC. - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20210711145900.15443-1-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 2 +- - arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -index 1b0f7e4551ea..f69a38f42d2d 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -@@ -345,7 +345,7 @@ &spdif { - &spi0 { - status = "okay"; - -- spiflash@0 { -+ flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi -index c1bcc8ca3769..e310b51ab578 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi -@@ -543,7 +543,7 @@ &spi1 { - pinctrl-names = "default", "sleep"; - pinctrl-1 = <&spi1_sleep>; - -- spiflash@0 { -+ flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Thu, 1 Jul 2021 16:41:09 +0200 -Subject: [PATCH] arm64: dts: rockchip: remove clock_in_out from gmac2phy node - in rk3318-a95x-z2.dts - -Recently a clock_in_out property was added to the gmac2phy node -in rk3328.dtsi, so now the clock_in_out in rk3318-a95x-z2.dts -can be removed. - -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20210701144110.12333-1-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts -index 763cf9b4620e..d41f786b2f4b 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts -@@ -185,7 +185,6 @@ &gmac2phy { - assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; - assigned-clock-rate = <50000000>; - assigned-clocks = <&cru SCLK_MAC2PHY>; -- clock_in_out = "output"; - status = "okay"; - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Johan Jonker -Date: Thu, 1 Jul 2021 16:41:10 +0200 -Subject: [PATCH] arm64: dts: rockchip: remove ddc-i2c-scl-* properties from - rk3318-a95x-z2.dts - -The ddc-i2c-scl-* properties in the hdmi node are -not in use in the mainline kernel, so remove them. - -Reported-by: Alex Bee -Signed-off-by: Johan Jonker -Link: https://lore.kernel.org/r/20210701144110.12333-2-jbx6244@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts | 2 -- - 1 file changed, 2 deletions(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts -index d41f786b2f4b..43c928ac98f0 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts -@@ -193,8 +193,6 @@ &gpu { - }; - - &hdmi { -- ddc-i2c-scl-high-time-ns = <9625>; -- ddc-i2c-scl-low-time-ns = <10000>; - status = "okay"; - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Liang Chen -Date: Thu, 24 Jun 2021 19:47:17 +0800 -Subject: [PATCH] dt-bindings: arm: rockchip: add rk3568 compatible string to - pmu.yaml - -add "rockchip,rk3568-pmu", "syscon", "simple-mfd" for pmu nodes on a -rk3568 platform to pmu.ymal. - -Signed-off-by: Liang Chen -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20210624114719.1685-2-cl@rock-chips.com -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip/pmu.yaml | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml -index 53115b92d17f..ceb15cea77e2 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml -@@ -23,6 +23,7 @@ select: - - rockchip,rk3066-pmu - - rockchip,rk3288-pmu - - rockchip,rk3399-pmu -+ - rockchip,rk3568-pmu - - required: - - compatible -@@ -35,6 +36,7 @@ properties: - - rockchip,rk3066-pmu - - rockchip,rk3288-pmu - - rockchip,rk3399-pmu -+ - rockchip,rk3568-pmu - - const: syscon - - const: simple-mfd - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Liang Chen -Date: Thu, 24 Jun 2021 21:10:27 +0800 -Subject: [PATCH] arm64: dts: rockchip: add pmu and qos nodes for rk3568 - -Add the power-management and QoS nodes to the core rk3568 dtsi. - -Signed-off-by: Liang Chen -Link: https://lore.kernel.org/r/20210624131027.3719-1-cl@rock-chips.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568.dtsi | 229 +++++++++++++++++++++++ - 1 file changed, 229 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -index d225e6a45d5c..618849186c39 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -257,6 +258,99 @@ uart0: serial@fdd50000 { - status = "disabled"; - }; - -+ pmu: power-management@fdd90000 { -+ compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; -+ reg = <0x0 0xfdd90000 0x0 0x1000>; -+ -+ power: power-controller { -+ compatible = "rockchip,rk3568-power-controller"; -+ #power-domain-cells = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* These power domains are grouped by VD_GPU */ -+ power-domain@RK3568_PD_GPU { -+ reg = ; -+ clocks = <&cru ACLK_GPU_PRE>, -+ <&cru PCLK_GPU_PRE>; -+ pm_qos = <&qos_gpu>; -+ #power-domain-cells = <0>; -+ }; -+ -+ /* These power domains are grouped by VD_LOGIC */ -+ power-domain@RK3568_PD_VI { -+ reg = ; -+ clocks = <&cru HCLK_VI>, -+ <&cru PCLK_VI>; -+ pm_qos = <&qos_isp>, -+ <&qos_vicap0>, -+ <&qos_vicap1>; -+ #power-domain-cells = <0>; -+ }; -+ -+ power-domain@RK3568_PD_VO { -+ reg = ; -+ clocks = <&cru HCLK_VO>, -+ <&cru PCLK_VO>, -+ <&cru ACLK_VOP_PRE>; -+ pm_qos = <&qos_hdcp>, -+ <&qos_vop_m0>, -+ <&qos_vop_m1>; -+ #power-domain-cells = <0>; -+ }; -+ -+ power-domain@RK3568_PD_RGA { -+ reg = ; -+ clocks = <&cru HCLK_RGA_PRE>, -+ <&cru PCLK_RGA_PRE>; -+ pm_qos = <&qos_ebc>, -+ <&qos_iep>, -+ <&qos_jpeg_dec>, -+ <&qos_jpeg_enc>, -+ <&qos_rga_rd>, -+ <&qos_rga_wr>; -+ #power-domain-cells = <0>; -+ }; -+ -+ power-domain@RK3568_PD_VPU { -+ reg = ; -+ clocks = <&cru HCLK_VPU_PRE>; -+ pm_qos = <&qos_vpu>; -+ #power-domain-cells = <0>; -+ }; -+ -+ power-domain@RK3568_PD_RKVDEC { -+ clocks = <&cru HCLK_RKVDEC_PRE>; -+ reg = ; -+ pm_qos = <&qos_rkvdec>; -+ #power-domain-cells = <0>; -+ }; -+ -+ power-domain@RK3568_PD_RKVENC { -+ reg = ; -+ clocks = <&cru HCLK_RKVENC_PRE>; -+ pm_qos = <&qos_rkvenc_rd_m0>, -+ <&qos_rkvenc_rd_m1>, -+ <&qos_rkvenc_wr_m0>; -+ #power-domain-cells = <0>; -+ }; -+ -+ power-domain@RK3568_PD_PIPE { -+ reg = ; -+ clocks = <&cru PCLK_PIPE>; -+ pm_qos = <&qos_pcie2x1>, -+ <&qos_pcie3x1>, -+ <&qos_pcie3x2>, -+ <&qos_sata0>, -+ <&qos_sata1>, -+ <&qos_sata2>, -+ <&qos_usb3_0>, -+ <&qos_usb3_1>; -+ #power-domain-cells = <0>; -+ }; -+ }; -+ }; -+ - sdmmc2: mmc@fe000000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe000000 0x0 0x4000>; -@@ -271,6 +365,141 @@ sdmmc2: mmc@fe000000 { - status = "disabled"; - }; - -+ qos_gpu: qos@fe128000 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe128000 0x0 0x20>; -+ }; -+ -+ qos_rkvenc_rd_m0: qos@fe138080 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe138080 0x0 0x20>; -+ }; -+ -+ qos_rkvenc_rd_m1: qos@fe138100 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe138100 0x0 0x20>; -+ }; -+ -+ qos_rkvenc_wr_m0: qos@fe138180 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe138180 0x0 0x20>; -+ }; -+ -+ qos_isp: qos@fe148000 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe148000 0x0 0x20>; -+ }; -+ -+ qos_vicap0: qos@fe148080 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe148080 0x0 0x20>; -+ }; -+ -+ qos_vicap1: qos@fe148100 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe148100 0x0 0x20>; -+ }; -+ -+ qos_vpu: qos@fe150000 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe150000 0x0 0x20>; -+ }; -+ -+ qos_ebc: qos@fe158000 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe158000 0x0 0x20>; -+ }; -+ -+ qos_iep: qos@fe158100 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe158100 0x0 0x20>; -+ }; -+ -+ qos_jpeg_dec: qos@fe158180 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe158180 0x0 0x20>; -+ }; -+ -+ qos_jpeg_enc: qos@fe158200 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe158200 0x0 0x20>; -+ }; -+ -+ qos_rga_rd: qos@fe158280 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe158280 0x0 0x20>; -+ }; -+ -+ qos_rga_wr: qos@fe158300 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe158300 0x0 0x20>; -+ }; -+ -+ qos_npu: qos@fe180000 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe180000 0x0 0x20>; -+ }; -+ -+ qos_pcie2x1: qos@fe190000 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe190000 0x0 0x20>; -+ }; -+ -+ qos_pcie3x1: qos@fe190080 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe190080 0x0 0x20>; -+ }; -+ -+ qos_pcie3x2: qos@fe190100 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe190100 0x0 0x20>; -+ }; -+ -+ qos_sata0: qos@fe190200 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe190200 0x0 0x20>; -+ }; -+ -+ qos_sata1: qos@fe190280 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe190280 0x0 0x20>; -+ }; -+ -+ qos_sata2: qos@fe190300 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe190300 0x0 0x20>; -+ }; -+ -+ qos_usb3_0: qos@fe190380 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe190380 0x0 0x20>; -+ }; -+ -+ qos_usb3_1: qos@fe190400 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe190400 0x0 0x20>; -+ }; -+ -+ qos_rkvdec: qos@fe198000 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe198000 0x0 0x20>; -+ }; -+ -+ qos_hdcp: qos@fe1a8000 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe1a8000 0x0 0x20>; -+ }; -+ -+ qos_vop_m0: qos@fe1a8080 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe1a8080 0x0 0x20>; -+ }; -+ -+ qos_vop_m1: qos@fe1a8100 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe1a8100 0x0 0x20>; -+ }; -+ - sdmmc0: mmc@fe2b0000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe2b0000 0x0 0x4000>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Levin Du -Date: Fri, 9 Jul 2021 16:01:25 +0800 -Subject: [PATCH] dt-bindings: add doc for Firefly ROC-RK3328-PC - -Add devicetree binding documentation for the Firefly ROC-RK3328-PC. - -Signed-off-by: Levin Du -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20210709080126.17045-2-djw@t-chip.com.cn -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index 6546b015fc62..7ef902f45b38 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -115,6 +115,11 @@ properties: - - const: firefly,roc-rk3328-cc - - const: rockchip,rk3328 - -+ - description: Firefly ROC-RK3328-PC -+ items: -+ - const: firefly,roc-rk3328-pc -+ - const: rockchip,rk3328 -+ - - description: Firefly ROC-RK3399-PC - items: - - enum: - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Levin Du -Date: Fri, 9 Jul 2021 16:01:26 +0800 -Subject: [PATCH] arm64: dts: rockchip: add support for Firefly ROC-RK3328-PC - -ROC-RK3328-PC is the board inside the portable Firefly Station M1 -Geek PC. As a redesign after the ROC-RK3328-CC, it uses TypeC as -power input and OTG port, embedded with eMMC 5.1 storage and a -SDIO WiFi/BT chip (RTL8723DS). - -- Rockchip RK3328 SoC -- 2/4GB LPDDR3 RAM -- 16/32/64/128GB eMMC 5.1 -- TF card slot -- USB 3.0 Port x 1, USB 2.0 Port x 1, TypeC Port x 1 (Power/OTG) -- HDMI -- Gigabit Ethernet -- WiFi: RTL8723DS -- Audio: RK3328 -- Key: Power, Reset, Recovery -- LED: POWER, USER -- IR - -Signed-off-by: Levin Du -Link: https://lore.kernel.org/r/20210709080126.17045-3-djw@t-chip.com.cn -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../arm64/boot/dts/rockchip/rk3328-roc-pc.dts | 110 ++++++++++++++++++ - 2 files changed, 111 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index 7fdb41de01ec..46652b6d7c4d 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-pc.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts -new file mode 100644 -index 000000000000..e3e3984d01d4 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts -@@ -0,0 +1,110 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+// Copyright (c) 2021 T-Chip Intelligent Technology Co., Ltd -+ -+/dts-v1/; -+ -+#include -+ -+#include "rk3328-roc-cc.dts" -+ -+/ { -+ model = "Firefly ROC-RK3328-PC"; -+ compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328"; -+ -+ adc-keys { -+ compatible = "adc-keys"; -+ io-channels = <&saradc 0>; -+ io-channel-names = "buttons"; -+ keyup-threshold-microvolt = <1750000>; -+ -+ /* This button is unpopulated out of the factory. */ -+ button-recovery { -+ label = "Recovery"; -+ linux,code = ; -+ press-threshold-microvolt = <10000>; -+ }; -+ }; -+ -+ ir-receiver { -+ compatible = "gpio-ir-receiver"; -+ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; -+ linux,rc-map-name = "rc-khadas"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ir_int>; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_en>, <&wifi_host_wake>; -+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&codec { -+ mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_logic>; -+}; -+ -+&pinctrl { -+ ir { -+ ir_int: ir-int { -+ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sdmmcio { -+ sdio_per_pin: sdio-per-pin { -+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ wifi { -+ wifi_en: wifi-en { -+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wifi_host_wake: wifi-host-wake { -+ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>; -+ }; -+ -+ bt_rst: bt-rst { -+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_en: bt-en { -+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmic_int_l { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; -+}; -+ -+&rk805 { -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+}; -+ -+&saradc { -+ vref-supply = <&vcc_18>; -+ status = "okay"; -+}; -+ -+&usb20_host_drv { -+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; -+}; -+ -+&vcc_host1_5v { -+ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; -+}; -+ -+&vcc_sdio { -+ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio_per_pin>; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Levin Du -Date: Mon, 28 Jun 2021 11:54:01 +0800 -Subject: [PATCH] dt-bindings: add doc for Firefly ROC-RK3399-PC-PLUS - -Add devicetree binding documentation for the Firefly ROC-RK3399-PC-PLUS. - -Signed-off-by: Levin Du -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20210628035402.16812-2-djw@t-chip.com.cn -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index 7ef902f45b38..ce7785fe3598 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -127,6 +127,12 @@ properties: - - firefly,roc-rk3399-pc-mezzanine - - const: rockchip,rk3399 - -+ - description: Firefly ROC-RK3399-PC-PLUS -+ items: -+ - enum: -+ - firefly,roc-rk3399-pc-plus -+ - const: rockchip,rk3399 -+ - - description: FriendlyElec NanoPi R2S - items: - - const: friendlyarm,nanopi-r2s - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Levin Du -Date: Mon, 28 Jun 2021 11:54:02 +0800 -Subject: [PATCH] arm64: dts: rockchip: add support for Firefly - ROC-RK3399-PC-PLUS - -ROC-RK3399-PC-PLUS is the board inside the portable Firefly Station P1 Geek -PC. As a redesign after the ROC-RK3399-PC, it uses DC-12V as power input -and spares a USB 3 host port. It is also equipped with a USB WiFi chip and -audio codec without the mezzanine board. - -- Rockchip RK3399 SoC -- 4GB LPDDR4 RAM -- 16MB SPI-Flash -- eMMC slot -- TF card slot -- USB 3.0 Port x 1, USB 2.0 Port x 1, TypeC Port x 1 -- HDMI -- Gigabit Ethernet -- WiFi: RTL8723DU -- Audio: ES8388 -- Key: Recovery -- LED: WORK, DIY -- IR - -Signed-off-by: Kongxin Deng -Signed-off-by: Levin Du -Link: https://lore.kernel.org/r/20210628035402.16812-3-djw@t-chip.com.cn -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3399-roc-pc-plus.dts | 218 ++++++++++++++++++ - 2 files changed, 219 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index 46652b6d7c4d..2890756c294c 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -43,6 +43,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts -new file mode 100644 -index 000000000000..5a2661ae0131 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts -@@ -0,0 +1,218 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd -+ */ -+ -+/dts-v1/; -+#include "rk3399-roc-pc.dtsi" -+ -+/* -+ * Notice: -+ * 1. rk3399-roc-pc-plus is powered by dc_12v directly. -+ * 2. rk3399-roc-pc-plus has only vcc_bus_typec0 in schematic, which is coresponding -+ * to vcc_vbus_typec1 in rk3399-roc-pc. -+ * For simplicity, reserve the node name of vcc_vbus_typec1. -+ * 3. vcc5v0_host is actually 2 regulators (host0, 1) controlled by the same gpio. -+ */ -+ -+/delete-node/ &fusb1; -+/delete-node/ &hub_rst; -+/delete-node/ &mp8859; -+/delete-node/ &vcc_sys_en; -+/delete-node/ &vcc_vbus_typec0; -+/delete-node/ &yellow_led; -+ -+/ { -+ model = "Firefly ROC-RK3399-PC-PLUS Board"; -+ compatible = "firefly,roc-rk3399-pc-plus", "rockchip,rk3399"; -+ -+ dc_12v: dc-12v { -+ compatible = "regulator-fixed"; -+ regulator-name = "dc_12v"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ es8388-sound { -+ compatible = "simple-audio-card"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hp_det_pin>; -+ simple-audio-card,name = "rockchip,es8388-codec"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,mclk-fs = <256>; -+ simple-audio-card,widgets = -+ "Microphone", "Mic Jack", -+ "Headphone", "Headphones"; -+ simple-audio-card,routing = -+ "LINPUT1", "Mic Jack", -+ "Headphone Amp INL", "LOUT2", -+ "Headphone Amp INR", "ROUT2", -+ "Headphones", "Headphone Amp OUTL", -+ "Headphones", "Headphone Amp OUTR"; -+ simple-audio-card,hp-det-gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; -+ simple-audio-card,aux-devs = <&headphones_amp>; -+ simple-audio-card,pin-switches = "Headphones"; -+ -+ simple-audio-card,codec { -+ sound-dai = <&es8388>; -+ }; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s1>; -+ }; -+ }; -+ -+ gpio-fan { -+ #cooling-cells = <2>; -+ compatible = "gpio-fan"; -+ gpio-fan,speed-map = <0 0 3000 1>; -+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ /delete-node/ gpio-keys; -+ -+ /* not amplifier, used as switcher only */ -+ headphones_amp: headphones-amp { -+ compatible = "simple-audio-amplifier"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ear_ctl_pin>; -+ enable-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; -+ sound-name-prefix = "Headphone Amp"; -+ VCC-supply = <&vcca3v0_codec>; -+ }; -+ -+ ir-receiver { -+ linux,rc-map-name = "rc-khadas"; -+ }; -+ -+ leds { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&work_led_pin>, <&diy_led_pin>; -+ }; -+}; -+ -+&fusb0 { -+ vbus-supply = <&vcc_vbus_typec1>; -+}; -+ -+&i2c0 { -+ hym8563: hym8563@51 { -+ compatible = "haoyu,hym8563"; -+ reg = <0x51>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ clock-output-names = "xin32k"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hym8563_int>; -+ }; -+}; -+ -+&i2c1 { -+ es8388: es8388@11 { -+ compatible = "everest,es8388"; -+ reg = <0x11>; -+ clock-names = "mclk"; -+ clocks = <&cru SCLK_I2S_8CH_OUT>; -+ #sound-dai-cells = <0>; -+ }; -+}; -+ -+/* <4 RK_PA0 1 &pcfg_pull_none> is used as i2s_8ch_mclk_pin */ -+&i2s0_8ch_bus { -+ rockchip,pins = -+ <3 RK_PD0 1 &pcfg_pull_none>, -+ <3 RK_PD1 1 &pcfg_pull_none>, -+ <3 RK_PD2 1 &pcfg_pull_none>, -+ <3 RK_PD3 1 &pcfg_pull_none>, -+ <3 RK_PD4 1 &pcfg_pull_none>, -+ <3 RK_PD5 1 &pcfg_pull_none>, -+ <3 RK_PD6 1 &pcfg_pull_none>, -+ <3 RK_PD7 1 &pcfg_pull_none>; -+}; -+ -+&i2s1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s_8ch_mclk_pin>, <&i2s1_2ch_bus>; -+ rockchip,playback-channels = <2>; -+ rockchip,capture-channels = <2>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ es8388 { -+ ear_ctl_pin: ear-ctl-pin { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>; -+ }; -+ -+ hp_det_pin: hp-det-pin { -+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ hym8563 { -+ hym8563_int: hym8563-int { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ i2s1 { -+ i2s_8ch_mclk_pin: i2s-8ch-mclk-pin { -+ rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+ -+ u2phy0_otg: otg-port { -+ phy-supply = <&vcc_vbus_typec1>; -+ status = "okay"; -+ }; -+ -+ u2phy0_host: host-port { -+ phy-supply = <&vcc5v0_host>; -+ status = "okay"; -+ }; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+ -+ u2phy1_otg: otg-port { -+ phy-supply = <&vcc5v0_host>; -+ status = "okay"; -+ }; -+ -+ u2phy1_host: host-port { -+ phy-supply = <&vcc5v0_host>; -+ status = "okay"; -+ }; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_0 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&vcc_sys { -+ /* vcc_sys is fixed, not controlled by any gpio */ -+ /delete-property/ gpio; -+ /delete-property/ pinctrl-names; -+ /delete-property/ pinctrl-0; -+}; -+ -+&vcc5v0_host { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_host_en>; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Dennis Gilmore -Date: Wed, 14 Jul 2021 21:56:29 -0500 -Subject: [PATCH] arm64: dts: rockchip: set stdout-path on helios64 - -set the default output path to uart2 - -Signed-off-by: Dennis Gilmore -Link: https://lore.kernel.org/r/20210715025635.70452-2-dgilmore@redhat.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -index 738cfd21df3e..d911a9a4f0f0 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -@@ -43,6 +43,10 @@ avdd_1v8_s0: avdd-1v8-s0 { - vin-supply = <&vcc3v3_sys_s3>; - }; - -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ - clkin_gmac: external-gmac-clock { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Dennis Gilmore -Date: Wed, 14 Jul 2021 21:56:30 -0500 -Subject: [PATCH] arm64: dts: rockchip: add SPI support to helios64 - -add SPI support for the helios64, u-boot can live in spi1, spi2 is user -accessible, spi5 is for the sata controller rom. -https://wiki.kobol.io/helios64/spi/ - -Signed-off-by: Dennis Gilmore -Link: https://lore.kernel.org/r/20210715025635.70452-3-dgilmore@redhat.com -Signed-off-by: Heiko Stuebner ---- - .../dts/rockchip/rk3399-kobol-helios64.dts | 24 +++++++++++++++++++ - 1 file changed, 24 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -index d911a9a4f0f0..b275b4790211 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -@@ -21,6 +21,9 @@ / { - aliases { - mmc0 = &sdmmc; - mmc1 = &sdhci; -+ spi1 = &spi1; -+ spi2 = &spi2; -+ spi5 = &spi5; - }; - - avdd_0v9_s0: avdd-0v9-s0 { -@@ -473,6 +476,27 @@ &sdmmc { - status = "okay"; - }; - -+&spi1 { -+ status = "okay"; -+ -+ spiflash: flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0x0>; -+ spi-max-frequency = <25000000>; -+ status = "okay"; -+ m25p,fast-read; -+ }; -+}; -+ -+/* UEXT connector */ -+&spi2 { -+ status = "okay"; -+}; -+ -+&spi5 { -+ status = "okay"; -+}; -+ - &tcphy1 { - /* phy for &usbdrd_dwc3_1 */ - status = "okay"; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Dennis Gilmore -Date: Wed, 14 Jul 2021 21:56:31 -0500 -Subject: [PATCH] arm64: dts: rockchip: enable tsadc on helios64 - -Enable the tsadc thermal controller on the helios64 - -Signed-off-by: Dennis Gilmore -Link: https://lore.kernel.org/r/20210715025635.70452-4-dgilmore@redhat.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -index b275b4790211..63c7681843da 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts -@@ -502,6 +502,14 @@ &tcphy1 { - status = "okay"; - }; - -+&tsadc { -+ /* tshut mode 0:CRU 1:GPIO */ -+ rockchip,hw-tshut-mode = <1>; -+ /* tshut polarity 0:LOW 1:HIGH */ -+ rockchip,hw-tshut-polarity = <1>; -+ status = "okay"; -+}; -+ - &u2phy1 { - status = "okay"; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Simon Xue -Date: Mon, 5 Jul 2021 09:26:10 +0800 -Subject: [PATCH] arm64: dts: rockchip: add saradc node for rk3568 - -Add the core dt-node for the rk3568's saradc. - -Signed-off-by: Simon Xue -Link: https://lore.kernel.org/r/20210705012610.3831-1-xxm@rock-chips.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -index 618849186c39..11825909c5db 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi -@@ -754,6 +754,18 @@ uart9: serial@fe6d0000 { - status = "disabled"; - }; - -+ saradc: saradc@fe720000 { -+ compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; -+ reg = <0x0 0xfe720000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; -+ clock-names = "saradc", "apb_pclk"; -+ resets = <&cru SRST_P_SARADC>; -+ reset-names = "saradc-apb"; -+ #io-channel-cells = <1>; -+ status = "disabled"; -+ }; -+ - pinctrl: pinctrl { - compatible = "rockchip,rk3568-pinctrl"; - rockchip,grf = <&grf>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Fri, 18 Jun 2021 20:12:52 +0200 -Subject: [PATCH] dt-bindings: Add doc for ROCK Pi 4 A+ and B+ - -ROCK Pi 4 got 2 more variants called A+ and B+. -Add the dt-bindings documentation for it. - -Signed-off-by: Alex Bee -Acked-by: Rob Herring -Link: https://lore.kernel.org/r/20210618181256.27992-2-knaerzche@gmail.com -Signed-off-by: Heiko Stuebner ---- - Documentation/devicetree/bindings/arm/rockchip.yaml | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index ce7785fe3598..f051e3330302 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -471,11 +471,13 @@ properties: - - const: radxa,rock - - const: rockchip,rk3188 - -- - description: Radxa ROCK Pi 4A/B/C -+ - description: Radxa ROCK Pi 4A/A+/B/B+/C - items: - - enum: - - radxa,rockpi4a -+ - radxa,rockpi4a-plus - - radxa,rockpi4b -+ - radxa,rockpi4b-plus - - radxa,rockpi4c - - const: radxa,rockpi4 - - const: rockchip,rk3399 - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Fri, 18 Jun 2021 20:12:53 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add RK3399 ROCK Pi 4A+ board - -ROCK Pi 4A+ board is the successor of ROCK Pi 4A board. - -Differences to the original version are -- has RK3399 OP1 SoC revision -- has eMMC (16 or 32 GB) soldered on board (no changes required, - since it is enabled in rk3399-rock-pi-4.dtsi) -- dev boards have SPI flash soldered, but as per manufacturer response, - this won't be the case for mass production boards - -Signed-off-by: Alex Bee -Link: https://lore.kernel.org/r/20210618181256.27992-3-knaerzche@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts | 14 ++++++++++++++ - 2 files changed, 15 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index 2890756c294c..5e2e852c5f69 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -45,6 +45,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts -new file mode 100644 -index 000000000000..281a04b2f5e9 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts -@@ -0,0 +1,14 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2019 Akash Gajjar -+ * Copyright (c) 2019 Pragnesh Patel -+ */ -+ -+/dts-v1/; -+#include "rk3399-rock-pi-4.dtsi" -+#include "rk3399-op1-opp.dtsi" -+ -+/ { -+ model = "Radxa ROCK Pi 4A+"; -+ compatible = "radxa,rockpi4a-plus", "radxa,rockpi4", "rockchip,rk3399"; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Fri, 18 Jun 2021 20:12:54 +0200 -Subject: [PATCH] arm64: dts: rockchip: Add RK3399 ROCK Pi 4B+ board - -ROCK Pi 4B+ board is the successor of ROCK Pi 4B board. - -Differences to the original version are -- has RK3399 OP1 SoC revision -- has eMMC (16 or 32 GB) soldered on board (no changes required, - since it is enabled in rk3399-rock-pi-4.dtsi) -- dev boards have SPI flash soldered, but as per manufacturer response, - this won't be the case for mass production boards - -Signed-off-by: Alex Bee -Link: https://lore.kernel.org/r/20210618181256.27992-4-knaerzche@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/Makefile | 1 + - .../dts/rockchip/rk3399-rock-pi-4b-plus.dts | 47 +++++++++++++++++++ - 2 files changed, 48 insertions(+) - create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts - -diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile -index 5e2e852c5f69..b1c3f32ac11a 100644 ---- a/arch/arm64/boot/dts/rockchip/Makefile -+++ b/arch/arm64/boot/dts/rockchip/Makefile -@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb -+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b-plus.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2.dtb -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts -new file mode 100644 -index 000000000000..dfad13d2ab24 ---- /dev/null -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts -@@ -0,0 +1,47 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2019 Akash Gajjar -+ * Copyright (c) 2019 Pragnesh Patel -+ */ -+ -+/dts-v1/; -+#include "rk3399-rock-pi-4.dtsi" -+#include "rk3399-op1-opp.dtsi" -+ -+/ { -+ model = "Radxa ROCK Pi 4B+"; -+ compatible = "radxa,rockpi4b-plus", "radxa,rockpi4", "rockchip,rk3399"; -+ -+ aliases { -+ mmc2 = &sdio0; -+ }; -+}; -+ -+&sdio0 { -+ status = "okay"; -+ -+ brcmf: wifi@1 { -+ compatible = "brcm,bcm4329-fmac"; -+ reg = <1>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ interrupt-names = "host-wake"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_host_wake_l>; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm43438-bt"; -+ clocks = <&rk808 1>; -+ clock-names = "ext_clock"; -+ device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; -+ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; -+ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; -+ }; -+}; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Fri, 18 Jun 2021 20:12:55 +0200 -Subject: [PATCH] arm64: dts: rockchip: add ES8316 codec for ROCK Pi 4 - -ROCK Pi 4 boards have the codec connected to i2s0 and it is accessible -via i2c1 address 0x11. -Add an audio-graph-card for it. - -Signed-off-by: Alex Bee -Link: https://lore.kernel.org/r/20210618181256.27992-5-knaerzche@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 28 +++++++++++++++++++ - 1 file changed, 28 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -index b28888ea9262..b49072af4014 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -36,6 +36,12 @@ sdio_pwrseq: sdio-pwrseq { - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - -+ sound { -+ compatible = "audio-graph-card"; -+ label = "Analog"; -+ dais = <&i2s0_p0>; -+ }; -+ - vcc12v_dcin: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; -@@ -422,6 +428,20 @@ &i2c1 { - i2c-scl-rising-time-ns = <300>; - i2c-scl-falling-time-ns = <15>; - status = "okay"; -+ -+ es8316: codec@11 { -+ compatible = "everest,es8316"; -+ reg = <0x11>; -+ clocks = <&cru SCLK_I2S_8CH_OUT>; -+ clock-names = "mclk"; -+ #sound-dai-cells = <0>; -+ -+ port { -+ es8316_p0_0: endpoint { -+ remote-endpoint = <&i2s0_p0_0>; -+ }; -+ }; -+ }; - }; - - &i2c3 { -@@ -441,6 +461,14 @@ &i2s0 { - rockchip,capture-channels = <2>; - rockchip,playback-channels = <2>; - status = "okay"; -+ -+ i2s0_p0: port { -+ i2s0_p0_0: endpoint { -+ dai-format = "i2s"; -+ mclk-fs = <256>; -+ remote-endpoint = <&es8316_p0_0>; -+ }; -+ }; - }; - - &i2s1 { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Fri, 18 Jun 2021 20:12:56 +0200 -Subject: [PATCH] arm64: dts: rockchip: add SPDIF node for ROCK Pi 4 - -Add a SPDIF audio-graph-card to ROCK Pi 4 device tree. - -It's not enabled by default since all dma channels are used by -the (already) enabled i2s0/1/2 and the pin is muxed with GPIO4_C5 -which might be in use already. -If enabled SPDIF_TX will be available at pin #15. - -Signed-off-by: Alex Bee -Link: https://lore.kernel.org/r/20210618181256.27992-6-knaerzche@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 26 +++++++++++++++++++ - 1 file changed, 26 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -index b49072af4014..98136c88fa49 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -42,6 +42,23 @@ sound { - dais = <&i2s0_p0>; - }; - -+ sound-dit { -+ compatible = "audio-graph-card"; -+ label = "SPDIF"; -+ dais = <&spdif_p0>; -+ }; -+ -+ spdif-dit { -+ compatible = "linux,spdif-dit"; -+ #sound-dai-cells = <0>; -+ -+ port { -+ dit_p0_0: endpoint { -+ remote-endpoint = <&spdif_p0_0>; -+ }; -+ }; -+ }; -+ - vcc12v_dcin: dc-12v { - compatible = "regulator-fixed"; - regulator-name = "vcc12v_dcin"; -@@ -631,6 +648,15 @@ &sdhci { - status = "okay"; - }; - -+&spdif { -+ -+ spdif_p0: port { -+ spdif_p0_0: endpoint { -+ remote-endpoint = <&dit_p0_0>; -+ }; -+ }; -+}; -+ - &tcphy0 { - status = "okay"; - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Thu, 22 Jul 2021 09:39:55 +0200 -Subject: [PATCH] arm64: dts: rockchip: add csi-dphy to px30 - -Add the CSI dphy node to the core px30 devicetree for later use -with the rkisp. - -Signed-off-by: Heiko Stuebner -Link: https://lore.kernel.org/r/20210722073955.1192168-1-heiko@sntech.de -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/px30.dtsi | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi -index 248ebb61aa79..6e53a4cc75e6 100644 ---- a/arch/arm64/boot/dts/rockchip/px30.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi -@@ -864,6 +864,19 @@ dsi_dphy: phy@ff2e0000 { - status = "disabled"; - }; - -+ csi_dphy: phy@ff2f0000 { -+ compatible = "rockchip,px30-csi-dphy"; -+ reg = <0x0 0xff2f0000 0x0 0x4000>; -+ clocks = <&cru PCLK_MIPICSIPHY>; -+ clock-names = "pclk"; -+ #phy-cells = <0>; -+ power-domains = <&power PX30_PD_VI>; -+ resets = <&cru SRST_MIPICSIPHY_P>; -+ reset-names = "apb"; -+ rockchip,grf = <&grf>; -+ status = "disabled"; -+ }; -+ - usb20_otg: usb@ff300000 { - compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Wed, 10 Feb 2021 12:10:18 +0100 -Subject: [PATCH] arm64: dts: rockchip: add #phy-cells to mipi-dsi1 on rk3399 - -The dsi controller includes access to the dphy which might be used -not only for dsi output but also for csi input on dsi1, so add the -necessary #phy-cells to allow it to be used as phy. - -Signed-off-by: Heiko Stuebner -Tested-by: Sebastian Fricke -Acked-by: Helen Koike -Link: https://lore.kernel.org/r/20210210111020.2476369-5-heiko@sntech.de -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index aa5d7dca3432..8d68775365a3 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1870,6 +1870,7 @@ mipi_dsi1: mipi@ff968000 { - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; -+ #phy-cells = <0>; - status = "disabled"; - - ports { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Wed, 10 Feb 2021 12:10:19 +0100 -Subject: [PATCH] arm64: dts: rockchip: add cif clk-control pinctrl for rk3399 - -This enables variant a of the clkout signal for camera applications -and also the cifclkin pinctrl setting. - -Signed-off-by: Heiko Stuebner -Tested-by: Sebastian Fricke -Acked-by: Helen Koike -Link: https://lore.kernel.org/r/20210210111020.2476369-6-heiko@sntech.de -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 8d68775365a3..493042bc20c0 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -2107,6 +2107,18 @@ clk_32k: clk-32k { - }; - }; - -+ cif { -+ cif_clkin: cif-clkin { -+ rockchip,pins = -+ <2 RK_PB2 3 &pcfg_pull_none>; -+ }; -+ -+ cif_clkouta: cif-clkouta { -+ rockchip,pins = -+ <2 RK_PB3 3 &pcfg_pull_none>; -+ }; -+ }; -+ - edp { - edp_hpd: edp-hpd { - rockchip,pins = - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Heiko Stuebner -Date: Wed, 10 Feb 2021 12:10:20 +0100 -Subject: [PATCH] arm64: dts: rockchip: add isp1 node on rk3399 - -ISP1 is supplied by the tx1rx1 dphy, that is controlled from -inside the dsi1 controller, so include the necessary phy-link -for it. - -Signed-off-by: Heiko Stuebner -Tested-by: Sebastian Fricke -Acked-by: Helen Koike -Link: https://lore.kernel.org/r/20210210111020.2476369-7-heiko@sntech.de -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26 ++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 493042bc20c0..9db9484ca38f 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1762,6 +1762,32 @@ isp0_mmu: iommu@ff914000 { - rockchip,disable-mmu-reset; - }; - -+ isp1: isp1@ff920000 { -+ compatible = "rockchip,rk3399-cif-isp"; -+ reg = <0x0 0xff920000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cru SCLK_ISP1>, -+ <&cru ACLK_ISP1_WRAPPER>, -+ <&cru HCLK_ISP1_WRAPPER>; -+ clock-names = "isp", "aclk", "hclk"; -+ iommus = <&isp1_mmu>; -+ phys = <&mipi_dsi1>; -+ phy-names = "dphy"; -+ power-domains = <&power RK3399_PD_ISP1>; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ }; -+ - isp1_mmu: iommu@ff924000 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Paul Kocialkowski -Date: Wed, 28 Jul 2021 20:00:40 -0300 -Subject: [PATCH] arm64: dts: rockchip: Add VPU support for the PX30 - -The PX30 has a VPU (both decoder and encoder) with a dedicated IOMMU. -Describe these two entities in device-tree. - -Signed-off-by: Paul Kocialkowski -Signed-off-by: Ezequiel Garcia -Link: https://lore.kernel.org/r/20210728230040.17368-1-ezequiel@collabora.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/px30.dtsi | 22 ++++++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi -index 6e53a4cc75e6..185bcc5c16ac 100644 ---- a/arch/arm64/boot/dts/rockchip/px30.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi -@@ -1037,6 +1037,28 @@ gpu: gpu@ff400000 { - status = "disabled"; - }; - -+ vpu: video-codec@ff442000 { -+ compatible = "rockchip,px30-vpu"; -+ reg = <0x0 0xff442000 0x0 0x800>; -+ interrupts = , -+ ; -+ interrupt-names = "vepu", "vdpu"; -+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; -+ clock-names = "aclk", "hclk"; -+ iommus = <&vpu_mmu>; -+ power-domains = <&power PX30_PD_VPU>; -+ }; -+ -+ vpu_mmu: iommu@ff442800 { -+ compatible = "rockchip,iommu"; -+ reg = <0x0 0xff442800 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; -+ clock-names = "aclk", "iface"; -+ #iommu-cells = <0>; -+ power-domains = <&power PX30_PD_VPU>; -+ }; -+ - dsi: dsi@ff450000 { - compatible = "rockchip,px30-mipi-dsi"; - reg = <0x0 0xff450000 0x0 0x10000>; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chen-Yu Tsai -Date: Thu, 12 Aug 2021 17:47:52 +0800 -Subject: [PATCH] dt-bindings: arm: rockchip: Add gru-scarlet-dumo board - -Dumo is another variant of Scarlet, also known as the ASUS Chromebook -Tablet CT100. This is almost the same as Scarlet-Innolux, but uses a -specific calibration variant for the WiFi module. - -Add an entry for the board compatibles. - -Signed-off-by: Chen-Yu Tsai -Link: https://lore.kernel.org/r/20210812094753.2359087-2-wenst@chromium.org -Signed-off-by: Heiko Stuebner ---- - .../devicetree/bindings/arm/rockchip.yaml | 28 +++++++++++++++++++ - 1 file changed, 28 insertions(+) - -diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml -index f051e3330302..517f435cbc6e 100644 ---- a/Documentation/devicetree/bindings/arm/rockchip.yaml -+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml -@@ -298,6 +298,34 @@ properties: - - const: google,veyron - - const: rockchip,rk3288 - -+ - description: Google Scarlet - Dumo (ASUS Chromebook Tablet CT100) -+ items: -+ - const: google,scarlet-rev15-sku0 -+ - const: google,scarlet-rev15 -+ - const: google,scarlet-rev14-sku0 -+ - const: google,scarlet-rev14 -+ - const: google,scarlet-rev13-sku0 -+ - const: google,scarlet-rev13 -+ - const: google,scarlet-rev12-sku0 -+ - const: google,scarlet-rev12 -+ - const: google,scarlet-rev11-sku0 -+ - const: google,scarlet-rev11 -+ - const: google,scarlet-rev10-sku0 -+ - const: google,scarlet-rev10 -+ - const: google,scarlet-rev9-sku0 -+ - const: google,scarlet-rev9 -+ - const: google,scarlet-rev8-sku0 -+ - const: google,scarlet-rev8 -+ - const: google,scarlet-rev7-sku0 -+ - const: google,scarlet-rev7 -+ - const: google,scarlet-rev6-sku0 -+ - const: google,scarlet-rev6 -+ - const: google,scarlet-rev5-sku0 -+ - const: google,scarlet-rev5 -+ - const: google,scarlet -+ - const: google,gru -+ - const: rockchip,rk3399 -+ - - description: Google Scarlet - Kingdisplay (Acer Chromebook Tab 10) - items: - - const: google,scarlet-rev15-sku7 - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Dan Johansen -Date: Fri, 6 Aug 2021 00:04:27 +0200 -Subject: [PATCH] arm64: dts: rockchip: Setup USB typec port as datarole on for - Pinebook Pro - -Some chargers try to put the charged device into device data -role. Before this commit this condition caused the tcpm state machine to -issue a hard reset due to a capability missmatch. - -Signed-off-by: Dan Johansen -Link: https://lore.kernel.org/r/20210805220426.2693062-1-strit@manjaro.org -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts -index 9e5d07f5712e..dae8c252bc2b 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts -@@ -707,7 +707,7 @@ fusb0: fusb30x@22 { - - connector { - compatible = "usb-c-connector"; -- data-role = "host"; -+ data-role = "dual"; - label = "USB-C"; - op-sink-microwatt = <1000000>; - power-role = "dual"; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Fri, 30 Jul 2021 11:17:27 -0400 -Subject: [PATCH] arm64: dts: rockchip: add thermal fan control to rockpro64 - -The rockpro64 had a fan node since -commit 5882d65c1691 ("arm64: dts: rockchip: Add PWM fan for RockPro64") -however it was never tied into the thermal driver for automatic control. - -Add the links to the thermal node to permit the kernel to handle this -automatically. -Borrowed from the (rk3399-khadas-edge.dtsi). - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20210730151727.729822-1-pgwipeout@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3399-rockpro64.dtsi | 29 +++++++++++++++++++ - 1 file changed, 29 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -index 6bff8db7d33e..83db4ca67334 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -@@ -69,6 +69,7 @@ diy_led: led-1 { - - fan: pwm-fan { - compatible = "pwm-fan"; -+ cooling-levels = <0 100 150 200 255>; - #cooling-cells = <2>; - fan-supply = <&vcc12v_dcin>; - pwms = <&pwm1 0 50000 0>; -@@ -245,6 +246,34 @@ &cpu_b1 { - cpu-supply = <&vdd_cpu_b>; - }; - -+&cpu_thermal { -+ trips { -+ cpu_warm: cpu_warm { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_hot: cpu_hot { -+ temperature = <65000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map2 { -+ trip = <&cpu_warm>; -+ cooling-device = <&fan THERMAL_NO_LIMIT 1>; -+ }; -+ -+ map3 { -+ trip = <&cpu_hot>; -+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; -+ }; -+ }; -+}; -+ - &emmc_phy { - status = "okay"; - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chris Morgan -Date: Thu, 12 Aug 2021 21:45:43 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add SFC to PX30 - -Add a devicetree entry for the Rockchip SFC for the PX30 SOC. - -Signed-off-by: Chris Morgan -Signed-off-by: Jon Lin -Link: https://lore.kernel.org/r/20210812134546.31340-4-jon.lin@rock-chips.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/px30.dtsi | 38 ++++++++++++++++++++++++++ - 1 file changed, 38 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi -index 185bcc5c16ac..64f643145688 100644 ---- a/arch/arm64/boot/dts/rockchip/px30.dtsi -+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi -@@ -987,6 +987,18 @@ emmc: mmc@ff390000 { - status = "disabled"; - }; - -+ sfc: spi@ff3a0000 { -+ compatible = "rockchip,sfc"; -+ reg = <0x0 0xff3a0000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; -+ clock-names = "clk_sfc", "hclk_sfc"; -+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; -+ pinctrl-names = "default"; -+ power-domains = <&power PX30_PD_MMC_NAND>; -+ status = "disabled"; -+ }; -+ - nfc: nand-controller@ff3b0000 { - compatible = "rockchip,px30-nfc"; - reg = <0x0 0xff3b0000 0x0 0x4000>; -@@ -2008,6 +2020,32 @@ flash_bus8: flash-bus8 { - }; - }; - -+ sfc { -+ sfc_bus4: sfc-bus4 { -+ rockchip,pins = -+ <1 RK_PA0 3 &pcfg_pull_none>, -+ <1 RK_PA1 3 &pcfg_pull_none>, -+ <1 RK_PA2 3 &pcfg_pull_none>, -+ <1 RK_PA3 3 &pcfg_pull_none>; -+ }; -+ -+ sfc_bus2: sfc-bus2 { -+ rockchip,pins = -+ <1 RK_PA0 3 &pcfg_pull_none>, -+ <1 RK_PA1 3 &pcfg_pull_none>; -+ }; -+ -+ sfc_cs0: sfc-cs0 { -+ rockchip,pins = -+ <1 RK_PA4 3 &pcfg_pull_none>; -+ }; -+ -+ sfc_clk: sfc-clk { -+ rockchip,pins = -+ <1 RK_PB1 3 &pcfg_pull_none>; -+ }; -+ }; -+ - lcdc { - lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { - rockchip,pins = - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chris Morgan -Date: Thu, 12 Aug 2021 21:46:38 +0800 -Subject: [PATCH] arm64: dts: rockchip: Add SFC to RK3308 - -Add a devicetree entry for the Rockchip SFC for the RK3308 SOC. - -Signed-off-by: Chris Morgan -Signed-off-by: Jon Lin -Link: https://lore.kernel.org/r/20210812134639.31586-1-jon.lin@rock-chips.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3308.dtsi | 37 ++++++++++++++++++++++++ - 1 file changed, 37 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -index a185901aba9a..ce6f4a28d169 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi -@@ -731,6 +731,17 @@ gmac: ethernet@ff4e0000 { - status = "disabled"; - }; - -+ sfc: spi@ff4c0000 { -+ compatible = "rockchip,sfc"; -+ reg = <0x0 0xff4c0000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; -+ clock-names = "clk_sfc", "hclk_sfc"; -+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; -+ pinctrl-names = "default"; -+ status = "disabled"; -+ }; -+ - cru: clock-controller@ff500000 { - compatible = "rockchip,rk3308-cru"; - reg = <0x0 0xff500000 0x0 0x1000>; -@@ -1004,6 +1015,32 @@ flash_bus8: flash-bus8 { - }; - }; - -+ sfc { -+ sfc_bus4: sfc-bus4 { -+ rockchip,pins = -+ <3 RK_PA0 3 &pcfg_pull_none>, -+ <3 RK_PA1 3 &pcfg_pull_none>, -+ <3 RK_PA2 3 &pcfg_pull_none>, -+ <3 RK_PA3 3 &pcfg_pull_none>; -+ }; -+ -+ sfc_bus2: sfc-bus2 { -+ rockchip,pins = -+ <3 RK_PA0 3 &pcfg_pull_none>, -+ <3 RK_PA1 3 &pcfg_pull_none>; -+ }; -+ -+ sfc_cs0: sfc-cs0 { -+ rockchip,pins = -+ <3 RK_PA4 3 &pcfg_pull_none>; -+ }; -+ -+ sfc_clk: sfc-clk { -+ rockchip,pins = -+ <3 RK_PA5 3 &pcfg_pull_none>; -+ }; -+ }; -+ - gmac { - rmii_pins: rmii-pins { - rockchip,pins = - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Chris Morgan -Date: Thu, 12 Aug 2021 21:46:39 +0800 -Subject: [PATCH] arm64: dts: rockchip: Enable SFC for Odroid Go Advance - -This enables the Rockchip Serial Flash Controller for the Odroid Go -Advance. Note that while the attached SPI NOR flash and the controller -both support quad read mode, only 2 of the required 4 pins are present. -The rx bus width is set to 2 for this reason, and tx bus width is set -to 1 for compatibility reasons. - -Signed-off-by: Chris Morgan -Signed-off-by: Jon Lin -Link: https://lore.kernel.org/r/20210812134639.31586-2-jon.lin@rock-chips.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3326-odroid-go2.dts | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts -index 7fc674a99a6c..35218c2771a2 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts -@@ -517,6 +517,22 @@ &sdmmc { - status = "okay"; - }; - -+&sfc { -+ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <108000000>; -+ spi-rx-bus-width = <2>; -+ spi-tx-bus-width = <1>; -+ }; -+}; -+ - &tsadc { - status = "okay"; - }; - -From 6594988fd625ff0d9a8f90f1788e16185358a3e6 Mon Sep 17 00:00:00 2001 -From: Martin Blumenstingl -Date: Sat, 16 Oct 2021 12:50:22 +0200 -Subject: clk: composite: Use rate_ops.determine_rate when also a mux is - available - -Update clk_composite_determine_rate() to use rate_ops.determine_rate -when available in combination with a mux. So far clk_divider_ops provide -both, .round_rate and .determine_rate. Removing the former would make -clk-composite fail silently for example on Rockchip platforms (which -heavily use composite clocks). -Add support for using rate_ops.determine_rate when either -rate_ops.round_rate is not available or both (.round_rate and -.determine_rate) are provided. - -Suggested-by: Alex Bee -Signed-off-by: Martin Blumenstingl -Link: https://lore.kernel.org/r/20211016105022.303413-3-martin.blumenstingl@googlemail.com -Tested-by: Alex Bee -Tested-by: Chen-Yu Tsai -Signed-off-by: Stephen Boyd ---- - drivers/clk/clk-composite.c | 68 ++++++++++++++++++++++++++++++++------------- - 1 file changed, 48 insertions(+), 20 deletions(-) - -diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c -index 510a9965633bb..075c7f2a7ec4d 100644 ---- a/drivers/clk/clk-composite.c -+++ b/drivers/clk/clk-composite.c -@@ -42,6 +42,29 @@ static unsigned long clk_composite_recalc_rate(struct clk_hw *hw, - return rate_ops->recalc_rate(rate_hw, parent_rate); - } - -+static int clk_composite_determine_rate_for_parent(struct clk_hw *rate_hw, -+ struct clk_rate_request *req, -+ struct clk_hw *parent_hw, -+ const struct clk_ops *rate_ops) -+{ -+ long rate; -+ -+ req->best_parent_hw = parent_hw; -+ req->best_parent_rate = clk_hw_get_rate(parent_hw); -+ -+ if (rate_ops->determine_rate) -+ return rate_ops->determine_rate(rate_hw, req); -+ -+ rate = rate_ops->round_rate(rate_hw, req->rate, -+ &req->best_parent_rate); -+ if (rate < 0) -+ return rate; -+ -+ req->rate = rate; -+ -+ return 0; -+} -+ - static int clk_composite_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) - { -@@ -51,51 +74,56 @@ static int clk_composite_determine_rate(struct clk_hw *hw, - struct clk_hw *rate_hw = composite->rate_hw; - struct clk_hw *mux_hw = composite->mux_hw; - struct clk_hw *parent; -- unsigned long parent_rate; -- long tmp_rate, best_rate = 0; - unsigned long rate_diff; - unsigned long best_rate_diff = ULONG_MAX; -- long rate; -- int i; -+ unsigned long best_rate = 0; -+ int i, ret; - -- if (rate_hw && rate_ops && rate_ops->round_rate && -+ if (rate_hw && rate_ops && -+ (rate_ops->determine_rate || rate_ops->round_rate) && - mux_hw && mux_ops && mux_ops->set_parent) { - req->best_parent_hw = NULL; - - if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) { -+ struct clk_rate_request tmp_req = *req; -+ - parent = clk_hw_get_parent(mux_hw); -- req->best_parent_hw = parent; -- req->best_parent_rate = clk_hw_get_rate(parent); - -- rate = rate_ops->round_rate(rate_hw, req->rate, -- &req->best_parent_rate); -- if (rate < 0) -- return rate; -+ ret = clk_composite_determine_rate_for_parent(rate_hw, -+ &tmp_req, -+ parent, -+ rate_ops); -+ if (ret) -+ return ret; -+ -+ req->rate = tmp_req.rate; -+ req->best_parent_rate = tmp_req.best_parent_rate; - -- req->rate = rate; - return 0; - } - - for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) { -+ struct clk_rate_request tmp_req = *req; -+ - parent = clk_hw_get_parent_by_index(mux_hw, i); - if (!parent) - continue; - -- parent_rate = clk_hw_get_rate(parent); -- -- tmp_rate = rate_ops->round_rate(rate_hw, req->rate, -- &parent_rate); -- if (tmp_rate < 0) -+ ret = clk_composite_determine_rate_for_parent(rate_hw, -+ &tmp_req, -+ parent, -+ rate_ops); -+ if (ret) - continue; - -- rate_diff = abs(req->rate - tmp_rate); -+ rate_diff = abs(req->rate - tmp_req.rate); - - if (!rate_diff || !req->best_parent_hw - || best_rate_diff > rate_diff) { - req->best_parent_hw = parent; -- req->best_parent_rate = parent_rate; -+ req->best_parent_rate = tmp_req.best_parent_rate; - best_rate_diff = rate_diff; -- best_rate = tmp_rate; -+ best_rate = tmp_req.rate; - } - - if (!rate_diff) diff --git a/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch index 26a7ae18c1..77bf1119bb 100644 --- a/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch @@ -377,33 +377,6 @@ index df46edbec82c..cfc57be009a6 100644 }; -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 21 Aug 2021 19:13:31 +0200 -Subject: [PATCH] Commit a728c10dd62a ("arm64: dts: rockchip: remove - interrupt-names from iommu nodes") intended to remove the interrupt-names - property for the mmu nodes. It also removed them for the vpu node in - rk3399.dtsi which currently results in a non-working driver. Fix this by - re-adding them. - -Fixes: a728c10dd62a ("arm64: dts: rockchip: remove interrupt-names from iommu nodes") -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 9db9484ca38f..44def886b391 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1240,6 +1240,7 @@ vpu: video-codec@ff650000 { - reg = <0x0 0xff650000 0x0 0x800>; - interrupts = , - ; -+ interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Wed, 27 Oct 2021 14:43:40 +0200 diff --git a/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch index 85407b59c0..5dd82e3546 100644 --- a/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch @@ -340,16 +340,16 @@ index 05d5db3d85e5..fe43d785414c 100644 case V4L2_PIX_FMT_NV42: descr = "Y/CrCb 4:4:4"; break; + case V4L2_PIX_FMT_NV15: descr = "10-bit Y/CbCr 4:2:0 (Packed)"; break; + case V4L2_PIX_FMT_NV20: descr = "10-bit Y/CbCr 4:2:2 (Packed)"; break; - case V4L2_PIX_FMT_NV12M: descr = "Y/CbCr 4:2:0 (N-C)"; break; - case V4L2_PIX_FMT_NV21M: descr = "Y/CrCb 4:2:0 (N-C)"; break; - case V4L2_PIX_FMT_NV16M: descr = "Y/CbCr 4:2:2 (N-C)"; break; + case V4L2_PIX_FMT_NV12_4L4: descr = "Y/CbCr 4:2:0 (4x4 Linear)"; break; + case V4L2_PIX_FMT_NV12_16L16: descr = "Y/CbCr 4:2:0 (16x16 Linear)"; break; + case V4L2_PIX_FMT_NV12_32L32: descr = "Y/CbCr 4:2:0 (32x32 Linear)"; break; diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index 9260791b8438..169f8ad6fade 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -603,6 +603,9 @@ struct v4l2_pix_format { + #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */ - #define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */ +#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */ +#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/CbCr 4:2:2 10-bit packed */ diff --git a/projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch index 17d13f171f..a2f8d5a719 100644 --- a/projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch @@ -529,31 +529,3 @@ index 5a70a56cd406..47c1861eece0 100644 rockchip_gem_create_object(struct drm_device *drm, unsigned int size, bool alloc_kmap); -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andy Yan -Date: Sun, 27 Jun 2021 16:47:37 +0800 -Subject: [PATCH] drm/rockchip: Check iommu itself instead of it's parent for - device_is_available - -When iommu itself is disabled in dts, we should -fallback to non-iommu buffer, check iommu parent -is meanless here. - -Signed-off-by: Andy Yan ---- - drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -index 2e3ab573a817..8161540be6c8 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -367,7 +367,7 @@ static int rockchip_drm_platform_of_probe(struct device *dev) - } - - iommu = of_parse_phandle(port->parent, "iommus", 0); -- if (!iommu || !of_device_is_available(iommu->parent)) { -+ if (!iommu || !of_device_is_available(iommu)) { - DRM_DEV_DEBUG(dev, - "no iommu attached for %pOF, using non-iommu buffers\n", - port->parent); diff --git a/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch b/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch index e60383eaf2..dcf2fd5b8b 100644 --- a/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch +++ b/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch @@ -1,194 +1,3 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Benjamin Gaignard -Date: Thu, 15 Jul 2021 17:12:22 +0200 -Subject: [PATCH] media: hevc: Add scaling matrix control - -HEVC scaling lists are used for the scaling process for transform -coefficients. -V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED has to set when they are -encoded in the bitstream. - -Signed-off-by: Benjamin Gaignard -Reviewed-by: Jernej Skrabec -Reviewed-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../media/v4l/ext-ctrls-codec.rst | 57 +++++++++++++++++++ - .../media/v4l/vidioc-queryctrl.rst | 6 ++ - drivers/media/v4l2-core/v4l2-ctrls-core.c | 6 ++ - drivers/media/v4l2-core/v4l2-ctrls-defs.c | 4 ++ - include/media/hevc-ctrls.h | 11 ++++ - 5 files changed, 84 insertions(+) - -diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -index 5dd4afc5f1fe..dc08368d62fe 100644 ---- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -@@ -3068,6 +3068,63 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - - - \normalsize - -+``V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (struct)`` -+ Specifies the HEVC scaling matrix parameters used for the scaling process -+ for transform coefficients. -+ These matrix and parameters are defined according to :ref:`hevc`. -+ They are described in section 7.4.5 "Scaling list data semantics" of -+ the specification. -+ -+.. c:type:: v4l2_ctrl_hevc_scaling_matrix -+ -+.. raw:: latex -+ -+ \scriptsize -+ -+.. tabularcolumns:: |p{5.4cm}|p{6.8cm}|p{5.1cm}| -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_hevc_scaling_matrix -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``scaling_list_4x4[6][16]`` -+ - Scaling list is used for the scaling process for transform -+ coefficients. The values on each scaling list are expected -+ in raster scan order. -+ * - __u8 -+ - ``scaling_list_8x8[6][64]`` -+ - Scaling list is used for the scaling process for transform -+ coefficients. The values on each scaling list are expected -+ in raster scan order. -+ * - __u8 -+ - ``scaling_list_16x16[6][64]`` -+ - Scaling list is used for the scaling process for transform -+ coefficients. The values on each scaling list are expected -+ in raster scan order. -+ * - __u8 -+ - ``scaling_list_32x32[2][64]`` -+ - Scaling list is used for the scaling process for transform -+ coefficients. The values on each scaling list are expected -+ in raster scan order. -+ * - __u8 -+ - ``scaling_list_dc_coef_16x16[6]`` -+ - Scaling list is used for the scaling process for transform -+ coefficients. The values on each scaling list are expected -+ in raster scan order. -+ * - __u8 -+ - ``scaling_list_dc_coef_32x32[2]`` -+ - Scaling list is used for the scaling process for transform -+ coefficients. The values on each scaling list are expected -+ in raster scan order. -+ -+.. raw:: latex -+ -+ \normalsize -+ - .. c:type:: v4l2_hevc_dpb_entry - - .. raw:: latex -diff --git a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst -index f9ecf6276129..2f491c17dd5d 100644 ---- a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst -+++ b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst -@@ -495,6 +495,12 @@ See also the examples in :ref:`control`. - - n/a - - A struct :c:type:`v4l2_ctrl_hevc_slice_params`, containing HEVC - slice parameters for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_hevc_scaling_matrix`, containing HEVC -+ scaling matrix for stateless video decoders. - * - ``V4L2_CTRL_TYPE_VP8_FRAME`` - - n/a - - n/a -diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c -index b4802c9989fd..f557aca9d966 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls-core.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c -@@ -906,6 +906,9 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, - - break; - -+ case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: -+ break; -+ - case V4L2_CTRL_TYPE_AREA: - area = p; - if (!area->width || !area->height) -@@ -1465,6 +1468,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, - case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: - elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params); - break; -+ case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: -+ elem_size = sizeof(struct v4l2_ctrl_hevc_scaling_matrix); -+ break; - case V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS: - elem_size = sizeof(struct v4l2_ctrl_hevc_decode_params); - break; -diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c -index 22a031e25499..bca21812e216 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c -@@ -1001,6 +1001,7 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_MPEG_VIDEO_HEVC_SPS: return "HEVC Sequence Parameter Set"; - case V4L2_CID_MPEG_VIDEO_HEVC_PPS: return "HEVC Picture Parameter Set"; - case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: return "HEVC Slice Parameters"; -+ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: return "HEVC Scaling Matrix"; - case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS: return "HEVC Decode Parameters"; - case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE: return "HEVC Decode Mode"; - case V4L2_CID_MPEG_VIDEO_HEVC_START_CODE: return "HEVC Start Code"; -@@ -1502,6 +1503,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: - *type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS; - break; -+ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: -+ *type = V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX; -+ break; - case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS: - *type = V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS; - break; -diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index 53c0038c792b..0e5c4a2eecff 100644 ---- a/include/media/hevc-ctrls.h -+++ b/include/media/hevc-ctrls.h -@@ -19,6 +19,7 @@ - #define V4L2_CID_MPEG_VIDEO_HEVC_SPS (V4L2_CID_CODEC_BASE + 1008) - #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_CODEC_BASE + 1009) - #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_CODEC_BASE + 1010) -+#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_CODEC_BASE + 1011) - #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS (V4L2_CID_CODEC_BASE + 1012) - #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_CODEC_BASE + 1015) - #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_CODEC_BASE + 1016) -@@ -27,6 +28,7 @@ - #define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 - #define V4L2_CTRL_TYPE_HEVC_PPS 0x0121 - #define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122 -+#define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0123 - #define V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS 0x0124 - - enum v4l2_mpeg_video_hevc_decode_mode { -@@ -224,6 +226,15 @@ struct v4l2_ctrl_hevc_decode_params { - __u64 flags; - }; - -+struct v4l2_ctrl_hevc_scaling_matrix { -+ __u8 scaling_list_4x4[6][16]; -+ __u8 scaling_list_8x8[6][64]; -+ __u8 scaling_list_16x16[6][64]; -+ __u8 scaling_list_32x32[2][64]; -+ __u8 scaling_list_dc_coef_16x16[6]; -+ __u8 scaling_list_dc_coef_32x32[2]; -+}; -+ - /* MPEG-class control IDs specific to the Hantro driver as defined by V4L2 */ - #define V4L2_CID_CODEC_HANTRO_BASE (V4L2_CTRL_CLASS_CODEC | 0x1200) - /* - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 23 May 2020 15:03:46 +0000 @@ -3511,9 +3320,9 @@ index da32a6350344..4fb05e8b5a54 100644 }; MODULE_DEVICE_TABLE(of, of_rkvdec_match); @@ -1218,6 +1255,7 @@ static int rkvdec_probe(struct platform_device *pdev) + static int rkvdec_probe(struct platform_device *pdev) { struct rkvdec_dev *rkvdec; - struct resource *res; + const struct rkvdec_variant *variant; unsigned int i; int ret, irq;