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Merge pull request #5094 from jernejsk/aw-disp-fixes
Allwinner: linux: GPU and HDMI improvements
This commit is contained in:
dhewg
GitHub
commit
624436145d
@ -0,0 +1,57 @@
|
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From: Christian Hewitt <christianshewitt@gmail.com>
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Subject: [PATCH v2] drm/lima: add governor data with pre-defined thresholds
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Date: Wed, 27 Jan 2021 19:40:47 +0000
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This patch adapts the panfrost pre-defined thresholds change [0] to the
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lima driver to improve real-world performance. The upthreshold value has
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been set to ramp GPU frequency to max freq faster (compared to panfrost)
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to compensate for the lower overall performance of utgard devices.
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[0] https://patchwork.kernel.org/project/dri-devel/patch/20210121170445.19761-1-lukasz.luba@arm.com/
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Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
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Reviewed-by: Lukasz Luba <lukasz.luba@arm.com>
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Reviewed-by: Qiang Yu <yuq825@gmail.com>
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---
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drivers/gpu/drm/lima/lima_devfreq.c | 10 +++++++++-
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drivers/gpu/drm/lima/lima_devfreq.h | 2 ++
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2 files changed, 11 insertions(+), 1 deletion(-)
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--- a/drivers/gpu/drm/lima/lima_devfreq.c
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+++ b/drivers/gpu/drm/lima/lima_devfreq.c
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@@ -177,8 +177,16 @@ int lima_devfreq_init(struct lima_device
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lima_devfreq_profile.initial_freq = cur_freq;
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dev_pm_opp_put(opp);
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+ /*
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+ * Setup default thresholds for the simple_ondemand governor.
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+ * The values are chosen based on experiments.
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+ */
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+ ldevfreq->gov_data.upthreshold = 30;
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+ ldevfreq->gov_data.downdifferential = 5;
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+
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devfreq = devm_devfreq_add_device(dev, &lima_devfreq_profile,
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- DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL);
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+ DEVFREQ_GOV_SIMPLE_ONDEMAND,
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+ &ldevfreq->gov_data);
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if (IS_ERR(devfreq)) {
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dev_err(dev, "Couldn't initialize GPU devfreq\n");
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ret = PTR_ERR(devfreq);
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--- a/drivers/gpu/drm/lima/lima_devfreq.h
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+++ b/drivers/gpu/drm/lima/lima_devfreq.h
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@@ -4,6 +4,7 @@
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#ifndef __LIMA_DEVFREQ_H__
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#define __LIMA_DEVFREQ_H__
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+#include <linux/devfreq.h>
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#include <linux/spinlock.h>
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#include <linux/ktime.h>
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@@ -18,6 +19,7 @@ struct lima_devfreq {
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struct opp_table *clkname_opp_table;
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struct opp_table *regulators_opp_table;
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struct thermal_cooling_device *cooling;
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+ struct devfreq_simple_ondemand_data gov_data;
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bool opp_of_table_added;
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ktime_t busy_time;
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@ -0,0 +1,24 @@
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From: Lukasz Luba <lukasz.luba@arm.com>
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Subject: [PATCH] drm/lima: Use delayed timer as default in devfreq profile
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Date: Wed, 27 Jan 2021 10:51:21 +0000
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Devfreq framework supports 2 modes for monitoring devices.
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Use delayed timer as default instead of deferrable timer
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in order to monitor the GPU status regardless of CPU idle.
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Signed-off-by: Lukasz Luba <lukasz.luba@arm.com>
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Reviewed-by: Qiang Yu <yuq825@gmail.com>
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---
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drivers/gpu/drm/lima/lima_devfreq.c | 1 +
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1 file changed, 1 insertion(+)
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--- a/drivers/gpu/drm/lima/lima_devfreq.c
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+++ b/drivers/gpu/drm/lima/lima_devfreq.c
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@@ -86,6 +86,7 @@ static int lima_devfreq_get_dev_status(s
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}
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static struct devfreq_dev_profile lima_devfreq_profile = {
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+ .timer = DEVFREQ_TIMER_DELAYED,
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.polling_ms = 50, /* ~3 frames */
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.target = lima_devfreq_target,
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.get_dev_status = lima_devfreq_get_dev_status,
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@ -0,0 +1,59 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Lukasz Luba <lukasz.luba@arm.com>
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Date: Thu, 21 Jan 2021 17:04:45 +0000
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Subject: [PATCH] drm/panfrost: Add governor data with pre-defined thresholds
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The simple_ondemand devfreq governor uses two thresholds to decide about
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the frequency change: upthreshold, downdifferential. These two tunable
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change the behavior of the governor decision, e.g. how fast to increase
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the frequency or how rapidly limit the frequency. This patch adds needed
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governor data with thresholds values gathered experimentally in different
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workloads.
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Signed-off-by: Lukasz Luba <lukasz.luba@arm.com>
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Reviewed-by: Steven Price <steven.price@arm.com>
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Signed-off-by: Steven Price <steven.price@arm.com>
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Link: https://patchwork.freedesktop.org/patch/msgid/20210121170445.19761-1-lukasz.luba@arm.com
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---
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drivers/gpu/drm/panfrost/panfrost_devfreq.c | 10 +++++++++-
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drivers/gpu/drm/panfrost/panfrost_devfreq.h | 2 ++
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2 files changed, 11 insertions(+), 1 deletion(-)
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--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
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+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
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@@ -134,8 +134,16 @@ int panfrost_devfreq_init(struct panfros
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panfrost_devfreq_profile.initial_freq = cur_freq;
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dev_pm_opp_put(opp);
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+ /*
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+ * Setup default thresholds for the simple_ondemand governor.
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+ * The values are chosen based on experiments.
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+ */
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+ pfdevfreq->gov_data.upthreshold = 45;
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+ pfdevfreq->gov_data.downdifferential = 5;
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+
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devfreq = devm_devfreq_add_device(dev, &panfrost_devfreq_profile,
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- DEVFREQ_GOV_SIMPLE_ONDEMAND, NULL);
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+ DEVFREQ_GOV_SIMPLE_ONDEMAND,
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+ &pfdevfreq->gov_data);
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if (IS_ERR(devfreq)) {
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DRM_DEV_ERROR(dev, "Couldn't initialize GPU devfreq\n");
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ret = PTR_ERR(devfreq);
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--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.h
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+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.h
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@@ -4,6 +4,7 @@
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#ifndef __PANFROST_DEVFREQ_H__
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#define __PANFROST_DEVFREQ_H__
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+#include <linux/devfreq.h>
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#include <linux/spinlock.h>
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#include <linux/ktime.h>
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@@ -17,6 +18,7 @@ struct panfrost_devfreq {
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struct devfreq *devfreq;
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struct opp_table *regulators_opp_table;
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struct thermal_cooling_device *cooling;
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+ struct devfreq_simple_ondemand_data gov_data;
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bool opp_of_table_added;
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ktime_t busy_time;
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@ -0,0 +1,27 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Lukasz Luba <lukasz.luba@arm.com>
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Date: Tue, 5 Jan 2021 16:41:11 +0000
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Subject: [PATCH] drm/panfrost: Use delayed timer as default in devfreq profile
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Devfreq framework supports 2 modes for monitoring devices.
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Use delayed timer as default instead of deferrable timer
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in order to monitor the GPU status regardless of CPU idle.
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Signed-off-by: Lukasz Luba <lukasz.luba@arm.com>
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Reviewed-by: Steven Price <steven.price@arm.com>
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Signed-off-by: Steven Price <steven.price@arm.com>
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Link: https://patchwork.freedesktop.org/patch/msgid/20210105164111.30122-1-lukasz.luba@arm.com
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---
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drivers/gpu/drm/panfrost/panfrost_devfreq.c | 1 +
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1 file changed, 1 insertion(+)
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--- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c
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+++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c
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@@ -81,6 +81,7 @@ static int panfrost_devfreq_get_dev_stat
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}
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static struct devfreq_dev_profile panfrost_devfreq_profile = {
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+ .timer = DEVFREQ_TIMER_DELAYED,
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.polling_ms = 50, /* ~3 frames */
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.target = panfrost_devfreq_target,
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.get_dev_status = panfrost_devfreq_get_dev_status,
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@ -0,0 +1,25 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Wed, 3 Feb 2021 23:09:31 +0100
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Subject: [PATCH] clk: sunxi-ng: mp: fix parent rate change flag check
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CLK_SET_RATE_PARENT flag is checked on parent clock instead of current
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one. Fix that.
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Fixes: 3f790433c3cb ("clk: sunxi-ng: Adjust MP clock parent rate when allowed")
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/clk/sunxi-ng/ccu_mp.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/clk/sunxi-ng/ccu_mp.c
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+++ b/drivers/clk/sunxi-ng/ccu_mp.c
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@@ -108,7 +108,7 @@ static unsigned long ccu_mp_round_rate(s
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max_m = cmp->m.max ?: 1 << cmp->m.width;
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max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
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- if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
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+ if (!(clk_hw_get_flags(&cmp->common.hw) & CLK_SET_RATE_PARENT)) {
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ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
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rate = *parent_rate / p / m;
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} else {
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@ -0,0 +1,84 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Wed, 3 Feb 2021 23:16:42 +0100
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Subject: [PATCH] drm/sun4i: tcon: set sync polarity for tcon1 channel
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Channel 1 has polarity bits for vsync and hsync signals but driver never
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sets them. It turns out that with pre-HDMI2 controllers seemingly there
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is no issue if polarity is not set. However, with HDMI2 controllers
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(H6) there often comes to de-synchronization due to phase shift. This
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causes flickering screen. It's safe to assume that similar issues might
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happen also with pre-HDMI2 controllers.
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Solve issue with setting vsync and hsync polarity. Note that display
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stacks with tcon top have polarity bits actually in tcon0 polarity
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register.
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Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support")
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Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
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---
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drivers/gpu/drm/sun4i/sun4i_tcon.c | 24 ++++++++++++++++++++++++
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drivers/gpu/drm/sun4i/sun4i_tcon.h | 5 +++++
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2 files changed, 29 insertions(+)
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--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
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+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
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@@ -689,6 +689,29 @@ static void sun4i_tcon1_mode_set(struct
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SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
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SUN4I_TCON1_BASIC5_H_SYNC(hsync));
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+ /* Setup the polarity of sync signals */
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+ if (tcon->quirks->polarity_in_ch0) {
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+ val = 0;
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+
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+ if (mode->flags & DRM_MODE_FLAG_PHSYNC)
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+ val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
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+
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+ if (mode->flags & DRM_MODE_FLAG_PVSYNC)
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+ val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
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+
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+ regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
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+ } else {
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+ val = SUN4I_TCON1_IO_POL_UNKNOWN;
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+
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+ if (mode->flags & DRM_MODE_FLAG_PHSYNC)
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+ val |= SUN4I_TCON1_IO_POL_HSYNC_POSITIVE;
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+
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+ if (mode->flags & DRM_MODE_FLAG_PVSYNC)
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+ val |= SUN4I_TCON1_IO_POL_VSYNC_POSITIVE;
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+
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+ regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val);
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+ }
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+
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/* Map output pins to channel 1 */
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regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
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SUN4I_TCON_GCTL_IOMAP_MASK,
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@@ -1517,6 +1540,7 @@ static const struct sun4i_tcon_quirks su
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static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = {
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.has_channel_1 = true,
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+ .polarity_in_ch0 = true,
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.set_mux = sun8i_r40_tcon_tv_set_mux,
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};
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--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
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+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
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@@ -153,6 +153,10 @@
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#define SUN4I_TCON1_BASIC5_V_SYNC(height) (((height) - 1) & 0x3ff)
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#define SUN4I_TCON1_IO_POL_REG 0xf0
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+#define SUN4I_TCON1_IO_POL_UNKNOWN BIT(26)
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+#define SUN4I_TCON1_IO_POL_HSYNC_POSITIVE BIT(25)
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+#define SUN4I_TCON1_IO_POL_VSYNC_POSITIVE BIT(24)
|
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+
|
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#define SUN4I_TCON1_IO_TRI_REG 0xf4
|
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|
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#define SUN4I_TCON_ECC_FIFO_REG 0xf8
|
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@@ -235,6 +239,7 @@ struct sun4i_tcon_quirks {
|
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bool needs_de_be_mux; /* sun6i needs mux to select backend */
|
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bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */
|
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bool supports_lvds; /* Does the TCON support an LVDS output? */
|
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+ bool polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
|
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u8 dclk_min_div; /* minimum divider for TCON0 DCLK */
|
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|
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/* callback to handle tcon muxing options */
|
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@ -0,0 +1,49 @@
|
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
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From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
Date: Wed, 3 Feb 2021 23:25:13 +0100
|
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Subject: [PATCH] drm/sun4i: dw-hdmi: always set clock rate
|
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|
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As expected, HDMI controller clock should always match pixel clock. In
|
||||
the past, changing HDMI controller rate would seemingly worsen
|
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situation. However, that was the result of other bugs which are now
|
||||
fixed.
|
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|
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Fix that by removing set_rate quirk and always set clock rate.
|
||||
|
||||
Fixes: 40bb9d3147b2 ("drm/sun4i: Add support for H6 DW HDMI controller")
|
||||
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
---
|
||||
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 4 +---
|
||||
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 -
|
||||
2 files changed, 1 insertion(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
|
||||
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
|
||||
@@ -21,8 +21,7 @@ static void sun8i_dw_hdmi_encoder_mode_s
|
||||
{
|
||||
struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder);
|
||||
|
||||
- if (hdmi->quirks->set_rate)
|
||||
- clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000);
|
||||
+ clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000);
|
||||
}
|
||||
|
||||
static const struct drm_encoder_helper_funcs
|
||||
@@ -295,7 +294,6 @@ static int sun8i_dw_hdmi_remove(struct p
|
||||
|
||||
static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = {
|
||||
.mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
|
||||
- .set_rate = true,
|
||||
};
|
||||
|
||||
static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = {
|
||||
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
|
||||
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
|
||||
@@ -179,7 +179,6 @@ struct sun8i_dw_hdmi_quirks {
|
||||
enum drm_mode_status (*mode_valid)(struct dw_hdmi *hdmi, void *data,
|
||||
const struct drm_display_info *info,
|
||||
const struct drm_display_mode *mode);
|
||||
- unsigned int set_rate : 1;
|
||||
unsigned int use_drm_infoframe : 1;
|
||||
};
|
||||
|
||||
@ -0,0 +1,24 @@
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
Date: Wed, 3 Feb 2021 23:29:47 +0100
|
||||
Subject: [PATCH] drm/sun4i: Fix H6 HDMI PHY configuration
|
||||
|
||||
cpce value for 594 MHz is set differently in BSP driver. Fix that.
|
||||
|
||||
Fixes: c71c9b2fee17 ("drm/sun4i: Add support for Synopsys HDMI PHY")
|
||||
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
---
|
||||
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
|
||||
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
|
||||
@@ -89,7 +89,7 @@ static const struct dw_hdmi_mpll_config
|
||||
},
|
||||
}, {
|
||||
594000000, {
|
||||
- { 0x1a40, 0x0003 },
|
||||
+ { 0x1a7c, 0x0003 },
|
||||
{ 0x3b4c, 0x0003 },
|
||||
{ 0x5a64, 0x0003 },
|
||||
},
|
||||
@ -0,0 +1,34 @@
|
||||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
Date: Wed, 3 Feb 2021 23:32:16 +0100
|
||||
Subject: [PATCH] drm/sun4i: dw-hdmi: Fix max. frequency for H6
|
||||
|
||||
It turns out that reasoning for lowering max. supported frequency is
|
||||
wrong. Scrambling works just fine. Several now fixed bugs prevented
|
||||
proper functioning, even with rates lower than 340 MHz. Issues were just
|
||||
more pronounced with higher frequencies.
|
||||
|
||||
Fix that by allowing max. supported frequency in HW and fix the comment.
|
||||
|
||||
Fixes: cd9063757a22 ("drm/sun4i: DW HDMI: Lower max. supported rate for H6")
|
||||
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
---
|
||||
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 6 ++----
|
||||
1 file changed, 2 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
|
||||
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
|
||||
@@ -47,11 +47,9 @@ sun8i_dw_hdmi_mode_valid_h6(struct dw_hd
|
||||
{
|
||||
/*
|
||||
* Controller support maximum of 594 MHz, which correlates to
|
||||
- * 4K@60Hz 4:4:4 or RGB. However, for frequencies greater than
|
||||
- * 340 MHz scrambling has to be enabled. Because scrambling is
|
||||
- * not yet implemented, just limit to 340 MHz for now.
|
||||
+ * 4K@60Hz 4:4:4 or RGB.
|
||||
*/
|
||||
- if (mode->clock > 340000)
|
||||
+ if (mode->clock > 594000)
|
||||
return MODE_CLOCK_HIGH;
|
||||
|
||||
return MODE_OK;
|
||||
Loading…
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Reference in New Issue
Block a user