diff --git a/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.15.patch b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.15.patch new file mode 100644 index 0000000000..7a2165e1be --- /dev/null +++ b/projects/Rockchip/patches/linux/default/linux-0001-rockchip-from-5.15.patch @@ -0,0 +1,3414 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Tue, 13 Jul 2021 17:47:13 +0800 +Subject: [PATCH] clk: rockchip: add dt-binding clkid for hclk_sfc on rk3036 + +Add dt-binding for hclk_sfc on rk3036 + +Signed-off-by: Chris Morgan +Signed-off-by: Jon Lin +Acked-by: Stephen Boyd +Link: https://lore.kernel.org/r/20210713094718.1709-1-jon.lin@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + include/dt-bindings/clock/rk3036-cru.h | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/include/dt-bindings/clock/rk3036-cru.h b/include/dt-bindings/clock/rk3036-cru.h +index 35a5a01f9697..a96a9870ad59 100644 +--- a/include/dt-bindings/clock/rk3036-cru.h ++++ b/include/dt-bindings/clock/rk3036-cru.h +@@ -81,6 +81,7 @@ + #define HCLK_OTG0 449 + #define HCLK_OTG1 450 + #define HCLK_NANDC 453 ++#define HCLK_SFC 454 + #define HCLK_SDMMC 456 + #define HCLK_SDIO 457 + #define HCLK_EMMC 459 + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jon Lin +Date: Tue, 13 Jul 2021 17:44:50 +0800 +Subject: [PATCH] clk: rockchip: rk3036: fix up the sclk_sfc parent error + +Choose the correct pll + +Signed-off-by: Elaine Zhang +Signed-off-by: Jon Lin +Acked-by: Stephen Boyd +Link: https://lore.kernel.org/r/20210713094456.23288-5-jon.lin@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-rk3036.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c +index 614845cc5b4a..c38ad4ec8746 100644 +--- a/drivers/clk/rockchip/clk-rk3036.c ++++ b/drivers/clk/rockchip/clk-rk3036.c +@@ -121,6 +121,7 @@ PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" }; + PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" }; + + PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" }; ++PNAME(mux_pll_src_dmyapll_dpll_gpll_xin24_p) = { "dummy_apll", "dpll", "gpll", "xin24m" }; + + PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" }; + PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" }; +@@ -340,7 +341,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { + RK2928_CLKSEL_CON(16), 8, 2, MFLAGS, 10, 5, DFLAGS, + RK2928_CLKGATE_CON(10), 4, GFLAGS), + +- COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_apll_dpll_gpll_usb480m_p, 0, ++ COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_dmyapll_dpll_gpll_xin24_p, 0, + RK2928_CLKSEL_CON(16), 0, 2, MFLAGS, 2, 5, DFLAGS, + RK2928_CLKGATE_CON(10), 5, GFLAGS), + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jon Lin +Date: Tue, 13 Jul 2021 17:47:14 +0800 +Subject: [PATCH] clk: rockchip: Add support for hclk_sfc on rk3036 + +Add support for the bus clock for the serial flash controller on the +rk3036. Taken from the Rockchip BSP kernel but not tested on real +hardware (as I lack a 3036 based SoC to test). + +Signed-off-by: Chris Morgan +Signed-off-by: Jon Lin +Acked-by: Stephen Boyd +Link: https://lore.kernel.org/r/20210713094718.1709-2-jon.lin@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-rk3036.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c +index c38ad4ec8746..d644bc155ec6 100644 +--- a/drivers/clk/rockchip/clk-rk3036.c ++++ b/drivers/clk/rockchip/clk-rk3036.c +@@ -404,7 +404,7 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = { + GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS), + GATE(HCLK_OTG1, "hclk_otg1", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(7), 3, GFLAGS), + GATE(HCLK_I2S, "hclk_i2s", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS), +- GATE(0, "hclk_sfc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(3), 14, GFLAGS), ++ GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS), + GATE(HCLK_MAC, "hclk_mac", "hclk_peri", 0, RK2928_CLKGATE_CON(3), 5, GFLAGS), + + /* pclk_peri gates */ + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= + +Date: Thu, 10 Jun 2021 14:56:13 -0300 +Subject: [PATCH] dt-bindings: clk: Convert rockchip,rk3399-cru to DT schema +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Convert the rockchip,rk3399-cru binding to DT schema format. +Tested with +ARCH=arm64 make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml +ARCH=arm64 make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml + +Signed-off-by: Nícolas F. R. A. Prado +Reviewed-by: Rob Herring +Link: https://lore.kernel.org/r/20210610175613.167601-1-nfraprado@collabora.com +Signed-off-by: Heiko Stuebner +--- + .../bindings/clock/rockchip,rk3399-cru.txt | 68 -------------- + .../bindings/clock/rockchip,rk3399-cru.yaml | 92 +++++++++++++++++++ + 2 files changed, 92 insertions(+), 68 deletions(-) + delete mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt + create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml + +diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt +deleted file mode 100644 +index 3bc56fae90ac..000000000000 +--- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt ++++ /dev/null +@@ -1,68 +0,0 @@ +-* Rockchip RK3399 Clock and Reset Unit +- +-The RK3399 clock controller generates and supplies clock to various +-controllers within the SoC and also implements a reset controller for SoC +-peripherals. +- +-Required Properties: +- +-- compatible: PMU for CRU should be "rockchip,rk3399-pmucru" +-- compatible: CRU should be "rockchip,rk3399-cru" +-- reg: physical base address of the controller and length of memory mapped +- region. +-- #clock-cells: should be 1. +-- #reset-cells: should be 1. +- +-Optional Properties: +- +-- rockchip,grf: phandle to the syscon managing the "general register files". +- It is used for GRF muxes, if missing any muxes present in the GRF will not +- be available. +- +-Each clock is assigned an identifier and client nodes can use this identifier +-to specify the clock which they consume. All available clocks are defined as +-preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be +-used in device tree sources. Similar macros exist for the reset sources in +-these files. +- +-External clocks: +- +-There are several clocks that are generated outside the SoC. It is expected +-that they are defined using standard clock bindings with following +-clock-output-names: +- - "xin24m" - crystal input - required, +- - "xin32k" - rtc clock - optional, +- - "clkin_gmac" - external GMAC clock - optional, +- - "clkin_i2s" - external I2S clock - optional, +- - "pclkin_cif" - external ISP clock - optional, +- - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 +- - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 +- +-Example: Clock controller node: +- +- pmucru: pmu-clock-controller@ff750000 { +- compatible = "rockchip,rk3399-pmucru"; +- reg = <0x0 0xff750000 0x0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +- cru: clock-controller@ff760000 { +- compatible = "rockchip,rk3399-cru"; +- reg = <0x0 0xff760000 0x0 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; +- +-Example: UART controller node that consumes the clock generated by the clock +- controller: +- +- uart0: serial@ff1a0000 { +- compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; +- reg = <0x0 0xff180000 0x0 0x100>; +- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; +- clock-names = "baudclk", "apb_pclk"; +- interrupts = ; +- reg-shift = <2>; +- reg-io-width = <4>; +- }; +diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml +new file mode 100644 +index 000000000000..72b286a1beba +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml +@@ -0,0 +1,92 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/rockchip,rk3399-cru.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Rockchip RK3399 Clock and Reset Unit ++ ++maintainers: ++ - Xing Zheng ++ - Heiko Stuebner ++ ++description: | ++ The RK3399 clock controller generates and supplies clock to various ++ controllers within the SoC and also implements a reset controller for SoC ++ peripherals. ++ Each clock is assigned an identifier and client nodes can use this identifier ++ to specify the clock which they consume. All available clocks are defined as ++ preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be ++ used in device tree sources. Similar macros exist for the reset sources in ++ these files. ++ There are several clocks that are generated outside the SoC. It is expected ++ that they are defined using standard clock bindings with following ++ clock-output-names: ++ - "xin24m" - crystal input - required, ++ - "xin32k" - rtc clock - optional, ++ - "clkin_gmac" - external GMAC clock - optional, ++ - "clkin_i2s" - external I2S clock - optional, ++ - "pclkin_cif" - external ISP clock - optional, ++ - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 ++ - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 ++ ++properties: ++ compatible: ++ enum: ++ - rockchip,rk3399-pmucru ++ - rockchip,rk3399-cru ++ ++ reg: ++ maxItems: 1 ++ ++ "#clock-cells": ++ const: 1 ++ ++ "#reset-cells": ++ const: 1 ++ ++ clocks: ++ minItems: 1 ++ ++ assigned-clocks: ++ minItems: 1 ++ maxItems: 64 ++ ++ assigned-clock-parents: ++ minItems: 1 ++ maxItems: 64 ++ ++ assigned-clock-rates: ++ minItems: 1 ++ maxItems: 64 ++ ++ rockchip,grf: ++ $ref: /schemas/types.yaml#/definitions/phandle ++ description: > ++ phandle to the syscon managing the "general register files". It is used ++ for GRF muxes, if missing any muxes present in the GRF will not be ++ available. ++ ++required: ++ - compatible ++ - reg ++ - "#clock-cells" ++ - "#reset-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ pmucru: pmu-clock-controller@ff750000 { ++ compatible = "rockchip,rk3399-pmucru"; ++ reg = <0xff750000 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ - | ++ cru: clock-controller@ff760000 { ++ compatible = "rockchip,rk3399-cru"; ++ reg = <0xff760000 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Wed, 28 Jul 2021 14:00:28 -0400 +Subject: [PATCH] clk: rockchip: drop GRF dependency for rk3328/rk3036 pll + types + +The rk3036/rk3328 pll types were converted to checking the lock status +via the internal register in january 2020, so don't need the grf +reference since then. + +But it was forgotten to remove grf check when deciding between the +pll rate ops (read-only vs. read-write), so a clock driver without +the needed grf reference might've been put into the read-only mode +just because the grf reference was missing. + +This affected the rk356x that needs to reclock certain plls at boot. + +Fix this by removing the check for the grf for selecting the utilized +operations. + +Suggested-by: Heiko Stuebner +Fixes: 7f6ffbb885d1 ("clk: rockchip: convert rk3036 pll type to use internal lock status") +Signed-off-by: Peter Geis +[adjusted the commit message, adjusted the fixes tag] +Link: https://lore.kernel.org/r/20210728180034.717953-3-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-pll.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c +index fe937bcdb487..f7827b3b7fc1 100644 +--- a/drivers/clk/rockchip/clk-pll.c ++++ b/drivers/clk/rockchip/clk-pll.c +@@ -940,7 +940,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, + switch (pll_type) { + case pll_rk3036: + case pll_rk3328: +- if (!pll->rate_table || IS_ERR(ctx->grf)) ++ if (!pll->rate_table) + init.ops = &rockchip_rk3036_pll_clk_norate_ops; + else + init.ops = &rockchip_rk3036_pll_clk_ops; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Yunhao Tian +Date: Wed, 21 Jul 2021 20:48:16 +0800 +Subject: [PATCH] clk: rockchip: make rk3308 ddrphy4x clock critical + +Currently, no driver support for DDR memory controller (DMC) is present, +as a result, no driver is explicitly consuming the ddrphy clock. This means +that VPLL1 (parent of ddr clock) will be shutdown if we enable +and then disable any child clock of VPLL1 (e.g. SCLK_I2S0_8CH_TX). +If VPLL1 is disabled, the whole system will freeze, because the DDR +controller will lose its clock. So, it's necessary to prevent VPLL1 from +shutting down, by marking the ddrphy4x CLK_IS_CRITICAL. + +This bug was discovered when I was porting rockchip_i2s_tdm driver to +mainline kernel from Rockchip 4.4 kernel. I guess that other Rockchip +SoCs without DMC driver may need the same patch. If this applies to +other devices, please let us know. + +Signed-off-by: Yunhao Tian +Link: https://lore.kernel.org/r/BYAPR20MB24886765F888A9705CBEB70789E39@BYAPR20MB2488.namprd20.prod.outlook.com +[adapted subject, changed to add the clock to the critical list] +Signed-off-by: Heiko Stuebner +--- + drivers/clk/rockchip/clk-rk3308.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/clk/rockchip/clk-rk3308.c b/drivers/clk/rockchip/clk-rk3308.c +index 2c3bd0c749f2..db3396c3e6e9 100644 +--- a/drivers/clk/rockchip/clk-rk3308.c ++++ b/drivers/clk/rockchip/clk-rk3308.c +@@ -911,6 +911,7 @@ static const char *const rk3308_critical_clocks[] __initconst = { + "hclk_audio", + "pclk_audio", + "sclk_ddrc", ++ "clk_ddrphy4x", + }; + + static void __init rk3308_clk_init(struct device_node *np) + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Johan Jonker +Date: Sun, 11 Jul 2021 16:34:30 +0200 +Subject: [PATCH] arm64: dts: rockchip: remove interrupt-names from iommu nodes + +The iommu driver gets the interrupts by platform_get_irq(), +so remove interrupt-names property from iommu nodes. + +Signed-off-by: Johan Jonker +Link: https://lore.kernel.org/r/20210711143430.14347-2-jbx6244@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 5 ----- + arch/arm64/boot/dts/rockchip/rk3368.dtsi | 5 ----- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 -------- + 3 files changed, 18 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 8c821acb21ff..becc1c61b182 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -623,7 +623,6 @@ h265e_mmu: iommu@ff330200 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff330200 0 0x100>; + interrupts = ; +- interrupt-names = "h265e_mmu"; + clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -634,7 +633,6 @@ vepu_mmu: iommu@ff340800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff340800 0x0 0x40>; + interrupts = ; +- interrupt-names = "vepu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -656,7 +654,6 @@ vpu_mmu: iommu@ff350800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff350800 0x0 0x40>; + interrupts = ; +- interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -667,7 +664,6 @@ rkvdec_mmu: iommu@ff360480 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; + interrupts = ; +- interrupt-names = "rkvdec_mmu"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -700,7 +696,6 @@ vop_mmu: iommu@ff373f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff373f00 0x0 0x100>; + interrupts = ; +- interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi +index 4c64fbefb483..4217897cd454 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi +@@ -709,7 +709,6 @@ iep_mmu: iommu@ff900800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff900800 0x0 0x100>; + interrupts = ; +- interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -721,7 +720,6 @@ isp_mmu: iommu@ff914000 { + reg = <0x0 0xff914000 0x0 0x100>, + <0x0 0xff915000 0x0 0x100>; + interrupts = ; +- interrupt-names = "isp_mmu"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -733,7 +731,6 @@ vop_mmu: iommu@ff930300 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff930300 0x0 0x100>; + interrupts = ; +- interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -745,7 +742,6 @@ hevc_mmu: iommu@ff9a0440 { + reg = <0x0 0xff9a0440 0x0 0x40>, + <0x0 0xff9a0480 0x0 0x40>; + interrupts = ; +- interrupt-names = "hevc_mmu"; + clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -757,7 +753,6 @@ vpu_mmu: iommu@ff9a0800 { + reg = <0x0 0xff9a0800 0x0 0x100>; + interrupts = , + ; +- interrupt-names = "vepu_mmu", "vdpu_mmu"; + clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 3871c7fd83b0..aa5d7dca3432 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1240,7 +1240,6 @@ vpu: video-codec@ff650000 { + reg = <0x0 0xff650000 0x0 0x800>; + interrupts = , + ; +- interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; +@@ -1251,7 +1250,6 @@ vpu_mmu: iommu@ff650800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff650800 0x0 0x40>; + interrupts = ; +- interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -1273,7 +1271,6 @@ vdec_mmu: iommu@ff660480 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; + interrupts = ; +- interrupt-names = "vdec_mmu"; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_VDU>; +@@ -1284,7 +1281,6 @@ iep_mmu: iommu@ff670800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff670800 0x0 0x40>; + interrupts = ; +- interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -1666,7 +1662,6 @@ vopl_mmu: iommu@ff8f3f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff8f3f00 0x0 0x100>; + interrupts = ; +- interrupt-names = "vopl_mmu"; + clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_VOPL>; +@@ -1723,7 +1718,6 @@ vopb_mmu: iommu@ff903f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff903f00 0x0 0x100>; + interrupts = ; +- interrupt-names = "vopb_mmu"; + clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_VOPB>; +@@ -1761,7 +1755,6 @@ isp0_mmu: iommu@ff914000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; + interrupts = ; +- interrupt-names = "isp0_mmu"; + clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; +@@ -1773,7 +1766,6 @@ isp1_mmu: iommu@ff924000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; + interrupts = ; +- interrupt-names = "isp1_mmu"; + clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Johan Jonker +Date: Sun, 11 Jul 2021 16:59:00 +0200 +Subject: [PATCH] arm64: dts: rockchip: rename flash nodenames + +Nodes with compatible "jedec,spi-nor" are now checked with +jedec,spi-nor.yaml and mtd.yaml. The pattern is now +"^flash(@.*)?$", so change that for the boards with a +Rockchip SoC. + +Signed-off-by: Johan Jonker +Link: https://lore.kernel.org/r/20210711145900.15443-1-jbx6244@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 2 +- + arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +index 1b0f7e4551ea..f69a38f42d2d 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts +@@ -345,7 +345,7 @@ &spdif { + &spi0 { + status = "okay"; + +- spiflash@0 { ++ flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +index c1bcc8ca3769..e310b51ab578 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +@@ -543,7 +543,7 @@ &spi1 { + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&spi1_sleep>; + +- spiflash@0 { ++ flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Johan Jonker +Date: Thu, 1 Jul 2021 16:41:09 +0200 +Subject: [PATCH] arm64: dts: rockchip: remove clock_in_out from gmac2phy node + in rk3318-a95x-z2.dts + +Recently a clock_in_out property was added to the gmac2phy node +in rk3328.dtsi, so now the clock_in_out in rk3318-a95x-z2.dts +can be removed. + +Signed-off-by: Johan Jonker +Link: https://lore.kernel.org/r/20210701144110.12333-1-jbx6244@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts +index 763cf9b4620e..d41f786b2f4b 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts +@@ -185,7 +185,6 @@ &gmac2phy { + assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; + assigned-clock-rate = <50000000>; + assigned-clocks = <&cru SCLK_MAC2PHY>; +- clock_in_out = "output"; + status = "okay"; + }; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Johan Jonker +Date: Thu, 1 Jul 2021 16:41:10 +0200 +Subject: [PATCH] arm64: dts: rockchip: remove ddc-i2c-scl-* properties from + rk3318-a95x-z2.dts + +The ddc-i2c-scl-* properties in the hdmi node are +not in use in the mainline kernel, so remove them. + +Reported-by: Alex Bee +Signed-off-by: Johan Jonker +Link: https://lore.kernel.org/r/20210701144110.12333-2-jbx6244@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts +index d41f786b2f4b..43c928ac98f0 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dts +@@ -193,8 +193,6 @@ &gpu { + }; + + &hdmi { +- ddc-i2c-scl-high-time-ns = <9625>; +- ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; + }; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Liang Chen +Date: Thu, 24 Jun 2021 19:47:17 +0800 +Subject: [PATCH] dt-bindings: arm: rockchip: add rk3568 compatible string to + pmu.yaml + +add "rockchip,rk3568-pmu", "syscon", "simple-mfd" for pmu nodes on a +rk3568 platform to pmu.ymal. + +Signed-off-by: Liang Chen +Acked-by: Rob Herring +Link: https://lore.kernel.org/r/20210624114719.1685-2-cl@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip/pmu.yaml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml +index 53115b92d17f..ceb15cea77e2 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml +@@ -23,6 +23,7 @@ select: + - rockchip,rk3066-pmu + - rockchip,rk3288-pmu + - rockchip,rk3399-pmu ++ - rockchip,rk3568-pmu + + required: + - compatible +@@ -35,6 +36,7 @@ properties: + - rockchip,rk3066-pmu + - rockchip,rk3288-pmu + - rockchip,rk3399-pmu ++ - rockchip,rk3568-pmu + - const: syscon + - const: simple-mfd + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Liang Chen +Date: Thu, 24 Jun 2021 21:10:27 +0800 +Subject: [PATCH] arm64: dts: rockchip: add pmu and qos nodes for rk3568 + +Add the power-management and QoS nodes to the core rk3568 dtsi. + +Signed-off-by: Liang Chen +Link: https://lore.kernel.org/r/20210624131027.3719-1-cl@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 229 +++++++++++++++++++++++ + 1 file changed, 229 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +index d225e6a45d5c..618849186c39 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -8,6 +8,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -257,6 +258,99 @@ uart0: serial@fdd50000 { + status = "disabled"; + }; + ++ pmu: power-management@fdd90000 { ++ compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; ++ reg = <0x0 0xfdd90000 0x0 0x1000>; ++ ++ power: power-controller { ++ compatible = "rockchip,rk3568-power-controller"; ++ #power-domain-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* These power domains are grouped by VD_GPU */ ++ power-domain@RK3568_PD_GPU { ++ reg = ; ++ clocks = <&cru ACLK_GPU_PRE>, ++ <&cru PCLK_GPU_PRE>; ++ pm_qos = <&qos_gpu>; ++ #power-domain-cells = <0>; ++ }; ++ ++ /* These power domains are grouped by VD_LOGIC */ ++ power-domain@RK3568_PD_VI { ++ reg = ; ++ clocks = <&cru HCLK_VI>, ++ <&cru PCLK_VI>; ++ pm_qos = <&qos_isp>, ++ <&qos_vicap0>, ++ <&qos_vicap1>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_VO { ++ reg = ; ++ clocks = <&cru HCLK_VO>, ++ <&cru PCLK_VO>, ++ <&cru ACLK_VOP_PRE>; ++ pm_qos = <&qos_hdcp>, ++ <&qos_vop_m0>, ++ <&qos_vop_m1>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_RGA { ++ reg = ; ++ clocks = <&cru HCLK_RGA_PRE>, ++ <&cru PCLK_RGA_PRE>; ++ pm_qos = <&qos_ebc>, ++ <&qos_iep>, ++ <&qos_jpeg_dec>, ++ <&qos_jpeg_enc>, ++ <&qos_rga_rd>, ++ <&qos_rga_wr>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_VPU { ++ reg = ; ++ clocks = <&cru HCLK_VPU_PRE>; ++ pm_qos = <&qos_vpu>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_RKVDEC { ++ clocks = <&cru HCLK_RKVDEC_PRE>; ++ reg = ; ++ pm_qos = <&qos_rkvdec>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_RKVENC { ++ reg = ; ++ clocks = <&cru HCLK_RKVENC_PRE>; ++ pm_qos = <&qos_rkvenc_rd_m0>, ++ <&qos_rkvenc_rd_m1>, ++ <&qos_rkvenc_wr_m0>; ++ #power-domain-cells = <0>; ++ }; ++ ++ power-domain@RK3568_PD_PIPE { ++ reg = ; ++ clocks = <&cru PCLK_PIPE>; ++ pm_qos = <&qos_pcie2x1>, ++ <&qos_pcie3x1>, ++ <&qos_pcie3x2>, ++ <&qos_sata0>, ++ <&qos_sata1>, ++ <&qos_sata2>, ++ <&qos_usb3_0>, ++ <&qos_usb3_1>; ++ #power-domain-cells = <0>; ++ }; ++ }; ++ }; ++ + sdmmc2: mmc@fe000000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe000000 0x0 0x4000>; +@@ -271,6 +365,141 @@ sdmmc2: mmc@fe000000 { + status = "disabled"; + }; + ++ qos_gpu: qos@fe128000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe128000 0x0 0x20>; ++ }; ++ ++ qos_rkvenc_rd_m0: qos@fe138080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe138080 0x0 0x20>; ++ }; ++ ++ qos_rkvenc_rd_m1: qos@fe138100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe138100 0x0 0x20>; ++ }; ++ ++ qos_rkvenc_wr_m0: qos@fe138180 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe138180 0x0 0x20>; ++ }; ++ ++ qos_isp: qos@fe148000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe148000 0x0 0x20>; ++ }; ++ ++ qos_vicap0: qos@fe148080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe148080 0x0 0x20>; ++ }; ++ ++ qos_vicap1: qos@fe148100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe148100 0x0 0x20>; ++ }; ++ ++ qos_vpu: qos@fe150000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe150000 0x0 0x20>; ++ }; ++ ++ qos_ebc: qos@fe158000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158000 0x0 0x20>; ++ }; ++ ++ qos_iep: qos@fe158100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158100 0x0 0x20>; ++ }; ++ ++ qos_jpeg_dec: qos@fe158180 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158180 0x0 0x20>; ++ }; ++ ++ qos_jpeg_enc: qos@fe158200 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158200 0x0 0x20>; ++ }; ++ ++ qos_rga_rd: qos@fe158280 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158280 0x0 0x20>; ++ }; ++ ++ qos_rga_wr: qos@fe158300 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe158300 0x0 0x20>; ++ }; ++ ++ qos_npu: qos@fe180000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe180000 0x0 0x20>; ++ }; ++ ++ qos_pcie2x1: qos@fe190000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190000 0x0 0x20>; ++ }; ++ ++ qos_pcie3x1: qos@fe190080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190080 0x0 0x20>; ++ }; ++ ++ qos_pcie3x2: qos@fe190100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190100 0x0 0x20>; ++ }; ++ ++ qos_sata0: qos@fe190200 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190200 0x0 0x20>; ++ }; ++ ++ qos_sata1: qos@fe190280 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190280 0x0 0x20>; ++ }; ++ ++ qos_sata2: qos@fe190300 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190300 0x0 0x20>; ++ }; ++ ++ qos_usb3_0: qos@fe190380 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190380 0x0 0x20>; ++ }; ++ ++ qos_usb3_1: qos@fe190400 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe190400 0x0 0x20>; ++ }; ++ ++ qos_rkvdec: qos@fe198000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe198000 0x0 0x20>; ++ }; ++ ++ qos_hdcp: qos@fe1a8000 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe1a8000 0x0 0x20>; ++ }; ++ ++ qos_vop_m0: qos@fe1a8080 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe1a8080 0x0 0x20>; ++ }; ++ ++ qos_vop_m1: qos@fe1a8100 { ++ compatible = "rockchip,rk3568-qos", "syscon"; ++ reg = <0x0 0xfe1a8100 0x0 0x20>; ++ }; ++ + sdmmc0: mmc@fe2b0000 { + compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Levin Du +Date: Fri, 9 Jul 2021 16:01:25 +0800 +Subject: [PATCH] dt-bindings: add doc for Firefly ROC-RK3328-PC + +Add devicetree binding documentation for the Firefly ROC-RK3328-PC. + +Signed-off-by: Levin Du +Acked-by: Rob Herring +Link: https://lore.kernel.org/r/20210709080126.17045-2-djw@t-chip.com.cn +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index 6546b015fc62..7ef902f45b38 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -115,6 +115,11 @@ properties: + - const: firefly,roc-rk3328-cc + - const: rockchip,rk3328 + ++ - description: Firefly ROC-RK3328-PC ++ items: ++ - const: firefly,roc-rk3328-pc ++ - const: rockchip,rk3328 ++ + - description: Firefly ROC-RK3399-PC + items: + - enum: + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Levin Du +Date: Fri, 9 Jul 2021 16:01:26 +0800 +Subject: [PATCH] arm64: dts: rockchip: add support for Firefly ROC-RK3328-PC + +ROC-RK3328-PC is the board inside the portable Firefly Station M1 +Geek PC. As a redesign after the ROC-RK3328-CC, it uses TypeC as +power input and OTG port, embedded with eMMC 5.1 storage and a +SDIO WiFi/BT chip (RTL8723DS). + +- Rockchip RK3328 SoC +- 2/4GB LPDDR3 RAM +- 16/32/64/128GB eMMC 5.1 +- TF card slot +- USB 3.0 Port x 1, USB 2.0 Port x 1, TypeC Port x 1 (Power/OTG) +- HDMI +- Gigabit Ethernet +- WiFi: RTL8723DS +- Audio: RK3328 +- Key: Power, Reset, Recovery +- LED: POWER, USER +- IR + +Signed-off-by: Levin Du +Link: https://lore.kernel.org/r/20210709080126.17045-3-djw@t-chip.com.cn +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../arm64/boot/dts/rockchip/rk3328-roc-pc.dts | 110 ++++++++++++++++++ + 2 files changed, 111 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 7fdb41de01ec..46652b6d7c4d 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts +new file mode 100644 +index 000000000000..e3e3984d01d4 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dts +@@ -0,0 +1,110 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++// Copyright (c) 2021 T-Chip Intelligent Technology Co., Ltd ++ ++/dts-v1/; ++ ++#include ++ ++#include "rk3328-roc-cc.dts" ++ ++/ { ++ model = "Firefly ROC-RK3328-PC"; ++ compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328"; ++ ++ adc-keys { ++ compatible = "adc-keys"; ++ io-channels = <&saradc 0>; ++ io-channel-names = "buttons"; ++ keyup-threshold-microvolt = <1750000>; ++ ++ /* This button is unpopulated out of the factory. */ ++ button-recovery { ++ label = "Recovery"; ++ linux,code = ; ++ press-threshold-microvolt = <10000>; ++ }; ++ }; ++ ++ ir-receiver { ++ compatible = "gpio-ir-receiver"; ++ gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; ++ linux,rc-map-name = "rc-khadas"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ir_int>; ++ }; ++ ++ sdio_pwrseq: sdio-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_en>, <&wifi_host_wake>; ++ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&codec { ++ mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_logic>; ++}; ++ ++&pinctrl { ++ ir { ++ ir_int: ir-int { ++ rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ sdmmcio { ++ sdio_per_pin: sdio-per-pin { ++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ wifi { ++ wifi_en: wifi-en { ++ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ wifi_host_wake: wifi-host-wake { ++ rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none_4ma>; ++ }; ++ ++ bt_rst: bt-rst { ++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ bt_en: bt-en { ++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&pmic_int_l { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; ++}; ++ ++&rk805 { ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++}; ++ ++&saradc { ++ vref-supply = <&vcc_18>; ++ status = "okay"; ++}; ++ ++&usb20_host_drv { ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; ++}; ++ ++&vcc_host1_5v { ++ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; ++}; ++ ++&vcc_sdio { ++ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdio_per_pin>; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Levin Du +Date: Mon, 28 Jun 2021 11:54:01 +0800 +Subject: [PATCH] dt-bindings: add doc for Firefly ROC-RK3399-PC-PLUS + +Add devicetree binding documentation for the Firefly ROC-RK3399-PC-PLUS. + +Signed-off-by: Levin Du +Acked-by: Rob Herring +Link: https://lore.kernel.org/r/20210628035402.16812-2-djw@t-chip.com.cn +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index 7ef902f45b38..ce7785fe3598 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -127,6 +127,12 @@ properties: + - firefly,roc-rk3399-pc-mezzanine + - const: rockchip,rk3399 + ++ - description: Firefly ROC-RK3399-PC-PLUS ++ items: ++ - enum: ++ - firefly,roc-rk3399-pc-plus ++ - const: rockchip,rk3399 ++ + - description: FriendlyElec NanoPi R2S + items: + - const: friendlyarm,nanopi-r2s + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Levin Du +Date: Mon, 28 Jun 2021 11:54:02 +0800 +Subject: [PATCH] arm64: dts: rockchip: add support for Firefly + ROC-RK3399-PC-PLUS + +ROC-RK3399-PC-PLUS is the board inside the portable Firefly Station P1 Geek +PC. As a redesign after the ROC-RK3399-PC, it uses DC-12V as power input +and spares a USB 3 host port. It is also equipped with a USB WiFi chip and +audio codec without the mezzanine board. + +- Rockchip RK3399 SoC +- 4GB LPDDR4 RAM +- 16MB SPI-Flash +- eMMC slot +- TF card slot +- USB 3.0 Port x 1, USB 2.0 Port x 1, TypeC Port x 1 +- HDMI +- Gigabit Ethernet +- WiFi: RTL8723DU +- Audio: ES8388 +- Key: Recovery +- LED: WORK, DIY +- IR + +Signed-off-by: Kongxin Deng +Signed-off-by: Levin Du +Link: https://lore.kernel.org/r/20210628035402.16812-3-djw@t-chip.com.cn +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3399-roc-pc-plus.dts | 218 ++++++++++++++++++ + 2 files changed, 219 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 46652b6d7c4d..2890756c294c 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -43,6 +43,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts +new file mode 100644 +index 000000000000..5a2661ae0131 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dts +@@ -0,0 +1,218 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd ++ */ ++ ++/dts-v1/; ++#include "rk3399-roc-pc.dtsi" ++ ++/* ++ * Notice: ++ * 1. rk3399-roc-pc-plus is powered by dc_12v directly. ++ * 2. rk3399-roc-pc-plus has only vcc_bus_typec0 in schematic, which is coresponding ++ * to vcc_vbus_typec1 in rk3399-roc-pc. ++ * For simplicity, reserve the node name of vcc_vbus_typec1. ++ * 3. vcc5v0_host is actually 2 regulators (host0, 1) controlled by the same gpio. ++ */ ++ ++/delete-node/ &fusb1; ++/delete-node/ &hub_rst; ++/delete-node/ &mp8859; ++/delete-node/ &vcc_sys_en; ++/delete-node/ &vcc_vbus_typec0; ++/delete-node/ &yellow_led; ++ ++/ { ++ model = "Firefly ROC-RK3399-PC-PLUS Board"; ++ compatible = "firefly,roc-rk3399-pc-plus", "rockchip,rk3399"; ++ ++ dc_12v: dc-12v { ++ compatible = "regulator-fixed"; ++ regulator-name = "dc_12v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ es8388-sound { ++ compatible = "simple-audio-card"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_det_pin>; ++ simple-audio-card,name = "rockchip,es8388-codec"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,widgets = ++ "Microphone", "Mic Jack", ++ "Headphone", "Headphones"; ++ simple-audio-card,routing = ++ "LINPUT1", "Mic Jack", ++ "Headphone Amp INL", "LOUT2", ++ "Headphone Amp INR", "ROUT2", ++ "Headphones", "Headphone Amp OUTL", ++ "Headphones", "Headphone Amp OUTR"; ++ simple-audio-card,hp-det-gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; ++ simple-audio-card,aux-devs = <&headphones_amp>; ++ simple-audio-card,pin-switches = "Headphones"; ++ ++ simple-audio-card,codec { ++ sound-dai = <&es8388>; ++ }; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1>; ++ }; ++ }; ++ ++ gpio-fan { ++ #cooling-cells = <2>; ++ compatible = "gpio-fan"; ++ gpio-fan,speed-map = <0 0 3000 1>; ++ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ /delete-node/ gpio-keys; ++ ++ /* not amplifier, used as switcher only */ ++ headphones_amp: headphones-amp { ++ compatible = "simple-audio-amplifier"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ear_ctl_pin>; ++ enable-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; ++ sound-name-prefix = "Headphone Amp"; ++ VCC-supply = <&vcca3v0_codec>; ++ }; ++ ++ ir-receiver { ++ linux,rc-map-name = "rc-khadas"; ++ }; ++ ++ leds { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&work_led_pin>, <&diy_led_pin>; ++ }; ++}; ++ ++&fusb0 { ++ vbus-supply = <&vcc_vbus_typec1>; ++}; ++ ++&i2c0 { ++ hym8563: hym8563@51 { ++ compatible = "haoyu,hym8563"; ++ reg = <0x51>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <0>; ++ clock-frequency = <32768>; ++ clock-output-names = "xin32k"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hym8563_int>; ++ }; ++}; ++ ++&i2c1 { ++ es8388: es8388@11 { ++ compatible = "everest,es8388"; ++ reg = <0x11>; ++ clock-names = "mclk"; ++ clocks = <&cru SCLK_I2S_8CH_OUT>; ++ #sound-dai-cells = <0>; ++ }; ++}; ++ ++/* <4 RK_PA0 1 &pcfg_pull_none> is used as i2s_8ch_mclk_pin */ ++&i2s0_8ch_bus { ++ rockchip,pins = ++ <3 RK_PD0 1 &pcfg_pull_none>, ++ <3 RK_PD1 1 &pcfg_pull_none>, ++ <3 RK_PD2 1 &pcfg_pull_none>, ++ <3 RK_PD3 1 &pcfg_pull_none>, ++ <3 RK_PD4 1 &pcfg_pull_none>, ++ <3 RK_PD5 1 &pcfg_pull_none>, ++ <3 RK_PD6 1 &pcfg_pull_none>, ++ <3 RK_PD7 1 &pcfg_pull_none>; ++}; ++ ++&i2s1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s_8ch_mclk_pin>, <&i2s1_2ch_bus>; ++ rockchip,playback-channels = <2>; ++ rockchip,capture-channels = <2>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ es8388 { ++ ear_ctl_pin: ear-ctl-pin { ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_high>; ++ }; ++ ++ hp_det_pin: hp-det-pin { ++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ hym8563 { ++ hym8563_int: hym8563-int { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ i2s1 { ++ i2s_8ch_mclk_pin: i2s-8ch-mclk-pin { ++ rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&u2phy0 { ++ status = "okay"; ++ ++ u2phy0_otg: otg-port { ++ phy-supply = <&vcc_vbus_typec1>; ++ status = "okay"; ++ }; ++ ++ u2phy0_host: host-port { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++ }; ++}; ++ ++&u2phy1 { ++ status = "okay"; ++ ++ u2phy1_otg: otg-port { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++ }; ++ ++ u2phy1_host: host-port { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; ++ status = "okay"; ++}; ++ ++&usbdrd_dwc3_0 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ ++&vcc_sys { ++ /* vcc_sys is fixed, not controlled by any gpio */ ++ /delete-property/ gpio; ++ /delete-property/ pinctrl-names; ++ /delete-property/ pinctrl-0; ++}; ++ ++&vcc5v0_host { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Dennis Gilmore +Date: Wed, 14 Jul 2021 21:56:29 -0500 +Subject: [PATCH] arm64: dts: rockchip: set stdout-path on helios64 + +set the default output path to uart2 + +Signed-off-by: Dennis Gilmore +Link: https://lore.kernel.org/r/20210715025635.70452-2-dgilmore@redhat.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +index 738cfd21df3e..d911a9a4f0f0 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +@@ -43,6 +43,10 @@ avdd_1v8_s0: avdd-1v8-s0 { + vin-supply = <&vcc3v3_sys_s3>; + }; + ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Dennis Gilmore +Date: Wed, 14 Jul 2021 21:56:30 -0500 +Subject: [PATCH] arm64: dts: rockchip: add SPI support to helios64 + +add SPI support for the helios64, u-boot can live in spi1, spi2 is user +accessible, spi5 is for the sata controller rom. +https://wiki.kobol.io/helios64/spi/ + +Signed-off-by: Dennis Gilmore +Link: https://lore.kernel.org/r/20210715025635.70452-3-dgilmore@redhat.com +Signed-off-by: Heiko Stuebner +--- + .../dts/rockchip/rk3399-kobol-helios64.dts | 24 +++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +index d911a9a4f0f0..b275b4790211 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +@@ -21,6 +21,9 @@ / { + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; ++ spi1 = &spi1; ++ spi2 = &spi2; ++ spi5 = &spi5; + }; + + avdd_0v9_s0: avdd-0v9-s0 { +@@ -473,6 +476,27 @@ &sdmmc { + status = "okay"; + }; + ++&spi1 { ++ status = "okay"; ++ ++ spiflash: flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0x0>; ++ spi-max-frequency = <25000000>; ++ status = "okay"; ++ m25p,fast-read; ++ }; ++}; ++ ++/* UEXT connector */ ++&spi2 { ++ status = "okay"; ++}; ++ ++&spi5 { ++ status = "okay"; ++}; ++ + &tcphy1 { + /* phy for &usbdrd_dwc3_1 */ + status = "okay"; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Dennis Gilmore +Date: Wed, 14 Jul 2021 21:56:31 -0500 +Subject: [PATCH] arm64: dts: rockchip: enable tsadc on helios64 + +Enable the tsadc thermal controller on the helios64 + +Signed-off-by: Dennis Gilmore +Link: https://lore.kernel.org/r/20210715025635.70452-4-dgilmore@redhat.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +index b275b4790211..63c7681843da 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts +@@ -502,6 +502,14 @@ &tcphy1 { + status = "okay"; + }; + ++&tsadc { ++ /* tshut mode 0:CRU 1:GPIO */ ++ rockchip,hw-tshut-mode = <1>; ++ /* tshut polarity 0:LOW 1:HIGH */ ++ rockchip,hw-tshut-polarity = <1>; ++ status = "okay"; ++}; ++ + &u2phy1 { + status = "okay"; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Simon Xue +Date: Mon, 5 Jul 2021 09:26:10 +0800 +Subject: [PATCH] arm64: dts: rockchip: add saradc node for rk3568 + +Add the core dt-node for the rk3568's saradc. + +Signed-off-by: Simon Xue +Link: https://lore.kernel.org/r/20210705012610.3831-1-xxm@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +index 618849186c39..11825909c5db 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -754,6 +754,18 @@ uart9: serial@fe6d0000 { + status = "disabled"; + }; + ++ saradc: saradc@fe720000 { ++ compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; ++ reg = <0x0 0xfe720000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; ++ clock-names = "saradc", "apb_pclk"; ++ resets = <&cru SRST_P_SARADC>; ++ reset-names = "saradc-apb"; ++ #io-channel-cells = <1>; ++ status = "disabled"; ++ }; ++ + pinctrl: pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <&grf>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Matthias Brugger +Date: Thu, 15 Jul 2021 18:41:01 +0200 +Subject: [PATCH] arm64: dts: rockchip: Disable CDN DP on Pinebook Pro + +The CDN DP needs a PHY and a extcon to work correctly. But no extcon is +provided by the device-tree, which leads to an error: +cdn-dp fec00000.dp: [drm:cdn_dp_probe [rockchipdrm]] *ERROR* missing extcon or phy +cdn-dp: probe of fec00000.dp failed with error -22 + +Disable the CDN DP to make graphic work on the Pinebook Pro. + +Reported-by: Guillaume Gardet +Signed-off-by: Matthias Brugger +Link: https://lore.kernel.org/r/20210715164101.11486-1-matthias.bgg@kernel.org +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +index 2b5f001ff4a6..9e5d07f5712e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +@@ -385,10 +385,6 @@ mains_charger: dc-charger { + }; + }; + +-&cdn_dp { +- status = "okay"; +-}; +- + &cpu_b0 { + cpu-supply = <&vdd_cpu_b>; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 18 Jun 2021 20:12:52 +0200 +Subject: [PATCH] dt-bindings: Add doc for ROCK Pi 4 A+ and B+ + +ROCK Pi 4 got 2 more variants called A+ and B+. +Add the dt-bindings documentation for it. + +Signed-off-by: Alex Bee +Acked-by: Rob Herring +Link: https://lore.kernel.org/r/20210618181256.27992-2-knaerzche@gmail.com +Signed-off-by: Heiko Stuebner +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index ce7785fe3598..f051e3330302 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -471,11 +471,13 @@ properties: + - const: radxa,rock + - const: rockchip,rk3188 + +- - description: Radxa ROCK Pi 4A/B/C ++ - description: Radxa ROCK Pi 4A/A+/B/B+/C + items: + - enum: + - radxa,rockpi4a ++ - radxa,rockpi4a-plus + - radxa,rockpi4b ++ - radxa,rockpi4b-plus + - radxa,rockpi4c + - const: radxa,rockpi4 + - const: rockchip,rk3399 + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 18 Jun 2021 20:12:53 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add RK3399 ROCK Pi 4A+ board + +ROCK Pi 4A+ board is the successor of ROCK Pi 4A board. + +Differences to the original version are +- has RK3399 OP1 SoC revision +- has eMMC (16 or 32 GB) soldered on board (no changes required, + since it is enabled in rk3399-rock-pi-4.dtsi) +- dev boards have SPI flash soldered, but as per manufacturer response, + this won't be the case for mass production boards + +Signed-off-by: Alex Bee +Link: https://lore.kernel.org/r/20210618181256.27992-3-knaerzche@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts | 14 ++++++++++++++ + 2 files changed, 15 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 2890756c294c..5e2e852c5f69 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -45,6 +45,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts +new file mode 100644 +index 000000000000..281a04b2f5e9 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts +@@ -0,0 +1,14 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 Akash Gajjar ++ * Copyright (c) 2019 Pragnesh Patel ++ */ ++ ++/dts-v1/; ++#include "rk3399-rock-pi-4.dtsi" ++#include "rk3399-op1-opp.dtsi" ++ ++/ { ++ model = "Radxa ROCK Pi 4A+"; ++ compatible = "radxa,rockpi4a-plus", "radxa,rockpi4", "rockchip,rk3399"; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 18 Jun 2021 20:12:54 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add RK3399 ROCK Pi 4B+ board + +ROCK Pi 4B+ board is the successor of ROCK Pi 4B board. + +Differences to the original version are +- has RK3399 OP1 SoC revision +- has eMMC (16 or 32 GB) soldered on board (no changes required, + since it is enabled in rk3399-rock-pi-4.dtsi) +- dev boards have SPI flash soldered, but as per manufacturer response, + this won't be the case for mass production boards + +Signed-off-by: Alex Bee +Link: https://lore.kernel.org/r/20210618181256.27992-4-knaerzche@gmail.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../dts/rockchip/rk3399-rock-pi-4b-plus.dts | 47 +++++++++++++++++++ + 2 files changed, 48 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 5e2e852c5f69..b1c3f32ac11a 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b-plus.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts +new file mode 100644 +index 000000000000..dfad13d2ab24 +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts +@@ -0,0 +1,47 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2019 Akash Gajjar ++ * Copyright (c) 2019 Pragnesh Patel ++ */ ++ ++/dts-v1/; ++#include "rk3399-rock-pi-4.dtsi" ++#include "rk3399-op1-opp.dtsi" ++ ++/ { ++ model = "Radxa ROCK Pi 4B+"; ++ compatible = "radxa,rockpi4b-plus", "radxa,rockpi4", "rockchip,rk3399"; ++ ++ aliases { ++ mmc2 = &sdio0; ++ }; ++}; ++ ++&sdio0 { ++ status = "okay"; ++ ++ brcmf: wifi@1 { ++ compatible = "brcm,bcm4329-fmac"; ++ reg = <1>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ interrupt-names = "host-wake"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wifi_host_wake_l>; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ clocks = <&rk808 1>; ++ clock-names = "ext_clock"; ++ device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; ++ host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; ++ shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; ++ }; ++}; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 18 Jun 2021 20:12:55 +0200 +Subject: [PATCH] arm64: dts: rockchip: add ES8316 codec for ROCK Pi 4 + +ROCK Pi 4 boards have the codec connected to i2s0 and it is accessible +via i2c1 address 0x11. +Add an audio-graph-card for it. + +Signed-off-by: Alex Bee +Link: https://lore.kernel.org/r/20210618181256.27992-5-knaerzche@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 28 +++++++++++++++++++ + 1 file changed, 28 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +index b28888ea9262..b49072af4014 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +@@ -36,6 +36,12 @@ sdio_pwrseq: sdio-pwrseq { + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + ++ sound { ++ compatible = "audio-graph-card"; ++ label = "Analog"; ++ dais = <&i2s0_p0>; ++ }; ++ + vcc12v_dcin: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; +@@ -422,6 +428,20 @@ &i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; ++ ++ es8316: codec@11 { ++ compatible = "everest,es8316"; ++ reg = <0x11>; ++ clocks = <&cru SCLK_I2S_8CH_OUT>; ++ clock-names = "mclk"; ++ #sound-dai-cells = <0>; ++ ++ port { ++ es8316_p0_0: endpoint { ++ remote-endpoint = <&i2s0_p0_0>; ++ }; ++ }; ++ }; + }; + + &i2c3 { +@@ -441,6 +461,14 @@ &i2s0 { + rockchip,capture-channels = <2>; + rockchip,playback-channels = <2>; + status = "okay"; ++ ++ i2s0_p0: port { ++ i2s0_p0_0: endpoint { ++ dai-format = "i2s"; ++ mclk-fs = <256>; ++ remote-endpoint = <&es8316_p0_0>; ++ }; ++ }; + }; + + &i2s1 { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 18 Jun 2021 20:12:56 +0200 +Subject: [PATCH] arm64: dts: rockchip: add SPDIF node for ROCK Pi 4 + +Add a SPDIF audio-graph-card to ROCK Pi 4 device tree. + +It's not enabled by default since all dma channels are used by +the (already) enabled i2s0/1/2 and the pin is muxed with GPIO4_C5 +which might be in use already. +If enabled SPDIF_TX will be available at pin #15. + +Signed-off-by: Alex Bee +Link: https://lore.kernel.org/r/20210618181256.27992-6-knaerzche@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 26 +++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +index b49072af4014..98136c88fa49 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +@@ -42,6 +42,23 @@ sound { + dais = <&i2s0_p0>; + }; + ++ sound-dit { ++ compatible = "audio-graph-card"; ++ label = "SPDIF"; ++ dais = <&spdif_p0>; ++ }; ++ ++ spdif-dit { ++ compatible = "linux,spdif-dit"; ++ #sound-dai-cells = <0>; ++ ++ port { ++ dit_p0_0: endpoint { ++ remote-endpoint = <&spdif_p0_0>; ++ }; ++ }; ++ }; ++ + vcc12v_dcin: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; +@@ -631,6 +648,15 @@ &sdhci { + status = "okay"; + }; + ++&spdif { ++ ++ spdif_p0: port { ++ spdif_p0_0: endpoint { ++ remote-endpoint = <&dit_p0_0>; ++ }; ++ }; ++}; ++ + &tcphy0 { + status = "okay"; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Thu, 22 Jul 2021 09:39:55 +0200 +Subject: [PATCH] arm64: dts: rockchip: add csi-dphy to px30 + +Add the CSI dphy node to the core px30 devicetree for later use +with the rkisp. + +Signed-off-by: Heiko Stuebner +Link: https://lore.kernel.org/r/20210722073955.1192168-1-heiko@sntech.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/px30.dtsi | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi +index 248ebb61aa79..6e53a4cc75e6 100644 +--- a/arch/arm64/boot/dts/rockchip/px30.dtsi ++++ b/arch/arm64/boot/dts/rockchip/px30.dtsi +@@ -864,6 +864,19 @@ dsi_dphy: phy@ff2e0000 { + status = "disabled"; + }; + ++ csi_dphy: phy@ff2f0000 { ++ compatible = "rockchip,px30-csi-dphy"; ++ reg = <0x0 0xff2f0000 0x0 0x4000>; ++ clocks = <&cru PCLK_MIPICSIPHY>; ++ clock-names = "pclk"; ++ #phy-cells = <0>; ++ power-domains = <&power PX30_PD_VI>; ++ resets = <&cru SRST_MIPICSIPHY_P>; ++ reset-names = "apb"; ++ rockchip,grf = <&grf>; ++ status = "disabled"; ++ }; ++ + usb20_otg: usb@ff300000 { + compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Wed, 10 Feb 2021 12:10:18 +0100 +Subject: [PATCH] arm64: dts: rockchip: add #phy-cells to mipi-dsi1 on rk3399 + +The dsi controller includes access to the dphy which might be used +not only for dsi output but also for csi input on dsi1, so add the +necessary #phy-cells to allow it to be used as phy. + +Signed-off-by: Heiko Stuebner +Tested-by: Sebastian Fricke +Acked-by: Helen Koike +Link: https://lore.kernel.org/r/20210210111020.2476369-5-heiko@sntech.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index aa5d7dca3432..8d68775365a3 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1870,6 +1870,7 @@ mipi_dsi1: mipi@ff968000 { + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; ++ #phy-cells = <0>; + status = "disabled"; + + ports { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Wed, 10 Feb 2021 12:10:19 +0100 +Subject: [PATCH] arm64: dts: rockchip: add cif clk-control pinctrl for rk3399 + +This enables variant a of the clkout signal for camera applications +and also the cifclkin pinctrl setting. + +Signed-off-by: Heiko Stuebner +Tested-by: Sebastian Fricke +Acked-by: Helen Koike +Link: https://lore.kernel.org/r/20210210111020.2476369-6-heiko@sntech.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 8d68775365a3..493042bc20c0 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -2107,6 +2107,18 @@ clk_32k: clk-32k { + }; + }; + ++ cif { ++ cif_clkin: cif-clkin { ++ rockchip,pins = ++ <2 RK_PB2 3 &pcfg_pull_none>; ++ }; ++ ++ cif_clkouta: cif-clkouta { ++ rockchip,pins = ++ <2 RK_PB3 3 &pcfg_pull_none>; ++ }; ++ }; ++ + edp { + edp_hpd: edp-hpd { + rockchip,pins = + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Heiko Stuebner +Date: Wed, 10 Feb 2021 12:10:20 +0100 +Subject: [PATCH] arm64: dts: rockchip: add isp1 node on rk3399 + +ISP1 is supplied by the tx1rx1 dphy, that is controlled from +inside the dsi1 controller, so include the necessary phy-link +for it. + +Signed-off-by: Heiko Stuebner +Tested-by: Sebastian Fricke +Acked-by: Helen Koike +Link: https://lore.kernel.org/r/20210210111020.2476369-7-heiko@sntech.de +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26 ++++++++++++++++++++++++ + 1 file changed, 26 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 493042bc20c0..9db9484ca38f 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1762,6 +1762,32 @@ isp0_mmu: iommu@ff914000 { + rockchip,disable-mmu-reset; + }; + ++ isp1: isp1@ff920000 { ++ compatible = "rockchip,rk3399-cif-isp"; ++ reg = <0x0 0xff920000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_ISP1>, ++ <&cru ACLK_ISP1_WRAPPER>, ++ <&cru HCLK_ISP1_WRAPPER>; ++ clock-names = "isp", "aclk", "hclk"; ++ iommus = <&isp1_mmu>; ++ phys = <&mipi_dsi1>; ++ phy-names = "dphy"; ++ power-domains = <&power RK3399_PD_ISP1>; ++ status = "disabled"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ }; ++ + isp1_mmu: iommu@ff924000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski +Date: Wed, 28 Jul 2021 20:00:40 -0300 +Subject: [PATCH] arm64: dts: rockchip: Add VPU support for the PX30 + +The PX30 has a VPU (both decoder and encoder) with a dedicated IOMMU. +Describe these two entities in device-tree. + +Signed-off-by: Paul Kocialkowski +Signed-off-by: Ezequiel Garcia +Link: https://lore.kernel.org/r/20210728230040.17368-1-ezequiel@collabora.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/px30.dtsi | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi +index 6e53a4cc75e6..185bcc5c16ac 100644 +--- a/arch/arm64/boot/dts/rockchip/px30.dtsi ++++ b/arch/arm64/boot/dts/rockchip/px30.dtsi +@@ -1037,6 +1037,28 @@ gpu: gpu@ff400000 { + status = "disabled"; + }; + ++ vpu: video-codec@ff442000 { ++ compatible = "rockchip,px30-vpu"; ++ reg = <0x0 0xff442000 0x0 0x800>; ++ interrupts = , ++ ; ++ interrupt-names = "vepu", "vdpu"; ++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; ++ clock-names = "aclk", "hclk"; ++ iommus = <&vpu_mmu>; ++ power-domains = <&power PX30_PD_VPU>; ++ }; ++ ++ vpu_mmu: iommu@ff442800 { ++ compatible = "rockchip,iommu"; ++ reg = <0x0 0xff442800 0x0 0x100>; ++ interrupts = ; ++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; ++ clock-names = "aclk", "iface"; ++ #iommu-cells = <0>; ++ power-domains = <&power PX30_PD_VPU>; ++ }; ++ + dsi: dsi@ff450000 { + compatible = "rockchip,px30-mipi-dsi"; + reg = <0x0 0xff450000 0x0 0x10000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai +Date: Thu, 12 Aug 2021 17:47:52 +0800 +Subject: [PATCH] dt-bindings: arm: rockchip: Add gru-scarlet-dumo board + +Dumo is another variant of Scarlet, also known as the ASUS Chromebook +Tablet CT100. This is almost the same as Scarlet-Innolux, but uses a +specific calibration variant for the WiFi module. + +Add an entry for the board compatibles. + +Signed-off-by: Chen-Yu Tsai +Link: https://lore.kernel.org/r/20210812094753.2359087-2-wenst@chromium.org +Signed-off-by: Heiko Stuebner +--- + .../devicetree/bindings/arm/rockchip.yaml | 28 +++++++++++++++++++ + 1 file changed, 28 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index f051e3330302..517f435cbc6e 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -298,6 +298,34 @@ properties: + - const: google,veyron + - const: rockchip,rk3288 + ++ - description: Google Scarlet - Dumo (ASUS Chromebook Tablet CT100) ++ items: ++ - const: google,scarlet-rev15-sku0 ++ - const: google,scarlet-rev15 ++ - const: google,scarlet-rev14-sku0 ++ - const: google,scarlet-rev14 ++ - const: google,scarlet-rev13-sku0 ++ - const: google,scarlet-rev13 ++ - const: google,scarlet-rev12-sku0 ++ - const: google,scarlet-rev12 ++ - const: google,scarlet-rev11-sku0 ++ - const: google,scarlet-rev11 ++ - const: google,scarlet-rev10-sku0 ++ - const: google,scarlet-rev10 ++ - const: google,scarlet-rev9-sku0 ++ - const: google,scarlet-rev9 ++ - const: google,scarlet-rev8-sku0 ++ - const: google,scarlet-rev8 ++ - const: google,scarlet-rev7-sku0 ++ - const: google,scarlet-rev7 ++ - const: google,scarlet-rev6-sku0 ++ - const: google,scarlet-rev6 ++ - const: google,scarlet-rev5-sku0 ++ - const: google,scarlet-rev5 ++ - const: google,scarlet ++ - const: google,gru ++ - const: rockchip,rk3399 ++ + - description: Google Scarlet - Kingdisplay (Acer Chromebook Tab 10) + items: + - const: google,scarlet-rev15-sku7 + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Dan Johansen +Date: Fri, 6 Aug 2021 00:04:27 +0200 +Subject: [PATCH] arm64: dts: rockchip: Setup USB typec port as datarole on for + Pinebook Pro + +Some chargers try to put the charged device into device data +role. Before this commit this condition caused the tcpm state machine to +issue a hard reset due to a capability missmatch. + +Signed-off-by: Dan Johansen +Link: https://lore.kernel.org/r/20210805220426.2693062-1-strit@manjaro.org +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +index 9e5d07f5712e..dae8c252bc2b 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +@@ -707,7 +707,7 @@ fusb0: fusb30x@22 { + + connector { + compatible = "usb-c-connector"; +- data-role = "host"; ++ data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Peter Geis +Date: Fri, 30 Jul 2021 11:17:27 -0400 +Subject: [PATCH] arm64: dts: rockchip: add thermal fan control to rockpro64 + +The rockpro64 had a fan node since +commit 5882d65c1691 ("arm64: dts: rockchip: Add PWM fan for RockPro64") +however it was never tied into the thermal driver for automatic control. + +Add the links to the thermal node to permit the kernel to handle this +automatically. +Borrowed from the (rk3399-khadas-edge.dtsi). + +Signed-off-by: Peter Geis +Link: https://lore.kernel.org/r/20210730151727.729822-1-pgwipeout@gmail.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3399-rockpro64.dtsi | 29 +++++++++++++++++++ + 1 file changed, 29 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +index 6bff8db7d33e..83db4ca67334 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +@@ -69,6 +69,7 @@ diy_led: led-1 { + + fan: pwm-fan { + compatible = "pwm-fan"; ++ cooling-levels = <0 100 150 200 255>; + #cooling-cells = <2>; + fan-supply = <&vcc12v_dcin>; + pwms = <&pwm1 0 50000 0>; +@@ -245,6 +246,34 @@ &cpu_b1 { + cpu-supply = <&vdd_cpu_b>; + }; + ++&cpu_thermal { ++ trips { ++ cpu_warm: cpu_warm { ++ temperature = <55000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ ++ cpu_hot: cpu_hot { ++ temperature = <65000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ ++ cooling-maps { ++ map2 { ++ trip = <&cpu_warm>; ++ cooling-device = <&fan THERMAL_NO_LIMIT 1>; ++ }; ++ ++ map3 { ++ trip = <&cpu_hot>; ++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>; ++ }; ++ }; ++}; ++ + &emmc_phy { + status = "okay"; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Thu, 12 Aug 2021 21:45:43 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add SFC to PX30 + +Add a devicetree entry for the Rockchip SFC for the PX30 SOC. + +Signed-off-by: Chris Morgan +Signed-off-by: Jon Lin +Link: https://lore.kernel.org/r/20210812134546.31340-4-jon.lin@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/px30.dtsi | 38 ++++++++++++++++++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi +index 185bcc5c16ac..64f643145688 100644 +--- a/arch/arm64/boot/dts/rockchip/px30.dtsi ++++ b/arch/arm64/boot/dts/rockchip/px30.dtsi +@@ -987,6 +987,18 @@ emmc: mmc@ff390000 { + status = "disabled"; + }; + ++ sfc: spi@ff3a0000 { ++ compatible = "rockchip,sfc"; ++ reg = <0x0 0xff3a0000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; ++ clock-names = "clk_sfc", "hclk_sfc"; ++ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; ++ pinctrl-names = "default"; ++ power-domains = <&power PX30_PD_MMC_NAND>; ++ status = "disabled"; ++ }; ++ + nfc: nand-controller@ff3b0000 { + compatible = "rockchip,px30-nfc"; + reg = <0x0 0xff3b0000 0x0 0x4000>; +@@ -2008,6 +2020,32 @@ flash_bus8: flash-bus8 { + }; + }; + ++ sfc { ++ sfc_bus4: sfc-bus4 { ++ rockchip,pins = ++ <1 RK_PA0 3 &pcfg_pull_none>, ++ <1 RK_PA1 3 &pcfg_pull_none>, ++ <1 RK_PA2 3 &pcfg_pull_none>, ++ <1 RK_PA3 3 &pcfg_pull_none>; ++ }; ++ ++ sfc_bus2: sfc-bus2 { ++ rockchip,pins = ++ <1 RK_PA0 3 &pcfg_pull_none>, ++ <1 RK_PA1 3 &pcfg_pull_none>; ++ }; ++ ++ sfc_cs0: sfc-cs0 { ++ rockchip,pins = ++ <1 RK_PA4 3 &pcfg_pull_none>; ++ }; ++ ++ sfc_clk: sfc-clk { ++ rockchip,pins = ++ <1 RK_PB1 3 &pcfg_pull_none>; ++ }; ++ }; ++ + lcdc { + lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { + rockchip,pins = + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Thu, 12 Aug 2021 21:46:38 +0800 +Subject: [PATCH] arm64: dts: rockchip: Add SFC to RK3308 + +Add a devicetree entry for the Rockchip SFC for the RK3308 SOC. + +Signed-off-by: Chris Morgan +Signed-off-by: Jon Lin +Link: https://lore.kernel.org/r/20210812134639.31586-1-jon.lin@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + arch/arm64/boot/dts/rockchip/rk3308.dtsi | 37 ++++++++++++++++++++++++ + 1 file changed, 37 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +index a185901aba9a..ce6f4a28d169 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +@@ -731,6 +731,17 @@ gmac: ethernet@ff4e0000 { + status = "disabled"; + }; + ++ sfc: spi@ff4c0000 { ++ compatible = "rockchip,sfc"; ++ reg = <0x0 0xff4c0000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; ++ clock-names = "clk_sfc", "hclk_sfc"; ++ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; ++ pinctrl-names = "default"; ++ status = "disabled"; ++ }; ++ + cru: clock-controller@ff500000 { + compatible = "rockchip,rk3308-cru"; + reg = <0x0 0xff500000 0x0 0x1000>; +@@ -1004,6 +1015,32 @@ flash_bus8: flash-bus8 { + }; + }; + ++ sfc { ++ sfc_bus4: sfc-bus4 { ++ rockchip,pins = ++ <3 RK_PA0 3 &pcfg_pull_none>, ++ <3 RK_PA1 3 &pcfg_pull_none>, ++ <3 RK_PA2 3 &pcfg_pull_none>, ++ <3 RK_PA3 3 &pcfg_pull_none>; ++ }; ++ ++ sfc_bus2: sfc-bus2 { ++ rockchip,pins = ++ <3 RK_PA0 3 &pcfg_pull_none>, ++ <3 RK_PA1 3 &pcfg_pull_none>; ++ }; ++ ++ sfc_cs0: sfc-cs0 { ++ rockchip,pins = ++ <3 RK_PA4 3 &pcfg_pull_none>; ++ }; ++ ++ sfc_clk: sfc-clk { ++ rockchip,pins = ++ <3 RK_PA5 3 &pcfg_pull_none>; ++ }; ++ }; ++ + gmac { + rmii_pins: rmii-pins { + rockchip,pins = + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Thu, 12 Aug 2021 21:46:39 +0800 +Subject: [PATCH] arm64: dts: rockchip: Enable SFC for Odroid Go Advance + +This enables the Rockchip Serial Flash Controller for the Odroid Go +Advance. Note that while the attached SPI NOR flash and the controller +both support quad read mode, only 2 of the required 4 pins are present. +The rx bus width is set to 2 for this reason, and tx bus width is set +to 1 for compatibility reasons. + +Signed-off-by: Chris Morgan +Signed-off-by: Jon Lin +Link: https://lore.kernel.org/r/20210812134639.31586-2-jon.lin@rock-chips.com +Signed-off-by: Heiko Stuebner +--- + .../boot/dts/rockchip/rk3326-odroid-go2.dts | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +index 7fc674a99a6c..35218c2771a2 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts +@@ -517,6 +517,22 @@ &sdmmc { + status = "okay"; + }; + ++&sfc { ++ pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <108000000>; ++ spi-rx-bus-width = <2>; ++ spi-tx-bus-width = <1>; ++ }; ++}; ++ + &tsadc { + status = "okay"; + }; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Thu, 12 Aug 2021 21:45:41 +0800 +Subject: [PATCH] spi: rockchip-sfc: Bindings for Rockchip serial flash + controller + +Add bindings for the Rockchip serial flash controller. New device +specific parameter of rockchip,sfc-no-dma included in documentation. + +Signed-off-by: Chris Morgan +Signed-off-by: Jon Lin +Tested-by: Peter Geis +Link: https://lore.kernel.org/r/20210812134546.31340-2-jon.lin@rock-chips.com +Signed-off-by: Mark Brown +--- + .../devicetree/bindings/spi/rockchip-sfc.yaml | 91 +++++++++++++++++++ + 1 file changed, 91 insertions(+) + create mode 100644 Documentation/devicetree/bindings/spi/rockchip-sfc.yaml + +diff --git a/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml +new file mode 100644 +index 000000000000..339fb39529f3 +--- /dev/null ++++ b/Documentation/devicetree/bindings/spi/rockchip-sfc.yaml +@@ -0,0 +1,91 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Rockchip Serial Flash Controller (SFC) ++ ++maintainers: ++ - Heiko Stuebner ++ - Chris Morgan ++ ++allOf: ++ - $ref: spi-controller.yaml# ++ ++properties: ++ compatible: ++ const: rockchip,sfc ++ description: ++ The rockchip sfc controller is a standalone IP with version register, ++ and the driver can handle all the feature difference inside the IP ++ depending on the version register. ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: Bus Clock ++ - description: Module Clock ++ ++ clock-names: ++ items: ++ - const: clk_sfc ++ - const: hclk_sfc ++ ++ power-domains: ++ maxItems: 1 ++ ++ rockchip,sfc-no-dma: ++ description: Disable DMA and utilize FIFO mode only ++ type: boolean ++ ++patternProperties: ++ "^flash@[0-3]$": ++ type: object ++ properties: ++ reg: ++ minimum: 0 ++ maximum: 3 ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ ++ sfc: spi@ff3a0000 { ++ compatible = "rockchip,sfc"; ++ reg = <0xff3a0000 0x4000>; ++ interrupts = ; ++ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; ++ clock-names = "clk_sfc", "hclk_sfc"; ++ pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>; ++ pinctrl-names = "default"; ++ power-domains = <&power PX30_PD_MMC_NAND>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <108000000>; ++ spi-rx-bus-width = <2>; ++ spi-tx-bus-width = <2>; ++ }; ++ }; ++ ++... + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Chris Morgan +Date: Thu, 12 Aug 2021 21:45:42 +0800 +Subject: [PATCH] spi: rockchip-sfc: add rockchip serial flash controller + +Add the rockchip serial flash controller (SFC) driver. + +Signed-off-by: Chris Morgan +Signed-off-by: Jon Lin +Tested-by: Peter Geis +Tested-by: Chris Morgan +Link: https://lore.kernel.org/r/20210812134546.31340-3-jon.lin@rock-chips.com +Signed-off-by: Mark Brown +--- + drivers/spi/Kconfig | 12 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-rockchip-sfc.c | 694 +++++++++++++++++++++++++++++++++ + 3 files changed, 707 insertions(+) + create mode 100644 drivers/spi/spi-rockchip-sfc.c + +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index e71a4c514f7b..83e352b0c8f9 100644 +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -658,6 +658,18 @@ config SPI_ROCKCHIP + The main usecase of this controller is to use spi flash as boot + device. + ++config SPI_ROCKCHIP_SFC ++ tristate "Rockchip Serial Flash Controller (SFC)" ++ depends on ARCH_ROCKCHIP || COMPILE_TEST ++ depends on HAS_IOMEM && HAS_DMA ++ help ++ This enables support for Rockchip serial flash controller. This ++ is a specialized controller used to access SPI flash on some ++ Rockchip SOCs. ++ ++ ROCKCHIP SFC supports DMA and PIO modes. When DMA is not available, ++ the driver automatically falls back to PIO mode. ++ + config SPI_RB4XX + tristate "Mikrotik RB4XX SPI master" + depends on SPI_MASTER && ATH79 +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index 13e54c45e9df..699db95c8441 100644 +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -95,6 +95,7 @@ obj-$(CONFIG_SPI_QCOM_GENI) += spi-geni-qcom.o + obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom-qspi.o + obj-$(CONFIG_SPI_QUP) += spi-qup.o + obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o ++obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o + obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o + obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o + obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o +diff --git a/drivers/spi/spi-rockchip-sfc.c b/drivers/spi/spi-rockchip-sfc.c +new file mode 100644 +index 000000000000..7c4d47fe80c2 +--- /dev/null ++++ b/drivers/spi/spi-rockchip-sfc.c +@@ -0,0 +1,694 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Rockchip Serial Flash Controller Driver ++ * ++ * Copyright (c) 2017-2021, Rockchip Inc. ++ * Author: Shawn Lin ++ * Chris Morgan ++ * Jon Lin ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* System control */ ++#define SFC_CTRL 0x0 ++#define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1) ++#define SFC_CTRL_CMD_BITS_SHIFT 8 ++#define SFC_CTRL_ADDR_BITS_SHIFT 10 ++#define SFC_CTRL_DATA_BITS_SHIFT 12 ++ ++/* Interrupt mask */ ++#define SFC_IMR 0x4 ++#define SFC_IMR_RX_FULL BIT(0) ++#define SFC_IMR_RX_UFLOW BIT(1) ++#define SFC_IMR_TX_OFLOW BIT(2) ++#define SFC_IMR_TX_EMPTY BIT(3) ++#define SFC_IMR_TRAN_FINISH BIT(4) ++#define SFC_IMR_BUS_ERR BIT(5) ++#define SFC_IMR_NSPI_ERR BIT(6) ++#define SFC_IMR_DMA BIT(7) ++ ++/* Interrupt clear */ ++#define SFC_ICLR 0x8 ++#define SFC_ICLR_RX_FULL BIT(0) ++#define SFC_ICLR_RX_UFLOW BIT(1) ++#define SFC_ICLR_TX_OFLOW BIT(2) ++#define SFC_ICLR_TX_EMPTY BIT(3) ++#define SFC_ICLR_TRAN_FINISH BIT(4) ++#define SFC_ICLR_BUS_ERR BIT(5) ++#define SFC_ICLR_NSPI_ERR BIT(6) ++#define SFC_ICLR_DMA BIT(7) ++ ++/* FIFO threshold level */ ++#define SFC_FTLR 0xc ++#define SFC_FTLR_TX_SHIFT 0 ++#define SFC_FTLR_TX_MASK 0x1f ++#define SFC_FTLR_RX_SHIFT 8 ++#define SFC_FTLR_RX_MASK 0x1f ++ ++/* Reset FSM and FIFO */ ++#define SFC_RCVR 0x10 ++#define SFC_RCVR_RESET BIT(0) ++ ++/* Enhanced mode */ ++#define SFC_AX 0x14 ++ ++/* Address Bit number */ ++#define SFC_ABIT 0x18 ++ ++/* Interrupt status */ ++#define SFC_ISR 0x1c ++#define SFC_ISR_RX_FULL_SHIFT BIT(0) ++#define SFC_ISR_RX_UFLOW_SHIFT BIT(1) ++#define SFC_ISR_TX_OFLOW_SHIFT BIT(2) ++#define SFC_ISR_TX_EMPTY_SHIFT BIT(3) ++#define SFC_ISR_TX_FINISH_SHIFT BIT(4) ++#define SFC_ISR_BUS_ERR_SHIFT BIT(5) ++#define SFC_ISR_NSPI_ERR_SHIFT BIT(6) ++#define SFC_ISR_DMA_SHIFT BIT(7) ++ ++/* FIFO status */ ++#define SFC_FSR 0x20 ++#define SFC_FSR_TX_IS_FULL BIT(0) ++#define SFC_FSR_TX_IS_EMPTY BIT(1) ++#define SFC_FSR_RX_IS_EMPTY BIT(2) ++#define SFC_FSR_RX_IS_FULL BIT(3) ++#define SFC_FSR_TXLV_MASK GENMASK(12, 8) ++#define SFC_FSR_TXLV_SHIFT 8 ++#define SFC_FSR_RXLV_MASK GENMASK(20, 16) ++#define SFC_FSR_RXLV_SHIFT 16 ++ ++/* FSM status */ ++#define SFC_SR 0x24 ++#define SFC_SR_IS_IDLE 0x0 ++#define SFC_SR_IS_BUSY 0x1 ++ ++/* Raw interrupt status */ ++#define SFC_RISR 0x28 ++#define SFC_RISR_RX_FULL BIT(0) ++#define SFC_RISR_RX_UNDERFLOW BIT(1) ++#define SFC_RISR_TX_OVERFLOW BIT(2) ++#define SFC_RISR_TX_EMPTY BIT(3) ++#define SFC_RISR_TRAN_FINISH BIT(4) ++#define SFC_RISR_BUS_ERR BIT(5) ++#define SFC_RISR_NSPI_ERR BIT(6) ++#define SFC_RISR_DMA BIT(7) ++ ++/* Version */ ++#define SFC_VER 0x2C ++#define SFC_VER_3 0x3 ++#define SFC_VER_4 0x4 ++#define SFC_VER_5 0x5 ++ ++/* Delay line controller resiter */ ++#define SFC_DLL_CTRL0 0x3C ++#define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) ++#define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU ++#define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU ++ ++/* Master trigger */ ++#define SFC_DMA_TRIGGER 0x80 ++#define SFC_DMA_TRIGGER_START 1 ++ ++/* Src or Dst addr for master */ ++#define SFC_DMA_ADDR 0x84 ++ ++/* Length control register extension 32GB */ ++#define SFC_LEN_CTRL 0x88 ++#define SFC_LEN_CTRL_TRB_SEL 1 ++#define SFC_LEN_EXT 0x8C ++ ++/* Command */ ++#define SFC_CMD 0x100 ++#define SFC_CMD_IDX_SHIFT 0 ++#define SFC_CMD_DUMMY_SHIFT 8 ++#define SFC_CMD_DIR_SHIFT 12 ++#define SFC_CMD_DIR_RD 0 ++#define SFC_CMD_DIR_WR 1 ++#define SFC_CMD_ADDR_SHIFT 14 ++#define SFC_CMD_ADDR_0BITS 0 ++#define SFC_CMD_ADDR_24BITS 1 ++#define SFC_CMD_ADDR_32BITS 2 ++#define SFC_CMD_ADDR_XBITS 3 ++#define SFC_CMD_TRAN_BYTES_SHIFT 16 ++#define SFC_CMD_CS_SHIFT 30 ++ ++/* Address */ ++#define SFC_ADDR 0x104 ++ ++/* Data */ ++#define SFC_DATA 0x108 ++ ++/* The controller and documentation reports that it supports up to 4 CS ++ * devices (0-3), however I have only been able to test a single CS (CS 0) ++ * due to the configuration of my device. ++ */ ++#define SFC_MAX_CHIPSELECT_NUM 4 ++ ++/* The SFC can transfer max 16KB - 1 at one time ++ * we set it to 15.5KB here for alignment. ++ */ ++#define SFC_MAX_IOSIZE_VER3 (512 * 31) ++ ++/* DMA is only enabled for large data transmission */ ++#define SFC_DMA_TRANS_THRETHOLD (0x40) ++ ++/* Maximum clock values from datasheet suggest keeping clock value under ++ * 150MHz. No minimum or average value is suggested. ++ */ ++#define SFC_MAX_SPEED (150 * 1000 * 1000) ++ ++struct rockchip_sfc { ++ struct device *dev; ++ void __iomem *regbase; ++ struct clk *hclk; ++ struct clk *clk; ++ u32 frequency; ++ /* virtual mapped addr for dma_buffer */ ++ void *buffer; ++ dma_addr_t dma_buffer; ++ struct completion cp; ++ bool use_dma; ++ u32 max_iosize; ++ u16 version; ++}; ++ ++static int rockchip_sfc_reset(struct rockchip_sfc *sfc) ++{ ++ int err; ++ u32 status; ++ ++ writel_relaxed(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR); ++ ++ err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status, ++ !(status & SFC_RCVR_RESET), 20, ++ jiffies_to_usecs(HZ)); ++ if (err) ++ dev_err(sfc->dev, "SFC reset never finished\n"); ++ ++ /* Still need to clear the masked interrupt from RISR */ ++ writel_relaxed(0xFFFFFFFF, sfc->regbase + SFC_ICLR); ++ ++ dev_dbg(sfc->dev, "reset\n"); ++ ++ return err; ++} ++ ++static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc) ++{ ++ return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff); ++} ++ ++static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc) ++{ ++ return SFC_MAX_IOSIZE_VER3; ++} ++ ++static void rockchip_sfc_irq_unmask(struct rockchip_sfc *sfc, u32 mask) ++{ ++ u32 reg; ++ ++ /* Enable transfer complete interrupt */ ++ reg = readl(sfc->regbase + SFC_IMR); ++ reg &= ~mask; ++ writel(reg, sfc->regbase + SFC_IMR); ++} ++ ++static void rockchip_sfc_irq_mask(struct rockchip_sfc *sfc, u32 mask) ++{ ++ u32 reg; ++ ++ /* Disable transfer finish interrupt */ ++ reg = readl(sfc->regbase + SFC_IMR); ++ reg |= mask; ++ writel(reg, sfc->regbase + SFC_IMR); ++} ++ ++static int rockchip_sfc_init(struct rockchip_sfc *sfc) ++{ ++ writel(0, sfc->regbase + SFC_CTRL); ++ writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); ++ rockchip_sfc_irq_mask(sfc, 0xFFFFFFFF); ++ if (rockchip_sfc_get_version(sfc) >= SFC_VER_4) ++ writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL); ++ ++ return 0; ++} ++ ++static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) ++{ ++ int ret = 0; ++ u32 status; ++ ++ ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, ++ status & SFC_FSR_TXLV_MASK, 0, ++ timeout_us); ++ if (ret) { ++ dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n"); ++ ++ ret = -ETIMEDOUT; ++ } ++ ++ return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT; ++} ++ ++static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us) ++{ ++ int ret = 0; ++ u32 status; ++ ++ ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status, ++ status & SFC_FSR_RXLV_MASK, 0, ++ timeout_us); ++ if (ret) { ++ dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n"); ++ ++ ret = -ETIMEDOUT; ++ } ++ ++ return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT; ++} ++ ++static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op) ++{ ++ if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) { ++ /* ++ * SFC not support output DUMMY cycles right after CMD cycles, so ++ * treat it as ADDR cycles. ++ */ ++ op->addr.nbytes = op->dummy.nbytes; ++ op->addr.buswidth = op->dummy.buswidth; ++ op->addr.val = 0xFFFFFFFFF; ++ ++ op->dummy.nbytes = 0; ++ } ++} ++ ++static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc, ++ struct spi_mem *mem, ++ const struct spi_mem_op *op, ++ u32 len) ++{ ++ u32 ctrl = 0, cmd = 0; ++ ++ /* set CMD */ ++ cmd = op->cmd.opcode; ++ ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT); ++ ++ /* set ADDR */ ++ if (op->addr.nbytes) { ++ if (op->addr.nbytes == 4) { ++ cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT; ++ } else if (op->addr.nbytes == 3) { ++ cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT; ++ } else { ++ cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT; ++ writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT); ++ } ++ ++ ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT); ++ } ++ ++ /* set DUMMY */ ++ if (op->dummy.nbytes) { ++ if (op->dummy.buswidth == 4) ++ cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT; ++ else if (op->dummy.buswidth == 2) ++ cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT; ++ else ++ cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT; ++ } ++ ++ /* set DATA */ ++ if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */ ++ writel(len, sfc->regbase + SFC_LEN_EXT); ++ else ++ cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT; ++ if (len) { ++ if (op->data.dir == SPI_MEM_DATA_OUT) ++ cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; ++ ++ ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT); ++ } ++ if (!len && op->addr.nbytes) ++ cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT; ++ ++ /* set the Controller */ ++ ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE; ++ cmd |= mem->spi->chip_select << SFC_CMD_CS_SHIFT; ++ ++ dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n", ++ op->addr.nbytes, op->addr.buswidth, ++ op->dummy.nbytes, op->dummy.buswidth); ++ dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n", ++ ctrl, cmd, op->addr.val, len); ++ ++ writel(ctrl, sfc->regbase + SFC_CTRL); ++ writel(cmd, sfc->regbase + SFC_CMD); ++ if (op->addr.nbytes) ++ writel(op->addr.val, sfc->regbase + SFC_ADDR); ++ ++ return 0; ++} ++ ++static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len) ++{ ++ u8 bytes = len & 0x3; ++ u32 dwords; ++ int tx_level; ++ u32 write_words; ++ u32 tmp = 0; ++ ++ dwords = len >> 2; ++ while (dwords) { ++ tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); ++ if (tx_level < 0) ++ return tx_level; ++ write_words = min_t(u32, tx_level, dwords); ++ iowrite32_rep(sfc->regbase + SFC_DATA, buf, write_words); ++ buf += write_words << 2; ++ dwords -= write_words; ++ } ++ ++ /* write the rest non word aligned bytes */ ++ if (bytes) { ++ tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000); ++ if (tx_level < 0) ++ return tx_level; ++ memcpy(&tmp, buf, bytes); ++ writel(tmp, sfc->regbase + SFC_DATA); ++ } ++ ++ return len; ++} ++ ++static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len) ++{ ++ u8 bytes = len & 0x3; ++ u32 dwords; ++ u8 read_words; ++ int rx_level; ++ int tmp; ++ ++ /* word aligned access only */ ++ dwords = len >> 2; ++ while (dwords) { ++ rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); ++ if (rx_level < 0) ++ return rx_level; ++ read_words = min_t(u32, rx_level, dwords); ++ ioread32_rep(sfc->regbase + SFC_DATA, buf, read_words); ++ buf += read_words << 2; ++ dwords -= read_words; ++ } ++ ++ /* read the rest non word aligned bytes */ ++ if (bytes) { ++ rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000); ++ if (rx_level < 0) ++ return rx_level; ++ tmp = readl(sfc->regbase + SFC_DATA); ++ memcpy(buf, &tmp, bytes); ++ } ++ ++ return len; ++} ++ ++static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len) ++{ ++ writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR); ++ writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR); ++ writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER); ++ ++ return len; ++} ++ ++static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc, ++ const struct spi_mem_op *op, u32 len) ++{ ++ dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len); ++ ++ if (op->data.dir == SPI_MEM_DATA_OUT) ++ return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len); ++ else ++ return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len); ++} ++ ++static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc, ++ const struct spi_mem_op *op, u32 len) ++{ ++ int ret; ++ ++ dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len); ++ ++ if (op->data.dir == SPI_MEM_DATA_OUT) ++ memcpy_toio(sfc->buffer, op->data.buf.out, len); ++ ++ ret = rockchip_sfc_fifo_transfer_dma(sfc, sfc->dma_buffer, len); ++ if (!wait_for_completion_timeout(&sfc->cp, msecs_to_jiffies(2000))) { ++ dev_err(sfc->dev, "DMA wait for transfer finish timeout\n"); ++ ret = -ETIMEDOUT; ++ } ++ rockchip_sfc_irq_mask(sfc, SFC_IMR_DMA); ++ if (op->data.dir == SPI_MEM_DATA_IN) ++ memcpy_fromio(op->data.buf.in, sfc->buffer, len); ++ ++ return ret; ++} ++ ++static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us) ++{ ++ int ret = 0; ++ u32 status; ++ ++ ret = readl_poll_timeout(sfc->regbase + SFC_SR, status, ++ !(status & SFC_SR_IS_BUSY), ++ 20, timeout_us); ++ if (ret) { ++ dev_err(sfc->dev, "wait sfc idle timeout\n"); ++ rockchip_sfc_reset(sfc); ++ ++ ret = -EIO; ++ } ++ ++ return ret; ++} ++ ++static int rockchip_sfc_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) ++{ ++ struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master); ++ u32 len = op->data.nbytes; ++ int ret; ++ ++ if (unlikely(mem->spi->max_speed_hz != sfc->frequency)) { ++ ret = clk_set_rate(sfc->clk, mem->spi->max_speed_hz); ++ if (ret) ++ return ret; ++ sfc->frequency = mem->spi->max_speed_hz; ++ dev_dbg(sfc->dev, "set_freq=%dHz real_freq=%ldHz\n", ++ sfc->frequency, clk_get_rate(sfc->clk)); ++ } ++ ++ rockchip_sfc_adjust_op_work((struct spi_mem_op *)op); ++ rockchip_sfc_xfer_setup(sfc, mem, op, len); ++ if (len) { ++ if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD) { ++ init_completion(&sfc->cp); ++ rockchip_sfc_irq_unmask(sfc, SFC_IMR_DMA); ++ ret = rockchip_sfc_xfer_data_dma(sfc, op, len); ++ } else { ++ ret = rockchip_sfc_xfer_data_poll(sfc, op, len); ++ } ++ ++ if (ret != len) { ++ dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir); ++ ++ return -EIO; ++ } ++ } ++ ++ return rockchip_sfc_xfer_done(sfc, 100000); ++} ++ ++static int rockchip_sfc_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) ++{ ++ struct rockchip_sfc *sfc = spi_master_get_devdata(mem->spi->master); ++ ++ op->data.nbytes = min(op->data.nbytes, sfc->max_iosize); ++ ++ return 0; ++} ++ ++static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = { ++ .exec_op = rockchip_sfc_exec_mem_op, ++ .adjust_op_size = rockchip_sfc_adjust_op_size, ++}; ++ ++static irqreturn_t rockchip_sfc_irq_handler(int irq, void *dev_id) ++{ ++ struct rockchip_sfc *sfc = dev_id; ++ u32 reg; ++ ++ reg = readl(sfc->regbase + SFC_RISR); ++ ++ /* Clear interrupt */ ++ writel_relaxed(reg, sfc->regbase + SFC_ICLR); ++ ++ if (reg & SFC_RISR_DMA) { ++ complete(&sfc->cp); ++ ++ return IRQ_HANDLED; ++ } ++ ++ return IRQ_NONE; ++} ++ ++static int rockchip_sfc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct spi_master *master; ++ struct resource *res; ++ struct rockchip_sfc *sfc; ++ int ret; ++ ++ master = devm_spi_alloc_master(&pdev->dev, sizeof(*sfc)); ++ if (!master) ++ return -ENOMEM; ++ ++ master->flags = SPI_MASTER_HALF_DUPLEX; ++ master->mem_ops = &rockchip_sfc_mem_ops; ++ master->dev.of_node = pdev->dev.of_node; ++ master->mode_bits = SPI_TX_QUAD | SPI_TX_DUAL | SPI_RX_QUAD | SPI_RX_DUAL; ++ master->max_speed_hz = SFC_MAX_SPEED; ++ master->num_chipselect = SFC_MAX_CHIPSELECT_NUM; ++ ++ sfc = spi_master_get_devdata(master); ++ sfc->dev = dev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ sfc->regbase = devm_ioremap_resource(dev, res); ++ if (IS_ERR(sfc->regbase)) ++ return PTR_ERR(sfc->regbase); ++ ++ sfc->clk = devm_clk_get(&pdev->dev, "clk_sfc"); ++ if (IS_ERR(sfc->clk)) { ++ dev_err(&pdev->dev, "Failed to get sfc interface clk\n"); ++ return PTR_ERR(sfc->clk); ++ } ++ ++ sfc->hclk = devm_clk_get(&pdev->dev, "hclk_sfc"); ++ if (IS_ERR(sfc->hclk)) { ++ dev_err(&pdev->dev, "Failed to get sfc ahb clk\n"); ++ return PTR_ERR(sfc->hclk); ++ } ++ ++ sfc->use_dma = !of_property_read_bool(sfc->dev->of_node, ++ "rockchip,sfc-no-dma"); ++ ++ if (sfc->use_dma) { ++ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); ++ if (ret) { ++ dev_warn(dev, "Unable to set dma mask\n"); ++ return ret; ++ } ++ ++ sfc->buffer = dmam_alloc_coherent(dev, SFC_MAX_IOSIZE_VER3, ++ &sfc->dma_buffer, ++ GFP_KERNEL); ++ if (!sfc->buffer) ++ return -ENOMEM; ++ } ++ ++ ret = clk_prepare_enable(sfc->hclk); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to enable ahb clk\n"); ++ goto err_hclk; ++ } ++ ++ ret = clk_prepare_enable(sfc->clk); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to enable interface clk\n"); ++ goto err_clk; ++ } ++ ++ /* Find the irq */ ++ ret = platform_get_irq(pdev, 0); ++ if (ret < 0) { ++ dev_err(dev, "Failed to get the irq\n"); ++ goto err_irq; ++ } ++ ++ ret = devm_request_irq(dev, ret, rockchip_sfc_irq_handler, ++ 0, pdev->name, sfc); ++ if (ret) { ++ dev_err(dev, "Failed to request irq\n"); ++ ++ return ret; ++ } ++ ++ ret = rockchip_sfc_init(sfc); ++ if (ret) ++ goto err_irq; ++ ++ sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc); ++ sfc->version = rockchip_sfc_get_version(sfc); ++ ++ ret = spi_register_master(master); ++ if (ret) ++ goto err_irq; ++ ++ return 0; ++ ++err_irq: ++ clk_disable_unprepare(sfc->clk); ++err_clk: ++ clk_disable_unprepare(sfc->hclk); ++err_hclk: ++ return ret; ++} ++ ++static int rockchip_sfc_remove(struct platform_device *pdev) ++{ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct rockchip_sfc *sfc = platform_get_drvdata(pdev); ++ ++ spi_unregister_master(master); ++ ++ clk_disable_unprepare(sfc->clk); ++ clk_disable_unprepare(sfc->hclk); ++ ++ return 0; ++} ++ ++static const struct of_device_id rockchip_sfc_dt_ids[] = { ++ { .compatible = "rockchip,sfc"}, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, rockchip_sfc_dt_ids); ++ ++static struct platform_driver rockchip_sfc_driver = { ++ .driver = { ++ .name = "rockchip-sfc", ++ .of_match_table = rockchip_sfc_dt_ids, ++ }, ++ .probe = rockchip_sfc_probe, ++ .remove = rockchip_sfc_remove, ++}; ++module_platform_driver(rockchip_sfc_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Rockchip Serial Flash Controller Driver"); ++MODULE_AUTHOR("Shawn Lin "); ++MODULE_AUTHOR("Chris Morgan "); ++MODULE_AUTHOR("Jon Lin "); diff --git a/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch new file mode 100644 index 0000000000..ac822561ca --- /dev/null +++ b/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch @@ -0,0 +1,437 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 10 Oct 2020 15:32:18 +0000 +Subject: [PATCH] phy/rockchip: inno-hdmi: use correct vco_div_5 macro on + rk3328 + +inno_hdmi_phy_rk3328_clk_set_rate() is using the RK3228 macro +when configuring vco_div_5 on RK3328. + +Fix this by using correct vco_div_5 macro for RK3328. + +Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") +Signed-off-by: Jonas Karlman +--- + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +index 80acca4e9e14..15339338aae3 100644 +--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +@@ -790,8 +790,8 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, + RK3328_PRE_PLL_POWER_DOWN); + + /* Configure pre-pll */ +- inno_update_bits(inno, 0xa0, RK3228_PCLK_VCO_DIV_5_MASK, +- RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en)); ++ inno_update_bits(inno, 0xa0, RK3328_PCLK_VCO_DIV_5_MASK, ++ RK3328_PCLK_VCO_DIV_5(cfg->vco_div_5_en)); + inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv)); + + val = RK3328_SPREAD_SPECTRUM_MOD_DISABLE; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Zheng Yang +Date: Sat, 10 Oct 2020 15:32:18 +0000 +Subject: [PATCH] phy/rockchip: inno-hdmi: round fractal pixclock in rk3328 + recalc_rate + +inno_hdmi_phy_rk3328_clk_recalc_rate() is returning a rate not found +in the pre pll config table when the fractal divider is used. +This can prevent proper power_on because a tmdsclock for the new rate +is not found in the pre pll config table. + +Fix this by saving and returning a rounded pixel rate that exist +in the pre pll config table. + +Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") +Signed-off-by: Zheng Yang +Signed-off-by: Jonas Karlman +--- + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +index 15339338aae3..15a008a1ac7b 100644 +--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +@@ -745,10 +745,12 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw, + do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2)); + } + +- inno->pixclock = vco; +- dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); ++ inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000; + +- return vco; ++ dev_dbg(inno->dev, "%s rate %lu vco %llu\n", ++ __func__, inno->pixclock, vco); ++ ++ return inno->pixclock; + } + + static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 10 Oct 2020 15:32:19 +0000 +Subject: [PATCH] phy/rockchip: inno-hdmi: remove unused no_c from rk3328 + recalc_rate + +no_c is not used in any calculation, lets remove it. + +Signed-off-by: Jonas Karlman +--- + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +index 15a008a1ac7b..4b936ca19920 100644 +--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +@@ -714,7 +714,7 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw, + { + struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); + unsigned long frac; +- u8 nd, no_a, no_b, no_c, no_d; ++ u8 nd, no_a, no_b, no_d; + u64 vco; + u16 nf; + +@@ -737,9 +737,6 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw, + no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK; + no_b >>= RK3328_PRE_PLL_PCLK_DIV_B_SHIFT; + no_b += 2; +- no_c = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_C_MASK; +- no_c >>= RK3328_PRE_PLL_PCLK_DIV_C_SHIFT; +- no_c = 1 << no_c; + no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK; + + do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2)); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sat, 10 Oct 2020 15:32:19 +0000 +Subject: [PATCH] phy/rockchip: inno-hdmi: do not power on rk3328 post pll on + reg write + +inno_write is used to configure 0xaa reg, that also hold the +POST_PLL_POWER_DOWN bit. +When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not +taken into consideration. + +Fix this by keeping the power down bit until configuration is complete. +Also reorder the reg write order for consistency. + +Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") +Signed-off-by: Jonas Karlman +--- + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +index 4b936ca19920..620961fcfc1d 100644 +--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +@@ -1020,9 +1020,10 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, + + inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); + if (cfg->postdiv == 1) { +- inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS); + inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | + RK3328_POST_PLL_PRE_DIV(cfg->prediv)); ++ inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS | ++ RK3328_POST_PLL_POWER_DOWN); + } else { + v = (cfg->postdiv / 2) - 1; + v &= RK3328_POST_PLL_POST_DIV_MASK; +@@ -1030,7 +1031,8 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, + inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | + RK3328_POST_PLL_PRE_DIV(cfg->prediv)); + inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE | +- RK3328_POST_PLL_REFCLK_SEL_TMDS); ++ RK3328_POST_PLL_REFCLK_SEL_TMDS | ++ RK3328_POST_PLL_POWER_DOWN); + } + + for (v = 0; v < 14; v++) + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Huicong Xu +Date: Sat, 10 Oct 2020 15:32:20 +0000 +Subject: [PATCH] phy/rockchip: inno-hdmi: force set_rate on power_on + +Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and +not in pixel clock rate. +When the hdmiphy clock is configured with the same pixel clock rate using +clk_set_rate() the clock framework do not signal the hdmi phy driver +to set_rate when switching between 8-bit and Deep Color. +This result in pre/post pll not being re-configured when switching between +regular 8-bit and Deep Color video formats. + +Fix this by calling set_rate in power_on to force pre pll re-configuration. + +Signed-off-by: Huicong Xu +Signed-off-by: Jonas Karlman +--- + drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +index 620961fcfc1d..2f01259823ea 100644 +--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +@@ -245,6 +245,7 @@ struct inno_hdmi_phy { + struct clk_hw hw; + struct clk *phyclk; + unsigned long pixclock; ++ unsigned long tmdsclock; + }; + + struct pre_pll_config { +@@ -485,6 +486,8 @@ static int inno_hdmi_phy_power_on(struct phy *phy) + + dev_dbg(inno->dev, "Inno HDMI PHY Power On\n"); + ++ inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000); ++ + ret = clk_prepare_enable(inno->phyclk); + if (ret) + return ret; +@@ -509,6 +512,8 @@ static int inno_hdmi_phy_power_off(struct phy *phy) + + clk_disable_unprepare(inno->phyclk); + ++ inno->tmdsclock = 0; ++ + dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); + + return 0; +@@ -628,6 +633,9 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, + dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", + __func__, rate, tmdsclock); + ++ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) ++ return 0; ++ + cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); + if (IS_ERR(cfg)) + return PTR_ERR(cfg); +@@ -670,6 +678,7 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, + } + + inno->pixclock = rate; ++ inno->tmdsclock = tmdsclock; + + return 0; + } +@@ -781,6 +790,9 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, + dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", + __func__, rate, tmdsclock); + ++ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) ++ return 0; ++ + cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); + if (IS_ERR(cfg)) + return PTR_ERR(cfg); +@@ -820,6 +832,7 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, + } + + inno->pixclock = rate; ++ inno->tmdsclock = tmdsclock; + + return 0; + } + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 17 Feb 2019 22:14:38 +0000 +Subject: [PATCH] mmc: core: set initial signal voltage on power off + +Some boards have SD card connectors where the power rail cannot be switched +off by the driver. If the card has not been power cycled, it may still be +using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling +will fail to boot from a UHS card that continue to use 1.8V signaling. + +Set initial signal voltage in mmc_power_off() to allow re-boot to function. + +This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288), +same issue have been seen on some Rockchip RK3399 boards. + +I am sending this as a RFC because I have no insights into SD/MMC subsystem, +this change fix a re-boot issue on my boards and does not break emmc/sdio. +Is this an acceptable workaround? Any advice is appreciated. + +Signed-off-by: Jonas Karlman +--- + drivers/mmc/core/core.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c +index 95fedcf56e4a..38e75b275bb6 100644 +--- a/drivers/mmc/core/core.c ++++ b/drivers/mmc/core/core.c +@@ -1355,6 +1355,14 @@ void mmc_power_off(struct mmc_host *host) + if (host->ios.power_mode == MMC_POWER_OFF) + return; + ++ mmc_set_initial_signal_voltage(host); ++ ++ /* ++ * This delay should be sufficient to allow the power supply ++ * to reach the minimum voltage. ++ */ ++ mmc_delay(host->ios.power_delay_ms); ++ + mmc_pwrseq_power_off(host); + + host->ios.clock = 0; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 23 Jun 2021 13:59:26 +0200 +Subject: [PATCH] arm64: dts: rockchip: Fix GPU register width for RK3328 + +As can be seen in RK3328's TRM the register range for the GPU is +0xff300000 to 0xff330000. +It would (and does in vendor kernel) overlap with the registers of +the HEVC encoder (node/driver do not exist yet in upstream kernel). +See already existing h265e_mmu node. + +Fixes: 752fbc0c8da7 ("arm64: dts: rockchip: add rk3328 mali gpu node") +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index becc1c61b182..5b2020590f53 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -599,7 +599,7 @@ saradc: adc@ff280000 { + + gpu: gpu@ff300000 { + compatible = "rockchip,rk3328-mali", "arm,mali-450"; +- reg = <0x0 0xff300000 0x0 0x40000>; ++ reg = <0x0 0xff300000 0x0 0x30000>; + interrupts = , + , + , + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 23 Jun 2021 16:59:18 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add sdmmc_ext for RK3328 + +RK3328 SoC has a fourth mmc controller called SDMMC_EXT. Some +boards have sdio wifi connected to it. In order to use it +one would have to add the pinctrls from sdmmc0ext group which +is done on board level. + +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index 5b2020590f53..df46edbec82c 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -975,6 +975,20 @@ usb_host0_ohci: usb@ff5d0000 { + status = "disabled"; + }; + ++ sdmmc_ext: mmc@ff5f0000 { ++ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; ++ reg = <0x0 0xff5f0000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, ++ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; ++ fifo-depth = <0x100>; ++ max-frequency = <150000000>; ++ resets = <&cru SRST_SDMMCEXT>; ++ reset-names = "reset"; ++ status = "disabled"; ++ }; ++ + usbdrd3: usb@ff600000 { + compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; + reg = <0x0 0xff600000 0x0 0x100000>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Wed, 23 Jun 2021 17:02:08 +0200 +Subject: [PATCH] arm64: dts: rockchip: Add sdmmc/sdio/emmc reset controls for + RK3328 + +The DW MCI controller driver will use them to reset the IP block before +initialisation. + +Fixes: d717f7352ec6 ("arm64: dts: rockchip: add sdmmc/sdio/emmc nodes for RK3328 SoCs") +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +index df46edbec82c..cfc57be009a6 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi +@@ -853,6 +853,8 @@ sdmmc: mmc@ff500000 { + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; ++ resets = <&cru SRST_MMC0>; ++ reset-names = "reset"; + status = "disabled"; + }; + +@@ -865,6 +867,8 @@ sdio: mmc@ff510000 { + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; ++ resets = <&cru SRST_SDIO>; ++ reset-names = "reset"; + status = "disabled"; + }; + +@@ -877,6 +881,8 @@ emmc: mmc@ff520000 { + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; ++ resets = <&cru SRST_EMMC>; ++ reset-names = "reset"; + status = "disabled"; + }; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 21 Aug 2021 19:13:31 +0200 +Subject: [PATCH] Commit a728c10dd62a ("arm64: dts: rockchip: remove + interrupt-names from iommu nodes") intended to remove the interrupt-names + property for the mmu nodes. It also removed them for the vpu node in + rk3399.dtsi which currently results in a non-working driver. Fix this by + re-adding them. + +Fixes: a728c10dd62a ("arm64: dts: rockchip: remove interrupt-names from iommu nodes") +Signed-off-by: Alex Bee +--- + arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +index 9db9484ca38f..44def886b391 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi +@@ -1240,6 +1240,7 @@ vpu: video-codec@ff650000 { + reg = <0x0 0xff650000 0x0 0x800>; + interrupts = , + ; ++ interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; diff --git a/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-next.patch b/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-next.patch deleted file mode 100644 index 234c257969..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-0003-rockchip-from-next.patch +++ /dev/null @@ -1,219 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Tue, 11 May 2021 17:13:34 -0400 -Subject: [PATCH] regulator: fan53555: only bind tcs4525 to correct chip id - -The tcs4525 regulator has a chip id of <12>. -Only allow the driver to bind to the correct chip id for safety, in -accordance with the other supported devices. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20210511211335.2935163-3-pgwipeout@gmail.com -Signed-off-by: Mark Brown ---- - drivers/regulator/fan53555.c | 25 ++++++++++++++++++------- - 1 file changed, 18 insertions(+), 7 deletions(-) - -diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c -index 26f06f685b1b..16f28f9df6a1 100644 ---- a/drivers/regulator/fan53555.c -+++ b/drivers/regulator/fan53555.c -@@ -89,6 +89,10 @@ enum { - FAN53555_CHIP_ID_08 = 8, - }; - -+enum { -+ TCS4525_CHIP_ID_12 = 12, -+}; -+ - /* IC mask revision */ - enum { - FAN53555_CHIP_REV_00 = 0x3, -@@ -368,14 +372,21 @@ static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di) - - static int fan53555_voltages_setup_tcs(struct fan53555_device_info *di) - { -- di->slew_reg = TCS4525_TIME; -- di->slew_mask = TCS_SLEW_MASK; -- di->slew_shift = TCS_SLEW_MASK; -+ switch (di->chip_id) { -+ case TCS4525_CHIP_ID_12: -+ di->slew_reg = TCS4525_TIME; -+ di->slew_mask = TCS_SLEW_MASK; -+ di->slew_shift = TCS_SLEW_MASK; - -- /* Init voltage range and step */ -- di->vsel_min = 600000; -- di->vsel_step = 6250; -- di->vsel_count = FAN53526_NVOLTAGES; -+ /* Init voltage range and step */ -+ di->vsel_min = 600000; -+ di->vsel_step = 6250; -+ di->vsel_count = FAN53526_NVOLTAGES; -+ break; -+ default: -+ dev_err(di->dev, "Chip ID %d not supported!\n", di->chip_id); -+ return -EINVAL; -+ } - - return 0; - } - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Tue, 11 May 2021 17:13:35 -0400 -Subject: [PATCH] regulator: fan53555: fix tcs4525 function names - -The tcs4525 is based off the fan53526. -Rename the tcs4525 functions to align with this. - -Signed-off-by: Peter Geis -Link: https://lore.kernel.org/r/20210511211335.2935163-4-pgwipeout@gmail.com -Signed-off-by: Mark Brown ---- - drivers/regulator/fan53555.c | 18 +++++++++--------- - 1 file changed, 9 insertions(+), 9 deletions(-) - -diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c -index 16f28f9df6a1..2695be617373 100644 ---- a/drivers/regulator/fan53555.c -+++ b/drivers/regulator/fan53555.c -@@ -67,7 +67,7 @@ enum fan53555_vendor { - FAN53526_VENDOR_FAIRCHILD = 0, - FAN53555_VENDOR_FAIRCHILD, - FAN53555_VENDOR_SILERGY, -- FAN53555_VENDOR_TCS, -+ FAN53526_VENDOR_TCS, - }; - - enum { -@@ -233,7 +233,7 @@ static int fan53555_set_ramp(struct regulator_dev *rdev, int ramp) - slew_rate_t = slew_rates; - slew_rate_n = ARRAY_SIZE(slew_rates); - break; -- case FAN53555_VENDOR_TCS: -+ case FAN53526_VENDOR_TCS: - slew_rate_t = tcs_slew_rates; - slew_rate_n = ARRAY_SIZE(tcs_slew_rates); - break; -@@ -370,7 +370,7 @@ static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di) - return 0; - } - --static int fan53555_voltages_setup_tcs(struct fan53555_device_info *di) -+static int fan53526_voltages_setup_tcs(struct fan53555_device_info *di) - { - switch (di->chip_id) { - case TCS4525_CHIP_ID_12: -@@ -420,7 +420,7 @@ static int fan53555_device_setup(struct fan53555_device_info *di, - return -EINVAL; - } - break; -- case FAN53555_VENDOR_TCS: -+ case FAN53526_VENDOR_TCS: - switch (pdata->sleep_vsel_id) { - case FAN53555_VSEL_ID_0: - di->sleep_reg = TCS4525_VSEL0; -@@ -459,7 +459,7 @@ static int fan53555_device_setup(struct fan53555_device_info *di, - di->mode_reg = di->vol_reg; - di->mode_mask = VSEL_MODE; - break; -- case FAN53555_VENDOR_TCS: -+ case FAN53526_VENDOR_TCS: - di->mode_reg = TCS4525_COMMAND; - - switch (pdata->sleep_vsel_id) { -@@ -487,8 +487,8 @@ static int fan53555_device_setup(struct fan53555_device_info *di, - case FAN53555_VENDOR_SILERGY: - ret = fan53555_voltages_setup_silergy(di); - break; -- case FAN53555_VENDOR_TCS: -- ret = fan53555_voltages_setup_tcs(di); -+ case FAN53526_VENDOR_TCS: -+ ret = fan53526_voltages_setup_tcs(di); - break; - default: - dev_err(di->dev, "vendor %d not supported!\n", di->vendor); -@@ -563,7 +563,7 @@ static const struct of_device_id __maybe_unused fan53555_dt_ids[] = { - .data = (void *)FAN53555_VENDOR_SILERGY, - }, { - .compatible = "tcs,tcs4525", -- .data = (void *)FAN53555_VENDOR_TCS -+ .data = (void *)FAN53526_VENDOR_TCS - }, - { } - }; -@@ -671,7 +671,7 @@ static const struct i2c_device_id fan53555_id[] = { - .driver_data = FAN53555_VENDOR_SILERGY - }, { - .name = "tcs4525", -- .driver_data = FAN53555_VENDOR_TCS -+ .driver_data = FAN53526_VENDOR_TCS - }, - { }, - }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Axel Lin -Date: Mon, 17 May 2021 09:03:17 +0800 -Subject: [PATCH] regulator: fan53555: Fix slew_shift setting for tcs4525 - -Fix trivial copy-paste mistake. - -Signed-off-by: Axel Lin -Link: https://lore.kernel.org/r/20210517010318.1027949-1-axel.lin@ingics.com -Signed-off-by: Mark Brown ---- - drivers/regulator/fan53555.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c -index 2695be617373..d582ef3a3aeb 100644 ---- a/drivers/regulator/fan53555.c -+++ b/drivers/regulator/fan53555.c -@@ -376,7 +376,7 @@ static int fan53526_voltages_setup_tcs(struct fan53555_device_info *di) - case TCS4525_CHIP_ID_12: - di->slew_reg = TCS4525_TIME; - di->slew_mask = TCS_SLEW_MASK; -- di->slew_shift = TCS_SLEW_MASK; -+ di->slew_shift = TCS_SLEW_SHIFT; - - /* Init voltage range and step */ - di->vsel_min = 600000; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Axel Lin -Date: Mon, 17 May 2021 09:03:18 +0800 -Subject: [PATCH] regulator: fan53555: Cleanup unused define and redundant - assignment - -TCS_VSEL_NSEL_MASK is not used so remove it. -Also remove redundant assignment for di->slew_reg. - -Signed-off-by: Axel Lin -Link: https://lore.kernel.org/r/20210517010318.1027949-2-axel.lin@ingics.com -Signed-off-by: Mark Brown ---- - drivers/regulator/fan53555.c | 2 -- - 1 file changed, 2 deletions(-) - -diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c -index d582ef3a3aeb..f3f49cf3731b 100644 ---- a/drivers/regulator/fan53555.c -+++ b/drivers/regulator/fan53555.c -@@ -56,7 +56,6 @@ - #define FAN53555_NVOLTAGES 64 /* Numbers of voltages */ - #define FAN53526_NVOLTAGES 128 - --#define TCS_VSEL_NSEL_MASK 0x7f - #define TCS_VSEL0_MODE (1 << 7) - #define TCS_VSEL1_MODE (1 << 6) - -@@ -362,7 +361,6 @@ static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di) - return -EINVAL; - } - di->slew_reg = FAN53555_CONTROL; -- di->slew_reg = FAN53555_CONTROL; - di->slew_mask = CTL_SLEW_MASK; - di->slew_shift = CTL_SLEW_SHIFT; - di->vsel_count = FAN53555_NVOLTAGES; diff --git a/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch deleted file mode 100644 index 2f04777360..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-0004-rockchip-from-list.patch +++ /dev/null @@ -1,1184 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 10 Oct 2020 15:32:18 +0000 -Subject: [PATCH] phy/rockchip: inno-hdmi: use correct vco_div_5 macro on - rk3328 - -inno_hdmi_phy_rk3328_clk_set_rate() is using the RK3228 macro -when configuring vco_div_5 on RK3328. - -Fix this by using correct vco_div_5 macro for RK3328. - -Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") -Signed-off-by: Jonas Karlman ---- - drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -index 9ca20c947283..b0ac1d3ee390 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -@@ -790,8 +790,8 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, - RK3328_PRE_PLL_POWER_DOWN); - - /* Configure pre-pll */ -- inno_update_bits(inno, 0xa0, RK3228_PCLK_VCO_DIV_5_MASK, -- RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en)); -+ inno_update_bits(inno, 0xa0, RK3328_PCLK_VCO_DIV_5_MASK, -+ RK3328_PCLK_VCO_DIV_5(cfg->vco_div_5_en)); - inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv)); - - val = RK3328_SPREAD_SPECTRUM_MOD_DISABLE; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Zheng Yang -Date: Sat, 10 Oct 2020 15:32:18 +0000 -Subject: [PATCH] phy/rockchip: inno-hdmi: round fractal pixclock in rk3328 - recalc_rate - -inno_hdmi_phy_rk3328_clk_recalc_rate() is returning a rate not found -in the pre pll config table when the fractal divider is used. -This can prevent proper power_on because a tmdsclock for the new rate -is not found in the pre pll config table. - -Fix this by saving and returning a rounded pixel rate that exist -in the pre pll config table. - -Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") -Signed-off-by: Zheng Yang -Signed-off-by: Jonas Karlman ---- - drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 8 +++++--- - 1 file changed, 5 insertions(+), 3 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -index b0ac1d3ee390..093d2334e8cd 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -@@ -745,10 +745,12 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw, - do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2)); - } - -- inno->pixclock = vco; -- dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock); -+ inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000; - -- return vco; -+ dev_dbg(inno->dev, "%s rate %lu vco %llu\n", -+ __func__, inno->pixclock, vco); -+ -+ return inno->pixclock; - } - - static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 10 Oct 2020 15:32:19 +0000 -Subject: [PATCH] phy/rockchip: inno-hdmi: remove unused no_c from rk3328 - recalc_rate - -no_c is not used in any calculation, lets remove it. - -Signed-off-by: Jonas Karlman ---- - drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 5 +---- - 1 file changed, 1 insertion(+), 4 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -index 093d2334e8cd..06db69c8373e 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -@@ -714,7 +714,7 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw, - { - struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw); - unsigned long frac; -- u8 nd, no_a, no_b, no_c, no_d; -+ u8 nd, no_a, no_b, no_d; - u64 vco; - u16 nf; - -@@ -737,9 +737,6 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw, - no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK; - no_b >>= RK3328_PRE_PLL_PCLK_DIV_B_SHIFT; - no_b += 2; -- no_c = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_C_MASK; -- no_c >>= RK3328_PRE_PLL_PCLK_DIV_C_SHIFT; -- no_c = 1 << no_c; - no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK; - - do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2)); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 10 Oct 2020 15:32:19 +0000 -Subject: [PATCH] phy/rockchip: inno-hdmi: do not power on rk3328 post pll on - reg write - -inno_write is used to configure 0xaa reg, that also hold the -POST_PLL_POWER_DOWN bit. -When POST_PLL_REFCLK_SEL_TMDS is configured the power down bit is not -taken into consideration. - -Fix this by keeping the power down bit until configuration is complete. -Also reorder the reg write order for consistency. - -Fixes: 53706a116863 ("phy: add Rockchip Innosilicon hdmi phy") -Signed-off-by: Jonas Karlman ---- - drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -index 06db69c8373e..3a59a6da0440 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -@@ -1020,9 +1020,10 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, - - inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv)); - if (cfg->postdiv == 1) { -- inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS); - inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | - RK3328_POST_PLL_PRE_DIV(cfg->prediv)); -+ inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS | -+ RK3328_POST_PLL_POWER_DOWN); - } else { - v = (cfg->postdiv / 2) - 1; - v &= RK3328_POST_PLL_POST_DIV_MASK; -@@ -1030,7 +1031,8 @@ inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno, - inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) | - RK3328_POST_PLL_PRE_DIV(cfg->prediv)); - inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE | -- RK3328_POST_PLL_REFCLK_SEL_TMDS); -+ RK3328_POST_PLL_REFCLK_SEL_TMDS | -+ RK3328_POST_PLL_POWER_DOWN); - } - - for (v = 0; v < 14; v++) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Huicong Xu -Date: Sat, 10 Oct 2020 15:32:20 +0000 -Subject: [PATCH] phy/rockchip: inno-hdmi: force set_rate on power_on - -Regular 8-bit and Deep Color video formats mainly differ in TMDS rate and -not in pixel clock rate. -When the hdmiphy clock is configured with the same pixel clock rate using -clk_set_rate() the clock framework do not signal the hdmi phy driver -to set_rate when switching between 8-bit and Deep Color. -This result in pre/post pll not being re-configured when switching between -regular 8-bit and Deep Color video formats. - -Fix this by calling set_rate in power_on to force pre pll re-configuration. - -Signed-off-by: Huicong Xu -Signed-off-by: Jonas Karlman ---- - drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -index 3a59a6da0440..3719309ad0d0 100644 ---- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -@@ -245,6 +245,7 @@ struct inno_hdmi_phy { - struct clk_hw hw; - struct clk *phyclk; - unsigned long pixclock; -+ unsigned long tmdsclock; - }; - - struct pre_pll_config { -@@ -485,6 +486,8 @@ static int inno_hdmi_phy_power_on(struct phy *phy) - - dev_dbg(inno->dev, "Inno HDMI PHY Power On\n"); - -+ inno->plat_data->clk_ops->set_rate(&inno->hw, inno->pixclock, 24000000); -+ - ret = clk_prepare_enable(inno->phyclk); - if (ret) - return ret; -@@ -509,6 +512,8 @@ static int inno_hdmi_phy_power_off(struct phy *phy) - - clk_disable_unprepare(inno->phyclk); - -+ inno->tmdsclock = 0; -+ - dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n"); - - return 0; -@@ -628,6 +633,9 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, - dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", - __func__, rate, tmdsclock); - -+ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) -+ return 0; -+ - cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); - if (IS_ERR(cfg)) - return PTR_ERR(cfg); -@@ -670,6 +678,7 @@ static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, - } - - inno->pixclock = rate; -+ inno->tmdsclock = tmdsclock; - - return 0; - } -@@ -781,6 +790,9 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, - dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n", - __func__, rate, tmdsclock); - -+ if (inno->pixclock == rate && inno->tmdsclock == tmdsclock) -+ return 0; -+ - cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate); - if (IS_ERR(cfg)) - return PTR_ERR(cfg); -@@ -820,6 +832,7 @@ static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw, - } - - inno->pixclock = rate; -+ inno->tmdsclock = tmdsclock; - - return 0; - } - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Mon, 16 Nov 2020 15:17:33 +0000 -Subject: [PATCH] phy: rockchip: add rockchip usb3 innosilicon phy driver - -The innosilicon based usb3 phy used in rockchip devices such as the rk3328 is bugged, requiring special handling. -The following erata have been observed: - - usb3 device disconnect events are not detected by the controller - - usb2 hubs with no devices attached do not trigger disconnect events when removed - - interrupts are not reliable - -To work around these issue we implement polling of the usb2 and usb3 status. -On usb3 disconnection we reset the usb3 phy which triggers the disconnect event. -On usb2 disconnection we have to force reset the whole controller. -This requires a handoff to a special dwc3 device driver. - -This has been tested on the rk3328-roc-cc board with the following devices: - - usb2 only device - - usb3 only device - - usb2 only hub without devices - - usb3 hub without devices - - usb2 hub with devices - - usb3 hub with devices - -Signed-off-by: Peter Geis ---- - drivers/phy/rockchip/Kconfig | 9 + - drivers/phy/rockchip/Makefile | 1 + - drivers/phy/rockchip/phy-rockchip-inno-usb3.c | 425 ++++++++++++++++++ - 3 files changed, 435 insertions(+) - create mode 100644 drivers/phy/rockchip/phy-rockchip-inno-usb3.c - -diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig -index c2f22f90736c..ce16e0877354 100644 ---- a/drivers/phy/rockchip/Kconfig -+++ b/drivers/phy/rockchip/Kconfig -@@ -47,6 +47,15 @@ config PHY_ROCKCHIP_INNO_USB2 - help - Support for Rockchip USB2.0 PHY with Innosilicon IP block. - -+config PHY_ROCKCHIP_INNO_USB3 -+ tristate "Rockchip INNO USB3PHY Driver" -+ depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF -+ depends on COMMON_CLK -+ depends on USB_SUPPORT -+ select USB_COMMON -+ help -+ Support for Rockchip USB3.0 PHY with Innosilicon IP block. -+ - config PHY_ROCKCHIP_INNO_DSIDPHY - tristate "Rockchip Innosilicon MIPI/LVDS/TTL PHY driver" - depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF -diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile -index c3cfc7f0af5c..738e3574a722 100644 ---- a/drivers/phy/rockchip/Makefile -+++ b/drivers/phy/rockchip/Makefile -@@ -5,6 +5,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o - obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o - obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o - obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o -+obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB3) += phy-rockchip-inno-usb3.o - obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o - obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o - obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o -diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb3.c b/drivers/phy/rockchip/phy-rockchip-inno-usb3.c -new file mode 100644 -index 000000000000..6e4aa2f0ba46 ---- /dev/null -+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb3.c -@@ -0,0 +1,425 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define USB3_STATUS_REG 0x284 -+#define USB2_STATUS_REG 0x30 -+#define USB3_CONN_BIT BIT(0) -+#define USB2_CONN_BIT BIT(7) -+#define USB2_STATE_SHIFT 6 -+#define REG_WRITE_MASK GENMASK(31, 16) -+ -+struct rockchip_usb3phy_port{ -+ struct device *dev; -+ struct regmap *regmap; -+ struct usb_phy phy; -+ struct rockchip_usb3phy *parent; -+ unsigned char type; -+}; -+ -+enum usb3phy_mode { -+ PHY_IDLE = 0, -+ PHY_USB3, -+ PHY_USB2, -+ PHY_COMBO -+}; -+ -+struct rockchip_usb3phy { -+ struct device *dev; -+ struct regmap *regmap; -+ struct clk *clk_pipe; -+ struct clk *clk_otg; -+ struct reset_control *u3por_rst; -+ struct reset_control *u2por_rst; -+ struct reset_control *pipe_rst; -+ struct reset_control *utmi_rst; -+ struct reset_control *pipe_apb_rst; -+ struct reset_control *utmi_apb_rst; -+ struct rockchip_usb3phy_port port_pipe; -+ struct rockchip_usb3phy_port port_utmi; -+ struct work_struct usb_phy_work; -+ struct notifier_block nb; -+ enum usb3phy_mode mode; -+ struct mutex lock; -+}; -+ -+static int rockchip_usb3phy_reset(struct rockchip_usb3phy *usb3phy, bool reset, enum usb3phy_mode mode) -+{ -+ if (reset == true) { -+ if ((mode == PHY_USB2) | (mode == PHY_COMBO)){ -+ clk_disable_unprepare(usb3phy->clk_otg); -+ reset_control_assert(usb3phy->utmi_rst); -+ reset_control_assert(usb3phy->u2por_rst); -+ } -+ if ((mode == PHY_USB3) | (mode == PHY_COMBO)){ -+ clk_disable_unprepare(usb3phy->clk_pipe); -+ reset_control_assert(usb3phy->pipe_rst); -+ reset_control_assert(usb3phy->u3por_rst); -+ } -+ } -+ -+ if (reset == false) { -+ if ((mode == PHY_USB2) | (mode == PHY_COMBO)){ -+ reset_control_deassert(usb3phy->u2por_rst); -+ udelay(1000); -+ clk_prepare_enable(usb3phy->clk_otg); -+ udelay(500); -+ reset_control_deassert(usb3phy->utmi_rst); -+ } -+ if ((mode == PHY_USB3) | (mode == PHY_COMBO)){ -+ reset_control_deassert(usb3phy->u3por_rst); -+ udelay(500); -+ clk_prepare_enable(usb3phy->clk_pipe); -+ udelay(1000); -+ reset_control_deassert(usb3phy->pipe_rst); -+ } -+ } -+ -+ return 0; -+} -+ -+static void rockchip_usb3phy_work(struct work_struct *work) -+{ -+ struct rockchip_usb3phy *usb3phy = container_of(work, struct rockchip_usb3phy, usb_phy_work); -+ struct rockchip_usb3phy_port *port_pipe = &usb3phy->port_pipe; -+ struct rockchip_usb3phy_port *port_utmi = &usb3phy->port_utmi; -+ int usb2, usb3, tmp, state; -+ -+ mutex_lock(&usb3phy->lock); -+ -+ regmap_read(port_pipe->regmap, USB3_STATUS_REG, &tmp); -+ usb3 = tmp & USB3_CONN_BIT; -+ regmap_read(usb3phy->regmap, USB2_STATUS_REG, &tmp); -+ usb2 = ((tmp & USB2_CONN_BIT) ^ USB2_CONN_BIT ) >> USB2_STATE_SHIFT; -+ state = (usb3 | usb2); -+ dev_dbg(usb3phy->dev, "mode %i, state %i\n", usb3phy->mode, state); -+ -+ if (usb3phy->mode == state) -+ /* not our device */ -+ goto out; -+ -+ if (usb2) { -+ usb3phy->mode = PHY_USB2; -+ dev_dbg(usb3phy->dev, "usb3phy utmi polling started\n"); -+ regmap_read_poll_timeout(usb3phy->regmap, USB2_STATUS_REG, tmp, (tmp & USB2_CONN_BIT), 2000, 0); -+ state = ((tmp & USB2_CONN_BIT) ^ USB2_CONN_BIT ) >> USB2_STATE_SHIFT; -+ dev_dbg(usb3phy->dev, "usb3phy utmi polling completed\n"); -+ -+ atomic_notifier_call_chain(&port_utmi->phy.notifier, 0, NULL); -+ goto out; -+ } -+ -+ if (usb3) { -+ dev_dbg(usb3phy->dev, "usb3phy pipe polling started\n"); -+ regmap_read_poll_timeout(port_pipe->regmap, USB3_STATUS_REG, tmp, !(tmp & USB3_CONN_BIT), 2000, 0); -+ dev_dbg(usb3phy->dev, "usb3phy pipe polling completed\n"); -+ -+ rockchip_usb3phy_reset(usb3phy, true, PHY_USB3); -+ udelay(500); -+ rockchip_usb3phy_reset(usb3phy, false, PHY_USB3); -+ udelay(500); -+ -+ goto out; -+ } -+ -+out: -+ usb3phy->mode = PHY_IDLE; -+ mutex_unlock(&usb3phy->lock); -+ return; -+} -+ -+static int rockchip_usb3phy_parse_dt(struct rockchip_usb3phy *usb3phy, struct device *dev) -+{ -+ usb3phy->clk_pipe = devm_clk_get(dev, "usb3phy-pipe"); -+ if (IS_ERR(usb3phy->clk_pipe)) { -+ dev_err(dev, "could not get usb3phy pipe clock\n"); -+ return PTR_ERR(usb3phy->clk_pipe); -+ } -+ -+ usb3phy->clk_otg = devm_clk_get(dev, "usb3phy-otg"); -+ if (IS_ERR(usb3phy->clk_otg)) { -+ dev_err(dev, "could not get usb3phy otg clock\n"); -+ return PTR_ERR(usb3phy->clk_otg); -+ } -+ -+ usb3phy->u2por_rst = devm_reset_control_get(dev, "usb3phy-u2-por"); -+ if (IS_ERR(usb3phy->u2por_rst)) { -+ dev_err(dev, "no usb3phy-u2-por reset control found\n"); -+ return PTR_ERR(usb3phy->u2por_rst); -+ } -+ -+ usb3phy->u3por_rst = devm_reset_control_get(dev, "usb3phy-u3-por"); -+ if (IS_ERR(usb3phy->u3por_rst)) { -+ dev_err(dev, "no usb3phy-u3-por reset control found\n"); -+ return PTR_ERR(usb3phy->u3por_rst); -+ } -+ -+ usb3phy->pipe_rst = devm_reset_control_get(dev, "usb3phy-pipe-mac"); -+ if (IS_ERR(usb3phy->pipe_rst)) { -+ dev_err(dev, "no usb3phy_pipe_mac reset control found\n"); -+ return PTR_ERR(usb3phy->pipe_rst); -+ } -+ -+ usb3phy->utmi_rst = devm_reset_control_get(dev, "usb3phy-utmi-mac"); -+ if (IS_ERR(usb3phy->utmi_rst)) { -+ dev_err(dev, "no usb3phy-utmi-mac reset control found\n"); -+ return PTR_ERR(usb3phy->utmi_rst); -+ } -+ -+ usb3phy->pipe_apb_rst = devm_reset_control_get(dev, "usb3phy-pipe-apb"); -+ if (IS_ERR(usb3phy->pipe_apb_rst)) { -+ dev_err(dev, "no usb3phy-pipe-apb reset control found\n"); -+ return PTR_ERR(usb3phy->pipe_apb_rst); -+ } -+ -+ usb3phy->utmi_apb_rst = devm_reset_control_get(dev, "usb3phy-utmi-apb"); -+ if (IS_ERR(usb3phy->utmi_apb_rst)) { -+ dev_err(dev, "no usb3phy-utmi-apb reset control found\n"); -+ return PTR_ERR(usb3phy->utmi_apb_rst); -+ } -+ -+ return 0; -+} -+ -+static int rockchip_usb3phy_notify(struct notifier_block *nb, unsigned long action, void *data) -+{ -+ struct rockchip_usb3phy *usb3phy = container_of(nb, struct rockchip_usb3phy, nb); -+ switch (action) { -+ case USB_DEVICE_ADD: -+ dev_dbg(usb3phy->dev, "notified of device add\n"); -+ if (!(mutex_is_locked(&usb3phy->lock))) -+ schedule_work(&usb3phy->usb_phy_work); -+ return NOTIFY_OK; -+ } -+ return NOTIFY_DONE; -+} -+ -+static int rockchip_usb3phy_init(struct usb_phy *phy) -+{ -+ struct rockchip_usb3phy_port *usb3phy_port = container_of(phy, struct rockchip_usb3phy_port, phy); -+ struct rockchip_usb3phy *usb3phy = usb3phy_port->parent; -+ -+ dev_warn(usb3phy->dev, "usb3phy_init %s\n", phy->label); -+ if (phy->type == USB_PHY_TYPE_USB3){ -+ rockchip_usb3phy_reset(usb3phy, false, PHY_USB3); -+ udelay(100); /* let it stabilize */ -+ usb3phy->nb.notifier_call = rockchip_usb3phy_notify; -+ usb_register_notify(&usb3phy->nb); -+ } -+ if (phy->type == USB_PHY_TYPE_USB2){ -+ rockchip_usb3phy_reset(usb3phy, false, PHY_USB2); -+ udelay(100); /* let it stabilize */ -+ } -+ -+ return 0; -+} -+ -+static void rockchip_usb3phy_shutdown(struct usb_phy *phy) -+{ -+ struct rockchip_usb3phy_port *usb3phy_port = container_of(phy, struct rockchip_usb3phy_port, phy); -+ struct rockchip_usb3phy *usb3phy = usb3phy_port->parent; -+ -+ dev_dbg(usb3phy->dev, "usb3phy_shutdown\n"); -+ if (phy->type == USB_PHY_TYPE_USB3){ -+ rockchip_usb3phy_reset(usb3phy, false, PHY_USB3); -+ usb_unregister_notify(&usb3phy->nb); -+ } -+ if (phy->type == USB_PHY_TYPE_USB2){ -+ rockchip_usb3phy_reset(usb3phy, false, PHY_USB2); -+ } -+} -+ -+static const struct regmap_config rockchip_usb3phy_port_regmap_config = { -+ .reg_bits = 32, -+ .val_bits = 32, -+ .reg_stride = 4, -+ .max_register = 0x1000, -+}; -+ -+static const struct regmap_config rockchip_usb3phy_regmap_config = { -+ .reg_bits = 32, -+ .val_bits = 32, -+ .reg_stride = 4, -+ .max_register = 0x1000, -+ .write_flag_mask = REG_WRITE_MASK, -+}; -+ -+static int rockchip_usb3phy_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct device_node *np = dev->of_node; -+ struct rockchip_usb3phy *usb3phy; -+ struct rockchip_usb3phy_port *usb3phy_port; -+ struct regmap_config regmap_config = rockchip_usb3phy_regmap_config; -+ struct regmap_config regmap_port_config = rockchip_usb3phy_port_regmap_config; -+ const struct of_device_id *match; -+ void __iomem *base; -+ int ret; -+ -+ match = of_match_device(dev->driver->of_match_table, dev); -+ if (!match) { -+ dev_err(dev, "phy node not assigned\n"); -+ return -EINVAL; -+ } -+ -+ if (of_node_name_eq(np, "usb3-phy")) { -+ dev_dbg(dev, "Probe usb3phy main block\n"); -+ -+ usb3phy = devm_kzalloc(dev, sizeof(*usb3phy), GFP_KERNEL); -+ if (!usb3phy) -+ return -ENOMEM; -+ -+ ret = rockchip_usb3phy_parse_dt(usb3phy, dev); -+ if (ret) { -+ dev_err(dev, "parse dt failed %i\n", ret); -+ return ret; -+ } -+ -+ base = devm_of_iomap(dev, np, 0, NULL); -+ if (IS_ERR(base)) { -+ dev_err(dev, "failed port ioremap\n"); -+ return PTR_ERR(base); -+ } -+ -+ regmap_config.name = np->name; -+ -+ usb3phy->regmap = devm_regmap_init_mmio(dev, base, ®map_config); -+ if (IS_ERR(usb3phy->regmap)) { -+ dev_err(dev, "regmap init failed\n"); -+ return PTR_ERR(usb3phy->regmap); -+ } -+ -+ usb3phy->dev = dev; -+ platform_set_drvdata(pdev, usb3phy); -+ -+ /* place block in reset */ -+ reset_control_assert(usb3phy->pipe_rst); -+ reset_control_assert(usb3phy->utmi_rst); -+ reset_control_assert(usb3phy->u3por_rst); -+ reset_control_assert(usb3phy->u2por_rst); -+ reset_control_assert(usb3phy->pipe_apb_rst); -+ reset_control_assert(usb3phy->utmi_apb_rst); -+ -+ udelay(20); -+ -+ /* take apb interface out of reset */ -+ reset_control_deassert(usb3phy->utmi_apb_rst); -+ reset_control_deassert(usb3phy->pipe_apb_rst); -+ -+ usb3phy->mode = PHY_IDLE; -+ INIT_WORK(&usb3phy->usb_phy_work, rockchip_usb3phy_work); -+ dev_dbg(dev, "Completed usb3phy core probe \n"); -+ -+ return devm_of_platform_populate(&pdev->dev); -+ } -+ -+ /* probe the actual ports */ -+ usb3phy = platform_get_drvdata(of_find_device_by_node(np->parent)); -+ -+ if (of_node_name_eq(np, "utmi")) { -+ usb3phy_port = &usb3phy->port_utmi; -+ usb3phy_port->phy.label = "usb2-phy"; -+ usb3phy_port->phy.type = USB_PHY_TYPE_USB2; -+ } -+ else if (of_node_name_eq(np, "pipe")) { -+ usb3phy_port = &usb3phy->port_pipe; -+ usb3phy_port->phy.label = "usb3-phy"; -+ usb3phy_port->phy.type = USB_PHY_TYPE_USB3; -+ } -+ else { -+ dev_err(dev, "unknown child node port type %s\n", np->name); -+ return -EINVAL; -+ } -+ -+ usb3phy_port->dev = dev; -+ -+ base = devm_of_iomap(dev, np, 0, NULL); -+ if (IS_ERR(base)) { -+ dev_err(dev, "failed port ioremap\n"); -+ return PTR_ERR(base); -+ } -+ -+ regmap_port_config.name = np->name; -+ -+ usb3phy_port->regmap = devm_regmap_init_mmio(dev, base, ®map_port_config); -+ if (IS_ERR(usb3phy_port->regmap)) { -+ dev_err(dev, "regmap init failed\n"); -+ return PTR_ERR(usb3phy_port->regmap); -+ } -+ -+ usb3phy_port->phy.dev = dev; -+ usb3phy_port->phy.init = rockchip_usb3phy_init; -+ usb3phy_port->phy.shutdown = rockchip_usb3phy_shutdown; -+ usb3phy_port->parent = usb3phy; -+ -+ ret = usb_add_phy_dev(&usb3phy_port->phy); -+ if (ret) { -+ dev_err(dev, "add usb phy failed %i\n", ret); -+ return ret; -+ } -+ -+ mutex_init(&usb3phy->lock); -+ -+ dev_info(dev, "Completed usb3phy %s port init\n", usb3phy_port->phy.label); -+ return 0; -+} -+ -+ -+static int rockchip_usb3phy_remove(struct platform_device *pdev) -+{ -+ struct rockchip_usb3phy *usb3phy = platform_get_drvdata(pdev); -+ struct rockchip_usb3phy_port *port_pipe = &usb3phy->port_pipe; -+ struct rockchip_usb3phy_port *port_utmi = &usb3phy->port_utmi; -+ -+ if (&port_pipe->phy.head) -+ usb_remove_phy(&port_pipe->phy); -+ if (&port_utmi->phy.head) -+ usb_remove_phy(&port_utmi->phy); -+ -+ reset_control_assert(usb3phy->pipe_apb_rst); -+ reset_control_assert(usb3phy->utmi_apb_rst); -+ -+ return 0; -+} -+ -+static const struct of_device_id rockchip_usb3phy_dt_ids[] = { -+ { .compatible = "rockchip,rk3328-usb3phy", }, -+ { .compatible = "rockchip,rk3328-usb3phy-utmi", }, -+ { .compatible = "rockchip,rk3328-usb3phy-pipe", }, -+ { /* sentinel */ } -+}; -+ -+MODULE_DEVICE_TABLE(of, rockchip_usb3phy_dt_ids); -+ -+static struct platform_driver rockchip_usb3phy_driver = { -+ .probe = rockchip_usb3phy_probe, -+ .remove = rockchip_usb3phy_remove, -+ .driver = { -+ .name = "rockchip-usb3-phy", -+ .of_match_table = rockchip_usb3phy_dt_ids, -+ }, -+}; -+ -+module_platform_driver(rockchip_usb3phy_driver); -+ -+MODULE_AUTHOR("Peter Geis "); -+MODULE_DESCRIPTION("Rockchip USB 3 PHY driver"); -+MODULE_LICENSE("GPL v2"); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Mon, 16 Nov 2020 15:17:34 +0000 -Subject: [PATCH] usb: dwc3: add rockchip innosilicon usb3 glue layer - -This adds the handler glue for the rockchip usb3 innosilicon phy driver. -This driver attaches to the phy driver through the notification system. -When a usb2 disconnect event occurs this driver tears down the hcd and rebuilds it manually. -This is to work around the usb2 controller becoming wedged and not detecting any usb2 devices after a usb2 hub is removed. - -It is based off work originally done by rockchip. - -Signed-off-by: Peter Geis ---- - drivers/usb/dwc3/Kconfig | 10 + - drivers/usb/dwc3/Makefile | 1 + - drivers/usb/dwc3/dwc3-rockchip-inno.c | 271 ++++++++++++++++++++++++++ - 3 files changed, 282 insertions(+) - create mode 100644 drivers/usb/dwc3/dwc3-rockchip-inno.c - -diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig -index 7a2304565a73..2e33a45f55ff 100644 ---- a/drivers/usb/dwc3/Kconfig -+++ b/drivers/usb/dwc3/Kconfig -@@ -139,4 +139,14 @@ config USB_DWC3_QCOM - for peripheral mode support. - Say 'Y' or 'M' if you have one such device. - -+config USB_DWC3_ROCKCHIP_INNO -+ tristate "Rockchip Platforms with INNO PHY" -+ depends on OF && COMMON_CLK && ARCH_ROCKCHIP -+ depends on USB=y || USB=USB_DWC3 -+ default USB_DWC3 -+ help -+ Support of USB2/3 functionality in Rockchip platforms -+ with INNO USB 3.0 PHY IP inside. -+ say 'Y' or 'M' if you have one such device. -+ - endif -diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile -index ae86da0dc5bd..f5eb7de10128 100644 ---- a/drivers/usb/dwc3/Makefile -+++ b/drivers/usb/dwc3/Makefile -@@ -51,4 +51,5 @@ obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o - obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o - obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o - obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o - obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o -+obj-$(CONFIG_USB_DWC3_ROCKCHIP_INNO) += dwc3-rockchip-inno.o -diff --git a/drivers/usb/dwc3/dwc3-rockchip-inno.c b/drivers/usb/dwc3/dwc3-rockchip-inno.c -new file mode 100644 -index 000000000000..7007ddbcbdae ---- /dev/null -+++ b/drivers/usb/dwc3/dwc3-rockchip-inno.c -@@ -0,0 +1,271 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * dwc3-rockchip-inno.c - DWC3 glue layer for Rockchip devices with Innosilicon based PHY -+ * -+ * Based on dwc3-of-simple.c -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "core.h" -+#include "../host/xhci.h" -+ -+ -+struct dwc3_rk_inno { -+ struct device *dev; -+ struct clk_bulk_data *clks; -+ struct dwc3 *dwc; -+ struct usb_phy *phy; -+ struct notifier_block reset_nb; -+ struct work_struct reset_work; -+ struct mutex lock; -+ int num_clocks; -+ struct reset_control *resets; -+}; -+ -+static int dwc3_rk_inno_host_reset_notifier(struct notifier_block *nb, unsigned long event, void *data) -+{ -+ struct dwc3_rk_inno *rk_inno = container_of(nb, struct dwc3_rk_inno, reset_nb); -+ -+ schedule_work(&rk_inno->reset_work); -+ -+ return NOTIFY_DONE; -+} -+ -+static void dwc3_rk_inno_host_reset_work(struct work_struct *work) -+{ -+ struct dwc3_rk_inno *rk_inno = container_of(work, struct dwc3_rk_inno, reset_work); -+ struct usb_hcd *hcd = dev_get_drvdata(&rk_inno->dwc->xhci->dev); -+ struct usb_hcd *shared_hcd = hcd->shared_hcd; -+ struct xhci_hcd *xhci = hcd_to_xhci(hcd); -+ unsigned int count = 0; -+ -+ mutex_lock(&rk_inno->lock); -+ -+ if (hcd->state != HC_STATE_HALT) { -+ usb_remove_hcd(shared_hcd); -+ usb_remove_hcd(hcd); -+ } -+ -+ if (rk_inno->phy) -+ usb_phy_shutdown(rk_inno->phy); -+ -+ while (hcd->state != HC_STATE_HALT) { -+ if (++count > 1000) { -+ dev_err(rk_inno->dev, "wait for HCD remove 1s timeout!\n"); -+ break; -+ } -+ usleep_range(1000, 1100); -+ } -+ -+ if (hcd->state == HC_STATE_HALT) { -+ xhci->shared_hcd = shared_hcd; -+ usb_add_hcd(hcd, hcd->irq, IRQF_SHARED); -+ usb_add_hcd(shared_hcd, hcd->irq, IRQF_SHARED); -+ } -+ -+ if (rk_inno->phy) -+ usb_phy_init(rk_inno->phy); -+ -+ mutex_unlock(&rk_inno->lock); -+ dev_dbg(rk_inno->dev, "host reset complete\n"); -+} -+ -+static int dwc3_rk_inno_probe(struct platform_device *pdev) -+{ -+ struct dwc3_rk_inno *rk_inno; -+ struct device *dev = &pdev->dev; -+ struct device_node *np = dev->of_node, *child, *node; -+ struct platform_device *child_pdev; -+ -+ int ret; -+ -+ rk_inno = devm_kzalloc(dev, sizeof(*rk_inno), GFP_KERNEL); -+ if (!rk_inno) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, rk_inno); -+ rk_inno->dev = dev; -+ -+ rk_inno->resets = of_reset_control_array_get(np, false, true, -+ true); -+ if (IS_ERR(rk_inno->resets)) { -+ ret = PTR_ERR(rk_inno->resets); -+ dev_err(dev, "failed to get device resets, err=%d\n", ret); -+ return ret; -+ } -+ -+ ret = reset_control_deassert(rk_inno->resets); -+ if (ret) -+ goto err_resetc_put; -+ -+ ret = clk_bulk_get_all(rk_inno->dev, &rk_inno->clks); -+ if (ret < 0) -+ goto err_resetc_assert; -+ -+ rk_inno->num_clocks = ret; -+ ret = clk_bulk_prepare_enable(rk_inno->num_clocks, rk_inno->clks); -+ if (ret) -+ goto err_resetc_assert; -+ -+ ret = of_platform_populate(np, NULL, NULL, dev); -+ if (ret) -+ goto err_clk_put; -+ -+ child = of_get_child_by_name(np, "dwc3"); -+ if (!child) { -+ dev_err(dev, "failed to find dwc3 core node\n"); -+ ret = -ENODEV; -+ goto err_plat_depopulate; -+ } -+ -+ child_pdev = of_find_device_by_node(child); -+ if (!child_pdev) { -+ dev_err(dev, "failed to get dwc3 core device\n"); -+ ret = -ENODEV; -+ goto err_plat_depopulate; -+ } -+ -+ rk_inno->dwc = platform_get_drvdata(child_pdev); -+ if (!rk_inno->dwc || !rk_inno->dwc->xhci) { -+ ret = -EPROBE_DEFER; -+ goto err_plat_depopulate; -+ } -+ -+ node = of_parse_phandle(child, "usb-phy", 0); -+ INIT_WORK(&rk_inno->reset_work, dwc3_rk_inno_host_reset_work); -+ rk_inno->reset_nb.notifier_call = dwc3_rk_inno_host_reset_notifier; -+ rk_inno->phy = devm_usb_get_phy_by_node(dev, node, &rk_inno->reset_nb); -+ of_node_put(node); -+ mutex_init(&rk_inno->lock); -+ -+ pm_runtime_set_active(dev); -+ pm_runtime_enable(dev); -+ pm_runtime_get_sync(dev); -+ -+ return 0; -+ -+err_plat_depopulate: -+ of_platform_depopulate(dev); -+ -+err_clk_put: -+ clk_bulk_disable_unprepare(rk_inno->num_clocks, rk_inno->clks); -+ clk_bulk_put_all(rk_inno->num_clocks, rk_inno->clks); -+ -+err_resetc_assert: -+ reset_control_assert(rk_inno->resets); -+ -+err_resetc_put: -+ reset_control_put(rk_inno->resets); -+ return ret; -+} -+ -+static void __dwc3_rk_inno_teardown(struct dwc3_rk_inno *rk_inno) -+{ -+ of_platform_depopulate(rk_inno->dev); -+ -+ clk_bulk_disable_unprepare(rk_inno->num_clocks, rk_inno->clks); -+ clk_bulk_put_all(rk_inno->num_clocks, rk_inno->clks); -+ rk_inno->num_clocks = 0; -+ -+ reset_control_assert(rk_inno->resets); -+ -+ reset_control_put(rk_inno->resets); -+ -+ pm_runtime_disable(rk_inno->dev); -+ pm_runtime_put_noidle(rk_inno->dev); -+ pm_runtime_set_suspended(rk_inno->dev); -+} -+ -+static int dwc3_rk_inno_remove(struct platform_device *pdev) -+{ -+ struct dwc3_rk_inno *rk_inno = platform_get_drvdata(pdev); -+ -+ __dwc3_rk_inno_teardown(rk_inno); -+ -+ return 0; -+} -+ -+static void dwc3_rk_inno_shutdown(struct platform_device *pdev) -+{ -+ struct dwc3_rk_inno *rk_inno = platform_get_drvdata(pdev); -+ -+ __dwc3_rk_inno_teardown(rk_inno); -+} -+ -+static int __maybe_unused dwc3_rk_inno_runtime_suspend(struct device *dev) -+{ -+ struct dwc3_rk_inno *rk_inno = dev_get_drvdata(dev); -+ -+ clk_bulk_disable(rk_inno->num_clocks, rk_inno->clks); -+ -+ return 0; -+} -+ -+static int __maybe_unused dwc3_rk_inno_runtime_resume(struct device *dev) -+{ -+ struct dwc3_rk_inno *rk_inno = dev_get_drvdata(dev); -+ -+ return clk_bulk_enable(rk_inno->num_clocks, rk_inno->clks); -+} -+ -+static int __maybe_unused dwc3_rk_inno_suspend(struct device *dev) -+{ -+ struct dwc3_rk_inno *rk_inno = dev_get_drvdata(dev); -+ -+ reset_control_assert(rk_inno->resets); -+ -+ return 0; -+} -+ -+static int __maybe_unused dwc3_rk_inno_resume(struct device *dev) -+{ -+ struct dwc3_rk_inno *rk_inno = dev_get_drvdata(dev); -+ -+ reset_control_deassert(rk_inno->resets); -+ -+ return 0; -+} -+ -+static const struct dev_pm_ops dwc3_rk_inno_dev_pm_ops = { -+ SET_SYSTEM_SLEEP_PM_OPS(dwc3_rk_inno_suspend, dwc3_rk_inno_resume) -+ SET_RUNTIME_PM_OPS(dwc3_rk_inno_runtime_suspend, -+ dwc3_rk_inno_runtime_resume, NULL) -+}; -+ -+static const struct of_device_id of_dwc3_rk_inno_match[] = { -+ { .compatible = "rockchip,rk3328-dwc3" }, -+ { /* Sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, of_dwc3_rk_inno_match); -+ -+static struct platform_driver dwc3_rk_inno_driver = { -+ .probe = dwc3_rk_inno_probe, -+ .remove = dwc3_rk_inno_remove, -+ .shutdown = dwc3_rk_inno_shutdown, -+ .driver = { -+ .name = "dwc3-rk-inno", -+ .of_match_table = of_dwc3_rk_inno_match, -+ .pm = &dwc3_rk_inno_dev_pm_ops, -+ }, -+}; -+ -+module_platform_driver(dwc3_rk_inno_driver); -+MODULE_LICENSE("GPL v2"); -+MODULE_DESCRIPTION("DesignWare USB3 Rockchip Innosilicon Glue Layer"); -+MODULE_AUTHOR("Peter Geis "); - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 17 Feb 2019 22:14:38 +0000 -Subject: [PATCH] mmc: core: set initial signal voltage on power off - -Some boards have SD card connectors where the power rail cannot be switched -off by the driver. If the card has not been power cycled, it may still be -using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling -will fail to boot from a UHS card that continue to use 1.8V signaling. - -Set initial signal voltage in mmc_power_off() to allow re-boot to function. - -This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288), -same issue have been seen on some Rockchip RK3399 boards. - -I am sending this as a RFC because I have no insights into SD/MMC subsystem, -this change fix a re-boot issue on my boards and does not break emmc/sdio. -Is this an acceptable workaround? Any advice is appreciated. - -Signed-off-by: Jonas Karlman ---- - drivers/mmc/core/core.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c -index eaf4810fe656..6f8ea06b187b 100644 ---- a/drivers/mmc/core/core.c -+++ b/drivers/mmc/core/core.c -@@ -1349,6 +1349,14 @@ void mmc_power_off(struct mmc_host *host) - if (host->ios.power_mode == MMC_POWER_OFF) - return; - -+ mmc_set_initial_signal_voltage(host); -+ -+ /* -+ * This delay should be sufficient to allow the power supply -+ * to reach the minimum voltage. -+ */ -+ mmc_delay(host->ios.power_delay_ms); -+ - mmc_pwrseq_power_off(host); - - host->ios.clock = 0; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Rudi Heitbaum -Date: Fri, 28 May 2021 10:19:50 +0000 -Subject: [PATCH] regulator: fan53555: add tcs4526 - -For rk3399pro boards the tcs4526 regulator supports the vdd_gpu -regulator. The tcs4526 regulator has a chip id of <0>. -Add the compatibile tcs,tcs4526 - -without this patch, the dmesg output is: - fan53555-regulator 0-0010: Chip ID 0 not supported! - fan53555-regulator 0-0010: Failed to setup device! - fan53555-regulator: probe of 0-0010 failed with error -22 -with this patch, the dmesg output is: - vdd_gpu: supplied by vcc5v0_sys - -The regulators are described as: -- Dedicated power management IC TCS4525 -- Lithium battery protection chip TCS4526 - -This has been tested with a Radxa Rock Pi N10. - -Signed-off-by: Rudi Heitbaum ---- - drivers/regulator/fan53555.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/drivers/regulator/fan53555.c b/drivers/regulator/fan53555.c -index f3f49cf3731b..bc8242e1dd0f 100644 ---- a/drivers/regulator/fan53555.c -+++ b/drivers/regulator/fan53555.c -@@ -92,6 +92,10 @@ enum { - TCS4525_CHIP_ID_12 = 12, - }; - -+enum { -+ TCS4526_CHIP_ID_00 = 0, -+}; -+ - /* IC mask revision */ - enum { - FAN53555_CHIP_REV_00 = 0x3, -@@ -372,6 +376,7 @@ static int fan53526_voltages_setup_tcs(struct fan53555_device_info *di) - { - switch (di->chip_id) { - case TCS4525_CHIP_ID_12: -+ case TCS4526_CHIP_ID_00: - di->slew_reg = TCS4525_TIME; - di->slew_mask = TCS_SLEW_MASK; - di->slew_shift = TCS_SLEW_SHIFT; -@@ -562,6 +567,9 @@ static const struct of_device_id __maybe_unused fan53555_dt_ids[] = { - }, { - .compatible = "tcs,tcs4525", - .data = (void *)FAN53526_VENDOR_TCS -+ }, { -+ .compatible = "tcs,tcs4526", -+ .data = (void *)FAN53526_VENDOR_TCS - }, - { } - }; -@@ -670,6 +678,9 @@ static const struct i2c_device_id fan53555_id[] = { - }, { - .name = "tcs4525", - .driver_data = FAN53526_VENDOR_TCS -+ }, { -+ .name = "tcs4526", -+ .driver_data = FAN53526_VENDOR_TCS - }, - { }, - }; diff --git a/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-5.15.patch b/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-5.15.patch new file mode 100644 index 0000000000..c54e0ae4f6 --- /dev/null +++ b/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-5.15.patch @@ -0,0 +1,1303 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Mon, 19 Jul 2021 22:52:33 +0200 +Subject: [PATCH] media: hantro: vp8: Move noisy WARN_ON to vpu_debug + +When the VP8 decoders can't find a reference frame, +the driver falls back to the current output frame. + +This will probably produce some undesirable results, +leading to frame corruption, but shouldn't cause +noisy warnings. + +Signed-off-by: Ezequiel Garcia +Acked-by: Nicolas Dufresne +Tested-by: Alex Bee +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/staging/media/hantro/hantro_g1_vp8_dec.c | 13 ++++++++++--- + .../staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c | 13 ++++++++++--- + 2 files changed, 20 insertions(+), 6 deletions(-) + +diff --git a/drivers/staging/media/hantro/hantro_g1_vp8_dec.c b/drivers/staging/media/hantro/hantro_g1_vp8_dec.c +index 96622a7f8279..2afd5996d75f 100644 +--- a/drivers/staging/media/hantro/hantro_g1_vp8_dec.c ++++ b/drivers/staging/media/hantro/hantro_g1_vp8_dec.c +@@ -376,12 +376,17 @@ static void cfg_ref(struct hantro_ctx *ctx, + vb2_dst = hantro_get_dst_buf(ctx); + + ref = hantro_get_ref(ctx, hdr->last_frame_ts); +- if (!ref) ++ if (!ref) { ++ vpu_debug(0, "failed to find last frame ts=%llu\n", ++ hdr->last_frame_ts); + ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); ++ } + vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(0)); + + ref = hantro_get_ref(ctx, hdr->golden_frame_ts); +- WARN_ON(!ref && hdr->golden_frame_ts); ++ if (!ref && hdr->golden_frame_ts) ++ vpu_debug(0, "failed to find golden frame ts=%llu\n", ++ hdr->golden_frame_ts); + if (!ref) + ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); + if (hdr->flags & V4L2_VP8_FRAME_FLAG_SIGN_BIAS_GOLDEN) +@@ -389,7 +394,9 @@ static void cfg_ref(struct hantro_ctx *ctx, + vdpu_write_relaxed(vpu, ref, G1_REG_ADDR_REF(4)); + + ref = hantro_get_ref(ctx, hdr->alt_frame_ts); +- WARN_ON(!ref && hdr->alt_frame_ts); ++ if (!ref && hdr->alt_frame_ts) ++ vpu_debug(0, "failed to find alt frame ts=%llu\n", ++ hdr->alt_frame_ts); + if (!ref) + ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); + if (hdr->flags & V4L2_VP8_FRAME_FLAG_SIGN_BIAS_ALT) +diff --git a/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c b/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c +index 951b55f58a61..704607511b57 100644 +--- a/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c ++++ b/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c +@@ -453,12 +453,17 @@ static void cfg_ref(struct hantro_ctx *ctx, + vb2_dst = hantro_get_dst_buf(ctx); + + ref = hantro_get_ref(ctx, hdr->last_frame_ts); +- if (!ref) ++ if (!ref) { ++ vpu_debug(0, "failed to find last frame ts=%llu\n", ++ hdr->last_frame_ts); + ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); ++ } + vdpu_write_relaxed(vpu, ref, VDPU_REG_VP8_ADDR_REF0); + + ref = hantro_get_ref(ctx, hdr->golden_frame_ts); +- WARN_ON(!ref && hdr->golden_frame_ts); ++ if (!ref && hdr->golden_frame_ts) ++ vpu_debug(0, "failed to find golden frame ts=%llu\n", ++ hdr->golden_frame_ts); + if (!ref) + ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); + if (hdr->flags & V4L2_VP8_FRAME_FLAG_SIGN_BIAS_GOLDEN) +@@ -466,7 +471,9 @@ static void cfg_ref(struct hantro_ctx *ctx, + vdpu_write_relaxed(vpu, ref, VDPU_REG_VP8_ADDR_REF2_5(2)); + + ref = hantro_get_ref(ctx, hdr->alt_frame_ts); +- WARN_ON(!ref && hdr->alt_frame_ts); ++ if (!ref && hdr->alt_frame_ts) ++ vpu_debug(0, "failed to find alt frame ts=%llu\n", ++ hdr->alt_frame_ts); + if (!ref) + ref = vb2_dma_contig_plane_dma_addr(&vb2_dst->vb2_buf, 0); + if (hdr->flags & V4L2_VP8_FRAME_FLAG_SIGN_BIAS_ALT) + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Mon, 19 Jul 2021 22:52:34 +0200 +Subject: [PATCH] media: hantro: Make struct hantro_variant.init() optional + +The hantro_variant.init() function is there for platforms +to perform hardware-specific initialization, such as +clock rate bumping. + +Not all platforms require it, so make it optional. + +Signed-off-by: Ezequiel Garcia +Tested-by: Alex Bee +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/staging/media/hantro/hantro.h | 4 ++-- + drivers/staging/media/hantro/hantro_drv.c | 10 ++++++---- + drivers/staging/media/hantro/sama5d4_vdec_hw.c | 6 ------ + 3 files changed, 8 insertions(+), 12 deletions(-) + +diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h +index a70c386de6f1..c2e2dca38628 100644 +--- a/drivers/staging/media/hantro/hantro.h ++++ b/drivers/staging/media/hantro/hantro.h +@@ -61,8 +61,8 @@ struct hantro_irq { + * @num_postproc_fmts: Number of post-processor formats. + * @codec: Supported codecs + * @codec_ops: Codec ops. +- * @init: Initialize hardware. +- * @runtime_resume: reenable hardware after power gating ++ * @init: Initialize hardware, optional. ++ * @runtime_resume: reenable hardware after power gating, optional. + * @irqs: array of irq names and interrupt handlers + * @num_irqs: number of irqs in the array + * @clk_names: array of clock names +diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c +index 31d8449ca1d2..9b5415176bfe 100644 +--- a/drivers/staging/media/hantro/hantro_drv.c ++++ b/drivers/staging/media/hantro/hantro_drv.c +@@ -942,10 +942,12 @@ static int hantro_probe(struct platform_device *pdev) + } + } + +- ret = vpu->variant->init(vpu); +- if (ret) { +- dev_err(&pdev->dev, "Failed to init VPU hardware\n"); +- return ret; ++ if (vpu->variant->init) { ++ ret = vpu->variant->init(vpu); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to init VPU hardware\n"); ++ return ret; ++ } + } + + pm_runtime_set_autosuspend_delay(vpu->dev, 100); +diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c +index 58ae72c2b723..9c3b8cd0b239 100644 +--- a/drivers/staging/media/hantro/sama5d4_vdec_hw.c ++++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c +@@ -64,11 +64,6 @@ static const struct hantro_fmt sama5d4_vdec_fmts[] = { + }, + }; + +-static int sama5d4_hw_init(struct hantro_dev *vpu) +-{ +- return 0; +-} +- + /* + * Supported codec ops. + */ +@@ -109,7 +104,6 @@ const struct hantro_variant sama5d4_vdec_variant = { + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | + HANTRO_H264_DECODER, + .codec_ops = sama5d4_vdec_codec_ops, +- .init = sama5d4_hw_init, + .irqs = sama5d4_irqs, + .num_irqs = ARRAY_SIZE(sama5d4_irqs), + .clk_names = sama5d4_clk_names, + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Mon, 19 Jul 2021 22:52:35 +0200 +Subject: [PATCH] media: hantro: Avoid redundant hantro_get_{dst,src}_buf() + calls + +Getting the next src/dst buffer is relatively expensive +so avoid doing it multiple times. + +Signed-off-by: Ezequiel Garcia +Tested-by: Alex Bee +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + .../staging/media/hantro/hantro_g1_h264_dec.c | 17 ++++++++--------- + .../staging/media/hantro/hantro_g1_vp8_dec.c | 18 +++++++++--------- + .../media/hantro/rockchip_vpu2_hw_vp8_dec.c | 19 +++++++++---------- + 3 files changed, 26 insertions(+), 28 deletions(-) + +diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c +index 5c792b7bcb79..2aa37baad0c3 100644 +--- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c ++++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c +@@ -19,13 +19,12 @@ + #include "hantro_hw.h" + #include "hantro_v4l2.h" + +-static void set_params(struct hantro_ctx *ctx) ++static void set_params(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) + { + const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; + const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode; + const struct v4l2_ctrl_h264_sps *sps = ctrls->sps; + const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; +- struct vb2_v4l2_buffer *src_buf = hantro_get_src_buf(ctx); + struct hantro_dev *vpu = ctx->dev; + u32 reg; + +@@ -226,22 +225,20 @@ static void set_ref(struct hantro_ctx *ctx) + } + } + +-static void set_buffers(struct hantro_ctx *ctx) ++static void set_buffers(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) + { + const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; +- struct vb2_v4l2_buffer *src_buf, *dst_buf; ++ struct vb2_v4l2_buffer *dst_buf; + struct hantro_dev *vpu = ctx->dev; + dma_addr_t src_dma, dst_dma; + size_t offset = 0; + +- src_buf = hantro_get_src_buf(ctx); +- dst_buf = hantro_get_dst_buf(ctx); +- + /* Source (stream) buffer. */ + src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); + vdpu_write_relaxed(vpu, src_dma, G1_REG_ADDR_STR); + + /* Destination (decoded frame) buffer. */ ++ dst_buf = hantro_get_dst_buf(ctx); + dst_dma = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf); + /* Adjust dma addr to start at second line for bottom field */ + if (ctrls->decode->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) +@@ -276,6 +273,7 @@ static void set_buffers(struct hantro_ctx *ctx) + int hantro_g1_h264_dec_run(struct hantro_ctx *ctx) + { + struct hantro_dev *vpu = ctx->dev; ++ struct vb2_v4l2_buffer *src_buf; + int ret; + + /* Prepare the H264 decoder context. */ +@@ -284,9 +282,10 @@ int hantro_g1_h264_dec_run(struct hantro_ctx *ctx) + return ret; + + /* Configure hardware registers. */ +- set_params(ctx); ++ src_buf = hantro_get_src_buf(ctx); ++ set_params(ctx, src_buf); + set_ref(ctx); +- set_buffers(ctx); ++ set_buffers(ctx, src_buf); + + hantro_end_prepare_run(ctx); + +diff --git a/drivers/staging/media/hantro/hantro_g1_vp8_dec.c b/drivers/staging/media/hantro/hantro_g1_vp8_dec.c +index 2afd5996d75f..6180b23e7d94 100644 +--- a/drivers/staging/media/hantro/hantro_g1_vp8_dec.c ++++ b/drivers/staging/media/hantro/hantro_g1_vp8_dec.c +@@ -367,13 +367,12 @@ static void cfg_tap(struct hantro_ctx *ctx, + } + + static void cfg_ref(struct hantro_ctx *ctx, +- const struct v4l2_ctrl_vp8_frame *hdr) ++ const struct v4l2_ctrl_vp8_frame *hdr, ++ struct vb2_v4l2_buffer *vb2_dst) + { + struct hantro_dev *vpu = ctx->dev; +- struct vb2_v4l2_buffer *vb2_dst; + dma_addr_t ref; + +- vb2_dst = hantro_get_dst_buf(ctx); + + ref = hantro_get_ref(ctx, hdr->last_frame_ts); + if (!ref) { +@@ -405,16 +404,14 @@ static void cfg_ref(struct hantro_ctx *ctx, + } + + static void cfg_buffers(struct hantro_ctx *ctx, +- const struct v4l2_ctrl_vp8_frame *hdr) ++ const struct v4l2_ctrl_vp8_frame *hdr, ++ struct vb2_v4l2_buffer *vb2_dst) + { + const struct v4l2_vp8_segment *seg = &hdr->segment; + struct hantro_dev *vpu = ctx->dev; +- struct vb2_v4l2_buffer *vb2_dst; + dma_addr_t dst_dma; + u32 reg; + +- vb2_dst = hantro_get_dst_buf(ctx); +- + /* Set probability table buffer address */ + vdpu_write_relaxed(vpu, ctx->vp8_dec.prob_tbl.dma, + G1_REG_ADDR_QTABLE); +@@ -436,6 +433,7 @@ int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx) + { + const struct v4l2_ctrl_vp8_frame *hdr; + struct hantro_dev *vpu = ctx->dev; ++ struct vb2_v4l2_buffer *vb2_dst; + size_t height = ctx->dst_fmt.height; + size_t width = ctx->dst_fmt.width; + u32 mb_width, mb_height; +@@ -499,8 +497,10 @@ int hantro_g1_vp8_dec_run(struct hantro_ctx *ctx) + cfg_qp(ctx, hdr); + cfg_parts(ctx, hdr); + cfg_tap(ctx, hdr); +- cfg_ref(ctx, hdr); +- cfg_buffers(ctx, hdr); ++ ++ vb2_dst = hantro_get_dst_buf(ctx); ++ cfg_ref(ctx, hdr, vb2_dst); ++ cfg_buffers(ctx, hdr, vb2_dst); + + hantro_end_prepare_run(ctx); + +diff --git a/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c b/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c +index 704607511b57..d079075448c9 100644 +--- a/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c ++++ b/drivers/staging/media/hantro/rockchip_vpu2_hw_vp8_dec.c +@@ -444,14 +444,12 @@ static void cfg_tap(struct hantro_ctx *ctx, + } + + static void cfg_ref(struct hantro_ctx *ctx, +- const struct v4l2_ctrl_vp8_frame *hdr) ++ const struct v4l2_ctrl_vp8_frame *hdr, ++ struct vb2_v4l2_buffer *vb2_dst) + { + struct hantro_dev *vpu = ctx->dev; +- struct vb2_v4l2_buffer *vb2_dst; + dma_addr_t ref; + +- vb2_dst = hantro_get_dst_buf(ctx); +- + ref = hantro_get_ref(ctx, hdr->last_frame_ts); + if (!ref) { + vpu_debug(0, "failed to find last frame ts=%llu\n", +@@ -482,16 +480,14 @@ static void cfg_ref(struct hantro_ctx *ctx, + } + + static void cfg_buffers(struct hantro_ctx *ctx, +- const struct v4l2_ctrl_vp8_frame *hdr) ++ const struct v4l2_ctrl_vp8_frame *hdr, ++ struct vb2_v4l2_buffer *vb2_dst) + { + const struct v4l2_vp8_segment *seg = &hdr->segment; + struct hantro_dev *vpu = ctx->dev; +- struct vb2_v4l2_buffer *vb2_dst; + dma_addr_t dst_dma; + u32 reg; + +- vb2_dst = hantro_get_dst_buf(ctx); +- + /* Set probability table buffer address */ + vdpu_write_relaxed(vpu, ctx->vp8_dec.prob_tbl.dma, + VDPU_REG_ADDR_QTABLE); +@@ -514,6 +510,7 @@ int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx) + { + const struct v4l2_ctrl_vp8_frame *hdr; + struct hantro_dev *vpu = ctx->dev; ++ struct vb2_v4l2_buffer *vb2_dst; + size_t height = ctx->dst_fmt.height; + size_t width = ctx->dst_fmt.width; + u32 mb_width, mb_height; +@@ -590,8 +587,10 @@ int rockchip_vpu2_vp8_dec_run(struct hantro_ctx *ctx) + cfg_qp(ctx, hdr); + cfg_parts(ctx, hdr); + cfg_tap(ctx, hdr); +- cfg_ref(ctx, hdr); +- cfg_buffers(ctx, hdr); ++ ++ vb2_dst = hantro_get_dst_buf(ctx); ++ cfg_ref(ctx, hdr, vb2_dst); ++ cfg_buffers(ctx, hdr, vb2_dst); + + hantro_end_prepare_run(ctx); + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Mon, 19 Jul 2021 22:52:36 +0200 +Subject: [PATCH] media: hantro: h264: Move DPB valid and long-term bitmaps + +In order to reuse these bitmaps, move this process to +struct hantro_h264_dec_hw_ctx. This will be used by +the Rockchip VDPU2 H.264 driver. + +This idea was originally proposed by Jonas Karlman +in "[RFC 08/12] media: hantro: Fix H264 decoding of field encoded content" +which was posted a while ago. + +Link: https://lore.kernel.org/linux-media/HE1PR06MB4011EA39133818A85768B91FACBF0@HE1PR06MB4011.eurprd06.prod.outlook.com/ + +Signed-off-by: Ezequiel Garcia +Tested-by: Alex Bee +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + .../staging/media/hantro/hantro_g1_h264_dec.c | 17 ++--------------- + drivers/staging/media/hantro/hantro_h264.c | 13 +++++++++++++ + drivers/staging/media/hantro/hantro_hw.h | 4 ++++ + 3 files changed, 19 insertions(+), 15 deletions(-) + +diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c +index 2aa37baad0c3..6faacfc44c7c 100644 +--- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c ++++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c +@@ -129,25 +129,12 @@ static void set_ref(struct hantro_ctx *ctx) + struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; + const u8 *b0_reflist, *b1_reflist, *p_reflist; + struct hantro_dev *vpu = ctx->dev; +- u32 dpb_longterm = 0; +- u32 dpb_valid = 0; + int reg_num; + u32 reg; + int i; + +- /* +- * Set up bit maps of valid and long term DPBs. +- * NOTE: The bits are reversed, i.e. MSb is DPB 0. +- */ +- for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { +- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) +- dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); +- +- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) +- dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); +- } +- vdpu_write_relaxed(vpu, dpb_valid << 16, G1_REG_VALID_REF); +- vdpu_write_relaxed(vpu, dpb_longterm << 16, G1_REG_LT_REF); ++ vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF); ++ vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF); + + /* + * Set up reference frame picture numbers. +diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c +index ed6eaf11d96f..6d72136760e7 100644 +--- a/drivers/staging/media/hantro/hantro_h264.c ++++ b/drivers/staging/media/hantro/hantro_h264.c +@@ -229,12 +229,25 @@ static void prepare_table(struct hantro_ctx *ctx) + const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode; + struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu; + const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; ++ u32 dpb_longterm = 0; ++ u32 dpb_valid = 0; + int i; + + for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { + tbl->poc[i * 2] = dpb[i].top_field_order_cnt; + tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt; ++ ++ /* ++ * Set up bit maps of valid and long term DPBs. ++ * NOTE: The bits are reversed, i.e. MSb is DPB 0. ++ */ ++ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) ++ dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); ++ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) ++ dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); + } ++ ctx->h264_dec.dpb_valid = dpb_valid << 16; ++ ctx->h264_dec.dpb_longterm = dpb_longterm << 16; + + tbl->poc[32] = dec_param->top_field_order_cnt; + tbl->poc[33] = dec_param->bottom_field_order_cnt; +diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h +index 5dcf65805396..ce678fedaad6 100644 +--- a/drivers/staging/media/hantro/hantro_hw.h ++++ b/drivers/staging/media/hantro/hantro_hw.h +@@ -89,12 +89,16 @@ struct hantro_h264_dec_reflists { + * @dpb: DPB + * @reflists: P/B0/B1 reflists + * @ctrls: V4L2 controls attached to a run ++ * @dpb_longterm: DPB long-term ++ * @dpb_valid: DPB valid + */ + struct hantro_h264_dec_hw_ctx { + struct hantro_aux_buf priv; + struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE]; + struct hantro_h264_dec_reflists reflists; + struct hantro_h264_dec_ctrls ctrls; ++ u32 dpb_longterm; ++ u32 dpb_valid; + }; + + /** + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Mon, 19 Jul 2021 22:52:37 +0200 +Subject: [PATCH] media: hantro: h264: Move reference picture number to a + helper + +Add a hantro_h264_get_ref_nbr() helper function to get the reference +picture numbers. This will be used by the Rockchip VDPU2 H.264 driver. + +This idea was originally proposed by Jonas Karlman in +"[RFC 09/12] media: hantro: Refactor G1 H264 code" +posted a while ago. + +Link: https://lore.kernel.org/linux-media/HE1PR06MB401165F2BA0AD8A634FDFAF2ACBF0@HE1PR06MB4011.eurprd06.prod.outlook.com/ + +Signed-off-by: Ezequiel Garcia +Tested-by: Alex Bee +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/staging/media/hantro/hantro_g1_h264_dec.c | 14 ++------------ + drivers/staging/media/hantro/hantro_h264.c | 11 +++++++++++ + drivers/staging/media/hantro/hantro_hw.h | 2 ++ + 3 files changed, 15 insertions(+), 12 deletions(-) + +diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c +index 6faacfc44c7c..236ce24ca00c 100644 +--- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c ++++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c +@@ -126,7 +126,6 @@ static void set_params(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) + + static void set_ref(struct hantro_ctx *ctx) + { +- struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; + const u8 *b0_reflist, *b1_reflist, *p_reflist; + struct hantro_dev *vpu = ctx->dev; + int reg_num; +@@ -143,17 +142,8 @@ static void set_ref(struct hantro_ctx *ctx) + * subsequential reference pictures. + */ + for (i = 0; i < HANTRO_H264_DPB_SIZE; i += 2) { +- reg = 0; +- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) +- reg |= G1_REG_REF_PIC_REFER0_NBR(dpb[i].pic_num); +- else +- reg |= G1_REG_REF_PIC_REFER0_NBR(dpb[i].frame_num); +- +- if (dpb[i + 1].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) +- reg |= G1_REG_REF_PIC_REFER1_NBR(dpb[i + 1].pic_num); +- else +- reg |= G1_REG_REF_PIC_REFER1_NBR(dpb[i + 1].frame_num); +- ++ reg = G1_REG_REF_PIC_REFER0_NBR(hantro_h264_get_ref_nbr(ctx, i)) | ++ G1_REG_REF_PIC_REFER1_NBR(hantro_h264_get_ref_nbr(ctx, i + 1)); + vdpu_write_relaxed(vpu, reg, G1_REG_REF_PIC(i / 2)); + } + +diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c +index 6d72136760e7..0b4d2491be3b 100644 +--- a/drivers/staging/media/hantro/hantro_h264.c ++++ b/drivers/staging/media/hantro/hantro_h264.c +@@ -348,6 +348,17 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, + return dma_addr; + } + ++u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, unsigned int dpb_idx) ++{ ++ const struct v4l2_h264_dpb_entry *dpb = &ctx->h264_dec.dpb[dpb_idx]; ++ ++ if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) ++ return 0; ++ if (dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) ++ return dpb->pic_num; ++ return dpb->frame_num; ++} ++ + int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx) + { + struct hantro_h264_dec_hw_ctx *h264_ctx = &ctx->h264_dec; +diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h +index ce678fedaad6..7a8048afe357 100644 +--- a/drivers/staging/media/hantro/hantro_hw.h ++++ b/drivers/staging/media/hantro/hantro_hw.h +@@ -238,6 +238,8 @@ void hantro_jpeg_enc_done(struct hantro_ctx *ctx); + + dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, + unsigned int dpb_idx); ++u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, ++ unsigned int dpb_idx); + int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx); + int hantro_g1_h264_dec_run(struct hantro_ctx *ctx); + int hantro_h264_dec_init(struct hantro_ctx *ctx); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Mon, 19 Jul 2021 22:52:38 +0200 +Subject: [PATCH] media: hantro: Add H.264 support for Rockchip VDPU2 + +Rockchip VDPU2 core is present on RK3328, RK3326/PX30, RK3399 +and others. It's similar to Hantro G1, but it's not compatible with it. + +Signed-off-by: Jonas Karlman +Signed-off-by: Ezequiel Garcia +Tested-by: Alex Bee +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/staging/media/hantro/Makefile | 1 + + drivers/staging/media/hantro/hantro_hw.h | 1 + + .../media/hantro/rockchip_vpu2_hw_h264_dec.c | 491 ++++++++++++++++++ + 3 files changed, 493 insertions(+) + create mode 100644 drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c + +diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile +index 287370188d2a..90036831fec4 100644 +--- a/drivers/staging/media/hantro/Makefile ++++ b/drivers/staging/media/hantro/Makefile +@@ -13,6 +13,7 @@ hantro-vpu-y += \ + hantro_g2_hevc_dec.o \ + hantro_g1_vp8_dec.o \ + rockchip_vpu2_hw_jpeg_enc.o \ ++ rockchip_vpu2_hw_h264_dec.o \ + rockchip_vpu2_hw_mpeg2_dec.o \ + rockchip_vpu2_hw_vp8_dec.o \ + hantro_jpeg.o \ +diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h +index 7a8048afe357..9296624654a6 100644 +--- a/drivers/staging/media/hantro/hantro_hw.h ++++ b/drivers/staging/media/hantro/hantro_hw.h +@@ -241,6 +241,7 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, + u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, + unsigned int dpb_idx); + int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx); ++int rockchip_vpu2_h264_dec_run(struct hantro_ctx *ctx); + int hantro_g1_h264_dec_run(struct hantro_ctx *ctx); + int hantro_h264_dec_init(struct hantro_ctx *ctx); + void hantro_h264_dec_exit(struct hantro_ctx *ctx); +diff --git a/drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c b/drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c +new file mode 100644 +index 000000000000..64a6330475eb +--- /dev/null ++++ b/drivers/staging/media/hantro/rockchip_vpu2_hw_h264_dec.c +@@ -0,0 +1,491 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Hantro VPU codec driver ++ * ++ * Copyright (c) 2014 Rockchip Electronics Co., Ltd. ++ * Hertz Wong ++ * Herman Chen ++ * ++ * Copyright (C) 2014 Google, Inc. ++ * Tomasz Figa ++ */ ++ ++#include ++#include ++ ++#include ++ ++#include "hantro_hw.h" ++#include "hantro_v4l2.h" ++ ++#define VDPU_SWREG(nr) ((nr) * 4) ++ ++#define VDPU_REG_DEC_OUT_BASE VDPU_SWREG(63) ++#define VDPU_REG_RLC_VLC_BASE VDPU_SWREG(64) ++#define VDPU_REG_QTABLE_BASE VDPU_SWREG(61) ++#define VDPU_REG_DIR_MV_BASE VDPU_SWREG(62) ++#define VDPU_REG_REFER_BASE(i) (VDPU_SWREG(84 + (i))) ++#define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) ++ ++#define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) ++#define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) ++#define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) ++#define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) ++#define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) ++ ++#define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) ++#define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) ++ ++#define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) ++#define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) ++#define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0)) ++ ++#define VDPU_REG_DEC_MODE(v) (((v) << 0) & GENMASK(3, 0)) ++ ++#define VDPU_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(5) : 0) ++#define VDPU_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(4) : 0) ++#define VDPU_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(3) : 0) ++#define VDPU_REG_DEC_INSWAP32_E(v) ((v) ? BIT(2) : 0) ++#define VDPU_REG_DEC_OUT_ENDIAN(v) ((v) ? BIT(1) : 0) ++#define VDPU_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(0) : 0) ++ ++#define VDPU_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(22) : 0) ++#define VDPU_REG_DEC_MAX_BURST(v) (((v) << 16) & GENMASK(20, 16)) ++#define VDPU_REG_DEC_AXI_WR_ID(v) (((v) << 8) & GENMASK(15, 8)) ++#define VDPU_REG_DEC_AXI_RD_ID(v) (((v) << 0) & GENMASK(7, 0)) ++ ++#define VDPU_REG_START_CODE_E(v) ((v) ? BIT(22) : 0) ++#define VDPU_REG_CH_8PIX_ILEAV_E(v) ((v) ? BIT(21) : 0) ++#define VDPU_REG_RLC_MODE_E(v) ((v) ? BIT(20) : 0) ++#define VDPU_REG_PIC_INTERLACE_E(v) ((v) ? BIT(17) : 0) ++#define VDPU_REG_PIC_FIELDMODE_E(v) ((v) ? BIT(16) : 0) ++#define VDPU_REG_PIC_TOPFIELD_E(v) ((v) ? BIT(13) : 0) ++#define VDPU_REG_WRITE_MVS_E(v) ((v) ? BIT(10) : 0) ++#define VDPU_REG_SEQ_MBAFF_E(v) ((v) ? BIT(7) : 0) ++#define VDPU_REG_PICORD_COUNT_E(v) ((v) ? BIT(6) : 0) ++#define VDPU_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(5) : 0) ++#define VDPU_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(4) : 0) ++ ++#define VDPU_REG_PRED_BC_TAP_0_0(v) (((v) << 22) & GENMASK(31, 22)) ++#define VDPU_REG_PRED_BC_TAP_0_1(v) (((v) << 12) & GENMASK(21, 12)) ++#define VDPU_REG_PRED_BC_TAP_0_2(v) (((v) << 2) & GENMASK(11, 2)) ++ ++#define VDPU_REG_REFBU_E(v) ((v) ? BIT(31) : 0) ++ ++#define VDPU_REG_PINIT_RLIST_F9(v) (((v) << 25) & GENMASK(29, 25)) ++#define VDPU_REG_PINIT_RLIST_F8(v) (((v) << 20) & GENMASK(24, 20)) ++#define VDPU_REG_PINIT_RLIST_F7(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_PINIT_RLIST_F6(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_PINIT_RLIST_F5(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_PINIT_RLIST_F4(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_PINIT_RLIST_F15(v) (((v) << 25) & GENMASK(29, 25)) ++#define VDPU_REG_PINIT_RLIST_F14(v) (((v) << 20) & GENMASK(24, 20)) ++#define VDPU_REG_PINIT_RLIST_F13(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_PINIT_RLIST_F12(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_PINIT_RLIST_F11(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_PINIT_RLIST_F10(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_REFER1_NBR(v) (((v) << 16) & GENMASK(31, 16)) ++#define VDPU_REG_REFER0_NBR(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_REFER3_NBR(v) (((v) << 16) & GENMASK(31, 16)) ++#define VDPU_REG_REFER2_NBR(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_REFER5_NBR(v) (((v) << 16) & GENMASK(31, 16)) ++#define VDPU_REG_REFER4_NBR(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_REFER7_NBR(v) (((v) << 16) & GENMASK(31, 16)) ++#define VDPU_REG_REFER6_NBR(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_REFER9_NBR(v) (((v) << 16) & GENMASK(31, 16)) ++#define VDPU_REG_REFER8_NBR(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_REFER11_NBR(v) (((v) << 16) & GENMASK(31, 16)) ++#define VDPU_REG_REFER10_NBR(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_REFER13_NBR(v) (((v) << 16) & GENMASK(31, 16)) ++#define VDPU_REG_REFER12_NBR(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_REFER15_NBR(v) (((v) << 16) & GENMASK(31, 16)) ++#define VDPU_REG_REFER14_NBR(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_BINIT_RLIST_F5(v) (((v) << 25) & GENMASK(29, 25)) ++#define VDPU_REG_BINIT_RLIST_F4(v) (((v) << 20) & GENMASK(24, 20)) ++#define VDPU_REG_BINIT_RLIST_F3(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_BINIT_RLIST_F2(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_BINIT_RLIST_F1(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_BINIT_RLIST_F0(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_BINIT_RLIST_F11(v) (((v) << 25) & GENMASK(29, 25)) ++#define VDPU_REG_BINIT_RLIST_F10(v) (((v) << 20) & GENMASK(24, 20)) ++#define VDPU_REG_BINIT_RLIST_F9(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_BINIT_RLIST_F8(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_BINIT_RLIST_F7(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_BINIT_RLIST_F6(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_BINIT_RLIST_F15(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_BINIT_RLIST_F14(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_BINIT_RLIST_F13(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_BINIT_RLIST_F12(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_BINIT_RLIST_B5(v) (((v) << 25) & GENMASK(29, 25)) ++#define VDPU_REG_BINIT_RLIST_B4(v) (((v) << 20) & GENMASK(24, 20)) ++#define VDPU_REG_BINIT_RLIST_B3(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_BINIT_RLIST_B2(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_BINIT_RLIST_B1(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_BINIT_RLIST_B0(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_BINIT_RLIST_B11(v) (((v) << 25) & GENMASK(29, 25)) ++#define VDPU_REG_BINIT_RLIST_B10(v) (((v) << 20) & GENMASK(24, 20)) ++#define VDPU_REG_BINIT_RLIST_B9(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_BINIT_RLIST_B8(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_BINIT_RLIST_B7(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_BINIT_RLIST_B6(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_BINIT_RLIST_B15(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_BINIT_RLIST_B14(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_BINIT_RLIST_B13(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_BINIT_RLIST_B12(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_PINIT_RLIST_F3(v) (((v) << 15) & GENMASK(19, 15)) ++#define VDPU_REG_PINIT_RLIST_F2(v) (((v) << 10) & GENMASK(14, 10)) ++#define VDPU_REG_PINIT_RLIST_F1(v) (((v) << 5) & GENMASK(9, 5)) ++#define VDPU_REG_PINIT_RLIST_F0(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_REFER_LTERM_E(v) (((v) << 0) & GENMASK(31, 0)) ++ ++#define VDPU_REG_REFER_VALID_E(v) (((v) << 0) & GENMASK(31, 0)) ++ ++#define VDPU_REG_STRM_START_BIT(v) (((v) << 0) & GENMASK(5, 0)) ++ ++#define VDPU_REG_CH_QP_OFFSET2(v) (((v) << 22) & GENMASK(26, 22)) ++#define VDPU_REG_CH_QP_OFFSET(v) (((v) << 17) & GENMASK(21, 17)) ++#define VDPU_REG_PIC_MB_HEIGHT_P(v) (((v) << 9) & GENMASK(16, 9)) ++#define VDPU_REG_PIC_MB_WIDTH(v) (((v) << 0) & GENMASK(8, 0)) ++ ++#define VDPU_REG_WEIGHT_BIPR_IDC(v) (((v) << 16) & GENMASK(17, 16)) ++#define VDPU_REG_REF_FRAMES(v) (((v) << 0) & GENMASK(4, 0)) ++ ++#define VDPU_REG_FILT_CTRL_PRES(v) ((v) ? BIT(31) : 0) ++#define VDPU_REG_RDPIC_CNT_PRES(v) ((v) ? BIT(30) : 0) ++#define VDPU_REG_FRAMENUM_LEN(v) (((v) << 16) & GENMASK(20, 16)) ++#define VDPU_REG_FRAMENUM(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_REFPIC_MK_LEN(v) (((v) << 16) & GENMASK(26, 16)) ++#define VDPU_REG_IDR_PIC_ID(v) (((v) << 0) & GENMASK(15, 0)) ++ ++#define VDPU_REG_PPS_ID(v) (((v) << 24) & GENMASK(31, 24)) ++#define VDPU_REG_REFIDX1_ACTIVE(v) (((v) << 19) & GENMASK(23, 19)) ++#define VDPU_REG_REFIDX0_ACTIVE(v) (((v) << 14) & GENMASK(18, 14)) ++#define VDPU_REG_POC_LENGTH(v) (((v) << 0) & GENMASK(7, 0)) ++ ++#define VDPU_REG_IDR_PIC_E(v) ((v) ? BIT(8) : 0) ++#define VDPU_REG_DIR_8X8_INFER_E(v) ((v) ? BIT(7) : 0) ++#define VDPU_REG_BLACKWHITE_E(v) ((v) ? BIT(6) : 0) ++#define VDPU_REG_CABAC_E(v) ((v) ? BIT(5) : 0) ++#define VDPU_REG_WEIGHT_PRED_E(v) ((v) ? BIT(4) : 0) ++#define VDPU_REG_CONST_INTRA_E(v) ((v) ? BIT(3) : 0) ++#define VDPU_REG_8X8TRANS_FLAG_E(v) ((v) ? BIT(2) : 0) ++#define VDPU_REG_TYPE1_QUANT_E(v) ((v) ? BIT(1) : 0) ++#define VDPU_REG_FIELDPIC_FLAG_E(v) ((v) ? BIT(0) : 0) ++ ++static void set_params(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) ++{ ++ const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; ++ const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode; ++ const struct v4l2_ctrl_h264_sps *sps = ctrls->sps; ++ const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; ++ struct hantro_dev *vpu = ctx->dev; ++ u32 reg; ++ ++ reg = VDPU_REG_DEC_ADV_PRE_DIS(0) | ++ VDPU_REG_DEC_SCMD_DIS(0) | ++ VDPU_REG_FILTERING_DIS(0) | ++ VDPU_REG_PIC_FIXED_QUANT(0) | ++ VDPU_REG_DEC_LATENCY(0); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(50)); ++ ++ reg = VDPU_REG_INIT_QP(pps->pic_init_qp_minus26 + 26) | ++ VDPU_REG_STREAM_LEN(vb2_get_plane_payload(&src_buf->vb2_buf, 0)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(51)); ++ ++ reg = VDPU_REG_APF_THRESHOLD(8) | ++ VDPU_REG_STARTMB_X(0) | ++ VDPU_REG_STARTMB_Y(0); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(52)); ++ ++ reg = VDPU_REG_DEC_MODE(0); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(53)); ++ ++ reg = VDPU_REG_DEC_STRENDIAN_E(1) | ++ VDPU_REG_DEC_STRSWAP32_E(1) | ++ VDPU_REG_DEC_OUTSWAP32_E(1) | ++ VDPU_REG_DEC_INSWAP32_E(1) | ++ VDPU_REG_DEC_OUT_ENDIAN(1) | ++ VDPU_REG_DEC_IN_ENDIAN(0); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(54)); ++ ++ reg = VDPU_REG_DEC_DATA_DISC_E(0) | ++ VDPU_REG_DEC_MAX_BURST(16) | ++ VDPU_REG_DEC_AXI_WR_ID(0) | ++ VDPU_REG_DEC_AXI_RD_ID(0xff); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(56)); ++ ++ reg = VDPU_REG_START_CODE_E(1) | ++ VDPU_REG_CH_8PIX_ILEAV_E(0) | ++ VDPU_REG_RLC_MODE_E(0) | ++ VDPU_REG_PIC_INTERLACE_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) && ++ (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD || ++ dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)) | ++ VDPU_REG_PIC_FIELDMODE_E(dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) | ++ VDPU_REG_PIC_TOPFIELD_E(!(dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD)) | ++ VDPU_REG_WRITE_MVS_E((sps->profile_idc > 66) && dec_param->nal_ref_idc) | ++ VDPU_REG_SEQ_MBAFF_E(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) | ++ VDPU_REG_PICORD_COUNT_E(sps->profile_idc > 66) | ++ VDPU_REG_DEC_TIMEOUT_E(1) | ++ VDPU_REG_DEC_CLK_GATE_E(1); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(57)); ++ ++ reg = VDPU_REG_PRED_BC_TAP_0_0(1) | ++ VDPU_REG_PRED_BC_TAP_0_1((u32)-5) | ++ VDPU_REG_PRED_BC_TAP_0_2(20); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(59)); ++ ++ reg = VDPU_REG_REFBU_E(0); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(65)); ++ ++ reg = VDPU_REG_STRM_START_BIT(0); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(109)); ++ ++ reg = VDPU_REG_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset) | ++ VDPU_REG_CH_QP_OFFSET(pps->chroma_qp_index_offset) | ++ VDPU_REG_PIC_MB_HEIGHT_P(MB_HEIGHT(ctx->src_fmt.height)) | ++ VDPU_REG_PIC_MB_WIDTH(MB_WIDTH(ctx->src_fmt.width)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(110)); ++ ++ reg = VDPU_REG_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc) | ++ VDPU_REG_REF_FRAMES(sps->max_num_ref_frames); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(111)); ++ ++ reg = VDPU_REG_FILT_CTRL_PRES(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT) | ++ VDPU_REG_RDPIC_CNT_PRES(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT) | ++ VDPU_REG_FRAMENUM_LEN(sps->log2_max_frame_num_minus4 + 4) | ++ VDPU_REG_FRAMENUM(dec_param->frame_num); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(112)); ++ ++ reg = VDPU_REG_REFPIC_MK_LEN(dec_param->dec_ref_pic_marking_bit_size) | ++ VDPU_REG_IDR_PIC_ID(dec_param->idr_pic_id); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(113)); ++ ++ reg = VDPU_REG_PPS_ID(pps->pic_parameter_set_id) | ++ VDPU_REG_REFIDX1_ACTIVE(pps->num_ref_idx_l1_default_active_minus1 + 1) | ++ VDPU_REG_REFIDX0_ACTIVE(pps->num_ref_idx_l0_default_active_minus1 + 1) | ++ VDPU_REG_POC_LENGTH(dec_param->pic_order_cnt_bit_size); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(114)); ++ ++ reg = VDPU_REG_IDR_PIC_E(dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC) | ++ VDPU_REG_DIR_8X8_INFER_E(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) | ++ VDPU_REG_BLACKWHITE_E(sps->profile_idc >= 100 && sps->chroma_format_idc == 0) | ++ VDPU_REG_CABAC_E(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) | ++ VDPU_REG_WEIGHT_PRED_E(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) | ++ VDPU_REG_CONST_INTRA_E(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) | ++ VDPU_REG_8X8TRANS_FLAG_E(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) | ++ VDPU_REG_TYPE1_QUANT_E(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT) | ++ VDPU_REG_FIELDPIC_FLAG_E(!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(115)); ++} ++ ++static void set_ref(struct hantro_ctx *ctx) ++{ ++ const u8 *b0_reflist, *b1_reflist, *p_reflist; ++ struct hantro_dev *vpu = ctx->dev; ++ u32 reg; ++ int i; ++ ++ b0_reflist = ctx->h264_dec.reflists.b0; ++ b1_reflist = ctx->h264_dec.reflists.b1; ++ p_reflist = ctx->h264_dec.reflists.p; ++ ++ reg = VDPU_REG_PINIT_RLIST_F9(p_reflist[9]) | ++ VDPU_REG_PINIT_RLIST_F8(p_reflist[8]) | ++ VDPU_REG_PINIT_RLIST_F7(p_reflist[7]) | ++ VDPU_REG_PINIT_RLIST_F6(p_reflist[6]) | ++ VDPU_REG_PINIT_RLIST_F5(p_reflist[5]) | ++ VDPU_REG_PINIT_RLIST_F4(p_reflist[4]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(74)); ++ ++ reg = VDPU_REG_PINIT_RLIST_F15(p_reflist[15]) | ++ VDPU_REG_PINIT_RLIST_F14(p_reflist[14]) | ++ VDPU_REG_PINIT_RLIST_F13(p_reflist[13]) | ++ VDPU_REG_PINIT_RLIST_F12(p_reflist[12]) | ++ VDPU_REG_PINIT_RLIST_F11(p_reflist[11]) | ++ VDPU_REG_PINIT_RLIST_F10(p_reflist[10]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(75)); ++ ++ reg = VDPU_REG_REFER1_NBR(hantro_h264_get_ref_nbr(ctx, 1)) | ++ VDPU_REG_REFER0_NBR(hantro_h264_get_ref_nbr(ctx, 0)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(76)); ++ ++ reg = VDPU_REG_REFER3_NBR(hantro_h264_get_ref_nbr(ctx, 3)) | ++ VDPU_REG_REFER2_NBR(hantro_h264_get_ref_nbr(ctx, 2)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(77)); ++ ++ reg = VDPU_REG_REFER5_NBR(hantro_h264_get_ref_nbr(ctx, 5)) | ++ VDPU_REG_REFER4_NBR(hantro_h264_get_ref_nbr(ctx, 4)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(78)); ++ ++ reg = VDPU_REG_REFER7_NBR(hantro_h264_get_ref_nbr(ctx, 7)) | ++ VDPU_REG_REFER6_NBR(hantro_h264_get_ref_nbr(ctx, 6)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(79)); ++ ++ reg = VDPU_REG_REFER9_NBR(hantro_h264_get_ref_nbr(ctx, 9)) | ++ VDPU_REG_REFER8_NBR(hantro_h264_get_ref_nbr(ctx, 8)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(80)); ++ ++ reg = VDPU_REG_REFER11_NBR(hantro_h264_get_ref_nbr(ctx, 11)) | ++ VDPU_REG_REFER10_NBR(hantro_h264_get_ref_nbr(ctx, 10)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(81)); ++ ++ reg = VDPU_REG_REFER13_NBR(hantro_h264_get_ref_nbr(ctx, 13)) | ++ VDPU_REG_REFER12_NBR(hantro_h264_get_ref_nbr(ctx, 12)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(82)); ++ ++ reg = VDPU_REG_REFER15_NBR(hantro_h264_get_ref_nbr(ctx, 15)) | ++ VDPU_REG_REFER14_NBR(hantro_h264_get_ref_nbr(ctx, 14)); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(83)); ++ ++ reg = VDPU_REG_BINIT_RLIST_F5(b0_reflist[5]) | ++ VDPU_REG_BINIT_RLIST_F4(b0_reflist[4]) | ++ VDPU_REG_BINIT_RLIST_F3(b0_reflist[3]) | ++ VDPU_REG_BINIT_RLIST_F2(b0_reflist[2]) | ++ VDPU_REG_BINIT_RLIST_F1(b0_reflist[1]) | ++ VDPU_REG_BINIT_RLIST_F0(b0_reflist[0]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(100)); ++ ++ reg = VDPU_REG_BINIT_RLIST_F11(b0_reflist[11]) | ++ VDPU_REG_BINIT_RLIST_F10(b0_reflist[10]) | ++ VDPU_REG_BINIT_RLIST_F9(b0_reflist[9]) | ++ VDPU_REG_BINIT_RLIST_F8(b0_reflist[8]) | ++ VDPU_REG_BINIT_RLIST_F7(b0_reflist[7]) | ++ VDPU_REG_BINIT_RLIST_F6(b0_reflist[6]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(101)); ++ ++ reg = VDPU_REG_BINIT_RLIST_F15(b0_reflist[15]) | ++ VDPU_REG_BINIT_RLIST_F14(b0_reflist[14]) | ++ VDPU_REG_BINIT_RLIST_F13(b0_reflist[13]) | ++ VDPU_REG_BINIT_RLIST_F12(b0_reflist[12]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(102)); ++ ++ reg = VDPU_REG_BINIT_RLIST_B5(b1_reflist[5]) | ++ VDPU_REG_BINIT_RLIST_B4(b1_reflist[4]) | ++ VDPU_REG_BINIT_RLIST_B3(b1_reflist[3]) | ++ VDPU_REG_BINIT_RLIST_B2(b1_reflist[2]) | ++ VDPU_REG_BINIT_RLIST_B1(b1_reflist[1]) | ++ VDPU_REG_BINIT_RLIST_B0(b1_reflist[0]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(103)); ++ ++ reg = VDPU_REG_BINIT_RLIST_B11(b1_reflist[11]) | ++ VDPU_REG_BINIT_RLIST_B10(b1_reflist[10]) | ++ VDPU_REG_BINIT_RLIST_B9(b1_reflist[9]) | ++ VDPU_REG_BINIT_RLIST_B8(b1_reflist[8]) | ++ VDPU_REG_BINIT_RLIST_B7(b1_reflist[7]) | ++ VDPU_REG_BINIT_RLIST_B6(b1_reflist[6]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(104)); ++ ++ reg = VDPU_REG_BINIT_RLIST_B15(b1_reflist[15]) | ++ VDPU_REG_BINIT_RLIST_B14(b1_reflist[14]) | ++ VDPU_REG_BINIT_RLIST_B13(b1_reflist[13]) | ++ VDPU_REG_BINIT_RLIST_B12(b1_reflist[12]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(105)); ++ ++ reg = VDPU_REG_PINIT_RLIST_F3(p_reflist[3]) | ++ VDPU_REG_PINIT_RLIST_F2(p_reflist[2]) | ++ VDPU_REG_PINIT_RLIST_F1(p_reflist[1]) | ++ VDPU_REG_PINIT_RLIST_F0(p_reflist[0]); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(106)); ++ ++ reg = VDPU_REG_REFER_LTERM_E(ctx->h264_dec.dpb_longterm); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(107)); ++ ++ reg = VDPU_REG_REFER_VALID_E(ctx->h264_dec.dpb_valid); ++ vdpu_write_relaxed(vpu, reg, VDPU_SWREG(108)); ++ ++ /* Set up addresses of DPB buffers. */ ++ for (i = 0; i < HANTRO_H264_DPB_SIZE; i++) { ++ dma_addr_t dma_addr = hantro_h264_get_ref_buf(ctx, i); ++ ++ vdpu_write_relaxed(vpu, dma_addr, VDPU_REG_REFER_BASE(i)); ++ } ++} ++ ++static void set_buffers(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *src_buf) ++{ ++ const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; ++ struct vb2_v4l2_buffer *dst_buf; ++ struct hantro_dev *vpu = ctx->dev; ++ dma_addr_t src_dma, dst_dma; ++ size_t offset = 0; ++ ++ /* Source (stream) buffer. */ ++ src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); ++ vdpu_write_relaxed(vpu, src_dma, VDPU_REG_RLC_VLC_BASE); ++ ++ /* Destination (decoded frame) buffer. */ ++ dst_buf = hantro_get_dst_buf(ctx); ++ dst_dma = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf); ++ /* Adjust dma addr to start at second line for bottom field */ ++ if (ctrls->decode->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) ++ offset = ALIGN(ctx->src_fmt.width, MB_DIM); ++ vdpu_write_relaxed(vpu, dst_dma + offset, VDPU_REG_DEC_OUT_BASE); ++ ++ /* Higher profiles require DMV buffer appended to reference frames. */ ++ if (ctrls->sps->profile_idc > 66 && ctrls->decode->nal_ref_idc) { ++ unsigned int bytes_per_mb = 384; ++ ++ /* DMV buffer for monochrome start directly after Y-plane */ ++ if (ctrls->sps->profile_idc >= 100 && ++ ctrls->sps->chroma_format_idc == 0) ++ bytes_per_mb = 256; ++ offset = bytes_per_mb * MB_WIDTH(ctx->src_fmt.width) * ++ MB_HEIGHT(ctx->src_fmt.height); ++ ++ /* ++ * DMV buffer is split in two for field encoded frames, ++ * adjust offset for bottom field ++ */ ++ if (ctrls->decode->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) ++ offset += 32 * MB_WIDTH(ctx->src_fmt.width) * ++ MB_HEIGHT(ctx->src_fmt.height); ++ vdpu_write_relaxed(vpu, dst_dma + offset, VDPU_REG_DIR_MV_BASE); ++ } ++ ++ /* Auxiliary buffer prepared in hantro_g1_h264_dec_prepare_table(). */ ++ vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, VDPU_REG_QTABLE_BASE); ++} ++ ++int rockchip_vpu2_h264_dec_run(struct hantro_ctx *ctx) ++{ ++ struct hantro_dev *vpu = ctx->dev; ++ struct vb2_v4l2_buffer *src_buf; ++ u32 reg; ++ int ret; ++ ++ /* Prepare the H264 decoder context. */ ++ ret = hantro_h264_dec_prepare_run(ctx); ++ if (ret) ++ return ret; ++ ++ src_buf = hantro_get_src_buf(ctx); ++ set_params(ctx, src_buf); ++ set_ref(ctx); ++ set_buffers(ctx, src_buf); ++ ++ hantro_end_prepare_run(ctx); ++ ++ /* Start decoding! */ ++ reg = vdpu_read(vpu, VDPU_SWREG(57)) | VDPU_REG_DEC_E(1); ++ vdpu_write(vpu, reg, VDPU_SWREG(57)); ++ ++ return 0; ++} + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Mon, 19 Jul 2021 22:52:39 +0200 +Subject: [PATCH] media: hantro: Enable H.264 on Rockchip VDPU2 + +Given H.264 support for VDPU2 was just added, let's enable it. +For now, this is only enabled on platform that don't have +an RKVDEC core, such as RK3328. + +Signed-off-by: Ezequiel Garcia +Tested-by: Alex Bee +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + .../staging/media/hantro/rockchip_vpu_hw.c | 26 ++++++++++++++++++- + 1 file changed, 25 insertions(+), 1 deletion(-) + +diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c +index 3ccc16413f42..e4e3b5e7689b 100644 +--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c ++++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c +@@ -162,6 +162,19 @@ static const struct hantro_fmt rk3399_vpu_dec_fmts[] = { + .fourcc = V4L2_PIX_FMT_NV12, + .codec_mode = HANTRO_MODE_NONE, + }, ++ { ++ .fourcc = V4L2_PIX_FMT_H264_SLICE, ++ .codec_mode = HANTRO_MODE_H264_DEC, ++ .max_depth = 2, ++ .frmsize = { ++ .min_width = 48, ++ .max_width = 1920, ++ .step_width = MB_DIM, ++ .min_height = 48, ++ .max_height = 1088, ++ .step_height = MB_DIM, ++ }, ++ }, + { + .fourcc = V4L2_PIX_FMT_MPEG2_SLICE, + .codec_mode = HANTRO_MODE_MPEG2_DEC, +@@ -388,6 +401,12 @@ static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = { + .init = hantro_jpeg_enc_init, + .exit = hantro_jpeg_enc_exit, + }, ++ [HANTRO_MODE_H264_DEC] = { ++ .run = rockchip_vpu2_h264_dec_run, ++ .reset = rockchip_vpu2_dec_reset, ++ .init = hantro_h264_dec_init, ++ .exit = hantro_h264_dec_exit, ++ }, + [HANTRO_MODE_MPEG2_DEC] = { + .run = rockchip_vpu2_mpeg2_dec_run, + .reset = rockchip_vpu2_dec_reset, +@@ -433,6 +452,8 @@ static const char * const rockchip_vpu_clk_names[] = { + "aclk", "hclk" + }; + ++/* VDPU1/VEPU1 */ ++ + const struct hantro_variant rk3036_vpu_variant = { + .dec_offset = 0x400, + .dec_fmts = rk3066_vpu_dec_fmts, +@@ -495,11 +516,14 @@ const struct hantro_variant rk3288_vpu_variant = { + .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) + }; + ++/* VDPU2/VEPU2 */ ++ + const struct hantro_variant rk3328_vpu_variant = { + .dec_offset = 0x400, + .dec_fmts = rk3399_vpu_dec_fmts, + .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), +- .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER, ++ .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | ++ HANTRO_H264_DECODER, + .codec_ops = rk3399_vpu_codec_ops, + .irqs = rockchip_vdpu2_irqs, + .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs), + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski +Date: Mon, 19 Jul 2021 22:52:41 +0200 +Subject: [PATCH] media: dt-bindings: media: rockchip-vpu: Add PX30 compatible + +The Rockchip PX30 SoC has a Hantro VPU that features a decoder (VDPU2) +and an encoder (VEPU2). + +Suggested-by: Alex Bee +Signed-off-by: Paul Kocialkowski +Signed-off-by: Ezequiel Garcia +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + Documentation/devicetree/bindings/media/rockchip-vpu.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml +index b88172a59de7..bacb60a34989 100644 +--- a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml ++++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml +@@ -22,6 +22,7 @@ properties: + - rockchip,rk3288-vpu + - rockchip,rk3328-vpu + - rockchip,rk3399-vpu ++ - rockchip,px30-vpu + - items: + - const: rockchip,rk3188-vpu + - const: rockchip,rk3066-vpu + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski +Date: Mon, 19 Jul 2021 22:52:40 +0200 +Subject: [PATCH] media: hantro: Add support for the Rockchip PX30 + +The PX30 SoC includes both the VDPU2 and VEPU2 blocks which are similar +to the RK3399 (Hantro G1/H1 with shuffled registers). + +Signed-off-by: Paul Kocialkowski +Signed-off-by: Ezequiel Garcia +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +--- + drivers/staging/media/hantro/hantro_drv.c | 1 + + drivers/staging/media/hantro/hantro_hw.h | 1 + + drivers/staging/media/hantro/rockchip_vpu_hw.c | 17 +++++++++++++++++ + 3 files changed, 19 insertions(+) + +diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c +index 9b5415176bfe..8a2edd67f2c6 100644 +--- a/drivers/staging/media/hantro/hantro_drv.c ++++ b/drivers/staging/media/hantro/hantro_drv.c +@@ -582,6 +582,7 @@ static const struct v4l2_file_operations hantro_fops = { + + static const struct of_device_id of_hantro_match[] = { + #ifdef CONFIG_VIDEO_HANTRO_ROCKCHIP ++ { .compatible = "rockchip,px30-vpu", .data = &px30_vpu_variant, }, + { .compatible = "rockchip,rk3036-vpu", .data = &rk3036_vpu_variant, }, + { .compatible = "rockchip,rk3066-vpu", .data = &rk3066_vpu_variant, }, + { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, }, +diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h +index 9296624654a6..df7b5e3a57b9 100644 +--- a/drivers/staging/media/hantro/hantro_hw.h ++++ b/drivers/staging/media/hantro/hantro_hw.h +@@ -209,6 +209,7 @@ enum hantro_enc_fmt { + + extern const struct hantro_variant imx8mq_vpu_g2_variant; + extern const struct hantro_variant imx8mq_vpu_variant; ++extern const struct hantro_variant px30_vpu_variant; + extern const struct hantro_variant rk3036_vpu_variant; + extern const struct hantro_variant rk3066_vpu_variant; + extern const struct hantro_variant rk3288_vpu_variant; +diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c +index e4e3b5e7689b..d4f52957cc53 100644 +--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c ++++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c +@@ -548,3 +548,20 @@ const struct hantro_variant rk3399_vpu_variant = { + .clk_names = rockchip_vpu_clk_names, + .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) + }; ++ ++const struct hantro_variant px30_vpu_variant = { ++ .enc_offset = 0x0, ++ .enc_fmts = rockchip_vpu_enc_fmts, ++ .num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts), ++ .dec_offset = 0x400, ++ .dec_fmts = rk3399_vpu_dec_fmts, ++ .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), ++ .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | ++ HANTRO_VP8_DECODER | HANTRO_H264_DECODER, ++ .codec_ops = rk3399_vpu_codec_ops, ++ .irqs = rockchip_vpu2_irqs, ++ .num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs), ++ .init = rk3036_vpu_hw_init, ++ .clk_names = rockchip_vpu_clk_names, ++ .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) ++}; diff --git a/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch similarity index 73% rename from projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch rename to projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch index a835cda740..07dc5ef7bf 100644 --- a/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0011-v4l2-from-list.patch @@ -20,7 +20,7 @@ Reviewed-by: Ezequiel Garcia 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 7cc3b478a5f4..054d2e3eed67 100644 +index 76e97cbe2512..af44a16c0c4a 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -752,7 +752,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, @@ -47,10 +47,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 1263991de76f..71a6b7b0b057 100644 +index 7131156c1f2c..65a8334a188b 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -223,6 +223,8 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, +@@ -233,6 +233,8 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, pix_mp->pixelformat = coded_desc->decoded_fmts[0]; /* Always apply the frmsize constraint of the coded end. */ @@ -83,7 +83,7 @@ Signed-off-by: Jonas Karlman 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 054d2e3eed67..d46424ba88e8 100644 +index af44a16c0c4a..9852c3519f56 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -671,8 +671,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, @@ -98,7 +98,7 @@ index 054d2e3eed67..d46424ba88e8 100644 FRAME_MBS_ONLY_FLAG); WRITE_PPS(!!(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD), diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 71a6b7b0b057..f405dd72ad93 100644 +index 65a8334a188b..f4c5ee4a1e26 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -29,8 +29,11 @@ @@ -146,7 +146,7 @@ Reviewed-by: Ezequiel Garcia 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index d46424ba88e8..6536cf0d6054 100644 +index 9852c3519f56..f3ff3e709169 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -661,8 +661,8 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, @@ -179,7 +179,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 6536cf0d6054..bf632d45282b 100644 +index f3ff3e709169..503ae683d0fd 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -1015,8 +1015,9 @@ static int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx, @@ -214,7 +214,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 38 insertions(+), 39 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c -index 3dc17ebe14fa..4102c373b48a 100644 +index 04af03285a20..ae585828c388 100644 --- a/drivers/media/v4l2-core/v4l2-common.c +++ b/drivers/media/v4l2-core/v4l2-common.c @@ -333,6 +333,33 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf @@ -345,230 +345,13 @@ of 8 for NV15 and 4 for NV20. Signed-off-by: Jonas Karlman --- - .../userspace-api/media/v4l/pixfmt-nv15.rst | 101 ++++++++++++++++++ - .../userspace-api/media/v4l/pixfmt-nv20.rst | 99 +++++++++++++++++ - .../userspace-api/media/v4l/yuv-formats.rst | 2 + - drivers/media/v4l2-core/v4l2-common.c | 3 + - drivers/media/v4l2-core/v4l2-ioctl.c | 2 + - include/uapi/linux/videodev2.h | 3 + - 6 files changed, 210 insertions(+) - create mode 100644 Documentation/userspace-api/media/v4l/pixfmt-nv15.rst - create mode 100644 Documentation/userspace-api/media/v4l/pixfmt-nv20.rst + drivers/media/v4l2-core/v4l2-common.c | 3 +++ + drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++ + include/uapi/linux/videodev2.h | 3 +++ + 3 files changed, 8 insertions(+) -diff --git a/Documentation/userspace-api/media/v4l/pixfmt-nv15.rst b/Documentation/userspace-api/media/v4l/pixfmt-nv15.rst -new file mode 100644 -index 000000000000..d059db58c6e0 ---- /dev/null -+++ b/Documentation/userspace-api/media/v4l/pixfmt-nv15.rst -@@ -0,0 +1,101 @@ -+.. Permission is granted to copy, distribute and/or modify this -+.. document under the terms of the GNU Free Documentation License, -+.. Version 1.1 or any later version published by the Free Software -+.. Foundation, with no Invariant Sections, no Front-Cover Texts -+.. and no Back-Cover Texts. A copy of the license is included at -+.. Documentation/userspace-api/media/fdl-appendix.rst. -+.. -+.. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections -+ -+.. _V4L2-PIX-FMT-NV15: -+ -+************************** -+V4L2_PIX_FMT_NV15 ('NV15') -+************************** -+ -+Format with ½ horizontal and vertical chroma resolution, also known as -+YUV 4:2:0. One luminance and one chrominance plane with alternating -+chroma samples similar to ``V4L2_PIX_FMT_NV12`` but with 10-bit samples -+that are grouped into four and packed into five bytes. -+ -+The '15' suffix refers to the optimum effective bits per pixel which is -+achieved when the total number of luminance samples is a multiple of 8. -+ -+ -+Description -+=========== -+ -+This is a packed 10-bit two-plane version of the YUV 4:2:0 format. The -+three components are separated into two sub-images or planes. The Y plane -+is first. The Y plane has five bytes per each group of four pixels. A -+combined CbCr plane immediately follows the Y plane in memory. The CbCr -+plane is the same width, in bytes, as the Y plane (and of the image), but -+is half as tall in pixels. Each CbCr pair belongs to four pixels. For -+example, Cb\ :sub:`00`/Cr\ :sub:`00` belongs to Y'\ :sub:`00`, -+Y'\ :sub:`01`, Y'\ :sub:`10`, Y'\ :sub:`11`. -+ -+If the Y plane has pad bytes after each row, then the CbCr plane has as -+many pad bytes after its rows. -+ -+**Byte Order.** -+Little endian. Each cell is one byte. Pixels cross the byte boundary. -+ -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ -+ * - start + 0: -+ - Y'\ :sub:`00[7:0]` -+ - Y'\ :sub:`01[5:0]`\ Y'\ :sub:`00[9:8]` -+ - Y'\ :sub:`02[3:0]`\ Y'\ :sub:`01[9:6]` -+ - Y'\ :sub:`03[1:0]`\ Y'\ :sub:`02[9:4]` -+ - Y'\ :sub:`03[9:2]` -+ * - start + 5: -+ - Y'\ :sub:`10[7:0]` -+ - Y'\ :sub:`11[5:0]`\ Y'\ :sub:`10[9:8]` -+ - Y'\ :sub:`12[3:0]`\ Y'\ :sub:`11[9:6]` -+ - Y'\ :sub:`13[1:0]`\ Y'\ :sub:`12[9:4]` -+ - Y'\ :sub:`13[9:2]` -+ * - start + 10: -+ - Cb'\ :sub:`00[7:0]` -+ - Cr'\ :sub:`00[5:0]`\ Cb'\ :sub:`00[9:8]` -+ - Cb'\ :sub:`01[3:0]`\ Cr'\ :sub:`00[9:6]` -+ - Cr'\ :sub:`01[1:0]`\ Cb'\ :sub:`01[9:4]` -+ - Cr'\ :sub:`01[9:2]` -+ -+ -+**Color Sample Location:** -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ -+ * - -+ - 0 -+ - -+ - 1 -+ - 2 -+ - -+ - 3 -+ * - 0 -+ - Y -+ - -+ - Y -+ - Y -+ - -+ - Y -+ * - -+ - -+ - C -+ - -+ - -+ - C -+ - -+ * - 1 -+ - Y -+ - -+ - Y -+ - Y -+ - -+ - Y -diff --git a/Documentation/userspace-api/media/v4l/pixfmt-nv20.rst b/Documentation/userspace-api/media/v4l/pixfmt-nv20.rst -new file mode 100644 -index 000000000000..a8123be0baa3 ---- /dev/null -+++ b/Documentation/userspace-api/media/v4l/pixfmt-nv20.rst -@@ -0,0 +1,99 @@ -+.. Permission is granted to copy, distribute and/or modify this -+.. document under the terms of the GNU Free Documentation License, -+.. Version 1.1 or any later version published by the Free Software -+.. Foundation, with no Invariant Sections, no Front-Cover Texts -+.. and no Back-Cover Texts. A copy of the license is included at -+.. Documentation/userspace-api/media/fdl-appendix.rst. -+.. -+.. TODO: replace it to GFDL-1.1-or-later WITH no-invariant-sections -+ -+.. _V4L2-PIX-FMT-NV20: -+ -+************************** -+V4L2_PIX_FMT_NV20 ('NV20') -+************************** -+ -+Format with ½ horizontal chroma resolution, also known as YUV 4:2:2. -+One luminance and one chrominance plane with alternating chroma samples -+similar to ``V4L2_PIX_FMT_NV16`` but with 10-bit samples -+that are grouped into four and packed into five bytes. -+ -+The '20' suffix refers to the optimum effective bits per pixel which is -+achieved when the total number of luminance samples is a multiple of 4. -+ -+ -+Description -+=========== -+ -+This is a packed 10-bit two-plane version of the YUV 4:2:2 format. The -+three components are separated into two sub-images or planes. The Y plane -+is first. The Y plane has five bytes per each group of four pixels. A -+combined CbCr plane immediately follows the Y plane in memory. The CbCr -+plane is the same width and height, in bytes, as the Y plane (and of the -+image). Each CbCr pair belongs to two pixels. For example, -+Cb\ :sub:`00`/Cr\ :sub:`00` belongs to Y'\ :sub:`00`, Y'\ :sub:`01`. -+ -+If the Y plane has pad bytes after each row, then the CbCr plane has as -+many pad bytes after its rows. -+ -+**Byte Order.** -+Little endian. Each cell is one byte. Pixels cross the byte boundary. -+ -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ -+ * - start + 0: -+ - Y'\ :sub:`00[7:0]` -+ - Y'\ :sub:`01[5:0]`\ Y'\ :sub:`00[9:8]` -+ - Y'\ :sub:`02[3:0]`\ Y'\ :sub:`01[9:6]` -+ - Y'\ :sub:`03[1:0]`\ Y'\ :sub:`02[9:4]` -+ - Y'\ :sub:`03[9:2]` -+ * - start + 5: -+ - Y'\ :sub:`10[7:0]` -+ - Y'\ :sub:`11[5:0]`\ Y'\ :sub:`10[9:8]` -+ - Y'\ :sub:`12[3:0]`\ Y'\ :sub:`11[9:6]` -+ - Y'\ :sub:`13[1:0]`\ Y'\ :sub:`12[9:4]` -+ - Y'\ :sub:`13[9:2]` -+ * - start + 10: -+ - Cb'\ :sub:`00[7:0]` -+ - Cr'\ :sub:`00[5:0]`\ Cb'\ :sub:`00[9:8]` -+ - Cb'\ :sub:`01[3:0]`\ Cr'\ :sub:`00[9:6]` -+ - Cr'\ :sub:`01[1:0]`\ Cb'\ :sub:`01[9:4]` -+ - Cr'\ :sub:`01[9:2]` -+ * - start + 15: -+ - Cb'\ :sub:`10[7:0]` -+ - Cr'\ :sub:`10[5:0]`\ Cb'\ :sub:`10[9:8]` -+ - Cb'\ :sub:`11[3:0]`\ Cr'\ :sub:`10[9:6]` -+ - Cr'\ :sub:`11[1:0]`\ Cb'\ :sub:`11[9:4]` -+ - Cr'\ :sub:`11[9:2]` -+ -+ -+**Color Sample Location:** -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ -+ * - -+ - 0 -+ - -+ - 1 -+ - 2 -+ - -+ - 3 -+ * - 0 -+ - Y -+ - C -+ - Y -+ - Y -+ - C -+ - Y -+ * - 1 -+ - Y -+ - C -+ - Y -+ - Y -+ - C -+ - Y diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c -index 4102c373b48a..0caac755d303 100644 +index ae585828c388..5bafbdbe30b0 100644 --- a/drivers/media/v4l2-core/v4l2-common.c +++ b/drivers/media/v4l2-core/v4l2-common.c @@ -267,6 +267,9 @@ const struct v4l2_format_info *v4l2_format_info(u32 format) @@ -582,10 +365,10 @@ index 4102c373b48a..0caac755d303 100644 { .format = V4L2_PIX_FMT_YVU410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 }, { .format = V4L2_PIX_FMT_YUV411P, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 1 }, diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 9eda8b91d17a..1ff68c1bf14a 100644 +index 05d5db3d85e5..fe43d785414c 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1319,6 +1319,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) +@@ -1282,6 +1282,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_NV61: descr = "Y/CrCb 4:2:2"; break; case V4L2_PIX_FMT_NV24: descr = "Y/CbCr 4:4:4"; break; case V4L2_PIX_FMT_NV42: descr = "Y/CrCb 4:4:4"; break; @@ -595,12 +378,12 @@ index 9eda8b91d17a..1ff68c1bf14a 100644 case V4L2_PIX_FMT_NV21M: descr = "Y/CrCb 4:2:0 (N-C)"; break; case V4L2_PIX_FMT_NV16M: descr = "Y/CbCr 4:2:2 (N-C)"; break; diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index 534eaa4d39bc..f21eba15ceae 100644 +index 9260791b8438..169f8ad6fade 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h -@@ -609,6 +609,9 @@ struct v4l2_pix_format { - #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */ +@@ -603,6 +603,9 @@ struct v4l2_pix_format { #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */ + #define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */ +#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */ +#define V4L2_PIX_FMT_NV20 v4l2_fourcc('N', 'V', '2', '0') /* 20 Y/CbCr 4:2:2 10-bit packed */ @@ -626,7 +409,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index bf632d45282b..6f2d41b2e076 100644 +index 503ae683d0fd..88f5f4bb320b 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -893,9 +893,9 @@ static void config_registers(struct rkvdec_ctx *ctx, @@ -671,7 +454,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index f405dd72ad93..c81ca5c7e979 100644 +index f4c5ee4a1e26..d8d0eab9e25d 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -27,6 +27,17 @@ @@ -692,7 +475,7 @@ index f405dd72ad93..c81ca5c7e979 100644 static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) { struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); -@@ -167,13 +178,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) +@@ -177,13 +188,9 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; @@ -709,7 +492,7 @@ index f405dd72ad93..c81ca5c7e979 100644 } static int rkvdec_enum_framesizes(struct file *file, void *priv, -@@ -239,13 +246,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, +@@ -249,13 +256,7 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, &pix_mp->height, &coded_desc->frmsize); @@ -743,7 +526,7 @@ Signed-off-by: Jonas Karlman 2 files changed, 55 insertions(+), 6 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index c81ca5c7e979..a11474214bde 100644 +index d8d0eab9e25d..d31344c4acaa 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -38,6 +38,16 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, @@ -802,7 +585,7 @@ index c81ca5c7e979..a11474214bde 100644 }; static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { -@@ -176,6 +209,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) +@@ -186,6 +219,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) { struct v4l2_format *f = &ctx->decoded_fmt; @@ -810,7 +593,7 @@ index c81ca5c7e979..a11474214bde 100644 rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; -@@ -231,13 +265,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, +@@ -241,13 +275,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, if (WARN_ON(!coded_desc)) return -EINVAL; @@ -834,7 +617,7 @@ index c81ca5c7e979..a11474214bde 100644 /* Always apply the frmsize constraint of the coded end. */ pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width); -@@ -312,6 +350,7 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv, +@@ -322,6 +360,7 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv, return ret; ctx->decoded_fmt = *f; @@ -842,7 +625,7 @@ index c81ca5c7e979..a11474214bde 100644 return 0; } -@@ -401,6 +440,14 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv, +@@ -411,6 +450,14 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv, if (WARN_ON(!ctx->coded_fmt_desc)) return -EINVAL; @@ -858,10 +641,10 @@ index c81ca5c7e979..a11474214bde 100644 return -EINVAL; diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 77a137cca88e..e95c52e3168a 100644 +index 52ac3874c5e5..7b6f44ee8a1a 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -63,6 +63,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) +@@ -62,6 +62,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) struct rkvdec_coded_fmt_ops { int (*adjust_fmt)(struct rkvdec_ctx *ctx, struct v4l2_format *f); @@ -869,7 +652,7 @@ index 77a137cca88e..e95c52e3168a 100644 int (*start)(struct rkvdec_ctx *ctx); void (*stop)(struct rkvdec_ctx *ctx); int (*run)(struct rkvdec_ctx *ctx); -@@ -96,6 +97,7 @@ struct rkvdec_ctx { +@@ -95,6 +96,7 @@ struct rkvdec_ctx { struct v4l2_fh fh; struct v4l2_format coded_fmt; struct v4l2_format decoded_fmt; @@ -898,7 +681,7 @@ Signed-off-by: Jonas Karlman 2 files changed, 29 insertions(+), 10 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index 6f2d41b2e076..c115cd362a7f 100644 +index 88f5f4bb320b..c9a551dbd9bc 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -1021,6 +1021,25 @@ static int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx, @@ -936,7 +719,7 @@ index 6f2d41b2e076..c115cd362a7f 100644 .stop = rkvdec_h264_stop, .run = rkvdec_h264_run, diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index a11474214bde..b57a39ce4f48 100644 +index d31344c4acaa..d068383aeea8 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -31,7 +31,7 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, @@ -973,7 +756,7 @@ index a11474214bde..b57a39ce4f48 100644 return -EINVAL; if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl)) -@@ -145,6 +141,9 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = { +@@ -155,6 +151,9 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = { static const u32 rkvdec_h264_decoded_fmts[] = { V4L2_PIX_FMT_NV12, @@ -983,46 +766,3 @@ index a11474214bde..b57a39ce4f48 100644 }; static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:38 +0000 -Subject: [PATCH] media: rkvdec: h264: Support profile and level controls - -The Rockchip Video Decoder used in RK3399 supports H.264 profiles from -Baseline to High 4:2:2 up to Level 5.1, except for the Extended profile. - -Expose the V4L2_CID_MPEG_VIDEO_H264_PROFILE and the -V4L2_CID_MPEG_VIDEO_H264_LEVEL control, so that userspace can query the -driver for the list of supported profiles and level. - -Signed-off-by: Jonas Karlman -Reviewed-by: Ezequiel Garcia ---- - drivers/staging/media/rkvdec/rkvdec.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index b57a39ce4f48..9492822c12ae 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -132,6 +132,19 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { - .cfg.def = V4L2_MPEG_VIDEO_H264_START_CODE_ANNEX_B, - .cfg.max = V4L2_MPEG_VIDEO_H264_START_CODE_ANNEX_B, - }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_H264_PROFILE, -+ .cfg.min = V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE, -+ .cfg.max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422, -+ .cfg.menu_skip_mask = -+ BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED), -+ .cfg.def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_H264_LEVEL, -+ .cfg.min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0, -+ .cfg.max = V4L2_MPEG_VIDEO_H264_LEVEL_5_1, -+ }, - }; - - static const struct rkvdec_ctrls rkvdec_h264_ctrls = { diff --git a/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch similarity index 60% rename from projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch rename to projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch index 46a5a8f046..17d13f171f 100644 --- a/projects/Rockchip/patches/linux/default/linux-0021-drm-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch @@ -24,10 +24,10 @@ Reviewed-by: Sandy Huang 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c -index 722c7ebe4e88..2daf8a304b53 100644 +index eda832f9200d..9498e9d466fb 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c -@@ -278,6 +278,14 @@ const struct drm_format_info *__drm_format_info(u32 format) +@@ -258,6 +258,14 @@ const struct drm_format_info *__drm_format_info(u32 format) .num_planes = 2, .char_per_block = { 5, 5, 0 }, .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true }, @@ -43,10 +43,10 @@ index 722c7ebe4e88..2daf8a304b53 100644 .num_planes = 3, .char_per_block = { 2, 2, 2 }, .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0, diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h -index 5498d7a6556a..5b5db0381729 100644 +index f7156322aba5..a30bb7ef7632 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h -@@ -242,6 +242,8 @@ extern "C" { +@@ -279,6 +279,8 @@ extern "C" { * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian */ #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ @@ -76,10 +76,10 @@ Reviewed-by: Sandy Huang 3 files changed, 54 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index c80f7d9fd13f..eb663e25ad9e 100644 +index f5b9028a16a3..9df4a271f3aa 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -261,6 +261,18 @@ static bool has_rb_swapped(uint32_t format) +@@ -262,6 +262,18 @@ static bool has_rb_swapped(uint32_t format) } } @@ -98,7 +98,7 @@ index c80f7d9fd13f..eb663e25ad9e 100644 static enum vop_data_format vop_convert_format(uint32_t format) { switch (format) { -@@ -276,10 +288,13 @@ static enum vop_data_format vop_convert_format(uint32_t format) +@@ -277,10 +289,13 @@ static enum vop_data_format vop_convert_format(uint32_t format) case DRM_FORMAT_BGR565: return VOP_FMT_RGB565; case DRM_FORMAT_NV12: @@ -112,7 +112,7 @@ index c80f7d9fd13f..eb663e25ad9e 100644 return VOP_FMT_YUV444SP; default: DRM_ERROR("unsupported format[%08x]\n", format); -@@ -922,7 +937,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -931,7 +946,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane, dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); @@ -126,7 +126,7 @@ index c80f7d9fd13f..eb663e25ad9e 100644 offset += (src->y1 >> 16) * fb->pitches[0]; dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; -@@ -948,6 +968,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -957,6 +977,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, } VOP_WIN_SET(vop, win, format, format); @@ -134,7 +134,7 @@ index c80f7d9fd13f..eb663e25ad9e 100644 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); -@@ -964,7 +985,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -973,7 +994,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane, uv_obj = fb->obj[1]; rk_uv_obj = to_rockchip_obj(uv_obj); @@ -160,7 +160,7 @@ index 857d97cdc67c..b7169010622a 100644 struct vop_reg act_info; struct vop_reg dsp_info; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 80053d91a301..2c55e1852c3d 100644 +index ca7cc82125cb..fff9c3387b9d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -50,6 +50,23 @@ static const uint32_t formats_win_full[] = { @@ -187,7 +187,7 @@ index 80053d91a301..2c55e1852c3d 100644 static const uint64_t format_modifiers_win_full[] = { DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_MOD_INVALID, -@@ -579,11 +596,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = { +@@ -613,11 +630,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = { static const struct vop_win_phy rk3288_win01_data = { .scl = &rk3288_win_full_scl, @@ -202,7 +202,7 @@ index 80053d91a301..2c55e1852c3d 100644 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), -@@ -713,11 +731,12 @@ static const struct vop_intr rk3368_vop_intr = { +@@ -747,11 +765,12 @@ static const struct vop_intr rk3368_vop_intr = { static const struct vop_win_phy rk3368_win01_data = { .scl = &rk3288_win_full_scl, @@ -217,7 +217,7 @@ index 80053d91a301..2c55e1852c3d 100644 .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12), .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21), .y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22), -@@ -862,11 +881,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { +@@ -896,11 +915,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { static const struct vop_win_phy rk3399_win01_data = { .scl = &rk3288_win_full_scl, @@ -257,10 +257,10 @@ Signed-off-by: Qinglang Miao 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c -index a4a45daf93f2..9b4406191470 100644 +index 8ab3247dbc4a..8429c6706ec5 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.c +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c -@@ -98,7 +98,7 @@ static int cdn_dp_clk_enable(struct cdn_dp_device *dp) +@@ -100,7 +100,7 @@ static int cdn_dp_clk_enable(struct cdn_dp_device *dp) goto err_core_clk; } @@ -294,10 +294,10 @@ Signed-off-by: Qinglang Miao 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index eb663e25ad9e..c6c76e8ab66c 100644 +index 9df4a271f3aa..c3c0de25b8e6 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -602,7 +602,7 @@ static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) +@@ -603,7 +603,7 @@ static int vop_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) struct vop *vop = to_vop(crtc); int ret, i; @@ -306,7 +306,7 @@ index eb663e25ad9e..c6c76e8ab66c 100644 if (ret < 0) { DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret); return ret; -@@ -1933,7 +1933,7 @@ static int vop_initial(struct vop *vop) +@@ -1956,7 +1956,7 @@ static int vop_initial(struct vop *vop) return PTR_ERR(vop->dclk); } @@ -340,7 +340,7 @@ Signed-off-by: Qinglang Miao 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c -index 41edd0a421b2..4d463d50a63a 100644 +index 489d63c05c0d..aaf0b6bbcb85 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c @@ -145,7 +145,7 @@ static int rk3288_lvds_poweron(struct rockchip_lvds *lvds) @@ -362,3 +362,198 @@ index 41edd0a421b2..4d463d50a63a 100644 DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); return ret; +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Thomas Zimmermann +Date: Thu, 24 Jun 2021 11:55:02 +0200 +Subject: [PATCH] drm/rockchip: Implement mmap as GEM object function + +Moving the driver-specific mmap code into a GEM object function allows +for using DRM helpers for various mmap callbacks. + +The respective rockchip functions are being removed. The file_operations +structure fops is now being created by the helper macro +DEFINE_DRM_GEM_FOPS(). + +Signed-off-by: Thomas Zimmermann +Tested-by: Heiko Stuebner +--- + drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 13 +----- + drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c | 3 +- + drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 44 +++++-------------- + drivers/gpu/drm/rockchip/rockchip_drm_gem.h | 7 --- + 4 files changed, 15 insertions(+), 52 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +index b730b8d5d949..2e3ab573a817 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +@@ -208,16 +208,7 @@ static void rockchip_drm_unbind(struct device *dev) + drm_dev_put(drm_dev); + } + +-static const struct file_operations rockchip_drm_driver_fops = { +- .owner = THIS_MODULE, +- .open = drm_open, +- .mmap = rockchip_gem_mmap, +- .poll = drm_poll, +- .read = drm_read, +- .unlocked_ioctl = drm_ioctl, +- .compat_ioctl = drm_compat_ioctl, +- .release = drm_release, +-}; ++DEFINE_DRM_GEM_FOPS(rockchip_drm_driver_fops); + + static const struct drm_driver rockchip_drm_driver = { + .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, +@@ -226,7 +217,7 @@ static const struct drm_driver rockchip_drm_driver = { + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, + .gem_prime_import_sg_table = rockchip_gem_prime_import_sg_table, +- .gem_prime_mmap = rockchip_gem_mmap_buf, ++ .gem_prime_mmap = drm_gem_prime_mmap, + .fops = &rockchip_drm_driver_fops, + .name = DRIVER_NAME, + .desc = DRIVER_DESC, +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c +index 2fdc455c4ad7..d8418dd39d0e 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c +@@ -7,6 +7,7 @@ + #include + #include + #include ++#include + #include + + #include "rockchip_drm_drv.h" +@@ -24,7 +25,7 @@ static int rockchip_fbdev_mmap(struct fb_info *info, + struct drm_fb_helper *helper = info->par; + struct rockchip_drm_private *private = to_drm_private(helper); + +- return rockchip_gem_mmap_buf(private->fbdev_bo, vma); ++ return drm_gem_prime_mmap(private->fbdev_bo, vma); + } + + static const struct fb_ops rockchip_drm_fbdev_ops = { +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +index 7971f57436dd..63eb73b624aa 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +@@ -240,12 +240,22 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj, + int ret; + struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj); + ++ /* ++ * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the ++ * whole buffer from the start. ++ */ ++ vma->vm_pgoff = 0; ++ + /* + * We allocated a struct page table for rk_obj, so clear + * VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap(). + */ ++ vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP; + vma->vm_flags &= ~VM_PFNMAP; + ++ vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); ++ vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); ++ + if (rk_obj->pages) + ret = rockchip_drm_gem_object_mmap_iommu(obj, vma); + else +@@ -257,39 +267,6 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj, + return ret; + } + +-int rockchip_gem_mmap_buf(struct drm_gem_object *obj, +- struct vm_area_struct *vma) +-{ +- int ret; +- +- ret = drm_gem_mmap_obj(obj, obj->size, vma); +- if (ret) +- return ret; +- +- return rockchip_drm_gem_object_mmap(obj, vma); +-} +- +-/* drm driver mmap file operations */ +-int rockchip_gem_mmap(struct file *filp, struct vm_area_struct *vma) +-{ +- struct drm_gem_object *obj; +- int ret; +- +- ret = drm_gem_mmap(filp, vma); +- if (ret) +- return ret; +- +- /* +- * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the +- * whole buffer from the start. +- */ +- vma->vm_pgoff = 0; +- +- obj = vma->vm_private_data; +- +- return rockchip_drm_gem_object_mmap(obj, vma); +-} +- + static void rockchip_gem_release_object(struct rockchip_gem_object *rk_obj) + { + drm_gem_object_release(&rk_obj->base); +@@ -301,6 +278,7 @@ static const struct drm_gem_object_funcs rockchip_gem_object_funcs = { + .get_sg_table = rockchip_gem_prime_get_sg_table, + .vmap = rockchip_gem_prime_vmap, + .vunmap = rockchip_gem_prime_vunmap, ++ .mmap = rockchip_drm_gem_object_mmap, + .vm_ops = &drm_gem_cma_vm_ops, + }; + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h +index 5a70a56cd406..47c1861eece0 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h +@@ -34,13 +34,6 @@ rockchip_gem_prime_import_sg_table(struct drm_device *dev, + int rockchip_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map); + void rockchip_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map); + +-/* drm driver mmap file operations */ +-int rockchip_gem_mmap(struct file *filp, struct vm_area_struct *vma); +- +-/* mmap a gem object to userspace. */ +-int rockchip_gem_mmap_buf(struct drm_gem_object *obj, +- struct vm_area_struct *vma); +- + struct rockchip_gem_object * + rockchip_gem_create_object(struct drm_device *drm, unsigned int size, + bool alloc_kmap); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Andy Yan +Date: Sun, 27 Jun 2021 16:47:37 +0800 +Subject: [PATCH] drm/rockchip: Check iommu itself instead of it's parent for + device_is_available + +When iommu itself is disabled in dts, we should +fallback to non-iommu buffer, check iommu parent +is meanless here. + +Signed-off-by: Andy Yan +--- + drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +index 2e3ab573a817..8161540be6c8 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c ++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +@@ -367,7 +367,7 @@ static int rockchip_drm_platform_of_probe(struct device *dev) + } + + iommu = of_parse_phandle(port->parent, "iommus", 0); +- if (!iommu || !of_device_is_available(iommu->parent)) { ++ if (!iommu || !of_device_is_available(iommu)) { + DRM_DEV_DEBUG(dev, + "no iommu attached for %pOF, using non-iommu buffers\n", + port->parent); diff --git a/projects/Rockchip/patches/linux/default/linux-1001-drm-rockchip.patch b/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch similarity index 95% rename from projects/Rockchip/patches/linux/default/linux-1001-drm-rockchip.patch rename to projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch index 5c159a9078..0614779709 100644 --- a/projects/Rockchip/patches/linux/default/linux-1001-drm-rockchip.patch +++ b/projects/Rockchip/patches/linux/default/linux-1000-drm-rockchip.patch @@ -13,10 +13,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index c6c76e8ab66c..2f98a5e7dce1 100644 +index c3c0de25b8e6..395b7160a3c5 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1554,7 +1554,11 @@ static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) +@@ -1578,7 +1578,11 @@ static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) { struct rockchip_crtc_state *rockchip_state; @@ -47,10 +47,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 54 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 2f98a5e7dce1..defa314a8f96 100644 +index 395b7160a3c5..3603bf81b58b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1167,6 +1167,59 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc) +@@ -1181,6 +1181,59 @@ static void vop_crtc_disable_vblank(struct drm_crtc *crtc) spin_unlock_irqrestore(&vop->irq_lock, flags); } @@ -110,7 +110,7 @@ index 2f98a5e7dce1..defa314a8f96 100644 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) -@@ -1537,6 +1590,7 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, +@@ -1561,6 +1614,7 @@ static void vop_crtc_atomic_flush(struct drm_crtc *crtc, } static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = { @@ -133,10 +133,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index defa314a8f96..a9e6e8bdc848 100644 +index 3603bf81b58b..91ed741d09cd 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1205,6 +1205,9 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, +@@ -1219,6 +1219,9 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, if (!vop_crtc_is_tmds(crtc)) return MODE_OK; @@ -183,10 +183,10 @@ index b7169010622a..0b1984585082 100644 #define VOP_FEATURE_OUTPUT_RGB10 BIT(0) #define VOP_FEATURE_INTERNAL_RGB BIT(1) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 2c55e1852c3d..cf87361108a0 100644 +index fff9c3387b9d..37e623bdf287 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -700,6 +700,7 @@ static const struct vop_intr rk3288_vop_intr = { +@@ -734,6 +734,7 @@ static const struct vop_intr rk3288_vop_intr = { static const struct vop_data rk3288_vop = { .version = VOP_VERSION(3, 1), .feature = VOP_FEATURE_OUTPUT_RGB10, @@ -194,7 +194,7 @@ index 2c55e1852c3d..cf87361108a0 100644 .intr = &rk3288_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -801,6 +802,7 @@ static const struct vop_misc rk3368_misc = { +@@ -835,6 +836,7 @@ static const struct vop_misc rk3368_misc = { static const struct vop_data rk3368_vop = { .version = VOP_VERSION(3, 2), @@ -202,7 +202,7 @@ index 2c55e1852c3d..cf87361108a0 100644 .intr = &rk3368_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -822,6 +824,7 @@ static const struct vop_intr rk3366_vop_intr = { +@@ -856,6 +858,7 @@ static const struct vop_intr rk3366_vop_intr = { static const struct vop_data rk3366_vop = { .version = VOP_VERSION(3, 4), @@ -210,7 +210,7 @@ index 2c55e1852c3d..cf87361108a0 100644 .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -929,6 +932,7 @@ static const struct vop_afbc rk3399_vop_afbc = { +@@ -963,6 +966,7 @@ static const struct vop_afbc rk3399_vop_afbc = { static const struct vop_data rk3399_vop_big = { .version = VOP_VERSION(3, 5), .feature = VOP_FEATURE_OUTPUT_RGB10, @@ -218,7 +218,7 @@ index 2c55e1852c3d..cf87361108a0 100644 .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -955,6 +959,7 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { +@@ -989,6 +993,7 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_lit_win_yuv2yuv_data[] = { static const struct vop_data rk3399_vop_lit = { .version = VOP_VERSION(3, 6), @@ -226,7 +226,7 @@ index 2c55e1852c3d..cf87361108a0 100644 .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -975,6 +980,7 @@ static const struct vop_win_data rk3228_vop_win_data[] = { +@@ -1009,6 +1014,7 @@ static const struct vop_win_data rk3228_vop_win_data[] = { static const struct vop_data rk3228_vop = { .version = VOP_VERSION(3, 7), .feature = VOP_FEATURE_OUTPUT_RGB10, @@ -234,7 +234,7 @@ index 2c55e1852c3d..cf87361108a0 100644 .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, -@@ -1046,6 +1052,7 @@ static const struct vop_win_data rk3328_vop_win_data[] = { +@@ -1080,6 +1086,7 @@ static const struct vop_win_data rk3328_vop_win_data[] = { static const struct vop_data rk3328_vop = { .version = VOP_VERSION(3, 8), .feature = VOP_FEATURE_OUTPUT_RGB10, @@ -256,10 +256,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index a9e6e8bdc848..bf44282409ab 100644 +index 91ed741d09cd..5badaf5a87e7 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1199,6 +1199,7 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, +@@ -1213,6 +1213,7 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) { struct vop *vop = to_vop(crtc); @@ -267,7 +267,7 @@ index a9e6e8bdc848..bf44282409ab 100644 long rounded_rate; long lowest, highest; -@@ -1220,6 +1221,10 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, +@@ -1234,6 +1235,10 @@ static enum drm_mode_status vop_crtc_mode_valid(struct drm_crtc *crtc, if (rounded_rate > highest) return MODE_CLOCK_HIGH; @@ -278,7 +278,7 @@ index a9e6e8bdc848..bf44282409ab 100644 return MODE_OK; } -@@ -1228,8 +1233,19 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, +@@ -1242,8 +1247,19 @@ static bool vop_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *adjusted_mode) { struct vop *vop = to_vop(crtc); @@ -340,7 +340,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 23de359a1dec..f78851e7ef16 100644 +index 830bdd5e9b7c..08c4ea2b6bf2 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -181,7 +181,7 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { @@ -367,7 +367,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index f78851e7ef16..a308adb56d2f 100644 +index 08c4ea2b6bf2..546970b36dd2 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -183,6 +183,7 @@ static const struct dw_hdmi_phy_config rockchip_phy_config[] = { @@ -397,7 +397,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index a308adb56d2f..5b273f26f177 100644 +index 546970b36dd2..3bbd90e2e40b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -160,20 +160,8 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { @@ -455,7 +455,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 69 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 5b273f26f177..b5d2cdaa24fa 100644 +index 3bbd90e2e40b..2cdaeb76ab9e 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -79,80 +79,88 @@ struct rockchip_hdmi { @@ -628,7 +628,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index b5d2cdaa24fa..5f7ab8e6bb72 100644 +index 2cdaeb76ab9e..279d900e3e51 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -221,19 +221,11 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, @@ -667,7 +667,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 5f7ab8e6bb72..0e7ca368314d 100644 +index 279d900e3e51..20c37b22b3eb 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -225,7 +225,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, @@ -693,7 +693,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 0e7ca368314d..6f7641fbe6cc 100644 +index 20c37b22b3eb..f8001dd8dca7 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -306,6 +306,8 @@ static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, @@ -721,7 +721,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 6f7641fbe6cc..cc20a83fa9b8 100644 +index f8001dd8dca7..8b957af7c61a 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -396,9 +396,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = { @@ -756,7 +756,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index cc20a83fa9b8..fd614c8a3486 100644 +index 8b957af7c61a..303c6e81ca4f 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -516,8 +516,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, @@ -822,10 +822,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c -index 47d6482dda9d..a2b4d5487514 100644 +index a24a35553e13..7343d2d7676b 100644 --- a/drivers/clk/rockchip/clk-rk3228.c +++ b/drivers/clk/rockchip/clk-rk3228.c -@@ -408,7 +408,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { +@@ -409,7 +409,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { RK2928_CLKSEL_CON(29), 0, 3, DFLAGS), DIV(0, "sclk_vop_pre", "sclk_vop_src", 0, RK2928_CLKSEL_CON(27), 8, 8, DFLAGS), @@ -846,10 +846,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index cf87361108a0..05ade8ea962f 100644 +index 37e623bdf287..28df0bc79812 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -697,7 +697,7 @@ static const struct vop_intr rk3288_vop_intr = { +@@ -731,7 +731,7 @@ static const struct vop_intr rk3288_vop_intr = { .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8), }; @@ -858,7 +858,7 @@ index cf87361108a0..05ade8ea962f 100644 .version = VOP_VERSION(3, 1), .feature = VOP_FEATURE_OUTPUT_RGB10, .max_output = { 3840, 2160 }, -@@ -710,6 +710,19 @@ static const struct vop_data rk3288_vop = { +@@ -744,6 +744,19 @@ static const struct vop_data rk3288_vop = { .lut_size = 1024, }; @@ -878,7 +878,7 @@ index cf87361108a0..05ade8ea962f 100644 static const int rk3368_vop_intrs[] = { FS_INTR, 0, 0, -@@ -1075,8 +1088,10 @@ static const struct of_device_id vop_driver_dt_match[] = { +@@ -1109,8 +1122,10 @@ static const struct of_device_id vop_driver_dt_match[] = { .data = &rk3066_vop }, { .compatible = "rockchip,rk3188-vop", .data = &rk3188_vop }, @@ -903,10 +903,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 01ea1f170f77..3575dea1ee29 100644 +index 9c5a7791a1ab..b64b8fbe388d 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1037,7 +1037,7 @@ rga: rga@ff920000 { +@@ -1018,7 +1018,7 @@ rga: rga@ff920000 { }; vopb: vop@ff930000 { @@ -915,7 +915,7 @@ index 01ea1f170f77..3575dea1ee29 100644 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; interrupts = ; clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; -@@ -1087,7 +1087,7 @@ vopb_mmu: iommu@ff930300 { +@@ -1068,7 +1068,7 @@ vopb_mmu: iommu@ff930300 { }; vopl: vop@ff940000 { @@ -939,7 +939,7 @@ Signed-off-by: Jonas Karlman 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 0c79a9ba48bb..50199329ad6f 100644 +index e7c7c9b9c646..ee1968ecaa8f 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -137,7 +137,8 @@ struct dw_hdmi_phy_data { @@ -989,7 +989,7 @@ index 7b8ec8310699..539d86131fd4 100644 const struct rcar_hdmi_phy_params *params = rcar_hdmi_phy_params; diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h -index ea34ca146b82..4f61ede6486d 100644 +index 6a5716655619..182c8a8781df 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -152,7 +152,8 @@ struct dw_hdmi_plat_data { @@ -999,9 +999,9 @@ index ea34ca146b82..4f61ede6486d 100644 - unsigned long mpixelclock); + unsigned long mpixelclock, + unsigned long mtmdsclock); - }; - struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, + unsigned int disable_cec : 1; + }; From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman @@ -1016,7 +1016,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 50199329ad6f..2581789178c7 100644 +index ee1968ecaa8f..8b3ce725b211 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1448,6 +1448,7 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, @@ -1075,7 +1075,7 @@ Signed-off-by: Jonas Karlman 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 2581789178c7..6d319b95b992 100644 +index 8b3ce725b211..473db9629a66 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1450,7 +1450,9 @@ static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, @@ -1090,7 +1090,7 @@ index 2581789178c7..6d319b95b992 100644 /* PLL/MPLL Cfg - always match on final entry */ for (; mpll_config->mpixelclock != ~0UL; mpll_config++) diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h -index 4f61ede6486d..0ebe01835d2a 100644 +index 182c8a8781df..5387d2cd1560 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -149,6 +149,7 @@ struct dw_hdmi_plat_data { @@ -1113,7 +1113,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index fd614c8a3486..c22add144cf4 100644 +index 303c6e81ca4f..73fad678b6ee 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -221,8 +221,15 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, @@ -1154,7 +1154,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index c22add144cf4..1e558af2c9b2 100644 +index 73fad678b6ee..6471d601b98b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -165,6 +165,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { @@ -1225,7 +1225,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 41 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 1e558af2c9b2..6dbd0e422ca1 100644 +index 6471d601b98b..9af45fdfbd19 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -205,6 +205,46 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = { @@ -1302,7 +1302,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 78 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 6dbd0e422ca1..510ae5d5f133 100644 +index 9af45fdfbd19..134c2db8d0fe 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -68,6 +68,7 @@ struct rockchip_hdmi { @@ -1501,10 +1501,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 4 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index bf44282409ab..25b89ddb446d 100644 +index 5badaf5a87e7..af9e40d7f49b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1854,19 +1854,10 @@ static int vop_create_crtc(struct vop *vop) +@@ -1877,19 +1877,10 @@ static int vop_create_crtc(struct vop *vop) int ret; int i; @@ -1524,7 +1524,7 @@ index bf44282409ab..25b89ddb446d 100644 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base, 0, &vop_plane_funcs, win_data->phy->data_formats, -@@ -1899,32 +1890,13 @@ static int vop_create_crtc(struct vop *vop) +@@ -1922,32 +1913,13 @@ static int vop_create_crtc(struct vop *vop) drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size); } @@ -1587,10 +1587,10 @@ index 3aa37e177667..a2b59faa9184 100644 dev->mode_config.helper_private = &rockchip_mode_config_helpers; } diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 25b89ddb446d..74d7e474bf89 100644 +index af9e40d7f49b..ab3ae8d03231 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1831,7 +1831,7 @@ static irqreturn_t vop_isr(int irq, void *data) +@@ -1854,7 +1854,7 @@ static irqreturn_t vop_isr(int irq, void *data) return ret; } @@ -1599,7 +1599,7 @@ index 25b89ddb446d..74d7e474bf89 100644 const struct vop_win_data *win_data) { unsigned int flags = 0; -@@ -1841,6 +1841,8 @@ static void vop_plane_add_properties(struct drm_plane *plane, +@@ -1864,6 +1864,8 @@ static void vop_plane_add_properties(struct drm_plane *plane, if (flags) drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, DRM_MODE_ROTATE_0 | flags); @@ -1608,7 +1608,7 @@ index 25b89ddb446d..74d7e474bf89 100644 } static int vop_create_crtc(struct vop *vop) -@@ -1872,7 +1874,7 @@ static int vop_create_crtc(struct vop *vop) +@@ -1895,7 +1897,7 @@ static int vop_create_crtc(struct vop *vop) plane = &vop_win->base; drm_plane_helper_add(plane, &plane_helper_funcs); @@ -1629,10 +1629,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 74d7e474bf89..d8e0c5a4df01 100644 +index ab3ae8d03231..8c6d1881787c 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -1831,8 +1831,23 @@ static irqreturn_t vop_isr(int irq, void *data) +@@ -1854,8 +1854,23 @@ static irqreturn_t vop_isr(int irq, void *data) return ret; } @@ -1657,7 +1657,7 @@ index 74d7e474bf89..d8e0c5a4df01 100644 { unsigned int flags = 0; -@@ -1843,6 +1858,19 @@ static void vop_plane_add_properties(struct drm_plane *plane, int zpos, +@@ -1866,6 +1881,19 @@ static void vop_plane_add_properties(struct drm_plane *plane, int zpos, DRM_MODE_ROTATE_0 | flags); drm_plane_create_zpos_immutable_property(plane, zpos); @@ -1677,7 +1677,7 @@ index 74d7e474bf89..d8e0c5a4df01 100644 } static int vop_create_crtc(struct vop *vop) -@@ -1874,7 +1902,7 @@ static int vop_create_crtc(struct vop *vop) +@@ -1897,7 +1925,7 @@ static int vop_create_crtc(struct vop *vop) plane = &vop_win->base; drm_plane_helper_add(plane, &plane_helper_funcs); @@ -1703,10 +1703,10 @@ Signed-off-by: Jonas Karlman 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 3575dea1ee29..03e86d012edd 100644 +index b64b8fbe388d..38da07f42cd5 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1046,6 +1046,8 @@ vopb: vop@ff930000 { +@@ -1027,6 +1027,8 @@ vopb: vop@ff930000 { resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; reset-names = "axi", "ahb", "dclk"; iommus = <&vopb_mmu>; @@ -1716,10 +1716,10 @@ index 3575dea1ee29..03e86d012edd 100644 vopb_out: port { diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index 93c794695c46..db6c8bbb35f4 100644 +index baa5aebd3277..20a3cdbbe909 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c -@@ -231,7 +231,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { +@@ -232,7 +232,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), @@ -1728,7 +1728,7 @@ index 93c794695c46..db6c8bbb35f4 100644 }; static struct clk_div_table div_hclk_cpu_t[] = { -@@ -441,7 +441,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { +@@ -442,7 +442,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS, RK3288_CLKGATE_CON(3), 4, GFLAGS), @@ -1752,7 +1752,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index db6c8bbb35f4..426309f5dd44 100644 +index 20a3cdbbe909..47a2527fd238 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -121,6 +121,27 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { @@ -1783,7 +1783,7 @@ index db6c8bbb35f4..426309f5dd44 100644 #define RK3288_DIV_ACLK_CORE_M0_MASK 0xf #define RK3288_DIV_ACLK_CORE_M0_SHIFT 0 #define RK3288_DIV_ACLK_CORE_MP_MASK 0xf -@@ -231,7 +252,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { +@@ -232,7 +253,7 @@ static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = { [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12), RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates), [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16), @@ -1806,7 +1806,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 16 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index 426309f5dd44..b3247a3a7290 100644 +index 47a2527fd238..233890555616 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -127,18 +127,34 @@ static struct rockchip_pll_rate_table rk3288_npll_rates[] = { @@ -1857,7 +1857,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c -index 7df2f1e00347..d39d9ea39aca 100644 +index 62a4f2543960..980223c32aba 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -105,6 +105,25 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { @@ -1926,7 +1926,7 @@ index 7df2f1e00347..d39d9ea39aca 100644 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS); static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata = -@@ -1160,7 +1180,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { +@@ -1162,7 +1182,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(28), 0, GFLAGS), @@ -1947,10 +1947,10 @@ Subject: [PATCH] HACK: dts: rockchip: do not use vopl for hdmi 2 files changed, 18 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 03e86d012edd..746acfac1e92 100644 +index 38da07f42cd5..831484253e27 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1104,11 +1104,6 @@ vopl_out: port { +@@ -1085,11 +1085,6 @@ vopl_out: port { #address-cells = <1>; #size-cells = <0>; @@ -1962,7 +1962,7 @@ index 03e86d012edd..746acfac1e92 100644 vopl_out_edp: endpoint@1 { reg = <1>; remote-endpoint = <&edp_in_vopl>; -@@ -1249,10 +1244,6 @@ hdmi_in_vopb: endpoint@0 { +@@ -1230,10 +1225,6 @@ hdmi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_hdmi>; }; @@ -1974,10 +1974,10 @@ index 03e86d012edd..746acfac1e92 100644 }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 2551b238b97c..ea1ef6c7455a 100644 +index 44def886b391..52a748053a97 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1639,11 +1639,6 @@ vopl_out_edp: endpoint@1 { +@@ -1642,11 +1642,6 @@ vopl_out_edp: endpoint@1 { remote-endpoint = <&edp_in_vopl>; }; @@ -1989,7 +1989,7 @@ index 2551b238b97c..ea1ef6c7455a 100644 vopl_out_mipi1: endpoint@3 { reg = <3>; remote-endpoint = <&mipi1_in_vopl>; -@@ -1815,10 +1810,6 @@ hdmi_in_vopb: endpoint@0 { +@@ -1840,10 +1835,6 @@ hdmi_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_hdmi>; }; @@ -2012,7 +2012,7 @@ Subject: [PATCH] WIP: drm/bridge: dw-hdmi: limit mode and bus format to 1 file changed, 76 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 6d319b95b992..c2425d7fc465 100644 +index 473db9629a66..53fb6cf26137 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1859,6 +1859,21 @@ static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, @@ -2070,7 +2070,7 @@ index 6d319b95b992..c2425d7fc465 100644 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock); /* Set up HDMI_FC_INVIDCONF */ -@@ -2544,8 +2541,21 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) +@@ -2528,8 +2525,21 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) * - MEDIA_BUS_FMT_RGB888_1X24, */ @@ -2094,7 +2094,7 @@ index 6d319b95b992..c2425d7fc465 100644 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, struct drm_bridge_state *bridge_state, -@@ -2557,8 +2567,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2541,8 +2551,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, struct drm_display_info *info = &conn->display_info; struct drm_display_mode *mode = &crtc_state->mode; u8 max_bpc = conn_state->max_requested_bpc; @@ -2103,7 +2103,7 @@ index 6d319b95b992..c2425d7fc465 100644 u32 *output_fmts; unsigned int i = 0; -@@ -2581,29 +2589,33 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2565,29 +2573,33 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, * If the current mode enforces 4:2:0, force the output but format * to 4:2:0 and do not add the YUV422/444/RGB formats */ @@ -2145,7 +2145,7 @@ index 6d319b95b992..c2425d7fc465 100644 } /* -@@ -2612,40 +2624,51 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, +@@ -2596,40 +2608,51 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, */ if (max_bpc >= 16 && info->bpc == 16) { @@ -2208,7 +2208,7 @@ index 6d319b95b992..c2425d7fc465 100644 *num_output_fmts = i; -@@ -2825,11 +2848,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, +@@ -2809,11 +2832,20 @@ dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, struct dw_hdmi *hdmi = bridge->driver_private; const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; enum drm_mode_status mode_status = MODE_OK; @@ -2241,7 +2241,7 @@ Subject: [PATCH] WIP: drm/rockchip: dw_hdmi: add 10-bit rgb bus format 2 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 510ae5d5f133..43ad0278fad1 100644 +index 134c2db8d0fe..cba63dd5e8c8 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -77,6 +77,7 @@ struct rockchip_hdmi { @@ -2359,7 +2359,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index c2425d7fc465..f86b8fa40ab6 100644 +index 53fb6cf26137..df8ff6af9157 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1646,6 +1646,7 @@ static void hdmi_config_AVI(struct dw_hdmi *hdmi, @@ -2379,25 +2379,25 @@ index c2425d7fc465..f86b8fa40ab6 100644 /* * The Designware IP uses a different byte format from standard * AVI info frames, though generally the bits are in the correct -@@ -2431,7 +2434,8 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, +@@ -2416,7 +2419,8 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, if (!crtc) return 0; -- if (!hdr_metadata_equal(old_state, new_state)) { -+ if (!hdr_metadata_equal(old_state, new_state) || +- if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { ++ if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state) || + old_state->content_type != new_state->content_type) { crtc_state = drm_atomic_get_crtc_state(state, crtc); if (IS_ERR(crtc_state)) return PTR_ERR(crtc_state); -@@ -2499,6 +2503,8 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) +@@ -2484,6 +2488,8 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) drm_connector_attach_max_bpc_property(connector, 8, 16); + drm_connector_attach_content_type_property(connector); + if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe) - drm_object_attach_property(&connector->base, - connector->dev->mode_config.hdr_output_metadata_property, 0); + drm_connector_attach_hdr_output_metadata_property(connector); + From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman @@ -2412,7 +2412,7 @@ Subject: [PATCH] WIP: drm/rockchip: add yuv444 support 4 files changed, 77 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 43ad0278fad1..c8eaeb484672 100644 +index cba63dd5e8c8..6429892ac4df 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -62,6 +62,7 @@ struct rockchip_hdmi_chip_data { @@ -2490,10 +2490,10 @@ index 43ad0278fad1..c8eaeb484672 100644 static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index d8e0c5a4df01..9fde1c27072b 100644 +index 8c6d1881787c..abf3442baac0 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -325,6 +325,17 @@ static int vop_convert_afbc_format(uint32_t format) +@@ -326,6 +326,17 @@ static int vop_convert_afbc_format(uint32_t format) return -EINVAL; } @@ -2511,7 +2511,7 @@ index d8e0c5a4df01..9fde1c27072b 100644 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, uint32_t dst, bool is_horizontal, int vsu_mode, int *vskiplines) -@@ -1375,6 +1386,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1395,6 +1406,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, u16 vact_end = vact_st + vdisplay; uint32_t pin_pol, val; int dither_bpc = s->output_bpc ? s->output_bpc : 10; @@ -2519,7 +2519,7 @@ index d8e0c5a4df01..9fde1c27072b 100644 int ret; if (old_state && old_state->self_refresh_active) { -@@ -1448,6 +1460,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1468,6 +1480,8 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) s->output_mode = ROCKCHIP_OUT_MODE_P888; @@ -2528,7 +2528,7 @@ index d8e0c5a4df01..9fde1c27072b 100644 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) VOP_REG_SET(vop, common, pre_dither_down, 1); else -@@ -1463,6 +1477,21 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1483,6 +1497,21 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, VOP_REG_SET(vop, common, out_mode, s->output_mode); @@ -2572,10 +2572,10 @@ index 0b1984585082..72dd670bf2a7 100644 struct vop_intr { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 05ade8ea962f..f276ef4b3f64 100644 +index 28df0bc79812..e64cedf7c7a1 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -662,6 +662,11 @@ static const struct vop_common rk3288_common = { +@@ -696,6 +696,11 @@ static const struct vop_common rk3288_common = { .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), @@ -2587,7 +2587,7 @@ index 05ade8ea962f..f276ef4b3f64 100644 }; /* -@@ -1029,6 +1034,10 @@ static const struct vop_output rk3328_output = { +@@ -1063,6 +1068,10 @@ static const struct vop_output rk3328_output = { static const struct vop_misc rk3328_misc = { .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), @@ -2598,7 +2598,7 @@ index 05ade8ea962f..f276ef4b3f64 100644 }; static const struct vop_common rk3328_common = { -@@ -1041,6 +1050,11 @@ static const struct vop_common rk3328_common = { +@@ -1075,6 +1084,11 @@ static const struct vop_common rk3328_common = { .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), @@ -2624,7 +2624,7 @@ Subject: [PATCH] WIP: drm/rockchip: add yuv420 support 4 files changed, 47 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index c8eaeb484672..9fe690570e3d 100644 +index 6429892ac4df..257770ea2dc7 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -386,9 +386,21 @@ static bool is_yuv444(u32 format) @@ -2688,10 +2688,10 @@ index c8eaeb484672..9fe690570e3d 100644 static struct rockchip_hdmi_chip_data rk3399_chip_data = { diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 9fde1c27072b..4d855724e1dd 100644 +index abf3442baac0..5238bcbc7bae 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -326,6 +326,19 @@ static int vop_convert_afbc_format(uint32_t format) +@@ -327,6 +327,19 @@ static int vop_convert_afbc_format(uint32_t format) } static bool is_yuv_output(uint32_t bus_format) @@ -2711,7 +2711,7 @@ index 9fde1c27072b..4d855724e1dd 100644 { switch (bus_format) { case MEDIA_BUS_FMT_YUV8_1X24: -@@ -1460,7 +1473,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1480,7 +1493,7 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) s->output_mode = ROCKCHIP_OUT_MODE_P888; @@ -2720,7 +2720,7 @@ index 9fde1c27072b..4d855724e1dd 100644 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8) VOP_REG_SET(vop, common, pre_dither_down, 1); -@@ -1477,6 +1490,9 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, +@@ -1497,6 +1510,9 @@ static void vop_crtc_atomic_enable(struct drm_crtc *crtc, VOP_REG_SET(vop, common, out_mode, s->output_mode); @@ -2760,10 +2760,10 @@ index 72dd670bf2a7..a997578e174a 100644 /* output flags */ #define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index f276ef4b3f64..8c99cc2a7eda 100644 +index e64cedf7c7a1..a13059052124 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -664,6 +664,7 @@ static const struct vop_common rk3288_common = { +@@ -698,6 +698,7 @@ static const struct vop_common rk3288_common = { .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), .overlay_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 16), @@ -2771,7 +2771,7 @@ index f276ef4b3f64..8c99cc2a7eda 100644 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), .dsp_out_yuv = VOP_REG(RK3288_POST_SCL_CTRL, 0x1, 2), .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), -@@ -1052,6 +1053,7 @@ static const struct vop_common rk3328_common = { +@@ -1086,6 +1087,7 @@ static const struct vop_common rk3328_common = { .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), @@ -2791,7 +2791,7 @@ Subject: [PATCH] drm/rockchip: enable ycbcr_420_allowed and ycbcr_444_allowed 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index 9fe690570e3d..bccdbb3e0a54 100644 +index 257770ea2dc7..78b77b31436a 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -595,6 +595,7 @@ static const struct dw_hdmi_phy_ops rk3228_hdmi_phy_ops = { @@ -2826,7 +2826,7 @@ Signed-off-by: Alex Bee 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index bccdbb3e0a54..a612bf3da9ee 100644 +index 78b77b31436a..976dd3c9c26f 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -305,16 +305,30 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, @@ -2874,10 +2874,10 @@ Subject: [PATCH] !fixup drm/rockchip: rk3368's vop does not support 10-bit 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 8c99cc2a7eda..9ca9fff0d359 100644 +index a13059052124..11a80117f5bc 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -751,8 +751,8 @@ static const struct vop_intr rk3368_vop_intr = { +@@ -785,8 +785,8 @@ static const struct vop_intr rk3368_vop_intr = { static const struct vop_win_phy rk3368_win01_data = { .scl = &rk3288_win_full_scl, @@ -2900,10 +2900,10 @@ Signed-off-by: Alex Bee 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -index 9ca9fff0d359..e34482c3d2be 100644 +index 11a80117f5bc..43541a042a81 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c -@@ -1069,12 +1069,36 @@ static const struct vop_intr rk3328_vop_intr = { +@@ -1103,12 +1103,36 @@ static const struct vop_intr rk3328_vop_intr = { .clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0), }; @@ -2954,10 +2954,10 @@ Subject: [PATCH] rockchip: vop: force skip lines if image too big 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 4d855724e1dd..5622ffd1b587 100644 +index 5238bcbc7bae..20e45a23edf4 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -932,6 +932,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -941,6 +941,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, int format; int is_yuv = fb->format->is_yuv; int i; @@ -2965,7 +2965,7 @@ index 4d855724e1dd..5622ffd1b587 100644 /* * can't update plane when vop is disabled. -@@ -950,8 +951,14 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -959,8 +960,14 @@ static void vop_plane_atomic_update(struct drm_plane *plane, obj = fb->obj[0]; rk_obj = to_rockchip_obj(obj); @@ -2981,7 +2981,7 @@ index 4d855724e1dd..5622ffd1b587 100644 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff); dsp_info = (drm_rect_height(dest) - 1) << 16; -@@ -993,7 +1000,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -1002,7 +1009,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, VOP_WIN_SET(vop, win, format, format); VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format)); @@ -2990,7 +2990,7 @@ index 4d855724e1dd..5622ffd1b587 100644 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); VOP_WIN_SET(vop, win, y_mir_en, -@@ -1017,7 +1024,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, +@@ -1026,7 +1033,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, offset += (src->y1 >> 16) * fb->pitches[1] / vsub; dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; @@ -3014,10 +3014,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index d327fd300116..31c48c38c955 100644 +index cfc57be009a6..9c10b6e3b9bc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -805,8 +805,8 @@ cru: clock-controller@ff440000 { +@@ -793,8 +793,8 @@ cru: clock-controller@ff440000 { <0>, <24000000>, <24000000>, <24000000>, <15000000>, <15000000>, @@ -3046,7 +3046,7 @@ this. 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c -index b3247a3a7290..f5617529dbb5 100644 +index 233890555616..676e7c3c6f2b 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -122,7 +122,7 @@ static struct rockchip_pll_rate_table rk3288_pll_rates[] = { @@ -3085,7 +3085,7 @@ Signed-off-by: Alex Bee 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index f86b8fa40ab6..3340aef73d8d 100644 +index df8ff6af9157..5642a8c9bed5 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -81,15 +81,15 @@ static const u16 csc_coeff_rgb_out_eitu709[3][4] = { @@ -3131,7 +3131,7 @@ Signed-off-by: Alex Bee 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c -index d39d9ea39aca..16b0bf173299 100644 +index 980223c32aba..09c6f8020212 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -107,20 +107,34 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = { @@ -3213,7 +3213,7 @@ Signed-off-by: Alex Bee 1 file changed, 173 insertions(+), 25 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c -index 3719309ad0d0..00025dcd3bb9 100644 +index 2f01259823ea..1889e78e18ea 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -292,31 +292,179 @@ struct inno_hdmi_phy_drv_data { @@ -3445,7 +3445,7 @@ Signed-off-by: Algea Cao 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 3340aef73d8d..d798846579f5 100644 +index 5642a8c9bed5..84cc52858ffb 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -1060,7 +1060,7 @@ static void hdmi_video_csc(struct dw_hdmi *hdmi) @@ -3457,13 +3457,12 @@ index 3340aef73d8d..d798846579f5 100644 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { case 8: - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Tue, 1 Jun 2021 19:24:37 +0200 -Subject: [PATCH] drm/rockchip: allow 4096px with modes +Subject: [PATCH] drm/rockchip: allow 4096px width modes -There is no reason to limit to modes up to 3840. +There is not reason to limit vop output to 3840px width modes. Also drop the limitation from dw_hdmi_rockchip_mode_valid, since the max dimenstions of the actual vop version is validated in vop_crtc_mode_valid anyways. @@ -3475,7 +3474,7 @@ Signed-off-by: Alex Bee 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c -index a612bf3da9ee..e4cfa6adbd87 100644 +index 8d1d2b8d038b..07e1327acf5e 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -329,7 +329,7 @@ dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, @@ -3488,10 +3487,10 @@ index a612bf3da9ee..e4cfa6adbd87 100644 static void diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -index 5622ffd1b587..a0d27a9a9675 100644 +index 20a73cb3005e..b1473459a579 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c -@@ -401,8 +401,8 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, +@@ -402,8 +402,8 @@ static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, if (info->is_yuv) is_yuv = true; @@ -3502,3 +3501,5 @@ index 5622ffd1b587..a0d27a9a9675 100644 return; } + + diff --git a/projects/Rockchip/patches/linux/default/linux-1002-v4l2-rockchip.patch b/projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch similarity index 86% rename from projects/Rockchip/patches/linux/default/linux-1002-v4l2-rockchip.patch rename to projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch index b6e8d01e2c..c0f90d8482 100644 --- a/projects/Rockchip/patches/linux/default/linux-1002-v4l2-rockchip.patch +++ b/projects/Rockchip/patches/linux/default/linux-1001-v4l2-rockchip.patch @@ -10,10 +10,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 9492822c12ae..b49541f8ecf5 100644 +index d068383aeea8..5c03fdbd45ec 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1024,7 +1024,8 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) +@@ -986,7 +986,8 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) state = (status & RKVDEC_RDY_STA) ? VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; @@ -23,7 +23,7 @@ index 9492822c12ae..b49541f8ecf5 100644 if (cancel_delayed_work(&rkvdec->watchdog_work)) { struct rkvdec_ctx *ctx; -@@ -1045,7 +1046,8 @@ static void rkvdec_watchdog_func(struct work_struct *work) +@@ -1007,7 +1008,8 @@ static void rkvdec_watchdog_func(struct work_struct *work) ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); if (ctx) { dev_err(rkvdec->dev, "Frame processing timed out!\n"); @@ -46,10 +46,10 @@ Signed-off-by: Jonas Karlman 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index b49541f8ecf5..51e257a0233d 100644 +index 5c03fdbd45ec..ad5e02bbd8d0 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1145,9 +1145,9 @@ static int rkvdec_remove(struct platform_device *pdev) +@@ -1105,9 +1105,9 @@ static int rkvdec_remove(struct platform_device *pdev) { struct rkvdec_dev *rkvdec = platform_get_drvdata(pdev); @@ -77,7 +77,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index c115cd362a7f..d9a2fd9386e2 100644 +index c9a551dbd9bc..6ce11b736363 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -734,6 +734,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, @@ -131,7 +131,7 @@ Signed-off-by: Jonas Karlman 1 file changed, 64 insertions(+), 15 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index d9a2fd9386e2..d4f27ef7addd 100644 +index 6ce11b736363..9c3f08c94800 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -737,7 +737,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, @@ -247,58 +247,27 @@ This still need code cleanup and formatting Signed-off-by: Jonas Karlman --- - .../staging/media/hantro/hantro_g1_h264_dec.c | 17 +--- - drivers/staging/media/hantro/hantro_h264.c | 81 ++++++++++++++++--- - drivers/staging/media/hantro/hantro_hw.h | 2 + - 3 files changed, 74 insertions(+), 26 deletions(-) + drivers/staging/media/hantro/hantro_h264.c | 91 ++++++++++++++++------ + 1 file changed, 69 insertions(+), 22 deletions(-) -diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c -index 845bef73d218..869ee261a5db 100644 ---- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c -+++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c -@@ -130,25 +130,12 @@ static void set_ref(struct hantro_ctx *ctx) - struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; - const u8 *b0_reflist, *b1_reflist, *p_reflist; - struct hantro_dev *vpu = ctx->dev; -- u32 dpb_longterm = 0; -- u32 dpb_valid = 0; - int reg_num; - u32 reg; - int i; - -- /* -- * Set up bit maps of valid and long term DPBs. -- * NOTE: The bits are reversed, i.e. MSb is DPB 0. -- */ -- for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { -- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) -- dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); -- -- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) -- dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); -- } -- vdpu_write_relaxed(vpu, dpb_valid << 16, G1_REG_VALID_REF); -- vdpu_write_relaxed(vpu, dpb_longterm << 16, G1_REG_LT_REF); -+ vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF); -+ vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF); - - /* - * Set up reference frame picture numbers. diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c -index b1bdc00ac262..bc2af450a94c 100644 +index 0b4d2491be3b..7b56a68c176c 100644 --- a/drivers/staging/media/hantro/hantro_h264.c +++ b/drivers/staging/media/hantro/hantro_h264.c -@@ -227,17 +227,67 @@ static void prepare_table(struct hantro_ctx *ctx) +@@ -227,30 +227,67 @@ static void prepare_table(struct hantro_ctx *ctx) { const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; const struct v4l2_ctrl_h264_decode_params *dec_param = ctrls->decode; + const struct v4l2_ctrl_h264_sps *sps = ctrls->sps; struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu; const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; -+ u32 dpb_longterm = 0; -+ u32 dpb_valid = 0; + u32 dpb_longterm = 0; + u32 dpb_valid = 0; int i; +- for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { +- tbl->poc[i * 2] = dpb[i].top_field_order_cnt; +- tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt; + /* + * Set up bit maps of valid and long term DPBs. + * NOTE: The bits are reversed, i.e. MSb is DPB 0. @@ -315,7 +284,15 @@ index b1bdc00ac262..bc2af450a94c 100644 + if (dpb[i / 2].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) + dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE * 2 - 1 - i); + } -+ + +- /* +- * Set up bit maps of valid and long term DPBs. +- * NOTE: The bits are reversed, i.e. MSb is DPB 0. +- */ +- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) +- dpb_valid |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); +- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) +- dpb_longterm |= BIT(HANTRO_H264_DPB_SIZE - 1 - i); + ctx->h264_dec.dpb_valid = dpb_valid; + ctx->h264_dec.dpb_longterm = dpb_longterm; + } else { @@ -329,11 +306,13 @@ index b1bdc00ac262..bc2af450a94c 100644 + + ctx->h264_dec.dpb_valid = dpb_valid << 16; + ctx->h264_dec.dpb_longterm = dpb_longterm << 16; -+ } -+ - for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { -- tbl->poc[i * 2] = dpb[i].top_field_order_cnt; -- tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt; + } +- ctx->h264_dec.dpb_valid = dpb_valid << 16; +- ctx->h264_dec.dpb_longterm = dpb_longterm << 16; + +- tbl->poc[32] = dec_param->top_field_order_cnt; +- tbl->poc[33] = dec_param->bottom_field_order_cnt; ++ for (i = 0; i < HANTRO_H264_DPB_SIZE; ++i) { + if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) { + tbl->poc[i * 2] = dpb[i].top_field_order_cnt; + tbl->poc[i * 2 + 1] = dpb[i].bottom_field_order_cnt; @@ -341,10 +320,8 @@ index b1bdc00ac262..bc2af450a94c 100644 + tbl->poc[i * 2] = 0; + tbl->poc[i * 2 + 1] = 0; + } - } - -- tbl->poc[32] = dec_param->top_field_order_cnt; -- tbl->poc[33] = dec_param->bottom_field_order_cnt; ++ } ++ + if ((dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) || !(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD)) { + if ((dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)) + tbl->poc[32] = (dec_param->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) ? @@ -356,11 +333,11 @@ index b1bdc00ac262..bc2af450a94c 100644 + } else { + tbl->poc[32] = dec_param->top_field_order_cnt; + tbl->poc[33] = dec_param->bottom_field_order_cnt; -+ } ++ }; assemble_scaling_list(ctx); } -@@ -245,8 +295,7 @@ static void prepare_table(struct hantro_ctx *ctx) +@@ -258,8 +295,7 @@ static void prepare_table(struct hantro_ctx *ctx) static bool dpb_entry_match(const struct v4l2_h264_dpb_entry *a, const struct v4l2_h264_dpb_entry *b) { @@ -370,7 +347,7 @@ index b1bdc00ac262..bc2af450a94c 100644 } static void update_dpb(struct hantro_ctx *ctx) -@@ -260,13 +309,13 @@ static void update_dpb(struct hantro_ctx *ctx) +@@ -273,13 +309,13 @@ static void update_dpb(struct hantro_ctx *ctx) /* Disable all entries by default. */ for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++) @@ -386,7 +363,7 @@ index b1bdc00ac262..bc2af450a94c 100644 continue; /* -@@ -277,8 +326,7 @@ static void update_dpb(struct hantro_ctx *ctx) +@@ -290,8 +326,7 @@ static void update_dpb(struct hantro_ctx *ctx) struct v4l2_h264_dpb_entry *cdpb; cdpb = &ctx->h264_dec.dpb[j]; @@ -396,7 +373,7 @@ index b1bdc00ac262..bc2af450a94c 100644 continue; *cdpb = *ndpb; -@@ -314,7 +362,10 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, +@@ -327,7 +362,10 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, unsigned int dpb_idx) { struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; @@ -407,7 +384,7 @@ index b1bdc00ac262..bc2af450a94c 100644 if (dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) dma_addr = hantro_get_ref(ctx, dpb[dpb_idx].reference_ts); -@@ -332,7 +383,15 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, +@@ -345,7 +383,16 @@ dma_addr_t hantro_h264_get_ref_buf(struct hantro_ctx *ctx, dma_addr = hantro_get_dec_buf_addr(ctx, buf); } @@ -421,22 +398,10 @@ index b1bdc00ac262..bc2af450a94c 100644 + 0x1 : 0; + + return dma_addr | flags; ++ } - int hantro_h264_dec_prepare_run(struct hantro_ctx *ctx) -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index 219283a06f52..7e35140a4f22 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -90,6 +90,8 @@ struct hantro_h264_dec_hw_ctx { - struct v4l2_h264_dpb_entry dpb[HANTRO_H264_DPB_SIZE]; - struct hantro_h264_dec_reflists reflists; - struct hantro_h264_dec_ctrls ctrls; -+ u32 dpb_longterm; -+ u32 dpb_valid; - }; - - /** + u16 hantro_h264_get_ref_nbr(struct hantro_ctx *ctx, unsigned int dpb_idx) From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee @@ -449,7 +414,7 @@ Signed-off-by: Alex Bee 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_h264.c b/drivers/staging/media/hantro/hantro_h264.c -index bc2af450a94c..7bdefcc2fc77 100644 +index 7b56a68c176c..befa69d5c855 100644 --- a/drivers/staging/media/hantro/hantro_h264.c +++ b/drivers/staging/media/hantro/hantro_h264.c @@ -241,10 +241,10 @@ static void prepare_table(struct hantro_ctx *ctx) @@ -477,7 +442,7 @@ Signed-off-by: Alex Bee 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c -index d4f27ef7addd..627cd4efabef 100644 +index 9c3f08c94800..7238117b6cf4 100644 --- a/drivers/staging/media/rkvdec/rkvdec-h264.c +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c @@ -783,10 +783,10 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, @@ -512,32 +477,6 @@ index d4f27ef7addd..627cd4efabef 100644 set_ps_field(hw_rps, DPB_INFO(i, j), idx | (1 << 4)); -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 31 May 2020 18:22:01 +0200 -Subject: [PATCH] media: hantro: rk3288: increase max ACLK - -as per vendor source - -Signed-off-by: Alex Bee ---- - drivers/staging/media/hantro/rk3288_vpu_hw.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/rk3288_vpu_hw.c b/drivers/staging/media/hantro/rk3288_vpu_hw.c -index 7b299ee3e93d..23f793e73941 100644 ---- a/drivers/staging/media/hantro/rk3288_vpu_hw.c -+++ b/drivers/staging/media/hantro/rk3288_vpu_hw.c -@@ -13,7 +13,7 @@ - #include "hantro_g1_regs.h" - #include "hantro_h1_regs.h" - --#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000) -+#define RK3288_ACLK_MAX_FREQ (600 * 1000 * 1000) - - /* - * Supported formats. - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Randy Li Date: Sun, 6 Jan 2019 01:48:37 +0800 @@ -560,10 +499,10 @@ Signed-off-by: Randy Li create mode 100644 include/soc/rockchip/pm_domains.h diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c -index 54eb6cfc5d5b..727af107e6d3 100644 +index 0868b7d406fb..fddb4022c376 100644 --- a/drivers/soc/rockchip/pm_domains.c +++ b/drivers/soc/rockchip/pm_domains.c -@@ -196,6 +196,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, +@@ -204,6 +204,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, return 0; } @@ -652,10 +591,10 @@ Subject: [PATCH] WIP: media: rkvdec: implement reset controls 4 files changed, 87 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -index 8d35c327018b..dfafdb671798 100644 +index 089f11d21b25..3f4772c8d095 100644 --- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml +++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -@@ -43,6 +43,18 @@ properties: +@@ -51,6 +51,18 @@ properties: iommus: maxItems: 1 @@ -674,7 +613,7 @@ index 8d35c327018b..dfafdb671798 100644 required: - compatible - reg -@@ -50,6 +62,8 @@ required: +@@ -58,6 +70,8 @@ required: - clocks - clock-names - power-domains @@ -683,7 +622,7 @@ index 8d35c327018b..dfafdb671798 100644 additionalProperties: false -@@ -68,6 +82,11 @@ examples: +@@ -76,6 +90,11 @@ examples: clock-names = "axi", "ahb", "cabac", "core"; power-domains = <&power RK3399_PD_VDU>; iommus = <&vdec_mmu>; @@ -712,7 +651,7 @@ index 15b9bee92016..3acc914888f6 100644 #define RKVDEC_REG_SYSCTRL 0x008 #define RKVDEC_IN_ENDIAN BIT(0) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 51e257a0233d..c05ba31ed656 100644 +index ad5e02bbd8d0..6abce36eee7f 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -10,12 +10,15 @@ @@ -731,7 +670,7 @@ index 51e257a0233d..c05ba31ed656 100644 #include #include #include -@@ -725,6 +728,11 @@ static void rkvdec_job_finish(struct rkvdec_ctx *ctx, +@@ -687,6 +690,11 @@ static void rkvdec_job_finish(struct rkvdec_ctx *ctx, pm_runtime_mark_last_busy(rkvdec->dev); pm_runtime_put_autosuspend(rkvdec->dev); @@ -743,7 +682,7 @@ index 51e257a0233d..c05ba31ed656 100644 rkvdec_job_finish_no_pm(ctx, result); } -@@ -762,6 +770,33 @@ static void rkvdec_device_run(void *priv) +@@ -724,6 +732,33 @@ static void rkvdec_device_run(void *priv) if (WARN_ON(!desc)) return; @@ -775,9 +714,9 @@ index 51e257a0233d..c05ba31ed656 100644 + pm_runtime_suspend(rkvdec->dev); + } - ret = pm_runtime_get_sync(rkvdec->dev); + ret = pm_runtime_resume_and_get(rkvdec->dev); if (ret < 0) { -@@ -1029,6 +1064,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) +@@ -991,6 +1026,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) if (cancel_delayed_work(&rkvdec->watchdog_work)) { struct rkvdec_ctx *ctx; @@ -789,7 +728,7 @@ index 51e257a0233d..c05ba31ed656 100644 ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); rkvdec_job_finish(ctx, state); } -@@ -1046,6 +1086,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) +@@ -1008,6 +1048,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); if (ctx) { dev_err(rkvdec->dev, "Frame processing timed out!\n"); @@ -797,7 +736,7 @@ index 51e257a0233d..c05ba31ed656 100644 writel(RKVDEC_CONFIG_DEC_CLK_GATE_E | RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT); writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL); -@@ -1125,6 +1166,18 @@ static int rkvdec_probe(struct platform_device *pdev) +@@ -1085,6 +1126,18 @@ static int rkvdec_probe(struct platform_device *pdev) return ret; } @@ -817,7 +756,7 @@ index 51e257a0233d..c05ba31ed656 100644 pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_enable(&pdev->dev); diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index e95c52e3168a..c14cd2571bfc 100644 +index 7b6f44ee8a1a..fa24bcb6ff42 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h @@ -11,10 +11,11 @@ @@ -846,7 +785,7 @@ index e95c52e3168a..c14cd2571bfc 100644 struct rkvdec_ctx; struct rkvdec_ctrl_desc { -@@ -91,6 +98,8 @@ struct rkvdec_dev { +@@ -90,6 +97,8 @@ struct rkvdec_dev { void __iomem *regs; struct mutex vdev_lock; /* serializes ioctls */ struct delayed_work watchdog_work; @@ -866,11 +805,11 @@ Subject: [PATCH] WIP: arm64: dts: add resets to vdec for RK3399 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index ea1ef6c7455a..92e3f6da0297 100644 +index 52a748053a97..2c7b263a82cd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1022,7 +1022,10 @@ pd_vcodec@RK3399_PD_VCODEC { - pd_vdu@RK3399_PD_VDU { +@@ -993,7 +993,10 @@ power-domain@RK3399_PD_VCODEC { + power-domain@RK3399_PD_VDU { reg = ; clocks = <&cru ACLK_VDU>, - <&cru HCLK_VDU>; @@ -880,8 +819,8 @@ index ea1ef6c7455a..92e3f6da0297 100644 + pm_qos = <&qos_video_m1_r>, <&qos_video_m1_w>; - }; -@@ -1283,6 +1286,11 @@ vdec: video-codec@ff660000 { + #power-domain-cells = <0>; +@@ -1266,6 +1269,11 @@ vdec: video-codec@ff660000 { clock-names = "axi", "ahb", "cabac", "core"; iommus = <&vdec_mmu>; power-domains = <&power RK3399_PD_VDU>; @@ -905,10 +844,10 @@ Signed-off-by: Alex Bee 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 92e3f6da0297..03c6737ca0ea 100644 +index 2c7b263a82cd..ec3561d147d5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1279,7 +1279,7 @@ vpu_mmu: iommu@ff650800 { +@@ -1262,7 +1262,7 @@ vpu_mmu: iommu@ff650800 { vdec: video-codec@ff660000 { compatible = "rockchip,rk3399-vdec"; @@ -925,42 +864,40 @@ Subject: [PATCH] arm64: dts: rockchip: add rkvdec node for RK3328 Signed-off-by: Alex Bee --- - .../bindings/media/rockchip,vdec.yaml | 5 ++++ - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 26 ++++++++++++++++++- - 2 files changed, 30 insertions(+), 1 deletion(-) + .../bindings/media/rockchip,vdec.yaml | 3 +++ + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 ++++++++++++++++++- + 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -index dfafdb671798..360b750e5514 100644 +index 3f4772c8d095..21a78372dae6 100644 --- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml +++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -@@ -16,6 +16,11 @@ description: |- - properties: - compatible: - const: rockchip,rk3399-vdec -+ - items: -+ - enum: -+ - rockchip,rk3328-vdec -+ - const: rockchip,rk3399-vdec -+ +@@ -20,6 +20,9 @@ properties: + - items: + - const: rockchip,rk3228-vdec + - const: rockchip,rk3399-vdec ++ - items: ++ - const: rockchip,rk3328-vdec ++ - const: rockchip,rk3399-vdec reg: maxItems: 1 diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 31c48c38c955..bd0ec27cf49b 100644 +index 9c10b6e3b9bc..23021373e15b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -326,6 +326,10 @@ pd_hevc@RK3328_PD_HEVC { +@@ -306,6 +306,10 @@ power-domain@RK3328_PD_HEVC { }; - pd_video@RK3328_PD_VIDEO { + power-domain@RK3328_PD_VIDEO { reg = ; + clocks = <&cru ACLK_RKVDEC>, + <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + #power-domain-cells = <0>; }; - pd_vpu@RK3328_PD_VPU { - reg = ; -@@ -670,6 +674,26 @@ vpu_mmu: iommu@ff350800 { + power-domain@RK3328_PD_VPU { +@@ -660,6 +664,25 @@ vpu_mmu: iommu@ff350800 { power-domains = <&power RK3328_PD_VPU>; }; @@ -968,7 +905,6 @@ index 31c48c38c955..bd0ec27cf49b 100644 + compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; + reg = <0x0 0xff360000 0x0 0x480>; + interrupts = ; -+ interrupt-names = "vdpu"; + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + assigned-clock-rates = <400000000>, <400000000>, <300000000>; @@ -987,7 +923,7 @@ index 31c48c38c955..bd0ec27cf49b 100644 rkvdec_mmu: iommu@ff360480 { compatible = "rockchip,iommu"; reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; -@@ -678,7 +702,7 @@ rkvdec_mmu: iommu@ff360480 { +@@ -667,7 +690,7 @@ rkvdec_mmu: iommu@ff360480 { clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; @@ -1008,10 +944,10 @@ Signed-off-by: Alex Bee 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index c05ba31ed656..4111155d62f4 100644 +index 6abce36eee7f..fbaf0303f7c2 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1134,10 +1134,12 @@ static int rkvdec_probe(struct platform_device *pdev) +@@ -1096,10 +1096,12 @@ static int rkvdec_probe(struct platform_device *pdev) return ret; /* @@ -1027,3 +963,61 @@ index c05ba31ed656..4111155d62f4 100644 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); rkvdec->regs = devm_ioremap_resource(&pdev->dev, res); + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 21 Aug 2021 16:12:36 +0200 +Subject: [PATCH] media: hantro: rockchip: Increase RK3288's max ACLK + +Required to proper decode H.264@4K + +Signed-off-by: Alex Bee +--- + drivers/staging/media/hantro/rockchip_vpu_hw.c | 14 +++++++++++--- + 1 file changed, 11 insertions(+), 3 deletions(-) + +diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c +index d4f52957cc53..3d98e2251ea5 100644 +--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c ++++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c +@@ -15,7 +15,8 @@ + #include "rockchip_vpu2_regs.h" + + #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000) +-#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000) ++#define RK3288_ACLK_MAX_FREQ (600 * 1000 * 1000) ++#define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000) + + /* + * Supported formats. +@@ -272,13 +273,20 @@ static int rk3066_vpu_hw_init(struct hantro_dev *vpu) + return 0; + } + +-static int rockchip_vpu_hw_init(struct hantro_dev *vpu) ++static int rk3288_vpu_hw_init(struct hantro_dev *vpu) + { + /* Bump ACLK to max. possible freq. to improve performance. */ + clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ); + return 0; + } + ++static int rockchip_vpu_hw_init(struct hantro_dev *vpu) ++{ ++ /* Bump ACLK to max. possible freq. to improve performance. */ ++ clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ); ++ return 0; ++} ++ + static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx) + { + struct hantro_dev *vpu = ctx->dev; +@@ -511,7 +519,7 @@ const struct hantro_variant rk3288_vpu_variant = { + .codec_ops = rk3288_vpu_codec_ops, + .irqs = rockchip_vpu1_irqs, + .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs), +- .init = rockchip_vpu_hw_init, ++ .init = rk3288_vpu_hw_init, + .clk_names = rockchip_vpu_clk_names, + .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) + }; diff --git a/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch b/projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch similarity index 66% rename from projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch rename to projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch index dbf18c3562..474a2b40bc 100644 --- a/projects/Rockchip/patches/linux/default/linux-1003-for-libreelec.patch +++ b/projects/Rockchip/patches/linux/default/linux-1002-for-libreelec.patch @@ -10,25 +10,26 @@ other SoC components, we have to make sure voltage is never lower then Signed-off-by: Alex Bee --- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 33 ++++++++++++++++++++++++ - 1 file changed, 33 insertions(+) + arch/arm64/boot/dts/rockchip/rk3328.dtsi | 34 ++++++++++++++++++++++++ + 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index bd0ec27cf49b..21e32ddb21a0 100644 +index 23021373e15b..ca03c8ed9708 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -321,6 +321,10 @@ power: power-controller { +@@ -300,6 +300,11 @@ power: power-controller { #address-cells = <1>; #size-cells = <0>; + power-domain@RK3328_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; ++ #power-domain-cells = <0>; + }; power-domain@RK3328_PD_HEVC { reg = ; - }; -@@ -546,6 +550,11 @@ map0 { + #power-domain-cells = <0>; +@@ -539,6 +544,11 @@ map0 { <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; contribution = <4096>; }; @@ -40,7 +41,7 @@ index bd0ec27cf49b..21e32ddb21a0 100644 }; }; -@@ -627,7 +636,31 @@ gpu: gpu@ff300000 { +@@ -620,7 +630,31 @@ gpu: gpu@ff300000 { "ppmmu1"; clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; clock-names = "bus", "core"; @@ -73,42 +74,6 @@ index bd0ec27cf49b..21e32ddb21a0 100644 h265e_mmu: iommu@ff330200 { -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Mon, 10 Feb 2020 19:22:41 +0100 -Subject: [PATCH] arm64: dts: rockchip: add sdmmc ext node for RK3328 - -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 21e32ddb21a0..18d663aacd07 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -1109,6 +1109,20 @@ usbdrd_dwc3: dwc3@ff600000 { - }; - }; - -+ sdmmc_ext: dwmmc@ff5f0000 { -+ compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; -+ reg = <0x0 0xff5f0000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, -+ <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; -+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; -+ fifo-depth = <0x100>; -+ max-frequency = <150000000>; -+ resets = <&cru SRST_SDMMCEXT>; -+ reset-names = "reset"; -+ status = "disabled"; -+ }; -+ - gic: interrupt-controller@ff811000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Tue, 2 Feb 2021 17:22:21 +0200 @@ -183,10 +148,10 @@ index 9c1e38c54eae..ee332fc9cf1f 100644 simple-audio-card,codec { diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 03c6737ca0ea..9c2ac03c154b 100644 +index ec3561d147d5..b2ed593a229c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1782,7 +1782,7 @@ hdmi_sound: hdmi-sound { +@@ -1807,7 +1807,7 @@ hdmi_sound: hdmi-sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; simple-audio-card,mclk-fs = <256>; @@ -207,10 +172,10 @@ Signed-off-by: Alex Bee 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c -index 69c2c079d803..65fbffc4cbc7 100644 +index d62fb1a3c916..e46165bed006 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c -@@ -1093,7 +1093,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, +@@ -1073,7 +1073,7 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, ret = obj->funcs->mmap(obj, vma); if (ret) goto err_drm_gem_object_put; @@ -219,6 +184,7 @@ index 69c2c079d803..65fbffc4cbc7 100644 } else { if (!vma->vm_ops) { ret = -EINVAL; + From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sun, 25 Mar 2018 22:17:06 +0200 @@ -229,10 +195,10 @@ Subject: [PATCH] ASoC: hdmi-codec: fix channel allocation 1 file changed, 52 insertions(+), 61 deletions(-) diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c -index 403d4c6a49a8..7505c3eee4c1 100644 +index b61f980cabdc..3ad50ae8c93d 100644 --- a/sound/soc/codecs/hdmi-codec.c +++ b/sound/soc/codecs/hdmi-codec.c -@@ -195,78 +195,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = { +@@ -194,78 +194,69 @@ static const struct snd_pcm_chmap_elem hdmi_codec_8ch_chmaps[] = { */ static const struct hdmi_codec_cea_spk_alloc hdmi_codec_channel_alloc[] = { { .ca_id = 0x00, .n_ch = 2, @@ -364,63 +330,6 @@ index 403d4c6a49a8..7505c3eee4c1 100644 struct hdmi_codec_priv { -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 27 Feb 2021 17:41:48 +0100 -Subject: [PATCH] arm64: dts: rockchip: fix GPU register width and supplies for - RK3328 - -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 4 ++++ - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +- - 3 files changed, 9 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -index 3ac876c08d61..8607514437f5 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -161,6 +161,10 @@ &gmac2io { - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_logic>; -+}; -+ - &hdmi { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -index 89fde87f7650..bd62349a9390 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts -@@ -157,6 +157,10 @@ &gmac2io { - status = "okay"; - }; - -+&gpu { -+ mali-supply = <&vdd_logic>; -+}; -+ - &hdmi { - status = "okay"; - }; -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 18d663aacd07..0e5e492db9c7 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -619,7 +619,7 @@ saradc: adc@ff280000 { - - gpu: gpu@ff300000 { - compatible = "rockchip,rk3328-mali", "arm,mali-450"; -- reg = <0x0 0xff300000 0x0 0x40000>; -+ reg = <0x0 0xff300000 0x0 0x30000>; - interrupts = , - , - , - From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sun, 2 May 2021 20:44:21 +0200 @@ -434,10 +343,10 @@ Signed-off-by: Alex Bee 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -index 58097245994a..c7c515c6c5cb 100644 +index 83db4ca67334..06d2a1e3e340 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi -@@ -247,8 +247,8 @@ &gmac { +@@ -289,8 +289,8 @@ &gmac { snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; snps,reset-active-low; snps,reset-delays-us = <0 10000 50000>; @@ -452,20 +361,18 @@ index 58097245994a..c7c515c6c5cb 100644 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sat, 27 Feb 2021 17:52:02 +0100 -Subject: [PATCH] arm64: dts: rockchip: add SPDIF nodes for RK3328 A1/ROC CC - boards +Subject: [PATCH] arm64: dts: rockchip: add SPDIF nodes for RK3328 A1 board Signed-off-by: Alex Bee --- - arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 23 +++++++++++++++++++ - .../arm64/boot/dts/rockchip/rk3328-roc-cc.dts | 23 +++++++++++++++++++ - 2 files changed, 46 insertions(+) + arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 23 ++++++++++++++++++++++ + 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -index 4013f16bb368..1bb3f4a6e496 100644 +index de2d3e88e27f..68b74ed080f3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -@@ -52,6 +52,24 @@ ir-receiver { +@@ -57,6 +57,24 @@ ir-receiver { gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; linux,rc-map-name = "rc-beelink-gs1"; }; @@ -490,7 +397,7 @@ index 4013f16bb368..1bb3f4a6e496 100644 }; &analog_sound { -@@ -319,6 +337,11 @@ &sdmmc { +@@ -324,6 +342,11 @@ &sdmmc { status = "okay"; }; @@ -502,47 +409,6 @@ index 4013f16bb368..1bb3f4a6e496 100644 &tsadc { rockchip,hw-tshut-mode = <0>; rockchip,hw-tshut-polarity = <0>; -diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -index 8607514437f5..6ca08854aef3 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -102,6 +102,24 @@ user_led: led-1 { - mode = <0x05>; - }; - }; -+ -+ spdif_sound: spdif-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "SPDIF"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&spdif>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&spdif_dit>; -+ }; -+ }; -+ -+ spdif_dit: spdif-dit { -+ compatible = "linux,spdif-dit"; -+ #sound-dai-cells = <0>; -+ }; - }; - - &analog_sound { -@@ -337,6 +355,11 @@ &sdmmc { - status = "okay"; - }; - -+&spdif { -+ pinctrl-0 = <&spdifm0_tx>; -+ status = "okay"; -+}; -+ - &tsadc { - status = "okay"; - }; From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee @@ -555,10 +421,10 @@ Signed-off-by: Alex Bee 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -index 6ca08854aef3..fb21ad1324bc 100644 +index aa22a0c22265..a78fbddd21df 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts -@@ -83,6 +83,13 @@ vcc_phy: vcc-phy-regulator { +@@ -88,6 +88,13 @@ vcc_phy: vcc-phy-regulator { regulator-boot-on; }; @@ -572,7 +438,7 @@ index 6ca08854aef3..fb21ad1324bc 100644 leds { compatible = "gpio-leds"; -@@ -325,6 +332,13 @@ &io_domains { +@@ -308,6 +315,13 @@ &io_domains { }; &pinctrl { @@ -620,10 +486,10 @@ Subject: [PATCH] HACK: arm64: dts: enable FE phy for Beelink A1 also 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -index 1bb3f4a6e496..99f28dac0791 100644 +index 68b74ed080f3..6736b5dc53e4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts -@@ -142,6 +142,14 @@ rtl8211f: ethernet-phy@0 { +@@ -147,6 +147,14 @@ rtl8211f: ethernet-phy@0 { }; }; @@ -713,10 +579,10 @@ Signed-off-by: Alex Bee 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index 9c2ac03c154b..b1c7ee80d255 100644 +index b2ed593a229c..27938ff0d208 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1390,7 +1390,7 @@ cru: clock-controller@ff760000 { +@@ -1393,7 +1393,7 @@ cru: clock-controller@ff760000 { <1000000000>, <150000000>, <75000000>, <37500000>, @@ -728,157 +594,52 @@ index 9c2ac03c154b..b1c7ee80d255 100644 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee -Date: Wed, 5 May 2021 22:09:44 +0200 -Subject: [PATCH] arm64: dts: rockchip: limit emmc clockrate to 150 MHz for - Rock Pi4 board - -as per https://github.com/radxa/kernel/commit/db9dfc2cdd25103c553845d24967e4cb31852b61 +Date: Sat, 21 Aug 2021 17:04:46 +0200 +Subject: [PATCH] arm64: dts: rockchip: Enable USB3 for rk3328 Beelink A1 Signed-off-by: Alex Bee --- - arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 1 + - 1 file changed, 1 insertion(+) + arch/arm64/boot/dts/rockchip/rk3328-a1.dts | 5 +++++ + 1 file changed, 5 insertions(+) -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -index fb7599f07af4..155f22b53103 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -593,6 +593,7 @@ &sdmmc { +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +index 6736b5dc53e4..9000fae2a5ee 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +@@ -388,6 +388,11 @@ &usb_host0_ehci { + status = "okay"; + }; - &sdhci { - bus-width = <8>; -+ max-frequency = <150000000>; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; ++&usbdrd3 { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ + &vop { + status = "okay"; + }; From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Rudi Heitbaum -Date: Tue, 1 Jun 2021 19:42:31 +0200 -Subject: [PATCH] arm64: dts: rockchip: dts additions for Rock Pi N10 +From: Alex Bee +Date: Sat, 21 Aug 2021 14:03:25 +0200 +Subject: [PATCH] HACK: media: hantro: rockchip: disable H264 for RK3328 +Signed-off-by: Alex Bee --- - .../dts/rockchip/rk3399pro-rock-pi-n10.dts | 4 + - .../dts/rockchip/rk3399pro-vmarc-som.dtsi | 83 +++++++++++++++++++ - 2 files changed, 87 insertions(+) + drivers/staging/media/hantro/rockchip_vpu_hw.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) -diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts -index 369de5dc0ebd..48ac0cfa93c0 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dts -@@ -20,3 +20,7 @@ chosen { - stdout-path = "serial2:1500000n8"; - }; - }; -+ -+&uart2 { -+ status = "okay"; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi -index 7257494d2831..9e2994e27d05 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi -@@ -57,6 +57,22 @@ &hdmi { - pinctrl-0 = <&hdmi_cec>; - }; - -+&hdmi_sound { -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ assigned-clocks = <&cru ACLK_GPU>; -+ assigned-clock-rates = <200000000>; -+ status = "okay"; -+ /delete-property/ operating-points-v2; -+}; -+ -+&vopl { -+ status = "disabled"; -+}; -+ - &i2c0 { - clock-frequency = <400000>; - i2c-scl-falling-time-ns = <30>; -@@ -280,6 +296,50 @@ regulator-state-mem { - }; - }; - }; -+ -+ vdd_cpu_b: tcs4525@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ vin-supply = <&vcc5v0_sys>; -+ regulator-compatible = "fan53555-reg"; -+ pinctrl-0 = <&vsel1_gpio>; -+ vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <2300>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-state = <3>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: tcs4526@10 { -+ compatible = "tcs,tcs4526"; -+ reg = <0x10>; -+ vin-supply = <&vcc5v0_sys>; -+ regulator-compatible = "fan53555-reg"; -+ pinctrl-0 = <&vsel2_gpio>; -+ vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; -+ regulator-name = "vdd_gpu"; -+ regulator-min-microvolt = <735000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-ramp-delay = <1000>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-state = <3>; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+}; -+ -+&i2s2 { -+ status = "okay"; - }; - - &i2c1 { -@@ -351,6 +411,29 @@ pmic { - pmic_int_l: pmic-int-l { - rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>; - }; -+ vsel1_gpio: vsel1-gpio { -+ rockchip,pins = -+ <1 RK_PC1 0 &pcfg_pull_down>; -+ }; -+ vsel2_gpio: vsel2-gpio { -+ rockchip,pins = -+ <1 RK_PB6 0 &pcfg_pull_down>; -+ }; -+ -+ soc_slppin_gpio: soc-slppin-gpio { -+ rockchip,pins = -+ <1 RK_PA5 0 &pcfg_output_low>; -+ }; -+ -+ soc_slppin_slp: soc-slppin-slp { -+ rockchip,pins = -+ <1 RK_PA5 1 &pcfg_pull_down>; -+ }; -+ -+ soc_slppin_rst: soc-slppin-rst { -+ rockchip,pins = -+ <1 RK_PA5 2 &pcfg_pull_none>; -+ }; - }; - - sdio-pwrseq { +diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c +index 3d98e2251ea5..b201700ccc8a 100644 +--- a/drivers/staging/media/hantro/rockchip_vpu_hw.c ++++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c +@@ -530,8 +530,7 @@ const struct hantro_variant rk3328_vpu_variant = { + .dec_offset = 0x400, + .dec_fmts = rk3399_vpu_dec_fmts, + .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts), +- .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | +- HANTRO_H264_DECODER, ++ .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER, + .codec_ops = rk3399_vpu_codec_ops, + .irqs = rockchip_vdpu2_irqs, + .num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs), diff --git a/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch b/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch index 3663de8756..0c30dd7bad 100644 --- a/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch +++ b/projects/Rockchip/patches/linux/default/linux-2000-v4l-wip-rkvdec-vp9.patch @@ -10,20 +10,21 @@ Signed-off-by: Boris Brezillon Signed-off-by: Ezequiel Garcia Signed-off-by: Adrian Ratiu --- - .../userspace-api/media/v4l/biblio.rst | 10 + - .../media/v4l/ext-ctrls-codec.rst | 550 ++++++++++++++++++ - drivers/media/v4l2-core/v4l2-ctrls.c | 239 ++++++++ - drivers/media/v4l2-core/v4l2-ioctl.c | 1 + - include/media/v4l2-ctrls.h | 5 + - include/media/vp9-ctrls.h | 486 ++++++++++++++++ - 6 files changed, 1291 insertions(+) + .../userspace-api/media/v4l/biblio.rst | 10 + + .../media/v4l/ext-ctrls-codec.rst | 1100 +++++++++++++++++ + drivers/media/v4l2-core/v4l2-ctrls-core.c | 225 ++++ + drivers/media/v4l2-core/v4l2-ctrls-defs.c | 14 + + drivers/media/v4l2-core/v4l2-ioctl.c | 1 + + include/media/v4l2-ctrls.h | 5 + + include/media/vp9-ctrls.h | 486 ++++++++ + 7 files changed, 1841 insertions(+) create mode 100644 include/media/vp9-ctrls.h diff --git a/Documentation/userspace-api/media/v4l/biblio.rst b/Documentation/userspace-api/media/v4l/biblio.rst -index 7869b6f6ff72..6b4a83b053f5 100644 +index 7b8e6738ff9e..9cd18c153d19 100644 --- a/Documentation/userspace-api/media/v4l/biblio.rst +++ b/Documentation/userspace-api/media/v4l/biblio.rst -@@ -407,3 +407,13 @@ VP8 +@@ -417,3 +417,13 @@ VP8 :title: RFC 6386: "VP8 Data Format and Decoding Guide" :author: J. Bankoski et al. @@ -38,11 +39,11 @@ index 7869b6f6ff72..6b4a83b053f5 100644 + +:author: Adrian Grange (Google), Peter de Rivaz (Argon Design), Jonathan Hunt (Argon Design) diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -index ce728c757eaf..456488f2b5ca 100644 +index 8c6e2a11ed95..5dd4afc5f1fe 100644 --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -@@ -2730,6 +2730,556 @@ enum v4l2_mpeg_video_h264_hierarchical_coding_type - - - ``padding[3]`` +@@ -3106,6 +3106,556 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - + - ``padding[2]`` - Applications and drivers must set this to zero. +.. _v4l2-mpeg-vp9: @@ -598,41 +599,570 @@ index ce728c757eaf..456488f2b5ca 100644 .. raw:: latex \normalsize -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 41f8410d08d6..7ed11f296008 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -971,6 +971,11 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: return "VP9 Profile"; - case V4L2_CID_MPEG_VIDEO_VP9_LEVEL: return "VP9 Level"; - case V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER: return "VP8 Frame Header"; -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS: return "VP9 Frame Decode Parameters"; -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(0): return "VP9 Frame Context 0"; -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(1): return "VP9 Frame Context 1"; -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(2): return "VP9 Frame Context 2"; -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(3): return "VP9 Frame Context 3"; +@@ -3157,6 +3707,556 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - + - ``padding[6]`` + - Applications and drivers must set this to zero. - /* HEVC controls */ - case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: return "HEVC I-Frame QP Value"; -@@ -1452,6 +1457,15 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER: - *type = V4L2_CTRL_TYPE_VP8_FRAME_HEADER; - break; -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS: -+ *type = V4L2_CTRL_TYPE_VP9_FRAME_DECODE_PARAMS; -+ break; -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(0): -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(1): -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(2): -+ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(3): -+ *type = V4L2_CTRL_TYPE_VP9_FRAME_CONTEXT; -+ break; - case V4L2_CID_MPEG_VIDEO_HEVC_SPS: - *type = V4L2_CTRL_TYPE_HEVC_SPS; - break; -@@ -1754,6 +1768,219 @@ static void std_log(const struct v4l2_ctrl *ctrl) - 0; \ - }) ++.. _v4l2-mpeg-vp9: ++ ++``V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(0..3) (struct)`` ++ Stores VP9 probabilities attached to a specific frame context. The VP9 ++ specification allows using a maximum of 4 contexts. Each frame being ++ decoded refers to one of those context. See section '7.1.2 Refresh ++ probs semantics' section of :ref:`vp9` for more details about these ++ contexts. ++ ++ This control is bi-directional: ++ ++ * all 4 contexts must be initialized by userspace just after the ++ stream is started and before the first decoding request is submitted. ++ * the referenced context might be read by the kernel when a decoding ++ request is submitted, and will be updated after the decoder is done ++ decoding the frame if the `V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX` flag ++ is set. ++ * contexts will be read back by user space before each decoding request ++ to retrieve the updated probabilities. ++ * userspace will re-initialize the context to their default values when ++ a reset context is required. ++ ++ .. note:: ++ ++ This compound control is not yet part of the public kernel API and ++ it is expected to change. ++ ++.. c:type:: v4l2_ctrl_vp9_frame_ctx ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{5.8cm}|p{4.8cm}|p{6.6cm}| ++ ++.. flat-table:: struct v4l2_ctrl_vp9_frame_ctx ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - struct :c:type:`v4l2_vp9_probabilities` ++ - ``probs`` ++ - Structure with VP9 probabilities attached to the context. ++ ++.. c:type:: v4l2_vp9_probabilities ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: struct v4l2_vp9_probabilities ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``tx8[2][1]`` ++ - TX 8x8 probabilities. ++ * - __u8 ++ - ``tx16[2][2]`` ++ - TX 16x16 probabilities. ++ * - __u8 ++ - ``tx32[2][3]`` ++ - TX 32x32 probabilities. ++ * - __u8 ++ - ``coef[4][2][2][6][6][3]`` ++ - Coefficient probabilities. ++ * - __u8 ++ - ``skip[3]`` ++ - Skip probabilities. ++ * - __u8 ++ - ``inter_mode[7][3]`` ++ - Inter prediction mode probabilities. ++ * - __u8 ++ - ``interp_filter[4][2]`` ++ - Interpolation filter probabilities. ++ * - __u8 ++ - ``is_inter[4]`` ++ - Is inter-block probabilities. ++ * - __u8 ++ - ``comp_mode[5]`` ++ - Compound prediction mode probabilities. ++ * - __u8 ++ - ``single_ref[5][2]`` ++ - Single reference probabilities. ++ * - __u8 ++ - ``comp_mode[5]`` ++ - Compound reference probabilities. ++ * - __u8 ++ - ``y_mode[4][9]`` ++ - Y prediction mode probabilities. ++ * - __u8 ++ - ``uv_mode[10][9]`` ++ - UV prediction mode probabilities. ++ * - __u8 ++ - ``partition[16][3]`` ++ - Partition probabilities. ++ * - __u8 ++ - ``mv.joint[3]`` ++ - Motion vector joint probabilities. ++ * - __u8 ++ - ``mv.sign[2]`` ++ - Motion vector sign probabilities. ++ * - __u8 ++ - ``mv.class[2][10]`` ++ - Motion vector class probabilities. ++ * - __u8 ++ - ``mv.class0_bit[2]`` ++ - Motion vector class0 bit probabilities. ++ * - __u8 ++ - ``mv.bits[2][10]`` ++ - Motion vector bits probabilities. ++ * - __u8 ++ - ``mv.class0_fr[2][2][3]`` ++ - Motion vector class0 fractional bit probabilities. ++ * - __u8 ++ - ``mv.fr[2][3]`` ++ - Motion vector fractional bit probabilities. ++ * - __u8 ++ - ``mv.class0_hp[2]`` ++ - Motion vector class0 high precision fractional bit probabilities. ++ * - __u8 ++ - ``mv.hp[2]`` ++ - Motion vector high precision fractional bit probabilities. ++ ++``V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS (struct)`` ++ Specifies the frame parameters for the associated VP9 frame decode request. ++ This includes the necessary parameters for configuring a stateless hardware ++ decoding pipeline for VP9. The bitstream parameters are defined according ++ to :ref:`vp9`. ++ ++ .. note:: ++ ++ This compound control is not yet part of the public kernel API and ++ it is expected to change. ++ ++.. c:type:: v4l2_ctrl_vp9_frame_decode_params ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: struct v4l2_ctrl_vp9_frame_decode_params ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u32 ++ - ``flags`` ++ - Combination of V4L2_VP9_FRAME_FLAG_* flags. See ++ :c:type:`v4l2_vp9_frame_flags`. ++ * - __u16 ++ - ``compressed_header_size`` ++ - Compressed header size in bytes. ++ * - __u16 ++ - ``uncompressed_header_size`` ++ - Uncompressed header size in bytes. ++ * - __u8 ++ - ``profile`` ++ - VP9 profile. Can be 0, 1, 2 or 3. ++ * - __u8 ++ - ``reset_frame_context`` ++ - Frame context that should be used/updated when decoding the frame. ++ * - __u8 ++ - ``bit_depth`` ++ - Component depth in bits. Must be 8 for profile 0 and 1. Must 10 or 12 ++ for profile 2 and 3. ++ * - __u8 ++ - ``interpolation_filter`` ++ - Specifies the filter selection used for performing inter prediction. See ++ :c:type:`v4l2_vp9_interpolation_filter`. ++ * - __u8 ++ - ``tile_cols_log2`` ++ - Specifies the base 2 logarithm of the width of each tile (where the ++ width is measured in units of 8x8 blocks). Shall be less than or equal ++ to 6. ++ * - __u8 ++ - ``tile_rows_log2`` ++ - Specifies the base 2 logarithm of the height of each tile (where the ++ height is measured in units of 8x8 blocks) ++ * - __u8 ++ - ``tx_mode`` ++ - Specifies the TX mode. See :c:type:`v4l2_vp9_tx_mode`. ++ * - __u8 ++ - ``reference_mode`` ++ - Specifies the type of inter prediction to be used. See ++ :c:type:`v4l2_vp9_reference_mode`. ++ * - __u8 ++ - ``padding[7]`` ++ - Needed to make this struct 64 bit aligned. Shall be filled with zeroes. ++ * - __u16 ++ - ``frame_width_minus_1`` ++ - Add 1 to get the frame width expressed in pixels. ++ * - __u16 ++ - ``frame_height_minus_1`` ++ - Add 1 to get the frame height expressed in pixels. ++ * - __u16 ++ - ``frame_width_minus_1`` ++ - Add 1 to get the expected render width expressed in pixels. This is ++ not used during the decoding process but might be used by HW scalers to ++ prepare a frame that's ready for scanout. ++ * - __u16 ++ - frame_height_minus_1 ++ - Add 1 to get the expected render height expressed in pixels. This is ++ not used during the decoding process but might be used by HW scalers to ++ prepare a frame that's ready for scanout. ++ * - __u64 ++ - ``refs[3]`` ++ - Array of reference frame timestamps. ++ * - struct :c:type:`v4l2_vp9_loop_filter` ++ - ``lf`` ++ - Loop filter parameters. See struct :c:type:`v4l2_vp9_loop_filter`. ++ * - struct :c:type:`v4l2_vp9_quantization` ++ - ``quant`` ++ - Quantization parameters. See :c:type:`v4l2_vp9_quantization`. ++ * - struct :c:type:`v4l2_vp9_segmentation` ++ - ``seg`` ++ - Segmentation parameters. See :c:type:`v4l2_vp9_segmentation`. ++ * - struct :c:type:`v4l2_vp9_probabilities` ++ - ``probs`` ++ - Probabilities. See :c:type:`v4l2_vp9_probabilities`. ++ ++.. c:type:: v4l2_vp9_frame_flags ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_frame_flags ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_FRAME_FLAG_KEY_FRAME`` ++ - The frame is a key frame. ++ * - ``V4L2_VP9_FRAME_FLAG_SHOW_FRAME`` ++ - The frame should be displayed. ++ * - ``V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT`` ++ - The decoding should be error resilient. ++ * - ``V4L2_VP9_FRAME_FLAG_INTRA_ONLY`` ++ - The frame does not reference other frames. ++ * - ``V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV`` ++ - the frame might can high precision motion vectors. ++ * - ``V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX`` ++ - Frame context should be updated after decoding. ++ * - ``V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE`` ++ - Parallel decoding is used. ++ * - ``V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING`` ++ - Vertical subsampling is enabled. ++ * - ``V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING`` ++ - Horizontal subsampling is enabled. ++ * - ``V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING`` ++ - The full UV range is used. ++ ++.. c:type:: v4l2_vp9_ref_id ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_ref_id ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_REF_ID_LAST`` ++ - Last reference frame. ++ * - ``V4L2_REF_ID_GOLDEN`` ++ - Golden reference frame. ++ * - ``V4L2_REF_ID_ALTREF`` ++ - Alternative reference frame. ++ * - ``V4L2_REF_ID_CNT`` ++ - Number of reference frames. ++ ++.. c:type:: v4l2_vp9_tx_mode ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_tx_mode ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_TX_MODE_ONLY_4X4`` ++ - Transform size is 4x4. ++ * - ``V4L2_VP9_TX_MODE_ALLOW_8X8`` ++ - Transform size can be up to 8x8. ++ * - ``V4L2_VP9_TX_MODE_ALLOW_16X16`` ++ - Transform size can be up to 16x16. ++ * - ``V4L2_VP9_TX_MODE_ALLOW_32X32`` ++ - transform size can be up to 32x32. ++ * - ``V4L2_VP9_TX_MODE_SELECT`` ++ - Bitstream contains transform size for each block. ++ ++.. c:type:: v4l2_vp9_reference_mode ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_reference_mode ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_REF_MODE_SINGLE`` ++ - Indicates that all the inter blocks use only a single reference frame ++ to generate motion compensated prediction. ++ * - ``V4L2_VP9_REF_MODE_COMPOUND`` ++ - Requires all the inter blocks to use compound mode. Single reference ++ frame prediction is not allowed. ++ * - ``V4L2_VP9_REF_MODE_SELECT`` ++ - Allows each individual inter block to select between single and ++ compound prediction modes. ++ ++.. c:type:: v4l2_vp9_interpolation_filter ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_interpolation_filter ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_INTERP_FILTER_8TAP`` ++ - Height tap filter. ++ * - ``V4L2_VP9_INTERP_FILTER_8TAP_SMOOTH`` ++ - Height tap smooth filter. ++ * - ``V4L2_VP9_INTERP_FILTER_8TAP_SHARP`` ++ - Height tap sharp filter. ++ * - ``V4L2_VP9_INTERP_FILTER_BILINEAR`` ++ - Bilinear filter. ++ * - ``V4L2_VP9_INTERP_FILTER_SWITCHABLE`` ++ - Filter selection is signaled at the block level. ++ ++.. c:type:: v4l2_vp9_reset_frame_context ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_reset_frame_context ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_RESET_FRAME_CTX_NONE`` ++ - Do not reset any frame context. ++ * - ``V4L2_VP9_RESET_FRAME_CTX_SPEC`` ++ - Reset the frame context pointed by ++ :c:type:`v4l2_ctrl_vp9_frame_decode_params`.frame_context_idx. ++ * - ``V4L2_VP9_RESET_FRAME_CTX_ALL`` ++ - Reset all frame contexts. ++ ++.. c:type:: v4l2_vp9_intra_prediction_mode ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_intra_prediction_mode ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_INTRA_PRED_DC`` ++ - DC intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_V`` ++ - Vertical intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_H`` ++ - Horizontal intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_D45`` ++ - D45 intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_D135`` ++ - D135 intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_D117`` ++ - D117 intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_D153`` ++ - D153 intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_D207`` ++ - D207 intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_D63`` ++ - D63 intra prediction. ++ * - ``V4L2_VP9_INTRA_PRED_MODE_TM`` ++ - True motion intra prediction. ++ ++.. c:type:: v4l2_vp9_segmentation ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: struct v4l2_vp9_segmentation ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``flags`` ++ - Combination of V4L2_VP9_SEGMENTATION_FLAG_* flags. See ++ :c:type:`v4l2_vp9_segmentation_flags`. ++ * - __u8 ++ - ``tree_probs[7]`` ++ - Specifies the probability values to be used when decoding a Segment-ID. ++ See '5.15. Segmentation map' section of :ref:`vp9` for more details. ++ * - __u8 ++ - ``pred_prob[3]`` ++ - Specifies the probability values to be used when decoding a ++ Predicted-Segment-ID. See '6.4.14. Get segment id syntax' ++ section of :ref:`vp9` for more details. ++ * - __u8 ++ - ``padding[5]`` ++ - Used to align this struct on 64 bit. Shall be filled with zeroes. ++ * - __u8 ++ - ``feature_enabled[8]`` ++ - Bitmask defining which features are enabled in each segment. ++ * - __u8 ++ - ``feature_data[8][4]`` ++ - Data attached to each feature. Data entry is only valid if the feature ++ is enabled. ++ ++.. c:type:: v4l2_vp9_segment_feature ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_segment_feature ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_SEGMENT_FEATURE_QP_DELTA`` ++ - QP delta segment feature. ++ * - ``V4L2_VP9_SEGMENT_FEATURE_LF`` ++ - Loop filter segment feature. ++ * - ``V4L2_VP9_SEGMENT_FEATURE_REF_FRAME`` ++ - Reference frame segment feature. ++ * - ``V4L2_VP9_SEGMENT_FEATURE_SKIP`` ++ - Skip segment feature. ++ * - ``V4L2_VP9_SEGMENT_FEATURE_CNT`` ++ - Number of segment features. ++ ++.. c:type:: v4l2_vp9_segmentation_flags ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_segmentation_flags ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_SEGMENTATION_FLAG_ENABLED`` ++ - Indicates that this frame makes use of the segmentation tool. ++ * - ``V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP`` ++ - Indicates that the segmentation map should be updated during the ++ decoding of this frame. ++ * - ``V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE`` ++ - Indicates that the updates to the segmentation map are coded ++ relative to the existing segmentation map. ++ * - ``V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA`` ++ - Indicates that new parameters are about to be specified for each ++ segment. ++ * - ``V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE`` ++ - Indicates that the segmentation parameters represent the actual values ++ to be used. ++ ++.. c:type:: v4l2_vp9_quantization ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: struct v4l2_vp9_quantization ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``base_q_idx`` ++ - Indicates the base frame qindex. ++ * - __s8 ++ - ``delta_q_y_dc`` ++ - Indicates the Y DC quantizer relative to base_q_idx. ++ * - __s8 ++ - ``delta_q_uv_dc`` ++ - Indicates the UV DC quantizer relative to base_q_idx. ++ * - __s8 ++ - ``delta_q_uv_ac`` ++ - Indicates the UV AC quantizer relative to base_q_idx. ++ * - __u8 ++ - ``padding[4]`` ++ - Padding bytes used to align this struct on 64 bit. Must be set to 0. ++ ++.. c:type:: v4l2_vp9_loop_filter ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: struct v4l2_vp9_loop_filter ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 1 2 ++ ++ * - __u8 ++ - ``flags`` ++ - Combination of V4L2_VP9_LOOP_FILTER_FLAG_* flags. ++ See :c:type:`v4l2_vp9_loop_filter_flags`. ++ * - __u8 ++ - ``level`` ++ - Indicates the loop filter strength. ++ * - __u8 ++ - ``sharpness`` ++ - Indicates the sharpness level. ++ * - __s8 ++ - ``ref_deltas[4]`` ++ - Contains the adjustment needed for the filter level based on the chosen ++ reference frame. ++ * - __s8 ++ - ``mode_deltas[2]`` ++ - Contains the adjustment needed for the filter level based on the chosen ++ mode ++ * - __u8 ++ - ``level_lookup[8][4][2]`` ++ - Level lookup table. ++ ++ ++.. c:type:: v4l2_vp9_loop_filter_flags ++ ++.. cssclass:: longtable ++ ++.. tabularcolumns:: |p{1.5cm}|p{6.3cm}|p{9.4cm}| ++ ++.. flat-table:: enum v4l2_vp9_loop_filter_flags ++ :header-rows: 0 ++ :stub-columns: 0 ++ :widths: 1 2 ++ ++ * - ``V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED`` ++ - When set, the filter level depends on the mode and reference frame used ++ to predict a block. ++ * - ``V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE`` ++ - When set, the bitstream contains additional syntax elements that ++ specify which mode and reference frame deltas are to be updated. ++ + .. raw:: latex + + \normalsize +diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c +index c4b5082849b6..b4802c9989fd 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls-core.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c +@@ -289,6 +289,219 @@ static void std_log(const struct v4l2_ctrl *ctrl) + } + } +static int +validate_vp9_lf_params(struct v4l2_vp9_loop_filter *lf) @@ -847,11 +1377,11 @@ index 41f8410d08d6..7ed11f296008 100644 + return 0; +} + - /* Validate a new control */ - - #define zero_padding(s) \ -@@ -1871,6 +2098,12 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, - zero_padding(p_vp8_frame_header->coder_state); + /* + * Round towards the closest legal value. Be careful when we are + * close to the maximum range of the control type to prevent +@@ -574,6 +787,12 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, + zero_padding(p_vp8_frame->coder_state); break; + case V4L2_CTRL_TYPE_VP9_FRAME_DECODE_PARAMS: @@ -863,9 +1393,9 @@ index 41f8410d08d6..7ed11f296008 100644 case V4L2_CTRL_TYPE_HEVC_SPS: p_hevc_sps = p; -@@ -2635,6 +2868,12 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, - case V4L2_CTRL_TYPE_VP8_FRAME_HEADER: - elem_size = sizeof(struct v4l2_ctrl_vp8_frame_header); +@@ -1231,6 +1450,12 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, + case V4L2_CTRL_TYPE_VP8_FRAME: + elem_size = sizeof(struct v4l2_ctrl_vp8_frame); break; + case V4L2_CTRL_TYPE_VP9_FRAME_CONTEXT: + elem_size = sizeof(struct v4l2_ctrl_vp9_frame_ctx); @@ -876,11 +1406,43 @@ index 41f8410d08d6..7ed11f296008 100644 case V4L2_CTRL_TYPE_HEVC_SPS: elem_size = sizeof(struct v4l2_ctrl_hevc_sps); break; +diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c +index b6344bbf1e00..22a031e25499 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c +@@ -940,6 +940,11 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_MPEG_VIDEO_VP8_PROFILE: return "VP8 Profile"; + case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: return "VP9 Profile"; + case V4L2_CID_MPEG_VIDEO_VP9_LEVEL: return "VP9 Level"; ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS: return "VP9 Frame Decode Parameters"; ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(0): return "VP9 Frame Context 0"; ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(1): return "VP9 Frame Context 1"; ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(2): return "VP9 Frame Context 2"; ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(3): return "VP9 Frame Context 3"; + + /* HEVC controls */ + case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: return "HEVC I-Frame QP Value"; +@@ -1479,6 +1484,15 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, + case V4L2_CID_STATELESS_VP8_FRAME: + *type = V4L2_CTRL_TYPE_VP8_FRAME; + break; ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_DECODE_PARAMS: ++ *type = V4L2_CTRL_TYPE_VP9_FRAME_DECODE_PARAMS; ++ break; ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(0): ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(1): ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(2): ++ case V4L2_CID_MPEG_VIDEO_VP9_FRAME_CONTEXT(3): ++ *type = V4L2_CTRL_TYPE_VP9_FRAME_CONTEXT; ++ break; + case V4L2_CID_MPEG_VIDEO_HEVC_SPS: + *type = V4L2_CTRL_TYPE_HEVC_SPS; + break; diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 1ff68c1bf14a..783733bef2da 100644 +index fe43d785414c..47f812a081ca 100644 --- a/drivers/media/v4l2-core/v4l2-ioctl.c +++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1429,6 +1429,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) +@@ -1394,6 +1394,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) case V4L2_PIX_FMT_VP8: descr = "VP8"; break; case V4L2_PIX_FMT_VP8_FRAME: descr = "VP8 Frame"; break; case V4L2_PIX_FMT_VP9: descr = "VP9"; break; @@ -889,30 +1451,30 @@ index 1ff68c1bf14a..783733bef2da 100644 case V4L2_PIX_FMT_HEVC_SLICE: descr = "HEVC Parsed Slice Data"; break; case V4L2_PIX_FMT_FWHT: descr = "FWHT"; break; /* used in vicodec */ diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h -index 9ecbb98908f0..ebcb34759ad8 100644 +index 575b59fbac77..f62c529b6a70 100644 --- a/include/media/v4l2-ctrls.h +++ b/include/media/v4l2-ctrls.h -@@ -21,6 +21,7 @@ - #include - #include - #include -+#include +@@ -18,6 +18,7 @@ + * This will move to the public headers once this API is fully stable. + */ #include ++#include /* forward references */ -@@ -53,6 +54,8 @@ struct video_device; + struct file; +@@ -50,6 +51,8 @@ struct video_device; * @p_h264_decode_params: Pointer to a struct v4l2_ctrl_h264_decode_params. * @p_h264_pred_weights: Pointer to a struct v4l2_ctrl_h264_pred_weights. - * @p_vp8_frame_header: Pointer to a VP8 frame header structure. + * @p_vp8_frame: Pointer to a VP8 frame params structure. + * @p_vp9_frame_ctx: Pointer to a VP9 frame context structure. + * @p_vp9_frame_decode_params: Pointer to a VP9 frame params structure. * @p_hevc_sps: Pointer to an HEVC sequence parameter set structure. * @p_hevc_pps: Pointer to an HEVC picture parameter set structure. * @p_hevc_slice_params: Pointer to an HEVC slice parameters structure. -@@ -80,6 +83,8 @@ union v4l2_ctrl_ptr { - struct v4l2_ctrl_hevc_sps *p_hevc_sps; - struct v4l2_ctrl_hevc_pps *p_hevc_pps; +@@ -82,6 +85,8 @@ union v4l2_ctrl_ptr { struct v4l2_ctrl_hevc_slice_params *p_hevc_slice_params; + struct v4l2_ctrl_hdr10_cll_info *p_hdr10_cll; + struct v4l2_ctrl_hdr10_mastering_display *p_hdr10_mastering; + struct v4l2_ctrl_vp9_frame_ctx *p_vp9_frame_ctx; + struct v4l2_ctrl_vp9_frame_decode_params *p_vp9_frame_decode_params; struct v4l2_area *p_area; @@ -920,7 +1482,7 @@ index 9ecbb98908f0..ebcb34759ad8 100644 const void *p_const; diff --git a/include/media/vp9-ctrls.h b/include/media/vp9-ctrls.h new file mode 100644 -index 000000000000..a14fffb3ad61 +index 000000000000..f62f528d4b39 --- /dev/null +++ b/include/media/vp9-ctrls.h @@ -0,0 +1,486 @@ @@ -1425,9 +1987,9 @@ Signed-off-by: Adrian Ratiu --- drivers/staging/media/rkvdec/Makefile | 2 +- drivers/staging/media/rkvdec/rkvdec-vp9.c | 1577 +++++++++++++++++++++ - drivers/staging/media/rkvdec/rkvdec.c | 60 +- + drivers/staging/media/rkvdec/rkvdec.c | 59 +- drivers/staging/media/rkvdec/rkvdec.h | 6 + - 4 files changed, 1643 insertions(+), 2 deletions(-) + 4 files changed, 1642 insertions(+), 2 deletions(-) create mode 100644 drivers/staging/media/rkvdec/rkvdec-vp9.c diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile @@ -3023,10 +3585,10 @@ index 000000000000..8b443ed511c9 + .done = rkvdec_vp9_done, +}; diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index c4e0ec16c285..f3578c5ea902 100644 +index fbaf0303f7c2..2c0c6dcbd066 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -162,6 +162,39 @@ static const u32 rkvdec_h264_decoded_fmts[] = { +@@ -159,6 +159,39 @@ static const u32 rkvdec_h264_decoded_fmts[] = { V4L2_PIX_FMT_NV20, }; @@ -3066,7 +3628,7 @@ index c4e0ec16c285..f3578c5ea902 100644 static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { { .fourcc = V4L2_PIX_FMT_H264_SLICE, -@@ -177,6 +211,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { +@@ -174,6 +207,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { .ops = &rkvdec_h264_fmt_ops, .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), .decoded_fmts = rkvdec_h264_decoded_fmts, @@ -3088,7 +3650,7 @@ index c4e0ec16c285..f3578c5ea902 100644 } }; -@@ -376,7 +425,7 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, +@@ -373,7 +421,7 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; const struct rkvdec_coded_fmt_desc *desc; struct v4l2_format *cap_fmt; @@ -3097,7 +3659,7 @@ index c4e0ec16c285..f3578c5ea902 100644 int ret; /* -@@ -388,6 +437,15 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, +@@ -385,6 +433,15 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, if (vb2_is_busy(peer_vq)) return -EBUSY; @@ -3114,10 +3676,10 @@ index c4e0ec16c285..f3578c5ea902 100644 if (ret) return ret; diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index c14cd2571bfc..d760c3609e2c 100644 +index fa24bcb6ff42..18dd721172d8 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -58,6 +58,10 @@ struct rkvdec_vp9_decoded_buffer_info { +@@ -57,6 +57,10 @@ struct rkvdec_vp9_decoded_buffer_info { struct rkvdec_decoded_buffer { /* Must be the first field in this struct. */ struct v4l2_m2m_buffer base; @@ -3128,7 +3690,7 @@ index c14cd2571bfc..d760c3609e2c 100644 }; static inline struct rkvdec_decoded_buffer * -@@ -128,4 +132,6 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); +@@ -127,4 +131,6 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; diff --git a/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch b/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch index 246dda8da6..bd7b255037 100644 --- a/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch +++ b/projects/Rockchip/patches/linux/default/linux-2001-v4l-wip-rkvdec-hevc.patch @@ -1,41 +1,49 @@ From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 26 Oct 2019 13:55:15 +0200 -Subject: [PATCH] media: uapi: hevc: Add scaling matrix control +From: Benjamin Gaignard +Date: Thu, 15 Jul 2021 17:12:22 +0200 +Subject: [PATCH] media: hevc: Add scaling matrix control -HEVC has a scaling matrix concept. Add support for it. +HEVC scaling lists are used for the scaling process for transform +coefficients. +V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED has to set when they are +encoded in the bitstream. -Signed-off-by: Jernej Skrabec +Signed-off-by: Benjamin Gaignard +Reviewed-by: Jernej Skrabec +Reviewed-by: Ezequiel Garcia +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab --- - .../media/v4l/ext-ctrls-codec.rst | 41 +++++++++++++++++++ - .../media/v4l/pixfmt-compressed.rst | 1 + - drivers/media/v4l2-core/v4l2-ctrls.c | 10 +++++ - include/media/hevc-ctrls.h | 11 +++++ - 4 files changed, 63 insertions(+) + .../media/v4l/ext-ctrls-codec.rst | 57 +++++++++++++++++++ + .../media/v4l/vidioc-queryctrl.rst | 6 ++ + drivers/media/v4l2-core/v4l2-ctrls-core.c | 6 ++ + drivers/media/v4l2-core/v4l2-ctrls-defs.c | 4 ++ + include/media/hevc-ctrls.h | 11 ++++ + 5 files changed, 84 insertions(+) diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -index 456488f2b5ca..81529b1d8d69 100644 +index 5dd4afc5f1fe..dc08368d62fe 100644 --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -@@ -4866,6 +4866,47 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - - - ``padding[6]`` - - Applications and drivers must set this to zero. +@@ -3068,6 +3068,63 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - + + \normalsize +``V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (struct)`` -+ Specifies the scaling matrix (as extracted from the bitstream) for -+ the associated HEVC slice data. The bitstream parameters are -+ defined according to :ref:`hevc`, section 7.4.5 "Scaling list -+ data semantics". For further documentation, refer to the above -+ specification, unless there is an explicit comment stating -+ otherwise. -+ -+ .. note:: -+ -+ This compound control is not yet part of the public kernel API and -+ it is expected to change. ++ Specifies the HEVC scaling matrix parameters used for the scaling process ++ for transform coefficients. ++ These matrix and parameters are defined according to :ref:`hevc`. ++ They are described in section 7.4.5 "Scaling list data semantics" of ++ the specification. + +.. c:type:: v4l2_ctrl_hevc_scaling_matrix + ++.. raw:: latex ++ ++ \scriptsize ++ ++.. tabularcolumns:: |p{5.4cm}|p{6.8cm}|p{5.1cm}| ++ +.. cssclass:: longtable + +.. flat-table:: struct v4l2_ctrl_hevc_scaling_matrix @@ -45,50 +53,65 @@ index 456488f2b5ca..81529b1d8d69 100644 + + * - __u8 + - ``scaling_list_4x4[6][16]`` -+ - ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. + * - __u8 + - ``scaling_list_8x8[6][64]`` -+ - ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. + * - __u8 + - ``scaling_list_16x16[6][64]`` -+ - ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. + * - __u8 + - ``scaling_list_32x32[2][64]`` -+ - ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. + * - __u8 + - ``scaling_list_dc_coef_16x16[6]`` -+ - ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. + * - __u8 + - ``scaling_list_dc_coef_32x32[2]`` -+ - ++ - Scaling list is used for the scaling process for transform ++ coefficients. The values on each scaling list are expected ++ in raster scan order. + - ``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (enum)`` - Specifies the decoding mode to use. Currently exposes slice-based and - frame-based decoding but new modes might be added later on. -diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c -index 7ed11f296008..a2609de88d26 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls.c -@@ -1026,6 +1026,7 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_MPEG_VIDEO_HEVC_SPS: return "HEVC Sequence Parameter Set"; - case V4L2_CID_MPEG_VIDEO_HEVC_PPS: return "HEVC Picture Parameter Set"; - case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: return "HEVC Slice Parameters"; -+ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: return "HEVC Scaling Matrix"; - case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE: return "HEVC Decode Mode"; - case V4L2_CID_MPEG_VIDEO_HEVC_START_CODE: return "HEVC Start Code"; ++.. raw:: latex ++ ++ \normalsize ++ + .. c:type:: v4l2_hevc_dpb_entry + + .. raw:: latex +diff --git a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst +index f9ecf6276129..2f491c17dd5d 100644 +--- a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst ++++ b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst +@@ -495,6 +495,12 @@ See also the examples in :ref:`control`. + - n/a + - A struct :c:type:`v4l2_ctrl_hevc_slice_params`, containing HEVC + slice parameters for stateless video decoders. ++ * - ``V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX`` ++ - n/a ++ - n/a ++ - n/a ++ - A struct :c:type:`v4l2_ctrl_hevc_scaling_matrix`, containing HEVC ++ scaling matrix for stateless video decoders. + * - ``V4L2_CTRL_TYPE_VP8_FRAME`` + - n/a + - n/a +diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c +index b4802c9989fd..f557aca9d966 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls-core.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c +@@ -906,6 +906,9 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, -@@ -1475,6 +1476,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: - *type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS; - break; -+ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: -+ *type = V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX; -+ break; - case V4L2_CID_UNIT_CELL_SIZE: - *type = V4L2_CTRL_TYPE_AREA; - *flags |= V4L2_CTRL_FLAG_READ_ONLY; -@@ -2167,6 +2171,9 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, - zero_padding(*p_hevc_slice_params); break; + case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: @@ -97,18 +120,40 @@ index 7ed11f296008..a2609de88d26 100644 case V4L2_CTRL_TYPE_AREA: area = p; if (!area->width || !area->height) -@@ -2883,6 +2890,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, +@@ -1465,6 +1468,9 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params); break; + case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: + elem_size = sizeof(struct v4l2_ctrl_hevc_scaling_matrix); + break; - case V4L2_CTRL_TYPE_AREA: - elem_size = sizeof(struct v4l2_area); + case V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS: + elem_size = sizeof(struct v4l2_ctrl_hevc_decode_params); + break; +diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c +index 22a031e25499..bca21812e216 100644 +--- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c ++++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c +@@ -1001,6 +1001,7 @@ const char *v4l2_ctrl_get_name(u32 id) + case V4L2_CID_MPEG_VIDEO_HEVC_SPS: return "HEVC Sequence Parameter Set"; + case V4L2_CID_MPEG_VIDEO_HEVC_PPS: return "HEVC Picture Parameter Set"; + case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: return "HEVC Slice Parameters"; ++ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: return "HEVC Scaling Matrix"; + case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS: return "HEVC Decode Parameters"; + case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE: return "HEVC Decode Mode"; + case V4L2_CID_MPEG_VIDEO_HEVC_START_CODE: return "HEVC Start Code"; +@@ -1502,6 +1503,9 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, + case V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS: + *type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS; + break; ++ case V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX: ++ *type = V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX; ++ break; + case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS: + *type = V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS; break; diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index 1009cf0891cc..1592e52c3614 100644 +index 53c0038c792b..0e5c4a2eecff 100644 --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h @@ -19,6 +19,7 @@ @@ -116,18 +161,18 @@ index 1009cf0891cc..1592e52c3614 100644 #define V4L2_CID_MPEG_VIDEO_HEVC_PPS (V4L2_CID_CODEC_BASE + 1009) #define V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS (V4L2_CID_CODEC_BASE + 1010) +#define V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (V4L2_CID_CODEC_BASE + 1011) + #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS (V4L2_CID_CODEC_BASE + 1012) #define V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (V4L2_CID_CODEC_BASE + 1015) #define V4L2_CID_MPEG_VIDEO_HEVC_START_CODE (V4L2_CID_CODEC_BASE + 1016) - -@@ -26,6 +27,7 @@ +@@ -27,6 +28,7 @@ #define V4L2_CTRL_TYPE_HEVC_SPS 0x0120 #define V4L2_CTRL_TYPE_HEVC_PPS 0x0121 #define V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS 0x0122 +#define V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX 0x0123 + #define V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS 0x0124 enum v4l2_mpeg_video_hevc_decode_mode { - V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED, -@@ -209,4 +211,13 @@ struct v4l2_ctrl_hevc_slice_params { +@@ -224,6 +226,15 @@ struct v4l2_ctrl_hevc_decode_params { __u64 flags; }; @@ -140,70 +185,59 @@ index 1009cf0891cc..1592e52c3614 100644 + __u8 scaling_list_dc_coef_32x32[2]; +}; + - #endif + /* MPEG-class control IDs specific to the Hantro driver as defined by V4L2 */ + #define V4L2_CID_CODEC_HANTRO_BASE (V4L2_CTRL_CLASS_CODEC | 0x1200) + /* From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 26 Oct 2019 15:42:28 +0200 -Subject: [PATCH] media: uapi: hevc: Add segment address field +From: Jernej Skrabec +Date: Sun, 6 Jun 2021 10:23:13 +0200 +Subject: [PATCH] media: hevc: Add segment address field If HEVC frame consists of multiple slices, segment address has to be known in order to properly decode it. Add segment address field to slice parameters. -Signed-off-by: Jernej Skrabec +Signed-off-by: Jernej Skrabec +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab --- - Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst | 5 ++++- - include/media/hevc-ctrls.h | 5 ++++- - 2 files changed, 8 insertions(+), 2 deletions(-) + Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst | 3 +++ + include/media/hevc-ctrls.h | 3 ++- + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -index 81529b1d8d69..817773791888 100644 +index dc08368d62fe..9b25674fcd40 100644 --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -@@ -4661,6 +4661,9 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - - * - __u32 - - ``data_bit_offset`` - - Offset (in bits) to the video data in the current slice data. +@@ -3000,6 +3000,9 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - + * - __u8 + - ``pic_struct`` + - + * - __u32 + - ``slice_segment_addr`` + - * - __u8 - - ``nal_unit_type`` - - -@@ -4738,7 +4741,7 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - - - ``num_rps_poc_lt_curr`` - - The number of reference pictures in the long-term set. - * - __u8 -- - ``padding[7]`` -+ - ``padding[5]`` - - Applications and drivers must set this to zero. - * - struct :c:type:`v4l2_hevc_dpb_entry` - - ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` + - ``ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` + - The list of L0 reference elements as indices in the DPB. diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index 1592e52c3614..3e2e32098312 100644 +index 0e5c4a2eecff..ef63bc205756 100644 --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h -@@ -167,6 +167,9 @@ struct v4l2_ctrl_hevc_slice_params { - __u32 bit_size; - __u32 data_bit_offset; - -+ /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ -+ __u32 slice_segment_addr; -+ - /* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */ - __u8 nal_unit_type; - __u8 nuh_temporal_id_plus1; -@@ -200,7 +203,7 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 num_rps_poc_st_curr_after; - __u8 num_rps_poc_lt_curr; - -- __u8 padding; -+ __u8 padding[5]; +@@ -198,10 +198,11 @@ struct v4l2_ctrl_hevc_slice_params { + __u8 pic_struct; /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ - struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; ++ __u32 slice_segment_addr; + __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + +- __u8 padding[5]; ++ __u8 padding; + + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ + struct v4l2_hevc_pred_weight_table pred_weight_table; From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman @@ -214,46 +248,40 @@ NOTE: these fields are used by rkvdec hevc backend Signed-off-by: Jonas Karlman --- - include/media/hevc-ctrls.h | 16 ++++++++++++---- - 1 file changed, 12 insertions(+), 4 deletions(-) + include/media/hevc-ctrls.h | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index 3e2e32098312..3cc3b47e1417 100644 +index ef63bc205756..a808894e8c76 100644 --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h -@@ -56,6 +56,9 @@ enum v4l2_mpeg_video_hevc_start_code { +@@ -58,6 +58,8 @@ enum v4l2_mpeg_video_hevc_start_code { /* The controls are not stable at the moment and will likely be reworked. */ struct v4l2_ctrl_hevc_sps { /* ISO/IEC 23008-2, ITU-T Rec. H.265: Sequence parameter set */ + __u8 video_parameter_set_id; + __u8 seq_parameter_set_id; -+ __u8 chroma_format_idc; __u16 pic_width_in_luma_samples; __u16 pic_height_in_luma_samples; __u8 bit_depth_luma_minus8; -@@ -76,9 +79,8 @@ struct v4l2_ctrl_hevc_sps { - __u8 log2_diff_max_min_pcm_luma_coding_block_size; - __u8 num_short_term_ref_pic_sets; - __u8 num_long_term_ref_pics_sps; -- __u8 chroma_format_idc; - -- __u8 padding; -+ __u8 padding[7]; +@@ -81,6 +83,8 @@ struct v4l2_ctrl_hevc_sps { + __u8 chroma_format_idc; + __u8 sps_max_sub_layers_minus1; ++ __u8 padding[6]; ++ __u64 flags; }; -@@ -105,7 +107,10 @@ struct v4l2_ctrl_hevc_sps { + +@@ -108,6 +112,7 @@ struct v4l2_ctrl_hevc_sps { struct v4l2_ctrl_hevc_pps { /* ISO/IEC 23008-2, ITU-T Rec. H.265: Picture parameter set */ + __u8 pic_parameter_set_id; __u8 num_extra_slice_header_bits; -+ __u8 num_ref_idx_l0_default_active_minus1; -+ __u8 num_ref_idx_l1_default_active_minus1; - __s8 init_qp_minus26; - __u8 diff_cu_qp_delta_depth; - __s8 pps_cb_qp_offset; -@@ -118,7 +123,7 @@ struct v4l2_ctrl_hevc_pps { + __u8 num_ref_idx_l0_default_active_minus1; + __u8 num_ref_idx_l1_default_active_minus1; +@@ -123,7 +128,7 @@ struct v4l2_ctrl_hevc_pps { __s8 pps_tc_offset_div2; __u8 log2_parallel_merge_level_minus2; @@ -262,18 +290,18 @@ index 3e2e32098312..3cc3b47e1417 100644 __u64 flags; }; -@@ -203,7 +208,10 @@ struct v4l2_ctrl_hevc_slice_params { - __u8 num_rps_poc_st_curr_after; - __u8 num_rps_poc_lt_curr; +@@ -202,7 +207,10 @@ struct v4l2_ctrl_hevc_slice_params { + __u8 ref_idx_l0[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + __u8 ref_idx_l1[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; -- __u8 padding[5]; +- __u8 padding; + __u16 short_term_ref_pic_set_size; + __u16 long_term_ref_pic_set_size; + -+ __u8 padding; ++ __u8 padding[4]; - /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ - struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ + struct v4l2_hevc_pred_weight_table pred_weight_table; From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman @@ -281,42 +309,34 @@ Date: Sat, 23 May 2020 15:07:15 +0000 Subject: [PATCH] HACK: media: uapi: hevc: tiles and num_slices --- - include/media/hevc-ctrls.h | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) + include/media/hevc-ctrls.h | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/media/hevc-ctrls.h b/include/media/hevc-ctrls.h -index 3cc3b47e1417..b33e1a8141e1 100644 +index a808894e8c76..f1b8756521b9 100644 --- a/include/media/hevc-ctrls.h +++ b/include/media/hevc-ctrls.h -@@ -80,7 +80,8 @@ struct v4l2_ctrl_hevc_sps { - __u8 num_short_term_ref_pic_sets; - __u8 num_long_term_ref_pics_sps; +@@ -83,7 +83,8 @@ struct v4l2_ctrl_hevc_sps { + __u8 chroma_format_idc; + __u8 sps_max_sub_layers_minus1; -- __u8 padding[7]; +- __u8 padding[6]; + __u8 num_slices; -+ __u8 padding[6]; ++ __u8 padding[5]; __u64 flags; }; -@@ -174,6 +175,7 @@ struct v4l2_ctrl_hevc_slice_params { - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ - __u32 slice_segment_addr; -+ __u32 num_entry_point_offsets; - - /* ISO/IEC 23008-2, ITU-T Rec. H.265: NAL unit header */ - __u8 nal_unit_type; -@@ -211,7 +213,9 @@ struct v4l2_ctrl_hevc_slice_params { +@@ -210,7 +211,9 @@ struct v4l2_ctrl_hevc_slice_params { __u16 short_term_ref_pic_set_size; __u16 long_term_ref_pic_set_size; -- __u8 padding; -+ __u8 padding[5]; -+ +- __u8 padding[4]; ++ __u32 num_entry_point_offsets; + __u32 entry_point_offset_minus1[256]; ++ __u8 padding[8]; - /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */ - struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]; + /* ISO/IEC 23008-2, ITU-T Rec. H.265: Weighted prediction parameter */ + struct v4l2_hevc_pred_weight_table pred_weight_table; From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman @@ -331,9 +351,9 @@ Signed-off-by: Jonas Karlman drivers/staging/media/rkvdec/Makefile | 2 +- drivers/staging/media/rkvdec/rkvdec-hevc.c | 2522 ++++++++++++++++++++ drivers/staging/media/rkvdec/rkvdec-regs.h | 1 + - drivers/staging/media/rkvdec/rkvdec.c | 70 + + drivers/staging/media/rkvdec/rkvdec.c | 67 + drivers/staging/media/rkvdec/rkvdec.h | 1 + - 5 files changed, 2595 insertions(+), 1 deletion(-) + 5 files changed, 2592 insertions(+), 1 deletion(-) create mode 100644 drivers/staging/media/rkvdec/rkvdec-hevc.c diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile @@ -347,7 +367,7 @@ index cb86b429cfaa..a77122641d14 100644 +rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c new file mode 100644 -index 000000000000..03ba848411c6 +index 000000000000..c3cceba837c2 --- /dev/null +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c @@ -0,0 +1,2522 @@ @@ -2886,11 +2906,11 @@ index 3acc914888f6..4addfaefdfb4 100644 #define RKVDEC_MODE_VP9 2 #define RKVDEC_RPS_MODE BIT(24) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index f3578c5ea902..a44db1aa161e 100644 +index 2c0c6dcbd066..c269e4a21a29 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -162,6 +162,57 @@ static const u32 rkvdec_h264_decoded_fmts[] = { - V4L2_PIX_FMT_NV20, +@@ -147,6 +147,58 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { + }, }; +static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { @@ -2944,10 +2964,11 @@ index f3578c5ea902..a44db1aa161e 100644 + V4L2_PIX_FMT_NV15, +}; + - static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = { - { - .mandatory = true, -@@ -212,6 +267,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { ++ + static const struct rkvdec_ctrls rkvdec_h264_ctrls = { + .ctrls = rkvdec_h264_ctrl_descs, + .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), +@@ -208,6 +260,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), .decoded_fmts = rkvdec_h264_decoded_fmts, }, @@ -2970,10 +2991,10 @@ index f3578c5ea902..a44db1aa161e 100644 .fourcc = V4L2_PIX_FMT_VP9_FRAME, .frmsize = { diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index d760c3609e2c..975fe4b5dd68 100644 +index 18dd721172d8..d60840c179a4 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -132,6 +132,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); +@@ -131,6 +131,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; @@ -2982,6 +3003,132 @@ index d760c3609e2c..975fe4b5dd68 100644 #endif /* RKVDEC_H_ */ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sat, 21 Aug 2021 16:01:43 +0200 +Subject: [PATCH] media: rkvdec: hevc: adapt for 5.14 uAPI + +Signed-off-by: Alex Bee +--- + drivers/staging/media/rkvdec/rkvdec-hevc.c | 29 +++++++++++++--------- + drivers/staging/media/rkvdec/rkvdec.c | 3 +++ + 2 files changed, 20 insertions(+), 12 deletions(-) + +diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c +index c3cceba837c2..5c341b5fa534 100644 +--- a/drivers/staging/media/rkvdec/rkvdec-hevc.c ++++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c +@@ -116,6 +116,7 @@ struct rkvdec_hevc_priv_tbl { + struct rkvdec_hevc_run { + struct rkvdec_run base; + const struct v4l2_ctrl_hevc_slice_params *slices_params; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params; + const struct v4l2_ctrl_hevc_sps *sps; + const struct v4l2_ctrl_hevc_pps *pps; + const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; +@@ -2179,6 +2180,7 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, + static void assemble_hw_rps(struct rkvdec_ctx *ctx, + struct rkvdec_hevc_run *run) + { ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; + const struct v4l2_ctrl_hevc_slice_params *sl_params; + const struct v4l2_hevc_dpb_entry *dpb; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; +@@ -2200,7 +2202,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + + for (j = 0; j < run->num_slices; j++) { + sl_params = &run->slices_params[j]; +- dpb = sl_params->dpb; ++ dpb = decode_params->dpb; + + hw_ps = &priv_tbl->rps[j]; + memset(hw_ps, 0, sizeof(*hw_ps)); +@@ -2228,9 +2230,9 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, + WRITE_RPS(sl_params->long_term_ref_pic_set_size, + LONG_TERM_REF_PIC_SET_SIZE); + +- WRITE_RPS(sl_params->num_rps_poc_st_curr_before + +- sl_params->num_rps_poc_st_curr_after + +- sl_params->num_rps_poc_lt_curr, ++ WRITE_RPS(decode_params->num_poc_st_curr_before + ++ decode_params->num_poc_st_curr_after + ++ decode_params->num_poc_lt_curr, + NUM_RPS_POC); + + //WRITE_RPS(0x3ffff, PS_FIELD(206, 18)); +@@ -2280,12 +2282,12 @@ get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, + unsigned int dpb_idx) + { + struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; +- const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; +- const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; ++ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; + struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; + int buf_idx = -1; + +- if (dpb_idx < sl_params->num_active_dpb_entries) ++ if (dpb_idx < decode_params->num_active_dpb_entries) + buf_idx = vb2_find_timestamp(cap_q, + dpb[dpb_idx].timestamp, 0); + +@@ -2303,8 +2305,9 @@ static void config_registers(struct rkvdec_ctx *ctx, + struct rkvdec_hevc_run *run) + { + struct rkvdec_dev *rkvdec = ctx->dev; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; + const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; +- const struct v4l2_hevc_dpb_entry *dpb = sl_params->dpb; ++ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; + dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; + const struct v4l2_pix_format_mplane *dst_fmt; +@@ -2366,8 +2369,8 @@ static void config_registers(struct rkvdec_ctx *ctx, + for (i = 0; i < 15; i++) { + struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); + +- if (i < 4 && sl_params->num_active_dpb_entries) { +- reg = GENMASK(sl_params->num_active_dpb_entries - 1, 0); ++ if (i < 4 && decode_params->num_active_dpb_entries) { ++ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); + reg = (reg >> (i * 4)) & 0xf; + } else + reg = 0; +@@ -2376,7 +2379,7 @@ static void config_registers(struct rkvdec_ctx *ctx, + writel_relaxed(refer_addr | reg, + rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); + +- reg = RKVDEC_POC_REFER(i < sl_params->num_active_dpb_entries ? dpb[i].pic_order_cnt[0] : 0); ++ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt[0] : 0); + writel_relaxed(reg, + rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); + } +@@ -2461,7 +2464,9 @@ static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, + struct rkvdec_hevc_run *run) + { + struct v4l2_ctrl *ctrl; +- ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS); ++ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, + V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS); + run->slices_params = ctrl ? ctrl->p_cur.p : NULL; +diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c +index c269e4a21a29..e91c2b3e9fd9 100644 +--- a/drivers/staging/media/rkvdec/rkvdec.c ++++ b/drivers/staging/media/rkvdec/rkvdec.c +@@ -163,6 +163,9 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { + { + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX, + }, ++ { ++ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS, ++ }, + { + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE, + .cfg.min = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_FRAME_BASED, + From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 1 Aug 2020 12:24:58 +0000 @@ -2993,10 +3140,10 @@ Subject: [PATCH] WIP: media: rkvdec: add HEVC format validation 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 03ba848411c6..b8ad7fc2271c 100644 +index 5c341b5fa534..8ea2ad9f4f3a 100644 --- a/drivers/staging/media/rkvdec/rkvdec-hevc.c +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2415,6 +2415,16 @@ static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, +@@ -2418,6 +2418,16 @@ static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, return 0; } @@ -3013,7 +3160,7 @@ index 03ba848411c6..b8ad7fc2271c 100644 static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) { struct rkvdec_dev *rkvdec = ctx->dev; -@@ -2516,6 +2526,7 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) +@@ -2521,6 +2531,7 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { .adjust_fmt = rkvdec_hevc_adjust_fmt, @@ -3022,7 +3169,7 @@ index 03ba848411c6..b8ad7fc2271c 100644 .stop = rkvdec_hevc_stop, .run = rkvdec_hevc_run, diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index a44db1aa161e..7419ae7027ab 100644 +index e91c2b3e9fd9..da32a6350344 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -79,6 +79,26 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) @@ -3056,19 +3203,19 @@ index a44db1aa161e..7419ae7027ab 100644 { struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); -- if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_SPS && !ctx->valid_fmt) { +- if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) { + if (!ctx->valid_fmt) { ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); if (ctx->valid_fmt) { struct v4l2_pix_format_mplane *pix_mp; -@@ -173,6 +193,7 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { +@@ -156,6 +176,7 @@ static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { + }, { - .mandatory = true, .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS, + .cfg.ops = &rkvdec_ctrl_ops, }, { - .mandatory = true, + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PPS, From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee @@ -3082,10 +3229,10 @@ Signed-off-by: Alex Bee 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index b8ad7fc2271c..943f3f4a644a 100644 +index 8ea2ad9f4f3a..58ae8a1a4ff3 100644 --- a/drivers/staging/media/rkvdec/rkvdec-hevc.c +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2164,9 +2164,9 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, +@@ -2165,9 +2165,9 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, for (i = 0; i <= pps->num_tile_rows_minus1; i++) WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i)); } else { @@ -3109,10 +3256,10 @@ Signed-off-by: Alex Bee 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 943f3f4a644a..93b4e09e5bf1 100644 +index 58ae8a1a4ff3..55bf61a84165 100644 --- a/drivers/staging/media/rkvdec/rkvdec-hevc.c +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2194,8 +2194,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, +@@ -2196,8 +2196,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, #define REF_PIC_IDX_L1(i) PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4) #define LOWDELAY PS_FIELD(182, 1) @@ -3123,7 +3270,7 @@ index 943f3f4a644a..93b4e09e5bf1 100644 #define NUM_RPS_POC PS_FIELD(202, 4) for (j = 0; j < run->num_slices; j++) { -@@ -2222,11 +2222,11 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, +@@ -2224,11 +2224,11 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, // TODO: lowdelay WRITE_RPS(0, LOWDELAY); @@ -3137,8 +3284,8 @@ index 943f3f4a644a..93b4e09e5bf1 100644 - LONG_TERM_REF_PIC_SET_SIZE); + SHORT_TERM_RPS_BIT_OFFSET); - WRITE_RPS(sl_params->num_rps_poc_st_curr_before + - sl_params->num_rps_poc_st_curr_after + + WRITE_RPS(decode_params->num_poc_st_curr_before + + decode_params->num_poc_st_curr_after + From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee @@ -3148,13 +3295,13 @@ Subject: [PATCH] WIP: media: rkvdec: hevc: implement lowdelay Signed-off-by: Alex Bee --- drivers/staging/media/rkvdec/rkvdec-hevc.c | 16 ++++++++++++++-- - 1 files changed, 14 insertions(+), 2 deletions(-) + 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 93b4e09e5bf1..8a94fc04980f 100644 +index 55bf61a84165..3cca79282111 100644 --- a/drivers/staging/media/rkvdec/rkvdec-hevc.c +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2185,6 +2185,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, +@@ -2187,6 +2187,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; struct rkvdec_rps_packet *hw_ps; int i, j; @@ -3162,15 +3309,15 @@ index 93b4e09e5bf1..8a94fc04980f 100644 #define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value) -@@ -2201,6 +2202,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, +@@ -2203,6 +2204,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, for (j = 0; j < run->num_slices; j++) { sl_params = &run->slices_params[j]; - dpb = sl_params->dpb; + dpb = decode_params->dpb; + lowdelay = 0; hw_ps = &priv_tbl->rps[j]; memset(hw_ps, 0, sizeof(*hw_ps)); -@@ -2219,8 +2221,18 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, +@@ -2221,8 +2223,18 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, //WRITE_RPS(0xffffffff, PS_FIELD(96, 32)); @@ -3179,7 +3326,7 @@ index 93b4e09e5bf1..8a94fc04980f 100644 + if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I && + !(!!(sl_params->flags & V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT))) { + lowdelay = 1; -+ for (i = 0; i < sl_params->num_active_dpb_entries; i++) { ++ for (i = 0; i < decode_params->num_active_dpb_entries; i++) { + if (dpb[i].pic_order_cnt[0] > sl_params->slice_pic_order_cnt) { + lowdelay = 0; + break; @@ -3191,6 +3338,7 @@ index 93b4e09e5bf1..8a94fc04980f 100644 WRITE_RPS(sl_params->long_term_ref_pic_set_size + sl_params->short_term_ref_pic_set_size, + From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: Alex Bee Date: Sat, 30 Jan 2021 18:16:39 +0100 @@ -3213,7 +3361,7 @@ Signed-off-by: Alex Bee 2 files changed, 84 insertions(+), 30 deletions(-) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 7419ae7027ab..ab8b42f4f98c 100644 +index da32a6350344..4fb05e8b5a54 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c @@ -14,6 +14,7 @@ @@ -3224,7 +3372,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 #include #include #include -@@ -273,21 +274,6 @@ static const u32 rkvdec_vp9_decoded_fmts[] = { +@@ -269,21 +270,6 @@ static const u32 rkvdec_vp9_decoded_fmts[] = { }; static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { @@ -3246,7 +3394,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 { .fourcc = V4L2_PIX_FMT_HEVC_SLICE, .frmsize = { -@@ -302,6 +288,23 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { +@@ -298,6 +284,23 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { .ops = &rkvdec_hevc_fmt_ops, .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), .decoded_fmts = rkvdec_hevc_decoded_fmts, @@ -3270,7 +3418,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 }, { .fourcc = V4L2_PIX_FMT_VP9_FRAME, -@@ -317,16 +320,31 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { +@@ -313,16 +316,31 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { .ops = &rkvdec_vp9_fmt_ops, .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), .decoded_fmts = rkvdec_vp9_decoded_fmts, @@ -3305,7 +3453,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 return &rkvdec_coded_fmts[i]; } -@@ -349,7 +367,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) +@@ -345,7 +363,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) { struct v4l2_format *f = &ctx->coded_fmt; @@ -3314,7 +3462,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; -@@ -376,11 +394,13 @@ static int rkvdec_enum_framesizes(struct file *file, void *priv, +@@ -372,11 +390,13 @@ static int rkvdec_enum_framesizes(struct file *file, void *priv, struct v4l2_frmsizeenum *fsize) { const struct rkvdec_coded_fmt_desc *fmt; @@ -3329,7 +3477,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 if (!fmt) return -EINVAL; -@@ -451,10 +471,11 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv, +@@ -447,10 +467,11 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv, struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); const struct rkvdec_coded_fmt_desc *desc; @@ -3344,7 +3492,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 } v4l2_apply_frmsize_constraints(&pix_mp->width, -@@ -541,7 +562,8 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, +@@ -537,7 +558,8 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, if (ret) return ret; @@ -3354,7 +3502,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 if (!desc) return -EINVAL; ctx->coded_fmt_desc = desc; -@@ -589,7 +611,10 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv, +@@ -585,7 +607,10 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv, static int rkvdec_enum_output_fmt(struct file *file, void *priv, struct v4l2_fmtdesc *f) { @@ -3366,7 +3514,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 return -EINVAL; f->pixelformat = rkvdec_coded_fmts[f->index].fourcc; -@@ -1040,14 +1065,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx) +@@ -993,14 +1018,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx) int ret; for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) @@ -3388,7 +3536,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 } ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); -@@ -1251,8 +1279,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) +@@ -1204,8 +1232,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) } } @@ -3407,7 +3555,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_rkvdec_match); -@@ -1265,6 +1302,7 @@ static int rkvdec_probe(struct platform_device *pdev) +@@ -1218,6 +1255,7 @@ static int rkvdec_probe(struct platform_device *pdev) { struct rkvdec_dev *rkvdec; struct resource *res; @@ -3415,7 +3563,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 unsigned int i; int ret, irq; -@@ -1290,6 +1328,12 @@ static int rkvdec_probe(struct platform_device *pdev) +@@ -1243,6 +1281,12 @@ static int rkvdec_probe(struct platform_device *pdev) if (ret) return ret; @@ -3429,7 +3577,7 @@ index 7419ae7027ab..ab8b42f4f98c 100644 * Don't bump ACLK to max. possible freq. (500 MHz) to improve performance, * since it will lead to non-recoverable decoder lockups in case of decoding diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 975fe4b5dd68..cc505bc4a042 100644 +index d60840c179a4..ac1e7d053f62 100644 --- a/drivers/staging/media/rkvdec/rkvdec.h +++ b/drivers/staging/media/rkvdec/rkvdec.h @@ -29,6 +29,10 @@ @@ -3443,7 +3591,7 @@ index 975fe4b5dd68..cc505bc4a042 100644 struct rkvdec_ctx; struct rkvdec_ctrl_desc { -@@ -71,6 +75,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) +@@ -70,6 +74,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) base.vb.vb2_buf); } @@ -3454,7 +3602,7 @@ index 975fe4b5dd68..cc505bc4a042 100644 struct rkvdec_coded_fmt_ops { int (*adjust_fmt)(struct rkvdec_ctx *ctx, struct v4l2_format *f); -@@ -90,6 +98,7 @@ struct rkvdec_coded_fmt_desc { +@@ -89,6 +97,7 @@ struct rkvdec_coded_fmt_desc { const struct rkvdec_coded_fmt_ops *ops; unsigned int num_decoded_fmts; const u32 *decoded_fmts; @@ -3462,7 +3610,7 @@ index 975fe4b5dd68..cc505bc4a042 100644 }; struct rkvdec_dev { -@@ -104,6 +113,7 @@ struct rkvdec_dev { +@@ -103,6 +112,7 @@ struct rkvdec_dev { struct delayed_work watchdog_work; struct reset_control *rstc; u8 reset_mask; @@ -3485,10 +3633,10 @@ Signed-off-by: Alex Bee 1 file changed, 8 insertions(+) diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index ab8b42f4f98c..162623567a1d 100644 +index 4fb05e8b5a54..8767b1149009 100644 --- a/drivers/staging/media/rkvdec/rkvdec.c +++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1285,11 +1285,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { +@@ -1238,11 +1238,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { RKVDEC_CAPABILITY_VP9 }; @@ -3520,10 +3668,10 @@ Signed-off-by: Alex Bee 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 746acfac1e92..32e141a3955b 100644 +index 831484253e27..64b36cc8ef94 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1271,6 +1271,25 @@ vpu_mmu: iommu@ff9a0800 { +@@ -1252,6 +1252,25 @@ vpu_mmu: iommu@ff9a0800 { power-domains = <&power RK3288_PD_VIDEO>; }; @@ -3549,7 +3697,7 @@ index 746acfac1e92..32e141a3955b 100644 hevc_mmu: iommu@ff9c0440 { compatible = "rockchip,iommu"; reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; -@@ -1279,7 +1298,7 @@ hevc_mmu: iommu@ff9c0440 { +@@ -1260,7 +1279,7 @@ hevc_mmu: iommu@ff9c0440 { clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; diff --git a/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch b/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch index c74198a69a..c5a382818e 100644 --- a/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch +++ b/projects/Rockchip/patches/linux/default/linux-2002-v4l-wip-iep-driver.patch @@ -109,10 +109,10 @@ Signed-off-by: Alex Bee create mode 100644 drivers/media/platform/rockchip/iep/iep.h diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig -index 7e152bbb4fa6..eee78b20c791 100644 +index 157c924686e4..d77056060c7f 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig -@@ -462,6 +462,20 @@ config VIDEO_RENESAS_VSP1 +@@ -527,6 +527,20 @@ config VIDEO_RENESAS_VSP1 To compile this driver as a module, choose M here: the module will be called vsp1. @@ -134,10 +134,10 @@ index 7e152bbb4fa6..eee78b20c791 100644 tristate "Rockchip Raster 2d Graphic Acceleration Unit" depends on VIDEO_DEV && VIDEO_V4L2 diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile -index 62b6cdc8c730..f99a873818d5 100644 +index 73ce083c2fc6..d1cf1cf99027 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile -@@ -52,6 +52,7 @@ obj-$(CONFIG_VIDEO_RENESAS_FDP1) += rcar_fdp1.o +@@ -54,6 +54,7 @@ obj-$(CONFIG_VIDEO_RENESAS_FDP1) += rcar_fdp1.o obj-$(CONFIG_VIDEO_RENESAS_JPU) += rcar_jpu.o obj-$(CONFIG_VIDEO_RENESAS_VSP1) += vsp1/ @@ -1680,10 +1680,10 @@ Signed-off-by: Alex Bee 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 0e5e492db9c7..f014b87c48f0 100644 +index ca03c8ed9708..ef0d04afc1b1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -771,6 +771,28 @@ vop_mmu: iommu@ff373f00 { +@@ -759,6 +759,28 @@ vop_mmu: iommu@ff373f00 { status = "disabled"; }; @@ -1724,10 +1724,10 @@ Signed-off-by: Alex Bee 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -index b1c7ee80d255..be839c1a7692 100644 +index 27938ff0d208..9adfc422ae90 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi -@@ -1304,6 +1304,17 @@ vdec_mmu: iommu@ff660480 { +@@ -1286,14 +1286,25 @@ vdec_mmu: iommu@ff660480 { #iommu-cells = <0>; }; @@ -1745,8 +1745,7 @@ index b1c7ee80d255..be839c1a7692 100644 iep_mmu: iommu@ff670800 { compatible = "rockchip,iommu"; reg = <0x0 0xff670800 0x0 0x40>; -@@ -1311,8 +1322,8 @@ iep_mmu: iommu@ff670800 { - interrupt-names = "iep_mmu"; + interrupts = ; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_IEP>; @@ -1767,10 +1766,10 @@ Signed-off-by: Alex Bee 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi -index 32e141a3955b..6b1523b38e53 100644 +index 64b36cc8ef94..159c22805d03 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1002,6 +1002,17 @@ crypto: cypto-controller@ff8a0000 { +@@ -983,6 +983,17 @@ crypto: cypto-controller@ff8a0000 { status = "okay"; }; @@ -1788,7 +1787,7 @@ index 32e141a3955b..6b1523b38e53 100644 iep_mmu: iommu@ff900800 { compatible = "rockchip,iommu"; reg = <0x0 0xff900800 0x0 0x40>; -@@ -1009,8 +1020,8 @@ iep_mmu: iommu@ff900800 { +@@ -990,8 +1001,8 @@ iep_mmu: iommu@ff900800 { interrupt-names = "iep_mmu"; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; clock-names = "aclk", "iface";