Allwinner: u-boot: Update patches for 2021.07

This commit is contained in:
Jernej Skrabec 2021-09-11 09:08:19 +02:00 committed by heitbaum
parent 03e61f9216
commit 6427019a9e
23 changed files with 78 additions and 3081 deletions

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@ -536,7 +536,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
#define ARM_PSCI_STACK_SIZE (1 << ARM_PSCI_STACK_SHIFT)
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -549,17 +549,20 @@ void mmu_page_table_flush(unsigned long
@@ -535,17 +535,20 @@ void mmu_page_table_flush(unsigned long
#ifdef CONFIG_ARMV7_PSCI
void psci_arch_cpu_entry(void);
void psci_arch_init(void);

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@ -1,181 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Wed, 18 Nov 2020 17:32:02 +0000
Subject: [PATCH] sunxi: Factor out eGON BROM header description
To be able to easily share the Allwinner eGON BROM header structure
between the tools and the SPL code, move the struct definition into a
separate header file.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/include/asm/arch-sunxi/spl.h | 65 +--------------------
include/sunxi_image.h | 81 +++++++++++++++++++++++++++
2 files changed, 82 insertions(+), 64 deletions(-)
create mode 100644 include/sunxi_image.h
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -7,19 +7,7 @@
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_ARCH_SPL_H_
-#define BOOT0_MAGIC "eGON.BT0"
-#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */
-#define SPL_MAJOR_BITS 3
-#define SPL_MINOR_BITS 5
-#define SPL_VERSION(maj, min) \
- ((((maj) & ((1U << SPL_MAJOR_BITS) - 1)) << SPL_MINOR_BITS) | \
- ((min) & ((1U << SPL_MINOR_BITS) - 1)))
-
-#define SPL_HEADER_VERSION SPL_VERSION(0, 2)
-
-#define SPL_ENV_HEADER_VERSION SPL_VERSION(0, 1)
-#define SPL_DT_HEADER_VERSION SPL_VERSION(0, 2)
-#define SPL_DRAM_HEADER_VERSION SPL_VERSION(0, 3)
+#include <sunxi_image.h>
#define SPL_ADDR CONFIG_SUNXI_SRAM_ADDRESS
@@ -31,57 +19,6 @@
#define SUNXI_BOOTED_FROM_MMC0_HIGH 0x10
#define SUNXI_BOOTED_FROM_MMC2_HIGH 0x12
-/* boot head definition from sun4i boot code */
-struct boot_file_head {
- uint32_t b_instruction; /* one intruction jumping to real code */
- uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */
- uint32_t check_sum; /* generated by PC */
- uint32_t length; /* generated by PC */
- /*
- * We use a simplified header, only filling in what is needed
- * by the boot ROM. To be compatible with Allwinner tools we
- * would need to implement the proper fields here instead of
- * padding.
- *
- * Actually we want the ability to recognize our "sunxi" variant
- * of the SPL. To do so, let's place a special signature into the
- * "pub_head_size" field. We can reasonably expect Allwinner's
- * boot0 to always have the upper 16 bits of this set to 0 (after
- * all the value shouldn't be larger than the limit imposed by
- * SRAM size).
- * If the signature is present (at 0x14), then we know it's safe
- * to use the remaining 8 bytes (at 0x18) for our own purposes.
- * (E.g. sunxi-tools "fel" utility can pass information there.)
- */
- union {
- uint32_t pub_head_size;
- uint8_t spl_signature[4];
- };
- uint32_t fel_script_address; /* since v0.1, set by sunxi-fel */
- /*
- * If the fel_uEnv_length member below is set to a non-zero value,
- * it specifies the size (byte count) of data at fel_script_address.
- * At the same time this indicates that the data is in uEnv.txt
- * compatible format, ready to be imported via "env import -t".
- */
- uint32_t fel_uEnv_length; /* since v0.1, set by sunxi-fel */
- /*
- * Offset of an ASCIIZ string (relative to the SPL header), which
- * contains the default device tree name (CONFIG_DEFAULT_DEVICE_TREE).
- * This is optional and may be set to NULL. Is intended to be used
- * by flash programming tools for providing nice informative messages
- * to the users.
- */
- uint32_t dt_name_offset; /* since v0.2, set by mksunxiboot */
- uint32_t dram_size; /* in MiB, since v0.3, set by SPL */
- uint32_t boot_media; /* written here by the boot ROM */
- /* A padding area (may be used for storing text strings) */
- uint32_t string_pool[13]; /* since v0.2, filled by mksunxiboot */
- /* The header must be a multiple of 32 bytes (for VBAR alignment) */
-};
-
-/* Compile time check to assure proper alignment of structure */
-typedef char boot_file_head_not_multiple_of_32[1 - 2*(sizeof(struct boot_file_head) % 32)];
#define is_boot0_magic(addr) (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0)
--- /dev/null
+++ b/include/sunxi_image.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Constants and data structures used in Allwinner "eGON" images, as
+ * parsed by the Boot-ROM.
+ *
+ * Shared between mkimage and the SPL.
+ */
+#ifndef SUNXI_IMAGE_H
+#define SUNXI_IMAGE_H
+
+#define BOOT0_MAGIC "eGON.BT0"
+#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */
+#define SPL_MAJOR_BITS 3
+#define SPL_MINOR_BITS 5
+#define SPL_VERSION(maj, min) \
+ ((((maj) & ((1U << SPL_MAJOR_BITS) - 1)) << SPL_MINOR_BITS) | \
+ ((min) & ((1U << SPL_MINOR_BITS) - 1)))
+
+#define SPL_HEADER_VERSION SPL_VERSION(0, 2)
+
+#define SPL_ENV_HEADER_VERSION SPL_VERSION(0, 1)
+#define SPL_DT_HEADER_VERSION SPL_VERSION(0, 2)
+#define SPL_DRAM_HEADER_VERSION SPL_VERSION(0, 3)
+
+/* boot head definition from sun4i boot code */
+struct boot_file_head {
+ uint32_t b_instruction; /* one intruction jumping to real code */
+ uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */
+ uint32_t check_sum; /* generated by PC */
+ uint32_t length; /* generated by PC */
+ /*
+ * We use a simplified header, only filling in what is needed
+ * by the boot ROM. To be compatible with Allwinner tools we
+ * would need to implement the proper fields here instead of
+ * padding.
+ *
+ * Actually we want the ability to recognize our "sunxi" variant
+ * of the SPL. To do so, let's place a special signature into the
+ * "pub_head_size" field. We can reasonably expect Allwinner's
+ * boot0 to always have the upper 16 bits of this set to 0 (after
+ * all the value shouldn't be larger than the limit imposed by
+ * SRAM size).
+ * If the signature is present (at 0x14), then we know it's safe
+ * to use the remaining 8 bytes (at 0x18) for our own purposes.
+ * (E.g. sunxi-tools "fel" utility can pass information there.)
+ */
+ union {
+ uint32_t pub_head_size;
+ uint8_t spl_signature[4];
+ };
+ uint32_t fel_script_address; /* since v0.1, set by sunxi-fel */
+ /*
+ * If the fel_uEnv_length member below is set to a non-zero value,
+ * it specifies the size (byte count) of data at fel_script_address.
+ * At the same time this indicates that the data is in uEnv.txt
+ * compatible format, ready to be imported via "env import -t".
+ */
+ uint32_t fel_uEnv_length; /* since v0.1, set by sunxi-fel */
+ /*
+ * Offset of an ASCIIZ string (relative to the SPL header), which
+ * contains the default device tree name (CONFIG_DEFAULT_DEVICE_TREE).
+ * This is optional and may be set to NULL. Is intended to be used
+ * by flash programming tools for providing nice informative messages
+ * to the users.
+ */
+ uint32_t dt_name_offset; /* since v0.2, set by mksunxiboot */
+ uint32_t dram_size; /* in MiB, since v0.3, set by SPL */
+ uint32_t boot_media; /* written here by the boot ROM */
+ /* A padding area (may be used for storing text strings) */
+ uint32_t string_pool[13]; /* since v0.2, filled by mksunxiboot */
+ /* The header must be a multiple of 32 bytes (for VBAR alignment) */
+};
+
+/* Compile time check to assure proper alignment of structure */
+typedef char boot_file_head_not_multiple_of_32[1 - 2*(sizeof(struct boot_file_head) % 32)];
+
+#endif

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@ -20,7 +20,7 @@ Subject: [PATCH] Makefile: Add support for building a sunxi resume shim
# git files that we don't want to ignore even it they are dot-files
--- a/Makefile
+++ b/Makefile
@@ -961,6 +961,21 @@ INPUTS-$(CONFIG_X86) += u-boot-x86-start
@@ -992,6 +992,21 @@ INPUTS-$(CONFIG_X86) += u-boot-x86-start
$(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \
$(if $(CONFIG_TPL_X86_16BIT_INIT),tpl/u-boot-tpl.bin)

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@ -1,202 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Wed, 18 Nov 2020 17:32:03 +0000
Subject: [PATCH] tools: mkimage: Add Allwinner eGON support
So far we used the separate mksunxiboot tool for generating a bootable
image for Allwinner SPLs, probably just for historical reasons.
Use the mkimage framework to generate a so called eGON image the
Allwinner BROM expects.
The new image type is called "sunxi_egon", to differentiate it
from the (still to be implemented) secure boot TOC0 image.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
common/image.c | 1 +
include/image.h | 1 +
include/sunxi_image.h | 1 +
tools/Makefile | 1 +
tools/sunxi_egon.c | 136 ++++++++++++++++++++++++++++++++++++++++++
5 files changed, 140 insertions(+)
create mode 100644 tools/sunxi_egon.c
--- a/common/image.c
+++ b/common/image.c
@@ -189,6 +189,7 @@ static const table_entry_t uimage_type[]
{ IH_TYPE_STM32IMAGE, "stm32image", "STMicroelectronics STM32 Image" },
{ IH_TYPE_MTKIMAGE, "mtk_image", "MediaTek BootROM loadable Image" },
{ IH_TYPE_COPRO, "copro", "Coprocessor Image"},
+ { IH_TYPE_SUNXI_EGON, "sunxi_egon", "Allwinner eGON Boot Image" },
{ -1, "", "", },
};
--- a/include/image.h
+++ b/include/image.h
@@ -308,6 +308,7 @@ enum {
IH_TYPE_IMX8MIMAGE, /* Freescale IMX8MBoot Image */
IH_TYPE_IMX8IMAGE, /* Freescale IMX8Boot Image */
IH_TYPE_COPRO, /* Coprocessor Image for remoteproc*/
+ IH_TYPE_SUNXI_EGON, /* Allwinner eGON Boot Image */
IH_TYPE_COUNT, /* Number of image types */
};
--- a/include/sunxi_image.h
+++ b/include/sunxi_image.h
@@ -13,6 +13,7 @@
#define SUNXI_IMAGE_H
#define BOOT0_MAGIC "eGON.BT0"
+#define BROM_STAMP_VALUE 0x5f0a6c39
#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */
#define SPL_MAJOR_BITS 3
#define SPL_MINOR_BITS 5
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -104,6 +104,7 @@ dumpimage-mkimage-objs := aisimage.o \
stm32image.o \
$(ROCKCHIP_OBS) \
socfpgaimage.o \
+ sunxi_egon.o \
lib/crc16.o \
lib/sha1.o \
lib/sha256.o \
--- /dev/null
+++ b/tools/sunxi_egon.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2018 Arm Ltd.
+ */
+
+#include "imagetool.h"
+#include <image.h>
+
+#include <sunxi_image.h>
+
+/*
+ * NAND requires 8K padding. SD/eMMC gets away with 512 bytes,
+ * but let's use the larger padding to cover both.
+ */
+#define PAD_SIZE 8192
+
+static int egon_check_params(struct image_tool_params *params)
+{
+ /* We just need a binary image file. */
+ return !params->dflag;
+}
+
+static int egon_verify_header(unsigned char *ptr, int image_size,
+ struct image_tool_params *params)
+{
+ const struct boot_file_head *header = (void *)ptr;
+ uint32_t length;
+
+ /* First 4 bytes must be an ARM branch instruction. */
+ if ((le32_to_cpu(header->b_instruction) & 0xff000000) != 0xea000000)
+ return EXIT_FAILURE;
+
+ if (memcmp(header->magic, BOOT0_MAGIC, sizeof(header->magic)))
+ return EXIT_FAILURE;
+
+ length = le32_to_cpu(header->length);
+ /* Must be at least 512 byte aligned. */
+ if (length & 511)
+ return EXIT_FAILURE;
+
+ /*
+ * Image could also contain U-Boot proper, so could be bigger.
+ * But it must not be shorter.
+ */
+ if (image_size < length)
+ return EXIT_FAILURE;
+
+ return EXIT_SUCCESS;
+}
+
+static void egon_print_header(const void *buf)
+{
+ const struct boot_file_head *header = buf;
+
+ printf("Allwinner eGON image, size: %d bytes\n",
+ le32_to_cpu(header->length));
+
+ if (memcmp(header->spl_signature, SPL_SIGNATURE, 3))
+ return;
+
+ printf("\tSPL header version %d.%d\n",
+ header->spl_signature[3] >> SPL_MINOR_BITS,
+ header->spl_signature[3] & ((1U << SPL_MINOR_BITS) - 1));
+ if (header->spl_signature[3] >= SPL_DT_HEADER_VERSION) {
+ uint32_t dt_name_offs = le32_to_cpu(header->dt_name_offset);
+
+ if (dt_name_offs > 0)
+ printf("\tDT name: %s\n", (char *)buf + dt_name_offs);
+ }
+}
+
+static void egon_set_header(void *buf, struct stat *sbuf, int infd,
+ struct image_tool_params *params)
+{
+ struct boot_file_head *header = buf;
+ uint32_t *buf32 = buf;
+ uint32_t checksum = 0, value;
+ int i;
+
+ /* Generate an ARM branch instruction to jump over the header. */
+ value = 0xea000000 | (sizeof(struct boot_file_head) / 4 - 2);
+ header->b_instruction = cpu_to_le32(value);
+
+ memcpy(header->magic, BOOT0_MAGIC, sizeof(header->magic));
+ header->check_sum = cpu_to_le32(BROM_STAMP_VALUE);
+ header->length = cpu_to_le32(params->file_size);
+
+ memcpy(header->spl_signature, SPL_SIGNATURE, 3);
+
+ /* If an image name has been provided, use it as the DT name. */
+ if (params->imagename && params->imagename[0]) {
+ header->spl_signature[3] = SPL_DT_HEADER_VERSION;
+
+ value = offsetof(struct boot_file_head, string_pool);
+ header->dt_name_offset = cpu_to_le32(value);
+
+ strncpy((char *)header->string_pool, params->imagename, 52);
+ /* Make sure we have a terminating zero byte. */
+ ((char *)header->string_pool)[51] = 0;
+ } else
+ header->spl_signature[3] = SPL_ENV_HEADER_VERSION;
+
+ /* Calculate the checksum. Yes, it's that simple. */
+ for (i = 0; i < sbuf->st_size / 4; i++)
+ checksum += le32_to_cpu(buf32[i]);
+ header->check_sum = cpu_to_le32(checksum);
+}
+
+static int egon_check_image_type(uint8_t type)
+{
+ return type == IH_TYPE_SUNXI_EGON ? 0 : 1;
+}
+
+static int egon_vrec_header(struct image_tool_params *params,
+ struct image_type_params *tparams)
+{
+ tparams->hdr = calloc(sizeof(struct boot_file_head), 1);
+
+ /* Return padding to 8K blocks. */
+ return ALIGN(params->file_size, PAD_SIZE) - params->file_size;
+}
+
+U_BOOT_IMAGE_TYPE(
+ sunxi_egon,
+ "Allwinner eGON Boot Image support",
+ sizeof(struct boot_file_head),
+ NULL,
+ egon_check_params,
+ egon_verify_header,
+ egon_print_header,
+ egon_set_header,
+ NULL,
+ egon_check_image_type,
+ NULL,
+ egon_vrec_header
+);

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@ -1,35 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Andre Przywara <andre.przywara@arm.com>
Date: Wed, 18 Nov 2020 17:32:04 +0000
Subject: [PATCH] sunxi: Use mkimage for SPL boot image generation
Switch the SPL boot image generation from using mksunxiboot to the new
sunxi_egon format of mkimage.
Verified to create identical results for all 152 Allwinner boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
---
scripts/Makefile.spl | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -382,11 +382,11 @@ endif
$(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
$(call if_changed,mkimage)
-quiet_cmd_mksunxiboot = MKSUNXI $@
-cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \
- --default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@
+MKIMAGEFLAGS_sunxi-spl.bin = -T sunxi_egon \
+ -n $(CONFIG_DEFAULT_DEVICE_TREE)
+
$(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin FORCE
- $(call if_changed,mksunxiboot)
+ $(call if_changed,mkimage)
quiet_cmd_sunxi_spl_image_builder = SUNXI_SPL_IMAGE_BUILDER $@
cmd_sunxi_spl_image_builder = $(objtree)/tools/sunxi-spl-image-builder \

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@ -10,7 +10,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -30,6 +30,7 @@
@@ -33,6 +33,7 @@
#ifdef CONFIG_ARM64
fit {
description = "Configuration to load ATF before U-Boot";

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@ -1,51 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Fri, 20 Nov 2020 01:26:34 -0600
Subject: [PATCH] sunxi: Put secure monitor in SRAM A2
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/include/asm/arch-sunxi/cpu.h | 9 +++++++++
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 1 -
include/configs/sunxi-common.h | 2 ++
3 files changed, 11 insertions(+), 1 deletion(-)
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -14,6 +14,15 @@
#include <asm/arch/cpu_sun4i.h>
#endif
+#if defined(CONFIG_MACH_SUN4I)
+#define SUNXI_SRAM_A2_BASE 0x00004000
+#elif defined(CONFIG_MACH_SUN6I) || \
+ defined(CONFIG_MACH_SUN8I) || \
+ defined(CONFIG_MACH_SUN50I) || \
+ defined(CONFIG_MACH_SUN50I_H5)
+#define SUNXI_SRAM_A2_BASE 0x00040000
+#endif
+
#define SOCID_A64 0x1689
#define SOCID_H3 0x1680
#define SOCID_V3S 0x1681
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -11,7 +11,6 @@
#define SUNXI_SRAM_A1_BASE 0x00000000
#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */
-#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -192,6 +192,8 @@
#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
+#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_A2_BASE + 0x4000
+#define CONFIG_ARMV7_SECURE_MAX_SIZE (16 * 1024) /* 16 KB */
/* I2C */
#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \

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@ -17,7 +17,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
#ifdef CONFIG_MACH_SUN50I_H6
#define BL31_ADDR 0x104000
#define SCP_ADDR 0x114000
@@ -7,6 +8,9 @@
@@ -9,6 +10,9 @@
#define BL31_ADDR 0x44000
#define SCP_ADDR 0x50000
#endif
@ -27,7 +27,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
/ {
aliases {
@@ -27,6 +31,7 @@
@@ -30,6 +34,7 @@
filename = "spl/sunxi-spl.bin";
};
@ -35,7 +35,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
#ifdef CONFIG_ARM64
fit {
description = "Configuration to load ATF before U-Boot";
@@ -94,6 +99,59 @@
@@ -103,6 +108,59 @@
};
};
#else

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@ -10,7 +10,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -10,6 +10,7 @@
@@ -12,6 +12,7 @@
#endif
#else
#define SCP_ADDR 0x48000
@ -18,7 +18,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
#endif
/ {
@@ -118,6 +119,18 @@
@@ -127,6 +128,18 @@
};
};
@ -37,7 +37,7 @@ Signed-off-by: Samuel Holland <samuel@sholland.org>
scp {
description = "SCP firmware";
type = "firmware";
@@ -145,7 +158,7 @@
@@ -154,7 +167,7 @@
@config-SEQ {
description = "NAME";
firmware = "uboot";

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@ -1,21 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Wed, 18 Nov 2020 23:00:07 -0600
Subject: [PATCH] sunxi: binman: Respect the default FIT configuration
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/sunxi-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -82,7 +82,7 @@
};
configurations {
- default = "config-1";
+ default = "@config-DEFAULT-SEQ";
@config-SEQ {
description = "NAME";

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@ -1,21 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Wed, 18 Nov 2020 23:04:49 -0600
Subject: [PATCH] sunxi: binman: Do not hardcode U-Boot load address
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/sunxi-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -40,7 +40,7 @@
os = "u-boot";
arch = "arm64";
compression = "none";
- load = <0x4a000000>;
+ load = <CONFIG_SYS_TEXT_BASE>;
u-boot-nodtb {
};

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@ -1,185 +0,0 @@
From 4d2be560fe0123536aed35f86184290b0afffccc Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Thu, 1 Oct 2020 19:56:38 +0200
Subject: [PATCH] sunxi: dram: h6: Improve DDR3 config detection
It turns out that in rare cases, current analytical approach to detect
correct DRAM bus width and rank on H6 doesn't work. On some TV boxes
with DDR3, incorrect DRAM configuration triggers write leveling error
which immediately stops initialization process. Exact reason why this
error appears isn't known. However, if correct configuration is used,
initalization works without problem.
In order to fix this issue, simply try another configuration when any
kind of error appears during initialization, not just those related to
rank and bus width.
Tested-by: Thomas Graichen <thomas.graichen@googlemail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
arch/arm/mach-sunxi/dram_sun50i_h6.c | 95 +++++++++++++++-------------
1 file changed, 51 insertions(+), 44 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index 9e34da474798..1cde6132be2c 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -37,9 +37,9 @@
static void mctl_sys_init(struct dram_para *para);
static void mctl_com_init(struct dram_para *para);
-static void mctl_channel_init(struct dram_para *para);
+static bool mctl_channel_init(struct dram_para *para);
-static void mctl_core_init(struct dram_para *para)
+static bool mctl_core_init(struct dram_para *para)
{
mctl_sys_init(para);
mctl_com_init(para);
@@ -51,7 +51,7 @@ static void mctl_core_init(struct dram_para *para)
default:
panic("Unsupported DRAM type!");
};
- mctl_channel_init(para);
+ return mctl_channel_init(para);
}
/* PHY initialisation */
@@ -411,7 +411,7 @@ static void mctl_bit_delay_set(struct dram_para *para)
}
}
-static void mctl_channel_init(struct dram_para *para)
+static bool mctl_channel_init(struct dram_para *para)
{
struct sunxi_mctl_com_reg * const mctl_com =
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
@@ -528,46 +528,15 @@ static void mctl_channel_init(struct dram_para *para)
clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff);
udelay(10);
- if (readl(&mctl_phy->pgsr[0]) & 0x400000)
- {
- /* Check for single rank and optionally half DQ. */
- if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&
- (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) {
- para->ranks = 1;
-
- if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 ||
- (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2)
- para->bus_full_width = 0;
-
- /* Restart DRAM initialization from scratch. */
- mctl_core_init(para);
- return;
- }
-
- /*
- * Check for dual rank and half DQ. NOTE: This combination
- * is highly unlikely and was not tested. Condition is the
- * same as in libdram, though.
- */
- if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 &&
- (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) {
- para->bus_full_width = 0;
-
- /* Restart DRAM initialization from scratch. */
- mctl_core_init(para);
- return;
- }
-
- panic("This DRAM setup is currently not supported.\n");
- }
-
if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {
/* Oops! There's something wrong! */
debug("PLL = %x\n", readl(0x3001010));
debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0]));
for (i = 0; i < 4; i++)
debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0]));
- panic("Error while initializing DRAM PHY!\n");
+ debug("Error while initializing DRAM PHY!\n");
+
+ return false;
}
if (sunxi_dram_is_lpddr(para->type))
@@ -582,13 +551,54 @@ static void mctl_channel_init(struct dram_para *para)
writel(0xffffffff, &mctl_com->maer0);
writel(0x7ff, &mctl_com->maer1);
writel(0xffff, &mctl_com->maer2);
+
+ return true;
+}
+
+static void mctl_auto_detect_rank_width(struct dram_para *para)
+{
+ /* this is minimum size that it's supported */
+ para->cols = 8;
+ para->rows = 13;
+
+ /*
+ * Strategy here is to test most demanding combination first and least
+ * demanding last, otherwise HW might not be fully utilized. For
+ * example, half bus width and rank = 1 combination would also work
+ * on HW with full bus width and rank = 2, but only 1/4 RAM would be
+ * visible.
+ */
+
+ debug("testing 32-bit width, rank = 2\n");
+ para->bus_full_width = 1;
+ para->ranks = 2;
+ if (mctl_core_init(para))
+ return;
+
+ debug("testing 32-bit width, rank = 1\n");
+ para->bus_full_width = 1;
+ para->ranks = 1;
+ if (mctl_core_init(para))
+ return;
+
+ debug("testing 16-bit width, rank = 2\n");
+ para->bus_full_width = 0;
+ para->ranks = 2;
+ if (mctl_core_init(para))
+ return;
+
+ debug("testing 16-bit width, rank = 1\n");
+ para->bus_full_width = 0;
+ para->ranks = 1;
+ if (mctl_core_init(para))
+ return;
+
+ panic("This DRAM setup is currently not supported.\n");
}
static void mctl_auto_detect_dram_size(struct dram_para *para)
{
/* TODO: non-(LP)DDR3 */
- /* Detect rank number and half DQ by the code in mctl_channel_init. */
- mctl_core_init(para);
/* detect row address bits */
para->cols = 8;
@@ -652,10 +662,6 @@ unsigned long sunxi_dram_init(void)
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
struct dram_para para = {
.clk = CONFIG_DRAM_CLK,
- .ranks = 2,
- .cols = 11,
- .rows = 14,
- .bus_full_width = 1,
#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
.type = SUNXI_DRAM_TYPE_LPDDR3,
.dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
@@ -673,6 +679,7 @@ unsigned long sunxi_dram_init(void)
setbits_le32(0x7010310, BIT(8));
clrbits_le32(0x7010318, 0x3f);
+ mctl_auto_detect_rank_width(&para);
mctl_auto_detect_dram_size(&para);
mctl_core_init(&para);
--
2.29.2

View File

@ -1,201 +0,0 @@
From 6edd6f3d8ee26d37a557a890fa75e0840c6273db Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Sun, 3 Jan 2021 10:50:27 +0100
Subject: [PATCH v3 2/2] sunxi: Add support for Tanix TX6
This commit adds support for Tanix TX6 TV box, based on H6. It's low end
H6 board, with 3 GiB of RAM, eMMC, fast ethernet, USB, IR and other
peripherals.
DT file is taken from Linux 5.11-rc1 release.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/sun50i-h6-tanix-tx6.dts | 124 +++++++++++++++++++++++++++
board/sunxi/MAINTAINERS | 6 ++
configs/tanix_tx6_defconfig | 10 +++
4 files changed, 142 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/sun50i-h6-tanix-tx6.dts
create mode 100644 configs/tanix_tx6_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fd47e408f826..e00aed1ec207 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -607,7 +607,8 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-beelink-gs1.dtb \
sun50i-h6-orangepi-lite2.dtb \
sun50i-h6-orangepi-one-plus.dtb \
- sun50i-h6-pine-h64.dtb
+ sun50i-h6-pine-h64.dtb \
+ sun50i-h6-tanix-tx6.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-amarula-relic.dtb \
sun50i-a64-bananapi-m64.dtb \
diff --git a/arch/arm/dts/sun50i-h6-tanix-tx6.dts b/arch/arm/dts/sun50i-h6-tanix-tx6.dts
new file mode 100644
index 000000000000..be81330db14f
--- /dev/null
+++ b/arch/arm/dts/sun50i-h6-tanix-tx6.dts
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Tanix TX6";
+ compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_vdd_cpu_gpu: vdd-cpu-gpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu-gpu";
+ regulator-min-microvolt = <1135000>;
+ regulator-max-microvolt = <1135000>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_vdd_cpu_gpu>;
+};
+
+&de {
+ status = "okay";
+};
+
+&dwc3 {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&reg_vdd_cpu_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&r_ir {
+ linux,rc-map-name = "rc-tanix-tx5max";
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
+
+&usb2otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb2phy {
+ status = "okay";
+};
+
+&usb3phy {
+ status = "okay";
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index d3755ae41a9d..1b37a9899edd 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -489,6 +489,12 @@ S: Maintained
F: configs/Sunchip_CX-A99_defconfig
W: https://linux-sunxi.org/Sunchip_CX-A99
+TANIX TX6 BOARD
+M: Jernej Skrabec <jernej.skrabec@siol.net>
+S: Maintained
+F: configs/tanix_tx6_defconfig
+W: https://linux-sunxi.org/Tanix_TX6
+
TBS A711 BOARD
M: Maxime Ripard <mripard@kernel.org>
S: Maintained
diff --git a/configs/tanix_tx6_defconfig b/configs/tanix_tx6_defconfig
new file mode 100644
index 000000000000..9ce812ecc35d
--- /dev/null
+++ b/configs/tanix_tx6_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I_H6=y
+CONFIG_SUNXI_DRAM_H6_DDR3_1333=y
+CONFIG_DRAM_CLK=648
+CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-tanix-tx6"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
--
2.30.0

View File

@ -1,159 +0,0 @@
From a0770d90e89c03115eaf1c22d74b955f37b8ddbd Mon Sep 17 00:00:00 2001
From: Andre Heider <a.heider@gmail.com>
Date: Tue, 26 Nov 2019 12:38:46 +0100
Subject: [PATCH 1/3] sunxi: board: extract creating a unique sid into a helper
function
Refactor setup_environment() so we can use the created sid for a
Bluetooth address too.
Signed-off-by: Andre Heider <a.heider@gmail.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
[rebased]
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
board/sunxi/board.c | 121 ++++++++++++++++++++++++--------------------
1 file changed, 66 insertions(+), 55 deletions(-)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 708a27ed78e9..4a29e351141b 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -789,6 +789,38 @@ static void parse_spl_header(const uint32_t spl_addr)
env_set_hex("fel_scriptaddr", spl->fel_script_address);
}
+static bool get_unique_sid(unsigned int *sid)
+{
+ if (sunxi_get_sid(sid) != 0)
+ return false;
+
+ if (!sid[0])
+ return false;
+
+ /*
+ * The single words 1 - 3 of the SID have quite a few bits
+ * which are the same on many models, so we take a crc32
+ * of all 3 words, to get a more unique value.
+ *
+ * Note we only do this on newer SoCs as we cannot change
+ * the algorithm on older SoCs since those have been using
+ * fixed mac-addresses based on only using word 3 for a
+ * long time and changing a fixed mac-address with an
+ * u-boot update is not good.
+ */
+#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
+ !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
+ !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
+ sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
+#endif
+
+ /* Ensure the NIC specific bytes of the mac are not all 0 */
+ if ((sid[3] & 0xffffff) == 0)
+ sid[3] |= 0x800000;
+
+ return true;
+}
+
/*
* Note this function gets called multiple times.
* It must not make any changes to env variables which already exist.
@@ -799,61 +831,40 @@ static void setup_environment(const void *fdt)
unsigned int sid[4];
uint8_t mac_addr[6];
char ethaddr[16];
- int i, ret;
-
- ret = sunxi_get_sid(sid);
- if (ret == 0 && sid[0] != 0) {
- /*
- * The single words 1 - 3 of the SID have quite a few bits
- * which are the same on many models, so we take a crc32
- * of all 3 words, to get a more unique value.
- *
- * Note we only do this on newer SoCs as we cannot change
- * the algorithm on older SoCs since those have been using
- * fixed mac-addresses based on only using word 3 for a
- * long time and changing a fixed mac-address with an
- * u-boot update is not good.
- */
-#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
- !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
- !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
- sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
-#endif
-
- /* Ensure the NIC specific bytes of the mac are not all 0 */
- if ((sid[3] & 0xffffff) == 0)
- sid[3] |= 0x800000;
-
- for (i = 0; i < 4; i++) {
- sprintf(ethaddr, "ethernet%d", i);
- if (!fdt_get_alias(fdt, ethaddr))
- continue;
-
- if (i == 0)
- strcpy(ethaddr, "ethaddr");
- else
- sprintf(ethaddr, "eth%daddr", i);
-
- if (env_get(ethaddr))
- continue;
-
- /* Non OUI / registered MAC address */
- mac_addr[0] = (i << 4) | 0x02;
- mac_addr[1] = (sid[0] >> 0) & 0xff;
- mac_addr[2] = (sid[3] >> 24) & 0xff;
- mac_addr[3] = (sid[3] >> 16) & 0xff;
- mac_addr[4] = (sid[3] >> 8) & 0xff;
- mac_addr[5] = (sid[3] >> 0) & 0xff;
-
- eth_env_set_enetaddr(ethaddr, mac_addr);
- }
-
- if (!env_get("serial#")) {
- snprintf(serial_string, sizeof(serial_string),
- "%08x%08x", sid[0], sid[3]);
-
- env_set("serial#", serial_string);
- }
+ int i;
+
+ if (!get_unique_sid(sid))
+ return;
+
+ for (i = 0; i < 4; i++) {
+ sprintf(ethaddr, "ethernet%d", i);
+ if (!fdt_get_alias(fdt, ethaddr))
+ continue;
+
+ if (i == 0)
+ strcpy(ethaddr, "ethaddr");
+ else
+ sprintf(ethaddr, "eth%daddr", i);
+
+ if (env_get(ethaddr))
+ continue;
+
+ /* Non OUI / registered MAC address */
+ mac_addr[0] = (i << 4) | 0x02;
+ mac_addr[1] = (sid[0] >> 0) & 0xff;
+ mac_addr[2] = (sid[3] >> 24) & 0xff;
+ mac_addr[3] = (sid[3] >> 16) & 0xff;
+ mac_addr[4] = (sid[3] >> 8) & 0xff;
+ mac_addr[5] = (sid[3] >> 0) & 0xff;
+
+ eth_env_set_enetaddr(ethaddr, mac_addr);
+ }
+
+ if (!env_get("serial#")) {
+ snprintf(serial_string, sizeof(serial_string),
+ "%08x%08x", sid[0], sid[3]);
+
+ env_set("serial#", serial_string);
}
}
--
2.30.0

View File

@ -1,96 +0,0 @@
From c8216074411efbc484d2e308451477fa9f4e342c Mon Sep 17 00:00:00 2001
From: Andre Heider <a.heider@gmail.com>
Date: Sun, 17 Nov 2019 20:24:43 +0100
Subject: [PATCH 2/3] arm: sunxi: add a config option to fixup a Bluetooth
address
Some Bluetooth controllers, like the BCM4345C5 of the Orange Pi 3,
ship with the controller default address.
Add a config option to fix it up so it can function properly.
Signed-off-by: Andre Heider <a.heider@gmail.com>
Tested-by: Ondrej Jirman <megous@megous.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
[rebased]
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
arch/arm/mach-sunxi/Kconfig | 11 +++++++++++
board/sunxi/board.c | 34 ++++++++++++++++++++++++++++++++++
2 files changed, 45 insertions(+)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 49ef217f08c0..269aef5f01a1 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1016,4 +1016,15 @@ config PINEPHONE_DT_SELECTION
Enable this option to automatically select the device tree for the
correct PinePhone hardware revision during boot.
+config FIXUP_BDADDR
+ string "Fixup the Bluetooth controller address"
+ default ""
+ help
+ This option specifies the DT compatible name of the Bluetooth
+ controller for which to set the "local-bd-address" property.
+ Set this option if your device ships with the Bluetooth controller
+ default address.
+ The used address is "bdaddr" if set, and "ethaddr" with the LSB
+ flipped elsewise.
+
endif
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 4a29e351141b..d19119b7eb36 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -908,6 +908,38 @@ int misc_init_r(void)
return 0;
}
+static void fixup_bd_address(void *blob)
+{
+ /* Some devices ship with a Bluetooth controller default address.
+ * Set a valid address through the device tree.
+ */
+ uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
+ unsigned int sid[4];
+ int i;
+
+ if (!CONFIG_FIXUP_BDADDR[0])
+ return;
+
+ if (eth_env_get_enetaddr("bdaddr", tmp)) {
+ /* Convert between the binary formats of the corresponding stacks */
+ for (i = 0; i < ETH_ALEN; ++i)
+ bdaddr[i] = tmp[ETH_ALEN - i - 1];
+ } else {
+ if (!get_unique_sid(sid))
+ return;
+
+ bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1;
+ bdaddr[1] = (sid[3] >> 8) & 0xff;
+ bdaddr[2] = (sid[3] >> 16) & 0xff;
+ bdaddr[3] = (sid[3] >> 24) & 0xff;
+ bdaddr[4] = (sid[0] >> 0) & 0xff;
+ bdaddr[5] = 0x02;
+ }
+
+ do_fixup_by_compat(blob, CONFIG_FIXUP_BDADDR,
+ "local-bd-address", bdaddr, ETH_ALEN, 1);
+}
+
int ft_board_setup(void *blob, struct bd_info *bd)
{
int __maybe_unused r;
@@ -918,6 +950,8 @@ int ft_board_setup(void *blob, struct bd_info *bd)
*/
setup_environment(blob);
+ fixup_bd_address(blob);
+
#ifdef CONFIG_VIDEO_DT_SIMPLEFB
r = sunxi_simplefb_setup(blob);
if (r)
--
2.30.0

View File

@ -1,424 +0,0 @@
From ebbb185d268f795de19aa4d2934531ec61a8ed84 Mon Sep 17 00:00:00 2001
From: Andre Heider <a.heider@gmail.com>
Date: Mon, 18 Nov 2019 09:54:43 +0100
Subject: [PATCH 3/3] arm64: dts: sun50i: Add support for Orange Pi 3
dts file is taken from Linux 5.11-rc1 tag.
The Bluetooth controller of this device ships with a default address,
use the new CONFIG_FIXUP_BDADDR option to fix it up.
Signed-off-by: Andre Heider <a.heider@gmail.com>
Acked-by: Maxime Ripard <mripard@kernel.org>
[Updated OrangePi 3 DT, rebase and config update]
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun50i-h6-orangepi-3.dts | 345 ++++++++++++++++++++++++++
board/sunxi/MAINTAINERS | 5 +
configs/orangepi_3_defconfig | 13 +
4 files changed, 364 insertions(+)
create mode 100644 arch/arm/dts/sun50i-h6-orangepi-3.dts
create mode 100644 configs/orangepi_3_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e00aed1ec207..607571d04b25 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -605,6 +605,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-beelink-gs1.dtb \
+ sun50i-h6-orangepi-3.dtb \
sun50i-h6-orangepi-lite2.dtb \
sun50i-h6-orangepi-one-plus.dtb \
sun50i-h6-pine-h64.dtb \
diff --git a/arch/arm/dts/sun50i-h6-orangepi-3.dts b/arch/arm/dts/sun50i-h6-orangepi-3.dts
new file mode 100644
index 000000000000..15c9dd8c4479
--- /dev/null
+++ b/arch/arm/dts/sun50i-h6-orangepi-3.dts
@@ -0,0 +1,345 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2019 Ondřej Jirman <megous@megous.com>
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "OrangePi 3";
+ compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ power {
+ label = "orangepi:red:power";
+ gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ default-state = "on";
+ };
+
+ status {
+ label = "orangepi:green:status";
+ gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
+ };
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the DC jack */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ reg_vcc33_wifi: vcc33-wifi {
+ /* Always on 3.3V regulator for WiFi and BT */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc33-wifi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&reg_vcc5v>;
+ };
+
+ reg_vcc_wifi_io: vcc-wifi-io {
+ /* Always on 1.8V/300mA regulator for WiFi and BT IO */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-wifi-io";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ vin-supply = <&reg_vcc33_wifi>;
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rtc 1>;
+ clock-names = "ext_clock";
+ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_dcdca>;
+};
+
+&de {
+ status = "okay";
+};
+
+&dwc3 {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&reg_dcdcc>;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <&reg_cldo1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc33_wifi>;
+ vqmmc-supply = <&reg_vcc_wifi_io>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ brcm: sdio-wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&r_pio>;
+ interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ vmmc-supply = <&reg_cldo1>;
+ vqmmc-supply = <&reg_bldo2>;
+ cap-mmc-hw-reset;
+ non-removable;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pc-supply = <&reg_bldo2>;
+ vcc-pd-supply = <&reg_cldo1>;
+ vcc-pg-supply = <&reg_vcc_wifi_io>;
+};
+
+&r_i2c {
+ status = "okay";
+
+ axp805: pmic@36 {
+ compatible = "x-powers,axp805", "x-powers,axp806";
+ reg = <0x36>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ x-powers,self-working-mode;
+ vina-supply = <&reg_vcc5v>;
+ vinb-supply = <&reg_vcc5v>;
+ vinc-supply = <&reg_vcc5v>;
+ vind-supply = <&reg_vcc5v>;
+ vine-supply = <&reg_vcc5v>;
+ aldoin-supply = <&reg_vcc5v>;
+ bldoin-supply = <&reg_vcc5v>;
+ cldoin-supply = <&reg_vcc5v>;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl-led-ir";
+ };
+
+ reg_aldo2: aldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33-audio-tv-ephy-mac";
+ };
+
+ /* ALDO3 is shorted to CLDO1 */
+ reg_aldo3: aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1";
+ };
+
+ reg_bldo1: bldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18-dram-bias-pll";
+ };
+
+ reg_bldo2: bldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-efuse-pcie-hdmi-pc";
+ };
+
+ bldo3 {
+ /* unused */
+ };
+
+ bldo4 {
+ /* unused */
+ };
+
+ reg_cldo1: cldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2";
+ };
+
+ cldo2 {
+ /* unused */
+ };
+
+ cldo3 {
+ /* unused */
+ };
+
+ reg_dcdca: dcdca {
+ regulator-always-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1160000>;
+ regulator-ramp-delay = <2500>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdcc: dcdcc {
+ regulator-enable-ramp-delay = <32000>;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-ramp-delay = <2500>;
+ regulator-name = "vdd-gpu";
+ };
+
+ reg_dcdcd: dcdcd {
+ regulator-always-on;
+ regulator-min-microvolt = <960000>;
+ regulator-max-microvolt = <960000>;
+ regulator-name = "vdd-sys";
+ };
+
+ reg_dcdce: dcdce {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-dram";
+ };
+
+ sw {
+ /* unused */
+ };
+ };
+ };
+};
+
+&r_ir {
+ status = "okay";
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
+
+/* There's the BT part of the AP6256 connected to that UART */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ clocks = <&rtc 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */
+ host-wakeup-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */
+ shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */
+ max-speed = <1500000>;
+ };
+};
+
+&usb2otg {
+ /*
+ * This board doesn't have a controllable VBUS even though it
+ * does have an ID pin. Using it as anything but a USB host is
+ * unsafe.
+ */
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb2phy {
+ usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
+ usb0_vbus-supply = <&reg_vcc5v>;
+ usb3_vbus-supply = <&reg_vcc5v>;
+ status = "okay";
+};
+
+&usb3phy {
+ status = "okay";
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 1b37a9899edd..95b4df83e0a9 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -385,6 +385,11 @@ M: Icenowy Zheng <icenowy@aosc.io>
S: Maintained
F: configs/teres_i_defconfig
+ORANGEPI 3 BOARD
+M: Andre Heider <a.heider@gmail.com>
+S: Maintained
+F: configs/orangepi_3_defconfig
+
ORANGEPI LITE2 BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
diff --git a/configs/orangepi_3_defconfig b/configs/orangepi_3_defconfig
new file mode 100644
index 000000000000..6a4a11739213
--- /dev/null
+++ b/configs/orangepi_3_defconfig
@@ -0,0 +1,13 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I_H6=y
+CONFIG_SUNXI_DRAM_H6_LPDDR3=y
+CONFIG_MMC0_CD_PIN="PF6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_FIXUP_BDADDR="brcm,bcm4345c5"
+# CONFIG_PSCI_RESET is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-orangepi-3"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
--
2.30.0

View File

@ -1,40 +0,0 @@
From: megous@megous.com
Date: Mon, 29 Jul 2019 01:39:42 +0200
Subject: [U-Boot] [PATCH] Fix unreliable detection of DRAM size on Orange Pi 3
From: Ondrej Jirman <megous@megous.com>
Orange Pi 3 has 2 GiB of DRAM, that sometime get misdetected
as 4 GiB, due to false negative result from mctl_mem_matches()
when detecting number of column address bits. This leads to
u-boot detecting more address bits than there are and the
boot process hangs shortly after.
In mctl_mem_matches() we need to wait for each write to finish,
separately. Without this, the check is not reliable for some
unknown reason, probably having to do with unpredictable memory
access ordering.
Patch was made with help from André Przywara, who noticed that
my original idea about detection failing due to read-back from
cache without involving DRAM was false, because data cache is
still of at the time of the DRAM size autodetection.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Cc: André Przywara <andre.przywara@arm.com>
---
arch/arm/mach-sunxi/dram_helpers.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c
index 239ab421a8..6dba448638 100644
--- a/arch/arm/mach-sunxi/dram_helpers.c
+++ b/arch/arm/mach-sunxi/dram_helpers.c
@@ -30,6 +30,7 @@ bool mctl_mem_matches(u32 offset)
{
/* Try to write different values to RAM at two addresses */
writel(0, CONFIG_SYS_SDRAM_BASE);
+ dsb();
writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
dsb();
/* Check if the same value is actually observed when reading back */

View File

@ -1,4 +1,4 @@
From 06860479d1bfd84037f29236511d5945e5193c85 Mon Sep 17 00:00:00 2001
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jernej Skrabec <jernej.skrabec@siol.net>
Date: Sun, 8 Mar 2020 08:08:03 +0100
Subject: [PATCH] OrangePi PC2: Update defaults
@ -7,11 +7,9 @@ Subject: [PATCH] OrangePi PC2: Update defaults
configs/orangepi_pc2_defconfig | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig
index 3d65b87d33..1ffeeed6cd 100644
--- a/configs/orangepi_pc2_defconfig
+++ b/configs/orangepi_pc2_defconfig
@@ -3,12 +3,14 @@ CONFIG_SPL=y
@@ -5,11 +5,13 @@ CONFIG_SPL=y
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
@ -19,7 +17,6 @@ index 3d65b87d33..1ffeeed6cd 100644
CONFIG_MACPWR="PD6"
CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SPL_I2C_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-orangepi-pc2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SUN8I_EMAC=y
+CONFIG_SY8106A_POWER=y
@ -27,6 +24,3 @@ index 3d65b87d33..1ffeeed6cd 100644
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_MUSB_GADGET=y
--
2.25.1

View File

@ -0,0 +1,63 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sun, 18 Apr 2021 22:21:41 -0500
Subject: [PATCH] sunxi: A23/A33/H3: Move sun8i secure monitor to SRAM A2
So far for the H3, A23, and A33 SoCs, we use DRAM to hold the secure
monitor code (providing PSCI runtime services). And while those SoCs do
not have the secure SRAM B like older SoCs, there is enough (secure)
SRAM A2 to put the monitor code and data in there instead.
Follow the design of 64-bit SoCs and use the first part for the monitor,
and the last 16 KiB for the SCP firmware. With this change, the monitor
no longer needs to reserve a region in DRAM.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
[Andre: amend commit message, fix R40 and V3s build]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 11 +++++++++++
include/configs/sun8i.h | 10 ++++++++++
2 files changed, 21 insertions(+)
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -11,7 +11,18 @@
#define SUNXI_SRAM_A1_BASE 0x00000000
#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */
+#if defined(CONFIG_SUNXI_GEN_SUN6I) && \
+ !defined(CONFIG_MACH_SUN8I_R40) && \
+ !defined(CONFIG_MACH_SUN8I_V3S)
+#define SUNXI_SRAM_A2_BASE 0x00040000
+#ifdef CONFIG_MACH_SUN8I_H3
+#define SUNXI_SRAM_A2_SIZE (48 * 1024) /* 16+32 kiB */
+#else
+#define SUNXI_SRAM_A2_SIZE (80 * 1024) /* 16+64 kiB */
+#endif
+#else
#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
+#endif
#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -12,6 +12,16 @@
* A23 specific configuration
*/
+#ifdef SUNXI_SRAM_A2_SIZE
+/*
+ * If the SoC has enough SRAM A2, use that for the secure monitor.
+ * Skip the first 16 KiB of SRAM A2, which is not usable, as only certain bytes
+ * are writable. Reserve the last 17 KiB for the resume shim and SCP firmware.
+ */
+#define CONFIG_ARMV7_SECURE_BASE (SUNXI_SRAM_A2_BASE + 16 * 1024)
+#define CONFIG_ARMV7_SECURE_MAX_SIZE (SUNXI_SRAM_A2_SIZE - 33 * 1024)
+#endif
+
/*
* Include common sunxi configuration where most the settings are
*/

View File

@ -1,65 +0,0 @@
From: Andre Przywara <andre.przywara@arm.com>
Subject: [PATCH] sunxi: Properly check for SATAPWR and MACPWR
Date: Tue, 19 Jan 2021 01:05:20 +0000
The #ifdef CONFIG_xxxPWR conditionals were not working as expected, as
string Kconfig symbols are always "defined" from the preprocessor's
perspective. This lead to unnecessary calls to the GPIO routines, but
also always added a half a second delay to wait for a SATA disk to power
up. Many thanks to Peter for pointing this out!
Fix this by properly comparing the Kconfig symbols against the empty
string. strcmp() would be nicer for this, but GCC does not optimise this
away, probably due to our standalone compiler switches.
Reported-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi WinPlus
Tested-by: Peter Robinson <pbrobinson@gmail.com>
---
board/sunxi/board.c | 34 ++++++++++++++++++++++------------
1 file changed, 22 insertions(+), 12 deletions(-)
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -264,18 +264,28 @@ int board_init(void)
if (ret)
return ret;
-#ifdef CONFIG_SATAPWR
- satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
- gpio_request(satapwr_pin, "satapwr");
- gpio_direction_output(satapwr_pin, 1);
- /* Give attached sata device time to power-up to avoid link timeouts */
- mdelay(500);
-#endif
-#ifdef CONFIG_MACPWR
- macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
- gpio_request(macpwr_pin, "macpwr");
- gpio_direction_output(macpwr_pin, 1);
-#endif
+ /* strcmp() would look better, but doesn't get optimised away. */
+ if (CONFIG_SATAPWR[0]) {
+ satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
+ if (satapwr_pin >= 0) {
+ gpio_request(satapwr_pin, "satapwr");
+ gpio_direction_output(satapwr_pin, 1);
+
+ /*
+ * Give the attached SATA device time to power-up
+ * to avoid link timeouts
+ */
+ mdelay(500);
+ }
+ }
+
+ if (CONFIG_MACPWR[0]) {
+ macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
+ if (macpwr_pin >= 0) {
+ gpio_request(macpwr_pin, "macpwr");
+ gpio_direction_output(macpwr_pin, 1);
+ }
+ }
#ifdef CONFIG_DM_I2C
/*

View File

@ -1,4 +1,4 @@
From 55d3cc28b37000d1a3d7224c0ba4a808274e0b33 Mon Sep 17 00:00:00 2001
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Fri, 27 Oct 2017 17:25:00 +0800
Subject: [PATCH 20/20] sunxi: call fdt_fixup_ethernet again to set macaddr for
@ -18,11 +18,9 @@ Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
board/sunxi/board.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 192cf8ca45..0fe70f47cb 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -751,10 +751,12 @@ int ft_board_setup(void *blob, bd_t *bd)
@@ -970,10 +970,12 @@ int ft_board_setup(void *blob, struct bd
int __maybe_unused r;
/*
@ -35,8 +33,5 @@ index 192cf8ca45..0fe70f47cb 100644
setup_environment(blob);
+ fdt_fixup_ethernet(blob);
#ifdef CONFIG_VIDEO_DT_SIMPLEFB
r = sunxi_simplefb_setup(blob);
--
2.13.6
bluetooth_dt_fixup(blob);