mirror of
https://github.com/LibreELEC/LibreELEC.tv.git
synced 2025-07-24 11:16:51 +00:00
flashrom: downgrade to flashrom-1061
Signed-off-by: Stephan Raue <stephan@openelec.tv>
This commit is contained in:
Stephan Raue
parent
4aaf5ef6e4
commit
670b178850
@ -1,5 +1,5 @@
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PKG_NAME="flashrom"
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PKG_VERSION="1114"
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PKG_VERSION="1061"
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PKG_REV="1"
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PKG_ARCH="any"
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PKG_LICENSE="GPL"
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@ -0,0 +1,467 @@
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diff -Naur flashrom-1061/bitbang_spi.c flashrom-1061.patch/bitbang_spi.c
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--- flashrom-1061/bitbang_spi.c 2010-06-27 14:12:28.000000000 +0200
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+++ flashrom-1061.patch/bitbang_spi.c 2010-06-27 14:16:51.108934759 +0200
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@@ -26,17 +26,29 @@
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#include "chipdrivers.h"
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#include "spi.h"
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-/* Length of half a clock period in usecs */
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-int bitbang_spi_half_period = 0;
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+/* Length of half a clock period in usecs. Default to 1 (500 kHz). */
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+int bitbang_spi_half_period = 1;
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enum bitbang_spi_master bitbang_spi_master = BITBANG_SPI_INVALID;
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const struct bitbang_spi_master_entry bitbang_spi_master_table[] = {
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+#if CONFIG_INTERNAL == 1
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+#if defined(__i386__) || defined(__x86_64__)
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+ {
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+ .set_cs = mcp6x_bitbang_set_cs,
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+ .set_sck = mcp6x_bitbang_set_sck,
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+ .set_mosi = mcp6x_bitbang_set_mosi,
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+ .get_miso = mcp6x_bitbang_get_miso,
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+ },
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+#endif
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+#endif
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+
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{}, /* This entry corresponds to BITBANG_SPI_INVALID. */
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};
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const int bitbang_spi_master_count = ARRAY_SIZE(bitbang_spi_master_table);
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+/* Note that CS# is active low, so val=0 means the chip is active. */
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void bitbang_spi_set_cs(int val)
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{
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bitbang_spi_master_table[bitbang_spi_master].set_cs(val);
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@@ -57,10 +69,18 @@
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return bitbang_spi_master_table[bitbang_spi_master].get_miso();
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}
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-int bitbang_spi_init(void)
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+int bitbang_spi_init(enum bitbang_spi_master master)
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{
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+ bitbang_spi_master = master;
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+
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+ if (bitbang_spi_master == BITBANG_SPI_INVALID) {
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+ msg_perr("Invalid bitbang SPI master. \n"
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+ "Please report a bug at flashrom@flashrom.org\n");
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+ return 1;
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+ }
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bitbang_spi_set_cs(1);
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bitbang_spi_set_sck(0);
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+ bitbang_spi_set_mosi(0);
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buses_supported = CHIP_BUSTYPE_SPI;
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return 0;
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}
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@@ -87,6 +107,7 @@
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{
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static unsigned char *bufout = NULL;
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static unsigned char *bufin = NULL;
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+ unsigned char *tmp;
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static int oldbufsize = 0;
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int bufsize;
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int i;
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@@ -98,20 +119,34 @@
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bufsize = max(writecnt + readcnt, 260);
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/* Never shrink. realloc() calls are expensive. */
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if (bufsize > oldbufsize) {
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- bufout = realloc(bufout, bufsize);
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- if (!bufout) {
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+ tmp = realloc(bufout, bufsize);
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+ if (!tmp) {
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msg_perr("Out of memory!\n");
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+ if (bufout)
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+ free(bufout);
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+ bufout = NULL;
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if (bufin)
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free(bufin);
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+ bufin = NULL;
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+ oldbufsize = 0;
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exit(1);
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- }
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- bufin = realloc(bufout, bufsize);
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- if (!bufin) {
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+ } else
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+ bufout = tmp;
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+
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+ tmp = realloc(bufin, bufsize);
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+ if (!tmp) {
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msg_perr("Out of memory!\n");
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+ if (bufin)
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+ free(bufin);
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+ bufin = NULL;
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if (bufout)
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free(bufout);
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+ bufout = NULL;
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+ oldbufsize = 0;
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exit(1);
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- }
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+ } else
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+ bufin = tmp;
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+
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oldbufsize = bufsize;
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}
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@@ -135,8 +170,13 @@
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int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len)
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{
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- /* Maximum read length is unlimited, use 64k bytes. */
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- return spi_read_chunked(flash, buf, start, len, 64 * 1024);
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+ /* Maximum read length is unlimited in theory.
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+ * The current implementation can handle reads of up to 65536 bytes.
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+ * Please note that you need two buffers of 2n+4 bytes each for a read
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+ * of n bytes, resulting in a total memory requirement of 4n+8 bytes.
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+ * To conserve memory, read in chunks of 256 bytes.
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+ */
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+ return spi_read_chunked(flash, buf, start, len, 256);
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}
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int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf)
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diff -Naur flashrom-1061/chipset_enable.c flashrom-1061.patch/chipset_enable.c
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--- flashrom-1061/chipset_enable.c 2010-06-27 14:12:28.000000000 +0200
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+++ flashrom-1061.patch/chipset_enable.c 2010-06-27 14:16:51.111932537 +0200
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@@ -1092,10 +1092,8 @@
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{
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int ret = 0;
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uint8_t val;
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- uint16_t status;
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char *busname;
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- uint32_t mcp_spibaraddr;
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- void *mcp_spibar;
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+ uint32_t mcp6x_spibaraddr;
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struct pci_dev *smbusdev;
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msg_pinfo("This chipset is not really supported yet. Guesswork...\n");
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@@ -1144,40 +1142,33 @@
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smbusdev->bus, smbusdev->dev, smbusdev->func);
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/* Locate the BAR where the SPI interface lives. */
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- mcp_spibaraddr = pci_read_long(smbusdev, 0x74);
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- msg_pdbg("SPI BAR is at 0x%08x, ", mcp_spibaraddr);
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+ mcp6x_spibaraddr = pci_read_long(smbusdev, 0x74);
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+ msg_pdbg("SPI BAR is at 0x%08x, ", mcp6x_spibaraddr);
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/* We hope this has native alignment. We know the SPI interface (well,
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* a set of GPIOs that is connected to SPI flash) is at offset 0x530,
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* so we expect a size of at least 0x800. Clear the lower bits.
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* It is entirely possible that the BAR is 64k big and the low bits are
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* reserved for an entirely different purpose.
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*/
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- mcp_spibaraddr &= ~0x7ff;
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- msg_pdbg("after clearing low bits BAR is at 0x%08x\n", mcp_spibaraddr);
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+ mcp6x_spibaraddr &= ~0x7ff;
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+ msg_pdbg("after clearing low bits BAR is at 0x%08x\n", mcp6x_spibaraddr);
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/* Accessing a NULL pointer BAR is evil. Don't do it. */
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- if (mcp_spibaraddr && (buses_supported == CHIP_BUSTYPE_SPI)) {
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+ if (mcp6x_spibaraddr && (buses_supported == CHIP_BUSTYPE_SPI)) {
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/* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */
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- mcp_spibar = physmap("MCP67 SPI", mcp_spibaraddr, 0x544);
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+ mcp6x_spibar = physmap("Nvidia MCP6x SPI", mcp6x_spibaraddr, 0x544);
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-/* Guessed. If this is correct, migrate to a separate MCP67 SPI driver. */
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-#define MCP67_SPI_CS (1 << 1)
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-#define MCP67_SPI_SCK (1 << 2)
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-#define MCP67_SPI_MOSI (1 << 3)
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-#define MCP67_SPI_MISO (1 << 4)
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-#define MCP67_SPI_ENABLE (1 << 0)
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-#define MCP67_SPI_IDLE (1 << 8)
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-
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- status = mmio_readw(mcp_spibar + 0x530);
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- msg_pdbg("SPI control is 0x%04x, enable=%i, idle=%i\n",
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- status, status & 0x1, (status >> 8) & 0x1);
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+ if (mcp6x_spi_init())
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+ ret = 1;
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+#if 0
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/* FIXME: Remove the physunmap once the SPI driver exists. */
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- physunmap(mcp_spibar, 0x544);
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- } else if (!mcp_spibaraddr && (buses_supported & CHIP_BUSTYPE_SPI)) {
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+ physunmap(mcp6x_spibar, 0x544);
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+#endif
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+ } else if (!mcp6x_spibaraddr && (buses_supported & CHIP_BUSTYPE_SPI)) {
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msg_pdbg("Strange. MCP SPI BAR is invalid.\n");
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buses_supported &= ~CHIP_BUSTYPE_SPI;
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ret = 1;
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- } else if (mcp_spibaraddr && !(buses_supported & CHIP_BUSTYPE_SPI)) {
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+ } else if (mcp6x_spibaraddr && !(buses_supported & CHIP_BUSTYPE_SPI)) {
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msg_pdbg("Strange. MCP SPI BAR is valid, but chipset apparently"
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" doesn't have SPI enabled.\n");
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} else {
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@@ -1215,8 +1206,7 @@
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result = enable_flash_mcp55(dev, name);
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break;
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case CHIP_BUSTYPE_SPI:
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- msg_pinfo("SPI on this chipset is not supported yet.\n");
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- buses_supported = CHIP_BUSTYPE_NONE;
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+ msg_perr("SPI on this chipset is WIP. DO NOT USE!\n");
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break;
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default:
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msg_pinfo("Something went wrong with bus type detection.\n");
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@@ -1241,8 +1231,7 @@
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msg_pinfo("LPC on this chipset is not supported yet.\n");
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break;
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case CHIP_BUSTYPE_SPI:
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- msg_pinfo("SPI on this chipset is not supported yet.\n");
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- buses_supported = CHIP_BUSTYPE_NONE;
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+ msg_perr("SPI on this chipset is WIP. DO NOT USE!\n");
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break;
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default:
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msg_pinfo("Something went wrong with bus type detection.\n");
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diff -Naur flashrom-1061/flash.h flashrom-1061.patch/flash.h
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--- flashrom-1061/flash.h 2010-06-27 14:12:28.000000000 +0200
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+++ flashrom-1061.patch/flash.h 2010-06-27 14:16:51.102937596 +0200
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@@ -128,13 +128,16 @@
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void programmer_delay(int usecs);
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enum bitbang_spi_master {
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+#if CONFIG_INTERNAL == 1
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+#if defined(__i386__) || defined(__x86_64__)
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+ BITBANG_SPI_MASTER_MCP,
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+#endif
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+#endif
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BITBANG_SPI_INVALID /* This must always be the last entry. */
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};
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extern const int bitbang_spi_master_count;
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-extern enum bitbang_spi_master bitbang_spi_master;
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-
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struct bitbang_spi_master_entry {
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void (*set_cs) (int val);
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void (*set_sck) (int val);
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@@ -530,10 +533,22 @@
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int ft2232_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
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int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf);
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+/* mcp6x_spi.c */
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+#if CONFIG_INTERNAL == 1
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+#if defined(__i386__) || defined(__x86_64__)
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+extern void *mcp6x_spibar;
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+int mcp6x_spi_init(void);
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+void mcp6x_bitbang_set_cs(int val);
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+void mcp6x_bitbang_set_sck(int val);
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+void mcp6x_bitbang_set_mosi(int val);
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+int mcp6x_bitbang_get_miso(void);
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+#endif
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+#endif
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+
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/* bitbang_spi.c */
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extern int bitbang_spi_half_period;
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extern const struct bitbang_spi_master_entry bitbang_spi_master_table[];
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-int bitbang_spi_init(void);
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+int bitbang_spi_init(enum bitbang_spi_master master);
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int bitbang_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
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int bitbang_spi_read(struct flashchip *flash, uint8_t *buf, int start, int len);
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int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf);
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@@ -636,6 +651,7 @@
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SPI_CONTROLLER_SB600,
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SPI_CONTROLLER_VIA,
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SPI_CONTROLLER_WBSIO,
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+ SPI_CONTROLLER_MCP6X_BITBANG,
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#endif
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#endif
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#if CONFIG_FT2232_SPI == 1
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diff -Naur flashrom-1061/hwaccess.h flashrom-1061.patch/hwaccess.h
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--- flashrom-1061/hwaccess.h 2010-06-27 14:12:28.000000000 +0200
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+++ flashrom-1061.patch/hwaccess.h 2010-06-27 14:16:51.106934727 +0200
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@@ -176,6 +176,10 @@
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#define __DARWIN__
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#endif
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+/* Clarification about OUTB/OUTW/OUTL argument order:
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+ * OUT[BWL](val, port)
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+ */
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+
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#if defined(__FreeBSD__) || defined(__DragonFly__)
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#include <machine/cpufunc.h>
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#define off64_t off_t
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diff -Naur flashrom-1061/Makefile flashrom-1061.patch/Makefile
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--- flashrom-1061/Makefile 2010-06-27 14:12:28.000000000 +0200
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+++ flashrom-1061.patch/Makefile 2010-06-27 14:16:51.110933115 +0200
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@@ -107,8 +107,12 @@
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# Always enable serprog for now. Needs to be disabled on Windows.
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CONFIG_SERPROG ?= yes
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-# Bitbanging SPI infrastructure is not used yet.
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+# Bitbanging SPI infrastructure, default off unless needed.
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+ifeq ($(CONFIG_INTERNAL), yes)
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+CONFIG_BITBANG_SPI = yes
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+else
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CONFIG_BITBANG_SPI ?= no
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+endif
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# Always enable 3Com NICs for now.
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CONFIG_NIC3COM ?= yes
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@@ -151,7 +155,7 @@
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FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1'
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PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o dmi.o internal.o
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# FIXME: The PROGRAMMER_OBJS below should only be included on x86.
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-PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o
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+PROGRAMMER_OBJS += it87spi.o ichspi.o sb600spi.o wbsio_spi.o mcp6x_spi.o
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NEED_PCI := yes
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endif
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diff -Naur flashrom-1061/mcp6x_spi.c flashrom-1061.patch/mcp6x_spi.c
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--- flashrom-1061/mcp6x_spi.c 1970-01-01 01:00:00.000000000 +0100
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+++ flashrom-1061.patch/mcp6x_spi.c 2010-06-27 14:16:51.112932658 +0200
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@@ -0,0 +1,132 @@
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+/*
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+ * This file is part of the flashrom project.
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+ *
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+ * Copyright (C) 2010 Carl-Daniel Hailfinger
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
|
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+ * the Free Software Foundation; version 2 of the License.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
|
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+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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+ */
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+
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+/* Driver for the Nvidia MCP6x/MCP7x MCP6X_SPI controller.
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+ * Based on clean room reverse engineered docs from
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+ * http://www.flashrom.org/pipermail/flashrom/2009-December/001180.html
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+ * created by Michael Karcher.
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+ */
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+
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+#if defined(__i386__) || defined(__x86_64__)
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+
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+#include <stdint.h>
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+#include <stdlib.h>
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+#include <ctype.h>
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+#include "flash.h"
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+
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+/* We have two sets of pins, out and in. The numbers for both sets are
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+ * independent and are bitshift values, not real pin numbers.
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+ */
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+
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+/* Guessed. */
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+#define MCP6X_SPI_CS 1
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+#define MCP6X_SPI_SCK 2
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+#define MCP6X_SPI_MOSI 3
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+#define MCP6X_SPI_MISO 4
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+#define MCP6X_SPI_ENABLE 0
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+#define MCP6X_SPI_IDLE 8
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+
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+void *mcp6x_spibar = NULL;
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+
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+void mcp6x_request_spibus(void)
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+{
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+ uint8_t byte;
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+
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+ byte = mmio_readb(mcp6x_spibar + 0x530);
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+ byte |= 1 << MCP6X_SPI_ENABLE;
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+ mmio_writeb(byte, mcp6x_spibar + 0x530);
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+
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+ /* Wait until we are allowed to use the SPI bus. */
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+ while (!(mmio_readw(mcp6x_spibar + 0x530) & (1 << MCP6X_SPI_IDLE))) ;
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+}
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+
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+void mcp6x_release_spibus(void)
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+{
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+ uint8_t byte;
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+
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+ byte = mmio_readb(mcp6x_spibar + 0x530);
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+ byte &= ~(1 << MCP6X_SPI_ENABLE);
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+ mmio_writeb(byte, mcp6x_spibar + 0x530);
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+}
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+
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+void mcp6x_bitbang_set_cs(int val)
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+{
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+ uint8_t byte;
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+
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+ /* Requesting and releasing the SPI bus is handled in here to allow the
|
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+ * chipset to use its own SPI engine for native reads.
|
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+ */
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+ if (val == 0)
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+ mcp6x_request_spibus();
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+
|
||||
+ byte = mmio_readb(mcp6x_spibar + 0x530);
|
||||
+ byte &= ~(1 << MCP6X_SPI_CS);
|
||||
+ byte |= (val << MCP6X_SPI_CS);
|
||||
+ mmio_writeb(byte, mcp6x_spibar + 0x530);
|
||||
+
|
||||
+ if (val == 1)
|
||||
+ mcp6x_release_spibus();
|
||||
+}
|
||||
+
|
||||
+void mcp6x_bitbang_set_sck(int val)
|
||||
+{
|
||||
+ uint8_t byte;
|
||||
+
|
||||
+ byte = mmio_readb(mcp6x_spibar + 0x530);
|
||||
+ byte &= ~(1 << MCP6X_SPI_SCK);
|
||||
+ byte |= (val << MCP6X_SPI_SCK);
|
||||
+ mmio_writeb(byte, mcp6x_spibar + 0x530);
|
||||
+}
|
||||
+
|
||||
+void mcp6x_bitbang_set_mosi(int val)
|
||||
+{
|
||||
+ uint8_t byte;
|
||||
+
|
||||
+ byte = mmio_readb(mcp6x_spibar + 0x530);
|
||||
+ byte &= ~(1 << MCP6X_SPI_MOSI);
|
||||
+ byte |= (val << MCP6X_SPI_MOSI);
|
||||
+ mmio_writeb(byte, mcp6x_spibar + 0x530);
|
||||
+}
|
||||
+
|
||||
+int mcp6x_bitbang_get_miso(void)
|
||||
+{
|
||||
+ uint8_t byte;
|
||||
+
|
||||
+ byte = mmio_readb(mcp6x_spibar + 0x530);
|
||||
+ byte = (byte >> MCP6X_SPI_MISO) & 0x1;
|
||||
+ return byte;
|
||||
+}
|
||||
+
|
||||
+int mcp6x_spi_init(void)
|
||||
+{
|
||||
+ uint16_t status;
|
||||
+
|
||||
+ status = mmio_readw(mcp6x_spibar + 0x530);
|
||||
+ msg_pdbg("SPI control is 0x%04x, enable=%i, idle=%i\n",
|
||||
+ status, (status >> MCP6X_SPI_ENABLE) & 0x1,
|
||||
+ (status >> MCP6X_SPI_IDLE) & 0x1);
|
||||
+
|
||||
+ if (bitbang_spi_init(BITBANG_SPI_MASTER_MCP))
|
||||
+ return 1;
|
||||
+ spi_controller = SPI_CONTROLLER_MCP6X_BITBANG;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+#endif
|
||||
diff -Naur flashrom-1061/spi25.c flashrom-1061.patch/spi25.c
|
||||
--- flashrom-1061/spi25.c 2010-06-27 14:12:28.000000000 +0200
|
||||
+++ flashrom-1061.patch/spi25.c 2010-06-27 14:18:30.952808392 +0200
|
||||
@@ -182,6 +182,7 @@
|
||||
#if defined(__i386__) || defined(__x86_64__)
|
||||
case SPI_CONTROLLER_IT87XX:
|
||||
case SPI_CONTROLLER_WBSIO:
|
||||
+ case SPI_CONTROLLER_MCP6X_BITBANG:
|
||||
msg_cinfo("4 byte RDID not supported on this SPI controller\n");
|
||||
return 0;
|
||||
break;
|
||||
diff -Naur flashrom-1061/spi.c flashrom-1061.patch/spi.c
|
||||
--- flashrom-1061/spi.c 2010-06-27 14:12:28.000000000 +0200
|
||||
+++ flashrom-1061.patch/spi.c 2010-06-27 14:16:51.109934600 +0200
|
||||
@@ -83,6 +83,13 @@
|
||||
.read = wbsio_spi_read,
|
||||
.write_256 = wbsio_spi_write_1,
|
||||
},
|
||||
+
|
||||
+ { /* SPI_CONTROLLER_MCP6X_BITBANG */
|
||||
+ .command = bitbang_spi_send_command,
|
||||
+ .multicommand = default_spi_send_multicommand,
|
||||
+ .read = bitbang_spi_read,
|
||||
+ .write_256 = bitbang_spi_write_256,
|
||||
+ },
|
||||
#endif
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user