From 68b6d35202c693725d583c48b6149a6f5e24c66c Mon Sep 17 00:00:00 2001 From: MilhouseVH Date: Sun, 9 Jun 2019 14:20:26 +0100 Subject: [PATCH] linux (Generic/Allwinner): update to linux-5.1.8 --- packages/linux/package.mk | 4 +- .../patches/linux/0005-hdmi-init-fix.patch | 118 ------------------ 2 files changed, 2 insertions(+), 120 deletions(-) delete mode 100644 projects/Allwinner/patches/linux/0005-hdmi-init-fix.patch diff --git a/packages/linux/package.mk b/packages/linux/package.mk index 5ffc2cdac8..cb651e8d16 100644 --- a/packages/linux/package.mk +++ b/packages/linux/package.mk @@ -29,8 +29,8 @@ case "$LINUX" in PKG_SOURCE_NAME="linux-$LINUX-$PKG_VERSION.tar.gz" ;; *) - PKG_VERSION="5.1.7" - PKG_SHA256="0246d04df2b799bd0adbde8f24fcb0daa18819fa5442e9bdd6992979b7adf3a6" + PKG_VERSION="5.1.8" + PKG_SHA256="d0164ffcc6e2ab3a96cc771d3fbdf2f8b49a2597ec4da9a06df590b0fe87a6ec" PKG_URL="https://www.kernel.org/pub/linux/kernel/v5.x/$PKG_NAME-$PKG_VERSION.tar.xz" PKG_PATCH_DIRS="default" ;; diff --git a/projects/Allwinner/patches/linux/0005-hdmi-init-fix.patch b/projects/Allwinner/patches/linux/0005-hdmi-init-fix.patch deleted file mode 100644 index 7022c77884..0000000000 --- a/projects/Allwinner/patches/linux/0005-hdmi-init-fix.patch +++ /dev/null @@ -1,118 +0,0 @@ -From 4029cb43656ede363011e199e589357b2de95617 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 14 May 2019 22:02:46 +0200 -Subject: [PATCH 1/2] drm/sun4i: Fix sun8i HDMI PHY clock initialization - -Current code initializes HDMI PHY clock driver before reset line is -deasserted and clocks enabled. Because of that, initial readout of -clock divider is incorrect (0 instead of 2). This causes any clock -rate with divider 1 (register value 0) to be set incorrectly. - -Fix this by moving initialization of HDMI PHY clock driver after reset -line is deasserted and clocks enabled. - -Cc: stable@vger.kernel.org # 4.17+ -Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 26 ++++++++++++++------------ - 1 file changed, 14 insertions(+), 12 deletions(-) - -diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -index 66ea3a902e36..afc6d4a9c20b 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -@@ -672,22 +672,13 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) - goto err_put_clk_pll0; - } - } -- -- ret = sun8i_phy_clk_create(phy, dev, -- phy->variant->has_second_pll); -- if (ret) { -- dev_err(dev, "Couldn't create the PHY clock\n"); -- goto err_put_clk_pll1; -- } -- -- clk_prepare_enable(phy->clk_phy); - } - - phy->rst_phy = of_reset_control_get_shared(node, "phy"); - if (IS_ERR(phy->rst_phy)) { - dev_err(dev, "Could not get phy reset control\n"); - ret = PTR_ERR(phy->rst_phy); -- goto err_disable_clk_phy; -+ goto err_put_clk_pll1; - } - - ret = reset_control_deassert(phy->rst_phy); -@@ -708,18 +699,29 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) - goto err_disable_clk_bus; - } - -+ if (phy->variant->has_phy_clk) { -+ ret = sun8i_phy_clk_create(phy, dev, -+ phy->variant->has_second_pll); -+ if (ret) { -+ dev_err(dev, "Couldn't create the PHY clock\n"); -+ goto err_disable_clk_mod; -+ } -+ -+ clk_prepare_enable(phy->clk_phy); -+ } -+ - hdmi->phy = phy; - - return 0; - -+err_disable_clk_mod: -+ clk_disable_unprepare(phy->clk_mod); - err_disable_clk_bus: - clk_disable_unprepare(phy->clk_bus); - err_deassert_rst_phy: - reset_control_assert(phy->rst_phy); - err_put_rst_phy: - reset_control_put(phy->rst_phy); --err_disable_clk_phy: -- clk_disable_unprepare(phy->clk_phy); - err_put_clk_pll1: - clk_put(phy->clk_pll1); - err_put_clk_pll0: --- -2.21.0 - -From 3ebe28afd2b9250375d38bc1144a4aac74340464 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 14 May 2019 22:26:20 +0200 -Subject: [PATCH 2/2] drm/sun4i: Fix sun8i HDMI PHY configuration for > 148.5 - MHz - -Vendor provided documentation says that EMP bits should be set to 3 for -pixel clocks greater than 148.5 MHz. - -Fix that. - -Cc: stable@vger.kernel.org # 4.17+ -Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -index afc6d4a9c20b..43643ad31730 100644 ---- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c -@@ -293,7 +293,8 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi, - SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW | - SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4); - ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) | -- SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13); -+ SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13) | -+ SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(3); - } - - regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, --- -2.21.0 -