diff --git a/packages/linux-drivers/RTL8192EU/package.mk b/packages/linux-drivers/RTL8192EU/package.mk index ce5db333fb..a519e8b470 100644 --- a/packages/linux-drivers/RTL8192EU/package.mk +++ b/packages/linux-drivers/RTL8192EU/package.mk @@ -3,12 +3,12 @@ # Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv) PKG_NAME="RTL8192EU" -PKG_VERSION="4c9751be79ef847ef44ef63203278f4f05f21e52" -PKG_SHA256="09a957d70eeec4042116b95a6614676645346dece3c53a467a1a13e8b33a1c83" +PKG_VERSION="e0f967cea1d0037c730246c572f7fef000865ff7" +PKG_SHA256="2e11e26fccba644e4e5576948dbc1a5dd3ccd22f89be3d45eaa7c4276b8e766a" PKG_LICENSE="GPL" PKG_SITE="https://github.com/Mange/rtl8192eu-linux-driver" PKG_URL="https://github.com/Mange/rtl8192eu-linux-driver/archive/${PKG_VERSION}.tar.gz" -PKG_LONGDESC="Realtek RTL8192EU Linux 3.x driver" +PKG_LONGDESC="Realtek RTL8192EU Linux driver" PKG_IS_KERNEL_PKG="yes" pre_make_target() { diff --git a/packages/linux-drivers/RTL8812AU/package.mk b/packages/linux-drivers/RTL8812AU/package.mk index 34d6e32a4f..4e915617fd 100644 --- a/packages/linux-drivers/RTL8812AU/package.mk +++ b/packages/linux-drivers/RTL8812AU/package.mk @@ -3,12 +3,12 @@ # Copyright (C) 2018-present Team LibreELEC (https://libreelec.tv) PKG_NAME="RTL8812AU" -PKG_VERSION="307d694076b056588c652c2bdaa543a89eb255d9" -PKG_SHA256="51b8f5835afc95a8645277031a20c840db12959b1761ff730a2c0b986653c812" +PKG_VERSION="37e27f9165300c89607144b646545fac576ec510" +PKG_SHA256="749ba2e77d0364381445e40f7f0b7041d861cf9a356dbe53085e3abaef888c1d" PKG_LICENSE="GPL" PKG_SITE="https://github.com/aircrack-ng/rtl8812au" PKG_URL="https://github.com/aircrack-ng/rtl8812au/archive/${PKG_VERSION}.tar.gz" -PKG_LONGDESC="Realtek RTL8812AU Linux 3.x driver" +PKG_LONGDESC="Realtek RTL8812AU Linux driver" PKG_IS_KERNEL_PKG="yes" pre_make_target() { diff --git a/packages/linux-drivers/bcm_sta/patches/bcm_sta-0600-kernel-5.17-fix.patch b/packages/linux-drivers/bcm_sta/patches/bcm_sta-0600-kernel-5.17-fix.patch new file mode 100644 index 0000000000..7dba405fba --- /dev/null +++ b/packages/linux-drivers/bcm_sta/patches/bcm_sta-0600-kernel-5.17-fix.patch @@ -0,0 +1,26 @@ +--- a/x86-64/src/wl/sys/wl_linux.c 2022-02-19 15:22:05.006428601 +0000 ++++ b/x86-64/src/wl/sys/wl_linux.c 2022-02-19 21:55:03.290519415 +0000 +@@ -3287,7 +3287,11 @@ + static ssize_t + wl_proc_read(struct file *filp, char __user *buffer, size_t length, loff_t *offp) + { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0) + wl_info_t * wl = PDE_DATA(file_inode(filp)); ++#else ++ wl_info_t * wl = file_inode(filp)->i_private; ++#endif + #endif + int bcmerror, len; + int to_user = 0; +@@ -3344,7 +3348,11 @@ + static ssize_t + wl_proc_write(struct file *filp, const char __user *buff, size_t length, loff_t *offp) + { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0) + wl_info_t * wl = PDE_DATA(file_inode(filp)); ++#else ++ wl_info_t * wl = file_inode(filp)->i_private; ++#endif + #endif + int from_user = 0; + int bcmerror; diff --git a/packages/linux-firmware/iwlwifi-firmware/package.mk b/packages/linux-firmware/iwlwifi-firmware/package.mk index fe40b3c7e0..124bd77dfc 100644 --- a/packages/linux-firmware/iwlwifi-firmware/package.mk +++ b/packages/linux-firmware/iwlwifi-firmware/package.mk @@ -3,8 +3,8 @@ # Copyright (C) 2017-present Team LibreELEC (https://libreelec.tv) PKG_NAME="iwlwifi-firmware" -PKG_VERSION="fbe2571d45b43ae84abd4841ef50735b59a287c9" -PKG_SHA256="f2ff60e3b9309292c74c72154a1da4c3c94bbeaea0cc595fd33edc74e5845be4" +PKG_VERSION="ccf1a23d7f51e98562664c1ae80f51437b1c39dc" +PKG_SHA256="5e3ca25ceb47571e7639a03d6350179834df90a31eb98a5b37536fec4dbace7e" PKG_LICENSE="Free-to-use" PKG_SITE="https://github.com/LibreELEC/iwlwifi-firmware" PKG_URL="https://github.com/LibreELEC/iwlwifi-firmware/archive/${PKG_VERSION}.tar.gz" diff --git a/packages/linux-firmware/kernel-firmware/package.mk b/packages/linux-firmware/kernel-firmware/package.mk index b017beb390..c108506279 100644 --- a/packages/linux-firmware/kernel-firmware/package.mk +++ b/packages/linux-firmware/kernel-firmware/package.mk @@ -2,8 +2,8 @@ # Copyright (C) 2016-present Team LibreELEC (https://libreelec.tv) PKG_NAME="kernel-firmware" -PKG_VERSION="20211216" -PKG_SHA256="330ae22410701c00c1174d23e22f1d2a98e7d6d5c0b0ed4e34c70a392ac6ca97" +PKG_VERSION="20220209" +PKG_SHA256="2fd289256b6127a6528b2243e0227bfe1750833c725b5c9139fad183e94d4172" PKG_LICENSE="other" PKG_SITE="https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/" PKG_URL="https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/snapshot/${PKG_VERSION}.tar.gz" diff --git a/packages/linux/package.mk b/packages/linux/package.mk index 813db8d3ce..48baab9c7f 100644 --- a/packages/linux/package.mk +++ b/packages/linux/package.mk @@ -28,8 +28,8 @@ case "${LINUX}" in PKG_SOURCE_NAME="linux-${LINUX}-${PKG_VERSION}.tar.gz" ;; *) - PKG_VERSION="5.16.14" - PKG_SHA256="7a8ba58659d5e5f0f9e1e0a4fbed39ac520149d24d7aec4636fcf8255d0574f6" + PKG_VERSION="5.17" + PKG_SHA256="555fef61dddb591a83d62dd04e252792f9af4ba9ef14683f64840e46fa20b1b1" PKG_URL="https://www.kernel.org/pub/linux/kernel/v5.x/${PKG_NAME}-${PKG_VERSION}.tar.xz" PKG_PATCH_DIRS="default" ;; diff --git a/packages/linux/patches/default/linux-001-5-16-bluetooth-read-codec-capabilities-only-if-supported.patch b/packages/linux/patches/default/linux-001-5-16-bluetooth-read-codec-capabilities-only-if-supported.patch deleted file mode 100644 index 69ec345cd7..0000000000 --- a/packages/linux/patches/default/linux-001-5-16-bluetooth-read-codec-capabilities-only-if-supported.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 107fe0482b549a0e43a971e5fd104719c6e495ef Mon Sep 17 00:00:00 2001 -From: Kiran K -Date: Tue, 5 Oct 2021 20:15:56 +0530 -Subject: Bluetooth: Read codec capabilities only if supported - -Read codec capabilities only if HCI_READ_LOCAL_CODEC_CAPABILITIES -command is supported. If capablities are not supported, then -cache codec data without caps. - -Signed-off-by: Kiran K -Signed-off-by: Marcel Holtmann ---- - net/bluetooth/hci_codec.c | 18 ++++++++++++++++-- - 1 file changed, 16 insertions(+), 2 deletions(-) - -diff --git a/net/bluetooth/hci_codec.c b/net/bluetooth/hci_codec.c -index f0421d0edaa37..38201532f58e8 100644 ---- a/net/bluetooth/hci_codec.c -+++ b/net/bluetooth/hci_codec.c -@@ -25,9 +25,11 @@ static int hci_codec_list_add(struct list_head *list, - } - entry->transport = sent->transport; - entry->len = len; -- entry->num_caps = rp->num_caps; -- if (rp->num_caps) -+ entry->num_caps = 0; -+ if (rp) { -+ entry->num_caps = rp->num_caps; - memcpy(entry->caps, caps, len); -+ } - list_add(&entry->list, list); - - return 0; -@@ -58,6 +60,18 @@ static void hci_read_codec_capabilities(struct hci_dev *hdev, __u8 transport, - __u32 len; - - cmd->transport = i; -+ -+ /* If Read_Codec_Capabilities command is not supported -+ * then just add codec to the list without caps -+ */ -+ if (!(hdev->commands[45] & 0x08)) { -+ hci_dev_lock(hdev); -+ hci_codec_list_add(&hdev->local_codecs, cmd, -+ NULL, NULL, 0); -+ hci_dev_unlock(hdev); -+ continue; -+ } -+ - skb = __hci_cmd_sync(hdev, HCI_OP_READ_LOCAL_CODEC_CAPS, - sizeof(*cmd), cmd, - HCI_CMD_TIMEOUT); --- -cgit 1.2.3-1.el7 - diff --git a/packages/x11/driver/xf86-video-nvidia-legacy/patches/xf86-video-nvidia-legacy-100.09-kernel-5.17.patch b/packages/x11/driver/xf86-video-nvidia-legacy/patches/xf86-video-nvidia-legacy-100.09-kernel-5.17.patch new file mode 100644 index 0000000000..418e061677 --- /dev/null +++ b/packages/x11/driver/xf86-video-nvidia-legacy/patches/xf86-video-nvidia-legacy-100.09-kernel-5.17.patch @@ -0,0 +1,18 @@ +--- a/kernel/nv-linux.h 2022-02-20 00:41:53.585928825 +0000 ++++ b/kernel/nv-linux.h 2022-02-20 00:43:04.285797471 +0000 +@@ -2051,11 +2051,15 @@ + __entry; \ + }) + ++#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0) + #if defined(NV_PDE_DATA_PRESENT) + # define NV_PDE_DATA(inode) PDE_DATA(inode) + #else + # define NV_PDE_DATA(inode) PDE(inode)->data + #endif ++#else ++# define NV_PDE_DATA(inode) inode->i_private ++#endif + + #if defined(NV_PROC_REMOVE_PRESENT) + # define NV_REMOVE_PROC_ENTRY(entry) \ diff --git a/projects/Allwinner/linux/linux.aarch64.conf b/projects/Allwinner/linux/linux.aarch64.conf index 17351eeb1b..5b054d6feb 100644 --- a/projects/Allwinner/linux/linux.aarch64.conf +++ b/projects/Allwinner/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.16.2 Kernel Configuration +# Linux/arm64 5.17.0-rc3 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621" CONFIG_CC_IS_GCC=y @@ -227,7 +227,6 @@ CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y -CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -440,6 +439,8 @@ CONFIG_AS_HAS_LSE_ATOMICS=y # # ARMv8.2 architectural features # +CONFIG_AS_HAS_ARMV8_2=y +CONFIG_AS_HAS_SHA3=y # CONFIG_ARM64_PMEM is not set # CONFIG_ARM64_RAS_EXTN is not set # CONFIG_ARM64_CNP is not set @@ -671,6 +672,7 @@ CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y @@ -816,13 +818,12 @@ CONFIG_MEMORY_FAILURE=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -# CONFIG_CLEANCACHE is not set -# CONFIG_FRONTSWAP is not set CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set CONFIG_CMA_DEBUGFS=y CONFIG_CMA_SYSFS=y CONFIG_CMA_AREAS=7 +# CONFIG_ZSWAP is not set # CONFIG_ZPOOL is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y @@ -838,6 +839,7 @@ CONFIG_ZONE_DMA32=y # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_SECRETMEM=y +# CONFIG_ANON_VMA_NAME is not set # # Data Access Monitoring @@ -1410,6 +1412,7 @@ CONFIG_HAVE_PCI=y # CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y @@ -1839,6 +1842,7 @@ CONFIG_NET_VENDOR_CAVIUM=y CONFIG_NET_VENDOR_CORTINA=y # CONFIG_GEMINI_ETHERNET is not set # CONFIG_DNET is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set CONFIG_NET_VENDOR_EZCHIP=y # CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set # CONFIG_NET_VENDOR_GOOGLE is not set @@ -1901,6 +1905,7 @@ CONFIG_DWMAC_SUN8I=m # CONFIG_DWMAC_INTEL_PLAT is not set CONFIG_NET_VENDOR_SYNOPSYS=y # CONFIG_DWC_XLGMAC is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set CONFIG_NET_VENDOR_VIA=y # CONFIG_VIA_VELOCITY is not set CONFIG_NET_VENDOR_WIZNET=y @@ -2644,14 +2649,14 @@ CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set CONFIG_PINCTRL_AXP209=y -# CONFIG_PINCTRL_MCP23S08 is not set -CONFIG_PINCTRL_SINGLE=y -# CONFIG_PINCTRL_SX150X is not set -# CONFIG_PINCTRL_STMFX is not set CONFIG_PINCTRL_MAX77620=y -# CONFIG_PINCTRL_RK805 is not set -# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_MCP23S08 is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_RK805 is not set +CONFIG_PINCTRL_SINGLE=y +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_SX150X is not set # # Renesas pinctrl drivers @@ -2756,6 +2761,7 @@ CONFIG_GPIO_MAX77620=y # # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set @@ -2801,6 +2807,7 @@ CONFIG_AXP20X_POWER=y # CONFIG_CHARGER_LT3651 is not set # CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_MAX77976 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set @@ -2922,6 +2929,7 @@ CONFIG_SENSORS_LM90=m # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set @@ -2950,6 +2958,7 @@ CONFIG_SENSORS_LM90=m # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_INA209 is not set CONFIG_SENSORS_INA2XX=m +# CONFIG_SENSORS_INA238 is not set # CONFIG_SENSORS_INA3221 is not set # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set @@ -3136,7 +3145,6 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set -# CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set @@ -3182,6 +3190,7 @@ CONFIG_REGULATOR_MAX77620=y # CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX20086 is not set # CONFIG_REGULATOR_MAX77826 is not set # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MP5416 is not set @@ -3631,6 +3640,7 @@ CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5693 is not set # CONFIG_VIDEO_OV5695 is not set # CONFIG_VIDEO_OV7251 is not set # CONFIG_VIDEO_OV772X is not set @@ -3924,8 +3934,7 @@ CONFIG_DRM_FBDEV_OVERALLOC=100 CONFIG_DRM_LOAD_EDID_FIRMWARE=y # CONFIG_DRM_DP_CEC is not set CONFIG_DRM_GEM_CMA_HELPER=y -CONFIG_DRM_KMS_CMA_HELPER=y -CONFIG_DRM_GEM_SHMEM_HELPER=y +CONFIG_DRM_GEM_SHMEM_HELPER=m CONFIG_DRM_SCHED=m # @@ -3949,7 +3958,8 @@ CONFIG_DRM_I2C_SIL164=m # CONFIG_DRM_VKMS is not set # CONFIG_DRM_UDL is not set # CONFIG_DRM_RCAR_DW_HDMI is not set -# CONFIG_DRM_RCAR_LVDS is not set +# CONFIG_DRM_RCAR_USE_LVDS is not set +# CONFIG_DRM_RCAR_MIPI_DSI is not set CONFIG_DRM_SUN4I=y # CONFIG_DRM_SUN4I_HDMI is not set # CONFIG_DRM_SUN4I_BACKEND is not set @@ -4045,6 +4055,7 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9163 is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set # CONFIG_TINYDRM_ILI9486 is not set @@ -4059,6 +4070,7 @@ CONFIG_DRM_PANFROST=m # CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_NOMODESET=y # # Frame buffer Devices @@ -4196,6 +4208,7 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_AMD_ACP_CONFIG is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set @@ -4261,6 +4274,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set CONFIG_SND_SOC_AK4613=m @@ -4357,6 +4371,7 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set # CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320ADC3XXX is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set @@ -4477,6 +4492,7 @@ CONFIG_HID_KENSINGTON=y # CONFIG_HID_LCPOWER is not set # CONFIG_HID_LED is not set # CONFIG_HID_LENOVO is not set +# CONFIG_HID_LETSKETCH is not set CONFIG_HID_LOGITECH=y # CONFIG_HID_LOGITECH_DJ is not set CONFIG_HID_LOGITECH_HIDPP=m @@ -4902,6 +4918,10 @@ CONFIG_LEDS_TRIGGER_PANIC=y # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set # CONFIG_LEDS_TRIGGER_TTY is not set + +# +# Simple LED drivers +# # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_SUPPORT=y @@ -5154,6 +5174,7 @@ CONFIG_R8188EU=m CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_HANTRO_SUNXI=y +# CONFIG_VIDEO_MAX96712 is not set CONFIG_VIDEO_SUNXI=y CONFIG_VIDEO_SUNXI_CEDRUS=y @@ -5176,6 +5197,7 @@ CONFIG_VIDEO_SUNXI_CEDRUS=y # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set +# CONFIG_SURFACE_PLATFORMS is not set CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y @@ -5201,6 +5223,7 @@ CONFIG_COMMON_CLK_SCPI=y # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_LAN966X is not set # CONFIG_COMMON_CLK_S2MPS11 is not set # CONFIG_COMMON_CLK_AXI_CLKGEN is not set # CONFIG_COMMON_CLK_XGENE is not set @@ -5351,6 +5374,7 @@ CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y # # DEVFREQ Drivers # +CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=y # CONFIG_PM_DEVFREQ_EVENT is not set CONFIG_EXTCON=y @@ -5490,6 +5514,12 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_XILINX_XADC is not set # end of Analog to digital converters +# +# Analog to digital and digital to analog converters +# +# CONFIG_AD74413R is not set +# end of Analog to digital and digital to analog converters + # # Analog Front Ends # @@ -5547,6 +5577,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # # Digital to analog converters # +# CONFIG_AD3552R is not set # CONFIG_AD5064 is not set # CONFIG_AD5360 is not set # CONFIG_AD5380 is not set @@ -5566,6 +5597,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set +# CONFIG_AD7293 is not set # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set # CONFIG_DPOT_DAC is not set @@ -5589,6 +5621,12 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # # end of IIO dummy driver +# +# Filters +# +# CONFIG_ADMV8818 is not set +# end of Filters + # # Frequency Synthesizers DDS/PLL # @@ -5604,6 +5642,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 # # CONFIG_ADF4350 is not set # CONFIG_ADF4371 is not set +# CONFIG_ADMV1013 is not set # CONFIG_ADRF6780 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL @@ -5900,8 +5939,10 @@ CONFIG_PHY_SUN50I_USB3=y # CONFIG_PHY_CADENCE_SALVO is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set # CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_FSL_IMX8M_PCIE is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_LAN966X_SERDES is not set # CONFIG_PHY_CPCAP_USB is not set # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set @@ -5923,6 +5964,7 @@ CONFIG_PHY_SAMSUNG_USB2=y CONFIG_ARM_PMU=y # CONFIG_ARM_DSU_PMU is not set # CONFIG_ARM_SPE_PMU is not set +# CONFIG_MARVELL_CN10K_TAD_PMU is not set # end of Performance monitor support CONFIG_RAS=y @@ -6300,7 +6342,7 @@ CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y # end of Kernel hardening options # end of Security options -CONFIG_XOR_BLOCKS=m +CONFIG_XOR_BLOCKS=y CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA=y CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA=y CONFIG_CRYPTO=y @@ -6447,6 +6489,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_KDF800108_CTR=y CONFIG_CRYPTO_USER_API=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_SKCIPHER=y @@ -6454,25 +6497,6 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y CONFIG_CRYPTO_USER_API_AEAD=y CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y CONFIG_CRYPTO_HASH_INFO=y - -# -# Crypto library routines -# -CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=m -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_BLAKE2S=y -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y -CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y -CONFIG_CRYPTO_LIB_CHACHA=y -CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y -CONFIG_CRYPTO_LIB_CURVE25519=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y -CONFIG_CRYPTO_LIB_POLY1305=y -CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y -CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_DEV_ALLWINNER=y # CONFIG_CRYPTO_DEV_SUN4I_SS is not set @@ -6524,7 +6548,6 @@ CONFIG_HAVE_ARCH_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y -CONFIG_GENERIC_FIND_FIRST_BIT=y # CONFIG_CORDIC is not set # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y @@ -6533,6 +6556,26 @@ CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y CONFIG_INDIRECT_PIO=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y +CONFIG_CRYPTO_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y +CONFIG_CRYPTO_LIB_CURVE25519=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + CONFIG_CRC_CCITT=m CONFIG_CRC16=y CONFIG_CRC_T10DIF=y @@ -6693,11 +6736,21 @@ CONFIG_HAVE_ARCH_KGDB=y CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y # CONFIG_UBSAN is not set CONFIG_HAVE_KCSAN_COMPILER=y +CONFIG_HAVE_ARCH_KCSAN=y +CONFIG_HAVE_KCSAN_COMPILER=y +# CONFIG_KCSAN is not set # end of Generic Kernel Debugging Instruments CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# end of Networking Debugging + # # Memory Debugging # @@ -6840,12 +6893,12 @@ CONFIG_STRICT_DEVMEM=y # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_TEST_REF_TRACKER is not set # CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set # CONFIG_INTERVAL_TREE_TEST is not set @@ -6863,7 +6916,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_XARRAY is not set # CONFIG_TEST_OVERFLOW is not set # CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_HASH is not set +# CONFIG_TEST_SIPHASH is not set # CONFIG_TEST_IDA is not set # CONFIG_TEST_LKM is not set # CONFIG_TEST_BITOPS is not set diff --git a/projects/Allwinner/linux/linux.arm.conf b/projects/Allwinner/linux/linux.arm.conf index a0c8fbd9c3..38fc3ae874 100644 --- a/projects/Allwinner/linux/linux.arm.conf +++ b/projects/Allwinner/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.16.5 Kernel Configuration +# Linux/arm 5.17.0-rc3 Kernel Configuration # CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-10.3.0 (GCC) 10.3.0" CONFIG_CC_IS_GCC=y @@ -220,7 +220,6 @@ CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y -CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -652,6 +651,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y @@ -790,8 +790,6 @@ CONFIG_CONTIG_ALLOC=y CONFIG_BOUNCE=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -CONFIG_CLEANCACHE=y -CONFIG_FRONTSWAP=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set CONFIG_CMA_DEBUGFS=y @@ -806,6 +804,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_GUP_TEST is not set CONFIG_KMAP_LOCAL=y CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y +# CONFIG_ANON_VMA_NAME is not set # # Data Access Monitoring @@ -1338,6 +1337,7 @@ CONFIG_HAVE_PCI=y # CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y @@ -1536,7 +1536,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_ISCSI_BOOT_SYSFS is not set # CONFIG_SCSI_UFSHCD is not set -# CONFIG_SCSI_UFS_HWMON is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_DH is not set # end of SCSI device support @@ -1654,6 +1653,7 @@ CONFIG_NET_VENDOR_CORTINA=y # CONFIG_GEMINI_ETHERNET is not set # CONFIG_DM9000 is not set # CONFIG_DNET is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set CONFIG_NET_VENDOR_EZCHIP=y # CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set # CONFIG_NET_VENDOR_FARADAY is not set @@ -1702,6 +1702,7 @@ CONFIG_DWMAC_SUN8I=y # CONFIG_DWMAC_INTEL_PLAT is not set CONFIG_NET_VENDOR_SYNOPSYS=y # CONFIG_DWC_XLGMAC is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set @@ -2363,11 +2364,11 @@ CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set CONFIG_PINCTRL_AXP209=y # CONFIG_PINCTRL_MCP23S08 is not set -# CONFIG_PINCTRL_SINGLE is not set -# CONFIG_PINCTRL_SX150X is not set -# CONFIG_PINCTRL_STMFX is not set -# CONFIG_PINCTRL_OCELOT is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_SX150X is not set # # Renesas pinctrl drivers @@ -2470,6 +2471,7 @@ CONFIG_GPIO_CDEV_V1=y # # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set @@ -2502,6 +2504,7 @@ CONFIG_AXP20X_POWER=y # CONFIG_CHARGER_LT3651 is not set # CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_MAX77976 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set @@ -2622,6 +2625,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set @@ -2650,6 +2654,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_INA209 is not set # CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA238 is not set # CONFIG_SENSORS_INA3221 is not set # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set @@ -2846,7 +2851,6 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set -# CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set @@ -2888,6 +2892,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX20086 is not set # CONFIG_REGULATOR_MAX77826 is not set # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MP5416 is not set @@ -3333,6 +3338,7 @@ CONFIG_VIDEO_ST_MIPID02=m # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5693 is not set # CONFIG_VIDEO_OV5695 is not set # CONFIG_VIDEO_OV7251 is not set # CONFIG_VIDEO_OV772X is not set @@ -3634,8 +3640,7 @@ CONFIG_DRM_FBDEV_OVERALLOC=100 CONFIG_DRM_LOAD_EDID_FIRMWARE=y # CONFIG_DRM_DP_CEC is not set CONFIG_DRM_GEM_CMA_HELPER=y -CONFIG_DRM_KMS_CMA_HELPER=y -CONFIG_DRM_GEM_SHMEM_HELPER=y +CONFIG_DRM_GEM_SHMEM_HELPER=m CONFIG_DRM_SCHED=m # @@ -3661,7 +3666,8 @@ CONFIG_DRM_SCHED=m # CONFIG_DRM_UDL is not set # CONFIG_DRM_ARMADA is not set # CONFIG_DRM_RCAR_DW_HDMI is not set -# CONFIG_DRM_RCAR_LVDS is not set +# CONFIG_DRM_RCAR_USE_LVDS is not set +# CONFIG_DRM_RCAR_MIPI_DSI is not set CONFIG_DRM_SUN4I=y CONFIG_DRM_SUN4I_HDMI=y CONFIG_DRM_SUN4I_HDMI_CEC=y @@ -3750,6 +3756,7 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9163 is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set # CONFIG_TINYDRM_ILI9486 is not set @@ -3766,6 +3773,7 @@ CONFIG_DRM_LIMA=m # CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_NOMODESET=y # # Frame buffer Devices @@ -3876,6 +3884,7 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_AMD_ACP_CONFIG is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set @@ -3939,6 +3948,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set @@ -4034,6 +4044,7 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set # CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320ADC3XXX is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set @@ -4154,6 +4165,7 @@ CONFIG_HID_KENSINGTON=y # CONFIG_HID_LCPOWER is not set # CONFIG_HID_LED is not set # CONFIG_HID_LENOVO is not set +# CONFIG_HID_LETSKETCH is not set CONFIG_HID_LOGITECH=y # CONFIG_HID_LOGITECH_DJ is not set CONFIG_HID_LOGITECH_HIDPP=m @@ -4581,6 +4593,10 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set # CONFIG_LEDS_TRIGGER_TTY is not set + +# +# Simple LED drivers +# # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y @@ -4820,6 +4836,7 @@ CONFIG_R8188EU=m CONFIG_STAGING_MEDIA=y # CONFIG_VIDEO_HANTRO is not set +# CONFIG_VIDEO_MAX96712 is not set CONFIG_VIDEO_SUNXI=y CONFIG_VIDEO_SUNXI_CEDRUS=y @@ -4863,6 +4880,7 @@ CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_LAN966X is not set # CONFIG_COMMON_CLK_AXI_CLKGEN is not set # CONFIG_COMMON_CLK_PWM is not set # CONFIG_COMMON_CLK_VC5 is not set @@ -4975,6 +4993,7 @@ CONFIG_DEVFREQ_GOV_PASSIVE=y # # DEVFREQ Drivers # +CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=y CONFIG_PM_DEVFREQ_EVENT=y CONFIG_EXTCON=y @@ -5113,6 +5132,12 @@ CONFIG_SUN4I_GPADC=y # CONFIG_XILINX_XADC is not set # end of Analog to digital converters +# +# Analog to digital and digital to analog converters +# +# CONFIG_AD74413R is not set +# end of Analog to digital and digital to analog converters + # # Analog Front Ends # @@ -5170,6 +5195,7 @@ CONFIG_SUN4I_GPADC=y # # Digital to analog converters # +# CONFIG_AD3552R is not set # CONFIG_AD5064 is not set # CONFIG_AD5360 is not set # CONFIG_AD5380 is not set @@ -5189,6 +5215,7 @@ CONFIG_SUN4I_GPADC=y # CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set +# CONFIG_AD7293 is not set # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set # CONFIG_DPOT_DAC is not set @@ -5212,6 +5239,11 @@ CONFIG_SUN4I_GPADC=y # # end of IIO dummy driver +# +# Filters +# +# end of Filters + # # Frequency Synthesizers DDS/PLL # @@ -5227,6 +5259,7 @@ CONFIG_SUN4I_GPADC=y # # CONFIG_ADF4350 is not set # CONFIG_ADF4371 is not set +# CONFIG_ADMV1013 is not set # CONFIG_ADRF6780 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL @@ -5513,8 +5546,10 @@ CONFIG_PHY_SUN50I_USB3=y # CONFIG_PHY_CADENCE_SALVO is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set # CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_FSL_IMX8M_PCIE is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_LAN966X_SERDES is not set # CONFIG_PHY_CPCAP_USB is not set # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set @@ -6010,6 +6045,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=m CONFIG_CRYPTO_JITTERENTROPY=m +CONFIG_CRYPTO_KDF800108_CTR=y CONFIG_CRYPTO_USER_API=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_SKCIPHER=y @@ -6017,24 +6053,6 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y CONFIG_CRYPTO_USER_API_AEAD=y CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y CONFIG_CRYPTO_HASH_INFO=y - -# -# Crypto library routines -# -CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=m -CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S=y -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y -CONFIG_CRYPTO_LIB_CHACHA=y -CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y -CONFIG_CRYPTO_LIB_CURVE25519=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y -CONFIG_CRYPTO_LIB_POLY1305=y -CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y -CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_DEV_ALLWINNER=y CONFIG_CRYPTO_DEV_SUN4I_SS=m @@ -6091,6 +6109,25 @@ CONFIG_CORDIC=m CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y +CONFIG_CRYPTO_LIB_CURVE25519=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + CONFIG_CRC_CCITT=y CONFIG_CRC16=y # CONFIG_CRC_T10DIF is not set @@ -6234,6 +6271,13 @@ CONFIG_HAVE_KCSAN_COMPILER=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# end of Networking Debugging + # # Memory Debugging # @@ -6261,6 +6305,8 @@ CONFIG_HAVE_ARCH_KASAN=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -6344,6 +6390,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set @@ -6356,6 +6403,7 @@ CONFIG_TRACING_SUPPORT=y # CONFIG_UNWINDER_FRAME_POINTER is not set CONFIG_UNWINDER_ARM=y CONFIG_ARM_UNWIND=y +# CONFIG_BACKTRACE_VERBOSE is not set # CONFIG_DEBUG_USER is not set # CONFIG_DEBUG_LL is not set CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" @@ -6378,6 +6426,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_TEST_REF_TRACKER is not set # CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set # CONFIG_INTERVAL_TREE_TEST is not set @@ -6395,7 +6444,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_XARRAY is not set # CONFIG_TEST_OVERFLOW is not set # CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_HASH is not set +# CONFIG_TEST_SIPHASH is not set # CONFIG_TEST_IDA is not set # CONFIG_TEST_LKM is not set # CONFIG_TEST_BITOPS is not set diff --git a/projects/Allwinner/patches/linux/0035-ARM-dts-sun8i-Adjust-power-key-nodes.patch b/projects/Allwinner/patches/linux/0035-ARM-dts-sun8i-Adjust-power-key-nodes.patch deleted file mode 100644 index 6a4f3e16f6..0000000000 --- a/projects/Allwinner/patches/linux/0035-ARM-dts-sun8i-Adjust-power-key-nodes.patch +++ /dev/null @@ -1,107 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 30 Jan 2021 18:12:26 +0100 -Subject: [PATCH] ARM: dts: sun8i: Adjust power key nodes - -Several H3 and one H2+ board have power key nodes, which are slightly -off. Some are missing wakeup-source property and some have BTN_0 code -assigned instead of KEY_POWER. - -Adjust them, so they can function as intended by designer. - -Signed-off-by: Jernej Skrabec -[BananaPi M2 Zero changes] -Signed-off-by: Michael Klein ---- - arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts | 3 ++- - arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 1 + - arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 3 ++- - arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 3 ++- - arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi | 3 ++- - arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi | 1 + - 6 files changed, 10 insertions(+), 4 deletions(-) - -diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts -index 8e8634ff2f9d..d5c7b7984d85 100644 ---- a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts -+++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts -@@ -52,8 +52,9 @@ gpio_keys { - - sw4 { - label = "power"; -- linux,code = ; -+ linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; -+ wakeup-source; - }; - }; - -diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi -index c7c3e7d8b3c8..fc45d5aaa67f 100644 ---- a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi -+++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi -@@ -81,6 +81,7 @@ k1 { - label = "k1"; - linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; -+ wakeup-source; - }; - }; - }; -diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts -index 597c425d08ec..9daffd90c12f 100644 ---- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts -+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts -@@ -99,8 +99,9 @@ sw2 { - - sw4 { - label = "sw4"; -- linux,code = ; -+ linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; -+ wakeup-source; - }; - }; - -diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts -index 5aff8ecc66cb..90f75fa85e68 100644 ---- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts -+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts -@@ -91,8 +91,9 @@ r_gpio_keys { - - sw4 { - label = "sw4"; -- linux,code = ; -+ linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; -+ wakeup-source; - }; - }; - }; -diff --git a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi -index 7a6af54dd342..d03f5853ef7b 100644 ---- a/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi -+++ b/arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi -@@ -82,8 +82,9 @@ gpio_keys { - - sw4 { - label = "power"; -- linux,code = ; -+ linux,code = ; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; -+ wakeup-source; - }; - }; - -diff --git a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi -index c44fd726945a..9e14fe5fdcde 100644 ---- a/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi -+++ b/arch/arm/boot/dts/sunxi-libretech-all-h3-cc.dtsi -@@ -49,6 +49,7 @@ power { - label = "power"; - linux,code = ; - gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ -+ wakeup-source; - }; - }; - diff --git a/projects/Allwinner/patches/linux/0051-arm64-dts-allwinner-h6-tanix-tx6-enable-ethernet.patch b/projects/Allwinner/patches/linux/0051-arm64-dts-allwinner-h6-tanix-tx6-enable-ethernet.patch index 1fe0dd8805..2756056efd 100644 --- a/projects/Allwinner/patches/linux/0051-arm64-dts-allwinner-h6-tanix-tx6-enable-ethernet.patch +++ b/projects/Allwinner/patches/linux/0051-arm64-dts-allwinner-h6-tanix-tx6-enable-ethernet.patch @@ -5,14 +5,14 @@ Subject: [PATCH] arm64: dts: allwinner: h6: tanix-tx6: enable ethernet Signed-off-by: Jernej Skrabec --- - .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 28 +++++++++++++++++++ + .../dts/allwinner/sun50i-h6-tanix.dtsi | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi @@ -13,6 +13,7 @@ - compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6"; + / { aliases { + ethernet0 = &emac; serial0 = &uart0; @@ -63,7 +63,7 @@ Signed-off-by: Jernej Skrabec pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; @@ -119,6 +143,10 @@ - vcc-pc-supply = <®_vcc1v8>; + vcc-pg-supply = <®_vcc1v8>; }; +&pwm { @@ -71,5 +71,5 @@ Signed-off-by: Jernej Skrabec +}; + &r_ir { - linux,rc-map-name = "rc-tanix-tx5max"; status = "okay"; + }; diff --git a/projects/Allwinner/patches/linux/0054-arm64-dts-allwinner-h6-tanix-tx6-add-bt-enable-rtw88.patch b/projects/Allwinner/patches/linux/0054-arm64-dts-allwinner-h6-tanix-tx6-add-bt-enable-rtw88.patch deleted file mode 100644 index 07c1bbec84..0000000000 --- a/projects/Allwinner/patches/linux/0054-arm64-dts-allwinner-h6-tanix-tx6-add-bt-enable-rtw88.patch +++ /dev/null @@ -1,108 +0,0 @@ -From ba918badf612c19b4e31a57b2ff4baa06e99d7d5 Mon Sep 17 00:00:00 2001 -From: heitbaum -Date: Sun, 23 May 2021 06:37:45 +0000 -Subject: [PATCH] Allwinner: linux: enable BT on Tanix TX6 and add wifi node for rtl8822cs (rtw88) - -Add and enable dts nodes for both rtw88 (rtl8822cs sdio) and uart rtl8822cs bluetooth. - -# udevadm info /sys/bus/sdio/devices/mmc1\:0001\:1/ -P: /devices/platform/soc/4021000.mmc/mmc_host/mmc1/mmc1:0001/mmc1:0001:1 -L: 0 -E: -DEVPATH=/devices/platform/soc/4021000.mmc/mmc_host/mmc1/mmc1:0001/mmc1:0001:1 -E: OF_NAME=sdio-wifi -E: OF_FULLNAME=/soc/mmc@4021000/sdio-wifi@1 -E: OF_COMPATIBLE_N=0 -E: SDIO_CLASS=07 -E: SDIO_ID=024C:C822 -E: SDIO_REVISION=0.0 -E: MODALIAS=sdio:c07v024CdC822 -E: SUBSYSTEM=sdio - -# dmesg | grep hci0 -Bluetooth: hci0: RTL: examining hci_ver=08 hci_rev=000c subver=8822 -Bluetooth: hci0: RTL: rom_version status=0 version=3 -Bluetooth: hci0: RTL: loading rtl_bt/rtl8822cs_fw.bin -Bluetooth: hci0: RTL: loading rtl_bt/rtl8822cs_config.bin - ---- - .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 32 +++++++++++++++++++ - 1 file changed, 48 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -@@ -47,12 +47,29 @@ - regulator-max-microvolt = <3300000>; - }; - -+ reg_vcc_wifi_io: vcc-wifi-io { -+ /* Always on 1.8V/300mA regulator for WiFi and BT IO */ -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc-wifi-io"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ vin-supply = <®_vcc3v3>; -+ }; -+ - reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu { - compatible = "regulator-fixed"; - regulator-name = "vdd-cpu-gpu"; - regulator-min-microvolt = <1135000>; - regulator-max-microvolt = <1135000>; - }; -+ -+ wifi_pwrseq: wifi-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rtc 1>; -+ clock-names = "ext_clock"; -+ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ -+ }; - }; - - &ac200_pwm_clk { -@@ -122,6 +139,22 @@ - status = "okay"; - }; - -+&mmc1 { -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc_wifi_io>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ rtl8822cs: sdio-wifi@1 { -+ reg = <1>; -+ interrupt-parent = <&r_pio>; -+ interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ -+ interrupt-names = "host-wake"; -+ }; -+}; -+ - &mmc2 { - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc1v8>; -@@ -158,6 +191,21 @@ - status = "okay"; - }; - -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; -+ uart-has-rtscts; -+ status = "okay"; -+ -+ bluetooth { -+ //use 8822cs compatible to load hci_h5 and btrtl driver -+ compatible = "realtek,rtl8822cs-bt"; -+ device-wake-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ -+ host-wake-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */ -+ enable-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ -+ }; -+}; -+ - &usb2otg { - dr_mode = "host"; - status = "okay"; diff --git a/projects/Allwinner/patches/linux/0054-arm64-dts-allwinner-h6-tanix-tx6-enable-rtw88-wifi-in-dts.patch b/projects/Allwinner/patches/linux/0054-arm64-dts-allwinner-h6-tanix-tx6-enable-rtw88-wifi-in-dts.patch new file mode 100644 index 0000000000..7aa88c6863 --- /dev/null +++ b/projects/Allwinner/patches/linux/0054-arm64-dts-allwinner-h6-tanix-tx6-enable-rtw88-wifi-in-dts.patch @@ -0,0 +1,58 @@ +From ba918badf612c19b4e31a57b2ff4baa06e99d7d5 Mon Sep 17 00:00:00 2001 +From: heitbaum +Date: Sun, 23 May 2021 06:37:45 +0000 +Subject: [PATCH] Allwinner: linux: add wifi node for rtl8822cs (rtw88) + +Add and enable dts node for rtw88 (rtl8822cs sdio) + +# udevadm info /sys/bus/sdio/devices/mmc1\:0001\:1/ +P: /devices/platform/soc/4021000.mmc/mmc_host/mmc1/mmc1:0001/mmc1:0001:1 +L: 0 +E: +DEVPATH=/devices/platform/soc/4021000.mmc/mmc_host/mmc1/mmc1:0001/mmc1:0001:1 +E: OF_NAME=sdio-wifi +E: OF_FULLNAME=/soc/mmc@4021000/sdio-wifi@1 +E: OF_COMPATIBLE_N=0 +E: SDIO_CLASS=07 +E: SDIO_ID=024C:C822 +E: SDIO_REVISION=0.0 +E: MODALIAS=sdio:c07v024CdC822 +E: SUBSYSTEM=sdio + +--- + .../dts/allwinner/sun50i-h6-tanix-tx6.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi +@@ -52,6 +52,16 @@ + regulator-max-microvolt = <3300000>; + }; + ++ reg_vcc_wifi_io: vcc-wifi-io { ++ /* Always on 1.8V/300mA regulator for WiFi and BT IO */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-wifi-io"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ vin-supply = <®_vcc3v3>; ++ }; ++ + reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu { + compatible = "regulator-fixed"; + regulator-name = "vdd-cpu-gpu"; +@@ -159,6 +169,13 @@ + bus-width = <4>; + non-removable; + status = "okay"; ++ ++ rtl8822cs: sdio-wifi@1 { ++ reg = <1>; ++ interrupt-parent = <&r_pio>; ++ interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ ++ interrupt-names = "host-wake"; ++ }; + }; + + &mmc2 { diff --git a/projects/Allwinner/patches/linux/0061-arm64-dts-allwinner-h6-tanix-tx6-Add-SPDIF.patch b/projects/Allwinner/patches/linux/0061-arm64-dts-allwinner-h6-tanix-tx6-Add-SPDIF.patch deleted file mode 100644 index 4a3fb2aeb1..0000000000 --- a/projects/Allwinner/patches/linux/0061-arm64-dts-allwinner-h6-tanix-tx6-Add-SPDIF.patch +++ /dev/null @@ -1,54 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 8 Nov 2021 20:48:17 +0100 -Subject: [PATCH] arm64: dts: allwinner: h6: tanix-tx6: Add SPDIF - -Tanix TX6 board has SPDIF connector in form of 3.5 mm jack. - -Add support for it. - -Signed-off-by: Jernej Skrabec ---- - .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 22 +++++++++++++++++++ - 1 file changed, 22 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -index 8f2a80f128de..6c10ff7f4b1c 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts -@@ -52,6 +52,24 @@ reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu { - regulator-min-microvolt = <1135000>; - regulator-max-microvolt = <1135000>; - }; -+ -+ sound-spdif { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "sun50i-h6-spdif"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&spdif>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&spdif_out>; -+ }; -+ }; -+ -+ spdif_out: spdif-out { -+ #sound-dai-cells = <0>; -+ compatible = "linux,spdif-dit"; -+ }; - }; - - &cpu0 { -@@ -127,6 +145,10 @@ &r_ir { - status = "okay"; - }; - -+&spdif { -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; diff --git a/projects/Allwinner/patches/linux/0062-ASoC-sunxi-sun4i-spdif-Implement-IEC958-control.patch b/projects/Allwinner/patches/linux/0062-ASoC-sunxi-sun4i-spdif-Implement-IEC958-control.patch deleted file mode 100644 index 9026016d48..0000000000 --- a/projects/Allwinner/patches/linux/0062-ASoC-sunxi-sun4i-spdif-Implement-IEC958-control.patch +++ /dev/null @@ -1,132 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 9 Nov 2021 18:52:37 +0100 -Subject: [PATCH] ASoC: sunxi: sun4i-spdif: Implement IEC958 control - -SPDIF core is capable of sending custom status. - -Implement IEC958 control handling. - -Signed-off-by: Jernej Skrabec ---- - sound/soc/sunxi/sun4i-spdif.c | 95 +++++++++++++++++++++++++++++++++++ - 1 file changed, 95 insertions(+) - -diff --git a/sound/soc/sunxi/sun4i-spdif.c b/sound/soc/sunxi/sun4i-spdif.c -index a10949bf0ca1..e80982b229ff 100644 ---- a/sound/soc/sunxi/sun4i-spdif.c -+++ b/sound/soc/sunxi/sun4i-spdif.c -@@ -21,6 +21,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -385,11 +386,105 @@ static int sun4i_spdif_trigger(struct snd_pcm_substream *substream, int cmd, - return ret; - } - -+static int sun4i_spdif_info(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_info *uinfo) -+{ -+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; -+ uinfo->count = 1; -+ -+ return 0; -+} -+ -+static int sun4i_spdif_get_status_mask(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ u8 *status = ucontrol->value.iec958.status; -+ -+ status[0] = 0xff; -+ status[1] = 0xff; -+ status[2] = 0xff; -+ status[3] = 0xff; -+ status[4] = 0xff; -+ -+ return 0; -+} -+ -+static int sun4i_spdif_get_status(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); -+ struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai); -+ u8 *status = ucontrol->value.iec958.status; -+ unsigned int reg; -+ -+ regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA0, ®); -+ -+ status[0] = reg & 0xff; -+ status[1] = (reg >> 8) & 0xff; -+ status[2] = (reg >> 16) & 0xff; -+ status[3] = (reg >> 24) & 0xff; -+ -+ regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA1, ®); -+ -+ status[4] = reg & 0xff; -+ -+ return 0; -+} -+ -+static int sun4i_spdif_set_status(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); -+ struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai); -+ u8 *status = ucontrol->value.iec958.status; -+ unsigned int reg; -+ -+ reg = ((u32)status[3] << 24); -+ reg |= ((u32)status[2] << 16); -+ reg |= ((u32)status[1] << 8); -+ reg |= (u32)status[0]; -+ -+ regmap_write(host->regmap, SUN4I_SPDIF_TXCHSTA0, reg); -+ -+ reg = status[4]; -+ regmap_write(host->regmap, SUN4I_SPDIF_TXCHSTA1, reg); -+ -+ reg = SUN4I_SPDIF_TXCFG_CHSTMODE; -+ if (status[0] & IEC958_AES0_NONAUDIO) -+ reg |= SUN4I_SPDIF_TXCFG_NONAUDIO; -+ -+ regmap_update_bits(host->regmap, SUN4I_SPDIF_TXCFG, -+ SUN4I_SPDIF_TXCFG_CHSTMODE | -+ SUN4I_SPDIF_TXCFG_NONAUDIO, reg); -+ -+ return 0; -+} -+ -+static struct snd_kcontrol_new sun4i_spdif_controls[] = { -+ { -+ .access = SNDRV_CTL_ELEM_ACCESS_READ, -+ .iface = SNDRV_CTL_ELEM_IFACE_PCM, -+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK), -+ .info = sun4i_spdif_info, -+ .get = sun4i_spdif_get_status_mask -+ }, -+ { -+ .iface = SNDRV_CTL_ELEM_IFACE_PCM, -+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), -+ .info = sun4i_spdif_info, -+ .get = sun4i_spdif_get_status, -+ .put = sun4i_spdif_set_status -+ } -+}; -+ - static int sun4i_spdif_soc_dai_probe(struct snd_soc_dai *dai) - { - struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(dai); - - snd_soc_dai_init_dma_data(dai, &host->dma_params_tx, NULL); -+ snd_soc_add_dai_controls(dai, sun4i_spdif_controls, -+ ARRAY_SIZE(sun4i_spdif_controls)); -+ - return 0; - } - diff --git a/projects/Allwinner/patches/linux/0064-ARM-dts-sun8i-h3-beelink-x2-Add-GPIO-CEC-node.patch b/projects/Allwinner/patches/linux/0064-ARM-dts-sun8i-h3-beelink-x2-Add-GPIO-CEC-node.patch deleted file mode 100644 index 7f8746afda..0000000000 --- a/projects/Allwinner/patches/linux/0064-ARM-dts-sun8i-h3-beelink-x2-Add-GPIO-CEC-node.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 20 Nov 2021 10:35:25 +0100 -Subject: [PATCH] ARM: dts: sun8i: h3: beelink-x2: Add GPIO CEC node - -Beelink X2 doesn't use HW CEC controller found in DW HDMI core. It has -dedicated GPIO pin for that purpose. - -Add a node for it. - -Signed-off-by: Jernej Skrabec ---- - arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts -index f0e591e1c771..4ab4bbf001ba 100644 ---- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts -+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts -@@ -57,6 +57,12 @@ aliases { - ethernet1 = &sdiowifi; - }; - -+ cec-gpio { -+ compatible = "cec-gpio"; -+ cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */ -+ hdmi-phandle = <&hdmi>; -+ }; -+ - chosen { - stdout-path = "serial0:115200n8"; - }; diff --git a/projects/Allwinner/patches/linux/0066-drm-sun4i-virtual-CMA-addresses-are-not-needed.patch b/projects/Allwinner/patches/linux/0066-drm-sun4i-virtual-CMA-addresses-are-not-needed.patch deleted file mode 100644 index 9223b4bfa1..0000000000 --- a/projects/Allwinner/patches/linux/0066-drm-sun4i-virtual-CMA-addresses-are-not-needed.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Tue, 5 Oct 2021 17:22:04 +0200 -Subject: [PATCH] drm/sun4i: virtual CMA addresses are not needed - -Driver never uses virtual address of DRM CMA buffers. Switch to CMA -helpers which don't deal with virtual mapping. - -This was actually already the case before commit ad408c766cef -("drm/sun4i: Use DRM_GEM_CMA_VMAP_DRIVER_OPS for GEM operations"), -but only convenient macro at the time used helpers with virtual -mapping. - -Signed-off-by: Jernej Skrabec ---- - drivers/gpu/drm/sun4i/sun4i_drv.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c -index 54dd562e294c..b630614b3d72 100644 ---- a/drivers/gpu/drm/sun4i/sun4i_drv.c -+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c -@@ -53,7 +53,7 @@ static const struct drm_driver sun4i_drv_driver = { - .minor = 0, - - /* GEM Operations */ -- DRM_GEM_CMA_DRIVER_OPS_VMAP_WITH_DUMB_CREATE(drm_sun4i_gem_dumb_create), -+ DRM_GEM_CMA_DRIVER_OPS_WITH_DUMB_CREATE(drm_sun4i_gem_dumb_create), - }; - - static int sun4i_drv_bind(struct device *dev) diff --git a/projects/Allwinner/patches/linux/0067-hantro-postproc-Fix-motion-vector-space-size.patch b/projects/Allwinner/patches/linux/0067-hantro-postproc-Fix-motion-vector-space-size.patch deleted file mode 100644 index 95ec0de49e..0000000000 --- a/projects/Allwinner/patches/linux/0067-hantro-postproc-Fix-motion-vector-space-size.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Tue, 16 Nov 2021 15:38:31 +0100 -Subject: [PATCH] hantro: postproc: Fix motion vector space size - -When the post-processor hardware block is enabled, the driver -allocates an internal queue of buffers for the decoder enginer, -and uses the vb2 queue for the post-processor engine. - -For instance, on a G1 core, the decoder engine produces NV12 buffers -and the post-processor engine can produce YUY2 buffers. The decoder -engine expects motion vectors to be appended to the NV12 buffers, -but this is only required for CODECs that need motion vectors, -such as H.264. - -Fix the post-processor logic accordingly. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/hantro_postproc.c | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index ed8916c950a4..07842152003f 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -132,9 +132,10 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx) - unsigned int num_buffers = cap_queue->num_buffers; - unsigned int i, buf_size; - -- buf_size = ctx->dst_fmt.plane_fmt[0].sizeimage + -- hantro_h264_mv_size(ctx->dst_fmt.width, -- ctx->dst_fmt.height); -+ buf_size = ctx->dst_fmt.plane_fmt[0].sizeimage; -+ if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE) -+ buf_size += hantro_h264_mv_size(ctx->dst_fmt.width, -+ ctx->dst_fmt.height); - - for (i = 0; i < num_buffers; ++i) { - struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i]; diff --git a/projects/Allwinner/patches/linux/0068-hantro-postproc-Introduce-struct-hantro_postproc_ops.patch b/projects/Allwinner/patches/linux/0068-hantro-postproc-Introduce-struct-hantro_postproc_ops.patch deleted file mode 100644 index 8466cd8f22..0000000000 --- a/projects/Allwinner/patches/linux/0068-hantro-postproc-Introduce-struct-hantro_postproc_ops.patch +++ /dev/null @@ -1,229 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Tue, 16 Nov 2021 15:38:32 +0100 -Subject: [PATCH] hantro: postproc: Introduce struct hantro_postproc_ops - -Turns out the post-processor block on the G2 core is substantially -different from the one on the G1 core. Introduce hantro_postproc_ops -with .enable and .disable methods, which will allow to support -the G2 post-processor cleanly. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Andrzej Pietrasiewicz -Reviewed-by: Benjamin Gaignard -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/hantro.h | 5 +-- - drivers/staging/media/hantro/hantro_hw.h | 13 ++++++- - .../staging/media/hantro/hantro_postproc.c | 35 +++++++++++++------ - drivers/staging/media/hantro/imx8m_vpu_hw.c | 2 +- - .../staging/media/hantro/rockchip_vpu_hw.c | 6 ++-- - .../staging/media/hantro/sama5d4_vdec_hw.c | 2 +- - 6 files changed, 45 insertions(+), 18 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index c2e2dca38628..c2e01959dc00 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -28,6 +28,7 @@ - - struct hantro_ctx; - struct hantro_codec_ops; -+struct hantro_postproc_ops; - - #define HANTRO_JPEG_ENCODER BIT(0) - #define HANTRO_ENCODERS 0x0000ffff -@@ -59,6 +60,7 @@ struct hantro_irq { - * @num_dec_fmts: Number of decoder formats. - * @postproc_fmts: Post-processor formats. - * @num_postproc_fmts: Number of post-processor formats. -+ * @postproc_ops: Post-processor ops. - * @codec: Supported codecs - * @codec_ops: Codec ops. - * @init: Initialize hardware, optional. -@@ -69,7 +71,6 @@ struct hantro_irq { - * @num_clocks: number of clocks in the array - * @reg_names: array of register range names - * @num_regs: number of register range names in the array -- * @postproc_regs: &struct hantro_postproc_regs pointer - */ - struct hantro_variant { - unsigned int enc_offset; -@@ -80,6 +81,7 @@ struct hantro_variant { - unsigned int num_dec_fmts; - const struct hantro_fmt *postproc_fmts; - unsigned int num_postproc_fmts; -+ const struct hantro_postproc_ops *postproc_ops; - unsigned int codec; - const struct hantro_codec_ops *codec_ops; - int (*init)(struct hantro_dev *vpu); -@@ -90,7 +92,6 @@ struct hantro_variant { - int num_clocks; - const char * const *reg_names; - int num_regs; -- const struct hantro_postproc_regs *postproc_regs; - }; - - /** -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index 267a6d33a47b..2f85430682d8 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -174,6 +174,17 @@ struct hantro_postproc_ctx { - struct hantro_aux_buf dec_q[VB2_MAX_FRAME]; - }; - -+/** -+ * struct hantro_postproc_ops - post-processor operations -+ * -+ * @enable: Enable the post-processor block. Optional. -+ * @disable: Disable the post-processor block. Optional. -+ */ -+struct hantro_postproc_ops { -+ void (*enable)(struct hantro_ctx *ctx); -+ void (*disable)(struct hantro_ctx *ctx); -+}; -+ - /** - * struct hantro_codec_ops - codec mode specific operations - * -@@ -221,7 +232,7 @@ extern const struct hantro_variant rk3328_vpu_variant; - extern const struct hantro_variant rk3399_vpu_variant; - extern const struct hantro_variant sama5d4_vdec_variant; - --extern const struct hantro_postproc_regs hantro_g1_postproc_regs; -+extern const struct hantro_postproc_ops hantro_g1_postproc_ops; - - extern const u32 hantro_vp8_dec_mc_filter[8][6]; - -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index 07842152003f..882fb8bc5ddd 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -15,14 +15,14 @@ - #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \ - { \ - hantro_reg_write(vpu, \ -- &(vpu)->variant->postproc_regs->reg_name, \ -+ &hantro_g1_postproc_regs.reg_name, \ - val); \ - } - - #define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \ - { \ - hantro_reg_write_s(vpu, \ -- &(vpu)->variant->postproc_regs->reg_name, \ -+ &hantro_g1_postproc_regs.reg_name, \ - val); \ - } - -@@ -64,16 +64,13 @@ bool hantro_needs_postproc(const struct hantro_ctx *ctx, - return fmt->fourcc != V4L2_PIX_FMT_NV12; - } - --void hantro_postproc_enable(struct hantro_ctx *ctx) -+static void hantro_postproc_g1_enable(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; - struct vb2_v4l2_buffer *dst_buf; - u32 src_pp_fmt, dst_pp_fmt; - dma_addr_t dst_dma; - -- if (!vpu->variant->postproc_regs) -- return; -- - /* Turn on pipeline mode. Must be done first. */ - HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x1); - -@@ -154,12 +151,30 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx) - return 0; - } - --void hantro_postproc_disable(struct hantro_ctx *ctx) -+static void hantro_postproc_g1_disable(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; - -- if (!vpu->variant->postproc_regs) -- return; -- - HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0); - } -+ -+void hantro_postproc_disable(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ -+ if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->disable) -+ vpu->variant->postproc_ops->disable(ctx); -+} -+ -+void hantro_postproc_enable(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ -+ if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->enable) -+ vpu->variant->postproc_ops->enable(ctx); -+} -+ -+const struct hantro_postproc_ops hantro_g1_postproc_ops = { -+ .enable = hantro_postproc_g1_enable, -+ .disable = hantro_postproc_g1_disable, -+}; -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index ea919bfb9891..22fa7d2f3b64 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -262,7 +262,7 @@ const struct hantro_variant imx8mq_vpu_variant = { - .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts), - .postproc_fmts = imx8m_vpu_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts), -- .postproc_regs = &hantro_g1_postproc_regs, -+ .postproc_ops = &hantro_g1_postproc_ops, - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | - HANTRO_H264_DECODER, - .codec_ops = imx8mq_vpu_codec_ops, -diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c -index d4f52957cc53..6c1ad5534ce5 100644 ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -460,7 +460,7 @@ const struct hantro_variant rk3036_vpu_variant = { - .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts), - .postproc_fmts = rockchip_vpu1_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts), -- .postproc_regs = &hantro_g1_postproc_regs, -+ .postproc_ops = &hantro_g1_postproc_ops, - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | - HANTRO_H264_DECODER, - .codec_ops = rk3036_vpu_codec_ops, -@@ -485,7 +485,7 @@ const struct hantro_variant rk3066_vpu_variant = { - .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts), - .postproc_fmts = rockchip_vpu1_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts), -- .postproc_regs = &hantro_g1_postproc_regs, -+ .postproc_ops = &hantro_g1_postproc_ops, - .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | - HANTRO_VP8_DECODER | HANTRO_H264_DECODER, - .codec_ops = rk3066_vpu_codec_ops, -@@ -505,7 +505,7 @@ const struct hantro_variant rk3288_vpu_variant = { - .num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts), - .postproc_fmts = rockchip_vpu1_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts), -- .postproc_regs = &hantro_g1_postproc_regs, -+ .postproc_ops = &hantro_g1_postproc_ops, - .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | - HANTRO_VP8_DECODER | HANTRO_H264_DECODER, - .codec_ops = rk3288_vpu_codec_ops, -diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c -index 9c3b8cd0b239..f3fecc7248c4 100644 ---- a/drivers/staging/media/hantro/sama5d4_vdec_hw.c -+++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c -@@ -100,7 +100,7 @@ const struct hantro_variant sama5d4_vdec_variant = { - .num_dec_fmts = ARRAY_SIZE(sama5d4_vdec_fmts), - .postproc_fmts = sama5d4_vdec_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(sama5d4_vdec_postproc_fmts), -- .postproc_regs = &hantro_g1_postproc_regs, -+ .postproc_ops = &hantro_g1_postproc_ops, - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | - HANTRO_H264_DECODER, - .codec_ops = sama5d4_vdec_codec_ops, diff --git a/projects/Allwinner/patches/linux/0069-hantro-Simplify-postprocessor.patch b/projects/Allwinner/patches/linux/0069-hantro-Simplify-postprocessor.patch deleted file mode 100644 index b97d1f284d..0000000000 --- a/projects/Allwinner/patches/linux/0069-hantro-Simplify-postprocessor.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Tue, 16 Nov 2021 15:38:33 +0100 -Subject: [PATCH] hantro: Simplify postprocessor - -Add a 'postprocessed' boolean property to struct hantro_fmt -to signal that a format is produced by the post-processor. -This will allow to introduce the G2 post-processor in a simple way. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/hantro.h | 2 ++ - drivers/staging/media/hantro/hantro_postproc.c | 8 +------- - drivers/staging/media/hantro/imx8m_vpu_hw.c | 1 + - drivers/staging/media/hantro/rockchip_vpu_hw.c | 1 + - drivers/staging/media/hantro/sama5d4_vdec_hw.c | 1 + - 5 files changed, 6 insertions(+), 7 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index c2e01959dc00..dd5e56765d4e 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -263,6 +263,7 @@ struct hantro_ctx { - * @max_depth: Maximum depth, for bitstream formats - * @enc_fmt: Format identifier for encoder registers. - * @frmsize: Supported range of frame sizes (only for bitstream formats). -+ * @postprocessed: Indicates if this format needs the post-processor. - */ - struct hantro_fmt { - char *name; -@@ -272,6 +273,7 @@ struct hantro_fmt { - int max_depth; - enum hantro_enc_fmt enc_fmt; - struct v4l2_frmsize_stepwise frmsize; -+ bool postprocessed; - }; - - struct hantro_reg { -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index 882fb8bc5ddd..4549aec08feb 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -53,15 +53,9 @@ const struct hantro_postproc_regs hantro_g1_postproc_regs = { - bool hantro_needs_postproc(const struct hantro_ctx *ctx, - const struct hantro_fmt *fmt) - { -- struct hantro_dev *vpu = ctx->dev; -- - if (ctx->is_encoder) - return false; -- -- if (!vpu->variant->postproc_fmts) -- return false; -- -- return fmt->fourcc != V4L2_PIX_FMT_NV12; -+ return fmt->postprocessed; - } - - static void hantro_postproc_g1_enable(struct hantro_ctx *ctx) -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index 22fa7d2f3b64..02e61438220a 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -82,6 +82,7 @@ static const struct hantro_fmt imx8m_vpu_postproc_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_YUYV, - .codec_mode = HANTRO_MODE_NONE, -+ .postprocessed = true, - }, - }; - -diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c -index 6c1ad5534ce5..f372f767d4ff 100644 ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -62,6 +62,7 @@ static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_YUYV, - .codec_mode = HANTRO_MODE_NONE, -+ .postprocessed = true, - }, - }; - -diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c -index f3fecc7248c4..b2fc1c5613e1 100644 ---- a/drivers/staging/media/hantro/sama5d4_vdec_hw.c -+++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c -@@ -15,6 +15,7 @@ static const struct hantro_fmt sama5d4_vdec_postproc_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_YUYV, - .codec_mode = HANTRO_MODE_NONE, -+ .postprocessed = true, - }, - }; - diff --git a/projects/Allwinner/patches/linux/0070-hantro-Add-quirk-for-NV12-NV12_4L4-capture-format.patch b/projects/Allwinner/patches/linux/0070-hantro-Add-quirk-for-NV12-NV12_4L4-capture-format.patch deleted file mode 100644 index d28bfa4a7a..0000000000 --- a/projects/Allwinner/patches/linux/0070-hantro-Add-quirk-for-NV12-NV12_4L4-capture-format.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Tue, 16 Nov 2021 15:38:34 +0100 -Subject: [PATCH] hantro: Add quirk for NV12/NV12_4L4 capture format - -The G2 core decoder engine produces NV12_4L4 format, -which is a simple NV12 4x4 tiled format. The driver currently -hides this format by always enabling the post-processor engine, -and therefore offering NV12 directly. - -This is done without using the logic in hantro_postproc.c -and therefore makes it difficult to add VP9 cleanly. - -Since fixing this is not easy, add a small quirk to force -NV12 if HEVC was configured, but otherwise declare NV12_4L4 -as the pixel format in imx8mq_vpu_g2_variant.dec_fmts. - -This will be used by the VP9 decoder which will be added soon. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/hantro_v4l2.c | 14 ++++++++++++++ - drivers/staging/media/hantro/imx8m_vpu_hw.c | 2 +- - 2 files changed, 15 insertions(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c -index bcb0bdff4a9a..d1f060c55fed 100644 ---- a/drivers/staging/media/hantro/hantro_v4l2.c -+++ b/drivers/staging/media/hantro/hantro_v4l2.c -@@ -150,6 +150,20 @@ static int vidioc_enum_fmt(struct file *file, void *priv, - unsigned int num_fmts, i, j = 0; - bool skip_mode_none; - -+ /* -+ * The HEVC decoder on the G2 core needs a little quirk to offer NV12 -+ * only on the capture side. Once the post-processor logic is used, -+ * we will be able to expose NV12_4L4 and NV12 as the other cases, -+ * and therefore remove this quirk. -+ */ -+ if (capture && ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE) { -+ if (f->index == 0) { -+ f->pixelformat = V4L2_PIX_FMT_NV12; -+ return 0; -+ } -+ return -EINVAL; -+ } -+ - /* - * When dealing with an encoder: - * - on the capture side we want to filter out all MODE_NONE formats. -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index 02e61438220a..a40b161e5956 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -134,7 +134,7 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = { - - static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = { - { -- .fourcc = V4L2_PIX_FMT_NV12, -+ .fourcc = V4L2_PIX_FMT_NV12_4L4, - .codec_mode = HANTRO_MODE_NONE, - }, - { diff --git a/projects/Allwinner/patches/linux/0071-media-uapi-Add-VP9-stateless-decoder-controls.patch b/projects/Allwinner/patches/linux/0071-media-uapi-Add-VP9-stateless-decoder-controls.patch deleted file mode 100644 index 32ed31131e..0000000000 --- a/projects/Allwinner/patches/linux/0071-media-uapi-Add-VP9-stateless-decoder-controls.patch +++ /dev/null @@ -1,1309 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:35 +0100 -Subject: [PATCH] media: uapi: Add VP9 stateless decoder controls - -Add the VP9 stateless decoder controls plus the documentation that goes -with it. - -Signed-off-by: Boris Brezillon -Co-developed-by: Ezequiel Garcia -Signed-off-by: Ezequiel Garcia -Signed-off-by: Adrian Ratiu -Signed-off-by: Andrzej Pietrasiewicz -Co-developed-by: Daniel Almeida -Signed-off-by: Daniel Almeida -Signed-off-by: Hans Verkuil ---- - .../userspace-api/media/v4l/biblio.rst | 10 + - .../media/v4l/ext-ctrls-codec-stateless.rst | 573 ++++++++++++++++++ - .../media/v4l/pixfmt-compressed.rst | 15 + - .../media/v4l/vidioc-g-ext-ctrls.rst | 8 + - .../media/v4l/vidioc-queryctrl.rst | 12 + - .../media/videodev2.h.rst.exceptions | 2 + - drivers/media/v4l2-core/v4l2-ctrls-core.c | 180 ++++++ - drivers/media/v4l2-core/v4l2-ctrls-defs.c | 8 + - drivers/media/v4l2-core/v4l2-ioctl.c | 1 + - include/media/v4l2-ctrls.h | 4 + - include/uapi/linux/v4l2-controls.h | 284 +++++++++ - include/uapi/linux/videodev2.h | 6 + - 12 files changed, 1103 insertions(+) - -diff --git a/Documentation/userspace-api/media/v4l/biblio.rst b/Documentation/userspace-api/media/v4l/biblio.rst -index 7b8e6738ff9e..9cd18c153d19 100644 ---- a/Documentation/userspace-api/media/v4l/biblio.rst -+++ b/Documentation/userspace-api/media/v4l/biblio.rst -@@ -417,3 +417,13 @@ VP8 - :title: RFC 6386: "VP8 Data Format and Decoding Guide" - - :author: J. Bankoski et al. -+ -+.. _vp9: -+ -+VP9 -+=== -+ -+ -+:title: VP9 Bitstream & Decoding Process Specification -+ -+:author: Adrian Grange (Google), Peter de Rivaz (Argon Design), Jonathan Hunt (Argon Design) -diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst -index 72f5e85b4f34..cc080c4257d0 100644 ---- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst -+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst -@@ -1458,3 +1458,576 @@ FWHT Flags - .. raw:: latex - - \normalsize -+ -+.. _v4l2-codec-stateless-vp9: -+ -+``V4L2_CID_STATELESS_VP9_COMPRESSED_HDR (struct)`` -+ Stores VP9 probabilities updates as parsed from the current compressed frame -+ header. A value of zero in an array element means no update of the relevant -+ probability. Motion vector-related updates contain a new value or zero. All -+ other updates contain values translated with inv_map_table[] (see 6.3.5 in -+ :ref:`vp9`). -+ -+.. c:type:: v4l2_ctrl_vp9_compressed_hdr -+ -+.. tabularcolumns:: |p{1cm}|p{4.8cm}|p{11.4cm}| -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_vp9_compressed_hdr -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``tx_mode`` -+ - Specifies the TX mode. See :ref:`TX Mode ` for more details. -+ * - __u8 -+ - ``tx8[2][1]`` -+ - TX 8x8 probabilities delta. -+ * - __u8 -+ - ``tx16[2][2]`` -+ - TX 16x16 probabilities delta. -+ * - __u8 -+ - ``tx32[2][3]`` -+ - TX 32x32 probabilities delta. -+ * - __u8 -+ - ``coef[4][2][2][6][6][3]`` -+ - Coefficient probabilities delta. -+ * - __u8 -+ - ``skip[3]`` -+ - Skip probabilities delta. -+ * - __u8 -+ - ``inter_mode[7][3]`` -+ - Inter prediction mode probabilities delta. -+ * - __u8 -+ - ``interp_filter[4][2]`` -+ - Interpolation filter probabilities delta. -+ * - __u8 -+ - ``is_inter[4]`` -+ - Is inter-block probabilities delta. -+ * - __u8 -+ - ``comp_mode[5]`` -+ - Compound prediction mode probabilities delta. -+ * - __u8 -+ - ``single_ref[5][2]`` -+ - Single reference probabilities delta. -+ * - __u8 -+ - ``comp_ref[5]`` -+ - Compound reference probabilities delta. -+ * - __u8 -+ - ``y_mode[4][9]`` -+ - Y prediction mode probabilities delta. -+ * - __u8 -+ - ``uv_mode[10][9]`` -+ - UV prediction mode probabilities delta. -+ * - __u8 -+ - ``partition[16][3]`` -+ - Partition probabilities delta. -+ * - __u8 -+ - ``mv.joint[3]`` -+ - Motion vector joint probabilities delta. -+ * - __u8 -+ - ``mv.sign[2]`` -+ - Motion vector sign probabilities delta. -+ * - __u8 -+ - ``mv.classes[2][10]`` -+ - Motion vector class probabilities delta. -+ * - __u8 -+ - ``mv.class0_bit[2]`` -+ - Motion vector class0 bit probabilities delta. -+ * - __u8 -+ - ``mv.bits[2][10]`` -+ - Motion vector bits probabilities delta. -+ * - __u8 -+ - ``mv.class0_fr[2][2][3]`` -+ - Motion vector class0 fractional bit probabilities delta. -+ * - __u8 -+ - ``mv.fr[2][3]`` -+ - Motion vector fractional bit probabilities delta. -+ * - __u8 -+ - ``mv.class0_hp[2]`` -+ - Motion vector class0 high precision fractional bit probabilities delta. -+ * - __u8 -+ - ``mv.hp[2]`` -+ - Motion vector high precision fractional bit probabilities delta. -+ -+.. _vp9_tx_mode: -+ -+``TX Mode`` -+ -+.. tabularcolumns:: |p{6.5cm}|p{0.5cm}|p{10.3cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_TX_MODE_ONLY_4X4`` -+ - 0 -+ - Transform size is 4x4. -+ * - ``V4L2_VP9_TX_MODE_ALLOW_8X8`` -+ - 1 -+ - Transform size can be up to 8x8. -+ * - ``V4L2_VP9_TX_MODE_ALLOW_16X16`` -+ - 2 -+ - Transform size can be up to 16x16. -+ * - ``V4L2_VP9_TX_MODE_ALLOW_32X32`` -+ - 3 -+ - transform size can be up to 32x32. -+ * - ``V4L2_VP9_TX_MODE_SELECT`` -+ - 4 -+ - Bitstream contains the transform size for each block. -+ -+See section '7.3.1 Tx mode semantics' of the :ref:`vp9` specification for more details. -+ -+``V4L2_CID_STATELESS_VP9_FRAME (struct)`` -+ Specifies the frame parameters for the associated VP9 frame decode request. -+ This includes the necessary parameters for configuring a stateless hardware -+ decoding pipeline for VP9. The bitstream parameters are defined according -+ to :ref:`vp9`. -+ -+.. c:type:: v4l2_ctrl_vp9_frame -+ -+.. raw:: latex -+ -+ \small -+ -+.. tabularcolumns:: |p{4.7cm}|p{5.5cm}|p{7.1cm}| -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_vp9_frame -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - struct :c:type:`v4l2_vp9_loop_filter` -+ - ``lf`` -+ - Loop filter parameters. See struct :c:type:`v4l2_vp9_loop_filter` for more details. -+ * - struct :c:type:`v4l2_vp9_quantization` -+ - ``quant`` -+ - Quantization parameters. See :c:type:`v4l2_vp9_quantization` for more details. -+ * - struct :c:type:`v4l2_vp9_segmentation` -+ - ``seg`` -+ - Segmentation parameters. See :c:type:`v4l2_vp9_segmentation` for more details. -+ * - __u32 -+ - ``flags`` -+ - Combination of V4L2_VP9_FRAME_FLAG_* flags. See :ref:`Frame Flags`. -+ * - __u16 -+ - ``compressed_header_size`` -+ - Compressed header size in bytes. -+ * - __u16 -+ - ``uncompressed_header_size`` -+ - Uncompressed header size in bytes. -+ * - __u16 -+ - ``frame_width_minus_1`` -+ - Add 1 to get the frame width expressed in pixels. See section 7.2.3 in :ref:`vp9`. -+ * - __u16 -+ - ``frame_height_minus_1`` -+ - Add 1 to get the frame height expressed in pixels. See section 7.2.3 in :ref:`vp9`. -+ * - __u16 -+ - ``render_width_minus_1`` -+ - Add 1 to get the expected render width expressed in pixels. This is -+ not used during the decoding process but might be used by HW scalers to -+ prepare a frame that's ready for scanout. See section 7.2.4 in :ref:`vp9`. -+ * - __u16 -+ - render_height_minus_1 -+ - Add 1 to get the expected render height expressed in pixels. This is -+ not used during the decoding process but might be used by HW scalers to -+ prepare a frame that's ready for scanout. See section 7.2.4 in :ref:`vp9`. -+ * - __u64 -+ - ``last_frame_ts`` -+ - "last" reference buffer timestamp. -+ The timestamp refers to the ``timestamp`` field in -+ struct :c:type:`v4l2_buffer`. Use the :c:func:`v4l2_timeval_to_ns()` -+ function to convert the struct :c:type:`timeval` in struct -+ :c:type:`v4l2_buffer` to a __u64. -+ * - __u64 -+ - ``golden_frame_ts`` -+ - "golden" reference buffer timestamp. -+ The timestamp refers to the ``timestamp`` field in -+ struct :c:type:`v4l2_buffer`. Use the :c:func:`v4l2_timeval_to_ns()` -+ function to convert the struct :c:type:`timeval` in struct -+ :c:type:`v4l2_buffer` to a __u64. -+ * - __u64 -+ - ``alt_frame_ts`` -+ - "alt" reference buffer timestamp. -+ The timestamp refers to the ``timestamp`` field in -+ struct :c:type:`v4l2_buffer`. Use the :c:func:`v4l2_timeval_to_ns()` -+ function to convert the struct :c:type:`timeval` in struct -+ :c:type:`v4l2_buffer` to a __u64. -+ * - __u8 -+ - ``ref_frame_sign_bias`` -+ - a bitfield specifying whether the sign bias is set for a given -+ reference frame. See :ref:`Reference Frame Sign Bias` -+ for more details. -+ * - __u8 -+ - ``reset_frame_context`` -+ - specifies whether the frame context should be reset to default values. See -+ :ref:`Reset Frame Context` for more details. -+ * - __u8 -+ - ``frame_context_idx`` -+ - Frame context that should be used/updated. -+ * - __u8 -+ - ``profile`` -+ - VP9 profile. Can be 0, 1, 2 or 3. -+ * - __u8 -+ - ``bit_depth`` -+ - Component depth in bits. Can be 8, 10 or 12. Note that not all profiles -+ support 10 and/or 12 bits depths. -+ * - __u8 -+ - ``interpolation_filter`` -+ - Specifies the filter selection used for performing inter prediction. See -+ :ref:`Interpolation Filter` for more details. -+ * - __u8 -+ - ``tile_cols_log2`` -+ - Specifies the base 2 logarithm of the width of each tile (where the -+ width is measured in units of 8x8 blocks). Shall be less than or equal -+ to 6. -+ * - __u8 -+ - ``tile_rows_log2`` -+ - Specifies the base 2 logarithm of the height of each tile (where the -+ height is measured in units of 8x8 blocks). -+ * - __u8 -+ - ``reference_mode`` -+ - Specifies the type of inter prediction to be used. See -+ :ref:`Reference Mode` for more details. -+ * - __u8 -+ - ``reserved[7]`` -+ - Applications and drivers must set this to zero. -+ -+.. raw:: latex -+ -+ \normalsize -+ -+.. _vp9_frame_flags: -+ -+``Frame Flags`` -+ -+.. tabularcolumns:: |p{10.0cm}|p{1.2cm}|p{6.1cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_FRAME_FLAG_KEY_FRAME`` -+ - 0x001 -+ - The frame is a key frame. -+ * - ``V4L2_VP9_FRAME_FLAG_SHOW_FRAME`` -+ - 0x002 -+ - The frame should be displayed. -+ * - ``V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT`` -+ - 0x004 -+ - The decoding should be error resilient. -+ * - ``V4L2_VP9_FRAME_FLAG_INTRA_ONLY`` -+ - 0x008 -+ - The frame does not reference other frames. -+ * - ``V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV`` -+ - 0x010 -+ - The frame can use high precision motion vectors. -+ * - ``V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX`` -+ - 0x020 -+ - Frame context should be updated after decoding. -+ * - ``V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE`` -+ - 0x040 -+ - Parallel decoding is used. -+ * - ``V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING`` -+ - 0x080 -+ - Vertical subsampling is enabled. -+ * - ``V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING`` -+ - 0x100 -+ - Horizontal subsampling is enabled. -+ * - ``V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING`` -+ - 0x200 -+ - The full UV range is used. -+ -+.. _vp9_ref_frame_sign_bias: -+ -+``Reference Frame Sign Bias`` -+ -+.. tabularcolumns:: |p{7.0cm}|p{1.2cm}|p{9.1cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_SIGN_BIAS_LAST`` -+ - 0x1 -+ - Sign bias is set for the last reference frame. -+ * - ``V4L2_VP9_SIGN_BIAS_GOLDEN`` -+ - 0x2 -+ - Sign bias is set for the golden reference frame. -+ * - ``V4L2_VP9_SIGN_BIAS_ALT`` -+ - 0x2 -+ - Sign bias is set for the alt reference frame. -+ -+.. _vp9_reset_frame_context: -+ -+``Reset Frame Context`` -+ -+.. tabularcolumns:: |p{7.0cm}|p{1.2cm}|p{9.1cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_RESET_FRAME_CTX_NONE`` -+ - 0 -+ - Do not reset any frame context. -+ * - ``V4L2_VP9_RESET_FRAME_CTX_SPEC`` -+ - 1 -+ - Reset the frame context pointed to by -+ :c:type:`v4l2_ctrl_vp9_frame`.frame_context_idx. -+ * - ``V4L2_VP9_RESET_FRAME_CTX_ALL`` -+ - 2 -+ - Reset all frame contexts. -+ -+See section '7.2 Uncompressed header semantics' of the :ref:`vp9` specification -+for more details. -+ -+.. _vp9_interpolation_filter: -+ -+``Interpolation Filter`` -+ -+.. tabularcolumns:: |p{9.0cm}|p{1.2cm}|p{7.1cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_INTERP_FILTER_EIGHTTAP`` -+ - 0 -+ - Eight tap filter. -+ * - ``V4L2_VP9_INTERP_FILTER_EIGHTTAP_SMOOTH`` -+ - 1 -+ - Eight tap smooth filter. -+ * - ``V4L2_VP9_INTERP_FILTER_EIGHTTAP_SHARP`` -+ - 2 -+ - Eeight tap sharp filter. -+ * - ``V4L2_VP9_INTERP_FILTER_BILINEAR`` -+ - 3 -+ - Bilinear filter. -+ * - ``V4L2_VP9_INTERP_FILTER_SWITCHABLE`` -+ - 4 -+ - Filter selection is signaled at the block level. -+ -+See section '7.2.7 Interpolation filter semantics' of the :ref:`vp9` specification -+for more details. -+ -+.. _vp9_reference_mode: -+ -+``Reference Mode`` -+ -+.. tabularcolumns:: |p{9.6cm}|p{0.5cm}|p{7.2cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_REFERENCE_MODE_SINGLE_REFERENCE`` -+ - 0 -+ - Indicates that all the inter blocks use only a single reference frame -+ to generate motion compensated prediction. -+ * - ``V4L2_VP9_REFERENCE_MODE_COMPOUND_REFERENCE`` -+ - 1 -+ - Requires all the inter blocks to use compound mode. Single reference -+ frame prediction is not allowed. -+ * - ``V4L2_VP9_REFERENCE_MODE_SELECT`` -+ - 2 -+ - Allows each individual inter block to select between single and -+ compound prediction modes. -+ -+See section '7.3.6 Frame reference mode semantics' of the :ref:`vp9` specification for more details. -+ -+.. c:type:: v4l2_vp9_segmentation -+ -+Encodes the quantization parameters. See section '7.2.10 Segmentation -+params syntax' of the :ref:`vp9` specification for more details. -+ -+.. tabularcolumns:: |p{0.8cm}|p{5cm}|p{11.4cm}| -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_vp9_segmentation -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``feature_data[8][4]`` -+ - Data attached to each feature. Data entry is only valid if the feature -+ is enabled. The array shall be indexed with segment number as the first dimension -+ (0..7) and one of V4L2_VP9_SEG_* as the second dimension. -+ See :ref:`Segment Feature IDs`. -+ * - __u8 -+ - ``feature_enabled[8]`` -+ - Bitmask defining which features are enabled in each segment. The value for each -+ segment is a combination of V4L2_VP9_SEGMENT_FEATURE_ENABLED(id) values where id is -+ one of V4L2_VP9_SEG_*. See :ref:`Segment Feature IDs`. -+ * - __u8 -+ - ``tree_probs[7]`` -+ - Specifies the probability values to be used when decoding a Segment-ID. -+ See '5.15. Segmentation map' section of :ref:`vp9` for more details. -+ * - __u8 -+ - ``pred_probs[3]`` -+ - Specifies the probability values to be used when decoding a -+ Predicted-Segment-ID. See '6.4.14. Get segment id syntax' -+ section of :ref:`vp9` for more details. -+ * - __u8 -+ - ``flags`` -+ - Combination of V4L2_VP9_SEGMENTATION_FLAG_* flags. See -+ :ref:`Segmentation Flags`. -+ * - __u8 -+ - ``reserved[5]`` -+ - Applications and drivers must set this to zero. -+ -+.. _vp9_segment_feature: -+ -+``Segment feature IDs`` -+ -+.. tabularcolumns:: |p{6.0cm}|p{1cm}|p{10.3cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_SEG_LVL_ALT_Q`` -+ - 0 -+ - Quantizer segment feature. -+ * - ``V4L2_VP9_SEG_LVL_ALT_L`` -+ - 1 -+ - Loop filter segment feature. -+ * - ``V4L2_VP9_SEG_LVL_REF_FRAME`` -+ - 2 -+ - Reference frame segment feature. -+ * - ``V4L2_VP9_SEG_LVL_SKIP`` -+ - 3 -+ - Skip segment feature. -+ * - ``V4L2_VP9_SEG_LVL_MAX`` -+ - 4 -+ - Number of segment features. -+ -+.. _vp9_segmentation_flags: -+ -+``Segmentation Flags`` -+ -+.. tabularcolumns:: |p{10.6cm}|p{0.8cm}|p{5.9cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_SEGMENTATION_FLAG_ENABLED`` -+ - 0x01 -+ - Indicates that this frame makes use of the segmentation tool. -+ * - ``V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP`` -+ - 0x02 -+ - Indicates that the segmentation map should be updated during the -+ decoding of this frame. -+ * - ``V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE`` -+ - 0x04 -+ - Indicates that the updates to the segmentation map are coded -+ relative to the existing segmentation map. -+ * - ``V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA`` -+ - 0x08 -+ - Indicates that new parameters are about to be specified for each -+ segment. -+ * - ``V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE`` -+ - 0x10 -+ - Indicates that the segmentation parameters represent the actual values -+ to be used. -+ -+.. c:type:: v4l2_vp9_quantization -+ -+Encodes the quantization parameters. See section '7.2.9 Quantization params -+syntax' of the VP9 specification for more details. -+ -+.. tabularcolumns:: |p{0.8cm}|p{4cm}|p{12.4cm}| -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_vp9_quantization -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``base_q_idx`` -+ - Indicates the base frame qindex. -+ * - __s8 -+ - ``delta_q_y_dc`` -+ - Indicates the Y DC quantizer relative to base_q_idx. -+ * - __s8 -+ - ``delta_q_uv_dc`` -+ - Indicates the UV DC quantizer relative to base_q_idx. -+ * - __s8 -+ - ``delta_q_uv_ac`` -+ - Indicates the UV AC quantizer relative to base_q_idx. -+ * - __u8 -+ - ``reserved[4]`` -+ - Applications and drivers must set this to zero. -+ -+.. c:type:: v4l2_vp9_loop_filter -+ -+This structure contains all loop filter related parameters. See sections -+'7.2.8 Loop filter semantics' of the :ref:`vp9` specification for more details. -+ -+.. tabularcolumns:: |p{0.8cm}|p{4cm}|p{12.4cm}| -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_vp9_loop_filter -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __s8 -+ - ``ref_deltas[4]`` -+ - Contains the adjustment needed for the filter level based on the chosen -+ reference frame. -+ * - __s8 -+ - ``mode_deltas[2]`` -+ - Contains the adjustment needed for the filter level based on the chosen -+ mode. -+ * - __u8 -+ - ``level`` -+ - Indicates the loop filter strength. -+ * - __u8 -+ - ``sharpness`` -+ - Indicates the sharpness level. -+ * - __u8 -+ - ``flags`` -+ - Combination of V4L2_VP9_LOOP_FILTER_FLAG_* flags. -+ See :ref:`Loop Filter Flags `. -+ * - __u8 -+ - ``reserved[7]`` -+ - Applications and drivers must set this to zero. -+ -+ -+.. _vp9_loop_filter_flags: -+ -+``Loop Filter Flags`` -+ -+.. tabularcolumns:: |p{9.6cm}|p{0.5cm}|p{7.2cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED`` -+ - 0x1 -+ - When set, the filter level depends on the mode and reference frame used -+ to predict a block. -+ * - ``V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE`` -+ - 0x2 -+ - When set, the bitstream contains additional syntax elements that -+ specify which mode and reference frame deltas are to be updated. -diff --git a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -index 0ede39907ee2..967fc803ef94 100644 ---- a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -+++ b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -@@ -172,6 +172,21 @@ Compressed Formats - - VP9 compressed video frame. The encoder generates one - compressed frame per buffer, and the decoder requires one - compressed frame per buffer. -+ * .. _V4L2-PIX-FMT-VP9-FRAME: -+ -+ - ``V4L2_PIX_FMT_VP9_FRAME`` -+ - 'VP9F' -+ - VP9 parsed frame, including the frame header, as extracted from the container. -+ This format is adapted for stateless video decoders that implement a -+ VP9 pipeline with the :ref:`stateless_decoder`. -+ Metadata associated with the frame to decode is required to be passed -+ through the ``V4L2_CID_STATELESS_VP9_FRAME`` and -+ the ``V4L2_CID_STATELESS_VP9_COMPRESSED_HDR`` controls. -+ See the :ref:`associated Codec Control IDs `. -+ Exactly one output and one capture buffer must be provided for use with -+ this pixel format. The output buffer must contain the appropriate number -+ of macroblocks to decode a full corresponding frame to the matching -+ capture buffer. - * .. _V4L2-PIX-FMT-HEVC: - - - ``V4L2_PIX_FMT_HEVC`` -diff --git a/Documentation/userspace-api/media/v4l/vidioc-g-ext-ctrls.rst b/Documentation/userspace-api/media/v4l/vidioc-g-ext-ctrls.rst -index fdde0ae6d521..29971a45a2d4 100644 ---- a/Documentation/userspace-api/media/v4l/vidioc-g-ext-ctrls.rst -+++ b/Documentation/userspace-api/media/v4l/vidioc-g-ext-ctrls.rst -@@ -233,6 +233,14 @@ still cause this situation. - - ``p_mpeg2_quantisation`` - - A pointer to a struct :c:type:`v4l2_ctrl_mpeg2_quantisation`. Valid if this control is - of type ``V4L2_CTRL_TYPE_MPEG2_QUANTISATION``. -+ * - struct :c:type:`v4l2_ctrl_vp9_compressed_hdr` * -+ - ``p_vp9_compressed_hdr_probs`` -+ - A pointer to a struct :c:type:`v4l2_ctrl_vp9_compressed_hdr`. Valid if this -+ control is of type ``V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR``. -+ * - struct :c:type:`v4l2_ctrl_vp9_frame` * -+ - ``p_vp9_frame`` -+ - A pointer to a struct :c:type:`v4l2_ctrl_vp9_frame`. Valid if this -+ control is of type ``V4L2_CTRL_TYPE_VP9_FRAME``. - * - struct :c:type:`v4l2_ctrl_hdr10_cll_info` * - - ``p_hdr10_cll`` - - A pointer to a struct :c:type:`v4l2_ctrl_hdr10_cll_info`. Valid if this control is -diff --git a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst -index 2f491c17dd5d..88f630252d98 100644 ---- a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst -+++ b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst -@@ -513,6 +513,18 @@ See also the examples in :ref:`control`. - - n/a - - A struct :c:type:`v4l2_ctrl_hevc_decode_params`, containing HEVC - decoding parameters for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_vp9_compressed_hdr`, containing VP9 -+ probabilities updates for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_VP9_FRAME`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_vp9_frame`, containing VP9 -+ frame decode parameters for stateless video decoders. - - .. raw:: latex - -diff --git a/Documentation/userspace-api/media/videodev2.h.rst.exceptions b/Documentation/userspace-api/media/videodev2.h.rst.exceptions -index eb0b1cd37abd..9cbb7a0c354a 100644 ---- a/Documentation/userspace-api/media/videodev2.h.rst.exceptions -+++ b/Documentation/userspace-api/media/videodev2.h.rst.exceptions -@@ -149,6 +149,8 @@ replace symbol V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_AREA :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_FWHT_PARAMS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_VP8_FRAME :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_VP9_FRAME :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_HDR10_CLL_INFO :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_HDR10_MASTERING_DISPLAY :c:type:`v4l2_ctrl_type` - -diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c -index 70adfc1b9c81..54abe5245dcc 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls-core.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c -@@ -283,6 +283,12 @@ static void std_log(const struct v4l2_ctrl *ctrl) - case V4L2_CTRL_TYPE_MPEG2_PICTURE: - pr_cont("MPEG2_PICTURE"); - break; -+ case V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR: -+ pr_cont("VP9_COMPRESSED_HDR"); -+ break; -+ case V4L2_CTRL_TYPE_VP9_FRAME: -+ pr_cont("VP9_FRAME"); -+ break; - default: - pr_cont("unknown type %d", ctrl->type); - break; -@@ -317,6 +323,168 @@ static void std_log(const struct v4l2_ctrl *ctrl) - #define zero_reserved(s) \ - memset(&(s).reserved, 0, sizeof((s).reserved)) - -+static int -+validate_vp9_lf_params(struct v4l2_vp9_loop_filter *lf) -+{ -+ unsigned int i; -+ -+ if (lf->flags & ~(V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED | -+ V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE)) -+ return -EINVAL; -+ -+ /* That all values are in the accepted range. */ -+ if (lf->level > GENMASK(5, 0)) -+ return -EINVAL; -+ -+ if (lf->sharpness > GENMASK(2, 0)) -+ return -EINVAL; -+ -+ for (i = 0; i < ARRAY_SIZE(lf->ref_deltas); i++) -+ if (lf->ref_deltas[i] < -63 || lf->ref_deltas[i] > 63) -+ return -EINVAL; -+ -+ for (i = 0; i < ARRAY_SIZE(lf->mode_deltas); i++) -+ if (lf->mode_deltas[i] < -63 || lf->mode_deltas[i] > 63) -+ return -EINVAL; -+ -+ zero_reserved(*lf); -+ return 0; -+} -+ -+static int -+validate_vp9_quant_params(struct v4l2_vp9_quantization *quant) -+{ -+ if (quant->delta_q_y_dc < -15 || quant->delta_q_y_dc > 15 || -+ quant->delta_q_uv_dc < -15 || quant->delta_q_uv_dc > 15 || -+ quant->delta_q_uv_ac < -15 || quant->delta_q_uv_ac > 15) -+ return -EINVAL; -+ -+ zero_reserved(*quant); -+ return 0; -+} -+ -+static int -+validate_vp9_seg_params(struct v4l2_vp9_segmentation *seg) -+{ -+ unsigned int i, j; -+ -+ if (seg->flags & ~(V4L2_VP9_SEGMENTATION_FLAG_ENABLED | -+ V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP | -+ V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE | -+ V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA | -+ V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE)) -+ return -EINVAL; -+ -+ for (i = 0; i < ARRAY_SIZE(seg->feature_enabled); i++) { -+ if (seg->feature_enabled[i] & -+ ~V4L2_VP9_SEGMENT_FEATURE_ENABLED_MASK) -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(seg->feature_data); i++) { -+ const int range[] = { 255, 63, 3, 0 }; -+ -+ for (j = 0; j < ARRAY_SIZE(seg->feature_data[j]); j++) { -+ if (seg->feature_data[i][j] < -range[j] || -+ seg->feature_data[i][j] > range[j]) -+ return -EINVAL; -+ } -+ } -+ -+ zero_reserved(*seg); -+ return 0; -+} -+ -+static int -+validate_vp9_compressed_hdr(struct v4l2_ctrl_vp9_compressed_hdr *hdr) -+{ -+ if (hdr->tx_mode > V4L2_VP9_TX_MODE_SELECT) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static int -+validate_vp9_frame(struct v4l2_ctrl_vp9_frame *frame) -+{ -+ int ret; -+ -+ /* Make sure we're not passed invalid flags. */ -+ if (frame->flags & ~(V4L2_VP9_FRAME_FLAG_KEY_FRAME | -+ V4L2_VP9_FRAME_FLAG_SHOW_FRAME | -+ V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT | -+ V4L2_VP9_FRAME_FLAG_INTRA_ONLY | -+ V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV | -+ V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX | -+ V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE | -+ V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING | -+ V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING | -+ V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING)) -+ return -EINVAL; -+ -+ if (frame->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT && -+ frame->flags & V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX) -+ return -EINVAL; -+ -+ if (frame->profile > V4L2_VP9_PROFILE_MAX) -+ return -EINVAL; -+ -+ if (frame->reset_frame_context > V4L2_VP9_RESET_FRAME_CTX_ALL) -+ return -EINVAL; -+ -+ if (frame->frame_context_idx >= V4L2_VP9_NUM_FRAME_CTX) -+ return -EINVAL; -+ -+ /* -+ * Profiles 0 and 1 only support 8-bit depth, profiles 2 and 3 only 10 -+ * and 12 bit depths. -+ */ -+ if ((frame->profile < 2 && frame->bit_depth != 8) || -+ (frame->profile >= 2 && -+ (frame->bit_depth != 10 && frame->bit_depth != 12))) -+ return -EINVAL; -+ -+ /* Profile 0 and 2 only accept YUV 4:2:0. */ -+ if ((frame->profile == 0 || frame->profile == 2) && -+ (!(frame->flags & V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING) || -+ !(frame->flags & V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING))) -+ return -EINVAL; -+ -+ /* Profile 1 and 3 only accept YUV 4:2:2, 4:4:0 and 4:4:4. */ -+ if ((frame->profile == 1 || frame->profile == 3) && -+ ((frame->flags & V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING) && -+ (frame->flags & V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING))) -+ return -EINVAL; -+ -+ if (frame->interpolation_filter > V4L2_VP9_INTERP_FILTER_SWITCHABLE) -+ return -EINVAL; -+ -+ /* -+ * According to the spec, tile_cols_log2 shall be less than or equal -+ * to 6. -+ */ -+ if (frame->tile_cols_log2 > 6) -+ return -EINVAL; -+ -+ if (frame->reference_mode > V4L2_VP9_REFERENCE_MODE_SELECT) -+ return -EINVAL; -+ -+ ret = validate_vp9_lf_params(&frame->lf); -+ if (ret) -+ return ret; -+ -+ ret = validate_vp9_quant_params(&frame->quant); -+ if (ret) -+ return ret; -+ -+ ret = validate_vp9_seg_params(&frame->seg); -+ if (ret) -+ return ret; -+ -+ zero_reserved(*frame); -+ return 0; -+} -+ - /* - * Compound controls validation requires setting unused fields/flags to zero - * in order to properly detect unchanged controls with std_equal's memcmp. -@@ -690,6 +858,12 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, - case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: - break; - -+ case V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR: -+ return validate_vp9_compressed_hdr(p); -+ -+ case V4L2_CTRL_TYPE_VP9_FRAME: -+ return validate_vp9_frame(p); -+ - case V4L2_CTRL_TYPE_AREA: - area = p; - if (!area->width || !area->height) -@@ -1255,6 +1429,12 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, - case V4L2_CTRL_TYPE_HDR10_MASTERING_DISPLAY: - elem_size = sizeof(struct v4l2_ctrl_hdr10_mastering_display); - break; -+ case V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR: -+ elem_size = sizeof(struct v4l2_ctrl_vp9_compressed_hdr); -+ break; -+ case V4L2_CTRL_TYPE_VP9_FRAME: -+ elem_size = sizeof(struct v4l2_ctrl_vp9_frame); -+ break; - case V4L2_CTRL_TYPE_AREA: - elem_size = sizeof(struct v4l2_area); - break; -diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c -index ebe82b6ba6e6..23594568b985 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c -@@ -1177,6 +1177,8 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_STATELESS_MPEG2_SEQUENCE: return "MPEG-2 Sequence Header"; - case V4L2_CID_STATELESS_MPEG2_PICTURE: return "MPEG-2 Picture Header"; - case V4L2_CID_STATELESS_MPEG2_QUANTISATION: return "MPEG-2 Quantisation Matrices"; -+ case V4L2_CID_STATELESS_VP9_COMPRESSED_HDR: return "VP9 Probabilities Updates"; -+ case V4L2_CID_STATELESS_VP9_FRAME: return "VP9 Frame Decode Parameters"; - - /* Colorimetry controls */ - /* Keep the order of the 'case's the same as in v4l2-controls.h! */ -@@ -1498,6 +1500,12 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS: - *type = V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS; - break; -+ case V4L2_CID_STATELESS_VP9_COMPRESSED_HDR: -+ *type = V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR; -+ break; -+ case V4L2_CID_STATELESS_VP9_FRAME: -+ *type = V4L2_CTRL_TYPE_VP9_FRAME; -+ break; - case V4L2_CID_UNIT_CELL_SIZE: - *type = V4L2_CTRL_TYPE_AREA; - *flags |= V4L2_CTRL_FLAG_READ_ONLY; -diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 31d0109ce5a8..51289d4741dc 100644 ---- a/drivers/media/v4l2-core/v4l2-ioctl.c -+++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1413,6 +1413,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) - case V4L2_PIX_FMT_VP8: descr = "VP8"; break; - case V4L2_PIX_FMT_VP8_FRAME: descr = "VP8 Frame"; break; - case V4L2_PIX_FMT_VP9: descr = "VP9"; break; -+ case V4L2_PIX_FMT_VP9_FRAME: descr = "VP9 Frame"; break; - case V4L2_PIX_FMT_HEVC: descr = "HEVC"; break; /* aka H.265 */ - case V4L2_PIX_FMT_HEVC_SLICE: descr = "HEVC Parsed Slice Data"; break; - case V4L2_PIX_FMT_FWHT: descr = "FWHT"; break; /* used in vicodec */ -diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h -index 575b59fbac77..b3ce438f1329 100644 ---- a/include/media/v4l2-ctrls.h -+++ b/include/media/v4l2-ctrls.h -@@ -50,6 +50,8 @@ struct video_device; - * @p_h264_decode_params: Pointer to a struct v4l2_ctrl_h264_decode_params. - * @p_h264_pred_weights: Pointer to a struct v4l2_ctrl_h264_pred_weights. - * @p_vp8_frame: Pointer to a VP8 frame params structure. -+ * @p_vp9_compressed_hdr_probs: Pointer to a VP9 frame compressed header probs structure. -+ * @p_vp9_frame: Pointer to a VP9 frame params structure. - * @p_hevc_sps: Pointer to an HEVC sequence parameter set structure. - * @p_hevc_pps: Pointer to an HEVC picture parameter set structure. - * @p_hevc_slice_params: Pointer to an HEVC slice parameters structure. -@@ -80,6 +82,8 @@ union v4l2_ctrl_ptr { - struct v4l2_ctrl_hevc_sps *p_hevc_sps; - struct v4l2_ctrl_hevc_pps *p_hevc_pps; - struct v4l2_ctrl_hevc_slice_params *p_hevc_slice_params; -+ struct v4l2_ctrl_vp9_compressed_hdr *p_vp9_compressed_hdr_probs; -+ struct v4l2_ctrl_vp9_frame *p_vp9_frame; - struct v4l2_ctrl_hdr10_cll_info *p_hdr10_cll; - struct v4l2_ctrl_hdr10_mastering_display *p_hdr10_mastering; - struct v4l2_area *p_area; -diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h -index 5fea5feb0412..f859b73f0490 100644 ---- a/include/uapi/linux/v4l2-controls.h -+++ b/include/uapi/linux/v4l2-controls.h -@@ -2016,6 +2016,290 @@ struct v4l2_ctrl_hdr10_mastering_display { - __u32 min_display_mastering_luminance; - }; - -+/* Stateless VP9 controls */ -+ -+#define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED 0x1 -+#define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE 0x2 -+ -+/** -+ * struct v4l2_vp9_loop_filter - VP9 loop filter parameters -+ * -+ * @ref_deltas: contains the adjustment needed for the filter level based on the -+ * chosen reference frame. If this syntax element is not present in the bitstream, -+ * users should pass its last value. -+ * @mode_deltas: contains the adjustment needed for the filter level based on the -+ * chosen mode. If this syntax element is not present in the bitstream, users should -+ * pass its last value. -+ * @level: indicates the loop filter strength. -+ * @sharpness: indicates the sharpness level. -+ * @flags: combination of V4L2_VP9_LOOP_FILTER_FLAG_{} flags. -+ * @reserved: padding field. Should be zeroed by applications. -+ * -+ * This structure contains all loop filter related parameters. See sections -+ * '7.2.8 Loop filter semantics' of the VP9 specification for more details. -+ */ -+struct v4l2_vp9_loop_filter { -+ __s8 ref_deltas[4]; -+ __s8 mode_deltas[2]; -+ __u8 level; -+ __u8 sharpness; -+ __u8 flags; -+ __u8 reserved[7]; -+}; -+ -+/** -+ * struct v4l2_vp9_quantization - VP9 quantization parameters -+ * -+ * @base_q_idx: indicates the base frame qindex. -+ * @delta_q_y_dc: indicates the Y DC quantizer relative to base_q_idx. -+ * @delta_q_uv_dc: indicates the UV DC quantizer relative to base_q_idx. -+ * @delta_q_uv_ac: indicates the UV AC quantizer relative to base_q_idx. -+ * @reserved: padding field. Should be zeroed by applications. -+ * -+ * Encodes the quantization parameters. See section '7.2.9 Quantization params -+ * syntax' of the VP9 specification for more details. -+ */ -+struct v4l2_vp9_quantization { -+ __u8 base_q_idx; -+ __s8 delta_q_y_dc; -+ __s8 delta_q_uv_dc; -+ __s8 delta_q_uv_ac; -+ __u8 reserved[4]; -+}; -+ -+#define V4L2_VP9_SEGMENTATION_FLAG_ENABLED 0x01 -+#define V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP 0x02 -+#define V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE 0x04 -+#define V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA 0x08 -+#define V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE 0x10 -+ -+#define V4L2_VP9_SEG_LVL_ALT_Q 0 -+#define V4L2_VP9_SEG_LVL_ALT_L 1 -+#define V4L2_VP9_SEG_LVL_REF_FRAME 2 -+#define V4L2_VP9_SEG_LVL_SKIP 3 -+#define V4L2_VP9_SEG_LVL_MAX 4 -+ -+#define V4L2_VP9_SEGMENT_FEATURE_ENABLED(id) (1 << (id)) -+#define V4L2_VP9_SEGMENT_FEATURE_ENABLED_MASK 0xf -+ -+/** -+ * struct v4l2_vp9_segmentation - VP9 segmentation parameters -+ * -+ * @feature_data: data attached to each feature. Data entry is only valid if -+ * the feature is enabled. The array shall be indexed with segment number as -+ * the first dimension (0..7) and one of V4L2_VP9_SEG_{} as the second dimension. -+ * @feature_enabled: bitmask defining which features are enabled in each segment. -+ * The value for each segment is a combination of V4L2_VP9_SEGMENT_FEATURE_ENABLED(id) -+ * values where id is one of V4L2_VP9_SEG_LVL_{}. -+ * @tree_probs: specifies the probability values to be used when decoding a -+ * Segment-ID. See '5.15. Segmentation map' section of the VP9 specification -+ * for more details. -+ * @pred_probs: specifies the probability values to be used when decoding a -+ * Predicted-Segment-ID. See '6.4.14. Get segment id syntax' section of :ref:`vp9` -+ * for more details. -+ * @flags: combination of V4L2_VP9_SEGMENTATION_FLAG_{} flags. -+ * @reserved: padding field. Should be zeroed by applications. -+ * -+ * Encodes the quantization parameters. See section '7.2.10 Segmentation params syntax' of -+ * the VP9 specification for more details. -+ */ -+struct v4l2_vp9_segmentation { -+ __s16 feature_data[8][4]; -+ __u8 feature_enabled[8]; -+ __u8 tree_probs[7]; -+ __u8 pred_probs[3]; -+ __u8 flags; -+ __u8 reserved[5]; -+}; -+ -+#define V4L2_VP9_FRAME_FLAG_KEY_FRAME 0x001 -+#define V4L2_VP9_FRAME_FLAG_SHOW_FRAME 0x002 -+#define V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT 0x004 -+#define V4L2_VP9_FRAME_FLAG_INTRA_ONLY 0x008 -+#define V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV 0x010 -+#define V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX 0x020 -+#define V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE 0x040 -+#define V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING 0x080 -+#define V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING 0x100 -+#define V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING 0x200 -+ -+#define V4L2_VP9_SIGN_BIAS_LAST 0x1 -+#define V4L2_VP9_SIGN_BIAS_GOLDEN 0x2 -+#define V4L2_VP9_SIGN_BIAS_ALT 0x4 -+ -+#define V4L2_VP9_RESET_FRAME_CTX_NONE 0 -+#define V4L2_VP9_RESET_FRAME_CTX_SPEC 1 -+#define V4L2_VP9_RESET_FRAME_CTX_ALL 2 -+ -+#define V4L2_VP9_INTERP_FILTER_EIGHTTAP 0 -+#define V4L2_VP9_INTERP_FILTER_EIGHTTAP_SMOOTH 1 -+#define V4L2_VP9_INTERP_FILTER_EIGHTTAP_SHARP 2 -+#define V4L2_VP9_INTERP_FILTER_BILINEAR 3 -+#define V4L2_VP9_INTERP_FILTER_SWITCHABLE 4 -+ -+#define V4L2_VP9_REFERENCE_MODE_SINGLE_REFERENCE 0 -+#define V4L2_VP9_REFERENCE_MODE_COMPOUND_REFERENCE 1 -+#define V4L2_VP9_REFERENCE_MODE_SELECT 2 -+ -+#define V4L2_VP9_PROFILE_MAX 3 -+ -+#define V4L2_CID_STATELESS_VP9_FRAME (V4L2_CID_CODEC_STATELESS_BASE + 300) -+/** -+ * struct v4l2_ctrl_vp9_frame - VP9 frame decoding control -+ * -+ * @lf: loop filter parameters. See &v4l2_vp9_loop_filter for more details. -+ * @quant: quantization parameters. See &v4l2_vp9_quantization for more details. -+ * @seg: segmentation parameters. See &v4l2_vp9_segmentation for more details. -+ * @flags: combination of V4L2_VP9_FRAME_FLAG_{} flags. -+ * @compressed_header_size: compressed header size in bytes. -+ * @uncompressed_header_size: uncompressed header size in bytes. -+ * @frame_width_minus_1: add 1 to it and you'll get the frame width expressed in pixels. -+ * @frame_height_minus_1: add 1 to it and you'll get the frame height expressed in pixels. -+ * @render_width_minus_1: add 1 to it and you'll get the expected render width expressed in -+ * pixels. This is not used during the decoding process but might be used by HW scalers -+ * to prepare a frame that's ready for scanout. -+ * @render_height_minus_1: add 1 to it and you'll get the expected render height expressed in -+ * pixels. This is not used during the decoding process but might be used by HW scalers -+ * to prepare a frame that's ready for scanout. -+ * @last_frame_ts: "last" reference buffer timestamp. -+ * The timestamp refers to the timestamp field in struct v4l2_buffer. -+ * Use v4l2_timeval_to_ns() to convert the struct timeval to a __u64. -+ * @golden_frame_ts: "golden" reference buffer timestamp. -+ * The timestamp refers to the timestamp field in struct v4l2_buffer. -+ * Use v4l2_timeval_to_ns() to convert the struct timeval to a __u64. -+ * @alt_frame_ts: "alt" reference buffer timestamp. -+ * The timestamp refers to the timestamp field in struct v4l2_buffer. -+ * Use v4l2_timeval_to_ns() to convert the struct timeval to a __u64. -+ * @ref_frame_sign_bias: a bitfield specifying whether the sign bias is set for a given -+ * reference frame. Either of V4L2_VP9_SIGN_BIAS_{}. -+ * @reset_frame_context: specifies whether the frame context should be reset to default values. -+ * Either of V4L2_VP9_RESET_FRAME_CTX_{}. -+ * @frame_context_idx: frame context that should be used/updated. -+ * @profile: VP9 profile. Can be 0, 1, 2 or 3. -+ * @bit_depth: bits per components. Can be 8, 10 or 12. Note that not all profiles support -+ * 10 and/or 12 bits depths. -+ * @interpolation_filter: specifies the filter selection used for performing inter prediction. -+ * Set to one of V4L2_VP9_INTERP_FILTER_{}. -+ * @tile_cols_log2: specifies the base 2 logarithm of the width of each tile (where the width -+ * is measured in units of 8x8 blocks). Shall be less than or equal to 6. -+ * @tile_rows_log2: specifies the base 2 logarithm of the height of each tile (where the height -+ * is measured in units of 8x8 blocks). -+ * @reference_mode: specifies the type of inter prediction to be used. -+ * Set to one of V4L2_VP9_REFERENCE_MODE_{}. -+ * @reserved: padding field. Should be zeroed by applications. -+ */ -+struct v4l2_ctrl_vp9_frame { -+ struct v4l2_vp9_loop_filter lf; -+ struct v4l2_vp9_quantization quant; -+ struct v4l2_vp9_segmentation seg; -+ __u32 flags; -+ __u16 compressed_header_size; -+ __u16 uncompressed_header_size; -+ __u16 frame_width_minus_1; -+ __u16 frame_height_minus_1; -+ __u16 render_width_minus_1; -+ __u16 render_height_minus_1; -+ __u64 last_frame_ts; -+ __u64 golden_frame_ts; -+ __u64 alt_frame_ts; -+ __u8 ref_frame_sign_bias; -+ __u8 reset_frame_context; -+ __u8 frame_context_idx; -+ __u8 profile; -+ __u8 bit_depth; -+ __u8 interpolation_filter; -+ __u8 tile_cols_log2; -+ __u8 tile_rows_log2; -+ __u8 reference_mode; -+ __u8 reserved[7]; -+}; -+ -+#define V4L2_VP9_NUM_FRAME_CTX 4 -+ -+/** -+ * struct v4l2_vp9_mv_probs - VP9 Motion vector probability updates -+ * @joint: motion vector joint probability updates. -+ * @sign: motion vector sign probability updates. -+ * @classes: motion vector class probability updates. -+ * @class0_bit: motion vector class0 bit probability updates. -+ * @bits: motion vector bits probability updates. -+ * @class0_fr: motion vector class0 fractional bit probability updates. -+ * @fr: motion vector fractional bit probability updates. -+ * @class0_hp: motion vector class0 high precision fractional bit probability updates. -+ * @hp: motion vector high precision fractional bit probability updates. -+ * -+ * This structure contains new values of motion vector probabilities. -+ * A value of zero in an array element means there is no update of the relevant probability. -+ * See `struct v4l2_vp9_prob_updates` for details. -+ */ -+struct v4l2_vp9_mv_probs { -+ __u8 joint[3]; -+ __u8 sign[2]; -+ __u8 classes[2][10]; -+ __u8 class0_bit[2]; -+ __u8 bits[2][10]; -+ __u8 class0_fr[2][2][3]; -+ __u8 fr[2][3]; -+ __u8 class0_hp[2]; -+ __u8 hp[2]; -+}; -+ -+#define V4L2_CID_STATELESS_VP9_COMPRESSED_HDR (V4L2_CID_CODEC_STATELESS_BASE + 301) -+ -+#define V4L2_VP9_TX_MODE_ONLY_4X4 0 -+#define V4L2_VP9_TX_MODE_ALLOW_8X8 1 -+#define V4L2_VP9_TX_MODE_ALLOW_16X16 2 -+#define V4L2_VP9_TX_MODE_ALLOW_32X32 3 -+#define V4L2_VP9_TX_MODE_SELECT 4 -+ -+/** -+ * struct v4l2_ctrl_vp9_compressed_hdr - VP9 probability updates control -+ * @tx_mode: specifies the TX mode. Set to one of V4L2_VP9_TX_MODE_{}. -+ * @tx8: TX 8x8 probability updates. -+ * @tx16: TX 16x16 probability updates. -+ * @tx32: TX 32x32 probability updates. -+ * @coef: coefficient probability updates. -+ * @skip: skip probability updates. -+ * @inter_mode: inter mode probability updates. -+ * @interp_filter: interpolation filter probability updates. -+ * @is_inter: is inter-block probability updates. -+ * @comp_mode: compound prediction mode probability updates. -+ * @single_ref: single ref probability updates. -+ * @comp_ref: compound ref probability updates. -+ * @y_mode: Y prediction mode probability updates. -+ * @uv_mode: UV prediction mode probability updates. -+ * @partition: partition probability updates. -+ * @mv: motion vector probability updates. -+ * -+ * This structure holds the probabilities update as parsed in the compressed -+ * header (Spec 6.3). These values represent the value of probability update after -+ * being translated with inv_map_table[] (see 6.3.5). A value of zero in an array element -+ * means that there is no update of the relevant probability. -+ * -+ * This control is optional and needs to be used when dealing with the hardware which is -+ * not capable of parsing the compressed header itself. Only drivers which need it will -+ * implement it. -+ */ -+struct v4l2_ctrl_vp9_compressed_hdr { -+ __u8 tx_mode; -+ __u8 tx8[2][1]; -+ __u8 tx16[2][2]; -+ __u8 tx32[2][3]; -+ __u8 coef[4][2][2][6][6][3]; -+ __u8 skip[3]; -+ __u8 inter_mode[7][3]; -+ __u8 interp_filter[4][2]; -+ __u8 is_inter[4]; -+ __u8 comp_mode[5]; -+ __u8 single_ref[5][2]; -+ __u8 comp_ref[5]; -+ __u8 y_mode[4][9]; -+ __u8 uv_mode[10][9]; -+ __u8 partition[16][3]; -+ -+ struct v4l2_vp9_mv_probs mv; -+}; -+ - /* MPEG-compression definitions kept for backwards compatibility */ - #ifndef __KERNEL__ - #define V4L2_CTRL_CLASS_MPEG V4L2_CTRL_CLASS_CODEC -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index f118fe7a9f58..df8b9c486ba1 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -703,6 +703,7 @@ struct v4l2_pix_format { - #define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') /* VP8 */ - #define V4L2_PIX_FMT_VP8_FRAME v4l2_fourcc('V', 'P', '8', 'F') /* VP8 parsed frame */ - #define V4L2_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0') /* VP9 */ -+#define V4L2_PIX_FMT_VP9_FRAME v4l2_fourcc('V', 'P', '9', 'F') /* VP9 parsed frame */ - #define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* HEVC aka H.265 */ - #define V4L2_PIX_FMT_FWHT v4l2_fourcc('F', 'W', 'H', 'T') /* Fast Walsh Hadamard Transform (vicodec) */ - #define V4L2_PIX_FMT_FWHT_STATELESS v4l2_fourcc('S', 'F', 'W', 'H') /* Stateless FWHT (vicodec) */ -@@ -1759,6 +1760,8 @@ struct v4l2_ext_control { - struct v4l2_ctrl_mpeg2_sequence __user *p_mpeg2_sequence; - struct v4l2_ctrl_mpeg2_picture __user *p_mpeg2_picture; - struct v4l2_ctrl_mpeg2_quantisation __user *p_mpeg2_quantisation; -+ struct v4l2_ctrl_vp9_compressed_hdr __user *p_vp9_compressed_hdr_probs; -+ struct v4l2_ctrl_vp9_frame __user *p_vp9_frame; - void __user *ptr; - }; - } __attribute__ ((packed)); -@@ -1823,6 +1826,9 @@ enum v4l2_ctrl_type { - V4L2_CTRL_TYPE_MPEG2_QUANTISATION = 0x0250, - V4L2_CTRL_TYPE_MPEG2_SEQUENCE = 0x0251, - V4L2_CTRL_TYPE_MPEG2_PICTURE = 0x0252, -+ -+ V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR = 0x0260, -+ V4L2_CTRL_TYPE_VP9_FRAME = 0x0261, - }; - - /* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */ diff --git a/projects/Allwinner/patches/linux/0072-media-Add-VP9-v4l2-library.patch b/projects/Allwinner/patches/linux/0072-media-Add-VP9-v4l2-library.patch deleted file mode 100644 index 62f9c5091c..0000000000 --- a/projects/Allwinner/patches/linux/0072-media-Add-VP9-v4l2-library.patch +++ /dev/null @@ -1,2141 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:36 +0100 -Subject: [PATCH] media: Add VP9 v4l2 library - -Provide code common to vp9 drivers in one central location. - -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil ---- - drivers/media/v4l2-core/Kconfig | 4 + - drivers/media/v4l2-core/Makefile | 1 + - drivers/media/v4l2-core/v4l2-vp9.c | 1850 ++++++++++++++++++++++++++++ - include/media/v4l2-vp9.h | 233 ++++ - 4 files changed, 2088 insertions(+) - create mode 100644 drivers/media/v4l2-core/v4l2-vp9.c - create mode 100644 include/media/v4l2-vp9.h - -diff --git a/drivers/media/v4l2-core/Kconfig b/drivers/media/v4l2-core/Kconfig -index 02dc1787e953..6ee75c6c820e 100644 ---- a/drivers/media/v4l2-core/Kconfig -+++ b/drivers/media/v4l2-core/Kconfig -@@ -52,6 +52,10 @@ config V4L2_JPEG_HELPER - config V4L2_H264 - tristate - -+# Used by drivers that need v4l2-vp9.ko -+config V4L2_VP9 -+ tristate -+ - # Used by drivers that need v4l2-mem2mem.ko - config V4L2_MEM2MEM_DEV - tristate -diff --git a/drivers/media/v4l2-core/Makefile b/drivers/media/v4l2-core/Makefile -index 66a78c556c98..83fac5c746f5 100644 ---- a/drivers/media/v4l2-core/Makefile -+++ b/drivers/media/v4l2-core/Makefile -@@ -24,6 +24,7 @@ obj-$(CONFIG_VIDEO_TUNER) += tuner.o - - obj-$(CONFIG_V4L2_MEM2MEM_DEV) += v4l2-mem2mem.o - obj-$(CONFIG_V4L2_H264) += v4l2-h264.o -+obj-$(CONFIG_V4L2_VP9) += v4l2-vp9.o - - obj-$(CONFIG_V4L2_FLASH_LED_CLASS) += v4l2-flash-led-class.o - -diff --git a/drivers/media/v4l2-core/v4l2-vp9.c b/drivers/media/v4l2-core/v4l2-vp9.c -new file mode 100644 -index 000000000000..859589f1fd35 ---- /dev/null -+++ b/drivers/media/v4l2-core/v4l2-vp9.c -@@ -0,0 +1,1850 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * V4L2 VP9 helpers. -+ * -+ * Copyright (C) 2021 Collabora, Ltd. -+ * -+ * Author: Andrzej Pietrasiewicz -+ */ -+ -+#include -+ -+#include -+ -+const u8 v4l2_vp9_kf_y_mode_prob[10][10][9] = { -+ { -+ /* above = dc */ -+ { 137, 30, 42, 148, 151, 207, 70, 52, 91 }, /*left = dc */ -+ { 92, 45, 102, 136, 116, 180, 74, 90, 100 }, /*left = v */ -+ { 73, 32, 19, 187, 222, 215, 46, 34, 100 }, /*left = h */ -+ { 91, 30, 32, 116, 121, 186, 93, 86, 94 }, /*left = d45 */ -+ { 72, 35, 36, 149, 68, 206, 68, 63, 105 }, /*left = d135*/ -+ { 73, 31, 28, 138, 57, 124, 55, 122, 151 }, /*left = d117*/ -+ { 67, 23, 21, 140, 126, 197, 40, 37, 171 }, /*left = d153*/ -+ { 86, 27, 28, 128, 154, 212, 45, 43, 53 }, /*left = d207*/ -+ { 74, 32, 27, 107, 86, 160, 63, 134, 102 }, /*left = d63 */ -+ { 59, 67, 44, 140, 161, 202, 78, 67, 119 }, /*left = tm */ -+ }, { /* above = v */ -+ { 63, 36, 126, 146, 123, 158, 60, 90, 96 }, /*left = dc */ -+ { 43, 46, 168, 134, 107, 128, 69, 142, 92 }, /*left = v */ -+ { 44, 29, 68, 159, 201, 177, 50, 57, 77 }, /*left = h */ -+ { 58, 38, 76, 114, 97, 172, 78, 133, 92 }, /*left = d45 */ -+ { 46, 41, 76, 140, 63, 184, 69, 112, 57 }, /*left = d135*/ -+ { 38, 32, 85, 140, 46, 112, 54, 151, 133 }, /*left = d117*/ -+ { 39, 27, 61, 131, 110, 175, 44, 75, 136 }, /*left = d153*/ -+ { 52, 30, 74, 113, 130, 175, 51, 64, 58 }, /*left = d207*/ -+ { 47, 35, 80, 100, 74, 143, 64, 163, 74 }, /*left = d63 */ -+ { 36, 61, 116, 114, 128, 162, 80, 125, 82 }, /*left = tm */ -+ }, { /* above = h */ -+ { 82, 26, 26, 171, 208, 204, 44, 32, 105 }, /*left = dc */ -+ { 55, 44, 68, 166, 179, 192, 57, 57, 108 }, /*left = v */ -+ { 42, 26, 11, 199, 241, 228, 23, 15, 85 }, /*left = h */ -+ { 68, 42, 19, 131, 160, 199, 55, 52, 83 }, /*left = d45 */ -+ { 58, 50, 25, 139, 115, 232, 39, 52, 118 }, /*left = d135*/ -+ { 50, 35, 33, 153, 104, 162, 64, 59, 131 }, /*left = d117*/ -+ { 44, 24, 16, 150, 177, 202, 33, 19, 156 }, /*left = d153*/ -+ { 55, 27, 12, 153, 203, 218, 26, 27, 49 }, /*left = d207*/ -+ { 53, 49, 21, 110, 116, 168, 59, 80, 76 }, /*left = d63 */ -+ { 38, 72, 19, 168, 203, 212, 50, 50, 107 }, /*left = tm */ -+ }, { /* above = d45 */ -+ { 103, 26, 36, 129, 132, 201, 83, 80, 93 }, /*left = dc */ -+ { 59, 38, 83, 112, 103, 162, 98, 136, 90 }, /*left = v */ -+ { 62, 30, 23, 158, 200, 207, 59, 57, 50 }, /*left = h */ -+ { 67, 30, 29, 84, 86, 191, 102, 91, 59 }, /*left = d45 */ -+ { 60, 32, 33, 112, 71, 220, 64, 89, 104 }, /*left = d135*/ -+ { 53, 26, 34, 130, 56, 149, 84, 120, 103 }, /*left = d117*/ -+ { 53, 21, 23, 133, 109, 210, 56, 77, 172 }, /*left = d153*/ -+ { 77, 19, 29, 112, 142, 228, 55, 66, 36 }, /*left = d207*/ -+ { 61, 29, 29, 93, 97, 165, 83, 175, 162 }, /*left = d63 */ -+ { 47, 47, 43, 114, 137, 181, 100, 99, 95 }, /*left = tm */ -+ }, { /* above = d135 */ -+ { 69, 23, 29, 128, 83, 199, 46, 44, 101 }, /*left = dc */ -+ { 53, 40, 55, 139, 69, 183, 61, 80, 110 }, /*left = v */ -+ { 40, 29, 19, 161, 180, 207, 43, 24, 91 }, /*left = h */ -+ { 60, 34, 19, 105, 61, 198, 53, 64, 89 }, /*left = d45 */ -+ { 52, 31, 22, 158, 40, 209, 58, 62, 89 }, /*left = d135*/ -+ { 44, 31, 29, 147, 46, 158, 56, 102, 198 }, /*left = d117*/ -+ { 35, 19, 12, 135, 87, 209, 41, 45, 167 }, /*left = d153*/ -+ { 55, 25, 21, 118, 95, 215, 38, 39, 66 }, /*left = d207*/ -+ { 51, 38, 25, 113, 58, 164, 70, 93, 97 }, /*left = d63 */ -+ { 47, 54, 34, 146, 108, 203, 72, 103, 151 }, /*left = tm */ -+ }, { /* above = d117 */ -+ { 64, 19, 37, 156, 66, 138, 49, 95, 133 }, /*left = dc */ -+ { 46, 27, 80, 150, 55, 124, 55, 121, 135 }, /*left = v */ -+ { 36, 23, 27, 165, 149, 166, 54, 64, 118 }, /*left = h */ -+ { 53, 21, 36, 131, 63, 163, 60, 109, 81 }, /*left = d45 */ -+ { 40, 26, 35, 154, 40, 185, 51, 97, 123 }, /*left = d135*/ -+ { 35, 19, 34, 179, 19, 97, 48, 129, 124 }, /*left = d117*/ -+ { 36, 20, 26, 136, 62, 164, 33, 77, 154 }, /*left = d153*/ -+ { 45, 18, 32, 130, 90, 157, 40, 79, 91 }, /*left = d207*/ -+ { 45, 26, 28, 129, 45, 129, 49, 147, 123 }, /*left = d63 */ -+ { 38, 44, 51, 136, 74, 162, 57, 97, 121 }, /*left = tm */ -+ }, { /* above = d153 */ -+ { 75, 17, 22, 136, 138, 185, 32, 34, 166 }, /*left = dc */ -+ { 56, 39, 58, 133, 117, 173, 48, 53, 187 }, /*left = v */ -+ { 35, 21, 12, 161, 212, 207, 20, 23, 145 }, /*left = h */ -+ { 56, 29, 19, 117, 109, 181, 55, 68, 112 }, /*left = d45 */ -+ { 47, 29, 17, 153, 64, 220, 59, 51, 114 }, /*left = d135*/ -+ { 46, 16, 24, 136, 76, 147, 41, 64, 172 }, /*left = d117*/ -+ { 34, 17, 11, 108, 152, 187, 13, 15, 209 }, /*left = d153*/ -+ { 51, 24, 14, 115, 133, 209, 32, 26, 104 }, /*left = d207*/ -+ { 55, 30, 18, 122, 79, 179, 44, 88, 116 }, /*left = d63 */ -+ { 37, 49, 25, 129, 168, 164, 41, 54, 148 }, /*left = tm */ -+ }, { /* above = d207 */ -+ { 82, 22, 32, 127, 143, 213, 39, 41, 70 }, /*left = dc */ -+ { 62, 44, 61, 123, 105, 189, 48, 57, 64 }, /*left = v */ -+ { 47, 25, 17, 175, 222, 220, 24, 30, 86 }, /*left = h */ -+ { 68, 36, 17, 106, 102, 206, 59, 74, 74 }, /*left = d45 */ -+ { 57, 39, 23, 151, 68, 216, 55, 63, 58 }, /*left = d135*/ -+ { 49, 30, 35, 141, 70, 168, 82, 40, 115 }, /*left = d117*/ -+ { 51, 25, 15, 136, 129, 202, 38, 35, 139 }, /*left = d153*/ -+ { 68, 26, 16, 111, 141, 215, 29, 28, 28 }, /*left = d207*/ -+ { 59, 39, 19, 114, 75, 180, 77, 104, 42 }, /*left = d63 */ -+ { 40, 61, 26, 126, 152, 206, 61, 59, 93 }, /*left = tm */ -+ }, { /* above = d63 */ -+ { 78, 23, 39, 111, 117, 170, 74, 124, 94 }, /*left = dc */ -+ { 48, 34, 86, 101, 92, 146, 78, 179, 134 }, /*left = v */ -+ { 47, 22, 24, 138, 187, 178, 68, 69, 59 }, /*left = h */ -+ { 56, 25, 33, 105, 112, 187, 95, 177, 129 }, /*left = d45 */ -+ { 48, 31, 27, 114, 63, 183, 82, 116, 56 }, /*left = d135*/ -+ { 43, 28, 37, 121, 63, 123, 61, 192, 169 }, /*left = d117*/ -+ { 42, 17, 24, 109, 97, 177, 56, 76, 122 }, /*left = d153*/ -+ { 58, 18, 28, 105, 139, 182, 70, 92, 63 }, /*left = d207*/ -+ { 46, 23, 32, 74, 86, 150, 67, 183, 88 }, /*left = d63 */ -+ { 36, 38, 48, 92, 122, 165, 88, 137, 91 }, /*left = tm */ -+ }, { /* above = tm */ -+ { 65, 70, 60, 155, 159, 199, 61, 60, 81 }, /*left = dc */ -+ { 44, 78, 115, 132, 119, 173, 71, 112, 93 }, /*left = v */ -+ { 39, 38, 21, 184, 227, 206, 42, 32, 64 }, /*left = h */ -+ { 58, 47, 36, 124, 137, 193, 80, 82, 78 }, /*left = d45 */ -+ { 49, 50, 35, 144, 95, 205, 63, 78, 59 }, /*left = d135*/ -+ { 41, 53, 52, 148, 71, 142, 65, 128, 51 }, /*left = d117*/ -+ { 40, 36, 28, 143, 143, 202, 40, 55, 137 }, /*left = d153*/ -+ { 52, 34, 29, 129, 183, 227, 42, 35, 43 }, /*left = d207*/ -+ { 42, 44, 44, 104, 105, 164, 64, 130, 80 }, /*left = d63 */ -+ { 43, 81, 53, 140, 169, 204, 68, 84, 72 }, /*left = tm */ -+ } -+}; -+EXPORT_SYMBOL_GPL(v4l2_vp9_kf_y_mode_prob); -+ -+const u8 v4l2_vp9_kf_partition_probs[16][3] = { -+ /* 8x8 -> 4x4 */ -+ { 158, 97, 94 }, /* a/l both not split */ -+ { 93, 24, 99 }, /* a split, l not split */ -+ { 85, 119, 44 }, /* l split, a not split */ -+ { 62, 59, 67 }, /* a/l both split */ -+ /* 16x16 -> 8x8 */ -+ { 149, 53, 53 }, /* a/l both not split */ -+ { 94, 20, 48 }, /* a split, l not split */ -+ { 83, 53, 24 }, /* l split, a not split */ -+ { 52, 18, 18 }, /* a/l both split */ -+ /* 32x32 -> 16x16 */ -+ { 150, 40, 39 }, /* a/l both not split */ -+ { 78, 12, 26 }, /* a split, l not split */ -+ { 67, 33, 11 }, /* l split, a not split */ -+ { 24, 7, 5 }, /* a/l both split */ -+ /* 64x64 -> 32x32 */ -+ { 174, 35, 49 }, /* a/l both not split */ -+ { 68, 11, 27 }, /* a split, l not split */ -+ { 57, 15, 9 }, /* l split, a not split */ -+ { 12, 3, 3 }, /* a/l both split */ -+}; -+EXPORT_SYMBOL_GPL(v4l2_vp9_kf_partition_probs); -+ -+const u8 v4l2_vp9_kf_uv_mode_prob[10][9] = { -+ { 144, 11, 54, 157, 195, 130, 46, 58, 108 }, /* y = dc */ -+ { 118, 15, 123, 148, 131, 101, 44, 93, 131 }, /* y = v */ -+ { 113, 12, 23, 188, 226, 142, 26, 32, 125 }, /* y = h */ -+ { 120, 11, 50, 123, 163, 135, 64, 77, 103 }, /* y = d45 */ -+ { 113, 9, 36, 155, 111, 157, 32, 44, 161 }, /* y = d135 */ -+ { 116, 9, 55, 176, 76, 96, 37, 61, 149 }, /* y = d117 */ -+ { 115, 9, 28, 141, 161, 167, 21, 25, 193 }, /* y = d153 */ -+ { 120, 12, 32, 145, 195, 142, 32, 38, 86 }, /* y = d207 */ -+ { 116, 12, 64, 120, 140, 125, 49, 115, 121 }, /* y = d63 */ -+ { 102, 19, 66, 162, 182, 122, 35, 59, 128 } /* y = tm */ -+}; -+EXPORT_SYMBOL_GPL(v4l2_vp9_kf_uv_mode_prob); -+ -+const struct v4l2_vp9_frame_context v4l2_vp9_default_probs = { -+ .tx8 = { -+ { 100 }, -+ { 66 }, -+ }, -+ .tx16 = { -+ { 20, 152 }, -+ { 15, 101 }, -+ }, -+ .tx32 = { -+ { 3, 136, 37 }, -+ { 5, 52, 13 }, -+ }, -+ .coef = { -+ { /* tx = 4x4 */ -+ { /* block Type 0 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 195, 29, 183 }, -+ { 84, 49, 136 }, -+ { 8, 42, 71 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 31, 107, 169 }, -+ { 35, 99, 159 }, -+ { 17, 82, 140 }, -+ { 8, 66, 114 }, -+ { 2, 44, 76 }, -+ { 1, 19, 32 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 40, 132, 201 }, -+ { 29, 114, 187 }, -+ { 13, 91, 157 }, -+ { 7, 75, 127 }, -+ { 3, 58, 95 }, -+ { 1, 28, 47 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 69, 142, 221 }, -+ { 42, 122, 201 }, -+ { 15, 91, 159 }, -+ { 6, 67, 121 }, -+ { 1, 42, 77 }, -+ { 1, 17, 31 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 102, 148, 228 }, -+ { 67, 117, 204 }, -+ { 17, 82, 154 }, -+ { 6, 59, 114 }, -+ { 2, 39, 75 }, -+ { 1, 15, 29 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 156, 57, 233 }, -+ { 119, 57, 212 }, -+ { 58, 48, 163 }, -+ { 29, 40, 124 }, -+ { 12, 30, 81 }, -+ { 3, 12, 31 } -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 191, 107, 226 }, -+ { 124, 117, 204 }, -+ { 25, 99, 155 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 29, 148, 210 }, -+ { 37, 126, 194 }, -+ { 8, 93, 157 }, -+ { 2, 68, 118 }, -+ { 1, 39, 69 }, -+ { 1, 17, 33 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 41, 151, 213 }, -+ { 27, 123, 193 }, -+ { 3, 82, 144 }, -+ { 1, 58, 105 }, -+ { 1, 32, 60 }, -+ { 1, 13, 26 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 59, 159, 220 }, -+ { 23, 126, 198 }, -+ { 4, 88, 151 }, -+ { 1, 66, 114 }, -+ { 1, 38, 71 }, -+ { 1, 18, 34 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 114, 136, 232 }, -+ { 51, 114, 207 }, -+ { 11, 83, 155 }, -+ { 3, 56, 105 }, -+ { 1, 33, 65 }, -+ { 1, 17, 34 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 149, 65, 234 }, -+ { 121, 57, 215 }, -+ { 61, 49, 166 }, -+ { 28, 36, 114 }, -+ { 12, 25, 76 }, -+ { 3, 16, 42 }, -+ }, -+ }, -+ }, -+ { /* block Type 1 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 214, 49, 220 }, -+ { 132, 63, 188 }, -+ { 42, 65, 137 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 85, 137, 221 }, -+ { 104, 131, 216 }, -+ { 49, 111, 192 }, -+ { 21, 87, 155 }, -+ { 2, 49, 87 }, -+ { 1, 16, 28 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 89, 163, 230 }, -+ { 90, 137, 220 }, -+ { 29, 100, 183 }, -+ { 10, 70, 135 }, -+ { 2, 42, 81 }, -+ { 1, 17, 33 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 108, 167, 237 }, -+ { 55, 133, 222 }, -+ { 15, 97, 179 }, -+ { 4, 72, 135 }, -+ { 1, 45, 85 }, -+ { 1, 19, 38 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 124, 146, 240 }, -+ { 66, 124, 224 }, -+ { 17, 88, 175 }, -+ { 4, 58, 122 }, -+ { 1, 36, 75 }, -+ { 1, 18, 37 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 141, 79, 241 }, -+ { 126, 70, 227 }, -+ { 66, 58, 182 }, -+ { 30, 44, 136 }, -+ { 12, 34, 96 }, -+ { 2, 20, 47 }, -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 229, 99, 249 }, -+ { 143, 111, 235 }, -+ { 46, 109, 192 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 82, 158, 236 }, -+ { 94, 146, 224 }, -+ { 25, 117, 191 }, -+ { 9, 87, 149 }, -+ { 3, 56, 99 }, -+ { 1, 33, 57 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 83, 167, 237 }, -+ { 68, 145, 222 }, -+ { 10, 103, 177 }, -+ { 2, 72, 131 }, -+ { 1, 41, 79 }, -+ { 1, 20, 39 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 99, 167, 239 }, -+ { 47, 141, 224 }, -+ { 10, 104, 178 }, -+ { 2, 73, 133 }, -+ { 1, 44, 85 }, -+ { 1, 22, 47 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 127, 145, 243 }, -+ { 71, 129, 228 }, -+ { 17, 93, 177 }, -+ { 3, 61, 124 }, -+ { 1, 41, 84 }, -+ { 1, 21, 52 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 157, 78, 244 }, -+ { 140, 72, 231 }, -+ { 69, 58, 184 }, -+ { 31, 44, 137 }, -+ { 14, 38, 105 }, -+ { 8, 23, 61 }, -+ }, -+ }, -+ }, -+ }, -+ { /* tx = 8x8 */ -+ { /* block Type 0 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 125, 34, 187 }, -+ { 52, 41, 133 }, -+ { 6, 31, 56 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 37, 109, 153 }, -+ { 51, 102, 147 }, -+ { 23, 87, 128 }, -+ { 8, 67, 101 }, -+ { 1, 41, 63 }, -+ { 1, 19, 29 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 31, 154, 185 }, -+ { 17, 127, 175 }, -+ { 6, 96, 145 }, -+ { 2, 73, 114 }, -+ { 1, 51, 82 }, -+ { 1, 28, 45 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 23, 163, 200 }, -+ { 10, 131, 185 }, -+ { 2, 93, 148 }, -+ { 1, 67, 111 }, -+ { 1, 41, 69 }, -+ { 1, 14, 24 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 29, 176, 217 }, -+ { 12, 145, 201 }, -+ { 3, 101, 156 }, -+ { 1, 69, 111 }, -+ { 1, 39, 63 }, -+ { 1, 14, 23 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 57, 192, 233 }, -+ { 25, 154, 215 }, -+ { 6, 109, 167 }, -+ { 3, 78, 118 }, -+ { 1, 48, 69 }, -+ { 1, 21, 29 }, -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 202, 105, 245 }, -+ { 108, 106, 216 }, -+ { 18, 90, 144 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 33, 172, 219 }, -+ { 64, 149, 206 }, -+ { 14, 117, 177 }, -+ { 5, 90, 141 }, -+ { 2, 61, 95 }, -+ { 1, 37, 57 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 33, 179, 220 }, -+ { 11, 140, 198 }, -+ { 1, 89, 148 }, -+ { 1, 60, 104 }, -+ { 1, 33, 57 }, -+ { 1, 12, 21 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 30, 181, 221 }, -+ { 8, 141, 198 }, -+ { 1, 87, 145 }, -+ { 1, 58, 100 }, -+ { 1, 31, 55 }, -+ { 1, 12, 20 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 32, 186, 224 }, -+ { 7, 142, 198 }, -+ { 1, 86, 143 }, -+ { 1, 58, 100 }, -+ { 1, 31, 55 }, -+ { 1, 12, 22 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 57, 192, 227 }, -+ { 20, 143, 204 }, -+ { 3, 96, 154 }, -+ { 1, 68, 112 }, -+ { 1, 42, 69 }, -+ { 1, 19, 32 }, -+ }, -+ }, -+ }, -+ { /* block Type 1 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 212, 35, 215 }, -+ { 113, 47, 169 }, -+ { 29, 48, 105 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 74, 129, 203 }, -+ { 106, 120, 203 }, -+ { 49, 107, 178 }, -+ { 19, 84, 144 }, -+ { 4, 50, 84 }, -+ { 1, 15, 25 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 71, 172, 217 }, -+ { 44, 141, 209 }, -+ { 15, 102, 173 }, -+ { 6, 76, 133 }, -+ { 2, 51, 89 }, -+ { 1, 24, 42 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 64, 185, 231 }, -+ { 31, 148, 216 }, -+ { 8, 103, 175 }, -+ { 3, 74, 131 }, -+ { 1, 46, 81 }, -+ { 1, 18, 30 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 65, 196, 235 }, -+ { 25, 157, 221 }, -+ { 5, 105, 174 }, -+ { 1, 67, 120 }, -+ { 1, 38, 69 }, -+ { 1, 15, 30 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 65, 204, 238 }, -+ { 30, 156, 224 }, -+ { 7, 107, 177 }, -+ { 2, 70, 124 }, -+ { 1, 42, 73 }, -+ { 1, 18, 34 }, -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 225, 86, 251 }, -+ { 144, 104, 235 }, -+ { 42, 99, 181 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 85, 175, 239 }, -+ { 112, 165, 229 }, -+ { 29, 136, 200 }, -+ { 12, 103, 162 }, -+ { 6, 77, 123 }, -+ { 2, 53, 84 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 75, 183, 239 }, -+ { 30, 155, 221 }, -+ { 3, 106, 171 }, -+ { 1, 74, 128 }, -+ { 1, 44, 76 }, -+ { 1, 17, 28 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 73, 185, 240 }, -+ { 27, 159, 222 }, -+ { 2, 107, 172 }, -+ { 1, 75, 127 }, -+ { 1, 42, 73 }, -+ { 1, 17, 29 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 62, 190, 238 }, -+ { 21, 159, 222 }, -+ { 2, 107, 172 }, -+ { 1, 72, 122 }, -+ { 1, 40, 71 }, -+ { 1, 18, 32 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 61, 199, 240 }, -+ { 27, 161, 226 }, -+ { 4, 113, 180 }, -+ { 1, 76, 129 }, -+ { 1, 46, 80 }, -+ { 1, 23, 41 }, -+ }, -+ }, -+ }, -+ }, -+ { /* tx = 16x16 */ -+ { /* block Type 0 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 7, 27, 153 }, -+ { 5, 30, 95 }, -+ { 1, 16, 30 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 50, 75, 127 }, -+ { 57, 75, 124 }, -+ { 27, 67, 108 }, -+ { 10, 54, 86 }, -+ { 1, 33, 52 }, -+ { 1, 12, 18 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 43, 125, 151 }, -+ { 26, 108, 148 }, -+ { 7, 83, 122 }, -+ { 2, 59, 89 }, -+ { 1, 38, 60 }, -+ { 1, 17, 27 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 23, 144, 163 }, -+ { 13, 112, 154 }, -+ { 2, 75, 117 }, -+ { 1, 50, 81 }, -+ { 1, 31, 51 }, -+ { 1, 14, 23 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 18, 162, 185 }, -+ { 6, 123, 171 }, -+ { 1, 78, 125 }, -+ { 1, 51, 86 }, -+ { 1, 31, 54 }, -+ { 1, 14, 23 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 15, 199, 227 }, -+ { 3, 150, 204 }, -+ { 1, 91, 146 }, -+ { 1, 55, 95 }, -+ { 1, 30, 53 }, -+ { 1, 11, 20 }, -+ } -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 19, 55, 240 }, -+ { 19, 59, 196 }, -+ { 3, 52, 105 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 41, 166, 207 }, -+ { 104, 153, 199 }, -+ { 31, 123, 181 }, -+ { 14, 101, 152 }, -+ { 5, 72, 106 }, -+ { 1, 36, 52 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 35, 176, 211 }, -+ { 12, 131, 190 }, -+ { 2, 88, 144 }, -+ { 1, 60, 101 }, -+ { 1, 36, 60 }, -+ { 1, 16, 28 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 28, 183, 213 }, -+ { 8, 134, 191 }, -+ { 1, 86, 142 }, -+ { 1, 56, 96 }, -+ { 1, 30, 53 }, -+ { 1, 12, 20 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 20, 190, 215 }, -+ { 4, 135, 192 }, -+ { 1, 84, 139 }, -+ { 1, 53, 91 }, -+ { 1, 28, 49 }, -+ { 1, 11, 20 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 13, 196, 216 }, -+ { 2, 137, 192 }, -+ { 1, 86, 143 }, -+ { 1, 57, 99 }, -+ { 1, 32, 56 }, -+ { 1, 13, 24 }, -+ }, -+ }, -+ }, -+ { /* block Type 1 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 211, 29, 217 }, -+ { 96, 47, 156 }, -+ { 22, 43, 87 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 78, 120, 193 }, -+ { 111, 116, 186 }, -+ { 46, 102, 164 }, -+ { 15, 80, 128 }, -+ { 2, 49, 76 }, -+ { 1, 18, 28 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 71, 161, 203 }, -+ { 42, 132, 192 }, -+ { 10, 98, 150 }, -+ { 3, 69, 109 }, -+ { 1, 44, 70 }, -+ { 1, 18, 29 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 57, 186, 211 }, -+ { 30, 140, 196 }, -+ { 4, 93, 146 }, -+ { 1, 62, 102 }, -+ { 1, 38, 65 }, -+ { 1, 16, 27 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 47, 199, 217 }, -+ { 14, 145, 196 }, -+ { 1, 88, 142 }, -+ { 1, 57, 98 }, -+ { 1, 36, 62 }, -+ { 1, 15, 26 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 26, 219, 229 }, -+ { 5, 155, 207 }, -+ { 1, 94, 151 }, -+ { 1, 60, 104 }, -+ { 1, 36, 62 }, -+ { 1, 16, 28 }, -+ } -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 233, 29, 248 }, -+ { 146, 47, 220 }, -+ { 43, 52, 140 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 100, 163, 232 }, -+ { 179, 161, 222 }, -+ { 63, 142, 204 }, -+ { 37, 113, 174 }, -+ { 26, 89, 137 }, -+ { 18, 68, 97 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 85, 181, 230 }, -+ { 32, 146, 209 }, -+ { 7, 100, 164 }, -+ { 3, 71, 121 }, -+ { 1, 45, 77 }, -+ { 1, 18, 30 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 65, 187, 230 }, -+ { 20, 148, 207 }, -+ { 2, 97, 159 }, -+ { 1, 68, 116 }, -+ { 1, 40, 70 }, -+ { 1, 14, 29 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 40, 194, 227 }, -+ { 8, 147, 204 }, -+ { 1, 94, 155 }, -+ { 1, 65, 112 }, -+ { 1, 39, 66 }, -+ { 1, 14, 26 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 16, 208, 228 }, -+ { 3, 151, 207 }, -+ { 1, 98, 160 }, -+ { 1, 67, 117 }, -+ { 1, 41, 74 }, -+ { 1, 17, 31 }, -+ }, -+ }, -+ }, -+ }, -+ { /* tx = 32x32 */ -+ { /* block Type 0 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 17, 38, 140 }, -+ { 7, 34, 80 }, -+ { 1, 17, 29 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 37, 75, 128 }, -+ { 41, 76, 128 }, -+ { 26, 66, 116 }, -+ { 12, 52, 94 }, -+ { 2, 32, 55 }, -+ { 1, 10, 16 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 50, 127, 154 }, -+ { 37, 109, 152 }, -+ { 16, 82, 121 }, -+ { 5, 59, 85 }, -+ { 1, 35, 54 }, -+ { 1, 13, 20 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 40, 142, 167 }, -+ { 17, 110, 157 }, -+ { 2, 71, 112 }, -+ { 1, 44, 72 }, -+ { 1, 27, 45 }, -+ { 1, 11, 17 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 30, 175, 188 }, -+ { 9, 124, 169 }, -+ { 1, 74, 116 }, -+ { 1, 48, 78 }, -+ { 1, 30, 49 }, -+ { 1, 11, 18 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 10, 222, 223 }, -+ { 2, 150, 194 }, -+ { 1, 83, 128 }, -+ { 1, 48, 79 }, -+ { 1, 27, 45 }, -+ { 1, 11, 17 }, -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 36, 41, 235 }, -+ { 29, 36, 193 }, -+ { 10, 27, 111 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 85, 165, 222 }, -+ { 177, 162, 215 }, -+ { 110, 135, 195 }, -+ { 57, 113, 168 }, -+ { 23, 83, 120 }, -+ { 10, 49, 61 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 85, 190, 223 }, -+ { 36, 139, 200 }, -+ { 5, 90, 146 }, -+ { 1, 60, 103 }, -+ { 1, 38, 65 }, -+ { 1, 18, 30 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 72, 202, 223 }, -+ { 23, 141, 199 }, -+ { 2, 86, 140 }, -+ { 1, 56, 97 }, -+ { 1, 36, 61 }, -+ { 1, 16, 27 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 55, 218, 225 }, -+ { 13, 145, 200 }, -+ { 1, 86, 141 }, -+ { 1, 57, 99 }, -+ { 1, 35, 61 }, -+ { 1, 13, 22 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 15, 235, 212 }, -+ { 1, 132, 184 }, -+ { 1, 84, 139 }, -+ { 1, 57, 97 }, -+ { 1, 34, 56 }, -+ { 1, 14, 23 }, -+ }, -+ }, -+ }, -+ { /* block Type 1 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 181, 21, 201 }, -+ { 61, 37, 123 }, -+ { 10, 38, 71 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 47, 106, 172 }, -+ { 95, 104, 173 }, -+ { 42, 93, 159 }, -+ { 18, 77, 131 }, -+ { 4, 50, 81 }, -+ { 1, 17, 23 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 62, 147, 199 }, -+ { 44, 130, 189 }, -+ { 28, 102, 154 }, -+ { 18, 75, 115 }, -+ { 2, 44, 65 }, -+ { 1, 12, 19 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 55, 153, 210 }, -+ { 24, 130, 194 }, -+ { 3, 93, 146 }, -+ { 1, 61, 97 }, -+ { 1, 31, 50 }, -+ { 1, 10, 16 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 49, 186, 223 }, -+ { 17, 148, 204 }, -+ { 1, 96, 142 }, -+ { 1, 53, 83 }, -+ { 1, 26, 44 }, -+ { 1, 11, 17 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 13, 217, 212 }, -+ { 2, 136, 180 }, -+ { 1, 78, 124 }, -+ { 1, 50, 83 }, -+ { 1, 29, 49 }, -+ { 1, 14, 23 }, -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 197, 13, 247 }, -+ { 82, 17, 222 }, -+ { 25, 17, 162 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 126, 186, 247 }, -+ { 234, 191, 243 }, -+ { 176, 177, 234 }, -+ { 104, 158, 220 }, -+ { 66, 128, 186 }, -+ { 55, 90, 137 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 111, 197, 242 }, -+ { 46, 158, 219 }, -+ { 9, 104, 171 }, -+ { 2, 65, 125 }, -+ { 1, 44, 80 }, -+ { 1, 17, 91 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 104, 208, 245 }, -+ { 39, 168, 224 }, -+ { 3, 109, 162 }, -+ { 1, 79, 124 }, -+ { 1, 50, 102 }, -+ { 1, 43, 102 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 84, 220, 246 }, -+ { 31, 177, 231 }, -+ { 2, 115, 180 }, -+ { 1, 79, 134 }, -+ { 1, 55, 77 }, -+ { 1, 60, 79 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 43, 243, 240 }, -+ { 8, 180, 217 }, -+ { 1, 115, 166 }, -+ { 1, 84, 121 }, -+ { 1, 51, 67 }, -+ { 1, 16, 6 }, -+ }, -+ }, -+ }, -+ }, -+ }, -+ -+ .skip = { 192, 128, 64 }, -+ .inter_mode = { -+ { 2, 173, 34 }, -+ { 7, 145, 85 }, -+ { 7, 166, 63 }, -+ { 7, 94, 66 }, -+ { 8, 64, 46 }, -+ { 17, 81, 31 }, -+ { 25, 29, 30 }, -+ }, -+ .interp_filter = { -+ { 235, 162 }, -+ { 36, 255 }, -+ { 34, 3 }, -+ { 149, 144 }, -+ }, -+ .is_inter = { 9, 102, 187, 225 }, -+ .comp_mode = { 239, 183, 119, 96, 41 }, -+ .single_ref = { -+ { 33, 16 }, -+ { 77, 74 }, -+ { 142, 142 }, -+ { 172, 170 }, -+ { 238, 247 }, -+ }, -+ .comp_ref = { 50, 126, 123, 221, 226 }, -+ .y_mode = { -+ { 65, 32, 18, 144, 162, 194, 41, 51, 98 }, -+ { 132, 68, 18, 165, 217, 196, 45, 40, 78 }, -+ { 173, 80, 19, 176, 240, 193, 64, 35, 46 }, -+ { 221, 135, 38, 194, 248, 121, 96, 85, 29 }, -+ }, -+ .uv_mode = { -+ { 120, 7, 76, 176, 208, 126, 28, 54, 103 } /* y = dc */, -+ { 48, 12, 154, 155, 139, 90, 34, 117, 119 } /* y = v */, -+ { 67, 6, 25, 204, 243, 158, 13, 21, 96 } /* y = h */, -+ { 97, 5, 44, 131, 176, 139, 48, 68, 97 } /* y = d45 */, -+ { 83, 5, 42, 156, 111, 152, 26, 49, 152 } /* y = d135 */, -+ { 80, 5, 58, 178, 74, 83, 33, 62, 145 } /* y = d117 */, -+ { 86, 5, 32, 154, 192, 168, 14, 22, 163 } /* y = d153 */, -+ { 85, 5, 32, 156, 216, 148, 19, 29, 73 } /* y = d207 */, -+ { 77, 7, 64, 116, 132, 122, 37, 126, 120 } /* y = d63 */, -+ { 101, 21, 107, 181, 192, 103, 19, 67, 125 } /* y = tm */ -+ }, -+ .partition = { -+ /* 8x8 -> 4x4 */ -+ { 199, 122, 141 } /* a/l both not split */, -+ { 147, 63, 159 } /* a split, l not split */, -+ { 148, 133, 118 } /* l split, a not split */, -+ { 121, 104, 114 } /* a/l both split */, -+ /* 16x16 -> 8x8 */ -+ { 174, 73, 87 } /* a/l both not split */, -+ { 92, 41, 83 } /* a split, l not split */, -+ { 82, 99, 50 } /* l split, a not split */, -+ { 53, 39, 39 } /* a/l both split */, -+ /* 32x32 -> 16x16 */ -+ { 177, 58, 59 } /* a/l both not split */, -+ { 68, 26, 63 } /* a split, l not split */, -+ { 52, 79, 25 } /* l split, a not split */, -+ { 17, 14, 12 } /* a/l both split */, -+ /* 64x64 -> 32x32 */ -+ { 222, 34, 30 } /* a/l both not split */, -+ { 72, 16, 44 } /* a split, l not split */, -+ { 58, 32, 12 } /* l split, a not split */, -+ { 10, 7, 6 } /* a/l both split */, -+ }, -+ -+ .mv = { -+ .joint = { 32, 64, 96 }, -+ .sign = { 128, 128 }, -+ .classes = { -+ { 224, 144, 192, 168, 192, 176, 192, 198, 198, 245 }, -+ { 216, 128, 176, 160, 176, 176, 192, 198, 198, 208 }, -+ }, -+ .class0_bit = { 216, 208 }, -+ .bits = { -+ { 136, 140, 148, 160, 176, 192, 224, 234, 234, 240}, -+ { 136, 140, 148, 160, 176, 192, 224, 234, 234, 240}, -+ }, -+ .class0_fr = { -+ { -+ { 128, 128, 64 }, -+ { 96, 112, 64 }, -+ }, -+ { -+ { 128, 128, 64 }, -+ { 96, 112, 64 }, -+ }, -+ }, -+ .fr = { -+ { 64, 96, 64 }, -+ { 64, 96, 64 }, -+ }, -+ .class0_hp = { 160, 160 }, -+ .hp = { 128, 128 }, -+ }, -+}; -+EXPORT_SYMBOL_GPL(v4l2_vp9_default_probs); -+ -+static u32 fastdiv(u32 dividend, u16 divisor) -+{ -+#define DIV_INV(d) ((u32)(((1ULL << 32) + ((d) - 1)) / (d))) -+#define DIVS_INV(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9) \ -+ DIV_INV(d0), DIV_INV(d1), DIV_INV(d2), DIV_INV(d3), \ -+ DIV_INV(d4), DIV_INV(d5), DIV_INV(d6), DIV_INV(d7), \ -+ DIV_INV(d8), DIV_INV(d9) -+ -+ static const u32 inv[] = { -+ DIV_INV(2), DIV_INV(3), DIV_INV(4), DIV_INV(5), -+ DIV_INV(6), DIV_INV(7), DIV_INV(8), DIV_INV(9), -+ DIVS_INV(10, 11, 12, 13, 14, 15, 16, 17, 18, 19), -+ DIVS_INV(20, 21, 22, 23, 24, 25, 26, 27, 28, 29), -+ DIVS_INV(30, 31, 32, 33, 34, 35, 36, 37, 38, 39), -+ DIVS_INV(40, 41, 42, 43, 44, 45, 46, 47, 48, 49), -+ DIVS_INV(50, 51, 52, 53, 54, 55, 56, 57, 58, 59), -+ DIVS_INV(60, 61, 62, 63, 64, 65, 66, 67, 68, 69), -+ DIVS_INV(70, 71, 72, 73, 74, 75, 76, 77, 78, 79), -+ DIVS_INV(80, 81, 82, 83, 84, 85, 86, 87, 88, 89), -+ DIVS_INV(90, 91, 92, 93, 94, 95, 96, 97, 98, 99), -+ DIVS_INV(100, 101, 102, 103, 104, 105, 106, 107, 108, 109), -+ DIVS_INV(110, 111, 112, 113, 114, 115, 116, 117, 118, 119), -+ DIVS_INV(120, 121, 122, 123, 124, 125, 126, 127, 128, 129), -+ DIVS_INV(130, 131, 132, 133, 134, 135, 136, 137, 138, 139), -+ DIVS_INV(140, 141, 142, 143, 144, 145, 146, 147, 148, 149), -+ DIVS_INV(150, 151, 152, 153, 154, 155, 156, 157, 158, 159), -+ DIVS_INV(160, 161, 162, 163, 164, 165, 166, 167, 168, 169), -+ DIVS_INV(170, 171, 172, 173, 174, 175, 176, 177, 178, 179), -+ DIVS_INV(180, 181, 182, 183, 184, 185, 186, 187, 188, 189), -+ DIVS_INV(190, 191, 192, 193, 194, 195, 196, 197, 198, 199), -+ DIVS_INV(200, 201, 202, 203, 204, 205, 206, 207, 208, 209), -+ DIVS_INV(210, 211, 212, 213, 214, 215, 216, 217, 218, 219), -+ DIVS_INV(220, 221, 222, 223, 224, 225, 226, 227, 228, 229), -+ DIVS_INV(230, 231, 232, 233, 234, 235, 236, 237, 238, 239), -+ DIVS_INV(240, 241, 242, 243, 244, 245, 246, 247, 248, 249), -+ DIV_INV(250), DIV_INV(251), DIV_INV(252), DIV_INV(253), -+ DIV_INV(254), DIV_INV(255), DIV_INV(256), -+ }; -+ -+ if (divisor == 0) -+ return 0; -+ else if (divisor == 1) -+ return dividend; -+ -+ if (WARN_ON(divisor - 2 >= ARRAY_SIZE(inv))) -+ return dividend; -+ -+ return ((u64)dividend * inv[divisor - 2]) >> 32; -+} -+ -+/* 6.3.6 inv_recenter_nonneg(v, m) */ -+static int inv_recenter_nonneg(int v, int m) -+{ -+ if (v > 2 * m) -+ return v; -+ -+ if (v & 1) -+ return m - ((v + 1) >> 1); -+ -+ return m + (v >> 1); -+} -+ -+/* -+ * part of 6.3.5 inv_remap_prob(deltaProb, prob) -+ * delta = inv_map_table[deltaProb] done by userspace -+ */ -+static int update_prob(int delta, int prob) -+{ -+ if (!delta) -+ return prob; -+ -+ return prob <= 128 ? -+ 1 + inv_recenter_nonneg(delta, prob - 1) : -+ 255 - inv_recenter_nonneg(delta, 255 - prob); -+} -+ -+/* Counterpart to 6.3.2 tx_mode_probs() */ -+static void update_tx_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->tx8); i++) { -+ u8 *p8x8 = probs->tx8[i]; -+ u8 *p16x16 = probs->tx16[i]; -+ u8 *p32x32 = probs->tx32[i]; -+ const u8 *d8x8 = deltas->tx8[i]; -+ const u8 *d16x16 = deltas->tx16[i]; -+ const u8 *d32x32 = deltas->tx32[i]; -+ -+ p8x8[0] = update_prob(d8x8[0], p8x8[0]); -+ p16x16[0] = update_prob(d16x16[0], p16x16[0]); -+ p16x16[1] = update_prob(d16x16[1], p16x16[1]); -+ p32x32[0] = update_prob(d32x32[0], p32x32[0]); -+ p32x32[1] = update_prob(d32x32[1], p32x32[1]); -+ p32x32[2] = update_prob(d32x32[2], p32x32[2]); -+ } -+} -+ -+#define BAND_6(band) ((band) == 0 ? 3 : 6) -+ -+static void update_coeff(const u8 deltas[6][6][3], u8 probs[6][6][3]) -+{ -+ int l, m, n; -+ -+ for (l = 0; l < 6; l++) -+ for (m = 0; m < BAND_6(l); m++) { -+ u8 *p = probs[l][m]; -+ const u8 *d = deltas[l][m]; -+ -+ for (n = 0; n < 3; n++) -+ p[n] = update_prob(d[n], p[n]); -+ } -+} -+ -+/* Counterpart to 6.3.7 read_coef_probs() */ -+static void update_coef_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ int i, j, k; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->coef); i++) { -+ for (j = 0; j < ARRAY_SIZE(probs->coef[0]); j++) -+ for (k = 0; k < ARRAY_SIZE(probs->coef[0][0]); k++) -+ update_coeff(deltas->coef[i][j][k], probs->coef[i][j][k]); -+ -+ if (deltas->tx_mode == i) -+ break; -+ } -+} -+ -+/* Counterpart to 6.3.8 read_skip_prob() */ -+static void update_skip_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->skip); i++) -+ probs->skip[i] = update_prob(deltas->skip[i], probs->skip[i]); -+} -+ -+/* Counterpart to 6.3.9 read_inter_mode_probs() */ -+static void update_inter_mode_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->inter_mode); i++) { -+ u8 *p = probs->inter_mode[i]; -+ const u8 *d = deltas->inter_mode[i]; -+ -+ p[0] = update_prob(d[0], p[0]); -+ p[1] = update_prob(d[1], p[1]); -+ p[2] = update_prob(d[2], p[2]); -+ } -+} -+ -+/* Counterpart to 6.3.10 read_interp_filter_probs() */ -+static void update_interp_filter_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->interp_filter); i++) { -+ u8 *p = probs->interp_filter[i]; -+ const u8 *d = deltas->interp_filter[i]; -+ -+ p[0] = update_prob(d[0], p[0]); -+ p[1] = update_prob(d[1], p[1]); -+ } -+} -+ -+/* Counterpart to 6.3.11 read_is_inter_probs() */ -+static void update_is_inter_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->is_inter); i++) -+ probs->is_inter[i] = update_prob(deltas->is_inter[i], probs->is_inter[i]); -+} -+ -+/* 6.3.12 frame_reference_mode() done entirely in userspace */ -+ -+/* Counterpart to 6.3.13 frame_reference_mode_probs() */ -+static void -+update_frame_reference_mode_probs(unsigned int reference_mode, -+ struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ if (reference_mode == V4L2_VP9_REFERENCE_MODE_SELECT) -+ for (i = 0; i < ARRAY_SIZE(probs->comp_mode); i++) -+ probs->comp_mode[i] = update_prob(deltas->comp_mode[i], -+ probs->comp_mode[i]); -+ -+ if (reference_mode != V4L2_VP9_REFERENCE_MODE_COMPOUND_REFERENCE) -+ for (i = 0; i < ARRAY_SIZE(probs->single_ref); i++) { -+ u8 *p = probs->single_ref[i]; -+ const u8 *d = deltas->single_ref[i]; -+ -+ p[0] = update_prob(d[0], p[0]); -+ p[1] = update_prob(d[1], p[1]); -+ } -+ -+ if (reference_mode != V4L2_VP9_REFERENCE_MODE_SINGLE_REFERENCE) -+ for (i = 0; i < ARRAY_SIZE(probs->comp_ref); i++) -+ probs->comp_ref[i] = update_prob(deltas->comp_ref[i], probs->comp_ref[i]); -+} -+ -+/* Counterpart to 6.3.14 read_y_mode_probs() */ -+static void update_y_mode_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i, j; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->y_mode); i++) -+ for (j = 0; j < ARRAY_SIZE(probs->y_mode[0]); ++j) -+ probs->y_mode[i][j] = -+ update_prob(deltas->y_mode[i][j], probs->y_mode[i][j]); -+} -+ -+/* Counterpart to 6.3.15 read_partition_probs() */ -+static void update_partition_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i, j; -+ -+ for (i = 0; i < 4; i++) -+ for (j = 0; j < 4; j++) { -+ u8 *p = probs->partition[i * 4 + j]; -+ const u8 *d = deltas->partition[i * 4 + j]; -+ -+ p[0] = update_prob(d[0], p[0]); -+ p[1] = update_prob(d[1], p[1]); -+ p[2] = update_prob(d[2], p[2]); -+ } -+} -+ -+static inline int update_mv_prob(int delta, int prob) -+{ -+ if (!delta) -+ return prob; -+ -+ return delta; -+} -+ -+/* Counterpart to 6.3.16 mv_probs() */ -+static void update_mv_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ u8 *p = probs->mv.joint; -+ const u8 *d = deltas->mv.joint; -+ unsigned int i, j; -+ -+ p[0] = update_mv_prob(d[0], p[0]); -+ p[1] = update_mv_prob(d[1], p[1]); -+ p[2] = update_mv_prob(d[2], p[2]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->mv.sign); i++) { -+ p = probs->mv.sign; -+ d = deltas->mv.sign; -+ p[i] = update_mv_prob(d[i], p[i]); -+ -+ p = probs->mv.classes[i]; -+ d = deltas->mv.classes[i]; -+ for (j = 0; j < ARRAY_SIZE(probs->mv.classes[0]); j++) -+ p[j] = update_mv_prob(d[j], p[j]); -+ -+ p = probs->mv.class0_bit; -+ d = deltas->mv.class0_bit; -+ p[i] = update_mv_prob(d[i], p[i]); -+ -+ p = probs->mv.bits[i]; -+ d = deltas->mv.bits[i]; -+ for (j = 0; j < ARRAY_SIZE(probs->mv.bits[0]); j++) -+ p[j] = update_mv_prob(d[j], p[j]); -+ -+ for (j = 0; j < ARRAY_SIZE(probs->mv.class0_fr[0]); j++) { -+ p = probs->mv.class0_fr[i][j]; -+ d = deltas->mv.class0_fr[i][j]; -+ -+ p[0] = update_mv_prob(d[0], p[0]); -+ p[1] = update_mv_prob(d[1], p[1]); -+ p[2] = update_mv_prob(d[2], p[2]); -+ } -+ -+ p = probs->mv.fr[i]; -+ d = deltas->mv.fr[i]; -+ for (j = 0; j < ARRAY_SIZE(probs->mv.fr[i]); j++) -+ p[j] = update_mv_prob(d[j], p[j]); -+ -+ if (dec_params->flags & V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV) { -+ p = probs->mv.class0_hp; -+ d = deltas->mv.class0_hp; -+ p[i] = update_mv_prob(d[i], p[i]); -+ -+ p = probs->mv.hp; -+ d = deltas->mv.hp; -+ p[i] = update_mv_prob(d[i], p[i]); -+ } -+ } -+} -+ -+/* Counterpart to 6.3 compressed_header(), but parsing has been done in userspace. */ -+void v4l2_vp9_fw_update_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ if (deltas->tx_mode == V4L2_VP9_TX_MODE_SELECT) -+ update_tx_probs(probs, deltas); -+ -+ update_coef_probs(probs, deltas, dec_params); -+ -+ update_skip_probs(probs, deltas); -+ -+ if (dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME || -+ dec_params->flags & V4L2_VP9_FRAME_FLAG_INTRA_ONLY) -+ return; -+ -+ update_inter_mode_probs(probs, deltas); -+ -+ if (dec_params->interpolation_filter == V4L2_VP9_INTERP_FILTER_SWITCHABLE) -+ update_interp_filter_probs(probs, deltas); -+ -+ update_is_inter_probs(probs, deltas); -+ -+ update_frame_reference_mode_probs(dec_params->reference_mode, probs, deltas); -+ -+ update_y_mode_probs(probs, deltas); -+ -+ update_partition_probs(probs, deltas); -+ -+ update_mv_probs(probs, deltas, dec_params); -+} -+EXPORT_SYMBOL_GPL(v4l2_vp9_fw_update_probs); -+ -+u8 v4l2_vp9_reset_frame_ctx(const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct v4l2_vp9_frame_context *frame_context) -+{ -+ int i; -+ -+ u8 fctx_idx = dec_params->frame_context_idx; -+ -+ if (dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME || -+ dec_params->flags & V4L2_VP9_FRAME_FLAG_INTRA_ONLY || -+ dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) { -+ /* -+ * setup_past_independence() -+ * We do nothing here. Instead of storing default probs in some intermediate -+ * location and then copying from that location to appropriate contexts -+ * in save_probs() below, we skip that step and save default probs directly -+ * to appropriate contexts. -+ */ -+ if (dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME || -+ dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT || -+ dec_params->reset_frame_context == V4L2_VP9_RESET_FRAME_CTX_ALL) -+ for (i = 0; i < 4; ++i) -+ /* save_probs(i) */ -+ memcpy(&frame_context[i], &v4l2_vp9_default_probs, -+ sizeof(v4l2_vp9_default_probs)); -+ else if (dec_params->reset_frame_context == V4L2_VP9_RESET_FRAME_CTX_SPEC) -+ /* save_probs(fctx_idx) */ -+ memcpy(&frame_context[fctx_idx], &v4l2_vp9_default_probs, -+ sizeof(v4l2_vp9_default_probs)); -+ fctx_idx = 0; -+ } -+ -+ return fctx_idx; -+} -+EXPORT_SYMBOL_GPL(v4l2_vp9_reset_frame_ctx); -+ -+/* 8.4.1 Merge prob process */ -+static u8 merge_prob(u8 pre_prob, u32 ct0, u32 ct1, u16 count_sat, u32 max_update_factor) -+{ -+ u32 den, prob, count, factor; -+ -+ den = ct0 + ct1; -+ if (!den) { -+ /* -+ * prob = 128, count = 0, update_factor = 0 -+ * Round2's argument: pre_prob * 256 -+ * (pre_prob * 256 + 128) >> 8 == pre_prob -+ */ -+ return pre_prob; -+ } -+ -+ prob = clamp(((ct0 << 8) + (den >> 1)) / den, (u32)1, (u32)255); -+ count = min_t(u32, den, count_sat); -+ factor = fastdiv(max_update_factor * count, count_sat); -+ -+ /* -+ * Round2(pre_prob * (256 - factor) + prob * factor, 8) -+ * Round2(pre_prob * 256 + (prob - pre_prob) * factor, 8) -+ * (pre_prob * 256 >> 8) + (((prob - pre_prob) * factor + 128) >> 8) -+ */ -+ return pre_prob + (((prob - pre_prob) * factor + 128) >> 8); -+} -+ -+static inline u8 noncoef_merge_prob(u8 pre_prob, u32 ct0, u32 ct1) -+{ -+ return merge_prob(pre_prob, ct0, ct1, 20, 128); -+} -+ -+/* 8.4.2 Merge probs process */ -+/* -+ * merge_probs() is a recursive function in the spec. We avoid recursion in the kernel. -+ * That said, the "tree" parameter of merge_probs() controls how deep the recursion goes. -+ * It turns out that in all cases the recursive calls boil down to a short-ish series -+ * of merge_prob() invocations (note no "s"). -+ * -+ * Variant A -+ * --------- -+ * merge_probs(small_token_tree, 2): -+ * merge_prob(p[1], c[0], c[1] + c[2]) -+ * merge_prob(p[2], c[1], c[2]) -+ * -+ * Variant B -+ * --------- -+ * merge_probs(binary_tree, 0) or -+ * merge_probs(tx_size_8_tree, 0): -+ * merge_prob(p[0], c[0], c[1]) -+ * -+ * Variant C -+ * --------- -+ * merge_probs(inter_mode_tree, 0): -+ * merge_prob(p[0], c[2], c[1] + c[0] + c[3]) -+ * merge_prob(p[1], c[0], c[1] + c[3]) -+ * merge_prob(p[2], c[1], c[3]) -+ * -+ * Variant D -+ * --------- -+ * merge_probs(intra_mode_tree, 0): -+ * merge_prob(p[0], c[0], c[1] + ... + c[9]) -+ * merge_prob(p[1], c[9], c[1] + ... + c[8]) -+ * merge_prob(p[2], c[1], c[2] + ... + c[8]) -+ * merge_prob(p[3], c[2] + c[4] + c[5], c[3] + c[8] + c[6] + c[7]) -+ * merge_prob(p[4], c[2], c[4] + c[5]) -+ * merge_prob(p[5], c[4], c[5]) -+ * merge_prob(p[6], c[3], c[8] + c[6] + c[7]) -+ * merge_prob(p[7], c[8], c[6] + c[7]) -+ * merge_prob(p[8], c[6], c[7]) -+ * -+ * Variant E -+ * --------- -+ * merge_probs(partition_tree, 0) or -+ * merge_probs(tx_size_32_tree, 0) or -+ * merge_probs(mv_joint_tree, 0) or -+ * merge_probs(mv_fr_tree, 0): -+ * merge_prob(p[0], c[0], c[1] + c[2] + c[3]) -+ * merge_prob(p[1], c[1], c[2] + c[3]) -+ * merge_prob(p[2], c[2], c[3]) -+ * -+ * Variant F -+ * --------- -+ * merge_probs(interp_filter_tree, 0) or -+ * merge_probs(tx_size_16_tree, 0): -+ * merge_prob(p[0], c[0], c[1] + c[2]) -+ * merge_prob(p[1], c[1], c[2]) -+ * -+ * Variant G -+ * --------- -+ * merge_probs(mv_class_tree, 0): -+ * merge_prob(p[0], c[0], c[1] + ... + c[10]) -+ * merge_prob(p[1], c[1], c[2] + ... + c[10]) -+ * merge_prob(p[2], c[2] + c[3], c[4] + ... + c[10]) -+ * merge_prob(p[3], c[2], c[3]) -+ * merge_prob(p[4], c[4] + c[5], c[6] + ... + c[10]) -+ * merge_prob(p[5], c[4], c[5]) -+ * merge_prob(p[6], c[6], c[7] + ... + c[10]) -+ * merge_prob(p[7], c[7] + c[8], c[9] + c[10]) -+ * merge_prob(p[8], c[7], c[8]) -+ * merge_prob(p[9], c[9], [10]) -+ */ -+ -+static inline void merge_probs_variant_a(u8 *p, const u32 *c, u16 count_sat, u32 update_factor) -+{ -+ p[1] = merge_prob(p[1], c[0], c[1] + c[2], count_sat, update_factor); -+ p[2] = merge_prob(p[2], c[1], c[2], count_sat, update_factor); -+} -+ -+static inline void merge_probs_variant_b(u8 *p, const u32 *c, u16 count_sat, u32 update_factor) -+{ -+ p[0] = merge_prob(p[0], c[0], c[1], count_sat, update_factor); -+} -+ -+static inline void merge_probs_variant_c(u8 *p, const u32 *c) -+{ -+ p[0] = noncoef_merge_prob(p[0], c[2], c[1] + c[0] + c[3]); -+ p[1] = noncoef_merge_prob(p[1], c[0], c[1] + c[3]); -+ p[2] = noncoef_merge_prob(p[2], c[1], c[3]); -+} -+ -+static void merge_probs_variant_d(u8 *p, const u32 *c) -+{ -+ u32 sum = 0, s2; -+ -+ sum = c[1] + c[2] + c[3] + c[4] + c[5] + c[6] + c[7] + c[8] + c[9]; -+ -+ p[0] = noncoef_merge_prob(p[0], c[0], sum); -+ sum -= c[9]; -+ p[1] = noncoef_merge_prob(p[1], c[9], sum); -+ sum -= c[1]; -+ p[2] = noncoef_merge_prob(p[2], c[1], sum); -+ s2 = c[2] + c[4] + c[5]; -+ sum -= s2; -+ p[3] = noncoef_merge_prob(p[3], s2, sum); -+ s2 -= c[2]; -+ p[4] = noncoef_merge_prob(p[4], c[2], s2); -+ p[5] = noncoef_merge_prob(p[5], c[4], c[5]); -+ sum -= c[3]; -+ p[6] = noncoef_merge_prob(p[6], c[3], sum); -+ sum -= c[8]; -+ p[7] = noncoef_merge_prob(p[7], c[8], sum); -+ p[8] = noncoef_merge_prob(p[8], c[6], c[7]); -+} -+ -+static inline void merge_probs_variant_e(u8 *p, const u32 *c) -+{ -+ p[0] = noncoef_merge_prob(p[0], c[0], c[1] + c[2] + c[3]); -+ p[1] = noncoef_merge_prob(p[1], c[1], c[2] + c[3]); -+ p[2] = noncoef_merge_prob(p[2], c[2], c[3]); -+} -+ -+static inline void merge_probs_variant_f(u8 *p, const u32 *c) -+{ -+ p[0] = noncoef_merge_prob(p[0], c[0], c[1] + c[2]); -+ p[1] = noncoef_merge_prob(p[1], c[1], c[2]); -+} -+ -+static void merge_probs_variant_g(u8 *p, const u32 *c) -+{ -+ u32 sum; -+ -+ sum = c[1] + c[2] + c[3] + c[4] + c[5] + c[6] + c[7] + c[8] + c[9] + c[10]; -+ p[0] = noncoef_merge_prob(p[0], c[0], sum); -+ sum -= c[1]; -+ p[1] = noncoef_merge_prob(p[1], c[1], sum); -+ sum -= c[2] + c[3]; -+ p[2] = noncoef_merge_prob(p[2], c[2] + c[3], sum); -+ p[3] = noncoef_merge_prob(p[3], c[2], c[3]); -+ sum -= c[4] + c[5]; -+ p[4] = noncoef_merge_prob(p[4], c[4] + c[5], sum); -+ p[5] = noncoef_merge_prob(p[5], c[4], c[5]); -+ sum -= c[6]; -+ p[6] = noncoef_merge_prob(p[6], c[6], sum); -+ p[7] = noncoef_merge_prob(p[7], c[7] + c[8], c[9] + c[10]); -+ p[8] = noncoef_merge_prob(p[8], c[7], c[8]); -+ p[9] = noncoef_merge_prob(p[9], c[9], c[10]); -+} -+ -+/* 8.4.3 Coefficient probability adaptation process */ -+static inline void adapt_probs_variant_a_coef(u8 *p, const u32 *c, u32 update_factor) -+{ -+ merge_probs_variant_a(p, c, 24, update_factor); -+} -+ -+static inline void adapt_probs_variant_b_coef(u8 *p, const u32 *c, u32 update_factor) -+{ -+ merge_probs_variant_b(p, c, 24, update_factor); -+} -+ -+static void _adapt_coeff(unsigned int i, unsigned int j, unsigned int k, -+ struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_vp9_frame_symbol_counts *counts, -+ u32 uf) -+{ -+ s32 l, m; -+ -+ for (l = 0; l < ARRAY_SIZE(probs->coef[0][0][0]); l++) { -+ for (m = 0; m < BAND_6(l); m++) { -+ u8 *p = probs->coef[i][j][k][l][m]; -+ const u32 counts_more_coefs[2] = { -+ *counts->eob[i][j][k][l][m][1], -+ *counts->eob[i][j][k][l][m][0] - *counts->eob[i][j][k][l][m][1], -+ }; -+ -+ adapt_probs_variant_a_coef(p, *counts->coeff[i][j][k][l][m], uf); -+ adapt_probs_variant_b_coef(p, counts_more_coefs, uf); -+ } -+ } -+} -+ -+static void _adapt_coef_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_vp9_frame_symbol_counts *counts, -+ unsigned int uf) -+{ -+ unsigned int i, j, k; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->coef); i++) -+ for (j = 0; j < ARRAY_SIZE(probs->coef[0]); j++) -+ for (k = 0; k < ARRAY_SIZE(probs->coef[0][0]); k++) -+ _adapt_coeff(i, j, k, probs, counts, uf); -+} -+ -+void v4l2_vp9_adapt_coef_probs(struct v4l2_vp9_frame_context *probs, -+ struct v4l2_vp9_frame_symbol_counts *counts, -+ bool use_128, -+ bool frame_is_intra) -+{ -+ if (frame_is_intra) { -+ _adapt_coef_probs(probs, counts, 112); -+ } else { -+ if (use_128) -+ _adapt_coef_probs(probs, counts, 128); -+ else -+ _adapt_coef_probs(probs, counts, 112); -+ } -+} -+EXPORT_SYMBOL_GPL(v4l2_vp9_adapt_coef_probs); -+ -+/* 8.4.4 Non coefficient probability adaptation process, adapt_probs() */ -+static inline void adapt_probs_variant_b(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_b(p, c, 20, 128); -+} -+ -+static inline void adapt_probs_variant_c(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_c(p, c); -+} -+ -+static inline void adapt_probs_variant_d(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_d(p, c); -+} -+ -+static inline void adapt_probs_variant_e(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_e(p, c); -+} -+ -+static inline void adapt_probs_variant_f(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_f(p, c); -+} -+ -+static inline void adapt_probs_variant_g(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_g(p, c); -+} -+ -+/* 8.4.4 Non coefficient probability adaptation process, adapt_prob() */ -+static inline u8 adapt_prob(u8 prob, const u32 counts[2]) -+{ -+ return noncoef_merge_prob(prob, counts[0], counts[1]); -+} -+ -+/* 8.4.4 Non coefficient probability adaptation process */ -+void v4l2_vp9_adapt_noncoef_probs(struct v4l2_vp9_frame_context *probs, -+ struct v4l2_vp9_frame_symbol_counts *counts, -+ u8 reference_mode, u8 interpolation_filter, u8 tx_mode, -+ u32 flags) -+{ -+ unsigned int i, j; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->is_inter); i++) -+ probs->is_inter[i] = adapt_prob(probs->is_inter[i], (*counts->intra_inter)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->comp_mode); i++) -+ probs->comp_mode[i] = adapt_prob(probs->comp_mode[i], (*counts->comp)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->comp_ref); i++) -+ probs->comp_ref[i] = adapt_prob(probs->comp_ref[i], (*counts->comp_ref)[i]); -+ -+ if (reference_mode != V4L2_VP9_REFERENCE_MODE_COMPOUND_REFERENCE) -+ for (i = 0; i < ARRAY_SIZE(probs->single_ref); i++) -+ for (j = 0; j < ARRAY_SIZE(probs->single_ref[0]); j++) -+ probs->single_ref[i][j] = adapt_prob(probs->single_ref[i][j], -+ (*counts->single_ref)[i][j]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->inter_mode); i++) -+ adapt_probs_variant_c(probs->inter_mode[i], (*counts->mv_mode)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->y_mode); i++) -+ adapt_probs_variant_d(probs->y_mode[i], (*counts->y_mode)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->uv_mode); i++) -+ adapt_probs_variant_d(probs->uv_mode[i], (*counts->uv_mode)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->partition); i++) -+ adapt_probs_variant_e(probs->partition[i], (*counts->partition)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->skip); i++) -+ probs->skip[i] = adapt_prob(probs->skip[i], (*counts->skip)[i]); -+ -+ if (interpolation_filter == V4L2_VP9_INTERP_FILTER_SWITCHABLE) -+ for (i = 0; i < ARRAY_SIZE(probs->interp_filter); i++) -+ adapt_probs_variant_f(probs->interp_filter[i], (*counts->filter)[i]); -+ -+ if (tx_mode == V4L2_VP9_TX_MODE_SELECT) -+ for (i = 0; i < ARRAY_SIZE(probs->tx8); i++) { -+ adapt_probs_variant_b(probs->tx8[i], (*counts->tx8p)[i]); -+ adapt_probs_variant_f(probs->tx16[i], (*counts->tx16p)[i]); -+ adapt_probs_variant_e(probs->tx32[i], (*counts->tx32p)[i]); -+ } -+ -+ adapt_probs_variant_e(probs->mv.joint, *counts->mv_joint); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->mv.sign); i++) { -+ probs->mv.sign[i] = adapt_prob(probs->mv.sign[i], (*counts->sign)[i]); -+ -+ adapt_probs_variant_g(probs->mv.classes[i], (*counts->classes)[i]); -+ -+ probs->mv.class0_bit[i] = adapt_prob(probs->mv.class0_bit[i], (*counts->class0)[i]); -+ -+ for (j = 0; j < ARRAY_SIZE(probs->mv.bits[0]); j++) -+ probs->mv.bits[i][j] = adapt_prob(probs->mv.bits[i][j], -+ (*counts->bits)[i][j]); -+ -+ for (j = 0; j < ARRAY_SIZE(probs->mv.class0_fr[0]); j++) -+ adapt_probs_variant_e(probs->mv.class0_fr[i][j], -+ (*counts->class0_fp)[i][j]); -+ -+ adapt_probs_variant_e(probs->mv.fr[i], (*counts->fp)[i]); -+ -+ if (!(flags & V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV)) -+ continue; -+ -+ probs->mv.class0_hp[i] = adapt_prob(probs->mv.class0_hp[i], -+ (*counts->class0_hp)[i]); -+ -+ probs->mv.hp[i] = adapt_prob(probs->mv.hp[i], (*counts->hp)[i]); -+ } -+} -+EXPORT_SYMBOL_GPL(v4l2_vp9_adapt_noncoef_probs); -+ -+bool -+v4l2_vp9_seg_feat_enabled(const u8 *feature_enabled, -+ unsigned int feature, -+ unsigned int segid) -+{ -+ u8 mask = V4L2_VP9_SEGMENT_FEATURE_ENABLED(feature); -+ -+ return !!(feature_enabled[segid] & mask); -+} -+EXPORT_SYMBOL_GPL(v4l2_vp9_seg_feat_enabled); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("V4L2 VP9 Helpers"); -+MODULE_AUTHOR("Andrzej Pietrasiewicz "); -diff --git a/include/media/v4l2-vp9.h b/include/media/v4l2-vp9.h -new file mode 100644 -index 000000000000..05478ad6d4ab ---- /dev/null -+++ b/include/media/v4l2-vp9.h -@@ -0,0 +1,233 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * Helper functions for vp9 codecs. -+ * -+ * Copyright (c) 2021 Collabora, Ltd. -+ * -+ * Author: Andrzej Pietrasiewicz -+ */ -+ -+#ifndef _MEDIA_V4L2_VP9_H -+#define _MEDIA_V4L2_VP9_H -+ -+#include -+ -+/** -+ * struct v4l2_vp9_frame_mv_context - motion vector-related probabilities -+ * -+ * @joint: motion vector joint probabilities. -+ * @sign: motion vector sign probabilities. -+ * @classes: motion vector class probabilities. -+ * @class0_bit: motion vector class0 bit probabilities. -+ * @bits: motion vector bits probabilities. -+ * @class0_fr: motion vector class0 fractional bit probabilities. -+ * @fr: motion vector fractional bit probabilities. -+ * @class0_hp: motion vector class0 high precision fractional bit probabilities. -+ * @hp: motion vector high precision fractional bit probabilities. -+ * -+ * A member of v4l2_vp9_frame_context. -+ */ -+struct v4l2_vp9_frame_mv_context { -+ u8 joint[3]; -+ u8 sign[2]; -+ u8 classes[2][10]; -+ u8 class0_bit[2]; -+ u8 bits[2][10]; -+ u8 class0_fr[2][2][3]; -+ u8 fr[2][3]; -+ u8 class0_hp[2]; -+ u8 hp[2]; -+}; -+ -+/** -+ * struct v4l2_vp9_frame_context - frame probabilities, including motion-vector related -+ * -+ * @tx8: TX 8x8 probabilities. -+ * @tx16: TX 16x16 probabilities. -+ * @tx32: TX 32x32 probabilities. -+ * @coef: coefficient probabilities. -+ * @skip: skip probabilities. -+ * @inter_mode: inter mode probabilities. -+ * @interp_filter: interpolation filter probabilities. -+ * @is_inter: is inter-block probabilities. -+ * @comp_mode: compound prediction mode probabilities. -+ * @single_ref: single ref probabilities. -+ * @comp_ref: compound ref probabilities. -+ * @y_mode: Y prediction mode probabilities. -+ * @uv_mode: UV prediction mode probabilities. -+ * @partition: partition probabilities. -+ * @mv: motion vector probabilities. -+ * -+ * Drivers which need to keep track of frame context(s) can use this struct. -+ * The members correspond to probability tables, which are specified only implicitly in the -+ * vp9 spec. Section 10.5 "Default probability tables" contains all the types of involved -+ * tables, i.e. the actual tables are of the same kind, and when they are reset (which is -+ * mandated by the spec sometimes) they are overwritten with values from the default tables. -+ */ -+struct v4l2_vp9_frame_context { -+ u8 tx8[2][1]; -+ u8 tx16[2][2]; -+ u8 tx32[2][3]; -+ u8 coef[4][2][2][6][6][3]; -+ u8 skip[3]; -+ u8 inter_mode[7][3]; -+ u8 interp_filter[4][2]; -+ u8 is_inter[4]; -+ u8 comp_mode[5]; -+ u8 single_ref[5][2]; -+ u8 comp_ref[5]; -+ u8 y_mode[4][9]; -+ u8 uv_mode[10][9]; -+ u8 partition[16][3]; -+ -+ struct v4l2_vp9_frame_mv_context mv; -+}; -+ -+/** -+ * struct v4l2_vp9_frame_symbol_counts - pointers to arrays of symbol counts -+ * -+ * @partition: partition counts. -+ * @skip: skip counts. -+ * @intra_inter: is inter-block counts. -+ * @tx32p: TX32 counts. -+ * @tx16p: TX16 counts. -+ * @tx8p: TX8 counts. -+ * @y_mode: Y prediction mode counts. -+ * @uv_mode: UV prediction mode counts. -+ * @comp: compound prediction mode counts. -+ * @comp_ref: compound ref counts. -+ * @single_ref: single ref counts. -+ * @mv_mode: inter mode counts. -+ * @filter: interpolation filter counts. -+ * @mv_joint: motion vector joint counts. -+ * @sign: motion vector sign counts. -+ * @classes: motion vector class counts. -+ * @class0: motion vector class0 bit counts. -+ * @bits: motion vector bits counts. -+ * @class0_fp: motion vector class0 fractional bit counts. -+ * @fp: motion vector fractional bit counts. -+ * @class0_hp: motion vector class0 high precision fractional bit counts. -+ * @hp: motion vector high precision fractional bit counts. -+ * @coeff: coefficient counts. -+ * @eob: eob counts -+ * -+ * The fields correspond to what is specified in section 8.3 "Clear counts process" of the spec. -+ * Different pieces of hardware can report the counts in different order, so we cannot rely on -+ * simply overlaying a struct on a relevant block of memory. Instead we provide pointers to -+ * arrays or array of pointers to arrays in case of coeff, or array of pointers for eob. -+ */ -+struct v4l2_vp9_frame_symbol_counts { -+ u32 (*partition)[16][4]; -+ u32 (*skip)[3][2]; -+ u32 (*intra_inter)[4][2]; -+ u32 (*tx32p)[2][4]; -+ u32 (*tx16p)[2][4]; -+ u32 (*tx8p)[2][2]; -+ u32 (*y_mode)[4][10]; -+ u32 (*uv_mode)[10][10]; -+ u32 (*comp)[5][2]; -+ u32 (*comp_ref)[5][2]; -+ u32 (*single_ref)[5][2][2]; -+ u32 (*mv_mode)[7][4]; -+ u32 (*filter)[4][3]; -+ u32 (*mv_joint)[4]; -+ u32 (*sign)[2][2]; -+ u32 (*classes)[2][11]; -+ u32 (*class0)[2][2]; -+ u32 (*bits)[2][10][2]; -+ u32 (*class0_fp)[2][2][4]; -+ u32 (*fp)[2][4]; -+ u32 (*class0_hp)[2][2]; -+ u32 (*hp)[2][2]; -+ u32 (*coeff[4][2][2][6][6])[3]; -+ u32 *eob[4][2][2][6][6][2]; -+}; -+ -+extern const u8 v4l2_vp9_kf_y_mode_prob[10][10][9]; /* Section 10.4 of the spec */ -+extern const u8 v4l2_vp9_kf_partition_probs[16][3]; /* Section 10.4 of the spec */ -+extern const u8 v4l2_vp9_kf_uv_mode_prob[10][9]; /* Section 10.4 of the spec */ -+extern const struct v4l2_vp9_frame_context v4l2_vp9_default_probs; /* Section 10.5 of the spec */ -+ -+/** -+ * v4l2_vp9_fw_update_probs() - Perform forward update of vp9 probabilities -+ * -+ * @probs: current probabilities values -+ * @deltas: delta values from compressed header -+ * @dec_params: vp9 frame decoding parameters -+ * -+ * This function performs forward updates of probabilities for the vp9 boolean decoder. -+ * The frame header can contain a directive to update the probabilities (deltas), if so, then -+ * the deltas are provided in the header, too. The userspace parses those and passes the said -+ * deltas struct to the kernel. -+ */ -+void v4l2_vp9_fw_update_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas, -+ const struct v4l2_ctrl_vp9_frame *dec_params); -+ -+/** -+ * v4l2_vp9_reset_frame_ctx() - Reset appropriate frame context -+ * -+ * @dec_params: vp9 frame decoding parameters -+ * @frame_context: array of the 4 frame contexts -+ * -+ * This function resets appropriate frame contexts, based on what's in dec_params. -+ * -+ * Returns the frame context index after the update, which might be reset to zero if -+ * mandated by the spec. -+ */ -+u8 v4l2_vp9_reset_frame_ctx(const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct v4l2_vp9_frame_context *frame_context); -+ -+/** -+ * v4l2_vp9_adapt_coef_probs() - Perform backward update of vp9 coefficients probabilities -+ * -+ * @probs: current probabilities values -+ * @counts: values of symbol counts after the current frame has been decoded -+ * @use_128: flag to request that 128 is used as update factor if true, otherwise 112 is used -+ * @frame_is_intra: flag indicating that FrameIsIntra is true -+ * -+ * This function performs backward updates of coefficients probabilities for the vp9 boolean -+ * decoder. After a frame has been decoded the counts of how many times a given symbol has -+ * occurred are known and are used to update the probability of each symbol. -+ */ -+void v4l2_vp9_adapt_coef_probs(struct v4l2_vp9_frame_context *probs, -+ struct v4l2_vp9_frame_symbol_counts *counts, -+ bool use_128, -+ bool frame_is_intra); -+ -+/** -+ * v4l2_vp9_adapt_noncoef_probs() - Perform backward update of vp9 non-coefficients probabilities -+ * -+ * @probs: current probabilities values -+ * @counts: values of symbol counts after the current frame has been decoded -+ * @reference_mode: specifies the type of inter prediction to be used. See -+ * &v4l2_vp9_reference_mode for more details -+ * @interpolation_filter: specifies the filter selection used for performing inter prediction. -+ * See &v4l2_vp9_interpolation_filter for more details -+ * @tx_mode: specifies the TX mode. See &v4l2_vp9_tx_mode for more details -+ * @flags: combination of V4L2_VP9_FRAME_FLAG_* flags -+ * -+ * This function performs backward updates of non-coefficients probabilities for the vp9 boolean -+ * decoder. After a frame has been decoded the counts of how many times a given symbol has -+ * occurred are known and are used to update the probability of each symbol. -+ */ -+void v4l2_vp9_adapt_noncoef_probs(struct v4l2_vp9_frame_context *probs, -+ struct v4l2_vp9_frame_symbol_counts *counts, -+ u8 reference_mode, u8 interpolation_filter, u8 tx_mode, -+ u32 flags); -+ -+/** -+ * v4l2_vp9_seg_feat_enabled() - Check if a segmentation feature is enabled -+ * -+ * @feature_enabled: array of 8-bit flags (for all segments) -+ * @feature: id of the feature to check -+ * @segid: id of the segment to look up -+ * -+ * This function returns true if a given feature is active in a given segment. -+ */ -+bool -+v4l2_vp9_seg_feat_enabled(const u8 *feature_enabled, -+ unsigned int feature, -+ unsigned int segid); -+ -+#endif /* _MEDIA_V4L2_VP9_H */ diff --git a/projects/Allwinner/patches/linux/0073-media-rkvdec-Add-the-VP9-backend.patch b/projects/Allwinner/patches/linux/0073-media-rkvdec-Add-the-VP9-backend.patch deleted file mode 100644 index cf1bdf401d..0000000000 --- a/projects/Allwinner/patches/linux/0073-media-rkvdec-Add-the-VP9-backend.patch +++ /dev/null @@ -1,1217 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Wed, 17 Nov 2021 12:52:56 +0100 -Subject: [PATCH] media: rkvdec: Add the VP9 backend - -The Rockchip VDEC supports VP9 profile 0 up to 4096x2304@30fps. Add -a backend for this new format. - -Signed-off-by: Boris Brezillon -Signed-off-by: Ezequiel Garcia -Signed-off-by: Adrian Ratiu -Co-developed-by: Andrzej Pietrasiewicz -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/rkvdec/Kconfig | 1 + - drivers/staging/media/rkvdec/Makefile | 2 +- - drivers/staging/media/rkvdec/rkvdec-vp9.c | 1072 +++++++++++++++++++++ - drivers/staging/media/rkvdec/rkvdec.c | 41 +- - drivers/staging/media/rkvdec/rkvdec.h | 12 +- - 5 files changed, 1121 insertions(+), 7 deletions(-) - create mode 100644 drivers/staging/media/rkvdec/rkvdec-vp9.c - -diff --git a/drivers/staging/media/rkvdec/Kconfig b/drivers/staging/media/rkvdec/Kconfig -index c02199b5e0fd..dc7292f346fa 100644 ---- a/drivers/staging/media/rkvdec/Kconfig -+++ b/drivers/staging/media/rkvdec/Kconfig -@@ -9,6 +9,7 @@ config VIDEO_ROCKCHIP_VDEC - select VIDEOBUF2_VMALLOC - select V4L2_MEM2MEM_DEV - select V4L2_H264 -+ select V4L2_VP9 - help - Support for the Rockchip Video Decoder IP present on Rockchip SoCs, - which accelerates video decoding. -diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile -index c08fed0a39f9..cb86b429cfaa 100644 ---- a/drivers/staging/media/rkvdec/Makefile -+++ b/drivers/staging/media/rkvdec/Makefile -@@ -1,3 +1,3 @@ - obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o - --rockchip-vdec-y += rkvdec.o rkvdec-h264.o -+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o -diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c -new file mode 100644 -index 000000000000..311a12656072 ---- /dev/null -+++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c -@@ -0,0 +1,1072 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip Video Decoder VP9 backend -+ * -+ * Copyright (C) 2019 Collabora, Ltd. -+ * Boris Brezillon -+ * Copyright (C) 2021 Collabora, Ltd. -+ * Andrzej Pietrasiewicz -+ * -+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd. -+ * Alpha Lin -+ */ -+ -+/* -+ * For following the vp9 spec please start reading this driver -+ * code from rkvdec_vp9_run() followed by rkvdec_vp9_done(). -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "rkvdec.h" -+#include "rkvdec-regs.h" -+ -+#define RKVDEC_VP9_PROBE_SIZE 4864 -+#define RKVDEC_VP9_COUNT_SIZE 13232 -+#define RKVDEC_VP9_MAX_SEGMAP_SIZE 73728 -+ -+struct rkvdec_vp9_intra_mode_probs { -+ u8 y_mode[105]; -+ u8 uv_mode[23]; -+}; -+ -+struct rkvdec_vp9_intra_only_frame_probs { -+ u8 coef_intra[4][2][128]; -+ struct rkvdec_vp9_intra_mode_probs intra_mode[10]; -+}; -+ -+struct rkvdec_vp9_inter_frame_probs { -+ u8 y_mode[4][9]; -+ u8 comp_mode[5]; -+ u8 comp_ref[5]; -+ u8 single_ref[5][2]; -+ u8 inter_mode[7][3]; -+ u8 interp_filter[4][2]; -+ u8 padding0[11]; -+ u8 coef[2][4][2][128]; -+ u8 uv_mode_0_2[3][9]; -+ u8 padding1[5]; -+ u8 uv_mode_3_5[3][9]; -+ u8 padding2[5]; -+ u8 uv_mode_6_8[3][9]; -+ u8 padding3[5]; -+ u8 uv_mode_9[9]; -+ u8 padding4[7]; -+ u8 padding5[16]; -+ struct { -+ u8 joint[3]; -+ u8 sign[2]; -+ u8 classes[2][10]; -+ u8 class0_bit[2]; -+ u8 bits[2][10]; -+ u8 class0_fr[2][2][3]; -+ u8 fr[2][3]; -+ u8 class0_hp[2]; -+ u8 hp[2]; -+ } mv; -+}; -+ -+struct rkvdec_vp9_probs { -+ u8 partition[16][3]; -+ u8 pred[3]; -+ u8 tree[7]; -+ u8 skip[3]; -+ u8 tx32[2][3]; -+ u8 tx16[2][2]; -+ u8 tx8[2][1]; -+ u8 is_inter[4]; -+ /* 128 bit alignment */ -+ u8 padding0[3]; -+ union { -+ struct rkvdec_vp9_inter_frame_probs inter; -+ struct rkvdec_vp9_intra_only_frame_probs intra_only; -+ }; -+}; -+ -+/* Data structure describing auxiliary buffer format. */ -+struct rkvdec_vp9_priv_tbl { -+ struct rkvdec_vp9_probs probs; -+ u8 segmap[2][RKVDEC_VP9_MAX_SEGMAP_SIZE]; -+}; -+ -+struct rkvdec_vp9_refs_counts { -+ u32 eob[2]; -+ u32 coeff[3]; -+}; -+ -+struct rkvdec_vp9_inter_frame_symbol_counts { -+ u32 partition[16][4]; -+ u32 skip[3][2]; -+ u32 inter[4][2]; -+ u32 tx32p[2][4]; -+ u32 tx16p[2][4]; -+ u32 tx8p[2][2]; -+ u32 y_mode[4][10]; -+ u32 uv_mode[10][10]; -+ u32 comp[5][2]; -+ u32 comp_ref[5][2]; -+ u32 single_ref[5][2][2]; -+ u32 mv_mode[7][4]; -+ u32 filter[4][3]; -+ u32 mv_joint[4]; -+ u32 sign[2][2]; -+ /* add 1 element for align */ -+ u32 classes[2][11 + 1]; -+ u32 class0[2][2]; -+ u32 bits[2][10][2]; -+ u32 class0_fp[2][2][4]; -+ u32 fp[2][4]; -+ u32 class0_hp[2][2]; -+ u32 hp[2][2]; -+ struct rkvdec_vp9_refs_counts ref_cnt[2][4][2][6][6]; -+}; -+ -+struct rkvdec_vp9_intra_frame_symbol_counts { -+ u32 partition[4][4][4]; -+ u32 skip[3][2]; -+ u32 intra[4][2]; -+ u32 tx32p[2][4]; -+ u32 tx16p[2][4]; -+ u32 tx8p[2][2]; -+ struct rkvdec_vp9_refs_counts ref_cnt[2][4][2][6][6]; -+}; -+ -+struct rkvdec_vp9_run { -+ struct rkvdec_run base; -+ const struct v4l2_ctrl_vp9_frame *decode_params; -+}; -+ -+struct rkvdec_vp9_frame_info { -+ u32 valid : 1; -+ u32 segmapid : 1; -+ u32 frame_context_idx : 2; -+ u32 reference_mode : 2; -+ u32 tx_mode : 3; -+ u32 interpolation_filter : 3; -+ u32 flags; -+ u64 timestamp; -+ struct v4l2_vp9_segmentation seg; -+ struct v4l2_vp9_loop_filter lf; -+}; -+ -+struct rkvdec_vp9_ctx { -+ struct rkvdec_aux_buf priv_tbl; -+ struct rkvdec_aux_buf count_tbl; -+ struct v4l2_vp9_frame_symbol_counts inter_cnts; -+ struct v4l2_vp9_frame_symbol_counts intra_cnts; -+ struct v4l2_vp9_frame_context probability_tables; -+ struct v4l2_vp9_frame_context frame_context[4]; -+ struct rkvdec_vp9_frame_info cur; -+ struct rkvdec_vp9_frame_info last; -+}; -+ -+static void write_coeff_plane(const u8 coef[6][6][3], u8 *coeff_plane) -+{ -+ unsigned int idx = 0, byte_count = 0; -+ int k, m, n; -+ u8 p; -+ -+ for (k = 0; k < 6; k++) { -+ for (m = 0; m < 6; m++) { -+ for (n = 0; n < 3; n++) { -+ p = coef[k][m][n]; -+ coeff_plane[idx++] = p; -+ byte_count++; -+ if (byte_count == 27) { -+ idx += 5; -+ byte_count = 0; -+ } -+ } -+ } -+ } -+} -+ -+static void init_intra_only_probs(struct rkvdec_ctx *ctx, -+ const struct rkvdec_vp9_run *run) -+{ -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ struct rkvdec_vp9_priv_tbl *tbl = vp9_ctx->priv_tbl.cpu; -+ struct rkvdec_vp9_intra_only_frame_probs *rkprobs; -+ const struct v4l2_vp9_frame_context *probs; -+ unsigned int i, j, k; -+ -+ rkprobs = &tbl->probs.intra_only; -+ probs = &vp9_ctx->probability_tables; -+ -+ /* -+ * intra only 149 x 128 bits ,aligned to 152 x 128 bits coeff related -+ * prob 64 x 128 bits -+ */ -+ for (i = 0; i < ARRAY_SIZE(probs->coef); i++) { -+ for (j = 0; j < ARRAY_SIZE(probs->coef[0]); j++) -+ write_coeff_plane(probs->coef[i][j][0], -+ rkprobs->coef_intra[i][j]); -+ } -+ -+ /* intra mode prob 80 x 128 bits */ -+ for (i = 0; i < ARRAY_SIZE(v4l2_vp9_kf_y_mode_prob); i++) { -+ unsigned int byte_count = 0; -+ int idx = 0; -+ -+ /* vp9_kf_y_mode_prob */ -+ for (j = 0; j < ARRAY_SIZE(v4l2_vp9_kf_y_mode_prob[0]); j++) { -+ for (k = 0; k < ARRAY_SIZE(v4l2_vp9_kf_y_mode_prob[0][0]); -+ k++) { -+ u8 val = v4l2_vp9_kf_y_mode_prob[i][j][k]; -+ -+ rkprobs->intra_mode[i].y_mode[idx++] = val; -+ byte_count++; -+ if (byte_count == 27) { -+ byte_count = 0; -+ idx += 5; -+ } -+ } -+ } -+ -+ } -+ -+ for (i = 0; i < sizeof(v4l2_vp9_kf_uv_mode_prob); ++i) { -+ const u8 *ptr = (const u8 *)v4l2_vp9_kf_uv_mode_prob; -+ -+ rkprobs->intra_mode[i / 23].uv_mode[i % 23] = ptr[i]; -+ } -+} -+ -+static void init_inter_probs(struct rkvdec_ctx *ctx, -+ const struct rkvdec_vp9_run *run) -+{ -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ struct rkvdec_vp9_priv_tbl *tbl = vp9_ctx->priv_tbl.cpu; -+ struct rkvdec_vp9_inter_frame_probs *rkprobs; -+ const struct v4l2_vp9_frame_context *probs; -+ unsigned int i, j, k; -+ -+ rkprobs = &tbl->probs.inter; -+ probs = &vp9_ctx->probability_tables; -+ -+ /* -+ * inter probs -+ * 151 x 128 bits, aligned to 152 x 128 bits -+ * inter only -+ * intra_y_mode & inter_block info 6 x 128 bits -+ */ -+ -+ memcpy(rkprobs->y_mode, probs->y_mode, sizeof(rkprobs->y_mode)); -+ memcpy(rkprobs->comp_mode, probs->comp_mode, -+ sizeof(rkprobs->comp_mode)); -+ memcpy(rkprobs->comp_ref, probs->comp_ref, -+ sizeof(rkprobs->comp_ref)); -+ memcpy(rkprobs->single_ref, probs->single_ref, -+ sizeof(rkprobs->single_ref)); -+ memcpy(rkprobs->inter_mode, probs->inter_mode, -+ sizeof(rkprobs->inter_mode)); -+ memcpy(rkprobs->interp_filter, probs->interp_filter, -+ sizeof(rkprobs->interp_filter)); -+ -+ /* 128 x 128 bits coeff related */ -+ for (i = 0; i < ARRAY_SIZE(probs->coef); i++) { -+ for (j = 0; j < ARRAY_SIZE(probs->coef[0]); j++) { -+ for (k = 0; k < ARRAY_SIZE(probs->coef[0][0]); k++) -+ write_coeff_plane(probs->coef[i][j][k], -+ rkprobs->coef[k][i][j]); -+ } -+ } -+ -+ /* intra uv mode 6 x 128 */ -+ memcpy(rkprobs->uv_mode_0_2, &probs->uv_mode[0], -+ sizeof(rkprobs->uv_mode_0_2)); -+ memcpy(rkprobs->uv_mode_3_5, &probs->uv_mode[3], -+ sizeof(rkprobs->uv_mode_3_5)); -+ memcpy(rkprobs->uv_mode_6_8, &probs->uv_mode[6], -+ sizeof(rkprobs->uv_mode_6_8)); -+ memcpy(rkprobs->uv_mode_9, &probs->uv_mode[9], -+ sizeof(rkprobs->uv_mode_9)); -+ -+ /* mv related 6 x 128 */ -+ memcpy(rkprobs->mv.joint, probs->mv.joint, -+ sizeof(rkprobs->mv.joint)); -+ memcpy(rkprobs->mv.sign, probs->mv.sign, -+ sizeof(rkprobs->mv.sign)); -+ memcpy(rkprobs->mv.classes, probs->mv.classes, -+ sizeof(rkprobs->mv.classes)); -+ memcpy(rkprobs->mv.class0_bit, probs->mv.class0_bit, -+ sizeof(rkprobs->mv.class0_bit)); -+ memcpy(rkprobs->mv.bits, probs->mv.bits, -+ sizeof(rkprobs->mv.bits)); -+ memcpy(rkprobs->mv.class0_fr, probs->mv.class0_fr, -+ sizeof(rkprobs->mv.class0_fr)); -+ memcpy(rkprobs->mv.fr, probs->mv.fr, -+ sizeof(rkprobs->mv.fr)); -+ memcpy(rkprobs->mv.class0_hp, probs->mv.class0_hp, -+ sizeof(rkprobs->mv.class0_hp)); -+ memcpy(rkprobs->mv.hp, probs->mv.hp, -+ sizeof(rkprobs->mv.hp)); -+} -+ -+static void init_probs(struct rkvdec_ctx *ctx, -+ const struct rkvdec_vp9_run *run) -+{ -+ const struct v4l2_ctrl_vp9_frame *dec_params; -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ struct rkvdec_vp9_priv_tbl *tbl = vp9_ctx->priv_tbl.cpu; -+ struct rkvdec_vp9_probs *rkprobs = &tbl->probs; -+ const struct v4l2_vp9_segmentation *seg; -+ const struct v4l2_vp9_frame_context *probs; -+ bool intra_only; -+ -+ dec_params = run->decode_params; -+ probs = &vp9_ctx->probability_tables; -+ seg = &dec_params->seg; -+ -+ memset(rkprobs, 0, sizeof(*rkprobs)); -+ -+ intra_only = !!(dec_params->flags & -+ (V4L2_VP9_FRAME_FLAG_KEY_FRAME | -+ V4L2_VP9_FRAME_FLAG_INTRA_ONLY)); -+ -+ /* sb info 5 x 128 bit */ -+ memcpy(rkprobs->partition, -+ intra_only ? v4l2_vp9_kf_partition_probs : probs->partition, -+ sizeof(rkprobs->partition)); -+ -+ memcpy(rkprobs->pred, seg->pred_probs, sizeof(rkprobs->pred)); -+ memcpy(rkprobs->tree, seg->tree_probs, sizeof(rkprobs->tree)); -+ memcpy(rkprobs->skip, probs->skip, sizeof(rkprobs->skip)); -+ memcpy(rkprobs->tx32, probs->tx32, sizeof(rkprobs->tx32)); -+ memcpy(rkprobs->tx16, probs->tx16, sizeof(rkprobs->tx16)); -+ memcpy(rkprobs->tx8, probs->tx8, sizeof(rkprobs->tx8)); -+ memcpy(rkprobs->is_inter, probs->is_inter, sizeof(rkprobs->is_inter)); -+ -+ if (intra_only) -+ init_intra_only_probs(ctx, run); -+ else -+ init_inter_probs(ctx, run); -+} -+ -+struct rkvdec_vp9_ref_reg { -+ u32 reg_frm_size; -+ u32 reg_hor_stride; -+ u32 reg_y_stride; -+ u32 reg_yuv_stride; -+ u32 reg_ref_base; -+}; -+ -+static struct rkvdec_vp9_ref_reg ref_regs[] = { -+ { -+ .reg_frm_size = RKVDEC_REG_VP9_FRAME_SIZE(0), -+ .reg_hor_stride = RKVDEC_VP9_HOR_VIRSTRIDE(0), -+ .reg_y_stride = RKVDEC_VP9_LAST_FRAME_YSTRIDE, -+ .reg_yuv_stride = RKVDEC_VP9_LAST_FRAME_YUVSTRIDE, -+ .reg_ref_base = RKVDEC_REG_VP9_LAST_FRAME_BASE, -+ }, -+ { -+ .reg_frm_size = RKVDEC_REG_VP9_FRAME_SIZE(1), -+ .reg_hor_stride = RKVDEC_VP9_HOR_VIRSTRIDE(1), -+ .reg_y_stride = RKVDEC_VP9_GOLDEN_FRAME_YSTRIDE, -+ .reg_yuv_stride = 0, -+ .reg_ref_base = RKVDEC_REG_VP9_GOLDEN_FRAME_BASE, -+ }, -+ { -+ .reg_frm_size = RKVDEC_REG_VP9_FRAME_SIZE(2), -+ .reg_hor_stride = RKVDEC_VP9_HOR_VIRSTRIDE(2), -+ .reg_y_stride = RKVDEC_VP9_ALTREF_FRAME_YSTRIDE, -+ .reg_yuv_stride = 0, -+ .reg_ref_base = RKVDEC_REG_VP9_ALTREF_FRAME_BASE, -+ } -+}; -+ -+static struct rkvdec_decoded_buffer * -+get_ref_buf(struct rkvdec_ctx *ctx, struct vb2_v4l2_buffer *dst, u64 timestamp) -+{ -+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -+ int buf_idx; -+ -+ /* -+ * If a ref is unused or invalid, address of current destination -+ * buffer is returned. -+ */ -+ buf_idx = vb2_find_timestamp(cap_q, timestamp, 0); -+ if (buf_idx < 0) -+ return vb2_to_rkvdec_decoded_buf(&dst->vb2_buf); -+ -+ return vb2_to_rkvdec_decoded_buf(vb2_get_buffer(cap_q, buf_idx)); -+} -+ -+static dma_addr_t get_mv_base_addr(struct rkvdec_decoded_buffer *buf) -+{ -+ unsigned int aligned_pitch, aligned_height, yuv_len; -+ -+ aligned_height = round_up(buf->vp9.height, 64); -+ aligned_pitch = round_up(buf->vp9.width * buf->vp9.bit_depth, 512) / 8; -+ yuv_len = (aligned_height * aligned_pitch * 3) / 2; -+ -+ return vb2_dma_contig_plane_dma_addr(&buf->base.vb.vb2_buf, 0) + -+ yuv_len; -+} -+ -+static void config_ref_registers(struct rkvdec_ctx *ctx, -+ const struct rkvdec_vp9_run *run, -+ struct rkvdec_decoded_buffer *ref_buf, -+ struct rkvdec_vp9_ref_reg *ref_reg) -+{ -+ unsigned int aligned_pitch, aligned_height, y_len, yuv_len; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ -+ aligned_height = round_up(ref_buf->vp9.height, 64); -+ writel_relaxed(RKVDEC_VP9_FRAMEWIDTH(ref_buf->vp9.width) | -+ RKVDEC_VP9_FRAMEHEIGHT(ref_buf->vp9.height), -+ rkvdec->regs + ref_reg->reg_frm_size); -+ -+ writel_relaxed(vb2_dma_contig_plane_dma_addr(&ref_buf->base.vb.vb2_buf, 0), -+ rkvdec->regs + ref_reg->reg_ref_base); -+ -+ if (&ref_buf->base.vb == run->base.bufs.dst) -+ return; -+ -+ aligned_pitch = round_up(ref_buf->vp9.width * ref_buf->vp9.bit_depth, 512) / 8; -+ y_len = aligned_height * aligned_pitch; -+ yuv_len = (y_len * 3) / 2; -+ -+ writel_relaxed(RKVDEC_HOR_Y_VIRSTRIDE(aligned_pitch / 16) | -+ RKVDEC_HOR_UV_VIRSTRIDE(aligned_pitch / 16), -+ rkvdec->regs + ref_reg->reg_hor_stride); -+ writel_relaxed(RKVDEC_VP9_REF_YSTRIDE(y_len / 16), -+ rkvdec->regs + ref_reg->reg_y_stride); -+ -+ if (!ref_reg->reg_yuv_stride) -+ return; -+ -+ writel_relaxed(RKVDEC_VP9_REF_YUVSTRIDE(yuv_len / 16), -+ rkvdec->regs + ref_reg->reg_yuv_stride); -+} -+ -+static void config_seg_registers(struct rkvdec_ctx *ctx, unsigned int segid) -+{ -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ const struct v4l2_vp9_segmentation *seg; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ s16 feature_val; -+ int feature_id; -+ u32 val = 0; -+ -+ seg = vp9_ctx->last.valid ? &vp9_ctx->last.seg : &vp9_ctx->cur.seg; -+ feature_id = V4L2_VP9_SEG_LVL_ALT_Q; -+ if (v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid)) { -+ feature_val = seg->feature_data[segid][feature_id]; -+ val |= RKVDEC_SEGID_FRAME_QP_DELTA_EN(1) | -+ RKVDEC_SEGID_FRAME_QP_DELTA(feature_val); -+ } -+ -+ feature_id = V4L2_VP9_SEG_LVL_ALT_L; -+ if (v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid)) { -+ feature_val = seg->feature_data[segid][feature_id]; -+ val |= RKVDEC_SEGID_FRAME_LOOPFILTER_VALUE_EN(1) | -+ RKVDEC_SEGID_FRAME_LOOPFILTER_VALUE(feature_val); -+ } -+ -+ feature_id = V4L2_VP9_SEG_LVL_REF_FRAME; -+ if (v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid)) { -+ feature_val = seg->feature_data[segid][feature_id]; -+ val |= RKVDEC_SEGID_REFERINFO_EN(1) | -+ RKVDEC_SEGID_REFERINFO(feature_val); -+ } -+ -+ feature_id = V4L2_VP9_SEG_LVL_SKIP; -+ if (v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid)) -+ val |= RKVDEC_SEGID_FRAME_SKIP_EN(1); -+ -+ if (!segid && -+ (seg->flags & V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE)) -+ val |= RKVDEC_SEGID_ABS_DELTA(1); -+ -+ writel_relaxed(val, rkvdec->regs + RKVDEC_VP9_SEGID_GRP(segid)); -+} -+ -+static void update_dec_buf_info(struct rkvdec_decoded_buffer *buf, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ buf->vp9.width = dec_params->frame_width_minus_1 + 1; -+ buf->vp9.height = dec_params->frame_height_minus_1 + 1; -+ buf->vp9.bit_depth = dec_params->bit_depth; -+} -+ -+static void update_ctx_cur_info(struct rkvdec_vp9_ctx *vp9_ctx, -+ struct rkvdec_decoded_buffer *buf, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ vp9_ctx->cur.valid = true; -+ vp9_ctx->cur.reference_mode = dec_params->reference_mode; -+ vp9_ctx->cur.interpolation_filter = dec_params->interpolation_filter; -+ vp9_ctx->cur.flags = dec_params->flags; -+ vp9_ctx->cur.timestamp = buf->base.vb.vb2_buf.timestamp; -+ vp9_ctx->cur.seg = dec_params->seg; -+ vp9_ctx->cur.lf = dec_params->lf; -+} -+ -+static void update_ctx_last_info(struct rkvdec_vp9_ctx *vp9_ctx) -+{ -+ vp9_ctx->last = vp9_ctx->cur; -+} -+ -+static void config_registers(struct rkvdec_ctx *ctx, -+ const struct rkvdec_vp9_run *run) -+{ -+ unsigned int y_len, uv_len, yuv_len, bit_depth, aligned_height, aligned_pitch, stream_len; -+ const struct v4l2_ctrl_vp9_frame *dec_params; -+ struct rkvdec_decoded_buffer *ref_bufs[3]; -+ struct rkvdec_decoded_buffer *dst, *last, *mv_ref; -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ u32 val, last_frame_info = 0; -+ const struct v4l2_vp9_segmentation *seg; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ dma_addr_t addr; -+ bool intra_only; -+ unsigned int i; -+ -+ dec_params = run->decode_params; -+ dst = vb2_to_rkvdec_decoded_buf(&run->base.bufs.dst->vb2_buf); -+ ref_bufs[0] = get_ref_buf(ctx, &dst->base.vb, dec_params->last_frame_ts); -+ ref_bufs[1] = get_ref_buf(ctx, &dst->base.vb, dec_params->golden_frame_ts); -+ ref_bufs[2] = get_ref_buf(ctx, &dst->base.vb, dec_params->alt_frame_ts); -+ -+ if (vp9_ctx->last.valid) -+ last = get_ref_buf(ctx, &dst->base.vb, vp9_ctx->last.timestamp); -+ else -+ last = dst; -+ -+ update_dec_buf_info(dst, dec_params); -+ update_ctx_cur_info(vp9_ctx, dst, dec_params); -+ seg = &dec_params->seg; -+ -+ intra_only = !!(dec_params->flags & -+ (V4L2_VP9_FRAME_FLAG_KEY_FRAME | -+ V4L2_VP9_FRAME_FLAG_INTRA_ONLY)); -+ -+ writel_relaxed(RKVDEC_MODE(RKVDEC_MODE_VP9), -+ rkvdec->regs + RKVDEC_REG_SYSCTRL); -+ -+ bit_depth = dec_params->bit_depth; -+ aligned_height = round_up(ctx->decoded_fmt.fmt.pix_mp.height, 64); -+ -+ aligned_pitch = round_up(ctx->decoded_fmt.fmt.pix_mp.width * -+ bit_depth, -+ 512) / 8; -+ y_len = aligned_height * aligned_pitch; -+ uv_len = y_len / 2; -+ yuv_len = y_len + uv_len; -+ -+ writel_relaxed(RKVDEC_Y_HOR_VIRSTRIDE(aligned_pitch / 16) | -+ RKVDEC_UV_HOR_VIRSTRIDE(aligned_pitch / 16), -+ rkvdec->regs + RKVDEC_REG_PICPAR); -+ writel_relaxed(RKVDEC_Y_VIRSTRIDE(y_len / 16), -+ rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE); -+ writel_relaxed(RKVDEC_YUV_VIRSTRIDE(yuv_len / 16), -+ rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE); -+ -+ stream_len = vb2_get_plane_payload(&run->base.bufs.src->vb2_buf, 0); -+ writel_relaxed(RKVDEC_STRM_LEN(stream_len), -+ rkvdec->regs + RKVDEC_REG_STRM_LEN); -+ -+ /* -+ * Reset count buffer, because decoder only output intra related syntax -+ * counts when decoding intra frame, but update entropy need to update -+ * all the probabilities. -+ */ -+ if (intra_only) -+ memset(vp9_ctx->count_tbl.cpu, 0, vp9_ctx->count_tbl.size); -+ -+ vp9_ctx->cur.segmapid = vp9_ctx->last.segmapid; -+ if (!intra_only && -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) && -+ (!(seg->flags & V4L2_VP9_SEGMENTATION_FLAG_ENABLED) || -+ (seg->flags & V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP))) -+ vp9_ctx->cur.segmapid++; -+ -+ for (i = 0; i < ARRAY_SIZE(ref_bufs); i++) -+ config_ref_registers(ctx, run, ref_bufs[i], &ref_regs[i]); -+ -+ for (i = 0; i < 8; i++) -+ config_seg_registers(ctx, i); -+ -+ writel_relaxed(RKVDEC_VP9_TX_MODE(vp9_ctx->cur.tx_mode) | -+ RKVDEC_VP9_FRAME_REF_MODE(dec_params->reference_mode), -+ rkvdec->regs + RKVDEC_VP9_CPRHEADER_CONFIG); -+ -+ if (!intra_only) { -+ const struct v4l2_vp9_loop_filter *lf; -+ s8 delta; -+ -+ if (vp9_ctx->last.valid) -+ lf = &vp9_ctx->last.lf; -+ else -+ lf = &vp9_ctx->cur.lf; -+ -+ val = 0; -+ for (i = 0; i < ARRAY_SIZE(lf->ref_deltas); i++) { -+ delta = lf->ref_deltas[i]; -+ val |= RKVDEC_REF_DELTAS_LASTFRAME(i, delta); -+ } -+ -+ writel_relaxed(val, -+ rkvdec->regs + RKVDEC_VP9_REF_DELTAS_LASTFRAME); -+ -+ for (i = 0; i < ARRAY_SIZE(lf->mode_deltas); i++) { -+ delta = lf->mode_deltas[i]; -+ last_frame_info |= RKVDEC_MODE_DELTAS_LASTFRAME(i, -+ delta); -+ } -+ } -+ -+ if (vp9_ctx->last.valid && !intra_only && -+ vp9_ctx->last.seg.flags & V4L2_VP9_SEGMENTATION_FLAG_ENABLED) -+ last_frame_info |= RKVDEC_SEG_EN_LASTFRAME; -+ -+ if (vp9_ctx->last.valid && -+ vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_SHOW_FRAME) -+ last_frame_info |= RKVDEC_LAST_SHOW_FRAME; -+ -+ if (vp9_ctx->last.valid && -+ vp9_ctx->last.flags & -+ (V4L2_VP9_FRAME_FLAG_KEY_FRAME | V4L2_VP9_FRAME_FLAG_INTRA_ONLY)) -+ last_frame_info |= RKVDEC_LAST_INTRA_ONLY; -+ -+ if (vp9_ctx->last.valid && -+ last->vp9.width == dst->vp9.width && -+ last->vp9.height == dst->vp9.height) -+ last_frame_info |= RKVDEC_LAST_WIDHHEIGHT_EQCUR; -+ -+ writel_relaxed(last_frame_info, -+ rkvdec->regs + RKVDEC_VP9_INFO_LASTFRAME); -+ -+ writel_relaxed(stream_len - dec_params->compressed_header_size - -+ dec_params->uncompressed_header_size, -+ rkvdec->regs + RKVDEC_VP9_LASTTILE_SIZE); -+ -+ for (i = 0; !intra_only && i < ARRAY_SIZE(ref_bufs); i++) { -+ unsigned int refw = ref_bufs[i]->vp9.width; -+ unsigned int refh = ref_bufs[i]->vp9.height; -+ u32 hscale, vscale; -+ -+ hscale = (refw << 14) / dst->vp9.width; -+ vscale = (refh << 14) / dst->vp9.height; -+ writel_relaxed(RKVDEC_VP9_REF_HOR_SCALE(hscale) | -+ RKVDEC_VP9_REF_VER_SCALE(vscale), -+ rkvdec->regs + RKVDEC_VP9_REF_SCALE(i)); -+ } -+ -+ addr = vb2_dma_contig_plane_dma_addr(&dst->base.vb.vb2_buf, 0); -+ writel_relaxed(addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE); -+ addr = vb2_dma_contig_plane_dma_addr(&run->base.bufs.src->vb2_buf, 0); -+ writel_relaxed(addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); -+ writel_relaxed(vp9_ctx->priv_tbl.dma + -+ offsetof(struct rkvdec_vp9_priv_tbl, probs), -+ rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE); -+ writel_relaxed(vp9_ctx->count_tbl.dma, -+ rkvdec->regs + RKVDEC_REG_VP9COUNT_BASE); -+ -+ writel_relaxed(vp9_ctx->priv_tbl.dma + -+ offsetof(struct rkvdec_vp9_priv_tbl, segmap) + -+ (RKVDEC_VP9_MAX_SEGMAP_SIZE * vp9_ctx->cur.segmapid), -+ rkvdec->regs + RKVDEC_REG_VP9_SEGIDCUR_BASE); -+ writel_relaxed(vp9_ctx->priv_tbl.dma + -+ offsetof(struct rkvdec_vp9_priv_tbl, segmap) + -+ (RKVDEC_VP9_MAX_SEGMAP_SIZE * (!vp9_ctx->cur.segmapid)), -+ rkvdec->regs + RKVDEC_REG_VP9_SEGIDLAST_BASE); -+ -+ if (!intra_only && -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) && -+ vp9_ctx->last.valid) -+ mv_ref = last; -+ else -+ mv_ref = dst; -+ -+ writel_relaxed(get_mv_base_addr(mv_ref), -+ rkvdec->regs + RKVDEC_VP9_REF_COLMV_BASE); -+ -+ writel_relaxed(ctx->decoded_fmt.fmt.pix_mp.width | -+ (ctx->decoded_fmt.fmt.pix_mp.height << 16), -+ rkvdec->regs + RKVDEC_REG_PERFORMANCE_CYCLE); -+} -+ -+static int validate_dec_params(struct rkvdec_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ unsigned int aligned_width, aligned_height; -+ -+ /* We only support profile 0. */ -+ if (dec_params->profile != 0) { -+ dev_err(ctx->dev->dev, "unsupported profile %d\n", -+ dec_params->profile); -+ return -EINVAL; -+ } -+ -+ aligned_width = round_up(dec_params->frame_width_minus_1 + 1, 64); -+ aligned_height = round_up(dec_params->frame_height_minus_1 + 1, 64); -+ -+ /* -+ * Userspace should update the capture/decoded format when the -+ * resolution changes. -+ */ -+ if (aligned_width != ctx->decoded_fmt.fmt.pix_mp.width || -+ aligned_height != ctx->decoded_fmt.fmt.pix_mp.height) { -+ dev_err(ctx->dev->dev, -+ "unexpected bitstream resolution %dx%d\n", -+ dec_params->frame_width_minus_1 + 1, -+ dec_params->frame_height_minus_1 + 1); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int rkvdec_vp9_run_preamble(struct rkvdec_ctx *ctx, -+ struct rkvdec_vp9_run *run) -+{ -+ const struct v4l2_ctrl_vp9_frame *dec_params; -+ const struct v4l2_ctrl_vp9_compressed_hdr *prob_updates; -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ struct v4l2_ctrl *ctrl; -+ unsigned int fctx_idx; -+ int ret; -+ -+ /* v4l2-specific stuff */ -+ rkvdec_run_preamble(ctx, &run->base); -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_VP9_FRAME); -+ if (WARN_ON(!ctrl)) -+ return -EINVAL; -+ dec_params = ctrl->p_cur.p; -+ -+ ret = validate_dec_params(ctx, dec_params); -+ if (ret) -+ return ret; -+ -+ run->decode_params = dec_params; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_VP9_COMPRESSED_HDR); -+ if (WARN_ON(!ctrl)) -+ return -EINVAL; -+ prob_updates = ctrl->p_cur.p; -+ vp9_ctx->cur.tx_mode = prob_updates->tx_mode; -+ -+ /* -+ * vp9 stuff -+ * -+ * by this point the userspace has done all parts of 6.2 uncompressed_header() -+ * except this fragment: -+ * if ( FrameIsIntra || error_resilient_mode ) { -+ * setup_past_independence ( ) -+ * if ( frame_type == KEY_FRAME || error_resilient_mode == 1 || -+ * reset_frame_context == 3 ) { -+ * for ( i = 0; i < 4; i ++ ) { -+ * save_probs( i ) -+ * } -+ * } else if ( reset_frame_context == 2 ) { -+ * save_probs( frame_context_idx ) -+ * } -+ * frame_context_idx = 0 -+ * } -+ */ -+ fctx_idx = v4l2_vp9_reset_frame_ctx(dec_params, vp9_ctx->frame_context); -+ vp9_ctx->cur.frame_context_idx = fctx_idx; -+ -+ /* 6.1 frame(sz): load_probs() and load_probs2() */ -+ vp9_ctx->probability_tables = vp9_ctx->frame_context[fctx_idx]; -+ -+ /* -+ * The userspace has also performed 6.3 compressed_header(), but handling the -+ * probs in a special way. All probs which need updating, except MV-related, -+ * have been read from the bitstream and translated through inv_map_table[], -+ * but no 6.3.6 inv_recenter_nonneg(v, m) has been performed. The values passed -+ * by userspace are either translated values (there are no 0 values in -+ * inv_map_table[]), or zero to indicate no update. All MV-related probs which need -+ * updating have been read from the bitstream and (mv_prob << 1) | 1 has been -+ * performed. The values passed by userspace are either new values -+ * to replace old ones (the above mentioned shift and bitwise or never result in -+ * a zero) or zero to indicate no update. -+ * fw_update_probs() performs actual probs updates or leaves probs as-is -+ * for values for which a zero was passed from userspace. -+ */ -+ v4l2_vp9_fw_update_probs(&vp9_ctx->probability_tables, prob_updates, dec_params); -+ -+ return 0; -+} -+ -+static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_vp9_run run = { }; -+ int ret; -+ -+ ret = rkvdec_vp9_run_preamble(ctx, &run); -+ if (ret) { -+ rkvdec_run_postamble(ctx, &run.base); -+ return ret; -+ } -+ -+ /* Prepare probs. */ -+ init_probs(ctx, &run); -+ -+ /* Configure hardware registers. */ -+ config_registers(ctx, &run); -+ -+ rkvdec_run_postamble(ctx, &run.base); -+ -+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); -+ -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); -+ -+ writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -+ /* Start decoding! */ -+ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | -+ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ -+ return 0; -+} -+ -+#define copy_tx_and_skip(p1, p2) \ -+do { \ -+ memcpy((p1)->tx8, (p2)->tx8, sizeof((p1)->tx8)); \ -+ memcpy((p1)->tx16, (p2)->tx16, sizeof((p1)->tx16)); \ -+ memcpy((p1)->tx32, (p2)->tx32, sizeof((p1)->tx32)); \ -+ memcpy((p1)->skip, (p2)->skip, sizeof((p1)->skip)); \ -+} while (0) -+ -+static void rkvdec_vp9_done(struct rkvdec_ctx *ctx, -+ struct vb2_v4l2_buffer *src_buf, -+ struct vb2_v4l2_buffer *dst_buf, -+ enum vb2_buffer_state result) -+{ -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ unsigned int fctx_idx; -+ -+ /* v4l2-specific stuff */ -+ if (result == VB2_BUF_STATE_ERROR) -+ goto out_update_last; -+ -+ /* -+ * vp9 stuff -+ * -+ * 6.1.2 refresh_probs() -+ * -+ * In the spec a complementary condition goes last in 6.1.2 refresh_probs(), -+ * but it makes no sense to perform all the activities from the first "if" -+ * there if we actually are not refreshing the frame context. On top of that, -+ * because of 6.2 uncompressed_header() whenever error_resilient_mode == 1, -+ * refresh_frame_context == 0. Consequently, if we don't jump to out_update_last -+ * it means error_resilient_mode must be 0. -+ */ -+ if (!(vp9_ctx->cur.flags & V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX)) -+ goto out_update_last; -+ -+ fctx_idx = vp9_ctx->cur.frame_context_idx; -+ -+ if (!(vp9_ctx->cur.flags & V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE)) { -+ /* error_resilient_mode == 0 && frame_parallel_decoding_mode == 0 */ -+ struct v4l2_vp9_frame_context *probs = &vp9_ctx->probability_tables; -+ bool frame_is_intra = vp9_ctx->cur.flags & -+ (V4L2_VP9_FRAME_FLAG_KEY_FRAME | V4L2_VP9_FRAME_FLAG_INTRA_ONLY); -+ struct tx_and_skip { -+ u8 tx8[2][1]; -+ u8 tx16[2][2]; -+ u8 tx32[2][3]; -+ u8 skip[3]; -+ } _tx_skip, *tx_skip = &_tx_skip; -+ struct v4l2_vp9_frame_symbol_counts *counts; -+ -+ /* buffer the forward-updated TX and skip probs */ -+ if (frame_is_intra) -+ copy_tx_and_skip(tx_skip, probs); -+ -+ /* 6.1.2 refresh_probs(): load_probs() and load_probs2() */ -+ *probs = vp9_ctx->frame_context[fctx_idx]; -+ -+ /* if FrameIsIntra then undo the effect of load_probs2() */ -+ if (frame_is_intra) -+ copy_tx_and_skip(probs, tx_skip); -+ -+ counts = frame_is_intra ? &vp9_ctx->intra_cnts : &vp9_ctx->inter_cnts; -+ v4l2_vp9_adapt_coef_probs(probs, counts, -+ !vp9_ctx->last.valid || -+ vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME, -+ frame_is_intra); -+ if (!frame_is_intra) { -+ const struct rkvdec_vp9_inter_frame_symbol_counts *inter_cnts; -+ u32 classes[2][11]; -+ int i; -+ -+ inter_cnts = vp9_ctx->count_tbl.cpu; -+ for (i = 0; i < ARRAY_SIZE(classes); ++i) -+ memcpy(classes[i], inter_cnts->classes[i], sizeof(classes[0])); -+ counts->classes = &classes; -+ -+ /* load_probs2() already done */ -+ v4l2_vp9_adapt_noncoef_probs(&vp9_ctx->probability_tables, counts, -+ vp9_ctx->cur.reference_mode, -+ vp9_ctx->cur.interpolation_filter, -+ vp9_ctx->cur.tx_mode, vp9_ctx->cur.flags); -+ } -+ } -+ -+ /* 6.1.2 refresh_probs(): save_probs(fctx_idx) */ -+ vp9_ctx->frame_context[fctx_idx] = vp9_ctx->probability_tables; -+ -+out_update_last: -+ update_ctx_last_info(vp9_ctx); -+} -+ -+static void rkvdec_init_v4l2_vp9_count_tbl(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ struct rkvdec_vp9_intra_frame_symbol_counts *intra_cnts = vp9_ctx->count_tbl.cpu; -+ struct rkvdec_vp9_inter_frame_symbol_counts *inter_cnts = vp9_ctx->count_tbl.cpu; -+ int i, j, k, l, m; -+ -+ vp9_ctx->inter_cnts.partition = &inter_cnts->partition; -+ vp9_ctx->inter_cnts.skip = &inter_cnts->skip; -+ vp9_ctx->inter_cnts.intra_inter = &inter_cnts->inter; -+ vp9_ctx->inter_cnts.tx32p = &inter_cnts->tx32p; -+ vp9_ctx->inter_cnts.tx16p = &inter_cnts->tx16p; -+ vp9_ctx->inter_cnts.tx8p = &inter_cnts->tx8p; -+ -+ vp9_ctx->intra_cnts.partition = (u32 (*)[16][4])(&intra_cnts->partition); -+ vp9_ctx->intra_cnts.skip = &intra_cnts->skip; -+ vp9_ctx->intra_cnts.intra_inter = &intra_cnts->intra; -+ vp9_ctx->intra_cnts.tx32p = &intra_cnts->tx32p; -+ vp9_ctx->intra_cnts.tx16p = &intra_cnts->tx16p; -+ vp9_ctx->intra_cnts.tx8p = &intra_cnts->tx8p; -+ -+ vp9_ctx->inter_cnts.y_mode = &inter_cnts->y_mode; -+ vp9_ctx->inter_cnts.uv_mode = &inter_cnts->uv_mode; -+ vp9_ctx->inter_cnts.comp = &inter_cnts->comp; -+ vp9_ctx->inter_cnts.comp_ref = &inter_cnts->comp_ref; -+ vp9_ctx->inter_cnts.single_ref = &inter_cnts->single_ref; -+ vp9_ctx->inter_cnts.mv_mode = &inter_cnts->mv_mode; -+ vp9_ctx->inter_cnts.filter = &inter_cnts->filter; -+ vp9_ctx->inter_cnts.mv_joint = &inter_cnts->mv_joint; -+ vp9_ctx->inter_cnts.sign = &inter_cnts->sign; -+ /* -+ * rk hardware actually uses "u32 classes[2][11 + 1];" -+ * instead of "u32 classes[2][11];", so this must be explicitly -+ * copied into vp9_ctx->classes when passing the data to the -+ * vp9 library function -+ */ -+ vp9_ctx->inter_cnts.class0 = &inter_cnts->class0; -+ vp9_ctx->inter_cnts.bits = &inter_cnts->bits; -+ vp9_ctx->inter_cnts.class0_fp = &inter_cnts->class0_fp; -+ vp9_ctx->inter_cnts.fp = &inter_cnts->fp; -+ vp9_ctx->inter_cnts.class0_hp = &inter_cnts->class0_hp; -+ vp9_ctx->inter_cnts.hp = &inter_cnts->hp; -+ -+#define INNERMOST_LOOP \ -+ do { \ -+ for (m = 0; m < ARRAY_SIZE(vp9_ctx->inter_cnts.coeff[0][0][0][0]); ++m) {\ -+ vp9_ctx->inter_cnts.coeff[i][j][k][l][m] = \ -+ &inter_cnts->ref_cnt[k][i][j][l][m].coeff; \ -+ vp9_ctx->inter_cnts.eob[i][j][k][l][m][0] = \ -+ &inter_cnts->ref_cnt[k][i][j][l][m].eob[0]; \ -+ vp9_ctx->inter_cnts.eob[i][j][k][l][m][1] = \ -+ &inter_cnts->ref_cnt[k][i][j][l][m].eob[1]; \ -+ \ -+ vp9_ctx->intra_cnts.coeff[i][j][k][l][m] = \ -+ &intra_cnts->ref_cnt[k][i][j][l][m].coeff; \ -+ vp9_ctx->intra_cnts.eob[i][j][k][l][m][0] = \ -+ &intra_cnts->ref_cnt[k][i][j][l][m].eob[0]; \ -+ vp9_ctx->intra_cnts.eob[i][j][k][l][m][1] = \ -+ &intra_cnts->ref_cnt[k][i][j][l][m].eob[1]; \ -+ } \ -+ } while (0) -+ -+ for (i = 0; i < ARRAY_SIZE(vp9_ctx->inter_cnts.coeff); ++i) -+ for (j = 0; j < ARRAY_SIZE(vp9_ctx->inter_cnts.coeff[0]); ++j) -+ for (k = 0; k < ARRAY_SIZE(vp9_ctx->inter_cnts.coeff[0][0]); ++k) -+ for (l = 0; l < ARRAY_SIZE(vp9_ctx->inter_cnts.coeff[0][0][0]); ++l) -+ INNERMOST_LOOP; -+#undef INNERMOST_LOOP -+} -+ -+static int rkvdec_vp9_start(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_vp9_priv_tbl *priv_tbl; -+ struct rkvdec_vp9_ctx *vp9_ctx; -+ unsigned char *count_tbl; -+ int ret; -+ -+ vp9_ctx = kzalloc(sizeof(*vp9_ctx), GFP_KERNEL); -+ if (!vp9_ctx) -+ return -ENOMEM; -+ -+ ctx->priv = vp9_ctx; -+ -+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), -+ &vp9_ctx->priv_tbl.dma, GFP_KERNEL); -+ if (!priv_tbl) { -+ ret = -ENOMEM; -+ goto err_free_ctx; -+ } -+ -+ vp9_ctx->priv_tbl.size = sizeof(*priv_tbl); -+ vp9_ctx->priv_tbl.cpu = priv_tbl; -+ memset(priv_tbl, 0, sizeof(*priv_tbl)); -+ -+ count_tbl = dma_alloc_coherent(rkvdec->dev, RKVDEC_VP9_COUNT_SIZE, -+ &vp9_ctx->count_tbl.dma, GFP_KERNEL); -+ if (!count_tbl) { -+ ret = -ENOMEM; -+ goto err_free_priv_tbl; -+ } -+ -+ vp9_ctx->count_tbl.size = RKVDEC_VP9_COUNT_SIZE; -+ vp9_ctx->count_tbl.cpu = count_tbl; -+ memset(count_tbl, 0, sizeof(*count_tbl)); -+ rkvdec_init_v4l2_vp9_count_tbl(ctx); -+ -+ return 0; -+ -+err_free_priv_tbl: -+ dma_free_coherent(rkvdec->dev, vp9_ctx->priv_tbl.size, -+ vp9_ctx->priv_tbl.cpu, vp9_ctx->priv_tbl.dma); -+ -+err_free_ctx: -+ kfree(vp9_ctx); -+ return ret; -+} -+ -+static void rkvdec_vp9_stop(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ -+ dma_free_coherent(rkvdec->dev, vp9_ctx->count_tbl.size, -+ vp9_ctx->count_tbl.cpu, vp9_ctx->count_tbl.dma); -+ dma_free_coherent(rkvdec->dev, vp9_ctx->priv_tbl.size, -+ vp9_ctx->priv_tbl.cpu, vp9_ctx->priv_tbl.dma); -+ kfree(vp9_ctx); -+} -+ -+static int rkvdec_vp9_adjust_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_format *f) -+{ -+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; -+ -+ fmt->num_planes = 1; -+ if (!fmt->plane_fmt[0].sizeimage) -+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * 2; -+ return 0; -+} -+ -+const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops = { -+ .adjust_fmt = rkvdec_vp9_adjust_fmt, -+ .start = rkvdec_vp9_start, -+ .stop = rkvdec_vp9_stop, -+ .run = rkvdec_vp9_run, -+ .done = rkvdec_vp9_done, -+}; -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 4fd4a2907da7..ad2624c30843 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -99,10 +99,30 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = { - .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), - }; - --static const u32 rkvdec_h264_decoded_fmts[] = { -+static const u32 rkvdec_h264_vp9_decoded_fmts[] = { - V4L2_PIX_FMT_NV12, - }; - -+static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = { -+ { -+ .cfg.id = V4L2_CID_STATELESS_VP9_FRAME, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_VP9_PROFILE, -+ .cfg.min = V4L2_MPEG_VIDEO_VP9_PROFILE_0, -+ .cfg.max = V4L2_MPEG_VIDEO_VP9_PROFILE_0, -+ .cfg.def = V4L2_MPEG_VIDEO_VP9_PROFILE_0, -+ }, -+}; -+ -+static const struct rkvdec_ctrls rkvdec_vp9_ctrls = { -+ .ctrls = rkvdec_vp9_ctrl_descs, -+ .num_ctrls = ARRAY_SIZE(rkvdec_vp9_ctrl_descs), -+}; -+ - static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, -@@ -116,8 +136,23 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - }, - .ctrls = &rkvdec_h264_ctrls, - .ops = &rkvdec_h264_fmt_ops, -- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), -- .decoded_fmts = rkvdec_h264_decoded_fmts, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), -+ .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_VP9_FRAME, -+ .frmsize = { -+ .min_width = 64, -+ .max_width = 4096, -+ .step_width = 64, -+ .min_height = 64, -+ .max_height = 2304, -+ .step_height = 64, -+ }, -+ .ctrls = &rkvdec_vp9_ctrls, -+ .ops = &rkvdec_vp9_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), -+ .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, - } - }; - -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 52ac3874c5e5..2f4ea1786b93 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -42,14 +42,18 @@ struct rkvdec_run { - - struct rkvdec_vp9_decoded_buffer_info { - /* Info needed when the decoded frame serves as a reference frame. */ -- u16 width; -- u16 height; -- u32 bit_depth : 4; -+ unsigned short width; -+ unsigned short height; -+ unsigned int bit_depth : 4; - }; - - struct rkvdec_decoded_buffer { - /* Must be the first field in this struct. */ - struct v4l2_m2m_buffer base; -+ -+ union { -+ struct rkvdec_vp9_decoded_buffer_info vp9; -+ }; - }; - - static inline struct rkvdec_decoded_buffer * -@@ -116,4 +120,6 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - - extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; -+extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; -+ - #endif /* RKVDEC_H_ */ diff --git a/projects/Allwinner/patches/linux/0074-media-hantro-Rename-registers.patch b/projects/Allwinner/patches/linux/0074-media-hantro-Rename-registers.patch deleted file mode 100644 index 84d420e852..0000000000 --- a/projects/Allwinner/patches/linux/0074-media-hantro-Rename-registers.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:38 +0100 -Subject: [PATCH] media: hantro: Rename registers - -Add more consistency in the way registers are named. - -Signed-off-by: Andrzej Pietrasiewicz -Reviewed-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil ---- - .../staging/media/hantro/hantro_g2_hevc_dec.c | 40 +++++++++---------- - drivers/staging/media/hantro/hantro_g2_regs.h | 28 ++++++------- - 2 files changed, 34 insertions(+), 34 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -index 76a921163b9a..abae36f9b418 100644 ---- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -@@ -448,9 +448,9 @@ static int set_ref(struct hantro_ctx *ctx) - if (dpb[i].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR) - dpb_longterm_e |= BIT(V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1 - i); - -- hantro_write_addr(vpu, G2_REG_ADDR_REF(i), luma_addr); -- hantro_write_addr(vpu, G2_REG_CHR_REF(i), chroma_addr); -- hantro_write_addr(vpu, G2_REG_DMV_REF(i), mv_addr); -+ hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr); -+ hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr); -+ hantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr); - } - - luma_addr = hantro_hevc_get_ref_buf(ctx, decode_params->pic_order_cnt_val); -@@ -460,20 +460,20 @@ static int set_ref(struct hantro_ctx *ctx) - chroma_addr = luma_addr + cr_offset; - mv_addr = luma_addr + mv_offset; - -- hantro_write_addr(vpu, G2_REG_ADDR_REF(i), luma_addr); -- hantro_write_addr(vpu, G2_REG_CHR_REF(i), chroma_addr); -- hantro_write_addr(vpu, G2_REG_DMV_REF(i++), mv_addr); -+ hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr); -+ hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr); -+ hantro_write_addr(vpu, G2_REF_MV_ADDR(i++), mv_addr); - -- hantro_write_addr(vpu, G2_ADDR_DST, luma_addr); -- hantro_write_addr(vpu, G2_ADDR_DST_CHR, chroma_addr); -- hantro_write_addr(vpu, G2_ADDR_DST_MV, mv_addr); -+ hantro_write_addr(vpu, G2_OUT_LUMA_ADDR, luma_addr); -+ hantro_write_addr(vpu, G2_OUT_CHROMA_ADDR, chroma_addr); -+ hantro_write_addr(vpu, G2_OUT_MV_ADDR, mv_addr); - - hantro_hevc_ref_remove_unused(ctx); - - for (; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) { -- hantro_write_addr(vpu, G2_REG_ADDR_REF(i), 0); -- hantro_write_addr(vpu, G2_REG_CHR_REF(i), 0); -- hantro_write_addr(vpu, G2_REG_DMV_REF(i), 0); -+ hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), 0); -+ hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), 0); -+ hantro_write_addr(vpu, G2_REF_MV_ADDR(i), 0); - } - - hantro_reg_write(vpu, &g2_refer_lterm_e, dpb_longterm_e); -@@ -499,7 +499,7 @@ static void set_buffers(struct hantro_ctx *ctx) - src_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); - src_buf_len = vb2_plane_size(&src_buf->vb2_buf, 0); - -- hantro_write_addr(vpu, G2_ADDR_STR, src_dma); -+ hantro_write_addr(vpu, G2_STREAM_ADDR, src_dma); - hantro_reg_write(vpu, &g2_stream_len, src_len); - hantro_reg_write(vpu, &g2_strm_buffer_len, src_buf_len); - hantro_reg_write(vpu, &g2_strm_start_offset, 0); -@@ -508,12 +508,12 @@ static void set_buffers(struct hantro_ctx *ctx) - /* Destination (decoded frame) buffer. */ - dst_dma = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf); - -- hantro_write_addr(vpu, G2_RASTER_SCAN, dst_dma); -- hantro_write_addr(vpu, G2_RASTER_SCAN_CHR, dst_dma + cr_offset); -- hantro_write_addr(vpu, G2_ADDR_TILE_SIZE, ctx->hevc_dec.tile_sizes.dma); -- hantro_write_addr(vpu, G2_TILE_FILTER, ctx->hevc_dec.tile_filter.dma); -- hantro_write_addr(vpu, G2_TILE_SAO, ctx->hevc_dec.tile_sao.dma); -- hantro_write_addr(vpu, G2_TILE_BSD, ctx->hevc_dec.tile_bsd.dma); -+ hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma); -+ hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + cr_offset); -+ hantro_write_addr(vpu, G2_TILE_SIZES_ADDR, ctx->hevc_dec.tile_sizes.dma); -+ hantro_write_addr(vpu, G2_TILE_FILTER_ADDR, ctx->hevc_dec.tile_filter.dma); -+ hantro_write_addr(vpu, G2_TILE_SAO_ADDR, ctx->hevc_dec.tile_sao.dma); -+ hantro_write_addr(vpu, G2_TILE_BSD_ADDR, ctx->hevc_dec.tile_bsd.dma); - } - - static void prepare_scaling_list_buffer(struct hantro_ctx *ctx) -@@ -563,7 +563,7 @@ static void prepare_scaling_list_buffer(struct hantro_ctx *ctx) - for (k = 0; k < 8; k++) - *p++ = sc->scaling_list_32x32[i][8 * k + j]; - -- hantro_write_addr(vpu, HEVC_SCALING_LIST, ctx->hevc_dec.scaling_lists.dma); -+ hantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma); - } - - static void hantro_g2_check_idle(struct hantro_dev *vpu) -diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h -index bb22fa921914..24b18f839ff8 100644 ---- a/drivers/staging/media/hantro/hantro_g2_regs.h -+++ b/drivers/staging/media/hantro/hantro_g2_regs.h -@@ -177,20 +177,20 @@ - #define G2_REG_CONFIG_DEC_CLK_GATE_E BIT(16) - #define G2_REG_CONFIG_DEC_CLK_GATE_IDLE_E BIT(17) - --#define G2_ADDR_DST (G2_SWREG(65)) --#define G2_REG_ADDR_REF(i) (G2_SWREG(67) + ((i) * 0x8)) --#define G2_ADDR_DST_CHR (G2_SWREG(99)) --#define G2_REG_CHR_REF(i) (G2_SWREG(101) + ((i) * 0x8)) --#define G2_ADDR_DST_MV (G2_SWREG(133)) --#define G2_REG_DMV_REF(i) (G2_SWREG(135) + ((i) * 0x8)) --#define G2_ADDR_TILE_SIZE (G2_SWREG(167)) --#define G2_ADDR_STR (G2_SWREG(169)) --#define HEVC_SCALING_LIST (G2_SWREG(171)) --#define G2_RASTER_SCAN (G2_SWREG(175)) --#define G2_RASTER_SCAN_CHR (G2_SWREG(177)) --#define G2_TILE_FILTER (G2_SWREG(179)) --#define G2_TILE_SAO (G2_SWREG(181)) --#define G2_TILE_BSD (G2_SWREG(183)) -+#define G2_OUT_LUMA_ADDR (G2_SWREG(65)) -+#define G2_REF_LUMA_ADDR(i) (G2_SWREG(67) + ((i) * 0x8)) -+#define G2_OUT_CHROMA_ADDR (G2_SWREG(99)) -+#define G2_REF_CHROMA_ADDR(i) (G2_SWREG(101) + ((i) * 0x8)) -+#define G2_OUT_MV_ADDR (G2_SWREG(133)) -+#define G2_REF_MV_ADDR(i) (G2_SWREG(135) + ((i) * 0x8)) -+#define G2_TILE_SIZES_ADDR (G2_SWREG(167)) -+#define G2_STREAM_ADDR (G2_SWREG(169)) -+#define G2_HEVC_SCALING_LIST_ADDR (G2_SWREG(171)) -+#define G2_RS_OUT_LUMA_ADDR (G2_SWREG(175)) -+#define G2_RS_OUT_CHROMA_ADDR (G2_SWREG(177)) -+#define G2_TILE_FILTER_ADDR (G2_SWREG(179)) -+#define G2_TILE_SAO_ADDR (G2_SWREG(181)) -+#define G2_TILE_BSD_ADDR (G2_SWREG(183)) - - #define g2_strm_buffer_len G2_DEC_REG(258, 0, 0xffffffff) - #define g2_strm_start_offset G2_DEC_REG(259, 0, 0xffffffff) diff --git a/projects/Allwinner/patches/linux/0075-media-hantro-Prepare-for-other-G2-codecs.patch b/projects/Allwinner/patches/linux/0075-media-hantro-Prepare-for-other-G2-codecs.patch deleted file mode 100644 index 9ec34c1123..0000000000 --- a/projects/Allwinner/patches/linux/0075-media-hantro-Prepare-for-other-G2-codecs.patch +++ /dev/null @@ -1,178 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:39 +0100 -Subject: [PATCH] media: hantro: Prepare for other G2 codecs - -VeriSilicon Hantro G2 core supports other codecs besides hevc. -Factor out some common code in preparation for vp9 support. - -Signed-off-by: Andrzej Pietrasiewicz -Reviewed-by: Benjamin Gaignard -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/Makefile | 1 + - drivers/staging/media/hantro/hantro.h | 7 +++++ - drivers/staging/media/hantro/hantro_drv.c | 5 +++ - drivers/staging/media/hantro/hantro_g2.c | 26 ++++++++++++++++ - .../staging/media/hantro/hantro_g2_hevc_dec.c | 31 ------------------- - drivers/staging/media/hantro/hantro_g2_regs.h | 7 +++++ - drivers/staging/media/hantro/hantro_hw.h | 2 ++ - 7 files changed, 48 insertions(+), 31 deletions(-) - create mode 100644 drivers/staging/media/hantro/hantro_g2.c - -diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile -index 90036831fec4..fe6d84871d07 100644 ---- a/drivers/staging/media/hantro/Makefile -+++ b/drivers/staging/media/hantro/Makefile -@@ -12,6 +12,7 @@ hantro-vpu-y += \ - hantro_g1_mpeg2_dec.o \ - hantro_g2_hevc_dec.o \ - hantro_g1_vp8_dec.o \ -+ hantro_g2.o \ - rockchip_vpu2_hw_jpeg_enc.o \ - rockchip_vpu2_hw_h264_dec.o \ - rockchip_vpu2_hw_mpeg2_dec.o \ -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index dd5e56765d4e..d91eb2b1c509 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -369,6 +369,13 @@ static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg) - writel(val, vpu->dec_base + reg); - } - -+static inline void hantro_write_addr(struct hantro_dev *vpu, -+ unsigned long offset, -+ dma_addr_t addr) -+{ -+ vdpu_write(vpu, addr & 0xffffffff, offset); -+} -+ - static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg) - { - u32 val = readl(vpu->dec_base + reg); -diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c -index fb82b9297a2b..bb72e5e208b7 100644 ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -907,6 +907,11 @@ static int hantro_probe(struct platform_device *pdev) - vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset; - vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset; - -+ /** -+ * TODO: Eventually allow taking advantage of full 64-bit address space. -+ * Until then we assume the MSB portion of buffers' base addresses is -+ * always 0 due to this masking operation. -+ */ - ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32)); - if (ret) { - dev_err(vpu->dev, "Could not set DMA coherent mask.\n"); -diff --git a/drivers/staging/media/hantro/hantro_g2.c b/drivers/staging/media/hantro/hantro_g2.c -new file mode 100644 -index 000000000000..6f3e1f797f83 ---- /dev/null -+++ b/drivers/staging/media/hantro/hantro_g2.c -@@ -0,0 +1,26 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Hantro VPU codec driver -+ * -+ * Copyright (C) 2021 Collabora Ltd, Andrzej Pietrasiewicz -+ */ -+ -+#include "hantro_hw.h" -+#include "hantro_g2_regs.h" -+ -+void hantro_g2_check_idle(struct hantro_dev *vpu) -+{ -+ int i; -+ -+ for (i = 0; i < 3; i++) { -+ u32 status; -+ -+ /* Make sure the VPU is idle */ -+ status = vdpu_read(vpu, G2_REG_INTERRUPT); -+ if (status & G2_REG_INTERRUPT_DEC_E) { -+ dev_warn(vpu->dev, "device still running, aborting"); -+ status |= G2_REG_INTERRUPT_DEC_ABORT_E | G2_REG_INTERRUPT_DEC_IRQ_DIS; -+ vdpu_write(vpu, status, G2_REG_INTERRUPT); -+ } -+ } -+} -diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -index abae36f9b418..f62608b0b408 100644 ---- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -@@ -8,20 +8,6 @@ - #include "hantro_hw.h" - #include "hantro_g2_regs.h" - --#define HEVC_DEC_MODE 0xC -- --#define BUS_WIDTH_32 0 --#define BUS_WIDTH_64 1 --#define BUS_WIDTH_128 2 --#define BUS_WIDTH_256 3 -- --static inline void hantro_write_addr(struct hantro_dev *vpu, -- unsigned long offset, -- dma_addr_t addr) --{ -- vdpu_write(vpu, addr & 0xffffffff, offset); --} -- - static void prepare_tile_info_buffer(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -@@ -566,23 +552,6 @@ static void prepare_scaling_list_buffer(struct hantro_ctx *ctx) - hantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma); - } - --static void hantro_g2_check_idle(struct hantro_dev *vpu) --{ -- int i; -- -- for (i = 0; i < 3; i++) { -- u32 status; -- -- /* Make sure the VPU is idle */ -- status = vdpu_read(vpu, G2_REG_INTERRUPT); -- if (status & G2_REG_INTERRUPT_DEC_E) { -- dev_warn(vpu->dev, "device still running, aborting"); -- status |= G2_REG_INTERRUPT_DEC_ABORT_E | G2_REG_INTERRUPT_DEC_IRQ_DIS; -- vdpu_write(vpu, status, G2_REG_INTERRUPT); -- } -- } --} -- - int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h -index 24b18f839ff8..136ba6d98a1f 100644 ---- a/drivers/staging/media/hantro/hantro_g2_regs.h -+++ b/drivers/staging/media/hantro/hantro_g2_regs.h -@@ -27,6 +27,13 @@ - #define G2_REG_INTERRUPT_DEC_IRQ_DIS BIT(4) - #define G2_REG_INTERRUPT_DEC_E BIT(0) - -+#define HEVC_DEC_MODE 0xc -+ -+#define BUS_WIDTH_32 0 -+#define BUS_WIDTH_64 1 -+#define BUS_WIDTH_128 2 -+#define BUS_WIDTH_256 3 -+ - #define g2_strm_swap G2_DEC_REG(2, 28, 0xf) - #define g2_dirmv_swap G2_DEC_REG(2, 20, 0xf) - -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index 2f85430682d8..1d869abf90b2 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -312,4 +312,6 @@ void hantro_vp8_dec_exit(struct hantro_ctx *ctx); - void hantro_vp8_prob_update(struct hantro_ctx *ctx, - const struct v4l2_ctrl_vp8_frame *hdr); - -+void hantro_g2_check_idle(struct hantro_dev *vpu); -+ - #endif /* HANTRO_HW_H_ */ diff --git a/projects/Allwinner/patches/linux/0076-media-hantro-Support-VP9-on-the-G2-core.patch b/projects/Allwinner/patches/linux/0076-media-hantro-Support-VP9-on-the-G2-core.patch deleted file mode 100644 index 1b487a4208..0000000000 --- a/projects/Allwinner/patches/linux/0076-media-hantro-Support-VP9-on-the-G2-core.patch +++ /dev/null @@ -1,1888 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:40 +0100 -Subject: [PATCH] media: hantro: Support VP9 on the G2 core - -VeriSilicon Hantro G2 core supports VP9 codec. - -Signed-off-by: Andrzej Pietrasiewicz -Reviewed-by: Benjamin Gaignard -Signed-off-by: Hans Verkuil -[hverkuil: add kerneldoc line for HANTRO_MODE_VP9_DEC] ---- - drivers/staging/media/hantro/Kconfig | 1 + - drivers/staging/media/hantro/Makefile | 6 +- - drivers/staging/media/hantro/hantro.h | 27 + - drivers/staging/media/hantro/hantro_drv.c | 18 +- - drivers/staging/media/hantro/hantro_g2_regs.h | 97 ++ - .../staging/media/hantro/hantro_g2_vp9_dec.c | 980 ++++++++++++++++++ - drivers/staging/media/hantro/hantro_hw.h | 99 ++ - drivers/staging/media/hantro/hantro_v4l2.c | 6 + - drivers/staging/media/hantro/hantro_vp9.c | 240 +++++ - drivers/staging/media/hantro/hantro_vp9.h | 102 ++ - drivers/staging/media/hantro/imx8m_vpu_hw.c | 22 +- - 11 files changed, 1594 insertions(+), 4 deletions(-) - create mode 100644 drivers/staging/media/hantro/hantro_g2_vp9_dec.c - create mode 100644 drivers/staging/media/hantro/hantro_vp9.c - create mode 100644 drivers/staging/media/hantro/hantro_vp9.h - -diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig -index 20b1f6d7b69c..00a57d88c92e 100644 ---- a/drivers/staging/media/hantro/Kconfig -+++ b/drivers/staging/media/hantro/Kconfig -@@ -9,6 +9,7 @@ config VIDEO_HANTRO - select VIDEOBUF2_VMALLOC - select V4L2_MEM2MEM_DEV - select V4L2_H264 -+ select V4L2_VP9 - help - Support for the Hantro IP based Video Processing Units present on - Rockchip and NXP i.MX8M SoCs, which accelerate video and image -diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile -index fe6d84871d07..28af0a1ee4bf 100644 ---- a/drivers/staging/media/hantro/Makefile -+++ b/drivers/staging/media/hantro/Makefile -@@ -10,9 +10,10 @@ hantro-vpu-y += \ - hantro_g1.o \ - hantro_g1_h264_dec.o \ - hantro_g1_mpeg2_dec.o \ -- hantro_g2_hevc_dec.o \ - hantro_g1_vp8_dec.o \ - hantro_g2.o \ -+ hantro_g2_hevc_dec.o \ -+ hantro_g2_vp9_dec.o \ - rockchip_vpu2_hw_jpeg_enc.o \ - rockchip_vpu2_hw_h264_dec.o \ - rockchip_vpu2_hw_mpeg2_dec.o \ -@@ -21,7 +22,8 @@ hantro-vpu-y += \ - hantro_h264.o \ - hantro_hevc.o \ - hantro_mpeg2.o \ -- hantro_vp8.o -+ hantro_vp8.o \ -+ hantro_vp9.o - - hantro-vpu-$(CONFIG_VIDEO_HANTRO_IMX8M) += \ - imx8m_vpu_hw.o -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index d91eb2b1c509..7da23f7f207a 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -36,6 +36,7 @@ struct hantro_postproc_ops; - #define HANTRO_VP8_DECODER BIT(17) - #define HANTRO_H264_DECODER BIT(18) - #define HANTRO_HEVC_DECODER BIT(19) -+#define HANTRO_VP9_DECODER BIT(20) - #define HANTRO_DECODERS 0xffff0000 - - /** -@@ -102,6 +103,7 @@ struct hantro_variant { - * @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder. - * @HANTRO_MODE_VP8_DEC: VP8 decoder. - * @HANTRO_MODE_HEVC_DEC: HEVC decoder. -+ * @HANTRO_MODE_VP9_DEC: VP9 decoder. - */ - enum hantro_codec_mode { - HANTRO_MODE_NONE = -1, -@@ -110,6 +112,7 @@ enum hantro_codec_mode { - HANTRO_MODE_MPEG2_DEC, - HANTRO_MODE_VP8_DEC, - HANTRO_MODE_HEVC_DEC, -+ HANTRO_MODE_VP9_DEC, - }; - - /* -@@ -223,6 +226,7 @@ struct hantro_dev { - * @mpeg2_dec: MPEG-2-decoding context. - * @vp8_dec: VP8-decoding context. - * @hevc_dec: HEVC-decoding context. -+ * @vp9_dec: VP9-decoding context. - */ - struct hantro_ctx { - struct hantro_dev *dev; -@@ -250,6 +254,7 @@ struct hantro_ctx { - struct hantro_mpeg2_dec_hw_ctx mpeg2_dec; - struct hantro_vp8_dec_hw_ctx vp8_dec; - struct hantro_hevc_dec_hw_ctx hevc_dec; -+ struct hantro_vp9_dec_hw_ctx vp9_dec; - }; - }; - -@@ -299,6 +304,22 @@ struct hantro_postproc_regs { - struct hantro_reg display_width; - }; - -+struct hantro_vp9_decoded_buffer_info { -+ /* Info needed when the decoded frame serves as a reference frame. */ -+ unsigned short width; -+ unsigned short height; -+ u32 bit_depth : 4; -+}; -+ -+struct hantro_decoded_buffer { -+ /* Must be the first field in this struct. */ -+ struct v4l2_m2m_buffer base; -+ -+ union { -+ struct hantro_vp9_decoded_buffer_info vp9; -+ }; -+}; -+ - /* Logging helpers */ - - /** -@@ -436,6 +457,12 @@ hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb) - return vb2_dma_contig_plane_dma_addr(vb, 0); - } - -+static inline struct hantro_decoded_buffer * -+vb2_to_hantro_decoded_buf(struct vb2_buffer *buf) -+{ -+ return container_of(buf, struct hantro_decoded_buffer, base.vb.vb2_buf); -+} -+ - void hantro_postproc_disable(struct hantro_ctx *ctx); - void hantro_postproc_enable(struct hantro_ctx *ctx); - void hantro_postproc_free(struct hantro_ctx *ctx); -diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c -index bb72e5e208b7..ab2467998d29 100644 ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -232,7 +232,7 @@ queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) - dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; - dst_vq->drv_priv = ctx; - dst_vq->ops = &hantro_queue_ops; -- dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); -+ dst_vq->buf_struct_size = sizeof(struct hantro_decoded_buffer); - dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; - dst_vq->lock = &ctx->dev->vpu_mutex; - dst_vq->dev = ctx->dev->v4l2_dev.dev; -@@ -263,6 +263,12 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) - if (sps->bit_depth_luma_minus8 != 0) - /* Only 8-bit is supported */ - return -EINVAL; -+ } else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) { -+ const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame; -+ -+ /* We only support profile 0 */ -+ if (dec_params->profile != 0) -+ return -EINVAL; - } - return 0; - } -@@ -461,6 +467,16 @@ static const struct hantro_ctrl controls[] = { - .step = 1, - .ops = &hantro_hevc_ctrl_ops, - }, -+ }, { -+ .codec = HANTRO_VP9_DECODER, -+ .cfg = { -+ .id = V4L2_CID_STATELESS_VP9_FRAME, -+ }, -+ }, { -+ .codec = HANTRO_VP9_DECODER, -+ .cfg = { -+ .id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR, -+ }, - }, - }; - -diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h -index 136ba6d98a1f..9c857dd1ad9b 100644 ---- a/drivers/staging/media/hantro/hantro_g2_regs.h -+++ b/drivers/staging/media/hantro/hantro_g2_regs.h -@@ -28,6 +28,7 @@ - #define G2_REG_INTERRUPT_DEC_E BIT(0) - - #define HEVC_DEC_MODE 0xc -+#define VP9_DEC_MODE 0xd - - #define BUS_WIDTH_32 0 - #define BUS_WIDTH_64 1 -@@ -49,6 +50,7 @@ - #define g2_pic_height_in_cbs G2_DEC_REG(4, 6, 0x1fff) - #define g2_num_ref_frames G2_DEC_REG(4, 0, 0x1f) - -+#define g2_start_bit G2_DEC_REG(5, 25, 0x7f) - #define g2_scaling_list_e G2_DEC_REG(5, 24, 0x1) - #define g2_cb_qp_offset G2_DEC_REG(5, 19, 0x1f) - #define g2_cr_qp_offset G2_DEC_REG(5, 14, 0x1f) -@@ -84,6 +86,7 @@ - #define g2_bit_depth_y_minus8 G2_DEC_REG(8, 6, 0x3) - #define g2_bit_depth_c_minus8 G2_DEC_REG(8, 4, 0x3) - #define g2_output_8_bits G2_DEC_REG(8, 3, 0x1) -+#define g2_output_format G2_DEC_REG(8, 0, 0x7) - - #define g2_refidx1_active G2_DEC_REG(9, 19, 0x1f) - #define g2_refidx0_active G2_DEC_REG(9, 14, 0x1f) -@@ -96,6 +99,14 @@ - #define g2_tile_e G2_DEC_REG(10, 1, 0x1) - #define g2_entropy_sync_e G2_DEC_REG(10, 0, 0x1) - -+#define vp9_transform_mode G2_DEC_REG(11, 27, 0x7) -+#define vp9_filt_sharpness G2_DEC_REG(11, 21, 0x7) -+#define vp9_mcomp_filt_type G2_DEC_REG(11, 8, 0x7) -+#define vp9_high_prec_mv_e G2_DEC_REG(11, 7, 0x1) -+#define vp9_comp_pred_mode G2_DEC_REG(11, 4, 0x3) -+#define vp9_gref_sign_bias G2_DEC_REG(11, 2, 0x1) -+#define vp9_aref_sign_bias G2_DEC_REG(11, 0, 0x1) -+ - #define g2_refer_lterm_e G2_DEC_REG(12, 16, 0xffff) - #define g2_min_cb_size G2_DEC_REG(12, 13, 0x7) - #define g2_max_cb_size G2_DEC_REG(12, 10, 0x7) -@@ -154,6 +165,50 @@ - #define g2_partial_ctb_y G2_DEC_REG(20, 30, 0x1) - #define g2_pic_width_4x4 G2_DEC_REG(20, 16, 0xfff) - #define g2_pic_height_4x4 G2_DEC_REG(20, 0, 0xfff) -+ -+#define vp9_qp_delta_y_dc G2_DEC_REG(13, 23, 0x3f) -+#define vp9_qp_delta_ch_dc G2_DEC_REG(13, 17, 0x3f) -+#define vp9_qp_delta_ch_ac G2_DEC_REG(13, 11, 0x3f) -+#define vp9_last_sign_bias G2_DEC_REG(13, 10, 0x1) -+#define vp9_lossless_e G2_DEC_REG(13, 9, 0x1) -+#define vp9_comp_pred_var_ref1 G2_DEC_REG(13, 7, 0x3) -+#define vp9_comp_pred_var_ref0 G2_DEC_REG(13, 5, 0x3) -+#define vp9_comp_pred_fixed_ref G2_DEC_REG(13, 3, 0x3) -+#define vp9_segment_temp_upd_e G2_DEC_REG(13, 2, 0x1) -+#define vp9_segment_upd_e G2_DEC_REG(13, 1, 0x1) -+#define vp9_segment_e G2_DEC_REG(13, 0, 0x1) -+ -+#define vp9_filt_level G2_DEC_REG(14, 18, 0x3f) -+#define vp9_refpic_seg0 G2_DEC_REG(14, 15, 0x7) -+#define vp9_skip_seg0 G2_DEC_REG(14, 14, 0x1) -+#define vp9_filt_level_seg0 G2_DEC_REG(14, 8, 0x3f) -+#define vp9_quant_seg0 G2_DEC_REG(14, 0, 0xff) -+ -+#define vp9_refpic_seg1 G2_DEC_REG(15, 15, 0x7) -+#define vp9_skip_seg1 G2_DEC_REG(15, 14, 0x1) -+#define vp9_filt_level_seg1 G2_DEC_REG(15, 8, 0x3f) -+#define vp9_quant_seg1 G2_DEC_REG(15, 0, 0xff) -+ -+#define vp9_refpic_seg2 G2_DEC_REG(16, 15, 0x7) -+#define vp9_skip_seg2 G2_DEC_REG(16, 14, 0x1) -+#define vp9_filt_level_seg2 G2_DEC_REG(16, 8, 0x3f) -+#define vp9_quant_seg2 G2_DEC_REG(16, 0, 0xff) -+ -+#define vp9_refpic_seg3 G2_DEC_REG(17, 15, 0x7) -+#define vp9_skip_seg3 G2_DEC_REG(17, 14, 0x1) -+#define vp9_filt_level_seg3 G2_DEC_REG(17, 8, 0x3f) -+#define vp9_quant_seg3 G2_DEC_REG(17, 0, 0xff) -+ -+#define vp9_refpic_seg4 G2_DEC_REG(18, 15, 0x7) -+#define vp9_skip_seg4 G2_DEC_REG(18, 14, 0x1) -+#define vp9_filt_level_seg4 G2_DEC_REG(18, 8, 0x3f) -+#define vp9_quant_seg4 G2_DEC_REG(18, 0, 0xff) -+ -+#define vp9_refpic_seg5 G2_DEC_REG(19, 15, 0x7) -+#define vp9_skip_seg5 G2_DEC_REG(19, 14, 0x1) -+#define vp9_filt_level_seg5 G2_DEC_REG(19, 8, 0x3f) -+#define vp9_quant_seg5 G2_DEC_REG(19, 0, 0xff) -+ - #define hevc_cur_poc_00 G2_DEC_REG(46, 24, 0xff) - #define hevc_cur_poc_01 G2_DEC_REG(46, 16, 0xff) - #define hevc_cur_poc_02 G2_DEC_REG(46, 8, 0xff) -@@ -174,6 +229,44 @@ - #define hevc_cur_poc_14 G2_DEC_REG(49, 8, 0xff) - #define hevc_cur_poc_15 G2_DEC_REG(49, 0, 0xff) - -+#define vp9_refpic_seg6 G2_DEC_REG(31, 15, 0x7) -+#define vp9_skip_seg6 G2_DEC_REG(31, 14, 0x1) -+#define vp9_filt_level_seg6 G2_DEC_REG(31, 8, 0x3f) -+#define vp9_quant_seg6 G2_DEC_REG(31, 0, 0xff) -+ -+#define vp9_refpic_seg7 G2_DEC_REG(32, 15, 0x7) -+#define vp9_skip_seg7 G2_DEC_REG(32, 14, 0x1) -+#define vp9_filt_level_seg7 G2_DEC_REG(32, 8, 0x3f) -+#define vp9_quant_seg7 G2_DEC_REG(32, 0, 0xff) -+ -+#define vp9_lref_width G2_DEC_REG(33, 16, 0xffff) -+#define vp9_lref_height G2_DEC_REG(33, 0, 0xffff) -+ -+#define vp9_gref_width G2_DEC_REG(34, 16, 0xffff) -+#define vp9_gref_height G2_DEC_REG(34, 0, 0xffff) -+ -+#define vp9_aref_width G2_DEC_REG(35, 16, 0xffff) -+#define vp9_aref_height G2_DEC_REG(35, 0, 0xffff) -+ -+#define vp9_lref_hor_scale G2_DEC_REG(36, 16, 0xffff) -+#define vp9_lref_ver_scale G2_DEC_REG(36, 0, 0xffff) -+ -+#define vp9_gref_hor_scale G2_DEC_REG(37, 16, 0xffff) -+#define vp9_gref_ver_scale G2_DEC_REG(37, 0, 0xffff) -+ -+#define vp9_aref_hor_scale G2_DEC_REG(38, 16, 0xffff) -+#define vp9_aref_ver_scale G2_DEC_REG(38, 0, 0xffff) -+ -+#define vp9_filt_ref_adj_0 G2_DEC_REG(46, 24, 0x7f) -+#define vp9_filt_ref_adj_1 G2_DEC_REG(46, 16, 0x7f) -+#define vp9_filt_ref_adj_2 G2_DEC_REG(46, 8, 0x7f) -+#define vp9_filt_ref_adj_3 G2_DEC_REG(46, 0, 0x7f) -+ -+#define vp9_filt_mb_adj_0 G2_DEC_REG(47, 24, 0x7f) -+#define vp9_filt_mb_adj_1 G2_DEC_REG(47, 16, 0x7f) -+#define vp9_filt_mb_adj_2 G2_DEC_REG(47, 8, 0x7f) -+#define vp9_filt_mb_adj_3 G2_DEC_REG(47, 0, 0x7f) -+ - #define g2_apf_threshold G2_DEC_REG(55, 0, 0xffff) - - #define g2_clk_gate_e G2_DEC_REG(58, 16, 0x1) -@@ -186,6 +279,8 @@ - - #define G2_OUT_LUMA_ADDR (G2_SWREG(65)) - #define G2_REF_LUMA_ADDR(i) (G2_SWREG(67) + ((i) * 0x8)) -+#define G2_VP9_SEGMENT_WRITE_ADDR (G2_SWREG(79)) -+#define G2_VP9_SEGMENT_READ_ADDR (G2_SWREG(81)) - #define G2_OUT_CHROMA_ADDR (G2_SWREG(99)) - #define G2_REF_CHROMA_ADDR(i) (G2_SWREG(101) + ((i) * 0x8)) - #define G2_OUT_MV_ADDR (G2_SWREG(133)) -@@ -193,6 +288,8 @@ - #define G2_TILE_SIZES_ADDR (G2_SWREG(167)) - #define G2_STREAM_ADDR (G2_SWREG(169)) - #define G2_HEVC_SCALING_LIST_ADDR (G2_SWREG(171)) -+#define G2_VP9_CTX_COUNT_ADDR (G2_SWREG(171)) -+#define G2_VP9_PROBS_ADDR (G2_SWREG(173)) - #define G2_RS_OUT_LUMA_ADDR (G2_SWREG(175)) - #define G2_RS_OUT_CHROMA_ADDR (G2_SWREG(177)) - #define G2_TILE_FILTER_ADDR (G2_SWREG(179)) -diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -new file mode 100644 -index 000000000000..fc55b03a8004 ---- /dev/null -+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -@@ -0,0 +1,980 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Hantro VP9 codec driver -+ * -+ * Copyright (C) 2021 Collabora Ltd. -+ */ -+#include "media/videobuf2-core.h" -+#include "media/videobuf2-dma-contig.h" -+#include "media/videobuf2-v4l2.h" -+#include -+#include -+#include -+#include -+ -+#include "hantro.h" -+#include "hantro_vp9.h" -+#include "hantro_g2_regs.h" -+ -+#define G2_ALIGN 16 -+ -+enum hantro_ref_frames { -+ INTRA_FRAME = 0, -+ LAST_FRAME = 1, -+ GOLDEN_FRAME = 2, -+ ALTREF_FRAME = 3, -+ MAX_REF_FRAMES = 4 -+}; -+ -+static int start_prepare_run(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame **dec_params) -+{ -+ const struct v4l2_ctrl_vp9_compressed_hdr *prob_updates; -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ struct v4l2_ctrl *ctrl; -+ unsigned int fctx_idx; -+ -+ /* v4l2-specific stuff */ -+ hantro_start_prepare_run(ctx); -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_handler, V4L2_CID_STATELESS_VP9_FRAME); -+ if (WARN_ON(!ctrl)) -+ return -EINVAL; -+ *dec_params = ctrl->p_cur.p; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_handler, V4L2_CID_STATELESS_VP9_COMPRESSED_HDR); -+ if (WARN_ON(!ctrl)) -+ return -EINVAL; -+ prob_updates = ctrl->p_cur.p; -+ vp9_ctx->cur.tx_mode = prob_updates->tx_mode; -+ -+ /* -+ * vp9 stuff -+ * -+ * by this point the userspace has done all parts of 6.2 uncompressed_header() -+ * except this fragment: -+ * if ( FrameIsIntra || error_resilient_mode ) { -+ * setup_past_independence ( ) -+ * if ( frame_type == KEY_FRAME || error_resilient_mode == 1 || -+ * reset_frame_context == 3 ) { -+ * for ( i = 0; i < 4; i ++ ) { -+ * save_probs( i ) -+ * } -+ * } else if ( reset_frame_context == 2 ) { -+ * save_probs( frame_context_idx ) -+ * } -+ * frame_context_idx = 0 -+ * } -+ */ -+ fctx_idx = v4l2_vp9_reset_frame_ctx(*dec_params, vp9_ctx->frame_context); -+ vp9_ctx->cur.frame_context_idx = fctx_idx; -+ -+ /* 6.1 frame(sz): load_probs() and load_probs2() */ -+ vp9_ctx->probability_tables = vp9_ctx->frame_context[fctx_idx]; -+ -+ /* -+ * The userspace has also performed 6.3 compressed_header(), but handling the -+ * probs in a special way. All probs which need updating, except MV-related, -+ * have been read from the bitstream and translated through inv_map_table[], -+ * but no 6.3.6 inv_recenter_nonneg(v, m) has been performed. The values passed -+ * by userspace are either translated values (there are no 0 values in -+ * inv_map_table[]), or zero to indicate no update. All MV-related probs which need -+ * updating have been read from the bitstream and (mv_prob << 1) | 1 has been -+ * performed. The values passed by userspace are either new values -+ * to replace old ones (the above mentioned shift and bitwise or never result in -+ * a zero) or zero to indicate no update. -+ * fw_update_probs() performs actual probs updates or leaves probs as-is -+ * for values for which a zero was passed from userspace. -+ */ -+ v4l2_vp9_fw_update_probs(&vp9_ctx->probability_tables, prob_updates, *dec_params); -+ -+ return 0; -+} -+ -+static size_t chroma_offset(const struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ int bytes_per_pixel = dec_params->bit_depth == 8 ? 1 : 2; -+ -+ return ctx->src_fmt.width * ctx->src_fmt.height * bytes_per_pixel; -+} -+ -+static size_t mv_offset(const struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ size_t cr_offset = chroma_offset(ctx, dec_params); -+ -+ return ALIGN((cr_offset * 3) / 2, G2_ALIGN); -+} -+ -+static struct hantro_decoded_buffer * -+get_ref_buf(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *dst, u64 timestamp) -+{ -+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -+ int buf_idx; -+ -+ /* -+ * If a ref is unused or invalid, address of current destination -+ * buffer is returned. -+ */ -+ buf_idx = vb2_find_timestamp(cap_q, timestamp, 0); -+ if (buf_idx < 0) -+ return vb2_to_hantro_decoded_buf(&dst->vb2_buf); -+ -+ return vb2_to_hantro_decoded_buf(vb2_get_buffer(cap_q, buf_idx)); -+} -+ -+static void update_dec_buf_info(struct hantro_decoded_buffer *buf, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ buf->vp9.width = dec_params->frame_width_minus_1 + 1; -+ buf->vp9.height = dec_params->frame_height_minus_1 + 1; -+ buf->vp9.bit_depth = dec_params->bit_depth; -+} -+ -+static void update_ctx_cur_info(struct hantro_vp9_dec_hw_ctx *vp9_ctx, -+ struct hantro_decoded_buffer *buf, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ vp9_ctx->cur.valid = true; -+ vp9_ctx->cur.reference_mode = dec_params->reference_mode; -+ vp9_ctx->cur.interpolation_filter = dec_params->interpolation_filter; -+ vp9_ctx->cur.flags = dec_params->flags; -+ vp9_ctx->cur.timestamp = buf->base.vb.vb2_buf.timestamp; -+} -+ -+static void config_output(struct hantro_ctx *ctx, -+ struct hantro_decoded_buffer *dst, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ dma_addr_t luma_addr, chroma_addr, mv_addr; -+ -+ hantro_reg_write(ctx->dev, &g2_out_dis, 0); -+ hantro_reg_write(ctx->dev, &g2_output_format, 0); -+ -+ luma_addr = vb2_dma_contig_plane_dma_addr(&dst->base.vb.vb2_buf, 0); -+ hantro_write_addr(ctx->dev, G2_OUT_LUMA_ADDR, luma_addr); -+ -+ chroma_addr = luma_addr + chroma_offset(ctx, dec_params); -+ hantro_write_addr(ctx->dev, G2_OUT_CHROMA_ADDR, chroma_addr); -+ -+ mv_addr = luma_addr + mv_offset(ctx, dec_params); -+ hantro_write_addr(ctx->dev, G2_OUT_MV_ADDR, mv_addr); -+} -+ -+struct hantro_vp9_ref_reg { -+ const struct hantro_reg width; -+ const struct hantro_reg height; -+ const struct hantro_reg hor_scale; -+ const struct hantro_reg ver_scale; -+ u32 y_base; -+ u32 c_base; -+}; -+ -+static void config_ref(struct hantro_ctx *ctx, -+ struct hantro_decoded_buffer *dst, -+ const struct hantro_vp9_ref_reg *ref_reg, -+ const struct v4l2_ctrl_vp9_frame *dec_params, -+ u64 ref_ts) -+{ -+ struct hantro_decoded_buffer *buf; -+ dma_addr_t luma_addr, chroma_addr; -+ u32 refw, refh; -+ -+ buf = get_ref_buf(ctx, &dst->base.vb, ref_ts); -+ refw = buf->vp9.width; -+ refh = buf->vp9.height; -+ -+ hantro_reg_write(ctx->dev, &ref_reg->width, refw); -+ hantro_reg_write(ctx->dev, &ref_reg->height, refh); -+ -+ hantro_reg_write(ctx->dev, &ref_reg->hor_scale, (refw << 14) / dst->vp9.width); -+ hantro_reg_write(ctx->dev, &ref_reg->ver_scale, (refh << 14) / dst->vp9.height); -+ -+ luma_addr = vb2_dma_contig_plane_dma_addr(&buf->base.vb.vb2_buf, 0); -+ hantro_write_addr(ctx->dev, ref_reg->y_base, luma_addr); -+ -+ chroma_addr = luma_addr + chroma_offset(ctx, dec_params); -+ hantro_write_addr(ctx->dev, ref_reg->c_base, chroma_addr); -+} -+ -+static void config_ref_registers(struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct hantro_decoded_buffer *dst, -+ struct hantro_decoded_buffer *mv_ref) -+{ -+ static const struct hantro_vp9_ref_reg ref_regs[] = { -+ { -+ /* Last */ -+ .width = vp9_lref_width, -+ .height = vp9_lref_height, -+ .hor_scale = vp9_lref_hor_scale, -+ .ver_scale = vp9_lref_ver_scale, -+ .y_base = G2_REF_LUMA_ADDR(0), -+ .c_base = G2_REF_CHROMA_ADDR(0), -+ }, { -+ /* Golden */ -+ .width = vp9_gref_width, -+ .height = vp9_gref_height, -+ .hor_scale = vp9_gref_hor_scale, -+ .ver_scale = vp9_gref_ver_scale, -+ .y_base = G2_REF_LUMA_ADDR(4), -+ .c_base = G2_REF_CHROMA_ADDR(4), -+ }, { -+ /* Altref */ -+ .width = vp9_aref_width, -+ .height = vp9_aref_height, -+ .hor_scale = vp9_aref_hor_scale, -+ .ver_scale = vp9_aref_ver_scale, -+ .y_base = G2_REF_LUMA_ADDR(5), -+ .c_base = G2_REF_CHROMA_ADDR(5), -+ }, -+ }; -+ dma_addr_t mv_addr; -+ -+ config_ref(ctx, dst, &ref_regs[0], dec_params, dec_params->last_frame_ts); -+ config_ref(ctx, dst, &ref_regs[1], dec_params, dec_params->golden_frame_ts); -+ config_ref(ctx, dst, &ref_regs[2], dec_params, dec_params->alt_frame_ts); -+ -+ mv_addr = vb2_dma_contig_plane_dma_addr(&mv_ref->base.vb.vb2_buf, 0) + -+ mv_offset(ctx, dec_params); -+ hantro_write_addr(ctx->dev, G2_REF_MV_ADDR(0), mv_addr); -+ -+ hantro_reg_write(ctx->dev, &vp9_last_sign_bias, -+ dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_LAST ? 1 : 0); -+ -+ hantro_reg_write(ctx->dev, &vp9_gref_sign_bias, -+ dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_GOLDEN ? 1 : 0); -+ -+ hantro_reg_write(ctx->dev, &vp9_aref_sign_bias, -+ dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_ALT ? 1 : 0); -+} -+ -+static void recompute_tile_info(unsigned short *tile_info, unsigned int tiles, unsigned int sbs) -+{ -+ int i; -+ unsigned int accumulated = 0; -+ unsigned int next_accumulated; -+ -+ for (i = 1; i <= tiles; ++i) { -+ next_accumulated = i * sbs / tiles; -+ *tile_info++ = next_accumulated - accumulated; -+ accumulated = next_accumulated; -+ } -+} -+ -+static void -+recompute_tile_rc_info(struct hantro_ctx *ctx, -+ unsigned int tile_r, unsigned int tile_c, -+ unsigned int sbs_r, unsigned int sbs_c) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ -+ recompute_tile_info(vp9_ctx->tile_r_info, tile_r, sbs_r); -+ recompute_tile_info(vp9_ctx->tile_c_info, tile_c, sbs_c); -+ -+ vp9_ctx->last_tile_r = tile_r; -+ vp9_ctx->last_tile_c = tile_c; -+ vp9_ctx->last_sbs_r = sbs_r; -+ vp9_ctx->last_sbs_c = sbs_c; -+} -+ -+static inline unsigned int first_tile_row(unsigned int tile_r, unsigned int sbs_r) -+{ -+ if (tile_r == sbs_r + 1) -+ return 1; -+ -+ if (tile_r == sbs_r + 2) -+ return 2; -+ -+ return 0; -+} -+ -+static void -+fill_tile_info(struct hantro_ctx *ctx, -+ unsigned int tile_r, unsigned int tile_c, -+ unsigned int sbs_r, unsigned int sbs_c, -+ unsigned short *tile_mem) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ unsigned int i, j; -+ bool first = true; -+ -+ for (i = first_tile_row(tile_r, sbs_r); i < tile_r; ++i) { -+ unsigned short r_info = vp9_ctx->tile_r_info[i]; -+ -+ if (first) { -+ if (i > 0) -+ r_info += vp9_ctx->tile_r_info[0]; -+ if (i == 2) -+ r_info += vp9_ctx->tile_r_info[1]; -+ first = false; -+ } -+ for (j = 0; j < tile_c; ++j) { -+ *tile_mem++ = vp9_ctx->tile_c_info[j]; -+ *tile_mem++ = r_info; -+ } -+ } -+} -+ -+static void -+config_tiles(struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct hantro_decoded_buffer *dst) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ struct hantro_aux_buf *misc = &vp9_ctx->misc; -+ struct hantro_aux_buf *tile_edge = &vp9_ctx->tile_edge; -+ dma_addr_t addr; -+ unsigned short *tile_mem; -+ -+ addr = misc->dma + vp9_ctx->tile_info_offset; -+ hantro_write_addr(ctx->dev, G2_TILE_SIZES_ADDR, addr); -+ -+ tile_mem = misc->cpu + vp9_ctx->tile_info_offset; -+ if (dec_params->tile_cols_log2 || dec_params->tile_rows_log2) { -+ unsigned int tile_r = (1 << dec_params->tile_rows_log2); -+ unsigned int tile_c = (1 << dec_params->tile_cols_log2); -+ unsigned int sbs_r = hantro_vp9_num_sbs(dst->vp9.height); -+ unsigned int sbs_c = hantro_vp9_num_sbs(dst->vp9.width); -+ -+ if (tile_r != vp9_ctx->last_tile_r || tile_c != vp9_ctx->last_tile_c || -+ sbs_r != vp9_ctx->last_sbs_r || sbs_c != vp9_ctx->last_sbs_c) -+ recompute_tile_rc_info(ctx, tile_r, tile_c, sbs_r, sbs_c); -+ -+ fill_tile_info(ctx, tile_r, tile_c, sbs_r, sbs_c, tile_mem); -+ -+ hantro_reg_write(ctx->dev, &g2_tile_e, 1); -+ hantro_reg_write(ctx->dev, &g2_num_tile_cols, tile_c); -+ hantro_reg_write(ctx->dev, &g2_num_tile_rows, tile_r); -+ -+ } else { -+ tile_mem[0] = hantro_vp9_num_sbs(dst->vp9.width); -+ tile_mem[1] = hantro_vp9_num_sbs(dst->vp9.height); -+ -+ hantro_reg_write(ctx->dev, &g2_tile_e, 0); -+ hantro_reg_write(ctx->dev, &g2_num_tile_cols, 1); -+ hantro_reg_write(ctx->dev, &g2_num_tile_rows, 1); -+ } -+ -+ /* provide aux buffers even if no tiles are used */ -+ addr = tile_edge->dma; -+ hantro_write_addr(ctx->dev, G2_TILE_FILTER_ADDR, addr); -+ -+ addr = tile_edge->dma + vp9_ctx->bsd_ctrl_offset; -+ hantro_write_addr(ctx->dev, G2_TILE_BSD_ADDR, addr); -+} -+ -+static void -+update_feat_and_flag(struct hantro_vp9_dec_hw_ctx *vp9_ctx, -+ const struct v4l2_vp9_segmentation *seg, -+ unsigned int feature, -+ unsigned int segid) -+{ -+ u8 mask = V4L2_VP9_SEGMENT_FEATURE_ENABLED(feature); -+ -+ vp9_ctx->feature_data[segid][feature] = seg->feature_data[segid][feature]; -+ vp9_ctx->feature_enabled[segid] &= ~mask; -+ vp9_ctx->feature_enabled[segid] |= (seg->feature_enabled[segid] & mask); -+} -+ -+static inline s16 clip3(s16 x, s16 y, s16 z) -+{ -+ return (z < x) ? x : (z > y) ? y : z; -+} -+ -+static s16 feat_val_clip3(s16 feat_val, s16 feature_data, bool absolute, u8 clip) -+{ -+ if (absolute) -+ return feature_data; -+ -+ return clip3(0, 255, feat_val + feature_data); -+} -+ -+static void config_segment(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ const struct v4l2_vp9_segmentation *seg; -+ s16 feat_val; -+ unsigned char feat_id; -+ unsigned int segid; -+ bool segment_enabled, absolute, update_data; -+ -+ static const struct hantro_reg seg_regs[8][V4L2_VP9_SEG_LVL_MAX] = { -+ { vp9_quant_seg0, vp9_filt_level_seg0, vp9_refpic_seg0, vp9_skip_seg0 }, -+ { vp9_quant_seg1, vp9_filt_level_seg1, vp9_refpic_seg1, vp9_skip_seg1 }, -+ { vp9_quant_seg2, vp9_filt_level_seg2, vp9_refpic_seg2, vp9_skip_seg2 }, -+ { vp9_quant_seg3, vp9_filt_level_seg3, vp9_refpic_seg3, vp9_skip_seg3 }, -+ { vp9_quant_seg4, vp9_filt_level_seg4, vp9_refpic_seg4, vp9_skip_seg4 }, -+ { vp9_quant_seg5, vp9_filt_level_seg5, vp9_refpic_seg5, vp9_skip_seg5 }, -+ { vp9_quant_seg6, vp9_filt_level_seg6, vp9_refpic_seg6, vp9_skip_seg6 }, -+ { vp9_quant_seg7, vp9_filt_level_seg7, vp9_refpic_seg7, vp9_skip_seg7 }, -+ }; -+ -+ segment_enabled = !!(dec_params->seg.flags & V4L2_VP9_SEGMENTATION_FLAG_ENABLED); -+ hantro_reg_write(ctx->dev, &vp9_segment_e, segment_enabled); -+ hantro_reg_write(ctx->dev, &vp9_segment_upd_e, -+ !!(dec_params->seg.flags & V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP)); -+ hantro_reg_write(ctx->dev, &vp9_segment_temp_upd_e, -+ !!(dec_params->seg.flags & V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE)); -+ -+ seg = &dec_params->seg; -+ absolute = !!(seg->flags & V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE); -+ update_data = !!(seg->flags & V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA); -+ -+ for (segid = 0; segid < 8; ++segid) { -+ /* Quantizer segment feature */ -+ feat_id = V4L2_VP9_SEG_LVL_ALT_Q; -+ feat_val = dec_params->quant.base_q_idx; -+ if (segment_enabled) { -+ if (update_data) -+ update_feat_and_flag(vp9_ctx, seg, feat_id, segid); -+ if (v4l2_vp9_seg_feat_enabled(vp9_ctx->feature_enabled, feat_id, segid)) -+ feat_val = feat_val_clip3(feat_val, -+ vp9_ctx->feature_data[segid][feat_id], -+ absolute, 255); -+ } -+ hantro_reg_write(ctx->dev, &seg_regs[segid][feat_id], feat_val); -+ -+ /* Loop filter segment feature */ -+ feat_id = V4L2_VP9_SEG_LVL_ALT_L; -+ feat_val = dec_params->lf.level; -+ if (segment_enabled) { -+ if (update_data) -+ update_feat_and_flag(vp9_ctx, seg, feat_id, segid); -+ if (v4l2_vp9_seg_feat_enabled(vp9_ctx->feature_enabled, feat_id, segid)) -+ feat_val = feat_val_clip3(feat_val, -+ vp9_ctx->feature_data[segid][feat_id], -+ absolute, 63); -+ } -+ hantro_reg_write(ctx->dev, &seg_regs[segid][feat_id], feat_val); -+ -+ /* Reference frame segment feature */ -+ feat_id = V4L2_VP9_SEG_LVL_REF_FRAME; -+ feat_val = 0; -+ if (segment_enabled) { -+ if (update_data) -+ update_feat_and_flag(vp9_ctx, seg, feat_id, segid); -+ if (!(dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME) && -+ v4l2_vp9_seg_feat_enabled(vp9_ctx->feature_enabled, feat_id, segid)) -+ feat_val = vp9_ctx->feature_data[segid][feat_id] + 1; -+ } -+ hantro_reg_write(ctx->dev, &seg_regs[segid][feat_id], feat_val); -+ -+ /* Skip segment feature */ -+ feat_id = V4L2_VP9_SEG_LVL_SKIP; -+ feat_val = 0; -+ if (segment_enabled) { -+ if (update_data) -+ update_feat_and_flag(vp9_ctx, seg, feat_id, segid); -+ feat_val = v4l2_vp9_seg_feat_enabled(vp9_ctx->feature_enabled, -+ feat_id, segid) ? 1 : 0; -+ } -+ hantro_reg_write(ctx->dev, &seg_regs[segid][feat_id], feat_val); -+ } -+} -+ -+static void config_loop_filter(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ bool d = dec_params->lf.flags & V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED; -+ -+ hantro_reg_write(ctx->dev, &vp9_filt_level, dec_params->lf.level); -+ hantro_reg_write(ctx->dev, &g2_out_filtering_dis, dec_params->lf.level == 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_sharpness, dec_params->lf.sharpness); -+ -+ hantro_reg_write(ctx->dev, &vp9_filt_ref_adj_0, d ? dec_params->lf.ref_deltas[0] : 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_ref_adj_1, d ? dec_params->lf.ref_deltas[1] : 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_ref_adj_2, d ? dec_params->lf.ref_deltas[2] : 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_ref_adj_3, d ? dec_params->lf.ref_deltas[3] : 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_mb_adj_0, d ? dec_params->lf.mode_deltas[0] : 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_mb_adj_1, d ? dec_params->lf.mode_deltas[1] : 0); -+} -+ -+static void config_picture_dimensions(struct hantro_ctx *ctx, struct hantro_decoded_buffer *dst) -+{ -+ u32 pic_w_4x4, pic_h_4x4; -+ -+ hantro_reg_write(ctx->dev, &g2_pic_width_in_cbs, (dst->vp9.width + 7) / 8); -+ hantro_reg_write(ctx->dev, &g2_pic_height_in_cbs, (dst->vp9.height + 7) / 8); -+ pic_w_4x4 = roundup(dst->vp9.width, 8) >> 2; -+ pic_h_4x4 = roundup(dst->vp9.height, 8) >> 2; -+ hantro_reg_write(ctx->dev, &g2_pic_width_4x4, pic_w_4x4); -+ hantro_reg_write(ctx->dev, &g2_pic_height_4x4, pic_h_4x4); -+} -+ -+static void -+config_bit_depth(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8); -+ hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8); -+} -+ -+static inline bool is_lossless(const struct v4l2_vp9_quantization *quant) -+{ -+ return quant->base_q_idx == 0 && quant->delta_q_uv_ac == 0 && -+ quant->delta_q_uv_dc == 0 && quant->delta_q_y_dc == 0; -+} -+ -+static void -+config_quant(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ hantro_reg_write(ctx->dev, &vp9_qp_delta_y_dc, dec_params->quant.delta_q_y_dc); -+ hantro_reg_write(ctx->dev, &vp9_qp_delta_ch_dc, dec_params->quant.delta_q_uv_dc); -+ hantro_reg_write(ctx->dev, &vp9_qp_delta_ch_ac, dec_params->quant.delta_q_uv_ac); -+ hantro_reg_write(ctx->dev, &vp9_lossless_e, is_lossless(&dec_params->quant)); -+} -+ -+static u32 -+hantro_interp_filter_from_v4l2(unsigned int interpolation_filter) -+{ -+ switch (interpolation_filter) { -+ case V4L2_VP9_INTERP_FILTER_EIGHTTAP: -+ return 0x1; -+ case V4L2_VP9_INTERP_FILTER_EIGHTTAP_SMOOTH: -+ return 0; -+ case V4L2_VP9_INTERP_FILTER_EIGHTTAP_SHARP: -+ return 0x2; -+ case V4L2_VP9_INTERP_FILTER_BILINEAR: -+ return 0x3; -+ case V4L2_VP9_INTERP_FILTER_SWITCHABLE: -+ return 0x4; -+ } -+ -+ return 0; -+} -+ -+static void -+config_others(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params, -+ bool intra_only, bool resolution_change) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ -+ hantro_reg_write(ctx->dev, &g2_idr_pic_e, intra_only); -+ -+ hantro_reg_write(ctx->dev, &vp9_transform_mode, vp9_ctx->cur.tx_mode); -+ -+ hantro_reg_write(ctx->dev, &vp9_mcomp_filt_type, intra_only ? -+ 0 : hantro_interp_filter_from_v4l2(dec_params->interpolation_filter)); -+ -+ hantro_reg_write(ctx->dev, &vp9_high_prec_mv_e, -+ !!(dec_params->flags & V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV)); -+ -+ hantro_reg_write(ctx->dev, &vp9_comp_pred_mode, dec_params->reference_mode); -+ -+ hantro_reg_write(ctx->dev, &g2_tempor_mvp_e, -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) && -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME) && -+ !(vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME) && -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_INTRA_ONLY) && -+ !resolution_change && -+ vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_SHOW_FRAME -+ ); -+ -+ hantro_reg_write(ctx->dev, &g2_write_mvs_e, -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME)); -+} -+ -+static void -+config_compound_reference(struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ u32 comp_fixed_ref, comp_var_ref[2]; -+ bool last_ref_frame_sign_bias; -+ bool golden_ref_frame_sign_bias; -+ bool alt_ref_frame_sign_bias; -+ bool comp_ref_allowed = 0; -+ -+ comp_fixed_ref = 0; -+ comp_var_ref[0] = 0; -+ comp_var_ref[1] = 0; -+ -+ last_ref_frame_sign_bias = dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_LAST; -+ golden_ref_frame_sign_bias = dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_GOLDEN; -+ alt_ref_frame_sign_bias = dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_ALT; -+ -+ /* 6.3.12 Frame reference mode syntax */ -+ comp_ref_allowed |= golden_ref_frame_sign_bias != last_ref_frame_sign_bias; -+ comp_ref_allowed |= alt_ref_frame_sign_bias != last_ref_frame_sign_bias; -+ -+ if (comp_ref_allowed) { -+ if (last_ref_frame_sign_bias == -+ golden_ref_frame_sign_bias) { -+ comp_fixed_ref = ALTREF_FRAME; -+ comp_var_ref[0] = LAST_FRAME; -+ comp_var_ref[1] = GOLDEN_FRAME; -+ } else if (last_ref_frame_sign_bias == -+ alt_ref_frame_sign_bias) { -+ comp_fixed_ref = GOLDEN_FRAME; -+ comp_var_ref[0] = LAST_FRAME; -+ comp_var_ref[1] = ALTREF_FRAME; -+ } else { -+ comp_fixed_ref = LAST_FRAME; -+ comp_var_ref[0] = GOLDEN_FRAME; -+ comp_var_ref[1] = ALTREF_FRAME; -+ } -+ } -+ -+ hantro_reg_write(ctx->dev, &vp9_comp_pred_fixed_ref, comp_fixed_ref); -+ hantro_reg_write(ctx->dev, &vp9_comp_pred_var_ref0, comp_var_ref[0]); -+ hantro_reg_write(ctx->dev, &vp9_comp_pred_var_ref1, comp_var_ref[1]); -+} -+ -+#define INNER_LOOP \ -+do { \ -+ for (m = 0; m < ARRAY_SIZE(adaptive->coef[0][0][0][0]); ++m) { \ -+ memcpy(adaptive->coef[i][j][k][l][m], \ -+ probs->coef[i][j][k][l][m], \ -+ sizeof(probs->coef[i][j][k][l][m])); \ -+ \ -+ adaptive->coef[i][j][k][l][m][3] = 0; \ -+ } \ -+} while (0) -+ -+static void config_probs(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ struct hantro_aux_buf *misc = &vp9_ctx->misc; -+ struct hantro_g2_all_probs *all_probs = misc->cpu; -+ struct hantro_g2_probs *adaptive; -+ struct hantro_g2_mv_probs *mv; -+ const struct v4l2_vp9_segmentation *seg = &dec_params->seg; -+ const struct v4l2_vp9_frame_context *probs = &vp9_ctx->probability_tables; -+ int i, j, k, l, m; -+ -+ for (i = 0; i < ARRAY_SIZE(all_probs->kf_y_mode_prob); ++i) -+ for (j = 0; j < ARRAY_SIZE(all_probs->kf_y_mode_prob[0]); ++j) { -+ memcpy(all_probs->kf_y_mode_prob[i][j], -+ v4l2_vp9_kf_y_mode_prob[i][j], -+ ARRAY_SIZE(all_probs->kf_y_mode_prob[i][j])); -+ -+ all_probs->kf_y_mode_prob_tail[i][j][0] = -+ v4l2_vp9_kf_y_mode_prob[i][j][8]; -+ } -+ -+ memcpy(all_probs->mb_segment_tree_probs, seg->tree_probs, -+ sizeof(all_probs->mb_segment_tree_probs)); -+ -+ memcpy(all_probs->segment_pred_probs, seg->pred_probs, -+ sizeof(all_probs->segment_pred_probs)); -+ -+ for (i = 0; i < ARRAY_SIZE(all_probs->kf_uv_mode_prob); ++i) { -+ memcpy(all_probs->kf_uv_mode_prob[i], v4l2_vp9_kf_uv_mode_prob[i], -+ ARRAY_SIZE(all_probs->kf_uv_mode_prob[i])); -+ -+ all_probs->kf_uv_mode_prob_tail[i][0] = v4l2_vp9_kf_uv_mode_prob[i][8]; -+ } -+ -+ adaptive = &all_probs->probs; -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->inter_mode); ++i) { -+ memcpy(adaptive->inter_mode[i], probs->inter_mode[i], -+ ARRAY_SIZE(probs->inter_mode[i])); -+ -+ adaptive->inter_mode[i][3] = 0; -+ } -+ -+ memcpy(adaptive->is_inter, probs->is_inter, sizeof(adaptive->is_inter)); -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->uv_mode); ++i) { -+ memcpy(adaptive->uv_mode[i], probs->uv_mode[i], -+ sizeof(adaptive->uv_mode[i])); -+ adaptive->uv_mode_tail[i][0] = probs->uv_mode[i][8]; -+ } -+ -+ memcpy(adaptive->tx8, probs->tx8, sizeof(adaptive->tx8)); -+ memcpy(adaptive->tx16, probs->tx16, sizeof(adaptive->tx16)); -+ memcpy(adaptive->tx32, probs->tx32, sizeof(adaptive->tx32)); -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->y_mode); ++i) { -+ memcpy(adaptive->y_mode[i], probs->y_mode[i], -+ ARRAY_SIZE(adaptive->y_mode[i])); -+ -+ adaptive->y_mode_tail[i][0] = probs->y_mode[i][8]; -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->partition[0]); ++i) { -+ memcpy(adaptive->partition[0][i], v4l2_vp9_kf_partition_probs[i], -+ sizeof(v4l2_vp9_kf_partition_probs[i])); -+ -+ adaptive->partition[0][i][3] = 0; -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->partition[1]); ++i) { -+ memcpy(adaptive->partition[1][i], probs->partition[i], -+ sizeof(probs->partition[i])); -+ -+ adaptive->partition[1][i][3] = 0; -+ } -+ -+ memcpy(adaptive->interp_filter, probs->interp_filter, -+ sizeof(adaptive->interp_filter)); -+ -+ memcpy(adaptive->comp_mode, probs->comp_mode, sizeof(adaptive->comp_mode)); -+ -+ memcpy(adaptive->skip, probs->skip, sizeof(adaptive->skip)); -+ -+ mv = &adaptive->mv; -+ -+ memcpy(mv->joint, probs->mv.joint, sizeof(mv->joint)); -+ memcpy(mv->sign, probs->mv.sign, sizeof(mv->sign)); -+ memcpy(mv->class0_bit, probs->mv.class0_bit, sizeof(mv->class0_bit)); -+ memcpy(mv->fr, probs->mv.fr, sizeof(mv->fr)); -+ memcpy(mv->class0_hp, probs->mv.class0_hp, sizeof(mv->class0_hp)); -+ memcpy(mv->hp, probs->mv.hp, sizeof(mv->hp)); -+ memcpy(mv->classes, probs->mv.classes, sizeof(mv->classes)); -+ memcpy(mv->class0_fr, probs->mv.class0_fr, sizeof(mv->class0_fr)); -+ memcpy(mv->bits, probs->mv.bits, sizeof(mv->bits)); -+ -+ memcpy(adaptive->single_ref, probs->single_ref, sizeof(adaptive->single_ref)); -+ -+ memcpy(adaptive->comp_ref, probs->comp_ref, sizeof(adaptive->comp_ref)); -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->coef); ++i) -+ for (j = 0; j < ARRAY_SIZE(adaptive->coef[0]); ++j) -+ for (k = 0; k < ARRAY_SIZE(adaptive->coef[0][0]); ++k) -+ for (l = 0; l < ARRAY_SIZE(adaptive->coef[0][0][0]); ++l) -+ INNER_LOOP; -+ -+ hantro_write_addr(ctx->dev, G2_VP9_PROBS_ADDR, misc->dma); -+} -+ -+static void config_counts(struct hantro_ctx *ctx) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_dec = &ctx->vp9_dec; -+ struct hantro_aux_buf *misc = &vp9_dec->misc; -+ dma_addr_t addr = misc->dma + vp9_dec->ctx_counters_offset; -+ -+ hantro_write_addr(ctx->dev, G2_VP9_CTX_COUNT_ADDR, addr); -+} -+ -+static void config_seg_map(struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params, -+ bool intra_only, bool update_map) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ struct hantro_aux_buf *segment_map = &vp9_ctx->segment_map; -+ dma_addr_t addr; -+ -+ if (intra_only || -+ (dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT)) { -+ memset(segment_map->cpu, 0, segment_map->size); -+ memset(vp9_ctx->feature_data, 0, sizeof(vp9_ctx->feature_data)); -+ memset(vp9_ctx->feature_enabled, 0, sizeof(vp9_ctx->feature_enabled)); -+ } -+ -+ addr = segment_map->dma + vp9_ctx->active_segment * vp9_ctx->segment_map_size; -+ hantro_write_addr(ctx->dev, G2_VP9_SEGMENT_READ_ADDR, addr); -+ -+ addr = segment_map->dma + (1 - vp9_ctx->active_segment) * vp9_ctx->segment_map_size; -+ hantro_write_addr(ctx->dev, G2_VP9_SEGMENT_WRITE_ADDR, addr); -+ -+ if (update_map) -+ vp9_ctx->active_segment = 1 - vp9_ctx->active_segment; -+} -+ -+static void -+config_source(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct vb2_v4l2_buffer *vb2_src) -+{ -+ dma_addr_t stream_base, tmp_addr; -+ unsigned int headres_size; -+ u32 src_len, start_bit, src_buf_len; -+ -+ headres_size = dec_params->uncompressed_header_size -+ + dec_params->compressed_header_size; -+ -+ stream_base = vb2_dma_contig_plane_dma_addr(&vb2_src->vb2_buf, 0); -+ hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base); -+ -+ tmp_addr = stream_base + headres_size; -+ start_bit = (tmp_addr & 0xf) * 8; -+ hantro_reg_write(ctx->dev, &g2_start_bit, start_bit); -+ -+ src_len = vb2_get_plane_payload(&vb2_src->vb2_buf, 0); -+ src_len += start_bit / 8 - headres_size; -+ hantro_reg_write(ctx->dev, &g2_stream_len, src_len); -+ -+ tmp_addr &= ~0xf; -+ hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base); -+ src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0); -+ hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len); -+} -+ -+static void -+config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct vb2_v4l2_buffer *vb2_src, struct vb2_v4l2_buffer *vb2_dst) -+{ -+ struct hantro_decoded_buffer *dst, *last, *mv_ref; -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ const struct v4l2_vp9_segmentation *seg; -+ bool intra_only, resolution_change; -+ -+ /* vp9 stuff */ -+ dst = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf); -+ -+ if (vp9_ctx->last.valid) -+ last = get_ref_buf(ctx, &dst->base.vb, vp9_ctx->last.timestamp); -+ else -+ last = dst; -+ -+ update_dec_buf_info(dst, dec_params); -+ update_ctx_cur_info(vp9_ctx, dst, dec_params); -+ seg = &dec_params->seg; -+ -+ intra_only = !!(dec_params->flags & -+ (V4L2_VP9_FRAME_FLAG_KEY_FRAME | -+ V4L2_VP9_FRAME_FLAG_INTRA_ONLY)); -+ -+ if (!intra_only && -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) && -+ vp9_ctx->last.valid) -+ mv_ref = last; -+ else -+ mv_ref = dst; -+ -+ resolution_change = dst->vp9.width != last->vp9.width || -+ dst->vp9.height != last->vp9.height; -+ -+ /* configure basic registers */ -+ hantro_reg_write(ctx->dev, &g2_mode, VP9_DEC_MODE); -+ hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf); -+ hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf); -+ hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf); -+ hantro_reg_write(ctx->dev, &g2_buswidth, BUS_WIDTH_128); -+ hantro_reg_write(ctx->dev, &g2_max_burst, 16); -+ hantro_reg_write(ctx->dev, &g2_apf_threshold, 8); -+ hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1); -+ hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1); -+ hantro_reg_write(ctx->dev, &g2_max_cb_size, 6); -+ hantro_reg_write(ctx->dev, &g2_min_cb_size, 3); -+ -+ config_output(ctx, dst, dec_params); -+ -+ if (!intra_only) -+ config_ref_registers(ctx, dec_params, dst, mv_ref); -+ -+ config_tiles(ctx, dec_params, dst); -+ config_segment(ctx, dec_params); -+ config_loop_filter(ctx, dec_params); -+ config_picture_dimensions(ctx, dst); -+ config_bit_depth(ctx, dec_params); -+ config_quant(ctx, dec_params); -+ config_others(ctx, dec_params, intra_only, resolution_change); -+ config_compound_reference(ctx, dec_params); -+ config_probs(ctx, dec_params); -+ config_counts(ctx); -+ config_seg_map(ctx, dec_params, intra_only, -+ seg->flags & V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP); -+ config_source(ctx, dec_params, vb2_src); -+} -+ -+int hantro_g2_vp9_dec_run(struct hantro_ctx *ctx) -+{ -+ const struct v4l2_ctrl_vp9_frame *decode_params; -+ struct vb2_v4l2_buffer *src; -+ struct vb2_v4l2_buffer *dst; -+ int ret; -+ -+ hantro_g2_check_idle(ctx->dev); -+ -+ ret = start_prepare_run(ctx, &decode_params); -+ if (ret) { -+ hantro_end_prepare_run(ctx); -+ return ret; -+ } -+ -+ src = hantro_get_src_buf(ctx); -+ dst = hantro_get_dst_buf(ctx); -+ -+ config_registers(ctx, decode_params, src, dst); -+ -+ hantro_end_prepare_run(ctx); -+ -+ vdpu_write(ctx->dev, G2_REG_INTERRUPT_DEC_E, G2_REG_INTERRUPT); -+ -+ return 0; -+} -+ -+#define copy_tx_and_skip(p1, p2) \ -+do { \ -+ memcpy((p1)->tx8, (p2)->tx8, sizeof((p1)->tx8)); \ -+ memcpy((p1)->tx16, (p2)->tx16, sizeof((p1)->tx16)); \ -+ memcpy((p1)->tx32, (p2)->tx32, sizeof((p1)->tx32)); \ -+ memcpy((p1)->skip, (p2)->skip, sizeof((p1)->skip)); \ -+} while (0) -+ -+void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ unsigned int fctx_idx; -+ -+ if (!(vp9_ctx->cur.flags & V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX)) -+ goto out_update_last; -+ -+ fctx_idx = vp9_ctx->cur.frame_context_idx; -+ -+ if (!(vp9_ctx->cur.flags & V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE)) { -+ /* error_resilient_mode == 0 && frame_parallel_decoding_mode == 0 */ -+ struct v4l2_vp9_frame_context *probs = &vp9_ctx->probability_tables; -+ bool frame_is_intra = vp9_ctx->cur.flags & -+ (V4L2_VP9_FRAME_FLAG_KEY_FRAME | V4L2_VP9_FRAME_FLAG_INTRA_ONLY); -+ struct tx_and_skip { -+ u8 tx8[2][1]; -+ u8 tx16[2][2]; -+ u8 tx32[2][3]; -+ u8 skip[3]; -+ } _tx_skip, *tx_skip = &_tx_skip; -+ struct v4l2_vp9_frame_symbol_counts *counts; -+ struct symbol_counts *hantro_cnts; -+ u32 tx16p[2][4]; -+ int i; -+ -+ /* buffer the forward-updated TX and skip probs */ -+ if (frame_is_intra) -+ copy_tx_and_skip(tx_skip, probs); -+ -+ /* 6.1.2 refresh_probs(): load_probs() and load_probs2() */ -+ *probs = vp9_ctx->frame_context[fctx_idx]; -+ -+ /* if FrameIsIntra then undo the effect of load_probs2() */ -+ if (frame_is_intra) -+ copy_tx_and_skip(probs, tx_skip); -+ -+ counts = &vp9_ctx->cnts; -+ hantro_cnts = vp9_ctx->misc.cpu + vp9_ctx->ctx_counters_offset; -+ for (i = 0; i < ARRAY_SIZE(tx16p); ++i) { -+ memcpy(tx16p[i], -+ hantro_cnts->tx16x16_count[i], -+ sizeof(hantro_cnts->tx16x16_count[0])); -+ tx16p[i][3] = 0; -+ } -+ counts->tx16p = &tx16p; -+ -+ v4l2_vp9_adapt_coef_probs(probs, counts, -+ !vp9_ctx->last.valid || -+ vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME, -+ frame_is_intra); -+ -+ if (!frame_is_intra) { -+ /* load_probs2() already done */ -+ u32 mv_mode[7][4]; -+ -+ for (i = 0; i < ARRAY_SIZE(mv_mode); ++i) { -+ mv_mode[i][0] = hantro_cnts->inter_mode_counts[i][1][0]; -+ mv_mode[i][1] = hantro_cnts->inter_mode_counts[i][2][0]; -+ mv_mode[i][2] = hantro_cnts->inter_mode_counts[i][0][0]; -+ mv_mode[i][3] = hantro_cnts->inter_mode_counts[i][2][1]; -+ } -+ counts->mv_mode = &mv_mode; -+ v4l2_vp9_adapt_noncoef_probs(&vp9_ctx->probability_tables, counts, -+ vp9_ctx->cur.reference_mode, -+ vp9_ctx->cur.interpolation_filter, -+ vp9_ctx->cur.tx_mode, vp9_ctx->cur.flags); -+ } -+ } -+ -+ vp9_ctx->frame_context[fctx_idx] = vp9_ctx->probability_tables; -+ -+out_update_last: -+ vp9_ctx->last = vp9_ctx->cur; -+} -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index 1d869abf90b2..fe5b51046d33 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - #include - - #define DEC_8190_ALIGN_MASK 0x07U -@@ -165,6 +166,82 @@ struct hantro_vp8_dec_hw_ctx { - struct hantro_aux_buf prob_tbl; - }; - -+/** -+ * struct hantro_vp9_frame_info -+ * -+ * @valid: frame info valid flag -+ * @frame_context_idx: index of frame context -+ * @reference_mode: inter prediction type -+ * @tx_mode: transform mode -+ * @interpolation_filter: filter selection for inter prediction -+ * @flags: frame flags -+ * @timestamp: frame timestamp -+ */ -+struct hantro_vp9_frame_info { -+ u32 valid : 1; -+ u32 frame_context_idx : 2; -+ u32 reference_mode : 2; -+ u32 tx_mode : 3; -+ u32 interpolation_filter : 3; -+ u32 flags; -+ u64 timestamp; -+}; -+ -+#define MAX_SB_COLS 64 -+#define MAX_SB_ROWS 34 -+ -+/** -+ * struct hantro_vp9_dec_hw_ctx -+ * -+ * @tile_edge: auxiliary DMA buffer for tile edge processing -+ * @segment_map: auxiliary DMA buffer for segment map -+ * @misc: auxiliary DMA buffer for tile info, probabilities and hw counters -+ * @cnts: vp9 library struct for abstracting hw counters access -+ * @probability_tables: VP9 probability tables implied by the spec -+ * @frame_context: VP9 frame contexts -+ * @cur: current frame information -+ * @last: last frame information -+ * @bsd_ctrl_offset: bsd offset into tile_edge -+ * @segment_map_size: size of segment map -+ * @ctx_counters_offset: hw counters offset into misc -+ * @tile_info_offset: tile info offset into misc -+ * @tile_r_info: per-tile information array -+ * @tile_c_info: per-tile information array -+ * @last_tile_r: last number of tile rows -+ * @last_tile_c: last number of tile cols -+ * @last_sbs_r: last number of superblock rows -+ * @last_sbs_c: last number of superblock cols -+ * @active_segment: number of active segment (alternating between 0 and 1) -+ * @feature_enabled: segmentation feature enabled flags -+ * @feature_data: segmentation feature data -+ */ -+struct hantro_vp9_dec_hw_ctx { -+ struct hantro_aux_buf tile_edge; -+ struct hantro_aux_buf segment_map; -+ struct hantro_aux_buf misc; -+ struct v4l2_vp9_frame_symbol_counts cnts; -+ struct v4l2_vp9_frame_context probability_tables; -+ struct v4l2_vp9_frame_context frame_context[4]; -+ struct hantro_vp9_frame_info cur; -+ struct hantro_vp9_frame_info last; -+ -+ unsigned int bsd_ctrl_offset; -+ unsigned int segment_map_size; -+ unsigned int ctx_counters_offset; -+ unsigned int tile_info_offset; -+ -+ unsigned short tile_r_info[MAX_SB_ROWS]; -+ unsigned short tile_c_info[MAX_SB_COLS]; -+ unsigned int last_tile_r; -+ unsigned int last_tile_c; -+ unsigned int last_sbs_r; -+ unsigned int last_sbs_c; -+ -+ unsigned int active_segment; -+ u8 feature_enabled[8]; -+ s16 feature_data[8][4]; -+}; -+ - /** - * struct hantro_postproc_ctx - * -@@ -271,6 +348,24 @@ void hantro_hevc_ref_remove_unused(struct hantro_ctx *ctx); - size_t hantro_hevc_chroma_offset(const struct v4l2_ctrl_hevc_sps *sps); - size_t hantro_hevc_motion_vectors_offset(const struct v4l2_ctrl_hevc_sps *sps); - -+static inline unsigned short hantro_vp9_num_sbs(unsigned short dimension) -+{ -+ return (dimension + 63) / 64; -+} -+ -+static inline size_t -+hantro_vp9_mv_size(unsigned int width, unsigned int height) -+{ -+ int num_ctbs; -+ -+ /* -+ * There can be up to (CTBs x 64) number of blocks, -+ * and the motion vector for each block needs 16 bytes. -+ */ -+ num_ctbs = hantro_vp9_num_sbs(width) * hantro_vp9_num_sbs(height); -+ return (num_ctbs * 64) * 16; -+} -+ - static inline size_t - hantro_h264_mv_size(unsigned int width, unsigned int height) - { -@@ -312,6 +407,10 @@ void hantro_vp8_dec_exit(struct hantro_ctx *ctx); - void hantro_vp8_prob_update(struct hantro_ctx *ctx, - const struct v4l2_ctrl_vp8_frame *hdr); - -+int hantro_g2_vp9_dec_run(struct hantro_ctx *ctx); -+void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx); -+int hantro_vp9_dec_init(struct hantro_ctx *ctx); -+void hantro_vp9_dec_exit(struct hantro_ctx *ctx); - void hantro_g2_check_idle(struct hantro_dev *vpu); - - #endif /* HANTRO_HW_H_ */ -diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c -index d1f060c55fed..e4b0645ba6fc 100644 ---- a/drivers/staging/media/hantro/hantro_v4l2.c -+++ b/drivers/staging/media/hantro/hantro_v4l2.c -@@ -299,6 +299,11 @@ static int hantro_try_fmt(const struct hantro_ctx *ctx, - pix_mp->plane_fmt[0].sizeimage += - hantro_h264_mv_size(pix_mp->width, - pix_mp->height); -+ else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME && -+ !hantro_needs_postproc(ctx, fmt)) -+ pix_mp->plane_fmt[0].sizeimage += -+ hantro_vp9_mv_size(pix_mp->width, -+ pix_mp->height); - } else if (!pix_mp->plane_fmt[0].sizeimage) { - /* - * For coded formats the application can specify -@@ -407,6 +412,7 @@ hantro_update_requires_request(struct hantro_ctx *ctx, u32 fourcc) - case V4L2_PIX_FMT_VP8_FRAME: - case V4L2_PIX_FMT_H264_SLICE: - case V4L2_PIX_FMT_HEVC_SLICE: -+ case V4L2_PIX_FMT_VP9_FRAME: - ctx->fh.m2m_ctx->out_q_ctx.q.requires_requests = true; - break; - default: -diff --git a/drivers/staging/media/hantro/hantro_vp9.c b/drivers/staging/media/hantro/hantro_vp9.c -new file mode 100644 -index 000000000000..566cd376c097 ---- /dev/null -+++ b/drivers/staging/media/hantro/hantro_vp9.c -@@ -0,0 +1,240 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Hantro VP9 codec driver -+ * -+ * Copyright (C) 2021 Collabora Ltd. -+ */ -+ -+#include -+#include -+ -+#include "hantro.h" -+#include "hantro_hw.h" -+#include "hantro_vp9.h" -+ -+#define POW2(x) (1 << (x)) -+ -+#define MAX_LOG2_TILE_COLUMNS 6 -+#define MAX_NUM_TILE_COLS POW2(MAX_LOG2_TILE_COLUMNS) -+#define MAX_TILE_COLS 20 -+#define MAX_TILE_ROWS 22 -+ -+static size_t hantro_vp9_tile_filter_size(unsigned int height) -+{ -+ u32 h, height32, size; -+ -+ h = roundup(height, 8); -+ -+ height32 = roundup(h, 64); -+ size = 24 * height32 * (MAX_NUM_TILE_COLS - 1); /* luma: 8, chroma: 8 + 8 */ -+ -+ return size; -+} -+ -+static size_t hantro_vp9_bsd_control_size(unsigned int height) -+{ -+ u32 h, height32; -+ -+ h = roundup(height, 8); -+ height32 = roundup(h, 64); -+ -+ return 16 * (height32 / 4) * (MAX_NUM_TILE_COLS - 1); -+} -+ -+static size_t hantro_vp9_segment_map_size(unsigned int width, unsigned int height) -+{ -+ u32 w, h; -+ int num_ctbs; -+ -+ w = roundup(width, 8); -+ h = roundup(height, 8); -+ num_ctbs = ((w + 63) / 64) * ((h + 63) / 64); -+ -+ return num_ctbs * 32; -+} -+ -+static inline size_t hantro_vp9_prob_tab_size(void) -+{ -+ return roundup(sizeof(struct hantro_g2_all_probs), 16); -+} -+ -+static inline size_t hantro_vp9_count_tab_size(void) -+{ -+ return roundup(sizeof(struct symbol_counts), 16); -+} -+ -+static inline size_t hantro_vp9_tile_info_size(void) -+{ -+ return roundup((MAX_TILE_COLS * MAX_TILE_ROWS * 4 * sizeof(u16) + 15 + 16) & ~0xf, 16); -+} -+ -+static void *get_coeffs_arr(struct symbol_counts *cnts, int i, int j, int k, int l, int m) -+{ -+ if (i == 0) -+ return &cnts->count_coeffs[j][k][l][m]; -+ -+ if (i == 1) -+ return &cnts->count_coeffs8x8[j][k][l][m]; -+ -+ if (i == 2) -+ return &cnts->count_coeffs16x16[j][k][l][m]; -+ -+ if (i == 3) -+ return &cnts->count_coeffs32x32[j][k][l][m]; -+ -+ return NULL; -+} -+ -+static void *get_eobs1(struct symbol_counts *cnts, int i, int j, int k, int l, int m) -+{ -+ if (i == 0) -+ return &cnts->count_coeffs[j][k][l][m][3]; -+ -+ if (i == 1) -+ return &cnts->count_coeffs8x8[j][k][l][m][3]; -+ -+ if (i == 2) -+ return &cnts->count_coeffs16x16[j][k][l][m][3]; -+ -+ if (i == 3) -+ return &cnts->count_coeffs32x32[j][k][l][m][3]; -+ -+ return NULL; -+} -+ -+#define INNER_LOOP \ -+ do { \ -+ for (m = 0; m < ARRAY_SIZE(vp9_ctx->cnts.coeff[i][0][0][0]); ++m) { \ -+ vp9_ctx->cnts.coeff[i][j][k][l][m] = \ -+ get_coeffs_arr(cnts, i, j, k, l, m); \ -+ vp9_ctx->cnts.eob[i][j][k][l][m][0] = \ -+ &cnts->count_eobs[i][j][k][l][m]; \ -+ vp9_ctx->cnts.eob[i][j][k][l][m][1] = \ -+ get_eobs1(cnts, i, j, k, l, m); \ -+ } \ -+ } while (0) -+ -+static void init_v4l2_vp9_count_tbl(struct hantro_ctx *ctx) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ struct symbol_counts *cnts = vp9_ctx->misc.cpu + vp9_ctx->ctx_counters_offset; -+ int i, j, k, l, m; -+ -+ vp9_ctx->cnts.partition = &cnts->partition_counts; -+ vp9_ctx->cnts.skip = &cnts->mbskip_count; -+ vp9_ctx->cnts.intra_inter = &cnts->intra_inter_count; -+ vp9_ctx->cnts.tx32p = &cnts->tx32x32_count; -+ /* -+ * g2 hardware uses tx16x16_count[2][3], while the api -+ * expects tx16p[2][4], so this must be explicitly copied -+ * into vp9_ctx->cnts.tx16p when passing the data to the -+ * vp9 library function -+ */ -+ vp9_ctx->cnts.tx8p = &cnts->tx8x8_count; -+ -+ vp9_ctx->cnts.y_mode = &cnts->sb_ymode_counts; -+ vp9_ctx->cnts.uv_mode = &cnts->uv_mode_counts; -+ vp9_ctx->cnts.comp = &cnts->comp_inter_count; -+ vp9_ctx->cnts.comp_ref = &cnts->comp_ref_count; -+ vp9_ctx->cnts.single_ref = &cnts->single_ref_count; -+ vp9_ctx->cnts.filter = &cnts->switchable_interp_counts; -+ vp9_ctx->cnts.mv_joint = &cnts->mv_counts.joints; -+ vp9_ctx->cnts.sign = &cnts->mv_counts.sign; -+ vp9_ctx->cnts.classes = &cnts->mv_counts.classes; -+ vp9_ctx->cnts.class0 = &cnts->mv_counts.class0; -+ vp9_ctx->cnts.bits = &cnts->mv_counts.bits; -+ vp9_ctx->cnts.class0_fp = &cnts->mv_counts.class0_fp; -+ vp9_ctx->cnts.fp = &cnts->mv_counts.fp; -+ vp9_ctx->cnts.class0_hp = &cnts->mv_counts.class0_hp; -+ vp9_ctx->cnts.hp = &cnts->mv_counts.hp; -+ -+ for (i = 0; i < ARRAY_SIZE(vp9_ctx->cnts.coeff); ++i) -+ for (j = 0; j < ARRAY_SIZE(vp9_ctx->cnts.coeff[i]); ++j) -+ for (k = 0; k < ARRAY_SIZE(vp9_ctx->cnts.coeff[i][0]); ++k) -+ for (l = 0; l < ARRAY_SIZE(vp9_ctx->cnts.coeff[i][0][0]); ++l) -+ INNER_LOOP; -+} -+ -+int hantro_vp9_dec_init(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ const struct hantro_variant *variant = vpu->variant; -+ struct hantro_vp9_dec_hw_ctx *vp9_dec = &ctx->vp9_dec; -+ struct hantro_aux_buf *tile_edge = &vp9_dec->tile_edge; -+ struct hantro_aux_buf *segment_map = &vp9_dec->segment_map; -+ struct hantro_aux_buf *misc = &vp9_dec->misc; -+ u32 i, max_width, max_height, size; -+ -+ if (variant->num_dec_fmts < 1) -+ return -EINVAL; -+ -+ for (i = 0; i < variant->num_dec_fmts; ++i) -+ if (variant->dec_fmts[i].fourcc == V4L2_PIX_FMT_VP9_FRAME) -+ break; -+ -+ if (i == variant->num_dec_fmts) -+ return -EINVAL; -+ -+ max_width = vpu->variant->dec_fmts[i].frmsize.max_width; -+ max_height = vpu->variant->dec_fmts[i].frmsize.max_height; -+ -+ size = hantro_vp9_tile_filter_size(max_height); -+ vp9_dec->bsd_ctrl_offset = size; -+ size += hantro_vp9_bsd_control_size(max_height); -+ -+ tile_edge->cpu = dma_alloc_coherent(vpu->dev, size, &tile_edge->dma, GFP_KERNEL); -+ if (!tile_edge->cpu) -+ return -ENOMEM; -+ -+ tile_edge->size = size; -+ memset(tile_edge->cpu, 0, size); -+ -+ size = hantro_vp9_segment_map_size(max_width, max_height); -+ vp9_dec->segment_map_size = size; -+ size *= 2; /* we need two areas of this size, used alternately */ -+ -+ segment_map->cpu = dma_alloc_coherent(vpu->dev, size, &segment_map->dma, GFP_KERNEL); -+ if (!segment_map->cpu) -+ goto err_segment_map; -+ -+ segment_map->size = size; -+ memset(segment_map->cpu, 0, size); -+ -+ size = hantro_vp9_prob_tab_size(); -+ vp9_dec->ctx_counters_offset = size; -+ size += hantro_vp9_count_tab_size(); -+ vp9_dec->tile_info_offset = size; -+ size += hantro_vp9_tile_info_size(); -+ -+ misc->cpu = dma_alloc_coherent(vpu->dev, size, &misc->dma, GFP_KERNEL); -+ if (!misc->cpu) -+ goto err_misc; -+ -+ misc->size = size; -+ memset(misc->cpu, 0, size); -+ -+ init_v4l2_vp9_count_tbl(ctx); -+ -+ return 0; -+ -+err_misc: -+ dma_free_coherent(vpu->dev, segment_map->size, segment_map->cpu, segment_map->dma); -+ -+err_segment_map: -+ dma_free_coherent(vpu->dev, tile_edge->size, tile_edge->cpu, tile_edge->dma); -+ -+ return -ENOMEM; -+} -+ -+void hantro_vp9_dec_exit(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ struct hantro_vp9_dec_hw_ctx *vp9_dec = &ctx->vp9_dec; -+ struct hantro_aux_buf *tile_edge = &vp9_dec->tile_edge; -+ struct hantro_aux_buf *segment_map = &vp9_dec->segment_map; -+ struct hantro_aux_buf *misc = &vp9_dec->misc; -+ -+ dma_free_coherent(vpu->dev, misc->size, misc->cpu, misc->dma); -+ dma_free_coherent(vpu->dev, segment_map->size, segment_map->cpu, segment_map->dma); -+ dma_free_coherent(vpu->dev, tile_edge->size, tile_edge->cpu, tile_edge->dma); -+} -diff --git a/drivers/staging/media/hantro/hantro_vp9.h b/drivers/staging/media/hantro/hantro_vp9.h -new file mode 100644 -index 000000000000..26b69275f098 ---- /dev/null -+++ b/drivers/staging/media/hantro/hantro_vp9.h -@@ -0,0 +1,102 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Hantro VP9 codec driver -+ * -+ * Copyright (C) 2021 Collabora Ltd. -+ */ -+ -+struct hantro_g2_mv_probs { -+ u8 joint[3]; -+ u8 sign[2]; -+ u8 class0_bit[2][1]; -+ u8 fr[2][3]; -+ u8 class0_hp[2]; -+ u8 hp[2]; -+ u8 classes[2][10]; -+ u8 class0_fr[2][2][3]; -+ u8 bits[2][10]; -+}; -+ -+struct hantro_g2_probs { -+ u8 inter_mode[7][4]; -+ u8 is_inter[4]; -+ u8 uv_mode[10][8]; -+ u8 tx8[2][1]; -+ u8 tx16[2][2]; -+ u8 tx32[2][3]; -+ u8 y_mode_tail[4][1]; -+ u8 y_mode[4][8]; -+ u8 partition[2][16][4]; /* [keyframe][][], [inter][][] */ -+ u8 uv_mode_tail[10][1]; -+ u8 interp_filter[4][2]; -+ u8 comp_mode[5]; -+ u8 skip[3]; -+ -+ u8 pad1[1]; -+ -+ struct hantro_g2_mv_probs mv; -+ -+ u8 single_ref[5][2]; -+ u8 comp_ref[5]; -+ -+ u8 pad2[17]; -+ -+ u8 coef[4][2][2][6][6][4]; -+}; -+ -+struct hantro_g2_all_probs { -+ u8 kf_y_mode_prob[10][10][8]; -+ -+ u8 kf_y_mode_prob_tail[10][10][1]; -+ u8 ref_pred_probs[3]; -+ u8 mb_segment_tree_probs[7]; -+ u8 segment_pred_probs[3]; -+ u8 ref_scores[4]; -+ u8 prob_comppred[2]; -+ -+ u8 pad1[9]; -+ -+ u8 kf_uv_mode_prob[10][8]; -+ u8 kf_uv_mode_prob_tail[10][1]; -+ -+ u8 pad2[6]; -+ -+ struct hantro_g2_probs probs; -+}; -+ -+struct mv_counts { -+ u32 joints[4]; -+ u32 sign[2][2]; -+ u32 classes[2][11]; -+ u32 class0[2][2]; -+ u32 bits[2][10][2]; -+ u32 class0_fp[2][2][4]; -+ u32 fp[2][4]; -+ u32 class0_hp[2][2]; -+ u32 hp[2][2]; -+}; -+ -+struct symbol_counts { -+ u32 inter_mode_counts[7][3][2]; -+ u32 sb_ymode_counts[4][10]; -+ u32 uv_mode_counts[10][10]; -+ u32 partition_counts[16][4]; -+ u32 switchable_interp_counts[4][3]; -+ u32 intra_inter_count[4][2]; -+ u32 comp_inter_count[5][2]; -+ u32 single_ref_count[5][2][2]; -+ u32 comp_ref_count[5][2]; -+ u32 tx32x32_count[2][4]; -+ u32 tx16x16_count[2][3]; -+ u32 tx8x8_count[2][2]; -+ u32 mbskip_count[3][2]; -+ -+ struct mv_counts mv_counts; -+ -+ u32 count_coeffs[2][2][6][6][4]; -+ u32 count_coeffs8x8[2][2][6][6][4]; -+ u32 count_coeffs16x16[2][2][6][6][4]; -+ u32 count_coeffs32x32[2][2][6][6][4]; -+ -+ u32 count_eobs[4][2][2][6][6]; -+}; -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index a40b161e5956..455a107ffb02 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -150,6 +150,19 @@ static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = { - .step_height = MB_DIM, - }, - }, -+ { -+ .fourcc = V4L2_PIX_FMT_VP9_FRAME, -+ .codec_mode = HANTRO_MODE_VP9_DEC, -+ .max_depth = 2, -+ .frmsize = { -+ .min_width = 48, -+ .max_width = 3840, -+ .step_width = MB_DIM, -+ .min_height = 48, -+ .max_height = 2160, -+ .step_height = MB_DIM, -+ }, -+ }, - }; - - static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id) -@@ -241,6 +254,13 @@ static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = { - .init = hantro_hevc_dec_init, - .exit = hantro_hevc_dec_exit, - }, -+ [HANTRO_MODE_VP9_DEC] = { -+ .run = hantro_g2_vp9_dec_run, -+ .done = hantro_g2_vp9_dec_done, -+ .reset = imx8m_vpu_g2_reset, -+ .init = hantro_vp9_dec_init, -+ .exit = hantro_vp9_dec_exit, -+ }, - }; - - /* -@@ -281,7 +301,7 @@ const struct hantro_variant imx8mq_vpu_g2_variant = { - .dec_offset = 0x0, - .dec_fmts = imx8m_vpu_g2_dec_fmts, - .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_g2_dec_fmts), -- .codec = HANTRO_HEVC_DECODER, -+ .codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER, - .codec_ops = imx8mq_vpu_g2_codec_ops, - .init = imx8mq_vpu_hw_init, - .runtime_resume = imx8mq_runtime_resume, diff --git a/projects/Allwinner/patches/linux/0077-media-hantro-Staticize-a-struct-in-postprocessor-cod.patch b/projects/Allwinner/patches/linux/0077-media-hantro-Staticize-a-struct-in-postprocessor-cod.patch deleted file mode 100644 index b4c6db8cca..0000000000 --- a/projects/Allwinner/patches/linux/0077-media-hantro-Staticize-a-struct-in-postprocessor-cod.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:41 +0100 -Subject: [PATCH] media: hantro: Staticize a struct in postprocessor code - -The struct is not used outside this file, so it can be static. - -Signed-off-by: Andrzej Pietrasiewicz -Reviewed-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/hantro_postproc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index 4549aec08feb..89de43021779 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -33,7 +33,7 @@ - #define VPU_PP_OUT_RGB 0x0 - #define VPU_PP_OUT_YUYV 0x3 - --const struct hantro_postproc_regs hantro_g1_postproc_regs = { -+static const struct hantro_postproc_regs hantro_g1_postproc_regs = { - .pipeline_en = {G1_REG_PP_INTERRUPT, 1, 0x1}, - .max_burst = {G1_REG_PP_DEV_CONFIG, 0, 0x1f}, - .clk_gate = {G1_REG_PP_DEV_CONFIG, 1, 0x1}, diff --git a/projects/Allwinner/patches/linux/0078-media-hantro-Support-NV12-on-the-G2-core.patch b/projects/Allwinner/patches/linux/0078-media-hantro-Support-NV12-on-the-G2-core.patch deleted file mode 100644 index 9c7fc3930f..0000000000 --- a/projects/Allwinner/patches/linux/0078-media-hantro-Support-NV12-on-the-G2-core.patch +++ /dev/null @@ -1,161 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:42 +0100 -Subject: [PATCH] media: hantro: Support NV12 on the G2 core - -The G2 decoder block produces NV12 4x4 tiled format (NV12_4L4). -Enable the G2 post-processor block, in order to produce regular NV12. - -The logic in hantro_postproc.c is leveraged to take care of allocating -the extra buffers and configure the post-processor, which is -significantly simpler than the one on the G1. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Hans Verkuil ---- - .../staging/media/hantro/hantro_g2_vp9_dec.c | 6 ++-- - drivers/staging/media/hantro/hantro_hw.h | 1 + - .../staging/media/hantro/hantro_postproc.c | 31 +++++++++++++++++++ - drivers/staging/media/hantro/imx8m_vpu_hw.c | 11 +++++++ - 4 files changed, 46 insertions(+), 3 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -index fc55b03a8004..e04242d10fa2 100644 ---- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -@@ -152,7 +152,7 @@ static void config_output(struct hantro_ctx *ctx, - hantro_reg_write(ctx->dev, &g2_out_dis, 0); - hantro_reg_write(ctx->dev, &g2_output_format, 0); - -- luma_addr = vb2_dma_contig_plane_dma_addr(&dst->base.vb.vb2_buf, 0); -+ luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf); - hantro_write_addr(ctx->dev, G2_OUT_LUMA_ADDR, luma_addr); - - chroma_addr = luma_addr + chroma_offset(ctx, dec_params); -@@ -191,7 +191,7 @@ static void config_ref(struct hantro_ctx *ctx, - hantro_reg_write(ctx->dev, &ref_reg->hor_scale, (refw << 14) / dst->vp9.width); - hantro_reg_write(ctx->dev, &ref_reg->ver_scale, (refh << 14) / dst->vp9.height); - -- luma_addr = vb2_dma_contig_plane_dma_addr(&buf->base.vb.vb2_buf, 0); -+ luma_addr = hantro_get_dec_buf_addr(ctx, &buf->base.vb.vb2_buf); - hantro_write_addr(ctx->dev, ref_reg->y_base, luma_addr); - - chroma_addr = luma_addr + chroma_offset(ctx, dec_params); -@@ -236,7 +236,7 @@ static void config_ref_registers(struct hantro_ctx *ctx, - config_ref(ctx, dst, &ref_regs[1], dec_params, dec_params->golden_frame_ts); - config_ref(ctx, dst, &ref_regs[2], dec_params, dec_params->alt_frame_ts); - -- mv_addr = vb2_dma_contig_plane_dma_addr(&mv_ref->base.vb.vb2_buf, 0) + -+ mv_addr = hantro_get_dec_buf_addr(ctx, &mv_ref->base.vb.vb2_buf) + - mv_offset(ctx, dec_params); - hantro_write_addr(ctx->dev, G2_REF_MV_ADDR(0), mv_addr); - -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index fe5b51046d33..dbe51303724b 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -310,6 +310,7 @@ extern const struct hantro_variant rk3399_vpu_variant; - extern const struct hantro_variant sama5d4_vdec_variant; - - extern const struct hantro_postproc_ops hantro_g1_postproc_ops; -+extern const struct hantro_postproc_ops hantro_g2_postproc_ops; - - extern const u32 hantro_vp8_dec_mc_filter[8][6]; - -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index 89de43021779..a7774ad4c445 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -11,6 +11,7 @@ - #include "hantro.h" - #include "hantro_hw.h" - #include "hantro_g1_regs.h" -+#include "hantro_g2_regs.h" - - #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \ - { \ -@@ -99,6 +100,21 @@ static void hantro_postproc_g1_enable(struct hantro_ctx *ctx) - HANTRO_PP_REG_WRITE(vpu, display_width, ctx->dst_fmt.width); - } - -+static void hantro_postproc_g2_enable(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ struct vb2_v4l2_buffer *dst_buf; -+ size_t chroma_offset = ctx->dst_fmt.width * ctx->dst_fmt.height; -+ dma_addr_t dst_dma; -+ -+ dst_buf = hantro_get_dst_buf(ctx); -+ dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ -+ hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma); -+ hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + chroma_offset); -+ hantro_reg_write(vpu, &g2_out_rs_e, 1); -+} -+ - void hantro_postproc_free(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -@@ -127,6 +143,9 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx) - if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE) - buf_size += hantro_h264_mv_size(ctx->dst_fmt.width, - ctx->dst_fmt.height); -+ else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME) -+ buf_size += hantro_vp9_mv_size(ctx->dst_fmt.width, -+ ctx->dst_fmt.height); - - for (i = 0; i < num_buffers; ++i) { - struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i]; -@@ -152,6 +171,13 @@ static void hantro_postproc_g1_disable(struct hantro_ctx *ctx) - HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0); - } - -+static void hantro_postproc_g2_disable(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ -+ hantro_reg_write(vpu, &g2_out_rs_e, 0); -+} -+ - void hantro_postproc_disable(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -@@ -172,3 +198,8 @@ const struct hantro_postproc_ops hantro_g1_postproc_ops = { - .enable = hantro_postproc_g1_enable, - .disable = hantro_postproc_g1_disable, - }; -+ -+const struct hantro_postproc_ops hantro_g2_postproc_ops = { -+ .enable = hantro_postproc_g2_enable, -+ .disable = hantro_postproc_g2_disable, -+}; -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index 455a107ffb02..1a43f6fceef9 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -132,6 +132,14 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = { - }, - }; - -+static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_NV12, -+ .codec_mode = HANTRO_MODE_NONE, -+ .postprocessed = true, -+ }, -+}; -+ - static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_NV12_4L4, -@@ -301,6 +309,9 @@ const struct hantro_variant imx8mq_vpu_g2_variant = { - .dec_offset = 0x0, - .dec_fmts = imx8m_vpu_g2_dec_fmts, - .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_g2_dec_fmts), -+ .postproc_fmts = imx8m_vpu_g2_postproc_fmts, -+ .num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_g2_postproc_fmts), -+ .postproc_ops = &hantro_g2_postproc_ops, - .codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER, - .codec_ops = imx8mq_vpu_g2_codec_ops, - .init = imx8mq_vpu_hw_init, diff --git a/projects/Allwinner/patches/linux/0080-media-hantro-add-support-for-reset-lines.patch b/projects/Allwinner/patches/linux/0080-media-hantro-add-support-for-reset-lines.patch deleted file mode 100644 index 116ec8c526..0000000000 --- a/projects/Allwinner/patches/linux/0080-media-hantro-add-support-for-reset-lines.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 7 Aug 2021 17:29:11 +0200 -Subject: [PATCH] media: hantro: add support for reset lines - -Some SoCs like Allwinner H6 use reset lines for resetting Hantro G2. Add -support for them. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/hantro/hantro.h | 3 +++ - drivers/staging/media/hantro/hantro_drv.c | 15 ++++++++++++++- - 2 files changed, 17 insertions(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index 7da23f7f207a..33eb3e092cc1 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -171,6 +172,7 @@ hantro_vdev_to_func(struct video_device *vdev) - * @dev: Pointer to device for convenient logging using - * dev_ macros. - * @clocks: Array of clock handles. -+ * @resets: Array of reset handles. - * @reg_bases: Mapped addresses of VPU registers. - * @enc_base: Mapped address of VPU encoder register for convenience. - * @dec_base: Mapped address of VPU decoder register for convenience. -@@ -190,6 +192,7 @@ struct hantro_dev { - struct platform_device *pdev; - struct device *dev; - struct clk_bulk_data *clocks; -+ struct reset_control *resets; - void __iomem **reg_bases; - void __iomem *enc_base; - void __iomem *dec_base; -diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c -index 3d3107a39dae..770f4ce71d29 100644 ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -905,6 +905,10 @@ static int hantro_probe(struct platform_device *pdev) - return PTR_ERR(vpu->clocks[0].clk); - } - -+ vpu->resets = devm_reset_control_array_get(&pdev->dev, false, true); -+ if (IS_ERR(vpu->resets)) -+ return PTR_ERR(vpu->resets); -+ - num_bases = vpu->variant->num_regs ?: 1; - vpu->reg_bases = devm_kcalloc(&pdev->dev, num_bases, - sizeof(*vpu->reg_bases), GFP_KERNEL); -@@ -978,10 +982,16 @@ static int hantro_probe(struct platform_device *pdev) - pm_runtime_use_autosuspend(vpu->dev); - pm_runtime_enable(vpu->dev); - -+ ret = reset_control_deassert(vpu->resets); -+ if (ret) { -+ dev_err(&pdev->dev, "Failed to deassert resets\n"); -+ goto err_pm_disable; -+ } -+ - ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks); - if (ret) { - dev_err(&pdev->dev, "Failed to prepare clocks\n"); -- goto err_pm_disable; -+ goto err_rst_assert; - } - - ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev); -@@ -1037,6 +1047,8 @@ static int hantro_probe(struct platform_device *pdev) - v4l2_device_unregister(&vpu->v4l2_dev); - err_clk_unprepare: - clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); -+err_rst_assert: -+ reset_control_assert(vpu->resets); - err_pm_disable: - pm_runtime_dont_use_autosuspend(vpu->dev); - pm_runtime_disable(vpu->dev); -@@ -1056,6 +1068,7 @@ static int hantro_remove(struct platform_device *pdev) - v4l2_m2m_release(vpu->m2m_dev); - v4l2_device_unregister(&vpu->v4l2_dev); - clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); -+ reset_control_assert(vpu->resets); - pm_runtime_dont_use_autosuspend(vpu->dev); - pm_runtime_disable(vpu->dev); - return 0; diff --git a/projects/Allwinner/patches/linux/0081-media-hantro-vp9-use-double-buffering-if-needed.patch b/projects/Allwinner/patches/linux/0081-media-hantro-vp9-use-double-buffering-if-needed.patch deleted file mode 100644 index 15f258c253..0000000000 --- a/projects/Allwinner/patches/linux/0081-media-hantro-vp9-use-double-buffering-if-needed.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 21 Nov 2021 20:39:11 +0100 -Subject: [PATCH] media: hantro: vp9: use double buffering if needed - -Some G2 variants need double buffering to be enabled in order to work -correctly, like that found in Allwinner H6 SoC. - -Add platform quirk for that. - -Reviewed-by: Andrzej Pietrasiewicz -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/hantro/hantro.h | 2 ++ - drivers/staging/media/hantro/hantro_g2_regs.h | 1 + - drivers/staging/media/hantro/hantro_g2_vp9_dec.c | 2 ++ - 3 files changed, 5 insertions(+) - -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index 33eb3e092cc1..d03824fa3222 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -73,6 +73,7 @@ struct hantro_irq { - * @num_clocks: number of clocks in the array - * @reg_names: array of register range names - * @num_regs: number of register range names in the array -+ * @double_buffer: core needs double buffering - */ - struct hantro_variant { - unsigned int enc_offset; -@@ -94,6 +95,7 @@ struct hantro_variant { - int num_clocks; - const char * const *reg_names; - int num_regs; -+ unsigned int double_buffer : 1; - }; - - /** -diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h -index 9c857dd1ad9b..15a391a4650e 100644 ---- a/drivers/staging/media/hantro/hantro_g2_regs.h -+++ b/drivers/staging/media/hantro/hantro_g2_regs.h -@@ -270,6 +270,7 @@ - #define g2_apf_threshold G2_DEC_REG(55, 0, 0xffff) - - #define g2_clk_gate_e G2_DEC_REG(58, 16, 0x1) -+#define g2_double_buffer_e G2_DEC_REG(58, 15, 0x1) - #define g2_buswidth G2_DEC_REG(58, 8, 0x7) - #define g2_max_burst G2_DEC_REG(58, 0, 0xff) - -diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -index e04242d10fa2..d4fc649a4da1 100644 ---- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -@@ -847,6 +847,8 @@ config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_p - hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1); - hantro_reg_write(ctx->dev, &g2_max_cb_size, 6); - hantro_reg_write(ctx->dev, &g2_min_cb_size, 3); -+ if (ctx->dev->variant->double_buffer) -+ hantro_reg_write(ctx->dev, &g2_double_buffer_e, 1); - - config_output(ctx, dst, dec_params); - diff --git a/projects/Allwinner/patches/linux/0082-media-hantro-vp9-add-support-for-legacy-register-set.patch b/projects/Allwinner/patches/linux/0082-media-hantro-vp9-add-support-for-legacy-register-set.patch deleted file mode 100644 index 0283b8f83e..0000000000 --- a/projects/Allwinner/patches/linux/0082-media-hantro-vp9-add-support-for-legacy-register-set.patch +++ /dev/null @@ -1,242 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 26 Sep 2021 19:47:03 +0200 -Subject: [PATCH] media: hantro: vp9: add support for legacy register set - -Some older G2 cores uses slightly different register set for HEVC and -VP9. Since vast majority of registers and logic is the same, it doesn't -make sense to introduce another drivers. - -Add legacy_regs quirk and implement only VP9 changes for now. HEVC -changes will be introduced later, if needed. - -Reviewed-by: Andrzej Pietrasiewicz -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/hantro/hantro.h | 2 + - drivers/staging/media/hantro/hantro_g2_regs.h | 16 ++++ - .../staging/media/hantro/hantro_g2_vp9_dec.c | 74 ++++++++++++++----- - 3 files changed, 75 insertions(+), 17 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index d03824fa3222..83ed25d9657b 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -74,6 +74,7 @@ struct hantro_irq { - * @reg_names: array of register range names - * @num_regs: number of register range names in the array - * @double_buffer: core needs double buffering -+ * @legacy_regs: core uses legacy register set - */ - struct hantro_variant { - unsigned int enc_offset; -@@ -96,6 +97,7 @@ struct hantro_variant { - const char * const *reg_names; - int num_regs; - unsigned int double_buffer : 1; -+ unsigned int legacy_regs : 1; - }; - - /** -diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h -index 15a391a4650e..b7c6f9877b9d 100644 ---- a/drivers/staging/media/hantro/hantro_g2_regs.h -+++ b/drivers/staging/media/hantro/hantro_g2_regs.h -@@ -36,7 +36,13 @@ - #define BUS_WIDTH_256 3 - - #define g2_strm_swap G2_DEC_REG(2, 28, 0xf) -+#define g2_strm_swap_old G2_DEC_REG(2, 27, 0x1f) -+#define g2_pic_swap G2_DEC_REG(2, 22, 0x1f) - #define g2_dirmv_swap G2_DEC_REG(2, 20, 0xf) -+#define g2_dirmv_swap_old G2_DEC_REG(2, 17, 0x1f) -+#define g2_tab0_swap_old G2_DEC_REG(2, 12, 0x1f) -+#define g2_tab1_swap_old G2_DEC_REG(2, 7, 0x1f) -+#define g2_tab2_swap_old G2_DEC_REG(2, 2, 0x1f) - - #define g2_mode G2_DEC_REG(3, 27, 0x1f) - #define g2_compress_swap G2_DEC_REG(3, 20, 0xf) -@@ -45,6 +51,8 @@ - #define g2_out_dis G2_DEC_REG(3, 15, 0x1) - #define g2_out_filtering_dis G2_DEC_REG(3, 14, 0x1) - #define g2_write_mvs_e G2_DEC_REG(3, 12, 0x1) -+#define g2_tab3_swap_old G2_DEC_REG(3, 7, 0x1f) -+#define g2_rscan_swap G2_DEC_REG(3, 2, 0x1f) - - #define g2_pic_width_in_cbs G2_DEC_REG(4, 19, 0x1fff) - #define g2_pic_height_in_cbs G2_DEC_REG(4, 6, 0x1fff) -@@ -58,6 +66,7 @@ - #define g2_tempor_mvp_e G2_DEC_REG(5, 11, 0x1) - #define g2_max_cu_qpd_depth G2_DEC_REG(5, 5, 0x3f) - #define g2_cu_qpd_e G2_DEC_REG(5, 4, 0x1) -+#define g2_pix_shift G2_DEC_REG(5, 0, 0xf) - - #define g2_stream_len G2_DEC_REG(6, 0, 0xffffffff) - -@@ -80,21 +89,28 @@ - - #define g2_const_intra_e G2_DEC_REG(8, 31, 0x1) - #define g2_filt_ctrl_pres G2_DEC_REG(8, 30, 0x1) -+#define g2_bit_depth_y G2_DEC_REG(8, 21, 0xf) -+#define g2_bit_depth_c G2_DEC_REG(8, 17, 0xf) - #define g2_idr_pic_e G2_DEC_REG(8, 16, 0x1) - #define g2_bit_depth_pcm_y G2_DEC_REG(8, 12, 0xf) - #define g2_bit_depth_pcm_c G2_DEC_REG(8, 8, 0xf) - #define g2_bit_depth_y_minus8 G2_DEC_REG(8, 6, 0x3) - #define g2_bit_depth_c_minus8 G2_DEC_REG(8, 4, 0x3) -+#define g2_rs_out_bit_depth G2_DEC_REG(8, 4, 0xf) - #define g2_output_8_bits G2_DEC_REG(8, 3, 0x1) - #define g2_output_format G2_DEC_REG(8, 0, 0x7) -+#define g2_pp_pix_shift G2_DEC_REG(8, 0, 0xf) - - #define g2_refidx1_active G2_DEC_REG(9, 19, 0x1f) - #define g2_refidx0_active G2_DEC_REG(9, 14, 0x1f) - #define g2_hdr_skip_length G2_DEC_REG(9, 0, 0x3fff) - - #define g2_start_code_e G2_DEC_REG(10, 31, 0x1) -+#define g2_init_qp_old G2_DEC_REG(10, 25, 0x3f) - #define g2_init_qp G2_DEC_REG(10, 24, 0x3f) -+#define g2_num_tile_cols_old G2_DEC_REG(10, 20, 0x1f) - #define g2_num_tile_cols G2_DEC_REG(10, 19, 0x1f) -+#define g2_num_tile_rows_old G2_DEC_REG(10, 15, 0x1f) - #define g2_num_tile_rows G2_DEC_REG(10, 14, 0x1f) - #define g2_tile_e G2_DEC_REG(10, 1, 0x1) - #define g2_entropy_sync_e G2_DEC_REG(10, 0, 0x1) -diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -index d4fc649a4da1..91c21b634fab 100644 ---- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -@@ -150,7 +150,8 @@ static void config_output(struct hantro_ctx *ctx, - dma_addr_t luma_addr, chroma_addr, mv_addr; - - hantro_reg_write(ctx->dev, &g2_out_dis, 0); -- hantro_reg_write(ctx->dev, &g2_output_format, 0); -+ if (!ctx->dev->variant->legacy_regs) -+ hantro_reg_write(ctx->dev, &g2_output_format, 0); - - luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf); - hantro_write_addr(ctx->dev, G2_OUT_LUMA_ADDR, luma_addr); -@@ -327,6 +328,7 @@ config_tiles(struct hantro_ctx *ctx, - struct hantro_aux_buf *tile_edge = &vp9_ctx->tile_edge; - dma_addr_t addr; - unsigned short *tile_mem; -+ unsigned int rows, cols; - - addr = misc->dma + vp9_ctx->tile_info_offset; - hantro_write_addr(ctx->dev, G2_TILE_SIZES_ADDR, addr); -@@ -344,17 +346,24 @@ config_tiles(struct hantro_ctx *ctx, - - fill_tile_info(ctx, tile_r, tile_c, sbs_r, sbs_c, tile_mem); - -+ cols = tile_c; -+ rows = tile_r; - hantro_reg_write(ctx->dev, &g2_tile_e, 1); -- hantro_reg_write(ctx->dev, &g2_num_tile_cols, tile_c); -- hantro_reg_write(ctx->dev, &g2_num_tile_rows, tile_r); -- - } else { - tile_mem[0] = hantro_vp9_num_sbs(dst->vp9.width); - tile_mem[1] = hantro_vp9_num_sbs(dst->vp9.height); - -+ cols = 1; -+ rows = 1; - hantro_reg_write(ctx->dev, &g2_tile_e, 0); -- hantro_reg_write(ctx->dev, &g2_num_tile_cols, 1); -- hantro_reg_write(ctx->dev, &g2_num_tile_rows, 1); -+ } -+ -+ if (ctx->dev->variant->legacy_regs) { -+ hantro_reg_write(ctx->dev, &g2_num_tile_cols_old, cols); -+ hantro_reg_write(ctx->dev, &g2_num_tile_rows_old, rows); -+ } else { -+ hantro_reg_write(ctx->dev, &g2_num_tile_cols, cols); -+ hantro_reg_write(ctx->dev, &g2_num_tile_rows, rows); - } - - /* provide aux buffers even if no tiles are used */ -@@ -505,8 +514,22 @@ static void config_picture_dimensions(struct hantro_ctx *ctx, struct hantro_deco - static void - config_bit_depth(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) - { -- hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8); -- hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8); -+ if (ctx->dev->variant->legacy_regs) { -+ u8 pp_shift = 0; -+ -+ hantro_reg_write(ctx->dev, &g2_bit_depth_y, dec_params->bit_depth); -+ hantro_reg_write(ctx->dev, &g2_bit_depth_c, dec_params->bit_depth); -+ hantro_reg_write(ctx->dev, &g2_rs_out_bit_depth, dec_params->bit_depth); -+ -+ if (dec_params->bit_depth > 8) -+ pp_shift = 16 - dec_params->bit_depth; -+ -+ hantro_reg_write(ctx->dev, &g2_pp_pix_shift, pp_shift); -+ hantro_reg_write(ctx->dev, &g2_pix_shift, 0); -+ } else { -+ hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8); -+ hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8); -+ } - } - - static inline bool is_lossless(const struct v4l2_vp9_quantization *quant) -@@ -784,9 +807,13 @@ config_source(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_para - + dec_params->compressed_header_size; - - stream_base = vb2_dma_contig_plane_dma_addr(&vb2_src->vb2_buf, 0); -- hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base); - - tmp_addr = stream_base + headres_size; -+ if (ctx->dev->variant->legacy_regs) -+ hantro_write_addr(ctx->dev, G2_STREAM_ADDR, (tmp_addr & ~0xf)); -+ else -+ hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base); -+ - start_bit = (tmp_addr & 0xf) * 8; - hantro_reg_write(ctx->dev, &g2_start_bit, start_bit); - -@@ -794,10 +821,12 @@ config_source(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_para - src_len += start_bit / 8 - headres_size; - hantro_reg_write(ctx->dev, &g2_stream_len, src_len); - -- tmp_addr &= ~0xf; -- hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base); -- src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0); -- hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len); -+ if (!ctx->dev->variant->legacy_regs) { -+ tmp_addr &= ~0xf; -+ hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base); -+ src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0); -+ hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len); -+ } - } - - static void -@@ -837,13 +866,24 @@ config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_p - - /* configure basic registers */ - hantro_reg_write(ctx->dev, &g2_mode, VP9_DEC_MODE); -- hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf); -- hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf); -- hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf); -+ if (!ctx->dev->variant->legacy_regs) { -+ hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf); -+ hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf); -+ hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf); -+ hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1); -+ } else { -+ hantro_reg_write(ctx->dev, &g2_strm_swap_old, 0x1f); -+ hantro_reg_write(ctx->dev, &g2_pic_swap, 0x10); -+ hantro_reg_write(ctx->dev, &g2_dirmv_swap_old, 0x10); -+ hantro_reg_write(ctx->dev, &g2_tab0_swap_old, 0x10); -+ hantro_reg_write(ctx->dev, &g2_tab1_swap_old, 0x10); -+ hantro_reg_write(ctx->dev, &g2_tab2_swap_old, 0x10); -+ hantro_reg_write(ctx->dev, &g2_tab3_swap_old, 0x10); -+ hantro_reg_write(ctx->dev, &g2_rscan_swap, 0x10); -+ } - hantro_reg_write(ctx->dev, &g2_buswidth, BUS_WIDTH_128); - hantro_reg_write(ctx->dev, &g2_max_burst, 16); - hantro_reg_write(ctx->dev, &g2_apf_threshold, 8); -- hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1); - hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1); - hantro_reg_write(ctx->dev, &g2_max_cb_size, 6); - hantro_reg_write(ctx->dev, &g2_min_cb_size, 3); diff --git a/projects/Allwinner/patches/linux/0083-media-hantro-move-postproc-enablement-for-old-cores.patch b/projects/Allwinner/patches/linux/0083-media-hantro-move-postproc-enablement-for-old-cores.patch deleted file mode 100644 index 6c5c6bf10c..0000000000 --- a/projects/Allwinner/patches/linux/0083-media-hantro-move-postproc-enablement-for-old-cores.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 22 Nov 2021 18:33:14 +0100 -Subject: [PATCH] media: hantro: move postproc enablement for old cores - -Older G2 cores, like that in Allwinner H6, seem to have issue with -latching postproc register values if this is first thing done in job. -Moving that to the end solves the issue. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/hantro/hantro.h | 2 ++ - drivers/staging/media/hantro/hantro_drv.c | 9 ++++++++- - 2 files changed, 10 insertions(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index 83ed25d9657b..06d0f3597694 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -75,6 +75,7 @@ struct hantro_irq { - * @num_regs: number of register range names in the array - * @double_buffer: core needs double buffering - * @legacy_regs: core uses legacy register set -+ * @late_postproc: postproc must be set up at the end of the job - */ - struct hantro_variant { - unsigned int enc_offset; -@@ -98,6 +99,7 @@ struct hantro_variant { - int num_regs; - unsigned int double_buffer : 1; - unsigned int legacy_regs : 1; -+ unsigned int late_postproc : 1; - }; - - /** -diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c -index 770f4ce71d29..33bf78be145b 100644 ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -130,7 +130,7 @@ void hantro_start_prepare_run(struct hantro_ctx *ctx) - v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req, - &ctx->ctrl_handler); - -- if (!ctx->is_encoder) { -+ if (!ctx->is_encoder && !ctx->dev->variant->late_postproc) { - if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt)) - hantro_postproc_enable(ctx); - else -@@ -142,6 +142,13 @@ void hantro_end_prepare_run(struct hantro_ctx *ctx) - { - struct vb2_v4l2_buffer *src_buf; - -+ if (!ctx->is_encoder && ctx->dev->variant->late_postproc) { -+ if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt)) -+ hantro_postproc_enable(ctx); -+ else -+ hantro_postproc_disable(ctx); -+ } -+ - src_buf = hantro_get_src_buf(ctx); - v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req, - &ctx->ctrl_handler); diff --git a/projects/Allwinner/patches/linux/0084-media-hantro-Convert-imx8m_vpu_g2_irq-to-helper.patch b/projects/Allwinner/patches/linux/0084-media-hantro-Convert-imx8m_vpu_g2_irq-to-helper.patch deleted file mode 100644 index 07bb28caac..0000000000 --- a/projects/Allwinner/patches/linux/0084-media-hantro-Convert-imx8m_vpu_g2_irq-to-helper.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 29 Nov 2021 19:02:17 +0100 -Subject: [PATCH] media: hantro: Convert imx8m_vpu_g2_irq to helper - -It turns out that imx8m_vpu_g2_irq() doesn't depend on any platform -specifics and can be used with other G2 platform drivers too. - -Move it to common code. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/hantro/hantro_g2.c | 18 ++++++++++++++++++ - drivers/staging/media/hantro/hantro_hw.h | 1 + - drivers/staging/media/hantro/imx8m_vpu_hw.c | 20 +------------------- - 3 files changed, 20 insertions(+), 19 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_g2.c b/drivers/staging/media/hantro/hantro_g2.c -index 6f3e1f797f83..ee5f14c5f8f2 100644 ---- a/drivers/staging/media/hantro/hantro_g2.c -+++ b/drivers/staging/media/hantro/hantro_g2.c -@@ -24,3 +24,21 @@ void hantro_g2_check_idle(struct hantro_dev *vpu) - } - } - } -+ -+irqreturn_t hantro_g2_irq(int irq, void *dev_id) -+{ -+ struct hantro_dev *vpu = dev_id; -+ enum vb2_buffer_state state; -+ u32 status; -+ -+ status = vdpu_read(vpu, G2_REG_INTERRUPT); -+ state = (status & G2_REG_INTERRUPT_DEC_RDY_INT) ? -+ VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; -+ -+ vdpu_write(vpu, 0, G2_REG_INTERRUPT); -+ vdpu_write(vpu, G2_REG_CONFIG_DEC_CLK_GATE_E, G2_REG_CONFIG); -+ -+ hantro_irq_done(vpu, state); -+ -+ return IRQ_HANDLED; -+} -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index dbe51303724b..c33b1f5df37b 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -413,5 +413,6 @@ void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx); - int hantro_vp9_dec_init(struct hantro_ctx *ctx); - void hantro_vp9_dec_exit(struct hantro_ctx *ctx); - void hantro_g2_check_idle(struct hantro_dev *vpu); -+irqreturn_t hantro_g2_irq(int irq, void *dev_id); - - #endif /* HANTRO_HW_H_ */ -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index 1a43f6fceef9..f5991b8e553a 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -191,24 +191,6 @@ static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id) - return IRQ_HANDLED; - } - --static irqreturn_t imx8m_vpu_g2_irq(int irq, void *dev_id) --{ -- struct hantro_dev *vpu = dev_id; -- enum vb2_buffer_state state; -- u32 status; -- -- status = vdpu_read(vpu, G2_REG_INTERRUPT); -- state = (status & G2_REG_INTERRUPT_DEC_RDY_INT) ? -- VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; -- -- vdpu_write(vpu, 0, G2_REG_INTERRUPT); -- vdpu_write(vpu, G2_REG_CONFIG_DEC_CLK_GATE_E, G2_REG_CONFIG); -- -- hantro_irq_done(vpu, state); -- -- return IRQ_HANDLED; --} -- - static int imx8mq_vpu_hw_init(struct hantro_dev *vpu) - { - vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1]; -@@ -280,7 +262,7 @@ static const struct hantro_irq imx8mq_irqs[] = { - }; - - static const struct hantro_irq imx8mq_g2_irqs[] = { -- { "g2", imx8m_vpu_g2_irq }, -+ { "g2", hantro_g2_irq }, - }; - - static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" }; diff --git a/projects/Allwinner/patches/linux/0085-media-hantro-Add-support-for-Allwinner-H6.patch b/projects/Allwinner/patches/linux/0085-media-hantro-Add-support-for-Allwinner-H6.patch deleted file mode 100644 index f27abb6def..0000000000 --- a/projects/Allwinner/patches/linux/0085-media-hantro-Add-support-for-Allwinner-H6.patch +++ /dev/null @@ -1,172 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Thu, 5 Aug 2021 20:43:03 +0200 -Subject: [PATCH] media: hantro: Add support for Allwinner H6 - -Allwinner H6 has a Hantro G2 core used for VP9 decoding. It's not clear -at this time if HEVC is also supported or not. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/hantro/Kconfig | 10 ++- - drivers/staging/media/hantro/Makefile | 3 + - drivers/staging/media/hantro/hantro_drv.c | 3 + - drivers/staging/media/hantro/hantro_hw.h | 1 + - drivers/staging/media/hantro/sunxi_vpu_hw.c | 86 +++++++++++++++++++++ - 5 files changed, 102 insertions(+), 1 deletion(-) - create mode 100644 drivers/staging/media/hantro/sunxi_vpu_hw.c - -diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig -index 00a57d88c92e..3c5d833322c8 100644 ---- a/drivers/staging/media/hantro/Kconfig -+++ b/drivers/staging/media/hantro/Kconfig -@@ -1,7 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0 - config VIDEO_HANTRO - tristate "Hantro VPU driver" -- depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || COMPILE_TEST -+ depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || ARCH_SUNXI || COMPILE_TEST - depends on VIDEO_DEV && VIDEO_V4L2 - select MEDIA_CONTROLLER - select MEDIA_CONTROLLER_REQUEST_API -@@ -40,3 +40,11 @@ config VIDEO_HANTRO_ROCKCHIP - default y - help - Enable support for RK3288, RK3328, and RK3399 SoCs. -+ -+config VIDEO_HANTRO_SUNXI -+ bool "Hantro VPU Allwinner support" -+ depends on VIDEO_HANTRO -+ depends on ARCH_SUNXI || COMPILE_TEST -+ default y -+ help -+ Enable support for H6 SoC. -diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile -index 28af0a1ee4bf..ebd5ede7bef7 100644 ---- a/drivers/staging/media/hantro/Makefile -+++ b/drivers/staging/media/hantro/Makefile -@@ -33,3 +33,6 @@ hantro-vpu-$(CONFIG_VIDEO_HANTRO_SAMA5D4) += \ - - hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \ - rockchip_vpu_hw.o -+ -+hantro-vpu-$(CONFIG_VIDEO_HANTRO_SUNXI) += \ -+ sunxi_vpu_hw.o -diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c -index 33bf78be145b..6a51f39dde56 100644 ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -620,6 +620,9 @@ static const struct of_device_id of_hantro_match[] = { - #endif - #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4 - { .compatible = "microchip,sama5d4-vdec", .data = &sama5d4_vdec_variant, }, -+#endif -+#ifdef CONFIG_VIDEO_HANTRO_SUNXI -+ { .compatible = "allwinner,sun50i-h6-vpu-g2", .data = &sunxi_vpu_variant, }, - #endif - { /* sentinel */ } - }; -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index c33b1f5df37b..c92a6ec4b187 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -308,6 +308,7 @@ extern const struct hantro_variant rk3288_vpu_variant; - extern const struct hantro_variant rk3328_vpu_variant; - extern const struct hantro_variant rk3399_vpu_variant; - extern const struct hantro_variant sama5d4_vdec_variant; -+extern const struct hantro_variant sunxi_vpu_variant; - - extern const struct hantro_postproc_ops hantro_g1_postproc_ops; - extern const struct hantro_postproc_ops hantro_g2_postproc_ops; -diff --git a/drivers/staging/media/hantro/sunxi_vpu_hw.c b/drivers/staging/media/hantro/sunxi_vpu_hw.c -new file mode 100644 -index 000000000000..90633406c4eb ---- /dev/null -+++ b/drivers/staging/media/hantro/sunxi_vpu_hw.c -@@ -0,0 +1,86 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Allwinner Hantro G2 VPU codec driver -+ * -+ * Copyright (C) 2021 Jernej Skrabec -+ */ -+ -+#include -+ -+#include "hantro.h" -+ -+static const struct hantro_fmt sunxi_vpu_postproc_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_NV12, -+ .codec_mode = HANTRO_MODE_NONE, -+ .postprocessed = true, -+ }, -+}; -+ -+static const struct hantro_fmt sunxi_vpu_dec_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_NV12_4L4, -+ .codec_mode = HANTRO_MODE_NONE, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_VP9_FRAME, -+ .codec_mode = HANTRO_MODE_VP9_DEC, -+ .max_depth = 2, -+ .frmsize = { -+ .min_width = 48, -+ .max_width = 3840, -+ .step_width = MB_DIM, -+ .min_height = 48, -+ .max_height = 2160, -+ .step_height = MB_DIM, -+ }, -+ }, -+}; -+ -+static int sunxi_vpu_hw_init(struct hantro_dev *vpu) -+{ -+ clk_set_rate(vpu->clocks[0].clk, 300000000); -+ -+ return 0; -+} -+ -+static void sunxi_vpu_reset(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ -+ reset_control_reset(vpu->resets); -+} -+ -+static const struct hantro_codec_ops sunxi_vpu_codec_ops[] = { -+ [HANTRO_MODE_VP9_DEC] = { -+ .run = hantro_g2_vp9_dec_run, -+ .done = hantro_g2_vp9_dec_done, -+ .reset = sunxi_vpu_reset, -+ .init = hantro_vp9_dec_init, -+ .exit = hantro_vp9_dec_exit, -+ }, -+}; -+ -+static const struct hantro_irq sunxi_irqs[] = { -+ { NULL, hantro_g2_irq }, -+}; -+ -+static const char * const sunxi_clk_names[] = { "mod", "bus" }; -+ -+const struct hantro_variant sunxi_vpu_variant = { -+ .dec_fmts = sunxi_vpu_dec_fmts, -+ .num_dec_fmts = ARRAY_SIZE(sunxi_vpu_dec_fmts), -+ .postproc_fmts = sunxi_vpu_postproc_fmts, -+ .num_postproc_fmts = ARRAY_SIZE(sunxi_vpu_postproc_fmts), -+ .postproc_ops = &hantro_g2_postproc_ops, -+ .codec = HANTRO_VP9_DECODER, -+ .codec_ops = sunxi_vpu_codec_ops, -+ .init = sunxi_vpu_hw_init, -+ .irqs = sunxi_irqs, -+ .num_irqs = ARRAY_SIZE(sunxi_irqs), -+ .clk_names = sunxi_clk_names, -+ .num_clocks = ARRAY_SIZE(sunxi_clk_names), -+ .double_buffer = 1, -+ .legacy_regs = 1, -+ .late_postproc = 1, -+}; diff --git a/projects/Allwinner/patches/linux/0086-arm64-dts-allwinner-h6-Add-Hantro-G2-node.patch b/projects/Allwinner/patches/linux/0086-arm64-dts-allwinner-h6-Add-Hantro-G2-node.patch deleted file mode 100644 index d7a5c5302b..0000000000 --- a/projects/Allwinner/patches/linux/0086-arm64-dts-allwinner-h6-Add-Hantro-G2-node.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Thu, 5 Aug 2021 22:32:38 +0200 -Subject: [PATCH] arm64: dts: allwinner: h6: Add Hantro G2 node - -H6 SoC has a second VPU, dedicated to VP9 decoding. It's a slightly -older design, though. - -Signed-off-by: Jernej Skrabec ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -index 4c4547f7d0c7..878061e75098 100644 ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -153,6 +153,15 @@ mixer0_out_tcon_top_mixer0: endpoint { - }; - }; - -+ video-codec-g2@1c00000 { -+ compatible = "allwinner,sun50i-h6-vpu-g2"; -+ reg = <0x01c00000 0x1000>; -+ interrupts = ; -+ clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>; -+ clock-names = "bus", "mod"; -+ resets = <&ccu RST_BUS_VP9>; -+ }; -+ - video-codec@1c0e000 { - compatible = "allwinner,sun50i-h6-video-engine"; - reg = <0x01c0e000 0x2000>; diff --git a/projects/Allwinner/patches/linux/0091-media-hantro-Fix-G2-HEVC-negotiated-pixelformat.patch b/projects/Allwinner/patches/linux/0091-media-hantro-Fix-G2-HEVC-negotiated-pixelformat.patch deleted file mode 100644 index a9e8f2b9a8..0000000000 --- a/projects/Allwinner/patches/linux/0091-media-hantro-Fix-G2-HEVC-negotiated-pixelformat.patch +++ /dev/null @@ -1,301 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Benjamin Gaignard -Date: Wed, 8 Dec 2021 17:44:18 +0100 -Subject: [PATCH] media: hantro: Fix G2/HEVC negotiated pixelformat - -G2/HEVC is broken because driver capture queue pixelformat ioctl G_FMT -returns VT12 while G2/HEVC always generate NV12 frames: - -video1: VIDIOC_S_FMT: type=vid-out-mplane, width=2560, height=1600, format=S265 little-endian (0x35363253), field=none, colorspace=0, num_planes=1, flags=0x0, ycbcr_enc=0, quantization=0, xfer_func=0 -plane 0: bytesperline=0 sizeimage=6144000 -video1: VIDIOC_S_EXT_CTRLS: which=0x0, count=1, error_idx=0, request_fd=0, name=HEVC Sequence Parameter Set, id/size=0x990cf0/32 -video1: VIDIOC_G_FMT: type=vid-cap-mplane, width=2560, height=1600, format=VT12 little-endian (0x32315456), field=none, colorspace=0, num_planes=1, flags=0x0, ycbcr_enc=0, quantization=0, xfer_func=0 -plane 0: bytesperline=2560 sizeimage=6144000 -video1: VIDIOC_ENUM_FMT: index=0, type=vid-cap-mplane, flags=0x0, pixelformat=NV12 little-endian (0x3231564e), mbus_code=0x0000, description='Y/CbCr 4:2:0' -video1: VIDIOC_ENUM_FMT: error -22: index=1, type=vid-cap-mplane, flags=0x0, pixelformat=.... little-endian (0x00000000), mbus_code=0x0000, description='' -video1: VIDIOC_G_FMT: type=vid-cap-mplane, width=2560, height=1600, format=VT12 little-endian (0x32315456), field=none, colorspace=0, num_planes=1, flags=0x0, ycbcr_enc=0, quantization=0, xfer_func=0 - -Use the postprocessor functions introduced by Hantro G2/VP9 codec series -to fix the issue and remove duplicated buffer management. -This allow Hantro G2/HEVC to produce NV12_4L4 and NV12. - -Fluster scores are 77/147 for HEVC and 129/303 for VP9 (no regression). - -Beauty, Jockey and ShakeNDry bitstreams from UVG (http://ultravideo.fi/) -set have also been tested. - -Fixes: 53a3e71095c5 ("media: hantro: Simplify postprocessor") -Signed-off-by: Benjamin Gaignard -Reviewed-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil -Signed-off-by: Mauro Carvalho Chehab ---- - .../staging/media/hantro/hantro_g2_hevc_dec.c | 25 +++--- - drivers/staging/media/hantro/hantro_hevc.c | 79 +++---------------- - drivers/staging/media/hantro/hantro_hw.h | 11 +++ - .../staging/media/hantro/hantro_postproc.c | 3 + - drivers/staging/media/hantro/hantro_v4l2.c | 19 ++--- - 5 files changed, 41 insertions(+), 96 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -index f62608b0b408..99d8ea7543da 100644 ---- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -@@ -354,6 +354,8 @@ static int set_ref(struct hantro_ctx *ctx) - const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; - dma_addr_t luma_addr, chroma_addr, mv_addr = 0; - struct hantro_dev *vpu = ctx->dev; -+ struct vb2_v4l2_buffer *vb2_dst; -+ struct hantro_decoded_buffer *dst; - size_t cr_offset = hantro_hevc_chroma_offset(sps); - size_t mv_offset = hantro_hevc_motion_vectors_offset(sps); - u32 max_ref_frames; -@@ -439,10 +441,15 @@ static int set_ref(struct hantro_ctx *ctx) - hantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr); - } - -- luma_addr = hantro_hevc_get_ref_buf(ctx, decode_params->pic_order_cnt_val); -+ vb2_dst = hantro_get_dst_buf(ctx); -+ dst = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf); -+ luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf); - if (!luma_addr) - return -ENOMEM; - -+ if (hantro_hevc_add_ref_buf(ctx, decode_params->pic_order_cnt_val, luma_addr)) -+ return -EINVAL; -+ - chroma_addr = luma_addr + cr_offset; - mv_addr = luma_addr + mv_offset; - -@@ -469,16 +476,12 @@ static int set_ref(struct hantro_ctx *ctx) - - static void set_buffers(struct hantro_ctx *ctx) - { -- struct vb2_v4l2_buffer *src_buf, *dst_buf; -+ struct vb2_v4l2_buffer *src_buf; - struct hantro_dev *vpu = ctx->dev; -- const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls; -- const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps; -- size_t cr_offset = hantro_hevc_chroma_offset(sps); -- dma_addr_t src_dma, dst_dma; -+ dma_addr_t src_dma; - u32 src_len, src_buf_len; - - src_buf = hantro_get_src_buf(ctx); -- dst_buf = hantro_get_dst_buf(ctx); - - /* Source (stream) buffer. */ - src_dma = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -@@ -491,11 +494,6 @@ static void set_buffers(struct hantro_ctx *ctx) - hantro_reg_write(vpu, &g2_strm_start_offset, 0); - hantro_reg_write(vpu, &g2_write_mvs_e, 1); - -- /* Destination (decoded frame) buffer. */ -- dst_dma = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf); -- -- hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma); -- hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + cr_offset); - hantro_write_addr(vpu, G2_TILE_SIZES_ADDR, ctx->hevc_dec.tile_sizes.dma); - hantro_write_addr(vpu, G2_TILE_FILTER_ADDR, ctx->hevc_dec.tile_filter.dma); - hantro_write_addr(vpu, G2_TILE_SAO_ADDR, ctx->hevc_dec.tile_sao.dma); -@@ -588,9 +586,6 @@ int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx) - /* Don't compress buffers */ - hantro_reg_write(vpu, &g2_ref_compress_bypass, 1); - -- /* use NV12 as output format */ -- hantro_reg_write(vpu, &g2_out_rs_e, 1); -- - /* Bus width and max burst */ - hantro_reg_write(vpu, &g2_buswidth, BUS_WIDTH_128); - hantro_reg_write(vpu, &g2_max_burst, 16); -diff --git a/drivers/staging/media/hantro/hantro_hevc.c b/drivers/staging/media/hantro/hantro_hevc.c -index ee03123e7704..b49a41d7ae91 100644 ---- a/drivers/staging/media/hantro/hantro_hevc.c -+++ b/drivers/staging/media/hantro/hantro_hevc.c -@@ -44,47 +44,6 @@ size_t hantro_hevc_motion_vectors_offset(const struct v4l2_ctrl_hevc_sps *sps) - return ALIGN((cr_offset * 3) / 2, G2_ALIGN); - } - --static size_t hantro_hevc_mv_size(const struct v4l2_ctrl_hevc_sps *sps) --{ -- u32 min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3; -- u32 ctb_log2_size_y = min_cb_log2_size_y + sps->log2_diff_max_min_luma_coding_block_size; -- u32 pic_width_in_ctbs_y = (sps->pic_width_in_luma_samples + (1 << ctb_log2_size_y) - 1) -- >> ctb_log2_size_y; -- u32 pic_height_in_ctbs_y = (sps->pic_height_in_luma_samples + (1 << ctb_log2_size_y) - 1) -- >> ctb_log2_size_y; -- size_t mv_size; -- -- mv_size = pic_width_in_ctbs_y * pic_height_in_ctbs_y * -- (1 << (2 * (ctb_log2_size_y - 4))) * 16; -- -- vpu_debug(4, "%dx%d (CTBs) %zu MV bytes\n", -- pic_width_in_ctbs_y, pic_height_in_ctbs_y, mv_size); -- -- return mv_size; --} -- --static size_t hantro_hevc_ref_size(struct hantro_ctx *ctx) --{ -- const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls; -- const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps; -- -- return hantro_hevc_motion_vectors_offset(sps) + hantro_hevc_mv_size(sps); --} -- --static void hantro_hevc_ref_free(struct hantro_ctx *ctx) --{ -- struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec; -- struct hantro_dev *vpu = ctx->dev; -- int i; -- -- for (i = 0; i < NUM_REF_PICTURES; i++) { -- if (hevc_dec->ref_bufs[i].cpu) -- dma_free_coherent(vpu->dev, hevc_dec->ref_bufs[i].size, -- hevc_dec->ref_bufs[i].cpu, -- hevc_dec->ref_bufs[i].dma); -- } --} -- - static void hantro_hevc_ref_init(struct hantro_ctx *ctx) - { - struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec; -@@ -108,37 +67,25 @@ dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, - } - } - -- /* Allocate a new reference buffer */ -+ return 0; -+} -+ -+int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr) -+{ -+ struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec; -+ int i; -+ -+ /* Add a new reference buffer */ - for (i = 0; i < NUM_REF_PICTURES; i++) { - if (hevc_dec->ref_bufs_poc[i] == UNUSED_REF) { -- if (!hevc_dec->ref_bufs[i].cpu) { -- struct hantro_dev *vpu = ctx->dev; -- -- /* -- * Allocate the space needed for the raw data + -- * motion vector data. Optimizations could be to -- * allocate raw data in non coherent memory and only -- * clear the motion vector data. -- */ -- hevc_dec->ref_bufs[i].cpu = -- dma_alloc_coherent(vpu->dev, -- hantro_hevc_ref_size(ctx), -- &hevc_dec->ref_bufs[i].dma, -- GFP_KERNEL); -- if (!hevc_dec->ref_bufs[i].cpu) -- return 0; -- -- hevc_dec->ref_bufs[i].size = hantro_hevc_ref_size(ctx); -- } - hevc_dec->ref_bufs_used |= 1 << i; -- memset(hevc_dec->ref_bufs[i].cpu, 0, hantro_hevc_ref_size(ctx)); - hevc_dec->ref_bufs_poc[i] = poc; -- -- return hevc_dec->ref_bufs[i].dma; -+ hevc_dec->ref_bufs[i].dma = addr; -+ return 0; - } - } - -- return 0; -+ return -EINVAL; - } - - void hantro_hevc_ref_remove_unused(struct hantro_ctx *ctx) -@@ -314,8 +261,6 @@ void hantro_hevc_dec_exit(struct hantro_ctx *ctx) - hevc_dec->tile_bsd.cpu, - hevc_dec->tile_bsd.dma); - hevc_dec->tile_bsd.cpu = NULL; -- -- hantro_hevc_ref_free(ctx); - } - - int hantro_hevc_dec_init(struct hantro_ctx *ctx) -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index cff817ca8d22..a018748fc4bf 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -346,6 +346,7 @@ void hantro_hevc_dec_exit(struct hantro_ctx *ctx); - int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx); - int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx); - dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, int poc); -+int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr); - void hantro_hevc_ref_remove_unused(struct hantro_ctx *ctx); - size_t hantro_hevc_chroma_offset(const struct v4l2_ctrl_hevc_sps *sps); - size_t hantro_hevc_motion_vectors_offset(const struct v4l2_ctrl_hevc_sps *sps); -@@ -395,6 +396,16 @@ hantro_h264_mv_size(unsigned int width, unsigned int height) - return 64 * MB_WIDTH(width) * MB_WIDTH(height) + 32; - } - -+static inline size_t -+hantro_hevc_mv_size(unsigned int width, unsigned int height) -+{ -+ /* -+ * A CTB can be 64x64, 32x32 or 16x16. -+ * Allocated memory for the "worse" case: 16x16 -+ */ -+ return width * height / 16; -+} -+ - int hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx); - int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx); - void hantro_mpeg2_dec_copy_qtable(u8 *qtable, -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index a7774ad4c445..248abe5423f0 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -146,6 +146,9 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx) - else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME) - buf_size += hantro_vp9_mv_size(ctx->dst_fmt.width, - ctx->dst_fmt.height); -+ else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE) -+ buf_size += hantro_hevc_mv_size(ctx->dst_fmt.width, -+ ctx->dst_fmt.height); - - for (i = 0; i < num_buffers; ++i) { - struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i]; -diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c -index c319f0e5fe60..e595905b3bd7 100644 ---- a/drivers/staging/media/hantro/hantro_v4l2.c -+++ b/drivers/staging/media/hantro/hantro_v4l2.c -@@ -148,20 +148,6 @@ static int vidioc_enum_fmt(struct file *file, void *priv, - unsigned int num_fmts, i, j = 0; - bool skip_mode_none; - -- /* -- * The HEVC decoder on the G2 core needs a little quirk to offer NV12 -- * only on the capture side. Once the post-processor logic is used, -- * we will be able to expose NV12_4L4 and NV12 as the other cases, -- * and therefore remove this quirk. -- */ -- if (capture && ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE) { -- if (f->index == 0) { -- f->pixelformat = V4L2_PIX_FMT_NV12; -- return 0; -- } -- return -EINVAL; -- } -- - /* - * When dealing with an encoder: - * - on the capture side we want to filter out all MODE_NONE formats. -@@ -302,6 +288,11 @@ static int hantro_try_fmt(const struct hantro_ctx *ctx, - pix_mp->plane_fmt[0].sizeimage += - hantro_vp9_mv_size(pix_mp->width, - pix_mp->height); -+ else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE && -+ !hantro_needs_postproc(ctx, fmt)) -+ pix_mp->plane_fmt[0].sizeimage += -+ hantro_hevc_mv_size(pix_mp->width, -+ pix_mp->height); - } else if (!pix_mp->plane_fmt[0].sizeimage) { - /* - * For coded formats the application can specify diff --git a/projects/Generic/linux/linux.x86_64.conf b/projects/Generic/linux/linux.x86_64.conf index 3d3eb16551..dda0ec6cc1 100644 --- a/projects/Generic/linux/linux.x86_64.conf +++ b/projects/Generic/linux/linux.x86_64.conf @@ -1,15 +1,15 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/x86 5.16.0-rc8 Kernel Configuration +# Linux/x86 5.17.0-rc3 Kernel Configuration # CONFIG_CC_VERSION_TEXT="x86_64-libreelec-linux-gnu-gcc-10.3.0 (GCC) 10.3.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=100300 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y -CONFIG_AS_VERSION=23501 +CONFIG_AS_VERSION=23700 CONFIG_LD_IS_BFD=y -CONFIG_LD_VERSION=23501 +CONFIG_LD_VERSION=23700 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y @@ -304,9 +304,6 @@ CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_HAS_CPU_RELAX=y CONFIG_ARCH_HAS_FILTER_PGPROT=y -CONFIG_HAVE_SETUP_PER_CPU_AREA=y -CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y -CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_NR_GPIO=1024 CONFIG_ARCH_SUSPEND_POSSIBLE=y @@ -475,7 +472,6 @@ CONFIG_HAVE_LIVEPATCH=y CONFIG_ARCH_HAS_ADD_PAGES=y CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_USE_PERCPU_NUMA_NODE_ID=y # # Power management and ACPI options @@ -546,6 +542,8 @@ CONFIG_HAVE_ACPI_APEI_NMI=y # CONFIG_ACPI_APEI is not set # CONFIG_ACPI_DPTF is not set # CONFIG_ACPI_CONFIGFS is not set +# CONFIG_ACPI_PFRUT is not set +CONFIG_ACPI_PCC=y # CONFIG_PMIC_OPREGION is not set CONFIG_X86_PM_TIMER=y CONFIG_ACPI_PRMT=y @@ -573,6 +571,7 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # CONFIG_X86_INTEL_PSTATE=y CONFIG_X86_PCC_CPUFREQ=m +# CONFIG_X86_AMD_PSTATE is not set CONFIG_X86_ACPI_CPUFREQ=y CONFIG_X86_ACPI_CPUFREQ_CPB=y CONFIG_X86_POWERNOW_K8=y @@ -720,6 +719,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_HAVE_STACK_VALIDATION=y CONFIG_HAVE_RELIABLE_STACKTRACE=y CONFIG_OLD_SIGSUSPEND3=y @@ -742,6 +742,7 @@ CONFIG_HAVE_STATIC_CALL_INLINE=y CONFIG_HAVE_PREEMPT_DYNAMIC=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y CONFIG_ARCH_HAS_ELFCORE_COMPAT=y CONFIG_ARCH_HAS_PARANOID_L1D_FLUSH=y CONFIG_DYNAMIC_SIGFRAME=y @@ -776,6 +777,7 @@ CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_ICQ=y CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_DEV_INTEGRITY is not set # CONFIG_BLK_DEV_ZONED is not set @@ -892,13 +894,16 @@ CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_THP_SWAP=y -CONFIG_CLEANCACHE=y -# CONFIG_FRONTSWAP is not set +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=19 +# CONFIG_ZSWAP is not set # CONFIG_ZPOOL is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y @@ -919,6 +924,7 @@ CONFIG_ARCH_HAS_PKEYS=y CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_MAPPING_DIRTY_HELPERS=y CONFIG_SECRETMEM=y +# CONFIG_ANON_VMA_NAME is not set # # Data Access Monitoring @@ -1359,6 +1365,7 @@ CONFIG_BT_INTEL=m CONFIG_BT_BCM=m CONFIG_BT_RTL=m CONFIG_BT_QCA=m +CONFIG_BT_MTK=m CONFIG_BT_HCIBTUSB=m CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y CONFIG_BT_HCIBTUSB_BCM=y @@ -1531,6 +1538,7 @@ CONFIG_AUXILIARY_BUS=y # CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set CONFIG_STANDALONE=y # CONFIG_PREVENT_FIRMWARE_BUILD is not set @@ -1643,7 +1651,6 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 # CONFIG_ATA_OVER_ETH is not set CONFIG_VIRTIO_BLK=y # CONFIG_BLK_DEV_RBD is not set -# CONFIG_BLK_DEV_RSXX is not set # # NVME Support @@ -1789,7 +1796,6 @@ CONFIG_MEGARAID_SAS=y # CONFIG_SCSI_MPI3MR is not set # CONFIG_SCSI_SMARTPQI is not set # CONFIG_SCSI_UFSHCD is not set -# CONFIG_SCSI_UFS_HWMON is not set # CONFIG_SCSI_HPTIOP is not set # CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_MYRB is not set @@ -2021,6 +2027,7 @@ CONFIG_NET_TULIP=y CONFIG_ULI526X=y # CONFIG_NET_VENDOR_DLINK is not set # CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set CONFIG_NET_VENDOR_EZCHIP=y # CONFIG_NET_VENDOR_GOOGLE is not set # CONFIG_NET_VENDOR_HUAWEI is not set @@ -2040,6 +2047,7 @@ CONFIG_IXGBE_HWMON=y # CONFIG_I40E is not set # CONFIG_I40EVF is not set CONFIG_ICE=y +CONFIG_ICE_HWTS=y # CONFIG_FM10K is not set CONFIG_IGC=y CONFIG_NET_VENDOR_MICROSOFT=y @@ -2102,6 +2110,7 @@ CONFIG_NET_VENDOR_SYNOPSYS=y # CONFIG_DWC_XLGMAC is not set # CONFIG_NET_VENDOR_TEHUTI is not set # CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set CONFIG_NET_VENDOR_VIA=y CONFIG_VIA_RHINE=y # CONFIG_VIA_RHINE_MMIO is not set @@ -2172,7 +2181,6 @@ CONFIG_MDIO_DEVRES=y # CONFIG_MDIO_BITBANG is not set # CONFIG_MDIO_BCM_UNIMAC is not set # CONFIG_MDIO_MVUSB is not set -# CONFIG_MDIO_MSCC_MIIM is not set # CONFIG_MDIO_THUNDER is not set # @@ -2766,6 +2774,7 @@ CONFIG_SERIAL_8250_DW=y # CONFIG_SERIAL_8250_RT288X is not set # CONFIG_SERIAL_8250_LPSS is not set CONFIG_SERIAL_8250_MID=y +# CONFIG_SERIAL_8250_PERICOM is not set # # Non-8250 serial port support @@ -3055,6 +3064,7 @@ CONFIG_GPIO_CDEV_V1=y # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set @@ -3081,6 +3091,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_MANAGER is not set # CONFIG_CHARGER_LT3651 is not set # CONFIG_CHARGER_LTC4162L is not set +# CONFIG_CHARGER_MAX77976 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24257 is not set # CONFIG_CHARGER_BQ24735 is not set @@ -3195,12 +3206,12 @@ CONFIG_SENSORS_JC42=m # CONFIG_SENSORS_LM95245 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_NTC_THERMISTOR is not set # CONFIG_SENSORS_NCT6683 is not set # CONFIG_SENSORS_NCT6775 is not set # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set # CONFIG_SENSORS_SBTSI is not set @@ -3225,6 +3236,7 @@ CONFIG_SENSORS_JC42=m # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_INA209 is not set # CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA238 is not set # CONFIG_SENSORS_INA3221 is not set # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set @@ -3255,6 +3267,8 @@ CONFIG_SENSORS_W83627EHF=y # # CONFIG_SENSORS_ACPI_POWER is not set CONFIG_SENSORS_ATK0110=m +# CONFIG_SENSORS_ASUS_WMI is not set +# CONFIG_SENSORS_ASUS_WMI_EC is not set CONFIG_THERMAL=y # CONFIG_THERMAL_NETLINK is not set CONFIG_THERMAL_STATISTICS=y @@ -3343,7 +3357,6 @@ CONFIG_MFD_INTEL_LPSS=y CONFIG_MFD_INTEL_LPSS_ACPI=y CONFIG_MFD_INTEL_LPSS_PCI=y # CONFIG_MFD_INTEL_PMC_BXT is not set -# CONFIG_MFD_INTEL_PMT is not set # CONFIG_MFD_IQS62X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set @@ -3426,6 +3439,7 @@ CONFIG_REGULATOR=y # CONFIG_REGULATOR_MAX8660 is not set # CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX20086 is not set # CONFIG_REGULATOR_MAX77826 is not set # CONFIG_REGULATOR_MP8859 is not set # CONFIG_REGULATOR_MT6311 is not set @@ -3920,6 +3934,7 @@ CONFIG_SDR_MAX2175=m # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5693 is not set # CONFIG_VIDEO_OV5695 is not set # CONFIG_VIDEO_OV7251 is not set # CONFIG_VIDEO_OV772X is not set @@ -4334,6 +4349,7 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_NOMODESET=y # # Frame buffer Devices @@ -4552,6 +4568,7 @@ CONFIG_SND_HDA_RECONFIG=y CONFIG_SND_HDA_INPUT_BEEP=y CONFIG_SND_HDA_INPUT_BEEP_MODE=1 CONFIG_SND_HDA_PATCH_LOADER=y +# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set CONFIG_SND_HDA_CODEC_REALTEK=m CONFIG_SND_HDA_CODEC_ANALOG=m CONFIG_SND_HDA_CODEC_SIGMATEL=m @@ -4618,6 +4635,7 @@ CONFIG_SND_SOC_AMD_RENOIR=m CONFIG_SND_SOC_AMD_RENOIR_MACH=m # CONFIG_SND_SOC_AMD_ACP5x is not set # CONFIG_SND_SOC_AMD_ACP6x is not set +# CONFIG_SND_AMD_ACP_CONFIG is not set # CONFIG_SND_SOC_AMD_ACP_COMMON is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set @@ -4710,6 +4728,7 @@ CONFIG_SND_SOC_ADAU7002=m # CONFIG_SND_SOC_ADAU7118_HW is not set # CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set @@ -4805,6 +4824,7 @@ CONFIG_SND_SOC_SPDIF=m # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set # CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320ADC3XXX is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set @@ -4920,6 +4940,7 @@ CONFIG_HID_KENSINGTON=y CONFIG_HID_LCPOWER=y # CONFIG_HID_LED is not set CONFIG_HID_LENOVO=y +# CONFIG_HID_LETSKETCH is not set CONFIG_HID_LOGITECH=y CONFIG_HID_LOGITECH_DJ=y CONFIG_HID_LOGITECH_HIDPP=y @@ -5322,6 +5343,10 @@ CONFIG_LEDS_TRIGGERS=y # CONFIG_LEDS_TRIGGER_PATTERN is not set CONFIG_LEDS_TRIGGER_AUDIO=m # CONFIG_LEDS_TRIGGER_TTY is not set + +# +# Simple LED drivers +# # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y @@ -5547,6 +5572,7 @@ CONFIG_WMI_BMOF=y # CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set # CONFIG_XIAOMI_WMI is not set # CONFIG_GIGABYTE_WMI is not set +# CONFIG_YOGABOOK_WMI is not set # CONFIG_ACERHDF is not set # CONFIG_ACER_WIRELESS is not set # CONFIG_ACER_WMI is not set @@ -5555,6 +5581,7 @@ CONFIG_WMI_BMOF=y # CONFIG_APPLE_GMUX is not set # CONFIG_ASUS_LAPTOP is not set # CONFIG_ASUS_WIRELESS is not set +# CONFIG_ASUS_TF103C_DOCK is not set # CONFIG_X86_PLATFORM_DRIVERS_DELL is not set # CONFIG_AMILO_RFKILL is not set # CONFIG_FUJITSU_LAPTOP is not set @@ -5591,6 +5618,7 @@ CONFIG_INTEL_ATOMISP2_PM=y # CONFIG_INTEL_SMARTCONNECT is not set # CONFIG_INTEL_TURBO_MAX_3 is not set # CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set +# CONFIG_INTEL_VSEC is not set # CONFIG_MSI_LAPTOP is not set # CONFIG_MSI_WMI is not set # CONFIG_PCENGINES_APU2 is not set @@ -5609,9 +5637,11 @@ CONFIG_INTEL_ATOMISP2_PM=y # CONFIG_TOPSTAR_LAPTOP is not set # CONFIG_I2C_MULTI_INSTANTIATE is not set # CONFIG_MLX_PLATFORM is not set +# CONFIG_X86_ANDROID_TABLETS is not set # CONFIG_INTEL_IPS is not set # CONFIG_INTEL_SCU_PCI is not set # CONFIG_INTEL_SCU_PLATFORM is not set +# CONFIG_SIEMENS_SIMATIC_IPC is not set CONFIG_PMC_ATOM=y # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set @@ -5630,6 +5660,7 @@ CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_SI544 is not set # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_LAN966X is not set # CONFIG_XILINX_VCU is not set # CONFIG_HWSPINLOCK is not set @@ -6295,6 +6326,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_KDF800108_CTR=y CONFIG_CRYPTO_USER_API=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_SKCIPHER=y @@ -6302,28 +6334,6 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y CONFIG_CRYPTO_USER_API_AEAD=y CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y CONFIG_CRYPTO_HASH_INFO=y - -# -# Crypto library routines -# -CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=m -CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=m -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m -CONFIG_CRYPTO_LIB_BLAKE2S=m -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m -CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m -CONFIG_CRYPTO_LIB_CHACHA=m -CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=m -CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m -CONFIG_CRYPTO_LIB_CURVE25519=m -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 -CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m -CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m -CONFIG_CRYPTO_LIB_POLY1305=m -CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m -CONFIG_CRYPTO_LIB_SHA256=y # CONFIG_CRYPTO_HW is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y @@ -6356,7 +6366,6 @@ CONFIG_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y -CONFIG_GENERIC_FIND_FIRST_BIT=y # CONFIG_CORDIC is not set # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y @@ -6365,6 +6374,29 @@ CONFIG_GENERIC_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + CONFIG_CRC_CCITT=y CONFIG_CRC16=y # CONFIG_CRC_T10DIF is not set @@ -6516,12 +6548,20 @@ CONFIG_HAVE_KCSAN_COMPILER=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# end of Networking Debugging + # # Memory Debugging # # CONFIG_PAGE_EXTENSION is not set # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_TABLE_CHECK is not set # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_PAGE_REF is not set # CONFIG_DEBUG_RODATA_TEST is not set @@ -6654,6 +6694,8 @@ CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_FENTRY=y CONFIG_HAVE_OBJTOOL_MCOUNT=y CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y +CONFIG_BUILDTIME_MCOUNT_SORT=y CONFIG_TRACER_MAX_TRACE=y CONFIG_TRACE_CLOCK=y CONFIG_RING_BUFFER=y @@ -6704,6 +6746,7 @@ CONFIG_FTRACE_MCOUNT_USE_CC=y # CONFIG_TRACE_EVAL_MAP_FILE is not set # CONFIG_FTRACE_RECORD_RECURSION is not set # CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_FTRACE_SORT_STARTUP_TEST is not set # CONFIG_RING_BUFFER_STARTUP_TEST is not set # CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set # CONFIG_PREEMPTIRQ_DELAY_TEST is not set @@ -6757,6 +6800,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_TEST_REF_TRACKER is not set # CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set # CONFIG_INTERVAL_TREE_TEST is not set @@ -6774,7 +6818,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_XARRAY is not set # CONFIG_TEST_OVERFLOW is not set # CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_HASH is not set +# CONFIG_TEST_SIPHASH is not set # CONFIG_TEST_IDA is not set # CONFIG_TEST_LKM is not set # CONFIG_TEST_BITOPS is not set diff --git a/projects/NXP/devices/iMX6/linux/linux.arm.conf b/projects/NXP/devices/iMX6/linux/linux.arm.conf index 9b51c1f686..56b49d03ea 100644 --- a/projects/NXP/devices/iMX6/linux/linux.arm.conf +++ b/projects/NXP/devices/iMX6/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.16.0-rc8 Kernel Configuration +# Linux/arm 5.17.0-rc3 Kernel Configuration # CONFIG_CC_VERSION_TEXT="armv7a-libreelec-linux-gnueabihf-gcc-10.3.0 (GCC) 10.3.0" CONFIG_CC_IS_GCC=y @@ -202,7 +202,6 @@ CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y -CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -667,6 +666,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y @@ -783,13 +783,12 @@ CONFIG_CONTIG_ALLOC=y CONFIG_BOUNCE=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -# CONFIG_CLEANCACHE is not set -# CONFIG_FRONTSWAP is not set CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 +# CONFIG_ZSWAP is not set # CONFIG_ZPOOL is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y @@ -798,6 +797,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_GUP_TEST is not set CONFIG_KMAP_LOCAL=y CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y +# CONFIG_ANON_VMA_NAME is not set # # Data Access Monitoring @@ -1032,6 +1032,7 @@ CONFIG_BT_INTEL=m CONFIG_BT_BCM=m CONFIG_BT_RTL=m CONFIG_BT_QCA=m +CONFIG_BT_MTK=m CONFIG_BT_HCIBTUSB=m CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y CONFIG_BT_HCIBTUSB_BCM=y @@ -1206,6 +1207,7 @@ CONFIG_PCI_IMX6=y # CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set # CONFIG_STANDALONE is not set CONFIG_PREVENT_FIRMWARE_BUILD=y @@ -1424,7 +1426,6 @@ CONFIG_BLK_DEV_RAM_SIZE=65536 # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_RBD is not set -# CONFIG_BLK_DEV_RSXX is not set # # NVME Support @@ -1746,6 +1747,7 @@ CONFIG_NET_VENDOR_DLINK=y # CONFIG_SUNDANCE is not set CONFIG_NET_VENDOR_EMULEX=y # CONFIG_BE2NET is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set CONFIG_NET_VENDOR_EZCHIP=y # CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set # CONFIG_NET_VENDOR_FARADAY is not set @@ -1866,6 +1868,7 @@ CONFIG_NET_VENDOR_TEHUTI=y CONFIG_NET_VENDOR_TI=y # CONFIG_TI_CPSW_PHY_SEL is not set # CONFIG_TLAN is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set CONFIG_NET_VENDOR_VIA=y # CONFIG_VIA_RHINE is not set # CONFIG_VIA_VELOCITY is not set @@ -2567,11 +2570,11 @@ CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set # CONFIG_PINCTRL_MCP23S08 is not set -# CONFIG_PINCTRL_SINGLE is not set -# CONFIG_PINCTRL_SX150X is not set -# CONFIG_PINCTRL_STMFX is not set -# CONFIG_PINCTRL_OCELOT is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_SX150X is not set CONFIG_PINCTRL_IMX=y CONFIG_PINCTRL_IMX6Q=y CONFIG_PINCTRL_IMX6SL=y @@ -2583,6 +2586,7 @@ CONFIG_PINCTRL_IMX6UL=y # CONFIG_PINCTRL_IMX8MP is not set # CONFIG_PINCTRL_IMX8MQ is not set # CONFIG_PINCTRL_IMX8ULP is not set +# CONFIG_PINCTRL_IMXRT1050 is not set # # Renesas pinctrl drivers @@ -2678,6 +2682,7 @@ CONFIG_GPIO_STMPE=y # # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set @@ -2720,6 +2725,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_LT3651 is not set # CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_MAX77976 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set @@ -2843,6 +2849,7 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set @@ -2872,6 +2879,7 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_INA209 is not set # CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA238 is not set # CONFIG_SENSORS_INA3221 is not set # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set @@ -3081,7 +3089,6 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_WM8350_I2C is not set CONFIG_MFD_WM8994=y # CONFIG_MFD_ROHM_BD718XX is not set -# CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set @@ -3124,6 +3131,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX20086 is not set # CONFIG_REGULATOR_MAX77826 is not set CONFIG_REGULATOR_MC13XXX_CORE=y CONFIG_REGULATOR_MC13783=y @@ -3540,6 +3548,7 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5693 is not set # CONFIG_VIDEO_OV5695 is not set # CONFIG_VIDEO_OV7251 is not set # CONFIG_VIDEO_OV772X is not set @@ -3840,7 +3849,6 @@ CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set # CONFIG_DRM_DP_CEC is not set CONFIG_DRM_GEM_CMA_HELPER=y -CONFIG_DRM_KMS_CMA_HELPER=y CONFIG_DRM_SCHED=y # @@ -3871,7 +3879,8 @@ CONFIG_DRM_SCHED=y # CONFIG_DRM_MGAG200 is not set # CONFIG_DRM_ARMADA is not set # CONFIG_DRM_RCAR_DW_HDMI is not set -# CONFIG_DRM_RCAR_LVDS is not set +# CONFIG_DRM_RCAR_USE_LVDS is not set +# CONFIG_DRM_RCAR_MIPI_DSI is not set # CONFIG_DRM_OMAP is not set # CONFIG_DRM_TILCDC is not set # CONFIG_DRM_QXL is not set @@ -3973,6 +3982,7 @@ CONFIG_DRM_ETNAVIV_THERMAL=y # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9163 is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set # CONFIG_TINYDRM_ILI9486 is not set @@ -3989,6 +3999,7 @@ CONFIG_DRM_ETNAVIV_THERMAL=y # CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_NOMODESET=y # # Frame buffer Devices @@ -4208,6 +4219,7 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_AMD_ACP_CONFIG is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set @@ -4278,6 +4290,7 @@ CONFIG_SND_SOC_WM_HUBS=y # CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set CONFIG_SND_SOC_AK4458=m # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set @@ -4375,6 +4388,7 @@ CONFIG_SND_SOC_SGTL5000=y # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set # CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320ADC3XXX is not set CONFIG_SND_SOC_TLV320AIC23=y CONFIG_SND_SOC_TLV320AIC23_I2C=y # CONFIG_SND_SOC_TLV320AIC23_SPI is not set @@ -4497,6 +4511,7 @@ CONFIG_HID_APPLE=y # CONFIG_HID_LCPOWER is not set # CONFIG_HID_LED is not set # CONFIG_HID_LENOVO is not set +# CONFIG_HID_LETSKETCH is not set # CONFIG_HID_LOGITECH is not set # CONFIG_HID_MAGICMOUSE is not set # CONFIG_HID_MALTRON is not set @@ -4984,6 +4999,10 @@ CONFIG_LEDS_TRIGGER_GPIO=y # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set # CONFIG_LEDS_TRIGGER_TTY is not set + +# +# Simple LED drivers +# # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y @@ -5288,6 +5307,7 @@ CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set CONFIG_COMMON_CLK_CS2000_CP=y +# CONFIG_COMMON_CLK_LAN966X is not set # CONFIG_COMMON_CLK_AXI_CLKGEN is not set # CONFIG_COMMON_CLK_PWM is not set # CONFIG_COMMON_CLK_VC5 is not set @@ -5532,6 +5552,12 @@ CONFIG_VF610_ADC=y # CONFIG_XILINX_XADC is not set # end of Analog to digital converters +# +# Analog to digital and digital to analog converters +# +# CONFIG_AD74413R is not set +# end of Analog to digital and digital to analog converters + # # Analog Front Ends # @@ -5589,6 +5615,7 @@ CONFIG_VF610_ADC=y # # Digital to analog converters # +# CONFIG_AD3552R is not set # CONFIG_AD5064 is not set # CONFIG_AD5360 is not set # CONFIG_AD5380 is not set @@ -5608,6 +5635,7 @@ CONFIG_VF610_ADC=y # CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set +# CONFIG_AD7293 is not set # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set # CONFIG_DPOT_DAC is not set @@ -5631,6 +5659,11 @@ CONFIG_VF610_ADC=y # # end of IIO dummy driver +# +# Filters +# +# end of Filters + # # Frequency Synthesizers DDS/PLL # @@ -5646,6 +5679,7 @@ CONFIG_VF610_ADC=y # # CONFIG_ADF4350 is not set # CONFIG_ADF4371 is not set +# CONFIG_ADMV1013 is not set # CONFIG_ADRF6780 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL @@ -5940,8 +5974,10 @@ CONFIG_RESET_CONTROLLER=y # CONFIG_PHY_CADENCE_SALVO is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set # CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_FSL_IMX8M_PCIE is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_LAN966X_SERDES is not set # CONFIG_PHY_CPCAP_USB is not set # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set @@ -6423,6 +6459,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_KDF800108_CTR=y CONFIG_CRYPTO_USER_API=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_SKCIPHER=y @@ -6431,24 +6468,6 @@ CONFIG_CRYPTO_USER_API_AEAD=y CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y # CONFIG_CRYPTO_STATS is not set CONFIG_CRYPTO_HASH_INFO=y - -# -# Crypto library routines -# -CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=m -CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S=m -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m -CONFIG_CRYPTO_LIB_CHACHA=m -CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m -CONFIG_CRYPTO_LIB_CURVE25519=m -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m -CONFIG_CRYPTO_LIB_POLY1305=m -CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m -CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y @@ -6508,6 +6527,25 @@ CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_STMP_DEVICE=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC_T10DIF=y @@ -6659,6 +6697,13 @@ CONFIG_HAVE_KCSAN_COMPILER=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# end of Networking Debugging + # # Memory Debugging # @@ -6686,6 +6731,8 @@ CONFIG_HAVE_ARCH_KASAN=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -6779,6 +6826,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y CONFIG_TRACE_CLOCK=y CONFIG_RING_BUFFER=y CONFIG_EVENT_TRACING=y @@ -6797,6 +6845,7 @@ CONFIG_TRACING_SUPPORT=y # CONFIG_UNWINDER_FRAME_POINTER is not set CONFIG_UNWINDER_ARM=y CONFIG_ARM_UNWIND=y +# CONFIG_BACKTRACE_VERBOSE is not set # CONFIG_DEBUG_USER is not set # CONFIG_DEBUG_LL is not set CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" @@ -6819,6 +6868,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_TEST_REF_TRACKER is not set # CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set # CONFIG_INTERVAL_TREE_TEST is not set @@ -6836,7 +6886,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_XARRAY is not set # CONFIG_TEST_OVERFLOW is not set # CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_HASH is not set +# CONFIG_TEST_SIPHASH is not set # CONFIG_TEST_IDA is not set # CONFIG_TEST_LKM is not set # CONFIG_TEST_BITOPS is not set diff --git a/projects/NXP/devices/iMX8/linux/linux.aarch64.conf b/projects/NXP/devices/iMX8/linux/linux.aarch64.conf index 257c03909d..1309eca700 100644 --- a/projects/NXP/devices/iMX8/linux/linux.aarch64.conf +++ b/projects/NXP/devices/iMX8/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.16.0-rc8 Kernel Configuration +# Linux/arm64 5.17.0-rc6 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621" CONFIG_CC_IS_GCC=y @@ -209,7 +209,6 @@ CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y -CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -425,6 +424,8 @@ CONFIG_AS_HAS_LSE_ATOMICS=y # # ARMv8.2 architectural features # +CONFIG_AS_HAS_ARMV8_2=y +CONFIG_AS_HAS_SHA3=y # CONFIG_ARM64_PMEM is not set # CONFIG_ARM64_RAS_EXTN is not set # CONFIG_ARM64_CNP is not set @@ -647,6 +648,7 @@ CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y @@ -699,6 +701,7 @@ CONFIG_MODPROBE_PATH="/sbin/modprobe" CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_ICQ=y CONFIG_BLK_DEV_BSGLIB=y # CONFIG_BLK_DEV_INTEGRITY is not set # CONFIG_BLK_DEV_ZONED is not set @@ -857,8 +860,6 @@ CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -CONFIG_CLEANCACHE=y -CONFIG_FRONTSWAP=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set CONFIG_CMA_DEBUGFS=y @@ -879,6 +880,7 @@ CONFIG_ZONE_DMA32=y # CONFIG_GUP_TEST is not set # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y +# CONFIG_ANON_VMA_NAME is not set # # Data Access Monitoring @@ -1415,6 +1417,7 @@ CONFIG_HAVE_PCI=y # CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y @@ -1714,7 +1717,6 @@ CONFIG_SCSI_LOWLEVEL=y CONFIG_ISCSI_TCP=y CONFIG_ISCSI_BOOT_SYSFS=y # CONFIG_SCSI_UFSHCD is not set -# CONFIG_SCSI_UFS_HWMON is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_DH is not set # end of SCSI device support @@ -1762,6 +1764,7 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_CAVIUM is not set # CONFIG_NET_VENDOR_CORTINA is not set # CONFIG_DNET is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set # CONFIG_NET_VENDOR_EZCHIP is not set CONFIG_NET_VENDOR_FREESCALE=y CONFIG_FEC=y @@ -1802,6 +1805,7 @@ CONFIG_DWMAC_GENERIC=y CONFIG_DWMAC_IMX8=y # CONFIG_DWMAC_INTEL_PLAT is not set # CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set CONFIG_NET_VENDOR_XILINX=y @@ -2496,12 +2500,12 @@ CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set # CONFIG_PINCTRL_MCP23S08 is not set -# CONFIG_PINCTRL_SINGLE is not set -# CONFIG_PINCTRL_SX150X is not set -# CONFIG_PINCTRL_STMFX is not set -# CONFIG_PINCTRL_RK805 is not set -# CONFIG_PINCTRL_OCELOT is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_RK805 is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_SX150X is not set CONFIG_PINCTRL_IMX=y CONFIG_PINCTRL_IMX_SCU=y CONFIG_PINCTRL_IMX8MM=y @@ -2512,6 +2516,7 @@ CONFIG_PINCTRL_IMX8QM=y CONFIG_PINCTRL_IMX8QXP=y # CONFIG_PINCTRL_IMX8DXL is not set # CONFIG_PINCTRL_IMX8ULP is not set +# CONFIG_PINCTRL_IMXRT1050 is not set # # Renesas pinctrl drivers @@ -2593,6 +2598,7 @@ CONFIG_GPIO_MXC=y # # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set @@ -2632,6 +2638,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_LT3651 is not set # CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_MAX77976 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set @@ -2754,6 +2761,7 @@ CONFIG_SENSORS_GPIO_FAN=m # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set @@ -2782,6 +2790,7 @@ CONFIG_SENSORS_PWM_FAN=m # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_INA209 is not set # CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA238 is not set # CONFIG_SENSORS_INA3221 is not set # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set @@ -2979,7 +2988,6 @@ CONFIG_MFD_WM5102=y # CONFIG_MFD_WM8350_I2C is not set CONFIG_MFD_WM8994=y CONFIG_MFD_ROHM_BD718XX=y -# CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set @@ -3025,6 +3033,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX20086 is not set # CONFIG_REGULATOR_MAX77826 is not set # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MP5416 is not set @@ -3453,6 +3462,7 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5693 is not set # CONFIG_VIDEO_OV5695 is not set # CONFIG_VIDEO_OV7251 is not set # CONFIG_VIDEO_OV772X is not set @@ -3753,7 +3763,6 @@ CONFIG_DRM_FBDEV_OVERALLOC=100 CONFIG_DRM_LOAD_EDID_FIRMWARE=y # CONFIG_DRM_DP_CEC is not set CONFIG_DRM_GEM_CMA_HELPER=y -CONFIG_DRM_KMS_CMA_HELPER=y CONFIG_DRM_SCHED=y # @@ -3777,7 +3786,8 @@ CONFIG_DRM_SCHED=y # CONFIG_DRM_VKMS is not set # CONFIG_DRM_UDL is not set # CONFIG_DRM_RCAR_DW_HDMI is not set -# CONFIG_DRM_RCAR_LVDS is not set +# CONFIG_DRM_RCAR_USE_LVDS is not set +# CONFIG_DRM_RCAR_MIPI_DSI is not set CONFIG_DRM_PANEL=y # @@ -3870,6 +3880,7 @@ CONFIG_DRM_ETNAVIV_THERMAL=y # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9163 is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set # CONFIG_TINYDRM_ILI9486 is not set @@ -3884,6 +3895,7 @@ CONFIG_DRM_ETNAVIV_THERMAL=y # CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_NOMODESET=y # # Frame buffer Devices @@ -3999,6 +4011,7 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_AMD_ACP_CONFIG is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set @@ -4067,6 +4080,7 @@ CONFIG_SND_SOC_WM_HUBS=y # CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set CONFIG_SND_SOC_AK4458=y # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set @@ -4165,9 +4179,10 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set # CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320ADC3XXX is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set -# CONFIG_SND_SOC_TLV320AIC31XX is not set +CONFIG_SND_SOC_TLV320AIC31XX=y # CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set # CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set # CONFIG_SND_SOC_TLV320AIC3X_I2C is not set @@ -4287,6 +4302,7 @@ CONFIG_HID_KENSINGTON=y # CONFIG_HID_LCPOWER is not set # CONFIG_HID_LED is not set CONFIG_HID_LENOVO=y +# CONFIG_HID_LETSKETCH is not set CONFIG_HID_LOGITECH=y CONFIG_HID_LOGITECH_DJ=y CONFIG_HID_LOGITECH_HIDPP=y @@ -4736,6 +4752,10 @@ CONFIG_LEDS_TRIGGER_CPU=y # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set # CONFIG_LEDS_TRIGGER_TTY is not set + +# +# Simple LED drivers +# # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_SUPPORT=y @@ -4997,6 +5017,7 @@ CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_HANTRO_IMX8M=y # CONFIG_VIDEO_IMX_MEDIA is not set +# CONFIG_VIDEO_MAX96712 is not set # # Android @@ -5028,6 +5049,7 @@ CONFIG_CROS_EC_SENSORHUB=y CONFIG_CROS_EC_SYSFS=y CONFIG_CROS_USBPD_NOTIFY=y # CONFIG_MELLANOX_PLATFORM is not set +# CONFIG_SURFACE_PLATFORMS is not set CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y @@ -5051,6 +5073,7 @@ CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_LAN966X is not set # CONFIG_COMMON_CLK_S2MPS11 is not set # CONFIG_COMMON_CLK_AXI_CLKGEN is not set # CONFIG_COMMON_CLK_XGENE is not set @@ -5326,6 +5349,12 @@ CONFIG_IIO=y # CONFIG_XILINX_XADC is not set # end of Analog to digital converters +# +# Analog to digital and digital to analog converters +# +# CONFIG_AD74413R is not set +# end of Analog to digital and digital to analog converters + # # Analog Front Ends # @@ -5385,6 +5414,7 @@ CONFIG_IIO=y # # Digital to analog converters # +# CONFIG_AD3552R is not set # CONFIG_AD5064 is not set # CONFIG_AD5360 is not set # CONFIG_AD5380 is not set @@ -5404,6 +5434,7 @@ CONFIG_IIO=y # CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set +# CONFIG_AD7293 is not set # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set # CONFIG_DPOT_DAC is not set @@ -5427,6 +5458,12 @@ CONFIG_IIO=y # # end of IIO dummy driver +# +# Filters +# +# CONFIG_ADMV8818 is not set +# end of Filters + # # Frequency Synthesizers DDS/PLL # @@ -5442,6 +5479,7 @@ CONFIG_IIO=y # # CONFIG_ADF4350 is not set # CONFIG_ADF4371 is not set +# CONFIG_ADMV1013 is not set # CONFIG_ADRF6780 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL @@ -5732,8 +5770,10 @@ CONFIG_GENERIC_PHY=y # CONFIG_PHY_CADENCE_SALVO is not set CONFIG_PHY_FSL_IMX8MQ_USB=y # CONFIG_PHY_MIXEL_MIPI_DPHY is not set +CONFIG_PHY_FSL_IMX8M_PCIE=y # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_LAN966X_SERDES is not set # CONFIG_PHY_CPCAP_USB is not set # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set @@ -5753,6 +5793,7 @@ CONFIG_ARM_PMU=y # CONFIG_ARM_DSU_PMU is not set CONFIG_FSL_IMX8_DDR_PMU=y # CONFIG_ARM_SPE_PMU is not set +# CONFIG_MARVELL_CN10K_TAD_PMU is not set # end of Performance monitor support # CONFIG_RAS is not set @@ -6099,7 +6140,7 @@ CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y # end of Kernel hardening options # end of Security options -CONFIG_XOR_BLOCKS=m +CONFIG_XOR_BLOCKS=y CONFIG_CRYPTO=y # @@ -6132,7 +6173,6 @@ CONFIG_CRYPTO_PCRYPT=y CONFIG_CRYPTO_CRYPTD=y # CONFIG_CRYPTO_AUTHENC is not set # CONFIG_CRYPTO_TEST is not set -CONFIG_CRYPTO_SIMD=y # # Public-key cryptography @@ -6244,6 +6284,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_KDF800108_CTR=y CONFIG_CRYPTO_USER_API=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_SKCIPHER=y @@ -6251,25 +6292,6 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y # CONFIG_CRYPTO_USER_API_AEAD is not set CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y CONFIG_CRYPTO_HASH_INFO=y - -# -# Crypto library routines -# -CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=m -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m -CONFIG_CRYPTO_LIB_BLAKE2S=m -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y -CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y -CONFIG_CRYPTO_LIB_CHACHA=m -CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m -CONFIG_CRYPTO_LIB_CURVE25519=m -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m -CONFIG_CRYPTO_LIB_POLY1305=m -CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m -CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_FSL_CAAM is not set # CONFIG_CRYPTO_DEV_SAHARA is not set @@ -6313,7 +6335,6 @@ CONFIG_HAVE_ARCH_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y -CONFIG_GENERIC_FIND_FIRST_BIT=y CONFIG_CORDIC=m # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y @@ -6322,6 +6343,26 @@ CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y # CONFIG_INDIRECT_PIO is not set + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + CONFIG_CRC_CCITT=m CONFIG_CRC16=y # CONFIG_CRC_T10DIF is not set @@ -6468,12 +6509,21 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y # CONFIG_UBSAN is not set +CONFIG_HAVE_ARCH_KCSAN=y CONFIG_HAVE_KCSAN_COMPILER=y +# CONFIG_KCSAN is not set # end of Generic Kernel Debugging Instruments CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# end of Networking Debugging + # # Memory Debugging # @@ -6616,7 +6666,6 @@ CONFIG_TRACING_SUPPORT=y # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set diff --git a/projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch b/projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch index eb9fbce52e..945597f49c 100644 --- a/projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch +++ b/projects/NXP/devices/iMX8/patches/linux/0001-drm-bridge-mhdp-Add-cdns-mhdp-driver-bridge-driver.patch @@ -3653,7 +3653,7 @@ index 17a9e7eb2130..bd013659404f 100644 --- a/drivers/gpu/drm/rockchip/Makefile +++ b/drivers/gpu/drm/rockchip/Makefile @@ -8,7 +8,7 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \ - rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o + rockchip_drm_gem.o rockchip_drm_vop.o rockchip_vop_reg.o rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o -rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o diff --git a/projects/NXP/devices/iMX8/patches/linux/0067-hantro-postproc-Fix-motion-vector-space-size.patch b/projects/NXP/devices/iMX8/patches/linux/0067-hantro-postproc-Fix-motion-vector-space-size.patch deleted file mode 100644 index 95ec0de49e..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0067-hantro-postproc-Fix-motion-vector-space-size.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Tue, 16 Nov 2021 15:38:31 +0100 -Subject: [PATCH] hantro: postproc: Fix motion vector space size - -When the post-processor hardware block is enabled, the driver -allocates an internal queue of buffers for the decoder enginer, -and uses the vb2 queue for the post-processor engine. - -For instance, on a G1 core, the decoder engine produces NV12 buffers -and the post-processor engine can produce YUY2 buffers. The decoder -engine expects motion vectors to be appended to the NV12 buffers, -but this is only required for CODECs that need motion vectors, -such as H.264. - -Fix the post-processor logic accordingly. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/hantro_postproc.c | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index ed8916c950a4..07842152003f 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -132,9 +132,10 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx) - unsigned int num_buffers = cap_queue->num_buffers; - unsigned int i, buf_size; - -- buf_size = ctx->dst_fmt.plane_fmt[0].sizeimage + -- hantro_h264_mv_size(ctx->dst_fmt.width, -- ctx->dst_fmt.height); -+ buf_size = ctx->dst_fmt.plane_fmt[0].sizeimage; -+ if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE) -+ buf_size += hantro_h264_mv_size(ctx->dst_fmt.width, -+ ctx->dst_fmt.height); - - for (i = 0; i < num_buffers; ++i) { - struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i]; diff --git a/projects/NXP/devices/iMX8/patches/linux/0068-hantro-postproc-Introduce-struct-hantro_postproc_ops.patch b/projects/NXP/devices/iMX8/patches/linux/0068-hantro-postproc-Introduce-struct-hantro_postproc_ops.patch deleted file mode 100644 index 8466cd8f22..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0068-hantro-postproc-Introduce-struct-hantro_postproc_ops.patch +++ /dev/null @@ -1,229 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Tue, 16 Nov 2021 15:38:32 +0100 -Subject: [PATCH] hantro: postproc: Introduce struct hantro_postproc_ops - -Turns out the post-processor block on the G2 core is substantially -different from the one on the G1 core. Introduce hantro_postproc_ops -with .enable and .disable methods, which will allow to support -the G2 post-processor cleanly. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Andrzej Pietrasiewicz -Reviewed-by: Benjamin Gaignard -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/hantro.h | 5 +-- - drivers/staging/media/hantro/hantro_hw.h | 13 ++++++- - .../staging/media/hantro/hantro_postproc.c | 35 +++++++++++++------ - drivers/staging/media/hantro/imx8m_vpu_hw.c | 2 +- - .../staging/media/hantro/rockchip_vpu_hw.c | 6 ++-- - .../staging/media/hantro/sama5d4_vdec_hw.c | 2 +- - 6 files changed, 45 insertions(+), 18 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index c2e2dca38628..c2e01959dc00 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -28,6 +28,7 @@ - - struct hantro_ctx; - struct hantro_codec_ops; -+struct hantro_postproc_ops; - - #define HANTRO_JPEG_ENCODER BIT(0) - #define HANTRO_ENCODERS 0x0000ffff -@@ -59,6 +60,7 @@ struct hantro_irq { - * @num_dec_fmts: Number of decoder formats. - * @postproc_fmts: Post-processor formats. - * @num_postproc_fmts: Number of post-processor formats. -+ * @postproc_ops: Post-processor ops. - * @codec: Supported codecs - * @codec_ops: Codec ops. - * @init: Initialize hardware, optional. -@@ -69,7 +71,6 @@ struct hantro_irq { - * @num_clocks: number of clocks in the array - * @reg_names: array of register range names - * @num_regs: number of register range names in the array -- * @postproc_regs: &struct hantro_postproc_regs pointer - */ - struct hantro_variant { - unsigned int enc_offset; -@@ -80,6 +81,7 @@ struct hantro_variant { - unsigned int num_dec_fmts; - const struct hantro_fmt *postproc_fmts; - unsigned int num_postproc_fmts; -+ const struct hantro_postproc_ops *postproc_ops; - unsigned int codec; - const struct hantro_codec_ops *codec_ops; - int (*init)(struct hantro_dev *vpu); -@@ -90,7 +92,6 @@ struct hantro_variant { - int num_clocks; - const char * const *reg_names; - int num_regs; -- const struct hantro_postproc_regs *postproc_regs; - }; - - /** -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index 267a6d33a47b..2f85430682d8 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -174,6 +174,17 @@ struct hantro_postproc_ctx { - struct hantro_aux_buf dec_q[VB2_MAX_FRAME]; - }; - -+/** -+ * struct hantro_postproc_ops - post-processor operations -+ * -+ * @enable: Enable the post-processor block. Optional. -+ * @disable: Disable the post-processor block. Optional. -+ */ -+struct hantro_postproc_ops { -+ void (*enable)(struct hantro_ctx *ctx); -+ void (*disable)(struct hantro_ctx *ctx); -+}; -+ - /** - * struct hantro_codec_ops - codec mode specific operations - * -@@ -221,7 +232,7 @@ extern const struct hantro_variant rk3328_vpu_variant; - extern const struct hantro_variant rk3399_vpu_variant; - extern const struct hantro_variant sama5d4_vdec_variant; - --extern const struct hantro_postproc_regs hantro_g1_postproc_regs; -+extern const struct hantro_postproc_ops hantro_g1_postproc_ops; - - extern const u32 hantro_vp8_dec_mc_filter[8][6]; - -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index 07842152003f..882fb8bc5ddd 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -15,14 +15,14 @@ - #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \ - { \ - hantro_reg_write(vpu, \ -- &(vpu)->variant->postproc_regs->reg_name, \ -+ &hantro_g1_postproc_regs.reg_name, \ - val); \ - } - - #define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \ - { \ - hantro_reg_write_s(vpu, \ -- &(vpu)->variant->postproc_regs->reg_name, \ -+ &hantro_g1_postproc_regs.reg_name, \ - val); \ - } - -@@ -64,16 +64,13 @@ bool hantro_needs_postproc(const struct hantro_ctx *ctx, - return fmt->fourcc != V4L2_PIX_FMT_NV12; - } - --void hantro_postproc_enable(struct hantro_ctx *ctx) -+static void hantro_postproc_g1_enable(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; - struct vb2_v4l2_buffer *dst_buf; - u32 src_pp_fmt, dst_pp_fmt; - dma_addr_t dst_dma; - -- if (!vpu->variant->postproc_regs) -- return; -- - /* Turn on pipeline mode. Must be done first. */ - HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x1); - -@@ -154,12 +151,30 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx) - return 0; - } - --void hantro_postproc_disable(struct hantro_ctx *ctx) -+static void hantro_postproc_g1_disable(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; - -- if (!vpu->variant->postproc_regs) -- return; -- - HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0); - } -+ -+void hantro_postproc_disable(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ -+ if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->disable) -+ vpu->variant->postproc_ops->disable(ctx); -+} -+ -+void hantro_postproc_enable(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ -+ if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->enable) -+ vpu->variant->postproc_ops->enable(ctx); -+} -+ -+const struct hantro_postproc_ops hantro_g1_postproc_ops = { -+ .enable = hantro_postproc_g1_enable, -+ .disable = hantro_postproc_g1_disable, -+}; -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index ea919bfb9891..22fa7d2f3b64 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -262,7 +262,7 @@ const struct hantro_variant imx8mq_vpu_variant = { - .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts), - .postproc_fmts = imx8m_vpu_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts), -- .postproc_regs = &hantro_g1_postproc_regs, -+ .postproc_ops = &hantro_g1_postproc_ops, - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | - HANTRO_H264_DECODER, - .codec_ops = imx8mq_vpu_codec_ops, -diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c -index d4f52957cc53..6c1ad5534ce5 100644 ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -460,7 +460,7 @@ const struct hantro_variant rk3036_vpu_variant = { - .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts), - .postproc_fmts = rockchip_vpu1_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts), -- .postproc_regs = &hantro_g1_postproc_regs, -+ .postproc_ops = &hantro_g1_postproc_ops, - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | - HANTRO_H264_DECODER, - .codec_ops = rk3036_vpu_codec_ops, -@@ -485,7 +485,7 @@ const struct hantro_variant rk3066_vpu_variant = { - .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts), - .postproc_fmts = rockchip_vpu1_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts), -- .postproc_regs = &hantro_g1_postproc_regs, -+ .postproc_ops = &hantro_g1_postproc_ops, - .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | - HANTRO_VP8_DECODER | HANTRO_H264_DECODER, - .codec_ops = rk3066_vpu_codec_ops, -@@ -505,7 +505,7 @@ const struct hantro_variant rk3288_vpu_variant = { - .num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts), - .postproc_fmts = rockchip_vpu1_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts), -- .postproc_regs = &hantro_g1_postproc_regs, -+ .postproc_ops = &hantro_g1_postproc_ops, - .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | - HANTRO_VP8_DECODER | HANTRO_H264_DECODER, - .codec_ops = rk3288_vpu_codec_ops, -diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c -index 9c3b8cd0b239..f3fecc7248c4 100644 ---- a/drivers/staging/media/hantro/sama5d4_vdec_hw.c -+++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c -@@ -100,7 +100,7 @@ const struct hantro_variant sama5d4_vdec_variant = { - .num_dec_fmts = ARRAY_SIZE(sama5d4_vdec_fmts), - .postproc_fmts = sama5d4_vdec_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(sama5d4_vdec_postproc_fmts), -- .postproc_regs = &hantro_g1_postproc_regs, -+ .postproc_ops = &hantro_g1_postproc_ops, - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | - HANTRO_H264_DECODER, - .codec_ops = sama5d4_vdec_codec_ops, diff --git a/projects/NXP/devices/iMX8/patches/linux/0069-hantro-Simplify-postprocessor.patch b/projects/NXP/devices/iMX8/patches/linux/0069-hantro-Simplify-postprocessor.patch deleted file mode 100644 index b97d1f284d..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0069-hantro-Simplify-postprocessor.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Tue, 16 Nov 2021 15:38:33 +0100 -Subject: [PATCH] hantro: Simplify postprocessor - -Add a 'postprocessed' boolean property to struct hantro_fmt -to signal that a format is produced by the post-processor. -This will allow to introduce the G2 post-processor in a simple way. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/hantro.h | 2 ++ - drivers/staging/media/hantro/hantro_postproc.c | 8 +------- - drivers/staging/media/hantro/imx8m_vpu_hw.c | 1 + - drivers/staging/media/hantro/rockchip_vpu_hw.c | 1 + - drivers/staging/media/hantro/sama5d4_vdec_hw.c | 1 + - 5 files changed, 6 insertions(+), 7 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index c2e01959dc00..dd5e56765d4e 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -263,6 +263,7 @@ struct hantro_ctx { - * @max_depth: Maximum depth, for bitstream formats - * @enc_fmt: Format identifier for encoder registers. - * @frmsize: Supported range of frame sizes (only for bitstream formats). -+ * @postprocessed: Indicates if this format needs the post-processor. - */ - struct hantro_fmt { - char *name; -@@ -272,6 +273,7 @@ struct hantro_fmt { - int max_depth; - enum hantro_enc_fmt enc_fmt; - struct v4l2_frmsize_stepwise frmsize; -+ bool postprocessed; - }; - - struct hantro_reg { -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index 882fb8bc5ddd..4549aec08feb 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -53,15 +53,9 @@ const struct hantro_postproc_regs hantro_g1_postproc_regs = { - bool hantro_needs_postproc(const struct hantro_ctx *ctx, - const struct hantro_fmt *fmt) - { -- struct hantro_dev *vpu = ctx->dev; -- - if (ctx->is_encoder) - return false; -- -- if (!vpu->variant->postproc_fmts) -- return false; -- -- return fmt->fourcc != V4L2_PIX_FMT_NV12; -+ return fmt->postprocessed; - } - - static void hantro_postproc_g1_enable(struct hantro_ctx *ctx) -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index 22fa7d2f3b64..02e61438220a 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -82,6 +82,7 @@ static const struct hantro_fmt imx8m_vpu_postproc_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_YUYV, - .codec_mode = HANTRO_MODE_NONE, -+ .postprocessed = true, - }, - }; - -diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c -index 6c1ad5534ce5..f372f767d4ff 100644 ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -62,6 +62,7 @@ static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_YUYV, - .codec_mode = HANTRO_MODE_NONE, -+ .postprocessed = true, - }, - }; - -diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c -index f3fecc7248c4..b2fc1c5613e1 100644 ---- a/drivers/staging/media/hantro/sama5d4_vdec_hw.c -+++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c -@@ -15,6 +15,7 @@ static const struct hantro_fmt sama5d4_vdec_postproc_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_YUYV, - .codec_mode = HANTRO_MODE_NONE, -+ .postprocessed = true, - }, - }; - diff --git a/projects/NXP/devices/iMX8/patches/linux/0070-hantro-Add-quirk-for-NV12-NV12_4L4-capture-format.patch b/projects/NXP/devices/iMX8/patches/linux/0070-hantro-Add-quirk-for-NV12-NV12_4L4-capture-format.patch deleted file mode 100644 index d28bfa4a7a..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0070-hantro-Add-quirk-for-NV12-NV12_4L4-capture-format.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Tue, 16 Nov 2021 15:38:34 +0100 -Subject: [PATCH] hantro: Add quirk for NV12/NV12_4L4 capture format - -The G2 core decoder engine produces NV12_4L4 format, -which is a simple NV12 4x4 tiled format. The driver currently -hides this format by always enabling the post-processor engine, -and therefore offering NV12 directly. - -This is done without using the logic in hantro_postproc.c -and therefore makes it difficult to add VP9 cleanly. - -Since fixing this is not easy, add a small quirk to force -NV12 if HEVC was configured, but otherwise declare NV12_4L4 -as the pixel format in imx8mq_vpu_g2_variant.dec_fmts. - -This will be used by the VP9 decoder which will be added soon. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/hantro_v4l2.c | 14 ++++++++++++++ - drivers/staging/media/hantro/imx8m_vpu_hw.c | 2 +- - 2 files changed, 15 insertions(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c -index bcb0bdff4a9a..d1f060c55fed 100644 ---- a/drivers/staging/media/hantro/hantro_v4l2.c -+++ b/drivers/staging/media/hantro/hantro_v4l2.c -@@ -150,6 +150,20 @@ static int vidioc_enum_fmt(struct file *file, void *priv, - unsigned int num_fmts, i, j = 0; - bool skip_mode_none; - -+ /* -+ * The HEVC decoder on the G2 core needs a little quirk to offer NV12 -+ * only on the capture side. Once the post-processor logic is used, -+ * we will be able to expose NV12_4L4 and NV12 as the other cases, -+ * and therefore remove this quirk. -+ */ -+ if (capture && ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE) { -+ if (f->index == 0) { -+ f->pixelformat = V4L2_PIX_FMT_NV12; -+ return 0; -+ } -+ return -EINVAL; -+ } -+ - /* - * When dealing with an encoder: - * - on the capture side we want to filter out all MODE_NONE formats. -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index 02e61438220a..a40b161e5956 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -134,7 +134,7 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = { - - static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = { - { -- .fourcc = V4L2_PIX_FMT_NV12, -+ .fourcc = V4L2_PIX_FMT_NV12_4L4, - .codec_mode = HANTRO_MODE_NONE, - }, - { diff --git a/projects/NXP/devices/iMX8/patches/linux/0071-media-uapi-Add-VP9-stateless-decoder-controls.patch b/projects/NXP/devices/iMX8/patches/linux/0071-media-uapi-Add-VP9-stateless-decoder-controls.patch deleted file mode 100644 index 32ed31131e..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0071-media-uapi-Add-VP9-stateless-decoder-controls.patch +++ /dev/null @@ -1,1309 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:35 +0100 -Subject: [PATCH] media: uapi: Add VP9 stateless decoder controls - -Add the VP9 stateless decoder controls plus the documentation that goes -with it. - -Signed-off-by: Boris Brezillon -Co-developed-by: Ezequiel Garcia -Signed-off-by: Ezequiel Garcia -Signed-off-by: Adrian Ratiu -Signed-off-by: Andrzej Pietrasiewicz -Co-developed-by: Daniel Almeida -Signed-off-by: Daniel Almeida -Signed-off-by: Hans Verkuil ---- - .../userspace-api/media/v4l/biblio.rst | 10 + - .../media/v4l/ext-ctrls-codec-stateless.rst | 573 ++++++++++++++++++ - .../media/v4l/pixfmt-compressed.rst | 15 + - .../media/v4l/vidioc-g-ext-ctrls.rst | 8 + - .../media/v4l/vidioc-queryctrl.rst | 12 + - .../media/videodev2.h.rst.exceptions | 2 + - drivers/media/v4l2-core/v4l2-ctrls-core.c | 180 ++++++ - drivers/media/v4l2-core/v4l2-ctrls-defs.c | 8 + - drivers/media/v4l2-core/v4l2-ioctl.c | 1 + - include/media/v4l2-ctrls.h | 4 + - include/uapi/linux/v4l2-controls.h | 284 +++++++++ - include/uapi/linux/videodev2.h | 6 + - 12 files changed, 1103 insertions(+) - -diff --git a/Documentation/userspace-api/media/v4l/biblio.rst b/Documentation/userspace-api/media/v4l/biblio.rst -index 7b8e6738ff9e..9cd18c153d19 100644 ---- a/Documentation/userspace-api/media/v4l/biblio.rst -+++ b/Documentation/userspace-api/media/v4l/biblio.rst -@@ -417,3 +417,13 @@ VP8 - :title: RFC 6386: "VP8 Data Format and Decoding Guide" - - :author: J. Bankoski et al. -+ -+.. _vp9: -+ -+VP9 -+=== -+ -+ -+:title: VP9 Bitstream & Decoding Process Specification -+ -+:author: Adrian Grange (Google), Peter de Rivaz (Argon Design), Jonathan Hunt (Argon Design) -diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst -index 72f5e85b4f34..cc080c4257d0 100644 ---- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst -+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst -@@ -1458,3 +1458,576 @@ FWHT Flags - .. raw:: latex - - \normalsize -+ -+.. _v4l2-codec-stateless-vp9: -+ -+``V4L2_CID_STATELESS_VP9_COMPRESSED_HDR (struct)`` -+ Stores VP9 probabilities updates as parsed from the current compressed frame -+ header. A value of zero in an array element means no update of the relevant -+ probability. Motion vector-related updates contain a new value or zero. All -+ other updates contain values translated with inv_map_table[] (see 6.3.5 in -+ :ref:`vp9`). -+ -+.. c:type:: v4l2_ctrl_vp9_compressed_hdr -+ -+.. tabularcolumns:: |p{1cm}|p{4.8cm}|p{11.4cm}| -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_vp9_compressed_hdr -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``tx_mode`` -+ - Specifies the TX mode. See :ref:`TX Mode ` for more details. -+ * - __u8 -+ - ``tx8[2][1]`` -+ - TX 8x8 probabilities delta. -+ * - __u8 -+ - ``tx16[2][2]`` -+ - TX 16x16 probabilities delta. -+ * - __u8 -+ - ``tx32[2][3]`` -+ - TX 32x32 probabilities delta. -+ * - __u8 -+ - ``coef[4][2][2][6][6][3]`` -+ - Coefficient probabilities delta. -+ * - __u8 -+ - ``skip[3]`` -+ - Skip probabilities delta. -+ * - __u8 -+ - ``inter_mode[7][3]`` -+ - Inter prediction mode probabilities delta. -+ * - __u8 -+ - ``interp_filter[4][2]`` -+ - Interpolation filter probabilities delta. -+ * - __u8 -+ - ``is_inter[4]`` -+ - Is inter-block probabilities delta. -+ * - __u8 -+ - ``comp_mode[5]`` -+ - Compound prediction mode probabilities delta. -+ * - __u8 -+ - ``single_ref[5][2]`` -+ - Single reference probabilities delta. -+ * - __u8 -+ - ``comp_ref[5]`` -+ - Compound reference probabilities delta. -+ * - __u8 -+ - ``y_mode[4][9]`` -+ - Y prediction mode probabilities delta. -+ * - __u8 -+ - ``uv_mode[10][9]`` -+ - UV prediction mode probabilities delta. -+ * - __u8 -+ - ``partition[16][3]`` -+ - Partition probabilities delta. -+ * - __u8 -+ - ``mv.joint[3]`` -+ - Motion vector joint probabilities delta. -+ * - __u8 -+ - ``mv.sign[2]`` -+ - Motion vector sign probabilities delta. -+ * - __u8 -+ - ``mv.classes[2][10]`` -+ - Motion vector class probabilities delta. -+ * - __u8 -+ - ``mv.class0_bit[2]`` -+ - Motion vector class0 bit probabilities delta. -+ * - __u8 -+ - ``mv.bits[2][10]`` -+ - Motion vector bits probabilities delta. -+ * - __u8 -+ - ``mv.class0_fr[2][2][3]`` -+ - Motion vector class0 fractional bit probabilities delta. -+ * - __u8 -+ - ``mv.fr[2][3]`` -+ - Motion vector fractional bit probabilities delta. -+ * - __u8 -+ - ``mv.class0_hp[2]`` -+ - Motion vector class0 high precision fractional bit probabilities delta. -+ * - __u8 -+ - ``mv.hp[2]`` -+ - Motion vector high precision fractional bit probabilities delta. -+ -+.. _vp9_tx_mode: -+ -+``TX Mode`` -+ -+.. tabularcolumns:: |p{6.5cm}|p{0.5cm}|p{10.3cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_TX_MODE_ONLY_4X4`` -+ - 0 -+ - Transform size is 4x4. -+ * - ``V4L2_VP9_TX_MODE_ALLOW_8X8`` -+ - 1 -+ - Transform size can be up to 8x8. -+ * - ``V4L2_VP9_TX_MODE_ALLOW_16X16`` -+ - 2 -+ - Transform size can be up to 16x16. -+ * - ``V4L2_VP9_TX_MODE_ALLOW_32X32`` -+ - 3 -+ - transform size can be up to 32x32. -+ * - ``V4L2_VP9_TX_MODE_SELECT`` -+ - 4 -+ - Bitstream contains the transform size for each block. -+ -+See section '7.3.1 Tx mode semantics' of the :ref:`vp9` specification for more details. -+ -+``V4L2_CID_STATELESS_VP9_FRAME (struct)`` -+ Specifies the frame parameters for the associated VP9 frame decode request. -+ This includes the necessary parameters for configuring a stateless hardware -+ decoding pipeline for VP9. The bitstream parameters are defined according -+ to :ref:`vp9`. -+ -+.. c:type:: v4l2_ctrl_vp9_frame -+ -+.. raw:: latex -+ -+ \small -+ -+.. tabularcolumns:: |p{4.7cm}|p{5.5cm}|p{7.1cm}| -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_vp9_frame -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - struct :c:type:`v4l2_vp9_loop_filter` -+ - ``lf`` -+ - Loop filter parameters. See struct :c:type:`v4l2_vp9_loop_filter` for more details. -+ * - struct :c:type:`v4l2_vp9_quantization` -+ - ``quant`` -+ - Quantization parameters. See :c:type:`v4l2_vp9_quantization` for more details. -+ * - struct :c:type:`v4l2_vp9_segmentation` -+ - ``seg`` -+ - Segmentation parameters. See :c:type:`v4l2_vp9_segmentation` for more details. -+ * - __u32 -+ - ``flags`` -+ - Combination of V4L2_VP9_FRAME_FLAG_* flags. See :ref:`Frame Flags`. -+ * - __u16 -+ - ``compressed_header_size`` -+ - Compressed header size in bytes. -+ * - __u16 -+ - ``uncompressed_header_size`` -+ - Uncompressed header size in bytes. -+ * - __u16 -+ - ``frame_width_minus_1`` -+ - Add 1 to get the frame width expressed in pixels. See section 7.2.3 in :ref:`vp9`. -+ * - __u16 -+ - ``frame_height_minus_1`` -+ - Add 1 to get the frame height expressed in pixels. See section 7.2.3 in :ref:`vp9`. -+ * - __u16 -+ - ``render_width_minus_1`` -+ - Add 1 to get the expected render width expressed in pixels. This is -+ not used during the decoding process but might be used by HW scalers to -+ prepare a frame that's ready for scanout. See section 7.2.4 in :ref:`vp9`. -+ * - __u16 -+ - render_height_minus_1 -+ - Add 1 to get the expected render height expressed in pixels. This is -+ not used during the decoding process but might be used by HW scalers to -+ prepare a frame that's ready for scanout. See section 7.2.4 in :ref:`vp9`. -+ * - __u64 -+ - ``last_frame_ts`` -+ - "last" reference buffer timestamp. -+ The timestamp refers to the ``timestamp`` field in -+ struct :c:type:`v4l2_buffer`. Use the :c:func:`v4l2_timeval_to_ns()` -+ function to convert the struct :c:type:`timeval` in struct -+ :c:type:`v4l2_buffer` to a __u64. -+ * - __u64 -+ - ``golden_frame_ts`` -+ - "golden" reference buffer timestamp. -+ The timestamp refers to the ``timestamp`` field in -+ struct :c:type:`v4l2_buffer`. Use the :c:func:`v4l2_timeval_to_ns()` -+ function to convert the struct :c:type:`timeval` in struct -+ :c:type:`v4l2_buffer` to a __u64. -+ * - __u64 -+ - ``alt_frame_ts`` -+ - "alt" reference buffer timestamp. -+ The timestamp refers to the ``timestamp`` field in -+ struct :c:type:`v4l2_buffer`. Use the :c:func:`v4l2_timeval_to_ns()` -+ function to convert the struct :c:type:`timeval` in struct -+ :c:type:`v4l2_buffer` to a __u64. -+ * - __u8 -+ - ``ref_frame_sign_bias`` -+ - a bitfield specifying whether the sign bias is set for a given -+ reference frame. See :ref:`Reference Frame Sign Bias` -+ for more details. -+ * - __u8 -+ - ``reset_frame_context`` -+ - specifies whether the frame context should be reset to default values. See -+ :ref:`Reset Frame Context` for more details. -+ * - __u8 -+ - ``frame_context_idx`` -+ - Frame context that should be used/updated. -+ * - __u8 -+ - ``profile`` -+ - VP9 profile. Can be 0, 1, 2 or 3. -+ * - __u8 -+ - ``bit_depth`` -+ - Component depth in bits. Can be 8, 10 or 12. Note that not all profiles -+ support 10 and/or 12 bits depths. -+ * - __u8 -+ - ``interpolation_filter`` -+ - Specifies the filter selection used for performing inter prediction. See -+ :ref:`Interpolation Filter` for more details. -+ * - __u8 -+ - ``tile_cols_log2`` -+ - Specifies the base 2 logarithm of the width of each tile (where the -+ width is measured in units of 8x8 blocks). Shall be less than or equal -+ to 6. -+ * - __u8 -+ - ``tile_rows_log2`` -+ - Specifies the base 2 logarithm of the height of each tile (where the -+ height is measured in units of 8x8 blocks). -+ * - __u8 -+ - ``reference_mode`` -+ - Specifies the type of inter prediction to be used. See -+ :ref:`Reference Mode` for more details. -+ * - __u8 -+ - ``reserved[7]`` -+ - Applications and drivers must set this to zero. -+ -+.. raw:: latex -+ -+ \normalsize -+ -+.. _vp9_frame_flags: -+ -+``Frame Flags`` -+ -+.. tabularcolumns:: |p{10.0cm}|p{1.2cm}|p{6.1cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_FRAME_FLAG_KEY_FRAME`` -+ - 0x001 -+ - The frame is a key frame. -+ * - ``V4L2_VP9_FRAME_FLAG_SHOW_FRAME`` -+ - 0x002 -+ - The frame should be displayed. -+ * - ``V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT`` -+ - 0x004 -+ - The decoding should be error resilient. -+ * - ``V4L2_VP9_FRAME_FLAG_INTRA_ONLY`` -+ - 0x008 -+ - The frame does not reference other frames. -+ * - ``V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV`` -+ - 0x010 -+ - The frame can use high precision motion vectors. -+ * - ``V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX`` -+ - 0x020 -+ - Frame context should be updated after decoding. -+ * - ``V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE`` -+ - 0x040 -+ - Parallel decoding is used. -+ * - ``V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING`` -+ - 0x080 -+ - Vertical subsampling is enabled. -+ * - ``V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING`` -+ - 0x100 -+ - Horizontal subsampling is enabled. -+ * - ``V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING`` -+ - 0x200 -+ - The full UV range is used. -+ -+.. _vp9_ref_frame_sign_bias: -+ -+``Reference Frame Sign Bias`` -+ -+.. tabularcolumns:: |p{7.0cm}|p{1.2cm}|p{9.1cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_SIGN_BIAS_LAST`` -+ - 0x1 -+ - Sign bias is set for the last reference frame. -+ * - ``V4L2_VP9_SIGN_BIAS_GOLDEN`` -+ - 0x2 -+ - Sign bias is set for the golden reference frame. -+ * - ``V4L2_VP9_SIGN_BIAS_ALT`` -+ - 0x2 -+ - Sign bias is set for the alt reference frame. -+ -+.. _vp9_reset_frame_context: -+ -+``Reset Frame Context`` -+ -+.. tabularcolumns:: |p{7.0cm}|p{1.2cm}|p{9.1cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_RESET_FRAME_CTX_NONE`` -+ - 0 -+ - Do not reset any frame context. -+ * - ``V4L2_VP9_RESET_FRAME_CTX_SPEC`` -+ - 1 -+ - Reset the frame context pointed to by -+ :c:type:`v4l2_ctrl_vp9_frame`.frame_context_idx. -+ * - ``V4L2_VP9_RESET_FRAME_CTX_ALL`` -+ - 2 -+ - Reset all frame contexts. -+ -+See section '7.2 Uncompressed header semantics' of the :ref:`vp9` specification -+for more details. -+ -+.. _vp9_interpolation_filter: -+ -+``Interpolation Filter`` -+ -+.. tabularcolumns:: |p{9.0cm}|p{1.2cm}|p{7.1cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_INTERP_FILTER_EIGHTTAP`` -+ - 0 -+ - Eight tap filter. -+ * - ``V4L2_VP9_INTERP_FILTER_EIGHTTAP_SMOOTH`` -+ - 1 -+ - Eight tap smooth filter. -+ * - ``V4L2_VP9_INTERP_FILTER_EIGHTTAP_SHARP`` -+ - 2 -+ - Eeight tap sharp filter. -+ * - ``V4L2_VP9_INTERP_FILTER_BILINEAR`` -+ - 3 -+ - Bilinear filter. -+ * - ``V4L2_VP9_INTERP_FILTER_SWITCHABLE`` -+ - 4 -+ - Filter selection is signaled at the block level. -+ -+See section '7.2.7 Interpolation filter semantics' of the :ref:`vp9` specification -+for more details. -+ -+.. _vp9_reference_mode: -+ -+``Reference Mode`` -+ -+.. tabularcolumns:: |p{9.6cm}|p{0.5cm}|p{7.2cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_REFERENCE_MODE_SINGLE_REFERENCE`` -+ - 0 -+ - Indicates that all the inter blocks use only a single reference frame -+ to generate motion compensated prediction. -+ * - ``V4L2_VP9_REFERENCE_MODE_COMPOUND_REFERENCE`` -+ - 1 -+ - Requires all the inter blocks to use compound mode. Single reference -+ frame prediction is not allowed. -+ * - ``V4L2_VP9_REFERENCE_MODE_SELECT`` -+ - 2 -+ - Allows each individual inter block to select between single and -+ compound prediction modes. -+ -+See section '7.3.6 Frame reference mode semantics' of the :ref:`vp9` specification for more details. -+ -+.. c:type:: v4l2_vp9_segmentation -+ -+Encodes the quantization parameters. See section '7.2.10 Segmentation -+params syntax' of the :ref:`vp9` specification for more details. -+ -+.. tabularcolumns:: |p{0.8cm}|p{5cm}|p{11.4cm}| -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_vp9_segmentation -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``feature_data[8][4]`` -+ - Data attached to each feature. Data entry is only valid if the feature -+ is enabled. The array shall be indexed with segment number as the first dimension -+ (0..7) and one of V4L2_VP9_SEG_* as the second dimension. -+ See :ref:`Segment Feature IDs`. -+ * - __u8 -+ - ``feature_enabled[8]`` -+ - Bitmask defining which features are enabled in each segment. The value for each -+ segment is a combination of V4L2_VP9_SEGMENT_FEATURE_ENABLED(id) values where id is -+ one of V4L2_VP9_SEG_*. See :ref:`Segment Feature IDs`. -+ * - __u8 -+ - ``tree_probs[7]`` -+ - Specifies the probability values to be used when decoding a Segment-ID. -+ See '5.15. Segmentation map' section of :ref:`vp9` for more details. -+ * - __u8 -+ - ``pred_probs[3]`` -+ - Specifies the probability values to be used when decoding a -+ Predicted-Segment-ID. See '6.4.14. Get segment id syntax' -+ section of :ref:`vp9` for more details. -+ * - __u8 -+ - ``flags`` -+ - Combination of V4L2_VP9_SEGMENTATION_FLAG_* flags. See -+ :ref:`Segmentation Flags`. -+ * - __u8 -+ - ``reserved[5]`` -+ - Applications and drivers must set this to zero. -+ -+.. _vp9_segment_feature: -+ -+``Segment feature IDs`` -+ -+.. tabularcolumns:: |p{6.0cm}|p{1cm}|p{10.3cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_SEG_LVL_ALT_Q`` -+ - 0 -+ - Quantizer segment feature. -+ * - ``V4L2_VP9_SEG_LVL_ALT_L`` -+ - 1 -+ - Loop filter segment feature. -+ * - ``V4L2_VP9_SEG_LVL_REF_FRAME`` -+ - 2 -+ - Reference frame segment feature. -+ * - ``V4L2_VP9_SEG_LVL_SKIP`` -+ - 3 -+ - Skip segment feature. -+ * - ``V4L2_VP9_SEG_LVL_MAX`` -+ - 4 -+ - Number of segment features. -+ -+.. _vp9_segmentation_flags: -+ -+``Segmentation Flags`` -+ -+.. tabularcolumns:: |p{10.6cm}|p{0.8cm}|p{5.9cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_SEGMENTATION_FLAG_ENABLED`` -+ - 0x01 -+ - Indicates that this frame makes use of the segmentation tool. -+ * - ``V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP`` -+ - 0x02 -+ - Indicates that the segmentation map should be updated during the -+ decoding of this frame. -+ * - ``V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE`` -+ - 0x04 -+ - Indicates that the updates to the segmentation map are coded -+ relative to the existing segmentation map. -+ * - ``V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA`` -+ - 0x08 -+ - Indicates that new parameters are about to be specified for each -+ segment. -+ * - ``V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE`` -+ - 0x10 -+ - Indicates that the segmentation parameters represent the actual values -+ to be used. -+ -+.. c:type:: v4l2_vp9_quantization -+ -+Encodes the quantization parameters. See section '7.2.9 Quantization params -+syntax' of the VP9 specification for more details. -+ -+.. tabularcolumns:: |p{0.8cm}|p{4cm}|p{12.4cm}| -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_vp9_quantization -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``base_q_idx`` -+ - Indicates the base frame qindex. -+ * - __s8 -+ - ``delta_q_y_dc`` -+ - Indicates the Y DC quantizer relative to base_q_idx. -+ * - __s8 -+ - ``delta_q_uv_dc`` -+ - Indicates the UV DC quantizer relative to base_q_idx. -+ * - __s8 -+ - ``delta_q_uv_ac`` -+ - Indicates the UV AC quantizer relative to base_q_idx. -+ * - __u8 -+ - ``reserved[4]`` -+ - Applications and drivers must set this to zero. -+ -+.. c:type:: v4l2_vp9_loop_filter -+ -+This structure contains all loop filter related parameters. See sections -+'7.2.8 Loop filter semantics' of the :ref:`vp9` specification for more details. -+ -+.. tabularcolumns:: |p{0.8cm}|p{4cm}|p{12.4cm}| -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_vp9_loop_filter -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __s8 -+ - ``ref_deltas[4]`` -+ - Contains the adjustment needed for the filter level based on the chosen -+ reference frame. -+ * - __s8 -+ - ``mode_deltas[2]`` -+ - Contains the adjustment needed for the filter level based on the chosen -+ mode. -+ * - __u8 -+ - ``level`` -+ - Indicates the loop filter strength. -+ * - __u8 -+ - ``sharpness`` -+ - Indicates the sharpness level. -+ * - __u8 -+ - ``flags`` -+ - Combination of V4L2_VP9_LOOP_FILTER_FLAG_* flags. -+ See :ref:`Loop Filter Flags `. -+ * - __u8 -+ - ``reserved[7]`` -+ - Applications and drivers must set this to zero. -+ -+ -+.. _vp9_loop_filter_flags: -+ -+``Loop Filter Flags`` -+ -+.. tabularcolumns:: |p{9.6cm}|p{0.5cm}|p{7.2cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED`` -+ - 0x1 -+ - When set, the filter level depends on the mode and reference frame used -+ to predict a block. -+ * - ``V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE`` -+ - 0x2 -+ - When set, the bitstream contains additional syntax elements that -+ specify which mode and reference frame deltas are to be updated. -diff --git a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -index 0ede39907ee2..967fc803ef94 100644 ---- a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -+++ b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -@@ -172,6 +172,21 @@ Compressed Formats - - VP9 compressed video frame. The encoder generates one - compressed frame per buffer, and the decoder requires one - compressed frame per buffer. -+ * .. _V4L2-PIX-FMT-VP9-FRAME: -+ -+ - ``V4L2_PIX_FMT_VP9_FRAME`` -+ - 'VP9F' -+ - VP9 parsed frame, including the frame header, as extracted from the container. -+ This format is adapted for stateless video decoders that implement a -+ VP9 pipeline with the :ref:`stateless_decoder`. -+ Metadata associated with the frame to decode is required to be passed -+ through the ``V4L2_CID_STATELESS_VP9_FRAME`` and -+ the ``V4L2_CID_STATELESS_VP9_COMPRESSED_HDR`` controls. -+ See the :ref:`associated Codec Control IDs `. -+ Exactly one output and one capture buffer must be provided for use with -+ this pixel format. The output buffer must contain the appropriate number -+ of macroblocks to decode a full corresponding frame to the matching -+ capture buffer. - * .. _V4L2-PIX-FMT-HEVC: - - - ``V4L2_PIX_FMT_HEVC`` -diff --git a/Documentation/userspace-api/media/v4l/vidioc-g-ext-ctrls.rst b/Documentation/userspace-api/media/v4l/vidioc-g-ext-ctrls.rst -index fdde0ae6d521..29971a45a2d4 100644 ---- a/Documentation/userspace-api/media/v4l/vidioc-g-ext-ctrls.rst -+++ b/Documentation/userspace-api/media/v4l/vidioc-g-ext-ctrls.rst -@@ -233,6 +233,14 @@ still cause this situation. - - ``p_mpeg2_quantisation`` - - A pointer to a struct :c:type:`v4l2_ctrl_mpeg2_quantisation`. Valid if this control is - of type ``V4L2_CTRL_TYPE_MPEG2_QUANTISATION``. -+ * - struct :c:type:`v4l2_ctrl_vp9_compressed_hdr` * -+ - ``p_vp9_compressed_hdr_probs`` -+ - A pointer to a struct :c:type:`v4l2_ctrl_vp9_compressed_hdr`. Valid if this -+ control is of type ``V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR``. -+ * - struct :c:type:`v4l2_ctrl_vp9_frame` * -+ - ``p_vp9_frame`` -+ - A pointer to a struct :c:type:`v4l2_ctrl_vp9_frame`. Valid if this -+ control is of type ``V4L2_CTRL_TYPE_VP9_FRAME``. - * - struct :c:type:`v4l2_ctrl_hdr10_cll_info` * - - ``p_hdr10_cll`` - - A pointer to a struct :c:type:`v4l2_ctrl_hdr10_cll_info`. Valid if this control is -diff --git a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst -index 2f491c17dd5d..88f630252d98 100644 ---- a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst -+++ b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst -@@ -513,6 +513,18 @@ See also the examples in :ref:`control`. - - n/a - - A struct :c:type:`v4l2_ctrl_hevc_decode_params`, containing HEVC - decoding parameters for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_vp9_compressed_hdr`, containing VP9 -+ probabilities updates for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_VP9_FRAME`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_vp9_frame`, containing VP9 -+ frame decode parameters for stateless video decoders. - - .. raw:: latex - -diff --git a/Documentation/userspace-api/media/videodev2.h.rst.exceptions b/Documentation/userspace-api/media/videodev2.h.rst.exceptions -index eb0b1cd37abd..9cbb7a0c354a 100644 ---- a/Documentation/userspace-api/media/videodev2.h.rst.exceptions -+++ b/Documentation/userspace-api/media/videodev2.h.rst.exceptions -@@ -149,6 +149,8 @@ replace symbol V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_AREA :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_FWHT_PARAMS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_VP8_FRAME :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_VP9_FRAME :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_HDR10_CLL_INFO :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_HDR10_MASTERING_DISPLAY :c:type:`v4l2_ctrl_type` - -diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c -index 70adfc1b9c81..54abe5245dcc 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls-core.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c -@@ -283,6 +283,12 @@ static void std_log(const struct v4l2_ctrl *ctrl) - case V4L2_CTRL_TYPE_MPEG2_PICTURE: - pr_cont("MPEG2_PICTURE"); - break; -+ case V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR: -+ pr_cont("VP9_COMPRESSED_HDR"); -+ break; -+ case V4L2_CTRL_TYPE_VP9_FRAME: -+ pr_cont("VP9_FRAME"); -+ break; - default: - pr_cont("unknown type %d", ctrl->type); - break; -@@ -317,6 +323,168 @@ static void std_log(const struct v4l2_ctrl *ctrl) - #define zero_reserved(s) \ - memset(&(s).reserved, 0, sizeof((s).reserved)) - -+static int -+validate_vp9_lf_params(struct v4l2_vp9_loop_filter *lf) -+{ -+ unsigned int i; -+ -+ if (lf->flags & ~(V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED | -+ V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE)) -+ return -EINVAL; -+ -+ /* That all values are in the accepted range. */ -+ if (lf->level > GENMASK(5, 0)) -+ return -EINVAL; -+ -+ if (lf->sharpness > GENMASK(2, 0)) -+ return -EINVAL; -+ -+ for (i = 0; i < ARRAY_SIZE(lf->ref_deltas); i++) -+ if (lf->ref_deltas[i] < -63 || lf->ref_deltas[i] > 63) -+ return -EINVAL; -+ -+ for (i = 0; i < ARRAY_SIZE(lf->mode_deltas); i++) -+ if (lf->mode_deltas[i] < -63 || lf->mode_deltas[i] > 63) -+ return -EINVAL; -+ -+ zero_reserved(*lf); -+ return 0; -+} -+ -+static int -+validate_vp9_quant_params(struct v4l2_vp9_quantization *quant) -+{ -+ if (quant->delta_q_y_dc < -15 || quant->delta_q_y_dc > 15 || -+ quant->delta_q_uv_dc < -15 || quant->delta_q_uv_dc > 15 || -+ quant->delta_q_uv_ac < -15 || quant->delta_q_uv_ac > 15) -+ return -EINVAL; -+ -+ zero_reserved(*quant); -+ return 0; -+} -+ -+static int -+validate_vp9_seg_params(struct v4l2_vp9_segmentation *seg) -+{ -+ unsigned int i, j; -+ -+ if (seg->flags & ~(V4L2_VP9_SEGMENTATION_FLAG_ENABLED | -+ V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP | -+ V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE | -+ V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA | -+ V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE)) -+ return -EINVAL; -+ -+ for (i = 0; i < ARRAY_SIZE(seg->feature_enabled); i++) { -+ if (seg->feature_enabled[i] & -+ ~V4L2_VP9_SEGMENT_FEATURE_ENABLED_MASK) -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(seg->feature_data); i++) { -+ const int range[] = { 255, 63, 3, 0 }; -+ -+ for (j = 0; j < ARRAY_SIZE(seg->feature_data[j]); j++) { -+ if (seg->feature_data[i][j] < -range[j] || -+ seg->feature_data[i][j] > range[j]) -+ return -EINVAL; -+ } -+ } -+ -+ zero_reserved(*seg); -+ return 0; -+} -+ -+static int -+validate_vp9_compressed_hdr(struct v4l2_ctrl_vp9_compressed_hdr *hdr) -+{ -+ if (hdr->tx_mode > V4L2_VP9_TX_MODE_SELECT) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static int -+validate_vp9_frame(struct v4l2_ctrl_vp9_frame *frame) -+{ -+ int ret; -+ -+ /* Make sure we're not passed invalid flags. */ -+ if (frame->flags & ~(V4L2_VP9_FRAME_FLAG_KEY_FRAME | -+ V4L2_VP9_FRAME_FLAG_SHOW_FRAME | -+ V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT | -+ V4L2_VP9_FRAME_FLAG_INTRA_ONLY | -+ V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV | -+ V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX | -+ V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE | -+ V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING | -+ V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING | -+ V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING)) -+ return -EINVAL; -+ -+ if (frame->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT && -+ frame->flags & V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX) -+ return -EINVAL; -+ -+ if (frame->profile > V4L2_VP9_PROFILE_MAX) -+ return -EINVAL; -+ -+ if (frame->reset_frame_context > V4L2_VP9_RESET_FRAME_CTX_ALL) -+ return -EINVAL; -+ -+ if (frame->frame_context_idx >= V4L2_VP9_NUM_FRAME_CTX) -+ return -EINVAL; -+ -+ /* -+ * Profiles 0 and 1 only support 8-bit depth, profiles 2 and 3 only 10 -+ * and 12 bit depths. -+ */ -+ if ((frame->profile < 2 && frame->bit_depth != 8) || -+ (frame->profile >= 2 && -+ (frame->bit_depth != 10 && frame->bit_depth != 12))) -+ return -EINVAL; -+ -+ /* Profile 0 and 2 only accept YUV 4:2:0. */ -+ if ((frame->profile == 0 || frame->profile == 2) && -+ (!(frame->flags & V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING) || -+ !(frame->flags & V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING))) -+ return -EINVAL; -+ -+ /* Profile 1 and 3 only accept YUV 4:2:2, 4:4:0 and 4:4:4. */ -+ if ((frame->profile == 1 || frame->profile == 3) && -+ ((frame->flags & V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING) && -+ (frame->flags & V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING))) -+ return -EINVAL; -+ -+ if (frame->interpolation_filter > V4L2_VP9_INTERP_FILTER_SWITCHABLE) -+ return -EINVAL; -+ -+ /* -+ * According to the spec, tile_cols_log2 shall be less than or equal -+ * to 6. -+ */ -+ if (frame->tile_cols_log2 > 6) -+ return -EINVAL; -+ -+ if (frame->reference_mode > V4L2_VP9_REFERENCE_MODE_SELECT) -+ return -EINVAL; -+ -+ ret = validate_vp9_lf_params(&frame->lf); -+ if (ret) -+ return ret; -+ -+ ret = validate_vp9_quant_params(&frame->quant); -+ if (ret) -+ return ret; -+ -+ ret = validate_vp9_seg_params(&frame->seg); -+ if (ret) -+ return ret; -+ -+ zero_reserved(*frame); -+ return 0; -+} -+ - /* - * Compound controls validation requires setting unused fields/flags to zero - * in order to properly detect unchanged controls with std_equal's memcmp. -@@ -690,6 +858,12 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, - case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: - break; - -+ case V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR: -+ return validate_vp9_compressed_hdr(p); -+ -+ case V4L2_CTRL_TYPE_VP9_FRAME: -+ return validate_vp9_frame(p); -+ - case V4L2_CTRL_TYPE_AREA: - area = p; - if (!area->width || !area->height) -@@ -1255,6 +1429,12 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, - case V4L2_CTRL_TYPE_HDR10_MASTERING_DISPLAY: - elem_size = sizeof(struct v4l2_ctrl_hdr10_mastering_display); - break; -+ case V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR: -+ elem_size = sizeof(struct v4l2_ctrl_vp9_compressed_hdr); -+ break; -+ case V4L2_CTRL_TYPE_VP9_FRAME: -+ elem_size = sizeof(struct v4l2_ctrl_vp9_frame); -+ break; - case V4L2_CTRL_TYPE_AREA: - elem_size = sizeof(struct v4l2_area); - break; -diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c -index ebe82b6ba6e6..23594568b985 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c -@@ -1177,6 +1177,8 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_STATELESS_MPEG2_SEQUENCE: return "MPEG-2 Sequence Header"; - case V4L2_CID_STATELESS_MPEG2_PICTURE: return "MPEG-2 Picture Header"; - case V4L2_CID_STATELESS_MPEG2_QUANTISATION: return "MPEG-2 Quantisation Matrices"; -+ case V4L2_CID_STATELESS_VP9_COMPRESSED_HDR: return "VP9 Probabilities Updates"; -+ case V4L2_CID_STATELESS_VP9_FRAME: return "VP9 Frame Decode Parameters"; - - /* Colorimetry controls */ - /* Keep the order of the 'case's the same as in v4l2-controls.h! */ -@@ -1498,6 +1500,12 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS: - *type = V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS; - break; -+ case V4L2_CID_STATELESS_VP9_COMPRESSED_HDR: -+ *type = V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR; -+ break; -+ case V4L2_CID_STATELESS_VP9_FRAME: -+ *type = V4L2_CTRL_TYPE_VP9_FRAME; -+ break; - case V4L2_CID_UNIT_CELL_SIZE: - *type = V4L2_CTRL_TYPE_AREA; - *flags |= V4L2_CTRL_FLAG_READ_ONLY; -diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 31d0109ce5a8..51289d4741dc 100644 ---- a/drivers/media/v4l2-core/v4l2-ioctl.c -+++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1413,6 +1413,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) - case V4L2_PIX_FMT_VP8: descr = "VP8"; break; - case V4L2_PIX_FMT_VP8_FRAME: descr = "VP8 Frame"; break; - case V4L2_PIX_FMT_VP9: descr = "VP9"; break; -+ case V4L2_PIX_FMT_VP9_FRAME: descr = "VP9 Frame"; break; - case V4L2_PIX_FMT_HEVC: descr = "HEVC"; break; /* aka H.265 */ - case V4L2_PIX_FMT_HEVC_SLICE: descr = "HEVC Parsed Slice Data"; break; - case V4L2_PIX_FMT_FWHT: descr = "FWHT"; break; /* used in vicodec */ -diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h -index 575b59fbac77..b3ce438f1329 100644 ---- a/include/media/v4l2-ctrls.h -+++ b/include/media/v4l2-ctrls.h -@@ -50,6 +50,8 @@ struct video_device; - * @p_h264_decode_params: Pointer to a struct v4l2_ctrl_h264_decode_params. - * @p_h264_pred_weights: Pointer to a struct v4l2_ctrl_h264_pred_weights. - * @p_vp8_frame: Pointer to a VP8 frame params structure. -+ * @p_vp9_compressed_hdr_probs: Pointer to a VP9 frame compressed header probs structure. -+ * @p_vp9_frame: Pointer to a VP9 frame params structure. - * @p_hevc_sps: Pointer to an HEVC sequence parameter set structure. - * @p_hevc_pps: Pointer to an HEVC picture parameter set structure. - * @p_hevc_slice_params: Pointer to an HEVC slice parameters structure. -@@ -80,6 +82,8 @@ union v4l2_ctrl_ptr { - struct v4l2_ctrl_hevc_sps *p_hevc_sps; - struct v4l2_ctrl_hevc_pps *p_hevc_pps; - struct v4l2_ctrl_hevc_slice_params *p_hevc_slice_params; -+ struct v4l2_ctrl_vp9_compressed_hdr *p_vp9_compressed_hdr_probs; -+ struct v4l2_ctrl_vp9_frame *p_vp9_frame; - struct v4l2_ctrl_hdr10_cll_info *p_hdr10_cll; - struct v4l2_ctrl_hdr10_mastering_display *p_hdr10_mastering; - struct v4l2_area *p_area; -diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h -index 5fea5feb0412..f859b73f0490 100644 ---- a/include/uapi/linux/v4l2-controls.h -+++ b/include/uapi/linux/v4l2-controls.h -@@ -2016,6 +2016,290 @@ struct v4l2_ctrl_hdr10_mastering_display { - __u32 min_display_mastering_luminance; - }; - -+/* Stateless VP9 controls */ -+ -+#define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED 0x1 -+#define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE 0x2 -+ -+/** -+ * struct v4l2_vp9_loop_filter - VP9 loop filter parameters -+ * -+ * @ref_deltas: contains the adjustment needed for the filter level based on the -+ * chosen reference frame. If this syntax element is not present in the bitstream, -+ * users should pass its last value. -+ * @mode_deltas: contains the adjustment needed for the filter level based on the -+ * chosen mode. If this syntax element is not present in the bitstream, users should -+ * pass its last value. -+ * @level: indicates the loop filter strength. -+ * @sharpness: indicates the sharpness level. -+ * @flags: combination of V4L2_VP9_LOOP_FILTER_FLAG_{} flags. -+ * @reserved: padding field. Should be zeroed by applications. -+ * -+ * This structure contains all loop filter related parameters. See sections -+ * '7.2.8 Loop filter semantics' of the VP9 specification for more details. -+ */ -+struct v4l2_vp9_loop_filter { -+ __s8 ref_deltas[4]; -+ __s8 mode_deltas[2]; -+ __u8 level; -+ __u8 sharpness; -+ __u8 flags; -+ __u8 reserved[7]; -+}; -+ -+/** -+ * struct v4l2_vp9_quantization - VP9 quantization parameters -+ * -+ * @base_q_idx: indicates the base frame qindex. -+ * @delta_q_y_dc: indicates the Y DC quantizer relative to base_q_idx. -+ * @delta_q_uv_dc: indicates the UV DC quantizer relative to base_q_idx. -+ * @delta_q_uv_ac: indicates the UV AC quantizer relative to base_q_idx. -+ * @reserved: padding field. Should be zeroed by applications. -+ * -+ * Encodes the quantization parameters. See section '7.2.9 Quantization params -+ * syntax' of the VP9 specification for more details. -+ */ -+struct v4l2_vp9_quantization { -+ __u8 base_q_idx; -+ __s8 delta_q_y_dc; -+ __s8 delta_q_uv_dc; -+ __s8 delta_q_uv_ac; -+ __u8 reserved[4]; -+}; -+ -+#define V4L2_VP9_SEGMENTATION_FLAG_ENABLED 0x01 -+#define V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP 0x02 -+#define V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE 0x04 -+#define V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA 0x08 -+#define V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE 0x10 -+ -+#define V4L2_VP9_SEG_LVL_ALT_Q 0 -+#define V4L2_VP9_SEG_LVL_ALT_L 1 -+#define V4L2_VP9_SEG_LVL_REF_FRAME 2 -+#define V4L2_VP9_SEG_LVL_SKIP 3 -+#define V4L2_VP9_SEG_LVL_MAX 4 -+ -+#define V4L2_VP9_SEGMENT_FEATURE_ENABLED(id) (1 << (id)) -+#define V4L2_VP9_SEGMENT_FEATURE_ENABLED_MASK 0xf -+ -+/** -+ * struct v4l2_vp9_segmentation - VP9 segmentation parameters -+ * -+ * @feature_data: data attached to each feature. Data entry is only valid if -+ * the feature is enabled. The array shall be indexed with segment number as -+ * the first dimension (0..7) and one of V4L2_VP9_SEG_{} as the second dimension. -+ * @feature_enabled: bitmask defining which features are enabled in each segment. -+ * The value for each segment is a combination of V4L2_VP9_SEGMENT_FEATURE_ENABLED(id) -+ * values where id is one of V4L2_VP9_SEG_LVL_{}. -+ * @tree_probs: specifies the probability values to be used when decoding a -+ * Segment-ID. See '5.15. Segmentation map' section of the VP9 specification -+ * for more details. -+ * @pred_probs: specifies the probability values to be used when decoding a -+ * Predicted-Segment-ID. See '6.4.14. Get segment id syntax' section of :ref:`vp9` -+ * for more details. -+ * @flags: combination of V4L2_VP9_SEGMENTATION_FLAG_{} flags. -+ * @reserved: padding field. Should be zeroed by applications. -+ * -+ * Encodes the quantization parameters. See section '7.2.10 Segmentation params syntax' of -+ * the VP9 specification for more details. -+ */ -+struct v4l2_vp9_segmentation { -+ __s16 feature_data[8][4]; -+ __u8 feature_enabled[8]; -+ __u8 tree_probs[7]; -+ __u8 pred_probs[3]; -+ __u8 flags; -+ __u8 reserved[5]; -+}; -+ -+#define V4L2_VP9_FRAME_FLAG_KEY_FRAME 0x001 -+#define V4L2_VP9_FRAME_FLAG_SHOW_FRAME 0x002 -+#define V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT 0x004 -+#define V4L2_VP9_FRAME_FLAG_INTRA_ONLY 0x008 -+#define V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV 0x010 -+#define V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX 0x020 -+#define V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE 0x040 -+#define V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING 0x080 -+#define V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING 0x100 -+#define V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING 0x200 -+ -+#define V4L2_VP9_SIGN_BIAS_LAST 0x1 -+#define V4L2_VP9_SIGN_BIAS_GOLDEN 0x2 -+#define V4L2_VP9_SIGN_BIAS_ALT 0x4 -+ -+#define V4L2_VP9_RESET_FRAME_CTX_NONE 0 -+#define V4L2_VP9_RESET_FRAME_CTX_SPEC 1 -+#define V4L2_VP9_RESET_FRAME_CTX_ALL 2 -+ -+#define V4L2_VP9_INTERP_FILTER_EIGHTTAP 0 -+#define V4L2_VP9_INTERP_FILTER_EIGHTTAP_SMOOTH 1 -+#define V4L2_VP9_INTERP_FILTER_EIGHTTAP_SHARP 2 -+#define V4L2_VP9_INTERP_FILTER_BILINEAR 3 -+#define V4L2_VP9_INTERP_FILTER_SWITCHABLE 4 -+ -+#define V4L2_VP9_REFERENCE_MODE_SINGLE_REFERENCE 0 -+#define V4L2_VP9_REFERENCE_MODE_COMPOUND_REFERENCE 1 -+#define V4L2_VP9_REFERENCE_MODE_SELECT 2 -+ -+#define V4L2_VP9_PROFILE_MAX 3 -+ -+#define V4L2_CID_STATELESS_VP9_FRAME (V4L2_CID_CODEC_STATELESS_BASE + 300) -+/** -+ * struct v4l2_ctrl_vp9_frame - VP9 frame decoding control -+ * -+ * @lf: loop filter parameters. See &v4l2_vp9_loop_filter for more details. -+ * @quant: quantization parameters. See &v4l2_vp9_quantization for more details. -+ * @seg: segmentation parameters. See &v4l2_vp9_segmentation for more details. -+ * @flags: combination of V4L2_VP9_FRAME_FLAG_{} flags. -+ * @compressed_header_size: compressed header size in bytes. -+ * @uncompressed_header_size: uncompressed header size in bytes. -+ * @frame_width_minus_1: add 1 to it and you'll get the frame width expressed in pixels. -+ * @frame_height_minus_1: add 1 to it and you'll get the frame height expressed in pixels. -+ * @render_width_minus_1: add 1 to it and you'll get the expected render width expressed in -+ * pixels. This is not used during the decoding process but might be used by HW scalers -+ * to prepare a frame that's ready for scanout. -+ * @render_height_minus_1: add 1 to it and you'll get the expected render height expressed in -+ * pixels. This is not used during the decoding process but might be used by HW scalers -+ * to prepare a frame that's ready for scanout. -+ * @last_frame_ts: "last" reference buffer timestamp. -+ * The timestamp refers to the timestamp field in struct v4l2_buffer. -+ * Use v4l2_timeval_to_ns() to convert the struct timeval to a __u64. -+ * @golden_frame_ts: "golden" reference buffer timestamp. -+ * The timestamp refers to the timestamp field in struct v4l2_buffer. -+ * Use v4l2_timeval_to_ns() to convert the struct timeval to a __u64. -+ * @alt_frame_ts: "alt" reference buffer timestamp. -+ * The timestamp refers to the timestamp field in struct v4l2_buffer. -+ * Use v4l2_timeval_to_ns() to convert the struct timeval to a __u64. -+ * @ref_frame_sign_bias: a bitfield specifying whether the sign bias is set for a given -+ * reference frame. Either of V4L2_VP9_SIGN_BIAS_{}. -+ * @reset_frame_context: specifies whether the frame context should be reset to default values. -+ * Either of V4L2_VP9_RESET_FRAME_CTX_{}. -+ * @frame_context_idx: frame context that should be used/updated. -+ * @profile: VP9 profile. Can be 0, 1, 2 or 3. -+ * @bit_depth: bits per components. Can be 8, 10 or 12. Note that not all profiles support -+ * 10 and/or 12 bits depths. -+ * @interpolation_filter: specifies the filter selection used for performing inter prediction. -+ * Set to one of V4L2_VP9_INTERP_FILTER_{}. -+ * @tile_cols_log2: specifies the base 2 logarithm of the width of each tile (where the width -+ * is measured in units of 8x8 blocks). Shall be less than or equal to 6. -+ * @tile_rows_log2: specifies the base 2 logarithm of the height of each tile (where the height -+ * is measured in units of 8x8 blocks). -+ * @reference_mode: specifies the type of inter prediction to be used. -+ * Set to one of V4L2_VP9_REFERENCE_MODE_{}. -+ * @reserved: padding field. Should be zeroed by applications. -+ */ -+struct v4l2_ctrl_vp9_frame { -+ struct v4l2_vp9_loop_filter lf; -+ struct v4l2_vp9_quantization quant; -+ struct v4l2_vp9_segmentation seg; -+ __u32 flags; -+ __u16 compressed_header_size; -+ __u16 uncompressed_header_size; -+ __u16 frame_width_minus_1; -+ __u16 frame_height_minus_1; -+ __u16 render_width_minus_1; -+ __u16 render_height_minus_1; -+ __u64 last_frame_ts; -+ __u64 golden_frame_ts; -+ __u64 alt_frame_ts; -+ __u8 ref_frame_sign_bias; -+ __u8 reset_frame_context; -+ __u8 frame_context_idx; -+ __u8 profile; -+ __u8 bit_depth; -+ __u8 interpolation_filter; -+ __u8 tile_cols_log2; -+ __u8 tile_rows_log2; -+ __u8 reference_mode; -+ __u8 reserved[7]; -+}; -+ -+#define V4L2_VP9_NUM_FRAME_CTX 4 -+ -+/** -+ * struct v4l2_vp9_mv_probs - VP9 Motion vector probability updates -+ * @joint: motion vector joint probability updates. -+ * @sign: motion vector sign probability updates. -+ * @classes: motion vector class probability updates. -+ * @class0_bit: motion vector class0 bit probability updates. -+ * @bits: motion vector bits probability updates. -+ * @class0_fr: motion vector class0 fractional bit probability updates. -+ * @fr: motion vector fractional bit probability updates. -+ * @class0_hp: motion vector class0 high precision fractional bit probability updates. -+ * @hp: motion vector high precision fractional bit probability updates. -+ * -+ * This structure contains new values of motion vector probabilities. -+ * A value of zero in an array element means there is no update of the relevant probability. -+ * See `struct v4l2_vp9_prob_updates` for details. -+ */ -+struct v4l2_vp9_mv_probs { -+ __u8 joint[3]; -+ __u8 sign[2]; -+ __u8 classes[2][10]; -+ __u8 class0_bit[2]; -+ __u8 bits[2][10]; -+ __u8 class0_fr[2][2][3]; -+ __u8 fr[2][3]; -+ __u8 class0_hp[2]; -+ __u8 hp[2]; -+}; -+ -+#define V4L2_CID_STATELESS_VP9_COMPRESSED_HDR (V4L2_CID_CODEC_STATELESS_BASE + 301) -+ -+#define V4L2_VP9_TX_MODE_ONLY_4X4 0 -+#define V4L2_VP9_TX_MODE_ALLOW_8X8 1 -+#define V4L2_VP9_TX_MODE_ALLOW_16X16 2 -+#define V4L2_VP9_TX_MODE_ALLOW_32X32 3 -+#define V4L2_VP9_TX_MODE_SELECT 4 -+ -+/** -+ * struct v4l2_ctrl_vp9_compressed_hdr - VP9 probability updates control -+ * @tx_mode: specifies the TX mode. Set to one of V4L2_VP9_TX_MODE_{}. -+ * @tx8: TX 8x8 probability updates. -+ * @tx16: TX 16x16 probability updates. -+ * @tx32: TX 32x32 probability updates. -+ * @coef: coefficient probability updates. -+ * @skip: skip probability updates. -+ * @inter_mode: inter mode probability updates. -+ * @interp_filter: interpolation filter probability updates. -+ * @is_inter: is inter-block probability updates. -+ * @comp_mode: compound prediction mode probability updates. -+ * @single_ref: single ref probability updates. -+ * @comp_ref: compound ref probability updates. -+ * @y_mode: Y prediction mode probability updates. -+ * @uv_mode: UV prediction mode probability updates. -+ * @partition: partition probability updates. -+ * @mv: motion vector probability updates. -+ * -+ * This structure holds the probabilities update as parsed in the compressed -+ * header (Spec 6.3). These values represent the value of probability update after -+ * being translated with inv_map_table[] (see 6.3.5). A value of zero in an array element -+ * means that there is no update of the relevant probability. -+ * -+ * This control is optional and needs to be used when dealing with the hardware which is -+ * not capable of parsing the compressed header itself. Only drivers which need it will -+ * implement it. -+ */ -+struct v4l2_ctrl_vp9_compressed_hdr { -+ __u8 tx_mode; -+ __u8 tx8[2][1]; -+ __u8 tx16[2][2]; -+ __u8 tx32[2][3]; -+ __u8 coef[4][2][2][6][6][3]; -+ __u8 skip[3]; -+ __u8 inter_mode[7][3]; -+ __u8 interp_filter[4][2]; -+ __u8 is_inter[4]; -+ __u8 comp_mode[5]; -+ __u8 single_ref[5][2]; -+ __u8 comp_ref[5]; -+ __u8 y_mode[4][9]; -+ __u8 uv_mode[10][9]; -+ __u8 partition[16][3]; -+ -+ struct v4l2_vp9_mv_probs mv; -+}; -+ - /* MPEG-compression definitions kept for backwards compatibility */ - #ifndef __KERNEL__ - #define V4L2_CTRL_CLASS_MPEG V4L2_CTRL_CLASS_CODEC -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index f118fe7a9f58..df8b9c486ba1 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -703,6 +703,7 @@ struct v4l2_pix_format { - #define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') /* VP8 */ - #define V4L2_PIX_FMT_VP8_FRAME v4l2_fourcc('V', 'P', '8', 'F') /* VP8 parsed frame */ - #define V4L2_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0') /* VP9 */ -+#define V4L2_PIX_FMT_VP9_FRAME v4l2_fourcc('V', 'P', '9', 'F') /* VP9 parsed frame */ - #define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* HEVC aka H.265 */ - #define V4L2_PIX_FMT_FWHT v4l2_fourcc('F', 'W', 'H', 'T') /* Fast Walsh Hadamard Transform (vicodec) */ - #define V4L2_PIX_FMT_FWHT_STATELESS v4l2_fourcc('S', 'F', 'W', 'H') /* Stateless FWHT (vicodec) */ -@@ -1759,6 +1760,8 @@ struct v4l2_ext_control { - struct v4l2_ctrl_mpeg2_sequence __user *p_mpeg2_sequence; - struct v4l2_ctrl_mpeg2_picture __user *p_mpeg2_picture; - struct v4l2_ctrl_mpeg2_quantisation __user *p_mpeg2_quantisation; -+ struct v4l2_ctrl_vp9_compressed_hdr __user *p_vp9_compressed_hdr_probs; -+ struct v4l2_ctrl_vp9_frame __user *p_vp9_frame; - void __user *ptr; - }; - } __attribute__ ((packed)); -@@ -1823,6 +1826,9 @@ enum v4l2_ctrl_type { - V4L2_CTRL_TYPE_MPEG2_QUANTISATION = 0x0250, - V4L2_CTRL_TYPE_MPEG2_SEQUENCE = 0x0251, - V4L2_CTRL_TYPE_MPEG2_PICTURE = 0x0252, -+ -+ V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR = 0x0260, -+ V4L2_CTRL_TYPE_VP9_FRAME = 0x0261, - }; - - /* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */ diff --git a/projects/NXP/devices/iMX8/patches/linux/0072-media-Add-VP9-v4l2-library.patch b/projects/NXP/devices/iMX8/patches/linux/0072-media-Add-VP9-v4l2-library.patch deleted file mode 100644 index 62f9c5091c..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0072-media-Add-VP9-v4l2-library.patch +++ /dev/null @@ -1,2141 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:36 +0100 -Subject: [PATCH] media: Add VP9 v4l2 library - -Provide code common to vp9 drivers in one central location. - -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil ---- - drivers/media/v4l2-core/Kconfig | 4 + - drivers/media/v4l2-core/Makefile | 1 + - drivers/media/v4l2-core/v4l2-vp9.c | 1850 ++++++++++++++++++++++++++++ - include/media/v4l2-vp9.h | 233 ++++ - 4 files changed, 2088 insertions(+) - create mode 100644 drivers/media/v4l2-core/v4l2-vp9.c - create mode 100644 include/media/v4l2-vp9.h - -diff --git a/drivers/media/v4l2-core/Kconfig b/drivers/media/v4l2-core/Kconfig -index 02dc1787e953..6ee75c6c820e 100644 ---- a/drivers/media/v4l2-core/Kconfig -+++ b/drivers/media/v4l2-core/Kconfig -@@ -52,6 +52,10 @@ config V4L2_JPEG_HELPER - config V4L2_H264 - tristate - -+# Used by drivers that need v4l2-vp9.ko -+config V4L2_VP9 -+ tristate -+ - # Used by drivers that need v4l2-mem2mem.ko - config V4L2_MEM2MEM_DEV - tristate -diff --git a/drivers/media/v4l2-core/Makefile b/drivers/media/v4l2-core/Makefile -index 66a78c556c98..83fac5c746f5 100644 ---- a/drivers/media/v4l2-core/Makefile -+++ b/drivers/media/v4l2-core/Makefile -@@ -24,6 +24,7 @@ obj-$(CONFIG_VIDEO_TUNER) += tuner.o - - obj-$(CONFIG_V4L2_MEM2MEM_DEV) += v4l2-mem2mem.o - obj-$(CONFIG_V4L2_H264) += v4l2-h264.o -+obj-$(CONFIG_V4L2_VP9) += v4l2-vp9.o - - obj-$(CONFIG_V4L2_FLASH_LED_CLASS) += v4l2-flash-led-class.o - -diff --git a/drivers/media/v4l2-core/v4l2-vp9.c b/drivers/media/v4l2-core/v4l2-vp9.c -new file mode 100644 -index 000000000000..859589f1fd35 ---- /dev/null -+++ b/drivers/media/v4l2-core/v4l2-vp9.c -@@ -0,0 +1,1850 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * V4L2 VP9 helpers. -+ * -+ * Copyright (C) 2021 Collabora, Ltd. -+ * -+ * Author: Andrzej Pietrasiewicz -+ */ -+ -+#include -+ -+#include -+ -+const u8 v4l2_vp9_kf_y_mode_prob[10][10][9] = { -+ { -+ /* above = dc */ -+ { 137, 30, 42, 148, 151, 207, 70, 52, 91 }, /*left = dc */ -+ { 92, 45, 102, 136, 116, 180, 74, 90, 100 }, /*left = v */ -+ { 73, 32, 19, 187, 222, 215, 46, 34, 100 }, /*left = h */ -+ { 91, 30, 32, 116, 121, 186, 93, 86, 94 }, /*left = d45 */ -+ { 72, 35, 36, 149, 68, 206, 68, 63, 105 }, /*left = d135*/ -+ { 73, 31, 28, 138, 57, 124, 55, 122, 151 }, /*left = d117*/ -+ { 67, 23, 21, 140, 126, 197, 40, 37, 171 }, /*left = d153*/ -+ { 86, 27, 28, 128, 154, 212, 45, 43, 53 }, /*left = d207*/ -+ { 74, 32, 27, 107, 86, 160, 63, 134, 102 }, /*left = d63 */ -+ { 59, 67, 44, 140, 161, 202, 78, 67, 119 }, /*left = tm */ -+ }, { /* above = v */ -+ { 63, 36, 126, 146, 123, 158, 60, 90, 96 }, /*left = dc */ -+ { 43, 46, 168, 134, 107, 128, 69, 142, 92 }, /*left = v */ -+ { 44, 29, 68, 159, 201, 177, 50, 57, 77 }, /*left = h */ -+ { 58, 38, 76, 114, 97, 172, 78, 133, 92 }, /*left = d45 */ -+ { 46, 41, 76, 140, 63, 184, 69, 112, 57 }, /*left = d135*/ -+ { 38, 32, 85, 140, 46, 112, 54, 151, 133 }, /*left = d117*/ -+ { 39, 27, 61, 131, 110, 175, 44, 75, 136 }, /*left = d153*/ -+ { 52, 30, 74, 113, 130, 175, 51, 64, 58 }, /*left = d207*/ -+ { 47, 35, 80, 100, 74, 143, 64, 163, 74 }, /*left = d63 */ -+ { 36, 61, 116, 114, 128, 162, 80, 125, 82 }, /*left = tm */ -+ }, { /* above = h */ -+ { 82, 26, 26, 171, 208, 204, 44, 32, 105 }, /*left = dc */ -+ { 55, 44, 68, 166, 179, 192, 57, 57, 108 }, /*left = v */ -+ { 42, 26, 11, 199, 241, 228, 23, 15, 85 }, /*left = h */ -+ { 68, 42, 19, 131, 160, 199, 55, 52, 83 }, /*left = d45 */ -+ { 58, 50, 25, 139, 115, 232, 39, 52, 118 }, /*left = d135*/ -+ { 50, 35, 33, 153, 104, 162, 64, 59, 131 }, /*left = d117*/ -+ { 44, 24, 16, 150, 177, 202, 33, 19, 156 }, /*left = d153*/ -+ { 55, 27, 12, 153, 203, 218, 26, 27, 49 }, /*left = d207*/ -+ { 53, 49, 21, 110, 116, 168, 59, 80, 76 }, /*left = d63 */ -+ { 38, 72, 19, 168, 203, 212, 50, 50, 107 }, /*left = tm */ -+ }, { /* above = d45 */ -+ { 103, 26, 36, 129, 132, 201, 83, 80, 93 }, /*left = dc */ -+ { 59, 38, 83, 112, 103, 162, 98, 136, 90 }, /*left = v */ -+ { 62, 30, 23, 158, 200, 207, 59, 57, 50 }, /*left = h */ -+ { 67, 30, 29, 84, 86, 191, 102, 91, 59 }, /*left = d45 */ -+ { 60, 32, 33, 112, 71, 220, 64, 89, 104 }, /*left = d135*/ -+ { 53, 26, 34, 130, 56, 149, 84, 120, 103 }, /*left = d117*/ -+ { 53, 21, 23, 133, 109, 210, 56, 77, 172 }, /*left = d153*/ -+ { 77, 19, 29, 112, 142, 228, 55, 66, 36 }, /*left = d207*/ -+ { 61, 29, 29, 93, 97, 165, 83, 175, 162 }, /*left = d63 */ -+ { 47, 47, 43, 114, 137, 181, 100, 99, 95 }, /*left = tm */ -+ }, { /* above = d135 */ -+ { 69, 23, 29, 128, 83, 199, 46, 44, 101 }, /*left = dc */ -+ { 53, 40, 55, 139, 69, 183, 61, 80, 110 }, /*left = v */ -+ { 40, 29, 19, 161, 180, 207, 43, 24, 91 }, /*left = h */ -+ { 60, 34, 19, 105, 61, 198, 53, 64, 89 }, /*left = d45 */ -+ { 52, 31, 22, 158, 40, 209, 58, 62, 89 }, /*left = d135*/ -+ { 44, 31, 29, 147, 46, 158, 56, 102, 198 }, /*left = d117*/ -+ { 35, 19, 12, 135, 87, 209, 41, 45, 167 }, /*left = d153*/ -+ { 55, 25, 21, 118, 95, 215, 38, 39, 66 }, /*left = d207*/ -+ { 51, 38, 25, 113, 58, 164, 70, 93, 97 }, /*left = d63 */ -+ { 47, 54, 34, 146, 108, 203, 72, 103, 151 }, /*left = tm */ -+ }, { /* above = d117 */ -+ { 64, 19, 37, 156, 66, 138, 49, 95, 133 }, /*left = dc */ -+ { 46, 27, 80, 150, 55, 124, 55, 121, 135 }, /*left = v */ -+ { 36, 23, 27, 165, 149, 166, 54, 64, 118 }, /*left = h */ -+ { 53, 21, 36, 131, 63, 163, 60, 109, 81 }, /*left = d45 */ -+ { 40, 26, 35, 154, 40, 185, 51, 97, 123 }, /*left = d135*/ -+ { 35, 19, 34, 179, 19, 97, 48, 129, 124 }, /*left = d117*/ -+ { 36, 20, 26, 136, 62, 164, 33, 77, 154 }, /*left = d153*/ -+ { 45, 18, 32, 130, 90, 157, 40, 79, 91 }, /*left = d207*/ -+ { 45, 26, 28, 129, 45, 129, 49, 147, 123 }, /*left = d63 */ -+ { 38, 44, 51, 136, 74, 162, 57, 97, 121 }, /*left = tm */ -+ }, { /* above = d153 */ -+ { 75, 17, 22, 136, 138, 185, 32, 34, 166 }, /*left = dc */ -+ { 56, 39, 58, 133, 117, 173, 48, 53, 187 }, /*left = v */ -+ { 35, 21, 12, 161, 212, 207, 20, 23, 145 }, /*left = h */ -+ { 56, 29, 19, 117, 109, 181, 55, 68, 112 }, /*left = d45 */ -+ { 47, 29, 17, 153, 64, 220, 59, 51, 114 }, /*left = d135*/ -+ { 46, 16, 24, 136, 76, 147, 41, 64, 172 }, /*left = d117*/ -+ { 34, 17, 11, 108, 152, 187, 13, 15, 209 }, /*left = d153*/ -+ { 51, 24, 14, 115, 133, 209, 32, 26, 104 }, /*left = d207*/ -+ { 55, 30, 18, 122, 79, 179, 44, 88, 116 }, /*left = d63 */ -+ { 37, 49, 25, 129, 168, 164, 41, 54, 148 }, /*left = tm */ -+ }, { /* above = d207 */ -+ { 82, 22, 32, 127, 143, 213, 39, 41, 70 }, /*left = dc */ -+ { 62, 44, 61, 123, 105, 189, 48, 57, 64 }, /*left = v */ -+ { 47, 25, 17, 175, 222, 220, 24, 30, 86 }, /*left = h */ -+ { 68, 36, 17, 106, 102, 206, 59, 74, 74 }, /*left = d45 */ -+ { 57, 39, 23, 151, 68, 216, 55, 63, 58 }, /*left = d135*/ -+ { 49, 30, 35, 141, 70, 168, 82, 40, 115 }, /*left = d117*/ -+ { 51, 25, 15, 136, 129, 202, 38, 35, 139 }, /*left = d153*/ -+ { 68, 26, 16, 111, 141, 215, 29, 28, 28 }, /*left = d207*/ -+ { 59, 39, 19, 114, 75, 180, 77, 104, 42 }, /*left = d63 */ -+ { 40, 61, 26, 126, 152, 206, 61, 59, 93 }, /*left = tm */ -+ }, { /* above = d63 */ -+ { 78, 23, 39, 111, 117, 170, 74, 124, 94 }, /*left = dc */ -+ { 48, 34, 86, 101, 92, 146, 78, 179, 134 }, /*left = v */ -+ { 47, 22, 24, 138, 187, 178, 68, 69, 59 }, /*left = h */ -+ { 56, 25, 33, 105, 112, 187, 95, 177, 129 }, /*left = d45 */ -+ { 48, 31, 27, 114, 63, 183, 82, 116, 56 }, /*left = d135*/ -+ { 43, 28, 37, 121, 63, 123, 61, 192, 169 }, /*left = d117*/ -+ { 42, 17, 24, 109, 97, 177, 56, 76, 122 }, /*left = d153*/ -+ { 58, 18, 28, 105, 139, 182, 70, 92, 63 }, /*left = d207*/ -+ { 46, 23, 32, 74, 86, 150, 67, 183, 88 }, /*left = d63 */ -+ { 36, 38, 48, 92, 122, 165, 88, 137, 91 }, /*left = tm */ -+ }, { /* above = tm */ -+ { 65, 70, 60, 155, 159, 199, 61, 60, 81 }, /*left = dc */ -+ { 44, 78, 115, 132, 119, 173, 71, 112, 93 }, /*left = v */ -+ { 39, 38, 21, 184, 227, 206, 42, 32, 64 }, /*left = h */ -+ { 58, 47, 36, 124, 137, 193, 80, 82, 78 }, /*left = d45 */ -+ { 49, 50, 35, 144, 95, 205, 63, 78, 59 }, /*left = d135*/ -+ { 41, 53, 52, 148, 71, 142, 65, 128, 51 }, /*left = d117*/ -+ { 40, 36, 28, 143, 143, 202, 40, 55, 137 }, /*left = d153*/ -+ { 52, 34, 29, 129, 183, 227, 42, 35, 43 }, /*left = d207*/ -+ { 42, 44, 44, 104, 105, 164, 64, 130, 80 }, /*left = d63 */ -+ { 43, 81, 53, 140, 169, 204, 68, 84, 72 }, /*left = tm */ -+ } -+}; -+EXPORT_SYMBOL_GPL(v4l2_vp9_kf_y_mode_prob); -+ -+const u8 v4l2_vp9_kf_partition_probs[16][3] = { -+ /* 8x8 -> 4x4 */ -+ { 158, 97, 94 }, /* a/l both not split */ -+ { 93, 24, 99 }, /* a split, l not split */ -+ { 85, 119, 44 }, /* l split, a not split */ -+ { 62, 59, 67 }, /* a/l both split */ -+ /* 16x16 -> 8x8 */ -+ { 149, 53, 53 }, /* a/l both not split */ -+ { 94, 20, 48 }, /* a split, l not split */ -+ { 83, 53, 24 }, /* l split, a not split */ -+ { 52, 18, 18 }, /* a/l both split */ -+ /* 32x32 -> 16x16 */ -+ { 150, 40, 39 }, /* a/l both not split */ -+ { 78, 12, 26 }, /* a split, l not split */ -+ { 67, 33, 11 }, /* l split, a not split */ -+ { 24, 7, 5 }, /* a/l both split */ -+ /* 64x64 -> 32x32 */ -+ { 174, 35, 49 }, /* a/l both not split */ -+ { 68, 11, 27 }, /* a split, l not split */ -+ { 57, 15, 9 }, /* l split, a not split */ -+ { 12, 3, 3 }, /* a/l both split */ -+}; -+EXPORT_SYMBOL_GPL(v4l2_vp9_kf_partition_probs); -+ -+const u8 v4l2_vp9_kf_uv_mode_prob[10][9] = { -+ { 144, 11, 54, 157, 195, 130, 46, 58, 108 }, /* y = dc */ -+ { 118, 15, 123, 148, 131, 101, 44, 93, 131 }, /* y = v */ -+ { 113, 12, 23, 188, 226, 142, 26, 32, 125 }, /* y = h */ -+ { 120, 11, 50, 123, 163, 135, 64, 77, 103 }, /* y = d45 */ -+ { 113, 9, 36, 155, 111, 157, 32, 44, 161 }, /* y = d135 */ -+ { 116, 9, 55, 176, 76, 96, 37, 61, 149 }, /* y = d117 */ -+ { 115, 9, 28, 141, 161, 167, 21, 25, 193 }, /* y = d153 */ -+ { 120, 12, 32, 145, 195, 142, 32, 38, 86 }, /* y = d207 */ -+ { 116, 12, 64, 120, 140, 125, 49, 115, 121 }, /* y = d63 */ -+ { 102, 19, 66, 162, 182, 122, 35, 59, 128 } /* y = tm */ -+}; -+EXPORT_SYMBOL_GPL(v4l2_vp9_kf_uv_mode_prob); -+ -+const struct v4l2_vp9_frame_context v4l2_vp9_default_probs = { -+ .tx8 = { -+ { 100 }, -+ { 66 }, -+ }, -+ .tx16 = { -+ { 20, 152 }, -+ { 15, 101 }, -+ }, -+ .tx32 = { -+ { 3, 136, 37 }, -+ { 5, 52, 13 }, -+ }, -+ .coef = { -+ { /* tx = 4x4 */ -+ { /* block Type 0 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 195, 29, 183 }, -+ { 84, 49, 136 }, -+ { 8, 42, 71 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 31, 107, 169 }, -+ { 35, 99, 159 }, -+ { 17, 82, 140 }, -+ { 8, 66, 114 }, -+ { 2, 44, 76 }, -+ { 1, 19, 32 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 40, 132, 201 }, -+ { 29, 114, 187 }, -+ { 13, 91, 157 }, -+ { 7, 75, 127 }, -+ { 3, 58, 95 }, -+ { 1, 28, 47 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 69, 142, 221 }, -+ { 42, 122, 201 }, -+ { 15, 91, 159 }, -+ { 6, 67, 121 }, -+ { 1, 42, 77 }, -+ { 1, 17, 31 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 102, 148, 228 }, -+ { 67, 117, 204 }, -+ { 17, 82, 154 }, -+ { 6, 59, 114 }, -+ { 2, 39, 75 }, -+ { 1, 15, 29 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 156, 57, 233 }, -+ { 119, 57, 212 }, -+ { 58, 48, 163 }, -+ { 29, 40, 124 }, -+ { 12, 30, 81 }, -+ { 3, 12, 31 } -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 191, 107, 226 }, -+ { 124, 117, 204 }, -+ { 25, 99, 155 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 29, 148, 210 }, -+ { 37, 126, 194 }, -+ { 8, 93, 157 }, -+ { 2, 68, 118 }, -+ { 1, 39, 69 }, -+ { 1, 17, 33 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 41, 151, 213 }, -+ { 27, 123, 193 }, -+ { 3, 82, 144 }, -+ { 1, 58, 105 }, -+ { 1, 32, 60 }, -+ { 1, 13, 26 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 59, 159, 220 }, -+ { 23, 126, 198 }, -+ { 4, 88, 151 }, -+ { 1, 66, 114 }, -+ { 1, 38, 71 }, -+ { 1, 18, 34 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 114, 136, 232 }, -+ { 51, 114, 207 }, -+ { 11, 83, 155 }, -+ { 3, 56, 105 }, -+ { 1, 33, 65 }, -+ { 1, 17, 34 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 149, 65, 234 }, -+ { 121, 57, 215 }, -+ { 61, 49, 166 }, -+ { 28, 36, 114 }, -+ { 12, 25, 76 }, -+ { 3, 16, 42 }, -+ }, -+ }, -+ }, -+ { /* block Type 1 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 214, 49, 220 }, -+ { 132, 63, 188 }, -+ { 42, 65, 137 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 85, 137, 221 }, -+ { 104, 131, 216 }, -+ { 49, 111, 192 }, -+ { 21, 87, 155 }, -+ { 2, 49, 87 }, -+ { 1, 16, 28 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 89, 163, 230 }, -+ { 90, 137, 220 }, -+ { 29, 100, 183 }, -+ { 10, 70, 135 }, -+ { 2, 42, 81 }, -+ { 1, 17, 33 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 108, 167, 237 }, -+ { 55, 133, 222 }, -+ { 15, 97, 179 }, -+ { 4, 72, 135 }, -+ { 1, 45, 85 }, -+ { 1, 19, 38 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 124, 146, 240 }, -+ { 66, 124, 224 }, -+ { 17, 88, 175 }, -+ { 4, 58, 122 }, -+ { 1, 36, 75 }, -+ { 1, 18, 37 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 141, 79, 241 }, -+ { 126, 70, 227 }, -+ { 66, 58, 182 }, -+ { 30, 44, 136 }, -+ { 12, 34, 96 }, -+ { 2, 20, 47 }, -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 229, 99, 249 }, -+ { 143, 111, 235 }, -+ { 46, 109, 192 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 82, 158, 236 }, -+ { 94, 146, 224 }, -+ { 25, 117, 191 }, -+ { 9, 87, 149 }, -+ { 3, 56, 99 }, -+ { 1, 33, 57 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 83, 167, 237 }, -+ { 68, 145, 222 }, -+ { 10, 103, 177 }, -+ { 2, 72, 131 }, -+ { 1, 41, 79 }, -+ { 1, 20, 39 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 99, 167, 239 }, -+ { 47, 141, 224 }, -+ { 10, 104, 178 }, -+ { 2, 73, 133 }, -+ { 1, 44, 85 }, -+ { 1, 22, 47 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 127, 145, 243 }, -+ { 71, 129, 228 }, -+ { 17, 93, 177 }, -+ { 3, 61, 124 }, -+ { 1, 41, 84 }, -+ { 1, 21, 52 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 157, 78, 244 }, -+ { 140, 72, 231 }, -+ { 69, 58, 184 }, -+ { 31, 44, 137 }, -+ { 14, 38, 105 }, -+ { 8, 23, 61 }, -+ }, -+ }, -+ }, -+ }, -+ { /* tx = 8x8 */ -+ { /* block Type 0 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 125, 34, 187 }, -+ { 52, 41, 133 }, -+ { 6, 31, 56 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 37, 109, 153 }, -+ { 51, 102, 147 }, -+ { 23, 87, 128 }, -+ { 8, 67, 101 }, -+ { 1, 41, 63 }, -+ { 1, 19, 29 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 31, 154, 185 }, -+ { 17, 127, 175 }, -+ { 6, 96, 145 }, -+ { 2, 73, 114 }, -+ { 1, 51, 82 }, -+ { 1, 28, 45 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 23, 163, 200 }, -+ { 10, 131, 185 }, -+ { 2, 93, 148 }, -+ { 1, 67, 111 }, -+ { 1, 41, 69 }, -+ { 1, 14, 24 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 29, 176, 217 }, -+ { 12, 145, 201 }, -+ { 3, 101, 156 }, -+ { 1, 69, 111 }, -+ { 1, 39, 63 }, -+ { 1, 14, 23 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 57, 192, 233 }, -+ { 25, 154, 215 }, -+ { 6, 109, 167 }, -+ { 3, 78, 118 }, -+ { 1, 48, 69 }, -+ { 1, 21, 29 }, -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 202, 105, 245 }, -+ { 108, 106, 216 }, -+ { 18, 90, 144 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 33, 172, 219 }, -+ { 64, 149, 206 }, -+ { 14, 117, 177 }, -+ { 5, 90, 141 }, -+ { 2, 61, 95 }, -+ { 1, 37, 57 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 33, 179, 220 }, -+ { 11, 140, 198 }, -+ { 1, 89, 148 }, -+ { 1, 60, 104 }, -+ { 1, 33, 57 }, -+ { 1, 12, 21 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 30, 181, 221 }, -+ { 8, 141, 198 }, -+ { 1, 87, 145 }, -+ { 1, 58, 100 }, -+ { 1, 31, 55 }, -+ { 1, 12, 20 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 32, 186, 224 }, -+ { 7, 142, 198 }, -+ { 1, 86, 143 }, -+ { 1, 58, 100 }, -+ { 1, 31, 55 }, -+ { 1, 12, 22 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 57, 192, 227 }, -+ { 20, 143, 204 }, -+ { 3, 96, 154 }, -+ { 1, 68, 112 }, -+ { 1, 42, 69 }, -+ { 1, 19, 32 }, -+ }, -+ }, -+ }, -+ { /* block Type 1 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 212, 35, 215 }, -+ { 113, 47, 169 }, -+ { 29, 48, 105 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 74, 129, 203 }, -+ { 106, 120, 203 }, -+ { 49, 107, 178 }, -+ { 19, 84, 144 }, -+ { 4, 50, 84 }, -+ { 1, 15, 25 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 71, 172, 217 }, -+ { 44, 141, 209 }, -+ { 15, 102, 173 }, -+ { 6, 76, 133 }, -+ { 2, 51, 89 }, -+ { 1, 24, 42 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 64, 185, 231 }, -+ { 31, 148, 216 }, -+ { 8, 103, 175 }, -+ { 3, 74, 131 }, -+ { 1, 46, 81 }, -+ { 1, 18, 30 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 65, 196, 235 }, -+ { 25, 157, 221 }, -+ { 5, 105, 174 }, -+ { 1, 67, 120 }, -+ { 1, 38, 69 }, -+ { 1, 15, 30 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 65, 204, 238 }, -+ { 30, 156, 224 }, -+ { 7, 107, 177 }, -+ { 2, 70, 124 }, -+ { 1, 42, 73 }, -+ { 1, 18, 34 }, -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 225, 86, 251 }, -+ { 144, 104, 235 }, -+ { 42, 99, 181 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 85, 175, 239 }, -+ { 112, 165, 229 }, -+ { 29, 136, 200 }, -+ { 12, 103, 162 }, -+ { 6, 77, 123 }, -+ { 2, 53, 84 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 75, 183, 239 }, -+ { 30, 155, 221 }, -+ { 3, 106, 171 }, -+ { 1, 74, 128 }, -+ { 1, 44, 76 }, -+ { 1, 17, 28 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 73, 185, 240 }, -+ { 27, 159, 222 }, -+ { 2, 107, 172 }, -+ { 1, 75, 127 }, -+ { 1, 42, 73 }, -+ { 1, 17, 29 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 62, 190, 238 }, -+ { 21, 159, 222 }, -+ { 2, 107, 172 }, -+ { 1, 72, 122 }, -+ { 1, 40, 71 }, -+ { 1, 18, 32 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 61, 199, 240 }, -+ { 27, 161, 226 }, -+ { 4, 113, 180 }, -+ { 1, 76, 129 }, -+ { 1, 46, 80 }, -+ { 1, 23, 41 }, -+ }, -+ }, -+ }, -+ }, -+ { /* tx = 16x16 */ -+ { /* block Type 0 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 7, 27, 153 }, -+ { 5, 30, 95 }, -+ { 1, 16, 30 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 50, 75, 127 }, -+ { 57, 75, 124 }, -+ { 27, 67, 108 }, -+ { 10, 54, 86 }, -+ { 1, 33, 52 }, -+ { 1, 12, 18 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 43, 125, 151 }, -+ { 26, 108, 148 }, -+ { 7, 83, 122 }, -+ { 2, 59, 89 }, -+ { 1, 38, 60 }, -+ { 1, 17, 27 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 23, 144, 163 }, -+ { 13, 112, 154 }, -+ { 2, 75, 117 }, -+ { 1, 50, 81 }, -+ { 1, 31, 51 }, -+ { 1, 14, 23 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 18, 162, 185 }, -+ { 6, 123, 171 }, -+ { 1, 78, 125 }, -+ { 1, 51, 86 }, -+ { 1, 31, 54 }, -+ { 1, 14, 23 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 15, 199, 227 }, -+ { 3, 150, 204 }, -+ { 1, 91, 146 }, -+ { 1, 55, 95 }, -+ { 1, 30, 53 }, -+ { 1, 11, 20 }, -+ } -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 19, 55, 240 }, -+ { 19, 59, 196 }, -+ { 3, 52, 105 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 41, 166, 207 }, -+ { 104, 153, 199 }, -+ { 31, 123, 181 }, -+ { 14, 101, 152 }, -+ { 5, 72, 106 }, -+ { 1, 36, 52 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 35, 176, 211 }, -+ { 12, 131, 190 }, -+ { 2, 88, 144 }, -+ { 1, 60, 101 }, -+ { 1, 36, 60 }, -+ { 1, 16, 28 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 28, 183, 213 }, -+ { 8, 134, 191 }, -+ { 1, 86, 142 }, -+ { 1, 56, 96 }, -+ { 1, 30, 53 }, -+ { 1, 12, 20 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 20, 190, 215 }, -+ { 4, 135, 192 }, -+ { 1, 84, 139 }, -+ { 1, 53, 91 }, -+ { 1, 28, 49 }, -+ { 1, 11, 20 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 13, 196, 216 }, -+ { 2, 137, 192 }, -+ { 1, 86, 143 }, -+ { 1, 57, 99 }, -+ { 1, 32, 56 }, -+ { 1, 13, 24 }, -+ }, -+ }, -+ }, -+ { /* block Type 1 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 211, 29, 217 }, -+ { 96, 47, 156 }, -+ { 22, 43, 87 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 78, 120, 193 }, -+ { 111, 116, 186 }, -+ { 46, 102, 164 }, -+ { 15, 80, 128 }, -+ { 2, 49, 76 }, -+ { 1, 18, 28 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 71, 161, 203 }, -+ { 42, 132, 192 }, -+ { 10, 98, 150 }, -+ { 3, 69, 109 }, -+ { 1, 44, 70 }, -+ { 1, 18, 29 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 57, 186, 211 }, -+ { 30, 140, 196 }, -+ { 4, 93, 146 }, -+ { 1, 62, 102 }, -+ { 1, 38, 65 }, -+ { 1, 16, 27 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 47, 199, 217 }, -+ { 14, 145, 196 }, -+ { 1, 88, 142 }, -+ { 1, 57, 98 }, -+ { 1, 36, 62 }, -+ { 1, 15, 26 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 26, 219, 229 }, -+ { 5, 155, 207 }, -+ { 1, 94, 151 }, -+ { 1, 60, 104 }, -+ { 1, 36, 62 }, -+ { 1, 16, 28 }, -+ } -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 233, 29, 248 }, -+ { 146, 47, 220 }, -+ { 43, 52, 140 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 100, 163, 232 }, -+ { 179, 161, 222 }, -+ { 63, 142, 204 }, -+ { 37, 113, 174 }, -+ { 26, 89, 137 }, -+ { 18, 68, 97 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 85, 181, 230 }, -+ { 32, 146, 209 }, -+ { 7, 100, 164 }, -+ { 3, 71, 121 }, -+ { 1, 45, 77 }, -+ { 1, 18, 30 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 65, 187, 230 }, -+ { 20, 148, 207 }, -+ { 2, 97, 159 }, -+ { 1, 68, 116 }, -+ { 1, 40, 70 }, -+ { 1, 14, 29 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 40, 194, 227 }, -+ { 8, 147, 204 }, -+ { 1, 94, 155 }, -+ { 1, 65, 112 }, -+ { 1, 39, 66 }, -+ { 1, 14, 26 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 16, 208, 228 }, -+ { 3, 151, 207 }, -+ { 1, 98, 160 }, -+ { 1, 67, 117 }, -+ { 1, 41, 74 }, -+ { 1, 17, 31 }, -+ }, -+ }, -+ }, -+ }, -+ { /* tx = 32x32 */ -+ { /* block Type 0 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 17, 38, 140 }, -+ { 7, 34, 80 }, -+ { 1, 17, 29 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 37, 75, 128 }, -+ { 41, 76, 128 }, -+ { 26, 66, 116 }, -+ { 12, 52, 94 }, -+ { 2, 32, 55 }, -+ { 1, 10, 16 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 50, 127, 154 }, -+ { 37, 109, 152 }, -+ { 16, 82, 121 }, -+ { 5, 59, 85 }, -+ { 1, 35, 54 }, -+ { 1, 13, 20 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 40, 142, 167 }, -+ { 17, 110, 157 }, -+ { 2, 71, 112 }, -+ { 1, 44, 72 }, -+ { 1, 27, 45 }, -+ { 1, 11, 17 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 30, 175, 188 }, -+ { 9, 124, 169 }, -+ { 1, 74, 116 }, -+ { 1, 48, 78 }, -+ { 1, 30, 49 }, -+ { 1, 11, 18 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 10, 222, 223 }, -+ { 2, 150, 194 }, -+ { 1, 83, 128 }, -+ { 1, 48, 79 }, -+ { 1, 27, 45 }, -+ { 1, 11, 17 }, -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 36, 41, 235 }, -+ { 29, 36, 193 }, -+ { 10, 27, 111 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 85, 165, 222 }, -+ { 177, 162, 215 }, -+ { 110, 135, 195 }, -+ { 57, 113, 168 }, -+ { 23, 83, 120 }, -+ { 10, 49, 61 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 85, 190, 223 }, -+ { 36, 139, 200 }, -+ { 5, 90, 146 }, -+ { 1, 60, 103 }, -+ { 1, 38, 65 }, -+ { 1, 18, 30 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 72, 202, 223 }, -+ { 23, 141, 199 }, -+ { 2, 86, 140 }, -+ { 1, 56, 97 }, -+ { 1, 36, 61 }, -+ { 1, 16, 27 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 55, 218, 225 }, -+ { 13, 145, 200 }, -+ { 1, 86, 141 }, -+ { 1, 57, 99 }, -+ { 1, 35, 61 }, -+ { 1, 13, 22 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 15, 235, 212 }, -+ { 1, 132, 184 }, -+ { 1, 84, 139 }, -+ { 1, 57, 97 }, -+ { 1, 34, 56 }, -+ { 1, 14, 23 }, -+ }, -+ }, -+ }, -+ { /* block Type 1 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 181, 21, 201 }, -+ { 61, 37, 123 }, -+ { 10, 38, 71 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 47, 106, 172 }, -+ { 95, 104, 173 }, -+ { 42, 93, 159 }, -+ { 18, 77, 131 }, -+ { 4, 50, 81 }, -+ { 1, 17, 23 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 62, 147, 199 }, -+ { 44, 130, 189 }, -+ { 28, 102, 154 }, -+ { 18, 75, 115 }, -+ { 2, 44, 65 }, -+ { 1, 12, 19 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 55, 153, 210 }, -+ { 24, 130, 194 }, -+ { 3, 93, 146 }, -+ { 1, 61, 97 }, -+ { 1, 31, 50 }, -+ { 1, 10, 16 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 49, 186, 223 }, -+ { 17, 148, 204 }, -+ { 1, 96, 142 }, -+ { 1, 53, 83 }, -+ { 1, 26, 44 }, -+ { 1, 11, 17 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 13, 217, 212 }, -+ { 2, 136, 180 }, -+ { 1, 78, 124 }, -+ { 1, 50, 83 }, -+ { 1, 29, 49 }, -+ { 1, 14, 23 }, -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 197, 13, 247 }, -+ { 82, 17, 222 }, -+ { 25, 17, 162 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 126, 186, 247 }, -+ { 234, 191, 243 }, -+ { 176, 177, 234 }, -+ { 104, 158, 220 }, -+ { 66, 128, 186 }, -+ { 55, 90, 137 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 111, 197, 242 }, -+ { 46, 158, 219 }, -+ { 9, 104, 171 }, -+ { 2, 65, 125 }, -+ { 1, 44, 80 }, -+ { 1, 17, 91 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 104, 208, 245 }, -+ { 39, 168, 224 }, -+ { 3, 109, 162 }, -+ { 1, 79, 124 }, -+ { 1, 50, 102 }, -+ { 1, 43, 102 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 84, 220, 246 }, -+ { 31, 177, 231 }, -+ { 2, 115, 180 }, -+ { 1, 79, 134 }, -+ { 1, 55, 77 }, -+ { 1, 60, 79 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 43, 243, 240 }, -+ { 8, 180, 217 }, -+ { 1, 115, 166 }, -+ { 1, 84, 121 }, -+ { 1, 51, 67 }, -+ { 1, 16, 6 }, -+ }, -+ }, -+ }, -+ }, -+ }, -+ -+ .skip = { 192, 128, 64 }, -+ .inter_mode = { -+ { 2, 173, 34 }, -+ { 7, 145, 85 }, -+ { 7, 166, 63 }, -+ { 7, 94, 66 }, -+ { 8, 64, 46 }, -+ { 17, 81, 31 }, -+ { 25, 29, 30 }, -+ }, -+ .interp_filter = { -+ { 235, 162 }, -+ { 36, 255 }, -+ { 34, 3 }, -+ { 149, 144 }, -+ }, -+ .is_inter = { 9, 102, 187, 225 }, -+ .comp_mode = { 239, 183, 119, 96, 41 }, -+ .single_ref = { -+ { 33, 16 }, -+ { 77, 74 }, -+ { 142, 142 }, -+ { 172, 170 }, -+ { 238, 247 }, -+ }, -+ .comp_ref = { 50, 126, 123, 221, 226 }, -+ .y_mode = { -+ { 65, 32, 18, 144, 162, 194, 41, 51, 98 }, -+ { 132, 68, 18, 165, 217, 196, 45, 40, 78 }, -+ { 173, 80, 19, 176, 240, 193, 64, 35, 46 }, -+ { 221, 135, 38, 194, 248, 121, 96, 85, 29 }, -+ }, -+ .uv_mode = { -+ { 120, 7, 76, 176, 208, 126, 28, 54, 103 } /* y = dc */, -+ { 48, 12, 154, 155, 139, 90, 34, 117, 119 } /* y = v */, -+ { 67, 6, 25, 204, 243, 158, 13, 21, 96 } /* y = h */, -+ { 97, 5, 44, 131, 176, 139, 48, 68, 97 } /* y = d45 */, -+ { 83, 5, 42, 156, 111, 152, 26, 49, 152 } /* y = d135 */, -+ { 80, 5, 58, 178, 74, 83, 33, 62, 145 } /* y = d117 */, -+ { 86, 5, 32, 154, 192, 168, 14, 22, 163 } /* y = d153 */, -+ { 85, 5, 32, 156, 216, 148, 19, 29, 73 } /* y = d207 */, -+ { 77, 7, 64, 116, 132, 122, 37, 126, 120 } /* y = d63 */, -+ { 101, 21, 107, 181, 192, 103, 19, 67, 125 } /* y = tm */ -+ }, -+ .partition = { -+ /* 8x8 -> 4x4 */ -+ { 199, 122, 141 } /* a/l both not split */, -+ { 147, 63, 159 } /* a split, l not split */, -+ { 148, 133, 118 } /* l split, a not split */, -+ { 121, 104, 114 } /* a/l both split */, -+ /* 16x16 -> 8x8 */ -+ { 174, 73, 87 } /* a/l both not split */, -+ { 92, 41, 83 } /* a split, l not split */, -+ { 82, 99, 50 } /* l split, a not split */, -+ { 53, 39, 39 } /* a/l both split */, -+ /* 32x32 -> 16x16 */ -+ { 177, 58, 59 } /* a/l both not split */, -+ { 68, 26, 63 } /* a split, l not split */, -+ { 52, 79, 25 } /* l split, a not split */, -+ { 17, 14, 12 } /* a/l both split */, -+ /* 64x64 -> 32x32 */ -+ { 222, 34, 30 } /* a/l both not split */, -+ { 72, 16, 44 } /* a split, l not split */, -+ { 58, 32, 12 } /* l split, a not split */, -+ { 10, 7, 6 } /* a/l both split */, -+ }, -+ -+ .mv = { -+ .joint = { 32, 64, 96 }, -+ .sign = { 128, 128 }, -+ .classes = { -+ { 224, 144, 192, 168, 192, 176, 192, 198, 198, 245 }, -+ { 216, 128, 176, 160, 176, 176, 192, 198, 198, 208 }, -+ }, -+ .class0_bit = { 216, 208 }, -+ .bits = { -+ { 136, 140, 148, 160, 176, 192, 224, 234, 234, 240}, -+ { 136, 140, 148, 160, 176, 192, 224, 234, 234, 240}, -+ }, -+ .class0_fr = { -+ { -+ { 128, 128, 64 }, -+ { 96, 112, 64 }, -+ }, -+ { -+ { 128, 128, 64 }, -+ { 96, 112, 64 }, -+ }, -+ }, -+ .fr = { -+ { 64, 96, 64 }, -+ { 64, 96, 64 }, -+ }, -+ .class0_hp = { 160, 160 }, -+ .hp = { 128, 128 }, -+ }, -+}; -+EXPORT_SYMBOL_GPL(v4l2_vp9_default_probs); -+ -+static u32 fastdiv(u32 dividend, u16 divisor) -+{ -+#define DIV_INV(d) ((u32)(((1ULL << 32) + ((d) - 1)) / (d))) -+#define DIVS_INV(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9) \ -+ DIV_INV(d0), DIV_INV(d1), DIV_INV(d2), DIV_INV(d3), \ -+ DIV_INV(d4), DIV_INV(d5), DIV_INV(d6), DIV_INV(d7), \ -+ DIV_INV(d8), DIV_INV(d9) -+ -+ static const u32 inv[] = { -+ DIV_INV(2), DIV_INV(3), DIV_INV(4), DIV_INV(5), -+ DIV_INV(6), DIV_INV(7), DIV_INV(8), DIV_INV(9), -+ DIVS_INV(10, 11, 12, 13, 14, 15, 16, 17, 18, 19), -+ DIVS_INV(20, 21, 22, 23, 24, 25, 26, 27, 28, 29), -+ DIVS_INV(30, 31, 32, 33, 34, 35, 36, 37, 38, 39), -+ DIVS_INV(40, 41, 42, 43, 44, 45, 46, 47, 48, 49), -+ DIVS_INV(50, 51, 52, 53, 54, 55, 56, 57, 58, 59), -+ DIVS_INV(60, 61, 62, 63, 64, 65, 66, 67, 68, 69), -+ DIVS_INV(70, 71, 72, 73, 74, 75, 76, 77, 78, 79), -+ DIVS_INV(80, 81, 82, 83, 84, 85, 86, 87, 88, 89), -+ DIVS_INV(90, 91, 92, 93, 94, 95, 96, 97, 98, 99), -+ DIVS_INV(100, 101, 102, 103, 104, 105, 106, 107, 108, 109), -+ DIVS_INV(110, 111, 112, 113, 114, 115, 116, 117, 118, 119), -+ DIVS_INV(120, 121, 122, 123, 124, 125, 126, 127, 128, 129), -+ DIVS_INV(130, 131, 132, 133, 134, 135, 136, 137, 138, 139), -+ DIVS_INV(140, 141, 142, 143, 144, 145, 146, 147, 148, 149), -+ DIVS_INV(150, 151, 152, 153, 154, 155, 156, 157, 158, 159), -+ DIVS_INV(160, 161, 162, 163, 164, 165, 166, 167, 168, 169), -+ DIVS_INV(170, 171, 172, 173, 174, 175, 176, 177, 178, 179), -+ DIVS_INV(180, 181, 182, 183, 184, 185, 186, 187, 188, 189), -+ DIVS_INV(190, 191, 192, 193, 194, 195, 196, 197, 198, 199), -+ DIVS_INV(200, 201, 202, 203, 204, 205, 206, 207, 208, 209), -+ DIVS_INV(210, 211, 212, 213, 214, 215, 216, 217, 218, 219), -+ DIVS_INV(220, 221, 222, 223, 224, 225, 226, 227, 228, 229), -+ DIVS_INV(230, 231, 232, 233, 234, 235, 236, 237, 238, 239), -+ DIVS_INV(240, 241, 242, 243, 244, 245, 246, 247, 248, 249), -+ DIV_INV(250), DIV_INV(251), DIV_INV(252), DIV_INV(253), -+ DIV_INV(254), DIV_INV(255), DIV_INV(256), -+ }; -+ -+ if (divisor == 0) -+ return 0; -+ else if (divisor == 1) -+ return dividend; -+ -+ if (WARN_ON(divisor - 2 >= ARRAY_SIZE(inv))) -+ return dividend; -+ -+ return ((u64)dividend * inv[divisor - 2]) >> 32; -+} -+ -+/* 6.3.6 inv_recenter_nonneg(v, m) */ -+static int inv_recenter_nonneg(int v, int m) -+{ -+ if (v > 2 * m) -+ return v; -+ -+ if (v & 1) -+ return m - ((v + 1) >> 1); -+ -+ return m + (v >> 1); -+} -+ -+/* -+ * part of 6.3.5 inv_remap_prob(deltaProb, prob) -+ * delta = inv_map_table[deltaProb] done by userspace -+ */ -+static int update_prob(int delta, int prob) -+{ -+ if (!delta) -+ return prob; -+ -+ return prob <= 128 ? -+ 1 + inv_recenter_nonneg(delta, prob - 1) : -+ 255 - inv_recenter_nonneg(delta, 255 - prob); -+} -+ -+/* Counterpart to 6.3.2 tx_mode_probs() */ -+static void update_tx_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->tx8); i++) { -+ u8 *p8x8 = probs->tx8[i]; -+ u8 *p16x16 = probs->tx16[i]; -+ u8 *p32x32 = probs->tx32[i]; -+ const u8 *d8x8 = deltas->tx8[i]; -+ const u8 *d16x16 = deltas->tx16[i]; -+ const u8 *d32x32 = deltas->tx32[i]; -+ -+ p8x8[0] = update_prob(d8x8[0], p8x8[0]); -+ p16x16[0] = update_prob(d16x16[0], p16x16[0]); -+ p16x16[1] = update_prob(d16x16[1], p16x16[1]); -+ p32x32[0] = update_prob(d32x32[0], p32x32[0]); -+ p32x32[1] = update_prob(d32x32[1], p32x32[1]); -+ p32x32[2] = update_prob(d32x32[2], p32x32[2]); -+ } -+} -+ -+#define BAND_6(band) ((band) == 0 ? 3 : 6) -+ -+static void update_coeff(const u8 deltas[6][6][3], u8 probs[6][6][3]) -+{ -+ int l, m, n; -+ -+ for (l = 0; l < 6; l++) -+ for (m = 0; m < BAND_6(l); m++) { -+ u8 *p = probs[l][m]; -+ const u8 *d = deltas[l][m]; -+ -+ for (n = 0; n < 3; n++) -+ p[n] = update_prob(d[n], p[n]); -+ } -+} -+ -+/* Counterpart to 6.3.7 read_coef_probs() */ -+static void update_coef_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ int i, j, k; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->coef); i++) { -+ for (j = 0; j < ARRAY_SIZE(probs->coef[0]); j++) -+ for (k = 0; k < ARRAY_SIZE(probs->coef[0][0]); k++) -+ update_coeff(deltas->coef[i][j][k], probs->coef[i][j][k]); -+ -+ if (deltas->tx_mode == i) -+ break; -+ } -+} -+ -+/* Counterpart to 6.3.8 read_skip_prob() */ -+static void update_skip_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->skip); i++) -+ probs->skip[i] = update_prob(deltas->skip[i], probs->skip[i]); -+} -+ -+/* Counterpart to 6.3.9 read_inter_mode_probs() */ -+static void update_inter_mode_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->inter_mode); i++) { -+ u8 *p = probs->inter_mode[i]; -+ const u8 *d = deltas->inter_mode[i]; -+ -+ p[0] = update_prob(d[0], p[0]); -+ p[1] = update_prob(d[1], p[1]); -+ p[2] = update_prob(d[2], p[2]); -+ } -+} -+ -+/* Counterpart to 6.3.10 read_interp_filter_probs() */ -+static void update_interp_filter_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->interp_filter); i++) { -+ u8 *p = probs->interp_filter[i]; -+ const u8 *d = deltas->interp_filter[i]; -+ -+ p[0] = update_prob(d[0], p[0]); -+ p[1] = update_prob(d[1], p[1]); -+ } -+} -+ -+/* Counterpart to 6.3.11 read_is_inter_probs() */ -+static void update_is_inter_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->is_inter); i++) -+ probs->is_inter[i] = update_prob(deltas->is_inter[i], probs->is_inter[i]); -+} -+ -+/* 6.3.12 frame_reference_mode() done entirely in userspace */ -+ -+/* Counterpart to 6.3.13 frame_reference_mode_probs() */ -+static void -+update_frame_reference_mode_probs(unsigned int reference_mode, -+ struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ if (reference_mode == V4L2_VP9_REFERENCE_MODE_SELECT) -+ for (i = 0; i < ARRAY_SIZE(probs->comp_mode); i++) -+ probs->comp_mode[i] = update_prob(deltas->comp_mode[i], -+ probs->comp_mode[i]); -+ -+ if (reference_mode != V4L2_VP9_REFERENCE_MODE_COMPOUND_REFERENCE) -+ for (i = 0; i < ARRAY_SIZE(probs->single_ref); i++) { -+ u8 *p = probs->single_ref[i]; -+ const u8 *d = deltas->single_ref[i]; -+ -+ p[0] = update_prob(d[0], p[0]); -+ p[1] = update_prob(d[1], p[1]); -+ } -+ -+ if (reference_mode != V4L2_VP9_REFERENCE_MODE_SINGLE_REFERENCE) -+ for (i = 0; i < ARRAY_SIZE(probs->comp_ref); i++) -+ probs->comp_ref[i] = update_prob(deltas->comp_ref[i], probs->comp_ref[i]); -+} -+ -+/* Counterpart to 6.3.14 read_y_mode_probs() */ -+static void update_y_mode_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i, j; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->y_mode); i++) -+ for (j = 0; j < ARRAY_SIZE(probs->y_mode[0]); ++j) -+ probs->y_mode[i][j] = -+ update_prob(deltas->y_mode[i][j], probs->y_mode[i][j]); -+} -+ -+/* Counterpart to 6.3.15 read_partition_probs() */ -+static void update_partition_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i, j; -+ -+ for (i = 0; i < 4; i++) -+ for (j = 0; j < 4; j++) { -+ u8 *p = probs->partition[i * 4 + j]; -+ const u8 *d = deltas->partition[i * 4 + j]; -+ -+ p[0] = update_prob(d[0], p[0]); -+ p[1] = update_prob(d[1], p[1]); -+ p[2] = update_prob(d[2], p[2]); -+ } -+} -+ -+static inline int update_mv_prob(int delta, int prob) -+{ -+ if (!delta) -+ return prob; -+ -+ return delta; -+} -+ -+/* Counterpart to 6.3.16 mv_probs() */ -+static void update_mv_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ u8 *p = probs->mv.joint; -+ const u8 *d = deltas->mv.joint; -+ unsigned int i, j; -+ -+ p[0] = update_mv_prob(d[0], p[0]); -+ p[1] = update_mv_prob(d[1], p[1]); -+ p[2] = update_mv_prob(d[2], p[2]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->mv.sign); i++) { -+ p = probs->mv.sign; -+ d = deltas->mv.sign; -+ p[i] = update_mv_prob(d[i], p[i]); -+ -+ p = probs->mv.classes[i]; -+ d = deltas->mv.classes[i]; -+ for (j = 0; j < ARRAY_SIZE(probs->mv.classes[0]); j++) -+ p[j] = update_mv_prob(d[j], p[j]); -+ -+ p = probs->mv.class0_bit; -+ d = deltas->mv.class0_bit; -+ p[i] = update_mv_prob(d[i], p[i]); -+ -+ p = probs->mv.bits[i]; -+ d = deltas->mv.bits[i]; -+ for (j = 0; j < ARRAY_SIZE(probs->mv.bits[0]); j++) -+ p[j] = update_mv_prob(d[j], p[j]); -+ -+ for (j = 0; j < ARRAY_SIZE(probs->mv.class0_fr[0]); j++) { -+ p = probs->mv.class0_fr[i][j]; -+ d = deltas->mv.class0_fr[i][j]; -+ -+ p[0] = update_mv_prob(d[0], p[0]); -+ p[1] = update_mv_prob(d[1], p[1]); -+ p[2] = update_mv_prob(d[2], p[2]); -+ } -+ -+ p = probs->mv.fr[i]; -+ d = deltas->mv.fr[i]; -+ for (j = 0; j < ARRAY_SIZE(probs->mv.fr[i]); j++) -+ p[j] = update_mv_prob(d[j], p[j]); -+ -+ if (dec_params->flags & V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV) { -+ p = probs->mv.class0_hp; -+ d = deltas->mv.class0_hp; -+ p[i] = update_mv_prob(d[i], p[i]); -+ -+ p = probs->mv.hp; -+ d = deltas->mv.hp; -+ p[i] = update_mv_prob(d[i], p[i]); -+ } -+ } -+} -+ -+/* Counterpart to 6.3 compressed_header(), but parsing has been done in userspace. */ -+void v4l2_vp9_fw_update_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ if (deltas->tx_mode == V4L2_VP9_TX_MODE_SELECT) -+ update_tx_probs(probs, deltas); -+ -+ update_coef_probs(probs, deltas, dec_params); -+ -+ update_skip_probs(probs, deltas); -+ -+ if (dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME || -+ dec_params->flags & V4L2_VP9_FRAME_FLAG_INTRA_ONLY) -+ return; -+ -+ update_inter_mode_probs(probs, deltas); -+ -+ if (dec_params->interpolation_filter == V4L2_VP9_INTERP_FILTER_SWITCHABLE) -+ update_interp_filter_probs(probs, deltas); -+ -+ update_is_inter_probs(probs, deltas); -+ -+ update_frame_reference_mode_probs(dec_params->reference_mode, probs, deltas); -+ -+ update_y_mode_probs(probs, deltas); -+ -+ update_partition_probs(probs, deltas); -+ -+ update_mv_probs(probs, deltas, dec_params); -+} -+EXPORT_SYMBOL_GPL(v4l2_vp9_fw_update_probs); -+ -+u8 v4l2_vp9_reset_frame_ctx(const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct v4l2_vp9_frame_context *frame_context) -+{ -+ int i; -+ -+ u8 fctx_idx = dec_params->frame_context_idx; -+ -+ if (dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME || -+ dec_params->flags & V4L2_VP9_FRAME_FLAG_INTRA_ONLY || -+ dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) { -+ /* -+ * setup_past_independence() -+ * We do nothing here. Instead of storing default probs in some intermediate -+ * location and then copying from that location to appropriate contexts -+ * in save_probs() below, we skip that step and save default probs directly -+ * to appropriate contexts. -+ */ -+ if (dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME || -+ dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT || -+ dec_params->reset_frame_context == V4L2_VP9_RESET_FRAME_CTX_ALL) -+ for (i = 0; i < 4; ++i) -+ /* save_probs(i) */ -+ memcpy(&frame_context[i], &v4l2_vp9_default_probs, -+ sizeof(v4l2_vp9_default_probs)); -+ else if (dec_params->reset_frame_context == V4L2_VP9_RESET_FRAME_CTX_SPEC) -+ /* save_probs(fctx_idx) */ -+ memcpy(&frame_context[fctx_idx], &v4l2_vp9_default_probs, -+ sizeof(v4l2_vp9_default_probs)); -+ fctx_idx = 0; -+ } -+ -+ return fctx_idx; -+} -+EXPORT_SYMBOL_GPL(v4l2_vp9_reset_frame_ctx); -+ -+/* 8.4.1 Merge prob process */ -+static u8 merge_prob(u8 pre_prob, u32 ct0, u32 ct1, u16 count_sat, u32 max_update_factor) -+{ -+ u32 den, prob, count, factor; -+ -+ den = ct0 + ct1; -+ if (!den) { -+ /* -+ * prob = 128, count = 0, update_factor = 0 -+ * Round2's argument: pre_prob * 256 -+ * (pre_prob * 256 + 128) >> 8 == pre_prob -+ */ -+ return pre_prob; -+ } -+ -+ prob = clamp(((ct0 << 8) + (den >> 1)) / den, (u32)1, (u32)255); -+ count = min_t(u32, den, count_sat); -+ factor = fastdiv(max_update_factor * count, count_sat); -+ -+ /* -+ * Round2(pre_prob * (256 - factor) + prob * factor, 8) -+ * Round2(pre_prob * 256 + (prob - pre_prob) * factor, 8) -+ * (pre_prob * 256 >> 8) + (((prob - pre_prob) * factor + 128) >> 8) -+ */ -+ return pre_prob + (((prob - pre_prob) * factor + 128) >> 8); -+} -+ -+static inline u8 noncoef_merge_prob(u8 pre_prob, u32 ct0, u32 ct1) -+{ -+ return merge_prob(pre_prob, ct0, ct1, 20, 128); -+} -+ -+/* 8.4.2 Merge probs process */ -+/* -+ * merge_probs() is a recursive function in the spec. We avoid recursion in the kernel. -+ * That said, the "tree" parameter of merge_probs() controls how deep the recursion goes. -+ * It turns out that in all cases the recursive calls boil down to a short-ish series -+ * of merge_prob() invocations (note no "s"). -+ * -+ * Variant A -+ * --------- -+ * merge_probs(small_token_tree, 2): -+ * merge_prob(p[1], c[0], c[1] + c[2]) -+ * merge_prob(p[2], c[1], c[2]) -+ * -+ * Variant B -+ * --------- -+ * merge_probs(binary_tree, 0) or -+ * merge_probs(tx_size_8_tree, 0): -+ * merge_prob(p[0], c[0], c[1]) -+ * -+ * Variant C -+ * --------- -+ * merge_probs(inter_mode_tree, 0): -+ * merge_prob(p[0], c[2], c[1] + c[0] + c[3]) -+ * merge_prob(p[1], c[0], c[1] + c[3]) -+ * merge_prob(p[2], c[1], c[3]) -+ * -+ * Variant D -+ * --------- -+ * merge_probs(intra_mode_tree, 0): -+ * merge_prob(p[0], c[0], c[1] + ... + c[9]) -+ * merge_prob(p[1], c[9], c[1] + ... + c[8]) -+ * merge_prob(p[2], c[1], c[2] + ... + c[8]) -+ * merge_prob(p[3], c[2] + c[4] + c[5], c[3] + c[8] + c[6] + c[7]) -+ * merge_prob(p[4], c[2], c[4] + c[5]) -+ * merge_prob(p[5], c[4], c[5]) -+ * merge_prob(p[6], c[3], c[8] + c[6] + c[7]) -+ * merge_prob(p[7], c[8], c[6] + c[7]) -+ * merge_prob(p[8], c[6], c[7]) -+ * -+ * Variant E -+ * --------- -+ * merge_probs(partition_tree, 0) or -+ * merge_probs(tx_size_32_tree, 0) or -+ * merge_probs(mv_joint_tree, 0) or -+ * merge_probs(mv_fr_tree, 0): -+ * merge_prob(p[0], c[0], c[1] + c[2] + c[3]) -+ * merge_prob(p[1], c[1], c[2] + c[3]) -+ * merge_prob(p[2], c[2], c[3]) -+ * -+ * Variant F -+ * --------- -+ * merge_probs(interp_filter_tree, 0) or -+ * merge_probs(tx_size_16_tree, 0): -+ * merge_prob(p[0], c[0], c[1] + c[2]) -+ * merge_prob(p[1], c[1], c[2]) -+ * -+ * Variant G -+ * --------- -+ * merge_probs(mv_class_tree, 0): -+ * merge_prob(p[0], c[0], c[1] + ... + c[10]) -+ * merge_prob(p[1], c[1], c[2] + ... + c[10]) -+ * merge_prob(p[2], c[2] + c[3], c[4] + ... + c[10]) -+ * merge_prob(p[3], c[2], c[3]) -+ * merge_prob(p[4], c[4] + c[5], c[6] + ... + c[10]) -+ * merge_prob(p[5], c[4], c[5]) -+ * merge_prob(p[6], c[6], c[7] + ... + c[10]) -+ * merge_prob(p[7], c[7] + c[8], c[9] + c[10]) -+ * merge_prob(p[8], c[7], c[8]) -+ * merge_prob(p[9], c[9], [10]) -+ */ -+ -+static inline void merge_probs_variant_a(u8 *p, const u32 *c, u16 count_sat, u32 update_factor) -+{ -+ p[1] = merge_prob(p[1], c[0], c[1] + c[2], count_sat, update_factor); -+ p[2] = merge_prob(p[2], c[1], c[2], count_sat, update_factor); -+} -+ -+static inline void merge_probs_variant_b(u8 *p, const u32 *c, u16 count_sat, u32 update_factor) -+{ -+ p[0] = merge_prob(p[0], c[0], c[1], count_sat, update_factor); -+} -+ -+static inline void merge_probs_variant_c(u8 *p, const u32 *c) -+{ -+ p[0] = noncoef_merge_prob(p[0], c[2], c[1] + c[0] + c[3]); -+ p[1] = noncoef_merge_prob(p[1], c[0], c[1] + c[3]); -+ p[2] = noncoef_merge_prob(p[2], c[1], c[3]); -+} -+ -+static void merge_probs_variant_d(u8 *p, const u32 *c) -+{ -+ u32 sum = 0, s2; -+ -+ sum = c[1] + c[2] + c[3] + c[4] + c[5] + c[6] + c[7] + c[8] + c[9]; -+ -+ p[0] = noncoef_merge_prob(p[0], c[0], sum); -+ sum -= c[9]; -+ p[1] = noncoef_merge_prob(p[1], c[9], sum); -+ sum -= c[1]; -+ p[2] = noncoef_merge_prob(p[2], c[1], sum); -+ s2 = c[2] + c[4] + c[5]; -+ sum -= s2; -+ p[3] = noncoef_merge_prob(p[3], s2, sum); -+ s2 -= c[2]; -+ p[4] = noncoef_merge_prob(p[4], c[2], s2); -+ p[5] = noncoef_merge_prob(p[5], c[4], c[5]); -+ sum -= c[3]; -+ p[6] = noncoef_merge_prob(p[6], c[3], sum); -+ sum -= c[8]; -+ p[7] = noncoef_merge_prob(p[7], c[8], sum); -+ p[8] = noncoef_merge_prob(p[8], c[6], c[7]); -+} -+ -+static inline void merge_probs_variant_e(u8 *p, const u32 *c) -+{ -+ p[0] = noncoef_merge_prob(p[0], c[0], c[1] + c[2] + c[3]); -+ p[1] = noncoef_merge_prob(p[1], c[1], c[2] + c[3]); -+ p[2] = noncoef_merge_prob(p[2], c[2], c[3]); -+} -+ -+static inline void merge_probs_variant_f(u8 *p, const u32 *c) -+{ -+ p[0] = noncoef_merge_prob(p[0], c[0], c[1] + c[2]); -+ p[1] = noncoef_merge_prob(p[1], c[1], c[2]); -+} -+ -+static void merge_probs_variant_g(u8 *p, const u32 *c) -+{ -+ u32 sum; -+ -+ sum = c[1] + c[2] + c[3] + c[4] + c[5] + c[6] + c[7] + c[8] + c[9] + c[10]; -+ p[0] = noncoef_merge_prob(p[0], c[0], sum); -+ sum -= c[1]; -+ p[1] = noncoef_merge_prob(p[1], c[1], sum); -+ sum -= c[2] + c[3]; -+ p[2] = noncoef_merge_prob(p[2], c[2] + c[3], sum); -+ p[3] = noncoef_merge_prob(p[3], c[2], c[3]); -+ sum -= c[4] + c[5]; -+ p[4] = noncoef_merge_prob(p[4], c[4] + c[5], sum); -+ p[5] = noncoef_merge_prob(p[5], c[4], c[5]); -+ sum -= c[6]; -+ p[6] = noncoef_merge_prob(p[6], c[6], sum); -+ p[7] = noncoef_merge_prob(p[7], c[7] + c[8], c[9] + c[10]); -+ p[8] = noncoef_merge_prob(p[8], c[7], c[8]); -+ p[9] = noncoef_merge_prob(p[9], c[9], c[10]); -+} -+ -+/* 8.4.3 Coefficient probability adaptation process */ -+static inline void adapt_probs_variant_a_coef(u8 *p, const u32 *c, u32 update_factor) -+{ -+ merge_probs_variant_a(p, c, 24, update_factor); -+} -+ -+static inline void adapt_probs_variant_b_coef(u8 *p, const u32 *c, u32 update_factor) -+{ -+ merge_probs_variant_b(p, c, 24, update_factor); -+} -+ -+static void _adapt_coeff(unsigned int i, unsigned int j, unsigned int k, -+ struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_vp9_frame_symbol_counts *counts, -+ u32 uf) -+{ -+ s32 l, m; -+ -+ for (l = 0; l < ARRAY_SIZE(probs->coef[0][0][0]); l++) { -+ for (m = 0; m < BAND_6(l); m++) { -+ u8 *p = probs->coef[i][j][k][l][m]; -+ const u32 counts_more_coefs[2] = { -+ *counts->eob[i][j][k][l][m][1], -+ *counts->eob[i][j][k][l][m][0] - *counts->eob[i][j][k][l][m][1], -+ }; -+ -+ adapt_probs_variant_a_coef(p, *counts->coeff[i][j][k][l][m], uf); -+ adapt_probs_variant_b_coef(p, counts_more_coefs, uf); -+ } -+ } -+} -+ -+static void _adapt_coef_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_vp9_frame_symbol_counts *counts, -+ unsigned int uf) -+{ -+ unsigned int i, j, k; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->coef); i++) -+ for (j = 0; j < ARRAY_SIZE(probs->coef[0]); j++) -+ for (k = 0; k < ARRAY_SIZE(probs->coef[0][0]); k++) -+ _adapt_coeff(i, j, k, probs, counts, uf); -+} -+ -+void v4l2_vp9_adapt_coef_probs(struct v4l2_vp9_frame_context *probs, -+ struct v4l2_vp9_frame_symbol_counts *counts, -+ bool use_128, -+ bool frame_is_intra) -+{ -+ if (frame_is_intra) { -+ _adapt_coef_probs(probs, counts, 112); -+ } else { -+ if (use_128) -+ _adapt_coef_probs(probs, counts, 128); -+ else -+ _adapt_coef_probs(probs, counts, 112); -+ } -+} -+EXPORT_SYMBOL_GPL(v4l2_vp9_adapt_coef_probs); -+ -+/* 8.4.4 Non coefficient probability adaptation process, adapt_probs() */ -+static inline void adapt_probs_variant_b(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_b(p, c, 20, 128); -+} -+ -+static inline void adapt_probs_variant_c(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_c(p, c); -+} -+ -+static inline void adapt_probs_variant_d(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_d(p, c); -+} -+ -+static inline void adapt_probs_variant_e(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_e(p, c); -+} -+ -+static inline void adapt_probs_variant_f(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_f(p, c); -+} -+ -+static inline void adapt_probs_variant_g(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_g(p, c); -+} -+ -+/* 8.4.4 Non coefficient probability adaptation process, adapt_prob() */ -+static inline u8 adapt_prob(u8 prob, const u32 counts[2]) -+{ -+ return noncoef_merge_prob(prob, counts[0], counts[1]); -+} -+ -+/* 8.4.4 Non coefficient probability adaptation process */ -+void v4l2_vp9_adapt_noncoef_probs(struct v4l2_vp9_frame_context *probs, -+ struct v4l2_vp9_frame_symbol_counts *counts, -+ u8 reference_mode, u8 interpolation_filter, u8 tx_mode, -+ u32 flags) -+{ -+ unsigned int i, j; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->is_inter); i++) -+ probs->is_inter[i] = adapt_prob(probs->is_inter[i], (*counts->intra_inter)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->comp_mode); i++) -+ probs->comp_mode[i] = adapt_prob(probs->comp_mode[i], (*counts->comp)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->comp_ref); i++) -+ probs->comp_ref[i] = adapt_prob(probs->comp_ref[i], (*counts->comp_ref)[i]); -+ -+ if (reference_mode != V4L2_VP9_REFERENCE_MODE_COMPOUND_REFERENCE) -+ for (i = 0; i < ARRAY_SIZE(probs->single_ref); i++) -+ for (j = 0; j < ARRAY_SIZE(probs->single_ref[0]); j++) -+ probs->single_ref[i][j] = adapt_prob(probs->single_ref[i][j], -+ (*counts->single_ref)[i][j]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->inter_mode); i++) -+ adapt_probs_variant_c(probs->inter_mode[i], (*counts->mv_mode)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->y_mode); i++) -+ adapt_probs_variant_d(probs->y_mode[i], (*counts->y_mode)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->uv_mode); i++) -+ adapt_probs_variant_d(probs->uv_mode[i], (*counts->uv_mode)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->partition); i++) -+ adapt_probs_variant_e(probs->partition[i], (*counts->partition)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->skip); i++) -+ probs->skip[i] = adapt_prob(probs->skip[i], (*counts->skip)[i]); -+ -+ if (interpolation_filter == V4L2_VP9_INTERP_FILTER_SWITCHABLE) -+ for (i = 0; i < ARRAY_SIZE(probs->interp_filter); i++) -+ adapt_probs_variant_f(probs->interp_filter[i], (*counts->filter)[i]); -+ -+ if (tx_mode == V4L2_VP9_TX_MODE_SELECT) -+ for (i = 0; i < ARRAY_SIZE(probs->tx8); i++) { -+ adapt_probs_variant_b(probs->tx8[i], (*counts->tx8p)[i]); -+ adapt_probs_variant_f(probs->tx16[i], (*counts->tx16p)[i]); -+ adapt_probs_variant_e(probs->tx32[i], (*counts->tx32p)[i]); -+ } -+ -+ adapt_probs_variant_e(probs->mv.joint, *counts->mv_joint); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->mv.sign); i++) { -+ probs->mv.sign[i] = adapt_prob(probs->mv.sign[i], (*counts->sign)[i]); -+ -+ adapt_probs_variant_g(probs->mv.classes[i], (*counts->classes)[i]); -+ -+ probs->mv.class0_bit[i] = adapt_prob(probs->mv.class0_bit[i], (*counts->class0)[i]); -+ -+ for (j = 0; j < ARRAY_SIZE(probs->mv.bits[0]); j++) -+ probs->mv.bits[i][j] = adapt_prob(probs->mv.bits[i][j], -+ (*counts->bits)[i][j]); -+ -+ for (j = 0; j < ARRAY_SIZE(probs->mv.class0_fr[0]); j++) -+ adapt_probs_variant_e(probs->mv.class0_fr[i][j], -+ (*counts->class0_fp)[i][j]); -+ -+ adapt_probs_variant_e(probs->mv.fr[i], (*counts->fp)[i]); -+ -+ if (!(flags & V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV)) -+ continue; -+ -+ probs->mv.class0_hp[i] = adapt_prob(probs->mv.class0_hp[i], -+ (*counts->class0_hp)[i]); -+ -+ probs->mv.hp[i] = adapt_prob(probs->mv.hp[i], (*counts->hp)[i]); -+ } -+} -+EXPORT_SYMBOL_GPL(v4l2_vp9_adapt_noncoef_probs); -+ -+bool -+v4l2_vp9_seg_feat_enabled(const u8 *feature_enabled, -+ unsigned int feature, -+ unsigned int segid) -+{ -+ u8 mask = V4L2_VP9_SEGMENT_FEATURE_ENABLED(feature); -+ -+ return !!(feature_enabled[segid] & mask); -+} -+EXPORT_SYMBOL_GPL(v4l2_vp9_seg_feat_enabled); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("V4L2 VP9 Helpers"); -+MODULE_AUTHOR("Andrzej Pietrasiewicz "); -diff --git a/include/media/v4l2-vp9.h b/include/media/v4l2-vp9.h -new file mode 100644 -index 000000000000..05478ad6d4ab ---- /dev/null -+++ b/include/media/v4l2-vp9.h -@@ -0,0 +1,233 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * Helper functions for vp9 codecs. -+ * -+ * Copyright (c) 2021 Collabora, Ltd. -+ * -+ * Author: Andrzej Pietrasiewicz -+ */ -+ -+#ifndef _MEDIA_V4L2_VP9_H -+#define _MEDIA_V4L2_VP9_H -+ -+#include -+ -+/** -+ * struct v4l2_vp9_frame_mv_context - motion vector-related probabilities -+ * -+ * @joint: motion vector joint probabilities. -+ * @sign: motion vector sign probabilities. -+ * @classes: motion vector class probabilities. -+ * @class0_bit: motion vector class0 bit probabilities. -+ * @bits: motion vector bits probabilities. -+ * @class0_fr: motion vector class0 fractional bit probabilities. -+ * @fr: motion vector fractional bit probabilities. -+ * @class0_hp: motion vector class0 high precision fractional bit probabilities. -+ * @hp: motion vector high precision fractional bit probabilities. -+ * -+ * A member of v4l2_vp9_frame_context. -+ */ -+struct v4l2_vp9_frame_mv_context { -+ u8 joint[3]; -+ u8 sign[2]; -+ u8 classes[2][10]; -+ u8 class0_bit[2]; -+ u8 bits[2][10]; -+ u8 class0_fr[2][2][3]; -+ u8 fr[2][3]; -+ u8 class0_hp[2]; -+ u8 hp[2]; -+}; -+ -+/** -+ * struct v4l2_vp9_frame_context - frame probabilities, including motion-vector related -+ * -+ * @tx8: TX 8x8 probabilities. -+ * @tx16: TX 16x16 probabilities. -+ * @tx32: TX 32x32 probabilities. -+ * @coef: coefficient probabilities. -+ * @skip: skip probabilities. -+ * @inter_mode: inter mode probabilities. -+ * @interp_filter: interpolation filter probabilities. -+ * @is_inter: is inter-block probabilities. -+ * @comp_mode: compound prediction mode probabilities. -+ * @single_ref: single ref probabilities. -+ * @comp_ref: compound ref probabilities. -+ * @y_mode: Y prediction mode probabilities. -+ * @uv_mode: UV prediction mode probabilities. -+ * @partition: partition probabilities. -+ * @mv: motion vector probabilities. -+ * -+ * Drivers which need to keep track of frame context(s) can use this struct. -+ * The members correspond to probability tables, which are specified only implicitly in the -+ * vp9 spec. Section 10.5 "Default probability tables" contains all the types of involved -+ * tables, i.e. the actual tables are of the same kind, and when they are reset (which is -+ * mandated by the spec sometimes) they are overwritten with values from the default tables. -+ */ -+struct v4l2_vp9_frame_context { -+ u8 tx8[2][1]; -+ u8 tx16[2][2]; -+ u8 tx32[2][3]; -+ u8 coef[4][2][2][6][6][3]; -+ u8 skip[3]; -+ u8 inter_mode[7][3]; -+ u8 interp_filter[4][2]; -+ u8 is_inter[4]; -+ u8 comp_mode[5]; -+ u8 single_ref[5][2]; -+ u8 comp_ref[5]; -+ u8 y_mode[4][9]; -+ u8 uv_mode[10][9]; -+ u8 partition[16][3]; -+ -+ struct v4l2_vp9_frame_mv_context mv; -+}; -+ -+/** -+ * struct v4l2_vp9_frame_symbol_counts - pointers to arrays of symbol counts -+ * -+ * @partition: partition counts. -+ * @skip: skip counts. -+ * @intra_inter: is inter-block counts. -+ * @tx32p: TX32 counts. -+ * @tx16p: TX16 counts. -+ * @tx8p: TX8 counts. -+ * @y_mode: Y prediction mode counts. -+ * @uv_mode: UV prediction mode counts. -+ * @comp: compound prediction mode counts. -+ * @comp_ref: compound ref counts. -+ * @single_ref: single ref counts. -+ * @mv_mode: inter mode counts. -+ * @filter: interpolation filter counts. -+ * @mv_joint: motion vector joint counts. -+ * @sign: motion vector sign counts. -+ * @classes: motion vector class counts. -+ * @class0: motion vector class0 bit counts. -+ * @bits: motion vector bits counts. -+ * @class0_fp: motion vector class0 fractional bit counts. -+ * @fp: motion vector fractional bit counts. -+ * @class0_hp: motion vector class0 high precision fractional bit counts. -+ * @hp: motion vector high precision fractional bit counts. -+ * @coeff: coefficient counts. -+ * @eob: eob counts -+ * -+ * The fields correspond to what is specified in section 8.3 "Clear counts process" of the spec. -+ * Different pieces of hardware can report the counts in different order, so we cannot rely on -+ * simply overlaying a struct on a relevant block of memory. Instead we provide pointers to -+ * arrays or array of pointers to arrays in case of coeff, or array of pointers for eob. -+ */ -+struct v4l2_vp9_frame_symbol_counts { -+ u32 (*partition)[16][4]; -+ u32 (*skip)[3][2]; -+ u32 (*intra_inter)[4][2]; -+ u32 (*tx32p)[2][4]; -+ u32 (*tx16p)[2][4]; -+ u32 (*tx8p)[2][2]; -+ u32 (*y_mode)[4][10]; -+ u32 (*uv_mode)[10][10]; -+ u32 (*comp)[5][2]; -+ u32 (*comp_ref)[5][2]; -+ u32 (*single_ref)[5][2][2]; -+ u32 (*mv_mode)[7][4]; -+ u32 (*filter)[4][3]; -+ u32 (*mv_joint)[4]; -+ u32 (*sign)[2][2]; -+ u32 (*classes)[2][11]; -+ u32 (*class0)[2][2]; -+ u32 (*bits)[2][10][2]; -+ u32 (*class0_fp)[2][2][4]; -+ u32 (*fp)[2][4]; -+ u32 (*class0_hp)[2][2]; -+ u32 (*hp)[2][2]; -+ u32 (*coeff[4][2][2][6][6])[3]; -+ u32 *eob[4][2][2][6][6][2]; -+}; -+ -+extern const u8 v4l2_vp9_kf_y_mode_prob[10][10][9]; /* Section 10.4 of the spec */ -+extern const u8 v4l2_vp9_kf_partition_probs[16][3]; /* Section 10.4 of the spec */ -+extern const u8 v4l2_vp9_kf_uv_mode_prob[10][9]; /* Section 10.4 of the spec */ -+extern const struct v4l2_vp9_frame_context v4l2_vp9_default_probs; /* Section 10.5 of the spec */ -+ -+/** -+ * v4l2_vp9_fw_update_probs() - Perform forward update of vp9 probabilities -+ * -+ * @probs: current probabilities values -+ * @deltas: delta values from compressed header -+ * @dec_params: vp9 frame decoding parameters -+ * -+ * This function performs forward updates of probabilities for the vp9 boolean decoder. -+ * The frame header can contain a directive to update the probabilities (deltas), if so, then -+ * the deltas are provided in the header, too. The userspace parses those and passes the said -+ * deltas struct to the kernel. -+ */ -+void v4l2_vp9_fw_update_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas, -+ const struct v4l2_ctrl_vp9_frame *dec_params); -+ -+/** -+ * v4l2_vp9_reset_frame_ctx() - Reset appropriate frame context -+ * -+ * @dec_params: vp9 frame decoding parameters -+ * @frame_context: array of the 4 frame contexts -+ * -+ * This function resets appropriate frame contexts, based on what's in dec_params. -+ * -+ * Returns the frame context index after the update, which might be reset to zero if -+ * mandated by the spec. -+ */ -+u8 v4l2_vp9_reset_frame_ctx(const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct v4l2_vp9_frame_context *frame_context); -+ -+/** -+ * v4l2_vp9_adapt_coef_probs() - Perform backward update of vp9 coefficients probabilities -+ * -+ * @probs: current probabilities values -+ * @counts: values of symbol counts after the current frame has been decoded -+ * @use_128: flag to request that 128 is used as update factor if true, otherwise 112 is used -+ * @frame_is_intra: flag indicating that FrameIsIntra is true -+ * -+ * This function performs backward updates of coefficients probabilities for the vp9 boolean -+ * decoder. After a frame has been decoded the counts of how many times a given symbol has -+ * occurred are known and are used to update the probability of each symbol. -+ */ -+void v4l2_vp9_adapt_coef_probs(struct v4l2_vp9_frame_context *probs, -+ struct v4l2_vp9_frame_symbol_counts *counts, -+ bool use_128, -+ bool frame_is_intra); -+ -+/** -+ * v4l2_vp9_adapt_noncoef_probs() - Perform backward update of vp9 non-coefficients probabilities -+ * -+ * @probs: current probabilities values -+ * @counts: values of symbol counts after the current frame has been decoded -+ * @reference_mode: specifies the type of inter prediction to be used. See -+ * &v4l2_vp9_reference_mode for more details -+ * @interpolation_filter: specifies the filter selection used for performing inter prediction. -+ * See &v4l2_vp9_interpolation_filter for more details -+ * @tx_mode: specifies the TX mode. See &v4l2_vp9_tx_mode for more details -+ * @flags: combination of V4L2_VP9_FRAME_FLAG_* flags -+ * -+ * This function performs backward updates of non-coefficients probabilities for the vp9 boolean -+ * decoder. After a frame has been decoded the counts of how many times a given symbol has -+ * occurred are known and are used to update the probability of each symbol. -+ */ -+void v4l2_vp9_adapt_noncoef_probs(struct v4l2_vp9_frame_context *probs, -+ struct v4l2_vp9_frame_symbol_counts *counts, -+ u8 reference_mode, u8 interpolation_filter, u8 tx_mode, -+ u32 flags); -+ -+/** -+ * v4l2_vp9_seg_feat_enabled() - Check if a segmentation feature is enabled -+ * -+ * @feature_enabled: array of 8-bit flags (for all segments) -+ * @feature: id of the feature to check -+ * @segid: id of the segment to look up -+ * -+ * This function returns true if a given feature is active in a given segment. -+ */ -+bool -+v4l2_vp9_seg_feat_enabled(const u8 *feature_enabled, -+ unsigned int feature, -+ unsigned int segid); -+ -+#endif /* _MEDIA_V4L2_VP9_H */ diff --git a/projects/NXP/devices/iMX8/patches/linux/0074-media-hantro-Rename-registers.patch b/projects/NXP/devices/iMX8/patches/linux/0074-media-hantro-Rename-registers.patch deleted file mode 100644 index 84d420e852..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0074-media-hantro-Rename-registers.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:38 +0100 -Subject: [PATCH] media: hantro: Rename registers - -Add more consistency in the way registers are named. - -Signed-off-by: Andrzej Pietrasiewicz -Reviewed-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil ---- - .../staging/media/hantro/hantro_g2_hevc_dec.c | 40 +++++++++---------- - drivers/staging/media/hantro/hantro_g2_regs.h | 28 ++++++------- - 2 files changed, 34 insertions(+), 34 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -index 76a921163b9a..abae36f9b418 100644 ---- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -@@ -448,9 +448,9 @@ static int set_ref(struct hantro_ctx *ctx) - if (dpb[i].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR) - dpb_longterm_e |= BIT(V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1 - i); - -- hantro_write_addr(vpu, G2_REG_ADDR_REF(i), luma_addr); -- hantro_write_addr(vpu, G2_REG_CHR_REF(i), chroma_addr); -- hantro_write_addr(vpu, G2_REG_DMV_REF(i), mv_addr); -+ hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr); -+ hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr); -+ hantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr); - } - - luma_addr = hantro_hevc_get_ref_buf(ctx, decode_params->pic_order_cnt_val); -@@ -460,20 +460,20 @@ static int set_ref(struct hantro_ctx *ctx) - chroma_addr = luma_addr + cr_offset; - mv_addr = luma_addr + mv_offset; - -- hantro_write_addr(vpu, G2_REG_ADDR_REF(i), luma_addr); -- hantro_write_addr(vpu, G2_REG_CHR_REF(i), chroma_addr); -- hantro_write_addr(vpu, G2_REG_DMV_REF(i++), mv_addr); -+ hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr); -+ hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr); -+ hantro_write_addr(vpu, G2_REF_MV_ADDR(i++), mv_addr); - -- hantro_write_addr(vpu, G2_ADDR_DST, luma_addr); -- hantro_write_addr(vpu, G2_ADDR_DST_CHR, chroma_addr); -- hantro_write_addr(vpu, G2_ADDR_DST_MV, mv_addr); -+ hantro_write_addr(vpu, G2_OUT_LUMA_ADDR, luma_addr); -+ hantro_write_addr(vpu, G2_OUT_CHROMA_ADDR, chroma_addr); -+ hantro_write_addr(vpu, G2_OUT_MV_ADDR, mv_addr); - - hantro_hevc_ref_remove_unused(ctx); - - for (; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) { -- hantro_write_addr(vpu, G2_REG_ADDR_REF(i), 0); -- hantro_write_addr(vpu, G2_REG_CHR_REF(i), 0); -- hantro_write_addr(vpu, G2_REG_DMV_REF(i), 0); -+ hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), 0); -+ hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), 0); -+ hantro_write_addr(vpu, G2_REF_MV_ADDR(i), 0); - } - - hantro_reg_write(vpu, &g2_refer_lterm_e, dpb_longterm_e); -@@ -499,7 +499,7 @@ static void set_buffers(struct hantro_ctx *ctx) - src_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); - src_buf_len = vb2_plane_size(&src_buf->vb2_buf, 0); - -- hantro_write_addr(vpu, G2_ADDR_STR, src_dma); -+ hantro_write_addr(vpu, G2_STREAM_ADDR, src_dma); - hantro_reg_write(vpu, &g2_stream_len, src_len); - hantro_reg_write(vpu, &g2_strm_buffer_len, src_buf_len); - hantro_reg_write(vpu, &g2_strm_start_offset, 0); -@@ -508,12 +508,12 @@ static void set_buffers(struct hantro_ctx *ctx) - /* Destination (decoded frame) buffer. */ - dst_dma = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf); - -- hantro_write_addr(vpu, G2_RASTER_SCAN, dst_dma); -- hantro_write_addr(vpu, G2_RASTER_SCAN_CHR, dst_dma + cr_offset); -- hantro_write_addr(vpu, G2_ADDR_TILE_SIZE, ctx->hevc_dec.tile_sizes.dma); -- hantro_write_addr(vpu, G2_TILE_FILTER, ctx->hevc_dec.tile_filter.dma); -- hantro_write_addr(vpu, G2_TILE_SAO, ctx->hevc_dec.tile_sao.dma); -- hantro_write_addr(vpu, G2_TILE_BSD, ctx->hevc_dec.tile_bsd.dma); -+ hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma); -+ hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + cr_offset); -+ hantro_write_addr(vpu, G2_TILE_SIZES_ADDR, ctx->hevc_dec.tile_sizes.dma); -+ hantro_write_addr(vpu, G2_TILE_FILTER_ADDR, ctx->hevc_dec.tile_filter.dma); -+ hantro_write_addr(vpu, G2_TILE_SAO_ADDR, ctx->hevc_dec.tile_sao.dma); -+ hantro_write_addr(vpu, G2_TILE_BSD_ADDR, ctx->hevc_dec.tile_bsd.dma); - } - - static void prepare_scaling_list_buffer(struct hantro_ctx *ctx) -@@ -563,7 +563,7 @@ static void prepare_scaling_list_buffer(struct hantro_ctx *ctx) - for (k = 0; k < 8; k++) - *p++ = sc->scaling_list_32x32[i][8 * k + j]; - -- hantro_write_addr(vpu, HEVC_SCALING_LIST, ctx->hevc_dec.scaling_lists.dma); -+ hantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma); - } - - static void hantro_g2_check_idle(struct hantro_dev *vpu) -diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h -index bb22fa921914..24b18f839ff8 100644 ---- a/drivers/staging/media/hantro/hantro_g2_regs.h -+++ b/drivers/staging/media/hantro/hantro_g2_regs.h -@@ -177,20 +177,20 @@ - #define G2_REG_CONFIG_DEC_CLK_GATE_E BIT(16) - #define G2_REG_CONFIG_DEC_CLK_GATE_IDLE_E BIT(17) - --#define G2_ADDR_DST (G2_SWREG(65)) --#define G2_REG_ADDR_REF(i) (G2_SWREG(67) + ((i) * 0x8)) --#define G2_ADDR_DST_CHR (G2_SWREG(99)) --#define G2_REG_CHR_REF(i) (G2_SWREG(101) + ((i) * 0x8)) --#define G2_ADDR_DST_MV (G2_SWREG(133)) --#define G2_REG_DMV_REF(i) (G2_SWREG(135) + ((i) * 0x8)) --#define G2_ADDR_TILE_SIZE (G2_SWREG(167)) --#define G2_ADDR_STR (G2_SWREG(169)) --#define HEVC_SCALING_LIST (G2_SWREG(171)) --#define G2_RASTER_SCAN (G2_SWREG(175)) --#define G2_RASTER_SCAN_CHR (G2_SWREG(177)) --#define G2_TILE_FILTER (G2_SWREG(179)) --#define G2_TILE_SAO (G2_SWREG(181)) --#define G2_TILE_BSD (G2_SWREG(183)) -+#define G2_OUT_LUMA_ADDR (G2_SWREG(65)) -+#define G2_REF_LUMA_ADDR(i) (G2_SWREG(67) + ((i) * 0x8)) -+#define G2_OUT_CHROMA_ADDR (G2_SWREG(99)) -+#define G2_REF_CHROMA_ADDR(i) (G2_SWREG(101) + ((i) * 0x8)) -+#define G2_OUT_MV_ADDR (G2_SWREG(133)) -+#define G2_REF_MV_ADDR(i) (G2_SWREG(135) + ((i) * 0x8)) -+#define G2_TILE_SIZES_ADDR (G2_SWREG(167)) -+#define G2_STREAM_ADDR (G2_SWREG(169)) -+#define G2_HEVC_SCALING_LIST_ADDR (G2_SWREG(171)) -+#define G2_RS_OUT_LUMA_ADDR (G2_SWREG(175)) -+#define G2_RS_OUT_CHROMA_ADDR (G2_SWREG(177)) -+#define G2_TILE_FILTER_ADDR (G2_SWREG(179)) -+#define G2_TILE_SAO_ADDR (G2_SWREG(181)) -+#define G2_TILE_BSD_ADDR (G2_SWREG(183)) - - #define g2_strm_buffer_len G2_DEC_REG(258, 0, 0xffffffff) - #define g2_strm_start_offset G2_DEC_REG(259, 0, 0xffffffff) diff --git a/projects/NXP/devices/iMX8/patches/linux/0075-media-hantro-Prepare-for-other-G2-codecs.patch b/projects/NXP/devices/iMX8/patches/linux/0075-media-hantro-Prepare-for-other-G2-codecs.patch deleted file mode 100644 index 9ec34c1123..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0075-media-hantro-Prepare-for-other-G2-codecs.patch +++ /dev/null @@ -1,178 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:39 +0100 -Subject: [PATCH] media: hantro: Prepare for other G2 codecs - -VeriSilicon Hantro G2 core supports other codecs besides hevc. -Factor out some common code in preparation for vp9 support. - -Signed-off-by: Andrzej Pietrasiewicz -Reviewed-by: Benjamin Gaignard -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/Makefile | 1 + - drivers/staging/media/hantro/hantro.h | 7 +++++ - drivers/staging/media/hantro/hantro_drv.c | 5 +++ - drivers/staging/media/hantro/hantro_g2.c | 26 ++++++++++++++++ - .../staging/media/hantro/hantro_g2_hevc_dec.c | 31 ------------------- - drivers/staging/media/hantro/hantro_g2_regs.h | 7 +++++ - drivers/staging/media/hantro/hantro_hw.h | 2 ++ - 7 files changed, 48 insertions(+), 31 deletions(-) - create mode 100644 drivers/staging/media/hantro/hantro_g2.c - -diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile -index 90036831fec4..fe6d84871d07 100644 ---- a/drivers/staging/media/hantro/Makefile -+++ b/drivers/staging/media/hantro/Makefile -@@ -12,6 +12,7 @@ hantro-vpu-y += \ - hantro_g1_mpeg2_dec.o \ - hantro_g2_hevc_dec.o \ - hantro_g1_vp8_dec.o \ -+ hantro_g2.o \ - rockchip_vpu2_hw_jpeg_enc.o \ - rockchip_vpu2_hw_h264_dec.o \ - rockchip_vpu2_hw_mpeg2_dec.o \ -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index dd5e56765d4e..d91eb2b1c509 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -369,6 +369,13 @@ static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg) - writel(val, vpu->dec_base + reg); - } - -+static inline void hantro_write_addr(struct hantro_dev *vpu, -+ unsigned long offset, -+ dma_addr_t addr) -+{ -+ vdpu_write(vpu, addr & 0xffffffff, offset); -+} -+ - static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg) - { - u32 val = readl(vpu->dec_base + reg); -diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c -index fb82b9297a2b..bb72e5e208b7 100644 ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -907,6 +907,11 @@ static int hantro_probe(struct platform_device *pdev) - vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset; - vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset; - -+ /** -+ * TODO: Eventually allow taking advantage of full 64-bit address space. -+ * Until then we assume the MSB portion of buffers' base addresses is -+ * always 0 due to this masking operation. -+ */ - ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32)); - if (ret) { - dev_err(vpu->dev, "Could not set DMA coherent mask.\n"); -diff --git a/drivers/staging/media/hantro/hantro_g2.c b/drivers/staging/media/hantro/hantro_g2.c -new file mode 100644 -index 000000000000..6f3e1f797f83 ---- /dev/null -+++ b/drivers/staging/media/hantro/hantro_g2.c -@@ -0,0 +1,26 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Hantro VPU codec driver -+ * -+ * Copyright (C) 2021 Collabora Ltd, Andrzej Pietrasiewicz -+ */ -+ -+#include "hantro_hw.h" -+#include "hantro_g2_regs.h" -+ -+void hantro_g2_check_idle(struct hantro_dev *vpu) -+{ -+ int i; -+ -+ for (i = 0; i < 3; i++) { -+ u32 status; -+ -+ /* Make sure the VPU is idle */ -+ status = vdpu_read(vpu, G2_REG_INTERRUPT); -+ if (status & G2_REG_INTERRUPT_DEC_E) { -+ dev_warn(vpu->dev, "device still running, aborting"); -+ status |= G2_REG_INTERRUPT_DEC_ABORT_E | G2_REG_INTERRUPT_DEC_IRQ_DIS; -+ vdpu_write(vpu, status, G2_REG_INTERRUPT); -+ } -+ } -+} -diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -index abae36f9b418..f62608b0b408 100644 ---- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -@@ -8,20 +8,6 @@ - #include "hantro_hw.h" - #include "hantro_g2_regs.h" - --#define HEVC_DEC_MODE 0xC -- --#define BUS_WIDTH_32 0 --#define BUS_WIDTH_64 1 --#define BUS_WIDTH_128 2 --#define BUS_WIDTH_256 3 -- --static inline void hantro_write_addr(struct hantro_dev *vpu, -- unsigned long offset, -- dma_addr_t addr) --{ -- vdpu_write(vpu, addr & 0xffffffff, offset); --} -- - static void prepare_tile_info_buffer(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -@@ -566,23 +552,6 @@ static void prepare_scaling_list_buffer(struct hantro_ctx *ctx) - hantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma); - } - --static void hantro_g2_check_idle(struct hantro_dev *vpu) --{ -- int i; -- -- for (i = 0; i < 3; i++) { -- u32 status; -- -- /* Make sure the VPU is idle */ -- status = vdpu_read(vpu, G2_REG_INTERRUPT); -- if (status & G2_REG_INTERRUPT_DEC_E) { -- dev_warn(vpu->dev, "device still running, aborting"); -- status |= G2_REG_INTERRUPT_DEC_ABORT_E | G2_REG_INTERRUPT_DEC_IRQ_DIS; -- vdpu_write(vpu, status, G2_REG_INTERRUPT); -- } -- } --} -- - int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h -index 24b18f839ff8..136ba6d98a1f 100644 ---- a/drivers/staging/media/hantro/hantro_g2_regs.h -+++ b/drivers/staging/media/hantro/hantro_g2_regs.h -@@ -27,6 +27,13 @@ - #define G2_REG_INTERRUPT_DEC_IRQ_DIS BIT(4) - #define G2_REG_INTERRUPT_DEC_E BIT(0) - -+#define HEVC_DEC_MODE 0xc -+ -+#define BUS_WIDTH_32 0 -+#define BUS_WIDTH_64 1 -+#define BUS_WIDTH_128 2 -+#define BUS_WIDTH_256 3 -+ - #define g2_strm_swap G2_DEC_REG(2, 28, 0xf) - #define g2_dirmv_swap G2_DEC_REG(2, 20, 0xf) - -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index 2f85430682d8..1d869abf90b2 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -312,4 +312,6 @@ void hantro_vp8_dec_exit(struct hantro_ctx *ctx); - void hantro_vp8_prob_update(struct hantro_ctx *ctx, - const struct v4l2_ctrl_vp8_frame *hdr); - -+void hantro_g2_check_idle(struct hantro_dev *vpu); -+ - #endif /* HANTRO_HW_H_ */ diff --git a/projects/NXP/devices/iMX8/patches/linux/0076-media-hantro-Support-VP9-on-the-G2-core.patch b/projects/NXP/devices/iMX8/patches/linux/0076-media-hantro-Support-VP9-on-the-G2-core.patch deleted file mode 100644 index 1b487a4208..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0076-media-hantro-Support-VP9-on-the-G2-core.patch +++ /dev/null @@ -1,1888 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:40 +0100 -Subject: [PATCH] media: hantro: Support VP9 on the G2 core - -VeriSilicon Hantro G2 core supports VP9 codec. - -Signed-off-by: Andrzej Pietrasiewicz -Reviewed-by: Benjamin Gaignard -Signed-off-by: Hans Verkuil -[hverkuil: add kerneldoc line for HANTRO_MODE_VP9_DEC] ---- - drivers/staging/media/hantro/Kconfig | 1 + - drivers/staging/media/hantro/Makefile | 6 +- - drivers/staging/media/hantro/hantro.h | 27 + - drivers/staging/media/hantro/hantro_drv.c | 18 +- - drivers/staging/media/hantro/hantro_g2_regs.h | 97 ++ - .../staging/media/hantro/hantro_g2_vp9_dec.c | 980 ++++++++++++++++++ - drivers/staging/media/hantro/hantro_hw.h | 99 ++ - drivers/staging/media/hantro/hantro_v4l2.c | 6 + - drivers/staging/media/hantro/hantro_vp9.c | 240 +++++ - drivers/staging/media/hantro/hantro_vp9.h | 102 ++ - drivers/staging/media/hantro/imx8m_vpu_hw.c | 22 +- - 11 files changed, 1594 insertions(+), 4 deletions(-) - create mode 100644 drivers/staging/media/hantro/hantro_g2_vp9_dec.c - create mode 100644 drivers/staging/media/hantro/hantro_vp9.c - create mode 100644 drivers/staging/media/hantro/hantro_vp9.h - -diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig -index 20b1f6d7b69c..00a57d88c92e 100644 ---- a/drivers/staging/media/hantro/Kconfig -+++ b/drivers/staging/media/hantro/Kconfig -@@ -9,6 +9,7 @@ config VIDEO_HANTRO - select VIDEOBUF2_VMALLOC - select V4L2_MEM2MEM_DEV - select V4L2_H264 -+ select V4L2_VP9 - help - Support for the Hantro IP based Video Processing Units present on - Rockchip and NXP i.MX8M SoCs, which accelerate video and image -diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile -index fe6d84871d07..28af0a1ee4bf 100644 ---- a/drivers/staging/media/hantro/Makefile -+++ b/drivers/staging/media/hantro/Makefile -@@ -10,9 +10,10 @@ hantro-vpu-y += \ - hantro_g1.o \ - hantro_g1_h264_dec.o \ - hantro_g1_mpeg2_dec.o \ -- hantro_g2_hevc_dec.o \ - hantro_g1_vp8_dec.o \ - hantro_g2.o \ -+ hantro_g2_hevc_dec.o \ -+ hantro_g2_vp9_dec.o \ - rockchip_vpu2_hw_jpeg_enc.o \ - rockchip_vpu2_hw_h264_dec.o \ - rockchip_vpu2_hw_mpeg2_dec.o \ -@@ -21,7 +22,8 @@ hantro-vpu-y += \ - hantro_h264.o \ - hantro_hevc.o \ - hantro_mpeg2.o \ -- hantro_vp8.o -+ hantro_vp8.o \ -+ hantro_vp9.o - - hantro-vpu-$(CONFIG_VIDEO_HANTRO_IMX8M) += \ - imx8m_vpu_hw.o -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index d91eb2b1c509..7da23f7f207a 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -36,6 +36,7 @@ struct hantro_postproc_ops; - #define HANTRO_VP8_DECODER BIT(17) - #define HANTRO_H264_DECODER BIT(18) - #define HANTRO_HEVC_DECODER BIT(19) -+#define HANTRO_VP9_DECODER BIT(20) - #define HANTRO_DECODERS 0xffff0000 - - /** -@@ -102,6 +103,7 @@ struct hantro_variant { - * @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder. - * @HANTRO_MODE_VP8_DEC: VP8 decoder. - * @HANTRO_MODE_HEVC_DEC: HEVC decoder. -+ * @HANTRO_MODE_VP9_DEC: VP9 decoder. - */ - enum hantro_codec_mode { - HANTRO_MODE_NONE = -1, -@@ -110,6 +112,7 @@ enum hantro_codec_mode { - HANTRO_MODE_MPEG2_DEC, - HANTRO_MODE_VP8_DEC, - HANTRO_MODE_HEVC_DEC, -+ HANTRO_MODE_VP9_DEC, - }; - - /* -@@ -223,6 +226,7 @@ struct hantro_dev { - * @mpeg2_dec: MPEG-2-decoding context. - * @vp8_dec: VP8-decoding context. - * @hevc_dec: HEVC-decoding context. -+ * @vp9_dec: VP9-decoding context. - */ - struct hantro_ctx { - struct hantro_dev *dev; -@@ -250,6 +254,7 @@ struct hantro_ctx { - struct hantro_mpeg2_dec_hw_ctx mpeg2_dec; - struct hantro_vp8_dec_hw_ctx vp8_dec; - struct hantro_hevc_dec_hw_ctx hevc_dec; -+ struct hantro_vp9_dec_hw_ctx vp9_dec; - }; - }; - -@@ -299,6 +304,22 @@ struct hantro_postproc_regs { - struct hantro_reg display_width; - }; - -+struct hantro_vp9_decoded_buffer_info { -+ /* Info needed when the decoded frame serves as a reference frame. */ -+ unsigned short width; -+ unsigned short height; -+ u32 bit_depth : 4; -+}; -+ -+struct hantro_decoded_buffer { -+ /* Must be the first field in this struct. */ -+ struct v4l2_m2m_buffer base; -+ -+ union { -+ struct hantro_vp9_decoded_buffer_info vp9; -+ }; -+}; -+ - /* Logging helpers */ - - /** -@@ -436,6 +457,12 @@ hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb) - return vb2_dma_contig_plane_dma_addr(vb, 0); - } - -+static inline struct hantro_decoded_buffer * -+vb2_to_hantro_decoded_buf(struct vb2_buffer *buf) -+{ -+ return container_of(buf, struct hantro_decoded_buffer, base.vb.vb2_buf); -+} -+ - void hantro_postproc_disable(struct hantro_ctx *ctx); - void hantro_postproc_enable(struct hantro_ctx *ctx); - void hantro_postproc_free(struct hantro_ctx *ctx); -diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c -index bb72e5e208b7..ab2467998d29 100644 ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -232,7 +232,7 @@ queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) - dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; - dst_vq->drv_priv = ctx; - dst_vq->ops = &hantro_queue_ops; -- dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); -+ dst_vq->buf_struct_size = sizeof(struct hantro_decoded_buffer); - dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; - dst_vq->lock = &ctx->dev->vpu_mutex; - dst_vq->dev = ctx->dev->v4l2_dev.dev; -@@ -263,6 +263,12 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) - if (sps->bit_depth_luma_minus8 != 0) - /* Only 8-bit is supported */ - return -EINVAL; -+ } else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) { -+ const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame; -+ -+ /* We only support profile 0 */ -+ if (dec_params->profile != 0) -+ return -EINVAL; - } - return 0; - } -@@ -461,6 +467,16 @@ static const struct hantro_ctrl controls[] = { - .step = 1, - .ops = &hantro_hevc_ctrl_ops, - }, -+ }, { -+ .codec = HANTRO_VP9_DECODER, -+ .cfg = { -+ .id = V4L2_CID_STATELESS_VP9_FRAME, -+ }, -+ }, { -+ .codec = HANTRO_VP9_DECODER, -+ .cfg = { -+ .id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR, -+ }, - }, - }; - -diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h -index 136ba6d98a1f..9c857dd1ad9b 100644 ---- a/drivers/staging/media/hantro/hantro_g2_regs.h -+++ b/drivers/staging/media/hantro/hantro_g2_regs.h -@@ -28,6 +28,7 @@ - #define G2_REG_INTERRUPT_DEC_E BIT(0) - - #define HEVC_DEC_MODE 0xc -+#define VP9_DEC_MODE 0xd - - #define BUS_WIDTH_32 0 - #define BUS_WIDTH_64 1 -@@ -49,6 +50,7 @@ - #define g2_pic_height_in_cbs G2_DEC_REG(4, 6, 0x1fff) - #define g2_num_ref_frames G2_DEC_REG(4, 0, 0x1f) - -+#define g2_start_bit G2_DEC_REG(5, 25, 0x7f) - #define g2_scaling_list_e G2_DEC_REG(5, 24, 0x1) - #define g2_cb_qp_offset G2_DEC_REG(5, 19, 0x1f) - #define g2_cr_qp_offset G2_DEC_REG(5, 14, 0x1f) -@@ -84,6 +86,7 @@ - #define g2_bit_depth_y_minus8 G2_DEC_REG(8, 6, 0x3) - #define g2_bit_depth_c_minus8 G2_DEC_REG(8, 4, 0x3) - #define g2_output_8_bits G2_DEC_REG(8, 3, 0x1) -+#define g2_output_format G2_DEC_REG(8, 0, 0x7) - - #define g2_refidx1_active G2_DEC_REG(9, 19, 0x1f) - #define g2_refidx0_active G2_DEC_REG(9, 14, 0x1f) -@@ -96,6 +99,14 @@ - #define g2_tile_e G2_DEC_REG(10, 1, 0x1) - #define g2_entropy_sync_e G2_DEC_REG(10, 0, 0x1) - -+#define vp9_transform_mode G2_DEC_REG(11, 27, 0x7) -+#define vp9_filt_sharpness G2_DEC_REG(11, 21, 0x7) -+#define vp9_mcomp_filt_type G2_DEC_REG(11, 8, 0x7) -+#define vp9_high_prec_mv_e G2_DEC_REG(11, 7, 0x1) -+#define vp9_comp_pred_mode G2_DEC_REG(11, 4, 0x3) -+#define vp9_gref_sign_bias G2_DEC_REG(11, 2, 0x1) -+#define vp9_aref_sign_bias G2_DEC_REG(11, 0, 0x1) -+ - #define g2_refer_lterm_e G2_DEC_REG(12, 16, 0xffff) - #define g2_min_cb_size G2_DEC_REG(12, 13, 0x7) - #define g2_max_cb_size G2_DEC_REG(12, 10, 0x7) -@@ -154,6 +165,50 @@ - #define g2_partial_ctb_y G2_DEC_REG(20, 30, 0x1) - #define g2_pic_width_4x4 G2_DEC_REG(20, 16, 0xfff) - #define g2_pic_height_4x4 G2_DEC_REG(20, 0, 0xfff) -+ -+#define vp9_qp_delta_y_dc G2_DEC_REG(13, 23, 0x3f) -+#define vp9_qp_delta_ch_dc G2_DEC_REG(13, 17, 0x3f) -+#define vp9_qp_delta_ch_ac G2_DEC_REG(13, 11, 0x3f) -+#define vp9_last_sign_bias G2_DEC_REG(13, 10, 0x1) -+#define vp9_lossless_e G2_DEC_REG(13, 9, 0x1) -+#define vp9_comp_pred_var_ref1 G2_DEC_REG(13, 7, 0x3) -+#define vp9_comp_pred_var_ref0 G2_DEC_REG(13, 5, 0x3) -+#define vp9_comp_pred_fixed_ref G2_DEC_REG(13, 3, 0x3) -+#define vp9_segment_temp_upd_e G2_DEC_REG(13, 2, 0x1) -+#define vp9_segment_upd_e G2_DEC_REG(13, 1, 0x1) -+#define vp9_segment_e G2_DEC_REG(13, 0, 0x1) -+ -+#define vp9_filt_level G2_DEC_REG(14, 18, 0x3f) -+#define vp9_refpic_seg0 G2_DEC_REG(14, 15, 0x7) -+#define vp9_skip_seg0 G2_DEC_REG(14, 14, 0x1) -+#define vp9_filt_level_seg0 G2_DEC_REG(14, 8, 0x3f) -+#define vp9_quant_seg0 G2_DEC_REG(14, 0, 0xff) -+ -+#define vp9_refpic_seg1 G2_DEC_REG(15, 15, 0x7) -+#define vp9_skip_seg1 G2_DEC_REG(15, 14, 0x1) -+#define vp9_filt_level_seg1 G2_DEC_REG(15, 8, 0x3f) -+#define vp9_quant_seg1 G2_DEC_REG(15, 0, 0xff) -+ -+#define vp9_refpic_seg2 G2_DEC_REG(16, 15, 0x7) -+#define vp9_skip_seg2 G2_DEC_REG(16, 14, 0x1) -+#define vp9_filt_level_seg2 G2_DEC_REG(16, 8, 0x3f) -+#define vp9_quant_seg2 G2_DEC_REG(16, 0, 0xff) -+ -+#define vp9_refpic_seg3 G2_DEC_REG(17, 15, 0x7) -+#define vp9_skip_seg3 G2_DEC_REG(17, 14, 0x1) -+#define vp9_filt_level_seg3 G2_DEC_REG(17, 8, 0x3f) -+#define vp9_quant_seg3 G2_DEC_REG(17, 0, 0xff) -+ -+#define vp9_refpic_seg4 G2_DEC_REG(18, 15, 0x7) -+#define vp9_skip_seg4 G2_DEC_REG(18, 14, 0x1) -+#define vp9_filt_level_seg4 G2_DEC_REG(18, 8, 0x3f) -+#define vp9_quant_seg4 G2_DEC_REG(18, 0, 0xff) -+ -+#define vp9_refpic_seg5 G2_DEC_REG(19, 15, 0x7) -+#define vp9_skip_seg5 G2_DEC_REG(19, 14, 0x1) -+#define vp9_filt_level_seg5 G2_DEC_REG(19, 8, 0x3f) -+#define vp9_quant_seg5 G2_DEC_REG(19, 0, 0xff) -+ - #define hevc_cur_poc_00 G2_DEC_REG(46, 24, 0xff) - #define hevc_cur_poc_01 G2_DEC_REG(46, 16, 0xff) - #define hevc_cur_poc_02 G2_DEC_REG(46, 8, 0xff) -@@ -174,6 +229,44 @@ - #define hevc_cur_poc_14 G2_DEC_REG(49, 8, 0xff) - #define hevc_cur_poc_15 G2_DEC_REG(49, 0, 0xff) - -+#define vp9_refpic_seg6 G2_DEC_REG(31, 15, 0x7) -+#define vp9_skip_seg6 G2_DEC_REG(31, 14, 0x1) -+#define vp9_filt_level_seg6 G2_DEC_REG(31, 8, 0x3f) -+#define vp9_quant_seg6 G2_DEC_REG(31, 0, 0xff) -+ -+#define vp9_refpic_seg7 G2_DEC_REG(32, 15, 0x7) -+#define vp9_skip_seg7 G2_DEC_REG(32, 14, 0x1) -+#define vp9_filt_level_seg7 G2_DEC_REG(32, 8, 0x3f) -+#define vp9_quant_seg7 G2_DEC_REG(32, 0, 0xff) -+ -+#define vp9_lref_width G2_DEC_REG(33, 16, 0xffff) -+#define vp9_lref_height G2_DEC_REG(33, 0, 0xffff) -+ -+#define vp9_gref_width G2_DEC_REG(34, 16, 0xffff) -+#define vp9_gref_height G2_DEC_REG(34, 0, 0xffff) -+ -+#define vp9_aref_width G2_DEC_REG(35, 16, 0xffff) -+#define vp9_aref_height G2_DEC_REG(35, 0, 0xffff) -+ -+#define vp9_lref_hor_scale G2_DEC_REG(36, 16, 0xffff) -+#define vp9_lref_ver_scale G2_DEC_REG(36, 0, 0xffff) -+ -+#define vp9_gref_hor_scale G2_DEC_REG(37, 16, 0xffff) -+#define vp9_gref_ver_scale G2_DEC_REG(37, 0, 0xffff) -+ -+#define vp9_aref_hor_scale G2_DEC_REG(38, 16, 0xffff) -+#define vp9_aref_ver_scale G2_DEC_REG(38, 0, 0xffff) -+ -+#define vp9_filt_ref_adj_0 G2_DEC_REG(46, 24, 0x7f) -+#define vp9_filt_ref_adj_1 G2_DEC_REG(46, 16, 0x7f) -+#define vp9_filt_ref_adj_2 G2_DEC_REG(46, 8, 0x7f) -+#define vp9_filt_ref_adj_3 G2_DEC_REG(46, 0, 0x7f) -+ -+#define vp9_filt_mb_adj_0 G2_DEC_REG(47, 24, 0x7f) -+#define vp9_filt_mb_adj_1 G2_DEC_REG(47, 16, 0x7f) -+#define vp9_filt_mb_adj_2 G2_DEC_REG(47, 8, 0x7f) -+#define vp9_filt_mb_adj_3 G2_DEC_REG(47, 0, 0x7f) -+ - #define g2_apf_threshold G2_DEC_REG(55, 0, 0xffff) - - #define g2_clk_gate_e G2_DEC_REG(58, 16, 0x1) -@@ -186,6 +279,8 @@ - - #define G2_OUT_LUMA_ADDR (G2_SWREG(65)) - #define G2_REF_LUMA_ADDR(i) (G2_SWREG(67) + ((i) * 0x8)) -+#define G2_VP9_SEGMENT_WRITE_ADDR (G2_SWREG(79)) -+#define G2_VP9_SEGMENT_READ_ADDR (G2_SWREG(81)) - #define G2_OUT_CHROMA_ADDR (G2_SWREG(99)) - #define G2_REF_CHROMA_ADDR(i) (G2_SWREG(101) + ((i) * 0x8)) - #define G2_OUT_MV_ADDR (G2_SWREG(133)) -@@ -193,6 +288,8 @@ - #define G2_TILE_SIZES_ADDR (G2_SWREG(167)) - #define G2_STREAM_ADDR (G2_SWREG(169)) - #define G2_HEVC_SCALING_LIST_ADDR (G2_SWREG(171)) -+#define G2_VP9_CTX_COUNT_ADDR (G2_SWREG(171)) -+#define G2_VP9_PROBS_ADDR (G2_SWREG(173)) - #define G2_RS_OUT_LUMA_ADDR (G2_SWREG(175)) - #define G2_RS_OUT_CHROMA_ADDR (G2_SWREG(177)) - #define G2_TILE_FILTER_ADDR (G2_SWREG(179)) -diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -new file mode 100644 -index 000000000000..fc55b03a8004 ---- /dev/null -+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -@@ -0,0 +1,980 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Hantro VP9 codec driver -+ * -+ * Copyright (C) 2021 Collabora Ltd. -+ */ -+#include "media/videobuf2-core.h" -+#include "media/videobuf2-dma-contig.h" -+#include "media/videobuf2-v4l2.h" -+#include -+#include -+#include -+#include -+ -+#include "hantro.h" -+#include "hantro_vp9.h" -+#include "hantro_g2_regs.h" -+ -+#define G2_ALIGN 16 -+ -+enum hantro_ref_frames { -+ INTRA_FRAME = 0, -+ LAST_FRAME = 1, -+ GOLDEN_FRAME = 2, -+ ALTREF_FRAME = 3, -+ MAX_REF_FRAMES = 4 -+}; -+ -+static int start_prepare_run(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame **dec_params) -+{ -+ const struct v4l2_ctrl_vp9_compressed_hdr *prob_updates; -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ struct v4l2_ctrl *ctrl; -+ unsigned int fctx_idx; -+ -+ /* v4l2-specific stuff */ -+ hantro_start_prepare_run(ctx); -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_handler, V4L2_CID_STATELESS_VP9_FRAME); -+ if (WARN_ON(!ctrl)) -+ return -EINVAL; -+ *dec_params = ctrl->p_cur.p; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_handler, V4L2_CID_STATELESS_VP9_COMPRESSED_HDR); -+ if (WARN_ON(!ctrl)) -+ return -EINVAL; -+ prob_updates = ctrl->p_cur.p; -+ vp9_ctx->cur.tx_mode = prob_updates->tx_mode; -+ -+ /* -+ * vp9 stuff -+ * -+ * by this point the userspace has done all parts of 6.2 uncompressed_header() -+ * except this fragment: -+ * if ( FrameIsIntra || error_resilient_mode ) { -+ * setup_past_independence ( ) -+ * if ( frame_type == KEY_FRAME || error_resilient_mode == 1 || -+ * reset_frame_context == 3 ) { -+ * for ( i = 0; i < 4; i ++ ) { -+ * save_probs( i ) -+ * } -+ * } else if ( reset_frame_context == 2 ) { -+ * save_probs( frame_context_idx ) -+ * } -+ * frame_context_idx = 0 -+ * } -+ */ -+ fctx_idx = v4l2_vp9_reset_frame_ctx(*dec_params, vp9_ctx->frame_context); -+ vp9_ctx->cur.frame_context_idx = fctx_idx; -+ -+ /* 6.1 frame(sz): load_probs() and load_probs2() */ -+ vp9_ctx->probability_tables = vp9_ctx->frame_context[fctx_idx]; -+ -+ /* -+ * The userspace has also performed 6.3 compressed_header(), but handling the -+ * probs in a special way. All probs which need updating, except MV-related, -+ * have been read from the bitstream and translated through inv_map_table[], -+ * but no 6.3.6 inv_recenter_nonneg(v, m) has been performed. The values passed -+ * by userspace are either translated values (there are no 0 values in -+ * inv_map_table[]), or zero to indicate no update. All MV-related probs which need -+ * updating have been read from the bitstream and (mv_prob << 1) | 1 has been -+ * performed. The values passed by userspace are either new values -+ * to replace old ones (the above mentioned shift and bitwise or never result in -+ * a zero) or zero to indicate no update. -+ * fw_update_probs() performs actual probs updates or leaves probs as-is -+ * for values for which a zero was passed from userspace. -+ */ -+ v4l2_vp9_fw_update_probs(&vp9_ctx->probability_tables, prob_updates, *dec_params); -+ -+ return 0; -+} -+ -+static size_t chroma_offset(const struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ int bytes_per_pixel = dec_params->bit_depth == 8 ? 1 : 2; -+ -+ return ctx->src_fmt.width * ctx->src_fmt.height * bytes_per_pixel; -+} -+ -+static size_t mv_offset(const struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ size_t cr_offset = chroma_offset(ctx, dec_params); -+ -+ return ALIGN((cr_offset * 3) / 2, G2_ALIGN); -+} -+ -+static struct hantro_decoded_buffer * -+get_ref_buf(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *dst, u64 timestamp) -+{ -+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -+ int buf_idx; -+ -+ /* -+ * If a ref is unused or invalid, address of current destination -+ * buffer is returned. -+ */ -+ buf_idx = vb2_find_timestamp(cap_q, timestamp, 0); -+ if (buf_idx < 0) -+ return vb2_to_hantro_decoded_buf(&dst->vb2_buf); -+ -+ return vb2_to_hantro_decoded_buf(vb2_get_buffer(cap_q, buf_idx)); -+} -+ -+static void update_dec_buf_info(struct hantro_decoded_buffer *buf, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ buf->vp9.width = dec_params->frame_width_minus_1 + 1; -+ buf->vp9.height = dec_params->frame_height_minus_1 + 1; -+ buf->vp9.bit_depth = dec_params->bit_depth; -+} -+ -+static void update_ctx_cur_info(struct hantro_vp9_dec_hw_ctx *vp9_ctx, -+ struct hantro_decoded_buffer *buf, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ vp9_ctx->cur.valid = true; -+ vp9_ctx->cur.reference_mode = dec_params->reference_mode; -+ vp9_ctx->cur.interpolation_filter = dec_params->interpolation_filter; -+ vp9_ctx->cur.flags = dec_params->flags; -+ vp9_ctx->cur.timestamp = buf->base.vb.vb2_buf.timestamp; -+} -+ -+static void config_output(struct hantro_ctx *ctx, -+ struct hantro_decoded_buffer *dst, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ dma_addr_t luma_addr, chroma_addr, mv_addr; -+ -+ hantro_reg_write(ctx->dev, &g2_out_dis, 0); -+ hantro_reg_write(ctx->dev, &g2_output_format, 0); -+ -+ luma_addr = vb2_dma_contig_plane_dma_addr(&dst->base.vb.vb2_buf, 0); -+ hantro_write_addr(ctx->dev, G2_OUT_LUMA_ADDR, luma_addr); -+ -+ chroma_addr = luma_addr + chroma_offset(ctx, dec_params); -+ hantro_write_addr(ctx->dev, G2_OUT_CHROMA_ADDR, chroma_addr); -+ -+ mv_addr = luma_addr + mv_offset(ctx, dec_params); -+ hantro_write_addr(ctx->dev, G2_OUT_MV_ADDR, mv_addr); -+} -+ -+struct hantro_vp9_ref_reg { -+ const struct hantro_reg width; -+ const struct hantro_reg height; -+ const struct hantro_reg hor_scale; -+ const struct hantro_reg ver_scale; -+ u32 y_base; -+ u32 c_base; -+}; -+ -+static void config_ref(struct hantro_ctx *ctx, -+ struct hantro_decoded_buffer *dst, -+ const struct hantro_vp9_ref_reg *ref_reg, -+ const struct v4l2_ctrl_vp9_frame *dec_params, -+ u64 ref_ts) -+{ -+ struct hantro_decoded_buffer *buf; -+ dma_addr_t luma_addr, chroma_addr; -+ u32 refw, refh; -+ -+ buf = get_ref_buf(ctx, &dst->base.vb, ref_ts); -+ refw = buf->vp9.width; -+ refh = buf->vp9.height; -+ -+ hantro_reg_write(ctx->dev, &ref_reg->width, refw); -+ hantro_reg_write(ctx->dev, &ref_reg->height, refh); -+ -+ hantro_reg_write(ctx->dev, &ref_reg->hor_scale, (refw << 14) / dst->vp9.width); -+ hantro_reg_write(ctx->dev, &ref_reg->ver_scale, (refh << 14) / dst->vp9.height); -+ -+ luma_addr = vb2_dma_contig_plane_dma_addr(&buf->base.vb.vb2_buf, 0); -+ hantro_write_addr(ctx->dev, ref_reg->y_base, luma_addr); -+ -+ chroma_addr = luma_addr + chroma_offset(ctx, dec_params); -+ hantro_write_addr(ctx->dev, ref_reg->c_base, chroma_addr); -+} -+ -+static void config_ref_registers(struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct hantro_decoded_buffer *dst, -+ struct hantro_decoded_buffer *mv_ref) -+{ -+ static const struct hantro_vp9_ref_reg ref_regs[] = { -+ { -+ /* Last */ -+ .width = vp9_lref_width, -+ .height = vp9_lref_height, -+ .hor_scale = vp9_lref_hor_scale, -+ .ver_scale = vp9_lref_ver_scale, -+ .y_base = G2_REF_LUMA_ADDR(0), -+ .c_base = G2_REF_CHROMA_ADDR(0), -+ }, { -+ /* Golden */ -+ .width = vp9_gref_width, -+ .height = vp9_gref_height, -+ .hor_scale = vp9_gref_hor_scale, -+ .ver_scale = vp9_gref_ver_scale, -+ .y_base = G2_REF_LUMA_ADDR(4), -+ .c_base = G2_REF_CHROMA_ADDR(4), -+ }, { -+ /* Altref */ -+ .width = vp9_aref_width, -+ .height = vp9_aref_height, -+ .hor_scale = vp9_aref_hor_scale, -+ .ver_scale = vp9_aref_ver_scale, -+ .y_base = G2_REF_LUMA_ADDR(5), -+ .c_base = G2_REF_CHROMA_ADDR(5), -+ }, -+ }; -+ dma_addr_t mv_addr; -+ -+ config_ref(ctx, dst, &ref_regs[0], dec_params, dec_params->last_frame_ts); -+ config_ref(ctx, dst, &ref_regs[1], dec_params, dec_params->golden_frame_ts); -+ config_ref(ctx, dst, &ref_regs[2], dec_params, dec_params->alt_frame_ts); -+ -+ mv_addr = vb2_dma_contig_plane_dma_addr(&mv_ref->base.vb.vb2_buf, 0) + -+ mv_offset(ctx, dec_params); -+ hantro_write_addr(ctx->dev, G2_REF_MV_ADDR(0), mv_addr); -+ -+ hantro_reg_write(ctx->dev, &vp9_last_sign_bias, -+ dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_LAST ? 1 : 0); -+ -+ hantro_reg_write(ctx->dev, &vp9_gref_sign_bias, -+ dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_GOLDEN ? 1 : 0); -+ -+ hantro_reg_write(ctx->dev, &vp9_aref_sign_bias, -+ dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_ALT ? 1 : 0); -+} -+ -+static void recompute_tile_info(unsigned short *tile_info, unsigned int tiles, unsigned int sbs) -+{ -+ int i; -+ unsigned int accumulated = 0; -+ unsigned int next_accumulated; -+ -+ for (i = 1; i <= tiles; ++i) { -+ next_accumulated = i * sbs / tiles; -+ *tile_info++ = next_accumulated - accumulated; -+ accumulated = next_accumulated; -+ } -+} -+ -+static void -+recompute_tile_rc_info(struct hantro_ctx *ctx, -+ unsigned int tile_r, unsigned int tile_c, -+ unsigned int sbs_r, unsigned int sbs_c) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ -+ recompute_tile_info(vp9_ctx->tile_r_info, tile_r, sbs_r); -+ recompute_tile_info(vp9_ctx->tile_c_info, tile_c, sbs_c); -+ -+ vp9_ctx->last_tile_r = tile_r; -+ vp9_ctx->last_tile_c = tile_c; -+ vp9_ctx->last_sbs_r = sbs_r; -+ vp9_ctx->last_sbs_c = sbs_c; -+} -+ -+static inline unsigned int first_tile_row(unsigned int tile_r, unsigned int sbs_r) -+{ -+ if (tile_r == sbs_r + 1) -+ return 1; -+ -+ if (tile_r == sbs_r + 2) -+ return 2; -+ -+ return 0; -+} -+ -+static void -+fill_tile_info(struct hantro_ctx *ctx, -+ unsigned int tile_r, unsigned int tile_c, -+ unsigned int sbs_r, unsigned int sbs_c, -+ unsigned short *tile_mem) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ unsigned int i, j; -+ bool first = true; -+ -+ for (i = first_tile_row(tile_r, sbs_r); i < tile_r; ++i) { -+ unsigned short r_info = vp9_ctx->tile_r_info[i]; -+ -+ if (first) { -+ if (i > 0) -+ r_info += vp9_ctx->tile_r_info[0]; -+ if (i == 2) -+ r_info += vp9_ctx->tile_r_info[1]; -+ first = false; -+ } -+ for (j = 0; j < tile_c; ++j) { -+ *tile_mem++ = vp9_ctx->tile_c_info[j]; -+ *tile_mem++ = r_info; -+ } -+ } -+} -+ -+static void -+config_tiles(struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct hantro_decoded_buffer *dst) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ struct hantro_aux_buf *misc = &vp9_ctx->misc; -+ struct hantro_aux_buf *tile_edge = &vp9_ctx->tile_edge; -+ dma_addr_t addr; -+ unsigned short *tile_mem; -+ -+ addr = misc->dma + vp9_ctx->tile_info_offset; -+ hantro_write_addr(ctx->dev, G2_TILE_SIZES_ADDR, addr); -+ -+ tile_mem = misc->cpu + vp9_ctx->tile_info_offset; -+ if (dec_params->tile_cols_log2 || dec_params->tile_rows_log2) { -+ unsigned int tile_r = (1 << dec_params->tile_rows_log2); -+ unsigned int tile_c = (1 << dec_params->tile_cols_log2); -+ unsigned int sbs_r = hantro_vp9_num_sbs(dst->vp9.height); -+ unsigned int sbs_c = hantro_vp9_num_sbs(dst->vp9.width); -+ -+ if (tile_r != vp9_ctx->last_tile_r || tile_c != vp9_ctx->last_tile_c || -+ sbs_r != vp9_ctx->last_sbs_r || sbs_c != vp9_ctx->last_sbs_c) -+ recompute_tile_rc_info(ctx, tile_r, tile_c, sbs_r, sbs_c); -+ -+ fill_tile_info(ctx, tile_r, tile_c, sbs_r, sbs_c, tile_mem); -+ -+ hantro_reg_write(ctx->dev, &g2_tile_e, 1); -+ hantro_reg_write(ctx->dev, &g2_num_tile_cols, tile_c); -+ hantro_reg_write(ctx->dev, &g2_num_tile_rows, tile_r); -+ -+ } else { -+ tile_mem[0] = hantro_vp9_num_sbs(dst->vp9.width); -+ tile_mem[1] = hantro_vp9_num_sbs(dst->vp9.height); -+ -+ hantro_reg_write(ctx->dev, &g2_tile_e, 0); -+ hantro_reg_write(ctx->dev, &g2_num_tile_cols, 1); -+ hantro_reg_write(ctx->dev, &g2_num_tile_rows, 1); -+ } -+ -+ /* provide aux buffers even if no tiles are used */ -+ addr = tile_edge->dma; -+ hantro_write_addr(ctx->dev, G2_TILE_FILTER_ADDR, addr); -+ -+ addr = tile_edge->dma + vp9_ctx->bsd_ctrl_offset; -+ hantro_write_addr(ctx->dev, G2_TILE_BSD_ADDR, addr); -+} -+ -+static void -+update_feat_and_flag(struct hantro_vp9_dec_hw_ctx *vp9_ctx, -+ const struct v4l2_vp9_segmentation *seg, -+ unsigned int feature, -+ unsigned int segid) -+{ -+ u8 mask = V4L2_VP9_SEGMENT_FEATURE_ENABLED(feature); -+ -+ vp9_ctx->feature_data[segid][feature] = seg->feature_data[segid][feature]; -+ vp9_ctx->feature_enabled[segid] &= ~mask; -+ vp9_ctx->feature_enabled[segid] |= (seg->feature_enabled[segid] & mask); -+} -+ -+static inline s16 clip3(s16 x, s16 y, s16 z) -+{ -+ return (z < x) ? x : (z > y) ? y : z; -+} -+ -+static s16 feat_val_clip3(s16 feat_val, s16 feature_data, bool absolute, u8 clip) -+{ -+ if (absolute) -+ return feature_data; -+ -+ return clip3(0, 255, feat_val + feature_data); -+} -+ -+static void config_segment(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ const struct v4l2_vp9_segmentation *seg; -+ s16 feat_val; -+ unsigned char feat_id; -+ unsigned int segid; -+ bool segment_enabled, absolute, update_data; -+ -+ static const struct hantro_reg seg_regs[8][V4L2_VP9_SEG_LVL_MAX] = { -+ { vp9_quant_seg0, vp9_filt_level_seg0, vp9_refpic_seg0, vp9_skip_seg0 }, -+ { vp9_quant_seg1, vp9_filt_level_seg1, vp9_refpic_seg1, vp9_skip_seg1 }, -+ { vp9_quant_seg2, vp9_filt_level_seg2, vp9_refpic_seg2, vp9_skip_seg2 }, -+ { vp9_quant_seg3, vp9_filt_level_seg3, vp9_refpic_seg3, vp9_skip_seg3 }, -+ { vp9_quant_seg4, vp9_filt_level_seg4, vp9_refpic_seg4, vp9_skip_seg4 }, -+ { vp9_quant_seg5, vp9_filt_level_seg5, vp9_refpic_seg5, vp9_skip_seg5 }, -+ { vp9_quant_seg6, vp9_filt_level_seg6, vp9_refpic_seg6, vp9_skip_seg6 }, -+ { vp9_quant_seg7, vp9_filt_level_seg7, vp9_refpic_seg7, vp9_skip_seg7 }, -+ }; -+ -+ segment_enabled = !!(dec_params->seg.flags & V4L2_VP9_SEGMENTATION_FLAG_ENABLED); -+ hantro_reg_write(ctx->dev, &vp9_segment_e, segment_enabled); -+ hantro_reg_write(ctx->dev, &vp9_segment_upd_e, -+ !!(dec_params->seg.flags & V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP)); -+ hantro_reg_write(ctx->dev, &vp9_segment_temp_upd_e, -+ !!(dec_params->seg.flags & V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE)); -+ -+ seg = &dec_params->seg; -+ absolute = !!(seg->flags & V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE); -+ update_data = !!(seg->flags & V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA); -+ -+ for (segid = 0; segid < 8; ++segid) { -+ /* Quantizer segment feature */ -+ feat_id = V4L2_VP9_SEG_LVL_ALT_Q; -+ feat_val = dec_params->quant.base_q_idx; -+ if (segment_enabled) { -+ if (update_data) -+ update_feat_and_flag(vp9_ctx, seg, feat_id, segid); -+ if (v4l2_vp9_seg_feat_enabled(vp9_ctx->feature_enabled, feat_id, segid)) -+ feat_val = feat_val_clip3(feat_val, -+ vp9_ctx->feature_data[segid][feat_id], -+ absolute, 255); -+ } -+ hantro_reg_write(ctx->dev, &seg_regs[segid][feat_id], feat_val); -+ -+ /* Loop filter segment feature */ -+ feat_id = V4L2_VP9_SEG_LVL_ALT_L; -+ feat_val = dec_params->lf.level; -+ if (segment_enabled) { -+ if (update_data) -+ update_feat_and_flag(vp9_ctx, seg, feat_id, segid); -+ if (v4l2_vp9_seg_feat_enabled(vp9_ctx->feature_enabled, feat_id, segid)) -+ feat_val = feat_val_clip3(feat_val, -+ vp9_ctx->feature_data[segid][feat_id], -+ absolute, 63); -+ } -+ hantro_reg_write(ctx->dev, &seg_regs[segid][feat_id], feat_val); -+ -+ /* Reference frame segment feature */ -+ feat_id = V4L2_VP9_SEG_LVL_REF_FRAME; -+ feat_val = 0; -+ if (segment_enabled) { -+ if (update_data) -+ update_feat_and_flag(vp9_ctx, seg, feat_id, segid); -+ if (!(dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME) && -+ v4l2_vp9_seg_feat_enabled(vp9_ctx->feature_enabled, feat_id, segid)) -+ feat_val = vp9_ctx->feature_data[segid][feat_id] + 1; -+ } -+ hantro_reg_write(ctx->dev, &seg_regs[segid][feat_id], feat_val); -+ -+ /* Skip segment feature */ -+ feat_id = V4L2_VP9_SEG_LVL_SKIP; -+ feat_val = 0; -+ if (segment_enabled) { -+ if (update_data) -+ update_feat_and_flag(vp9_ctx, seg, feat_id, segid); -+ feat_val = v4l2_vp9_seg_feat_enabled(vp9_ctx->feature_enabled, -+ feat_id, segid) ? 1 : 0; -+ } -+ hantro_reg_write(ctx->dev, &seg_regs[segid][feat_id], feat_val); -+ } -+} -+ -+static void config_loop_filter(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ bool d = dec_params->lf.flags & V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED; -+ -+ hantro_reg_write(ctx->dev, &vp9_filt_level, dec_params->lf.level); -+ hantro_reg_write(ctx->dev, &g2_out_filtering_dis, dec_params->lf.level == 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_sharpness, dec_params->lf.sharpness); -+ -+ hantro_reg_write(ctx->dev, &vp9_filt_ref_adj_0, d ? dec_params->lf.ref_deltas[0] : 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_ref_adj_1, d ? dec_params->lf.ref_deltas[1] : 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_ref_adj_2, d ? dec_params->lf.ref_deltas[2] : 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_ref_adj_3, d ? dec_params->lf.ref_deltas[3] : 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_mb_adj_0, d ? dec_params->lf.mode_deltas[0] : 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_mb_adj_1, d ? dec_params->lf.mode_deltas[1] : 0); -+} -+ -+static void config_picture_dimensions(struct hantro_ctx *ctx, struct hantro_decoded_buffer *dst) -+{ -+ u32 pic_w_4x4, pic_h_4x4; -+ -+ hantro_reg_write(ctx->dev, &g2_pic_width_in_cbs, (dst->vp9.width + 7) / 8); -+ hantro_reg_write(ctx->dev, &g2_pic_height_in_cbs, (dst->vp9.height + 7) / 8); -+ pic_w_4x4 = roundup(dst->vp9.width, 8) >> 2; -+ pic_h_4x4 = roundup(dst->vp9.height, 8) >> 2; -+ hantro_reg_write(ctx->dev, &g2_pic_width_4x4, pic_w_4x4); -+ hantro_reg_write(ctx->dev, &g2_pic_height_4x4, pic_h_4x4); -+} -+ -+static void -+config_bit_depth(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8); -+ hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8); -+} -+ -+static inline bool is_lossless(const struct v4l2_vp9_quantization *quant) -+{ -+ return quant->base_q_idx == 0 && quant->delta_q_uv_ac == 0 && -+ quant->delta_q_uv_dc == 0 && quant->delta_q_y_dc == 0; -+} -+ -+static void -+config_quant(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ hantro_reg_write(ctx->dev, &vp9_qp_delta_y_dc, dec_params->quant.delta_q_y_dc); -+ hantro_reg_write(ctx->dev, &vp9_qp_delta_ch_dc, dec_params->quant.delta_q_uv_dc); -+ hantro_reg_write(ctx->dev, &vp9_qp_delta_ch_ac, dec_params->quant.delta_q_uv_ac); -+ hantro_reg_write(ctx->dev, &vp9_lossless_e, is_lossless(&dec_params->quant)); -+} -+ -+static u32 -+hantro_interp_filter_from_v4l2(unsigned int interpolation_filter) -+{ -+ switch (interpolation_filter) { -+ case V4L2_VP9_INTERP_FILTER_EIGHTTAP: -+ return 0x1; -+ case V4L2_VP9_INTERP_FILTER_EIGHTTAP_SMOOTH: -+ return 0; -+ case V4L2_VP9_INTERP_FILTER_EIGHTTAP_SHARP: -+ return 0x2; -+ case V4L2_VP9_INTERP_FILTER_BILINEAR: -+ return 0x3; -+ case V4L2_VP9_INTERP_FILTER_SWITCHABLE: -+ return 0x4; -+ } -+ -+ return 0; -+} -+ -+static void -+config_others(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params, -+ bool intra_only, bool resolution_change) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ -+ hantro_reg_write(ctx->dev, &g2_idr_pic_e, intra_only); -+ -+ hantro_reg_write(ctx->dev, &vp9_transform_mode, vp9_ctx->cur.tx_mode); -+ -+ hantro_reg_write(ctx->dev, &vp9_mcomp_filt_type, intra_only ? -+ 0 : hantro_interp_filter_from_v4l2(dec_params->interpolation_filter)); -+ -+ hantro_reg_write(ctx->dev, &vp9_high_prec_mv_e, -+ !!(dec_params->flags & V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV)); -+ -+ hantro_reg_write(ctx->dev, &vp9_comp_pred_mode, dec_params->reference_mode); -+ -+ hantro_reg_write(ctx->dev, &g2_tempor_mvp_e, -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) && -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME) && -+ !(vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME) && -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_INTRA_ONLY) && -+ !resolution_change && -+ vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_SHOW_FRAME -+ ); -+ -+ hantro_reg_write(ctx->dev, &g2_write_mvs_e, -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME)); -+} -+ -+static void -+config_compound_reference(struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ u32 comp_fixed_ref, comp_var_ref[2]; -+ bool last_ref_frame_sign_bias; -+ bool golden_ref_frame_sign_bias; -+ bool alt_ref_frame_sign_bias; -+ bool comp_ref_allowed = 0; -+ -+ comp_fixed_ref = 0; -+ comp_var_ref[0] = 0; -+ comp_var_ref[1] = 0; -+ -+ last_ref_frame_sign_bias = dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_LAST; -+ golden_ref_frame_sign_bias = dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_GOLDEN; -+ alt_ref_frame_sign_bias = dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_ALT; -+ -+ /* 6.3.12 Frame reference mode syntax */ -+ comp_ref_allowed |= golden_ref_frame_sign_bias != last_ref_frame_sign_bias; -+ comp_ref_allowed |= alt_ref_frame_sign_bias != last_ref_frame_sign_bias; -+ -+ if (comp_ref_allowed) { -+ if (last_ref_frame_sign_bias == -+ golden_ref_frame_sign_bias) { -+ comp_fixed_ref = ALTREF_FRAME; -+ comp_var_ref[0] = LAST_FRAME; -+ comp_var_ref[1] = GOLDEN_FRAME; -+ } else if (last_ref_frame_sign_bias == -+ alt_ref_frame_sign_bias) { -+ comp_fixed_ref = GOLDEN_FRAME; -+ comp_var_ref[0] = LAST_FRAME; -+ comp_var_ref[1] = ALTREF_FRAME; -+ } else { -+ comp_fixed_ref = LAST_FRAME; -+ comp_var_ref[0] = GOLDEN_FRAME; -+ comp_var_ref[1] = ALTREF_FRAME; -+ } -+ } -+ -+ hantro_reg_write(ctx->dev, &vp9_comp_pred_fixed_ref, comp_fixed_ref); -+ hantro_reg_write(ctx->dev, &vp9_comp_pred_var_ref0, comp_var_ref[0]); -+ hantro_reg_write(ctx->dev, &vp9_comp_pred_var_ref1, comp_var_ref[1]); -+} -+ -+#define INNER_LOOP \ -+do { \ -+ for (m = 0; m < ARRAY_SIZE(adaptive->coef[0][0][0][0]); ++m) { \ -+ memcpy(adaptive->coef[i][j][k][l][m], \ -+ probs->coef[i][j][k][l][m], \ -+ sizeof(probs->coef[i][j][k][l][m])); \ -+ \ -+ adaptive->coef[i][j][k][l][m][3] = 0; \ -+ } \ -+} while (0) -+ -+static void config_probs(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ struct hantro_aux_buf *misc = &vp9_ctx->misc; -+ struct hantro_g2_all_probs *all_probs = misc->cpu; -+ struct hantro_g2_probs *adaptive; -+ struct hantro_g2_mv_probs *mv; -+ const struct v4l2_vp9_segmentation *seg = &dec_params->seg; -+ const struct v4l2_vp9_frame_context *probs = &vp9_ctx->probability_tables; -+ int i, j, k, l, m; -+ -+ for (i = 0; i < ARRAY_SIZE(all_probs->kf_y_mode_prob); ++i) -+ for (j = 0; j < ARRAY_SIZE(all_probs->kf_y_mode_prob[0]); ++j) { -+ memcpy(all_probs->kf_y_mode_prob[i][j], -+ v4l2_vp9_kf_y_mode_prob[i][j], -+ ARRAY_SIZE(all_probs->kf_y_mode_prob[i][j])); -+ -+ all_probs->kf_y_mode_prob_tail[i][j][0] = -+ v4l2_vp9_kf_y_mode_prob[i][j][8]; -+ } -+ -+ memcpy(all_probs->mb_segment_tree_probs, seg->tree_probs, -+ sizeof(all_probs->mb_segment_tree_probs)); -+ -+ memcpy(all_probs->segment_pred_probs, seg->pred_probs, -+ sizeof(all_probs->segment_pred_probs)); -+ -+ for (i = 0; i < ARRAY_SIZE(all_probs->kf_uv_mode_prob); ++i) { -+ memcpy(all_probs->kf_uv_mode_prob[i], v4l2_vp9_kf_uv_mode_prob[i], -+ ARRAY_SIZE(all_probs->kf_uv_mode_prob[i])); -+ -+ all_probs->kf_uv_mode_prob_tail[i][0] = v4l2_vp9_kf_uv_mode_prob[i][8]; -+ } -+ -+ adaptive = &all_probs->probs; -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->inter_mode); ++i) { -+ memcpy(adaptive->inter_mode[i], probs->inter_mode[i], -+ ARRAY_SIZE(probs->inter_mode[i])); -+ -+ adaptive->inter_mode[i][3] = 0; -+ } -+ -+ memcpy(adaptive->is_inter, probs->is_inter, sizeof(adaptive->is_inter)); -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->uv_mode); ++i) { -+ memcpy(adaptive->uv_mode[i], probs->uv_mode[i], -+ sizeof(adaptive->uv_mode[i])); -+ adaptive->uv_mode_tail[i][0] = probs->uv_mode[i][8]; -+ } -+ -+ memcpy(adaptive->tx8, probs->tx8, sizeof(adaptive->tx8)); -+ memcpy(adaptive->tx16, probs->tx16, sizeof(adaptive->tx16)); -+ memcpy(adaptive->tx32, probs->tx32, sizeof(adaptive->tx32)); -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->y_mode); ++i) { -+ memcpy(adaptive->y_mode[i], probs->y_mode[i], -+ ARRAY_SIZE(adaptive->y_mode[i])); -+ -+ adaptive->y_mode_tail[i][0] = probs->y_mode[i][8]; -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->partition[0]); ++i) { -+ memcpy(adaptive->partition[0][i], v4l2_vp9_kf_partition_probs[i], -+ sizeof(v4l2_vp9_kf_partition_probs[i])); -+ -+ adaptive->partition[0][i][3] = 0; -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->partition[1]); ++i) { -+ memcpy(adaptive->partition[1][i], probs->partition[i], -+ sizeof(probs->partition[i])); -+ -+ adaptive->partition[1][i][3] = 0; -+ } -+ -+ memcpy(adaptive->interp_filter, probs->interp_filter, -+ sizeof(adaptive->interp_filter)); -+ -+ memcpy(adaptive->comp_mode, probs->comp_mode, sizeof(adaptive->comp_mode)); -+ -+ memcpy(adaptive->skip, probs->skip, sizeof(adaptive->skip)); -+ -+ mv = &adaptive->mv; -+ -+ memcpy(mv->joint, probs->mv.joint, sizeof(mv->joint)); -+ memcpy(mv->sign, probs->mv.sign, sizeof(mv->sign)); -+ memcpy(mv->class0_bit, probs->mv.class0_bit, sizeof(mv->class0_bit)); -+ memcpy(mv->fr, probs->mv.fr, sizeof(mv->fr)); -+ memcpy(mv->class0_hp, probs->mv.class0_hp, sizeof(mv->class0_hp)); -+ memcpy(mv->hp, probs->mv.hp, sizeof(mv->hp)); -+ memcpy(mv->classes, probs->mv.classes, sizeof(mv->classes)); -+ memcpy(mv->class0_fr, probs->mv.class0_fr, sizeof(mv->class0_fr)); -+ memcpy(mv->bits, probs->mv.bits, sizeof(mv->bits)); -+ -+ memcpy(adaptive->single_ref, probs->single_ref, sizeof(adaptive->single_ref)); -+ -+ memcpy(adaptive->comp_ref, probs->comp_ref, sizeof(adaptive->comp_ref)); -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->coef); ++i) -+ for (j = 0; j < ARRAY_SIZE(adaptive->coef[0]); ++j) -+ for (k = 0; k < ARRAY_SIZE(adaptive->coef[0][0]); ++k) -+ for (l = 0; l < ARRAY_SIZE(adaptive->coef[0][0][0]); ++l) -+ INNER_LOOP; -+ -+ hantro_write_addr(ctx->dev, G2_VP9_PROBS_ADDR, misc->dma); -+} -+ -+static void config_counts(struct hantro_ctx *ctx) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_dec = &ctx->vp9_dec; -+ struct hantro_aux_buf *misc = &vp9_dec->misc; -+ dma_addr_t addr = misc->dma + vp9_dec->ctx_counters_offset; -+ -+ hantro_write_addr(ctx->dev, G2_VP9_CTX_COUNT_ADDR, addr); -+} -+ -+static void config_seg_map(struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params, -+ bool intra_only, bool update_map) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ struct hantro_aux_buf *segment_map = &vp9_ctx->segment_map; -+ dma_addr_t addr; -+ -+ if (intra_only || -+ (dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT)) { -+ memset(segment_map->cpu, 0, segment_map->size); -+ memset(vp9_ctx->feature_data, 0, sizeof(vp9_ctx->feature_data)); -+ memset(vp9_ctx->feature_enabled, 0, sizeof(vp9_ctx->feature_enabled)); -+ } -+ -+ addr = segment_map->dma + vp9_ctx->active_segment * vp9_ctx->segment_map_size; -+ hantro_write_addr(ctx->dev, G2_VP9_SEGMENT_READ_ADDR, addr); -+ -+ addr = segment_map->dma + (1 - vp9_ctx->active_segment) * vp9_ctx->segment_map_size; -+ hantro_write_addr(ctx->dev, G2_VP9_SEGMENT_WRITE_ADDR, addr); -+ -+ if (update_map) -+ vp9_ctx->active_segment = 1 - vp9_ctx->active_segment; -+} -+ -+static void -+config_source(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct vb2_v4l2_buffer *vb2_src) -+{ -+ dma_addr_t stream_base, tmp_addr; -+ unsigned int headres_size; -+ u32 src_len, start_bit, src_buf_len; -+ -+ headres_size = dec_params->uncompressed_header_size -+ + dec_params->compressed_header_size; -+ -+ stream_base = vb2_dma_contig_plane_dma_addr(&vb2_src->vb2_buf, 0); -+ hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base); -+ -+ tmp_addr = stream_base + headres_size; -+ start_bit = (tmp_addr & 0xf) * 8; -+ hantro_reg_write(ctx->dev, &g2_start_bit, start_bit); -+ -+ src_len = vb2_get_plane_payload(&vb2_src->vb2_buf, 0); -+ src_len += start_bit / 8 - headres_size; -+ hantro_reg_write(ctx->dev, &g2_stream_len, src_len); -+ -+ tmp_addr &= ~0xf; -+ hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base); -+ src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0); -+ hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len); -+} -+ -+static void -+config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct vb2_v4l2_buffer *vb2_src, struct vb2_v4l2_buffer *vb2_dst) -+{ -+ struct hantro_decoded_buffer *dst, *last, *mv_ref; -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ const struct v4l2_vp9_segmentation *seg; -+ bool intra_only, resolution_change; -+ -+ /* vp9 stuff */ -+ dst = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf); -+ -+ if (vp9_ctx->last.valid) -+ last = get_ref_buf(ctx, &dst->base.vb, vp9_ctx->last.timestamp); -+ else -+ last = dst; -+ -+ update_dec_buf_info(dst, dec_params); -+ update_ctx_cur_info(vp9_ctx, dst, dec_params); -+ seg = &dec_params->seg; -+ -+ intra_only = !!(dec_params->flags & -+ (V4L2_VP9_FRAME_FLAG_KEY_FRAME | -+ V4L2_VP9_FRAME_FLAG_INTRA_ONLY)); -+ -+ if (!intra_only && -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) && -+ vp9_ctx->last.valid) -+ mv_ref = last; -+ else -+ mv_ref = dst; -+ -+ resolution_change = dst->vp9.width != last->vp9.width || -+ dst->vp9.height != last->vp9.height; -+ -+ /* configure basic registers */ -+ hantro_reg_write(ctx->dev, &g2_mode, VP9_DEC_MODE); -+ hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf); -+ hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf); -+ hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf); -+ hantro_reg_write(ctx->dev, &g2_buswidth, BUS_WIDTH_128); -+ hantro_reg_write(ctx->dev, &g2_max_burst, 16); -+ hantro_reg_write(ctx->dev, &g2_apf_threshold, 8); -+ hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1); -+ hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1); -+ hantro_reg_write(ctx->dev, &g2_max_cb_size, 6); -+ hantro_reg_write(ctx->dev, &g2_min_cb_size, 3); -+ -+ config_output(ctx, dst, dec_params); -+ -+ if (!intra_only) -+ config_ref_registers(ctx, dec_params, dst, mv_ref); -+ -+ config_tiles(ctx, dec_params, dst); -+ config_segment(ctx, dec_params); -+ config_loop_filter(ctx, dec_params); -+ config_picture_dimensions(ctx, dst); -+ config_bit_depth(ctx, dec_params); -+ config_quant(ctx, dec_params); -+ config_others(ctx, dec_params, intra_only, resolution_change); -+ config_compound_reference(ctx, dec_params); -+ config_probs(ctx, dec_params); -+ config_counts(ctx); -+ config_seg_map(ctx, dec_params, intra_only, -+ seg->flags & V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP); -+ config_source(ctx, dec_params, vb2_src); -+} -+ -+int hantro_g2_vp9_dec_run(struct hantro_ctx *ctx) -+{ -+ const struct v4l2_ctrl_vp9_frame *decode_params; -+ struct vb2_v4l2_buffer *src; -+ struct vb2_v4l2_buffer *dst; -+ int ret; -+ -+ hantro_g2_check_idle(ctx->dev); -+ -+ ret = start_prepare_run(ctx, &decode_params); -+ if (ret) { -+ hantro_end_prepare_run(ctx); -+ return ret; -+ } -+ -+ src = hantro_get_src_buf(ctx); -+ dst = hantro_get_dst_buf(ctx); -+ -+ config_registers(ctx, decode_params, src, dst); -+ -+ hantro_end_prepare_run(ctx); -+ -+ vdpu_write(ctx->dev, G2_REG_INTERRUPT_DEC_E, G2_REG_INTERRUPT); -+ -+ return 0; -+} -+ -+#define copy_tx_and_skip(p1, p2) \ -+do { \ -+ memcpy((p1)->tx8, (p2)->tx8, sizeof((p1)->tx8)); \ -+ memcpy((p1)->tx16, (p2)->tx16, sizeof((p1)->tx16)); \ -+ memcpy((p1)->tx32, (p2)->tx32, sizeof((p1)->tx32)); \ -+ memcpy((p1)->skip, (p2)->skip, sizeof((p1)->skip)); \ -+} while (0) -+ -+void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ unsigned int fctx_idx; -+ -+ if (!(vp9_ctx->cur.flags & V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX)) -+ goto out_update_last; -+ -+ fctx_idx = vp9_ctx->cur.frame_context_idx; -+ -+ if (!(vp9_ctx->cur.flags & V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE)) { -+ /* error_resilient_mode == 0 && frame_parallel_decoding_mode == 0 */ -+ struct v4l2_vp9_frame_context *probs = &vp9_ctx->probability_tables; -+ bool frame_is_intra = vp9_ctx->cur.flags & -+ (V4L2_VP9_FRAME_FLAG_KEY_FRAME | V4L2_VP9_FRAME_FLAG_INTRA_ONLY); -+ struct tx_and_skip { -+ u8 tx8[2][1]; -+ u8 tx16[2][2]; -+ u8 tx32[2][3]; -+ u8 skip[3]; -+ } _tx_skip, *tx_skip = &_tx_skip; -+ struct v4l2_vp9_frame_symbol_counts *counts; -+ struct symbol_counts *hantro_cnts; -+ u32 tx16p[2][4]; -+ int i; -+ -+ /* buffer the forward-updated TX and skip probs */ -+ if (frame_is_intra) -+ copy_tx_and_skip(tx_skip, probs); -+ -+ /* 6.1.2 refresh_probs(): load_probs() and load_probs2() */ -+ *probs = vp9_ctx->frame_context[fctx_idx]; -+ -+ /* if FrameIsIntra then undo the effect of load_probs2() */ -+ if (frame_is_intra) -+ copy_tx_and_skip(probs, tx_skip); -+ -+ counts = &vp9_ctx->cnts; -+ hantro_cnts = vp9_ctx->misc.cpu + vp9_ctx->ctx_counters_offset; -+ for (i = 0; i < ARRAY_SIZE(tx16p); ++i) { -+ memcpy(tx16p[i], -+ hantro_cnts->tx16x16_count[i], -+ sizeof(hantro_cnts->tx16x16_count[0])); -+ tx16p[i][3] = 0; -+ } -+ counts->tx16p = &tx16p; -+ -+ v4l2_vp9_adapt_coef_probs(probs, counts, -+ !vp9_ctx->last.valid || -+ vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME, -+ frame_is_intra); -+ -+ if (!frame_is_intra) { -+ /* load_probs2() already done */ -+ u32 mv_mode[7][4]; -+ -+ for (i = 0; i < ARRAY_SIZE(mv_mode); ++i) { -+ mv_mode[i][0] = hantro_cnts->inter_mode_counts[i][1][0]; -+ mv_mode[i][1] = hantro_cnts->inter_mode_counts[i][2][0]; -+ mv_mode[i][2] = hantro_cnts->inter_mode_counts[i][0][0]; -+ mv_mode[i][3] = hantro_cnts->inter_mode_counts[i][2][1]; -+ } -+ counts->mv_mode = &mv_mode; -+ v4l2_vp9_adapt_noncoef_probs(&vp9_ctx->probability_tables, counts, -+ vp9_ctx->cur.reference_mode, -+ vp9_ctx->cur.interpolation_filter, -+ vp9_ctx->cur.tx_mode, vp9_ctx->cur.flags); -+ } -+ } -+ -+ vp9_ctx->frame_context[fctx_idx] = vp9_ctx->probability_tables; -+ -+out_update_last: -+ vp9_ctx->last = vp9_ctx->cur; -+} -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index 1d869abf90b2..fe5b51046d33 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - #include - - #define DEC_8190_ALIGN_MASK 0x07U -@@ -165,6 +166,82 @@ struct hantro_vp8_dec_hw_ctx { - struct hantro_aux_buf prob_tbl; - }; - -+/** -+ * struct hantro_vp9_frame_info -+ * -+ * @valid: frame info valid flag -+ * @frame_context_idx: index of frame context -+ * @reference_mode: inter prediction type -+ * @tx_mode: transform mode -+ * @interpolation_filter: filter selection for inter prediction -+ * @flags: frame flags -+ * @timestamp: frame timestamp -+ */ -+struct hantro_vp9_frame_info { -+ u32 valid : 1; -+ u32 frame_context_idx : 2; -+ u32 reference_mode : 2; -+ u32 tx_mode : 3; -+ u32 interpolation_filter : 3; -+ u32 flags; -+ u64 timestamp; -+}; -+ -+#define MAX_SB_COLS 64 -+#define MAX_SB_ROWS 34 -+ -+/** -+ * struct hantro_vp9_dec_hw_ctx -+ * -+ * @tile_edge: auxiliary DMA buffer for tile edge processing -+ * @segment_map: auxiliary DMA buffer for segment map -+ * @misc: auxiliary DMA buffer for tile info, probabilities and hw counters -+ * @cnts: vp9 library struct for abstracting hw counters access -+ * @probability_tables: VP9 probability tables implied by the spec -+ * @frame_context: VP9 frame contexts -+ * @cur: current frame information -+ * @last: last frame information -+ * @bsd_ctrl_offset: bsd offset into tile_edge -+ * @segment_map_size: size of segment map -+ * @ctx_counters_offset: hw counters offset into misc -+ * @tile_info_offset: tile info offset into misc -+ * @tile_r_info: per-tile information array -+ * @tile_c_info: per-tile information array -+ * @last_tile_r: last number of tile rows -+ * @last_tile_c: last number of tile cols -+ * @last_sbs_r: last number of superblock rows -+ * @last_sbs_c: last number of superblock cols -+ * @active_segment: number of active segment (alternating between 0 and 1) -+ * @feature_enabled: segmentation feature enabled flags -+ * @feature_data: segmentation feature data -+ */ -+struct hantro_vp9_dec_hw_ctx { -+ struct hantro_aux_buf tile_edge; -+ struct hantro_aux_buf segment_map; -+ struct hantro_aux_buf misc; -+ struct v4l2_vp9_frame_symbol_counts cnts; -+ struct v4l2_vp9_frame_context probability_tables; -+ struct v4l2_vp9_frame_context frame_context[4]; -+ struct hantro_vp9_frame_info cur; -+ struct hantro_vp9_frame_info last; -+ -+ unsigned int bsd_ctrl_offset; -+ unsigned int segment_map_size; -+ unsigned int ctx_counters_offset; -+ unsigned int tile_info_offset; -+ -+ unsigned short tile_r_info[MAX_SB_ROWS]; -+ unsigned short tile_c_info[MAX_SB_COLS]; -+ unsigned int last_tile_r; -+ unsigned int last_tile_c; -+ unsigned int last_sbs_r; -+ unsigned int last_sbs_c; -+ -+ unsigned int active_segment; -+ u8 feature_enabled[8]; -+ s16 feature_data[8][4]; -+}; -+ - /** - * struct hantro_postproc_ctx - * -@@ -271,6 +348,24 @@ void hantro_hevc_ref_remove_unused(struct hantro_ctx *ctx); - size_t hantro_hevc_chroma_offset(const struct v4l2_ctrl_hevc_sps *sps); - size_t hantro_hevc_motion_vectors_offset(const struct v4l2_ctrl_hevc_sps *sps); - -+static inline unsigned short hantro_vp9_num_sbs(unsigned short dimension) -+{ -+ return (dimension + 63) / 64; -+} -+ -+static inline size_t -+hantro_vp9_mv_size(unsigned int width, unsigned int height) -+{ -+ int num_ctbs; -+ -+ /* -+ * There can be up to (CTBs x 64) number of blocks, -+ * and the motion vector for each block needs 16 bytes. -+ */ -+ num_ctbs = hantro_vp9_num_sbs(width) * hantro_vp9_num_sbs(height); -+ return (num_ctbs * 64) * 16; -+} -+ - static inline size_t - hantro_h264_mv_size(unsigned int width, unsigned int height) - { -@@ -312,6 +407,10 @@ void hantro_vp8_dec_exit(struct hantro_ctx *ctx); - void hantro_vp8_prob_update(struct hantro_ctx *ctx, - const struct v4l2_ctrl_vp8_frame *hdr); - -+int hantro_g2_vp9_dec_run(struct hantro_ctx *ctx); -+void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx); -+int hantro_vp9_dec_init(struct hantro_ctx *ctx); -+void hantro_vp9_dec_exit(struct hantro_ctx *ctx); - void hantro_g2_check_idle(struct hantro_dev *vpu); - - #endif /* HANTRO_HW_H_ */ -diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c -index d1f060c55fed..e4b0645ba6fc 100644 ---- a/drivers/staging/media/hantro/hantro_v4l2.c -+++ b/drivers/staging/media/hantro/hantro_v4l2.c -@@ -299,6 +299,11 @@ static int hantro_try_fmt(const struct hantro_ctx *ctx, - pix_mp->plane_fmt[0].sizeimage += - hantro_h264_mv_size(pix_mp->width, - pix_mp->height); -+ else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME && -+ !hantro_needs_postproc(ctx, fmt)) -+ pix_mp->plane_fmt[0].sizeimage += -+ hantro_vp9_mv_size(pix_mp->width, -+ pix_mp->height); - } else if (!pix_mp->plane_fmt[0].sizeimage) { - /* - * For coded formats the application can specify -@@ -407,6 +412,7 @@ hantro_update_requires_request(struct hantro_ctx *ctx, u32 fourcc) - case V4L2_PIX_FMT_VP8_FRAME: - case V4L2_PIX_FMT_H264_SLICE: - case V4L2_PIX_FMT_HEVC_SLICE: -+ case V4L2_PIX_FMT_VP9_FRAME: - ctx->fh.m2m_ctx->out_q_ctx.q.requires_requests = true; - break; - default: -diff --git a/drivers/staging/media/hantro/hantro_vp9.c b/drivers/staging/media/hantro/hantro_vp9.c -new file mode 100644 -index 000000000000..566cd376c097 ---- /dev/null -+++ b/drivers/staging/media/hantro/hantro_vp9.c -@@ -0,0 +1,240 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Hantro VP9 codec driver -+ * -+ * Copyright (C) 2021 Collabora Ltd. -+ */ -+ -+#include -+#include -+ -+#include "hantro.h" -+#include "hantro_hw.h" -+#include "hantro_vp9.h" -+ -+#define POW2(x) (1 << (x)) -+ -+#define MAX_LOG2_TILE_COLUMNS 6 -+#define MAX_NUM_TILE_COLS POW2(MAX_LOG2_TILE_COLUMNS) -+#define MAX_TILE_COLS 20 -+#define MAX_TILE_ROWS 22 -+ -+static size_t hantro_vp9_tile_filter_size(unsigned int height) -+{ -+ u32 h, height32, size; -+ -+ h = roundup(height, 8); -+ -+ height32 = roundup(h, 64); -+ size = 24 * height32 * (MAX_NUM_TILE_COLS - 1); /* luma: 8, chroma: 8 + 8 */ -+ -+ return size; -+} -+ -+static size_t hantro_vp9_bsd_control_size(unsigned int height) -+{ -+ u32 h, height32; -+ -+ h = roundup(height, 8); -+ height32 = roundup(h, 64); -+ -+ return 16 * (height32 / 4) * (MAX_NUM_TILE_COLS - 1); -+} -+ -+static size_t hantro_vp9_segment_map_size(unsigned int width, unsigned int height) -+{ -+ u32 w, h; -+ int num_ctbs; -+ -+ w = roundup(width, 8); -+ h = roundup(height, 8); -+ num_ctbs = ((w + 63) / 64) * ((h + 63) / 64); -+ -+ return num_ctbs * 32; -+} -+ -+static inline size_t hantro_vp9_prob_tab_size(void) -+{ -+ return roundup(sizeof(struct hantro_g2_all_probs), 16); -+} -+ -+static inline size_t hantro_vp9_count_tab_size(void) -+{ -+ return roundup(sizeof(struct symbol_counts), 16); -+} -+ -+static inline size_t hantro_vp9_tile_info_size(void) -+{ -+ return roundup((MAX_TILE_COLS * MAX_TILE_ROWS * 4 * sizeof(u16) + 15 + 16) & ~0xf, 16); -+} -+ -+static void *get_coeffs_arr(struct symbol_counts *cnts, int i, int j, int k, int l, int m) -+{ -+ if (i == 0) -+ return &cnts->count_coeffs[j][k][l][m]; -+ -+ if (i == 1) -+ return &cnts->count_coeffs8x8[j][k][l][m]; -+ -+ if (i == 2) -+ return &cnts->count_coeffs16x16[j][k][l][m]; -+ -+ if (i == 3) -+ return &cnts->count_coeffs32x32[j][k][l][m]; -+ -+ return NULL; -+} -+ -+static void *get_eobs1(struct symbol_counts *cnts, int i, int j, int k, int l, int m) -+{ -+ if (i == 0) -+ return &cnts->count_coeffs[j][k][l][m][3]; -+ -+ if (i == 1) -+ return &cnts->count_coeffs8x8[j][k][l][m][3]; -+ -+ if (i == 2) -+ return &cnts->count_coeffs16x16[j][k][l][m][3]; -+ -+ if (i == 3) -+ return &cnts->count_coeffs32x32[j][k][l][m][3]; -+ -+ return NULL; -+} -+ -+#define INNER_LOOP \ -+ do { \ -+ for (m = 0; m < ARRAY_SIZE(vp9_ctx->cnts.coeff[i][0][0][0]); ++m) { \ -+ vp9_ctx->cnts.coeff[i][j][k][l][m] = \ -+ get_coeffs_arr(cnts, i, j, k, l, m); \ -+ vp9_ctx->cnts.eob[i][j][k][l][m][0] = \ -+ &cnts->count_eobs[i][j][k][l][m]; \ -+ vp9_ctx->cnts.eob[i][j][k][l][m][1] = \ -+ get_eobs1(cnts, i, j, k, l, m); \ -+ } \ -+ } while (0) -+ -+static void init_v4l2_vp9_count_tbl(struct hantro_ctx *ctx) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ struct symbol_counts *cnts = vp9_ctx->misc.cpu + vp9_ctx->ctx_counters_offset; -+ int i, j, k, l, m; -+ -+ vp9_ctx->cnts.partition = &cnts->partition_counts; -+ vp9_ctx->cnts.skip = &cnts->mbskip_count; -+ vp9_ctx->cnts.intra_inter = &cnts->intra_inter_count; -+ vp9_ctx->cnts.tx32p = &cnts->tx32x32_count; -+ /* -+ * g2 hardware uses tx16x16_count[2][3], while the api -+ * expects tx16p[2][4], so this must be explicitly copied -+ * into vp9_ctx->cnts.tx16p when passing the data to the -+ * vp9 library function -+ */ -+ vp9_ctx->cnts.tx8p = &cnts->tx8x8_count; -+ -+ vp9_ctx->cnts.y_mode = &cnts->sb_ymode_counts; -+ vp9_ctx->cnts.uv_mode = &cnts->uv_mode_counts; -+ vp9_ctx->cnts.comp = &cnts->comp_inter_count; -+ vp9_ctx->cnts.comp_ref = &cnts->comp_ref_count; -+ vp9_ctx->cnts.single_ref = &cnts->single_ref_count; -+ vp9_ctx->cnts.filter = &cnts->switchable_interp_counts; -+ vp9_ctx->cnts.mv_joint = &cnts->mv_counts.joints; -+ vp9_ctx->cnts.sign = &cnts->mv_counts.sign; -+ vp9_ctx->cnts.classes = &cnts->mv_counts.classes; -+ vp9_ctx->cnts.class0 = &cnts->mv_counts.class0; -+ vp9_ctx->cnts.bits = &cnts->mv_counts.bits; -+ vp9_ctx->cnts.class0_fp = &cnts->mv_counts.class0_fp; -+ vp9_ctx->cnts.fp = &cnts->mv_counts.fp; -+ vp9_ctx->cnts.class0_hp = &cnts->mv_counts.class0_hp; -+ vp9_ctx->cnts.hp = &cnts->mv_counts.hp; -+ -+ for (i = 0; i < ARRAY_SIZE(vp9_ctx->cnts.coeff); ++i) -+ for (j = 0; j < ARRAY_SIZE(vp9_ctx->cnts.coeff[i]); ++j) -+ for (k = 0; k < ARRAY_SIZE(vp9_ctx->cnts.coeff[i][0]); ++k) -+ for (l = 0; l < ARRAY_SIZE(vp9_ctx->cnts.coeff[i][0][0]); ++l) -+ INNER_LOOP; -+} -+ -+int hantro_vp9_dec_init(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ const struct hantro_variant *variant = vpu->variant; -+ struct hantro_vp9_dec_hw_ctx *vp9_dec = &ctx->vp9_dec; -+ struct hantro_aux_buf *tile_edge = &vp9_dec->tile_edge; -+ struct hantro_aux_buf *segment_map = &vp9_dec->segment_map; -+ struct hantro_aux_buf *misc = &vp9_dec->misc; -+ u32 i, max_width, max_height, size; -+ -+ if (variant->num_dec_fmts < 1) -+ return -EINVAL; -+ -+ for (i = 0; i < variant->num_dec_fmts; ++i) -+ if (variant->dec_fmts[i].fourcc == V4L2_PIX_FMT_VP9_FRAME) -+ break; -+ -+ if (i == variant->num_dec_fmts) -+ return -EINVAL; -+ -+ max_width = vpu->variant->dec_fmts[i].frmsize.max_width; -+ max_height = vpu->variant->dec_fmts[i].frmsize.max_height; -+ -+ size = hantro_vp9_tile_filter_size(max_height); -+ vp9_dec->bsd_ctrl_offset = size; -+ size += hantro_vp9_bsd_control_size(max_height); -+ -+ tile_edge->cpu = dma_alloc_coherent(vpu->dev, size, &tile_edge->dma, GFP_KERNEL); -+ if (!tile_edge->cpu) -+ return -ENOMEM; -+ -+ tile_edge->size = size; -+ memset(tile_edge->cpu, 0, size); -+ -+ size = hantro_vp9_segment_map_size(max_width, max_height); -+ vp9_dec->segment_map_size = size; -+ size *= 2; /* we need two areas of this size, used alternately */ -+ -+ segment_map->cpu = dma_alloc_coherent(vpu->dev, size, &segment_map->dma, GFP_KERNEL); -+ if (!segment_map->cpu) -+ goto err_segment_map; -+ -+ segment_map->size = size; -+ memset(segment_map->cpu, 0, size); -+ -+ size = hantro_vp9_prob_tab_size(); -+ vp9_dec->ctx_counters_offset = size; -+ size += hantro_vp9_count_tab_size(); -+ vp9_dec->tile_info_offset = size; -+ size += hantro_vp9_tile_info_size(); -+ -+ misc->cpu = dma_alloc_coherent(vpu->dev, size, &misc->dma, GFP_KERNEL); -+ if (!misc->cpu) -+ goto err_misc; -+ -+ misc->size = size; -+ memset(misc->cpu, 0, size); -+ -+ init_v4l2_vp9_count_tbl(ctx); -+ -+ return 0; -+ -+err_misc: -+ dma_free_coherent(vpu->dev, segment_map->size, segment_map->cpu, segment_map->dma); -+ -+err_segment_map: -+ dma_free_coherent(vpu->dev, tile_edge->size, tile_edge->cpu, tile_edge->dma); -+ -+ return -ENOMEM; -+} -+ -+void hantro_vp9_dec_exit(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ struct hantro_vp9_dec_hw_ctx *vp9_dec = &ctx->vp9_dec; -+ struct hantro_aux_buf *tile_edge = &vp9_dec->tile_edge; -+ struct hantro_aux_buf *segment_map = &vp9_dec->segment_map; -+ struct hantro_aux_buf *misc = &vp9_dec->misc; -+ -+ dma_free_coherent(vpu->dev, misc->size, misc->cpu, misc->dma); -+ dma_free_coherent(vpu->dev, segment_map->size, segment_map->cpu, segment_map->dma); -+ dma_free_coherent(vpu->dev, tile_edge->size, tile_edge->cpu, tile_edge->dma); -+} -diff --git a/drivers/staging/media/hantro/hantro_vp9.h b/drivers/staging/media/hantro/hantro_vp9.h -new file mode 100644 -index 000000000000..26b69275f098 ---- /dev/null -+++ b/drivers/staging/media/hantro/hantro_vp9.h -@@ -0,0 +1,102 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Hantro VP9 codec driver -+ * -+ * Copyright (C) 2021 Collabora Ltd. -+ */ -+ -+struct hantro_g2_mv_probs { -+ u8 joint[3]; -+ u8 sign[2]; -+ u8 class0_bit[2][1]; -+ u8 fr[2][3]; -+ u8 class0_hp[2]; -+ u8 hp[2]; -+ u8 classes[2][10]; -+ u8 class0_fr[2][2][3]; -+ u8 bits[2][10]; -+}; -+ -+struct hantro_g2_probs { -+ u8 inter_mode[7][4]; -+ u8 is_inter[4]; -+ u8 uv_mode[10][8]; -+ u8 tx8[2][1]; -+ u8 tx16[2][2]; -+ u8 tx32[2][3]; -+ u8 y_mode_tail[4][1]; -+ u8 y_mode[4][8]; -+ u8 partition[2][16][4]; /* [keyframe][][], [inter][][] */ -+ u8 uv_mode_tail[10][1]; -+ u8 interp_filter[4][2]; -+ u8 comp_mode[5]; -+ u8 skip[3]; -+ -+ u8 pad1[1]; -+ -+ struct hantro_g2_mv_probs mv; -+ -+ u8 single_ref[5][2]; -+ u8 comp_ref[5]; -+ -+ u8 pad2[17]; -+ -+ u8 coef[4][2][2][6][6][4]; -+}; -+ -+struct hantro_g2_all_probs { -+ u8 kf_y_mode_prob[10][10][8]; -+ -+ u8 kf_y_mode_prob_tail[10][10][1]; -+ u8 ref_pred_probs[3]; -+ u8 mb_segment_tree_probs[7]; -+ u8 segment_pred_probs[3]; -+ u8 ref_scores[4]; -+ u8 prob_comppred[2]; -+ -+ u8 pad1[9]; -+ -+ u8 kf_uv_mode_prob[10][8]; -+ u8 kf_uv_mode_prob_tail[10][1]; -+ -+ u8 pad2[6]; -+ -+ struct hantro_g2_probs probs; -+}; -+ -+struct mv_counts { -+ u32 joints[4]; -+ u32 sign[2][2]; -+ u32 classes[2][11]; -+ u32 class0[2][2]; -+ u32 bits[2][10][2]; -+ u32 class0_fp[2][2][4]; -+ u32 fp[2][4]; -+ u32 class0_hp[2][2]; -+ u32 hp[2][2]; -+}; -+ -+struct symbol_counts { -+ u32 inter_mode_counts[7][3][2]; -+ u32 sb_ymode_counts[4][10]; -+ u32 uv_mode_counts[10][10]; -+ u32 partition_counts[16][4]; -+ u32 switchable_interp_counts[4][3]; -+ u32 intra_inter_count[4][2]; -+ u32 comp_inter_count[5][2]; -+ u32 single_ref_count[5][2][2]; -+ u32 comp_ref_count[5][2]; -+ u32 tx32x32_count[2][4]; -+ u32 tx16x16_count[2][3]; -+ u32 tx8x8_count[2][2]; -+ u32 mbskip_count[3][2]; -+ -+ struct mv_counts mv_counts; -+ -+ u32 count_coeffs[2][2][6][6][4]; -+ u32 count_coeffs8x8[2][2][6][6][4]; -+ u32 count_coeffs16x16[2][2][6][6][4]; -+ u32 count_coeffs32x32[2][2][6][6][4]; -+ -+ u32 count_eobs[4][2][2][6][6]; -+}; -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index a40b161e5956..455a107ffb02 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -150,6 +150,19 @@ static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = { - .step_height = MB_DIM, - }, - }, -+ { -+ .fourcc = V4L2_PIX_FMT_VP9_FRAME, -+ .codec_mode = HANTRO_MODE_VP9_DEC, -+ .max_depth = 2, -+ .frmsize = { -+ .min_width = 48, -+ .max_width = 3840, -+ .step_width = MB_DIM, -+ .min_height = 48, -+ .max_height = 2160, -+ .step_height = MB_DIM, -+ }, -+ }, - }; - - static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id) -@@ -241,6 +254,13 @@ static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = { - .init = hantro_hevc_dec_init, - .exit = hantro_hevc_dec_exit, - }, -+ [HANTRO_MODE_VP9_DEC] = { -+ .run = hantro_g2_vp9_dec_run, -+ .done = hantro_g2_vp9_dec_done, -+ .reset = imx8m_vpu_g2_reset, -+ .init = hantro_vp9_dec_init, -+ .exit = hantro_vp9_dec_exit, -+ }, - }; - - /* -@@ -281,7 +301,7 @@ const struct hantro_variant imx8mq_vpu_g2_variant = { - .dec_offset = 0x0, - .dec_fmts = imx8m_vpu_g2_dec_fmts, - .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_g2_dec_fmts), -- .codec = HANTRO_HEVC_DECODER, -+ .codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER, - .codec_ops = imx8mq_vpu_g2_codec_ops, - .init = imx8mq_vpu_hw_init, - .runtime_resume = imx8mq_runtime_resume, diff --git a/projects/NXP/devices/iMX8/patches/linux/0077-media-hantro-Staticize-a-struct-in-postprocessor-cod.patch b/projects/NXP/devices/iMX8/patches/linux/0077-media-hantro-Staticize-a-struct-in-postprocessor-cod.patch deleted file mode 100644 index b4c6db8cca..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0077-media-hantro-Staticize-a-struct-in-postprocessor-cod.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:41 +0100 -Subject: [PATCH] media: hantro: Staticize a struct in postprocessor code - -The struct is not used outside this file, so it can be static. - -Signed-off-by: Andrzej Pietrasiewicz -Reviewed-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/hantro_postproc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index 4549aec08feb..89de43021779 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -33,7 +33,7 @@ - #define VPU_PP_OUT_RGB 0x0 - #define VPU_PP_OUT_YUYV 0x3 - --const struct hantro_postproc_regs hantro_g1_postproc_regs = { -+static const struct hantro_postproc_regs hantro_g1_postproc_regs = { - .pipeline_en = {G1_REG_PP_INTERRUPT, 1, 0x1}, - .max_burst = {G1_REG_PP_DEV_CONFIG, 0, 0x1f}, - .clk_gate = {G1_REG_PP_DEV_CONFIG, 1, 0x1}, diff --git a/projects/NXP/devices/iMX8/patches/linux/0078-media-hantro-Support-NV12-on-the-G2-core.patch b/projects/NXP/devices/iMX8/patches/linux/0078-media-hantro-Support-NV12-on-the-G2-core.patch deleted file mode 100644 index 9c7fc3930f..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0078-media-hantro-Support-NV12-on-the-G2-core.patch +++ /dev/null @@ -1,161 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:42 +0100 -Subject: [PATCH] media: hantro: Support NV12 on the G2 core - -The G2 decoder block produces NV12 4x4 tiled format (NV12_4L4). -Enable the G2 post-processor block, in order to produce regular NV12. - -The logic in hantro_postproc.c is leveraged to take care of allocating -the extra buffers and configure the post-processor, which is -significantly simpler than the one on the G1. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Hans Verkuil ---- - .../staging/media/hantro/hantro_g2_vp9_dec.c | 6 ++-- - drivers/staging/media/hantro/hantro_hw.h | 1 + - .../staging/media/hantro/hantro_postproc.c | 31 +++++++++++++++++++ - drivers/staging/media/hantro/imx8m_vpu_hw.c | 11 +++++++ - 4 files changed, 46 insertions(+), 3 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -index fc55b03a8004..e04242d10fa2 100644 ---- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -@@ -152,7 +152,7 @@ static void config_output(struct hantro_ctx *ctx, - hantro_reg_write(ctx->dev, &g2_out_dis, 0); - hantro_reg_write(ctx->dev, &g2_output_format, 0); - -- luma_addr = vb2_dma_contig_plane_dma_addr(&dst->base.vb.vb2_buf, 0); -+ luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf); - hantro_write_addr(ctx->dev, G2_OUT_LUMA_ADDR, luma_addr); - - chroma_addr = luma_addr + chroma_offset(ctx, dec_params); -@@ -191,7 +191,7 @@ static void config_ref(struct hantro_ctx *ctx, - hantro_reg_write(ctx->dev, &ref_reg->hor_scale, (refw << 14) / dst->vp9.width); - hantro_reg_write(ctx->dev, &ref_reg->ver_scale, (refh << 14) / dst->vp9.height); - -- luma_addr = vb2_dma_contig_plane_dma_addr(&buf->base.vb.vb2_buf, 0); -+ luma_addr = hantro_get_dec_buf_addr(ctx, &buf->base.vb.vb2_buf); - hantro_write_addr(ctx->dev, ref_reg->y_base, luma_addr); - - chroma_addr = luma_addr + chroma_offset(ctx, dec_params); -@@ -236,7 +236,7 @@ static void config_ref_registers(struct hantro_ctx *ctx, - config_ref(ctx, dst, &ref_regs[1], dec_params, dec_params->golden_frame_ts); - config_ref(ctx, dst, &ref_regs[2], dec_params, dec_params->alt_frame_ts); - -- mv_addr = vb2_dma_contig_plane_dma_addr(&mv_ref->base.vb.vb2_buf, 0) + -+ mv_addr = hantro_get_dec_buf_addr(ctx, &mv_ref->base.vb.vb2_buf) + - mv_offset(ctx, dec_params); - hantro_write_addr(ctx->dev, G2_REF_MV_ADDR(0), mv_addr); - -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index fe5b51046d33..dbe51303724b 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -310,6 +310,7 @@ extern const struct hantro_variant rk3399_vpu_variant; - extern const struct hantro_variant sama5d4_vdec_variant; - - extern const struct hantro_postproc_ops hantro_g1_postproc_ops; -+extern const struct hantro_postproc_ops hantro_g2_postproc_ops; - - extern const u32 hantro_vp8_dec_mc_filter[8][6]; - -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index 89de43021779..a7774ad4c445 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -11,6 +11,7 @@ - #include "hantro.h" - #include "hantro_hw.h" - #include "hantro_g1_regs.h" -+#include "hantro_g2_regs.h" - - #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \ - { \ -@@ -99,6 +100,21 @@ static void hantro_postproc_g1_enable(struct hantro_ctx *ctx) - HANTRO_PP_REG_WRITE(vpu, display_width, ctx->dst_fmt.width); - } - -+static void hantro_postproc_g2_enable(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ struct vb2_v4l2_buffer *dst_buf; -+ size_t chroma_offset = ctx->dst_fmt.width * ctx->dst_fmt.height; -+ dma_addr_t dst_dma; -+ -+ dst_buf = hantro_get_dst_buf(ctx); -+ dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ -+ hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma); -+ hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + chroma_offset); -+ hantro_reg_write(vpu, &g2_out_rs_e, 1); -+} -+ - void hantro_postproc_free(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -@@ -127,6 +143,9 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx) - if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE) - buf_size += hantro_h264_mv_size(ctx->dst_fmt.width, - ctx->dst_fmt.height); -+ else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME) -+ buf_size += hantro_vp9_mv_size(ctx->dst_fmt.width, -+ ctx->dst_fmt.height); - - for (i = 0; i < num_buffers; ++i) { - struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i]; -@@ -152,6 +171,13 @@ static void hantro_postproc_g1_disable(struct hantro_ctx *ctx) - HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0); - } - -+static void hantro_postproc_g2_disable(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ -+ hantro_reg_write(vpu, &g2_out_rs_e, 0); -+} -+ - void hantro_postproc_disable(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -@@ -172,3 +198,8 @@ const struct hantro_postproc_ops hantro_g1_postproc_ops = { - .enable = hantro_postproc_g1_enable, - .disable = hantro_postproc_g1_disable, - }; -+ -+const struct hantro_postproc_ops hantro_g2_postproc_ops = { -+ .enable = hantro_postproc_g2_enable, -+ .disable = hantro_postproc_g2_disable, -+}; -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index 455a107ffb02..1a43f6fceef9 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -132,6 +132,14 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = { - }, - }; - -+static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_NV12, -+ .codec_mode = HANTRO_MODE_NONE, -+ .postprocessed = true, -+ }, -+}; -+ - static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_NV12_4L4, -@@ -301,6 +309,9 @@ const struct hantro_variant imx8mq_vpu_g2_variant = { - .dec_offset = 0x0, - .dec_fmts = imx8m_vpu_g2_dec_fmts, - .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_g2_dec_fmts), -+ .postproc_fmts = imx8m_vpu_g2_postproc_fmts, -+ .num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_g2_postproc_fmts), -+ .postproc_ops = &hantro_g2_postproc_ops, - .codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER, - .codec_ops = imx8mq_vpu_g2_codec_ops, - .init = imx8mq_vpu_hw_init, diff --git a/projects/NXP/devices/iMX8/patches/linux/0080-media-hantro-add-support-for-reset-lines.patch b/projects/NXP/devices/iMX8/patches/linux/0080-media-hantro-add-support-for-reset-lines.patch deleted file mode 100644 index 116ec8c526..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0080-media-hantro-add-support-for-reset-lines.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sat, 7 Aug 2021 17:29:11 +0200 -Subject: [PATCH] media: hantro: add support for reset lines - -Some SoCs like Allwinner H6 use reset lines for resetting Hantro G2. Add -support for them. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/hantro/hantro.h | 3 +++ - drivers/staging/media/hantro/hantro_drv.c | 15 ++++++++++++++- - 2 files changed, 17 insertions(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index 7da23f7f207a..33eb3e092cc1 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -171,6 +172,7 @@ hantro_vdev_to_func(struct video_device *vdev) - * @dev: Pointer to device for convenient logging using - * dev_ macros. - * @clocks: Array of clock handles. -+ * @resets: Array of reset handles. - * @reg_bases: Mapped addresses of VPU registers. - * @enc_base: Mapped address of VPU encoder register for convenience. - * @dec_base: Mapped address of VPU decoder register for convenience. -@@ -190,6 +192,7 @@ struct hantro_dev { - struct platform_device *pdev; - struct device *dev; - struct clk_bulk_data *clocks; -+ struct reset_control *resets; - void __iomem **reg_bases; - void __iomem *enc_base; - void __iomem *dec_base; -diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c -index 3d3107a39dae..770f4ce71d29 100644 ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -905,6 +905,10 @@ static int hantro_probe(struct platform_device *pdev) - return PTR_ERR(vpu->clocks[0].clk); - } - -+ vpu->resets = devm_reset_control_array_get(&pdev->dev, false, true); -+ if (IS_ERR(vpu->resets)) -+ return PTR_ERR(vpu->resets); -+ - num_bases = vpu->variant->num_regs ?: 1; - vpu->reg_bases = devm_kcalloc(&pdev->dev, num_bases, - sizeof(*vpu->reg_bases), GFP_KERNEL); -@@ -978,10 +982,16 @@ static int hantro_probe(struct platform_device *pdev) - pm_runtime_use_autosuspend(vpu->dev); - pm_runtime_enable(vpu->dev); - -+ ret = reset_control_deassert(vpu->resets); -+ if (ret) { -+ dev_err(&pdev->dev, "Failed to deassert resets\n"); -+ goto err_pm_disable; -+ } -+ - ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks); - if (ret) { - dev_err(&pdev->dev, "Failed to prepare clocks\n"); -- goto err_pm_disable; -+ goto err_rst_assert; - } - - ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev); -@@ -1037,6 +1047,8 @@ static int hantro_probe(struct platform_device *pdev) - v4l2_device_unregister(&vpu->v4l2_dev); - err_clk_unprepare: - clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); -+err_rst_assert: -+ reset_control_assert(vpu->resets); - err_pm_disable: - pm_runtime_dont_use_autosuspend(vpu->dev); - pm_runtime_disable(vpu->dev); -@@ -1056,6 +1068,7 @@ static int hantro_remove(struct platform_device *pdev) - v4l2_m2m_release(vpu->m2m_dev); - v4l2_device_unregister(&vpu->v4l2_dev); - clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); -+ reset_control_assert(vpu->resets); - pm_runtime_dont_use_autosuspend(vpu->dev); - pm_runtime_disable(vpu->dev); - return 0; diff --git a/projects/NXP/devices/iMX8/patches/linux/0081-media-hantro-vp9-use-double-buffering-if-needed.patch b/projects/NXP/devices/iMX8/patches/linux/0081-media-hantro-vp9-use-double-buffering-if-needed.patch deleted file mode 100644 index 15f258c253..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0081-media-hantro-vp9-use-double-buffering-if-needed.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 21 Nov 2021 20:39:11 +0100 -Subject: [PATCH] media: hantro: vp9: use double buffering if needed - -Some G2 variants need double buffering to be enabled in order to work -correctly, like that found in Allwinner H6 SoC. - -Add platform quirk for that. - -Reviewed-by: Andrzej Pietrasiewicz -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/hantro/hantro.h | 2 ++ - drivers/staging/media/hantro/hantro_g2_regs.h | 1 + - drivers/staging/media/hantro/hantro_g2_vp9_dec.c | 2 ++ - 3 files changed, 5 insertions(+) - -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index 33eb3e092cc1..d03824fa3222 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -73,6 +73,7 @@ struct hantro_irq { - * @num_clocks: number of clocks in the array - * @reg_names: array of register range names - * @num_regs: number of register range names in the array -+ * @double_buffer: core needs double buffering - */ - struct hantro_variant { - unsigned int enc_offset; -@@ -94,6 +95,7 @@ struct hantro_variant { - int num_clocks; - const char * const *reg_names; - int num_regs; -+ unsigned int double_buffer : 1; - }; - - /** -diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h -index 9c857dd1ad9b..15a391a4650e 100644 ---- a/drivers/staging/media/hantro/hantro_g2_regs.h -+++ b/drivers/staging/media/hantro/hantro_g2_regs.h -@@ -270,6 +270,7 @@ - #define g2_apf_threshold G2_DEC_REG(55, 0, 0xffff) - - #define g2_clk_gate_e G2_DEC_REG(58, 16, 0x1) -+#define g2_double_buffer_e G2_DEC_REG(58, 15, 0x1) - #define g2_buswidth G2_DEC_REG(58, 8, 0x7) - #define g2_max_burst G2_DEC_REG(58, 0, 0xff) - -diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -index e04242d10fa2..d4fc649a4da1 100644 ---- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -@@ -847,6 +847,8 @@ config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_p - hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1); - hantro_reg_write(ctx->dev, &g2_max_cb_size, 6); - hantro_reg_write(ctx->dev, &g2_min_cb_size, 3); -+ if (ctx->dev->variant->double_buffer) -+ hantro_reg_write(ctx->dev, &g2_double_buffer_e, 1); - - config_output(ctx, dst, dec_params); - diff --git a/projects/NXP/devices/iMX8/patches/linux/0082-media-hantro-vp9-add-support-for-legacy-register-set.patch b/projects/NXP/devices/iMX8/patches/linux/0082-media-hantro-vp9-add-support-for-legacy-register-set.patch deleted file mode 100644 index 0283b8f83e..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0082-media-hantro-vp9-add-support-for-legacy-register-set.patch +++ /dev/null @@ -1,242 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Sun, 26 Sep 2021 19:47:03 +0200 -Subject: [PATCH] media: hantro: vp9: add support for legacy register set - -Some older G2 cores uses slightly different register set for HEVC and -VP9. Since vast majority of registers and logic is the same, it doesn't -make sense to introduce another drivers. - -Add legacy_regs quirk and implement only VP9 changes for now. HEVC -changes will be introduced later, if needed. - -Reviewed-by: Andrzej Pietrasiewicz -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/hantro/hantro.h | 2 + - drivers/staging/media/hantro/hantro_g2_regs.h | 16 ++++ - .../staging/media/hantro/hantro_g2_vp9_dec.c | 74 ++++++++++++++----- - 3 files changed, 75 insertions(+), 17 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index d03824fa3222..83ed25d9657b 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -74,6 +74,7 @@ struct hantro_irq { - * @reg_names: array of register range names - * @num_regs: number of register range names in the array - * @double_buffer: core needs double buffering -+ * @legacy_regs: core uses legacy register set - */ - struct hantro_variant { - unsigned int enc_offset; -@@ -96,6 +97,7 @@ struct hantro_variant { - const char * const *reg_names; - int num_regs; - unsigned int double_buffer : 1; -+ unsigned int legacy_regs : 1; - }; - - /** -diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h -index 15a391a4650e..b7c6f9877b9d 100644 ---- a/drivers/staging/media/hantro/hantro_g2_regs.h -+++ b/drivers/staging/media/hantro/hantro_g2_regs.h -@@ -36,7 +36,13 @@ - #define BUS_WIDTH_256 3 - - #define g2_strm_swap G2_DEC_REG(2, 28, 0xf) -+#define g2_strm_swap_old G2_DEC_REG(2, 27, 0x1f) -+#define g2_pic_swap G2_DEC_REG(2, 22, 0x1f) - #define g2_dirmv_swap G2_DEC_REG(2, 20, 0xf) -+#define g2_dirmv_swap_old G2_DEC_REG(2, 17, 0x1f) -+#define g2_tab0_swap_old G2_DEC_REG(2, 12, 0x1f) -+#define g2_tab1_swap_old G2_DEC_REG(2, 7, 0x1f) -+#define g2_tab2_swap_old G2_DEC_REG(2, 2, 0x1f) - - #define g2_mode G2_DEC_REG(3, 27, 0x1f) - #define g2_compress_swap G2_DEC_REG(3, 20, 0xf) -@@ -45,6 +51,8 @@ - #define g2_out_dis G2_DEC_REG(3, 15, 0x1) - #define g2_out_filtering_dis G2_DEC_REG(3, 14, 0x1) - #define g2_write_mvs_e G2_DEC_REG(3, 12, 0x1) -+#define g2_tab3_swap_old G2_DEC_REG(3, 7, 0x1f) -+#define g2_rscan_swap G2_DEC_REG(3, 2, 0x1f) - - #define g2_pic_width_in_cbs G2_DEC_REG(4, 19, 0x1fff) - #define g2_pic_height_in_cbs G2_DEC_REG(4, 6, 0x1fff) -@@ -58,6 +66,7 @@ - #define g2_tempor_mvp_e G2_DEC_REG(5, 11, 0x1) - #define g2_max_cu_qpd_depth G2_DEC_REG(5, 5, 0x3f) - #define g2_cu_qpd_e G2_DEC_REG(5, 4, 0x1) -+#define g2_pix_shift G2_DEC_REG(5, 0, 0xf) - - #define g2_stream_len G2_DEC_REG(6, 0, 0xffffffff) - -@@ -80,21 +89,28 @@ - - #define g2_const_intra_e G2_DEC_REG(8, 31, 0x1) - #define g2_filt_ctrl_pres G2_DEC_REG(8, 30, 0x1) -+#define g2_bit_depth_y G2_DEC_REG(8, 21, 0xf) -+#define g2_bit_depth_c G2_DEC_REG(8, 17, 0xf) - #define g2_idr_pic_e G2_DEC_REG(8, 16, 0x1) - #define g2_bit_depth_pcm_y G2_DEC_REG(8, 12, 0xf) - #define g2_bit_depth_pcm_c G2_DEC_REG(8, 8, 0xf) - #define g2_bit_depth_y_minus8 G2_DEC_REG(8, 6, 0x3) - #define g2_bit_depth_c_minus8 G2_DEC_REG(8, 4, 0x3) -+#define g2_rs_out_bit_depth G2_DEC_REG(8, 4, 0xf) - #define g2_output_8_bits G2_DEC_REG(8, 3, 0x1) - #define g2_output_format G2_DEC_REG(8, 0, 0x7) -+#define g2_pp_pix_shift G2_DEC_REG(8, 0, 0xf) - - #define g2_refidx1_active G2_DEC_REG(9, 19, 0x1f) - #define g2_refidx0_active G2_DEC_REG(9, 14, 0x1f) - #define g2_hdr_skip_length G2_DEC_REG(9, 0, 0x3fff) - - #define g2_start_code_e G2_DEC_REG(10, 31, 0x1) -+#define g2_init_qp_old G2_DEC_REG(10, 25, 0x3f) - #define g2_init_qp G2_DEC_REG(10, 24, 0x3f) -+#define g2_num_tile_cols_old G2_DEC_REG(10, 20, 0x1f) - #define g2_num_tile_cols G2_DEC_REG(10, 19, 0x1f) -+#define g2_num_tile_rows_old G2_DEC_REG(10, 15, 0x1f) - #define g2_num_tile_rows G2_DEC_REG(10, 14, 0x1f) - #define g2_tile_e G2_DEC_REG(10, 1, 0x1) - #define g2_entropy_sync_e G2_DEC_REG(10, 0, 0x1) -diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -index d4fc649a4da1..91c21b634fab 100644 ---- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -@@ -150,7 +150,8 @@ static void config_output(struct hantro_ctx *ctx, - dma_addr_t luma_addr, chroma_addr, mv_addr; - - hantro_reg_write(ctx->dev, &g2_out_dis, 0); -- hantro_reg_write(ctx->dev, &g2_output_format, 0); -+ if (!ctx->dev->variant->legacy_regs) -+ hantro_reg_write(ctx->dev, &g2_output_format, 0); - - luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf); - hantro_write_addr(ctx->dev, G2_OUT_LUMA_ADDR, luma_addr); -@@ -327,6 +328,7 @@ config_tiles(struct hantro_ctx *ctx, - struct hantro_aux_buf *tile_edge = &vp9_ctx->tile_edge; - dma_addr_t addr; - unsigned short *tile_mem; -+ unsigned int rows, cols; - - addr = misc->dma + vp9_ctx->tile_info_offset; - hantro_write_addr(ctx->dev, G2_TILE_SIZES_ADDR, addr); -@@ -344,17 +346,24 @@ config_tiles(struct hantro_ctx *ctx, - - fill_tile_info(ctx, tile_r, tile_c, sbs_r, sbs_c, tile_mem); - -+ cols = tile_c; -+ rows = tile_r; - hantro_reg_write(ctx->dev, &g2_tile_e, 1); -- hantro_reg_write(ctx->dev, &g2_num_tile_cols, tile_c); -- hantro_reg_write(ctx->dev, &g2_num_tile_rows, tile_r); -- - } else { - tile_mem[0] = hantro_vp9_num_sbs(dst->vp9.width); - tile_mem[1] = hantro_vp9_num_sbs(dst->vp9.height); - -+ cols = 1; -+ rows = 1; - hantro_reg_write(ctx->dev, &g2_tile_e, 0); -- hantro_reg_write(ctx->dev, &g2_num_tile_cols, 1); -- hantro_reg_write(ctx->dev, &g2_num_tile_rows, 1); -+ } -+ -+ if (ctx->dev->variant->legacy_regs) { -+ hantro_reg_write(ctx->dev, &g2_num_tile_cols_old, cols); -+ hantro_reg_write(ctx->dev, &g2_num_tile_rows_old, rows); -+ } else { -+ hantro_reg_write(ctx->dev, &g2_num_tile_cols, cols); -+ hantro_reg_write(ctx->dev, &g2_num_tile_rows, rows); - } - - /* provide aux buffers even if no tiles are used */ -@@ -505,8 +514,22 @@ static void config_picture_dimensions(struct hantro_ctx *ctx, struct hantro_deco - static void - config_bit_depth(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) - { -- hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8); -- hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8); -+ if (ctx->dev->variant->legacy_regs) { -+ u8 pp_shift = 0; -+ -+ hantro_reg_write(ctx->dev, &g2_bit_depth_y, dec_params->bit_depth); -+ hantro_reg_write(ctx->dev, &g2_bit_depth_c, dec_params->bit_depth); -+ hantro_reg_write(ctx->dev, &g2_rs_out_bit_depth, dec_params->bit_depth); -+ -+ if (dec_params->bit_depth > 8) -+ pp_shift = 16 - dec_params->bit_depth; -+ -+ hantro_reg_write(ctx->dev, &g2_pp_pix_shift, pp_shift); -+ hantro_reg_write(ctx->dev, &g2_pix_shift, 0); -+ } else { -+ hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8); -+ hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8); -+ } - } - - static inline bool is_lossless(const struct v4l2_vp9_quantization *quant) -@@ -784,9 +807,13 @@ config_source(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_para - + dec_params->compressed_header_size; - - stream_base = vb2_dma_contig_plane_dma_addr(&vb2_src->vb2_buf, 0); -- hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base); - - tmp_addr = stream_base + headres_size; -+ if (ctx->dev->variant->legacy_regs) -+ hantro_write_addr(ctx->dev, G2_STREAM_ADDR, (tmp_addr & ~0xf)); -+ else -+ hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base); -+ - start_bit = (tmp_addr & 0xf) * 8; - hantro_reg_write(ctx->dev, &g2_start_bit, start_bit); - -@@ -794,10 +821,12 @@ config_source(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_para - src_len += start_bit / 8 - headres_size; - hantro_reg_write(ctx->dev, &g2_stream_len, src_len); - -- tmp_addr &= ~0xf; -- hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base); -- src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0); -- hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len); -+ if (!ctx->dev->variant->legacy_regs) { -+ tmp_addr &= ~0xf; -+ hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base); -+ src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0); -+ hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len); -+ } - } - - static void -@@ -837,13 +866,24 @@ config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_p - - /* configure basic registers */ - hantro_reg_write(ctx->dev, &g2_mode, VP9_DEC_MODE); -- hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf); -- hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf); -- hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf); -+ if (!ctx->dev->variant->legacy_regs) { -+ hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf); -+ hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf); -+ hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf); -+ hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1); -+ } else { -+ hantro_reg_write(ctx->dev, &g2_strm_swap_old, 0x1f); -+ hantro_reg_write(ctx->dev, &g2_pic_swap, 0x10); -+ hantro_reg_write(ctx->dev, &g2_dirmv_swap_old, 0x10); -+ hantro_reg_write(ctx->dev, &g2_tab0_swap_old, 0x10); -+ hantro_reg_write(ctx->dev, &g2_tab1_swap_old, 0x10); -+ hantro_reg_write(ctx->dev, &g2_tab2_swap_old, 0x10); -+ hantro_reg_write(ctx->dev, &g2_tab3_swap_old, 0x10); -+ hantro_reg_write(ctx->dev, &g2_rscan_swap, 0x10); -+ } - hantro_reg_write(ctx->dev, &g2_buswidth, BUS_WIDTH_128); - hantro_reg_write(ctx->dev, &g2_max_burst, 16); - hantro_reg_write(ctx->dev, &g2_apf_threshold, 8); -- hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1); - hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1); - hantro_reg_write(ctx->dev, &g2_max_cb_size, 6); - hantro_reg_write(ctx->dev, &g2_min_cb_size, 3); diff --git a/projects/NXP/devices/iMX8/patches/linux/0083-media-hantro-move-postproc-enablement-for-old-cores.patch b/projects/NXP/devices/iMX8/patches/linux/0083-media-hantro-move-postproc-enablement-for-old-cores.patch deleted file mode 100644 index 6c5c6bf10c..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0083-media-hantro-move-postproc-enablement-for-old-cores.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 22 Nov 2021 18:33:14 +0100 -Subject: [PATCH] media: hantro: move postproc enablement for old cores - -Older G2 cores, like that in Allwinner H6, seem to have issue with -latching postproc register values if this is first thing done in job. -Moving that to the end solves the issue. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/hantro/hantro.h | 2 ++ - drivers/staging/media/hantro/hantro_drv.c | 9 ++++++++- - 2 files changed, 10 insertions(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index 83ed25d9657b..06d0f3597694 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -75,6 +75,7 @@ struct hantro_irq { - * @num_regs: number of register range names in the array - * @double_buffer: core needs double buffering - * @legacy_regs: core uses legacy register set -+ * @late_postproc: postproc must be set up at the end of the job - */ - struct hantro_variant { - unsigned int enc_offset; -@@ -98,6 +99,7 @@ struct hantro_variant { - int num_regs; - unsigned int double_buffer : 1; - unsigned int legacy_regs : 1; -+ unsigned int late_postproc : 1; - }; - - /** -diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c -index 770f4ce71d29..33bf78be145b 100644 ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -130,7 +130,7 @@ void hantro_start_prepare_run(struct hantro_ctx *ctx) - v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req, - &ctx->ctrl_handler); - -- if (!ctx->is_encoder) { -+ if (!ctx->is_encoder && !ctx->dev->variant->late_postproc) { - if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt)) - hantro_postproc_enable(ctx); - else -@@ -142,6 +142,13 @@ void hantro_end_prepare_run(struct hantro_ctx *ctx) - { - struct vb2_v4l2_buffer *src_buf; - -+ if (!ctx->is_encoder && ctx->dev->variant->late_postproc) { -+ if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt)) -+ hantro_postproc_enable(ctx); -+ else -+ hantro_postproc_disable(ctx); -+ } -+ - src_buf = hantro_get_src_buf(ctx); - v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req, - &ctx->ctrl_handler); diff --git a/projects/NXP/devices/iMX8/patches/linux/0084-media-hantro-Convert-imx8m_vpu_g2_irq-to-helper.patch b/projects/NXP/devices/iMX8/patches/linux/0084-media-hantro-Convert-imx8m_vpu_g2_irq-to-helper.patch deleted file mode 100644 index 07bb28caac..0000000000 --- a/projects/NXP/devices/iMX8/patches/linux/0084-media-hantro-Convert-imx8m_vpu_g2_irq-to-helper.patch +++ /dev/null @@ -1,92 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jernej Skrabec -Date: Mon, 29 Nov 2021 19:02:17 +0100 -Subject: [PATCH] media: hantro: Convert imx8m_vpu_g2_irq to helper - -It turns out that imx8m_vpu_g2_irq() doesn't depend on any platform -specifics and can be used with other G2 platform drivers too. - -Move it to common code. - -Signed-off-by: Jernej Skrabec ---- - drivers/staging/media/hantro/hantro_g2.c | 18 ++++++++++++++++++ - drivers/staging/media/hantro/hantro_hw.h | 1 + - drivers/staging/media/hantro/imx8m_vpu_hw.c | 20 +------------------- - 3 files changed, 20 insertions(+), 19 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_g2.c b/drivers/staging/media/hantro/hantro_g2.c -index 6f3e1f797f83..ee5f14c5f8f2 100644 ---- a/drivers/staging/media/hantro/hantro_g2.c -+++ b/drivers/staging/media/hantro/hantro_g2.c -@@ -24,3 +24,21 @@ void hantro_g2_check_idle(struct hantro_dev *vpu) - } - } - } -+ -+irqreturn_t hantro_g2_irq(int irq, void *dev_id) -+{ -+ struct hantro_dev *vpu = dev_id; -+ enum vb2_buffer_state state; -+ u32 status; -+ -+ status = vdpu_read(vpu, G2_REG_INTERRUPT); -+ state = (status & G2_REG_INTERRUPT_DEC_RDY_INT) ? -+ VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; -+ -+ vdpu_write(vpu, 0, G2_REG_INTERRUPT); -+ vdpu_write(vpu, G2_REG_CONFIG_DEC_CLK_GATE_E, G2_REG_CONFIG); -+ -+ hantro_irq_done(vpu, state); -+ -+ return IRQ_HANDLED; -+} -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index dbe51303724b..c33b1f5df37b 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -413,5 +413,6 @@ void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx); - int hantro_vp9_dec_init(struct hantro_ctx *ctx); - void hantro_vp9_dec_exit(struct hantro_ctx *ctx); - void hantro_g2_check_idle(struct hantro_dev *vpu); -+irqreturn_t hantro_g2_irq(int irq, void *dev_id); - - #endif /* HANTRO_HW_H_ */ -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index 1a43f6fceef9..f5991b8e553a 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -191,24 +191,6 @@ static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id) - return IRQ_HANDLED; - } - --static irqreturn_t imx8m_vpu_g2_irq(int irq, void *dev_id) --{ -- struct hantro_dev *vpu = dev_id; -- enum vb2_buffer_state state; -- u32 status; -- -- status = vdpu_read(vpu, G2_REG_INTERRUPT); -- state = (status & G2_REG_INTERRUPT_DEC_RDY_INT) ? -- VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; -- -- vdpu_write(vpu, 0, G2_REG_INTERRUPT); -- vdpu_write(vpu, G2_REG_CONFIG_DEC_CLK_GATE_E, G2_REG_CONFIG); -- -- hantro_irq_done(vpu, state); -- -- return IRQ_HANDLED; --} -- - static int imx8mq_vpu_hw_init(struct hantro_dev *vpu) - { - vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1]; -@@ -280,7 +262,7 @@ static const struct hantro_irq imx8mq_irqs[] = { - }; - - static const struct hantro_irq imx8mq_g2_irqs[] = { -- { "g2", imx8m_vpu_g2_irq }, -+ { "g2", hantro_g2_irq }, - }; - - static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" }; diff --git a/projects/NXP/devices/iMX8/patches/linux/0090-media-hantro-Let-VPU-decoders-get-controlled-by-vpu-blk-ctrl.patch b/projects/NXP/devices/iMX8/patches/linux/0090-media-hantro-Let-VPU-decoders-get-controlled-by-vpu-blk-ctrl.patch index 9a17494688..41e31d472f 100644 --- a/projects/NXP/devices/iMX8/patches/linux/0090-media-hantro-Let-VPU-decoders-get-controlled-by-vpu-blk-ctrl.patch +++ b/projects/NXP/devices/iMX8/patches/linux/0090-media-hantro-Let-VPU-decoders-get-controlled-by-vpu-blk-ctrl.patch @@ -1,3 +1,109 @@ +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 8549BC433FE + for ; Tue, 25 Jan 2022 17:26:03 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via 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dts: imx8mq-tqma8mq: Remove redundant vpu reference +Date: Tue, 25 Jan 2022 11:11:18 -0600 +Message-Id: <20220125171129.472775-2-aford173@gmail.com> +X-Mailer: git-send-email 2.32.0 +In-Reply-To: <20220125171129.472775-1-aford173@gmail.com> +References: <20220125171129.472775-1-aford173@gmail.com> +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +Precedence: bulk +List-ID: +X-Mailing-List: linux-kernel@vger.kernel.org + +The vpu is enabled by default, so there is no need to manually +enable it. + +Signed-off-by: Adam Ford + +diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi +index 8aedcddfeab8..38ffcd145b33 100644 +--- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi ++++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi +@@ -272,10 +272,6 @@ &usdhc1 { + status = "okay"; + }; + +-&vpu { +- status = "okay"; +-}; +- + /* Attention: wdog reset forcing POR needs baseboard support */ + &wdog1 { + status = "okay"; +-- +2.32.0 + + From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on @@ -376,8 +482,8 @@ index 511e74f0db8a..122f9c884b38 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -15,6 +15,7 @@ - #include + #include +#include #define BLK_SFT_RSTN 0x0 @@ -453,12 +559,12 @@ index 511e74f0db8a..122f9c884b38 100644 { .compatible = "fsl,imx8mm-vpu-blk-ctrl", @@ -599,6 +662,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = { - .compatible = "fsl,imx8mm-disp-blk-ctrl", - .data = &imx8mm_disp_blk_ctl_dev_data - } ,{ + .compatible = "fsl,imx8mn-disp-blk-ctrl", + .data = &imx8mn_disp_blk_ctl_dev_data + }, { + .compatible = "fsl,imx8mq-vpu-blk-ctrl", + .data = &imx8mq_vpu_blk_ctl_dev_data -+ } ,{ ++ }, { /* Sentinel */ } }; diff --git a/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf b/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf index 290928ac97..f2590507fe 100644 --- a/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf +++ b/projects/Qualcomm/devices/Dragonboard/linux/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.16.0-rc8 Kernel Configuration +# Linux/arm64 5.17.0-rc3 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621" CONFIG_CC_IS_GCC=y @@ -223,7 +223,6 @@ CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y -CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -436,6 +435,8 @@ CONFIG_AS_HAS_LSE_ATOMICS=y # # ARMv8.2 architectural features # +CONFIG_AS_HAS_ARMV8_2=y +CONFIG_AS_HAS_SHA3=y # CONFIG_ARM64_PMEM is not set # CONFIG_ARM64_RAS_EXTN is not set # CONFIG_ARM64_CNP is not set @@ -602,6 +603,7 @@ CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y CONFIG_HAVE_ACPI_APEI=y # CONFIG_ACPI_APEI is not set # CONFIG_ACPI_CONFIGFS is not set +# CONFIG_ACPI_PFRUT is not set CONFIG_ACPI_IORT=y CONFIG_ACPI_GTDT=y CONFIG_ACPI_PPTT=y @@ -701,6 +703,7 @@ CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y @@ -850,7 +853,6 @@ CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -# CONFIG_CLEANCACHE is not set CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set @@ -870,6 +872,7 @@ CONFIG_ZONE_DMA32=y # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_SECRETMEM=y +# CONFIG_ANON_VMA_NAME is not set # # Data Access Monitoring @@ -1018,7 +1021,6 @@ CONFIG_NF_TABLES=m # CONFIG_NF_TABLES_NETDEV is not set # CONFIG_NFT_NUMGEN is not set # CONFIG_NFT_CT is not set -# CONFIG_NFT_COUNTER is not set # CONFIG_NFT_CONNLIMIT is not set # CONFIG_NFT_LOG is not set # CONFIG_NFT_LIMIT is not set @@ -1577,6 +1579,7 @@ CONFIG_PCIE_QCOM=y # CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y @@ -1810,7 +1813,6 @@ CONFIG_XEN_BLKDEV_FRONTEND=y # CONFIG_XEN_BLKDEV_BACKEND is not set CONFIG_VIRTIO_BLK=y # CONFIG_BLK_DEV_RBD is not set -# CONFIG_BLK_DEV_RSXX is not set # # NVME Support @@ -2191,6 +2193,7 @@ CONFIG_NET_VENDOR_DLINK=y # CONFIG_SUNDANCE is not set CONFIG_NET_VENDOR_EMULEX=y # CONFIG_BE2NET is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set CONFIG_NET_VENDOR_EZCHIP=y # CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set CONFIG_NET_VENDOR_GOOGLE=y @@ -2328,6 +2331,7 @@ CONFIG_NET_VENDOR_TEHUTI=y CONFIG_NET_VENDOR_TI=y # CONFIG_TI_CPSW_PHY_SEL is not set # CONFIG_TLAN is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set CONFIG_NET_VENDOR_VIA=y # CONFIG_VIA_RHINE is not set # CONFIG_VIA_VELOCITY is not set @@ -2787,6 +2791,7 @@ CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_DW=y # CONFIG_SERIAL_8250_RT288X is not set +# CONFIG_SERIAL_8250_PERICOM is not set CONFIG_SERIAL_OF_PLATFORM=y # @@ -2843,6 +2848,7 @@ CONFIG_HW_RANDOM_CAVIUM=m # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m +# CONFIG_HW_RANDOM_CN10K is not set # CONFIG_APPLICOM is not set CONFIG_DEVMEM=y CONFIG_DEVPORT=y @@ -3045,13 +3051,13 @@ CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set # CONFIG_PINCTRL_AMD is not set -# CONFIG_PINCTRL_MCP23S08 is not set -CONFIG_PINCTRL_SINGLE=y -# CONFIG_PINCTRL_SX150X is not set -# CONFIG_PINCTRL_STMFX is not set CONFIG_PINCTRL_MAX77620=y -# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_MCP23S08 is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_SINGLE=y +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_SX150X is not set CONFIG_PINCTRL_MSM=y CONFIG_PINCTRL_APQ8064=y CONFIG_PINCTRL_APQ8084=y @@ -3085,9 +3091,11 @@ CONFIG_PINCTRL_QCOM_SSBI_PMIC=y # CONFIG_PINCTRL_SM6115 is not set # CONFIG_PINCTRL_SM6125 is not set # CONFIG_PINCTRL_SM6350 is not set +# CONFIG_PINCTRL_SDX65 is not set # CONFIG_PINCTRL_SM8150 is not set # CONFIG_PINCTRL_SM8250 is not set # CONFIG_PINCTRL_SM8350 is not set +# CONFIG_PINCTRL_SM8450 is not set # CONFIG_PINCTRL_LPASS_LPI is not set # @@ -3182,6 +3190,7 @@ CONFIG_GPIO_MAX77620=y # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set @@ -3225,6 +3234,7 @@ CONFIG_BATTERY_BQ27XXX_I2C=y # CONFIG_CHARGER_LT3651 is not set # CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_MAX77976 is not set # CONFIG_CHARGER_QCOM_SMBB is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set @@ -3428,7 +3438,6 @@ CONFIG_MFD_SYSCON=y # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set -# CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set @@ -3470,6 +3479,7 @@ CONFIG_REGULATOR_MAX77620=y # CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX20086 is not set # CONFIG_REGULATOR_MAX77826 is not set # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MP5416 is not set @@ -3792,6 +3802,7 @@ CONFIG_VIDEO_IR_I2C=y # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5693 is not set # CONFIG_VIDEO_OV5695 is not set # CONFIG_VIDEO_OV7251 is not set # CONFIG_VIDEO_OV772X is not set @@ -3906,7 +3917,8 @@ CONFIG_DRM_I2C_SIL164=m # CONFIG_DRM_AST is not set # CONFIG_DRM_MGAG200 is not set # CONFIG_DRM_RCAR_DW_HDMI is not set -# CONFIG_DRM_RCAR_LVDS is not set +# CONFIG_DRM_RCAR_USE_LVDS is not set +# CONFIG_DRM_RCAR_MIPI_DSI is not set # CONFIG_DRM_QXL is not set # CONFIG_DRM_VIRTIO_GPU is not set CONFIG_DRM_MSM=y @@ -3929,6 +3941,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set +# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set # CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set # CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set # CONFIG_DRM_PANEL_DSI_CM is not set @@ -3943,6 +3956,7 @@ CONFIG_DRM_PANEL_EDP=y # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_JDI_R63452 is not set # CONFIG_DRM_PANEL_KHADAS_TS050 is not set # CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set @@ -3952,6 +3966,7 @@ CONFIG_DRM_PANEL_EDP=y # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set # CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -3983,6 +3998,7 @@ CONFIG_DRM_PANEL_EDP=y # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set # CONFIG_DRM_PANEL_SONY_ACX424AKP is not set # CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set # CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set @@ -4046,6 +4062,7 @@ CONFIG_DRM_I2C_ADV7511_CEC=y # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9163 is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set # CONFIG_TINYDRM_ILI9486 is not set @@ -4061,6 +4078,7 @@ CONFIG_DRM_I2C_ADV7511_CEC=y # CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_NOMODESET=y # # Frame buffer Devices @@ -4277,6 +4295,7 @@ CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y CONFIG_SND_SOC=y # CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_AMD_ACP_CONFIG is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set @@ -4338,6 +4357,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set CONFIG_SND_SOC_AK4613=y @@ -4434,6 +4454,7 @@ CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=y # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set # CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320ADC3XXX is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set @@ -4553,6 +4574,7 @@ CONFIG_HID_KENSINGTON=y # CONFIG_HID_LCPOWER is not set # CONFIG_HID_LED is not set # CONFIG_HID_LENOVO is not set +# CONFIG_HID_LETSKETCH is not set CONFIG_HID_LOGITECH=m # CONFIG_HID_LOGITECH_HIDPP is not set # CONFIG_LOGITECH_FF is not set @@ -4675,6 +4697,7 @@ CONFIG_USB_OHCI_HCD_PLATFORM=y # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set # CONFIG_USB_HCD_TEST_MODE is not set +# CONFIG_USB_XEN_HCD is not set # # USB Device Class drivers @@ -5071,6 +5094,10 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set # CONFIG_LEDS_TRIGGER_TTY is not set + +# +# Simple LED drivers +# # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_SUPPORT=y @@ -5335,6 +5362,7 @@ CONFIG_COMMON_CLK_SCPI=y # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set CONFIG_COMMON_CLK_CS2000_CP=y +# CONFIG_COMMON_CLK_LAN966X is not set CONFIG_COMMON_CLK_S2MPS11=y # CONFIG_COMMON_CLK_AXI_CLKGEN is not set CONFIG_COMMON_CLK_XGENE=y @@ -5368,6 +5396,7 @@ CONFIG_MSM_MMCC_8960=y # CONFIG_MSM_GCC_8953 is not set CONFIG_MSM_GCC_8974=y CONFIG_MSM_MMCC_8974=y +# CONFIG_MSM_GCC_8976 is not set # CONFIG_MSM_MMCC_8994 is not set CONFIG_MSM_GCC_8994=y CONFIG_MSM_GCC_8996=y @@ -5404,12 +5433,14 @@ CONFIG_MSM_MMCC_8996=y # CONFIG_SDM_LPASSCC_845 is not set # CONFIG_SDX_GCC_55 is not set # CONFIG_SM_CAMCC_8250 is not set +# CONFIG_SDX_GCC_65 is not set # CONFIG_SM_GCC_6115 is not set # CONFIG_SM_GCC_6125 is not set # CONFIG_SM_GCC_6350 is not set # CONFIG_SM_GCC_8150 is not set # CONFIG_SM_GCC_8250 is not set # CONFIG_SM_GCC_8350 is not set +# CONFIG_SM_GCC_8450 is not set # CONFIG_SM_GPUCC_8150 is not set # CONFIG_SM_GPUCC_8250 is not set # CONFIG_SM_VIDEOCC_8150 is not set @@ -5717,6 +5748,12 @@ CONFIG_IIO=y # CONFIG_XILINX_XADC is not set # end of Analog to digital converters +# +# Analog to digital and digital to analog converters +# +# CONFIG_AD74413R is not set +# end of Analog to digital and digital to analog converters + # # Analog Front Ends # @@ -5772,6 +5809,7 @@ CONFIG_IIO=y # # Digital to analog converters # +# CONFIG_AD3552R is not set # CONFIG_AD5064 is not set # CONFIG_AD5360 is not set # CONFIG_AD5380 is not set @@ -5791,6 +5829,7 @@ CONFIG_IIO=y # CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set +# CONFIG_AD7293 is not set # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set # CONFIG_DPOT_DAC is not set @@ -5814,6 +5853,12 @@ CONFIG_IIO=y # # end of IIO dummy driver +# +# Filters +# +# CONFIG_ADMV8818 is not set +# end of Filters + # # Frequency Synthesizers DDS/PLL # @@ -5829,6 +5874,7 @@ CONFIG_IIO=y # # CONFIG_ADF4350 is not set # CONFIG_ADF4371 is not set +# CONFIG_ADMV1013 is not set # CONFIG_ADRF6780 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL @@ -6120,12 +6166,15 @@ CONFIG_PHY_XGENE=y # CONFIG_PHY_CADENCE_SALVO is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set # CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_FSL_IMX8M_PCIE is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_LAN966X_SERDES is not set # CONFIG_PHY_CPCAP_USB is not set # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set CONFIG_PHY_QCOM_APQ8064_SATA=y +# CONFIG_PHY_QCOM_EDP is not set # CONFIG_PHY_QCOM_IPQ4019_USB is not set CONFIG_PHY_QCOM_IPQ806X_SATA=y # CONFIG_PHY_QCOM_PCIE2 is not set @@ -6158,7 +6207,9 @@ CONFIG_ARM_PMU_ACPI=y # CONFIG_QCOM_L3_PMU is not set # CONFIG_ARM_SPE_PMU is not set # CONFIG_ARM_DMC620_PMU is not set +# CONFIG_MARVELL_CN10K_TAD_PMU is not set # CONFIG_HISI_PMU is not set +# CONFIG_HISI_PCIE_PMU is not set # end of Performance monitor support CONFIG_RAS=y @@ -6650,6 +6701,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_KDF800108_CTR=y CONFIG_CRYPTO_USER_API=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_SKCIPHER=y @@ -6658,25 +6710,6 @@ CONFIG_CRYPTO_USER_API_RNG=y CONFIG_CRYPTO_USER_API_AEAD=y CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y CONFIG_CRYPTO_HASH_INFO=y - -# -# Crypto library routines -# -CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_BLAKE2S=y -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y -CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y -CONFIG_CRYPTO_LIB_CHACHA=y -CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y -CONFIG_CRYPTO_LIB_CURVE25519=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y -CONFIG_CRYPTO_LIB_POLY1305=y -CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y -CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set @@ -6726,7 +6759,6 @@ CONFIG_HAVE_ARCH_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y -CONFIG_GENERIC_FIND_FIRST_BIT=y # CONFIG_CORDIC is not set # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y @@ -6735,6 +6767,26 @@ CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y # CONFIG_INDIRECT_PIO is not set + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y +CONFIG_CRYPTO_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y +CONFIG_CRYPTO_LIB_CURVE25519=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + CONFIG_CRC_CCITT=m CONFIG_CRC16=y CONFIG_CRC_T10DIF=y @@ -6903,6 +6955,13 @@ CONFIG_HAVE_KCSAN_COMPILER=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# end of Networking Debugging + # # Memory Debugging # @@ -7059,12 +7118,12 @@ CONFIG_CORESIGHT_SOURCE_ETM4X=y # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_TEST_REF_TRACKER is not set # CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set # CONFIG_INTERVAL_TREE_TEST is not set @@ -7082,7 +7141,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_XARRAY is not set # CONFIG_TEST_OVERFLOW is not set # CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_HASH is not set +# CONFIG_TEST_SIPHASH is not set # CONFIG_TEST_IDA is not set # CONFIG_TEST_LKM is not set # CONFIG_TEST_BITOPS is not set diff --git a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf index d19184a2da..86b7364139 100644 --- a/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf +++ b/projects/Rockchip/devices/RK3288/linux/default/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.16.0-rc8 Kernel Configuration +# Linux/arm 5.17.0-rc3 Kernel Configuration # CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-10.3.0 (GCC) 10.3.0" CONFIG_CC_IS_GCC=y @@ -217,7 +217,6 @@ CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y -CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -660,6 +659,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y @@ -802,13 +802,12 @@ CONFIG_CONTIG_ALLOC=y CONFIG_BOUNCE=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -# CONFIG_CLEANCACHE is not set -# CONFIG_FRONTSWAP is not set CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 +# CONFIG_ZSWAP is not set # CONFIG_ZPOOL is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y @@ -817,6 +816,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_GUP_TEST is not set CONFIG_KMAP_LOCAL=y CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y +# CONFIG_ANON_VMA_NAME is not set # # Data Access Monitoring @@ -1103,6 +1103,7 @@ CONFIG_HAVE_PCI=y # CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y @@ -1408,7 +1409,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_ISCSI_BOOT_SYSFS is not set # CONFIG_SCSI_UFSHCD is not set -# CONFIG_SCSI_UFS_HWMON is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_VIRTIO is not set # CONFIG_SCSI_DH is not set @@ -1485,6 +1485,7 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_CORTINA is not set # CONFIG_DM9000 is not set # CONFIG_DNET is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set # CONFIG_NET_VENDOR_EZCHIP is not set # CONFIG_NET_VENDOR_FARADAY is not set CONFIG_NET_VENDOR_GOOGLE=y @@ -1520,6 +1521,7 @@ CONFIG_DWMAC_GENERIC=y CONFIG_DWMAC_ROCKCHIP=y # CONFIG_DWMAC_INTEL_PLAT is not set # CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set @@ -2009,7 +2011,6 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_DW=y -CONFIG_SERIAL_8250_EM=y # CONFIG_SERIAL_8250_RT288X is not set CONFIG_SERIAL_OF_PLATFORM=y @@ -2222,14 +2223,14 @@ CONFIG_GENERIC_PINCONF=y CONFIG_PINCTRL_AS3722=y # CONFIG_PINCTRL_AXP209 is not set # CONFIG_PINCTRL_MCP23S08 is not set -CONFIG_PINCTRL_ROCKCHIP=y -# CONFIG_PINCTRL_SINGLE is not set -# CONFIG_PINCTRL_SX150X is not set -# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_OCELOT is not set CONFIG_PINCTRL_PALMAS=y # CONFIG_PINCTRL_RK805 is not set -# CONFIG_PINCTRL_OCELOT is not set -# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +CONFIG_PINCTRL_ROCKCHIP=y +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_SX150X is not set # # Renesas pinctrl drivers @@ -2318,6 +2319,7 @@ CONFIG_GPIO_TPS65910=y # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set @@ -2352,6 +2354,7 @@ CONFIG_BATTERY_CPCAP=y # CONFIG_CHARGER_MAX14577 is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set # CONFIG_CHARGER_MAX77693 is not set +# CONFIG_CHARGER_MAX77976 is not set # CONFIG_CHARGER_MAX8997 is not set # CONFIG_CHARGER_MAX8998 is not set # CONFIG_CHARGER_BQ2415X is not set @@ -2479,6 +2482,7 @@ CONFIG_SENSORS_LM90=y # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set @@ -2507,6 +2511,7 @@ CONFIG_SENSORS_PWM_FAN=m # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_INA209 is not set CONFIG_SENSORS_INA2XX=m +# CONFIG_SENSORS_INA238 is not set # CONFIG_SENSORS_INA3221 is not set # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set @@ -2711,7 +2716,6 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set -# CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set @@ -2766,6 +2770,7 @@ CONFIG_REGULATOR_MAX8907=y # CONFIG_REGULATOR_MAX8973 is not set CONFIG_REGULATOR_MAX8997=m CONFIG_REGULATOR_MAX8998=m +# CONFIG_REGULATOR_MAX20086 is not set CONFIG_REGULATOR_MAX77686=y CONFIG_REGULATOR_MAX77693=m CONFIG_REGULATOR_MAX77802=m @@ -3191,6 +3196,7 @@ CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5693 is not set # CONFIG_VIDEO_OV5695 is not set # CONFIG_VIDEO_OV7251 is not set # CONFIG_VIDEO_OV772X is not set @@ -3478,7 +3484,8 @@ CONFIG_ROCKCHIP_DW_HDMI=y # CONFIG_DRM_ARMADA is not set # CONFIG_DRM_ATMEL_HLCDC is not set # CONFIG_DRM_RCAR_DW_HDMI is not set -# CONFIG_DRM_RCAR_LVDS is not set +# CONFIG_DRM_RCAR_USE_LVDS is not set +# CONFIG_DRM_RCAR_MIPI_DSI is not set # CONFIG_DRM_OMAP is not set # CONFIG_DRM_TILCDC is not set # CONFIG_DRM_VIRTIO_GPU is not set @@ -3495,6 +3502,7 @@ CONFIG_DRM_PANEL=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set @@ -3571,6 +3579,7 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9163 is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set # CONFIG_TINYDRM_ILI9486 is not set @@ -3587,6 +3596,7 @@ CONFIG_DRM_PANFROST=y # CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_NOMODESET=y # # Frame buffer Devices @@ -3714,6 +3724,7 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_AMD_ACP_CONFIG is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set @@ -3776,6 +3787,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set @@ -3879,6 +3891,7 @@ CONFIG_SND_SOC_STI_SAS=m # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set # CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320ADC3XXX is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set @@ -4001,6 +4014,7 @@ CONFIG_HID_KENSINGTON=y CONFIG_HID_LCPOWER=y # CONFIG_HID_LED is not set CONFIG_HID_LENOVO=y +# CONFIG_HID_LETSKETCH is not set CONFIG_HID_LOGITECH=y CONFIG_HID_LOGITECH_DJ=y CONFIG_HID_LOGITECH_HIDPP=y @@ -4483,6 +4497,10 @@ CONFIG_LEDS_TRIGGER_CAMERA=y # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set # CONFIG_LEDS_TRIGGER_TTY is not set + +# +# Simple LED drivers +# # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y @@ -4749,6 +4767,7 @@ CONFIG_R8188EU=m CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_HANTRO_ROCKCHIP=y +# CONFIG_VIDEO_MAX96712 is not set CONFIG_VIDEO_ROCKCHIP_VDEC=m # @@ -4807,6 +4826,7 @@ CONFIG_COMMON_CLK_SCPI=m # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_LAN966X is not set CONFIG_COMMON_CLK_S2MPS11=m # CONFIG_COMMON_CLK_AXI_CLKGEN is not set # CONFIG_COMMON_CLK_PALMAS is not set @@ -5101,6 +5121,12 @@ CONFIG_VF610_ADC=m # CONFIG_XILINX_XADC is not set # end of Analog to digital converters +# +# Analog to digital and digital to analog converters +# +# CONFIG_AD74413R is not set +# end of Analog to digital and digital to analog converters + # # Analog Front Ends # @@ -5161,6 +5187,7 @@ CONFIG_VF610_ADC=m # # Digital to analog converters # +# CONFIG_AD3552R is not set # CONFIG_AD5064 is not set # CONFIG_AD5360 is not set # CONFIG_AD5380 is not set @@ -5180,6 +5207,7 @@ CONFIG_VF610_ADC=m # CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set +# CONFIG_AD7293 is not set # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set # CONFIG_DPOT_DAC is not set @@ -5203,6 +5231,11 @@ CONFIG_VF610_ADC=m # # end of IIO dummy driver +# +# Filters +# +# end of Filters + # # Frequency Synthesizers DDS/PLL # @@ -5218,6 +5251,7 @@ CONFIG_VF610_ADC=m # # CONFIG_ADF4350 is not set # CONFIG_ADF4371 is not set +# CONFIG_ADMV1013 is not set # CONFIG_ADRF6780 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL @@ -5512,8 +5546,10 @@ CONFIG_GENERIC_PHY=y # CONFIG_PHY_CADENCE_SALVO is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set # CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_FSL_IMX8M_PCIE is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_LAN966X_SERDES is not set # CONFIG_PHY_CPCAP_USB is not set # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set @@ -6057,6 +6093,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=m CONFIG_CRYPTO_JITTERENTROPY=m +CONFIG_CRYPTO_KDF800108_CTR=y CONFIG_CRYPTO_USER_API=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_SKCIPHER=y @@ -6066,27 +6103,6 @@ CONFIG_CRYPTO_USER_API_AEAD=m CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y # CONFIG_CRYPTO_STATS is not set CONFIG_CRYPTO_HASH_INFO=y - -# -# Crypto library routines -# -CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=m -CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=m -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m -CONFIG_CRYPTO_LIB_BLAKE2S=m -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y -CONFIG_CRYPTO_LIB_CHACHA=m -CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=y -CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y -CONFIG_CRYPTO_LIB_CURVE25519=m -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y -CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305=m -CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m -CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set @@ -6132,6 +6148,28 @@ CONFIG_CORDIC=m CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=y +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + CONFIG_CRC_CCITT=m CONFIG_CRC16=y # CONFIG_CRC_T10DIF is not set @@ -6279,6 +6317,13 @@ CONFIG_HAVE_KCSAN_COMPILER=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# end of Networking Debugging + # # Memory Debugging # @@ -6307,6 +6352,8 @@ CONFIG_HAVE_ARCH_KASAN=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -6391,6 +6438,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y CONFIG_TRACE_CLOCK=y CONFIG_RING_BUFFER=y CONFIG_EVENT_TRACING=y @@ -6458,6 +6506,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_TEST_REF_TRACKER is not set # CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set # CONFIG_INTERVAL_TREE_TEST is not set @@ -6475,7 +6524,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_XARRAY is not set # CONFIG_TEST_OVERFLOW is not set # CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_HASH is not set +# CONFIG_TEST_SIPHASH is not set # CONFIG_TEST_IDA is not set # CONFIG_TEST_LKM is not set # CONFIG_TEST_BITOPS is not set diff --git a/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf index a31b643592..a51b3a58ad 100644 --- a/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3328/linux/default/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.16.0-rc8 Kernel Configuration +# Linux/arm64 5.17.0-rc3 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621" CONFIG_CC_IS_GCC=y @@ -221,7 +221,6 @@ CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y -CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -430,6 +429,8 @@ CONFIG_AS_HAS_LSE_ATOMICS=y # # ARMv8.2 architectural features # +CONFIG_AS_HAS_ARMV8_2=y +CONFIG_AS_HAS_SHA3=y # CONFIG_ARM64_PMEM is not set # CONFIG_ARM64_RAS_EXTN is not set # CONFIG_ARM64_CNP is not set @@ -652,6 +653,7 @@ CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y @@ -866,13 +868,12 @@ CONFIG_MEMORY_FAILURE=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -# CONFIG_CLEANCACHE is not set -# CONFIG_FRONTSWAP is not set CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 +# CONFIG_ZSWAP is not set # CONFIG_ZPOOL is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y @@ -887,6 +888,7 @@ CONFIG_ZONE_DMA32=y # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_SECRETMEM=y +# CONFIG_ANON_VMA_NAME is not set # # Data Access Monitoring @@ -1342,6 +1344,7 @@ CONFIG_HAVE_PCI=y # CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y @@ -1636,7 +1639,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_ISCSI_BOOT_SYSFS is not set # CONFIG_SCSI_UFSHCD is not set -# CONFIG_SCSI_UFS_HWMON is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_VIRTIO is not set # CONFIG_SCSI_DH is not set @@ -1684,6 +1686,7 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_CAVIUM is not set # CONFIG_NET_VENDOR_CORTINA is not set # CONFIG_DNET is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set # CONFIG_NET_VENDOR_EZCHIP is not set CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_NET_VENDOR_HISILICON is not set @@ -1718,6 +1721,7 @@ CONFIG_DWMAC_GENERIC=y CONFIG_DWMAC_ROCKCHIP=y # CONFIG_DWMAC_INTEL_PLAT is not set # CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set @@ -2398,15 +2402,15 @@ CONFIG_PINMUX=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set +CONFIG_PINCTRL_MAX77620=y # CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_RK805=y CONFIG_PINCTRL_ROCKCHIP=y # CONFIG_PINCTRL_SINGLE is not set -# CONFIG_PINCTRL_SX150X is not set # CONFIG_PINCTRL_STMFX is not set -CONFIG_PINCTRL_MAX77620=y -CONFIG_PINCTRL_RK805=y -# CONFIG_PINCTRL_OCELOT is not set -# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_SX150X is not set # # Renesas pinctrl drivers @@ -2488,6 +2492,7 @@ CONFIG_GPIO_MAX77620=y # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set @@ -2529,6 +2534,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_LT3651 is not set # CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_MAX77976 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set @@ -2649,6 +2655,7 @@ CONFIG_SENSORS_LM90=m # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set @@ -2677,6 +2684,7 @@ CONFIG_SENSORS_PWM_FAN=m # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_INA209 is not set CONFIG_SENSORS_INA2XX=m +# CONFIG_SENSORS_INA238 is not set # CONFIG_SENSORS_INA3221 is not set # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set @@ -2865,7 +2873,6 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set -# CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set @@ -2908,6 +2915,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX20086 is not set # CONFIG_REGULATOR_MAX77826 is not set # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MP5416 is not set @@ -3272,6 +3280,7 @@ CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5693 is not set # CONFIG_VIDEO_OV5695 is not set # CONFIG_VIDEO_OV7251 is not set # CONFIG_VIDEO_OV772X is not set @@ -3555,7 +3564,8 @@ CONFIG_ROCKCHIP_DW_HDMI=y # CONFIG_ROCKCHIP_RK3066_HDMI is not set # CONFIG_DRM_UDL is not set # CONFIG_DRM_RCAR_DW_HDMI is not set -# CONFIG_DRM_RCAR_LVDS is not set +# CONFIG_DRM_RCAR_USE_LVDS is not set +# CONFIG_DRM_RCAR_MIPI_DSI is not set # CONFIG_DRM_VIRTIO_GPU is not set CONFIG_DRM_PANEL=y @@ -3568,6 +3578,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_SIMPLE is not set CONFIG_DRM_PANEL_EDP=y # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set @@ -3643,6 +3654,7 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9163 is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set # CONFIG_TINYDRM_ILI9486 is not set @@ -3657,6 +3669,7 @@ CONFIG_DRM_LIMA=y # CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_NOMODESET=y # # Frame buffer Devices @@ -3782,6 +3795,7 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_AMD_ACP_CONFIG is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set @@ -3843,6 +3857,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set CONFIG_SND_SOC_AK4613=m @@ -3947,6 +3962,7 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set # CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320ADC3XXX is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set @@ -4068,6 +4084,7 @@ CONFIG_HID_KENSINGTON=y CONFIG_HID_LCPOWER=y # CONFIG_HID_LED is not set CONFIG_HID_LENOVO=y +# CONFIG_HID_LETSKETCH is not set CONFIG_HID_LOGITECH=y CONFIG_HID_LOGITECH_DJ=y CONFIG_HID_LOGITECH_HIDPP=y @@ -4500,6 +4517,10 @@ CONFIG_LEDS_TRIGGER_PANIC=y # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set # CONFIG_LEDS_TRIGGER_TTY is not set + +# +# Simple LED drivers +# # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_SUPPORT=y @@ -4762,6 +4783,7 @@ CONFIG_R8188EU=m CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_HANTRO_ROCKCHIP=y +# CONFIG_VIDEO_MAX96712 is not set CONFIG_VIDEO_ROCKCHIP_VDEC=m # @@ -4784,6 +4806,7 @@ CONFIG_VIDEO_ROCKCHIP_VDEC=m CONFIG_CHROME_PLATFORMS=y # CONFIG_CROS_EC is not set # CONFIG_MELLANOX_PLATFORM is not set +# CONFIG_SURFACE_PLATFORMS is not set CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y @@ -4808,6 +4831,7 @@ CONFIG_COMMON_CLK_SCPI=y # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set CONFIG_COMMON_CLK_CS2000_CP=y +# CONFIG_COMMON_CLK_LAN966X is not set CONFIG_COMMON_CLK_S2MPS11=y # CONFIG_COMMON_CLK_AXI_CLKGEN is not set CONFIG_COMMON_CLK_XGENE=y @@ -5095,6 +5119,12 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_XILINX_XADC is not set # end of Analog to digital converters +# +# Analog to digital and digital to analog converters +# +# CONFIG_AD74413R is not set +# end of Analog to digital and digital to analog converters + # # Analog Front Ends # @@ -5152,6 +5182,7 @@ CONFIG_ROCKCHIP_SARADC=y # # Digital to analog converters # +# CONFIG_AD3552R is not set # CONFIG_AD5064 is not set # CONFIG_AD5360 is not set # CONFIG_AD5380 is not set @@ -5171,6 +5202,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set +# CONFIG_AD7293 is not set # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set # CONFIG_DPOT_DAC is not set @@ -5194,6 +5226,12 @@ CONFIG_ROCKCHIP_SARADC=y # # end of IIO dummy driver +# +# Filters +# +# CONFIG_ADMV8818 is not set +# end of Filters + # # Frequency Synthesizers DDS/PLL # @@ -5209,6 +5247,7 @@ CONFIG_ROCKCHIP_SARADC=y # # CONFIG_ADF4350 is not set # CONFIG_ADF4371 is not set +# CONFIG_ADMV1013 is not set # CONFIG_ADRF6780 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL @@ -5499,8 +5538,10 @@ CONFIG_GENERIC_PHY=y # CONFIG_PHY_CADENCE_SALVO is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set # CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_FSL_IMX8M_PCIE is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_LAN966X_SERDES is not set # CONFIG_PHY_CPCAP_USB is not set # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set @@ -5533,6 +5574,7 @@ CONFIG_PHY_ROCKCHIP_USB=y CONFIG_ARM_PMU=y # CONFIG_ARM_DSU_PMU is not set # CONFIG_ARM_SPE_PMU is not set +# CONFIG_MARVELL_CN10K_TAD_PMU is not set # end of Performance monitor support CONFIG_RAS=y @@ -5937,7 +5979,7 @@ CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y # end of Kernel hardening options # end of Security options -CONFIG_XOR_BLOCKS=m +CONFIG_XOR_BLOCKS=y CONFIG_CRYPTO=y # @@ -5970,7 +6012,6 @@ CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_AUTHENC=m # CONFIG_CRYPTO_TEST is not set -CONFIG_CRYPTO_SIMD=y CONFIG_CRYPTO_ENGINE=m # @@ -6084,6 +6125,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_KDF800108_CTR=y CONFIG_CRYPTO_USER_API=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_SKCIPHER=y @@ -6091,26 +6133,6 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y # CONFIG_CRYPTO_USER_API_AEAD is not set CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y CONFIG_CRYPTO_HASH_INFO=y - -# -# Crypto library routines -# -CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=m -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m -CONFIG_CRYPTO_LIB_BLAKE2S=m -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y -CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y -CONFIG_CRYPTO_LIB_CHACHA=m -CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m -CONFIG_CRYPTO_LIB_CURVE25519=m -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y -CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305=m -CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m -CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set @@ -6153,7 +6175,6 @@ CONFIG_HAVE_ARCH_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y -CONFIG_GENERIC_FIND_FIRST_BIT=y CONFIG_CORDIC=m # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y @@ -6162,6 +6183,27 @@ CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y # CONFIG_INDIRECT_PIO is not set + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + CONFIG_CRC_CCITT=m CONFIG_CRC16=y # CONFIG_CRC_T10DIF is not set @@ -6326,6 +6368,13 @@ CONFIG_HAVE_KCSAN_COMPILER=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# end of Networking Debugging + # # Memory Debugging # @@ -6467,7 +6516,6 @@ CONFIG_STRICT_DEVMEM=y # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y diff --git a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf index 9e7b33aa50..ca04640f1b 100644 --- a/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf +++ b/projects/Rockchip/devices/RK3399/linux/default/linux.aarch64.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 5.16.0-rc8 Kernel Configuration +# Linux/arm64 5.17.0-rc3 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-none-linux-gnu-gcc.real (GNU Toolchain for the A-profile Architecture 10.3-2021.07 (arm-10.29)) 10.3.1 20210621" CONFIG_CC_IS_GCC=y @@ -221,7 +221,6 @@ CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y -CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -430,6 +429,8 @@ CONFIG_AS_HAS_LSE_ATOMICS=y # # ARMv8.2 architectural features # +CONFIG_AS_HAS_ARMV8_2=y +CONFIG_AS_HAS_SHA3=y # CONFIG_ARM64_PMEM is not set # CONFIG_ARM64_RAS_EXTN is not set # CONFIG_ARM64_CNP is not set @@ -652,6 +653,7 @@ CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y @@ -867,13 +869,12 @@ CONFIG_MEMORY_FAILURE=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -# CONFIG_CLEANCACHE is not set -# CONFIG_FRONTSWAP is not set CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 +# CONFIG_ZSWAP is not set # CONFIG_ZPOOL is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y @@ -888,6 +889,7 @@ CONFIG_ZONE_DMA32=y # CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_SECRETMEM=y +# CONFIG_ANON_VMA_NAME is not set # # Data Access Monitoring @@ -1415,6 +1417,7 @@ CONFIG_PCIE_ROCKCHIP_HOST=m # CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y @@ -1617,7 +1620,6 @@ CONFIG_BLK_DEV_NBD=m # CONFIG_ATA_OVER_ETH is not set CONFIG_VIRTIO_BLK=y # CONFIG_BLK_DEV_RBD is not set -# CONFIG_BLK_DEV_RSXX is not set # # NVME Support @@ -1763,7 +1765,6 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_MPI3MR is not set # CONFIG_SCSI_SMARTPQI is not set # CONFIG_SCSI_UFSHCD is not set -# CONFIG_SCSI_UFS_HWMON is not set # CONFIG_SCSI_HPTIOP is not set # CONFIG_SCSI_MYRB is not set # CONFIG_SCSI_MYRS is not set @@ -1965,6 +1966,7 @@ CONFIG_NET_VENDOR_DLINK=y # CONFIG_SUNDANCE is not set CONFIG_NET_VENDOR_EMULEX=y # CONFIG_BE2NET is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set # CONFIG_NET_VENDOR_EZCHIP is not set CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_GVE is not set @@ -2041,6 +2043,7 @@ CONFIG_NET_VENDOR_TEHUTI=y CONFIG_NET_VENDOR_TI=y # CONFIG_TI_CPSW_PHY_SEL is not set # CONFIG_TLAN is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set @@ -2587,6 +2590,7 @@ CONFIG_SERIAL_8250_DWLIB=y CONFIG_SERIAL_8250_FSL=y CONFIG_SERIAL_8250_DW=y # CONFIG_SERIAL_8250_RT288X is not set +# CONFIG_SERIAL_8250_PERICOM is not set CONFIG_SERIAL_OF_PLATFORM=y # @@ -2637,6 +2641,7 @@ CONFIG_HW_RANDOM_OPTEE=m # CONFIG_HW_RANDOM_CCTRNG is not set # CONFIG_HW_RANDOM_XIPHERA is not set CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=m +# CONFIG_HW_RANDOM_CN10K is not set # CONFIG_APPLICOM is not set CONFIG_DEVMEM=y CONFIG_DEVPORT=y @@ -2821,15 +2826,15 @@ CONFIG_PINMUX=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set +CONFIG_PINCTRL_MAX77620=y # CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_RK805=y CONFIG_PINCTRL_ROCKCHIP=y # CONFIG_PINCTRL_SINGLE is not set -# CONFIG_PINCTRL_SX150X is not set # CONFIG_PINCTRL_STMFX is not set -CONFIG_PINCTRL_MAX77620=y -CONFIG_PINCTRL_RK805=y -# CONFIG_PINCTRL_OCELOT is not set -# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_SX150X is not set # # Renesas pinctrl drivers @@ -2921,6 +2926,7 @@ CONFIG_GPIO_MAX77620=y # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set @@ -2962,6 +2968,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_LT3651 is not set # CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_MAX77976 is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_BQ24190 is not set # CONFIG_CHARGER_BQ24257 is not set @@ -3084,6 +3091,7 @@ CONFIG_SENSORS_LM90=m # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set @@ -3113,6 +3121,7 @@ CONFIG_SENSORS_PWM_FAN=m # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_INA209 is not set CONFIG_SENSORS_INA2XX=m +# CONFIG_SENSORS_INA238 is not set # CONFIG_SENSORS_INA3221 is not set # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set @@ -3325,7 +3334,6 @@ CONFIG_MFD_WL1273_CORE=m # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set # CONFIG_MFD_ROHM_BD718XX is not set -# CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set @@ -3368,6 +3376,7 @@ CONFIG_REGULATOR_GPIO=y # CONFIG_REGULATOR_MAX8893 is not set # CONFIG_REGULATOR_MAX8952 is not set # CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX20086 is not set # CONFIG_REGULATOR_MAX77826 is not set # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MP5416 is not set @@ -3795,6 +3804,7 @@ CONFIG_VIDEO_OV2640=m # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5693 is not set # CONFIG_VIDEO_OV5695 is not set # CONFIG_VIDEO_OV7251 is not set # CONFIG_VIDEO_OV772X is not set @@ -4103,7 +4113,8 @@ CONFIG_ROCKCHIP_DW_HDMI=y # CONFIG_DRM_AST is not set # CONFIG_DRM_MGAG200 is not set # CONFIG_DRM_RCAR_DW_HDMI is not set -# CONFIG_DRM_RCAR_LVDS is not set +# CONFIG_DRM_RCAR_USE_LVDS is not set +# CONFIG_DRM_RCAR_MIPI_DSI is not set # CONFIG_DRM_QXL is not set # CONFIG_DRM_VIRTIO_GPU is not set CONFIG_DRM_PANEL=y @@ -4117,6 +4128,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_SIMPLE is not set CONFIG_DRM_PANEL_EDP=y # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set @@ -4195,6 +4207,7 @@ CONFIG_DRM_DW_HDMI_CEC=y # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9163 is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set # CONFIG_TINYDRM_ILI9486 is not set @@ -4209,6 +4222,7 @@ CONFIG_DRM_PANFROST=y # CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_NOMODESET=y # # Frame buffer Devices @@ -4425,6 +4439,7 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_AMD_ACP_CONFIG is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set @@ -4486,6 +4501,7 @@ CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set CONFIG_SND_SOC_AK4613=m @@ -4590,6 +4606,7 @@ CONFIG_SND_SOC_SPDIF=y # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set # CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320ADC3XXX is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set @@ -4711,6 +4728,7 @@ CONFIG_HID_KENSINGTON=y CONFIG_HID_LCPOWER=y # CONFIG_HID_LED is not set CONFIG_HID_LENOVO=y +# CONFIG_HID_LETSKETCH is not set CONFIG_HID_LOGITECH=y CONFIG_HID_LOGITECH_DJ=y CONFIG_HID_LOGITECH_HIDPP=y @@ -5182,6 +5200,10 @@ CONFIG_LEDS_TRIGGER_PANIC=y # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set # CONFIG_LEDS_TRIGGER_TTY is not set + +# +# Simple LED drivers +# # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_SUPPORT=y @@ -5458,6 +5480,7 @@ CONFIG_R8188EU=m CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_HANTRO=m CONFIG_VIDEO_HANTRO_ROCKCHIP=y +# CONFIG_VIDEO_MAX96712 is not set CONFIG_VIDEO_ROCKCHIP_VDEC=m # CONFIG_VIDEO_ZORAN is not set CONFIG_DVB_AV7110_IR=y @@ -5485,6 +5508,7 @@ CONFIG_DVB_SP8870=m # CONFIG_GOLDFISH is not set # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set +# CONFIG_SURFACE_PLATFORMS is not set CONFIG_HAVE_CLK=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y @@ -5509,6 +5533,7 @@ CONFIG_COMMON_CLK_SCPI=y # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set CONFIG_COMMON_CLK_CS2000_CP=y +# CONFIG_COMMON_CLK_LAN966X is not set CONFIG_COMMON_CLK_S2MPS11=y # CONFIG_COMMON_CLK_AXI_CLKGEN is not set CONFIG_COMMON_CLK_XGENE=y @@ -5795,6 +5820,12 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_XILINX_XADC is not set # end of Analog to digital converters +# +# Analog to digital and digital to analog converters +# +# CONFIG_AD74413R is not set +# end of Analog to digital and digital to analog converters + # # Analog Front Ends # @@ -5852,6 +5883,7 @@ CONFIG_ROCKCHIP_SARADC=y # # Digital to analog converters # +# CONFIG_AD3552R is not set # CONFIG_AD5064 is not set # CONFIG_AD5360 is not set # CONFIG_AD5380 is not set @@ -5871,6 +5903,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set +# CONFIG_AD7293 is not set # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set # CONFIG_DPOT_DAC is not set @@ -5894,6 +5927,12 @@ CONFIG_ROCKCHIP_SARADC=y # # end of IIO dummy driver +# +# Filters +# +# CONFIG_ADMV8818 is not set +# end of Filters + # # Frequency Synthesizers DDS/PLL # @@ -5909,6 +5948,7 @@ CONFIG_ROCKCHIP_SARADC=y # # CONFIG_ADF4350 is not set # CONFIG_ADF4371 is not set +# CONFIG_ADMV1013 is not set # CONFIG_ADRF6780 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL @@ -6205,8 +6245,10 @@ CONFIG_GENERIC_PHY_MIPI_DPHY=y # CONFIG_PHY_CADENCE_SALVO is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set # CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_FSL_IMX8M_PCIE is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_LAN966X_SERDES is not set # CONFIG_PHY_CPCAP_USB is not set # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set @@ -6239,6 +6281,8 @@ CONFIG_PHY_ROCKCHIP_USB=y CONFIG_ARM_PMU=y # CONFIG_ARM_DSU_PMU is not set # CONFIG_ARM_SPE_PMU is not set +# CONFIG_MARVELL_CN10K_TAD_PMU is not set +# CONFIG_HISI_PCIE_PMU is not set # end of Performance monitor support CONFIG_RAS=y @@ -6644,7 +6688,7 @@ CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y # end of Kernel hardening options # end of Security options -CONFIG_XOR_BLOCKS=m +CONFIG_XOR_BLOCKS=y CONFIG_CRYPTO=y # @@ -6677,7 +6721,6 @@ CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_AUTHENC=m # CONFIG_CRYPTO_TEST is not set -CONFIG_CRYPTO_SIMD=y CONFIG_CRYPTO_ENGINE=m # @@ -6791,6 +6834,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_KDF800108_CTR=y CONFIG_CRYPTO_USER_API=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_SKCIPHER=y @@ -6798,26 +6842,6 @@ CONFIG_CRYPTO_USER_API_SKCIPHER=y # CONFIG_CRYPTO_USER_API_AEAD is not set CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y CONFIG_CRYPTO_HASH_INFO=y - -# -# Crypto library routines -# -CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=m -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m -CONFIG_CRYPTO_LIB_BLAKE2S=m -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y -CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y -CONFIG_CRYPTO_LIB_CHACHA=m -CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m -CONFIG_CRYPTO_LIB_CURVE25519=m -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y -CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y -CONFIG_CRYPTO_LIB_POLY1305=m -CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m -CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set # CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set @@ -6862,7 +6886,6 @@ CONFIG_HAVE_ARCH_BITREVERSE=y CONFIG_GENERIC_STRNCPY_FROM_USER=y CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y -CONFIG_GENERIC_FIND_FIRST_BIT=y CONFIG_CORDIC=m # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y @@ -6871,6 +6894,27 @@ CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y # CONFIG_INDIRECT_PIO is not set + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + CONFIG_CRC_CCITT=m CONFIG_CRC16=y # CONFIG_CRC_T10DIF is not set @@ -7036,6 +7080,13 @@ CONFIG_HAVE_KCSAN_COMPILER=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# end of Networking Debugging + # # Memory Debugging # @@ -7177,7 +7228,6 @@ CONFIG_STRICT_DEVMEM=y # CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y diff --git a/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch index aa65a2e741..c039e12eb7 100644 --- a/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0002-rockchip-from-list.patch @@ -376,133 +376,3 @@ index d0410ae4def2..cc46855aba46 100644 status = "disabled"; }; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 27 Oct 2021 14:43:40 +0200 -Subject: [PATCH] arm64: dts: rockchip: add interrupt and headphone-detection - for Rock Pi4's audio codec - -As Schematics at [1] and [2] show C- and plus-revisions have interrupt and -headphone detection lines of ES8316 codec connected. - -Add them to the respective device trees. - -[1] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi_4c_v12_sch_20200620.pdf -[2] https://dl.radxa.com/rockpi4/docs/hw/rockpi4/rockpi4b_plus_v16_sch_20200628.pdf - -Signed-off-by: Alex Bee ---- - arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 12 +++++++++++- - .../boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts | 11 +++++++++++ - .../boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts | 11 +++++++++++ - arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts | 11 +++++++++++ - 4 files changed, 44 insertions(+), 1 deletion(-) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -index 6a434be62819..92acf6ea299b 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi -@@ -36,7 +36,7 @@ sdio_pwrseq: sdio-pwrseq { - reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; - }; - -- sound { -+ sound: sound { - compatible = "audio-graph-card"; - label = "Analog"; - dais = <&i2s0_p0>; -@@ -543,6 +543,16 @@ bt_wake_l: bt-wake-l { - }; - }; - -+ es8316 { -+ hp_detect: hp-detect { -+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ hp_int: hp-int { -+ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ - pcie { - pcie_pwr_en: pcie-pwr-en { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts -index 281a04b2f5e9..f5a68d8d072d 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dts -@@ -12,3 +12,14 @@ / { - model = "Radxa ROCK Pi 4A+"; - compatible = "radxa,rockpi4a-plus", "radxa,rockpi4", "rockchip,rk3399"; - }; -+ -+&es8316 { -+ pinctrl-0 = <&hp_detect &hp_int>; -+ pinctrl-names = "default"; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+}; -+ -+&sound { -+ hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -+}; -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts -index dfad13d2ab24..81bea953c891 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts -@@ -17,6 +17,13 @@ aliases { - }; - }; - -+&es8316 { -+ pinctrl-0 = <&hp_detect &hp_int>; -+ pinctrl-names = "default"; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+}; -+ - &sdio0 { - status = "okay"; - -@@ -31,6 +38,10 @@ brcmf: wifi@1 { - }; - }; - -+&sound { -+ hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -+}; -+ - &uart0 { - status = "okay"; - -diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts -index 99169bcd51c0..0ad7b6e22f70 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts -@@ -17,6 +17,13 @@ aliases { - }; - }; - -+&es8316 { -+ pinctrl-0 = <&hp_detect &hp_int>; -+ pinctrl-names = "default"; -+ interrupt-parent = <&gpio1>; -+ interrupts = ; -+}; -+ - &sdio0 { - status = "okay"; - -@@ -31,6 +38,10 @@ brcmf: wifi@1 { - }; - }; - -+&sound { -+ hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; -+}; -+ - &uart0 { - status = "okay"; - diff --git a/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-5.17.patch b/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-5.17.patch deleted file mode 100644 index a7199627bc..0000000000 --- a/projects/Rockchip/patches/linux/default/linux-0010-v4l2-from-5.17.patch +++ /dev/null @@ -1,7502 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Tue, 16 Nov 2021 15:38:31 +0100 -Subject: [PATCH] hantro: postproc: Fix motion vector space size - -When the post-processor hardware block is enabled, the driver -allocates an internal queue of buffers for the decoder enginer, -and uses the vb2 queue for the post-processor engine. - -For instance, on a G1 core, the decoder engine produces NV12 buffers -and the post-processor engine can produce YUY2 buffers. The decoder -engine expects motion vectors to be appended to the NV12 buffers, -but this is only required for CODECs that need motion vectors, -such as H.264. - -Fix the post-processor logic accordingly. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/hantro_postproc.c | 7 ++++--- - 1 file changed, 4 insertions(+), 3 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index ed8916c950a4..07842152003f 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -132,9 +132,10 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx) - unsigned int num_buffers = cap_queue->num_buffers; - unsigned int i, buf_size; - -- buf_size = ctx->dst_fmt.plane_fmt[0].sizeimage + -- hantro_h264_mv_size(ctx->dst_fmt.width, -- ctx->dst_fmt.height); -+ buf_size = ctx->dst_fmt.plane_fmt[0].sizeimage; -+ if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE) -+ buf_size += hantro_h264_mv_size(ctx->dst_fmt.width, -+ ctx->dst_fmt.height); - - for (i = 0; i < num_buffers; ++i) { - struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i]; - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Tue, 16 Nov 2021 15:38:32 +0100 -Subject: [PATCH] hantro: postproc: Introduce struct hantro_postproc_ops - -Turns out the post-processor block on the G2 core is substantially -different from the one on the G1 core. Introduce hantro_postproc_ops -with .enable and .disable methods, which will allow to support -the G2 post-processor cleanly. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Andrzej Pietrasiewicz -Reviewed-by: Benjamin Gaignard -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/hantro.h | 5 +-- - drivers/staging/media/hantro/hantro_hw.h | 13 +++++++- - .../staging/media/hantro/hantro_postproc.c | 33 ++++++++++++++----- - drivers/staging/media/hantro/imx8m_vpu_hw.c | 2 +- - .../staging/media/hantro/rockchip_vpu_hw.c | 6 ++-- - .../staging/media/hantro/sama5d4_vdec_hw.c | 2 +- - 6 files changed, 44 insertions(+), 17 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index c2e2dca38628..c2e01959dc00 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -28,6 +28,7 @@ - - struct hantro_ctx; - struct hantro_codec_ops; -+struct hantro_postproc_ops; - - #define HANTRO_JPEG_ENCODER BIT(0) - #define HANTRO_ENCODERS 0x0000ffff -@@ -59,6 +60,7 @@ struct hantro_irq { - * @num_dec_fmts: Number of decoder formats. - * @postproc_fmts: Post-processor formats. - * @num_postproc_fmts: Number of post-processor formats. -+ * @postproc_ops: Post-processor ops. - * @codec: Supported codecs - * @codec_ops: Codec ops. - * @init: Initialize hardware, optional. -@@ -69,7 +71,6 @@ struct hantro_irq { - * @num_clocks: number of clocks in the array - * @reg_names: array of register range names - * @num_regs: number of register range names in the array -- * @postproc_regs: &struct hantro_postproc_regs pointer - */ - struct hantro_variant { - unsigned int enc_offset; -@@ -80,6 +81,7 @@ struct hantro_variant { - unsigned int num_dec_fmts; - const struct hantro_fmt *postproc_fmts; - unsigned int num_postproc_fmts; -+ const struct hantro_postproc_ops *postproc_ops; - unsigned int codec; - const struct hantro_codec_ops *codec_ops; - int (*init)(struct hantro_dev *vpu); -@@ -90,7 +92,6 @@ struct hantro_variant { - int num_clocks; - const char * const *reg_names; - int num_regs; -- const struct hantro_postproc_regs *postproc_regs; - }; - - /** -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index 267a6d33a47b..2f85430682d8 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -174,6 +174,17 @@ struct hantro_postproc_ctx { - struct hantro_aux_buf dec_q[VB2_MAX_FRAME]; - }; - -+/** -+ * struct hantro_postproc_ops - post-processor operations -+ * -+ * @enable: Enable the post-processor block. Optional. -+ * @disable: Disable the post-processor block. Optional. -+ */ -+struct hantro_postproc_ops { -+ void (*enable)(struct hantro_ctx *ctx); -+ void (*disable)(struct hantro_ctx *ctx); -+}; -+ - /** - * struct hantro_codec_ops - codec mode specific operations - * -@@ -221,7 +232,7 @@ extern const struct hantro_variant rk3328_vpu_variant; - extern const struct hantro_variant rk3399_vpu_variant; - extern const struct hantro_variant sama5d4_vdec_variant; - --extern const struct hantro_postproc_regs hantro_g1_postproc_regs; -+extern const struct hantro_postproc_ops hantro_g1_postproc_ops; - - extern const u32 hantro_vp8_dec_mc_filter[8][6]; - -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index 07842152003f..882fb8bc5ddd 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -15,14 +15,14 @@ - #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \ - { \ - hantro_reg_write(vpu, \ -- &(vpu)->variant->postproc_regs->reg_name, \ -+ &hantro_g1_postproc_regs.reg_name, \ - val); \ - } - - #define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \ - { \ - hantro_reg_write_s(vpu, \ -- &(vpu)->variant->postproc_regs->reg_name, \ -+ &hantro_g1_postproc_regs.reg_name, \ - val); \ - } - -@@ -64,16 +64,13 @@ bool hantro_needs_postproc(const struct hantro_ctx *ctx, - return fmt->fourcc != V4L2_PIX_FMT_NV12; - } - --void hantro_postproc_enable(struct hantro_ctx *ctx) -+static void hantro_postproc_g1_enable(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; - struct vb2_v4l2_buffer *dst_buf; - u32 src_pp_fmt, dst_pp_fmt; - dma_addr_t dst_dma; - -- if (!vpu->variant->postproc_regs) -- return; -- - /* Turn on pipeline mode. Must be done first. */ - HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x1); - -@@ -154,12 +151,30 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx) - return 0; - } - -+static void hantro_postproc_g1_disable(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ -+ HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0); -+} -+ - void hantro_postproc_disable(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; - -- if (!vpu->variant->postproc_regs) -- return; -+ if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->disable) -+ vpu->variant->postproc_ops->disable(ctx); -+} - -- HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0); -+void hantro_postproc_enable(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ -+ if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->enable) -+ vpu->variant->postproc_ops->enable(ctx); - } -+ -+const struct hantro_postproc_ops hantro_g1_postproc_ops = { -+ .enable = hantro_postproc_g1_enable, -+ .disable = hantro_postproc_g1_disable, -+}; -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index ea919bfb9891..22fa7d2f3b64 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -262,7 +262,7 @@ const struct hantro_variant imx8mq_vpu_variant = { - .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts), - .postproc_fmts = imx8m_vpu_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts), -- .postproc_regs = &hantro_g1_postproc_regs, -+ .postproc_ops = &hantro_g1_postproc_ops, - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | - HANTRO_H264_DECODER, - .codec_ops = imx8mq_vpu_codec_ops, -diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c -index d4f52957cc53..6c1ad5534ce5 100644 ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -460,7 +460,7 @@ const struct hantro_variant rk3036_vpu_variant = { - .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts), - .postproc_fmts = rockchip_vpu1_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts), -- .postproc_regs = &hantro_g1_postproc_regs, -+ .postproc_ops = &hantro_g1_postproc_ops, - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | - HANTRO_H264_DECODER, - .codec_ops = rk3036_vpu_codec_ops, -@@ -485,7 +485,7 @@ const struct hantro_variant rk3066_vpu_variant = { - .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts), - .postproc_fmts = rockchip_vpu1_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts), -- .postproc_regs = &hantro_g1_postproc_regs, -+ .postproc_ops = &hantro_g1_postproc_ops, - .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | - HANTRO_VP8_DECODER | HANTRO_H264_DECODER, - .codec_ops = rk3066_vpu_codec_ops, -@@ -505,7 +505,7 @@ const struct hantro_variant rk3288_vpu_variant = { - .num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts), - .postproc_fmts = rockchip_vpu1_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts), -- .postproc_regs = &hantro_g1_postproc_regs, -+ .postproc_ops = &hantro_g1_postproc_ops, - .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | - HANTRO_VP8_DECODER | HANTRO_H264_DECODER, - .codec_ops = rk3288_vpu_codec_ops, -diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c -index 9c3b8cd0b239..f3fecc7248c4 100644 ---- a/drivers/staging/media/hantro/sama5d4_vdec_hw.c -+++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c -@@ -100,7 +100,7 @@ const struct hantro_variant sama5d4_vdec_variant = { - .num_dec_fmts = ARRAY_SIZE(sama5d4_vdec_fmts), - .postproc_fmts = sama5d4_vdec_postproc_fmts, - .num_postproc_fmts = ARRAY_SIZE(sama5d4_vdec_postproc_fmts), -- .postproc_regs = &hantro_g1_postproc_regs, -+ .postproc_ops = &hantro_g1_postproc_ops, - .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | - HANTRO_H264_DECODER, - .codec_ops = sama5d4_vdec_codec_ops, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Tue, 16 Nov 2021 15:38:33 +0100 -Subject: [PATCH] hantro: Simplify postprocessor - -Add a 'postprocessed' boolean property to struct hantro_fmt -to signal that a format is produced by the post-processor. -This will allow to introduce the G2 post-processor in a simple way. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/hantro.h | 2 ++ - drivers/staging/media/hantro/hantro_postproc.c | 8 +------- - drivers/staging/media/hantro/imx8m_vpu_hw.c | 1 + - drivers/staging/media/hantro/rockchip_vpu_hw.c | 1 + - drivers/staging/media/hantro/sama5d4_vdec_hw.c | 1 + - 5 files changed, 6 insertions(+), 7 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index c2e01959dc00..dd5e56765d4e 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -263,6 +263,7 @@ struct hantro_ctx { - * @max_depth: Maximum depth, for bitstream formats - * @enc_fmt: Format identifier for encoder registers. - * @frmsize: Supported range of frame sizes (only for bitstream formats). -+ * @postprocessed: Indicates if this format needs the post-processor. - */ - struct hantro_fmt { - char *name; -@@ -272,6 +273,7 @@ struct hantro_fmt { - int max_depth; - enum hantro_enc_fmt enc_fmt; - struct v4l2_frmsize_stepwise frmsize; -+ bool postprocessed; - }; - - struct hantro_reg { -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index 882fb8bc5ddd..4549aec08feb 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -53,15 +53,9 @@ const struct hantro_postproc_regs hantro_g1_postproc_regs = { - bool hantro_needs_postproc(const struct hantro_ctx *ctx, - const struct hantro_fmt *fmt) - { -- struct hantro_dev *vpu = ctx->dev; -- - if (ctx->is_encoder) - return false; -- -- if (!vpu->variant->postproc_fmts) -- return false; -- -- return fmt->fourcc != V4L2_PIX_FMT_NV12; -+ return fmt->postprocessed; - } - - static void hantro_postproc_g1_enable(struct hantro_ctx *ctx) -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index 22fa7d2f3b64..02e61438220a 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -82,6 +82,7 @@ static const struct hantro_fmt imx8m_vpu_postproc_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_YUYV, - .codec_mode = HANTRO_MODE_NONE, -+ .postprocessed = true, - }, - }; - -diff --git a/drivers/staging/media/hantro/rockchip_vpu_hw.c b/drivers/staging/media/hantro/rockchip_vpu_hw.c -index 6c1ad5534ce5..f372f767d4ff 100644 ---- a/drivers/staging/media/hantro/rockchip_vpu_hw.c -+++ b/drivers/staging/media/hantro/rockchip_vpu_hw.c -@@ -62,6 +62,7 @@ static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_YUYV, - .codec_mode = HANTRO_MODE_NONE, -+ .postprocessed = true, - }, - }; - -diff --git a/drivers/staging/media/hantro/sama5d4_vdec_hw.c b/drivers/staging/media/hantro/sama5d4_vdec_hw.c -index f3fecc7248c4..b2fc1c5613e1 100644 ---- a/drivers/staging/media/hantro/sama5d4_vdec_hw.c -+++ b/drivers/staging/media/hantro/sama5d4_vdec_hw.c -@@ -15,6 +15,7 @@ static const struct hantro_fmt sama5d4_vdec_postproc_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_YUYV, - .codec_mode = HANTRO_MODE_NONE, -+ .postprocessed = true, - }, - }; - - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Ezequiel Garcia -Date: Tue, 16 Nov 2021 15:38:34 +0100 -Subject: [PATCH] hantro: Add quirk for NV12/NV12_4L4 capture format - -The G2 core decoder engine produces NV12_4L4 format, -which is a simple NV12 4x4 tiled format. The driver currently -hides this format by always enabling the post-processor engine, -and therefore offering NV12 directly. - -This is done without using the logic in hantro_postproc.c -and therefore makes it difficult to add VP9 cleanly. - -Since fixing this is not easy, add a small quirk to force -NV12 if HEVC was configured, but otherwise declare NV12_4L4 -as the pixel format in imx8mq_vpu_g2_variant.dec_fmts. - -This will be used by the VP9 decoder which will be added soon. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/hantro_v4l2.c | 14 ++++++++++++++ - drivers/staging/media/hantro/imx8m_vpu_hw.c | 2 +- - 2 files changed, 15 insertions(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c -index bcb0bdff4a9a..d1f060c55fed 100644 ---- a/drivers/staging/media/hantro/hantro_v4l2.c -+++ b/drivers/staging/media/hantro/hantro_v4l2.c -@@ -150,6 +150,20 @@ static int vidioc_enum_fmt(struct file *file, void *priv, - unsigned int num_fmts, i, j = 0; - bool skip_mode_none; - -+ /* -+ * The HEVC decoder on the G2 core needs a little quirk to offer NV12 -+ * only on the capture side. Once the post-processor logic is used, -+ * we will be able to expose NV12_4L4 and NV12 as the other cases, -+ * and therefore remove this quirk. -+ */ -+ if (capture && ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE) { -+ if (f->index == 0) { -+ f->pixelformat = V4L2_PIX_FMT_NV12; -+ return 0; -+ } -+ return -EINVAL; -+ } -+ - /* - * When dealing with an encoder: - * - on the capture side we want to filter out all MODE_NONE formats. -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index 02e61438220a..a40b161e5956 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -134,7 +134,7 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = { - - static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = { - { -- .fourcc = V4L2_PIX_FMT_NV12, -+ .fourcc = V4L2_PIX_FMT_NV12_4L4, - .codec_mode = HANTRO_MODE_NONE, - }, - { - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:35 +0100 -Subject: [PATCH] media: uapi: Add VP9 stateless decoder controls - -Add the VP9 stateless decoder controls plus the documentation that goes -with it. - -Signed-off-by: Boris Brezillon -Co-developed-by: Ezequiel Garcia -Signed-off-by: Ezequiel Garcia -Signed-off-by: Adrian Ratiu -Signed-off-by: Andrzej Pietrasiewicz -Co-developed-by: Daniel Almeida -Signed-off-by: Daniel Almeida -Signed-off-by: Hans Verkuil ---- - .../userspace-api/media/v4l/biblio.rst | 10 + - .../media/v4l/ext-ctrls-codec-stateless.rst | 573 ++++++++++++++++++ - .../media/v4l/pixfmt-compressed.rst | 15 + - .../media/v4l/vidioc-g-ext-ctrls.rst | 8 + - .../media/v4l/vidioc-queryctrl.rst | 12 + - .../media/videodev2.h.rst.exceptions | 2 + - drivers/media/v4l2-core/v4l2-ctrls-core.c | 180 ++++++ - drivers/media/v4l2-core/v4l2-ctrls-defs.c | 8 + - drivers/media/v4l2-core/v4l2-ioctl.c | 1 + - include/media/v4l2-ctrls.h | 4 + - include/uapi/linux/v4l2-controls.h | 284 +++++++++ - include/uapi/linux/videodev2.h | 6 + - 12 files changed, 1103 insertions(+) - -diff --git a/Documentation/userspace-api/media/v4l/biblio.rst b/Documentation/userspace-api/media/v4l/biblio.rst -index 7b8e6738ff9e..9cd18c153d19 100644 ---- a/Documentation/userspace-api/media/v4l/biblio.rst -+++ b/Documentation/userspace-api/media/v4l/biblio.rst -@@ -417,3 +417,13 @@ VP8 - :title: RFC 6386: "VP8 Data Format and Decoding Guide" - - :author: J. Bankoski et al. -+ -+.. _vp9: -+ -+VP9 -+=== -+ -+ -+:title: VP9 Bitstream & Decoding Process Specification -+ -+:author: Adrian Grange (Google), Peter de Rivaz (Argon Design), Jonathan Hunt (Argon Design) -diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst -index 72f5e85b4f34..cc080c4257d0 100644 ---- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst -+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst -@@ -1458,3 +1458,576 @@ FWHT Flags - .. raw:: latex - - \normalsize -+ -+.. _v4l2-codec-stateless-vp9: -+ -+``V4L2_CID_STATELESS_VP9_COMPRESSED_HDR (struct)`` -+ Stores VP9 probabilities updates as parsed from the current compressed frame -+ header. A value of zero in an array element means no update of the relevant -+ probability. Motion vector-related updates contain a new value or zero. All -+ other updates contain values translated with inv_map_table[] (see 6.3.5 in -+ :ref:`vp9`). -+ -+.. c:type:: v4l2_ctrl_vp9_compressed_hdr -+ -+.. tabularcolumns:: |p{1cm}|p{4.8cm}|p{11.4cm}| -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_vp9_compressed_hdr -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``tx_mode`` -+ - Specifies the TX mode. See :ref:`TX Mode ` for more details. -+ * - __u8 -+ - ``tx8[2][1]`` -+ - TX 8x8 probabilities delta. -+ * - __u8 -+ - ``tx16[2][2]`` -+ - TX 16x16 probabilities delta. -+ * - __u8 -+ - ``tx32[2][3]`` -+ - TX 32x32 probabilities delta. -+ * - __u8 -+ - ``coef[4][2][2][6][6][3]`` -+ - Coefficient probabilities delta. -+ * - __u8 -+ - ``skip[3]`` -+ - Skip probabilities delta. -+ * - __u8 -+ - ``inter_mode[7][3]`` -+ - Inter prediction mode probabilities delta. -+ * - __u8 -+ - ``interp_filter[4][2]`` -+ - Interpolation filter probabilities delta. -+ * - __u8 -+ - ``is_inter[4]`` -+ - Is inter-block probabilities delta. -+ * - __u8 -+ - ``comp_mode[5]`` -+ - Compound prediction mode probabilities delta. -+ * - __u8 -+ - ``single_ref[5][2]`` -+ - Single reference probabilities delta. -+ * - __u8 -+ - ``comp_ref[5]`` -+ - Compound reference probabilities delta. -+ * - __u8 -+ - ``y_mode[4][9]`` -+ - Y prediction mode probabilities delta. -+ * - __u8 -+ - ``uv_mode[10][9]`` -+ - UV prediction mode probabilities delta. -+ * - __u8 -+ - ``partition[16][3]`` -+ - Partition probabilities delta. -+ * - __u8 -+ - ``mv.joint[3]`` -+ - Motion vector joint probabilities delta. -+ * - __u8 -+ - ``mv.sign[2]`` -+ - Motion vector sign probabilities delta. -+ * - __u8 -+ - ``mv.classes[2][10]`` -+ - Motion vector class probabilities delta. -+ * - __u8 -+ - ``mv.class0_bit[2]`` -+ - Motion vector class0 bit probabilities delta. -+ * - __u8 -+ - ``mv.bits[2][10]`` -+ - Motion vector bits probabilities delta. -+ * - __u8 -+ - ``mv.class0_fr[2][2][3]`` -+ - Motion vector class0 fractional bit probabilities delta. -+ * - __u8 -+ - ``mv.fr[2][3]`` -+ - Motion vector fractional bit probabilities delta. -+ * - __u8 -+ - ``mv.class0_hp[2]`` -+ - Motion vector class0 high precision fractional bit probabilities delta. -+ * - __u8 -+ - ``mv.hp[2]`` -+ - Motion vector high precision fractional bit probabilities delta. -+ -+.. _vp9_tx_mode: -+ -+``TX Mode`` -+ -+.. tabularcolumns:: |p{6.5cm}|p{0.5cm}|p{10.3cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_TX_MODE_ONLY_4X4`` -+ - 0 -+ - Transform size is 4x4. -+ * - ``V4L2_VP9_TX_MODE_ALLOW_8X8`` -+ - 1 -+ - Transform size can be up to 8x8. -+ * - ``V4L2_VP9_TX_MODE_ALLOW_16X16`` -+ - 2 -+ - Transform size can be up to 16x16. -+ * - ``V4L2_VP9_TX_MODE_ALLOW_32X32`` -+ - 3 -+ - transform size can be up to 32x32. -+ * - ``V4L2_VP9_TX_MODE_SELECT`` -+ - 4 -+ - Bitstream contains the transform size for each block. -+ -+See section '7.3.1 Tx mode semantics' of the :ref:`vp9` specification for more details. -+ -+``V4L2_CID_STATELESS_VP9_FRAME (struct)`` -+ Specifies the frame parameters for the associated VP9 frame decode request. -+ This includes the necessary parameters for configuring a stateless hardware -+ decoding pipeline for VP9. The bitstream parameters are defined according -+ to :ref:`vp9`. -+ -+.. c:type:: v4l2_ctrl_vp9_frame -+ -+.. raw:: latex -+ -+ \small -+ -+.. tabularcolumns:: |p{4.7cm}|p{5.5cm}|p{7.1cm}| -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_vp9_frame -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - struct :c:type:`v4l2_vp9_loop_filter` -+ - ``lf`` -+ - Loop filter parameters. See struct :c:type:`v4l2_vp9_loop_filter` for more details. -+ * - struct :c:type:`v4l2_vp9_quantization` -+ - ``quant`` -+ - Quantization parameters. See :c:type:`v4l2_vp9_quantization` for more details. -+ * - struct :c:type:`v4l2_vp9_segmentation` -+ - ``seg`` -+ - Segmentation parameters. See :c:type:`v4l2_vp9_segmentation` for more details. -+ * - __u32 -+ - ``flags`` -+ - Combination of V4L2_VP9_FRAME_FLAG_* flags. See :ref:`Frame Flags`. -+ * - __u16 -+ - ``compressed_header_size`` -+ - Compressed header size in bytes. -+ * - __u16 -+ - ``uncompressed_header_size`` -+ - Uncompressed header size in bytes. -+ * - __u16 -+ - ``frame_width_minus_1`` -+ - Add 1 to get the frame width expressed in pixels. See section 7.2.3 in :ref:`vp9`. -+ * - __u16 -+ - ``frame_height_minus_1`` -+ - Add 1 to get the frame height expressed in pixels. See section 7.2.3 in :ref:`vp9`. -+ * - __u16 -+ - ``render_width_minus_1`` -+ - Add 1 to get the expected render width expressed in pixels. This is -+ not used during the decoding process but might be used by HW scalers to -+ prepare a frame that's ready for scanout. See section 7.2.4 in :ref:`vp9`. -+ * - __u16 -+ - render_height_minus_1 -+ - Add 1 to get the expected render height expressed in pixels. This is -+ not used during the decoding process but might be used by HW scalers to -+ prepare a frame that's ready for scanout. See section 7.2.4 in :ref:`vp9`. -+ * - __u64 -+ - ``last_frame_ts`` -+ - "last" reference buffer timestamp. -+ The timestamp refers to the ``timestamp`` field in -+ struct :c:type:`v4l2_buffer`. Use the :c:func:`v4l2_timeval_to_ns()` -+ function to convert the struct :c:type:`timeval` in struct -+ :c:type:`v4l2_buffer` to a __u64. -+ * - __u64 -+ - ``golden_frame_ts`` -+ - "golden" reference buffer timestamp. -+ The timestamp refers to the ``timestamp`` field in -+ struct :c:type:`v4l2_buffer`. Use the :c:func:`v4l2_timeval_to_ns()` -+ function to convert the struct :c:type:`timeval` in struct -+ :c:type:`v4l2_buffer` to a __u64. -+ * - __u64 -+ - ``alt_frame_ts`` -+ - "alt" reference buffer timestamp. -+ The timestamp refers to the ``timestamp`` field in -+ struct :c:type:`v4l2_buffer`. Use the :c:func:`v4l2_timeval_to_ns()` -+ function to convert the struct :c:type:`timeval` in struct -+ :c:type:`v4l2_buffer` to a __u64. -+ * - __u8 -+ - ``ref_frame_sign_bias`` -+ - a bitfield specifying whether the sign bias is set for a given -+ reference frame. See :ref:`Reference Frame Sign Bias` -+ for more details. -+ * - __u8 -+ - ``reset_frame_context`` -+ - specifies whether the frame context should be reset to default values. See -+ :ref:`Reset Frame Context` for more details. -+ * - __u8 -+ - ``frame_context_idx`` -+ - Frame context that should be used/updated. -+ * - __u8 -+ - ``profile`` -+ - VP9 profile. Can be 0, 1, 2 or 3. -+ * - __u8 -+ - ``bit_depth`` -+ - Component depth in bits. Can be 8, 10 or 12. Note that not all profiles -+ support 10 and/or 12 bits depths. -+ * - __u8 -+ - ``interpolation_filter`` -+ - Specifies the filter selection used for performing inter prediction. See -+ :ref:`Interpolation Filter` for more details. -+ * - __u8 -+ - ``tile_cols_log2`` -+ - Specifies the base 2 logarithm of the width of each tile (where the -+ width is measured in units of 8x8 blocks). Shall be less than or equal -+ to 6. -+ * - __u8 -+ - ``tile_rows_log2`` -+ - Specifies the base 2 logarithm of the height of each tile (where the -+ height is measured in units of 8x8 blocks). -+ * - __u8 -+ - ``reference_mode`` -+ - Specifies the type of inter prediction to be used. See -+ :ref:`Reference Mode` for more details. -+ * - __u8 -+ - ``reserved[7]`` -+ - Applications and drivers must set this to zero. -+ -+.. raw:: latex -+ -+ \normalsize -+ -+.. _vp9_frame_flags: -+ -+``Frame Flags`` -+ -+.. tabularcolumns:: |p{10.0cm}|p{1.2cm}|p{6.1cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_FRAME_FLAG_KEY_FRAME`` -+ - 0x001 -+ - The frame is a key frame. -+ * - ``V4L2_VP9_FRAME_FLAG_SHOW_FRAME`` -+ - 0x002 -+ - The frame should be displayed. -+ * - ``V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT`` -+ - 0x004 -+ - The decoding should be error resilient. -+ * - ``V4L2_VP9_FRAME_FLAG_INTRA_ONLY`` -+ - 0x008 -+ - The frame does not reference other frames. -+ * - ``V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV`` -+ - 0x010 -+ - The frame can use high precision motion vectors. -+ * - ``V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX`` -+ - 0x020 -+ - Frame context should be updated after decoding. -+ * - ``V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE`` -+ - 0x040 -+ - Parallel decoding is used. -+ * - ``V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING`` -+ - 0x080 -+ - Vertical subsampling is enabled. -+ * - ``V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING`` -+ - 0x100 -+ - Horizontal subsampling is enabled. -+ * - ``V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING`` -+ - 0x200 -+ - The full UV range is used. -+ -+.. _vp9_ref_frame_sign_bias: -+ -+``Reference Frame Sign Bias`` -+ -+.. tabularcolumns:: |p{7.0cm}|p{1.2cm}|p{9.1cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_SIGN_BIAS_LAST`` -+ - 0x1 -+ - Sign bias is set for the last reference frame. -+ * - ``V4L2_VP9_SIGN_BIAS_GOLDEN`` -+ - 0x2 -+ - Sign bias is set for the golden reference frame. -+ * - ``V4L2_VP9_SIGN_BIAS_ALT`` -+ - 0x2 -+ - Sign bias is set for the alt reference frame. -+ -+.. _vp9_reset_frame_context: -+ -+``Reset Frame Context`` -+ -+.. tabularcolumns:: |p{7.0cm}|p{1.2cm}|p{9.1cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_RESET_FRAME_CTX_NONE`` -+ - 0 -+ - Do not reset any frame context. -+ * - ``V4L2_VP9_RESET_FRAME_CTX_SPEC`` -+ - 1 -+ - Reset the frame context pointed to by -+ :c:type:`v4l2_ctrl_vp9_frame`.frame_context_idx. -+ * - ``V4L2_VP9_RESET_FRAME_CTX_ALL`` -+ - 2 -+ - Reset all frame contexts. -+ -+See section '7.2 Uncompressed header semantics' of the :ref:`vp9` specification -+for more details. -+ -+.. _vp9_interpolation_filter: -+ -+``Interpolation Filter`` -+ -+.. tabularcolumns:: |p{9.0cm}|p{1.2cm}|p{7.1cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_INTERP_FILTER_EIGHTTAP`` -+ - 0 -+ - Eight tap filter. -+ * - ``V4L2_VP9_INTERP_FILTER_EIGHTTAP_SMOOTH`` -+ - 1 -+ - Eight tap smooth filter. -+ * - ``V4L2_VP9_INTERP_FILTER_EIGHTTAP_SHARP`` -+ - 2 -+ - Eeight tap sharp filter. -+ * - ``V4L2_VP9_INTERP_FILTER_BILINEAR`` -+ - 3 -+ - Bilinear filter. -+ * - ``V4L2_VP9_INTERP_FILTER_SWITCHABLE`` -+ - 4 -+ - Filter selection is signaled at the block level. -+ -+See section '7.2.7 Interpolation filter semantics' of the :ref:`vp9` specification -+for more details. -+ -+.. _vp9_reference_mode: -+ -+``Reference Mode`` -+ -+.. tabularcolumns:: |p{9.6cm}|p{0.5cm}|p{7.2cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_REFERENCE_MODE_SINGLE_REFERENCE`` -+ - 0 -+ - Indicates that all the inter blocks use only a single reference frame -+ to generate motion compensated prediction. -+ * - ``V4L2_VP9_REFERENCE_MODE_COMPOUND_REFERENCE`` -+ - 1 -+ - Requires all the inter blocks to use compound mode. Single reference -+ frame prediction is not allowed. -+ * - ``V4L2_VP9_REFERENCE_MODE_SELECT`` -+ - 2 -+ - Allows each individual inter block to select between single and -+ compound prediction modes. -+ -+See section '7.3.6 Frame reference mode semantics' of the :ref:`vp9` specification for more details. -+ -+.. c:type:: v4l2_vp9_segmentation -+ -+Encodes the quantization parameters. See section '7.2.10 Segmentation -+params syntax' of the :ref:`vp9` specification for more details. -+ -+.. tabularcolumns:: |p{0.8cm}|p{5cm}|p{11.4cm}| -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_vp9_segmentation -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``feature_data[8][4]`` -+ - Data attached to each feature. Data entry is only valid if the feature -+ is enabled. The array shall be indexed with segment number as the first dimension -+ (0..7) and one of V4L2_VP9_SEG_* as the second dimension. -+ See :ref:`Segment Feature IDs`. -+ * - __u8 -+ - ``feature_enabled[8]`` -+ - Bitmask defining which features are enabled in each segment. The value for each -+ segment is a combination of V4L2_VP9_SEGMENT_FEATURE_ENABLED(id) values where id is -+ one of V4L2_VP9_SEG_*. See :ref:`Segment Feature IDs`. -+ * - __u8 -+ - ``tree_probs[7]`` -+ - Specifies the probability values to be used when decoding a Segment-ID. -+ See '5.15. Segmentation map' section of :ref:`vp9` for more details. -+ * - __u8 -+ - ``pred_probs[3]`` -+ - Specifies the probability values to be used when decoding a -+ Predicted-Segment-ID. See '6.4.14. Get segment id syntax' -+ section of :ref:`vp9` for more details. -+ * - __u8 -+ - ``flags`` -+ - Combination of V4L2_VP9_SEGMENTATION_FLAG_* flags. See -+ :ref:`Segmentation Flags`. -+ * - __u8 -+ - ``reserved[5]`` -+ - Applications and drivers must set this to zero. -+ -+.. _vp9_segment_feature: -+ -+``Segment feature IDs`` -+ -+.. tabularcolumns:: |p{6.0cm}|p{1cm}|p{10.3cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_SEG_LVL_ALT_Q`` -+ - 0 -+ - Quantizer segment feature. -+ * - ``V4L2_VP9_SEG_LVL_ALT_L`` -+ - 1 -+ - Loop filter segment feature. -+ * - ``V4L2_VP9_SEG_LVL_REF_FRAME`` -+ - 2 -+ - Reference frame segment feature. -+ * - ``V4L2_VP9_SEG_LVL_SKIP`` -+ - 3 -+ - Skip segment feature. -+ * - ``V4L2_VP9_SEG_LVL_MAX`` -+ - 4 -+ - Number of segment features. -+ -+.. _vp9_segmentation_flags: -+ -+``Segmentation Flags`` -+ -+.. tabularcolumns:: |p{10.6cm}|p{0.8cm}|p{5.9cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_SEGMENTATION_FLAG_ENABLED`` -+ - 0x01 -+ - Indicates that this frame makes use of the segmentation tool. -+ * - ``V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP`` -+ - 0x02 -+ - Indicates that the segmentation map should be updated during the -+ decoding of this frame. -+ * - ``V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE`` -+ - 0x04 -+ - Indicates that the updates to the segmentation map are coded -+ relative to the existing segmentation map. -+ * - ``V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA`` -+ - 0x08 -+ - Indicates that new parameters are about to be specified for each -+ segment. -+ * - ``V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE`` -+ - 0x10 -+ - Indicates that the segmentation parameters represent the actual values -+ to be used. -+ -+.. c:type:: v4l2_vp9_quantization -+ -+Encodes the quantization parameters. See section '7.2.9 Quantization params -+syntax' of the VP9 specification for more details. -+ -+.. tabularcolumns:: |p{0.8cm}|p{4cm}|p{12.4cm}| -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_vp9_quantization -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``base_q_idx`` -+ - Indicates the base frame qindex. -+ * - __s8 -+ - ``delta_q_y_dc`` -+ - Indicates the Y DC quantizer relative to base_q_idx. -+ * - __s8 -+ - ``delta_q_uv_dc`` -+ - Indicates the UV DC quantizer relative to base_q_idx. -+ * - __s8 -+ - ``delta_q_uv_ac`` -+ - Indicates the UV AC quantizer relative to base_q_idx. -+ * - __u8 -+ - ``reserved[4]`` -+ - Applications and drivers must set this to zero. -+ -+.. c:type:: v4l2_vp9_loop_filter -+ -+This structure contains all loop filter related parameters. See sections -+'7.2.8 Loop filter semantics' of the :ref:`vp9` specification for more details. -+ -+.. tabularcolumns:: |p{0.8cm}|p{4cm}|p{12.4cm}| -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_vp9_loop_filter -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __s8 -+ - ``ref_deltas[4]`` -+ - Contains the adjustment needed for the filter level based on the chosen -+ reference frame. -+ * - __s8 -+ - ``mode_deltas[2]`` -+ - Contains the adjustment needed for the filter level based on the chosen -+ mode. -+ * - __u8 -+ - ``level`` -+ - Indicates the loop filter strength. -+ * - __u8 -+ - ``sharpness`` -+ - Indicates the sharpness level. -+ * - __u8 -+ - ``flags`` -+ - Combination of V4L2_VP9_LOOP_FILTER_FLAG_* flags. -+ See :ref:`Loop Filter Flags `. -+ * - __u8 -+ - ``reserved[7]`` -+ - Applications and drivers must set this to zero. -+ -+ -+.. _vp9_loop_filter_flags: -+ -+``Loop Filter Flags`` -+ -+.. tabularcolumns:: |p{9.6cm}|p{0.5cm}|p{7.2cm}| -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED`` -+ - 0x1 -+ - When set, the filter level depends on the mode and reference frame used -+ to predict a block. -+ * - ``V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE`` -+ - 0x2 -+ - When set, the bitstream contains additional syntax elements that -+ specify which mode and reference frame deltas are to be updated. -diff --git a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -index 0ede39907ee2..967fc803ef94 100644 ---- a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -+++ b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -@@ -172,6 +172,21 @@ Compressed Formats - - VP9 compressed video frame. The encoder generates one - compressed frame per buffer, and the decoder requires one - compressed frame per buffer. -+ * .. _V4L2-PIX-FMT-VP9-FRAME: -+ -+ - ``V4L2_PIX_FMT_VP9_FRAME`` -+ - 'VP9F' -+ - VP9 parsed frame, including the frame header, as extracted from the container. -+ This format is adapted for stateless video decoders that implement a -+ VP9 pipeline with the :ref:`stateless_decoder`. -+ Metadata associated with the frame to decode is required to be passed -+ through the ``V4L2_CID_STATELESS_VP9_FRAME`` and -+ the ``V4L2_CID_STATELESS_VP9_COMPRESSED_HDR`` controls. -+ See the :ref:`associated Codec Control IDs `. -+ Exactly one output and one capture buffer must be provided for use with -+ this pixel format. The output buffer must contain the appropriate number -+ of macroblocks to decode a full corresponding frame to the matching -+ capture buffer. - * .. _V4L2-PIX-FMT-HEVC: - - - ``V4L2_PIX_FMT_HEVC`` -diff --git a/Documentation/userspace-api/media/v4l/vidioc-g-ext-ctrls.rst b/Documentation/userspace-api/media/v4l/vidioc-g-ext-ctrls.rst -index fdde0ae6d521..29971a45a2d4 100644 ---- a/Documentation/userspace-api/media/v4l/vidioc-g-ext-ctrls.rst -+++ b/Documentation/userspace-api/media/v4l/vidioc-g-ext-ctrls.rst -@@ -233,6 +233,14 @@ still cause this situation. - - ``p_mpeg2_quantisation`` - - A pointer to a struct :c:type:`v4l2_ctrl_mpeg2_quantisation`. Valid if this control is - of type ``V4L2_CTRL_TYPE_MPEG2_QUANTISATION``. -+ * - struct :c:type:`v4l2_ctrl_vp9_compressed_hdr` * -+ - ``p_vp9_compressed_hdr_probs`` -+ - A pointer to a struct :c:type:`v4l2_ctrl_vp9_compressed_hdr`. Valid if this -+ control is of type ``V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR``. -+ * - struct :c:type:`v4l2_ctrl_vp9_frame` * -+ - ``p_vp9_frame`` -+ - A pointer to a struct :c:type:`v4l2_ctrl_vp9_frame`. Valid if this -+ control is of type ``V4L2_CTRL_TYPE_VP9_FRAME``. - * - struct :c:type:`v4l2_ctrl_hdr10_cll_info` * - - ``p_hdr10_cll`` - - A pointer to a struct :c:type:`v4l2_ctrl_hdr10_cll_info`. Valid if this control is -diff --git a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst -index 2f491c17dd5d..88f630252d98 100644 ---- a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst -+++ b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst -@@ -513,6 +513,18 @@ See also the examples in :ref:`control`. - - n/a - - A struct :c:type:`v4l2_ctrl_hevc_decode_params`, containing HEVC - decoding parameters for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_vp9_compressed_hdr`, containing VP9 -+ probabilities updates for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_VP9_FRAME`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_vp9_frame`, containing VP9 -+ frame decode parameters for stateless video decoders. - - .. raw:: latex - -diff --git a/Documentation/userspace-api/media/videodev2.h.rst.exceptions b/Documentation/userspace-api/media/videodev2.h.rst.exceptions -index eb0b1cd37abd..9cbb7a0c354a 100644 ---- a/Documentation/userspace-api/media/videodev2.h.rst.exceptions -+++ b/Documentation/userspace-api/media/videodev2.h.rst.exceptions -@@ -149,6 +149,8 @@ replace symbol V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_AREA :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_FWHT_PARAMS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_VP8_FRAME :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_VP9_FRAME :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_HDR10_CLL_INFO :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_HDR10_MASTERING_DISPLAY :c:type:`v4l2_ctrl_type` - -diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c -index 70adfc1b9c81..54abe5245dcc 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls-core.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c -@@ -283,6 +283,12 @@ static void std_log(const struct v4l2_ctrl *ctrl) - case V4L2_CTRL_TYPE_MPEG2_PICTURE: - pr_cont("MPEG2_PICTURE"); - break; -+ case V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR: -+ pr_cont("VP9_COMPRESSED_HDR"); -+ break; -+ case V4L2_CTRL_TYPE_VP9_FRAME: -+ pr_cont("VP9_FRAME"); -+ break; - default: - pr_cont("unknown type %d", ctrl->type); - break; -@@ -317,6 +323,168 @@ static void std_log(const struct v4l2_ctrl *ctrl) - #define zero_reserved(s) \ - memset(&(s).reserved, 0, sizeof((s).reserved)) - -+static int -+validate_vp9_lf_params(struct v4l2_vp9_loop_filter *lf) -+{ -+ unsigned int i; -+ -+ if (lf->flags & ~(V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED | -+ V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE)) -+ return -EINVAL; -+ -+ /* That all values are in the accepted range. */ -+ if (lf->level > GENMASK(5, 0)) -+ return -EINVAL; -+ -+ if (lf->sharpness > GENMASK(2, 0)) -+ return -EINVAL; -+ -+ for (i = 0; i < ARRAY_SIZE(lf->ref_deltas); i++) -+ if (lf->ref_deltas[i] < -63 || lf->ref_deltas[i] > 63) -+ return -EINVAL; -+ -+ for (i = 0; i < ARRAY_SIZE(lf->mode_deltas); i++) -+ if (lf->mode_deltas[i] < -63 || lf->mode_deltas[i] > 63) -+ return -EINVAL; -+ -+ zero_reserved(*lf); -+ return 0; -+} -+ -+static int -+validate_vp9_quant_params(struct v4l2_vp9_quantization *quant) -+{ -+ if (quant->delta_q_y_dc < -15 || quant->delta_q_y_dc > 15 || -+ quant->delta_q_uv_dc < -15 || quant->delta_q_uv_dc > 15 || -+ quant->delta_q_uv_ac < -15 || quant->delta_q_uv_ac > 15) -+ return -EINVAL; -+ -+ zero_reserved(*quant); -+ return 0; -+} -+ -+static int -+validate_vp9_seg_params(struct v4l2_vp9_segmentation *seg) -+{ -+ unsigned int i, j; -+ -+ if (seg->flags & ~(V4L2_VP9_SEGMENTATION_FLAG_ENABLED | -+ V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP | -+ V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE | -+ V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA | -+ V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE)) -+ return -EINVAL; -+ -+ for (i = 0; i < ARRAY_SIZE(seg->feature_enabled); i++) { -+ if (seg->feature_enabled[i] & -+ ~V4L2_VP9_SEGMENT_FEATURE_ENABLED_MASK) -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(seg->feature_data); i++) { -+ const int range[] = { 255, 63, 3, 0 }; -+ -+ for (j = 0; j < ARRAY_SIZE(seg->feature_data[j]); j++) { -+ if (seg->feature_data[i][j] < -range[j] || -+ seg->feature_data[i][j] > range[j]) -+ return -EINVAL; -+ } -+ } -+ -+ zero_reserved(*seg); -+ return 0; -+} -+ -+static int -+validate_vp9_compressed_hdr(struct v4l2_ctrl_vp9_compressed_hdr *hdr) -+{ -+ if (hdr->tx_mode > V4L2_VP9_TX_MODE_SELECT) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static int -+validate_vp9_frame(struct v4l2_ctrl_vp9_frame *frame) -+{ -+ int ret; -+ -+ /* Make sure we're not passed invalid flags. */ -+ if (frame->flags & ~(V4L2_VP9_FRAME_FLAG_KEY_FRAME | -+ V4L2_VP9_FRAME_FLAG_SHOW_FRAME | -+ V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT | -+ V4L2_VP9_FRAME_FLAG_INTRA_ONLY | -+ V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV | -+ V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX | -+ V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE | -+ V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING | -+ V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING | -+ V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING)) -+ return -EINVAL; -+ -+ if (frame->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT && -+ frame->flags & V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX) -+ return -EINVAL; -+ -+ if (frame->profile > V4L2_VP9_PROFILE_MAX) -+ return -EINVAL; -+ -+ if (frame->reset_frame_context > V4L2_VP9_RESET_FRAME_CTX_ALL) -+ return -EINVAL; -+ -+ if (frame->frame_context_idx >= V4L2_VP9_NUM_FRAME_CTX) -+ return -EINVAL; -+ -+ /* -+ * Profiles 0 and 1 only support 8-bit depth, profiles 2 and 3 only 10 -+ * and 12 bit depths. -+ */ -+ if ((frame->profile < 2 && frame->bit_depth != 8) || -+ (frame->profile >= 2 && -+ (frame->bit_depth != 10 && frame->bit_depth != 12))) -+ return -EINVAL; -+ -+ /* Profile 0 and 2 only accept YUV 4:2:0. */ -+ if ((frame->profile == 0 || frame->profile == 2) && -+ (!(frame->flags & V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING) || -+ !(frame->flags & V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING))) -+ return -EINVAL; -+ -+ /* Profile 1 and 3 only accept YUV 4:2:2, 4:4:0 and 4:4:4. */ -+ if ((frame->profile == 1 || frame->profile == 3) && -+ ((frame->flags & V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING) && -+ (frame->flags & V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING))) -+ return -EINVAL; -+ -+ if (frame->interpolation_filter > V4L2_VP9_INTERP_FILTER_SWITCHABLE) -+ return -EINVAL; -+ -+ /* -+ * According to the spec, tile_cols_log2 shall be less than or equal -+ * to 6. -+ */ -+ if (frame->tile_cols_log2 > 6) -+ return -EINVAL; -+ -+ if (frame->reference_mode > V4L2_VP9_REFERENCE_MODE_SELECT) -+ return -EINVAL; -+ -+ ret = validate_vp9_lf_params(&frame->lf); -+ if (ret) -+ return ret; -+ -+ ret = validate_vp9_quant_params(&frame->quant); -+ if (ret) -+ return ret; -+ -+ ret = validate_vp9_seg_params(&frame->seg); -+ if (ret) -+ return ret; -+ -+ zero_reserved(*frame); -+ return 0; -+} -+ - /* - * Compound controls validation requires setting unused fields/flags to zero - * in order to properly detect unchanged controls with std_equal's memcmp. -@@ -690,6 +858,12 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, - case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: - break; - -+ case V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR: -+ return validate_vp9_compressed_hdr(p); -+ -+ case V4L2_CTRL_TYPE_VP9_FRAME: -+ return validate_vp9_frame(p); -+ - case V4L2_CTRL_TYPE_AREA: - area = p; - if (!area->width || !area->height) -@@ -1255,6 +1429,12 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, - case V4L2_CTRL_TYPE_HDR10_MASTERING_DISPLAY: - elem_size = sizeof(struct v4l2_ctrl_hdr10_mastering_display); - break; -+ case V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR: -+ elem_size = sizeof(struct v4l2_ctrl_vp9_compressed_hdr); -+ break; -+ case V4L2_CTRL_TYPE_VP9_FRAME: -+ elem_size = sizeof(struct v4l2_ctrl_vp9_frame); -+ break; - case V4L2_CTRL_TYPE_AREA: - elem_size = sizeof(struct v4l2_area); - break; -diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c -index ebe82b6ba6e6..23594568b985 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c -@@ -1177,6 +1177,8 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_STATELESS_MPEG2_SEQUENCE: return "MPEG-2 Sequence Header"; - case V4L2_CID_STATELESS_MPEG2_PICTURE: return "MPEG-2 Picture Header"; - case V4L2_CID_STATELESS_MPEG2_QUANTISATION: return "MPEG-2 Quantisation Matrices"; -+ case V4L2_CID_STATELESS_VP9_COMPRESSED_HDR: return "VP9 Probabilities Updates"; -+ case V4L2_CID_STATELESS_VP9_FRAME: return "VP9 Frame Decode Parameters"; - - /* Colorimetry controls */ - /* Keep the order of the 'case's the same as in v4l2-controls.h! */ -@@ -1498,6 +1500,12 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - case V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS: - *type = V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS; - break; -+ case V4L2_CID_STATELESS_VP9_COMPRESSED_HDR: -+ *type = V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR; -+ break; -+ case V4L2_CID_STATELESS_VP9_FRAME: -+ *type = V4L2_CTRL_TYPE_VP9_FRAME; -+ break; - case V4L2_CID_UNIT_CELL_SIZE: - *type = V4L2_CTRL_TYPE_AREA; - *flags |= V4L2_CTRL_FLAG_READ_ONLY; -diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c -index 31d0109ce5a8..51289d4741dc 100644 ---- a/drivers/media/v4l2-core/v4l2-ioctl.c -+++ b/drivers/media/v4l2-core/v4l2-ioctl.c -@@ -1413,6 +1413,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt) - case V4L2_PIX_FMT_VP8: descr = "VP8"; break; - case V4L2_PIX_FMT_VP8_FRAME: descr = "VP8 Frame"; break; - case V4L2_PIX_FMT_VP9: descr = "VP9"; break; -+ case V4L2_PIX_FMT_VP9_FRAME: descr = "VP9 Frame"; break; - case V4L2_PIX_FMT_HEVC: descr = "HEVC"; break; /* aka H.265 */ - case V4L2_PIX_FMT_HEVC_SLICE: descr = "HEVC Parsed Slice Data"; break; - case V4L2_PIX_FMT_FWHT: descr = "FWHT"; break; /* used in vicodec */ -diff --git a/include/media/v4l2-ctrls.h b/include/media/v4l2-ctrls.h -index 575b59fbac77..b3ce438f1329 100644 ---- a/include/media/v4l2-ctrls.h -+++ b/include/media/v4l2-ctrls.h -@@ -50,6 +50,8 @@ struct video_device; - * @p_h264_decode_params: Pointer to a struct v4l2_ctrl_h264_decode_params. - * @p_h264_pred_weights: Pointer to a struct v4l2_ctrl_h264_pred_weights. - * @p_vp8_frame: Pointer to a VP8 frame params structure. -+ * @p_vp9_compressed_hdr_probs: Pointer to a VP9 frame compressed header probs structure. -+ * @p_vp9_frame: Pointer to a VP9 frame params structure. - * @p_hevc_sps: Pointer to an HEVC sequence parameter set structure. - * @p_hevc_pps: Pointer to an HEVC picture parameter set structure. - * @p_hevc_slice_params: Pointer to an HEVC slice parameters structure. -@@ -80,6 +82,8 @@ union v4l2_ctrl_ptr { - struct v4l2_ctrl_hevc_sps *p_hevc_sps; - struct v4l2_ctrl_hevc_pps *p_hevc_pps; - struct v4l2_ctrl_hevc_slice_params *p_hevc_slice_params; -+ struct v4l2_ctrl_vp9_compressed_hdr *p_vp9_compressed_hdr_probs; -+ struct v4l2_ctrl_vp9_frame *p_vp9_frame; - struct v4l2_ctrl_hdr10_cll_info *p_hdr10_cll; - struct v4l2_ctrl_hdr10_mastering_display *p_hdr10_mastering; - struct v4l2_area *p_area; -diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h -index 5fea5feb0412..f859b73f0490 100644 ---- a/include/uapi/linux/v4l2-controls.h -+++ b/include/uapi/linux/v4l2-controls.h -@@ -2016,6 +2016,290 @@ struct v4l2_ctrl_hdr10_mastering_display { - __u32 min_display_mastering_luminance; - }; - -+/* Stateless VP9 controls */ -+ -+#define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED 0x1 -+#define V4L2_VP9_LOOP_FILTER_FLAG_DELTA_UPDATE 0x2 -+ -+/** -+ * struct v4l2_vp9_loop_filter - VP9 loop filter parameters -+ * -+ * @ref_deltas: contains the adjustment needed for the filter level based on the -+ * chosen reference frame. If this syntax element is not present in the bitstream, -+ * users should pass its last value. -+ * @mode_deltas: contains the adjustment needed for the filter level based on the -+ * chosen mode. If this syntax element is not present in the bitstream, users should -+ * pass its last value. -+ * @level: indicates the loop filter strength. -+ * @sharpness: indicates the sharpness level. -+ * @flags: combination of V4L2_VP9_LOOP_FILTER_FLAG_{} flags. -+ * @reserved: padding field. Should be zeroed by applications. -+ * -+ * This structure contains all loop filter related parameters. See sections -+ * '7.2.8 Loop filter semantics' of the VP9 specification for more details. -+ */ -+struct v4l2_vp9_loop_filter { -+ __s8 ref_deltas[4]; -+ __s8 mode_deltas[2]; -+ __u8 level; -+ __u8 sharpness; -+ __u8 flags; -+ __u8 reserved[7]; -+}; -+ -+/** -+ * struct v4l2_vp9_quantization - VP9 quantization parameters -+ * -+ * @base_q_idx: indicates the base frame qindex. -+ * @delta_q_y_dc: indicates the Y DC quantizer relative to base_q_idx. -+ * @delta_q_uv_dc: indicates the UV DC quantizer relative to base_q_idx. -+ * @delta_q_uv_ac: indicates the UV AC quantizer relative to base_q_idx. -+ * @reserved: padding field. Should be zeroed by applications. -+ * -+ * Encodes the quantization parameters. See section '7.2.9 Quantization params -+ * syntax' of the VP9 specification for more details. -+ */ -+struct v4l2_vp9_quantization { -+ __u8 base_q_idx; -+ __s8 delta_q_y_dc; -+ __s8 delta_q_uv_dc; -+ __s8 delta_q_uv_ac; -+ __u8 reserved[4]; -+}; -+ -+#define V4L2_VP9_SEGMENTATION_FLAG_ENABLED 0x01 -+#define V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP 0x02 -+#define V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE 0x04 -+#define V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA 0x08 -+#define V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE 0x10 -+ -+#define V4L2_VP9_SEG_LVL_ALT_Q 0 -+#define V4L2_VP9_SEG_LVL_ALT_L 1 -+#define V4L2_VP9_SEG_LVL_REF_FRAME 2 -+#define V4L2_VP9_SEG_LVL_SKIP 3 -+#define V4L2_VP9_SEG_LVL_MAX 4 -+ -+#define V4L2_VP9_SEGMENT_FEATURE_ENABLED(id) (1 << (id)) -+#define V4L2_VP9_SEGMENT_FEATURE_ENABLED_MASK 0xf -+ -+/** -+ * struct v4l2_vp9_segmentation - VP9 segmentation parameters -+ * -+ * @feature_data: data attached to each feature. Data entry is only valid if -+ * the feature is enabled. The array shall be indexed with segment number as -+ * the first dimension (0..7) and one of V4L2_VP9_SEG_{} as the second dimension. -+ * @feature_enabled: bitmask defining which features are enabled in each segment. -+ * The value for each segment is a combination of V4L2_VP9_SEGMENT_FEATURE_ENABLED(id) -+ * values where id is one of V4L2_VP9_SEG_LVL_{}. -+ * @tree_probs: specifies the probability values to be used when decoding a -+ * Segment-ID. See '5.15. Segmentation map' section of the VP9 specification -+ * for more details. -+ * @pred_probs: specifies the probability values to be used when decoding a -+ * Predicted-Segment-ID. See '6.4.14. Get segment id syntax' section of :ref:`vp9` -+ * for more details. -+ * @flags: combination of V4L2_VP9_SEGMENTATION_FLAG_{} flags. -+ * @reserved: padding field. Should be zeroed by applications. -+ * -+ * Encodes the quantization parameters. See section '7.2.10 Segmentation params syntax' of -+ * the VP9 specification for more details. -+ */ -+struct v4l2_vp9_segmentation { -+ __s16 feature_data[8][4]; -+ __u8 feature_enabled[8]; -+ __u8 tree_probs[7]; -+ __u8 pred_probs[3]; -+ __u8 flags; -+ __u8 reserved[5]; -+}; -+ -+#define V4L2_VP9_FRAME_FLAG_KEY_FRAME 0x001 -+#define V4L2_VP9_FRAME_FLAG_SHOW_FRAME 0x002 -+#define V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT 0x004 -+#define V4L2_VP9_FRAME_FLAG_INTRA_ONLY 0x008 -+#define V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV 0x010 -+#define V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX 0x020 -+#define V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE 0x040 -+#define V4L2_VP9_FRAME_FLAG_X_SUBSAMPLING 0x080 -+#define V4L2_VP9_FRAME_FLAG_Y_SUBSAMPLING 0x100 -+#define V4L2_VP9_FRAME_FLAG_COLOR_RANGE_FULL_SWING 0x200 -+ -+#define V4L2_VP9_SIGN_BIAS_LAST 0x1 -+#define V4L2_VP9_SIGN_BIAS_GOLDEN 0x2 -+#define V4L2_VP9_SIGN_BIAS_ALT 0x4 -+ -+#define V4L2_VP9_RESET_FRAME_CTX_NONE 0 -+#define V4L2_VP9_RESET_FRAME_CTX_SPEC 1 -+#define V4L2_VP9_RESET_FRAME_CTX_ALL 2 -+ -+#define V4L2_VP9_INTERP_FILTER_EIGHTTAP 0 -+#define V4L2_VP9_INTERP_FILTER_EIGHTTAP_SMOOTH 1 -+#define V4L2_VP9_INTERP_FILTER_EIGHTTAP_SHARP 2 -+#define V4L2_VP9_INTERP_FILTER_BILINEAR 3 -+#define V4L2_VP9_INTERP_FILTER_SWITCHABLE 4 -+ -+#define V4L2_VP9_REFERENCE_MODE_SINGLE_REFERENCE 0 -+#define V4L2_VP9_REFERENCE_MODE_COMPOUND_REFERENCE 1 -+#define V4L2_VP9_REFERENCE_MODE_SELECT 2 -+ -+#define V4L2_VP9_PROFILE_MAX 3 -+ -+#define V4L2_CID_STATELESS_VP9_FRAME (V4L2_CID_CODEC_STATELESS_BASE + 300) -+/** -+ * struct v4l2_ctrl_vp9_frame - VP9 frame decoding control -+ * -+ * @lf: loop filter parameters. See &v4l2_vp9_loop_filter for more details. -+ * @quant: quantization parameters. See &v4l2_vp9_quantization for more details. -+ * @seg: segmentation parameters. See &v4l2_vp9_segmentation for more details. -+ * @flags: combination of V4L2_VP9_FRAME_FLAG_{} flags. -+ * @compressed_header_size: compressed header size in bytes. -+ * @uncompressed_header_size: uncompressed header size in bytes. -+ * @frame_width_minus_1: add 1 to it and you'll get the frame width expressed in pixels. -+ * @frame_height_minus_1: add 1 to it and you'll get the frame height expressed in pixels. -+ * @render_width_minus_1: add 1 to it and you'll get the expected render width expressed in -+ * pixels. This is not used during the decoding process but might be used by HW scalers -+ * to prepare a frame that's ready for scanout. -+ * @render_height_minus_1: add 1 to it and you'll get the expected render height expressed in -+ * pixels. This is not used during the decoding process but might be used by HW scalers -+ * to prepare a frame that's ready for scanout. -+ * @last_frame_ts: "last" reference buffer timestamp. -+ * The timestamp refers to the timestamp field in struct v4l2_buffer. -+ * Use v4l2_timeval_to_ns() to convert the struct timeval to a __u64. -+ * @golden_frame_ts: "golden" reference buffer timestamp. -+ * The timestamp refers to the timestamp field in struct v4l2_buffer. -+ * Use v4l2_timeval_to_ns() to convert the struct timeval to a __u64. -+ * @alt_frame_ts: "alt" reference buffer timestamp. -+ * The timestamp refers to the timestamp field in struct v4l2_buffer. -+ * Use v4l2_timeval_to_ns() to convert the struct timeval to a __u64. -+ * @ref_frame_sign_bias: a bitfield specifying whether the sign bias is set for a given -+ * reference frame. Either of V4L2_VP9_SIGN_BIAS_{}. -+ * @reset_frame_context: specifies whether the frame context should be reset to default values. -+ * Either of V4L2_VP9_RESET_FRAME_CTX_{}. -+ * @frame_context_idx: frame context that should be used/updated. -+ * @profile: VP9 profile. Can be 0, 1, 2 or 3. -+ * @bit_depth: bits per components. Can be 8, 10 or 12. Note that not all profiles support -+ * 10 and/or 12 bits depths. -+ * @interpolation_filter: specifies the filter selection used for performing inter prediction. -+ * Set to one of V4L2_VP9_INTERP_FILTER_{}. -+ * @tile_cols_log2: specifies the base 2 logarithm of the width of each tile (where the width -+ * is measured in units of 8x8 blocks). Shall be less than or equal to 6. -+ * @tile_rows_log2: specifies the base 2 logarithm of the height of each tile (where the height -+ * is measured in units of 8x8 blocks). -+ * @reference_mode: specifies the type of inter prediction to be used. -+ * Set to one of V4L2_VP9_REFERENCE_MODE_{}. -+ * @reserved: padding field. Should be zeroed by applications. -+ */ -+struct v4l2_ctrl_vp9_frame { -+ struct v4l2_vp9_loop_filter lf; -+ struct v4l2_vp9_quantization quant; -+ struct v4l2_vp9_segmentation seg; -+ __u32 flags; -+ __u16 compressed_header_size; -+ __u16 uncompressed_header_size; -+ __u16 frame_width_minus_1; -+ __u16 frame_height_minus_1; -+ __u16 render_width_minus_1; -+ __u16 render_height_minus_1; -+ __u64 last_frame_ts; -+ __u64 golden_frame_ts; -+ __u64 alt_frame_ts; -+ __u8 ref_frame_sign_bias; -+ __u8 reset_frame_context; -+ __u8 frame_context_idx; -+ __u8 profile; -+ __u8 bit_depth; -+ __u8 interpolation_filter; -+ __u8 tile_cols_log2; -+ __u8 tile_rows_log2; -+ __u8 reference_mode; -+ __u8 reserved[7]; -+}; -+ -+#define V4L2_VP9_NUM_FRAME_CTX 4 -+ -+/** -+ * struct v4l2_vp9_mv_probs - VP9 Motion vector probability updates -+ * @joint: motion vector joint probability updates. -+ * @sign: motion vector sign probability updates. -+ * @classes: motion vector class probability updates. -+ * @class0_bit: motion vector class0 bit probability updates. -+ * @bits: motion vector bits probability updates. -+ * @class0_fr: motion vector class0 fractional bit probability updates. -+ * @fr: motion vector fractional bit probability updates. -+ * @class0_hp: motion vector class0 high precision fractional bit probability updates. -+ * @hp: motion vector high precision fractional bit probability updates. -+ * -+ * This structure contains new values of motion vector probabilities. -+ * A value of zero in an array element means there is no update of the relevant probability. -+ * See `struct v4l2_vp9_prob_updates` for details. -+ */ -+struct v4l2_vp9_mv_probs { -+ __u8 joint[3]; -+ __u8 sign[2]; -+ __u8 classes[2][10]; -+ __u8 class0_bit[2]; -+ __u8 bits[2][10]; -+ __u8 class0_fr[2][2][3]; -+ __u8 fr[2][3]; -+ __u8 class0_hp[2]; -+ __u8 hp[2]; -+}; -+ -+#define V4L2_CID_STATELESS_VP9_COMPRESSED_HDR (V4L2_CID_CODEC_STATELESS_BASE + 301) -+ -+#define V4L2_VP9_TX_MODE_ONLY_4X4 0 -+#define V4L2_VP9_TX_MODE_ALLOW_8X8 1 -+#define V4L2_VP9_TX_MODE_ALLOW_16X16 2 -+#define V4L2_VP9_TX_MODE_ALLOW_32X32 3 -+#define V4L2_VP9_TX_MODE_SELECT 4 -+ -+/** -+ * struct v4l2_ctrl_vp9_compressed_hdr - VP9 probability updates control -+ * @tx_mode: specifies the TX mode. Set to one of V4L2_VP9_TX_MODE_{}. -+ * @tx8: TX 8x8 probability updates. -+ * @tx16: TX 16x16 probability updates. -+ * @tx32: TX 32x32 probability updates. -+ * @coef: coefficient probability updates. -+ * @skip: skip probability updates. -+ * @inter_mode: inter mode probability updates. -+ * @interp_filter: interpolation filter probability updates. -+ * @is_inter: is inter-block probability updates. -+ * @comp_mode: compound prediction mode probability updates. -+ * @single_ref: single ref probability updates. -+ * @comp_ref: compound ref probability updates. -+ * @y_mode: Y prediction mode probability updates. -+ * @uv_mode: UV prediction mode probability updates. -+ * @partition: partition probability updates. -+ * @mv: motion vector probability updates. -+ * -+ * This structure holds the probabilities update as parsed in the compressed -+ * header (Spec 6.3). These values represent the value of probability update after -+ * being translated with inv_map_table[] (see 6.3.5). A value of zero in an array element -+ * means that there is no update of the relevant probability. -+ * -+ * This control is optional and needs to be used when dealing with the hardware which is -+ * not capable of parsing the compressed header itself. Only drivers which need it will -+ * implement it. -+ */ -+struct v4l2_ctrl_vp9_compressed_hdr { -+ __u8 tx_mode; -+ __u8 tx8[2][1]; -+ __u8 tx16[2][2]; -+ __u8 tx32[2][3]; -+ __u8 coef[4][2][2][6][6][3]; -+ __u8 skip[3]; -+ __u8 inter_mode[7][3]; -+ __u8 interp_filter[4][2]; -+ __u8 is_inter[4]; -+ __u8 comp_mode[5]; -+ __u8 single_ref[5][2]; -+ __u8 comp_ref[5]; -+ __u8 y_mode[4][9]; -+ __u8 uv_mode[10][9]; -+ __u8 partition[16][3]; -+ -+ struct v4l2_vp9_mv_probs mv; -+}; -+ - /* MPEG-compression definitions kept for backwards compatibility */ - #ifndef __KERNEL__ - #define V4L2_CTRL_CLASS_MPEG V4L2_CTRL_CLASS_CODEC -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index f118fe7a9f58..df8b9c486ba1 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -703,6 +703,7 @@ struct v4l2_pix_format { - #define V4L2_PIX_FMT_VP8 v4l2_fourcc('V', 'P', '8', '0') /* VP8 */ - #define V4L2_PIX_FMT_VP8_FRAME v4l2_fourcc('V', 'P', '8', 'F') /* VP8 parsed frame */ - #define V4L2_PIX_FMT_VP9 v4l2_fourcc('V', 'P', '9', '0') /* VP9 */ -+#define V4L2_PIX_FMT_VP9_FRAME v4l2_fourcc('V', 'P', '9', 'F') /* VP9 parsed frame */ - #define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* HEVC aka H.265 */ - #define V4L2_PIX_FMT_FWHT v4l2_fourcc('F', 'W', 'H', 'T') /* Fast Walsh Hadamard Transform (vicodec) */ - #define V4L2_PIX_FMT_FWHT_STATELESS v4l2_fourcc('S', 'F', 'W', 'H') /* Stateless FWHT (vicodec) */ -@@ -1759,6 +1760,8 @@ struct v4l2_ext_control { - struct v4l2_ctrl_mpeg2_sequence __user *p_mpeg2_sequence; - struct v4l2_ctrl_mpeg2_picture __user *p_mpeg2_picture; - struct v4l2_ctrl_mpeg2_quantisation __user *p_mpeg2_quantisation; -+ struct v4l2_ctrl_vp9_compressed_hdr __user *p_vp9_compressed_hdr_probs; -+ struct v4l2_ctrl_vp9_frame __user *p_vp9_frame; - void __user *ptr; - }; - } __attribute__ ((packed)); -@@ -1823,6 +1826,9 @@ enum v4l2_ctrl_type { - V4L2_CTRL_TYPE_MPEG2_QUANTISATION = 0x0250, - V4L2_CTRL_TYPE_MPEG2_SEQUENCE = 0x0251, - V4L2_CTRL_TYPE_MPEG2_PICTURE = 0x0252, -+ -+ V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR = 0x0260, -+ V4L2_CTRL_TYPE_VP9_FRAME = 0x0261, - }; - - /* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */ - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:36 +0100 -Subject: [PATCH] media: Add VP9 v4l2 library - -Provide code common to vp9 drivers in one central location. - -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil ---- - drivers/media/v4l2-core/Kconfig | 4 + - drivers/media/v4l2-core/Makefile | 1 + - drivers/media/v4l2-core/v4l2-vp9.c | 1850 ++++++++++++++++++++++++++++ - include/media/v4l2-vp9.h | 233 ++++ - 4 files changed, 2088 insertions(+) - create mode 100644 drivers/media/v4l2-core/v4l2-vp9.c - create mode 100644 include/media/v4l2-vp9.h - -diff --git a/drivers/media/v4l2-core/Kconfig b/drivers/media/v4l2-core/Kconfig -index 02dc1787e953..6ee75c6c820e 100644 ---- a/drivers/media/v4l2-core/Kconfig -+++ b/drivers/media/v4l2-core/Kconfig -@@ -52,6 +52,10 @@ config V4L2_JPEG_HELPER - config V4L2_H264 - tristate - -+# Used by drivers that need v4l2-vp9.ko -+config V4L2_VP9 -+ tristate -+ - # Used by drivers that need v4l2-mem2mem.ko - config V4L2_MEM2MEM_DEV - tristate -diff --git a/drivers/media/v4l2-core/Makefile b/drivers/media/v4l2-core/Makefile -index 66a78c556c98..83fac5c746f5 100644 ---- a/drivers/media/v4l2-core/Makefile -+++ b/drivers/media/v4l2-core/Makefile -@@ -24,6 +24,7 @@ obj-$(CONFIG_VIDEO_TUNER) += tuner.o - - obj-$(CONFIG_V4L2_MEM2MEM_DEV) += v4l2-mem2mem.o - obj-$(CONFIG_V4L2_H264) += v4l2-h264.o -+obj-$(CONFIG_V4L2_VP9) += v4l2-vp9.o - - obj-$(CONFIG_V4L2_FLASH_LED_CLASS) += v4l2-flash-led-class.o - -diff --git a/drivers/media/v4l2-core/v4l2-vp9.c b/drivers/media/v4l2-core/v4l2-vp9.c -new file mode 100644 -index 000000000000..859589f1fd35 ---- /dev/null -+++ b/drivers/media/v4l2-core/v4l2-vp9.c -@@ -0,0 +1,1850 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * V4L2 VP9 helpers. -+ * -+ * Copyright (C) 2021 Collabora, Ltd. -+ * -+ * Author: Andrzej Pietrasiewicz -+ */ -+ -+#include -+ -+#include -+ -+const u8 v4l2_vp9_kf_y_mode_prob[10][10][9] = { -+ { -+ /* above = dc */ -+ { 137, 30, 42, 148, 151, 207, 70, 52, 91 }, /*left = dc */ -+ { 92, 45, 102, 136, 116, 180, 74, 90, 100 }, /*left = v */ -+ { 73, 32, 19, 187, 222, 215, 46, 34, 100 }, /*left = h */ -+ { 91, 30, 32, 116, 121, 186, 93, 86, 94 }, /*left = d45 */ -+ { 72, 35, 36, 149, 68, 206, 68, 63, 105 }, /*left = d135*/ -+ { 73, 31, 28, 138, 57, 124, 55, 122, 151 }, /*left = d117*/ -+ { 67, 23, 21, 140, 126, 197, 40, 37, 171 }, /*left = d153*/ -+ { 86, 27, 28, 128, 154, 212, 45, 43, 53 }, /*left = d207*/ -+ { 74, 32, 27, 107, 86, 160, 63, 134, 102 }, /*left = d63 */ -+ { 59, 67, 44, 140, 161, 202, 78, 67, 119 }, /*left = tm */ -+ }, { /* above = v */ -+ { 63, 36, 126, 146, 123, 158, 60, 90, 96 }, /*left = dc */ -+ { 43, 46, 168, 134, 107, 128, 69, 142, 92 }, /*left = v */ -+ { 44, 29, 68, 159, 201, 177, 50, 57, 77 }, /*left = h */ -+ { 58, 38, 76, 114, 97, 172, 78, 133, 92 }, /*left = d45 */ -+ { 46, 41, 76, 140, 63, 184, 69, 112, 57 }, /*left = d135*/ -+ { 38, 32, 85, 140, 46, 112, 54, 151, 133 }, /*left = d117*/ -+ { 39, 27, 61, 131, 110, 175, 44, 75, 136 }, /*left = d153*/ -+ { 52, 30, 74, 113, 130, 175, 51, 64, 58 }, /*left = d207*/ -+ { 47, 35, 80, 100, 74, 143, 64, 163, 74 }, /*left = d63 */ -+ { 36, 61, 116, 114, 128, 162, 80, 125, 82 }, /*left = tm */ -+ }, { /* above = h */ -+ { 82, 26, 26, 171, 208, 204, 44, 32, 105 }, /*left = dc */ -+ { 55, 44, 68, 166, 179, 192, 57, 57, 108 }, /*left = v */ -+ { 42, 26, 11, 199, 241, 228, 23, 15, 85 }, /*left = h */ -+ { 68, 42, 19, 131, 160, 199, 55, 52, 83 }, /*left = d45 */ -+ { 58, 50, 25, 139, 115, 232, 39, 52, 118 }, /*left = d135*/ -+ { 50, 35, 33, 153, 104, 162, 64, 59, 131 }, /*left = d117*/ -+ { 44, 24, 16, 150, 177, 202, 33, 19, 156 }, /*left = d153*/ -+ { 55, 27, 12, 153, 203, 218, 26, 27, 49 }, /*left = d207*/ -+ { 53, 49, 21, 110, 116, 168, 59, 80, 76 }, /*left = d63 */ -+ { 38, 72, 19, 168, 203, 212, 50, 50, 107 }, /*left = tm */ -+ }, { /* above = d45 */ -+ { 103, 26, 36, 129, 132, 201, 83, 80, 93 }, /*left = dc */ -+ { 59, 38, 83, 112, 103, 162, 98, 136, 90 }, /*left = v */ -+ { 62, 30, 23, 158, 200, 207, 59, 57, 50 }, /*left = h */ -+ { 67, 30, 29, 84, 86, 191, 102, 91, 59 }, /*left = d45 */ -+ { 60, 32, 33, 112, 71, 220, 64, 89, 104 }, /*left = d135*/ -+ { 53, 26, 34, 130, 56, 149, 84, 120, 103 }, /*left = d117*/ -+ { 53, 21, 23, 133, 109, 210, 56, 77, 172 }, /*left = d153*/ -+ { 77, 19, 29, 112, 142, 228, 55, 66, 36 }, /*left = d207*/ -+ { 61, 29, 29, 93, 97, 165, 83, 175, 162 }, /*left = d63 */ -+ { 47, 47, 43, 114, 137, 181, 100, 99, 95 }, /*left = tm */ -+ }, { /* above = d135 */ -+ { 69, 23, 29, 128, 83, 199, 46, 44, 101 }, /*left = dc */ -+ { 53, 40, 55, 139, 69, 183, 61, 80, 110 }, /*left = v */ -+ { 40, 29, 19, 161, 180, 207, 43, 24, 91 }, /*left = h */ -+ { 60, 34, 19, 105, 61, 198, 53, 64, 89 }, /*left = d45 */ -+ { 52, 31, 22, 158, 40, 209, 58, 62, 89 }, /*left = d135*/ -+ { 44, 31, 29, 147, 46, 158, 56, 102, 198 }, /*left = d117*/ -+ { 35, 19, 12, 135, 87, 209, 41, 45, 167 }, /*left = d153*/ -+ { 55, 25, 21, 118, 95, 215, 38, 39, 66 }, /*left = d207*/ -+ { 51, 38, 25, 113, 58, 164, 70, 93, 97 }, /*left = d63 */ -+ { 47, 54, 34, 146, 108, 203, 72, 103, 151 }, /*left = tm */ -+ }, { /* above = d117 */ -+ { 64, 19, 37, 156, 66, 138, 49, 95, 133 }, /*left = dc */ -+ { 46, 27, 80, 150, 55, 124, 55, 121, 135 }, /*left = v */ -+ { 36, 23, 27, 165, 149, 166, 54, 64, 118 }, /*left = h */ -+ { 53, 21, 36, 131, 63, 163, 60, 109, 81 }, /*left = d45 */ -+ { 40, 26, 35, 154, 40, 185, 51, 97, 123 }, /*left = d135*/ -+ { 35, 19, 34, 179, 19, 97, 48, 129, 124 }, /*left = d117*/ -+ { 36, 20, 26, 136, 62, 164, 33, 77, 154 }, /*left = d153*/ -+ { 45, 18, 32, 130, 90, 157, 40, 79, 91 }, /*left = d207*/ -+ { 45, 26, 28, 129, 45, 129, 49, 147, 123 }, /*left = d63 */ -+ { 38, 44, 51, 136, 74, 162, 57, 97, 121 }, /*left = tm */ -+ }, { /* above = d153 */ -+ { 75, 17, 22, 136, 138, 185, 32, 34, 166 }, /*left = dc */ -+ { 56, 39, 58, 133, 117, 173, 48, 53, 187 }, /*left = v */ -+ { 35, 21, 12, 161, 212, 207, 20, 23, 145 }, /*left = h */ -+ { 56, 29, 19, 117, 109, 181, 55, 68, 112 }, /*left = d45 */ -+ { 47, 29, 17, 153, 64, 220, 59, 51, 114 }, /*left = d135*/ -+ { 46, 16, 24, 136, 76, 147, 41, 64, 172 }, /*left = d117*/ -+ { 34, 17, 11, 108, 152, 187, 13, 15, 209 }, /*left = d153*/ -+ { 51, 24, 14, 115, 133, 209, 32, 26, 104 }, /*left = d207*/ -+ { 55, 30, 18, 122, 79, 179, 44, 88, 116 }, /*left = d63 */ -+ { 37, 49, 25, 129, 168, 164, 41, 54, 148 }, /*left = tm */ -+ }, { /* above = d207 */ -+ { 82, 22, 32, 127, 143, 213, 39, 41, 70 }, /*left = dc */ -+ { 62, 44, 61, 123, 105, 189, 48, 57, 64 }, /*left = v */ -+ { 47, 25, 17, 175, 222, 220, 24, 30, 86 }, /*left = h */ -+ { 68, 36, 17, 106, 102, 206, 59, 74, 74 }, /*left = d45 */ -+ { 57, 39, 23, 151, 68, 216, 55, 63, 58 }, /*left = d135*/ -+ { 49, 30, 35, 141, 70, 168, 82, 40, 115 }, /*left = d117*/ -+ { 51, 25, 15, 136, 129, 202, 38, 35, 139 }, /*left = d153*/ -+ { 68, 26, 16, 111, 141, 215, 29, 28, 28 }, /*left = d207*/ -+ { 59, 39, 19, 114, 75, 180, 77, 104, 42 }, /*left = d63 */ -+ { 40, 61, 26, 126, 152, 206, 61, 59, 93 }, /*left = tm */ -+ }, { /* above = d63 */ -+ { 78, 23, 39, 111, 117, 170, 74, 124, 94 }, /*left = dc */ -+ { 48, 34, 86, 101, 92, 146, 78, 179, 134 }, /*left = v */ -+ { 47, 22, 24, 138, 187, 178, 68, 69, 59 }, /*left = h */ -+ { 56, 25, 33, 105, 112, 187, 95, 177, 129 }, /*left = d45 */ -+ { 48, 31, 27, 114, 63, 183, 82, 116, 56 }, /*left = d135*/ -+ { 43, 28, 37, 121, 63, 123, 61, 192, 169 }, /*left = d117*/ -+ { 42, 17, 24, 109, 97, 177, 56, 76, 122 }, /*left = d153*/ -+ { 58, 18, 28, 105, 139, 182, 70, 92, 63 }, /*left = d207*/ -+ { 46, 23, 32, 74, 86, 150, 67, 183, 88 }, /*left = d63 */ -+ { 36, 38, 48, 92, 122, 165, 88, 137, 91 }, /*left = tm */ -+ }, { /* above = tm */ -+ { 65, 70, 60, 155, 159, 199, 61, 60, 81 }, /*left = dc */ -+ { 44, 78, 115, 132, 119, 173, 71, 112, 93 }, /*left = v */ -+ { 39, 38, 21, 184, 227, 206, 42, 32, 64 }, /*left = h */ -+ { 58, 47, 36, 124, 137, 193, 80, 82, 78 }, /*left = d45 */ -+ { 49, 50, 35, 144, 95, 205, 63, 78, 59 }, /*left = d135*/ -+ { 41, 53, 52, 148, 71, 142, 65, 128, 51 }, /*left = d117*/ -+ { 40, 36, 28, 143, 143, 202, 40, 55, 137 }, /*left = d153*/ -+ { 52, 34, 29, 129, 183, 227, 42, 35, 43 }, /*left = d207*/ -+ { 42, 44, 44, 104, 105, 164, 64, 130, 80 }, /*left = d63 */ -+ { 43, 81, 53, 140, 169, 204, 68, 84, 72 }, /*left = tm */ -+ } -+}; -+EXPORT_SYMBOL_GPL(v4l2_vp9_kf_y_mode_prob); -+ -+const u8 v4l2_vp9_kf_partition_probs[16][3] = { -+ /* 8x8 -> 4x4 */ -+ { 158, 97, 94 }, /* a/l both not split */ -+ { 93, 24, 99 }, /* a split, l not split */ -+ { 85, 119, 44 }, /* l split, a not split */ -+ { 62, 59, 67 }, /* a/l both split */ -+ /* 16x16 -> 8x8 */ -+ { 149, 53, 53 }, /* a/l both not split */ -+ { 94, 20, 48 }, /* a split, l not split */ -+ { 83, 53, 24 }, /* l split, a not split */ -+ { 52, 18, 18 }, /* a/l both split */ -+ /* 32x32 -> 16x16 */ -+ { 150, 40, 39 }, /* a/l both not split */ -+ { 78, 12, 26 }, /* a split, l not split */ -+ { 67, 33, 11 }, /* l split, a not split */ -+ { 24, 7, 5 }, /* a/l both split */ -+ /* 64x64 -> 32x32 */ -+ { 174, 35, 49 }, /* a/l both not split */ -+ { 68, 11, 27 }, /* a split, l not split */ -+ { 57, 15, 9 }, /* l split, a not split */ -+ { 12, 3, 3 }, /* a/l both split */ -+}; -+EXPORT_SYMBOL_GPL(v4l2_vp9_kf_partition_probs); -+ -+const u8 v4l2_vp9_kf_uv_mode_prob[10][9] = { -+ { 144, 11, 54, 157, 195, 130, 46, 58, 108 }, /* y = dc */ -+ { 118, 15, 123, 148, 131, 101, 44, 93, 131 }, /* y = v */ -+ { 113, 12, 23, 188, 226, 142, 26, 32, 125 }, /* y = h */ -+ { 120, 11, 50, 123, 163, 135, 64, 77, 103 }, /* y = d45 */ -+ { 113, 9, 36, 155, 111, 157, 32, 44, 161 }, /* y = d135 */ -+ { 116, 9, 55, 176, 76, 96, 37, 61, 149 }, /* y = d117 */ -+ { 115, 9, 28, 141, 161, 167, 21, 25, 193 }, /* y = d153 */ -+ { 120, 12, 32, 145, 195, 142, 32, 38, 86 }, /* y = d207 */ -+ { 116, 12, 64, 120, 140, 125, 49, 115, 121 }, /* y = d63 */ -+ { 102, 19, 66, 162, 182, 122, 35, 59, 128 } /* y = tm */ -+}; -+EXPORT_SYMBOL_GPL(v4l2_vp9_kf_uv_mode_prob); -+ -+const struct v4l2_vp9_frame_context v4l2_vp9_default_probs = { -+ .tx8 = { -+ { 100 }, -+ { 66 }, -+ }, -+ .tx16 = { -+ { 20, 152 }, -+ { 15, 101 }, -+ }, -+ .tx32 = { -+ { 3, 136, 37 }, -+ { 5, 52, 13 }, -+ }, -+ .coef = { -+ { /* tx = 4x4 */ -+ { /* block Type 0 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 195, 29, 183 }, -+ { 84, 49, 136 }, -+ { 8, 42, 71 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 31, 107, 169 }, -+ { 35, 99, 159 }, -+ { 17, 82, 140 }, -+ { 8, 66, 114 }, -+ { 2, 44, 76 }, -+ { 1, 19, 32 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 40, 132, 201 }, -+ { 29, 114, 187 }, -+ { 13, 91, 157 }, -+ { 7, 75, 127 }, -+ { 3, 58, 95 }, -+ { 1, 28, 47 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 69, 142, 221 }, -+ { 42, 122, 201 }, -+ { 15, 91, 159 }, -+ { 6, 67, 121 }, -+ { 1, 42, 77 }, -+ { 1, 17, 31 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 102, 148, 228 }, -+ { 67, 117, 204 }, -+ { 17, 82, 154 }, -+ { 6, 59, 114 }, -+ { 2, 39, 75 }, -+ { 1, 15, 29 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 156, 57, 233 }, -+ { 119, 57, 212 }, -+ { 58, 48, 163 }, -+ { 29, 40, 124 }, -+ { 12, 30, 81 }, -+ { 3, 12, 31 } -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 191, 107, 226 }, -+ { 124, 117, 204 }, -+ { 25, 99, 155 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 29, 148, 210 }, -+ { 37, 126, 194 }, -+ { 8, 93, 157 }, -+ { 2, 68, 118 }, -+ { 1, 39, 69 }, -+ { 1, 17, 33 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 41, 151, 213 }, -+ { 27, 123, 193 }, -+ { 3, 82, 144 }, -+ { 1, 58, 105 }, -+ { 1, 32, 60 }, -+ { 1, 13, 26 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 59, 159, 220 }, -+ { 23, 126, 198 }, -+ { 4, 88, 151 }, -+ { 1, 66, 114 }, -+ { 1, 38, 71 }, -+ { 1, 18, 34 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 114, 136, 232 }, -+ { 51, 114, 207 }, -+ { 11, 83, 155 }, -+ { 3, 56, 105 }, -+ { 1, 33, 65 }, -+ { 1, 17, 34 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 149, 65, 234 }, -+ { 121, 57, 215 }, -+ { 61, 49, 166 }, -+ { 28, 36, 114 }, -+ { 12, 25, 76 }, -+ { 3, 16, 42 }, -+ }, -+ }, -+ }, -+ { /* block Type 1 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 214, 49, 220 }, -+ { 132, 63, 188 }, -+ { 42, 65, 137 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 85, 137, 221 }, -+ { 104, 131, 216 }, -+ { 49, 111, 192 }, -+ { 21, 87, 155 }, -+ { 2, 49, 87 }, -+ { 1, 16, 28 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 89, 163, 230 }, -+ { 90, 137, 220 }, -+ { 29, 100, 183 }, -+ { 10, 70, 135 }, -+ { 2, 42, 81 }, -+ { 1, 17, 33 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 108, 167, 237 }, -+ { 55, 133, 222 }, -+ { 15, 97, 179 }, -+ { 4, 72, 135 }, -+ { 1, 45, 85 }, -+ { 1, 19, 38 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 124, 146, 240 }, -+ { 66, 124, 224 }, -+ { 17, 88, 175 }, -+ { 4, 58, 122 }, -+ { 1, 36, 75 }, -+ { 1, 18, 37 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 141, 79, 241 }, -+ { 126, 70, 227 }, -+ { 66, 58, 182 }, -+ { 30, 44, 136 }, -+ { 12, 34, 96 }, -+ { 2, 20, 47 }, -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 229, 99, 249 }, -+ { 143, 111, 235 }, -+ { 46, 109, 192 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 82, 158, 236 }, -+ { 94, 146, 224 }, -+ { 25, 117, 191 }, -+ { 9, 87, 149 }, -+ { 3, 56, 99 }, -+ { 1, 33, 57 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 83, 167, 237 }, -+ { 68, 145, 222 }, -+ { 10, 103, 177 }, -+ { 2, 72, 131 }, -+ { 1, 41, 79 }, -+ { 1, 20, 39 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 99, 167, 239 }, -+ { 47, 141, 224 }, -+ { 10, 104, 178 }, -+ { 2, 73, 133 }, -+ { 1, 44, 85 }, -+ { 1, 22, 47 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 127, 145, 243 }, -+ { 71, 129, 228 }, -+ { 17, 93, 177 }, -+ { 3, 61, 124 }, -+ { 1, 41, 84 }, -+ { 1, 21, 52 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 157, 78, 244 }, -+ { 140, 72, 231 }, -+ { 69, 58, 184 }, -+ { 31, 44, 137 }, -+ { 14, 38, 105 }, -+ { 8, 23, 61 }, -+ }, -+ }, -+ }, -+ }, -+ { /* tx = 8x8 */ -+ { /* block Type 0 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 125, 34, 187 }, -+ { 52, 41, 133 }, -+ { 6, 31, 56 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 37, 109, 153 }, -+ { 51, 102, 147 }, -+ { 23, 87, 128 }, -+ { 8, 67, 101 }, -+ { 1, 41, 63 }, -+ { 1, 19, 29 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 31, 154, 185 }, -+ { 17, 127, 175 }, -+ { 6, 96, 145 }, -+ { 2, 73, 114 }, -+ { 1, 51, 82 }, -+ { 1, 28, 45 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 23, 163, 200 }, -+ { 10, 131, 185 }, -+ { 2, 93, 148 }, -+ { 1, 67, 111 }, -+ { 1, 41, 69 }, -+ { 1, 14, 24 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 29, 176, 217 }, -+ { 12, 145, 201 }, -+ { 3, 101, 156 }, -+ { 1, 69, 111 }, -+ { 1, 39, 63 }, -+ { 1, 14, 23 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 57, 192, 233 }, -+ { 25, 154, 215 }, -+ { 6, 109, 167 }, -+ { 3, 78, 118 }, -+ { 1, 48, 69 }, -+ { 1, 21, 29 }, -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 202, 105, 245 }, -+ { 108, 106, 216 }, -+ { 18, 90, 144 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 33, 172, 219 }, -+ { 64, 149, 206 }, -+ { 14, 117, 177 }, -+ { 5, 90, 141 }, -+ { 2, 61, 95 }, -+ { 1, 37, 57 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 33, 179, 220 }, -+ { 11, 140, 198 }, -+ { 1, 89, 148 }, -+ { 1, 60, 104 }, -+ { 1, 33, 57 }, -+ { 1, 12, 21 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 30, 181, 221 }, -+ { 8, 141, 198 }, -+ { 1, 87, 145 }, -+ { 1, 58, 100 }, -+ { 1, 31, 55 }, -+ { 1, 12, 20 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 32, 186, 224 }, -+ { 7, 142, 198 }, -+ { 1, 86, 143 }, -+ { 1, 58, 100 }, -+ { 1, 31, 55 }, -+ { 1, 12, 22 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 57, 192, 227 }, -+ { 20, 143, 204 }, -+ { 3, 96, 154 }, -+ { 1, 68, 112 }, -+ { 1, 42, 69 }, -+ { 1, 19, 32 }, -+ }, -+ }, -+ }, -+ { /* block Type 1 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 212, 35, 215 }, -+ { 113, 47, 169 }, -+ { 29, 48, 105 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 74, 129, 203 }, -+ { 106, 120, 203 }, -+ { 49, 107, 178 }, -+ { 19, 84, 144 }, -+ { 4, 50, 84 }, -+ { 1, 15, 25 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 71, 172, 217 }, -+ { 44, 141, 209 }, -+ { 15, 102, 173 }, -+ { 6, 76, 133 }, -+ { 2, 51, 89 }, -+ { 1, 24, 42 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 64, 185, 231 }, -+ { 31, 148, 216 }, -+ { 8, 103, 175 }, -+ { 3, 74, 131 }, -+ { 1, 46, 81 }, -+ { 1, 18, 30 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 65, 196, 235 }, -+ { 25, 157, 221 }, -+ { 5, 105, 174 }, -+ { 1, 67, 120 }, -+ { 1, 38, 69 }, -+ { 1, 15, 30 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 65, 204, 238 }, -+ { 30, 156, 224 }, -+ { 7, 107, 177 }, -+ { 2, 70, 124 }, -+ { 1, 42, 73 }, -+ { 1, 18, 34 }, -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 225, 86, 251 }, -+ { 144, 104, 235 }, -+ { 42, 99, 181 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 85, 175, 239 }, -+ { 112, 165, 229 }, -+ { 29, 136, 200 }, -+ { 12, 103, 162 }, -+ { 6, 77, 123 }, -+ { 2, 53, 84 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 75, 183, 239 }, -+ { 30, 155, 221 }, -+ { 3, 106, 171 }, -+ { 1, 74, 128 }, -+ { 1, 44, 76 }, -+ { 1, 17, 28 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 73, 185, 240 }, -+ { 27, 159, 222 }, -+ { 2, 107, 172 }, -+ { 1, 75, 127 }, -+ { 1, 42, 73 }, -+ { 1, 17, 29 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 62, 190, 238 }, -+ { 21, 159, 222 }, -+ { 2, 107, 172 }, -+ { 1, 72, 122 }, -+ { 1, 40, 71 }, -+ { 1, 18, 32 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 61, 199, 240 }, -+ { 27, 161, 226 }, -+ { 4, 113, 180 }, -+ { 1, 76, 129 }, -+ { 1, 46, 80 }, -+ { 1, 23, 41 }, -+ }, -+ }, -+ }, -+ }, -+ { /* tx = 16x16 */ -+ { /* block Type 0 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 7, 27, 153 }, -+ { 5, 30, 95 }, -+ { 1, 16, 30 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 50, 75, 127 }, -+ { 57, 75, 124 }, -+ { 27, 67, 108 }, -+ { 10, 54, 86 }, -+ { 1, 33, 52 }, -+ { 1, 12, 18 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 43, 125, 151 }, -+ { 26, 108, 148 }, -+ { 7, 83, 122 }, -+ { 2, 59, 89 }, -+ { 1, 38, 60 }, -+ { 1, 17, 27 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 23, 144, 163 }, -+ { 13, 112, 154 }, -+ { 2, 75, 117 }, -+ { 1, 50, 81 }, -+ { 1, 31, 51 }, -+ { 1, 14, 23 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 18, 162, 185 }, -+ { 6, 123, 171 }, -+ { 1, 78, 125 }, -+ { 1, 51, 86 }, -+ { 1, 31, 54 }, -+ { 1, 14, 23 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 15, 199, 227 }, -+ { 3, 150, 204 }, -+ { 1, 91, 146 }, -+ { 1, 55, 95 }, -+ { 1, 30, 53 }, -+ { 1, 11, 20 }, -+ } -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 19, 55, 240 }, -+ { 19, 59, 196 }, -+ { 3, 52, 105 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 41, 166, 207 }, -+ { 104, 153, 199 }, -+ { 31, 123, 181 }, -+ { 14, 101, 152 }, -+ { 5, 72, 106 }, -+ { 1, 36, 52 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 35, 176, 211 }, -+ { 12, 131, 190 }, -+ { 2, 88, 144 }, -+ { 1, 60, 101 }, -+ { 1, 36, 60 }, -+ { 1, 16, 28 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 28, 183, 213 }, -+ { 8, 134, 191 }, -+ { 1, 86, 142 }, -+ { 1, 56, 96 }, -+ { 1, 30, 53 }, -+ { 1, 12, 20 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 20, 190, 215 }, -+ { 4, 135, 192 }, -+ { 1, 84, 139 }, -+ { 1, 53, 91 }, -+ { 1, 28, 49 }, -+ { 1, 11, 20 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 13, 196, 216 }, -+ { 2, 137, 192 }, -+ { 1, 86, 143 }, -+ { 1, 57, 99 }, -+ { 1, 32, 56 }, -+ { 1, 13, 24 }, -+ }, -+ }, -+ }, -+ { /* block Type 1 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 211, 29, 217 }, -+ { 96, 47, 156 }, -+ { 22, 43, 87 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 78, 120, 193 }, -+ { 111, 116, 186 }, -+ { 46, 102, 164 }, -+ { 15, 80, 128 }, -+ { 2, 49, 76 }, -+ { 1, 18, 28 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 71, 161, 203 }, -+ { 42, 132, 192 }, -+ { 10, 98, 150 }, -+ { 3, 69, 109 }, -+ { 1, 44, 70 }, -+ { 1, 18, 29 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 57, 186, 211 }, -+ { 30, 140, 196 }, -+ { 4, 93, 146 }, -+ { 1, 62, 102 }, -+ { 1, 38, 65 }, -+ { 1, 16, 27 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 47, 199, 217 }, -+ { 14, 145, 196 }, -+ { 1, 88, 142 }, -+ { 1, 57, 98 }, -+ { 1, 36, 62 }, -+ { 1, 15, 26 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 26, 219, 229 }, -+ { 5, 155, 207 }, -+ { 1, 94, 151 }, -+ { 1, 60, 104 }, -+ { 1, 36, 62 }, -+ { 1, 16, 28 }, -+ } -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 233, 29, 248 }, -+ { 146, 47, 220 }, -+ { 43, 52, 140 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 100, 163, 232 }, -+ { 179, 161, 222 }, -+ { 63, 142, 204 }, -+ { 37, 113, 174 }, -+ { 26, 89, 137 }, -+ { 18, 68, 97 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 85, 181, 230 }, -+ { 32, 146, 209 }, -+ { 7, 100, 164 }, -+ { 3, 71, 121 }, -+ { 1, 45, 77 }, -+ { 1, 18, 30 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 65, 187, 230 }, -+ { 20, 148, 207 }, -+ { 2, 97, 159 }, -+ { 1, 68, 116 }, -+ { 1, 40, 70 }, -+ { 1, 14, 29 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 40, 194, 227 }, -+ { 8, 147, 204 }, -+ { 1, 94, 155 }, -+ { 1, 65, 112 }, -+ { 1, 39, 66 }, -+ { 1, 14, 26 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 16, 208, 228 }, -+ { 3, 151, 207 }, -+ { 1, 98, 160 }, -+ { 1, 67, 117 }, -+ { 1, 41, 74 }, -+ { 1, 17, 31 }, -+ }, -+ }, -+ }, -+ }, -+ { /* tx = 32x32 */ -+ { /* block Type 0 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 17, 38, 140 }, -+ { 7, 34, 80 }, -+ { 1, 17, 29 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 37, 75, 128 }, -+ { 41, 76, 128 }, -+ { 26, 66, 116 }, -+ { 12, 52, 94 }, -+ { 2, 32, 55 }, -+ { 1, 10, 16 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 50, 127, 154 }, -+ { 37, 109, 152 }, -+ { 16, 82, 121 }, -+ { 5, 59, 85 }, -+ { 1, 35, 54 }, -+ { 1, 13, 20 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 40, 142, 167 }, -+ { 17, 110, 157 }, -+ { 2, 71, 112 }, -+ { 1, 44, 72 }, -+ { 1, 27, 45 }, -+ { 1, 11, 17 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 30, 175, 188 }, -+ { 9, 124, 169 }, -+ { 1, 74, 116 }, -+ { 1, 48, 78 }, -+ { 1, 30, 49 }, -+ { 1, 11, 18 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 10, 222, 223 }, -+ { 2, 150, 194 }, -+ { 1, 83, 128 }, -+ { 1, 48, 79 }, -+ { 1, 27, 45 }, -+ { 1, 11, 17 }, -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 36, 41, 235 }, -+ { 29, 36, 193 }, -+ { 10, 27, 111 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 85, 165, 222 }, -+ { 177, 162, 215 }, -+ { 110, 135, 195 }, -+ { 57, 113, 168 }, -+ { 23, 83, 120 }, -+ { 10, 49, 61 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 85, 190, 223 }, -+ { 36, 139, 200 }, -+ { 5, 90, 146 }, -+ { 1, 60, 103 }, -+ { 1, 38, 65 }, -+ { 1, 18, 30 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 72, 202, 223 }, -+ { 23, 141, 199 }, -+ { 2, 86, 140 }, -+ { 1, 56, 97 }, -+ { 1, 36, 61 }, -+ { 1, 16, 27 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 55, 218, 225 }, -+ { 13, 145, 200 }, -+ { 1, 86, 141 }, -+ { 1, 57, 99 }, -+ { 1, 35, 61 }, -+ { 1, 13, 22 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 15, 235, 212 }, -+ { 1, 132, 184 }, -+ { 1, 84, 139 }, -+ { 1, 57, 97 }, -+ { 1, 34, 56 }, -+ { 1, 14, 23 }, -+ }, -+ }, -+ }, -+ { /* block Type 1 */ -+ { /* Intra */ -+ { /* Coeff Band 0 */ -+ { 181, 21, 201 }, -+ { 61, 37, 123 }, -+ { 10, 38, 71 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 47, 106, 172 }, -+ { 95, 104, 173 }, -+ { 42, 93, 159 }, -+ { 18, 77, 131 }, -+ { 4, 50, 81 }, -+ { 1, 17, 23 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 62, 147, 199 }, -+ { 44, 130, 189 }, -+ { 28, 102, 154 }, -+ { 18, 75, 115 }, -+ { 2, 44, 65 }, -+ { 1, 12, 19 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 55, 153, 210 }, -+ { 24, 130, 194 }, -+ { 3, 93, 146 }, -+ { 1, 61, 97 }, -+ { 1, 31, 50 }, -+ { 1, 10, 16 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 49, 186, 223 }, -+ { 17, 148, 204 }, -+ { 1, 96, 142 }, -+ { 1, 53, 83 }, -+ { 1, 26, 44 }, -+ { 1, 11, 17 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 13, 217, 212 }, -+ { 2, 136, 180 }, -+ { 1, 78, 124 }, -+ { 1, 50, 83 }, -+ { 1, 29, 49 }, -+ { 1, 14, 23 }, -+ }, -+ }, -+ { /* Inter */ -+ { /* Coeff Band 0 */ -+ { 197, 13, 247 }, -+ { 82, 17, 222 }, -+ { 25, 17, 162 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ { 0, 0, 0 }, -+ }, -+ { /* Coeff Band 1 */ -+ { 126, 186, 247 }, -+ { 234, 191, 243 }, -+ { 176, 177, 234 }, -+ { 104, 158, 220 }, -+ { 66, 128, 186 }, -+ { 55, 90, 137 }, -+ }, -+ { /* Coeff Band 2 */ -+ { 111, 197, 242 }, -+ { 46, 158, 219 }, -+ { 9, 104, 171 }, -+ { 2, 65, 125 }, -+ { 1, 44, 80 }, -+ { 1, 17, 91 }, -+ }, -+ { /* Coeff Band 3 */ -+ { 104, 208, 245 }, -+ { 39, 168, 224 }, -+ { 3, 109, 162 }, -+ { 1, 79, 124 }, -+ { 1, 50, 102 }, -+ { 1, 43, 102 }, -+ }, -+ { /* Coeff Band 4 */ -+ { 84, 220, 246 }, -+ { 31, 177, 231 }, -+ { 2, 115, 180 }, -+ { 1, 79, 134 }, -+ { 1, 55, 77 }, -+ { 1, 60, 79 }, -+ }, -+ { /* Coeff Band 5 */ -+ { 43, 243, 240 }, -+ { 8, 180, 217 }, -+ { 1, 115, 166 }, -+ { 1, 84, 121 }, -+ { 1, 51, 67 }, -+ { 1, 16, 6 }, -+ }, -+ }, -+ }, -+ }, -+ }, -+ -+ .skip = { 192, 128, 64 }, -+ .inter_mode = { -+ { 2, 173, 34 }, -+ { 7, 145, 85 }, -+ { 7, 166, 63 }, -+ { 7, 94, 66 }, -+ { 8, 64, 46 }, -+ { 17, 81, 31 }, -+ { 25, 29, 30 }, -+ }, -+ .interp_filter = { -+ { 235, 162 }, -+ { 36, 255 }, -+ { 34, 3 }, -+ { 149, 144 }, -+ }, -+ .is_inter = { 9, 102, 187, 225 }, -+ .comp_mode = { 239, 183, 119, 96, 41 }, -+ .single_ref = { -+ { 33, 16 }, -+ { 77, 74 }, -+ { 142, 142 }, -+ { 172, 170 }, -+ { 238, 247 }, -+ }, -+ .comp_ref = { 50, 126, 123, 221, 226 }, -+ .y_mode = { -+ { 65, 32, 18, 144, 162, 194, 41, 51, 98 }, -+ { 132, 68, 18, 165, 217, 196, 45, 40, 78 }, -+ { 173, 80, 19, 176, 240, 193, 64, 35, 46 }, -+ { 221, 135, 38, 194, 248, 121, 96, 85, 29 }, -+ }, -+ .uv_mode = { -+ { 120, 7, 76, 176, 208, 126, 28, 54, 103 } /* y = dc */, -+ { 48, 12, 154, 155, 139, 90, 34, 117, 119 } /* y = v */, -+ { 67, 6, 25, 204, 243, 158, 13, 21, 96 } /* y = h */, -+ { 97, 5, 44, 131, 176, 139, 48, 68, 97 } /* y = d45 */, -+ { 83, 5, 42, 156, 111, 152, 26, 49, 152 } /* y = d135 */, -+ { 80, 5, 58, 178, 74, 83, 33, 62, 145 } /* y = d117 */, -+ { 86, 5, 32, 154, 192, 168, 14, 22, 163 } /* y = d153 */, -+ { 85, 5, 32, 156, 216, 148, 19, 29, 73 } /* y = d207 */, -+ { 77, 7, 64, 116, 132, 122, 37, 126, 120 } /* y = d63 */, -+ { 101, 21, 107, 181, 192, 103, 19, 67, 125 } /* y = tm */ -+ }, -+ .partition = { -+ /* 8x8 -> 4x4 */ -+ { 199, 122, 141 } /* a/l both not split */, -+ { 147, 63, 159 } /* a split, l not split */, -+ { 148, 133, 118 } /* l split, a not split */, -+ { 121, 104, 114 } /* a/l both split */, -+ /* 16x16 -> 8x8 */ -+ { 174, 73, 87 } /* a/l both not split */, -+ { 92, 41, 83 } /* a split, l not split */, -+ { 82, 99, 50 } /* l split, a not split */, -+ { 53, 39, 39 } /* a/l both split */, -+ /* 32x32 -> 16x16 */ -+ { 177, 58, 59 } /* a/l both not split */, -+ { 68, 26, 63 } /* a split, l not split */, -+ { 52, 79, 25 } /* l split, a not split */, -+ { 17, 14, 12 } /* a/l both split */, -+ /* 64x64 -> 32x32 */ -+ { 222, 34, 30 } /* a/l both not split */, -+ { 72, 16, 44 } /* a split, l not split */, -+ { 58, 32, 12 } /* l split, a not split */, -+ { 10, 7, 6 } /* a/l both split */, -+ }, -+ -+ .mv = { -+ .joint = { 32, 64, 96 }, -+ .sign = { 128, 128 }, -+ .classes = { -+ { 224, 144, 192, 168, 192, 176, 192, 198, 198, 245 }, -+ { 216, 128, 176, 160, 176, 176, 192, 198, 198, 208 }, -+ }, -+ .class0_bit = { 216, 208 }, -+ .bits = { -+ { 136, 140, 148, 160, 176, 192, 224, 234, 234, 240}, -+ { 136, 140, 148, 160, 176, 192, 224, 234, 234, 240}, -+ }, -+ .class0_fr = { -+ { -+ { 128, 128, 64 }, -+ { 96, 112, 64 }, -+ }, -+ { -+ { 128, 128, 64 }, -+ { 96, 112, 64 }, -+ }, -+ }, -+ .fr = { -+ { 64, 96, 64 }, -+ { 64, 96, 64 }, -+ }, -+ .class0_hp = { 160, 160 }, -+ .hp = { 128, 128 }, -+ }, -+}; -+EXPORT_SYMBOL_GPL(v4l2_vp9_default_probs); -+ -+static u32 fastdiv(u32 dividend, u16 divisor) -+{ -+#define DIV_INV(d) ((u32)(((1ULL << 32) + ((d) - 1)) / (d))) -+#define DIVS_INV(d0, d1, d2, d3, d4, d5, d6, d7, d8, d9) \ -+ DIV_INV(d0), DIV_INV(d1), DIV_INV(d2), DIV_INV(d3), \ -+ DIV_INV(d4), DIV_INV(d5), DIV_INV(d6), DIV_INV(d7), \ -+ DIV_INV(d8), DIV_INV(d9) -+ -+ static const u32 inv[] = { -+ DIV_INV(2), DIV_INV(3), DIV_INV(4), DIV_INV(5), -+ DIV_INV(6), DIV_INV(7), DIV_INV(8), DIV_INV(9), -+ DIVS_INV(10, 11, 12, 13, 14, 15, 16, 17, 18, 19), -+ DIVS_INV(20, 21, 22, 23, 24, 25, 26, 27, 28, 29), -+ DIVS_INV(30, 31, 32, 33, 34, 35, 36, 37, 38, 39), -+ DIVS_INV(40, 41, 42, 43, 44, 45, 46, 47, 48, 49), -+ DIVS_INV(50, 51, 52, 53, 54, 55, 56, 57, 58, 59), -+ DIVS_INV(60, 61, 62, 63, 64, 65, 66, 67, 68, 69), -+ DIVS_INV(70, 71, 72, 73, 74, 75, 76, 77, 78, 79), -+ DIVS_INV(80, 81, 82, 83, 84, 85, 86, 87, 88, 89), -+ DIVS_INV(90, 91, 92, 93, 94, 95, 96, 97, 98, 99), -+ DIVS_INV(100, 101, 102, 103, 104, 105, 106, 107, 108, 109), -+ DIVS_INV(110, 111, 112, 113, 114, 115, 116, 117, 118, 119), -+ DIVS_INV(120, 121, 122, 123, 124, 125, 126, 127, 128, 129), -+ DIVS_INV(130, 131, 132, 133, 134, 135, 136, 137, 138, 139), -+ DIVS_INV(140, 141, 142, 143, 144, 145, 146, 147, 148, 149), -+ DIVS_INV(150, 151, 152, 153, 154, 155, 156, 157, 158, 159), -+ DIVS_INV(160, 161, 162, 163, 164, 165, 166, 167, 168, 169), -+ DIVS_INV(170, 171, 172, 173, 174, 175, 176, 177, 178, 179), -+ DIVS_INV(180, 181, 182, 183, 184, 185, 186, 187, 188, 189), -+ DIVS_INV(190, 191, 192, 193, 194, 195, 196, 197, 198, 199), -+ DIVS_INV(200, 201, 202, 203, 204, 205, 206, 207, 208, 209), -+ DIVS_INV(210, 211, 212, 213, 214, 215, 216, 217, 218, 219), -+ DIVS_INV(220, 221, 222, 223, 224, 225, 226, 227, 228, 229), -+ DIVS_INV(230, 231, 232, 233, 234, 235, 236, 237, 238, 239), -+ DIVS_INV(240, 241, 242, 243, 244, 245, 246, 247, 248, 249), -+ DIV_INV(250), DIV_INV(251), DIV_INV(252), DIV_INV(253), -+ DIV_INV(254), DIV_INV(255), DIV_INV(256), -+ }; -+ -+ if (divisor == 0) -+ return 0; -+ else if (divisor == 1) -+ return dividend; -+ -+ if (WARN_ON(divisor - 2 >= ARRAY_SIZE(inv))) -+ return dividend; -+ -+ return ((u64)dividend * inv[divisor - 2]) >> 32; -+} -+ -+/* 6.3.6 inv_recenter_nonneg(v, m) */ -+static int inv_recenter_nonneg(int v, int m) -+{ -+ if (v > 2 * m) -+ return v; -+ -+ if (v & 1) -+ return m - ((v + 1) >> 1); -+ -+ return m + (v >> 1); -+} -+ -+/* -+ * part of 6.3.5 inv_remap_prob(deltaProb, prob) -+ * delta = inv_map_table[deltaProb] done by userspace -+ */ -+static int update_prob(int delta, int prob) -+{ -+ if (!delta) -+ return prob; -+ -+ return prob <= 128 ? -+ 1 + inv_recenter_nonneg(delta, prob - 1) : -+ 255 - inv_recenter_nonneg(delta, 255 - prob); -+} -+ -+/* Counterpart to 6.3.2 tx_mode_probs() */ -+static void update_tx_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->tx8); i++) { -+ u8 *p8x8 = probs->tx8[i]; -+ u8 *p16x16 = probs->tx16[i]; -+ u8 *p32x32 = probs->tx32[i]; -+ const u8 *d8x8 = deltas->tx8[i]; -+ const u8 *d16x16 = deltas->tx16[i]; -+ const u8 *d32x32 = deltas->tx32[i]; -+ -+ p8x8[0] = update_prob(d8x8[0], p8x8[0]); -+ p16x16[0] = update_prob(d16x16[0], p16x16[0]); -+ p16x16[1] = update_prob(d16x16[1], p16x16[1]); -+ p32x32[0] = update_prob(d32x32[0], p32x32[0]); -+ p32x32[1] = update_prob(d32x32[1], p32x32[1]); -+ p32x32[2] = update_prob(d32x32[2], p32x32[2]); -+ } -+} -+ -+#define BAND_6(band) ((band) == 0 ? 3 : 6) -+ -+static void update_coeff(const u8 deltas[6][6][3], u8 probs[6][6][3]) -+{ -+ int l, m, n; -+ -+ for (l = 0; l < 6; l++) -+ for (m = 0; m < BAND_6(l); m++) { -+ u8 *p = probs[l][m]; -+ const u8 *d = deltas[l][m]; -+ -+ for (n = 0; n < 3; n++) -+ p[n] = update_prob(d[n], p[n]); -+ } -+} -+ -+/* Counterpart to 6.3.7 read_coef_probs() */ -+static void update_coef_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ int i, j, k; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->coef); i++) { -+ for (j = 0; j < ARRAY_SIZE(probs->coef[0]); j++) -+ for (k = 0; k < ARRAY_SIZE(probs->coef[0][0]); k++) -+ update_coeff(deltas->coef[i][j][k], probs->coef[i][j][k]); -+ -+ if (deltas->tx_mode == i) -+ break; -+ } -+} -+ -+/* Counterpart to 6.3.8 read_skip_prob() */ -+static void update_skip_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->skip); i++) -+ probs->skip[i] = update_prob(deltas->skip[i], probs->skip[i]); -+} -+ -+/* Counterpart to 6.3.9 read_inter_mode_probs() */ -+static void update_inter_mode_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->inter_mode); i++) { -+ u8 *p = probs->inter_mode[i]; -+ const u8 *d = deltas->inter_mode[i]; -+ -+ p[0] = update_prob(d[0], p[0]); -+ p[1] = update_prob(d[1], p[1]); -+ p[2] = update_prob(d[2], p[2]); -+ } -+} -+ -+/* Counterpart to 6.3.10 read_interp_filter_probs() */ -+static void update_interp_filter_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->interp_filter); i++) { -+ u8 *p = probs->interp_filter[i]; -+ const u8 *d = deltas->interp_filter[i]; -+ -+ p[0] = update_prob(d[0], p[0]); -+ p[1] = update_prob(d[1], p[1]); -+ } -+} -+ -+/* Counterpart to 6.3.11 read_is_inter_probs() */ -+static void update_is_inter_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->is_inter); i++) -+ probs->is_inter[i] = update_prob(deltas->is_inter[i], probs->is_inter[i]); -+} -+ -+/* 6.3.12 frame_reference_mode() done entirely in userspace */ -+ -+/* Counterpart to 6.3.13 frame_reference_mode_probs() */ -+static void -+update_frame_reference_mode_probs(unsigned int reference_mode, -+ struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i; -+ -+ if (reference_mode == V4L2_VP9_REFERENCE_MODE_SELECT) -+ for (i = 0; i < ARRAY_SIZE(probs->comp_mode); i++) -+ probs->comp_mode[i] = update_prob(deltas->comp_mode[i], -+ probs->comp_mode[i]); -+ -+ if (reference_mode != V4L2_VP9_REFERENCE_MODE_COMPOUND_REFERENCE) -+ for (i = 0; i < ARRAY_SIZE(probs->single_ref); i++) { -+ u8 *p = probs->single_ref[i]; -+ const u8 *d = deltas->single_ref[i]; -+ -+ p[0] = update_prob(d[0], p[0]); -+ p[1] = update_prob(d[1], p[1]); -+ } -+ -+ if (reference_mode != V4L2_VP9_REFERENCE_MODE_SINGLE_REFERENCE) -+ for (i = 0; i < ARRAY_SIZE(probs->comp_ref); i++) -+ probs->comp_ref[i] = update_prob(deltas->comp_ref[i], probs->comp_ref[i]); -+} -+ -+/* Counterpart to 6.3.14 read_y_mode_probs() */ -+static void update_y_mode_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i, j; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->y_mode); i++) -+ for (j = 0; j < ARRAY_SIZE(probs->y_mode[0]); ++j) -+ probs->y_mode[i][j] = -+ update_prob(deltas->y_mode[i][j], probs->y_mode[i][j]); -+} -+ -+/* Counterpart to 6.3.15 read_partition_probs() */ -+static void update_partition_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas) -+{ -+ int i, j; -+ -+ for (i = 0; i < 4; i++) -+ for (j = 0; j < 4; j++) { -+ u8 *p = probs->partition[i * 4 + j]; -+ const u8 *d = deltas->partition[i * 4 + j]; -+ -+ p[0] = update_prob(d[0], p[0]); -+ p[1] = update_prob(d[1], p[1]); -+ p[2] = update_prob(d[2], p[2]); -+ } -+} -+ -+static inline int update_mv_prob(int delta, int prob) -+{ -+ if (!delta) -+ return prob; -+ -+ return delta; -+} -+ -+/* Counterpart to 6.3.16 mv_probs() */ -+static void update_mv_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ u8 *p = probs->mv.joint; -+ const u8 *d = deltas->mv.joint; -+ unsigned int i, j; -+ -+ p[0] = update_mv_prob(d[0], p[0]); -+ p[1] = update_mv_prob(d[1], p[1]); -+ p[2] = update_mv_prob(d[2], p[2]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->mv.sign); i++) { -+ p = probs->mv.sign; -+ d = deltas->mv.sign; -+ p[i] = update_mv_prob(d[i], p[i]); -+ -+ p = probs->mv.classes[i]; -+ d = deltas->mv.classes[i]; -+ for (j = 0; j < ARRAY_SIZE(probs->mv.classes[0]); j++) -+ p[j] = update_mv_prob(d[j], p[j]); -+ -+ p = probs->mv.class0_bit; -+ d = deltas->mv.class0_bit; -+ p[i] = update_mv_prob(d[i], p[i]); -+ -+ p = probs->mv.bits[i]; -+ d = deltas->mv.bits[i]; -+ for (j = 0; j < ARRAY_SIZE(probs->mv.bits[0]); j++) -+ p[j] = update_mv_prob(d[j], p[j]); -+ -+ for (j = 0; j < ARRAY_SIZE(probs->mv.class0_fr[0]); j++) { -+ p = probs->mv.class0_fr[i][j]; -+ d = deltas->mv.class0_fr[i][j]; -+ -+ p[0] = update_mv_prob(d[0], p[0]); -+ p[1] = update_mv_prob(d[1], p[1]); -+ p[2] = update_mv_prob(d[2], p[2]); -+ } -+ -+ p = probs->mv.fr[i]; -+ d = deltas->mv.fr[i]; -+ for (j = 0; j < ARRAY_SIZE(probs->mv.fr[i]); j++) -+ p[j] = update_mv_prob(d[j], p[j]); -+ -+ if (dec_params->flags & V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV) { -+ p = probs->mv.class0_hp; -+ d = deltas->mv.class0_hp; -+ p[i] = update_mv_prob(d[i], p[i]); -+ -+ p = probs->mv.hp; -+ d = deltas->mv.hp; -+ p[i] = update_mv_prob(d[i], p[i]); -+ } -+ } -+} -+ -+/* Counterpart to 6.3 compressed_header(), but parsing has been done in userspace. */ -+void v4l2_vp9_fw_update_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ if (deltas->tx_mode == V4L2_VP9_TX_MODE_SELECT) -+ update_tx_probs(probs, deltas); -+ -+ update_coef_probs(probs, deltas, dec_params); -+ -+ update_skip_probs(probs, deltas); -+ -+ if (dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME || -+ dec_params->flags & V4L2_VP9_FRAME_FLAG_INTRA_ONLY) -+ return; -+ -+ update_inter_mode_probs(probs, deltas); -+ -+ if (dec_params->interpolation_filter == V4L2_VP9_INTERP_FILTER_SWITCHABLE) -+ update_interp_filter_probs(probs, deltas); -+ -+ update_is_inter_probs(probs, deltas); -+ -+ update_frame_reference_mode_probs(dec_params->reference_mode, probs, deltas); -+ -+ update_y_mode_probs(probs, deltas); -+ -+ update_partition_probs(probs, deltas); -+ -+ update_mv_probs(probs, deltas, dec_params); -+} -+EXPORT_SYMBOL_GPL(v4l2_vp9_fw_update_probs); -+ -+u8 v4l2_vp9_reset_frame_ctx(const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct v4l2_vp9_frame_context *frame_context) -+{ -+ int i; -+ -+ u8 fctx_idx = dec_params->frame_context_idx; -+ -+ if (dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME || -+ dec_params->flags & V4L2_VP9_FRAME_FLAG_INTRA_ONLY || -+ dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) { -+ /* -+ * setup_past_independence() -+ * We do nothing here. Instead of storing default probs in some intermediate -+ * location and then copying from that location to appropriate contexts -+ * in save_probs() below, we skip that step and save default probs directly -+ * to appropriate contexts. -+ */ -+ if (dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME || -+ dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT || -+ dec_params->reset_frame_context == V4L2_VP9_RESET_FRAME_CTX_ALL) -+ for (i = 0; i < 4; ++i) -+ /* save_probs(i) */ -+ memcpy(&frame_context[i], &v4l2_vp9_default_probs, -+ sizeof(v4l2_vp9_default_probs)); -+ else if (dec_params->reset_frame_context == V4L2_VP9_RESET_FRAME_CTX_SPEC) -+ /* save_probs(fctx_idx) */ -+ memcpy(&frame_context[fctx_idx], &v4l2_vp9_default_probs, -+ sizeof(v4l2_vp9_default_probs)); -+ fctx_idx = 0; -+ } -+ -+ return fctx_idx; -+} -+EXPORT_SYMBOL_GPL(v4l2_vp9_reset_frame_ctx); -+ -+/* 8.4.1 Merge prob process */ -+static u8 merge_prob(u8 pre_prob, u32 ct0, u32 ct1, u16 count_sat, u32 max_update_factor) -+{ -+ u32 den, prob, count, factor; -+ -+ den = ct0 + ct1; -+ if (!den) { -+ /* -+ * prob = 128, count = 0, update_factor = 0 -+ * Round2's argument: pre_prob * 256 -+ * (pre_prob * 256 + 128) >> 8 == pre_prob -+ */ -+ return pre_prob; -+ } -+ -+ prob = clamp(((ct0 << 8) + (den >> 1)) / den, (u32)1, (u32)255); -+ count = min_t(u32, den, count_sat); -+ factor = fastdiv(max_update_factor * count, count_sat); -+ -+ /* -+ * Round2(pre_prob * (256 - factor) + prob * factor, 8) -+ * Round2(pre_prob * 256 + (prob - pre_prob) * factor, 8) -+ * (pre_prob * 256 >> 8) + (((prob - pre_prob) * factor + 128) >> 8) -+ */ -+ return pre_prob + (((prob - pre_prob) * factor + 128) >> 8); -+} -+ -+static inline u8 noncoef_merge_prob(u8 pre_prob, u32 ct0, u32 ct1) -+{ -+ return merge_prob(pre_prob, ct0, ct1, 20, 128); -+} -+ -+/* 8.4.2 Merge probs process */ -+/* -+ * merge_probs() is a recursive function in the spec. We avoid recursion in the kernel. -+ * That said, the "tree" parameter of merge_probs() controls how deep the recursion goes. -+ * It turns out that in all cases the recursive calls boil down to a short-ish series -+ * of merge_prob() invocations (note no "s"). -+ * -+ * Variant A -+ * --------- -+ * merge_probs(small_token_tree, 2): -+ * merge_prob(p[1], c[0], c[1] + c[2]) -+ * merge_prob(p[2], c[1], c[2]) -+ * -+ * Variant B -+ * --------- -+ * merge_probs(binary_tree, 0) or -+ * merge_probs(tx_size_8_tree, 0): -+ * merge_prob(p[0], c[0], c[1]) -+ * -+ * Variant C -+ * --------- -+ * merge_probs(inter_mode_tree, 0): -+ * merge_prob(p[0], c[2], c[1] + c[0] + c[3]) -+ * merge_prob(p[1], c[0], c[1] + c[3]) -+ * merge_prob(p[2], c[1], c[3]) -+ * -+ * Variant D -+ * --------- -+ * merge_probs(intra_mode_tree, 0): -+ * merge_prob(p[0], c[0], c[1] + ... + c[9]) -+ * merge_prob(p[1], c[9], c[1] + ... + c[8]) -+ * merge_prob(p[2], c[1], c[2] + ... + c[8]) -+ * merge_prob(p[3], c[2] + c[4] + c[5], c[3] + c[8] + c[6] + c[7]) -+ * merge_prob(p[4], c[2], c[4] + c[5]) -+ * merge_prob(p[5], c[4], c[5]) -+ * merge_prob(p[6], c[3], c[8] + c[6] + c[7]) -+ * merge_prob(p[7], c[8], c[6] + c[7]) -+ * merge_prob(p[8], c[6], c[7]) -+ * -+ * Variant E -+ * --------- -+ * merge_probs(partition_tree, 0) or -+ * merge_probs(tx_size_32_tree, 0) or -+ * merge_probs(mv_joint_tree, 0) or -+ * merge_probs(mv_fr_tree, 0): -+ * merge_prob(p[0], c[0], c[1] + c[2] + c[3]) -+ * merge_prob(p[1], c[1], c[2] + c[3]) -+ * merge_prob(p[2], c[2], c[3]) -+ * -+ * Variant F -+ * --------- -+ * merge_probs(interp_filter_tree, 0) or -+ * merge_probs(tx_size_16_tree, 0): -+ * merge_prob(p[0], c[0], c[1] + c[2]) -+ * merge_prob(p[1], c[1], c[2]) -+ * -+ * Variant G -+ * --------- -+ * merge_probs(mv_class_tree, 0): -+ * merge_prob(p[0], c[0], c[1] + ... + c[10]) -+ * merge_prob(p[1], c[1], c[2] + ... + c[10]) -+ * merge_prob(p[2], c[2] + c[3], c[4] + ... + c[10]) -+ * merge_prob(p[3], c[2], c[3]) -+ * merge_prob(p[4], c[4] + c[5], c[6] + ... + c[10]) -+ * merge_prob(p[5], c[4], c[5]) -+ * merge_prob(p[6], c[6], c[7] + ... + c[10]) -+ * merge_prob(p[7], c[7] + c[8], c[9] + c[10]) -+ * merge_prob(p[8], c[7], c[8]) -+ * merge_prob(p[9], c[9], [10]) -+ */ -+ -+static inline void merge_probs_variant_a(u8 *p, const u32 *c, u16 count_sat, u32 update_factor) -+{ -+ p[1] = merge_prob(p[1], c[0], c[1] + c[2], count_sat, update_factor); -+ p[2] = merge_prob(p[2], c[1], c[2], count_sat, update_factor); -+} -+ -+static inline void merge_probs_variant_b(u8 *p, const u32 *c, u16 count_sat, u32 update_factor) -+{ -+ p[0] = merge_prob(p[0], c[0], c[1], count_sat, update_factor); -+} -+ -+static inline void merge_probs_variant_c(u8 *p, const u32 *c) -+{ -+ p[0] = noncoef_merge_prob(p[0], c[2], c[1] + c[0] + c[3]); -+ p[1] = noncoef_merge_prob(p[1], c[0], c[1] + c[3]); -+ p[2] = noncoef_merge_prob(p[2], c[1], c[3]); -+} -+ -+static void merge_probs_variant_d(u8 *p, const u32 *c) -+{ -+ u32 sum = 0, s2; -+ -+ sum = c[1] + c[2] + c[3] + c[4] + c[5] + c[6] + c[7] + c[8] + c[9]; -+ -+ p[0] = noncoef_merge_prob(p[0], c[0], sum); -+ sum -= c[9]; -+ p[1] = noncoef_merge_prob(p[1], c[9], sum); -+ sum -= c[1]; -+ p[2] = noncoef_merge_prob(p[2], c[1], sum); -+ s2 = c[2] + c[4] + c[5]; -+ sum -= s2; -+ p[3] = noncoef_merge_prob(p[3], s2, sum); -+ s2 -= c[2]; -+ p[4] = noncoef_merge_prob(p[4], c[2], s2); -+ p[5] = noncoef_merge_prob(p[5], c[4], c[5]); -+ sum -= c[3]; -+ p[6] = noncoef_merge_prob(p[6], c[3], sum); -+ sum -= c[8]; -+ p[7] = noncoef_merge_prob(p[7], c[8], sum); -+ p[8] = noncoef_merge_prob(p[8], c[6], c[7]); -+} -+ -+static inline void merge_probs_variant_e(u8 *p, const u32 *c) -+{ -+ p[0] = noncoef_merge_prob(p[0], c[0], c[1] + c[2] + c[3]); -+ p[1] = noncoef_merge_prob(p[1], c[1], c[2] + c[3]); -+ p[2] = noncoef_merge_prob(p[2], c[2], c[3]); -+} -+ -+static inline void merge_probs_variant_f(u8 *p, const u32 *c) -+{ -+ p[0] = noncoef_merge_prob(p[0], c[0], c[1] + c[2]); -+ p[1] = noncoef_merge_prob(p[1], c[1], c[2]); -+} -+ -+static void merge_probs_variant_g(u8 *p, const u32 *c) -+{ -+ u32 sum; -+ -+ sum = c[1] + c[2] + c[3] + c[4] + c[5] + c[6] + c[7] + c[8] + c[9] + c[10]; -+ p[0] = noncoef_merge_prob(p[0], c[0], sum); -+ sum -= c[1]; -+ p[1] = noncoef_merge_prob(p[1], c[1], sum); -+ sum -= c[2] + c[3]; -+ p[2] = noncoef_merge_prob(p[2], c[2] + c[3], sum); -+ p[3] = noncoef_merge_prob(p[3], c[2], c[3]); -+ sum -= c[4] + c[5]; -+ p[4] = noncoef_merge_prob(p[4], c[4] + c[5], sum); -+ p[5] = noncoef_merge_prob(p[5], c[4], c[5]); -+ sum -= c[6]; -+ p[6] = noncoef_merge_prob(p[6], c[6], sum); -+ p[7] = noncoef_merge_prob(p[7], c[7] + c[8], c[9] + c[10]); -+ p[8] = noncoef_merge_prob(p[8], c[7], c[8]); -+ p[9] = noncoef_merge_prob(p[9], c[9], c[10]); -+} -+ -+/* 8.4.3 Coefficient probability adaptation process */ -+static inline void adapt_probs_variant_a_coef(u8 *p, const u32 *c, u32 update_factor) -+{ -+ merge_probs_variant_a(p, c, 24, update_factor); -+} -+ -+static inline void adapt_probs_variant_b_coef(u8 *p, const u32 *c, u32 update_factor) -+{ -+ merge_probs_variant_b(p, c, 24, update_factor); -+} -+ -+static void _adapt_coeff(unsigned int i, unsigned int j, unsigned int k, -+ struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_vp9_frame_symbol_counts *counts, -+ u32 uf) -+{ -+ s32 l, m; -+ -+ for (l = 0; l < ARRAY_SIZE(probs->coef[0][0][0]); l++) { -+ for (m = 0; m < BAND_6(l); m++) { -+ u8 *p = probs->coef[i][j][k][l][m]; -+ const u32 counts_more_coefs[2] = { -+ *counts->eob[i][j][k][l][m][1], -+ *counts->eob[i][j][k][l][m][0] - *counts->eob[i][j][k][l][m][1], -+ }; -+ -+ adapt_probs_variant_a_coef(p, *counts->coeff[i][j][k][l][m], uf); -+ adapt_probs_variant_b_coef(p, counts_more_coefs, uf); -+ } -+ } -+} -+ -+static void _adapt_coef_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_vp9_frame_symbol_counts *counts, -+ unsigned int uf) -+{ -+ unsigned int i, j, k; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->coef); i++) -+ for (j = 0; j < ARRAY_SIZE(probs->coef[0]); j++) -+ for (k = 0; k < ARRAY_SIZE(probs->coef[0][0]); k++) -+ _adapt_coeff(i, j, k, probs, counts, uf); -+} -+ -+void v4l2_vp9_adapt_coef_probs(struct v4l2_vp9_frame_context *probs, -+ struct v4l2_vp9_frame_symbol_counts *counts, -+ bool use_128, -+ bool frame_is_intra) -+{ -+ if (frame_is_intra) { -+ _adapt_coef_probs(probs, counts, 112); -+ } else { -+ if (use_128) -+ _adapt_coef_probs(probs, counts, 128); -+ else -+ _adapt_coef_probs(probs, counts, 112); -+ } -+} -+EXPORT_SYMBOL_GPL(v4l2_vp9_adapt_coef_probs); -+ -+/* 8.4.4 Non coefficient probability adaptation process, adapt_probs() */ -+static inline void adapt_probs_variant_b(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_b(p, c, 20, 128); -+} -+ -+static inline void adapt_probs_variant_c(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_c(p, c); -+} -+ -+static inline void adapt_probs_variant_d(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_d(p, c); -+} -+ -+static inline void adapt_probs_variant_e(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_e(p, c); -+} -+ -+static inline void adapt_probs_variant_f(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_f(p, c); -+} -+ -+static inline void adapt_probs_variant_g(u8 *p, const u32 *c) -+{ -+ merge_probs_variant_g(p, c); -+} -+ -+/* 8.4.4 Non coefficient probability adaptation process, adapt_prob() */ -+static inline u8 adapt_prob(u8 prob, const u32 counts[2]) -+{ -+ return noncoef_merge_prob(prob, counts[0], counts[1]); -+} -+ -+/* 8.4.4 Non coefficient probability adaptation process */ -+void v4l2_vp9_adapt_noncoef_probs(struct v4l2_vp9_frame_context *probs, -+ struct v4l2_vp9_frame_symbol_counts *counts, -+ u8 reference_mode, u8 interpolation_filter, u8 tx_mode, -+ u32 flags) -+{ -+ unsigned int i, j; -+ -+ for (i = 0; i < ARRAY_SIZE(probs->is_inter); i++) -+ probs->is_inter[i] = adapt_prob(probs->is_inter[i], (*counts->intra_inter)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->comp_mode); i++) -+ probs->comp_mode[i] = adapt_prob(probs->comp_mode[i], (*counts->comp)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->comp_ref); i++) -+ probs->comp_ref[i] = adapt_prob(probs->comp_ref[i], (*counts->comp_ref)[i]); -+ -+ if (reference_mode != V4L2_VP9_REFERENCE_MODE_COMPOUND_REFERENCE) -+ for (i = 0; i < ARRAY_SIZE(probs->single_ref); i++) -+ for (j = 0; j < ARRAY_SIZE(probs->single_ref[0]); j++) -+ probs->single_ref[i][j] = adapt_prob(probs->single_ref[i][j], -+ (*counts->single_ref)[i][j]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->inter_mode); i++) -+ adapt_probs_variant_c(probs->inter_mode[i], (*counts->mv_mode)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->y_mode); i++) -+ adapt_probs_variant_d(probs->y_mode[i], (*counts->y_mode)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->uv_mode); i++) -+ adapt_probs_variant_d(probs->uv_mode[i], (*counts->uv_mode)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->partition); i++) -+ adapt_probs_variant_e(probs->partition[i], (*counts->partition)[i]); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->skip); i++) -+ probs->skip[i] = adapt_prob(probs->skip[i], (*counts->skip)[i]); -+ -+ if (interpolation_filter == V4L2_VP9_INTERP_FILTER_SWITCHABLE) -+ for (i = 0; i < ARRAY_SIZE(probs->interp_filter); i++) -+ adapt_probs_variant_f(probs->interp_filter[i], (*counts->filter)[i]); -+ -+ if (tx_mode == V4L2_VP9_TX_MODE_SELECT) -+ for (i = 0; i < ARRAY_SIZE(probs->tx8); i++) { -+ adapt_probs_variant_b(probs->tx8[i], (*counts->tx8p)[i]); -+ adapt_probs_variant_f(probs->tx16[i], (*counts->tx16p)[i]); -+ adapt_probs_variant_e(probs->tx32[i], (*counts->tx32p)[i]); -+ } -+ -+ adapt_probs_variant_e(probs->mv.joint, *counts->mv_joint); -+ -+ for (i = 0; i < ARRAY_SIZE(probs->mv.sign); i++) { -+ probs->mv.sign[i] = adapt_prob(probs->mv.sign[i], (*counts->sign)[i]); -+ -+ adapt_probs_variant_g(probs->mv.classes[i], (*counts->classes)[i]); -+ -+ probs->mv.class0_bit[i] = adapt_prob(probs->mv.class0_bit[i], (*counts->class0)[i]); -+ -+ for (j = 0; j < ARRAY_SIZE(probs->mv.bits[0]); j++) -+ probs->mv.bits[i][j] = adapt_prob(probs->mv.bits[i][j], -+ (*counts->bits)[i][j]); -+ -+ for (j = 0; j < ARRAY_SIZE(probs->mv.class0_fr[0]); j++) -+ adapt_probs_variant_e(probs->mv.class0_fr[i][j], -+ (*counts->class0_fp)[i][j]); -+ -+ adapt_probs_variant_e(probs->mv.fr[i], (*counts->fp)[i]); -+ -+ if (!(flags & V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV)) -+ continue; -+ -+ probs->mv.class0_hp[i] = adapt_prob(probs->mv.class0_hp[i], -+ (*counts->class0_hp)[i]); -+ -+ probs->mv.hp[i] = adapt_prob(probs->mv.hp[i], (*counts->hp)[i]); -+ } -+} -+EXPORT_SYMBOL_GPL(v4l2_vp9_adapt_noncoef_probs); -+ -+bool -+v4l2_vp9_seg_feat_enabled(const u8 *feature_enabled, -+ unsigned int feature, -+ unsigned int segid) -+{ -+ u8 mask = V4L2_VP9_SEGMENT_FEATURE_ENABLED(feature); -+ -+ return !!(feature_enabled[segid] & mask); -+} -+EXPORT_SYMBOL_GPL(v4l2_vp9_seg_feat_enabled); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("V4L2 VP9 Helpers"); -+MODULE_AUTHOR("Andrzej Pietrasiewicz "); -diff --git a/include/media/v4l2-vp9.h b/include/media/v4l2-vp9.h -new file mode 100644 -index 000000000000..05478ad6d4ab ---- /dev/null -+++ b/include/media/v4l2-vp9.h -@@ -0,0 +1,233 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * Helper functions for vp9 codecs. -+ * -+ * Copyright (c) 2021 Collabora, Ltd. -+ * -+ * Author: Andrzej Pietrasiewicz -+ */ -+ -+#ifndef _MEDIA_V4L2_VP9_H -+#define _MEDIA_V4L2_VP9_H -+ -+#include -+ -+/** -+ * struct v4l2_vp9_frame_mv_context - motion vector-related probabilities -+ * -+ * @joint: motion vector joint probabilities. -+ * @sign: motion vector sign probabilities. -+ * @classes: motion vector class probabilities. -+ * @class0_bit: motion vector class0 bit probabilities. -+ * @bits: motion vector bits probabilities. -+ * @class0_fr: motion vector class0 fractional bit probabilities. -+ * @fr: motion vector fractional bit probabilities. -+ * @class0_hp: motion vector class0 high precision fractional bit probabilities. -+ * @hp: motion vector high precision fractional bit probabilities. -+ * -+ * A member of v4l2_vp9_frame_context. -+ */ -+struct v4l2_vp9_frame_mv_context { -+ u8 joint[3]; -+ u8 sign[2]; -+ u8 classes[2][10]; -+ u8 class0_bit[2]; -+ u8 bits[2][10]; -+ u8 class0_fr[2][2][3]; -+ u8 fr[2][3]; -+ u8 class0_hp[2]; -+ u8 hp[2]; -+}; -+ -+/** -+ * struct v4l2_vp9_frame_context - frame probabilities, including motion-vector related -+ * -+ * @tx8: TX 8x8 probabilities. -+ * @tx16: TX 16x16 probabilities. -+ * @tx32: TX 32x32 probabilities. -+ * @coef: coefficient probabilities. -+ * @skip: skip probabilities. -+ * @inter_mode: inter mode probabilities. -+ * @interp_filter: interpolation filter probabilities. -+ * @is_inter: is inter-block probabilities. -+ * @comp_mode: compound prediction mode probabilities. -+ * @single_ref: single ref probabilities. -+ * @comp_ref: compound ref probabilities. -+ * @y_mode: Y prediction mode probabilities. -+ * @uv_mode: UV prediction mode probabilities. -+ * @partition: partition probabilities. -+ * @mv: motion vector probabilities. -+ * -+ * Drivers which need to keep track of frame context(s) can use this struct. -+ * The members correspond to probability tables, which are specified only implicitly in the -+ * vp9 spec. Section 10.5 "Default probability tables" contains all the types of involved -+ * tables, i.e. the actual tables are of the same kind, and when they are reset (which is -+ * mandated by the spec sometimes) they are overwritten with values from the default tables. -+ */ -+struct v4l2_vp9_frame_context { -+ u8 tx8[2][1]; -+ u8 tx16[2][2]; -+ u8 tx32[2][3]; -+ u8 coef[4][2][2][6][6][3]; -+ u8 skip[3]; -+ u8 inter_mode[7][3]; -+ u8 interp_filter[4][2]; -+ u8 is_inter[4]; -+ u8 comp_mode[5]; -+ u8 single_ref[5][2]; -+ u8 comp_ref[5]; -+ u8 y_mode[4][9]; -+ u8 uv_mode[10][9]; -+ u8 partition[16][3]; -+ -+ struct v4l2_vp9_frame_mv_context mv; -+}; -+ -+/** -+ * struct v4l2_vp9_frame_symbol_counts - pointers to arrays of symbol counts -+ * -+ * @partition: partition counts. -+ * @skip: skip counts. -+ * @intra_inter: is inter-block counts. -+ * @tx32p: TX32 counts. -+ * @tx16p: TX16 counts. -+ * @tx8p: TX8 counts. -+ * @y_mode: Y prediction mode counts. -+ * @uv_mode: UV prediction mode counts. -+ * @comp: compound prediction mode counts. -+ * @comp_ref: compound ref counts. -+ * @single_ref: single ref counts. -+ * @mv_mode: inter mode counts. -+ * @filter: interpolation filter counts. -+ * @mv_joint: motion vector joint counts. -+ * @sign: motion vector sign counts. -+ * @classes: motion vector class counts. -+ * @class0: motion vector class0 bit counts. -+ * @bits: motion vector bits counts. -+ * @class0_fp: motion vector class0 fractional bit counts. -+ * @fp: motion vector fractional bit counts. -+ * @class0_hp: motion vector class0 high precision fractional bit counts. -+ * @hp: motion vector high precision fractional bit counts. -+ * @coeff: coefficient counts. -+ * @eob: eob counts -+ * -+ * The fields correspond to what is specified in section 8.3 "Clear counts process" of the spec. -+ * Different pieces of hardware can report the counts in different order, so we cannot rely on -+ * simply overlaying a struct on a relevant block of memory. Instead we provide pointers to -+ * arrays or array of pointers to arrays in case of coeff, or array of pointers for eob. -+ */ -+struct v4l2_vp9_frame_symbol_counts { -+ u32 (*partition)[16][4]; -+ u32 (*skip)[3][2]; -+ u32 (*intra_inter)[4][2]; -+ u32 (*tx32p)[2][4]; -+ u32 (*tx16p)[2][4]; -+ u32 (*tx8p)[2][2]; -+ u32 (*y_mode)[4][10]; -+ u32 (*uv_mode)[10][10]; -+ u32 (*comp)[5][2]; -+ u32 (*comp_ref)[5][2]; -+ u32 (*single_ref)[5][2][2]; -+ u32 (*mv_mode)[7][4]; -+ u32 (*filter)[4][3]; -+ u32 (*mv_joint)[4]; -+ u32 (*sign)[2][2]; -+ u32 (*classes)[2][11]; -+ u32 (*class0)[2][2]; -+ u32 (*bits)[2][10][2]; -+ u32 (*class0_fp)[2][2][4]; -+ u32 (*fp)[2][4]; -+ u32 (*class0_hp)[2][2]; -+ u32 (*hp)[2][2]; -+ u32 (*coeff[4][2][2][6][6])[3]; -+ u32 *eob[4][2][2][6][6][2]; -+}; -+ -+extern const u8 v4l2_vp9_kf_y_mode_prob[10][10][9]; /* Section 10.4 of the spec */ -+extern const u8 v4l2_vp9_kf_partition_probs[16][3]; /* Section 10.4 of the spec */ -+extern const u8 v4l2_vp9_kf_uv_mode_prob[10][9]; /* Section 10.4 of the spec */ -+extern const struct v4l2_vp9_frame_context v4l2_vp9_default_probs; /* Section 10.5 of the spec */ -+ -+/** -+ * v4l2_vp9_fw_update_probs() - Perform forward update of vp9 probabilities -+ * -+ * @probs: current probabilities values -+ * @deltas: delta values from compressed header -+ * @dec_params: vp9 frame decoding parameters -+ * -+ * This function performs forward updates of probabilities for the vp9 boolean decoder. -+ * The frame header can contain a directive to update the probabilities (deltas), if so, then -+ * the deltas are provided in the header, too. The userspace parses those and passes the said -+ * deltas struct to the kernel. -+ */ -+void v4l2_vp9_fw_update_probs(struct v4l2_vp9_frame_context *probs, -+ const struct v4l2_ctrl_vp9_compressed_hdr *deltas, -+ const struct v4l2_ctrl_vp9_frame *dec_params); -+ -+/** -+ * v4l2_vp9_reset_frame_ctx() - Reset appropriate frame context -+ * -+ * @dec_params: vp9 frame decoding parameters -+ * @frame_context: array of the 4 frame contexts -+ * -+ * This function resets appropriate frame contexts, based on what's in dec_params. -+ * -+ * Returns the frame context index after the update, which might be reset to zero if -+ * mandated by the spec. -+ */ -+u8 v4l2_vp9_reset_frame_ctx(const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct v4l2_vp9_frame_context *frame_context); -+ -+/** -+ * v4l2_vp9_adapt_coef_probs() - Perform backward update of vp9 coefficients probabilities -+ * -+ * @probs: current probabilities values -+ * @counts: values of symbol counts after the current frame has been decoded -+ * @use_128: flag to request that 128 is used as update factor if true, otherwise 112 is used -+ * @frame_is_intra: flag indicating that FrameIsIntra is true -+ * -+ * This function performs backward updates of coefficients probabilities for the vp9 boolean -+ * decoder. After a frame has been decoded the counts of how many times a given symbol has -+ * occurred are known and are used to update the probability of each symbol. -+ */ -+void v4l2_vp9_adapt_coef_probs(struct v4l2_vp9_frame_context *probs, -+ struct v4l2_vp9_frame_symbol_counts *counts, -+ bool use_128, -+ bool frame_is_intra); -+ -+/** -+ * v4l2_vp9_adapt_noncoef_probs() - Perform backward update of vp9 non-coefficients probabilities -+ * -+ * @probs: current probabilities values -+ * @counts: values of symbol counts after the current frame has been decoded -+ * @reference_mode: specifies the type of inter prediction to be used. See -+ * &v4l2_vp9_reference_mode for more details -+ * @interpolation_filter: specifies the filter selection used for performing inter prediction. -+ * See &v4l2_vp9_interpolation_filter for more details -+ * @tx_mode: specifies the TX mode. See &v4l2_vp9_tx_mode for more details -+ * @flags: combination of V4L2_VP9_FRAME_FLAG_* flags -+ * -+ * This function performs backward updates of non-coefficients probabilities for the vp9 boolean -+ * decoder. After a frame has been decoded the counts of how many times a given symbol has -+ * occurred are known and are used to update the probability of each symbol. -+ */ -+void v4l2_vp9_adapt_noncoef_probs(struct v4l2_vp9_frame_context *probs, -+ struct v4l2_vp9_frame_symbol_counts *counts, -+ u8 reference_mode, u8 interpolation_filter, u8 tx_mode, -+ u32 flags); -+ -+/** -+ * v4l2_vp9_seg_feat_enabled() - Check if a segmentation feature is enabled -+ * -+ * @feature_enabled: array of 8-bit flags (for all segments) -+ * @feature: id of the feature to check -+ * @segid: id of the segment to look up -+ * -+ * This function returns true if a given feature is active in a given segment. -+ */ -+bool -+v4l2_vp9_seg_feat_enabled(const u8 *feature_enabled, -+ unsigned int feature, -+ unsigned int segid); -+ -+#endif /* _MEDIA_V4L2_VP9_H */ - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Wed, 17 Nov 2021 12:52:56 +0100 -Subject: [PATCH] media: rkvdec: Add the VP9 backend - -The Rockchip VDEC supports VP9 profile 0 up to 4096x2304@30fps. Add -a backend for this new format. - -Signed-off-by: Boris Brezillon -Signed-off-by: Ezequiel Garcia -Signed-off-by: Adrian Ratiu -Co-developed-by: Andrzej Pietrasiewicz -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/rkvdec/Kconfig | 1 + - drivers/staging/media/rkvdec/Makefile | 2 +- - drivers/staging/media/rkvdec/rkvdec-vp9.c | 1072 +++++++++++++++++++++ - drivers/staging/media/rkvdec/rkvdec.c | 41 +- - drivers/staging/media/rkvdec/rkvdec.h | 12 +- - 5 files changed, 1121 insertions(+), 7 deletions(-) - create mode 100644 drivers/staging/media/rkvdec/rkvdec-vp9.c - -diff --git a/drivers/staging/media/rkvdec/Kconfig b/drivers/staging/media/rkvdec/Kconfig -index c02199b5e0fd..dc7292f346fa 100644 ---- a/drivers/staging/media/rkvdec/Kconfig -+++ b/drivers/staging/media/rkvdec/Kconfig -@@ -9,6 +9,7 @@ config VIDEO_ROCKCHIP_VDEC - select VIDEOBUF2_VMALLOC - select V4L2_MEM2MEM_DEV - select V4L2_H264 -+ select V4L2_VP9 - help - Support for the Rockchip Video Decoder IP present on Rockchip SoCs, - which accelerates video decoding. -diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile -index c08fed0a39f9..cb86b429cfaa 100644 ---- a/drivers/staging/media/rkvdec/Makefile -+++ b/drivers/staging/media/rkvdec/Makefile -@@ -1,3 +1,3 @@ - obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o - --rockchip-vdec-y += rkvdec.o rkvdec-h264.o -+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o -diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c -new file mode 100644 -index 000000000000..311a12656072 ---- /dev/null -+++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c -@@ -0,0 +1,1072 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip Video Decoder VP9 backend -+ * -+ * Copyright (C) 2019 Collabora, Ltd. -+ * Boris Brezillon -+ * Copyright (C) 2021 Collabora, Ltd. -+ * Andrzej Pietrasiewicz -+ * -+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd. -+ * Alpha Lin -+ */ -+ -+/* -+ * For following the vp9 spec please start reading this driver -+ * code from rkvdec_vp9_run() followed by rkvdec_vp9_done(). -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include "rkvdec.h" -+#include "rkvdec-regs.h" -+ -+#define RKVDEC_VP9_PROBE_SIZE 4864 -+#define RKVDEC_VP9_COUNT_SIZE 13232 -+#define RKVDEC_VP9_MAX_SEGMAP_SIZE 73728 -+ -+struct rkvdec_vp9_intra_mode_probs { -+ u8 y_mode[105]; -+ u8 uv_mode[23]; -+}; -+ -+struct rkvdec_vp9_intra_only_frame_probs { -+ u8 coef_intra[4][2][128]; -+ struct rkvdec_vp9_intra_mode_probs intra_mode[10]; -+}; -+ -+struct rkvdec_vp9_inter_frame_probs { -+ u8 y_mode[4][9]; -+ u8 comp_mode[5]; -+ u8 comp_ref[5]; -+ u8 single_ref[5][2]; -+ u8 inter_mode[7][3]; -+ u8 interp_filter[4][2]; -+ u8 padding0[11]; -+ u8 coef[2][4][2][128]; -+ u8 uv_mode_0_2[3][9]; -+ u8 padding1[5]; -+ u8 uv_mode_3_5[3][9]; -+ u8 padding2[5]; -+ u8 uv_mode_6_8[3][9]; -+ u8 padding3[5]; -+ u8 uv_mode_9[9]; -+ u8 padding4[7]; -+ u8 padding5[16]; -+ struct { -+ u8 joint[3]; -+ u8 sign[2]; -+ u8 classes[2][10]; -+ u8 class0_bit[2]; -+ u8 bits[2][10]; -+ u8 class0_fr[2][2][3]; -+ u8 fr[2][3]; -+ u8 class0_hp[2]; -+ u8 hp[2]; -+ } mv; -+}; -+ -+struct rkvdec_vp9_probs { -+ u8 partition[16][3]; -+ u8 pred[3]; -+ u8 tree[7]; -+ u8 skip[3]; -+ u8 tx32[2][3]; -+ u8 tx16[2][2]; -+ u8 tx8[2][1]; -+ u8 is_inter[4]; -+ /* 128 bit alignment */ -+ u8 padding0[3]; -+ union { -+ struct rkvdec_vp9_inter_frame_probs inter; -+ struct rkvdec_vp9_intra_only_frame_probs intra_only; -+ }; -+}; -+ -+/* Data structure describing auxiliary buffer format. */ -+struct rkvdec_vp9_priv_tbl { -+ struct rkvdec_vp9_probs probs; -+ u8 segmap[2][RKVDEC_VP9_MAX_SEGMAP_SIZE]; -+}; -+ -+struct rkvdec_vp9_refs_counts { -+ u32 eob[2]; -+ u32 coeff[3]; -+}; -+ -+struct rkvdec_vp9_inter_frame_symbol_counts { -+ u32 partition[16][4]; -+ u32 skip[3][2]; -+ u32 inter[4][2]; -+ u32 tx32p[2][4]; -+ u32 tx16p[2][4]; -+ u32 tx8p[2][2]; -+ u32 y_mode[4][10]; -+ u32 uv_mode[10][10]; -+ u32 comp[5][2]; -+ u32 comp_ref[5][2]; -+ u32 single_ref[5][2][2]; -+ u32 mv_mode[7][4]; -+ u32 filter[4][3]; -+ u32 mv_joint[4]; -+ u32 sign[2][2]; -+ /* add 1 element for align */ -+ u32 classes[2][11 + 1]; -+ u32 class0[2][2]; -+ u32 bits[2][10][2]; -+ u32 class0_fp[2][2][4]; -+ u32 fp[2][4]; -+ u32 class0_hp[2][2]; -+ u32 hp[2][2]; -+ struct rkvdec_vp9_refs_counts ref_cnt[2][4][2][6][6]; -+}; -+ -+struct rkvdec_vp9_intra_frame_symbol_counts { -+ u32 partition[4][4][4]; -+ u32 skip[3][2]; -+ u32 intra[4][2]; -+ u32 tx32p[2][4]; -+ u32 tx16p[2][4]; -+ u32 tx8p[2][2]; -+ struct rkvdec_vp9_refs_counts ref_cnt[2][4][2][6][6]; -+}; -+ -+struct rkvdec_vp9_run { -+ struct rkvdec_run base; -+ const struct v4l2_ctrl_vp9_frame *decode_params; -+}; -+ -+struct rkvdec_vp9_frame_info { -+ u32 valid : 1; -+ u32 segmapid : 1; -+ u32 frame_context_idx : 2; -+ u32 reference_mode : 2; -+ u32 tx_mode : 3; -+ u32 interpolation_filter : 3; -+ u32 flags; -+ u64 timestamp; -+ struct v4l2_vp9_segmentation seg; -+ struct v4l2_vp9_loop_filter lf; -+}; -+ -+struct rkvdec_vp9_ctx { -+ struct rkvdec_aux_buf priv_tbl; -+ struct rkvdec_aux_buf count_tbl; -+ struct v4l2_vp9_frame_symbol_counts inter_cnts; -+ struct v4l2_vp9_frame_symbol_counts intra_cnts; -+ struct v4l2_vp9_frame_context probability_tables; -+ struct v4l2_vp9_frame_context frame_context[4]; -+ struct rkvdec_vp9_frame_info cur; -+ struct rkvdec_vp9_frame_info last; -+}; -+ -+static void write_coeff_plane(const u8 coef[6][6][3], u8 *coeff_plane) -+{ -+ unsigned int idx = 0, byte_count = 0; -+ int k, m, n; -+ u8 p; -+ -+ for (k = 0; k < 6; k++) { -+ for (m = 0; m < 6; m++) { -+ for (n = 0; n < 3; n++) { -+ p = coef[k][m][n]; -+ coeff_plane[idx++] = p; -+ byte_count++; -+ if (byte_count == 27) { -+ idx += 5; -+ byte_count = 0; -+ } -+ } -+ } -+ } -+} -+ -+static void init_intra_only_probs(struct rkvdec_ctx *ctx, -+ const struct rkvdec_vp9_run *run) -+{ -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ struct rkvdec_vp9_priv_tbl *tbl = vp9_ctx->priv_tbl.cpu; -+ struct rkvdec_vp9_intra_only_frame_probs *rkprobs; -+ const struct v4l2_vp9_frame_context *probs; -+ unsigned int i, j, k; -+ -+ rkprobs = &tbl->probs.intra_only; -+ probs = &vp9_ctx->probability_tables; -+ -+ /* -+ * intra only 149 x 128 bits ,aligned to 152 x 128 bits coeff related -+ * prob 64 x 128 bits -+ */ -+ for (i = 0; i < ARRAY_SIZE(probs->coef); i++) { -+ for (j = 0; j < ARRAY_SIZE(probs->coef[0]); j++) -+ write_coeff_plane(probs->coef[i][j][0], -+ rkprobs->coef_intra[i][j]); -+ } -+ -+ /* intra mode prob 80 x 128 bits */ -+ for (i = 0; i < ARRAY_SIZE(v4l2_vp9_kf_y_mode_prob); i++) { -+ unsigned int byte_count = 0; -+ int idx = 0; -+ -+ /* vp9_kf_y_mode_prob */ -+ for (j = 0; j < ARRAY_SIZE(v4l2_vp9_kf_y_mode_prob[0]); j++) { -+ for (k = 0; k < ARRAY_SIZE(v4l2_vp9_kf_y_mode_prob[0][0]); -+ k++) { -+ u8 val = v4l2_vp9_kf_y_mode_prob[i][j][k]; -+ -+ rkprobs->intra_mode[i].y_mode[idx++] = val; -+ byte_count++; -+ if (byte_count == 27) { -+ byte_count = 0; -+ idx += 5; -+ } -+ } -+ } -+ -+ } -+ -+ for (i = 0; i < sizeof(v4l2_vp9_kf_uv_mode_prob); ++i) { -+ const u8 *ptr = (const u8 *)v4l2_vp9_kf_uv_mode_prob; -+ -+ rkprobs->intra_mode[i / 23].uv_mode[i % 23] = ptr[i]; -+ } -+} -+ -+static void init_inter_probs(struct rkvdec_ctx *ctx, -+ const struct rkvdec_vp9_run *run) -+{ -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ struct rkvdec_vp9_priv_tbl *tbl = vp9_ctx->priv_tbl.cpu; -+ struct rkvdec_vp9_inter_frame_probs *rkprobs; -+ const struct v4l2_vp9_frame_context *probs; -+ unsigned int i, j, k; -+ -+ rkprobs = &tbl->probs.inter; -+ probs = &vp9_ctx->probability_tables; -+ -+ /* -+ * inter probs -+ * 151 x 128 bits, aligned to 152 x 128 bits -+ * inter only -+ * intra_y_mode & inter_block info 6 x 128 bits -+ */ -+ -+ memcpy(rkprobs->y_mode, probs->y_mode, sizeof(rkprobs->y_mode)); -+ memcpy(rkprobs->comp_mode, probs->comp_mode, -+ sizeof(rkprobs->comp_mode)); -+ memcpy(rkprobs->comp_ref, probs->comp_ref, -+ sizeof(rkprobs->comp_ref)); -+ memcpy(rkprobs->single_ref, probs->single_ref, -+ sizeof(rkprobs->single_ref)); -+ memcpy(rkprobs->inter_mode, probs->inter_mode, -+ sizeof(rkprobs->inter_mode)); -+ memcpy(rkprobs->interp_filter, probs->interp_filter, -+ sizeof(rkprobs->interp_filter)); -+ -+ /* 128 x 128 bits coeff related */ -+ for (i = 0; i < ARRAY_SIZE(probs->coef); i++) { -+ for (j = 0; j < ARRAY_SIZE(probs->coef[0]); j++) { -+ for (k = 0; k < ARRAY_SIZE(probs->coef[0][0]); k++) -+ write_coeff_plane(probs->coef[i][j][k], -+ rkprobs->coef[k][i][j]); -+ } -+ } -+ -+ /* intra uv mode 6 x 128 */ -+ memcpy(rkprobs->uv_mode_0_2, &probs->uv_mode[0], -+ sizeof(rkprobs->uv_mode_0_2)); -+ memcpy(rkprobs->uv_mode_3_5, &probs->uv_mode[3], -+ sizeof(rkprobs->uv_mode_3_5)); -+ memcpy(rkprobs->uv_mode_6_8, &probs->uv_mode[6], -+ sizeof(rkprobs->uv_mode_6_8)); -+ memcpy(rkprobs->uv_mode_9, &probs->uv_mode[9], -+ sizeof(rkprobs->uv_mode_9)); -+ -+ /* mv related 6 x 128 */ -+ memcpy(rkprobs->mv.joint, probs->mv.joint, -+ sizeof(rkprobs->mv.joint)); -+ memcpy(rkprobs->mv.sign, probs->mv.sign, -+ sizeof(rkprobs->mv.sign)); -+ memcpy(rkprobs->mv.classes, probs->mv.classes, -+ sizeof(rkprobs->mv.classes)); -+ memcpy(rkprobs->mv.class0_bit, probs->mv.class0_bit, -+ sizeof(rkprobs->mv.class0_bit)); -+ memcpy(rkprobs->mv.bits, probs->mv.bits, -+ sizeof(rkprobs->mv.bits)); -+ memcpy(rkprobs->mv.class0_fr, probs->mv.class0_fr, -+ sizeof(rkprobs->mv.class0_fr)); -+ memcpy(rkprobs->mv.fr, probs->mv.fr, -+ sizeof(rkprobs->mv.fr)); -+ memcpy(rkprobs->mv.class0_hp, probs->mv.class0_hp, -+ sizeof(rkprobs->mv.class0_hp)); -+ memcpy(rkprobs->mv.hp, probs->mv.hp, -+ sizeof(rkprobs->mv.hp)); -+} -+ -+static void init_probs(struct rkvdec_ctx *ctx, -+ const struct rkvdec_vp9_run *run) -+{ -+ const struct v4l2_ctrl_vp9_frame *dec_params; -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ struct rkvdec_vp9_priv_tbl *tbl = vp9_ctx->priv_tbl.cpu; -+ struct rkvdec_vp9_probs *rkprobs = &tbl->probs; -+ const struct v4l2_vp9_segmentation *seg; -+ const struct v4l2_vp9_frame_context *probs; -+ bool intra_only; -+ -+ dec_params = run->decode_params; -+ probs = &vp9_ctx->probability_tables; -+ seg = &dec_params->seg; -+ -+ memset(rkprobs, 0, sizeof(*rkprobs)); -+ -+ intra_only = !!(dec_params->flags & -+ (V4L2_VP9_FRAME_FLAG_KEY_FRAME | -+ V4L2_VP9_FRAME_FLAG_INTRA_ONLY)); -+ -+ /* sb info 5 x 128 bit */ -+ memcpy(rkprobs->partition, -+ intra_only ? v4l2_vp9_kf_partition_probs : probs->partition, -+ sizeof(rkprobs->partition)); -+ -+ memcpy(rkprobs->pred, seg->pred_probs, sizeof(rkprobs->pred)); -+ memcpy(rkprobs->tree, seg->tree_probs, sizeof(rkprobs->tree)); -+ memcpy(rkprobs->skip, probs->skip, sizeof(rkprobs->skip)); -+ memcpy(rkprobs->tx32, probs->tx32, sizeof(rkprobs->tx32)); -+ memcpy(rkprobs->tx16, probs->tx16, sizeof(rkprobs->tx16)); -+ memcpy(rkprobs->tx8, probs->tx8, sizeof(rkprobs->tx8)); -+ memcpy(rkprobs->is_inter, probs->is_inter, sizeof(rkprobs->is_inter)); -+ -+ if (intra_only) -+ init_intra_only_probs(ctx, run); -+ else -+ init_inter_probs(ctx, run); -+} -+ -+struct rkvdec_vp9_ref_reg { -+ u32 reg_frm_size; -+ u32 reg_hor_stride; -+ u32 reg_y_stride; -+ u32 reg_yuv_stride; -+ u32 reg_ref_base; -+}; -+ -+static struct rkvdec_vp9_ref_reg ref_regs[] = { -+ { -+ .reg_frm_size = RKVDEC_REG_VP9_FRAME_SIZE(0), -+ .reg_hor_stride = RKVDEC_VP9_HOR_VIRSTRIDE(0), -+ .reg_y_stride = RKVDEC_VP9_LAST_FRAME_YSTRIDE, -+ .reg_yuv_stride = RKVDEC_VP9_LAST_FRAME_YUVSTRIDE, -+ .reg_ref_base = RKVDEC_REG_VP9_LAST_FRAME_BASE, -+ }, -+ { -+ .reg_frm_size = RKVDEC_REG_VP9_FRAME_SIZE(1), -+ .reg_hor_stride = RKVDEC_VP9_HOR_VIRSTRIDE(1), -+ .reg_y_stride = RKVDEC_VP9_GOLDEN_FRAME_YSTRIDE, -+ .reg_yuv_stride = 0, -+ .reg_ref_base = RKVDEC_REG_VP9_GOLDEN_FRAME_BASE, -+ }, -+ { -+ .reg_frm_size = RKVDEC_REG_VP9_FRAME_SIZE(2), -+ .reg_hor_stride = RKVDEC_VP9_HOR_VIRSTRIDE(2), -+ .reg_y_stride = RKVDEC_VP9_ALTREF_FRAME_YSTRIDE, -+ .reg_yuv_stride = 0, -+ .reg_ref_base = RKVDEC_REG_VP9_ALTREF_FRAME_BASE, -+ } -+}; -+ -+static struct rkvdec_decoded_buffer * -+get_ref_buf(struct rkvdec_ctx *ctx, struct vb2_v4l2_buffer *dst, u64 timestamp) -+{ -+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -+ int buf_idx; -+ -+ /* -+ * If a ref is unused or invalid, address of current destination -+ * buffer is returned. -+ */ -+ buf_idx = vb2_find_timestamp(cap_q, timestamp, 0); -+ if (buf_idx < 0) -+ return vb2_to_rkvdec_decoded_buf(&dst->vb2_buf); -+ -+ return vb2_to_rkvdec_decoded_buf(vb2_get_buffer(cap_q, buf_idx)); -+} -+ -+static dma_addr_t get_mv_base_addr(struct rkvdec_decoded_buffer *buf) -+{ -+ unsigned int aligned_pitch, aligned_height, yuv_len; -+ -+ aligned_height = round_up(buf->vp9.height, 64); -+ aligned_pitch = round_up(buf->vp9.width * buf->vp9.bit_depth, 512) / 8; -+ yuv_len = (aligned_height * aligned_pitch * 3) / 2; -+ -+ return vb2_dma_contig_plane_dma_addr(&buf->base.vb.vb2_buf, 0) + -+ yuv_len; -+} -+ -+static void config_ref_registers(struct rkvdec_ctx *ctx, -+ const struct rkvdec_vp9_run *run, -+ struct rkvdec_decoded_buffer *ref_buf, -+ struct rkvdec_vp9_ref_reg *ref_reg) -+{ -+ unsigned int aligned_pitch, aligned_height, y_len, yuv_len; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ -+ aligned_height = round_up(ref_buf->vp9.height, 64); -+ writel_relaxed(RKVDEC_VP9_FRAMEWIDTH(ref_buf->vp9.width) | -+ RKVDEC_VP9_FRAMEHEIGHT(ref_buf->vp9.height), -+ rkvdec->regs + ref_reg->reg_frm_size); -+ -+ writel_relaxed(vb2_dma_contig_plane_dma_addr(&ref_buf->base.vb.vb2_buf, 0), -+ rkvdec->regs + ref_reg->reg_ref_base); -+ -+ if (&ref_buf->base.vb == run->base.bufs.dst) -+ return; -+ -+ aligned_pitch = round_up(ref_buf->vp9.width * ref_buf->vp9.bit_depth, 512) / 8; -+ y_len = aligned_height * aligned_pitch; -+ yuv_len = (y_len * 3) / 2; -+ -+ writel_relaxed(RKVDEC_HOR_Y_VIRSTRIDE(aligned_pitch / 16) | -+ RKVDEC_HOR_UV_VIRSTRIDE(aligned_pitch / 16), -+ rkvdec->regs + ref_reg->reg_hor_stride); -+ writel_relaxed(RKVDEC_VP9_REF_YSTRIDE(y_len / 16), -+ rkvdec->regs + ref_reg->reg_y_stride); -+ -+ if (!ref_reg->reg_yuv_stride) -+ return; -+ -+ writel_relaxed(RKVDEC_VP9_REF_YUVSTRIDE(yuv_len / 16), -+ rkvdec->regs + ref_reg->reg_yuv_stride); -+} -+ -+static void config_seg_registers(struct rkvdec_ctx *ctx, unsigned int segid) -+{ -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ const struct v4l2_vp9_segmentation *seg; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ s16 feature_val; -+ int feature_id; -+ u32 val = 0; -+ -+ seg = vp9_ctx->last.valid ? &vp9_ctx->last.seg : &vp9_ctx->cur.seg; -+ feature_id = V4L2_VP9_SEG_LVL_ALT_Q; -+ if (v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid)) { -+ feature_val = seg->feature_data[segid][feature_id]; -+ val |= RKVDEC_SEGID_FRAME_QP_DELTA_EN(1) | -+ RKVDEC_SEGID_FRAME_QP_DELTA(feature_val); -+ } -+ -+ feature_id = V4L2_VP9_SEG_LVL_ALT_L; -+ if (v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid)) { -+ feature_val = seg->feature_data[segid][feature_id]; -+ val |= RKVDEC_SEGID_FRAME_LOOPFILTER_VALUE_EN(1) | -+ RKVDEC_SEGID_FRAME_LOOPFILTER_VALUE(feature_val); -+ } -+ -+ feature_id = V4L2_VP9_SEG_LVL_REF_FRAME; -+ if (v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid)) { -+ feature_val = seg->feature_data[segid][feature_id]; -+ val |= RKVDEC_SEGID_REFERINFO_EN(1) | -+ RKVDEC_SEGID_REFERINFO(feature_val); -+ } -+ -+ feature_id = V4L2_VP9_SEG_LVL_SKIP; -+ if (v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid)) -+ val |= RKVDEC_SEGID_FRAME_SKIP_EN(1); -+ -+ if (!segid && -+ (seg->flags & V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE)) -+ val |= RKVDEC_SEGID_ABS_DELTA(1); -+ -+ writel_relaxed(val, rkvdec->regs + RKVDEC_VP9_SEGID_GRP(segid)); -+} -+ -+static void update_dec_buf_info(struct rkvdec_decoded_buffer *buf, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ buf->vp9.width = dec_params->frame_width_minus_1 + 1; -+ buf->vp9.height = dec_params->frame_height_minus_1 + 1; -+ buf->vp9.bit_depth = dec_params->bit_depth; -+} -+ -+static void update_ctx_cur_info(struct rkvdec_vp9_ctx *vp9_ctx, -+ struct rkvdec_decoded_buffer *buf, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ vp9_ctx->cur.valid = true; -+ vp9_ctx->cur.reference_mode = dec_params->reference_mode; -+ vp9_ctx->cur.interpolation_filter = dec_params->interpolation_filter; -+ vp9_ctx->cur.flags = dec_params->flags; -+ vp9_ctx->cur.timestamp = buf->base.vb.vb2_buf.timestamp; -+ vp9_ctx->cur.seg = dec_params->seg; -+ vp9_ctx->cur.lf = dec_params->lf; -+} -+ -+static void update_ctx_last_info(struct rkvdec_vp9_ctx *vp9_ctx) -+{ -+ vp9_ctx->last = vp9_ctx->cur; -+} -+ -+static void config_registers(struct rkvdec_ctx *ctx, -+ const struct rkvdec_vp9_run *run) -+{ -+ unsigned int y_len, uv_len, yuv_len, bit_depth, aligned_height, aligned_pitch, stream_len; -+ const struct v4l2_ctrl_vp9_frame *dec_params; -+ struct rkvdec_decoded_buffer *ref_bufs[3]; -+ struct rkvdec_decoded_buffer *dst, *last, *mv_ref; -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ u32 val, last_frame_info = 0; -+ const struct v4l2_vp9_segmentation *seg; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ dma_addr_t addr; -+ bool intra_only; -+ unsigned int i; -+ -+ dec_params = run->decode_params; -+ dst = vb2_to_rkvdec_decoded_buf(&run->base.bufs.dst->vb2_buf); -+ ref_bufs[0] = get_ref_buf(ctx, &dst->base.vb, dec_params->last_frame_ts); -+ ref_bufs[1] = get_ref_buf(ctx, &dst->base.vb, dec_params->golden_frame_ts); -+ ref_bufs[2] = get_ref_buf(ctx, &dst->base.vb, dec_params->alt_frame_ts); -+ -+ if (vp9_ctx->last.valid) -+ last = get_ref_buf(ctx, &dst->base.vb, vp9_ctx->last.timestamp); -+ else -+ last = dst; -+ -+ update_dec_buf_info(dst, dec_params); -+ update_ctx_cur_info(vp9_ctx, dst, dec_params); -+ seg = &dec_params->seg; -+ -+ intra_only = !!(dec_params->flags & -+ (V4L2_VP9_FRAME_FLAG_KEY_FRAME | -+ V4L2_VP9_FRAME_FLAG_INTRA_ONLY)); -+ -+ writel_relaxed(RKVDEC_MODE(RKVDEC_MODE_VP9), -+ rkvdec->regs + RKVDEC_REG_SYSCTRL); -+ -+ bit_depth = dec_params->bit_depth; -+ aligned_height = round_up(ctx->decoded_fmt.fmt.pix_mp.height, 64); -+ -+ aligned_pitch = round_up(ctx->decoded_fmt.fmt.pix_mp.width * -+ bit_depth, -+ 512) / 8; -+ y_len = aligned_height * aligned_pitch; -+ uv_len = y_len / 2; -+ yuv_len = y_len + uv_len; -+ -+ writel_relaxed(RKVDEC_Y_HOR_VIRSTRIDE(aligned_pitch / 16) | -+ RKVDEC_UV_HOR_VIRSTRIDE(aligned_pitch / 16), -+ rkvdec->regs + RKVDEC_REG_PICPAR); -+ writel_relaxed(RKVDEC_Y_VIRSTRIDE(y_len / 16), -+ rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE); -+ writel_relaxed(RKVDEC_YUV_VIRSTRIDE(yuv_len / 16), -+ rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE); -+ -+ stream_len = vb2_get_plane_payload(&run->base.bufs.src->vb2_buf, 0); -+ writel_relaxed(RKVDEC_STRM_LEN(stream_len), -+ rkvdec->regs + RKVDEC_REG_STRM_LEN); -+ -+ /* -+ * Reset count buffer, because decoder only output intra related syntax -+ * counts when decoding intra frame, but update entropy need to update -+ * all the probabilities. -+ */ -+ if (intra_only) -+ memset(vp9_ctx->count_tbl.cpu, 0, vp9_ctx->count_tbl.size); -+ -+ vp9_ctx->cur.segmapid = vp9_ctx->last.segmapid; -+ if (!intra_only && -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) && -+ (!(seg->flags & V4L2_VP9_SEGMENTATION_FLAG_ENABLED) || -+ (seg->flags & V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP))) -+ vp9_ctx->cur.segmapid++; -+ -+ for (i = 0; i < ARRAY_SIZE(ref_bufs); i++) -+ config_ref_registers(ctx, run, ref_bufs[i], &ref_regs[i]); -+ -+ for (i = 0; i < 8; i++) -+ config_seg_registers(ctx, i); -+ -+ writel_relaxed(RKVDEC_VP9_TX_MODE(vp9_ctx->cur.tx_mode) | -+ RKVDEC_VP9_FRAME_REF_MODE(dec_params->reference_mode), -+ rkvdec->regs + RKVDEC_VP9_CPRHEADER_CONFIG); -+ -+ if (!intra_only) { -+ const struct v4l2_vp9_loop_filter *lf; -+ s8 delta; -+ -+ if (vp9_ctx->last.valid) -+ lf = &vp9_ctx->last.lf; -+ else -+ lf = &vp9_ctx->cur.lf; -+ -+ val = 0; -+ for (i = 0; i < ARRAY_SIZE(lf->ref_deltas); i++) { -+ delta = lf->ref_deltas[i]; -+ val |= RKVDEC_REF_DELTAS_LASTFRAME(i, delta); -+ } -+ -+ writel_relaxed(val, -+ rkvdec->regs + RKVDEC_VP9_REF_DELTAS_LASTFRAME); -+ -+ for (i = 0; i < ARRAY_SIZE(lf->mode_deltas); i++) { -+ delta = lf->mode_deltas[i]; -+ last_frame_info |= RKVDEC_MODE_DELTAS_LASTFRAME(i, -+ delta); -+ } -+ } -+ -+ if (vp9_ctx->last.valid && !intra_only && -+ vp9_ctx->last.seg.flags & V4L2_VP9_SEGMENTATION_FLAG_ENABLED) -+ last_frame_info |= RKVDEC_SEG_EN_LASTFRAME; -+ -+ if (vp9_ctx->last.valid && -+ vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_SHOW_FRAME) -+ last_frame_info |= RKVDEC_LAST_SHOW_FRAME; -+ -+ if (vp9_ctx->last.valid && -+ vp9_ctx->last.flags & -+ (V4L2_VP9_FRAME_FLAG_KEY_FRAME | V4L2_VP9_FRAME_FLAG_INTRA_ONLY)) -+ last_frame_info |= RKVDEC_LAST_INTRA_ONLY; -+ -+ if (vp9_ctx->last.valid && -+ last->vp9.width == dst->vp9.width && -+ last->vp9.height == dst->vp9.height) -+ last_frame_info |= RKVDEC_LAST_WIDHHEIGHT_EQCUR; -+ -+ writel_relaxed(last_frame_info, -+ rkvdec->regs + RKVDEC_VP9_INFO_LASTFRAME); -+ -+ writel_relaxed(stream_len - dec_params->compressed_header_size - -+ dec_params->uncompressed_header_size, -+ rkvdec->regs + RKVDEC_VP9_LASTTILE_SIZE); -+ -+ for (i = 0; !intra_only && i < ARRAY_SIZE(ref_bufs); i++) { -+ unsigned int refw = ref_bufs[i]->vp9.width; -+ unsigned int refh = ref_bufs[i]->vp9.height; -+ u32 hscale, vscale; -+ -+ hscale = (refw << 14) / dst->vp9.width; -+ vscale = (refh << 14) / dst->vp9.height; -+ writel_relaxed(RKVDEC_VP9_REF_HOR_SCALE(hscale) | -+ RKVDEC_VP9_REF_VER_SCALE(vscale), -+ rkvdec->regs + RKVDEC_VP9_REF_SCALE(i)); -+ } -+ -+ addr = vb2_dma_contig_plane_dma_addr(&dst->base.vb.vb2_buf, 0); -+ writel_relaxed(addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE); -+ addr = vb2_dma_contig_plane_dma_addr(&run->base.bufs.src->vb2_buf, 0); -+ writel_relaxed(addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); -+ writel_relaxed(vp9_ctx->priv_tbl.dma + -+ offsetof(struct rkvdec_vp9_priv_tbl, probs), -+ rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE); -+ writel_relaxed(vp9_ctx->count_tbl.dma, -+ rkvdec->regs + RKVDEC_REG_VP9COUNT_BASE); -+ -+ writel_relaxed(vp9_ctx->priv_tbl.dma + -+ offsetof(struct rkvdec_vp9_priv_tbl, segmap) + -+ (RKVDEC_VP9_MAX_SEGMAP_SIZE * vp9_ctx->cur.segmapid), -+ rkvdec->regs + RKVDEC_REG_VP9_SEGIDCUR_BASE); -+ writel_relaxed(vp9_ctx->priv_tbl.dma + -+ offsetof(struct rkvdec_vp9_priv_tbl, segmap) + -+ (RKVDEC_VP9_MAX_SEGMAP_SIZE * (!vp9_ctx->cur.segmapid)), -+ rkvdec->regs + RKVDEC_REG_VP9_SEGIDLAST_BASE); -+ -+ if (!intra_only && -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) && -+ vp9_ctx->last.valid) -+ mv_ref = last; -+ else -+ mv_ref = dst; -+ -+ writel_relaxed(get_mv_base_addr(mv_ref), -+ rkvdec->regs + RKVDEC_VP9_REF_COLMV_BASE); -+ -+ writel_relaxed(ctx->decoded_fmt.fmt.pix_mp.width | -+ (ctx->decoded_fmt.fmt.pix_mp.height << 16), -+ rkvdec->regs + RKVDEC_REG_PERFORMANCE_CYCLE); -+} -+ -+static int validate_dec_params(struct rkvdec_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ unsigned int aligned_width, aligned_height; -+ -+ /* We only support profile 0. */ -+ if (dec_params->profile != 0) { -+ dev_err(ctx->dev->dev, "unsupported profile %d\n", -+ dec_params->profile); -+ return -EINVAL; -+ } -+ -+ aligned_width = round_up(dec_params->frame_width_minus_1 + 1, 64); -+ aligned_height = round_up(dec_params->frame_height_minus_1 + 1, 64); -+ -+ /* -+ * Userspace should update the capture/decoded format when the -+ * resolution changes. -+ */ -+ if (aligned_width != ctx->decoded_fmt.fmt.pix_mp.width || -+ aligned_height != ctx->decoded_fmt.fmt.pix_mp.height) { -+ dev_err(ctx->dev->dev, -+ "unexpected bitstream resolution %dx%d\n", -+ dec_params->frame_width_minus_1 + 1, -+ dec_params->frame_height_minus_1 + 1); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int rkvdec_vp9_run_preamble(struct rkvdec_ctx *ctx, -+ struct rkvdec_vp9_run *run) -+{ -+ const struct v4l2_ctrl_vp9_frame *dec_params; -+ const struct v4l2_ctrl_vp9_compressed_hdr *prob_updates; -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ struct v4l2_ctrl *ctrl; -+ unsigned int fctx_idx; -+ int ret; -+ -+ /* v4l2-specific stuff */ -+ rkvdec_run_preamble(ctx, &run->base); -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_VP9_FRAME); -+ if (WARN_ON(!ctrl)) -+ return -EINVAL; -+ dec_params = ctrl->p_cur.p; -+ -+ ret = validate_dec_params(ctx, dec_params); -+ if (ret) -+ return ret; -+ -+ run->decode_params = dec_params; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_VP9_COMPRESSED_HDR); -+ if (WARN_ON(!ctrl)) -+ return -EINVAL; -+ prob_updates = ctrl->p_cur.p; -+ vp9_ctx->cur.tx_mode = prob_updates->tx_mode; -+ -+ /* -+ * vp9 stuff -+ * -+ * by this point the userspace has done all parts of 6.2 uncompressed_header() -+ * except this fragment: -+ * if ( FrameIsIntra || error_resilient_mode ) { -+ * setup_past_independence ( ) -+ * if ( frame_type == KEY_FRAME || error_resilient_mode == 1 || -+ * reset_frame_context == 3 ) { -+ * for ( i = 0; i < 4; i ++ ) { -+ * save_probs( i ) -+ * } -+ * } else if ( reset_frame_context == 2 ) { -+ * save_probs( frame_context_idx ) -+ * } -+ * frame_context_idx = 0 -+ * } -+ */ -+ fctx_idx = v4l2_vp9_reset_frame_ctx(dec_params, vp9_ctx->frame_context); -+ vp9_ctx->cur.frame_context_idx = fctx_idx; -+ -+ /* 6.1 frame(sz): load_probs() and load_probs2() */ -+ vp9_ctx->probability_tables = vp9_ctx->frame_context[fctx_idx]; -+ -+ /* -+ * The userspace has also performed 6.3 compressed_header(), but handling the -+ * probs in a special way. All probs which need updating, except MV-related, -+ * have been read from the bitstream and translated through inv_map_table[], -+ * but no 6.3.6 inv_recenter_nonneg(v, m) has been performed. The values passed -+ * by userspace are either translated values (there are no 0 values in -+ * inv_map_table[]), or zero to indicate no update. All MV-related probs which need -+ * updating have been read from the bitstream and (mv_prob << 1) | 1 has been -+ * performed. The values passed by userspace are either new values -+ * to replace old ones (the above mentioned shift and bitwise or never result in -+ * a zero) or zero to indicate no update. -+ * fw_update_probs() performs actual probs updates or leaves probs as-is -+ * for values for which a zero was passed from userspace. -+ */ -+ v4l2_vp9_fw_update_probs(&vp9_ctx->probability_tables, prob_updates, dec_params); -+ -+ return 0; -+} -+ -+static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_vp9_run run = { }; -+ int ret; -+ -+ ret = rkvdec_vp9_run_preamble(ctx, &run); -+ if (ret) { -+ rkvdec_run_postamble(ctx, &run.base); -+ return ret; -+ } -+ -+ /* Prepare probs. */ -+ init_probs(ctx, &run); -+ -+ /* Configure hardware registers. */ -+ config_registers(ctx, &run); -+ -+ rkvdec_run_postamble(ctx, &run.base); -+ -+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); -+ -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); -+ -+ writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -+ /* Start decoding! */ -+ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | -+ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ -+ return 0; -+} -+ -+#define copy_tx_and_skip(p1, p2) \ -+do { \ -+ memcpy((p1)->tx8, (p2)->tx8, sizeof((p1)->tx8)); \ -+ memcpy((p1)->tx16, (p2)->tx16, sizeof((p1)->tx16)); \ -+ memcpy((p1)->tx32, (p2)->tx32, sizeof((p1)->tx32)); \ -+ memcpy((p1)->skip, (p2)->skip, sizeof((p1)->skip)); \ -+} while (0) -+ -+static void rkvdec_vp9_done(struct rkvdec_ctx *ctx, -+ struct vb2_v4l2_buffer *src_buf, -+ struct vb2_v4l2_buffer *dst_buf, -+ enum vb2_buffer_state result) -+{ -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ unsigned int fctx_idx; -+ -+ /* v4l2-specific stuff */ -+ if (result == VB2_BUF_STATE_ERROR) -+ goto out_update_last; -+ -+ /* -+ * vp9 stuff -+ * -+ * 6.1.2 refresh_probs() -+ * -+ * In the spec a complementary condition goes last in 6.1.2 refresh_probs(), -+ * but it makes no sense to perform all the activities from the first "if" -+ * there if we actually are not refreshing the frame context. On top of that, -+ * because of 6.2 uncompressed_header() whenever error_resilient_mode == 1, -+ * refresh_frame_context == 0. Consequently, if we don't jump to out_update_last -+ * it means error_resilient_mode must be 0. -+ */ -+ if (!(vp9_ctx->cur.flags & V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX)) -+ goto out_update_last; -+ -+ fctx_idx = vp9_ctx->cur.frame_context_idx; -+ -+ if (!(vp9_ctx->cur.flags & V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE)) { -+ /* error_resilient_mode == 0 && frame_parallel_decoding_mode == 0 */ -+ struct v4l2_vp9_frame_context *probs = &vp9_ctx->probability_tables; -+ bool frame_is_intra = vp9_ctx->cur.flags & -+ (V4L2_VP9_FRAME_FLAG_KEY_FRAME | V4L2_VP9_FRAME_FLAG_INTRA_ONLY); -+ struct tx_and_skip { -+ u8 tx8[2][1]; -+ u8 tx16[2][2]; -+ u8 tx32[2][3]; -+ u8 skip[3]; -+ } _tx_skip, *tx_skip = &_tx_skip; -+ struct v4l2_vp9_frame_symbol_counts *counts; -+ -+ /* buffer the forward-updated TX and skip probs */ -+ if (frame_is_intra) -+ copy_tx_and_skip(tx_skip, probs); -+ -+ /* 6.1.2 refresh_probs(): load_probs() and load_probs2() */ -+ *probs = vp9_ctx->frame_context[fctx_idx]; -+ -+ /* if FrameIsIntra then undo the effect of load_probs2() */ -+ if (frame_is_intra) -+ copy_tx_and_skip(probs, tx_skip); -+ -+ counts = frame_is_intra ? &vp9_ctx->intra_cnts : &vp9_ctx->inter_cnts; -+ v4l2_vp9_adapt_coef_probs(probs, counts, -+ !vp9_ctx->last.valid || -+ vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME, -+ frame_is_intra); -+ if (!frame_is_intra) { -+ const struct rkvdec_vp9_inter_frame_symbol_counts *inter_cnts; -+ u32 classes[2][11]; -+ int i; -+ -+ inter_cnts = vp9_ctx->count_tbl.cpu; -+ for (i = 0; i < ARRAY_SIZE(classes); ++i) -+ memcpy(classes[i], inter_cnts->classes[i], sizeof(classes[0])); -+ counts->classes = &classes; -+ -+ /* load_probs2() already done */ -+ v4l2_vp9_adapt_noncoef_probs(&vp9_ctx->probability_tables, counts, -+ vp9_ctx->cur.reference_mode, -+ vp9_ctx->cur.interpolation_filter, -+ vp9_ctx->cur.tx_mode, vp9_ctx->cur.flags); -+ } -+ } -+ -+ /* 6.1.2 refresh_probs(): save_probs(fctx_idx) */ -+ vp9_ctx->frame_context[fctx_idx] = vp9_ctx->probability_tables; -+ -+out_update_last: -+ update_ctx_last_info(vp9_ctx); -+} -+ -+static void rkvdec_init_v4l2_vp9_count_tbl(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ struct rkvdec_vp9_intra_frame_symbol_counts *intra_cnts = vp9_ctx->count_tbl.cpu; -+ struct rkvdec_vp9_inter_frame_symbol_counts *inter_cnts = vp9_ctx->count_tbl.cpu; -+ int i, j, k, l, m; -+ -+ vp9_ctx->inter_cnts.partition = &inter_cnts->partition; -+ vp9_ctx->inter_cnts.skip = &inter_cnts->skip; -+ vp9_ctx->inter_cnts.intra_inter = &inter_cnts->inter; -+ vp9_ctx->inter_cnts.tx32p = &inter_cnts->tx32p; -+ vp9_ctx->inter_cnts.tx16p = &inter_cnts->tx16p; -+ vp9_ctx->inter_cnts.tx8p = &inter_cnts->tx8p; -+ -+ vp9_ctx->intra_cnts.partition = (u32 (*)[16][4])(&intra_cnts->partition); -+ vp9_ctx->intra_cnts.skip = &intra_cnts->skip; -+ vp9_ctx->intra_cnts.intra_inter = &intra_cnts->intra; -+ vp9_ctx->intra_cnts.tx32p = &intra_cnts->tx32p; -+ vp9_ctx->intra_cnts.tx16p = &intra_cnts->tx16p; -+ vp9_ctx->intra_cnts.tx8p = &intra_cnts->tx8p; -+ -+ vp9_ctx->inter_cnts.y_mode = &inter_cnts->y_mode; -+ vp9_ctx->inter_cnts.uv_mode = &inter_cnts->uv_mode; -+ vp9_ctx->inter_cnts.comp = &inter_cnts->comp; -+ vp9_ctx->inter_cnts.comp_ref = &inter_cnts->comp_ref; -+ vp9_ctx->inter_cnts.single_ref = &inter_cnts->single_ref; -+ vp9_ctx->inter_cnts.mv_mode = &inter_cnts->mv_mode; -+ vp9_ctx->inter_cnts.filter = &inter_cnts->filter; -+ vp9_ctx->inter_cnts.mv_joint = &inter_cnts->mv_joint; -+ vp9_ctx->inter_cnts.sign = &inter_cnts->sign; -+ /* -+ * rk hardware actually uses "u32 classes[2][11 + 1];" -+ * instead of "u32 classes[2][11];", so this must be explicitly -+ * copied into vp9_ctx->classes when passing the data to the -+ * vp9 library function -+ */ -+ vp9_ctx->inter_cnts.class0 = &inter_cnts->class0; -+ vp9_ctx->inter_cnts.bits = &inter_cnts->bits; -+ vp9_ctx->inter_cnts.class0_fp = &inter_cnts->class0_fp; -+ vp9_ctx->inter_cnts.fp = &inter_cnts->fp; -+ vp9_ctx->inter_cnts.class0_hp = &inter_cnts->class0_hp; -+ vp9_ctx->inter_cnts.hp = &inter_cnts->hp; -+ -+#define INNERMOST_LOOP \ -+ do { \ -+ for (m = 0; m < ARRAY_SIZE(vp9_ctx->inter_cnts.coeff[0][0][0][0]); ++m) {\ -+ vp9_ctx->inter_cnts.coeff[i][j][k][l][m] = \ -+ &inter_cnts->ref_cnt[k][i][j][l][m].coeff; \ -+ vp9_ctx->inter_cnts.eob[i][j][k][l][m][0] = \ -+ &inter_cnts->ref_cnt[k][i][j][l][m].eob[0]; \ -+ vp9_ctx->inter_cnts.eob[i][j][k][l][m][1] = \ -+ &inter_cnts->ref_cnt[k][i][j][l][m].eob[1]; \ -+ \ -+ vp9_ctx->intra_cnts.coeff[i][j][k][l][m] = \ -+ &intra_cnts->ref_cnt[k][i][j][l][m].coeff; \ -+ vp9_ctx->intra_cnts.eob[i][j][k][l][m][0] = \ -+ &intra_cnts->ref_cnt[k][i][j][l][m].eob[0]; \ -+ vp9_ctx->intra_cnts.eob[i][j][k][l][m][1] = \ -+ &intra_cnts->ref_cnt[k][i][j][l][m].eob[1]; \ -+ } \ -+ } while (0) -+ -+ for (i = 0; i < ARRAY_SIZE(vp9_ctx->inter_cnts.coeff); ++i) -+ for (j = 0; j < ARRAY_SIZE(vp9_ctx->inter_cnts.coeff[0]); ++j) -+ for (k = 0; k < ARRAY_SIZE(vp9_ctx->inter_cnts.coeff[0][0]); ++k) -+ for (l = 0; l < ARRAY_SIZE(vp9_ctx->inter_cnts.coeff[0][0][0]); ++l) -+ INNERMOST_LOOP; -+#undef INNERMOST_LOOP -+} -+ -+static int rkvdec_vp9_start(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_vp9_priv_tbl *priv_tbl; -+ struct rkvdec_vp9_ctx *vp9_ctx; -+ unsigned char *count_tbl; -+ int ret; -+ -+ vp9_ctx = kzalloc(sizeof(*vp9_ctx), GFP_KERNEL); -+ if (!vp9_ctx) -+ return -ENOMEM; -+ -+ ctx->priv = vp9_ctx; -+ -+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), -+ &vp9_ctx->priv_tbl.dma, GFP_KERNEL); -+ if (!priv_tbl) { -+ ret = -ENOMEM; -+ goto err_free_ctx; -+ } -+ -+ vp9_ctx->priv_tbl.size = sizeof(*priv_tbl); -+ vp9_ctx->priv_tbl.cpu = priv_tbl; -+ memset(priv_tbl, 0, sizeof(*priv_tbl)); -+ -+ count_tbl = dma_alloc_coherent(rkvdec->dev, RKVDEC_VP9_COUNT_SIZE, -+ &vp9_ctx->count_tbl.dma, GFP_KERNEL); -+ if (!count_tbl) { -+ ret = -ENOMEM; -+ goto err_free_priv_tbl; -+ } -+ -+ vp9_ctx->count_tbl.size = RKVDEC_VP9_COUNT_SIZE; -+ vp9_ctx->count_tbl.cpu = count_tbl; -+ memset(count_tbl, 0, sizeof(*count_tbl)); -+ rkvdec_init_v4l2_vp9_count_tbl(ctx); -+ -+ return 0; -+ -+err_free_priv_tbl: -+ dma_free_coherent(rkvdec->dev, vp9_ctx->priv_tbl.size, -+ vp9_ctx->priv_tbl.cpu, vp9_ctx->priv_tbl.dma); -+ -+err_free_ctx: -+ kfree(vp9_ctx); -+ return ret; -+} -+ -+static void rkvdec_vp9_stop(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ -+ dma_free_coherent(rkvdec->dev, vp9_ctx->count_tbl.size, -+ vp9_ctx->count_tbl.cpu, vp9_ctx->count_tbl.dma); -+ dma_free_coherent(rkvdec->dev, vp9_ctx->priv_tbl.size, -+ vp9_ctx->priv_tbl.cpu, vp9_ctx->priv_tbl.dma); -+ kfree(vp9_ctx); -+} -+ -+static int rkvdec_vp9_adjust_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_format *f) -+{ -+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; -+ -+ fmt->num_planes = 1; -+ if (!fmt->plane_fmt[0].sizeimage) -+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * 2; -+ return 0; -+} -+ -+const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops = { -+ .adjust_fmt = rkvdec_vp9_adjust_fmt, -+ .start = rkvdec_vp9_start, -+ .stop = rkvdec_vp9_stop, -+ .run = rkvdec_vp9_run, -+ .done = rkvdec_vp9_done, -+}; -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 4fd4a2907da7..ad2624c30843 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -99,10 +99,30 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = { - .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), - }; - --static const u32 rkvdec_h264_decoded_fmts[] = { -+static const u32 rkvdec_h264_vp9_decoded_fmts[] = { - V4L2_PIX_FMT_NV12, - }; - -+static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = { -+ { -+ .cfg.id = V4L2_CID_STATELESS_VP9_FRAME, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_VP9_PROFILE, -+ .cfg.min = V4L2_MPEG_VIDEO_VP9_PROFILE_0, -+ .cfg.max = V4L2_MPEG_VIDEO_VP9_PROFILE_0, -+ .cfg.def = V4L2_MPEG_VIDEO_VP9_PROFILE_0, -+ }, -+}; -+ -+static const struct rkvdec_ctrls rkvdec_vp9_ctrls = { -+ .ctrls = rkvdec_vp9_ctrl_descs, -+ .num_ctrls = ARRAY_SIZE(rkvdec_vp9_ctrl_descs), -+}; -+ - static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, -@@ -116,8 +136,23 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - }, - .ctrls = &rkvdec_h264_ctrls, - .ops = &rkvdec_h264_fmt_ops, -- .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), -- .decoded_fmts = rkvdec_h264_decoded_fmts, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), -+ .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_VP9_FRAME, -+ .frmsize = { -+ .min_width = 64, -+ .max_width = 4096, -+ .step_width = 64, -+ .min_height = 64, -+ .max_height = 2304, -+ .step_height = 64, -+ }, -+ .ctrls = &rkvdec_vp9_ctrls, -+ .ops = &rkvdec_vp9_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_vp9_decoded_fmts), -+ .decoded_fmts = rkvdec_h264_vp9_decoded_fmts, - } - }; - -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 52ac3874c5e5..2f4ea1786b93 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -42,14 +42,18 @@ struct rkvdec_run { - - struct rkvdec_vp9_decoded_buffer_info { - /* Info needed when the decoded frame serves as a reference frame. */ -- u16 width; -- u16 height; -- u32 bit_depth : 4; -+ unsigned short width; -+ unsigned short height; -+ unsigned int bit_depth : 4; - }; - - struct rkvdec_decoded_buffer { - /* Must be the first field in this struct. */ - struct v4l2_m2m_buffer base; -+ -+ union { -+ struct rkvdec_vp9_decoded_buffer_info vp9; -+ }; - }; - - static inline struct rkvdec_decoded_buffer * -@@ -116,4 +120,6 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - - extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; -+extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; -+ - #endif /* RKVDEC_H_ */ - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:38 +0100 -Subject: [PATCH] media: hantro: Rename registers - -Add more consistency in the way registers are named. - -Signed-off-by: Andrzej Pietrasiewicz -Reviewed-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil ---- - .../staging/media/hantro/hantro_g2_hevc_dec.c | 40 +++++++++---------- - drivers/staging/media/hantro/hantro_g2_regs.h | 28 ++++++------- - 2 files changed, 34 insertions(+), 34 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -index 76a921163b9a..abae36f9b418 100644 ---- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -@@ -448,9 +448,9 @@ static int set_ref(struct hantro_ctx *ctx) - if (dpb[i].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR) - dpb_longterm_e |= BIT(V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1 - i); - -- hantro_write_addr(vpu, G2_REG_ADDR_REF(i), luma_addr); -- hantro_write_addr(vpu, G2_REG_CHR_REF(i), chroma_addr); -- hantro_write_addr(vpu, G2_REG_DMV_REF(i), mv_addr); -+ hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr); -+ hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr); -+ hantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr); - } - - luma_addr = hantro_hevc_get_ref_buf(ctx, decode_params->pic_order_cnt_val); -@@ -460,20 +460,20 @@ static int set_ref(struct hantro_ctx *ctx) - chroma_addr = luma_addr + cr_offset; - mv_addr = luma_addr + mv_offset; - -- hantro_write_addr(vpu, G2_REG_ADDR_REF(i), luma_addr); -- hantro_write_addr(vpu, G2_REG_CHR_REF(i), chroma_addr); -- hantro_write_addr(vpu, G2_REG_DMV_REF(i++), mv_addr); -+ hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr); -+ hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr); -+ hantro_write_addr(vpu, G2_REF_MV_ADDR(i++), mv_addr); - -- hantro_write_addr(vpu, G2_ADDR_DST, luma_addr); -- hantro_write_addr(vpu, G2_ADDR_DST_CHR, chroma_addr); -- hantro_write_addr(vpu, G2_ADDR_DST_MV, mv_addr); -+ hantro_write_addr(vpu, G2_OUT_LUMA_ADDR, luma_addr); -+ hantro_write_addr(vpu, G2_OUT_CHROMA_ADDR, chroma_addr); -+ hantro_write_addr(vpu, G2_OUT_MV_ADDR, mv_addr); - - hantro_hevc_ref_remove_unused(ctx); - - for (; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) { -- hantro_write_addr(vpu, G2_REG_ADDR_REF(i), 0); -- hantro_write_addr(vpu, G2_REG_CHR_REF(i), 0); -- hantro_write_addr(vpu, G2_REG_DMV_REF(i), 0); -+ hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), 0); -+ hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), 0); -+ hantro_write_addr(vpu, G2_REF_MV_ADDR(i), 0); - } - - hantro_reg_write(vpu, &g2_refer_lterm_e, dpb_longterm_e); -@@ -499,7 +499,7 @@ static void set_buffers(struct hantro_ctx *ctx) - src_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); - src_buf_len = vb2_plane_size(&src_buf->vb2_buf, 0); - -- hantro_write_addr(vpu, G2_ADDR_STR, src_dma); -+ hantro_write_addr(vpu, G2_STREAM_ADDR, src_dma); - hantro_reg_write(vpu, &g2_stream_len, src_len); - hantro_reg_write(vpu, &g2_strm_buffer_len, src_buf_len); - hantro_reg_write(vpu, &g2_strm_start_offset, 0); -@@ -508,12 +508,12 @@ static void set_buffers(struct hantro_ctx *ctx) - /* Destination (decoded frame) buffer. */ - dst_dma = hantro_get_dec_buf_addr(ctx, &dst_buf->vb2_buf); - -- hantro_write_addr(vpu, G2_RASTER_SCAN, dst_dma); -- hantro_write_addr(vpu, G2_RASTER_SCAN_CHR, dst_dma + cr_offset); -- hantro_write_addr(vpu, G2_ADDR_TILE_SIZE, ctx->hevc_dec.tile_sizes.dma); -- hantro_write_addr(vpu, G2_TILE_FILTER, ctx->hevc_dec.tile_filter.dma); -- hantro_write_addr(vpu, G2_TILE_SAO, ctx->hevc_dec.tile_sao.dma); -- hantro_write_addr(vpu, G2_TILE_BSD, ctx->hevc_dec.tile_bsd.dma); -+ hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma); -+ hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + cr_offset); -+ hantro_write_addr(vpu, G2_TILE_SIZES_ADDR, ctx->hevc_dec.tile_sizes.dma); -+ hantro_write_addr(vpu, G2_TILE_FILTER_ADDR, ctx->hevc_dec.tile_filter.dma); -+ hantro_write_addr(vpu, G2_TILE_SAO_ADDR, ctx->hevc_dec.tile_sao.dma); -+ hantro_write_addr(vpu, G2_TILE_BSD_ADDR, ctx->hevc_dec.tile_bsd.dma); - } - - static void prepare_scaling_list_buffer(struct hantro_ctx *ctx) -@@ -563,7 +563,7 @@ static void prepare_scaling_list_buffer(struct hantro_ctx *ctx) - for (k = 0; k < 8; k++) - *p++ = sc->scaling_list_32x32[i][8 * k + j]; - -- hantro_write_addr(vpu, HEVC_SCALING_LIST, ctx->hevc_dec.scaling_lists.dma); -+ hantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma); - } - - static void hantro_g2_check_idle(struct hantro_dev *vpu) -diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h -index bb22fa921914..24b18f839ff8 100644 ---- a/drivers/staging/media/hantro/hantro_g2_regs.h -+++ b/drivers/staging/media/hantro/hantro_g2_regs.h -@@ -177,20 +177,20 @@ - #define G2_REG_CONFIG_DEC_CLK_GATE_E BIT(16) - #define G2_REG_CONFIG_DEC_CLK_GATE_IDLE_E BIT(17) - --#define G2_ADDR_DST (G2_SWREG(65)) --#define G2_REG_ADDR_REF(i) (G2_SWREG(67) + ((i) * 0x8)) --#define G2_ADDR_DST_CHR (G2_SWREG(99)) --#define G2_REG_CHR_REF(i) (G2_SWREG(101) + ((i) * 0x8)) --#define G2_ADDR_DST_MV (G2_SWREG(133)) --#define G2_REG_DMV_REF(i) (G2_SWREG(135) + ((i) * 0x8)) --#define G2_ADDR_TILE_SIZE (G2_SWREG(167)) --#define G2_ADDR_STR (G2_SWREG(169)) --#define HEVC_SCALING_LIST (G2_SWREG(171)) --#define G2_RASTER_SCAN (G2_SWREG(175)) --#define G2_RASTER_SCAN_CHR (G2_SWREG(177)) --#define G2_TILE_FILTER (G2_SWREG(179)) --#define G2_TILE_SAO (G2_SWREG(181)) --#define G2_TILE_BSD (G2_SWREG(183)) -+#define G2_OUT_LUMA_ADDR (G2_SWREG(65)) -+#define G2_REF_LUMA_ADDR(i) (G2_SWREG(67) + ((i) * 0x8)) -+#define G2_OUT_CHROMA_ADDR (G2_SWREG(99)) -+#define G2_REF_CHROMA_ADDR(i) (G2_SWREG(101) + ((i) * 0x8)) -+#define G2_OUT_MV_ADDR (G2_SWREG(133)) -+#define G2_REF_MV_ADDR(i) (G2_SWREG(135) + ((i) * 0x8)) -+#define G2_TILE_SIZES_ADDR (G2_SWREG(167)) -+#define G2_STREAM_ADDR (G2_SWREG(169)) -+#define G2_HEVC_SCALING_LIST_ADDR (G2_SWREG(171)) -+#define G2_RS_OUT_LUMA_ADDR (G2_SWREG(175)) -+#define G2_RS_OUT_CHROMA_ADDR (G2_SWREG(177)) -+#define G2_TILE_FILTER_ADDR (G2_SWREG(179)) -+#define G2_TILE_SAO_ADDR (G2_SWREG(181)) -+#define G2_TILE_BSD_ADDR (G2_SWREG(183)) - - #define g2_strm_buffer_len G2_DEC_REG(258, 0, 0xffffffff) - #define g2_strm_start_offset G2_DEC_REG(259, 0, 0xffffffff) - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:39 +0100 -Subject: [PATCH] media: hantro: Prepare for other G2 codecs - -VeriSilicon Hantro G2 core supports other codecs besides hevc. -Factor out some common code in preparation for vp9 support. - -Signed-off-by: Andrzej Pietrasiewicz -Reviewed-by: Benjamin Gaignard -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/Makefile | 1 + - drivers/staging/media/hantro/hantro.h | 7 +++++ - drivers/staging/media/hantro/hantro_drv.c | 5 +++ - drivers/staging/media/hantro/hantro_g2.c | 26 ++++++++++++++++ - .../staging/media/hantro/hantro_g2_hevc_dec.c | 31 ------------------- - drivers/staging/media/hantro/hantro_g2_regs.h | 7 +++++ - drivers/staging/media/hantro/hantro_hw.h | 2 ++ - 7 files changed, 48 insertions(+), 31 deletions(-) - create mode 100644 drivers/staging/media/hantro/hantro_g2.c - -diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile -index 90036831fec4..fe6d84871d07 100644 ---- a/drivers/staging/media/hantro/Makefile -+++ b/drivers/staging/media/hantro/Makefile -@@ -12,6 +12,7 @@ hantro-vpu-y += \ - hantro_g1_mpeg2_dec.o \ - hantro_g2_hevc_dec.o \ - hantro_g1_vp8_dec.o \ -+ hantro_g2.o \ - rockchip_vpu2_hw_jpeg_enc.o \ - rockchip_vpu2_hw_h264_dec.o \ - rockchip_vpu2_hw_mpeg2_dec.o \ -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index dd5e56765d4e..d91eb2b1c509 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -369,6 +369,13 @@ static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg) - writel(val, vpu->dec_base + reg); - } - -+static inline void hantro_write_addr(struct hantro_dev *vpu, -+ unsigned long offset, -+ dma_addr_t addr) -+{ -+ vdpu_write(vpu, addr & 0xffffffff, offset); -+} -+ - static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg) - { - u32 val = readl(vpu->dec_base + reg); -diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c -index fb82b9297a2b..bb72e5e208b7 100644 ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -907,6 +907,11 @@ static int hantro_probe(struct platform_device *pdev) - vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset; - vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset; - -+ /** -+ * TODO: Eventually allow taking advantage of full 64-bit address space. -+ * Until then we assume the MSB portion of buffers' base addresses is -+ * always 0 due to this masking operation. -+ */ - ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32)); - if (ret) { - dev_err(vpu->dev, "Could not set DMA coherent mask.\n"); -diff --git a/drivers/staging/media/hantro/hantro_g2.c b/drivers/staging/media/hantro/hantro_g2.c -new file mode 100644 -index 000000000000..6f3e1f797f83 ---- /dev/null -+++ b/drivers/staging/media/hantro/hantro_g2.c -@@ -0,0 +1,26 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Hantro VPU codec driver -+ * -+ * Copyright (C) 2021 Collabora Ltd, Andrzej Pietrasiewicz -+ */ -+ -+#include "hantro_hw.h" -+#include "hantro_g2_regs.h" -+ -+void hantro_g2_check_idle(struct hantro_dev *vpu) -+{ -+ int i; -+ -+ for (i = 0; i < 3; i++) { -+ u32 status; -+ -+ /* Make sure the VPU is idle */ -+ status = vdpu_read(vpu, G2_REG_INTERRUPT); -+ if (status & G2_REG_INTERRUPT_DEC_E) { -+ dev_warn(vpu->dev, "device still running, aborting"); -+ status |= G2_REG_INTERRUPT_DEC_ABORT_E | G2_REG_INTERRUPT_DEC_IRQ_DIS; -+ vdpu_write(vpu, status, G2_REG_INTERRUPT); -+ } -+ } -+} -diff --git a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -index abae36f9b418..f62608b0b408 100644 ---- a/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -+++ b/drivers/staging/media/hantro/hantro_g2_hevc_dec.c -@@ -8,20 +8,6 @@ - #include "hantro_hw.h" - #include "hantro_g2_regs.h" - --#define HEVC_DEC_MODE 0xC -- --#define BUS_WIDTH_32 0 --#define BUS_WIDTH_64 1 --#define BUS_WIDTH_128 2 --#define BUS_WIDTH_256 3 -- --static inline void hantro_write_addr(struct hantro_dev *vpu, -- unsigned long offset, -- dma_addr_t addr) --{ -- vdpu_write(vpu, addr & 0xffffffff, offset); --} -- - static void prepare_tile_info_buffer(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -@@ -566,23 +552,6 @@ static void prepare_scaling_list_buffer(struct hantro_ctx *ctx) - hantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma); - } - --static void hantro_g2_check_idle(struct hantro_dev *vpu) --{ -- int i; -- -- for (i = 0; i < 3; i++) { -- u32 status; -- -- /* Make sure the VPU is idle */ -- status = vdpu_read(vpu, G2_REG_INTERRUPT); -- if (status & G2_REG_INTERRUPT_DEC_E) { -- dev_warn(vpu->dev, "device still running, aborting"); -- status |= G2_REG_INTERRUPT_DEC_ABORT_E | G2_REG_INTERRUPT_DEC_IRQ_DIS; -- vdpu_write(vpu, status, G2_REG_INTERRUPT); -- } -- } --} -- - int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h -index 24b18f839ff8..136ba6d98a1f 100644 ---- a/drivers/staging/media/hantro/hantro_g2_regs.h -+++ b/drivers/staging/media/hantro/hantro_g2_regs.h -@@ -27,6 +27,13 @@ - #define G2_REG_INTERRUPT_DEC_IRQ_DIS BIT(4) - #define G2_REG_INTERRUPT_DEC_E BIT(0) - -+#define HEVC_DEC_MODE 0xc -+ -+#define BUS_WIDTH_32 0 -+#define BUS_WIDTH_64 1 -+#define BUS_WIDTH_128 2 -+#define BUS_WIDTH_256 3 -+ - #define g2_strm_swap G2_DEC_REG(2, 28, 0xf) - #define g2_dirmv_swap G2_DEC_REG(2, 20, 0xf) - -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index 2f85430682d8..1d869abf90b2 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -312,4 +312,6 @@ void hantro_vp8_dec_exit(struct hantro_ctx *ctx); - void hantro_vp8_prob_update(struct hantro_ctx *ctx, - const struct v4l2_ctrl_vp8_frame *hdr); - -+void hantro_g2_check_idle(struct hantro_dev *vpu); -+ - #endif /* HANTRO_HW_H_ */ - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:40 +0100 -Subject: [PATCH] media: hantro: Support VP9 on the G2 core - -VeriSilicon Hantro G2 core supports VP9 codec. - -Signed-off-by: Andrzej Pietrasiewicz -Reviewed-by: Benjamin Gaignard -Signed-off-by: Hans Verkuil -[hverkuil: add kerneldoc line for HANTRO_MODE_VP9_DEC] ---- - drivers/staging/media/hantro/Kconfig | 1 + - drivers/staging/media/hantro/Makefile | 6 +- - drivers/staging/media/hantro/hantro.h | 27 + - drivers/staging/media/hantro/hantro_drv.c | 18 +- - drivers/staging/media/hantro/hantro_g2_regs.h | 97 ++ - .../staging/media/hantro/hantro_g2_vp9_dec.c | 980 ++++++++++++++++++ - drivers/staging/media/hantro/hantro_hw.h | 99 ++ - drivers/staging/media/hantro/hantro_v4l2.c | 6 + - drivers/staging/media/hantro/hantro_vp9.c | 240 +++++ - drivers/staging/media/hantro/hantro_vp9.h | 102 ++ - drivers/staging/media/hantro/imx8m_vpu_hw.c | 22 +- - 11 files changed, 1594 insertions(+), 4 deletions(-) - create mode 100644 drivers/staging/media/hantro/hantro_g2_vp9_dec.c - create mode 100644 drivers/staging/media/hantro/hantro_vp9.c - create mode 100644 drivers/staging/media/hantro/hantro_vp9.h - -diff --git a/drivers/staging/media/hantro/Kconfig b/drivers/staging/media/hantro/Kconfig -index 20b1f6d7b69c..00a57d88c92e 100644 ---- a/drivers/staging/media/hantro/Kconfig -+++ b/drivers/staging/media/hantro/Kconfig -@@ -9,6 +9,7 @@ config VIDEO_HANTRO - select VIDEOBUF2_VMALLOC - select V4L2_MEM2MEM_DEV - select V4L2_H264 -+ select V4L2_VP9 - help - Support for the Hantro IP based Video Processing Units present on - Rockchip and NXP i.MX8M SoCs, which accelerate video and image -diff --git a/drivers/staging/media/hantro/Makefile b/drivers/staging/media/hantro/Makefile -index fe6d84871d07..28af0a1ee4bf 100644 ---- a/drivers/staging/media/hantro/Makefile -+++ b/drivers/staging/media/hantro/Makefile -@@ -10,9 +10,10 @@ hantro-vpu-y += \ - hantro_g1.o \ - hantro_g1_h264_dec.o \ - hantro_g1_mpeg2_dec.o \ -- hantro_g2_hevc_dec.o \ - hantro_g1_vp8_dec.o \ - hantro_g2.o \ -+ hantro_g2_hevc_dec.o \ -+ hantro_g2_vp9_dec.o \ - rockchip_vpu2_hw_jpeg_enc.o \ - rockchip_vpu2_hw_h264_dec.o \ - rockchip_vpu2_hw_mpeg2_dec.o \ -@@ -21,7 +22,8 @@ hantro-vpu-y += \ - hantro_h264.o \ - hantro_hevc.o \ - hantro_mpeg2.o \ -- hantro_vp8.o -+ hantro_vp8.o \ -+ hantro_vp9.o - - hantro-vpu-$(CONFIG_VIDEO_HANTRO_IMX8M) += \ - imx8m_vpu_hw.o -diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h -index d91eb2b1c509..7da23f7f207a 100644 ---- a/drivers/staging/media/hantro/hantro.h -+++ b/drivers/staging/media/hantro/hantro.h -@@ -36,6 +36,7 @@ struct hantro_postproc_ops; - #define HANTRO_VP8_DECODER BIT(17) - #define HANTRO_H264_DECODER BIT(18) - #define HANTRO_HEVC_DECODER BIT(19) -+#define HANTRO_VP9_DECODER BIT(20) - #define HANTRO_DECODERS 0xffff0000 - - /** -@@ -102,6 +103,7 @@ struct hantro_variant { - * @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder. - * @HANTRO_MODE_VP8_DEC: VP8 decoder. - * @HANTRO_MODE_HEVC_DEC: HEVC decoder. -+ * @HANTRO_MODE_VP9_DEC: VP9 decoder. - */ - enum hantro_codec_mode { - HANTRO_MODE_NONE = -1, -@@ -110,6 +112,7 @@ enum hantro_codec_mode { - HANTRO_MODE_MPEG2_DEC, - HANTRO_MODE_VP8_DEC, - HANTRO_MODE_HEVC_DEC, -+ HANTRO_MODE_VP9_DEC, - }; - - /* -@@ -223,6 +226,7 @@ struct hantro_dev { - * @mpeg2_dec: MPEG-2-decoding context. - * @vp8_dec: VP8-decoding context. - * @hevc_dec: HEVC-decoding context. -+ * @vp9_dec: VP9-decoding context. - */ - struct hantro_ctx { - struct hantro_dev *dev; -@@ -250,6 +254,7 @@ struct hantro_ctx { - struct hantro_mpeg2_dec_hw_ctx mpeg2_dec; - struct hantro_vp8_dec_hw_ctx vp8_dec; - struct hantro_hevc_dec_hw_ctx hevc_dec; -+ struct hantro_vp9_dec_hw_ctx vp9_dec; - }; - }; - -@@ -299,6 +304,22 @@ struct hantro_postproc_regs { - struct hantro_reg display_width; - }; - -+struct hantro_vp9_decoded_buffer_info { -+ /* Info needed when the decoded frame serves as a reference frame. */ -+ unsigned short width; -+ unsigned short height; -+ u32 bit_depth : 4; -+}; -+ -+struct hantro_decoded_buffer { -+ /* Must be the first field in this struct. */ -+ struct v4l2_m2m_buffer base; -+ -+ union { -+ struct hantro_vp9_decoded_buffer_info vp9; -+ }; -+}; -+ - /* Logging helpers */ - - /** -@@ -436,6 +457,12 @@ hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb) - return vb2_dma_contig_plane_dma_addr(vb, 0); - } - -+static inline struct hantro_decoded_buffer * -+vb2_to_hantro_decoded_buf(struct vb2_buffer *buf) -+{ -+ return container_of(buf, struct hantro_decoded_buffer, base.vb.vb2_buf); -+} -+ - void hantro_postproc_disable(struct hantro_ctx *ctx); - void hantro_postproc_enable(struct hantro_ctx *ctx); - void hantro_postproc_free(struct hantro_ctx *ctx); -diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c -index bb72e5e208b7..ab2467998d29 100644 ---- a/drivers/staging/media/hantro/hantro_drv.c -+++ b/drivers/staging/media/hantro/hantro_drv.c -@@ -232,7 +232,7 @@ queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) - dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; - dst_vq->drv_priv = ctx; - dst_vq->ops = &hantro_queue_ops; -- dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); -+ dst_vq->buf_struct_size = sizeof(struct hantro_decoded_buffer); - dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; - dst_vq->lock = &ctx->dev->vpu_mutex; - dst_vq->dev = ctx->dev->v4l2_dev.dev; -@@ -263,6 +263,12 @@ static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) - if (sps->bit_depth_luma_minus8 != 0) - /* Only 8-bit is supported */ - return -EINVAL; -+ } else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) { -+ const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame; -+ -+ /* We only support profile 0 */ -+ if (dec_params->profile != 0) -+ return -EINVAL; - } - return 0; - } -@@ -461,6 +467,16 @@ static const struct hantro_ctrl controls[] = { - .step = 1, - .ops = &hantro_hevc_ctrl_ops, - }, -+ }, { -+ .codec = HANTRO_VP9_DECODER, -+ .cfg = { -+ .id = V4L2_CID_STATELESS_VP9_FRAME, -+ }, -+ }, { -+ .codec = HANTRO_VP9_DECODER, -+ .cfg = { -+ .id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR, -+ }, - }, - }; - -diff --git a/drivers/staging/media/hantro/hantro_g2_regs.h b/drivers/staging/media/hantro/hantro_g2_regs.h -index 136ba6d98a1f..9c857dd1ad9b 100644 ---- a/drivers/staging/media/hantro/hantro_g2_regs.h -+++ b/drivers/staging/media/hantro/hantro_g2_regs.h -@@ -28,6 +28,7 @@ - #define G2_REG_INTERRUPT_DEC_E BIT(0) - - #define HEVC_DEC_MODE 0xc -+#define VP9_DEC_MODE 0xd - - #define BUS_WIDTH_32 0 - #define BUS_WIDTH_64 1 -@@ -49,6 +50,7 @@ - #define g2_pic_height_in_cbs G2_DEC_REG(4, 6, 0x1fff) - #define g2_num_ref_frames G2_DEC_REG(4, 0, 0x1f) - -+#define g2_start_bit G2_DEC_REG(5, 25, 0x7f) - #define g2_scaling_list_e G2_DEC_REG(5, 24, 0x1) - #define g2_cb_qp_offset G2_DEC_REG(5, 19, 0x1f) - #define g2_cr_qp_offset G2_DEC_REG(5, 14, 0x1f) -@@ -84,6 +86,7 @@ - #define g2_bit_depth_y_minus8 G2_DEC_REG(8, 6, 0x3) - #define g2_bit_depth_c_minus8 G2_DEC_REG(8, 4, 0x3) - #define g2_output_8_bits G2_DEC_REG(8, 3, 0x1) -+#define g2_output_format G2_DEC_REG(8, 0, 0x7) - - #define g2_refidx1_active G2_DEC_REG(9, 19, 0x1f) - #define g2_refidx0_active G2_DEC_REG(9, 14, 0x1f) -@@ -96,6 +99,14 @@ - #define g2_tile_e G2_DEC_REG(10, 1, 0x1) - #define g2_entropy_sync_e G2_DEC_REG(10, 0, 0x1) - -+#define vp9_transform_mode G2_DEC_REG(11, 27, 0x7) -+#define vp9_filt_sharpness G2_DEC_REG(11, 21, 0x7) -+#define vp9_mcomp_filt_type G2_DEC_REG(11, 8, 0x7) -+#define vp9_high_prec_mv_e G2_DEC_REG(11, 7, 0x1) -+#define vp9_comp_pred_mode G2_DEC_REG(11, 4, 0x3) -+#define vp9_gref_sign_bias G2_DEC_REG(11, 2, 0x1) -+#define vp9_aref_sign_bias G2_DEC_REG(11, 0, 0x1) -+ - #define g2_refer_lterm_e G2_DEC_REG(12, 16, 0xffff) - #define g2_min_cb_size G2_DEC_REG(12, 13, 0x7) - #define g2_max_cb_size G2_DEC_REG(12, 10, 0x7) -@@ -154,6 +165,50 @@ - #define g2_partial_ctb_y G2_DEC_REG(20, 30, 0x1) - #define g2_pic_width_4x4 G2_DEC_REG(20, 16, 0xfff) - #define g2_pic_height_4x4 G2_DEC_REG(20, 0, 0xfff) -+ -+#define vp9_qp_delta_y_dc G2_DEC_REG(13, 23, 0x3f) -+#define vp9_qp_delta_ch_dc G2_DEC_REG(13, 17, 0x3f) -+#define vp9_qp_delta_ch_ac G2_DEC_REG(13, 11, 0x3f) -+#define vp9_last_sign_bias G2_DEC_REG(13, 10, 0x1) -+#define vp9_lossless_e G2_DEC_REG(13, 9, 0x1) -+#define vp9_comp_pred_var_ref1 G2_DEC_REG(13, 7, 0x3) -+#define vp9_comp_pred_var_ref0 G2_DEC_REG(13, 5, 0x3) -+#define vp9_comp_pred_fixed_ref G2_DEC_REG(13, 3, 0x3) -+#define vp9_segment_temp_upd_e G2_DEC_REG(13, 2, 0x1) -+#define vp9_segment_upd_e G2_DEC_REG(13, 1, 0x1) -+#define vp9_segment_e G2_DEC_REG(13, 0, 0x1) -+ -+#define vp9_filt_level G2_DEC_REG(14, 18, 0x3f) -+#define vp9_refpic_seg0 G2_DEC_REG(14, 15, 0x7) -+#define vp9_skip_seg0 G2_DEC_REG(14, 14, 0x1) -+#define vp9_filt_level_seg0 G2_DEC_REG(14, 8, 0x3f) -+#define vp9_quant_seg0 G2_DEC_REG(14, 0, 0xff) -+ -+#define vp9_refpic_seg1 G2_DEC_REG(15, 15, 0x7) -+#define vp9_skip_seg1 G2_DEC_REG(15, 14, 0x1) -+#define vp9_filt_level_seg1 G2_DEC_REG(15, 8, 0x3f) -+#define vp9_quant_seg1 G2_DEC_REG(15, 0, 0xff) -+ -+#define vp9_refpic_seg2 G2_DEC_REG(16, 15, 0x7) -+#define vp9_skip_seg2 G2_DEC_REG(16, 14, 0x1) -+#define vp9_filt_level_seg2 G2_DEC_REG(16, 8, 0x3f) -+#define vp9_quant_seg2 G2_DEC_REG(16, 0, 0xff) -+ -+#define vp9_refpic_seg3 G2_DEC_REG(17, 15, 0x7) -+#define vp9_skip_seg3 G2_DEC_REG(17, 14, 0x1) -+#define vp9_filt_level_seg3 G2_DEC_REG(17, 8, 0x3f) -+#define vp9_quant_seg3 G2_DEC_REG(17, 0, 0xff) -+ -+#define vp9_refpic_seg4 G2_DEC_REG(18, 15, 0x7) -+#define vp9_skip_seg4 G2_DEC_REG(18, 14, 0x1) -+#define vp9_filt_level_seg4 G2_DEC_REG(18, 8, 0x3f) -+#define vp9_quant_seg4 G2_DEC_REG(18, 0, 0xff) -+ -+#define vp9_refpic_seg5 G2_DEC_REG(19, 15, 0x7) -+#define vp9_skip_seg5 G2_DEC_REG(19, 14, 0x1) -+#define vp9_filt_level_seg5 G2_DEC_REG(19, 8, 0x3f) -+#define vp9_quant_seg5 G2_DEC_REG(19, 0, 0xff) -+ - #define hevc_cur_poc_00 G2_DEC_REG(46, 24, 0xff) - #define hevc_cur_poc_01 G2_DEC_REG(46, 16, 0xff) - #define hevc_cur_poc_02 G2_DEC_REG(46, 8, 0xff) -@@ -174,6 +229,44 @@ - #define hevc_cur_poc_14 G2_DEC_REG(49, 8, 0xff) - #define hevc_cur_poc_15 G2_DEC_REG(49, 0, 0xff) - -+#define vp9_refpic_seg6 G2_DEC_REG(31, 15, 0x7) -+#define vp9_skip_seg6 G2_DEC_REG(31, 14, 0x1) -+#define vp9_filt_level_seg6 G2_DEC_REG(31, 8, 0x3f) -+#define vp9_quant_seg6 G2_DEC_REG(31, 0, 0xff) -+ -+#define vp9_refpic_seg7 G2_DEC_REG(32, 15, 0x7) -+#define vp9_skip_seg7 G2_DEC_REG(32, 14, 0x1) -+#define vp9_filt_level_seg7 G2_DEC_REG(32, 8, 0x3f) -+#define vp9_quant_seg7 G2_DEC_REG(32, 0, 0xff) -+ -+#define vp9_lref_width G2_DEC_REG(33, 16, 0xffff) -+#define vp9_lref_height G2_DEC_REG(33, 0, 0xffff) -+ -+#define vp9_gref_width G2_DEC_REG(34, 16, 0xffff) -+#define vp9_gref_height G2_DEC_REG(34, 0, 0xffff) -+ -+#define vp9_aref_width G2_DEC_REG(35, 16, 0xffff) -+#define vp9_aref_height G2_DEC_REG(35, 0, 0xffff) -+ -+#define vp9_lref_hor_scale G2_DEC_REG(36, 16, 0xffff) -+#define vp9_lref_ver_scale G2_DEC_REG(36, 0, 0xffff) -+ -+#define vp9_gref_hor_scale G2_DEC_REG(37, 16, 0xffff) -+#define vp9_gref_ver_scale G2_DEC_REG(37, 0, 0xffff) -+ -+#define vp9_aref_hor_scale G2_DEC_REG(38, 16, 0xffff) -+#define vp9_aref_ver_scale G2_DEC_REG(38, 0, 0xffff) -+ -+#define vp9_filt_ref_adj_0 G2_DEC_REG(46, 24, 0x7f) -+#define vp9_filt_ref_adj_1 G2_DEC_REG(46, 16, 0x7f) -+#define vp9_filt_ref_adj_2 G2_DEC_REG(46, 8, 0x7f) -+#define vp9_filt_ref_adj_3 G2_DEC_REG(46, 0, 0x7f) -+ -+#define vp9_filt_mb_adj_0 G2_DEC_REG(47, 24, 0x7f) -+#define vp9_filt_mb_adj_1 G2_DEC_REG(47, 16, 0x7f) -+#define vp9_filt_mb_adj_2 G2_DEC_REG(47, 8, 0x7f) -+#define vp9_filt_mb_adj_3 G2_DEC_REG(47, 0, 0x7f) -+ - #define g2_apf_threshold G2_DEC_REG(55, 0, 0xffff) - - #define g2_clk_gate_e G2_DEC_REG(58, 16, 0x1) -@@ -186,6 +279,8 @@ - - #define G2_OUT_LUMA_ADDR (G2_SWREG(65)) - #define G2_REF_LUMA_ADDR(i) (G2_SWREG(67) + ((i) * 0x8)) -+#define G2_VP9_SEGMENT_WRITE_ADDR (G2_SWREG(79)) -+#define G2_VP9_SEGMENT_READ_ADDR (G2_SWREG(81)) - #define G2_OUT_CHROMA_ADDR (G2_SWREG(99)) - #define G2_REF_CHROMA_ADDR(i) (G2_SWREG(101) + ((i) * 0x8)) - #define G2_OUT_MV_ADDR (G2_SWREG(133)) -@@ -193,6 +288,8 @@ - #define G2_TILE_SIZES_ADDR (G2_SWREG(167)) - #define G2_STREAM_ADDR (G2_SWREG(169)) - #define G2_HEVC_SCALING_LIST_ADDR (G2_SWREG(171)) -+#define G2_VP9_CTX_COUNT_ADDR (G2_SWREG(171)) -+#define G2_VP9_PROBS_ADDR (G2_SWREG(173)) - #define G2_RS_OUT_LUMA_ADDR (G2_SWREG(175)) - #define G2_RS_OUT_CHROMA_ADDR (G2_SWREG(177)) - #define G2_TILE_FILTER_ADDR (G2_SWREG(179)) -diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -new file mode 100644 -index 000000000000..fc55b03a8004 ---- /dev/null -+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -@@ -0,0 +1,980 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Hantro VP9 codec driver -+ * -+ * Copyright (C) 2021 Collabora Ltd. -+ */ -+#include "media/videobuf2-core.h" -+#include "media/videobuf2-dma-contig.h" -+#include "media/videobuf2-v4l2.h" -+#include -+#include -+#include -+#include -+ -+#include "hantro.h" -+#include "hantro_vp9.h" -+#include "hantro_g2_regs.h" -+ -+#define G2_ALIGN 16 -+ -+enum hantro_ref_frames { -+ INTRA_FRAME = 0, -+ LAST_FRAME = 1, -+ GOLDEN_FRAME = 2, -+ ALTREF_FRAME = 3, -+ MAX_REF_FRAMES = 4 -+}; -+ -+static int start_prepare_run(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame **dec_params) -+{ -+ const struct v4l2_ctrl_vp9_compressed_hdr *prob_updates; -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ struct v4l2_ctrl *ctrl; -+ unsigned int fctx_idx; -+ -+ /* v4l2-specific stuff */ -+ hantro_start_prepare_run(ctx); -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_handler, V4L2_CID_STATELESS_VP9_FRAME); -+ if (WARN_ON(!ctrl)) -+ return -EINVAL; -+ *dec_params = ctrl->p_cur.p; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_handler, V4L2_CID_STATELESS_VP9_COMPRESSED_HDR); -+ if (WARN_ON(!ctrl)) -+ return -EINVAL; -+ prob_updates = ctrl->p_cur.p; -+ vp9_ctx->cur.tx_mode = prob_updates->tx_mode; -+ -+ /* -+ * vp9 stuff -+ * -+ * by this point the userspace has done all parts of 6.2 uncompressed_header() -+ * except this fragment: -+ * if ( FrameIsIntra || error_resilient_mode ) { -+ * setup_past_independence ( ) -+ * if ( frame_type == KEY_FRAME || error_resilient_mode == 1 || -+ * reset_frame_context == 3 ) { -+ * for ( i = 0; i < 4; i ++ ) { -+ * save_probs( i ) -+ * } -+ * } else if ( reset_frame_context == 2 ) { -+ * save_probs( frame_context_idx ) -+ * } -+ * frame_context_idx = 0 -+ * } -+ */ -+ fctx_idx = v4l2_vp9_reset_frame_ctx(*dec_params, vp9_ctx->frame_context); -+ vp9_ctx->cur.frame_context_idx = fctx_idx; -+ -+ /* 6.1 frame(sz): load_probs() and load_probs2() */ -+ vp9_ctx->probability_tables = vp9_ctx->frame_context[fctx_idx]; -+ -+ /* -+ * The userspace has also performed 6.3 compressed_header(), but handling the -+ * probs in a special way. All probs which need updating, except MV-related, -+ * have been read from the bitstream and translated through inv_map_table[], -+ * but no 6.3.6 inv_recenter_nonneg(v, m) has been performed. The values passed -+ * by userspace are either translated values (there are no 0 values in -+ * inv_map_table[]), or zero to indicate no update. All MV-related probs which need -+ * updating have been read from the bitstream and (mv_prob << 1) | 1 has been -+ * performed. The values passed by userspace are either new values -+ * to replace old ones (the above mentioned shift and bitwise or never result in -+ * a zero) or zero to indicate no update. -+ * fw_update_probs() performs actual probs updates or leaves probs as-is -+ * for values for which a zero was passed from userspace. -+ */ -+ v4l2_vp9_fw_update_probs(&vp9_ctx->probability_tables, prob_updates, *dec_params); -+ -+ return 0; -+} -+ -+static size_t chroma_offset(const struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ int bytes_per_pixel = dec_params->bit_depth == 8 ? 1 : 2; -+ -+ return ctx->src_fmt.width * ctx->src_fmt.height * bytes_per_pixel; -+} -+ -+static size_t mv_offset(const struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ size_t cr_offset = chroma_offset(ctx, dec_params); -+ -+ return ALIGN((cr_offset * 3) / 2, G2_ALIGN); -+} -+ -+static struct hantro_decoded_buffer * -+get_ref_buf(struct hantro_ctx *ctx, struct vb2_v4l2_buffer *dst, u64 timestamp) -+{ -+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -+ int buf_idx; -+ -+ /* -+ * If a ref is unused or invalid, address of current destination -+ * buffer is returned. -+ */ -+ buf_idx = vb2_find_timestamp(cap_q, timestamp, 0); -+ if (buf_idx < 0) -+ return vb2_to_hantro_decoded_buf(&dst->vb2_buf); -+ -+ return vb2_to_hantro_decoded_buf(vb2_get_buffer(cap_q, buf_idx)); -+} -+ -+static void update_dec_buf_info(struct hantro_decoded_buffer *buf, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ buf->vp9.width = dec_params->frame_width_minus_1 + 1; -+ buf->vp9.height = dec_params->frame_height_minus_1 + 1; -+ buf->vp9.bit_depth = dec_params->bit_depth; -+} -+ -+static void update_ctx_cur_info(struct hantro_vp9_dec_hw_ctx *vp9_ctx, -+ struct hantro_decoded_buffer *buf, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ vp9_ctx->cur.valid = true; -+ vp9_ctx->cur.reference_mode = dec_params->reference_mode; -+ vp9_ctx->cur.interpolation_filter = dec_params->interpolation_filter; -+ vp9_ctx->cur.flags = dec_params->flags; -+ vp9_ctx->cur.timestamp = buf->base.vb.vb2_buf.timestamp; -+} -+ -+static void config_output(struct hantro_ctx *ctx, -+ struct hantro_decoded_buffer *dst, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ dma_addr_t luma_addr, chroma_addr, mv_addr; -+ -+ hantro_reg_write(ctx->dev, &g2_out_dis, 0); -+ hantro_reg_write(ctx->dev, &g2_output_format, 0); -+ -+ luma_addr = vb2_dma_contig_plane_dma_addr(&dst->base.vb.vb2_buf, 0); -+ hantro_write_addr(ctx->dev, G2_OUT_LUMA_ADDR, luma_addr); -+ -+ chroma_addr = luma_addr + chroma_offset(ctx, dec_params); -+ hantro_write_addr(ctx->dev, G2_OUT_CHROMA_ADDR, chroma_addr); -+ -+ mv_addr = luma_addr + mv_offset(ctx, dec_params); -+ hantro_write_addr(ctx->dev, G2_OUT_MV_ADDR, mv_addr); -+} -+ -+struct hantro_vp9_ref_reg { -+ const struct hantro_reg width; -+ const struct hantro_reg height; -+ const struct hantro_reg hor_scale; -+ const struct hantro_reg ver_scale; -+ u32 y_base; -+ u32 c_base; -+}; -+ -+static void config_ref(struct hantro_ctx *ctx, -+ struct hantro_decoded_buffer *dst, -+ const struct hantro_vp9_ref_reg *ref_reg, -+ const struct v4l2_ctrl_vp9_frame *dec_params, -+ u64 ref_ts) -+{ -+ struct hantro_decoded_buffer *buf; -+ dma_addr_t luma_addr, chroma_addr; -+ u32 refw, refh; -+ -+ buf = get_ref_buf(ctx, &dst->base.vb, ref_ts); -+ refw = buf->vp9.width; -+ refh = buf->vp9.height; -+ -+ hantro_reg_write(ctx->dev, &ref_reg->width, refw); -+ hantro_reg_write(ctx->dev, &ref_reg->height, refh); -+ -+ hantro_reg_write(ctx->dev, &ref_reg->hor_scale, (refw << 14) / dst->vp9.width); -+ hantro_reg_write(ctx->dev, &ref_reg->ver_scale, (refh << 14) / dst->vp9.height); -+ -+ luma_addr = vb2_dma_contig_plane_dma_addr(&buf->base.vb.vb2_buf, 0); -+ hantro_write_addr(ctx->dev, ref_reg->y_base, luma_addr); -+ -+ chroma_addr = luma_addr + chroma_offset(ctx, dec_params); -+ hantro_write_addr(ctx->dev, ref_reg->c_base, chroma_addr); -+} -+ -+static void config_ref_registers(struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct hantro_decoded_buffer *dst, -+ struct hantro_decoded_buffer *mv_ref) -+{ -+ static const struct hantro_vp9_ref_reg ref_regs[] = { -+ { -+ /* Last */ -+ .width = vp9_lref_width, -+ .height = vp9_lref_height, -+ .hor_scale = vp9_lref_hor_scale, -+ .ver_scale = vp9_lref_ver_scale, -+ .y_base = G2_REF_LUMA_ADDR(0), -+ .c_base = G2_REF_CHROMA_ADDR(0), -+ }, { -+ /* Golden */ -+ .width = vp9_gref_width, -+ .height = vp9_gref_height, -+ .hor_scale = vp9_gref_hor_scale, -+ .ver_scale = vp9_gref_ver_scale, -+ .y_base = G2_REF_LUMA_ADDR(4), -+ .c_base = G2_REF_CHROMA_ADDR(4), -+ }, { -+ /* Altref */ -+ .width = vp9_aref_width, -+ .height = vp9_aref_height, -+ .hor_scale = vp9_aref_hor_scale, -+ .ver_scale = vp9_aref_ver_scale, -+ .y_base = G2_REF_LUMA_ADDR(5), -+ .c_base = G2_REF_CHROMA_ADDR(5), -+ }, -+ }; -+ dma_addr_t mv_addr; -+ -+ config_ref(ctx, dst, &ref_regs[0], dec_params, dec_params->last_frame_ts); -+ config_ref(ctx, dst, &ref_regs[1], dec_params, dec_params->golden_frame_ts); -+ config_ref(ctx, dst, &ref_regs[2], dec_params, dec_params->alt_frame_ts); -+ -+ mv_addr = vb2_dma_contig_plane_dma_addr(&mv_ref->base.vb.vb2_buf, 0) + -+ mv_offset(ctx, dec_params); -+ hantro_write_addr(ctx->dev, G2_REF_MV_ADDR(0), mv_addr); -+ -+ hantro_reg_write(ctx->dev, &vp9_last_sign_bias, -+ dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_LAST ? 1 : 0); -+ -+ hantro_reg_write(ctx->dev, &vp9_gref_sign_bias, -+ dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_GOLDEN ? 1 : 0); -+ -+ hantro_reg_write(ctx->dev, &vp9_aref_sign_bias, -+ dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_ALT ? 1 : 0); -+} -+ -+static void recompute_tile_info(unsigned short *tile_info, unsigned int tiles, unsigned int sbs) -+{ -+ int i; -+ unsigned int accumulated = 0; -+ unsigned int next_accumulated; -+ -+ for (i = 1; i <= tiles; ++i) { -+ next_accumulated = i * sbs / tiles; -+ *tile_info++ = next_accumulated - accumulated; -+ accumulated = next_accumulated; -+ } -+} -+ -+static void -+recompute_tile_rc_info(struct hantro_ctx *ctx, -+ unsigned int tile_r, unsigned int tile_c, -+ unsigned int sbs_r, unsigned int sbs_c) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ -+ recompute_tile_info(vp9_ctx->tile_r_info, tile_r, sbs_r); -+ recompute_tile_info(vp9_ctx->tile_c_info, tile_c, sbs_c); -+ -+ vp9_ctx->last_tile_r = tile_r; -+ vp9_ctx->last_tile_c = tile_c; -+ vp9_ctx->last_sbs_r = sbs_r; -+ vp9_ctx->last_sbs_c = sbs_c; -+} -+ -+static inline unsigned int first_tile_row(unsigned int tile_r, unsigned int sbs_r) -+{ -+ if (tile_r == sbs_r + 1) -+ return 1; -+ -+ if (tile_r == sbs_r + 2) -+ return 2; -+ -+ return 0; -+} -+ -+static void -+fill_tile_info(struct hantro_ctx *ctx, -+ unsigned int tile_r, unsigned int tile_c, -+ unsigned int sbs_r, unsigned int sbs_c, -+ unsigned short *tile_mem) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ unsigned int i, j; -+ bool first = true; -+ -+ for (i = first_tile_row(tile_r, sbs_r); i < tile_r; ++i) { -+ unsigned short r_info = vp9_ctx->tile_r_info[i]; -+ -+ if (first) { -+ if (i > 0) -+ r_info += vp9_ctx->tile_r_info[0]; -+ if (i == 2) -+ r_info += vp9_ctx->tile_r_info[1]; -+ first = false; -+ } -+ for (j = 0; j < tile_c; ++j) { -+ *tile_mem++ = vp9_ctx->tile_c_info[j]; -+ *tile_mem++ = r_info; -+ } -+ } -+} -+ -+static void -+config_tiles(struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct hantro_decoded_buffer *dst) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ struct hantro_aux_buf *misc = &vp9_ctx->misc; -+ struct hantro_aux_buf *tile_edge = &vp9_ctx->tile_edge; -+ dma_addr_t addr; -+ unsigned short *tile_mem; -+ -+ addr = misc->dma + vp9_ctx->tile_info_offset; -+ hantro_write_addr(ctx->dev, G2_TILE_SIZES_ADDR, addr); -+ -+ tile_mem = misc->cpu + vp9_ctx->tile_info_offset; -+ if (dec_params->tile_cols_log2 || dec_params->tile_rows_log2) { -+ unsigned int tile_r = (1 << dec_params->tile_rows_log2); -+ unsigned int tile_c = (1 << dec_params->tile_cols_log2); -+ unsigned int sbs_r = hantro_vp9_num_sbs(dst->vp9.height); -+ unsigned int sbs_c = hantro_vp9_num_sbs(dst->vp9.width); -+ -+ if (tile_r != vp9_ctx->last_tile_r || tile_c != vp9_ctx->last_tile_c || -+ sbs_r != vp9_ctx->last_sbs_r || sbs_c != vp9_ctx->last_sbs_c) -+ recompute_tile_rc_info(ctx, tile_r, tile_c, sbs_r, sbs_c); -+ -+ fill_tile_info(ctx, tile_r, tile_c, sbs_r, sbs_c, tile_mem); -+ -+ hantro_reg_write(ctx->dev, &g2_tile_e, 1); -+ hantro_reg_write(ctx->dev, &g2_num_tile_cols, tile_c); -+ hantro_reg_write(ctx->dev, &g2_num_tile_rows, tile_r); -+ -+ } else { -+ tile_mem[0] = hantro_vp9_num_sbs(dst->vp9.width); -+ tile_mem[1] = hantro_vp9_num_sbs(dst->vp9.height); -+ -+ hantro_reg_write(ctx->dev, &g2_tile_e, 0); -+ hantro_reg_write(ctx->dev, &g2_num_tile_cols, 1); -+ hantro_reg_write(ctx->dev, &g2_num_tile_rows, 1); -+ } -+ -+ /* provide aux buffers even if no tiles are used */ -+ addr = tile_edge->dma; -+ hantro_write_addr(ctx->dev, G2_TILE_FILTER_ADDR, addr); -+ -+ addr = tile_edge->dma + vp9_ctx->bsd_ctrl_offset; -+ hantro_write_addr(ctx->dev, G2_TILE_BSD_ADDR, addr); -+} -+ -+static void -+update_feat_and_flag(struct hantro_vp9_dec_hw_ctx *vp9_ctx, -+ const struct v4l2_vp9_segmentation *seg, -+ unsigned int feature, -+ unsigned int segid) -+{ -+ u8 mask = V4L2_VP9_SEGMENT_FEATURE_ENABLED(feature); -+ -+ vp9_ctx->feature_data[segid][feature] = seg->feature_data[segid][feature]; -+ vp9_ctx->feature_enabled[segid] &= ~mask; -+ vp9_ctx->feature_enabled[segid] |= (seg->feature_enabled[segid] & mask); -+} -+ -+static inline s16 clip3(s16 x, s16 y, s16 z) -+{ -+ return (z < x) ? x : (z > y) ? y : z; -+} -+ -+static s16 feat_val_clip3(s16 feat_val, s16 feature_data, bool absolute, u8 clip) -+{ -+ if (absolute) -+ return feature_data; -+ -+ return clip3(0, 255, feat_val + feature_data); -+} -+ -+static void config_segment(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ const struct v4l2_vp9_segmentation *seg; -+ s16 feat_val; -+ unsigned char feat_id; -+ unsigned int segid; -+ bool segment_enabled, absolute, update_data; -+ -+ static const struct hantro_reg seg_regs[8][V4L2_VP9_SEG_LVL_MAX] = { -+ { vp9_quant_seg0, vp9_filt_level_seg0, vp9_refpic_seg0, vp9_skip_seg0 }, -+ { vp9_quant_seg1, vp9_filt_level_seg1, vp9_refpic_seg1, vp9_skip_seg1 }, -+ { vp9_quant_seg2, vp9_filt_level_seg2, vp9_refpic_seg2, vp9_skip_seg2 }, -+ { vp9_quant_seg3, vp9_filt_level_seg3, vp9_refpic_seg3, vp9_skip_seg3 }, -+ { vp9_quant_seg4, vp9_filt_level_seg4, vp9_refpic_seg4, vp9_skip_seg4 }, -+ { vp9_quant_seg5, vp9_filt_level_seg5, vp9_refpic_seg5, vp9_skip_seg5 }, -+ { vp9_quant_seg6, vp9_filt_level_seg6, vp9_refpic_seg6, vp9_skip_seg6 }, -+ { vp9_quant_seg7, vp9_filt_level_seg7, vp9_refpic_seg7, vp9_skip_seg7 }, -+ }; -+ -+ segment_enabled = !!(dec_params->seg.flags & V4L2_VP9_SEGMENTATION_FLAG_ENABLED); -+ hantro_reg_write(ctx->dev, &vp9_segment_e, segment_enabled); -+ hantro_reg_write(ctx->dev, &vp9_segment_upd_e, -+ !!(dec_params->seg.flags & V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP)); -+ hantro_reg_write(ctx->dev, &vp9_segment_temp_upd_e, -+ !!(dec_params->seg.flags & V4L2_VP9_SEGMENTATION_FLAG_TEMPORAL_UPDATE)); -+ -+ seg = &dec_params->seg; -+ absolute = !!(seg->flags & V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE); -+ update_data = !!(seg->flags & V4L2_VP9_SEGMENTATION_FLAG_UPDATE_DATA); -+ -+ for (segid = 0; segid < 8; ++segid) { -+ /* Quantizer segment feature */ -+ feat_id = V4L2_VP9_SEG_LVL_ALT_Q; -+ feat_val = dec_params->quant.base_q_idx; -+ if (segment_enabled) { -+ if (update_data) -+ update_feat_and_flag(vp9_ctx, seg, feat_id, segid); -+ if (v4l2_vp9_seg_feat_enabled(vp9_ctx->feature_enabled, feat_id, segid)) -+ feat_val = feat_val_clip3(feat_val, -+ vp9_ctx->feature_data[segid][feat_id], -+ absolute, 255); -+ } -+ hantro_reg_write(ctx->dev, &seg_regs[segid][feat_id], feat_val); -+ -+ /* Loop filter segment feature */ -+ feat_id = V4L2_VP9_SEG_LVL_ALT_L; -+ feat_val = dec_params->lf.level; -+ if (segment_enabled) { -+ if (update_data) -+ update_feat_and_flag(vp9_ctx, seg, feat_id, segid); -+ if (v4l2_vp9_seg_feat_enabled(vp9_ctx->feature_enabled, feat_id, segid)) -+ feat_val = feat_val_clip3(feat_val, -+ vp9_ctx->feature_data[segid][feat_id], -+ absolute, 63); -+ } -+ hantro_reg_write(ctx->dev, &seg_regs[segid][feat_id], feat_val); -+ -+ /* Reference frame segment feature */ -+ feat_id = V4L2_VP9_SEG_LVL_REF_FRAME; -+ feat_val = 0; -+ if (segment_enabled) { -+ if (update_data) -+ update_feat_and_flag(vp9_ctx, seg, feat_id, segid); -+ if (!(dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME) && -+ v4l2_vp9_seg_feat_enabled(vp9_ctx->feature_enabled, feat_id, segid)) -+ feat_val = vp9_ctx->feature_data[segid][feat_id] + 1; -+ } -+ hantro_reg_write(ctx->dev, &seg_regs[segid][feat_id], feat_val); -+ -+ /* Skip segment feature */ -+ feat_id = V4L2_VP9_SEG_LVL_SKIP; -+ feat_val = 0; -+ if (segment_enabled) { -+ if (update_data) -+ update_feat_and_flag(vp9_ctx, seg, feat_id, segid); -+ feat_val = v4l2_vp9_seg_feat_enabled(vp9_ctx->feature_enabled, -+ feat_id, segid) ? 1 : 0; -+ } -+ hantro_reg_write(ctx->dev, &seg_regs[segid][feat_id], feat_val); -+ } -+} -+ -+static void config_loop_filter(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ bool d = dec_params->lf.flags & V4L2_VP9_LOOP_FILTER_FLAG_DELTA_ENABLED; -+ -+ hantro_reg_write(ctx->dev, &vp9_filt_level, dec_params->lf.level); -+ hantro_reg_write(ctx->dev, &g2_out_filtering_dis, dec_params->lf.level == 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_sharpness, dec_params->lf.sharpness); -+ -+ hantro_reg_write(ctx->dev, &vp9_filt_ref_adj_0, d ? dec_params->lf.ref_deltas[0] : 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_ref_adj_1, d ? dec_params->lf.ref_deltas[1] : 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_ref_adj_2, d ? dec_params->lf.ref_deltas[2] : 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_ref_adj_3, d ? dec_params->lf.ref_deltas[3] : 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_mb_adj_0, d ? dec_params->lf.mode_deltas[0] : 0); -+ hantro_reg_write(ctx->dev, &vp9_filt_mb_adj_1, d ? dec_params->lf.mode_deltas[1] : 0); -+} -+ -+static void config_picture_dimensions(struct hantro_ctx *ctx, struct hantro_decoded_buffer *dst) -+{ -+ u32 pic_w_4x4, pic_h_4x4; -+ -+ hantro_reg_write(ctx->dev, &g2_pic_width_in_cbs, (dst->vp9.width + 7) / 8); -+ hantro_reg_write(ctx->dev, &g2_pic_height_in_cbs, (dst->vp9.height + 7) / 8); -+ pic_w_4x4 = roundup(dst->vp9.width, 8) >> 2; -+ pic_h_4x4 = roundup(dst->vp9.height, 8) >> 2; -+ hantro_reg_write(ctx->dev, &g2_pic_width_4x4, pic_w_4x4); -+ hantro_reg_write(ctx->dev, &g2_pic_height_4x4, pic_h_4x4); -+} -+ -+static void -+config_bit_depth(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ hantro_reg_write(ctx->dev, &g2_bit_depth_y_minus8, dec_params->bit_depth - 8); -+ hantro_reg_write(ctx->dev, &g2_bit_depth_c_minus8, dec_params->bit_depth - 8); -+} -+ -+static inline bool is_lossless(const struct v4l2_vp9_quantization *quant) -+{ -+ return quant->base_q_idx == 0 && quant->delta_q_uv_ac == 0 && -+ quant->delta_q_uv_dc == 0 && quant->delta_q_y_dc == 0; -+} -+ -+static void -+config_quant(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ hantro_reg_write(ctx->dev, &vp9_qp_delta_y_dc, dec_params->quant.delta_q_y_dc); -+ hantro_reg_write(ctx->dev, &vp9_qp_delta_ch_dc, dec_params->quant.delta_q_uv_dc); -+ hantro_reg_write(ctx->dev, &vp9_qp_delta_ch_ac, dec_params->quant.delta_q_uv_ac); -+ hantro_reg_write(ctx->dev, &vp9_lossless_e, is_lossless(&dec_params->quant)); -+} -+ -+static u32 -+hantro_interp_filter_from_v4l2(unsigned int interpolation_filter) -+{ -+ switch (interpolation_filter) { -+ case V4L2_VP9_INTERP_FILTER_EIGHTTAP: -+ return 0x1; -+ case V4L2_VP9_INTERP_FILTER_EIGHTTAP_SMOOTH: -+ return 0; -+ case V4L2_VP9_INTERP_FILTER_EIGHTTAP_SHARP: -+ return 0x2; -+ case V4L2_VP9_INTERP_FILTER_BILINEAR: -+ return 0x3; -+ case V4L2_VP9_INTERP_FILTER_SWITCHABLE: -+ return 0x4; -+ } -+ -+ return 0; -+} -+ -+static void -+config_others(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params, -+ bool intra_only, bool resolution_change) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ -+ hantro_reg_write(ctx->dev, &g2_idr_pic_e, intra_only); -+ -+ hantro_reg_write(ctx->dev, &vp9_transform_mode, vp9_ctx->cur.tx_mode); -+ -+ hantro_reg_write(ctx->dev, &vp9_mcomp_filt_type, intra_only ? -+ 0 : hantro_interp_filter_from_v4l2(dec_params->interpolation_filter)); -+ -+ hantro_reg_write(ctx->dev, &vp9_high_prec_mv_e, -+ !!(dec_params->flags & V4L2_VP9_FRAME_FLAG_ALLOW_HIGH_PREC_MV)); -+ -+ hantro_reg_write(ctx->dev, &vp9_comp_pred_mode, dec_params->reference_mode); -+ -+ hantro_reg_write(ctx->dev, &g2_tempor_mvp_e, -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) && -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME) && -+ !(vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME) && -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_INTRA_ONLY) && -+ !resolution_change && -+ vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_SHOW_FRAME -+ ); -+ -+ hantro_reg_write(ctx->dev, &g2_write_mvs_e, -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME)); -+} -+ -+static void -+config_compound_reference(struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ u32 comp_fixed_ref, comp_var_ref[2]; -+ bool last_ref_frame_sign_bias; -+ bool golden_ref_frame_sign_bias; -+ bool alt_ref_frame_sign_bias; -+ bool comp_ref_allowed = 0; -+ -+ comp_fixed_ref = 0; -+ comp_var_ref[0] = 0; -+ comp_var_ref[1] = 0; -+ -+ last_ref_frame_sign_bias = dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_LAST; -+ golden_ref_frame_sign_bias = dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_GOLDEN; -+ alt_ref_frame_sign_bias = dec_params->ref_frame_sign_bias & V4L2_VP9_SIGN_BIAS_ALT; -+ -+ /* 6.3.12 Frame reference mode syntax */ -+ comp_ref_allowed |= golden_ref_frame_sign_bias != last_ref_frame_sign_bias; -+ comp_ref_allowed |= alt_ref_frame_sign_bias != last_ref_frame_sign_bias; -+ -+ if (comp_ref_allowed) { -+ if (last_ref_frame_sign_bias == -+ golden_ref_frame_sign_bias) { -+ comp_fixed_ref = ALTREF_FRAME; -+ comp_var_ref[0] = LAST_FRAME; -+ comp_var_ref[1] = GOLDEN_FRAME; -+ } else if (last_ref_frame_sign_bias == -+ alt_ref_frame_sign_bias) { -+ comp_fixed_ref = GOLDEN_FRAME; -+ comp_var_ref[0] = LAST_FRAME; -+ comp_var_ref[1] = ALTREF_FRAME; -+ } else { -+ comp_fixed_ref = LAST_FRAME; -+ comp_var_ref[0] = GOLDEN_FRAME; -+ comp_var_ref[1] = ALTREF_FRAME; -+ } -+ } -+ -+ hantro_reg_write(ctx->dev, &vp9_comp_pred_fixed_ref, comp_fixed_ref); -+ hantro_reg_write(ctx->dev, &vp9_comp_pred_var_ref0, comp_var_ref[0]); -+ hantro_reg_write(ctx->dev, &vp9_comp_pred_var_ref1, comp_var_ref[1]); -+} -+ -+#define INNER_LOOP \ -+do { \ -+ for (m = 0; m < ARRAY_SIZE(adaptive->coef[0][0][0][0]); ++m) { \ -+ memcpy(adaptive->coef[i][j][k][l][m], \ -+ probs->coef[i][j][k][l][m], \ -+ sizeof(probs->coef[i][j][k][l][m])); \ -+ \ -+ adaptive->coef[i][j][k][l][m][3] = 0; \ -+ } \ -+} while (0) -+ -+static void config_probs(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ struct hantro_aux_buf *misc = &vp9_ctx->misc; -+ struct hantro_g2_all_probs *all_probs = misc->cpu; -+ struct hantro_g2_probs *adaptive; -+ struct hantro_g2_mv_probs *mv; -+ const struct v4l2_vp9_segmentation *seg = &dec_params->seg; -+ const struct v4l2_vp9_frame_context *probs = &vp9_ctx->probability_tables; -+ int i, j, k, l, m; -+ -+ for (i = 0; i < ARRAY_SIZE(all_probs->kf_y_mode_prob); ++i) -+ for (j = 0; j < ARRAY_SIZE(all_probs->kf_y_mode_prob[0]); ++j) { -+ memcpy(all_probs->kf_y_mode_prob[i][j], -+ v4l2_vp9_kf_y_mode_prob[i][j], -+ ARRAY_SIZE(all_probs->kf_y_mode_prob[i][j])); -+ -+ all_probs->kf_y_mode_prob_tail[i][j][0] = -+ v4l2_vp9_kf_y_mode_prob[i][j][8]; -+ } -+ -+ memcpy(all_probs->mb_segment_tree_probs, seg->tree_probs, -+ sizeof(all_probs->mb_segment_tree_probs)); -+ -+ memcpy(all_probs->segment_pred_probs, seg->pred_probs, -+ sizeof(all_probs->segment_pred_probs)); -+ -+ for (i = 0; i < ARRAY_SIZE(all_probs->kf_uv_mode_prob); ++i) { -+ memcpy(all_probs->kf_uv_mode_prob[i], v4l2_vp9_kf_uv_mode_prob[i], -+ ARRAY_SIZE(all_probs->kf_uv_mode_prob[i])); -+ -+ all_probs->kf_uv_mode_prob_tail[i][0] = v4l2_vp9_kf_uv_mode_prob[i][8]; -+ } -+ -+ adaptive = &all_probs->probs; -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->inter_mode); ++i) { -+ memcpy(adaptive->inter_mode[i], probs->inter_mode[i], -+ ARRAY_SIZE(probs->inter_mode[i])); -+ -+ adaptive->inter_mode[i][3] = 0; -+ } -+ -+ memcpy(adaptive->is_inter, probs->is_inter, sizeof(adaptive->is_inter)); -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->uv_mode); ++i) { -+ memcpy(adaptive->uv_mode[i], probs->uv_mode[i], -+ sizeof(adaptive->uv_mode[i])); -+ adaptive->uv_mode_tail[i][0] = probs->uv_mode[i][8]; -+ } -+ -+ memcpy(adaptive->tx8, probs->tx8, sizeof(adaptive->tx8)); -+ memcpy(adaptive->tx16, probs->tx16, sizeof(adaptive->tx16)); -+ memcpy(adaptive->tx32, probs->tx32, sizeof(adaptive->tx32)); -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->y_mode); ++i) { -+ memcpy(adaptive->y_mode[i], probs->y_mode[i], -+ ARRAY_SIZE(adaptive->y_mode[i])); -+ -+ adaptive->y_mode_tail[i][0] = probs->y_mode[i][8]; -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->partition[0]); ++i) { -+ memcpy(adaptive->partition[0][i], v4l2_vp9_kf_partition_probs[i], -+ sizeof(v4l2_vp9_kf_partition_probs[i])); -+ -+ adaptive->partition[0][i][3] = 0; -+ } -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->partition[1]); ++i) { -+ memcpy(adaptive->partition[1][i], probs->partition[i], -+ sizeof(probs->partition[i])); -+ -+ adaptive->partition[1][i][3] = 0; -+ } -+ -+ memcpy(adaptive->interp_filter, probs->interp_filter, -+ sizeof(adaptive->interp_filter)); -+ -+ memcpy(adaptive->comp_mode, probs->comp_mode, sizeof(adaptive->comp_mode)); -+ -+ memcpy(adaptive->skip, probs->skip, sizeof(adaptive->skip)); -+ -+ mv = &adaptive->mv; -+ -+ memcpy(mv->joint, probs->mv.joint, sizeof(mv->joint)); -+ memcpy(mv->sign, probs->mv.sign, sizeof(mv->sign)); -+ memcpy(mv->class0_bit, probs->mv.class0_bit, sizeof(mv->class0_bit)); -+ memcpy(mv->fr, probs->mv.fr, sizeof(mv->fr)); -+ memcpy(mv->class0_hp, probs->mv.class0_hp, sizeof(mv->class0_hp)); -+ memcpy(mv->hp, probs->mv.hp, sizeof(mv->hp)); -+ memcpy(mv->classes, probs->mv.classes, sizeof(mv->classes)); -+ memcpy(mv->class0_fr, probs->mv.class0_fr, sizeof(mv->class0_fr)); -+ memcpy(mv->bits, probs->mv.bits, sizeof(mv->bits)); -+ -+ memcpy(adaptive->single_ref, probs->single_ref, sizeof(adaptive->single_ref)); -+ -+ memcpy(adaptive->comp_ref, probs->comp_ref, sizeof(adaptive->comp_ref)); -+ -+ for (i = 0; i < ARRAY_SIZE(adaptive->coef); ++i) -+ for (j = 0; j < ARRAY_SIZE(adaptive->coef[0]); ++j) -+ for (k = 0; k < ARRAY_SIZE(adaptive->coef[0][0]); ++k) -+ for (l = 0; l < ARRAY_SIZE(adaptive->coef[0][0][0]); ++l) -+ INNER_LOOP; -+ -+ hantro_write_addr(ctx->dev, G2_VP9_PROBS_ADDR, misc->dma); -+} -+ -+static void config_counts(struct hantro_ctx *ctx) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_dec = &ctx->vp9_dec; -+ struct hantro_aux_buf *misc = &vp9_dec->misc; -+ dma_addr_t addr = misc->dma + vp9_dec->ctx_counters_offset; -+ -+ hantro_write_addr(ctx->dev, G2_VP9_CTX_COUNT_ADDR, addr); -+} -+ -+static void config_seg_map(struct hantro_ctx *ctx, -+ const struct v4l2_ctrl_vp9_frame *dec_params, -+ bool intra_only, bool update_map) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ struct hantro_aux_buf *segment_map = &vp9_ctx->segment_map; -+ dma_addr_t addr; -+ -+ if (intra_only || -+ (dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT)) { -+ memset(segment_map->cpu, 0, segment_map->size); -+ memset(vp9_ctx->feature_data, 0, sizeof(vp9_ctx->feature_data)); -+ memset(vp9_ctx->feature_enabled, 0, sizeof(vp9_ctx->feature_enabled)); -+ } -+ -+ addr = segment_map->dma + vp9_ctx->active_segment * vp9_ctx->segment_map_size; -+ hantro_write_addr(ctx->dev, G2_VP9_SEGMENT_READ_ADDR, addr); -+ -+ addr = segment_map->dma + (1 - vp9_ctx->active_segment) * vp9_ctx->segment_map_size; -+ hantro_write_addr(ctx->dev, G2_VP9_SEGMENT_WRITE_ADDR, addr); -+ -+ if (update_map) -+ vp9_ctx->active_segment = 1 - vp9_ctx->active_segment; -+} -+ -+static void -+config_source(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct vb2_v4l2_buffer *vb2_src) -+{ -+ dma_addr_t stream_base, tmp_addr; -+ unsigned int headres_size; -+ u32 src_len, start_bit, src_buf_len; -+ -+ headres_size = dec_params->uncompressed_header_size -+ + dec_params->compressed_header_size; -+ -+ stream_base = vb2_dma_contig_plane_dma_addr(&vb2_src->vb2_buf, 0); -+ hantro_write_addr(ctx->dev, G2_STREAM_ADDR, stream_base); -+ -+ tmp_addr = stream_base + headres_size; -+ start_bit = (tmp_addr & 0xf) * 8; -+ hantro_reg_write(ctx->dev, &g2_start_bit, start_bit); -+ -+ src_len = vb2_get_plane_payload(&vb2_src->vb2_buf, 0); -+ src_len += start_bit / 8 - headres_size; -+ hantro_reg_write(ctx->dev, &g2_stream_len, src_len); -+ -+ tmp_addr &= ~0xf; -+ hantro_reg_write(ctx->dev, &g2_strm_start_offset, tmp_addr - stream_base); -+ src_buf_len = vb2_plane_size(&vb2_src->vb2_buf, 0); -+ hantro_reg_write(ctx->dev, &g2_strm_buffer_len, src_buf_len); -+} -+ -+static void -+config_registers(struct hantro_ctx *ctx, const struct v4l2_ctrl_vp9_frame *dec_params, -+ struct vb2_v4l2_buffer *vb2_src, struct vb2_v4l2_buffer *vb2_dst) -+{ -+ struct hantro_decoded_buffer *dst, *last, *mv_ref; -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ const struct v4l2_vp9_segmentation *seg; -+ bool intra_only, resolution_change; -+ -+ /* vp9 stuff */ -+ dst = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf); -+ -+ if (vp9_ctx->last.valid) -+ last = get_ref_buf(ctx, &dst->base.vb, vp9_ctx->last.timestamp); -+ else -+ last = dst; -+ -+ update_dec_buf_info(dst, dec_params); -+ update_ctx_cur_info(vp9_ctx, dst, dec_params); -+ seg = &dec_params->seg; -+ -+ intra_only = !!(dec_params->flags & -+ (V4L2_VP9_FRAME_FLAG_KEY_FRAME | -+ V4L2_VP9_FRAME_FLAG_INTRA_ONLY)); -+ -+ if (!intra_only && -+ !(dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) && -+ vp9_ctx->last.valid) -+ mv_ref = last; -+ else -+ mv_ref = dst; -+ -+ resolution_change = dst->vp9.width != last->vp9.width || -+ dst->vp9.height != last->vp9.height; -+ -+ /* configure basic registers */ -+ hantro_reg_write(ctx->dev, &g2_mode, VP9_DEC_MODE); -+ hantro_reg_write(ctx->dev, &g2_strm_swap, 0xf); -+ hantro_reg_write(ctx->dev, &g2_dirmv_swap, 0xf); -+ hantro_reg_write(ctx->dev, &g2_compress_swap, 0xf); -+ hantro_reg_write(ctx->dev, &g2_buswidth, BUS_WIDTH_128); -+ hantro_reg_write(ctx->dev, &g2_max_burst, 16); -+ hantro_reg_write(ctx->dev, &g2_apf_threshold, 8); -+ hantro_reg_write(ctx->dev, &g2_ref_compress_bypass, 1); -+ hantro_reg_write(ctx->dev, &g2_clk_gate_e, 1); -+ hantro_reg_write(ctx->dev, &g2_max_cb_size, 6); -+ hantro_reg_write(ctx->dev, &g2_min_cb_size, 3); -+ -+ config_output(ctx, dst, dec_params); -+ -+ if (!intra_only) -+ config_ref_registers(ctx, dec_params, dst, mv_ref); -+ -+ config_tiles(ctx, dec_params, dst); -+ config_segment(ctx, dec_params); -+ config_loop_filter(ctx, dec_params); -+ config_picture_dimensions(ctx, dst); -+ config_bit_depth(ctx, dec_params); -+ config_quant(ctx, dec_params); -+ config_others(ctx, dec_params, intra_only, resolution_change); -+ config_compound_reference(ctx, dec_params); -+ config_probs(ctx, dec_params); -+ config_counts(ctx); -+ config_seg_map(ctx, dec_params, intra_only, -+ seg->flags & V4L2_VP9_SEGMENTATION_FLAG_UPDATE_MAP); -+ config_source(ctx, dec_params, vb2_src); -+} -+ -+int hantro_g2_vp9_dec_run(struct hantro_ctx *ctx) -+{ -+ const struct v4l2_ctrl_vp9_frame *decode_params; -+ struct vb2_v4l2_buffer *src; -+ struct vb2_v4l2_buffer *dst; -+ int ret; -+ -+ hantro_g2_check_idle(ctx->dev); -+ -+ ret = start_prepare_run(ctx, &decode_params); -+ if (ret) { -+ hantro_end_prepare_run(ctx); -+ return ret; -+ } -+ -+ src = hantro_get_src_buf(ctx); -+ dst = hantro_get_dst_buf(ctx); -+ -+ config_registers(ctx, decode_params, src, dst); -+ -+ hantro_end_prepare_run(ctx); -+ -+ vdpu_write(ctx->dev, G2_REG_INTERRUPT_DEC_E, G2_REG_INTERRUPT); -+ -+ return 0; -+} -+ -+#define copy_tx_and_skip(p1, p2) \ -+do { \ -+ memcpy((p1)->tx8, (p2)->tx8, sizeof((p1)->tx8)); \ -+ memcpy((p1)->tx16, (p2)->tx16, sizeof((p1)->tx16)); \ -+ memcpy((p1)->tx32, (p2)->tx32, sizeof((p1)->tx32)); \ -+ memcpy((p1)->skip, (p2)->skip, sizeof((p1)->skip)); \ -+} while (0) -+ -+void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ unsigned int fctx_idx; -+ -+ if (!(vp9_ctx->cur.flags & V4L2_VP9_FRAME_FLAG_REFRESH_FRAME_CTX)) -+ goto out_update_last; -+ -+ fctx_idx = vp9_ctx->cur.frame_context_idx; -+ -+ if (!(vp9_ctx->cur.flags & V4L2_VP9_FRAME_FLAG_PARALLEL_DEC_MODE)) { -+ /* error_resilient_mode == 0 && frame_parallel_decoding_mode == 0 */ -+ struct v4l2_vp9_frame_context *probs = &vp9_ctx->probability_tables; -+ bool frame_is_intra = vp9_ctx->cur.flags & -+ (V4L2_VP9_FRAME_FLAG_KEY_FRAME | V4L2_VP9_FRAME_FLAG_INTRA_ONLY); -+ struct tx_and_skip { -+ u8 tx8[2][1]; -+ u8 tx16[2][2]; -+ u8 tx32[2][3]; -+ u8 skip[3]; -+ } _tx_skip, *tx_skip = &_tx_skip; -+ struct v4l2_vp9_frame_symbol_counts *counts; -+ struct symbol_counts *hantro_cnts; -+ u32 tx16p[2][4]; -+ int i; -+ -+ /* buffer the forward-updated TX and skip probs */ -+ if (frame_is_intra) -+ copy_tx_and_skip(tx_skip, probs); -+ -+ /* 6.1.2 refresh_probs(): load_probs() and load_probs2() */ -+ *probs = vp9_ctx->frame_context[fctx_idx]; -+ -+ /* if FrameIsIntra then undo the effect of load_probs2() */ -+ if (frame_is_intra) -+ copy_tx_and_skip(probs, tx_skip); -+ -+ counts = &vp9_ctx->cnts; -+ hantro_cnts = vp9_ctx->misc.cpu + vp9_ctx->ctx_counters_offset; -+ for (i = 0; i < ARRAY_SIZE(tx16p); ++i) { -+ memcpy(tx16p[i], -+ hantro_cnts->tx16x16_count[i], -+ sizeof(hantro_cnts->tx16x16_count[0])); -+ tx16p[i][3] = 0; -+ } -+ counts->tx16p = &tx16p; -+ -+ v4l2_vp9_adapt_coef_probs(probs, counts, -+ !vp9_ctx->last.valid || -+ vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_KEY_FRAME, -+ frame_is_intra); -+ -+ if (!frame_is_intra) { -+ /* load_probs2() already done */ -+ u32 mv_mode[7][4]; -+ -+ for (i = 0; i < ARRAY_SIZE(mv_mode); ++i) { -+ mv_mode[i][0] = hantro_cnts->inter_mode_counts[i][1][0]; -+ mv_mode[i][1] = hantro_cnts->inter_mode_counts[i][2][0]; -+ mv_mode[i][2] = hantro_cnts->inter_mode_counts[i][0][0]; -+ mv_mode[i][3] = hantro_cnts->inter_mode_counts[i][2][1]; -+ } -+ counts->mv_mode = &mv_mode; -+ v4l2_vp9_adapt_noncoef_probs(&vp9_ctx->probability_tables, counts, -+ vp9_ctx->cur.reference_mode, -+ vp9_ctx->cur.interpolation_filter, -+ vp9_ctx->cur.tx_mode, vp9_ctx->cur.flags); -+ } -+ } -+ -+ vp9_ctx->frame_context[fctx_idx] = vp9_ctx->probability_tables; -+ -+out_update_last: -+ vp9_ctx->last = vp9_ctx->cur; -+} -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index 1d869abf90b2..fe5b51046d33 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - #include - - #define DEC_8190_ALIGN_MASK 0x07U -@@ -165,6 +166,82 @@ struct hantro_vp8_dec_hw_ctx { - struct hantro_aux_buf prob_tbl; - }; - -+/** -+ * struct hantro_vp9_frame_info -+ * -+ * @valid: frame info valid flag -+ * @frame_context_idx: index of frame context -+ * @reference_mode: inter prediction type -+ * @tx_mode: transform mode -+ * @interpolation_filter: filter selection for inter prediction -+ * @flags: frame flags -+ * @timestamp: frame timestamp -+ */ -+struct hantro_vp9_frame_info { -+ u32 valid : 1; -+ u32 frame_context_idx : 2; -+ u32 reference_mode : 2; -+ u32 tx_mode : 3; -+ u32 interpolation_filter : 3; -+ u32 flags; -+ u64 timestamp; -+}; -+ -+#define MAX_SB_COLS 64 -+#define MAX_SB_ROWS 34 -+ -+/** -+ * struct hantro_vp9_dec_hw_ctx -+ * -+ * @tile_edge: auxiliary DMA buffer for tile edge processing -+ * @segment_map: auxiliary DMA buffer for segment map -+ * @misc: auxiliary DMA buffer for tile info, probabilities and hw counters -+ * @cnts: vp9 library struct for abstracting hw counters access -+ * @probability_tables: VP9 probability tables implied by the spec -+ * @frame_context: VP9 frame contexts -+ * @cur: current frame information -+ * @last: last frame information -+ * @bsd_ctrl_offset: bsd offset into tile_edge -+ * @segment_map_size: size of segment map -+ * @ctx_counters_offset: hw counters offset into misc -+ * @tile_info_offset: tile info offset into misc -+ * @tile_r_info: per-tile information array -+ * @tile_c_info: per-tile information array -+ * @last_tile_r: last number of tile rows -+ * @last_tile_c: last number of tile cols -+ * @last_sbs_r: last number of superblock rows -+ * @last_sbs_c: last number of superblock cols -+ * @active_segment: number of active segment (alternating between 0 and 1) -+ * @feature_enabled: segmentation feature enabled flags -+ * @feature_data: segmentation feature data -+ */ -+struct hantro_vp9_dec_hw_ctx { -+ struct hantro_aux_buf tile_edge; -+ struct hantro_aux_buf segment_map; -+ struct hantro_aux_buf misc; -+ struct v4l2_vp9_frame_symbol_counts cnts; -+ struct v4l2_vp9_frame_context probability_tables; -+ struct v4l2_vp9_frame_context frame_context[4]; -+ struct hantro_vp9_frame_info cur; -+ struct hantro_vp9_frame_info last; -+ -+ unsigned int bsd_ctrl_offset; -+ unsigned int segment_map_size; -+ unsigned int ctx_counters_offset; -+ unsigned int tile_info_offset; -+ -+ unsigned short tile_r_info[MAX_SB_ROWS]; -+ unsigned short tile_c_info[MAX_SB_COLS]; -+ unsigned int last_tile_r; -+ unsigned int last_tile_c; -+ unsigned int last_sbs_r; -+ unsigned int last_sbs_c; -+ -+ unsigned int active_segment; -+ u8 feature_enabled[8]; -+ s16 feature_data[8][4]; -+}; -+ - /** - * struct hantro_postproc_ctx - * -@@ -271,6 +348,24 @@ void hantro_hevc_ref_remove_unused(struct hantro_ctx *ctx); - size_t hantro_hevc_chroma_offset(const struct v4l2_ctrl_hevc_sps *sps); - size_t hantro_hevc_motion_vectors_offset(const struct v4l2_ctrl_hevc_sps *sps); - -+static inline unsigned short hantro_vp9_num_sbs(unsigned short dimension) -+{ -+ return (dimension + 63) / 64; -+} -+ -+static inline size_t -+hantro_vp9_mv_size(unsigned int width, unsigned int height) -+{ -+ int num_ctbs; -+ -+ /* -+ * There can be up to (CTBs x 64) number of blocks, -+ * and the motion vector for each block needs 16 bytes. -+ */ -+ num_ctbs = hantro_vp9_num_sbs(width) * hantro_vp9_num_sbs(height); -+ return (num_ctbs * 64) * 16; -+} -+ - static inline size_t - hantro_h264_mv_size(unsigned int width, unsigned int height) - { -@@ -312,6 +407,10 @@ void hantro_vp8_dec_exit(struct hantro_ctx *ctx); - void hantro_vp8_prob_update(struct hantro_ctx *ctx, - const struct v4l2_ctrl_vp8_frame *hdr); - -+int hantro_g2_vp9_dec_run(struct hantro_ctx *ctx); -+void hantro_g2_vp9_dec_done(struct hantro_ctx *ctx); -+int hantro_vp9_dec_init(struct hantro_ctx *ctx); -+void hantro_vp9_dec_exit(struct hantro_ctx *ctx); - void hantro_g2_check_idle(struct hantro_dev *vpu); - - #endif /* HANTRO_HW_H_ */ -diff --git a/drivers/staging/media/hantro/hantro_v4l2.c b/drivers/staging/media/hantro/hantro_v4l2.c -index d1f060c55fed..e4b0645ba6fc 100644 ---- a/drivers/staging/media/hantro/hantro_v4l2.c -+++ b/drivers/staging/media/hantro/hantro_v4l2.c -@@ -299,6 +299,11 @@ static int hantro_try_fmt(const struct hantro_ctx *ctx, - pix_mp->plane_fmt[0].sizeimage += - hantro_h264_mv_size(pix_mp->width, - pix_mp->height); -+ else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME && -+ !hantro_needs_postproc(ctx, fmt)) -+ pix_mp->plane_fmt[0].sizeimage += -+ hantro_vp9_mv_size(pix_mp->width, -+ pix_mp->height); - } else if (!pix_mp->plane_fmt[0].sizeimage) { - /* - * For coded formats the application can specify -@@ -407,6 +412,7 @@ hantro_update_requires_request(struct hantro_ctx *ctx, u32 fourcc) - case V4L2_PIX_FMT_VP8_FRAME: - case V4L2_PIX_FMT_H264_SLICE: - case V4L2_PIX_FMT_HEVC_SLICE: -+ case V4L2_PIX_FMT_VP9_FRAME: - ctx->fh.m2m_ctx->out_q_ctx.q.requires_requests = true; - break; - default: -diff --git a/drivers/staging/media/hantro/hantro_vp9.c b/drivers/staging/media/hantro/hantro_vp9.c -new file mode 100644 -index 000000000000..566cd376c097 ---- /dev/null -+++ b/drivers/staging/media/hantro/hantro_vp9.c -@@ -0,0 +1,240 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Hantro VP9 codec driver -+ * -+ * Copyright (C) 2021 Collabora Ltd. -+ */ -+ -+#include -+#include -+ -+#include "hantro.h" -+#include "hantro_hw.h" -+#include "hantro_vp9.h" -+ -+#define POW2(x) (1 << (x)) -+ -+#define MAX_LOG2_TILE_COLUMNS 6 -+#define MAX_NUM_TILE_COLS POW2(MAX_LOG2_TILE_COLUMNS) -+#define MAX_TILE_COLS 20 -+#define MAX_TILE_ROWS 22 -+ -+static size_t hantro_vp9_tile_filter_size(unsigned int height) -+{ -+ u32 h, height32, size; -+ -+ h = roundup(height, 8); -+ -+ height32 = roundup(h, 64); -+ size = 24 * height32 * (MAX_NUM_TILE_COLS - 1); /* luma: 8, chroma: 8 + 8 */ -+ -+ return size; -+} -+ -+static size_t hantro_vp9_bsd_control_size(unsigned int height) -+{ -+ u32 h, height32; -+ -+ h = roundup(height, 8); -+ height32 = roundup(h, 64); -+ -+ return 16 * (height32 / 4) * (MAX_NUM_TILE_COLS - 1); -+} -+ -+static size_t hantro_vp9_segment_map_size(unsigned int width, unsigned int height) -+{ -+ u32 w, h; -+ int num_ctbs; -+ -+ w = roundup(width, 8); -+ h = roundup(height, 8); -+ num_ctbs = ((w + 63) / 64) * ((h + 63) / 64); -+ -+ return num_ctbs * 32; -+} -+ -+static inline size_t hantro_vp9_prob_tab_size(void) -+{ -+ return roundup(sizeof(struct hantro_g2_all_probs), 16); -+} -+ -+static inline size_t hantro_vp9_count_tab_size(void) -+{ -+ return roundup(sizeof(struct symbol_counts), 16); -+} -+ -+static inline size_t hantro_vp9_tile_info_size(void) -+{ -+ return roundup((MAX_TILE_COLS * MAX_TILE_ROWS * 4 * sizeof(u16) + 15 + 16) & ~0xf, 16); -+} -+ -+static void *get_coeffs_arr(struct symbol_counts *cnts, int i, int j, int k, int l, int m) -+{ -+ if (i == 0) -+ return &cnts->count_coeffs[j][k][l][m]; -+ -+ if (i == 1) -+ return &cnts->count_coeffs8x8[j][k][l][m]; -+ -+ if (i == 2) -+ return &cnts->count_coeffs16x16[j][k][l][m]; -+ -+ if (i == 3) -+ return &cnts->count_coeffs32x32[j][k][l][m]; -+ -+ return NULL; -+} -+ -+static void *get_eobs1(struct symbol_counts *cnts, int i, int j, int k, int l, int m) -+{ -+ if (i == 0) -+ return &cnts->count_coeffs[j][k][l][m][3]; -+ -+ if (i == 1) -+ return &cnts->count_coeffs8x8[j][k][l][m][3]; -+ -+ if (i == 2) -+ return &cnts->count_coeffs16x16[j][k][l][m][3]; -+ -+ if (i == 3) -+ return &cnts->count_coeffs32x32[j][k][l][m][3]; -+ -+ return NULL; -+} -+ -+#define INNER_LOOP \ -+ do { \ -+ for (m = 0; m < ARRAY_SIZE(vp9_ctx->cnts.coeff[i][0][0][0]); ++m) { \ -+ vp9_ctx->cnts.coeff[i][j][k][l][m] = \ -+ get_coeffs_arr(cnts, i, j, k, l, m); \ -+ vp9_ctx->cnts.eob[i][j][k][l][m][0] = \ -+ &cnts->count_eobs[i][j][k][l][m]; \ -+ vp9_ctx->cnts.eob[i][j][k][l][m][1] = \ -+ get_eobs1(cnts, i, j, k, l, m); \ -+ } \ -+ } while (0) -+ -+static void init_v4l2_vp9_count_tbl(struct hantro_ctx *ctx) -+{ -+ struct hantro_vp9_dec_hw_ctx *vp9_ctx = &ctx->vp9_dec; -+ struct symbol_counts *cnts = vp9_ctx->misc.cpu + vp9_ctx->ctx_counters_offset; -+ int i, j, k, l, m; -+ -+ vp9_ctx->cnts.partition = &cnts->partition_counts; -+ vp9_ctx->cnts.skip = &cnts->mbskip_count; -+ vp9_ctx->cnts.intra_inter = &cnts->intra_inter_count; -+ vp9_ctx->cnts.tx32p = &cnts->tx32x32_count; -+ /* -+ * g2 hardware uses tx16x16_count[2][3], while the api -+ * expects tx16p[2][4], so this must be explicitly copied -+ * into vp9_ctx->cnts.tx16p when passing the data to the -+ * vp9 library function -+ */ -+ vp9_ctx->cnts.tx8p = &cnts->tx8x8_count; -+ -+ vp9_ctx->cnts.y_mode = &cnts->sb_ymode_counts; -+ vp9_ctx->cnts.uv_mode = &cnts->uv_mode_counts; -+ vp9_ctx->cnts.comp = &cnts->comp_inter_count; -+ vp9_ctx->cnts.comp_ref = &cnts->comp_ref_count; -+ vp9_ctx->cnts.single_ref = &cnts->single_ref_count; -+ vp9_ctx->cnts.filter = &cnts->switchable_interp_counts; -+ vp9_ctx->cnts.mv_joint = &cnts->mv_counts.joints; -+ vp9_ctx->cnts.sign = &cnts->mv_counts.sign; -+ vp9_ctx->cnts.classes = &cnts->mv_counts.classes; -+ vp9_ctx->cnts.class0 = &cnts->mv_counts.class0; -+ vp9_ctx->cnts.bits = &cnts->mv_counts.bits; -+ vp9_ctx->cnts.class0_fp = &cnts->mv_counts.class0_fp; -+ vp9_ctx->cnts.fp = &cnts->mv_counts.fp; -+ vp9_ctx->cnts.class0_hp = &cnts->mv_counts.class0_hp; -+ vp9_ctx->cnts.hp = &cnts->mv_counts.hp; -+ -+ for (i = 0; i < ARRAY_SIZE(vp9_ctx->cnts.coeff); ++i) -+ for (j = 0; j < ARRAY_SIZE(vp9_ctx->cnts.coeff[i]); ++j) -+ for (k = 0; k < ARRAY_SIZE(vp9_ctx->cnts.coeff[i][0]); ++k) -+ for (l = 0; l < ARRAY_SIZE(vp9_ctx->cnts.coeff[i][0][0]); ++l) -+ INNER_LOOP; -+} -+ -+int hantro_vp9_dec_init(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ const struct hantro_variant *variant = vpu->variant; -+ struct hantro_vp9_dec_hw_ctx *vp9_dec = &ctx->vp9_dec; -+ struct hantro_aux_buf *tile_edge = &vp9_dec->tile_edge; -+ struct hantro_aux_buf *segment_map = &vp9_dec->segment_map; -+ struct hantro_aux_buf *misc = &vp9_dec->misc; -+ u32 i, max_width, max_height, size; -+ -+ if (variant->num_dec_fmts < 1) -+ return -EINVAL; -+ -+ for (i = 0; i < variant->num_dec_fmts; ++i) -+ if (variant->dec_fmts[i].fourcc == V4L2_PIX_FMT_VP9_FRAME) -+ break; -+ -+ if (i == variant->num_dec_fmts) -+ return -EINVAL; -+ -+ max_width = vpu->variant->dec_fmts[i].frmsize.max_width; -+ max_height = vpu->variant->dec_fmts[i].frmsize.max_height; -+ -+ size = hantro_vp9_tile_filter_size(max_height); -+ vp9_dec->bsd_ctrl_offset = size; -+ size += hantro_vp9_bsd_control_size(max_height); -+ -+ tile_edge->cpu = dma_alloc_coherent(vpu->dev, size, &tile_edge->dma, GFP_KERNEL); -+ if (!tile_edge->cpu) -+ return -ENOMEM; -+ -+ tile_edge->size = size; -+ memset(tile_edge->cpu, 0, size); -+ -+ size = hantro_vp9_segment_map_size(max_width, max_height); -+ vp9_dec->segment_map_size = size; -+ size *= 2; /* we need two areas of this size, used alternately */ -+ -+ segment_map->cpu = dma_alloc_coherent(vpu->dev, size, &segment_map->dma, GFP_KERNEL); -+ if (!segment_map->cpu) -+ goto err_segment_map; -+ -+ segment_map->size = size; -+ memset(segment_map->cpu, 0, size); -+ -+ size = hantro_vp9_prob_tab_size(); -+ vp9_dec->ctx_counters_offset = size; -+ size += hantro_vp9_count_tab_size(); -+ vp9_dec->tile_info_offset = size; -+ size += hantro_vp9_tile_info_size(); -+ -+ misc->cpu = dma_alloc_coherent(vpu->dev, size, &misc->dma, GFP_KERNEL); -+ if (!misc->cpu) -+ goto err_misc; -+ -+ misc->size = size; -+ memset(misc->cpu, 0, size); -+ -+ init_v4l2_vp9_count_tbl(ctx); -+ -+ return 0; -+ -+err_misc: -+ dma_free_coherent(vpu->dev, segment_map->size, segment_map->cpu, segment_map->dma); -+ -+err_segment_map: -+ dma_free_coherent(vpu->dev, tile_edge->size, tile_edge->cpu, tile_edge->dma); -+ -+ return -ENOMEM; -+} -+ -+void hantro_vp9_dec_exit(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ struct hantro_vp9_dec_hw_ctx *vp9_dec = &ctx->vp9_dec; -+ struct hantro_aux_buf *tile_edge = &vp9_dec->tile_edge; -+ struct hantro_aux_buf *segment_map = &vp9_dec->segment_map; -+ struct hantro_aux_buf *misc = &vp9_dec->misc; -+ -+ dma_free_coherent(vpu->dev, misc->size, misc->cpu, misc->dma); -+ dma_free_coherent(vpu->dev, segment_map->size, segment_map->cpu, segment_map->dma); -+ dma_free_coherent(vpu->dev, tile_edge->size, tile_edge->cpu, tile_edge->dma); -+} -diff --git a/drivers/staging/media/hantro/hantro_vp9.h b/drivers/staging/media/hantro/hantro_vp9.h -new file mode 100644 -index 000000000000..26b69275f098 ---- /dev/null -+++ b/drivers/staging/media/hantro/hantro_vp9.h -@@ -0,0 +1,102 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Hantro VP9 codec driver -+ * -+ * Copyright (C) 2021 Collabora Ltd. -+ */ -+ -+struct hantro_g2_mv_probs { -+ u8 joint[3]; -+ u8 sign[2]; -+ u8 class0_bit[2][1]; -+ u8 fr[2][3]; -+ u8 class0_hp[2]; -+ u8 hp[2]; -+ u8 classes[2][10]; -+ u8 class0_fr[2][2][3]; -+ u8 bits[2][10]; -+}; -+ -+struct hantro_g2_probs { -+ u8 inter_mode[7][4]; -+ u8 is_inter[4]; -+ u8 uv_mode[10][8]; -+ u8 tx8[2][1]; -+ u8 tx16[2][2]; -+ u8 tx32[2][3]; -+ u8 y_mode_tail[4][1]; -+ u8 y_mode[4][8]; -+ u8 partition[2][16][4]; /* [keyframe][][], [inter][][] */ -+ u8 uv_mode_tail[10][1]; -+ u8 interp_filter[4][2]; -+ u8 comp_mode[5]; -+ u8 skip[3]; -+ -+ u8 pad1[1]; -+ -+ struct hantro_g2_mv_probs mv; -+ -+ u8 single_ref[5][2]; -+ u8 comp_ref[5]; -+ -+ u8 pad2[17]; -+ -+ u8 coef[4][2][2][6][6][4]; -+}; -+ -+struct hantro_g2_all_probs { -+ u8 kf_y_mode_prob[10][10][8]; -+ -+ u8 kf_y_mode_prob_tail[10][10][1]; -+ u8 ref_pred_probs[3]; -+ u8 mb_segment_tree_probs[7]; -+ u8 segment_pred_probs[3]; -+ u8 ref_scores[4]; -+ u8 prob_comppred[2]; -+ -+ u8 pad1[9]; -+ -+ u8 kf_uv_mode_prob[10][8]; -+ u8 kf_uv_mode_prob_tail[10][1]; -+ -+ u8 pad2[6]; -+ -+ struct hantro_g2_probs probs; -+}; -+ -+struct mv_counts { -+ u32 joints[4]; -+ u32 sign[2][2]; -+ u32 classes[2][11]; -+ u32 class0[2][2]; -+ u32 bits[2][10][2]; -+ u32 class0_fp[2][2][4]; -+ u32 fp[2][4]; -+ u32 class0_hp[2][2]; -+ u32 hp[2][2]; -+}; -+ -+struct symbol_counts { -+ u32 inter_mode_counts[7][3][2]; -+ u32 sb_ymode_counts[4][10]; -+ u32 uv_mode_counts[10][10]; -+ u32 partition_counts[16][4]; -+ u32 switchable_interp_counts[4][3]; -+ u32 intra_inter_count[4][2]; -+ u32 comp_inter_count[5][2]; -+ u32 single_ref_count[5][2][2]; -+ u32 comp_ref_count[5][2]; -+ u32 tx32x32_count[2][4]; -+ u32 tx16x16_count[2][3]; -+ u32 tx8x8_count[2][2]; -+ u32 mbskip_count[3][2]; -+ -+ struct mv_counts mv_counts; -+ -+ u32 count_coeffs[2][2][6][6][4]; -+ u32 count_coeffs8x8[2][2][6][6][4]; -+ u32 count_coeffs16x16[2][2][6][6][4]; -+ u32 count_coeffs32x32[2][2][6][6][4]; -+ -+ u32 count_eobs[4][2][2][6][6]; -+}; -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index a40b161e5956..455a107ffb02 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -150,6 +150,19 @@ static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = { - .step_height = MB_DIM, - }, - }, -+ { -+ .fourcc = V4L2_PIX_FMT_VP9_FRAME, -+ .codec_mode = HANTRO_MODE_VP9_DEC, -+ .max_depth = 2, -+ .frmsize = { -+ .min_width = 48, -+ .max_width = 3840, -+ .step_width = MB_DIM, -+ .min_height = 48, -+ .max_height = 2160, -+ .step_height = MB_DIM, -+ }, -+ }, - }; - - static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id) -@@ -241,6 +254,13 @@ static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = { - .init = hantro_hevc_dec_init, - .exit = hantro_hevc_dec_exit, - }, -+ [HANTRO_MODE_VP9_DEC] = { -+ .run = hantro_g2_vp9_dec_run, -+ .done = hantro_g2_vp9_dec_done, -+ .reset = imx8m_vpu_g2_reset, -+ .init = hantro_vp9_dec_init, -+ .exit = hantro_vp9_dec_exit, -+ }, - }; - - /* -@@ -281,7 +301,7 @@ const struct hantro_variant imx8mq_vpu_g2_variant = { - .dec_offset = 0x0, - .dec_fmts = imx8m_vpu_g2_dec_fmts, - .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_g2_dec_fmts), -- .codec = HANTRO_HEVC_DECODER, -+ .codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER, - .codec_ops = imx8mq_vpu_g2_codec_ops, - .init = imx8mq_vpu_hw_init, - .runtime_resume = imx8mq_runtime_resume, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:41 +0100 -Subject: [PATCH] media: hantro: Staticize a struct in postprocessor code - -The struct is not used outside this file, so it can be static. - -Signed-off-by: Andrzej Pietrasiewicz -Reviewed-by: Ezequiel Garcia -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/hantro/hantro_postproc.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index 4549aec08feb..89de43021779 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -33,7 +33,7 @@ - #define VPU_PP_OUT_RGB 0x0 - #define VPU_PP_OUT_YUYV 0x3 - --const struct hantro_postproc_regs hantro_g1_postproc_regs = { -+static const struct hantro_postproc_regs hantro_g1_postproc_regs = { - .pipeline_en = {G1_REG_PP_INTERRUPT, 1, 0x1}, - .max_burst = {G1_REG_PP_DEV_CONFIG, 0, 0x1f}, - .clk_gate = {G1_REG_PP_DEV_CONFIG, 1, 0x1}, - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Andrzej Pietrasiewicz -Date: Tue, 16 Nov 2021 15:38:42 +0100 -Subject: [PATCH] media: hantro: Support NV12 on the G2 core - -The G2 decoder block produces NV12 4x4 tiled format (NV12_4L4). -Enable the G2 post-processor block, in order to produce regular NV12. - -The logic in hantro_postproc.c is leveraged to take care of allocating -the extra buffers and configure the post-processor, which is -significantly simpler than the one on the G1. - -Signed-off-by: Ezequiel Garcia -Signed-off-by: Andrzej Pietrasiewicz -Signed-off-by: Hans Verkuil ---- - .../staging/media/hantro/hantro_g2_vp9_dec.c | 6 ++-- - drivers/staging/media/hantro/hantro_hw.h | 1 + - .../staging/media/hantro/hantro_postproc.c | 31 +++++++++++++++++++ - drivers/staging/media/hantro/imx8m_vpu_hw.c | 11 +++++++ - 4 files changed, 46 insertions(+), 3 deletions(-) - -diff --git a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -index fc55b03a8004..e04242d10fa2 100644 ---- a/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -+++ b/drivers/staging/media/hantro/hantro_g2_vp9_dec.c -@@ -152,7 +152,7 @@ static void config_output(struct hantro_ctx *ctx, - hantro_reg_write(ctx->dev, &g2_out_dis, 0); - hantro_reg_write(ctx->dev, &g2_output_format, 0); - -- luma_addr = vb2_dma_contig_plane_dma_addr(&dst->base.vb.vb2_buf, 0); -+ luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf); - hantro_write_addr(ctx->dev, G2_OUT_LUMA_ADDR, luma_addr); - - chroma_addr = luma_addr + chroma_offset(ctx, dec_params); -@@ -191,7 +191,7 @@ static void config_ref(struct hantro_ctx *ctx, - hantro_reg_write(ctx->dev, &ref_reg->hor_scale, (refw << 14) / dst->vp9.width); - hantro_reg_write(ctx->dev, &ref_reg->ver_scale, (refh << 14) / dst->vp9.height); - -- luma_addr = vb2_dma_contig_plane_dma_addr(&buf->base.vb.vb2_buf, 0); -+ luma_addr = hantro_get_dec_buf_addr(ctx, &buf->base.vb.vb2_buf); - hantro_write_addr(ctx->dev, ref_reg->y_base, luma_addr); - - chroma_addr = luma_addr + chroma_offset(ctx, dec_params); -@@ -236,7 +236,7 @@ static void config_ref_registers(struct hantro_ctx *ctx, - config_ref(ctx, dst, &ref_regs[1], dec_params, dec_params->golden_frame_ts); - config_ref(ctx, dst, &ref_regs[2], dec_params, dec_params->alt_frame_ts); - -- mv_addr = vb2_dma_contig_plane_dma_addr(&mv_ref->base.vb.vb2_buf, 0) + -+ mv_addr = hantro_get_dec_buf_addr(ctx, &mv_ref->base.vb.vb2_buf) + - mv_offset(ctx, dec_params); - hantro_write_addr(ctx->dev, G2_REF_MV_ADDR(0), mv_addr); - -diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h -index fe5b51046d33..dbe51303724b 100644 ---- a/drivers/staging/media/hantro/hantro_hw.h -+++ b/drivers/staging/media/hantro/hantro_hw.h -@@ -310,6 +310,7 @@ extern const struct hantro_variant rk3399_vpu_variant; - extern const struct hantro_variant sama5d4_vdec_variant; - - extern const struct hantro_postproc_ops hantro_g1_postproc_ops; -+extern const struct hantro_postproc_ops hantro_g2_postproc_ops; - - extern const u32 hantro_vp8_dec_mc_filter[8][6]; - -diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c -index 89de43021779..a7774ad4c445 100644 ---- a/drivers/staging/media/hantro/hantro_postproc.c -+++ b/drivers/staging/media/hantro/hantro_postproc.c -@@ -11,6 +11,7 @@ - #include "hantro.h" - #include "hantro_hw.h" - #include "hantro_g1_regs.h" -+#include "hantro_g2_regs.h" - - #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \ - { \ -@@ -99,6 +100,21 @@ static void hantro_postproc_g1_enable(struct hantro_ctx *ctx) - HANTRO_PP_REG_WRITE(vpu, display_width, ctx->dst_fmt.width); - } - -+static void hantro_postproc_g2_enable(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ struct vb2_v4l2_buffer *dst_buf; -+ size_t chroma_offset = ctx->dst_fmt.width * ctx->dst_fmt.height; -+ dma_addr_t dst_dma; -+ -+ dst_buf = hantro_get_dst_buf(ctx); -+ dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ -+ hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma); -+ hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + chroma_offset); -+ hantro_reg_write(vpu, &g2_out_rs_e, 1); -+} -+ - void hantro_postproc_free(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -@@ -127,6 +143,9 @@ int hantro_postproc_alloc(struct hantro_ctx *ctx) - if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE) - buf_size += hantro_h264_mv_size(ctx->dst_fmt.width, - ctx->dst_fmt.height); -+ else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME) -+ buf_size += hantro_vp9_mv_size(ctx->dst_fmt.width, -+ ctx->dst_fmt.height); - - for (i = 0; i < num_buffers; ++i) { - struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i]; -@@ -152,6 +171,13 @@ static void hantro_postproc_g1_disable(struct hantro_ctx *ctx) - HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0); - } - -+static void hantro_postproc_g2_disable(struct hantro_ctx *ctx) -+{ -+ struct hantro_dev *vpu = ctx->dev; -+ -+ hantro_reg_write(vpu, &g2_out_rs_e, 0); -+} -+ - void hantro_postproc_disable(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -@@ -172,3 +198,8 @@ const struct hantro_postproc_ops hantro_g1_postproc_ops = { - .enable = hantro_postproc_g1_enable, - .disable = hantro_postproc_g1_disable, - }; -+ -+const struct hantro_postproc_ops hantro_g2_postproc_ops = { -+ .enable = hantro_postproc_g2_enable, -+ .disable = hantro_postproc_g2_disable, -+}; -diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c -index 455a107ffb02..1a43f6fceef9 100644 ---- a/drivers/staging/media/hantro/imx8m_vpu_hw.c -+++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c -@@ -132,6 +132,14 @@ static const struct hantro_fmt imx8m_vpu_dec_fmts[] = { - }, - }; - -+static const struct hantro_fmt imx8m_vpu_g2_postproc_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_NV12, -+ .codec_mode = HANTRO_MODE_NONE, -+ .postprocessed = true, -+ }, -+}; -+ - static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_NV12_4L4, -@@ -301,6 +309,9 @@ const struct hantro_variant imx8mq_vpu_g2_variant = { - .dec_offset = 0x0, - .dec_fmts = imx8m_vpu_g2_dec_fmts, - .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_g2_dec_fmts), -+ .postproc_fmts = imx8m_vpu_g2_postproc_fmts, -+ .num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_g2_postproc_fmts), -+ .postproc_ops = &hantro_g2_postproc_ops, - .codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER, - .codec_ops = imx8mq_vpu_g2_codec_ops, - .init = imx8mq_vpu_hw_init, diff --git a/projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch b/projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch index 46f742fcd4..7fb50ab8dc 100644 --- a/projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch +++ b/projects/Rockchip/patches/linux/default/linux-0020-drm-from-list.patch @@ -362,169 +362,3 @@ index be74c87a8be4..288462fd5d8e 100644 DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); return ret; -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Thomas Zimmermann -Date: Thu, 24 Jun 2021 11:55:02 +0200 -Subject: [PATCH] drm/rockchip: Implement mmap as GEM object function - -Moving the driver-specific mmap code into a GEM object function allows -for using DRM helpers for various mmap callbacks. - -The respective rockchip functions are being removed. The file_operations -structure fops is now being created by the helper macro -DEFINE_DRM_GEM_FOPS(). - -Signed-off-by: Thomas Zimmermann -Tested-by: Heiko Stuebner ---- - drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 13 +----- - drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c | 3 +- - drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 44 +++++-------------- - drivers/gpu/drm/rockchip/rockchip_drm_gem.h | 7 --- - 4 files changed, 15 insertions(+), 52 deletions(-) - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -index e4ebe60b3cc1..69c699459dce 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c -@@ -199,16 +199,7 @@ static void rockchip_drm_unbind(struct device *dev) - drm_dev_put(drm_dev); - } - --static const struct file_operations rockchip_drm_driver_fops = { -- .owner = THIS_MODULE, -- .open = drm_open, -- .mmap = rockchip_gem_mmap, -- .poll = drm_poll, -- .read = drm_read, -- .unlocked_ioctl = drm_ioctl, -- .compat_ioctl = drm_compat_ioctl, -- .release = drm_release, --}; -+DEFINE_DRM_GEM_FOPS(rockchip_drm_driver_fops); - - static const struct drm_driver rockchip_drm_driver = { - .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, -@@ -217,7 +208,7 @@ static const struct drm_driver rockchip_drm_driver = { - .prime_handle_to_fd = drm_gem_prime_handle_to_fd, - .prime_fd_to_handle = drm_gem_prime_fd_to_handle, - .gem_prime_import_sg_table = rockchip_gem_prime_import_sg_table, -- .gem_prime_mmap = rockchip_gem_mmap_buf, -+ .gem_prime_mmap = drm_gem_prime_mmap, - .fops = &rockchip_drm_driver_fops, - .name = DRIVER_NAME, - .desc = DRIVER_DESC, -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c -index 2fdc455c4ad7..d8418dd39d0e 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c -@@ -7,6 +7,7 @@ - #include - #include - #include -+#include - #include - - #include "rockchip_drm_drv.h" -@@ -24,7 +25,7 @@ static int rockchip_fbdev_mmap(struct fb_info *info, - struct drm_fb_helper *helper = info->par; - struct rockchip_drm_private *private = to_drm_private(helper); - -- return rockchip_gem_mmap_buf(private->fbdev_bo, vma); -+ return drm_gem_prime_mmap(private->fbdev_bo, vma); - } - - static const struct fb_ops rockchip_drm_fbdev_ops = { -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c -index 7971f57436dd..63eb73b624aa 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c -@@ -240,12 +240,22 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj, - int ret; - struct rockchip_gem_object *rk_obj = to_rockchip_obj(obj); - -+ /* -+ * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the -+ * whole buffer from the start. -+ */ -+ vma->vm_pgoff = 0; -+ - /* - * We allocated a struct page table for rk_obj, so clear - * VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap(). - */ -+ vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP; - vma->vm_flags &= ~VM_PFNMAP; - -+ vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); -+ vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); -+ - if (rk_obj->pages) - ret = rockchip_drm_gem_object_mmap_iommu(obj, vma); - else -@@ -257,39 +267,6 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj, - return ret; - } - --int rockchip_gem_mmap_buf(struct drm_gem_object *obj, -- struct vm_area_struct *vma) --{ -- int ret; -- -- ret = drm_gem_mmap_obj(obj, obj->size, vma); -- if (ret) -- return ret; -- -- return rockchip_drm_gem_object_mmap(obj, vma); --} -- --/* drm driver mmap file operations */ --int rockchip_gem_mmap(struct file *filp, struct vm_area_struct *vma) --{ -- struct drm_gem_object *obj; -- int ret; -- -- ret = drm_gem_mmap(filp, vma); -- if (ret) -- return ret; -- -- /* -- * Set vm_pgoff (used as a fake buffer offset by DRM) to 0 and map the -- * whole buffer from the start. -- */ -- vma->vm_pgoff = 0; -- -- obj = vma->vm_private_data; -- -- return rockchip_drm_gem_object_mmap(obj, vma); --} -- - static void rockchip_gem_release_object(struct rockchip_gem_object *rk_obj) - { - drm_gem_object_release(&rk_obj->base); -@@ -301,6 +278,7 @@ static const struct drm_gem_object_funcs rockchip_gem_object_funcs = { - .get_sg_table = rockchip_gem_prime_get_sg_table, - .vmap = rockchip_gem_prime_vmap, - .vunmap = rockchip_gem_prime_vunmap, -+ .mmap = rockchip_drm_gem_object_mmap, - .vm_ops = &drm_gem_cma_vm_ops, - }; - -diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h -index 5a70a56cd406..47c1861eece0 100644 ---- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h -+++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h -@@ -34,13 +34,6 @@ rockchip_gem_prime_import_sg_table(struct drm_device *dev, - int rockchip_gem_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map); - void rockchip_gem_prime_vunmap(struct drm_gem_object *obj, struct dma_buf_map *map); - --/* drm driver mmap file operations */ --int rockchip_gem_mmap(struct file *filp, struct vm_area_struct *vma); -- --/* mmap a gem object to userspace. */ --int rockchip_gem_mmap_buf(struct drm_gem_object *obj, -- struct vm_area_struct *vma); -- - struct rockchip_gem_object * - rockchip_gem_create_object(struct drm_device *drm, unsigned int size, - bool alloc_kmap); diff --git a/projects/Samsung/linux/linux.arm.conf b/projects/Samsung/linux/linux.arm.conf index 5338d0ee06..b22f5100d5 100644 --- a/projects/Samsung/linux/linux.arm.conf +++ b/projects/Samsung/linux/linux.arm.conf @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 5.16.0-rc8 Kernel Configuration +# Linux/arm 5.17.0-rc3 Kernel Configuration # CONFIG_CC_VERSION_TEXT="armv7ve-libreelec-linux-gnueabihf-gcc-10.3.0 (GCC) 10.3.0" CONFIG_CC_IS_GCC=y @@ -210,7 +210,6 @@ CONFIG_ELF_CORE=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_FUTEX_PI=y -CONFIG_HAVE_FUTEX_CMPXCHG=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y @@ -673,6 +672,7 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y @@ -806,13 +806,12 @@ CONFIG_CONTIG_ALLOC=y CONFIG_BOUNCE=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -# CONFIG_CLEANCACHE is not set -# CONFIG_FRONTSWAP is not set CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set # CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 +# CONFIG_ZSWAP is not set # CONFIG_ZPOOL is not set # CONFIG_ZSMALLOC is not set CONFIG_GENERIC_EARLY_IOREMAP=y @@ -821,6 +820,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_GUP_TEST is not set CONFIG_KMAP_LOCAL=y CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y +# CONFIG_ANON_VMA_NAME is not set # # Data Access Monitoring @@ -1066,6 +1066,7 @@ CONFIG_HAVE_PCI=y # CONFIG_UEVENT_HELPER is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y @@ -1260,7 +1261,6 @@ CONFIG_SCSI_LOWLEVEL=y CONFIG_ISCSI_TCP=y CONFIG_ISCSI_BOOT_SYSFS=y # CONFIG_SCSI_UFSHCD is not set -# CONFIG_SCSI_UFS_HWMON is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_DH is not set # end of SCSI device support @@ -1334,6 +1334,7 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_CORTINA is not set # CONFIG_DM9000 is not set # CONFIG_DNET is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set # CONFIG_NET_VENDOR_EZCHIP is not set # CONFIG_NET_VENDOR_FARADAY is not set # CONFIG_NET_VENDOR_GOOGLE is not set @@ -1362,6 +1363,7 @@ CONFIG_ETHERNET=y # CONFIG_NET_VENDOR_SOCIONEXT is not set # CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set # CONFIG_NET_VENDOR_XILINX is not set @@ -1931,7 +1933,6 @@ CONFIG_I2C_GPIO=y # CONFIG_I2C_OCORES is not set # CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_RK3X is not set -CONFIG_HAVE_S3C2410_I2C=y CONFIG_I2C_S3C2410=y # CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_XILINX is not set @@ -2021,11 +2022,11 @@ CONFIG_PINMUX=y CONFIG_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set # CONFIG_PINCTRL_MCP23S08 is not set -# CONFIG_PINCTRL_SINGLE is not set -# CONFIG_PINCTRL_SX150X is not set -# CONFIG_PINCTRL_STMFX is not set -# CONFIG_PINCTRL_OCELOT is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_SX150X is not set # # Renesas pinctrl drivers @@ -2108,6 +2109,7 @@ CONFIG_GPIO_WM8994=y # # CONFIG_GPIO_AGGREGATOR is not set # CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_SIM is not set # end of Virtual GPIO drivers # CONFIG_W1 is not set @@ -2150,6 +2152,7 @@ CONFIG_BATTERY_MAX17042=y CONFIG_CHARGER_MAX14577=y # CONFIG_CHARGER_DETECTOR_MAX14656 is not set CONFIG_CHARGER_MAX77693=y +# CONFIG_CHARGER_MAX77976 is not set CONFIG_CHARGER_MAX8997=y CONFIG_CHARGER_MAX8998=y # CONFIG_CHARGER_BQ2415X is not set @@ -2272,6 +2275,7 @@ CONFIG_SENSORS_NTC_THERMISTOR=y # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set @@ -2300,6 +2304,7 @@ CONFIG_SENSORS_PWM_FAN=y # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_INA209 is not set CONFIG_SENSORS_INA2XX=y +# CONFIG_SENSORS_INA238 is not set # CONFIG_SENSORS_INA3221 is not set # CONFIG_SENSORS_TC74 is not set # CONFIG_SENSORS_THMC50 is not set @@ -2499,7 +2504,6 @@ CONFIG_MFD_TPS65090=y # CONFIG_MFD_WM8350_I2C is not set CONFIG_MFD_WM8994=y # CONFIG_MFD_ROHM_BD718XX is not set -# CONFIG_MFD_ROHM_BD70528 is not set # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD957XMUF is not set # CONFIG_MFD_STPMIC1 is not set @@ -2542,6 +2546,7 @@ CONFIG_REGULATOR_MAX8952=y # CONFIG_REGULATOR_MAX8973 is not set CONFIG_REGULATOR_MAX8997=y CONFIG_REGULATOR_MAX8998=y +# CONFIG_REGULATOR_MAX20086 is not set CONFIG_REGULATOR_MAX77686=y CONFIG_REGULATOR_MAX77693=y CONFIG_REGULATOR_MAX77802=y @@ -2847,6 +2852,7 @@ CONFIG_VIDEOBUF2_VMALLOC=m # CONFIG_VIDEO_OV6650 is not set # CONFIG_VIDEO_OV5670 is not set # CONFIG_VIDEO_OV5675 is not set +# CONFIG_VIDEO_OV5693 is not set # CONFIG_VIDEO_OV5695 is not set # CONFIG_VIDEO_OV7251 is not set # CONFIG_VIDEO_OV772X is not set @@ -2980,7 +2986,8 @@ CONFIG_DRM_EXYNOS_HDMI=y # CONFIG_DRM_UDL is not set # CONFIG_DRM_ARMADA is not set # CONFIG_DRM_RCAR_DW_HDMI is not set -# CONFIG_DRM_RCAR_LVDS is not set +# CONFIG_DRM_RCAR_USE_LVDS is not set +# CONFIG_DRM_RCAR_MIPI_DSI is not set # CONFIG_DRM_OMAP is not set # CONFIG_DRM_TILCDC is not set # CONFIG_DRM_FSL_DCU is not set @@ -2993,6 +3000,7 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_ABT_Y030XX067A is not set # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set +# CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set # CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set # CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set # CONFIG_DRM_PANEL_DSI_CM is not set @@ -3007,6 +3015,7 @@ CONFIG_DRM_PANEL_EDP=y # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set # CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set # CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +# CONFIG_DRM_PANEL_JDI_R63452 is not set # CONFIG_DRM_PANEL_KHADAS_TS050 is not set # CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set @@ -3016,6 +3025,7 @@ CONFIG_DRM_PANEL_SAMSUNG_LD9040=y # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set # CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set # CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -3047,6 +3057,7 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=y # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set # CONFIG_DRM_PANEL_SONY_ACX424AKP is not set # CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set # CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set @@ -3106,6 +3117,7 @@ CONFIG_DRM_ANALOGIX_DP=y # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_SIMPLEDRM is not set # CONFIG_TINYDRM_HX8357D is not set +# CONFIG_TINYDRM_ILI9163 is not set # CONFIG_TINYDRM_ILI9225 is not set # CONFIG_TINYDRM_ILI9341 is not set # CONFIG_TINYDRM_ILI9486 is not set @@ -3122,6 +3134,7 @@ CONFIG_DRM_ANALOGIX_DP=y # CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_NOMODESET=y # # Frame buffer Devices @@ -3259,6 +3272,7 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y # CONFIG_SND_SOC_ADI is not set # CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_AMD_ACP_CONFIG is not set # CONFIG_SND_ATMEL_SOC is not set # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set # CONFIG_SND_DESIGNWARE_I2S is not set @@ -3324,6 +3338,7 @@ CONFIG_SND_SOC_WM_HUBS=y # CONFIG_SND_SOC_ADAU7118_I2C is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set @@ -3420,6 +3435,7 @@ CONFIG_SND_SOC_RT5631=y # CONFIG_SND_SOC_TDA7419 is not set # CONFIG_SND_SOC_TFA9879 is not set # CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320ADC3XXX is not set # CONFIG_SND_SOC_TLV320AIC23_I2C is not set # CONFIG_SND_SOC_TLV320AIC23_SPI is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set @@ -3538,6 +3554,7 @@ CONFIG_HID_KENSINGTON=y # CONFIG_HID_LCPOWER is not set # CONFIG_HID_LED is not set # CONFIG_HID_LENOVO is not set +# CONFIG_HID_LETSKETCH is not set CONFIG_HID_LOGITECH=y # CONFIG_HID_LOGITECH_HIDPP is not set # CONFIG_LOGITECH_FF is not set @@ -3940,6 +3957,10 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set # CONFIG_LEDS_TRIGGER_TTY is not set + +# +# Simple LED drivers +# # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y @@ -4050,7 +4071,6 @@ CONFIG_RTC_I2C_AND_SPI=y # # on-CPU RTC drivers # -CONFIG_HAVE_S3C_RTC=y CONFIG_RTC_DRV_S3C=y # CONFIG_RTC_DRV_PL030 is not set # CONFIG_RTC_DRV_PL031 is not set @@ -4227,6 +4247,7 @@ CONFIG_COMMON_CLK_MAX77686=y # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_LAN966X is not set CONFIG_COMMON_CLK_S2MPS11=y # CONFIG_COMMON_CLK_AXI_CLKGEN is not set # CONFIG_COMMON_CLK_PWM is not set @@ -4327,6 +4348,7 @@ CONFIG_EXYNOS_IOMMU=y CONFIG_SOC_SAMSUNG=y CONFIG_EXYNOS_ASV_ARM=y CONFIG_EXYNOS_CHIPID=y +# CONFIG_EXYNOS_USI is not set CONFIG_EXYNOS_PMU=y CONFIG_EXYNOS_PMU_ARM_DRIVERS=y CONFIG_EXYNOS_PM_DOMAINS=y @@ -4500,6 +4522,12 @@ CONFIG_EXYNOS_ADC=y # CONFIG_XILINX_XADC is not set # end of Analog to digital converters +# +# Analog to digital and digital to analog converters +# +# CONFIG_AD74413R is not set +# end of Analog to digital and digital to analog converters + # # Analog Front Ends # @@ -4555,6 +4583,7 @@ CONFIG_EXYNOS_ADC=y # # Digital to analog converters # +# CONFIG_AD3552R is not set # CONFIG_AD5064 is not set # CONFIG_AD5360 is not set # CONFIG_AD5380 is not set @@ -4574,6 +4603,7 @@ CONFIG_EXYNOS_ADC=y # CONFIG_AD5766 is not set # CONFIG_AD5770R is not set # CONFIG_AD5791 is not set +# CONFIG_AD7293 is not set # CONFIG_AD7303 is not set # CONFIG_AD8801 is not set # CONFIG_DPOT_DAC is not set @@ -4597,6 +4627,11 @@ CONFIG_EXYNOS_ADC=y # # end of IIO dummy driver +# +# Filters +# +# end of Filters + # # Frequency Synthesizers DDS/PLL # @@ -4612,6 +4647,7 @@ CONFIG_EXYNOS_ADC=y # # CONFIG_ADF4350 is not set # CONFIG_ADF4371 is not set +# CONFIG_ADMV1013 is not set # CONFIG_ADRF6780 is not set # end of Phase-Locked Loop (PLL) frequency synthesizers # end of Frequency Synthesizers DDS/PLL @@ -4896,8 +4932,10 @@ CONFIG_GENERIC_PHY=y # CONFIG_PHY_CADENCE_SALVO is not set # CONFIG_PHY_FSL_IMX8MQ_USB is not set # CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_FSL_IMX8M_PCIE is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_LAN966X_SERDES is not set # CONFIG_PHY_CPCAP_USB is not set # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set @@ -5402,6 +5440,7 @@ CONFIG_CRYPTO_DRBG_HMAC=y # CONFIG_CRYPTO_DRBG_CTR is not set CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_KDF800108_CTR=y CONFIG_CRYPTO_USER_API=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_SKCIPHER=y @@ -5411,25 +5450,6 @@ CONFIG_CRYPTO_USER_API_AEAD=m CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y # CONFIG_CRYPTO_STATS is not set CONFIG_CRYPTO_HASH_INFO=y - -# -# Crypto library routines -# -CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=m -CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y -CONFIG_CRYPTO_LIB_BLAKE2S=y -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y -CONFIG_CRYPTO_LIB_CHACHA=y -CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=y -CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y -CONFIG_CRYPTO_LIB_CURVE25519=y -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y -CONFIG_CRYPTO_LIB_POLY1305=y -CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y -CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_DEV_EXYNOS_RNG=y CONFIG_CRYPTO_DEV_S5P=y @@ -5475,6 +5495,26 @@ CONFIG_CORDIC=m CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CHACHA=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=y +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y +CONFIG_CRYPTO_LIB_CURVE25519=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + CONFIG_CRC_CCITT=y CONFIG_CRC16=y # CONFIG_CRC_T10DIF is not set @@ -5640,6 +5680,13 @@ CONFIG_HAVE_KCSAN_COMPILER=y CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# end of Networking Debugging + # # Memory Debugging # @@ -5668,6 +5715,8 @@ CONFIG_HAVE_ARCH_KASAN=y CONFIG_CC_HAS_KASAN_GENERIC=y CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y # CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set # end of Memory Debugging # CONFIG_DEBUG_SHIRQ is not set @@ -5765,6 +5814,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_BUILDTIME_MCOUNT_SORT=y CONFIG_TRACE_CLOCK=y CONFIG_RING_BUFFER=y CONFIG_EVENT_TRACING=y @@ -5834,6 +5884,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_DIV64 is not set # CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_TEST_REF_TRACKER is not set # CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set # CONFIG_INTERVAL_TREE_TEST is not set @@ -5851,7 +5902,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_XARRAY is not set # CONFIG_TEST_OVERFLOW is not set # CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_HASH is not set +# CONFIG_TEST_SIPHASH is not set # CONFIG_TEST_IDA is not set # CONFIG_TEST_LKM is not set # CONFIG_TEST_BITOPS is not set